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authorJason Reiss <jreiss@multitech.com>2020-11-03 12:45:39 -0600
committerJohn Klug <john.klug@multitech.com>2020-11-10 18:14:32 -0600
commit3831438ec7fbd3bbd98062cf547fc04529bb10d5 (patch)
tree091546f969b5a3faddfb5df4983a206e2bad14f1 /recipes-connectivity/lora/lora-packet-forwarder-geolocation
parent49cbb0e63d01d45d5c68245e77a39e5ffcfb85bd (diff)
downloadmeta-mlinux-3831438ec7fbd3bbd98062cf547fc04529bb10d5.tar.gz
meta-mlinux-3831438ec7fbd3bbd98062cf547fc04529bb10d5.tar.bz2
meta-mlinux-3831438ec7fbd3bbd98062cf547fc04529bb10d5.zip
lora: update v2.1 power tables
Diffstat (limited to 'recipes-connectivity/lora/lora-packet-forwarder-geolocation')
-rw-r--r--recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_single_antenna_16ch_US91532
-rw-r--r--recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_single_antenna_64ch_US91532
-rw-r--r--recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_single_antenna_full_duplex_64ch_US91532
3 files changed, 48 insertions, 48 deletions
diff --git a/recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_single_antenna_16ch_US915 b/recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_single_antenna_16ch_US915
index d6f1123..81745a2 100644
--- a/recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_single_antenna_16ch_US915
+++ b/recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_single_antenna_16ch_US915
@@ -17,22 +17,22 @@
"tx_freq_min": 923300000,
"tx_freq_max": 927500000,
"tx_lut":[
- { "rf_power": 9, "fpga_dig_gain": 5, "ad9361_atten": 104, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -23, "ad9361_tcomp_coeff_b": 3177 },
- { "rf_power": 11, "fpga_dig_gain": 5, "ad9361_atten": 96, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -21, "ad9361_tcomp_coeff_b": 2888 },
- { "rf_power": 12, "fpga_dig_gain": 5, "ad9361_atten": 93, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -20, "ad9361_tcomp_coeff_b": 2683 },
- { "rf_power": 13, "fpga_dig_gain": 5, "ad9361_atten": 88, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -20, "ad9361_tcomp_coeff_b": 2530 },
- { "rf_power": 14, "fpga_dig_gain": 5, "ad9361_atten": 84, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -19, "ad9361_tcomp_coeff_b": 2367 },
- { "rf_power": 16, "fpga_dig_gain": 5, "ad9361_atten": 75, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -18, "ad9361_tcomp_coeff_b": 1943 },
- { "rf_power": 18, "fpga_dig_gain": 5, "ad9361_atten": 67, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -16, "ad9361_tcomp_coeff_b": 1537 },
- { "rf_power": 20, "fpga_dig_gain": 5, "ad9361_atten": 59, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -15, "ad9361_tcomp_coeff_b": 1135 },
- { "rf_power": 22, "fpga_dig_gain": 5, "ad9361_atten": 51, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -13, "ad9361_tcomp_coeff_b": 714 },
- { "rf_power": 24, "fpga_dig_gain": 5, "ad9361_atten": 42, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -11, "ad9361_tcomp_coeff_b": 262 },
- { "rf_power": 25, "fpga_dig_gain": 5, "ad9361_atten": 38, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -9, "ad9361_tcomp_coeff_b": -6 },
- { "rf_power": 26, "fpga_dig_gain": 5, "ad9361_atten": 33, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -8, "ad9361_tcomp_coeff_b": -193 },
- { "rf_power": 27, "fpga_dig_gain": 5, "ad9361_atten": 29, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -7, "ad9361_tcomp_coeff_b": -356 },
- { "rf_power": 28, "fpga_dig_gain": 5, "ad9361_atten": 24, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -6, "ad9361_tcomp_coeff_b": -470 },
- { "rf_power": 29, "fpga_dig_gain": 5, "ad9361_atten": 18, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -6, "ad9361_tcomp_coeff_b": -534 },
- { "rf_power": 30, "fpga_dig_gain": 5, "ad9361_atten": 11, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -4, "ad9361_tcomp_coeff_b": -589 }]
+ { "rf_power": 9, "fpga_dig_gain": 5, "ad9361_atten": 103, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -17, "ad9361_tcomp_coeff_b": 477 },
+ { "rf_power": 11, "fpga_dig_gain": 5, "ad9361_atten": 99, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -17, "ad9361_tcomp_coeff_b": 477 },
+ { "rf_power": 12, "fpga_dig_gain": 5, "ad9361_atten": 95, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -17, "ad9361_tcomp_coeff_b": 477 },
+ { "rf_power": 13, "fpga_dig_gain": 5, "ad9361_atten": 91, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -3, "ad9361_tcomp_coeff_b": -508 },
+ { "rf_power": 14, "fpga_dig_gain": 5, "ad9361_atten": 87, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -3, "ad9361_tcomp_coeff_b": -508 },
+ { "rf_power": 16, "fpga_dig_gain": 5, "ad9361_atten": 79, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -2, "ad9361_tcomp_coeff_b": -610 },
+ { "rf_power": 18, "fpga_dig_gain": 5, "ad9361_atten": 71, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -1, "ad9361_tcomp_coeff_b": -1247 },
+ { "rf_power": 20, "fpga_dig_gain": 5, "ad9361_atten": 63, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1417 },
+ { "rf_power": 22, "fpga_dig_gain": 5, "ad9361_atten": 55, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1417 },
+ { "rf_power": 24, "fpga_dig_gain": 5, "ad9361_atten": 47, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1555 },
+ { "rf_power": 25, "fpga_dig_gain": 5, "ad9361_atten": 43, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1785 },
+ { "rf_power": 26, "fpga_dig_gain": 5, "ad9361_atten": 39, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1785 },
+ { "rf_power": 27, "fpga_dig_gain": 5, "ad9361_atten": 35, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1785 },
+ { "rf_power": 28, "fpga_dig_gain": 5, "ad9361_atten": 30, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -1, "ad9361_tcomp_coeff_b": -1755 },
+ { "rf_power": 29, "fpga_dig_gain": 5, "ad9361_atten": 26, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -1, "ad9361_tcomp_coeff_b": -1755 },
+ { "rf_power": 30, "fpga_dig_gain": 5, "ad9361_atten": 22, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -3, "ad9361_tcomp_coeff_b": -1183 }]
}],
"SX1301_conf":[
{
diff --git a/recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_single_antenna_64ch_US915 b/recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_single_antenna_64ch_US915
index 9133313..61774f2 100644
--- a/recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_single_antenna_64ch_US915
+++ b/recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_single_antenna_64ch_US915
@@ -17,22 +17,22 @@
"tx_freq_min": 923300000,
"tx_freq_max": 927500000,
"tx_lut":[
- { "rf_power": 9, "fpga_dig_gain": 5, "ad9361_atten": 104, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -23, "ad9361_tcomp_coeff_b": 3177 },
- { "rf_power": 11, "fpga_dig_gain": 5, "ad9361_atten": 96, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -21, "ad9361_tcomp_coeff_b": 2888 },
- { "rf_power": 12, "fpga_dig_gain": 5, "ad9361_atten": 93, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -20, "ad9361_tcomp_coeff_b": 2683 },
- { "rf_power": 13, "fpga_dig_gain": 5, "ad9361_atten": 88, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -20, "ad9361_tcomp_coeff_b": 2530 },
- { "rf_power": 14, "fpga_dig_gain": 5, "ad9361_atten": 84, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -19, "ad9361_tcomp_coeff_b": 2367 },
- { "rf_power": 16, "fpga_dig_gain": 5, "ad9361_atten": 75, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -18, "ad9361_tcomp_coeff_b": 1943 },
- { "rf_power": 18, "fpga_dig_gain": 5, "ad9361_atten": 67, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -16, "ad9361_tcomp_coeff_b": 1537 },
- { "rf_power": 20, "fpga_dig_gain": 5, "ad9361_atten": 59, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -15, "ad9361_tcomp_coeff_b": 1135 },
- { "rf_power": 22, "fpga_dig_gain": 5, "ad9361_atten": 51, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -13, "ad9361_tcomp_coeff_b": 714 },
- { "rf_power": 24, "fpga_dig_gain": 5, "ad9361_atten": 42, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -11, "ad9361_tcomp_coeff_b": 262 },
- { "rf_power": 25, "fpga_dig_gain": 5, "ad9361_atten": 38, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -9, "ad9361_tcomp_coeff_b": -6 },
- { "rf_power": 26, "fpga_dig_gain": 5, "ad9361_atten": 33, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -8, "ad9361_tcomp_coeff_b": -193 },
- { "rf_power": 27, "fpga_dig_gain": 5, "ad9361_atten": 29, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -7, "ad9361_tcomp_coeff_b": -356 },
- { "rf_power": 28, "fpga_dig_gain": 5, "ad9361_atten": 24, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -6, "ad9361_tcomp_coeff_b": -470 },
- { "rf_power": 29, "fpga_dig_gain": 5, "ad9361_atten": 18, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -6, "ad9361_tcomp_coeff_b": -534 },
- { "rf_power": 30, "fpga_dig_gain": 5, "ad9361_atten": 11, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -4, "ad9361_tcomp_coeff_b": -589 }]
+ { "rf_power": 9, "fpga_dig_gain": 5, "ad9361_atten": 103, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -17, "ad9361_tcomp_coeff_b": 477 },
+ { "rf_power": 11, "fpga_dig_gain": 5, "ad9361_atten": 99, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -17, "ad9361_tcomp_coeff_b": 477 },
+ { "rf_power": 12, "fpga_dig_gain": 5, "ad9361_atten": 95, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -17, "ad9361_tcomp_coeff_b": 477 },
+ { "rf_power": 13, "fpga_dig_gain": 5, "ad9361_atten": 91, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -3, "ad9361_tcomp_coeff_b": -508 },
+ { "rf_power": 14, "fpga_dig_gain": 5, "ad9361_atten": 87, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -3, "ad9361_tcomp_coeff_b": -508 },
+ { "rf_power": 16, "fpga_dig_gain": 5, "ad9361_atten": 79, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -2, "ad9361_tcomp_coeff_b": -610 },
+ { "rf_power": 18, "fpga_dig_gain": 5, "ad9361_atten": 71, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -1, "ad9361_tcomp_coeff_b": -1247 },
+ { "rf_power": 20, "fpga_dig_gain": 5, "ad9361_atten": 63, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1417 },
+ { "rf_power": 22, "fpga_dig_gain": 5, "ad9361_atten": 55, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1417 },
+ { "rf_power": 24, "fpga_dig_gain": 5, "ad9361_atten": 47, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1555 },
+ { "rf_power": 25, "fpga_dig_gain": 5, "ad9361_atten": 43, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1785 },
+ { "rf_power": 26, "fpga_dig_gain": 5, "ad9361_atten": 39, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1785 },
+ { "rf_power": 27, "fpga_dig_gain": 5, "ad9361_atten": 35, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": 0, "ad9361_tcomp_coeff_b": -1785 },
+ { "rf_power": 28, "fpga_dig_gain": 5, "ad9361_atten": 30, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -1, "ad9361_tcomp_coeff_b": -1755 },
+ { "rf_power": 29, "fpga_dig_gain": 5, "ad9361_atten": 26, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -1, "ad9361_tcomp_coeff_b": -1755 },
+ { "rf_power": 30, "fpga_dig_gain": 5, "ad9361_atten": 22, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -3, "ad9361_tcomp_coeff_b": -1183 }]
}],
"SX1301_conf":[
{
diff --git a/recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_single_antenna_full_duplex_64ch_US915 b/recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_single_antenna_full_duplex_64ch_US915
index 0aaf4bf..76e683d 100644
--- a/recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_single_antenna_full_duplex_64ch_US915
+++ b/recipes-connectivity/lora/lora-packet-forwarder-geolocation/global_conf.json.MTAC_LORA_2_1_loc_single_antenna_full_duplex_64ch_US915
@@ -22,22 +22,22 @@
"tx_freq_min": 923300000,
"tx_freq_max": 927500000,
"tx_lut":[
- { "rf_power": 9, "fpga_dig_gain": 5, "ad9361_atten": 104, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -23, "ad9361_tcomp_coeff_b": 3177 },
- { "rf_power": 11, "fpga_dig_gain": 5, "ad9361_atten": 96, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -21, "ad9361_tcomp_coeff_b": 2888 },
- { "rf_power": 12, "fpga_dig_gain": 5, "ad9361_atten": 93, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -20, "ad9361_tcomp_coeff_b": 2683 },
- { "rf_power": 13, "fpga_dig_gain": 5, "ad9361_atten": 88, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -20, "ad9361_tcomp_coeff_b": 2530 },
- { "rf_power": 14, "fpga_dig_gain": 5, "ad9361_atten": 84, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -19, "ad9361_tcomp_coeff_b": 2367 },
- { "rf_power": 16, "fpga_dig_gain": 5, "ad9361_atten": 75, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -18, "ad9361_tcomp_coeff_b": 1943 },
- { "rf_power": 18, "fpga_dig_gain": 5, "ad9361_atten": 67, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -16, "ad9361_tcomp_coeff_b": 1537 },
- { "rf_power": 20, "fpga_dig_gain": 5, "ad9361_atten": 59, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -15, "ad9361_tcomp_coeff_b": 1135 },
- { "rf_power": 22, "fpga_dig_gain": 5, "ad9361_atten": 51, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -13, "ad9361_tcomp_coeff_b": 714 },
- { "rf_power": 24, "fpga_dig_gain": 5, "ad9361_atten": 42, "ad9361_auxdac_vref": 3, "ad9361_auxdac_word": 770, "ad9361_tcomp_coeff_a": -11, "ad9361_tcomp_coeff_b": 262 },
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}],
"SX1301_conf":[
{
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-20 15:38:42 +0000