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| author | Jason Reiss <jreiss@multitech.com> | 2017-04-21 15:08:25 -0500 |
|---|---|---|
| committer | Jason Reiss <jreiss@multitech.com> | 2017-04-21 15:08:25 -0500 |
| commit | 756b541a5722c9e248dc8bef593d34cc2acbd22a (patch) | |
| tree | 973d0a68c445da70705e55ebd6ad27a373a7371b /recipes-connectivity/lora/lora-gateway | |
| parent | a6153fbb5503cac3b93aedca526e86a218e86070 (diff) | |
| download | meta-mlinux-756b541a5722c9e248dc8bef593d34cc2acbd22a.tar.gz meta-mlinux-756b541a5722c9e248dc8bef593d34cc2acbd22a.tar.bz2 meta-mlinux-756b541a5722c9e248dc8bef593d34cc2acbd22a.zip | |
lora: update network server, loragw, and packet-forwarder versions
Diffstat (limited to 'recipes-connectivity/lora/lora-gateway')
| -rw-r--r-- | recipes-connectivity/lora/lora-gateway/lora-gateway-add-fpga-version-28-31-33.patch | 22 | ||||
| -rw-r--r-- | recipes-connectivity/lora/lora-gateway/lora-gateway-v28-skip-IQ-invert.patch | 24 |
2 files changed, 44 insertions, 2 deletions
diff --git a/recipes-connectivity/lora/lora-gateway/lora-gateway-add-fpga-version-28-31-33.patch b/recipes-connectivity/lora/lora-gateway/lora-gateway-add-fpga-version-28-31-33.patch index 1950573..7e73263 100644 --- a/recipes-connectivity/lora/lora-gateway/lora-gateway-add-fpga-version-28-31-33.patch +++ b/recipes-connectivity/lora/lora-gateway/lora-gateway-add-fpga-version-28-31-33.patch @@ -1,5 +1,5 @@ diff --git a/libloragw/src/loragw_reg.c b/libloragw/src/loragw_reg.c -index 7e396bc..e71e695 100644 +index 7e396bc..478f46a 100644 --- a/libloragw/src/loragw_reg.c +++ b/libloragw/src/loragw_reg.c @@ -48,7 +48,7 @@ Maintainer: Sylvain Miermont @@ -9,4 +9,22 @@ index 7e396bc..e71e695 100644 -const uint8_t FPGA_VERSION[] = { 31, 33 }; /* several versions could be supported */ +const uint8_t FPGA_VERSION[] = { 28, 31, 33 }; /* several versions could be supported */ - /*
\ No newline at end of file + /* + auto generated register mapping for C code : 11-Jul-2013 13:20:40 +@@ -415,6 +415,16 @@ bool check_fpga_version(uint8_t version) { + return false; + } + ++uint8_t read_fpga_version() { ++ uint8_t u = 0; ++ uint8_t spi_stat = lgw_spi_r(lgw_spi_target, LGW_SPI_MUX_MODE1, LGW_SPI_MUX_TARGET_FPGA, loregs[LGW_VERSION].addr, &u); ++ if (spi_stat != LGW_SPI_SUCCESS) { ++ DEBUG_MSG("ERROR READING VERSION REGISTER\n"); ++ return LGW_REG_ERROR; ++ } ++ return u; ++} ++ + /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ + + int reg_w_align32(void *spi_target, uint8_t spi_mux_mode, uint8_t spi_mux_target, struct lgw_reg_s r, int32_t reg_value) { diff --git a/recipes-connectivity/lora/lora-gateway/lora-gateway-v28-skip-IQ-invert.patch b/recipes-connectivity/lora/lora-gateway/lora-gateway-v28-skip-IQ-invert.patch new file mode 100644 index 0000000..25065df --- /dev/null +++ b/recipes-connectivity/lora/lora-gateway/lora-gateway-v28-skip-IQ-invert.patch @@ -0,0 +1,24 @@ +diff --git a/libloragw/src/loragw_fpga.c b/libloragw/src/loragw_fpga.c +index fa83a2a..7e667e3 100644 +--- a/libloragw/src/loragw_fpga.c ++++ b/libloragw/src/loragw_fpga.c +@@ -144,11 +144,14 @@ int lgw_fpga_configure(uint32_t tx_notch_freq) { + return LGW_REG_ERROR; + } + +- /* Required for Semtech AP2 reference design */ +- x = lgw_fpga_reg_w(LGW_FPGA_CTRL_INVERT_IQ, 1); +- if (x != LGW_REG_SUCCESS) { +- DEBUG_MSG("ERROR: Failed to configure FPGA polarity\n"); +- return LGW_REG_ERROR; ++ ++ if (read_fpga_version() > 28) { ++ /* Required for Semtech AP2 reference design and AP1.5 > v28 */ ++ x = lgw_fpga_reg_w(LGW_FPGA_CTRL_INVERT_IQ, 1); ++ if (x != LGW_REG_SUCCESS) { ++ DEBUG_MSG("ERROR: Failed to configure FPGA polarity\n"); ++ return LGW_REG_ERROR; ++ } + } + + /* Configure TX notch filter */ |