From 673abd92f999829bdd67d0273c43570a62123a63 Mon Sep 17 00:00:00 2001 From: Richard Purdie Date: Fri, 18 Feb 2011 15:32:57 +0000 Subject: conf/machine: Drop older machines with no recent updates These are all moving to meta-extras. Ideally in the future machines such as these will be maintained to topic specific layers as we move to a more layer oriented model. If this causes a problem for anyone please discuss it on the mailing list. Signed-off-by: Richard Purdie --- .../0001-ARM-OMAP-SmartReflex-driver.patch | 1002 ------------- ...P-Add-basic-support-for-OMAP34xx-in-McBSP.patch | 55 - .../omap3evm/0001-omap3-cpuidle.patch | 450 ------ ...e-add-a-platform-device-to-hook-up-the-GP.patch | 69 - .../0002-ARM-OMAP-SmartReflex-driver.patch | 278 ---- .../omap3evm/0002-omap3-cpuidle.patch | 88 -- .../0003-ARM-OMAP-SmartReflex-driver.patch | 1001 ------------- .../linux/linux-omap2-git/omap3evm/defconfig | 1567 -------------------- .../omap3evm/no-empty-flash-warnings.patch | 15 - .../linux-omap2-git/omap3evm/no-harry-potter.diff | 11 - 10 files changed, 4536 deletions(-) delete mode 100644 meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-ARM-OMAP-SmartReflex-driver.patch delete mode 100644 meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch delete mode 100644 meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3-cpuidle.patch delete mode 100644 meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch delete mode 100644 meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-ARM-OMAP-SmartReflex-driver.patch delete mode 100644 meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-omap3-cpuidle.patch delete mode 100644 meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0003-ARM-OMAP-SmartReflex-driver.patch delete mode 100644 meta/recipes-kernel/linux/linux-omap2-git/omap3evm/defconfig delete mode 100644 meta/recipes-kernel/linux/linux-omap2-git/omap3evm/no-empty-flash-warnings.patch delete mode 100644 meta/recipes-kernel/linux/linux-omap2-git/omap3evm/no-harry-potter.diff (limited to 'meta/recipes-kernel/linux/linux-omap2-git/omap3evm') diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-ARM-OMAP-SmartReflex-driver.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-ARM-OMAP-SmartReflex-driver.patch deleted file mode 100644 index 550a4f58be..0000000000 --- a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-ARM-OMAP-SmartReflex-driver.patch +++ /dev/null @@ -1,1002 +0,0 @@ -From: Kalle Jokiniemi -To: linux-omap@vger.kernel.org -Cc: Kalle Jokiniemi -Subject: [PATCH 1/3] ARM: OMAP: SmartReflex driver, reference source and header files -Date: Mon, 2 Jun 2008 14:30:12 +0300 - -The following patch set integrates TI's SmartReflex driver. SmartReflex is a -module that adjusts OMAP3 VDD1 and VDD2 operating voltages around the nominal -values of current operating point depending on silicon characteristics and -operating conditions. - -The driver creates two sysfs entries into /sys/power/ named "sr_vdd1_autocomp" -and "sr_vdd2_autocomp" which can be used to activate SmartReflex modules 1 and -2. - -Use the following commands to enable SmartReflex: - -echo -n 1 > /sys/power/sr_vdd1_autocomp -echo -n 1 > /sys/power/sr_vdd2_autocomp - -To disable: - -echo -n 0 > /sys/power/sr_vdd1_autocomp -echo -n 0 > /sys/power/sr_vdd2_autocomp - -This particular patch adds the TI reference source and header files for -SmartReflex. Only modifications include minor styling to pass checkpatch.pl -test. - -Signed-off-by: Kalle Jokiniemi ---- - arch/arm/mach-omap2/smartreflex.c | 815 +++++++++++++++++++++++++++++++++++++ - arch/arm/mach-omap2/smartreflex.h | 136 ++++++ - 2 files changed, 951 insertions(+), 0 deletions(-) - create mode 100644 arch/arm/mach-omap2/smartreflex.c - create mode 100644 arch/arm/mach-omap2/smartreflex.h - -diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c -new file mode 100644 -index 0000000..dae7460 ---- /dev/null -+++ b/arch/arm/mach-omap2/smartreflex.c -@@ -0,0 +1,815 @@ -+/* -+ * linux/arch/arm/mach-omap3/smartreflex.c -+ * -+ * OMAP34XX SmartReflex Voltage Control -+ * -+ * Copyright (C) 2007 Texas Instruments, Inc. -+ * Lesly A M -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include "prcm-regs.h" -+#include "smartreflex.h" -+ -+ -+/* #define DEBUG_SR 1 */ -+#ifdef DEBUG_SR -+# define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__ ,\ -+ ## args) -+#else -+# define DPRINTK(fmt, args...) -+#endif -+ -+struct omap_sr{ -+ int srid; -+ int is_sr_reset; -+ int is_autocomp_active; -+ struct clk *fck; -+ u32 req_opp_no; -+ u32 opp1_nvalue, opp2_nvalue, opp3_nvalue, opp4_nvalue, opp5_nvalue; -+ u32 senp_mod, senn_mod; -+ u32 srbase_addr; -+ u32 vpbase_addr; -+}; -+ -+static struct omap_sr sr1 = { -+ .srid = SR1, -+ .is_sr_reset = 1, -+ .is_autocomp_active = 0, -+ .srbase_addr = OMAP34XX_SR1_BASE, -+}; -+ -+static struct omap_sr sr2 = { -+ .srid = SR2, -+ .is_sr_reset = 1, -+ .is_autocomp_active = 0, -+ .srbase_addr = OMAP34XX_SR2_BASE, -+}; -+ -+static inline void sr_write_reg(struct omap_sr *sr, int offset, u32 value) -+{ -+ omap_writel(value, sr->srbase_addr + offset); -+} -+ -+static inline void sr_modify_reg(struct omap_sr *sr, int offset, u32 mask, -+ u32 value) -+{ -+ u32 reg_val; -+ -+ reg_val = omap_readl(sr->srbase_addr + offset); -+ reg_val &= ~mask; -+ reg_val |= value; -+ -+ omap_writel(reg_val, sr->srbase_addr + offset); -+} -+ -+static inline u32 sr_read_reg(struct omap_sr *sr, int offset) -+{ -+ return omap_readl(sr->srbase_addr + offset); -+} -+ -+ -+#ifndef USE_EFUSE_VALUES -+static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen) -+{ -+ u32 gn, rn, mul; -+ -+ for (gn = 0; gn < GAIN_MAXLIMIT; gn++) { -+ mul = 1 << (gn + 8); -+ rn = mul / sensor; -+ if (rn < R_MAXLIMIT) { -+ *sengain = gn; -+ *rnsen = rn; -+ } -+ } -+} -+#endif -+ -+static int sr_clk_enable(struct omap_sr *sr) -+{ -+ if (clk_enable(sr->fck) != 0) { -+ printk(KERN_ERR "Could not enable sr%d_fck\n", sr->srid); -+ goto clk_enable_err; -+ } -+ -+ /* set fclk- active , iclk- idle */ -+ sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK, -+ SR_CLKACTIVITY_IOFF_FON); -+ -+ return 0; -+ -+clk_enable_err: -+ return -1; -+} -+ -+static int sr_clk_disable(struct omap_sr *sr) -+{ -+ /* set fclk, iclk- idle */ -+ sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK, -+ SR_CLKACTIVITY_IOFF_FOFF); -+ -+ clk_disable(sr->fck); -+ sr->is_sr_reset = 1; -+ -+ return 0; -+} -+ -+static void sr_set_nvalues(struct omap_sr *sr) -+{ -+#ifdef USE_EFUSE_VALUES -+ u32 n1, n2; -+#else -+ u32 senpval, sennval; -+ u32 senpgain, senngain; -+ u32 rnsenp, rnsenn; -+#endif -+ -+ if (sr->srid == SR1) { -+#ifdef USE_EFUSE_VALUES -+ /* Read values for VDD1 from EFUSE */ -+#else -+ /* since E-Fuse Values are not available, calculating the -+ * reciprocal of the SenN and SenP values for SR1 -+ */ -+ sr->senp_mod = 0x03; /* SenN-M5 enabled */ -+ sr->senn_mod = 0x03; -+ -+ /* for OPP5 */ -+ senpval = 0x848 + 0x330; -+ sennval = 0xacd + 0x330; -+ -+ cal_reciprocal(senpval, &senpgain, &rnsenp); -+ cal_reciprocal(sennval, &senngain, &rnsenn); -+ -+ sr->opp5_nvalue = -+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | -+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | -+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | -+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); -+ -+ /* for OPP4 */ -+ senpval = 0x727 + 0x2a0; -+ sennval = 0x964 + 0x2a0; -+ -+ cal_reciprocal(senpval, &senpgain, &rnsenp); -+ cal_reciprocal(sennval, &senngain, &rnsenn); -+ -+ sr->opp4_nvalue = -+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | -+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | -+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | -+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); -+ -+ /* for OPP3 */ -+ senpval = 0x655 + 0x200; -+ sennval = 0x85b + 0x200; -+ -+ cal_reciprocal(senpval, &senpgain, &rnsenp); -+ cal_reciprocal(sennval, &senngain, &rnsenn); -+ -+ sr->opp3_nvalue = -+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | -+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | -+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | -+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); -+ -+ /* for OPP2 */ -+ senpval = 0x3be + 0x1a0; -+ sennval = 0x506 + 0x1a0; -+ -+ cal_reciprocal(senpval, &senpgain, &rnsenp); -+ cal_reciprocal(sennval, &senngain, &rnsenn); -+ -+ sr->opp2_nvalue = -+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | -+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | -+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | -+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); -+ -+ /* for OPP1 */ -+ senpval = 0x28c + 0x100; -+ sennval = 0x373 + 0x100; -+ -+ cal_reciprocal(senpval, &senpgain, &rnsenp); -+ cal_reciprocal(sennval, &senngain, &rnsenn); -+ -+ sr->opp1_nvalue = -+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | -+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | -+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | -+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); -+ -+ sr_clk_enable(sr); -+ sr_write_reg(sr, NVALUERECIPROCAL, sr->opp3_nvalue); -+ sr_clk_disable(sr); -+ -+#endif -+ } else if (sr->srid == SR2) { -+#ifdef USE_EFUSE_VALUES -+ /* Read values for VDD2 from EFUSE */ -+#else -+ /* since E-Fuse Values are not available, calculating the -+ * reciprocal of the SenN and SenP values for SR2 -+ */ -+ sr->senp_mod = 0x03; -+ sr->senn_mod = 0x03; -+ -+ /* for OPP3 */ -+ senpval = 0x579 + 0x200; -+ sennval = 0x76f + 0x200; -+ -+ cal_reciprocal(senpval, &senpgain, &rnsenp); -+ cal_reciprocal(sennval, &senngain, &rnsenn); -+ -+ sr->opp3_nvalue = -+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | -+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | -+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | -+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); -+ -+ /* for OPP2 */ -+ senpval = 0x390 + 0x1c0; -+ sennval = 0x4f5 + 0x1c0; -+ -+ cal_reciprocal(senpval, &senpgain, &rnsenp); -+ cal_reciprocal(sennval, &senngain, &rnsenn); -+ -+ sr->opp2_nvalue = -+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | -+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | -+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | -+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); -+ -+ /* for OPP1 */ -+ senpval = 0x25d; -+ sennval = 0x359; -+ -+ cal_reciprocal(senpval, &senpgain, &rnsenp); -+ cal_reciprocal(sennval, &senngain, &rnsenn); -+ -+ sr->opp1_nvalue = -+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | -+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | -+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | -+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); -+ -+#endif -+ } -+ -+} -+ -+static void sr_configure_vp(int srid) -+{ -+ u32 vpconfig; -+ -+ if (srid == SR1) { -+ vpconfig = PRM_VP1_CONFIG_ERROROFFSET | PRM_VP1_CONFIG_ERRORGAIN -+ | PRM_VP1_CONFIG_INITVOLTAGE | PRM_VP1_CONFIG_TIMEOUTEN; -+ -+ PRM_VP1_CONFIG = vpconfig; -+ PRM_VP1_VSTEPMIN = PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN | -+ PRM_VP1_VSTEPMIN_VSTEPMIN; -+ -+ PRM_VP1_VSTEPMAX = PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX | -+ PRM_VP1_VSTEPMAX_VSTEPMAX; -+ -+ PRM_VP1_VLIMITTO = PRM_VP1_VLIMITTO_VDDMAX | -+ PRM_VP1_VLIMITTO_VDDMIN | PRM_VP1_VLIMITTO_TIMEOUT; -+ -+ PRM_VP1_CONFIG |= PRM_VP1_CONFIG_INITVDD; -+ PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_INITVDD; -+ -+ } else if (srid == SR2) { -+ vpconfig = PRM_VP2_CONFIG_ERROROFFSET | PRM_VP2_CONFIG_ERRORGAIN -+ | PRM_VP2_CONFIG_INITVOLTAGE | PRM_VP2_CONFIG_TIMEOUTEN; -+ -+ PRM_VP2_CONFIG = vpconfig; -+ PRM_VP2_VSTEPMIN = PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN | -+ PRM_VP2_VSTEPMIN_VSTEPMIN; -+ -+ PRM_VP2_VSTEPMAX = PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX | -+ PRM_VP2_VSTEPMAX_VSTEPMAX; -+ -+ PRM_VP2_VLIMITTO = PRM_VP2_VLIMITTO_VDDMAX | -+ PRM_VP2_VLIMITTO_VDDMIN | PRM_VP2_VLIMITTO_TIMEOUT; -+ -+ PRM_VP2_CONFIG |= PRM_VP2_CONFIG_INITVDD; -+ PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_INITVDD; -+ -+ } -+} -+ -+static void sr_configure_vc(void) -+{ -+ PRM_VC_SMPS_SA = -+ (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA1_SHIFT) | -+ (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA0_SHIFT); -+ -+ PRM_VC_SMPS_VOL_RA = (R_VDD2_SR_CONTROL << PRM_VC_SMPS_VOLRA1_SHIFT) | -+ (R_VDD1_SR_CONTROL << PRM_VC_SMPS_VOLRA0_SHIFT); -+ -+ PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL0_ON << PRM_VC_CMD_ON_SHIFT) | -+ (PRM_VC_CMD_VAL0_ONLP << PRM_VC_CMD_ONLP_SHIFT) | -+ (PRM_VC_CMD_VAL0_RET << PRM_VC_CMD_RET_SHIFT) | -+ (PRM_VC_CMD_VAL0_OFF << PRM_VC_CMD_OFF_SHIFT); -+ -+ PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL1_ON << PRM_VC_CMD_ON_SHIFT) | -+ (PRM_VC_CMD_VAL1_ONLP << PRM_VC_CMD_ONLP_SHIFT) | -+ (PRM_VC_CMD_VAL1_RET << PRM_VC_CMD_RET_SHIFT) | -+ (PRM_VC_CMD_VAL1_OFF << PRM_VC_CMD_OFF_SHIFT); -+ -+ PRM_VC_CH_CONF = PRM_VC_CH_CONF_CMD1 | PRM_VC_CH_CONF_RAV1; -+ -+ PRM_VC_I2C_CFG = PRM_VC_I2C_CFG_MCODE | PRM_VC_I2C_CFG_HSEN -+ | PRM_VC_I2C_CFG_SREN; -+ -+ /* Setup voltctrl and other setup times */ -+#ifdef CONFIG_SYSOFFMODE -+ PRM_VOLTCTRL = PRM_VOLTCTRL_AUTO_OFF | PRM_VOLTCTRL_AUTO_RET; -+ PRM_CLKSETUP = PRM_CLKSETUP_DURATION; -+ PRM_VOLTSETUP1 = (PRM_VOLTSETUP_TIME2 << PRM_VOLTSETUP_TIME2_OFFSET) | -+ (PRM_VOLTSETUP_TIME1 << PRM_VOLTSETUP_TIME1_OFFSET); -+ PRM_VOLTOFFSET = PRM_VOLTOFFSET_DURATION; -+ PRM_VOLTSETUP2 = PRM_VOLTSETUP2_DURATION; -+#else -+ PRM_VOLTCTRL |= PRM_VOLTCTRL_AUTO_RET; -+#endif -+ -+} -+ -+ -+static void sr_configure(struct omap_sr *sr) -+{ -+ u32 sys_clk, sr_clk_length = 0; -+ u32 sr_config; -+ u32 senp_en , senn_en; -+ -+ senp_en = sr->senp_mod; -+ senn_en = sr->senn_mod; -+ -+ sys_clk = prcm_get_system_clock_speed(); -+ -+ switch (sys_clk) { -+ case 12000: -+ sr_clk_length = SRCLKLENGTH_12MHZ_SYSCLK; -+ break; -+ case 13000: -+ sr_clk_length = SRCLKLENGTH_13MHZ_SYSCLK; -+ break; -+ case 19200: -+ sr_clk_length = SRCLKLENGTH_19MHZ_SYSCLK; -+ break; -+ case 26000: -+ sr_clk_length = SRCLKLENGTH_26MHZ_SYSCLK; -+ break; -+ case 38400: -+ sr_clk_length = SRCLKLENGTH_38MHZ_SYSCLK; -+ break; -+ default : -+ printk(KERN_ERR "Invalid sysclk value\n"); -+ break; -+ } -+ -+ DPRINTK(KERN_DEBUG "SR : sys clk %lu\n", sys_clk); -+ if (sr->srid == SR1) { -+ sr_config = SR1_SRCONFIG_ACCUMDATA | -+ (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) | -+ SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN | -+ SRCONFIG_MINMAXAVG_EN | -+ (senn_en << SRCONFIG_SENNENABLE_SHIFT) | -+ (senp_en << SRCONFIG_SENPENABLE_SHIFT) | -+ SRCONFIG_DELAYCTRL; -+ -+ sr_write_reg(sr, SRCONFIG, sr_config); -+ -+ sr_write_reg(sr, AVGWEIGHT, SR1_AVGWEIGHT_SENPAVGWEIGHT | -+ SR1_AVGWEIGHT_SENNAVGWEIGHT); -+ -+ sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK | -+ SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK), -+ (SR1_ERRWEIGHT | SR1_ERRMAXLIMIT | SR1_ERRMINLIMIT)); -+ -+ } else if (sr->srid == SR2) { -+ sr_config = SR2_SRCONFIG_ACCUMDATA | -+ (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) | -+ SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN | -+ SRCONFIG_MINMAXAVG_EN | -+ (senn_en << SRCONFIG_SENNENABLE_SHIFT) | -+ (senp_en << SRCONFIG_SENPENABLE_SHIFT) | -+ SRCONFIG_DELAYCTRL; -+ -+ sr_write_reg(sr, SRCONFIG, sr_config); -+ -+ sr_write_reg(sr, AVGWEIGHT, SR2_AVGWEIGHT_SENPAVGWEIGHT | -+ SR2_AVGWEIGHT_SENNAVGWEIGHT); -+ -+ sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK | -+ SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK), -+ (SR2_ERRWEIGHT | SR2_ERRMAXLIMIT | SR2_ERRMINLIMIT)); -+ -+ } -+ sr->is_sr_reset = 0; -+} -+ -+static void sr_enable(struct omap_sr *sr, u32 target_opp_no) -+{ -+ u32 nvalue_reciprocal, current_nvalue; -+ -+ sr->req_opp_no = target_opp_no; -+ -+ if (sr->srid == SR1) { -+ switch (target_opp_no) { -+ case 5: -+ nvalue_reciprocal = sr->opp5_nvalue; -+ break; -+ case 4: -+ nvalue_reciprocal = sr->opp4_nvalue; -+ break; -+ case 3: -+ nvalue_reciprocal = sr->opp3_nvalue; -+ break; -+ case 2: -+ nvalue_reciprocal = sr->opp2_nvalue; -+ break; -+ case 1: -+ nvalue_reciprocal = sr->opp1_nvalue; -+ break; -+ default: -+ nvalue_reciprocal = sr->opp3_nvalue; -+ break; -+ } -+ } else { -+ switch (target_opp_no) { -+ case 3: -+ nvalue_reciprocal = sr->opp3_nvalue; -+ break; -+ case 2: -+ nvalue_reciprocal = sr->opp2_nvalue; -+ break; -+ case 1: -+ nvalue_reciprocal = sr->opp1_nvalue; -+ break; -+ default: -+ nvalue_reciprocal = sr->opp3_nvalue; -+ break; -+ } -+ } -+ -+ current_nvalue = sr_read_reg(sr, NVALUERECIPROCAL); -+ -+ if (current_nvalue == nvalue_reciprocal) { -+ DPRINTK("System is already at the desired voltage level\n"); -+ return; -+ } -+ -+ sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal); -+ -+ /* Enable the interrupt */ -+ sr_modify_reg(sr, ERRCONFIG, -+ (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST), -+ (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST)); -+ -+ if (sr->srid == SR1) { -+ /* Enable VP1 */ -+ PRM_VP1_CONFIG |= PRM_VP1_CONFIG_VPENABLE; -+ } else if (sr->srid == SR2) { -+ /* Enable VP2 */ -+ PRM_VP2_CONFIG |= PRM_VP2_CONFIG_VPENABLE; -+ } -+ -+ /* SRCONFIG - enable SR */ -+ sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE); -+ -+} -+ -+static void sr_disable(struct omap_sr *sr) -+{ -+ sr->is_sr_reset = 1; -+ -+ /* SRCONFIG - disable SR */ -+ sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, ~SRCONFIG_SRENABLE); -+ -+ if (sr->srid == SR1) { -+ /* Enable VP1 */ -+ PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE; -+ } else if (sr->srid == SR2) { -+ /* Enable VP2 */ -+ PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE; -+ } -+} -+ -+ -+void sr_start_vddautocomap(int srid, u32 target_opp_no) -+{ -+ struct omap_sr *sr = NULL; -+ -+ if (srid == SR1) -+ sr = &sr1; -+ else if (srid == SR2) -+ sr = &sr2; -+ -+ if (sr->is_sr_reset == 1) { -+ sr_clk_enable(sr); -+ sr_configure(sr); -+ } -+ -+ if (sr->is_autocomp_active == 1) -+ DPRINTK(KERN_WARNING "SR%d: VDD autocomp is already active\n", -+ srid); -+ -+ sr->is_autocomp_active = 1; -+ sr_enable(sr, target_opp_no); -+} -+EXPORT_SYMBOL(sr_start_vddautocomap); -+ -+int sr_stop_vddautocomap(int srid) -+{ -+ struct omap_sr *sr = NULL; -+ -+ if (srid == SR1) -+ sr = &sr1; -+ else if (srid == SR2) -+ sr = &sr2; -+ -+ if (sr->is_autocomp_active == 1) { -+ sr_disable(sr); -+ sr_clk_disable(sr); -+ sr->is_autocomp_active = 0; -+ return SR_TRUE; -+ } else { -+ DPRINTK(KERN_WARNING "SR%d: VDD autocomp is not active\n", -+ srid); -+ return SR_FALSE; -+ } -+ -+} -+EXPORT_SYMBOL(sr_stop_vddautocomap); -+ -+void enable_smartreflex(int srid) -+{ -+ u32 target_opp_no = 0; -+ struct omap_sr *sr = NULL; -+ -+ if (srid == SR1) -+ sr = &sr1; -+ else if (srid == SR2) -+ sr = &sr2; -+ -+ if (sr->is_autocomp_active == 1) { -+ if (sr->is_sr_reset == 1) { -+ if (srid == SR1) { -+ /* Enable SR clks */ -+ CM_FCLKEN_WKUP |= SR1_CLK_ENABLE; -+ target_opp_no = get_opp_no(current_vdd1_opp); -+ -+ } else if (srid == SR2) { -+ /* Enable SR clks */ -+ CM_FCLKEN_WKUP |= SR2_CLK_ENABLE; -+ target_opp_no = get_opp_no(current_vdd2_opp); -+ } -+ -+ sr_configure(sr); -+ -+ sr_enable(sr, target_opp_no); -+ } -+ } -+} -+ -+void disable_smartreflex(int srid) -+{ -+ struct omap_sr *sr = NULL; -+ -+ if (srid == SR1) -+ sr = &sr1; -+ else if (srid == SR2) -+ sr = &sr2; -+ -+ if (sr->is_autocomp_active == 1) { -+ if (srid == SR1) { -+ /* Enable SR clk */ -+ CM_FCLKEN_WKUP |= SR1_CLK_ENABLE; -+ -+ } else if (srid == SR2) { -+ /* Enable SR clk */ -+ CM_FCLKEN_WKUP |= SR2_CLK_ENABLE; -+ } -+ -+ if (sr->is_sr_reset == 0) { -+ -+ sr->is_sr_reset = 1; -+ /* SRCONFIG - disable SR */ -+ sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, -+ ~SRCONFIG_SRENABLE); -+ -+ if (sr->srid == SR1) { -+ /* Disable SR clk */ -+ CM_FCLKEN_WKUP &= ~SR1_CLK_ENABLE; -+ /* Enable VP1 */ -+ PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE; -+ -+ } else if (sr->srid == SR2) { -+ /* Disable SR clk */ -+ CM_FCLKEN_WKUP &= ~SR2_CLK_ENABLE; -+ /* Enable VP2 */ -+ PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE; -+ } -+ } -+ } -+} -+ -+ -+/* Voltage Scaling using SR VCBYPASS */ -+int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel) -+{ -+ int ret; -+ int sr_status = 0; -+ u32 vdd, target_opp_no; -+ u32 vc_bypass_value; -+ u32 reg_addr = 0; -+ u32 loop_cnt = 0, retries_cnt = 0; -+ -+ vdd = get_vdd(target_opp); -+ target_opp_no = get_opp_no(target_opp); -+ -+ if (vdd == PRCM_VDD1) { -+ sr_status = sr_stop_vddautocomap(SR1); -+ -+ PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL_0 & ~PRM_VC_CMD_ON_MASK) | -+ (vsel << PRM_VC_CMD_ON_SHIFT); -+ reg_addr = R_VDD1_SR_CONTROL; -+ -+ } else if (vdd == PRCM_VDD2) { -+ sr_status = sr_stop_vddautocomap(SR2); -+ -+ PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL_1 & ~PRM_VC_CMD_ON_MASK) | -+ (vsel << PRM_VC_CMD_ON_SHIFT); -+ reg_addr = R_VDD2_SR_CONTROL; -+ } -+ -+ vc_bypass_value = (vsel << PRM_VC_BYPASS_DATA_SHIFT) | -+ (reg_addr << PRM_VC_BYPASS_REGADDR_SHIFT) | -+ (R_SRI2C_SLAVE_ADDR << PRM_VC_BYPASS_SLAVEADDR_SHIFT); -+ -+ PRM_VC_BYPASS_VAL = vc_bypass_value; -+ -+ PRM_VC_BYPASS_VAL |= PRM_VC_BYPASS_VALID; -+ -+ DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, PRM_VC_BYPASS_VAL); -+ DPRINTK("PRM_IRQST_MPU %X\n", PRM_IRQSTATUS_MPU); -+ -+ while ((PRM_VC_BYPASS_VAL & PRM_VC_BYPASS_VALID) != 0x0) { -+ ret = loop_wait(&loop_cnt, &retries_cnt, 10); -+ if (ret != PRCM_PASS) { -+ printk(KERN_INFO "Loop count exceeded in check SR I2C" -+ "write\n"); -+ return ret; -+ } -+ } -+ -+ omap_udelay(T2_SMPS_UPDATE_DELAY); -+ -+ if (sr_status) { -+ if (vdd == PRCM_VDD1) -+ sr_start_vddautocomap(SR1, target_opp_no); -+ else if (vdd == PRCM_VDD2) -+ sr_start_vddautocomap(SR2, target_opp_no); -+ } -+ -+ return SR_PASS; -+} -+ -+/* Sysfs interface to select SR VDD1 auto compensation */ -+static ssize_t omap_sr_vdd1_autocomp_show(struct kset *subsys, char *buf) -+{ -+ return sprintf(buf, "%d\n", sr1.is_autocomp_active); -+} -+ -+static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys, -+ const char *buf, size_t n) -+{ -+ u32 current_vdd1opp_no; -+ unsigned short value; -+ -+ if (sscanf(buf, "%hu", &value) != 1 || (value > 1)) { -+ printk(KERN_ERR "sr_vdd1_autocomp: Invalid value\n"); -+ return -EINVAL; -+ } -+ -+ current_vdd1opp_no = get_opp_no(current_vdd1_opp); -+ -+ if (value == 0) -+ sr_stop_vddautocomap(SR1); -+ else -+ sr_start_vddautocomap(SR1, current_vdd1opp_no); -+ -+ return n; -+} -+ -+static struct subsys_attribute sr_vdd1_autocomp = { -+ .attr = { -+ .name = __stringify(sr_vdd1_autocomp), -+ .mode = 0644, -+ }, -+ .show = omap_sr_vdd1_autocomp_show, -+ .store = omap_sr_vdd1_autocomp_store, -+}; -+ -+/* Sysfs interface to select SR VDD2 auto compensation */ -+static ssize_t omap_sr_vdd2_autocomp_show(struct kset *subsys, char *buf) -+{ -+ return sprintf(buf, "%d\n", sr2.is_autocomp_active); -+} -+ -+static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys, -+ const char *buf, size_t n) -+{ -+ u32 current_vdd2opp_no; -+ unsigned short value; -+ -+ if (sscanf(buf, "%hu", &value) != 1 || (value > 1)) { -+ printk(KERN_ERR "sr_vdd2_autocomp: Invalid value\n"); -+ return -EINVAL; -+ } -+ -+ current_vdd2opp_no = get_opp_no(current_vdd2_opp); -+ -+ if (value == 0) -+ sr_stop_vddautocomap(SR2); -+ else -+ sr_start_vddautocomap(SR2, current_vdd2opp_no); -+ -+ return n; -+} -+ -+static struct subsys_attribute sr_vdd2_autocomp = { -+ .attr = { -+ .name = __stringify(sr_vdd2_autocomp), -+ .mode = 0644, -+ }, -+ .show = omap_sr_vdd2_autocomp_show, -+ .store = omap_sr_vdd2_autocomp_store, -+}; -+ -+ -+ -+static int __init omap3_sr_init(void) -+{ -+ int ret = 0; -+ u8 RdReg; -+ -+#ifdef CONFIG_ARCH_OMAP34XX -+ sr1.fck = clk_get(NULL, "sr1_fck"); -+ if (IS_ERR(sr1.fck)) -+ printk(KERN_ERR "Could not get sr1_fck\n"); -+ -+ sr2.fck = clk_get(NULL, "sr2_fck"); -+ if (IS_ERR(sr2.fck)) -+ printk(KERN_ERR "Could not get sr2_fck\n"); -+#endif /* #ifdef CONFIG_ARCH_OMAP34XX */ -+ -+ /* Call the VPConfig, VCConfig, set N Values. */ -+ sr_set_nvalues(&sr1); -+ sr_configure_vp(SR1); -+ -+ sr_set_nvalues(&sr2); -+ sr_configure_vp(SR2); -+ -+ sr_configure_vc(); -+ -+ /* Enable SR on T2 */ -+ ret = t2_in(PM_RECEIVER, &RdReg, R_DCDC_GLOBAL_CFG); -+ RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX; -+ ret |= t2_out(PM_RECEIVER, RdReg, R_DCDC_GLOBAL_CFG); -+ -+ -+ printk(KERN_INFO "SmartReflex driver initialized\n"); -+ -+ ret = subsys_create_file(&power_subsys, &sr_vdd1_autocomp); -+ if (ret) -+ printk(KERN_ERR "subsys_create_file failed: %d\n", ret); -+ -+ ret = subsys_create_file(&power_subsys, &sr_vdd2_autocomp); -+ if (ret) -+ printk(KERN_ERR "subsys_create_file failed: %d\n", ret); -+ -+ return 0; -+} -+ -+arch_initcall(omap3_sr_init); -diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h -new file mode 100644 -index 0000000..62907ef ---- /dev/null -+++ b/arch/arm/mach-omap2/smartreflex.h -@@ -0,0 +1,136 @@ -+/* -+ * linux/arch/arm/mach-omap3/smartreflex.h -+ * -+ * Copyright (C) 2007 Texas Instruments, Inc. -+ * Lesly A M -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+ -+/* SR Modules */ -+#define SR1 1 -+#define SR2 2 -+ -+#define SR_FAIL 1 -+#define SR_PASS 0 -+ -+#define SR_TRUE 1 -+#define SR_FALSE 0 -+ -+#define GAIN_MAXLIMIT 16 -+#define R_MAXLIMIT 256 -+ -+#define SR1_CLK_ENABLE (0x1 << 6) -+#define SR2_CLK_ENABLE (0x1 << 7) -+ -+/* PRM_VP1_CONFIG */ -+#define PRM_VP1_CONFIG_ERROROFFSET (0x00 << 24) -+#define PRM_VP1_CONFIG_ERRORGAIN (0x20 << 16) -+ -+#define PRM_VP1_CONFIG_INITVOLTAGE (0x30 << 8) /* 1.2 volt */ -+#define PRM_VP1_CONFIG_TIMEOUTEN (0x1 << 3) -+#define PRM_VP1_CONFIG_INITVDD (0x1 << 2) -+#define PRM_VP1_CONFIG_FORCEUPDATE (0x1 << 1) -+#define PRM_VP1_CONFIG_VPENABLE (0x1 << 0) -+ -+/* PRM_VP1_VSTEPMIN */ -+#define PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN (0x01F4 << 8) -+#define PRM_VP1_VSTEPMIN_VSTEPMIN (0x01 << 0) -+ -+/* PRM_VP1_VSTEPMAX */ -+#define PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX (0x01F4 << 8) -+#define PRM_VP1_VSTEPMAX_VSTEPMAX (0x04 << 0) -+ -+/* PRM_VP1_VLIMITTO */ -+#define PRM_VP1_VLIMITTO_VDDMAX (0x3C << 24) -+#define PRM_VP1_VLIMITTO_VDDMIN (0x0 << 16) -+#define PRM_VP1_VLIMITTO_TIMEOUT (0xFFFF << 0) -+ -+/* PRM_VP2_CONFIG */ -+#define PRM_VP2_CONFIG_ERROROFFSET (0x00 << 24) -+#define PRM_VP2_CONFIG_ERRORGAIN (0x20 << 16) -+ -+#define PRM_VP2_CONFIG_INITVOLTAGE (0x30 << 8) /* 1.2 volt */ -+#define PRM_VP2_CONFIG_TIMEOUTEN (0x1 << 3) -+#define PRM_VP2_CONFIG_INITVDD (0x1 << 2) -+#define PRM_VP2_CONFIG_FORCEUPDATE (0x1 << 1) -+#define PRM_VP2_CONFIG_VPENABLE (0x1 << 0) -+ -+/* PRM_VP2_VSTEPMIN */ -+#define PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN (0x01F4 << 8) -+#define PRM_VP2_VSTEPMIN_VSTEPMIN (0x01 << 0) -+ -+/* PRM_VP2_VSTEPMAX */ -+#define PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX (0x01F4 << 8) -+#define PRM_VP2_VSTEPMAX_VSTEPMAX (0x04 << 0) -+ -+/* PRM_VP2_VLIMITTO */ -+#define PRM_VP2_VLIMITTO_VDDMAX (0x2C << 24) -+#define PRM_VP2_VLIMITTO_VDDMIN (0x0 << 16) -+#define PRM_VP2_VLIMITTO_TIMEOUT (0xFFFF << 0) -+ -+/* SRCONFIG */ -+#define SR1_SRCONFIG_ACCUMDATA (0x1F4 << 22) -+#define SR2_SRCONFIG_ACCUMDATA (0x1F4 << 22) -+ -+#define SRCLKLENGTH_12MHZ_SYSCLK 0x3C -+#define SRCLKLENGTH_13MHZ_SYSCLK 0x41 -+#define SRCLKLENGTH_19MHZ_SYSCLK 0x60 -+#define SRCLKLENGTH_26MHZ_SYSCLK 0x82 -+#define SRCLKLENGTH_38MHZ_SYSCLK 0xC0 -+ -+#define SRCONFIG_SRCLKLENGTH_SHIFT 12 -+#define SRCONFIG_SENNENABLE_SHIFT 5 -+#define SRCONFIG_SENPENABLE_SHIFT 3 -+ -+#define SRCONFIG_SRENABLE (0x01 << 11) -+#define SRCONFIG_SENENABLE (0x01 << 10) -+#define SRCONFIG_ERRGEN_EN (0x01 << 9) -+#define SRCONFIG_MINMAXAVG_EN (0x01 << 8) -+ -+#define SRCONFIG_DELAYCTRL (0x01 << 2) -+#define SRCONFIG_CLKCTRL (0x00 << 0) -+ -+/* AVGWEIGHT */ -+#define SR1_AVGWEIGHT_SENPAVGWEIGHT (0x03 << 2) -+#define SR1_AVGWEIGHT_SENNAVGWEIGHT (0x03 << 0) -+ -+#define SR2_AVGWEIGHT_SENPAVGWEIGHT (0x01 << 2) -+#define SR2_AVGWEIGHT_SENNAVGWEIGHT (0x01 << 0) -+ -+/* NVALUERECIPROCAL */ -+#define NVALUERECIPROCAL_SENPGAIN_SHIFT 20 -+#define NVALUERECIPROCAL_SENNGAIN_SHIFT 16 -+#define NVALUERECIPROCAL_RNSENP_SHIFT 8 -+#define NVALUERECIPROCAL_RNSENN_SHIFT 0 -+ -+/* ERRCONFIG */ -+#define SR_CLKACTIVITY_MASK (0x03 << 20) -+#define SR_ERRWEIGHT_MASK (0x07 << 16) -+#define SR_ERRMAXLIMIT_MASK (0xFF << 8) -+#define SR_ERRMINLIMIT_MASK (0xFF << 0) -+ -+#define SR_CLKACTIVITY_IOFF_FOFF (0x00 << 20) -+#define SR_CLKACTIVITY_IOFF_FON (0x02 << 20) -+ -+#define ERRCONFIG_VPBOUNDINTEN (0x1 << 31) -+#define ERRCONFIG_VPBOUNDINTST (0x1 << 30) -+ -+#define SR1_ERRWEIGHT (0x07 << 16) -+#define SR1_ERRMAXLIMIT (0x02 << 8) -+#define SR1_ERRMINLIMIT (0xFA << 0) -+ -+#define SR2_ERRWEIGHT (0x07 << 16) -+#define SR2_ERRMAXLIMIT (0x02 << 8) -+#define SR2_ERRMINLIMIT (0xF9 << 0) -+ -+extern u32 current_vdd1_opp; -+extern u32 current_vdd2_opp; -+extern struct kset power_subsys; -+ -+extern inline int loop_wait(u32 *lcnt, u32 *rcnt, u32 delay); -+extern void omap_udelay(u32 udelay); -+ --- -1.5.4.3 diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch deleted file mode 100644 index 6e31ead2bd..0000000000 --- a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch +++ /dev/null @@ -1,55 +0,0 @@ -From a1dbb6dd28e9815a307b87b8d96dcf371d6cfd58 Mon Sep 17 00:00:00 2001 -From: Jarkko Nikula -Date: Mon, 19 May 2008 13:24:41 +0300 -Subject: [PATCH] ASoC: OMAP: Add basic support for OMAP34xx in McBSP DAI driver - -This adds support for OMAP34xx McBSP port 1 and 2. - -Signed-off-by: Jarkko Nikula ---- - sound/soc/omap/omap-mcbsp.c | 20 +++++++++++++++++++- - 1 files changed, 19 insertions(+), 1 deletions(-) - -diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c -index 40d87e6..8e6ec9d 100644 ---- a/sound/soc/omap/omap-mcbsp.c -+++ b/sound/soc/omap/omap-mcbsp.c -@@ -99,6 +99,21 @@ static const unsigned long omap2420_mcbsp_port[][2] = { - static const int omap2420_dma_reqs[][2] = {}; - static const unsigned long omap2420_mcbsp_port[][2] = {}; - #endif -+#if defined(CONFIG_ARCH_OMAP34XX) -+static const int omap34xx_dma_reqs[][2] = { -+ { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX }, -+ { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX }, -+}; -+static const unsigned long omap34xx_mcbsp_port[][2] = { -+ { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR2, -+ OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR2 }, -+ { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR2, -+ OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR2 }, -+}; -+#else -+static const int omap34xx_dma_reqs[][2] = {}; -+static const unsigned long omap34xx_mcbsp_port[][2] = {}; -+#endif - - static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream) - { -@@ -169,9 +184,12 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, - } else if (cpu_is_omap2420()) { - dma = omap2420_dma_reqs[bus_id][substream->stream]; - port = omap2420_mcbsp_port[bus_id][substream->stream]; -+ } else if (cpu_is_omap343x()) { -+ dma = omap34xx_dma_reqs[bus_id][substream->stream]; -+ port = omap34xx_mcbsp_port[bus_id][substream->stream]; - } else { - /* -- * TODO: Add support for 2430 and 3430 -+ * TODO: Add support for 2430 - */ - return -ENODEV; - } --- -1.5.5.1 - diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3-cpuidle.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3-cpuidle.patch deleted file mode 100644 index cdc9447b4c..0000000000 --- a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3-cpuidle.patch +++ /dev/null @@ -1,450 +0,0 @@ -From: "Rajendra Nayak" -To: -Subject: [PATCH 01/02] OMAP3 CPUidle driver -Date: Tue, 10 Jun 2008 12:39:00 +0530 - -This patch adds the OMAP3 cpuidle driver. Irq enable/disable is done in the core cpuidle driver -before it queries the governor for the next state. - -Signed-off-by: Rajendra Nayak - ---- - arch/arm/mach-omap2/Makefile | 2 - arch/arm/mach-omap2/cpuidle34xx.c | 293 ++++++++++++++++++++++++++++++++++++++ - arch/arm/mach-omap2/cpuidle34xx.h | 51 ++++++ - arch/arm/mach-omap2/pm34xx.c | 5 - drivers/cpuidle/cpuidle.c | 10 + - 5 files changed, 359 insertions(+), 2 deletions(-) - -Index: linux-omap-2.6/arch/arm/mach-omap2/Makefile -=================================================================== ---- linux-omap-2.6.orig/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:33.855303920 +0530 -+++ linux-omap-2.6/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:39.569121361 +0530 -@@ -20,7 +20,7 @@ obj-y += pm.o - obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o - obj-$(CONFIG_ARCH_OMAP2420) += sleep242x.o - obj-$(CONFIG_ARCH_OMAP2430) += sleep243x.o --obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o -+obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o - obj-$(CONFIG_PM_DEBUG) += pm-debug.o - endif - -Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c 2008-06-10 11:41:27.644820323 +0530 -@@ -0,0 +1,293 @@ -+/* -+ * linux/arch/arm/mach-omap2/cpuidle34xx.c -+ * -+ * OMAP3 CPU IDLE Routines -+ * -+ * Copyright (C) 2007-2008 Texas Instruments, Inc. -+ * Rajendra Nayak -+ * -+ * Copyright (C) 2007 Texas Instruments, Inc. -+ * Karthik Dasu -+ * -+ * Copyright (C) 2006 Nokia Corporation -+ * Tony Lindgren -+ * -+ * Copyright (C) 2005 Texas Instruments, Inc. -+ * Richard Woodruff -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include "cpuidle34xx.h" -+ -+#ifdef CONFIG_CPU_IDLE -+ -+struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; -+struct omap3_processor_cx current_cx_state; -+ -+static int omap3_idle_bm_check(void) -+{ -+ /* Check for omap3_fclks_active() here once available */ -+ return 0; -+} -+ -+/* omap3_enter_idle - Programs OMAP3 to enter the specified state. -+ * returns the total time during which the system was idle. -+ */ -+static int omap3_enter_idle(struct cpuidle_device *dev, -+ struct cpuidle_state *state) -+{ -+ struct omap3_processor_cx *cx = cpuidle_get_statedata(state); -+ struct timespec ts_preidle, ts_postidle, ts_idle; -+ struct powerdomain *mpu_pd, *core_pd, *per_pd, *neon_pd; -+ int neon_pwrst; -+ -+ current_cx_state = *cx; -+ -+ if (cx->type == OMAP3_STATE_C0) { -+ /* Do nothing for C0, not even a wfi */ -+ return 0; -+ } -+ -+ /* Used to keep track of the total time in idle */ -+ getnstimeofday(&ts_preidle); -+ -+ mpu_pd = pwrdm_lookup("mpu_pwrdm"); -+ core_pd = pwrdm_lookup("core_pwrdm"); -+ per_pd = pwrdm_lookup("per_pwrdm"); -+ neon_pd = pwrdm_lookup("neon_pwrdm"); -+ -+ /* Reset previous power state registers */ -+ pwrdm_clear_all_prev_pwrst(mpu_pd); -+ pwrdm_clear_all_prev_pwrst(neon_pd); -+ pwrdm_clear_all_prev_pwrst(core_pd); -+ pwrdm_clear_all_prev_pwrst(per_pd); -+ -+ if (omap_irq_pending()) -+ return 0; -+ -+ neon_pwrst = pwrdm_read_pwrst(neon_pd); -+ -+ /* Program MPU/NEON to target state */ -+ if (cx->mpu_state < PWRDM_POWER_ON) { -+ if (neon_pwrst == PWRDM_POWER_ON) { -+ if (cx->mpu_state == PWRDM_POWER_RET) -+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET); -+ else if (cx->mpu_state == PWRDM_POWER_OFF) -+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_OFF); -+ } -+ pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state); -+ } -+ -+ /* Program CORE to target state */ -+ if (cx->core_state < PWRDM_POWER_ON) -+ pwrdm_set_next_pwrst(core_pd, cx->core_state); -+ -+ /* Execute ARM wfi */ -+ omap_sram_idle(); -+ -+ /* Program MPU/NEON to ON */ -+ if (cx->mpu_state < PWRDM_POWER_ON) { -+ if (neon_pwrst == PWRDM_POWER_ON) -+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_ON); -+ pwrdm_set_next_pwrst(mpu_pd, PWRDM_POWER_ON); -+ } -+ -+ if (cx->core_state < PWRDM_POWER_ON) -+ pwrdm_set_next_pwrst(core_pd, PWRDM_POWER_ON); -+ -+ getnstimeofday(&ts_postidle); -+ ts_idle = timespec_sub(ts_postidle, ts_preidle); -+ return timespec_to_ns(&ts_idle); -+} -+ -+/* -+ * omap3_enter_idle_bm - enter function for states with CPUIDLE_FLAG_CHECK_BM -+ * -+ * This function checks for all the pre-requisites needed for OMAP3 to enter -+ * CORE RET/OFF state. It then calls omap3_enter_idle to program the desired -+ * C state. -+ */ -+static int omap3_enter_idle_bm(struct cpuidle_device *dev, -+ struct cpuidle_state *state) -+{ -+ struct cpuidle_state *new_state = NULL; -+ int i, j; -+ -+ if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) { -+ -+ /* Find current state in list */ -+ for (i = 0; i < OMAP3_MAX_STATES; i++) -+ if (state == &dev->states[i]) -+ break; -+ BUG_ON(i == OMAP3_MAX_STATES); -+ -+ /* Back up to non 'CHECK_BM' state */ -+ for (j = i - 1; j > 0; j--) { -+ struct cpuidle_state *s = &dev->states[j]; -+ -+ if (!(s->flags & CPUIDLE_FLAG_CHECK_BM)) { -+ new_state = s; -+ break; -+ } -+ } -+ -+ pr_debug("%s: Bus activity: Entering %s (instead of %s)\n", -+ __FUNCTION__, new_state->name, state->name); -+ } -+ -+ return omap3_enter_idle(dev, new_state ? : state); -+} -+ -+DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); -+ -+/* omap3_init_power_states - Initialises the OMAP3 specific C states. -+ * Below is the desciption of each C state. -+ * -+ C0 . System executing code -+ C1 . MPU WFI + Core active -+ C2 . MPU CSWR + Core active -+ C3 . MPU OFF + Core active -+ C4 . MPU CSWR + Core CSWR -+ C5 . MPU OFF + Core CSWR -+ C6 . MPU OFF + Core OFF -+ */ -+void omap_init_power_states(void) -+{ -+ /* C0 . System executing code */ -+ omap3_power_states[0].valid = 1; -+ omap3_power_states[0].type = OMAP3_STATE_C0; -+ omap3_power_states[0].sleep_latency = 0; -+ omap3_power_states[0].wakeup_latency = 0; -+ omap3_power_states[0].threshold = 0; -+ omap3_power_states[0].mpu_state = PWRDM_POWER_ON; -+ omap3_power_states[0].core_state = PWRDM_POWER_ON; -+ omap3_power_states[0].flags = CPUIDLE_FLAG_TIME_VALID | -+ CPUIDLE_FLAG_SHALLOW; -+ -+ /* C1 . MPU WFI + Core active */ -+ omap3_power_states[1].valid = 1; -+ omap3_power_states[1].type = OMAP3_STATE_C1; -+ omap3_power_states[1].sleep_latency = 10; -+ omap3_power_states[1].wakeup_latency = 10; -+ omap3_power_states[1].threshold = 30; -+ omap3_power_states[1].mpu_state = PWRDM_POWER_ON; -+ omap3_power_states[1].core_state = PWRDM_POWER_ON; -+ omap3_power_states[1].flags = CPUIDLE_FLAG_TIME_VALID | -+ CPUIDLE_FLAG_SHALLOW; -+ -+ /* C2 . MPU CSWR + Core active */ -+ omap3_power_states[2].valid = 1; -+ omap3_power_states[2].type = OMAP3_STATE_C2; -+ omap3_power_states[2].sleep_latency = 50; -+ omap3_power_states[2].wakeup_latency = 50; -+ omap3_power_states[2].threshold = 300; -+ omap3_power_states[2].mpu_state = PWRDM_POWER_RET; -+ omap3_power_states[2].core_state = PWRDM_POWER_ON; -+ omap3_power_states[2].flags = CPUIDLE_FLAG_TIME_VALID | -+ CPUIDLE_FLAG_BALANCED; -+ -+ /* C3 . MPU OFF + Core active */ -+ omap3_power_states[3].valid = 0; -+ omap3_power_states[3].type = OMAP3_STATE_C3; -+ omap3_power_states[3].sleep_latency = 1500; -+ omap3_power_states[3].wakeup_latency = 1800; -+ omap3_power_states[3].threshold = 4000; -+ omap3_power_states[3].mpu_state = PWRDM_POWER_OFF; -+ omap3_power_states[3].core_state = PWRDM_POWER_RET; -+ omap3_power_states[3].flags = CPUIDLE_FLAG_TIME_VALID | -+ CPUIDLE_FLAG_BALANCED; -+ -+ /* C4 . MPU CSWR + Core CSWR*/ -+ omap3_power_states[4].valid = 1; -+ omap3_power_states[4].type = OMAP3_STATE_C4; -+ omap3_power_states[4].sleep_latency = 2500; -+ omap3_power_states[4].wakeup_latency = 7500; -+ omap3_power_states[4].threshold = 12000; -+ omap3_power_states[4].mpu_state = PWRDM_POWER_RET; -+ omap3_power_states[4].core_state = PWRDM_POWER_RET; -+ omap3_power_states[4].flags = CPUIDLE_FLAG_TIME_VALID | -+ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM; -+ -+ /* C5 . MPU OFF + Core CSWR */ -+ omap3_power_states[5].valid = 0; -+ omap3_power_states[5].type = OMAP3_STATE_C5; -+ omap3_power_states[5].sleep_latency = 3000; -+ omap3_power_states[5].wakeup_latency = 8500; -+ omap3_power_states[5].threshold = 15000; -+ omap3_power_states[5].mpu_state = PWRDM_POWER_OFF; -+ omap3_power_states[5].core_state = PWRDM_POWER_RET; -+ omap3_power_states[5].flags = CPUIDLE_FLAG_TIME_VALID | -+ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM; -+ -+ /* C6 . MPU OFF + Core OFF */ -+ omap3_power_states[6].valid = 0; -+ omap3_power_states[6].type = OMAP3_STATE_C6; -+ omap3_power_states[6].sleep_latency = 10000; -+ omap3_power_states[6].wakeup_latency = 30000; -+ omap3_power_states[6].threshold = 300000; -+ omap3_power_states[6].mpu_state = PWRDM_POWER_OFF; -+ omap3_power_states[6].core_state = PWRDM_POWER_OFF; -+ omap3_power_states[6].flags = CPUIDLE_FLAG_TIME_VALID | -+ CPUIDLE_FLAG_DEEP | CPUIDLE_FLAG_CHECK_BM; -+} -+ -+struct cpuidle_driver omap3_idle_driver = { -+ .name = "omap3_idle", -+ .owner = THIS_MODULE, -+}; -+/* -+ * omap3_idle_init - Init routine for OMAP3 idle. -+ * Registers the OMAP3 specific cpuidle driver with the cpuidle f/w -+ * with the valid set of states. -+ */ -+int omap3_idle_init(void) -+{ -+ int i, count = 0; -+ struct omap3_processor_cx *cx; -+ struct cpuidle_state *state; -+ struct cpuidle_device *dev; -+ -+ omap_init_power_states(); -+ cpuidle_register_driver(&omap3_idle_driver); -+ -+ dev = &per_cpu(omap3_idle_dev, smp_processor_id()); -+ -+ for (i = 0; i < OMAP3_MAX_STATES; i++) { -+ cx = &omap3_power_states[i]; -+ state = &dev->states[count]; -+ -+ if (!cx->valid) -+ continue; -+ cpuidle_set_statedata(state, cx); -+ state->exit_latency = cx->sleep_latency + cx->wakeup_latency; -+ state->target_residency = cx->threshold; -+ state->flags = cx->flags; -+ state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ? -+ omap3_enter_idle_bm : omap3_enter_idle; -+ sprintf(state->name, "C%d", count+1); -+ count++; -+ } -+ -+ if (!count) -+ return -EINVAL; -+ dev->state_count = count; -+ -+ if (cpuidle_register_device(dev)) { -+ printk(KERN_ERR "%s: CPUidle register device failed\n", -+ __FUNCTION__); -+ return -EIO; -+ } -+ -+ return 0; -+} -+__initcall(omap3_idle_init); -+#endif /* CONFIG_CPU_IDLE */ -Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h 2008-06-09 20:15:39.569121361 +0530 -@@ -0,0 +1,51 @@ -+/* -+ * linux/arch/arm/mach-omap2/cpuidle34xx.h -+ * -+ * OMAP3 cpuidle structure definitions -+ * -+ * Copyright (C) 2007-2008 Texas Instruments, Inc. -+ * Written by Rajendra Nayak -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED -+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. -+ * -+ * History: -+ * -+ */ -+ -+#ifndef ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX -+#define ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX -+ -+#define OMAP3_MAX_STATES 7 -+#define OMAP3_STATE_C0 0 /* C0 - System executing code */ -+#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */ -+#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */ -+#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */ -+#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */ -+#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */ -+#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */ -+ -+extern void omap_sram_idle(void); -+extern int omap3_irq_pending(void); -+ -+struct omap3_processor_cx { -+ u8 valid; -+ u8 type; -+ u32 sleep_latency; -+ u32 wakeup_latency; -+ u32 mpu_state; -+ u32 core_state; -+ u32 threshold; -+ u32 flags; -+}; -+ -+void omap_init_power_states(void); -+int omap3_idle_init(void); -+ -+#endif /* ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX */ -+ -Index: linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c -=================================================================== ---- linux-omap-2.6.orig/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:15:33.855303920 +0530 -+++ linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:16:20.976798343 +0530 -@@ -141,7 +141,7 @@ static irqreturn_t prcm_interrupt_handle - return IRQ_HANDLED; - } - --static void omap_sram_idle(void) -+void omap_sram_idle(void) - { - /* Variable to tell what needs to be saved and restored - * in omap_sram_idle*/ -@@ -156,6 +156,7 @@ static void omap_sram_idle(void) - - mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); - switch (mpu_next_state) { -+ case PWRDM_POWER_ON: - case PWRDM_POWER_RET: - /* No need to save context */ - save_state = 0; -@@ -386,7 +387,9 @@ int __init omap3_pm_init(void) - - prcm_setup_regs(); - -+#ifndef CONFIG_CPU_IDLE - pm_idle = omap3_pm_idle; -+#endif - - err1: - return ret; -Index: linux-omap-2.6/drivers/cpuidle/cpuidle.c -=================================================================== ---- linux-omap-2.6.orig/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:33.856303888 +0530 -+++ linux-omap-2.6/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:39.570121329 +0530 -@@ -58,6 +58,11 @@ static void cpuidle_idle_call(void) - return; - } - -+#ifdef CONFIG_ARCH_OMAP3 -+ local_irq_disable(); -+ local_fiq_disable(); -+#endif -+ - /* ask the governor for the next state */ - next_state = cpuidle_curr_governor->select(dev); - if (need_resched()) -@@ -70,6 +75,11 @@ static void cpuidle_idle_call(void) - target_state->time += (unsigned long long)dev->last_residency; - target_state->usage++; - -+#ifdef CONFIG_ARCH_OMAP3 -+ local_irq_enable(); -+ local_fiq_enable(); -+#endif -+ - /* give the governor an opportunity to reflect on the outcome */ - if (cpuidle_curr_governor->reflect) - cpuidle_curr_governor->reflect(dev); - --- -To unsubscribe from this list: send the line "unsubscribe linux-omap" in -the body of a message to majordomo@vger.kernel.org -More majordomo info at http://vger.kernel.org/majordomo-info.html - diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch deleted file mode 100644 index 17329be29b..0000000000 --- a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 7a444ee080c5f1a62ac5042f1e7926622b3e1ce7 Mon Sep 17 00:00:00 2001 -From: Koen Kooi -Date: Fri, 30 May 2008 13:43:36 +0200 -Subject: [PATCH] ARM: OMAP: omap3beagle: add a platform device to hook up the GPIO leds to the leds-gpio driver - -omap3beagle: add a platform device to hook up the GPIO leds to the leds-gpio driver - * on revision A5 and earlier board the two leds can't be controlled seperately, should be fixed in rev. B and C boards. - -Signed-off-by: Koen Kooi ---- - arch/arm/mach-omap2/board-omap3beagle.c | 28 ++++++++++++++++++++++++++++ - 1 files changed, 28 insertions(+), 0 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index c992cc7..83891fc 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -72,6 +73,32 @@ static struct omap_lcd_config omap3_beagle_lcd_config __initdata = { - .ctrl_name = "internal", - }; - -+struct gpio_led gpio_leds[] = { -+ { -+ .name = "beagleboard::led0", -+ .default_trigger = "none", -+ .gpio = 149, -+ }, -+ { -+ .name = "beagleboard::led1", -+ .default_trigger = "none", -+ .gpio = 150, -+ }, -+}; -+ -+static struct gpio_led_platform_data gpio_led_info = { -+ .leds = gpio_leds, -+ .num_leds = ARRAY_SIZE(gpio_leds), -+}; -+ -+static struct platform_device leds_gpio = { -+ .name = "leds-gpio", -+ .id = -1, -+ .dev = { -+ .platform_data = &gpio_led_info, -+ }, -+}; -+ - static struct omap_board_config_kernel omap3_beagle_config[] __initdata = { - { OMAP_TAG_UART, &omap3_beagle_uart_config }, - { OMAP_TAG_MMC, &omap3beagle_mmc_config }, -@@ -83,6 +110,7 @@ static struct platform_device *omap3_beagle_devices[] __initdata = { - #ifdef CONFIG_RTC_DRV_TWL4030 - &omap3_beagle_twl4030rtc_device, - #endif -+ &leds_gpio, - }; - - static void __init omap3_beagle_init(void) --- -1.5.4.3 - diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-ARM-OMAP-SmartReflex-driver.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-ARM-OMAP-SmartReflex-driver.patch deleted file mode 100644 index 8e609395a0..0000000000 --- a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-ARM-OMAP-SmartReflex-driver.patch +++ /dev/null @@ -1,278 +0,0 @@ -From: Kalle Jokiniemi -To: linux-omap@vger.kernel.org -Cc: Kalle Jokiniemi -Subject: [PATCH 2/3] ARM: OMAP: SmartReflex driver: added required register and bit definitions. -Date: Fri, 6 Jun 2008 12:49:48 +0300 - -Added new register and bit definitions to enable Smartreflex driver integration. -Also PRM_VC_SMPS_SA bit definitions' naming was changed to match the naming of -other similar bit definitions. - -Signed-off-by: Kalle Jokiniemi ---- - arch/arm/mach-omap2/prm-regbits-34xx.h | 27 ++++++-- - arch/arm/mach-omap2/smartreflex.h | 124 ++++++++++++++++++++++++++++++- - include/asm-arm/arch-omap/control.h | 19 +++++ - include/asm-arm/arch-omap/omap34xx.h | 2 + - 4 files changed, 163 insertions(+), 9 deletions(-) - -diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h -index c6a7940..f82b5a7 100644 ---- a/arch/arm/mach-omap2/prm-regbits-34xx.h -+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h -@@ -435,10 +435,10 @@ - /* PM_PWSTST_EMU specific bits */ - - /* PRM_VC_SMPS_SA */ --#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16 --#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16) --#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0 --#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0) -+#define OMAP3430_SMPS_SA1_SHIFT 16 -+#define OMAP3430_SMPS_SA1_MASK (0x7f << 16) -+#define OMAP3430_SMPS_SA0_SHIFT 0 -+#define OMAP3430_SMPS_SA0_MASK (0x7f << 0) - - /* PRM_VC_SMPS_VOL_RA */ - #define OMAP3430_VOLRA1_SHIFT 16 -@@ -452,7 +452,7 @@ - #define OMAP3430_CMDRA0_SHIFT 0 - #define OMAP3430_CMDRA0_MASK (0xff << 0) - --/* PRM_VC_CMD_VAL_0 specific bits */ -+/* PRM_VC_CMD_VAL */ - #define OMAP3430_VC_CMD_ON_SHIFT 24 - #define OMAP3430_VC_CMD_ON_MASK (0xFF << 24) - #define OMAP3430_VC_CMD_ONLP_SHIFT 16 -@@ -462,7 +462,17 @@ - #define OMAP3430_VC_CMD_OFF_SHIFT 0 - #define OMAP3430_VC_CMD_OFF_MASK (0xFF << 0) - -+/* PRM_VC_CMD_VAL_0 specific bits */ -+#define OMAP3430_VC_CMD_VAL0_ON (0x3 << 4) -+#define OMAP3430_VC_CMD_VAL0_ONLP (0x3 << 3) -+#define OMAP3430_VC_CMD_VAL0_RET (0x3 << 3) -+#define OMAP3430_VC_CMD_VAL0_OFF (0x3 << 3) -+ - /* PRM_VC_CMD_VAL_1 specific bits */ -+#define OMAP3430_VC_CMD_VAL1_ON (0xB << 2) -+#define OMAP3430_VC_CMD_VAL1_ONLP (0x3 << 3) -+#define OMAP3430_VC_CMD_VAL1_RET (0x3 << 3) -+#define OMAP3430_VC_CMD_VAL1_OFF (0x3 << 3) - - /* PRM_VC_CH_CONF */ - #define OMAP3430_CMD1 (1 << 20) -@@ -521,6 +531,13 @@ - #define OMAP3430_AUTO_RET (1 << 1) - #define OMAP3430_AUTO_SLEEP (1 << 0) - -+/* Constants to define setup durations */ -+#define OMAP3430_CLKSETUP_DURATION 0xff -+#define OMAP3430_VOLTSETUP_TIME2 0xfff -+#define OMAP3430_VOLTSETUP_TIME1 0xfff -+#define OMAP3430_VOLTOFFSET_DURATION 0xff -+#define OMAP3430_VOLTSETUP2_DURATION 0xff -+ - /* PRM_SRAM_PCHARGE */ - #define OMAP3430_PCHARGE_TIME_SHIFT 0 - #define OMAP3430_PCHARGE_TIME_MASK (0xff << 0) -diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h -index 62907ef..2091a15 100644 ---- a/arch/arm/mach-omap2/smartreflex.h -+++ b/arch/arm/mach-omap2/smartreflex.h -@@ -1,5 +1,10 @@ -+#ifndef __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H -+#define __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H - /* -- * linux/arch/arm/mach-omap3/smartreflex.h -+ * linux/arch/arm/mach-omap2/smartreflex.h -+ * -+ * Copyright (C) 2008 Nokia Corporation -+ * Kalle Jokiniemi - * - * Copyright (C) 2007 Texas Instruments, Inc. - * Lesly A M -@@ -9,6 +14,21 @@ - * published by the Free Software Foundation. - */ - -+#define PHY_TO_OFF_PM_MASTER(p) (p - 0x36) -+#define PHY_TO_OFF_PM_RECIEVER(p) (p - 0x5b) -+#define PHY_TO_OFF_PM_INT(p) (p - 0x2e) -+ -+/* SMART REFLEX REG ADDRESS OFFSET */ -+#define SRCONFIG 0x00 -+#define SRSTATUS 0x04 -+#define SENVAL 0x08 -+#define SENMIN 0x0C -+#define SENMAX 0x10 -+#define SENAVG 0x14 -+#define AVGWEIGHT 0x18 -+#define NVALUERECIPROCAL 0x1C -+#define SENERROR 0x20 -+#define ERRCONFIG 0x24 - - /* SR Modules */ - #define SR1 1 -@@ -127,10 +147,106 @@ - #define SR2_ERRMAXLIMIT (0x02 << 8) - #define SR2_ERRMINLIMIT (0xF9 << 0) - -+/* T2 SMART REFLEX */ -+#define R_SRI2C_SLAVE_ADDR 0x12 -+#define R_VDD1_SR_CONTROL 0x00 -+#define R_VDD2_SR_CONTROL 0x01 -+#define T2_SMPS_UPDATE_DELAY 360 /* In uSec */ -+ -+/* Vmode control */ -+#define R_DCDC_GLOBAL_CFG PHY_TO_OFF_PM_RECIEVER(0x61) -+ -+#define R_VDD1_VSEL PHY_TO_OFF_PM_RECIEVER(0xb9) -+#define R_VDD1_VMODE_CFG PHY_TO_OFF_PM_RECIEVER(0xba) -+#define R_VDD1_VFLOOR PHY_TO_OFF_PM_RECIEVER(0xbb) -+#define R_VDD1_VROOF PHY_TO_OFF_PM_RECIEVER(0xbc) -+#define R_VDD1_STEP PHY_TO_OFF_PM_RECIEVER(0xbd) -+ -+#define R_VDD2_VSEL PHY_TO_OFF_PM_RECIEVER(0xc7) -+#define R_VDD2_VMODE_CFG PHY_TO_OFF_PM_RECIEVER(0xc8) -+#define R_VDD2_VFLOOR PHY_TO_OFF_PM_RECIEVER(0xc9) -+#define R_VDD2_VROOF PHY_TO_OFF_PM_RECIEVER(0xca) -+#define R_VDD2_STEP PHY_TO_OFF_PM_RECIEVER(0xcb) -+ -+/* R_DCDC_GLOBAL_CFG register, SMARTREFLEX_ENABLE valuws */ -+#define DCDC_GLOBAL_CFG_ENABLE_SRFLX 0x08 -+ -+/* VDDs*/ -+#define PRCM_VDD1 1 -+#define PRCM_VDD2 2 -+#define PRCM_MAX_SYSC_REGS 30 -+ -+/* XXX: These should be removed/moved from here once we have a working DVFS -+ implementation in place */ -+#define AT_3430 1 /*3430 ES 1.0 */ -+#define AT_3430_ES2 2 /*3430 ES 2.0 */ -+ -+#define ID_OPP 0xE2 /*OPP*/ -+ -+/* DEVICE ID/DPLL ID/CLOCK ID: bits 28-31 for OMAP type */ -+#define OMAP_TYPE_SHIFT 28 -+#define OMAP_TYPE_MASK 0xF -+/* OPP ID: bits: 0-4 for OPP number */ -+#define OPP_NO_POS 0 -+#define OPP_NO_MASK 0x1F -+/* OPP ID: bits: 5-6 for VDD */ -+#define VDD_NO_POS 5 -+#define VDD_NO_MASK 0x3 -+/* Other IDs: bits 20-27 for ID type */ -+/* These IDs have bits 25,26,27 as 1 */ -+#define OTHER_ID_TYPE_SHIFT 20 -+#define OTHER_ID_TYPE_MASK 0xFF -+ -+#define OTHER_ID_TYPE(X) ((X & OTHER_ID_TYPE_MASK) << OTHER_ID_TYPE_SHIFT) -+#define ID_OPP_NO(X) ((X & OPP_NO_MASK) << OPP_NO_POS) -+#define ID_VDD(X) ((X & VDD_NO_MASK) << VDD_NO_POS) -+#define OMAP(X) ((X >> OMAP_TYPE_SHIFT) & OMAP_TYPE_MASK) -+#define get_opp_no(X) ((X >> OPP_NO_POS) & OPP_NO_MASK) -+#define get_vdd(X) ((X >> VDD_NO_POS) & VDD_NO_MASK) -+ -+/* VDD1 OPPs */ -+#define PRCM_VDD1_OPP1 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ -+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x1)) -+#define PRCM_VDD1_OPP2 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ -+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x2)) -+#define PRCM_VDD1_OPP3 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ -+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x3)) -+#define PRCM_VDD1_OPP4 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ -+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x4)) -+#define PRCM_VDD1_OPP5 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ -+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x5)) -+#define PRCM_NO_VDD1_OPPS 5 -+ -+ -+/* VDD2 OPPs */ -+#define PRCM_VDD2_OPP1 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ -+ ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x1)) -+#define PRCM_VDD2_OPP2 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ -+ ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x2)) -+#define PRCM_VDD2_OPP3 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ -+ ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x3)) -+#define PRCM_NO_VDD2_OPPS 3 -+/* XXX: end remove/move */ -+ -+ -+/* XXX: find more appropriate place for these once DVFS is in place */ - extern u32 current_vdd1_opp; - extern u32 current_vdd2_opp; --extern struct kset power_subsys; - --extern inline int loop_wait(u32 *lcnt, u32 *rcnt, u32 delay); --extern void omap_udelay(u32 udelay); -+/* -+ * Smartreflex module enable/disable interface. -+ * NOTE: if smartreflex is not enabled from sysfs, these functions will not -+ * do anything. -+ */ -+#if defined(CONFIG_ARCH_OMAP34XX) && defined(CONFIG_TWL4030_CORE) -+void enable_smartreflex(int srid); -+void disable_smartreflex(int srid); -+#else -+static inline void enable_smartreflex(int srid) {} -+static inline void disable_smartreflex(int srid) {} -+#endif -+ -+ -+#endif -+ - -diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h -index 12bc22a..6e64fe7 100644 ---- a/include/asm-arm/arch-omap/control.h -+++ b/include/asm-arm/arch-omap/control.h -@@ -138,6 +138,15 @@ - #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) - #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) - #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) -+#define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) -+#define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) -+#define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) -+#define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c) -+#define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) -+#define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124) -+#define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) -+#define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c) -+#define OMAP343X_CONTROL_FUSE_SR (OMAP2_CONTROL_GENERAL + 0x0130) - #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) - #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) - #define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4) -@@ -172,6 +181,16 @@ - #define OMAP2_SYSBOOT_1_MASK (1 << 1) - #define OMAP2_SYSBOOT_0_MASK (1 << 0) - -+/* CONTROL_FUSE_SR bits */ -+#define OMAP343X_SR2_SENNENABLE_MASK (0x3 << 10) -+#define OMAP343X_SR2_SENNENABLE_SHIFT 10 -+#define OMAP343X_SR2_SENPENABLE_MASK (0x3 << 8) -+#define OMAP343X_SR2_SENPENABLE_SHIFT 8 -+#define OMAP343X_SR1_SENNENABLE_MASK (0x3 << 2) -+#define OMAP343X_SR1_SENNENABLE_SHIFT 2 -+#define OMAP343X_SR1_SENPENABLE_MASK (0x3 << 0) -+#define OMAP343X_SR1_SENPENABLE_SHIFT 0 -+ - #ifndef __ASSEMBLY__ - #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) - extern void __iomem *omap_ctrl_base_get(void); -diff --git a/include/asm-arm/arch-omap/omap34xx.h b/include/asm-arm/arch-omap/omap34xx.h -index 6a0459a..3667fd6 100644 ---- a/include/asm-arm/arch-omap/omap34xx.h -+++ b/include/asm-arm/arch-omap/omap34xx.h -@@ -54,6 +54,8 @@ - #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000) - #define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000) - #define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000) -+#define OMAP34XX_SR1_BASE 0x480C9000 -+#define OMAP34XX_SR2_BASE 0x480CB000 - - - #if defined(CONFIG_ARCH_OMAP3430) --- -1.5.4.3 diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-omap3-cpuidle.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-omap3-cpuidle.patch deleted file mode 100644 index d35fd47567..0000000000 --- a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0002-omap3-cpuidle.patch +++ /dev/null @@ -1,88 +0,0 @@ -From: "Rajendra Nayak" -To: -Subject: [PATCH 02/02] Kconfig changes -Date: Tue, 10 Jun 2008 12:39:02 +0530 - -Updates the CPUidle Kconfig - -Signed-off-by: Rajendra Nayak - ---- - arch/arm/Kconfig | 10 ++++++++++ - drivers/cpuidle/Kconfig | 28 ++++++++++++++++++++++------ - 2 files changed, 32 insertions(+), 6 deletions(-) - -Index: linux-omap-2.6/arch/arm/Kconfig -=================================================================== ---- linux-omap-2.6.orig/arch/arm/Kconfig 2008-06-10 11:43:10.790502713 +0530 -+++ linux-omap-2.6/arch/arm/Kconfig 2008-06-10 11:43:38.701604549 +0530 -@@ -954,6 +954,16 @@ config ATAGS_PROC - - endmenu - -+if (ARCH_OMAP) -+ -+menu "CPUIdle" -+ -+source "drivers/cpuidle/Kconfig" -+ -+endmenu -+ -+endif -+ - if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA) - - menu "CPU Frequency scaling" -Index: linux-omap-2.6/drivers/cpuidle/Kconfig -=================================================================== ---- linux-omap-2.6.orig/drivers/cpuidle/Kconfig 2008-06-10 11:43:10.790502713 +0530 -+++ linux-omap-2.6/drivers/cpuidle/Kconfig 2008-06-10 12:06:36.139332151 +0530 -@@ -1,20 +1,36 @@ -+menu "CPU idle PM support" - - config CPU_IDLE - bool "CPU idle PM support" -- default ACPI -+ default n - help - CPU idle is a generic framework for supporting software-controlled - idle processor power management. It includes modular cross-platform - governors that can be swapped during runtime. - -- If you're using an ACPI-enabled platform, you should say Y here. -+ If you're using a mobile platform that supports CPU idle PM (e.g. -+ an ACPI-capable notebook), you should say Y here. -+ -+if CPU_IDLE -+ -+comment "Governors" - - config CPU_IDLE_GOV_LADDER -- bool -+ bool "ladder" - depends on CPU_IDLE -- default y -+ default n - - config CPU_IDLE_GOV_MENU -- bool -+ bool "menu" - depends on CPU_IDLE && NO_HZ -- default y -+ default n -+ help -+ This cpuidle governor evaluates all available states and chooses the -+ deepest state that meets all of the following constraints: BM activity, -+ expected time until next timer interrupt, and last break event time -+ delta. It is designed to minimize power consumption. Currently -+ dynticks is required. -+ -+endif # CPU_IDLE -+ -+endmenu - --- -To unsubscribe from this list: send the line "unsubscribe linux-omap" in -the body of a message to majordomo@vger.kernel.org -More majordomo info at http://vger.kernel.org/majordomo-info.html - diff --git a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0003-ARM-OMAP-SmartReflex-driver.patch b/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0003-ARM-OMAP-SmartReflex-driver.patch deleted file mode 100644 index 40d5790367..0000000000 --- a/meta/recipes-kernel/linux/linux-omap2-git/omap3evm/0003-ARM-OMAP-SmartReflex-driver.patch +++ /dev/null @@ -1,1001 +0,0 @@ -From: Kalle Jokiniemi -To: linux-omap@vger.kernel.org -Cc: Kalle Jokiniemi -Subject: [PATCH 3/3] ARM: OMAP: SmartReflex driver: integration to linux-omap -Date: Fri, 6 Jun 2008 12:49:49 +0300 -Message-Id: <1212745789-13926-3-git-send-email-ext-kalle.jokiniemi@nokia.com> - -- Changed register accesses to use prm_{read,write}_mod_reg and - prm_{set,clear,rmw}_mod_reg_bits() functions instread of - "REG_X = REG_Y" type accesses. - -- Changed direct register clock enables/disab