| Age | Commit message (Collapse) | Author | Files | |
|---|---|---|---|---|
| 2018-03-25 | site/risc-v: Cache common variables to build libIDL | Khem Raj | 1 | |
| These variables force runtime tests during configure they are already cached for other architectures Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Ross Burton <ross.burton@intel.com> | ||||
| 2018-03-15 | site/riscv: Shunt the realloc configure test for startup-notification | Khem Raj | 1 | |
| Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Ross Burton <ross.burton@intel.com> | ||||
| 2017-11-05 | site: Add riscv32 and riscv64 | Khem Raj | 1 | |
| Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Ross Burton <ross.burton@intel.com> | ||||
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index : openembedded-core.git | |
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