diff options
Diffstat (limited to 'meta/recipes-devtools')
| -rw-r--r-- | meta/recipes-devtools/binutils/binutils-2.22.inc | 2 | ||||
| -rw-r--r-- | meta/recipes-devtools/binutils/binutils/binutils-powerpc-e5500.patch | 918 |
2 files changed, 872 insertions, 48 deletions
diff --git a/meta/recipes-devtools/binutils/binutils-2.22.inc b/meta/recipes-devtools/binutils/binutils-2.22.inc index 6f1e0dc4ed..ca2d30eca9 100644 --- a/meta/recipes-devtools/binutils/binutils-2.22.inc +++ b/meta/recipes-devtools/binutils/binutils-2.22.inc @@ -1,4 +1,4 @@ -PR = "r10" +PR = "r11" LIC_FILES_CHKSUM="\ file://src-release;endline=17;md5=4830a9ef968f3b18dd5e9f2c00db2d35\ diff --git a/meta/recipes-devtools/binutils/binutils/binutils-powerpc-e5500.patch b/meta/recipes-devtools/binutils/binutils/binutils-powerpc-e5500.patch index cd42a77324..1f146ce68e 100644 --- a/meta/recipes-devtools/binutils/binutils/binutils-powerpc-e5500.patch +++ b/meta/recipes-devtools/binutils/binutils/binutils-powerpc-e5500.patch @@ -1,103 +1,501 @@ -Upstream-Status: Pending +Upstream-Status: Backport +Signed-off- by: Khem Raj <raj.khem@gmail.com> -Add support for FSL PowerPC e5500 core. +From 4f017a6dfe0c3e84c21431c85e82ce2af0941ac1 Mon Sep 17 00:00:00 2001 +From: Alan Modra <amodra@bigpond.net.au> +Date: Fri, 9 Mar 2012 23:39:02 +0000 +Subject: [PATCH] include/opcode/ * ppc.h: Add PPC_OPCODE_ALTIVEC2, + PPC_OPCODE_E6500, PPC_OPCODE_TMR. opcodes/ * ppc-dis.c + (ppc_opts): Add entries for "e5500" and "e6500". * + ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New. + (PPCVEC2, PPCTMR, E6500): New short names. + (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, + mvidsplt, mviwsplt, icblq., mftmr, mttmr, dcblq., + miso, lvexbx, lvexhx, lvexwx, stvexbx, stvexhx, stvexwx, + lvepx, lvepxl, stvepx, stvepxl, lvtrx, lvtrxl, + lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl, + lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, + ESYNC optional operands on sync instruction for E6500 + target. bfd/ * archures.c: Add bfd_mach_ppc_e5500 and + bfd_mach_ppc_e6500. * bfd-in2.h: Regenerate. * + cpu-powerpc.c (bfd_powerpc_archs): Add entryies for + bfd_mach_ppc_e5500 and bfd_mach_ppc_e6500. gas/ * + config/tc-ppc.c (md_show_usage): Document -me5500 and + -me6500. (ppc_handle_align): Add termination nop + opcode for e500mc family. * doc/as.texinfo: Document + options -me5500 and -me6500. * doc/c-ppc.texi: Likewise. + gas/testsuite/ * gas/ppc/e500mc64_nop.s: New test + case for e500mc family termination nops. * + gas/ppc/e500mc64_nop.d: Likewise. * + gas/ppc/e5500_nop.s: Likewise. * + gas/ppc/e5500_nop.d: Likewise. * + gas/ppc/e6500_nop.s: Likewise. * + gas/ppc/e6500_nop.d: Likewise. * gas/ppc/e6500.s: + New. * gas/ppc/e6500.d: Likewise. * gas/ppc/ppc.exp: + Run e6500, e500mc64_nop, e5500_nop, and e6500_nop. -Signed-off-by: Edmar Wienskoski <edmar@freescale.com> -Signed-off-by: Kumar Gala <galak@kernel.crashing.org> +--- + bfd/ChangeLog | 7 +++ + bfd/archures.c | 6 +- + bfd/bfd-in2.h | 2 + + bfd/cpu-powerpc.c | 34 ++++++++++- + gas/ChangeLog | 7 +++ + gas/config/tc-ppc.c | 14 ++++- + gas/doc/as.texinfo | 6 +- + gas/doc/c-ppc.texi | 8 ++- + gas/testsuite/ChangeLog | 13 ++++ + gas/testsuite/gas/ppc/e500mc64_nop.d | 13 ++++ + gas/testsuite/gas/ppc/e500mc64_nop.s | 5 ++ + gas/testsuite/gas/ppc/e5500_nop.d | 13 ++++ + gas/testsuite/gas/ppc/e5500_nop.s | 5 ++ + gas/testsuite/gas/ppc/e6500.d | 75 +++++++++++++++++++++++ + gas/testsuite/gas/ppc/e6500.s | 69 +++++++++++++++++++++ + gas/testsuite/gas/ppc/e6500_nop.d | 13 ++++ + gas/testsuite/gas/ppc/e6500_nop.s | 5 ++ + gas/testsuite/gas/ppc/ppc.exp | 4 ++ + include/opcode/ChangeLog | 4 ++ + include/opcode/ppc.h | 11 +++- + opcodes/ChangeLog | 12 ++++ + opcodes/ppc-dis.c | 14 ++++- + opcodes/ppc-opc.c | 112 +++++++++++++++++++++++++++++++--- + 23 files changed, 432 insertions(+), 20 deletions(-) + create mode 100644 gas/testsuite/gas/ppc/e500mc64_nop.d + create mode 100644 gas/testsuite/gas/ppc/e500mc64_nop.s + create mode 100644 gas/testsuite/gas/ppc/e5500_nop.d + create mode 100644 gas/testsuite/gas/ppc/e5500_nop.s + create mode 100644 gas/testsuite/gas/ppc/e6500.d + create mode 100644 gas/testsuite/gas/ppc/e6500.s + create mode 100644 gas/testsuite/gas/ppc/e6500_nop.d + create mode 100644 gas/testsuite/gas/ppc/e6500_nop.s Index: binutils-2.22/bfd/archures.c =================================================================== ---- binutils-2.22.orig/bfd/archures.c -+++ binutils-2.22/bfd/archures.c -@@ -239,6 +239,7 @@ DESCRIPTION +--- binutils-2.22.orig/bfd/archures.c 2012-07-06 20:40:40.000000000 -0700 ++++ binutils-2.22/bfd/archures.c 2012-07-06 20:41:27.822780001 -0700 +@@ -1,7 +1,7 @@ + /* BFD library support routines for architectures. + Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +- 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 +- Free Software Foundation, Inc. ++ 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, ++ 2012 Free Software Foundation, Inc. + Hacked by John Gilmore and Steve Chamberlain of Cygnus Support. + + This file is part of BFD, the Binary File Descriptor library. +@@ -239,6 +239,8 @@ .#define bfd_mach_ppc_e500 500 .#define bfd_mach_ppc_e500mc 5001 .#define bfd_mach_ppc_e500mc64 5005 +.#define bfd_mach_ppc_e5500 5006 ++.#define bfd_mach_ppc_e6500 5007 .#define bfd_mach_ppc_titan 83 . bfd_arch_rs6000, {* IBM RS/6000 *} .#define bfd_mach_rs6k 6000 Index: binutils-2.22/bfd/bfd-in2.h =================================================================== ---- binutils-2.22.orig/bfd/bfd-in2.h -+++ binutils-2.22/bfd/bfd-in2.h -@@ -1946,6 +1946,7 @@ enum bfd_architecture +--- binutils-2.22.orig/bfd/bfd-in2.h 2012-07-06 20:40:40.000000000 -0700 ++++ binutils-2.22/bfd/bfd-in2.h 2012-07-06 20:41:27.822780001 -0700 +@@ -1946,6 +1946,8 @@ #define bfd_mach_ppc_e500 500 #define bfd_mach_ppc_e500mc 5001 #define bfd_mach_ppc_e500mc64 5005 +#define bfd_mach_ppc_e5500 5006 ++#define bfd_mach_ppc_e6500 5007 #define bfd_mach_ppc_titan 83 bfd_arch_rs6000, /* IBM RS/6000 */ #define bfd_mach_rs6k 6000 Index: binutils-2.22/bfd/cpu-powerpc.c =================================================================== ---- binutils-2.22.orig/bfd/cpu-powerpc.c -+++ binutils-2.22/bfd/cpu-powerpc.c -@@ -352,6 +352,20 @@ const bfd_arch_info_type bfd_powerpc_arc - FALSE, /* not the default */ - powerpc_compatible, - bfd_default_scan, -+ &bfd_powerpc_archs[19] -+ }, -+ { -+ 64, /* 64 bits in a word */ -+ 64, /* 64 bits in an address */ -+ 8, /* 8 bits in a byte */ -+ bfd_arch_powerpc, -+ bfd_mach_ppc_e5500, -+ "powerpc", -+ "powerpc:e5500", -+ 3, -+ FALSE, /* not the default */ -+ powerpc_compatible, -+ bfd_default_scan, - 0 - } - }; +--- binutils-2.22.orig/bfd/cpu-powerpc.c 2012-07-06 20:40:40.000000000 -0700 ++++ binutils-2.22/bfd/cpu-powerpc.c 2012-07-06 20:41:27.822780001 -0700 +@@ -1,6 +1,6 @@ + /* BFD PowerPC CPU definition +- Copyright 1994, 1995, 1996, 2000, 2001, 2002, 2003, 2005, 2007, 2008, 2010 +- Free Software Foundation, Inc. ++ Copyright 1994, 1995, 1996, 2000, 2001, 2002, 2003, 2005, 2007, 2008, ++ 2010, 2012 Free Software Foundation, Inc. + Contributed by Ian Lance Taylor, Cygnus Support. + + This file is part of BFD, the Binary File Descriptor library. Index: binutils-2.22/gas/config/tc-ppc.c =================================================================== ---- binutils-2.22.orig/gas/config/tc-ppc.c -+++ binutils-2.22/gas/config/tc-ppc.c -@@ -1265,6 +1265,7 @@ PowerPC options:\n\ +--- binutils-2.22.orig/gas/config/tc-ppc.c 2012-07-06 20:40:40.000000000 -0700 ++++ binutils-2.22/gas/config/tc-ppc.c 2012-07-06 20:41:27.826780001 -0700 +@@ -1,6 +1,6 @@ + /* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000) + Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, +- 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 ++ 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 + Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support. + +@@ -1265,6 +1265,8 @@ -me500, -me500x2 generate code for Motorola e500 core complex\n\ -me500mc, generate code for Freescale e500mc core complex\n\ -me500mc64, generate code for Freescale e500mc64 core complex\n\ +-me5500, generate code for Freescale e5500 core complex\n\ ++-me6500, generate code for Freescale e6500 core complex\n\ -mspe generate code for Motorola SPE instructions\n\ -mtitan generate code for AppliedMicro Titan core complex\n\ -mregnames Allow symbolic names for registers\n\ +@@ -6012,8 +6014,14 @@ + } + + if ((ppc_cpu & PPC_OPCODE_POWER7) != 0) +- /* power7 group terminating nop: "ori 2,2,0". */ +- md_number_to_chars (dest, 0x60420000, 4); ++ { ++ if (ppc_cpu & PPC_OPCODE_E500MC) ++ /* e500mc group terminating nop: "ori 0,0,0". */ ++ md_number_to_chars (dest, 0x60000000, 4); ++ else ++ /* power7 group terminating nop: "ori 2,2,0". */ ++ md_number_to_chars (dest, 0x60420000, 4); ++ } + else + /* power6 group terminating nop: "ori 1,1,0". */ + md_number_to_chars (dest, 0x60210000, 4); Index: binutils-2.22/gas/doc/as.texinfo =================================================================== ---- binutils-2.22.orig/gas/doc/as.texinfo -+++ binutils-2.22/gas/doc/as.texinfo -@@ -434,7 +434,7 @@ gcc(1), ld(1), and the Info entries for +--- binutils-2.22.orig/gas/doc/as.texinfo 2012-07-06 20:40:40.000000000 -0700 ++++ binutils-2.22/gas/doc/as.texinfo 2012-07-06 20:41:27.826780001 -0700 +@@ -1,6 +1,6 @@ + \input texinfo @c -*-Texinfo-*- + @c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, +-@c 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 ++@c 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 + @c Free Software Foundation, Inc. + @c UPDATE!! On future updates-- + @c (1) check for new machine-dep cmdline options in +@@ -434,8 +434,8 @@ [@b{-a32}|@b{-a64}] [@b{-mpwrx}|@b{-mpwr2}|@b{-mpwr}|@b{-m601}|@b{-mppc}|@b{-mppc32}|@b{-m603}|@b{-m604}|@b{-m403}|@b{-m405}| @b{-m440}|@b{-m464}|@b{-m476}|@b{-m7400}|@b{-m7410}|@b{-m7450}|@b{-m7455}|@b{-m750cl}|@b{-mppc64}| - @b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-mppc64bridge}|@b{-mbooke}| -+ @b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-me5500}|@b{-mppc64bridge}|@b{-mbooke}| - @b{-mpower4}|@b{-mpr4}|@b{-mpower5}|@b{-mpwr5}|@b{-mpwr5x}|@b{-mpower6}|@b{-mpwr6}| +- @b{-mpower4}|@b{-mpr4}|@b{-mpower5}|@b{-mpwr5}|@b{-mpwr5x}|@b{-mpower6}|@b{-mpwr6}| ++ @b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-me5500}|@b{-me6500}|@b{-mppc64bridge}| ++ @b{-mbooke}|@b{-mpower4}|@b{-mpr4}|@b{-mpower5}|@b{-mpwr5}|@b{-mpwr5x}|@b{-mpower6}|@b{-mpwr6}| @b{-mpower7}|@b{-mpw7}|@b{-ma2}|@b{-mcell}|@b{-mspe}|@b{-mtitan}|@b{-me300}|@b{-mcom}] [@b{-many}] [@b{-maltivec}|@b{-mvsx}] + [@b{-mregnames}|@b{-mno-regnames}] Index: binutils-2.22/gas/doc/c-ppc.texi =================================================================== ---- binutils-2.22.orig/gas/doc/c-ppc.texi -+++ binutils-2.22/gas/doc/c-ppc.texi -@@ -88,6 +88,9 @@ Generate code for Freescale e500mc core +--- binutils-2.22.orig/gas/doc/c-ppc.texi 2012-07-06 20:40:40.000000000 -0700 ++++ binutils-2.22/gas/doc/c-ppc.texi 2012-07-06 20:41:27.826780001 -0700 +@@ -1,5 +1,5 @@ + @c Copyright 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011 +-@c Free Software Foundation, Inc. ++@c 2012 Free Software Foundation, Inc. + @c This is part of the GAS manual. + @c For copying conditions, see the file as.texinfo. + @c man end +@@ -88,6 +88,12 @@ @item -me500mc64 Generate code for Freescale e500mc64 core complex. +@item -me5500 +Generate code for Freescale e5500 core complex. + ++@item -me6500 ++Generate code for Freescale e6500 core complex. ++ @item -mspe Generate code for Motorola SPE instructions. +Index: binutils-2.22/gas/testsuite/gas/ppc/e500mc64_nop.d +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ binutils-2.22/gas/testsuite/gas/ppc/e500mc64_nop.d 2012-07-06 20:41:27.826780001 -0700 +@@ -0,0 +1,13 @@ ++#as: -mppc -me500mc64 ++#objdump: -dr -Me500mc64 ++#name: Power E500MC64 nop tests ++ ++.*: +file format elf(32)?(64)?-powerpc.* ++ ++Disassembly of section \.text: ++ ++0+00 <start>: ++ 0: 60 00 00 00 nop ++ 4: 60 00 00 00 nop ++ 8: 60 00 00 00 nop ++ c: 60 00 00 00 nop +Index: binutils-2.22/gas/testsuite/gas/ppc/e500mc64_nop.s +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ binutils-2.22/gas/testsuite/gas/ppc/e500mc64_nop.s 2012-07-06 20:41:27.826780001 -0700 +@@ -0,0 +1,5 @@ ++# Power E500MC64 nop tests ++ .section ".text" ++start: ++ nop ++ .p2align 4,,15 +Index: binutils-2.22/gas/testsuite/gas/ppc/e5500_nop.d +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ binutils-2.22/gas/testsuite/gas/ppc/e5500_nop.d 2012-07-06 20:41:27.826780001 -0700 +@@ -0,0 +1,13 @@ ++#as: -mppc -me5500 ++#objdump: -dr -Me5500 ++#name: Power E5500 nop tests ++ ++.*: +file format elf(32)?(64)?-powerpc.* ++ ++Disassembly of section \.text: ++ ++0+00 <start>: ++ 0: 60 00 00 00 nop ++ 4: 60 00 00 00 nop ++ 8: 60 00 00 00 nop ++ c: 60 00 00 00 nop +Index: binutils-2.22/gas/testsuite/gas/ppc/e5500_nop.s +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ binutils-2.22/gas/testsuite/gas/ppc/e5500_nop.s 2012-07-06 20:41:27.826780001 -0700 +@@ -0,0 +1,5 @@ ++# Power E5500 nop tests ++ .section ".text" ++start: ++ nop ++ .p2align 4,,15 +Index: binutils-2.22/gas/testsuite/gas/ppc/e6500.d +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ binutils-2.22/gas/testsuite/gas/ppc/e6500.d 2012-07-06 20:41:27.826780001 -0700 +@@ -0,0 +1,75 @@ ++#as: -mppc -me6500 ++#objdump: -dr -Me6500 ++#name: Power E6500 tests ++ ++.*: +file format elf(32)?(64)?-powerpc.* ++ ++Disassembly of section \.text: ++ ++0+00 <start>: ++ 0: 10 01 10 c0 vabsdub v0,v1,v2 ++ 4: 10 01 11 00 vabsduh v0,v1,v2 ++ 8: 10 01 11 40 vabsduw v0,v1,v2 ++ c: 7c 01 10 dc mvidsplt v0,r1,r2 ++ 10: 7c 01 11 1c mviwsplt v0,r1,r2 ++ 14: 7c 00 12 0a lvexbx v0,0,r2 ++ 18: 7c 01 12 0a lvexbx v0,r1,r2 ++ 1c: 7c 00 12 4a lvexhx v0,0,r2 ++ 20: 7c 01 12 4a lvexhx v0,r1,r2 ++ 24: 7c 00 12 8a lvexwx v0,0,r2 ++ 28: 7c 01 12 8a lvexwx v0,r1,r2 ++ 2c: 7c 00 13 0a stvexbx v0,0,r2 ++ 30: 7c 01 13 0a stvexbx v0,r1,r2 ++ 34: 7c 00 13 4a stvexhx v0,0,r2 ++ 38: 7c 01 13 4a stvexhx v0,r1,r2 ++ 3c: 7c 00 13 8a stvexwx v0,0,r2 ++ 40: 7c 01 13 8a stvexwx v0,r1,r2 ++ 44: 7c 00 12 4e lvepx v0,0,r2 ++ 48: 7c 01 12 4e lvepx v0,r1,r2 ++ 4c: 7c 00 12 0e lvepxl v0,0,r2 ++ 50: 7c 01 12 0e lvepxl v0,r1,r2 ++ 54: 7c 00 16 4e stvepx v0,0,r2 ++ 58: 7c 01 16 4e stvepx v0,r1,r2 ++ 5c: 7c 00 16 0e stvepxl v0,0,r2 ++ 60: 7c 01 16 0e stvepxl v0,r1,r2 ++ 64: 7c 00 14 8a lvtlx v0,0,r2 ++ 68: 7c 01 14 8a lvtlx v0,r1,r2 ++ 6c: 7c 00 16 8a lvtlxl v0,0,r2 ++ 70: 7c 01 16 8a lvtlxl v0,r1,r2 ++ 74: 7c 00 14 4a lvtrx v0,0,r2 ++ 78: 7c 01 14 4a lvtrx v0,r1,r2 ++ 7c: 7c 00 16 4a lvtrxl v0,0,r2 ++ 80: 7c 01 16 4a lvtrxl v0,r1,r2 ++ 84: 7c 00 15 8a stvflx v0,0,r2 ++ 88: 7c 01 15 8a stvflx v0,r1,r2 ++ 8c: 7c 00 17 8a stvflxl v0,0,r2 ++ 90: 7c 01 17 8a stvflxl v0,r1,r2 ++ 94: 7c 00 15 4a stvfrx v0,0,r2 ++ 98: 7c 01 15 4a stvfrx v0,r1,r2 ++ 9c: 7c 00 17 4a stvfrxl v0,0,r2 ++ a0: 7c 01 17 4a stvfrxl v0,r1,r2 ++ a4: 7c 00 14 ca lvswx v0,0,r2 ++ a8: 7c 01 14 ca lvswx v0,r1,r2 ++ ac: 7c 00 16 ca lvswxl v0,0,r2 ++ b0: 7c 01 16 ca lvswxl v0,r1,r2 ++ b4: 7c 00 15 ca stvswx v0,0,r2 ++ b8: 7c 01 15 ca stvswx v0,r1,r2 ++ bc: 7c 00 17 ca stvswxl v0,0,r2 ++ c0: 7c 01 17 ca stvswxl v0,r1,r2 ++ c4: 7c 00 16 0a lvsm v0,0,r2 ++ c8: 7c 01 16 0a lvsm v0,r1,r2 ++ cc: 7f 5a d3 78 miso ++ d0: 7c 00 04 ac sync ++ d4: 7c 00 04 ac sync ++ d8: 7c 20 04 ac lwsync ++ dc: 7c 00 04 ac sync ++ e0: 7c 07 04 ac sync 0,7 ++ e4: 7c 28 04 ac sync 1,8 ++ e8: 7c 00 00 c3 dni 0,0 ++ ec: 7f ff 00 c3 dni 31,31 ++ f0: 7c 40 0b 4d dcblq. 2,0,r1 ++ f4: 7c 43 0b 4d dcblq. 2,r3,r1 ++ f8: 7c 40 09 8d icblq. 2,0,r1 ++ fc: 7c 43 09 8d icblq. 2,r3,r1 ++ 100: 7c 10 02 dc mftmr r0,16 ++ 104: 7c 10 03 dc mttmr 16,r0 +Index: binutils-2.22/gas/testsuite/gas/ppc/e6500.s +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ binutils-2.22/gas/testsuite/gas/ppc/e6500.s 2012-07-06 20:41:27.830780001 -0700 +@@ -0,0 +1,69 @@ ++# Power E6500 tests ++ .section ".text" ++start: ++ vabsdub 0, 1, 2 ++ vabsduh 0, 1, 2 ++ vabsduw 0, 1, 2 ++ mvidsplt 0, 1, 2 ++ mviwsplt 0, 1, 2 ++ lvexbx 0, 0, 2 ++ lvexbx 0, 1, 2 ++ lvexhx 0, 0, 2 ++ lvexhx 0, 1, 2 ++ lvexwx 0, 0, 2 ++ lvexwx 0, 1, 2 ++ stvexbx 0, 0, 2 ++ stvexbx 0, 1, 2 ++ stvexhx 0, 0, 2 ++ stvexhx 0, 1, 2 ++ stvexwx 0, 0, 2 ++ stvexwx 0, 1, 2 ++ lvepx 0, 0, 2 ++ lvepx 0, 1, 2 ++ lvepxl 0, 0, 2 ++ lvepxl 0, 1, 2 ++ stvepx 0, 0, 2 ++ stvepx 0, 1, 2 ++ stvepxl 0, 0, 2 ++ stvepxl 0, 1, 2 ++ lvtlx 0, 0, 2 ++ lvtlx 0, 1, 2 ++ lvtlxl 0, 0, 2 ++ lvtlxl 0, 1, 2 ++ lvtrx 0, 0, 2 ++ lvtrx 0, 1, 2 ++ lvtrxl 0, 0, 2 ++ lvtrxl 0, 1, 2 ++ stvflx 0, 0, 2 ++ stvflx 0, 1, 2 ++ stvflxl 0, 0, 2 ++ stvflxl 0, 1, 2 ++ stvfrx 0, 0, 2 ++ stvfrx 0, 1, 2 ++ stvfrxl 0, 0, 2 ++ stvfrxl 0, 1, 2 ++ lvswx 0, 0, 2 ++ lvswx 0, 1, 2 ++ lvswxl 0, 0, 2 ++ lvswxl 0, 1, 2 ++ stvswx 0, 0, 2 ++ stvswx 0, 1, 2 ++ stvswxl 0, 0, 2 ++ stvswxl 0, 1, 2 ++ lvsm 0, 0, 2 ++ lvsm 0, 1, 2 ++ miso ++ sync ++ sync 0,0 ++ sync 1,0 ++ sync 2,0 ++ sync 3,7 ++ sync 3,8 ++ dni 0,0 ++ dni 31,31 ++ dcblq. 2,0,1 ++ dcblq. 2,3,1 ++ icblq. 2,0,1 ++ icblq. 2,3,1 ++ mftmr 0,16 ++ mttmr 16,0 +Index: binutils-2.22/gas/testsuite/gas/ppc/e6500_nop.d +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ binutils-2.22/gas/testsuite/gas/ppc/e6500_nop.d 2012-07-06 20:41:27.830780001 -0700 +@@ -0,0 +1,13 @@ ++#as: -mppc -me6500 ++#objdump: -dr -Me6500 ++#name: Power E6500 nop tests ++ ++.*: +file format elf(32)?(64)?-powerpc.* ++ ++Disassembly of section \.text: ++ ++0+00 <start>: ++ 0: 60 00 00 00 nop ++ 4: 60 00 00 00 nop ++ 8: 60 00 00 00 nop ++ c: 60 00 00 00 nop +Index: binutils-2.22/gas/testsuite/gas/ppc/e6500_nop.s +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ binutils-2.22/gas/testsuite/gas/ppc/e6500_nop.s 2012-07-06 20:41:27.830780001 -0700 +@@ -0,0 +1,5 @@ ++# Power E6500 nop tests ++ .section ".text" ++start: ++ nop ++ .p2align 4,,15 +Index: binutils-2.22/gas/testsuite/gas/ppc/ppc.exp +=================================================================== +--- binutils-2.22.orig/gas/testsuite/gas/ppc/ppc.exp 2010-02-07 17:59:38.000000000 -0800 ++++ binutils-2.22/gas/testsuite/gas/ppc/ppc.exp 2012-07-06 20:41:27.830780001 -0700 +@@ -42,6 +42,10 @@ + run_list_test "range" "-a32" + run_dump_test "ppc750ps" + run_dump_test "e500mc" ++ run_dump_test "e6500" ++ run_dump_test "e500mc64_nop" ++ run_dump_test "e5500_nop" ++ run_dump_test "e6500_nop" + run_dump_test "a2" + run_dump_test "cell" + run_dump_test "common" +Index: binutils-2.22/include/opcode/ppc.h +=================================================================== +--- binutils-2.22.orig/include/opcode/ppc.h 2010-07-02 23:51:53.000000000 -0700 ++++ binutils-2.22/include/opcode/ppc.h 2012-07-06 20:41:27.830780001 -0700 +@@ -1,6 +1,6 @@ + /* ppc.h -- Header file for PowerPC opcode table + Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, +- 2007, 2008, 2009, 2010 Free Software Foundation, Inc. ++ 2007, 2008, 2009, 2010, 2012 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support + + This file is part of GDB, GAS, and the GNU binutils. +@@ -174,6 +174,15 @@ + /* Opcode which is supported by the e500 family */ + #define PPC_OPCODE_E500 0x100000000ull + ++/* Opcode is supported by Extended Altivec Vector Unit */ ++#define PPC_OPCODE_ALTIVEC2 0x200000000ull ++ ++/* Opcode is supported by Power E6500 */ ++#define PPC_OPCODE_E6500 0x400000000ull ++ ++/* Opcode is supported by Thread management APU */ ++#define PPC_OPCODE_TMR 0x800000000ull ++ + /* A macro to extract the major opcode from an instruction. */ + #define PPC_OP(i) (((i) >> 26) & 0x3f) + Index: binutils-2.22/opcodes/ppc-dis.c =================================================================== ---- binutils-2.22.orig/opcodes/ppc-dis.c -+++ binutils-2.22/opcodes/ppc-dis.c -@@ -114,6 +114,12 @@ struct ppc_mopt ppc_opts[] = { +--- binutils-2.22.orig/opcodes/ppc-dis.c 2012-07-06 20:40:40.000000000 -0700 ++++ binutils-2.22/opcodes/ppc-dis.c 2012-07-06 20:41:27.830780001 -0700 +@@ -1,6 +1,6 @@ + /* ppc-dis.c -- Disassemble PowerPC instructions + Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, +- 2008, 2009, 2010 Free Software Foundation, Inc. ++ 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support + + This file is part of the GNU opcodes library. +@@ -114,6 +114,18 @@ | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), 0 }, @@ -107,6 +505,432 @@ Index: binutils-2.22/opcodes/ppc-dis.c + | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 + | PPC_OPCODE_POWER7), + 0 }, ++ { "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL ++ | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI ++ | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC ++ | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4 ++ | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), ++ 0 }, { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI +Index: binutils-2.22/opcodes/ppc-opc.c +=================================================================== +--- binutils-2.22.orig/opcodes/ppc-opc.c 2011-11-21 01:29:40.000000000 -0800 ++++ binutils-2.22/opcodes/ppc-opc.c 2012-07-06 20:41:27.834780001 -0700 +@@ -1,6 +1,6 @@ + /* ppc-opc.c -- PowerPC opcode list + Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004, +- 2005, 2006, 2007, 2008, 2009, 2010, 2011 ++ 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 + Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support + +@@ -53,6 +53,7 @@ + static long extract_boe (unsigned long, ppc_cpu_t, int *); + static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **); + static long extract_fxm (unsigned long, ppc_cpu_t, int *); ++static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **); + static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **); + static long extract_mbe (unsigned long, ppc_cpu_t, int *); + static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **); +@@ -477,6 +478,7 @@ + lower 5 bits are stored in the upper 5 and vice- versa. */ + #define SPR SISIGNOPT + 1 + #define PMR SPR ++#define TMR SPR + #define SPR_MASK (0x3ff << 11) + { 0x3ff, 11, insert_spr, extract_spr, 0 }, + +@@ -499,8 +501,12 @@ + #define T STRM + { 0x3, 21, NULL, NULL, 0 }, + ++ /* The ESYNC field in an X (sync) form instruction. */ ++#define ESYNC STRM + 1 ++ { 0xf, 16, insert_ls, NULL, PPC_OPERAND_OPTIONAL }, ++ + /* The SV field in a POWER SC form instruction. */ +-#define SV STRM + 1 ++#define SV ESYNC + 1 + { 0x3fff, 2, NULL, NULL, 0 }, + + /* The TBR field in an XFX form instruction. This is like the SPR +@@ -542,6 +548,7 @@ + + /* The UIMM field in a VX form instruction. */ + #define UIMM SIMM + 1 ++#define DCTL UIMM + { 0x1f, 16, NULL, NULL, 0 }, + + /* The SHB field in a VA form instruction. */ +@@ -1027,6 +1034,32 @@ + return mask; + } + ++/* The LS field in a sync instruction that accepts 2 operands ++ Values 2 and 3 are reserved, ++ must be treated as 0 for future compatibility ++ Values 0 and 1 can be accepted, if field ESYNC is zero ++ Otherwise L = complement of ESYNC-bit2 (1<<18) */ ++ ++static unsigned long ++insert_ls (unsigned long insn, ++ long value, ++ ppc_cpu_t dialect ATTRIBUTE_UNUSED, ++ const char **errmsg ATTRIBUTE_UNUSED) ++{ ++ unsigned long ls; ++ ++ ls = (insn >> 21) & 0x03; ++ if (value == 0) ++ { ++ if (ls > 1) ++ return insn & ~(0x3 << 21); ++ return insn; ++ } ++ if ((value & 0x2) != 0) ++ return (insn & ~(0x3 << 21)) | ((value & 0xf) << 16); ++ return (insn & ~(0x3 << 21)) | (0x1 << 21) | ((value & 0xf) << 16); ++} ++ + /* The MB and ME fields in an M form instruction expressed as a single + operand which is itself a bitmask. The extraction function always + marks it as invalid, since we never want to recognize an +@@ -1795,6 +1828,9 @@ + /* An X form sync instruction with everything filled in except the LS field. */ + #define XSYNC_MASK (0xff9fffff) + ++/* An X form sync instruction with everything filled in except the L and E fields. */ ++#define XSYNCLE_MASK (0xff90ffff) ++ + /* An X_MASK, but with the EH bit clear. */ + #define XEH_MASK (X_MASK & ~((unsigned long )1)) + +@@ -1989,6 +2025,7 @@ + #define PPC860 PPC + #define PPCPS PPC_OPCODE_PPCPS + #define PPCVEC PPC_OPCODE_ALTIVEC ++#define PPCVEC2 PPC_OPCODE_ALTIVEC2 + #define PPCVSX PPC_OPCODE_VSX + #define POWER PPC_OPCODE_POWER + #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 +@@ -2007,6 +2044,7 @@ + #define PPCEFS PPC_OPCODE_EFS + #define PPCBRLK PPC_OPCODE_BRLOCK + #define PPCPMR PPC_OPCODE_PMR ++#define PPCTMR PPC_OPCODE_TMR + #define PPCCHLK PPC_OPCODE_CACHELCK + #define PPCRFMCI PPC_OPCODE_RFMCI + #define E500MC PPC_OPCODE_E500MC +@@ -2014,6 +2052,7 @@ + #define TITAN PPC_OPCODE_TITAN + #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN + #define E500 PPC_OPCODE_E500 ++#define E6500 PPC_OPCODE_E6500 + + /* The opcode table. + +@@ -2179,12 +2218,14 @@ + {"machhwsu", XO (4, 76,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, + {"machhwsu.", XO (4, 76,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, + {"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, ++{"vabsdub", VX (4, 192), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, + {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, + {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, + {"machhws", XO (4, 108,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, + {"machhws.", XO (4, 108,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, + {"nmachhws", XO (4, 110,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, + {"nmachhws.", XO (4, 110,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, ++{"vabsduh", VX (4, 256), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, + {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, + {"vslb", VX (4, 260), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, + {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +@@ -2197,6 +2238,7 @@ + {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, + {"macchwu", XO (4, 140,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, + {"macchwu.", XO (4, 140,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, ++{"vabsduw", VX (4, 320), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, + {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, + {"vslh", VX (4, 324), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, + {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +@@ -3680,6 +3722,8 @@ + + {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}}, + ++{"dni", XRC(31,97,1), XRB_MASK, E6500, PPCNONE, {DUI, DCTL}}, ++ + {"lvx", X(31,103), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, + {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +@@ -3689,6 +3733,8 @@ + {"mul", XO(31,107,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, + {"mul.", XO(31,107,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, + ++{"mvidsplt", X(31,110), X_MASK, PPCVEC2, PPCNONE, {VD, RA, RB}}, ++ + {"mtsrdin", X(31,114), XRA_MASK, PPC64, PPCNONE, {RS, RB}}, + + {"lharx", X(31,116), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}}, +@@ -3723,7 +3769,9 @@ + {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, + {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, + +-{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, ++{"mviwsplt", X(31,142), X_MASK, PPCVEC2, PPCNONE, {VD, RA, RB}}, ++ ++{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, + + {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, PPCNONE, {RS}}, + {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}}, +@@ -3760,7 +3808,7 @@ + {"stvehx", X(31,167), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, + {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +-{"dcbtlse", X(31,174), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, ++{"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, + + {"mtmsrd", X(31,178), XRLARB_MASK, PPC64, PPCNONE, {RS, A_L}}, + +@@ -3778,6 +3826,8 @@ + + {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, PPCNONE, {RA, RS}}, + ++{"icblq.", XRC(31,198,1), X_MASK, E6500, PPCNONE, {CT, RA0, RB}}, ++ + {"stvewx", X(31,199), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, + {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +@@ -3855,8 +3905,12 @@ + {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}}, + {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, PPCNONE, {RS, RA}}, + ++{"lvexbx", X(31,261), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, ++ + {"icbt", X(31,262), XRT_MASK, PPC403, PPCNONE, {RA, RB}}, + ++{"lvepxl", X(31,263), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, ++ + {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + {"doz", XO(31,264,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, + {"doz.", XO(31,264,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, +@@ -3890,6 +3944,9 @@ + + {"mfdcrux", X(31,291), X_MASK, PPC464, PPCNONE, {RS, RA}}, + ++{"lvexhx", X(31,293), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, ++{"lvepx", X(31,295), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, ++ + {"tlbie", X(31,306), XRTLRA_MASK, PPC, TITAN, {RB, L}}, + {"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}}, + +@@ -3941,6 +3998,8 @@ + {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN, {RT, SPR}}, + {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, PPCNONE, {RT, SPR}}, + ++{"lvexwx", X(31,325), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, ++ + {"dcread", X(31,326), X_MASK, PPC476|TITAN, PPCNONE, {RT, RA, RB}}, + + {"div", XO(31,331,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, +@@ -3949,6 +4008,7 @@ + {"lxvdsx", X(31,332), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, + + {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, PPCNONE, {RT, PMR}}, ++{"mftmr", X(31,366), X_MASK, PPCTMR|E6500, PPCNONE, {RT, TMR}}, + + {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, PPCNONE, {RT}}, + {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, PPCNONE, {RT}}, +@@ -4179,6 +4239,8 @@ + {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}}, + {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, PPCNONE, {RA, RS}}, + ++{"stvexbx", X(31,389), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, ++ + {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}}, + {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +@@ -4187,7 +4249,7 @@ + {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, + {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, + +-{"dcblce", X(31,398), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, ++{"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, + + {"slbmte", X(31,402), XRA_MASK, PPC64, PPCNONE, {RS, RB}}, + +@@ -4203,6 +4265,10 @@ + + {"mtdcrux", X(31,419), X_MASK, PPC464, PPCNONE, {RA, RS}}, + ++{"stvexhx", X(31,421), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, ++ ++{"dcblq.", XRC(31,422,1), X_MASK, E6500, PPCNONE, {CT, RA0, RB}}, ++ + {"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, + {"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, + {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +@@ -4216,6 +4282,8 @@ + + {"mdors", 0x7f9ce378, 0xffffffff, E500MC, PPCNONE, {0}}, + ++{"miso", 0x7f5ad378, 0xffffffff, E6500, PPCNONE, {0}}, ++ + {"mr", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}}, + {"or", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, + {"mr.", XRC(31,444,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}}, +@@ -4258,6 +4326,8 @@ + {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN, {SPR, RS}}, + {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, PPCNONE, {SPR, RS}}, + ++{"stvexwx", X(31,453), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, ++ + {"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}}, + {"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, PPCNONE, {CT}}, + +@@ -4268,6 +4338,7 @@ + {"divwu.", XO(31,459,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, + + {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, PPCNONE, {PMR, RS}}, ++{"mttmr", X(31,494), X_MASK, PPCTMR|E6500, PPCNONE, {TMR, RS}}, + + {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, PPCNONE, {RS}}, + {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, PPCNONE, {RS}}, +@@ -4453,7 +4524,7 @@ + {"divw", XO(31,491,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, + {"divw.", XO(31,491,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, + +-{"icbtlse", X(31,494), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, ++{"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, + + {"slbia", X(31,498), 0xffffffff, PPC64, PPCNONE, {0}}, + +@@ -4512,6 +4583,8 @@ + + {"lhdx", X(31,547), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, + ++{"lvtrx", X(31,549), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, ++ + {"bbelr", X(31,550), X_MASK, PPCBRLK, PPCNONE, {0}}, + + {"lvrx", X(31,551), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, +@@ -4528,6 +4601,8 @@ + + {"lwdx", X(31,579), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, + ++{"lvtlx", X(31,581), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, ++ + {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + + {"lxsdx", X(31,588), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, +@@ -4539,9 +4614,10 @@ + + {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}}, + {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}}, ++{"sync", X(31,598), XSYNCLE_MASK,E6500, PPCNONE, {LS, ESYNC}}, + {"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}}, + {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}}, +-{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, PPCNONE, {0}}, ++{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}}, + {"lwsync", X(31,598), 0xffffffff, E500, PPCNONE, {0}}, + {"dcs", X(31,598), 0xffffffff, PWRCOM, PPCNONE, {0}}, + +@@ -4552,6 +4628,8 @@ + + {"lddx", X(31,611), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, + ++{"lvswx", X(31,613), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, ++ + {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + + {"nego", XO(31,104,1,0), XORB_MASK, COM, PPCNONE, {RT, RA}}, +@@ -4601,6 +4679,8 @@ + + {"sthdx", X(31,675), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, + ++{"stvfrx", X(31,677), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, ++ + {"stvrx", X(31,679), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, + {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +@@ -4613,6 +4693,8 @@ + + {"stwdx", X(31,707), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, + ++{"stvflx", X(31,709), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, ++ + {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + + {"stxsdx", X(31,716), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}}, +@@ -4645,6 +4727,8 @@ + + {"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, + ++{"stvswx", X(31,741), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, ++ + {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + + {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +@@ -4673,6 +4757,8 @@ + {"srliq", XRC(31,760,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, + {"srliq.", XRC(31,760,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, + ++{"lvsm", X(31,773), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, ++{"stvepxl", X(31,775), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, + {"lvlxl", X(31,775), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, + {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, + +@@ -4705,6 +4791,8 @@ + + {"lfddx", X(31,803), X_MASK, E500MC, PPCNONE, {FRT, RA, RB}}, + ++{"lvtrxl", X(31,805), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, ++{"stvepx", X(31,807), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, + {"lvrxl", X(31,807), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, + + {"rac", X(31,818), X_MASK, M601, PPCNONE, {RT, RA, RB}}, +@@ -4725,6 +4813,8 @@ + {"sradi", XS(31,413,0), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}}, + {"sradi.", XS(31,413,1), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}}, + ++{"lvtlxl", X(31,837), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, ++ + {"divo", XO(31,331,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, + {"divo.", XO(31,331,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, + +@@ -4743,6 +4833,8 @@ + + {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, RA0, RB}}, + ++{"lvswxl", X(31,869), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, ++ + {"abso", XO(31,360,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}}, + {"abso.", XO(31,360,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}}, + +@@ -4788,6 +4880,8 @@ + + {"stfddx", X(31,931), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}}, + ++{"stvfrxl", X(31,933), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, ++ + {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, PPCNONE, {RA0, RB}}, + {"wclrall", X(31,934), XRARB_MASK, PPCA2, PPCNONE, {L}}, + {"wclr", X(31,934), X_MASK, PPCA2, PPCNONE, {L, RA0, RB}}, +@@ -4816,6 +4910,8 @@ + {"extsb", XRC(31,954,0), XRB_MASK, PPC, PPCNONE, {RA, RS}}, + {"extsb.", XRC(31,954,1), XRB_MASK, PPC, PPCNONE, {RA, RS}}, + ++{"stvflxl", X(31,965), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, ++ + {"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}}, + {"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, PPCNONE, {CT}}, + +@@ -4843,6 +4939,8 @@ + + {"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}}, + ++{"stvswxl", X(31,997), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, ++ + {"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, PPCNONE, {RA, RB}}, + + {"nabso", XO(31,488,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}}, |