qemu-native/powerpc: add qemu 0.12.4 powerpc support

In order to force 0.12.4 to allow a powerpc system boot, we need
a patch to qemu, and a new powerpc (not ppc) ROM.

This configuration supports non-graphical booting only, since the
ROM does not have support to pass a graphics device via the
device tree yet.

Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>

3 files changed, 144 insertions, 1 deletions

diff --git a/meta/packages/qemu/qemu-0.12.4/powerpc_rom.bin b/meta/packages/qemu/qemu-0.12.4/powerpc_rom.bin
new file mode 100644
index 0000000000..c4044296c5
--- /dev/null
+++ b/meta/packages/qemu/qemu-0.12.4/powerpc_rom.bin
diff --git a/meta/packages/qemu/qemu-0.12.4/qemu-ppc-hack.patch b/meta/packages/qemu/qemu-0.12.4/qemu-ppc-hack.patch
new file mode 100644
index 0000000000..3ed227ec35
--- /dev/null
+++ b/meta/packages/qemu/qemu-0.12.4/qemu-ppc-hack.patch
@@ -0,0 +1,136 @@
+Quick fixes to get the ppc system model to boot a 603e based

+kernel.

+

+diff --git a/hw/m48t59.c b/hw/m48t59.c

+index ce38f8b..d99054f 100644

+--- a/hw/m48t59.c

++++ b/hw/m48t59.c

+@@ -50,6 +50,7 @@

+  */

+ 

+ struct m48t59_t {

++    SysBusDevice busdev;

+     /* Model parameters */

+     uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59

+     /* Hardware parameters */

+@@ -74,11 +75,6 @@ typedef struct M48t59ISAState {

+     m48t59_t state;

+ } M48t59ISAState;

+ 

+-typedef struct M48t59SysBusState {

+-    SysBusDevice busdev;

+-    m48t59_t state;

+-} M48t59SysBusState;

+-

+ /* Fake timer functions */

+ 

+ /* Alarm management */

+@@ -629,8 +625,7 @@ static void m48t59_reset_isa(DeviceState *d)

+ 

+ static void m48t59_reset_sysbus(DeviceState *d)

+ {

+-    M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev);

+-    m48t59_t *NVRAM = &sys->state;

++    m48t59_t *NVRAM = container_of(d, m48t59_t, busdev.qdev);

+ 

+     m48t59_reset_common(NVRAM);

+ }

+@@ -642,7 +637,7 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,

+ {

+     DeviceState *dev;

+     SysBusDevice *s;

+-    M48t59SysBusState *d;

++    m48t59_t *d;

+ 

+     dev = qdev_create(NULL, "m48t59");

+     qdev_prop_set_uint32(dev, "type", type);

+@@ -659,9 +654,9 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,

+         sysbus_mmio_map(s, 0, mem_base);

+     }

+ 

+-    d = FROM_SYSBUS(M48t59SysBusState, s);

++    d = FROM_SYSBUS(m48t59_t, s);

+ 

+-    return &d->state;

++    return d;

+ }

+ 

+ m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)

+@@ -711,8 +706,7 @@ static int m48t59_init_isa1(ISADevice *dev)

+ 

+ static int m48t59_init1(SysBusDevice *dev)

+ {

+-    M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev);

+-    m48t59_t *s = &d->state;

++    m48t59_t *s = FROM_SYSBUS(m48t59_t, dev);

+     int mem_index;

+ 

+     sysbus_init_irq(dev, &s->IRQ);

+@@ -741,12 +735,12 @@ static ISADeviceInfo m48t59_isa_info = {

+ static SysBusDeviceInfo m48t59_info = {

+     .init = m48t59_init1,

+     .qdev.name  = "m48t59",

+-    .qdev.size = sizeof(M48t59SysBusState),

++    .qdev.size  = sizeof(m48t59_t),

+     .qdev.reset = m48t59_reset_sysbus,

+     .qdev.props = (Property[]) {

+-        DEFINE_PROP_UINT32("size",    M48t59SysBusState, state.size,    -1),

+-        DEFINE_PROP_UINT32("type",    M48t59SysBusState, state.type,    -1),

+-        DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base,  0),

++        DEFINE_PROP_UINT32("size",    m48t59_t, size,    -1),

++        DEFINE_PROP_UINT32("type",    m48t59_t, type,    -1),

++        DEFINE_PROP_HEX32( "io_base", m48t59_t, io_base,  0),

+         DEFINE_PROP_END_OF_LIST(),

+     }

+ };

+diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c

+index eb758f2..08db51b 100644

+--- a/hw/ppc_prep.c

++++ b/hw/ppc_prep.c

+@@ -73,7 +73,7 @@ qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)

+ /* Constants for devices init */

+ static const int ide_iobase[2] = { 0x1f0, 0x170 };

+ static const int ide_iobase2[2] = { 0x3f6, 0x376 };

+-static const int ide_irq[2] = { 13, 13 };

++static const int ide_irq[2] = { 13, 14 };

+ 

+ #define NE2000_NB_MAX 6

+ 

+@@ -620,9 +620,6 @@ static void ppc_prep_init (ram_addr_t ram_size,

+     if (filename) {

+         qemu_free(filename);

+     }

+-    if (env->nip < 0xFFF80000 && bios_size < 0x00100000) {

+-        hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n");

+-    }

+ 

+     if (linux_boot) {

+         kernel_base = KERNEL_LOAD_ADDR;

+diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c

+index e3bd29c..1cb2e07 100644

+--- a/target-ppc/op_helper.c

++++ b/target-ppc/op_helper.c

+@@ -1646,20 +1646,20 @@ static inline void do_rfi(target_ulong nip, target_ulong msr,

+ void helper_rfi (void)

+ {

+     do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],

+-           ~((target_ulong)0x0), 1);

++           ~((target_ulong)0xFFFF0000), 1);

+ }

+ 

+ #if defined(TARGET_PPC64)

+ void helper_rfid (void)

+ {

+     do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],

+-           ~((target_ulong)0x0), 0);

++           ~((target_ulong)0xFFFF0000), 0);

+ }

+ 

+ void helper_hrfid (void)

+ {

+     do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],

+-           ~((target_ulong)0x0), 0);

++           ~((target_ulong)0xFFFF0000), 0);

+ }

+ #endif

+ #endif

diff --git a/meta/packages/qemu/qemu_0.12.4.bb b/meta/packages/qemu/qemu_0.12.4.bb
index 7d158bf863..c253b03a2f 100644
--- a/meta/packages/qemu/qemu_0.12.4.bb
+++ b/meta/packages/qemu/qemu_0.12.4.bb
@@ -15,6 +15,13 @@ SRC_URI = "\
     file://qemugl-allow-glxcontext-release.patch \
     file://linker-flags.patch \
     file://init-info.patch \
-    file://qemu-vmware-vga-depth.patch"
+    file://qemu-vmware-vga-depth.patch \
+    file://qemu-ppc-hack.patch \
+    file://powerpc_rom.bin"
+
+do_install_append () {
+        install -d ${D}${datadir}/qemu
+        install -m 0755 ${WORKDIR}/powerpc_rom.bin ${D}${datadir}/qemu
+}
 
 S = "${WORKDIR}/qemu-${PV}"