Not all QEMU machines (outside of those available in OE-Core) are
capable of using the virtio-rng-pci device due to various machine models
not having a pci/virtio bus. This makes it such that the use of the
'-device virtio-rng-pci' flag to QEMU is machine specific.

This patch removes the general addition of the flag to all runqemu
targets and adds the flag into the QB_OPT_APPEND for all the qemu*
machines in OE-Core that support its use (which is all of them).

Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Signed-off-by: Ross Burton <ross.burton@intel.com>

This causes the default timeout to be set to infinity, it will still report out
every 5000 milliseconds

Signed-off-by: Saul Wold <sgw@linux.intel.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>

All qemu boards should be able to boot by runqemu.

Signed-off-by: Robert Yang <liezhi.yang@windriver.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>

Add qemuboot-mips.inc to reduce duplicated code, the various mips bsps
which can be boot by runqemu can require qemuboot-mips.inc

Signed-off-by: Robert Yang <liezhi.yang@windriver.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>

Add qemuboot-x86.inc to reduce duplicated code, the x86/x86_64 bsps
which can be boot by runqemu can require qemuboot-x86.inc.

Signed-off-by: Robert Yang <liezhi.yang@windriver.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>

QEMU usermode doesn't support n32 binaries, erroring with "Invalid
ELF image for this architecture".

Signed-off-by: Alexander Kanavin <alexander.kanavin@linux.intel.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>

The core emulated by default by qemu-mips(el) just crashes with
illegal instruction when encountering DSP and/or MIPS16e
instructions - we have to specify a CPU that supports the extra
instructions.

This is an issue when generating a rootfs and e.g. running some
of the package postinstall scriptlets.

The patch to qemu to add 24KEc as a CPU has been accepted
upstream, so let's use that CPU here as well as needed.

Signed-off-by: André Draszik <git@andred.net>
Signed-off-by: Ross Burton <ross.burton@intel.com>

Currently the -mcpu parameter is not passed to cross gcc when assembling
kernel .S file, the implicit -mcpu option that defaults to the latest
server cpu might casuse incorrect assembling.

A existent case is that wait instruction of ppce500mc is incorrectly assembled
to power9 version with default -mcpu setting, accordingly kernel boot calltrace
happend when wait instruction is executed on ppce500mc targets.

Signed-off-by: Zhenhua Luo <zhenhua.luo@nxp.com>
Signed-off-by: Ross Burton <ross.burton@intel.com>

- add 24kc big and little endian, which is based on mips32r2 w/o FPU
- add 24kec which is 24kc + DSP
- both can have the MIPS16e ASE enabled in their tunes

Signed-off-by: André Draszik <adraszik@tycoint.com>
Signed-off-by: Ross Burton <ross.burton@intel.com>

The MIPS16e instruction set still has to be enabled by setting
MIPS_INSTRUCTION_SET = 'mips16e'
in e.g. distro.conf and can be disabled on a per-recipe basis as
needed.

This is a similar approach as is available on ARM for Thumb support.

Note that contrary to the ARM Thumb support in OE, we do add a new
OVERRIDE (mips16e), as there are some recipes in OE that need to be
compiled slightly differently if mips16e mode is requested.

Signed-off-by: André Draszik <adraszik@tycoint.com>
Signed-off-by: Ross Burton <ross.burton@intel.com>