Patch to add HXD8 support Index: u-boot/Makefile =================================================================== --- u-boot.orig/Makefile +++ u-boot/Makefile @@ -2026,6 +2026,9 @@ qt2410_config : unconfig @./mkconfig $(@:_config=) arm arm920t qt2410 NULL s3c24x0 +hxd8_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t hxd8 NULL s3c24x0 + scb9328_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t scb9328 NULL imx Index: u-boot/board/hxd8/Makefile =================================================================== --- /dev/null +++ u-boot/board/hxd8/Makefile @@ -0,0 +1,65 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := hxd8.o udc.o pcf50606.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +all: $(LIB) lowevel_foo.bin + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +lowlevel_foo.o: lowlevel_foo.S + $(CC) -c -DTEXT_BASE=0x33F80000 -march=armv4 \ + -o lowlevel_foo.o lowlevel_foo.S + +lowlevel_foo: lowlevel_foo.o lowlevel_init.o lowlevel_foo.lds + $(LD) -T ./lowlevel_foo.lds -Ttext 0x33f80000 -Bstatic \ + lowlevel_init.o lowlevel_foo.o -o lowlevel_foo + +lowevel_foo.bin: lowlevel_foo + $(CROSS_COMPILE)objcopy --gap-fill=0xff -O binary \ + lowlevel_foo lowlevel_foo.bin + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### Index: u-boot/board/hxd8/hxd8.c =================================================================== --- /dev/null +++ u-boot/board/hxd8/hxd8.c @@ -0,0 +1,189 @@ +/* + * (C) Copyright 2007 by Openmoko, Inc. + * Author: Harald Welte + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define FCLK_SPEED 1 + +#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ +#define M_MDIV 0xC3 +#define M_PDIV 0x4 +#define M_SDIV 0x1 +#elif FCLK_SPEED==1 +#if 0 +#define M_MDIV 0x6e /* Fout = 399.65MHz */ +#define M_PDIV 0x3 +#define M_SDIV 0x1 +#else +#define M_MDIV 0x61 /* Fout = 296.35MHz due to wrong PLL capacitors */ +#define M_PDIV 0x1 +#define M_SDIV 0x2 +#endif +#endif + +#define USB_CLOCK 1 + +#if USB_CLOCK==0 +#define U_M_MDIV 0xA1 +#define U_M_PDIV 0x3 +#define U_M_SDIV 0x1 +#elif USB_CLOCK==1 +#define U_M_MDIV 0x3c +#define U_M_PDIV 0x4 +#define U_M_SDIV 0x2 +#endif + +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init (void) +{ + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + /* to reduce PLL lock time, adjust the LOCKTIME register */ + clk_power->LOCKTIME = 0xFFFFFF; + + /* configure MPLL */ + clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + + /* some delay between MPLL and UPLL */ + delay (4000); + + /* configure UPLL */ + clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); + + /* some delay between MPLL and UPLL */ + delay (8000); + + /* set up the I/O ports */ + gpio->GPACON = 0x005E0FFE; + gpio->GPADAT = 0x0001C000; + gpio->GPBCON = 0x00045542; + gpio->GPBUP = 0x000007FF; + gpio->GPCCON = 0xAAAA02A9; + gpio->GPCUP = 0x0000FFFF; + gpio->GPDCON = 0xAAAAAAAA; + gpio->GPDUP = 0x0000FFFF; + gpio->GPECON = 0xAAAAAAAA; + gpio->GPEUP = 0x0000FFFF; + gpio->GPFCON = 0x0000AAA9; + gpio->GPFUP = 0x000000FF; + gpio->GPGCON = 0x027D0316; + gpio->GPGUP = 0x0000FFFF; + gpio->GPHCON = 0x0014AAAA; + gpio->GPHUP = 0x000007FF; + gpio->GPJCON = 0x00000000; + + /* USB CHG enable */ + gpio->GPGDAT |= ( 1 << 11); +#if 0 + /* USB Device Part */ + /*GPGCON is reset for USB Device */ + gpio->GPGCON = (gpio->GPGCON & ~(3 << 24)) | (1 << 24); /* Output Mode */ + gpio->GPGUP = gpio->GPGUP | ( 1 << 12); /* Pull up disable */ + + gpio->GPGDAT |= ( 1 << 12); + gpio->GPGDAT &= ~( 1 << 12); + udelay(20000); + gpio->GPGDAT |= ( 1 << 12); +#endif + + /* arch number of SMDK2440-Board */ + gd->bd->bi_arch_number = MACH_TYPE_HXD8; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x30000100; + + icache_enable(); + dcache_enable(); + + return 0; +} + +void board_video_init(GraphicDevice *pGD) +{ + S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD(); + + lcd->LCDCON1 = 0x0000057b; + lcd->LCDCON2 = 0x0143c049; + lcd->LCDCON3 = 0x0009df01; + lcd->LCDCON4 = 0x00000028; + lcd->LCDCON5 = 0x00000b08; + + lcd->TPAL = 0x01202020; + + //lcd->LCDCON5 |= (0x01 << 3); +} + +int board_late_init(void) +{ + /* Initialize the Power Management Unit with a safe register set */ + pcf50606_init(); + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +u_int32_t get_board_rev(void) +{ + return 0x00000110; +} + +/* The sum of all part_size[]s must equal to the NAND size, i.e., 0x4000000. + "initrd" is sized such that it can hold two uncompressed 16 bit 640*480 + images: 640*480*2*2 = 1228800 < 1245184. */ + +unsigned int dynpart_size[] = { + CFG_UBOOT_SIZE, 0x20000, 0x200000, 0xa0000, 0x3fd00000, 0 }; +char *dynpart_names[] = { + "u-boot", "u-boot_env", "kernel", "splash", "rootfs", NULL }; + Index: u-boot/board/hxd8/lowlevel_init.S =================================================================== --- /dev/null +++ u-boot/board/hxd8/lowlevel_init.S @@ -0,0 +1,171 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * + * Modified for the FIC HXD8 by Harald Welte + * (C) Copyright 2007 by Openmoko, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + + +/* some parameters for the board */ + +/* + * + * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S + * + * Copyright (C) 2002 Samsung Electronics SW.LEE + * + */ + +#define BWSCON 0x48000000 + +/* BWSCON */ +#define DW8 (0x0) +#define DW16 (0x1) +#define DW32 (0x2) +#define WAIT (0x1<<2) +#define UBLB (0x1<<3) + +#define B1_BWSCON (DW32) +#define B2_BWSCON (DW16) +#define B3_BWSCON (DW16 + WAIT + UBLB) +#define B4_BWSCON (DW16) +#define B5_BWSCON (DW16) +#define B6_BWSCON (DW32) +#define B7_BWSCON (DW32) + +/* BANK0CON */ +#define B0_Tacs 0x0 /* 0clk */ +#define B0_Tcos 0x0 /* 0clk */ +#define B0_Tacc 0x7 /* 14clk */ +#define B0_Tcoh 0x0 /* 0clk */ +#define B0_Tah 0x0 /* 0clk */ +#define B0_Tacp 0x0 +#define B0_PMC 0x0 /* normal */ + +/* BANK1CON */ +#define B1_Tacs 0x0 /* 0clk */ +#define B1_Tcos 0x0 /* 0clk */ +#define B1_Tacc 0x7 /* 14clk */ +#define B1_Tcoh 0x0 /* 0clk */ +#define B1_Tah 0x0 /* 0clk */ +#define B1_Tacp 0x0 +#define B1_PMC 0x0 + +#define B2_Tacs 0x0 +#define B2_Tcos 0x0 +#define B2_Tacc 0x7 +#define B2_Tcoh 0x0 +#define B2_Tah 0x0 +#define B2_Tacp 0x0 +#define B2_PMC 0x0 + +#define B3_Tacs 0x0 /* 0clk */ +#define B3_Tcos 0x3 /* 4clk */ +#define B3_Tacc 0x7 /* 14clk */ +#define B3_Tcoh 0x1 /* 1clk */ +#define B3_Tah 0x0 /* 0clk */ +#define B3_Tacp 0x3 /* 6clk */ +#define B3_PMC 0x0 /* normal */ + +#define B4_Tacs 0x0 /* 0clk */ +#define B4_Tcos 0x0 /* 0clk */ +#define B4_Tacc 0x7 /* 14clk */ +#define B4_Tcoh 0x0 /* 0clk */ +#define B4_Tah 0x0 /* 0clk */ +#define B4_Tacp 0x0 +#define B4_PMC 0x0 /* normal */ + +#define B5_Tacs 0x0 /* 0clk */ +#define B5_Tcos 0x0 /* 0clk */ +#define B5_Tacc 0x7 /* 14clk */ +#define B5_Tcoh 0x0 /* 0clk */ +#define B5_Tah 0x0 /* 0clk */ +#define B5_Tacp 0x0 +#define B5_PMC 0x0 /* normal */ + +#define B6_MT 0x3 /* SDRAM */ +#define B6_Trcd 0x1 /* 3clk */ +#define B6_SCAN 0x2 /* 10bit */ + +#define B7_MT 0x3 /* SDRAM */ +#define B7_Trcd 0x1 /* 3clk */ +#define B7_SCAN 0x1 /* 9bit */ + +/* REFRESH parameter */ +#define REFEN 0x1 /* Refresh enable */ +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ +#define Trp 0x1 /* 3clk */ +#define Trc 0x3 /* 7clk */ +#define Tchr 0x2 /* 3clk */ +#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ +/**************************************/ + +_TEXT_BASE: + .word TEXT_BASE + +.globl lowlevel_init +lowlevel_init: + /* memory control configuration */ + /* make r0 relative the current location so that it */ + /* reads SMRDATA out of FLASH rather than memory ! */ + ldr r0, =SMRDATA + ldr r1, _TEXT_BASE + sub r0, r0, r1 + ldr r1, =BWSCON /* Bus Width Status Controller */ + add r2, r0, #13*4 +0: + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r2, r0 + bne 0b + + /* setup asynchronous bus mode */ + mrc p15, 0, r1 ,c1 ,c0, 0 + orr r1, r1, #0xc0000000 + mcr p15, 0, r1, c1, c0, 0 + + /* everything is fine now */ + mov pc, lr + + .ltorg +/* the literal pools origin */ + +SMRDATA: + .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) + .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) + .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) + .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) + .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) + .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) + .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) + .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) + .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) + .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) + .word 0x32 + .word 0x30 + .word 0x30 Index: u-boot/include/configs/hxd8.h =================================================================== --- /dev/null +++ u-boot/include/configs/hxd8.h @@ -0,0 +1,277 @@ +/* + * (C) Copyright 2007 Openmoko, Inc. + * Author: Harald Welte + * + * Configuation settings for the FIC HXD8 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* we want to be able to start u-boot directly from within NAND flash */ +#define CONFIG_LL_INIT_NAND_ONLY +#define CONFIG_S3C2410_NAND_BOOT 1 +#define CONFIG_S3C2410_NAND_SKIP_BAD 1 + +#define CFG_UBOOT_SIZE 0x40000 /* size of u-boot, for NAND loading */ + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2440 SoC */ +#define CONFIG_SMDK2440 1 /* on a SAMSUNG SMDK2440 Board */ +#define CONFIG_HXD8 1 /* on a FIC HXD8 Board */ + +/* input clock of PLL */ +#define CONFIG_SYS_CLK_FREQ 16934400/* the HXD8 has this input clock */ + + +#define USE_920T_MMU 1 +#define CONFIG_USE_IRQ 1 + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 2048*1024) + /* >> CFG_VIDEO_LOGO_MAX_SIZE */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL3 1 /* we use SERIAL 3 on HXD8 */ + +/************************************************************ + * RTC + ************************************************************/ +#define CONFIG_RTC_S3C24X0 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +/*********************************************************** + * Command definition + ***********************************************************/ +#define CONFIG_COMMANDS (\ + CFG_CMD_BDI | \ + CFG_CMD_LOADS | \ + CFG_CMD_LAODB | \ + CFG_CMD_IMI | \ + CFG_CMD_CACHE | \ + CFG_CMD_MEMORY | \ + CFG_CMD_ENV | \ + /* CFG_CMD_IRQ | */ \ + CFG_CMD_BOOTD | \ + CFG_CMD_CONSOLE | \ + /* CFG_CMD_BMP | */ \ + CFG_CMD_ASKENV | \ + CFG_CMD_RUN | \ + CFG_CMD_ECHO | \ + CFG_CMD_I2C | \ + CFG_CMD_REGINFO | \ + CFG_CMD_IMMAP | \ + CFG_CMD_DATE | \ + CFG_CMD_AUTOSCRIPT | \ + CFG_CMD_BSP | \ + CFG_CMD_ELF | \ + CFG_CMD_MISC | \ + /* CFG_CMD_USB | */ \ + CFG_CMD_JFFS2 | \ + CFG_CMD_DIAG | \ + /* CFG_CMD_HWFLOW | */ \ + CFG_CMD_SAVES | \ + CFG_CMD_NAND | \ + CFG_CMD_PORTIO | \ + CFG_CMD_MMC | \ + CFG_CMD_FAT | \ + CFG_CMD_EXT2 | \ + 0) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "" +#define CONFIG_BOOTCOMMAND "setenv bootargs ${bootargs_base} ${mtdparts}; nand read.e 0x32000000 kernel; bootm 0x32000000" + +#define CONFIG_DOS_PARTITION 1 + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* what's this ? it's not used anywhere */ +#define CONFIG_KGDB_SER_INDEX 3 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "HXD8 # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 64 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x30000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x33000000 /* default load address */ + +/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ +/* it to wrap 100 times (total 1562500) to get 1 sec. */ +#define CFG_HZ 1562500 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (512*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +#if 0 +#define CONFIG_USB_OHCI 1 +#endif + +#if 1 +#define CONFIG_USB_DEVICE 1 +#define CONFIG_USB_TTY 1 +#define CFG_CONSOLE_IS_IN_ENV 1 +#define CONFIG_USBD_VENDORID 0x1457 /* Linux/NetChip */ +#define CONFIG_USBD_PRODUCTID_GSERIAL 0x5120 /* gserial */ +#define CONFIG_USBD_PRODUCTID_CDCACM 0x511a /* CDC ACM */ +#define CONFIG_USBD_MANUFACTURER "Openmoko, Inc" +#define CONFIG_USBD_PRODUCT_NAME "HXD8 Bootloader " U_BOOT_VERSION +#define CONFIG_USBD_DFU 1 +#define CONFIG_USBD_DFU_XFER_SIZE 4096 /* 0x4000 */ +#define CONFIG_USBD_DFU_INTERFACE 2 +#endif +#define CFG_CONSOLE_IS_IN_ENV 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "usbtty=cdc_acm\0" \ + "bootargs_base=rootfstype=jffs2 root=/dev/mtdblock4 console=ttySAC2,115200 console=tty0 loglevel=8\0" \ + "" + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#define PHYS_SDRAM_RES_SIZE 0x00200000 /* 2 MB for frame buffer */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* No NOR flash in this device */ +#define CFG_NO_FLASH 1 + +#define CFG_ENV_SIZE 0x20000 /* 128k Total Size of Environment Sector */ +#define CFG_ENV_IS_IN_NAND 1 +#define CFG_ENV_OFFSET_OOB 1 /* Location of ENV stored in block 0 OOB */ +#define CFG_PREBOOT_OVERRIDE 1 /* allow preboot from memory */ + +#define NAND_MAX_CHIPS 3 +#define CFG_NAND_BASE 0x4e000000 +#define CFG_MAX_NAND_DEVICE NAND_MAX_CHIPS +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE, CFG_NAND_BASE, CFG_NAND_BASE } + +#define CONFIG_MMC 1 +#define CFG_MMC_BASE 0xff000000 + +/* EXT2 driver */ +#define CONFIG_EXT2 1 + +#define CONFIG_FAT 1 +#define CONFIG_SUPPORT_VFAT + +#if 1 +/* JFFS2 driver */ +#define CONFIG_JFFS2_CMDLINE 1 +#define CONFIG_JFFS2_NAND 1 +#define CONFIG_JFFS2_NAND_DEV 0 +//#define CONFIG_JFFS2_NAND_OFF 0x634000 +//#define CONFIG_JFFS2_NAND_SIZE 0x39cc000 +#endif + +/* ATAG configuration */ +#define CONFIG_INITRD_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_REVISION_TAG 1 +#if 0 +#define CONFIG_SERIAL_TAG 1 +#endif + +#define CONFIG_DRIVER_S3C24X0_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CFG_I2C_SPEED 400000 /* 400kHz according to PCF50606 data sheet */ +#define CFG_I2C_SLAVE 0x7f + +/* we have a board_late_init() function */ +#define BOARD_LATE_INIT 1 + +#if 1 +#define CONFIG_VIDEO +#define CONFIG_VIDEO_S3C2410 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CFG_VIDEO_LOGO_MAX_SIZE (640*480+1024+100) /* 100 = slack */ +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_UNZIP + +#define VIDEO_KBD_INIT_FCT 0 +#define VIDEO_TSTC_FCT serial_tstc +#define VIDEO_GETC_FCT serial_getc + +#define LCD_VIDEO_ADDR 0x33d00000 +#endif + +#define CONFIG_S3C2410_NAND_BBT 1 +//#define CONFIG_S3C2410_NAND_HWECC 1 + +#define CONFIG_DRIVER_PCF50606 1 + +#define MTDIDS_DEFAULT "nand0=hxd8-nand" +#define MTPARTS_DEFAULT "hxd8-nand:256k(u-boot),128k(u-boot_env),2M(kernel),640k(splash),0x3fd00000(jffs2)" +#define CFG_NAND_DYNPART_MTD_KERNEL_NAME "hxd8-nand" +#define CONFIG_NAND_DYNPART + +#endif /* __CONFIG_H */ Index: u-boot/board/hxd8/udc.c =================================================================== --- /dev/null +++ u-boot/board/hxd8/udc.c @@ -0,0 +1,30 @@ + +#include +#include +#include + +#if defined(CONFIG_USB_DEVICE) + +void udc_ctrl(enum usbd_event event, int param) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + switch (event) { + case UDC_CTRL_PULLUP_ENABLE: + if (param) + gpio->GPBDAT |= (1 << 9); /* GPB9 */ + else + gpio->GPBDAT &= ~(1 << 9); /* GPB9 */ + break; + case UDC_CTRL_500mA_ENABLE: + if (param) + gpio->GPADAT |= (1 << 0); /* GPA0 */ + else + gpio->GPADAT &= ~(1 << 0); /* GPA0 */ + break; + default: + break; + } +} + +#endif /* CONFIG_USB_DEVICE */ Index: u-boot/board/hxd8/pcf50606.c =================================================================== --- /dev/null +++ u-boot/board/hxd8/pcf50606.c @@ -0,0 +1,67 @@ + +#include +#include + +/* initial register set for PCF50606 in HXD8 devices */ +const u_int8_t pcf50606_initial_regs[__NUM_PCF50606_REGS] = { + [PCF50606_REG_OOCS] = 0x00, + /* gap */ + [PCF50606_REG_INT1M] = PCF50606_INT1_SECOND, + [PCF50606_REG_INT2M] = PCF50606_INT2_CHGFOK | + PCF50606_INT2_CHGERR | + PCF50606_INT2_CHGFRDY | + PCF50606_INT2_CHGPROT | + PCF50606_INT2_CHGWD10S | + PCF50606_INT2_CHGWDEXP, + [PCF50606_REG_INT3M] = PCF50606_INT3_TSCPRES, + [PCF50606_REG_OOCC1] = PCF50606_OOCC1_RTCWAK | + PCF50606_OOCC1_CHGWAK & + PCF50606_OOCC1_EXTONWAK_NO_WAKEUP, + [PCF50606_REG_OOCC2] = PCF50606_OOCC2_ONKEYDB_14ms | + PCF50606_OOCC2_EXTONDB_14ms, + /* gap */ + [PCF50606_REG_PSSC] = 0x00, + [PCF50606_REG_PWROKM] = 0x00, + /* gap */ + [PCF50606_REG_DCDC1] = 0xf0, /* CORE_1V3: on */ + [PCF50606_REG_DCDC2] = 0x00, + [PCF50606_REG_DCDC3] = 0x00, + [PCF50606_REG_DCDC4] = 0x30, /* 1.25A */ + + [PCF50606_REG_DCDEC1] = 0xe8, /* IO1_3V3: off */ + [PCF50606_REG_DCDEC2] = 0x00, + + [PCF50606_REG_DCUDC1] = 0x08, /* RF_3V3: off */ + [PCF50606_REG_DCUDC2] = 0x30, /* 1.25A current limit */ + + [PCF50606_REG_IOREGC] = 0xf8, /* AUDIO_3V3: on */ + + [PCF50606_REG_D1REGC1] = 0xf8, /* RC_3V3: on */ + + [PCF50606_REG_D2REGC1] = 0x18, /* GPS_3V3: off */ + + [PCF50606_REG_D3REGC1] = 0xf8, /* IO2_3V3: off */ + + [PCF50606_REG_LPREGC1] = 0xf8, /* LCM_3V3: on */ + [PCF50606_REG_LPREGC2] = 0x00, + + [PCF50606_REG_MBCC1] = 0x00, /* charger unused */ + [PCF50606_REG_MBCC2] = 0x00, /* unlimited charging */ + [PCF50606_REG_MBCC3] = 0x1a, /* 0.2*Ifast, 4.20V */ + [PCF50606_REG_BBCC] = 0x1f, /* 400uA */ + [PCF50606_REG_ADCC1] = 0x00, + [PCF50606_REG_ADCC2] = 0x00, + /* gap */ + [PCF50606_REG_ACDC1] = 0x00, + [PCF50606_REG_BVMC] = PCF50606_BVMC_THRSHLD_3V3, + [PCF50606_REG_PWMC1] = 0x1f, /* clock: 512 DC: 15/16*/ + [PCF50606_REG_LEDC1] = 0x00, + [PCF50606_REG_LEDC2] = 0x00, + [PCF50606_REG_GPOC1] = 0x03, /* PWM ACTIVE */ + [PCF50606_REG_GPOC2] = 0x07, /* back light pull low */ + [PCF50606_REG_GPOC3] = 0x00, + [PCF50606_REG_GPOC4] = 0x00, + [PCF50606_REG_GPOC5] = 0x00, +}; + + Index: u-boot/board/hxd8/config.mk =================================================================== --- /dev/null +++ u-boot/board/hxd8/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# David Mueller, ELSOFT AG, +# +# FIC HXD8 board with S3C2440X (ARM920T) cpu +# +# see http://www.samsung.com/ for more information on SAMSUNG +# + +CONFIG_USB_DFU_VENDOR=0x1457 +CONFIG_USB_DFU_PRODUCT=0x511a +CONFIG_USB_DFU_REVISION=0x0100 + +# +# HXD81v011 or later has 1 bank of 128 MB SDRAM +# +# 3000'0000 to 3800'0000 +# we load ourself to 37F8'0000 +# +# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 +# optionally with a ramdisk at 3080'0000 +# +# download area is 3200'0000 or 3300'0000 + +# FIXME: TEXT_BASE = 0x37F80000 +TEXT_BASE = 0x33F80000 Index: u-boot/board/hxd8/u-boot.lds =================================================================== --- /dev/null +++ u-boot/board/hxd8/u-boot.lds @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + cpu/arm920t/s3c24x0/nand_read.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} Index: u-boot/board/hxd8/lowlevel_foo.S =================================================================== --- /dev/null +++ u-boot/board/hxd8/lowlevel_foo.S @@ -0,0 +1,87 @@ + +_start: + b reset +undefvec: + b undefvec +swivec: + b swivec +pabtvec: + b pabtvec +dabtvec: + b dabtvec +rsvdvec: + b rsvdvec +irqvec: + b irqvec +fiqvec: + b fiqvec + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + +/* turn off the watchdog */ +#define pWTCON 0x53000000 +#define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ +#define INTSUBMSK 0x4A00001C +#define CLKDIVN 0x4C000014 /* clock divisor register */ +#define CAMDIVN 0x4C000018 + + ldr r0, =pWTCON + mov r1, #0x0 + str r1, [r0] + + mov r1, #0xffffffff + ldr r0, =INTMSK + str r1, [r0] + ldr r1, =0x7ff + ldr r0, =INTSUBMSK + str r1, [r0] + + /* FCLK:HCLK:PCLK = 1:3:6 */ + ldr r0, =CAMDIVN + mov r1, #0 + str r1, [r0] + + /* FCLK:HCLK:PCLK = 1:3:6 */ + ldr r0, =CLKDIVN + mov r1, #7 + str r1, [r0] + + bl cpu_init_crit + ldr r0,=TEXT_BASE + mov pc, r0 + +cpu_init_crit: + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) + bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) + orr r0, r0, #0x00000002 @ set bit 2 (A) Align + orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache + mcr p15, 0, r0, c1, c0, 0 + + /* + * before relocating, we have to setup RAM timing + * because memory timing is board-dependend, you will + * find a lowlevel_init.S in your board directory. + */ + mov ip, lr + bl lowlevel_init + mov lr, ip + mov pc, lr + Index: u-boot/board/hxd8/lowlevel_foo.lds =================================================================== --- /dev/null +++ u-boot/board/hxd8/lowlevel_foo.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + lowlevel_foo.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} Index: u-boot/cpu/arm920t/s3c24x0/nand.c =================================================================== --- u-boot.orig/cpu/arm920t/s3c24x0/nand.c +++ u-boot/cpu/arm920t/s3c24x0/nand.c @@ -83,6 +83,59 @@ #define NFDATA __REGb(NF_BASE + oNFDATA) #define NFSTAT __REGb(NF_BASE + oNFSTAT) +#if defined(CONFIG_HXD8) +static int hxd8_nand_dev_ready(struct mtd_info *mtd) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + u_int32_t val = gpio->GPCDAT; + + switch (nand_curr_device) { + case 0: + return (NFSTAT & 0x01); + case 1: /* RnB 3 */ + return ((val>>6) & 0x01); + case 2: /* RnB 4 */ + return ((val>>7) & 0x01); + case 3: /* RnB 2 */ + return ((val>>5) & 0x01); + default: + return 0; + } +} + +/* 4G Nand flash chip select function */ +static void hxd8_nand_select_chip(struct nand_chip *this, int chip) +{ + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + + if (chip == 0) + gpio->GPGDAT &= ~(1 << 1); + else + gpio->GPGDAT |= (1 << 1); + + if (chip == 1) + gpio->GPADAT &= ~(1 << 15); + else + gpio->GPADAT |= (1 << 15); + + if (chip == 2) + gpio->GPADAT &= ~(1 << 16); + else + gpio->GPADAT |= (1 << 16); + + if (chip == 3) + gpio->GPADAT &= ~(1 << 14); + else + gpio->GPADAT |= (1 << 14); + + /* UGLY: ew don't have mtd_info pointer, but know that + * s3c24xx hwcontrol function does not use it for CLRNCE */ + if (chip == -1) + this->hwcontrol(NULL, NAND_CTL_CLRNCE); + else + this->hwcontrol(NULL, NAND_CTL_SETNCE); +} +#endif static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd) { @@ -251,6 +304,11 @@ nand->eccmode = NAND_ECC_SOFT; #endif +#if defined(CONFIG_HXD8) + nand->dev_ready = hxd8_nand_dev_ready; + nand->select_chip = hxd8_nand_select_chip; +#endif + #ifdef CONFIG_S3C2410_NAND_BBT nand->options = NAND_USE_FLASH_BBT | NAND_DONT_CREATE_BBT; #else