Gross hacks to make the Zylonite boot from flash in VGA. Flash driver forward ported to 2.6.14 Index: linux-2.6.23/drivers/mtd/nand/Kconfig =================================================================== --- linux-2.6.23.orig/drivers/mtd/nand/Kconfig 2007-10-09 21:31:38.000000000 +0100 +++ linux-2.6.23/drivers/mtd/nand/Kconfig 2008-02-13 00:59:45.000000000 +0000 @@ -223,6 +223,10 @@ tristate "Support for NAND Flash on Sharp SL Series (C7xx + others)" depends on ARCH_PXA +config MTD_NAND_ZYLONITE + tristate "Support for NAND Flash on Zylonite" + depends on ARCH_PXA + config MTD_NAND_BASLER_EXCITE tristate "Support for NAND Flash on Basler eXcite" depends on BASLER_EXCITE Index: linux-2.6.23/drivers/mtd/nand/Makefile =================================================================== --- linux-2.6.23.orig/drivers/mtd/nand/Makefile 2007-10-09 21:31:38.000000000 +0100 +++ linux-2.6.23/drivers/mtd/nand/Makefile 2008-02-13 00:59:45.000000000 +0000 @@ -19,6 +19,7 @@ obj-$(CONFIG_MTD_NAND_H1900) += h1910.o obj-$(CONFIG_MTD_NAND_RTC_FROM4) += rtc_from4.o obj-$(CONFIG_MTD_NAND_SHARPSL) += sharpsl.o +obj-$(CONFIG_MTD_NAND_ZYLONITE) += mhn_nand.o obj-$(CONFIG_MTD_NAND_TS7250) += ts7250.o obj-$(CONFIG_MTD_NAND_NANDSIM) += nandsim.o obj-$(CONFIG_MTD_NAND_CS553X) += cs553x_nand.o Index: linux-2.6.23/drivers/mtd/nand/mhn_nand.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ linux-2.6.23/drivers/mtd/nand/mhn_nand.c 2008-02-13 00:59:45.000000000 +0000 @@ -0,0 +1,3869 @@ +/* + * drivers/mtd/nand/mhn_nand.c + * + * Copyright (C) 2005 Intel Coporation (chao.xie@intel.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Overview: + * This is a device driver for the NAND flash device on zylonite board + * which utilizes the Samsung K9K1216Q0C parts. This is a 64Mibit NAND + * flash device. + + *(C) Copyright 2006 Marvell International Ltd. + * All Rights Reserved + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include + +//#define NDCR 0xf0000000 +//#define NDCR (*((volatile u32 *)0xf0000000)) +//#define NDCR __REG_2(0x43100000) /* Data Flash Control register */ +#define NDCR_SPARE_EN (0x1<<31) +#define NDCR_ECC_EN (0x1<<30) +#define NDCR_DMA_EN (0x1<<29) +#define NDCR_ND_RUN (0x1<<28) +#define NDCR_DWIDTH_C (0x1<<27) +#define NDCR_DWIDTH_M (0x1<<26) +#define NDCR_PAGE_SZ (0x1<<24) +#define NDCR_NCSX (0x1<<23) +#define NDCR_ND_MODE (0x3<<21) +#define NDCR_NAND_MODE 0x0 +#define NDCR_CLR_PG_CNT (0x1<<20) +#define NDCR_CLR_ECC ( 0x1<<19) +#define NDCR_RD_ID_CNT_MASK (0x7<<16) +#define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK) +#define NDCR_RA_START (0x1<<15) +#define NDCR_PG_PER_BLK (0x1<<14) +#define NDCR_ND_ARB_EN (0x1<<12) + +//#define NDSR (*((volatile u32 *)0xf0000014)) +//#define NDSR __REG_2(0x43100014) /* Data Controller Status Register */ +#define NDSR_RDY (0x1<<11) +#define NDSR_CS0_PAGED (0x1<<10) +#define NDSR_CS1_PAGED (0x1<<9) +#define NDSR_CS0_CMDD (0x1<<8) +#define NDSR_CS1_CMDD (0x1<<7) +#define NDSR_CS0_BBD (0x1<<6) +#define NDSR_CS1_BBD (0x1<<5) +#define NDSR_DBERR (0x1<<4) +#define NDSR_SBERR (0x1<<3) +#define NDSR_WRDREQ (0x1<<2) +#define NDSR_RDDREQ (0x1<<1) +#define NDSR_WRCMDREQ (0x1) + +#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ +//#define NDCB0 __REG_2(0x43100048) /* Data Controller Command Buffer0 */ +//#define NDCB1 __REG_2(0x4310004C) /* Data Controller Command Buffer1 */ +//#define NDCB2 __REG_2(0x43100050) /* Data Controller Command Buffer2 */ +#define NDCB0_AUTO_RS (0x1<<25) +#define NDCB0_CSEL (0x1<<24) +#define NDCB0_CMD_TYPE_MASK (0x7<<21) +#define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK) +#define NDCB0_NC (0x1<<20) +#define NDCB0_DBC (0x1<<19) +#define NDCB0_ADDR_CYC_MASK (0x7<<16) +#define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK) +#define NDCB0_CMD2_MASK (0xff<<8) +#define NDCB0_CMD1_MASK (0xff) +#define NDCB0_ADDR_CYC_SHIFT (16) +#define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */ +#define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */ +#define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */ +#define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */ +#define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */ +#define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */ +#define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */ +#define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */ +#define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */ +#define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */ +#define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */ +#define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */ +#define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */ +#define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */ +#define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */ +#define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */ +#define DCMD(x) __REG2(0x4000020c, (x) << 4) +#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */ +#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */ +#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ +#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */ +#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ +#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */ +#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */ +#define DCMD_BURST8 (1 << 16) /* 8 byte burst */ +#define DCMD_BURST16 (2 << 16) /* 16 byte burst */ +#define DCMD_BURST32 (3 << 16) /* 32 byte burst */ +#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */ +#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ +#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ +#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ +#define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4) +#define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4) +#define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4) +#define DRCMR(n) __REG2(0x40000100, (n)<<2) +#define DRCMR97 __REG(0x40001184) /* Request to Channel Map Register for NAND interface data transmit & receive Request */ +#define DRCMR98 __REG(0x40001188) /* Reserved */ +#define DRCMR99 __REG(0x4000118C) /* Request to Channel Map Register for NAND interface command transmit Request */ +#define DRCMRRXSADR DRCMR2 +#define DRCMRTXSADR DRCMR3 +#define DRCMRRXBTRBR DRCMR4 +#define DRCMRTXBTTHR DRCMR5 +#define DRCMRRXFFRBR DRCMR6 +#define DRCMRTXFFTHR DRCMR7 +#define DRCMRRXMCDR DRCMR8 +#define DRCMRRXMODR DRCMR9 +#define DRCMRTXMODR DRCMR10 +#define DRCMRRXPCDR DRCMR11 +#define DRCMRTXPCDR DRCMR12 +#define DRCMRRXSSDR DRCMR13 +#define DRCMRTXSSDR DRCMR14 +#define DRCMRRXICDR DRCMR17 +#define DRCMRTXICDR DRCMR18 +#define DRCMRRXSTRBR DRCMR19 +#define DRCMRTXSTTHR DRCMR20 +#define DRCMRRXMMC DRCMR21 +#define DRCMRTXMMC DRCMR22 +#define DRCMRRXMMC2 DRCMR93 +#define DRCMRTXMMC2 DRCMR94 +#define DRCMRRXMMC3 DRCMR100 +#define DRCMRTXMMC3 DRCMR101 +#define DRCMRUDC(x) DRCMR((x) + 24) +#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ +#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ +#define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */ +#define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */ +#define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */ +#define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */ +#define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */ +#define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */ +#define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */ +#define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */ +#define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */ +#define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */ +#define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */ +#define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */ +#define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */ +#define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */ +#define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */ +#define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */ +#define DCSR16 __REG(0x40000040) /* DMA Control / Status Register for Channel 16 */ +#define DCSR17 __REG(0x40000044) /* DMA Control / Status Register for Channel 17 */ +#define DCSR18 __REG(0x40000048) /* DMA Control / Status Register for Channel 18 */ +#define DCSR19 __REG(0x4000004c) /* DMA Control / Status Register for Channel 19 */ +#define DCSR20 __REG(0x40000050) /* DMA Control / Status Register for Channel 20 */ +#define DCSR21 __REG(0x40000054) /* DMA Control / Status Register for Channel 21 */ +#define DCSR22 __REG(0x40000058) /* DMA Control / Status Register for Channel 22 */ +#define DCSR23 __REG(0x4000005c) /* DMA Control / Status Register for Channel 23 */ +#define DCSR24 __REG(0x40000060) /* DMA Control / Status Register for Channel 24 */ +#define DCSR25 __REG(0x40000064) /* DMA Control / Status Register for Channel 25 */ +#define DCSR26 __REG(0x40000068) /* DMA Control / Status Register for Channel 26 */ +#define DCSR27 __REG(0x4000006c) /* DMA Control / Status Register for Channel 27 */ +#define DCSR28 __REG(0x40000070) /* DMA Control / Status Register for Channel 28 */ +#define DCSR29 __REG(0x40000074) /* DMA Control / Status Register for Channel 29 */ +#define DCSR30 __REG(0x40000078) /* DMA Control / Status Register for Channel 30 */ +#define DCSR31 __REG(0x4000007c) /* DMA Control / Status Register for Channel 31 */ +#define DCSR(x) __REG2(0x40000000, (x) << 2) +#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ +#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ +#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ +#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ +#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ +#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ +#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ +#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ +#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ +#define DCSR_EORINTR (1 << 9) /* The end of Receive */ +#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ +#define DCSR_RASINTR (1 << 4) /* Request After Channel Stopped */ +#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ +#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */ +#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */ +#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */ +#define DDADR(x) __REG2(0x40000200, (x) << 4) +//#define __REG_2(x) (*((volatile u32 *)io_p2v_2(x))) +#define IRQ_NAND PXA_IRQ(45) +#define CKEN_NAND 4 ///< NAND Flash Controller Clock Enable + +/* #define CONFIG_MTD_NAND_MONAHANS_DEBUG */ +#ifdef CONFIG_MTD_NAND_MONAHANS_DEBUG +#define D1(x) do { \ + printk(KERN_DEBUG "%s: ", __FUNCTION__); \ + x; \ + }while(0) + +#define DPRINTK(fmt,args...) printk(KERN_DEBUG fmt, ##args ) +#define PRINT_BUF(buf, num) print_buf(buf, num) +#else +#define D1(x) +#define DPRINTK(fmt,args...) +#define PRINT_BUF(buf, num) +#endif + +/* DFC timing 0 register */ +#define DFC_TIMING_tRP 0 +#define DFC_TIMING_tRH 3 +#define DFC_TIMING_tWP 8 +#define DFC_TIMING_tWH 11 +#define DFC_TIMING_tCS 16 +#define DFC_TIMING_tCH 19 + +/* DFC timing 1 register */ +#define DFC_TIMING_tAR 0 +#define DFC_TIMING_tWHR 4 +#define DFC_TIMING_tR 16 + +/* max value for each timing setting in DFC */ +#define DFC_TIMING_MAX_tCH 7 +#define DFC_TIMING_MAX_tCS 7 +#define DFC_TIMING_MAX_tWH 7 +#define DFC_TIMING_MAX_tWP 7 +#define DFC_TIMING_MAX_tRH 7 +#define DFC_TIMING_MAX_tRP 7 +#define DFC_TIMING_MAX_tR 65535 +#define DFC_TIMING_MAX_tWHR 15 +#define DFC_TIMING_MAX_tAR 15 + +/* + * The Data Flash Controller Flash timing structure + * For NAND flash used on Zylonite board(Samsung K9K1216Q0C), + * user should use value at end of each row of following member + * bracketed. + */ +struct dfc_flash_timing { + uint32_t tCH; /* Enable signal hold time */ + uint32_t tCS; /* Enable signal setup time */ + uint32_t tWH; /* ND_nWE high duration */ + uint32_t tWP; /* ND_nWE pulse time */ + uint32_t tRH; /* ND_nRE high duration */ + uint32_t tRP; /* ND_nRE pulse width */ + uint32_t tR; /* ND_nWE high to ND_nRE low for read */ + uint32_t tWHR;/* ND_nWE high to ND_nRE low delay for status read */ + uint32_t tAR; /* ND_ALE low to ND_nRE low delay */ +}; + +/* DFC command type */ +enum { + DFC_CMD_READ = 0x00000000, + DFC_CMD_PROGRAM = 0x00200000, + DFC_CMD_ERASE = 0x00400000, + DFC_CMD_READ_ID = 0x00600000, + DFC_CMD_STATUS_READ = 0x00800000, + DFC_CMD_RESET = 0x00a00000 +}; + +/* + * The Data Flash Controller Flash specification structure + * For NAND flash used on Zylonite board(Samsung K9K1216Q0C), + * user should use value at end of each row of following member + * bracketed. + */ +struct dfc_flash_info { + struct dfc_flash_timing timing; /* NAND Flash timing */ + + int enable_arbiter;/* Data flash bus arbiter enable (ND_ARB_EN) */ + uint32_t page_per_block;/* Pages per block (PG_PER_BLK) */ + uint32_t row_addr_start;/* Row address start position (RA_START) */ + uint32_t read_id_bytes; /* returned ID bytes(RD_ID_CNT) */ + uint32_t dfc_mode; /* NAND, CARBONDALE, PIXLEY... (ND_MODE) */ + uint32_t ncsx; /* Chip select don't care bit (NCSX) */ + uint32_t page_size; /* Page size in bytes (PAGE_SZ) */ + uint32_t oob_size; /* OOB size */ + uint32_t flash_width; /* Width of Flash memory (DWIDTH_M) */ + uint32_t dfc_width; /* Width of flash controller(DWIDTH_C) */ + uint32_t num_blocks; /* Number of physical blocks in Flash */ + uint32_t chip_id; + + /* command codes */ + uint32_t read1; /* Read */ + uint32_t read2; /* unused, DFC don't support yet */ + uint32_t program; /* two cycle command */ + uint32_t read_status; + uint32_t read_id; + uint32_t erase; /* two cycle command */ + uint32_t reset; + uint32_t lock; /* lock whole flash */ + uint32_t unlock; /* two cycle command, supporting partial unlock */ + uint32_t lock_status; /* read block lock status */ + + /* addr2ndcb1 - encode address cycles into register NDCB1 */ + /* ndbbr2addr - convert register NDBBR to bad block address */ + int (*addr2ndcb1)(uint16_t cmd, uint32_t addr, uint32_t *p); + int (*ndbbr2addr)(uint16_t cmd, uint32_t ndbbr,uint32_t *p); +}; + +enum { + DFC_FLASH_NULL = 0 , + DFC_FLASH_Samsung_512Mb_X_16 = 1, + DFC_FLASH_Micron_1Gb_X_8 = 2, + DFC_FLASH_Micron_1Gb_X_16 = 3, + DFC_FLASH_STM_1Gb_X_16 = 4, + DFC_FLASH_STM_2Gb_X_16 = 5, + DFC_FLASH_END, +}; + +static int dfc_get_flash_info(int type, struct dfc_flash_info **flash_info); + +#define DFC_NDCR 0 +#define DFC_NDTR0CS0 1 +#define DFC_NDTR1CS0 3 +#define DFC_NDSR 5 +#define DFC_NDPCR 6 +#define DFC_NDBDR0 7 +#define DFC_NDBDR1 8 +#define DFC_NDDB 16 +#define DFC_NDCB0 18 +#define DFC_NDCB1 19 +#define DFC_NDCB2 20 + +/* The Data Flash Controller Mode structure */ +struct dfc_mode { + int enable_dma; /* DMA, or nonDMA mode */ + int enable_ecc; /* ECC on/off */ + int enable_spare; /* Spare enable */ + int chip_select; /* CS0 or CS1 */ +}; + +/* The Data Flash Controller Context structure */ +struct dfc_context { + unsigned char __iomem *membase; /* DFC register base */ + struct dfc_mode *dfc_mode; /* DFC mode */ + int data_dma_ch; /* Data DMA channel number */ + int cmd_dma_ch; /* CMD DMA channel number */ + struct dfc_flash_info *flash_info; /* Flash Spec */ + struct mtd_info *mtd; +}; + +#define NDCB0_DMA_ADDR 0x43100048 +#define NDDB_DMA_ADDR 0x43100040 + +#define NDSR_MASK 0xFFF + +/* The following data is a rough evaluation */ + +/* microsecond, for readID/readStatus/reset */ +#define NAND_OTHER_TIMEOUT 10 +/* microsecond, for readID/readStatus/reset */ +#define NAND_CMD_TIMEOUT 10 + +#define BBT_BLOCK_BAD 0x03 +#define BBT_BLOCK_GOOD 0x00 +#define BBT_BLOCK_REV1 0x01 +#define BBT_BLOCK_REV2 0x02 + +#define BUFLEN (2048 + 64) + +/* + * DFC data size enumeration transfered from/to controller, + * including padding (zero)to be a multiple of 32. + */ +enum { + DFC_DATA_SIZE_STATUS = 8, /* ReadStatus/ReadBlockLockStatus */ + DFC_DATA_SIZE_ID = 7, /* ReadID */ + + DFC_DATA_SIZE_32 = 32, + DFC_DATA_SIZE_512 = 512, /* R/W disabling spare area */ + DFC_DATA_SIZE_520 = 520, /* Spare=1, ECC=1 */ + DFC_DATA_SIZE_528 = 528, /* Spare=1, ECC=0 */ + DFC_DATA_SIZE_544 = 544, /* R/W enabling spare area.(DMA mode)*/ + + DFC_DATA_SIZE_64 = 64, + DFC_DATA_SIZE_2048 = 2048, /* R/W disabling spare area */ + DFC_DATA_SIZE_2088 = 2088, /* R/W enabling spare area with ecc */ + DFC_DATA_SIZE_2112 = 2112, /* R/W enabling spare area without ecc*/ + DFC_DATA_SIZE_2096 = 2096, /* R/W enabling spare area */ + DFC_DATA_SIZE_UNUSED = 0xFFFF +}; + +/* DFC padding size enumeration transfered from/to controller */ +enum { + /* + * ReadStatus/ReadBlockLockStatus/ReadID/ + * Read/Program disabling spare area(Both 512 and 2048) + * Read/Program enabling spare area, disabling ECC + */ + DFC_PADDING_SIZE_0 = 0, + + /* Read/program with SPARE_EN=1, ECC_EN=0, pgSize=512 */ + DFC_PADDING_SIZE_16 = 16, + /* for read/program with SPARE_EN=1, ECC_EN=1, pgSize=512 and 2048 */ + DFC_PADDING_SIZE_24 = 24, + DFC_PADDING_SIZE_UNUSED = 0xFFFF +}; + +static unsigned int flash_config = DFC_FLASH_NULL; + +void dfc_set_timing(struct dfc_context *context, struct dfc_flash_timing *t); +void dfc_set_dma(struct dfc_context *context); +void dfc_set_ecc(struct dfc_context *context); +void dfc_set_spare(struct dfc_context *context); + +int dfc_get_pattern(struct dfc_context *context, uint16_t cmd, + int *data_size, int *padding); + +static int dfc_wait_event(struct dfc_context *context, uint32_t event, + uint32_t *event_out, uint32_t timeout, int enable_int); + +int dfc_send_cmd(struct dfc_context *context, uint16_t cmd, + uint32_t addr, int num_pages); + +void dfc_stop(struct dfc_context *context); +void dfc_read_fifo_partial(struct dfc_context *context, uint8_t *buffer, + int nbytes, int data_size); +void dfc_write_fifo_partial(struct dfc_context *context, uint8_t *buffer, + int nbytes, int data_size); + +void dfc_read_fifo(struct dfc_context *context, uint8_t *buffer, int nbytes); +void dfc_write_fifo(struct dfc_context *context, uint8_t *buffer, int nbytes); + +void dfc_read_badblock_addr(struct dfc_context *context, uint32_t *bbaddr); + +void dfc_clear_int(struct dfc_context *context, uint32_t int_mask); +void dfc_enable_int(struct dfc_context *context, uint32_t int_mask); +void dfc_disable_int(struct dfc_context *context, uint32_t int_mask); + +/* high level primitives */ +int dfc_init(struct dfc_context *context, int type); +int dfc_init_no_gpio(struct dfc_context *context, int type); + +int dfc_reset_flash(struct dfc_context *context); + +int dfc_setup_cmd_dma(struct dfc_context *context, + uint16_t cmd, uint32_t addr, int num_pages, + uint32_t *buf, uint32_t buf_phys, + uint32_t next_desc_phys, uint32_t dma_int_en, + struct pxa_dma_desc *dma_desc); + +int dfc_setup_data_dma(struct dfc_context *context, + uint16_t cmd, uint32_t buf_phys, + uint32_t next_desc_phys, uint32_t dma_int_en, + struct pxa_dma_desc *dma_desc); + +void dfc_start_cmd_dma(struct dfc_context *context, + struct pxa_dma_desc *dma_desc); +void dfc_start_data_dma(struct dfc_context *context, + struct pxa_dma_desc *dma_desc); +static int monahans_df_dev_ready(struct mtd_info *mtd); + +#ifdef CONFIG_DVFM +static int mhn_nand_dvfm_notifier(unsigned cmd, void *client_data, void *info); +static struct mhn_fv_notifier dvfm_notifier = { + .name = "monahans-nand-flash", + .priority = 0, + .notifier_call = mhn_nand_dvfm_notifier, +}; +#endif + +static unsigned short search_rel_block(int block, struct mtd_info *mtd); + +/***************************************************************************** + * The DFC registers read/write routines + *****************************************************************************/ +static inline void dfc_write(struct dfc_context *context, int offset, + unsigned long value) +{ + offset <<= 2; + writel(value, context->membase + offset); +} + +static inline unsigned int dfc_read(struct dfc_context *context, int offset) +{ + offset <<= 2; + return __raw_readl(context->membase + offset); +} + +/**************************************************************************** + * Flash Information + ***************************************************************************/ + +static int Samsung512MbX16Addr2NDCB1(uint16_t cmd, uint32_t addr, uint32_t *p); +static int Samsung512MbX16NDBBR2Addr(uint16_t cmd, uint32_t ndbbr, uint32_t *p); + +static struct dfc_flash_info samsung512MbX16 = +{ + .timing = { + .tCH = 10, /* tCH, Enable signal hold time */ + .tCS = 0, /* tCS, Enable signal setup time */ + .tWH = 20, /* tWH, ND_nWE high duration */ + .tWP = 40, /* tWP, ND_nWE pulse time */ + .tRH = 30, /* tRH, ND_nRE high duration */ + .tRP = 40, /* tRP, ND_nRE pulse width */ + /* tR = tR+tRR+tWB+1, ND_nWE high to ND_nRE low for read */ + .tR = 11123, + /* tWHR, ND_nWE high to ND_nRE low delay for status read */ + .tWHR = 110, + .tAR = 10, /* tAR, ND_ALE low to ND_nRE low delay */ + }, + .enable_arbiter = 1, /* Data flash bus arbiter enable */ + .page_per_block = 32, /* Pages per block */ + .row_addr_start = 0, /* Second cycle start, Row address start position */ + .read_id_bytes = 2, /* 2 bytes, returned ID bytes */ + .dfc_mode = 0, /* NAND mode */ + .ncsx = 0, + .page_size = 512, /* Page size in bytes */ + .oob_size = 16, /* OOB size in bytes */ + .flash_width = 16, /* Width of Flash memory */ + .dfc_width = 16, /* Width of flash controller */ + .num_blocks = 4096, /* Number of physical blocks in Flash */ + .chip_id = 0x46ec, + + /* command codes */ + .read1 = 0x0000, /* Read */ + .read2 = 0x0050, /* Read1 unused, current DFC don't support */ + .program = 0x1080, /* Write, two cycle command */ + .read_status = 0x0070, /* Read status */ + .read_id = 0x0090, /* Read ID */ + .erase = 0xD060, /* Erase, two cycle command */ + .reset = 0x00FF, /* Reset */ + .lock = 0x002A, /* Lock whole flash */ + .unlock = 0x2423, /* Unlock, two cycle command, supporting partial unlock */ + .lock_status = 0x007A, /* Read block lock status */ + .addr2ndcb1 = Samsung512MbX16Addr2NDCB1, + .ndbbr2addr = Samsung512MbX16NDBBR2Addr, +}; + +static int Samsung512MbX16Addr2NDCB1(uint16_t cmd, uint32_t addr, uint32_t *p) +{ + uint32_t ndcb1 = 0; + + if (addr >= 0x4000000) return -EINVAL; + + if (cmd == samsung512MbX16.read1 || cmd == samsung512MbX16.program) { + ndcb1 = (addr & 0xFF) | ((addr >> 1) & 0x01FFFF00); + } else if (cmd == samsung512MbX16.erase) { + ndcb1 = ((addr >> 9) & 0x00FFFFFF); + } + + *p = ndcb1; + return 0; + +} + +static int Samsung512MbX16NDBBR2Addr(uint16_t cmd, uint32_t ndbbr, uint32_t *p) +{ + *p = ndbbr << 9; + return 0; +} + +static int Micron1GbX8Addr2NDCB1(uint16_t cmd, uint32_t addr, uint32_t *p); +static int Micron1GbX8NDBBR2Addr(uint16_t cmd, uint32_t ndbbr, uint32_t *p); + +static struct dfc_flash_info micron1GbX8 = +{ + .timing = { + .tCH = 10, /* tCH, Enable signal hold time */ + .tCS = 25, /* tCS, Enable signal setup time */ + .tWH = 15, /* tWH, ND_nWE high duration */ + .tWP = 25, /* tWP, ND_nWE pulse time */ + .tRH = 15, /* tRH, ND_nRE high duration */ + .tRP = 25, /* tRP, ND_nRE pulse width */ + /* tR = tR+tRR+tWB+1, ND_nWE high to ND_nRE low for read */ + .tR = 25000, + /* tWHR, ND_nWE high to ND_nRE low delay for status read */ + .tWHR = 60, + .tAR = 10, /* tAR, ND_ALE low to ND_nRE low delay */ + }, + .enable_arbiter = 1, /* Data flash bus arbiter enable */ + .page_per_block = 64, /* Pages per block */ + .row_addr_start = 1, /* Second cycle start, Row address start position */ + .read_id_bytes = 4, /* Returned ID bytes */ + .dfc_mode = 0, /* NAND mode */ + .ncsx = 0, + .page_size = 2048, /* Page size in bytes */ + .oob_size = 64, /* OOB size in bytes */ + .flash_width = 8, /* Width of Flash memory */ + .dfc_width = 8, /* Width of flash controller */ + .num_blocks = 1024, /* Number of physical blocks in Flash */ + .chip_id = 0xa12c, + /* command codes */ + .read1 = 0x3000, /* Read */ + .read2 = 0x0050, /* Read1 unused, current DFC don't support */ + .program = 0x1080, /* Write, two cycle command */ + .read_status = 0x0070, /* Read status */ + .read_id = 0x0090, /* Read ID */ + .erase = 0xD060, /* Erase, two cycle command */ + .reset = 0x00FF, /* Reset */ + .lock = 0x002A, /* Lock whole flash */ + .unlock = 0x2423, /* Unlock, two cycle command, supporting partial unlock */ + .lock_status = 0x007A, /* Read block lock status */ + .addr2ndcb1 = Micron1GbX8Addr2NDCB1, + .ndbbr2addr = Micron1GbX8NDBBR2Addr, +}; + +static int Micron1GbX8Addr2NDCB1(uint16_t cmd, uint32_t addr, uint32_t *p) +{ + uint32_t ndcb1 = 0; + uint32_t page; + + if (addr >= 0x8000000) + return -EINVAL; + page = addr / micron1GbX8.page_size; + addr = (page / micron1GbX8.page_per_block) << 18 | + (page % micron1GbX8.page_per_block) << 12; + + if (cmd == micron1GbX8.read1 || cmd == micron1GbX8.program) { + ndcb1 = (addr & 0xFFF) | ((addr << 4) & 0xFFFF0000); + } + else if (cmd == micron1GbX8.erase) { + ndcb1 = ((addr >> 18) << 6) & 0xFFFF; + } + + *p = ndcb1; + return 0; +} + +static int Micron1GbX8NDBBR2Addr(uint16_t cmd, uint32_t ndbbr, uint32_t *p) +{ + if (cmd == micron1GbX8.read1 || cmd == micron1GbX8.program) { + *p = ((ndbbr & 0xF) << 8) | ((ndbbr >> 8) << 16); + } + else if (cmd == micron1GbX8.erase) { + *p = (ndbbr >> 6) << 18; + } + + + return 0; +} + + +static int Micron1GbX16Addr2NDCB1(uint16_t cmd, uint32_t addr, uint32_t *p); +static int Micron1GbX16NDBBR2Addr(uint16_t cmd, uint32_t ndbbr, uint32_t *p); + +static struct dfc_flash_info micron1GbX16 = +{ + .timing = { + .tCH = 10, /* tCH, Enable signal hold time */ + .tCS = 25, /* tCS, Enable signal setup time */ + .tWH = 15, /* tWH, ND_nWE high duration */ + .tWP = 25, /* tWP, ND_nWE pulse time */ + .tRH = 15, /* tRH, ND_nRE high duration */ + .tRP = 25, /* tRP, ND_nRE pulse width */ + /* tR = tR+tRR+tWB+1, ND_nWE high to ND_nRE low for read */ + .tR = 25000, + /* tWHR, ND_nWE high to ND_nRE low delay for status read */ + .tWHR = 60, + .tAR = 10, /* tAR, ND_ALE low to ND_nRE low delay */ + }, + .enable_arbiter = 1, /* Data flash bus arbiter enable */ + .page_per_block = 64, /* Pages per block */ + .row_addr_start = 1, /* Second cycle start, Row address start position */ + .read_id_bytes = 4, /* Returned ID bytes */ + .dfc_mode = 0, /* NAND mode */ + .ncsx = 0, + .page_size = 2048, /* Page size in bytes */ + .oob_size = 64, /* OOB size in bytes */ + .flash_width = 16, /* Width of Flash memory */ + .dfc_width = 16, /* Width of flash controller */ + .num_blocks = 1024, /* Number of physical blocks in Flash */ + .chip_id = 0xb12c, + + /* command codes */ + .read1 = 0x3000, /* Read */ + .read2 = 0x0050, /* Read1 unused, current DFC don't support */ + .program = 0x1080, /* Write, two cycle command */ + .read_status = 0x0070, /* Read status */ + .read_id = 0x0090, /* Read ID */ + .erase = 0xD060, /* Erase, two cycle command */ + .reset = 0x00FF, /* Reset */ + .lock = 0x002A, /* Lock whole flash */ + .unlock = 0x2423, /* Unlock, two cycle command, supporting partial unlock */ + .lock_status = 0x007A, /* Read block lock status */ + .addr2ndcb1 = Micron1GbX16Addr2NDCB1, + .ndbbr2addr = Micron1GbX16NDBBR2Addr, +}; + +static int Micron1GbX16Addr2NDCB1(uint16_t cmd, uint32_t addr, uint32_t *p) +{ + uint32_t ndcb1 = 0; + uint32_t page; + + if (addr >= 0x8000000) + return -EINVAL; + page = addr / micron1GbX16.page_size; + addr = (page / micron1GbX16.page_per_block) << 17 | + (page % micron1GbX16.page_per_block) << 11; + + if (cmd == micron1GbX16.read1 || cmd == micron1GbX16.program) { + ndcb1 = (addr & 0x7FF) | ((addr << 5) & 0xFFFF0000); + } + else if (cmd == micron1GbX16.erase) { + ndcb1 = ((addr >> 17) << 6) & 0xFFFF; + } + *p = ndcb1; + return 0; +} + +static int Micron1GbX16NDBBR2Addr(uint16_t cmd, uint32_t ndbbr, uint32_t *p) +{ + if (cmd == micron1GbX16.read1 || cmd == micron1GbX16.program) { + *p = ((ndbbr & 0x7) << 8) | ((ndbbr >> 8) << 16); + } + else if (cmd == micron1GbX16.erase) { + *p = (ndbbr >> 6) << 17; + } + + return 0; +} + +static int STM1GbX16Addr2NDCB1(uint16_t cmd, uint32_t addr, uint32_t *p); +static int STM1GbX16NDBBR2Addr(uint16_t cmd, uint32_t ndbbr, uint32_t *p); + +static struct dfc_flash_info stm1GbX16 = +{ + .timing = { + .tCH = 10, /* tCH, Enable signal hold time */ + .tCS = 10, /* tCS, Enable signal setup time */ + .tWH = 20, /* tWH, ND_nWE high duration */ + .tWP = 25, /* tWP, ND_nWE pulse time */ + .tRH = 20, /* tRH, ND_nRE high duration */ + .tRP = 25, /* tRP, ND_nRE pulse width */ + /* tR = tR+tRR+tWB+1, ND_nWE high to ND_nRE low for read */ + .tR = 25000, + /* tWHR, ND_nWE high to ND_nRE low delay for status read */ + .tWHR = 60, + .tAR = 10, /* tAR, ND_ALE low to ND_nRE low delay */ + }, + .enable_arbiter = 1, /* Data flash bus arbiter enable */ + .page_per_block = 64, /* Pages per block */ + .row_addr_start = 1, /* Second cycle start, Row address start position */ + .read_id_bytes = 4, /* Returned ID bytes */ + .dfc_mode = 0, /* NAND mode */ + .ncsx = 0, + .page_size = 2048, /* Page size in bytes */ + .oob_size = 64, /* OOB size in bytes */ + .flash_width = 16, /* Width of Flash memory */ + .dfc_width = 16, /* Width of flash controller */ + .num_blocks = 1024, /* Number of physical blocks in Flash */ + .chip_id = 0xb120, + + /* command codes */ + .read1 = 0x3000, /* Read */ + .read2 = 0x0050, /* Read1 unused, current DFC don't support */ + .program = 0x1080, /* Write, two cycle command */ + .read_status = 0x0070, /* Read status */ + .read_id = 0x0090, /* Read ID */ + .erase = 0xD060, /* Erase, two cycle command */ + .reset = 0x00FF, /* Reset */ + .lock = 0x002A, /* Lock whole flash */ + .unlock = 0x2423, /* Unlock, two cycle command, supporting partial unlock */ + .lock_status = 0x007A, /* Read block lock status */ + .addr2ndcb1 = STM1GbX16Addr2NDCB1, + .ndbbr2addr = STM1GbX16NDBBR2Addr, +}; + +static int STM1GbX16Addr2NDCB1(uint16_t cmd, uint32_t addr, uint32_t *p) +{ + uint32_t ndcb1 = 0; + uint32_t page; + + if (addr >= 0x8000000) + return -EINVAL; + page = addr / stm1GbX16.page_size; + addr = (page / stm1GbX16.page_per_block) << 17 | + (page % stm1GbX16.page_per_block) << 11; + + if (cmd == stm1GbX16.read1 || cmd == stm1GbX16.program) { + ndcb1 = (addr & 0x7FF) | ((addr << 5) & 0xFFFF0000); + } + else if (cmd == stm1GbX16.erase) { + ndcb1 = ((addr >> 17) << 6) & 0xFFFF; + } + *p = ndcb1; + return 0; +} + +static int STM1GbX16NDBBR2Addr(uint16_t cmd, uint32_t ndbbr, uint32_t *p) +{ + if (cmd == stm1GbX16.read1 || cmd == stm1GbX16.program) { + *p = ((ndbbr & 0x7) << 8) | ((ndbbr >> 8) << 16); + } + else if (cmd == stm1GbX16.erase) { + *p = (ndbbr >> 6) << 17; + } + + return 0; +} + +static int STM2GbX16Addr2NDCB1(uint16_t cmd, uint32_t addr, uint32_t *p); +static int STM2GbX16NDBBR2Addr(uint16_t cmd, uint32_t ndbbr, uint32_t *p); + +static struct dfc_flash_info stm2GbX16 = +{ + .timing = { + .tCH = 10, /* tCH, Enable signal hold time */ + .tCS = 10, /* tCS, Enable signal setup time */ + .tWH = 20, /* tWH, ND_nWE high duration */ + .tWP = 25, /* tWP, ND_nWE pulse time */ + .tRH = 20, /* tRH, ND_nRE high duration */ + .tRP = 25, /* tRP, ND_nRE pulse width */ + /* tR = tR+tRR+tWB+1, ND_nWE high to ND_nRE low for read */ + .tR = 25000, + /* tWHR, ND_nWE high to ND_nRE low delay for status read */ + .tWHR = 60, + .tAR = 10, /* tAR, ND_ALE low to ND_nRE low delay */ + }, + .enable_arbiter = 1, /* Data flash bus arbiter enable */ + .page_per_block = 64, /* Pages per block */ + .row_addr_start = 1, /* Second cycle start, Row address start position */ + .read_id_bytes = 4, /* Returned ID bytes */ + .dfc_mode = 0, /* NAND mode */ + .ncsx = 0, + .page_size = 2048, /* Page size in bytes */ + .oob_size = 64, /* OOB size in bytes */ + .flash_width = 16, /* Width of Flash memory */ + .dfc_width = 16, /* Width of flash controller */ + .num_blocks = 2048, /* Number of physical blocks in Flash */ + .chip_id = 0xca20, + + /* command codes */ + .read1 = 0x3000, /* Read */ + .read2 = 0x0050, /* Read1 unused, current DFC don't support */ + .program = 0x1080, /* Write, two cycle command */ + .read_status = 0x0070, /* Read status */ + .read_id = 0x0090, /* Read ID */ + .erase = 0xD060, /* Erase, two cycle command */ + .reset = 0x00FF, /* Reset */ + .lock = 0x002A, /* Lock whole flash */ + .unlock = 0x2423, /* Unlock, two cycle command, supporting partial unlock */ + .lock_status = 0x007A, /* Read block lock status */ + .addr2ndcb1 = STM2GbX16Addr2NDCB1, + .ndbbr2addr = STM2GbX16NDBBR2Addr, +}; + +static int STM2GbX16Addr2NDCB1(uint16_t cmd, uint32_t addr, uint32_t *p) +{ + uint32_t ndcb1 = 0; + uint32_t page; + + if (addr >= 0x8000000) + return -EINVAL; + page = addr / stm2GbX16.page_size; + addr = (page / stm2GbX16.page_per_block) << 17 | + (page % stm2GbX16.page_per_block) << 11; + + if (cmd == stm2GbX16.read1 || cmd == stm2GbX16.program) { + ndcb1 = (addr & 0x7FF) | ((addr << 5) & 0xFFFF0000); + } + else if (cmd == stm2GbX16.erase) { + ndcb1 = ((addr >> 17) << 6) & 0xFFFF; + } + *p = ndcb1; + return 0; +} + +static int STM2GbX16NDBBR2Addr(uint16_t cmd, uint32_t ndbbr, uint32_t *p) +{ + if (cmd == stm2GbX16.read1 || cmd == stm2GbX16.program) { + *p = ((ndbbr & 0x7) << 8) | ((ndbbr >> 8) << 16); + } + else if (cmd == stm2GbX16.erase) { + *p = (ndbbr >> 6) << 17; + } + + return 0; +} + +static struct { + int type; + struct dfc_flash_info *flash_info; +} type_info[] = { + { DFC_FLASH_Samsung_512Mb_X_16, &samsung512MbX16}, + { DFC_FLASH_Micron_1Gb_X_8, µn1GbX8}, + { DFC_FLASH_Micron_1Gb_X_16, µn1GbX16}, + { DFC_FLASH_STM_1Gb_X_16, &stm1GbX16}, + { DFC_FLASH_STM_2Gb_X_16, &stm2GbX16}, + { DFC_FLASH_NULL, NULL}, +}; + +int dfc_get_flash_info(int type, struct dfc_flash_info **flash_info) +{ + uint32_t i = 0; + + while(type_info[i].type != DFC_FLASH_NULL) { + if (type_info[i].type == type) { + *flash_info = type_info[i].flash_info; + return 0; + } + i++; + } + *flash_info = NULL; + return -EINVAL; +} + +/****************************************************************************** + dfc_set_timing + + Description: + This function sets flash timing property in DFC timing register + according to input timing value embodied in context structure. + It is called once during the hardware initialization. + Input Parameters: + Output Parameters: + None + Returns: + None +*******************************************************************************/ +//#if defined(CONFIG_CPU_MONAHANS_L) || defined(CONFIG_CPU_MONAHANS_LV) +#define DFC_CLOCK 208 +//#else +//#define DFC_CLOCK 104 +//#endif +#define CLOCK_NS DFC_CLOCK/1000 + +void dfc_set_timing(struct dfc_context *context, struct dfc_flash_timing *t) +{ + struct dfc_flash_timing timing = *t; + + uint32_t r0 = 0; + uint32_t r1 = 0; + + /* + * num of clock cycles = time (ns) / one clock sycle (ns) + 1 + * - integer division will truncate the result, so add a 1 in all cases + * - subtract the extra 1 cycle added to all register timing values + */ + timing.tCH = min(((int) (timing.tCH * CLOCK_NS) + 1), + DFC_TIMING_MAX_tCH); + timing.tCS = min(((int) (timing.tCS * CLOCK_NS) + 1), + DFC_TIMING_MAX_tCS); + timing.tWH = min(((int) (timing.tWH * CLOCK_NS) + 1), + DFC_TIMING_MAX_tWH); + timing.tWP = min(((int) (timing.tWP * CLOCK_NS) + 1), + DFC_TIMING_MAX_tWP); + timing.tRH = min(((int) (timing.tRH * CLOCK_NS) + 1), + DFC_TIMING_MAX_tRH); + timing.tRP = min(((int) (timing.tRP * CLOCK_NS) + 1), + DFC_TIMING_MAX_tRP); + + r0 = (timing.tCH << DFC_TIMING_tCH) | + (timing.tCS << DFC_TIMING_tCS) | + (timing.tWH << DFC_TIMING_tWH) | + (timing.tWP << DFC_TIMING_tWP) | + (timing.tRH << DFC_TIMING_tRH) | + (timing.tRP << DFC_TIMING_tRP); + + dfc_write(context, DFC_NDTR0CS0, r0); + + timing.tR = min(((int) (timing.tR * CLOCK_NS) + 1), + DFC_TIMING_MAX_tR); + timing.tWHR = min(((int) (timing.tWHR * CLOCK_NS) + 1), + DFC_TIMING_MAX_tWHR); + timing.tAR = min(((int) (timing.tAR * CLOCK_NS) + 1), + DFC_TIMING_MAX_tAR); + + r1 = (timing.tR << DFC_TIMING_tR) | + (timing.tWHR << DFC_TIMING_tWHR) | + (timing.tAR << DFC_TIMING_tAR); + + dfc_write(context, DFC_NDTR1CS0, r1); + return; +} + +/****************************************************************************** + dfc_set_dma + + Description: + Enables or Disables DMA in line with setting in DFC mode of context + structure. DMA mode of DFC. Performs a read-modify-write operation that + only changes the driven DMA_EN bit field In DMA mode, all commands and + data are transferred by DMA. DMA can be enable/disable on the fly. + Input Parameters: + context -Pointer to DFC context structure + Output Parameters: + None + Returns: + None +*******************************************************************************/ +void +dfc_set_dma(struct dfc_context* context) +{ + uint32_t ndcr; + + ndcr = dfc_read(context, DFC_NDCR); + if (context->dfc_mode->enable_dma) + ndcr |= NDCR_DMA_EN; + else + ndcr &= ~NDCR_DMA_EN; + + dfc_write(context, DFC_NDCR, ndcr); + + /* Read again to make sure write work */ + ndcr = dfc_read(context, DFC_NDCR); + return; +} + + +/****************************************************************************** + dfc_set_ecc + + Description: + This function enables or disables hardware ECC capability of DFC in line + with setting in DFC mode of context structure. + Input Parameters: + context -Pointer to DFC context structure + Output Parameters: + None + Returns: + None +*******************************************************************************/ +void +dfc_set_ecc(struct dfc_context* context) +{ + uint32_t ndcr; + + ndcr = dfc_read(context, DFC_NDCR); + if (context->dfc_mode->enable_ecc) + ndcr |= NDCR_ECC_EN; + else + ndcr &= ~NDCR_ECC_EN; + + dfc_write(context, DFC_NDCR, ndcr); + + /* Read again to make sure write work */ + ndcr = dfc_read(context, DFC_NDCR); + return; +} + +/****************************************************************************** + dfc_set_spare + + Description: + This function enables or disables accesses to spare area of NAND Flash + through DFC in line with setting in DFC mode of context structure. + Input Parameters: + context -Pointer to DFC context structure + Output Parameters: + None + Returns: + None +*******************************************************************************/ +void +dfc_set_spare(struct dfc_context* context) +{ + uint32_t ndcr; + + ndcr = dfc_read(context, DFC_NDCR); + if (context->dfc_mode->enable_spare) + ndcr |= NDCR_SPARE_EN; + else + ndcr &= ~NDCR_SPARE_EN; + + dfc_write(context, DFC_NDCR, ndcr); + + /* Read again to make sure write work */ + ndcr = dfc_read(context, DFC_NDCR); + return; +} + +static unsigned int get_delta (unsigned int start) +{ + unsigned int stop = OSCR; + return (stop - start); +} + +static int dfc_wait_event(struct dfc_context *context, uint32_t event, + uint32_t *event_out, uint32_t timeout, int enable_int) +{ + uint32_t ndsr; + uint32_t to = 3 * timeout; /* 3 ticks ~ 1us */ + int status; + int start = OSCR; + + if (enable_int) + dfc_enable_int(context, event); + + while (1) { + ndsr = dfc_read(context, DFC_NDSR); + ndsr &= NDSR_MASK; + if (ndsr & event) { + /* event happened */ + *event_out = ndsr & event; + dfc_clear_int(context, *event_out); + status = 0; + break; + } else if (get_delta(start) > to) { + status = -ETIME; + break; + } + } + + if (enable_int) + dfc_disable_int(context, event); + return status; +} + +/****************************************************************************** + dfc_get_pattern + + Description: + This function is used to retrieve buffer size setting for a transaction + based on cmd. + Input Parameters: + context - Pointer to DFC context structure + cmd + Specifies type of command to be sent to NAND flash .The LSB of this + parameter defines the first command code for 2-cycles command. The + MSB defines the second command code for 2-cycles command. If MSB is + set to zero, this indicates that one cycle command + Output Parameters: + data_size + It is used to retrieve length of data transferred to/from DFC, + which includes padding bytes + padding + It is used to retrieve how many padding bytes there should be + in buffer of data_size. + Returns: + 0 + If size setting is returned successfully + -EINVAL + If page size specified in flash spec of context structure is not 512 or + 2048;If specified command index is not read1/program/erase/reset/readID/ + readStatus. +*******************************************************************************/ +int dfc_get_pattern(struct dfc_context *context, uint16_t cmd, + int *data_size, int *padding) +{ + struct dfc_mode* dfc_mode = context->dfc_mode; + struct dfc_flash_info * flash_info = context->flash_info; + uint32_t page_size = context->flash_info->page_size; /* 512 or 2048 */ + + if (cmd == flash_info->read1 || + cmd == flash_info->program) { + if (512 == page_size) { + /* add for DMA */ + if (dfc_mode->enable_dma) { + *data_size = DFC_DATA_SIZE_544; + if (dfc_mode->enable_ecc) + *padding = DFC_PADDING_SIZE_24; + else + *padding = DFC_PADDING_SIZE_16; + } else if (!dfc_mode->enable_spare) { + *data_size = DFC_DATA_SIZE_512; + *padding = DFC_PADDING_SIZE_0; + } else { + + if (dfc_mode->enable_ecc) + *data_size = DFC_DATA_SIZE_520; + else + *data_size = DFC_DATA_SIZE_528; + + *padding = DFC_PADDING_SIZE_0; + } + } else if (2048 == page_size) { + /* add for DMA */ + if (dfc_mode->enable_dma) { + *data_size = DFC_DATA_SIZE_2112; + if (dfc_mode->enable_ecc) + *padding = DFC_PADDING_SIZE_24; + else + *padding = DFC_PADDING_SIZE_0; + } else if (!dfc_mode->enable_spare) { + *data_size = DFC_DATA_SIZE_2048; + *padding = DFC_PADDING_SIZE_0; + } else { + + if (dfc_mode->enable_ecc) + *data_size = DFC_DATA_SIZE_2088; + else + *data_size = DFC_DATA_SIZE_2112; + + *padding = DFC_PADDING_SIZE_0; + } + } else /* if the page_size is neither 512 or 2048 */ + return -EINVAL; + } else if (cmd == flash_info->read_id) { + *data_size = DFC_DATA_SIZE_ID; + *padding = DFC_PADDING_SIZE_0; + } else if(cmd == flash_info->read_status) { + *data_size = DFC_DATA_SIZE_STATUS; + *padding = DFC_PADDING_SIZE_0; + } else if (cmd == flash_info->erase || cmd == flash_info->reset) { + *data_size = DFC_DATA_SIZE_UNUSED; + *padding = DFC_PADDING_SIZE_UNUSED; + } else + return -EINVAL; + return 0; +} + + +/****************************************************************************** + dfc_send_cmd + + Description: + This function configures DFC to send command through DFC to NAND flash + Input Parameters: + context + Pointer to DFC context structure + cmd + Specifies type of command to be sent to NAND flash .The LSB of this + parameter defines the first command code for 2-cycles command. The + MSB defines the second command code for 2-cycles command. If MSB is + set to zero, this indicates that one cycle command + addr + Address sent out to the flash device withthis command. For page read/ + program commands , 4-cycles address is sent. For erase command only + 3-cycles address is sent. If it is equal to 0xFFFFFFFF, the address + should not be used. + num_pages + It specifies the number of pages of data to be transferred for + a program or read commands. Unused for any other commands than + read/program. + + Output Parameters: + None + Returns: + 0 + If size setting is returned successfully + -EINVAL + If specified command index is not read1/program/erase/reset/readID/ + readStatus. +*******************************************************************************/ +int dfc_send_cmd(struct dfc_context *context, uint16_t cmd, + uint32_t addr, int num_pages) +{ + struct dfc_flash_info *flash_info = context->flash_info; + struct dfc_mode *dfc_mode = context->dfc_mode; + uint8_t cmd2; + uint32_t event_out; + uint32_t ndcb0=0, ndcb1=0, ndcb2=0, ndcr; + int status; + + /* It is a must to set ND_RUN firstly, then write command buffer + * If conversely,it does not work + */ + dfc_write(context, DFC_NDSR, NDSR_MASK); + + /* Set ND_RUN */ + ndcr = dfc_read(context, DFC_NDCR); + dfc_write(context, DFC_NDCR, (ndcr | NDCR_ND_RUN)); + + // Wait for write command request + status = dfc_wait_event(context, NDSR_WRCMDREQ, + &event_out, NAND_CMD_TIMEOUT, 0); + + if (status) /* Timeout */ + return status; + + cmd2 = (cmd>>8) & 0xFF; + ndcb0 = cmd | (dfc_mode->chip_select<<24) | ((cmd2?1:0)<<19); + + if (cmd == flash_info->read1) { + if (0xFFFFFFFF != addr) { + ndcb0 |= NDCB0_ADDR_CYC(4); + status = flash_info->addr2ndcb1(cmd, addr, &ndcb1); + if (status) + return status; + ndcb2 = (num_pages - 1) << 8; + } + } else if (cmd == flash_info->program) { + ndcb0 |= NDCB0_CMD_TYPE(1) | NDCB0_AUTO_RS; + ndcb0 |= NDCB0_ADDR_CYC(4); + status = flash_info->addr2ndcb1(cmd, addr, &ndcb1); + if (status) + return status; + ndcb2 = (num_pages-1) << 8; + } else if (cmd == flash_info->erase) { + ndcb0 |= NDCB0_CMD_TYPE(2) | NDCB0_AUTO_RS; + ndcb0 |= NDCB0_ADDR_CYC(3); + status = flash_info->addr2ndcb1(cmd, addr, &ndcb1); + if (status) + return status; + } else if (cmd == flash_info->read_id) { + ndcb0 |= NDCB0_CMD_TYPE(3); + } else if(cmd == flash_info->read_status) { + ndcb0 |= NDCB0_CMD_TYPE(4); + } else if(cmd == flash_info->reset) { + ndcb0 |= NDCB0_CMD_TYPE(5); + } else if (cmd == flash_info->lock) { + ndcb0 |= NDCB0_CMD_TYPE(5); + } else + return -EINVAL; + + /* Write to DFC command register */ + dfc_write(context, DFC_NDCB0, ndcb0); + dfc_write(context, DFC_NDCB0, ndcb1); + dfc_write(context, DFC_NDCB0, ndcb2); + + return 0; +} + +/****************************************************************************** + dfc_stop + + Description: + This function clears ND_RUN bit of NDCR. + Input Parameters: + context--Pointer to DFC context structure + Output Parameters: + None + Returns: + None +*******************************************************************************/ +void dfc_stop(struct dfc_context *context) +{ + unsigned int ndcr; + ndcr = dfc_read(context, DFC_NDCR); + dfc_write(context, DFC_NDCR, (ndcr & ~NDCR_ND_RUN)); + ndcr = dfc_read(context, DFC_NDCR); + + return; +} + +int dfc_setup_cmd_dma(struct dfc_context *context, + uint16_t cmd, uint32_t addr, int num_pages, + uint32_t *buf, uint32_t buf_phys, + uint32_t next_desc_phys, uint32_t dma_int_en, + struct pxa_dma_desc *dma_desc) +{ + struct dfc_flash_info *flash_info = context->flash_info; + struct dfc_mode *dfc_mode = context->dfc_mode; + uint8_t cmd2; + uint32_t event_out; + uint32_t ndcb0=0, ndcb1=0, ndcb2=0, ndcr; + int status; + + /* + * It is a must to set ND_RUN firstly, then write command buffer + * If conversely,it does not work + */ + dfc_write(context, DFC_NDSR, NDSR_MASK); + + /* Set ND_RUN */ + ndcr = dfc_read(context, DFC_NDCR); + ndcr |= NDCR_ND_RUN; + dfc_write(context, DFC_NDCR, ndcr); + + /* Wait for write command request */ + status = dfc_wait_event(context, NDSR_WRCMDREQ, + &event_out, NAND_CMD_TIMEOUT, 0); + + if (status) + return status; /* Timeout */ + + cmd2 = (cmd>>8) & 0xFF; + ndcb0 = cmd | (dfc_mode->chip_select<<24) | ((cmd2?1:0)<<19); + + if (cmd == flash_info->read1) { + if (0xFFFFFFFF != addr) { + ndcb0 |= NDCB0_ADDR_CYC(4); + status = flash_info->addr2ndcb1(cmd, addr, &ndcb1); + if (status) + return status; + ndcb2 = (num_pages-1) << 8; + } + } else if (cmd == flash_info->program) { + ndcb0 |= NDCB0_CMD_TYPE(1) | NDCB0_AUTO_RS; + ndcb0 |= NDCB0_ADDR_CYC(4); + + status = flash_info->addr2ndcb1(cmd, addr, &ndcb1); + if (status) + return status; + ndcb2 = (num_pages-1) << 8; + } else if (cmd == flash_info->erase) { + ndcb0 |= NDCB0_CMD_TYPE(2) | NDCB0_AUTO_RS; + ndcb0 |= NDCB0_ADDR_CYC(3); + + status = flash_info->addr2ndcb1(cmd, addr, &ndcb1); + if (status) + return status; + } else if (cmd == flash_info->read_id) { + ndcb0 |= NDCB0_CMD_TYPE(3); + } else if (cmd == flash_info->read_status) { + ndcb0 |= NDCB0_CMD_TYPE(4); + } else if (cmd == flash_info->reset) { + ndcb0 |= NDCB0_CMD_TYPE(5); + } else if (cmd == flash_info->lock) { + ndcb0 |= NDCB0_CMD_TYPE(5); + } else + return -EINVAL; + + *((uint32_t *)buf) = ndcb0; + *((uint32_t *)buf + 1) = ndcb1; + *((uint32_t *)buf + 2) = ndcb2; + + dma_int_en &= (DCMD_STARTIRQEN | DCMD_ENDIRQEN); + + dma_desc->ddadr = next_desc_phys; + dma_desc->dsadr = buf_phys; + dma_desc->dtadr = NDCB0_DMA_ADDR; + dma_desc->dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | dma_int_en | + DCMD_WIDTH4 | DCMD_BURST16 | 12; + return 0; +} + +int dfc_setup_data_dma(struct dfc_context* context, + uint16_t cmd, uint32_t buf_phys, + uint32_t next_desc_phys, uint32_t dma_int_en, + struct pxa_dma_desc* dma_desc) +{ + struct dfc_flash_info * flash_info = context->flash_info; + int data_size, padding; + + dfc_get_pattern(context, cmd, &data_size, &padding); + + dma_desc->ddadr = next_desc_phys; + dma_int_en &= (DCMD_STARTIRQEN | DCMD_ENDIRQEN); + + if (cmd == flash_info->program) { + + dma_desc->dsadr = buf_phys; + dma_desc->dtadr = NDDB_DMA_ADDR; + dma_desc->dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG | dma_int_en | + DCMD_WIDTH4 | DCMD_BURST32 | data_size; + + } else if (cmd == flash_info->read1 || cmd == flash_info->read_id || + cmd == flash_info->read_status) { + + dma_desc->dsadr = NDDB_DMA_ADDR; + dma_desc->dtadr = buf_phys; + dma_desc->dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC | dma_int_en | + DCMD_WIDTH4 | DCMD_BURST32 | data_size; + } + else + return -EINVAL; + return 0; +} + +void dfc_start_cmd_dma(struct dfc_context* context, struct pxa_dma_desc* dma_desc) +{ + DRCMR99 = DRCMR_MAPVLD | context->cmd_dma_ch; /* NAND CMD DRCMR */ + DDADR(context->cmd_dma_ch) = (uint32_t)dma_desc; + DCSR(context->cmd_dma_ch) |= DCSR_RUN; +} + +void dfc_start_data_dma(struct dfc_context* context, struct pxa_dma_desc* dma_desc) +{ + DRCMR97 = DRCMR_MAPVLD | context->data_dma_ch; + DDADR(context->data_dma_ch) = (uint32_t)dma_desc; + DCSR(context->data_dma_ch) |= DCSR_RUN; +} + +/****************************************************************************** + dfc_read_fifo_partial + + Description: + This function reads data from data buffer of DFC.Bytes can be any less than + or equal to data_size, the left is ignored by ReadFIFO though they will be + read from NDDB to clear data buffer. + Input Parameters: + context + Pointer to DFC context structure + nbytes + Indicating how much data should be read into buffer. + data_size + Specifing length of data transferred to/from DFC, which includes + padding bytes + Output Parameters: + pBuffer + Pointer to the data buffer where data should be placed. + Returns: + None +*******************************************************************************/ +void dfc_read_fifo_partial(struct dfc_context *context, uint8_t *buffer, + int nbytes, int data_size) +{ + uint32_t data = 0; + uint32_t i = 0; + uint32_t bytes_multi; + uint32_t bytes_remain; + + + if (1 == data_size) { + data = dfc_read(context, DFC_NDDB) & 0xFF; + *buffer++ = (uint8_t)data; + } else if (2 == data_size) { + data = dfc_read(context, DFC_NDDB) & 0xFFFF; + *buffer++ = data & 0xFF; + *buffer++ = (data >> 8) & 0xFF; + } else { + bytes_multi = (nbytes & 0xFFFFFFFC); + bytes_remain = nbytes & 0x03; + + i = 0; + /* Read the bytes_multi*4 bytes data */ + while (i < bytes_multi) { + data = dfc_read(context, DFC_NDDB); + /* FIXME: we don't know whether the buffer + * align to 4 bytes or not. Cast the buffer + * to int is not safe here. Especially under + * gcc 4.x. Used memcpy here. But the memcpy + * may be not correct on BE architecture. + * --by Yin, Fengwei + */ + memcpy(buffer, &data, sizeof(data)); + i += sizeof(data); + buffer += sizeof(data); + } + + /* Read the left bytes_remain bytes data */ + if (bytes_remain) { + data = dfc_read(context, DFC_NDDB); + for (i = 0; i < bytes_remain; i++) + *buffer++ = (uint8_t)((data >> (8*i)) & 0xFF); + } + + /* When read the remain bytes, we always read 4 bytes data + * to DFC. So the data_size should subtract following number. + */ + data_size -= bytes_multi + (bytes_remain ? sizeof(data) : 0); + + /* We need Read data_size bytes data totally */ + while (data_size > 0) { + data = dfc_read(context, DFC_NDDB); + data_size -= sizeof(data); + } + +/* + while(i < ((uint32_t)data_size) ) { + if (i < bytes_multi) { + temp = (uint32_t *)buffer; + *temp = dfc_reg->nddb; + } else if (i == bytes_multi && bytes_remain){ + uint32_t j = 0; + data = dfc_reg->nddb; + while (j++ < bytes_remain) { + *buffer++ = (uint8_t) \ + ((data>>(8*j)) & 0xFF); + } + } else { + data = dfc_reg->nddb; + } + i += 4; + buffer += 4; + } +*/ + } + return; +} + +/****************************************************************************** + dfc_write_fifo_partial + + Description: + Write to data buffer of DFC from a buffer. Bytes can be same as + data_size, also can be data_size-padding, but can¡¯t be random value, + the left will be automatically padded by WriteFIFO. + Input Parameters: + context + Pointer to DFC context structure + bytes + Indicating how much data should be read into buffer. + data_size + Specifing length of data transferred to/from DFC, which includes + padding bytes + buffer + Pointer to the data buffer where data will be taken from to be written + to DFC data buffer + Output Parameters: + None + Returns: + None +*******************************************************************************/ +void dfc_write_fifo_partial(struct dfc_context *context, uint8_t *buffer, + int nbytes, int data_size) +{ + uint32_t i = 0; + + uint32_t bytes_multi = (nbytes & 0xFFFFFFFC); + uint32_t bytes_remain = nbytes & 0x03; + uint32_t temp; + /* + * caller guarantee buffer contains appropriate data thereby + * it is impossible for nbytes not to be a multiple of 4 byte + */ + + /* Write the bytes_multi*4 bytes data */ + while (i < bytes_multi) { + temp = buffer[0] | buffer[1] << 8 | + buffer[2] << 16 | buffer[3] << 24; + dfc_write(context, DFC_NDDB, temp); + buffer += 4; + i += 4; + } + + /* Write the left bytes_remain bytes data */ + if (bytes_remain) { + temp = 0xFFFFFFFF; + for (i = 0; i < bytes_remain; i++) + temp &= *buffer++ << i*8; + + dfc_write(context, DFC_NDDB, temp); + } + + /* When write the remain bytes, we always write 4 bytes data + * to DFC. So the data_size should subtract following number. + */ + data_size -= bytes_multi + (bytes_remain ? sizeof(temp) : 0); + + while (data_size > 0) { + dfc_write(context, DFC_NDDB, 0xFFFFFFFF); + data_size -= 4; + } + +/* + while (i < ((uint32_t)data_size)) { + if (i < bytes_multi) { + temp = (uint32_t *)buffer; + dfc_reg->nddb = *temp; + } + else if (i == bytes_multi && bytes_remain) { + uint32_t j = 0, data = 0xFFFFFFFF; + while (j < bytes_remain) { + data &= (uint8_t)(*buffer) << j; + buffer++; + j++; + } + dfc_reg->nddb = data; + } + else { + dfc_reg->nddb = 0xFFFFFFFF; + } + i += 4; + buffer += 4; + } +*/ + + return; +} + +/****************************************************************************** + dfc_read_fifo + Description: + This function reads data from data buffer of DFC.Bytes can be any less + than or equal to data_size, the left is ignored by ReadFIFO though they + will be read from NDDB to clear data buffer. + Input Parameters: + context + Pointer to DFC context structure + nbytes + Indicating how much data should be read into buffer. + data_size + Specifing length of data transferred to/from DFC, which includes + padding bytes + Output Parameters: + buffer + Pointer to the data buffer where data should be placed. + Returns: + None +*******************************************************************************/ + +void dfc_read_fifo(struct dfc_context *context, uint8_t *buffer, int nbytes) +{ + uint32_t i = 0; + + uint32_t bytes_multi = (nbytes & 0xFFFFFFFC); + uint32_t bytes_remain = nbytes & 0x03; + uint32_t temp; + + /* Read the bytes_multi*4 bytes data */ + while (i < bytes_multi) { + temp = dfc_read(context, DFC_NDDB); + /* FIXME: we don't know whether the buffer + * align to 4 bytes or not. Cast the buffer + * to int is not safe here. Especially under + * gcc 4.x. Used memcpy here. But the memcpy + * may be not correct on BE architecture. + * --by Yin, Fengwei + */ + memcpy(buffer, &temp, sizeof(temp)); + i += sizeof(temp); + buffer += sizeof(temp); + } + + /* Read the left bytes_remain bytes data */ + temp = dfc_read(context, DFC_NDDB); + for (i = 0; i < bytes_remain; i++) { + *buffer++ = (uint8_t)((temp >> (8*i)) & 0xFF); + } + +/* + while (i < bytes_multi) { + temp = (uint32_t *)buffer; + *temp = dfc_reg->nddb; + i += 4; + buffer += 4; + } + + if (bytes_remain) { + data = dfc_reg->nddb; + for (i = 0; i < bytes_remain; i++) { + *buffer++ = (uint8_t)((data>>(8*i)) & 0xFF); + } + } +*/ + + return; +} + +/****************************************************************************** + dfc_write_fifo + Description: + Write to data buffer of DFC from a buffer.Bytes can be same as data_size, + also can be data_size-padding, but can¡¯t be random value, the left will + be automatically padded by WriteFIFO. + Input Parameters: + context + Pointer to DFC context structure + nbytes + Indicating how much data should be read into buffer. + data_size + Specifing length of data transferred to/from DFC, which includes + padding bytes + buffer + Pointer to the data buffer where data will be taken from to be written to + DFC data buffer + Output Parameters: + None + Returns: + None +*******************************************************************************/ +void dfc_write_fifo(struct dfc_context *context, uint8_t *buffer, int nbytes) +{ + uint32_t bytes_multi = (nbytes & 0xFFFFFFFC); + uint32_t bytes_remain = nbytes & 0x03; + uint32_t i=0; + uint32_t temp; + + /* Write the bytes_multi*4 bytes data */ + while (i < bytes_multi) { + temp = buffer[0] | buffer[1] << 8 | + buffer[2] << 16 | buffer[3] << 24; + dfc_write(context, DFC_NDDB, temp); + buffer += 4; + i += 4; + } + + /* Write the left bytes_remain bytes data */ + temp = 0xFFFFFFFF; + for (i = 0; i < bytes_remain; i++) + temp &= *buffer++ << i*8; + dfc_write(context, DFC_NDDB, temp); + +/* + while (i < nbytes) { + temp = (uint32_t *)buffer; + dfc_reg->nddb = *temp; + i += 4; + buffer += 4; + } +*/ +} + +/****************************************************************************** + dfc_read_badblock_addr + + Description: + This function reads bad block address in units of block starting from 0 + if bad block is detected. It takes into the account if the operation is + for CS0 or CS1 depending on settings of chip_select parameter of DFC + Mode structure. + Input Parameters: + context + Pointer to DFC context structure + Output Parameters: + pBadBlockAddr + Used to retrieve bad block address back to caller if bad block is + detected + Returns: + None +*******************************************************************************/ +void dfc_read_badblock_addr(struct dfc_context *context, uint32_t *bbaddr) +{ + uint32_t ndbdr; + if (0 == context->dfc_mode->chip_select) + ndbdr = dfc_read(context, DFC_NDBDR0); + else + ndbdr = dfc_read(context, DFC_NDBDR1); + + if (512 == context->flash_info->page_size) { + ndbdr = (ndbdr >> 5) & 0xFFF; + *bbaddr = ndbdr; + } else if (2048 == context->flash_info->page_size) { + /* 16 bits LB */ + ndbdr = (ndbdr >> 8); + *bbaddr = ndbdr; + } + return; +} + +/****************************************************************************** + dfc_enable_int + + Description: + This function is used to enable DFC interrupts. The bits in int_mask + will be used to unmask NDCR register to enable corresponding interrupts. + Input Parameters: + context + Pointer to DFC context structure + int_mask + Specifies what interrupts to enable + Output Parameters: + None + Returns: + None +*******************************************************************************/ +void dfc_enable_int(struct dfc_context *context, uint32_t int_mask) +{ + uint32_t ndcr; + + ndcr = dfc_read(context, DFC_NDCR); + ndcr &= ~int_mask; + dfc_write(context, DFC_NDCR, ndcr); + + ndcr = dfc_read(context, DFC_NDCR); + return; +} + +/****************************************************************************** + dfc_disable_int + + Description: + This function is used to disable DFC interrupts. + The bits inint_mask will be used to mask NDCR register to disable + corresponding interrupts. + Input Parameters: + context + Pointer to DFC context structure + int_mask + Specifies what interrupts to disable + Output Parameters: + None + Returns: + None +*******************************************************************************/ +void dfc_disable_int(struct dfc_context *context, uint32_t int_mask) +{ + uint32_t ndcr; + + ndcr = dfc_read(context, DFC_NDCR); + ndcr |= int_mask; + dfc_write(context, DFC_NDCR, ndcr); + + ndcr = dfc_read(context, DFC_NDCR); + return; +} + +/****************************************************************************** + dfc_clear_int + + Description: + This function is used to disable DFC interrupts. + The bits in int_mask will be used to clear corresponding interrupts + in NDCR register + Input Parameters: + context + Pointer to DFC context structure + int_mask + Specifies what interrupts to clear + Output Parameters: + None + Return