From 62155e17564a986215d61697c6b8a20cc0b4e07f Mon Sep 17 00:00:00 2001 From: Sergio Aguirre Date: Thu, 4 Feb 2010 18:12:37 -0600 Subject: [PATCH 14/71] OMAP3: CLOCK: Add capability to change rate of dpll4_m5_ck_3630 Add necessary clk_sel definitions to clock framework to allow changing dpll4_m5_ck_3630 rate. Based on patch by Tuukka Toivonen with subject: OMAP3: CLOCK: Add capability to change rate of dpll4_m5_ck Signed-off-by: Sergio Aguirre --- arch/arm/mach-omap2/clock34xx_data.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c index 89e2f61..8d101ef 100644 --- a/arch/arm/mach-omap2/clock34xx_data.c +++ b/arch/arm/mach-omap2/clock34xx_data.c @@ -934,6 +934,8 @@ static struct clk dpll4_m5_ck_3630 __initdata = { .clksel = div32_dpll4_clksel, .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, + .set_rate = &omap2_clksel_set_rate, + .round_rate = &omap2_clksel_round_rate, }; /* The PWRDN bit is apparently only available on 3430ES2 and above */ -- 1.6.6.1