/*
 * (C) Copyright 2006 Harald Welte <hwelte@hmw-consulting.de>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>

#if 0
#define DEBUGN	printf
#else
#define DEBUGN(x, args ...) {}
#endif

#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#if !defined(CFG_NAND_LEGACY)

#include <nand.h>
#include <s3c2410.h>

#define __REGb(x)	(*(volatile unsigned char *)(x))
#define __REGi(x)	(*(volatile unsigned int *)(x))

#define	NF_BASE		0x4e000000
#define	NFCONF		__REGi(NF_BASE + 0x0)
#define	NFCMD		__REGb(NF_BASE + 0x4)
#define	NFADDR		__REGb(NF_BASE + 0x8)
#define	NFDATA		__REGb(NF_BASE + 0xc)
#define	NFSTAT		__REGb(NF_BASE + 0x10)

#define S3C2410_NFCONF_EN          (1<<15)
#define S3C2410_NFCONF_512BYTE     (1<<14)
#define S3C2410_NFCONF_4STEP       (1<<13)
#define S3C2410_NFCONF_INITECC     (1<<12)
#define S3C2410_NFCONF_nFCE        (1<<11)
#define S3C2410_NFCONF_TACLS(x)    ((x)<<8)
#define S3C2410_NFCONF_TWRPH0(x)   ((x)<<4)
#define S3C2410_NFCONF_TWRPH1(x)   ((x)<<0)

static u16 s3c2410_read_word(struct mtd_info *mtd)
{
	unsigned char byte = 0;

	printf("s3c2410_read_word: WARNING, this function is not implemented yet\n");
	return byte;	
}

static void s3c2410_write_word(struct mtd_info *mtd, u16 word)
{
	printf("s3c2410_write_word: WARNING, this function is not implemented yet\n");
}

static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd)
{
	struct nand_chip *chip = mtd->priv;

	DEBUGN("hwcontrol(): 0x%02x: ", cmd);

	switch (cmd) {
	case NAND_CTL_SETNCE:
		NFCONF &= ~S3C2410_NFCONF_nFCE;
		DEBUGN("NFCONF=0x%08x\n", NFCONF);
		break;
	case NAND_CTL_CLRNCE:
		NFCONF |= S3C2410_NFCONF_nFCE;
		DEBUGN("NFCONF=0x%08x\n", NFCONF);
		break;
	case NAND_CTL_SETALE:
		chip->IO_ADDR_W = NF_BASE + 0x8;
		DEBUGN("SETALE\n");
		break;
	case NAND_CTL_SETCLE:
		chip->IO_ADDR_W = NF_BASE + 0x4;
		DEBUGN("SETCLE\n");
		break;
	default:
		chip->IO_ADDR_W = NF_BASE + 0xc;
		break;
	}
	return;
}

static int s3c2410_dev_ready(struct mtd_info *mtd)
{
	DEBUGN("dev_ready\n");
	return (NFSTAT & 0x01);
}

static void s3c2410_cmdfunc(struct mtd_info *mtd, unsigned cmd,
			    int column, int page_addr)
{
	DEBUGN("cmdfunc(): 0x%02x, col=%d, page=%d\n", cmd, column, page_addr);

	switch (cmd) {
	case NAND_CMD_READ0:
	case NAND_CMD_READ1:
	case NAND_CMD_READOOB:
		NFCMD = cmd;
		NFADDR = column & 0xff;
		NFADDR = page_addr & 0xff;
		NFADDR = (page_addr >> 8) & 0xff;
		NFADDR = (page_addr >> 16) & 0xff;
		break;
	case NAND_CMD_READID:
		NFCMD = cmd;
		NFADDR = 0;
		break;
	case NAND_CMD_PAGEPROG:
		NFCMD = cmd;
		printf("PAGEPROG not implemented\n");
		break;
	case NAND_CMD_ERASE1:
		NFCMD = cmd;
		NFADDR = page_addr & 0xff;
		NFADDR = (page_addr >> 8) & 0xff;
		NFADDR = (page_addr >> 16) & 0xff;
		break;
	case NAND_CMD_ERASE2:
		NFCMD = cmd;
		break;
	case NAND_CMD_SEQIN:
		printf("SEQIN not implemented\n");
		break;
	case NAND_CMD_STATUS:
		NFCMD = cmd;
		break;
	case NAND_CMD_RESET:
		NFCMD = cmd;
		break;
	default:
		break;
	}

	while (!s3c2410_dev_ready(mtd));
}

void board_nand_init(struct nand_chip *nand)
{
	u_int32_t cfg;
	u_int8_t tacls, twrph0, twrph1;
	S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();

	DEBUGN("board_nand_init()\n");

	clk_power->CLKCON |= (1 << 4);

	/* initialize hardware */
	twrph0 = 3; twrph1 = 0; tacls = 0;

	/* default timings: maximum */
	//twrph0 = 8; twrph1 = 8; tacls = 8;

	cfg = S3C2410_NFCONF_EN;
	cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
	cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
	cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);

	//NFCONF = cfg;
	NFCONF = 0xf842;

	/* initialize nand_chip data structure */
	nand->IO_ADDR_R = nand->IO_ADDR_W = 0x4e00000c;

	/* read_buf and write_buf are default */
	/* read_byte and write_byte are default */

	/* need to override word read/write since default routines try 16bit wide
	 * register access of an (in our case) 8bit register */
	nand->read_word = s3c2410_read_word;
	nand->write_word = s3c2410_write_word;

	/* hwcontrol always must be implemented */
	nand->hwcontrol = s3c2410_hwcontrol;

	nand->dev_ready = s3c2410_dev_ready;

	nand->eccmode = NAND_ECC_SOFT;
	nand->options = 0;
	//nand->waitfunc = dfc_wait;

	//nand->cmdfunc = s3c2410_cmdfunc;
	//nand->autooob = &delta_oob;
	//nand->badblock_pattern = &delta_bbt_descr;
	
#if 0
	/* reset */
	nand->hwcontrol(NULL, NAND_CTL_SETNCE);
	nand->cmdfunc(NULL, NAND_CMD_RESET, -1, -1);
	while (nand->dev_ready(NULL) == 0) {}
	nand->hwcontrol(NULL, NAND_CTL_CLRNCE);
#endif

	DEBUGN("end of nand_init\n");
}

#else
 #error "U-Boot legacy NAND support not available for S3C2410"
#endif
#endif
