--- 050125/include/asm-arm/proc-armv/ptrace.h Tue Jan 25 00:22:44 2005 +++ 050218/include/asm-arm/proc-armv/ptrace.h Thu Feb 17 16:13:54 2005 @@ -40,6 +40,10 @@ struct pt_regs { long uregs[18]; +#if defined(CONFIG_CPU_PXA27X) + long cpar; + long mmx[ 16*2 + 6 + 1 ]; +#endif }; #define ARM_cpsr uregs[16] --- 050125/include/asm-arm/sigcontext.h Tue Jan 25 00:22:42 2005 +++ 050218/include/asm-arm/sigcontext.h Thu Feb 17 18:16:28 2005 @@ -28,6 +28,10 @@ unsigned long arm_pc; unsigned long arm_cpsr; unsigned long fault_address; +#if defined(CONFIG_CPU_PXA27X) + unsigned long arm_cpar; + unsigned long arm_mmx[ 16*2 + 6 + 1 ]; +#endif }; --- 050125/include/asm-arm/elf.h Tue Jan 25 00:54:49 2005 +++ 050218/include/asm-arm/elf.h Thu Feb 17 16:19:02 2005 @@ -1,6 +1,8 @@ #ifndef __ASMARM_ELF_H #define __ASMARM_ELF_H +#include <linux/config.h> + /* * ELF register definitions.. */ @@ -14,6 +16,7 @@ #define EM_ARM 40 #define EF_ARM_APCS26 0x08 +#define EF_ARM_SOFT_FLOAT 0x200 #define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t)) typedef elf_greg_t elf_gregset_t[ELF_NGREG]; --- 050125/arch/arm/kernel/entry-armv.S Tue Jan 25 00:21:45 2005 +++ 050218/arch/arm/kernel/entry-armv.S Fri Feb 18 07:29:34 2005 @@ -271,7 +271,7 @@ tst \irqstat, #IRQ_MASK_DOORBELLHOST movne \irqnr, #IRQ_DOORBELLHOST bne 1001f - + tst \irqstat, #IRQ_MASK_I2OINPOST movne \irqnr, #IRQ_I2OINPOST bne 1001f @@ -494,12 +494,12 @@ #elif defined(CONFIG_ARCH_L7200) #include <asm/hardware.h> - + .equ irq_base_addr, IO_BASE_2 .macro disable_fiq .endm - + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp mov \irqstat, #irq_base_addr @ Virt addr IRQ regs add \irqstat, \irqstat, #0x00001000 @ Status reg @@ -589,7 +589,7 @@ .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - + /* Read all interrupts pending... */ ldr \irqnr, =IO_ADDRESS(PLAT_PERIPHERAL_BASE) + OMAHA_INTPND ldr \irqstat, [\irqnr] /* INTPND */ @@ -607,7 +607,7 @@ .endm .macro irq_prio_table - .endm + .endm #elif defined(CONFIG_ARCH_CLPS711X) @@ -654,23 +654,23 @@ .macro irq_prio_table .endm - + #elif defined (CONFIG_ARCH_CAMELOT) #include <asm/arch/platform.h> #undef IRQ_MODE /* same name defined in asm/proc/ptrace.h */ #include <asm/arch/int_ctrl00.h> - + .macro disable_fiq .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - + ldr \irqstat, =INT_ID(IO_ADDRESS(EXC_INT_CTRL00_BASE)) - ldr \irqnr,[\irqstat] + ldr \irqnr,[\irqstat] cmp \irqnr,#0 subne \irqnr,\irqnr,#1 - + .endm .macro irq_prio_table @@ -910,7 +910,7 @@ mov pc, r7 @ check, if this is a relevant code cmp r0, #0 @ check return value beq 1f @ else let linux do what it has to do -2: +2: #endif #ifndef CONFIG_KGDB adrsvc al, r9, 1f @ r9 = normal FP return @@ -977,6 +977,9 @@ stmia r5, {r2 - r4} @ Save USR pc, cpsr, old_r0 stmdb r5, {sp, lr}^ alignment_trap r7, r7, __temp_abt +#ifdef CONFIG_CPU_PXA27X + save_user_mmx +#endif zero_fp mov r0, r2 @ remove once everyones in sync #ifdef MULTI_CPU @@ -1001,6 +1004,9 @@ stmia r8, {r5 - r7} @ save pc, psr, old_r0 stmdb r8, {sp, lr}^ alignment_trap r4, r7, __temp_irq +#ifdef CONFIG_CPU_PXA27X + save_user_mmx +#endif zero_fp get_current_task tsk #ifdef CONFIG_PREEMPT @@ -1039,6 +1045,9 @@ stmia r8, {r5 - r7} @ Save USR pc, cpsr, old_r0 stmdb r8, {sp, lr}^ @ Save user sp, lr alignment_trap r4, r7, __temp_und +#ifdef CONFIG_CPU_PXA27X + save_user_mmx +#endif zero_fp tst r6, #T_BIT @ Thumb mode bne fpundefinstr @@ -1068,6 +1077,9 @@ stmia r8, {r5 - r7} @ Save USR pc, cpsr, old_r0 stmdb r8, {sp, lr}^ @ Save sp_usr lr_usr alignment_trap r4, r7, __temp_abt +#ifdef CONFIG_CPU_PXA27X + save_user_mmx +#endif zero_fp mov r0, #MODE_SVC msr cpsr_c, r0 @ Enable interrupts @@ -1394,7 +1406,7 @@ stmfd sp!, {r4, r5} #endif mrc p15, 0, r2, c3, c0 - str r2, [sp, #-4]! + str r2, [sp, #-4]! ldr r2, [r0] str sp, [r2] --- 050125/arch/arm/kernel/entry-header.S Tue Jan 25 00:21:45 2005 +++ 050218/arch/arm/kernel/entry-header.S Thu Feb 17 20:15:24 2005 @@ -42,9 +42,44 @@ @ Stack format (ensured by USER_* and SVC_*) @ #ifdef CONFIG_CPU_32 -#define S_FRAME_SIZE 72 -#define S_OLD_R0 68 -#define S_PSR 64 +#ifdef CONFIG_CPU_PXA27X + #define S_MMX 80 + + #define MMX_WR0 (0x00) + #define MMX_WR1 (0x08) + #define MMX_WR2 (0x10) + #define MMX_WR3 (0x18) + #define MMX_WR4 (0x20) + #define MMX_WR5 (0x28) + #define MMX_WR6 (0x30) + #define MMX_WR7 (0x38) + #define MMX_WR8 (0x40) + #define MMX_WR9 (0x48) + #define MMX_WR10 (0x50) + #define MMX_WR11 (0x58) + #define MMX_WR12 (0x60) + #define MMX_WR13 (0x68) + #define MMX_WR14 (0x70) + #define MMX_WR15 (0x78) + #define MMX_WCSSF (0x80) + #define MMX_WCASF (0x84) + #define MMX_WCGR0 (0x88) + #define MMX_WCGR1 (0x8C) + #define MMX_WCGR2 (0x90) + #define MMX_WCGR3 (0x94) + + #define MMX_SIZE (0x98) + + #define S_FRAME_SIZE (76+4+MMX_SIZE) + + #define S_CPAR 72 + #define S_OLD_R0 68 + #define S_PSR 64 +#else + #define S_FRAME_SIZE 72 + #define S_OLD_R0 68 + #define S_PSR 64 +#endif #else #define S_FRAME_SIZE 68 #define S_OLD_R0 64 @@ -88,6 +123,43 @@ set_cpsr_c \temp, #MODE_SVC .endm +#ifdef CONFIG_CPU_PXA27X + .macro save_user_mmx + mrc p15, 0, r0, c15, c1, 0 + str r0, [sp, #S_CPAR] @ Save CPAR + cmp r0, #3 + bne 1f + add r0,sp,#S_MMX @ StoreMMX + bic r0, r0, #7 + wstrw wCSSF, [r0, #MMX_WCSSF] + wstrw wCASF, [r0, #MMX_WCASF] + wstrw wCGR0, [r0, #MMX_WCGR0] + wstrw wCGR1, [r0, #MMX_WCGR1] + wstrw wCGR2, [r0, #MMX_WCGR2] + wstrw wCGR3, [r0, #MMX_WCGR3] + wstrd wR0, [r0, #MMX_WR0] + wstrd wR1, [r0, #MMX_WR1] + wstrd wR2, [r0, #MMX_WR2] + wstrd wR3, [r0, #MMX_WR3] + wstrd wR4, [r0, #MMX_WR4] + wstrd wR5, [r0, #MMX_WR5] + wstrd wR6, [r0, #MMX_WR6] + wstrd wR7, [r0, #MMX_WR7] + wstrd wR8, [r0, #MMX_WR8] + wstrd wR9, [r0, #MMX_WR9] + wstrd wR10, [r0, #MMX_WR10] + wstrd wR11, [r0, #MMX_WR11] + wstrd wR12, [r0, #MMX_WR12] + wstrd wR13, [r0, #MMX_WR13] + wstrd wR14, [r0, #MMX_WR14] + wstrd wR15, [r0, #MMX_WR15] +1: + mov r0, #1 + mcr p15, 0, r0, c15, c1, 0 @ CP0 Only. + ldr r0, [sp] @ Restore R0 + .endm +#endif + .macro save_user_regs sub sp, sp, #S_FRAME_SIZE stmia sp, {r0 - r12} @ Calling r0 - r12 @@ -97,12 +169,44 @@ str lr, [sp, #S_PC] @ Save calling PC str r8, [sp, #S_PSR] @ Save CPSR str r0, [sp, #S_OLD_R0] @ Save OLD_R0 + save_user_mmx .endm /* * Must be called with IRQs already disabled. */ .macro restore_user_regs +#ifdef CONFIG_CPU_PXA27X + ldr r1, [sp, #S_CPAR] + mcr p15, 0, r1, c15, c1, 0 + cmp r1, #3 + bne 2f + add r1,sp,#S_MMX @ LoadMMX + bic r1, r1, #7 + wldrd wR0, [r1, #MMX_WR0] + wldrd wR1, [r1, #MMX_WR1] + wldrd wR2, [r1, #MMX_WR2] + wldrd wR3, [r1, #MMX_WR3] + wldrd wR4, [r1, #MMX_WR4] + wldrd wR5, [r1, #MMX_WR5] + wldrd wR6, [r1, #MMX_WR6] + wldrd wR7, [r1, #MMX_WR7] + wldrd wR8, [r1, #MMX_WR8] + wldrd wR9, [r1, #MMX_WR9] + wldrd wR10, [r1, #MMX_WR10] + wldrd wR11, [r1, #MMX_WR11] + wldrd wR12, [r1, #MMX_WR12] + wldrd wR13, [r1, #MMX_WR13] + wldrd wR14, [r1, #MMX_WR14] + wldrd wR15, [r1, #MMX_WR15] + wldrw wCSSF, [r1, #MMX_WCSSF] + wldrw wCASF, [r1, #MMX_WCASF] + wldrw wCGR0, [r1, #MMX_WCGR0] + wldrw wCGR1, [r1, #MMX_WCGR1] + wldrw wCGR2, [r1, #MMX_WCGR2] + wldrw wCGR3, [r1, #MMX_WCGR3] +2: +#endif ldr r1, [sp, #S_PSR] @ Get calling cpsr ldr lr, [sp, #S_PC]! @ Get PC msr spsr, r1 @ save in spsr_svc @@ -116,6 +220,37 @@ * Must be called with IRQs already disabled. */ .macro fast_restore_user_regs +#ifdef CONFIG_CPU_PXA27X + ldr r1, [sp, #S_OFF + S_CPAR] + mcr p15, 0, r1, c15, c1, 0 + cmp r1, #3 + bne 3f + add r1,sp,#S_OFF + S_MMX @ LoadMMX + bic r1, r1, #7 + wldrd wR0, [r1, #MMX_WR0] + wldrd wR1, [r1, #MMX_WR1] + wldrd wR2, [r1, #MMX_WR2] + wldrd wR3, [r1, #MMX_WR3] + wldrd wR4, [r1, #MMX_WR4] + wldrd wR5, [r1, #MMX_WR5] + wldrd wR6, [r1, #MMX_WR6] + wldrd wR7, [r1, #MMX_WR7] + wldrd wR8, [r1, #MMX_WR8] + wldrd wR9, [r1, #MMX_WR9] + wldrd wR10, [r1, #MMX_WR10] + wldrd wR11, [r1, #MMX_WR11] + wldrd wR12, [r1, #MMX_WR12] + wldrd wR13, [r1, #MMX_WR13] + wldrd wR14, [r1, #MMX_WR14] + wldrd wR15, [r1, #MMX_WR15] + wldrw wCSSF, [r1, #MMX_WCSSF] + wldrw wCASF, [r1, #MMX_WCASF] + wldrw wCGR0, [r1, #MMX_WCGR0] + wldrw wCGR1, [r1, #MMX_WCGR1] + wldrw wCGR2, [r1, #MMX_WCGR2] + wldrw wCGR3, [r1, #MMX_WCGR3] +3: +#endif ldr r1, [sp, #S_OFF + S_PSR] @ get calling cpsr ldr lr, [sp, #S_OFF + S_PC]! @ get pc msr spsr, r1 @ save in spsr_svc --- 050125/arch/arm/kernel/signal.c Tue Jan 25 00:21:45 2005 +++ 050218/arch/arm/kernel/signal.c Thu Feb 17 18:22:10 2005 @@ -198,6 +198,13 @@ { int err = 0; +#if defined(CONFIG_CPU_PXA27X) + int _m; + __get_user_error(regs->cpar, &sc->arm_cpar, err); + for( _m=0; _m<16*2 + 6 + 1; ++_m ) { + __get_user_error(regs->mmx[ _m ], &sc->arm_mmx[ _m ], err); + } +#endif __get_user_error(regs->ARM_r0, &sc->arm_r0, err); __get_user_error(regs->ARM_r1, &sc->arm_r1, err); __get_user_error(regs->ARM_r2, &sc->arm_r2, err); @@ -312,6 +319,13 @@ { int err = 0; +#if defined(CONFIG_CPU_PXA27X) + int _m; + __put_user_error(regs->cpar, &sc->arm_cpar, err); + for( _m=0; _m<16*2 + 6 + 1; ++_m ) { + __put_user_error(regs->mmx[ _m ], &sc->arm_mmx[ _m ], err); + } +#endif __put_user_error(regs->ARM_r0, &sc->arm_r0, err); __put_user_error(regs->ARM_r1, &sc->arm_r1, err); __put_user_error(regs->ARM_r2, &sc->arm_r2, err); --- 050125/arch/arm/Makefile Tue Jan 25 00:21:44 2005 +++ 050218/arch/arm/Makefile Thu Feb 17 09:38:40 2005 @@ -69,7 +69,8 @@ ifeq ($(CONFIG_ARCH_SHARP_SL),y) CROSS_COMPILE = arm-linux- -arch-y :=-D__LINUX_ARM_ARCH__=4 -march=armv4 -Wa,-mxscale +#arch-y :=-D__LINUX_ARM_ARCH__=4 -march=armv4 -Wa,-mxscale +arch-y :=-D__LINUX_ARM_ARCH__=4 -Wa,-mcpu=iwmmxt tune-y :=-mtune=strongarm endif @@ -212,7 +213,7 @@ MACHINE = omaha endif -ifeq ($(CONFIG_XIP_KERNEL),y) +ifeq ($(CONFIG_XIP_KERNEL),y) DATAADDR := $(TEXTADDR) # Replace phys addr with virt addr while keeping offset from base. # Virt base addr also defined in include/asm-arm/arch-*/hardware.h --- 050125/fs/binfmt_elf.c Tue Jan 25 00:22:37 2005 +++ 050218/fs/binfmt_elf.c Thu Feb 17 08:52:54 2005 @@ -815,6 +815,15 @@ ELF_PLAT_INIT(regs); #endif +#if defined(CONFIG_CPU_PXA27X) + if( elf_ex.e_flags & EF_ARM_SOFT_FLOAT ) { + regs->cpar = 0x03; //CP0 CP1 Used. + } + else { + regs->cpar = 0x01; //CP0 Only. + } +#endif + start_thread(regs, elf_entry, bprm->p); if (current->ptrace & PT_PTRACED) send_sig(SIGTRAP, current, 0);