From 41019c38e9fb5ebd296106e3edeb391b8e323115 Mon Sep 17 00:00:00 2001 From: Florian Boor Date: Fri, 10 Sep 2010 19:06:18 +0200 Subject: linux: Add 2.6.28 patches and config for Mini6410. --- recipes/linux/linux-2.6.28/mini6410/defconfig | 1716 + recipes/linux/linux-2.6.28/mini6410/mini6410.patch | 192017 ++++++++++++++++++ .../linux/linux-2.6.28/mini6410/undefined.patch | 11 + recipes/linux/linux_2.6.28.bb | 9 + 4 files changed, 193753 insertions(+) create mode 100644 recipes/linux/linux-2.6.28/mini6410/defconfig create mode 100644 recipes/linux/linux-2.6.28/mini6410/mini6410.patch create mode 100644 recipes/linux/linux-2.6.28/mini6410/undefined.patch (limited to 'recipes') diff --git a/recipes/linux/linux-2.6.28/mini6410/defconfig b/recipes/linux/linux-2.6.28/mini6410/defconfig new file mode 100644 index 0000000000..45cd4f9d9a --- /dev/null +++ b/recipes/linux/linux-2.6.28/mini6410/defconfig @@ -0,0 +1,1716 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.28.6 +# Fri Sep 10 15:29:39 2010 +# +CONFIG_ARM=y +# CONFIG_HAVE_PWM is not set +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +# CONFIG_GENERIC_TIME is not set +# CONFIG_GENERIC_CLOCKEVENTS is not set +CONFIG_MMU=y +CONFIG_NO_IOPORT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_CLASSIC_RCU=y +CONFIG_FREEZER=y + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +CONFIG_ARCH_S3C64XX=y +# CONFIG_ARCH_S5P64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +CONFIG_PLAT_S3C64XX=y +CONFIG_CPU_S3C6400_INIT=y +CONFIG_CPU_S3C6400_CLOCK=y +CONFIG_S3C64XX_SETUP_I2C0=y +# CONFIG_S3C64XX_ADC is not set +CONFIG_S3C64XX_DEV_FIMC0=y +CONFIG_S3C64XX_DEV_FIMC1=y +CONFIG_S3C64XX_SETUP_FIMC0=y +CONFIG_S3C64XX_SETUP_FIMC1=y +# CONFIG_S3C6410_PWM is not set +CONFIG_NONE_PWM=y +CONFIG_PLAT_S3C=y + +# +# Boot options +# +# CONFIG_S3C_BOOT_WATCHDOG is not set +CONFIG_S3C_BOOT_ERROR_RESET=y + +# +# Power management +# +# CONFIG_S3C2410_PM_DEBUG is not set +# CONFIG_S3C2410_PM_CHECK is not set +CONFIG_S3C_LOWLEVEL_UART_PORT=0 +# CONFIG_SPLIT_ROOT_FILESYSTEM is not set +CONFIG_S3C_GPIO_SPACE=0 +CONFIG_S3C_GPIO_TRACK=y +CONFIG_S3C_GPIO_PULL_UPDOWN=y +CONFIG_S3C_GPIO_CFG_S3C24XX=y +CONFIG_S3C_GPIO_CFG_S3C64XX=y +CONFIG_S3C_DEV_HSMMC=y +CONFIG_S3C_DEV_HSMMC1=y +CONFIG_S3C_DEV_HSMMC2=y +CONFIG_S3C_DMA_PL080=y +CONFIG_CPU_S3C6410=y +CONFIG_S3C6410_SETUP_SDHCI=y +CONFIG_MACH_SMDK6410=y + +# +# SMDK6410 MMC/SD slot setup +# +CONFIG_SMDK6410_SD_CH0=y +# CONFIG_SMDK6410_SD_CH1 is not set +# CONFIG_SMDK6410_SD_CH2 is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_V6=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +# CONFIG_OUTER_CACHE is not set +CONFIG_ARM_VIC=y +CONFIG_DMABOUNCE=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT=y +CONFIG_HZ=200 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_APM_EMULATION=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_S3C=y +# CONFIG_MTD_NAND_S3C_DEBUG is not set +CONFIG_MTD_NAND_S3C_HWECC=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +CONFIG_DM9000=y +CONFIG_DM9000_DEBUGLEVEL=4 +# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set +# CONFIG_SMC911X is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=480 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=272 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_S3C=y +# CONFIG_TOUCHSCREEN_NEW is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_WM97XX is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_DEVKMEM is not set +CONFIG_LEDS_MINI6410=y +CONFIG_MINI6410_HELLO_MODULE=m +CONFIG_MINI6410_BUTTONS=y +CONFIG_MINI6410_BUZZER=y +# CONFIG_MINI6410_ADC is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_UARTS=4 +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_SERIAL_S3C6400=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_S3C_MEM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_S3C2410=y +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_AT24 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_TPS65010 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_S3C2410_WATCHDOG=y + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_UCB1400_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +# CONFIG_VIDEO_ALLOW_V4L1 is not set +CONFIG_VIDEO_V4L1_COMPAT=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEOBUF_GEN=y +CONFIG_VIDEOBUF_VMALLOC=y +CONFIG_VIDEO_IR=y +CONFIG_VIDEO_TVEEPROM=y +CONFIG_VIDEO_TUNER=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +CONFIG_VIDEO_FIXED_MINOR_RANGES=y +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set +CONFIG_VIDEO_IR_I2C=y + +# +# Encoders/decoders and other helper chips +# + +# +# Audio decoders +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TDA9875 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +CONFIG_VIDEO_MSP3400=y +# CONFIG_VIDEO_CS5345 is not set +CONFIG_VIDEO_CS53L32A=y +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +CONFIG_VIDEO_WM8775=y +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set + +# +# Video decoders +# +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_TCM825X is not set +CONFIG_VIDEO_SAA711X=y +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_TVP5150 is not set + +# +# Video and audio decoders +# +CONFIG_VIDEO_CX25840=y + +# +# MPEG video encoders +# +CONFIG_VIDEO_CX2341X=y + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_SOC_CAMERA is not set +CONFIG_V4L_USB_DRIVERS=y +CONFIG_USB_VIDEO_CLASS=y +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_GSPCA=y +CONFIG_USB_M5602=y +CONFIG_USB_GSPCA_CONEX=y +CONFIG_USB_GSPCA_ETOMS=y +CONFIG_USB_GSPCA_FINEPIX=y +CONFIG_USB_GSPCA_MARS=y +CONFIG_USB_GSPCA_OV519=y +CONFIG_USB_GSPCA_PAC207=y +CONFIG_USB_GSPCA_PAC7311=y +CONFIG_USB_GSPCA_SONIXB=y +CONFIG_USB_GSPCA_SONIXJ=y +CONFIG_USB_GSPCA_SPCA500=y +CONFIG_USB_GSPCA_SPCA501=y +CONFIG_USB_GSPCA_SPCA505=y +CONFIG_USB_GSPCA_SPCA506=y +CONFIG_USB_GSPCA_SPCA508=y +CONFIG_USB_GSPCA_SPCA561=y +CONFIG_USB_GSPCA_STK014=y +CONFIG_USB_GSPCA_SUNPLUS=y +CONFIG_USB_GSPCA_T613=y +CONFIG_USB_GSPCA_TV8532=y +CONFIG_USB_GSPCA_VC032X=y +CONFIG_USB_GSPCA_ZC3XX=y +CONFIG_VIDEO_PVRUSB2=y +CONFIG_VIDEO_PVRUSB2_SYSFS=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_EM28XX=y +# CONFIG_VIDEO_EM28XX_ALSA is not set +CONFIG_VIDEO_USBVISION=y +CONFIG_USB_ET61X251=y +CONFIG_USB_SN9C102=y +CONFIG_USB_ZC0301=y +CONFIG_USB_ZR364XX=y +CONFIG_USB_STKWEBCAM=y +CONFIG_USB_S2255=y +CONFIG_VIDEO_SAMSUNG=y + +# +# FIMC configurations +# +CONFIG_VIDEO_FIMC=y +CONFIG_VIDEO_FIMC_DEBUG=y +# CONFIG_S5K4BA is not set +# CONFIG_S5K3BA is not set +CONFIG_OV965X=y +CONFIG_OV965X_VGA=y +# CONFIG_OV965X_QVGA is not set +# CONFIG_OV965X_SVGA is not set +# CONFIG_OV965X_SXGA is not set +CONFIG_VIDEO_FIMC_CAM_CH=0 +CONFIG_VIDEO_FIMC_CAM_RESET=1 +CONFIG_VIDEO_POST=y +CONFIG_VIDEO_MFC10=y +CONFIG_VIDEO_MFC_DEBUG=y +CONFIG_VIDEO_JPEG=y +CONFIG_VIDEO_TV=y +CONFIG_VIDEO_ROTATOR=y +CONFIG_VIDEO_G2D=y +CONFIG_VIDEO_G3D=y +CONFIG_VIDEO_CMM=y + +# +# Reserved memory configurations +# +CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC=15360 +CONFIG_VIDEO_SAMSUNG_MEMSIZE_POST=8192 +CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV=8192 +CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC=6144 +CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG=8192 +CONFIG_VIDEO_SAMSUNG_MEMSIZE_CMM=8192 +# CONFIG_RADIO_ADAPTERS is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +CONFIG_FB_S3C=y +CONFIG_FB_S3C_TFT480272=y +# CONFIG_FB_S3C_TFT800480 is not set +# CONFIG_FB_S3C_T240320 is not set +# CONFIG_FB_S3C_TFT640480 is not set +# CONFIG_FB_S3C_VGA1024768 is not set +# CONFIG_FB_S3C_VGA800600 is not set +# CONFIG_FB_S3C_VGA640480 is not set +# CONFIG_FB_S3C_EZVGA800600 is not set +CONFIG_FB_S3C_BPP=y +# CONFIG_FB_S3C_BPP_8 is not set +CONFIG_FB_S3C_BPP_16=y +# CONFIG_FB_S3C_BPP_24 is not set +# CONFIG_FB_S3C_BPP_28 is not set +# CONFIG_FB_S3C_BPP_32 is not set +CONFIG_FB_S3C_NUM=4 +# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set +CONFIG_FB_S3C_DOUBLE_BUFFERING=y +# CONFIG_FB_S1D13XXX is not set +CONFIG_BACKLIGHT_FRIENDLY_ARM=y +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224 is not set +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_VMASTER=y +CONFIG_SND_AC97_CODEC=y +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +# CONFIG_SND_AC97_POWER_SAVE is not set +CONFIG_SND_ARM=y +CONFIG_SND_USB=y +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_CAIAQ is not set +CONFIG_SND_SOC=y +CONFIG_SND_SOC_AC97_BUS=y + +# +# SoC Audio for the Samsung S3C +# +CONFIG_SND_S3C64XX_SOC=y +CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713=y +# CONFIG_SOUND_WM9713_INPUT_STREAM_LINE is not set +CONFIG_SOUND_WM9713_INPUT_STREAM_MIC=y +CONFIG_SND_S3C6410_SOC_AC97=y +# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8580 is not set +# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990 is not set +# CONFIG_SND_S3C64XX_SOC_SMDK6410_S5M8751 is not set +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_WM9713=y +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=y +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HID_DEBUG=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +# CONFIG_HID_COMPAT is not set +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DELL=y +CONFIG_HID_EZKEY=y +CONFIG_HID_GYRATION=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +CONFIG_USB_DEBUG=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_S3C_OTG_HOST is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; +# + +# +# see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=y +# CONFIG_USB_SERIAL_CONSOLE is not set +# CONFIG_USB_EZUSB is not set +# CONFIG_USB_SERIAL_GENERIC is not set +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_CP2101 is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +CONFIG_USB_SERIAL_PL2303=y +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C2410 is not set +CONFIG_USB_GADGET_S3C_OTGD=y +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set + +# +# NOTE: S3C OTG device role enables the controller driver below +# +CONFIG_USB_S3C_OTGD=y +CONFIG_USB_GADGET_S3C_OTGD_DMA_MODE=y +# CONFIG_USB_GADGET_S3C_OTGD_SLAVE_MODE is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +CONFIG_SDIO_UART=y +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_S3C=y +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_S3C=y +# CONFIG_DMADEVICES is not set +# CONFIG_REGULATOR is not set +# CONFIG_UIO is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=936 +CONFIG_FAT_DEFAULT_IOCHARSET="utf8" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_YAFFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_SUMMARY=y +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_XATTR=y +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +CONFIG_NLS_CODEPAGE_936=y +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_S3C_UART=0 + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y diff --git a/recipes/linux/linux-2.6.28/mini6410/mini6410.patch b/recipes/linux/linux-2.6.28/mini6410/mini6410.patch new file mode 100644 index 0000000000..a9c908b5b6 --- /dev/null +++ b/recipes/linux/linux-2.6.28/mini6410/mini6410.patch @@ -0,0 +1,192017 @@ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/ChangeLog linux-2.6.28.6/ChangeLog +--- linux-2.6.28/ChangeLog 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/ChangeLog 2009-04-30 10:05:47.000000000 +0200 +@@ -0,0 +1,2178 @@ ++previous samsung-ap-2.6 repository ChangeLog_s3c64xx for s3c64xx branch ++----------------------------------------------------------------------- ++rel-0-0-0 : Kwanghyun La (Nov.10.2008) ++ It's not fixed version , just only initial copy version for ++ estimation. ++ ++dev-0-0-1 : Ilho Lee ++dev-0-0-2 : Ilho Lee ++ Touchscreen D/D added, but Ethernet D/D is being adding. ++ ++dev-0-0-3 : Jongpill Lee ++ Support ADC driver and merge adc-s3c64xx.c and adc-s3c24xx.c file ++ ++ Removed Files: ++ R A arch/arm/plat-s3c64xx/adc-s3c64xx.c ++ ++ Added Files: ++ A arch/arm/plat-s3c/adc.c ++ ++ Modified Files: ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/Kconfig ++ M arch/arm/plat-s3c/Makefile ++ M arch/arm/plat-s3c/include/plat/adc.h ++ M drivers/char/Kconfig ++ ++dev-0-0-4 : Jongpill Lee ++ Bug fixed on ADC driver ++ ++ Modified Files: ++ M arch/arm/plat-s3c/adc.c ++ ++dev-0-0-5 : Ilho Lee ++ SMC9115 ethernet D/D is working(small_root only) ++ ++dev-0-0-6: Jinsung Yang ++ - NAND driver support ++ ++ Added files: ++ A arch/arm/configs/smdk6410mtd_defconfig ++ A arch/arm/plat-s3c/include/plat/partition.h ++ A drivers/mtd/nand/s3c_nand.c ++ ++ Modified files: ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/Kconfig ++ M arch/arm/plat-s3c/include/plat/nand.h ++ M arch/arm/plat-s3c/include/plat/regs-nand.h ++ M arch/arm/plat-s3c64xx/devs.c ++ M drivers/mtd/nand/Kconfig ++ M drivers/mtd/nand/Makefile ++ ++dev-0-0-7: Sungjun Bae ++ - I2S WM8580, I2SWM8990 Complete. ++ ++ Modified Files: ++ M arch/arm/configs/smdk6410mtd_defconfig arch/arm/configs/smdk6410nfs_defconfig ++ M arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h ++ M arch/arm/plat-s3c64xx/include/plat/regs-clock.h include/sound/soc.h ++ M sound/soc/soc-core.c sound/soc/codecs/wm8580.c sound/soc/codecs/wm8990.c ++ ++dev-0-0-8: Sungjun Bae ++ - DMA File Structure was changed. ++ ++ Modified Files: ++ M arch/arm/plat-s3c/Makefile ++ M arch/arm/plat-s3c/include/mach/s3c-dma.h ++ M arch/arm/plat-s3c64xx/Makefile ++ Added Files: ++ A arch/arm/plat-s3c/dma-pl080.c ++ Removed Files: ++ R arch/arm/plat-s3c64xx/dma-pl080.c ++ ++dev-0-0-9: Ilho Lee ++ - PL330 DMA D/D file added ++ ++ Modified Files: ++ M arch/arm/plat-s3c/Makefile ++ M arch/arm/plat-s3c/Kconfig ++ ++ Added Files: ++ A arch/arm/plat-s3c/dma-pl330.c ++ A arch/arm/plat-s3c/dma-pl330-microcode.c ++ ++ ++dev-0-0-10: eyryu ++ - Add SMDKC100 initial. ++ ++dev-0-0-11: Ilho Lee ++ - DMA definition files changed ++ ++ Modified Files: ++ M arch/arm/mach-s3c6410/dma.c ++ M arch/arm/mach-s5pc100/dma.c ++ ++dev-0-0-12: Jinsung Yang ++ - gpiolib support for s5pc1xx architecture ++ ++ Modified files: ++ M arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h ++ M arch/arm/mach-s5pc100/include/mach/gpio.h ++ M arch/arm/plat-s3c/gpio-config.c ++ M arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h ++ ++ Added files: ++ A arch/arm/plat-s5pc1xx/gpiolib.c ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-a0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-a1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-b.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-c.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-d.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-e0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-e1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f2.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f3.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g2.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g3.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h2.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h3.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-i.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j2.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j3.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j4.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k2.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k3.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp00.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp01.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp02.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp03.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp04.h ++ ++dev-0-0-13: eyryu ++ - Add SMDKC100 clock & serial ++ ++dev-0-0-14: Ilho Lee ++ - ADC D/D added ++ ++ Added Files: ++ A arch/arm/plat-s3c24xx/adc.c ++ A arch/arm/plat-s3c64xx/adc.c ++ ++dev-0-0-15: eyryu ++ - Support SMDKC100 UART driver ++ - Add SMDKC100 clock & serial ++ ++rel-1-0-0: Kyoungil Kim ++ - Official Release (08.11.27) ++ ++dev-1-0-0: Kyoungil Kim ++ ++dev-1-0-1: Ilho Lee ++ - CPU idle added ++ ++ Added Files: ++ A arch/arm/mach-s3c6400/idle.h ++ A arch/arm/mach-s5pc100/idle.h ++ ++ Modified Files: ++ M arch/arm/mach-s3c6410/cpu.c ++ M arch/arm/mach-s5pc100/cpu.c ++ ++dev-1-0-2: Ilho Lee ++ - S3C24XX -> S3C changed in the S3C DMA D/D. ++ ++ Modified Files: ++ M arch/arm/mach-s3c6410/dma.c ++ M arch/arm/mach-s5pc100/dma.c ++ M arch/arm/plat-s3c/dma-pl080.c ++ M arch/arm/plat-s3c/dma-pl330.c ++ M arch/arm/plat-s3c/include/plat/s3c-dma.h ++ ++dev-1-0-3: Ilho Lee ++ - PL330 DMA D/D is adding.. ++ ++ Modified Files: ++ M arch/arm/plat-s3c/dma-pl330.c ++ M arch/arm/plat-s3c/dma-pl330-mcode.h ++ M arch/arm/plat-s3c/include/mach/s3c-dma.h ++ ++dev-1-0-4: Byungjae Lee ++ - Support File Storage Gadget for SMDK6410 HS USB OTG ++ ++ Modified Files: ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/cpu.c ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c64xx/devs.c ++ M arch/arm/plat-s3c64xx/include/plat/regs-clock.h ++ M drivers/usb/gadget/Kconfig ++ M drivers/usb/gadget/Makefile ++ M drivers/usb/gadget/epautoconf.c ++ M drivers/usb/gadget/gadget_chips.h ++ ++ Added Files: ++ A arch/arm/plat-s3c/include/plat/regs-otg.h ++ A drivers/usb/gadget/s3c_udc.h ++ A drivers/usb/gadget/s3c_udc_otg.c ++ ++dev-1-0-5: Ilho Lee ++ - S3C touchscreen D/D changed. ++ ++ Modified Files: ++ M drivers/input/touchscreen/s3c-ts.c ++ ++dev-1-0-6: Jinsung Yang ++ - Clock system support for S5PC100 ++ ++ Modified files: ++ M arch/arm/plat-s3c/clock.c ++ M arch/arm/plat-s3c/include/plat/clock.h ++ M arch/arm/plat-s5pc1xx/clock.c ++ M arch/arm/plat-s5pc1xx/s5pc100-clock.c ++ M arch/arm/plat-s5pc1xx/include/plat/pll.h ++ M arch/arm/plat-s5pc1xx/include/plat/regs-clock.h ++ ++dev-1-0-7: Jinsung Yang ++ - LCD (LTE480WV) support for SMDKC100 ++ ++ Modified files: ++ drivers/video/samsung/s5pfb_fimd5x.c ++ ++dev-1-0-8: Byungjae Lee ++ - Masked HCLK for USB OTG at register clocks ++ ++ Modified files: ++ M arch/arm/plat-s3c64xx/clock.c ++ M drivers/usb/gadget/s3c_udc_otg.c ++ ++dev-1-0-9: Ilho Lee ++ - Ext-interrupts handlers added. ++ ++ Added Files: ++ A arch/arm/plat-s5pc1xx/irq-eint.c ++ ++dev-1-0-10: Ilho Lee ++ - SMC9115 ethernet(100Mbps) D/D ported. ++ ++ Added Files: ++ A arch/arm/plat-s5pc1xx/irq-eint.c ++ ++dev-1-0-11: Ilho Lee ++ - dev-adc.c deleted. ++ ++ Deleted Files: ++ D arch/arm/plat-s3c/dev-adc.c ++ ++rel-1-0-1: Kyoungil Kim ++ - Git Release (08.12.09) ++ ++v2.6.28-rc7-s3c64xx-r0d0: Kyoungil Kim ++ - s3c64xx rc7 initial git tag ++ ++v2.6.28-rc8-s3c64xx: Kyoungil Kim ++ - s3c64xx rc8 patch ++ ++v2.6.28-rc8-s3c64xx-r0d0: Kyoungil Kim ++ ++v2.6.28-rc8-s3c64xx-r0d1: Jinsung Yang ++ - Fix for wrong comments ++ ++v2.6.28-rc8-s3c64xx-r0d2: Jongpill Lee ++ ++ - bug fixed about OS Timer ++ ++ Modified Files: ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/include/plat/cpu.h ++ M arch/arm/plat-s3c/include/plat/regs-timer.h ++ M arch/arm/plat-s3c/time.c ++ M arch/arm/plat-s3c24xx/include/plat/cpu.h ++ ++v2.6.28-rc8-s3c64xx-r0d3: Jongpill Lee ++ - Remove adc driver on s3c24xx ++ Modified Files: ++ M arch/arm/plat-s3c24xx/Kconfig ++ M arch/arm/plat-s3c24xx/Makefile ++ Deleted Files: ++ D arch/arm/plat-s3c24xx/adc.c ++ ++v2.6.28-rc8-s3c64xx-r0d4: Jinsung Yang ++ - 24 bit logo display support ++ - s3c framebuffer driver naming rule changes ++ ++ Modified files: ++ M drivers/video/cfbimgblt.c ++ M drivers/video/samsung/s3cfb.c ++ M drivers/video/samsung/s3cfb.h ++ M drivers/video/samsung/s3cfb_fimd4x.c ++ M drivers/video/samsung/s3cfb_fimd5x.c ++ M drivers/video/samsung/s3cfb_lte480wv.c ++ M drivers/video/samsung/s3cfb_lts222qv.c ++ M drivers/video/samsung/s3cfb_ltv350qv.c ++ M drivers/video/samsung/s3cfb_spi.c ++ ++v2.6.28-rc8-s3c64xx-r0d5: Jongpill Lee ++ -Support cpu freq on smdk6410 ++ ++ Added Files: ++ A arch/arm/plat-s3c64xx/s3c64xx-cpufreq.carch/arm/plat-s3c64xx/s3c64xx-cpufreq.c ++ Modified Files: ++ M arch/arm/Kconfig ++ M arch/arm/plat-s3c/clock.c ++ M arch/arm/plat-s3c64xx/Makefile ++ ++v2.6.28-rc8-s3c64xx-r0d6: Kyoungil Kim ++ - split plat-s5p64xx, mach-s5p6440 ++ - Support for s5p6440 serial ++ ++ Added Files ++ A arch/arm/configs/smdk6440ramdisk_defconfig ++ A arch/arm/mach-s5p6440/Kconfig ++ A arch/arm/mach-s5p6440/Makefile.boot ++ A arch/arm/mach-s5p6440/cpu.c ++ A arch/arm/mach-s5p6440/dma.c ++ A arch/arm/mach-s5p6440/include/mach/debug-macro.S ++ A arch/arm/mach-s5p6440/include/mach/dma.h ++ A arch/arm/mach-s5p6440/include/mach/entry-macro.S ++ A arch/arm/mach-s5p6440/include/mach/gpio-core.h ++ A arch/arm/mach-s5p6440/include/mach/gpio.h ++ A arch/arm/mach-s5p6440/include/mach/hardware.h ++ A arch/arm/mach-s5p6440/include/mach/idle.h ++ A arch/arm/mach-s5p6440/include/mach/irqs.h ++ A arch/arm/mach-s5p6440/include/mach/map.h ++ A arch/arm/mach-s5p6440/include/mach/memory.h ++ A arch/arm/mach-s5p6440/include/mach/regs-irq.h ++ A arch/arm/mach-s5p6440/include/mach/regs-mem.h ++ A arch/arm/mach-s5p6440/include/mach/system.h ++ A arch/arm/mach-s5p6440/include/mach/tick.h ++ A arch/arm/mach-s5p6440/include/mach/uncompress.h ++ A arch/arm/mach-s5p6440/mach-smdk6440.c ++ A arch/arm/mach-s5p6440/setup-sdhci.c ++ A arch/arm/plat-s5p64xx/Kconfig ++ A arch/arm/plat-s5p64xx/Makefile ++ A arch/arm/plat-s5p64xx/adc.c ++ A arch/arm/plat-s5p64xx/clock.c ++ A arch/arm/plat-s5p64xx/cpu.c ++ A arch/arm/plat-s5p64xx/dev-uart.c ++ A arch/arm/plat-s5p64xx/devs.c ++ A arch/arm/plat-s5p64xx/gpiolib.c ++ A arch/arm/plat-s5p64xx/include/plat/dma.h ++ A arch/arm/plat-s5p64xx/include/plat/gpio-bank-a.h ++ A arch/arm/plat-s5p64xx/include/plat/gpio-bank-b.h ++ A arch/arm/plat-s5p64xx/include/plat/gpio-bank-c.h ++ A arch/arm/plat-s5p64xx/include/plat/gpio-bank-f.h ++ A arch/arm/plat-s5p64xx/include/plat/gpio-bank-g.h ++ A arch/arm/plat-s5p64xx/include/plat/gpio-bank-h.h ++ A arch/arm/plat-s5p64xx/include/plat/gpio-bank-i.h ++ A arch/arm/plat-s5p64xx/include/plat/gpio-bank-j.h ++ A arch/arm/plat-s5p64xx/include/plat/gpio-bank-n.h ++ A arch/arm/plat-s5p64xx/include/plat/gpio-bank-p.h ++ A arch/arm/plat-s5p64xx/include/plat/gpio-bank-r.h ++ A arch/arm/plat-s5p64xx/include/plat/irqs.h ++ A arch/arm/plat-s5p64xx/include/plat/pll.h ++ A arch/arm/plat-s5p64xx/include/plat/regs-clock.h ++ A arch/arm/plat-s5p64xx/include/plat/regs-gpio.h ++ A arch/arm/plat-s5p64xx/include/plat/regs-sys.h ++ A arch/arm/plat-s5p64xx/include/plat/s5p6440.h ++ A arch/arm/plat-s5p64xx/irq-eint.c ++ A arch/arm/plat-s5p64xx/irq.c ++ A arch/arm/plat-s5p64xx/s5p6440-clock.c ++ A arch/arm/plat-s5p64xx/s5p6440-init.c ++ A arch/arm/plat-s5p64xx/setup-i2c0.c ++ A arch/arm/plat-s5p64xx/setup-i2c1.c ++ Modified Files ++ M arch/arm/Kconfig ++ M arch/arm/Makefile ++ M arch/arm/mach-s5p6440/Makefile ++ M arch/arm/mm/Kconfig ++ M arch/arm/plat-s3c/Kconfig ++ M arch/arm/plat-s3c/include/plat/clock.h ++ M arch/arm/plat-s3c/include/plat/cpu.h ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s3c/include/plat/regs-lcd.h ++ M arch/arm/tools/mach-types ++ M drivers/i2c/busses/Kconfig ++ M drivers/input/touchscreen/Kconfig ++ M drivers/mtd/nand/Kconfig ++ M drivers/serial/Kconfig ++ M drivers/video/Kconfig ++ M drivers/video/samsung/Makefile ++ M drivers/video/samsung/s3cfb.h ++ M drivers/video/samsung/s3cfb_spi.c ++ ++v2.6.28-rc8-s3c64xx-r0d7: Ilho Lee ++ - ASYN/SYN mode select added. ++ ++ Modified Files: ++ M arch/arm/plat-s3c64xx/include/plat/regs-clock.h ++ M arch/arm/plat-s3c64xx/s3c6400-clock.c ++ ++v2.6.28-rc8-s3c64xx-r0d8: Kyoungil Kim ++ - Support for FPGA6440 lcd ++ ++ Modified Files: ++ M arch/arm/mach-s5p6440/include/mach/gpio.h ++ M drivers/video/samsung/s3cfb_fimd5x.c ++ M drivers/video/samsung/s3cfb_lts222qv.c ++ M drivers/video/samsung/s3cfb_spi.c ++ ++v2.6.28-rc8-s3c64xx-r0d9: Jongpill Lee ++ - Support APM on SMDK6410 ++ ++ Modified Files: ++ M arch/arm/configs/smdk6410mtd_defconfig ++ M arch/arm/mach-s3c6400/include/mach/regs-irq.h ++ M arch/arm/mach-s3c6410/Makefile ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/Makefile ++ M arch/arm/plat-s3c/include/plat/regs-serial.h ++ M arch/arm/plat-s3c64xx/Makefile ++ M arch/arm/plat-s3c64xx/include/plat/gpio-bank-k.h ++ M arch/arm/plat-s3c64xx/include/plat/gpio-bank-l.h ++ M arch/arm/plat-s3c64xx/include/plat/regs-gpio.h ++ M arch/arm/plat-s3c64xx/irq.c ++ M drivers/video/samsung/s3cfb_fimd4x.c ++ Added Files: ++ A arch/arm/mach-s3c6410/irq.c ++ A arch/arm/mach-s3c6410/pm.c ++ A arch/arm/plat-s3c64xx/include/plat/gpio-bank-m.h ++ A arch/arm/plat-s3c64xx/include/plat/pm.h ++ A arch/arm/plat-s3c64xx/pm.c ++ A arch/arm/plat-s3c64xx/sleep.S ++ ++v2.6.28-rc8-s3c64xx-r0d10: Jongpill Lee ++ - Support RTC on SMDK6410 ++ ++ MOdified Files: ++ M arch/arm/mach-s3c2410/include/mach/map.h ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/include/plat/regs-rtc.h ++ M arch/arm/plat-s3c64xx/devs.c ++ M arch/arm/plat-s3c64xx/include/plat/pm.h ++ M drivers/rtc/Kconfig ++ M drivers/rtc/rtc-s3c.c ++ ++v2.6.28-rc8-s3c64xx-r0d11: Kyoungil Kim ++ - Keypad Driver for SMDK6410 ++ ++ Modified Files: ++ M arch/arm/configs/smdk6410mtd_defconfig ++ M arch/arm/configs/smdk6410nfs_defconfig ++ M arch/arm/configs/smdk6410ramdisk_defconfig ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/gpio-config.c ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s3c64xx/clock.c ++ M arch/arm/plat-s3c64xx/devs.c ++ M arch/arm/plat-s3c64xx/include/plat/gpio-bank-k.h ++ M arch/arm/plat-s3c64xx/include/plat/gpio-bank-l.h ++ M drivers/input/keyboard/Kconfig ++ M drivers/input/keyboard/Makefile ++ M drivers/input/touchscreen/s3c-ts.c ++ Added Files: ++ A arch/arm/plat-s3c64xx/include/plat/regs-keypad.h ++ A drivers/input/keyboard/s3c-keypad.c ++ A drivers/input/keyboard/s3c-keypad.h ++ ++v2.6.28-rc8-s3c64xx-r0d12: Jongpill Lee ++ - Support HS-SPI on SMDK6410 ++ ++ Added Files: ++ A arch/arm/plat-s3c64xx/include/plat/regs-spi.h ++ A drivers/spi/hspi-s3c64xx.c ++ A drivers/spi/hspi-s3c64xx.h ++ A drivers/spi/spi-dev.c ++ A drivers/spi/spi-dev.h ++ ++ Modified Files: ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M drivers/rtc/rtc-s3c.c ++ M drivers/spi/Kconfig ++ M drivers/spi/Makefile ++ ++v2.6.28-rc8-s3c64xx-r0d13: Ilho Lee ++ - Support HS-MMC on SMDK6410 ++ ++v2.6.28-rc8-s3c64xx-r0d14: Jongpill Lee ++ - bug fiex on PM Driver ++ ++ Modified Files: ++ M arch/arm/configs/smdk6410mtd_defconfig ++ M arch/arm/plat-s3c64xx/sleep.S ++ ++v2.6.28-rc8-s3c64xx-r0d15: Kyoungil Kim ++ - Support USB host on SMDK6410 ++ ++ Modifiled Files: ++ M arch/arm/configs/smdk6410mtd_defconfig ++ M arch/arm/configs/smdk6410nfs_defconfig ++ M arch/arm/configs/smdk6410onenand_defconfig ++ M arch/arm/configs/smdk6410ramdisk_defconfig ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/mach-s5p6440/mach-smdk6440.c ++ M arch/arm/plat-s3c/include/plat/partition.h ++ M arch/arm/plat-s3c64xx/devs.c ++ M drivers/usb/Kconfig ++ M drivers/usb/gadget/s3c_udc_otg.c ++ M drivers/usb/host/ohci-hcd.c ++ M drivers/usb/host/ohci-s3c2410.c ++ Added Files: ++ A arch/arm/mach-s3c6400/include/mach/usb-control.h ++ ++v2.6.28-rc8-s3c64xx-r0d16: Jongpill Lee ++ - Support DVS on CPUFREQ Driver ++ ++ Added Files: ++ A arch/arm/plat-s3c64xx/ltc3714.c ++ Modified Files: ++ M arch/arm/plat-s3c/clock.c ++ M arch/arm/plat-s3c64xx/Makefile ++ M arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c ++ ++v2.6.28-rc8-s3c64xx-r0d17: Byungjae Lee ++ - Support Ethernet gadget and RNDIS for SMDK6410 ++ ++ Modifiled Files: ++ M arch/arm/configs/smdk6410mtd_defconfig ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M drivers/usb/gadget/Kconfig ++ M drivers/usb/gadget/epautoconf.c ++ M drivers/usb/gadget/f_rndis.c ++ M drivers/usb/gadget/s3c_udc.h ++ M drivers/usb/gadget/s3c_udc_otg.c ++ M drivers/usb/gadget/u_ether.c ++ Added Files: ++ A drivers/usb/gadget/s3c_udc_otg_xfer_dma.c ++ A drivers/usb/gadget/s3c_udc_otg_xfer_slave.c ++ ++v2.6.28-rc8-s3c64xx-r0d18: Jongpill Lee ++ - Remove warning message ++ ++ Modified Files: ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/mach-s3c6410/pm.c ++ M arch/arm/plat-s3c/clock.c ++ M arch/arm/plat-s3c64xx/clock.c ++ M arch/arm/plat-s3c64xx/include/plat/pm.h ++ M arch/arm/plat-s3c64xx/irq.c ++ M arch/arm/plat-s3c64xx/ltc3714.c ++ M arch/arm/plat-s3c64xx/pm.c ++ M arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c ++ M drivers/rtc/rtc-s3c.c ++ M drivers/spi/hspi-s3c64xx.c ++ ++v2.6.28-rc8-s3c64xx-r0d19: Kyoungil Kim ++ - Support Watchdog on SMDK6410 ++ ++ Modified Files: ++ M arch/arm/configs/smdk6410mtd_defconfig ++ M arch/arm/configs/smdk6410nfs_defconfig ++ M arch/arm/configs/smdk6410onenand_defconfig ++ M arch/arm/configs/smdk6410ramdisk_defconfig ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c64xx/devs.c ++ M drivers/watchdog/Kconfig ++ ++v2.6.28-rc8-s3c64xx-r0d20: Ryu Euiyoul ++ - Support S5M8751 on SMDK6410 ++ ++ Modified Files: ++ M sound/soc/codecs/Kconfig ++ M sound/soc/codecs/Makefile ++ M sound/soc/s3c64xx/Kconfig ++ M sound/soc/s3c64xx/Makefile ++ ++ Added Files: ++ A sound/soc/codecs/s5m8751.c ++ A sound/soc/codecs/s5m8751.h ++ A sound/soc/s3c64xx/smdk6410_s5m8751.c ++ A arch/arm/configs/smdk6410rf_defconfig ++ ++v2.6.28-rc8-s3c64xx-r0d21: SungJun Bae ++ - Support wm8580 on VEGA-L FPGA (Draft) ++ ++ Modified Files: ++ M arch/arm/configs/smdk6440ramdisk_defconfig ++ M arch/arm/mach-s5p6440/dma.c ++ M arch/arm/mach-s5p6440/mach-smdk6440.c ++ M arch/arm/plat-s3c/dma-pl080.c ++ M sound/soc/s3c64xx/Kconfig ++ M sound/soc/s3c64xx/Makefile ++ M sound/soc/s3c64xx/s3c-i2s.h ++ M sound/soc/s3c64xx/s3c-pcm.c ++ M sound/soc/s3c64xx/s3c6410-i2s-v40.c ++ ++ Added Files: ++ A sound/soc/s3c64xx/s5p6440-i2s-v40.c ++ A sound/soc/s3c64xx/smdk6440_wm8580.c ++ ++v2.6.28.6-s3c64xx: Kyoungil Kim ++ ++v2.6.28.6-s3c64xx-r0d0: Kyoungil Kim ++ ++v2.6.28.6-s3c64xx-r0d1: SungJun Bae ++ - Support Post Processor on SMDK6410 ++ ++ Modified Files: ++ M ChangeLog_s3c64xx ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s3c/include/plat/regs-lcd.h ++ M arch/arm/plat-s3c64xx/devs.c ++ M drivers/media/video/Kconfig ++ M drivers/media/video/Makefile ++ ++ Added Files: ++ A arch/arm/plat-s3c/include/plat/regs-pp.h ++ A arch/arm/plat-s3c/include/plat/reserved_mem.h ++ A drivers/media/video/samsung/post/Kconfig ++ A drivers/media/video/samsung/post/Makefile ++ A drivers/media/video/samsung/post/s3c_pp.h ++ A drivers/media/video/samsung/post/s3c_pp_6400.c ++ A drivers/media/video/samsung/post/s3c_pp_common.c ++ A drivers/media/video/samsung/post/s3c_pp_common.h ++ ++v2.6.28.6-s3c64xx-r0d2: SungJun Bae ++ - Support TV encoder,scaler on SMDK6410 ++ ++ Modified Files: ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s3c64xx/devs.c ++ M drivers/media/video/Kconfig ++ M drivers/media/video/Makefile ++ M drivers/media/video/samsung/Kconfig ++ M drivers/media/video/samsung/post/s3c_pp_6400.c ++ M drivers/media/video/v4l2-dev.c ++ M include/media/v4l2-dev.h ++ ++ Added Files: ++ A arch/arm/plat-s3c/include/plat/regs-tvenc.h ++ A arch/arm/plat-s3c/include/plat/regs-tvscaler.h ++ A drivers/media/video/samsung/tv/Kconfig ++ A drivers/media/video/samsung/tv/Makefile ++ A drivers/media/video/samsung/tv/s3c-tvenc.c ++ A drivers/media/video/samsung/tv/s3c-tvenc.h ++ A drivers/media/video/samsung/tv/s3c-tvscaler.c ++ A drivers/media/video/samsung/tv/s3c-tvscaler.h ++v2.6.28.6-s3c64xx-r0d3: Jaeryul Oh ++ - Support JPEG, roator on SMDK6410 ++ ++ Modified Files : ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s3c64xx/devs.c ++ M drivers/media/video/samsung/Kconfig ++ M drivers/media/video/samsung/Makefile ++ ++ Added Files: ++ A drivers/media/video/samsung/jpeg/Kconfig ++ A drivers/media/video/samsung/jpeg/Makefile ++ A drivers/media/video/samsung/jpeg/jpg_conf.h ++ A drivers/media/video/samsung/jpeg/jpg_mem.c ++ A drivers/media/video/samsung/jpeg/jpg_mem.h ++ A drivers/media/video/samsung/jpeg/jpg_misc.c ++ A drivers/media/video/samsung/jpeg/jpg_misc.h ++ A drivers/media/video/samsung/jpeg/jpg_opr.c ++ A drivers/media/video/samsung/jpeg/jpg_opr.h ++ A drivers/media/video/samsung/jpeg/log_msg.c ++ A drivers/media/video/samsung/jpeg/log_msg.h ++ A drivers/media/video/samsung/jpeg/s3c-jpeg.c ++ A drivers/media/video/samsung/jpeg/s3c-jpeg.h ++ A drivers/media/video/samsung/rotator/Kconfig ++ A drivers/media/video/samsung/rotator/Makefile ++ A drivers/media/video/samsung/rotator/regs-rotator.h ++ A drivers/media/video/samsung/rotator/s3c_rotator.c ++ A drivers/media/video/samsung/rotator/s3c_rotator_common.h ++ ++v2.6.28.6-s3c64xx-r0d4: Jinsung Yang ++ - FIMC support for SMDK6410 ++ - Including reserved memory feature with bootmem ++ - All functions have been finished on the planning ++ ++v2.6.28.6-s3c64xx-r0d5: SungJun Bae ++ - bootmem applied to post and tv. ++ M drivers/media/video/samsung/post/s3c_pp_6400.c ++ M drivers/media/video/samsung/tv/s3c-tvscaler.h ++ ++v2.6.28.6-s3c64xx-r0d6: PyoungJae Jung, Jiun Yu ++ - MFC support for SMDK6410 ++ - It support bootmem for large buffer memory ++ - Changed coding style to linux kernel coding style ++ - Bug fixed in Hybrid DiVX encoding problem ++ ++ Modified Files: ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s3c64xx/devs.c ++ M arch/arm/plat-s3c64xx/include/plat/media.h ++ M drivers/media/video/samsung/Kconfig ++ M drivers/media/video/samsung/Makefile ++ ++ Added Files: ++ A arch/arm/plat-s3c64xx/include/plat/regs-mfc.h ++ A drivers/media/video/samsung/mfc/Kconfig ++ A drivers/media/video/samsung/mfc/Makefile ++ A drivers/media/video/samsung/mfc/prism_s.h ++ A drivers/media/video/samsung/mfc/prism_s_v137.c ++ A drivers/media/video/samsung/mfc/s3c_mfc.c ++ A drivers/media/video/samsung/mfc/s3c_mfc.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_base.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_bitproc_buf.c ++ A drivers/media/video/samsung/mfc/s3c_mfc_bitproc_buf.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_config.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_databuf.c ++ A drivers/media/video/samsung/mfc/s3c_mfc_databuf.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_hw_init.c ++ A drivers/media/video/samsung/mfc/s3c_mfc_hw_init.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_inst_pool.c ++ A drivers/media/video/samsung/mfc/s3c_mfc_inst_pool.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_instance.c ++ A drivers/media/video/samsung/mfc/s3c_mfc_instance.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_intr_noti.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_params.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_set_config.c ++ A drivers/media/video/samsung/mfc/s3c_mfc_sfr.c ++ A drivers/media/video/samsung/mfc/s3c_mfc_sfr.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_types.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_yuv_buf_manager.c ++ A drivers/media/video/samsung/mfc/s3c_mfc_yuv_buf_manager.h ++ ++v2.6.28.6-s3c64xx-r0d7: Kyoungil Kim ++ - Just Prevent tag for SMDK6410 ++ ++v2.6.28.6-s3c64xx-r0d8: Jaeryul Oh ++ - Fixed Bug in case of dynamic fps change of MPEG4 encoding ++ ++ Modified Files: ++ M drivers/media/video/samsung/mfc/s3c_mfc_instance.h ++ M drivers/media/video/samsung/mfc/s3c_mfc_instance.c ++ ++v2.6.28.6-s3c64xx-r0d9: Jonghun Han ++ - S3C6410 FIMG-2D driver support ++ ++ Added Files: ++ drivers/media/video/samsung/g2d/Kconfig ++ drivers/media/video/samsung/g2d/Makefile ++ drivers/media/video/samsung/g2d/s3c_fimg2d2x.c ++ drivers/media/video/samsung/g2d/s3c_fimg2d2x.h ++ arch/arm/plat-s3c/include/plat/regs-g2d.h ++ ++ Modified Files: ++ arch/arm/configs/smdk6410mtd_defconfig ++ arch/arm/configs/smdk6410nfs_defconfig ++ arch/arm/configs/smdk6410onenand_defconfig ++ arch/arm/configs/smdk6410ramdisk_defconfig ++ arch/arm/mach-s3c6400/include/mach/map.h ++ arch/arm/mach-s3c6410/mach-smdk6410.c ++ arch/arm/plat-s3c/include/plat/devs.h ++ arch/arm/plat-s3c64xx/devs.c ++ drivers/media/video/samsung/Kconfig ++ drivers/media/video/samsung/Makefile ++ drivers/video/samsung/s3cfb.c ++ drivers/video/samsung/s3cfb_fimd4x.c ++ ++v2.6.28.6-s3c64xx-r1: Jonghun Han ++ - Official Release (09.03.06) ++ ++v2.6.28.6-s3c64xx-r1d0: Kyoungil Kim ++ ++v2.6.28.6-s3c64xx-r1d1 : Byungjae Lee ++ - implemented s3c6410 OTG host role for Mass storage only ++ ++ Modified Files: ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s3c64xx/devs.c ++ M drivers/usb/Makefile ++ M drivers/usb/host/Kconfig ++ M drivers/usb/host/Makefile ++ ++ Added Files: ++ A drivers/usb/host/s3c-otg/* ++ ++v2.6.28.6-s3c64xx-r1d2 : Byungjae Lee ++ - implemented s3c6410 OTG host role for HID(Keyboard, Mouse) ++ and Card Reader ++ ++ Modified Files: ++ M drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.c ++ M drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.c ++ M drivers/usb/host/s3c-otg/s3c-otg-hcdi-kal.h ++ M drivers/usb/host/s3c-otg/s3c-otg-scheduler-ischeduler.c ++ M drivers/usb/host/s3c-otg/s3c-otg-scheduler-scheduler.h ++ M drivers/usb/host/s3c-otg/s3c-otg-transfer-common.c ++ M drivers/usb/host/s3c-otg/s3c-otg-transferchecker-common.c ++ ++v2.6.28.6-s3c64xx-r1d3 : Jongpill Lee ++ - defect is fixed on cpufreq driver ++ ++ Modified Files: ++ M arch/arm/plat-s3c64xx/clock.c ++ ++v2.6.28.6-s3c64xx-r1d4 : Jongpill Lee ++ - defect is fixed on pm ++ ++ MOdified Fils: ++ M arch/arm/plat-s3c64xx/pm.c ++ ++v2.6.28.6-s3c64xx-r1d5: Kyoungil Kim ++ - Just Second Prevent tag for SMDK6410 ++ ++v2.6.28.6-s3c64xx-r1d6 : Jonghun Han ++ - update S3C6410 FIMG-2D driver ++ ++ Modified Fils: ++ M arch/arm/plat-s3c/include/plat/regs-g2d.h ++ M drivers/media/video/samsung/g2d/s3c_fimg2d2x.c ++ ++v2.6.28.6-s3c64xx-r2: Kyoungil Kim ++ - Official Release (09.03.09) ++ ++v2.6.28.6-s3c64xx-r2d0: Kyoungil Kim ++ ++v2.6.28.6-s3c64xx-r2d1: Jaeryul Oh ++ - Fixed Bug in case of rotator function of MFC ++ ++ Modified Files: ++ M drivers/media/video/samsung/mfc/s3c_mfc_instance.c ++ ++v2.6.28.6-s3c64xx-r2d2: Jonghun Han ++ - S3C6410 FIMG-3D driver support ++ ++ Modified Files: ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s3c64xx/devs.c ++ M drivers/char/s3c_mem.c ++ M drivers/media/video/samsung/Kconfig ++ M drivers/media/video/samsung/Makefile ++ M drivers/media/video/samsung/g2d/s3c_fimg2d2x.c ++ ++ Added Files: ++ A drivers/media/video/samsung/g3d/Kconfig ++ A drivers/media/video/samsung/g3d/Makefile ++ A drivers/media/video/samsung/g3d/s3c_fimg3d.c ++ A drivers/media/video/samsung/g3d/s3c_fimg3d.h ++ ++v2.6.28.6-s3c64xx-r2d3: Jonghun Han ++ - S5PC100 FIMG-2D driver support ++ ++ Modified Files: ++ M drivers/media/video/samsung/g2d/Kconfig ++ M drivers/media/video/samsung/g2d/s3c_fimg2d2x.c ++ ++v2.6.28.6-s3c64xx-r3: Kyoungil Kim ++ - Official Release (09.03.13) ++ ++v2.6.28.6-s3c64xx-r3d0: Kyoungil Kim ++ ++v2.6.28.6-s3c64xx-r3d1: Byungae Lee ++ - Support SMDK6410 USB Serial Gadget (with CDC ACM) ++ ++ Modified Files: ++ M arch/arm/plat-s3c/include/plat/regs-otg.h ++ M drivers/usb/gadget/s3c_udc_otg.c ++ M drivers/usb/gadget/s3c_udc_otg_xfer_dma.c ++ M drivers/usb/gadget/s3c_udc_otg_xfer_slave.c ++ ++v2.6.28.6-s3c64xx-r3d2: Byungae Lee ++ - Removed warning on the debug message for the USB Gadget ++ ++ Modified Files: ++ M drivers/usb/gadget/s3c_udc_otg.c ++ M drivers/usb/gadget/s3c_udc_otg_xfer_dma.c ++ ++v2.6.28.6-s3c64xx-r3d3: SungJun Bae ++ - Support CMM driver. ++ ++ Added Files: ++ A drivers/media/video/samsung/cmm/CMMMisc.c ++ A drivers/media/video/samsung/cmm/CMMMisc.h ++ A drivers/media/video/samsung/cmm/Kconfig ++ A drivers/media/video/samsung/cmm/LogMsg.c ++ A drivers/media/video/samsung/cmm/LogMsg.h ++ A drivers/media/video/samsung/cmm/Makefile ++ A drivers/media/video/samsung/cmm/s3c-cmm.c ++ A drivers/media/video/samsung/cmm/s3c-cmm.h ++ ++ Modified Files: ++ M drivers/media/video/samsung/Kconfig ++ M drivers/media/video/samsung/Makefile ++ ++ ++v2.6.28.6-s3c64xx-r4: Jonghun Han ++ - Official Release (09.03.24) ++ ++v2.6.28.6-s3c64xx-r4d0: Jonghun Han ++ ++v2.6.28.6-s3c64xx-r4d1: Kyoungil Kim ++ - The last tag for s3c64xx branch(09.03.24) ++ ++rel-0-0-0 : Kwanghyun La (Nov.10.2008) ++ It's not fixed version , just only initial copy version for ++ estimation. ++ ++previous samsung-ap-2.6 repository ChangeLog_s5pc1xx for s5pc1xx branch ++----------------------------------------------------------------------- ++dev-0-0-1 : Ilho Lee ++dev-0-0-2 : Ilho Lee ++ Touchscreen D/D added, but Ethernet D/D is being adding. ++ ++dev-0-0-3 : Jongpill Lee ++ Support ADC driver and merge adc-s3c64xx.c and adc-s3c24xx.c file ++ ++ Removed Files: ++ R A arch/arm/plat-s3c64xx/adc-s3c64xx.c ++ ++ Added Files: ++ A arch/arm/plat-s3c/adc.c ++ ++ Modified Files: ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/Kconfig ++ M arch/arm/plat-s3c/Makefile ++ M arch/arm/plat-s3c/include/plat/adc.h ++ M drivers/char/Kconfig ++ ++dev-0-0-4 : Jongpill Lee ++ Bug fixed on ADC driver ++ ++ Modified Files: ++ M arch/arm/plat-s3c/adc.c ++ ++dev-0-0-5 : Ilho Lee ++ SMC9115 ethernet D/D is working(small_root only) ++ ++dev-0-0-6: Jinsung Yang ++ - NAND driver support ++ ++ Added files: ++ A arch/arm/configs/smdk6410mtd_defconfig ++ A arch/arm/plat-s3c/include/plat/partition.h ++ A drivers/mtd/nand/s3c_nand.c ++ ++ Modified files: ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/Kconfig ++ M arch/arm/plat-s3c/include/plat/nand.h ++ M arch/arm/plat-s3c/include/plat/regs-nand.h ++ M arch/arm/plat-s3c64xx/devs.c ++ M drivers/mtd/nand/Kconfig ++ M drivers/mtd/nand/Makefile ++ ++dev-0-0-7: Sungjun Bae ++ - I2S WM8580, I2SWM8990 Complete. ++ ++ Modified Files: ++ M arch/arm/configs/smdk6410mtd_defconfig arch/arm/configs/smdk6410nfs_defconfig ++ M arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h ++ M arch/arm/plat-s3c64xx/include/plat/regs-clock.h include/sound/soc.h ++ M sound/soc/soc-core.c sound/soc/codecs/wm8580.c sound/soc/codecs/wm8990.c ++ ++dev-0-0-8: Sungjun Bae ++ - DMA File Structure was changed. ++ ++ Modified Files: ++ M arch/arm/plat-s3c/Makefile ++ M arch/arm/plat-s3c/include/mach/s3c-dma.h ++ M arch/arm/plat-s3c64xx/Makefile ++ Added Files: ++ A arch/arm/plat-s3c/dma-pl080.c ++ Removed Files: ++ R arch/arm/plat-s3c64xx/dma-pl080.c ++ ++dev-0-0-9: Ilho Lee ++ - PL330 DMA D/D file added ++ ++ Modified Files: ++ M arch/arm/plat-s3c/Makefile ++ M arch/arm/plat-s3c/Kconfig ++ ++ Added Files: ++ A arch/arm/plat-s3c/dma-pl330.c ++ A arch/arm/plat-s3c/dma-pl330-microcode.c ++ ++ ++dev-0-0-10: eyryu ++ - Add SMDKC100 initial. ++ ++dev-0-0-11: Ilho Lee ++ - DMA definition files changed ++ ++ Modified Files: ++ M arch/arm/mach-s3c6410/dma.c ++ M arch/arm/mach-s5pc100/dma.c ++ ++dev-0-0-12: Jinsung Yang ++ - gpiolib support for s5pc1xx architecture ++ ++ Modified files: ++ M arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h ++ M arch/arm/mach-s5pc100/include/mach/gpio.h ++ M arch/arm/plat-s3c/gpio-config.c ++ M arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h ++ ++ Added files: ++ A arch/arm/plat-s5pc1xx/gpiolib.c ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-a0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-a1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-b.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-c.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-d.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-e0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-e1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f2.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f3.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g2.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g3.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h2.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h3.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-i.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j2.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j3.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j4.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k2.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k3.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp00.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp01.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp02.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp03.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp04.h ++ ++dev-0-0-13: eyryu ++ - Add SMDKC100 clock & serial ++ ++dev-0-0-14: Ilho Lee ++ - ADC D/D added ++ ++ Added Files: ++ A arch/arm/plat-s3c24xx/adc.c ++ A arch/arm/plat-s3c64xx/adc.c ++ ++dev-0-0-15: eyryu ++ - Support SMDKC100 UART driver ++ - Add SMDKC100 clock & serial ++ ++rel-1-0-0: Kyoungil Kim ++ - Official Release (08.11.27) ++ ++dev-1-0-0: Kyoungil Kim ++ ++dev-1-0-1: Ilho Lee ++ - CPU idle added ++ ++ Added Files: ++ A arch/arm/mach-s3c6400/idle.h ++ A arch/arm/mach-s5pc100/idle.h ++ ++ Modified Files: ++ M arch/arm/mach-s3c6410/cpu.c ++ M arch/arm/mach-s5pc100/cpu.c ++ ++dev-1-0-2: Ilho Lee ++ - S3C24XX -> S3C changed in the S3C DMA D/D. ++ ++ Modified Files: ++ M arch/arm/mach-s3c6410/dma.c ++ M arch/arm/mach-s5pc100/dma.c ++ M arch/arm/plat-s3c/dma-pl080.c ++ M arch/arm/plat-s3c/dma-pl330.c ++ M arch/arm/plat-s3c/include/plat/s3c-dma.h ++ ++dev-1-0-3: Ilho Lee ++ - PL330 DMA D/D is adding.. ++ ++ Modified Files: ++ M arch/arm/plat-s3c/dma-pl330.c ++ M arch/arm/plat-s3c/dma-pl330-mcode.h ++ M arch/arm/plat-s3c/include/mach/s3c-dma.h ++ ++dev-1-0-4: Byungjae Lee ++ - Support File Storage Gadget for SMDK6410 HS USB OTG ++ ++ Modified Files: ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/cpu.c ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c64xx/devs.c ++ M arch/arm/plat-s3c64xx/include/plat/regs-clock.h ++ M drivers/usb/gadget/Kconfig ++ M drivers/usb/gadget/Makefile ++ M drivers/usb/gadget/epautoconf.c ++ M drivers/usb/gadget/gadget_chips.h ++ ++ Added Files: ++ A arch/arm/plat-s3c/include/plat/regs-otg.h ++ A drivers/usb/gadget/s3c_udc.h ++ A drivers/usb/gadget/s3c_udc_otg.c ++ ++dev-1-0-5: Ilho Lee ++ - S3C touchscreen D/D changed. ++ ++ Modified Files: ++ M drivers/input/touchscreen/s3c-ts.c ++ ++dev-1-0-6: Jinsung Yang ++ - Clock system support for S5PC100 ++ ++ Modified files: ++ M arch/arm/plat-s3c/clock.c ++ M arch/arm/plat-s3c/include/plat/clock.h ++ M arch/arm/plat-s5pc1xx/clock.c ++ M arch/arm/plat-s5pc1xx/s5pc100-clock.c ++ M arch/arm/plat-s5pc1xx/include/plat/pll.h ++ M arch/arm/plat-s5pc1xx/include/plat/regs-clock.h ++ ++dev-1-0-7: Jinsung Yang ++ - LCD (LTE480WV) support for SMDKC100 ++ ++ Modified files: ++ drivers/video/samsung/s5pfb_fimd5x.c ++ ++dev-1-0-8: Byungjae Lee ++ - Masked HCLK for USB OTG at register clocks ++ ++ Modified files: ++ M arch/arm/plat-s3c64xx/clock.c ++ M drivers/usb/gadget/s3c_udc_otg.c ++ ++dev-1-0-9: Ilho Lee ++ - Ext-interrupts handlers added. ++ ++ Added Files: ++ A arch/arm/plat-s5pc1xx/irq-eint.c ++ ++dev-1-0-10: Ilho Lee ++ - SMC9115 ethernet(100Mbps) D/D ported. ++ ++ Added Files: ++ A arch/arm/plat-s5pc1xx/irq-eint.c ++ ++dev-1-0-11: Ilho Lee ++ - dev-adc.c deleted. ++ ++ Deleted Files: ++ D arch/arm/plat-s3c/dev-adc.c ++ ++rel-1-0-1: Kyoungil Kim ++ - Git Release (08.12.09) ++ ++v2.6.28-rc7-s5pc1xx-r0d0: Kyoungil Kim ++ - s5pc1xx rc7 initial git tag ++ ++v2.6.28-rc7-s5pc1xx-r0d1: Ilho Lee ++ - PL330 DMA D/D changed. ++ ++ Modified files: ++ M arch/arm/plat-s3c/dma-pl330.c ++ M arch/arm/plat-s3c/dma-pl330-mcode.h ++ ++v2.6.28-rc7-s5pc1xx-r0d2: Jongpill Lee ++ - System Timer support on SMDKC100 ++ ++ Added Files: ++ A arch/arm/plat-s5pc1xx/s5pc1xx-time.c ++ ++v2.6.28-rc7-s5pc1xx-r0d3: Jongpill Lee ++ - System Timer bug fixed ++ ++ Modified Files: ++ M ChangeLog_s5pc1xx ++ M arch/arm/mach-s5pc100/cpu.c ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/include/mach/tick.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s3c/Makefile ++ M arch/arm/plat-s3c/include/plat/map-base.h ++ M arch/arm/plat-s5pc1xx/Makefile ++ M arch/arm/plat-s5pc1xx/include/plat/regs-sys-timer.h ++ ++v2.6.28-rc8-s5pc1xx: Kyoungil Kim ++ - s5pc1xx rc8 patch ++ ++v2.6.28-rc8-s5pc1xx-r0d0: Kyoungil Kim ++ ++v2.6.28-rc8-s5pc1xx-r0d1: Abhilash Kesavan ++ - S5PC100 NAND driver support ++ ++ Added Files: ++ A arch/arm/configs/smdkc100mtd_defconfig ++ ++ Modified Files: ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s3c/Kconfig ++ M arch/arm/plat-s3c/include/plat/partition.h ++ M arch/arm/plat-s5pc1xx/devs.c ++ M drivers/mtd/nand/Kconfig ++ M drivers/mtd/nand/s3c_nand.c ++ ++v2.6.28-rc8-s5pc1xx-r0d2: Jinsung Yang ++ - Fix for wrong comments ++ ++v2.6.28-rc8-s5pc1xx-r0d3: Jinsung Yang ++ - Merge from s3c64xx branch ++ ++v2.6.28-rc8-s5pc1xx-r0d4: Abhilash Kesavan ++ - Touch-up for Nand ++ ++ Modified Files: ++ M arch/arm/configs/smdkc100mtd_defconfig ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ ++ ++v2.6.28-rc8-s5pc1xx-r0d5: Abhilash Kesavan ++ - Support for HS-MMC and USB ++ ++ Added Files: ++ A arch/arm/mach-s5pc100/include/mach/usb-control.h ++ A arch/arm/mach-s5pc100/setup-sdhci.c ++ ++ Modified Files: ++ M arch/arm/configs/smdkc100mtd_defconfig ++ M arch/arm/configs/smdkc100nfs_defconfig ++ M arch/arm/mach-s5pc100/Kconfig ++ M arch/arm/mach-s5pc100/Makefile ++ M arch/arm/mach-s5pc100/cpu.c ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s3c/include/plat/sdhci.h ++ M arch/arm/plat-s5pc1xx/devs.c ++ M arch/arm/plat-s5pc1xx/include/plat/regs-clock.h ++ M arch/arm/plat-s5pc1xx/include/plat/regs-sys.h ++ M drivers/mmc/host/Kconfig ++ M drivers/mmc/host/sdhci-s3c.c ++ M drivers/usb/Kconfig ++ M drivers/usb/gadget/Kconfig ++ M drivers/usb/gadget/f_rndis.c ++ M drivers/usb/gadget/s3c_udc_otg.c ++ M drivers/usb/host/ohci-hcd.c ++ M drivers/usb/host/ohci-s3c2410.c ++ ++v2.6.28-rc8-s5pc1xx-r0d6: Ilho Lee ++ - Touchscreen D/D got enabled and PL330 S&G DMA operations supported. ++ ++ Modified Files: ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s3c/dma-pl330.c ++ ++v2.6.28-rc8-s5pc1xx-r0d7: Abhilash Kesavan ++ - Support for HS-MMC for S5PC1XX (Completed) ++ ++ Added Files: ++ A drivers/mmc/host/s3c-hsmmc.c ++ A drivers/mmc/host/s3c-hsmmc.h ++ A arch/arm/plat-s5pc1xx/include/plat/regs-hsmmc.h ++ ++ Deleted Files: ++ D arch/arm/mach-s5pc100/setup-sdhci.c ++ ++ Modified Files: ++ M arch/arm/configs/smdkc100mtd_defconfig ++ M arch/arm/configs/smdkc100nfs_defconfig ++ M arch/arm/mach-s5pc100/Kconfig ++ M arch/arm/mach-s5pc100/Makefile ++ M arch/arm/mach-s5pc100/cpu.c ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s5pc1xx/devs.c ++ M drivers/mmc/host/Kconfig ++ M drivers/mmc/host/Makefile ++ ++v2.6.28-rc8-s5pc1xx-r0d8: Jongpill Lee ++ - Bug fixed on clock ++ ++ Modified Files: ++ M arch/arm/plat-s3c/clock.c ++ ++v2.6.28-rc8-s5pc1xx-r0d9: Abhilash Kesavan ++ - Support for ADC and PWM for S5PC100 ++ ++ Added Files: ++ A arch/arm/plat-s5pc1xx/adc.c ++ A arch/arm/plat-s5pc1xx/pwm-s5pc100.c ++ A arch/arm/plat-s5pc1xx/pwm-s5pc100.h ++ ++ Modified Files: ++ M arch/arm/configs/smdkc100mtd_defconfig ++ M arch/arm/configs/smdkc100nfs_defconfig ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s3c/Kconfig ++ M arch/arm/plat-s3c/include/plat/regs-timer.h ++ M arch/arm/plat-s5pc1xx/Kconfig ++ M arch/arm/plat-s5pc1xx/Makefile ++ M drivers/mmc/host/s3c-hsmmc.c ++ M drivers/video/samsung/s3cfb.h ++ M drivers/video/samsung/s3cfb_fimd5x.c ++ ++v2.6.28-rc8-s5pc1xx-r1: Kyoungil Kim ++ - Internal Release(09.01.12) ++ ++v2.6.28-rc8-s5pc1xx-v1: Kyoungil Kim ++ - Official Release(09.01.12) ++ ++v2.6.28-rc8-s5pc1xx-r1d0: Kyoungil Kim ++ ++v2.6.28-rc8-s5pc1xx-r1d1: JongPill Lee ++ - Support IDLE Function on S5PC100 ++ ++ Added Files: ++ A arch/arm/plat-s5pc1xx/include/plat/regs-power.h ++ ++ Modified Files: ++ M arch/arm/mach-s5pc100/cpu.c ++ M arch/arm/mach-s5pc100/include/mach/system.h ++ ++v2.6.28-rc8-s5pc1xx-r1d2: Abhilash Kesavan ++ - Support OneNand on S5PC100 (I) ++ ++ Added Files: ++ A arch/arm/plat-s3c/include/plat/regs-onenand.h ++ ++ Modified Files: ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s3c/include/plat/partition.h ++ M drivers/mtd/onenand/Makefile ++ M drivers/mtd/onenand/onenand_bbt.c ++ M drivers/mtd/onenand/s3c_onenand.c ++ M drivers/mtd/onenand/s3c_onenand.h ++ ++v2.6.28-rc8-s5pc1xx-r1d3: Kyoungil Kim ++ - Support Keypad on S5PC100 ++ ++ Modified Files: ++ M arch/arm/configs/smdkc100_defconfig ++ M arch/arm/configs/smdkc100mtd_defconfig ++ M arch/arm/configs/smdkc100nfs_defconfig ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s5pc1xx/clock.c ++ M arch/arm/plat-s5pc1xx/devs.c ++ M drivers/input/keyboard/Kconfig ++ M drivers/input/keyboard/s3c-keypad.h ++ ++v2.6.28-rc8-s5pc1xx-r1d4: Abhilash Kesavan ++ - Support HS-SPI on S5PC100 ++ ++ Added Files: ++ A arch/arm/plat-s3c/include/plat/regs-spi.h ++ A drivers/spi/hspi-s3c.c ++ A drivers/spi/hspi-s3c.h ++ A drivers/spi/spi-dev.c ++ A drivers/spi/spi-dev.h ++ ++ Modified Files: ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s5pc1xx/devs.c ++ M drivers/spi/Kconfig ++ M drivers/spi/Makefile ++ ++v2.6.28-rc8-s5pc1xx-r1d5: Jongpill Lee ++ - Support APM on S5PC100 ++ ++ Added Files: ++ A arch/arm/plat-s5pc1xx/include/plat/pm.h ++ A arch/arm/plat-s5pc1xx/pm.c ++ A arch/arm/mach-s5pc100/pm.c ++ A arch/arm/plat-s5pc1xx/sleep.S ++ ++ Modified Files: ++ M arch/arm/mach-s5pc100/Makefile ++ M arch/arm/mach-s5pc100/include/mach/regs-irq.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s5pc1xx/Makefile ++ M arch/arm/plat-s5pc1xx/include/plat/regs-power.h ++ M arch/arm/plat-s5pc1xx/s5pc100-clock.c ++ M drivers/serial/s5pc100.c ++ M drivers/serial/samsung.c ++ M drivers/serial/samsung.h ++ M drivers/video/samsung/s3cfb_fimd5x.c ++ ++v2.6.28-rc8-s5pc1xx-r1d6: Jongpill Lee ++ - Support RTC Wakeup from Sleep mode ++ ++ Modified Files: ++ M arch/arm/plat-s5pc1xx/pm.c ++ ++v2.6.28-rc8-s5pc1xx-r1d7: PyoungJae Jung/Jiun Yu ++ - Support MFC driver ++ ++ Modified Files: ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s5pc1xx/devs.c ++ ++v2.6.28-rc8-s5pc1xx-r2: Kyoungil Kim ++ - Official Release(09.01.23) ++ ++v2.6.28-rc8-s5pc1xx-r2d0: Kyoungil Kim ++ ++v2.6.28-rc8-s5pc1xx-r2d1: Byungjae Lee ++ - Support CDC Ethernet and RNDIS ++ - for SMDKc100 UBS OTG Deive role on DMA mode ++ ++ Modified Files: ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s3c/include/plat/regs-otg.h ++ M drivers/usb/gadget/Kconfig ++ M drivers/usb/gadget/epautoconf.c ++ M drivers/usb/gadget/s3c_udc.h ++ M drivers/usb/gadget/s3c_udc_otg.c ++ M drivers/usb/gadget/u_ether.c ++ ++ Added Files: ++ A drivers/usb/gadget/s3c_udc_otg_xfer_dma.c ++ A drivers/usb/gadget/s3c_udc_otg_xfer_slave.c ++ ++ ++v2.6.28-rc8-s5pc1xx-r2d2: Jinsung Yang ++ - S5PC100 FIMC Driver ++ - Compilable version ++ ++ Modified files: ++ M drivers/media/video/Kconfig ++ M drivers/media/video/Makefile ++ M include/linux/i2c-id.h ++ ++ Added files: ++ A arch/arm/plat-s5pc1xx/include/plat/fimc.h ++ A arch/arm/plat-s5pc1xx/include/plat/regs-fimc.h ++ A drivers/media/video/samsung/Kconfig ++ A drivers/media/video/samsung/Makefile ++ A drivers/media/video/samsung/s3c_fimc.h ++ A drivers/media/video/samsung/s3c_fimc4x_regs.c ++ A drivers/media/video/samsung/s3c_fimc_cfg.c ++ A drivers/media/video/samsung/s3c_fimc_core.c ++ A drivers/media/video/samsung/s3c_fimc_v4l2.c ++ A drivers/media/video/samsung/s5k4ba.c ++ A drivers/media/video/samsung/s5k4ba.h ++ ++v2.6.28-rc8-s5pc1xx-r2d3: Jinsung Yang ++ - S5PC100 FIMC device setup support ++ ++ Modified files: ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s5pc1xx/Kconfig ++ M arch/arm/plat-s5pc1xx/Makefile ++ ++ Added files: ++ A arch/arm/plat-s5pc1xx/dev-fimc0.c ++ A arch/arm/plat-s5pc1xx/dev-fimc1.c ++ A arch/arm/plat-s5pc1xx/dev-fimc2.c ++ A arch/arm/plat-s5pc1xx/setup-fimc0.c ++ A arch/arm/plat-s5pc1xx/setup-fimc1.c ++ A arch/arm/plat-s5pc1xx/setup-fimc2.c ++ ++v2.6.28-rc8-s5pc1xx-r2d4: Kyoungil Kim ++ - modified otg_phy_init proto type ++ ++ Modified files: ++ M drivers/usb/gadget/s3c_udc_otg.c ++ ++v2.6.28-rc8-s5pc1xx-r2d5: Hatim Ali ++ - S5PC100 Watchdog Timer support ++ ++ Modified files: ++ M arch/arm/configs/smdkc100nfs_defconfig ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s5pc1xx/devs.c ++ M drivers/watchdog/Kconfig ++ ++v2.6.28-rc8-s5pc1xx-r2d6: Abhilash Kesavan ++ - S5PC100 AC97 WM9713 support ++ ++ Modified files: ++ M arch/arm/mach-s5pc100/dma.c ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s5pc1xx/devs.c ++ M sound/soc/codecs/wm9713.c ++ M sound/soc/s5pc1xx/Kconfig ++ M sound/soc/s5pc1xx/Makefile ++ ++ Added Files: ++ A sound/soc/s5pc1xx/s5pc1xx-ac97.c ++ A sound/soc/s5pc1xx/s5pc1xx-ac97.h ++ A sound/soc/s5pc1xx/smdkc100_wm9713.c ++ ++v2.6.28-rc8-s5pc1xx-r2d7: Jinsung Yang ++ - S5PC100 FIMC driver ++ - Camera input and memory output support ++ - Both camera channels (A and B) support ++ - Preview and capture related functionalities support ++ - S5K3BA and S5K4BA module support ++ ++v2.6.28-rc8-s5pc1xx-r2d8: Hatim Ali ++ - S5PC100 Notification LED support ++ ++ Modified files: ++ M arch/arm/Kconfig ++ M arch/arm/mach-s5pc100/Makefile ++ ++ Added Files: ++ A arch/arm/mach-s5pc100/leds-s5pc100.c ++ A arch/arm/mach-s5pc100/leds.c ++ A arch/arm/mach-s5pc100/leds.h ++ ++v2.6.28-rc8-s5pc1xx-r2d9: Abhilash Kesavan ++ - Enabled LCD/OSD Support for S5PC100 ++ ++ Modified files: ++ M arch/arm/plat-s5pc1xx/devs.c ++ M drivers/video/samsung/s3cfb.h ++ M drivers/video/samsung/s3cfb_spi.c ++ ++v2.6.28-rc8-s5pc1xx-r2d10: Jinsung Yang ++ - S5PC100 FIMC driver ++ - Alpha Release ++ - Camera input support ++ - Memory input support ++ - Memory output support ++ - LCD FIFO output support ++ - Both camera channels (A and B) support ++ - Preview and capture related functionalities support ++ - S5K3BA and S5K4BA module support ++ ++v2.6.28.6-s5pc1xx: Kyoungil Kim ++ ++v2.6.28.6-s5pc1xx-r0d0: Kyoungil Kim ++ ++v2.6.28.6-s5pc1xx-r0d1: Abhilash Kesavan ++ - Pre-Beta Version ++ ++v2.6.28.6-s5pc1xx-r0d2: Jinsung Yang ++ - FIMC support for SMDKC100 ++ - Including reserved memory feature with bootmem ++ - All functions have been finished on the planning except for 'Input Rotator' with LCD FIFO Output ++ ++ ++v2.6.28.6-s5pc1xx-r0d3: Abhilash Kesavan ++ - IrDA support for S5PC100 ++ ++ Modified files: ++ M drivers/net/irda/s3c-sir.c ++ M include/net/irda/irda_device.h ++ ++v2.6.28.6-s5pc1xx-r0d4: Jae-Cheol Lee ++ - Support CPUFREQ for SMDKC100 ++ - DFS is only enabled, not DVS. ++ ++ Modified files: ++ M arch/arm/plat-s5pc1xx/s5pc100-clock.c ++ M arch/arm/Kconfig ++ M arch/arm/plat-s5pc1xx/Makefile ++ M arch/arm/plat-s3c/clock.c ++ ++ Added files: ++ A arch/arm/plat-s5pc1xx/s5pc1xx-cpufreq.c ++ A arch/arm/plat-s5pc1xx/changediv.S ++ A arch/arm/plat-s5pc1xx/ltc3714.c ++ ++v2.6.28.6-s5pc1xx-r0d5: Kukjin Kim ++ - System Timer Modified for EVT1 ++ ++ Modified files: ++ M arch/arm/plat-s5pc1xx/include/plat/regs-sys-timer.h ++ M arch/arm/plat-s5pc1xx/s5pc1xx-time.c ++ ++v2.6.28.6-s5pc1xx-r0d6: Jonghun Han ++ - S5PC100 FIMG-2D driver support ++ Modified files: ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s3c/include/plat/regs-g2d.h ++ M arch/arm/plat-s5pc1xx/devs.c ++ M drivers/media/video/samsung/g2d/Kconfig ++ M drivers/media/video/samsung/g2d/s3c_fimg2d2x.c ++ ++v2.6.28.6-s5pc1xx-r0d7: Jae-Cheol Lee ++ - Support SMDKC100 EVT1 POP type (Onenand+mDDR+OneDRAM) ++ Modified files: ++ M arch/arm/configs/smdkc100onenand_defconfig ++ M arch/arm/plat-s5pc1xx/cpu.c ++ M arch/arm/plat-s5pc1xx/s5pc100-clock.c ++ ++v2.6.28.6-s5pc1xx-r0d8: PyoungJae Jung/JiUn Yu ++ - Support MFC (FIMV) for s5pc100 ++ - MFC driver is Alpha version ++ - remove CMM support and support bootmem memory secure way ++ - change directory name to separate to S3C6410 MFC driver ++ ++ Added files: ++ A drivers/media/video/samsung/mfc40/command_control_fw.c ++ A drivers/media/video/samsung/mfc40/s3c_mfc_errorno.h ++ A drivers/media/video/samsung/mfc40/h263_dec_fw.c ++ A drivers/media/video/samsung/mfc40/s3c_mfc_fw.h ++ A drivers/media/video/samsung/mfc40/h264_dec_fw.c ++ A drivers/media/video/samsung/mfc40/s3c-mfc.h ++ A drivers/media/video/samsung/mfc40/h264_enc_fw.c ++ A drivers/media/video/samsung/mfc40/s3c_mfc_interface.h ++ A drivers/media/video/samsung/mfc40/Kconfig ++ A drivers/media/video/samsung/mfc40/s3c_mfc_intr.c ++ A drivers/media/video/samsung/mfc40/Makefile ++ A drivers/media/video/samsung/mfc40/s3c_mfc_intr.h ++ A drivers/media/video/samsung/mfc40/mp2_dec_fw.c ++ A drivers/media/video/samsung/mfc40/s3c_mfc_logmsg.c ++ A drivers/media/video/samsung/mfc40/mp4_dec_fw.c ++ A drivers/media/video/samsung/mfc40/s3c_mfc_logmsg.h ++ A drivers/media/video/samsung/mfc40/mp4_dec_order_fw.c ++ A drivers/media/video/samsung/mfc40/s3c_mfc_memory.c ++ A drivers/media/video/samsung/mfc40/mp4_enc_fw.c ++ A drivers/media/video/samsung/mfc40/s3c_mfc_memory.h ++ A drivers/media/video/samsung/mfc40/s3c_mfc_buffer_manager.c ++ A drivers/media/video/samsung/mfc40/s3c_mfc_opr.c ++ A drivers/media/video/samsung/mfc40/s3c_mfc_buffer_manager.h ++ A drivers/media/video/samsung/mfc40/s3c_mfc_opr.h ++ A drivers/media/video/samsung/mfc40/s3c-mfc.c ++ A drivers/media/video/samsung/mfc40/s3c_mfc_types.h ++ A drivers/media/video/samsung/mfc40/s3c_mfc_common.c ++ A drivers/media/video/samsung/mfc40/vc1_dec_fw.c ++ A drivers/media/video/samsung/mfc40/s3c_mfc_common.h ++ A arch/arm/plat-s5pc1xx/include/plat/regs-mfc.h ++ ++ ++ Modified files: ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ ++v2.6.28.6-s5pc1xx-r0d9: Jonghun Han ++ - S5PC100 FIMG-3D driver support ++ Modified files: ++ M arch/arm/plat-s3c/dma-pl330.c ++ M arch/arm/plat-s3c/include/mach/s3c-dma.h ++ M drivers/char/s3c_mem.c ++ M drivers/char/s3c_mem.h ++ M drivers/media/video/samsung/g3d/Kconfig ++ M drivers/media/video/samsung/g3d/s3c_fimg3d.h ++ ++v2.6.28.6-s5pc1xx-r0d10: Seungchull Suh ++ - SMC9115 works correctly. Before, full-duplex mode is not set. ++ M drivers/net/smc911x.c ++ ++ ++v2.6.28.6-s5pc1xx-r1: Kyoungil Kim ++ - Official Release(09.03.20) ++ ++v2.6.28.6-s5pc1xx-r1d0: Kyoungil Kim ++ ++v2.6.28.6-s5pc1xx-r1d1: Jaeryul Oh ++ - Support JPEG for s5pc100 ++ ++ Added files: ++ A drivers/media/video/samsung/jpeg_v2/jpg_mem.c ++ A drivers/media/video/samsung/jpeg_v2/jpg_misc.c ++ A drivers/media/video/samsung/jpeg_v2/s3c-jpeg.c ++ A drivers/media/video/samsung/jpeg_v2/jpg_opr.c ++ A drivers/media/video/samsung/jpeg_v2/log_msg.c ++ ++ A drivers/media/video/samsung/jpeg_v2/log_msg.h ++ A drivers/media/video/samsung/jpeg_v2/jpg_conf.h ++ A drivers/media/video/samsung/jpeg_v2/jpg_mem.h ++ A drivers/media/video/samsung/jpeg_v2/jpg_misc.h ++ A drivers/media/video/samsung/jpeg_v2/regs-jpeg.h ++ A drivers/media/video/samsung/jpeg_v2/s3c-jpeg.h ++ A drivers/media/video/samsung/jpeg_v2/jpg_opr.h ++ A drivers/media/video/samsung/jpeg_v2/Makefile ++ A drivers/media/video/samsung/jpeg_v2/Kconfig ++ ++ Modified files: ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s5pc1xx/devs.c ++ M drivers/media/video/samsung/Kconfig ++ M drivers/media/video/samsung/Makefile ++ ++v2.6.28.6-s5pc1xx-r1d2: Kyoungil Kim ++ - The last tag for s5pc1xx branch(09.03.24) ++ ++current linux-2.6-samsung repository ChangeLog ++----------------------------------------------------------------------- ++v2.6.28.6-samsung: Kyoungil Kim ++ - Merge s3c64xx branch and s5pc1xx branch to master branch(09.03.24) ++ ++v2.6.28.6-samsung-r0d0: Kyoungil Kim ++ ++v2.6.28.6-samsung-r0d1: Kukjin Kim ++ - Remove swp file ++ ++ Removed Files: ++ R arch/arm/plat-s3c/include/plat/.cpu-freq.h.swp ++ ++v2.6.28.6-samsung-r0d2: Kyoungil Kim ++ - Unified the ChangeLog files ++ ++ Modified Files: ++ M ChangeLog ++ ++ Deleted Files: ++ D ChangeLog_s3c64xx ++ D ChangeLog_s5pc1xx ++ ++v2.6.28.6-samsung-r0d3: Kukjin Kim ++ - System Timer initialize modified ++ ++ Modified Files: ++ M arch/arm/plat-s5pc1xx/s5pc1xx-time.c ++ ++v2.6.28.6-samsung-r0d4: Kukjin Kim ++ - System Timer init and setup function remodified ++ ++ Modified Files: ++ M arch/arm/plat-s5pc1xx/s5pc1xx-time.c ++ ++v2.6.28.6-samsung-r0d5: Kukjin Kim ++ - Support extcsd revision 1.3 ++ ++ Modified Files: ++ M drivers/mmc/core/mmc.c ++ ++v2.6.28.6-samsung-r0d6: Jaeryul Oh ++ - JPEG for c100 is updated ++ ++ Modified Files: ++ M drivers/media/video/samsung/Kconfig ++ M drivers/media/video/samsung/jpeg_v2/jpg_mem.h ++ M drivers/media/video/samsung/jpeg_v2/jpg_opr.c ++ M drivers/media/video/samsung/jpeg_v2/jpg_opr.h ++ M drivers/media/video/samsung/jpeg_v2/s3c-jpeg.c ++ M drivers/media/video/samsung/jpeg_v2/s3c-jpeg.h ++ ++v2.6.28.6-samsung-r0d7: Jae-Cheol Lee ++ - Adopting system timer h/w bug workaround ++ ++ Modified files: ++ M arch/arm/plat-s5pc1xx/s5pc1xx-time.c ++ ++v2.6.28.6-samsung-r0d8: Byungjae Lee ++ - Implemented OTG Host role for SMDKC100 ++ OTG Host role support only MassStorage and HID(Keyboard, Mouse) ++ ++ Modified Files: ++ M arch/arm/configs/smdkc100mtd_defconfig ++ M arch/arm/configs/smdkc100onenand_defconfig ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s5pc1xx/devs.c ++ M drivers/usb/host/Kconfig ++ M drivers/usb/host/s3c-otg/s3c-otg-hcdi-debug.h ++ M drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.c ++ M drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.h ++ M drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.h ++ M drivers/usb/host/s3c-otg/s3c-otg-oci.c ++ M drivers/usb/host/s3c-otg/s3c-otg-oci.h ++ ++v2.6.28.6-samsung-r0d9: Jonghun Han ++ - Support YUV422 Interleave output for FIMC ++ ++ Modified Files: ++ M drivers/media/video/samsung/fimc/s3c_fimc.h ++ M drivers/media/video/samsung/fimc/s3c_fimc3x_regs.c ++ M drivers/media/video/samsung/fimc/s3c_fimc_cfg.c ++ ++v2.6.28.6-samsung-r0d10: Kyoungil Kim ++ - change the smc911 driver from full duplex to half duplex ++ ++ Modified Files: ++ M drivers/net/smc911x.c ++ ++v2.6.28.6-samsung-r0d11: Jae-Cheol Lee ++ - Support SMDK6440 EVT0 board ++ ++ Modified Files: ++ M arch/arm/mach-s5p6440/mach-smdk6440.c ++ M arch/arm/plat-s5p64xx/include/plat/pll.h ++ ++v2.6.28.6-samsung-r0d12: Kyoungil Kim ++ - Prevent for SMDKC100 MM IP ++ ++v2.6.28.6-samsung-r0d13: Jae-Cheol Lee ++ - Fixed PLL calculation bug in MASK value ++ ++ Modified Files: ++ M arch/arm/plat-s3c64xx/include/plat/pll.h ++ M arch/arm/plat-s5pc1xx/include/plat/pll.h ++ ++v2.6.28.6-samsung-r0d14: Byungjae Lee ++ - Implemented USB OTG Device role for SMDK6440 ++ ++ Modified Files: ++ M arch/arm/configs/smdk6440ramdisk_defconfig ++ M arch/arm/mach-s5p6440/mach-smdk6440.c ++ M arch/arm/plat-s3c/include/plat/regs-otg.h ++ M arch/arm/plat-s5p64xx/devs.c ++ M arch/arm/plat-s5p64xx/include/plat/regs-clock.h ++ M drivers/usb/gadget/Kconfig ++ M drivers/usb/gadget/s3c_udc.h ++ M drivers/usb/gadget/s3c_udc_otg.c ++ ++v2.6.28.6-samsung-r0d15: Jongpill Lee ++ - Modify code for SPi ++ ++ Modified Files ++ M drivers/spi/hspi-s3c64xx.c ++ ++v2.6.28.6-samsung-r1: Jaeryul Oh ++ - Official Release (09.04.06) ++ ++v2.6.28.6-samsung-r1d0: Jae-Cheol Lee ++ - Modified default configuration for SMDK6440 ++ Modified Files: ++ M arch/arm/configs/smdk6440ramdisk_defconfig ++ ++v2.6.28.6-samsung-r1d1: Jaeryul Oh ++ - MFC, JPEG suspend/resume related code for SMDK6410 changed ++ Modified Files : ++ M drivers/media/video/samsung/jpeg/jpg_mem.c ++ M drivers/media/video/samsung/jpeg/s3c-jpeg.c ++ M drivers/media/video/samsung/mfc10/s3c_mfc.c ++ ++v2.6.28.6-samsung-r1d2: Jae-Cheol Lee ++ - Modified voltage regulator control code for SMDKC100 ++ Modified Files : ++ M arch/arm/plat-s5pc1xx/ltc3714.c ++ ++v2.6.28.6-samsung-r1d3: Jae-Cheol Lee ++ - Support CHIPID for S5P6440 ++ Modified Files: ++ M arch/arm/plat-s5pc1xx/cpu.c ++ ++v2.6.28.6-samsung-r1d4: Jiun Yu, PyoungJae Jung ++ - fixed cache issue in MFC driver ++ ++v2.6.28.6-samsung-r1d5: Jae-Cheol Lee ++ - Change Console UART port 0 -> 1 for SMDK6440 ++ Modified Files: ++ M arch/arm/configs/smdk6440ramdisk_defconfig ++ ++v2.6.28.6-samsung-r1d6: Byungjae Lee ++ - Fixed BUG USB OTG Device role for SMDK6440 and C100 ++ ++ Modified Files: ++ M drivers/usb/gadget/s3c_udc_otg.c ++ ++v2.6.28.6-samsung-r1d7: Jongpill LEe ++ - Support RTC for S5P6440 ++ ++ Modified files: ++ M arch/arm/mach-s5p6440/include/mach/map.h ++ M arch/arm/mach-s5p6440/mach-smdk6440.c ++ M arch/arm/plat-s3c/include/plat/regs-rtc.h ++ M arch/arm/plat-s5p64xx/devs.c ++ M drivers/rtc/Kconfig ++ M drivers/rtc/rtc-s3c.c ++ ++v2.6.28.6-samsung-r2: Kyoungil Kim ++ - Official Release for SMDK6410(09.04.09) ++ ++v2.6.28.6-samsung-r2d0: Jongpill LEe ++ - Support Watchdog timer for S5P6440 ++ ++ Modified Files: ++ M arch/arm/mach-s5p6440/include/mach/map.h ++ M arch/arm/mach-s5p6440/mach-smdk6440.c ++ M arch/arm/plat-s5p64xx/devs.c ++ M drivers/rtc/rtc-s3c.c ++ M drivers/watchdog/Kconfig ++ ++v2.6.28.6-samsung-r2d1: Jongpill Lee ++ - Support ADC Driver for S5P6440 ++ ++ Modified Files: ++ M arch/arm/mach-s5p6440/include/mach/map.h ++ M arch/arm/mach-s5p6440/mach-smdk6440.c ++ M arch/arm/plat-s3c64xx/adc.c ++ M arch/arm/plat-s5p64xx/Kconfig ++ M arch/arm/plat-s5p64xx/devs.c ++ ++v2.6.28.6-samsung-r2d2: Jiun, Yu, PyoungJae Jung ++ - fixed cache issue in MFC1.0(6410) driver ++ ++ Modified Files : ++ M drivers/media/video/samsung/mfc10/s3c_mfc_set_config.c ++ ++v2.6.28.6-samsung-r2d3: Jiun, Yu, PyoungJae Jung ++ - fixed cache issue in MFC1.0(6410) driver ++ - changed cache update way to dma_cache_maint ++ ++ Modified Files : ++ M drivers/media/video/samsung/mfc10/s3c_mfc_set_config.c ++ M drivers/media/video/samsung/mfc10/s3c_mfc.c ++ M drivers/media/video/samsung/mfc10/s3c_mfc_databuf.c ++ M drivers/media/video/samsung/mfc10/s3c_mfc_instance.c ++ M drivers/media/video/samsung/mfc10/s3c_mfc_set_config.c ++ ++v2.6.28.6-samsung-r2d4: Jae-Cheol Lee ++ - Support DVFS on SMDK6440 board ++ ++ Modified Files : ++ M arch/arm/Kconfig ++ M arch/arm/plat-s5p64xx/Makefile ++ M arch/arm/plat-s5p64xx/clock.c ++ M arch/arm/plat-s5p64xx/ltc3714.c ++ M arch/arm/plat-s5p64xx/s5p64xx-cpufreq ++ ++v2.6.28.6-samsung-r2d5: Jongpill Lee ++ - Modify some code for S5PC100 ++ ++ Modified Files : ++ M arch/arm/plat-s5pc1xx/include/plat/regs-clock.h ++ M arch/arm/plat-s5pc1xx/include/plat/regs-power.h ++ ++v2.6.28.6-samsung-r2d6: Jae-Cheol Lee ++ - Support backlight class by PWM on SMDK6440 board ++ ++ Added Files : ++ A arch/arm/plat-s5p64xx/pwm.c ++ ++ Modified Files : ++ M arch/arm/configs/smdk6440ramdisk_defconfig ++ M arch/arm/mach-s5p6440/cpu.c ++ M arch/arm/mach-s5p6440/mach-smdk6440.c ++ M arch/arm/plat-s3c/include/plat/clock.h ++ M arch/arm/plat-s3c/pwm-clock.c ++ M arch/arm/plat-s5p64xx/Kconfig ++ M arch/arm/plat-s5p64xx/Makefile ++ M arch/arm/plat-s5p64xx/clock.c ++ M arch/arm/plat-s5p64xx/pwm.c ++ M drivers/video/samsung/s3cfb_fimd5x.c ++ ++v2.6.28.6-samsung-r2d7: Jaeryul Oh ++ - MFC suspend/resume related code for SMDK6410 updated ++ Modified Files : ++ M drivers/media/video/samsung/mfc10/s3c_mfc.c ++ M drivers/media/video/samsung/mfc10/s3c_mfc_config.h ++ ++v2.6.28.6-samsung-r2d8: Jinsung Yang ++ - The 1st phase of MIPI-CSI support ++ ++ Addes files: ++ A arch/arm/plat-s5pc1xx/dev-csis.c ++ A arch/arm/plat-s5pc1xx/include/plat/csis.h ++ A arch/arm/plat-s5pc1xx/include/plat/regs-csis.h ++ A arch/arm/plat-s5pc1xx/setup-csis.c ++ A drivers/media/video/samsung/fimc/s3c_csis.c ++ A drivers/media/video/samsung/fimc/s3c_csis.h ++ ++ Modified files: ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s5pc1xx/Kconfig ++ M arch/arm/plat-s5pc1xx/Makefile ++ M arch/arm/plat-s5pc1xx/clock.c ++ M arch/arm/plat-s5pc1xx/include/plat/regs-clock.h ++ M drivers/media/video/samsung/fimc/Kconfig ++ M drivers/media/video/samsung/fimc/Makefile ++ M drivers/media/video/samsung/fimc/s3c_fimc.h ++ ++v2.6.28.6-samsung-r2d9: Jongpill Lee ++ - Temporary support APM for S5P6440 ++ ++ Added Files: ++ A arch/arm/mach-s5p6440/pm.c ++ A arch/arm/plat-s5p64xx/include/plat/pm.h ++ A arch/arm/plat-s5p64xx/pm.c ++ A arch/arm/plat-s5p64xx/sleep.S ++ ++ Modified Files: ++ M arch/arm/mach-s5p6440/Makefile ++ M arch/arm/mach-s5p6440/include/mach/gpio.h ++ M arch/arm/mach-s5p6440/include/mach/regs-irq.h ++ M arch/arm/mach-s5p6440/mach-smdk6440.c ++ M arch/arm/plat-s5p64xx/Makefile ++ M arch/arm/plat-s5p64xx/include/plat/regs-gpio.h ++ M drivers/video/samsung/s3cfb_fimd5x.c ++ ++v2.6.28.6-samsung-r2d10: Jae-Cheol Lee ++ - Support backlight class driver by PWM on SMDK6410 ++ ++ Added Files: ++ A arch/arm/plat-s3c64xx/pwm.c ++ ++ Modified Files: ++ M arch/arm/mach-s5p6440/include/mach/gpio.h ++ M arch/arm/mach-s3c6410/cpu.c ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c64xx/Kconfig ++ M arch/arm/plat-s3c64xx/Makefile ++ ++v2.6.28.6-samsung-r2d11: jongpill Lee ++ - bug fix on GPIO for S5P6440 ++ ++ MOdified Files: ++ M arch/arm/mach-s5p6440/include/mach/gpio.h ++ ++v2.6.28.6-samsung-r2d12: jongpill Lee ++ - APM Support for S5P6440 ++ ++ Modified Files: ++ M arch/arm/plat-s3c64xx/sleep.S ++ ++v2.6.28.6-samsung-r2d13: Jae-Cheol Lee ++ - Support old style PWM driver for SMDK6410 ++ ++ Modified Files: ++ M arch/arm/plat-s3c64xx/Kconfig ++ M arch/arm/plat-s3c64xx/Makefile ++ M arch/arm/plat-s3c64xx/pwm-s3c6410.c ++ M arch/arm/plat-s3c64xx/pwm-s3c6410.h ++ M drivers/video/samsung/s3cfb_fimd4x.c ++ ++v2.6.28.6-samsung-r2d14: Jongpill Lee ++ - Support reboot command ++ ++ Modified Files: ++ M arch/arm/mach-s3c6400/include/mach/system.h ++ M arch/arm/mach-s5p6440/include/mach/system.h ++ M arch/arm/plat-s3c/include/plat/regs-watchdog.h ++ ++v2.6.28.6-samsung-r2d15: Jaeryul Oh ++ - MFC memory buffer size is changed ++ Modified Files : ++ M drivers/media/video/samsung/mfc10/s3c_mfc_config.h ++ ++v2.6.28.6-samsung-r2d16: Abhilash Kesavan ++ - Support backlight class driver by PWM on SMDKC100 ++ ++ Added Files: ++ A arch/arm/plat-s5pc1xx/pwm.c ++ ++ Modified Files: ++ M arch/arm/mach-s5pc100/cpu.c ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s5pc1xx/Kconfig ++ M arch/arm/plat-s5pc1xx/Makefile ++ M arch/arm/plat-s3c/include/plat/clock.h ++ M drivers/video/samsung/s3cfb_fimd5x.c ++ M drivers/video/backlight/Kconfig ++ ++v2.6.28.6-samsung-r2d17: Kyoungil Kim ++ - Modified full speed configuration for gadget ++ ++ Modified Files: ++ M arch/arm/mach-s5p6440/mach-smdk6440.c ++ M drivers/usb/gadget/s3c_udc_otg.c ++ M drivers/usb/gadget/s3c_udc_otg_xfer_dma.c ++ ++v2.6.28.6-samsung-r3: Kyoungil Kim ++ - Official Release for SMDK6410(09.04.23) ++ ++v2.6.28.6-samsung-r3d0: Kyoungil Kim ++ ++v2.6.28.6-samsung-r3d1: Jaeryul Oh ++ - Clk name that MFC & JPEG (6410) uses is added ++ Modified Files : ++ M arch/arm/plat-s3c64xx/clock.c ++ M drivers/media/video/samsung/jpeg/s3c-jpeg.c ++ M drivers/media/video/samsung/mfc10/s3c_mfc.c ++ ++v2.6.28.6-samsung-r3d2: Jae-Cheol Lee ++ - Fixed APM bug on SMDKC100 ++ Modified Files: ++ M arch/arm/plat-s5pc1xx/pm.c ++ M arch/arm/plat-s5pc1xx/sleep.S ++ M arch/arm/plat-s5pc1xx/s5pc1xx-time.c ++ M arch/arm/plat-s5pc1xx/include/plat/regs-clock.h ++ M arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h ++ ++v2.6.28.6-samsung-r3d3: Thomas Abraham ++ - Added PM support for USB device on C100. ++ Modified Files: ++ M drivers/usb/gadget/s3c_udc_otg.c ++ M drivers/usb/gadget/file_storage.c ++ ++v2.6.28.6-samsung-r3d4: Jinsung Yang ++ - S5P6440 Post Processor Support ++ - Just compilable version ++ ++ Added files: ++ A arch/arm/plat-s5p64xx/bootmem.c ++ A arch/arm/plat-s5p64xx/dev-post.c ++ A arch/arm/plat-s5p64xx/include/plat/media.h ++ A arch/arm/plat-s5p64xx/include/plat/post.h ++ A arch/arm/plat-s5p64xx/include/plat/regs-post.h ++ A arch/arm/plat-s5p64xx/include/plat/regs-pp.h ++ A arch/arm/plat-s5p64xx/setup-post.c ++ A drivers/media/video/samsung/post/s3c_post.h ++ A drivers/media/video/samsung/post/s3c_post_cfg.c ++ A drivers/media/video/samsung/post/s3c_post_core.c ++ A drivers/media/video/samsung/post/s3c_post_regs.c ++ A drivers/media/video/samsung/post/s3c_post_v4l2.c ++ ++ Modified files: ++ M arch/arm/mach-s5p6440/include/mach/map.h ++ M arch/arm/plat-s5p64xx/Makefile ++ M arch/arm/plat-s5p64xx/clock.c ++ M drivers/media/video/samsung/Kconfig ++ M drivers/media/video/samsung/post/Kconfig ++ M drivers/media/video/samsung/post/Makefile ++ ++v2.6.28.6-samsung-r3d5: Thomas Abraham ++ - Fixed PM bug in USB gadget. ++ Modified Files: ++ M drivers/usb/gadget/s3c_udc_otg.c ++ ++v2.6.28.6-samsung-r3d6: Abhilash Kesavan ++ - Added PM defconfig (Base), Onenand Platform and Misc PM Fixes ++ Modified Files: ++ M drivers/mtd/onenand/generic.c ++ M drivers/mtd/onenand/s3c_onenand.c ++ M drivers/media/video/samsung/g3d/s3c_fimg3d.c ++ M sound/soc/codecs/wm9713.c ++ ++ Added File: ++ A arch/arm/configs/smdkc100pm_defconfig ++ ++v2.6.28.6-samsung-r3d7: Jongpill Lee ++ - ADC bug fixed on SMDK6440 ++ ++ Modified Files: ++ ++ M arch/arm/plat-s5p64xx/adc.c ++ ++v2.6.28.6-samsung-r3d8: Jae-Cheol Lee ++ - Support DFS on SMDK6440 ++ Modified Files: ++ M arch/arm/plat-s5p64xx/clock.c ++ ++v2.6.28.6-samsung-r3d9: SungJun Bae ++ - merged with mfc branch v2.6.28.6-samsung-mfc-r0d0 ++ ++v2.6.28.6-samsung-r3d10: Jongpill Lee ++ - Bug fixed on APM driver for S3C6410 ++ ++ MOdified Files: ++ M arch/arm/plat-s3c64xx/sleep.S ++ ++v2.6.28.6-samsung-r4: Kyoungil Kim ++ - Official Release for SMDK6410, 6440, C100(09.04.30) ++ ++v2.6.28.6-samsung-r4d0: Kyoungil Kim ++ ++v2.6.28.6-samsung-r4d1: Jassi ++ - Addded SPI driver support for S3C6410 and S5P6440 acc to latest ++ Linux-SPI architecture ++ ++v2.6.28.6-samsung-r5: Kyoungil Kim ++ - Official Release for SMDK6410, 6440, C100(09.04.30) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/ChangeLog_mfc linux-2.6.28.6/ChangeLog_mfc +--- linux-2.6.28/ChangeLog_mfc 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/ChangeLog_mfc 2009-04-30 09:36:36.000000000 +0200 +@@ -0,0 +1,2069 @@ ++previous samsung-ap-2.6 repository ChangeLog_s3c64xx for s3c64xx branch ++----------------------------------------------------------------------- ++rel-0-0-0 : Kwanghyun La (Nov.10.2008) ++ It's not fixed version , just only initial copy version for ++ estimation. ++ ++dev-0-0-1 : Ilho Lee ++dev-0-0-2 : Ilho Lee ++ Touchscreen D/D added, but Ethernet D/D is being adding. ++ ++dev-0-0-3 : Jongpill Lee ++ Support ADC driver and merge adc-s3c64xx.c and adc-s3c24xx.c file ++ ++ Removed Files: ++ R A arch/arm/plat-s3c64xx/adc-s3c64xx.c ++ ++ Added Files: ++ A arch/arm/plat-s3c/adc.c ++ ++ Modified Files: ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/Kconfig ++ M arch/arm/plat-s3c/Makefile ++ M arch/arm/plat-s3c/include/plat/adc.h ++ M drivers/char/Kconfig ++ ++dev-0-0-4 : Jongpill Lee ++ Bug fixed on ADC driver ++ ++ Modified Files: ++ M arch/arm/plat-s3c/adc.c ++ ++dev-0-0-5 : Ilho Lee ++ SMC9115 ethernet D/D is working(small_root only) ++ ++dev-0-0-6: Jinsung Yang ++ - NAND driver support ++ ++ Added files: ++ A arch/arm/configs/smdk6410mtd_defconfig ++ A arch/arm/plat-s3c/include/plat/partition.h ++ A drivers/mtd/nand/s3c_nand.c ++ ++ Modified files: ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/Kconfig ++ M arch/arm/plat-s3c/include/plat/nand.h ++ M arch/arm/plat-s3c/include/plat/regs-nand.h ++ M arch/arm/plat-s3c64xx/devs.c ++ M drivers/mtd/nand/Kconfig ++ M drivers/mtd/nand/Makefile ++ ++dev-0-0-7: Sungjun Bae ++ - I2S WM8580, I2SWM8990 Complete. ++ ++ Modified Files: ++ M arch/arm/configs/smdk6410mtd_defconfig arch/arm/configs/smdk6410nfs_defconfig ++ M arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h ++ M arch/arm/plat-s3c64xx/include/plat/regs-clock.h include/sound/soc.h ++ M sound/soc/soc-core.c sound/soc/codecs/wm8580.c sound/soc/codecs/wm8990.c ++ ++dev-0-0-8: Sungjun Bae ++ - DMA File Structure was changed. ++ ++ Modified Files: ++ M arch/arm/plat-s3c/Makefile ++ M arch/arm/plat-s3c/include/mach/s3c-dma.h ++ M arch/arm/plat-s3c64xx/Makefile ++ Added Files: ++ A arch/arm/plat-s3c/dma-pl080.c ++ Removed Files: ++ R arch/arm/plat-s3c64xx/dma-pl080.c ++ ++dev-0-0-9: Ilho Lee ++ - PL330 DMA D/D file added ++ ++ Modified Files: ++ M arch/arm/plat-s3c/Makefile ++ M arch/arm/plat-s3c/Kconfig ++ ++ Added Files: ++ A arch/arm/plat-s3c/dma-pl330.c ++ A arch/arm/plat-s3c/dma-pl330-microcode.c ++ ++ ++dev-0-0-10: eyryu ++ - Add SMDKC100 initial. ++ ++dev-0-0-11: Ilho Lee ++ - DMA definition files changed ++ ++ Modified Files: ++ M arch/arm/mach-s3c6410/dma.c ++ M arch/arm/mach-s5pc100/dma.c ++ ++dev-0-0-12: Jinsung Yang ++ - gpiolib support for s5pc1xx architecture ++ ++ Modified files: ++ M arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h ++ M arch/arm/mach-s5pc100/include/mach/gpio.h ++ M arch/arm/plat-s3c/gpio-config.c ++ M arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h ++ ++ Added files: ++ A arch/arm/plat-s5pc1xx/gpiolib.c ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-a0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-a1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-b.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-c.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-d.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-e0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-e1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f2.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f3.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g2.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g3.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h2.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h3.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-i.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j2.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j3.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j4.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k2.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k3.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp00.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp01.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp02.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp03.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp04.h ++ ++dev-0-0-13: eyryu ++ - Add SMDKC100 clock & serial ++ ++dev-0-0-14: Ilho Lee ++ - ADC D/D added ++ ++ Added Files: ++ A arch/arm/plat-s3c24xx/adc.c ++ A arch/arm/plat-s3c64xx/adc.c ++ ++dev-0-0-15: eyryu ++ - Support SMDKC100 UART driver ++ - Add SMDKC100 clock & serial ++ ++rel-1-0-0: Kyoungil Kim ++ - Official Release (08.11.27) ++ ++dev-1-0-0: Kyoungil Kim ++ ++dev-1-0-1: Ilho Lee ++ - CPU idle added ++ ++ Added Files: ++ A arch/arm/mach-s3c6400/idle.h ++ A arch/arm/mach-s5pc100/idle.h ++ ++ Modified Files: ++ M arch/arm/mach-s3c6410/cpu.c ++ M arch/arm/mach-s5pc100/cpu.c ++ ++dev-1-0-2: Ilho Lee ++ - S3C24XX -> S3C changed in the S3C DMA D/D. ++ ++ Modified Files: ++ M arch/arm/mach-s3c6410/dma.c ++ M arch/arm/mach-s5pc100/dma.c ++ M arch/arm/plat-s3c/dma-pl080.c ++ M arch/arm/plat-s3c/dma-pl330.c ++ M arch/arm/plat-s3c/include/plat/s3c-dma.h ++ ++dev-1-0-3: Ilho Lee ++ - PL330 DMA D/D is adding.. ++ ++ Modified Files: ++ M arch/arm/plat-s3c/dma-pl330.c ++ M arch/arm/plat-s3c/dma-pl330-mcode.h ++ M arch/arm/plat-s3c/include/mach/s3c-dma.h ++ ++dev-1-0-4: Byungjae Lee ++ - Support File Storage Gadget for SMDK6410 HS USB OTG ++ ++ Modified Files: ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/cpu.c ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c64xx/devs.c ++ M arch/arm/plat-s3c64xx/include/plat/regs-clock.h ++ M drivers/usb/gadget/Kconfig ++ M drivers/usb/gadget/Makefile ++ M drivers/usb/gadget/epautoconf.c ++ M drivers/usb/gadget/gadget_chips.h ++ ++ Added Files: ++ A arch/arm/plat-s3c/include/plat/regs-otg.h ++ A drivers/usb/gadget/s3c_udc.h ++ A drivers/usb/gadget/s3c_udc_otg.c ++ ++dev-1-0-5: Ilho Lee ++ - S3C touchscreen D/D changed. ++ ++ Modified Files: ++ M drivers/input/touchscreen/s3c-ts.c ++ ++dev-1-0-6: Jinsung Yang ++ - Clock system support for S5PC100 ++ ++ Modified files: ++ M arch/arm/plat-s3c/clock.c ++ M arch/arm/plat-s3c/include/plat/clock.h ++ M arch/arm/plat-s5pc1xx/clock.c ++ M arch/arm/plat-s5pc1xx/s5pc100-clock.c ++ M arch/arm/plat-s5pc1xx/include/plat/pll.h ++ M arch/arm/plat-s5pc1xx/include/plat/regs-clock.h ++ ++dev-1-0-7: Jinsung Yang ++ - LCD (LTE480WV) support for SMDKC100 ++ ++ Modified files: ++ drivers/video/samsung/s5pfb_fimd5x.c ++ ++dev-1-0-8: Byungjae Lee ++ - Masked HCLK for USB OTG at register clocks ++ ++ Modified files: ++ M arch/arm/plat-s3c64xx/clock.c ++ M drivers/usb/gadget/s3c_udc_otg.c ++ ++dev-1-0-9: Ilho Lee ++ - Ext-interrupts handlers added. ++ ++ Added Files: ++ A arch/arm/plat-s5pc1xx/irq-eint.c ++ ++dev-1-0-10: Ilho Lee ++ - SMC9115 ethernet(100Mbps) D/D ported. ++ ++ Added Files: ++ A arch/arm/plat-s5pc1xx/irq-eint.c ++ ++dev-1-0-11: Ilho Lee ++ - dev-adc.c deleted. ++ ++ Deleted Files: ++ D arch/arm/plat-s3c/dev-adc.c ++ ++rel-1-0-1: Kyoungil Kim ++ - Git Release (08.12.09) ++ ++v2.6.28-rc7-s3c64xx-r0d0: Kyoungil Kim ++ - s3c64xx rc7 initial git tag ++ ++v2.6.28-rc8-s3c64xx: Kyoungil Kim ++ - s3c64xx rc8 patch ++ ++v2.6.28-rc8-s3c64xx-r0d0: Kyoungil Kim ++ ++v2.6.28-rc8-s3c64xx-r0d1: Jinsung Yang ++ - Fix for wrong comments ++ ++v2.6.28-rc8-s3c64xx-r0d2: Jongpill Lee ++ ++ - bug fixed about OS Timer ++ ++ Modified Files: ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/include/plat/cpu.h ++ M arch/arm/plat-s3c/include/plat/regs-timer.h ++ M arch/arm/plat-s3c/time.c ++ M arch/arm/plat-s3c24xx/include/plat/cpu.h ++ ++v2.6.28-rc8-s3c64xx-r0d3: Jongpill Lee ++ - Remove adc driver on s3c24xx ++ Modified Files: ++ M arch/arm/plat-s3c24xx/Kconfig ++ M arch/arm/plat-s3c24xx/Makefile ++ Deleted Files: ++ D arch/arm/plat-s3c24xx/adc.c ++ ++v2.6.28-rc8-s3c64xx-r0d4: Jinsung Yang ++ - 24 bit logo display support ++ - s3c framebuffer driver naming rule changes ++ ++ Modified files: ++ M drivers/video/cfbimgblt.c ++ M drivers/video/samsung/s3cfb.c ++ M drivers/video/samsung/s3cfb.h ++ M drivers/video/samsung/s3cfb_fimd4x.c ++ M drivers/video/samsung/s3cfb_fimd5x.c ++ M drivers/video/samsung/s3cfb_lte480wv.c ++ M drivers/video/samsung/s3cfb_lts222qv.c ++ M drivers/video/samsung/s3cfb_ltv350qv.c ++ M drivers/video/samsung/s3cfb_spi.c ++ ++v2.6.28-rc8-s3c64xx-r0d5: Jongpill Lee ++ -Support cpu freq on smdk6410 ++ ++ Added Files: ++ A arch/arm/plat-s3c64xx/s3c64xx-cpufreq.carch/arm/plat-s3c64xx/s3c64xx-cpufreq.c ++ Modified Files: ++ M arch/arm/Kconfig ++ M arch/arm/plat-s3c/clock.c ++ M arch/arm/plat-s3c64xx/Makefile ++ ++v2.6.28-rc8-s3c64xx-r0d6: Kyoungil Kim ++ - split plat-s5p64xx, mach-s5p6440 ++ - Support for s5p6440 serial ++ ++ Added Files ++ A arch/arm/configs/smdk6440ramdisk_defconfig ++ A arch/arm/mach-s5p6440/Kconfig ++ A arch/arm/mach-s5p6440/Makefile.boot ++ A arch/arm/mach-s5p6440/cpu.c ++ A arch/arm/mach-s5p6440/dma.c ++ A arch/arm/mach-s5p6440/include/mach/debug-macro.S ++ A arch/arm/mach-s5p6440/include/mach/dma.h ++ A arch/arm/mach-s5p6440/include/mach/entry-macro.S ++ A arch/arm/mach-s5p6440/include/mach/gpio-core.h ++ A arch/arm/mach-s5p6440/include/mach/gpio.h ++ A arch/arm/mach-s5p6440/include/mach/hardware.h ++ A arch/arm/mach-s5p6440/include/mach/idle.h ++ A arch/arm/mach-s5p6440/include/mach/irqs.h ++ A arch/arm/mach-s5p6440/include/mach/map.h ++ A arch/arm/mach-s5p6440/include/mach/memory.h ++ A arch/arm/mach-s5p6440/include/mach/regs-irq.h ++ A arch/arm/mach-s5p6440/include/mach/regs-mem.h ++ A arch/arm/mach-s5p6440/include/mach/system.h ++ A arch/arm/mach-s5p6440/include/mach/tick.h ++ A arch/arm/mach-s5p6440/include/mach/uncompress.h ++ A arch/arm/mach-s5p6440/mach-smdk6440.c ++ A arch/arm/mach-s5p6440/setup-sdhci.c ++ A arch/arm/plat-s5p64xx/Kconfig ++ A arch/arm/plat-s5p64xx/Makefile ++ A arch/arm/plat-s5p64xx/adc.c ++ A arch/arm/plat-s5p64xx/clock.c ++ A arch/arm/plat-s5p64xx/cpu.c ++ A arch/arm/plat-s5p64xx/dev-uart.c ++ A arch/arm/plat-s5p64xx/devs.c ++ A arch/arm/plat-s5p64xx/gpiolib.c ++ A arch/arm/plat-s5p64xx/include/plat/dma.h ++ A arch/arm/plat-s5p64xx/include/plat/gpio-bank-a.h ++ A arch/arm/plat-s5p64xx/include/plat/gpio-bank-b.h ++ A arch/arm/plat-s5p64xx/include/plat/gpio-bank-c.h ++ A arch/arm/plat-s5p64xx/include/plat/gpio-bank-f.h ++ A arch/arm/plat-s5p64xx/include/plat/gpio-bank-g.h ++ A arch/arm/plat-s5p64xx/include/plat/gpio-bank-h.h ++ A arch/arm/plat-s5p64xx/include/plat/gpio-bank-i.h ++ A arch/arm/plat-s5p64xx/include/plat/gpio-bank-j.h ++ A arch/arm/plat-s5p64xx/include/plat/gpio-bank-n.h ++ A arch/arm/plat-s5p64xx/include/plat/gpio-bank-p.h ++ A arch/arm/plat-s5p64xx/include/plat/gpio-bank-r.h ++ A arch/arm/plat-s5p64xx/include/plat/irqs.h ++ A arch/arm/plat-s5p64xx/include/plat/pll.h ++ A arch/arm/plat-s5p64xx/include/plat/regs-clock.h ++ A arch/arm/plat-s5p64xx/include/plat/regs-gpio.h ++ A arch/arm/plat-s5p64xx/include/plat/regs-sys.h ++ A arch/arm/plat-s5p64xx/include/plat/s5p6440.h ++ A arch/arm/plat-s5p64xx/irq-eint.c ++ A arch/arm/plat-s5p64xx/irq.c ++ A arch/arm/plat-s5p64xx/s5p6440-clock.c ++ A arch/arm/plat-s5p64xx/s5p6440-init.c ++ A arch/arm/plat-s5p64xx/setup-i2c0.c ++ A arch/arm/plat-s5p64xx/setup-i2c1.c ++ Modified Files ++ M arch/arm/Kconfig ++ M arch/arm/Makefile ++ M arch/arm/mach-s5p6440/Makefile ++ M arch/arm/mm/Kconfig ++ M arch/arm/plat-s3c/Kconfig ++ M arch/arm/plat-s3c/include/plat/clock.h ++ M arch/arm/plat-s3c/include/plat/cpu.h ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s3c/include/plat/regs-lcd.h ++ M arch/arm/tools/mach-types ++ M drivers/i2c/busses/Kconfig ++ M drivers/input/touchscreen/Kconfig ++ M drivers/mtd/nand/Kconfig ++ M drivers/serial/Kconfig ++ M drivers/video/Kconfig ++ M drivers/video/samsung/Makefile ++ M drivers/video/samsung/s3cfb.h ++ M drivers/video/samsung/s3cfb_spi.c ++ ++v2.6.28-rc8-s3c64xx-r0d7: Ilho Lee ++ - ASYN/SYN mode select added. ++ ++ Modified Files: ++ M arch/arm/plat-s3c64xx/include/plat/regs-clock.h ++ M arch/arm/plat-s3c64xx/s3c6400-clock.c ++ ++v2.6.28-rc8-s3c64xx-r0d8: Kyoungil Kim ++ - Support for FPGA6440 lcd ++ ++ Modified Files: ++ M arch/arm/mach-s5p6440/include/mach/gpio.h ++ M drivers/video/samsung/s3cfb_fimd5x.c ++ M drivers/video/samsung/s3cfb_lts222qv.c ++ M drivers/video/samsung/s3cfb_spi.c ++ ++v2.6.28-rc8-s3c64xx-r0d9: Jongpill Lee ++ - Support APM on SMDK6410 ++ ++ Modified Files: ++ M arch/arm/configs/smdk6410mtd_defconfig ++ M arch/arm/mach-s3c6400/include/mach/regs-irq.h ++ M arch/arm/mach-s3c6410/Makefile ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/Makefile ++ M arch/arm/plat-s3c/include/plat/regs-serial.h ++ M arch/arm/plat-s3c64xx/Makefile ++ M arch/arm/plat-s3c64xx/include/plat/gpio-bank-k.h ++ M arch/arm/plat-s3c64xx/include/plat/gpio-bank-l.h ++ M arch/arm/plat-s3c64xx/include/plat/regs-gpio.h ++ M arch/arm/plat-s3c64xx/irq.c ++ M drivers/video/samsung/s3cfb_fimd4x.c ++ Added Files: ++ A arch/arm/mach-s3c6410/irq.c ++ A arch/arm/mach-s3c6410/pm.c ++ A arch/arm/plat-s3c64xx/include/plat/gpio-bank-m.h ++ A arch/arm/plat-s3c64xx/include/plat/pm.h ++ A arch/arm/plat-s3c64xx/pm.c ++ A arch/arm/plat-s3c64xx/sleep.S ++ ++v2.6.28-rc8-s3c64xx-r0d10: Jongpill Lee ++ - Support RTC on SMDK6410 ++ ++ MOdified Files: ++ M arch/arm/mach-s3c2410/include/mach/map.h ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/include/plat/regs-rtc.h ++ M arch/arm/plat-s3c64xx/devs.c ++ M arch/arm/plat-s3c64xx/include/plat/pm.h ++ M drivers/rtc/Kconfig ++ M drivers/rtc/rtc-s3c.c ++ ++v2.6.28-rc8-s3c64xx-r0d11: Kyoungil Kim ++ - Keypad Driver for SMDK6410 ++ ++ Modified Files: ++ M arch/arm/configs/smdk6410mtd_defconfig ++ M arch/arm/configs/smdk6410nfs_defconfig ++ M arch/arm/configs/smdk6410ramdisk_defconfig ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/gpio-config.c ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s3c64xx/clock.c ++ M arch/arm/plat-s3c64xx/devs.c ++ M arch/arm/plat-s3c64xx/include/plat/gpio-bank-k.h ++ M arch/arm/plat-s3c64xx/include/plat/gpio-bank-l.h ++ M drivers/input/keyboard/Kconfig ++ M drivers/input/keyboard/Makefile ++ M drivers/input/touchscreen/s3c-ts.c ++ Added Files: ++ A arch/arm/plat-s3c64xx/include/plat/regs-keypad.h ++ A drivers/input/keyboard/s3c-keypad.c ++ A drivers/input/keyboard/s3c-keypad.h ++ ++v2.6.28-rc8-s3c64xx-r0d12: Jongpill Lee ++ - Support HS-SPI on SMDK6410 ++ ++ Added Files: ++ A arch/arm/plat-s3c64xx/include/plat/regs-spi.h ++ A drivers/spi/hspi-s3c64xx.c ++ A drivers/spi/hspi-s3c64xx.h ++ A drivers/spi/spi-dev.c ++ A drivers/spi/spi-dev.h ++ ++ Modified Files: ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M drivers/rtc/rtc-s3c.c ++ M drivers/spi/Kconfig ++ M drivers/spi/Makefile ++ ++v2.6.28-rc8-s3c64xx-r0d13: Ilho Lee ++ - Support HS-MMC on SMDK6410 ++ ++v2.6.28-rc8-s3c64xx-r0d14: Jongpill Lee ++ - bug fiex on PM Driver ++ ++ Modified Files: ++ M arch/arm/configs/smdk6410mtd_defconfig ++ M arch/arm/plat-s3c64xx/sleep.S ++ ++v2.6.28-rc8-s3c64xx-r0d15: Kyoungil Kim ++ - Support USB host on SMDK6410 ++ ++ Modifiled Files: ++ M arch/arm/configs/smdk6410mtd_defconfig ++ M arch/arm/configs/smdk6410nfs_defconfig ++ M arch/arm/configs/smdk6410onenand_defconfig ++ M arch/arm/configs/smdk6410ramdisk_defconfig ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/mach-s5p6440/mach-smdk6440.c ++ M arch/arm/plat-s3c/include/plat/partition.h ++ M arch/arm/plat-s3c64xx/devs.c ++ M drivers/usb/Kconfig ++ M drivers/usb/gadget/s3c_udc_otg.c ++ M drivers/usb/host/ohci-hcd.c ++ M drivers/usb/host/ohci-s3c2410.c ++ Added Files: ++ A arch/arm/mach-s3c6400/include/mach/usb-control.h ++ ++v2.6.28-rc8-s3c64xx-r0d16: Jongpill Lee ++ - Support DVS on CPUFREQ Driver ++ ++ Added Files: ++ A arch/arm/plat-s3c64xx/ltc3714.c ++ Modified Files: ++ M arch/arm/plat-s3c/clock.c ++ M arch/arm/plat-s3c64xx/Makefile ++ M arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c ++ ++v2.6.28-rc8-s3c64xx-r0d17: Byungjae Lee ++ - Support Ethernet gadget and RNDIS for SMDK6410 ++ ++ Modifiled Files: ++ M arch/arm/configs/smdk6410mtd_defconfig ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M drivers/usb/gadget/Kconfig ++ M drivers/usb/gadget/epautoconf.c ++ M drivers/usb/gadget/f_rndis.c ++ M drivers/usb/gadget/s3c_udc.h ++ M drivers/usb/gadget/s3c_udc_otg.c ++ M drivers/usb/gadget/u_ether.c ++ Added Files: ++ A drivers/usb/gadget/s3c_udc_otg_xfer_dma.c ++ A drivers/usb/gadget/s3c_udc_otg_xfer_slave.c ++ ++v2.6.28-rc8-s3c64xx-r0d18: Jongpill Lee ++ - Remove warning message ++ ++ Modified Files: ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/mach-s3c6410/pm.c ++ M arch/arm/plat-s3c/clock.c ++ M arch/arm/plat-s3c64xx/clock.c ++ M arch/arm/plat-s3c64xx/include/plat/pm.h ++ M arch/arm/plat-s3c64xx/irq.c ++ M arch/arm/plat-s3c64xx/ltc3714.c ++ M arch/arm/plat-s3c64xx/pm.c ++ M arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c ++ M drivers/rtc/rtc-s3c.c ++ M drivers/spi/hspi-s3c64xx.c ++ ++v2.6.28-rc8-s3c64xx-r0d19: Kyoungil Kim ++ - Support Watchdog on SMDK6410 ++ ++ Modified Files: ++ M arch/arm/configs/smdk6410mtd_defconfig ++ M arch/arm/configs/smdk6410nfs_defconfig ++ M arch/arm/configs/smdk6410onenand_defconfig ++ M arch/arm/configs/smdk6410ramdisk_defconfig ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c64xx/devs.c ++ M drivers/watchdog/Kconfig ++ ++v2.6.28-rc8-s3c64xx-r0d20: Ryu Euiyoul ++ - Support S5M8751 on SMDK6410 ++ ++ Modified Files: ++ M sound/soc/codecs/Kconfig ++ M sound/soc/codecs/Makefile ++ M sound/soc/s3c64xx/Kconfig ++ M sound/soc/s3c64xx/Makefile ++ ++ Added Files: ++ A sound/soc/codecs/s5m8751.c ++ A sound/soc/codecs/s5m8751.h ++ A sound/soc/s3c64xx/smdk6410_s5m8751.c ++ A arch/arm/configs/smdk6410rf_defconfig ++ ++v2.6.28-rc8-s3c64xx-r0d21: SungJun Bae ++ - Support wm8580 on VEGA-L FPGA (Draft) ++ ++ Modified Files: ++ M arch/arm/configs/smdk6440ramdisk_defconfig ++ M arch/arm/mach-s5p6440/dma.c ++ M arch/arm/mach-s5p6440/mach-smdk6440.c ++ M arch/arm/plat-s3c/dma-pl080.c ++ M sound/soc/s3c64xx/Kconfig ++ M sound/soc/s3c64xx/Makefile ++ M sound/soc/s3c64xx/s3c-i2s.h ++ M sound/soc/s3c64xx/s3c-pcm.c ++ M sound/soc/s3c64xx/s3c6410-i2s-v40.c ++ ++ Added Files: ++ A sound/soc/s3c64xx/s5p6440-i2s-v40.c ++ A sound/soc/s3c64xx/smdk6440_wm8580.c ++ ++v2.6.28.6-s3c64xx: Kyoungil Kim ++ ++v2.6.28.6-s3c64xx-r0d0: Kyoungil Kim ++ ++v2.6.28.6-s3c64xx-r0d1: SungJun Bae ++ - Support Post Processor on SMDK6410 ++ ++ Modified Files: ++ M ChangeLog_s3c64xx ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s3c/include/plat/regs-lcd.h ++ M arch/arm/plat-s3c64xx/devs.c ++ M drivers/media/video/Kconfig ++ M drivers/media/video/Makefile ++ ++ Added Files: ++ A arch/arm/plat-s3c/include/plat/regs-pp.h ++ A arch/arm/plat-s3c/include/plat/reserved_mem.h ++ A drivers/media/video/samsung/post/Kconfig ++ A drivers/media/video/samsung/post/Makefile ++ A drivers/media/video/samsung/post/s3c_pp.h ++ A drivers/media/video/samsung/post/s3c_pp_6400.c ++ A drivers/media/video/samsung/post/s3c_pp_common.c ++ A drivers/media/video/samsung/post/s3c_pp_common.h ++ ++v2.6.28.6-s3c64xx-r0d2: SungJun Bae ++ - Support TV encoder,scaler on SMDK6410 ++ ++ Modified Files: ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s3c64xx/devs.c ++ M drivers/media/video/Kconfig ++ M drivers/media/video/Makefile ++ M drivers/media/video/samsung/Kconfig ++ M drivers/media/video/samsung/post/s3c_pp_6400.c ++ M drivers/media/video/v4l2-dev.c ++ M include/media/v4l2-dev.h ++ ++ Added Files: ++ A arch/arm/plat-s3c/include/plat/regs-tvenc.h ++ A arch/arm/plat-s3c/include/plat/regs-tvscaler.h ++ A drivers/media/video/samsung/tv/Kconfig ++ A drivers/media/video/samsung/tv/Makefile ++ A drivers/media/video/samsung/tv/s3c-tvenc.c ++ A drivers/media/video/samsung/tv/s3c-tvenc.h ++ A drivers/media/video/samsung/tv/s3c-tvscaler.c ++ A drivers/media/video/samsung/tv/s3c-tvscaler.h ++v2.6.28.6-s3c64xx-r0d3: Jaeryul Oh ++ - Support JPEG, roator on SMDK6410 ++ ++ Modified Files : ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s3c64xx/devs.c ++ M drivers/media/video/samsung/Kconfig ++ M drivers/media/video/samsung/Makefile ++ ++ Added Files: ++ A drivers/media/video/samsung/jpeg/Kconfig ++ A drivers/media/video/samsung/jpeg/Makefile ++ A drivers/media/video/samsung/jpeg/jpg_conf.h ++ A drivers/media/video/samsung/jpeg/jpg_mem.c ++ A drivers/media/video/samsung/jpeg/jpg_mem.h ++ A drivers/media/video/samsung/jpeg/jpg_misc.c ++ A drivers/media/video/samsung/jpeg/jpg_misc.h ++ A drivers/media/video/samsung/jpeg/jpg_opr.c ++ A drivers/media/video/samsung/jpeg/jpg_opr.h ++ A drivers/media/video/samsung/jpeg/log_msg.c ++ A drivers/media/video/samsung/jpeg/log_msg.h ++ A drivers/media/video/samsung/jpeg/s3c-jpeg.c ++ A drivers/media/video/samsung/jpeg/s3c-jpeg.h ++ A drivers/media/video/samsung/rotator/Kconfig ++ A drivers/media/video/samsung/rotator/Makefile ++ A drivers/media/video/samsung/rotator/regs-rotator.h ++ A drivers/media/video/samsung/rotator/s3c_rotator.c ++ A drivers/media/video/samsung/rotator/s3c_rotator_common.h ++ ++v2.6.28.6-s3c64xx-r0d4: Jinsung Yang ++ - FIMC support for SMDK6410 ++ - Including reserved memory feature with bootmem ++ - All functions have been finished on the planning ++ ++v2.6.28.6-s3c64xx-r0d5: SungJun Bae ++ - bootmem applied to post and tv. ++ M drivers/media/video/samsung/post/s3c_pp_6400.c ++ M drivers/media/video/samsung/tv/s3c-tvscaler.h ++ ++v2.6.28.6-s3c64xx-r0d6: PyoungJae Jung, Jiun Yu ++ - MFC support for SMDK6410 ++ - It support bootmem for large buffer memory ++ - Changed coding style to linux kernel coding style ++ - Bug fixed in Hybrid DiVX encoding problem ++ ++ Modified Files: ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s3c64xx/devs.c ++ M arch/arm/plat-s3c64xx/include/plat/media.h ++ M drivers/media/video/samsung/Kconfig ++ M drivers/media/video/samsung/Makefile ++ ++ Added Files: ++ A arch/arm/plat-s3c64xx/include/plat/regs-mfc.h ++ A drivers/media/video/samsung/mfc/Kconfig ++ A drivers/media/video/samsung/mfc/Makefile ++ A drivers/media/video/samsung/mfc/prism_s.h ++ A drivers/media/video/samsung/mfc/prism_s_v137.c ++ A drivers/media/video/samsung/mfc/s3c_mfc.c ++ A drivers/media/video/samsung/mfc/s3c_mfc.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_base.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_bitproc_buf.c ++ A drivers/media/video/samsung/mfc/s3c_mfc_bitproc_buf.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_config.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_databuf.c ++ A drivers/media/video/samsung/mfc/s3c_mfc_databuf.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_hw_init.c ++ A drivers/media/video/samsung/mfc/s3c_mfc_hw_init.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_inst_pool.c ++ A drivers/media/video/samsung/mfc/s3c_mfc_inst_pool.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_instance.c ++ A drivers/media/video/samsung/mfc/s3c_mfc_instance.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_intr_noti.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_params.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_set_config.c ++ A drivers/media/video/samsung/mfc/s3c_mfc_sfr.c ++ A drivers/media/video/samsung/mfc/s3c_mfc_sfr.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_types.h ++ A drivers/media/video/samsung/mfc/s3c_mfc_yuv_buf_manager.c ++ A drivers/media/video/samsung/mfc/s3c_mfc_yuv_buf_manager.h ++ ++v2.6.28.6-s3c64xx-r0d7: Kyoungil Kim ++ - Just Prevent tag for SMDK6410 ++ ++v2.6.28.6-s3c64xx-r0d8: Jaeryul Oh ++ - Fixed Bug in case of dynamic fps change of MPEG4 encoding ++ ++ Modified Files: ++ M drivers/media/video/samsung/mfc/s3c_mfc_instance.h ++ M drivers/media/video/samsung/mfc/s3c_mfc_instance.c ++ ++v2.6.28.6-s3c64xx-r0d9: Jonghun Han ++ - S3C6410 FIMG-2D driver support ++ ++ Added Files: ++ drivers/media/video/samsung/g2d/Kconfig ++ drivers/media/video/samsung/g2d/Makefile ++ drivers/media/video/samsung/g2d/s3c_fimg2d2x.c ++ drivers/media/video/samsung/g2d/s3c_fimg2d2x.h ++ arch/arm/plat-s3c/include/plat/regs-g2d.h ++ ++ Modified Files: ++ arch/arm/configs/smdk6410mtd_defconfig ++ arch/arm/configs/smdk6410nfs_defconfig ++ arch/arm/configs/smdk6410onenand_defconfig ++ arch/arm/configs/smdk6410ramdisk_defconfig ++ arch/arm/mach-s3c6400/include/mach/map.h ++ arch/arm/mach-s3c6410/mach-smdk6410.c ++ arch/arm/plat-s3c/include/plat/devs.h ++ arch/arm/plat-s3c64xx/devs.c ++ drivers/media/video/samsung/Kconfig ++ drivers/media/video/samsung/Makefile ++ drivers/video/samsung/s3cfb.c ++ drivers/video/samsung/s3cfb_fimd4x.c ++ ++v2.6.28.6-s3c64xx-r1: Jonghun Han ++ - Official Release (09.03.06) ++ ++v2.6.28.6-s3c64xx-r1d0: Kyoungil Kim ++ ++v2.6.28.6-s3c64xx-r1d1 : Byungjae Lee ++ - implemented s3c6410 OTG host role for Mass storage only ++ ++ Modified Files: ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s3c64xx/devs.c ++ M drivers/usb/Makefile ++ M drivers/usb/host/Kconfig ++ M drivers/usb/host/Makefile ++ ++ Added Files: ++ A drivers/usb/host/s3c-otg/* ++ ++v2.6.28.6-s3c64xx-r1d2 : Byungjae Lee ++ - implemented s3c6410 OTG host role for HID(Keyboard, Mouse) ++ and Card Reader ++ ++ Modified Files: ++ M drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.c ++ M drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.c ++ M drivers/usb/host/s3c-otg/s3c-otg-hcdi-kal.h ++ M drivers/usb/host/s3c-otg/s3c-otg-scheduler-ischeduler.c ++ M drivers/usb/host/s3c-otg/s3c-otg-scheduler-scheduler.h ++ M drivers/usb/host/s3c-otg/s3c-otg-transfer-common.c ++ M drivers/usb/host/s3c-otg/s3c-otg-transferchecker-common.c ++ ++v2.6.28.6-s3c64xx-r1d3 : Jongpill Lee ++ - defect is fixed on cpufreq driver ++ ++ Modified Files: ++ M arch/arm/plat-s3c64xx/clock.c ++ ++v2.6.28.6-s3c64xx-r1d4 : Jongpill Lee ++ - defect is fixed on pm ++ ++ MOdified Fils: ++ M arch/arm/plat-s3c64xx/pm.c ++ ++v2.6.28.6-s3c64xx-r1d5: Kyoungil Kim ++ - Just Second Prevent tag for SMDK6410 ++ ++v2.6.28.6-s3c64xx-r1d6 : Jonghun Han ++ - update S3C6410 FIMG-2D driver ++ ++ Modified Fils: ++ M arch/arm/plat-s3c/include/plat/regs-g2d.h ++ M drivers/media/video/samsung/g2d/s3c_fimg2d2x.c ++ ++v2.6.28.6-s3c64xx-r2: Kyoungil Kim ++ - Official Release (09.03.09) ++ ++v2.6.28.6-s3c64xx-r2d0: Kyoungil Kim ++ ++v2.6.28.6-s3c64xx-r2d1: Jaeryul Oh ++ - Fixed Bug in case of rotator function of MFC ++ ++ Modified Files: ++ M drivers/media/video/samsung/mfc/s3c_mfc_instance.c ++ ++v2.6.28.6-s3c64xx-r2d2: Jonghun Han ++ - S3C6410 FIMG-3D driver support ++ ++ Modified Files: ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s3c64xx/devs.c ++ M drivers/char/s3c_mem.c ++ M drivers/media/video/samsung/Kconfig ++ M drivers/media/video/samsung/Makefile ++ M drivers/media/video/samsung/g2d/s3c_fimg2d2x.c ++ ++ Added Files: ++ A drivers/media/video/samsung/g3d/Kconfig ++ A drivers/media/video/samsung/g3d/Makefile ++ A drivers/media/video/samsung/g3d/s3c_fimg3d.c ++ A drivers/media/video/samsung/g3d/s3c_fimg3d.h ++ ++v2.6.28.6-s3c64xx-r2d3: Jonghun Han ++ - S5PC100 FIMG-2D driver support ++ ++ Modified Files: ++ M drivers/media/video/samsung/g2d/Kconfig ++ M drivers/media/video/samsung/g2d/s3c_fimg2d2x.c ++ ++v2.6.28.6-s3c64xx-r3: Kyoungil Kim ++ - Official Release (09.03.13) ++ ++v2.6.28.6-s3c64xx-r3d0: Kyoungil Kim ++ ++v2.6.28.6-s3c64xx-r3d1: Byungae Lee ++ - Support SMDK6410 USB Serial Gadget (with CDC ACM) ++ ++ Modified Files: ++ M arch/arm/plat-s3c/include/plat/regs-otg.h ++ M drivers/usb/gadget/s3c_udc_otg.c ++ M drivers/usb/gadget/s3c_udc_otg_xfer_dma.c ++ M drivers/usb/gadget/s3c_udc_otg_xfer_slave.c ++ ++v2.6.28.6-s3c64xx-r3d2: Byungae Lee ++ - Removed warning on the debug message for the USB Gadget ++ ++ Modified Files: ++ M drivers/usb/gadget/s3c_udc_otg.c ++ M drivers/usb/gadget/s3c_udc_otg_xfer_dma.c ++ ++v2.6.28.6-s3c64xx-r3d3: SungJun Bae ++ - Support CMM driver. ++ ++ Added Files: ++ A drivers/media/video/samsung/cmm/CMMMisc.c ++ A drivers/media/video/samsung/cmm/CMMMisc.h ++ A drivers/media/video/samsung/cmm/Kconfig ++ A drivers/media/video/samsung/cmm/LogMsg.c ++ A drivers/media/video/samsung/cmm/LogMsg.h ++ A drivers/media/video/samsung/cmm/Makefile ++ A drivers/media/video/samsung/cmm/s3c-cmm.c ++ A drivers/media/video/samsung/cmm/s3c-cmm.h ++ ++ Modified Files: ++ M drivers/media/video/samsung/Kconfig ++ M drivers/media/video/samsung/Makefile ++ ++ ++v2.6.28.6-s3c64xx-r4: Jonghun Han ++ - Official Release (09.03.24) ++ ++v2.6.28.6-s3c64xx-r4d0: Jonghun Han ++ ++v2.6.28.6-s3c64xx-r4d1: Kyoungil Kim ++ - The last tag for s3c64xx branch(09.03.24) ++ ++rel-0-0-0 : Kwanghyun La (Nov.10.2008) ++ It's not fixed version , just only initial copy version for ++ estimation. ++ ++previous samsung-ap-2.6 repository ChangeLog_s5pc1xx for s5pc1xx branch ++----------------------------------------------------------------------- ++dev-0-0-1 : Ilho Lee ++dev-0-0-2 : Ilho Lee ++ Touchscreen D/D added, but Ethernet D/D is being adding. ++ ++dev-0-0-3 : Jongpill Lee ++ Support ADC driver and merge adc-s3c64xx.c and adc-s3c24xx.c file ++ ++ Removed Files: ++ R A arch/arm/plat-s3c64xx/adc-s3c64xx.c ++ ++ Added Files: ++ A arch/arm/plat-s3c/adc.c ++ ++ Modified Files: ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/Kconfig ++ M arch/arm/plat-s3c/Makefile ++ M arch/arm/plat-s3c/include/plat/adc.h ++ M drivers/char/Kconfig ++ ++dev-0-0-4 : Jongpill Lee ++ Bug fixed on ADC driver ++ ++ Modified Files: ++ M arch/arm/plat-s3c/adc.c ++ ++dev-0-0-5 : Ilho Lee ++ SMC9115 ethernet D/D is working(small_root only) ++ ++dev-0-0-6: Jinsung Yang ++ - NAND driver support ++ ++ Added files: ++ A arch/arm/configs/smdk6410mtd_defconfig ++ A arch/arm/plat-s3c/include/plat/partition.h ++ A drivers/mtd/nand/s3c_nand.c ++ ++ Modified files: ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c/Kconfig ++ M arch/arm/plat-s3c/include/plat/nand.h ++ M arch/arm/plat-s3c/include/plat/regs-nand.h ++ M arch/arm/plat-s3c64xx/devs.c ++ M drivers/mtd/nand/Kconfig ++ M drivers/mtd/nand/Makefile ++ ++dev-0-0-7: Sungjun Bae ++ - I2S WM8580, I2SWM8990 Complete. ++ ++ Modified Files: ++ M arch/arm/configs/smdk6410mtd_defconfig arch/arm/configs/smdk6410nfs_defconfig ++ M arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h ++ M arch/arm/plat-s3c64xx/include/plat/regs-clock.h include/sound/soc.h ++ M sound/soc/soc-core.c sound/soc/codecs/wm8580.c sound/soc/codecs/wm8990.c ++ ++dev-0-0-8: Sungjun Bae ++ - DMA File Structure was changed. ++ ++ Modified Files: ++ M arch/arm/plat-s3c/Makefile ++ M arch/arm/plat-s3c/include/mach/s3c-dma.h ++ M arch/arm/plat-s3c64xx/Makefile ++ Added Files: ++ A arch/arm/plat-s3c/dma-pl080.c ++ Removed Files: ++ R arch/arm/plat-s3c64xx/dma-pl080.c ++ ++dev-0-0-9: Ilho Lee ++ - PL330 DMA D/D file added ++ ++ Modified Files: ++ M arch/arm/plat-s3c/Makefile ++ M arch/arm/plat-s3c/Kconfig ++ ++ Added Files: ++ A arch/arm/plat-s3c/dma-pl330.c ++ A arch/arm/plat-s3c/dma-pl330-microcode.c ++ ++ ++dev-0-0-10: eyryu ++ - Add SMDKC100 initial. ++ ++dev-0-0-11: Ilho Lee ++ - DMA definition files changed ++ ++ Modified Files: ++ M arch/arm/mach-s3c6410/dma.c ++ M arch/arm/mach-s5pc100/dma.c ++ ++dev-0-0-12: Jinsung Yang ++ - gpiolib support for s5pc1xx architecture ++ ++ Modified files: ++ M arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h ++ M arch/arm/mach-s5pc100/include/mach/gpio.h ++ M arch/arm/plat-s3c/gpio-config.c ++ M arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h ++ ++ Added files: ++ A arch/arm/plat-s5pc1xx/gpiolib.c ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-a0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-a1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-b.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-c.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-d.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-e0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-e1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f2.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f3.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g2.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g3.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h2.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h3.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-i.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j2.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j3.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j4.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k0.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k1.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k2.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k3.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp00.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp01.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp02.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp03.h ++ A arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp04.h ++ ++dev-0-0-13: eyryu ++ - Add SMDKC100 clock & serial ++ ++dev-0-0-14: Ilho Lee ++ - ADC D/D added ++ ++ Added Files: ++ A arch/arm/plat-s3c24xx/adc.c ++ A arch/arm/plat-s3c64xx/adc.c ++ ++dev-0-0-15: eyryu ++ - Support SMDKC100 UART driver ++ - Add SMDKC100 clock & serial ++ ++rel-1-0-0: Kyoungil Kim ++ - Official Release (08.11.27) ++ ++dev-1-0-0: Kyoungil Kim ++ ++dev-1-0-1: Ilho Lee ++ - CPU idle added ++ ++ Added Files: ++ A arch/arm/mach-s3c6400/idle.h ++ A arch/arm/mach-s5pc100/idle.h ++ ++ Modified Files: ++ M arch/arm/mach-s3c6410/cpu.c ++ M arch/arm/mach-s5pc100/cpu.c ++ ++dev-1-0-2: Ilho Lee ++ - S3C24XX -> S3C changed in the S3C DMA D/D. ++ ++ Modified Files: ++ M arch/arm/mach-s3c6410/dma.c ++ M arch/arm/mach-s5pc100/dma.c ++ M arch/arm/plat-s3c/dma-pl080.c ++ M arch/arm/plat-s3c/dma-pl330.c ++ M arch/arm/plat-s3c/include/plat/s3c-dma.h ++ ++dev-1-0-3: Ilho Lee ++ - PL330 DMA D/D is adding.. ++ ++ Modified Files: ++ M arch/arm/plat-s3c/dma-pl330.c ++ M arch/arm/plat-s3c/dma-pl330-mcode.h ++ M arch/arm/plat-s3c/include/mach/s3c-dma.h ++ ++dev-1-0-4: Byungjae Lee ++ - Support File Storage Gadget for SMDK6410 HS USB OTG ++ ++ Modified Files: ++ M arch/arm/mach-s3c6400/include/mach/map.h ++ M arch/arm/mach-s3c6410/cpu.c ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/plat-s3c64xx/devs.c ++ M arch/arm/plat-s3c64xx/include/plat/regs-clock.h ++ M drivers/usb/gadget/Kconfig ++ M drivers/usb/gadget/Makefile ++ M drivers/usb/gadget/epautoconf.c ++ M drivers/usb/gadget/gadget_chips.h ++ ++ Added Files: ++ A arch/arm/plat-s3c/include/plat/regs-otg.h ++ A drivers/usb/gadget/s3c_udc.h ++ A drivers/usb/gadget/s3c_udc_otg.c ++ ++dev-1-0-5: Ilho Lee ++ - S3C touchscreen D/D changed. ++ ++ Modified Files: ++ M drivers/input/touchscreen/s3c-ts.c ++ ++dev-1-0-6: Jinsung Yang ++ - Clock system support for S5PC100 ++ ++ Modified files: ++ M arch/arm/plat-s3c/clock.c ++ M arch/arm/plat-s3c/include/plat/clock.h ++ M arch/arm/plat-s5pc1xx/clock.c ++ M arch/arm/plat-s5pc1xx/s5pc100-clock.c ++ M arch/arm/plat-s5pc1xx/include/plat/pll.h ++ M arch/arm/plat-s5pc1xx/include/plat/regs-clock.h ++ ++dev-1-0-7: Jinsung Yang ++ - LCD (LTE480WV) support for SMDKC100 ++ ++ Modified files: ++ drivers/video/samsung/s5pfb_fimd5x.c ++ ++dev-1-0-8: Byungjae Lee ++ - Masked HCLK for USB OTG at register clocks ++ ++ Modified files: ++ M arch/arm/plat-s3c64xx/clock.c ++ M drivers/usb/gadget/s3c_udc_otg.c ++ ++dev-1-0-9: Ilho Lee ++ - Ext-interrupts handlers added. ++ ++ Added Files: ++ A arch/arm/plat-s5pc1xx/irq-eint.c ++ ++dev-1-0-10: Ilho Lee ++ - SMC9115 ethernet(100Mbps) D/D ported. ++ ++ Added Files: ++ A arch/arm/plat-s5pc1xx/irq-eint.c ++ ++dev-1-0-11: Ilho Lee ++ - dev-adc.c deleted. ++ ++ Deleted Files: ++ D arch/arm/plat-s3c/dev-adc.c ++ ++rel-1-0-1: Kyoungil Kim ++ - Git Release (08.12.09) ++ ++v2.6.28-rc7-s5pc1xx-r0d0: Kyoungil Kim ++ - s5pc1xx rc7 initial git tag ++ ++v2.6.28-rc7-s5pc1xx-r0d1: Ilho Lee ++ - PL330 DMA D/D changed. ++ ++ Modified files: ++ M arch/arm/plat-s3c/dma-pl330.c ++ M arch/arm/plat-s3c/dma-pl330-mcode.h ++ ++v2.6.28-rc7-s5pc1xx-r0d2: Jongpill Lee ++ - System Timer support on SMDKC100 ++ ++ Added Files: ++ A arch/arm/plat-s5pc1xx/s5pc1xx-time.c ++ ++v2.6.28-rc7-s5pc1xx-r0d3: Jongpill Lee ++ - System Timer bug fixed ++ ++ Modified Files: ++ M ChangeLog_s5pc1xx ++ M arch/arm/mach-s5pc100/cpu.c ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/include/mach/tick.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s3c/Makefile ++ M arch/arm/plat-s3c/include/plat/map-base.h ++ M arch/arm/plat-s5pc1xx/Makefile ++ M arch/arm/plat-s5pc1xx/include/plat/regs-sys-timer.h ++ ++v2.6.28-rc8-s5pc1xx: Kyoungil Kim ++ - s5pc1xx rc8 patch ++ ++v2.6.28-rc8-s5pc1xx-r0d0: Kyoungil Kim ++ ++v2.6.28-rc8-s5pc1xx-r0d1: Abhilash Kesavan ++ - S5PC100 NAND driver support ++ ++ Added Files: ++ A arch/arm/configs/smdkc100mtd_defconfig ++ ++ Modified Files: ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s3c/Kconfig ++ M arch/arm/plat-s3c/include/plat/partition.h ++ M arch/arm/plat-s5pc1xx/devs.c ++ M drivers/mtd/nand/Kconfig ++ M drivers/mtd/nand/s3c_nand.c ++ ++v2.6.28-rc8-s5pc1xx-r0d2: Jinsung Yang ++ - Fix for wrong comments ++ ++v2.6.28-rc8-s5pc1xx-r0d3: Jinsung Yang ++ - Merge from s3c64xx branch ++ ++v2.6.28-rc8-s5pc1xx-r0d4: Abhilash Kesavan ++ - Touch-up for Nand ++ ++ Modified Files: ++ M arch/arm/configs/smdkc100mtd_defconfig ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ ++ ++v2.6.28-rc8-s5pc1xx-r0d5: Abhilash Kesavan ++ - Support for HS-MMC and USB ++ ++ Added Files: ++ A arch/arm/mach-s5pc100/include/mach/usb-control.h ++ A arch/arm/mach-s5pc100/setup-sdhci.c ++ ++ Modified Files: ++ M arch/arm/configs/smdkc100mtd_defconfig ++ M arch/arm/configs/smdkc100nfs_defconfig ++ M arch/arm/mach-s5pc100/Kconfig ++ M arch/arm/mach-s5pc100/Makefile ++ M arch/arm/mach-s5pc100/cpu.c ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s3c/include/plat/sdhci.h ++ M arch/arm/plat-s5pc1xx/devs.c ++ M arch/arm/plat-s5pc1xx/include/plat/regs-clock.h ++ M arch/arm/plat-s5pc1xx/include/plat/regs-sys.h ++ M drivers/mmc/host/Kconfig ++ M drivers/mmc/host/sdhci-s3c.c ++ M drivers/usb/Kconfig ++ M drivers/usb/gadget/Kconfig ++ M drivers/usb/gadget/f_rndis.c ++ M drivers/usb/gadget/s3c_udc_otg.c ++ M drivers/usb/host/ohci-hcd.c ++ M drivers/usb/host/ohci-s3c2410.c ++ ++v2.6.28-rc8-s5pc1xx-r0d6: Ilho Lee ++ - Touchscreen D/D got enabled and PL330 S&G DMA operations supported. ++ ++ Modified Files: ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s3c/dma-pl330.c ++ ++v2.6.28-rc8-s5pc1xx-r0d7: Abhilash Kesavan ++ - Support for HS-MMC for S5PC1XX (Completed) ++ ++ Added Files: ++ A drivers/mmc/host/s3c-hsmmc.c ++ A drivers/mmc/host/s3c-hsmmc.h ++ A arch/arm/plat-s5pc1xx/include/plat/regs-hsmmc.h ++ ++ Deleted Files: ++ D arch/arm/mach-s5pc100/setup-sdhci.c ++ ++ Modified Files: ++ M arch/arm/configs/smdkc100mtd_defconfig ++ M arch/arm/configs/smdkc100nfs_defconfig ++ M arch/arm/mach-s5pc100/Kconfig ++ M arch/arm/mach-s5pc100/Makefile ++ M arch/arm/mach-s5pc100/cpu.c ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s5pc1xx/devs.c ++ M drivers/mmc/host/Kconfig ++ M drivers/mmc/host/Makefile ++ ++v2.6.28-rc8-s5pc1xx-r0d8: Jongpill Lee ++ - Bug fixed on clock ++ ++ Modified Files: ++ M arch/arm/plat-s3c/clock.c ++ ++v2.6.28-rc8-s5pc1xx-r0d9: Abhilash Kesavan ++ - Support for ADC and PWM for S5PC100 ++ ++ Added Files: ++ A arch/arm/plat-s5pc1xx/adc.c ++ A arch/arm/plat-s5pc1xx/pwm-s5pc100.c ++ A arch/arm/plat-s5pc1xx/pwm-s5pc100.h ++ ++ Modified Files: ++ M arch/arm/configs/smdkc100mtd_defconfig ++ M arch/arm/configs/smdkc100nfs_defconfig ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s3c/Kconfig ++ M arch/arm/plat-s3c/include/plat/regs-timer.h ++ M arch/arm/plat-s5pc1xx/Kconfig ++ M arch/arm/plat-s5pc1xx/Makefile ++ M drivers/mmc/host/s3c-hsmmc.c ++ M drivers/video/samsung/s3cfb.h ++ M drivers/video/samsung/s3cfb_fimd5x.c ++ ++v2.6.28-rc8-s5pc1xx-r1: Kyoungil Kim ++ - Internal Release(09.01.12) ++ ++v2.6.28-rc8-s5pc1xx-v1: Kyoungil Kim ++ - Official Release(09.01.12) ++ ++v2.6.28-rc8-s5pc1xx-r1d0: Kyoungil Kim ++ ++v2.6.28-rc8-s5pc1xx-r1d1: JongPill Lee ++ - Support IDLE Function on S5PC100 ++ ++ Added Files: ++ A arch/arm/plat-s5pc1xx/include/plat/regs-power.h ++ ++ Modified Files: ++ M arch/arm/mach-s5pc100/cpu.c ++ M arch/arm/mach-s5pc100/include/mach/system.h ++ ++v2.6.28-rc8-s5pc1xx-r1d2: Abhilash Kesavan ++ - Support OneNand on S5PC100 (I) ++ ++ Added Files: ++ A arch/arm/plat-s3c/include/plat/regs-onenand.h ++ ++ Modified Files: ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s3c/include/plat/partition.h ++ M drivers/mtd/onenand/Makefile ++ M drivers/mtd/onenand/onenand_bbt.c ++ M drivers/mtd/onenand/s3c_onenand.c ++ M drivers/mtd/onenand/s3c_onenand.h ++ ++v2.6.28-rc8-s5pc1xx-r1d3: Kyoungil Kim ++ - Support Keypad on S5PC100 ++ ++ Modified Files: ++ M arch/arm/configs/smdkc100_defconfig ++ M arch/arm/configs/smdkc100mtd_defconfig ++ M arch/arm/configs/smdkc100nfs_defconfig ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s5pc1xx/clock.c ++ M arch/arm/plat-s5pc1xx/devs.c ++ M drivers/input/keyboard/Kconfig ++ M drivers/input/keyboard/s3c-keypad.h ++ ++v2.6.28-rc8-s5pc1xx-r1d4: Abhilash Kesavan ++ - Support HS-SPI on S5PC100 ++ ++ Added Files: ++ A arch/arm/plat-s3c/include/plat/regs-spi.h ++ A drivers/spi/hspi-s3c.c ++ A drivers/spi/hspi-s3c.h ++ A drivers/spi/spi-dev.c ++ A drivers/spi/spi-dev.h ++ ++ Modified Files: ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s5pc1xx/devs.c ++ M drivers/spi/Kconfig ++ M drivers/spi/Makefile ++ ++v2.6.28-rc8-s5pc1xx-r1d5: Jongpill Lee ++ - Support APM on S5PC100 ++ ++ Added Files: ++ A arch/arm/plat-s5pc1xx/include/plat/pm.h ++ A arch/arm/plat-s5pc1xx/pm.c ++ A arch/arm/mach-s5pc100/pm.c ++ A arch/arm/plat-s5pc1xx/sleep.S ++ ++ Modified Files: ++ M arch/arm/mach-s5pc100/Makefile ++ M arch/arm/mach-s5pc100/include/mach/regs-irq.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s5pc1xx/Makefile ++ M arch/arm/plat-s5pc1xx/include/plat/regs-power.h ++ M arch/arm/plat-s5pc1xx/s5pc100-clock.c ++ M drivers/serial/s5pc100.c ++ M drivers/serial/samsung.c ++ M drivers/serial/samsung.h ++ M drivers/video/samsung/s3cfb_fimd5x.c ++ ++v2.6.28-rc8-s5pc1xx-r1d6: Jongpill Lee ++ - Support RTC Wakeup from Sleep mode ++ ++ Modified Files: ++ M arch/arm/plat-s5pc1xx/pm.c ++ ++v2.6.28-rc8-s5pc1xx-r1d7: PyoungJae Jung/Jiun Yu ++ - Support MFC driver ++ ++ Modified Files: ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s5pc1xx/devs.c ++ ++v2.6.28-rc8-s5pc1xx-r2: Kyoungil Kim ++ - Official Release(09.01.23) ++ ++v2.6.28-rc8-s5pc1xx-r2d0: Kyoungil Kim ++ ++v2.6.28-rc8-s5pc1xx-r2d1: Byungjae Lee ++ - Support CDC Ethernet and RNDIS ++ - for SMDKc100 UBS OTG Deive role on DMA mode ++ ++ Modified Files: ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s3c/include/plat/regs-otg.h ++ M drivers/usb/gadget/Kconfig ++ M drivers/usb/gadget/epautoconf.c ++ M drivers/usb/gadget/s3c_udc.h ++ M drivers/usb/gadget/s3c_udc_otg.c ++ M drivers/usb/gadget/u_ether.c ++ ++ Added Files: ++ A drivers/usb/gadget/s3c_udc_otg_xfer_dma.c ++ A drivers/usb/gadget/s3c_udc_otg_xfer_slave.c ++ ++ ++v2.6.28-rc8-s5pc1xx-r2d2: Jinsung Yang ++ - S5PC100 FIMC Driver ++ - Compilable version ++ ++ Modified files: ++ M drivers/media/video/Kconfig ++ M drivers/media/video/Makefile ++ M include/linux/i2c-id.h ++ ++ Added files: ++ A arch/arm/plat-s5pc1xx/include/plat/fimc.h ++ A arch/arm/plat-s5pc1xx/include/plat/regs-fimc.h ++ A drivers/media/video/samsung/Kconfig ++ A drivers/media/video/samsung/Makefile ++ A drivers/media/video/samsung/s3c_fimc.h ++ A drivers/media/video/samsung/s3c_fimc4x_regs.c ++ A drivers/media/video/samsung/s3c_fimc_cfg.c ++ A drivers/media/video/samsung/s3c_fimc_core.c ++ A drivers/media/video/samsung/s3c_fimc_v4l2.c ++ A drivers/media/video/samsung/s5k4ba.c ++ A drivers/media/video/samsung/s5k4ba.h ++ ++v2.6.28-rc8-s5pc1xx-r2d3: Jinsung Yang ++ - S5PC100 FIMC device setup support ++ ++ Modified files: ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s5pc1xx/Kconfig ++ M arch/arm/plat-s5pc1xx/Makefile ++ ++ Added files: ++ A arch/arm/plat-s5pc1xx/dev-fimc0.c ++ A arch/arm/plat-s5pc1xx/dev-fimc1.c ++ A arch/arm/plat-s5pc1xx/dev-fimc2.c ++ A arch/arm/plat-s5pc1xx/setup-fimc0.c ++ A arch/arm/plat-s5pc1xx/setup-fimc1.c ++ A arch/arm/plat-s5pc1xx/setup-fimc2.c ++ ++v2.6.28-rc8-s5pc1xx-r2d4: Kyoungil Kim ++ - modified otg_phy_init proto type ++ ++ Modified files: ++ M drivers/usb/gadget/s3c_udc_otg.c ++ ++v2.6.28-rc8-s5pc1xx-r2d5: Hatim Ali ++ - S5PC100 Watchdog Timer support ++ ++ Modified files: ++ M arch/arm/configs/smdkc100nfs_defconfig ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s5pc1xx/devs.c ++ M drivers/watchdog/Kconfig ++ ++v2.6.28-rc8-s5pc1xx-r2d6: Abhilash Kesavan ++ - S5PC100 AC97 WM9713 support ++ ++ Modified files: ++ M arch/arm/mach-s5pc100/dma.c ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s5pc1xx/devs.c ++ M sound/soc/codecs/wm9713.c ++ M sound/soc/s5pc1xx/Kconfig ++ M sound/soc/s5pc1xx/Makefile ++ ++ Added Files: ++ A sound/soc/s5pc1xx/s5pc1xx-ac97.c ++ A sound/soc/s5pc1xx/s5pc1xx-ac97.h ++ A sound/soc/s5pc1xx/smdkc100_wm9713.c ++ ++v2.6.28-rc8-s5pc1xx-r2d7: Jinsung Yang ++ - S5PC100 FIMC driver ++ - Camera input and memory output support ++ - Both camera channels (A and B) support ++ - Preview and capture related functionalities support ++ - S5K3BA and S5K4BA module support ++ ++v2.6.28-rc8-s5pc1xx-r2d8: Hatim Ali ++ - S5PC100 Notification LED support ++ ++ Modified files: ++ M arch/arm/Kconfig ++ M arch/arm/mach-s5pc100/Makefile ++ ++ Added Files: ++ A arch/arm/mach-s5pc100/leds-s5pc100.c ++ A arch/arm/mach-s5pc100/leds.c ++ A arch/arm/mach-s5pc100/leds.h ++ ++v2.6.28-rc8-s5pc1xx-r2d9: Abhilash Kesavan ++ - Enabled LCD/OSD Support for S5PC100 ++ ++ Modified files: ++ M arch/arm/plat-s5pc1xx/devs.c ++ M drivers/video/samsung/s3cfb.h ++ M drivers/video/samsung/s3cfb_spi.c ++ ++v2.6.28-rc8-s5pc1xx-r2d10: Jinsung Yang ++ - S5PC100 FIMC driver ++ - Alpha Release ++ - Camera input support ++ - Memory input support ++ - Memory output support ++ - LCD FIFO output support ++ - Both camera channels (A and B) support ++ - Preview and capture related functionalities support ++ - S5K3BA and S5K4BA module support ++ ++v2.6.28.6-s5pc1xx: Kyoungil Kim ++ ++v2.6.28.6-s5pc1xx-r0d0: Kyoungil Kim ++ ++v2.6.28.6-s5pc1xx-r0d1: Abhilash Kesavan ++ - Pre-Beta Version ++ ++v2.6.28.6-s5pc1xx-r0d2: Jinsung Yang ++ - FIMC support for SMDKC100 ++ - Including reserved memory feature with bootmem ++ - All functions have been finished on the planning except for 'Input Rotator' with LCD FIFO Output ++ ++ ++v2.6.28.6-s5pc1xx-r0d3: Abhilash Kesavan ++ - IrDA support for S5PC100 ++ ++ Modified files: ++ M drivers/net/irda/s3c-sir.c ++ M include/net/irda/irda_device.h ++ ++v2.6.28.6-s5pc1xx-r0d4: Jae-Cheol Lee ++ - Support CPUFREQ for SMDKC100 ++ - DFS is only enabled, not DVS. ++ ++ Modified files: ++ M arch/arm/plat-s5pc1xx/s5pc100-clock.c ++ M arch/arm/Kconfig ++ M arch/arm/plat-s5pc1xx/Makefile ++ M arch/arm/plat-s3c/clock.c ++ ++ Added files: ++ A arch/arm/plat-s5pc1xx/s5pc1xx-cpufreq.c ++ A arch/arm/plat-s5pc1xx/changediv.S ++ A arch/arm/plat-s5pc1xx/ltc3714.c ++ ++v2.6.28.6-s5pc1xx-r0d5: Kukjin Kim ++ - System Timer Modified for EVT1 ++ ++ Modified files: ++ M arch/arm/plat-s5pc1xx/include/plat/regs-sys-timer.h ++ M arch/arm/plat-s5pc1xx/s5pc1xx-time.c ++ ++v2.6.28.6-s5pc1xx-r0d6: Jonghun Han ++ - S5PC100 FIMG-2D driver support ++ Modified files: ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s3c/include/plat/regs-g2d.h ++ M arch/arm/plat-s5pc1xx/devs.c ++ M drivers/media/video/samsung/g2d/Kconfig ++ M drivers/media/video/samsung/g2d/s3c_fimg2d2x.c ++ ++v2.6.28.6-s5pc1xx-r0d7: Jae-Cheol Lee ++ - Support SMDKC100 EVT1 POP type (Onenand+mDDR+OneDRAM) ++ Modified files: ++ M arch/arm/configs/smdkc100onenand_defconfig ++ M arch/arm/plat-s5pc1xx/cpu.c ++ M arch/arm/plat-s5pc1xx/s5pc100-clock.c ++ ++v2.6.28.6-s5pc1xx-r0d8: PyoungJae Jung/JiUn Yu ++ - Support MFC (FIMV) for s5pc100 ++ - MFC driver is Alpha version ++ - remove CMM support and support bootmem memory secure way ++ - change directory name to separate to S3C6410 MFC driver ++ ++ Added files: ++ A drivers/media/video/samsung/mfc40/command_control_fw.c ++ A drivers/media/video/samsung/mfc40/s3c_mfc_errorno.h ++ A drivers/media/video/samsung/mfc40/h263_dec_fw.c ++ A drivers/media/video/samsung/mfc40/s3c_mfc_fw.h ++ A drivers/media/video/samsung/mfc40/h264_dec_fw.c ++ A drivers/media/video/samsung/mfc40/s3c-mfc.h ++ A drivers/media/video/samsung/mfc40/h264_enc_fw.c ++ A drivers/media/video/samsung/mfc40/s3c_mfc_interface.h ++ A drivers/media/video/samsung/mfc40/Kconfig ++ A drivers/media/video/samsung/mfc40/s3c_mfc_intr.c ++ A drivers/media/video/samsung/mfc40/Makefile ++ A drivers/media/video/samsung/mfc40/s3c_mfc_intr.h ++ A drivers/media/video/samsung/mfc40/mp2_dec_fw.c ++ A drivers/media/video/samsung/mfc40/s3c_mfc_logmsg.c ++ A drivers/media/video/samsung/mfc40/mp4_dec_fw.c ++ A drivers/media/video/samsung/mfc40/s3c_mfc_logmsg.h ++ A drivers/media/video/samsung/mfc40/mp4_dec_order_fw.c ++ A drivers/media/video/samsung/mfc40/s3c_mfc_memory.c ++ A drivers/media/video/samsung/mfc40/mp4_enc_fw.c ++ A drivers/media/video/samsung/mfc40/s3c_mfc_memory.h ++ A drivers/media/video/samsung/mfc40/s3c_mfc_buffer_manager.c ++ A drivers/media/video/samsung/mfc40/s3c_mfc_opr.c ++ A drivers/media/video/samsung/mfc40/s3c_mfc_buffer_manager.h ++ A drivers/media/video/samsung/mfc40/s3c_mfc_opr.h ++ A drivers/media/video/samsung/mfc40/s3c-mfc.c ++ A drivers/media/video/samsung/mfc40/s3c_mfc_types.h ++ A drivers/media/video/samsung/mfc40/s3c_mfc_common.c ++ A drivers/media/video/samsung/mfc40/vc1_dec_fw.c ++ A drivers/media/video/samsung/mfc40/s3c_mfc_common.h ++ A arch/arm/plat-s5pc1xx/include/plat/regs-mfc.h ++ ++ ++ Modified files: ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ ++v2.6.28.6-s5pc1xx-r0d9: Jonghun Han ++ - S5PC100 FIMG-3D driver support ++ Modified files: ++ M arch/arm/plat-s3c/dma-pl330.c ++ M arch/arm/plat-s3c/include/mach/s3c-dma.h ++ M drivers/char/s3c_mem.c ++ M drivers/char/s3c_mem.h ++ M drivers/media/video/samsung/g3d/Kconfig ++ M drivers/media/video/samsung/g3d/s3c_fimg3d.h ++ ++v2.6.28.6-s5pc1xx-r0d10: Seungchull Suh ++ - SMC9115 works correctly. Before, full-duplex mode is not set. ++ M drivers/net/smc911x.c ++ ++ ++v2.6.28.6-s5pc1xx-r1: Kyoungil Kim ++ - Official Release(09.03.20) ++ ++v2.6.28.6-s5pc1xx-r1d0: Kyoungil Kim ++ ++v2.6.28.6-s5pc1xx-r1d1: Jaeryul Oh ++ - Support JPEG for s5pc100 ++ ++ Added files: ++ A drivers/media/video/samsung/jpeg_v2/jpg_mem.c ++ A drivers/media/video/samsung/jpeg_v2/jpg_misc.c ++ A drivers/media/video/samsung/jpeg_v2/s3c-jpeg.c ++ A drivers/media/video/samsung/jpeg_v2/jpg_opr.c ++ A drivers/media/video/samsung/jpeg_v2/log_msg.c ++ ++ A drivers/media/video/samsung/jpeg_v2/log_msg.h ++ A drivers/media/video/samsung/jpeg_v2/jpg_conf.h ++ A drivers/media/video/samsung/jpeg_v2/jpg_mem.h ++ A drivers/media/video/samsung/jpeg_v2/jpg_misc.h ++ A drivers/media/video/samsung/jpeg_v2/regs-jpeg.h ++ A drivers/media/video/samsung/jpeg_v2/s3c-jpeg.h ++ A drivers/media/video/samsung/jpeg_v2/jpg_opr.h ++ A drivers/media/video/samsung/jpeg_v2/Makefile ++ A drivers/media/video/samsung/jpeg_v2/Kconfig ++ ++ Modified files: ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s5pc1xx/devs.c ++ M drivers/media/video/samsung/Kconfig ++ M drivers/media/video/samsung/Makefile ++ ++v2.6.28.6-s5pc1xx-r1d2: Kyoungil Kim ++ - The last tag for s5pc1xx branch(09.03.24) ++ ++current linux-2.6-samsung repository ChangeLog ++----------------------------------------------------------------------- ++v2.6.28.6-samsung: Kyoungil Kim ++ - Merge s3c64xx branch and s5pc1xx branch to master branch(09.03.24) ++ ++v2.6.28.6-samsung-r0d0: Kyoungil Kim ++ ++v2.6.28.6-samsung-r0d1: Kukjin Kim ++ - Remove swp file ++ ++ Removed Files: ++ R arch/arm/plat-s3c/include/plat/.cpu-freq.h.swp ++ ++v2.6.28.6-samsung-r0d2: Kyoungil Kim ++ - Unified the ChangeLog files ++ ++ Modified Files: ++ M ChangeLog ++ ++ Deleted Files: ++ D ChangeLog_s3c64xx ++ D ChangeLog_s5pc1xx ++ ++v2.6.28.6-samsung-r0d3: Kukjin Kim ++ - System Timer initialize modified ++ ++ Modified Files: ++ M arch/arm/plat-s5pc1xx/s5pc1xx-time.c ++ ++v2.6.28.6-samsung-r0d4: Kukjin Kim ++ - System Timer init and setup function remodified ++ ++ Modified Files: ++ M arch/arm/plat-s5pc1xx/s5pc1xx-time.c ++ ++v2.6.28.6-samsung-r0d5: Kukjin Kim ++ - Support extcsd revision 1.3 ++ ++ Modified Files: ++ M drivers/mmc/core/mmc.c ++ ++v2.6.28.6-samsung-r0d6: Jaeryul Oh ++ - JPEG for c100 is updated ++ ++ Modified Files: ++ M drivers/media/video/samsung/Kconfig ++ M drivers/media/video/samsung/jpeg_v2/jpg_mem.h ++ M drivers/media/video/samsung/jpeg_v2/jpg_opr.c ++ M drivers/media/video/samsung/jpeg_v2/jpg_opr.h ++ M drivers/media/video/samsung/jpeg_v2/s3c-jpeg.c ++ M drivers/media/video/samsung/jpeg_v2/s3c-jpeg.h ++ ++v2.6.28.6-samsung-r0d7: Jae-Cheol Lee ++ - Adopting system timer h/w bug workaround ++ ++ Modified files: ++ M arch/arm/plat-s5pc1xx/s5pc1xx-time.c ++ ++v2.6.28.6-samsung-r0d8: Byungjae Lee ++ - Implemented OTG Host role for SMDKC100 ++ OTG Host role support only MassStorage and HID(Keyboard, Mouse) ++ ++ Modified Files: ++ M arch/arm/configs/smdkc100mtd_defconfig ++ M arch/arm/configs/smdkc100onenand_defconfig ++ M arch/arm/mach-s3c6410/mach-smdk6410.c ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s5pc1xx/devs.c ++ M drivers/usb/host/Kconfig ++ M drivers/usb/host/s3c-otg/s3c-otg-hcdi-debug.h ++ M drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.c ++ M drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.h ++ M drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.h ++ M drivers/usb/host/s3c-otg/s3c-otg-oci.c ++ M drivers/usb/host/s3c-otg/s3c-otg-oci.h ++ ++v2.6.28.6-samsung-r0d9: Jonghun Han ++ - Support YUV422 Interleave output for FIMC ++ ++ Modified Files: ++ M drivers/media/video/samsung/fimc/s3c_fimc.h ++ M drivers/media/video/samsung/fimc/s3c_fimc3x_regs.c ++ M drivers/media/video/samsung/fimc/s3c_fimc_cfg.c ++ ++v2.6.28.6-samsung-r0d10: Kyoungil Kim ++ - change the smc911 driver from full duplex to half duplex ++ ++ Modified Files: ++ M drivers/net/smc911x.c ++ ++v2.6.28.6-samsung-r0d11: Jae-Cheol Lee ++ - Support SMDK6440 EVT0 board ++ ++ Modified Files: ++ M arch/arm/mach-s5p6440/mach-smdk6440.c ++ M arch/arm/plat-s5p64xx/include/plat/pll.h ++ ++v2.6.28.6-samsung-r0d12: Kyoungil Kim ++ - Prevent for SMDKC100 MM IP ++ ++v2.6.28.6-samsung-r0d13: Jae-Cheol Lee ++ - Fixed PLL calculation bug in MASK value ++ ++ Modified Files: ++ M arch/arm/plat-s3c64xx/include/plat/pll.h ++ M arch/arm/plat-s5pc1xx/include/plat/pll.h ++ ++v2.6.28.6-samsung-r0d14: Byungjae Lee ++ - Implemented USB OTG Device role for SMDK6440 ++ ++ Modified Files: ++ M arch/arm/configs/smdk6440ramdisk_defconfig ++ M arch/arm/mach-s5p6440/mach-smdk6440.c ++ M arch/arm/plat-s3c/include/plat/regs-otg.h ++ M arch/arm/plat-s5p64xx/devs.c ++ M arch/arm/plat-s5p64xx/include/plat/regs-clock.h ++ M drivers/usb/gadget/Kconfig ++ M drivers/usb/gadget/s3c_udc.h ++ M drivers/usb/gadget/s3c_udc_otg.c ++ ++v2.6.28.6-samsung-r0d15: Jongpill Lee ++ - Modify code for SPi ++ ++ Modified Files ++ M drivers/spi/hspi-s3c64xx.c ++ ++v2.6.28.6-samsung-r1: Jaeryul Oh ++ - Official Release (09.04.06) ++ ++v2.6.28.6-samsung-r1d0: Jae-Cheol Lee ++ - Modified default configuration for SMDK6440 ++ Modified Files: ++ M arch/arm/configs/smdk6440ramdisk_defconfig ++ ++v2.6.28.6-samsung-r1d1: Jaeryul Oh ++ - MFC, JPEG suspend/resume related code for SMDK6410 changed ++ Modified Files : ++ M drivers/media/video/samsung/jpeg/jpg_mem.c ++ M drivers/media/video/samsung/jpeg/s3c-jpeg.c ++ M drivers/media/video/samsung/mfc10/s3c_mfc.c ++ ++v2.6.28.6-samsung-r1d2: Jae-Cheol Lee ++ - Modified voltage regulator control code for SMDKC100 ++ Modified Files : ++ M arch/arm/plat-s5pc1xx/ltc3714.c ++ ++v2.6.28.6-samsung-r1d3: Jae-Cheol Lee ++ - Support CHIPID for S5P6440 ++ Modified Files: ++ M arch/arm/plat-s5pc1xx/cpu.c ++ ++v2.6.28.6-samsung-r1d4: Jiun Yu, PyoungJae Jung ++ - fixed cache issue in MFC driver ++ ++v2.6.28.6-samsung-r1d5: Jae-Cheol Lee ++ - Change Console UART port 0 -> 1 for SMDK6440 ++ Modified Files: ++ M arch/arm/configs/smdk6440ramdisk_defconfig ++ ++v2.6.28.6-samsung-r1d6: Byungjae Lee ++ - Fixed BUG USB OTG Device role for SMDK6440 and C100 ++ ++ Modified Files: ++ M drivers/usb/gadget/s3c_udc_otg.c ++ ++v2.6.28.6-samsung-r1d7: Jongpill LEe ++ - Support RTC for S5P6440 ++ ++ Modified files: ++ M arch/arm/mach-s5p6440/include/mach/map.h ++ M arch/arm/mach-s5p6440/mach-smdk6440.c ++ M arch/arm/plat-s3c/include/plat/regs-rtc.h ++ M arch/arm/plat-s5p64xx/devs.c ++ M drivers/rtc/Kconfig ++ M drivers/rtc/rtc-s3c.c ++ ++v2.6.28.6-samsung-r2: Kyoungil Kim ++ - Official Release for SMDK6410(09.04.09) ++ ++v2.6.28.6-samsung-r2d0: Jongpill LEe ++ - Support Watchdog timer for S5P6440 ++ ++ Modified Files: ++ M arch/arm/mach-s5p6440/include/mach/map.h ++ M arch/arm/mach-s5p6440/mach-smdk6440.c ++ M arch/arm/plat-s5p64xx/devs.c ++ M drivers/rtc/rtc-s3c.c ++ M drivers/watchdog/Kconfig ++ ++v2.6.28.6-samsung-r2d1: Jongpill Lee ++ - Support ADC Driver for S5P6440 ++ ++ Modified Files: ++ M arch/arm/mach-s5p6440/include/mach/map.h ++ M arch/arm/mach-s5p6440/mach-smdk6440.c ++ M arch/arm/plat-s3c64xx/adc.c ++ M arch/arm/plat-s5p64xx/Kconfig ++ M arch/arm/plat-s5p64xx/devs.c ++ ++v2.6.28.6-samsung-r2d2: Jiun, Yu, PyoungJae Jung ++ - fixed cache issue in MFC1.0(6410) driver ++ ++ Modified Files : ++ M drivers/media/video/samsung/mfc10/s3c_mfc_set_config.c ++ ++v2.6.28.6-samsung-r2d3: Jiun, Yu, PyoungJae Jung ++ - fixed cache issue in MFC1.0(6410) driver ++ - changed cache update way to dma_cache_maint ++ ++ Modified Files : ++ M drivers/media/video/samsung/mfc10/s3c_mfc_set_config.c ++ M drivers/media/video/samsung/mfc10/s3c_mfc.c ++ M drivers/media/video/samsung/mfc10/s3c_mfc_databuf.c ++ M drivers/media/video/samsung/mfc10/s3c_mfc_instance.c ++ M drivers/media/video/samsung/mfc10/s3c_mfc_set_config.c ++ ++v2.6.28.6-samsung-r2d4: Jae-Cheol Lee ++ - Support DVFS on SMDK6440 board ++ ++ Modified Files : ++ M arch/arm/Kconfig ++ M arch/arm/plat-s5p64xx/Makefile ++ M arch/arm/plat-s5p64xx/clock.c ++ M arch/arm/plat-s5p64xx/ltc3714.c ++ M arch/arm/plat-s5p64xx/s5p64xx-cpufreq ++ ++v2.6.28.6-samsung-r2d5: Jongpill Lee ++ - Modify some code for S5PC100 ++ ++ Modified Files : ++ M arch/arm/plat-s5pc1xx/include/plat/regs-clock.h ++ M arch/arm/plat-s5pc1xx/include/plat/regs-power.h ++ ++v2.6.28.6-samsung-r2d6: Jae-Cheol Lee ++ - Support backlight class by PWM on SMDK6440 board ++ ++ Added Files : ++ A arch/arm/plat-s5p64xx/pwm.c ++ ++ Modified Files : ++ M arch/arm/configs/smdk6440ramdisk_defconfig ++ M arch/arm/mach-s5p6440/cpu.c ++ M arch/arm/mach-s5p6440/mach-smdk6440.c ++ M arch/arm/plat-s3c/include/plat/clock.h ++ M arch/arm/plat-s3c/pwm-clock.c ++ M arch/arm/plat-s5p64xx/Kconfig ++ M arch/arm/plat-s5p64xx/Makefile ++ M arch/arm/plat-s5p64xx/clock.c ++ M arch/arm/plat-s5p64xx/pwm.c ++ M drivers/video/samsung/s3cfb_fimd5x.c ++ ++v2.6.28.6-samsung-r2d7: Jaeryul Oh ++ - MFC suspend/resume related code for SMDK6410 updated ++ Modified Files : ++ M drivers/media/video/samsung/mfc10/s3c_mfc.c ++ M drivers/media/video/samsung/mfc10/s3c_mfc_config.h ++ ++v2.6.28.6-samsung-r2d8: Jinsung Yang ++ - The 1st phase of MIPI-CSI support ++ ++ Addes files: ++ A arch/arm/plat-s5pc1xx/dev-csis.c ++ A arch/arm/plat-s5pc1xx/include/plat/csis.h ++ A arch/arm/plat-s5pc1xx/include/plat/regs-csis.h ++ A arch/arm/plat-s5pc1xx/setup-csis.c ++ A drivers/media/video/samsung/fimc/s3c_csis.c ++ A drivers/media/video/samsung/fimc/s3c_csis.h ++ ++ Modified files: ++ M arch/arm/mach-s5pc100/include/mach/map.h ++ M arch/arm/mach-s5pc100/mach-smdkc100.c ++ M arch/arm/plat-s3c/include/plat/devs.h ++ M arch/arm/plat-s5pc1xx/Kconfig ++ M arch/arm/plat-s5pc1xx/Makefile ++ M arch/arm/plat-s5pc1xx/clock.c ++ M arch/arm/plat-s5pc1xx/include/plat/regs-clock.h ++ M drivers/media/video/samsung/fimc/Kconfig ++ M drivers/media/video/samsung/fimc/Makefile ++ M drivers/media/video/samsung/fimc/s3c_fimc.h ++ ++v2.6.28.6-samsung-mfc-r0: PyoungJae Jung, Jiun Yu ++ - first initial version of MFC branch ++ - upgraded MFC40 driver ++ - updated FW ++ - supported multi-instance ++ - unstable version ++ ++ Addeds files: ++ A drivers/media/video/samsung/mfc40/s3c_mfc_msg.h ++ ++ Modified files: ++ M drivers/media/video/samsung/Kconfig ++ M drivers/media/video/samsung/mfc40/Kconfig ++ M drivers/media/video/samsung/mfc40/s3c-mfc.c ++ M drivers/media/video/samsung/mfc40/s3c_mfc_buffer_manager.c ++ M drivers/media/video/samsung/mfc40/s3c_mfc_common.c ++ M drivers/media/video/samsung/mfc40/s3c_mfc_interface.h ++ M drivers/media/video/samsung/mfc40/s3c_mfc_intr.c ++ M drivers/media/video/samsung/mfc40/s3c_mfc_logmsg.c ++ M drivers/media/video/samsung/mfc40/s3c_mfc_logmsg.h ++ M drivers/media/video/samsung/mfc40/s3c_mfc_opr.c ++ ++ Deleted files: ++ D drivers/media/video/samsung/mfc40/s3c-mfc.h ++ ++v2.6.28.6-samsung-mfc-r0d0: PyoungJae Jung, Jiun Yu ++ - updated new MFC driver ++ - fixed bugs in memory manager unit in multi-instance ++ - deleted unused files (logmsg) ++ - pre beta level version ++ ++ Modified files: ++ M drivers/media/video/samsung/mfc40/Makefile ++ M drivers/media/video/samsung/mfc40/command_control_fw.c ++ M drivers/media/video/samsung/mfc40/h263_dec_fw.c ++ M drivers/media/video/samsung/mfc40/h264_dec_fw.c ++ M drivers/media/video/samsung/mfc40/h264_enc_fw.c ++ M drivers/media/video/samsung/mfc40/mp2_dec_fw.c ++ M drivers/media/video/samsung/mfc40/mp4_dec_fw.c ++ M drivers/media/video/samsung/mfc40/mp4_enc_fw.c ++ M drivers/media/video/samsung/mfc40/s3c-mfc.c ++ M drivers/media/video/samsung/mfc40/s3c_mfc_buffer_manager.c ++ M drivers/media/video/samsung/mfc40/s3c_mfc_buffer_manager.h ++ M drivers/media/video/samsung/mfc40/s3c_mfc_common.c ++ M drivers/media/video/samsung/mfc40/s3c_mfc_common.h ++ M drivers/media/video/samsung/mfc40/s3c_mfc_errorno.h ++ M drivers/media/video/samsung/mfc40/s3c_mfc_fw.h ++ M drivers/media/video/samsung/mfc40/s3c_mfc_interface.h ++ M drivers/media/video/samsung/mfc40/s3c_mfc_logmsg.h ++ M drivers/media/video/samsung/mfc40/s3c_mfc_memory.h ++ M drivers/media/video/samsung/mfc40/s3c_mfc_opr.c ++ M drivers/media/video/samsung/mfc40/s3c_mfc_opr.h ++ M drivers/media/video/samsung/mfc40/vc1_dec_fw.c ++ ++ Deleted files: ++ D drivers/media/video/samsung/mfc40/s3c_mfc_msg.h ++ D drivers/media/video/samsung/mfc40/s3c_mfc_logmsg.c ++ ++v2.6.28.6-samsung-mfc-r0d1: PyoungJae Jung, Jiun Yu, Satish ++ - update CMM driver for hybrid Divx in 6410 support ++ - change coding style ++ ++ Added files: ++ A drivers/media/video/samsung/cmm/s3c_cmm.c ++ A drivers/media/video/samsung/cmm/s3c_cmm.h ++ ++ Modified files: ++ M drivers/media/video/samsung/cmm/Makefile ++ ++ Deleted files: ++ D drivers/media/video/samsung/cmm/CMMMisc.c ++ D drivers/media/video/samsung/cmm/CMMMisc.h ++ D drivers/media/video/samsung/cmm/LogMsg.c ++ D drivers/media/video/samsung/cmm/LogMsg.h ++ D drivers/media/video/samsung/cmm/s3c-cmm.c ++ D drivers/media/video/samsung/cmm/s3c-cmm.h ++ ++v2.6.28.6-samsung-r3d3-mfc-r0: PyoungJae Jung, Jiun Yu ++ - merge with v2.6.28.6-samsung-r3d3 in master branch ++ - change tag name convention ++ * master branch tag + mfc tag +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/Documentation/spi/spidev_fdx.c linux-2.6.28.6/Documentation/spi/spidev_fdx.c +--- linux-2.6.28/Documentation/spi/spidev_fdx.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/Documentation/spi/spidev_fdx.c 2009-04-30 09:36:37.000000000 +0200 +@@ -14,12 +14,14 @@ + + static int verbose; + ++#define MAX_LEN 4096 ++ + static void do_read(int fd, int len) + { +- unsigned char buf[32], *bp; +- int status; ++ unsigned char buf[MAX_LEN], *bp; ++ int status, i; + +- /* read at least 2 bytes, no more than 32 */ ++ /* read at least 2 bytes, no more than MAX_LEN */ + if (len < 2) + len = 2; + else if (len > sizeof(buf)) +@@ -36,20 +38,22 @@ + return; + } + +- printf("read(%2d, %2d): %02x %02x,", len, status, +- buf[0], buf[1]); +- status -= 2; +- bp = buf + 2; +- while (status-- > 0) +- printf(" %02x", *bp++); ++ printf("\nread(%2d, %2d):", len, status); ++ bp = buf; ++ for(i=0; i), the IPAQ 1940 or + the Samsung SMDK2410 development board (and derivatives). + ++config ARCH_S3C64XX ++ bool "Samsung S3C64XX" ++ select GENERIC_GPIO ++ select HAVE_CLK ++ help ++ Samsung S3C64XX series based systems ++ ++config ARCH_S5P64XX ++ bool "Samsung S5P64XX" ++ select GENERIC_GPIO ++ select HAVE_CLK ++ help ++ Samsung S5P64XX series based systems ++ ++config ARCH_S5PC1XX ++ bool "Samsung S5PC1XX" ++ select GENERIC_GPIO ++ select HAVE_CLK ++ help ++ Samsung S5PC1XX series based systems ++ + config ARCH_SHARK + bool "Shark" + select ISA +@@ -590,6 +611,9 @@ + source "arch/arm/mach-kirkwood/Kconfig" + + source "arch/arm/plat-s3c24xx/Kconfig" ++source "arch/arm/plat-s3c64xx/Kconfig" ++source "arch/arm/plat-s5pc1xx/Kconfig" ++source "arch/arm/plat-s5p64xx/Kconfig" + source "arch/arm/plat-s3c/Kconfig" + + if ARCH_S3C2410 +@@ -601,6 +625,19 @@ + source "arch/arm/mach-s3c2443/Kconfig" + endif + ++if ARCH_S3C64XX ++source "arch/arm/mach-s3c6400/Kconfig" ++source "arch/arm/mach-s3c6410/Kconfig" ++endif ++ ++if ARCH_S5PC1XX ++source "arch/arm/mach-s5pc100/Kconfig" ++endif ++ ++if ARCH_S5P64XX ++source "arch/arm/mach-s5p6440/Kconfig" ++endif ++ + source "arch/arm/mach-lh7a40x/Kconfig" + + source "arch/arm/mach-imx/Kconfig" +@@ -805,7 +842,7 @@ + config HZ + int + default 128 if ARCH_L7200 +- default 200 if ARCH_EBSA110 || ARCH_S3C2410 ++ default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S3C64XX || ARCH_S5P64XX || ARCH_S5PC1XX + default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER + default AT91_TIMER_HZ if ARCH_AT91 + default 100 +@@ -876,7 +913,8 @@ + ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ + ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ + ARCH_AT91 || ARCH_DAVINCI || \ +- ARCH_KS8695 || MACH_RD88F5182 ++ ARCH_KS8695 || MACH_RD88F5182 || \ ++ MACH_SMDKC100 + help + If you say Y here, the LEDs on your machine will be used + to provide useful information about your current system status. +@@ -891,7 +929,8 @@ + config LEDS_TIMER + bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \ + OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ +- || MACH_OMAP_PERSEUS2 ++ || MACH_OMAP_PERSEUS2 || \ ++ MACH_SMDKC100 + depends on LEDS + depends on !GENERIC_CLOCKEVENTS + default y if ARCH_EBSA110 +@@ -910,7 +949,7 @@ + bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \ + !ARCH_OMAP) \ + || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \ +- || MACH_OMAP_PERSEUS2 ++ || MACH_OMAP_PERSEUS2 || MACH_SMDKC100 + depends on LEDS + help + If you say Y here, the red LED will be used to give a good real +@@ -1037,7 +1076,7 @@ + + menu "CPU Power Management" + +-if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA) ++if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA || CPU_S3C6410 || CPU_S5PC100 || CPU_S5P6440) + + source "drivers/cpufreq/Kconfig" + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/Makefile linux-2.6.28.6/arch/arm/Makefile +--- linux-2.6.28/arch/arm/Makefile 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/Makefile 2009-04-30 09:36:37.000000000 +0200 +@@ -121,7 +121,14 @@ + machine-$(CONFIG_ARCH_OMAP3) := omap2 + plat-$(CONFIG_ARCH_OMAP) := omap + machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443 ++ machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 + plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c ++ machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410 ++ plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c ++ machine-$(CONFIG_ARCH_S5P64XX) := s5p6440 ++ plat-$(CONFIG_PLAT_S5P64XX) := s5p64xx s3c ++ machine-$(CONFIG_ARCH_S5PC1XX) := s5pc100 ++ plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx s3c + machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x + machine-$(CONFIG_ARCH_VERSATILE) := versatile + machine-$(CONFIG_ARCH_IMX) := imx +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/common/vic.c linux-2.6.28.6/arch/arm/common/vic.c +--- linux-2.6.28/arch/arm/common/vic.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/common/vic.c 2009-04-30 09:36:37.000000000 +0200 +@@ -69,12 +69,12 @@ + /* + * Make sure we clear all existing interrupts + */ +- writel(0, base + VIC_VECT_ADDR); ++ writel(0, base + VIC_PL190_VECT_ADDR); + for (i = 0; i < 19; i++) { + unsigned int value; + +- value = readl(base + VIC_VECT_ADDR); +- writel(value, base + VIC_VECT_ADDR); ++ value = readl(base + VIC_PL190_VECT_ADDR); ++ writel(value, base + VIC_PL190_VECT_ADDR); + } + + for (i = 0; i < 16; i++) { +@@ -82,7 +82,7 @@ + writel(VIC_VECT_CNTL_ENABLE | i, reg); + } + +- writel(32, base + VIC_DEF_VECT_ADDR); ++ writel(32, base + VIC_PL190_DEF_VECT_ADDR); + + for (i = 0; i < 32; i++) { + unsigned int irq = irq_start + i; +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/configs/s3c6400_defconfig linux-2.6.28.6/arch/arm/configs/s3c6400_defconfig +--- linux-2.6.28/arch/arm/configs/s3c6400_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/configs/s3c6400_defconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,845 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28-rc3 ++# Mon Nov 3 10:10:30 2008 ++# ++CONFIG_ARM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++CONFIG_NO_IOPORT=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++CONFIG_LOCALVERSION_AUTO=y ++CONFIG_SWAP=y ++# CONFIG_SYSVIPC is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_COMPAT_BRK=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++CONFIG_LSF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_CLASSIC_RCU=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++CONFIG_ARCH_S3C64XX=y ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_PLAT_S3C64XX=y ++CONFIG_CPU_S3C6400_INIT=y ++CONFIG_CPU_S3C6400_CLOCK=y ++CONFIG_S3C64XX_SETUP_I2C0=y ++CONFIG_S3C64XX_SETUP_I2C1=y ++CONFIG_PLAT_S3C=y ++ ++# ++# Boot options ++# ++CONFIG_S3C_BOOT_ERROR_RESET=y ++ ++# ++# Power management ++# ++CONFIG_S3C_LOWLEVEL_UART_PORT=0 ++CONFIG_S3C_GPIO_SPACE=0 ++CONFIG_S3C_GPIO_TRACK=y ++CONFIG_S3C_GPIO_PULL_UPDOWN=y ++CONFIG_S3C_GPIO_CFG_S3C24XX=y ++CONFIG_S3C_GPIO_CFG_S3C64XX=y ++CONFIG_S3C_DEV_HSMMC=y ++CONFIG_S3C_DEV_HSMMC1=y ++CONFIG_S3C_DEV_I2C1=y ++CONFIG_CPU_S3C6410=y ++CONFIG_S3C6410_SETUP_SDHCI=y ++CONFIG_MACH_SMDK6410=y ++CONFIG_SMDK6410_SD_CH0=y ++# CONFIG_SMDK6410_SD_CH1 is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++CONFIG_ARM_THUMB=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++CONFIG_ARM_VIC=y ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=100 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/bin/bash initrd=0x51000000,4M" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++# CONFIG_FPE_NWFPE is not set ++# CONFIG_FPE_FASTFPE is not set ++CONFIG_VFP=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++ ++# ++# Power management options ++# ++# CONFIG_PM is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_NET is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_MTD is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=4096 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++# CONFIG_SCSI is not set ++# CONFIG_SCSI_DMA is not set ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_GPIO is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_LIFEBOOK=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++CONFIG_SERIAL_8250=y ++# CONFIG_SERIAL_8250_CONSOLE is not set ++CONFIG_SERIAL_8250_NR_UARTS=4 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=4 ++# CONFIG_SERIAL_8250_EXTENDED is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_SAMSUNG=y ++CONFIG_SERIAL_SAMSUNG_UARTS=4 ++# CONFIG_SERIAL_SAMSUNG_DEBUG is not set ++CONFIG_SERIAL_SAMSUNG_CONSOLE=y ++CONFIG_SERIAL_S3C6400=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++CONFIG_I2C_S3C2410=y ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++CONFIG_AT24=y ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++# CONFIG_DEBUG_GPIO is not set ++# CONFIG_GPIO_SYSFS is not set ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++CONFIG_HWMON=y ++# CONFIG_HWMON_VID is not set ++# CONFIG_SENSORS_AD7414 is not set ++# CONFIG_SENSORS_AD7418 is not set ++# CONFIG_SENSORS_ADM1021 is not set ++# CONFIG_SENSORS_ADM1025 is not set ++# CONFIG_SENSORS_ADM1026 is not set ++# CONFIG_SENSORS_ADM1029 is not set ++# CONFIG_SENSORS_ADM1031 is not set ++# CONFIG_SENSORS_ADM9240 is not set ++# CONFIG_SENSORS_ADT7470 is not set ++# CONFIG_SENSORS_ADT7473 is not set ++# CONFIG_SENSORS_ATXP1 is not set ++# CONFIG_SENSORS_DS1621 is not set ++# CONFIG_SENSORS_F71805F is not set ++# CONFIG_SENSORS_F71882FG is not set ++# CONFIG_SENSORS_F75375S is not set ++# CONFIG_SENSORS_GL518SM is not set ++# CONFIG_SENSORS_GL520SM is not set ++# CONFIG_SENSORS_IT87 is not set ++# CONFIG_SENSORS_LM63 is not set ++# CONFIG_SENSORS_LM75 is not set ++# CONFIG_SENSORS_LM77 is not set ++# CONFIG_SENSORS_LM78 is not set ++# CONFIG_SENSORS_LM80 is not set ++# CONFIG_SENSORS_LM83 is not set ++# CONFIG_SENSORS_LM85 is not set ++# CONFIG_SENSORS_LM87 is not set ++# CONFIG_SENSORS_LM90 is not set ++# CONFIG_SENSORS_LM92 is not set ++# CONFIG_SENSORS_LM93 is not set ++# CONFIG_SENSORS_MAX1619 is not set ++# CONFIG_SENSORS_MAX6650 is not set ++# CONFIG_SENSORS_PC87360 is not set ++# CONFIG_SENSORS_PC87427 is not set ++# CONFIG_SENSORS_DME1737 is not set ++# CONFIG_SENSORS_SMSC47M1 is not set ++# CONFIG_SENSORS_SMSC47M192 is not set ++# CONFIG_SENSORS_SMSC47B397 is not set ++# CONFIG_SENSORS_ADS7828 is not set ++# CONFIG_SENSORS_THMC50 is not set ++# CONFIG_SENSORS_VT1211 is not set ++# CONFIG_SENSORS_W83781D is not set ++# CONFIG_SENSORS_W83791D is not set ++# CONFIG_SENSORS_W83792D is not set ++# CONFIG_SENSORS_W83793 is not set ++# CONFIG_SENSORS_W83L785TS is not set ++# CONFIG_SENSORS_W83L786NG is not set ++# CONFIG_SENSORS_W83627HF is not set ++# CONFIG_SENSORS_W83627EHF is not set ++# CONFIG_HWMON_DEBUG_CHIP is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++# CONFIG_WATCHDOG is not set ++ ++# ++# Sonics Silicon Backplane ++# ++CONFIG_SSB_POSSIBLE=y ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++# CONFIG_FB is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_SOUND is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++# CONFIG_HID_PID is not set ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++# CONFIG_USB_ARCH_HAS_OHCI is not set ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++# CONFIG_USB is not set ++ ++# ++# Enable Host or Gadget support to see Inventra options ++# ++ ++# ++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' ++# ++# CONFIG_USB_GADGET is not set ++CONFIG_MMC=y ++CONFIG_MMC_DEBUG=y ++CONFIG_MMC_UNSAFE_RESUME=y ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++CONFIG_SDIO_UART=y ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_S3C=y ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_NEW_LEDS is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++ ++# ++# Voltage and Current regulators ++# ++# CONFIG_REGULATOR is not set ++# CONFIG_REGULATOR_FIXED_VOLTAGE is not set ++# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set ++# CONFIG_REGULATOR_BQ24022 is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++CONFIG_EXT3_FS_POSIX_ACL=y ++CONFIG_EXT3_FS_SECURITY=y ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++CONFIG_GENERIC_ACL=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++# CONFIG_MSDOS_FS is not set ++# CONFIG_VFAT_FS is not set ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_CRAMFS=y ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++CONFIG_ROMFS_FS=y ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++# CONFIG_NLS is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_PI_LIST=y ++# CONFIG_RT_MUTEX_TESTER is not set ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++CONFIG_DEBUG_SPINLOCK_SLEEP=y ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_DEBUG_USER=y ++CONFIG_DEBUG_ERRORS=y ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++CONFIG_DEBUG_S3C_PORT=y ++CONFIG_DEBUG_S3C_UART=0 ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++# CONFIG_CRYPTO is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++# CONFIG_CRC_CCITT is not set ++# CONFIG_CRC16 is not set ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_DMA=y +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/configs/smdk6410mtd_defconfig linux-2.6.28.6/arch/arm/configs/smdk6410mtd_defconfig +--- linux-2.6.28/arch/arm/configs/smdk6410mtd_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/configs/smdk6410mtd_defconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,1468 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28-rc8 ++# Fri Jan 30 14:36:44 2009 ++# ++CONFIG_ARM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++CONFIG_NO_IOPORT=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++CONFIG_LOCALVERSION_AUTO=y ++CONFIG_SWAP=y ++# CONFIG_SYSVIPC is not set ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_COMPAT_BRK=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++CONFIG_LSF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_CLASSIC_RCU=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++CONFIG_ARCH_S3C64XX=y ++# CONFIG_ARCH_S5P64XX is not set ++# CONFIG_ARCH_S5PC1XX is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_PLAT_S3C64XX=y ++CONFIG_CPU_S3C6400_INIT=y ++CONFIG_CPU_S3C6400_CLOCK=y ++CONFIG_S3C64XX_SETUP_I2C0=y ++CONFIG_S3C64XX_SETUP_I2C1=y ++# CONFIG_S3C64XX_ADC is not set ++CONFIG_PLAT_S3C=y ++ ++# ++# Boot options ++# ++CONFIG_S3C_BOOT_ERROR_RESET=y ++ ++# ++# Power management ++# ++CONFIG_S3C_LOWLEVEL_UART_PORT=0 ++CONFIG_SPLIT_ROOT_FILESYSTEM=y ++CONFIG_S3C_GPIO_SPACE=0 ++CONFIG_S3C_GPIO_TRACK=y ++CONFIG_S3C_GPIO_PULL_UPDOWN=y ++CONFIG_S3C_GPIO_CFG_S3C24XX=y ++CONFIG_S3C_GPIO_CFG_S3C64XX=y ++CONFIG_S3C_DEV_HSMMC=y ++CONFIG_S3C_DEV_HSMMC1=y ++CONFIG_S3C_DEV_I2C1=y ++CONFIG_S3C_DMA_PL080=y ++CONFIG_CPU_S3C6410=y ++CONFIG_S3C6410_SETUP_SDHCI=y ++CONFIG_MACH_SMDK6410=y ++CONFIG_SMDK6410_SD_CH0=y ++# CONFIG_SMDK6410_SD_CH1 is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++CONFIG_ARM_THUMB=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++CONFIG_ARM_VIC=y ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=200 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC0,115200 mem=128M" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_FREQ is not set ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_FPE_NWFPE=y ++# CONFIG_FPE_NWFPE_XP is not set ++# CONFIG_FPE_FASTFPE is not set ++CONFIG_VFP=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++ ++# ++# Power management options ++# ++# CONFIG_PM is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_PACKET is not set ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++CONFIG_IP_PNP_BOOTP=y ++# CONFIG_IP_PNP_RARP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++CONFIG_INET_XFRM_MODE_TRANSPORT=y ++CONFIG_INET_XFRM_MODE_TUNNEL=y ++CONFIG_INET_XFRM_MODE_BEET=y ++# CONFIG_INET_LRO is not set ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_CONCAT is not set ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_VERIFY_WRITE is not set ++# CONFIG_MTD_NAND_ECC_SMC is not set ++# CONFIG_MTD_NAND_MUSEUM_IDS is not set ++# CONFIG_MTD_NAND_GPIO is not set ++CONFIG_MTD_NAND_IDS=y ++CONFIG_MTD_NAND_S3C=y ++# CONFIG_MTD_NAND_S3C_DEBUG is not set ++CONFIG_MTD_NAND_S3C_HWECC=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ALAUDA is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# UBI - Unsorted block images ++# ++# CONFIG_MTD_UBI is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=8192 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++# CONFIG_SCSI_MULTI_LUN is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_PHYLIB is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_AX88796 is not set ++# CONFIG_SMC91X is not set ++# CONFIG_DM9000 is not set ++CONFIG_SMC911X=y ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++CONFIG_NETDEV_1000=y ++CONFIG_NETDEV_10000=y ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++CONFIG_PPP=y ++CONFIG_PPP_MULTILINK=y ++CONFIG_PPP_FILTER=y ++CONFIG_PPP_ASYNC=y ++CONFIG_PPP_SYNC_TTY=y ++# CONFIG_PPP_DEFLATE is not set ++# CONFIG_PPP_BSDCOMP is not set ++# CONFIG_PPP_MPPE is not set ++# CONFIG_PPPOE is not set ++# CONFIG_PPPOL2TP is not set ++# CONFIG_SLIP is not set ++CONFIG_SLHC=y ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_GPIO is not set ++# CONFIG_KEYPAD_S3C is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_LIFEBOOK=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_S3C=y ++CONFIG_TOUCHSCREEN_NEW=y ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++CONFIG_SERIAL_8250=y ++# CONFIG_SERIAL_8250_CONSOLE is not set ++CONFIG_SERIAL_8250_NR_UARTS=4 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=4 ++# CONFIG_SERIAL_8250_EXTENDED is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_SAMSUNG=y ++CONFIG_SERIAL_SAMSUNG_UARTS=4 ++# CONFIG_SERIAL_SAMSUNG_DEBUG is not set ++CONFIG_SERIAL_SAMSUNG_CONSOLE=y ++CONFIG_SERIAL_S3C6400=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_S3C_MEM=y ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++CONFIG_I2C_S3C2410=y ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++CONFIG_AT24=y ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++# CONFIG_DEBUG_GPIO is not set ++# CONFIG_GPIO_SYSFS is not set ++ ++# ++# Memory mapped GPIO expanders: ++# ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++CONFIG_HWMON=y ++# CONFIG_HWMON_VID is not set ++# CONFIG_SENSORS_AD7414 is not set ++# CONFIG_SENSORS_AD7418 is not set ++# CONFIG_SENSORS_ADM1021 is not set ++# CONFIG_SENSORS_ADM1025 is not set ++# CONFIG_SENSORS_ADM1026 is not set ++# CONFIG_SENSORS_ADM1029 is not set ++# CONFIG_SENSORS_ADM1031 is not set ++# CONFIG_SENSORS_ADM9240 is not set ++# CONFIG_SENSORS_ADT7462 is not set ++# CONFIG_SENSORS_ADT7470 is not set ++# CONFIG_SENSORS_ADT7473 is not set ++# CONFIG_SENSORS_ATXP1 is not set ++# CONFIG_SENSORS_DS1621 is not set ++# CONFIG_SENSORS_F71805F is not set ++# CONFIG_SENSORS_F71882FG is not set ++# CONFIG_SENSORS_F75375S is not set ++# CONFIG_SENSORS_GL518SM is not set ++# CONFIG_SENSORS_GL520SM is not set ++# CONFIG_SENSORS_IT87 is not set ++# CONFIG_SENSORS_LM63 is not set ++# CONFIG_SENSORS_LM75 is not set ++# CONFIG_SENSORS_LM77 is not set ++# CONFIG_SENSORS_LM78 is not set ++# CONFIG_SENSORS_LM80 is not set ++# CONFIG_SENSORS_LM83 is not set ++# CONFIG_SENSORS_LM85 is not set ++# CONFIG_SENSORS_LM87 is not set ++# CONFIG_SENSORS_LM90 is not set ++# CONFIG_SENSORS_LM92 is not set ++# CONFIG_SENSORS_LM93 is not set ++# CONFIG_SENSORS_MAX1619 is not set ++# CONFIG_SENSORS_MAX6650 is not set ++# CONFIG_SENSORS_PC87360 is not set ++# CONFIG_SENSORS_PC87427 is not set ++# CONFIG_SENSORS_DME1737 is not set ++# CONFIG_SENSORS_SMSC47M1 is not set ++# CONFIG_SENSORS_SMSC47M192 is not set ++# CONFIG_SENSORS_SMSC47B397 is not set ++# CONFIG_SENSORS_ADS7828 is not set ++# CONFIG_SENSORS_THMC50 is not set ++# CONFIG_SENSORS_VT1211 is not set ++# CONFIG_SENSORS_W83781D is not set ++# CONFIG_SENSORS_W83791D is not set ++# CONFIG_SENSORS_W83792D is not set ++# CONFIG_SENSORS_W83793 is not set ++# CONFIG_SENSORS_W83L785TS is not set ++# CONFIG_SENSORS_W83L786NG is not set ++# CONFIG_SENSORS_W83627HF is not set ++# CONFIG_SENSORS_W83627EHF is not set ++# CONFIG_HWMON_DEBUG_CHIP is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# # ++# # Watchdog Device Drivers ++# # ++# # CONFIG_SOFT_WATCHDOG is not set ++CONFIG_S3C2410_WATCHDOG=y ++ ++# # ++# # ISA-based Watchdog Cards ++# # ++# # CONFIG_PCWATCHDOG is not set ++# # CONFIG_MIXCOMWD is not set ++# # CONFIG_WDT is not set ++ ++# ++# Sonics Silicon Backplane ++# ++CONFIG_SSB_POSSIBLE=y ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++CONFIG_FB_S3C=y ++CONFIG_FB_S3C_LTE480WV=y ++# CONFIG_FB_S3C_LTV350QV is not set ++# CONFIG_FB_S3C_LTS222QV is not set ++CONFIG_FB_S3C_BPP=y ++# CONFIG_FB_S3C_BPP_8 is not set ++CONFIG_FB_S3C_BPP_16=y ++# CONFIG_FB_S3C_BPP_24 is not set ++# CONFIG_FB_S3C_BPP_32 is not set ++CONFIG_FB_S3C_NUM=1 ++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set ++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++# CONFIG_LOGO_LINUX_CLUT224 is not set ++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++CONFIG_SND_ARM=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_CAIAQ is not set ++CONFIG_SND_SOC=y ++ ++# ++# SoC Audio for the Samsung S3C ++# ++CONFIG_SND_S3C64XX_SOC=y ++CONFIG_SND_S3C6410_SOC_I2S=y ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713 is not set ++CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8580=y ++CONFIG_SOUND_WM8580_INPUT_STREAM_LINE=y ++# CONFIG_SOUND_WM8580_INPUT_STREAM_MIC is not set ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990 is not set ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM8580=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_BRIGHT=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_DELL=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++CONFIG_USB_DEVICE_CLASS=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_DPCM is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++# CONFIG_USB_GADGET is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++CONFIG_SDIO_UART=y ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_S3C=y ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_NEW_LEDS is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++CONFIG_EXT3_FS_POSIX_ACL=y ++CONFIG_EXT3_FS_SECURITY=y ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++CONFIG_GENERIC_ACL=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_JFFS2_FS is not set ++CONFIG_CRAMFS=y ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++CONFIG_ROMFS_FS=y ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++# CONFIG_NFS_FS is not set ++# CONFIG_NFSD is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_UTF8 is not set ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_PI_LIST=y ++# CONFIG_RT_MUTEX_TESTER is not set ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++CONFIG_DEBUG_SPINLOCK_SLEEP=y ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_DEBUG_USER=y ++CONFIG_DEBUG_ERRORS=y ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++CONFIG_DEBUG_S3C_PORT=y ++CONFIG_DEBUG_S3C_UART=0 ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++# CONFIG_CRYPTO_MANAGER is not set ++# CONFIG_CRYPTO_MANAGER2 is not set ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++# CONFIG_CRYPTO_MD5 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_CRC_CCITT=y ++# CONFIG_CRC16 is not set ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_DMA=y +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/configs/smdk6410nfs_defconfig linux-2.6.28.6/arch/arm/configs/smdk6410nfs_defconfig +--- linux-2.6.28/arch/arm/configs/smdk6410nfs_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/configs/smdk6410nfs_defconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,1395 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28-rc4 ++# Tue Nov 25 12:51:23 2008 ++# ++CONFIG_ARM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++CONFIG_NO_IOPORT=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++CONFIG_LOCALVERSION_AUTO=y ++CONFIG_SWAP=y ++# CONFIG_SYSVIPC is not set ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_COMPAT_BRK=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++CONFIG_LSF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_CLASSIC_RCU=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++CONFIG_ARCH_S3C64XX=y ++# CONFIG_ARCH_S5PC1XX is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_PLAT_S3C64XX=y ++CONFIG_CPU_S3C6400_INIT=y ++CONFIG_CPU_S3C6400_CLOCK=y ++CONFIG_S3C64XX_SETUP_I2C0=y ++CONFIG_S3C64XX_SETUP_I2C1=y ++CONFIG_PLAT_S3C=y ++ ++# ++# Boot options ++# ++CONFIG_S3C_BOOT_ERROR_RESET=y ++ ++# ++# Power management ++# ++CONFIG_S3C_LOWLEVEL_UART_PORT=0 ++CONFIG_S3C_GPIO_SPACE=0 ++CONFIG_S3C_GPIO_TRACK=y ++CONFIG_S3C_GPIO_PULL_UPDOWN=y ++CONFIG_S3C_GPIO_CFG_S3C24XX=y ++CONFIG_S3C_GPIO_CFG_S3C64XX=y ++CONFIG_S3C_DEV_HSMMC=y ++CONFIG_S3C_DEV_HSMMC1=y ++CONFIG_S3C_DEV_I2C1=y ++CONFIG_CPU_S3C6410=y ++CONFIG_S3C6410_SETUP_SDHCI=y ++CONFIG_MACH_SMDK6410=y ++CONFIG_SMDK6410_SD_CH0=y ++# CONFIG_SMDK6410_SD_CH1 is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++CONFIG_ARM_THUMB=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++CONFIG_ARM_VIC=y ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=200 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_CMDLINE="root=/dev/nfs rw nfsroot=12.23.106.52:/opt/small_root_eabi ip=192.168.0.20:12.23.106.52:192.168.0.1:255.255.255.0:test::off init=/linuxrc console=ttySAC0,115200 mem=128M" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++# CONFIG_FPE_NWFPE is not set ++# CONFIG_FPE_FASTFPE is not set ++CONFIG_VFP=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++ ++# ++# Power management options ++# ++# CONFIG_PM is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_PACKET is not set ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++CONFIG_IP_PNP_BOOTP=y ++# CONFIG_IP_PNP_RARP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++CONFIG_INET_XFRM_MODE_TRANSPORT=y ++CONFIG_INET_XFRM_MODE_TUNNEL=y ++CONFIG_INET_XFRM_MODE_BEET=y ++# CONFIG_INET_LRO is not set ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++# CONFIG_MTD is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=8192 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++# CONFIG_SCSI_MULTI_LUN is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_PHYLIB is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_AX88796 is not set ++# CONFIG_SMC91X is not set ++# CONFIG_DM9000 is not set ++CONFIG_SMC911X=y ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++CONFIG_NETDEV_1000=y ++CONFIG_NETDEV_10000=y ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++# CONFIG_WAN is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_GPIO is not set ++# CONFIG_KEYPAD_S3C is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_LIFEBOOK=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_S3C=y ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++CONFIG_SERIAL_8250=y ++# CONFIG_SERIAL_8250_CONSOLE is not set ++CONFIG_SERIAL_8250_NR_UARTS=4 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=4 ++# CONFIG_SERIAL_8250_EXTENDED is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_SAMSUNG=y ++CONFIG_SERIAL_SAMSUNG_UARTS=4 ++# CONFIG_SERIAL_SAMSUNG_DEBUG is not set ++CONFIG_SERIAL_SAMSUNG_CONSOLE=y ++CONFIG_SERIAL_S3C6400=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_NVRAM is not set ++# CONFIG_S3C_ADC is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++CONFIG_I2C_S3C2410=y ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++CONFIG_AT24=y ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++# CONFIG_DEBUG_GPIO is not set ++# CONFIG_GPIO_SYSFS is not set ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++CONFIG_HWMON=y ++# CONFIG_HWMON_VID is not set ++# CONFIG_SENSORS_AD7414 is not set ++# CONFIG_SENSORS_AD7418 is not set ++# CONFIG_SENSORS_ADM1021 is not set ++# CONFIG_SENSORS_ADM1025 is not set ++# CONFIG_SENSORS_ADM1026 is not set ++# CONFIG_SENSORS_ADM1029 is not set ++# CONFIG_SENSORS_ADM1031 is not set ++# CONFIG_SENSORS_ADM9240 is not set ++# CONFIG_SENSORS_ADT7470 is not set ++# CONFIG_SENSORS_ADT7473 is not set ++# CONFIG_SENSORS_ATXP1 is not set ++# CONFIG_SENSORS_DS1621 is not set ++# CONFIG_SENSORS_F71805F is not set ++# CONFIG_SENSORS_F71882FG is not set ++# CONFIG_SENSORS_F75375S is not set ++# CONFIG_SENSORS_GL518SM is not set ++# CONFIG_SENSORS_GL520SM is not set ++# CONFIG_SENSORS_IT87 is not set ++# CONFIG_SENSORS_LM63 is not set ++# CONFIG_SENSORS_LM75 is not set ++# CONFIG_SENSORS_LM77 is not set ++# CONFIG_SENSORS_LM78 is not set ++# CONFIG_SENSORS_LM80 is not set ++# CONFIG_SENSORS_LM83 is not set ++# CONFIG_SENSORS_LM85 is not set ++# CONFIG_SENSORS_LM87 is not set ++# CONFIG_SENSORS_LM90 is not set ++# CONFIG_SENSORS_LM92 is not set ++# CONFIG_SENSORS_LM93 is not set ++# CONFIG_SENSORS_MAX1619 is not set ++# CONFIG_SENSORS_MAX6650 is not set ++# CONFIG_SENSORS_PC87360 is not set ++# CONFIG_SENSORS_PC87427 is not set ++# CONFIG_SENSORS_DME1737 is not set ++# CONFIG_SENSORS_SMSC47M1 is not set ++# CONFIG_SENSORS_SMSC47M192 is not set ++# CONFIG_SENSORS_SMSC47B397 is not set ++# CONFIG_SENSORS_ADS7828 is not set ++# CONFIG_SENSORS_THMC50 is not set ++# CONFIG_SENSORS_VT1211 is not set ++# CONFIG_SENSORS_W83781D is not set ++# CONFIG_SENSORS_W83791D is not set ++# CONFIG_SENSORS_W83792D is not set ++# CONFIG_SENSORS_W83793 is not set ++# CONFIG_SENSORS_W83L785TS is not set ++# CONFIG_SENSORS_W83L786NG is not set ++# CONFIG_SENSORS_W83627HF is not set ++# CONFIG_SENSORS_W83627EHF is not set ++# CONFIG_HWMON_DEBUG_CHIP is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# # ++# # Watchdog Device Drivers ++# # ++# # CONFIG_SOFT_WATCHDOG is not set ++CONFIG_S3C2410_WATCHDOG=y ++ ++# # ++# # ISA-based Watchdog Cards ++# # ++# # CONFIG_PCWATCHDOG is not set ++# # CONFIG_MIXCOMWD is not set ++# # CONFIG_WDT is not set ++ ++# ++# Sonics Silicon Backplane ++# ++CONFIG_SSB_POSSIBLE=y ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++CONFIG_FB_S3C=y ++CONFIG_FB_S3C_LTE480WV=y ++# CONFIG_FB_S3C_LTV350QV is not set ++# CONFIG_FB_S3C_LTS222QV is not set ++CONFIG_FB_S3C_BPP=y ++# CONFIG_FB_S3C_BPP_8 is not set ++CONFIG_FB_S3C_BPP_16=y ++# CONFIG_FB_S3C_BPP_24 is not set ++# CONFIG_FB_S3C_BPP_32 is not set ++CONFIG_FB_S3C_NUM=1 ++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set ++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++# CONFIG_LOGO_LINUX_CLUT224 is not set ++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++CONFIG_SND_ARM=y ++CONFIG_SND_SOC=y ++ ++# ++# SoC Audio for the Samsung S3C ++# ++CONFIG_SND_S3C64XX_SOC=y ++CONFIG_SND_S3C6410_SOC_I2S=y ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713 is not set ++CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8580=y ++CONFIG_SOUND_WM8580_INPUT_STREAM_LINE=y ++# CONFIG_SOUND_WM8580_INPUT_STREAM_MIC is not set ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990 is not set ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM8580=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++# CONFIG_HID_PID is not set ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_BRIGHT=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_DELL=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++CONFIG_USB_DEVICE_CLASS=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_DPCM is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++# CONFIG_USB_GADGET_S3C_OTGD is not set ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FILE_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++CONFIG_SDIO_UART=y ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_S3C=y ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_NEW_LEDS is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++CONFIG_EXT3_FS_POSIX_ACL=y ++CONFIG_EXT3_FS_SECURITY=y ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++CONFIG_GENERIC_ACL=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_CRAMFS=y ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++CONFIG_ROMFS_FS=y ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++# CONFIG_NFS_V4 is not set ++CONFIG_ROOT_NFS=y ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_ACL_SUPPORT=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_BSD_DISKLABEL=y ++# CONFIG_MINIX_SUBPARTITION is not set ++CONFIG_SOLARIS_X86_PARTITION=y ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++# CONFIG_EFI_PARTITION is not set ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_UTF8 is not set ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_PI_LIST=y ++# CONFIG_RT_MUTEX_TESTER is not set ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++CONFIG_DEBUG_SPINLOCK_SLEEP=y ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_DEBUG_USER=y ++CONFIG_DEBUG_ERRORS=y ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++CONFIG_DEBUG_S3C_PORT=y ++CONFIG_DEBUG_S3C_UART=0 ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++# CONFIG_CRYPTO_MANAGER is not set ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++# CONFIG_CRYPTO_MD5 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++# CONFIG_CRC_CCITT is not set ++# CONFIG_CRC16 is not set ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_DMA=y +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/configs/smdk6410onenand_defconfig linux-2.6.28.6/arch/arm/configs/smdk6410onenand_defconfig +--- linux-2.6.28/arch/arm/configs/smdk6410onenand_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/configs/smdk6410onenand_defconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,1267 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28-rc8 ++# Thu Jan 15 18:17:50 2009 ++# ++CONFIG_ARM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++CONFIG_NO_IOPORT=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++CONFIG_LOCALVERSION_AUTO=y ++CONFIG_SWAP=y ++# CONFIG_SYSVIPC is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_COMPAT_BRK=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++CONFIG_LSF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_CLASSIC_RCU=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++CONFIG_ARCH_S3C64XX=y ++# CONFIG_ARCH_S5P64XX is not set ++# CONFIG_ARCH_S5PC1XX is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_PLAT_S3C64XX=y ++CONFIG_CPU_S3C6400_INIT=y ++CONFIG_CPU_S3C6400_CLOCK=y ++CONFIG_S3C64XX_SETUP_I2C0=y ++CONFIG_S3C64XX_SETUP_I2C1=y ++# CONFIG_S3C64XX_ADC is not set ++CONFIG_PLAT_S3C=y ++ ++# ++# Boot options ++# ++CONFIG_S3C_BOOT_ERROR_RESET=y ++ ++# ++# Power management ++# ++CONFIG_S3C_LOWLEVEL_UART_PORT=0 ++CONFIG_SPLIT_ROOT_FILESYSTEM=y ++CONFIG_S3C_GPIO_SPACE=0 ++CONFIG_S3C_GPIO_TRACK=y ++CONFIG_S3C_GPIO_PULL_UPDOWN=y ++CONFIG_S3C_GPIO_CFG_S3C24XX=y ++CONFIG_S3C_GPIO_CFG_S3C64XX=y ++CONFIG_S3C_DEV_HSMMC=y ++CONFIG_S3C_DEV_HSMMC1=y ++CONFIG_S3C_DEV_I2C1=y ++CONFIG_S3C_DMA_PL080=y ++CONFIG_CPU_S3C6410=y ++CONFIG_S3C6410_SETUP_SDHCI=y ++CONFIG_MACH_SMDK6410=y ++CONFIG_SMDK6410_SD_CH0=y ++# CONFIG_SMDK6410_SD_CH1 is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++CONFIG_ARM_THUMB=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++CONFIG_ARM_VIC=y ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=200 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_CMDLINE="root=/dev/mtdblock2 rw rootfstype=jffs2 init=/linuxrc console=ttySAC0,115200 mem=128M" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_FREQ is not set ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++# CONFIG_FPE_NWFPE is not set ++# CONFIG_FPE_FASTFPE is not set ++# CONFIG_VFP is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++ ++# ++# Power management options ++# ++# CONFIG_PM is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_NET is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_CONCAT is not set ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++# CONFIG_MTD_NAND is not set ++CONFIG_MTD_ONENAND=y ++CONFIG_MTD_ONENAND_VERIFY_WRITE=y ++CONFIG_MTD_ONENAND_GENERIC=y ++# CONFIG_MTD_ONENAND_OTP is not set ++# CONFIG_MTD_ONENAND_2X_PROGRAM is not set ++# CONFIG_MTD_ONENAND_SIM is not set ++ ++# ++# UBI - Unsorted block images ++# ++# CONFIG_MTD_UBI is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=8192 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++# CONFIG_SCSI_MULTI_LUN is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_GPIO is not set ++# CONFIG_KEYPAD_S3C is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_LIFEBOOK=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_S3C=y ++CONFIG_TOUCHSCREEN_NEW=y ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++CONFIG_SERIAL_8250=y ++# CONFIG_SERIAL_8250_CONSOLE is not set ++CONFIG_SERIAL_8250_NR_UARTS=4 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=4 ++# CONFIG_SERIAL_8250_EXTENDED is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_SAMSUNG=y ++CONFIG_SERIAL_SAMSUNG_UARTS=4 ++# CONFIG_SERIAL_SAMSUNG_DEBUG is not set ++CONFIG_SERIAL_SAMSUNG_CONSOLE=y ++CONFIG_SERIAL_S3C6400=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_S3C_MEM=y ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++CONFIG_I2C_S3C2410=y ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++CONFIG_AT24=y ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++# CONFIG_DEBUG_GPIO is not set ++# CONFIG_GPIO_SYSFS is not set ++ ++# ++# Memory mapped GPIO expanders: ++# ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++CONFIG_HWMON=y ++# CONFIG_HWMON_VID is not set ++# CONFIG_SENSORS_AD7414 is not set ++# CONFIG_SENSORS_AD7418 is not set ++# CONFIG_SENSORS_ADM1021 is not set ++# CONFIG_SENSORS_ADM1025 is not set ++# CONFIG_SENSORS_ADM1026 is not set ++# CONFIG_SENSORS_ADM1029 is not set ++# CONFIG_SENSORS_ADM1031 is not set ++# CONFIG_SENSORS_ADM9240 is not set ++# CONFIG_SENSORS_ADT7462 is not set ++# CONFIG_SENSORS_ADT7470 is not set ++# CONFIG_SENSORS_ADT7473 is not set ++# CONFIG_SENSORS_ATXP1 is not set ++# CONFIG_SENSORS_DS1621 is not set ++# CONFIG_SENSORS_F71805F is not set ++# CONFIG_SENSORS_F71882FG is not set ++# CONFIG_SENSORS_F75375S is not set ++# CONFIG_SENSORS_GL518SM is not set ++# CONFIG_SENSORS_GL520SM is not set ++# CONFIG_SENSORS_IT87 is not set ++# CONFIG_SENSORS_LM63 is not set ++# CONFIG_SENSORS_LM75 is not set ++# CONFIG_SENSORS_LM77 is not set ++# CONFIG_SENSORS_LM78 is not set ++# CONFIG_SENSORS_LM80 is not set ++# CONFIG_SENSORS_LM83 is not set ++# CONFIG_SENSORS_LM85 is not set ++# CONFIG_SENSORS_LM87 is not set ++# CONFIG_SENSORS_LM90 is not set ++# CONFIG_SENSORS_LM92 is not set ++# CONFIG_SENSORS_LM93 is not set ++# CONFIG_SENSORS_MAX1619 is not set ++# CONFIG_SENSORS_MAX6650 is not set ++# CONFIG_SENSORS_PC87360 is not set ++# CONFIG_SENSORS_PC87427 is not set ++# CONFIG_SENSORS_DME1737 is not set ++# CONFIG_SENSORS_SMSC47M1 is not set ++# CONFIG_SENSORS_SMSC47M192 is not set ++# CONFIG_SENSORS_SMSC47B397 is not set ++# CONFIG_SENSORS_ADS7828 is not set ++# CONFIG_SENSORS_THMC50 is not set ++# CONFIG_SENSORS_VT1211 is not set ++# CONFIG_SENSORS_W83781D is not set ++# CONFIG_SENSORS_W83791D is not set ++# CONFIG_SENSORS_W83792D is not set ++# CONFIG_SENSORS_W83793 is not set ++# CONFIG_SENSORS_W83L785TS is not set ++# CONFIG_SENSORS_W83L786NG is not set ++# CONFIG_SENSORS_W83627HF is not set ++# CONFIG_SENSORS_W83627EHF is not set ++# CONFIG_HWMON_DEBUG_CHIP is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# # ++# # Watchdog Device Drivers ++# # ++# # CONFIG_SOFT_WATCHDOG is not set ++CONFIG_S3C2410_WATCHDOG=y ++ ++# # ++# # ISA-based Watchdog Cards ++# # ++# # CONFIG_PCWATCHDOG is not set ++# # CONFIG_MIXCOMWD is not set ++# # CONFIG_WDT is not set ++ ++# ++# Sonics Silicon Backplane ++# ++CONFIG_SSB_POSSIBLE=y ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++CONFIG_FB_S3C=y ++CONFIG_FB_S3C_LTE480WV=y ++# CONFIG_FB_S3C_LTV350QV is not set ++# CONFIG_FB_S3C_LTS222QV is not set ++CONFIG_FB_S3C_BPP=y ++# CONFIG_FB_S3C_BPP_8 is not set ++CONFIG_FB_S3C_BPP_16=y ++# CONFIG_FB_S3C_BPP_24 is not set ++# CONFIG_FB_S3C_BPP_32 is not set ++CONFIG_FB_S3C_NUM=1 ++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set ++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++# CONFIG_LOGO_LINUX_CLUT224 is not set ++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++CONFIG_SND_ARM=y ++CONFIG_SND_SOC=y ++ ++# ++# SoC Audio for the Samsung S3C ++# ++CONFIG_SND_S3C64XX_SOC=y ++CONFIG_SND_S3C6410_SOC_I2S=y ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713 is not set ++CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8580=y ++CONFIG_SOUND_WM8580_INPUT_STREAM_LINE=y ++# CONFIG_SOUND_WM8580_INPUT_STREAM_MIC is not set ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990 is not set ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM8580=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++# CONFIG_HID_PID is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_BRIGHT=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_DELL=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++CONFIG_USB_DEVICE_CLASS=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_DPCM is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++# CONFIG_USB_GADGET_S3C_OTGD is not set ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FILE_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++CONFIG_SDIO_UART=y ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_S3C=y ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_NEW_LEDS is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++CONFIG_EXT3_FS_POSIX_ACL=y ++CONFIG_EXT3_FS_SECURITY=y ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++CONFIG_GENERIC_ACL=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++CONFIG_JFFS2_FS_WRITEBUFFER=y ++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++CONFIG_JFFS2_COMPRESSION_OPTIONS=y ++CONFIG_JFFS2_ZLIB=y ++CONFIG_JFFS2_LZO=y ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++# CONFIG_JFFS2_CMODE_NONE is not set ++CONFIG_JFFS2_CMODE_PRIORITY=y ++# CONFIG_JFFS2_CMODE_SIZE is not set ++# CONFIG_JFFS2_CMODE_FAVOURLZO is not set ++CONFIG_CRAMFS=y ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++CONFIG_ROMFS_FS=y ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_UTF8 is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_PI_LIST=y ++# CONFIG_RT_MUTEX_TESTER is not set ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++CONFIG_DEBUG_SPINLOCK_SLEEP=y ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_DEBUG_USER=y ++CONFIG_DEBUG_ERRORS=y ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++CONFIG_DEBUG_S3C_PORT=y ++CONFIG_DEBUG_S3C_UART=0 ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++# CONFIG_CRYPTO is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++# CONFIG_CRC_CCITT is not set ++# CONFIG_CRC16 is not set ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_DMA=y +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/configs/smdk6410ramdisk_defconfig linux-2.6.28.6/arch/arm/configs/smdk6410ramdisk_defconfig +--- linux-2.6.28/arch/arm/configs/smdk6410ramdisk_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/configs/smdk6410ramdisk_defconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,1124 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28-rc4 ++# Tue Nov 25 12:52:51 2008 ++# ++CONFIG_ARM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++CONFIG_NO_IOPORT=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++CONFIG_LOCALVERSION_AUTO=y ++CONFIG_SWAP=y ++# CONFIG_SYSVIPC is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_COMPAT_BRK=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++CONFIG_LSF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_CLASSIC_RCU=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++CONFIG_ARCH_S3C64XX=y ++# CONFIG_ARCH_S5PC1XX is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_PLAT_S3C64XX=y ++CONFIG_CPU_S3C6400_INIT=y ++CONFIG_CPU_S3C6400_CLOCK=y ++CONFIG_S3C64XX_SETUP_I2C0=y ++CONFIG_S3C64XX_SETUP_I2C1=y ++CONFIG_PLAT_S3C=y ++ ++# ++# Boot options ++# ++CONFIG_S3C_BOOT_ERROR_RESET=y ++ ++# ++# Power management ++# ++CONFIG_S3C_LOWLEVEL_UART_PORT=0 ++CONFIG_S3C_GPIO_SPACE=0 ++CONFIG_S3C_GPIO_TRACK=y ++CONFIG_S3C_GPIO_PULL_UPDOWN=y ++CONFIG_S3C_GPIO_CFG_S3C24XX=y ++CONFIG_S3C_GPIO_CFG_S3C64XX=y ++CONFIG_S3C_DEV_HSMMC=y ++CONFIG_S3C_DEV_HSMMC1=y ++CONFIG_S3C_DEV_I2C1=y ++CONFIG_CPU_S3C6410=y ++CONFIG_S3C6410_SETUP_SDHCI=y ++CONFIG_MACH_SMDK6410=y ++CONFIG_SMDK6410_SD_CH0=y ++# CONFIG_SMDK6410_SD_CH1 is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++CONFIG_ARM_THUMB=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++CONFIG_ARM_VIC=y ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=200 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x50800000,8M console=ttySAC0,115200 init=/linuxrc mem=128M" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++# CONFIG_FPE_NWFPE is not set ++# CONFIG_FPE_FASTFPE is not set ++CONFIG_VFP=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++ ++# ++# Power management options ++# ++# CONFIG_PM is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_NET is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_MTD is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=8192 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++# CONFIG_SCSI_MULTI_LUN is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_GPIO is not set ++# CONFIG_KEYPAD_S3C is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_LIFEBOOK=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_S3C=y ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++CONFIG_SERIAL_8250=y ++# CONFIG_SERIAL_8250_CONSOLE is not set ++CONFIG_SERIAL_8250_NR_UARTS=4 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=4 ++# CONFIG_SERIAL_8250_EXTENDED is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_SAMSUNG=y ++CONFIG_SERIAL_SAMSUNG_UARTS=4 ++# CONFIG_SERIAL_SAMSUNG_DEBUG is not set ++CONFIG_SERIAL_SAMSUNG_CONSOLE=y ++CONFIG_SERIAL_S3C6400=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_NVRAM is not set ++# CONFIG_S3C_ADC is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++CONFIG_I2C_S3C2410=y ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++CONFIG_AT24=y ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++# CONFIG_DEBUG_GPIO is not set ++# CONFIG_GPIO_SYSFS is not set ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++CONFIG_HWMON=y ++# CONFIG_HWMON_VID is not set ++# CONFIG_SENSORS_AD7414 is not set ++# CONFIG_SENSORS_AD7418 is not set ++# CONFIG_SENSORS_ADM1021 is not set ++# CONFIG_SENSORS_ADM1025 is not set ++# CONFIG_SENSORS_ADM1026 is not set ++# CONFIG_SENSORS_ADM1029 is not set ++# CONFIG_SENSORS_ADM1031 is not set ++# CONFIG_SENSORS_ADM9240 is not set ++# CONFIG_SENSORS_ADT7470 is not set ++# CONFIG_SENSORS_ADT7473 is not set ++# CONFIG_SENSORS_ATXP1 is not set ++# CONFIG_SENSORS_DS1621 is not set ++# CONFIG_SENSORS_F71805F is not set ++# CONFIG_SENSORS_F71882FG is not set ++# CONFIG_SENSORS_F75375S is not set ++# CONFIG_SENSORS_GL518SM is not set ++# CONFIG_SENSORS_GL520SM is not set ++# CONFIG_SENSORS_IT87 is not set ++# CONFIG_SENSORS_LM63 is not set ++# CONFIG_SENSORS_LM75 is not set ++# CONFIG_SENSORS_LM77 is not set ++# CONFIG_SENSORS_LM78 is not set ++# CONFIG_SENSORS_LM80 is not set ++# CONFIG_SENSORS_LM83 is not set ++# CONFIG_SENSORS_LM85 is not set ++# CONFIG_SENSORS_LM87 is not set ++# CONFIG_SENSORS_LM90 is not set ++# CONFIG_SENSORS_LM92 is not set ++# CONFIG_SENSORS_LM93 is not set ++# CONFIG_SENSORS_MAX1619 is not set ++# CONFIG_SENSORS_MAX6650 is not set ++# CONFIG_SENSORS_PC87360 is not set ++# CONFIG_SENSORS_PC87427 is not set ++# CONFIG_SENSORS_DME1737 is not set ++# CONFIG_SENSORS_SMSC47M1 is not set ++# CONFIG_SENSORS_SMSC47M192 is not set ++# CONFIG_SENSORS_SMSC47B397 is not set ++# CONFIG_SENSORS_ADS7828 is not set ++# CONFIG_SENSORS_THMC50 is not set ++# CONFIG_SENSORS_VT1211 is not set ++# CONFIG_SENSORS_W83781D is not set ++# CONFIG_SENSORS_W83791D is not set ++# CONFIG_SENSORS_W83792D is not set ++# CONFIG_SENSORS_W83793 is not set ++# CONFIG_SENSORS_W83L785TS is not set ++# CONFIG_SENSORS_W83L786NG is not set ++# CONFIG_SENSORS_W83627HF is not set ++# CONFIG_SENSORS_W83627EHF is not set ++# CONFIG_HWMON_DEBUG_CHIP is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# # ++# # Watchdog Device Drivers ++# # ++# # CONFIG_SOFT_WATCHDOG is not set ++CONFIG_S3C2410_WATCHDOG=y ++ ++# # ++# # ISA-based Watchdog Cards ++# # ++# # CONFIG_PCWATCHDOG is not set ++# # CONFIG_MIXCOMWD is not set ++# # CONFIG_WDT is not set ++ ++# ++# Sonics Silicon Backplane ++# ++CONFIG_SSB_POSSIBLE=y ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++CONFIG_FB_S3C=y ++CONFIG_FB_S3C_LTE480WV=y ++# CONFIG_FB_S3C_LTV350QV is not set ++# CONFIG_FB_S3C_LTS222QV is not set ++CONFIG_FB_S3C_BPP=y ++# CONFIG_FB_S3C_BPP_8 is not set ++CONFIG_FB_S3C_BPP_16=y ++# CONFIG_FB_S3C_BPP_24 is not set ++# CONFIG_FB_S3C_BPP_32 is not set ++CONFIG_FB_S3C_NUM=1 ++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set ++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++# CONFIG_LOGO_LINUX_CLUT224 is not set ++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y ++# CONFIG_SOUND is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++# CONFIG_HID_PID is not set ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_BRIGHT=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_DELL=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++CONFIG_USB_DEVICE_CLASS=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_DPCM is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++# CONFIG_USB_GADGET_S3C_OTGD is not set ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FILE_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++CONFIG_SDIO_UART=y ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_S3C=y ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_NEW_LEDS is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++CONFIG_EXT3_FS_POSIX_ACL=y ++CONFIG_EXT3_FS_SECURITY=y ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++CONFIG_GENERIC_ACL=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_CRAMFS=y ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++CONFIG_ROMFS_FS=y ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_UTF8 is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_PI_LIST=y ++# CONFIG_RT_MUTEX_TESTER is not set ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++CONFIG_DEBUG_SPINLOCK_SLEEP=y ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_DEBUG_USER=y ++CONFIG_DEBUG_ERRORS=y ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++CONFIG_DEBUG_S3C_PORT=y ++CONFIG_DEBUG_S3C_UART=0 ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++# CONFIG_CRYPTO is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++# CONFIG_CRC_CCITT is not set ++# CONFIG_CRC16 is not set ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_DMA=y +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/configs/smdk6410rf_defconfig linux-2.6.28.6/arch/arm/configs/smdk6410rf_defconfig +--- linux-2.6.28/arch/arm/configs/smdk6410rf_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/configs/smdk6410rf_defconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,1040 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28-rc8 ++# Mon Feb 2 12:53:27 2009 ++# ++CONFIG_ARM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++CONFIG_NO_IOPORT=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++CONFIG_LOCALVERSION_AUTO=y ++CONFIG_SWAP=y ++# CONFIG_SYSVIPC is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_COMPAT_BRK=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++CONFIG_LSF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_CLASSIC_RCU=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++CONFIG_ARCH_S3C64XX=y ++# CONFIG_ARCH_S5P64XX is not set ++# CONFIG_ARCH_S5PC1XX is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_PLAT_S3C64XX=y ++CONFIG_CPU_S3C6400_INIT=y ++CONFIG_CPU_S3C6400_CLOCK=y ++CONFIG_S3C64XX_SETUP_I2C0=y ++CONFIG_S3C64XX_SETUP_I2C1=y ++# CONFIG_S3C64XX_ADC is not set ++CONFIG_PLAT_S3C=y ++ ++# ++# Boot options ++# ++CONFIG_S3C_BOOT_ERROR_RESET=y ++ ++# ++# Power management ++# ++CONFIG_S3C_LOWLEVEL_UART_PORT=0 ++CONFIG_SPLIT_ROOT_FILESYSTEM=y ++CONFIG_S3C_GPIO_SPACE=0 ++CONFIG_S3C_GPIO_TRACK=y ++CONFIG_S3C_GPIO_PULL_UPDOWN=y ++CONFIG_S3C_GPIO_CFG_S3C24XX=y ++CONFIG_S3C_GPIO_CFG_S3C64XX=y ++CONFIG_S3C_DEV_HSMMC=y ++CONFIG_S3C_DEV_HSMMC1=y ++CONFIG_S3C_DEV_I2C1=y ++CONFIG_S3C_DMA_PL080=y ++CONFIG_CPU_S3C6410=y ++CONFIG_S3C6410_SETUP_SDHCI=y ++CONFIG_MACH_SMDK6410=y ++CONFIG_SMDK6410_SD_CH0=y ++# CONFIG_SMDK6410_SD_CH1 is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++CONFIG_ARM_THUMB=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++CONFIG_ARM_VIC=y ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=200 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC0,115200 mem=128M" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_FREQ is not set ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++# CONFIG_FPE_NWFPE is not set ++# CONFIG_FPE_FASTFPE is not set ++# CONFIG_VFP is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++ ++# ++# Power management options ++# ++# CONFIG_PM is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_NET is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_CONCAT is not set ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_M25P80 is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_VERIFY_WRITE is not set ++# CONFIG_MTD_NAND_ECC_SMC is not set ++# CONFIG_MTD_NAND_MUSEUM_IDS is not set ++# CONFIG_MTD_NAND_GPIO is not set ++CONFIG_MTD_NAND_IDS=y ++CONFIG_MTD_NAND_S3C=y ++# CONFIG_MTD_NAND_S3C_DEBUG is not set ++CONFIG_MTD_NAND_S3C_HWECC=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# UBI - Unsorted block images ++# ++# CONFIG_MTD_UBI is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=8192 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++# CONFIG_SCSI is not set ++# CONFIG_SCSI_DMA is not set ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_GPIO is not set ++# CONFIG_KEYPAD_S3C is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_LIFEBOOK=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++# CONFIG_TOUCHSCREEN_ADS7846 is not set ++CONFIG_TOUCHSCREEN_S3C=y ++CONFIG_TOUCHSCREEN_NEW=y ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++CONFIG_SERIAL_8250=y ++# CONFIG_SERIAL_8250_CONSOLE is not set ++CONFIG_SERIAL_8250_NR_UARTS=4 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=4 ++# CONFIG_SERIAL_8250_EXTENDED is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_SAMSUNG=y ++CONFIG_SERIAL_SAMSUNG_UARTS=4 ++# CONFIG_SERIAL_SAMSUNG_DEBUG is not set ++CONFIG_SERIAL_SAMSUNG_CONSOLE=y ++CONFIG_SERIAL_S3C6400=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_S3C_MEM=y ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++CONFIG_I2C_S3C2410=y ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++CONFIG_AT24=y ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_BITBANG is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_AT25 is not set ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_TLE62X0 is not set ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++# CONFIG_DEBUG_GPIO is not set ++# CONFIG_GPIO_SYSFS is not set ++ ++# ++# Memory mapped GPIO expanders: ++# ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MCP23S08 is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++CONFIG_HWMON=y ++# CONFIG_HWMON_VID is not set ++# CONFIG_SENSORS_AD7414 is not set ++# CONFIG_SENSORS_AD7418 is not set ++# CONFIG_SENSORS_ADCXX is not set ++# CONFIG_SENSORS_ADM1021 is not set ++# CONFIG_SENSORS_ADM1025 is not set ++# CONFIG_SENSORS_ADM1026 is not set ++# CONFIG_SENSORS_ADM1029 is not set ++# CONFIG_SENSORS_ADM1031 is not set ++# CONFIG_SENSORS_ADM9240 is not set ++# CONFIG_SENSORS_ADT7462 is not set ++# CONFIG_SENSORS_ADT7470 is not set ++# CONFIG_SENSORS_ADT7473 is not set ++# CONFIG_SENSORS_ATXP1 is not set ++# CONFIG_SENSORS_DS1621 is not set ++# CONFIG_SENSORS_F71805F is not set ++# CONFIG_SENSORS_F71882FG is not set ++# CONFIG_SENSORS_F75375S is not set ++# CONFIG_SENSORS_GL518SM is not set ++# CONFIG_SENSORS_GL520SM is not set ++# CONFIG_SENSORS_IT87 is not set ++# CONFIG_SENSORS_LM63 is not set ++# CONFIG_SENSORS_LM70 is not set ++# CONFIG_SENSORS_LM75 is not set ++# CONFIG_SENSORS_LM77 is not set ++# CONFIG_SENSORS_LM78 is not set ++# CONFIG_SENSORS_LM80 is not set ++# CONFIG_SENSORS_LM83 is not set ++# CONFIG_SENSORS_LM85 is not set ++# CONFIG_SENSORS_LM87 is not set ++# CONFIG_SENSORS_LM90 is not set ++# CONFIG_SENSORS_LM92 is not set ++# CONFIG_SENSORS_LM93 is not set ++# CONFIG_SENSORS_MAX1111 is not set ++# CONFIG_SENSORS_MAX1619 is not set ++# CONFIG_SENSORS_MAX6650 is not set ++# CONFIG_SENSORS_PC87360 is not set ++# CONFIG_SENSORS_PC87427 is not set ++# CONFIG_SENSORS_DME1737 is not set ++# CONFIG_SENSORS_SMSC47M1 is not set ++# CONFIG_SENSORS_SMSC47M192 is not set ++# CONFIG_SENSORS_SMSC47B397 is not set ++# CONFIG_SENSORS_ADS7828 is not set ++# CONFIG_SENSORS_THMC50 is not set ++# CONFIG_SENSORS_VT1211 is not set ++# CONFIG_SENSORS_W83781D is not set ++# CONFIG_SENSORS_W83791D is not set ++# CONFIG_SENSORS_W83792D is not set ++# CONFIG_SENSORS_W83793 is not set ++# CONFIG_SENSORS_W83L785TS is not set ++# CONFIG_SENSORS_W83L786NG is not set ++# CONFIG_SENSORS_W83627HF is not set ++# CONFIG_SENSORS_W83627EHF is not set ++# CONFIG_HWMON_DEBUG_CHIP is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++# CONFIG_FB is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++CONFIG_SND_ARM=y ++CONFIG_SND_SPI=y ++CONFIG_SND_SOC=y ++ ++# ++# SoC Audio for the Samsung S3C ++# ++CONFIG_SND_S3C64XX_SOC=y ++CONFIG_SND_S3C6410_SOC_I2S_V32=y ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713 is not set ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8580 is not set ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990 is not set ++CONFIG_SND_S3C64XX_SOC_SMDK6410_S5M8751=y ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_S5M8751=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++# CONFIG_HID_PID is not set ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++# CONFIG_USB_ARCH_HAS_OHCI is not set ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++# CONFIG_USB is not set ++ ++# ++# Enable Host or Gadget support to see Inventra options ++# ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++# CONFIG_USB_GADGET is not set ++CONFIG_MMC=y ++CONFIG_MMC_DEBUG=y ++CONFIG_MMC_UNSAFE_RESUME=y ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++CONFIG_SDIO_UART=y ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_S3C=y ++# CONFIG_MMC_SPI is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_NEW_LEDS is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++CONFIG_EXT3_FS_POSIX_ACL=y ++CONFIG_EXT3_FS_SECURITY=y ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++CONFIG_GENERIC_ACL=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++# CONFIG_MSDOS_FS is not set ++# CONFIG_VFAT_FS is not set ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_JFFS2_FS is not set ++CONFIG_CRAMFS=y ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++CONFIG_ROMFS_FS=y ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_UTF8 is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_PI_LIST=y ++# CONFIG_RT_MUTEX_TESTER is not set ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++CONFIG_DEBUG_SPINLOCK_SLEEP=y ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_DEBUG_USER=y ++CONFIG_DEBUG_ERRORS=y ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++CONFIG_DEBUG_S3C_PORT=y ++CONFIG_DEBUG_S3C_UART=0 ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++# CONFIG_CRYPTO is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++# CONFIG_CRC_CCITT is not set ++# CONFIG_CRC16 is not set ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_DMA=y +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/configs/smdk6440ramdisk_defconfig linux-2.6.28.6/arch/arm/configs/smdk6440ramdisk_defconfig +--- linux-2.6.28/arch/arm/configs/smdk6440ramdisk_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/configs/smdk6440ramdisk_defconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,1285 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28.6 ++# Sat Apr 4 19:51:52 2009 ++# ++CONFIG_ARM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++CONFIG_NO_IOPORT=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++CONFIG_LOCALVERSION_AUTO=y ++CONFIG_SWAP=y ++# CONFIG_SYSVIPC is not set ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_COMPAT_BRK=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++CONFIG_LSF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_CLASSIC_RCU=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++# CONFIG_ARCH_S3C64XX is not set ++CONFIG_ARCH_S5P64XX=y ++# CONFIG_ARCH_S5PC1XX is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_PLAT_S5P64XX=y ++CONFIG_CPU_S5P6440_INIT=y ++CONFIG_CPU_S5P6440_CLOCK=y ++CONFIG_S5P64XX_SETUP_I2C0=y ++CONFIG_S5P64XX_SETUP_I2C1=y ++CONFIG_PLAT_S3C=y ++# CONFIG_HAVE_PWM is not set ++# ++# Boot options ++# ++CONFIG_S3C_BOOT_ERROR_RESET=y ++ ++# ++# Power management ++# ++CONFIG_S3C_LOWLEVEL_UART_PORT=1 ++CONFIG_S3C_GPIO_SPACE=0 ++CONFIG_S3C_GPIO_TRACK=y ++CONFIG_S3C_GPIO_PULL_UPDOWN=y ++CONFIG_S3C_GPIO_CFG_S3C24XX=y ++CONFIG_S3C_GPIO_CFG_S3C64XX=y ++CONFIG_S3C_DEV_HSMMC=y ++CONFIG_S3C_DEV_HSMMC1=y ++CONFIG_S3C_DEV_I2C1=y ++CONFIG_S3C_DMA_PL330=y ++CONFIG_CPU_S5P6440=y ++CONFIG_S5P6440_SETUP_SDHCI=y ++CONFIG_MACH_SMDK6440=y ++CONFIG_SMDK6440_SD_CH0=y ++# CONFIG_SMDK6440_SD_CH1 is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++CONFIG_ARM_THUMB=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++CONFIG_ARM_VIC=y ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=200 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc mem=256M" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++# CONFIG_FPE_NWFPE is not set ++# CONFIG_FPE_FASTFPE is not set ++CONFIG_VFP=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++ ++# ++# Power management options ++# ++# CONFIG_PM is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_PACKET is not set ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++CONFIG_IP_PNP_BOOTP=y ++# CONFIG_IP_PNP_RARP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++CONFIG_INET_XFRM_MODE_TRANSPORT=y ++CONFIG_INET_XFRM_MODE_TUNNEL=y ++CONFIG_INET_XFRM_MODE_BEET=y ++# CONFIG_INET_LRO is not set ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++# CONFIG_MTD is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=8192 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++# CONFIG_SCSI_MULTI_LUN is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_PHYLIB is not set ++CONFIG_NET_ETHERNET=y ++# CONFIG_MII is not set ++# CONFIG_AX88796 is not set ++# CONFIG_SMC91X is not set ++# CONFIG_DM9000 is not set ++# CONFIG_SMC911X is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++CONFIG_NETDEV_1000=y ++CONFIG_NETDEV_10000=y ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++# CONFIG_WAN is not set ++CONFIG_PPP=y ++CONFIG_PPP_MULTILINK=y ++CONFIG_PPP_FILTER=y ++CONFIG_PPP_ASYNC=y ++CONFIG_PPP_SYNC_TTY=y ++# CONFIG_PPP_DEFLATE is not set ++# CONFIG_PPP_BSDCOMP is not set ++# CONFIG_PPP_MPPE is not set ++# CONFIG_PPPOE is not set ++# CONFIG_PPPOL2TP is not set ++# CONFIG_SLIP is not set ++CONFIG_SLHC=y ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_GPIO is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_LIFEBOOK=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_S3C=y ++CONFIG_TOUCHSCREEN_NEW=y ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++CONFIG_SERIAL_8250=y ++# CONFIG_SERIAL_8250_CONSOLE is not set ++CONFIG_SERIAL_8250_NR_UARTS=4 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=4 ++# CONFIG_SERIAL_8250_EXTENDED is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_SAMSUNG=y ++CONFIG_SERIAL_SAMSUNG_UARTS=4 ++# CONFIG_SERIAL_SAMSUNG_DEBUG is not set ++CONFIG_SERIAL_SAMSUNG_CONSOLE=y ++CONFIG_SERIAL_S3C6400=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_S3C_MEM=y ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++CONFIG_I2C_S3C2410=y ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++CONFIG_AT24=y ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++# CONFIG_DEBUG_GPIO is not set ++# CONFIG_GPIO_SYSFS is not set ++ ++# ++# Memory mapped GPIO expanders: ++# ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++CONFIG_HWMON=y ++# CONFIG_HWMON_VID is not set ++# CONFIG_SENSORS_AD7414 is not set ++# CONFIG_SENSORS_AD7418 is not set ++# CONFIG_SENSORS_ADM1021 is not set ++# CONFIG_SENSORS_ADM1025 is not set ++# CONFIG_SENSORS_ADM1026 is not set ++# CONFIG_SENSORS_ADM1029 is not set ++# CONFIG_SENSORS_ADM1031 is not set ++# CONFIG_SENSORS_ADM9240 is not set ++# CONFIG_SENSORS_ADT7462 is not set ++# CONFIG_SENSORS_ADT7470 is not set ++# CONFIG_SENSORS_ADT7473 is not set ++# CONFIG_SENSORS_ATXP1 is not set ++# CONFIG_SENSORS_DS1621 is not set ++# CONFIG_SENSORS_F71805F is not set ++# CONFIG_SENSORS_F71882FG is not set ++# CONFIG_SENSORS_F75375S is not set ++# CONFIG_SENSORS_GL518SM is not set ++# CONFIG_SENSORS_GL520SM is not set ++# CONFIG_SENSORS_IT87 is not set ++# CONFIG_SENSORS_LM63 is not set ++# CONFIG_SENSORS_LM75 is not set ++# CONFIG_SENSORS_LM77 is not set ++# CONFIG_SENSORS_LM78 is not set ++# CONFIG_SENSORS_LM80 is not set ++# CONFIG_SENSORS_LM83 is not set ++# CONFIG_SENSORS_LM85 is not set ++# CONFIG_SENSORS_LM87 is not set ++# CONFIG_SENSORS_LM90 is not set ++# CONFIG_SENSORS_LM92 is not set ++# CONFIG_SENSORS_LM93 is not set ++# CONFIG_SENSORS_MAX1619 is not set ++# CONFIG_SENSORS_MAX6650 is not set ++# CONFIG_SENSORS_PC87360 is not set ++# CONFIG_SENSORS_PC87427 is not set ++# CONFIG_SENSORS_DME1737 is not set ++# CONFIG_SENSORS_SMSC47M1 is not set ++# CONFIG_SENSORS_SMSC47M192 is not set ++# CONFIG_SENSORS_SMSC47B397 is not set ++# CONFIG_SENSORS_ADS7828 is not set ++# CONFIG_SENSORS_THMC50 is not set ++# CONFIG_SENSORS_VT1211 is not set ++# CONFIG_SENSORS_W83781D is not set ++# CONFIG_SENSORS_W83791D is not set ++# CONFIG_SENSORS_W83792D is not set ++# CONFIG_SENSORS_W83793 is not set ++# CONFIG_SENSORS_W83L785TS is not set ++# CONFIG_SENSORS_W83L786NG is not set ++# CONFIG_SENSORS_W83627HF is not set ++# CONFIG_SENSORS_W83627EHF is not set ++# CONFIG_HWMON_DEBUG_CHIP is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++CONFIG_FB_S3C=y ++CONFIG_FB_S3C_LTE480WV=y ++# CONFIG_FB_S3C_LTV350QV is not set ++# CONFIG_FB_S3C_LTS222QV is not set ++CONFIG_FB_S3C_BPP=y ++# CONFIG_FB_S3C_BPP_8 is not set ++CONFIG_FB_S3C_BPP_16=y ++# CONFIG_FB_S3C_BPP_24 is not set ++# CONFIG_FB_S3C_BPP_28 is not set ++# CONFIG_FB_S3C_BPP_32 is not set ++CONFIG_FB_S3C_NUM=1 ++CONFIG_FB_S3C_VIRTUAL_SCREEN=y ++CONFIG_FB_S3C_DOUBLE_BUFFERING=y ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++CONFIG_BACKLIGHT_LCD_SUPPORT=y ++CONFIG_BACKLIGHT_CLASS_DEVICE=y ++CONFIG_BACKLIGHT_PWM=y ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++# CONFIG_LOGO_LINUX_CLUT224 is not set ++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++CONFIG_SND_ARM=y ++CONFIG_SND_SOC=y ++ ++# ++# SoC Audio for the Samsung S3C ++# ++CONFIG_SND_S5P64XX_SOC=y ++CONFIG_SND_S5P6440_SOC_I2S=y ++CONFIG_SND_S5P64XX_SOC_SMDK6440_WM8580=y ++CONFIG_SOUND_SMDK6440_WM8580_INPUT_STREAM_LINE=y ++# CONFIG_SOUND_SMDK6440_WM8580_INPUT_STREAM_MIC is not set ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM8580=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++# CONFIG_HID_PID is not set ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++# CONFIG_USB_ARCH_HAS_OHCI is not set ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++# CONFIG_USB is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++CONFIG_USB_GADGET_S3C_OTGD=y ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++ ++# ++# NOTE: S3C OTG device role enables the controller driver below ++# ++CONFIG_USB_S3C_OTGD=y ++CONFIG_USB_GADGET_S3C_OTGD_DMA_MODE=y ++# CONFIG_USB_GADGET_S3C_OTGD_SLAVE_MODE is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++CONFIG_USB_ETH=m ++CONFIG_USB_ETH_RNDIS=y ++# CONFIG_USB_GADGETFS is not set ++CONFIG_USB_FILE_STORAGE=m ++# CONFIG_USB_FILE_STORAGE_TEST is not set ++CONFIG_USB_G_SERIAL=m ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++CONFIG_MMC_DEBUG=y ++CONFIG_MMC_UNSAFE_RESUME=y ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++CONFIG_SDIO_UART=y ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++CONFIG_MMC_SDHCI=y ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_NEW_LEDS is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++CONFIG_EXT3_FS_POSIX_ACL=y ++CONFIG_EXT3_FS_SECURITY=y ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++CONFIG_GENERIC_ACL=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_CRAMFS=y ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++CONFIG_ROMFS_FS=y ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++# CONFIG_NFS_V3_ACL is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_ROOT_NFS is not set ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_UTF8 is not set ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_PI_LIST=y ++# CONFIG_RT_MUTEX_TESTER is not set ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++CONFIG_DEBUG_SPINLOCK_SLEEP=y ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_DEBUG_USER=y ++CONFIG_DEBUG_ERRORS=y ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++CONFIG_DEBUG_S3C_PORT=y ++CONFIG_DEBUG_S3C_UART=1 ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++# CONFIG_CRYPTO_MANAGER is not set ++# CONFIG_CRYPTO_MANAGER2 is not set ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++# CONFIG_CRYPTO_MD5 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_CRC_CCITT=y ++# CONFIG_CRC16 is not set ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_DMA=y +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/configs/smdkc100_defconfig linux-2.6.28.6/arch/arm/configs/smdkc100_defconfig +--- linux-2.6.28/arch/arm/configs/smdkc100_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/configs/smdkc100_defconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,947 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28-rc7 ++# Thu Dec 11 15:31:22 2008 ++# ++CONFIG_ARM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++CONFIG_NO_IOPORT=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++CONFIG_LOCALVERSION_AUTO=y ++CONFIG_SWAP=y ++# CONFIG_SYSVIPC is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_COMPAT_BRK=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++CONFIG_LSF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_CLASSIC_RCU=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++# CONFIG_ARCH_S3C64XX is not set ++CONFIG_ARCH_S5PC1XX=y ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_S3C64XX_SETUP_I2C1=y ++CONFIG_PLAT_S5PC1XX=y ++CONFIG_CPU_S5PC100_INIT=y ++CONFIG_CPU_S5PC100_CLOCK=y ++CONFIG_S5PC1XX_SETUP_I2C0=y ++CONFIG_S5PC1XX_SETUP_I2C1=y ++CONFIG_PLAT_S3C=y ++ ++# ++# Boot options ++# ++# CONFIG_S3C_BOOT_ERROR_RESET is not set ++ ++# ++# Power management ++# ++CONFIG_S3C_LOWLEVEL_UART_PORT=0 ++CONFIG_S3C_GPIO_SPACE=0 ++CONFIG_S3C_GPIO_TRACK=y ++CONFIG_S3C_GPIO_PULL_UPDOWN=y ++CONFIG_S3C_GPIO_CFG_S5PC1XX=y ++CONFIG_S3C_DEV_I2C1=y ++CONFIG_S3C_DMA_PL330=y ++CONFIG_CPU_S5PC100=y ++CONFIG_MACH_SMDKC100=y ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_IFAR=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++CONFIG_ARM_THUMB=y ++# CONFIG_ARM_THUMBEE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_HAS_TLS_REG=y ++# CONFIG_OUTER_CACHE is not set ++CONFIG_ARM_VIC=y ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=200 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC0,115200 init=/linuxrc mem=128M" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++# CONFIG_FPE_NWFPE is not set ++# CONFIG_FPE_FASTFPE is not set ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++# CONFIG_NEON is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++ ++# ++# Power management options ++# ++# CONFIG_PM is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_NET is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_MTD is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=8192 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++# CONFIG_SCSI is not set ++# CONFIG_SCSI_DMA is not set ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_GPIO is not set ++# CONFIG_KEYPAD_S3C is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_LIFEBOOK=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_S3C=y ++CONFIG_TOUCHSCREEN_NEW=y ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++CONFIG_SERIAL_8250=y ++# CONFIG_SERIAL_8250_CONSOLE is not set ++CONFIG_SERIAL_8250_NR_UARTS=4 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=4 ++# CONFIG_SERIAL_8250_EXTENDED is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_SAMSUNG=y ++CONFIG_SERIAL_SAMSUNG_UARTS=4 ++# CONFIG_SERIAL_SAMSUNG_DEBUG is not set ++CONFIG_SERIAL_SAMSUNG_CONSOLE=y ++CONFIG_SERIAL_S5PC100=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_S3C_MEM=y ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++CONFIG_I2C_S3C2410=y ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++CONFIG_AT24=y ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++# CONFIG_DEBUG_GPIO is not set ++# CONFIG_GPIO_SYSFS is not set ++ ++# ++# Memory mapped GPIO expanders: ++# ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++CONFIG_HWMON=y ++# CONFIG_HWMON_VID is not set ++# CONFIG_SENSORS_AD7414 is not set ++# CONFIG_SENSORS_AD7418 is not set ++# CONFIG_SENSORS_ADM1021 is not set ++# CONFIG_SENSORS_ADM1025 is not set ++# CONFIG_SENSORS_ADM1026 is not set ++# CONFIG_SENSORS_ADM1029 is not set ++# CONFIG_SENSORS_ADM1031 is not set ++# CONFIG_SENSORS_ADM9240 is not set ++# CONFIG_SENSORS_ADT7462 is not set ++# CONFIG_SENSORS_ADT7470 is not set ++# CONFIG_SENSORS_ADT7473 is not set ++# CONFIG_SENSORS_ATXP1 is not set ++# CONFIG_SENSORS_DS1621 is not set ++# CONFIG_SENSORS_F71805F is not set ++# CONFIG_SENSORS_F71882FG is not set ++# CONFIG_SENSORS_F75375S is not set ++# CONFIG_SENSORS_GL518SM is not set ++# CONFIG_SENSORS_GL520SM is not set ++# CONFIG_SENSORS_IT87 is not set ++# CONFIG_SENSORS_LM63 is not set ++# CONFIG_SENSORS_LM75 is not set ++# CONFIG_SENSORS_LM77 is not set ++# CONFIG_SENSORS_LM78 is not set ++# CONFIG_SENSORS_LM80 is not set ++# CONFIG_SENSORS_LM83 is not set ++# CONFIG_SENSORS_LM85 is not set ++# CONFIG_SENSORS_LM87 is not set ++# CONFIG_SENSORS_LM90 is not set ++# CONFIG_SENSORS_LM92 is not set ++# CONFIG_SENSORS_LM93 is not set ++# CONFIG_SENSORS_MAX1619 is not set ++# CONFIG_SENSORS_MAX6650 is not set ++# CONFIG_SENSORS_PC87360 is not set ++# CONFIG_SENSORS_PC87427 is not set ++# CONFIG_SENSORS_DME1737 is not set ++# CONFIG_SENSORS_SMSC47M1 is not set ++# CONFIG_SENSORS_SMSC47M192 is not set ++# CONFIG_SENSORS_SMSC47B397 is not set ++# CONFIG_SENSORS_ADS7828 is not set ++# CONFIG_SENSORS_THMC50 is not set ++# CONFIG_SENSORS_VT1211 is not set ++# CONFIG_SENSORS_W83781D is not set ++# CONFIG_SENSORS_W83791D is not set ++# CONFIG_SENSORS_W83792D is not set ++# CONFIG_SENSORS_W83793 is not set ++# CONFIG_SENSORS_W83L785TS is not set ++# CONFIG_SENSORS_W83L786NG is not set ++# CONFIG_SENSORS_W83627HF is not set ++# CONFIG_SENSORS_W83627EHF is not set ++# CONFIG_HWMON_DEBUG_CHIP is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++CONFIG_FB_S3C=y ++CONFIG_FB_S3C_LTE480WV=y ++# CONFIG_FB_S3C_LTV350QV is not set ++# CONFIG_FB_S3C_LTS222QV is not set ++CONFIG_FB_S3C_BPP=y ++# CONFIG_FB_S3C_BPP_8 is not set ++CONFIG_FB_S3C_BPP_16=y ++# CONFIG_FB_S3C_BPP_24 is not set ++# CONFIG_FB_S3C_BPP_32 is not set ++CONFIG_FB_S3C_NUM=1 ++CONFIG_FB_S3C_VIRTUAL_SCREEN=y ++CONFIG_FB_S3C_DOUBLE_BUFFERING=y ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++# CONFIG_LOGO_LINUX_CLUT224 is not set ++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y ++# CONFIG_SOUND is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++# CONFIG_HID_PID is not set ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++# CONFIG_USB_ARCH_HAS_OHCI is not set ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++# CONFIG_USB is not set ++ ++# ++# Enable Host or Gadget support to see Inventra options ++# ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++# CONFIG_USB_GADGET is not set ++CONFIG_MMC=y ++CONFIG_MMC_DEBUG=y ++CONFIG_MMC_UNSAFE_RESUME=y ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++CONFIG_SDIO_UART=y ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++CONFIG_MMC_SDHCI=y ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_NEW_LEDS is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++CONFIG_EXT3_FS_POSIX_ACL=y ++CONFIG_EXT3_FS_SECURITY=y ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++CONFIG_GENERIC_ACL=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++# CONFIG_MSDOS_FS is not set ++# CONFIG_VFAT_FS is not set ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_CRAMFS=y ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++CONFIG_ROMFS_FS=y ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_UTF8 is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_PI_LIST=y ++# CONFIG_RT_MUTEX_TESTER is not set ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++CONFIG_DEBUG_SPINLOCK_SLEEP=y ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_DEBUG_USER=y ++CONFIG_DEBUG_ERRORS=y ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++# CONFIG_DEBUG_S3C_PORT is not set ++CONFIG_DEBUG_S3C_UART=0 ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++# CONFIG_CRYPTO is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++# CONFIG_CRC_CCITT is not set ++# CONFIG_CRC16 is not set ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_DMA=y +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/configs/smdkc100mtd_defconfig linux-2.6.28.6/arch/arm/configs/smdkc100mtd_defconfig +--- linux-2.6.28/arch/arm/configs/smdkc100mtd_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/configs/smdkc100mtd_defconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,1608 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28.6 ++# Tue Mar 31 14:00:16 2009 ++# ++CONFIG_ARM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++CONFIG_NO_IOPORT=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_ZONE_DMA=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++CONFIG_LOCALVERSION_AUTO=y ++CONFIG_SWAP=y ++# CONFIG_SYSVIPC is not set ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_COMPAT_BRK=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++CONFIG_LSF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_CLASSIC_RCU=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_S5P64XX is not set ++CONFIG_ARCH_S5PC1XX=y ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_S3C64XX_SETUP_I2C1=y ++CONFIG_PLAT_S5PC1XX=y ++CONFIG_CPU_S5PC100_INIT=y ++CONFIG_CPU_S5PC100_CLOCK=y ++CONFIG_S5PC1XX_SETUP_I2C0=y ++CONFIG_S5PC1XX_SETUP_I2C1=y ++CONFIG_S5PC1XX_ADC=y ++CONFIG_S5PC1XX_PWM=y ++CONFIG_S5PC1XX_DEV_FIMC0=y ++CONFIG_S5PC1XX_DEV_FIMC1=y ++CONFIG_S5PC1XX_DEV_FIMC2=y ++CONFIG_S5PC1XX_SETUP_FIMC0=y ++CONFIG_S5PC1XX_SETUP_FIMC1=y ++CONFIG_S5PC1XX_SETUP_FIMC2=y ++CONFIG_PLAT_S3C=y ++ ++# ++# Boot options ++# ++# CONFIG_S3C_BOOT_ERROR_RESET is not set ++ ++# ++# Power management ++# ++CONFIG_S3C_LOWLEVEL_UART_PORT=0 ++CONFIG_SPLIT_ROOT_FILESYSTEM=y ++CONFIG_S3C_GPIO_SPACE=0 ++CONFIG_S3C_GPIO_TRACK=y ++CONFIG_S3C_GPIO_PULL_UPDOWN=y ++CONFIG_S3C_GPIO_CFG_S5PC1XX=y ++CONFIG_S3C_DEV_HSMMC=y ++CONFIG_S3C_DEV_HSMMC1=y ++CONFIG_S3C_DEV_I2C1=y ++CONFIG_S3C_DMA_PL330=y ++CONFIG_CPU_S5PC100=y ++CONFIG_S5PC1XX_SETUP_SDHCI=y ++CONFIG_MACH_SMDKC100=y ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_IFAR=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++CONFIG_ARM_THUMB=y ++# CONFIG_ARM_THUMBEE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_HAS_TLS_REG=y ++# CONFIG_OUTER_CACHE is not set ++CONFIG_ARM_VIC=y ++CONFIG_DMABOUNCE=y ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=200 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++# CONFIG_LEDS is not set ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC0,115200 mem=128M" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_FREQ is not set ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++# CONFIG_FPE_NWFPE is not set ++# CONFIG_FPE_FASTFPE is not set ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++# CONFIG_NEON is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++ ++# ++# Power management options ++# ++# CONFIG_PM is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_PACKET is not set ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++CONFIG_IP_PNP_BOOTP=y ++# CONFIG_IP_PNP_RARP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++CONFIG_INET_XFRM_MODE_TRANSPORT=y ++CONFIG_INET_XFRM_MODE_TUNNEL=y ++CONFIG_INET_XFRM_MODE_BEET=y ++# CONFIG_INET_LRO is not set ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++CONFIG_MTD_CONCAT=y ++CONFIG_MTD_PARTITIONS=y ++CONFIG_MTD_REDBOOT_PARTS=y ++CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 ++CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y ++# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_M25P80 is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_VERIFY_WRITE is not set ++# CONFIG_MTD_NAND_ECC_SMC is not set ++# CONFIG_MTD_NAND_MUSEUM_IDS is not set ++# CONFIG_MTD_NAND_GPIO is not set ++CONFIG_MTD_NAND_IDS=y ++CONFIG_MTD_NAND_S3C=y ++# CONFIG_MTD_NAND_S3C_DEBUG is not set ++CONFIG_MTD_NAND_S3C_HWECC=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ALAUDA is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# UBI - Unsorted block images ++# ++# CONFIG_MTD_UBI is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=8192 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++# CONFIG_SCSI_MULTI_LUN is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_NET_ETHERNET is not set ++CONFIG_NETDEV_1000=y ++CONFIG_NETDEV_10000=y ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++CONFIG_PPP=y ++CONFIG_PPP_MULTILINK=y ++CONFIG_PPP_FILTER=y ++CONFIG_PPP_ASYNC=y ++CONFIG_PPP_SYNC_TTY=y ++# CONFIG_PPP_DEFLATE is not set ++# CONFIG_PPP_BSDCOMP is not set ++# CONFIG_PPP_MPPE is not set ++# CONFIG_PPPOE is not set ++# CONFIG_PPPOL2TP is not set ++# CONFIG_SLIP is not set ++CONFIG_SLHC=y ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_GPIO is not set ++# CONFIG_KEYPAD_S3C is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_LIFEBOOK=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++# CONFIG_TOUCHSCREEN_ADS7846 is not set ++CONFIG_TOUCHSCREEN_S3C=y ++CONFIG_TOUCHSCREEN_NEW=y ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++CONFIG_SERIAL_8250=y ++# CONFIG_SERIAL_8250_CONSOLE is not set ++CONFIG_SERIAL_8250_NR_UARTS=4 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=4 ++# CONFIG_SERIAL_8250_EXTENDED is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_SAMSUNG=y ++CONFIG_SERIAL_SAMSUNG_UARTS=4 ++# CONFIG_SERIAL_SAMSUNG_DEBUG is not set ++CONFIG_SERIAL_SAMSUNG_CONSOLE=y ++CONFIG_SERIAL_S5PC100=y ++# CONFIG_SERIAL_S5PC1XX_HSUART is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_S3C_MEM=y ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_HELPER_AUTO is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++CONFIG_I2C_S3C2410=y ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_AT24 is not set ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_BITBANG is not set ++CONFIG_HS_SPI_S5PC100=y ++CONFIG_HSPICLK_PCLK=y ++# CONFIG_HSPICLK_SCLK_48M is not set ++# CONFIG_WORD_TRANSIZE is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_AT25 is not set ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_TLE62X0 is not set ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++# CONFIG_DEBUG_GPIO is not set ++# CONFIG_GPIO_SYSFS is not set ++ ++# ++# Memory mapped GPIO expanders: ++# ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MCP23S08 is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++CONFIG_HWMON=y ++# CONFIG_HWMON_VID is not set ++# CONFIG_SENSORS_AD7414 is not set ++# CONFIG_SENSORS_AD7418 is not set ++# CONFIG_SENSORS_ADCXX is not set ++# CONFIG_SENSORS_ADM1021 is not set ++# CONFIG_SENSORS_ADM1025 is not set ++# CONFIG_SENSORS_ADM1026 is not set ++# CONFIG_SENSORS_ADM1029 is not set ++# CONFIG_SENSORS_ADM1031 is not set ++# CONFIG_SENSORS_ADM9240 is not set ++# CONFIG_SENSORS_ADT7462 is not set ++# CONFIG_SENSORS_ADT7470 is not set ++# CONFIG_SENSORS_ADT7473 is not set ++# CONFIG_SENSORS_ATXP1 is not set ++# CONFIG_SENSORS_DS1621 is not set ++# CONFIG_SENSORS_F71805F is not set ++# CONFIG_SENSORS_F71882FG is not set ++# CONFIG_SENSORS_F75375S is not set ++# CONFIG_SENSORS_GL518SM is not set ++# CONFIG_SENSORS_GL520SM is not set ++# CONFIG_SENSORS_IT87 is not set ++# CONFIG_SENSORS_LM63 is not set ++# CONFIG_SENSORS_LM70 is not set ++# CONFIG_SENSORS_LM75 is not set ++# CONFIG_SENSORS_LM77 is not set ++# CONFIG_SENSORS_LM78 is not set ++# CONFIG_SENSORS_LM80 is not set ++# CONFIG_SENSORS_LM83 is not set ++# CONFIG_SENSORS_LM85 is not set ++# CONFIG_SENSORS_LM87 is not set ++# CONFIG_SENSORS_LM90 is not set ++# CONFIG_SENSORS_LM92 is not set ++# CONFIG_SENSORS_LM93 is not set ++# CONFIG_SENSORS_MAX1111 is not set ++# CONFIG_SENSORS_MAX1619 is not set ++# CONFIG_SENSORS_MAX6650 is not set ++# CONFIG_SENSORS_PC87360 is not set ++# CONFIG_SENSORS_PC87427 is not set ++# CONFIG_SENSORS_DME1737 is not set ++# CONFIG_SENSORS_SMSC47M1 is not set ++# CONFIG_SENSORS_SMSC47M192 is not set ++# CONFIG_SENSORS_SMSC47B397 is not set ++# CONFIG_SENSORS_ADS7828 is not set ++# CONFIG_SENSORS_THMC50 is not set ++# CONFIG_SENSORS_VT1211 is not set ++# CONFIG_SENSORS_W83781D is not set ++# CONFIG_SENSORS_W83791D is not set ++# CONFIG_SENSORS_W83792D is not set ++# CONFIG_SENSORS_W83793 is not set ++# CONFIG_SENSORS_W83L785TS is not set ++# CONFIG_SENSORS_W83L786NG is not set ++# CONFIG_SENSORS_W83627HF is not set ++# CONFIG_SENSORS_W83627EHF is not set ++# CONFIG_HWMON_DEBUG_CHIP is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++CONFIG_FB_S3C=y ++CONFIG_FB_S3C_LTE480WV=y ++# CONFIG_FB_S3C_LTV350QV is not set ++# CONFIG_FB_S3C_LTS222QV is not set ++CONFIG_FB_S3C_BPP=y ++# CONFIG_FB_S3C_BPP_8 is not set ++CONFIG_FB_S3C_BPP_16=y ++# CONFIG_FB_S3C_BPP_24 is not set ++# CONFIG_FB_S3C_BPP_28 is not set ++# CONFIG_FB_S3C_BPP_32 is not set ++CONFIG_FB_S3C_NUM=1 ++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set ++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++# CONFIG_LOGO_LINUX_CLUT224 is not set ++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++CONFIG_SND_ARM=y ++CONFIG_SND_SPI=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_CAIAQ is not set ++CONFIG_SND_SOC=y ++ ++# ++# SoC Audio for the Samsung S3C ++# ++CONFIG_SND_S5PC1XX_SOC=y ++CONFIG_SND_SOC_I2S_V50=y ++CONFIG_SND_SMDKC100_WM8580=y ++CONFIG_SOUND_S5PC100_WM8580_INPUT_STREAM_LINE=y ++# CONFIG_SOUND_S5PC100_WM8580_INPUT_STREAM_MIC is not set ++# CONFIG_SND_SMDKC100_WM9713 is not set ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM8580=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_BRIGHT=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_DELL=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++CONFIG_USB_DEVICE_CLASS=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_S3C_OTG_HOST is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++CONFIG_USB_ACM=y ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_DPCM is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++# CONFIG_USB_GADGET_S3C_OTGD is not set ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++# CONFIG_USB_GADGET_S3C_OTGD_DMA_MODE is not set ++# CONFIG_USB_GADGET_S3C_OTGD_SLAVE_MODE is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FILE_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_S3C=y ++# CONFIG_MMC_SDHCI_SCATTERGATHER is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_NEW_LEDS is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_DS3234 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_DRV_S3C=y ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++CONFIG_EXT3_FS_POSIX_ACL=y ++CONFIG_EXT3_FS_SECURITY=y ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++CONFIG_GENERIC_ACL=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_YAFFS_FS is not set ++# CONFIG_JFFS2_FS is not set ++CONFIG_CRAMFS=y ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++CONFIG_ROMFS_FS=y ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++# CONFIG_NFS_V4 is not set ++# CONFIG_ROOT_NFS is not set ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_ACL_SUPPORT=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_BSD_DISKLABEL=y ++# CONFIG_MINIX_SUBPARTITION is not set ++CONFIG_SOLARIS_X86_PARTITION=y ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++# CONFIG_EFI_PARTITION is not set ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_UTF8 is not set ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_PI_LIST=y ++# CONFIG_RT_MUTEX_TESTER is not set ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++CONFIG_DEBUG_SPINLOCK_SLEEP=y ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_DEBUG_USER=y ++CONFIG_DEBUG_ERRORS=y ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++# CONFIG_DEBUG_S3C_PORT is not set ++CONFIG_DEBUG_S3C_UART=0 ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++# CONFIG_CRYPTO_MANAGER is not set ++# CONFIG_CRYPTO_MANAGER2 is not set ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++# CONFIG_CRYPTO_MD5 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_CRC_CCITT=y ++# CONFIG_CRC16 is not set ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_DMA=y +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/configs/smdkc100nfs_defconfig linux-2.6.28.6/arch/arm/configs/smdkc100nfs_defconfig +--- linux-2.6.28/arch/arm/configs/smdkc100nfs_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/configs/smdkc100nfs_defconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,1657 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28.6 ++# Sat Mar 21 18:43:29 2009 ++# ++CONFIG_ARM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++CONFIG_NO_IOPORT=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_ZONE_DMA=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++CONFIG_LOCALVERSION_AUTO=y ++CONFIG_SWAP=y ++# CONFIG_SYSVIPC is not set ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_COMPAT_BRK=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++CONFIG_LSF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_CLASSIC_RCU=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_S5P64XX is not set ++CONFIG_ARCH_S5PC1XX=y ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_S3C64XX_SETUP_I2C1=y ++CONFIG_PLAT_S5PC1XX=y ++CONFIG_CPU_S5PC100_INIT=y ++CONFIG_CPU_S5PC100_CLOCK=y ++CONFIG_S5PC1XX_SETUP_I2C0=y ++CONFIG_S5PC1XX_SETUP_I2C1=y ++CONFIG_S5PC1XX_ADC=y ++CONFIG_S5PC1XX_PWM=y ++CONFIG_S5PC1XX_DEV_FIMC0=y ++CONFIG_S5PC1XX_DEV_FIMC1=y ++CONFIG_S5PC1XX_DEV_FIMC2=y ++CONFIG_S5PC1XX_SETUP_FIMC0=y ++CONFIG_S5PC1XX_SETUP_FIMC1=y ++CONFIG_S5PC1XX_SETUP_FIMC2=y ++CONFIG_PLAT_S3C=y ++ ++# ++# Boot options ++# ++# CONFIG_S3C_BOOT_WATCHDOG is not set ++# CONFIG_S3C_BOOT_ERROR_RESET is not set ++ ++# ++# Power management ++# ++CONFIG_S3C_LOWLEVEL_UART_PORT=0 ++CONFIG_SPLIT_ROOT_FILESYSTEM=y ++CONFIG_S3C_GPIO_SPACE=0 ++CONFIG_S3C_GPIO_TRACK=y ++CONFIG_S3C_GPIO_PULL_UPDOWN=y ++CONFIG_S3C_GPIO_CFG_S5PC1XX=y ++CONFIG_S3C_DEV_HSMMC=y ++CONFIG_S3C_DEV_HSMMC1=y ++CONFIG_S3C_DEV_I2C1=y ++CONFIG_S3C_DMA_PL330=y ++CONFIG_CPU_S5PC100=y ++CONFIG_S5PC1XX_SETUP_SDHCI=y ++CONFIG_MACH_SMDKC100=y ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_IFAR=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++CONFIG_ARM_THUMB=y ++# CONFIG_ARM_THUMBEE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_HAS_TLS_REG=y ++# CONFIG_OUTER_CACHE is not set ++CONFIG_ARM_VIC=y ++CONFIG_DMABOUNCE=y ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=200 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++# CONFIG_LEDS is not set ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_CMDLINE="root=/dev/nfs rw nfsroot=12.23.106.52:/opt/small_root_eabi ip=192.168.0.20:12.23.106.52:192.168.0.1:255.255.255.0:test::off init=/linuxrc console=ttySAC0,115200 mem=128M" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_FREQ is not set ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++# CONFIG_FPE_NWFPE is not set ++# CONFIG_FPE_FASTFPE is not set ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++# CONFIG_NEON is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++ ++# ++# Power management options ++# ++# CONFIG_PM is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_PACKET is not set ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++CONFIG_IP_PNP_BOOTP=y ++# CONFIG_IP_PNP_RARP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++CONFIG_INET_XFRM_MODE_TRANSPORT=y ++CONFIG_INET_XFRM_MODE_TUNNEL=y ++CONFIG_INET_XFRM_MODE_BEET=y ++# CONFIG_INET_LRO is not set ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++CONFIG_MTD_CONCAT=y ++CONFIG_MTD_PARTITIONS=y ++CONFIG_MTD_REDBOOT_PARTS=y ++CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 ++CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y ++# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_M25P80 is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_VERIFY_WRITE is not set ++# CONFIG_MTD_NAND_ECC_SMC is not set ++# CONFIG_MTD_NAND_MUSEUM_IDS is not set ++# CONFIG_MTD_NAND_GPIO is not set ++CONFIG_MTD_NAND_IDS=y ++CONFIG_MTD_NAND_S3C=y ++# CONFIG_MTD_NAND_S3C_DEBUG is not set ++CONFIG_MTD_NAND_S3C_HWECC=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ALAUDA is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# UBI - Unsorted block images ++# ++# CONFIG_MTD_UBI is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=8192 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++# CONFIG_SCSI_MULTI_LUN is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_PHYLIB is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_AX88796 is not set ++# CONFIG_SMC91X is not set ++# CONFIG_DM9000 is not set ++# CONFIG_ENC28J60 is not set ++CONFIG_SMC911X=y ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++CONFIG_NETDEV_1000=y ++CONFIG_NETDEV_10000=y ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++CONFIG_PPP=y ++CONFIG_PPP_MULTILINK=y ++CONFIG_PPP_FILTER=y ++CONFIG_PPP_ASYNC=y ++CONFIG_PPP_SYNC_TTY=y ++# CONFIG_PPP_DEFLATE is not set ++# CONFIG_PPP_BSDCOMP is not set ++# CONFIG_PPP_MPPE is not set ++# CONFIG_PPPOE is not set ++# CONFIG_PPPOL2TP is not set ++# CONFIG_SLIP is not set ++CONFIG_SLHC=y ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_GPIO is not set ++# CONFIG_KEYPAD_S3C is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_LIFEBOOK=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++# CONFIG_TOUCHSCREEN_ADS7846 is not set ++CONFIG_TOUCHSCREEN_S3C=y ++CONFIG_TOUCHSCREEN_NEW=y ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++CONFIG_SERIAL_8250=y ++# CONFIG_SERIAL_8250_CONSOLE is not set ++CONFIG_SERIAL_8250_NR_UARTS=4 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=4 ++# CONFIG_SERIAL_8250_EXTENDED is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_SAMSUNG=y ++CONFIG_SERIAL_SAMSUNG_UARTS=4 ++# CONFIG_SERIAL_SAMSUNG_DEBUG is not set ++CONFIG_SERIAL_SAMSUNG_CONSOLE=y ++CONFIG_SERIAL_S5PC100=y ++# CONFIG_SERIAL_S5PC1XX_HSUART is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_S3C_MEM=y ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_HELPER_AUTO is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++CONFIG_I2C_S3C2410=y ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_AT24 is not set ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_BITBANG is not set ++CONFIG_HS_SPI_S5PC100=y ++CONFIG_HSPICLK_PCLK=y ++# CONFIG_HSPICLK_SCLK_48M is not set ++# CONFIG_WORD_TRANSIZE is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_AT25 is not set ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_TLE62X0 is not set ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++# CONFIG_DEBUG_GPIO is not set ++# CONFIG_GPIO_SYSFS is not set ++ ++# ++# Memory mapped GPIO expanders: ++# ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MCP23S08 is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++CONFIG_HWMON=y ++# CONFIG_HWMON_VID is not set ++# CONFIG_SENSORS_AD7414 is not set ++# CONFIG_SENSORS_AD7418 is not set ++# CONFIG_SENSORS_ADCXX is not set ++# CONFIG_SENSORS_ADM1021 is not set ++# CONFIG_SENSORS_ADM1025 is not set ++# CONFIG_SENSORS_ADM1026 is not set ++# CONFIG_SENSORS_ADM1029 is not set ++# CONFIG_SENSORS_ADM1031 is not set ++# CONFIG_SENSORS_ADM9240 is not set ++# CONFIG_SENSORS_ADT7462 is not set ++# CONFIG_SENSORS_ADT7470 is not set ++# CONFIG_SENSORS_ADT7473 is not set ++# CONFIG_SENSORS_ATXP1 is not set ++# CONFIG_SENSORS_DS1621 is not set ++# CONFIG_SENSORS_F71805F is not set ++# CONFIG_SENSORS_F71882FG is not set ++# CONFIG_SENSORS_F75375S is not set ++# CONFIG_SENSORS_GL518SM is not set ++# CONFIG_SENSORS_GL520SM is not set ++# CONFIG_SENSORS_IT87 is not set ++# CONFIG_SENSORS_LM63 is not set ++# CONFIG_SENSORS_LM70 is not set ++# CONFIG_SENSORS_LM75 is not set ++# CONFIG_SENSORS_LM77 is not set ++# CONFIG_SENSORS_LM78 is not set ++# CONFIG_SENSORS_LM80 is not set ++# CONFIG_SENSORS_LM83 is not set ++# CONFIG_SENSORS_LM85 is not set ++# CONFIG_SENSORS_LM87 is not set ++# CONFIG_SENSORS_LM90 is not set ++# CONFIG_SENSORS_LM92 is not set ++# CONFIG_SENSORS_LM93 is not set ++# CONFIG_SENSORS_MAX1111 is not set ++# CONFIG_SENSORS_MAX1619 is not set ++# CONFIG_SENSORS_MAX6650 is not set ++# CONFIG_SENSORS_PC87360 is not set ++# CONFIG_SENSORS_PC87427 is not set ++# CONFIG_SENSORS_DME1737 is not set ++# CONFIG_SENSORS_SMSC47M1 is not set ++# CONFIG_SENSORS_SMSC47M192 is not set ++# CONFIG_SENSORS_SMSC47B397 is not set ++# CONFIG_SENSORS_ADS7828 is not set ++# CONFIG_SENSORS_THMC50 is not set ++# CONFIG_SENSORS_VT1211 is not set ++# CONFIG_SENSORS_W83781D is not set ++# CONFIG_SENSORS_W83791D is not set ++# CONFIG_SENSORS_W83792D is not set ++# CONFIG_SENSORS_W83793 is not set ++# CONFIG_SENSORS_W83L785TS is not set ++# CONFIG_SENSORS_W83L786NG is not set ++# CONFIG_SENSORS_W83627HF is not set ++# CONFIG_SENSORS_W83627EHF is not set ++# CONFIG_HWMON_DEBUG_CHIP is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++CONFIG_S3C2410_WATCHDOG=y ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++CONFIG_FB_S3C=y ++CONFIG_FB_S3C_LTE480WV=y ++# CONFIG_FB_S3C_LTV350QV is not set ++# CONFIG_FB_S3C_LTS222QV is not set ++CONFIG_FB_S3C_BPP=y ++# CONFIG_FB_S3C_BPP_8 is not set ++CONFIG_FB_S3C_BPP_16=y ++# CONFIG_FB_S3C_BPP_24 is not set ++# CONFIG_FB_S3C_BPP_32 is not set ++CONFIG_FB_S3C_NUM=1 ++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set ++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++# CONFIG_LOGO_LINUX_CLUT224 is not set ++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++CONFIG_SND_ARM=y ++CONFIG_SND_SPI=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_CAIAQ is not set ++CONFIG_SND_SOC=y ++ ++# ++# SoC Audio for the Samsung S3C ++# ++CONFIG_SND_S5PC1XX_SOC=y ++CONFIG_SND_SOC_I2S_V50=y ++CONFIG_SND_SMDKC100_WM8580=y ++CONFIG_SOUND_S5PC100_WM8580_INPUT_STREAM_LINE=y ++# CONFIG_SOUND_S5PC100_WM8580_INPUT_STREAM_MIC is not set ++# CONFIG_SND_SMDKC100_WM9713 is not set ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM8580=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_BRIGHT=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_DELL=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++CONFIG_USB_DEVICE_CLASS=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_DPCM is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++CONFIG_USB_GADGET_S3C_OTGD=y ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++ ++# ++# NOTE: S3C OTG device role enables the controller driver below ++# ++CONFIG_USB_S3C_OTGD=y ++CONFIG_USB_GADGET_S3C_OTGD_DMA_MODE=y ++# CONFIG_USB_GADGET_S3C_OTGD_SLAVE_MODE is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++CONFIG_USB_ETH=m ++# CONFIG_USB_ETH_RNDIS is not set ++# CONFIG_USB_GADGETFS is not set ++CONFIG_USB_FILE_STORAGE=m ++# CONFIG_USB_FILE_STORAGE_TEST is not set ++CONFIG_USB_G_SERIAL=m ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_S3C=y ++# CONFIG_MMC_SDHCI_SCATTERGATHER is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_NEW_LEDS is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_DS3234 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_DRV_S3C=y ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++CONFIG_EXT3_FS_POSIX_ACL=y ++CONFIG_EXT3_FS_SECURITY=y ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++CONFIG_GENERIC_ACL=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_YAFFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++CONFIG_JFFS2_FS_WRITEBUFFER=y ++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_CRAMFS=y ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++CONFIG_ROMFS_FS=y ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++# CONFIG_NFS_V4 is not set ++CONFIG_ROOT_NFS=y ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_ACL_SUPPORT=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_BSD_DISKLABEL=y ++# CONFIG_MINIX_SUBPARTITION is not set ++CONFIG_SOLARIS_X86_PARTITION=y ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++# CONFIG_EFI_PARTITION is not set ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_UTF8 is not set ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_PI_LIST=y ++# CONFIG_RT_MUTEX_TESTER is not set ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++CONFIG_DEBUG_SPINLOCK_SLEEP=y ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_DEBUG_USER=y ++CONFIG_DEBUG_ERRORS=y ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++# CONFIG_DEBUG_S3C_PORT is not set ++CONFIG_DEBUG_S3C_UART=0 ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++# CONFIG_CRYPTO_MANAGER is not set ++# CONFIG_CRYPTO_MANAGER2 is not set ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++# CONFIG_CRYPTO_MD5 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_CRC_CCITT=y ++# CONFIG_CRC16 is not set ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_DMA=y +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/configs/smdkc100onenand_defconfig linux-2.6.28.6/arch/arm/configs/smdkc100onenand_defconfig +--- linux-2.6.28/arch/arm/configs/smdkc100onenand_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/configs/smdkc100onenand_defconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,1625 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28.6 ++# Tue Mar 31 13:05:11 2009 ++# ++CONFIG_ARM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++CONFIG_NO_IOPORT=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_ZONE_DMA=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++CONFIG_LOCALVERSION_AUTO=y ++CONFIG_SWAP=y ++# CONFIG_SYSVIPC is not set ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_COMPAT_BRK=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++CONFIG_LSF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_CLASSIC_RCU=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_S5P64XX is not set ++CONFIG_ARCH_S5PC1XX=y ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_S3C64XX_SETUP_I2C1=y ++CONFIG_PLAT_S5PC1XX=y ++CONFIG_CPU_S5PC100_INIT=y ++CONFIG_CPU_S5PC100_CLOCK=y ++CONFIG_S5PC1XX_SETUP_I2C0=y ++CONFIG_S5PC1XX_SETUP_I2C1=y ++CONFIG_S5PC1XX_ADC=y ++CONFIG_S5PC1XX_PWM=y ++CONFIG_S5PC1XX_DEV_FIMC0=y ++CONFIG_S5PC1XX_DEV_FIMC1=y ++CONFIG_S5PC1XX_DEV_FIMC2=y ++CONFIG_S5PC1XX_SETUP_FIMC0=y ++CONFIG_S5PC1XX_SETUP_FIMC1=y ++CONFIG_S5PC1XX_SETUP_FIMC2=y ++CONFIG_PLAT_S3C=y ++ ++# ++# Boot options ++# ++# CONFIG_S3C_BOOT_WATCHDOG is not set ++# CONFIG_S3C_BOOT_ERROR_RESET is not set ++ ++# ++# Power management ++# ++CONFIG_S3C_LOWLEVEL_UART_PORT=0 ++CONFIG_SPLIT_ROOT_FILESYSTEM=y ++CONFIG_S3C_GPIO_SPACE=0 ++CONFIG_S3C_GPIO_TRACK=y ++CONFIG_S3C_GPIO_PULL_UPDOWN=y ++CONFIG_S3C_GPIO_CFG_S5PC1XX=y ++CONFIG_S3C_DEV_HSMMC=y ++CONFIG_S3C_DEV_HSMMC1=y ++CONFIG_S3C_DEV_I2C1=y ++CONFIG_S3C_DMA_PL330=y ++CONFIG_CPU_S5PC100=y ++CONFIG_S5PC1XX_SETUP_SDHCI=y ++CONFIG_MACH_SMDKC100=y ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_IFAR=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++CONFIG_ARM_THUMB=y ++# CONFIG_ARM_THUMBEE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_HAS_TLS_REG=y ++# CONFIG_OUTER_CACHE is not set ++CONFIG_ARM_VIC=y ++CONFIG_DMABOUNCE=y ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=200 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++# CONFIG_LEDS is not set ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC0,115200 mem=128M" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_FREQ is not set ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++# CONFIG_FPE_NWFPE is not set ++# CONFIG_FPE_FASTFPE is not set ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++# CONFIG_NEON is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++ ++# ++# Power management options ++# ++# CONFIG_PM is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_PACKET is not set ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++CONFIG_IP_PNP_BOOTP=y ++# CONFIG_IP_PNP_RARP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++CONFIG_INET_XFRM_MODE_TRANSPORT=y ++CONFIG_INET_XFRM_MODE_TUNNEL=y ++CONFIG_INET_XFRM_MODE_BEET=y ++# CONFIG_INET_LRO is not set ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++CONFIG_MTD_CONCAT=y ++CONFIG_MTD_PARTITIONS=y ++CONFIG_MTD_REDBOOT_PARTS=y ++CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 ++CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y ++# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_M25P80 is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++# CONFIG_MTD_NAND is not set ++CONFIG_MTD_ONENAND=y ++CONFIG_MTD_ONENAND_VERIFY_WRITE=y ++CONFIG_MTD_ONENAND_GENERIC=y ++# CONFIG_MTD_ONENAND_OTP is not set ++# CONFIG_MTD_ONENAND_2X_PROGRAM is not set ++# CONFIG_MTD_ONENAND_SIM is not set ++ ++# ++# UBI - Unsorted block images ++# ++# CONFIG_MTD_UBI is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=8192 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++# CONFIG_SCSI_MULTI_LUN is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_NET_ETHERNET is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++CONFIG_PPP=y ++CONFIG_PPP_MULTILINK=y ++CONFIG_PPP_FILTER=y ++CONFIG_PPP_ASYNC=y ++CONFIG_PPP_SYNC_TTY=y ++# CONFIG_PPP_DEFLATE is not set ++# CONFIG_PPP_BSDCOMP is not set ++# CONFIG_PPP_MPPE is not set ++# CONFIG_PPPOE is not set ++# CONFIG_PPPOL2TP is not set ++# CONFIG_SLIP is not set ++CONFIG_SLHC=y ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_GPIO is not set ++CONFIG_KEYPAD_S3C=y ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_LIFEBOOK=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++# CONFIG_TOUCHSCREEN_ADS7846 is not set ++CONFIG_TOUCHSCREEN_S3C=y ++CONFIG_TOUCHSCREEN_NEW=y ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++CONFIG_SERIAL_8250=y ++# CONFIG_SERIAL_8250_CONSOLE is not set ++CONFIG_SERIAL_8250_NR_UARTS=4 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=4 ++# CONFIG_SERIAL_8250_EXTENDED is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_SAMSUNG=y ++CONFIG_SERIAL_SAMSUNG_UARTS=4 ++# CONFIG_SERIAL_SAMSUNG_DEBUG is not set ++CONFIG_SERIAL_SAMSUNG_CONSOLE=y ++CONFIG_SERIAL_S5PC100=y ++# CONFIG_SERIAL_S5PC1XX_HSUART is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_S3C_MEM=y ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_HELPER_AUTO is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++CONFIG_I2C_S3C2410=y ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_AT24 is not set ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_BITBANG is not set ++CONFIG_HS_SPI_S5PC100=y ++CONFIG_HSPICLK_PCLK=y ++# CONFIG_HSPICLK_SCLK_48M is not set ++# CONFIG_WORD_TRANSIZE is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_AT25 is not set ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_TLE62X0 is not set ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++# CONFIG_DEBUG_GPIO is not set ++# CONFIG_GPIO_SYSFS is not set ++ ++# ++# Memory mapped GPIO expanders: ++# ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MCP23S08 is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++CONFIG_HWMON=y ++# CONFIG_HWMON_VID is not set ++# CONFIG_SENSORS_AD7414 is not set ++# CONFIG_SENSORS_AD7418 is not set ++# CONFIG_SENSORS_ADCXX is not set ++# CONFIG_SENSORS_ADM1021 is not set ++# CONFIG_SENSORS_ADM1025 is not set ++# CONFIG_SENSORS_ADM1026 is not set ++# CONFIG_SENSORS_ADM1029 is not set ++# CONFIG_SENSORS_ADM1031 is not set ++# CONFIG_SENSORS_ADM9240 is not set ++# CONFIG_SENSORS_ADT7462 is not set ++# CONFIG_SENSORS_ADT7470 is not set ++# CONFIG_SENSORS_ADT7473 is not set ++# CONFIG_SENSORS_ATXP1 is not set ++# CONFIG_SENSORS_DS1621 is not set ++# CONFIG_SENSORS_F71805F is not set ++# CONFIG_SENSORS_F71882FG is not set ++# CONFIG_SENSORS_F75375S is not set ++# CONFIG_SENSORS_GL518SM is not set ++# CONFIG_SENSORS_GL520SM is not set ++# CONFIG_SENSORS_IT87 is not set ++# CONFIG_SENSORS_LM63 is not set ++# CONFIG_SENSORS_LM70 is not set ++# CONFIG_SENSORS_LM75 is not set ++# CONFIG_SENSORS_LM77 is not set ++# CONFIG_SENSORS_LM78 is not set ++# CONFIG_SENSORS_LM80 is not set ++# CONFIG_SENSORS_LM83 is not set ++# CONFIG_SENSORS_LM85 is not set ++# CONFIG_SENSORS_LM87 is not set ++# CONFIG_SENSORS_LM90 is not set ++# CONFIG_SENSORS_LM92 is not set ++# CONFIG_SENSORS_LM93 is not set ++# CONFIG_SENSORS_MAX1111 is not set ++# CONFIG_SENSORS_MAX1619 is not set ++# CONFIG_SENSORS_MAX6650 is not set ++# CONFIG_SENSORS_PC87360 is not set ++# CONFIG_SENSORS_PC87427 is not set ++# CONFIG_SENSORS_DME1737 is not set ++# CONFIG_SENSORS_SMSC47M1 is not set ++# CONFIG_SENSORS_SMSC47M192 is not set ++# CONFIG_SENSORS_SMSC47B397 is not set ++# CONFIG_SENSORS_ADS7828 is not set ++# CONFIG_SENSORS_THMC50 is not set ++# CONFIG_SENSORS_VT1211 is not set ++# CONFIG_SENSORS_W83781D is not set ++# CONFIG_SENSORS_W83791D is not set ++# CONFIG_SENSORS_W83792D is not set ++# CONFIG_SENSORS_W83793 is not set ++# CONFIG_SENSORS_W83L785TS is not set ++# CONFIG_SENSORS_W83L786NG is not set ++# CONFIG_SENSORS_W83627HF is not set ++# CONFIG_SENSORS_W83627EHF is not set ++# CONFIG_HWMON_DEBUG_CHIP is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++CONFIG_S3C2410_WATCHDOG=y ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++# CONFIG_VIDEO_DEV is not set ++# CONFIG_DVB_CORE is not set ++# CONFIG_VIDEO_MEDIA is not set ++ ++# ++# Multimedia drivers ++# ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++CONFIG_FB_S3C=y ++CONFIG_FB_S3C_LTE480WV=y ++# CONFIG_FB_S3C_LTV350QV is not set ++# CONFIG_FB_S3C_LTS222QV is not set ++CONFIG_FB_S3C_BPP=y ++# CONFIG_FB_S3C_BPP_8 is not set ++CONFIG_FB_S3C_BPP_16=y ++# CONFIG_FB_S3C_BPP_24 is not set ++# CONFIG_FB_S3C_BPP_28 is not set ++# CONFIG_FB_S3C_BPP_32 is not set ++CONFIG_FB_S3C_NUM=1 ++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set ++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++# CONFIG_LOGO_LINUX_CLUT224 is not set ++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++CONFIG_SND_ARM=y ++CONFIG_SND_SPI=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_CAIAQ is not set ++CONFIG_SND_SOC=y ++ ++# ++# SoC Audio for the Samsung S3C ++# ++CONFIG_SND_S5PC1XX_SOC=y ++CONFIG_SND_SOC_I2S_V50=y ++CONFIG_SND_SMDKC100_WM8580=y ++CONFIG_SOUND_S5PC100_WM8580_INPUT_STREAM_LINE=y ++# CONFIG_SOUND_S5PC100_WM8580_INPUT_STREAM_MIC is not set ++# CONFIG_SND_SMDKC100_WM9713 is not set ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM8580=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_BRIGHT=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_DELL=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++CONFIG_USB_DEVICE_CLASS=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_S3C_OTG_HOST is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_DPCM is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++# CONFIG_USB_GADGET_S3C_OTGD is not set ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++# CONFIG_USB_GADGET_S3C_OTGD_DMA_MODE is not set ++# CONFIG_USB_GADGET_S3C_OTGD_SLAVE_MODE is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FILE_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_S3C=y ++# CONFIG_MMC_SDHCI_SCATTERGATHER is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_NEW_LEDS is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_DS3234 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_DRV_S3C=y ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++CONFIG_EXT3_FS_POSIX_ACL=y ++CONFIG_EXT3_FS_SECURITY=y ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++CONFIG_GENERIC_ACL=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_YAFFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++CONFIG_JFFS2_FS_WRITEBUFFER=y ++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_CRAMFS=y ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++CONFIG_ROMFS_FS=y ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++# CONFIG_NFS_V4 is not set ++# CONFIG_ROOT_NFS is not set ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_ACL_SUPPORT=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_BSD_DISKLABEL=y ++# CONFIG_MINIX_SUBPARTITION is not set ++CONFIG_SOLARIS_X86_PARTITION=y ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++# CONFIG_EFI_PARTITION is not set ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_UTF8 is not set ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_PI_LIST=y ++# CONFIG_RT_MUTEX_TESTER is not set ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++CONFIG_DEBUG_SPINLOCK_SLEEP=y ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_DEBUG_USER=y ++CONFIG_DEBUG_ERRORS=y ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++# CONFIG_DEBUG_S3C_PORT is not set ++CONFIG_DEBUG_S3C_UART=0 ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++# CONFIG_CRYPTO_MANAGER is not set ++# CONFIG_CRYPTO_MANAGER2 is not set ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++# CONFIG_CRYPTO_MD5 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_CRC_CCITT=y ++# CONFIG_CRC16 is not set ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_DMA=y +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/configs/smdkc100pm_defconfig linux-2.6.28.6/arch/arm/configs/smdkc100pm_defconfig +--- linux-2.6.28/arch/arm/configs/smdkc100pm_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/configs/smdkc100pm_defconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,1560 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28.6 ++# Tue Apr 28 11:19:27 2009 ++# ++CONFIG_ARM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++CONFIG_NO_IOPORT=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_ZONE_DMA=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="" ++CONFIG_LOCALVERSION_AUTO=y ++CONFIG_SWAP=y ++# CONFIG_SYSVIPC is not set ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_COMPAT_BRK=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++CONFIG_LBD=y ++# CONFIG_BLK_DEV_IO_TRACE is not set ++CONFIG_LSF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_CLASSIC_RCU=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_S5P64XX is not set ++CONFIG_ARCH_S5PC1XX=y ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_S3C64XX_SETUP_I2C1=y ++CONFIG_PLAT_S5PC1XX=y ++CONFIG_CPU_S5PC100_INIT=y ++CONFIG_CPU_S5PC100_CLOCK=y ++CONFIG_S5PC1XX_SETUP_I2C0=y ++CONFIG_S5PC1XX_SETUP_I2C1=y ++CONFIG_S5PC1XX_ADC=y ++CONFIG_S5PC1XX_DEV_FIMC0=y ++CONFIG_S5PC1XX_DEV_FIMC1=y ++CONFIG_S5PC1XX_DEV_FIMC2=y ++CONFIG_S5PC1XX_SETUP_FIMC0=y ++CONFIG_S5PC1XX_SETUP_FIMC1=y ++CONFIG_S5PC1XX_SETUP_FIMC2=y ++CONFIG_S5PC1XX_DEV_CSIS=y ++CONFIG_S5PC1XX_SETUP_CSIS=y ++CONFIG_S5PC1XX_PWM=y ++# CONFIG_TIMER_PWM is not set ++# CONFIG_NO_PWM is not set ++CONFIG_PLAT_S3C=y ++ ++# ++# Boot options ++# ++# CONFIG_S3C_BOOT_WATCHDOG is not set ++# CONFIG_S3C_BOOT_ERROR_RESET is not set ++ ++# ++# Power management ++# ++# CONFIG_S3C2410_PM_DEBUG is not set ++# CONFIG_S3C2410_PM_CHECK is not set ++CONFIG_S3C_LOWLEVEL_UART_PORT=0 ++CONFIG_SPLIT_ROOT_FILESYSTEM=y ++CONFIG_S3C_GPIO_SPACE=0 ++CONFIG_S3C_GPIO_TRACK=y ++CONFIG_S3C_GPIO_PULL_UPDOWN=y ++CONFIG_S3C_GPIO_CFG_S5PC1XX=y ++CONFIG_S3C_DEV_HSMMC=y ++CONFIG_S3C_DEV_HSMMC1=y ++CONFIG_S3C_DEV_I2C1=y ++CONFIG_S3C_DMA_PL330=y ++CONFIG_CPU_S5PC100=y ++CONFIG_S5PC1XX_SETUP_SDHCI=y ++CONFIG_MACH_SMDKC100=y ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_IFAR=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++CONFIG_ARM_THUMB=y ++# CONFIG_ARM_THUMBEE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_HAS_TLS_REG=y ++# CONFIG_OUTER_CACHE is not set ++CONFIG_ARM_VIC=y ++CONFIG_DMABOUNCE=y ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=200 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++CONFIG_UNEVICTABLE_LRU=y ++# CONFIG_LEDS is not set ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC0,115200 mem=128M" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_FREQ is not set ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++# CONFIG_FPE_NWFPE is not set ++# CONFIG_FPE_FASTFPE is not set ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++# CONFIG_NEON is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++ ++# ++# Power management options ++# ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++CONFIG_PM_SLEEP=y ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++CONFIG_APM_EMULATION=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_PACKET is not set ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++# CONFIG_IP_PNP_DHCP is not set ++CONFIG_IP_PNP_BOOTP=y ++# CONFIG_IP_PNP_RARP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++CONFIG_INET_XFRM_MODE_TRANSPORT=y ++CONFIG_INET_XFRM_MODE_TUNNEL=y ++CONFIG_INET_XFRM_MODE_BEET=y ++# CONFIG_INET_LRO is not set ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++CONFIG_MTD_CONCAT=y ++CONFIG_MTD_PARTITIONS=y ++CONFIG_MTD_REDBOOT_PARTS=y ++CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 ++CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y ++# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_M25P80 is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_VERIFY_WRITE is not set ++# CONFIG_MTD_NAND_ECC_SMC is not set ++# CONFIG_MTD_NAND_MUSEUM_IDS is not set ++# CONFIG_MTD_NAND_GPIO is not set ++CONFIG_MTD_NAND_IDS=y ++CONFIG_MTD_NAND_S3C=y ++# CONFIG_MTD_NAND_S3C_DEBUG is not set ++CONFIG_MTD_NAND_S3C_HWECC=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++CONFIG_MTD_ONENAND=y ++# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set ++CONFIG_MTD_ONENAND_GENERIC=y ++# CONFIG_MTD_ONENAND_OTP is not set ++# CONFIG_MTD_ONENAND_2X_PROGRAM is not set ++# CONFIG_MTD_ONENAND_SIM is not set ++ ++# ++# UBI - Unsorted block images ++# ++# CONFIG_MTD_UBI is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=8192 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++# CONFIG_SCSI_MULTI_LUN is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_NET_ETHERNET is not set ++CONFIG_NETDEV_1000=y ++CONFIG_NETDEV_10000=y ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++# CONFIG_WAN is not set ++CONFIG_PPP=y ++CONFIG_PPP_MULTILINK=y ++CONFIG_PPP_FILTER=y ++CONFIG_PPP_ASYNC=y ++CONFIG_PPP_SYNC_TTY=y ++# CONFIG_PPP_DEFLATE is not set ++# CONFIG_PPP_BSDCOMP is not set ++# CONFIG_PPP_MPPE is not set ++# CONFIG_PPPOE is not set ++# CONFIG_PPPOL2TP is not set ++# CONFIG_SLIP is not set ++CONFIG_SLHC=y ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_GPIO is not set ++# CONFIG_KEYPAD_S3C is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_LIFEBOOK=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++# CONFIG_TOUCHSCREEN_ADS7846 is not set ++CONFIG_TOUCHSCREEN_S3C=y ++CONFIG_TOUCHSCREEN_NEW=y ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_DEVKMEM=y ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++CONFIG_SERIAL_8250=y ++# CONFIG_SERIAL_8250_CONSOLE is not set ++CONFIG_SERIAL_8250_NR_UARTS=4 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=4 ++# CONFIG_SERIAL_8250_EXTENDED is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_SAMSUNG=y ++CONFIG_SERIAL_SAMSUNG_UARTS=4 ++# CONFIG_SERIAL_SAMSUNG_DEBUG is not set ++CONFIG_SERIAL_SAMSUNG_CONSOLE=y ++CONFIG_SERIAL_S5PC100=y ++# CONFIG_SERIAL_S5PC1XX_HSUART is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_S3C_MEM=y ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_HELPER_AUTO is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++CONFIG_I2C_S3C2410=y ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_AT24 is not set ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_BITBANG is not set ++CONFIG_HS_SPI_S5PC100=y ++CONFIG_HSPICLK_PCLK=y ++# CONFIG_HSPICLK_SCLK_48M is not set ++# CONFIG_WORD_TRANSIZE is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_AT25 is not set ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_TLE62X0 is not set ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++# CONFIG_DEBUG_GPIO is not set ++# CONFIG_GPIO_SYSFS is not set ++ ++# ++# Memory mapped GPIO expanders: ++# ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MCP23S08 is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++CONFIG_HWMON=y ++# CONFIG_HWMON_VID is not set ++# CONFIG_SENSORS_AD7414 is not set ++# CONFIG_SENSORS_AD7418 is not set ++# CONFIG_SENSORS_ADCXX is not set ++# CONFIG_SENSORS_ADM1021 is not set ++# CONFIG_SENSORS_ADM1025 is not set ++# CONFIG_SENSORS_ADM1026 is not set ++# CONFIG_SENSORS_ADM1029 is not set ++# CONFIG_SENSORS_ADM1031 is not set ++# CONFIG_SENSORS_ADM9240 is not set ++# CONFIG_SENSORS_ADT7462 is not set ++# CONFIG_SENSORS_ADT7470 is not set ++# CONFIG_SENSORS_ADT7473 is not set ++# CONFIG_SENSORS_ATXP1 is not set ++# CONFIG_SENSORS_DS1621 is not set ++# CONFIG_SENSORS_F71805F is not set ++# CONFIG_SENSORS_F71882FG is not set ++# CONFIG_SENSORS_F75375S is not set ++# CONFIG_SENSORS_GL518SM is not set ++# CONFIG_SENSORS_GL520SM is not set ++# CONFIG_SENSORS_IT87 is not set ++# CONFIG_SENSORS_LM63 is not set ++# CONFIG_SENSORS_LM70 is not set ++# CONFIG_SENSORS_LM75 is not set ++# CONFIG_SENSORS_LM77 is not set ++# CONFIG_SENSORS_LM78 is not set ++# CONFIG_SENSORS_LM80 is not set ++# CONFIG_SENSORS_LM83 is not set ++# CONFIG_SENSORS_LM85 is not set ++# CONFIG_SENSORS_LM87 is not set ++# CONFIG_SENSORS_LM90 is not set ++# CONFIG_SENSORS_LM92 is not set ++# CONFIG_SENSORS_LM93 is not set ++# CONFIG_SENSORS_MAX1111 is not set ++# CONFIG_SENSORS_MAX1619 is not set ++# CONFIG_SENSORS_MAX6650 is not set ++# CONFIG_SENSORS_PC87360 is not set ++# CONFIG_SENSORS_PC87427 is not set ++# CONFIG_SENSORS_DME1737 is not set ++# CONFIG_SENSORS_SMSC47M1 is not set ++# CONFIG_SENSORS_SMSC47M192 is not set ++# CONFIG_SENSORS_SMSC47B397 is not set ++# CONFIG_SENSORS_ADS7828 is not set ++# CONFIG_SENSORS_THMC50 is not set ++# CONFIG_SENSORS_VT1211 is not set ++# CONFIG_SENSORS_W83781D is not set ++# CONFIG_SENSORS_W83791D is not set ++# CONFIG_SENSORS_W83792D is not set ++# CONFIG_SENSORS_W83793 is not set ++# CONFIG_SENSORS_W83L785TS is not set ++# CONFIG_SENSORS_W83L786NG is not set ++# CONFIG_SENSORS_W83627HF is not set ++# CONFIG_SENSORS_W83627EHF is not set ++# CONFIG_HWMON_DEBUG_CHIP is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++CONFIG_S3C2410_WATCHDOG=y ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2_COMMON=y ++CONFIG_VIDEO_ALLOW_V4L1=y ++CONFIG_VIDEO_V4L1_COMPAT=y ++# CONFIG_DVB_CORE is not set ++CONFIG_VIDEO_MEDIA=y ++ ++# ++# Multimedia drivers ++# ++# CONFIG_MEDIA_ATTACH is not set ++CONFIG_MEDIA_TUNER=y ++# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set ++CONFIG_MEDIA_TUNER_SIMPLE=y ++CONFIG_MEDIA_TUNER_TDA8290=y ++CONFIG_MEDIA_TUNER_TDA9887=y ++CONFIG_MEDIA_TUNER_TEA5761=y ++CONFIG_MEDIA_TUNER_TEA5767=y ++CONFIG_MEDIA_TUNER_MT20XX=y ++CONFIG_MEDIA_TUNER_XC2028=y ++CONFIG_MEDIA_TUNER_XC5000=y ++CONFIG_VIDEO_V4L2=y ++CONFIG_VIDEO_V4L1=y ++CONFIG_VIDEO_CAPTURE_DRIVERS=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++CONFIG_VIDEO_FIXED_MINOR_RANGES=y ++CONFIG_VIDEO_HELPER_CHIPS_AUTO=y ++# CONFIG_VIDEO_VIVI is not set ++# CONFIG_VIDEO_CPIA is not set ++# CONFIG_VIDEO_SAA5246A is not set ++# CONFIG_VIDEO_SAA5249 is not set ++# CONFIG_SOC_CAMERA is not set ++CONFIG_VIDEO_SAMSUNG=y ++ ++# ++# FIMC configurations ++# ++CONFIG_VIDEO_FIMC=y ++# CONFIG_VIDEO_FIMC_DEBUG is not set ++# CONFIG_VIDEO_FIMC_MIPI is not set ++CONFIG_S5K4BA=y ++# CONFIG_S5K3BA is not set ++CONFIG_VIDEO_FIMC_CAM_CH=0 ++CONFIG_VIDEO_FIMC_CAM_RESET=0 ++CONFIG_VIDEO_MFC40=y ++CONFIG_VIDEO_JPEG_V2=y ++CONFIG_VIDEO_ROTATOR=y ++CONFIG_VIDEO_G2D=y ++CONFIG_VIDEO_G3D=y ++ ++# ++# Reserved memory configurations ++# ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC=10240 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC=32768 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG=32768 ++CONFIG_VIDEO_MFC_MAX_INSTANCE=1 ++# CONFIG_RADIO_ADAPTERS is not set ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++CONFIG_FB_S3C=y ++CONFIG_FB_S3C_LTE480WV=y ++# CONFIG_FB_S3C_LTV350QV is not set ++# CONFIG_FB_S3C_LTS222QV is not set ++CONFIG_FB_S3C_BPP=y ++# CONFIG_FB_S3C_BPP_8 is not set ++CONFIG_FB_S3C_BPP_16=y ++# CONFIG_FB_S3C_BPP_24 is not set ++# CONFIG_FB_S3C_BPP_28 is not set ++# CONFIG_FB_S3C_BPP_32 is not set ++CONFIG_FB_S3C_NUM=1 ++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set ++# CONFIG_FB_S3C_DOUBLE_BUFFERING is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++# CONFIG_LOGO_LINUX_CLUT224 is not set ++CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224=y ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++CONFIG_SND_ARM=y ++CONFIG_SND_SPI=y ++CONFIG_SND_SOC=y ++ ++# ++# SoC Audio for the Samsung S3C ++# ++CONFIG_SND_S5PC1XX_SOC=y ++CONFIG_SND_SOC_I2S_V50=y ++CONFIG_SND_SMDKC100_WM8580=y ++CONFIG_SOUND_S5PC100_WM8580_INPUT_STREAM_LINE=y ++# CONFIG_SOUND_S5PC100_WM8580_INPUT_STREAM_MIC is not set ++# CONFIG_SND_SMDKC100_WM9713 is not set ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM8580=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++# CONFIG_HID_PID is not set ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++# CONFIG_USB is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++CONFIG_USB_GADGET_S3C_OTGD=y ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++ ++# ++# NOTE: S3C OTG device role enables the controller driver below ++# ++CONFIG_USB_S3C_OTGD=y ++CONFIG_USB_GADGET_S3C_OTGD_DMA_MODE=y ++# CONFIG_USB_GADGET_S3C_OTGD_SLAVE_MODE is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++CONFIG_USB_ETH=m ++CONFIG_USB_ETH_RNDIS=y ++# CONFIG_USB_GADGETFS is not set ++CONFIG_USB_FILE_STORAGE=m ++# CONFIG_USB_FILE_STORAGE_TEST is not set ++CONFIG_USB_G_SERIAL=m ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_S3C=y ++# CONFIG_MMC_SPI is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_NEW_LEDS is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_DS3234 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_DRV_S3C=y ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++CONFIG_EXT3_FS_POSIX_ACL=y ++CONFIG_EXT3_FS_SECURITY=y ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++CONFIG_GENERIC_ACL=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_YAFFS_FS is not set ++# CONFIG_JFFS2_FS is not set ++CONFIG_CRAMFS=y ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++CONFIG_ROMFS_FS=y ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++# CONFIG_NFS_V4 is not set ++# CONFIG_ROOT_NFS is not set ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_ACL_SUPPORT=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_BSD_DISKLABEL=y ++# CONFIG_MINIX_SUBPARTITION is not set ++CONFIG_SOLARIS_X86_PARTITION=y ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++# CONFIG_EFI_PARTITION is not set ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_UTF8 is not set ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_PI_LIST=y ++# CONFIG_RT_MUTEX_TESTER is not set ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++CONFIG_DEBUG_SPINLOCK_SLEEP=y ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_DEBUG_USER=y ++CONFIG_DEBUG_ERRORS=y ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++# CONFIG_DEBUG_S3C_PORT is not set ++CONFIG_DEBUG_S3C_UART=0 ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++# CONFIG_CRYPTO_MANAGER is not set ++# CONFIG_CRYPTO_MANAGER2 is not set ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++# CONFIG_CRYPTO_MD5 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_CRC_CCITT=y ++# CONFIG_CRC16 is not set ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_DMA=y +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/include/asm/hardware/vic.h linux-2.6.28.6/arch/arm/include/asm/hardware/vic.h +--- linux-2.6.28/arch/arm/include/asm/hardware/vic.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/include/asm/hardware/vic.h 2009-04-30 09:36:37.000000000 +0200 +@@ -29,15 +29,17 @@ + #define VIC_INT_SOFT 0x18 + #define VIC_INT_SOFT_CLEAR 0x1c + #define VIC_PROTECT 0x20 +-#define VIC_VECT_ADDR 0x30 +-#define VIC_DEF_VECT_ADDR 0x34 ++#define VIC_PL190_VECT_ADDR 0x30 /* PL190 only */ ++#define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */ + +-#define VIC_VECT_ADDR0 0x100 /* 0 to 15 */ +-#define VIC_VECT_CNTL0 0x200 /* 0 to 15 */ ++#define VIC_VECT_ADDR0 0x100 /* 0 to 15 (0..31 PL192) */ ++#define VIC_VECT_CNTL0 0x200 /* 0 to 15 (0..31 PL192) */ + #define VIC_ITCR 0x300 /* VIC test control register */ + + #define VIC_VECT_CNTL_ENABLE (1 << 5) + ++#define VIC_PL192_VECT_ADDR 0xF00 ++ + #ifndef __ASSEMBLY__ + void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources); + #endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/include/asm/memory.h linux-2.6.28.6/arch/arm/include/asm/memory.h +--- linux-2.6.28/arch/arm/include/asm/memory.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/include/asm/memory.h 2009-10-21 09:48:29.000000000 +0200 +@@ -104,7 +104,7 @@ + * between 2MB and 14MB inclusive. + */ + #ifndef CONSISTENT_DMA_SIZE +-#define CONSISTENT_DMA_SIZE SZ_2M ++#define CONSISTENT_DMA_SIZE (SZ_8M + SZ_4M)//SZ_2M + #endif + + /* +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2410/Kconfig linux-2.6.28.6/arch/arm/mach-s3c2410/Kconfig +--- linux-2.6.28/arch/arm/mach-s3c2410/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2410/Kconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -32,11 +32,6 @@ + help + GPIO code for S3C2410 and similar processors + +-config S3C2410_CLOCK +- bool +- help +- Clock code for the S3C2410, and similar processors +- + config SIMTEC_NOR + bool + help +@@ -84,6 +79,7 @@ + select PM_SIMTEC if PM + select SIMTEC_NOR + select MACH_BAST_IDE ++ select S3C24XX_DCLK + select ISA + help + Say Y here if you are using the Simtec Electronics EB2410ITX +@@ -121,6 +117,7 @@ + config MACH_VR1000 + bool "Thorcom VR1000" + select PM_SIMTEC if PM ++ select S3C24XX_DCLK + select SIMTEC_NOR + select MACH_BAST_IDE + select CPU_S3C2410 +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2410/Makefile linux-2.6.28.6/arch/arm/mach-s3c2410/Makefile +--- linux-2.6.28/arch/arm/mach-s3c2410/Makefile 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2410/Makefile 2009-04-30 09:36:37.000000000 +0200 +@@ -15,7 +15,6 @@ + obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o + obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o + obj-$(CONFIG_S3C2410_GPIO) += gpio.o +-obj-$(CONFIG_S3C2410_CLOCK) += clock.o + + # Machine support + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2410/dma.c linux-2.6.28.6/arch/arm/mach-s3c2410/dma.c +--- linux-2.6.28/arch/arm/mach-s3c2410/dma.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2410/dma.c 2009-04-30 09:36:37.000000000 +0200 +@@ -25,12 +25,12 @@ + + #include + #include +-#include ++#include + #include + #include + #include + #include +-#include ++#include + + static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = { + [DMACH_XD0] = { +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2410/include/mach/bast-irq.h linux-2.6.28.6/arch/arm/mach-s3c2410/include/mach/bast-irq.h +--- linux-2.6.28/arch/arm/mach-s3c2410/include/mach/bast-irq.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2410/include/mach/bast-irq.h 2009-12-08 07:35:53.000000000 +0100 +@@ -22,7 +22,7 @@ + #define IRQ_PCSERIAL2 IRQ_EINT14 + #define IRQ_PCPARALLEL IRQ_EINT13 + #define IRQ_ASIX IRQ_EINT11 +-#define IRQ_DM9000 IRQ_EINT10 ++#define IRQ_DM9000 IRQ_EINT7//IRQ_EINT10 + #define IRQ_ISA IRQ_EINT9 + #define IRQ_SMALERT IRQ_EINT8 + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2410/include/mach/gpio-core.h linux-2.6.28.6/arch/arm/mach-s3c2410/include/mach/gpio-core.h +--- linux-2.6.28/arch/arm/mach-s3c2410/include/mach/gpio-core.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2410/include/mach/gpio-core.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,34 @@ ++/* arch/arm/mach-s3c24100/include/mach/gpio-core.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C2410 - GPIO core support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_GPIO_CORE_H ++#define __ASM_ARCH_GPIO_CORE_H __FILE__ ++ ++#include ++#include ++ ++extern struct s3c_gpio_chip s3c24xx_gpios[]; ++ ++static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin) ++{ ++ struct s3c_gpio_chip *chip; ++ ++ if (pin > S3C2410_GPG10) ++ return NULL; ++ ++ chip = &s3c24xx_gpios[pin/32]; ++ return (S3C2410_GPIO_OFFSET(pin) > chip->chip.ngpio) ? chip : NULL; ++} ++ ++#endif /* __ASM_ARCH_GPIO_CORE_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2410/include/mach/irqs.h linux-2.6.28.6/arch/arm/mach-s3c2410/include/mach/irqs.h +--- linux-2.6.28/arch/arm/mach-s3c2410/include/mach/irqs.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2410/include/mach/irqs.h 2009-04-30 09:36:37.000000000 +0200 +@@ -134,6 +134,8 @@ + #define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ + #define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ + ++#define IRQ_HSMMC0 IRQ_S3C2443_HSMMC ++ + #define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) + #define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) + #define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16) +@@ -160,6 +162,12 @@ + #define NR_IRQS (IRQ_S3C2440_AC97+1) + #endif + ++/* compatibility define. */ ++#define IRQ_UART3 IRQ_S3C2443_UART3 ++#define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3 ++#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 ++#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 ++ + /* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ + #define FIQ_START IRQ_EINT0 + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2410/include/mach/map.h linux-2.6.28.6/arch/arm/mach-s3c2410/include/mach/map.h +--- linux-2.6.28/arch/arm/mach-s3c2410/include/mach/map.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2410/include/mach/map.h 2009-04-30 09:36:37.000000000 +0200 +@@ -13,34 +13,20 @@ + #ifndef __ASM_ARCH_MAP_H + #define __ASM_ARCH_MAP_H + ++#include + #include + + #define S3C2410_ADDR(x) S3C_ADDR(x) + +-/* interrupt controller is the first thing we put in, to make +- * the assembly code for the irq detection easier +- */ +-#define S3C24XX_VA_IRQ S3C_VA_IRQ +-#define S3C2410_PA_IRQ (0x4A000000) +-#define S3C24XX_SZ_IRQ SZ_1M +- +-/* memory controller registers */ +-#define S3C24XX_VA_MEMCTRL S3C_VA_MEM +-#define S3C2410_PA_MEMCTRL (0x48000000) +-#define S3C24XX_SZ_MEMCTRL SZ_1M +- + /* USB host controller */ + #define S3C2410_PA_USBHOST (0x49000000) +-#define S3C24XX_SZ_USBHOST SZ_1M + + /* DMA controller */ + #define S3C2410_PA_DMA (0x4B000000) + #define S3C24XX_SZ_DMA SZ_1M + + /* Clock and Power management */ +-#define S3C24XX_VA_CLKPWR S3C_VA_SYS + #define S3C2410_PA_CLKPWR (0x4C000000) +-#define S3C24XX_SZ_CLKPWR SZ_1M + + /* LCD controller */ + #define S3C2410_PA_LCD (0x4D000000) +@@ -48,48 +34,12 @@ + + /* NAND flash controller */ + #define S3C2410_PA_NAND (0x4E000000) +-#define S3C24XX_SZ_NAND SZ_1M +- +-/* UARTs */ +-#define S3C24XX_VA_UART S3C_VA_UART +-#define S3C2410_PA_UART (0x50000000) +-#define S3C24XX_SZ_UART SZ_1M +- +-/* Timers */ +-#define S3C24XX_VA_TIMER S3C_VA_TIMER +-#define S3C2410_PA_TIMER (0x51000000) +-#define S3C24XX_SZ_TIMER SZ_1M +- +-/* USB Device port */ +-#define S3C2410_PA_USBDEV (0x52000000) +-#define S3C24XX_SZ_USBDEV SZ_1M +- +-/* Watchdog */ +-#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG +-#define S3C2410_PA_WATCHDOG (0x53000000) +-#define S3C24XX_SZ_WATCHDOG SZ_1M + + /* IIC hardware controller */ + #define S3C2410_PA_IIC (0x54000000) +-#define S3C24XX_SZ_IIC SZ_1M + + /* IIS controller */ + #define S3C2410_PA_IIS (0x55000000) +-#define S3C24XX_SZ_IIS SZ_1M +- +-/* GPIO ports */ +- +-/* the calculation for the VA of this must ensure that +- * it is the same distance apart from the UART in the +- * phsyical address space, as the initial mapping for the IO +- * is done as a 1:1 maping. This puts it (currently) at +- * 0xFA800000, which is not in the way of any current mapping +- * by the base system. +-*/ +- +-#define S3C2410_PA_GPIO (0x56000000) +-#define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) +-#define S3C24XX_SZ_GPIO SZ_1M + + /* RTC */ + #define S3C2410_PA_RTC (0x57000000) +@@ -97,15 +47,12 @@ + + /* ADC */ + #define S3C2410_PA_ADC (0x58000000) +-#define S3C24XX_SZ_ADC SZ_1M + + /* SPI */ + #define S3C2410_PA_SPI (0x59000000) +-#define S3C24XX_SZ_SPI SZ_1M + + /* SDI */ + #define S3C2410_PA_SDI (0x5A000000) +-#define S3C24XX_SZ_SDI SZ_1M + + /* CAMIF */ + #define S3C2440_PA_CAMIF (0x4F000000) +@@ -120,13 +67,6 @@ + #define S3C2443_PA_HSMMC (0x4A800000) + #define S3C2443_SZ_HSMMC (256) + +-/* ISA style IO, for each machine to sort out mappings for, if it +- * implements it. We reserve two 16M regions for ISA. +- */ +- +-#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000) +-#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000) +- + /* physical addresses of all the chip-select areas */ + + #define S3C2410_CS0 (0x00000000) +@@ -152,27 +92,16 @@ + #define S3C24XX_PA_TIMER S3C2410_PA_TIMER + #define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV + #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG +-#define S3C24XX_PA_IIC S3C2410_PA_IIC + #define S3C24XX_PA_IIS S3C2410_PA_IIS + #define S3C24XX_PA_GPIO S3C2410_PA_GPIO + #define S3C24XX_PA_RTC S3C2410_PA_RTC + #define S3C24XX_PA_ADC S3C2410_PA_ADC + #define S3C24XX_PA_SPI S3C2410_PA_SPI ++#define S3C24XX_PA_SDI S3C2410_PA_SDI ++#define S3C24XX_PA_NAND S3C2410_PA_NAND + +-/* deal with the registers that move under the 2412/2413 */ +- +-#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) +-#ifndef __ASSEMBLY__ +-extern void __iomem *s3c24xx_va_gpio2; +-#endif +-#ifdef CONFIG_CPU_S3C2412_ONLY +-#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10) +-#else +-#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2 +-#endif +-#else +-#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO +-#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO +-#endif ++#define S3C_PA_IIC S3C2410_PA_IIC ++#define S3C_PA_UART S3C24XX_PA_UART ++#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC + + #endif /* __ASM_ARCH_MAP_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2410/include/mach/regs-clock.h linux-2.6.28.6/arch/arm/mach-s3c2410/include/mach/regs-clock.h +--- linux-2.6.28/arch/arm/mach-s3c2410/include/mach/regs-clock.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2410/include/mach/regs-clock.h 2009-04-30 09:36:37.000000000 +0200 +@@ -42,13 +42,6 @@ + #define S3C2410_CLKCON_IIS (1<<17) + #define S3C2410_CLKCON_SPI (1<<18) + +-#define S3C2410_PLLCON_MDIVSHIFT 12 +-#define S3C2410_PLLCON_PDIVSHIFT 4 +-#define S3C2410_PLLCON_SDIVSHIFT 0 +-#define S3C2410_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1) +-#define S3C2410_PLLCON_PDIVMASK ((1<<5)-1) +-#define S3C2410_PLLCON_SDIVMASK 3 +- + /* DCLKCON register addresses in gpio.h */ + + #define S3C2410_DCLKCON_DCLK0EN (1<<0) +@@ -76,32 +69,6 @@ + #define S3C2410_CLKSLOW_SLOWVAL(x) (x) + #define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7) + +-#ifndef __ASSEMBLY__ +- +-#include +- +-static inline unsigned int +-s3c2410_get_pll(unsigned int pllval, unsigned int baseclk) +-{ +- unsigned int mdiv, pdiv, sdiv; +- uint64_t fvco; +- +- mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT; +- pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT; +- sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT; +- +- mdiv &= S3C2410_PLLCON_MDIVMASK; +- pdiv &= S3C2410_PLLCON_PDIVMASK; +- sdiv &= S3C2410_PLLCON_SDIVMASK; +- +- fvco = (uint64_t)baseclk * (mdiv + 8); +- do_div(fvco, (pdiv + 2) << sdiv); +- +- return (unsigned int)fvco; +-} +- +-#endif /* __ASSEMBLY__ */ +- + #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) + + /* extra registers */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2410/include/mach/regs-gpio.h linux-2.6.28.6/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +--- linux-2.6.28/arch/arm/mach-s3c2410/include/mach/regs-gpio.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2410/include/mach/regs-gpio.h 2009-04-30 09:36:37.000000000 +0200 +@@ -1053,13 +1053,6 @@ + #define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C) + #define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90) + +-/* values for S3C2410_EXTINT0/1/2 */ +-#define S3C2410_EXTINT_LOWLEV (0x00) +-#define S3C2410_EXTINT_HILEV (0x01) +-#define S3C2410_EXTINT_FALLEDGE (0x02) +-#define S3C2410_EXTINT_RISEEDGE (0x04) +-#define S3C2410_EXTINT_BOTHEDGE (0x06) +- + /* interrupt filtering conrrol for EINT16..EINT23 */ + #define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94) + #define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2410/include/mach/spi.h linux-2.6.28.6/arch/arm/mach-s3c2410/include/mach/spi.h +--- linux-2.6.28/arch/arm/mach-s3c2410/include/mach/spi.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2410/include/mach/spi.h 2009-04-30 09:36:37.000000000 +0200 +@@ -22,5 +22,12 @@ + void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol); + }; + ++/* Standard setup / suspend routines for SPI GPIO pins. */ ++ ++extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi, ++ int enable); ++ ++extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi, ++ int enable); + + #endif /* __ASM_ARCH_SPI_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2410/include/mach/system-reset.h linux-2.6.28.6/arch/arm/mach-s3c2410/include/mach/system-reset.h +--- linux-2.6.28/arch/arm/mach-s3c2410/include/mach/system-reset.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2410/include/mach/system-reset.h 2009-04-30 09:36:37.000000000 +0200 +@@ -13,7 +13,7 @@ + #include + #include + +-#include ++#include + #include + + #include +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2410/include/mach/tick.h linux-2.6.28.6/arch/arm/mach-s3c2410/include/mach/tick.h +--- linux-2.6.28/arch/arm/mach-s3c2410/include/mach/tick.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2410/include/mach/tick.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,15 @@ ++/* linux/arch/arm/mach-s3c2410/include/mach/tick.h ++ * ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C2410 - timer tick support ++ */ ++ ++#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0)) ++ ++static inline int s3c24xx_ostimer_pending(void) ++{ ++ return __raw_readl(S3C2410_SRCPND) & SRCPND_TIMER4; ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2410/mach-amlm5900.c linux-2.6.28.6/arch/arm/mach-s3c2410/mach-amlm5900.c +--- linux-2.6.28/arch/arm/mach-s3c2410/mach-amlm5900.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2410/mach-amlm5900.c 2009-04-30 09:36:37.000000000 +0200 +@@ -52,6 +52,7 @@ + #include + #include + ++#include + #include + #include + +@@ -150,7 +151,7 @@ + #endif + &s3c_device_adc, + &s3c_device_wdt, +- &s3c_device_i2c, ++ &s3c_device_i2c0, + &s3c_device_usb, + &s3c_device_rtc, + &s3c_device_usbgadget, +@@ -233,6 +234,7 @@ + #ifdef CONFIG_FB_S3C2410 + s3c24xx_fb_set_platdata(&amlm5900_fb_info); + #endif ++ s3c_i2c0_set_platdata(NULL); + platform_add_devices(amlm5900_devices, ARRAY_SIZE(amlm5900_devices)); + } + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2410/mach-bast.c linux-2.6.28.6/arch/arm/mach-s3c2410/mach-bast.c +--- linux-2.6.28/arch/arm/mach-s3c2410/mach-bast.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2410/mach-bast.c 2009-04-30 09:36:37.000000000 +0200 +@@ -44,8 +44,8 @@ + #include + #include + +-#include +-#include ++#include ++#include + #include + + #include +@@ -406,7 +406,7 @@ + * standard 100KHz i2c bus frequency + */ + +-static struct s3c2410_platform_i2c bast_i2c_info = { ++static struct s3c2410_platform_i2c __initdata bast_i2c_info = { + .flags = 0, + .slave_addr = 0x10, + .bus_freq = 100*1000, +@@ -553,7 +553,7 @@ + &s3c_device_usb, + &s3c_device_lcd, + &s3c_device_wdt, +- &s3c_device_i2c, ++ &s3c_device_i2c0, + &s3c_device_rtc, + &s3c_device_nand, + &bast_device_dm9k, +@@ -588,7 +588,8 @@ + s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks)); + + s3c_device_nand.dev.platform_data = &bast_nand_info; +- s3c_device_i2c.dev.platform_data = &bast_i2c_info; ++ ++ s3c_i2c0_set_platdata(&bast_i2c_info); + + s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); + s3c24xx_init_clocks(0); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2410/mach-h1940.c linux-2.6.28.6/arch/arm/mach-s3c2410/mach-h1940.c +--- linux-2.6.28/arch/arm/mach-s3c2410/mach-h1940.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2410/mach-h1940.c 2009-04-30 09:36:37.000000000 +0200 +@@ -38,11 +38,13 @@ + #include + #include + #include +-#include ++#include ++#include + + #include + #include + #include ++#include + #include + + static struct map_desc h1940_iodesc[] __initdata = { +@@ -183,7 +185,7 @@ + &s3c_device_usb, + &s3c_device_lcd, + &s3c_device_wdt, +- &s3c_device_i2c, ++ &s3c_device_i2c0, + &s3c_device_iis, + &s3c_device_usbgadget, + &s3c_device_leds, +@@ -215,6 +217,7 @@ + + s3c24xx_fb_set_platdata(&h1940_fb_info); + s3c24xx_udc_set_platdata(&h1940_udc_cfg); ++ s3c_i2c0_set_platdata(NULL); + + /* Turn off suspend on both USB ports, and switch the + * selectable USB port to USB device mode. */ +@@ -223,10 +226,9 @@ + S3C2410_MISCCR_USBSUSPND0 | + S3C2410_MISCCR_USBSUSPND1, 0x0); + +- tmp = ( +- 0x78 << S3C2410_PLLCON_MDIVSHIFT) +- | (0x02 << S3C2410_PLLCON_PDIVSHIFT) +- | (0x03 << S3C2410_PLLCON_SDIVSHIFT); ++ tmp = (0x78 << S3C24XX_PLLCON_MDIVSHIFT) ++ | (0x02 << S3C24XX_PLLCON_PDIVSHIFT) ++ | (0x03 << S3C24XX_PLLCON_SDIVSHIFT); + writel(tmp, S3C2410_UPLLCON); + + platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices)); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2410/mach-n30.c linux-2.6.28.6/arch/arm/mach-s3c2410/mach-n30.c +--- linux-2.6.28/arch/arm/mach-s3c2410/mach-n30.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2410/mach-n30.c 2009-04-30 09:36:37.000000000 +0200 +@@ -40,14 +40,14 @@ + #include + #include + +-#include ++#include + #include + + #include + #include + #include + #include +-#include ++#include + + static struct map_desc n30_iodesc[] __initdata = { + /* nothing here yet */ +@@ -320,7 +320,7 @@ + static struct platform_device *n30_devices[] __initdata = { + &s3c_device_lcd, + &s3c_device_wdt, +- &s3c_device_i2c, ++ &s3c_device_i2c0, + &s3c_device_iis, + &s3c_device_usb, + &s3c_device_usbgadget, +@@ -332,7 +332,7 @@ + static struct platform_device *n35_devices[] __initdata = { + &s3c_device_lcd, + &s3c_device_wdt, +- &s3c_device_i2c, ++ &s3c_device_i2c0, + &s3c_device_iis, + &s3c_device_usbgadget, + &n35_button_device, +@@ -501,7 +501,7 @@ + static void __init n30_init(void) + { + s3c24xx_fb_set_platdata(&n30_fb_info); +- s3c_device_i2c.dev.platform_data = &n30_i2ccfg; ++ s3c_device_i2c0.dev.platform_data = &n30_i2ccfg; + s3c24xx_udc_set_platdata(&n30_udc_cfg); + + /* Turn off suspend on both USB ports, and switch the +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2410/mach-otom.c linux-2.6.28.6/arch/arm/mach-s3c2410/mach-otom.c +--- linux-2.6.28/arch/arm/mach-s3c2410/mach-otom.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2410/mach-otom.c 2009-04-30 09:36:37.000000000 +0200 +@@ -35,6 +35,7 @@ + #include + #include + #include ++#include + #include + + static struct map_desc otom11_iodesc[] __initdata = { +@@ -94,7 +95,7 @@ + &s3c_device_usb, + &s3c_device_lcd, + &s3c_device_wdt, +- &s3c_device_i2c, ++ &s3c_device_i2c0, + &s3c_device_iis, + &s3c_device_rtc, + &otom_device_nor, +@@ -109,6 +110,7 @@ + + static void __init otom11_init(void) + { ++ s3c_i2c0_set_platdata(NULL); + platform_add_devices(otom11_devices, ARRAY_SIZE(otom11_devices)); + } + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2410/mach-qt2410.c linux-2.6.28.6/arch/arm/mach-s3c2410/mach-qt2410.c +--- linux-2.6.28/arch/arm/mach-s3c2410/mach-qt2410.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2410/mach-qt2410.c 2009-04-30 09:36:37.000000000 +0200 +@@ -50,10 +50,11 @@ + #include + #include + #include +-#include +-#include ++#include ++#include + #include + #include ++#include + + #include + #include +@@ -247,7 +248,7 @@ + &s3c_device_usb, + &s3c_device_lcd, + &s3c_device_wdt, +- &s3c_device_i2c, ++ &s3c_device_i2c0, + &s3c_device_iis, + &s3c_device_sdi, + &s3c_device_usbgadget, +@@ -349,6 +350,7 @@ + s3c2410_gpio_setpin(S3C2410_GPB0, 1); + + s3c24xx_udc_set_platdata(&qt2410_udc_cfg); ++ s3c_i2c0_set_platdata(NULL); + + s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT); + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2410/mach-smdk2410.c linux-2.6.28.6/arch/arm/mach-s3c2410/mach-smdk2410.c +--- linux-2.6.28/arch/arm/mach-s3c2410/mach-smdk2410.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2410/mach-smdk2410.c 2009-04-30 09:36:37.000000000 +0200 +@@ -47,6 +47,7 @@ + #include + + #include ++#include + + #include + #include +@@ -89,7 +90,7 @@ + &s3c_device_usb, + &s3c_device_lcd, + &s3c_device_wdt, +- &s3c_device_i2c, ++ &s3c_device_i2c0, + &s3c_device_iis, + }; + +@@ -102,6 +103,7 @@ + + static void __init smdk2410_init(void) + { ++ s3c_i2c0_set_platdata(NULL); + platform_add_devices(smdk2410_devices, ARRAY_SIZE(smdk2410_devices)); + smdk_machine_init(); + } +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2410/mach-tct_hammer.c linux-2.6.28.6/arch/arm/mach-s3c2410/mach-tct_hammer.c +--- linux-2.6.28/arch/arm/mach-s3c2410/mach-tct_hammer.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2410/mach-tct_hammer.c 2009-04-30 09:36:37.000000000 +0200 +@@ -45,6 +45,7 @@ + #include + + #include ++#include + #include + #include + +@@ -127,7 +128,7 @@ + static struct platform_device *tct_hammer_devices[] __initdata = { + &s3c_device_adc, + &s3c_device_wdt, +- &s3c_device_i2c, ++ &s3c_device_i2c0, + &s3c_device_usb, + &s3c_device_rtc, + &s3c_device_usbgadget, +@@ -146,6 +147,7 @@ + + static void __init tct_hammer_init(void) + { ++ s3c_i2c0_set_platdata(NULL); + platform_add_devices(tct_hammer_devices, ARRAY_SIZE(tct_hammer_devices)); + } + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2410/mach-vr1000.c linux-2.6.28.6/arch/arm/mach-s3c2410/mach-vr1000.c +--- linux-2.6.28/arch/arm/mach-s3c2410/mach-vr1000.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2410/mach-vr1000.c 2009-04-30 09:36:37.000000000 +0200 +@@ -47,6 +47,7 @@ + #include + #include + #include ++#include + + #include "usb-simtec.h" + #include "nor-simtec.h" +@@ -334,7 +335,7 @@ + &s3c_device_usb, + &s3c_device_lcd, + &s3c_device_wdt, +- &s3c_device_i2c, ++ &s3c_device_i2c0, + &s3c_device_adc, + &serial_device, + &vr1000_dm9k0, +@@ -384,6 +385,7 @@ + + static void __init vr1000_init(void) + { ++ s3c_i2c0_set_platdata(NULL); + platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices)); + + i2c_register_board_info(0, vr1000_i2c_devs, +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2410/s3c2410.c linux-2.6.28.6/arch/arm/mach-s3c2410/s3c2410.c +--- linux-2.6.28/arch/arm/mach-s3c2410/s3c2410.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2410/s3c2410.c 2009-04-30 09:36:37.000000000 +0200 +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -28,6 +29,8 @@ + #include + #include + ++#include ++ + #include + #include + +@@ -35,6 +38,7 @@ + #include + #include + #include ++#include + + /* Initial IO mappings */ + +@@ -59,25 +63,28 @@ + * machine specific initialisation. + */ + +-void __init s3c2410_map_io(struct map_desc *mach_desc, int mach_size) ++void __init s3c2410_map_io(void) + { +- /* register our io-tables */ +- + iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc)); +- iotable_init(mach_desc, mach_size); + } + +-void __init s3c2410_init_clocks(int xtal) ++void __init_or_cpufreq s3c2410_setup_clocks(void) + { ++ struct clk *xtal_clk; + unsigned long tmp; ++ unsigned long xtal; + unsigned long fclk; + unsigned long hclk; + unsigned long pclk; + ++ xtal_clk = clk_get(NULL, "xtal"); ++ xtal = clk_get_rate(xtal_clk); ++ clk_put(xtal_clk); ++ + /* now we've got our machine bits initialised, work out what + * clocks we've got */ + +- fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal); ++ fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal); + + tmp = __raw_readl(S3C2410_CLKDIVN); + +@@ -95,7 +102,13 @@ + * console to use them + */ + +- s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); ++ s3c24xx_setup_clocks(fclk, hclk, pclk); ++} ++ ++void __init s3c2410_init_clocks(int xtal) ++{ ++ s3c24xx_register_baseclocks(xtal); ++ s3c2410_setup_clocks(); + s3c2410_baseclk_add(); + } + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2412/clock.c linux-2.6.28.6/arch/arm/mach-s3c2412/clock.c +--- linux-2.6.28/arch/arm/mach-s3c2412/clock.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2412/clock.c 2009-04-30 09:36:37.000000000 +0200 +@@ -93,12 +93,6 @@ + + /* clock selections */ + +-/* CPU EXTCLK input */ +-static struct clk clk_ext = { +- .name = "extclk", +- .id = -1, +-}; +- + static struct clk clk_erefclk = { + .name = "erefclk", + .id = -1, +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2412/dma.c linux-2.6.28.6/arch/arm/mach-s3c2412/dma.c +--- linux-2.6.28/arch/arm/mach-s3c2412/dma.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2412/dma.c 2009-04-30 09:36:37.000000000 +0200 +@@ -26,13 +26,13 @@ + + #include + #include +-#include ++#include + #include + #include + #include + #include + #include +-#include ++#include + + #define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID } + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2412/mach-jive.c linux-2.6.28.6/arch/arm/mach-s3c2412/mach-jive.c +--- linux-2.6.28/arch/arm/mach-s3c2412/mach-jive.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2412/mach-jive.c 2009-04-30 09:36:37.000000000 +0200 +@@ -31,8 +31,8 @@ + #include + + #include +-#include +-#include ++#include ++#include + + #include + #include +@@ -52,7 +52,8 @@ + #include + #include + #include +-#include ++#include ++#include + + static struct map_desc jive_iodesc[] __initdata = { + }; +@@ -450,14 +451,14 @@ + + /* I2C bus and device configuration. */ + +-static struct s3c2410_platform_i2c jive_i2c_cfg = { ++static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = { + .max_freq = 80 * 1000, + .bus_freq = 50 * 1000, + .flags = S3C_IICFLG_FILTER, + .sda_delay = 2, + }; + +-static struct i2c_board_info jive_i2c_devs[] = { ++static struct i2c_board_info jive_i2c_devs[] __initdata = { + [0] = { + I2C_BOARD_INFO("lis302dl", 0x1c), + .irq = IRQ_EINT14, +@@ -470,7 +471,7 @@ + &s3c_device_usb, + &s3c_device_rtc, + &s3c_device_wdt, +- &s3c_device_i2c, ++ &s3c_device_i2c0, + &s3c_device_lcd, + &jive_device_lcdspi, + &jive_device_wm8750, +@@ -663,7 +664,7 @@ + + spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs)); + +- s3c_device_i2c.dev.platform_data = &jive_i2c_cfg; ++ s3c_i2c0_set_platdata(&jive_i2c_cfg); + i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs)); + + pm_power_off = jive_power_off; +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2412/mach-smdk2413.c linux-2.6.28.6/arch/arm/mach-s3c2412/mach-smdk2413.c +--- linux-2.6.28/arch/arm/mach-s3c2412/mach-smdk2413.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2412/mach-smdk2413.c 2009-04-30 09:36:37.000000000 +0200 +@@ -37,7 +37,8 @@ + #include + + #include +-#include ++#include ++#include + #include + + #include +@@ -105,7 +106,7 @@ + &s3c_device_usb, + //&s3c_device_lcd, + &s3c_device_wdt, +- &s3c_device_i2c, ++ &s3c_device_i2c0, + &s3c_device_iis, + &s3c_device_usbgadget, + }; +@@ -142,6 +143,7 @@ + + + s3c24xx_udc_set_platdata(&smdk2413_udc_cfg); ++ s3c_i2c0_set_platdata(NULL); + + platform_add_devices(smdk2413_devices, ARRAY_SIZE(smdk2413_devices)); + smdk_machine_init(); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2412/mach-vstms.c linux-2.6.28.6/arch/arm/mach-s3c2412/mach-vstms.c +--- linux-2.6.28/arch/arm/mach-s3c2412/mach-vstms.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2412/mach-vstms.c 2009-04-30 09:36:37.000000000 +0200 +@@ -39,7 +39,8 @@ + #include + #include + +-#include ++#include ++#include + + #include + #include +@@ -122,7 +123,7 @@ + static struct platform_device *vstms_devices[] __initdata = { + &s3c_device_usb, + &s3c_device_wdt, +- &s3c_device_i2c, ++ &s3c_device_i2c0, + &s3c_device_iis, + &s3c_device_rtc, + &s3c_device_nand, +@@ -151,6 +152,7 @@ + + static void __init vstms_init(void) + { ++ s3c_i2c0_set_platdata(NULL); + platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices)); + } + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2412/s3c2412.c linux-2.6.28.6/arch/arm/mach-s3c2412/s3c2412.c +--- linux-2.6.28/arch/arm/mach-s3c2412/s3c2412.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2412/s3c2412.c 2009-04-30 09:36:37.000000000 +0200 +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -33,13 +34,15 @@ + #include + #include + ++#include ++ + #include + #include + #include + #include + #include + #include +-#include ++#include + #include + + #include +@@ -47,6 +50,7 @@ + #include + #include + #include ++#include + + #ifndef CONFIG_CPU_S3C2412_ONLY + void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO; +@@ -136,7 +140,7 @@ + * machine specific initialisation. + */ + +-void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size) ++void __init s3c2412_map_io(void) + { + /* move base of IO */ + +@@ -153,20 +157,25 @@ + /* register our io-tables */ + + iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc)); +- iotable_init(mach_desc, mach_size); + } + +-void __init s3c2412_init_clocks(int xtal) ++void __init_or_cpufreq s3c2412_setup_clocks(void) + { ++ struct clk *xtal_clk; + unsigned long tmp; ++ unsigned long xtal; + unsigned long fclk; + unsigned long hclk; + unsigned long pclk; + ++ xtal_clk = clk_get(NULL, "xtal"); ++ xtal = clk_get_rate(xtal_clk); ++ clk_put(xtal_clk); ++ + /* now we've got our machine bits initialised, work out what + * clocks we've got */ + +- fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2); ++ fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2); + + clk_mpll.rate = fclk; + +@@ -183,11 +192,17 @@ + printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", + print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); + ++ s3c24xx_setup_clocks(fclk, hclk, pclk); ++} ++ ++void __init s3c2412_init_clocks(int xtal) ++{ + /* initialise the clocks here, to allow other things like the + * console to use them + */ + +- s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); ++ s3c24xx_register_baseclocks(xtal); ++ s3c2412_setup_clocks(); + s3c2412_baseclk_add(); + } + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2440/Kconfig linux-2.6.28.6/arch/arm/mach-s3c2440/Kconfig +--- linux-2.6.28/arch/arm/mach-s3c2440/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2440/Kconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -28,6 +28,7 @@ + config MACH_ANUBIS + bool "Simtec Electronics ANUBIS" + select CPU_S3C2440 ++ select S3C24XX_DCLK + select PM_SIMTEC if PM + select HAVE_PATA_PLATFORM + help +@@ -37,6 +38,7 @@ + config MACH_OSIRIS + bool "Simtec IM2440D20 (OSIRIS) module" + select CPU_S3C2440 ++ select S3C24XX_DCLK + select PM_SIMTEC if PM + help + Say Y here if you are using the Simtec IM2440D20 module, also +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2440/dma.c linux-2.6.28.6/arch/arm/mach-s3c2440/dma.c +--- linux-2.6.28/arch/arm/mach-s3c2440/dma.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2440/dma.c 2009-04-30 09:36:37.000000000 +0200 +@@ -25,12 +25,12 @@ + + #include + #include +-#include ++#include + #include + #include + #include + #include +-#include ++#include + + static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = { + [DMACH_XD0] = { +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2440/mach-anubis.c linux-2.6.28.6/arch/arm/mach-s3c2440/mach-anubis.c +--- linux-2.6.28/arch/arm/mach-s3c2440/mach-anubis.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2440/mach-anubis.c 2009-04-30 09:36:37.000000000 +0200 +@@ -39,7 +39,8 @@ + #include + #include + #include +-#include ++#include ++#include + + #include + #include +@@ -404,7 +405,7 @@ + &s3c_device_usb, + &s3c_device_wdt, + &s3c_device_adc, +- &s3c_device_i2c, ++ &s3c_device_i2c0, + &s3c_device_rtc, + &s3c_device_nand, + &anubis_device_ide0, +@@ -468,6 +469,7 @@ + + static void __init anubis_init(void) + { ++ s3c_i2c0_set_platdata(NULL); + platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices)); + + i2c_register_board_info(0, anubis_i2c_devs, +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2440/mach-at2440evb.c linux-2.6.28.6/arch/arm/mach-s3c2440/mach-at2440evb.c +--- linux-2.6.28/arch/arm/mach-s3c2440/mach-at2440evb.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2440/mach-at2440evb.c 2009-04-30 09:36:37.000000000 +0200 +@@ -35,7 +35,8 @@ + #include + #include + #include +-#include ++#include ++#include + + #include + #include +@@ -166,7 +167,7 @@ + &s3c_device_usb, + &s3c_device_wdt, + &s3c_device_adc, +- &s3c_device_i2c, ++ &s3c_device_i2c0, + &s3c_device_rtc, + &s3c_device_nand, + &at2440evb_device_eth, +@@ -183,6 +184,7 @@ + + static void __init at2440evb_init(void) + { ++ s3c_i2c0_set_platdata(NULL); + platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices)); + } + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2440/mach-nexcoder.c linux-2.6.28.6/arch/arm/mach-s3c2440/mach-nexcoder.c +--- linux-2.6.28/arch/arm/mach-s3c2440/mach-nexcoder.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2440/mach-nexcoder.c 2009-04-30 09:36:37.000000000 +0200 +@@ -37,6 +37,7 @@ + //#include + #include + #include ++#include + + #include + #include +@@ -107,7 +108,7 @@ + &s3c_device_usb, + &s3c_device_lcd, + &s3c_device_wdt, +- &s3c_device_i2c, ++ &s3c_device_i2c0, + &s3c_device_iis, + &s3c_device_rtc, + &s3c_device_camif, +@@ -142,6 +143,7 @@ + + static void __init nexcoder_init(void) + { ++ s3c_i2c0_set_platdata(NULL); + platform_add_devices(nexcoder_devices, ARRAY_SIZE(nexcoder_devices)); + }; + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2440/mach-osiris.c linux-2.6.28.6/arch/arm/mach-s3c2440/mach-osiris.c +--- linux-2.6.28/arch/arm/mach-s3c2440/mach-osiris.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2440/mach-osiris.c 2009-04-30 09:36:37.000000000 +0200 +@@ -37,7 +37,8 @@ + #include + #include + #include +-#include ++#include ++#include + + #include + #include +@@ -335,7 +336,7 @@ + /* Standard Osiris devices */ + + static struct platform_device *osiris_devices[] __initdata = { +- &s3c_device_i2c, ++ &s3c_device_i2c0, + &s3c_device_wdt, + &s3c_device_nand, + &osiris_pcmcia, +@@ -398,6 +399,8 @@ + sysdev_class_register(&osiris_pm_sysclass); + sysdev_register(&osiris_pm_sysdev); + ++ s3c_i2c0_set_platdata(NULL); ++ + i2c_register_board_info(0, osiris_i2c_devs, + ARRAY_SIZE(osiris_i2c_devs)); + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2440/mach-rx3715.c linux-2.6.28.6/arch/arm/mach-s3c2440/mach-rx3715.c +--- linux-2.6.28/arch/arm/mach-s3c2440/mach-rx3715.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2440/mach-rx3715.c 2009-04-30 09:36:37.000000000 +0200 +@@ -42,7 +42,7 @@ + #include + + #include +-#include ++#include + #include + + #include +@@ -179,7 +179,7 @@ + &s3c_device_usb, + &s3c_device_lcd, + &s3c_device_wdt, +- &s3c_device_i2c, ++ &s3c_device_i2c0, + &s3c_device_iis, + &s3c_device_nand, + }; +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2440/mach-smdk2440.c linux-2.6.28.6/arch/arm/mach-s3c2440/mach-smdk2440.c +--- linux-2.6.28/arch/arm/mach-s3c2440/mach-smdk2440.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2440/mach-smdk2440.c 2009-04-30 09:36:37.000000000 +0200 +@@ -37,6 +37,7 @@ + + #include + #include ++#include + + #include + #include +@@ -152,7 +153,7 @@ + &s3c_device_usb, + &s3c_device_lcd, + &s3c_device_wdt, +- &s3c_device_i2c, ++ &s3c_device_i2c0, + &s3c_device_iis, + }; + +@@ -166,6 +167,7 @@ + static void __init smdk2440_machine_init(void) + { + s3c24xx_fb_set_platdata(&smdk2440_fb_info); ++ s3c_i2c0_set_platdata(NULL); + + platform_add_devices(smdk2440_devices, ARRAY_SIZE(smdk2440_devices)); + smdk_machine_init(); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2443/Kconfig linux-2.6.28.6/arch/arm/mach-s3c2443/Kconfig +--- linux-2.6.28/arch/arm/mach-s3c2443/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2443/Kconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -24,6 +24,7 @@ + bool "SMDK2443" + select CPU_S3C2443 + select MACH_SMDK ++ select S3C_DEV_HSMMC + help + Say Y here if you are using an SMDK2443 + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2443/clock.c linux-2.6.28.6/arch/arm/mach-s3c2443/clock.c +--- linux-2.6.28/arch/arm/mach-s3c2443/clock.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2443/clock.c 2009-04-30 09:36:37.000000000 +0200 +@@ -39,6 +39,8 @@ + + #include + ++#include ++ + #include + #include + #include +@@ -145,12 +147,6 @@ + + /* clock selections */ + +-/* CPU EXTCLK input */ +-static struct clk clk_ext = { +- .name = "ext", +- .id = -1, +-}; +- + static struct clk clk_mpllref = { + .name = "mpllref", + .parent = &clk_xtal, +@@ -165,14 +161,6 @@ + }; + #endif + +-static struct clk clk_epllref; +- +-static struct clk clk_epll = { +- .name = "epll", +- .parent = &clk_epllref, +- .id = -1, +-}; +- + static struct clk clk_i2s_ext = { + .name = "i2s-ext", + .id = -1, +@@ -1011,22 +999,20 @@ + &clk_prediv, + }; + +-void __init s3c2443_init_clocks(int xtal) ++void __init_or_cpufreq s3c2443_setup_clocks(void) + { +- unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); + unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); + unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); ++ struct clk *xtal_clk; ++ unsigned long xtal; + unsigned long pll; + unsigned long fclk; + unsigned long hclk; + unsigned long pclk; +- struct clk *clkp; +- int ret; +- int ptr; + +- /* s3c2443 parents h and p clocks from prediv */ +- clk_h.parent = &clk_prediv; +- clk_p.parent = &clk_prediv; ++ xtal_clk = clk_get(NULL, "xtal"); ++ xtal = clk_get_rate(xtal_clk); ++ clk_put(xtal_clk); + + pll = s3c2443_get_mpll(mpllcon, xtal); + clk_msysclk.rate = pll; +@@ -1036,13 +1022,29 @@ + hclk /= s3c2443_get_hdiv(clkdiv0); + pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1); + +- s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); ++ s3c24xx_setup_clocks(fclk, hclk, pclk); + + printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n", + (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on", + print_mhz(pll), print_mhz(fclk), + print_mhz(hclk), print_mhz(pclk)); + ++ s3c24xx_setup_clocks(fclk, hclk, pclk); ++} ++ ++void __init s3c2443_init_clocks(int xtal) ++{ ++ struct clk *clkp; ++ unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); ++ int ret; ++ int ptr; ++ ++ /* s3c2443 parents h and p clocks from prediv */ ++ clk_h.parent = &clk_prediv; ++ clk_p.parent = &clk_prediv; ++ ++ s3c24xx_register_baseclocks(xtal); ++ s3c2443_setup_clocks(); + s3c2443_clk_initparents(); + + for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { +@@ -1056,7 +1058,7 @@ + } + + clk_epll.rate = s3c2443_get_epll(epllcon, xtal); +- ++ clk_epll.parent = &clk_epllref; + clk_usb_bus.parent = &clk_usb_bus_host; + + /* ensure usb bus clock is within correct rate of 48MHz */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2443/dma.c linux-2.6.28.6/arch/arm/mach-s3c2443/dma.c +--- linux-2.6.28/arch/arm/mach-s3c2443/dma.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2443/dma.c 2009-04-30 09:36:37.000000000 +0200 +@@ -26,12 +26,12 @@ + + #include + #include +-#include ++#include + #include + #include + #include + #include +-#include ++#include + + #define MAP(x) { \ + [0] = (x) | DMA_CH_VALID, \ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2443/mach-smdk2443.c linux-2.6.28.6/arch/arm/mach-s3c2443/mach-smdk2443.c +--- linux-2.6.28/arch/arm/mach-s3c2443/mach-smdk2443.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2443/mach-smdk2443.c 2009-04-30 09:36:37.000000000 +0200 +@@ -37,6 +37,7 @@ + + #include + #include ++#include + + #include + #include +@@ -103,8 +104,8 @@ + + static struct platform_device *smdk2443_devices[] __initdata = { + &s3c_device_wdt, +- &s3c_device_i2c, +- &s3c_device_hsmmc, ++ &s3c_device_i2c0, ++ &s3c_device_hsmmc0, + }; + + static void __init smdk2443_map_io(void) +@@ -116,6 +117,7 @@ + + static void __init smdk2443_machine_init(void) + { ++ s3c_i2c0_set_platdata(NULL); + platform_add_devices(smdk2443_devices, ARRAY_SIZE(smdk2443_devices)); + smdk_machine_init(); + } +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c2443/s3c2443.c linux-2.6.28.6/arch/arm/mach-s3c2443/s3c2443.c +--- linux-2.6.28/arch/arm/mach-s3c2443/s3c2443.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c2443/s3c2443.c 2009-04-30 09:36:37.000000000 +0200 +@@ -81,10 +81,9 @@ + * machine specific initialisation. + */ + +-void __init s3c2443_map_io(struct map_desc *mach_desc, int mach_size) ++void __init s3c2443_map_io(void) + { + iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc)); +- iotable_init(mach_desc, mach_size); + } + + /* need to register class before we actually register the device, and +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/debug-macro.S linux-2.6.28.6/arch/arm/mach-s3c24a0/include/mach/debug-macro.S +--- linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/debug-macro.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c24a0/include/mach/debug-macro.S 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,28 @@ ++/* arch/arm/mach-s3c2410/include/mach/debug-macro.S ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++/* pull in the relevant register and map files. */ ++ ++#include ++#include ++ ++ .macro addruart, rx ++ mrc p15, 0, \rx, c1, c0 ++ tst \rx, #1 ++ ldreq \rx, = S3C24XX_PA_UART ++ ldrne \rx, = S3C24XX_VA_UART ++#if CONFIG_DEBUG_S3C_UART != 0 ++ add \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART) ++#endif ++ .endm ++ ++/* include the reset of the code which will do the work, we're only ++ * compiling for a single cpu processor type so the default of s3c2440 ++ * will be fine with us. ++ */ ++ ++#include +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/io.h linux-2.6.28.6/arch/arm/mach-s3c24a0/include/mach/io.h +--- linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/io.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c24a0/include/mach/io.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,16 @@ ++/* arch/arm/mach-s3c24a0/include/mach/io.h ++ * ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * ++ * IO access and mapping routines for the S3C24A0 ++ */ ++ ++#ifndef __ASM_ARM_ARCH_IO_H ++#define __ASM_ARM_ARCH_IO_H ++ ++/* No current ISA/PCI bus support. */ ++#define __io(a) ((void __iomem *)(a)) ++#define __mem_pci(a) (a) ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/irqs.h linux-2.6.28.6/arch/arm/mach-s3c24a0/include/mach/irqs.h +--- linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/irqs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c24a0/include/mach/irqs.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,115 @@ ++/* linux/arch/arm/mach-s3c24a0/include/mach/irqs.h ++ * ++ * Copyright (c) 2003-2005 Simtec Electronics ++ * Ben Dooks ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++ ++#ifndef __ASM_ARCH_24A0_IRQS_H ++#define __ASM_ARCH_24A0_IRQS_H __FILE__ ++ ++#define IRQ_EINT0t2 S3C2410_IRQ(0) /* 16 */ ++/* for generic entry-macro.S */ ++#define IRQ_EINT0 IRQ_EINT0t2 ++ ++#define IRQ_EINT3t6 S3C2410_IRQ(1) ++#define IRQ_EINT7t10 S3C2410_IRQ(2) ++#define IRQ_EINT11t14 S3C2410_IRQ(3) ++#define IRQ_EINT15t18 S3C2410_IRQ(4) /* 20 */ ++#define IRQ_TICK S3C2410_IRQ(5) ++#define IRQ_DCTQ S3C2410_IRQ(6) ++#define IRQ_MC S3C2410_IRQ(7) ++#define IRQ_ME S3C2410_IRQ(8) /* 24 */ ++#define IRQ_KEYPAD S3C2410_IRQ(9) ++#define IRQ_TIMER0 S3C2410_IRQ(10) ++#define IRQ_TIMER1 S3C2410_IRQ(11) ++#define IRQ_TIMER2 S3C2410_IRQ(12) ++#define IRQ_TIMER3_4 S3C2410_IRQ(13) ++#define IRQ_OS_TIMER IRQ_TIMER3_4 ++#define IRQ_LCD S3C2410_IRQ(14) ++#define IRQ_CAM_C S3C2410_IRQ(15) ++#define IRQ_WDT_BATFLT S3C2410_IRQ(16) /* 32 */ ++#define IRQ_UART0 S3C2410_IRQ(17) ++#define IRQ_CAM_P S3C2410_IRQ(18) ++#define IRQ_MODEM S3C2410_IRQ(19) ++#define IRQ_DMA S3C2410_IRQ(20) ++#define IRQ_SDI S3C2410_IRQ(21) ++#define IRQ_SPI0 S3C2410_IRQ(22) ++#define IRQ_UART1 S3C2410_IRQ(23) ++#define IRQ_AC97_NFLASH S3C2410_IRQ(24) /* 40 */ ++#define IRQ_USBD S3C2410_IRQ(25) ++#define IRQ_USBH S3C2410_IRQ(26) ++#define IRQ_IIC S3C2410_IRQ(27) ++#define IRQ_IRDA_MSTICK S3C2410_IRQ(28) /* 44 */ ++#define IRQ_VLX_SPI1 S3C2410_IRQ(29) ++#define IRQ_RTC S3C2410_IRQ(30) /* 46 */ ++#define IRQ_ADC_PEN S3C2410_IRQ(31) ++ ++/* interrupts generated from the external interrupts sources */ ++#define IRQ_EINT00 S3C2410_IRQ(32) /* 48 */ ++#define IRQ_EINT1 S3C2410_IRQ(33) ++#define IRQ_EINT2 S3C2410_IRQ(34) ++#define IRQ_EINT3 S3C2410_IRQ(35) ++#define IRQ_EINT4 S3C2410_IRQ(36) ++#define IRQ_EINT5 S3C2410_IRQ(37) ++#define IRQ_EINT6 S3C2410_IRQ(38) ++#define IRQ_EINT7 S3C2410_IRQ(39) ++#define IRQ_EINT8 S3C2410_IRQ(40) ++#define IRQ_EINT9 S3C2410_IRQ(41) ++#define IRQ_EINT10 S3C2410_IRQ(42) ++#define IRQ_EINT11 S3C2410_IRQ(43) ++#define IRQ_EINT12 S3C2410_IRQ(44) ++#define IRQ_EINT13 S3C2410_IRQ(45) ++#define IRQ_EINT14 S3C2410_IRQ(46) ++#define IRQ_EINT15 S3C2410_IRQ(47) ++#define IRQ_EINT16 S3C2410_IRQ(48) ++#define IRQ_EINT17 S3C2410_IRQ(49) ++#define IRQ_EINT18 S3C2410_IRQ(50) ++ ++/* SUB IRQS */ ++#define IRQ_S3CUART_RX0 S3C2410_IRQ(51) /* 67 */ ++#define IRQ_S3CUART_TX0 S3C2410_IRQ(52) ++#define IRQ_S3CUART_ERR0 S3C2410_IRQ(53) ++ ++#define IRQ_S3CUART_RX1 S3C2410_IRQ(54) ++#define IRQ_S3CUART_TX1 S3C2410_IRQ(55) ++#define IRQ_S3CUART_ERR1 S3C2410_IRQ(56) ++ ++#define IRQ_S3CUART_RX2 (0x0) ++#define IRQ_S3CUART_TX2 (0x0) ++#define IRQ_S3CUART_ERR2 (0x0) ++ ++ ++#define IRQ_IRDA S3C2410_IRQ(57) ++#define IRQ_MSTICK S3C2410_IRQ(58) ++#define IRQ_RESERVED0 S3C2410_IRQ(59) ++#define IRQ_RESERVED1 S3C2410_IRQ(60) ++#define IRQ_RESERVED2 S3C2410_IRQ(61) ++#define IRQ_TIMER3 S3C2410_IRQ(62) ++#define IRQ_TIMER4 S3C2410_IRQ(63) ++#define IRQ_WDT S3C2410_IRQ(64) ++#define IRQ_BATFLT S3C2410_IRQ(65) ++#define IRQ_POST S3C2410_IRQ(66) ++#define IRQ_DISP_FIFO S3C2410_IRQ(67) ++#define IRQ_PENUP S3C2410_IRQ(68) ++#define IRQ_PENDN S3C2410_IRQ(69) ++#define IRQ_ADC S3C2410_IRQ(70) ++#define IRQ_DISP_FRAME S3C2410_IRQ(71) ++#define IRQ_NFLASH S3C2410_IRQ(72) ++#define IRQ_AC97 S3C2410_IRQ(73) ++#define IRQ_SPI1 S3C2410_IRQ(74) ++#define IRQ_VLX S3C2410_IRQ(75) ++#define IRQ_DMA0 S3C2410_IRQ(76) ++#define IRQ_DMA1 S3C2410_IRQ(77) ++#define IRQ_DMA2 S3C2410_IRQ(78) ++#define IRQ_DMA3 S3C2410_IRQ(79) ++ ++#define IRQ_TC (0x0) ++ ++#define NR_IRQS (IRQ_DMA3+1) ++ ++#endif /* __ASM_ARCH_24A0_IRQS_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/map.h linux-2.6.28.6/arch/arm/mach-s3c24a0/include/mach/map.h +--- linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/map.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c24a0/include/mach/map.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,85 @@ ++/* linux/arch/arm/mach-s3c24a0/include/mach/map.h ++ * ++ * Copyright 2003,2007 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S3C24A0 - Memory map definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_24A0_MAP_H ++#define __ASM_ARCH_24A0_MAP_H __FILE__ ++ ++#include ++#include ++ ++#define S3C24A0_PA_IO_BASE (0x40000000) ++#define S3C24A0_PA_CLKPWR (0x40000000) ++#define S3C24A0_PA_IRQ (0x40200000) ++#define S3C24A0_PA_DMA (0x40400000) ++#define S3C24A0_PA_MEMCTRL (0x40C00000) ++#define S3C24A0_PA_NAND (0x40C00000) ++#define S3C24A0_PA_SROM (0x40C20000) ++#define S3C24A0_PA_SDRAM (0x40C40000) ++#define S3C24A0_PA_BUSM (0x40CE0000) ++#define S3C24A0_PA_USBHOST (0x41000000) ++#define S3C24A0_PA_MODEMIF (0x41180000) ++#define S3C24A0_PA_IRDA (0x41800000) ++#define S3C24A0_PA_TIMER (0x44000000) ++#define S3C24A0_PA_WATCHDOG (0x44100000) ++#define S3C24A0_PA_RTC (0x44200000) ++#define S3C24A0_PA_UART (0x44400000) ++#define S3C24A0_PA_UART0 (S3C24A0_PA_UART) ++#define S3C24A0_PA_UART1 (S3C24A0_PA_UART + 0x4000) ++#define S3C24A0_PA_SPI (0x44500000) ++#define S3C24A0_PA_IIC (0x44600000) ++#define S3C24A0_PA_IIS (0x44700000) ++#define S3C24A0_PA_GPIO (0x44800000) ++#define S3C24A0_PA_KEYIF (0x44900000) ++#define S3C24A0_PA_USBDEV (0x44A00000) ++#define S3C24A0_PA_AC97 (0x45000000) ++#define S3C24A0_PA_ADC (0x45800000) ++#define S3C24A0_PA_SDI (0x46000000) ++#define S3C24A0_PA_MS (0x46100000) ++#define S3C24A0_PA_LCD (0x4A000000) ++#define S3C24A0_PA_VPOST (0x4A100000) ++ ++/* physical addresses of all the chip-select areas */ ++ ++#define S3C24A0_CS0 (0x00000000) ++#define S3C24A0_CS1 (0x04000000) ++#define S3C24A0_CS2 (0x08000000) ++#define S3C24A0_CS3 (0x0C000000) ++#define S3C24A0_CS4 (0x10000000) ++#define S3C24A0_CS5 (0x40000000) ++ ++#define S3C24A0_SDRAM_PA (S3C24A0_CS4) ++ ++/* Use a single interface for common resources between S3C24XX cpus */ ++ ++#define S3C24XX_PA_IRQ S3C24A0_PA_IRQ ++#define S3C24XX_PA_MEMCTRL S3C24A0_PA_MEMCTRL ++#define S3C24XX_PA_USBHOST S3C24A0_PA_USBHOST ++#define S3C24XX_PA_DMA S3C24A0_PA_DMA ++#define S3C24XX_PA_CLKPWR S3C24A0_PA_CLKPWR ++#define S3C24XX_PA_LCD S3C24A0_PA_LCD ++#define S3C24XX_PA_UART S3C24A0_PA_UART ++#define S3C24XX_PA_TIMER S3C24A0_PA_TIMER ++#define S3C24XX_PA_USBDEV S3C24A0_PA_USBDEV ++#define S3C24XX_PA_WATCHDOG S3C24A0_PA_WATCHDOG ++#define S3C24XX_PA_IIS S3C24A0_PA_IIS ++#define S3C24XX_PA_GPIO S3C24A0_PA_GPIO ++#define S3C24XX_PA_RTC S3C24A0_PA_RTC ++#define S3C24XX_PA_ADC S3C24A0_PA_ADC ++#define S3C24XX_PA_SPI S3C24A0_PA_SPI ++#define S3C24XX_PA_SDI S3C24A0_PA_SDI ++#define S3C24XX_PA_NAND S3C24A0_PA_NAND ++ ++#define S3C_PA_UART S3C24A0_PA_UART ++#define S3C_PA_IIC S3C24A0_PA_IIC ++ ++#endif /* __ASM_ARCH_24A0_MAP_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/memory.h linux-2.6.28.6/arch/arm/mach-s3c24a0/include/mach/memory.h +--- linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/memory.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c24a0/include/mach/memory.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,19 @@ ++/* linux/arch/arm/mach-s3c24a0/include/mach/memory.h ++ * from linux/include/asm-arm/arch-rpc/memory.h ++ * ++ * Copyright (C) 1996,1997,1998 Russell King. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_24A0_MEMORY_H ++#define __ASM_ARCH_24A0_MEMORY_H __FILE__ ++ ++#define PHYS_OFFSET UL(0x10000000) ++ ++#define __virt_to_bus(x) __virt_to_phys(x) ++#define __bus_to_virt(x) __phys_to_virt(x) ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/regs-clock.h linux-2.6.28.6/arch/arm/mach-s3c24a0/include/mach/regs-clock.h +--- linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/regs-clock.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c24a0/include/mach/regs-clock.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,88 @@ ++/* linux/arch/arm/mach-s3c24a0/include/mach/regs-clock.h ++ * ++ * Copyright (c) 2003,2004,2005,2006 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C24A0 clock register definitions ++*/ ++ ++#ifndef __ASM_ARCH_24A0_REGS_CLOCK_H ++#define __ASM_ARCH_24A0_REGS_CLOCK_H __FILE__ ++ ++#define S3C24A0_MPLLCON S3C2410_CLKREG(0x10) ++#define S3C24A0_UPLLCON S3C2410_CLKREG(0x14) ++#define S3C24A0_CLKCON S3C2410_CLKREG(0x20) ++#define S3C24A0_CLKSRC S3C2410_CLKREG(0x24) ++#define S3C24A0_CLKDIVN S3C2410_CLKREG(0x28) ++ ++/* CLKCON register bits */ ++ ++#define S3C24A0_CLKCON_VLX (1<<29) ++#define S3C24A0_CLKCON_VPOST (1<<28) ++#define S3C24A0_CLKCON_WDT (1<<27) /* reserved */ ++#define S3C24A0_CLKCON_MPEGDCTQ (1<<26) ++#define S3C24A0_CLKCON_VPOSTIF (1<<25) ++#define S3C24A0_CLKCON_MPEG4IF (1<<24) ++#define S3C24A0_CLKCON_CAM_UPLL (1<<23) ++#define S3C24A0_CLKCON_LCDC (1<<22) ++#define S3C24A0_CLKCON_CAM_HCLK (1<<21) ++#define S3C24A0_CLKCON_MPEG4 (1<<20) ++#define S3C24A0_CLKCON_KEYPAD (1<<19) ++#define S3C24A0_CLKCON_ADC (1<<18) ++#define S3C24A0_CLKCON_SDI (1<<17) ++#define S3C24A0_CLKCON_MS (1<<16) /* memory stick */ ++#define S3C24A0_CLKCON_USBD (1<<15) ++#define S3C24A0_CLKCON_GPIO (1<<14) ++#define S3C24A0_CLKCON_IIS (1<<13) ++#define S3C24A0_CLKCON_IIC (1<<12) ++#define S3C24A0_CLKCON_SPI (1<<11) ++#define S3C24A0_CLKCON_UART1 (1<<10) ++#define S3C24A0_CLKCON_UART0 (1<<9) ++#define S3C24A0_CLKCON_PWMT (1<<8) ++#define S3C24A0_CLKCON_USBH (1<<7) ++#define S3C24A0_CLKCON_AC97 (1<<6) ++#define S3C24A0_CLKCON_IrDA (1<<4) ++#define S3C24A0_CLKCON_IDLE (1<<2) ++#define S3C24A0_CLKCON_MON (1<<1) ++#define S3C24A0_CLKCON_STOP (1<<0) ++ ++/* CLKSRC register bits */ ++ ++#define S3C24A0_CLKSRC_OSC (1<<8) /* CLKSRC */ ++#define S3C24A0_CLKSRC_UPLL (1<<7) ++#define S3C24A0_CLKSRC_MPLL (1<<5) ++#define S3C24A0_CLKSRC_EXT (1<<4) ++ ++/* Use a single interface with the common code, for s3c24xx */ ++ ++#define S3C2410_MPLLCON S3C24A0_MPLLCON ++#define S3C2410_UPLLCON S3C24A0_UPLLCON ++#define S3C2410_CLKCON S3C24A0_CLKCON ++#define S3C2410_CLKSLOW S3C24A0_CLKSRC ++#define S3C2410_CLKDIVN S3C24A0_CLKDIVN ++ ++#define S3C2410_CLKCON_IDLE S3C24A0_CLKCON_IDLE ++#define S3C2410_CLKCON_POWER S3C24A0_CLKCON_STOP ++#define S3C2410_CLKCON_LCDC S3C24A0_CLKCON_LCDC ++#define S3C2410_CLKCON_USBH S3C24A0_CLKCON_USBH ++#define S3C2410_CLKCON_USBD S3C24A0_CLKCON_USBD ++#define S3C2410_CLKCON_PWMT S3C24A0_CLKCON_PWMT ++#define S3C2410_CLKCON_SDI S3C24A0_CLKCON_SDI ++#define S3C2410_CLKCON_UART0 S3C24A0_CLKCON_UART0 ++#define S3C2410_CLKCON_UART1 S3C24A0_CLKCON_UART1 ++#define S3C2410_CLKCON_GPIO S3C24A0_CLKCON_GPIO ++#define S3C2410_CLKCON_ADC S3C24A0_CLKCON_ADC ++#define S3C2410_CLKCON_IIC S3C24A0_CLKCON_IIC ++#define S3C2410_CLKCON_IIS S3C24A0_CLKCON_IIS ++#define S3C2410_CLKCON_SPI S3C24A0_CLKCON_SPI ++ ++#define S3C2410_CLKSLOW_UCLK_OFF S3C24A0_CLKSRC_UPLL ++#define S3C2410_CLKSLOW_MPLL_OFF S3C24A0_CLKSRC_MPLL ++#define S3C2410_CLKSLOW_SLOW (0xFF) ++#define S3C2410_CLKSLOW_GET_SLOWVAL(x) (0x1) ++ ++#endif /* __ASM_ARCH_24A0_REGS_CLOCK_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/regs-irq.h linux-2.6.28.6/arch/arm/mach-s3c24a0/include/mach/regs-irq.h +--- linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/regs-irq.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c24a0/include/mach/regs-irq.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,25 @@ ++/* linux/arch/arm/mach-s3c24a0/include/mach/regs-irq.h ++ * ++ * Copyright (c) 2003 Simtec Electronics ++ * http://www.simtec.co.uk/products/SWLINUX/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++ ++#ifndef ___ASM_ARCH_24A0_REGS_IRQ_H ++#define ___ASM_ARCH_24A0_REGS_IRQ_H __FILE__ ++ ++ ++#define S3C2410_EINTMASK S3C2410_EINTREG(0x034) ++#define S3C2410_EINTPEND S3C2410_EINTREG(0X038) ++ ++#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x034) ++#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X038) ++ ++#endif /* __ASM_ARCH_24A0_REGS_IRQ_H */ ++ ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/system.h linux-2.6.28.6/arch/arm/mach-s3c24a0/include/mach/system.h +--- linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/system.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c24a0/include/mach/system.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,25 @@ ++/* linux/arch/arm/mach-s3c24a0/include/mach/system.h ++ * ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * ++ * S3C24A0 - System function defines and includes ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++ ++#include ++ ++static void arch_idle(void) ++{ ++ /* currently no specific idle support. */ ++} ++ ++void (*s3c24xx_reset_hook)(void); ++ ++#include +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/tick.h linux-2.6.28.6/arch/arm/mach-s3c24a0/include/mach/tick.h +--- linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/tick.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c24a0/include/mach/tick.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,15 @@ ++/* linux/arch/arm/mach-s3c24a0/include/mach/tick.h ++ * ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C24A0 - timer tick support ++ */ ++ ++#define SUBSRC_TIMER4 (1 << (IRQ_TIMER4 - IRQ_S3CUART_RX0)) ++ ++static inline int s3c24xx_ostimer_pending(void) ++{ ++ return __raw_readl(S3C2410_SUBSRCPND) & SUBSRC_TIMER4; ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/timex.h linux-2.6.28.6/arch/arm/mach-s3c24a0/include/mach/timex.h +--- linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/timex.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c24a0/include/mach/timex.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,18 @@ ++/* linux/arch/arm/mach-s3c24a0/include/mach/timex.h ++ * ++ * Copyright (c) 2008 Simtec Electronics ++ * Ben Dooks ++ * ++ * S3C2410 - time parameters ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_TIMEX_H ++#define __ASM_ARCH_TIMEX_H ++ ++#define CLOCK_TICK_RATE 12000000 ++ ++#endif /* __ASM_ARCH_TIMEX_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/vmalloc.h linux-2.6.28.6/arch/arm/mach-s3c24a0/include/mach/vmalloc.h +--- linux-2.6.28/arch/arm/mach-s3c24a0/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c24a0/include/mach/vmalloc.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,17 @@ ++/* linux/include/asm-arm/arch-s3c24ao/vmalloc.h ++ * ++ * Copyright 2008 Simtec Electronics ++ ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C24A0 vmalloc definition ++*/ ++ ++#ifndef __ASM_ARCH_VMALLOC_H ++#define __ASM_ARCH_VMALLOC_H ++ ++#define VMALLOC_END (0xE0000000) ++ ++#endif /* __ASM_ARCH_VMALLOC_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6400/Kconfig linux-2.6.28.6/arch/arm/mach-s3c6400/Kconfig +--- linux-2.6.28/arch/arm/mach-s3c6400/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6400/Kconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,8 @@ ++# arch/arm/mach-s3c6400/Kconfig ++# ++# Copyright 2008 Openmoko, Inc. ++# Simtec Electronics, Ben Dooks ++# ++# Licensed under GPLv2 ++ ++# Currently nothing here, this will be added later +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6400/Makefile linux-2.6.28.6/arch/arm/mach-s3c6400/Makefile +--- linux-2.6.28/arch/arm/mach-s3c6400/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6400/Makefile 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,15 @@ ++# arch/arm/mach-s3c6400/Makefile ++# ++# Copyright 2008 Openmoko, Inc. ++# Copyright 2008 Simtec Electronics ++# ++# Licensed under GPLv2 ++ ++obj-y := ++obj-m := ++obj-n := ++obj- := ++ ++# Core support for S3C6400 system ++ ++obj-n += blank.o +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6400/Makefile.boot linux-2.6.28.6/arch/arm/mach-s3c6400/Makefile.boot +--- linux-2.6.28/arch/arm/mach-s3c6400/Makefile.boot 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6400/Makefile.boot 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,2 @@ ++ zreladdr-y := 0x50008000 ++params_phys-y := 0x50000100 +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6400/include/mach/debug-macro.S linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/debug-macro.S +--- linux-2.6.28/arch/arm/mach-s3c6400/include/mach/debug-macro.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/debug-macro.S 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,39 @@ ++/* linux/arch/arm/mach-s3c6400/include/mach/debug-macro.S ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++/* pull in the relevant register and map files. */ ++ ++#include ++#include ++ ++ /* note, for the boot process to work we have to keep the UART ++ * virtual address aligned to an 1MiB boundary for the L1 ++ * mapping the head code makes. We keep the UART virtual address ++ * aligned and add in the offset when we load the value here. ++ */ ++ ++ .macro addruart, rx ++ mrc p15, 0, \rx, c1, c0 ++ tst \rx, #1 ++ ldreq \rx, = S3C_PA_UART ++ ldrne \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff) ++#if CONFIG_DEBUG_S3C_UART != 0 ++ add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) ++#endif ++ .endm ++ ++/* include the reset of the code which will do the work, we're only ++ * compiling for a single cpu processor type so the default of s3c2440 ++ * will be fine with us. ++ */ ++ ++#include +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6400/include/mach/dma.h linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/dma.h +--- linux-2.6.28/arch/arm/mach-s3c6400/include/mach/dma.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/dma.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,16 @@ ++/* linux/arch/arm/mach-s3c6400/include/mach/dma.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C6400 - DMA support ++ */ ++ ++#ifndef __ASM_ARCH_DMA_H ++#define __ASM_ARCH_DMA_H __FILE__ ++ ++#include ++ ++#endif /* __ASM_ARCH_IRQ_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6400/include/mach/entry-macro.S linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/entry-macro.S +--- linux-2.6.28/arch/arm/mach-s3c6400/include/mach/entry-macro.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/entry-macro.S 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,44 @@ ++/* linux/arch/arm/mach-s3c6400/include/mach/entry-macro.S ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * Low-level IRQ helper macros for the Samsung S3C64XX series ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++*/ ++ ++#include ++#include ++#include ++ ++ .macro disable_fiq ++ .endm ++ ++ .macro get_irqnr_preamble, base, tmp ++ ldr \base, =S3C_VA_VIC0 ++ .endm ++ ++ .macro arch_ret_to_user, tmp1, tmp2 ++ .endm ++ ++ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ++ ++ @ check the vic0 ++ mov \irqnr, # S3C_IRQ_OFFSET + 31 ++ ldr \irqstat, [ \base, # VIC_IRQ_STATUS ] ++ teq \irqstat, #0 ++ ++ @ otherwise try vic1 ++ addeq \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0) ++ addeq \irqnr, \irqnr, #32 ++ ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] ++ teqeq \irqstat, #0 ++ ++ clzne \irqstat, \irqstat ++ subne \irqnr, \irqnr, \irqstat ++ .endm +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6400/include/mach/gpio-core.h linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/gpio-core.h +--- linux-2.6.28/arch/arm/mach-s3c6400/include/mach/gpio-core.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/gpio-core.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,21 @@ ++/* linux/arch/arm/mach-s3c6400/include/mach/gpio-core.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C64XX - GPIO core support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_GPIO_CORE_H ++#define __ASM_ARCH_GPIO_CORE_H __FILE__ ++ ++/* currently we just include the platform support */ ++#include ++ ++#endif /* __ASM_ARCH_GPIO_CORE_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6400/include/mach/gpio.h linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/gpio.h +--- linux-2.6.28/arch/arm/mach-s3c6400/include/mach/gpio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/gpio.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,96 @@ ++/* linux/arch/arm/mach-s3c6400/include/mach/gpio.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S3C6400 - GPIO lib support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define gpio_get_value __gpio_get_value ++#define gpio_set_value __gpio_set_value ++#define gpio_cansleep __gpio_cansleep ++#define gpio_to_irq __gpio_to_irq ++ ++/* GPIO bank sizes */ ++#define S3C64XX_GPIO_A_NR (8) ++#define S3C64XX_GPIO_B_NR (7) ++#define S3C64XX_GPIO_C_NR (8) ++#define S3C64XX_GPIO_D_NR (5) ++#define S3C64XX_GPIO_E_NR (5) ++#define S3C64XX_GPIO_F_NR (16) ++#define S3C64XX_GPIO_G_NR (7) ++#define S3C64XX_GPIO_H_NR (10) ++#define S3C64XX_GPIO_I_NR (16) ++#define S3C64XX_GPIO_J_NR (12) ++#define S3C64XX_GPIO_K_NR (16) ++#define S3C64XX_GPIO_L_NR (15) ++#define S3C64XX_GPIO_M_NR (6) ++#define S3C64XX_GPIO_N_NR (16) ++#define S3C64XX_GPIO_O_NR (16) ++#define S3C64XX_GPIO_P_NR (15) ++#define S3C64XX_GPIO_Q_NR (9) ++ ++/* GPIO bank numbes */ ++ ++/* CONFIG_S3C_GPIO_SPACE allows the user to select extra ++ * space for debugging purposes so that any accidental ++ * change from one gpio bank to another can be caught. ++*/ ++ ++#define S3C64XX_GPIO_NEXT(__gpio) \ ++ ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) ++ ++enum s3c_gpio_number { ++ S3C64XX_GPIO_A_START = 0, ++ S3C64XX_GPIO_B_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_A), ++ S3C64XX_GPIO_C_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_B), ++ S3C64XX_GPIO_D_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_C), ++ S3C64XX_GPIO_E_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_D), ++ S3C64XX_GPIO_F_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_E), ++ S3C64XX_GPIO_G_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_F), ++ S3C64XX_GPIO_H_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_G), ++ S3C64XX_GPIO_I_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_H), ++ S3C64XX_GPIO_J_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_I), ++ S3C64XX_GPIO_K_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_J), ++ S3C64XX_GPIO_L_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_K), ++ S3C64XX_GPIO_M_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_L), ++ S3C64XX_GPIO_N_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_M), ++ S3C64XX_GPIO_O_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_N), ++ S3C64XX_GPIO_P_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_O), ++ S3C64XX_GPIO_Q_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_P), ++}; ++ ++/* S3C64XX GPIO number definitions. */ ++ ++#define S3C64XX_GPA(_nr) (S3C64XX_GPIO_A_START + (_nr)) ++#define S3C64XX_GPB(_nr) (S3C64XX_GPIO_B_START + (_nr)) ++#define S3C64XX_GPC(_nr) (S3C64XX_GPIO_C_START + (_nr)) ++#define S3C64XX_GPD(_nr) (S3C64XX_GPIO_D_START + (_nr)) ++#define S3C64XX_GPE(_nr) (S3C64XX_GPIO_E_START + (_nr)) ++#define S3C64XX_GPF(_nr) (S3C64XX_GPIO_F_START + (_nr)) ++#define S3C64XX_GPG(_nr) (S3C64XX_GPIO_G_START + (_nr)) ++#define S3C64XX_GPH(_nr) (S3C64XX_GPIO_H_START + (_nr)) ++#define S3C64XX_GPI(_nr) (S3C64XX_GPIO_I_START + (_nr)) ++#define S3C64XX_GPJ(_nr) (S3C64XX_GPIO_J_START + (_nr)) ++#define S3C64XX_GPK(_nr) (S3C64XX_GPIO_K_START + (_nr)) ++#define S3C64XX_GPL(_nr) (S3C64XX_GPIO_L_START + (_nr)) ++#define S3C64XX_GPM(_nr) (S3C64XX_GPIO_M_START + (_nr)) ++#define S3C64XX_GPN(_nr) (S3C64XX_GPIO_N_START + (_nr)) ++#define S3C64XX_GPO(_nr) (S3C64XX_GPIO_O_START + (_nr)) ++#define S3C64XX_GPP(_nr) (S3C64XX_GPIO_P_START + (_nr)) ++#define S3C64XX_GPQ(_nr) (S3C64XX_GPIO_Q_START + (_nr)) ++ ++/* the end of the S3C64XX specific gpios */ ++#define S3C64XX_GPIO_END (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1) ++#define S3C_GPIO_END S3C64XX_GPIO_END ++ ++/* define the number of gpios we need to the one after the GPQ() range */ ++#define ARCH_NR_GPIOS (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1) ++ ++#include +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6400/include/mach/hardware.h linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/hardware.h +--- linux-2.6.28/arch/arm/mach-s3c6400/include/mach/hardware.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/hardware.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,16 @@ ++/* linux/arch/arm/mach-s3c6400/include/mach/hardware.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C6400 - Hardware support ++ */ ++ ++#ifndef __ASM_ARCH_HARDWARE_H ++#define __ASM_ARCH_HARDWARE_H __FILE__ ++ ++/* currently nothing here, placeholder */ ++ ++#endif /* __ASM_ARCH_IRQ_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6400/include/mach/idle.h linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/idle.h +--- linux-2.6.28/arch/arm/mach-s3c6400/include/mach/idle.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/idle.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,24 @@ ++/* linux/arch/arm/mach-s3c6400/include/mach/idle.h ++ * ++ * Copyright (c) 2004 Simtec Electronics ++ * http://www.simtec.co.uk/products/SWLINUX/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C6400 CPU Idle controls ++*/ ++ ++#ifndef __ASM_ARCH_IDLE_H ++#define __ASM_ARCH_IDLE_H __FILE__ ++ ++/* This allows the over-ride of the default idle code, in case there ++ * is any other things to be done over idle (like DVS) ++*/ ++ ++extern void (*s3c64xx_idle)(void); ++ ++extern void s3c64xx_default_idle(void); ++ ++#endif /* __ASM_ARCH_IDLE_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6400/include/mach/irqs.h linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/irqs.h +--- linux-2.6.28/arch/arm/mach-s3c6400/include/mach/irqs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/irqs.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,20 @@ ++/* linux/arch/arm/mach-s3c6400/include/mach/irqs.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C6400 - IRQ definitions ++ */ ++ ++#ifndef __ASM_ARCH_IRQS_H ++#define __ASM_ARCH_IRQS_H __FILE__ ++ ++#ifndef __ASM_ARM_IRQ_H ++#error "Do not include this directly, instead #include " ++#endif ++ ++#include ++ ++#endif /* __ASM_ARCH_IRQ_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6400/include/mach/map.h linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/map.h +--- linux-2.6.28/arch/arm/mach-s3c6400/include/mach/map.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/map.h 2010-04-21 06:39:24.000000000 +0200 +@@ -0,0 +1,199 @@ ++/* linux/arch/arm/mach-s3c6400/include/mach/map.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks a ++ * ++ * S3C64XX - Memory map definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_MAP_H ++#define __ASM_ARCH_MAP_H __FILE__ ++ ++#include ++ ++/* HSMMC units */ ++#define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000)) ++#define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0) ++#define S3C64XX_PA_HSMMC1 S3C64XX_PA_HSMMC(1) ++#define S3C64XX_PA_HSMMC2 S3C64XX_PA_HSMMC(2) ++#define S3C_SZ_HSMMC SZ_1M ++ ++#define S3C_PA_UART (0x7F005000) ++#define S3C_PA_UART0 (S3C_PA_UART + 0x00) ++#define S3C_PA_UART1 (S3C_PA_UART + 0x400) ++#define S3C_PA_UART2 (S3C_PA_UART + 0x800) ++#define S3C_PA_UART3 (S3C_PA_UART + 0xC00) ++#define S3C_UART_OFFSET (0x400) ++ ++/* See notes on UART VA mapping in debug-macro.S */ ++#define S3C_VA_UARTx(x) (S3C_VA_UART + (S3C_PA_UART & 0xfffff) + ((x) * S3C_UART_OFFSET)) ++ ++#define S3C_VA_UART0 S3C_VA_UARTx(0) ++#define S3C_VA_UART1 S3C_VA_UARTx(1) ++#define S3C_VA_UART2 S3C_VA_UARTx(2) ++#define S3C_VA_UART3 S3C_VA_UARTx(3) ++#define S3C_SZ_UART SZ_256 ++ ++#define S3C64XX_PA_SYSCON (0x7E00F000) ++#define S3C64XX_PA_TIMER (0x7F006000) ++#define S3C64XX_PA_IIC0 (0x7F004000) ++#define S3C64XX_PA_IIC1 (0x7F00F000) ++ ++#define S3C64XX_PA_GPIO (0x7F008000) ++#define S3C64XX_VA_GPIO S3C_ADDR(0x00500000) ++#define S3C64XX_SZ_GPIO SZ_4K ++ ++#define S3C64XX_PA_SDRAM (0x50000000) ++#define S3C64XX_PA_VIC0 (0x71200000) ++#define S3C64XX_PA_VIC1 (0x71300000) ++ ++#define S3C64XX_VA_SROMC S3C_VA_SROMC ++#define S3C64XX_PA_SROMC (0x70000000) ++#define S3C64XX_SZ_SROMC SZ_1M ++ ++#define S3C64XX_VA_LCD S3C_VA_LCD ++#define S3C64XX_PA_LCD (0x77100000) ++#define S3C64XX_SZ_LCD SZ_1M ++ ++#define S3C64XX_PA_G2D (0x76100000) ++#define S3C64XX_SZ_G2D SZ_1M ++ ++#define S3C64XX_PA_G3D (0x72000000) ++#define S3C64XX_SZ_G3D SZ_16M ++ ++#define S3C64XX_PA_FIMC (0x78000000) ++#define S3C64XX_SZ_FIMC SZ_1M ++ ++#define S3C64XX_PA_ADC (0x7E00B000) ++//#define S3C64XX_PA_SMC9115 (0x18000000) ++//#define S3C64XX_SZ_SMC9115 SZ_512M ++#define S3C64XX_PA_DM9000 (0x18000000) ++#define S3C64XX_SZ_DM9000 SZ_1M ++#define S3C64XX_VA_DM9000 S3C_ADDR(0x03b00300) ++ ++#define S3C6400_PA_AC97 (0x7F001000) ++ ++#define S3C64XX_PA_IIS (0x7F002000) ++#define S3C64XX_PA_RTC (0x7E005000) ++#define S3C64XX_PA_IIS_V40 (0x7F00D000) ++#define S3C_SZ_IIS SZ_8K ++ ++/* DMA controller */ ++#define S3C64XX_PA_DMA (0x75000000) ++ ++/* place VICs close together */ ++#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00) ++#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) ++ ++/* Host I/F Indirect & Direct */ ++#define S3C64XX_VA_HOSTIFA S3C_ADDR(0x00B00000) ++#define S3C64XX_PA_HOSTIFA (0x74000000) ++#define S3C64XX_SZ_HOSTIFA SZ_1M ++ ++#define S3C64XX_VA_HOSTIFB S3C_ADDR(0x00C00000) ++#define S3C64XX_PA_HOSTIFB (0x74100000) ++#define S3C64XX_SZ_HOSTIFB SZ_1M ++ ++/* TV-ENCODER */ ++#define S3C6400_PA_TVENC (0x76200000) ++#define S5PC100_PA_TVENC (0xF0000000) ++#define S3C_SZ_TVENC SZ_1M ++ ++/* TV-SCALER*/ ++#define S3C6400_PA_TVSCALER (0x76300000) ++#define S3C_SZ_TVSCALER SZ_1M ++ ++/* Rotator */ ++#define S3C6400_PA_ROTATOR (0x77200000) ++#define S3C_SZ_ROTATOR SZ_1M ++ ++/* JPEG */ ++#define S3C6400_PA_JPEG (0x78800000) ++#define S3C_SZ_JPEG SZ_4M ++ ++/* VPP */ ++#define S3C6400_PA_VPP (0x77000000) ++#define S5PC100_PA_VPP (0xF0100000) ++#define S3C_SZ_VPP SZ_1M ++ ++/* MFC */ ++#define S3C6400_PA_MFC (0x7E002000) ++#define S5PC100_PA_MFC (0xF1000000) ++#define S3C_SZ_MFC SZ_4K ++ ++/* NAND flash controller */ ++#define S3C64XX_PA_NAND (0x70200000) ++#define S3C64XX_SZ_NAND SZ_1M ++ ++/* OneNAND */ ++#define S3C64XX_PA_ONENAND (0x70100000) ++#define S3C_SZ_ONENAND SZ_1M ++ ++/* USB Host */ ++#define S3C64XX_PA_USBHOST (0x74300000) ++#define S3C64XX_SZ_USBHOST SZ_1M ++ ++/* USB OTG */ ++#define S3C64XX_VA_OTG S3C_ADDR(0x03900000) ++#define S3C64XX_PA_OTG (0x7C000000) ++#define S3C64XX_SZ_OTG SZ_1M ++ ++/* USB OTG SFR */ ++#define S3C64XX_VA_OTGSFR S3C_ADDR(0x03a00000) ++#define S3C64XX_PA_OTGSFR (0x7C100000) ++#define S3C64XX_SZ_OTGSFR SZ_1M ++ ++#define S3C64XX_PA_KEYPAD (0x7E00A000) ++#define S3C64XX_SZ_KEYPAD SZ_4K ++ ++/* SPI */ ++#define S3C64XX_PA_SPI (0x7F00B000) ++#define S3C64XX_PA_SPI0 (0x7F00B000) ++#define S3C64XX_PA_SPI1 (0x7F00C000) ++#define S3C64XX_SZ_SPI SZ_8K ++#define S3C64XX_SZ_SPI0 SZ_4K ++#define S3C64XX_SZ_SPI1 SZ_4K ++ ++/* Watchdog */ ++#define S3C64XX_PA_WATCHDOG (0x7E004000) ++#define S3C64XX_SZ_WATCHDOG SZ_4K ++ ++/* compatibiltiy defines. */ ++#define S3C_PA_TIMER S3C64XX_PA_TIMER ++#define S3C_PA_HSMMC0 S3C64XX_PA_HSMMC0 ++#define S3C_PA_HSMMC1 S3C64XX_PA_HSMMC1 ++#define S3C_PA_HSMMC2 S3C64XX_PA_HSMMC2 ++#define S3C_PA_IIC S3C64XX_PA_IIC0 ++#define S3C_PA_IIC1 S3C64XX_PA_IIC1 ++ ++#define S3C_PA_RTC S3C64XX_PA_RTC ++ ++#define S3C_PA_SPI S3C64XX_PA_SPI ++#define S3C_PA_SPI0 S3C64XX_PA_SPI0 ++#define S3C_PA_SPI1 S3C64XX_PA_SPI1 ++#define S3C_SZ_SPI S3C64XX_SZ_SPI ++#define S3C_SZ_SPI0 S3C64XX_SZ_SPI0 ++#define S3C_SZ_SPI1 S3C64XX_SZ_SPI1 ++ ++#define S3C_PA_IIS S3C64XX_PA_IIS ++#define S3C_PA_ADC S3C64XX_PA_ADC ++#define S3C_PA_DMA S3C64XX_PA_DMA ++ ++#define S3C_VA_OTG S3C64XX_VA_OTG ++#define S3C_PA_OTG S3C64XX_PA_OTG ++#define S3C_SZ_OTG S3C64XX_SZ_OTG ++ ++#define S3C_VA_OTGSFR S3C64XX_VA_OTGSFR ++#define S3C_PA_OTGSFR S3C64XX_PA_OTGSFR ++#define S3C_SZ_OTGSFR S3C64XX_SZ_OTGSFR ++ ++#define S3C_PA_KEYPAD S3C64XX_PA_KEYPAD ++#define S3C_SZ_KEYPAD S3C64XX_SZ_KEYPAD ++ ++#endif /* __ASM_ARCH_6400_MAP_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6400/include/mach/memory.h linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/memory.h +--- linux-2.6.28/arch/arm/mach-s3c6400/include/mach/memory.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/memory.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,22 @@ ++/* linux/arch/arm/mach-s3c6400/include/mach/memory.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_MEMORY_H ++#define __ASM_ARCH_MEMORY_H ++ ++#define PHYS_OFFSET UL(0x50000000) ++#define CONSISTENT_DMA_SIZE (SZ_8M + SZ_4M + SZ_2M) ++ ++#define __virt_to_bus(x) __virt_to_phys(x) ++#define __bus_to_virt(x) __phys_to_virt(x) ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6400/include/mach/regs-irq.h linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/regs-irq.h +--- linux-2.6.28/arch/arm/mach-s3c6400/include/mach/regs-irq.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/regs-irq.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,69 @@ ++/* linux/arch/arm/mach-s3c6400/include/mach/regs-irq.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S3C64XX - IRQ register definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_REGS_IRQ_H ++#define __ASM_ARCH_REGS_IRQ_H __FILE__ ++ ++#include ++#include ++/* interrupt controller */ ++#define S3C_VIC0REG(x) ((x) + S3C_VA_VIC0) ++#define S3C_VIC1REG(x) ((x) + S3C_VA_VIC1) ++ ++#define S3C64XX_VIC0IRQSTATUS S3C_VIC0REG(0x000) ++#define S3C64XX_VIC1IRQSTATUS S3C_VIC1REG(0x000) ++ ++#define S3C64XX_VIC0FIQSTATUS S3C_VIC0REG(0x004) ++#define S3C64XX_VIC1FIQSTATUS S3C_VIC1REG(0x004) ++ ++#define S3C64XX_VIC0RAWINTR S3C_VIC0REG(0x008) ++#define S3C64XX_VIC1RAWINTR S3C_VIC1REG(0x008) ++ ++#define S3C64XX_VIC0INTSELECT S3C_VIC0REG(0x00C) ++#define S3C64XX_VIC1INTSELECT S3C_VIC1REG(0x00C) ++ ++#define S3C64XX_VIC0INTENABLE S3C_VIC0REG(0x010) ++#define S3C64XX_VIC1INTENABLE S3C_VIC1REG(0x010) ++ ++#define S3C64XX_VIC0INTENCLEAR S3C_VIC0REG(0x014) ++#define S3C64XX_VIC1INTENCLEAR S3C_VIC1REG(0x014) ++ ++#define S3C64XX_VIC0SOFTINT S3C_VIC0REG(0x018) ++#define S3C64XX_VIC1SOFTINT S3C_VIC1REG(0x018) ++ ++#define S3C64XX_VIC0SOFTINTCLEAR S3C_VIC0REG(0x01C) ++#define S3C64XX_VIC1SOFTINTCLEAR S3C_VIC1REG(0x01C) ++ ++#define S3C64XX_VIC0PROTECTION S3C_VIC0REG(0x020) ++#define S3C64XX_VIC1PROTECTION S3C_VIC1REG(0x020) ++ ++#define S3C64XX_VIC0SWPRIORITYMASK S3C_VIC0REG(0x024) ++#define S3C64XX_VIC1SWPRIORITYMASK S3C_VIC1REG(0x024) ++ ++#define S3C64XX_VIC0PRIORITYDAISY S3C_VIC0REG(0x028) ++#define S3C64XX_VIC1PRIORITYDAISY S3C_VIC1REG(0x028) ++ ++#define S3C64XX_VIC0VECTADDR0 S3C_VIC0REG(0x100) ++#define S3C64XX_VIC1VECTADDR0 S3C_VIC1REG(0x100) ++ ++#define S3C64XX_VIC0VECTADDR1 S3C_VIC0REG(0x104) ++#define S3C64XX_VIC1VECTADDR1 S3C_VIC1REG(0x104) ++ ++#define S3C64XX_VIC0VECTADDR2 S3C_VIC0REG(0x108) ++#define S3C64XX_VIC1VECTADDR2 S3C_VIC1REG(0x108) ++ ++#define S3C64XX_VIC0ADDRESS S3C_VIC0REG(0xF00) ++#define S3C64XX_VIC1ADDRESS S3C_VIC1REG(0xF00) ++ ++#endif /* __ASM_ARCH_6400_REGS_IRQ_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6400/include/mach/regs-mem.h linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/regs-mem.h +--- linux-2.6.28/arch/arm/mach-s3c6400/include/mach/regs-mem.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/regs-mem.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,70 @@ ++/* linux/arch/arm/mach-s3c6400/include/mach/regs-mem.h ++ * ++ * Copyright (c) 2004 Simtec Electronics ++ * http://www.simtec.co.uk/products/SWLINUX/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C2410 Memory Control register definitions ++*/ ++ ++#ifndef __ASM_ARM_MEMREGS_H ++#define __ASM_ARM_MEMREGS_H ++ ++#ifndef S3C64XX_MEMREG ++#define S3C64XX_MEMREG(x) (S3C64XX_VA_SROMC + (x)) ++#endif ++ ++ ++/* Bank Idle Cycle Control Registers 0-5 */ ++#define S3C64XX_SROM_BW S3C64XX_MEMREG(0x00) ++ ++#define S3C64XX_SROM_BC0 S3C64XX_MEMREG(0x04) ++#define S3C64XX_SROM_BC1 S3C64XX_MEMREG(0x08) ++#define S3C64XX_SROM_BC2 S3C64XX_MEMREG(0x0C) ++#define S3C64XX_SROM_BC3 S3C64XX_MEMREG(0x10) ++#define S3C64XX_SROM_BC4 S3C64XX_MEMREG(0x14) ++#define S3C64XX_SROM_BC5 S3C64XX_MEMREG(0x18) ++ ++/* SROM BW */ ++#define S3C64XX_SROM_BW_DATA_WIDTH0_8BIT (0 << 0) ++#define S3C64XX_SROM_BW_DATA_WIDTH0_16BIT (1 << 0) ++#define S3C64XX_SROM_BW_DATA_WIDTH0_MASK (1 << 0) ++ ++#define S3C64XX_SROM_BW_WAIT_ENABLE0_DISABLE (0 << 2) ++#define S3C64XX_SROM_BW_WAIT_ENABLE0_ENABLE (1 << 2) ++#define S3C64XX_SROM_BW_WAIT_ENABLE0_MASK (1 << 2) ++ ++#define S3C64XX_SROM_BW_BYTE_ENABLE0_DISABLE (0 << 3) ++#define S3C64XX_SROM_BW_BYTE_ENABLE0_ENABLE (1 << 3) ++#define S3C64XX_SROM_BW_BYTE_ENABLE0_MASK (1 << 3) ++ ++#define S3C64XX_SROM_BW_DATA_WIDTH1_8BIT (0 << 4) ++#define S3C64XX_SROM_BW_DATA_WIDTH1_16BIT (1 << 4) ++#define S3C64XX_SROM_BW_DATA_WIDTH1_MASK (1 << 4) ++ ++#define S3C64XX_SROM_BW_WAIT_ENABLE1_DISABLE (0 << 6) ++#define S3C64XX_SROM_BW_WAIT_ENABLE1_ENABLE (1 << 6) ++#define S3C64XX_SROM_BW_WAIT_ENABLE1_MASK (1 << 6) ++ ++#define S3C64XX_SROM_BW_BYTE_ENABLE1_DISABLE (0 << 7) ++#define S3C64XX_SROM_BW_BYTE_ENABLE1_ENABLE (1 << 7) ++#define S3C64XX_SROM_BW_BYTE_ENABLE1_MASK (1 << 7) ++ ++#define S3C64XX_SROM_BW_DATA_WIDTH2_8BIT (0 << 8) ++#define S3C64XX_SROM_BW_DATA_WIDTH2_16BIT (1 << 8) ++#define S3C64XX_SROM_BW_DATA_WIDTH2_MASK (1 << 8) ++ ++/* SROM BCn */ ++#define S3C64XX_SROM_BCn_TACS(x) (x << 28) ++#define S3C64XX_SROM_BCn_TCOS(x) (x << 24) ++#define S3C64XX_SROM_BCn_TACC(x) (x << 16) ++#define S3C64XX_SROM_BCn_TCOH(x) (x << 12) ++#define S3C64XX_SROM_BCn_TCAH(x) (x << 8) ++#define S3C64XX_SROM_BCn_TACP(x) (x << 4) ++#define S3C64XX_SROM_BCn_PMC_NORMAL (0 << 0) ++#define S3C64XX_SROM_BCn_PMC_4 (1 << 0) ++ ++#endif /* __ASM_ARM_MEMREGS_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6400/include/mach/system.h linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/system.h +--- linux-2.6.28/arch/arm/mach-s3c6400/include/mach/system.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/system.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,48 @@ ++/* linux/arch/arm/mach-s3c6400/include/mach/system.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C6400 - system implementation ++ */ ++ ++#ifndef __ASM_ARCH_SYSTEM_H ++#define __ASM_ARCH_SYSTEM_H __FILE__ ++ ++#include ++#include ++#include ++ ++void (*s3c64xx_idle)(void); ++void (*s3c64xx_reset_hook)(void); ++ ++void s3c64xx_default_idle(void) ++{ ++ /* nothing here yet */ ++} ++ ++static void arch_idle(void) ++{ ++ if (s3c64xx_idle != NULL) ++ (s3c64xx_idle)(); ++ else ++ s3c64xx_default_idle(); ++} ++ ++static void arch_reset(char mode) ++{ ++ void __iomem *wdt_reg; ++ ++ wdt_reg = ioremap(S3C64XX_PA_WATCHDOG,S3C64XX_SZ_WATCHDOG); ++ ++ /* nothing here yet */ ++ ++ writel(S3C2410_WTCNT_CNT, wdt_reg + S3C2410_WTCNT_OFFSET); /* Watchdog Count Register*/ ++ writel(S3C2410_WTCNT_CON, wdt_reg + S3C2410_WTCON_OFFSET); /* Watchdog Controller Register*/ ++ writel(S3C2410_WTCNT_DAT, wdt_reg + S3C2410_WTDAT_OFFSET); /* Watchdog Data Register*/ ++ ++} ++ ++#endif /* __ASM_ARCH_IRQ_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6400/include/mach/tick.h linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/tick.h +--- linux-2.6.28/arch/arm/mach-s3c6400/include/mach/tick.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/tick.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,29 @@ ++/* linux/arch/arm/mach-s3c6400/include/mach/tick.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S3C64XX - Timer tick support definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_TICK_H ++#define __ASM_ARCH_TICK_H __FILE__ ++ ++/* note, the timer interrutps turn up in 2 places, the vic and then ++ * the timer block. We take the VIC as the base at the moment. ++ */ ++static inline u32 s3c24xx_ostimer_pending(void) ++{ ++ u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS); ++ return pend & 1 << (IRQ_TIMER4_VIC - S3C64XX_IRQ_VIC0(0)); ++} ++ ++#define TICK_MAX (0xffffffff) ++ ++#endif /* __ASM_ARCH_6400_TICK_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6400/include/mach/uncompress.h linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/uncompress.h +--- linux-2.6.28/arch/arm/mach-s3c6400/include/mach/uncompress.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/uncompress.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,26 @@ ++/* linux/arch/arm/mach-s3c6400/include/mach/uncompress.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S3C6400 - uncompress code ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_UNCOMPRESS_H ++#define __ASM_ARCH_UNCOMPRESS_H ++ ++#include ++#include ++ ++static void arch_detect_cpu(void) ++{ ++ /* we do not need to do any cpu detection here at the moment. */ ++} ++ ++#endif /* __ASM_ARCH_UNCOMPRESS_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6400/include/mach/usb-control.h linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/usb-control.h +--- linux-2.6.28/arch/arm/mach-s3c6400/include/mach/usb-control.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6400/include/mach/usb-control.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,41 @@ ++/* arch/arm/mach-s3c2410/include/mach/usb-control.h ++ * ++ * Copyright (c) 2004 Simtec Electronics ++ * Ben Dooks ++ * ++ * S3C2410 - usb port information ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_USBCONTROL_H ++#define __ASM_ARCH_USBCONTROL_H "arch/arm/mach-s3c6400/include/mach/usb-control.h" ++ ++#define S3C_HCDFLG_USED (1) ++ ++struct s3c2410_hcd_port { ++ unsigned char flags; ++ unsigned char power; ++ unsigned char oc_status; ++ unsigned char oc_changed; ++}; ++ ++struct s3c2410_hcd_info { ++ struct usb_hcd *hcd; ++ struct s3c2410_hcd_port port[2]; ++ ++ void (*power_control)(int port, int to); ++ void (*enable_oc)(struct s3c2410_hcd_info *, int on); ++ void (*report_oc)(struct s3c2410_hcd_info *, int ports); ++}; ++ ++static void inline s3c2410_usb_report_oc(struct s3c2410_hcd_info *info, int ports) ++{ ++ if (info->report_oc != NULL) { ++ (info->report_oc)(info, ports); ++ } ++} ++ ++#endif /*__ASM_ARCH_USBCONTROL_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6410/Kconfig linux-2.6.28.6/arch/arm/mach-s3c6410/Kconfig +--- linux-2.6.28/arch/arm/mach-s3c6410/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6410/Kconfig 2009-11-01 09:58:26.000000000 +0100 +@@ -0,0 +1,70 @@ ++# arch/arm/mach-s3c6410/Kconfig ++# ++# Copyright 2008 Openmoko, Inc. ++# Copyright 2008 Simtec Electronics ++# ++# Licensed under GPLv2 ++ ++# Configuration options for the S3C6410 CPU ++ ++config CPU_S3C6410 ++ bool ++ select CPU_S3C6400_INIT ++ select CPU_S3C6400_CLOCK ++ help ++ Enable S3C6410 CPU support ++ ++config S3C6410_SETUP_SDHCI ++ bool ++ help ++ Internal helper functions for S3C6410 based SDHCI systems ++ ++config MACH_SMDK6410 ++ bool "SMDK6410" ++ select CPU_S3C6410 ++ select S3C_DEV_HSMMC ++ select S3C_DEV_HSMMC1 ++ select S3C_DEV_HSMMC2 ++# select S3C_DEV_I2C1 ++ select S3C6410_SETUP_SDHCI ++# select S3C64XX_SETUP_I2C1 ++ select S3C_DMA_PL080 ++ help ++ Machine support for the Samsung SMDK6410 ++ ++# At least some of the SMDK6410s were shipped with the card detect ++# for the MMC/SD slots connected to the same input. This means that ++# either the boards need to be altered to have channel0 to an alternate ++# configuration or that only one slot can be used. ++ ++menu "SMDK6410 MMC/SD slot setup" ++ depends on MACH_SMDK6410 ++ ++config SMDK6410_SD_CH0 ++ bool "Use channel 0" ++ depends on MACH_SMDK6410 ++ help ++ Select CON7 (channel 0) as the MMC/SD slot, as ++ at least some SMDK6410 boards come with the ++ resistors fitted so that the card detects for ++ channels 0 and 1 are the same. ++ ++config SMDK6410_SD_CH1 ++ bool "Use channel 1" ++ depends on MACH_SMDK6410 ++ help ++ Select CON6 (channel 1) as the MMC/SD slot, as ++ at least some SMDK6410 boards come with the ++ resistors fitted so that the card detects for ++ channels 0 and 1 are the same. ++ ++config SMDK6410_SD_CH2 ++ bool "Use channel 2" ++ depends on MACH_SMDK6410 ++ help ++ Select CON6 (channel 1) as the MMC/SD slot, as ++ at least some SMDK6410 boards come with the ++ resistors fitted so that the card detects for ++ channels 0 and 1 are the same. ++ ++endmenu +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6410/Makefile linux-2.6.28.6/arch/arm/mach-s3c6410/Makefile +--- linux-2.6.28/arch/arm/mach-s3c6410/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6410/Makefile 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,28 @@ ++# arch/arm/plat-s3c6410/Makefile ++# ++# Copyright 2008 Openmoko, Inc. ++# Copyright 2008 Simtec Electronics ++# ++# Licensed under GPLv2 ++ ++obj-y := ++obj-m := ++obj-n := ++obj- := ++ ++# Core support for S3C6410 system ++ ++obj-$(CONFIG_CPU_S3C6410) += cpu.o ++obj-$(CONFIG_CPU_S3C6410) += dma.o ++obj-$(CONFIG_CPU_S3C6410) += irq.o ++ ++ ++# Helper and device support ++ ++obj-$(CONFIG_S3C6410_SETUP_SDHCI) += setup-sdhci.o ++ ++obj-$(CONFIG_PM) += pm.o ++ ++# machine support ++ ++obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6410/cpu.c linux-2.6.28.6/arch/arm/mach-s3c6410/cpu.c +--- linux-2.6.28/arch/arm/mach-s3c6410/cpu.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6410/cpu.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,133 @@ ++/* linux/arch/arm/mach-s3c6410/cpu.c ++ * ++ * Copyright 2008 Simtec Electronics ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Initial IO mappings */ ++ ++static struct map_desc s3c6410_iodesc[] __initdata = { ++ IODESC_ENT(LCD), ++ IODESC_ENT(SROMC), ++ IODESC_ENT(HOSTIFB), ++ IODESC_ENT(OTG), ++ IODESC_ENT(OTGSFR), ++}; ++ ++static void s3c6410_idle(void) ++{ ++ unsigned long tmp; ++ ++ /* Ensure our idle mode is to go to idle */ ++ /* Set WFI instruction to SLEEP mode */ ++ ++ tmp = __raw_readl(S3C_PWR_CFG); ++ tmp &= ~(0x3<<5); ++ tmp |= (0x1<<5); ++ __raw_writel(tmp, S3C_PWR_CFG); ++ ++ cpu_do_idle(); ++} ++ ++/* s3c6410_map_io ++ * ++ * register the standard cpu IO areas ++*/ ++ ++void __init s3c6410_map_io(void) ++{ ++ iotable_init(s3c6410_iodesc, ARRAY_SIZE(s3c6410_iodesc)); ++ ++ /* initialise device information early */ ++ s3c6410_default_sdhci0(); ++ s3c6410_default_sdhci1(); ++ s3c6410_default_sdhci2(); ++ ++ /* the i2c devices are directly compatible with s3c2440 */ ++ s3c_i2c0_setname("s3c2440-i2c"); ++ s3c_i2c1_setname("s3c2440-i2c"); ++ ++ /* set our idle function */ ++ s3c64xx_idle = s3c6410_idle; ++} ++ ++void __init s3c6410_init_clocks(int xtal) ++{ ++ printk(KERN_DEBUG "%s: initialising clocks\n", __func__); ++ s3c24xx_register_baseclocks(xtal); ++ s3c64xx_register_clocks(); ++ s3c6400_register_clocks(); ++ s3c6400_setup_clocks(); ++#ifdef CONFIG_HAVE_PWM ++ s3c24xx_pwmclk_init(); ++#endif ++} ++ ++void __init s3c6410_init_irq(void) ++{ ++ /* VIC0 is missing IRQ7, VIC1 is fully populated. */ ++ s3c64xx_init_irq(~0 & ~(1 << 7), ~0); ++} ++ ++struct sysdev_class s3c6410_sysclass = { ++ .name = "s3c6410-core", ++}; ++ ++static struct sys_device s3c6410_sysdev = { ++ .cls = &s3c6410_sysclass, ++}; ++ ++static int __init s3c6410_core_init(void) ++{ ++ return sysdev_class_register(&s3c6410_sysclass); ++} ++ ++core_initcall(s3c6410_core_init); ++ ++int __init s3c6410_init(void) ++{ ++ printk("S3C6410: Initialising architecture\n"); ++ ++ return sysdev_register(&s3c6410_sysdev); ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6410/dma.c linux-2.6.28.6/arch/arm/mach-s3c6410/dma.c +--- linux-2.6.28/arch/arm/mach-s3c6410/dma.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6410/dma.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,364 @@ ++/* linux/arch/arm/mach-s3c6410/dma.c ++ * ++ * Copyright (c) 2003-2005,2006 Samsung Electronics ++ * ++ * S3C6410 DMA selection ++ * ++ * http://www.samsung.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++ ++/* DMAC-0 */ ++#define MAP0(x) { \ ++ [0] = (x) | DMA_CH_VALID, \ ++ [1] = (x) | DMA_CH_VALID, \ ++ [2] = (x) | DMA_CH_VALID, \ ++ [3] = (x) | DMA_CH_VALID, \ ++ [4] = (x) | DMA_CH_VALID, \ ++ [5] = (x) | DMA_CH_VALID, \ ++ [6] = (x) | DMA_CH_VALID, \ ++ [7] = (x) | DMA_CH_VALID, \ ++ [8] = (x), \ ++ [9] = (x), \ ++ [10] = (x), \ ++ [11] = (x), \ ++ [12] = (x), \ ++ [13] = (x), \ ++ [14] = (x), \ ++ [15] = (x), \ ++ [16] = (x), \ ++ [17] = (x), \ ++ [18] = (x), \ ++ [19] = (x), \ ++ [20] = (x), \ ++ [21] = (x), \ ++ [22] = (x), \ ++ [23] = (x), \ ++ [24] = (x), \ ++ [25] = (x), \ ++ [26] = (x), \ ++ [27] = (x), \ ++ [28] = (x), \ ++ [29] = (x), \ ++ [30] = (x), \ ++ [31] = (x), \ ++ } ++ ++/* DMAC-1 */ ++#define MAP1(x) { \ ++ [0] = (x), \ ++ [1] = (x), \ ++ [2] = (x), \ ++ [3] = (x), \ ++ [4] = (x), \ ++ [5] = (x), \ ++ [6] = (x), \ ++ [7] = (x), \ ++ [8] = (x) | DMA_CH_VALID, \ ++ [9] = (x) | DMA_CH_VALID, \ ++ [10] = (x) | DMA_CH_VALID, \ ++ [11] = (x) | DMA_CH_VALID, \ ++ [12] = (x) | DMA_CH_VALID, \ ++ [13] = (x) | DMA_CH_VALID, \ ++ [14] = (x) | DMA_CH_VALID, \ ++ [15] = (x) | DMA_CH_VALID, \ ++ [16] = (x), \ ++ [17] = (x), \ ++ [18] = (x), \ ++ [19] = (x), \ ++ [20] = (x), \ ++ [21] = (x), \ ++ [22] = (x), \ ++ [23] = (x), \ ++ [24] = (x), \ ++ [25] = (x), \ ++ [26] = (x), \ ++ [27] = (x), \ ++ [28] = (x), \ ++ [29] = (x), \ ++ [30] = (x), \ ++ [31] = (x), \ ++ } ++ ++/* SDMAC-0 */ ++#define MAP2(x) { \ ++ [0] = (x), \ ++ [1] = (x), \ ++ [2] = (x), \ ++ [3] = (x), \ ++ [4] = (x), \ ++ [5] = (x), \ ++ [6] = (x), \ ++ [7] = (x), \ ++ [8] = (x), \ ++ [9] = (x), \ ++ [10] = (x), \ ++ [11] = (x), \ ++ [12] = (x), \ ++ [13] = (x), \ ++ [14] = (x), \ ++ [15] = (x), \ ++ [16] = (x) | DMA_CH_VALID, \ ++ [17] = (x) | DMA_CH_VALID, \ ++ [18] = (x) | DMA_CH_VALID, \ ++ [19] = (x) | DMA_CH_VALID, \ ++ [20] = (x) | DMA_CH_VALID, \ ++ [21] = (x) | DMA_CH_VALID, \ ++ [22] = (x) | DMA_CH_VALID, \ ++ [23] = (x) | DMA_CH_VALID, \ ++ [24] = (x), \ ++ [25] = (x), \ ++ [26] = (x), \ ++ [27] = (x), \ ++ [28] = (x), \ ++ [29] = (x), \ ++ [30] = (x), \ ++ [31] = (x), \ ++ } ++ ++/* SDMAC-1 */ ++#define MAP3(x) { \ ++ [0] = (x), \ ++ [1] = (x), \ ++ [2] = (x), \ ++ [3] = (x), \ ++ [4] = (x), \ ++ [5] = (x), \ ++ [6] = (x), \ ++ [7] = (x), \ ++ [8] = (x), \ ++ [9] = (x), \ ++ [10] = (x), \ ++ [11] = (x), \ ++ [12] = (x), \ ++ [13] = (x), \ ++ [14] = (x), \ ++ [15] = (x), \ ++ [16] = (x), \ ++ [17] = (x), \ ++ [18] = (x), \ ++ [19] = (x), \ ++ [20] = (x), \ ++ [21] = (x), \ ++ [22] = (x), \ ++ [23] = (x), \ ++ [24] = (x) | DMA_CH_VALID, \ ++ [25] = (x) | DMA_CH_VALID, \ ++ [26] = (x) | DMA_CH_VALID, \ ++ [27] = (x) | DMA_CH_VALID, \ ++ [28] = (x) | DMA_CH_VALID, \ ++ [29] = (x) | DMA_CH_VALID, \ ++ [30] = (x) | DMA_CH_VALID, \ ++ [31] = (x) | DMA_CH_VALID, \ ++ } ++ ++/* SDMAC-0 */ ++#define MAP2_ONENAND(x) { \ ++ [0] = (x), \ ++ [1] = (x), \ ++ [2] = (x), \ ++ [3] = (x) , \ ++ [4] = (x), \ ++ [5] = (x), \ ++ [6] = (x), \ ++ [7] = (x), \ ++ [8] = (x), \ ++ [9] = (x), \ ++ [10] = (x), \ ++ [11] = (x), \ ++ [12] = (x), \ ++ [13] = (x), \ ++ [14] = (x), \ ++ [15] = (x), \ ++ [16] = (x), \ ++ [17] = (x), \ ++ [18] = (x) , \ ++ [19] = (x) | DMA_CH_VALID, \ ++ [20] = (x), \ ++ [21] = (x), \ ++ [22] = (x), \ ++ [23] = (x), \ ++ [24] = (x), \ ++ [25] = (x), \ ++ [26] = (x), \ ++ [27] = (x), \ ++ [28] = (x), \ ++ [29] = (x), \ ++ [30] = (x), \ ++ [31] = (x), \ ++ } ++ ++ ++/* DMAC0 DMA request sources */ ++#define S3C_DMA0_UART0CH0 0 ++#define S3C_DMA0_UART0CH1 1 ++#define S3C_DMA0_UART1CH0 2 ++#define S3C_DMA0_UART1CH1 3 ++#define S3C_DMA0_ONENAND_RX 3 /* Memory to Memory DMA */ ++#define S3C_DMA0_UART2CH0 4 ++#define S3C_DMA0_UART2CH1 5 ++#define S3C_DMA0_UART3CH0 6 ++#define S3C_DMA0_UART3CH1 7 ++#define S3C_DMA0_PCM0_TX 8 ++#define S3C_DMA0_PCM0_RX 9 ++#define S3C_DMA0_I2S0_TX 10 ++#define S3C_DMA0_I2S0_RX 11 ++#define S3C_DMA0_SPI0_TX 12 ++#define S3C_DMA0_SPI0_RX 13 ++#define S3C_DMA0_HSI_TX 14 ++#define S3C_DMA0_HSI_RX 15 ++ ++/* DMAC1 DMA request sources */ ++#define S3C_DMA1_PCM1_TX 0 ++#define S3C_DMA1_PCM1_RX 1 ++#define S3C_DMA1_I2S1_TX 2 ++#define S3C_DMA1_I2S1_RX 3 ++#define S3C_DMA1_SPI1_TX 4 ++#define S3C_DMA1_SPI1_RX 5 ++#define S3C_DMA1_AC97_PCMOUT 6 ++#define S3C_DMA1_AC97_PCMIN 7 ++#define S3C_DMA1_AC97_MICIN 8 ++#define S3C_DMA1_PWM 9 ++#define S3C_DMA1_IRDA 10 ++#define S3C_DMA1_EXT 11 ++ ++ ++static struct s3c_dma_map __initdata s3c6410_dma_mappings[] = { ++ ++ [DMACH_I2S_IN] = { ++ .name = "i2s0-in", ++ .channels = MAP0(S3C_DMA0_I2S0_RX), ++ .hw_addr.from = S3C_DMA0_I2S0_RX, ++ .sdma_sel = 1 << S3C_DMA0_I2S0_RX, ++ }, ++ [DMACH_I2S_OUT] = { ++ .name = "i2s0-out", ++ .channels = MAP0(S3C_DMA0_I2S0_TX), ++ .hw_addr.to = S3C_DMA0_I2S0_TX, ++ .sdma_sel = 1 << S3C_DMA0_I2S0_TX, ++ }, ++ [DMACH_I2S1_IN] = { ++ .name = "i2s1-in", ++ .channels = MAP1(S3C_DMA1_I2S1_RX), ++ .hw_addr.from = S3C_DMA1_I2S1_RX, ++ .sdma_sel = 1 << (S3C_DMA1_I2S1_RX+S3C_DMA1), ++ }, ++ [DMACH_I2S1_OUT] = { ++ .name = "i2s1-out", ++ .channels = MAP1(S3C_DMA1_I2S1_TX), ++ .hw_addr.to = S3C_DMA1_I2S1_TX, ++ .sdma_sel = 1 << (S3C_DMA1_I2S1_TX+S3C_DMA1), ++ }, ++ [DMACH_SPI0_IN] = { ++ .name = "spi0-in", ++ .channels = MAP0(S3C_DMA0_SPI0_RX), ++ .hw_addr.from = S3C_DMA0_SPI0_RX, ++ .sdma_sel = 1 << S3C_DMA0_SPI0_RX, ++ }, ++ [DMACH_SPI0_OUT] = { ++ .name = "spi0-out", ++ .channels = MAP0(S3C_DMA0_SPI0_TX), ++ .hw_addr.to = S3C_DMA0_SPI0_TX, ++ .sdma_sel = 1 << S3C_DMA0_SPI0_TX, ++ }, ++ [DMACH_SPI1_IN] = { ++ .name = "spi1-in", ++ .channels = MAP1(S3C_DMA1_SPI1_RX), ++ .hw_addr.from = S3C_DMA1_SPI1_RX, ++ .sdma_sel = 1 << (S3C_DMA1_SPI1_RX+S3C_DMA1), ++ }, ++ [DMACH_SPI1_OUT] = { ++ .name = "spi1-out", ++ .channels = MAP1(S3C_DMA1_SPI1_TX), ++ .hw_addr.to = S3C_DMA1_SPI1_TX, ++ .sdma_sel = 1 << (S3C_DMA1_SPI1_TX+S3C_DMA1), ++ }, ++ [DMACH_AC97_PCM_OUT] = { ++ .name = "ac97-pcm-out", ++ .channels = MAP1(S3C_DMA1_AC97_PCMOUT), ++ .hw_addr.to = S3C_DMA1_AC97_PCMOUT, ++ .sdma_sel = 1 << (S3C_DMA1_AC97_PCMOUT+S3C_DMA1), ++ }, ++ [DMACH_AC97_PCM_IN] = { ++ .name = "ac97-pcm-in", ++ .channels = MAP1(S3C_DMA1_AC97_PCMIN), ++ .hw_addr.from = S3C_DMA1_AC97_PCMIN, ++ .sdma_sel = 1 << (S3C_DMA1_AC97_PCMIN+S3C_DMA1), ++ }, ++ [DMACH_AC97_MIC_IN] = { ++ .name = "ac97-mic-in", ++ .channels = MAP1(S3C_DMA1_AC97_MICIN), ++ .hw_addr.from = S3C_DMA1_AC97_MICIN, ++ .sdma_sel = 1 << (S3C_DMA1_AC97_MICIN+S3C_DMA1), ++ }, ++ [DMACH_ONENAND_IN] = { ++ .name = "onenand-in", ++ .channels = MAP2_ONENAND(S3C_DMA0_ONENAND_RX), ++ .hw_addr.from = S3C_DMA0_ONENAND_RX, ++ }, ++ [DMACH_3D_M2M] = { ++ .name = "3D-M2M", ++ .channels = MAP1(S3C_DMA1_EXT), ++ .hw_addr.from = S3C_DMA1_EXT, ++ }, ++ [DMACH_I2S_V40_IN] = { ++ .name = "i2s-v40-in", ++ .channels = MAP0(S3C_DMA0_HSI_RX), ++ .hw_addr.from = S3C_DMA0_HSI_RX, ++ .sdma_sel = 1 << S3C_DMA0_HSI_RX, ++ }, ++ [DMACH_I2S_V40_OUT] = { ++ .name = "i2s-v40-out", ++ .channels = MAP0(S3C_DMA0_HSI_TX), ++ .hw_addr.to = S3C_DMA0_HSI_TX, ++ .sdma_sel = 1 << S3C_DMA0_HSI_TX, ++ }, ++}; ++ ++static void s3c6410_dma_select(struct s3c2410_dma_chan *chan, ++ struct s3c_dma_map *map) ++{ ++ chan->map = map; ++} ++ ++static struct s3c_dma_selection __initdata s3c6410_dma_sel = { ++ .select = s3c6410_dma_select, ++ .dcon_mask = 0, ++ .map = s3c6410_dma_mappings, ++ .map_size = ARRAY_SIZE(s3c6410_dma_mappings), ++}; ++ ++static int __init s3c6410_dma_add(struct sys_device *sysdev) ++{ ++ s3c_dma_init(S3C_DMA_CHANNELS, IRQ_DMA0, 0x20); ++ return s3c_dma_init_map(&s3c6410_dma_sel); ++} ++ ++static struct sysdev_driver s3c6410_dma_driver = { ++ .add = s3c6410_dma_add, ++}; ++ ++static int __init s3c6410_dma_init(void) ++{ ++ return sysdev_driver_register(&s3c6410_sysclass, &s3c6410_dma_driver); ++} ++ ++arch_initcall(s3c6410_dma_init); ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6410/irq.c linux-2.6.28.6/arch/arm/mach-s3c6410/irq.c +--- linux-2.6.28/arch/arm/mach-s3c6410/irq.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6410/irq.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,47 @@ ++/* linux/arch/arm/mach-s3c6410/irq.c ++ * ++ * Copyright (c) 2006 Simtec Electronics ++ * Ben Dooks ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++static int s3c6410_irq_add(struct sys_device *sysdev) ++{ ++ return 0; ++} ++ ++static struct sysdev_driver s3c6410_irq_driver = { ++ .add = s3c6410_irq_add, ++ .suspend = s3c64xx_irq_suspend, ++ .resume = s3c64xx_irq_resume, ++}; ++ ++static int s3c6410_irq_init(void) ++{ ++ return sysdev_driver_register(&s3c6410_sysclass, &s3c6410_irq_driver); ++} ++ ++arch_initcall(s3c6410_irq_init); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6410/mach-smdk6410.c linux-2.6.28.6/arch/arm/mach-s3c6410/mach-smdk6410.c +--- linux-2.6.28/arch/arm/mach-s3c6410/mach-smdk6410.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6410/mach-smdk6410.c 2010-07-20 05:04:29.000000000 +0200 +@@ -0,0 +1,524 @@ ++/* linux/arch/arm/mach-s3c6410/mach-smdk6410.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++ ++ ++ ++ ++ ++#ifdef CONFIG_USB_SUPPORT ++#include ++#include ++ ++/* S3C_USB_CLKSRC 0: EPLL 1: CLK_48M */ ++#define S3C_USB_CLKSRC 1 ++ ++#ifdef USB_HOST_PORT2_EN ++#define OTGH_PHY_CLK_VALUE (0x60) /* Serial Interface, otg_phy input clk 48Mhz Oscillator */ ++#else ++//#define OTGH_PHY_CLK_VALUE (0x20) /* UTMI Interface, otg_phy input clk 48Mhz Oscillator */ ++#define OTGH_PHY_CLK_VALUE (0x0) ++ ++#endif ++#endif ++ ++#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK ++#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB ++#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE ++ ++extern struct sys_timer s3c_timer; ++extern void s3c64xx_reserve_bootmem(void); ++ ++//static struct samspi_device spidev_b0_cs0; ++#if 0 ++static struct samspi_device ProtocolADriver_b1_cs0; ++static struct samspi_device spidev_b0_cs1; ++static struct samspi_device ProtocolBDriver_b1_cs1; ++static struct samspi_device spidev_b1_cs2; ++#endif ++ ++static struct spi_board_info __initdata sam_spi_devs[] = { ++ [0] = { ++ .modalias = "spidev", /* Test Interface */ ++ .mode = SPI_MODE_2, /* CPOL=1, CPHA=0 */ ++ .max_speed_hz = 2468013, ++ /* Connected to SPI-0 as 1st Slave */ ++ .bus_num = 0, ++ .irq = IRQ_SPI0, ++ .chip_select = 0, ++// .controller_data = (void *)&spidev_b0_cs0, ++#if 0 ++ }, { ++ .modalias = "ProtocolADriver", ++ .mode = SPI_MODE_2, ++ .max_speed_hz = 1357923, ++ /* Connected to SPI-1 as 1st Slave */ ++ .bus_num = 1, ++ .irq = IRQ_SPI1, ++ .chip_select = 0, ++ .controller_data = (void *)&ProtocolADriver_b1_cs0, ++ }, { ++ .modalias = "spidev", ++ .mode = SPI_MODE_2, ++ .max_speed_hz = 2357923, ++ /* Connected to SPI-0 as 2nd Slave */ ++ .bus_num = 0, ++ .irq = IRQ_SPI0, ++ .chip_select = 1, ++ .controller_data = (void *)&spidev_b0_cs1, ++ }, { ++ .modalias = "ProtocolBDriver", ++ .mode = SPI_MODE_2, ++ .max_speed_hz = 3357923, ++ /* Connected to SPI-1 as 2ndst Slave */ ++ .bus_num = 1, ++ .irq = IRQ_SPI1, ++ .chip_select = 1, ++ .controller_data = (void *)&ProtocolBDriver_b1_cs1, ++ }, { ++ .modalias = "spidev", ++ .mode = SPI_MODE_2, ++ .max_speed_hz = 4357923, ++ /* Connected to SPI-1 as 3rd Slave */ ++ .bus_num = 1, ++ .irq = IRQ_SPI1, ++ .chip_select = 2, ++ .controller_data = (void *)&spidev_b1_cs2, ++#endif ++ }, ++}; ++ ++static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = { ++ [0] = { ++ .hwport = 0, ++ .flags = 0, ++ .ucon = S3C64XX_UCON_DEFAULT, ++ .ulcon = S3C64XX_ULCON_DEFAULT, ++ .ufcon = S3C64XX_UFCON_DEFAULT, ++ }, ++ [1] = { ++ .hwport = 1, ++ .flags = 0, ++ .ucon = S3C64XX_UCON_DEFAULT, ++ .ulcon = S3C64XX_ULCON_DEFAULT, ++ .ufcon = S3C64XX_UFCON_DEFAULT, ++ }, ++ [2] = { ++ .hwport = 2, ++ .flags = 0, ++ .ucon = S3C64XX_UCON_DEFAULT, ++ .ulcon = S3C64XX_ULCON_DEFAULT, ++ .ufcon = S3C64XX_UFCON_DEFAULT, ++ }, ++ [3] = { ++ .hwport = 3, ++ .flags = 0, ++ .ucon = S3C64XX_UCON_DEFAULT, ++ .ulcon = S3C64XX_ULCON_DEFAULT, ++ .ufcon = S3C64XX_UFCON_DEFAULT, ++ }, ++}; ++ ++struct map_desc smdk6410_iodesc[] = { ++ { ++ .virtual = (u32)S3C64XX_VA_DM9000, ++ .pfn = __phys_to_pfn(S3C64XX_PA_DM9000), ++ .length = S3C64XX_SZ_DM9000, ++ .type = MT_DEVICE, ++ }, ++}; ++ ++static struct platform_device *smdk6410_devices[] __initdata = { ++#ifdef CONFIG_SMDK6410_SD_CH0 ++ &s3c_device_hsmmc0, ++#endif ++#ifdef CONFIG_SMDK6410_SD_CH1 ++ &s3c_device_hsmmc1, ++#endif ++#ifdef CONFIG_SMDK6410_SD_CH2 ++ &s3c_device_hsmmc2, ++#endif ++ &s3c_device_wdt, ++ &s3c_device_rtc, ++ &s3c_device_i2c0, ++ //&s3c_device_i2c1, ++ &s3c_device_spi0, ++ &s3c_device_spi1, ++ &s3c_device_keypad, ++#if defined(CONFIG_TOUCHSCREEN_S3C) ++ &s3c_device_ts, ++#endif ++ &s3c_device_dm9000, ++ &s3c_device_lcd, ++ &s3c_device_vpp, ++ &s3c_device_mfc, ++ &s3c_device_tvenc, ++ &s3c_device_tvscaler, ++ &s3c_device_rotator, ++ &s3c_device_jpeg, ++ &s3c_device_nand, ++ &s3c_device_onenand, ++ &s3c_device_usb, ++ &s3c_device_usbgadget, ++ &s3c_device_usb_otghcd, ++ &s3c_device_fimc0, ++ &s3c_device_fimc1, ++ &s3c_device_g2d, ++ &s3c_device_g3d, ++ ++#ifdef CONFIG_S3C64XX_ADC ++ &s3c_device_adc, ++#endif ++ ++#ifdef CONFIG_HAVE_PWM ++ &s3c_device_timer[0], ++ &s3c_device_timer[1], ++#endif ++}; ++ ++static struct i2c_board_info i2c_devs0[] __initdata = { ++ { I2C_BOARD_INFO("24c08", 0x50), }, ++/* { I2C_BOARD_INFO("WM8580", 0x1b), }, */ ++}; ++ ++static struct i2c_board_info i2c_devs1[] __initdata = { ++ { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */ ++ { I2C_BOARD_INFO("WM8580", 0x1b), }, ++}; ++ ++static struct s3c_ts_mach_info s3c_ts_platform __initdata = { ++ .delay = 0xFFFF, ++ .presc = 0xFF, ++ .oversampling_shift = 2, ++ .resol_bit = 12, ++ .s3c_adc_con = ADC_TYPE_2, ++}; ++ ++static struct s3c_adc_mach_info s3c_adc_platform = { ++ /* s3c6410 support 12-bit resolution */ ++ .delay = 10000, ++ .presc = 49, ++ .resolution = 12, ++}; ++ ++#if defined(CONFIG_HAVE_PWM) ++static struct platform_pwm_backlight_data smdk_backlight_data = { ++ .pwm_id = 1, ++ .max_brightness = 255, ++ .dft_brightness = 255, ++ .pwm_period_ns = 78770, ++}; ++ ++static struct platform_device smdk_backlight_device = { ++ .name = "pwm-backlight", ++ .dev = { ++ .parent = &s3c_device_timer[1].dev, ++ .platform_data = &smdk_backlight_data, ++ }, ++}; ++ ++static void __init smdk_backlight_register(void) ++{ ++ int ret = platform_device_register(&smdk_backlight_device); ++ if (ret) ++ printk(KERN_ERR "smdk: failed to register backlight device: %d\n", ret); ++} ++#else ++#define smdk_backlight_register() do { } while (0) ++#endif ++ ++static void __init smdk6410_map_io(void) ++{ ++ s3c_device_nand.name = "s3c6410-nand"; ++ ++ s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc)); ++ s3c24xx_init_clocks(12000000); ++ s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs)); ++ s3c64xx_reserve_bootmem(); ++} ++ ++static void __init smdk6410_smc911x_set(void) ++{ ++ unsigned int tmp; ++ ++ tmp = __raw_readl(S3C64XX_SROM_BW); ++ tmp &= ~(S3C64XX_SROM_BW_WAIT_ENABLE1_MASK | S3C64XX_SROM_BW_WAIT_ENABLE1_MASK | ++ S3C64XX_SROM_BW_DATA_WIDTH1_MASK); ++ tmp |= S3C64XX_SROM_BW_BYTE_ENABLE1_ENABLE | S3C64XX_SROM_BW_WAIT_ENABLE1_ENABLE | ++ S3C64XX_SROM_BW_DATA_WIDTH1_16BIT; ++ ++ __raw_writel(tmp, S3C64XX_SROM_BW); ++ ++ __raw_writel(S3C64XX_SROM_BCn_TACS(0) | S3C64XX_SROM_BCn_TCOS(4) | ++ S3C64XX_SROM_BCn_TACC(13) | S3C64XX_SROM_BCn_TCOH(1) | ++ S3C64XX_SROM_BCn_TCAH(4) | S3C64XX_SROM_BCn_TACP(6) | ++ S3C64XX_SROM_BCn_PMC_NORMAL, S3C64XX_SROM_BC1); ++} ++ ++ ++ ++ ++ ++ ++ ++ ++ ++static void __init smdk6410_machine_init(void) ++{ ++ unsigned int tmp; ++ ++ s3c_device_nand.dev.platform_data = &s3c_nand_mtd_part_info; ++ s3c_device_onenand.dev.platform_data = &s3c_onenand_data; ++ ++ ++ s3c_i2c0_set_platdata(NULL); ++ ++#if defined(CONFIG_TOUCHSCREEN_S3C) ++ s3c_ts_set_platdata(&s3c_ts_platform); ++#endif ++ s3c_adc_set_platdata(&s3c_adc_platform); ++ ++ i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0)); ++ i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); ++ ++ spi_register_board_info(sam_spi_devs, ARRAY_SIZE(sam_spi_devs)); ++ ++ s3c_fimc0_set_platdata(NULL); ++ s3c_fimc1_set_platdata(NULL); ++ ++#ifdef CONFIG_VIDEO_FIMC ++ //s3c_fimc_reset_camera(); ++#endif ++ ++ platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices)); ++ s3c6410_pm_init(); ++ ++ smdk_backlight_register(); ++ ++} ++ ++MACHINE_START(SMDK6410, "SMDK6410") ++ /* Maintainer: Ben Dooks */ ++ .phys_io = S3C_PA_UART & 0xfff00000, ++ .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, ++ .boot_params = S3C64XX_PA_SDRAM + 0x100, ++ ++ .init_irq = s3c6410_init_irq, ++ .map_io = smdk6410_map_io, ++ .init_machine = smdk6410_machine_init, ++ .timer = &s3c64xx_timer, ++MACHINE_END ++ ++#ifdef CONFIG_USB_SUPPORT ++/* Initializes OTG Phy. */ ++void otg_phy_init(void) { ++ ++ writel(readl(S3C_OTHERS)|S3C_OTHERS_USB_SIG_MASK, S3C_OTHERS); ++ writel(0x0, S3C_USBOTG_PHYPWR); /* Power up */ ++ writel(OTGH_PHY_CLK_VALUE, S3C_USBOTG_PHYCLK); ++ writel(0x1, S3C_USBOTG_RSTCON); ++ ++ udelay(50); ++ writel(0x0, S3C_USBOTG_RSTCON); ++ udelay(50); ++} ++EXPORT_SYMBOL(otg_phy_init); ++ ++/* USB Control request data struct must be located here for DMA transfer */ ++struct usb_ctrlrequest usb_ctrl __attribute__((aligned(8))); ++EXPORT_SYMBOL(usb_ctrl); ++ ++/* OTG PHY Power Off */ ++void otg_phy_off(void) { ++ writel(readl(S3C_USBOTG_PHYPWR)|(0x1F<<1), S3C_USBOTG_PHYPWR); ++ writel(readl(S3C_OTHERS)&~S3C_OTHERS_USB_SIG_MASK, S3C_OTHERS); ++} ++EXPORT_SYMBOL(otg_phy_off); ++ ++void usb_host_clk_en(void) { ++ struct clk *otg_clk; ++ ++ switch (S3C_USB_CLKSRC) { ++ case 0: /* epll clk */ ++ writel((readl(S3C_CLK_SRC)& ~S3C6400_CLKSRC_UHOST_MASK) ++ |S3C_CLKSRC_EPLL_CLKSEL|S3C_CLKSRC_UHOST_EPLL, ++ S3C_CLK_SRC); ++ ++ /* USB host colock divider ratio is 2 */ ++ writel((readl(S3C_CLK_DIV1)& ~S3C6400_CLKDIV1_UHOST_MASK) ++ |(1<<20), S3C_CLK_DIV1); ++ break; ++ case 1: /* oscillator 48M clk */ ++ otg_clk = clk_get(NULL, "otg"); ++ clk_enable(otg_clk); ++ writel(readl(S3C_CLK_SRC)& ~S3C6400_CLKSRC_UHOST_MASK, S3C_CLK_SRC); ++ otg_phy_init(); ++ ++ /* USB host colock divider ratio is 1 */ ++ writel(readl(S3C_CLK_DIV1)& ~S3C6400_CLKDIV1_UHOST_MASK, S3C_CLK_DIV1); ++ break; ++ default: ++ printk(KERN_INFO "Unknown USB Host Clock Source\n"); ++ BUG(); ++ break; ++ } ++ ++ writel(readl(S3C_HCLK_GATE)|S3C_CLKCON_HCLK_UHOST|S3C_CLKCON_HCLK_SECUR, ++ S3C_HCLK_GATE); ++ writel(readl(S3C_SCLK_GATE)|S3C_CLKCON_SCLK_UHOST, S3C_SCLK_GATE); ++ ++} ++ ++EXPORT_SYMBOL(usb_host_clk_en); ++#endif ++ ++#if defined(CONFIG_RTC_DRV_S3C) ++/* RTC common Function for samsung APs*/ ++unsigned int s3c_rtc_set_bit_byte(void __iomem *base, uint offset, uint val) ++{ ++ writeb(val, base + offset); ++ ++ return 0; ++} ++ ++unsigned int s3c_rtc_read_alarm_status(void __iomem *base) ++{ ++ return 1; ++} ++ ++void s3c_rtc_set_pie(void __iomem *base, uint to) ++{ ++ unsigned int tmp; ++ ++ tmp = readw(base + S3C2410_RTCCON) & ~S3C_RTCCON_TICEN; ++ ++ if (to) ++ tmp |= S3C_RTCCON_TICEN; ++ ++ writew(tmp, base + S3C2410_RTCCON); ++} ++ ++void s3c_rtc_set_freq_regs(void __iomem *base, uint freq, uint s3c_freq) ++{ ++ unsigned int tmp; ++ ++ tmp = readw(base + S3C2410_RTCCON) & (S3C_RTCCON_TICEN | S3C2410_RTCCON_RTCEN ); ++ writew(tmp, base + S3C2410_RTCCON); ++ s3c_freq = freq; ++ tmp = (32768 / freq)-1; ++ writel(tmp, base + S3C2410_TICNT); ++} ++ ++void s3c_rtc_enable_set(struct platform_device *pdev,void __iomem *base, int en) ++{ ++ unsigned int tmp; ++ ++ if (!en) { ++ tmp = readw(base + S3C2410_RTCCON); ++ writew(tmp & ~ (S3C2410_RTCCON_RTCEN | S3C_RTCCON_TICEN), base + S3C2410_RTCCON); ++ } else { ++ /* re-enable the device, and check it is ok */ ++ if ((readw(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0){ ++ dev_info(&pdev->dev, "rtc disabled, re-enabling\n"); ++ ++ tmp = readw(base + S3C2410_RTCCON); ++ writew(tmp|S3C2410_RTCCON_RTCEN, base+S3C2410_RTCCON); ++ } ++ ++ if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)){ ++ dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n"); ++ ++ tmp = readw(base + S3C2410_RTCCON); ++ writew(tmp& ~S3C2410_RTCCON_CNTSEL, base+S3C2410_RTCCON); ++ } ++ ++ if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)){ ++ dev_info(&pdev->dev, "removing RTCCON_CLKRST\n"); ++ ++ tmp = readw(base + S3C2410_RTCCON); ++ writew(tmp & ~S3C2410_RTCCON_CLKRST, base+S3C2410_RTCCON); ++ } ++ } ++} ++#endif ++ ++#if defined(CONFIG_KEYPAD_S3C) || defined (CONFIG_KEYPAD_S3C_MODULE) ++void s3c_setup_keypad_cfg_gpio(int rows, int columns) ++{ ++ unsigned int gpio; ++ unsigned int end; ++} ++ ++EXPORT_SYMBOL(s3c_setup_keypad_cfg_gpio); ++#endif ++ ++#ifdef CONFIG_MMC_SDHCI_S3C ++void s3c_setup_hsmmc_clock(void) ++{ ++ struct clk *clk; ++ ++ clk = clk_get(NULL, "mmc_bus"); ++} ++EXPORT_SYMBOL(s3c_setup_hsmmc_clock); ++#endif ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6410/pm.c linux-2.6.28.6/arch/arm/mach-s3c6410/pm.c +--- linux-2.6.28/arch/arm/mach-s3c6410/pm.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6410/pm.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,103 @@ ++/* linux/arch/arm/mach-s3c6410/pm.c ++ * ++ * Copyright (c) 2006 Samsung Electronics ++ * ++ * ++ * S3C6410 (and compatible) Power Manager (Suspend-To-RAM) support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++ ++#include ++#include ++//#include ++#include ++#include ++ ++#ifdef CONFIG_S3C2410_PM_DEBUG ++extern void pm_dbg(const char *fmt, ...); ++#define DBG(fmt...) pm_dbg(fmt) ++#else ++#define DBG(fmt...) printk(KERN_DEBUG fmt) ++#endif ++ ++//static void s3c6410_cpu_suspend(void) ++void s3c6410_cpu_suspend(void) ++{ ++ unsigned long tmp; ++ ++ /* issue the standby signal into the pm unit. Note, we ++ * issue a write-buffer drain just in case */ ++ ++ tmp = 0; ++ ++ asm("b 1f\n\t" ++ ".align 5\n\t" ++ "1:\n\t" ++ "mcr p15, 0, %0, c7, c10, 5\n\t" ++ "mcr p15, 0, %0, c7, c10, 4\n\t" ++ "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp)); ++ ++ /* we should never get past here */ ++ ++ panic("sleep resumed to originator?"); ++} ++ ++static void s3c6410_pm_prepare(void) ++{ ++ ++} ++ ++static int s3c6410_pm_add(struct sys_device *sysdev) ++{ ++ pm_cpu_prep = s3c6410_pm_prepare; ++ pm_cpu_sleep = s3c6410_cpu_suspend; ++ ++ return 0; ++} ++ ++static struct sleep_save s3c6410_sleep[] = { ++ ++}; ++ ++static int s3c6410_pm_resume(struct sys_device *dev) ++{ ++ s3c6410_pm_do_restore(s3c6410_sleep, ARRAY_SIZE(s3c6410_sleep)); ++ return 0; ++} ++ ++static struct sysdev_driver s3c6410_pm_driver = { ++ .add = s3c6410_pm_add, ++ .resume = s3c6410_pm_resume, ++}; ++ ++static __init int s3c6410_pm_drvinit(void) ++{ ++ return sysdev_driver_register(&s3c6410_sysclass, &s3c6410_pm_driver); ++} ++ ++arch_initcall(s3c6410_pm_drvinit); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s3c6410/setup-sdhci.c linux-2.6.28.6/arch/arm/mach-s3c6410/setup-sdhci.c +--- linux-2.6.28/arch/arm/mach-s3c6410/setup-sdhci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s3c6410/setup-sdhci.c 2010-04-21 06:34:54.000000000 +0200 +@@ -0,0 +1,119 @@ ++/* linux/arch/arm/mach-s3c6410/setup-sdhci.c ++ * ++ * Copyright 2008 Simtec Electronics ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC) ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ ++ ++char *s3c6410_hsmmc_clksrcs[4] = { ++ [0] = "hsmmc", ++ [1] = "hsmmc", ++ [2] = "mmc_bus", ++ /* [3] = "48m", - note not succesfully used yet */ ++}; ++ ++void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) ++{ ++ unsigned int gpio; ++ unsigned int end; ++ ++ end = S3C64XX_GPG(2 + width); ++ ++ /* Set all the necessary GPG pins to special-function 0 */ ++ for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) { ++ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); ++ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); ++ } ++ s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); ++ s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2)); ++} ++ ++void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev, ++ void __iomem *r, ++ struct mmc_ios *ios, ++ struct mmc_card *card) ++{ ++ u32 ctrl2, ctrl3 = 0; ++ ++ /* don't need to alter anything acording to card-type */ ++ ++ writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4); ++ ++ /* finally, we don't need to add delay values in HS-MMC interface. ++ * all delay values are removed. by scsuh. ++ */ ++ ctrl2 = readl(r + S3C_SDHCI_CONTROL2); ++ ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; ++ ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | ++ S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | ++ S3C_SDHCI_CTRL2_DFCNT_NONE | ++ S3C_SDHCI_CTRL2_ENCLKOUTHOLD); ++ ++ writel(ctrl2, r + S3C_SDHCI_CONTROL2); ++ writel(ctrl3, r + S3C_SDHCI_CONTROL3); ++} ++ ++void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) ++{ ++ unsigned int gpio; ++ unsigned int end; ++ ++ end = S3C64XX_GPH(2 + width); ++ ++ /* Set all the necessary GPG pins to special-function 0 */ ++ for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) { ++ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); ++ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); ++ } ++ ++ s3c_gpio_setpull(S3C64XX_GPN(6), S3C_GPIO_PULL_UP); ++ s3c_gpio_cfgpin(S3C64XX_GPN(6), S3C_GPIO_SFN(3)); ++ ++ ++} ++ ++void s3c6410_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) ++{ ++ unsigned int gpio; ++ unsigned int end; ++ ++ /* CMD */ ++ s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C_GPIO_SFN(3)); ++ s3c_gpio_setpull(S3C64XX_GPC(4), S3C_GPIO_PULL_NONE); ++ ++ /* CLK */ ++ s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C_GPIO_SFN(3)); ++ s3c_gpio_setpull(S3C64XX_GPC(5), S3C_GPIO_PULL_NONE); ++ ++ end = S3C64XX_GPH(6+width); ++ ++ /* Set all the necessary GPG pins to special-function 0 */ ++ for (gpio = S3C64XX_GPH(6); gpio < end; gpio++) { ++ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); ++ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); ++ } ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/Kconfig linux-2.6.28.6/arch/arm/mach-s5p6440/Kconfig +--- linux-2.6.28/arch/arm/mach-s5p6440/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/Kconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,70 @@ ++# arch/arm/mach-s5p6440/Kconfig ++# ++# Copyright 2008 Openmoko, Inc. ++# Copyright 2008 Simtec Electronics ++# ++# Licensed under GPLv2 ++ ++# Configuration options for the S5P6440 CPU ++ ++config CPU_S5P6440 ++ bool ++ select CPU_S5P6440_INIT ++ select CPU_S5P6440_CLOCK ++ help ++ Enable S5P6440 CPU support ++ ++config S5P6440_SETUP_SDHCI ++ bool ++ help ++ Internal helper functions for S5P6440 based SDHCI systems ++ ++config MACH_SMDK6440 ++ bool "SMDK6440" ++ select CPU_S5P6440 ++ select S3C_DEV_HSMMC ++ select S3C_DEV_HSMMC1 ++ select S3C_DEV_HSMMC2 ++ select S3C_DEV_I2C1 ++ select S5P6440_SETUP_SDHCI ++ select S5P64XX_SETUP_I2C1 ++ select S3C_DMA_PL330 ++ help ++ Machine support for the Samsung SMDK6440 ++ ++# At least some of the SMDK6440s were shipped with the card detect ++# for the MMC/SD slots connected to the same input. This means that ++# either the boards need to be altered to have channel0 to an alternate ++# configuration or that only one slot can be used. ++ ++menu "SMDK6440 MMC/SD slot setup" ++ depends on MACH_SMDK6440 ++ ++config SMDK6440_SD_CH0 ++ bool "Use channel 0" ++ depends on MACH_SMDK6440 ++ help ++ Select CON7 (channel 0) as the MMC/SD slot, as ++ at least some SMDK6440 boards come with the ++ resistors fitted so that the card detects for ++ channels 0 and 1 are the same. ++ ++config SMDK6440_SD_CH1 ++ bool "Use channel 1" ++ depends on MACH_SMDK6440 ++ help ++ Select CON6 (channel 1) as the MMC/SD slot, as ++ at least some SMDK6440 boards come with the ++ resistors fitted so that the card detects for ++ channels 0 and 1 are the same. ++ ++config SMDK6440_SD_CH2 ++ bool "Use channel 2" ++ depends on MACH_SMDK6440 ++ help ++ Select CON6 (channel 1) as the MMC/SD slot, as ++ at least some SMDK6410 boards come with the ++ resistors fitted so that the card detects for ++ channels 0 and 1 are the same. ++ ++endmenu +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/Makefile linux-2.6.28.6/arch/arm/mach-s5p6440/Makefile +--- linux-2.6.28/arch/arm/mach-s5p6440/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/Makefile 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,26 @@ ++# arch/arm/mach-s5p6440/Makefile ++# ++# Copyright 2008 Openmoko, Inc. ++# Copyright 2008 Simtec Electronics ++# ++# Licensed under GPLv2 ++ ++obj-y := ++obj-m := ++obj-n := ++obj- := ++ ++# Core support for S5P6440 system ++ ++obj-$(CONFIG_CPU_S5P6440) += cpu.o ++obj-$(CONFIG_CPU_S5P6440) += dma.o ++ ++# Helper and device support ++ ++obj-$(CONFIG_S5P6440_SETUP_SDHCI) += setup-sdhci.o ++ ++obj-$(CONFIG_PM) += pm.o ++ ++# machine support ++ ++obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/Makefile.boot linux-2.6.28.6/arch/arm/mach-s5p6440/Makefile.boot +--- linux-2.6.28/arch/arm/mach-s5p6440/Makefile.boot 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/Makefile.boot 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,2 @@ ++ zreladdr-y := 0x20008000 ++params_phys-y := 0x20000100 +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/cpu.c linux-2.6.28.6/arch/arm/mach-s5p6440/cpu.c +--- linux-2.6.28/arch/arm/mach-s5p6440/cpu.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/cpu.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,132 @@ ++/* linux/arch/arm/mach-s5p6440/cpu.c ++ * ++ * Copyright 2008 Simtec Electronics ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Initial IO mappings */ ++ ++static struct map_desc s5p6440_iodesc[] __initdata = { ++ IODESC_ENT(LCD), ++ IODESC_ENT(SROMC), ++ IODESC_ENT(HOSTIFB), ++ IODESC_ENT(OTG), ++ IODESC_ENT(OTGSFR), ++}; ++ ++static void s5p6440_idle(void) ++{ ++ unsigned long tmp; ++ ++ /* Ensure our idle mode is to go to idle */ ++ /* Set WFI instruction to SLEEP mode */ ++ ++ tmp = __raw_readl(S3C_PWR_CFG); ++ tmp &= ~(0x3<<5); ++ tmp |= (0x1<<5); ++ __raw_writel(tmp, S3C_PWR_CFG); ++ ++ cpu_do_idle(); ++} ++ ++/* s5p6440_map_io ++ * ++ * register the standard cpu IO areas ++*/ ++ ++void __init s5p6440_map_io(void) ++{ ++ iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc)); ++ ++ /* initialise device information early */ ++ s3c6410_default_sdhci0(); ++ s3c6410_default_sdhci1(); ++ s3c6410_default_sdhci2(); ++ ++ /* the i2c devices are directly compatible with s3c2440 */ ++ s3c_i2c0_setname("s3c2440-i2c"); ++ s3c_i2c1_setname("s3c2440-i2c"); ++ ++ /* set our idle function */ ++ s5p64xx_idle = s5p6440_idle; ++} ++ ++void __init s5p6440_init_clocks(int xtal) ++{ ++ printk(KERN_DEBUG "%s: initialising clocks\n", __func__); ++ s3c24xx_register_baseclocks(xtal); ++ s5p64xx_register_clocks(); ++ s5p6440_register_clocks(); ++ s5p6440_setup_clocks(); ++#ifdef CONFIG_HAVE_PWM ++ s3c24xx_pwmclk_init(); ++#endif ++} ++ ++void __init s5p6440_init_irq(void) ++{ ++ /* VIC0 is missing IRQ7, VIC1 is fully populated. */ ++ s5p64xx_init_irq(~0 & ~(1 << 7), ~0); ++} ++ ++struct sysdev_class s5p6440_sysclass = { ++ .name = "s5p6440-core", ++}; ++ ++static struct sys_device s5p6440_sysdev = { ++ .cls = &s5p6440_sysclass, ++}; ++ ++static int __init s5p6440_core_init(void) ++{ ++ return sysdev_class_register(&s5p6440_sysclass); ++} ++ ++core_initcall(s5p6440_core_init); ++ ++int __init s5p6440_init(void) ++{ ++ printk("S5P6440: Initialising architecture\n"); ++ ++ return sysdev_register(&s5p6440_sysdev); ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/dma.c linux-2.6.28.6/arch/arm/mach-s5p6440/dma.c +--- linux-2.6.28/arch/arm/mach-s5p6440/dma.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/dma.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,155 @@ ++/* linux/arch/arm/mach-s5p6440/dma.c ++ * ++ * Copyright (c) 2003-2005,2006 Samsung Electronics ++ * ++ * S5P6440 DMA selection ++ * ++ * http://www.samsung.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++ ++/* DMAC */ ++#define MAP0(x) { \ ++ [0] = (x) | DMA_CH_VALID, \ ++ [1] = (x) | DMA_CH_VALID, \ ++ [2] = (x) | DMA_CH_VALID, \ ++ [3] = (x) | DMA_CH_VALID, \ ++ [4] = (x) | DMA_CH_VALID, \ ++ [5] = (x) | DMA_CH_VALID, \ ++ [6] = (x) | DMA_CH_VALID, \ ++ [7] = (x) | DMA_CH_VALID, \ ++ } ++ ++ ++/* DMA request sources */ ++#define S3C_DMA0_UART0CH0 0 ++#define S3C_DMA0_UART0CH1 1 ++#define S3C_DMA0_UART1CH0 2 ++#define S3C_DMA0_UART1CH1 3 ++#define S3C_DMA0_UART2CH0 4 ++#define S3C_DMA0_UART2CH1 5 ++#define S3C_DMA0_UART3CH0 6 ++#define S3C_DMA0_UART3CH1 7 ++#define S3C_DMA0_PCM0_TX 10 ++#define S3C_DMA0_PCM0_RX 11 ++#define S3C_DMA0_I2S0_TX 12 ++#define S3C_DMA0_I2S0_RX 13 ++#define S3C_DMA0_SPI0_TX 14 ++#define S3C_DMA0_SPI0_RX 15 ++#define S3C_DMA0_SPI1_TX 20 ++#define S3C_DMA0_SPI1_RX 21 ++#define S3C_DMA0_GPS 24 ++#define S3C_DMA0_PWM 29 ++#define S3C_DMA0_EXTERNAL 31 ++ ++#define S3C_DMA_M2M 0 ++ ++ ++static struct s3c_dma_map __initdata s5p6440_dma_mappings[] = { ++ ++ [DMACH_I2S_IN] = { ++ .name = "i2s0-in", ++ .channels = MAP0(S3C_DMA0_I2S0_RX), ++ .hw_addr.from = S3C_DMA0_I2S0_RX, ++ }, ++ [DMACH_I2S_OUT] = { ++ .name = "i2s0-out", ++ .channels = MAP0(S3C_DMA0_I2S0_TX), ++ .hw_addr.to = S3C_DMA0_I2S0_TX, ++ }, ++ [DMACH_SPI0_IN] = { ++ .name = "spi0-in", ++ .channels = MAP0(S3C_DMA0_SPI0_RX), ++ .hw_addr.from = S3C_DMA0_SPI0_RX, ++ }, ++ [DMACH_SPI0_OUT] = { ++ .name = "spi0-out", ++ .channels = MAP0(S3C_DMA0_SPI0_TX), ++ .hw_addr.to = S3C_DMA0_SPI0_TX, ++ }, ++ [DMACH_SPI1_IN] = { ++ .name = "spi1-in", ++ .channels = MAP0(S3C_DMA0_SPI1_RX), ++ .hw_addr.from = S3C_DMA0_SPI1_RX, ++ }, ++ [DMACH_SPI1_OUT] = { ++ .name = "spi1-out", ++ .channels = MAP0(S3C_DMA0_SPI1_TX), ++ .hw_addr.to = S3C_DMA0_SPI1_TX, ++ }, ++ [DMACH_AC97_PCM_OUT] = { ++ .name = "ac97-pcm-out", ++ .channels = MAP0(S3C_DMA0_PCM0_TX), ++ .hw_addr.to = S3C_DMA0_PCM0_TX, ++ }, ++ [DMACH_AC97_PCM_IN] = { ++ .name = "ac97-pcm-in", ++ .channels = MAP0(S3C_DMA0_PCM0_RX), ++ .hw_addr.from = S3C_DMA0_PCM0_RX, ++ }, ++ [DMACH_3D_M2M] = { ++ .name = "3D-M2M", ++ .channels = MAP0(S3C_DMA_M2M), ++ .hw_addr.from = 0, ++ }, ++ [DMACH_I2S_V40_IN] = { ++ .name = "i2s-v40-in", ++ .channels = MAP0(S3C_DMA0_I2S0_RX), ++ .hw_addr.from = S3C_DMA0_I2S0_RX, ++ .sdma_sel = 1 << S3C_DMA0_I2S0_RX, ++ }, ++ [DMACH_I2S_V40_OUT] = { ++ .name = "i2s-v40-out", ++ .channels = MAP0(S3C_DMA0_I2S0_TX), ++ .hw_addr.to = S3C_DMA0_I2S0_TX, ++ .sdma_sel = 1 << S3C_DMA0_I2S0_TX, ++ }, ++}; ++ ++static void s5p6440_dma_select(struct s3c2410_dma_chan *chan, ++ struct s3c_dma_map *map) ++{ ++ chan->map = map; ++} ++ ++static struct s3c_dma_selection __initdata s5p6440_dma_sel = { ++ .select = s5p6440_dma_select, ++ .dcon_mask = 0, ++ .map = s5p6440_dma_mappings, ++ .map_size = ARRAY_SIZE(s5p6440_dma_mappings), ++}; ++ ++static int __init s5p6440_dma_add(struct sys_device *sysdev) ++{ ++ s3c_dma_init(S3C_DMA_CHANNELS, IRQ_DMA0, 0x1000); ++ return s3c_dma_init_map(&s5p6440_dma_sel); ++} ++ ++static struct sysdev_driver s5p6440_dma_driver = { ++ .add = s5p6440_dma_add, ++}; ++ ++static int __init s5p6440_dma_init(void) ++{ ++ return sysdev_driver_register(&s5p6440_sysclass, &s5p6440_dma_driver); ++} ++ ++arch_initcall(s5p6440_dma_init); ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/include/mach/debug-macro.S linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/debug-macro.S +--- linux-2.6.28/arch/arm/mach-s5p6440/include/mach/debug-macro.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/debug-macro.S 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,39 @@ ++/* linux/arch/arm/mach-s5p6440/include/mach/debug-macro.S ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++/* pull in the relevant register and map files. */ ++ ++#include ++#include ++ ++ /* note, for the boot process to work we have to keep the UART ++ * virtual address aligned to an 1MiB boundary for the L1 ++ * mapping the head code makes. We keep the UART virtual address ++ * aligned and add in the offset when we load the value here. ++ */ ++ ++ .macro addruart, rx ++ mrc p15, 0, \rx, c1, c0 ++ tst \rx, #1 ++ ldreq \rx, = S3C_PA_UART ++ ldrne \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff) ++#if CONFIG_DEBUG_S3C_UART != 0 ++ add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) ++#endif ++ .endm ++ ++/* include the reset of the code which will do the work, we're only ++ * compiling for a single cpu processor type so the default of s3c2440 ++ * will be fine with us. ++ */ ++ ++#include +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/include/mach/dma.h linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/dma.h +--- linux-2.6.28/arch/arm/mach-s5p6440/include/mach/dma.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/dma.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,21 @@ ++/* linux/arch/arm/mach-s5p6440/include/mach/dma.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5P6440 - DMA support ++ */ ++ ++#ifndef __ASM_ARCH_DMA_H ++#define __ASM_ARCH_DMA_H __FILE__ ++ ++#include ++ ++#define S3C_DMA_CONTROLLERS (1) ++#define S3C_CHANNELS_PER_DMA (8) ++#define S3C_CANDIDATE_CHANNELS_PER_DMA (32) ++#define S3C_DMA_CHANNELS (S3C_DMA_CONTROLLERS*S3C_CHANNELS_PER_DMA) ++ ++#endif /* __ASM_ARCH_IRQ_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/include/mach/entry-macro.S linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/entry-macro.S +--- linux-2.6.28/arch/arm/mach-s5p6440/include/mach/entry-macro.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/entry-macro.S 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,44 @@ ++/* linux/arch/arm/mach-s5p6440/include/mach/entry-macro.S ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * Low-level IRQ helper macros for the Samsung S5P64XX series ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++*/ ++ ++#include ++#include ++#include ++ ++ .macro disable_fiq ++ .endm ++ ++ .macro get_irqnr_preamble, base, tmp ++ ldr \base, =S3C_VA_VIC0 ++ .endm ++ ++ .macro arch_ret_to_user, tmp1, tmp2 ++ .endm ++ ++ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ++ ++ @ check the vic0 ++ mov \irqnr, # S3C_IRQ_OFFSET + 31 ++ ldr \irqstat, [ \base, # VIC_IRQ_STATUS ] ++ teq \irqstat, #0 ++ ++ @ otherwise try vic1 ++ addeq \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0) ++ addeq \irqnr, \irqnr, #32 ++ ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] ++ teqeq \irqstat, #0 ++ ++ clzne \irqstat, \irqstat ++ subne \irqnr, \irqnr, \irqstat ++ .endm +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/include/mach/gpio-core.h linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/gpio-core.h +--- linux-2.6.28/arch/arm/mach-s5p6440/include/mach/gpio-core.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/gpio-core.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,21 @@ ++/* linux/arch/arm/mach-s5p6440/include/mach/gpio-core.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5P64XX - GPIO core support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_GPIO_CORE_H ++#define __ASM_ARCH_GPIO_CORE_H __FILE__ ++ ++/* currently we just include the platform support */ ++#include ++ ++#endif /* __ASM_ARCH_GPIO_CORE_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/include/mach/gpio.h linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/gpio.h +--- linux-2.6.28/arch/arm/mach-s5p6440/include/mach/gpio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/gpio.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,78 @@ ++/* linux/arch/arm/mach-s5p6440/include/mach/gpio.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S3C6400 - GPIO lib support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define gpio_get_value __gpio_get_value ++#define gpio_set_value __gpio_set_value ++#define gpio_cansleep __gpio_cansleep ++#define gpio_to_irq __gpio_to_irq ++ ++/* GPIO bank sizes */ ++#define S5P64XX_GPIO_A_NR (6) ++#define S5P64XX_GPIO_B_NR (7) ++#define S5P64XX_GPIO_C_NR (8) ++#define S5P64XX_GPIO_F_NR (16) ++#define S5P64XX_GPIO_G_NR (7) ++#define S5P64XX_GPIO_H_NR (10) ++#define S5P64XX_GPIO_I_NR (16) ++#define S5P64XX_GPIO_J_NR (12) ++#define S5P64XX_GPIO_N_NR (16) ++#define S5P64XX_GPIO_P_NR (11) ++#define S5P64XX_GPIO_R_NR (15) ++ ++/* GPIO bank numbes */ ++ ++/* CONFIG_S3C_GPIO_SPACE allows the user to select extra ++ * space for debugging purposes so that any accidental ++ * change from one gpio bank to another can be caught. ++*/ ++ ++#define S5P64XX_GPIO_NEXT(__gpio) \ ++ ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) ++ ++enum s3c_gpio_number { ++ S5P64XX_GPIO_A_START = 0, ++ S5P64XX_GPIO_B_START = S5P64XX_GPIO_NEXT(S5P64XX_GPIO_A), ++ S5P64XX_GPIO_C_START = S5P64XX_GPIO_NEXT(S5P64XX_GPIO_B), ++ S5P64XX_GPIO_F_START = S5P64XX_GPIO_NEXT(S5P64XX_GPIO_C), ++ S5P64XX_GPIO_G_START = S5P64XX_GPIO_NEXT(S5P64XX_GPIO_F), ++ S5P64XX_GPIO_H_START = S5P64XX_GPIO_NEXT(S5P64XX_GPIO_G), ++ S5P64XX_GPIO_I_START = S5P64XX_GPIO_NEXT(S5P64XX_GPIO_H), ++ S5P64XX_GPIO_J_START = S5P64XX_GPIO_NEXT(S5P64XX_GPIO_I), ++ S5P64XX_GPIO_N_START = S5P64XX_GPIO_NEXT(S5P64XX_GPIO_J), ++ S5P64XX_GPIO_P_START = S5P64XX_GPIO_NEXT(S5P64XX_GPIO_N), ++ S5P64XX_GPIO_R_START = S5P64XX_GPIO_NEXT(S5P64XX_GPIO_P), ++}; ++ ++/* S5P64XX GPIO number definitions. */ ++ ++#define S5P64XX_GPA(_nr) (S5P64XX_GPIO_A_START + (_nr)) ++#define S5P64XX_GPB(_nr) (S5P64XX_GPIO_B_START + (_nr)) ++#define S5P64XX_GPC(_nr) (S5P64XX_GPIO_C_START + (_nr)) ++#define S5P64XX_GPF(_nr) (S5P64XX_GPIO_F_START + (_nr)) ++#define S5P64XX_GPG(_nr) (S5P64XX_GPIO_G_START + (_nr)) ++#define S5P64XX_GPH(_nr) (S5P64XX_GPIO_H_START + (_nr)) ++#define S5P64XX_GPI(_nr) (S5P64XX_GPIO_I_START + (_nr)) ++#define S5P64XX_GPJ(_nr) (S5P64XX_GPIO_J_START + (_nr)) ++#define S5P64XX_GPN(_nr) (S5P64XX_GPIO_N_START + (_nr)) ++#define S5P64XX_GPP(_nr) (S5P64XX_GPIO_P_START + (_nr)) ++#define S5P64XX_GPR(_nr) (S5P64XX_GPIO_R_START + (_nr)) ++ ++/* the end of the S5P64XX specific gpios */ ++#define S5P64XX_GPIO_END (S5P64XX_GPR(S5P64XX_GPIO_R_NR) + 1) ++#define S3C_GPIO_END S5P64XX_GPIO_END ++ ++/* define the number of gpios we need to the one after the GPR() range */ ++#define ARCH_NR_GPIOS (S5P64XX_GPR(S5P64XX_GPIO_R_NR) + 1) ++ ++#include +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/include/mach/hardware.h linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/hardware.h +--- linux-2.6.28/arch/arm/mach-s5p6440/include/mach/hardware.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/hardware.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,16 @@ ++/* linux/arch/arm/mach-s5p6440/include/mach/hardware.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C6400 - Hardware support ++ */ ++ ++#ifndef __ASM_ARCH_HARDWARE_H ++#define __ASM_ARCH_HARDWARE_H __FILE__ ++ ++/* currently nothing here, placeholder */ ++ ++#endif /* __ASM_ARCH_IRQ_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/include/mach/idle.h linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/idle.h +--- linux-2.6.28/arch/arm/mach-s5p6440/include/mach/idle.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/idle.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,24 @@ ++/* linux/arch/arm/mach-s5p6440/include/mach/idle.h ++ * ++ * Copyright (c) 2004 Simtec Electronics ++ * http://www.simtec.co.uk/products/SWLINUX/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C6400 CPU Idle controls ++*/ ++ ++#ifndef __ASM_ARCH_IDLE_H ++#define __ASM_ARCH_IDLE_H __FILE__ ++ ++/* This allows the over-ride of the default idle code, in case there ++ * is any other things to be done over idle (like DVS) ++*/ ++ ++extern void (*s5p64xx_idle)(void); ++ ++extern void s5p64xx_default_idle(void); ++ ++#endif /* __ASM_ARCH_IDLE_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/include/mach/irqs.h linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/irqs.h +--- linux-2.6.28/arch/arm/mach-s5p6440/include/mach/irqs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/irqs.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,20 @@ ++/* linux/arch/arm/mach-s5p6440/include/mach/irqs.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C6400 - IRQ definitions ++ */ ++ ++#ifndef __ASM_ARCH_IRQS_H ++#define __ASM_ARCH_IRQS_H __FILE__ ++ ++#ifndef __ASM_ARM_IRQ_H ++#error "Do not include this directly, instead #include " ++#endif ++ ++#include ++ ++#endif /* __ASM_ARCH_IRQ_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/include/mach/map.h linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/map.h +--- linux-2.6.28/arch/arm/mach-s5p6440/include/mach/map.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/map.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,151 @@ ++/* linux/arch/arm/mach-s5p6440/include/mach/map.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S5P64XX - Memory map definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_MAP_H ++#define __ASM_ARCH_MAP_H __FILE__ ++ ++#include ++ ++/* HSMMC units */ ++#define S5P64XX_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) ++#define S5P64XX_PA_HSMMC0 S5P64XX_PA_HSMMC(0) ++#define S5P64XX_PA_HSMMC1 S5P64XX_PA_HSMMC(1) ++#define S5P64XX_PA_HSMMC2 S5P64XX_PA_HSMMC(2) ++ ++#define S3C_PA_UART (0xEC005000) ++#define S3C_PA_UART0 (S3C_PA_UART + 0x00) ++#define S3C_PA_UART1 (S3C_PA_UART + 0x400) ++#define S3C_PA_UART2 (S3C_PA_UART + 0x800) ++#define S3C_PA_UART3 (S3C_PA_UART + 0xC00) ++#define S3C_UART_OFFSET (0x400) ++ ++/* See notes on UART VA mapping in debug-macro.S */ ++#define S3C_VA_UARTx(x) (S3C_VA_UART + (S3C_PA_UART & 0xfffff) + ((x) * S3C_UART_OFFSET)) ++ ++#define S3C_VA_UART0 S3C_VA_UARTx(0) ++#define S3C_VA_UART1 S3C_VA_UARTx(1) ++#define S3C_VA_UART2 S3C_VA_UARTx(2) ++#define S3C_VA_UART3 S3C_VA_UARTx(3) ++#define S3C_SZ_UART SZ_256 ++ ++#define S5P64XX_PA_SYSCON (0xE0100000) ++#define S5P64XX_PA_TIMER (0xEA000000) ++#define S5P64XX_PA_IIC0 (0xEC104000) ++#define S5P64XX_PA_IIC1 (0xEC20F000) ++ ++#define S5P64XX_PA_SPI0 (0xEC400000) ++#define S5P64XX_PA_SPI1 (0xEC500000) ++#define S5P64XX_SZ_SPI0 SZ_4K ++#define S5P64XX_SZ_SPI1 SZ_4K ++ ++#define S5P64XX_PA_GPIO (0xE0308000) ++#define S5P64XX_VA_GPIO S3C_ADDR(0x00500000) ++#define S5P64XX_SZ_GPIO SZ_4K ++ ++#define S5P64XX_PA_SDRAM (0x20000000) ++#define S5P64XX_PA_VIC0 (0xE4000000) ++#define S5P64XX_PA_VIC1 (0xE4100000) ++ ++#define S5P64XX_VA_SROMC S3C_VA_SROMC ++#define S5P64XX_PA_SROMC (0xE7000000) ++#define S5P64XX_SZ_SROMC SZ_1M ++ ++#define S5P64XX_VA_LCD S3C_VA_LCD ++#define S5P64XX_PA_LCD (0xEE000000) ++#define S5P64XX_SZ_LCD SZ_1M ++ ++#define S5P64XX_PA_ADC (0xF3000000) ++ ++#define S5P64XX_PA_IIS_V40 (0xF2000000) ++#define S3C_SZ_IIS SZ_8K ++ ++#define S5P64XX_PA_RTC (0xEA100000) ++ ++/* place VICs close together */ ++#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00) ++#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) ++ ++//////////////////////////////////////////////////// ++//These are not changed to support for s5p6440 ++ ++/* DMA controller */ ++#define S5P64XX_PA_DMA (0xE9000000) ++ ++#define S5P64XX_PA_SMC9115 (0x18000000) ++#define S5P64XX_SZ_SMC9115 SZ_512M ++ ++#define S5P64XX_PA_IIS (0xF2000000) ++/* Host I/F Indirect & Direct */ ++#define S5P64XX_VA_HOSTIFA S3C_ADDR(0x00B00000) ++#define S5P64XX_PA_HOSTIFA (0x74000000) ++#define S5P64XX_SZ_HOSTIFA SZ_1M ++ ++#define S5P64XX_VA_HOSTIFB S3C_ADDR(0x00C00000) ++#define S5P64XX_PA_HOSTIFB (0x74100000) ++#define S5P64XX_SZ_HOSTIFB SZ_1M ++ ++/////////////////////////////////////////////////// ++ ++/* Watchdog */ ++#define S5P64XX_PA_WATCHDOG (0xEA200000) ++#define S5P64XX_SZ_WATCHDOG SZ_4K ++ ++/* NAND flash controller */ ++#define S5P64XX_PA_NAND (0xE7100000) ++#define S5P64XX_SZ_NAND SZ_1M ++ ++/* USB OTG */ ++#define S5P64XX_VA_OTG S3C_ADDR(0x03900000) ++#define S5P64XX_PA_OTG (0xED100000) ++#define S5P64XX_SZ_OTG SZ_1M ++ ++/* USB OTG SFR */ ++#define S5P64XX_VA_OTGSFR S3C_ADDR(0x03a00000) ++#define S5P64XX_PA_OTGSFR (0xED200000) ++#define S5P64XX_SZ_OTGSFR SZ_1M ++ ++/* Post Processor */ ++#define S5P64XX_PA_POST (0xEE100000) ++#define S5P64XX_SZ_POST SZ_1M ++ ++/* compatibiltiy defines. */ ++#define S3C_PA_TIMER S5P64XX_PA_TIMER ++#define S3C_PA_HSMMC0 S5P64XX_PA_HSMMC0 ++#define S3C_PA_HSMMC1 S5P64XX_PA_HSMMC1 ++#define S3C_PA_HSMMC2 S5P64XX_PA_HSMMC2 ++#define S3C_SZ_HSMMC SZ_4K ++ ++#define S3C_PA_SPI0 S5P64XX_PA_SPI0 ++#define S3C_PA_SPI1 S5P64XX_PA_SPI1 ++#define S3C_SZ_SPI0 S5P64XX_SZ_SPI0 ++#define S3C_SZ_SPI1 S5P64XX_SZ_SPI1 ++ ++#define S3C_PA_IIC S5P64XX_PA_IIC0 ++#define S3C_PA_IIC1 S5P64XX_PA_IIC1 ++ ++#define S3C_PA_RTC S5P64XX_PA_RTC ++ ++#define S3C_PA_IIS S5P64XX_PA_IIS ++#define S3C_PA_ADC S5P64XX_PA_ADC ++#define S3C_PA_DMA S5P64XX_PA_DMA ++ ++#define S3C_VA_OTG S5P64XX_VA_OTG ++#define S3C_PA_OTG S5P64XX_PA_OTG ++#define S3C_SZ_OTG S5P64XX_SZ_OTG ++ ++#define S3C_VA_OTGSFR S5P64XX_VA_OTGSFR ++#define S3C_PA_OTGSFR S5P64XX_PA_OTGSFR ++#define S3C_SZ_OTGSFR S5P64XX_SZ_OTGSFR ++ ++#endif /* __ASM_ARCH_6440_MAP_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/include/mach/memory.h linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/memory.h +--- linux-2.6.28/arch/arm/mach-s5p6440/include/mach/memory.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/memory.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,23 @@ ++/* linux/arch/arm/mach-s5p6440/include/mach/memory.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_MEMORY_H ++#define __ASM_ARCH_MEMORY_H ++ ++ ++#define PHYS_OFFSET UL(0x20000000) ++#define CONSISTENT_DMA_SIZE SZ_8M ++ ++#define __virt_to_bus(x) __virt_to_phys(x) ++#define __bus_to_virt(x) __phys_to_virt(x) ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/include/mach/regs-irq.h linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/regs-irq.h +--- linux-2.6.28/arch/arm/mach-s5p6440/include/mach/regs-irq.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/regs-irq.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,69 @@ ++/* linux/arch/arm/mach-s5p6440/include/mach/regs-irq.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S5P64XX - IRQ register definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_REGS_IRQ_H ++#define __ASM_ARCH_REGS_IRQ_H __FILE__ ++ ++#include ++#include ++/* interrupt controller */ ++#define S3C_VIC0REG(x) ((x) + S3C_VA_VIC0) ++#define S3C_VIC1REG(x) ((x) + S3C_VA_VIC1) ++ ++#define S5P64XX_VIC0IRQSTATUS S3C_VIC0REG(0x000) ++#define S5P64XX_VIC1IRQSTATUS S3C_VIC1REG(0x000) ++ ++#define S5P64XX_VIC0FIQSTATUS S3C_VIC0REG(0x004) ++#define S5P64XX_VIC1FIQSTATUS S3C_VIC1REG(0x004) ++ ++#define S5P64XX_VIC0RAWINTR S3C_VIC0REG(0x008) ++#define S5P64XX_VIC1RAWINTR S3C_VIC1REG(0x008) ++ ++#define S5P64XX_VIC0INTSELECT S3C_VIC0REG(0x00C) ++#define S5P64XX_VIC1INTSELECT S3C_VIC1REG(0x00C) ++ ++#define S5P64XX_VIC0INTENABLE S3C_VIC0REG(0x010) ++#define S5P64XX_VIC1INTENABLE S3C_VIC1REG(0x010) ++ ++#define S5P64XX_VIC0INTENCLEAR S3C_VIC0REG(0x014) ++#define S5P64XX_VIC1INTENCLEAR S3C_VIC1REG(0x014) ++ ++#define S5P64XX_VIC0SOFTINT S3C_VIC0REG(0x018) ++#define S5P64XX_VIC1SOFTINT S3C_VIC1REG(0x018) ++ ++#define S5P64XX_VIC0SOFTINTCLEAR S3C_VIC0REG(0x01C) ++#define S5P64XX_VIC1SOFTINTCLEAR S3C_VIC1REG(0x01C) ++ ++#define S5P64XX_VIC0PROTECTION S3C_VIC0REG(0x020) ++#define S5P64XX_VIC1PROTECTION S3C_VIC1REG(0x020) ++ ++#define S5P64XX_VIC0SWPRIORITYMASK S3C_VIC0REG(0x024) ++#define S5P64XX_VIC1SWPRIORITYMASK S3C_VIC1REG(0x024) ++ ++#define S5P64XX_VIC0PRIORITYDAISY S3C_VIC0REG(0x028) ++#define S5P64XX_VIC1PRIORITYDAISY S3C_VIC1REG(0x028) ++ ++#define S5P64XX_VIC0VECTADDR0 S3C_VIC0REG(0x100) ++#define S5P64XX_VIC1VECTADDR0 S3C_VIC1REG(0x100) ++ ++#define S5P64XX_VIC0VECTADDR1 S3C_VIC0REG(0x104) ++#define S5P64XX_VIC1VECTADDR1 S3C_VIC1REG(0x104) ++ ++#define S5P64XX_VIC0VECTADDR2 S3C_VIC0REG(0x108) ++#define S5P64XX_VIC1VECTADDR2 S3C_VIC1REG(0x108) ++ ++#define S5P64XX_VIC0ADDRESS S3C_VIC0REG(0xF00) ++#define S5P64XX_VIC1ADDRESS S3C_VIC1REG(0xF00) ++ ++#endif /* __ASM_ARCH_6400_REGS_IRQ_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/include/mach/regs-mem.h linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/regs-mem.h +--- linux-2.6.28/arch/arm/mach-s5p6440/include/mach/regs-mem.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/regs-mem.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,70 @@ ++/* linux/arch/arm/mach-s5p6440/include/mach/regs-mem.h ++ * ++ * Copyright (c) 2004 Simtec Electronics ++ * http://www.simtec.co.uk/products/SWLINUX/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C2410 Memory Control register definitions ++*/ ++ ++#ifndef __ASM_ARM_MEMREGS_H ++#define __ASM_ARM_MEMREGS_H ++ ++#ifndef S5P64XX_MEMREG ++#define S5P64XX_MEMREG(x) (S5P64XX_VA_SROMC + (x)) ++#endif ++ ++ ++/* Bank Idle Cycle Control Registers 0-5 */ ++#define S5P64XX_SROM_BW S5P64XX_MEMREG(0x00) ++ ++#define S5P64XX_SROM_BC0 S5P64XX_MEMREG(0x04) ++#define S5P64XX_SROM_BC1 S5P64XX_MEMREG(0x08) ++#define S5P64XX_SROM_BC2 S5P64XX_MEMREG(0x0C) ++#define S5P64XX_SROM_BC3 S5P64XX_MEMREG(0x10) ++#define S5P64XX_SROM_BC4 S5P64XX_MEMREG(0x14) ++#define S5P64XX_SROM_BC5 S5P64XX_MEMREG(0x18) ++ ++/* SROM BW */ ++#define S5P64XX_SROM_BW_DATA_WIDTH0_8BIT (0 << 0) ++#define S5P64XX_SROM_BW_DATA_WIDTH0_16BIT (1 << 0) ++#define S5P64XX_SROM_BW_DATA_WIDTH0_MASK (1 << 0) ++ ++#define S5P64XX_SROM_BW_WAIT_ENABLE0_DISABLE (0 << 2) ++#define S5P64XX_SROM_BW_WAIT_ENABLE0_ENABLE (1 << 2) ++#define S5P64XX_SROM_BW_WAIT_ENABLE0_MASK (1 << 2) ++ ++#define S5P64XX_SROM_BW_BYTE_ENABLE0_DISABLE (0 << 3) ++#define S5P64XX_SROM_BW_BYTE_ENABLE0_ENABLE (1 << 3) ++#define S5P64XX_SROM_BW_BYTE_ENABLE0_MASK (1 << 3) ++ ++#define S5P64XX_SROM_BW_DATA_WIDTH1_8BIT (0 << 4) ++#define S5P64XX_SROM_BW_DATA_WIDTH1_16BIT (1 << 4) ++#define S5P64XX_SROM_BW_DATA_WIDTH1_MASK (1 << 4) ++ ++#define S5P64XX_SROM_BW_WAIT_ENABLE1_DISABLE (0 << 6) ++#define S5P64XX_SROM_BW_WAIT_ENABLE1_ENABLE (1 << 6) ++#define S5P64XX_SROM_BW_WAIT_ENABLE1_MASK (1 << 6) ++ ++#define S5P64XX_SROM_BW_BYTE_ENABLE1_DISABLE (0 << 7) ++#define S5P64XX_SROM_BW_BYTE_ENABLE1_ENABLE (1 << 7) ++#define S5P64XX_SROM_BW_BYTE_ENABLE1_MASK (1 << 7) ++ ++#define S5P64XX_SROM_BW_DATA_WIDTH2_8BIT (0 << 8) ++#define S5P64XX_SROM_BW_DATA_WIDTH2_16BIT (1 << 8) ++#define S5P64XX_SROM_BW_DATA_WIDTH2_MASK (1 << 8) ++ ++/* SROM BCn */ ++#define S5P64XX_SROM_BCn_TACS(x) (x << 28) ++#define S5P64XX_SROM_BCn_TCOS(x) (x << 24) ++#define S5P64XX_SROM_BCn_TACC(x) (x << 16) ++#define S5P64XX_SROM_BCn_TCOH(x) (x << 12) ++#define S5P64XX_SROM_BCn_TCAH(x) (x << 8) ++#define S5P64XX_SROM_BCn_TACP(x) (x << 4) ++#define S5P64XX_SROM_BCn_PMC_NORMAL (0 << 0) ++#define S5P64XX_SROM_BCn_PMC_4 (1 << 0) ++ ++#endif /* __ASM_ARM_MEMREGS_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/include/mach/system.h linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/system.h +--- linux-2.6.28/arch/arm/mach-s5p6440/include/mach/system.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/system.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,47 @@ ++/* linux/arch/arm/mach-s5p6440/include/mach/system.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C6400 - system implementation ++ */ ++ ++#ifndef __ASM_ARCH_SYSTEM_H ++#define __ASM_ARCH_SYSTEM_H __FILE__ ++ ++#include ++#include ++#include ++ ++void (*s5p64xx_idle)(void); ++void (*s5p64xx_reset_hook)(void); ++ ++void s5p64xx_default_idle(void) ++{ ++ /* nothing here yet */ ++} ++ ++static void arch_idle(void) ++{ ++ if (s5p64xx_idle != NULL) ++ (s5p64xx_idle)(); ++ else ++ s5p64xx_default_idle(); ++} ++ ++static void arch_reset(char mode) ++{ ++ void __iomem *wdt_reg; ++ ++ wdt_reg = ioremap(S5P64XX_PA_WATCHDOG,S5P64XX_SZ_WATCHDOG); ++ ++ /* nothing here yet */ ++ ++ writel(S3C2410_WTCNT_CNT, wdt_reg + S3C2410_WTCNT_OFFSET); /* Watchdog Count Register*/ ++ writel(S3C2410_WTCNT_CON, wdt_reg + S3C2410_WTCON_OFFSET); /* Watchdog Controller Register*/ ++ writel(S3C2410_WTCNT_DAT, wdt_reg + S3C2410_WTDAT_OFFSET); /* Watchdog Data Register*/ ++} ++ ++#endif /* __ASM_ARCH_IRQ_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/include/mach/tick.h linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/tick.h +--- linux-2.6.28/arch/arm/mach-s5p6440/include/mach/tick.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/tick.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,29 @@ ++/* linux/arch/arm/mach-s5p6440/include/mach/tick.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S5P64XX - Timer tick support definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_TICK_H ++#define __ASM_ARCH_TICK_H __FILE__ ++ ++/* note, the timer interrutps turn up in 2 places, the vic and then ++ * the timer block. We take the VIC as the base at the moment. ++ */ ++static inline u32 s3c24xx_ostimer_pending(void) ++{ ++ u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS); ++ return pend & 1 << (IRQ_TIMER4_VIC - S5P64XX_IRQ_VIC0(0)); ++} ++ ++#define TICK_MAX (0xffffffff) ++ ++#endif /* __ASM_ARCH_6400_TICK_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/include/mach/uncompress.h linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/uncompress.h +--- linux-2.6.28/arch/arm/mach-s5p6440/include/mach/uncompress.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/include/mach/uncompress.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,26 @@ ++/* linux/arch/arm/mach-s5p6440/include/mach/uncompress.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S3C6400 - uncompress code ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_UNCOMPRESS_H ++#define __ASM_ARCH_UNCOMPRESS_H ++ ++#include ++#include ++ ++static void arch_detect_cpu(void) ++{ ++ /* we do not need to do any cpu detection here at the moment. */ ++} ++ ++#endif /* __ASM_ARCH_UNCOMPRESS_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/mach-smdk6440.c linux-2.6.28.6/arch/arm/mach-s5p6440/mach-smdk6440.c +--- linux-2.6.28/arch/arm/mach-s5p6440/mach-smdk6440.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/mach-smdk6440.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,432 @@ ++/* linux/arch/arm/mach-s5p6440/mach-smdk6440.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++ ++#ifdef CONFIG_USB_SUPPORT ++#include ++#include ++ ++/* S3C_USB_CLKSRC 0: EPLL 1: CLK_48M */ ++#define S3C_USB_CLKSRC 1 ++#define OTGH_PHY_CLK_VALUE (0x02) /* UTMI Interface, Cristal, 12Mhz clk for PLL */ ++#endif ++ ++#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK ++#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB ++#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE ++ ++//static struct samspi_device spidev_b0_cs0; ++#if 0 ++static struct samspi_device ProtocolADriver_b1_cs0; ++static struct samspi_device spidev_b0_cs1; ++static struct samspi_device ProtocolBDriver_b1_cs1; ++static struct samspi_device spidev_b1_cs2; ++#endif ++ ++static struct spi_board_info __initdata sam_spi_devs[] = { ++ [0] = { ++ .modalias = "spidev", /* Test Interface */ ++ .mode = SPI_MODE_2, /* CPOL=1, CPHA=0 */ ++ .max_speed_hz = 2468013, ++ /* Connected to SPI-0 as 1st Slave */ ++ .bus_num = 0, ++ .irq = IRQ_SPI0, ++ .chip_select = 0, ++// .controller_data = (void *)&spidev_b0_cs0, ++#if 0 ++ }, { ++ .modalias = "ProtocolADriver", ++ .mode = SPI_MODE_2, ++ .max_speed_hz = 1357923, ++ /* Connected to SPI-1 as 1st Slave */ ++ .bus_num = 1, ++ .irq = IRQ_SPI1, ++ .chip_select = 0, ++ .controller_data = (void *)&ProtocolADriver_b1_cs0, ++ }, { ++ .modalias = "spidev", ++ .mode = SPI_MODE_2, ++ .max_speed_hz = 2357923, ++ /* Connected to SPI-0 as 2nd Slave */ ++ .bus_num = 0, ++ .irq = IRQ_SPI0, ++ .chip_select = 1, ++ .controller_data = (void *)&spidev_b0_cs1, ++ }, { ++ .modalias = "ProtocolBDriver", ++ .mode = SPI_MODE_2, ++ .max_speed_hz = 3357923, ++ /* Connected to SPI-1 as 2ndst Slave */ ++ .bus_num = 1, ++ .irq = IRQ_SPI1, ++ .chip_select = 1, ++ .controller_data = (void *)&ProtocolBDriver_b1_cs1, ++ }, { ++ .modalias = "spidev", ++ .mode = SPI_MODE_2, ++ .max_speed_hz = 4357923, ++ /* Connected to SPI-1 as 3rd Slave */ ++ .bus_num = 1, ++ .irq = IRQ_SPI1, ++ .chip_select = 2, ++ .controller_data = (void *)&spidev_b1_cs2, ++#endif ++ }, ++}; ++ ++static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = { ++ [0] = { ++ .hwport = 0, ++ .flags = 0, ++ .ucon = S3C64XX_UCON_DEFAULT, ++ .ulcon = S3C64XX_ULCON_DEFAULT, ++ .ufcon = S3C64XX_UFCON_DEFAULT, ++ }, ++ [1] = { ++ .hwport = 1, ++ .flags = 0, ++ .ucon = S3C64XX_UCON_DEFAULT, ++ .ulcon = S3C64XX_ULCON_DEFAULT, ++ .ufcon = S3C64XX_UFCON_DEFAULT, ++ }, ++ [2] = { ++ .hwport = 2, ++ .flags = 0, ++ .ucon = S3C64XX_UCON_DEFAULT, ++ .ulcon = S3C64XX_ULCON_DEFAULT, ++ .ufcon = S3C64XX_UFCON_DEFAULT, ++ }, ++ [3] = { ++ .hwport = 3, ++ .flags = 0, ++ .ucon = S3C64XX_UCON_DEFAULT, ++ .ulcon = S3C64XX_ULCON_DEFAULT, ++ .ufcon = S3C64XX_UFCON_DEFAULT, ++ }, ++}; ++ ++struct map_desc smdk6440_iodesc[] = {}; ++ ++static struct platform_device *smdk6440_devices[] __initdata = { ++#ifdef CONFIG_SMDK6440_SD_CH0 ++ &s3c_device_hsmmc0, ++#endif ++#ifdef CONFIG_SMDK6440_SD_CH1 ++ &s3c_device_hsmmc1, ++#endif ++#ifdef CONFIG_SMDK6440_SD_CH2 ++ &s3c_device_hsmmc2, ++#endif ++ &s3c_device_wdt, ++ &s3c_device_rtc, ++ &s3c_device_i2c0, ++ &s3c_device_i2c1, ++ &s3c_device_spi0, ++ &s3c_device_spi1, ++ &s3c_device_ts, ++ &s3c_device_smc911x, ++ &s3c_device_lcd, ++ &s3c_device_nand, ++ &s3c_device_usbgadget, ++ &s3c_device_usb_otghcd, ++ ++#ifdef CONFIG_S5P64XX_ADC ++ &s3c_device_adc, ++#endif ++ ++#ifdef CONFIG_HAVE_PWM ++ &s3c_device_timer[0], ++ &s3c_device_timer[1], ++#endif ++}; ++ ++static struct i2c_board_info i2c_devs0[] __initdata = { ++ { I2C_BOARD_INFO("24c08", 0x50), }, ++ //{ I2C_BOARD_INFO("WM8580", 0x10), }, ++}; ++ ++static struct i2c_board_info i2c_devs1[] __initdata = { ++ { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */ ++ { I2C_BOARD_INFO("WM8580", 0x1a), }, ++ //{ I2C_BOARD_INFO("WM8580", 0x1b), }, ++}; ++ ++ ++static struct s3c_ts_mach_info s3c_ts_platform __initdata = { ++ .delay = 10000, ++ .presc = 49, ++ .oversampling_shift = 2, ++ .resol_bit = 12, ++ .s3c_adc_con = ADC_TYPE_2, ++}; ++ ++static struct s3c_adc_mach_info s3c_adc_platform = { ++ /* s3c6410 support 12-bit resolution */ ++ .delay = 10000, ++ .presc = 49, ++ .resolution = 12, ++}; ++ ++#if defined(CONFIG_HAVE_PWM) ++static struct platform_pwm_backlight_data smdk_backlight_data = { ++ .pwm_id = 1, ++ .max_brightness = 255, ++ .dft_brightness = 255, ++ .pwm_period_ns = 78770, ++}; ++ ++static struct platform_device smdk_backlight_device = { ++ .name = "pwm-backlight", ++ .dev = { ++ .parent = &s3c_device_timer[1].dev, ++ .platform_data = &smdk_backlight_data, ++ }, ++}; ++ ++static void __init smdk_backlight_register(void) ++{ ++ int ret = platform_device_register(&smdk_backlight_device); ++ if (ret) ++ printk(KERN_ERR "smdk: failed to register backlight device: %d\n", ret); ++} ++#else ++#define smdk_backlight_register() do { } while (0) ++#endif ++ ++void smdk6440_setup_sdhci0 (void); ++ ++static void __init smdk6440_map_io(void) ++{ ++ s3c_device_nand.name = "s5p6440-nand"; ++ ++ s5p64xx_init_io(smdk6440_iodesc, ARRAY_SIZE(smdk6440_iodesc)); ++ s3c24xx_init_clocks(12000000); ++ s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs)); ++ ++ smdk6440_setup_sdhci0(); ++} ++ ++static void __init smdk6440_smc911x_set(void) ++{ ++ unsigned int tmp; ++ ++ tmp = __raw_readl(S5P64XX_SROM_BW); ++ tmp &= ~(S5P64XX_SROM_BW_WAIT_ENABLE1_MASK | S5P64XX_SROM_BW_WAIT_ENABLE1_MASK | ++ S5P64XX_SROM_BW_DATA_WIDTH1_MASK); ++ tmp |= S5P64XX_SROM_BW_BYTE_ENABLE1_ENABLE | S5P64XX_SROM_BW_WAIT_ENABLE1_ENABLE | ++ S5P64XX_SROM_BW_DATA_WIDTH1_16BIT; ++ ++ __raw_writel(tmp, S5P64XX_SROM_BW); ++ ++ __raw_writel(S5P64XX_SROM_BCn_TACS(0) | S5P64XX_SROM_BCn_TCOS(4) | ++ S5P64XX_SROM_BCn_TACC(13) | S5P64XX_SROM_BCn_TCOH(1) | ++ S5P64XX_SROM_BCn_TCAH(4) | S5P64XX_SROM_BCn_TACP(6) | ++ S5P64XX_SROM_BCn_PMC_NORMAL, S5P64XX_SROM_BC1); ++} ++ ++static void __init smdk6440_machine_init(void) ++{ ++ s3c_device_nand.dev.platform_data = &s3c_nand_mtd_part_info; ++ ++ smdk6440_smc911x_set(); ++ ++ s3c_i2c0_set_platdata(NULL); ++ s3c_i2c1_set_platdata(NULL); ++ ++ s3c_ts_set_platdata(&s3c_ts_platform); ++ s3c_adc_set_platdata(&s3c_adc_platform); ++ ++ i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0)); ++ i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); ++ ++ spi_register_board_info(sam_spi_devs, ARRAY_SIZE(sam_spi_devs)); ++ ++ platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices)); ++ ++ s5p6440_pm_init(); ++ ++ smdk_backlight_register(); ++ ++} ++ ++MACHINE_START(SMDK6440, "SMDK6440") ++ /* Maintainer: Ben Dooks */ ++ .phys_io = S3C_PA_UART & 0xfff00000, ++ .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, ++ .boot_params = S5P64XX_PA_SDRAM + 0x100, ++ ++ .init_irq = s5p6440_init_irq, ++ .map_io = smdk6440_map_io, ++ .init_machine = smdk6440_machine_init, ++ .timer = &s3c64xx_timer, ++MACHINE_END ++ ++#ifdef CONFIG_USB_SUPPORT ++/* Initializes OTG Phy. */ ++void otg_phy_init(void) { ++ ++ int err; ++ ++ if (gpio_is_valid(S5P64XX_GPN(1))) { ++ err = gpio_request(S5P64XX_GPN(1), "GPN"); ++ ++ if(err) ++ printk(KERN_ERR "failed to request GPN1\n"); ++ ++ gpio_direction_output(S5P64XX_GPN(1), 1); ++ } ++ ++ writel(readl(S3C_OTHERS)&~S3C_OTHERS_USB_SIG_MASK, S3C_OTHERS); ++ writel(0x0, S3C_USBOTG_PHYPWR); /* Power up */ ++ writel(OTGH_PHY_CLK_VALUE, S3C_USBOTG_PHYCLK); ++ writel(0x1, S3C_USBOTG_RSTCON); ++ ++ udelay(50); ++ writel(0x0, S3C_USBOTG_RSTCON); ++ udelay(50); ++} ++EXPORT_SYMBOL(otg_phy_init); ++ ++/* USB Control request data struct must be located here for DMA transfer */ ++struct usb_ctrlrequest usb_ctrl __attribute__((aligned(8))); ++EXPORT_SYMBOL(usb_ctrl); ++ ++/* OTG PHY Power Off */ ++void otg_phy_off(void) { ++ writel(readl(S3C_USBOTG_PHYPWR)|(0x1F<<1), S3C_USBOTG_PHYPWR); ++ writel(readl(S3C_OTHERS)&~S3C_OTHERS_USB_SIG_MASK, S3C_OTHERS); ++ ++ gpio_free(S5P64XX_GPN(1)); ++} ++EXPORT_SYMBOL(otg_phy_off); ++ ++#endif ++ ++#if defined(CONFIG_RTC_DRV_S3C) ++/* RTC common Function for samsung APs*/ ++unsigned int s3c_rtc_set_bit_byte(void __iomem *base, uint offset, uint val) ++{ ++ writeb(val, base + offset); ++ ++ return 0; ++} ++ ++unsigned int s3c_rtc_read_alarm_status(void __iomem *base) ++{ ++ return 1; ++} ++ ++void s3c_rtc_set_pie(void __iomem *base, uint to) ++{ ++ unsigned int tmp; ++ ++ tmp = readw(base + S3C2410_RTCCON) & ~S3C_RTCCON_TICEN; ++ ++ if (to) ++ tmp |= S3C_RTCCON_TICEN; ++ ++ writew(tmp, base + S3C2410_RTCCON); ++} ++ ++void s3c_rtc_set_freq_regs(void __iomem *base, uint freq, uint s3c_freq) ++{ ++ unsigned int tmp; ++ ++ tmp = readw(base + S3C2410_RTCCON) & (S3C_RTCCON_TICEN | S3C2410_RTCCON_RTCEN ); ++ writew(tmp, base + S3C2410_RTCCON); ++ s3c_freq = freq; ++ tmp = (32768 / freq)-1; ++ writel(tmp, base + S3C2410_TICNT); ++} ++ ++void s3c_rtc_enable_set(struct platform_device *pdev,void __iomem *base, int en) ++{ ++ unsigned int tmp; ++ ++ if (!en) { ++ tmp = readw(base + S3C2410_RTCCON); ++ writew(tmp & ~ (S3C2410_RTCCON_RTCEN | S3C_RTCCON_TICEN), base + S3C2410_RTCCON); ++ } else { ++ /* re-enable the device, and check it is ok */ ++ if ((readw(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0){ ++ dev_info(&pdev->dev, "rtc disabled, re-enabling\n"); ++ ++ tmp = readw(base + S3C2410_RTCCON); ++ writew(tmp|S3C2410_RTCCON_RTCEN, base+S3C2410_RTCCON); ++ } ++ ++ if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)){ ++ dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n"); ++ ++ tmp = readw(base + S3C2410_RTCCON); ++ writew(tmp& ~S3C2410_RTCCON_CNTSEL, base+S3C2410_RTCCON); ++ } ++ ++ if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)){ ++ dev_info(&pdev->dev, "removing RTCCON_CLKRST\n"); ++ ++ tmp = readw(base + S3C2410_RTCCON); ++ writew(tmp & ~S3C2410_RTCCON_CLKRST, base+S3C2410_RTCCON); ++ } ++ } ++} ++#endif ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/pm.c linux-2.6.28.6/arch/arm/mach-s5p6440/pm.c +--- linux-2.6.28/arch/arm/mach-s5p6440/pm.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/pm.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,103 @@ ++/* linux/arch/arm/mach-s5p6440/pm.c ++ * ++ * Copyright (c) 2006 Samsung Electronics ++ * ++ * ++ * S3C6410 (and compatible) Power Manager (Suspend-To-RAM) support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++ ++#include ++#include ++//#include ++#include ++#include ++ ++#ifdef CONFIG_S3C2410_PM_DEBUG ++extern void pm_dbg(const char *fmt, ...); ++#define DBG(fmt...) pm_dbg(fmt) ++#else ++#define DBG(fmt...) printk(KERN_DEBUG fmt) ++#endif ++ ++//static void s5p6440_cpu_suspend(void) ++void s5p6440_cpu_suspend(void) ++{ ++ unsigned long tmp; ++ ++ /* issue the standby signal into the pm unit. Note, we ++ * issue a write-buffer drain just in case */ ++ ++ tmp = 0; ++ ++ asm("b 1f\n\t" ++ ".align 5\n\t" ++ "1:\n\t" ++ "mcr p15, 0, %0, c7, c10, 5\n\t" ++ "mcr p15, 0, %0, c7, c10, 4\n\t" ++ "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp)); ++ ++ /* we should never get past here */ ++ ++ panic("sleep resumed to originator?"); ++} ++ ++static void s5p6440_pm_prepare(void) ++{ ++ ++} ++ ++static int s5p6440_pm_add(struct sys_device *sysdev) ++{ ++ pm_cpu_prep = s5p6440_pm_prepare; ++ pm_cpu_sleep = s5p6440_cpu_suspend; ++ ++ return 0; ++} ++ ++static struct sleep_save s5p6440_sleep[] = { ++ ++}; ++ ++static int s5p6440_pm_resume(struct sys_device *dev) ++{ ++ s5p6440_pm_do_restore(s5p6440_sleep, ARRAY_SIZE(s5p6440_sleep)); ++ return 0; ++} ++ ++static struct sysdev_driver s5p6440_pm_driver = { ++ .add = s5p6440_pm_add, ++ .resume = s5p6440_pm_resume, ++}; ++ ++static __init int s5p6440_pm_drvinit(void) ++{ ++ return sysdev_driver_register(&s5p6440_sysclass, &s5p6440_pm_driver); ++} ++ ++arch_initcall(s5p6440_pm_drvinit); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5p6440/setup-sdhci.c linux-2.6.28.6/arch/arm/mach-s5p6440/setup-sdhci.c +--- linux-2.6.28/arch/arm/mach-s5p6440/setup-sdhci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5p6440/setup-sdhci.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,160 @@ ++/* linux/arch/arm/mach-s3c6410/setup-sdhci.c ++ * ++ * Copyright 2008 Simtec Electronics ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC) ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ ++ ++char *s3c6410_hsmmc_clksrcs[4] = { ++ [0] = "hsmmc", ++ [1] = "hsmmc", ++ [2] = "mmc_bus", ++ /* [3] = "48m", - note not succesfully used yet */ ++}; ++ ++void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) ++{ ++ unsigned int gpio; ++ unsigned int end; ++ ++ /* GPIO should be set on 4bit though 1-bit setting is comming. */ ++ if (width == 1) ++ width = 4; ++ end = S5P64XX_GPG(2 + width); ++ ++ /* Set all the necessary GPG pins to special-function 0 */ ++ for (gpio = S5P64XX_GPG(0); gpio < end; gpio++) { ++ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); ++ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); ++ } ++ ++#if 0 ++ s3c_gpio_setpull(S5P64XX_GPG(6), S3C_GPIO_PULL_UP); ++ s3c_gpio_cfgpin(S5P64XX_GPG(6), S3C_GPIO_SFN(2)); ++#endif ++} ++ ++void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev, ++ void __iomem *r, ++ struct mmc_ios *ios, ++ struct mmc_card *card) ++{ ++ u32 ctrl2, ctrl3 = 0; ++ ++ /* don't need to alter anything acording to card-type */ ++ ++ writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4); ++ ++ ctrl2 = readl(r + S3C_SDHCI_CONTROL2); ++ ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; ++ ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | ++ S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | ++ S3C_SDHCI_CTRL2_ENFBCLKRX | ++ S3C_SDHCI_CTRL2_DFCNT_NONE | ++ S3C_SDHCI_CTRL2_ENCLKOUTHOLD); ++ ++ writel(ctrl2, r + S3C_SDHCI_CONTROL2); ++ writel(ctrl3, r + S3C_SDHCI_CONTROL3); ++} ++ ++void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) ++{ ++ unsigned int gpio; ++ unsigned int end; ++ ++ /* GPIO should be set on 4bit though 1-bit setting is comming. */ ++ if (width == 1) ++ width = 4; ++ end = S5P64XX_GPH(2 + width); ++ ++ /* Set all the necessary GPG pins to special-function 0 */ ++ for (gpio = S5P64XX_GPH(0); gpio < end; gpio++) { ++ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); ++ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); ++ } ++ ++ s3c_gpio_setpull(S5P64XX_GPG(6), S3C_GPIO_PULL_UP); ++ s3c_gpio_cfgpin(S5P64XX_GPG(6), S3C_GPIO_SFN(3)); ++} ++ ++void s3c6410_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) ++{ ++ /* XXX: should be done later. */ ++#if 0 ++ unsigned int gpio; ++ unsigned int end; ++ ++ /* GPIO should be set on 4bit though 1-bit setting is comming. */ ++ if (width == 1) ++ width = 4; ++ end = S5P64XX_GPH(2 + width); ++ ++ /* Set all the necessary GPG pins to special-function 0 */ ++ for (gpio = S5P64XX_GPH(0); gpio < end; gpio++) { ++ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); ++ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); ++ } ++ ++ s3c_gpio_setpull(S5P64XX_GPG(6), S3C_GPIO_PULL_UP); ++ s3c_gpio_cfgpin(S5P64XX_GPG(6), S3C_GPIO_SFN(3)); ++#endif ++} ++ ++static void setup_sdhci0_irq_cd (void) ++{ ++ /* init GPIO as a ext irq */ ++ s3c_gpio_cfgpin(S5P64XX_GPN(13), S3C_GPIO_SFN(2)); ++ s3c_gpio_setpull(S5P64XX_GPN(13), S3C_GPIO_PULL_NONE); ++ ++ set_irq_type(S3C_EINT(13), IRQ_TYPE_EDGE_BOTH); ++} ++ ++static uint detect_sdhci0_irq_cd (void) ++{ ++ uint detect; ++ ++ detect = readl(S5P64XX_GPNDAT); ++ detect &= 0x2000; /* GPN13 */ ++ ++ return (!detect); ++} ++ ++static struct s3c_sdhci_platdata s3c_hsmmc0_platdata = { ++ .max_width = 4, ++ .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | ++ MMC_CAP_SD_HIGHSPEED | MMC_CAP_BOOT_ONTHEFLY), ++ .cfg_ext_cd = setup_sdhci0_irq_cd, ++ .detect_ext_cd = detect_sdhci0_irq_cd, ++ .ext_cd = S3C_EINT(13), ++}; ++ ++void smdk6440_setup_sdhci0 (void) ++{ ++ s3c_sdhci0_set_platdata(&s3c_hsmmc0_platdata); ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/Kconfig linux-2.6.28.6/arch/arm/mach-s5pc100/Kconfig +--- linux-2.6.28/arch/arm/mach-s5pc100/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/Kconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,33 @@ ++# arch/arm/mach-s5pc100/Kconfig ++# ++# Copyright 2008 Openmoko, Inc. ++# Copyright 2008 Simtec Electronics ++# ++# Licensed under GPLv2 ++ ++# Configuration options for the S5PC100 CPU ++ ++config CPU_S5PC100 ++ bool ++ select CPU_S5PC100_INIT ++ select CPU_S5PC100_CLOCK ++ help ++ Enable S5PC100 CPU support ++ ++config S5PC1XX_SETUP_SDHCI ++ bool ++ help ++ Internal helper functions for S5PC1XX based SDHCI systems ++ ++config MACH_SMDKC100 ++ bool "SMDKC100" ++ select CPU_S5PC100 ++ select S3C_DMA_PL330 ++ select S3C_DEV_I2C1 ++ select S3C_DEV_HSMMC ++ select S3C_DEV_HSMMC1 ++ select S5PC1XX_SETUP_SDHCI ++ select S3C64XX_SETUP_I2C1 ++ help ++ Machine support for the Samsung SMDKC100 ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/Makefile linux-2.6.28.6/arch/arm/mach-s5pc100/Makefile +--- linux-2.6.28/arch/arm/mach-s5pc100/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/Makefile 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,29 @@ ++# arch/arm/mach-s5pc100/Makefile ++# ++# Copyright 2008 Openmoko, Inc. ++# Copyright 2008 Simtec Electronics ++# ++# Licensed under GPLv2 ++ ++obj-y := ++led-y := leds.o ++obj-m := ++obj-n := ++obj- := ++ ++# Core support for S5PC100 system ++ ++obj-$(CONFIG_CPU_S5PC100) += cpu.o ++obj-$(CONFIG_CPU_S5PC100) += dma.o ++ ++# Helper and device support ++obj-$(CONFIG_PM) += pm.o ++obj-$(CONFIG_S5PC1XX_SETUP_SDHCI) += setup-sdhci.o ++ ++# machine support ++ ++obj-$(CONFIG_MACH_SMDKC100) += mach-smdkc100.o ++ ++# LEDs support ++led-$(CONFIG_MACH_SMDKC100) += leds-s5pc100.o ++obj-$(CONFIG_LEDS) += $(led-y) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/Makefile.boot linux-2.6.28.6/arch/arm/mach-s5pc100/Makefile.boot +--- linux-2.6.28/arch/arm/mach-s5pc100/Makefile.boot 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/Makefile.boot 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,2 @@ ++ zreladdr-y := 0x20008000 ++params_phys-y := 0x20000100 +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/cpu.c linux-2.6.28.6/arch/arm/mach-s5pc100/cpu.c +--- linux-2.6.28/arch/arm/mach-s5pc100/cpu.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/cpu.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,166 @@ ++/* linux/arch/arm/mach-s5pc100/cpu.c ++ * ++ * Copyright 2008 Samsung Electronics ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#undef T32_PROBE_DEBUGGING ++ ++#if defined(T32_PROBE_DEBUGGING) ++#include ++#include ++#include ++#endif ++ ++/* Initial IO mappings */ ++ ++static struct map_desc s5pc100_iodesc[] __initdata = { ++ IODESC_ENT(LCD), ++ IODESC_ENT(SROMC), ++ IODESC_ENT(SYSTIMER), ++ IODESC_ENT(OTG), ++ IODESC_ENT(OTGSFR), ++ IODESC_ENT(SYSCON), ++ IODESC_ENT(GPIO), ++ IODESC_ENT(NAND), ++ //IODESC_ENT(HOSTIFB), ++}; ++ ++/* s5pc100_map_io ++ * ++ * register the standard cpu IO areas ++*/ ++ ++static void s5pc100_idle(void) ++{ ++#if !defined(CONFIG_MMC_SDHCI_S3C) && !defined(CONFIG_MMC_SDHCI_MODULE) ++ unsigned int tmp; ++ ++#if defined(T32_PROBE_DEBUGGING) ++/* debugging with T32 GPIO port GPD1 which is connected with 2 pin of J1 connector */ ++ gpio_direction_output(S5PC1XX_GPD(1), 0); ++#endif ++/* ++ * 1. Set CFG_STANDBYWFI field of PWR_CFG to 2¡¯b01. ++ * 2. Set PMU_INT_DISABLE bit of OTHERS register to 1¡¯b1 to prevent interrupts from ++ * occurring while entering IDLE mode. ++ * 3. Execute Wait For Interrupt instruction (WFI). ++*/ ++ tmp = __raw_readl(S5P_PWR_CFG); ++ tmp &= S5P_CFG_WFI_CLEAN; ++ tmp |= S5P_CFG_WFI_IDLE; ++ __raw_writel(tmp, S5P_PWR_CFG); ++ ++ cpu_do_idle(); ++ ++#if defined(T32_PROBE_DEBUGGING) ++ gpio_direction_output(S5PC1XX_GPD(1), 1); ++#endif ++#endif ++} ++ ++void __init s5pc100_map_io(void) ++{ ++ iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc)); ++ ++ /* HS-MMC Platform data */ ++ ++ s3c6410_default_sdhci0(); ++ s3c6410_default_sdhci1(); ++ ++ /* set s5pc100 idle function */ ++ ++ s5pc1xx_idle = s5pc100_idle; ++ ++ ++#if 0 ++ /* the i2c devices are directly compatible with s3c2440 */ ++ s3c_i2c0_setname("s3c2440-i2c"); ++ s3c_i2c1_setname("s3c2440-i2c"); ++#endif ++} ++ ++void __init s5pc100_init_clocks(int xtal) ++{ ++ printk(KERN_DEBUG "%s: initialising clocks\n", __func__); ++ s3c24xx_register_baseclocks(xtal); ++ s5pc1xx_register_clocks(); ++ s5pc100_register_clocks(); ++ s5pc100_setup_clocks(); ++#if defined(CONFIG_TIMER_PWM) ++ s3c24xx_pwmclk_init(); ++#endif ++} ++ ++void __init s5pc100_init_irq(void) ++{ ++ /* VIC0, VIC1, and VIC2 are fully populated. */ ++ s5pc1xx_init_irq(~0, ~0, ~0); ++} ++ ++struct sysdev_class s5pc100_sysclass = { ++ .name = "s5pc100-core", ++}; ++ ++static struct sys_device s5pc100_sysdev = { ++ .cls = &s5pc100_sysclass, ++}; ++ ++static int __init s5pc100_core_init(void) ++{ ++ return sysdev_class_register(&s5pc100_sysclass); ++} ++ ++core_initcall(s5pc100_core_init); ++ ++int __init s5pc100_init(void) ++{ ++ printk("S5PC100: Initialising architecture\n"); ++ ++#if defined (CONFIG_S3C_SIR) ++ s3c24xx_uart_src[3]->name = "s3c-irda"; ++#endif ++ ++ return sysdev_register(&s5pc100_sysdev); ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/dma.c linux-2.6.28.6/arch/arm/mach-s5pc100/dma.c +--- linux-2.6.28/arch/arm/mach-s5pc100/dma.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/dma.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,306 @@ ++/* linux/arch/arm/mach-s5pc100/dma.c ++ * ++ * Copyright (c) 2003-2008,2009 Samsung Electronics ++ * ++ * S5PC100 DMA selection ++ * ++ * http://www.samsung.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++/* M2M DMAC */ ++#define MAP0(x) { \ ++ [0] = (x) | DMA_CH_VALID, \ ++ [1] = (x) | DMA_CH_VALID, \ ++ [2] = (x) | DMA_CH_VALID, \ ++ [3] = (x) | DMA_CH_VALID, \ ++ [4] = (x) | DMA_CH_VALID, \ ++ [5] = (x) | DMA_CH_VALID, \ ++ [6] = (x) | DMA_CH_VALID, \ ++ [7] = (x) | DMA_CH_VALID, \ ++ [8] = (x), \ ++ [9] = (x), \ ++ [10] = (x), \ ++ [11] = (x), \ ++ [12] = (x), \ ++ [13] = (x), \ ++ [14] = (x), \ ++ [15] = (x), \ ++ [16] = (x), \ ++ [17] = (x), \ ++ [18] = (x), \ ++ [19] = (x), \ ++ [20] = (x), \ ++ [21] = (x), \ ++ [22] = (x), \ ++ [23] = (x), \ ++ } ++ ++/* Peri-DMAC 0 */ ++#define MAP1(x) { \ ++ [0] = (x), \ ++ [1] = (x), \ ++ [2] = (x), \ ++ [3] = (x), \ ++ [4] = (x), \ ++ [5] = (x), \ ++ [6] = (x), \ ++ [7] = (x), \ ++ [8] = (x) | DMA_CH_VALID, \ ++ [9] = (x) | DMA_CH_VALID, \ ++ [10] = (x) | DMA_CH_VALID, \ ++ [11] = (x) | DMA_CH_VALID, \ ++ [12] = (x) | DMA_CH_VALID, \ ++ [13] = (x) | DMA_CH_VALID, \ ++ [14] = (x) | DMA_CH_VALID, \ ++ [15] = (x) | DMA_CH_VALID, \ ++ [16] = (x), \ ++ [17] = (x), \ ++ [18] = (x), \ ++ [19] = (x), \ ++ [20] = (x), \ ++ [21] = (x), \ ++ [22] = (x), \ ++ [23] = (x), \ ++ } ++ ++/* Peri-DMAC 1 */ ++#define MAP2(x) { \ ++ [0] = (x), \ ++ [1] = (x), \ ++ [2] = (x), \ ++ [3] = (x), \ ++ [4] = (x), \ ++ [5] = (x), \ ++ [6] = (x), \ ++ [7] = (x), \ ++ [8] = (x), \ ++ [9] = (x), \ ++ [10] = (x), \ ++ [11] = (x), \ ++ [12] = (x), \ ++ [13] = (x), \ ++ [14] = (x), \ ++ [15] = (x), \ ++ [16] = (x) | DMA_CH_VALID, \ ++ [17] = (x) | DMA_CH_VALID, \ ++ [18] = (x) | DMA_CH_VALID, \ ++ [19] = (x) | DMA_CH_VALID, \ ++ [20] = (x) | DMA_CH_VALID, \ ++ [21] = (x) | DMA_CH_VALID, \ ++ [22] = (x) | DMA_CH_VALID, \ ++ [23] = (x) | DMA_CH_VALID, \ ++ } ++ ++ ++/* DMA request sources of Peri-DMAC 1 */ ++#define S3C_PDMA1_UART0CH0 0 ++#define S3C_PDMA1_UART0CH1 1 ++#define S3C_PDMA1_UART1CH0 2 ++#define S3C_PDMA1_UART1CH1 3 ++#define S3C_PDMA1_UART2CH0 4 ++#define S3C_PDMA1_UART2CH1 5 ++#define S3C_PDMA1_UART3CH0 6 ++#define S3C_PDMA1_UART3CH1 7 ++#define S3C_PDMA1_IRDA 8 ++#define S3C_PDMA1_I2S0_RX 9 ++#define S3C_PDMA1_I2S0_TX 10 ++#define S3C_PDMA1_I2S0S_TX 11 ++#define S3C_PDMA1_I2S1_RX 12 ++#define S3C_PDMA1_I2S1_TX 13 ++#define S3C_PDMA1_I2S2_RX 14 ++#define S3C_PDMA1_I2S2_TX 15 ++#define S3C_PDMA1_SPI0_RX 16 ++#define S3C_PDMA1_SPI0_TX 17 ++#define S3C_PDMA1_SPI1_RX 18 ++#define S3C_PDMA1_SPI1_TX 19 ++#define S3C_PDMA1_SPI2_RX 20 ++#define S3C_PDMA1_SPI2_TX 21 ++#define S3C_PDMA1_PCM0_RX 22 ++#define S3C_PDMA1_PCM0_TX 23 ++#define S3C_PDMA1_PCM1_RX 24 ++#define S3C_PDMA1_PCM1_TX 25 ++#define S3C_PDMA1_MSM_REQ0 26 ++#define S3C_PDMA1_MSM_REQ1 27 ++#define S3C_PDMA1_MSM_REQ2 28 ++#define S3C_PDMA1_MSM_REQ3 29 ++#define S3C_PDMA1_CG 30 ++#define S3C_PDMA1_Reserved 31 ++ ++ ++/* DMA request sources of Peri-DMAC 0 */ ++#define S3C_PDMA0_UART0CH0 0 ++#define S3C_PDMA0_UART0CH1 1 ++#define S3C_PDMA0_UART1CH0 2 ++#define S3C_PDMA0_UART1CH1 3 ++#define S3C_PDMA0_UART2CH0 4 ++#define S3C_PDMA0_UART2CH1 5 ++#define S3C_PDMA0_UART3CH0 6 ++#define S3C_PDMA0_UART3CH1 7 ++#define S3C_PDMA0_IRDA 8 ++#define S3C_PDMA0_I2S0_RX 9 ++#define S3C_PDMA0_I2S0_TX 10 ++#define S3C_PDMA0_I2S0S_TX 11 ++#define S3C_PDMA0_I2S1_RX 12 ++#define S3C_PDMA0_I2S1_TX 13 ++#define S3C_PDMA0_I2S2_RX 14 ++#define S3C_PDMA0_I2S2_TX 15 ++#define S3C_PDMA0_SPI0_RX 16 ++#define S3C_PDMA0_SPI0_TX 17 ++#define S3C_PDMA0_SPI1_RX 18 ++#define S3C_PDMA0_SPI1_TX 19 ++#define S3C_PDMA0_SPI2_RX 20 ++#define S3C_PDMA0_SPI2_TX 21 ++#define S3C_PDMA0_AC_MICIN 22 ++#define S3C_PDMA0_AC_PCMIN 23 ++#define S3C_PDMA0_AC_PCMOUT 24 ++#define S3C_PDMA0_EXTERNAL 25 ++#define S3C_PDMA0_PWM 26 ++#define S3C_PDMA0_SPDIF 27 ++#define S3C_PDMA0_HSI_TX 28 ++#define S3C_PDMA0_HSI_RX 29 ++#define S3C_PDMA0_Reserved_1 30 ++#define S3C_PDMA0_Reserved 31 ++ ++ ++/* DMA request sources of M2M-DMAC */ ++#define S3C_DMA_SEC_TX 0 ++#define S3C_DMA_SEC_RX 1 ++#define S3C_DMA_M2M 2 ++ ++ ++static struct s3c_dma_map __initdata s5pc100_dma_mappings[] = { ++ ++ [DMACH_I2S_IN] = { ++ .name = "i2s0-in", ++ .channels = MAP1(S3C_PDMA0_I2S0_RX), ++ .hw_addr.from = S3C_PDMA0_I2S0_RX, ++ }, ++ [DMACH_I2S_OUT] = { ++ .name = "i2s0-out", ++ .channels = MAP1(S3C_PDMA0_I2S0_TX), ++ .hw_addr.to = S3C_PDMA0_I2S0_TX, ++ }, ++ [DMACH_I2S1_IN] = { ++ .name = "i2s1-in", ++ .channels = MAP2(S3C_PDMA1_I2S1_RX), ++ .hw_addr.from = S3C_PDMA1_I2S1_RX, ++ }, ++ [DMACH_I2S1_OUT] = { ++ .name = "i2s1-out", ++ .channels = MAP2(S3C_PDMA1_I2S1_TX), ++ .hw_addr.to = S3C_PDMA1_I2S1_TX, ++ }, ++ [DMACH_SPI0_IN] = { ++ .name = "spi0-in", ++ .channels = MAP1(S3C_PDMA0_SPI0_RX), ++ .hw_addr.from = S3C_PDMA0_SPI0_RX, ++ }, ++ [DMACH_SPI0_OUT] = { ++ .name = "spi0-out", ++ .channels = MAP1(S3C_PDMA0_SPI0_TX), ++ .hw_addr.to = S3C_PDMA0_SPI0_TX, ++ }, ++ [DMACH_SPI1_IN] = { ++ .name = "spi1-in", ++ .channels = MAP2(S3C_PDMA1_SPI1_RX), ++ .hw_addr.from = S3C_PDMA1_SPI1_RX, ++ }, ++ [DMACH_SPI1_OUT] = { ++ .name = "spi1-out", ++ .channels = MAP2(S3C_PDMA1_SPI1_TX), ++ .hw_addr.to = S3C_PDMA1_SPI1_TX, ++ }, ++ [DMACH_AC97_PCM_OUT] = { ++ .name = "ac97-pcm-out", ++ .channels = MAP1(S3C_PDMA0_AC_PCMOUT), ++ .hw_addr.to = S3C_PDMA0_AC_PCMOUT, ++ }, ++ [DMACH_AC97_PCM_IN] = { ++ .name = "ac97-pcm-in", ++ .channels = MAP1(S3C_PDMA0_AC_PCMIN), ++ .hw_addr.from = S3C_PDMA0_AC_PCMIN, ++ }, ++ [DMACH_AC97_MIC_IN] = { ++ .name = "ac97-mic-in", ++ .channels = MAP1(S3C_PDMA0_AC_MICIN), ++ .hw_addr.from = S3C_PDMA0_AC_MICIN, ++ }, ++ [DMACH_I2S_V40_IN] = { ++ .name = "i2s-v40-in", ++ .channels = MAP1(S3C_PDMA0_HSI_RX), ++ .hw_addr.from = S3C_PDMA0_HSI_RX, ++ }, ++ [DMACH_I2S_V40_OUT] = { ++ .name = "i2s-v40-out", ++ .channels = MAP1(S3C_PDMA0_HSI_TX), ++ .hw_addr.to = S3C_PDMA0_HSI_TX, ++ }, ++ [DMACH_I2S_V50_OUT] = { ++ .name = "i2s-v50-out", ++ .channels = MAP1(S3C_PDMA1_I2S0_TX), ++ .hw_addr.to = S3C_PDMA1_I2S0_TX, ++ }, ++ [DMACH_I2S_V50_IN] = { ++ .name = "i2s-v50-in", ++ .channels = MAP1(S3C_PDMA1_I2S0_RX), ++ .hw_addr.from = S3C_PDMA1_I2S0_RX, ++ }, ++ [DMACH_ONENAND_IN] = { ++ .name = "onenand-in", ++ .channels = MAP0(S3C_DMA_M2M), ++ .hw_addr.from = 0, ++ }, ++ [DMACH_3D_M2M] = { ++ .name = "3D-M2M", ++ .channels = MAP0(S3C_DMA_M2M), ++ .hw_addr.from = 0, ++ }, ++}; ++ ++static void s5pc100_dma_select(struct s3c2410_dma_chan *chan, ++ struct s3c_dma_map *map) ++{ ++ chan->map = map; ++} ++ ++static struct s3c_dma_selection __initdata s5pc100_dma_sel = { ++ .select = s5pc100_dma_select, ++ .dcon_mask = 0, ++ .map = s5pc100_dma_mappings, ++ .map_size = ARRAY_SIZE(s5pc100_dma_mappings), ++}; ++ ++static int __init s5pc100_dma_add(struct sys_device *sysdev) ++{ ++ s3c_dma_init(S3C_DMA_CHANNELS, IRQ_MDMA, 0x20); ++ return s3c_dma_init_map(&s5pc100_dma_sel); ++} ++ ++static struct sysdev_driver s5pc100_dma_driver = { ++ .add = s5pc100_dma_add, ++}; ++ ++static int __init s5pc100_dma_init(void) ++{ ++ return sysdev_driver_register(&s5pc100_sysclass, &s5pc100_dma_driver); ++} ++ ++arch_initcall(s5pc100_dma_init); ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/include/mach/debug-macro.S linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/debug-macro.S +--- linux-2.6.28/arch/arm/mach-s5pc100/include/mach/debug-macro.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/debug-macro.S 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,39 @@ ++/* arch/arm/mach-s5pc100/include/mach/debug-macro.S ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++/* pull in the relevant register and map files. */ ++ ++#include ++#include ++ ++ /* note, for the boot process to work we have to keep the UART ++ * virtual address aligned to an 1MiB boundary for the L1 ++ * mapping the head code makes. We keep the UART virtual address ++ * aligned and add in the offset when we load the value here. ++ */ ++ ++ .macro addruart, rx ++ mrc p15, 0, \rx, c1, c0 ++ tst \rx, #1 ++ ldreq \rx, = S3C_PA_UART ++ ldrne \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff) ++#if CONFIG_DEBUG_S3C_UART != 0 ++ add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) ++#endif ++ .endm ++ ++/* include the reset of the code which will do the work, we're only ++ * compiling for a single cpu processor type so the default of s3c2440 ++ * will be fine with us. ++ */ ++ ++#include +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/include/mach/dma.h linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/dma.h +--- linux-2.6.28/arch/arm/mach-s5pc100/include/mach/dma.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/dma.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,22 @@ ++/* linux/arch/arm/mach-s5pc100/include/mach/dma.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5PC100 - DMA support ++ */ ++ ++#ifndef __ASM_ARCH_DMA_H ++#define __ASM_ARCH_DMA_H __FILE__ ++ ++#include ++ ++#define S3C_DMA_CONTROLLERS (3) ++#define S3C_CHANNELS_PER_DMA (8) ++#define S3C_CANDIDATE_CHANNELS_PER_DMA (32) ++#define S3C_DMA_CHANNELS (S3C_DMA_CONTROLLERS*S3C_CHANNELS_PER_DMA) ++ ++#endif /* __ASM_ARCH_DMA_H */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/include/mach/entry-macro.S linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/entry-macro.S +--- linux-2.6.28/arch/arm/mach-s5pc100/include/mach/entry-macro.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/entry-macro.S 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,50 @@ ++/* arch/arm/mach-s5pc100/include/mach/entry-macro.S ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * Low-level IRQ helper macros for the Samsung S5PC1XX series ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++*/ ++ ++#include ++#include ++#include ++ ++ .macro disable_fiq ++ .endm ++ ++ .macro get_irqnr_preamble, base, tmp ++ ldr \base, =S3C_VA_VIC0 ++ .endm ++ ++ .macro arch_ret_to_user, tmp1, tmp2 ++ .endm ++ ++ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ++ ++ @ check the vic0 ++ mov \irqnr, # S3C_IRQ_OFFSET + 31 ++ ldr \irqstat, [ \base, # VIC_IRQ_STATUS ] ++ teq \irqstat, #0 ++ ++ @ otherwise try vic1 ++ addeq \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0) ++ addeq \irqnr, \irqnr, #32 ++ ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] ++ teqeq \irqstat, #0 ++ ++ @ otherwise try vic2 ++ addeq \tmp, \base, #(S3C_VA_VIC2 - S3C_VA_VIC0) ++ addeq \irqnr, \irqnr, #32 ++ ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] ++ teqeq \irqstat, #0 ++ ++ clzne \irqstat, \irqstat ++ subne \irqnr, \irqnr, \irqstat ++ .endm +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/include/mach/gpio-core.h linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/gpio-core.h +--- linux-2.6.28/arch/arm/mach-s5pc100/include/mach/gpio-core.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/gpio-core.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,21 @@ ++/* arch/arm/mach-s5pc100/include/mach/gpio-core.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5PC1XX - GPIO core support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_GPIO_CORE_H ++#define __ASM_ARCH_GPIO_CORE_H __FILE__ ++ ++/* currently we just include the platform support */ ++#include ++ ++#endif /* __ASM_ARCH_GPIO_CORE_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/include/mach/gpio.h linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/gpio.h +--- linux-2.6.28/arch/arm/mach-s5pc100/include/mach/gpio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/gpio.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,146 @@ ++/* arch/arm/mach-s5pc100/include/mach/gpio.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S5PC100 - GPIO lib support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define gpio_get_value __gpio_get_value ++#define gpio_set_value __gpio_set_value ++#define gpio_cansleep __gpio_cansleep ++#define gpio_to_irq __gpio_to_irq ++ ++/* GPIO bank sizes */ ++#define S5PC1XX_GPIO_A0_NR (8) ++#define S5PC1XX_GPIO_A1_NR (5) ++#define S5PC1XX_GPIO_B_NR (8) ++#define S5PC1XX_GPIO_C_NR (5) ++#define S5PC1XX_GPIO_D_NR (7) ++#define S5PC1XX_GPIO_E0_NR (8) ++#define S5PC1XX_GPIO_E1_NR (6) ++#define S5PC1XX_GPIO_F0_NR (8) ++#define S5PC1XX_GPIO_F1_NR (8) ++#define S5PC1XX_GPIO_F2_NR (8) ++#define S5PC1XX_GPIO_F3_NR (4) ++#define S5PC1XX_GPIO_G0_NR (8) ++#define S5PC1XX_GPIO_G1_NR (3) ++#define S5PC1XX_GPIO_G2_NR (7) ++#define S5PC1XX_GPIO_G3_NR (7) ++#define S5PC1XX_GPIO_H0_NR (8) ++#define S5PC1XX_GPIO_H1_NR (8) ++#define S5PC1XX_GPIO_H2_NR (8) ++#define S5PC1XX_GPIO_H3_NR (8) ++#define S5PC1XX_GPIO_I_NR (8) ++#define S5PC1XX_GPIO_J0_NR (8) ++#define S5PC1XX_GPIO_J1_NR (5) ++#define S5PC1XX_GPIO_J2_NR (8) ++#define S5PC1XX_GPIO_J3_NR (8) ++#define S5PC1XX_GPIO_J4_NR (4) ++#define S5PC1XX_GPIO_K0_NR (8) ++#define S5PC1XX_GPIO_K1_NR (6) ++#define S5PC1XX_GPIO_K2_NR (8) ++#define S5PC1XX_GPIO_K3_NR (8) ++#define S5PC1XX_GPIO_MP00_NR (8) ++#define S5PC1XX_GPIO_MP01_NR (8) ++#define S5PC1XX_GPIO_MP02_NR (8) ++#define S5PC1XX_GPIO_MP03_NR (8) ++#define S5PC1XX_GPIO_MP04_NR (5) ++ ++/* GPIO bank numbes */ ++ ++/* CONFIG_S3C_GPIO_SPACE allows the user to select extra ++ * space for debugging purposes so that any accidental ++ * change from one gpio bank to another can be caught. ++*/ ++ ++#define S5PC1XX_GPIO_NEXT(__gpio) \ ++ ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) ++ ++enum s3c_gpio_number { ++ S5PC1XX_GPIO_A0_START = 0, ++ S5PC1XX_GPIO_A1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A0), ++ S5PC1XX_GPIO_B_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A1), ++ S5PC1XX_GPIO_C_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_B), ++ S5PC1XX_GPIO_D_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_C), ++ S5PC1XX_GPIO_E0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_D), ++ S5PC1XX_GPIO_E1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E0), ++ S5PC1XX_GPIO_F0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E1), ++ S5PC1XX_GPIO_F1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F0), ++ S5PC1XX_GPIO_F2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F1), ++ S5PC1XX_GPIO_F3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F2), ++ S5PC1XX_GPIO_G0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F3), ++ S5PC1XX_GPIO_G1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G0), ++ S5PC1XX_GPIO_G2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G1), ++ S5PC1XX_GPIO_G3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G2), ++ S5PC1XX_GPIO_H0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G3), ++ S5PC1XX_GPIO_H1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H0), ++ S5PC1XX_GPIO_H2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H1), ++ S5PC1XX_GPIO_H3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H2), ++ S5PC1XX_GPIO_I_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H3), ++ S5PC1XX_GPIO_J0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_I), ++ S5PC1XX_GPIO_J1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J0), ++ S5PC1XX_GPIO_J2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J1), ++ S5PC1XX_GPIO_J3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J2), ++ S5PC1XX_GPIO_J4_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J3), ++ S5PC1XX_GPIO_K0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J4), ++ S5PC1XX_GPIO_K1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K0), ++ S5PC1XX_GPIO_K2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K1), ++ S5PC1XX_GPIO_K3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K2), ++ S5PC1XX_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K3), ++ S5PC1XX_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP00), ++ S5PC1XX_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP01), ++ S5PC1XX_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP02), ++ S5PC1XX_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP03), ++}; ++ ++/* S5PC1XX GPIO number definitions. */ ++#define S5PC1XX_GPA0(_nr) (S5PC1XX_GPIO_A0_START + (_nr)) ++#define S5PC1XX_GPA1(_nr) (S5PC1XX_GPIO_A1_START + (_nr)) ++#define S5PC1XX_GPB(_nr) (S5PC1XX_GPIO_B_START + (_nr)) ++#define S5PC1XX_GPC(_nr) (S5PC1XX_GPIO_C_START + (_nr)) ++#define S5PC1XX_GPD(_nr) (S5PC1XX_GPIO_D_START + (_nr)) ++#define S5PC1XX_GPE0(_nr) (S5PC1XX_GPIO_E0_START + (_nr)) ++#define S5PC1XX_GPE1(_nr) (S5PC1XX_GPIO_E1_START + (_nr)) ++#define S5PC1XX_GPF0(_nr) (S5PC1XX_GPIO_F0_START + (_nr)) ++#define S5PC1XX_GPF1(_nr) (S5PC1XX_GPIO_F1_START + (_nr)) ++#define S5PC1XX_GPF2(_nr) (S5PC1XX_GPIO_F2_START + (_nr)) ++#define S5PC1XX_GPF3(_nr) (S5PC1XX_GPIO_F3_START + (_nr)) ++#define S5PC1XX_GPG0(_nr) (S5PC1XX_GPIO_G0_START + (_nr)) ++#define S5PC1XX_GPG1(_nr) (S5PC1XX_GPIO_G1_START + (_nr)) ++#define S5PC1XX_GPG2(_nr) (S5PC1XX_GPIO_G2_START + (_nr)) ++#define S5PC1XX_GPG3(_nr) (S5PC1XX_GPIO_G3_START + (_nr)) ++#define S5PC1XX_GPH0(_nr) (S5PC1XX_GPIO_H0_START + (_nr)) ++#define S5PC1XX_GPH1(_nr) (S5PC1XX_GPIO_H1_START + (_nr)) ++#define S5PC1XX_GPH2(_nr) (S5PC1XX_GPIO_H2_START + (_nr)) ++#define S5PC1XX_GPH3(_nr) (S5PC1XX_GPIO_H3_START + (_nr)) ++#define S5PC1XX_GPI(_nr) (S5PC1XX_GPIO_I_START + (_nr)) ++#define S5PC1XX_GPJ0(_nr) (S5PC1XX_GPIO_J0_START + (_nr)) ++#define S5PC1XX_GPJ1(_nr) (S5PC1XX_GPIO_J1_START + (_nr)) ++#define S5PC1XX_GPJ2(_nr) (S5PC1XX_GPIO_J2_START + (_nr)) ++#define S5PC1XX_GPJ3(_nr) (S5PC1XX_GPIO_J3_START + (_nr)) ++#define S5PC1XX_GPJ4(_nr) (S5PC1XX_GPIO_J4_START + (_nr)) ++#define S5PC1XX_GPK0(_nr) (S5PC1XX_GPIO_K0_START + (_nr)) ++#define S5PC1XX_GPK1(_nr) (S5PC1XX_GPIO_K1_START + (_nr)) ++#define S5PC1XX_GPK2(_nr) (S5PC1XX_GPIO_K2_START + (_nr)) ++#define S5PC1XX_GPK3(_nr) (S5PC1XX_GPIO_K3_START + (_nr)) ++#define S5PC1XX_MP00(_nr) (S5PC1XX_GPIO_MP00_START + (_nr)) ++#define S5PC1XX_MP01(_nr) (S5PC1XX_GPIO_MP01_START + (_nr)) ++#define S5PC1XX_MP02(_nr) (S5PC1XX_GPIO_MP02_START + (_nr)) ++#define S5PC1XX_MP03(_nr) (S5PC1XX_GPIO_MP03_START + (_nr)) ++#define S5PC1XX_MP04(_nr) (S5PC1XX_GPIO_MP04_START + (_nr)) ++ ++/* the end of the S5PC1XX specific gpios */ ++#define S5PC1XX_GPIO_END (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1) ++#define S3C_GPIO_END S5PC1XX_GPIO_END ++ ++/* define the number of gpios we need to the one after the MP04() range */ ++#define ARCH_NR_GPIOS (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1) ++ ++#include +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/include/mach/hardware.h linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/hardware.h +--- linux-2.6.28/arch/arm/mach-s5pc100/include/mach/hardware.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/hardware.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,16 @@ ++/* linux/arch/arm/mach-s5pc100/include/mach/hardware.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C6400 - Hardware support ++ */ ++ ++#ifndef __ASM_ARCH_HARDWARE_H ++#define __ASM_ARCH_HARDWARE_H __FILE__ ++ ++/* currently nothing here, placeholder */ ++ ++#endif /* __ASM_ARCH_HARDWARE_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/include/mach/idle.h linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/idle.h +--- linux-2.6.28/arch/arm/mach-s5pc100/include/mach/idle.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/idle.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,24 @@ ++/* arch/arm/mach-s5pc100/include/mach/idle.h ++ * ++ * Copyright (c) 2004 Simtec Electronics ++ * http://www.simtec.co.uk/products/SWLINUX/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S5PC100 CPU Idle controls ++*/ ++ ++#ifndef __ASM_ARCH_IDLE_H ++#define __ASM_ARCH_IDLE_H __FILE__ ++ ++/* This allows the over-ride of the default idle code, in case there ++ * is any other things to be done over idle (like DVS) ++*/ ++ ++extern void (*s5pc1xx_idle)(void); ++ ++extern void s5pc1xx_default_idle(void); ++ ++#endif /* __ASM_ARCH_IDLE_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/include/mach/irqs.h linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/irqs.h +--- linux-2.6.28/arch/arm/mach-s5pc100/include/mach/irqs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/irqs.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,20 @@ ++/* linux/arch/arm/mach-s5pc100/include/mach/irqs.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5PC100 - IRQ definitions ++ */ ++ ++#ifndef __ASM_ARCH_IRQS_H ++#define __ASM_ARCH_IRQS_H __FILE__ ++ ++#ifndef __ASM_ARM_IRQ_H ++#error "Do not include this directly, instead #include " ++#endif ++ ++#include ++ ++#endif /* __ASM_ARCH_IRQ_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/include/mach/map.h linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/map.h +--- linux-2.6.28/arch/arm/mach-s5pc100/include/mach/map.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/map.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,182 @@ ++/* linux/arch/arm/mach-s5pc100/include/mach/map.h ++ * ++ * Copyright 2008 Samsung Electronics Co. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S5PC1XX - Memory map definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_MAP_H ++#define __ASM_ARCH_MAP_H __FILE__ ++ ++#include ++ ++#define S3C_PA_UART (0xEC000000) ++#define S3C_PA_UART0 (S3C_PA_UART + 0x00) ++#define S3C_PA_UART1 (S3C_PA_UART + 0x400) ++#define S3C_PA_UART2 (S3C_PA_UART + 0x800) ++#define S3C_PA_UART3 (S3C_PA_UART + 0xC00) ++#define S3C_UART_OFFSET (0x400) ++ ++/* See notes on UART VA mapping in debug-macro.S */ ++#define S3C_VA_UARTx(x) (S3C_VA_UART + (S3C_PA_UART & 0xfffff) + ((x) * S3C_UART_OFFSET)) ++ ++#define S3C_VA_UART0 S3C_VA_UARTx(0) ++#define S3C_VA_UART1 S3C_VA_UARTx(1) ++#define S3C_VA_UART2 S3C_VA_UARTx(2) ++#define S3C_VA_UART3 S3C_VA_UARTx(3) ++ ++#define S5PC1XX_PA_SYSCON (0xE0100000) ++#define S5PC1XX_VA_SYSCON S3C_VA_SYS ++#define S5PC1XX_SZ_SYSCON SZ_2M ++ ++#define S5PC1XX_PA_TIMER (0xEA000000) ++#define S5PC1XX_PA_IIC0 (0xEC100000) ++#define S5PC1XX_PA_IIC1 (0xEC200000) ++ ++#define S5PC1XX_PA_GPIO (0xE0300000) ++#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) ++#define S5PC1XX_SZ_GPIO SZ_4K ++ ++#define S5PC1XX_PA_SDRAM (0x20000000) ++#define S5PC1XX_PA_VIC0 (0xE4000000) ++#define S5PC1XX_PA_VIC1 (0xE4100000) ++#define S5PC1XX_PA_VIC2 (0xE4200000) ++ ++#define S5PC1XX_VA_SROMC S3C_VA_SROMC ++#define S5PC1XX_PA_SROMC (0xE7000000) ++#define S5PC1XX_SZ_SROMC SZ_4K ++ ++#define S5PC1XX_VA_LCD S3C_VA_LCD ++#define S5PC1XX_PA_LCD (0xEE000000) ++#define S5PC1XX_SZ_LCD SZ_1M ++ ++#define S5PC1XX_PA_G2D (0xEE800000) ++#define S5PC1XX_SZ_G2D SZ_1M ++ ++#define S5PC1XX_VA_SYSTIMER S3C_VA_SYSTIMER ++#define S5PC1XX_PA_SYSTIMER (0xEA100000) ++#define S5PC1XX_SZ_SYSTIMER SZ_1M ++ ++#define S5PC1XX_PA_ADC (0xF3000000) ++#define S5PC1XX_PA_SMC9115 (0x98000000) ++#define S5PC1XX_PA_RTC (0xEA300000) ++ ++#define S5PC1XX_PA_IIS (0xF2000000) ++#define S3C_SZ_IIS SZ_4K ++ ++#define S5PC1XX_PA_CHIPID (0xE0000000) ++#define S5PC1XX_VA_CHIPID S3C_ADDR(0x00700000) ++ ++/* NAND flash controller */ ++#define S5PC1XX_VA_NAND S3C_VA_NAND ++#define S5PC1XX_PA_NAND (0xE7200000) ++#define S5PC1XX_SZ_NAND SZ_1M ++ ++/* DMA controller */ ++#define S5PC1XX_PA_DMA (0xE8100000) ++ ++/* place VICs close together */ ++#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x0) ++#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) ++#define S3C_VA_VIC2 (S3C_VA_IRQ + 0x20000) ++ ++/* USB Host */ ++#define S5PC1XX_PA_USBHOST (0xED400000) ++#define S5PC1XX_SZ_USBHOST SZ_1M ++ ++/* USB OTG */ ++#define S5PC1XX_VA_OTG S3C_ADDR(0x00E00000) ++#define S5PC1XX_PA_OTG (0xED200000) ++#define S5PC1XX_SZ_OTG SZ_1M ++ ++/* USB OTG SFR */ ++#define S5PC1XX_VA_OTGSFR S3C_ADDR(0x00F00000) ++#define S5PC1XX_PA_OTGSFR (0xED300000) ++#define S5PC1XX_SZ_OTGSFR SZ_1M ++ ++/* FIMC */ ++#define S5PC1XX_PA_FIMC0 (0xEE200000) ++#define S5PC1XX_PA_FIMC1 (0xEE300000) ++#define S5PC1XX_PA_FIMC2 (0xEE400000) ++ ++/* HSMMC units */ ++#define S5PC1XX_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) ++#define S5PC1XX_PA_HSMMC0 S5PC1XX_PA_HSMMC(0) ++#define S5PC1XX_PA_HSMMC1 S5PC1XX_PA_HSMMC(1) ++#define S5PC1XX_PA_HSMMC2 S5PC1XX_PA_HSMMC(2) ++#define S5PC1XX_SZ_HSMMC SZ_1M ++ ++#define S3C_PA_HSMMC0 S5PC1XX_PA_HSMMC0 ++#define S3C_PA_HSMMC1 S5PC1XX_PA_HSMMC1 ++#define S3C_PA_HSMMC2 S5PC1XX_PA_HSMMC2 ++ ++#define S5PC1XX_PA_SPI(x) (0xEC300000 + ((x) * 0x100000)) ++#define S5PC1XX_SZ_SPI SZ_1M ++#define S5PC1XX_PA_SPI0 S5PC1XX_PA_SPI(0) ++#define S5PC1XX_PA_SPI1 S5PC1XX_PA_SPI(1) ++#define S5PC1XX_PA_SPI2 S5PC1XX_PA_SPI(2) ++ ++#define S5PC1XX_PA_ONENAND (0xE7100000) ++#define S5PC1XX_SZ_ONENAND SZ_1M ++ ++#define S5PC1XX_PA_KEYPAD (0xF3100000) ++#define S5PC1XX_SZ_KEYPAD SZ_4K ++ ++#define S3C_PA_IIS S5PC1XX_PA_IIS ++#define S3C_PA_ADC S5PC1XX_PA_ADC ++#define S3C_PA_DMA S5PC1XX_PA_DMA ++#define S3C_PA_RTC S5PC1XX_PA_RTC ++#define S3C_PA_KEYPAD S5PC1XX_PA_KEYPAD ++#define S3C_SZ_KEYPAD S5PC1XX_SZ_KEYPAD ++ ++/* WATCHDOG TIMER*/ ++#define S5PC1XX_PA_WDT (0xEA200000) ++#define S3C_PA_WDT S5PC1XX_PA_WDT ++ ++/* MFC V4.0 */ ++#define S5PC1XX_PA_MFC (0xF1000000) ++#define S5PC1XX_SZ_MFC SZ_4K ++ ++/* JPEG */ ++#define S5PC1XX_PA_JPEG (0xEE500000) ++#define S5PC1XX_SZ_JPEG SZ_1M ++ ++/* AC97 */ ++#define S5PC1XX_PA_AC97 (0xF2300000) ++#define S5PC1XX_SZ_AC97 SZ_1M ++ ++/* G3D */ ++#define S5PC1XX_PA_G3D (0xEF000000) ++#define S5PC1XX_SZ_G3D SZ_16M ++ ++/* Rotator */ ++#define S5PC1XX_PA_ROTATOR (0xEE100000) ++#define S5PC1XX_SZ_ROTATOR SZ_1M ++ ++/* MIPI CSIS */ ++#define S5PC1XX_PA_CSIS (0xECC00000) ++#define S5PC1XX_SZ_CSIS SZ_1M ++ ++/* compatibiltiy defines. */ ++#define S3C_SZ_HSMMC S5PC1XX_SZ_HSMMC ++ ++#define S3C_PA_TIMER S5PC1XX_PA_TIMER ++#define S3C_PA_IIC S5PC1XX_PA_IIC0 ++#define S3C_PA_IIC1 S5PC1XX_PA_IIC1 ++ ++#define S3C_VA_OTG S5PC1XX_VA_OTG ++#define S3C_PA_OTG S5PC1XX_PA_OTG ++#define S3C_SZ_OTG S5PC1XX_SZ_OTG ++ ++#define S3C_VA_OTGSFR S5PC1XX_VA_OTGSFR ++#define S3C_PA_OTGSFR S5PC1XX_PA_OTGSFR ++#define S3C_SZ_OTGSFR S5PC1XX_SZ_OTGSFR ++ ++#endif /* __ASM_ARCH_6400_MAP_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/include/mach/memory.h linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/memory.h +--- linux-2.6.28/arch/arm/mach-s5pc100/include/mach/memory.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/memory.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,22 @@ ++/* arch/arm/mach-s5pc100/include/mach/memory.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_MEMORY_H ++#define __ASM_ARCH_MEMORY_H ++ ++#define PHYS_OFFSET UL(0x20000000) ++#define CONSISTENT_DMA_SIZE (SZ_8M + SZ_4M + SZ_2M) ++ ++#define __virt_to_bus(x) __virt_to_phys(x) ++#define __bus_to_virt(x) __phys_to_virt(x) ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/include/mach/regs-irq.h linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/regs-irq.h +--- linux-2.6.28/arch/arm/mach-s5pc100/include/mach/regs-irq.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/regs-irq.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,277 @@ ++/* linux/arch/arm/mach-s5pc100/include/mach/regs-irq.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S5PC1XX - IRQ register definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_REGS_IRQ_H ++#define __ASM_ARCH_REGS_IRQ_H __FILE__ ++ ++#include ++#include ++/* interrupt controller */ ++#define S5PC100_VIC0REG(x) ((x) + S3C_VA_VIC0) ++#define S5PC100_VIC1REG(x) ((x) + S3C_VA_VIC1) ++#define S5PC100_VIC2REG(x) ((x) + S3C_VA_VIC2) ++ ++#define S5PC100_VIC0IRQSTATUS S5PC100_VIC0REG(0x000) ++#define S5PC100_VIC0FIQSTATUS S5PC100_VIC0REG(0x004) ++#define S5PC100_VIC0RAWINTR S5PC100_VIC0REG(0x008) ++#define S5PC100_VIC0INTSELECT S5PC100_VIC0REG(0x00C) ++#define S5PC100_VIC0INTENABLE S5PC100_VIC0REG(0x010) ++#define S5PC100_VIC0INTENCLEAR S5PC100_VIC0REG(0x014) ++#define S5PC100_VIC0SOFTINT S5PC100_VIC0REG(0x018) ++#define S5PC100_VIC0SOFTINTCLEAR S5PC100_VIC0REG(0x01C) ++#define S5PC100_VIC0PROTECTION S5PC100_VIC0REG(0x020) ++#define S5PC100_VIC0SWPRIORITYMASK S5PC100_VIC0REG(0x024) ++#define S5PC100_VIC0PRIORITYDAISY S5PC100_VIC0REG(0x028) ++#define S5PC100_VIC0VECTADDR0 S5PC100_VIC0REG(0x100) ++#define S5PC100_VIC0VECTADDR1 S5PC100_VIC0REG(0x104) ++#define S5PC100_VIC0VECTADDR2 S5PC100_VIC0REG(0x108) ++#define S5PC100_VIC0VECTADDR3 S5PC100_VIC0REG(0x10C) ++#define S5PC100_VIC0VECTADDR4 S5PC100_VIC0REG(0x110) ++#define S5PC100_VIC0VECTADDR5 S5PC100_VIC0REG(0x114) ++#define S5PC100_VIC0VECTADDR6 S5PC100_VIC0REG(0x118) ++#define S5PC100_VIC0VECTADDR7 S5PC100_VIC0REG(0x11C) ++#define S5PC100_VIC0VECTADDR8 S5PC100_VIC0REG(0x120) ++#define S5PC100_VIC0VECTADDR9 S5PC100_VIC0REG(0x124) ++#define S5PC100_VIC0VECTADDR10 S5PC100_VIC0REG(0x128) ++#define S5PC100_VIC0VECTADDR11 S5PC100_VIC0REG(0x12C) ++#define S5PC100_VIC0VECTADDR12 S5PC100_VIC0REG(0x130) ++#define S5PC100_VIC0VECTADDR13 S5PC100_VIC0REG(0x134) ++#define S5PC100_VIC0VECTADDR14 S5PC100_VIC0REG(0x138) ++#define S5PC100_VIC0VECTADDR15 S5PC100_VIC0REG(0x13C) ++#define S5PC100_VIC0VECTADDR16 S5PC100_VIC0REG(0x140) ++#define S5PC100_VIC0VECTADDR17 S5PC100_VIC0REG(0x144) ++#define S5PC100_VIC0VECTADDR18 S5PC100_VIC0REG(0x148) ++#define S5PC100_VIC0VECTADDR19 S5PC100_VIC0REG(0x14C) ++#define S5PC100_VIC0VECTADDR20 S5PC100_VIC0REG(0x150) ++#define S5PC100_VIC0VECTADDR21 S5PC100_VIC0REG(0x154) ++#define S5PC100_VIC0VECTADDR22 S5PC100_VIC0REG(0x158) ++#define S5PC100_VIC0VECTADDR23 S5PC100_VIC0REG(0x15C) ++#define S5PC100_VIC0VECTADDR24 S5PC100_VIC0REG(0x160) ++#define S5PC100_VIC0VECTADDR25 S5PC100_VIC0REG(0x164) ++#define S5PC100_VIC0VECTADDR26 S5PC100_VIC0REG(0x168) ++#define S5PC100_VIC0VECTADDR27 S5PC100_VIC0REG(0x16C) ++#define S5PC100_VIC0VECTADDR28 S5PC100_VIC0REG(0x170) ++#define S5PC100_VIC0VECTADDR29 S5PC100_VIC0REG(0x174) ++#define S5PC100_VIC0VECTADDR30 S5PC100_VIC0REG(0x178) ++#define S5PC100_VIC0VECTADDR31 S5PC100_VIC0REG(0x17C) ++#define S5PC100_VIC0VECPRIORITY0 S5PC100_VIC0REG(0x200) ++#define S5PC100_VIC0VECTPRIORITY1 S5PC100_VIC0REG(0x204) ++#define S5PC100_VIC0VECTPRIORITY2 S5PC100_VIC0REG(0x208) ++#define S5PC100_VIC0VECTPRIORITY3 S5PC100_VIC0REG(0x20C) ++#define S5PC100_VIC0VECTPRIORITY4 S5PC100_VIC0REG(0x210) ++#define S5PC100_VIC0VECTPRIORITY5 S5PC100_VIC0REG(0x214) ++#define S5PC100_VIC0VECTPRIORITY6 S5PC100_VIC0REG(0x218) ++#define S5PC100_VIC0VECTPRIORITY7 S5PC100_VIC0REG(0x21C) ++#define S5PC100_VIC0VECTPRIORITY8 S5PC100_VIC0REG(0x220) ++#define S5PC100_VIC0VECTPRIORITY9 S5PC100_VIC0REG(0x224) ++#define S5PC100_VIC0VECTPRIORITY10 S5PC100_VIC0REG(0x228) ++#define S5PC100_VIC0VECTPRIORITY11 S5PC100_VIC0REG(0x22C) ++#define S5PC100_VIC0VECTPRIORITY12 S5PC100_VIC0REG(0x230) ++#define S5PC100_VIC0VECTPRIORITY13 S5PC100_VIC0REG(0x234) ++#define S5PC100_VIC0VECTPRIORITY14 S5PC100_VIC0REG(0x238) ++#define S5PC100_VIC0VECTPRIORITY15 S5PC100_VIC0REG(0x23C) ++#define S5PC100_VIC0VECTPRIORITY16 S5PC100_VIC0REG(0x240) ++#define S5PC100_VIC0VECTPRIORITY17 S5PC100_VIC0REG(0x244) ++#define S5PC100_VIC0VECTPRIORITY18 S5PC100_VIC0REG(0x248) ++#define S5PC100_VIC0VECTPRIORITY19 S5PC100_VIC0REG(0x24C) ++#define S5PC100_VIC0VECTPRIORITY20 S5PC100_VIC0REG(0x250) ++#define S5PC100_VIC0VECTPRIORITY21 S5PC100_VIC0REG(0x254) ++#define S5PC100_VIC0VECTPRIORITY22 S5PC100_VIC0REG(0x258) ++#define S5PC100_VIC0VECTPRIORITY23 S5PC100_VIC0REG(0x25C) ++#define S5PC100_VIC0VECTPRIORITY24 S5PC100_VIC0REG(0x260) ++#define S5PC100_VIC0VECTPRIORITY25 S5PC100_VIC0REG(0x264) ++#define S5PC100_VIC0VECTPRIORITY26 S5PC100_VIC0REG(0x268) ++#define S5PC100_VIC0VECTPRIORITY27 S5PC100_VIC0REG(0x26C) ++#define S5PC100_VIC0VECTPRIORITY28 S5PC100_VIC0REG(0x270) ++#define S5PC100_VIC0VECTPRIORITY29 S5PC100_VIC0REG(0x274) ++#define S5PC100_VIC0VECTPRIORITY30 S5PC100_VIC0REG(0x278) ++#define S5PC100_VIC0VECTPRIORITY31 S5PC100_VIC0REG(0x27C) ++#define S5PC100_VIC0ADDRESS S5PC100_VIC0REG(0xF00) ++#define S5PC100_VIC0PERIPHID0 S5PC100_VIC0REG(0xFE0) ++#define S5PC100_VIC0PERIPHID1 S5PC100_VIC0REG(0xFE4) ++#define S5PC100_VIC0PERIPHID2 S5PC100_VIC0REG(0xFE8) ++#define S5PC100_VIC0PERIPHID3 S5PC100_VIC0REG(0xFEC) ++#define S5PC100_VIC0PCELLID0 S5PC100_VIC0REG(0xFF0) ++#define S5PC100_VIC0PCELLID1 S5PC100_VIC0REG(0xFF4) ++#define S5PC100_VIC0PCELLID2 S5PC100_VIC0REG(0xFF8) ++#define S5PC100_VIC0PCELLID3 S5PC100_VIC0REG(0xFFC) ++#define S5PC100_VIC1IRQSTATUS S5PC100_VIC1REG(0x000) ++#define S5PC100_VIC1FIQSTATUS S5PC100_VIC1REG(0x004) ++#define S5PC100_VIC1RAWINTR S5PC100_VIC1REG(0x008) ++#define S5PC100_VIC1INTSELECT S5PC100_VIC1REG(0x00C) ++#define S5PC100_VIC1INTENABLE S5PC100_VIC1REG(0x010) ++#define S5PC100_VIC1INTENCLEAR S5PC100_VIC1REG(0x014) ++#define S5PC100_VIC1SOFTINT S5PC100_VIC1REG(0x018) ++#define S5PC100_VIC1SOFTINTCLEAR S5PC100_VIC1REG(0x01C) ++#define S5PC100_VIC1PROTECTION S5PC100_VIC1REG(0x020) ++#define S5PC100_VIC1SWPRIORITYMASK S5PC100_VIC1REG(0x024) ++#define S5PC100_VIC1PRIORITYDAISY S5PC100_VIC1REG(0x028) ++#define S5PC100_VIC1VECTADDR0 S5PC100_VIC1REG(0x100) ++#define S5PC100_VIC1VECTADDR1 S5PC100_VIC1REG(0x104) ++#define S5PC100_VIC1VECTADDR2 S5PC100_VIC1REG(0x108) ++#define S5PC100_VIC1VECTADDR3 S5PC100_VIC1REG(0x10C) ++#define S5PC100_VIC1VECTADDR4 S5PC100_VIC1REG(0x110) ++#define S5PC100_VIC1VECTADDR5 S5PC100_VIC1REG(0x114) ++#define S5PC100_VIC1VECTADDR6 S5PC100_VIC1REG(0x118) ++#define S5PC100_VIC1VECTADDR7 S5PC100_VIC1REG(0x11C) ++#define S5PC100_VIC1VECTADDR8 S5PC100_VIC1REG(0x120) ++#define S5PC100_VIC1VECTADDR9 S5PC100_VIC1REG(0x124) ++#define S5PC100_VIC1VECTADDR10 S5PC100_VIC1REG(0x128) ++#define S5PC100_VIC1VECTADDR11 S5PC100_VIC1REG(0x12C) ++#define S5PC100_VIC1VECTADDR12 S5PC100_VIC1REG(0x130) ++#define S5PC100_VIC1VECTADDR13 S5PC100_VIC1REG(0x134) ++#define S5PC100_VIC1VECTADDR14 S5PC100_VIC1REG(0x138) ++#define S5PC100_VIC1VECTADDR15 S5PC100_VIC1REG(0x13C) ++#define S5PC100_VIC1VECTADDR16 S5PC100_VIC1REG(0x140) ++#define S5PC100_VIC1VECTADDR17 S5PC100_VIC1REG(0x144) ++#define S5PC100_VIC1VECTADDR18 S5PC100_VIC1REG(0x148) ++#define S5PC100_VIC1VECTADDR19 S5PC100_VIC1REG(0x14C) ++#define S5PC100_VIC1VECTADDR20 S5PC100_VIC1REG(0x150) ++#define S5PC100_VIC1VECTADDR21 S5PC100_VIC1REG(0x154) ++#define S5PC100_VIC1VECTADDR22 S5PC100_VIC1REG(0x158) ++#define S5PC100_VIC1VECTADDR23 S5PC100_VIC1REG(0x15C) ++#define S5PC100_VIC1VECTADDR24 S5PC100_VIC1REG(0x160) ++#define S5PC100_VIC1VECTADDR25 S5PC100_VIC1REG(0x164) ++#define S5PC100_VIC1VECTADDR26 S5PC100_VIC1REG(0x168) ++#define S5PC100_VIC1VECTADDR27 S5PC100_VIC1REG(0x16C) ++#define S5PC100_VIC1VECTADDR28 S5PC100_VIC1REG(0x170) ++#define S5PC100_VIC1VECTADDR29 S5PC100_VIC1REG(0x174) ++#define S5PC100_VIC1VECTADDR30 S5PC100_VIC1REG(0x178) ++#define S5PC100_VIC1VECTADDR31 S5PC100_VIC1REG(0x17C) ++#define S5PC100_VIC1VECPRIORITY0 S5PC100_VIC1REG(0x200) ++#define S5PC100_VIC1VECTPRIORITY1 S5PC100_VIC1REG(0x204) ++#define S5PC100_VIC1VECTPRIORITY2 S5PC100_VIC1REG(0x208) ++#define S5PC100_VIC1VECTPRIORITY3 S5PC100_VIC1REG(0x20C) ++#define S5PC100_VIC1VECTPRIORITY4 S5PC100_VIC1REG(0x210) ++#define S5PC100_VIC1VECTPRIORITY5 S5PC100_VIC1REG(0x214) ++#define S5PC100_VIC1VECTPRIORITY6 S5PC100_VIC1REG(0x218) ++#define S5PC100_VIC1VECTPRIORITY7 S5PC100_VIC1REG(0x21C) ++#define S5PC100_VIC1VECTPRIORITY8 S5PC100_VIC1REG(0x220) ++#define S5PC100_VIC1VECTPRIORITY9 S5PC100_VIC1REG(0x224) ++#define S5PC100_VIC1VECTPRIORITY10 S5PC100_VIC1REG(0x228) ++#define S5PC100_VIC1VECTPRIORITY11 S5PC100_VIC1REG(0x22C) ++#define S5PC100_VIC1VECTPRIORITY12 S5PC100_VIC1REG(0x230) ++#define S5PC100_VIC1VECTPRIORITY13 S5PC100_VIC1REG(0x234) ++#define S5PC100_VIC1VECTPRIORITY14 S5PC100_VIC1REG(0x238) ++#define S5PC100_VIC1VECTPRIORITY15 S5PC100_VIC1REG(0x23C) ++#define S5PC100_VIC1VECTPRIORITY16 S5PC100_VIC1REG(0x240) ++#define S5PC100_VIC1VECTPRIORITY17 S5PC100_VIC1REG(0x244) ++#define S5PC100_VIC1VECTPRIORITY18 S5PC100_VIC1REG(0x248) ++#define S5PC100_VIC1VECTPRIORITY19 S5PC100_VIC1REG(0x24C) ++#define S5PC100_VIC1VECTPRIORITY20 S5PC100_VIC1REG(0x250) ++#define S5PC100_VIC1VECTPRIORITY21 S5PC100_VIC1REG(0x254) ++#define S5PC100_VIC1VECTPRIORITY22 S5PC100_VIC1REG(0x258) ++#define S5PC100_VIC1VECTPRIORITY23 S5PC100_VIC1REG(0x25C) ++#define S5PC100_VIC1VECTPRIORITY24 S5PC100_VIC1REG(0x260) ++#define S5PC100_VIC1VECTPRIORITY25 S5PC100_VIC1REG(0x264) ++#define S5PC100_VIC1VECTPRIORITY26 S5PC100_VIC1REG(0x268) ++#define S5PC100_VIC1VECTPRIORITY27 S5PC100_VIC1REG(0x26C) ++#define S5PC100_VIC1VECTPRIORITY28 S5PC100_VIC1REG(0x270) ++#define S5PC100_VIC1VECTPRIORITY29 S5PC100_VIC1REG(0x274) ++#define S5PC100_VIC1VECTPRIORITY30 S5PC100_VIC1REG(0x278) ++#define S5PC100_VIC1VECTPRIORITY31 S5PC100_VIC1REG(0x27C) ++#define S5PC100_VIC1ADDRESS S5PC100_VIC1REG(0xF00) ++#define S5PC100_VIC1PERIPHID0 S5PC100_VIC1REG(0xFE0) ++#define S5PC100_VIC1PERIPHID1 S5PC100_VIC1REG(0xFE4) ++#define S5PC100_VIC1PERIPHID2 S5PC100_VIC1REG(0xFE8) ++#define S5PC100_VIC1PCELLID0 S5PC100_VIC1REG(0xFF0) ++#define S5PC100_VIC1PCELLID1 S5PC100_VIC1REG(0xFF4) ++#define S5PC100_VIC1PCELLID2 S5PC100_VIC1REG(0xFF8) ++#define S5PC100_VIC1PCELLID3 S5PC100_VIC1REG(0xFFC) ++#define S5PC100_VIC2IRQSTATUS S5PC100_VIC2REG(0x000) ++#define S5PC100_VIC2FIQSTATUS S5PC100_VIC2REG(0x004) ++#define S5PC100_VIC2RAWINTR S5PC100_VIC2REG(0x008) ++#define S5PC100_VIC2INTSELECT S5PC100_VIC2REG(0x00C) ++#define S5PC100_VIC2INTENABLE S5PC100_VIC2REG(0x010) ++#define S5PC100_VIC2INTENCLEAR S5PC100_VIC2REG(0x014) ++#define S5PC100_VIC2SOFTINT S5PC100_VIC2REG(0x018) ++#define S5PC100_VIC2SOFTINTCLEAR S5PC100_VIC2REG(0x01C) ++#define S5PC100_VIC2PROTECTION S5PC100_VIC2REG(0x020) ++#define S5PC100_VIC2SWPRIORITYMASK S5PC100_VIC2REG(0x024) ++#define S5PC100_VIC2PRIORITYDAISY S5PC100_VIC2REG(0x028) ++#define S5PC100_VIC2VECTADDR0 S5PC100_VIC2REG(0x100) ++#define S5PC100_VIC2VECTADDR1 S5PC100_VIC2REG(0x104) ++#define S5PC100_VIC2VECTADDR2 S5PC100_VIC2REG(0x108) ++#define S5PC100_VIC2VECTADDR3 S5PC100_VIC2REG(0x10C) ++#define S5PC100_VIC2VECTADDR4 S5PC100_VIC2REG(0x110) ++#define S5PC100_VIC2VECTADDR5 S5PC100_VIC2REG(0x114) ++#define S5PC100_VIC2VECTADDR6 S5PC100_VIC2REG(0x118) ++#define S5PC100_VIC2VECTADDR7 S5PC100_VIC2REG(0x11C) ++#define S5PC100_VIC2VECTADDR8 S5PC100_VIC2REG(0x120) ++#define S5PC100_VIC2VECTADDR9 S5PC100_VIC2REG(0x124) ++#define S5PC100_VIC2VECTADDR10 S5PC100_VIC2REG(0x128) ++#define S5PC100_VIC2VECTADDR11 S5PC100_VIC2REG(0x12C) ++#define S5PC100_VIC2VECTADDR12 S5PC100_VIC2REG(0x130) ++#define S5PC100_VIC2VECTADDR13 S5PC100_VIC2REG(0x134) ++#define S5PC100_VIC2VECTADDR14 S5PC100_VIC2REG(0x138) ++#define S5PC100_VIC2VECTADDR15 S5PC100_VIC2REG(0x13C) ++#define S5PC100_VIC2VECTADDR16 S5PC100_VIC2REG(0x140) ++#define S5PC100_VIC2VECTADDR17 S5PC100_VIC2REG(0x144) ++#define S5PC100_VIC2VECTADDR18 S5PC100_VIC2REG(0x148) ++#define S5PC100_VIC2VECTADDR19 S5PC100_VIC2REG(0x14C) ++#define S5PC100_VIC2VECTADDR20 S5PC100_VIC2REG(0x150) ++#define S5PC100_VIC2VECTADDR21 S5PC100_VIC2REG(0x154) ++#define S5PC100_VIC2VECTADDR22 S5PC100_VIC2REG(0x158) ++#define S5PC100_VIC2VECTADDR23 S5PC100_VIC2REG(0x15C) ++#define S5PC100_VIC2VECTADDR24 S5PC100_VIC2REG(0x160) ++#define S5PC100_VIC2VECTADDR25 S5PC100_VIC2REG(0x164) ++#define S5PC100_VIC2VECTADDR26 S5PC100_VIC2REG(0x168) ++#define S5PC100_VIC2VECTADDR27 S5PC100_VIC2REG(0x16C) ++#define S5PC100_VIC2VECTADDR28 S5PC100_VIC2REG(0x170) ++#define S5PC100_VIC2VECTADDR29 S5PC100_VIC2REG(0x174) ++#define S5PC100_VIC2VECTADDR30 S5PC100_VIC2REG(0x178) ++#define S5PC100_VIC2VECTADDR31 S5PC100_VIC2REG(0x17C) ++#define S5PC100_VIC2VECPRIORITY0 S5PC100_VIC2REG(0x200) ++#define S5PC100_VIC2VECTPRIORITY1 S5PC100_VIC2REG(0x204) ++#define S5PC100_VIC2VECTPRIORITY2 S5PC100_VIC2REG(0x208) ++#define S5PC100_VIC2VECTPRIORITY3 S5PC100_VIC2REG(0x20C) ++#define S5PC100_VIC2VECTPRIORITY4 S5PC100_VIC2REG(0x210) ++#define S5PC100_VIC2VECTPRIORITY5 S5PC100_VIC2REG(0x214) ++#define S5PC100_VIC2VECTPRIORITY6 S5PC100_VIC2REG(0x218) ++#define S5PC100_VIC2VECTPRIORITY7 S5PC100_VIC2REG(0x21C) ++#define S5PC100_VIC2VECTPRIORITY8 S5PC100_VIC2REG(0x220) ++#define S5PC100_VIC2VECTPRIORITY9 S5PC100_VIC2REG(0x224) ++#define S5PC100_VIC2VECTPRIORITY10 S5PC100_VIC2REG(0x228) ++#define S5PC100_VIC2VECTPRIORITY11 S5PC100_VIC2REG(0x22C) ++#define S5PC100_VIC2VECTPRIORITY12 S5PC100_VIC2REG(0x230) ++#define S5PC100_VIC2VECTPRIORITY13 S5PC100_VIC2REG(0x234) ++#define S5PC100_VIC2VECTPRIORITY14 S5PC100_VIC2REG(0x238) ++#define S5PC100_VIC2VECTPRIORITY15 S5PC100_VIC2REG(0x23C) ++#define S5PC100_VIC2VECTPRIORITY16 S5PC100_VIC2REG(0x240) ++#define S5PC100_VIC2VECTPRIORITY17 S5PC100_VIC2REG(0x244) ++#define S5PC100_VIC2VECTPRIORITY18 S5PC100_VIC2REG(0x248) ++#define S5PC100_VIC2VECTPRIORITY19 S5PC100_VIC2REG(0x24C) ++#define S5PC100_VIC2VECTPRIORITY20 S5PC100_VIC2REG(0x250) ++#define S5PC100_VIC2VECTPRIORITY21 S5PC100_VIC2REG(0x254) ++#define S5PC100_VIC2VECTPRIORITY22 S5PC100_VIC2REG(0x258) ++#define S5PC100_VIC2VECTPRIORITY23 S5PC100_VIC2REG(0x25C) ++#define S5PC100_VIC2VECTPRIORITY24 S5PC100_VIC2REG(0x260) ++#define S5PC100_VIC2VECTPRIORITY25 S5PC100_VIC2REG(0x264) ++#define S5PC100_VIC2VECTPRIORITY26 S5PC100_VIC2REG(0x268) ++#define S5PC100_VIC2VECTPRIORITY27 S5PC100_VIC2REG(0x26C) ++#define S5PC100_VIC2VECTPRIORITY28 S5PC100_VIC2REG(0x270) ++#define S5PC100_VIC2VECTPRIORITY29 S5PC100_VIC2REG(0x274) ++#define S5PC100_VIC2VECTPRIORITY30 S5PC100_VIC2REG(0x278) ++#define S5PC100_VIC2VECTPRIORITY31 S5PC100_VIC2REG(0x27C) ++#define S5PC100_VIC2ADDRESS S5PC100_VIC2REG(0xF00) ++#define S5PC100_VIC2PERIPHID0 S5PC100_VIC2REG(0xFE0) ++#define S5PC100_VIC2PERIPHID1 S5PC100_VIC2REG(0xFE4) ++#define S5PC100_VIC2PERIPHID2 S5PC100_VIC2REG(0xFE8) ++#define S5PC100_VIC2PERIPHID3 S5PC100_VIC2REG(0xFEC) ++#define S5PC100_VIC2PCELLID0 S5PC100_VIC2REG(0xFF0) ++#define S5PC100_VIC2PCELLID1 S5PC100_VIC2REG(0xFF4) ++#define S5PC100_VIC2PCELLID2 S5PC100_VIC2REG(0xFF8) ++#define S5PC100_VIC2PCELLID3 S5PC100_VIC2REG(0xFFC) ++ ++#endif /* __ASM_ARCH_REGS_IRQ_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/include/mach/regs-mem.h linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/regs-mem.h +--- linux-2.6.28/arch/arm/mach-s5pc100/include/mach/regs-mem.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/regs-mem.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,86 @@ ++/* arch/arm/mach-s5pc100/include/mach/regs-mem.h ++ * ++ * Copyright (c) 2004 Simtec Electronics ++ * http://www.simtec.co.uk/products/SWLINUX/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S5PC100 Memory Control register definitions ++*/ ++ ++#ifndef __ASM_ARM_MEMREGS_H ++#define __ASM_ARM_MEMREGS_H ++ ++#ifndef S5PC1XX_MEMREG ++#define S5PC1XX_MEMREG(x) (S5PC1XX_VA_SROMC + (x)) ++#endif ++ ++ ++/* Bank Idle Cycle Control Registers 0-5 */ ++#define S5PC1XX_SROM_BW S5PC1XX_MEMREG(0x00) ++ ++#define S5PC1XX_SROM_BC0 S5PC1XX_MEMREG(0x04) ++#define S5PC1XX_SROM_BC1 S5PC1XX_MEMREG(0x08) ++#define S5PC1XX_SROM_BC2 S5PC1XX_MEMREG(0x0C) ++#define S5PC1XX_SROM_BC3 S5PC1XX_MEMREG(0x10) ++#define S5PC1XX_SROM_BC4 S5PC1XX_MEMREG(0x14) ++#define S5PC1XX_SROM_BC5 S5PC1XX_MEMREG(0x18) ++ ++/* SROM BW */ ++#define S5PC1XX_SROM_BW_DATA_WIDTH0_8BIT (0 << 0) ++#define S5PC1XX_SROM_BW_DATA_WIDTH0_16BIT (1 << 0) ++#define S5PC1XX_SROM_BW_DATA_WIDTH0_MASK (1 << 0) ++ ++#define S5PC1XX_SROM_BW_WAIT_ENABLE0_DISABLE (0 << 2) ++#define S5PC1XX_SROM_BW_WAIT_ENABLE0_ENABLE (1 << 2) ++#define S5PC1XX_SROM_BW_WAIT_ENABLE0_MASK (1 << 2) ++ ++#define S5PC1XX_SROM_BW_BYTE_ENABLE0_DISABLE (0 << 3) ++#define S5PC1XX_SROM_BW_BYTE_ENABLE0_ENABLE (1 << 3) ++#define S5PC1XX_SROM_BW_BYTE_ENABLE0_MASK (1 << 3) ++ ++#define S5PC1XX_SROM_BW_DATA_WIDTH1_8BIT (0 << 4) ++#define S5PC1XX_SROM_BW_DATA_WIDTH1_16BIT (1 << 4) ++#define S5PC1XX_SROM_BW_DATA_WIDTH1_MASK (1 << 4) ++ ++#define S5PC1XX_SROM_BW_WAIT_ENABLE1_DISABLE (0 << 6) ++#define S5PC1XX_SROM_BW_WAIT_ENABLE1_ENABLE (1 << 6) ++#define S5PC1XX_SROM_BW_WAIT_ENABLE1_MASK (1 << 6) ++ ++#define S5PC1XX_SROM_BW_BYTE_ENABLE1_DISABLE (0 << 7) ++#define S5PC1XX_SROM_BW_BYTE_ENABLE1_ENABLE (1 << 7) ++#define S5PC1XX_SROM_BW_BYTE_ENABLE1_MASK (1 << 7) ++ ++#define S5PC1XX_SROM_BW_DATA_WIDTH2_8BIT (0 << 8) ++#define S5PC1XX_SROM_BW_DATA_WIDTH2_16BIT (1 << 8) ++#define S5PC1XX_SROM_BW_DATA_WIDTH2_MASK (1 << 8) ++ ++#define S5PC1XX_SROM_BW_DATA_WIDTH3_8BIT (0 << 12) ++#define S5PC1XX_SROM_BW_DATA_WIDTH3_16BIT (1 << 12) ++#define S5PC1XX_SROM_BW_DATA_WIDTH3_MASK (1 << 12) ++ ++#define S5PC1XX_SROM_BW_ADDR_MODE3_HWORD_ADDR (0 << 13) ++#define S5PC1XX_SROM_BW_ADDR_MODE3_BYTE_ADDR (1 << 13) ++#define S5PC1XX_SROM_BW_ADDR_MODE3_MASK (1 << 13) ++ ++#define S5PC1XX_SROM_BW_WAIT_ENABLE3_DISABLE (0 << 14) ++#define S5PC1XX_SROM_BW_WAIT_ENABLE3_ENABLE (1 << 14) ++#define S5PC1XX_SROM_BW_WAIT_ENABLE3_MASK (1 << 14) ++ ++#define S5PC1XX_SROM_BW_BYTE_ENABLE3_DISABLE (0 << 15) ++#define S5PC1XX_SROM_BW_BYTE_ENABLE3_ENABLE (1 << 15) ++#define S5PC1XX_SROM_BW_BYTE_ENABLE3_MASK (1 << 15) ++ ++/* SROM BCn */ ++#define S5PC1XX_SROM_BCn_TACS(x) (x << 28) ++#define S5PC1XX_SROM_BCn_TCOS(x) (x << 24) ++#define S5PC1XX_SROM_BCn_TACC(x) (x << 16) ++#define S5PC1XX_SROM_BCn_TCOH(x) (x << 12) ++#define S5PC1XX_SROM_BCn_TCAH(x) (x << 8) ++#define S5PC1XX_SROM_BCn_TACP(x) (x << 4) ++#define S5PC1XX_SROM_BCn_PMC_NORMAL (0 << 0) ++#define S5PC1XX_SROM_BCn_PMC_4 (1 << 0) ++ ++#endif /* __ASM_ARM_MEMREGS_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/include/mach/system.h linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/system.h +--- linux-2.6.28/arch/arm/mach-s5pc100/include/mach/system.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/system.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,36 @@ ++/* linux/arch/arm/mach-s5pc100/include/mach/system.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5PC100 - system implementation ++ */ ++ ++ #include ++ ++#ifndef __ASM_ARCH_SYSTEM_H ++#define __ASM_ARCH_SYSTEM_H __FILE__ ++ ++void (*s5pc1xx_idle)(void); ++ ++void s5pc1xx_default_idle(void) ++{ ++ printk("default idle function\n"); ++} ++ ++static void arch_idle(void) ++{ ++ if(s5pc1xx_idle != NULL) ++ (s5pc1xx_idle)(); ++ else ++ s5pc1xx_default_idle(); ++} ++ ++static void arch_reset(char mode) ++{ ++ /* nothing here yet */ ++} ++ ++#endif /* __ASM_ARCH_IRQ_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/include/mach/tick.h linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/tick.h +--- linux-2.6.28/arch/arm/mach-s5pc100/include/mach/tick.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/tick.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,29 @@ ++/* linux/arch/arm/mach-s5pc100/include/mach/tick.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S5PC1XX - Timer tick support definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_TICK_H ++#define __ASM_ARCH_TICK_H __FILE__ ++ ++/* note, the timer interrutps turn up in 2 places, the vic and then ++ * the timer block. We take the VIC as the base at the moment. ++ */ ++static inline u32 s5pc1xx_ostimer_pending(void) ++{ ++ u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS); ++ return pend & 1 << (IRQ_SYSTIMER - S5PC1XX_IRQ_VIC0(0)); ++} ++ ++#define TICK_MAX (0xffffffff) ++ ++#endif /* __ASM_ARCH_6400_TICK_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/include/mach/uncompress.h linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/uncompress.h +--- linux-2.6.28/arch/arm/mach-s5pc100/include/mach/uncompress.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/uncompress.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,26 @@ ++/* arch/arm/mach-s5pc100/include/mach/uncompress.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S5PC100 - uncompress code ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_UNCOMPRESS_H ++#define __ASM_ARCH_UNCOMPRESS_H ++ ++#include ++#include ++ ++static void arch_detect_cpu(void) ++{ ++ /* we do not need to do any cpu detection here at the moment. */ ++} ++ ++#endif /* __ASM_ARCH_UNCOMPRESS_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/include/mach/usb-control.h linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/usb-control.h +--- linux-2.6.28/arch/arm/mach-s5pc100/include/mach/usb-control.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/include/mach/usb-control.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,41 @@ ++/* arch/arm/mach-s3c2410/include/mach/usb-control.h ++ * ++ * Copyright (c) 2004 Simtec Electronics ++ * Ben Dooks ++ * ++ * S3C2410 - usb port information ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_USBCONTROL_H ++#define __ASM_ARCH_USBCONTROL_H "arch/arm/mach-s5pc100/include/mach/usb-control.h" ++ ++#define S3C_HCDFLG_USED (1) ++ ++struct s3c2410_hcd_port { ++ unsigned char flags; ++ unsigned char power; ++ unsigned char oc_status; ++ unsigned char oc_changed; ++}; ++ ++struct s3c2410_hcd_info { ++ struct usb_hcd *hcd; ++ struct s3c2410_hcd_port port[2]; ++ ++ void (*power_control)(int port, int to); ++ void (*enable_oc)(struct s3c2410_hcd_info *, int on); ++ void (*report_oc)(struct s3c2410_hcd_info *, int ports); ++}; ++ ++static void inline s3c2410_usb_report_oc(struct s3c2410_hcd_info *info, int ports) ++{ ++ if (info->report_oc != NULL) { ++ (info->report_oc)(info, ports); ++ } ++} ++ ++#endif /*__ASM_ARCH_USBCONTROL_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/leds-s5pc100.c linux-2.6.28.6/arch/arm/mach-s5pc100/leds-s5pc100.c +--- linux-2.6.28/arch/arm/mach-s5pc100/leds-s5pc100.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/leds-s5pc100.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,120 @@ ++/* ++ * linux/arch/arm/mach-s5pc100/leds-s5pc100.c ++ * ++ * Copyright 2008 by Samsung Electronics Incorporated ++ * ++ * There are 16 LEDs on the debug board (all green); four may be used ++ * for logical 'green', 'amber', 'red', and 'blue' (after "claiming"). ++ * ++ * The "surfer" expansion board and H2 sample board also have two-color ++ * green+red LEDs (in parallel), used here for timer and idle indicators. ++ */ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "leds.h" ++ ++#define LED0 S5PC1XX_GPH1(4) ++#define LED1 S5PC1XX_GPH1(5) ++#define LED2 S5PC1XX_GPH1(6) ++#define LED3 S5PC1XX_GPH1(7) ++ ++#define LED_STATE_ENABLED 1<<0 ++#define LED_STATE_CLAIMED 1<<1 ++#define LED_TIMER_ON 1<<2 ++#define LED_IDLE 1<<3 ++ ++ ++void s5pc100_leds_event(led_event_t evt) ++{ ++ unsigned long flags; ++ ++ static u16 led_state, hw_led_state; ++ ++ local_irq_save(flags); ++ ++ if (!(led_state & LED_STATE_ENABLED) && evt != led_start) ++ goto done; ++ ++ switch (evt) { ++ case led_start: ++ led_state |= LED_STATE_ENABLED; ++ break; ++ ++ case led_stop: ++ case led_halted: ++ /* all leds off during suspend or shutdown */ ++ led_state &= ~LED_STATE_ENABLED; ++ break; ++ ++ case led_claim: ++ led_state |= LED_STATE_CLAIMED; ++ hw_led_state = 0; ++ break; ++ ++ case led_release: ++ led_state &= ~LED_STATE_CLAIMED; ++ break; ++ ++#ifdef CONFIG_LEDS_TIMER ++ case led_timer: ++ led_state ^= LED_TIMER_ON; ++ ++ if (led_state & LED_TIMER_ON) ++ gpio_set_value(LED0, 1); ++ else { ++ gpio_set_value(LED0, 0); ++ } ++ ++ break; ++#endif ++ ++#ifdef CONFIG_LEDS_CPU ++ case led_idle_start: ++ gpio_set_value(LED1, 1); ++ break; ++ ++ case led_idle_end: ++ gpio_set_value(LED1, 0); ++ break; ++#endif ++ ++ case led_green_on: ++ break; ++ case led_green_off: ++ break; ++ ++ case led_amber_on: ++ break; ++ case led_amber_off: ++ break; ++ ++ case led_red_on: ++ break; ++ case led_red_off: ++ break; ++ ++ case led_blue_on: ++ break; ++ case led_blue_off: ++ break; ++ ++ default: ++ break; ++ } ++ ++done: ++ local_irq_restore(flags); ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/leds.c linux-2.6.28.6/arch/arm/mach-s5pc100/leds.c +--- linux-2.6.28/arch/arm/mach-s5pc100/leds.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/leds.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,91 @@ ++/* ++ * linux/arch/arm/mach-s5pc100/leds.c ++ * ++ * S5PC100 LEDs dispatcher ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include "leds.h" ++ ++static irqreturn_t eint11_switch(int irq, void *dev_id) ++{ ++ ++ printk("EINT11 interrupt occures!!!\n"); ++ return IRQ_HANDLED; ++} ++ ++ ++static int __init ++s5pc100_leds_init(void) ++{ ++ if (machine_is_smdkc100()) ++ leds_event = s5pc100_leds_event; ++ else ++ return -1; ++ ++ if (machine_is_smdkc100()) ++ { ++ gpio_request(S5PC1XX_GPH1(4), "GPH1"); ++ gpio_direction_output(S5PC1XX_GPH1(4), 1); ++ if(gpio_get_value(S5PC1XX_GPH1(4)) == 0) ++ { ++ printk(KERN_WARNING "LED: can't set GPH1(4) to output mode\n"); ++ } ++ ++ gpio_request(S5PC1XX_GPH1(5), "GPH1"); ++ gpio_direction_output(S5PC1XX_GPH1(5), 1); ++ if(gpio_get_value(S5PC1XX_GPH1(5)) == 0) ++ { ++ printk(KERN_WARNING "LED: can't set GPH1(5) to output mode\n"); ++ } ++ ++ gpio_request(S5PC1XX_GPH1(6), "GPH1"); ++ gpio_direction_output(S5PC1XX_GPH1(6), 1); ++ if(gpio_get_value(S5PC1XX_GPH1(6)) == 0) ++ { ++ printk(KERN_WARNING "LED: can't set GPH1(6) to output mode\n"); ++ } ++ ++ gpio_request(S5PC1XX_GPH1(7), "GPH1"); ++ gpio_direction_output(S5PC1XX_GPH1(7), 1); ++ if(gpio_get_value(S5PC1XX_GPH1(7)) == 0) ++ { ++ printk(KERN_WARNING "LED: can't set GPH1(7) to output mode\n"); ++ } ++ } ++ ++ /* Get irqs */ ++ set_irq_type(IRQ_EINT11, IRQ_TYPE_EDGE_FALLING); ++ s3c_gpio_setpull(S5PC1XX_GPH1(3), S3C_GPIO_PULL_NONE); ++ if (request_irq(IRQ_EINT11, eint11_switch, IRQF_DISABLED, "EINT11", NULL)) { ++ return -EIO; ++ } ++ ++ leds_event(led_start); ++ return 0; ++} ++ ++__initcall(s5pc100_leds_init); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/leds.h linux-2.6.28.6/arch/arm/mach-s5pc100/leds.h +--- linux-2.6.28/arch/arm/mach-s5pc100/leds.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/leds.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1 @@ ++extern void s5pc100_leds_event(led_event_t evt); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/mach-smdkc100.c linux-2.6.28.6/arch/arm/mach-s5pc100/mach-smdkc100.c +--- linux-2.6.28/arch/arm/mach-s5pc100/mach-smdkc100.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/mach-smdkc100.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,473 @@ ++/* linux/arch/arm/mach-s5pc100/mach-smdkc100.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_USB_SUPPORT ++#include ++#include ++#include ++ ++/* S3C_USB_CLKSRC 0: EPLL 1: CLK_48M */ ++#define S3C_USB_CLKSRC 1 ++#define OTGH_PHY_CLK_VALUE (0x22) /* UTMI Interface, otg_phy input clk 12Mhz Oscillator */ ++#endif ++ ++#if defined(CONFIG_PM) ++#include ++#endif ++ ++#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK ++#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB ++#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE ++ ++extern struct sys_timer s5pc1xx_timer; ++extern void s5pc1xx_reserve_bootmem(void); ++ ++static struct s3c24xx_uart_clksrc smdkc100_serial_clocks[] = { ++#if defined(CONFIG_SERIAL_S5PC1XX_HSUART) ++/* HS-UART Clock using SCLK */ ++ [0] = { ++ .name = "uclk1", ++ .divisor = 1, ++ .min_baud = 0, ++ .max_baud = 0, ++ }, ++#else ++ [0] = { ++ .name = "pclk", ++ .divisor = 1, ++ .min_baud = 0, ++ .max_baud = 0, ++ }, ++#endif ++}; ++ ++static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = { ++ [0] = { ++ .hwport = 0, ++ .flags = 0, ++ .ucon = S3C64XX_UCON_DEFAULT, ++ .ulcon = S3C64XX_ULCON_DEFAULT, ++ .ufcon = S3C64XX_UFCON_DEFAULT, ++ .clocks = smdkc100_serial_clocks, ++ .clocks_size = ARRAY_SIZE(smdkc100_serial_clocks), ++ }, ++ [1] = { ++ .hwport = 1, ++ .flags = 0, ++ .ucon = S3C64XX_UCON_DEFAULT, ++ .ulcon = S3C64XX_ULCON_DEFAULT, ++ .ufcon = S3C64XX_UFCON_DEFAULT, ++ .clocks = smdkc100_serial_clocks, ++ .clocks_size = ARRAY_SIZE(smdkc100_serial_clocks), ++ }, ++ [2] = { ++ .hwport = 2, ++ .flags = 0, ++ .ucon = S3C64XX_UCON_DEFAULT, ++ .ulcon = S3C64XX_ULCON_DEFAULT, ++ .ufcon = S3C64XX_UFCON_DEFAULT, ++ .clocks = smdkc100_serial_clocks, ++ .clocks_size = ARRAY_SIZE(smdkc100_serial_clocks), ++ }, ++ [3] = { ++ .hwport = 3, ++ .flags = 0, ++ .ucon = S3C64XX_UCON_DEFAULT, ++ .ulcon = S3C64XX_ULCON_DEFAULT, ++ .ufcon = S3C64XX_UFCON_DEFAULT, ++ .clocks = smdkc100_serial_clocks, ++ .clocks_size = ARRAY_SIZE(smdkc100_serial_clocks), ++ }, ++}; ++ ++struct map_desc smdkc100_iodesc[] = {}; ++ ++static struct platform_device *smdkc100_devices[] __initdata = { ++ &s3c_device_lcd, ++ &s3c_device_nand, ++ &s3c_device_onenand, ++ &s3c_device_keypad, ++ &s3c_device_ts, ++ &s3c_device_adc, ++ &s3c_device_rtc, ++ &s3c_device_smc911x, ++ &s3c_device_i2c0, ++ &s3c_device_i2c1, ++ &s3c_device_usb, ++ &s3c_device_usbgadget, ++ &s3c_device_usb_otghcd, ++ &s3c_device_hsmmc0, ++ &s3c_device_hsmmc1, ++ &s3c_device_spi0, ++ &s3c_device_spi1, ++ &s3c_device_mfc, ++ &s3c_device_jpeg, ++ &s3c_device_fimc0, ++ &s3c_device_fimc1, ++ &s3c_device_fimc2, ++ &s3c_device_ac97, ++ &s3c_device_wdt, ++ &s3c_device_g3d, ++ &s3c_device_g2d, ++ &s3c_device_rotator, ++ &s3c_device_csis, ++#if defined(CONFIG_TIMER_PWM) ++ &s3c_device_timer[0], ++ &s3c_device_timer[1], ++#endif ++}; ++ ++ ++static struct s3c_ts_mach_info s3c_ts_platform __initdata = { ++ .delay = 10000, ++ .presc = 49, ++ .oversampling_shift = 2, ++ .resol_bit = 12, ++ .s3c_adc_con = ADC_TYPE_2, ++}; ++ ++static struct s3c_adc_mach_info s3c_adc_platform __initdata = { ++ /* s5pc100 supports 12-bit resolution */ ++ .delay = 10000, ++ .presc = 49, ++ .resolution = 12, ++}; ++ ++static struct i2c_board_info i2c_devs0[] __initdata = { ++ { I2C_BOARD_INFO("24c08", 0x50), }, ++}; ++ ++static struct i2c_board_info i2c_devs1[] __initdata = { ++ { I2C_BOARD_INFO("24c128", 0x57), }, ++}; ++ ++#if defined(CONFIG_TIMER_PWM) ++static struct platform_pwm_backlight_data smdk_backlight_data = { ++ .pwm_id = 0, ++ .max_brightness = 255, ++ .dft_brightness = 255, ++ .pwm_period_ns = 78770, ++}; ++ ++static struct platform_device smdk_backlight_device = { ++ .name = "pwm-backlight", ++ .dev = { ++ .parent = &s3c_device_timer[0].dev, ++ .platform_data = &smdk_backlight_data, ++ }, ++}; ++ ++static void __init smdk_backlight_register(void) ++{ ++ int ret = platform_device_register(&smdk_backlight_device); ++ if (ret) ++ printk(KERN_ERR "smdk: failed to register backlight device: %d\n", ret); ++} ++#else ++#define smdk_backlight_register() do { } while (0) ++#endif ++ ++static void __init smdkc100_map_io(void) ++{ ++ s3c_device_nand.name = "s5pc100-nand"; ++ s5pc1xx_init_io(smdkc100_iodesc, ARRAY_SIZE(smdkc100_iodesc)); ++ s3c24xx_init_clocks(0); ++ s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs)); ++ s5pc1xx_reserve_bootmem(); ++} ++ ++static void __init smdkc100_smc911x_set(void) ++{ ++ unsigned int tmp; ++ ++ tmp = __raw_readl(S5PC1XX_GPK0CON); ++ tmp &=~S5PC1XX_GPK0_3_MASK; ++ tmp |=(S5PC1XX_GPK0_3_SROM_CSn3); ++ __raw_writel(tmp, S5PC1XX_GPK0CON); ++ ++ tmp = __raw_readl(S5PC1XX_SROM_BW); ++ tmp &= ~(S5PC1XX_SROM_BW_BYTE_ENABLE3_MASK | S5PC1XX_SROM_BW_WAIT_ENABLE3_MASK | ++ S5PC1XX_SROM_BW_ADDR_MODE3_MASK | S5PC1XX_SROM_BW_DATA_WIDTH3_MASK); ++ tmp |= S5PC1XX_SROM_BW_DATA_WIDTH3_16BIT; ++ ++ __raw_writel(tmp, S5PC1XX_SROM_BW); ++ ++ __raw_writel((0x0<<28)|(0x4<<24)|(0xd<<16)|(0x1<<12)|(0x4<<8)|(0x6<<4)|(0x0<<0), S5PC1XX_SROM_BC3); ++ ++ __raw_writel(S5PC1XX_SROM_BCn_TACS(1) | S5PC1XX_SROM_BCn_TCOS(0) | ++ S5PC1XX_SROM_BCn_TACC(27) | S5PC1XX_SROM_BCn_TCOH(0) | ++ S5PC1XX_SROM_BCn_TCAH(2) | S5PC1XX_SROM_BCn_TACP(0) | ++ S5PC1XX_SROM_BCn_PMC_NORMAL, S5PC1XX_SROM_BC3); ++} ++ ++static void __init smdkc100_machine_init(void) ++{ ++ s3c_device_nand.dev.platform_data = &s3c_nand_mtd_part_info; ++ s3c_device_onenand.dev.platform_data = &s3c_onenand_data; ++ ++ smdkc100_smc911x_set(); ++ ++ s3c_ts_set_platdata(&s3c_ts_platform); ++ s3c_adc_set_platdata(&s3c_adc_platform); ++ ++ /* i2c */ ++ s3c_i2c0_set_platdata(NULL); ++ s3c_i2c1_set_platdata(NULL); ++ i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0)); ++ i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); ++ ++ /* fimc */ ++ s3c_fimc0_set_platdata(NULL); ++ s3c_fimc1_set_platdata(NULL); ++ s3c_fimc2_set_platdata(NULL); ++ ++ /* mipi-csi2 */ ++ s3c_csis_set_platdata(NULL); ++ ++#ifdef CONFIG_VIDEO_FIMC ++ s3c_fimc_reset_camera(); ++#endif ++ ++ /* Setting up the HS-MMC clock for 133MHz using doutMpll */ ++ writel((readl(S5P_CLK_DIV3) & ~(0xfff << 0)), S5P_CLK_DIV3); ++ ++ platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices)); ++ ++#if defined(CONFIG_PM) ++ s5pc1xx_pm_init(); ++#endif ++ smdk_backlight_register(); ++} ++ ++MACHINE_START(SMDKC100, "SMDKC100") ++ /* Maintainer: Ben Dooks */ ++ .phys_io = S3C_PA_UART & 0xfff00000, ++ .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, ++ .boot_params = S5PC1XX_PA_SDRAM + 0x100, ++ ++ .init_irq = s5pc100_init_irq, ++ .map_io = smdkc100_map_io, ++ .init_machine = smdkc100_machine_init, ++ .timer = &s5pc1xx_timer, ++MACHINE_END ++ ++ ++#ifdef CONFIG_USB_SUPPORT ++/* Initializes OTG Phy. */ ++void otg_phy_init(void) { ++ writel(readl(S5P_OTHERS)|S5P_OTHERS_USB_SIG_MASK, S5P_OTHERS); ++ writel(0x0, S3C_USBOTG_PHYPWR); /* Power up */ ++ writel(OTGH_PHY_CLK_VALUE, S3C_USBOTG_PHYCLK); ++ writel(0x7, S3C_USBOTG_RSTCON); ++ ++ udelay(50); ++ writel(0x0, S3C_USBOTG_RSTCON); ++ udelay(50); ++} ++EXPORT_SYMBOL(otg_phy_init); ++ ++/* USB Control request data struct must be located here for DMA transfer */ ++struct usb_ctrlrequest usb_ctrl __attribute__((aligned(8))); ++EXPORT_SYMBOL(usb_ctrl); ++ ++/* OTG PHY Power Off */ ++void otg_phy_off(void) { ++ writel(readl(S3C_USBOTG_PHYCLK) | (0X1 << 4), S3C_USBOTG_PHYCLK); ++ writel(readl(S5P_OTHERS)&~S5P_OTHERS_USB_SIG_MASK, S5P_OTHERS); ++} ++EXPORT_SYMBOL(otg_phy_off); ++ ++void usb_host_clk_en(void) { ++ struct clk *otg_clk; ++ ++ switch (S3C_USB_CLKSRC) { ++ case 0: /* epll clk */ ++ /* Setting the epll clk to 48 MHz, P=3, M=96, S=3 */ ++ writel((readl(S5P_EPLL_CON) & ~(S5P_EPLL_MASK)) | (S5P_EPLL_EN \ ++ | S5P_EPLLVAL(96,3,3)), S5P_EPLL_CON); ++ writel((readl(S5P_CLK_SRC0) | S5P_CLKSRC0_EPLL_MASK), S5P_CLK_SRC0); ++ writel((readl(S5P_CLK_SRC1)& ~S5P_CLKSRC1_UHOST_MASK), S5P_CLK_SRC1); ++ ++ /* USB host clock divider ratio is 1 */ ++ writel((readl(S5P_CLK_DIV2)& ~S5P_CLKDIV2_UHOST_MASK), S5P_CLK_DIV2); ++ break; ++ ++ case 1: /* oscillator 12M clk */ ++ otg_clk = clk_get(NULL, "otg"); ++ clk_enable(otg_clk); ++ otg_phy_init(); ++ writel((readl(S5P_CLK_SRC1) | S5P_CLKSRC1_CLK48M_MASK) \ ++ | S5P_CLKSRC1_UHOST_MASK, S5P_CLK_SRC1); ++ ++ //USB host colock divider ratio is 1 ++ writel(readl(S5P_CLK_DIV2)& ~S5P_CLKDIV2_UHOST_MASK, S5P_CLK_DIV2); ++ break; ++ /* Add other clock sources here */ ++ ++ default: ++ printk(KERN_INFO "Unknown USB Host Clock Source\n"); ++ BUG(); ++ break; ++ } ++ ++ writel(readl(S5P_CLKGATE_D10)|S5P_CLKGATE_D10_USBHOST, S5P_CLKGATE_D10); ++ writel(readl(S5P_SCLKGATE0)|S5P_CLKGATE_SCLK0_USBHOST, S5P_SCLKGATE0); ++ ++} ++ ++EXPORT_SYMBOL(usb_host_clk_en); ++#endif ++ ++#if defined(CONFIG_RTC_DRV_S3C) ++/* RTC common Function for samsung APs*/ ++unsigned int s3c_rtc_set_bit_byte(void __iomem *base, uint offset, uint val) ++{ ++ writeb(val, base + offset); ++ ++ return 0; ++} ++ ++unsigned int s3c_rtc_read_alarm_status(void __iomem *base) ++{ ++ return 1; ++} ++ ++void s3c_rtc_set_pie(void __iomem *base, uint to) ++{ ++ unsigned int tmp; ++ ++ tmp = readw(base + S3C2410_RTCCON) & ~S3C_RTCCON_TICEN; ++ ++ if (to) ++ tmp |= S3C_RTCCON_TICEN; ++ ++ writew(tmp, base + S3C2410_RTCCON); ++} ++ ++void s3c_rtc_set_freq_regs(void __iomem *base, uint freq, uint s3c_freq) ++{ ++ unsigned int tmp; ++ ++ tmp = readw(base + S3C2410_RTCCON) & (S3C_RTCCON_TICEN | S3C2410_RTCCON_RTCEN ); ++ writew(tmp, base + S3C2410_RTCCON); ++ s3c_freq = freq; ++ tmp = (32768 / freq)-1; ++ writel(tmp, base + S3C2410_TICNT); ++} ++ ++void s3c_rtc_enable_set(struct platform_device *pdev,void __iomem *base, int en) ++{ ++ unsigned int tmp; ++ ++ if (!en) { ++ tmp = readw(base + S3C2410_RTCCON); ++ writew(tmp & ~ (S3C2410_RTCCON_RTCEN | S3C_RTCCON_TICEN), base + S3C2410_RTCCON); ++ } else { ++ /* re-enable the device, and check it is ok */ ++ if ((readw(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0){ ++ dev_info(&pdev->dev, "rtc disabled, re-enabling\n"); ++ ++ tmp = readw(base + S3C2410_RTCCON); ++ writew(tmp|S3C2410_RTCCON_RTCEN, base+S3C2410_RTCCON); ++ } ++ ++ if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)){ ++ dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n"); ++ ++ tmp = readw(base + S3C2410_RTCCON); ++ writew(tmp& ~S3C2410_RTCCON_CNTSEL, base+S3C2410_RTCCON); ++ } ++ ++ if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)){ ++ dev_info(&pdev->dev, "removing RTCCON_CLKRST\n"); ++ ++ tmp = readw(base + S3C2410_RTCCON); ++ writew(tmp & ~S3C2410_RTCCON_CLKRST, base+S3C2410_RTCCON); ++ } ++ } ++} ++#endif ++ ++#if defined(CONFIG_KEYPAD_S3C) || defined (CONFIG_KEYPAD_S3C_MODULE) ++void s3c_setup_keypad_cfg_gpio(int rows, int columns) ++{ ++ unsigned int gpio; ++ unsigned int end; ++ ++ end = S5PC1XX_GPH3(rows); ++ ++ /* Set all the necessary GPH2 pins to special-function 0 */ ++ for (gpio = S5PC1XX_GPH3(0); gpio < end; gpio++) { ++ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); ++ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); ++ } ++ ++ end = S5PC1XX_GPH2(columns); ++ ++ /* Set all the necessary GPK pins to special-function 0 */ ++ for (gpio = S5PC1XX_GPH2(0); gpio < end; gpio++) { ++ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); ++ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); ++ } ++} ++ ++EXPORT_SYMBOL(s3c_setup_keypad_cfg_gpio); ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/pm.c linux-2.6.28.6/arch/arm/mach-s5pc100/pm.c +--- linux-2.6.28/arch/arm/mach-s5pc100/pm.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/pm.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,107 @@ ++/* linux/arch/arm/mach-s5pc100/pm.c ++ * ++ * Copyright (c) 2006 Samsung Electronics ++ * ++ * ++ * S3C6410 (and compatible) Power Manager (Suspend-To-RAM) support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++#define DBG(fmt...) printk(KERN_DEBUG fmt) ++ ++void s5pc100_cpu_suspend(void) ++{ ++ unsigned long tmp; ++ ++ /* issue the standby signal into the pm unit. Note, we ++ * issue a write-buffer drain just in case */ ++ ++ tmp = 0; ++/* ++ * MCR p15,0,,c7,c10,5 ; Data Memory Barrier Operation. ++ * MCR p15,0,,c7,c10,4 ; Data Synchronization Barrier operation. ++ * MCR p15,0,,c7,c0,4 ; Wait For Interrupt. ++ */ ++ ++ asm("b 1f\n\t" ++ ".align 5\n\t" ++ "1:\n\t" ++ "mcr p15, 0, %0, c7, c10, 5\n\t" ++ "mcr p15, 0, %0, c7, c10, 4\n\t" ++ ".word 0xe320f003" :: "r" (tmp)); ++ ++ /* we should never get past here */ ++ ++ panic("sleep resumed to originator?"); ++} ++ ++static void s5pc100_pm_prepare(void) ++{ ++ ++} ++ ++static int s5pc100_pm_add(struct sys_device *sysdev) ++{ ++ pm_cpu_prep = s5pc100_pm_prepare; ++ pm_cpu_sleep = s5pc100_cpu_suspend; ++ ++ return 0; ++} ++ ++static struct sleep_save s5pc100_sleep[] = { ++ ++}; ++ ++static int s5pc100_pm_suspend(struct sys_device *dev, pm_message_t state) ++{ ++ s5pc1xx_pm_do_save(s5pc100_sleep, ARRAY_SIZE(s5pc100_sleep)); ++ return 0; ++} ++ ++static int s5pc100_pm_resume(struct sys_device *dev) ++{ ++ s5pc1xx_pm_do_restore(s5pc100_sleep, ARRAY_SIZE(s5pc100_sleep)); ++ return 0; ++} ++ ++static struct sysdev_driver s5pc100_pm_driver = { ++ .add = s5pc100_pm_add, ++ .resume = s5pc100_pm_resume, ++}; ++ ++static __init int s5pc100_pm_drvinit(void) ++{ ++ return sysdev_driver_register(&s5pc100_sysclass, &s5pc100_pm_driver); ++} ++ ++arch_initcall(s5pc100_pm_drvinit); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mach-s5pc100/setup-sdhci.c linux-2.6.28.6/arch/arm/mach-s5pc100/setup-sdhci.c +--- linux-2.6.28/arch/arm/mach-s5pc100/setup-sdhci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mach-s5pc100/setup-sdhci.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,118 @@ ++/* linux/arch/arm/mach-s3c6410/setup-sdhci.c ++ * ++ * Copyright 2008 Simtec Electronics ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC) ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ ++char *s3c6410_hsmmc_clksrcs[4] = { ++ [0] = "mmc_bus", ++ [1] = "mmc_bus", ++ [2] = "hsmmc", ++}; ++ ++void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) ++{ ++ unsigned int gpio; ++ unsigned int end; ++ ++ /* Channel 0 supports 1,4 and 8-bit bus width */ ++ end = S5PC1XX_GPG0(2 + width); ++ ++ /* Set all the necessary GPG0 ins to special-function 2 */ ++ for (gpio = S5PC1XX_GPG0(0); gpio < end; gpio++) { ++ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); ++ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); ++ } ++ ++ /* GPG1 chip Detect */ ++ s3c_gpio_setpull(S5PC1XX_GPG1(2), S3C_GPIO_PULL_UP); ++ s3c_gpio_cfgpin(S5PC1XX_GPG1(2), S3C_GPIO_SFN(2)); ++} ++ ++void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev, ++ void __iomem *r, ++ struct mmc_ios *ios, ++ struct mmc_card *card) ++{ ++ u32 ctrl2, ctrl3 = 0; ++ ++ /* don't need to alter anything acording to card-type */ ++ ++ writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4); ++ ++ /* No need for any delay values in the HS-MMC interface */ ++ ctrl2 = readl(r + S3C_SDHCI_CONTROL2); ++ ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; ++ ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | ++ S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | ++ S3C_SDHCI_CTRL2_DFCNT_NONE | ++ S3C_SDHCI_CTRL2_ENCLKOUTHOLD); ++ ++ writel(ctrl2, r + S3C_SDHCI_CONTROL2); ++ writel(ctrl3, r + S3C_SDHCI_CONTROL3); ++} ++ ++void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) ++{ ++ unsigned int gpio; ++ unsigned int end; ++ ++ /* Channel 1 supports 1 and 4-bit bus width */ ++ end = S5PC1XX_GPG2(2 + width); ++ ++ /* Set all the necessary GPG2 pins to special-function 2 */ ++ for (gpio = S5PC1XX_GPG2(0); gpio < end; gpio++) { ++ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); ++ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); ++ } ++ ++ /* GPG2 chip Detect */ ++ s3c_gpio_setpull(S5PC1XX_GPG2(6), S3C_GPIO_PULL_UP); ++ s3c_gpio_cfgpin(S5PC1XX_GPG2(6), S3C_GPIO_SFN(2)); ++} ++ ++void s3c6410_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) ++{ ++ unsigned int gpio; ++ unsigned int end; ++ ++ /* Channel 1 supports 1 and 4-bit bus width */ ++ end = S5PC1XX_GPG3(2 + width); ++ ++ /* Set all the necessary GPG3 pins to special-function 2 */ ++ for (gpio = S5PC1XX_GPG3(0); gpio < end; gpio++) { ++ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); ++ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); ++ } ++ ++ /* GPG3 chip Detect */ ++ s3c_gpio_setpull(S5PC1XX_GPG3(6), S3C_GPIO_PULL_UP); ++ s3c_gpio_cfgpin(S5PC1XX_GPG3(6), S3C_GPIO_SFN(2)); ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/mm/Kconfig linux-2.6.28.6/arch/arm/mm/Kconfig +--- linux-2.6.28/arch/arm/mm/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/mm/Kconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -183,14 +183,14 @@ + depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || \ + MACH_VERSATILE_AB || ARCH_OMAP730 || \ + ARCH_OMAP16XX || MACH_REALVIEW_EB || \ +- ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \ ++ ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_S3C24A0 || \ + ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \ + ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \ + ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \ + ARCH_NS9XXX || ARCH_DAVINCI || ARCH_MX2 + default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || \ + ARCH_OMAP730 || ARCH_OMAP16XX || \ +- ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \ ++ ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_S3C24A0 || \ + ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \ + ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \ + ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \ +@@ -400,9 +400,10 @@ + # ARMv6 + config CPU_V6 + bool "Support ARM V6 processor" +- depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 ++ depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || ARCH_S3C64XX || ARCH_S5P64XX + default y if ARCH_MX3 + default y if ARCH_MSM ++ default y if (ARCH_S3C64XX || ARCH_S5P64XX) + select CPU_32v6 + select CPU_ABRT_EV6 + select CPU_PABRT_NOIFAR +@@ -428,7 +429,8 @@ + # ARMv7 + config CPU_V7 + bool "Support ARM V7 processor" +- depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP3 ++ depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP3 || ARCH_S5PC1XX ++ default y if ARCH_S5PC1XX + select CPU_32v6K + select CPU_32v7 + select CPU_ABRT_EV7 +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-omap/cpu-omap.c linux-2.6.28.6/arch/arm/plat-omap/cpu-omap.c +--- linux-2.6.28/arch/arm/plat-omap/cpu-omap.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-omap/cpu-omap.c 2009-04-30 09:36:37.000000000 +0200 +@@ -22,7 +22,7 @@ + #include + #include + +-#include ++//#include + #include + + #define VERY_HI_RATE 900000000 +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/Kconfig linux-2.6.28.6/arch/arm/plat-s3c/Kconfig +--- linux-2.6.28/arch/arm/plat-s3c/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/Kconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -6,8 +6,8 @@ + + config PLAT_S3C + bool +- depends on ARCH_S3C2410 +- default y if ARCH_S3C2410 ++ depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX || ARCH_S5P64XX || ARCH_S5PC1XX ++ default y + select NO_IOPORT + help + Base platform code for any Samsung S3C device +@@ -16,24 +16,24 @@ + + config CPU_LLSERIAL_S3C2410_ONLY + bool +- depends on ARCH_S3C2410 ++ depends on PLAT_S3C + default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440 + + config CPU_LLSERIAL_S3C2440_ONLY + bool +- depends on ARCH_S3C2410 ++ depends on PLAT_S3C + default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410 + + config CPU_LLSERIAL_S3C2410 + bool +- depends on ARCH_S3C2410 ++ depends on PLAT_S3C + help + Selected if there is an S3C2410 (or register compatible) serial + low-level implementation needed + + config CPU_LLSERIAL_S3C2440 + bool +- depends on ARCH_S3C2410 ++ depends on PLAT_S3C + help + Selected if there is an S3C2440 (or register compatible) serial + low-level implementation needed +@@ -102,3 +102,97 @@ + such as the `Uncompressing...` at start time. The value of + this configuration should be between zero and two. The port + must have been initialised by the boot-loader before use. ++ ++config SPLIT_ROOT_FILESYSTEM ++ bool "S3C MTD has 4 partitions" ++ depends on (ARCH_S3C64XX || ARCH_S5PC1XX || ARCH_S5P64XX) && MTD ++ help ++ Choose this if you want to use 4 mtd partitions ++ ++# options for gpiolib support ++ ++config S3C_GPIO_SPACE ++ int "Space between gpio banks" ++ default 0 ++ help ++ Add a number of spare GPIO entries between each bank for debugging ++ purposes. This allows any problems where an counter overflows from ++ one bank to another to be caught, at the expense of using a little ++ more memory. ++ ++config S3C_GPIO_TRACK ++ bool ++ help ++ Internal configuration option to enable the s3c specific gpio ++ chip tracking if the platform requires it. ++ ++config S3C_GPIO_PULL_UPDOWN ++ bool ++ help ++ Internal configuration to enable the correct GPIO pull helper ++ ++config S3C_GPIO_PULL_DOWN ++ bool ++ help ++ Internal configuration to enable the correct GPIO pull helper ++ ++config S3C_GPIO_PULL_UP ++ bool ++ help ++ Internal configuration to enable the correct GPIO pull helper ++ ++config S3C_GPIO_CFG_S3C24XX ++ bool ++ help ++ Internal configuration to enable S3C24XX style GPIO configuration ++ functions. ++ ++config S3C_GPIO_CFG_S3C64XX ++ bool ++ help ++ Internal configuration to enable S3C64XX style GPIO configuration ++ functions. ++ ++config S3C_GPIO_CFG_S5PC1XX ++ bool ++ help ++ Internal configuration to enable S5PC1XX style GPIO configuration ++ functions. ++# device definitions to compile in ++ ++config S3C_DEV_HSMMC ++ bool ++ depends on PLAT_S3C ++ help ++ Compile in platform device definitions for HSMMC code ++ ++config S3C_DEV_HSMMC1 ++ bool ++ depends on PLAT_S3C ++ help ++ Compile in platform device definitions for HSMMC channel 1 ++ ++config S3C_DEV_HSMMC2 ++ bool ++ depends on PLAT_S3C ++ help ++ Compile in platform device definitions for HSMMC channel 2 ++ ++config S3C_DEV_I2C1 ++ bool ++ depends on PLAT_S3C ++ help ++ Compile in platform device definitions for I2C channel 1 ++ ++config S3C_DMA_PL080 ++ bool ++ depends on PLAT_S3C ++ help ++ PL080 DMA supported ++ ++config S3C_DMA_PL330 ++ bool ++ depends on PLAT_S3C ++ help ++ PL330 DMA supported ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/Makefile linux-2.6.28.6/arch/arm/plat-s3c/Makefile +--- linux-2.6.28/arch/arm/plat-s3c/Makefile 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/Makefile 2009-04-30 09:36:37.000000000 +0200 +@@ -1,3 +1,32 @@ +-# dummy makefile, currently just including asm/arm/plat-s3c/include/plat ++# arch/arm/plat-s3c/Makefile ++# ++# Copyright 2008 Simtec Electronics ++# ++# Licensed under GPLv2 + +-obj-n := dummy.o ++obj-y := ++obj-m := ++obj-n := ++obj- := ++ ++# Core support for all Samsung SoCs ++ ++obj-y += init.o ++ifndef CONFIG_ARCH_S5PC1XX ++obj-y += time.o ++endif ++obj-y += clock.o ++obj-y += pwm-clock.o ++obj-y += gpio.o ++obj-y += gpio-config.o ++obj-$(CONFIG_S3C_DMA_PL080) += dma-pl080.o ++obj-$(CONFIG_S3C_DMA_PL330) += dma-pl330.o ++ ++# devices ++obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o ++obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o ++obj-$(CONFIG_S3C_DEV_HSMMC2) += dev-hsmmc2.o ++obj-y += dev-i2c0.o ++obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o ++obj-$(CONFIG_TOUCHSCREEN_S3C) += dev-ts.o ++obj-$(CONFIG_SND_S3C6410_SOC_I2S) += dev-i2s.o +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/clock.c linux-2.6.28.6/arch/arm/plat-s3c/clock.c +--- linux-2.6.28/arch/arm/plat-s3c/clock.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/clock.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,446 @@ ++/* linux/arch/arm/plat-s3c/clock.c ++ * ++ * Copyright (c) 2004-2005 Simtec Electronics ++ * Ben Dooks ++ * ++ * S3C24XX Core clock control support ++ * ++ * Based on, and code from linux/arch/arm/mach-versatile/clock.c ++ ** ++ ** Copyright (C) 2004 ARM Limited. ++ ** Written by Deep Blue Solutions Limited. ++ * ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++static LIST_HEAD(clocks); ++ ++/* We originally used an mutex here, but some contexts (see resume) ++ * are calling functions such as clk_set_parent() with IRQs disabled ++ * causing an BUG to be triggered. ++ */ ++DEFINE_SPINLOCK(clocks_lock); ++ ++/* enable and disable calls for use with the clk struct */ ++ ++static int clk_null_enable(struct clk *clk, int enable) ++{ ++ return 0; ++} ++ ++/* Clock API calls */ ++ ++struct clk *clk_get(struct device *dev, const char *id) ++{ ++ struct clk *p; ++ struct clk *clk = ERR_PTR(-ENOENT); ++ int idno; ++ ++ if (dev == NULL || dev->bus != &platform_bus_type) ++ idno = -1; ++ else ++ idno = to_platform_device(dev)->id; ++ ++ spin_lock(&clocks_lock); ++ ++ list_for_each_entry(p, &clocks, list) { ++ if (p->id == idno && ++ strcmp(id, p->name) == 0 && ++ try_module_get(p->owner)) { ++ clk = p; ++ break; ++ } ++ } ++ ++ /* check for the case where a device was supplied, but the ++ * clock that was being searched for is not device specific */ ++ ++ if (IS_ERR(clk)) { ++ list_for_each_entry(p, &clocks, list) { ++ if (p->id == -1 && strcmp(id, p->name) == 0 && ++ try_module_get(p->owner)) { ++ clk = p; ++ break; ++ } ++ } ++ } ++ ++ spin_unlock(&clocks_lock); ++ return clk; ++} ++ ++void clk_put(struct clk *clk) ++{ ++ module_put(clk->owner); ++} ++ ++int clk_enable(struct clk *clk) ++{ ++ if (IS_ERR(clk) || clk == NULL) ++ return -EINVAL; ++ ++ clk_enable(clk->parent); ++ ++ spin_lock(&clocks_lock); ++ ++ if ((clk->usage++) == 0) ++ (clk->enable)(clk, 1); ++ ++ spin_unlock(&clocks_lock); ++ return 0; ++} ++ ++void clk_disable(struct clk *clk) ++{ ++ if (IS_ERR(clk) || clk == NULL) ++ return; ++ ++ spin_lock(&clocks_lock); ++ ++ if ((--clk->usage) == 0) ++ (clk->enable)(clk, 0); ++ ++ spin_unlock(&clocks_lock); ++ clk_disable(clk->parent); ++} ++ ++ ++unsigned long clk_get_rate(struct clk *clk) ++{ ++ if (IS_ERR(clk)) ++ return 0; ++ ++ if (clk->rate != 0) ++ return clk->rate; ++ ++ if (clk->get_rate != NULL) ++ return (clk->get_rate)(clk); ++ ++ if (clk->parent != NULL) ++ return clk_get_rate(clk->parent); ++ ++ return clk->rate; ++} ++ ++long clk_round_rate(struct clk *clk, unsigned long rate) ++{ ++ if (!IS_ERR(clk) && clk->round_rate) ++ return (clk->round_rate)(clk, rate); ++ ++ return rate; ++} ++ ++int clk_set_rate(struct clk *clk, unsigned long rate) ++{ ++ int ret; ++ ++ if (IS_ERR(clk)) ++ return -EINVAL; ++ ++ /* We do not default just do a clk->rate = rate as ++ * the clock may have been made this way by choice. ++ */ ++ ++ WARN_ON(clk->set_rate == NULL); ++ ++ if (clk->set_rate == NULL) ++ return -EINVAL; ++ spin_lock(&clocks_lock); ++ ret = (clk->set_rate)(clk, rate); ++ spin_unlock(&clocks_lock); ++ ++ return ret; ++} ++ ++struct clk *clk_get_parent(struct clk *clk) ++{ ++ return clk->parent; ++} ++ ++int clk_set_parent(struct clk *clk, struct clk *parent) ++{ ++ int ret = 0; ++ ++ if (IS_ERR(clk)) ++ return -EINVAL; ++ ++ spin_lock(&clocks_lock); ++ ++ if (clk->set_parent) ++ ret = (clk->set_parent)(clk, parent); ++ ++ spin_unlock(&clocks_lock); ++ ++ return ret; ++} ++ ++EXPORT_SYMBOL(clk_get); ++EXPORT_SYMBOL(clk_put); ++EXPORT_SYMBOL(clk_enable); ++EXPORT_SYMBOL(clk_disable); ++EXPORT_SYMBOL(clk_get_rate); ++EXPORT_SYMBOL(clk_round_rate); ++EXPORT_SYMBOL(clk_set_rate); ++EXPORT_SYMBOL(clk_get_parent); ++EXPORT_SYMBOL(clk_set_parent); ++ ++/* base clocks */ ++ ++static int clk_default_setrate(struct clk *clk, unsigned long rate) ++{ ++ clk->rate = rate; ++ return 0; ++} ++ ++struct clk clk_xtal = { ++ .name = "xtal", ++ .id = -1, ++ .rate = 0, ++ .parent = NULL, ++ .ctrlbit = 0, ++}; ++ ++struct clk clk_ext = { ++ .name = "ext", ++ .id = -1, ++}; ++ ++struct clk clk_epll = { ++ .name = "epll", ++ .id = -1, ++}; ++ ++struct clk clk_mpll = { ++ .name = "mpll", ++ .id = -1, ++ .set_rate = clk_default_setrate, ++}; ++ ++struct clk clk_upll = { ++ .name = "upll", ++ .id = -1, ++ .parent = NULL, ++ .ctrlbit = 0, ++}; ++ ++struct clk clk_f = { ++ .name = "fclk", ++ .id = -1, ++ .rate = 0, ++ .parent = &clk_mpll, ++ .ctrlbit = 0, ++#if defined(CONFIG_CPU_FREQ) && defined(CONFIG_CPU_S3C6410) ++ .set_rate = s3c_fclk_set_rate, ++ .round_rate = s3c_fclk_round_rate, ++#endif ++}; ++ ++struct clk clk_h = { ++ .name = "hclk", ++ .id = -1, ++ .rate = 0, ++ .parent = NULL, ++ .ctrlbit = 0, ++ .set_rate = clk_default_setrate, ++}; ++ ++#ifdef CONFIG_CPU_S3C6410 ++struct clk clk_hx2 = { ++ .name = "hclkx2", ++ .id = -1, ++ .rate = 0, ++ .parent = NULL, ++ .ctrlbit = 0, ++ .set_rate = clk_default_setrate, ++}; ++#endif ++ ++struct clk clk_p = { ++ .name = "pclk", ++ .id = -1, ++ .rate = 0, ++ .parent = NULL, ++ .ctrlbit = 0, ++ .set_rate = clk_default_setrate, ++}; ++ ++struct clk clk_usb_bus = { ++ .name = "usb-bus", ++ .id = -1, ++ .rate = 0, ++ .parent = &clk_upll, ++}; ++ ++struct clk s3c24xx_uclk = { ++ .name = "uclk", ++ .id = -1, ++}; ++ ++#ifdef CONFIG_CPU_S5P6440 ++struct clk clk_h_low = { ++ .name = "hclk_low", ++ .id = -1, ++ .rate = 0, ++ .parent = NULL, ++ .ctrlbit = 0, ++ .set_rate = clk_default_setrate, ++}; ++ ++struct clk clk_p_low = { ++ .name = "pclk_low", ++ .id = -1, ++ .rate = 0, ++ .parent = NULL, ++ .ctrlbit = 0, ++ .set_rate = clk_default_setrate, ++}; ++#endif ++ ++#ifdef CONFIG_CPU_S5PC100 ++struct clk clk_hpll = { ++ .name = "hpll", ++ .id = -1, ++}; ++ ++struct clk clk_hd0 = { ++ .name = "hclkd0", ++ .id = -1, ++ .rate = 0, ++ .parent = NULL, ++ .ctrlbit = 0, ++ .set_rate = clk_default_setrate, ++}; ++ ++struct clk clk_pd0 = { ++ .name = "pclkd0", ++ .id = -1, ++ .rate = 0, ++ .parent = NULL, ++ .ctrlbit = 0, ++ .set_rate = clk_default_setrate, ++}; ++#endif ++ ++ ++/* initialise the clock system */ ++ ++int s3c24xx_register_clock(struct clk *clk) ++{ ++ clk->owner = THIS_MODULE; ++ ++ if (clk->enable == NULL) ++ clk->enable = clk_null_enable; ++ ++ /* add to the list of available clocks */ ++ ++ /* Quick check to see if this clock has already been registered. */ ++ BUG_ON(clk->list.prev != clk->list.next); ++ ++ spin_lock(&clocks_lock); ++ list_add(&clk->list, &clocks); ++ spin_unlock(&clocks_lock); ++ ++ return 0; ++} ++ ++int s3c24xx_register_clocks(struct clk **clks, int nr_clks) ++{ ++ int fails = 0; ++ ++ for (; nr_clks > 0; nr_clks--, clks++) { ++ if (s3c24xx_register_clock(*clks) < 0) ++ fails++; ++ } ++ ++ return fails; ++} ++ ++/* initalise all the clocks */ ++ ++int __init s3c24xx_register_baseclocks(unsigned long xtal) ++{ ++ printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n"); ++ ++ clk_xtal.rate = xtal; ++ ++ /* register our clocks */ ++ ++ if (s3c24xx_register_clock(&clk_xtal) < 0) ++ printk(KERN_ERR "failed to register master xtal\n"); ++ ++ if (s3c24xx_register_clock(&clk_mpll) < 0) ++ printk(KERN_ERR "failed to register mpll clock\n"); ++ ++ if (s3c24xx_register_clock(&clk_upll) < 0) ++ printk(KERN_ERR "failed to register upll clock\n"); ++ ++ if (s3c24xx_register_clock(&clk_f) < 0) ++ printk(KERN_ERR "failed to register cpu fclk\n"); ++ ++#ifdef CONFIG_CPU_S5P6440 ++ if (s3c24xx_register_clock(&clk_h_low) < 0) ++ printk(KERN_ERR "failed to register cpu hclk_low\n"); ++ ++ if (s3c24xx_register_clock(&clk_p_low) < 0) ++ printk(KERN_ERR "failed to register cpu pclk_low\n"); ++#endif ++ ++#ifdef CONFIG_CPU_S5PC100 ++ if (s3c24xx_register_clock(&clk_hd0) < 0) ++ printk(KERN_ERR "failed to register cpu hclkd0\n"); ++ ++ if (s3c24xx_register_clock(&clk_pd0) < 0) ++ printk(KERN_ERR "failed to register cpu pclkd0\n"); ++#endif ++ ++ if (s3c24xx_register_clock(&clk_h) < 0) ++ printk(KERN_ERR "failed to register cpu hclk\n"); ++ ++#ifdef CONFIG_CPU_S3C6410 ++ if (s3c24xx_register_clock(&clk_hx2) < 0) ++ printk(KERN_ERR "failed to register cpu hclkx2\n"); ++#endif ++ ++ if (s3c24xx_register_clock(&clk_p) < 0) ++ printk(KERN_ERR "failed to register cpu pclk\n"); ++ ++ return 0; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/dev-hsmmc.c linux-2.6.28.6/arch/arm/plat-s3c/dev-hsmmc.c +--- linux-2.6.28/arch/arm/plat-s3c/dev-hsmmc.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/dev-hsmmc.c 2010-04-21 06:36:09.000000000 +0200 +@@ -0,0 +1,105 @@ ++/* linux/arch/arm/plat-s3c/dev-hsmmc.c ++ * ++ * Copyright (c) 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C series device definition for hsmmc devices ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++static void setup_sdhci0_irq_cd (void) ++{ ++ /* init GPIO as a ext irq */ ++ ++ s3c_gpio_cfgpin(S3C64XX_GPN(13), S3C_GPIO_SFN(2)); ++ s3c_gpio_setpull(S3C64XX_GPN(13), S3C_GPIO_PULL_NONE); ++ ++ set_irq_type(S3C_EINT(13), IRQ_TYPE_EDGE_BOTH); ++ ++} ++ ++static uint detect_sdhci0_irq_cd (void) ++{ ++ uint detect; ++ ++ detect = readl(S3C64XX_GPNDAT); ++ detect &= 0x2000; /* GPN13 */ ++ return (!detect); ++} ++ ++static struct resource s3c_hsmmc_resource[] = { ++ [0] = { ++ .start = S3C_PA_HSMMC0, ++ .end = S3C_PA_HSMMC0 + S3C_SZ_HSMMC - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_HSMMC0, ++ .end = IRQ_HSMMC0, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL; ++ ++struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = { ++ .max_width = 4, ++ .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | ++ MMC_CAP_SD_HIGHSPEED), ++ .cfg_ext_cd = setup_sdhci0_irq_cd, ++ .detect_ext_cd = detect_sdhci0_irq_cd, ++ .ext_cd = S3C_EINT(13), ++}; ++ ++struct platform_device s3c_device_hsmmc0 = { ++ .name = "s3c-sdhci", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(s3c_hsmmc_resource), ++ .resource = s3c_hsmmc_resource, ++ .dev = { ++ .dma_mask = &s3c_device_hsmmc_dmamask, ++ .coherent_dma_mask = 0xffffffffUL, ++ .platform_data = &s3c_hsmmc0_def_platdata, ++ }, ++}; ++ ++void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd) ++{ ++ struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata; ++ ++ set->max_width = pd->max_width; ++ ++ if (pd->host_caps) ++ set->host_caps = pd->host_caps; ++ if (pd->cfg_gpio) ++ set->cfg_gpio = pd->cfg_gpio; ++ if (pd->cfg_card) ++ set->cfg_card = pd->cfg_card; ++ if (pd->cfg_ext_cd) ++ set->cfg_ext_cd = pd->cfg_ext_cd; ++ if (pd->detect_ext_cd) ++ set->detect_ext_cd = pd->detect_ext_cd; ++ if (pd->ext_cd) ++ set->ext_cd = pd->ext_cd; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/dev-hsmmc1.c linux-2.6.28.6/arch/arm/plat-s3c/dev-hsmmc1.c +--- linux-2.6.28/arch/arm/plat-s3c/dev-hsmmc1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/dev-hsmmc1.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,75 @@ ++/* linux/arch/arm/plat-s3c/dev-hsmmc1.c ++ * ++ * Copyright (c) 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C series device definition for hsmmc device 1 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++static struct resource s3c_hsmmc1_resource[] = { ++ [0] = { ++ .start = S3C_PA_HSMMC1, ++ .end = S3C_PA_HSMMC1 + S3C_SZ_HSMMC - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_HSMMC1, ++ .end = IRQ_HSMMC1, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static u64 s3c_device_hsmmc1_dmamask = 0xffffffffUL; ++ ++struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = { ++ .max_width = 4, ++ .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | ++ MMC_CAP_SD_HIGHSPEED), ++}; ++ ++struct platform_device s3c_device_hsmmc1 = { ++ .name = "s3c-sdhci", ++ .id = 1, ++ .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource), ++ .resource = s3c_hsmmc1_resource, ++ .dev = { ++ .dma_mask = &s3c_device_hsmmc1_dmamask, ++ .coherent_dma_mask = 0xffffffffUL, ++ .platform_data = &s3c_hsmmc1_def_platdata, ++ }, ++}; ++ ++void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd) ++{ ++ struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata; ++ ++ set->max_width = pd->max_width; ++ ++ if (pd->host_caps) ++ set->host_caps = pd->host_caps; ++ if (pd->cfg_gpio) ++ set->cfg_gpio = pd->cfg_gpio; ++ if (pd->cfg_card) ++ set->cfg_card = pd->cfg_card; ++ if (pd->cfg_ext_cd) ++ set->cfg_ext_cd = pd->cfg_ext_cd; ++ if (pd->detect_ext_cd) ++ set->detect_ext_cd = pd->detect_ext_cd; ++ if (pd->ext_cd) ++ set->ext_cd = pd->ext_cd; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/dev-hsmmc2.c linux-2.6.28.6/arch/arm/plat-s3c/dev-hsmmc2.c +--- linux-2.6.28/arch/arm/plat-s3c/dev-hsmmc2.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/dev-hsmmc2.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,75 @@ ++/* linux/arch/arm/plat-s3c/dev-hsmmc1.c ++ * ++ * Copyright (c) 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C series device definition for hsmmc device 1 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++static struct resource s3c_hsmmc2_resource[] = { ++ [0] = { ++ .start = S3C_PA_HSMMC2, ++ .end = S3C_PA_HSMMC2 + S3C_SZ_HSMMC - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_HSMMC2, ++ .end = IRQ_HSMMC2, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static u64 s3c_device_hsmmc2_dmamask = 0xffffffffUL; ++ ++struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = { ++ .max_width = 4, ++ .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | ++ MMC_CAP_SD_HIGHSPEED | MMC_CAP_ON_BOARD), ++}; ++ ++struct platform_device s3c_device_hsmmc2 = { ++ .name = "s3c-sdhci", ++ .id = 2, ++ .num_resources = ARRAY_SIZE(s3c_hsmmc2_resource), ++ .resource = s3c_hsmmc2_resource, ++ .dev = { ++ .dma_mask = &s3c_device_hsmmc2_dmamask, ++ .coherent_dma_mask = 0xffffffffUL, ++ .platform_data = &s3c_hsmmc2_def_platdata, ++ }, ++}; ++ ++void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd) ++{ ++ struct s3c_sdhci_platdata *set = &s3c_hsmmc2_def_platdata; ++ ++ set->max_width = pd->max_width; ++ ++ if (pd->host_caps) ++ set->host_caps = pd->host_caps; ++ if (pd->cfg_gpio) ++ set->cfg_gpio = pd->cfg_gpio; ++ if (pd->cfg_card) ++ set->cfg_card = pd->cfg_card; ++ if (pd->cfg_ext_cd) ++ set->cfg_ext_cd = pd->cfg_ext_cd; ++ if (pd->detect_ext_cd) ++ set->detect_ext_cd = pd->detect_ext_cd; ++ if (pd->ext_cd) ++ set->ext_cd = pd->ext_cd; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/dev-i2c0.c linux-2.6.28.6/arch/arm/plat-s3c/dev-i2c0.c +--- linux-2.6.28/arch/arm/plat-s3c/dev-i2c0.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/dev-i2c0.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,71 @@ ++/* linux/arch/arm/plat-s3c/dev-i2c0.c ++ * ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C series device definition for i2c device 0 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++static struct resource s3c_i2c_resource[] = { ++ [0] = { ++ .start = S3C_PA_IIC, ++ .end = S3C_PA_IIC + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_IIC, ++ .end = IRQ_IIC, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++struct platform_device s3c_device_i2c0 = { ++ .name = "s3c2410-i2c", ++#ifdef CONFIG_S3C_DEV_I2C1 ++ .id = 0, ++#else ++ .id = -1, ++#endif ++ .num_resources = ARRAY_SIZE(s3c_i2c_resource), ++ .resource = s3c_i2c_resource, ++}; ++ ++static struct s3c2410_platform_i2c default_i2c_data0 __initdata = { ++ .flags = 0, ++ .slave_addr = 0x10, ++ .bus_freq = 100*1000, ++ .max_freq = 400*1000, ++ .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON, ++}; ++ ++void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd) ++{ ++ struct s3c2410_platform_i2c *npd; ++ ++ if (!pd) ++ pd = &default_i2c_data0; ++ ++ npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL); ++ if (!npd) ++ printk(KERN_ERR "%s: no memory for platform data\n", __func__); ++ else if (!npd->cfg_gpio) ++ npd->cfg_gpio = s3c_i2c0_cfg_gpio; ++ ++ s3c_device_i2c0.dev.platform_data = npd; ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/dev-i2c1.c linux-2.6.28.6/arch/arm/plat-s3c/dev-i2c1.c +--- linux-2.6.28/arch/arm/plat-s3c/dev-i2c1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/dev-i2c1.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,68 @@ ++/* linux/arch/arm/plat-s3c/dev-i2c1.c ++ * ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C series device definition for i2c device 1 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++static struct resource s3c_i2c_resource[] = { ++ [0] = { ++ .start = S3C_PA_IIC1, ++ .end = S3C_PA_IIC1 + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_IIC1, ++ .end = IRQ_IIC1, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++struct platform_device s3c_device_i2c1 = { ++ .name = "s3c2410-i2c", ++ .id = 1, ++ .num_resources = ARRAY_SIZE(s3c_i2c_resource), ++ .resource = s3c_i2c_resource, ++}; ++ ++static struct s3c2410_platform_i2c default_i2c_data1 __initdata = { ++ .flags = 0, ++ .bus_num = 1, ++ .slave_addr = 0x10, ++ .bus_freq = 100*1000, ++ .max_freq = 400*1000, ++ .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON, ++}; ++ ++void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd) ++{ ++ struct s3c2410_platform_i2c *npd; ++ ++ if (!pd) ++ pd = &default_i2c_data1; ++ ++ npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL); ++ if (!npd) ++ printk(KERN_ERR "%s: no memory for platform data\n", __func__); ++ else if (!npd->cfg_gpio) ++ npd->cfg_gpio = s3c_i2c1_cfg_gpio; ++ ++ s3c_device_i2c1.dev.platform_data = npd; ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/dev-i2s.c linux-2.6.28.6/arch/arm/plat-s3c/dev-i2s.c +--- linux-2.6.28/arch/arm/plat-s3c/dev-i2s.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/dev-i2s.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,49 @@ ++/* linux/arch/arm/plat-s3c/dev-i2s.c ++ * ++ * Copyright (c) 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C series device definition for hsmmc devices ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++ ++/* IIS */ ++static struct resource s3c_iis_resource[] = { ++ [0] = { ++ .start = S3C_PA_IIS, ++ .end = S3C_PA_IIS + S3C_SZ_IIS -1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_S3C6410_IIS, ++ .end = IRQ_S3C6410_IIS, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static u64 s3c_device_iis_dmamask = 0xffffffffUL; ++ ++struct platform_device s3c_device_iis = { ++ .name = "s3c-iis", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_iis_resource), ++ .resource = s3c_iis_resource, ++ .dev = { ++ .dma_mask = &s3c_device_iis_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/dev-ts.c linux-2.6.28.6/arch/arm/plat-s3c/dev-ts.c +--- linux-2.6.28/arch/arm/plat-s3c/dev-ts.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/dev-ts.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,62 @@ ++/* linux/arch/arm/plat-s3c/dev-ts.c ++ * ++ * Copyright (c) 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C series device definition for hsmmc devices ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++/* Touch srcreen */ ++static struct resource s3c_ts_resource[] = { ++ [0] = { ++ .start = S3C_PA_ADC, ++ .end = S3C_PA_ADC + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_PENDN, ++ .end = IRQ_PENDN, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = IRQ_ADC, ++ .end = IRQ_ADC, ++ .flags = IORESOURCE_IRQ, ++ } ++ ++}; ++ ++struct platform_device s3c_device_ts = { ++ .name = "s3c-ts", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_ts_resource), ++ .resource = s3c_ts_resource, ++}; ++ ++void __init s3c_ts_set_platdata(struct s3c_ts_mach_info *pd) ++{ ++ struct s3c_ts_mach_info *npd; ++ ++ npd = kmalloc(sizeof(*npd), GFP_KERNEL); ++ if (npd) { ++ memcpy(npd, pd, sizeof(*npd)); ++ s3c_device_ts.dev.platform_data = npd; ++ } else { ++ printk(KERN_ERR "no memory for Touchscreen platform data\n"); ++ } ++} ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/dma-pl080.c linux-2.6.28.6/arch/arm/plat-s3c/dma-pl080.c +--- linux-2.6.28/arch/arm/plat-s3c/dma-pl080.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/dma-pl080.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,1600 @@ ++/* linux/arch/arm/plat-s3c/dma-pl080.c ++ * ++ * Copyright (c) 2003-2005,2006 Samsung Electronics ++ * ++ * S3C6400/S3C6410 DMA core ++ * ++ * http://www.samsung.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifdef CONFIG_S3C_DMA_DEBUG ++#define DEBUG ++#endif ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++ ++/* io map for dma */ ++static void __iomem *dma_base; ++static struct kmem_cache *dma_kmem; ++ ++static int dma_channels; ++struct s3c_dma_selection dma_sel; ++static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX]; ++ ++/* dma channel state information */ ++struct s3c2410_dma_chan s3c_dma_chans[S3C_DMA_CHANNELS]; ++s3c_dma_controller_t s3c_dma_cntlrs[S3C_DMA_CONTROLLERS]; ++ ++#undef pr_debug ++//#define dma_dbg ++ ++#ifdef dma_dbg ++#define sh_printk(fmt...) printk( fmt) ++#define pr_debug(fmt...) printk( fmt) ++#else ++#define sh_printk(fmt...) ++#define pr_debug(fmt...) ++#endif ++ ++/* debugging functions */ ++ ++#define BUF_MAGIC (0xcafebabe) ++ ++#define dmawarn(fmt...) printk(KERN_DEBUG fmt) ++ ++#define dma_regaddr(chan, reg) ((chan)->regs + (reg)) ++#define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg)) ++#define dma_rdreg(chan, reg) readl((chan)->regs + (reg)) ++ ++#define dbg_showregs(chan) do { } while(0) ++#define dbg_showchan(chan) do { } while(0) ++ ++void s3c_dma_dump(int dcon_num, int channel) ++{ ++ unsigned long tmp; ++ s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num]; ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_INT_STATUS); ++ printk("%d dcon_num %d subchnnel INT_STATUS %lx\n", dcon_num, channel, tmp); ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_INT_TCSTATUS); ++ printk("%d dcon_num %d subchnnel INT_TCSTATUS %lx\n", dcon_num, channel, tmp); ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_ENBLD_CHANNELS); ++ printk("%d dcon_num %d subchnnel ENBLD_CHANNELS %lx\n", dcon_num, channel, tmp); ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CONFIGURATION); ++ printk("%d dcon_num %d subchnnel DMAC_CONFIGUARATION %lx\n", dcon_num, channel, tmp); ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CSRCADDR(channel)); ++ printk("%d dcon_num %d subchnnel SRCADDRESS %lx\n", dcon_num, channel, tmp); ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CDESTADDR(channel)); ++ printk("%d dcon_num %d subchnnel DESTADDRESS %lx\n", dcon_num, channel, tmp); ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CLLI(channel)); ++ printk("%d dcon_num %d subchnnel LLI %lx\n", dcon_num, channel, tmp); ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CCONTROL0(channel)); ++ printk("%d dcon_num %d subchnnel CCONTROL0 %lx\n", dcon_num, channel, tmp); ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CCONTROL1(channel)); ++ printk("%d dcon_num %d subchnnel CCONTROL1 %lx\n", dcon_num, channel, tmp); ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CCONFIGURATION(channel)); ++ ++ printk("%d dcon_num %d subchnnel CH CONFIGUARATION %lx\n", dcon_num, channel, tmp); ++} ++ ++ ++/* lookup_dma_channel ++ * ++ * change the dma channel number given into a real dma channel id ++*/ ++ ++static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel) ++{ ++ if (channel & DMACH_LOW_LEVEL) ++ return &s3c_dma_chans[channel & ~DMACH_LOW_LEVEL]; ++ else ++ return dma_chan_map[channel]; ++} ++ ++/* s3c_dma_stats_timeout ++ * ++ * Update DMA stats from timeout info ++ */ ++static void s3c_dma_stats_timeout(struct s3c_dma_stats * stats, int val) ++{ ++ if (stats == NULL) ++ return; ++ ++ if (val > stats->timeout_longest) ++ stats->timeout_longest = val; ++ if (val < stats->timeout_shortest) ++ stats->timeout_shortest = val; ++ ++ stats->timeout_avg += val; ++} ++ ++void s3c_enable_dmac(unsigned int dcon_num) ++{ ++ s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num]; ++ dma_wrreg(dma_controller, S3C_DMAC_CONFIGURATION, S3C_DMA_CONTROLLER_ENABLE); ++} ++ ++void s3c_disable_dmac(unsigned int dcon_num) ++{ ++ unsigned long tmp; ++ s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num]; ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CONFIGURATION); ++ tmp &= ~S3C_DMA_CONTROLLER_ENABLE; ++ dma_wrreg(dma_controller, S3C_DMAC_CONFIGURATION, tmp); ++} ++ ++void s3c_clear_interrupts (int dcon_num, int channel) ++{ ++ unsigned long tmp; ++ s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num]; ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_INT_TCCLEAR); ++ tmp |= (1 << channel); ++ dma_wrreg(dma_controller, S3C_DMAC_INT_TCCLEAR, tmp); ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_INT_ERRORCLEAR); ++ tmp |= (1 << channel); ++ dma_wrreg(dma_controller, S3C_DMAC_INT_ERRORCLEAR, tmp); ++} ++ ++/* s3c_dma_waitforload ++ * ++ * wait for the DMA engine to load a buffer, and update the state accordingly ++ */ ++static int s3c_dma_waitforload(struct s3c2410_dma_chan *chan, int line) ++{ ++ int timeout = chan->load_timeout; ++ int took; ++ ++ pr_debug("%s channel number : %d\n", __FUNCTION__, chan->number); ++ ++ if (chan->load_state != S3C_DMALOAD_1LOADED) { ++ printk(KERN_ERR ++ "dma%d: s3c_dma_waitforload() called in loadstate %d from line %d\n", ++ chan->number, chan->load_state, line); ++ return 0; ++ } ++ ++ if (chan->stats != NULL) ++ chan->stats->loads++; ++ ++ while (--timeout > 0) { ++ if ((dma_rdreg(chan->dma_con, S3C_DMAC_ENBLD_CHANNELS)) & (0x1 << chan->number)) { ++ took = chan->load_timeout - timeout; ++ s3c_dma_stats_timeout(chan->stats, took); ++ ++ switch (chan->load_state) { ++ case S3C_DMALOAD_1LOADED: ++ chan->load_state = S3C_DMALOAD_1RUNNING; ++ break; ++ ++ default: ++ printk(KERN_ERR ++ "dma%d: unknown load_state in s3c_dma_waitforload() %d\n", ++ chan->number, chan->load_state); ++ } ++ ++ return 1; ++ } ++ } ++ ++ if (chan->stats != NULL) { ++ chan->stats->timeout_failed++; ++ } ++ ++ return 0; ++} ++ ++ ++/* s3c_dma_loadbuffer ++ * ++ * load a buffer, and update the channel state ++ */ ++static inline int s3c_dma_loadbuffer(struct s3c2410_dma_chan *chan, ++ struct s3c_dma_buf *buf) ++{ ++ unsigned long reload; ++ ++ pr_debug("s3c_chan_loadbuffer: loading buffer %p (0x%08lx,0x%06x)\n", ++ buf, (unsigned long) buf->data, buf->size); ++ ++ if (buf == NULL) { ++ dmawarn("buffer is NULL\n"); ++ return -EINVAL; ++ } ++ ++ /* check the state of the channel before we do anything */ ++ ++ if (chan->load_state == S3C_DMALOAD_1LOADED) { ++ dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n"); ++ reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0; ++ } ++ ++ if (chan->load_state == S3C_DMALOAD_1LOADED_1RUNNING) { ++ dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n"); ++ reload = S3C2410_DCON_AUTORELOAD; ++ } ++ ++ writel(buf->data, chan->addr_reg); ++ ++ pr_debug("%s: DMA control0 - %08x\n", __FUNCTION__, chan->dcon); ++ pr_debug("%s: DMA control1 - %08x\n", __FUNCTION__, (buf->size / chan->xfer_unit)); ++ ++ dma_wrreg(chan, S3C_DMAC_CxCONTROL0, chan->dcon); ++ dma_wrreg(chan, S3C_DMAC_CxCONTROL1, (buf->size / chan->xfer_unit)); ++ ++ chan->next = buf->next; ++ ++ /* update the state of the channel */ ++ ++ switch (chan->load_state) { ++ case S3C_DMALOAD_NONE: ++ chan->load_state = S3C_DMALOAD_1LOADED; ++ break; ++ ++ case S3C_DMALOAD_1RUNNING: ++ chan->load_state = S3C_DMALOAD_1LOADED_1RUNNING; ++ break; ++ ++ default: ++ dmawarn("dmaload: unknown state %d in loadbuffer\n", chan->load_state); ++ break; ++ } ++ ++ return 0; ++} ++ ++ ++/* s3c_dma_call_op ++ * ++ * small routine to call the o routine with the given op if it has been ++ * registered ++ */ ++static void s3c_dma_call_op(struct s3c2410_dma_chan * chan, enum s3c_chan_op op) ++{ ++ if (chan->op_fn != NULL) { ++ (chan->op_fn) (chan, op); ++ } ++} ++ ++/* s3c_dma_buffdone ++ * ++ * small wrapper to check if callback routine needs to be called, and ++ * if so, call it ++ */ ++static inline void s3c_dma_buffdone(struct s3c2410_dma_chan * chan, ++ struct s3c_dma_buf * buf, ++ enum s3c2410_dma_buffresult result) ++{ ++ pr_debug("callback_fn will be called=%p, buf=%p, id=%p, size=%d, result=%d\n", ++ chan->callback_fn, buf, buf->id, buf->size, result); ++ ++ if (chan->callback_fn != NULL) { ++ (chan->callback_fn) (chan, buf->id, buf->size, result); ++ } ++} ++ ++/* s3c_dma_start ++ * ++ * start a dma channel going ++ */ ++static int s3c_dma_start(struct s3c2410_dma_chan *chan) ++{ ++ unsigned long flags; ++ ++ pr_debug("s3c_start_dma: channel number=%d, index=%d\n", chan->number, chan->index); ++ ++ local_irq_save(flags); ++ ++ if (chan->state == S3C_DMA_RUNNING) { ++ pr_debug("s3c_start_dma: already running (%d)\n", chan->state); ++ local_irq_restore(flags); ++ return 0; ++ } ++ ++ chan->state = S3C_DMA_RUNNING; ++ ++ /* check wether there is anything to load, and if not, see ++ * if we can find anything to load ++ */ ++ ++ if (chan->load_state == S3C_DMALOAD_NONE) { ++ if (chan->next == NULL) { ++ printk(KERN_ERR "dma%d: dcon_num has nothing loaded\n", chan->number); ++ chan->state = S3C_DMA_IDLE; ++ local_irq_restore(flags); ++ return -EINVAL; ++ } ++ ++ s3c_dma_loadbuffer(chan, chan->next); ++ } ++ ++ dbg_showchan(chan); ++ ++ /* enable the channel */ ++ ++ if (!chan->irq_enabled) { ++ enable_irq(chan->irq); ++ chan->irq_enabled = 1; ++ } ++ ++ /* Get the DMA channel started ...*/ ++ dma_wrreg(chan, S3C_DMAC_CxCONFIGURATION, chan->config_flags); ++ ++ pr_debug("%s:wrote %08lx to S3C_DMAC_CxCONFIGURATION.\n",__FUNCTION__, chan->config_flags); ++ ++ /* Start the DMA operation on Peripheral */ ++ s3c_dma_call_op(chan, S3C2410_DMAOP_START); ++ ++ dbg_showchan(chan); ++ ++ local_irq_restore(flags); ++ return 0; ++} ++ ++ ++/* s3c2410_dma_enqueue ++ * ++ * queue an given buffer for dma transfer. ++ * ++ * id the device driver's id information for this buffer ++ * data the physical address of the buffer data ++ * size the size of the buffer in bytes ++ * ++ * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART ++ * is checked, and if set, the channel is started. If this flag isn't set, ++ * then an error will be returned. ++ * ++ * It is possible to queue more than one DMA buffer onto a channel at ++ * once, and the code will deal with the re-loading of the next buffer ++ * when necessary. ++ */ ++int s3c2410_dma_enqueue(unsigned int channel, void *id, ++ dma_addr_t data, int size) ++{ ++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); ++ struct s3c_dma_buf *buf; ++ unsigned long flags; ++ ++ pr_debug("%s: id=%p, data=%08x, size=%d\n", __FUNCTION__, id, (unsigned int) data, size); ++ ++ buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC); ++ if (buf == NULL) { ++ printk(KERN_ERR "dma<%d> no memory for buffer\n", channel); ++ return -ENOMEM; ++ } ++ ++ pr_debug("%s: new buffer %p\n", __FUNCTION__, buf); ++ ++ //dbg_showchan(chan); ++ ++ buf->next = NULL; ++ buf->data = buf->ptr = data; ++ buf->size = size; ++ buf->id = id; ++ buf->magic = BUF_MAGIC; ++ ++ local_irq_save(flags); ++ ++ if (chan->curr == NULL) { ++ /* we've got nothing loaded... */ ++ pr_debug("%s: buffer %p queued onto empty channel\n", __FUNCTION__, buf); ++ ++ chan->curr = buf; ++ chan->end = buf; ++ chan->next = NULL; ++ } else { ++ pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n", ++ chan->number, __FUNCTION__, buf); ++ ++ if (chan->end == NULL) /* In case of flushing */ ++ pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n", ++ chan->number, __FUNCTION__, chan); ++ else { ++ chan->end->next = buf; ++ chan->end = buf; ++ } ++ } ++ ++ /* if necessary, update the next buffer field */ ++ if (chan->next == NULL) ++ chan->next = buf; ++ ++ /* check to see if we can load a buffer */ ++ if (chan->state == S3C_DMA_RUNNING) { ++ if (chan->load_state == S3C_DMALOAD_1LOADED && 1) { ++ if (s3c_dma_waitforload(chan, __LINE__) == 0) { ++ printk(KERN_ERR "dma%d: loadbuffer:" ++ "timeout loading buffer\n", chan->number); ++ dbg_showchan(chan); ++ local_irq_restore(flags); ++ return -EINVAL; ++ } ++ } ++ } else if (chan->state == S3C_DMA_IDLE) { ++ if (chan->flags & S3C2410_DMAF_AUTOSTART) { ++ s3c2410_dma_ctrl(channel, S3C2410_DMAOP_START); ++ } else { ++ pr_debug("loading onto stopped channel\n"); ++ } ++ } ++ ++ local_irq_restore(flags); ++ return 0; ++} ++EXPORT_SYMBOL(s3c2410_dma_enqueue); ++ ++/* s3c2410_dma_enqueue_sg ++ * ++ * queue an given buffer for dma transfer. ++ * ++ * id the device driver's id information for this buffer ++ * data the physical address of the buffer data ++ * size the size of the buffer in bytes ++ * sg_reg the scatter&gather list ++ * ++ * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART ++ * is checked, and if set, the channel is started. If this flag isn't set, ++ * then an error will be returned. ++ * ++ * It is possible to queue more than one DMA buffer onto a channel at ++ * once, and the code will deal with the re-loading of the next buffer ++ * when necessary. ++ */ ++int s3c2410_dma_enqueue_sg(unsigned int channel, void *id, ++ dma_addr_t data, int size, struct s3c_sg_list *sg_list) ++{ ++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); ++ struct s3c_dma_buf *buf; ++ unsigned long flags; ++ ++ pr_debug("%s: id=%p, data=%08x, size=%d\n", __FUNCTION__, id, (unsigned int) data, size); ++ ++ buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC); ++ if (buf == NULL) { ++ printk(KERN_ERR "dma<%d> no memory for buffer\n", channel); ++ return -ENOMEM; ++ } ++ ++ pr_debug("%s: new buffer %p\n", __FUNCTION__, buf); ++ ++ //dbg_showchan(chan); ++ ++ buf->next = NULL; ++ buf->data = buf->ptr = data; ++ buf->size = size; ++ buf->id = id; ++ buf->magic = BUF_MAGIC; ++ ++ local_irq_save(flags); ++ ++ if (chan->curr == NULL) { ++ /* we've got nothing loaded... */ ++ pr_debug("%s: buffer %p queued onto empty channel\n", __FUNCTION__, buf); ++ ++ chan->curr = buf; ++ chan->end = buf; ++ chan->next = NULL; ++ } else { ++ pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n", ++ chan->number, __FUNCTION__, buf); ++ ++ if (chan->end == NULL) /* In case of flushing */ ++ pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n", ++ chan->number, __FUNCTION__, chan); ++ else { ++ chan->end->next = buf; ++ chan->end = buf; ++ } ++ } ++ ++ /* if necessary, update the next buffer field */ ++ if (chan->next == NULL) ++ chan->next = buf; ++ ++ /* check to see if we can load a buffer */ ++ if (chan->state == S3C_DMA_RUNNING) { ++ if (chan->load_state == S3C_DMALOAD_1LOADED && 1) { ++ if (s3c_dma_waitforload(chan, __LINE__) == 0) { ++ printk(KERN_ERR "dma%d: loadbuffer:" ++ "timeout loading buffer\n", chan->number); ++ dbg_showchan(chan); ++ local_irq_restore(flags); ++ return -EINVAL; ++ } ++ } ++ } else if (chan->state == S3C_DMA_IDLE) { ++ dma_wrreg(chan, S3C_DMAC_CxLLI, virt_to_phys(&sg_list)); ++ ++ if (chan->flags & S3C2410_DMAF_AUTOSTART) { ++ s3c2410_dma_ctrl(channel, S3C2410_DMAOP_START); ++ } else { ++ pr_debug("loading onto stopped channel\n"); ++ } ++ } ++ ++ local_irq_restore(flags); ++ return 0; ++} ++EXPORT_SYMBOL(s3c2410_dma_enqueue_sg); ++ ++ ++static inline void s3c_dma_freebuf(struct s3c_dma_buf * buf) ++{ ++ int magicok = (buf->magic == BUF_MAGIC); ++ ++ buf->magic = -1; ++ ++ if (magicok) { ++ kmem_cache_free(dma_kmem, buf); ++ } else { ++ printk("s3c_dma_freebuf: buff %p with bad magic\n", buf); ++ } ++} ++ ++/* s3c_dma_lastxfer ++ * ++ * called when the system is out of buffers, to ensure that the channel ++ * is prepared for shutdown. ++ */ ++static inline void s3c_dma_lastxfer(struct s3c2410_dma_chan *chan) ++{ ++ pr_debug("DMA CH %d: s3c_dma_lastxfer: load_state %d\n", chan->number, chan->load_state); ++ ++ switch (chan->load_state) { ++ case S3C_DMALOAD_NONE: ++ pr_debug("DMA CH %d: s3c_dma_lastxfer: load_state : S3C2_DMALOAD_NONE%d\n", chan->number); ++ break; ++ ++ case S3C_DMALOAD_1LOADED: ++ if (s3c_dma_waitforload(chan, __LINE__) == 0) { ++ /* flag error? */ ++ printk(KERN_ERR "dma%d: timeout waiting for load\n", chan->number); ++ return; ++ } ++ break; ++ ++ default: ++ pr_debug("dma%d: lastxfer: unhandled load_state %d with no next", ++ chan->number, chan->load_state); ++ return; ++ ++ } ++ ++} ++ ++ ++#define dmadbg2(x...) ++ ++static irqreturn_t s3c_dma_irq(int irq, void *devpw) ++{ ++ unsigned int channel = 0, dcon_num, i; ++ unsigned long tmp; ++ s3c_dma_controller_t *dma_controller = (s3c_dma_controller_t *) devpw; ++ ++ struct s3c2410_dma_chan *chan=NULL; ++ struct s3c_dma_buf *buf; ++ ++ dcon_num = dma_controller->number; ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_INT_TCSTATUS); ++ pr_debug("# s3c_dma_irq: TC status : 0x%x\n", tmp); ++ ++ if(tmp==0) { ++ return IRQ_HANDLED; ++ } ++ ++ for (i = 0; i < S3C_CHANNELS_PER_DMA; i++) { ++ if (tmp & 0x01) { ++ ++ pr_debug("# DMA Controller %d: requestor %d\n", dcon_num, i); ++ ++ channel = i; ++ chan = &s3c_dma_chans[channel + dcon_num * S3C_CHANNELS_PER_DMA]; ++ pr_debug("# DMA channel number : %d, index : %d\n", chan->number, chan->index); ++ ++ buf = chan->curr; ++ ++ dbg_showchan(chan); ++ ++ /* modify the channel state */ ++ switch (chan->load_state) { ++ case S3C_DMALOAD_1RUNNING: ++ /* TODO - if we are running only one buffer, we probably ++ * want to reload here, and then worry about the buffer ++ * callback */ ++ ++ chan->load_state = S3C_DMALOAD_NONE; ++ break; ++ ++ case S3C_DMALOAD_1LOADED: ++ /* iirc, we should go back to NONE loaded here, we ++ * had a buffer, and it was never verified as being ++ * loaded. ++ */ ++ ++ chan->load_state = S3C_DMALOAD_NONE; ++ break; ++ ++ case S3C_DMALOAD_1LOADED_1RUNNING: ++ /* we'll worry about checking to see if another buffer is ++ * ready after we've called back the owner. This should ++ * ensure we do not wait around too long for the DMA ++ * engine to start the next transfer ++ */ ++ ++ chan->load_state = S3C_DMALOAD_1LOADED; ++ break; ++ ++ case S3C_DMALOAD_NONE: ++ printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n", ++ chan->number); ++ break; ++ ++ default: ++ printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n", ++ chan->number, chan->load_state); ++ break; ++ } ++ ++ if (buf != NULL) { ++ /* update the chain to make sure that if we load any more ++ * buffers when we call the callback function, things should ++ * work properly */ ++ ++ chan->curr = buf->next; ++ buf->next = NULL; ++ ++ if (buf->magic != BUF_MAGIC) { ++ printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n", ++ chan->number, __FUNCTION__, buf); ++ goto next_channel; ++ } ++ ++ s3c_dma_buffdone(chan, buf, S3C2410_RES_OK); ++ ++ /* free resouces */ ++ s3c_dma_freebuf(buf); ++ } else { ++ ++ } ++ ++ if (chan->next != NULL) { ++ unsigned long flags; ++ ++ switch (chan->load_state) { ++ case S3C_DMALOAD_1RUNNING: ++ /* don't need to do anything for this state */ ++ break; ++ ++ case S3C_DMALOAD_NONE: ++ /* can load buffer immediately */ ++ break; ++ ++ case S3C_DMALOAD_1LOADED: ++ if (s3c_dma_waitforload(chan, __LINE__) == 0) { ++ /* flag error? */ ++ printk(KERN_ERR "dma%d: timeout waiting for load\n", ++ chan->number); ++ goto next_channel; ++ } ++ ++ break; ++ ++ case S3C_DMALOAD_1LOADED_1RUNNING: ++ goto next_channel; ++ ++ default: ++ printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n", ++ chan->number, chan->load_state); ++ goto next_channel; ++ } ++ ++ local_irq_save(flags); ++ s3c_dma_loadbuffer(chan, chan->next); ++ ++ //shaju added for dbg ++ dma_wrreg(chan, S3C_DMAC_CxCONFIGURATION, chan->config_flags); ++ ++ local_irq_restore(flags); ++ ++ } else { ++ s3c_dma_lastxfer(chan); ++ ++ /* see if we can stop this channel.. */ ++ if (chan->load_state == S3C_DMALOAD_NONE) { ++ pr_debug("# DMA CH %d(index:%d): end of transfer, stopping channel (%ld)\n", ++ chan->number, chan->index, jiffies); ++ s3c2410_dma_ctrl(chan->index | DMACH_LOW_LEVEL, S3C2410_DMAOP_STOP); ++ } ++ } ++ } ++ ++next_channel: ++ tmp >>= 1; ++ ++ } ++ ++ s3c_clear_interrupts(chan->dma_con->number, chan->number); ++ ++ return IRQ_HANDLED; ++} ++ ++static struct s3c2410_dma_chan *s3c_dma_map_channel(int channel); ++ ++/* s3c_request_dma ++ * ++ * get control of an dma channel ++*/ ++ ++int s3c2410_dma_request(unsigned int channel, ++ struct s3c2410_dma_client *client, ++ void *dev) ++{ ++ struct s3c2410_dma_chan *chan; ++ unsigned long flags; ++ int err; ++ ++ pr_debug("DMA CH %d: s3c2410_request_dma: client=%s, dev=%p\n", ++ channel, client->name, dev); ++ ++ local_irq_save(flags); ++ ++ chan = s3c_dma_map_channel(channel); ++ if (chan == NULL) { ++ local_irq_restore(flags); ++ return -EBUSY; ++ } ++ ++ dbg_showchan(chan); ++ ++ chan->client = client; ++ chan->in_use = 1; ++ ++ chan->dma_con->in_use++; ++ ++ if (!chan->irq_claimed) { ++ pr_debug("DMA CH %d: %s : requesting irq %d\n", ++ channel, __FUNCTION__, chan->irq); ++ ++ chan->irq_claimed = 1; ++ local_irq_restore(flags); ++ ++ err = request_irq(chan->irq, s3c_dma_irq, IRQF_DISABLED|IRQF_SHARED, ++ client->name, (void *) chan->dma_con); ++ ++ local_irq_save(flags); ++ ++ if (err) { ++ chan->in_use = 0; ++ chan->irq_claimed = 0; ++ chan->dma_con->in_use--; ++ local_irq_restore(flags); ++ ++ printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n", ++ client->name, chan->irq, chan->number); ++ return err; ++ } ++ ++ chan->irq_enabled = 1; ++ ++ /* enable the main dma.. this can be disabled ++ * when main channel use count is 0 */ ++ s3c_enable_dmac(chan->dma_con->number); ++ } ++ ++ s3c_clear_interrupts(chan->dma_con->number, chan->number); ++ local_irq_restore(flags); ++ ++ /* need to setup */ ++ ++ pr_debug("%s: channel initialised, %p, number:%d, index:%d\n", __FUNCTION__, chan, chan->number, chan->index); ++ ++ return 0; ++} ++EXPORT_SYMBOL(s3c2410_dma_request); ++ ++/* s3c_dma_free ++ * ++ * release the given channel back to the system, will stop and flush ++ * any outstanding transfers, and ensure the channel is ready for the ++ * next claimant. ++ * ++ * Note, although a warning is currently printed if the freeing client ++ * info is not the same as the registrant's client info, the free is still ++ * allowed to go through. ++ */ ++int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client) ++{ ++ unsigned long flags; ++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); ++ pr_debug("%s: DMA channel %d will be stopped\n", __FUNCTION__, chan->number); ++ ++ if (chan == NULL) ++ return -EINVAL; ++ ++ local_irq_save(flags); ++ ++ if (chan->client != client) { ++ printk(KERN_WARNING ++ "DMA CH %d: possible free from different client (channel %p, passed %p)\n", ++ channel, chan->client, client); ++ } ++ ++ /* sort out stopping and freeing the channel */ ++ ++ if (chan->state != S3C_DMA_IDLE) { ++ pr_debug("%s: need to stop dma channel %p\n", __FUNCTION__, chan); ++ ++ /* possibly flush the channel */ ++ s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP); ++ } ++ ++ chan->client = NULL; ++ chan->in_use = 0; ++ ++ chan->dma_con->in_use--; ++ ++ if (chan->irq_claimed) ++ free_irq(chan->irq, (void *)chan->dma_con); ++ ++ chan->irq_claimed = 0; ++ ++ if (!(channel & DMACH_LOW_LEVEL)) ++ dma_chan_map[channel] = NULL; ++ ++ local_irq_restore(flags); ++ ++ return 0; ++} ++EXPORT_SYMBOL(s3c2410_dma_free); ++ ++/*actively polling for the A bit can block the cpu*/ ++void s3c_dma_flush_fifo(struct s3c2410_dma_chan *chan) ++{ ++ unsigned long tmp; ++ ++ tmp = dma_rdreg(chan, S3C_DMAC_CxCONFIGURATION); ++ tmp |= S3C_DMACONFIG_HALT; ++ dma_wrreg(chan, S3C_DMAC_CxCONFIGURATION, tmp); ++ ++ tmp = dma_rdreg(chan, S3C_DMAC_CxCONFIGURATION); ++ ++ /*this while loop can be very dangerous..may be put the process to sleep rather than waiting till fifo is drained */ ++ while (tmp & S3C_DMACONFIG_ACTIVE) { ++ tmp = dma_rdreg(chan, S3C_DMAC_CxCONFIGURATION); ++ } ++} ++ ++static int s3c_dma_dostop(struct s3c2410_dma_chan *chan) ++{ ++ unsigned long tmp; ++ unsigned long flags; ++ ++ pr_debug("%s: DMA Channel No : %d\n", __FUNCTION__, chan->number); ++ ++ dbg_showchan(chan); ++ ++ local_irq_save(flags); ++ ++ s3c_dma_flush_fifo(chan); ++ ++ s3c_dma_call_op(chan, S3C2410_DMAOP_STOP); ++ ++ tmp = dma_rdreg(chan, S3C_DMAC_CxCONFIGURATION); ++ ++ tmp &= ~S3C_DMACONFIG_CHANNEL_ENABLE; ++ dma_wrreg(chan, S3C_DMAC_CxCONFIGURATION, tmp); ++ ++ pr_debug("%s: S3C_DMAC_CxCONFIGURATION : %08x\n", __FUNCTION__, tmp); ++ ++ chan->state = S3C_DMA_IDLE; ++ chan->load_state = S3C_DMALOAD_NONE; ++ ++ local_irq_restore(flags); ++ ++ return 0; ++} ++ ++static void s3c_dma_showchan(struct s3c2410_dma_chan * chan) ++{ ++ ++} ++ ++/* s3c_dma_flush ++ * ++ * stop the channel, and remove all current and pending transfers ++ */ ++ ++void s3c_waitforstop(struct s3c2410_dma_chan *chan) ++{ ++ ++} ++ ++static int s3c_dma_flush(struct s3c2410_dma_chan *chan) ++{ ++ struct s3c_dma_buf *buf, *next; ++ unsigned long flags; ++ ++ pr_debug("%s:\n", __FUNCTION__); ++ ++ local_irq_save(flags); ++ ++ s3c_dma_showchan(chan); ++ ++ if (chan->state != S3C_DMA_IDLE) { ++ pr_debug("%s: stopping channel...\n", __FUNCTION__); ++ s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP); ++ } ++ ++ buf = chan->curr; ++ if (buf == NULL) ++ buf = chan->next; ++ ++ chan->curr = chan->next = chan->end = NULL; ++ chan->load_state = S3C_DMALOAD_NONE; ++ ++ if (buf != NULL) { ++ for (; buf != NULL; buf = next) { ++ next = buf->next; ++ ++ pr_debug("%s: free buffer %p, next %p\n", __FUNCTION__, buf, buf->next); ++ ++ s3c_dma_buffdone(chan, buf, S3C2410_RES_ABORT); ++ s3c_dma_freebuf(buf); ++ } ++ } ++ //s3c_dma_waitforstop(chan); ++ ++ s3c_dma_showchan(chan); ++ local_irq_restore(flags); ++ ++ return 0; ++} ++ ++int s3c_dma_started(struct s3c2410_dma_chan *chan) ++{ ++ unsigned long flags; ++ ++ local_irq_save(flags); ++ ++ dbg_showchan(chan); ++ ++ /* if we've only loaded one buffer onto the channel, then chec ++ * to see if we have another, and if so, try and load it so when ++ * the first buffer is finished, the new one will be loaded onto ++ * the channel */ ++ ++ if (chan->next != NULL) { ++ if (chan->load_state == S3C_DMALOAD_1LOADED) { ++ ++ if (s3c_dma_waitforload(chan, __LINE__) == 0) { ++ pr_debug("%s: buff not yet loaded, no more todo\n", ++ __FUNCTION__); ++ } else { ++ chan->load_state = S3C_DMALOAD_1RUNNING; ++ s3c_dma_loadbuffer(chan, chan->next); ++ } ++ ++ } else if (chan->load_state == S3C_DMALOAD_1RUNNING) { ++ s3c_dma_loadbuffer(chan, chan->next); ++ } ++ } ++ ++ local_irq_restore(flags); ++ ++ return 0; ++ ++} ++ ++int s3c2410_dma_ctrl(dmach_t channel, enum s3c_chan_op op) ++{ ++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); ++ ++ if (chan == NULL) ++ return -EINVAL; ++ ++ switch (op) { ++ case S3C2410_DMAOP_START: ++ return s3c_dma_start(chan); ++ ++ case S3C2410_DMAOP_STOP: ++ return s3c_dma_dostop(chan); ++ ++ case S3C2410_DMAOP_PAUSE: ++ case S3C2410_DMAOP_RESUME: ++ return -ENOENT; ++ ++ case S3C2410_DMAOP_FLUSH: ++ return s3c_dma_flush(chan); ++ ++ case S3C2410_DMAOP_STARTED: ++ return s3c_dma_started(chan); ++ ++ case S3C2410_DMAOP_TIMEOUT: ++ return 0; ++ ++ } ++ ++ return -ENOENT; /* unknown, don't bother */ ++} ++EXPORT_SYMBOL(s3c2410_dma_ctrl); ++ ++ ++/* s3c_dma_config ++ * ++ * xfersize: size of unit in bytes (1,2,4) ++ * dcon: base value of the DCONx register ++ */ ++int s3c2410_dma_config(dmach_t channel, ++ int xferunit, ++ int dcon) ++{ ++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); ++ ++ pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n", ++ __FUNCTION__, channel, xferunit, dcon); ++ ++ if (chan == NULL) ++ return -EINVAL; ++ ++ pr_debug("%s: Initial dcon is %08x\n", __FUNCTION__, dcon); ++ ++ dcon |= chan->dcon & dma_sel.dcon_mask; ++ ++ pr_debug("%s: New dcon is %08x\n", __FUNCTION__, dcon); ++ ++ switch (xferunit) { ++ case 1: ++ dcon |= S3C_DMACONTROL_SRC_WIDTH_BYTE; ++ dcon |= S3C_DMACONTROL_DEST_WIDTH_BYTE; ++ break; ++ ++ case 2: ++ dcon |= S3C_DMACONTROL_SRC_WIDTH_HWORD; ++ dcon |= S3C_DMACONTROL_DEST_WIDTH_HWORD; ++ break; ++ ++ case 4: ++ dcon |= S3C_DMACONTROL_SRC_WIDTH_WORD; ++ dcon |= S3C_DMACONTROL_DEST_WIDTH_WORD; ++ break; ++ ++ default: ++ pr_debug("%s: Bad transfer size %d\n", __FUNCTION__, xferunit); ++ return -EINVAL; ++ } ++ ++ pr_debug("%s: DMA Channel control : %08x\n", __FUNCTION__, dcon); ++ ++ dcon |= S3C_DMACONTROL_TC_INT_ENABLE; ++ dcon |= chan->control_flags; ++ pr_debug("%s: dcon now %08x\n", __FUNCTION__, dcon); ++ ++ /* For DMCCxControl 0 */ ++ chan->dcon = dcon; ++ ++ /* For DMACCxControl 1 : xferunit means transfer width.*/ ++ chan->xfer_unit = xferunit; ++ ++ return 0; ++} ++EXPORT_SYMBOL(s3c2410_dma_config); ++ ++ ++int s3c2410_dma_setflags(dmach_t channel, unsigned int flags) ++{ ++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); ++ ++ if (chan == NULL) ++ return -EINVAL; ++ ++ pr_debug("%s: chan=%p, flags=%08x\n", __FUNCTION__, chan, flags); ++ ++ chan->flags = flags; ++ ++ return 0; ++} ++EXPORT_SYMBOL(s3c2410_dma_setflags); ++ ++ ++/* do we need to protect the settings of the fields from ++ * irq? ++ */ ++ ++int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn) ++{ ++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); ++ ++ if (chan == NULL) ++ return -EINVAL; ++ ++ pr_debug("%s: chan=%p, op rtn=%p\n", __FUNCTION__, chan, rtn); ++ ++ chan->op_fn = rtn; ++ ++ return 0; ++} ++EXPORT_SYMBOL(s3c2410_dma_set_opfn); ++ ++ ++int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn) ++{ ++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); ++ ++ if (chan == NULL) ++ return -EINVAL; ++ ++ pr_debug("%s: chan=%p, callback rtn=%p\n", __FUNCTION__, chan, rtn); ++ ++ chan->callback_fn = rtn; ++ ++ return 0; ++} ++EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn); ++ ++ ++/* s3c2410_dma_devconfig ++ * ++ * configure the dma source/destination hardware type and address ++ * ++ * flowctrl: direction of dma flow ++ * ++ * src_per dst_per: dma channel number of src and dst periphreal, ++ * ++ * devaddr: physical address of the source ++ */ ++ ++int s3c2410_dma_devconfig(int channel, ++ enum s3c2410_dmasrc source, ++ int hwcfg, ++ unsigned long devaddr) ++{ ++ unsigned long tmp; ++ ++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); ++ ++ if (chan == NULL) ++ return -EINVAL; ++ ++ pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n", ++ __FUNCTION__, (int)source, hwcfg, devaddr); ++ ++ chan->source = source; ++ chan->dev_addr = devaddr; ++ ++ switch (source) { ++ case S3C2410_DMASRC_MEM: ++ /* source is Memory : Mem-to-Peri ( Write into FIFO) */ ++ tmp = S3C_DMACONFIG_TCMASK | S3C_DMACONFIG_FLOWCTRL_MEM2PER | (chan->map->hw_addr.to) << ++ S3C_DEST_SHIFT | S3C_DMACONFIG_CHANNEL_ENABLE; ++ ++ chan->config_flags = tmp; ++ ++ /* TODO : Now, Scatter&Gather DMA NOT supported */ ++ dma_wrreg(chan, S3C_DMAC_CxLLI, 0); ++ ++ /* devaddr : Periperal address (destination) */ ++ dma_wrreg(chan, S3C_DMAC_CxDESTADDR, devaddr); ++ ++ /* source address : memory(buffer) address */ ++ chan->addr_reg = dma_regaddr(chan, S3C_DMAC_CxSRCADDR); ++ ++ chan->control_flags = S3C_DMACONTROL_SRC_INC | S3C_DMACONTROL_DEST_AXI_PERI ; ++ //chan->control_flags = hwcfg; ++ return 0; ++ ++ case S3C2410_DMASRC_HW: ++ /* source is peripheral : Peri-to-Mem ( Read from FIFO) */ ++ tmp = S3C_DMACONFIG_TCMASK | S3C_DMACONFIG_FLOWCTRL_PER2MEM | (chan->map->hw_addr.from) << ++ S3C_SRC_SHIFT | S3C_DMACONFIG_CHANNEL_ENABLE; ++ ++ chan->config_flags = tmp; ++ ++ /* TODO : Now, Scatter&Gather DMA NOT supported */ ++ dma_wrreg(chan, S3C_DMAC_CxLLI, 0); ++ ++ /* devaddr : Periperal address (source) */ ++ dma_wrreg(chan, S3C_DMAC_CxSRCADDR, devaddr); ++ ++ /* destination address : memory(buffer) address */ ++ chan->addr_reg = dma_regaddr(chan, S3C_DMAC_CxDESTADDR); ++ ++ chan->control_flags = S3C_DMACONTROL_DEST_INC | S3C_DMACONTROL_SRC_AXI_PERI; ++ //chan->control_flags = hwcfg; ++ ++ return 0; ++ ++ case S3C_DMA_MEM2MEM: ++ /* this is temporary for G3D */ ++ tmp = S3C_DMACONFIG_TCMASK | S3C_DMACONFIG_FLOWCTRL_MEM2MEM | S3C_DMACONFIG_CHANNEL_ENABLE; ++ ++ chan->config_flags = tmp; ++ ++ /* TODO : Now, Scatter&Gather DMA NOT YET supported */ ++ dma_wrreg(chan, S3C_DMAC_CxLLI, 0); ++ ++ /* devaddr : memory/onenand address (source) */ ++ dma_wrreg(chan, S3C_DMAC_CxSRCADDR, devaddr); ++ ++ /* destination address : memory(buffer) address */ ++ chan->addr_reg = dma_regaddr(chan, S3C_DMAC_CxDESTADDR); ++ ++ chan->control_flags |= (S3C_DMACONTROL_SRC_INC | S3C_DMACONTROL_DEST_AXI_PERI ++ | S3C_DMACONTROL_SBSIZE_4 | S3C_DMACONTROL_DBSIZE_4); ++ //chan->control_flags = hwcfg; ++ ++ return 0; ++ ++ case S3C_DMA_MEM2MEM_P: ++ /* source is memory : Memory-to-Mem ( Read/Write) */ ++ tmp = S3C_DMACONFIG_TCMASK | S3C_DMACONFIG_FLOWCTRL_MEM2MEM | S3C_DMACONFIG_CHANNEL_ENABLE; ++ ++ //if(chan->map->hw_addr.from == S3C_DMA0_ONENAND_RX) { ++ //tmp |= S3C_DMACONFIG_ONENANDMODESRC; ++ //} ++ ++ chan->config_flags = tmp; ++ ++ /* TODO : Now, Scatter&Gather DMA NOT YET supported */ ++ dma_wrreg(chan, S3C_DMAC_CxLLI, 0); ++ ++ /* devaddr : memory/onenand address (source) */ ++ dma_wrreg(chan, S3C_DMAC_CxSRCADDR, devaddr); ++ ++ /* destination address : memory(buffer) address */ ++ chan->addr_reg = dma_regaddr(chan, S3C_DMAC_CxDESTADDR); ++ ++ chan->control_flags |= (S3C_DMACONTROL_SRC_INC | S3C_DMACONTROL_DEST_INC ++ | S3C_DMACONTROL_SBSIZE_4 | S3C_DMACONTROL_DBSIZE_4); ++ //chan->control_flags = hwcfg; ++ ++ return 0; ++ ++ case S3C_DMA_PER2PER: ++ printk("Peripheral-to-Peripheral DMA NOT YET implemented !! \n"); ++ return -EINVAL; ++ ++ default: ++ printk(KERN_ERR "DMA CH :%d - invalid source type ()\n", channel); ++ printk("Unsupported DMA configuration from the device driver using DMA driver \n"); ++ return -EINVAL; ++ } ++ ++} ++ ++EXPORT_SYMBOL(s3c2410_dma_devconfig); ++ ++ ++/* ++ * s3c_dma_getposition ++ * returns the current transfer points for the dma source and destination ++ */ ++int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst) ++{ ++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); ++ ++ if (chan == NULL) ++ return -EINVAL; ++ ++ if (src != NULL) ++ *src = dma_rdreg(chan, S3C_DMAC_CxSRCADDR); ++ ++ if (dst != NULL) ++ *dst = dma_rdreg(chan, S3C_DMAC_CxDESTADDR); ++ ++ return 0; ++} ++ ++EXPORT_SYMBOL(s3c2410_dma_getposition); ++ ++ ++/* system device class */ ++#ifdef CONFIG_PM ++static int s3c_dma_suspend (struct sys_device *dev, pm_message_t state) ++{ ++ return 0; ++} ++ ++static int s3c_dma_resume (struct sys_device *dev) ++{ ++ return 0; ++} ++#else ++#define s3c_dma_suspend NULL ++#define s3c_dma_resume NULL ++#endif /* CONFIG_PM */ ++ ++struct sysdev_class dma_sysclass = { ++ .name = "s3c64xx-dma", ++ .suspend = s3c_dma_suspend, ++ .resume = s3c_dma_resume, ++}; ++ ++/* kmem cache implementation */ ++ ++static void s3c_dma_cache_ctor(void *p) ++{ ++ memset(p, 0, sizeof(struct s3c_dma_buf)); ++} ++ ++ ++void dma_test (int dcon_num, int channel) ++{ ++ int tmp; ++ ++ s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num]; ++ ++ dma_wrreg(dma_controller, S3C_DMAC_CONFIGURATION, S3C_DMA_CONTROLLER_ENABLE); ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CONFIGURATION); ++ printk("reg val %d\n", tmp); ++ dma_wrreg(dma_controller, S3C_DMAC_CCONFIGURATION(channel), 0x01); ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CCONFIGURATION(channel)); ++ ++ printk("reg conf %x\n", tmp); ++ dma_wrreg(dma_controller, S3C_DMAC_CCONTROL0(channel), 0x8ff02064); ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CCONTROL0(channel)); ++ printk("reg ctrl %x\n", tmp); ++} ++ ++ ++/* initialisation code */ ++ ++int __init s3c_dma_init(unsigned int channels, unsigned int irq, ++ unsigned int stride) ++{ ++ struct s3c2410_dma_chan *cp; ++ s3c_dma_controller_t *dconp; ++ int channel, controller; ++ int ret; ++ ++ printk("S3C DMA-pl080 Controller Driver, (c) 2006-2007 Samsung Electronics\n"); ++ ++ dma_channels = channels; ++ printk("Total %d DMA channels will be initialized.\n", channels); ++ ++ ret = sysdev_class_register(&dma_sysclass); ++ if (ret != 0) { ++ printk(KERN_ERR "dma sysclass registration failed.\n"); ++ goto err; ++ } ++ ++ dma_kmem = kmem_cache_create("dma_desc", sizeof(struct s3c_dma_buf), 0, ++ SLAB_HWCACHE_ALIGN, (void *)s3c_dma_cache_ctor); ++ ++ if (dma_kmem == NULL) { ++ printk(KERN_ERR "DMA failed to make kmem cache\n"); ++ ret = -ENOMEM; ++ goto err; ++ } ++ ++ for (controller = 0; controller < S3C_DMA_CONTROLLERS; controller++) { ++ dconp = &s3c_dma_cntlrs[controller]; ++ ++ memset(dconp, 0, sizeof(s3c_dma_controller_t)); ++ ++ if(controller < 2) { ++ dma_base = ioremap((S3C_PA_DMA + (controller * 0x100000)), 0x200); ++ if (dma_base == NULL) { ++ printk(KERN_ERR "DMA failed to ioremap register block\n"); ++ return -ENOMEM; ++ } ++ ++ /* dma controller's irqs are in order.. */ ++ dconp->irq = controller + IRQ_DMA0; ++ } ++ else { ++ dma_base = ioremap(((S3C_PA_DMA + 0x8B00000) + ((controller%2) * 0x100000)), 0x200); ++ if (dma_base == NULL) { ++ printk(KERN_ERR "SDMA failed to ioremap register block\n"); ++ return -ENOMEM; ++ } ++ ++ /* dma controller's irqs are in order.. */ ++ dconp->irq = (controller%2) + IRQ_SDMA0; ++ } ++ ++ dconp->number = controller; ++ dconp->regs = dma_base; ++ sh_printk("DMA controller : %d irq %d regs_base %x\n", dconp->number, dconp->irq, ++ dconp->regs); ++ } ++ ++ for (channel = 0; channel < channels; channel++) { ++ controller = channel / S3C_CHANNELS_PER_DMA; ++ cp = &s3c_dma_chans[channel]; ++ ++ memset(cp, 0, sizeof(struct s3c2410_dma_chan)); ++ ++ cp->dma_con = &s3c_dma_cntlrs[controller]; ++ ++ /* dma channel irqs are in order.. */ ++ cp->index = channel; ++ cp->number = channel%S3C_CHANNELS_PER_DMA; ++ ++ cp->irq = s3c_dma_cntlrs[controller].irq; ++ ++ cp->regs = s3c_dma_cntlrs[controller].regs + ((channel%S3C_CHANNELS_PER_DMA)*stride) + 0x100; ++ ++ /* point current stats somewhere */ ++ cp->stats = &cp->stats_store; ++ cp->stats_store.timeout_shortest = LONG_MAX; ++ ++ /* basic channel configuration */ ++ cp->load_timeout = 1 << 18; ++ ++ /* register system device */ ++ cp->dev.cls = &dma_sysclass; ++ cp->dev.id = channel; ++ //ret = sysdev_register(&cp->dev); ++ ++ sh_printk("DMA channel %d at %p, irq %d\n", cp->number, cp->regs, cp->irq); ++ } ++ ++ return 0; ++ ++err: ++ kmem_cache_destroy(dma_kmem); ++ iounmap(dma_base); ++ dma_base = NULL; ++ return ret; ++} ++ ++ ++ ++static inline int is_channel_valid(unsigned int channel) ++{ ++ return (channel & DMA_CH_VALID); ++} ++ ++static struct s3c_dma_order *dma_order; ++ ++ ++/* s3c_dma_map_channel() ++ * ++ * turn the virtual channel number into a real, and un-used hardware ++ * channel. ++ * ++ * first, try the dma ordering given to us by either the relevant ++ * dma code, or the board. Then just find the first usable free ++ * channel ++*/ ++ ++struct s3c2410_dma_chan *s3c_dma_map_channel(int channel) ++{ ++ struct s3c_dma_order_ch *ord = NULL; ++ struct s3c_dma_map *ch_map; ++ struct s3c2410_dma_chan *dmach; ++ int ch; ++ ++ if (dma_sel.map == NULL || channel > dma_sel.map_size) ++ return NULL; ++ ++ ch_map = dma_sel.map + channel; ++ ++ /* first, try the board mapping */ ++ ++ if (dma_order) { ++ ord = &dma_order->channels[channel]; ++ ++ for (ch = 0; ch < dma_channels; ch++) { ++ if (!is_channel_valid(ord->list[ch])) ++ continue; ++ ++ if (s3c_dma_chans[ord->list[ch]].in_use == 0) { ++ ch = ord->list[ch] & ~DMA_CH_VALID; ++ goto found; ++ } ++ } ++ ++ if (ord->flags & DMA_CH_NEVER) ++ return NULL; ++ } ++ ++ /* second, search the channel map for first free */ ++ ++ for (ch = 0; ch < dma_channels; ch++) { ++ if (!is_channel_valid(ch_map->channels[ch])) ++ continue; ++ ++ if (s3c_dma_chans[ch].in_use == 0) { ++ pr_debug("mapped channel %d to %d\n", channel, ch); ++ break; ++ } ++ } ++ ++ if (ch >= dma_channels) ++ return NULL; ++ ++ /* update our channel mapping */ ++ ++ found: ++ dmach = &s3c_dma_chans[ch]; ++ dma_chan_map[channel] = dmach; ++ ++ /* select the channel */ ++ (dma_sel.select)(dmach, ch_map); ++ ++ return dmach; ++} ++ ++static int s3c_dma_check_entry(struct s3c_dma_map *map, int ch) ++{ ++ unsigned long tmp = __raw_readl(S3C_SDMA_SEL); ++ ++ tmp |= map->sdma_sel; ++ __raw_writel(tmp, S3C_SDMA_SEL); ++ ++ return 0; ++} ++ ++int __init s3c_dma_init_map(struct s3c_dma_selection *sel) ++{ ++ struct s3c_dma_map *nmap; ++ size_t map_sz = sizeof(*nmap) * sel->map_size; ++ int ptr; ++ ++ nmap = kmalloc(map_sz, GFP_KERNEL); ++ if (nmap == NULL) ++ return -ENOMEM; ++ ++ memcpy(nmap, sel->map, map_sz); ++ memcpy(&dma_sel, sel, sizeof(*sel)); ++ ++ dma_sel.map = nmap; ++ ++ for (ptr = 0; ptr < sel->map_size; ptr++) ++ s3c_dma_check_entry(nmap+ptr, ptr); ++ ++ return 0; ++} ++ ++int __init s3c_dma_order_set(struct s3c_dma_order *ord) ++{ ++ struct s3c_dma_order *nord = dma_order; ++ ++ if (nord == NULL) ++ nord = kmalloc(sizeof(struct s3c_dma_order), GFP_KERNEL); ++ ++ if (nord == NULL) { ++ printk(KERN_ERR "no memory to store dma channel order\n"); ++ return -ENOMEM; ++ } ++ ++ dma_order = nord; ++ memcpy(nord, ord, sizeof(struct s3c_dma_order)); ++ return 0; ++} ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/dma-pl330-mcode.h linux-2.6.28.6/arch/arm/plat-s3c/dma-pl330-mcode.h +--- linux-2.6.28/arch/arm/plat-s3c/dma-pl330-mcode.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/dma-pl330-mcode.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,1145 @@ ++/* linux/arch/arm/plat-s3c/dma-pl330-mcode.h ++ * ++ * DMA PL330 microcode ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++/*------------------------------------------------------*/ ++/* Version : v1.1 */ ++/* Date last updated : Dec. 10, 2008 */ ++/*------------------------------------------------------*/ ++ ++ ++#define PL330_DMA_DEBUG ++#undef PL330_DMA_DEBUG ++ ++#ifdef PL330_DMA_DEBUG ++#define dma_debug(fmt...) printk( fmt) ++#else ++#define dma_debug(fmt...) ++#endif ++ ++#define print_warning(fmt...) printk( fmt) ++ ++#define PL330_P2M_DMA 0 ++#define PL330_M2P_DMA 1 ++#define PL330_M2M_DMA 2 ++#define PL330_P2P_DMA 3 ++ ++#define PL330_MAX_ITERATION_NUM 256 ++#define PL330_MAX_JUMPBACK_NUM 256 ++#define PL330_MAX_EVENT_NUM 32 ++#define PL330_MAX_PERIPHERAL_NUM 32 ++#define PL330_MAX_CHANNEL_NUM 8 ++ ++#define DMA_DBGSTATUS 0x0 ++#define DMA_DBGCMD 0x1 ++#define DMA_DBGINST0 0x2 ++#define DMA_DBGINST1 0x3 ++ ++#define memOutp8(addr, data) (*(volatile u8 *)(addr) = (data)) ++#define Outp32(addr, data) (*(volatile u32 *)(addr) = (data)) ++#define Inp32(addr) (*(volatile u32 *)(addr)) ++ ++ ++/* Parameter set for Channel Control Register */ ++typedef struct DMA_control ++{ ++ unsigned uSI :1 ; /* [0] Transfer size not count */ ++ unsigned uSBSize :3 ; /* [3:1] Source 1 transfer size */ ++ unsigned uSBLength :4 ; /* [7:4] Sourse burst len */ ++ unsigned uSProt :3 ; /* [10:8] Source Protection set 101b=5 */ ++ unsigned uSCache :3 ; /* [13:11] Source Cache control */ ++ unsigned uDI :1 ; /* [14] Destination increment */ ++ unsigned uDBSize :3 ; /* [17:15] Destination 1 transfer size */ ++ unsigned uDBLength :4 ; /* [21:18] Destination burst len */ ++ unsigned uDProt :3 ; /* [24:22] Source Protection set 101b=5 */ ++ unsigned uDCache :3 ; /* [27:25] Source Cache control */ ++ unsigned uESSize :4 ; /* [31:28] endian_swap_size */ ++} pl330_DMA_control_t; ++ ++ ++/* Parameter list for a DMA operation */ ++typedef struct DMA_parameters ++{ ++ unsigned long mDirection; /* DMA direction */ ++ unsigned long mPeriNum; /* DMA Peripheral number */ ++ unsigned long mSrcAddr; /* DMA source address */ ++ unsigned long mDstAddr; /* DMA destination address */ ++ unsigned long mTrSize; /* DMA Transfer size */ ++ pl330_DMA_control_t mControl; /* DMA control */ ++ unsigned long mIrqEnable; /* DMA Send IRQ */ ++ unsigned long mLoop; /* DMA Infinite Loop - 0(off) */ ++ unsigned long mBwJump; /* DMA backward relative offset */ ++ unsigned long mLastReq; /* The last DMA Req. */ ++} pl330_DMA_parameters_t; ++ ++ ++static void print_dma_param_info(pl330_DMA_parameters_t dma_param) ++{ ++ /* Parameter list for a DMA operation */ ++ dma_debug(" mDirection = %lu\n", dma_param.mDirection); ++ dma_debug(" mPeriNum = %lu\n", dma_param.mPeriNum); ++ dma_debug(" mSrcAddr = 0x%x\n", dma_param.mSrcAddr); ++ dma_debug(" mDstAddr = 0x%x\n", dma_param.mDstAddr); ++ dma_debug(" mTrSize = %lu\n", dma_param.mTrSize); ++ dma_debug(" mControl = 0x%x\n", dma_param.mControl); ++ dma_debug(" mIrqEnable = %lu\n", dma_param.mIrqEnable); ++ dma_debug(" mLoop = %lu\n", dma_param.mLoop); ++ dma_debug(" mBwJump = %lu\n", dma_param.mBwJump); ++ dma_debug(" mLastReq = %lu\n", dma_param.mLastReq); ++} ++ ++/*---------------------- Primitive functions -------------*/ ++/* When the DMAC is operating in real-time then you can only issue a limited subset of instructions as follows: ++ * DMAGO starts a DMA transaction using a DMA channel that you specify. ++ * DMASEV signals the occurrence of an event, or interrupt, using an event number that you specify. ++ * DMAKILL terminates a thread. ++ ++ * Prior to issuing DMAGO, you must ensure that the system memory contains a suitable ++ * program for the DMAC to execute, starting at the address that the DMAGO specifies. ++ */ ++ ++/* DMAMOV CCR, ... */ ++static int encodeDmaMoveChCtrl(u8 * mcode_ptr, u32 dmacon) ++{ ++ u8 uInsBytes[6]; ++ u32 i; ++ ++ uInsBytes[0] = (u8)(0xbc); ++ uInsBytes[1] = (u8)(0x1); ++ uInsBytes[2] = (u8)((dmacon>>0)&0xff); ++ uInsBytes[3] = (u8)((dmacon>>8)&0xff); ++ uInsBytes[4] = (u8)((dmacon>>16)&0xff); ++ uInsBytes[5] = (u8)((dmacon>>24)&0xff); ++ ++ for(i=0; i<6; i++) ++ { ++ memOutp8(mcode_ptr+i, uInsBytes[i]); ++ } ++ ++ return 6; ++} ++ ++/* DMAMOV SAR, uStAddr ++ * DMAMOV DAR, uStAddr */ ++static int encodeDmaMove(u8 * mcode_ptr, u8 uDir, u32 uStAddr) ++{ ++ u8 uInsBytes[6]; ++ u32 i; ++ ++ uInsBytes[0] = (u8)(0xbc); ++ uInsBytes[1] = (u8)(0x0|uDir); ++ uInsBytes[2] = (u8)((uStAddr>>0)&0xff); ++ uInsBytes[3] = (u8)((uStAddr>>8)&0xff); ++ uInsBytes[4] = (u8)((uStAddr>>16)&0xff); ++ uInsBytes[5] = (u8)((uStAddr>>24)&0xff); ++ ++ for(i=0; i<6; i++) ++ { ++ memOutp8(mcode_ptr+i, uInsBytes[i]); ++ } ++ ++ return 6; ++} ++ ++ ++/* DMALD, DMALDS, DMALDB */ ++static int encodeDmaLoad(u8 * mcode_ptr) ++{ ++ u8 bs=0; ++ u8 x=0; ++ u8 uInsBytes[1]; ++ u32 i; ++ ++ uInsBytes[0] = (u8)(0x04|(bs<<1)|(x<<0)); ++ ++ for(i=0; i<1; i++) ++ { ++ memOutp8(mcode_ptr+i, uInsBytes[i]); ++ } ++ ++ return 1; ++} ++ ++/* DMALDPS, DMALDPB (Load Peripheral) */ ++static int encodeDmaLoadPeri(u8 * mcode_ptr, u8 mPeriNum) ++{ ++ u8 bs; ++ u8 uInsBytes[2]; ++ u32 i; ++ u8 m_uBurstSz=1; ++ ++ if(mPeriNum > PL330_MAX_PERIPHERAL_NUM) { ++ print_warning("[%s] The peripheral number is too big ! : %d\n", __FUNCTION__, mPeriNum); ++ return 0; ++ } ++ ++ bs = (m_uBurstSz == 1) ? 0 : 1; // single -> 0, burst -> 1 ++ ++ uInsBytes[0] = (u8)(0x25|(bs<<1)); ++ uInsBytes[1] = (u8)(0x00|((mPeriNum&0x1f)<<3)); ++ ++ for(i=0; i<2; i++) ++ { ++ memOutp8(mcode_ptr+i, uInsBytes[i]); ++ } ++ ++ return 2; ++} ++ ++/* DMAST, DMASTS, DMASTB */ ++static int encodeDmaStore(u8 * mcode_ptr) ++{ ++ u8 bs=0; ++ u8 x=0; ++ u8 uInsBytes[1]; ++ u32 i; ++ ++ uInsBytes[0] = (u8)(0x08|(bs<<1)|(x<<0)); ++ ++ for(i=0; i<1; i++) ++ { ++ memOutp8(mcode_ptr+i, uInsBytes[i]); ++ } ++ ++ return 1; ++} ++ ++/* DMASTPS, DMASTPB (Store and notify Peripheral) */ ++static int encodeDmaStorePeri(u8 * mcode_ptr, u8 mPeriNum) ++{ ++ u8 bs; ++ u8 uInsBytes[2]; ++ u32 i; ++ u8 m_uBurstSz=1; ++ ++ if(mPeriNum > PL330_MAX_PERIPHERAL_NUM) { ++ print_warning("[%s] The peripheral number is too big ! : %d\n", __FUNCTION__, mPeriNum); ++ return 0; ++ } ++ ++ bs = (m_uBurstSz == 1) ? 0 : 1; /* single:0, burst:1 */ ++ ++ uInsBytes[0] = (u8)(0x29|(bs<<1)); ++ uInsBytes[1] = (u8)(0x00|((mPeriNum&0x1f)<<3)); ++ ++ for(i=0; i<2; i++) ++ { ++ memOutp8(mcode_ptr+i, uInsBytes[i]); ++ } ++ ++ return 2; ++} ++ ++/* DMASTZ */ ++static int encodeDmaStoreZero(u8 * mcode_ptr) ++{ ++ u8 uInsBytes[1]; ++ u32 i; ++ ++ uInsBytes[0] = (u8)(0x0c); ++ ++ for(i=0; i<1; i++) ++ { ++ memOutp8(mcode_ptr+i, uInsBytes[i]); ++ } ++ ++ return 1; ++} ++ ++/* DMALP */ ++static int encodeDmaLoop(u8 * mcode_ptr, u8 uLoopCnt, u8 uIteration) ++{ ++ u8 uInsBytes[2]; ++ u32 i; ++ ++ uInsBytes[0] = (u8)(0x20|(uLoopCnt<<1)); ++ uInsBytes[1] = (u8)(uIteration); ++ ++ for(i=0; i<2; i++) ++ { ++ memOutp8(mcode_ptr+i, uInsBytes[i]); ++ } ++ ++ return 2; ++ ++} ++ ++/* DMALPFE */ ++static int encodeDmaLoopForever(u8 * mcode_ptr, u8 uBwJump) ++{ ++ u8 bs=0; ++ u8 x=0; ++ u8 uInsBytes[2]; ++ u32 i; ++ ++ uInsBytes[0] = (u8)(0x28|(0<<4)|(0<<2)|(bs<<1)|x); ++ uInsBytes[1] = (u8)(uBwJump); ++ ++ for(i=0; i<2; i++) ++ { ++ memOutp8(mcode_ptr + i, uInsBytes[i]); ++ } ++ ++ return 2; ++} ++ ++ ++/* DMALPEND, DMALPENDS, DMALPENDB */ ++static int encodeDmaLoopEnd(u8 * mcode_ptr, u8 uLoopCnt, u8 uBwJump) ++{ ++ u8 bs=0; ++ u8 x=0; ++ u8 uInsBytes[2]; ++ u32 i; ++ ++ uInsBytes[0] = (u8)(0x38|(1<<4)|(uLoopCnt<<2)|(bs<<1)|x); ++ uInsBytes[1] = (u8)(uBwJump); ++ ++ for(i=0; i<2; i++) ++ { ++ memOutp8(mcode_ptr + i, uInsBytes[i]); ++ } ++ ++ return 2; ++} ++ ++/* DMAWFP, DMAWFPS, DMAWFPB (Wait For Peripheral) */ ++static int encodeDmaWaitForPeri(u8 * mcode_ptr, u8 mPeriNum) ++{ ++ u8 bs=0; ++ u8 p=0; ++ u8 uInsBytes[2]; ++ u32 i; ++ ++ if(mPeriNum > PL330_MAX_PERIPHERAL_NUM) { ++ print_warning("[%s] The peripheral number is too big ! : %d\n", __FUNCTION__, mPeriNum); ++ return 0; ++ } ++ ++ uInsBytes[0] = (u8)(0x30|(bs<<1)|p); ++ uInsBytes[1] = (u8)(0x00|((mPeriNum&0x1f)<<3)); ++ ++ for(i=0; i<2; i++) ++ { ++ memOutp8(mcode_ptr+i, uInsBytes[i]); ++ } ++ ++ return 2; ++} ++ ++/* DMAWFE (Wait For Event) : 0 ~ 31 */ ++static int encodeDmaWaitForEvent(u8 * mcode_ptr, u8 uEventNum) ++{ ++ u8 uInsBytes[2]; ++ u32 i; ++ ++ if(uEventNum > PL330_MAX_EVENT_NUM) { ++ print_warning("[%s] The uEventNum number is too big ! : %d\n", __FUNCTION__, uEventNum); ++ return 0; ++ } ++ ++ uInsBytes[0] = (u8)(0x36); ++ uInsBytes[1] = (u8)((uEventNum<<3)|0x2); /* for cache coherency, invalid is issued. */ ++ ++ for(i=0; i<2; i++) ++ { ++ memOutp8(mcode_ptr+i, uInsBytes[i]); ++ } ++ ++ return 2; ++} ++ ++/* DMAFLUSHP (Flush and notify Peripheral) */ ++static int encodeDmaFlushPeri(u8 * mcode_ptr, u8 mPeriNum) ++{ ++ u8 uInsBytes[2]; ++ u32 i; ++ ++ if(mPeriNum > PL330_MAX_PERIPHERAL_NUM) { ++ print_warning("[%s] The peripheral number is too big ! : %d\n", __FUNCTION__, mPeriNum); ++ return 0; ++ } ++ ++ uInsBytes[0] = (u8)(0x35); ++ uInsBytes[1] = (u8)(0x00|((mPeriNum&0x1f)<<3)); ++ ++ for(i=0; i<2; i++) ++ { ++ memOutp8(mcode_ptr+i, uInsBytes[i]); ++ } ++ ++ return 2; ++} ++ ++/* DMAEND */ ++static int encodeDmaEnd(u8 * mcode_ptr) ++{ ++ memOutp8(mcode_ptr, 0x00); ++ ++ return 1; ++} ++ ++/* DMAADDH (Add Halfword) */ ++static int encodeDmaAddHalfword(u8 * mcode_ptr, bool bSrcDir, u16 uStAddr) ++{ ++ u8 uDir = (bSrcDir) ? 0 : 1; /* src addr=0, dst addr=1 */ ++ u8 uInsBytes[3]; ++ u32 i; ++ ++ uInsBytes[0] = (u8)(0x54|(uDir<<1)); ++ uInsBytes[1] = (u8)((uStAddr>>0)&0xff); ++ uInsBytes[2] = (u8)((uStAddr>>8)&0xff); ++ ++ for(i=0; i<3; i++) ++ { ++ memOutp8(mcode_ptr+i, uInsBytes[i]); ++ } ++ ++ return 3; ++} ++ ++/* DMAKILL (Kill) */ ++static int encodeDmaKill(u8 * mcode_ptr) ++{ ++ u8 uInsBytes[1]; ++ u32 i; ++ uInsBytes[0] = (u8)(0x01); ++ ++ for(i=0; i<1; i++) ++ { ++ memOutp8(mcode_ptr+i, uInsBytes[i]); ++ } ++ ++ return 1; ++} ++ ++/* DMANOP (No operation) */ ++static int encodeDmaNop(u8 * mcode_ptr) ++{ ++ u8 uInsBytes[1]; ++ u32 i; ++ uInsBytes[0] = (u8)(0x18); ++ ++ for(i=0; i<1; i++) ++ { ++ memOutp8(mcode_ptr+i, uInsBytes[i]); ++ } ++ ++ return 1; ++} ++ ++ ++/* DMARMB (Read Memory Barrier) */ ++static int encodeDmaReadMemBarrier(u8 * mcode_ptr) ++{ ++ u8 uInsBytes[1]; ++ u32 i; ++ uInsBytes[0] = (u8)(0x12); ++ ++ for(i=0; i<1; i++) ++ { ++ memOutp8(mcode_ptr+i, uInsBytes[i]); ++ } ++ ++ return 1; ++} ++ ++/* DMASEV (Send Event) : 0 ~ 31 */ ++static int encodeDmaSendEvent(u8 * mcode_ptr, u8 uEventNum) ++{ ++ u8 uInsBytes[2]; ++ u32 i; ++ uInsBytes[0] = (u8)(0x34); ++ uInsBytes[1] = (u8)((uEventNum<<3)|0x0); ++ ++ if(uEventNum > PL330_MAX_EVENT_NUM) { ++ print_warning("[%s] Event number is too big ! : %d\n", __FUNCTION__, uEventNum); ++ return 0; ++ } ++ ++ for(i=0; i<2; i++) ++ { ++ memOutp8(mcode_ptr + i, uInsBytes[i]); ++ } ++ ++ return 2; ++} ++ ++ ++/* DMAWMB (Write Memory Barrier) */ ++static int encodeDmaWriteMemBarrier(u8 * mcode_ptr) ++{ ++ u8 uInsBytes[1]; ++ u32 i; ++ uInsBytes[0] = (u8)(0x13); ++ ++ for(i=0; i<1; i++) ++ { ++ memOutp8(mcode_ptr + i, uInsBytes[i]); ++ } ++ ++ return 1; ++} ++ ++/* DMAGO over DBGINST[0:1] registers */ ++static void encodeDmaGoOverDBGINST(u32 * mcode_ptr, u8 chanNum, u32 mbufAddr, u8 m_secureBit) ++{ ++ u32 x; ++ u8 uDmaGo; /* DMAGO instruction */ ++ ++ if(chanNum > PL330_MAX_CHANNEL_NUM) { ++ print_warning("[%s] Channel number is too big ! : %d\n", __FUNCTION__, chanNum); ++ return; ++ } ++ ++ do ++ { ++ x = Inp32(mcode_ptr+DMA_DBGSTATUS); ++ } while ((x&0x1)==0x1); ++ ++ uDmaGo = (m_secureBit==0) ? ++ (0xa0|(0<<1)) : /* secure mode : M2M DMA only */ ++ (0xa0|(1<<1)); /* non-secure mode : M2P/P2M DMA only */ ++ ++ Outp32(mcode_ptr+DMA_DBGINST0, (chanNum<<24)|(uDmaGo<<16)|(chanNum<<8)|(0<<0)); ++ Outp32(mcode_ptr+DMA_DBGINST1, mbufAddr); ++ Outp32(mcode_ptr+DMA_DBGCMD, 0); /* 0 : execute the instruction that the DBGINST0,1 registers contain */ ++ ++} ++ ++/* DMAKILL over DBGINST[0:1] registers - Stop a DMA channel */ ++static void encodeDmaKillChannelOverDBGINST(u32 * mcode_ptr, u8 chanNum) ++{ ++ u32 x; ++ ++ if(chanNum > PL330_MAX_CHANNEL_NUM) { ++ print_warning("[%s] Channel number is too big ! : %d\n", __FUNCTION__, chanNum); ++ return; ++ } ++ ++ do ++ { ++ x = Inp32(mcode_ptr+DMA_DBGSTATUS); ++ } while ((x&0x1)==0x1); ++ ++ Outp32(mcode_ptr+DMA_DBGINST0, (0<<24)|(1<<16)|(chanNum<<8)|(1<<0)); /* issue instruction by channel thread */ ++ Outp32(mcode_ptr+DMA_DBGINST1, 0); ++ Outp32(mcode_ptr+DMA_DBGCMD, 0); /* 0 : execute the instruction that the DBGINST0,1 registers contain */ ++ ++ do ++ { ++ x = Inp32(mcode_ptr+DMA_DBGSTATUS); ++ } while ((x&0x1)==0x1); ++} ++ ++/* DMAKILL over DBGINST[0:1] registers - Stop a DMA controller (stop all of the channels) */ ++static void encodeDmaKillDMACOverDBGINST(u32 * mcode_ptr) ++{ ++ u32 x; ++ ++ do ++ { ++ x = Inp32(mcode_ptr+DMA_DBGSTATUS); ++ } while ((x&0x1)==0x1); ++ ++ Outp32(mcode_ptr+DMA_DBGINST0, (0<<24)|(1<<16)|(0<<8)|(0<<0)); /* issue instruction by manager thread */ ++ Outp32(mcode_ptr+DMA_DBGINST1, 0); ++ Outp32(mcode_ptr+DMA_DBGCMD, 0); /* 0 : execute the instruction that the DBGINST0,1 registers contain */ ++ ++ do ++ { ++ x = Inp32(mcode_ptr+DMA_DBGSTATUS); ++ } while ((x&0x1)==0x1); ++} ++ ++/*----------------------------------------------------------*/ ++/* Wrapper functions */ ++/*----------------------------------------------------------*/ ++ ++/* config_DMA_Go_command ++ * - make DMA GO command into the Debug Instruction register 0/1 ++ * ++ * mcode_ptr the buffer for PL330 DMAGO micro code to be stored into ++ * chanNum the DMA channel number to be started ++ * mbufAddr the start address of the buffer containing PL330 DMA micro codes ++ */ ++static void config_DMA_GO_command(u32 * mcode_ptr, int chanNum, u32 mbufAddr, int secureMode) ++{ ++ dma_debug("%s entered - channel Num=%d\n", __FUNCTION__, chanNum); ++ dma_debug("mcode_ptr=0x%p, mbufAddr=0x%x, secureMode=%d\n\n", mcode_ptr, mbufAddr, secureMode); ++ encodeDmaGoOverDBGINST(mcode_ptr, (u8)chanNum, mbufAddr, (u8)secureMode); ++} ++ ++/* config_DMA_stop_channel ++ * - stop the DMA channel working on ++ * mcode_ptr the buffer for PL330 DMAKILL micro code to be stored into ++ * chanNum the DMA channel number to be stopped ++ */ ++static void config_DMA_stop_channel(u32 * mcode_ptr, int chanNum) ++{ ++ dma_debug("%s entered - channel Num=%d\n", __FUNCTION__, chanNum); ++ encodeDmaKillChannelOverDBGINST(mcode_ptr, (u8)chanNum); ++} ++ ++/* config_DMA_stop_controller ++ * - stop the DMA controller ++ * mcode_ptr the buffer for PL330 DMAKILL micro code to be stored into ++ */ ++static void config_DMA_stop_controller(u32 * mcode_ptr) ++{ ++ dma_debug("%s entered - mcode_ptr=0x%p\n", __FUNCTION__, mcode_ptr); ++ encodeDmaKillDMACOverDBGINST(mcode_ptr); ++} ++ ++ ++/* config_DMA_start_address ++ * - set the DMA start address ++ * ++ * mcode_ptr the pointer to the buffer for PL330 DMAMOVE micro code to be stored into ++ * uStAddr the DMA start address ++ */ ++static int config_DMA_start_address(u8 * mcode_ptr, int uStAddr) ++{ ++ dma_debug("%s entered - start addr=0x%x\n", __FUNCTION__, uStAddr); ++ return encodeDmaMove(mcode_ptr, 0, (u32)uStAddr); ++} ++ ++ ++/* config_DMA_destination_address ++ * - set the DMA destination address ++ * ++ * mcode_ptr the pointer to the buffer for PL330 DMAMOVE micro code to be stored into ++ * uStAddr the DMA destination address ++ */ ++static int config_DMA_destination_address(u8 * mcode_ptr, int uStAddr) ++{ ++ dma_debug("%s entered - destination addr=0x%x\n", __FUNCTION__, uStAddr); ++ return encodeDmaMove(mcode_ptr, 2, (u32)uStAddr); ++} ++ ++ ++/* config_DMA_control ++ * - set the burst length, burst size, source and destination increment/fixed field ++ * ++ * mcode_ptr the pointer to the buffer for PL330 DMAMOVE micro code to be stored into ++ * dmacon the value for the DMA channel control register ++ */ ++static int config_DMA_control(u8 * mcode_ptr, pl330_DMA_control_t dmacon) ++{ ++ dma_debug("%s entered - dmacon : 0x%p\n", __FUNCTION__, &dmacon); ++ return encodeDmaMoveChCtrl(mcode_ptr, *(u32 *)&dmacon); ++} ++ ++ ++/* config_DMA_transfer_remainder ++ * - set the transfer size of the remainder ++ * ++ * mcode_ptr the pointer to the buffer for PL330 DMA micro code to be stored into ++ * lcRemainder the remainder except for the LC-aligned transfers ++ * dma_param the parameter set for a DMA operation ++ */ ++static int config_DMA_transfer_remainder(u8 * mcode_ptr, int lcRemainder, pl330_DMA_parameters_t dma_param) ++{ ++ int mcode_size = 0, msize = 0; ++ int lc0 = 0, lcSize = 0, mLoopStart0 = 0, dmaSent = 0; ++ ++ dma_debug("%s entered - lcRemainder=%d\n", __FUNCTION__, lcRemainder); ++ ++ dmaSent = dma_param.mTrSize - lcRemainder; ++ ++ msize = config_DMA_start_address(mcode_ptr+mcode_size, dma_param.mSrcAddr+dmaSent); ++ mcode_size+= msize; ++ ++ msize = config_DMA_destination_address(mcode_ptr+mcode_size, dma_param.mDstAddr+dmaSent); ++ mcode_size+= msize; ++ ++ dma_param.mControl.uSBSize = 0x2; /* 4 bytes */ ++ dma_param.mControl.uSBLength = 0x0; /* 1 transfer */ ++ dma_param.mControl.uDBSize = 0x2; /* 4 bytes */ ++ dma_param.mControl.uDBLength = 0x0; /* 1 transfer */ ++ ++ msize = config_DMA_control(mcode_ptr+mcode_size, dma_param.mControl); ++ mcode_size+= msize; ++ ++ lcSize = (dma_param.mControl.uSBLength+1)*(1< (8*1024*1024)) { ++ print_warning("[%s] The chunk size is too big !: %lu\n", __FUNCTION__, dma_param.mTrSize); ++ return 0; ++ } ++ break; ++ ++ case PL330_M2P_DMA: ++ case PL330_P2M_DMA: ++ if(dma_param.mTrSize > (2*1024*1024)) { ++ print_warning("[%s] The chunk size is too big !: %lu\n", __FUNCTION__, dma_param.mTrSize); ++ return 0; ++ } ++ break; ++ ++ case PL330_P2P_DMA: ++ print_warning("[%s] P2P DMA selected !\n", __FUNCTION__); ++ break; ++ ++ default: ++ print_warning("[%s] Invaild DMA direction entered !\n", __FUNCTION__); ++ break; ++ } ++ ++ lcSize = (dma_param.mControl.uSBLength+1)*(1< PL330_MAX_ITERATION_NUM) { ++ lc1 = lc0/PL330_MAX_ITERATION_NUM; ++ dma_debug(" Inner loop : lc1=%d\n", lc1); ++ ++ if(lc1 <= PL330_MAX_ITERATION_NUM) { ++ msize = encodeDmaLoop(mcode_ptr+mcode_size, 1, lc1-1); ++ mcode_size+= msize; ++ mLoopStart1 = mcode_size; ++ ++ msize = encodeDmaLoop(mcode_ptr+mcode_size, 0, PL330_MAX_ITERATION_NUM-1); ++ mcode_size+= msize; ++ mLoopStart0 = mcode_size; ++ ++ switch(dma_param.mDirection) { ++ case PL330_M2M_DMA: ++ msize = encodeDmaLoad(mcode_ptr+mcode_size); ++ mcode_size+= msize; ++ msize = encodeDmaReadMemBarrier(mcode_ptr+mcode_size); ++ mcode_size+= msize; ++ msize = encodeDmaStore(mcode_ptr+mcode_size); ++ mcode_size+= msize; ++ break; ++ ++ case PL330_M2P_DMA: ++ msize = encodeDmaWaitForPeri(mcode_ptr+mcode_size, (u8)dma_param.mPeriNum); ++ mcode_size+= msize; ++ msize = encodeDmaLoad(mcode_ptr+mcode_size); ++ mcode_size+= msize; ++ msize = encodeDmaStorePeri(mcode_ptr+mcode_size, (u8)dma_param.mPeriNum); ++ mcode_size+= msize; ++ msize = encodeDmaFlushPeri(mcode_ptr+mcode_size, (u8)dma_param.mPeriNum); ++ mcode_size+= msize; ++ break; ++ ++ case PL330_P2M_DMA: ++ msize = encodeDmaWaitForPeri(mcode_ptr+mcode_size, (u8)dma_param.mPeriNum); ++ mcode_size+= msize; ++ msize = encodeDmaLoadPeri(mcode_ptr+mcode_size, (u8)dma_param.mPeriNum); ++ mcode_size+= msize; ++ msize = encodeDmaStore(mcode_ptr+mcode_size); ++ mcode_size+= msize; ++ msize = encodeDmaFlushPeri(mcode_ptr+mcode_size, (u8)dma_param.mPeriNum); ++ mcode_size+= msize; ++ break; ++ ++ case PL330_P2P_DMA: ++ print_warning("[%s] P2P DMA selected !\n", __FUNCTION__); ++ break; ++ ++ default: ++ print_warning("[%s] Invaild DMA direction selected !\n", __FUNCTION__); ++ break; ++ } ++ ++ msize = encodeDmaLoopEnd(mcode_ptr+mcode_size, 0, (u8)(mcode_size-mLoopStart0)); ++ mcode_size+= msize; ++ ++ msize = encodeDmaLoopEnd(mcode_ptr+mcode_size, 1, (u8)(mcode_size-mLoopStart1)); ++ mcode_size+= msize; ++ ++ lc0 = lc0 - (lc1*PL330_MAX_ITERATION_NUM); ++ } ++ else { ++ print_warning("[%s] The transfer size is over the limit (lc1=%d)\n", __FUNCTION__, lc1); ++ } ++ } ++ ++ if(lc0 > 0) { ++ dma_debug("Single loop : lc0=%d\n", lc0); ++ msize = encodeDmaLoop(mcode_ptr+mcode_size, 0, lc0-1); ++ mcode_size+= msize; ++ mLoopStart0 = mcode_size; ++ ++ switch(dma_param.mDirection) { ++ case PL330_M2M_DMA: ++ msize = encodeDmaLoad(mcode_ptr+mcode_size); ++ mcode_size+= msize; ++ msize = encodeDmaStore(mcode_ptr+mcode_size); ++ mcode_size+= msize; ++ break; ++ ++ case PL330_M2P_DMA: ++ msize = encodeDmaWaitForPeri(mcode_ptr+mcode_size, (u8)dma_param.mPeriNum); ++ mcode_size+= msize; ++ msize = encodeDmaLoad(mcode_ptr+mcode_size); ++ mcode_size+= msize; ++ msize = encodeDmaStorePeri(mcode_ptr+mcode_size, (u8)dma_param.mPeriNum); ++ mcode_size+= msize; ++ msize = encodeDmaFlushPeri(mcode_ptr+mcode_size, (u8)dma_param.mPeriNum); ++ mcode_size+= msize; ++ break; ++ ++ case PL330_P2M_DMA: ++ msize = encodeDmaWaitForPeri(mcode_ptr+mcode_size, (u8)dma_param.mPeriNum); ++ mcode_size+= msize; ++ msize = encodeDmaLoadPeri(mcode_ptr+mcode_size, (u8)dma_param.mPeriNum); ++ mcode_size+= msize; ++ msize = encodeDmaStore(mcode_ptr+mcode_size); ++ mcode_size+= msize; ++ msize = encodeDmaFlushPeri(mcode_ptr+mcode_size, (u8)dma_param.mPeriNum); ++ mcode_size+= msize; ++ break; ++ ++ case PL330_P2P_DMA: ++ print_warning("[%s] P2P DMA selected !\n", __FUNCTION__); ++ break; ++ ++ default: ++ break; ++ } ++ ++ msize = encodeDmaLoopEnd(mcode_ptr+mcode_size, 0, (u8)(mcode_size-mLoopStart0)); ++ mcode_size+= msize; ++ } ++ ++ if(lcRemainder !=0) { ++ msize = config_DMA_transfer_remainder(mcode_ptr+mcode_size, lcRemainder, dma_param); ++ mcode_size += msize; ++ } ++ ++ return mcode_size; ++} ++ ++ ++/* config_DMA_transfer_size_for_oneNAND ++ * - set the transfer size ++ * ++ * mcode_ptr the pointer to the buffer for PL330 DMA micro code to be stored into ++ * dma_param the parameter set for a DMA operation ++ */ ++#define ONENAND_PAGE_SIZE 2048 ++#define ONENAND_OOB_SIZE 64 ++#define ONENAND_PAGE_WITH_OOB (ONENAND_PAGE_SIZE+ONENAND_OOB_SIZE) ++#define MAX_ONENAND_PAGE_CNT 64 ++ ++static int config_DMA_transfer_size_for_oneNAND(u8 * mcode_ptr, pl330_DMA_parameters_t dma_param) ++{ ++ int i = 0, pageCnt =0; ++ int mcode_size = 0, msize = 0; ++ int lc0 = 0, lcSize = 0; ++ int mLoopStart = 0; ++ ++ dma_debug("%s entered\n", __FUNCTION__); ++ ++ if(dma_param.mTrSize > (MAX_ONENAND_PAGE_CNT*ONENAND_PAGE_WITH_OOB)) { ++ print_warning("[%s] The chunk size is too big !: %lu\n", __FUNCTION__, dma_param.mTrSize); ++ return 0; ++ } ++ ++ /* Buffer address on SDRAM */ ++ switch(dma_param.mDirection) { ++ case PL330_M2P_DMA: /* Write into oneNAND */ ++ msize = config_DMA_start_address(mcode_ptr+mcode_size, dma_param.mSrcAddr); ++ mcode_size+= msize; ++ break; ++ ++ case PL330_P2M_DMA: /* Read from oneNAND */ ++ msize = config_DMA_destination_address(mcode_ptr+mcode_size, dma_param.mDstAddr); ++ mcode_size+= msize; ++ break; ++ ++ case PL330_P2P_DMA: ++ case PL330_M2M_DMA: ++ default: ++ print_warning("[%s] Invaild DMA direction selected !\n", __FUNCTION__); ++ break; ++ } ++ ++ lcSize = (dma_param.mControl.uSBLength+1)*(1< ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "dma-pl330-mcode.h" ++ ++#undef pr_debug ++//#define dma_dbg ++ ++#ifdef dma_dbg ++#define pr_debug(fmt...) printk( fmt) ++#else ++#define pr_debug(fmt...) ++#endif ++ ++/* io map for dma */ ++static void __iomem *dma_base; ++static struct kmem_cache *dma_kmem; ++ ++static int dma_channels; ++struct s3c_dma_selection dma_sel; ++static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX]; ++ ++/* dma channel state information */ ++struct s3c2410_dma_chan s3c_dma_chans[S3C_DMA_CHANNELS]; ++s3c_dma_controller_t s3c_dma_cntlrs[S3C_DMA_CONTROLLERS]; ++ ++#define SIZE_OF_MICRO_CODES 512 ++#define PL330_NON_SECURE_DMA 1 ++#define PL330_SECURE_DMA 0 ++ ++#define BUF_MAGIC (0xcafebabe) ++ ++#define dmawarn(fmt...) printk(KERN_DEBUG fmt) ++ ++#define dma_regaddr(dcon, reg) ((dcon)->regs + (reg)) ++#define dma_wrreg(dcon, reg, val) writel((val), (dcon)->regs + (reg)) ++#define dma_rdreg(dcon, reg) readl((dcon)->regs + (reg)) ++ ++#define dbg_showregs(chan) do { } while(0) ++#define dbg_showchan(chan) do { } while(0) ++ ++void s3c_dma_dump(int dcon_num, int channel) ++{ ++ unsigned long tmp; ++ s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num]; ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_DS); ++ printk("%d dcon_num %d chnnel : DMA status %lx\n", dcon_num, channel, tmp); ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_DPC); ++ printk("%d dcon_num %d chnnel : DMA program counter %lx\n", dcon_num, channel, tmp); ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_INTEN); ++ printk("%d dcon_num %d chnnel : INT enable %lx\n", dcon_num, channel, tmp); ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_ES); ++ printk("%d dcon_num %d chnnel : Event status %lx\n", dcon_num, channel, tmp); ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_INTSTATUS); ++ printk("%d dcon_num %d chnnel : INT status %lx\n", dcon_num, channel, tmp); ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_FSC); ++ printk("%d dcon_num %d chnnel : Fault status %lx\n", dcon_num, channel, tmp); ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_FTC(channel)); ++ printk("%d dcon_num %d chnnel : Fault type %lx\n", dcon_num, channel, tmp); ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CS(channel)); ++ printk("%d dcon_num %d chnnel : Channel status %lx\n", dcon_num, channel, tmp); ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_CPC(channel)); ++ printk("%d dcon_num %d chnnel : Channel program counter %lx\n", dcon_num, channel, tmp); ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_SA(channel)); ++ printk("%d dcon_num %d chnnel : Source address %lx\n", dcon_num, channel, tmp); ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_DA(channel)); ++ printk("%d dcon_num %d chnnel : Destination address %lx\n", dcon_num, channel, tmp); ++} ++ ++ ++/* lookup_dma_channel ++ * ++ * change the dma channel number given into a real dma channel id ++ */ ++ ++static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel) ++{ ++ if (channel & DMACH_LOW_LEVEL) ++ return &s3c_dma_chans[channel & ~DMACH_LOW_LEVEL]; ++ else ++ return dma_chan_map[channel]; ++} ++ ++/* s3c_dma_stats_timeout ++ * ++ * Update DMA stats from timeout info ++ */ ++static void s3c_dma_stats_timeout(struct s3c_dma_stats * stats, int val) ++{ ++ if (stats == NULL) ++ return; ++ ++ if (val > stats->timeout_longest) ++ stats->timeout_longest = val; ++ if (val < stats->timeout_shortest) ++ stats->timeout_shortest = val; ++ ++ stats->timeout_avg += val; ++} ++ ++void s3c_enable_dmac(unsigned int dcon_num) ++{ ++ s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num]; ++ ++ start_DMA_controller(dma_regaddr(dma_controller, S3C_DMAC_DBGSTATUS)); ++} ++ ++void s3c_disable_dmac(unsigned int dcon_num) ++{ ++ s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num]; ++ ++ stop_DMA_controller(dma_regaddr(dma_controller, S3C_DMAC_DBGSTATUS)); ++} ++ ++void s3c_clear_interrupts (int dcon_num, int channel) ++{ ++ unsigned long tmp; ++ s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num]; ++ ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_INTCLR); ++ tmp |= (1 << channel); ++ dma_wrreg(dma_controller, S3C_DMAC_INTCLR, tmp); ++} ++ ++/* s3c_dma_waitforload ++ * ++ * wait for the DMA engine to load a buffer, and update the state accordingly ++ */ ++static int s3c_dma_waitforload(struct s3c2410_dma_chan *chan, int line) ++{ ++ int timeout = chan->load_timeout; ++ int took; ++ ++ pr_debug("%s channel number : %d\n", __FUNCTION__, chan->number); ++ ++ if (chan->load_state != S3C_DMALOAD_1LOADED) { ++ printk(KERN_ERR ++ "dma CH %d: s3c_dma_waitforload() called in loadstate %d from line %d\n", ++ chan->number, chan->load_state, line); ++ return 0; ++ } ++ ++ if (chan->stats != NULL) ++ chan->stats->loads++; ++ ++ while (--timeout > 0) { ++ //if ((dma_rdreg(chan->dma_con, S3C_DMAC_CS(chan->number))) & S3C_DMAC_CS_EXECUTING) { ++ took = chan->load_timeout - timeout; ++ s3c_dma_stats_timeout(chan->stats, took); ++ ++ switch (chan->load_state) { ++ case S3C_DMALOAD_1LOADED: ++ chan->load_state = S3C_DMALOAD_1RUNNING; ++ break; ++ ++ default: ++ printk(KERN_ERR ++ "dma CH %d: unknown load_state in s3c_dma_waitforload() %d\n", ++ chan->number, chan->load_state); ++ } ++ return 1; ++ //} ++ } ++ ++ if (chan->stats != NULL) { ++ chan->stats->timeout_failed++; ++ } ++ ++ return 0; ++} ++ ++ ++/* s3c_dma_loadbuffer ++ * ++ * load a buffer, and update the channel state ++ */ ++static inline int s3c_dma_loadbuffer(struct s3c2410_dma_chan *chan, ++ struct s3c_dma_buf *buf) ++{ ++ unsigned long tmp; ++ pl330_DMA_parameters_t dma_param; ++ struct s3c_dma_buf *firstbuf; ++ int bwJump = 0; ++ ++ memset(&dma_param, 0, sizeof(pl330_DMA_parameters_t)); ++ pr_debug("s3c_chan_loadbuffer: loading buffer %p (0x%08lx,0x%06x)\n", ++ buf, (unsigned long) buf->data, buf->size); ++ ++ if (buf == NULL) { ++ dmawarn("buffer is NULL\n"); ++ return -EINVAL; ++ } ++ ++ pr_debug("%s: DMA CCR - %08x\n", __FUNCTION__, chan->dcon); ++ pr_debug("%s: DMA Loop count - %08x\n", __FUNCTION__, (buf->size / chan->xfer_unit)); ++ ++ firstbuf = buf; ++ ++ do { ++ dma_param.mPeriNum = chan->config_flags; ++ dma_param.mDirection = chan->source; ++ ++ switch (dma_param.mDirection) { ++ case S3C2410_DMASRC_MEM: /* source is Memory : Mem-to-Peri (Write into FIFO) */ ++ dma_param.mSrcAddr = buf->data; ++ dma_param.mDstAddr = chan->dev_addr; ++ break; ++ ++ case S3C2410_DMASRC_HW: /* source is peripheral : Peri-to-Mem (Read from FIFO) */ ++ dma_param.mSrcAddr = chan->dev_addr; ++ dma_param.mDstAddr = buf->data; ++ break; ++ ++ case S3C_DMA_MEM2MEM: /* source & Destination : Mem-to-Mem */ ++ dma_param.mSrcAddr = chan->dev_addr; ++ dma_param.mDstAddr = buf->data; ++ break; ++ ++ case S3C_DMA_MEM2MEM_SET: /* source & Destination : Mem-to-Mem */ ++ dma_param.mDirection = S3C_DMA_MEM2MEM; ++ dma_param.mSrcAddr = chan->dev_addr; ++ dma_param.mDstAddr = buf->data; ++ break; ++ ++ case S3C_DMA_PER2PER: ++ default: ++ printk("Peripheral-to-Peripheral DMA NOT YET implemented !! \n"); ++ return -EINVAL; ++ } ++ ++ dma_param.mTrSize = buf->size; ++ ++ dma_param.mLoop = 0; ++ dma_param.mControl = *(pl330_DMA_control_t *) &chan->dcon; ++ ++ chan->next = buf->next; ++ buf = chan->next; ++ ++ if(buf==NULL) { ++ firstbuf->next = NULL; ++ dma_param.mLastReq = 1; ++ dma_param.mIrqEnable = 1; ++ } ++ else { ++ dma_param.mLastReq = 0; ++ dma_param.mIrqEnable = 0; ++ } ++ ++ bwJump += setup_DMA_channel(((u8 *)firstbuf->mcptr_cpu)+bwJump, dma_param, chan->number); ++ pr_debug("%s: DMA bwJump - %d\n", __FUNCTION__, bwJump); ++ ++ }while(buf != NULL); ++ ++ if(dma_param.mIrqEnable) { ++ tmp = dma_rdreg(chan->dma_con, S3C_DMAC_INTEN); ++ tmp |= (1 << chan->number); ++ dma_wrreg(chan->dma_con, S3C_DMAC_INTEN, tmp); ++ } ++ ++ /* update the state of the channel */ ++ ++ switch (chan->load_state) { ++ case S3C_DMALOAD_NONE: ++ chan->load_state = S3C_DMALOAD_1LOADED; ++ break; ++ ++ case S3C_DMALOAD_1RUNNING: ++ chan->load_state = S3C_DMALOAD_1LOADED_1RUNNING; ++ break; ++ ++ default: ++ dmawarn("dmaload: unknown state %d in loadbuffer\n", chan->load_state); ++ break; ++ } ++ ++ return 0; ++} ++ ++ ++/* s3c_dma_call_op ++ * ++ * small routine to call the o routine with the given op if it has been ++ * registered ++ */ ++static void s3c_dma_call_op(struct s3c2410_dma_chan * chan, enum s3c_chan_op op) ++{ ++ if (chan->op_fn != NULL) { ++ (chan->op_fn) (chan, op); ++ } ++} ++ ++/* s3c_dma_buffdone ++ * ++ * small wrapper to check if callback routine needs to be called, and ++ * if so, call it ++ */ ++static inline void s3c_dma_buffdone(struct s3c2410_dma_chan * chan, ++ struct s3c_dma_buf * buf, ++ enum s3c2410_dma_buffresult result) ++{ ++ pr_debug("callback_fn will be called=%p, buf=%p, id=%p, size=%d, result=%d\n", ++ chan->callback_fn, buf, buf->id, buf->size, result); ++ ++ if (chan->callback_fn != NULL) { ++ (chan->callback_fn) (chan, buf->id, buf->size, result); ++ } ++} ++ ++/* s3c_dma_start ++ * ++ * start a dma channel going ++ */ ++static int s3c_dma_start(struct s3c2410_dma_chan *chan) ++{ ++ unsigned long flags; ++ ++ pr_debug("s3c_start_dma: channel number=%d, index=%d\n", chan->number, chan->index); ++ ++ local_irq_save(flags); ++ ++ if (chan->state == S3C_DMA_RUNNING) { ++ pr_debug("s3c_start_dma: already running (%d)\n", chan->state); ++ local_irq_restore(flags); ++ return 0; ++ } ++ ++ chan->state = S3C_DMA_RUNNING; ++ ++ /* check wether there is anything to load, and if not, see ++ * if we can find anything to load ++ */ ++ ++ if (chan->load_state == S3C_DMALOAD_NONE) { ++ if (chan->next == NULL) { ++ printk(KERN_ERR "dma CH %d: dcon_num has nothing loaded\n", chan->number); ++ chan->state = S3C_DMA_IDLE; ++ local_irq_restore(flags); ++ return -EINVAL; ++ } ++ s3c_dma_loadbuffer(chan, chan->next); ++ } ++ ++ dbg_showchan(chan); ++ ++ /* enable the channel */ ++ ++ if (!chan->irq_enabled) { ++ enable_irq(chan->irq); ++ chan->irq_enabled = 1; ++ } ++ ++ start_DMA_channel(dma_regaddr(chan->dma_con, S3C_DMAC_DBGSTATUS), chan->number, ++ chan->curr->mcptr, PL330_NON_SECURE_DMA); ++ ++ /* Start the DMA operation on Peripheral */ ++ s3c_dma_call_op(chan, S3C2410_DMAOP_START); ++ ++ dbg_showchan(chan); ++ ++ local_irq_restore(flags); ++ return 0; ++} ++ ++ ++/* s3c_dma_canload ++ * ++ * work out if we can queue another buffer into the DMA engine ++ */ ++ ++ ++static int s3c_dma_canload(struct s3c2410_dma_chan * chan) ++{ ++ if (chan->load_state == S3C_DMALOAD_NONE || chan->load_state == S3C_DMALOAD_1RUNNING) ++ return 1; ++ ++ return 0; ++} ++ ++ ++ ++/* s3c2410_dma_enqueue ++ * ++ * queue an given buffer for dma transfer. ++ * ++ * id the device driver's id information for this buffer ++ * data the physical address of the buffer data ++ * size the size of the buffer in bytes ++ * ++ * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART ++ * is checked, and if set, the channel is started. If this flag isn't set, ++ * then an error will be returned. ++ * ++ * It is possible to queue more than one DMA buffer onto a channel at ++ * once, and the code will deal with the re-loading of the next buffer ++ * when necessary. ++ */ ++int s3c2410_dma_enqueue(unsigned int channel, void *id, ++ dma_addr_t data, int size) ++{ ++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); ++ struct s3c_dma_buf *buf; ++ unsigned long flags; ++ ++ pr_debug("%s: id=%p, data=%08x, size=%d\n", __FUNCTION__, id, (unsigned int) data, size); ++ ++ buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC); ++ if (buf == NULL) { ++ printk(KERN_ERR "dma <%d> no memory for buffer\n", channel); ++ return -ENOMEM; ++ } ++ ++ pr_debug("%s: new buffer %p\n", __FUNCTION__, buf); ++ ++ buf->next = NULL; ++ buf->data = buf->ptr = data; ++ buf->size = size; ++ buf->id = id; ++ buf->magic = BUF_MAGIC; ++ ++ local_irq_save(flags); ++ ++ buf->mcptr_cpu = dma_alloc_coherent(NULL, SIZE_OF_MICRO_CODES, &buf->mcptr, GFP_ATOMIC); ++ ++ if (buf->mcptr_cpu == NULL) { ++ printk(KERN_ERR "%s: failed to allocate memory for micro codes\n", __FUNCTION__); ++ return -ENOMEM; ++ } ++ ++ if (chan->curr == NULL) { ++ /* we've got nothing loaded... */ ++ pr_debug("%s: buffer %p queued onto empty channel\n", __FUNCTION__, buf); ++ ++ chan->curr = buf; ++ chan->end = buf; ++ chan->next = NULL; ++ } else { ++ pr_debug("dma CH %d: %s: buffer %p queued onto non-empty channel\n", ++ chan->number, __FUNCTION__, buf); ++ ++ if (chan->end == NULL) /* In case of flushing */ ++ pr_debug("dma CH %d: %s: %p not empty, and chan->end==NULL?\n", ++ chan->number, __FUNCTION__, chan); ++ else { ++ chan->end->next = buf; ++ chan->end = buf; ++ } ++ } ++ ++ /* if necessary, update the next buffer field */ ++ if (chan->next == NULL) ++ chan->next = buf; ++ ++ /* check to see if we can load a buffer */ ++ if (chan->state == S3C_DMA_RUNNING) { ++ if (chan->load_state == S3C_DMALOAD_1LOADED && 1) { ++ if (s3c_dma_waitforload(chan, __LINE__) == 0) { ++ printk(KERN_ERR "dma CH %d: loadbuffer:" ++ "timeout loading buffer\n", chan->number); ++ dbg_showchan(chan); ++ local_irq_restore(flags); ++ return -EINVAL; ++ } ++ } ++ ++ } else if (chan->state == S3C_DMA_IDLE) { ++ if (chan->flags & S3C2410_DMAF_AUTOSTART) { ++ s3c2410_dma_ctrl(channel, S3C2410_DMAOP_START); ++ } else { ++ pr_debug("loading onto stopped channel\n"); ++ } ++ } ++ ++ local_irq_restore(flags); ++ return 0; ++} ++EXPORT_SYMBOL(s3c2410_dma_enqueue); ++ ++static inline void s3c_dma_freebuf(struct s3c_dma_buf * buf) ++{ ++ int magicok = (buf->magic == BUF_MAGIC); ++ ++ buf->magic = -1; ++ ++ if (magicok) { ++ local_irq_enable(); ++ dma_free_coherent(NULL, SIZE_OF_MICRO_CODES, buf->mcptr_cpu, buf->mcptr); ++ local_irq_disable(); ++ ++ kmem_cache_free(dma_kmem, buf); ++ } else { ++ printk("s3c_dma_freebuf: buff %p with bad magic\n", buf); ++ } ++} ++ ++/* s3c_dma_lastxfer ++ * ++ * called when the system is out of buffers, to ensure that the channel ++ * is prepared for shutdown. ++ */ ++static inline void s3c_dma_lastxfer(struct s3c2410_dma_chan *chan) ++{ ++ pr_debug("DMA CH %d: s3c_dma_lastxfer: load_state %d\n", chan->number, chan->load_state); ++ ++ switch (chan->load_state) { ++ case S3C_DMALOAD_NONE: ++ pr_debug("DMA CH %d: s3c_dma_lastxfer: load_state : S3C2410_DMALOAD_NONE %d\n", chan->number); ++ break; ++ ++ case S3C_DMALOAD_1LOADED: ++ if (s3c_dma_waitforload(chan, __LINE__) == 0) { ++ /* flag error? */ ++ printk(KERN_ERR "dma CH %d: timeout waiting for load\n", chan->number); ++ return; ++ } ++ break; ++ ++ default: ++ pr_debug("dma CH %d: lastxfer: unhandled load_state %d with no next", ++ chan->number, chan->load_state); ++ return; ++ ++ } ++ ++} ++ ++ ++#define dmadbg2(x...) ++ ++static irqreturn_t s3c_dma_irq(int irq, void *devpw) ++{ ++ unsigned int channel = 0, dcon_num, i; ++ unsigned long tmp; ++ s3c_dma_controller_t *dma_controller = (s3c_dma_controller_t *) devpw; ++ ++ struct s3c2410_dma_chan *chan=NULL; ++ struct s3c_dma_buf *buf; ++ ++ dcon_num = dma_controller->number; ++ tmp = dma_rdreg(dma_controller, S3C_DMAC_INTSTATUS); ++ pr_debug("# s3c_dma_irq: IRQ status : 0x%x\n", tmp); ++ ++ for (i = 0; i < S3C_CHANNELS_PER_DMA; i++) { ++ if (tmp & 0x01) { ++ ++ pr_debug("# DMAC %d: requestor %d\n", dcon_num, i); ++ ++ channel = i; ++ chan = &s3c_dma_chans[channel + dcon_num * S3C_CHANNELS_PER_DMA]; ++ pr_debug("# DMA CH:%d, index:%d load_state:%d\n", chan->number, chan->index, chan->load_state); ++ ++ buf = chan->curr; ++ ++ dbg_showchan(chan); ++ ++ /* modify the channel state */ ++ switch (chan->load_state) { ++ case S3C_DMALOAD_1RUNNING: ++ /* TODO - if we are running only one buffer, we probably ++ * want to reload here, and then worry about the buffer ++ * callback */ ++ ++ chan->load_state = S3C_DMALOAD_NONE; ++ break; ++ ++ case S3C_DMALOAD_1LOADED: ++ /* iirc, we should go back to NONE loaded here, we ++ * had a buffer, and it was never verified as being ++ * loaded. ++ */ ++ ++ chan->load_state = S3C_DMALOAD_NONE; ++ break; ++ ++ case S3C_DMALOAD_1LOADED_1RUNNING: ++ /* we'll worry about checking to see if another buffer is ++ * ready after we've called back the owner. This should ++ * ensure we do not wait around too long for the DMA ++ * engine to start the next transfer ++ */ ++ ++ chan->load_state = S3C_DMALOAD_1LOADED; ++ break; ++ ++ case S3C_DMALOAD_NONE: ++ printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n", ++ chan->number); ++ break; ++ ++ default: ++ printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n", ++ chan->number, chan->load_state); ++ break; ++ } ++ ++ if (buf != NULL) { ++ /* update the chain to make sure that if we load any more ++ * buffers when we call the callback function, things should ++ * work properly */ ++ ++ chan->curr = buf->next; ++ buf->next = NULL; ++ ++ if (buf->magic != BUF_MAGIC) { ++ printk(KERN_ERR "dma CH %d: %s: buf %p incorrect magic\n", ++ chan->number, __FUNCTION__, buf); ++ goto next_channel; ++ } ++ ++ s3c_dma_buffdone(chan, buf, S3C2410_RES_OK); ++ ++ /* free resouces */ ++ s3c_dma_freebuf(buf); ++ } else { ++ } ++ ++ /* only reload if the channel is still running... our buffer done ++ * routine may have altered the state by requesting the dma channel ++ * to stop or shutdown... */ ++ ++ if (chan->next != NULL && chan->state != S3C_DMA_IDLE) { ++ unsigned long flags; ++ ++ switch (chan->load_state) { ++ case S3C_DMALOAD_1RUNNING: ++ /* don't need to do anything for this state */ ++ break; ++ ++ case S3C_DMALOAD_NONE: ++ /* can load buffer immediately */ ++ break; ++ ++ case S3C_DMALOAD_1LOADED: ++ if (s3c_dma_waitforload(chan, __LINE__) == 0) { ++ /* flag error? */ ++ printk(KERN_ERR "dma CH %d: timeout waiting for load\n", ++ chan->number); ++ goto next_channel; ++ } ++ ++ break; ++ ++ case S3C_DMALOAD_1LOADED_1RUNNING: ++ goto next_channel; ++ ++ default: ++ printk(KERN_ERR "dma CH %d: unknown load_state in irq, %d\n", ++ chan->number, chan->load_state); ++ goto next_channel; ++ } ++ ++ local_irq_save(flags); ++ s3c_dma_loadbuffer(chan, chan->next); ++ start_DMA_channel(dma_regaddr(chan->dma_con, S3C_DMAC_DBGSTATUS), chan->number, ++ chan->curr->mcptr, PL330_NON_SECURE_DMA); ++ ++ local_irq_restore(flags); ++ ++ } else { ++ s3c_dma_lastxfer(chan); ++ ++ /* see if we can stop this channel.. */ ++ if (chan->load_state == S3C_DMALOAD_NONE) { ++ pr_debug("# DMA CH %d - (index:%d): end of transfer, stopping channel (%ld)\n", ++ chan->number, chan->index, jiffies); ++ s3c2410_dma_ctrl(chan->index | DMACH_LOW_LEVEL, S3C2410_DMAOP_STOP); ++ } ++ } ++ } ++ ++next_channel: ++ tmp >>= 1; ++ ++ } ++ ++ s3c_clear_interrupts(chan->dma_con->number, chan->number); ++ ++ return IRQ_HANDLED; ++} ++ ++static struct s3c2410_dma_chan *s3c_dma_map_channel(int channel); ++ ++/* s3c2410_dma_request ++ * ++ * get control of an dma channel ++*/ ++ ++int s3c2410_dma_request(unsigned int channel, ++ struct s3c2410_dma_client *client, ++ void *dev) ++{ ++ struct s3c2410_dma_chan *chan; ++ unsigned long flags; ++ int err; ++ ++ pr_debug("DMA CH %d: s3c2410_request_dma: client=%s, dev=%p\n", ++ channel, client->name, dev); ++ ++ local_irq_save(flags); ++ ++ chan = s3c_dma_map_channel(channel); ++ if (chan == NULL) { ++ local_irq_restore(flags); ++ return -EBUSY; ++ } ++ ++ dbg_showchan(chan); ++ ++ chan->client = client; ++ chan->in_use = 1; ++ ++ chan->dma_con->in_use++; ++ ++ if (!chan->irq_claimed) { ++ pr_debug("DMA CH %d: %s : requesting irq %d\n", ++ channel, __FUNCTION__, chan->irq); ++ ++ chan->irq_claimed = 1; ++ local_irq_restore(flags); ++ ++ err = request_irq(chan->irq, s3c_dma_irq, IRQF_DISABLED, ++ client->name, (void *) chan->dma_con); ++ ++ local_irq_save(flags); ++ ++ if (err) { ++ chan->in_use = 0; ++ chan->irq_claimed = 0; ++ chan->dma_con->in_use--; ++ local_irq_restore(flags); ++ ++ printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n", ++ client->name, chan->irq, chan->number); ++ return err; ++ } ++ ++ chan->irq_enabled = 1; ++ ++ /* enable the main dma.. this can be disabled ++ * when main channel use count is 0 */ ++ s3c_enable_dmac(chan->dma_con->number); ++ } ++ ++ s3c_clear_interrupts(chan->dma_con->number, chan->number); ++ local_irq_restore(flags); ++ ++ /* need to setup */ ++ ++ pr_debug("%s: channel initialised, %p, number:%d, index:%d\n", __FUNCTION__, chan, chan->number, chan->index); ++ ++ return 0; ++} ++EXPORT_SYMBOL(s3c2410_dma_request); ++ ++/* s3c2410_dma_free ++ * ++ * release the given channel back to the system, will stop and flush ++ * any outstanding transfers, and ensure the channel is ready for the ++ * next claimant. ++ * ++ * Note, although a warning is currently printed if the freeing client ++ * info is not the same as the registrant's client info, the free is still ++ * allowed to go through. ++ */ ++int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client) ++{ ++ unsigned long flags; ++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); ++ pr_debug("%s: DMA channel %d will be stopped\n", __FUNCTION__, chan->number); ++ ++ if (chan == NULL) ++ return -EINVAL; ++ ++ local_irq_save(flags); ++ ++ if (chan->client != client) { ++ printk(KERN_WARNING ++ "DMA CH %d: possible free from different client (channel %p, passed %p)\n", ++ channel, chan->client, client); ++ } ++ ++ /* sort out stopping and freeing the channel */ ++ ++ if (chan->state != S3C_DMA_IDLE) { ++ pr_debug("%s: need to stop dma channel %p\n", __FUNCTION__, chan); ++ ++ /* possibly flush the channel */ ++ s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP); ++ } ++ ++ chan->client = NULL; ++ chan->in_use = 0; ++ ++ chan->dma_con->in_use--; ++ ++ if (chan->irq_claimed) ++ free_irq(chan->irq, (void *)chan->dma_con); ++ ++ chan->irq_claimed = 0; ++ ++ if (!(channel & DMACH_LOW_LEVEL)) ++ dma_chan_map[channel] = NULL; ++ ++ local_irq_restore(flags); ++ ++ return 0; ++} ++EXPORT_SYMBOL(s3c2410_dma_free); ++ ++ ++static int s3c_dma_dostop(struct s3c2410_dma_chan *chan) ++{ ++ unsigned long flags; ++ ++ pr_debug("%s: DMA Channel No : %d\n", __FUNCTION__, chan->number); ++ ++ dbg_showchan(chan); ++ ++ local_irq_save(flags); ++ ++ s3c_dma_call_op(chan, S3C2410_DMAOP_STOP); ++ ++ stop_DMA_channel(dma_regaddr(chan->dma_con, S3C_DMAC_DBGSTATUS), chan->number); ++ ++ chan->state = S3C_DMA_IDLE; ++ chan->load_state = S3C_DMALOAD_NONE; ++ ++ local_irq_restore(flags); ++ ++ return 0; ++} ++ ++static void s3c_dma_showchan(struct s3c2410_dma_chan * chan) ++{ ++ ++} ++ ++/* s3c_dma_flush ++ * ++ * stop the channel, and remove all current and pending transfers ++ */ ++ ++void s3c_waitforstop(struct s3c2410_dma_chan *chan) ++{ ++ ++} ++ ++static int s3c_dma_flush(struct s3c2410_dma_chan *chan) ++{ ++ struct s3c_dma_buf *buf, *next; ++ unsigned long flags; ++ ++ pr_debug("%s:\n", __FUNCTION__); ++ ++ local_irq_save(flags); ++ ++ s3c_dma_showchan(chan); ++ ++ if (chan->state != S3C_DMA_IDLE) { ++ pr_debug("%s: stopping channel...\n", __FUNCTION__); ++ s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP); ++ } ++ ++ buf = chan->curr; ++ if (buf == NULL) ++ buf = chan->next; ++ ++ chan->curr = chan->next = chan->end = NULL; ++ chan->load_state = S3C_DMALOAD_NONE; ++ ++ if (buf != NULL) { ++ for (; buf != NULL; buf = next) { ++ next = buf->next; ++ ++ pr_debug("%s: free buffer %p, next %p\n", __FUNCTION__, buf, buf->next); ++ ++ s3c_dma_buffdone(chan, buf, S3C2410_RES_ABORT); ++ s3c_dma_freebuf(buf); ++ } ++ } ++ //s3c_dma_waitforstop(chan); ++ ++ s3c_dma_showchan(chan); ++ local_irq_restore(flags); ++ ++ return 0; ++} ++ ++int s3c_dma_started(struct s3c2410_dma_chan *chan) ++{ ++ unsigned long flags; ++ ++ local_irq_save(flags); ++ ++ dbg_showchan(chan); ++ ++ /* if we've only loaded one buffer onto the channel, then chec ++ * to see if we have another, and if so, try and load it so when ++ * the first buffer is finished, the new one will be loaded onto ++ * the channel */ ++ ++ if (chan->next != NULL) { ++ if (chan->load_state == S3C_DMALOAD_1LOADED) { ++ ++ if (s3c_dma_waitforload(chan, __LINE__) == 0) { ++ pr_debug("%s: buff not yet loaded, no more todo\n", ++ __FUNCTION__); ++ } else { ++ chan->load_state = S3C_DMALOAD_1RUNNING; ++ s3c_dma_loadbuffer(chan, chan->next); ++ } ++ ++ } else if (chan->load_state == S3C_DMALOAD_1RUNNING) { ++ s3c_dma_loadbuffer(chan, chan->next); ++ } ++ } ++ ++ local_irq_restore(flags); ++ ++ return 0; ++ ++} ++ ++int s3c2410_dma_ctrl(dmach_t channel, enum s3c_chan_op op) ++{ ++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); ++ ++ if (chan == NULL) ++ return -EINVAL; ++ ++ switch (op) { ++ case S3C2410_DMAOP_START: ++ return s3c_dma_start(chan); ++ ++ case S3C2410_DMAOP_STOP: ++ return s3c_dma_dostop(chan); ++ ++ case S3C2410_DMAOP_PAUSE: ++ case S3C2410_DMAOP_RESUME: ++ return -ENOENT; ++ ++ case S3C2410_DMAOP_FLUSH: ++ return s3c_dma_flush(chan); ++ ++ case S3C2410_DMAOP_STARTED: ++ return s3c_dma_started(chan); ++ ++ case S3C2410_DMAOP_TIMEOUT: ++ return 0; ++ ++ } ++ ++ printk("Invalid operation entered \n"); ++ return -ENOENT; /* unknown, don't bother */ ++} ++EXPORT_SYMBOL(s3c2410_dma_ctrl); ++ ++ ++/* s3c2410_dma_config ++ * ++ * xfersize: size of unit in bytes (1,2,4) ++ * dcon: base value of the DCONx register ++ */ ++int s3c2410_dma_config(dmach_t channel, ++ int xferunit, ++ int dcon) ++{ ++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); ++ ++ pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n", ++ __FUNCTION__, channel, xferunit, dcon); ++ ++ if (chan == NULL) ++ return -EINVAL; ++ ++ pr_debug("%s: Initial dcon is %08x\n", __FUNCTION__, dcon); ++ ++ dcon |= chan->dcon & dma_sel.dcon_mask; ++ ++ pr_debug("%s: New dcon is %08x\n", __FUNCTION__, dcon); ++ ++ switch (xferunit) { ++ case 1: ++ dcon |= S3C_DMACONTROL_SRC_WIDTH_BYTE; ++ dcon |= S3C_DMACONTROL_DEST_WIDTH_BYTE; ++ break; ++ ++ case 2: ++ dcon |= S3C_DMACONTROL_SRC_WIDTH_HWORD; ++ dcon |= S3C_DMACONTROL_DEST_WIDTH_HWORD; ++ break; ++ ++ case 4: ++ dcon |= S3C_DMACONTROL_SRC_WIDTH_WORD; ++ dcon |= S3C_DMACONTROL_DEST_WIDTH_WORD; ++ break; ++ ++ case 8: ++ dcon |= S3C_DMACONTROL_SRC_WIDTH_DWORD; ++ dcon |= S3C_DMACONTROL_DEST_WIDTH_DWORD; ++ break; ++ ++ default: ++ printk("%s: Bad transfer size %d\n", __FUNCTION__, xferunit); ++ return -EINVAL; ++ } ++ ++ pr_debug("%s: DMA Channel control : %08x\n", __FUNCTION__, dcon); ++ ++ dcon |= chan->control_flags; ++ pr_debug("%s: dcon now %08x\n", __FUNCTION__, dcon); ++ ++ /* For DMCCxControl 0 */ ++ chan->dcon = dcon; ++ ++ /* For DMACCxControl 1 : xferunit means transfer width.*/ ++ chan->xfer_unit = xferunit; ++ ++ return 0; ++} ++EXPORT_SYMBOL(s3c2410_dma_config); ++ ++int s3c2410_dma_setflags(dmach_t channel, unsigned int flags) ++{ ++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); ++ ++ if (chan == NULL) ++ return -EINVAL; ++ ++ pr_debug("%s: chan=%p, flags=%08x\n", __FUNCTION__, chan, flags); ++ ++ chan->flags = flags; ++ ++ return 0; ++} ++EXPORT_SYMBOL(s3c2410_dma_setflags); ++ ++ ++/* do we need to protect the settings of the fields from ++ * irq? ++ */ ++ ++int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn) ++{ ++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); ++ ++ if (chan == NULL) ++ return -EINVAL; ++ ++ pr_debug("%s: chan=%p, op rtn=%p\n", __FUNCTION__, chan, rtn); ++ ++ chan->op_fn = rtn; ++ ++ return 0; ++} ++EXPORT_SYMBOL(s3c2410_dma_set_opfn); ++ ++ ++int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn) ++{ ++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); ++ ++ if (chan == NULL) ++ return -EINVAL; ++ ++ pr_debug("%s: chan=%p, callback rtn=%p\n", __FUNCTION__, chan, rtn); ++ ++ chan->callback_fn = rtn; ++ ++ return 0; ++} ++EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn); ++ ++ ++/* s3c2410_dma_devconfig ++ * ++ * configure the dma source/destination hardware type and address ++ * ++ * flowctrl: direction of dma flow ++ * ++ * src_per dst_per: dma channel number of src and dst periphreal, ++ * ++ * devaddr: physical address of the source ++ */ ++ ++int s3c2410_dma_devconfig(int channel, ++ enum s3c2410_dmasrc source, ++ int hwcfg, ++ unsigned long devaddr) ++{ ++ ++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); ++ ++ if (chan == NULL) ++ return -EINVAL; ++ ++ pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n", ++ __FUNCTION__, (int)source, hwcfg, devaddr); ++ ++ chan->source = source; ++ chan->dev_addr = devaddr; ++ ++ switch (source) { ++ case S3C2410_DMASRC_MEM: ++ /* source is Memory : Mem-to-Peri ( Write into FIFO) */ ++ chan->config_flags = chan->map->hw_addr.to; ++ ++ hwcfg = S3C_DMACONTROL_DBSIZE(1)|S3C_DMACONTROL_SBSIZE(1); ++ chan->control_flags = S3C_DMACONTROL_DP_NON_SECURE|S3C_DMACONTROL_DEST_FIXED| ++ S3C_DMACONTROL_SP_NON_SECURE|S3C_DMACONTROL_SRC_INC| ++ hwcfg; ++ //chan->control_flags = hwcfg; ++ return 0; ++ ++ case S3C2410_DMASRC_HW: ++ /* source is peripheral : Peri-to-Mem ( Read from FIFO) */ ++ chan->config_flags = chan->map->hw_addr.from; ++ ++ hwcfg = S3C_DMACONTROL_DBSIZE(1)|S3C_DMACONTROL_SBSIZE(1); ++ chan->control_flags = S3C_DMACONTROL_DP_NON_SECURE|S3C_DMACONTROL_DEST_INC| ++ S3C_DMACONTROL_SP_NON_SECURE|S3C_DMACONTROL_SRC_FIXED| ++ hwcfg; ++ //chan->control_flags = hwcfg; ++ return 0; ++ ++ case S3C_DMA_MEM2MEM: ++ ++ chan->config_flags = 0; ++ ++ hwcfg = S3C_DMACONTROL_DBSIZE(16)|S3C_DMACONTROL_SBSIZE(16); ++ chan->control_flags = S3C_DMACONTROL_DP_NON_SECURE|S3C_DMACONTROL_DEST_INC| ++ S3C_DMACONTROL_SP_NON_SECURE|S3C_DMACONTROL_SRC_INC| ++ hwcfg; ++ //chan->control_flags = hwcfg; ++ return 0; ++ ++ case S3C_DMA_MEM2MEM_SET: ++ ++ chan->config_flags = 0; ++ ++ hwcfg = S3C_DMACONTROL_DBSIZE(16)|S3C_DMACONTROL_SBSIZE(16); ++ chan->control_flags = S3C_DMACONTROL_DP_NON_SECURE|S3C_DMACONTROL_DEST_INC| ++ S3C_DMACONTROL_SP_NON_SECURE|S3C_DMACONTROL_SRC_FIXED| ++ hwcfg; ++ //chan->control_flags = hwcfg; ++ return 0; ++ ++ ++ case S3C_DMA_PER2PER: ++ printk("Peripheral-to-Peripheral DMA NOT YET implemented !! \n"); ++ return -EINVAL; ++ ++ default: ++ printk(KERN_ERR "DMA CH :%d - invalid source type ()\n", channel); ++ printk("Unsupported DMA configuration from the device driver using DMA driver \n"); ++ return -EINVAL; ++ } ++ ++} ++ ++EXPORT_SYMBOL(s3c2410_dma_devconfig); ++ ++ ++/* ++ * s3c2410_dma_getposition ++ * returns the current transfer points for the dma source and destination ++ */ ++int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst) ++{ ++ struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); ++ ++ if (chan == NULL) ++ return -EINVAL; ++ ++ if (src != NULL) ++ *src = dma_rdreg(chan->dma_con, S3C_DMAC_SA(chan->number)); ++ ++ if (dst != NULL) ++ *dst = dma_rdreg(chan->dma_con, S3C_DMAC_DA(chan->number)); ++ ++ return 0; ++} ++ ++EXPORT_SYMBOL(s3c2410_dma_getposition); ++ ++ ++/* system device class */ ++#ifdef CONFIG_PM ++static int s3c_dma_suspend (struct sys_device *dev, pm_message_t state) ++{ ++ return 0; ++} ++ ++static int s3c_dma_resume (struct sys_device *dev) ++{ ++ return 0; ++} ++#else ++#define s3c_dma_suspend NULL ++#define s3c_dma_resume NULL ++#endif /* CONFIG_PM */ ++ ++struct sysdev_class dma_sysclass = { ++ .name = "pl330-dma", ++ .suspend = s3c_dma_suspend, ++ .resume = s3c_dma_resume, ++}; ++ ++/* kmem cache implementation */ ++ ++static void s3c_dma_cache_ctor(void *p) ++{ ++ memset(p, 0, sizeof(struct s3c_dma_buf)); ++} ++ ++ ++/* initialisation code */ ++ ++int __init s3c_dma_init(unsigned int channels, unsigned int irq, ++ unsigned int stride) ++{ ++ struct s3c2410_dma_chan *cp; ++ s3c_dma_controller_t *dconp; ++ int channel, controller; ++ int ret; ++ ++ printk("S3C PL330-DMA Controller Driver, (c) 2008-2009 Samsung Electronics\n"); ++ ++ dma_channels = channels; ++ printk("Total %d DMA channels will be initialized.\n", channels); ++ ++ ret = sysdev_class_register(&dma_sysclass); ++ if (ret != 0) { ++ printk(KERN_ERR "dma sysclass registration failed.\n"); ++ goto err; ++ } ++ ++ dma_kmem = kmem_cache_create("dma_desc", ++ sizeof(struct s3c_dma_buf), 0, ++ SLAB_HWCACHE_ALIGN, ++ s3c_dma_cache_ctor); ++ ++ if (dma_kmem == NULL) { ++ printk(KERN_ERR "DMA failed to make kmem cache for DMA channel descriptor\n"); ++ ret = -ENOMEM; ++ goto err; ++ } ++ ++ for (controller = 0; controller < S3C_DMA_CONTROLLERS; controller++) { ++ dconp = &s3c_dma_cntlrs[controller]; ++ ++ memset(dconp, 0, sizeof(s3c_dma_controller_t)); ++ ++ if(controller == 0) { ++ dma_base = ioremap(S3C_PA_DMA, stride); ++ if (dma_base == NULL) { ++ printk(KERN_ERR "M2M-DMA failed to ioremap register block\n"); ++ return -ENOMEM; ++ } ++ ++ /* dma controller's irqs are in order.. */ ++ dconp->irq = controller + irq; ++ } ++ else { ++ dma_base = ioremap(((S3C_PA_DMA + 0xF00000) + ((controller-1) * 0x200000)), stride); ++ if (dma_base == NULL) { ++ printk(KERN_ERR "Peri-DMA failed to ioremap register block\n"); ++ return -ENOMEM; ++ } ++ ++ /* dma controller's irqs are in order.. */ ++ dconp->irq = controller + irq; ++ } ++ ++ dconp->number = controller; ++ dconp->regs = dma_base; ++ pr_debug("PL330 DMA controller : %d irq %d regs_base %x\n", dconp->number, dconp->irq, ++ dconp->regs); ++ } ++ ++ for (channel = 0; channel < channels; channel++) { ++ controller = channel / S3C_CHANNELS_PER_DMA; ++ cp = &s3c_dma_chans[channel]; ++ ++ memset(cp, 0, sizeof(struct s3c2410_dma_chan)); ++ ++ cp->dma_con = &s3c_dma_cntlrs[controller]; ++ ++ /* dma channel irqs are in order.. */ ++ cp->index = channel; ++ cp->number = channel%S3C_CHANNELS_PER_DMA; ++ ++ cp->irq = s3c_dma_cntlrs[controller].irq; ++ ++ cp->regs = s3c_dma_cntlrs[controller].regs; ++ ++ /* point current stats somewhere */ ++ cp->stats = &cp->stats_store; ++ cp->stats_store.timeout_shortest = LONG_MAX; ++ ++ /* basic channel configuration */ ++ cp->load_timeout = 1 << 18; ++ ++ /* register system device */ ++ cp->dev.cls = &dma_sysclass; ++ cp->dev.id = channel; ++ ++ pr_debug("DMA channel %d at %p, irq %d\n", cp->number, cp->regs, cp->irq); ++ } ++ ++ return 0; ++err: ++ kmem_cache_destroy(dma_kmem); ++ iounmap(dma_base); ++ dma_base = NULL; ++ return ret; ++} ++ ++ ++ ++static inline int is_channel_valid(unsigned int channel) ++{ ++ return (channel & DMA_CH_VALID); ++} ++ ++static struct s3c_dma_order *dma_order; ++ ++ ++/* s3c_dma_map_channel() ++ * ++ * turn the virtual channel number into a real, and un-used hardware ++ * channel. ++ * ++ * first, try the dma ordering given to us by either the relevant ++ * dma code, or the board. Then just find the first usable free ++ * channel ++*/ ++ ++struct s3c2410_dma_chan *s3c_dma_map_channel(int channel) ++{ ++ struct s3c_dma_order_ch *ord = NULL; ++ struct s3c_dma_map *ch_map; ++ struct s3c2410_dma_chan *dmach; ++ int ch; ++ ++ if (dma_sel.map == NULL || channel > dma_sel.map_size) ++ return NULL; ++ ++ ch_map = dma_sel.map + channel; ++ ++ /* first, try the board mapping */ ++ ++ if (dma_order) { ++ ord = &dma_order->channels[channel]; ++ ++ for (ch = 0; ch < dma_channels; ch++) { ++ if (!is_channel_valid(ord->list[ch])) ++ continue; ++ ++ if (s3c_dma_chans[ord->list[ch]].in_use == 0) { ++ ch = ord->list[ch] & ~DMA_CH_VALID; ++ goto found; ++ } ++ } ++ ++ if (ord->flags & DMA_CH_NEVER) ++ return NULL; ++ } ++ ++ /* second, search the channel map for first free */ ++ ++ for (ch = 0; ch < dma_channels; ch++) { ++ if (!is_channel_valid(ch_map->channels[ch])) ++ continue; ++ ++ if (s3c_dma_chans[ch].in_use == 0) { ++ pr_debug("mapped channel %d to %d\n", channel, ch); ++ break; ++ } ++ } ++ ++ if (ch >= dma_channels) ++ return NULL; ++ ++ /* update our channel mapping */ ++ ++ found: ++ dmach = &s3c_dma_chans[ch]; ++ dma_chan_map[channel] = dmach; ++ ++ /* select the channel */ ++ (dma_sel.select)(dmach, ch_map); ++ ++ return dmach; ++} ++ ++static int s3c_dma_check_entry(struct s3c_dma_map *map, int ch) ++{ ++ return 0; ++} ++ ++int __init s3c_dma_init_map(struct s3c_dma_selection *sel) ++{ ++ struct s3c_dma_map *nmap; ++ size_t map_sz = sizeof(*nmap) * sel->map_size; ++ int ptr; ++ ++ nmap = kmalloc(map_sz, GFP_KERNEL); ++ if (nmap == NULL) ++ return -ENOMEM; ++ ++ memcpy(nmap, sel->map, map_sz); ++ memcpy(&dma_sel, sel, sizeof(*sel)); ++ ++ dma_sel.map = nmap; ++ ++ for (ptr = 0; ptr < sel->map_size; ptr++) ++ s3c_dma_check_entry(nmap+ptr, ptr); ++ ++ return 0; ++} ++ ++int __init s3c_dma_order_set(struct s3c_dma_order *ord) ++{ ++ struct s3c_dma_order *nord = dma_order; ++ ++ if (nord == NULL) ++ nord = kmalloc(sizeof(struct s3c_dma_order), GFP_KERNEL); ++ ++ if (nord == NULL) { ++ printk(KERN_ERR "no memory to store dma channel order\n"); ++ return -ENOMEM; ++ } ++ ++ dma_order = nord; ++ memcpy(nord, ord, sizeof(struct s3c_dma_order)); ++ return 0; ++} ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/gpio-config.c linux-2.6.28.6/arch/arm/plat-s3c/gpio-config.c +--- linux-2.6.28/arch/arm/plat-s3c/gpio-config.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/gpio-config.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,189 @@ ++/* linux/arch/arm/plat-s3c/gpio-config.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C series GPIO configuration core ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++int s3c_gpio_cfgpin(unsigned int pin, unsigned int config) ++{ ++ struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); ++ unsigned long flags; ++ int offset; ++ int ret; ++ ++ if (!chip) ++ return -EINVAL; ++ ++ offset = pin - chip->chip.base; ++ ++ local_irq_save(flags); ++ ret = s3c_gpio_do_setcfg(chip, offset, config); ++ local_irq_restore(flags); ++ ++ return ret; ++} ++ ++int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull) ++{ ++ struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); ++ unsigned long flags; ++ int offset, ret; ++ ++ if (!chip) ++ return -EINVAL; ++ ++ offset = pin - chip->chip.base; ++ ++ local_irq_save(flags); ++ ret = s3c_gpio_do_setpull(chip, offset, pull); ++ local_irq_restore(flags); ++ ++ return ret; ++} ++ ++EXPORT_SYMBOL(s3c_gpio_cfgpin); ++EXPORT_SYMBOL(s3c_gpio_setpull); ++ ++#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX ++int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip, ++ unsigned int off, unsigned int cfg) ++{ ++ void __iomem *reg = chip->base; ++ unsigned int shift = off; ++ u32 con; ++ ++ if (s3c_gpio_is_cfg_special(cfg)) { ++ cfg &= 0xf; ++ ++ /* Map output to 0, and SFN2 to 1 */ ++ cfg -= 1; ++ if (cfg > 1) ++ return -EINVAL; ++ ++ cfg <<= shift; ++ } ++ ++ con = __raw_readl(reg); ++ con &= ~(0x1 << shift); ++ con |= cfg; ++ __raw_writel(con, reg); ++ ++ return 0; ++} ++ ++int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip, ++ unsigned int off, unsigned int cfg) ++{ ++ void __iomem *reg = chip->base; ++ unsigned int shift = off * 2; ++ u32 con; ++ ++ if (s3c_gpio_is_cfg_special(cfg)) { ++ cfg &= 0xf; ++ if (cfg > 3) ++ return -EINVAL; ++ ++ cfg <<= shift; ++ } ++ ++ con = __raw_readl(reg); ++ con &= ~(0x3 << shift); ++ con |= cfg; ++ __raw_writel(con, reg); ++ ++ return 0; ++} ++#endif ++ ++#ifdef CONFIG_S3C_GPIO_CFG_S3C64XX ++int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, ++ unsigned int off, unsigned int cfg) ++{ ++ void __iomem *reg = chip->base; ++ unsigned int shift = (off & 7) * 4; ++ u32 con; ++ ++ if (off < 8 && chip->chip.ngpio > 8) ++ reg -= 4; ++ ++ if (s3c_gpio_is_cfg_special(cfg)) { ++ cfg &= 0xf; ++ cfg <<= shift; ++ } ++ ++ con = __raw_readl(reg); ++ con &= ~(0xf << shift); ++ con |= cfg; ++ __raw_writel(con, reg); ++ ++ return 0; ++} ++#endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */ ++ ++#ifdef CONFIG_S3C_GPIO_CFG_S5PC1XX ++int s3c_gpio_setcfg_s5pc1xx(struct s3c_gpio_chip *chip, ++ unsigned int off, unsigned int cfg) ++{ ++ void __iomem *reg = chip->base; ++ unsigned int shift = (off & 7) * 4; ++ u32 con; ++ ++ if (s3c_gpio_is_cfg_special(cfg)) { ++ cfg &= 0xf; ++ cfg <<= shift; ++ } ++ ++ con = __raw_readl(reg); ++ con &= ~(0xf << shift); ++ con |= cfg; ++ __raw_writel(con, reg); ++ ++ return 0; ++} ++#endif /* CONFIG_S3C_GPIO_CFG_S5PC1XX */ ++ ++#ifdef CONFIG_S3C_GPIO_PULL_UPDOWN ++int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip, ++ unsigned int off, s3c_gpio_pull_t pull) ++{ ++ void __iomem *reg = chip->base + 0x08; ++ int shift = off * 2; ++ u32 pup; ++ ++ pup = __raw_readl(reg); ++ pup &= ~(3 << shift); ++ pup |= pull << shift; ++ __raw_writel(pup, reg); ++ ++ return 0; ++} ++ ++s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip, ++ unsigned int off) ++{ ++ void __iomem *reg = chip->base + 0x08; ++ int shift = off * 2; ++ u32 pup = __raw_readl(reg); ++ ++ pup >>= shift; ++ pup &= 0x3; ++ return (__force s3c_gpio_pull_t)pup; ++} ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/gpio.c linux-2.6.28.6/arch/arm/plat-s3c/gpio.c +--- linux-2.6.28/arch/arm/plat-s3c/gpio.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/gpio.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,147 @@ ++/* linux/arch/arm/plat-s3c/gpio.c ++ * ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C series GPIO core ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#ifdef CONFIG_S3C_GPIO_TRACK ++struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; ++ ++static __init void s3c_gpiolib_track(struct s3c_gpio_chip *chip) ++{ ++ unsigned int gpn; ++ int i; ++ ++ gpn = chip->chip.base; ++ for (i = 0; i < chip->chip.ngpio; i++, gpn++) { ++ BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios)); ++ s3c_gpios[gpn] = chip; ++ } ++} ++#endif /* CONFIG_S3C_GPIO_TRACK */ ++ ++/* Default routines for controlling GPIO, based on the original S3C24XX ++ * GPIO functions which deal with the case where each gpio bank of the ++ * chip is as following: ++ * ++ * base + 0x00: Control register, 2 bits per gpio ++ * gpio n: 2 bits starting at (2*n) ++ * 00 = input, 01 = output, others mean special-function ++ * base + 0x04: Data register, 1 bit per gpio ++ * bit n: data bit n ++*/ ++ ++static int s3c_gpiolib_input(struct gpio_chip *chip, unsigned offset) ++{ ++ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); ++ void __iomem *base = ourchip->base; ++ unsigned long flags; ++ unsigned long con; ++ ++ local_irq_save(flags); ++ ++ con = __raw_readl(base + 0x00); ++ con &= ~(3 << (offset * 2)); ++ ++ __raw_writel(con, base + 0x00); ++ ++ local_irq_restore(flags); ++ return 0; ++} ++ ++static int s3c_gpiolib_output(struct gpio_chip *chip, ++ unsigned offset, int value) ++{ ++ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); ++ void __iomem *base = ourchip->base; ++ unsigned long flags; ++ unsigned long dat; ++ unsigned long con; ++ ++ local_irq_save(flags); ++ ++ dat = __raw_readl(base + 0x04); ++ dat &= ~(1 << offset); ++ if (value) ++ dat |= 1 << offset; ++ __raw_writel(dat, base + 0x04); ++ ++ con = __raw_readl(base + 0x00); ++ con &= ~(3 << (offset * 2)); ++ con |= 1 << (offset * 2); ++ ++ __raw_writel(con, base + 0x00); ++ __raw_writel(dat, base + 0x04); ++ ++ local_irq_restore(flags); ++ return 0; ++} ++ ++static void s3c_gpiolib_set(struct gpio_chip *chip, ++ unsigned offset, int value) ++{ ++ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); ++ void __iomem *base = ourchip->base; ++ unsigned long flags; ++ unsigned long dat; ++ ++ local_irq_save(flags); ++ ++ dat = __raw_readl(base + 0x04); ++ dat &= ~(1 << offset); ++ if (value) ++ dat |= 1 << offset; ++ __raw_writel(dat, base + 0x04); ++ ++ local_irq_restore(flags); ++} ++ ++static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset) ++{ ++ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); ++ unsigned long val; ++ ++ val = __raw_readl(ourchip->base + 0x04); ++ val >>= offset; ++ val &= 1; ++ ++ return val; ++} ++ ++__init void s3c_gpiolib_add(struct s3c_gpio_chip *chip) ++{ ++ struct gpio_chip *gc = &chip->chip; ++ int ret; ++ ++ BUG_ON(!chip->base); ++ BUG_ON(!gc->label); ++ BUG_ON(!gc->ngpio); ++ ++ if (!gc->direction_input) ++ gc->direction_input = s3c_gpiolib_input; ++ if (!gc->direction_output) ++ gc->direction_output = s3c_gpiolib_output; ++ if (!gc->set) ++ gc->set = s3c_gpiolib_set; ++ if (!gc->get) ++ gc->get = s3c_gpiolib_get; ++ ++ /* gpiochip_add() prints own failure message on error. */ ++ ret = gpiochip_add(gc); ++ if (ret >= 0) ++ s3c_gpiolib_track(chip); ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/mach/audio.h linux-2.6.28.6/arch/arm/plat-s3c/include/mach/audio.h +--- linux-2.6.28/arch/arm/plat-s3c/include/mach/audio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/mach/audio.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,45 @@ ++/* linux/arch/arm/plat-s3c/include/mach/audio.h ++ * ++ * Copyright (c) 2004-2005 Simtec Electronics ++ * http://www.simtec.co.uk/products/SWLINUX/ ++ * Ben Dooks ++ * ++ * S3C24XX - Audio platfrom_device info ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_AUDIO_H ++#define __ASM_ARCH_AUDIO_H __FILE__ ++ ++/* struct s3c24xx_iis_ops ++ * ++ * called from the s3c24xx audio core to deal with the architecture ++ * or the codec's setup and control. ++ * ++ * the pointer to itself is passed through in case the caller wants to ++ * embed this in an larger structure for easy reference to it's context. ++*/ ++ ++struct s3c24xx_iis_ops { ++ struct module *owner; ++ ++ int (*startup)(struct s3c24xx_iis_ops *me); ++ void (*shutdown)(struct s3c24xx_iis_ops *me); ++ int (*suspend)(struct s3c24xx_iis_ops *me); ++ int (*resume)(struct s3c24xx_iis_ops *me); ++ ++ int (*open)(struct s3c24xx_iis_ops *me, struct snd_pcm_substream *strm); ++ int (*close)(struct s3c24xx_iis_ops *me, struct snd_pcm_substream *strm); ++ int (*prepare)(struct s3c24xx_iis_ops *me, struct snd_pcm_substream *strm, struct snd_pcm_runtime *rt); ++}; ++ ++struct s3c24xx_platdata_iis { ++ const char *codec_clk; ++ struct s3c24xx_iis_ops *ops; ++ int (*match_dev)(struct device *dev); ++}; ++ ++#endif /* __ASM_ARCH_AUDIO_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/mach/dma-pl080.h linux-2.6.28.6/arch/arm/plat-s3c/include/mach/dma-pl080.h +--- linux-2.6.28/arch/arm/plat-s3c/include/mach/dma-pl080.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/mach/dma-pl080.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,183 @@ ++/* linux/arch/arm/plat-s3c/include/mach/dma-pl080.h ++ * ++ */ ++ ++#ifndef __ARM_MACH_DMA_PL080_H ++#define __ARM_MACH_DMA_PL080_H ++ ++/* ++ * This is the maximum DMA address(physical address) that can be DMAd to. ++ * ++ */ ++#define MAX_DMA_ADDRESS 0x40000000 ++#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ ++ ++#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ ++ ++/* We have 4 dma controllers - DMA0, DMA1, SDMA0, SDMA1 */ ++#define S3C_DMA_CONTROLLERS (4) ++#define S3C_CHANNELS_PER_DMA (8) ++#define S3C_CANDIDATE_CHANNELS_PER_DMA (16) ++#define S3C_DMA_CHANNELS (S3C_DMA_CONTROLLERS*S3C_CHANNELS_PER_DMA) ++ ++/* flags */ ++#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about */ ++#define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */ ++ ++/* DMA Register definitions */ ++#define S3C2410_DCON_AUTORELOAD (0<<22) ++#define S3C2410_DCON_NORELOAD (1<<22) ++ ++/*=================================================*/ ++/* DMA Register Definitions for S3C6400 */ ++ ++#define S3C_DMAC_INT_STATUS (0x00) ++#define S3C_DMAC_INT_TCSTATUS (0x04) ++#define S3C_DMAC_INT_TCCLEAR (0x08) ++#define S3C_DMAC_INT_ERRORSTATUS (0x0c) ++#define S3C_DMAC_INT_ERRORCLEAR (0x10) ++#define S3C_DMAC_RAW_INTTCSTATUS (0x14) ++#define S3C_DMAC_RAW_INTERRORSTATUS (0x18) ++#define S3C_DMAC_ENBLD_CHANNELS (0x1c) ++#define S3C_DMAC_SOFTBREQ (0x20) ++#define S3C_DMAC_SOFTSREQ (0x24) ++#define S3C_DMAC_SOFTLBREQ (0x28) ++#define S3C_DMAC_SOFTLSREQ (0x2c) ++#define S3C_DMAC_CONFIGURATION (0x30) ++#define S3C_DMAC_SYNC (0x34) ++ ++#define S3C_DMAC_CxSRCADDR (0x00) ++#define S3C_DMAC_CxDESTADDR (0x04) ++#define S3C_DMAC_CxLLI (0x08) ++#define S3C_DMAC_CxCONTROL0 (0x0C) ++#define S3C_DMAC_CxCONTROL1 (0x10) ++#define S3C_DMAC_CxCONFIGURATION (0x14) ++ ++#define S3C_DMAC_C0SRCADDR (0x100) ++#define S3C_DMAC_C0DESTADDR (0x104) ++#define S3C_DMAC_C0LLI (0x108) ++#define S3C_DMAC_C0CONTROL0 (0x10C) ++#define S3C_DMAC_C0CONTROL1 (0x110) ++#define S3C_DMAC_C0CONFIGURATION (0x114) ++ ++#define S3C_DMAC_C1SRCADDR (0x120) ++#define S3C_DMAC_C1DESTADDR (0x124) ++#define S3C_DMAC_C1LLI (0x128) ++#define S3C_DMAC_C1CONTROL0 (0x12C) ++#define S3C_DMAC_C1CONTROL1 (0x130) ++#define S3C_DMAC_C1CONFIGURATION (0x134) ++ ++#define S3C_DMAC_C2SRCADDR (0x140) ++#define S3C_DMAC_C2DESTADDR (0x144) ++#define S3C_DMAC_C2LLI (0x148) ++#define S3C_DMAC_C2CONTROL0 (0x14C) ++#define S3C_DMAC_C2CONTROL1 (0x150) ++#define S3C_DMAC_C2CONFIGURATION (0x154) ++ ++#define S3C_DMAC_C3SRCADDR (0x160) ++#define S3C_DMAC_C3DESTADDR (0x164) ++#define S3C_DMAC_C3LLI (0x168) ++#define S3C_DMAC_C3CONTROL0 (0x16C) ++#define S3C_DMAC_C3CONTROL1 (0x170) ++#define S3C_DMAC_C3CONFIGURATION (0x174) ++ ++#define S3C_DMAC_C4SRCADDR (0x180) ++#define S3C_DMAC_C4DESTADDR (0x184) ++#define S3C_DMAC_C4LLI (0x188) ++#define S3C_DMAC_C4CONTROL0 (0x18C) ++#define S3C_DMAC_C4CONTROL1 (0x190) ++#define S3C_DMAC_C4CONFIGURATION (0x194) ++ ++#define S3C_DMAC_C5SRCADDR (0x1A0) ++#define S3C_DMAC_C5DESTADDR (0x1A4) ++#define S3C_DMAC_C5LLI (0x1A8) ++#define S3C_DMAC_C5CONTROL0 (0x1AC) ++#define S3C_DMAC_C5CONTROL1 (0x1B0) ++#define S3C_DMAC_C5CONFIGURATION (0x1B4) ++ ++#define S3C_DMAC_C6SRCADDR (0x1C0) ++#define S3C_DMAC_C6DESTADDR (0x1C4) ++#define S3C_DMAC_C6LLI (0x1C8) ++#define S3C_DMAC_C6CONTROL0 (0x1CC) ++#define S3C_DMAC_C6CONTROL1 (0x1D0) ++#define S3C_DMAC_C6CONFIGURATION (0x1D4) ++ ++#define S3C_DMAC_C7SRCADDR (0x1E0) ++#define S3C_DMAC_C7DESTADDR (0x1E4) ++#define S3C_DMAC_C7LLI (0x1E8) ++#define S3C_DMAC_C7CONTROL0 (0x1EC) ++#define S3C_DMAC_C7CONTROL1 (0x1F0) ++#define S3C_DMAC_C7CONFIGURATION (0x1F4) ++ ++/* DMACConfiguration(0x30) */ ++#define S3C_DMA_CONTROLLER_ENABLE (1<<0) ++ ++/* DMACCxControl0 : Channel control register 0 */ ++#define S3C_DMACONTROL_TC_INT_ENABLE (1<<31) ++#define S3C_DMACONTROL_DEST_NO_INC (0<<27) ++#define S3C_DMACONTROL_DEST_INC (1<<27) ++#define S3C_DMACONTROL_SRC_NO_INC (0<<26) ++#define S3C_DMACONTROL_SRC_INC (1<<26) ++#define S3C_DMACONTROL_DEST_AXI_SPINE (0<<25) ++#define S3C_DMACONTROL_DEST_AXI_PERI (1<<25) ++#define S3C_DMACONTROL_SRC_AXI_SPINE (0<<24) ++#define S3C_DMACONTROL_SRC_AXI_PERI (1<<24) ++#define S3C_DMACONTROL_DEST_WIDTH_BYTE (0<<21) ++#define S3C_DMACONTROL_DEST_WIDTH_HWORD (1<<21) ++#define S3C_DMACONTROL_DEST_WIDTH_WORD (2<<21) ++#define S3C_DMACONTROL_SRC_WIDTH_BYTE (0<<18) ++#define S3C_DMACONTROL_SRC_WIDTH_HWORD (1<<18) ++#define S3C_DMACONTROL_SRC_WIDTH_WORD (2<<18) ++ ++#define S3C_DMACONTROL_DBSIZE_1 (0<<15) ++#define S3C_DMACONTROL_DBSIZE_4 (1<<15) ++#define S3C_DMACONTROL_DBSIZE_8 (2<<15) ++#define S3C_DMACONTROL_DBSIZE_16 (3<<15) ++#define S3C_DMACONTROL_DBSIZE_32 (4<<15) ++#define S3C_DMACONTROL_DBSIZE_64 (5<<15) ++#define S3C_DMACONTROL_DBSIZE_128 (6<<15) ++#define S3C_DMACONTROL_DBSIZE_256 (7<<15) ++ ++#define S3C_DMACONTROL_SBSIZE_1 (0<<12) ++#define S3C_DMACONTROL_SBSIZE_4 (1<<12) ++#define S3C_DMACONTROL_SBSIZE_8 (2<<12) ++#define S3C_DMACONTROL_SBSIZE_16 (3<<12) ++#define S3C_DMACONTROL_SBSIZE_32 (4<<12) ++#define S3C_DMACONTROL_SBSIZE_64 (5<<12) ++#define S3C_DMACONTROL_SBSIZE_128 (6<<12) ++#define S3C_DMACONTROL_SBSIZE_256 (7<<12) ++ ++ ++/* Channel configuration register, DMACCxConfiguration */ ++#define S3C_DMACONFIG_HALT (1<<18) /*The contents of the channels FIFO are drained*/ ++#define S3C_DMACONFIG_ACTIVE (1<<17) /*Check channel fifo has data or not*/ ++#define S3C_DMACONFIG_LOCK (1<<16) ++#define S3C_DMACONFIG_TCMASK (1<<15) /*Terminal count interrupt mask*/ ++#define S3C_DMACONFIG_ERRORMASK (1<<14) /*Interrup error mask*/ ++#define S3C_DMACONFIG_FLOWCTRL_MEM2MEM (0<<11) ++#define S3C_DMACONFIG_FLOWCTRL_MEM2PER (1<<11) ++#define S3C_DMACONFIG_FLOWCTRL_PER2MEM (2<<11) ++#define S3C_DMACONFIG_FLOWCTRL_PER2PER (3<<11) ++#define S3C_DMACONFIG_ONENANDMODEDST (1<<10) /* Reserved: OneNandModeDst */ ++#define S3C_DMACONFIG_DESTPERIPHERAL(x) ((x)<<6) ++#define S3C_DMACONFIG_ONENANDMODESRC (1<<5) /* Reserved: OneNandModeSrc */ ++#define S3C_DMACONFIG_SRCPERIPHERAL(x) ((x)<<1) ++#define S3C_DMACONFIG_CHANNEL_ENABLE (1<<0) ++ ++#define S3C_DMA1 16 ++ ++#define S3C_DEST_SHIFT 6 ++#define S3C_SRC_SHIFT 1 ++ ++ ++/* #define S3C_DMAC_CSRCADDR(ch) S3C_DMAC_C##ch##SRCADDR */ ++#define S3C_DMAC_CSRCADDR(ch) (S3C_DMAC_C0SRCADDR+ch*0x20) ++#define S3C_DMAC_CDESTADDR(ch) (S3C_DMAC_C0DESTADDR+ch*0x20) ++#define S3C_DMAC_CLLI(ch) (S3C_DMAC_C0LLI+ch*0x20) ++#define S3C_DMAC_CCONTROL0(ch) (S3C_DMAC_C0CONTROL0+ch*0x20) ++#define S3C_DMAC_CCONTROL1(ch) (S3C_DMAC_C0CONTROL1+ch*0x20) ++#define S3C_DMAC_CCONFIGURATION(ch) (S3C_DMAC_C0CONFIGURATION+ch*0x20) ++ ++ ++ ++#endif //__ARM_MACH_DMA_PL080_H +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/mach/dma-pl330.h linux-2.6.28.6/arch/arm/plat-s3c/include/mach/dma-pl330.h +--- linux-2.6.28/arch/arm/plat-s3c/include/mach/dma-pl330.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/mach/dma-pl330.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,114 @@ ++/* linux/arch/arm/plat-s3c/include/mach/dma-pl330.h ++ * ++ */ ++ ++#ifndef __ARM_MACH_DMA_PL330_H ++#define __ARM_MACH_DMA_PL330_H __FILE__ ++ ++#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ ++ ++ ++/* flags */ ++#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about */ ++#define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */ ++ ++/*=================================================*/ ++/* DMA Register Definitions for PL330 DMAC */ ++ ++#define S3C_DMAC_DS (0x00) ++#define S3C_DMAC_DPC (0x04) ++#define S3C_DMAC_INTEN (0x20) /* R/W */ ++#define S3C_DMAC_ES (0x24) ++#define S3C_DMAC_INTSTATUS (0x28) ++#define S3C_DMAC_INTCLR (0x2C) /* W/O */ ++#define S3C_DMAC_FSM (0x30) ++#define S3C_DMAC_FSC (0x34) ++#define S3C_DMAC_FTM (0x38) ++ ++#define S3C_DMAC_FTC0 (0x40) ++#define S3C_DMAC_CS0 (0x100) ++#define S3C_DMAC_CPC0 (0x104) ++#define S3C_DMAC_SA_0 (0x400) ++#define S3C_DMAC_DA_0 (0x404) ++#define S3C_DMAC_CC_0 (0x408) ++#define S3C_DMAC_LC0_0 (0x40C) ++#define S3C_DMAC_LC1_0 (0x410) ++ ++#define S3C_DMAC_FTC(ch) (S3C_DMAC_FTC0+ch*0x4) ++#define S3C_DMAC_CS(ch) (S3C_DMAC_CS0+ch*0x8) ++#define S3C_DMAC_CPC(ch) (S3C_DMAC_CPC0+ch*0x8) ++#define S3C_DMAC_SA(ch) (S3C_DMAC_SA_0+ch*0x20) ++#define S3C_DMAC_DA(ch) (S3C_DMAC_DA_0+ch*0x20) ++#define S3C_DMAC_CC(ch) (S3C_DMAC_CC_0+ch*0x20) ++#define S3C_DMAC_LC0(ch) (S3C_DMAC_LC0_0+ch*0x20) ++#define S3C_DMAC_LC10(ch) (S3C_DMAC_LC1_0+ch*0x20) ++ ++#define S3C_DMAC_DBGSTATUS (0xD00) ++#define S3C_DMAC_DBGCMD (0xD04) /* W/O */ ++#define S3C_DMAC_DBGINST0 (0xD08) /* W/O */ ++#define S3C_DMAC_DBGINST1 (0xD0C) /* W/O */ ++#define S3C_DMAC_CR0 (0xE00) ++#define S3C_DMAC_CR1 (0xE04) ++#define S3C_DMAC_CR2 (0xE08) ++#define S3C_DMAC_CR3 (0xE0C) ++#define S3C_DMAC_CR4 (0xE10) ++#define S3C_DMAC_CRDn (0xE14) ++ ++#define S3C_DMAC_PERI_ID (0xFE0) ++#define S3C_DMAC_PCELL_ID (0xFF0) ++ ++/* S3C_DMAC_CS[3:0] - Channel status */ ++#define S3C_DMAC_CS_STOPPED 0x0 ++#define S3C_DMAC_CS_EXECUTING 0x1 ++#define S3C_DMAC_CS_CACHE_MISS 0x2 ++#define S3C_DMAC_CS_UPDATING_PC 0x3 ++#define S3C_DMAC_CS_WAITING_FOR_EVENT 0x4 ++#define S3C_DMAC_CS_AT_BARRIER 0x5 ++#define S3C_DMAC_CS_QUEUE_BUSY 0x6 ++#define S3C_DMAC_CS_WAITING_FOR_PERI 0x7 ++#define S3C_DMAC_CS_KILLING 0x8 ++#define S3C_DMAC_CS_COMPLETING 0x9 ++#define S3C_DMAC_CS_FAULT_COMPLETING 0xE ++#define S3C_DMAC_CS_FAULTING 0xF ++ ++ ++ ++/* S3C_DMAC_INTEN : Interrupt Enable Register */ ++#define S3C_DMAC_INTEN_EVENT(x) ((x)<<0) ++#define S3C_DMAC_INTEN_IRQ(x) ((x)<<1) ++ ++/* S3C_DMAC_INTCLR : Interrupt Clear Register */ ++#define S3C_DMAC_INTCLR_IRQ(x) ((x)<<1) ++ ++/* S3C DMA Channel control */ ++/* Source control */ ++#define S3C_DMACONTROL_SRC_INC (1<<0) ++#define S3C_DMACONTROL_SRC_FIXED (0<<0) ++#define S3C_DMACONTROL_SRC_WIDTH_BYTE (0<<1) ++#define S3C_DMACONTROL_SRC_WIDTH_HWORD (1<<1) ++#define S3C_DMACONTROL_SRC_WIDTH_WORD (2<<1) ++#define S3C_DMACONTROL_SRC_WIDTH_DWORD (3<<1) ++#define S3C_DMACONTROL_SBSIZE(x) (((x-1)&0xF)<<4) ++#define S3C_DMACONTROL_SP_SECURE (0<<8) ++#define S3C_DMACONTROL_SP_NON_SECURE (2<<8) ++#define S3C_DMACONTROL_SCACHE (0<<11) ++ ++/* Destination control */ ++#define S3C_DMACONTROL_DEST_INC (1<<14) ++#define S3C_DMACONTROL_DEST_FIXED (0<<14) ++#define S3C_DMACONTROL_DEST_WIDTH_BYTE (0<<15) ++#define S3C_DMACONTROL_DEST_WIDTH_HWORD (1<<15) ++#define S3C_DMACONTROL_DEST_WIDTH_WORD (2<<15) ++#define S3C_DMACONTROL_DEST_WIDTH_DWORD (3<<15) ++#define S3C_DMACONTROL_DBSIZE(x) (((x-1)&0xF)<<18) ++#define S3C_DMACONTROL_DP_SECURE (0<<22) ++#define S3C_DMACONTROL_DP_NON_SECURE (2<<22) ++#define S3C_DMACONTROL_DCACHE (0<<25) ++ ++#define S3C_DMACONTROL_ES_SIZE_8 (0<<28) ++#define S3C_DMACONTROL_ES_SIZE_16 (1<<28) ++#define S3C_DMACONTROL_ES_SIZE_32 (2<<28) ++#define S3C_DMACONTROL_ES_SIZE_64 (3<<28) ++ ++#endif /* __ARM_MACH_DMA_PL330_H */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/mach/io.h linux-2.6.28.6/arch/arm/plat-s3c/include/mach/io.h +--- linux-2.6.28/arch/arm/plat-s3c/include/mach/io.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/mach/io.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,18 @@ ++/* linux/arch/arm/plat-s3c/include/mach/io.h ++ * ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * ++ * Default IO routines for plat-s3c based systems, such as S3C24A0 ++ */ ++ ++#ifndef __ASM_ARM_ARCH_IO_H ++#define __ASM_ARM_ARCH_IO_H ++ ++/* No current ISA/PCI bus support. */ ++#define __io(a) ((void __iomem *)(a)) ++#define __mem_pci(a) (a) ++ ++#define IO_SPACE_LIMIT (0xFFFFFFFF) ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/mach/s3c-dma.h linux-2.6.28.6/arch/arm/plat-s3c/include/mach/s3c-dma.h +--- linux-2.6.28/arch/arm/plat-s3c/include/mach/s3c-dma.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/mach/s3c-dma.h 2009-10-20 04:30:42.000000000 +0200 +@@ -0,0 +1,372 @@ ++/* linux/arch/arm/plat-s3c/include/mach/s3c-dma.h ++ * ++ */ ++ ++#ifndef __ARM_MACH_S3C_DMA_H ++#define __ARM_MACH_S3C_DMA_H ++ ++#include ++#include ++#include ++ ++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) ++#include ++#elif defined(CONFIG_CPU_S5PC100) || defined(CONFIG_CPU_S5P6440) ++#include ++#endif ++ ++/* We use `virtual` dma channels to hide the fact we have only a limited ++ * number of DMA channels, and not of all of them (dependant on the device) ++ * can be attached to any DMA source. We therefore let the DMA core handle ++ * the allocation of hardware channels to clients. ++*/ ++ ++enum dma_ch { ++ DMACH_XD0, ++ DMACH_XD1, ++ DMACH_SDI, ++ DMACH_SPI0, ++ DMACH_SPI_TX, ++ DMACH_SPI_RX, ++ DMACH_SPI1, ++ DMACH_UART0, ++ DMACH_UART1, ++ DMACH_UART2, ++ DMACH_TIMER, ++ DMACH_I2S_IN, ++ DMACH_I2S_OUT, ++ DMACH_I2S_IN_1, /* s3c2450 iis_1 rx */ ++ DMACH_I2S_OUT_1, /* s3c2450 iis_1 tx */ ++ DMACH_I2S_V40_IN, ++ DMACH_I2S_V40_OUT, ++ DMACH_I2S_V50_OUT, ++ DMACH_I2S_V50_IN, ++ DMACH_PCM_IN, ++ DMACH_PCM_OUT, ++ DMACH_MIC_IN, ++ DMACH_USB_EP1, ++ DMACH_USB_EP2, ++ DMACH_USB_EP3, ++ DMACH_USB_EP4, ++ DMACH_UART0_SRC2, /* s3c2412 second uart sources */ ++ DMACH_UART1_SRC2, ++ DMACH_UART2_SRC2, ++ DMACH_UART3, /* s3c2443 has extra uart */ ++ DMACH_UART3_SRC2, ++ DMACH_I2S1_IN, /* S3C6400 */ ++ DMACH_I2S1_OUT, ++ DMACH_SPI0_IN, ++ DMACH_SPI0_OUT, ++ DMACH_SPI1_IN, ++ DMACH_SPI1_OUT, ++ DMACH_AC97_PCM_OUT, ++ DMACH_AC97_PCM_IN, ++ DMACH_AC97_MIC_IN, ++ DMACH_ONENAND_IN, ++ DMACH_3D_M2M, ++ DMACH_MAX, /* the end entry */ ++}; ++ ++/* types */ ++ ++enum s3c_dma_state { ++ S3C_DMA_IDLE, ++ S3C_DMA_RUNNING, ++ S3C_DMA_PAUSED ++}; ++ ++ ++/* enum s3c_dma_loadst ++ * ++ * This represents the state of the DMA engine, wrt to the loaded / running ++ * transfers. Since we don't have any way of knowing exactly the state of ++ * the DMA transfers, we need to know the state to make decisions on wether ++ * we can ++ * ++ * S3C_DMA_NONE ++ * ++ * There are no buffers loaded (the channel should be inactive) ++ * ++ * S3C_DMA_1LOADED ++ * ++ * There is one buffer loaded, however it has not been confirmed to be ++ * loaded by the DMA engine. This may be because the channel is not ++ * yet running, or the DMA driver decided that it was too costly to ++ * sit and wait for it to happen. ++ * ++ * S3C_DMA_1RUNNING ++ * ++ * The buffer has been confirmed running, and not finisged ++ * ++ * S3C_DMA_1LOADED_1RUNNING ++ * ++ * There is a buffer waiting to be loaded by the DMA engine, and one ++ * currently running. ++*/ ++ ++enum s3c_dma_loadst { ++ S3C_DMALOAD_NONE, ++ S3C_DMALOAD_1LOADED, ++ S3C_DMALOAD_1RUNNING, ++ S3C_DMALOAD_1LOADED_1RUNNING, ++}; ++ ++enum s3c2410_dma_buffresult { ++ S3C2410_RES_OK, ++ S3C2410_RES_ERR, ++ S3C2410_RES_ABORT ++}; ++ ++enum s3c2410_dmasrc { ++ S3C2410_DMASRC_HW, /* source is memory */ ++ S3C2410_DMASRC_MEM, /* source is hardware */ ++ S3C_DMA_MEM2MEM, /* source is memory - READ/WRITE */ ++ S3C_DMA_MEM2MEM_SET, /* source is memory - READ/WRITE for MEMSET*/ ++ S3C_DMA_MEM2MEM_P, /* source is hardware - READ/WRITE */ ++ S3C_DMA_PER2PER /* source is hardware - READ/WRITE */ ++}; ++ ++/* enum s3c_chan_op ++ * ++ * operation codes passed to the DMA code by the user, and also used ++ * to inform the current channel owner of any changes to the system state ++*/ ++ ++enum s3c_chan_op { ++ S3C2410_DMAOP_START, ++ S3C2410_DMAOP_STOP, ++ S3C2410_DMAOP_PAUSE, ++ S3C2410_DMAOP_RESUME, ++ S3C2410_DMAOP_FLUSH, ++ S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */ ++ S3C2410_DMAOP_STARTED, /* indicate channel started */ ++}; ++ ++/* dma buffer */ ++ ++struct s3c2410_dma_client { ++ char *name; ++}; ++ ++/* s3c2410_dma_buf_s ++ * ++ * internally used buffer structure to describe a queued or running ++ * buffer. ++*/ ++ ++struct s3c_dma_buf; ++struct s3c_dma_buf { ++ struct s3c_dma_buf *next; ++ int magic; /* magic */ ++ int size; /* buffer size in bytes */ ++ dma_addr_t data; /* start of DMA data */ ++ dma_addr_t ptr; /* where the DMA got to [1] */ ++ void *id; /* client's id */ ++ dma_addr_t mcptr; /* physical pointer to a set of micro codes */ ++ unsigned long *mcptr_cpu; /* virtual pointer to a set of micro codes */ ++}; ++ ++/* [1] is this updated for both recv/send modes? */ ++ ++struct s3c2410_dma_chan; ++ ++/* s3c2410_dma_cbfn_t ++ * ++ * buffer callback routine type ++*/ ++ ++typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *, ++ void *buf, int size, ++ enum s3c2410_dma_buffresult result); ++ ++typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *, ++ enum s3c_chan_op ); ++ ++struct s3c_dma_stats { ++ unsigned long loads; ++ unsigned long timeout_longest; ++ unsigned long timeout_shortest; ++ unsigned long timeout_avg; ++ unsigned long timeout_failed; ++}; ++ ++struct s3c2410_dma_map; ++ ++/* struct s3c2410_dma_chan ++ * ++ * full state information for each DMA channel ++*/ ++ ++/*========================== S3C DMA ===========================================*/ ++typedef struct s3c_dma_controller s3c_dma_controller_t; ++struct s3c_dma_controller { ++ /* channel state flags and information */ ++ unsigned char number; /* number of this dma channel */ ++ unsigned char in_use; /* channel allocated and how many channel are used */ ++ unsigned char irq_claimed; /* irq claimed for channel */ ++ unsigned char irq_enabled; /* irq enabled for channel */ ++ unsigned char xfer_unit; /* size of an transfer */ ++ ++ /* channel state */ ++ ++ enum s3c_dma_state state; ++ enum s3c_dma_loadst load_state; ++ struct s3c2410_dma_client *client; ++ ++ /* channel configuration */ ++ unsigned long dev_addr; ++ unsigned long load_timeout; ++ unsigned int flags; /* channel flags */ ++ ++ /* channel's hardware position and configuration */ ++ void __iomem *regs; /* channels registers */ ++ void __iomem *addr_reg; /* data address register */ ++ unsigned int irq; /* channel irq */ ++ unsigned long dcon; /* default value of DCON */ ++ ++}; ++ ++struct s3c2410_dma_chan { ++ /* channel state flags and information */ ++ unsigned char number; /* number of this dma channel */ ++ unsigned char in_use; /* channel allocated */ ++ unsigned char irq_claimed; /* irq claimed for channel */ ++ unsigned char irq_enabled; /* irq enabled for channel */ ++ unsigned char xfer_unit; /* size of an transfer */ ++ ++ /* channel state */ ++ ++ enum s3c_dma_state state; ++ enum s3c_dma_loadst load_state; ++ struct s3c2410_dma_client *client; ++ ++ /* channel configuration */ ++ enum s3c2410_dmasrc source; ++ unsigned long dev_addr; ++ unsigned long load_timeout; ++ unsigned int flags; /* channel flags */ ++ ++ struct s3c_dma_map *map; /* channel hw maps */ ++ ++ /* channel's hardware position and configuration */ ++ void __iomem *regs; /* channels registers */ ++ void __iomem *addr_reg; /* data address register */ ++ unsigned int irq; /* channel irq */ ++ unsigned long dcon; /* default value of DCON */ ++ ++ /* driver handles */ ++ s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */ ++ s3c2410_dma_opfn_t op_fn; /* channel op callback */ ++ ++ /* stats gathering */ ++ struct s3c_dma_stats *stats; ++ struct s3c_dma_stats stats_store; ++ ++ /* buffer list and information */ ++ struct s3c_dma_buf *curr; /* current dma buffer */ ++ struct s3c_dma_buf *next; /* next buffer to load */ ++ struct s3c_dma_buf *end; /* end of queue */ ++ ++ /* system device */ ++ struct sys_device dev; ++ ++ unsigned int index; /* channel index */ ++ unsigned int config_flags; /* channel flags */ ++ unsigned int control_flags; /* channel flags */ ++ s3c_dma_controller_t *dma_con; ++}; ++ ++/* the currently allocated channel information */ ++extern struct s3c2410_dma_chan s3c2410_chans[]; ++ ++/* note, we don't really use dma_device_t at the moment */ ++typedef unsigned long dma_device_t; ++ ++struct s3c_sg_list { ++ unsigned long uSrcAddr; ++ unsigned long uDstAddr; ++ unsigned long uNextLLI; ++ unsigned long uCxControl0; ++ unsigned long uCxControl1; ++}; ++ ++/* functions --------------------------------------------------------------- */ ++ ++/* s3c2410_dma_request ++ * ++ * request a dma channel exclusivley ++*/ ++ ++extern int s3c2410_dma_request(dmach_t channel, ++ struct s3c2410_dma_client *, void *dev); ++ ++ ++/* s3c2410_dma_ctrl ++ * ++ * change the state of the dma channel ++*/ ++ ++extern int s3c2410_dma_ctrl(dmach_t channel, enum s3c_chan_op op); ++ ++ ++/* s3c2410_dma_setflags ++ * ++ * set the channel's flags to a given state ++*/ ++ ++extern int s3c2410_dma_setflags(dmach_t channel, ++ unsigned int flags); ++ ++ ++/* s3c2410_dma_free ++ * ++ * free the dma channel (will also abort any outstanding operations) ++*/ ++ ++extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *); ++ ++ ++/* s3c2410_dma_enqueue ++ * ++ * place the given buffer onto the queue of operations for the channel. ++ * The buffer must be allocated from dma coherent memory, or the Dcache/WB ++ * drained before the buffer is given to the DMA system. ++*/ ++ ++extern int s3c2410_dma_enqueue(dmach_t channel, void *id, ++ dma_addr_t data, int size); ++ ++extern int s3c2410_dma_enqueue_sg(dmach_t channel, void *id, ++ dma_addr_t data, int size, struct s3c_sg_list *sg_list); ++ ++/* s3c2410_dma_config ++ * ++ * configure the dma channel ++*/ ++ ++extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon); ++ ++/* s3c2410_dma_devconfig ++ * ++ * configure the device we're talking to ++*/ ++ ++extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source, ++ int hwcfg, unsigned long devaddr); ++ ++/* s3c2410_dma_getposition ++ * ++ * get the position that the dma transfer is currently at ++*/ ++ ++extern int s3c2410_dma_getposition(dmach_t channel, ++ dma_addr_t *src, dma_addr_t *dest); ++ ++ ++extern int s3c2410_dma_set_opfn(dmach_t, s3c2410_dma_opfn_t rtn); ++extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn); ++ ++ ++ ++ ++#endif //__ARM_MACH_S3C_DMA_H +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/mach/timex.h linux-2.6.28.6/arch/arm/plat-s3c/include/mach/timex.h +--- linux-2.6.28/arch/arm/plat-s3c/include/mach/timex.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/mach/timex.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,26 @@ ++/* linux/arch/arm/plat-s3c/include/mach/timex.h ++ * ++ * Copyright (c) 2003-2005 Simtec Electronics ++ * Ben Dooks ++ * ++ * S3C2410 - time parameters ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_TIMEX_H ++#define __ASM_ARCH_TIMEX_H ++ ++/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it ++ * a variable is useless. It seems as long as we make our timers an ++ * exact multiple of HZ, any value that makes a 1->1 correspondence ++ * for the time conversion functions to/from jiffies is acceptable. ++*/ ++ ++ ++#define CLOCK_TICK_RATE 12000000 ++ ++ ++#endif /* __ASM_ARCH_TIMEX_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/mach/vmalloc.h linux-2.6.28.6/arch/arm/plat-s3c/include/mach/vmalloc.h +--- linux-2.6.28/arch/arm/plat-s3c/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/mach/vmalloc.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,20 @@ ++/* linux/arch/arm/plat-s3c/include/mach/vmalloc.h ++ * ++ * from arch/arm/mach-iop3xx/include/mach/vmalloc.h ++ * ++ * Copyright (c) 2003 Simtec Electronics ++ * http://www.simtec.co.uk/products/SWLINUX/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C2410 vmalloc definition ++*/ ++ ++#ifndef __ASM_ARCH_VMALLOC_H ++#define __ASM_ARCH_VMALLOC_H ++ ++#define VMALLOC_END (0xE0000000) ++ ++#endif /* __ASM_ARCH_VMALLOC_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/adc.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/adc.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/adc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/adc.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,37 @@ ++/* arch/arm/plat-s3c/include/plat/adc.h ++ * ++ * Copyright (c) 2004 Simtec Electronics ++ * Ben Dooks ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_ADC_H ++#define __ASM_ARCH_ADC_H __FILE__ ++ ++ ++struct s3c_adc_request ++{ ++ /* for linked list */ ++ struct list_head *list; ++ /* after finish ADC sampling, s3c_adc_request function call this function with three parameter */ ++ void (*callback)( int channel, unsigned long int param, unsigned short sample); ++ /* for private data */ ++ unsigned long int param; ++ /* selected channel for ADC sampling */ ++ int channel; ++}; ++ ++struct s3c_adc_mach_info ++{ ++ /* if you need to use some platform data, add in here*/ ++ int delay; ++ int presc; ++ int resolution; ++}; ++ ++void __init s3c_adc_set_platdata(struct s3c_adc_mach_info *pd); ++ ++#endif /* __ASM_ARCH_ADC_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/clock.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/clock.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/clock.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/clock.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,112 @@ ++/* linux/arch/arm/plat-s3c/include/plat/clock.h ++ * ++ * Copyright (c) 2004-2005 Simtec Electronics ++ * http://www.simtec.co.uk/products/SWLINUX/ ++ * Written by Ben Dooks, ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++ ++struct clk { ++ struct list_head list; ++ struct module *owner; ++ struct clk *parent; ++ const char *name; ++ int id; ++ int usage; ++ unsigned long rate; ++ unsigned long ctrlbit; ++ ++ int (*enable)(struct clk *, int enable); ++ int (*set_rate)(struct clk *c, unsigned long rate); ++ unsigned long (*get_rate)(struct clk *c); ++ unsigned long (*round_rate)(struct clk *c, unsigned long rate); ++ int (*set_parent)(struct clk *c, struct clk *parent); ++}; ++ ++/* other clocks which may be registered by board support */ ++ ++extern struct clk s3c24xx_dclk0; ++extern struct clk s3c24xx_dclk1; ++extern struct clk s3c24xx_clkout0; ++extern struct clk s3c24xx_clkout1; ++extern struct clk s3c24xx_uclk; ++ ++extern struct clk clk_usb_bus; ++ ++/* core clock support */ ++ ++extern struct clk clk_f; ++extern struct clk clk_h; ++extern struct clk clk_p; ++extern struct clk clk_mpll; ++extern struct clk clk_upll; ++extern struct clk clk_epll; ++extern struct clk clk_xtal; ++extern struct clk clk_ext; ++ ++#ifdef CONFIG_CPU_S3C6410 ++extern struct clk clk_hx2; ++#endif ++ ++#ifdef CONFIG_CPU_S5P6440 ++extern struct clk clk_h_low; ++extern struct clk clk_p_low; ++#endif ++ ++#ifdef CONFIG_CPU_S5PC100 ++extern struct clk clk_hpll; ++extern struct clk clk_hd0; ++extern struct clk clk_pd0; ++extern struct clk clk_54m; ++extern struct clk clk_dout_mpll2; ++#endif ++ ++/* S3C64XX specific clocks */ ++extern struct clk clk_27m; ++extern struct clk clk_48m; ++ ++/* exports for arch/arm/mach-s3c2410 ++ * ++ * Please DO NOT use these outside of arch/arm/mach-s3c2410 ++*/ ++ ++extern spinlock_t clocks_lock; ++ ++extern int s3c2410_clkcon_enable(struct clk *clk, int enable); ++ ++extern int s3c24xx_register_clock(struct clk *clk); ++extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks); ++ ++extern int s3c24xx_register_baseclocks(unsigned long xtal); ++ ++extern void s3c64xx_register_clocks(void); ++extern void s5p64xx_register_clocks(void); ++ ++extern void s3c24xx_setup_clocks(unsigned long fclk, ++ unsigned long hclk, ++ unsigned long pclk); ++ ++extern void s3c2410_setup_clocks(void); ++extern void s3c2412_setup_clocks(void); ++extern void s3c244x_setup_clocks(void); ++extern void s3c2443_setup_clocks(void); ++ ++/* S3C64XX specific functions and clocks */ ++ ++extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable); ++extern int s5p64xx_sclk_ctrl(struct clk *clk, int enable); ++ ++#ifdef CONFIG_CPU_S5PC100 ++extern void s5pc1xx_register_clocks(void); ++extern int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable); ++extern int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable); ++#endif ++ ++#if defined(CONFIG_HAVE_PWM) || defined(CONFIG_TIMER_PWM) ++extern int s3c24xx_pwmclk_init(void); ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/cpu-freq.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/cpu-freq.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/cpu-freq.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/cpu-freq.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,94 @@ ++/* arch/arm/plat-s3c/include/plat/cpu-freq.h ++ * ++ * Copyright (c) 2006,2007 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S3C CPU frequency scaling support - driver and board ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++ ++struct s3c_cpufreq_info; ++struct s3c_cpufreq_board; ++struct s3c_iotimings; ++ ++struct s3c_freq { ++ unsigned long fclk; ++ unsigned long armclk; ++ unsigned long hclk_tns; /* in 10ths of ns */ ++ unsigned long hclk; ++ unsigned long pclk; ++}; ++ ++/* wrapper 'struct cpufreq_freqs' so that any drivers receiving the ++ * notification can use this information that is not provided by just ++ * having the core frequency alone. ++ */ ++ ++struct s3c_cpufreq_freqs { ++ struct cpufreq_freqs freqs; ++ struct s3c_freq old; ++ struct s3c_freq new; ++}; ++ ++#define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs) ++ ++struct s3c_clkdivs { ++ int p_divisor; /* fclk / pclk */ ++ int h_divisor; /* fclk / hclk */ ++ int arm_divisor; /* not all cpus have this. */ ++ unsigned char dvs; /* using dvs mode to arm. */ ++}; ++ ++#define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s)) ++ ++struct s3c_pllval { ++ unsigned long freq; ++ unsigned long pll_reg; ++}; ++ ++struct s3c_cpufreq_config { ++ struct s3c_freq freq; ++ struct s3c_pllval pll; ++ struct s3c_clkdivs divs; ++ struct s3c_cpufreq_info *info; /* for core, not drivers */ ++ struct s3c_cpufreq_board *board; ++}; ++ ++/* s3c_cpufreq_board ++ * ++ * per-board configuraton information, such as memory refresh and ++ * how to initialise IO timings. ++ */ ++struct s3c_cpufreq_board { ++ unsigned int refresh; /* refresh period in ns */ ++ unsigned int auto_io:1; /* automatically init io timings. */ ++ unsigned int need_io:1; /* set if needs io timing support. */ ++ ++ /* any non-zero field in here is taken as an upper limit. */ ++ struct s3c_freq max; /* frequency limits */ ++}; ++ ++/* Things depending on frequency scaling. */ ++#ifdef CONFIG_CPU_FREQ_S3C ++#define __init_or_cpufreq ++#else ++#define __init_or_cpufreq __init ++#endif ++ ++/* Board functions */ ++ ++#ifdef CONFIG_CPU_FREQ_S3C ++extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board); ++#else ++ ++static inline int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board) ++{ ++ return 0; ++} ++#endif /* CONFIG_CPU_FREQ_S3C */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/cpu.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/cpu.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/cpu.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/cpu.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,89 @@ ++/* linux/arch/arm/plat-s3c/include/plat/cpu.h ++ * ++ * Copyright (c) 2004-2005 Simtec Electronics ++ * Ben Dooks ++ * ++ * Header file for S3C24XX CPU support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++/* todo - fix when rmk changes iodescs to use `void __iomem *` */ ++ ++#if defined (CONFIG_ARCH_S3C2410) ++#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } ++#elif defined(CONFIG_ARCH_S3C64XX) ++#define IODESC_ENT(x) { (unsigned long)S3C64XX_VA_##x, __phys_to_pfn(S3C64XX_PA_##x), S3C64XX_SZ_##x, MT_DEVICE } ++#elif defined(CONFIG_ARCH_S5P64XX) ++#define IODESC_ENT(x) { (unsigned long)S5P64XX_VA_##x, __phys_to_pfn(S5P64XX_PA_##x), S5P64XX_SZ_##x, MT_DEVICE } ++#elif defined(CONFIG_ARCH_S5PC1XX) ++#define IODESC_ENT(x) { (unsigned long)S5PC1XX_VA_##x, __phys_to_pfn(S5PC1XX_PA_##x), S5PC1XX_SZ_##x, MT_DEVICE } ++#else ++#error IODESC_ENT(x) macro should be defined! ++#endif ++ ++#ifndef MHZ ++#define MHZ (1000*1000) ++#endif ++ ++#define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000) ++ ++/* forward declaration */ ++struct s3c24xx_uart_resources; ++struct platform_device; ++struct s3c2410_uartcfg; ++struct map_desc; ++ ++/* per-cpu initialisation function table. */ ++ ++struct cpu_table { ++ unsigned long idcode; ++ unsigned long idmask; ++ void (*map_io)(void); ++ void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no); ++ void (*init_clocks)(int xtal); ++ int (*init)(void); ++ const char *name; ++}; ++ ++extern void s3c_init_cpu(unsigned long idcode, ++ struct cpu_table *cpus, unsigned int cputab_size); ++ ++/* core initialisation functions */ ++ ++extern void s3c24xx_init_irq(void); ++extern void s3c64xx_init_irq(u32 vic0, u32 vic1); ++extern void s5p64xx_init_irq(u32 vic0, u32 vic1); ++extern void s5pc1xx_init_irq(u32 vic0, u32 vic1, u32 vic2); ++ ++extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); ++extern void s3c64xx_init_io(struct map_desc *mach_desc, int size); ++extern void s5p64xx_init_io(struct map_desc *mach_desc, int size); ++extern void s5pc1xx_init_io(struct map_desc *mach_desc, int size); ++ ++extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no); ++ ++extern void s3c24xx_init_clocks(int xtal); ++ ++extern void s3c24xx_init_uartdevs(char *name, ++ struct s3c24xx_uart_resources *res, ++ struct s3c2410_uartcfg *cfg, int no); ++ ++/* timer for 2410/2440 */ ++ ++struct sys_timer; ++extern struct sys_timer s3c24xx_timer; ++extern struct sys_timer s3c64xx_timer; ++/* system device classes */ ++ ++extern struct sysdev_class s3c2410_sysclass; ++extern struct sysdev_class s3c2412_sysclass; ++extern struct sysdev_class s3c2440_sysclass; ++extern struct sysdev_class s3c2442_sysclass; ++extern struct sysdev_class s3c2443_sysclass; ++ ++extern struct sysdev_class s3c6410_sysclass; ++extern struct sysdev_class s5p6440_sysclass; ++extern struct sysdev_class s5pc100_sysclass; +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/debug-macro.S linux-2.6.28.6/arch/arm/plat-s3c/include/plat/debug-macro.S +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/debug-macro.S 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/debug-macro.S 2009-04-30 09:36:37.000000000 +0200 +@@ -1,4 +1,4 @@ +-/* linux/include/asm-arm/plat-s3c/debug-macro.S ++/* linux/arch/arm/plat-s3c/include/plat/debug-macro.S + * + * Copyright 2005, 2007 Simtec Electronics + * http://armlinux.simtec.co.uk/ +@@ -20,7 +20,7 @@ + .endm + + #ifndef fifo_level +-#define fifo_level fifo_level_s3c2410 ++#define fifo_level fifo_level_s3c2440 + #endif + + .macro fifo_full_s3c2440 rd, rx +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/devs.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/devs.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/devs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/devs.h 2010-04-07 07:46:30.000000000 +0200 +@@ -0,0 +1,81 @@ ++/* linux/arch/arm/plat-s3c/include/plat/devs.h ++ * ++ * Copyright (c) 2004 Simtec Electronics ++ * Ben Dooks ++ * ++ * Header file for s3c2410 standard platform devices ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++#include ++ ++struct s3c24xx_uart_resources { ++ struct resource *resources; ++ unsigned long nr_resources; ++}; ++ ++extern struct s3c24xx_uart_resources s3c2410_uart_resources[]; ++extern struct s3c24xx_uart_resources s3c64xx_uart_resources[]; ++extern struct s3c24xx_uart_resources s5p64xx_uart_resources[]; ++extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[]; ++ ++extern struct platform_device *s3c24xx_uart_devs[]; ++extern struct platform_device *s3c24xx_uart_src[]; ++ ++extern struct platform_device s3c_device_timer[]; ++ ++extern struct platform_device s3c_device_usb; ++extern struct platform_device s3c_device_lcd; ++extern struct platform_device s3c_device_g2d; ++extern struct platform_device s3c_device_g3d; ++extern struct platform_device s3c_device_vpp; ++extern struct platform_device s3c_device_tvenc; ++extern struct platform_device s3c_device_tvscaler; ++extern struct platform_device s3c_device_rotator; ++extern struct platform_device s3c_device_jpeg; ++extern struct platform_device s3c_device_wdt; ++extern struct platform_device s3c_device_i2c0; ++extern struct platform_device s3c_device_i2c1; ++extern struct platform_device s3c_device_iis; ++extern struct platform_device s3c_device_rtc; ++extern struct platform_device s3c_device_adc; ++extern struct platform_device s3c_device_sdi; ++extern struct platform_device s3c_device_hsmmc0; ++extern struct platform_device s3c_device_hsmmc1; ++extern struct platform_device s3c_device_hsmmc2; ++ ++extern struct platform_device s3c_device_spi0; ++extern struct platform_device s3c_device_spi1; ++ ++extern struct platform_device s3c_device_nand; ++extern struct platform_device s3c_device_onenand; ++ ++extern struct platform_device s3c_device_usbgadget; ++extern struct platform_device s3c_device_usb_otghcd; ++extern struct platform_device s3c_device_keypad; ++extern struct platform_device s3c_device_ts; ++extern struct platform_device s3c_device_g3d; ++ ++extern struct platform_device s3c_device_dm9000; ++ ++extern struct platform_device s3c_device_fimc0; ++extern struct platform_device s3c_device_fimc1; ++ ++extern struct platform_device s3c_device_mfc; ++extern struct platform_device s3c_device_ac97; ++ ++extern struct platform_device s3c_device_fimc0; ++extern struct platform_device s3c_device_fimc1; ++extern struct platform_device s3c_device_fimc2; ++ ++extern struct platform_device s3c_device_csis; ++ ++/* s3c2440 specific devices */ ++ ++#ifdef CONFIG_CPU_S3C2440 ++ ++extern struct platform_device s3c_device_camif; ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,194 @@ ++/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg-helper.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S3C Platform - GPIO pin configuration helper definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++/* This is meant for core cpu support, machine or other driver files ++ * should not be including this header. ++ */ ++ ++#ifndef __PLAT_GPIO_CFG_HELPERS_H ++#define __PLAT_GPIO_CFG_HELPERS_H __FILE__ ++ ++/* As a note, all gpio configuration functions are entered exclusively, either ++ * with the relevant lock held or the system prevented from doing anything else ++ * by disabling interrupts. ++*/ ++ ++static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip, ++ unsigned int off, unsigned int config) ++{ ++ return (chip->config->set_config)(chip, off, config); ++} ++ ++static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip, ++ unsigned int off, s3c_gpio_pull_t pull) ++{ ++ return (chip->config->set_pull)(chip, off, pull); ++} ++ ++/** ++ * s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration. ++ * @chip: The gpio chip that is being configured. ++ * @off: The offset for the GPIO being configured. ++ * @cfg: The configuration value to set. ++ * ++ * This helper deal with the GPIO cases where the control register ++ * has two bits of configuration per gpio, which have the following ++ * functions: ++ * 00 = input ++ * 01 = output ++ * 1x = special function ++*/ ++extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip, ++ unsigned int off, unsigned int cfg); ++ ++/** ++ * s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A) ++ * @chip: The gpio chip that is being configured. ++ * @off: The offset for the GPIO being configured. ++ * @cfg: The configuration value to set. ++ * ++ * This helper deal with the GPIO cases where the control register ++ * has one bit of configuration for the gpio, where setting the bit ++ * means the pin is in special function mode and unset means output. ++*/ ++extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip, ++ unsigned int off, unsigned int cfg); ++ ++/** ++ * s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config. ++ * @chip: The gpio chip that is being configured. ++ * @off: The offset for the GPIO being configured. ++ * @cfg: The configuration value to set. ++ * ++ * This helper deal with the GPIO cases where the control register has 4 bits ++ * of control per GPIO, generally in the form of: ++ * 0000 = Input ++ * 0001 = Output ++ * others = Special functions (dependant on bank) ++ * ++ * Note, since the code to deal with the case where there are two control ++ * registers instead of one, we do not have a seperate set of functions for ++ * each case. ++*/ ++extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, ++ unsigned int off, unsigned int cfg); ++ ++/** ++ * s3c_gpio_setcfg_s5pc1xx - S5PC1XX 4bit single register GPIO config. ++ * @chip: The gpio chip that is being configured. ++ * @off: The offset for the GPIO being configured. ++ * @cfg: The configuration value to set. ++ * ++ * This helper deal with the GPIO cases where the control register has 4 bits ++ * of control per GPIO, generally in the form of: ++ * 0000 = Input ++ * 0001 = Output ++ * others = Special functions (dependant on bank) ++ * ++ * Note, since the code to deal with the case where there are two control ++ * registers instead of one, we do not have a seperate set of functions for ++ * each case. ++*/ ++extern int s3c_gpio_setcfg_s5pc1xx(struct s3c_gpio_chip *chip, ++ unsigned int off, unsigned int cfg); ++ ++/* Pull-{up,down} resistor controls. ++ * ++ * S3C2410,S3C2440,S3C24A0 = Pull-UP, ++ * S3C2412,S3C2413 = Pull-Down ++ * S3C6400,S3C6410 = Pull-Both [None,Down,Up,Undef] ++ * S3C2443 = Pull-Both [not same as S3C6400] ++ */ ++ ++/** ++ * s3c_gpio_setpull_1up() - Pull configuration for choice of up or none. ++ * @chip: The gpio chip that is being configured. ++ * @off: The offset for the GPIO being configured. ++ * @param: pull: The pull mode being requested. ++ * ++ * This is a helper function for the case where we have GPIOs with one ++ * bit configuring the presence of a pull-up resistor. ++ */ ++extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip, ++ unsigned int off, s3c_gpio_pull_t pull); ++ ++/** ++ * s3c_gpio_setpull_1down() - Pull configuration for choice of down or none ++ * @chip: The gpio chip that is being configured ++ * @off: The offset for the GPIO being configured ++ * @param: pull: The pull mode being requested ++ * ++ * This is a helper function for the case where we have GPIOs with one ++ * bit configuring the presence of a pull-down resistor. ++ */ ++extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip, ++ unsigned int off, s3c_gpio_pull_t pull); ++ ++/** ++ * s3c_gpio_setpull_upown() - Pull configuration for choice of up, down or none ++ * @chip: The gpio chip that is being configured. ++ * @off: The offset for the GPIO being configured. ++ * @param: pull: The pull mode being requested. ++ * ++ * This is a helper function for the case where we have GPIOs with two ++ * bits configuring the presence of a pull resistor, in the following ++ * order: ++ * 00 = No pull resistor connected ++ * 01 = Pull-up resistor connected ++ * 10 = Pull-down resistor connected ++ */ ++extern int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip, ++ unsigned int off, s3c_gpio_pull_t pull); ++ ++ ++/** ++ * s3c_gpio_getpull_updown() - Get configuration for choice of up, down or none ++ * @chip: The gpio chip that the GPIO pin belongs to ++ * @off: The offset to the pin to get the configuration of. ++ * ++ * This helper function reads the state of the pull-{up,down} resistor for the ++ * given GPIO in the same case as s3c_gpio_setpull_upown. ++*/ ++extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip, ++ unsigned int off); ++ ++/** ++ * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443. ++ * @chip: The gpio chip that is being configured. ++ * @off: The offset for the GPIO being configured. ++ * @param: pull: The pull mode being requested. ++ * ++ * This is a helper function for the case where we have GPIOs with two ++ * bits configuring the presence of a pull resistor, in the following ++ * order: ++ * 00 = Pull-up resistor connected ++ * 10 = Pull-down resistor connected ++ * x1 = No pull up resistor ++ */ ++extern int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip, ++ unsigned int off, s3c_gpio_pull_t pull); ++ ++/** ++ * s3c_gpio_getpull_s3c2443() - Get configuration for s3c2443 pull resistors ++ * @chip: The gpio chip that the GPIO pin belongs to. ++ * @off: The offset to the pin to get the configuration of. ++ * ++ * This helper function reads the state of the pull-{up,down} resistor for the ++ * given GPIO in the same case as s3c_gpio_setpull_upown. ++*/ ++extern s3c_gpio_pull_t s3c_gpio_getpull_s3c24xx(struct s3c_gpio_chip *chip, ++ unsigned int off); ++ ++#endif /* __PLAT_GPIO_CFG_HELPERS_H */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/gpio-cfg.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/gpio-cfg.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/gpio-cfg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/gpio-cfg.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,110 @@ ++/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S3C Platform - GPIO pin configuration ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++/* This file contains the necessary definitions to get the basic gpio ++ * pin configuration done such as setting a pin to input or output or ++ * changing the pull-{up,down} configurations. ++ */ ++ ++/* Note, this interface is being added to the s3c64xx arch first and will ++ * be added to the s3c24xx systems later. ++ */ ++ ++#ifndef __PLAT_GPIO_CFG_H ++#define __PLAT_GPIO_CFG_H __FILE__ ++ ++typedef unsigned int __bitwise__ s3c_gpio_pull_t; ++ ++/* forward declaration if gpio-core.h hasn't been included */ ++struct s3c_gpio_chip; ++ ++/** ++ * struct s3c_gpio_cfg GPIO configuration ++ * @cfg_eint: Configuration setting when used for external interrupt source ++ * @get_pull: Read the current pull configuration for the GPIO ++ * @set_pull: Set the current pull configuraiton for the GPIO ++ * @set_config: Set the current configuration for the GPIO ++ * @get_config: Read the current configuration for the GPIO ++ * ++ * Each chip can have more than one type of GPIO bank available and some ++ * have different capabilites even when they have the same control register ++ * layouts. Provide an point to vector control routine and provide any ++ * per-bank configuration information that other systems such as the ++ * external interrupt code will need. ++ */ ++struct s3c_gpio_cfg { ++ unsigned int cfg_eint; ++ ++ s3c_gpio_pull_t (*get_pull)(struct s3c_gpio_chip *chip, unsigned offs); ++ int (*set_pull)(struct s3c_gpio_chip *chip, unsigned offs, ++ s3c_gpio_pull_t pull); ++ ++ unsigned (*get_config)(struct s3c_gpio_chip *chip, unsigned offs); ++ int (*set_config)(struct s3c_gpio_chip *chip, unsigned offs, ++ unsigned config); ++}; ++ ++#define S3C_GPIO_SPECIAL_MARK (0xfffffff0) ++#define S3C_GPIO_SPECIAL(x) (S3C_GPIO_SPECIAL_MARK | (x)) ++ ++/* Defines for generic pin configurations */ ++#define S3C_GPIO_INPUT (S3C_GPIO_SPECIAL(0)) ++#define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1)) ++#define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x)) ++ ++#define s3c_gpio_is_cfg_special(_cfg) \ ++ (((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK) ++ ++/** ++ * s3c_gpio_cfgpin() - Change the GPIO function of a pin. ++ * @pin pin The pin number to configure. ++ * @pin to The configuration for the pin's function. ++ * ++ * Configure which function is actually connected to the external ++ * pin, such as an gpio input, output or some form of special function ++ * connected to an internal peripheral block. ++ */ ++extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to); ++ ++/* Define values for the pull-{up,down} available for each gpio pin. ++ * ++ * These values control the state of the weak pull-{up,down} resistors ++ * available on most pins on the S3C series. Not all chips support both ++ * up or down settings, and it may be dependant on the chip that is being ++ * used to whether the particular mode is available. ++ */ ++#define S3C_GPIO_PULL_NONE ((__force s3c_gpio_pull_t)0x00) ++#define S3C_GPIO_PULL_DOWN ((__force s3c_gpio_pull_t)0x01) ++#define S3C_GPIO_PULL_UP ((__force s3c_gpio_pull_t)0x02) ++ ++/** ++ * s3c_gpio_setpull() - set the state of a gpio pin pull resistor ++ * @pin: The pin number to configure the pull resistor. ++ * @pull: The configuration for the pull resistor. ++ * ++ * This function sets the state of the pull-{up,down} resistor for the ++ * specified pin. It will return 0 if successfull, or a negative error ++ * code if the pin cannot support the requested pull setting. ++*/ ++extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull); ++ ++/** ++ * s3c_gpio_getpull() - get the pull resistor state of a gpio pin ++ * @pin: The pin number to get the settings for ++ * ++ * Read the pull resistor value for the specified pin. ++*/ ++extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin); ++ ++#endif /* __PLAT_GPIO_CFG_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/gpio-core.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/gpio-core.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/gpio-core.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/gpio-core.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,77 @@ ++/* linux/arch/arm/plat-s3c/include/plat/gpio-core.h ++ * ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S3C Platform - GPIO core ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++/* Define the core gpiolib support functions that the s3c platforms may ++ * need to extend or change depending on the hardware and the s3c chip ++ * selected at build or found at run time. ++ * ++ * These definitions are not intended for driver inclusion, there is ++ * nothing here that should not live outside the platform and core ++ * specific code. ++*/ ++ ++struct s3c_gpio_cfg; ++ ++/** ++ * struct s3c_gpio_chip - wrapper for specific implementation of gpio ++ * @chip: The chip structure to be exported via gpiolib. ++ * @base: The base pointer to the gpio configuration registers. ++ * @config: special function and pull-resistor control information. ++ * ++ * This wrapper provides the necessary information for the Samsung ++ * specific gpios being registered with gpiolib. ++ */ ++struct s3c_gpio_chip { ++ struct gpio_chip chip; ++ struct s3c_gpio_cfg *config; ++ void __iomem *base; ++}; ++ ++static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc) ++{ ++ return container_of(gpc, struct s3c_gpio_chip, chip); ++} ++ ++/** s3c_gpiolib_add() - add the s3c specific version of a gpio_chip. ++ * @chip: The chip to register ++ * ++ * This is a wrapper to gpiochip_add() that takes our specific gpio chip ++ * information and makes the necessary alterations for the platform and ++ * notes the information for use with the configuration systems and any ++ * other parts of the system. ++ */ ++extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip); ++ ++/* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios ++ * for use with the configuration calls, and other parts of the s3c gpiolib ++ * support code. ++ * ++ * Not all s3c support code will need this, as some configurations of cpu ++ * may only support one or two different configuration options and have an ++ * easy gpio to s3c_gpio_chip mapping function. If this is the case, then ++ * the machine support file should provide its own s3c_gpiolib_getchip() ++ * and any other necessary functions. ++ */ ++ ++#ifdef CONFIG_S3C_GPIO_TRACK ++extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; ++ ++static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip) ++{ ++ return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL; ++} ++#else ++/* machine specific code should provide s3c_gpiolib_getchip */ ++ ++static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { } ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/hsmmc.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/hsmmc.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/hsmmc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/hsmmc.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,47 @@ ++#ifndef __ASM_S3C_HSMMC_H ++#define __ASM_S3C_HSMMC_H ++ ++#ifndef __ASSEMBLY__ ++ ++#include ++#include ++ ++#define NUM_OF_HSMMC_CLKSOURCES 1 ++ ++#define SPEED_NORMAL 0 ++#define SPEED_HIGH 1 ++ ++struct s3c_hsmmc_fd_cfg { ++ ulong ctrl2; ++ ulong ctrl3[2]; /* 0: low speed, 1: high speed */ ++ ulong ctrl4; ++}; ++ ++struct s3c_hsmmc_clk_cfg { ++ char *name; ++ u32 src; ++}; ++ ++struct s3c_hsmmc_cfg { ++ u32 hwport; /* hardware port number */ ++ u32 enabled; /* if port is used, set 1 */ ++ u32 host_caps; /* host capabilities */ ++ u32 bus_width; /* bus width */ ++ ++ void *base; /* base address of host */ ++ ++ u8 highspeed; /* ENHIGHSPD bit configuration */ ++ ++ /* feedback delay control configuration (0: mmc, 1: sd) */ ++ struct s3c_hsmmc_fd_cfg fd_ctrl[2]; ++ ++ /* clock source control */ ++ struct s3c_hsmmc_clk_cfg clocks[NUM_OF_HSMMC_CLKSOURCES]; ++}; ++ ++extern void hsmmc_set_gpio(uint channel, uint width); ++ ++#endif /* __ASSEMBLY__ */ ++ ++#endif /* __ASM_S3C_HSMMC_H */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/iic-core.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/iic-core.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/iic-core.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/iic-core.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,35 @@ ++/* linux/arch/arm/plat-s3c/include/plat/iic-core.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * ++ * S3C - I2C Controller core functions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_IIC_CORE_H ++#define __ASM_ARCH_IIC_CORE_H __FILE__ ++ ++/* These functions are only for use with the core support code, such as ++ * the cpu specific initialisation code ++ */ ++ ++/* re-define device name depending on support. */ ++static inline void s3c_i2c0_setname(char *name) ++{ ++ /* currently this device is always compiled in */ ++ s3c_device_i2c0.name = name; ++} ++ ++static inline void s3c_i2c1_setname(char *name) ++{ ++#ifdef CONFIG_S3C_DEV_I2C1 ++ s3c_device_i2c1.name = name; ++#endif ++} ++ ++#endif /* __ASM_ARCH_IIC_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/iic.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/iic.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/iic.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/iic.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,57 @@ ++/* linux/arch/arm/plat-s3c/include/plat/iic.h ++ * ++ * Copyright (c) 2004 Simtec Electronics ++ * Ben Dooks ++ * ++ * S3C2410 - I2C Controller platfrom_device info ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_IIC_H ++#define __ASM_ARCH_IIC_H __FILE__ ++ ++#define S3C_IICFLG_FILTER (1<<0) /* enable s3c2440 filter */ ++ ++/* Notes: ++ * 1) All frequencies are expressed in Hz ++ * 2) A value of zero is `do not care` ++*/ ++ ++struct s3c2410_platform_i2c { ++ int bus_num; /* bus number to use */ ++ unsigned int flags; ++ unsigned int slave_addr; /* slave address for controller */ ++ unsigned long bus_freq; /* standard bus frequency */ ++ unsigned long max_freq; /* max frequency for the bus */ ++ unsigned long min_freq; /* min frequency for the bus */ ++ unsigned int sda_delay; /* pclks (s3c2440 only) */ ++ ++ void (*cfg_gpio)(struct platform_device *dev); ++}; ++ ++/** ++ * s3c_i2c0_set_platdata - set platform data for i2c0 device ++ * @i2c: The platform data to set, or NULL for default data. ++ * ++ * Register the given platform data for use with the i2c0 device. This ++ * call copies the platform data, so the caller can use __initdata for ++ * their copy. ++ * ++ * This call will set cfg_gpio if is null to the default platform ++ * implementation. ++ * ++ * Any user of s3c_device_i2c0 should call this, even if it is with ++ * NULL to ensure that the device is given the default platform data ++ * as the driver will no longer carry defaults. ++ */ ++extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c); ++extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c); ++ ++/* defined by architecture to configure gpio */ ++extern void s3c_i2c0_cfg_gpio(struct platform_device *dev); ++extern void s3c_i2c1_cfg_gpio(struct platform_device *dev); ++ ++#endif /* __ASM_ARCH_IIC_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/map-base.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/map-base.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/map-base.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/map-base.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,44 @@ ++/* linux/arch/arm/plat-s3c/include/plat/map-base.h ++ * ++ * Copyright 2003, 2007 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S3C - Memory map definitions (virtual addresses) ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_PLAT_MAP_H ++#define __ASM_PLAT_MAP_H __FILE__ ++ ++/* Fit all our registers in at 0xF4000000 upwards, trying to use as ++ * little of the VA space as possible so vmalloc and friends have a ++ * better chance of getting memory. ++ * ++ * we try to ensure stuff like the IRQ registers are available for ++ * an single MOVS instruction (ie, only 8 bits of set data) ++ */ ++ ++#define S3C_ADDR_BASE (0xF4000000) ++ ++#ifndef __ASSEMBLY__ ++#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x)) ++#else ++#define S3C_ADDR(x) (S3C_ADDR_BASE + (x)) ++#endif ++ ++#define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */ ++#define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */ ++#define S3C_VA_MEM S3C_ADDR(0x00200000) /* system control */ ++#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */ ++#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */ ++#define S3C_VA_LCD S3C_ADDR(0x00600000) /* LCD */ ++#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */ ++#define S3C_VA_SROMC S3C_ADDR(0x01100000) /* SROM SFR */ ++#define S3C_VA_SYSTIMER S3C_ADDR(0x01200000) /* SROM SFR */ ++#define S3C_VA_NAND S3C_ADDR(0x01400000) /* NAND */ ++ ++#endif /* __ASM_PLAT_MAP_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/map.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/map.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/map.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/map.h 2009-04-30 09:36:37.000000000 +0200 +@@ -1,4 +1,4 @@ +-/* linux/include/asm-arm/plat-s3c/map.h ++/* linux/arch/arm/plat-s3c/include/plat/map.h + * + * Copyright 2003, 2007 Simtec Electronics + * http://armlinux.simtec.co.uk/ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/nand.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/nand.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/nand.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/nand.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,55 @@ ++/* linux/arch/arm/plat-s3c/include/plat/nand.h ++ * ++ * Copyright (c) 2004 Simtec Electronics ++ * Ben Dooks ++ * ++ * S3C2410 - NAND device controller platfrom_device info ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++/* struct s3c2410_nand_set ++ * ++ * define an set of one or more nand chips registered with an unique mtd ++ * ++ * nr_chips = number of chips in this set ++ * nr_partitions = number of partitions pointed to be partitoons (or zero) ++ * name = name of set (optional) ++ * nr_map = map for low-layer logical to physical chip numbers (option) ++ * partitions = mtd partition list ++*/ ++ ++struct s3c2410_nand_set { ++ unsigned int disable_ecc : 1; ++ ++ int nr_chips; ++ int nr_partitions; ++ char *name; ++ int *nr_map; ++ struct mtd_partition *partitions; ++ struct nand_ecclayout *ecc_layout; ++}; ++ ++struct s3c2410_platform_nand { ++ /* timing information for controller, all times in nanoseconds */ ++ ++ int tacls; /* time for active CLE/ALE to nWE/nOE */ ++ int twrph0; /* active time for nWE/nOE */ ++ int twrph1; /* time for release CLE/ALE from nWE/nOE inactive */ ++ ++ unsigned int ignore_unset_ecc : 1; ++ ++ int nr_sets; ++ struct s3c2410_nand_set *sets; ++ ++ void (*select_chip)(struct s3c2410_nand_set *, ++ int chip); ++}; ++ ++struct s3c_nand_mtd_info { ++ uint chip_nr; ++ uint mtd_part_nr; ++ struct mtd_partition *partition; ++}; +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/partition.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/partition.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/partition.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/partition.h 2010-04-16 05:13:12.000000000 +0200 +@@ -0,0 +1,44 @@ ++/* linux/arch/arm/plat-s3c/include/plat/partition.h ++ * ++ * Copyright (c) 2008 Samsung Electronics ++ * ++ * Partition information ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++ ++struct mtd_partition s3c_partition_info[] = { ++ { ++ .name = "Bootloader", ++ .offset = 0, ++ .size = (4 * 128 *SZ_1K), ++ .mask_flags = MTD_CAP_NANDFLASH, ++ }, ++ { ++ .name = "Kernel", ++ .offset = (4 * 128 *SZ_1K), ++ .size = (5*SZ_1M) , ++ .mask_flags = MTD_CAP_NANDFLASH, ++ }, ++ { ++ .name = "File System", ++ .offset = MTDPART_OFS_APPEND, ++ .size = MTDPART_SIZ_FULL, ++ } ++}; ++ ++struct s3c_nand_mtd_info s3c_nand_mtd_part_info = { ++ .chip_nr = 1, ++ .mtd_part_nr = ARRAY_SIZE(s3c_partition_info), ++ .partition = s3c_partition_info, ++}; ++ ++struct flash_platform_data s3c_onenand_data = { ++ .parts = s3c_partition_info, ++ .nr_parts = ARRAY_SIZE(s3c_partition_info), ++}; ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-ac97.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-ac97.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-ac97.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-ac97.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,67 @@ ++/* linux/arch/arm/plat-s3c/include/plat/regs-ac97.h ++ * ++ * Copyright (c) 2006 Simtec Electronics ++ * http://www.simtec.co.uk/products/SWLINUX/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C2440 AC97 Controller ++*/ ++ ++#ifndef __ASM_ARCH_REGS_AC97_H ++#define __ASM_ARCH_REGS_AC97_H __FILE__ ++ ++#define S3C_AC97_GLBCTRL (0x00) ++ ++#define S3C_AC97_GLBCTRL_CODECREADYIE (1<<22) ++#define S3C_AC97_GLBCTRL_PCMOUTURIE (1<<21) ++#define S3C_AC97_GLBCTRL_PCMINORIE (1<<20) ++#define S3C_AC97_GLBCTRL_MICINORIE (1<<19) ++#define S3C_AC97_GLBCTRL_PCMOUTTIE (1<<18) ++#define S3C_AC97_GLBCTRL_PCMINTIE (1<<17) ++#define S3C_AC97_GLBCTRL_MICINTIE (1<<16) ++#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF (0<<12) ++#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO (1<<12) ++#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA (2<<12) ++#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK (3<<12) ++#define S3C_AC97_GLBCTRL_PCMINTM_OFF (0<<10) ++#define S3C_AC97_GLBCTRL_PCMINTM_PIO (1<<10) ++#define S3C_AC97_GLBCTRL_PCMINTM_DMA (2<<10) ++#define S3C_AC97_GLBCTRL_PCMINTM_MASK (3<<10) ++#define S3C_AC97_GLBCTRL_MICINTM_OFF (0<<8) ++#define S3C_AC97_GLBCTRL_MICINTM_PIO (1<<8) ++#define S3C_AC97_GLBCTRL_MICINTM_DMA (2<<8) ++#define S3C_AC97_GLBCTRL_MICINTM_MASK (3<<8) ++#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE (1<<3) ++#define S3C_AC97_GLBCTRL_ACLINKON (1<<2) ++#define S3C_AC97_GLBCTRL_WARMRESET (1<<1) ++#define S3C_AC97_GLBCTRL_COLDRESET (1<<0) ++ ++#define S3C_AC97_GLBSTAT (0x04) ++ ++#define S3C_AC97_GLBSTAT_CODECREADY (1<<22) ++#define S3C_AC97_GLBSTAT_PCMOUTUR (1<<21) ++#define S3C_AC97_GLBSTAT_PCMINORI (1<<20) ++#define S3C_AC97_GLBSTAT_MICINORI (1<<19) ++#define S3C_AC97_GLBSTAT_PCMOUTTI (1<<18) ++#define S3C_AC97_GLBSTAT_PCMINTI (1<<17) ++#define S3C_AC97_GLBSTAT_MICINTI (1<<16) ++#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE (0<<0) ++#define S3C_AC97_GLBSTAT_MAINSTATE_INIT (1<<0) ++#define S3C_AC97_GLBSTAT_MAINSTATE_READY (2<<0) ++#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE (3<<0) ++#define S3C_AC97_GLBSTAT_MAINSTATE_LP (4<<0) ++#define S3C_AC97_GLBSTAT_MAINSTATE_WARM (5<<0) ++ ++#define S3C_AC97_CODEC_CMD (0x08) ++ ++#define S3C_AC97_CODEC_CMD_READ (1<<23) ++ ++#define S3C_AC97_STAT (0x0c) ++#define S3C_AC97_PCM_ADDR (0x10) ++#define S3C_AC97_PCM_DATA (0x18) ++#define S3C_AC97_MIC_DATA (0x1C) ++ ++#endif /* __ASM_ARCH_REGS_AC97_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-adc.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-adc.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-adc.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-adc.h 2009-04-30 09:36:37.000000000 +0200 +@@ -1,4 +1,4 @@ +-/* arch/arm/mach-s3c2410/include/mach/regs-adc.h ++/* linux/arch/arm/plat-s3c/include/plat/regs-adc.h + * + * Copyright (c) 2004 Shannon Holland + * +@@ -19,15 +19,24 @@ + #define S3C2410_ADCDLY S3C2410_ADCREG(0x08) + #define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C) + #define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10) ++#define S3C2410_ADCUPDN S3C2410_ADCREG(0x14) ++#define S3C2443_ADCMUX S3C2410_ADCREG(0x18) ++#define S3C6400_ADCCLRINT S3C2410_ADCREG(0x18) ++#define S3C6400_ADCCLRWK S3C2410_ADCREG(0x20) + + + /* ADCCON Register Bits */ ++#define S3C6410_ADCCON_RESSEL_10BIT (0x0<<16) ++#define S3C6410_ADCCON_RESSEL_12BIT (0x1<<16) + #define S3C2410_ADCCON_ECFLG (1<<15) + #define S3C2410_ADCCON_PRSCEN (1<<14) + #define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6) + #define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6) + #define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3) ++#define S3C2443_ADCCON_SELMUX(x) (((x)&0xF)<<0) + #define S3C2410_ADCCON_MUXMASK (0x7<<3) ++#define S3C2450_ADCCON_RESSEL_10BIT (0x0<<3) ++#define S3C2450_ADCCON_RESSEL_12BIT (0x1<<3) + #define S3C2410_ADCCON_STDBM (1<<2) + #define S3C2410_ADCCON_READ_START (1<<1) + #define S3C2410_ADCCON_ENABLE_START (1<<0) +@@ -35,6 +44,7 @@ + + + /* ADCTSC Register Bits */ ++#define S3C2410_ADCTSC_UD_SEN (1<<8) + #define S3C2410_ADCTSC_YM_SEN (1<<7) + #define S3C2410_ADCTSC_YP_SEN (1<<6) + #define S3C2410_ADCTSC_XM_SEN (1<<5) +@@ -55,6 +65,65 @@ + #define S3C2410_ADCDAT1_XY_PST (0x3<<12) + #define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF) + ++/*--------------------------- Common definitions for S3C ---------------------------*/ ++/* The following definitions will be applied to S3C24XX, S3C64XX, S5PC1XX. */ ++/*-----------------------------------------------------------------------------------*/ ++ ++#define S3C_ADCREG(x) (x) ++ ++#define S3C_ADCCON S3C_ADCREG(0x00) ++#define S3C_ADCTSC S3C_ADCREG(0x04) ++#define S3C_ADCDLY S3C_ADCREG(0x08) ++#define S3C_ADCDAT0 S3C_ADCREG(0x0C) ++#define S3C_ADCDAT1 S3C_ADCREG(0x10) ++#define S3C_ADCUPDN S3C_ADCREG(0x14) ++#define S3C_ADCCLRINT S3C_ADCREG(0x18) ++#define S3C_ADCMUX S3C_ADCREG(0x1C) ++#define S3C_ADCCLRWK S3C_ADCREG(0x20) ++ ++ ++/* ADCCON Register Bits */ ++#define S3C_ADCCON_RESSEL_10BIT (0x0<<16) ++#define S3C_ADCCON_RESSEL_12BIT (0x1<<16) ++#define S3C_ADCCON_ECFLG (1<<15) ++#define S3C_ADCCON_PRSCEN (1<<14) ++#define S3C_ADCCON_PRSCVL(x) (((x)&0xFF)<<6) ++#define S3C_ADCCON_PRSCVLMASK (0xFF<<6) ++#define S3C_ADCCON_SELMUX(x) (((x)&0x7)<<3) ++#define S3C_ADCCON_SELMUX_1(x) (((x)&0xF)<<0) ++#define S3C_ADCCON_MUXMASK (0x7<<3) ++#define S3C_ADCCON_RESSEL_10BIT_1 (0x0<<3) ++#define S3C_ADCCON_RESSEL_12BIT_1 (0x1<<3) ++#define S3C_ADCCON_STDBM (1<<2) ++#define S3C_ADCCON_READ_START (1<<1) ++#define S3C_ADCCON_ENABLE_START (1<<0) ++#define S3C_ADCCON_STARTMASK (0x3<<0) ++ ++ ++/* ADCTSC Register Bits */ ++#define S3C_ADCTSC_UD_SEN (1<<8) ++#define S3C_ADCTSC_YM_SEN (1<<7) ++#define S3C_ADCTSC_YP_SEN (1<<6) ++#define S3C_ADCTSC_XM_SEN (1<<5) ++#define S3C_ADCTSC_XP_SEN (1<<4) ++#define S3C_ADCTSC_PULL_UP_DISABLE (1<<3) ++#define S3C_ADCTSC_AUTO_PST (1<<2) ++#define S3C_ADCTSC_XY_PST(x) (((x)&0x3)<<0) ++ ++/* ADCDAT0 Bits */ ++#define S3C_ADCDAT0_UPDOWN (1<<15) ++#define S3C_ADCDAT0_AUTO_PST (1<<14) ++#define S3C_ADCDAT0_XY_PST (0x3<<12) ++#define S3C_ADCDAT0_XPDATA_MASK (0x03FF) ++#define S3C_ADCDAT0_XPDATA_MASK_12BIT (0x0FFF) ++ ++/* ADCDAT1 Bits */ ++#define S3C_ADCDAT1_UPDOWN (1<<15) ++#define S3C_ADCDAT1_AUTO_PST (1<<14) ++#define S3C_ADCDAT1_XY_PST (0x3<<12) ++#define S3C_ADCDAT1_YPDATA_MASK (0x03FF) ++#define S3C_ADCDAT1_YPDATA_MASK_12BIT (0x0FFF) ++ + #endif /* __ASM_ARCH_REGS_ADC_H */ + + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-g2d.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-g2d.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-g2d.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-g2d.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,197 @@ ++/* linux/arch/arm/plat-s3c/include/plat/regs-g2d.h ++ * ++ * Driver file for Samsung 2D Accelerator(FIMG-2D) ++ * Jonghun Han, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++#ifndef __ASM_ARM_REGS_S3C_G2D_H ++#define __ASM_ARM_REGS_S3C_G2D_H ++ ++/************************************************************************/ ++/*Graphics 2D Registers part */ ++/************************************************************************/ ++#define S3C_G2DREG(x) ((x)) ++ ++/* Graphics 2D General Registers */ ++#define S3C_G2D_CONTROL_REG S3C_G2DREG(0x00) /* Control register */ ++#define S3C_G2D_INTEN_REG S3C_G2DREG(0x04) /* Interrupt enable register */ ++#define S3C_G2D_FIFO_INTC_REG S3C_G2DREG(0x08) /* Interrupt control register */ ++#define S3C_G2D_INTC_PEND_REG S3C_G2DREG(0x0c) /* Interrupt control pending register */ ++#define S3C_G2D_FIFO_STAT_REG S3C_G2DREG(0x10) /* Command FIFO status register */ ++ ++/* Graphics 2D Command Registers */ ++#define S3C_G2D_CMD0_REG S3C_G2DREG(0x100) /* Command register for Line/Point drawing */ ++#define S3C_G2D_CMD1_REG S3C_G2DREG(0x104) /* Command register for BitBLT */ ++#define S3C_G2D_CMD2_REG S3C_G2DREG(0x108) /* Command register for Host to Screen Bitblt transfer start */ ++#define S3C_G2D_CMD3_REG S3C_G2DREG(0x10c) /* Command register for Host to Screen Bitblt transfer continue */ ++#define S3C_G2D_CMD4_REG S3C_G2DREG(0x110) /* Command register for Color expansion (Font start) */ ++#define S3C_G2D_CMD5_REG S3C_G2DREG(0x114) /* Command register for Color expansion (Font continue) */ ++#define S3C_G2D_CMD6_REG S3C_G2DREG(0x118) /* Reserved */ ++#define S3C_G2D_CMD7_REG S3C_G2DREG(0x11c) /* Command register for Color expansion (memory to screen) */ ++ ++/* Graphics 2D Parameter Setting Registers */ ++/* Resolution */ ++#define S3C_G2D_SRC_RES_REG S3C_G2DREG(0x200) /* Source image resolution */ ++#define S3C_G2D_HORI_RES_REG S3C_G2DREG(0x204) /* Source image horizontal resolution */ ++#define S3C_G2D_VERT_RES_REG S3C_G2DREG(0x208) /* Source image vertical resolution */ ++#define S3C_G2D_SC_RES_REG S3C_G2DREG(0x210) /* Screen resolution */ ++#define S3C_G2D_SC_HORI_REG S3C_G2DREG(0x214) /* Screen horizontal resolutuon */ ++#define S3C_G2D_SC_VERT_REG S3C_G2DREG(0x218) /* Screen vertical resolution */ ++ ++/* Clipping window */ ++#define S3C_G2D_CW_LT_REG S3C_G2DREG(0x220) /* LeftTop coordinates of Clip Window */ ++#define S3C_G2D_CW_LT_X_REG S3C_G2DREG(0x224) /* Left X coordinate of Clip Window */ ++#define S3C_G2D_CW_LT_Y_REG S3C_G2DREG(0x228) /* Top Y coordinate of Clip Window */ ++#define S3C_G2D_CW_RB_REG S3C_G2DREG(0x230) /* RightBottom coordinate of Clip Window */ ++#define S3C_G2D_CW_RB_X_REG S3C_G2DREG(0x234) /* Right X coordinate of Clip Window */ ++#define S3C_G2D_CW_RB_Y_REG S3C_G2DREG(0x238) /* Bottom Y coordinate of Clip Window */ ++ ++/* Coordinates */ ++#define S3C_G2D_COORD0_REG S3C_G2DREG(0x300) ++#define S3C_G2D_COORD0_X_REG S3C_G2DREG(0x304) ++#define S3C_G2D_COORD0_Y_REG S3C_G2DREG(0x308) ++#define S3C_G2D_COORD1_REG S3C_G2DREG(0x310) ++#define S3C_G2D_COORD1_X_REG S3C_G2DREG(0x314) ++#define S3C_G2D_COORD1_Y_REG S3C_G2DREG(0x318) ++#define S3C_G2D_COORD2_REG S3C_G2DREG(0x320) ++#define S3C_G2D_COORD2_X_REG S3C_G2DREG(0x324) ++#define S3C_G2D_COORD2_Y_REG S3C_G2DREG(0x328) ++#define S3C_G2D_COORD3_REG S3C_G2DREG(0x330) ++#define S3C_G2D_COORD3_X_REG S3C_G2DREG(0x334) ++#define S3C_G2D_COORD3_Y_REG S3C_G2DREG(0x338) ++ ++/* Rotation */ ++#define S3C_G2D_ROT_OC_REG S3C_G2DREG(0x340) /* Rotation Origin Coordinates */ ++#define S3C_G2D_ROT_OC_X_REG S3C_G2DREG(0x344) /* X coordinate of Rotation Origin Coordinates */ ++#define S3C_G2D_ROT_OC_Y_REG S3C_G2DREG(0x348) /* Y coordinate of Rotation Origin Coordinates */ ++#define S3C_G2D_ROTATE_REG S3C_G2DREG(0x34c) /* Rotation Mode register */ ++#define S3C_G2D_ENDIA_READSIZE S3C_G2DREG(0x350) /* Reserved */ ++ ++/* X,Y Increment setting */ ++#define S3C_G2D_X_INCR_REG S3C_G2DREG(0x400) ++#define S3C_G2D_Y_INCR_REG S3C_G2DREG(0x404) ++#define S3C_G2D_ROP_REG S3C_G2DREG(0x410) ++#define S3C_G2D_ALPHA_REG S3C_G2DREG(0x420) ++ ++/* Color */ ++#define S3C_G2D_FG_COLOR_REG S3C_G2DREG(0x500) /* Foreground Color Alpha register */ ++#define S3C_G2D_BG_COLOR_REG S3C_G2DREG(0x504) /* Background Color register */ ++#define S3C_G2D_BS_COLOR_REG S3C_G2DREG(0x508) /* Blue Screen Color register */ ++#define S3C_G2D_SRC_COLOR_MODE S3C_G2DREG(0x510) /* Src Image Color Mode register */ ++#define S3C_G2D_DST_COLOR_MODE S3C_G2DREG(0x514) /* Dest Image Color Mode register */ ++ ++/* Pattern */ ++#define S3C_G2D_PATTERN_REG S3C_G2DREG(0x600) ++#define S3C_G2D_PATOFF_REG S3C_G2DREG(0x700) ++#define S3C_G2D_PATOFF_X_REG S3C_G2DREG(0x704) ++#define S3C_G2D_PATOFF_Y_REG S3C_G2DREG(0x708) ++#define S3C_G2D_STENCIL_CNTL_REG S3C_G2DREG(0x720) ++#define S3C_G2D_STENCIL_DR_MIN_REG S3C_G2DREG(0x724) ++#define S3C_G2D_STENCIL_DR_MAX_REG S3C_G2DREG(0x728) ++ ++#define S3C_G2D_SRC_BASE_ADDR S3C_G2DREG(0x730) /* Source image base address register */ ++#define S3C_G2D_DST_BASE_ADDR S3C_G2DREG(0x734) /* Dest image base address register */ ++ ++ ++/************************************************************************/ ++/* Bit definition part */ ++/************************************************************************/ ++#define S3C_G2D_FIFO_USED(x) (((x)&0x7f)>>1) ++ ++#define S3C_G2D_FULL_H(x) ((x)&0x7FF) ++#define S3C_G2D_FULL_V(x) (((x)&0x7FF)<<16) ++ ++#define S3C_G2D_ALPHA(x) ((x)&0xFF) ++ ++/* interrupt mode select */ ++#define S3C_G2D_INTC_PEND_REG_CLRSEL_LEVEL (1<<31) ++#define S3C_G2D_INTC_PEND_REG_CLRSEL_PULSE (0<<31) ++ ++#define S3C_G2D_INTEN_REG_FIFO_INT_E (1<<0) ++#define S3C_G2D_INTEN_REG_ACF (1<<9) ++#define S3C_G2D_INTEN_REG_CCF (1<<10) ++ ++#define S3C_G2D_PEND_REG_INTP_ALL_FIN (1<<9) ++#define S3C_G2D_PEND_REG_INTP_CMD_FIN (1<<10) ++ ++/* Line/Point drawing */ ++#define S3C_G2D_CMD0_REG_D_LAST (0<<9) ++#define S3C_G2D_CMD0_REG_D_NO_LAST (1<<9) ++ ++#define S3C_G2D_CMD0_REG_M_Y (0<<8) ++#define S3C_G2D_CMD0_REG_M_X (1<<8) ++ ++#define S3C_G2D_CMD0_REG_L (1<<1) ++#define S3C_G2D_CMD0_REG_P (1<<0) ++ ++/* BitBLT */ ++#define S3C_G2D_CMD1_REG_S (1<<1) ++#define S3C_G2D_CMD1_REG_N (1<<0) ++ ++/* resource color mode */ ++#define S3C_G2D_COLOR_MODE_REG_C3_32BPP (1<<3) ++#define S3C_G2D_COLOR_MODE_REG_C3_24BPP (1<<3) ++#define S3C_G2D_COLOR_MODE_REG_C2_18BPP (1<<2) ++#define S3C_G2D_COLOR_MODE_REG_C1_16BPP (1<<1) ++#define S3C_G2D_COLOR_MODE_REG_C0_15BPP (1<<0) ++ ++#define S3C_G2D_COLOR_RGB_565 (0x0<<0) ++#define S3C_G2D_COLOR_RGBA_5551 (0x1<<0) ++#define S3C_G2D_COLOR_ARGB_1555 (0x2<<0) ++#define S3C_G2D_COLOR_RGBA_8888 (0x3<<0) ++#define S3C_G2D_COLOR_ARGB_8888 (0x4<<0) ++#define S3C_G2D_COLOR_XRGB_8888 (0x5<<0) ++#define S3C_G2D_COLOR_RGBX_8888 (0x6<<0) ++ ++/* rotation mode */ ++#define S3C_G2D_ROTATRE_REG_FY (1<<5) ++#define S3C_G2D_ROTATRE_REG_FX (1<<4) ++#define S3C_G2D_ROTATRE_REG_R3_270 (1<<3) ++#define S3C_G2D_ROTATRE_REG_R2_180 (1<<2) ++#define S3C_G2D_ROTATRE_REG_R1_90 (1<<1) ++#define S3C_G2D_ROTATRE_REG_R0_0 (1<<0) ++ ++/* Endian select */ ++#define S3C_G2D_ENDIAN_READSIZE_BIG_ENDIAN_BIG (1<<4) ++#define S3C_G2D_ENDIAN_READSIZE_BIG_ENDIAN_LITTLE (0<<4) ++ ++#define S3C_G2D_ENDIAN_READSIZE_SIZE_HW_DISABLE (0<<2) ++#define S3C_G2D_ENDIAN_READSIZE_SIZE_HW_ENABLE (1<<2) ++ ++/* read buffer size */ ++#define S3C_G2D_ENDIAN_READSIZE_READ_SIZE_1 (0<<0) ++#define S3C_G2D_ENDIAN_READSIZE_READ_SIZE_4 (1<<0) ++#define S3C_G2D_ENDIAN_READSIZE_READ_SIZE_8 (2<<0) ++#define S3C_G2D_ENDIAN_READSIZE_READ_SIZE_16 (3<<0) ++ ++/* Third Operans Select */ ++#define S3C_G2D_ROP_REG_OS_PATTERN (0<<13) ++#define S3C_G2D_ROP_REG_OS_FG_COLOR (1<<13) ++ ++/* Alpha Blending Mode */ ++#define S3C_G2D_ROP_REG_ABM_NO_BLENDING (0<<10) ++#define S3C_G2D_ROP_REG_ABM_SRC_BITMAP (1<<10) ++#define S3C_G2D_ROP_REG_ABM_REGISTER (2<<10) ++#define S3C_G2D_ROP_REG_ABM_FADING (4<<10) ++ ++/* Raster operation mode */ ++#define S3C_G2D_ROP_REG_T_OPAQUE_MODE (0<<9) ++#define S3C_G2D_ROP_REG_T_TRANSP_MODE (1<<9) ++ ++#define S3C_G2D_ROP_REG_B_BS_MODE_OFF (0<<8) ++#define S3C_G2D_ROP_REG_B_BS_MODE_ON (1<<8) ++ ++ ++/* stencil control */ ++#define S3C_G2D_STENCIL_CNTL_REG_STENCIL_ON_ON (1<<31) ++#define S3C_G2D_STENCIL_CNTL_REG_STENCIL_ON_OFF (0<<31) ++ ++#define S3C_G2D_STENCIL_CNTL_REG_STENCIL_INVERSE (1<<23) ++#define S3C_G2D_STENCIL_CNTL_REG_STENCIL_SWAP (1<<0) ++ ++/*********************************************************************************/ ++#endif /* __ASM_ARM_REGS_S3C_G2D_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-hsmmc.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-hsmmc.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-hsmmc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-hsmmc.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,210 @@ ++/* linux/include/asm-arm/arch-s3c2410/regs-hsmmc.h ++ * ++ * Copyright (c) 2004 Samsung Electronics ++ * http://www.samsung.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C HS-MMC Controller ++*/ ++ ++#ifndef __ASM_ARCH_REGS_HSMMC_H ++#define __ASM_ARCH_REGS_HSMMC_H __FILE__ ++ ++/* ++ * HS MMC Interface ++ */ ++#define S3C_HSMMC_REG(x) (x) ++ ++#define S3C_HSMMC_SYSAD (0x00) ++ ++#define S3C_HSMMC_BLKSIZE (0x04) ++#define S3C_HSMMC_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) ++ ++#define S3C_HSMMC_BLKCNT (0x06) ++#define S3C_HSMMC_ARGUMENT (0x08) ++ ++#define S3C_HSMMC_TRNMOD (0x0c) ++#define S3C_HSMMC_TRNS_DMA 0x01 ++#define S3C_HSMMC_TRNS_BLK_CNT_EN 0x02 ++#define S3C_HSMMC_TRNS_ACMD12 0x04 ++#define S3C_HSMMC_TRNS_READ 0x10 ++#define S3C_HSMMC_TRNS_MULTI 0x20 ++ ++#define S3C_HSMMC_CMDREG (0x0e) ++#define S3C_HSMMC_RSPREG0 (0x10) ++#define S3C_HSMMC_RSPREG1 (0x14) ++#define S3C_HSMMC_RSPREG2 (0x18) ++#define S3C_HSMMC_RSPREG3 (0x1c) ++#define S3C_HSMMC_CMD_RESP_MASK 0x03 ++#define S3C_HSMMC_CMD_CRC 0x08 ++#define S3C_HSMMC_CMD_INDEX 0x10 ++#define S3C_HSMMC_CMD_DATA 0x20 ++#define S3C_HSMMC_CMD_RESP_NONE 0x00 ++#define S3C_HSMMC_CMD_RESP_LONG 0x01 ++#define S3C_HSMMC_CMD_RESP_SHORT 0x02 ++#define S3C_HSMMC_CMD_RESP_SHORT_BUSY 0x03 ++#define S3C_HSMMC_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) ++ ++#define S3C_HSMMC_BDATA (0x20) ++ ++#define S3C_HSMMC_PRNSTS (0x24) ++#define S3C_HSMMC_CMD_INHIBIT 0x00000001 ++#define S3C_HSMMC_DATA_INHIBIT 0x00000002 ++#define S3C_HSMMC_DOING_WRITE 0x00000100 ++#define S3C_HSMMC_DOING_READ 0x00000200 ++#define S3C_HSMMC_SPACE_AVAILABLE 0x00000400 ++#define S3C_HSMMC_DATA_AVAILABLE 0x00000800 ++#define S3C_HSMMC_CARD_PRESENT 0x00010000 ++#define S3C_HSMMC_WRITE_PROTECT 0x00080000 ++ ++#define S3C_HSMMC_HOSTCTL (0x28) ++#define S3C_HSMMC_CTRL_LED 0x01 ++#define S3C_HSMMC_CTRL_4BITBUS 0x02 ++#define S3C_HSMMC_CTRL_HIGHSPEED 0x04 ++#define S3C_HSMMC_CTRL_1BIT 0x00 ++#define S3C_HSMMC_CTRL_4BIT 0x02 ++#define S3C_HSMMC_CTRL_8BIT 0x20 ++#define S3C_HSMMC_CTRL_SDMA 0x00 ++#define S3C_HSMMC_CTRL_ADMA2_32 0x10 ++ ++#define S3C_HSMMC_PWRCON (0x29) ++#define S3C_HSMMC_POWER_OFF 0x00 ++#define S3C_HSMMC_POWER_ON 0x01 ++#define S3C_HSMMC_POWER_180 0x0A ++#define S3C_HSMMC_POWER_300 0x0C ++#define S3C_HSMMC_POWER_330 0x0E ++#define S3C_HSMMC_POWER_ON_ALL 0xFF ++ ++#define S3C_HSMMC_BLKGAP (0x2a) ++#define S3C_HSMMC_WAKCON (0x2b) ++ ++#define S3C_HSMMC_CLKCON (0x2c) ++#define S3C_HSMMC_DIVIDER_SHIFT 8 ++#define S3C_HSMMC_CLOCK_EXT_STABLE 0x0008 ++#define S3C_HSMMC_CLOCK_CARD_EN 0x0004 ++#define S3C_HSMMC_CLOCK_INT_STABLE 0x0002 ++#define S3C_HSMMC_CLOCK_INT_EN 0x0001 ++ ++#define S3C_HSMMC_TIMEOUTCON (0x2e) ++#define S3C_HSMMC_TIMEOUT_MAX 0x0E ++ ++#define S3C_HSMMC_SWRST (0x2f) ++#define S3C_HSMMC_RESET_ALL 0x01 ++#define S3C_HSMMC_RESET_CMD 0x02 ++#define S3C_HSMMC_RESET_DATA 0x04 ++ ++#define S3C_HSMMC_NORINTSTS (0x30) ++#define S3C_HSMMC_NIS_ERR 0x00008000 ++#define S3C_HSMMC_NIS_CMDCMP 0x00000001 ++#define S3C_HSMMC_NIS_TRSCMP 0x00000002 ++#define S3C_HSMMC_NIS_DMA 0x00000008 ++ ++#define S3C_HSMMC_ERRINTSTS (0x32) ++#define S3C_HSMMC_EIS_CMDTIMEOUT 0x00000001 ++#define S3C_HSMMC_EIS_CMDERR 0x0000000E ++#define S3C_HSMMC_EIS_DATATIMEOUT 0x00000010 ++#define S3C_HSMMC_EIS_DATAERR 0x00000060 ++#define S3C_HSMMC_EIS_CMD12ERR 0x00000100 ++#define S3C_HSMMC_EIS_ADMAERR 0x00000200 ++ ++#define S3C_HSMMC_NORINTSTSEN (0x34) ++#define S3C_HSMMC_ERRINTSTSEN (0x36) ++ ++#define S3C_HSMMC_NORINTSIGEN (0x38) ++#define S3C_HSMMC_INT_MASK_ALL 0x0000 ++#define S3C_HSMMC_INT_RESPONSE 0x00000001 ++#define S3C_HSMMC_INT_DATA_END 0x00000002 ++#define S3C_HSMMC_INT_DMA_END 0x00000008 ++#define S3C_HSMMC_INT_SPACE_AVAIL 0x00000010 ++#define S3C_HSMMC_INT_DATA_AVAIL 0x00000020 ++#define S3C_HSMMC_INT_CARD_INSERT 0x00000040 ++#define S3C_HSMMC_INT_CARD_REMOVE 0x00000080 ++#define S3C_HSMMC_INT_CARD_CHANGE 0x000000c0 /* oring of above two */ ++#define S3C_HSMMC_INT_CARD_INT 0x00000100 ++#define S3C_HSMMC_INT_TIMEOUT 0x00010000 ++#define S3C_HSMMC_INT_CRC 0x00020000 ++#define S3C_HSMMC_INT_END_BIT 0x00040000 ++#define S3C_HSMMC_INT_INDEX 0x00080000 ++#define S3C_HSMMC_INT_DATA_TIMEOUT 0x00100000 ++#define S3C_HSMMC_INT_DATA_CRC 0x00200000 ++#define S3C_HSMMC_INT_DATA_END_BIT 0x00400000 ++#define S3C_HSMMC_INT_BUS_POWER 0x00800000 ++#define S3C_HSMMC_INT_ACMD12ERR 0x01000000 ++#define S3C_HSMMC_INT_ADMAERR 0x02000000 ++ ++#define S3C_HSMMC_INT_NORMAL_MASK 0x00007FFF ++#define S3C_HSMMC_INT_ERROR_MASK 0xFFFF8000 ++ ++#define S3C_HSMMC_INT_CMD_MASK (S3C_HSMMC_INT_RESPONSE | \ ++ S3C_HSMMC_INT_TIMEOUT | \ ++ S3C_HSMMC_INT_CRC | \ ++ S3C_HSMMC_INT_END_BIT | \ ++ S3C_HSMMC_INT_INDEX | \ ++ S3C_HSMMC_NIS_ERR \ ++ ) ++#define S3C_HSMMC_INT_DATA_MASK (S3C_HSMMC_INT_DATA_END | \ ++ S3C_HSMMC_INT_DMA_END | \ ++ S3C_HSMMC_INT_DATA_AVAIL | \ ++ S3C_HSMMC_INT_SPACE_AVAIL | \ ++ S3C_HSMMC_INT_DATA_TIMEOUT | \ ++ S3C_HSMMC_INT_DATA_CRC | \ ++ S3C_HSMMC_INT_DATA_END_BIT \ ++ ) ++ ++#define S3C_HSMMC_ERRINTSIGEN (0x3a) ++#define S3C_HSMMC_ACMD12ERRSTS (0x3c) ++ ++#define S3C_HSMMC_CAPAREG (0x40) ++#define S3C_HSMMC_TIMEOUT_CLK_MASK 0x0000003F ++#define S3C_HSMMC_TIMEOUT_CLK_SHIFT 0 ++#define S3C_HSMMC_TIMEOUT_CLK_UNIT 0x00000080 ++#define S3C_HSMMC_CLOCK_BASE_MASK 0x00003F00 ++#define S3C_HSMMC_CLOCK_BASE_SHIFT 8 ++#define S3C_HSMMC_MAX_BLOCK_MASK 0x00030000 ++#define S3C_HSMMC_MAX_BLOCK_SHIFT 16 ++#define S3C_HSMMC_CAN_DO_DMA 0x00400000 ++#define S3C_HSMMC_CAN_DO_ADMA2 0x00080000 ++#define S3C_HSMMC_CAN_VDD_330 0x01000000 ++#define S3C_HSMMC_CAN_VDD_300 0x02000000 ++#define S3C_HSMMC_CAN_VDD_180 0x04000000 ++ ++#define S3C_HSMMC_MAXCURR (0x48) ++ ++/* For ADMA2 */ ++#define S3C_HSMMC_FEAER (0x50) ++#define S3C_HSMMC_FEERR (0x52) ++ ++#define S3C_HSMMC_ADMAERR (0x54) ++#define S3C_HSMMC_ADMAERR_CONTINUE_REQUEST (1<<9) ++#define S3C_HSMMC_ADMAERR_INTRRUPT_STATUS (1<<8) ++#define S3C_HSMMC_ADMAERR_LENGTH_MISMATCH (1<<2) ++#define S3C_HSMMC_ADMAERR_STATE_ST_STOP (0<<0) ++#define S3C_HSMMC_ADMAERR_STATE_ST_FDS (1<<0) ++#define S3C_HSMMC_ADMAERR_STATE_ST_TFR (3<<0) ++ ++#define S3C_HSMMC_ADMASYSADDR (0x58) ++#define S3C_HSMMC_ADMA_ATTR_MSK 0x3F ++#define S3C_HSMMC_ADMA_ATTR_ACT_NOP (0<<4) ++#define S3C_HSMMC_ADMA_ATTR_ACT_RSV (1<<4) ++#define S3C_HSMMC_ADMA_ATTR_ACT_TRAN (2<<4) ++#define S3C_HSMMC_ADMA_ATTR_ACT_LINK (3<<4) ++#define S3C_HSMMC_ADMA_ATTR_INT (1<<2) ++#define S3C_HSMMC_ADMA_ATTR_END (1<<1) ++#define S3C_HSMMC_ADMA_ATTR_VALID (1<<0) ++ ++#define S3C_HSMMC_CONTROL2 (0x80) ++#define S3C_HSMMC_CONTROL3 (0x84) ++#define S3C_HSMMC_CONTROL4 (0x8C) ++#define S3C_HSMMC_DEBUG (0x88) ++ ++#define S3C_HSMMC_HCVER (0xfe) ++#define S3C_HSMMC_VENDOR_VER_MASK 0xFF00 ++#define S3C_HSMMC_VENDOR_VER_SHIFT 8 ++#define S3C_HSMMC_SPEC_VER_MASK 0x00FF ++#define S3C_HSMMC_SPEC_VER_SHIFT 0 ++ ++#endif /* __ASM_ARCH_REGS_HSMMC_H */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-iic.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-iic.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-iic.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-iic.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,56 @@ ++/* linux/arch/arm/plat-s3c/include/plat/regs-iic.h ++ * ++ * Copyright (c) 2004 Simtec Electronics ++ * http://www.simtec.co.uk/products/SWLINUX/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C2410 I2C Controller ++*/ ++ ++#ifndef __ASM_ARCH_REGS_IIC_H ++#define __ASM_ARCH_REGS_IIC_H __FILE__ ++ ++/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */ ++ ++#define S3C2410_IICREG(x) (x) ++ ++#define S3C2410_IICCON S3C2410_IICREG(0x00) ++#define S3C2410_IICSTAT S3C2410_IICREG(0x04) ++#define S3C2410_IICADD S3C2410_IICREG(0x08) ++#define S3C2410_IICDS S3C2410_IICREG(0x0C) ++#define S3C2440_IICLC S3C2410_IICREG(0x10) ++ ++#define S3C2410_IICCON_ACKEN (1<<7) ++#define S3C2410_IICCON_TXDIV_16 (0<<6) ++#define S3C2410_IICCON_TXDIV_512 (1<<6) ++#define S3C2410_IICCON_IRQEN (1<<5) ++#define S3C2410_IICCON_IRQPEND (1<<4) ++#define S3C2410_IICCON_SCALE(x) ((x)&15) ++#define S3C2410_IICCON_SCALEMASK (0xf) ++ ++#define S3C2410_IICSTAT_MASTER_RX (2<<6) ++#define S3C2410_IICSTAT_MASTER_TX (3<<6) ++#define S3C2410_IICSTAT_SLAVE_RX (0<<6) ++#define S3C2410_IICSTAT_SLAVE_TX (1<<6) ++#define S3C2410_IICSTAT_MODEMASK (3<<6) ++ ++#define S3C2410_IICSTAT_START (1<<5) ++#define S3C2410_IICSTAT_BUSBUSY (1<<5) ++#define S3C2410_IICSTAT_TXRXEN (1<<4) ++#define S3C2410_IICSTAT_ARBITR (1<<3) ++#define S3C2410_IICSTAT_ASSLAVE (1<<2) ++#define S3C2410_IICSTAT_ADDR0 (1<<1) ++#define S3C2410_IICSTAT_LASTBIT (1<<0) ++ ++#define S3C2410_IICLC_SDA_DELAY0 (0 << 0) ++#define S3C2410_IICLC_SDA_DELAY5 (1 << 0) ++#define S3C2410_IICLC_SDA_DELAY10 (2 << 0) ++#define S3C2410_IICLC_SDA_DELAY15 (3 << 0) ++#define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0) ++ ++#define S3C2410_IICLC_FILTER_ON (1<<2) ++ ++#endif /* __ASM_ARCH_REGS_IIC_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-iis.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-iis.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-iis.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-iis.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,126 @@ ++/* linux/arch/arm/plat-s3c/include/plat/regs-iis.h ++ * ++ * Copyright (c) 2003 Simtec Electronics ++ * http://www.simtec.co.uk/products/SWLINUX/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C64XX IIS register definition ++*/ ++ ++#ifndef __ASM_ARCH_REGS_IIS_H ++#define __ASM_ARCH_REGS_IIS_H ++ ++#define S3C64XX_IIS0REG(x) ((x) + S3C64XX_PA_IIS_V40) ++ ++//#define S3C_IIS0CON S3C64XX_IIS0REG(0x00) ++//#define S3C_IIS0MOD S3C64XX_IIS0REG(0x04) ++//#define S3C_IIS0FIC S3C64XX_IIS0REG(0x08) ++//#define S3C_IIS0PSR S3C64XX_IIS0REG(0x0C) ++//#define S3C_IIS0TXD S3C64XX_IIS0REG(0x10) ++//#define S3C_IIS0RXD S3C64XX_IIS0REG(0x14) ++ ++#define S3C64XX_IIS0CON (0x00) ++#define S3C64XX_IIS0MOD (0x04) ++#define S3C64XX_IIS0FIC (0x08) ++#define S3C64XX_IIS0PSR (0x0C) ++#define S3C64XX_IIS0TXD (0x10) ++#define S3C64XX_IIS0RXD (0x14) ++ ++#define S3C64XX_IISCON_LRINDEX (1<<8) ++#define S3C64XX_IISCON_TXFIFORDY (1<<7) ++#define S3C64XX_IISCON_RXFIFORDY (1<<6) ++#define S3C64XX_IISCON_TXDMAEN (1<<5) ++#define S3C64XX_IISCON_RXDMAEN (1<<4) ++#define S3C64XX_IISCON_TXIDLE (1<<3) ++#define S3C64XX_IISCON_RXIDLE (1<<2) ++#define S3C64XX_IISCON_PSCEN (1<<1) ++#define S3C64XX_IISCON_IISEN (1<<0) ++ ++//#define S3C64XX_IISMOD_MPLL (1<<9) ++#define S3C64XX_IISMOD_MPLL (0x01<<10) ++#define S3C64XX_IISMOD_SLAVE (1<<8) ++#define S3C64XX_IISMOD_NOXFER (0<<6) ++#define S3C64XX_IISMOD_RXMODE (1<<6) ++#define S3C64XX_IISMOD_TXMODE (2<<6) ++#define S3C64XX_IISMOD_TXRXMODE (3<<6) ++#define S3C64XX_IISMOD_LR_LLOW (0<<5) ++#define S3C64XX_IISMOD_LR_RLOW (1<<5) ++#define S3C64XX_IISMOD_IIS (0<<4) ++#define S3C64XX_IISMOD_MSB (1<<4) ++#define S3C64XX_IISMOD_8BIT (0<<3) ++#define S3C64XX_IISMOD_16BIT (1<<3) ++#define S3C64XX_IISMOD_BITMASK (1<<3) ++#define S3C64XX_IISMOD_256FS (0<<2) ++#define S3C64XX_IISMOD_384FS (1<<2) ++#define S3C64XX_IISMOD_16FS (0<<0) ++#define S3C64XX_IISMOD_32FS (1<<0) ++#define S3C64XX_IISMOD_48FS (2<<0) ++#define S3C64XX_IISMOD_FS_MASK (3<<0) ++ ++#define S3C64XX_IIS0MOD_DCE_MASK (0x3<<16) ++#define S3C64XX_IIS0MOD_DCE_SD2 (0x1<<17) ++#define S3C64XX_IIS0MOD_DCE_SD1 (0x1<<16) ++#define S3C64XX_IIS0MOD_BLC_MASK (0x3<<13) ++#define S3C64XX_IIS0MOD_BLC_16BIT (0x0<<13) ++#define S3C64XX_IIS0MOD_BLC_08BIT (0x1<<13) ++#define S3C64XX_IIS0MOD_BLC_24BIT (0x2<<13) ++#define S3C64XX_IIS0MOD_CLK_MASK (0x7<<10) ++#define S3C64XX_IIS0MOD_INTERNAL_CLK (0x0<<12) ++#define S3C64XX_IIS0MOD_EXTERNAL_CLK (0x1<<12) ++#define S3C64XX_IIS0MOD_IMS_INTERNAL_MASTER (0x0<<10) ++#define S3C64XX_IIS0MOD_IMS_EXTERNAL_MASTER (0x1<<10) ++#define S3C64XX_IIS0MOD_IMS_SLAVE (0x2<<10) ++#define S3C64XX_IIS0MOD_MODE_MASK (0x3<<8) ++#define S3C64XX_IIS0MOD_TXMODE (0x0<<8) ++#define S3C64XX_IIS0MOD_RXMODE (0x1<<8) ++#define S3C64XX_IIS0MOD_TXRXMODE (0x2<<8) ++#define S3C64XX_IIS0MOD_FM_MASK (0x3<<5) ++#define S3C64XX_IIS0MOD_IIS (0x0<<5) ++#define S3C64XX_IIS0MOD_MSB (0x1<<5) ++#define S3C64XX_IIS0MOD_LSB (0x2<<5) ++#define S3C64XX_IIS0MOD_FS_MASK (0x3<<3) ++#define S3C64XX_IIS0MOD_768FS (0x3<<3) ++#define S3C64XX_IIS0MOD_384FS (0x2<<3) ++#define S3C64XX_IIS0MOD_512FS (0x1<<3) ++#define S3C64XX_IIS0MOD_256FS (0x0<<3) ++#define S3C64XX_IIS0MOD_BFS_MASK (0x3<<1) ++#define S3C64XX_IIS0MOD_48FS (0x1<<1) ++#define S3C64XX_IIS0MOD_32FS (0x0<<1) ++ ++#define S3C64XX_IISPSR (0x08) ++#define S3C64XX_IISPSR_INTMASK (31<<5) ++#define S3C64XX_IISPSR_INTSHIFT (5) ++#define S3C64XX_IISPSR_EXTMASK (31<<0) ++#define S3C64XX_IISPSR_EXTSHFIT (0) ++ ++#define S3C64XX_IISFCON (0x0c) ++ ++#define S3C64XX_IISFCON_TXDMA (1<<15) ++#define S3C64XX_IISFCON_RXDMA (1<<14) ++#define S3C64XX_IISFCON_TXENABLE (1<<13) ++#define S3C64XX_IISFCON_RXENABLE (1<<12) ++#define S3C64XX_IISFCON_TXMASK (0x3f << 6) ++#define S3C64XX_IISFCON_TXSHIFT (6) ++#define S3C64XX_IISFCON_RXMASK (0x3f) ++#define S3C64XX_IISFCON_RXSHIFT (0) ++ ++#define S3C64XX_IISFIFO (0x10) ++#define S3C64XX_IISFIFORX (0x14) ++ ++#define S3C64XX_IIS0CON_I2SACTIVE (0x1<<0) ++#define S3C64XX_IIS0CON_RXDMACTIVE (0x1<<1) ++#define S3C64XX_IIS0CON_I2SACTIVE (0x1<<0) ++#define S3C64XX_IIS0CON_TXDMACTIVE (0x1<<2) ++ ++#define S3C64XX_IIS_TX_FLUSH (0x1<<15) ++#define S3C64XX_IIS_RX_FLUSH (0x1<<7) ++ ++#define S3C64XX_IISCON_FTXURINTEN (0x1<<16) ++ ++#define S3C64XX_IIS0MOD_24BIT (0x2<<13) ++#define S3C64XX_IIS0MOD_8BIT (0x1<<13) ++#define S3C64XX_IIS0MOD_16BIT (0x0<<13) ++#endif /* __ASM_ARCH_REGS_IIS_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-irqtype.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-irqtype.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-irqtype.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-irqtype.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,21 @@ ++/* linux/arch/arm/plat-s3c/include/plat/regs-irqtype.h ++ * ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C - IRQ detection types. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++/* values for S3C2410_EXTINT0/1/2 and other cpus in the series, including ++ * the S3C64XX ++*/ ++#define S3C2410_EXTINT_LOWLEV (0x00) ++#define S3C2410_EXTINT_HILEV (0x01) ++#define S3C2410_EXTINT_FALLEDGE (0x02) ++#define S3C2410_EXTINT_RISEEDGE (0x04) ++#define S3C2410_EXTINT_BOTHEDGE (0x06) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-keypad.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-keypad.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-keypad.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-keypad.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,40 @@ ++/* linux/arch/arm/plat-s3c64xx/include/plat/regs-keypad.h ++ * ++ * ++ * S3C6410 Key Interface register definitions ++ * ++ * Kim Kyoungil, Copyright (c) 2006-2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++ ++#ifndef __ASM_ARCH_REGS_KEYPAD_H ++#define __ASM_ARCH_REGS_KEYPAD_H ++ ++/* ++ * Keypad Interface ++ */ ++#define S3C_KEYPADREG(x) (x) ++ ++#define S3C_KEYIFCON S3C_KEYPADREG(0x00) ++#define S3C_KEYIFSTSCLR S3C_KEYPADREG(0x04) ++#define S3C_KEYIFCOL S3C_KEYPADREG(0x08) ++#define S3C_KEYIFROW S3C_KEYPADREG(0x0C) ++#define S3C_KEYIFFC S3C_KEYPADREG(0x10) ++ ++#define KEYCOL_DMASK (0xff) ++#define KEYROW_DMASK (0xff) ++#define INT_F_EN (1<<0) /*falling edge(key-pressed) interuppt enable*/ ++#define INT_R_EN (1<<1) /*rising edge(key-released) interuppt enable*/ ++#define DF_EN (1<<2) /*debouncing filter enable*/ ++#define FC_EN (1<<3) /*filter clock enable*/ ++#define KEYIFCON_INIT (KEYIFCON_CLEAR |INT_F_EN|INT_R_EN|DF_EN|FC_EN) ++#define KEYIFSTSCLR_CLEAR (0xffff) ++ ++#endif /* __ASM_ARCH_REGS_KEYPAD_H */ ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-lcd.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-lcd.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-lcd.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-lcd.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,518 @@ ++/* linux/arch/arm/plat-s3c/include/plat/regs-lcd.h ++ * ++ * Copyright (c) 2003 Simtec Electronics ++ * http://www.simtec.co.uk/products/SWLINUX/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++ ++#ifndef ___ASM_ARCH_REGS_LCD_H ++#define ___ASM_ARCH_REGS_LCD_H ++ ++#include ++ ++/***************************************************************************/ ++/* LCD Registers for S3C2443/2450/S3C6400/6410 */ ++#define S3C_LCDREG(x) ((x) + S3C_VA_LCD) ++ ++/* LCD control registers */ ++#define S3C_VIDCON0 S3C_LCDREG(0x00) /* Video control 0 register */ ++#define S3C_VIDCON1 S3C_LCDREG(0x04) /* Video control 1 register */ ++ ++#if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416) ++#define S3C_VIDTCON0 S3C_LCDREG(0x08) /* LCD CONTROL 1 */ ++#define S3C_VIDTCON1 S3C_LCDREG(0x0C) /* LCD CONTROL 1 */ ++#define S3C_VIDTCON2 S3C_LCDREG(0x10) /* LCD CONTROL 1 */ ++#define S3C_WINCON0 S3C_LCDREG(0x14) /* LCD CONTROL 1 */ ++#define S3C_WINCON1 S3C_LCDREG(0x18) /* LCD CONTROL 1 */ ++#define S3C_VIDOSD0A S3C_LCDREG(0x28) /* LCD CONTROL 1 */ ++#define S3C_VIDOSD0B S3C_LCDREG(0x2C) /* LCD CONTROL 1 */ ++#define S3C_VIDOSD0C S3C_LCDREG(0x30) /* LCD CONTROL 1 */ ++#define S3C_VIDOSD1A S3C_LCDREG(0x34) /* LCD CONTROL 1 */ ++#define S3C_VIDOSD1B S3C_LCDREG(0x38) /* LCD CONTROL 1 */ ++#define S3C_VIDOSD1C S3C_LCDREG(0x3C) /* LCD CONTROL 1 */ ++#define S3C_VIDW00ADD0B0 S3C_LCDREG(0x64) /* LCD CONTROL 1 */ ++#define S3C_VIDW00ADD0B1 S3C_LCDREG(0x68) /* LCD CONTROL 1 */ ++#define S3C_VIDW01ADD0 S3C_LCDREG(0x6C) /* LCD CONTROL 1 */ ++#define S3C_VIDW00ADD1B0 S3C_LCDREG(0x7C) /* LCD CONTROL 1 */ ++#define S3C_VIDW00ADD1B1 S3C_LCDREG(0x80) /* LCD CONTROL 1 */ ++#define S3C_VIDW01ADD1 S3C_LCDREG(0x84) /* LCD CONTROL 1 */ ++#define S3C_VIDW00ADD2B0 S3C_LCDREG(0x94) /* LCD CONTROL 1 */ ++#define S3C_VIDW00ADD2B1 S3C_LCDREG(0x98) /* LCD CONTROL 1 */ ++#define S3C_VIDW01ADD2 S3C_LCDREG(0x9C) /* LCD CONTROL 1 */ ++#define S3C_VIDINTCON S3C_LCDREG(0xAC) /* LCD CONTROL 1 */ ++#define S3C_W1KEYCON0 S3C_LCDREG(0xB0) /* LCD CONTROL 1 */ ++#define S3C_W1KEYCON1 S3C_LCDREG(0xB4) /* LCD CONTROL 1 */ ++#define S3C_WIN0MAP S3C_LCDREG(0xD0) /* LCD CONTROL 1 */ ++#define S3C_WIN1MAP S3C_LCDREG(0xD4) /* LCD CONTROL 1 */ ++#define S3C_WPALCON S3C_LCDREG(0xE4) /* LCD CONTROL 1 */ ++#define S3C_SYSIFCON0 S3C_LCDREG(0x130) /* LCD CONTROL 1 */ ++#define S3C_SYSIFCON1 S3C_LCDREG(0x134) /* LCD CONTROL 1 */ ++#define S3C_DITHMODE S3C_LCDREG(0x138) /* LCD CONTROL 1 */ ++#define S3C_SIFCCON0 S3C_LCDREG(0x13C) /* LCD CONTROL 1 */ ++#define S3C_SIFCCON1 S3C_LCDREG(0x140) /* LCD CONTROL 1 */ ++#define S3C_SIFCCON2 S3C_LCDREG(0x144) /* LCD CONTROL 1 */ ++#define S3C_CPUTRIGCON2 S3C_LCDREG(0x160) /* LCD CONTROL 1 */ ++ ++#elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5PC100) ++#define S3C_VIDCON2 S3C_LCDREG(0x08) /* Video control 2 register */ ++#define S3C_VIDTCON0 S3C_LCDREG(0x10) /* Video time control 0 register */ ++#define S3C_VIDTCON1 S3C_LCDREG(0x14) /* Video time control 1 register */ ++#define S3C_VIDTCON2 S3C_LCDREG(0x18) /* Video time control 2 register */ ++#define S3C_VIDTCON3 S3C_LCDREG(0x1C) /* Video time control 3 register */ ++ ++#define S3C_WINCON0 S3C_LCDREG(0x20) /* Window control 0 register */ ++#define S3C_WINCON1 S3C_LCDREG(0x24) /* Window control 1 register */ ++#define S3C_WINCON2 S3C_LCDREG(0x28) /* Window control 2 register */ ++#define S3C_WINCON3 S3C_LCDREG(0x2C) /* Window control 3 register */ ++#define S3C_WINCON4 S3C_LCDREG(0x30) /* Window control 4 register*/ ++ ++ ++#define S3C_VIDOSD0A S3C_LCDREG(0x40) /* Video Window 0 position control register */ ++#define S3C_VIDOSD0B S3C_LCDREG(0x44) /* Video Window 0 position control register1 */ ++#define S3C_VIDOSD0C S3C_LCDREG(0x48) /* Video Window 0 position control register */ ++ ++#define S3C_VIDOSD1A S3C_LCDREG(0x50) /* Video Window 1 position control register */ ++#define S3C_VIDOSD1B S3C_LCDREG(0x54) /* Video Window 1 position control register */ ++#define S3C_VIDOSD1C S3C_LCDREG(0x58) /* Video Window 1 position control register */ ++#define S3C_VIDOSD1D S3C_LCDREG(0x5C) /* Video Window 1 position control register */ ++ ++#define S3C_VIDOSD2A S3C_LCDREG(0x60) /* Video Window 2 position control register */ ++#define S3C_VIDOSD2B S3C_LCDREG(0x64) /* Video Window 2 position control register */ ++#define S3C_VIDOSD2C S3C_LCDREG(0x68) /* Video Window 2 position control register */ ++#define S3C_VIDOSD2D S3C_LCDREG(0x6C) /* Video Window 2 position control register */ ++ ++#define S3C_VIDOSD3A S3C_LCDREG(0x70) /* Video Window 3 position control register */ ++#define S3C_VIDOSD3B S3C_LCDREG(0x74) /* Video Window 3 position control register */ ++#define S3C_VIDOSD3C S3C_LCDREG(0x78) /* Video Window 3 position control register */ ++ ++#define S3C_VIDOSD4A S3C_LCDREG(0x80) /* Video Window 4 position control register */ ++#define S3C_VIDOSD4B S3C_LCDREG(0x84) /* Video Window 4 position control register */ ++#define S3C_VIDOSD4C S3C_LCDREG(0x88) /* Video Window 4 position control register */ ++ ++#define S3C_VIDW00ADD2B0 S3C_LCDREG(0x94) /* LCD CONTROL 1 */ ++#define S3C_VIDW00ADD2B1 S3C_LCDREG(0x98) /* LCD CONTROL 1 */ ++ ++#define S3C_VIDW00ADD0B0 S3C_LCDREG(0x0A0) /* Window 0 buffer start address register, buffer 0 */ ++#define S3C_VIDW00ADD0B1 S3C_LCDREG(0x0A4) /* Window 0 buffer start address register, buffer 1 */ ++#define S3C_VIDW01ADD0B0 S3C_LCDREG(0x0A8) /* Window 1 buffer start address register, buffer 0 */ ++#define S3C_VIDW01ADD0B1 S3C_LCDREG(0x0AC) /* Window 1 buffer start address register, buffer 1 */ ++#define S3C_VIDW02ADD0 S3C_LCDREG(0x0B0) /* Window 2 buffer start address register */ ++#define S3C_VIDW03ADD0 S3C_LCDREG(0x0B8) /* Window 3 buffer start address register */ ++#define S3C_VIDW04ADD0 S3C_LCDREG(0x0C0) /* Window 4 buffer start address register */ ++#define S3C_VIDW00ADD1B0 S3C_LCDREG(0x0D0) /* Window 0 buffer end address register, buffer 0 */ ++#define S3C_VIDW00ADD1B1 S3C_LCDREG(0x0D4) /* Window 0 buffer end address register, buffer 1 */ ++#define S3C_VIDW01ADD1B0 S3C_LCDREG(0x0D8) /* Window 1 buffer end address register, buffer 0 */ ++#define S3C_VIDW01ADD1B1 S3C_LCDREG(0x0DC) /* Window 1 buffer end address register, buffer 1 */ ++#define S3C_VIDW02ADD1 S3C_LCDREG(0x0E0) /* Window 2 buffer end address register */ ++#define S3C_VIDW03ADD1 S3C_LCDREG(0x0E8) /* Window 3 buffer end address register */ ++#define S3C_VIDW04ADD1 S3C_LCDREG(0x0F0) /* Window 4 buffer end address register */ ++#define S3C_VIDW00ADD2 S3C_LCDREG(0x100) /* Window 0 buffer size register */ ++#define S3C_VIDW01ADD2 S3C_LCDREG(0x104) /* Window 1 buffer size register */ ++ ++#define S3C_VIDW02ADD2 S3C_LCDREG(0x108) /* Window 2 buffer size register */ ++#define S3C_VIDW03ADD2 S3C_LCDREG(0x10C) /* Window 3 buffer size register */ ++#define S3C_VIDW04ADD2 S3C_LCDREG(0x110) /* Window 4 buffer size register */ ++ ++#define S3C_VIDINTCON0 S3C_LCDREG(0x130) /* Indicate the Video interrupt control register */ ++#define S3C_VIDINTCON1 S3C_LCDREG(0x134) /* Video Interrupt Pending register */ ++#define S3C_W1KEYCON0 S3C_LCDREG(0x140) /* Color key control register */ ++#define S3C_W1KEYCON1 S3C_LCDREG(0x144) /* Color key value ( transparent value) register */ ++#define S3C_W2KEYCON0 S3C_LCDREG(0x148) /* Color key control register */ ++#define S3C_W2KEYCON1 S3C_LCDREG(0x14C) /* Color key value (transparent value) register */ ++ ++#define S3C_W3KEYCON0 S3C_LCDREG(0x150) /* Color key control register */ ++#define S3C_W3KEYCON1 S3C_LCDREG(0x154) /* Color key value (transparent value) register */ ++#define S3C_W4KEYCON0 S3C_LCDREG(0x158) /* Color key control register */ ++#define S3C_W4KEYCON1 S3C_LCDREG(0x15C) /* Color key value (transparent value) register */ ++#define S3C_DITHMODE S3C_LCDREG(0x170) /* Dithering mode register. */ ++ ++#define S3C_WIN0MAP S3C_LCDREG(0x180) /* Window color control */ ++#define S3C_WIN1MAP S3C_LCDREG(0x184) /* Window color control */ ++#define S3C_WIN2MAP S3C_LCDREG(0x188) /* Window color control */ ++#define S3C_WIN3MAP S3C_LCDREG(0x18C) /* Window color control */ ++#define S3C_WIN4MAP S3C_LCDREG(0x190) /* Window color control */ ++#define S3C_WPALCON S3C_LCDREG(0x1A0) /* Window Palette control register */ ++ ++#define S3C_TRIGCON S3C_LCDREG(0x1A4) /* I80 / RGB Trigger Control Regiter */ ++#define S3C_I80IFCONA0 S3C_LCDREG(0x1B0) /* I80 Interface control 0 for Main LDI */ ++#define S3C_I80IFCONA1 S3C_LCDREG(0x1B4) /* I80 Interface control 0 for Sub LDI */ ++#define S3C_I80IFCONB0 S3C_LCDREG(0x1B8) /* I80 Inteface control 1 for Main LDI */ ++#define S3C_I80IFCONB1 S3C_LCDREG(0x1BC) /* I80 Inteface control 1 for Sub LDI */ ++#define S3C_LDI_CMDCON0 S3C_LCDREG(0x1D0) /* I80 Interface LDI Command Control 0 */ ++#define S3C_LDI_CMDCON1 S3C_LCDREG(0x1D4) /* I80 Interface LDI Command Control 1 */ ++#define S3C_SIFCCON0 S3C_LCDREG(0x1E0) /* LCD i80 System Interface Command Control 0 */ ++#define S3C_SIFCCON1 S3C_LCDREG(0x1E4) /* LCD i80 System Interface Command Control 1 */ ++#define S3C_SIFCCON2 S3C_LCDREG(0x1E8) /* LCD i80 System Interface Command Control 2 */ ++ ++#define S3C_LDI_CMD0 S3C_LCDREG(0x280) /* I80 Inteface LDI Command 0 */ ++#define S3C_LDI_CMD1 S3C_LCDREG(0x284) /* I80 Inteface LDI Command 1 */ ++#define S3C_LDI_CMD2 S3C_LCDREG(0x288) /* I80 Inteface LDI Command 2 */ ++#define S3C_LDI_CMD3 S3C_LCDREG(0x28C) /* I80 Inteface LDI Command 3 */ ++#define S3C_LDI_CMD4 S3C_LCDREG(0x290) /* I80 Inteface LDI Command 4 */ ++#define S3C_LDI_CMD5 S3C_LCDREG(0x294) /* I80 Inteface LDI Command 5 */ ++#define S3C_LDI_CMD6 S3C_LCDREG(0x298) /* I80 Inteface LDI Command 6 */ ++#define S3C_LDI_CMD7 S3C_LCDREG(0x29C) /* I80 Inteface LDI Command 7 */ ++#define S3C_LDI_CMD8 S3C_LCDREG(0x2A0) /* I80 Inteface LDI Command 8 */ ++#define S3C_LDI_CMD9 S3C_LCDREG(0x2A4) /* I80 Inteface LDI Command 9 */ ++#define S3C_LDI_CMD10 S3C_LCDREG(0x2A8) /* I80 Inteface LDI Command 10 */ ++#define S3C_LDI_CMD11 S3C_LCDREG(0x2AC) /* I80 Inteface LDI Command 11 */ ++ ++#define S3C_W2PDATA01 S3C_LCDREG(0x300) /* Window 2 Palette Data of the Index 0,1 */ ++#define S3C_W2PDATA23 S3C_LCDREG(0x304) /* Window 2 Palette Data of the Index 2,3 */ ++#define S3C_W2PDATA45 S3C_LCDREG(0x308) /* Window 2 Palette Data of the Index 4,5 */ ++#define S3C_W2PDATA67 S3C_LCDREG(0x30C) /* Window 2 Palette Data of the Index 6,7 */ ++#define S3C_W2PDATA89 S3C_LCDREG(0x310) /* Window 2 Palette Data of the Index 8,9 */ ++#define S3C_W2PDATAAB S3C_LCDREG(0x314) /* Window 2 Palette Data of the Index A, B */ ++#define S3C_W2PDATACD S3C_LCDREG(0x318) /* Window 2 Palette Data of the Index C, D */ ++#define S3C_W2PDATAEF S3C_LCDREG(0x31C) /* Window 2 Palette Data of the Index E, F */ ++#define S3C_W3PDATA01 S3C_LCDREG(0x320) /* Window 3 Palette Data of the Index 0,1 */ ++#define S3C_W3PDATA23 S3C_LCDREG(0x324) /* Window 3 Palette Data of the Index 2,3 */ ++#define S3C_W3PDATA45 S3C_LCDREG(0x328) /* Window 3 Palette Data of the Index 4,5 */ ++#define S3C_W3PDATA67 S3C_LCDREG(0x32C) /* Window 3 Palette Data of the Index 6,7 */ ++#define S3C_W3PDATA89 S3C_LCDREG(0x330) /* Window 3 Palette Data of the Index 8,9 */ ++#define S3C_W3PDATAAB S3C_LCDREG(0x334) /* Window 3 Palette Data of the Index A, B */ ++#define S3C_W3PDATACD S3C_LCDREG(0x338) /* Window 3 Palette Data of the Index C, D */ ++#define S3C_W3PDATAEF S3C_LCDREG(0x33C) /* Window 3 Palette Data of the Index E, F */ ++#define S3C_W4PDATA01 S3C_LCDREG(0x340) /* Window 3 Palette Data of the Index 0,1 */ ++#define S3C_W4PDATA23 S3C_LCDREG(0x344) /* Window 3 Palette Data of the Index 2,3 */ ++#endif ++ ++#define S3C_TFTPAL2(x) S3C_LCDREG((0x300 + (x)*4)) ++#define S3C_TFTPAL3(x) S3C_LCDREG((0x320 + (x)*4)) ++#define S3C_TFTPAL4(x) S3C_LCDREG((0x340 + (x)*4)) ++#define S3C_TFTPAL0(x) S3C_LCDREG((0x400 + (x)*4)) ++#define S3C_TFTPAL1(x) S3C_LCDREG((0x800 + (x)*4)) ++ ++/*--------------------------------------------------------------*/ ++/* Video Main Control 0 register - VIDCON0 */ ++#define S3C_VIDCON0_INTERLACE_F_PROGRESSIVE (0<<29) ++#define S3C_VIDCON0_INTERLACE_F_INTERLACE (1<<29) ++#define S3C_VIDCON0_INTERLACE_F_MASK (1<<29) ++#define S3C_VIDCON0_VIDOUT(x) (((x)&0x7)<<26) ++#define S3C_VIDCON0_VIDOUT_RGB_IF (0<<26) ++#define S3C_VIDCON0_VIDOUT_TV (1<<26) ++#define S3C_VIDCON0_VIDOUT_I80IF0 (2<<26) ++#define S3C_VIDCON0_VIDOUT_I80IF1 (3<<26) ++#define S3C_VIDCON0_VIDOUT_TVNRGBIF (4<<26) ++#define S3C_VIDCON0_VIDOUT_TVNI80IF0 (6<<26) ++#define S3C_VIDCON0_VIDOUT_TVNI80IF1 (7<<26) ++#define S3C_VIDCON0_VIDOUT_MASK (7<<26) ++#define S3C_VIDCON0_L1_DATA16(x) (((x)&0x7)<<23) ++#define S3C_VIDCON0_L1_DATA16_SUB_16_MODE (0<<23) ++#define S3C_VIDCON0_L1_DATA16_SUB_16PLUS2_MODE (1<<23) ++#define S3C_VIDCON0_L1_DATA16_SUB_9PLUS9_MODE (2<<23) ++#define S3C_VIDCON0_L1_DATA16_SUB_16PLUS8_MODE (3<<23) ++#define S3C_VIDCON0_L1_DATA16_SUB_18_MODE (4<<23) ++#define S3C_VIDCON0_L0_DATA16(x) (((x)&0x7)<<20) ++#define S3C_VIDCON0_L0_DATA16_MAIN_16_MODE (0<<20) ++#define S3C_VIDCON0_L0_DATA16_MAIN_16PLUS2_MODE (1<<20) ++#define S3C_VIDCON0_L0_DATA16_MAIN_9PLUS9_MODE (2<<20) ++#define S3C_VIDCON0_L0_DATA16_MAIN_16PLUS8_MODE (3<<20) ++#define S3C_VIDCON0_L0_DATA16_MAIN_18_MODE (4<<20) ++#define S3C_VIDCON0_PNRMODE(x) (((x)&0x3)<<17) ++#define S3C_VIDCON0_PNRMODE_RGB_P (0<<17) ++#define S3C_VIDCON0_PNRMODE_BGR_P (1<<17) ++#define S3C_VIDCON0_PNRMODE_RGB_S (2<<17) ++#define S3C_VIDCON0_PNRMODE_BGR_S (3<<17) ++#define S3C_VIDCON0_PNRMODE_MASK (3<<17) ++#define S3C_VIDCON0_CLKVALUP_ALWAYS (0<<16) ++#define S3C_VIDCON0_CLKVALUP_ST_FRM (1<<16) ++#define S3C_VIDCON0_CLKVAL_F(x) (((x)&0xFF)<<6) ++#define S3C_VIDCON0_VCLKEN_ENABLE (1<<5) ++#define S3C_VIDCON0_CLKDIR_DIVIDED (1<<4) ++#define S3C_VIDCON0_CLKDIR_DIRECTED (0<<4) ++#define S3C_VIDCON0_CLKSEL(x) (((x)&0x3)<<2) ++#define S3C_VIDCON0_CLKSEL_F_HCLK (0<<2) ++#define S3C_VIDCON0_ENVID_ENABLE (1 << 1) /* 0:Disable 1:Enable LCD video output and logic immediatly */ ++#define S3C_VIDCON0_ENVID_DISABLE (0 << 1) /* 0:Disable 1:Enable LCD video output and logic immediatly */ ++#define S3C_VIDCON0_ENVID_F_ENABLE (1 << 0) /* 0:Dis 1:Ena wait until Current frame end. */ ++#define S3C_VIDCON0_ENVID_F_DISABLE (0 << 0) /* 0:Dis 1:Ena wait until Current frame end. */ ++ ++/* Video Main Control 1 register - VIDCON1 */ ++#define S3C_VIDCON1_IVCLK_FALL_EDGE (0<<7) ++#define S3C_VIDCON1_IVCLK_RISE_EDGE (1<<7) ++#define S3C_VIDCON1_IHSYNC_NORMAL (0<<6) ++#define S3C_VIDCON1_IHSYNC_INVERT (1<<6) ++#define S3C_VIDCON1_IVSYNC_NORMAL (0<<5) ++#define S3C_VIDCON1_IVSYNC_INVERT (1<<5) ++#define S3C_VIDCON1_IVDEN_NORMAL (0<<4) ++#define S3C_VIDCON1_IVDEN_INVERT (1<<4) ++ ++/* Video Main Control 2 register - VIDCON2 */ ++#define S3C_VIDCON2_EN601_DISABLE (0<<23) ++#define S3C_VIDCON2_EN601_ENABLE (1<<23) ++#define S3C_VIDCON2_EN601_MASK (1<<23) ++#define S3C_VIDCON2_TVFORMATSEL0_HARDWARE (0<<14) ++#define S3C_VIDCON2_TVFORMATSEL0_SOFTWARE (1<<14) ++#define S3C_VIDCON2_TVFORMATSEL0_MASK (1<<14) ++#define S3C_VIDCON2_TVFORMATSEL1_RGB (0<<12) ++#define S3C_VIDCON2_TVFORMATSEL1_YUV422 (1<<12) ++#define S3C_VIDCON2_TVFORMATSEL1_YUV444 (2<<12) ++#define S3C_VIDCON2_TVFORMATSEL1_MASK (0x3<<12) ++#define S3C_VIDCON2_ORGYUV_YCBCR (0<<8) ++#define S3C_VIDCON2_ORGYUV_CBCRY (1<<8) ++#define S3C_VIDCON2_ORGYUV_MASK (1<<8) ++#define S3C_VIDCON2_YUVORD_CBCR (0<<7) ++#define S3C_VIDCON2_YUVORD_CRCB (1<<7) ++#define S3C_VIDCON2_YUVORD_MASK (1<<7) ++ ++/* VIDEO Time Control 0 register - VIDTCON0 */ ++#define S3C_VIDTCON0_VBPDE(x) (((x)&0xFF)<<24) ++#define S3C_VIDTCON0_VBPD(x) (((x)&0xFF)<<16) ++#define S3C_VIDTCON0_VFPD(x) (((x)&0xFF)<<8) ++#define S3C_VIDTCON0_VSPW(x) (((x)&0xFF)<<0) ++ ++/* VIDEO Time Control 1 register - VIDTCON1 */ ++#define S3C_VIDTCON1_VFPDE(x) (((x)&0xFF)<<24) ++#define S3C_VIDTCON1_HBPD(x) (((x)&0xFF)<<16) ++#define S3C_VIDTCON1_HFPD(x) (((x)&0xFF)<<8) ++#define S3C_VIDTCON1_HSPW(x) (((x)&0xFF)<<0) ++ ++/* VIDEO Time Control 2 register - VIDTCON2 */ ++#define S3C_VIDTCON2_LINEVAL(x) (((x)&0x7FF)<<11) /* these bits determine the vertical size of lcd panel */ ++#define S3C_VIDTCON2_HOZVAL(x) (((x)&0x7FF)<<0) /* these bits determine the horizontal size of lcd panel*/ ++ ++ ++/* Window 0~4 Control register - WINCONx */ ++#define S3C_WINCONx_WIDE_NARROW(x) (((x)&0x3)<<26) ++#define S3C_WINCONx_ENLOCAL_DMA (0<<22) ++#define S3C_WINCONx_ENLOCAL (1<<22) ++#define S3C_WINCONx_ENLOCAL_MASK (1<<22) ++#define S3C_WINCONx_BUFSEL_0 (0<<20) ++#define S3C_WINCONx_BUFSEL_1 (1<<20) ++#define S3C_WINCONx_BUFSEL_MASK (1<<20) ++#define S3C_WINCONx_BUFAUTOEN_DISABLE (0<<19) ++#define S3C_WINCONx_BUFAUTOEN_ENABLE (1<<19) ++#define S3C_WINCONx_BUFAUTOEN_MASK (1<<19) ++#define S3C_WINCONx_BITSWP_DISABLE (0<<18) ++#define S3C_WINCONx_BITSWP_ENABLE (1<<18) ++#define S3C_WINCONx_BYTSWP_DISABLE (0<<17) ++#define S3C_WINCONx_BYTSWP_ENABLE (1<<17) ++#define S3C_WINCONx_HAWSWP_DISABLE (0<<16) ++#define S3C_WINCONx_HAWSWP_ENABLE (1<<16) ++#define S3C_WINCONx_WSWP_DISABLE (0<<15) ++#define S3C_WINCONx_WSWP_ENABLE (1<<15) ++#define S3C_WINCONx_INRGB_RGB (0<<13) ++#define S3C_WINCONx_INRGB_YUV (1<<13) ++#define S3C_WINCONx_INRGB_MASK (1<<13) ++#define S3C_WINCONx_BURSTLEN_16WORD (0<<9) ++#define S3C_WINCONx_BURSTLEN_8WORD (1<<9) ++#define S3C_WINCONx_BURSTLEN_4WORD (2<<9) ++#define S3C_WINCONx_BLD_PIX_PLANE (0<<6) ++#define S3C_WINCONx_BLD_PIX_PIXEL (1<<6) ++#define S3C_WINCONx_BLD_PIX_MASK (1<<6) ++#define S3C_WINCONx_BPPMODE_F_1BPP (0<<2) ++#define S3C_WINCONx_BPPMODE_F_2BPP (1<<2) ++#define S3C_WINCONx_BPPMODE_F_4BPP (2<<2) ++#define S3C_WINCONx_BPPMODE_F_8BPP_PAL (3<<2) ++#define S3C_WINCONx_BPPMODE_F_8BPP_NOPAL (4<<2) ++#define S3C_WINCONx_BPPMODE_F_16BPP_565 (5<<2) ++#define S3C_WINCONx_BPPMODE_F_16BPP_A555 (6<<2) ++#define S3C_WINCONx_BPPMODE_F_18BPP_666 (8<<2) ++#define S3C_WINCONx_BPPMODE_F_24BPP_888 (11<<2) ++#define S3C_WINCONx_BPPMODE_F_24BPP_A887 (0xc<<2) ++#define S3C_WINCONx_BPPMODE_F_25BPP_A888 (0xd<<2) ++#define S3C_WINCONx_BPPMODE_F_28BPP_A888 (0xd<<2) ++#define S3C_WINCONx_BPPMODE_F_MASK (0xf<<2) ++#define S3C_WINCONx_ALPHA_SEL_0 (0<<1) ++#define S3C_WINCONx_ALPHA_SEL_1 (1<<1) ++#define S3C_WINCONx_ALPHA_SEL_MASK (1<<1) ++#define S3C_WINCONx_ENWIN_F_DISABLE (0<<0) ++#define S3C_WINCONx_ENWIN_F_ENABLE (1<<0) ++ ++/* Window 1-2 Control register - WINCON1 */ ++#define S3C_WINCON1_LOCALSEL_TV (0<<23) ++#define S3C_WINCON1_LOCALSEL_CAMERA (1<<23) ++#define S3C_WINCON1_LOCALSEL_MASK (1<<23) ++#define S3C_WINCON2_LOCALSEL_TV (0<<23) ++#define S3C_WINCON2_LOCALSEL_CAMERA (1<<23) ++#define S3C_WINCON2_LOCALSEL_MASK (1<<23) ++ ++/* Window 0~4 Position Control A register - VIDOSDxA */ ++#define S3C_VIDOSDxA_OSD_LTX_F(x) (((x)&0x7FF)<<11) ++#define S3C_VIDOSDxA_OSD_LTY_F(x) (((x)&0x7FF)<<0) ++ ++/* Window 0~4 Position Control B register - VIDOSDxB */ ++#define S3C_VIDOSDxB_OSD_RBX_F(x) (((x)&0x7FF)<<11) ++#define S3C_VIDOSDxB_OSD_RBY_F(x) (((x)&0x7FF)<<0) ++ ++/* Window 0 Position Control C register - VIDOSD0C */ ++#define S3C_VIDOSD0C_OSDSIZE(x) (((x)&0xFFFFFF)<<0) ++ ++/* Window 1~4 Position Control C register - VIDOSDxC */ ++#define S3C_VIDOSDxC_ALPHA0_R(x) (((x)&0xF)<<20) ++#define S3C_VIDOSDxC_ALPHA0_G(x) (((x)&0xF)<<16) ++#define S3C_VIDOSDxC_ALPHA0_B(x) (((x)&0xF)<<12) ++#define S3C_VIDOSDxC_ALPHA1_R(x) (((x)&0xF)<<8) ++#define S3C_VIDOSDxC_ALPHA1_G(x) (((x)&0xF)<<4) ++#define S3C_VIDOSDxC_ALPHA1_B(x) (((x)&0xF)<<0) ++ ++/* Window 1~2 Position Control D register - VIDOSDxD */ ++#define S3C_VIDOSDxD_OSDSIZE(x) (((x)&0xFFFFFF)<<0) ++ ++/* Frame buffer Start Address register - VIDWxxADD0 */ ++#define S3C_VIDWxxADD0_VBANK_F(x) (((x)&0xFF)<<23) /* the end address of the LCD frame buffer. */ ++#define S3C_VIDWxxADD0_VBASEU_F(x) (((x)&0xFFFFFF)<<0) /* Virtual screen offset size (the number of byte). */ ++ ++/* Frame buffer End Address register - VIDWxxADD1 */ ++#define S3C_VIDWxxADD1_VBASEL_F(x) (((x)&0xFFFFFF)<<0) /* the end address of the LCD frame buffer. */ ++ ++/* Frame buffer Size register - VIDWxxADD2 */ ++#define S3C_VIDWxxADD2_OFFSIZE_F(x) (((x)&0x1FFF)<<13) /* Virtual screen offset size (the number of byte). */ ++#define S3C_VIDWxxADD2_PAGEWIDTH_F(x) (((x)&0x1FFF)<<0) /* Virtual screen page width (the number of byte). */ ++ ++/* VIDEO Interrupt Control 0 register - VIDINTCON0 */ ++#define S3C_VIDINTCON0_FIFOINTERVAL(x) (((x)&0x3F)<<20) ++#define S3C_VIDINTCON0_SYSMAINCON_DISABLE (0<<19) ++#define S3C_VIDINTCON0_SYSMAINCON_ENABLE (1<<19) ++#define S3C_VIDINTCON0_SYSSUBCON_DISABLE (0<<18) ++#define S3C_VIDINTCON0_SYSSUBCON_ENABLE (1<<18) ++#define S3C_VIDINTCON0_SYSIFDONE_DISABLE (0<<17) ++#define S3C_VIDINTCON0_SYSIFDONE_ENABLE (1<<17) ++#define S3C_VIDINTCON0_FRAMESEL0_BACK (0<<15) ++#define S3C_VIDINTCON0_FRAMESEL0_VSYNC (1<<15) ++#define S3C_VIDINTCON0_FRAMESEL0_ACTIVE (2<<15) ++#define S3C_VIDINTCON0_FRAMESEL0_FRONT (3<<15) ++#define S3C_VIDINTCON0_FRAMESEL0_MASK (3<<15) ++#define S3C_VIDINTCON0_FRAMESEL1_NONE (0<<13) ++#define S3C_VIDINTCON0_FRAMESEL1_BACK (1<<13) ++#define S3C_VIDINTCON0_FRAMESEL1_VSYNC (2<<13) ++#define S3C_VIDINTCON0_FRAMESEL1_FRONT (3<<13) ++#define S3C_VIDINTCON0_INTFRMEN_DISABLE (0<<12) ++#define S3C_VIDINTCON0_INTFRMEN_ENABLE (1<<12) ++#define S3C_VIDINTCON0_FRAMEINT_MASK (0x1F<<12) ++#define S3C_VIDINTCON0_FIFOSEL_WIN4 (1<<11) ++#define S3C_VIDINTCON0_FIFOSEL_WIN3 (1<<10) ++#define S3C_VIDINTCON0_FIFOSEL_WIN2 (1<<9) ++#define S3C_VIDINTCON0_FIFOSEL_WIN1 (1<<6) ++#define S3C_VIDINTCON0_FIFOSEL_WIN0 (1<<5) ++#define S3C_VIDINTCON0_FIFOSEL_ALL (0x73<<5) ++#define S3C_VIDINTCON0_FIFOLEVEL_25 (0<<2) ++#define S3C_VIDINTCON0_FIFOLEVEL_50 (1<<2) ++#define S3C_VIDINTCON0_FIFOLEVEL_75 (2<<2) ++#define S3C_VIDINTCON0_FIFOLEVEL_EMPTY (3<<2) ++#define S3C_VIDINTCON0_FIFOLEVEL_FULL (4<<2) ++#define S3C_VIDINTCON0_INTFIFOEN_DISABLE (0<<1) ++#define S3C_VIDINTCON0_INTFIFOEN_ENABLE (1<<1) ++#define S3C_VIDINTCON0_INTEN_DISABLE (0<<0) ++#define S3C_VIDINTCON0_INTEN_ENABLE (1<<0) ++#define S3C_VIDINTCON0_INTEN_MASK (1<<0) ++ ++/* VIDEO Interrupt Control 1 register - VIDINTCON1 */ ++#define S3C_VIDINTCON1_INTI80PEND (0<<2) ++#define S3C_VIDINTCON1_INTFRMPEND (1<<1) ++#define S3C_VIDINTCON1_INTFIFOPEND (1<<0) ++ ++/* WIN 1~4 Color Key 0 register - WxKEYCON0 */ ++#define S3C_WxKEYCON0_KEYBLEN_DISABLE (0<<26) ++#define S3C_WxKEYCON0_KEYBLEN_ENABLE (1<<26) ++#define S3C_WxKEYCON0_KEYEN_F_DISABLE (0<<25) ++#define S3C_WxKEYCON0_KEYEN_F_ENABLE (1<<25) ++#define S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE (0<<24) ++#define S3C_WxKEYCON0_DIRCON_MATCH_BG_IMAGE (1<<24) ++#define S3C_WxKEYCON0_COMPKEY(x) (((x)&0xFFFFFF)<<0) ++ ++/* WIN 1~4 Color Key 1 register - WxKEYCON1 */ ++#define S3C_WxKEYCON1_COLVAL(x) (((x)&0xFFFFFF)<<0) ++ ++/* Dithering Control 1 register - DITHMODE */ ++#define S3C_DITHMODE_RDITHPOS_8BIT (0<<5) ++#define S3C_DITHMODE_RDITHPOS_6BIT (1<<5) ++#define S3C_DITHMODE_RDITHPOS_5BIT (2<<5) ++#define S3C_DITHMODE_GDITHPOS_8BIT (0<<3) ++#define S3C_DITHMODE_GDITHPOS_6BIT (1<<3) ++#define S3C_DITHMODE_GDITHPOS_5BIT (2<<3) ++#define S3C_DITHMODE_BDITHPOS_8BIT (0<<1) ++#define S3C_DITHMODE_BDITHPOS_6BIT (1<<1) ++#define S3C_DITHMODE_BDITHPOS_5BIT (2<<1) ++#define S3C_DITHMODE_RGB_DITHPOS_MASK (0x3f<<1) ++#define S3C_DITHMODE_DITHERING_DISABLE (0<<0) ++#define S3C_DITHMODE_DITHERING_ENABLE (1<<0) ++#define S3C_DITHMODE_DITHERING_MASK (1<<0) ++ ++/* Window 0~4 Color map register - WINxMAP */ ++#define S3C_WINxMAP_MAPCOLEN_F_ENABLE (1<<24) ++#define S3C_WINxMAP_MAPCOLEN_F_DISABLE (0<<24) ++#define S3C_WINxMAP_MAPCOLOR (((x)&0xFFFFFF)<<0) ++ ++/* Window Palette Control register - WPALCON */ ++#define S3C_WPALCON_PALUPDATEEN (1<<9) ++#define S3C_WPALCON_W4PAL_16BIT_A (1<<8) /* A:5:5:5 */ ++#define S3C_WPALCON_W4PAL_16BIT (0<<8) /* 5:6:5 */ ++#define S3C_WPALCON_W3PAL_16BIT_A (1<<7) /* A:5:5:5 */ ++#define S3C_WPALCON_W3PAL_16BIT (0<<7) /* 5:6:5 */ ++#define S3C_WPALCON_W2PAL_16BIT_A (1<<6) /* A:5:5:5 */ ++#define S3C_WPALCON_W2PAL_16BIT (0<<6) /* 5:6:5 */ ++#define S3C_WPALCON_W1PAL_25BIT_A (0<<3) /* A:8:8:8 */ ++#define S3C_WPALCON_W1PAL_24BIT (1<<3) /* 8:8:8 */ ++#define S3C_WPALCON_W1PAL_19BIT_A (2<<3) /* A:6:6:6 */ ++#define S3C_WPALCON_W1PAL_18BIT_A (3<<3) /* A:6:6:5 */ ++#define S3C_WPALCON_W1PAL_18BIT (4<<3) /* 6:6:6 */ ++#define S3C_WPALCON_W1PAL_16BIT_A (5<<3) /* A:5:5:5 */ ++#define S3C_WPALCON_W1PAL_16BIT (6<<3) /* 5:6:5 */ ++#define S3C_WPALCON_W0PAL_25BIT_A (0<<0) /* A:8:8:8 */ ++#define S3C_WPALCON_W0PAL_24BIT (1<<0) /* 8:8:8 */ ++#define S3C_WPALCON_W0PAL_19BIT_A (2<<0) /* A:6:6:6 */ ++#define S3C_WPALCON_W0PAL_18BIT_A (3<<0) /* A:6:6:5 */ ++#define S3C_WPALCON_W0PAL_18BIT (4<<0) /* 6:6:6 */ ++#define S3C_WPALCON_W0PAL_16BIT_A (5<<0) /* A:5:5:5 */ ++#define S3C_WPALCON_W0PAL_16BIT (6<<0) /* 5:6:5 */ ++ ++/* I80/RGB Trigger Control register - TRIGCON */ ++#define S3C_TRIGCON_SWFRSTATUS_REQUESTED (1<<2) ++#define S3C_TRIGCON_SWFRSTATUS_NOT_REQUESTED (0<<2) ++#define S3C_TRIGCON_SWTRGCMD (1<<1) ++#define S3C_TRIGCON_TRGMODE_ENABLE (1<<0) ++#define S3C_TRIGCON_TRGMODE_DISABLE (0<<0) ++ ++/* LCD I80 Interface Control 0 register - I80IFCONA0 */ ++#define S3C_I80IFCONAx_LCD_CS_SETUP(x) (((x)&0xF)<<16) ++#define S3C_I80IFCONAx_LCD_WR_SETUP(x) (((x)&0xF)<<12) ++#define S3C_I80IFCONAx_LCD_WR_ACT(x) (((x)&0xF)<<8) ++#define S3C_I80IFCONAx_LCD_WR_HOLD(x) (((x)&0xF)<<4) ++ ++ ++/***************************************************************************/ ++/*HOST IF registers */ ++/* Host I/F A - */ ++#define S3C_HOSTIFAREG(x) ((x) + S3C64XX_VA_HOSTIFA) ++#define S3C_HOSTIFAREG_PHYS(x) ((x) + S3C64XX_PA_HOSTIFA) ++ ++/* Host I/F B - Modem I/F */ ++#define S3C_HOSTIFBREG(x) ((x) + S3C64XX_VA_HOSTIFB) ++#define S3C_HOSTIFBREG_PHYS(x) ((x) + S3C64XX_PA_HOSTIFB) ++ ++#define S3C_HOSTIFB_INT2AP S3C_HOSTIFBREG(0x8000) ++#define S3C_HOSTIFB_INT2MSM S3C_HOSTIFBREG(0x8004) ++#define S3C_HOSTIFB_MIFCON S3C_HOSTIFBREG(0x8008) ++#define S3C_HOSTIFB_MIFPCON S3C_HOSTIFBREG(0x800C) ++#define S3C_HOSTIFB_MSMINTCLR S3C_HOSTIFBREG(0x8010) ++ ++#define S3C_HOSTIFB_MIFCON_INT2MSM_DIS (0x0<<3) ++#define S3C_HOSTIFB_MIFCON_INT2MSM_EN (0x1<<3) ++#define S3C_HOSTIFB_MIFCON_INT2AP_DIS (0x0<<2) ++#define S3C_HOSTIFB_MIFCON_INT2AP_EN (0x1<<2) ++#define S3C_HOSTIFB_MIFCON_WAKEUP_DIS (0x0<<1) ++#define S3C_HOSTIFB_MIFCON_WAKEUP_EN (0x1<<1) ++ ++#define S3C_HOSTIFB_MIFPCON_SEL_VSYNC_DIR_OUT (0x0<<5) ++#define S3C_HOSTIFB_MIFPCON_SEL_VSYNC_DIR_IN (0x1<<5) ++#define S3C_HOSTIFB_MIFPCON_INT2M_LEVEL_DIS (0x0<<4) ++#define S3C_HOSTIFB_MIFPCON_INT2M_LEVEL_EN (0x1<<4) ++#define S3C_HOSTIFB_MIFPCON_SEL_NORMAL (0x0<<3) ++#define S3C_HOSTIFB_MIFPCON_SEL_BYPASS (0x1<<3) ++ ++#define S3C_HOSTIFB_MIFPCON_SEL_RS0 0 ++#define S3C_HOSTIFB_MIFPCON_SEL_RS1 1 ++#define S3C_HOSTIFB_MIFPCON_SEL_RS2 2 ++#define S3C_HOSTIFB_MIFPCON_SEL_RS3 3 ++#define S3C_HOSTIFB_MIFPCON_SEL_RS4 4 ++#define S3C_HOSTIFB_MIFPCON_SEL_RS5 5 ++#define S3C_HOSTIFB_MIFPCON_SEL_RS6 6 ++ ++#define S3C_WINCONx_ENLOCAL_POST (1<<22) ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-nand.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-nand.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-nand.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-nand.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,172 @@ ++/* linux/arch/arm/plat-s3c/include/plat/regs-nand.h ++ * ++ * Copyright (c) 2004,2005 Simtec Electronics ++ * http://www.simtec.co.uk/products/SWLINUX/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C2410 NAND register definitions ++*/ ++ ++#ifndef __ASM_ARM_REGS_NAND ++#define __ASM_ARM_REGS_NAND ++ ++ ++#define S3C2410_NFREG(x) (x) ++ ++#define S3C2410_NFCONF S3C2410_NFREG(0x00) ++#define S3C2410_NFCMD S3C2410_NFREG(0x04) ++#define S3C2410_NFADDR S3C2410_NFREG(0x08) ++#define S3C2410_NFDATA S3C2410_NFREG(0x0C) ++#define S3C2410_NFSTAT S3C2410_NFREG(0x10) ++#define S3C2410_NFECC S3C2410_NFREG(0x14) ++ ++#define S3C2440_NFCONT S3C2410_NFREG(0x04) ++#define S3C2440_NFCMD S3C2410_NFREG(0x08) ++#define S3C2440_NFADDR S3C2410_NFREG(0x0C) ++#define S3C2440_NFDATA S3C2410_NFREG(0x10) ++#define S3C2440_NFECCD0 S3C2410_NFREG(0x14) ++#define S3C2440_NFECCD1 S3C2410_NFREG(0x18) ++#define S3C2440_NFECCD S3C2410_NFREG(0x1C) ++#define S3C2440_NFSTAT S3C2410_NFREG(0x20) ++#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24) ++#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28) ++#define S3C2440_NFMECC0 S3C2410_NFREG(0x2C) ++#define S3C2440_NFMECC1 S3C2410_NFREG(0x30) ++#define S3C2440_NFSECC S3C2410_NFREG(0x34) ++#define S3C2440_NFSBLK S3C2410_NFREG(0x38) ++#define S3C2440_NFEBLK S3C2410_NFREG(0x3C) ++ ++#define S3C2412_NFSBLK S3C2410_NFREG(0x20) ++#define S3C2412_NFEBLK S3C2410_NFREG(0x24) ++#define S3C2412_NFSTAT S3C2410_NFREG(0x28) ++#define S3C2412_NFMECC_ERR0 S3C2410_NFREG(0x2C) ++#define S3C2412_NFMECC_ERR1 S3C2410_NFREG(0x30) ++#define S3C2412_NFMECC0 S3C2410_NFREG(0x34) ++#define S3C2412_NFMECC1 S3C2410_NFREG(0x38) ++#define S3C2412_NFSECC S3C2410_NFREG(0x3C) ++ ++#define S3C2410_NFCONF_EN (1<<15) ++#define S3C2410_NFCONF_512BYTE (1<<14) ++#define S3C2410_NFCONF_4STEP (1<<13) ++#define S3C2410_NFCONF_INITECC (1<<12) ++#define S3C2410_NFCONF_nFCE (1<<11) ++#define S3C2410_NFCONF_TACLS(x) ((x)<<8) ++#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) ++#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0) ++ ++#define S3C2410_NFSTAT_BUSY (1<<0) ++ ++#define S3C2440_NFCONF_BUSWIDTH_8 (0<<0) ++#define S3C2440_NFCONF_BUSWIDTH_16 (1<<0) ++#define S3C2440_NFCONF_ADVFLASH (1<<3) ++#define S3C2440_NFCONF_TACLS(x) ((x)<<12) ++#define S3C2440_NFCONF_TWRPH0(x) ((x)<<8) ++#define S3C2440_NFCONF_TWRPH1(x) ((x)<<4) ++ ++#define S3C2440_NFCONT_LOCKTIGHT (1<<13) ++#define S3C2440_NFCONT_SOFTLOCK (1<<12) ++#define S3C2440_NFCONT_ILLEGALACC_EN (1<<10) ++#define S3C2440_NFCONT_RNBINT_EN (1<<9) ++#define S3C2440_NFCONT_RN_FALLING (1<<8) ++#define S3C2440_NFCONT_SPARE_ECCLOCK (1<<6) ++#define S3C2440_NFCONT_MAIN_ECCLOCK (1<<5) ++#define S3C2440_NFCONT_INITECC (1<<4) ++#define S3C2440_NFCONT_nFCE (1<<1) ++#define S3C2440_NFCONT_ENABLE (1<<0) ++ ++#define S3C2440_NFSTAT_READY (1<<0) ++#define S3C2440_NFSTAT_nCE (1<<1) ++#define S3C2440_NFSTAT_RnB_CHANGE (1<<2) ++#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1<<3) ++ ++#define S3C2412_NFCONF_NANDBOOT (1<<31) ++#define S3C2412_NFCONF_ECCCLKCON (1<<30) ++#define S3C2412_NFCONF_ECC_MLC (1<<24) ++#define S3C2412_NFCONF_TACLS_MASK (7<<12) /* 1 extra bit of Tacls */ ++ ++#define S3C2412_NFCONT_ECC4_DIRWR (1<<18) ++#define S3C2412_NFCONT_LOCKTIGHT (1<<17) ++#define S3C2412_NFCONT_SOFTLOCK (1<<16) ++#define S3C2412_NFCONT_ECC4_ENCINT (1<<13) ++#define S3C2412_NFCONT_ECC4_DECINT (1<<12) ++#define S3C2412_NFCONT_MAIN_ECC_LOCK (1<<7) ++#define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5) ++#define S3C2412_NFCONT_nFCE1 (1<<2) ++#define S3C2412_NFCONT_nFCE0 (1<<1) ++ ++#define S3C2412_NFSTAT_ECC_ENCDONE (1<<7) ++#define S3C2412_NFSTAT_ECC_DECDONE (1<<6) ++#define S3C2412_NFSTAT_ILLEGAL_ACCESS (1<<5) ++#define S3C2412_NFSTAT_RnB_CHANGE (1<<4) ++#define S3C2412_NFSTAT_nFCE1 (1<<3) ++#define S3C2412_NFSTAT_nFCE0 (1<<2) ++#define S3C2412_NFSTAT_Res1 (1<<1) ++#define S3C2412_NFSTAT_READY (1<<0) ++ ++#define S3C2412_NFECCERR_SERRDATA(x) (((x) >> 21) & 0xf) ++#define S3C2412_NFECCERR_SERRBIT(x) (((x) >> 18) & 0x7) ++#define S3C2412_NFECCERR_MERRDATA(x) (((x) >> 7) & 0x3ff) ++#define S3C2412_NFECCERR_MERRBIT(x) (((x) >> 4) & 0x7) ++#define S3C2412_NFECCERR_SPARE_ERR(x) (((x) >> 2) & 0x3) ++#define S3C2412_NFECCERR_MAIN_ERR(x) (((x) >> 2) & 0x3) ++#define S3C2412_NFECCERR_NONE (0) ++#define S3C2412_NFECCERR_1BIT (1) ++#define S3C2412_NFECCERR_MULTIBIT (2) ++#define S3C2412_NFECCERR_ECCAREA (3) ++ ++/* for s3c_nand.c */ ++#define S3C_NFCONF S3C2410_NFREG(0x00) ++#define S3C_NFCONT S3C2410_NFREG(0x04) ++#define S3C_NFCMMD S3C2410_NFREG(0x08) ++#define S3C_NFADDR S3C2410_NFREG(0x0c) ++#define S3C_NFDATA8 S3C2410_NFREG(0x10) ++#define S3C_NFDATA S3C2410_NFREG(0x10) ++#define S3C_NFMECCDATA0 S3C2410_NFREG(0x14) ++#define S3C_NFMECCDATA1 S3C2410_NFREG(0x18) ++#define S3C_NFSECCDATA S3C2410_NFREG(0x1c) ++#define S3C_NFSBLK S3C2410_NFREG(0x20) ++#define S3C_NFEBLK S3C2410_NFREG(0x24) ++#define S3C_NFSTAT S3C2410_NFREG(0x28) ++#define S3C_NFMECCERR0 S3C2410_NFREG(0x2c) ++#define S3C_NFMECCERR1 S3C2410_NFREG(0x30) ++#define S3C_NFMECC0 S3C2410_NFREG(0x34) ++#define S3C_NFMECC1 S3C2410_NFREG(0x38) ++#define S3C_NFSECC S3C2410_NFREG(0x3c) ++#define S3C_NFMLCBITPT S3C2410_NFREG(0x40) ++ ++#define S3C_NFCONF_NANDBOOT (1<<31) ++#define S3C_NFCONF_ECCCLKCON (1<<30) ++#define S3C_NFCONF_ECC_MLC (1<<24) ++#define S3C_NFCONF_ECC_1BIT (0<<23) ++#define S3C_NFCONF_ECC_4BIT (2<<23) ++#define S3C_NFCONF_ECC_8BIT (1<<23) ++#define S3C_NFCONF_TACLS(x) ((x)<<12) ++#define S3C_NFCONF_TWRPH0(x) ((x)<<8) ++#define S3C_NFCONF_TWRPH1(x) ((x)<<4) ++#define S3C_NFCONF_ADVFLASH (1<<3) ++#define S3C_NFCONF_PAGESIZE (1<<2) ++#define S3C_NFCONF_ADDRCYCLE (1<<1) ++#define S3C_NFCONF_BUSWIDTH (1<<0) ++ ++#define S3C_NFCONT_ECC_ENC (1<<18) ++#define S3C_NFCONT_LOCKTGHT (1<<17) ++#define S3C_NFCONT_LOCKSOFT (1<<16) ++#define S3C_NFCONT_MECCLOCK (1<<7) ++#define S3C_NFCONT_SECCLOCK (1<<6) ++#define S3C_NFCONT_INITMECC (1<<5) ++#define S3C_NFCONT_INITSECC (1<<4) ++#define S3C_NFCONT_nFCE1 (1<<2) ++#define S3C_NFCONT_nFCE0 (1<<1) ++#define S3C_NFCONT_INITECC (S3C_NFCONT_INITSECC | S3C_NFCONT_INITMECC) ++ ++#define S3C_NFSTAT_ECCENCDONE (1<<7) ++#define S3C_NFSTAT_ECCDECDONE (1<<6) ++#define S3C_NFSTAT_BUSY (1<<0) ++ ++#define S3C_NFECCERR0_ECCBUSY (1<<31) ++ ++#endif /* __ASM_ARM_REGS_NAND */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-onenand.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-onenand.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-onenand.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-onenand.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,409 @@ ++#ifndef __ASM_ARCH_REGS_ONENAND_H ++#define __ASM_ARCH_REGS_ONENAND_H __FILE__ ++ ++/* ++ * DMA for OneNAND ++ */ ++#define ONENAND_DMA_CON (0) ++#if defined(CONFIG_CPU_S3C6410) ++#define ONENAND_DMA_BASE (0x75000000) ++#endif ++#define ONENAND_DMA_TRANSFER_WORD (4) ++ ++/* ++ * SFRs ++ */ ++#define ONENAND_REG_MEM_CFG (0x000) ++#define ONENAND_REG_BURST_LEN (0x010) ++#define ONENAND_REG_MEM_RESET (0x020) ++#define ONENAND_REG_INT_ERR_STAT (0x030) ++#define ONENAND_REG_INT_ERR_MASK (0x040) ++#define ONENAND_REG_INT_ERR_ACK (0x050) ++#define ONENAND_REG_ECC_ERR_STAT (0x060) ++#define ONENAND_REG_MANUFACT_ID (0x070) ++#define ONENAND_REG_DEVICE_ID (0x080) ++#define ONENAND_REG_DATA_BUF_SIZE (0x090) ++#define ONENAND_REG_BOOT_BUF_SIZE (0x0A0) ++#define ONENAND_REG_BUF_AMOUNT (0x0B0) ++#define ONENAND_REG_TECH (0x0C0) ++#define ONENAND_REG_FBA_WIDTH (0x0D0) ++#define ONENAND_REG_FPA_WIDTH (0x0E0) ++#define ONENAND_REG_FSA_WIDTH (0x0F0) ++#define ONENAND_REG_REVISION (0x100) ++#define ONENAND_REG_DATARAM0 (0x110) ++#define ONENAND_REG_DATARAM1 (0x120) ++#define ONENAND_REG_SYNC_MODE (0x130) ++#define ONENAND_REG_TRANS_SPARE (0x140) ++#define ONENAND_REG_LOCK_BIT (0x150) ++#define ONENAND_REG_DBS_DFS_WIDTH (0x160) ++#define ONENAND_REG_PAGE_CNT (0x170) ++#define ONENAND_REG_ERR_PAGE_ADDR (0x180) ++#define ONENAND_REG_BURST_RD_LAT (0x190) ++#define ONENAND_REG_INT_PIN_ENABLE (0x1A0) ++#define ONENAND_REG_INT_MON_CYC (0x1B0) ++#define ONENAND_REG_ACC_CLOCK (0x1C0) ++#define ONENAND_REG_SLOW_RD_PATH (0x1D0) ++#define ONENAND_REG_ERR_BLK_ADDR (0x1E0) ++#define ONENAND_REG_FLASH_VER_ID (0x1F0) ++ ++#if defined(CONFIG_CPU_S3C6410) ++#define ONENAND_REG_FLASH_AUX_CNTRL (0x300) ++#elif defined(CONFIG_CPU_S5PC100) ++#define ONENAND_REG_ECC_ERR_STAT2 (0x300) ++#endif ++ ++#if defined(CONFIG_CPU_S5PC100) ++#define ONENAND_REG_BANK_EN (0x220) ++#define ONENAND_REG_WTCHDOG_RST_L (0x260) ++#define ONENAND_REG_WTCHDOG_RST_H (0x270) ++#define ONENAND_REG_SYNC_WRITE (0x280) ++#define ONENAND_REG_CACHE_READ (0x290) ++#define ONENAND_REG_COLD_RST_DLY (0x2A0) ++#define ONENAND_REG_DDP_DEVICE (0x2B0) ++#define ONENAND_REG_MULTI_PLANE (0x2C0) ++#define ONENAND_REG_MEM_CNT (0x2D0) ++#define ONENAND_REG_TRANS_MODE (0x2E0) ++#define ONENAND_REG_DEV_STAT (0x2F0) ++ ++#define ONENAND_REG_ECC_ERR_STAT3 (0x310) ++#define ONENAND_REG_ECC_ERR_STAT4 (0x320) ++#define ONENAND_REG_EFCT_BUF_CNT (0x330) ++#define ONENAND_REG_DEV_PAGE_SIZE (0x340) ++#define ONENAND_REG_SUPERLOAD_EN (0x350) ++#define ONENAND_REG_CACHE_PRG_EN (0x360) ++#define ONENAND_REG_SINGLE_PAGE_BUF (0x370) ++#define ONENAND_REG_OFFSET_ADDR (0x380) ++#define ONENAND_REG_INT_MON_STATUS (0x390) ++#endif ++ ++/* ++ * SFR values ++ */ ++#define ONENAND_MEM_CFG_SYNC_READ (1 << 15) ++#define ONENAND_MEM_CFG_BRL_7 (7 << 12) ++#define ONENAND_MEM_CFG_BRL_6 (6 << 12) ++#define ONENAND_MEM_CFG_BRL_5 (5 << 12) ++#define ONENAND_MEM_CFG_BRL_4 (4 << 12) ++#define ONENAND_MEM_CFG_BRL_3 (3 << 12) ++#define ONENAND_MEM_CFG_BRL_10 (2 << 12) ++#define ONENAND_MEM_CFG_BRL_9 (1 << 12) ++#define ONENAND_MEM_CFG_BRL_8 (0 << 12) ++#define ONENAND_MEM_CFG_BRL_SHIFT (12) ++#define ONENAND_MEM_CFG_BL_1K (5 << 9) ++#define ONENAND_MEM_CFG_BL_32 (4 << 9) ++#define ONENAND_MEM_CFG_BL_16 (3 << 9) ++#define ONENAND_MEM_CFG_BL_8 (2 << 9) ++#define ONENAND_MEM_CFG_BL_4 (1 << 9) ++#define ONENAND_MEM_CFG_BL_CONT (0 << 9) ++#define ONENAND_MEM_CFG_BL_SHIFT (9) ++#define ONENAND_MEM_CFG_NO_ECC (1 << 8) ++#define ONENAND_MEM_CFG_RDY_HIGH (1 << 7) ++#define ONENAND_MEM_CFG_INT_HIGH (1 << 6) ++#define ONENAND_MEM_CFG_IOBE (1 << 5) ++#define ONENAND_MEM_CFG_RDY_CONF (1 << 4) ++#define ONENAND_MEM_CFG_HF (1 << 2) ++#define ONENAND_MEM_CFG_WM_SYNC (1 << 1) ++#define ONENAND_MEM_CFG_BWPS_UNLOCK (1 << 0) ++ ++#define ONENAND_BURST_LEN_CONT (0) ++#define ONENAND_BURST_LEN_4 (4) ++#define ONENAND_BURST_LEN_8 (8) ++#define ONENAND_BURST_LEN_16 (16) ++ ++#define ONENAND_MEM_RESET_WARM (0x1) ++#define ONENAND_MEM_RESET_COLD (0x2) ++#define ONENAND_MEM_RESET_HOT (0x3) ++ ++#define ONENAND_INT_ERR_CACHE_OP_ERR (1 << 13) ++#define ONENAND_INT_ERR_RST_CMP (1 << 12) ++#define ONENAND_INT_ERR_RDY_ACT (1 << 11) ++#define ONENAND_INT_ERR_INT_ACT (1 << 10) ++#define ONENAND_INT_ERR_UNSUP_CMD (1 << 9) ++#define ONENAND_INT_ERR_LOCKED_BLK (1 << 8) ++#define ONENAND_INT_ERR_BLK_RW_CMP (1 << 7) ++#define ONENAND_INT_ERR_ERS_CMP (1 << 6) ++#define ONENAND_INT_ERR_PGM_CMP (1 << 5) ++#define ONENAND_INT_ERR_LOAD_CMP (1 << 4) ++#define ONENAND_INT_ERR_ERS_FAIL (1 << 3) ++#define ONENAND_INT_ERR_PGM_FAIL (1 << 2) ++#define ONENAND_INT_ERR_INT_TO (1 << 1) ++#define ONENAND_INT_ERR_LD_FAIL_ECC_ERR (1 << 0) ++ ++#define ONENAND_DEVICE_DENSITY_SHIFT (4) ++#define ONENAND_DEVICE_IS_DDP (1 << 3) ++#define ONENAND_DEVICE_IS_DEMUX (1 << 2) ++#define ONENAND_DEVICE_VCC_MASK (0x3) ++#define ONENAND_DEVICE_DENSITY_128Mb (0x000) ++#define ONENAND_DEVICE_DENSITY_256Mb (0x001) ++#define ONENAND_DEVICE_DENSITY_512Mb (0x002) ++#define ONENAND_DEVICE_DENSITY_1Gb (0x003) ++#define ONENAND_DEVICE_DENSITY_2Gb (0x004) ++#define ONENAND_DEVICE_DENSITY_4Gb (0x005) ++ ++#define ONENAND_SYNC_MODE_RM_SYNC (1 << 1) ++#define ONENAND_SYNC_MODE_WM_SYNC (1 << 0) ++ ++#define ONENAND_TRANS_SPARE_TSRF_INC (1 << 0) ++ ++#define ONENAND_INT_PIN_ENABLE (1 << 0) ++ ++#define ONENAND_ACC_CLOCK_266_133 (0x5) ++#define ONENAND_ACC_CLOCK_166_83 (0x3) ++#define ONENAND_ACC_CLOCK_134_67 (0x3) ++#define ONENAND_ACC_CLOCK_100_50 (0x2) ++#define ONENAND_ACC_CLOCK_60_30 (0x2) ++ ++#if defined(CONFIG_CPU_S3C6410) ++#define ONENAND_FLASH_AUX_WD_DISABLE (1 << 0) ++#endif ++ ++/* ++ * Datain values for mapped commands ++ */ ++#define ONENAND_DATAIN_ERASE_STATUS (0x00) ++#define ONENAND_DATAIN_ERASE_MULTI (0x01) ++#define ONENAND_DATAIN_ERASE_SINGLE (0x03) ++#define ONENAND_DATAIN_ERASE_VERIFY (0x15) ++#define ONENAND_DATAIN_UNLOCK_START (0x08) ++#define ONENAND_DATAIN_UNLOCK_END (0x09) ++#define ONENAND_DATAIN_LOCK_START (0x0A) ++#define ONENAND_DATAIN_LOCK_END (0x0B) ++#define ONENAND_DATAIN_LOCKTIGHT_START (0x0C) ++#define ONENAND_DATAIN_LOCKTIGHT_END (0x0D) ++#define ONENAND_DATAIN_UNLOCK_ALL (0x0E) ++#define ONENAND_DATAIN_COPYBACK_SRC (0x1000) ++#define ONENAND_DATAIN_COPYBACK_DST (0x2000) ++#define ONENAND_DATAIN_ACCESS_OTP (0x12) ++#define ONENAND_DATAIN_ACCESS_MAIN (0x14) ++#define ONENAND_DATAIN_PIPELINE_READ (0x4000) ++#define ONENAND_DATAIN_PIPELINE_WRITE (0x4100) ++#define ONENAND_DATAIN_RMW_LOAD (0x10) ++#define ONENAND_DATAIN_RMW_MODIFY (0x11) ++ ++/* ++ * Device ID Register F001h (R) ++ */ ++#define ONENAND_DEVICE_DENSITY_SHIFT (4) ++#define ONENAND_DEVICE_IS_DDP (1 << 3) ++#define ONENAND_DEVICE_IS_DEMUX (1 << 2) ++#define ONENAND_DEVICE_VCC_MASK (0x3) ++ ++/* ++ * Version ID Register F002h (R) ++ */ ++#define ONENAND_VERSION_PROCESS_SHIFT (8) ++ ++/* ++ * Start Address 1 F100h (R/W) ++ */ ++#define ONENAND_DDP_SHIFT (15) ++#define ONENAND_DDP_CHIP0 (0) ++#define ONENAND_DDP_CHIP1 (1 << ONENAND_DDP_SHIFT) ++ ++/* ++ * Start Buffer Register F200h (R/W) ++ */ ++#define ONENAND_BSA_MASK (0x03) ++#define ONENAND_BSA_SHIFT (8) ++#define ONENAND_BSA_BOOTRAM (0 << 2) ++#define ONENAND_BSA_DATARAM0 (2 << 2) ++#define ONENAND_BSA_DATARAM1 (3 << 2) ++#define ONENAND_BSC_MASK (0x03) ++ ++/* ++ * Command Register F220h (R/W) ++ */ ++#define ONENAND_CMD_READ (0x00) ++#define ONENAND_CMD_READOOB (0x13) ++#define ONENAND_CMD_PROG (0x80) ++#define ONENAND_CMD_PROGOOB (0x1A) ++#define ONENAND_CMD_UNLOCK (0x23) ++#define ONENAND_CMD_LOCK (0x2A) ++#define ONENAND_CMD_LOCK_TIGHT (0x2C) ++#define ONENAND_CMD_UNLOCK_ALL (0x27) ++#define ONENAND_CMD_ERASE (0x94) ++#define ONENAND_CMD_RESET (0xF0) ++#define ONENAND_CMD_OTP_ACCESS (0x65) ++#define ONENAND_CMD_READID (0x90) ++#define ONENAND_CMD_STARTADDR1 (0xE0) ++#define ONENAND_CMD_WP_STATUS (0xE1) ++#define ONENAND_CMD_PIPELINE_READ (0x01) ++#define ONENAND_CMD_PIPELINE_WRITE (0x81) ++ ++/* ++ * Command Mapping for OneNAND Controller ++ */ ++#if defined(CONFIG_CPU_S5PC100) ++#define ONENAND_AHB_ADDR (0xB0000000) ++#elif defined(CONFIG_CPU_S3C6410) ++#define ONENAND_DUMMY_ADDR (0x20400000) ++#define ONENAND_AHB_ADDR (0x20000000) ++#endif ++#define ONENAND_CMD_MAP_00 (0x0) ++#define ONENAND_CMD_MAP_01 (0x1) ++#define ONENAND_CMD_MAP_10 (0x2) ++#define ONENAND_CMD_MAP_11 (0x3) ++#define ONENAND_CMD_MAP_FF (0xF) ++ ++#if defined(CONFIG_CPU_S3C6400) ++#define ONENAND_CMD_SHIFT (22) ++#define ONENAND_MEM_ADDR_MASK (0x3fffff) ++#define ONENAND_DDP_SHIFT_1Gb (19) ++#define ONENAND_DDP_SHIFT_2Gb (20) ++#define ONENAND_DDP_SHIFT_4Gb (21) ++ ++#define ONENAND_FBA_SHIFT_128Mb (9) ++#define ONENAND_FBA_SHIFT_256Mb (9) ++#define ONENAND_FBA_SHIFT_512Mb (10) ++#define ONENAND_FBA_SHIFT_1Gb_DDP (10) ++#define ONENAND_FBA_SHIFT_1Gb (10) ++#define ONENAND_FBA_SHIFT_2Gb_DDP (10) ++#define ONENAND_FBA_SHIFT_2Gb (10) ++#define ONENAND_FBA_SHIFT_4Gb_DDP (10) ++#define ONENAND_FBA_SHIFT_4Gb (10) ++ ++#define ONENAND_FPA_SHIFT_128Mb (3) ++#define ONENAND_FPA_SHIFT_256Mb (3) ++#define ONENAND_FPA_SHIFT_512Mb (4) ++#define ONENAND_FPA_SHIFT_1Gb_DDP (4) ++#define ONENAND_FPA_SHIFT_1Gb (4) ++#define ONENAND_FPA_SHIFT_2Gb_DDP (4) ++#define ONENAND_FPA_SHIFT_2Gb (4) ++#define ONENAND_FPA_SHIFT_4Gb_DDP (4) ++#define ONENAND_FPA_SHIFT_4Gb (4) ++ ++#define ONENAND_FSA_SHIFT (2) ++#define ONENAND_FBA_MASK_128Mb (0xff) ++#define ONENAND_FBA_MASK_256Mb (0x1ff) ++#define ONENAND_FBA_MASK_512Mb (0x1ff) ++#define ONENAND_FBA_MASK_1Gb_DDP (0x1ff) ++#define ONENAND_FBA_MASK_1Gb (0x3ff) ++#define ONENAND_FBA_MASK_2Gb_DDP (0x3ff) ++#define ONENAND_FBA_MASK_2Gb (0x7ff) ++#define ONENAND_FBA_MASK_4Gb_DDP (0x7ff) ++#define ONENAND_FBA_MASK_4Gb (0xfff) ++#define ONENAND_FPA_MASK (0x3f) ++#define ONENAND_FSA_MASK (0x3) ++ ++#elif defined(CONFIG_CPU_S3C6410) ++#define ONENAND_CMD_SHIFT (24) ++#define ONENAND_MEM_ADDR_MASK (0xffffff) ++#define ONENAND_DDP_SHIFT_1Gb (21) ++#define ONENAND_DDP_SHIFT_2Gb (22) ++#define ONENAND_DDP_SHIFT_4Gb (23) ++#define ONENAND_FBA_SHIFT (12) ++#define ONENAND_FPA_SHIFT (6) ++#define ONENAND_FSA_SHIFT (4) ++#define ONENAND_FBA_MASK_128Mb (0xff) ++#define ONENAND_FBA_MASK_256Mb (0x1ff) ++#define ONENAND_FBA_MASK_512Mb (0x1ff) ++#define ONENAND_FBA_MASK_1Gb_DDP (0x1ff) ++#define ONENAND_FBA_MASK_1Gb (0x3ff) ++#define ONENAND_FBA_MASK_2Gb_DDP (0x3ff) ++#define ONENAND_FBA_MASK_2Gb (0x7ff) ++#define ONENAND_FBA_MASK_4Gb_DDP (0x7ff) ++#define ONENAND_FBA_MASK_4Gb (0xfff) ++#define ONENAND_FPA_MASK (0x3f) ++#define ONENAND_FSA_MASK (0x3) ++ ++#elif defined(CONFIG_CPU_S5PC100) ++#define ONENAND_CMD_SHIFT (26) ++#define ONENAND_MEM_ADDR_MASK (0xffffff) ++#define ONENAND_DDP_SHIFT_1Gb (22) ++#define ONENAND_DDP_SHIFT_2Gb (23) ++#define ONENAND_DDP_SHIFT_4Gb (24) ++#define ONENAND_FBA_SHIFT (13) ++#define ONENAND_FPA_SHIFT (7) ++#define ONENAND_FSA_SHIFT (5) ++#define ONENAND_FBA_MASK_128Mb (0xff) ++#define ONENAND_FBA_MASK_256Mb (0x1ff) ++#define ONENAND_FBA_MASK_512Mb (0x1ff) ++#define ONENAND_FBA_MASK_1Gb_DDP (0x1ff) ++#define ONENAND_FBA_MASK_1Gb (0x3ff) ++#define ONENAND_FBA_MASK_2Gb_DDP (0x3ff) ++#define ONENAND_FBA_MASK_2Gb (0x7ff) ++#define ONENAND_FBA_MASK_4Gb_DDP (0x7ff) ++#define ONENAND_FBA_MASK_4Gb (0xfff) ++#define ONENAND_FPA_MASK (0x3f) ++#define ONENAND_FSA_MASK (0x3) ++ ++#else ++ ++/* ++ * Start Address 8 F107h (R/W) ++ */ ++#define ONENAND_FPA_MASK (0x3f) ++#define ONENAND_FPA_SHIFT (2) ++#define ONENAND_FSA_MASK (0x03) ++ ++#endif ++ ++/* ++ * System Configuration 1 Register F221h (R, R/W) ++ */ ++#define ONENAND_SYS_CFG1_SYNC_READ (1 << 15) ++#define ONENAND_SYS_CFG1_BRL_7 (7 << 12) ++#define ONENAND_SYS_CFG1_BRL_6 (6 << 12) ++#define ONENAND_SYS_CFG1_BRL_5 (5 << 12) ++#define ONENAND_SYS_CFG1_BRL_4 (4 << 12) ++#define ONENAND_SYS_CFG1_BRL_3 (3 << 12) ++#define ONENAND_SYS_CFG1_BRL_10 (2 << 12) ++#define ONENAND_SYS_CFG1_BRL_9 (1 << 12) ++#define ONENAND_SYS_CFG1_BRL_8 (0 << 12) ++#define ONENAND_SYS_CFG1_BRL_SHIFT (12) ++#define ONENAND_SYS_CFG1_BL_32 (4 << 9) ++#define ONENAND_SYS_CFG1_BL_16 (3 << 9) ++#define ONENAND_SYS_CFG1_BL_8 (2 << 9) ++#define ONENAND_SYS_CFG1_BL_4 (1 << 9) ++#define ONENAND_SYS_CFG1_BL_CONT (0 << 9) ++#define ONENAND_SYS_CFG1_BL_SHIFT (9) ++#define ONENAND_SYS_CFG1_NO_ECC (1 << 8) ++#define ONENAND_SYS_CFG1_RDY (1 << 7) ++#define ONENAND_SYS_CFG1_INT (1 << 6) ++#define ONENAND_SYS_CFG1_IOBE (1 << 5) ++#define ONENAND_SYS_CFG1_RDY_CONF (1 << 4) ++ ++/* ++ * Controller Status Register F240h (R) ++ */ ++#define ONENAND_CTRL_ONGO (1 << 15) ++#define ONENAND_CTRL_LOCK (1 << 14) ++#define ONENAND_CTRL_LOAD (1 << 13) ++#define ONENAND_CTRL_PROGRAM (1 << 12) ++#define ONENAND_CTRL_ERASE (1 << 11) ++#define ONENAND_CTRL_ERROR (1 << 10) ++#define ONENAND_CTRL_RSTB (1 << 7) ++#define ONENAND_CTRL_OTP_L (1 << 6) ++#define ONENAND_CTRL_OTP_BL (1 << 5) ++ ++/* ++ * Interrupt Status Register F241h (R) ++ */ ++#define ONENAND_INT_MASTER (1 << 15) ++#define ONENAND_INT_READ (1 << 7) ++#define ONENAND_INT_WRITE (1 << 6) ++#define ONENAND_INT_ERASE (1 << 5) ++#define ONENAND_INT_RESET (1 << 4) ++#define ONENAND_INT_CLEAR (0 << 0) ++ ++/* ++ * NAND Flash Write Protection Status Register F24Eh (R) ++ */ ++#define ONENAND_WP_US (1 << 2) ++#define ONENAND_WP_LS (1 << 1) ++#define ONENAND_WP_LTS (1 << 0) ++ ++/* ++ * ECC Status Register FF00h (R) ++ */ ++#define ONENAND_ECC_1BIT (1 << 0) ++#define ONENAND_ECC_1BIT_ALL (0x5555) ++#define ONENAND_ECC_2BIT (1 << 1) ++#define ONENAND_ECC_2BIT_ALL (0xAAAA) ++ ++/* ++ * One-Time Programmable (OTP) ++ */ ++#define ONENAND_OTP_LOCK_OFFSET (14) ++ ++#endif /* __ASM_ARCH_REGS_ONENAND_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-otg.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-otg.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-otg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-otg.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,255 @@ ++/* linux/arch/arm/plat-s3c/include/plat/regs-otg.h ++ * ++ * Copyright (C) 2004 Herbert Poetzl ++ * ++ * This include file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++*/ ++ ++#ifndef __ASM_ARCH_REGS_USB_OTG_HS_H ++#define __ASM_ARCH_REGS_USB_OTG_HS_H ++ ++/* USB2.0 OTG Controller register */ ++#define S3C_USBOTG_PHYREG(x) ((x) + S3C_VA_OTGSFR) ++#define S3C_USBOTG_PHYPWR S3C_USBOTG_PHYREG(0x0) ++#define S3C_USBOTG_PHYCLK S3C_USBOTG_PHYREG(0x4) ++#define S3C_USBOTG_RSTCON S3C_USBOTG_PHYREG(0x8) ++ ++ ++/* USB2.0 OTG Controller register */ ++#define S3C_USBOTGREG(x) ((x) + S3C_VA_OTG) ++/*============================================================================================== */ ++ /* Core Global Registers */ ++#define S3C_UDC_OTG_GOTGCTL S3C_USBOTGREG(0x000) /* OTG Control & Status */ ++#define S3C_UDC_OTG_GOTGINT S3C_USBOTGREG(0x004) /* OTG Interrupt */ ++#define S3C_UDC_OTG_GAHBCFG S3C_USBOTGREG(0x008) /* Core AHB Configuration */ ++#define S3C_UDC_OTG_GUSBCFG S3C_USBOTGREG(0x00C) /* Core USB Configuration */ ++#define S3C_UDC_OTG_GRSTCTL S3C_USBOTGREG(0x010) /* Core Reset */ ++#define S3C_UDC_OTG_GINTSTS S3C_USBOTGREG(0x014) /* Core Interrupt */ ++#define S3C_UDC_OTG_GINTMSK S3C_USBOTGREG(0x018) /* Core Interrupt Mask */ ++#define S3C_UDC_OTG_GRXSTSR S3C_USBOTGREG(0x01C) /* Receive Status Debug Read/Status Read */ ++#define S3C_UDC_OTG_GRXSTSP S3C_USBOTGREG(0x020) /* Receive Status Debug Pop/Status Pop */ ++#define S3C_UDC_OTG_GRXFSIZ S3C_USBOTGREG(0x024) /* Receive FIFO Size */ ++#define S3C_UDC_OTG_GNPTXFSIZ S3C_USBOTGREG(0x028) /* Non-Periodic Transmit FIFO Size */ ++#define S3C_UDC_OTG_GNPTXSTS S3C_USBOTGREG(0x02C) /* Non-Periodic Transmit FIFO/Queue Status */ ++ ++#define S3C_UDC_OTG_HPTXFSIZ S3C_USBOTGREG(0x100) /* Host Periodic Transmit FIFO Size */ ++#define S3C_UDC_OTG_DIEPTXF(n) S3C_USBOTGREG(0x104 + (n-1)*0x4)/* Device IN EP Transmit FIFO Size Register */ ++ ++/*============================================================================================== */ ++/* Host Mode Registers */ ++/*------------------------------------------------ */ ++/* Host Global Registers */ ++#define S3C_UDC_OTG_HCFG S3C_USBOTGREG(0x400) /* Host Configuration */ ++#define S3C_UDC_OTG_HFIR S3C_USBOTGREG(0x404) /* Host Frame Interval */ ++#define S3C_UDC_OTG_HFNUM S3C_USBOTGREG(0x408) /* Host Frame Number/Frame Time Remaining */ ++#define S3C_UDC_OTG_HPTXSTS S3C_USBOTGREG(0x410) /* Host Periodic Transmit FIFO/Queue Status */ ++#define S3C_UDC_OTG_HAINT S3C_USBOTGREG(0x414) /* Host All Channels Interrupt */ ++#define S3C_UDC_OTG_HAINTMSK S3C_USBOTGREG(0x418) /* Host All Channels Interrupt Mask */ ++ ++/*------------------------------------------------ */ ++/* Host Port Control & Status Registers */ ++#define S3C_UDC_OTG_HPRT S3C_USBOTGREG(0x440) /* Host Port Control & Status */ ++ ++/*------------------------------------------------ */ ++/* Host Channel-Specific Registers */ ++#define S3C_UDC_OTG_HCCHAR0 S3C_USBOTGREG(0x500) /* Host Channel-0 Characteristics */ ++#define S3C_UDC_OTG_HCSPLT0 S3C_USBOTGREG(0x504) /* Host Channel-0 Split Control */ ++#define S3C_UDC_OTG_HCINT0 S3C_USBOTGREG(0x508) /* Host Channel-0 Interrupt */ ++#define S3C_UDC_OTG_HCINTMSK0 S3C_USBOTGREG(0x50C) /* Host Channel-0 Interrupt Mask */ ++#define S3C_UDC_OTG_HCTSIZ0 S3C_USBOTGREG(0x510) /* Host Channel-0 Transfer Size */ ++#define S3C_UDC_OTG_HCDMA0 S3C_USBOTGREG(0x514) /* Host Channel-0 DMA Address */ ++ ++ ++/*============================================================================================== */ ++/* Device Mode Registers */ ++/*------------------------------------------------ */ ++/* Device Global Registers */ ++#define S3C_UDC_OTG_DCFG S3C_USBOTGREG(0x800) /* Device Configuration */ ++#define S3C_UDC_OTG_DCTL S3C_USBOTGREG(0x804) /* Device Control */ ++#define S3C_UDC_OTG_DSTS S3C_USBOTGREG(0x808) /* Device Status */ ++#define S3C_UDC_OTG_DIEPMSK S3C_USBOTGREG(0x810) /* Device IN Endpoint Common Interrupt Mask */ ++#define S3C_UDC_OTG_DOEPMSK S3C_USBOTGREG(0x814) /* Device OUT Endpoint Common Interrupt Mask */ ++#define S3C_UDC_OTG_DAINT S3C_USBOTGREG(0x818) /* Device All Endpoints Interrupt */ ++#define S3C_UDC_OTG_DAINTMSK S3C_USBOTGREG(0x81C) /* Device All Endpoints Interrupt Mask */ ++#define S3C_UDC_OTG_DTKNQR1 S3C_USBOTGREG(0x820) /* Device IN Token Sequence Learning Queue Read 1 */ ++#define S3C_UDC_OTG_DTKNQR2 S3C_USBOTGREG(0x824) /* Device IN Token Sequence Learning Queue Read 2 */ ++#define S3C_UDC_OTG_DVBUSDIS S3C_USBOTGREG(0x828) /* Device VBUS Discharge Time */ ++#define S3C_UDC_OTG_DVBUSPULSE S3C_USBOTGREG(0x82C) /* Device VBUS Pulsing Time */ ++#define S3C_UDC_OTG_DTKNQR3 S3C_USBOTGREG(0x830) /* Device IN Token Sequence Learning Queue Read 3 */ ++#define S3C_UDC_OTG_DTKNQR4 S3C_USBOTGREG(0x834) /* Device IN Token Sequence Learning Queue Read 4 */ ++ ++/*------------------------------------------------ */ ++/* Device Logical IN Endpoint-Specific Registers */ ++#define S3C_UDC_OTG_DIEPCTL(n) S3C_USBOTGREG(0x900 + n*0x20) /* Device IN Endpoint n Control */ ++#define S3C_UDC_OTG_DIEPINT(n) S3C_USBOTGREG(0x908 + n*0x20) /* Device IN Endpoint n Interrupt */ ++#define S3C_UDC_OTG_DIEPTSIZ(n) S3C_USBOTGREG(0x910 + n*0x20) /* Device IN Endpoint n Transfer Size */ ++#define S3C_UDC_OTG_DIEPDMA(n) S3C_USBOTGREG(0x914 + n*0x20) /* Device IN Endpoint n DMA Address */ ++ ++/*------------------------------------------------ */ ++/* Device Logical OUT Endpoint-Specific Registers */ ++#define S3C_UDC_OTG_DOEPCTL(n) S3C_USBOTGREG(0xB00 + n*0x20) /* Device OUT Endpoint n Control */ ++#define S3C_UDC_OTG_DOEPINT(n) S3C_USBOTGREG(0xB08 + n*0x20) /* Device OUT Endpoint n Interrupt */ ++#define S3C_UDC_OTG_DOEPTSIZ(n) S3C_USBOTGREG(0xB10 + n*0x20) /* Device OUT Endpoint n Transfer Size */ ++#define S3C_UDC_OTG_DOEPDMA(n) S3C_USBOTGREG(0xB14 + n*0x20) /* Device OUT Endpoint n DMA Address */ ++ ++/*------------------------------------------------ */ ++/* Endpoint FIFO address */ ++#define S3C_UDC_OTG_EP0_FIFO S3C_USBOTGREG(0x1000) ++#define S3C_UDC_OTG_EP1_FIFO S3C_USBOTGREG(0x2000) ++#define S3C_UDC_OTG_EP2_FIFO S3C_USBOTGREG(0x3000) ++#define S3C_UDC_OTG_EP3_FIFO S3C_USBOTGREG(0x4000) ++#define S3C_UDC_OTG_EP4_FIFO S3C_USBOTGREG(0x5000) ++#define S3C_UDC_OTG_EP5_FIFO S3C_USBOTGREG(0x6000) ++#define S3C_UDC_OTG_EP6_FIFO S3C_USBOTGREG(0x7000) ++#define S3C_UDC_OTG_EP7_FIFO S3C_USBOTGREG(0x8000) ++#define S3C_UDC_OTG_EP8_FIFO S3C_USBOTGREG(0x9000) ++ ++/*===================================================================== */ ++/*definitions related to CSR setting */ ++ ++/* S3C_UDC_OTG_GOTGCTL */ ++#define B_SESSION_VALID (0x1<<19) ++#define A_SESSION_VALID (0x1<<18) ++ ++/* S3C_UDC_OTG_GAHBCFG */ ++#define PTXFE_HALF (0<<8) ++#define PTXFE_ZERO (1<<8) ++#define NPTXFE_HALF (0<<7) ++#define NPTXFE_ZERO (1<<7) ++#define MODE_SLAVE (0<<5) ++#define MODE_DMA (1<<5) ++#define BURST_SINGLE (0<<1) ++#define BURST_INCR (1<<1) ++#define BURST_INCR4 (3<<1) ++#define BURST_INCR8 (5<<1) ++#define BURST_INCR16 (7<<1) ++#define GBL_INT_UNMASK (1<<0) ++#define GBL_INT_MASK (0<<0) ++ ++/* S3C_UDC_OTG_GRSTCTL */ ++#define AHB_MASTER_IDLE (1u<<31) ++#define CORE_SOFT_RESET (0x1<<0) ++ ++/* S3C_UDC_OTG_GINTSTS/S3C_UDC_OTG_GINTMSK core interrupt register */ ++#define INT_RESUME (1u<<31) ++#define INT_DISCONN (0x1<<29) ++#define INT_CONN_ID_STS_CNG (0x1<<28) ++#define INT_OUT_EP (0x1<<19) ++#define INT_IN_EP (0x1<<18) ++#define INT_ENUMDONE (0x1<<13) ++#define INT_RESET (0x1<<12) ++#define INT_SUSPEND (0x1<<11) ++#define INT_EARLY_SUSPEND (0x1<<10) ++#define INT_NP_TX_FIFO_EMPTY (0x1<<5) ++#define INT_RX_FIFO_NOT_EMPTY (0x1<<4) ++#define INT_SOF (0x1<<3) ++#define INT_DEV_MODE (0x0<<0) ++#define INT_HOST_MODE (0x1<<1) ++#define INT_GOUTNakEff (0x01<<7) ++#define INT_GINNakEff (0x01<<6) ++ ++#define FULL_SPEED_CONTROL_PKT_SIZE 8 ++#define FULL_SPEED_BULK_PKT_SIZE 64 ++ ++#define HIGH_SPEED_CONTROL_PKT_SIZE 64 ++#define HIGH_SPEED_BULK_PKT_SIZE 512 ++ ++#ifndef CONFIG_PLAT_S5P64XX ++#define RX_FIFO_SIZE 2048 ++#define NPTX_FIFO_START_ADDR RX_FIFO_SIZE ++#define NPTX_FIFO_SIZE 2048 ++#define PTX_FIFO_SIZE 2048 ++#else ++#define RX_FIFO_SIZE 1024 ++#define NPTX_FIFO_START_ADDR RX_FIFO_SIZE ++#define NPTX_FIFO_SIZE 256 ++#define PTX_FIFO_SIZE 256 ++#endif ++ ++#define DEPCTL_TXFNUM_0 (0x0<<22) ++#define DEPCTL_TXFNUM_1 (0x1<<22) ++#define DEPCTL_TXFNUM_2 (0x2<<22) ++#define DEPCTL_TXFNUM_3 (0x3<<22) ++#define DEPCTL_TXFNUM_4 (0x4<<22) ++ ++ ++/* Enumeration speed */ ++#define USB_HIGH_30_60MHZ (0x0<<1) ++#define USB_FULL_30_60MHZ (0x1<<1) ++#define USB_LOW_6MHZ (0x2<<1) ++#define USB_FULL_48MHZ (0x3<<1) ++ ++/* S3C_UDC_OTG_GRXSTSP STATUS */ ++#define OUT_PKT_RECEIVED (0x2<<17) ++#define OUT_TRANSFER_COMPLELTED (0x3<<17) ++#define SETUP_TRANSACTION_COMPLETED (0x4<<17) ++#define SETUP_PKT_RECEIVED (0x6<<17) ++#define GLOBAL_OUT_NAK (0x1<<17) ++ ++ ++/* S3C_UDC_OTG_DCTL device control register */ ++#define NORMAL_OPERATION (0x1<<0) ++#define SOFT_DISCONNECT (0x1<<1) ++ ++/* S3C_UDC_OTG_DAINT device all endpoint interrupt register */ ++#define DAINT_OUT_BIT (16) ++#define DAINT_MASK (0xFFFF) ++ ++ ++ ++/* S3C_UDC_OTG_DIEPCTL0/DOEPCTL0 device control IN/OUT endpoint 0 control register */ ++#define DEPCTL_EPENA (0x1<<31) ++#define DEPCTL_EPDIS (0x1<<30) ++#define DEPCTL_SETD1PID (0x1<<29) ++#define DEPCTL_SETD0PID (0x1<<28) ++#define DEPCTL_SNAK (0x1<<27) ++#define DEPCTL_CNAK (0x1<<26) ++#define DEPCTL_STALL (0x1<<21) ++#define DEPCTL_TYPE_BIT (18) ++#define DEPCTL_TYPE_MASK (0x3<<18) ++#define DEPCTL_CTRL_TYPE (0x0<<18) ++#define DEPCTL_ISO_TYPE (0x1<<18) ++#define DEPCTL_BULK_TYPE (0x2<<18) ++#define DEPCTL_INTR_TYPE (0x3<<18) ++#define DEPCTL_USBACTEP (0x1<<15) ++#define DEPCTL_NEXT_EP_BIT (11) ++#define DEPCTL_MPS_BIT (0) ++#define DEPCTL_MPS_MASK (0x7FF) ++ ++#define DEPCTL0_MPS_64 (0x0<<0) ++#define DEPCTL0_MPS_32 (0x1<<0) ++#define DEPCTL0_MPS_16 (0x2<<0) ++#define DEPCTL0_MPS_8 (0x3<<0) ++#define DEPCTL_MPS_BULK_512 (512<<0) ++#define DEPCTL_MPS_INT_MPS_16 (16<<0) ++ ++#define DIEPCTL0_NEXT_EP_BIT (11) ++ ++/* S3C_UDC_OTG_DIEPCTLn/DOEPCTLn device control IN/OUT endpoint n control register */ ++ ++/* S3C_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint common interrupt mask register */ ++/* S3C_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */ ++#define BACK2BACK_SETUP_RECEIVED (0x1<<6) ++#define INTKNEPMIS (0x1<<5) ++#define INTKN_TXFEMP (0x1<<4) ++#define NON_ISO_IN_EP_TIMEOUT (0x1<<3) ++#define CTRL_OUT_EP_SETUP_PHASE_DONE (0x1<<3) ++#define AHB_ERROR (0x1<<2) ++#define EPDISBLD (0x1<<1) ++#define TRANSFER_DONE (0x1<<0) ++ ++/*DIEPTSIZ0 / DOEPTSIZ0 */ ++ ++/* DEPTSIZ common bit */ ++#define DEPTSIZ_PKT_CNT_BIT (19) ++#define DEPTSIZ_XFER_SIZE_BIT (0) ++ ++#define DEPTSIZ_SETUP_PKCNT_1 (1<<29) ++#define DEPTSIZ_SETUP_PKCNT_2 (2<<29) ++#define DEPTSIZ_SETUP_PKCNT_3 (3<<29) ++ ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-pp.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-pp.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-pp.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-pp.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,80 @@ ++/* linux/include/asm-arm/arch-s3c2410/regs-hsmmc.h ++ * ++ * Copyright (c) 2004 Samsung Electronics ++ * http://www.samsung.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C HSMMC Controller ++*/ ++ ++#ifndef __ASM_ARCH_REGS_PP_H ++#define __ASM_ARCH_REGS_PP_H __FILE__ ++ ++#define S3C_VPP(x) ((x)) ++ ++#define S3C_VPP_MODE S3C_VPP(0x00) ++#define S3C_VPP_PRESCALE_RATIO S3C_VPP(0x04) ++#define S3C_VPP_PRESCALEIMGSIZE S3C_VPP(0x08) ++#define S3C_VPP_SRCIMGSIZE S3C_VPP(0x0C) ++#define S3C_VPP_MAINSCALE_H_RATIO S3C_VPP(0x10) ++#define S3C_VPP_MAINSCALE_V_RATIO S3C_VPP(0x14) ++#define S3C_VPP_DSTIMGSIZE S3C_VPP(0x18) ++#define S3C_VPP_PRESCALE_SHFACTOR S3C_VPP(0x1C) ++#define S3C_VPP_ADDRSTART_Y S3C_VPP(0x20) ++#define S3C_VPP_ADDRSTART_CB S3C_VPP(0x24) ++#define S3C_VPP_ADDRSTART_CR S3C_VPP(0x28) ++#define S3C_VPP_ADDRSTART_RGB S3C_VPP(0x2C) ++#define S3C_VPP_ADDREND_Y S3C_VPP(0x30) ++#define S3C_VPP_ADDREND_CB S3C_VPP(0x34) ++#define S3C_VPP_ADDREND_CR S3C_VPP(0x38) ++#define S3C_VPP_ADDREND_RGB S3C_VPP(0x3C) ++#define S3C_VPP_OFFSET_Y S3C_VPP(0x40) ++#define S3C_VPP_OFFSET_CB S3C_VPP(0x44) ++#define S3C_VPP_OFFSET_CR S3C_VPP(0x48) ++#define S3C_VPP_OFFSET_RGB S3C_VPP(0x4C) ++#define S3C_VPP_NXTADDRSTART_Y S3C_VPP(0x54) ++#define S3C_VPP_NXTADDRSTART_CB S3C_VPP(0x58) ++#define S3C_VPP_NXTADDRSTART_CR S3C_VPP(0x5C) ++#define S3C_VPP_NXTADDRSTART_RGB S3C_VPP(0x60) ++#define S3C_VPP_NXTADDREND_Y S3C_VPP(0x64) ++#define S3C_VPP_NXTADDREND_CB S3C_VPP(0x68) ++#define S3C_VPP_NXTADDREND_CR S3C_VPP(0x6C) ++#define S3C_VPP_NXTADDREND_RGB S3C_VPP(0x70) ++#define S3C_VPP_ADDRSTART_OCB S3C_VPP(0x74) ++#define S3C_VPP_ADDRSTART_OCR S3C_VPP(0x78) ++#define S3C_VPP_ADDREND_OCB S3C_VPP(0x7C) ++#define S3C_VPP_ADDREND_OCR S3C_VPP(0x80) ++#define S3C_VPP_OFFSET_OCB S3C_VPP(0x84) ++#define S3C_VPP_OFFSET_OCR S3C_VPP(0x88) ++#define S3C_VPP_NXTADDRSTART_OCB S3C_VPP(0x8C) ++#define S3C_VPP_NXTADDRSTART_OCR S3C_VPP(0x90) ++#define S3C_VPP_NXTADDREND_OCB S3C_VPP(0x94) ++#define S3C_VPP_NXTADDREND_OCR S3C_VPP(0x98) ++#define S3C_VPP_POSTENVID S3C_VPP(0x9C) ++#define S3C_VPP_MODE_2 S3C_VPP(0xA0) ++ ++//POSTENVID ++#define S3C_POSTENVID_ENABLE (0x1<<31) // khlee ++#define S3C_POSTENVID_DISABLE (0x0<<31) ++ ++//MODE Control register ++#define S3C_MODE_AUTOLOAD_ENABLE (0x1<<14) ++#define S3C_MODE_POST_INT_ENABLE (0x1<<7) ++#define S3C_MODE_POST_PENDING (0x1<<6) ++#define S3C_MODE_IRQ_LEVEL (0x1<<5) ++#define S3C_MODE_H_CLK_INPUT (0x0<<2) ++#define S3C_MODE_EXT_CLK_0_INPUT (0x1<<2) ++#define S3C_MODE_EXT_CLK_1_INPUT (0x3<<2) ++ ++//MODE Control register 2 ++#define S3C_MODE2_ADDR_CHANGE_ENABLE (0x0<<4) ++#define S3C_MODE2_ADDR_CHANGE_DISABLE (0x1<<4) ++#define S3C_MODE2_CHANGE_AT_FIELD_END (0x0<<3) ++#define S3C_MODE2_CHANGE_AT_FRAME_END (0x1<<3) ++#define S3C_MODE2_SOFTWARE_TRIGGER (0x0<<0) ++#define S3C_MODE2_HARDWARE_TRIGGER (0x1<<0) ++ ++#endif /* __ASM_ARCH_REGS_HSMMC_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-rotator.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-rotator.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-rotator.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-rotator.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,68 @@ ++/* linux/include/asm-arm/arch-s3c2410/regs-roator.h ++ * ++ * Copyright (c) 2004 Samsung Electronics ++ * http://www.samsung.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C Rotator Controller ++*/ ++ ++#ifndef __ASM_ARCH_REGS_ROTATOR_H ++#define __ASM_ARCH_REGS_ROTATOR_H __FILE__ ++ ++ ++/************************************************************************* ++ * Macro part ++ ************************************************************************/ ++#define S3C_ROT_SRC_WIDTH(x) ((x) << 0) ++#define S3C_ROT_SRC_HEIGHT(x) ((x) << 16) ++ ++ ++/************************************************************************* ++ * Bit definition part ++ ************************************************************************/ ++#define S3C_ROTATOR_IDLE (0 << 0) ++#define S3C_ROTATOR_CTRLREG_MASK (0xE0F0) ++ ++#define S3C_ROTATOR_CTRLCFG_ENABLE_INT (1 << 24) ++ ++#define S3C_ROTATOR_CTRLCFG_INPUT_YUV420 (0 << 13) ++#define S3C_ROTATOR_CTRLCFG_INPUT_YUV422 (3 << 13) ++#define S3C_ROTATOR_CTRLCFG_INPUT_RGB565 (4 << 13) ++#define S3C_ROTATOR_CTRLCFG_INPUT_RGB888 (5 << 13) ++ ++#define S3C_ROTATOR_CTRLCFG_DEGREE_BYPASS (0 << 6) ++#define S3C_ROTATOR_CTRLCFG_DEGREE_90 (1 << 6) ++#define S3C_ROTATOR_CTRLCFG_DEGREE_180 (2 << 6) ++#define S3C_ROTATOR_CTRLCFG_DEGREE_270 (3 << 6) ++ ++#define S3C_ROTATOR_CTRLCFG_FLIP_BYPASS (0 << 4) ++#define S3C_ROTATOR_CTRLCFG_FLIP_VER (2 << 4) ++#define S3C_ROTATOR_CTRLCFG_FLIP_HOR (3 << 4) ++ ++#define S3C_ROTATOR_STATCFG_STATUS_IDLE (0 << 0) ++#define S3C_ROTATOR_CTRLCFG_START_ROTATE (1 << 0) ++#define S3C_ROTATOR_STATCFG_STATUS_BUSY (2 << 0) ++#define S3C_ROTATOR_STATCFG_STATUS_BUSY_MORE (3 << 0) ++#define S3C_ROTATOR_STATCFG_INT_PEND (1 << 8) ++ ++ ++/************************************************************************* ++ * Register part ++ ************************************************************************/ ++#define S3C_ROTATOR(x) ((x)) ++#define S3C_ROTATOR_CTRLCFG S3C_ROTATOR(0x0) ++#define S3C_ROTATOR_SRCADDRREG0 S3C_ROTATOR(0x4) ++#define S3C_ROTATOR_SRCADDRREG1 S3C_ROTATOR(0x8) ++#define S3C_ROTATOR_SRCADDRREG2 S3C_ROTATOR(0xC) ++#define S3C_ROTATOR_SRCSIZEREG S3C_ROTATOR(0x10) ++#define S3C_ROTATOR_DESTADDRREG0 S3C_ROTATOR(0x18) ++#define S3C_ROTATOR_DESTADDRREG1 S3C_ROTATOR(0x1C) ++#define S3C_ROTATOR_DESTADDRREG2 S3C_ROTATOR(0x20) ++#define S3C_ROTATOR_STATCFG S3C_ROTATOR(0x2C) ++ ++#endif /* __ASM_ARCH_REGS_ROTATOR_H */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-rtc.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-rtc.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-rtc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-rtc.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,83 @@ ++/* linux/arch/arm/plat-s3c/include/plat/regs-rtc.h ++ * ++ * Copyright (c) 2003 Simtec Electronics ++ * http://www.simtec.co.uk/products/SWLINUX/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C2410 Internal RTC register definition ++*/ ++ ++#ifndef __ASM_ARCH_REGS_RTC_H ++#define __ASM_ARCH_REGS_RTC_H __FILE__ ++ ++#define S3C2410_RTCREG(x) (x) ++ ++#define S3C2410_INTP S3C2410_RTCREG(0x30) ++#define S3C2410_INTP_ALM (1<<1) ++#define S3C2410_INTP_TIC (1<<0) ++ ++#define S3C2410_RTCCON S3C2410_RTCREG(0x40) ++#define S3C2410_RTCCON_RTCEN (1<<0) ++#define S3C2410_RTCCON_CLKSEL (1<<1) ++#define S3C2410_RTCCON_CNTSEL (1<<2) ++#define S3C2410_RTCCON_CLKRST (1<<3) ++ ++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || defined (CONFIG_CPU_S5PC100) || defined (CONFIG_CPU_S5P6440) ++#define S3C_MAX_CNT 32768 ++#define S3C_RTCCON_TICEN (1<<8) ++#define S3C_RTC_TICNT S3C2410_RTCREG(0x40) ++#else ++#define S3C_INTP_ALM (1<<1) ++#define S3C_MAX_CNT 128 ++#define S3C_RTCCON_TICEN (1<<7) ++#define S3C_RTC_TICNT S3C2410_RTCREG(0x44) ++#endif ++ ++/* Common Reg for samsung AP*/ ++#define S3C_INTP S3C2410_RTCREG(0x30) ++#define S3C_INTP_ALM (1<<1) ++#define S3C_INTP_TIC (1<<0) ++ ++ ++#define S3C2410_TICNT S3C2410_RTCREG(0x44) ++#define S3C2410_TICNT_ENABLE (1<<7) ++#define S3C64XX_TICNT_ENABLE (1<<8) ++ ++#define S3C2410_RTCALM S3C2410_RTCREG(0x50) ++#define S3C2410_RTCALM_ALMEN (1<<6) ++#define S3C2410_RTCALM_YEAREN (1<<5) ++#define S3C2410_RTCALM_MONEN (1<<4) ++#define S3C2410_RTCALM_DAYEN (1<<3) ++#define S3C2410_RTCALM_HOUREN (1<<2) ++#define S3C2410_RTCALM_MINEN (1<<1) ++#define S3C2410_RTCALM_SECEN (1<<0) ++ ++#define S3C2410_RTCALM_ALL \ ++ S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\ ++ S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\ ++ S3C2410_RTCALM_SECEN ++ ++ ++#define S3C2410_ALMSEC S3C2410_RTCREG(0x54) ++#define S3C2410_ALMMIN S3C2410_RTCREG(0x58) ++#define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c) ++ ++#define S3C2410_ALMDATE S3C2410_RTCREG(0x60) ++#define S3C2410_ALMMON S3C2410_RTCREG(0x64) ++#define S3C2410_ALMYEAR S3C2410_RTCREG(0x68) ++ ++#define S3C2410_RTCRST S3C2410_RTCREG(0x6c) ++ ++#define S3C2410_RTCSEC S3C2410_RTCREG(0x70) ++#define S3C2410_RTCMIN S3C2410_RTCREG(0x74) ++#define S3C2410_RTCHOUR S3C2410_RTCREG(0x78) ++#define S3C2410_RTCDATE S3C2410_RTCREG(0x7c) ++#define S3C2410_RTCDAY S3C2410_RTCREG(0x80) ++#define S3C2410_RTCMON S3C2410_RTCREG(0x84) ++#define S3C2410_RTCYEAR S3C2410_RTCREG(0x88) ++ ++ ++#endif /* __ASM_ARCH_REGS_RTC_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-sdhci.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-sdhci.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-sdhci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-sdhci.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,87 @@ ++/* linux/arch/arm/plat-s3c/include/plat/regs-sdhci.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S3C Platform - SDHCI (HSMMC) register definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __PLAT_S3C_SDHCI_REGS_H ++#define __PLAT_S3C_SDHCI_REGS_H __FILE__ ++ ++#define S3C_SDHCI_CONTROL2 (0x80) ++#define S3C_SDHCI_CONTROL3 (0x84) ++#define S3C64XX_SDHCI_CONTROL4 (0x8C) ++ ++#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31) ++#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK (1 << 30) ++#define S3C_SDHCI_CTRL2_CDINVRXD3 (1 << 29) ++#define S3C_SDHCI_CTRL2_SLCARDOUT (1 << 28) ++ ++#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24) ++#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24) ++#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24) ++ ++#define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16) ++#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16) ++#define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16) ++ ++#define S3C_SDHCI_CTRL2_ENFBCLKTX (1 << 15) ++#define S3C_SDHCI_CTRL2_ENFBCLKRX (1 << 14) ++#define S3C_SDHCI_CTRL2_SDCDSEL (1 << 13) ++#define S3C_SDHCI_CTRL2_SDSIGPC (1 << 12) ++#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11) ++ ++#define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9) ++#define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9) ++#define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9) ++#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9) ++#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9) ++#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9) ++ ++#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8) ++#define S3C_SDHCI_CTRL2_RWAITMODE (1 << 7) ++#define S3C_SDHCI_CTRL2_DISBUFRD (1 << 6) ++#define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4) ++#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4) ++#define S3C_SDHCI_CTRL2_PWRSYNC (1 << 3) ++#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1) ++#define S3C_SDHCI_CTRL2_HWINITFIN (1 << 0) ++ ++#define S3C_SDHCI_CTRL3_FCSEL3 (1 << 31) ++#define S3C_SDHCI_CTRL3_FCSEL2 (1 << 23) ++#define S3C_SDHCI_CTRL3_FCSEL1 (1 << 15) ++#define S3C_SDHCI_CTRL3_FCSEL0 (1 << 7) ++ ++#define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24) ++#define S3C_SDHCI_CTRL3_FIA3_SHIFT (24) ++#define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24) ++ ++#define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16) ++#define S3C_SDHCI_CTRL3_FIA2_SHIFT (16) ++#define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16) ++ ++#define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8) ++#define S3C_SDHCI_CTRL3_FIA1_SHIFT (8) ++#define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8) ++ ++#define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0) ++#define S3C_SDHCI_CTRL3_FIA0_SHIFT (0) ++#define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0) ++ ++#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16) ++#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16) ++#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16) ++#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16) ++#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16) ++#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16) ++ ++#define S3C64XX_SDHCI_CONTROL4_BUSY (1) ++ ++#endif /* __PLAT_S3C_SDHCI_REGS_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-serial.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-serial.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-serial.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-serial.h 2009-04-30 09:36:37.000000000 +0200 +@@ -1,4 +1,4 @@ +-/* arch/arm/mach-s3c2410/include/mach/regs-serial.h ++/* linux/arch/arm/plat-s3c/include/plat/regs-serial.h + * + * From linux/include/asm-arm/hardware/serial_s3c2410.h + * +@@ -32,6 +32,17 @@ + #ifndef __ASM_ARM_REGS_SERIAL_H + #define __ASM_ARM_REGS_SERIAL_H + ++#if defined(CONFIG_PLAT_S3C64XX) || defined(CONFIG_PLAT_S5PC1XX) ++#define S3C24XX_VA_UART0 (S3C_VA_UART) ++#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x400) ++#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x800) ++#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC00) ++ ++#define S3C2410_PA_UART0 (S3C24XX_PA_UART) ++#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x400) ++#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x800) ++#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC00) ++#else + #define S3C24XX_VA_UART0 (S3C_VA_UART) + #define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 ) + #define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 ) +@@ -41,6 +52,7 @@ + #define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 ) + #define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 ) + #define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 ) ++#endif + + #define S3C2410_URXH (0x24) + #define S3C2410_UTXH (0x20) +@@ -48,11 +60,13 @@ + #define S3C2410_UCON (0x04) + #define S3C2410_UFCON (0x08) + #define S3C2410_UMCON (0x0C) +-#define S3C2410_UBRDIV (0x28) + #define S3C2410_UTRSTAT (0x10) + #define S3C2410_UERSTAT (0x14) + #define S3C2410_UFSTAT (0x18) + #define S3C2410_UMSTAT (0x1C) ++#define S3C2410_UBRDIV (0x28) ++#define S3C2410_UDIVSLOT (0x2C) ++#define S3C2410_UINTMSK (0x38) + + #define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3)) + +@@ -77,6 +91,12 @@ + #define S3C2440_UCON_FCLK (3<<10) + #define S3C2443_UCON_EPLL (3<<10) + ++#define S3C6400_UCON_CLKMASK (3<<10) ++#define S3C6400_UCON_PCLK (0<<10) ++#define S3C6400_UCON_PCLK2 (2<<10) ++#define S3C6400_UCON_UCLK0 (1<<10) ++#define S3C6400_UCON_UCLK1 (3<<10) ++ + #define S3C2440_UCON2_FCLK_EN (1<<15) + #define S3C2440_UCON0_DIVMASK (15 << 12) + #define S3C2440_UCON1_DIVMASK (15 << 12) +@@ -149,6 +169,14 @@ + #define S3C2410_UFSTAT_RXMASK (15<<0) + #define S3C2410_UFSTAT_RXSHIFT (0) + ++/* UFSTAT S3C24A0 */ ++#define S3C24A0_UFSTAT_TXFULL (1 << 14) ++#define S3C24A0_UFSTAT_RXFULL (1 << 6) ++#define S3C24A0_UFSTAT_TXMASK (63 << 8) ++#define S3C24A0_UFSTAT_TXSHIFT (8) ++#define S3C24A0_UFSTAT_RXMASK (63) ++#define S3C24A0_UFSTAT_RXSHIFT (0) ++ + /* UFSTAT S3C2443 same as S3C2440 */ + #define S3C2440_UFSTAT_TXFULL (1<<14) + #define S3C2440_UFSTAT_RXFULL (1<<6) +@@ -175,6 +203,135 @@ + + #define S3C2443_DIVSLOT (0x2C) + ++/* S3C64XX only */ ++#define S3C64XX_ULCON_WORD_5BIT (0 << 0) ++#define S3C64XX_ULCON_WORD_6BIT (1 << 0) ++#define S3C64XX_ULCON_WORD_7BIT (2 << 0) ++#define S3C64XX_ULCON_WORD_8BIT (3 << 0) ++ ++#define S3C64XX_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ ++ S3C2410_UCON_RXILEVEL | \ ++ S3C2410_UCON_TXIRQMODE | \ ++ S3C2410_UCON_RXIRQMODE | \ ++ S3C2410_UCON_RXFIFO_TOI | \ ++ S3C2443_UCON_RXERR_IRQEN) ++ ++#define S3C64XX_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ ++ S3C2440_UFCON_TXTRIG16 | \ ++ S3C2410_UFCON_RXTRIG8 ) ++ ++#define S3C64XX_ULCON_DEFAULT S3C64XX_ULCON_WORD_8BIT ++ ++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S5PC100) ++#define S3C_ULCON (0x00) ++#define S3C_UCON (0x04) ++#define S3C_UFCON (0x08) ++#define S3C_UMCON (0x0C) ++#define S3C_UTRSTAT (0x10) ++#define S3C_UERSTAT (0x14) ++#define S3C_UFSTAT (0x18) ++#define S3C_UMSTAT (0x1C) ++#define S3C_UTXH (0x20) ++#define S3C_URXH (0x24) ++#define S3C_UBRDIV (0x28) ++#define S3C_UDIVSLOT (0x2C) ++#define S3C_UINTPND (0x30) ++#define S3C_UINTSP (0x34) ++#define S3C_UINTMSK (0x38) ++ ++/* base definitions for UART Line Control Register */ ++#define S3C_LCON_CFGMASK (0x7f) ++ ++#define S3C_LCON_CS5 (0x0) ++#define S3C_LCON_CS6 (0x1) ++#define S3C_LCON_CS7 (0x2) ++#define S3C_LCON_CS8 (0x3) ++#define S3C_LCON_CSMASK (0x3) ++ ++#define S3C_LCON_PNONE (0x0) ++#define S3C_LCON_PEVEN (0x5 << 3) ++#define S3C_LCON_PODD (0x4 << 3) ++#define S3C_LCON_PMASK (0x7 << 3) ++ ++#define S3C_LCON_STOPB (1<<2) ++#define S3C_LCON_IRM (1<<6) ++ ++#define S3C_UCON_CLKMASK (3<<10) ++#define S3C_UCON_PCLK (0<<10) ++#define S3C_UCON_UCLK (1<<10) ++#define S3C_UCON_PCLK2 (2<<10) ++#define S3C_UCON_FCLK (3<<10) ++ ++#define S3C_UCON_TXILEVEL (1<<9) ++#define S3C_UCON_RXILEVEL (1<<8) ++#define S3C_UCON_TXIRQMODE (1<<2) ++#define S3C_UCON_RXIRQMODE (1<<0) ++#define S3C_UCON_RXFIFO_TOI (1<<7) ++#define S3C_UCON_RX_ESIE (1<<6) ++#define S3C_UCON_LOOP_OPERATION (0<<5) ++#define S3C_UCON_NO_SBS (0<<4) ++ ++ ++#define S3C_UCON_DEFAULT (S3C_UCON_TXILEVEL | \ ++ S3C_UCON_RXILEVEL | \ ++ S3C_UCON_TXIRQMODE | \ ++ S3C_UCON_RXIRQMODE | \ ++ S3C_UCON_RXFIFO_TOI) ++ ++/* base definitions for UART FIFO Control Register */ ++#define S3C_UFCON_FIFOMODE (1<<0) ++#define S3C_UFCON_RXTRIG12 (2<<4) ++ ++/* S3C2413 FIFO trigger levels */ ++#define S3C_UFCON_RXTRIG1 (0<<4) ++#define S3C_UFCON_RXTRIG8 (1<<4) ++#define S3C_UFCON_RXTRIG16 (2<<4) ++#define S3C_UFCON_RXTRIG32 (3<<4) ++ ++#define S3C_UFCON_TXTRIG0 (0<<6) ++#define S3C_UFCON_TXTRIG16 (1<<6) ++#define S3C_UFCON_TXTRIG32 (2<<6) ++#define S3C_UFCON_TXTRIG48 (3<<6) ++ ++#define S3C_UFCON_RESETBOTH (3<<1) ++#define S3C_UFCON_RESETTX (1<<2) ++#define S3C_UFCON_RESETRX (1<<1) ++#define S3C_UFCON_FIFO_ENABLE (1<<0) ++ ++#define S3C_UFCON_DEFAULT (S3C_UFCON_FIFOMODE | \ ++ S3C_UFCON_TXTRIG0 | \ ++ S3C_UFCON_RXTRIG8 ) ++ ++#define S3C_UMCOM_AFC (1<<4) ++#define S3C_UMCOM_RTS_LOW (1<<0) ++ ++#define S3C_UFSTAT_TXFULL (1<<14) ++#define S3C_UFSTAT_RXFULL (1<<6) ++#define S3C_UFSTAT_TXSHIFT (8) ++#define S3C_UFSTAT_RXSHIFT (0) ++#define S3C_UFSTAT_TXMASK (63<<8) ++#define S3C_UFSTAT_RXMASK (63) ++ ++#define S3C_UTRSTAT_TXE (1<<2) ++#define S3C_UTRSTAT_TXFE (1<<1) ++#define S3C_UTRSTAT_RXDR (1<<0) ++ ++#define UART_RX_INT (1<<0) ++#define UART_TX_INT (1<<2) ++#define UART_ERR_INT (1<<1) ++#define UART_MODEM_INT (1<<3) ++ ++#define S3C_UERSTAT_OVERRUN (1<<0) ++#define S3C_UERSTAT_FRAME (1<<2) ++#define S3C_UERSTAT_BREAK (1<<3) ++#define S3C_UERSTAT_ANY (S3C_UERSTAT_OVERRUN | \ ++ S3C_UERSTAT_FRAME | \ ++ S3C_UERSTAT_BREAK) ++ ++#define S3C_UMSTAT_CTS (1<<0) ++#define S3C_UMSTAT_DeltaCTS (1<<2) ++#endif ++ + #ifndef __ASSEMBLY__ + + /* struct s3c24xx_uart_clksrc +@@ -208,7 +365,11 @@ + unsigned char hwport; /* hardware port number */ + unsigned char unused; + unsigned short flags; ++#if !defined(CONFIG_CPU_S3C6400) && !defined(CONFIG_CPU_S3C6410) && !defined(CONFIG_CPU_S5PC100) + upf_t uart_flags; /* default uart flags */ ++#else ++ unsigned long uart_flags; /* default uart flags */ ++#endif + + unsigned long ucon; /* value of ucon for port */ + unsigned long ulcon; /* value of ulcon for port */ +@@ -224,7 +385,7 @@ + * or platform_add_device() before the console_initcall() + */ + +-extern struct platform_device *s3c24xx_uart_devs[3]; ++extern struct platform_device *s3c24xx_uart_devs[4]; + + #endif /* __ASSEMBLY__ */ + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-spi.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-spi.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-spi.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-spi.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,124 @@ ++/* linux/include/asm-arm/arch-s3c2410/regs-spi.h ++ * ++ * Copyright (c) 2004 Fetron GmbH ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C2410 SPI register definition ++*/ ++ ++#ifndef __ASM_ARCH_REGS_SPI_H ++#define __ASM_ARCH_REGS_SPI_H ++ ++/* ++ * SPI(High speed) Registers ++ */ ++ ++#define S3C_SPI_REG_CH0(x) ((x) + S3C_VA_SPI0) ++#define S3C_SPI_REG_CH1(x) ((x) + S3C_VA_SPI1) ++ ++#define S3C_CH_CFG (0x00) //SPI configuration ++#define S3C_CLK_CFG (0x04) //Clock configuration ++#define S3C_MODE_CFG (0x08) //SPI FIFO control ++#define S3C_SLAVE_SEL (0x0C) //Slave selection ++#define S3C_SPI_INT_EN (0x10) //SPI interrupt enable ++#define S3C_SPI_STATUS (0x14) //SPI status ++#define S3C_SPI_TX_DATA (0x18) //SPI TX data ++#define S3C_SPI_RX_DATA (0x1C) //SPI RX data ++#define S3C_PACKET_CNT (0x20) //count how many data master gets ++#define S3C_PENDING_CLR (0x24) //Pending clear ++#define S3C_SWAP_CFG (0x28) //SWAP config register ++#define S3C_FB_CLK (0x2C) //SWAP FB config register ++ ++ ++#define SPI_CH_HIGH_SPEED_EN (1<<6) ++#define SPI_CH_SW_RST (1<<5) ++#define SPI_CH_MASTER (0<<4) ++#define SPI_CH_SLAVE (1<<4) ++#define SPI_CH_RISING (0<<3) ++#define SPI_CH_FALLING (1<<3) ++#define SPI_CH_FORMAT_A (0<<2) ++#define SPI_CH_FORMAT_B (1<<2) ++#define SPI_CH_RXCH_OFF (0<<1) ++#define SPI_CH_RXCH_ON (1<<1) ++#define SPI_CH_TXCH_OFF (0<<0) ++#define SPI_CH_TXCH_ON (1<<0) ++ ++#define SPI_CLKSEL_PCLK (0<<9) ++#define SPI_CLKSEL_SCLK_48 (1<<9) ++#define SPI_CLKSEL_SCLK (2<<9) ++#define SPI_ENCLK_DISABLE (0<<8) ++#define SPI_ENCLK_ENABLE (1<<8) ++ ++#define SPI_MODE_CH_TSZ_BYTE (0<<29) ++#define SPI_MODE_CH_TSZ_HALFWORD (1<<29) ++#define SPI_MODE_CH_TSZ_WORD (2<<29) ++#define SPI_MODE_BUS_TSZ_BYTE (0<<18) ++#define SPI_MODE_BUS_TSZ_HALFWORD (1<<17) ++#define SPI_MODE_BUS_TSZ_WORD (2<<17) ++#define SPI_MODE_SWAP_ENABLE (1<<3) ++#define SPI_MODE_SWAP_DISABLE (0<<3) ++#define SPI_MODE_RXDMA_OFF (0<<2) ++#define SPI_MODE_RXDMA_ON (1<<2) ++#define SPI_MODE_TXDMA_OFF (0<<1) ++#define SPI_MODE_TXDMA_ON (1<<1) ++#define SPI_MODE_SINGLE (0<<0) ++#define SPI_MODE_4BURST (1<<0) ++ ++#define SPI_SLAVE_MAN (0<<1) ++#define SPI_SLAVE_AUTO (1<<1) ++#define SPI_SLAVE_SIG_ACT (0<<0) ++#define SPI_SLAVE_SIG_INACT (1<<0) ++ ++#define SPI_INT_TRAILING_DIS (0<<6) ++#define SPI_INT_TRAILING_EN (1<<6) ++#define SPI_INT_RX_OVERRUN_DIS (0<<5) ++#define SPI_INT_RX_OVERRUN_EN (1<<5) ++#define SPI_INT_RX_UNDERRUN_DIS (0<<4) ++#define SPI_INT_RX_UNDERRUN_EN (1<<4) ++#define SPI_INT_TX_OVERRUN_DIS (0<<3) ++#define SPI_INT_TX_OVERRUN_EN (1<<3) ++#define SPI_INT_TX_UNDERRUN_DIS (0<<2) ++#define SPI_INT_TX_UNDERRUN_EN (1<<2) ++#define SPI_INT_RX_FIFORDY_DIS (0<<1) ++#define SPI_INT_RX_FIFORDY_EN (1<<1) ++#define SPI_INT_TX_FIFORDY_DIS (0<<0) ++#define SPI_INT_TX_FIFORDY_EN (1<<0) ++ ++#define SPI_STUS_TX_DONE (1<<21) ++#define SPI_STUS_TRAILCNT_ZERO (1<<20) ++#define SPI_STUS_RX_OVERRUN_ERR (1<<5) ++#define SPI_STUS_RX_UNDERRUN_ERR (1<<4) ++#define SPI_STUS_TX_OVERRUN_ERR (1<<3) ++#define SPI_STUS_TX_UNDERRUN_ERR (1<<2) ++#define SPI_STUS_RX_FIFORDY (1<<1) ++#define SPI_STUS_TX_FIFORDY (1<<0) ++ ++#define SPI_PACKET_CNT_DIS (0<<16) ++#define SPI_PACKET_CNT_EN (1<<16) ++ ++#define SPI_PND_TX_UNDERRUN_CLR (1<<4) ++#define SPI_PND_TX_OVERRUN_CLR (1<<3) ++#define SPI_PND_RX_UNDERRUN_CLR (1<<2) ++#define SPI_PND_RX_OVERRUN_CLR (1<<1) ++#define SPI_PND_TRAILING_CLR (1<<0) ++ ++#define SPI_SWAP_RX_HALF_WORD (1<<7) ++#define SPI_SWAP_RX_BYTE (1<<6) ++#define SPI_SWAP_RX_BIT (1<<5) ++#define SPI_SWAP_RX_EN (1<<4) ++#define SPI_SWAP_TX_HALF_WORD (1<<3) ++#define SPI_SWAP_TX_BYTE (1<<2) ++#define SPI_SWAP_TX_BIT (1<<1) ++#define SPI_SWAP_TX_EN (1<<0) ++ ++#define SPI_FBCLK_0NS (0<<0) ++#define SPI_FBCLK_3NS (1<<0) ++#define SPI_FBCLK_6NS (2<<0) ++#define SPI_FBCLK_9NS (3<<0) ++ ++ ++#endif /* __ASM_ARCH_REGS_SPI_H */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-timer.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-timer.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-timer.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-timer.h 2009-04-30 09:36:37.000000000 +0200 +@@ -1,4 +1,4 @@ +-/* arch/arm/mach-s3c2410/include/mach/regs-timer.h ++/* linux/arch/arm/plat-s3c/include/plat/regs-timer.h + * + * Copyright (c) 2003 Simtec Electronics + * http://www.simtec.co.uk/products/SWLINUX/ +@@ -21,12 +20,15 @@ + #define S3C2410_TCFG1 S3C_TIMERREG(0x04) + #define S3C2410_TCON S3C_TIMERREG(0x08) + ++#define S3C64XX_TINT_CSTAT S3C_TIMERREG(0x44) ++ + #define S3C2410_TCFG_PRESCALER0_MASK (255<<0) + #define S3C2410_TCFG_PRESCALER1_MASK (255<<8) + #define S3C2410_TCFG_PRESCALER1_SHIFT (8) + #define S3C2410_TCFG_DEADZONE_MASK (255<<16) + #define S3C2410_TCFG_DEADZONE_SHIFT (16) + ++#define S3C2410_TCFG1_MUX4_DIV1 (0<<16) + #define S3C2410_TCFG1_MUX4_DIV2 (0<<16) + #define S3C2410_TCFG1_MUX4_DIV4 (1<<16) + #define S3C2410_TCFG1_MUX4_DIV8 (2<<16) +@@ -109,6 +111,109 @@ + #define S3C2410_TCON_T0MANUALUPD (1<<1) + #define S3C2410_TCON_T0START (1<<0) + ++/* Interrupt Control and Status register*/ ++#define S3C_TINT_CSTAT_T4INT (1<<9) ++#define S3C_TINT_CSTAT_T3INT (1<<8) ++#define S3C_TINT_CSTAT_T2INT (1<<7) ++#define S3C_TINT_CSTAT_T1INT (1<<6) ++#define S3C_TINT_CSTAT_T0INT (1<<5) ++#define S3C_TINT_CSTAT_T4INTEN (1<<4) ++#define S3C_TINT_CSTAT_T3INTEN (1<<3) ++#define S3C_TINT_CSTAT_T2INTEN (1<<2) ++#define S3C_TINT_CSTAT_T1INTEN (1<<1) ++#define S3C_TINT_CSTAT_T0INTEN (1<<0) ++ ++#if defined(CONFIG_PLAT_S3C64XX) || defined(CONFIG_PLAT_S5PC1XX) ++#define S3C_TCFG0 S3C_TIMERREG(0x00) ++#define S3C_TCFG1 S3C_TIMERREG(0x04) ++#define S3C_TCON S3C_TIMERREG(0x08) ++#define S3C_TINT_CSTAT S3C_TIMERREG(0x44) ++ ++#define S3C_TCFG_PRESCALER0_MASK (255<<0) ++#define S3C_TCFG_PRESCALER1_MASK (255<<8) ++#define S3C_TCFG_PRESCALER1_SHIFT (8) ++#define S3C_TCFG_PRESCALER0_SHIFT (0) ++#define S3C_TCFG_DEADZONE_MASK (255<<16) ++#define S3C_TCFG_DEADZONE_SHIFT (16) ++ ++#define S3C_TCFG1_MUX4_DIV1 (0<<16) ++#define S3C_TCFG1_MUX4_DIV2 (1<<16) ++#define S3C_TCFG1_MUX4_DIV4 (2<<16) ++#define S3C_TCFG1_MUX4_DIV8 (3<<16) ++#define S3C_TCFG1_MUX4_DIV16 (4<<16) ++#define S3C_TCFG1_MUX4_TCLK1 (5<<16) ++#define S3C_TCFG1_MUX4_MASK (15<<16) ++ ++#define S3C_TCFG1_MUX3_DIV1 (0<<12) ++#define S3C_TCFG1_MUX3_DIV2 (1<<12) ++#define S3C_TCFG1_MUX3_DIV4 (2<<12) ++#define S3C_TCFG1_MUX3_DIV8 (3<<12) ++#define S3C_TCFG1_MUX3_DIV16 (4<<12) ++#define S3C_TCFG1_MUX3_TCLK1 (5<<12) ++#define S3C_TCFG1_MUX3_MASK (15<<12) ++ ++#define S3C_TCFG1_MUX2_DIV1 (0<<8) ++#define S3C_TCFG1_MUX2_DIV2 (1<<8) ++#define S3C_TCFG1_MUX2_DIV4 (2<<8) ++#define S3C_TCFG1_MUX2_DIV8 (3<<8) ++#define S3C_TCFG1_MUX2_DIV16 (4<<8) ++#define S3C_TCFG1_MUX2_TCLK1 (5<<8) ++#define S3C_TCFG1_MUX2_MASK (15<<8) ++ ++#define S3C_TCFG1_MUX1_DIV1 (0<<4) ++#define S3C_TCFG1_MUX1_DIV2 (1<<4) ++#define S3C_TCFG1_MUX1_DIV4 (2<<4) ++#define S3C_TCFG1_MUX1_DIV8 (3<<4) ++#define S3C_TCFG1_MUX1_DIV16 (4<<4) ++#define S3C_TCFG1_MUX1_TCLK0 (5<<4) ++#define S3C_TCFG1_MUX1_MASK (15<<4) ++ ++#define S3C_TCFG1_MUX0_DIV1 (0<<0) ++#define S3C_TCFG1_MUX0_DIV2 (1<<0) ++#define S3C_TCFG1_MUX0_DIV4 (2<<0) ++#define S3C_TCFG1_MUX0_DIV8 (3<<0) ++#define S3C_TCFG1_MUX0_DIV16 (4<<0) ++#define S3C_TCFG1_MUX0_TCLK0 (5<<0) ++#define S3C_TCFG1_MUX0_MASK (15<<0) ++ ++/* for each timer, we have an count buffer, an compare buffer and ++ * * * an observation buffer ++ * * */ ++ ++/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */ ++/* 32bit timer used */ ++ ++#define S3C_TCNTB(tmr) S3C_TIMERREG2(tmr, 0x00) ++#define S3C_TCMPB(tmr) S3C_TIMERREG2(tmr, 0x04) ++#define S3C_TCNTO(tmr) S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08)) ++ ++#define S3C_TCON_T4RELOAD (1<<22) ++#define S3C_TCON_T4MANUALUPD (1<<21) ++#define S3C_TCON_T4START (1<<20) ++ ++#define S3C_TCON_T3RELOAD (1<<19) ++#define S3C_TCON_T3INVERT (1<<18) ++#define S3C_TCON_T3MANUALUPD (1<<17) ++#define S3C_TCON_T3START (1<<16) ++ ++#define S3C_TCON_T2RELOAD (1<<15) ++#define S3C_TCON_T2INVERT (1<<14) ++#define S3C_TCON_T2MANUALUPD (1<<13) ++#define S3C_TCON_T2START (1<<12) ++ ++#define S3C_TCON_T1RELOAD (1<<11) ++#define S3C_TCON_T1INVERT (1<<10) ++#define S3C_TCON_T1MANUALUPD (1<<9) ++#define S3C_TCON_T1START (1<<8) ++ ++#define S3C_TCON_T0DEADZONE (1<<4) ++#define S3C_TCON_T0RELOAD (1<<3) ++#define S3C_TCON_T0INVERT (1<<2) ++#define S3C_TCON_T0MANUALUPD (1<<1) ++#define S3C_TCON_T0START (1<<0) ++ ++#endif ++ + #endif /* __ASM_ARCH_REGS_TIMER_H */ + + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-tvenc.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-tvenc.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-tvenc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-tvenc.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,198 @@ ++/* linux/include/asm-arm/arch-s3c2410/regs-tvenc.h ++ * ++ * Copyright (c) 2007 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation.*/ ++ ++#ifndef __ASM_ARM_REGS_TVENC_H ++#define __ASM_ARM_REGS_TVENC_H ++ ++#define S3C_TVCTRL (0x00) ++#define S3C_VBPORCH (0x04) ++#define S3C_HBPORCH (0x08) ++#define S3C_HENHOFFSET (0x0C) ++#define S3C_VDEMOWINSIZE (0x10) ++#define S3C_HDEMOWINSIZE (0x14) ++#define S3C_INIMAGESIZE (0x18) ++#define S3C_PEDCTRL (0x1C) ++#define S3C_YCFILTERBW (0x20) ++#define S3C_HUECTRL (0x24) ++#define S3C_FSCCTRL (0x28) ++#define S3C_FSCDTOMANCTRL (0x2C) ++#define S3C_BGCTRL (0x34) ++#define S3C_BGHVAVCTRL (0x38) ++#define S3C_CONTRABRIGHT (0x44) ++#define S3C_CBCRGAINCTRL (0x48) ++#define S3C_DEMOWINCTRL (0x4C) ++#define S3C_FTCA (0x50) ++#define S3C_BWGAIN (0x58) ++#define S3C_SHARPCTRL (0x60) ++#define S3C_GAMMACTRL (0x64) ++#define S3C_FSCAUXCTRL (0x68) ++#define S3C_SYNCSIZECTRL (0x6C) ++#define S3C_BURSTCTRL (0x70) ++#define S3C_MACROBURSTCTRL (0x74) ++#define S3C_ACTVIDPOCTRL (0x78) ++#define S3C_ENCCTRL (0x7C) ++#define S3C_MUTECTRL (0x80) ++#define S3C_MACROVISION0 (0x84) ++#define S3C_MACROVISION1 (0x88) ++#define S3C_MACROVISION2 (0x8C) ++#define S3C_MACROVISION3 (0x90) ++#define S3C_MACROVISION4 (0x94) ++#define S3C_MACROVISION5 (0x98) ++#define S3C_MACROVISION6 (0x9C) ++ ++ ++#define S3C_TVCTRL_FIFOURINT_DIS 0<<16 ++#define S3C_TVCTRL_FIFOURINT_ENA 1<<16 ++#define S3C_TVCTRL_FIFOURINT_OCCUR 1<<12 ++#define S3C_TVCTRL_OUTTYPE_C 0<<8 ++#define S3C_TVCTRL_OUTTYPE_S 1<<8 ++#define S3C_TVCTRL_OUTFMT_NTSC_M 0<<4 ++#define S3C_TVCTRL_OUTFMT_NTSC_J 1<<4 ++#define S3C_TVCTRL_OUTFMT_PAL_BDG 2<<4 ++#define S3C_TVCTRL_OUTFMT_PAL_M 3<<4 ++#define S3C_TVCTRL_OUTFMT_PAL_NC 4<<4 ++#define S3C_TVCTRL_OFF 0<<0 ++#define S3C_TVCTRL_ON 1<<0 ++ ++// vertical back porch control ++#define VBP_VEFBPD(n) (((n)&0x1FF)<<16) ++#define VBP_VOFBPD(n) (((n)&0xFF)<<0) ++ ++#define VBP_VEFBPD_NTSC 0x11C<<16 ++#define VBP_VEFBPD_PAL 0x14F<<16 ++#define VBP_VOFBPD_NTSC 0x15<<0 ++#define VBP_VOFBPD_PAL 0x16<<0 ++ ++ ++// horizontal back porch end point ++#define HBP_HSPW(n) (((n)&0xFF)<<16) ++#define HBP_HBPD(n) (((n)&0x7FF)<<0) ++ ++#define HBP_HSPW_NTSC 0x80<<16 ++#define HBP_HSPW_PAL 0x80<<16 ++#define HBP_HBPD_NTSC 0xF4<<0 ++#define HBP_HBPD_PAL 0x108<<0 ++ ++// horizontal enhancer offset ++#define HEO_VAWCC(n) (((n)&0x3F)<<24) ++#define HEO_HAWCC(n) (((n)&0xFF)<<16) ++#define HEO_DTO(n) (((n)&0x7)<<8) ++#define HEO_HEOV(n) (((n)&0x1F)<<0) ++ ++#define HEO_DTO_NTSC 0x4<<8 ++#define HEO_DTO_PAL 0x4<<8 ++#define HEO_HEOV_NTSC 0x1A<<0 ++#define HEO_HEOV_PAL 0x1A<<0 ++ ++ ++// vertical demo window size ++#define VDW_VDWS(n) (((n)&0x1FF)<<16) ++#define VDW_VDWSP(n) (((n)&0x1FF)<<0) ++ ++#define VDW_VDWS_DEF 0xF0<<16 ++#define VDW_VDWSP_DEF 0x0<<0 ++ ++ ++// horizontal demo window size ++#define HDW_HDWEP(n) (((n)&0x7FF)<<16) ++#define HDW_HDWSP(n) (((n)&0x7FF)<<0) ++ ++#define HDW_HDWEP_DEF 0x5A0<<16 ++#define HDW_HDWSP_DEF 0x0<<0 ++ ++ ++// input image size ++#define IIS_HEIGHT(n) (((n)&0x3FF)<<16) ++#define IIS_WIDTH(n) (((n)&0x7FF)<<0) ++ ++// encoder pedestal control ++#define EPC_PED_ON 0<<0 ++#define EPC_PED_OFF 1<<0 ++ ++// yc filter bandwidth control ++#define YFB_YBW_60 0<<4 ++#define YFB_YBW_38 1<<4 ++#define YFB_YBW_31 2<<4 ++#define YFB_YBW_26 3<<4 ++#define YFB_YBW_21 4<<4 ++#define YFB_CBW_12 0<<0 ++#define YFB_CBW_10 1<<0 ++#define YFB_CBW_08 2<<0 ++#define YFB_CBW_06 3<<0 ++ ++// hue control ++#define HUE_CTRL(n) (((n)&0xFF)<<0) ++ ++// fsc control ++#define FSC_CTRL(n) (((n)&0x7FFF)<<0) ++ ++// fsc dto manually control enable ++#define FDM_CTRL(n) (((n)&0x7FFFFFFF)<<0) ++ ++// background control ++#define BGC_BGYOFS(n) (((n)&0xF)<<0) ++ ++#define BGC_SME_DIS 0<<8 ++#define BGC_SME_ENA 1<<8 ++#define BGC_BGCS_BLACK 0<<4 ++#define BGC_BGCS_BLUE 1<<4 ++#define BGC_BGCS_RED 2<<4 ++#define BGC_BGCS_MAGENTA 3<<4 ++#define BGC_BGCS_GREEN 4<<4 ++#define BGC_BGCS_CYAN 5<<4 ++#define BGC_BGCS_YELLOW 6<<4 ++#define BGC_BGCS_WHITE 7<<4 ++ ++// background vav & hav control ++#define BVH_BG_HL(n) (((n)&0xFF)<<24) ++#define BVH_BG_HS(n) (((n)&0xFF)<<16) ++#define BVH_BG_VL(n) (((n)&0xFF)<<8) ++#define BVH_BG_VS(n) (((n)&0xFF)<<0) ++ ++// sync size control ++#define SSC_HSYNC(n) (((n)&0x3FF)<<0) ++ ++#define SSC_HSYNC_NTSC 0x3D<<0 ++#define SSC_HSYNC_PAL 0x3E<<0 ++ ++// burst signal control ++#define BSC_BEND(n) (((n)&0x3FF)<<16) ++#define BSC_BSTART(n) (((n)&0x3FF)<<0) ++ ++#define BSC_BEND_NTSC 0x69<<16 ++#define BSC_BEND_PAL 0x6A<<16 ++#define BSC_BSTART_NTSC 0x49<<0 ++#define BSC_BSTART_PAL 0x4A<<0 ++ ++// macrovision burst signal control ++#define MBS_BSTART(n) (((n)&0x3FF)<<0) ++ ++#define MBS_BSTART_NTSC 0x41<<0 ++#define MBS_BSTART_PAL 0x42<<0 ++ ++// active video position control ++#define AVP_AVEND(n) (((n)&0x3FF)<<16) ++#define AVP_AVSTART(n) (((n)&0x3FF)<<0) ++ ++#define AVP_AVEND_NTSC 0x348<<16 ++#define AVP_AVEND_PAL 0x352<<16 ++#define AVP_AVSTART_NTSC 0x78<<0 ++#define AVP_AVSTART_PAL 0x82<<0 ++ ++// encoder control ++#define ENC_BGEN_DIS 0<<0 ++#define ENC_BGEN_ENA 1<<0 ++ ++#define NTSC_WIDTH (720) ++#define NTSC_HEIGHT (480) ++#define PAL_WIDTH (720) ++#define PAL_HEIGHT (576) ++ ++#endif /* __ASM_ARM_REGS_TVENC_H */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-tvscaler.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-tvscaler.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-tvscaler.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-tvscaler.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,78 @@ ++/* linux/include/asm-arm/arch-s3c2410/regs-tvscaler.h ++ * ++ * Copyright (c) 2007 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C6400 TV SCALER register definitions ++*/ ++ ++#ifndef __ASM_ARM_REGS_TVSCALER ++#define __ASM_ARM_REGS_TVSCALER "regs-tvscaler.h" ++ ++#define S3C_MODE (0x00) ++#define S3C_PRESCALE_RATIO (0x04) ++#define S3C_PRESCALEIMGSIZE (0x08) ++#define S3C_SRCIMGSIZE (0x0C) ++#define S3C_MAINSCALE_H_RATIO (0x10) ++#define S3C_MAINSCALE_V_RATIO (0x14) ++#define S3C_DSTIMGSIZE (0x18) ++#define S3C_PRESCALE_SHFACTOR (0x1C) ++#define S3C_ADDRSTART_Y (0x20) ++#define S3C_ADDRSTART_CB (0x24) ++#define S3C_ADDRSTART_CR (0x28) ++#define S3C_ADDRSTART_RGB (0x2C) ++#define S3C_ADDREND_Y (0x30) ++#define S3C_ADDREND_CB (0x34) ++#define S3C_ADDREND_CR (0x38) ++#define S3C_ADDREND_RGB (0x3C) ++#define S3C_OFFSET_Y (0x40) ++#define S3C_OFFSET_CB (0x44) ++#define S3C_OFFSET_CR (0x48) ++#define S3C_OFFSET_RGB (0x4C) ++#define S3C_NXTADDRSTART_Y (0x54) ++#define S3C_NXTADDRSTART_CB (0x58) ++#define S3C_NXTADDRSTART_CR (0x5C) ++#define S3C_NXTADDRSTART_RGB (0x60) ++#define S3C_NXTADDREND_Y (0x64) ++#define S3C_NXTADDREND_CB (0x68) ++#define S3C_NXTADDREND_CR (0x6C) ++#define S3C_NXTADDREND_RGB (0x70) ++#define S3C_ADDRSTART_OCB (0x74) ++#define S3C_ADDRSTART_OCR (0x78) ++#define S3C_ADDREND_OCB (0x7C) ++#define S3C_ADDREND_OCR (0x80) ++#define S3C_OFFSET_OCB (0x84) ++#define S3C_OFFSET_OCR (0x88) ++#define S3C_NXTADDRSTART_OCB (0x8C) ++#define S3C_NXTADDRSTART_OCR (0x90) ++#define S3C_NXTADDREND_OCB (0x94) ++#define S3C_NXTADDREND_OCR (0x98) ++#define S3C_POSTENVID (0x9C) ++#define S3C_MODE2 (0xA0) ++ ++//POSTENVID ++#define S3C_POSTENVID_ENABLE (0x1<<31) ++#define S3C_POSTENVID_DISABLE (0x0<<31) ++ ++//MODE Control register ++#define S3C_MODE_AUTOLOAD_ENABLE (0x1<<14) ++#define S3C_MODE_POST_INT_ENABLE (0x1<<7) ++#define S3C_MODE_POST_PENDING (0x1<<6) ++#define S3C_MODE_IRQ_LEVEL (0x1<<5) ++#define S3C_MODE_H_CLK_INPUT (0x0<<2) ++#define S3C_MODE_EXT_CLK_0_INPUT (0x1<<2) ++#define S3C_MODE_EXT_CLK_1_INPUT (0x3<<2) ++ ++//MODE Control register 2 ++#define S3C_MODE2_ADDR_CHANGE_ENABLE (0x0<<4) ++#define S3C_MODE2_ADDR_CHANGE_DISABLE (0x1<<4) ++#define S3C_MODE2_CHANGE_AT_FIELD_END (0x0<<3) ++#define S3C_MODE2_CHANGE_AT_FRAME_END (0x1<<3) ++#define S3C_MODE2_SOFTWARE_TRIGGER (0x0<<0) ++#define S3C_MODE2_HARDWARE_TRIGGER (0x1<<0) ++ ++#endif /* __ASM_ARM_REGS_TVSCALER */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-watchdog.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-watchdog.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/regs-watchdog.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/regs-watchdog.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,49 @@ ++/* linux/arch/arm/plat-s3c/include/plat/regs-watchdog.h ++ * ++ * Copyright (c) 2003 Simtec Electronics ++ * http://www.simtec.co.uk/products/SWLINUX/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C2410 Watchdog timer control ++*/ ++ ++ ++#ifndef __ASM_ARCH_REGS_WATCHDOG_H ++#define __ASM_ARCH_REGS_WATCHDOG_H ++ ++#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG) ++ ++#define S3C2410_WTCON S3C_WDOGREG(0x00) ++#define S3C2410_WTDAT S3C_WDOGREG(0x04) ++#define S3C2410_WTCNT S3C_WDOGREG(0x08) ++ ++#define S3C2410_WTCON_OFFSET (0x00) ++#define S3C2410_WTDAT_OFFSET (0x04) ++#define S3C2410_WTCNT_OFFSET (0x08) ++ ++#define S3C2410_WTCNT_CNT (0x1) ++#define S3C2410_WTCNT_CON (0x7639) ++#define S3C2410_WTCNT_DAT (0xFFCF) ++ ++/* the watchdog can either generate a reset pulse, or an ++ * interrupt. ++ */ ++ ++#define S3C2410_WTCON_RSTEN (0x01) ++#define S3C2410_WTCON_INTEN (1<<2) ++#define S3C2410_WTCON_ENABLE (1<<5) ++ ++#define S3C2410_WTCON_DIV16 (0<<3) ++#define S3C2410_WTCON_DIV32 (1<<3) ++#define S3C2410_WTCON_DIV64 (2<<3) ++#define S3C2410_WTCON_DIV128 (3<<3) ++ ++#define S3C2410_WTCON_PRESCALE(x) ((x) << 8) ++#define S3C2410_WTCON_PRESCALE_MASK (0xff00) ++ ++#endif /* __ASM_ARCH_REGS_WATCHDOG_H */ ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/s3c-dma.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/s3c-dma.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/s3c-dma.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/s3c-dma.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,78 @@ ++/* linux/arch/arm/plat-s3c/include/plat/dma.h ++ * ++ */ ++ ++#ifndef __ARM_PLAT_S3C_DMA_H ++#define __ARM_PLAT_S3C_DMA_H ++ ++extern struct sysdev_class dma_sysclass; ++extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS]; ++ ++#define DMA_CH_VALID (1<<31) ++#define DMA_CH_NEVER (1<<30) ++ ++struct s3c_dma_addr { ++ unsigned long from; ++ unsigned long to; ++}; ++ ++/* struct s3c_dma_map ++ * ++ * this holds the mapping information for the channel selected ++ * to be connected to the specified device ++*/ ++ ++struct s3c_dma_map { ++ const char *name; ++ struct s3c_dma_addr hw_addr; ++ ++ unsigned long channels[S3C_DMA_CHANNELS]; ++ unsigned long channels_rx[S3C_DMA_CHANNELS]; ++ ++ unsigned long sdma_sel; ++}; ++ ++struct s3c_dma_selection { ++ struct s3c_dma_map *map; ++ unsigned long map_size; ++ unsigned long dcon_mask; ++ ++ void (*select)(struct s3c2410_dma_chan *chan, ++ struct s3c_dma_map *map); ++ ++ void (*direction)(struct s3c2410_dma_chan *chan, ++ struct s3c_dma_map *map, ++ enum s3c2410_dmasrc dir); ++}; ++ ++extern int s3c_dma_init_map(struct s3c_dma_selection *sel); ++ ++/* struct s3c_dma_order_ch ++ * ++ * channel map for one of the `enum dma_ch` dma channels. the list ++ * entry contains a set of low-level channel numbers, orred with ++ * DMA_CH_VALID, which are checked in the order in the array. ++*/ ++ ++struct s3c_dma_order_ch { ++ unsigned int list[S3C_DMA_CHANNELS]; /* list of channels */ ++ unsigned int flags; /* flags */ ++}; ++ ++/* struct s3c_dma_order ++ * ++ * information provided by either the core or the board to give the ++ * dma system a hint on how to allocate channels ++*/ ++ ++struct s3c_dma_order { ++ struct s3c_dma_order_ch channels[DMACH_MAX]; ++}; ++ ++extern int s3c_dma_order_set(struct s3c_dma_order *map); ++ ++/* DMA init code, called from the cpu support code */ ++ ++extern int s3c_dma_init(unsigned int channels, unsigned int irq, ++ unsigned int stride); ++#endif //__ARM_PLAT_S3C_DMA_H +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/sdhci.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/sdhci.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/sdhci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/sdhci.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,130 @@ ++/* linux/arch/arm/plat-s3c/include/plat/sdhci.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S3C Platform - SDHCI (HSMMC) platform data definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __PLAT_S3C_SDHCI_H ++#define __PLAT_S3C_SDHCI_H __FILE__ ++ ++struct platform_device; ++struct mmc_host; ++struct mmc_card; ++struct mmc_ios; ++ ++/** ++ * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI ++ * @max_width: The maximum number of data bits supported. ++ * @host_caps: Standard MMC host capabilities bit field. ++ * @cfg_gpio: Configure the GPIO for a specific card bit-width ++ * @cfg_card: Configure the interface for a specific card and speed. This ++ * is necessary the controllers and/or GPIO blocks require the ++ * changing of driver-strength and other controls dependant on ++ * the card and speed of operation. ++ * ++ * Initialisation data specific to either the machine or the platform ++ * for the device driver to use or call-back when configuring gpio or ++ * card speed information. ++*/ ++struct s3c_sdhci_platdata { ++ unsigned int max_width; ++ unsigned int host_caps; ++ ++ char **clocks; /* set of clock sources */ ++ ++ void (*cfg_gpio)(struct platform_device *dev, int width); ++ void (*cfg_card)(struct platform_device *dev, ++ void __iomem *regbase, ++ struct mmc_ios *ios, ++ struct mmc_card *card); ++ /* add to deal with EXT_IRQ as a card detect pin */ ++ void (*cfg_ext_cd) (void); ++ unsigned int (*detect_ext_cd) (void); ++ unsigned int ext_cd; ++ ++}; ++ ++/** ++ * s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device. ++ * @pd: Platform data to register to device. ++ * ++ * Register the given platform data for use withe S3C SDHCI device. ++ * The call will copy the platform data, so the board definitions can ++ * make the structure itself __initdata. ++ */ ++extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd); ++extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd); ++extern void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd); ++ ++ ++/* Default platform data, exported so that per-cpu initialisation can ++ * set the correct one when there are more than one cpu type selected. ++*/ ++ ++extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata; ++extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata; ++extern struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata; ++ ++/* Helper function availablity */ ++ ++#if defined (CONFIG_S3C6410_SETUP_SDHCI) || defined (CONFIG_S5PC1XX_SETUP_SDHCI) \ ++ || defined (CONFIG_S5P6440_SETUP_SDHCI) ++extern char *s3c6410_hsmmc_clksrcs[4]; ++ ++extern void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *, int w); ++extern void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *, int w); ++extern void s3c6410_setup_sdhci2_cfg_gpio(struct platform_device *, int w); ++ ++extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev, ++ void __iomem *r, ++ struct mmc_ios *ios, ++ struct mmc_card *card); ++ ++#ifdef CONFIG_S3C_DEV_HSMMC ++static inline void s3c6410_default_sdhci0(void) ++{ ++ s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs; ++ s3c_hsmmc0_def_platdata.cfg_gpio = s3c6410_setup_sdhci0_cfg_gpio; ++ s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; ++} ++#else ++static inline void s3c6410_default_sdhci0(void) { } ++#endif /* CONFIG_S3C_DEV_HSMMC */ ++ ++#ifdef CONFIG_S3C_DEV_HSMMC1 ++static inline void s3c6410_default_sdhci1(void) ++{ ++ s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs; ++ s3c_hsmmc1_def_platdata.cfg_gpio = s3c6410_setup_sdhci1_cfg_gpio; ++ s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; ++} ++#else ++static inline void s3c6410_default_sdhci1(void) { } ++#endif /* CONFIG_S3C_DEV_HSMMC1*/ ++ ++#ifdef CONFIG_S3C_DEV_HSMMC2 ++static inline void s3c6410_default_sdhci2(void) ++{ ++ s3c_hsmmc2_def_platdata.clocks = s3c6410_hsmmc_clksrcs; ++ s3c_hsmmc2_def_platdata.cfg_gpio = s3c6410_setup_sdhci2_cfg_gpio; ++ s3c_hsmmc2_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; ++} ++#else ++static inline void s3c6410_default_sdhci2(void) { } ++#endif /* CONFIG_S3C_DEV_HSMMC1*/ ++ ++#else ++static inline void s3c6410_default_sdhci0(void) { } ++static inline void s3c6410_default_sdhci1(void) { } ++static inline void s3c6410_default_sdhci2(void) { } ++#endif /* CONFIG_S3C6410_SETUP_SDHCI */ ++ ++#endif /* __PLAT_S3C_SDHCI_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/ts.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/ts.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/ts.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/ts.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,42 @@ ++/* linux/arch/arm/plat-s3c/include/plat/ts.h ++ * ++ * Copyright (c) 2004 Simtec Electronics ++ * Ben Dooks ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARCH_TS_H ++#define __ASM_ARCH_TS_H __FILE__ ++ ++ ++enum s3c_adc_type { ++ ADC_TYPE_0, ++ ADC_TYPE_1, /* S3C2416, S3C2450 */ ++ ADC_TYPE_2, /* S3C64XX, S5PC1XX */ ++}; ++ ++struct s3c_ts_mach_info { ++ int delay; ++ int presc; ++ int oversampling_shift; ++ int resol_bit; ++ enum s3c_adc_type s3c_adc_con; ++}; ++ ++struct s3c_ts_info { ++ struct input_dev *dev; ++ long xp; ++ long yp; ++ int count; ++ int shift; ++ char phys[32]; ++ int resol_bit; ++ enum s3c_adc_type s3c_adc_con; ++}; ++ ++extern void __init s3c_ts_set_platdata(struct s3c_ts_mach_info *pd); ++ ++#endif /* __ASM_ARCH_TS_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/include/plat/uncompress.h linux-2.6.28.6/arch/arm/plat-s3c/include/plat/uncompress.h +--- linux-2.6.28/arch/arm/plat-s3c/include/plat/uncompress.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/include/plat/uncompress.h 2009-04-30 09:36:37.000000000 +0200 +@@ -1,4 +1,4 @@ +-/* linux/include/asm-arm/plat-s3c/uncompress.h ++/* linux/arch/arm/plat-s3c/include/plat/uncompress.h + * + * Copyright 2003, 2007 Simtec Electronics + * http://armlinux.simtec.co.uk/ +@@ -28,7 +28,7 @@ + /* defines for UART registers */ + + #include +-#include ++#include + + /* working in physical space... */ + #undef S3C2410_WDOGREG +@@ -37,7 +37,7 @@ + /* how many bytes we allow into the FIFO at a time in FIFO mode */ + #define FIFO_MAX (14) + +-#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT) ++#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT) + + static __inline__ void + uart_wr(unsigned int reg, unsigned int val) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/init.c linux-2.6.28.6/arch/arm/plat-s3c/init.c +--- linux-2.6.28/arch/arm/plat-s3c/init.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/init.c 2009-10-29 09:19:25.000000000 +0100 +@@ -0,0 +1,162 @@ ++/* linux/arch/arm/plat-s3c/init.c ++ * ++ * Copyright (c) 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C series CPU initialisation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++static struct cpu_table *cpu; ++ ++static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode, ++ struct cpu_table *tab, ++ unsigned int count) ++{ ++ for (; count != 0; count--, tab++) { ++ if ((idcode & tab->idmask) == tab->idcode) ++ return tab; ++ } ++ ++ return NULL; ++} ++ ++void __init s3c_init_cpu(unsigned long idcode, ++ struct cpu_table *cputab, unsigned int cputab_size) ++{ ++ cpu = s3c_lookup_cpu(idcode, cputab, cputab_size); ++ ++ if (cpu == NULL) { ++ printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode); ++ panic("Unknown S3C24XX CPU"); ++ } ++ ++ printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode); ++ ++ if (cpu->map_io == NULL || cpu->init == NULL) { ++ printk(KERN_ERR "CPU %s support not enabled\n", cpu->name); ++ panic("Unsupported Samsung CPU"); ++ } ++ ++ cpu->map_io(); ++} ++ ++/* s3c24xx_init_clocks ++ * ++ * Initialise the clock subsystem and associated information from the ++ * given master crystal value. ++ * ++ * xtal = 0 -> use default PLL crystal value (normally 12MHz) ++ * != 0 -> PLL crystal value in Hz ++*/ ++ ++void __init s3c24xx_init_clocks(int xtal) ++{ ++ if (xtal == 0) ++ xtal = 12*1000*1000; ++ ++ if (cpu == NULL) ++ panic("s3c24xx_init_clocks: no cpu setup?\n"); ++ ++ if (cpu->init_clocks == NULL) ++ panic("s3c24xx_init_clocks: cpu has no clock init\n"); ++ else ++ (cpu->init_clocks)(xtal); ++} ++ ++/* uart management */ ++ ++static int nr_uarts __initdata = 0; ++ ++static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS]; ++ ++/* s3c24xx_init_uartdevs ++ * ++ * copy the specified platform data and configuration into our central ++ * set of devices, before the data is thrown away after the init process. ++ * ++ * This also fills in the array passed to the serial driver for the ++ * early initialisation of the console. ++*/ ++ ++void __init s3c24xx_init_uartdevs(char *name, ++ struct s3c24xx_uart_resources *res, ++ struct s3c2410_uartcfg *cfg, int no) ++{ ++ struct platform_device *platdev; ++ struct s3c2410_uartcfg *cfgptr = uart_cfgs; ++ struct s3c24xx_uart_resources *resp; ++ int uart; ++ ++ //printk("iiiiiiiiiiiiiiiiiiii=%d\n",no); ++ memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no); ++ ++ for (uart = 0; uart < no; uart++, cfg++, cfgptr++) { ++ platdev = s3c24xx_uart_src[cfgptr->hwport]; ++ ++ resp = res + cfgptr->hwport; ++ ++ s3c24xx_uart_devs[uart] = platdev; ++ ++ platdev->name = name; ++ platdev->resource = resp->resources; ++ platdev->num_resources = resp->nr_resources; ++ ++ platdev->dev.platform_data = cfgptr; ++ } ++ ++ nr_uarts = no; ++} ++ ++void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) ++{ ++ if (cpu == NULL) ++ return; ++ ++ if (cpu->init_uarts == NULL) { ++ printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n"); ++ } else ++ (cpu->init_uarts)(cfg, no); ++} ++ ++static int __init s3c_arch_init(void) ++{ ++ int ret; ++ ++ // do the correct init for cpu ++ ++ if (cpu == NULL) ++ panic("s3c_arch_init: NULL cpu\n"); ++ ++ ret = (cpu->init)(); ++ if (ret != 0) ++ return ret; ++ ++ ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts); ++ return ret; ++} ++ ++arch_initcall(s3c_arch_init); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/pwm-clock.c linux-2.6.28.6/arch/arm/plat-s3c/pwm-clock.c +--- linux-2.6.28/arch/arm/plat-s3c/pwm-clock.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/pwm-clock.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,435 @@ ++/* linux/arch/arm/plat-s3c/pwm-clock.c ++ * ++ * Copyright (c) 2007 Simtec Electronics ++ * Copyright (c) 2007, 2008 Ben Dooks ++ * Ben Dooks ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++/* Each of the timers 0 through 5 go through the following ++ * clock tree, with the inputs depending on the timers. ++ * ++ * pclk ---- [ prescaler 0 ] -+---> timer 0 ++ * +---> timer 1 ++ * ++ * pclk ---- [ prescaler 1 ] -+---> timer 2 ++ * +---> timer 3 ++ * \---> timer 4 ++ * ++ * Which are fed into the timers as so: ++ * ++ * prescaled 0 ---- [ div 2,4,8,16 ] ---\ ++ * [mux] -> timer 0 ++ * tclk 0 ------------------------------/ ++ * ++ * prescaled 0 ---- [ div 2,4,8,16 ] ---\ ++ * [mux] -> timer 1 ++ * tclk 0 ------------------------------/ ++ * ++ * ++ * prescaled 1 ---- [ div 2,4,8,16 ] ---\ ++ * [mux] -> timer 2 ++ * tclk 1 ------------------------------/ ++ * ++ * prescaled 1 ---- [ div 2,4,8,16 ] ---\ ++ * [mux] -> timer 3 ++ * tclk 1 ------------------------------/ ++ * ++ * prescaled 1 ---- [ div 2,4,8, 16 ] --\ ++ * [mux] -> timer 4 ++ * tclk 1 ------------------------------/ ++ * ++ * Since the mux and the divider are tied together in the ++ * same register space, it is impossible to set the parent ++ * and the rate at the same time. To avoid this, we add an ++ * intermediate 'prescaled-and-divided' clock to select ++ * as the parent for the timer input clock called tdiv. ++ * ++ * prescaled clk --> pwm-tdiv ---\ ++ * [ mux ] --> timer X ++ * tclk -------------------------/ ++*/ ++ ++static unsigned long clk_pwm_scaler_getrate(struct clk *clk) ++{ ++ unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0); ++ ++ if (clk->id == 1) { ++ tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK; ++ tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT; ++ } else { ++ tcfg0 &= S3C2410_TCFG_PRESCALER0_MASK; ++ } ++ ++ return clk_get_rate(clk->parent) / (tcfg0 + 1); ++} ++ ++/* TODO - add set rate calls. */ ++ ++static struct clk clk_timer_scaler[] = { ++ [0] = { ++ .name = "pwm-scaler0", ++ .id = -1, ++ .get_rate = clk_pwm_scaler_getrate, ++ }, ++ [1] = { ++ .name = "pwm-scaler1", ++ .id = -1, ++ .get_rate = clk_pwm_scaler_getrate, ++ }, ++}; ++ ++static struct clk clk_timer_tclk[] = { ++ [0] = { ++ .name = "pwm-tclk0", ++ .id = -1, ++ }, ++ [1] = { ++ .name = "pwm-tclk1", ++ .id = -1, ++ }, ++}; ++ ++struct pwm_tdiv_clk { ++ struct clk clk; ++ unsigned int divisor; ++}; ++ ++static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk) ++{ ++ return container_of(clk, struct pwm_tdiv_clk, clk); ++} ++ ++static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) ++{ ++ return 1 << (1 + tcfg1); ++} ++ ++static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk) ++{ ++ unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); ++ unsigned int divisor; ++ ++ tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id); ++ tcfg1 &= S3C2410_TCFG1_MUX_MASK; ++ ++ if (tcfg1 == S3C2410_TCFG1_MUX_TCLK) ++ divisor = to_tdiv(clk)->divisor; ++ else ++ divisor = tcfg_to_divisor(tcfg1); ++ ++ return clk_get_rate(clk->parent) / divisor; ++} ++ ++static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk, ++ unsigned long rate) ++{ ++ unsigned long parent_rate; ++ unsigned long divisor; ++ ++ parent_rate = clk_get_rate(clk->parent); ++ divisor = parent_rate / rate; ++ ++ if (divisor <= 2) ++ divisor = 2; ++ else if (divisor <= 4) ++ divisor = 4; ++ else if (divisor <= 8) ++ divisor = 8; ++ else ++ divisor = 16; ++ ++ return parent_rate / divisor; ++} ++ ++static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk) ++{ ++ unsigned long bits; ++ ++ switch (divclk->divisor) { ++ case 2: ++ bits = S3C2410_TCFG1_MUX_DIV2; ++ break; ++ case 4: ++ bits = S3C2410_TCFG1_MUX_DIV4; ++ break; ++ case 8: ++ bits = S3C2410_TCFG1_MUX_DIV8; ++ break; ++ case 16: ++ default: ++ bits = S3C2410_TCFG1_MUX_DIV16; ++ break; ++ } ++ ++ return bits; ++} ++ ++static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk) ++{ ++ unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); ++ unsigned long bits = clk_pwm_tdiv_bits(divclk); ++ unsigned long flags; ++ unsigned long shift = S3C2410_TCFG1_SHIFT(divclk->clk.id); ++ ++ local_irq_save(flags); ++ ++ tcfg1 = __raw_readl(S3C2410_TCFG1); ++ tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift); ++ tcfg1 |= bits << shift; ++ __raw_writel(tcfg1, S3C2410_TCFG1); ++ ++ local_irq_restore(flags); ++} ++ ++static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate) ++{ ++ struct pwm_tdiv_clk *divclk = to_tdiv(clk); ++ unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); ++ unsigned long parent_rate = clk_get_rate(clk->parent); ++ unsigned long divisor; ++ ++ tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id); ++ tcfg1 &= S3C2410_TCFG1_MUX_MASK; ++ ++ rate = clk_round_rate(clk, rate); ++ divisor = parent_rate / rate; ++ ++ if (divisor > 16) ++ return -EINVAL; ++ ++ divclk->divisor = divisor; ++ ++ /* Update the current MUX settings if we are currently ++ * selected as the clock source for this clock. */ ++ ++ if (tcfg1 != S3C2410_TCFG1_MUX_TCLK) ++ clk_pwm_tdiv_update(divclk); ++ ++ return 0; ++} ++ ++static struct pwm_tdiv_clk clk_timer_tdiv[] = { ++ [0] = { ++ .clk = { ++ .name = "pwm-tdiv", ++ .parent = &clk_timer_scaler[0], ++ .get_rate = clk_pwm_tdiv_get_rate, ++ .set_rate = clk_pwm_tdiv_set_rate, ++ .round_rate = clk_pwm_tdiv_round_rate, ++ }, ++ }, ++ [1] = { ++ .clk = { ++ .name = "pwm-tdiv", ++ .parent = &clk_timer_scaler[0], ++ .get_rate = clk_pwm_tdiv_get_rate, ++ .set_rate = clk_pwm_tdiv_set_rate, ++ .round_rate = clk_pwm_tdiv_round_rate, ++ } ++ }, ++ [2] = { ++ .clk = { ++ .name = "pwm-tdiv", ++ .parent = &clk_timer_scaler[1], ++ .get_rate = clk_pwm_tdiv_get_rate, ++ .set_rate = clk_pwm_tdiv_set_rate, ++ .round_rate = clk_pwm_tdiv_round_rate, ++ }, ++ }, ++ [3] = { ++ .clk = { ++ .name = "pwm-tdiv", ++ .parent = &clk_timer_scaler[1], ++ .get_rate = clk_pwm_tdiv_get_rate, ++ .set_rate = clk_pwm_tdiv_set_rate, ++ .round_rate = clk_pwm_tdiv_round_rate, ++ }, ++ }, ++ [4] = { ++ .clk = { ++ .name = "pwm-tdiv", ++ .parent = &clk_timer_scaler[1], ++ .get_rate = clk_pwm_tdiv_get_rate, ++ .set_rate = clk_pwm_tdiv_set_rate, ++ .round_rate = clk_pwm_tdiv_round_rate, ++ }, ++ }, ++}; ++ ++static int __init clk_pwm_tdiv_register(unsigned int id) ++{ ++ struct pwm_tdiv_clk *divclk = &clk_timer_tdiv[id]; ++ unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); ++ ++ tcfg1 >>= S3C2410_TCFG1_SHIFT(id); ++ tcfg1 &= S3C2410_TCFG1_MUX_MASK; ++ ++ divclk->clk.id = id; ++ divclk->divisor = tcfg_to_divisor(tcfg1); ++ ++ return s3c24xx_register_clock(&divclk->clk); ++} ++ ++static inline struct clk *s3c24xx_pwmclk_tclk(unsigned int id) ++{ ++ return (id >= 2) ? &clk_timer_tclk[1] : &clk_timer_tclk[0]; ++} ++ ++static inline struct clk *s3c24xx_pwmclk_tdiv(unsigned int id) ++{ ++ return &clk_timer_tdiv[id].clk; ++} ++ ++static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent) ++{ ++ unsigned int id = clk->id; ++ unsigned long tcfg1; ++ unsigned long flags; ++ unsigned long bits; ++ unsigned long shift = S3C2410_TCFG1_SHIFT(id); ++ ++ if (parent == s3c24xx_pwmclk_tclk(id)) ++ bits = S3C2410_TCFG1_MUX_TCLK << shift; ++ else if (parent == s3c24xx_pwmclk_tdiv(id)) ++ bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift; ++ else ++ return -EINVAL; ++ ++ clk->parent = parent; ++ ++ local_irq_save(flags); ++ ++ tcfg1 = __raw_readl(S3C2410_TCFG1); ++ tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift); ++ __raw_writel(tcfg1 | bits, S3C2410_TCFG1); ++ ++ local_irq_restore(flags); ++ ++ return 0; ++} ++ ++static struct clk clk_tin[] = { ++ [0] = { ++ .name = "pwm-tin", ++ .id = 0, ++ .set_parent = clk_pwm_tin_set_parent, ++ }, ++ [1] = { ++ .name = "pwm-tin", ++ .id = 1, ++ .set_parent = clk_pwm_tin_set_parent, ++ }, ++ [2] = { ++ .name = "pwm-tin", ++ .id = 2, ++ .set_parent = clk_pwm_tin_set_parent, ++ }, ++ [3] = { ++ .name = "pwm-tin", ++ .id = 3, ++ .set_parent = clk_pwm_tin_set_parent, ++ }, ++ [4] = { ++ .name = "pwm-tin", ++ .id = 4, ++ .set_parent = clk_pwm_tin_set_parent, ++ }, ++}; ++ ++static __init int clk_pwm_tin_register(struct clk *pwm) ++{ ++ unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); ++ unsigned int id = pwm->id; ++ ++ struct clk *parent; ++ int ret; ++ ++ ret = s3c24xx_register_clock(pwm); ++ if (ret < 0) ++ return ret; ++ ++ tcfg1 >>= S3C2410_TCFG1_SHIFT(id); ++ tcfg1 &= S3C2410_TCFG1_MUX_MASK; ++ ++ if (tcfg1 == S3C2410_TCFG1_MUX_TCLK) ++ parent = s3c24xx_pwmclk_tclk(id); ++ else ++ parent = s3c24xx_pwmclk_tdiv(id); ++ ++ return clk_set_parent(pwm, parent); ++} ++ ++int __init s3c24xx_pwmclk_init(void) ++{ ++ struct clk *clk_timers; ++ unsigned int clk; ++ int ret; ++ ++ clk_timers = clk_get(NULL, "timers"); ++ if (IS_ERR(clk_timers)) { ++ printk(KERN_ERR "%s: no parent clock\n", __func__); ++ return -EINVAL; ++ } ++ ++ for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) { ++ clk_timer_scaler[clk].parent = clk_timers; ++ ret = s3c24xx_register_clock(&clk_timer_scaler[clk]); ++ if (ret < 0) { ++ printk(KERN_ERR "error adding pwm scaler%d clock\n", clk); ++ goto err; ++ } ++ } ++ ++ for (clk = 0; clk < ARRAY_SIZE(clk_timer_tclk); clk++) { ++ ret = s3c24xx_register_clock(&clk_timer_tclk[clk]); ++ if (ret < 0) { ++ printk(KERN_ERR "error adding pww tclk%d\n", clk); ++ goto err; ++ } ++ } ++ ++ for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) { ++ ret = clk_pwm_tdiv_register(clk); ++ if (ret < 0) { ++ printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk); ++ goto err; ++ } ++ } ++ ++ for (clk = 0; clk < ARRAY_SIZE(clk_tin); clk++) { ++ ret = clk_pwm_tin_register(&clk_tin[clk]); ++ if (ret < 0) { ++ printk(KERN_ERR "error adding pwm%d tin clock\n", clk); ++ goto err; ++ } ++ } ++ ++ return 0; ++ ++ err: ++ return ret; ++} ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c/time.c linux-2.6.28.6/arch/arm/plat-s3c/time.c +--- linux-2.6.28/arch/arm/plat-s3c/time.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c/time.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,373 @@ ++/* linux/arch/arm/plat-s3c/time.c ++ * ++ * Copyright (C) 2003-2005 Simtec Electronics ++ * Ben Dooks, ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++static unsigned long timer_startval; ++static unsigned long timer_usec_ticks; ++ ++#ifndef TICK_MAX ++#define TICK_MAX (0xffff) ++#endif ++ ++#define TIMER_USEC_SHIFT 16 ++ ++/* we use the shifted arithmetic to work out the ratio of timer ticks ++ * to usecs, as often the peripheral clock is not a nice even multiple ++ * of 1MHz. ++ * ++ * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok ++ * for the current HZ value of 200 without producing overflows. ++ * ++ * Original patch by Dimitry Andric, updated by Ben Dooks ++*/ ++ ++ ++/* timer_mask_usec_ticks ++ * ++ * given a clock and divisor, make the value to pass into timer_ticks_to_usec ++ * to scale the ticks into usecs ++*/ ++ ++static inline unsigned long ++timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk) ++{ ++ unsigned long den = pclk / 1000; ++ ++ return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den; ++} ++ ++/* timer_ticks_to_usec ++ * ++ * convert timer ticks to usec. ++*/ ++ ++static inline unsigned long timer_ticks_to_usec(unsigned long ticks) ++{ ++ unsigned long res; ++ ++ res = ticks * timer_usec_ticks; ++ res += 1 << (TIMER_USEC_SHIFT - 4); /* round up slightly */ ++ ++ return res >> TIMER_USEC_SHIFT; ++} ++ ++/*** ++ * Returns microsecond since last clock interrupt. Note that interrupts ++ * will have been disabled by do_gettimeoffset() ++ * IRQs are disabled before entering here from do_gettimeofday() ++ */ ++ ++static unsigned long s3c2410_gettimeoffset (void) ++{ ++ unsigned long tdone; ++ unsigned long tval; ++ ++ /* work out how many ticks have gone since last timer interrupt */ ++ ++ tval = __raw_readl(S3C2410_TCNTO(4)); ++ tdone = timer_startval - tval; ++ ++ /* check to see if there is an interrupt pending */ ++ ++ if (s3c24xx_ostimer_pending()) { ++ /* re-read the timer, and try and fix up for the missed ++ * interrupt. Note, the interrupt may go off before the ++ * timer has re-loaded from wrapping. ++ */ ++ ++ tval = __raw_readl(S3C2410_TCNTO(4)); ++ tdone = timer_startval - tval; ++ ++ if (tval != 0) ++ tdone += timer_startval; ++ } ++ ++ return timer_ticks_to_usec(tdone); ++} ++ ++ ++/* ++ * IRQ handler for the timer ++ */ ++static irqreturn_t ++s3c2410_timer_interrupt(int irq, void *dev_id) ++{ ++ timer_tick(); ++ return IRQ_HANDLED; ++} ++ ++static struct irqaction s3c2410_timer_irq = { ++ .name = "S3C2410 Timer Tick", ++ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, ++ .handler = s3c2410_timer_interrupt, ++}; ++ ++#define use_tclk1_12() ( \ ++ machine_is_bast() || \ ++ machine_is_vr1000() || \ ++ machine_is_anubis() || \ ++ machine_is_osiris()) ++ ++/* ++ * Set up timer interrupt, and return the current time in seconds. ++ * ++ * Currently we only use timer4, as it is the only timer which has no ++ * other function that can be exploited externally ++ */ ++static void s3c2410_timer_setup (void) ++{ ++ unsigned long tcon; ++ unsigned long tcnt; ++ unsigned long tcfg1; ++ unsigned long tcfg0; ++ ++ tcnt = TICK_MAX; /* default value for tcnt */ ++ ++ /* read the current timer configuration bits */ ++ ++ tcon = __raw_readl(S3C2410_TCON); ++ tcfg1 = __raw_readl(S3C2410_TCFG1); ++ tcfg0 = __raw_readl(S3C2410_TCFG0); ++ ++ /* configure the system for whichever machine is in use */ ++ ++ if (use_tclk1_12()) { ++ /* timer is at 12MHz, scaler is 1 */ ++ timer_usec_ticks = timer_mask_usec_ticks(1, 12000000); ++ tcnt = 12000000 / HZ; ++ ++ tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK; ++ tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1; ++ } else { ++ unsigned long pclk; ++ struct clk *clk; ++ ++ /* for the h1940 (and others), we use the pclk from the core ++ * to generate the timer values. since values around 50 to ++ * 70MHz are not values we can directly generate the timer ++ * value from, we need to pre-scale and divide before using it. ++ * ++ * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz ++ * (8.45 ticks per usec) ++ */ ++ ++ /* this is used as default if no other timer can be found */ ++ ++ clk = clk_get(NULL, "timers"); ++ if (IS_ERR(clk)) ++ panic("failed to get clock for system timer"); ++ ++ clk_enable(clk); ++ ++ pclk = clk_get_rate(clk); ++ ++ /* configure clock tick */ ++ ++ timer_usec_ticks = timer_mask_usec_ticks(6, pclk); ++ ++ tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK; ++ tcfg1 |= S3C2410_TCFG1_MUX4_DIV2; ++ ++ tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK; ++ tcfg0 |= ((6 - 1) / 2) << S3C2410_TCFG_PRESCALER1_SHIFT; ++ ++ tcnt = (pclk / 6) / HZ; ++ } ++ ++ /* timers reload after counting zero, so reduce the count by 1 */ ++ ++ tcnt--; ++ ++ printk(KERN_DEBUG "timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n", ++ tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks); ++ ++ /* check to see if timer is within 16bit range... */ ++ if (tcnt > TICK_MAX) { ++ panic("setup_timer: HZ is too small, cannot configure timer!"); ++ return; ++ } ++ ++ __raw_writel(tcfg1, S3C2410_TCFG1); ++ __raw_writel(tcfg0, S3C2410_TCFG0); ++ ++ timer_startval = tcnt; ++ __raw_writel(tcnt, S3C2410_TCNTB(4)); ++ ++ /* ensure timer is stopped... */ ++ ++ tcon &= ~(7<<20); ++ tcon |= S3C2410_TCON_T4RELOAD; ++ tcon |= S3C2410_TCON_T4MANUALUPD; ++ ++ __raw_writel(tcon, S3C2410_TCON); ++ __raw_writel(tcnt, S3C2410_TCNTB(4)); ++ __raw_writel(tcnt, S3C2410_TCMPB(4)); ++ ++ /* start the timer running */ ++ tcon |= S3C2410_TCON_T4START; ++ tcon &= ~S3C2410_TCON_T4MANUALUPD; ++ __raw_writel(tcon, S3C2410_TCON); ++} ++ ++static void s3c64xx_timer_setup (void) ++{ ++ unsigned long tcon; ++ unsigned long tcnt; ++ unsigned long tcfg1; ++ unsigned long tcfg0; ++ ++ tcnt = TICK_MAX; /* default value for tcnt */ ++ ++ /* read the current timer configuration bits */ ++ ++ tcon = __raw_readl(S3C2410_TCON); ++ tcfg1 = __raw_readl(S3C2410_TCFG1); ++ tcfg0 = __raw_readl(S3C2410_TCFG0); ++ ++ /* configure the system for whichever machine is in use */ ++ ++ if (use_tclk1_12()) { ++ /* timer is at 12MHz, scaler is 1 */ ++ timer_usec_ticks = timer_mask_usec_ticks(1, 12000000); ++ tcnt = 12000000 / HZ; ++ ++ tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK; ++ tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1; ++ } else { ++ unsigned long pclk; ++ struct clk *clk; ++ ++ /* for the h1940 (and others), we use the pclk from the core ++ * to generate the timer values. since values around 50 to ++ * 70MHz are not values we can directly generate the timer ++ * value from, we need to pre-scale and divide before using it. ++ * ++ * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz ++ * (8.45 ticks per usec) ++ */ ++ ++ /* this is used as default if no other timer can be found */ ++ ++ clk = clk_get(NULL, "timers"); ++ if (IS_ERR(clk)) ++ panic("failed to get clock for system timer"); ++ ++ clk_enable(clk); ++ ++ pclk = clk_get_rate(clk); ++ ++ /* configure clock tick */ ++ ++ timer_usec_ticks = timer_mask_usec_ticks(6, pclk); ++ ++ tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK; ++ tcfg1 |= S3C2410_TCFG1_MUX4_DIV1; ++ ++ tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK; ++ tcfg0 |= (6) << S3C2410_TCFG_PRESCALER1_SHIFT; ++ ++ tcnt = (pclk / 7) / HZ; ++ } ++ ++ /* timers reload after counting zero, so reduce the count by 1 */ ++ ++ tcnt--; ++ ++ printk(KERN_DEBUG "timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n", ++ tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks); ++ ++ /* check to see if timer is within 16bit range... */ ++ if (tcnt > TICK_MAX) { ++ panic("setup_timer: HZ is too small, cannot configure timer!"); ++ return; ++ } ++ ++ __raw_writel(tcfg1, S3C2410_TCFG1); ++ __raw_writel(tcfg0, S3C2410_TCFG0); ++ ++ timer_startval = tcnt; ++ __raw_writel(tcnt, S3C2410_TCNTB(4)); ++ ++ /* ensure timer is stopped... */ ++ ++ tcon &= ~(7<<20); ++ tcon |= S3C2410_TCON_T4RELOAD; ++ tcon |= S3C2410_TCON_T4MANUALUPD; ++ ++ __raw_writel(tcon, S3C2410_TCON); ++ __raw_writel(tcnt, S3C2410_TCNTB(4)); ++ __raw_writel(tcnt, S3C2410_TCMPB(4)); ++ ++ /* start the timer running */ ++ tcon |= S3C2410_TCON_T4START; ++ tcon &= ~S3C2410_TCON_T4MANUALUPD; ++ __raw_writel(tcon, S3C2410_TCON); ++ ++ /* Timer interrupt Enable */ ++ __raw_writel(__raw_readl(S3C64XX_TINT_CSTAT) | S3C_TINT_CSTAT_T4INTEN , S3C64XX_TINT_CSTAT); ++} ++ ++ ++static void __init s3c2410_timer_init(void) ++{ ++ s3c2410_timer_setup(); ++ setup_irq(IRQ_TIMER4, &s3c2410_timer_irq); ++} ++ ++static void __init s3c64xx_timer_init(void) ++{ ++ s3c64xx_timer_setup(); ++ setup_irq(IRQ_TIMER4, &s3c2410_timer_irq); ++} ++ ++struct sys_timer s3c24xx_timer = { ++ .init = s3c2410_timer_init, ++ .offset = s3c2410_gettimeoffset, ++ .resume = s3c2410_timer_setup ++}; ++ ++struct sys_timer s3c64xx_timer = { ++ .init = s3c64xx_timer_init, ++ .offset = s3c2410_gettimeoffset, ++ .resume = s3c64xx_timer_setup ++}; ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/Kconfig linux-2.6.28.6/arch/arm/plat-s3c24xx/Kconfig +--- linux-2.6.28/arch/arm/plat-s3c24xx/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/Kconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -6,8 +6,8 @@ + + config PLAT_S3C24XX + bool +- depends on ARCH_S3C2410 +- default y if ARCH_S3C2410 ++ depends on ARCH_S3C2410 || ARCH_S3C24A0 ++ default y + select NO_IOPORT + select ARCH_REQUIRE_GPIOLIB + help +@@ -15,6 +15,19 @@ + + if PLAT_S3C24XX + ++# code that is shared between a number of the s3c24xx implementations ++ ++config S3C2410_CLOCK ++ bool ++ help ++ Clock code for the S3C2410, and similar processors which ++ is currently includes the S3C2410, S3C2440, S3C2442. ++ ++config S3C24XX_DCLK ++ bool ++ help ++ Clock code for supporting DCLK/CLKOUT on S3C24XX architectures ++ + config CPU_S3C244X + bool + depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442) +@@ -49,6 +62,22 @@ + Enable debugging output for the DMA code. This option sends info + to the kernel log, at priority KERN_DEBUG. + ++# SPI default pin configuration code ++ ++config S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13 ++ bool ++ help ++ SPI GPIO configuration code for BUS0 when connected to ++ GPE11, GPE12 and GPE13. ++ ++config S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7 ++ bool ++ help ++ SPI GPIO configuration code for BUS 1 when connected to ++ GPG5, GPG6 and GPG7. ++ ++# common code for s3c24xx based machines, such as the SMDKs. ++ + config MACH_SMDK + bool + help +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/Makefile linux-2.6.28.6/arch/arm/plat-s3c24xx/Makefile +--- linux-2.6.28/arch/arm/plat-s3c24xx/Makefile 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/Makefile 2009-04-30 09:36:37.000000000 +0200 +@@ -17,9 +17,8 @@ + obj-y += devs.o + obj-y += gpio.o + obj-y += gpiolib.o +-obj-y += time.o + obj-y += clock.o +-obj-y += pwm-clock.o ++obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o + + # Architecture dependant builds + +@@ -30,5 +29,17 @@ + obj-$(CONFIG_PM) += pm.o + obj-$(CONFIG_PM) += sleep.o + obj-$(CONFIG_HAVE_PWM) += pwm.o ++obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o + obj-$(CONFIG_S3C2410_DMA) += dma.o ++ ++# device specific setup and/or initialisation ++obj-$(CONFIG_ARCH_S3C2410) += setup-i2c.o ++ ++# SPI gpio central GPIO functions ++ ++obj-$(CONFIG_S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13) += spi-bus0-gpe11_12_13.o ++obj-$(CONFIG_S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7) += spi-bus1-gpg5_6_7.o ++ ++# machine common support ++ + obj-$(CONFIG_MACH_SMDK) += common-smdk.o +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/clock-dclk.c linux-2.6.28.6/arch/arm/plat-s3c24xx/clock-dclk.c +--- linux-2.6.28/arch/arm/plat-s3c24xx/clock-dclk.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/clock-dclk.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,194 @@ ++/* linux/arch/arm/plat-s3c24xx/clock-dclk.c ++ * ++ * Copyright (c) 2004,2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C24XX - definitions for DCLK and CLKOUT registers ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++/* clocks that could be registered by external code */ ++ ++static int s3c24xx_dclk_enable(struct clk *clk, int enable) ++{ ++ unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON); ++ ++ if (enable) ++ dclkcon |= clk->ctrlbit; ++ else ++ dclkcon &= ~clk->ctrlbit; ++ ++ __raw_writel(dclkcon, S3C24XX_DCLKCON); ++ ++ return 0; ++} ++ ++static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent) ++{ ++ unsigned long dclkcon; ++ unsigned int uclk; ++ ++ if (parent == &clk_upll) ++ uclk = 1; ++ else if (parent == &clk_p) ++ uclk = 0; ++ else ++ return -EINVAL; ++ ++ clk->parent = parent; ++ ++ dclkcon = __raw_readl(S3C24XX_DCLKCON); ++ ++ if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) { ++ if (uclk) ++ dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK; ++ else ++ dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK; ++ } else { ++ if (uclk) ++ dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK; ++ else ++ dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK; ++ } ++ ++ __raw_writel(dclkcon, S3C24XX_DCLKCON); ++ ++ return 0; ++} ++static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate) ++{ ++ unsigned long div; ++ ++ if ((rate == 0) || !clk->parent) ++ return 0; ++ ++ div = clk_get_rate(clk->parent) / rate; ++ if (div < 2) ++ div = 2; ++ else if (div > 16) ++ div = 16; ++ ++ return div; ++} ++ ++static unsigned long s3c24xx_round_dclk_rate(struct clk *clk, ++ unsigned long rate) ++{ ++ unsigned long div = s3c24xx_calc_div(clk, rate); ++ ++ if (div == 0) ++ return 0; ++ ++ return clk_get_rate(clk->parent) / div; ++} ++ ++static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate) ++{ ++ unsigned long mask, data, div = s3c24xx_calc_div(clk, rate); ++ ++ if (div == 0) ++ return -EINVAL; ++ ++ if (clk == &s3c24xx_dclk0) { ++ mask = S3C2410_DCLKCON_DCLK0_DIV_MASK | ++ S3C2410_DCLKCON_DCLK0_CMP_MASK; ++ data = S3C2410_DCLKCON_DCLK0_DIV(div) | ++ S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2); ++ } else if (clk == &s3c24xx_dclk1) { ++ mask = S3C2410_DCLKCON_DCLK1_DIV_MASK | ++ S3C2410_DCLKCON_DCLK1_CMP_MASK; ++ data = S3C2410_DCLKCON_DCLK1_DIV(div) | ++ S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2); ++ } else ++ return -EINVAL; ++ ++ clk->rate = clk_get_rate(clk->parent) / div; ++ __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data), ++ S3C24XX_DCLKCON); ++ return clk->rate; ++} ++static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) ++{ ++ unsigned long mask; ++ unsigned long source; ++ ++ /* calculate the MISCCR setting for the clock */ ++ ++ if (parent == &clk_xtal) ++ source = S3C2410_MISCCR_CLK0_MPLL; ++ else if (parent == &clk_upll) ++ source = S3C2410_MISCCR_CLK0_UPLL; ++ else if (parent == &clk_f) ++ source = S3C2410_MISCCR_CLK0_FCLK; ++ else if (parent == &clk_h) ++ source = S3C2410_MISCCR_CLK0_HCLK; ++ else if (parent == &clk_p) ++ source = S3C2410_MISCCR_CLK0_PCLK; ++ else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0) ++ source = S3C2410_MISCCR_CLK0_DCLK0; ++ else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1) ++ source = S3C2410_MISCCR_CLK0_DCLK0; ++ else ++ return -EINVAL; ++ ++ clk->parent = parent; ++ ++ if (clk == &s3c24xx_clkout0) ++ mask = S3C2410_MISCCR_CLK0_MASK; ++ else { ++ source <<= 4; ++ mask = S3C2410_MISCCR_CLK1_MASK; ++ } ++ ++ s3c2410_modify_misccr(mask, source); ++ return 0; ++} ++ ++/* external clock definitions */ ++ ++struct clk s3c24xx_dclk0 = { ++ .name = "dclk0", ++ .id = -1, ++ .ctrlbit = S3C2410_DCLKCON_DCLK0EN, ++ .enable = s3c24xx_dclk_enable, ++ .set_parent = s3c24xx_dclk_setparent, ++ .set_rate = s3c24xx_set_dclk_rate, ++ .round_rate = s3c24xx_round_dclk_rate, ++}; ++ ++struct clk s3c24xx_dclk1 = { ++ .name = "dclk1", ++ .id = -1, ++ .ctrlbit = S3C2410_DCLKCON_DCLK1EN, ++ .enable = s3c24xx_dclk_enable, ++ .set_parent = s3c24xx_dclk_setparent, ++ .set_rate = s3c24xx_set_dclk_rate, ++ .round_rate = s3c24xx_round_dclk_rate, ++}; ++ ++struct clk s3c24xx_clkout0 = { ++ .name = "clkout0", ++ .id = -1, ++ .set_parent = s3c24xx_clkout_setparent, ++}; ++ ++struct clk s3c24xx_clkout1 = { ++ .name = "clkout1", ++ .id = -1, ++ .set_parent = s3c24xx_clkout_setparent, ++}; +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/clock.c linux-2.6.28.6/arch/arm/plat-s3c24xx/clock.c +--- linux-2.6.28/arch/arm/plat-s3c24xx/clock.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/clock.c 2009-04-30 09:36:37.000000000 +0200 +@@ -27,18 +27,8 @@ + */ + + #include +-#include + #include +-#include +-#include +-#include +-#include +-#include +-#include +-#include + #include +-#include +-#include + #include + + #include +@@ -47,490 +37,23 @@ + #include + #include + ++#include ++ + #include + #include +- +-/* clock information */ +- +-static LIST_HEAD(clocks); +- +-DEFINE_MUTEX(clocks_mutex); +- +-/* enable and disable calls for use with the clk struct */ +- +-static int clk_null_enable(struct clk *clk, int enable) +-{ +- return 0; +-} +- +-/* Clock API calls */ +- +-struct clk *clk_get(struct device *dev, const char *id) +-{ +- struct clk *p; +- struct clk *clk = ERR_PTR(-ENOENT); +- int idno; +- +- if (dev == NULL || dev->bus != &platform_bus_type) +- idno = -1; +- else +- idno = to_platform_device(dev)->id; +- +- mutex_lock(&clocks_mutex); +- +- list_for_each_entry(p, &clocks, list) { +- if (p->id == idno && +- strcmp(id, p->name) == 0 && +- try_module_get(p->owner)) { +- clk = p; +- break; +- } +- } +- +- /* check for the case where a device was supplied, but the +- * clock that was being searched for is not device specific */ +- +- if (IS_ERR(clk)) { +- list_for_each_entry(p, &clocks, list) { +- if (p->id == -1 && strcmp(id, p->name) == 0 && +- try_module_get(p->owner)) { +- clk = p; +- break; +- } +- } +- } +- +- mutex_unlock(&clocks_mutex); +- return clk; +-} +- +-void clk_put(struct clk *clk) +-{ +- module_put(clk->owner); +-} +- +-int clk_enable(struct clk *clk) +-{ +- if (IS_ERR(clk) || clk == NULL) +- return -EINVAL; +- +- clk_enable(clk->parent); +- +- mutex_lock(&clocks_mutex); +- +- if ((clk->usage++) == 0) +- (clk->enable)(clk, 1); +- +- mutex_unlock(&clocks_mutex); +- return 0; +-} +- +-void clk_disable(struct clk *clk) +-{ +- if (IS_ERR(clk) || clk == NULL) +- return; +- +- mutex_lock(&clocks_mutex); +- +- if ((--clk->usage) == 0) +- (clk->enable)(clk, 0); +- +- mutex_unlock(&clocks_mutex); +- clk_disable(clk->parent); +-} +- +- +-unsigned long clk_get_rate(struct clk *clk) +-{ +- if (IS_ERR(clk)) +- return 0; +- +- if (clk->rate != 0) +- return clk->rate; +- +- if (clk->get_rate != NULL) +- return (clk->get_rate)(clk); +- +- if (clk->parent != NULL) +- return clk_get_rate(clk->parent); +- +- return clk->rate; +-} +- +-long clk_round_rate(struct clk *clk, unsigned long rate) +-{ +- if (!IS_ERR(clk) && clk->round_rate) +- return (clk->round_rate)(clk, rate); +- +- return rate; +-} +- +-int clk_set_rate(struct clk *clk, unsigned long rate) +-{ +- int ret; +- +- if (IS_ERR(clk)) +- return -EINVAL; +- +- /* We do not default just do a clk->rate = rate as +- * the clock may have been made this way by choice. +- */ +- +- WARN_ON(clk->set_rate == NULL); +- +- if (clk->set_rate == NULL) +- return -EINVAL; +- +- mutex_lock(&clocks_mutex); +- ret = (clk->set_rate)(clk, rate); +- mutex_unlock(&clocks_mutex); +- +- return ret; +-} +- +-struct clk *clk_get_parent(struct clk *clk) +-{ +- return clk->parent; +-} +- +-int clk_set_parent(struct clk *clk, struct clk *parent) +-{ +- int ret = 0; +- +- if (IS_ERR(clk)) +- return -EINVAL; +- +- mutex_lock(&clocks_mutex); +- +- if (clk->set_parent) +- ret = (clk->set_parent)(clk, parent); +- +- mutex_unlock(&clocks_mutex); +- +- return ret; +-} +- +-EXPORT_SYMBOL(clk_get); +-EXPORT_SYMBOL(clk_put); +-EXPORT_SYMBOL(clk_enable); +-EXPORT_SYMBOL(clk_disable); +-EXPORT_SYMBOL(clk_get_rate); +-EXPORT_SYMBOL(clk_round_rate); +-EXPORT_SYMBOL(clk_set_rate); +-EXPORT_SYMBOL(clk_get_parent); +-EXPORT_SYMBOL(clk_set_parent); +- +-/* base clocks */ +- +-static int clk_default_setrate(struct clk *clk, unsigned long rate) +-{ +- clk->rate = rate; +- return 0; +-} +- +-struct clk clk_xtal = { +- .name = "xtal", +- .id = -1, +- .rate = 0, +- .parent = NULL, +- .ctrlbit = 0, +-}; +- +-struct clk clk_mpll = { +- .name = "mpll", +- .id = -1, +- .set_rate = clk_default_setrate, +-}; +- +-struct clk clk_upll = { +- .name = "upll", +- .id = -1, +- .parent = NULL, +- .ctrlbit = 0, +-}; +- +-struct clk clk_f = { +- .name = "fclk", +- .id = -1, +- .rate = 0, +- .parent = &clk_mpll, +- .ctrlbit = 0, +- .set_rate = clk_default_setrate, +-}; +- +-struct clk clk_h = { +- .name = "hclk", +- .id = -1, +- .rate = 0, +- .parent = NULL, +- .ctrlbit = 0, +- .set_rate = clk_default_setrate, +-}; +- +-struct clk clk_p = { +- .name = "pclk", +- .id = -1, +- .rate = 0, +- .parent = NULL, +- .ctrlbit = 0, +- .set_rate = clk_default_setrate, +-}; +- +-struct clk clk_usb_bus = { +- .name = "usb-bus", +- .id = -1, +- .rate = 0, +- .parent = &clk_upll, +-}; +- +-/* clocks that could be registered by external code */ +- +-static int s3c24xx_dclk_enable(struct clk *clk, int enable) +-{ +- unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON); +- +- if (enable) +- dclkcon |= clk->ctrlbit; +- else +- dclkcon &= ~clk->ctrlbit; +- +- __raw_writel(dclkcon, S3C24XX_DCLKCON); +- +- return 0; +-} +- +-static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent) +-{ +- unsigned long dclkcon; +- unsigned int uclk; +- +- if (parent == &clk_upll) +- uclk = 1; +- else if (parent == &clk_p) +- uclk = 0; +- else +- return -EINVAL; +- +- clk->parent = parent; +- +- dclkcon = __raw_readl(S3C24XX_DCLKCON); +- +- if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) { +- if (uclk) +- dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK; +- else +- dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK; +- } else { +- if (uclk) +- dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK; +- else +- dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK; +- } +- +- __raw_writel(dclkcon, S3C24XX_DCLKCON); +- +- return 0; +-} +- +-static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate) +-{ +- unsigned long div; +- +- if ((rate == 0) || !clk->parent) +- return 0; +- +- div = clk_get_rate(clk->parent) / rate; +- if (div < 2) +- div = 2; +- else if (div > 16) +- div = 16; +- +- return div; +-} +- +-static unsigned long s3c24xx_round_dclk_rate(struct clk *clk, +- unsigned long rate) +-{ +- unsigned long div = s3c24xx_calc_div(clk, rate); +- +- if (div == 0) +- return 0; +- +- return clk_get_rate(clk->parent) / div; +-} +- +-static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate) +-{ +- unsigned long mask, data, div = s3c24xx_calc_div(clk, rate); +- +- if (div == 0) +- return -EINVAL; +- +- if (clk == &s3c24xx_dclk0) { +- mask = S3C2410_DCLKCON_DCLK0_DIV_MASK | +- S3C2410_DCLKCON_DCLK0_CMP_MASK; +- data = S3C2410_DCLKCON_DCLK0_DIV(div) | +- S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2); +- } else if (clk == &s3c24xx_dclk1) { +- mask = S3C2410_DCLKCON_DCLK1_DIV_MASK | +- S3C2410_DCLKCON_DCLK1_CMP_MASK; +- data = S3C2410_DCLKCON_DCLK1_DIV(div) | +- S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2); +- } else +- return -EINVAL; +- +- clk->rate = clk_get_rate(clk->parent) / div; +- __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data), +- S3C24XX_DCLKCON); +- return clk->rate; +-} +- +-static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) +-{ +- unsigned long mask; +- unsigned long source; +- +- /* calculate the MISCCR setting for the clock */ +- +- if (parent == &clk_xtal) +- source = S3C2410_MISCCR_CLK0_MPLL; +- else if (parent == &clk_upll) +- source = S3C2410_MISCCR_CLK0_UPLL; +- else if (parent == &clk_f) +- source = S3C2410_MISCCR_CLK0_FCLK; +- else if (parent == &clk_h) +- source = S3C2410_MISCCR_CLK0_HCLK; +- else if (parent == &clk_p) +- source = S3C2410_MISCCR_CLK0_PCLK; +- else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0) +- source = S3C2410_MISCCR_CLK0_DCLK0; +- else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1) +- source = S3C2410_MISCCR_CLK0_DCLK0; +- else +- return -EINVAL; +- +- clk->parent = parent; +- +- if (clk == &s3c24xx_clkout0) +- mask = S3C2410_MISCCR_CLK0_MASK; +- else { +- source <<= 4; +- mask = S3C2410_MISCCR_CLK1_MASK; +- } +- +- s3c2410_modify_misccr(mask, source); +- return 0; +-} +- +-/* external clock definitions */ +- +-struct clk s3c24xx_dclk0 = { +- .name = "dclk0", +- .id = -1, +- .ctrlbit = S3C2410_DCLKCON_DCLK0EN, +- .enable = s3c24xx_dclk_enable, +- .set_parent = s3c24xx_dclk_setparent, +- .set_rate = s3c24xx_set_dclk_rate, +- .round_rate = s3c24xx_round_dclk_rate, +-}; +- +-struct clk s3c24xx_dclk1 = { +- .name = "dclk1", +- .id = -1, +- .ctrlbit = S3C2410_DCLKCON_DCLK1EN, +- .enable = s3c24xx_dclk_enable, +- .set_parent = s3c24xx_dclk_setparent, +- .set_rate = s3c24xx_set_dclk_rate, +- .round_rate = s3c24xx_round_dclk_rate, +-}; +- +-struct clk s3c24xx_clkout0 = { +- .name = "clkout0", +- .id = -1, +- .set_parent = s3c24xx_clkout_setparent, +-}; +- +-struct clk s3c24xx_clkout1 = { +- .name = "clkout1", +- .id = -1, +- .set_parent = s3c24xx_clkout_setparent, +-}; +- +-struct clk s3c24xx_uclk = { +- .name = "uclk", +- .id = -1, +-}; +- +-/* initialise the clock system */ +- +-int s3c24xx_register_clock(struct clk *clk) +-{ +- clk->owner = THIS_MODULE; +- +- if (clk->enable == NULL) +- clk->enable = clk_null_enable; +- +- /* add to the list of available clocks */ +- +- mutex_lock(&clocks_mutex); +- list_add(&clk->list, &clocks); +- mutex_unlock(&clocks_mutex); +- +- return 0; +-} +- +-int s3c24xx_register_clocks(struct clk **clks, int nr_clks) +-{ +- int fails = 0; +- +- for (; nr_clks > 0; nr_clks--, clks++) { +- if (s3c24xx_register_clock(*clks) < 0) +- fails++; +- } +- +- return fails; +-} ++#include + + /* initalise all the clocks */ + +-int __init s3c24xx_setup_clocks(unsigned long xtal, +- unsigned long fclk, ++void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk, + unsigned long hclk, + unsigned long pclk) + { +- printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n"); +- +- /* initialise the main system clocks */ +- +- clk_xtal.rate = xtal; +- clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), xtal); ++ clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON), ++ clk_xtal.rate); + + clk_mpll.rate = fclk; + clk_h.rate = hclk; + clk_p.rate = pclk; + clk_f.rate = fclk; +- +- /* assume uart clocks are correctly setup */ +- +- /* register our clocks */ +- +- if (s3c24xx_register_clock(&clk_xtal) < 0) +- printk(KERN_ERR "failed to register master xtal\n"); +- +- if (s3c24xx_register_clock(&clk_mpll) < 0) +- printk(KERN_ERR "failed to register mpll clock\n"); +- +- if (s3c24xx_register_clock(&clk_upll) < 0) +- printk(KERN_ERR "failed to register upll clock\n"); +- +- if (s3c24xx_register_clock(&clk_f) < 0) +- printk(KERN_ERR "failed to register cpu fclk\n"); +- +- if (s3c24xx_register_clock(&clk_h) < 0) +- printk(KERN_ERR "failed to register cpu hclk\n"); +- +- if (s3c24xx_register_clock(&clk_p) < 0) +- printk(KERN_ERR "failed to register cpu pclk\n"); +- +- return 0; + } +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/common-smdk.c linux-2.6.28.6/arch/arm/plat-s3c24xx/common-smdk.c +--- linux-2.6.28/arch/arm/plat-s3c24xx/common-smdk.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/common-smdk.c 2009-04-30 09:36:37.000000000 +0200 +@@ -38,7 +38,7 @@ + #include + #include + +-#include ++#include + + #include + #include +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/cpu.c linux-2.6.28.6/arch/arm/plat-s3c24xx/cpu.c +--- linux-2.6.28/arch/arm/plat-s3c24xx/cpu.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/cpu.c 2009-04-30 09:36:37.000000000 +0200 +@@ -55,16 +55,6 @@ + #include + #include + +-struct cpu_table { +- unsigned long idcode; +- unsigned long idmask; +- void (*map_io)(struct map_desc *mach_desc, int size); +- void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no); +- void (*init_clocks)(int xtal); +- int (*init)(void); +- const char *name; +-}; +- + /* table of supported CPUs */ + + static const char name_s3c2400[] = "S3C2400"; +@@ -169,23 +159,7 @@ + IODESC_ENT(UART) + }; + +-static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode) +-{ +- struct cpu_table *tab; +- int count; +- +- tab = cpu_ids; +- for (count = 0; count < ARRAY_SIZE(cpu_ids); count++, tab++) { +- if ((idcode & tab->idmask) == tab->idcode) +- return tab; +- } +- +- return NULL; +-} +- +-/* cpu information */ +- +-static struct cpu_table *cpu; ++/* read cpu identificaiton code */ + + static unsigned long s3c24xx_read_idcode_v5(void) + { +@@ -231,6 +205,7 @@ + unsigned long idcode = 0x0; + + /* initialise the io descriptors we need for initialisation */ ++ iotable_init(mach_desc, size); + iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); + + if (cpu_architecture() >= CPU_ARCH_ARMv5) { +@@ -239,117 +214,7 @@ + idcode = s3c24xx_read_idcode_v4(); + } + +- cpu = s3c_lookup_cpu(idcode); +- +- if (cpu == NULL) { +- printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode); +- panic("Unknown S3C24XX CPU"); +- } +- +- printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode); +- +- if (cpu->map_io == NULL || cpu->init == NULL) { +- printk(KERN_ERR "CPU %s support not enabled\n", cpu->name); +- panic("Unsupported S3C24XX CPU"); +- } +- + arm_pm_restart = s3c24xx_pm_restart; + +- (cpu->map_io)(mach_desc, size); +-} +- +-/* s3c24xx_init_clocks +- * +- * Initialise the clock subsystem and associated information from the +- * given master crystal value. +- * +- * xtal = 0 -> use default PLL crystal value (normally 12MHz) +- * != 0 -> PLL crystal value in Hz +-*/ +- +-void __init s3c24xx_init_clocks(int xtal) +-{ +- if (xtal == 0) +- xtal = 12*1000*1000; +- +- if (cpu == NULL) +- panic("s3c24xx_init_clocks: no cpu setup?\n"); +- +- if (cpu->init_clocks == NULL) +- panic("s3c24xx_init_clocks: cpu has no clock init\n"); +- else +- (cpu->init_clocks)(xtal); ++ s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); + } +- +-/* uart management */ +- +-static int nr_uarts __initdata = 0; +- +-static struct s3c2410_uartcfg uart_cfgs[3]; +- +-/* s3c24xx_init_uartdevs +- * +- * copy the specified platform data and configuration into our central +- * set of devices, before the data is thrown away after the init process. +- * +- * This also fills in the array passed to the serial driver for the +- * early initialisation of the console. +-*/ +- +-void __init s3c24xx_init_uartdevs(char *name, +- struct s3c24xx_uart_resources *res, +- struct s3c2410_uartcfg *cfg, int no) +-{ +- struct platform_device *platdev; +- struct s3c2410_uartcfg *cfgptr = uart_cfgs; +- struct s3c24xx_uart_resources *resp; +- int uart; +- +- memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no); +- +- for (uart = 0; uart < no; uart++, cfg++, cfgptr++) { +- platdev = s3c24xx_uart_src[cfgptr->hwport]; +- +- resp = res + cfgptr->hwport; +- +- s3c24xx_uart_devs[uart] = platdev; +- +- platdev->name = name; +- platdev->resource = resp->resources; +- platdev->num_resources = resp->nr_resources; +- +- platdev->dev.platform_data = cfgptr; +- } +- +- nr_uarts = no; +-} +- +-void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) +-{ +- if (cpu == NULL) +- return; +- +- if (cpu->init_uarts == NULL) { +- printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n"); +- } else +- (cpu->init_uarts)(cfg, no); +-} +- +-static int __init s3c_arch_init(void) +-{ +- int ret; +- +- // do the correct init for cpu +- +- if (cpu == NULL) +- panic("s3c_arch_init: NULL cpu\n"); +- +- ret = (cpu->init)(); +- if (ret != 0) +- return ret; +- +- ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts); +- return ret; +-} +- +-arch_initcall(s3c_arch_init); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/devs.c linux-2.6.28.6/arch/arm/plat-s3c24xx/devs.c +--- linux-2.6.28/arch/arm/plat-s3c24xx/devs.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/devs.c 2009-04-30 09:36:37.000000000 +0200 +@@ -29,11 +29,11 @@ + #include + + #include +-#include ++#include + + #include + #include +-#include ++#include + + /* Serial port registrations */ + +@@ -76,6 +76,19 @@ + } + }; + ++static struct resource s3c2410_uart3_resource[] = { ++ [0] = { ++ .start = S3C2443_PA_UART3, ++ .end = S3C2443_PA_UART3 + 0x3fff, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_S3CUART_RX3, ++ .end = IRQ_S3CUART_ERR3, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ + struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = { + [0] = { + .resources = s3c2410_uart0_resource, +@@ -89,6 +102,10 @@ + .resources = s3c2410_uart2_resource, + .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource), + }, ++ [3] = { ++ .resources = s3c2410_uart3_resource, ++ .nr_resources = ARRAY_SIZE(s3c2410_uart3_resource), ++ }, + }; + + /* yart devices */ +@@ -105,13 +122,18 @@ + .id = 2, + }; + +-struct platform_device *s3c24xx_uart_src[3] = { ++static struct platform_device s3c24xx_uart_device3 = { ++ .id = 3, ++}; ++ ++struct platform_device *s3c24xx_uart_src[4] = { + &s3c24xx_uart_device0, + &s3c24xx_uart_device1, + &s3c24xx_uart_device2, ++ &s3c24xx_uart_device3, + }; + +-struct platform_device *s3c24xx_uart_devs[3] = { ++struct platform_device *s3c24xx_uart_devs[4] = { + }; + + /* USB Host Controller */ +@@ -192,8 +214,8 @@ + + static struct resource s3c_nand_resource[] = { + [0] = { +- .start = S3C2410_PA_NAND, +- .end = S3C2410_PA_NAND + S3C24XX_SZ_NAND - 1, ++ .start = S3C24XX_PA_NAND, ++ .end = S3C24XX_PA_NAND + S3C24XX_SZ_NAND - 1, + .flags = IORESOURCE_MEM, + } + }; +@@ -271,31 +293,6 @@ + + EXPORT_SYMBOL(s3c_device_wdt); + +-/* I2C */ +- +-static struct resource s3c_i2c_resource[] = { +- [0] = { +- .start = S3C24XX_PA_IIC, +- .end = S3C24XX_PA_IIC + S3C24XX_SZ_IIC - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = IRQ_IIC, +- .end = IRQ_IIC, +- .flags = IORESOURCE_IRQ, +- } +- +-}; +- +-struct platform_device s3c_device_i2c = { +- .name = "s3c2410-i2c", +- .id = -1, +- .num_resources = ARRAY_SIZE(s3c_i2c_resource), +- .resource = s3c_i2c_resource, +-}; +- +-EXPORT_SYMBOL(s3c_device_i2c); +- + /* IIS */ + + static struct resource s3c_iis_resource[] = { +@@ -382,8 +379,8 @@ + + static struct resource s3c_sdi_resource[] = { + [0] = { +- .start = S3C2410_PA_SDI, +- .end = S3C2410_PA_SDI + S3C24XX_SZ_SDI - 1, ++ .start = S3C24XX_PA_SDI, ++ .end = S3C24XX_PA_SDI + S3C24XX_SZ_SDI - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { +@@ -403,36 +400,6 @@ + + EXPORT_SYMBOL(s3c_device_sdi); + +-/* High-speed MMC/SD */ +- +-static struct resource s3c_hsmmc_resource[] = { +- [0] = { +- .start = S3C2443_PA_HSMMC, +- .end = S3C2443_PA_HSMMC + S3C2443_SZ_HSMMC - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = IRQ_S3C2443_HSMMC, +- .end = IRQ_S3C2443_HSMMC, +- .flags = IORESOURCE_IRQ, +- } +-}; +- +-static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL; +- +-struct platform_device s3c_device_hsmmc = { +- .name = "s3c-sdhci", +- .id = -1, +- .num_resources = ARRAY_SIZE(s3c_hsmmc_resource), +- .resource = s3c_hsmmc_resource, +- .dev = { +- .dma_mask = &s3c_device_hsmmc_dmamask, +- .coherent_dma_mask = 0xffffffffUL +- } +-}; +- +- +- + /* SPI (0) */ + + static struct resource s3c_spi0_resource[] = { +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/gpiolib.c linux-2.6.28.6/arch/arm/plat-s3c24xx/gpiolib.c +--- linux-2.6.28/arch/arm/plat-s3c24xx/gpiolib.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/gpiolib.c 2009-04-30 09:36:37.000000000 +0200 +@@ -19,104 +19,12 @@ + #include + #include + ++#include + #include + #include + + #include + +-struct s3c24xx_gpio_chip { +- struct gpio_chip chip; +- void __iomem *base; +-}; +- +-static inline struct s3c24xx_gpio_chip *to_s3c_chip(struct gpio_chip *gpc) +-{ +- return container_of(gpc, struct s3c24xx_gpio_chip, chip); +-} +- +-/* these routines are exported for use by other parts of the platform +- * and system support, but are not intended to be used directly by the +- * drivers themsevles. +- */ +- +-static int s3c24xx_gpiolib_input(struct gpio_chip *chip, unsigned offset) +-{ +- struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); +- void __iomem *base = ourchip->base; +- unsigned long flags; +- unsigned long con; +- +- local_irq_save(flags); +- +- con = __raw_readl(base + 0x00); +- con &= ~(3 << (offset * 2)); +- con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2); +- +- __raw_writel(con, base + 0x00); +- +- local_irq_restore(flags); +- return 0; +-} +- +-static int s3c24xx_gpiolib_output(struct gpio_chip *chip, +- unsigned offset, int value) +-{ +- struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); +- void __iomem *base = ourchip->base; +- unsigned long flags; +- unsigned long dat; +- unsigned long con; +- +- local_irq_save(flags); +- +- dat = __raw_readl(base + 0x04); +- dat &= ~(1 << offset); +- if (value) +- dat |= 1 << offset; +- __raw_writel(dat, base + 0x04); +- +- con = __raw_readl(base + 0x00); +- con &= ~(3 << (offset * 2)); +- con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2); +- +- __raw_writel(con, base + 0x00); +- __raw_writel(dat, base + 0x04); +- +- local_irq_restore(flags); +- return 0; +-} +- +-static void s3c24xx_gpiolib_set(struct gpio_chip *chip, +- unsigned offset, int value) +-{ +- struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); +- void __iomem *base = ourchip->base; +- unsigned long flags; +- unsigned long dat; +- +- local_irq_save(flags); +- +- dat = __raw_readl(base + 0x04); +- dat &= ~(1 << offset); +- if (value) +- dat |= 1 << offset; +- __raw_writel(dat, base + 0x04); +- +- local_irq_restore(flags); +-} +- +-static int s3c24xx_gpiolib_get(struct gpio_chip *chip, unsigned offset) +-{ +- struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); +- unsigned long val; +- +- val = __raw_readl(ourchip->base + 0x04); +- val >>= offset; +- val &= 1; +- +- return val; +-} +- + static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset) + { + return -EINVAL; +@@ -125,7 +33,7 @@ + static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip, + unsigned offset, int value) + { +- struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); ++ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + unsigned long flags; + unsigned long dat; +@@ -151,7 +59,7 @@ + return 0; + } + +-static struct s3c24xx_gpio_chip gpios[] = { ++struct s3c_gpio_chip s3c24xx_gpios[] = { + [0] = { + .base = S3C24XX_GPIO_BASE(S3C2410_GPA0), + .chip = { +@@ -161,8 +69,6 @@ + .ngpio = 24, + .direction_input = s3c24xx_gpiolib_banka_input, + .direction_output = s3c24xx_gpiolib_banka_output, +- .set = s3c24xx_gpiolib_set, +- .get = s3c24xx_gpiolib_get, + }, + }, + [1] = { +@@ -172,10 +78,6 @@ + .owner = THIS_MODULE, + .label = "GPIOB", + .ngpio = 16, +- .direction_input = s3c24xx_gpiolib_input, +- .direction_output = s3c24xx_gpiolib_output, +- .set = s3c24xx_gpiolib_set, +- .get = s3c24xx_gpiolib_get, + }, + }, + [2] = { +@@ -185,10 +87,6 @@ + .owner = THIS_MODULE, + .label = "GPIOC", + .ngpio = 16, +- .direction_input = s3c24xx_gpiolib_input, +- .direction_output = s3c24xx_gpiolib_output, +- .set = s3c24xx_gpiolib_set, +- .get = s3c24xx_gpiolib_get, + }, + }, + [3] = { +@@ -198,10 +96,6 @@ + .owner = THIS_MODULE, + .label = "GPIOD", + .ngpio = 16, +- .direction_input = s3c24xx_gpiolib_input, +- .direction_output = s3c24xx_gpiolib_output, +- .set = s3c24xx_gpiolib_set, +- .get = s3c24xx_gpiolib_get, + }, + }, + [4] = { +@@ -211,10 +105,6 @@ + .label = "GPIOE", + .owner = THIS_MODULE, + .ngpio = 16, +- .direction_input = s3c24xx_gpiolib_input, +- .direction_output = s3c24xx_gpiolib_output, +- .set = s3c24xx_gpiolib_set, +- .get = s3c24xx_gpiolib_get, + }, + }, + [5] = { +@@ -224,10 +114,6 @@ + .owner = THIS_MODULE, + .label = "GPIOF", + .ngpio = 8, +- .direction_input = s3c24xx_gpiolib_input, +- .direction_output = s3c24xx_gpiolib_output, +- .set = s3c24xx_gpiolib_set, +- .get = s3c24xx_gpiolib_get, + }, + }, + [6] = { +@@ -237,21 +123,17 @@ + .owner = THIS_MODULE, + .label = "GPIOG", + .ngpio = 10, +- .direction_input = s3c24xx_gpiolib_input, +- .direction_output = s3c24xx_gpiolib_output, +- .set = s3c24xx_gpiolib_set, +- .get = s3c24xx_gpiolib_get, + }, + }, + }; + + static __init int s3c24xx_gpiolib_init(void) + { +- struct s3c24xx_gpio_chip *chip = gpios; ++ struct s3c_gpio_chip *chip = s3c24xx_gpios; + int gpn; + +- for (gpn = 0; gpn < ARRAY_SIZE(gpios); gpn++, chip++) +- gpiochip_add(&chip->chip); ++ for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) ++ s3c_gpiolib_add(chip); + + return 0; + } +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/map.h linux-2.6.28.6/arch/arm/plat-s3c24xx/include/plat/map.h +--- linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/map.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/include/plat/map.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,99 @@ ++/* linux/include/asm-arm/plat-s3c24xx/map.h ++ * ++ * Copyright (c) 2008 Simtec Electronics ++ * Ben Dooks ++ * ++ * S3C24XX - Memory map definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_PLAT_S3C24XX_MAP_H ++#define __ASM_PLAT_S3C24XX_MAP_H ++ ++/* interrupt controller is the first thing we put in, to make ++ * the assembly code for the irq detection easier ++ */ ++#define S3C24XX_VA_IRQ S3C_VA_IRQ ++#define S3C2410_PA_IRQ (0x4A000000) ++#define S3C24XX_SZ_IRQ SZ_1M ++ ++/* memory controller registers */ ++#define S3C24XX_VA_MEMCTRL S3C_VA_MEM ++#define S3C2410_PA_MEMCTRL (0x48000000) ++#define S3C24XX_SZ_MEMCTRL SZ_1M ++ ++/* UARTs */ ++#define S3C24XX_VA_UART S3C_VA_UART ++#define S3C2410_PA_UART (0x50000000) ++#define S3C24XX_SZ_UART SZ_1M ++#define S3C_UART_OFFSET (0x4000) ++ ++/* Timers */ ++#define S3C24XX_VA_TIMER S3C_VA_TIMER ++#define S3C2410_PA_TIMER (0x51000000) ++#define S3C24XX_SZ_TIMER SZ_1M ++ ++/* Clock and Power management */ ++#define S3C24XX_VA_CLKPWR S3C_VA_SYS ++#define S3C24XX_SZ_CLKPWR SZ_1M ++ ++/* USB Device port */ ++#define S3C2410_PA_USBDEV (0x52000000) ++#define S3C24XX_SZ_USBDEV SZ_1M ++ ++/* Watchdog */ ++#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG ++#define S3C2410_PA_WATCHDOG (0x53000000) ++#define S3C24XX_SZ_WATCHDOG SZ_1M ++ ++/* Standard size definitions for peripheral blocks. */ ++ ++#define S3C24XX_SZ_IIS SZ_1M ++#define S3C24XX_SZ_ADC SZ_1M ++#define S3C24XX_SZ_SPI SZ_1M ++#define S3C24XX_SZ_SDI SZ_1M ++#define S3C24XX_SZ_NAND SZ_1M ++#define S3C24XX_SZ_USBHOST SZ_1M ++ ++/* GPIO ports */ ++ ++/* the calculation for the VA of this must ensure that ++ * it is the same distance apart from the UART in the ++ * phsyical address space, as the initial mapping for the IO ++ * is done as a 1:1 maping. This puts it (currently) at ++ * 0xFA800000, which is not in the way of any current mapping ++ * by the base system. ++*/ ++ ++#define S3C2410_PA_GPIO (0x56000000) ++#define S3C24XX_VA_GPIO ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) ++#define S3C24XX_SZ_GPIO SZ_1M ++ ++ ++/* ISA style IO, for each machine to sort out mappings for, if it ++ * implements it. We reserve two 16M regions for ISA. ++ */ ++ ++#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000) ++#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000) ++ ++/* deal with the registers that move under the 2412/2413 */ ++ ++#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) ++#ifndef __ASSEMBLY__ ++extern void __iomem *s3c24xx_va_gpio2; ++#endif ++#ifdef CONFIG_CPU_S3C2412_ONLY ++#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10) ++#else ++#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2 ++#endif ++#else ++#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO ++#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO ++#endif ++ ++#endif /* __ASM_PLAT_S3C24XX_MAP_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/mci.h linux-2.6.28.6/arch/arm/plat-s3c24xx/include/plat/mci.h +--- linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/mci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/include/plat/mci.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,15 @@ ++#ifndef _ARCH_MCI_H ++#define _ARCH_MCI_H ++ ++struct s3c24xx_mci_pdata { ++ unsigned int wprotect_invert : 1; ++ unsigned int detect_invert : 1; /* set => detect active high. */ ++ ++ unsigned int gpio_detect; ++ unsigned int gpio_wprotect; ++ unsigned long ocr_avail; ++ void (*set_power)(unsigned char power_mode, ++ unsigned short vdd); ++}; ++ ++#endif /* _ARCH_NCI_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/pll.h linux-2.6.28.6/arch/arm/plat-s3c24xx/include/plat/pll.h +--- linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/pll.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/include/plat/pll.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,37 @@ ++/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h ++ * ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C24xx - common pll registers and code ++ */ ++ ++#define S3C24XX_PLLCON_MDIVSHIFT 12 ++#define S3C24XX_PLLCON_PDIVSHIFT 4 ++#define S3C24XX_PLLCON_SDIVSHIFT 0 ++#define S3C24XX_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1) ++#define S3C24XX_PLLCON_PDIVMASK ((1<<5)-1) ++#define S3C24XX_PLLCON_SDIVMASK 3 ++ ++#include ++ ++static inline unsigned int ++s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk) ++{ ++ unsigned int mdiv, pdiv, sdiv; ++ uint64_t fvco; ++ ++ mdiv = pllval >> S3C24XX_PLLCON_MDIVSHIFT; ++ pdiv = pllval >> S3C24XX_PLLCON_PDIVSHIFT; ++ sdiv = pllval >> S3C24XX_PLLCON_SDIVSHIFT; ++ ++ mdiv &= S3C24XX_PLLCON_MDIVMASK; ++ pdiv &= S3C24XX_PLLCON_PDIVMASK; ++ sdiv &= S3C24XX_PLLCON_SDIVMASK; ++ ++ fvco = (uint64_t)baseclk * (mdiv + 8); ++ do_div(fvco, (pdiv + 2) << sdiv); ++ ++ return (unsigned int)fvco; ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/regs-spi.h linux-2.6.28.6/arch/arm/plat-s3c24xx/include/plat/regs-spi.h +--- linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/regs-spi.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/include/plat/regs-spi.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,82 @@ ++/* arch/arm/mach-s3c2410/include/mach/regs-spi.h ++ * ++ * Copyright (c) 2004 Fetron GmbH ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C2410 SPI register definition ++*/ ++ ++#ifndef __ASM_ARCH_REGS_SPI_H ++#define __ASM_ARCH_REGS_SPI_H ++ ++#define S3C2410_SPI1 (0x20) ++#define S3C2412_SPI1 (0x100) ++ ++#define S3C2410_SPCON (0x00) ++ ++#define S3C2412_SPCON_RXFIFO_RB2 (0<<14) ++#define S3C2412_SPCON_RXFIFO_RB4 (1<<14) ++#define S3C2412_SPCON_RXFIFO_RB12 (2<<14) ++#define S3C2412_SPCON_RXFIFO_RB14 (3<<14) ++#define S3C2412_SPCON_TXFIFO_RB2 (0<<12) ++#define S3C2412_SPCON_TXFIFO_RB4 (1<<12) ++#define S3C2412_SPCON_TXFIFO_RB12 (2<<12) ++#define S3C2412_SPCON_TXFIFO_RB14 (3<<12) ++#define S3C2412_SPCON_RXFIFO_RESET (1<<11) /* RxFIFO reset */ ++#define S3C2412_SPCON_TXFIFO_RESET (1<<10) /* TxFIFO reset */ ++#define S3C2412_SPCON_RXFIFO_EN (1<<9) /* RxFIFO Enable */ ++#define S3C2412_SPCON_TXFIFO_EN (1<<8) /* TxFIFO Enable */ ++ ++#define S3C2412_SPCON_DIRC_RX (1<<7) ++ ++#define S3C2410_SPCON_SMOD_DMA (2<<5) /* DMA mode */ ++#define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */ ++#define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */ ++#define S3C2410_SPCON_ENSCK (1<<4) /* Enable SCK */ ++#define S3C2410_SPCON_MSTR (1<<3) /* Master/Slave select ++ 0: slave, 1: master */ ++#define S3C2410_SPCON_CPOL_HIGH (1<<2) /* Clock polarity select */ ++#define S3C2410_SPCON_CPOL_LOW (0<<2) /* Clock polarity select */ ++ ++#define S3C2410_SPCON_CPHA_FMTB (1<<1) /* Clock Phase Select */ ++#define S3C2410_SPCON_CPHA_FMTA (0<<1) /* Clock Phase Select */ ++ ++#define S3C2410_SPCON_TAGD (1<<0) /* Tx auto garbage data mode */ ++ ++ ++#define S3C2410_SPSTA (0x04) ++ ++#define S3C2412_SPSTA_RXFIFO_AE (1<<11) ++#define S3C2412_SPSTA_TXFIFO_AE (1<<10) ++#define S3C2412_SPSTA_RXFIFO_ERROR (1<<9) ++#define S3C2412_SPSTA_TXFIFO_ERROR (1<<8) ++#define S3C2412_SPSTA_RXFIFO_FIFO (1<<7) ++#define S3C2412_SPSTA_RXFIFO_EMPTY (1<<6) ++#define S3C2412_SPSTA_TXFIFO_NFULL (1<<5) ++#define S3C2412_SPSTA_TXFIFO_EMPTY (1<<4) ++ ++#define S3C2410_SPSTA_DCOL (1<<2) /* Data Collision Error */ ++#define S3C2410_SPSTA_MULD (1<<1) /* Multi Master Error */ ++#define S3C2410_SPSTA_READY (1<<0) /* Data Tx/Rx ready */ ++#define S3C2412_SPSTA_READY_ORG (1<<3) ++ ++#define S3C2410_SPPIN (0x08) ++ ++#define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */ ++#define S3C2410_SPPIN_RESERVED (1<<1) ++#define S3C2400_SPPIN_nCS (1<<1) /* SPI Card Select */ ++#define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */ ++ ++#define S3C2410_SPPRE (0x0C) ++#define S3C2410_SPTDAT (0x10) ++#define S3C2410_SPRDAT (0x14) ++ ++#define S3C2412_TXFIFO (0x18) ++#define S3C2412_RXFIFO (0x18) ++#define S3C2412_SPFIC (0x24) ++ ++ ++#endif /* __ASM_ARCH_REGS_SPI_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/regs-udc.h linux-2.6.28.6/arch/arm/plat-s3c24xx/include/plat/regs-udc.h +--- linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/regs-udc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/include/plat/regs-udc.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,153 @@ ++/* arch/arm/mach-s3c2410/include/mach/regs-udc.h ++ * ++ * Copyright (C) 2004 Herbert Poetzl ++ * ++ * This include file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++*/ ++ ++#ifndef __ASM_ARCH_REGS_UDC_H ++#define __ASM_ARCH_REGS_UDC_H ++ ++#define S3C2410_USBDREG(x) (x) ++ ++#define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140) ++#define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144) ++#define S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148) ++ ++#define S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158) ++#define S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c) ++ ++#define S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c) ++ ++#define S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170) ++#define S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174) ++ ++#define S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0) ++#define S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4) ++#define S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8) ++#define S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc) ++#define S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0) ++ ++#define S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200) ++#define S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204) ++#define S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208) ++#define S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c) ++#define S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210) ++#define S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214) ++ ++#define S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218) ++#define S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c) ++#define S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220) ++#define S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224) ++#define S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228) ++#define S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c) ++ ++#define S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240) ++#define S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244) ++#define S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248) ++#define S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c) ++#define S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250) ++#define S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254) ++ ++#define S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258) ++#define S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c) ++#define S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260) ++#define S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264) ++#define S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268) ++#define S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c) ++ ++#define S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178) ++ ++/* indexed registers */ ++ ++#define S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x0180) ++ ++#define S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184) ++ ++#define S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184) ++#define S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188) ++ ++#define S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190) ++#define S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194) ++#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198) ++#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c) ++ ++#define S3C2410_UDC_FUNCADDR_UPDATE (1<<7) ++ ++#define S3C2410_UDC_PWR_ISOUP (1<<7) // R/W ++#define S3C2410_UDC_PWR_RESET (1<<3) // R ++#define S3C2410_UDC_PWR_RESUME (1<<2) // R/W ++#define S3C2410_UDC_PWR_SUSPEND (1<<1) // R ++#define S3C2410_UDC_PWR_ENSUSPEND (1<<0) // R/W ++ ++#define S3C2410_UDC_PWR_DEFAULT 0x00 ++ ++#define S3C2410_UDC_INT_EP4 (1<<4) // R/W (clear only) ++#define S3C2410_UDC_INT_EP3 (1<<3) // R/W (clear only) ++#define S3C2410_UDC_INT_EP2 (1<<2) // R/W (clear only) ++#define S3C2410_UDC_INT_EP1 (1<<1) // R/W (clear only) ++#define S3C2410_UDC_INT_EP0 (1<<0) // R/W (clear only) ++ ++#define S3C2410_UDC_USBINT_RESET (1<<2) // R/W (clear only) ++#define S3C2410_UDC_USBINT_RESUME (1<<1) // R/W (clear only) ++#define S3C2410_UDC_USBINT_SUSPEND (1<<0) // R/W (clear only) ++ ++#define S3C2410_UDC_INTE_EP4 (1<<4) // R/W ++#define S3C2410_UDC_INTE_EP3 (1<<3) // R/W ++#define S3C2410_UDC_INTE_EP2 (1<<2) // R/W ++#define S3C2410_UDC_INTE_EP1 (1<<1) // R/W ++#define S3C2410_UDC_INTE_EP0 (1<<0) // R/W ++ ++#define S3C2410_UDC_USBINTE_RESET (1<<2) // R/W ++#define S3C2410_UDC_USBINTE_SUSPEND (1<<0) // R/W ++ ++ ++#define S3C2410_UDC_INDEX_EP0 (0x00) ++#define S3C2410_UDC_INDEX_EP1 (0x01) // ?? ++#define S3C2410_UDC_INDEX_EP2 (0x02) // ?? ++#define S3C2410_UDC_INDEX_EP3 (0x03) // ?? ++#define S3C2410_UDC_INDEX_EP4 (0x04) // ?? ++ ++#define S3C2410_UDC_ICSR1_CLRDT (1<<6) // R/W ++#define S3C2410_UDC_ICSR1_SENTSTL (1<<5) // R/W (clear only) ++#define S3C2410_UDC_ICSR1_SENDSTL (1<<4) // R/W ++#define S3C2410_UDC_ICSR1_FFLUSH (1<<3) // W (set only) ++#define S3C2410_UDC_ICSR1_UNDRUN (1<<2) // R/W (clear only) ++#define S3C2410_UDC_ICSR1_PKTRDY (1<<0) // R/W (set only) ++ ++#define S3C2410_UDC_ICSR2_AUTOSET (1<<7) // R/W ++#define S3C2410_UDC_ICSR2_ISO (1<<6) // R/W ++#define S3C2410_UDC_ICSR2_MODEIN (1<<5) // R/W ++#define S3C2410_UDC_ICSR2_DMAIEN (1<<4) // R/W ++ ++#define S3C2410_UDC_OCSR1_CLRDT (1<<7) // R/W ++#define S3C2410_UDC_OCSR1_SENTSTL (1<<6) // R/W (clear only) ++#define S3C2410_UDC_OCSR1_SENDSTL (1<<5) // R/W ++#define S3C2410_UDC_OCSR1_FFLUSH (1<<4) // R/W ++#define S3C2410_UDC_OCSR1_DERROR (1<<3) // R ++#define S3C2410_UDC_OCSR1_OVRRUN (1<<2) // R/W (clear only) ++#define S3C2410_UDC_OCSR1_PKTRDY (1<<0) // R/W (clear only) ++ ++#define S3C2410_UDC_OCSR2_AUTOCLR (1<<7) // R/W ++#define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W ++#define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W ++ ++#define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0) ++#define S3C2410_UDC_EP0_CSR_IPKRDY (1<<1) ++#define S3C2410_UDC_EP0_CSR_SENTSTL (1<<2) ++#define S3C2410_UDC_EP0_CSR_DE (1<<3) ++#define S3C2410_UDC_EP0_CSR_SE (1<<4) ++#define S3C2410_UDC_EP0_CSR_SENDSTL (1<<5) ++#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1<<6) ++#define S3C2410_UDC_EP0_CSR_SSE (1<<7) ++ ++#define S3C2410_UDC_MAXP_8 (1<<0) ++#define S3C2410_UDC_MAXP_16 (1<<1) ++#define S3C2410_UDC_MAXP_32 (1<<2) ++#define S3C2410_UDC_MAXP_64 (1<<3) ++ ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/s3c2400.h linux-2.6.28.6/arch/arm/plat-s3c24xx/include/plat/s3c2400.h +--- linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/s3c2400.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/include/plat/s3c2400.h 2009-04-30 09:36:37.000000000 +0200 +@@ -17,7 +17,7 @@ + + extern int s3c2400_init(void); + +-extern void s3c2400_map_io(struct map_desc *mach_desc, int size); ++extern void s3c2400_map_io(void); + + extern void s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no); + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/s3c2410.h linux-2.6.28.6/arch/arm/plat-s3c24xx/include/plat/s3c2410.h +--- linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/s3c2410.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/include/plat/s3c2410.h 2009-04-30 09:36:37.000000000 +0200 +@@ -15,7 +15,7 @@ + + extern int s3c2410_init(void); + +-extern void s3c2410_map_io(struct map_desc *mach_desc, int size); ++extern void s3c2410_map_io(void); + + extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no); + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/s3c2412.h linux-2.6.28.6/arch/arm/plat-s3c24xx/include/plat/s3c2412.h +--- linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/s3c2412.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/include/plat/s3c2412.h 2009-04-30 09:36:37.000000000 +0200 +@@ -14,7 +14,7 @@ + + extern int s3c2412_init(void); + +-extern void s3c2412_map_io(struct map_desc *mach_desc, int size); ++extern void s3c2412_map_io(void); + + extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no); + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/s3c2443.h linux-2.6.28.6/arch/arm/plat-s3c24xx/include/plat/s3c2443.h +--- linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/s3c2443.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/include/plat/s3c2443.h 2009-04-30 09:36:37.000000000 +0200 +@@ -16,7 +16,7 @@ + + extern int s3c2443_init(void); + +-extern void s3c2443_map_io(struct map_desc *mach_desc, int size); ++extern void s3c2443_map_io(void); + + extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no); + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/udc.h linux-2.6.28.6/arch/arm/plat-s3c24xx/include/plat/udc.h +--- linux-2.6.28/arch/arm/plat-s3c24xx/include/plat/udc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/include/plat/udc.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,36 @@ ++/* arch/arm/mach-s3c2410/include/mach/udc.h ++ * ++ * Copyright (c) 2005 Arnaud Patard ++ * ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * ++ * Changelog: ++ * 14-Mar-2005 RTP Created file ++ * 02-Aug-2005 RTP File rename ++ * 07-Sep-2005 BJD Minor cleanups, changed cmd to enum ++ * 18-Jan-2007 HMW Add per-platform vbus_draw function ++*/ ++ ++#ifndef __ASM_ARM_ARCH_UDC_H ++#define __ASM_ARM_ARCH_UDC_H ++ ++enum s3c2410_udc_cmd_e { ++ S3C2410_UDC_P_ENABLE = 1, /* Pull-up enable */ ++ S3C2410_UDC_P_DISABLE = 2, /* Pull-up disable */ ++ S3C2410_UDC_P_RESET = 3, /* UDC reset, in case of */ ++}; ++ ++struct s3c2410_udc_mach_info { ++ void (*udc_command)(enum s3c2410_udc_cmd_e); ++ void (*vbus_draw)(unsigned int ma); ++ unsigned int vbus_pin; ++ unsigned char vbus_pin_inverted; ++}; ++ ++extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *); ++ ++#endif /* __ASM_ARM_ARCH_UDC_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/irq.c linux-2.6.28.6/arch/arm/plat-s3c24xx/irq.c +--- linux-2.6.28/arch/arm/plat-s3c24xx/irq.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/irq.c 2009-04-30 09:36:37.000000000 +0200 +@@ -62,6 +62,7 @@ + + #include + ++#include + #include + #include + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/pm.c linux-2.6.28.6/arch/arm/plat-s3c24xx/pm.c +--- linux-2.6.28/arch/arm/plat-s3c24xx/pm.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/pm.c 2009-04-30 09:36:37.000000000 +0200 +@@ -76,11 +76,13 @@ + SAVE_ITEM(S3C2410_BANKCON4), + SAVE_ITEM(S3C2410_BANKCON5), + ++#ifndef CONFIG_CPU_FREQ + SAVE_ITEM(S3C2410_CLKDIVN), + SAVE_ITEM(S3C2410_MPLLCON), ++ SAVE_ITEM(S3C2410_REFRESH), ++#endif + SAVE_ITEM(S3C2410_UPLLCON), + SAVE_ITEM(S3C2410_CLKSLOW), +- SAVE_ITEM(S3C2410_REFRESH), + }; + + static struct gpio_sleep { +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/s3c2410-clock.c linux-2.6.28.6/arch/arm/plat-s3c24xx/s3c2410-clock.c +--- linux-2.6.28/arch/arm/plat-s3c24xx/s3c2410-clock.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/s3c2410-clock.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,276 @@ ++/* linux/arch/arm/mach-s3c2410/clock.c ++ * ++ * Copyright (c) 2006 Simtec Electronics ++ * Ben Dooks ++ * ++ * S3C2410,S3C2440,S3C2442 Clock control support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++int s3c2410_clkcon_enable(struct clk *clk, int enable) ++{ ++ unsigned int clocks = clk->ctrlbit; ++ unsigned long clkcon; ++ ++ clkcon = __raw_readl(S3C2410_CLKCON); ++ ++ if (enable) ++ clkcon |= clocks; ++ else ++ clkcon &= ~clocks; ++ ++ /* ensure none of the special function bits set */ ++ clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER); ++ ++ __raw_writel(clkcon, S3C2410_CLKCON); ++ ++ return 0; ++} ++ ++static int s3c2410_upll_enable(struct clk *clk, int enable) ++{ ++ unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW); ++ unsigned long orig = clkslow; ++ ++ if (enable) ++ clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF; ++ else ++ clkslow |= S3C2410_CLKSLOW_UCLK_OFF; ++ ++ __raw_writel(clkslow, S3C2410_CLKSLOW); ++ ++ /* if we started the UPLL, then allow to settle */ ++ ++ if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF)) ++ udelay(200); ++ ++ return 0; ++} ++ ++/* standard clock definitions */ ++ ++static struct clk init_clocks_disable[] = { ++ { ++ .name = "nand", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s3c2410_clkcon_enable, ++ .ctrlbit = S3C2410_CLKCON_NAND, ++ }, { ++ .name = "sdi", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s3c2410_clkcon_enable, ++ .ctrlbit = S3C2410_CLKCON_SDI, ++ }, { ++ .name = "adc", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s3c2410_clkcon_enable, ++ .ctrlbit = S3C2410_CLKCON_ADC, ++ }, { ++ .name = "i2c", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s3c2410_clkcon_enable, ++ .ctrlbit = S3C2410_CLKCON_IIC, ++ }, { ++ .name = "iis", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s3c2410_clkcon_enable, ++ .ctrlbit = S3C2410_CLKCON_IIS, ++ }, { ++ .name = "spi", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s3c2410_clkcon_enable, ++ .ctrlbit = S3C2410_CLKCON_SPI, ++ } ++}; ++ ++static struct clk init_clocks[] = { ++ { ++ .name = "lcd", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s3c2410_clkcon_enable, ++ .ctrlbit = S3C2410_CLKCON_LCDC, ++ }, { ++ .name = "gpio", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s3c2410_clkcon_enable, ++ .ctrlbit = S3C2410_CLKCON_GPIO, ++ }, { ++ .name = "usb-host", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s3c2410_clkcon_enable, ++ .ctrlbit = S3C2410_CLKCON_USBH, ++ }, { ++ .name = "usb-device", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s3c2410_clkcon_enable, ++ .ctrlbit = S3C2410_CLKCON_USBD, ++ }, { ++ .name = "timers", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s3c2410_clkcon_enable, ++ .ctrlbit = S3C2410_CLKCON_PWMT, ++ }, { ++ .name = "uart", ++ .id = 0, ++ .parent = &clk_p, ++ .enable = s3c2410_clkcon_enable, ++ .ctrlbit = S3C2410_CLKCON_UART0, ++ }, { ++ .name = "uart", ++ .id = 1, ++ .parent = &clk_p, ++ .enable = s3c2410_clkcon_enable, ++ .ctrlbit = S3C2410_CLKCON_UART1, ++ }, { ++ .name = "uart", ++ .id = 2, ++ .parent = &clk_p, ++ .enable = s3c2410_clkcon_enable, ++ .ctrlbit = S3C2410_CLKCON_UART2, ++ }, { ++ .name = "rtc", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s3c2410_clkcon_enable, ++ .ctrlbit = S3C2410_CLKCON_RTC, ++ }, { ++ .name = "watchdog", ++ .id = -1, ++ .parent = &clk_p, ++ .ctrlbit = 0, ++ }, { ++ .name = "usb-bus-host", ++ .id = -1, ++ .parent = &clk_usb_bus, ++ }, { ++ .name = "usb-bus-gadget", ++ .id = -1, ++ .parent = &clk_usb_bus, ++ }, ++}; ++ ++/* s3c2410_baseclk_add() ++ * ++ * Add all the clocks used by the s3c2410 or compatible CPUs ++ * such as the S3C2440 and S3C2442. ++ * ++ * We cannot use a system device as we are needed before any ++ * of the init-calls that initialise the devices are actually ++ * done. ++*/ ++ ++int __init s3c2410_baseclk_add(void) ++{ ++ unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW); ++ unsigned long clkcon = __raw_readl(S3C2410_CLKCON); ++ struct clk *clkp; ++ struct clk *xtal; ++ int ret; ++ int ptr; ++ ++ clk_upll.enable = s3c2410_upll_enable; ++ ++ if (s3c24xx_register_clock(&clk_usb_bus) < 0) ++ printk(KERN_ERR "failed to register usb bus clock\n"); ++ ++ /* register clocks from clock array */ ++ ++ clkp = init_clocks; ++ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { ++ /* ensure that we note the clock state */ ++ ++ clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0; ++ ++ ret = s3c24xx_register_clock(clkp); ++ if (ret < 0) { ++ printk(KERN_ERR "Failed to register clock %s (%d)\n", ++ clkp->name, ret); ++ } ++ } ++ ++ /* We must be careful disabling the clocks we are not intending to ++ * be using at boot time, as subsystems such as the LCD which do ++ * their own DMA requests to the bus can cause the system to lockup ++ * if they where in the middle of requesting bus access. ++ * ++ * Disabling the LCD clock if the LCD is active is very dangerous, ++ * and therefore the bootloader should be careful to not enable ++ * the LCD clock if it is not needed. ++ */ ++ ++ /* install (and disable) the clocks we do not need immediately */ ++ ++ clkp = init_clocks_disable; ++ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { ++ ++ ret = s3c24xx_register_clock(clkp); ++ if (ret < 0) { ++ printk(KERN_ERR "Failed to register clock %s (%d)\n", ++ clkp->name, ret); ++ } ++ ++ s3c2410_clkcon_enable(clkp, 0); ++ } ++ ++ /* show the clock-slow value */ ++ ++ xtal = clk_get(NULL, "xtal"); ++ ++ printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n", ++ print_mhz(clk_get_rate(xtal) / ++ ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))), ++ (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast", ++ (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on", ++ (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on"); ++ ++ return 0; ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/s3c244x-clock.c linux-2.6.28.6/arch/arm/plat-s3c24xx/s3c244x-clock.c +--- linux-2.6.28/arch/arm/plat-s3c24xx/s3c244x-clock.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/s3c244x-clock.c 2009-04-30 09:36:37.000000000 +0200 +@@ -31,7 +31,6 @@ + #include + #include + #include +-#include + #include + #include + +@@ -102,13 +101,13 @@ + if (clk_get_rate(clock_upll) > (94 * MHZ)) { + clk_usb_bus.rate = clk_get_rate(clock_upll) / 2; + +- mutex_lock(&clocks_mutex); ++ spin_lock(&clocks_lock); + + clkdivn = __raw_readl(S3C2410_CLKDIVN); + clkdivn |= S3C2440_CLKDIVN_UCLK; + __raw_writel(clkdivn, S3C2410_CLKDIVN); + +- mutex_unlock(&clocks_mutex); ++ spin_unlock(&clocks_lock); + } + + return 0; +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/s3c244x.c linux-2.6.28.6/arch/arm/plat-s3c24xx/s3c244x.c +--- linux-2.6.28/arch/arm/plat-s3c24xx/s3c244x.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/s3c244x.c 2009-04-30 09:36:37.000000000 +0200 +@@ -29,6 +29,8 @@ + #include + #include + ++#include ++ + #include + #include + #include +@@ -42,6 +44,7 @@ + #include + #include + #include ++#include + + static struct map_desc s3c244x_iodesc[] __initdata = { + IODESC_ENT(CLKPWR), +@@ -56,32 +59,34 @@ + s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no); + } + +-void __init s3c244x_map_io(struct map_desc *mach_desc, int size) ++void __init s3c244x_map_io(void) + { + /* register our io-tables */ + + iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc)); +- iotable_init(mach_desc, size); + + /* rename any peripherals used differing from the s3c2410 */ + + s3c_device_sdi.name = "s3c2440-sdi"; +- s3c_device_i2c.name = "s3c2440-i2c"; ++ s3c_device_i2c0.name = "s3c2440-i2c"; + s3c_device_nand.name = "s3c2440-nand"; + s3c_device_usbgadget.name = "s3c2440-usbgadget"; + } + +-void __init s3c244x_init_clocks(int xtal) ++void __init_or_cpufreq s3c244x_setup_clocks(void) + { ++ struct clk *xtal_clk; + unsigned long clkdiv; + unsigned long camdiv; ++ unsigned long xtal; + unsigned long hclk, fclk, pclk; + int hdiv = 1; + +- /* now we've got our machine bits initialised, work out what +- * clocks we've got */ ++ xtal_clk = clk_get(NULL, "xtal"); ++ xtal = clk_get_rate(xtal_clk); ++ clk_put(xtal_clk); + +- fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2; ++ fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2; + + clkdiv = __raw_readl(S3C2410_CLKDIVN); + camdiv = __raw_readl(S3C2440_CAMDIVN); +@@ -107,18 +112,24 @@ + } + + hclk = fclk / hdiv; +- pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1); ++ pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1); + + /* print brief summary of clocks, etc */ + + printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", + print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); + ++ s3c24xx_setup_clocks(fclk, hclk, pclk); ++} ++ ++void __init s3c244x_init_clocks(int xtal) ++{ + /* initialise the clocks here, to allow other things like the + * console to use them, and to add new ones after the initialisation + */ + +- s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); ++ s3c24xx_register_baseclocks(xtal); ++ s3c244x_setup_clocks(); + s3c2410_baseclk_add(); + } + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/s3c244x.h linux-2.6.28.6/arch/arm/plat-s3c24xx/s3c244x.h +--- linux-2.6.28/arch/arm/plat-s3c24xx/s3c244x.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/s3c244x.h 2009-04-30 09:36:37.000000000 +0200 +@@ -12,7 +12,7 @@ + + #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) + +-extern void s3c244x_map_io(struct map_desc *mach_desc, int size); ++extern void s3c244x_map_io(void); + + extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no); + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/setup-i2c.c linux-2.6.28.6/arch/arm/plat-s3c24xx/setup-i2c.c +--- linux-2.6.28/arch/arm/plat-s3c24xx/setup-i2c.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/setup-i2c.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,25 @@ ++/* linux/arch/arm/plat-s3c24xx/setup-i2c.c ++ * ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * ++ * S3C24XX Base setup for i2c device ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++ ++struct platform_device; ++ ++#include ++#include ++#include ++ ++void s3c_i2c0_cfg_gpio(struct platform_device *dev) ++{ ++ s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA); ++ s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL); ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c linux-2.6.28.6/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c +--- linux-2.6.28/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,37 @@ ++/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c ++ * ++ * Copyright (c) 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S3C24XX SPI - gpio configuration for bus 0 on gpe11,12,13 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License. ++*/ ++ ++#include ++ ++#include ++ ++#include ++#include ++ ++void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi, ++ int enable) ++{ ++ if (enable) { ++ s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPE13_SPICLK0); ++ s3c2410_gpio_cfgpin(S3C2410_GPE12, S3C2410_GPE12_SPIMOSI0); ++ s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPE11_SPIMISO0); ++ s3c2410_gpio_pullup(S3C2410_GPE11, 0); ++ s3c2410_gpio_pullup(S3C2410_GPE13, 0); ++ } else { ++ s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPIO_INPUT); ++ s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPIO_INPUT); ++ s3c2410_gpio_pullup(S3C2410_GPE11, 1); ++ s3c2410_gpio_pullup(S3C2410_GPE12, 1); ++ s3c2410_gpio_pullup(S3C2410_GPE13, 1); ++ } ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c linux-2.6.28.6/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c +--- linux-2.6.28/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,37 @@ ++/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpg5_6_7.c ++ * ++ * Copyright (c) 2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * ++ * S3C24XX SPI - gpio configuration for bus 1 on gpg5,6,7 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License. ++*/ ++ ++#include ++ ++#include ++ ++#include ++#include ++ ++void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi, ++ int enable) ++{ ++ if (enable) { ++ s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPG7_SPICLK1); ++ s3c2410_gpio_cfgpin(S3C2410_GPG6, S3C2410_GPG6_SPIMOSI1); ++ s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPG5_SPIMISO1); ++ s3c2410_gpio_pullup(S3C2410_GPG5, 0); ++ s3c2410_gpio_pullup(S3C2410_GPG6, 0); ++ } else { ++ s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPIO_INPUT); ++ s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPIO_INPUT); ++ s3c2410_gpio_pullup(S3C2410_GPG5, 1); ++ s3c2410_gpio_pullup(S3C2410_GPG6, 1); ++ s3c2410_gpio_pullup(S3C2410_GPG7, 1); ++ } ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/Kconfig linux-2.6.28.6/arch/arm/plat-s3c64xx/Kconfig +--- linux-2.6.28/arch/arm/plat-s3c64xx/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/Kconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,107 @@ ++# arch/arm/plat-s3c64xx/Kconfig ++# ++# Copyright 2008 Openmoko, Inc. ++# Copyright 2008 Simtec Electronics ++# Ben Dooks ++# ++# Licensed under GPLv2 ++ ++config PLAT_S3C64XX ++ bool ++ depends on ARCH_S3C64XX ++ select PLAT_S3C ++ select ARM_VIC ++ default y ++ select NO_IOPORT ++ select ARCH_REQUIRE_GPIOLIB ++ select S3C_GPIO_TRACK ++ select S3C_GPIO_PULL_UPDOWN ++ select S3C_GPIO_CFG_S3C24XX ++ select S3C_GPIO_CFG_S3C64XX ++ select DMABOUNCE ++ help ++ Base platform code for any Samsung S3C64XX device ++ ++if PLAT_S3C64XX ++ ++# Configuration options shared by all S3C64XX implementations ++ ++config CPU_S3C6400_INIT ++ bool ++ help ++ Common initialisation code for the S3C6400 that is shared ++ by other CPUs in the series, such as the S3C6410. ++ ++config CPU_S3C6400_CLOCK ++ bool ++ help ++ Common clock support code for the S3C6400 that is shared ++ by other CPUs in the series, such as the S3C6410. ++ ++# platform specific device setup ++ ++config S3C64XX_SETUP_I2C0 ++ bool ++ default y ++ help ++ Common setup code for i2c bus 0. ++ ++ Note, currently since i2c0 is always compiled, this setup helper ++ is always compiled with it. ++ ++config S3C64XX_SETUP_I2C1 ++ bool ++ help ++ Common setup code for i2c bus 1. ++ ++config S3C64XX_ADC ++ bool "S3C64XX ADC D/D support" ++ help ++ Analog to Digital conversion(ADC) D/D for S3C64XX support ++ ++config S3C64XX_DEV_FIMC0 ++ bool ++ default y ++ help ++ Compile in platform device definitions for FIMC controller 0 ++ ++config S3C64XX_DEV_FIMC1 ++ bool ++ default y ++ help ++ Compile in platform device definitions for FIMC controller 1 ++ ++config S3C64XX_SETUP_FIMC0 ++ bool ++ default y ++ help ++ Common setup code for FIMC controller 0 ++ ++config S3C64XX_SETUP_FIMC1 ++ bool ++ default y ++ help ++ Common setup code for FIMC controller 1 ++ ++choice ++ prompt "PWM device support" ++ default NONE_PWM ++ ++config S3C6410_PWM ++ bool "Support Old API" ++ help ++ Support for exporting the PWM timer blocks via old type API ++ ++config HAVE_PWM ++ bool "PWM device support" ++ help ++ Support for exporting the PWM timer blocks via the pwm device ++ ++config NONE_PWM ++ bool "No PWM support" ++ help ++ PWM is not supported ++ ++endchoice ++ ++endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/Makefile linux-2.6.28.6/arch/arm/plat-s3c64xx/Makefile +--- linux-2.6.28/arch/arm/plat-s3c64xx/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/Makefile 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,43 @@ ++# arch/arm/plat-s3c64xx/Makefile ++# ++# Copyright 2008 Openmoko, Inc. ++# Copyright 2008 Simtec Electronics ++# ++# Licensed under GPLv2 ++ ++obj-y := ++obj-m := ++obj-n := dummy.o ++obj- := ++ ++# Core files ++ ++obj-y += dev-uart.o devs.o ++obj-y += cpu.o ++obj-y += irq.o ++obj-y += irq-eint.o ++obj-y += irq-eint-group.o ++obj-y += clock.o ++obj-y += gpiolib.o ++obj-y += bootmem.o ++ ++# CPU support ++ ++obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o ++obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o ++obj-$(CONFIG_CPU_FREQ) += s3c64xx-cpufreq.o ltc3714.o ++obj-$(CONFIG_PM) += pm.o ++obj-$(CONFIG_PM) += sleep.o ++ ++# Device setup ++ ++obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o ++obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o ++obj-$(CONFIG_S3C64XX_ADC) += adc.o ++ ++obj-$(CONFIG_S3C64XX_DEV_FIMC0) += dev-fimc0.o ++obj-$(CONFIG_S3C64XX_DEV_FIMC1) += dev-fimc1.o ++obj-$(CONFIG_S3C64XX_SETUP_FIMC0) += setup-fimc0.o ++obj-$(CONFIG_S3C64XX_SETUP_FIMC1) += setup-fimc1.o ++obj-$(CONFIG_HAVE_PWM) += pwm.o ++obj-$(CONFIG_S3C6410_PWM) += pwm-s3c6410.o +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/adc.c linux-2.6.28.6/arch/arm/plat-s3c64xx/adc.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/adc.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/adc.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,370 @@ ++/* linux/arch/arm/plat-s3c64xx/adc.c ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * Copyright (c) 2004 Arnaud Patard ++ * iPAQ H1940 touchscreen support ++ * ++ * ChangeLog ++ * ++ * 2004-09-05: Herbert Pötzl ++ * - added clock (de-)allocation code ++ * ++ * 2005-03-06: Arnaud Patard ++ * - h1940_ -> s3c24xx (this driver is now also used on the n30 ++ * machines :P) ++ * - Debug messages are now enabled with the config option ++ * TOUCHSCREEN_S3C_DEBUG ++ * - Changed the way the value are read ++ * - Input subsystem should now work ++ * - Use ioremap and readl/writel ++ * ++ * 2005-03-23: Arnaud Patard ++ * - Make use of some undocumented features of the touchscreen ++ * controller ++ * ++ */ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#define ADC_MINOR 131 ++#define ADC_INPUT_PIN _IOW('S', 0x0c, unsigned long) ++ ++#define ADC_WITH_TOUCHSCREEN ++ ++static struct clk *adc_clock; ++ ++static void __iomem *base_addr; ++static int adc_port = 0; ++struct s3c_adc_mach_info *plat_data; ++ ++ ++#ifdef ADC_WITH_TOUCHSCREEN ++static DEFINE_MUTEX(adc_mutex); ++ ++static unsigned long data_for_ADCCON; ++static unsigned long data_for_ADCTSC; ++ ++static void s3c_adc_save_SFR_on_ADC(void) ++{ ++ data_for_ADCCON = readl(base_addr + S3C_ADCCON); ++ data_for_ADCTSC = readl(base_addr + S3C_ADCTSC); ++} ++ ++static void s3c_adc_restore_SFR_on_ADC(void) ++{ ++ writel(data_for_ADCCON, base_addr + S3C_ADCCON); ++ writel(data_for_ADCTSC, base_addr + S3C_ADCTSC); ++} ++#else ++static struct resource *adc_mem; ++#endif ++ ++static int s3c_adc_open(struct inode *inode, struct file *file) ++{ ++ printk(KERN_INFO " s3c_adc_open() entered\n"); ++ return 0; ++} ++ ++unsigned int s3c_adc_convert(void) ++{ ++ unsigned int adc_return = 0; ++ unsigned long data0; ++ unsigned long data1; ++ ++ writel(readl(base_addr + S3C_ADCCON) | S3C_ADCCON_SELMUX(adc_port), base_addr + S3C_ADCCON); ++ ++ udelay(10); ++ ++ writel(readl(base_addr + S3C_ADCCON) | S3C_ADCCON_ENABLE_START, base_addr + S3C_ADCCON); ++ ++ do { ++ data0 = readl(base_addr + S3C_ADCCON); ++ } while(!(data0 & S3C_ADCCON_ECFLG)); ++ ++ data1 = readl(base_addr + S3C_ADCDAT0); ++ ++ if (plat_data->resolution == 12) ++ adc_return = data1 & S3C_ADCDAT0_XPDATA_MASK_12BIT; ++ else ++ adc_return = data1 & S3C_ADCDAT0_XPDATA_MASK; ++ ++ return adc_return; ++} ++ ++ ++int s3c_adc_get(struct s3c_adc_request *req) ++{ ++ unsigned adc_channel = req->channel; ++ int adc_value_ret = 0; ++ ++ adc_value_ret = s3c_adc_convert(); ++ ++ req->callback(adc_channel,req->param, adc_value_ret); ++ ++ return 0; ++} ++EXPORT_SYMBOL(s3c_adc_get); ++ ++ ++static ssize_t ++s3c_adc_read(struct file *file, char __user * buffer, ++ size_t size, loff_t * pos) ++{ ++ int adc_value = 0; ++ ++ printk(KERN_INFO " s3c_adc_read() entered\n"); ++ ++#ifdef ADC_WITH_TOUCHSCREEN ++ mutex_lock(&adc_mutex); ++ s3c_adc_save_SFR_on_ADC(); ++#endif ++ ++ adc_value = s3c_adc_convert(); ++ ++#ifdef ADC_WITH_TOUCHSCREEN ++ s3c_adc_restore_SFR_on_ADC(); ++ mutex_unlock(&adc_mutex); ++#endif ++ ++ printk(KERN_INFO " Converted Value: %03d\n", adc_value); ++ ++ if (copy_to_user(buffer, &adc_value, sizeof(unsigned int))) { ++ return -EFAULT; ++ } ++ return sizeof(unsigned int); ++} ++ ++ ++static int s3c_adc_ioctl(struct inode *inode, struct file *file, ++ unsigned int cmd, unsigned long arg) ++{ ++ ++ printk(KERN_INFO " s3c_adc_ioctl(cmd:: %d) entered\n", cmd); ++ ++ switch (cmd) { ++ case ADC_INPUT_PIN: ++ adc_port = (unsigned int) arg; ++ ++ if (adc_port >= 4) ++ printk(" %d is already reserved for TouchScreen\n", adc_port); ++ return 0; ++ ++ default: ++ return -ENOIOCTLCMD; ++ } ++} ++ ++static struct file_operations s3c_adc_fops = { ++ .owner = THIS_MODULE, ++ .read = s3c_adc_read, ++ .open = s3c_adc_open, ++ .ioctl = s3c_adc_ioctl, ++}; ++ ++static struct miscdevice s3c_adc_miscdev = { ++ .minor = ADC_MINOR, ++ .name = "adc", ++ .fops = &s3c_adc_fops, ++}; ++ ++static struct s3c_adc_mach_info *s3c_adc_get_platdata(struct device *dev) ++{ ++ if(dev->platform_data != NULL) ++ { ++ return (struct s3c_adc_mach_info*) dev->platform_data; ++ } else { ++ printk(KERN_INFO "No ADC platform data \n"); ++ return 0; ++ } ++} ++ ++/* ++ * The functions for inserting/removing us as a module. ++ */ ++ ++static int __init s3c_adc_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ struct device *dev; ++ int ret; ++ int size; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ dev = &pdev->dev; ++ ++ if(res == NULL){ ++ dev_err(dev,"no memory resource specified\n"); ++ return -ENOENT; ++ } ++ ++ size = (res->end - res->start) + 1; ++ ++#if !defined(ADC_WITH_TOUCHSCREEN) ++ adc_mem = request_mem_region(res->start, size, pdev->name); ++ if(adc_mem == NULL){ ++ dev_err(dev, "failed to get memory region\n"); ++ ret = -ENOENT; ++ goto err_req; ++ } ++#endif ++ ++ base_addr = ioremap(res->start, size); ++ if(base_addr == NULL){ ++ dev_err(dev,"fail to ioremap() region\n"); ++ ret = -ENOENT; ++ goto err_map; ++ } ++ ++ adc_clock = clk_get(&pdev->dev, "adc"); ++ ++ if(IS_ERR(adc_clock)){ ++ dev_err(dev,"failed to fine ADC clock source\n"); ++ ret = PTR_ERR(adc_clock); ++ goto err_clk; ++ } ++ ++ clk_enable(adc_clock); ++ ++ /* read platform data from device struct */ ++ plat_data = s3c_adc_get_platdata(&pdev->dev); ++ ++ if ((plat_data->presc & 0xff) > 0) ++ writel(S3C_ADCCON_PRSCEN | S3C_ADCCON_PRSCVL(plat_data->presc & 0xff), base_addr + S3C_ADCCON); ++ else ++ writel(0, base_addr + S3C_ADCCON); ++ ++ /* Initialise registers */ ++ if ((plat_data->delay & 0xffff) > 0) ++ writel(plat_data->delay & 0xffff, base_addr + S3C_ADCDLY); ++ ++ if (plat_data->resolution == 12) ++ writel(readl(base_addr + S3C_ADCCON) | S3C_ADCCON_RESSEL_12BIT, base_addr + S3C_ADCCON); ++ ++ ret = misc_register(&s3c_adc_miscdev); ++ if (ret) { ++ printk (KERN_ERR "cannot register miscdev on minor=%d (%d)\n", ++ ADC_MINOR, ret); ++ goto err_clk; ++ } ++ ++ printk(KERN_INFO "S5P64XX ADC driver successfully probed\n"); ++ ++ return 0; ++ ++err_clk: ++ clk_disable(adc_clock); ++ clk_put(adc_clock); ++ ++err_map: ++ iounmap(base_addr); ++ ++#if !defined(ADC_WITH_TOUCHSCREEN) ++err_req: ++ release_resource(adc_mem); ++ kfree(adc_mem); ++#endif ++ ++ return ret; ++} ++ ++ ++static int s3c_adc_remove(struct platform_device *dev) ++{ ++ printk(KERN_INFO "s3c_adc_remove() of ADC called !\n"); ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static unsigned int adccon, adctsc, adcdly; ++ ++static int s3c_adc_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ adccon = readl(base_addr + S3C_ADCCON); ++ adctsc = readl(base_addr + S3C_ADCTSC); ++ adcdly = readl(base_addr + S3C_ADCDLY); ++ ++ clk_disable(adc_clock); ++ ++ return 0; ++} ++ ++static int s3c_adc_resume(struct platform_device *pdev) ++{ ++ clk_enable(adc_clock); ++ ++ writel(adccon, base_addr + S3C_ADCCON); ++ writel(adctsc, base_addr + S3C_ADCTSC); ++ writel(adcdly, base_addr + S3C_ADCDLY); ++ ++ return 0; ++} ++#else ++#define s3c_adc_suspend NULL ++#define s3c_adc_resume NULL ++#endif ++ ++static struct platform_driver s3c_adc_driver = { ++ .probe = s3c_adc_probe, ++ .remove = s3c_adc_remove, ++ .suspend = s3c_adc_suspend, ++ .resume = s3c_adc_resume, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "s3c-adc", ++ }, ++}; ++ ++static char banner[] __initdata = KERN_INFO "S3C64XX ADC driver, (c) 2008 Samsung Electronics\n"; ++ ++int __init s3c_adc_init(void) ++{ ++ printk(banner); ++ return platform_driver_register(&s3c_adc_driver); ++} ++ ++void __exit s3c_adc_exit(void) ++{ ++ platform_driver_unregister(&s3c_adc_driver); ++} ++ ++module_init(s3c_adc_init); ++module_exit(s3c_adc_exit); ++ ++MODULE_AUTHOR("boyko.lee@samsung.com"); ++MODULE_DESCRIPTION("S3C64XX ADC driver"); ++MODULE_LICENSE("GPL"); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/bootmem.c linux-2.6.28.6/arch/arm/plat-s3c64xx/bootmem.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/bootmem.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/bootmem.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,175 @@ ++/* linux/arch/arm/plat-s5pc1xx/bootmem.c ++ * ++ * Copyright 2009 Samsung Electronics ++ * Jinsung Yang ++ * http://samsungsemi.com/ ++ * ++ * Bootmem helper functions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "plat/media.h" ++ ++static struct s3c_media_device s3c_mdevs[S3C_MDEV_MAX] = { ++ { ++ .id = S3C_MDEV_FIMC, ++ .name = "fimc", ++ ++#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC ++ .memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC * SZ_1K, ++#else ++ .memsize = 0, ++#endif ++ .paddr = 0, ++ }, ++ ++ { ++ .id = S3C_MDEV_POST, ++ .name = "pp", ++ ++#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_POST ++ .memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_POST * SZ_1K, ++#else ++ .memsize = 0, ++#endif ++ .paddr = 0, ++ }, ++ ++ { ++ .id = S3C_MDEV_TV, ++ .name = "tv", ++ ++#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV ++ .memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV * SZ_1K, ++#else ++ .memsize = 0, ++#endif ++ .paddr = 0, ++ }, ++ ++ { ++ .id = S3C_MDEV_MFC, ++ .name = "mfc", ++ ++#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC ++ .memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC * SZ_1K, ++#else ++ .memsize = 0, ++#endif ++ .paddr = 0, ++ }, ++ ++ { ++ .id = S3C_MDEV_JPEG, ++ .name = "jpeg", ++ ++#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG ++ .memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG * SZ_1K, ++#else ++ .memsize = 0, ++#endif ++ .paddr = 0, ++ }, ++ ++ { ++ .id = S3C_MDEV_CMM, ++ .name = "cmm", ++ ++#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_CMM ++ .memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_CMM * SZ_1K, ++#else ++ .memsize = 0, ++#endif ++ .paddr = 0, ++ } ++}; ++ ++static struct s3c_media_device *s3c_get_media_device(int dev_id) ++{ ++ struct s3c_media_device *mdev = NULL; ++ int i, found; ++ ++ if (dev_id < 0 || dev_id >= S3C_MDEV_MAX) ++ return NULL; ++ ++ i = 0; ++ found = 0; ++ while (!found && (i < S3C_MDEV_MAX)) { ++ mdev = &s3c_mdevs[i]; ++ if (mdev->id == dev_id) ++ found = 1; ++ else ++ i++; ++ } ++ ++ if (!found) ++ mdev = NULL; ++ ++ return mdev; ++} ++ ++dma_addr_t s3c_get_media_memory(int dev_id) ++{ ++ struct s3c_media_device *mdev; ++ ++ mdev = s3c_get_media_device(dev_id); ++ if (!mdev){ ++ printk(KERN_ERR "invalid media device\n"); ++ return 0; ++ } ++ ++ if (!mdev->paddr) { ++ printk(KERN_ERR "no memory for %s\n", mdev->name); ++ return 0; ++ } ++ ++ return mdev->paddr; ++} ++ ++size_t s3c_get_media_memsize(int dev_id) ++{ ++ struct s3c_media_device *mdev; ++ ++ mdev = s3c_get_media_device(dev_id); ++ if (!mdev){ ++ printk(KERN_ERR "invalid media device\n"); ++ return 0; ++ } ++ ++ return mdev->memsize; ++} ++ ++void s3c64xx_reserve_bootmem(void) ++{ ++ struct s3c_media_device *mdev; ++ int i; ++ ++ for(i = 0; i < sizeof(s3c_mdevs) / sizeof(s3c_mdevs[0]); i++) { ++ mdev = &s3c_mdevs[i]; ++ if (mdev->memsize > 0) { ++ mdev->paddr = virt_to_phys(alloc_bootmem_low(mdev->memsize)); ++ printk(KERN_INFO \ ++ "s3c64xx: %lu bytes SDRAM reserved " ++ "for %s at 0x%08x\n", ++ (unsigned long) mdev->memsize, \ ++ mdev->name, mdev->paddr); ++ } ++ } ++} ++ ++/* FIXME: temporary implementation to avoid compile error */ ++int dma_needs_bounce(struct device *dev, dma_addr_t addr, size_t size) ++{ ++ return 0; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/clock.c linux-2.6.28.6/arch/arm/plat-s3c64xx/clock.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/clock.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/clock.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,464 @@ ++/* linux/arch/arm/plat-s3c64xx/clock.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C64XX Base clock support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++/* definition for cpu freq */ ++ ++#define ARM_PLL_CON S3C_APLL_CON ++#define ARM_CLK_DIV S3C_CLK_DIV0 ++ ++#define ARM_DIV_RATIO_BIT 0 ++#define ARM_DIV_MASK (0xf<> 16) & 0x3ff; ++ p = (apll_con >> 8) & 0x3f; ++ s = apll_con & 0x3; ++ ++ ret = (m * (INIT_XTAL / (p * (1 << s)))); ++ ++ return (ret / (clk_div0_tmp + 1)); ++} ++ ++unsigned long s3c_fclk_round_rate(struct clk *clk, unsigned long rate) ++{ ++ u32 iter; ++ ++ for(iter = 1 ; iter < ARRAY_SIZE(s3c_cpu_clock_table) ; iter++){ ++ if(rate > s3c_cpu_clock_table[iter][0]) ++ return s3c_cpu_clock_table[iter-1][0]; ++ } ++ ++ return s3c_cpu_clock_table[ARRAY_SIZE(s3c_cpu_clock_table) - 1][0]; ++} ++ ++int s3c_fclk_set_rate(struct clk *clk, unsigned long rate) ++{ ++ u32 round_tmp; ++ u32 iter; ++ u32 clk_div0_tmp; ++ ++ round_tmp = s3c_fclk_round_rate(clk,rate); ++ ++ if(round_tmp == (int)s3c_fclk_get_rate()) ++ return 0; ++ ++ ++ for (iter = 0 ; iter < ARRAY_SIZE(s3c_cpu_clock_table) ; iter++){ ++ if(round_tmp == s3c_cpu_clock_table[iter][0]) ++ break; ++ } ++ ++ if(iter >= ARRAY_SIZE(s3c_cpu_clock_table)) ++ iter = ARRAY_SIZE(s3c_cpu_clock_table) - 1; ++ ++ clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK); ++ clk_div0_tmp |= s3c_cpu_clock_table[iter][5]; ++ ++ __raw_writel(clk_div0_tmp, ARM_CLK_DIV); ++ ++ clk->rate = s3c_cpu_clock_table[iter][0]; ++ ++ return 0; ++} ++ ++static int s3c64xx_setrate_sclk_cam(struct clk *clk, unsigned long rate) ++{ ++ u32 shift = 20; ++ u32 cam_div, cfg; ++ unsigned long src_clk = clk_get_rate(clk->parent); ++ ++ cam_div = src_clk / rate; ++ ++ if (cam_div > 32) ++ cam_div = 32; ++ ++ cfg = __raw_readl(S3C_CLK_DIV0); ++ cfg &= ~(0xf << shift); ++ cfg |= ((cam_div - 1) << shift); ++ __raw_writel(cfg, S3C_CLK_DIV0); ++ ++ printk("parent clock for camera: %ld.%03ld MHz, divisor: %d\n", \ ++ print_mhz(src_clk), cam_div); ++ ++ return 0; ++} ++ ++struct clk clk_cpu = { ++ .name = "clk_cpu", ++ .id = -1, ++ .rate = 0, ++ .parent = &clk_mpll, ++ .ctrlbit = 0, ++ .set_rate = s3c_fclk_set_rate, ++ .round_rate = s3c_fclk_round_rate, ++}; ++ ++static int inline s3c64xx_gate(void __iomem *reg, ++ struct clk *clk, ++ int enable) ++{ ++ unsigned int ctrlbit = clk->ctrlbit; ++ u32 con; ++ ++ con = __raw_readl(reg); ++ ++ if (enable) ++ con |= ctrlbit; ++ else ++ con &= ~ctrlbit; ++ ++ __raw_writel(con, reg); ++ return 0; ++} ++ ++static int s3c64xx_pclk_ctrl(struct clk *clk, int enable) ++{ ++ return s3c64xx_gate(S3C_PCLK_GATE, clk, enable); ++} ++ ++static int s3c64xx_hclk_ctrl(struct clk *clk, int enable) ++{ ++ return s3c64xx_gate(S3C_HCLK_GATE, clk, enable); ++} ++ ++int s3c64xx_sclk_ctrl(struct clk *clk, int enable) ++{ ++ return s3c64xx_gate(S3C_SCLK_GATE, clk, enable); ++} ++ ++static struct clk init_clocks_disable[] = { ++ { ++ .name = "nand", ++ .id = -1, ++ .parent = &clk_h, ++ }, { ++ .name = "adc", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s3c64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_TSADC, ++ }, { ++ .name = "keypad", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s3c64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_KEYPAD, ++ }, { ++ .name = "i2c", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s3c64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_IIC, ++ }, { ++ .name = "iis", ++ .id = 0, ++ .parent = &clk_p, ++ .enable = s3c64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_IIS0, ++ }, { ++ .name = "iis", ++ .id = 1, ++ .parent = &clk_p, ++ .enable = s3c64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_IIS1, ++ }, { ++ .name = "iis_v40", ++ .id = 0, ++ .parent = &clk_p, ++ .enable = s3c64xx_pclk_ctrl, ++ .ctrlbit = S3C6410_CLKCON_PCLK_IIS2, ++ }, { ++ .name = "spi", ++ .id = 0, ++ .parent = &clk_p, ++ .enable = s3c64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_SPI0, ++ }, { ++ .name = "spi", ++ .id = 1, ++ .parent = &clk_p, ++ .enable = s3c64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_SPI1, ++ }, { ++ .name = "48m", ++ .id = 0, ++ .parent = &clk_48m, ++ .enable = s3c64xx_sclk_ctrl, ++ .ctrlbit = S3C_CLKCON_SCLK_MMC0_48, ++ }, { ++ .name = "48m", ++ .id = 1, ++ .parent = &clk_48m, ++ .enable = s3c64xx_sclk_ctrl, ++ .ctrlbit = S3C_CLKCON_SCLK_MMC1_48, ++ }, { ++ .name = "48m", ++ .id = 2, ++ .parent = &clk_48m, ++ .enable = s3c64xx_sclk_ctrl, ++ .ctrlbit = S3C_CLKCON_SCLK_MMC2_48, ++ }, { ++ .name = "otg", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s3c64xx_hclk_ctrl, ++ .ctrlbit = S3C_CLKCON_HCLK_USB ++ }, ++ ++}; ++ ++static struct clk init_clocks[] = { ++ { ++ .name = "lcd", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s3c64xx_hclk_ctrl, ++ .ctrlbit = S3C_CLKCON_HCLK_LCD, ++ }, { ++ .name = "gpio", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s3c64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_GPIO, ++ }, { ++ .name = "usb-host", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s3c64xx_hclk_ctrl, ++ .ctrlbit = S3C_CLKCON_SCLK_UHOST, ++ }, { ++ .name = "hsmmc", ++ .id = 0, ++ .parent = &clk_h, ++ .enable = s3c64xx_hclk_ctrl, ++ .ctrlbit = S3C_CLKCON_HCLK_HSMMC0, ++ }, { ++ .name = "hsmmc", ++ .id = 1, ++ .parent = &clk_h, ++ .enable = s3c64xx_hclk_ctrl, ++ .ctrlbit = S3C_CLKCON_HCLK_HSMMC1, ++ }, { ++ .name = "hsmmc", ++ .id = 2, ++ .parent = &clk_h, ++ .enable = s3c64xx_hclk_ctrl, ++ .ctrlbit = S3C_CLKCON_HCLK_HSMMC2, ++ }, { ++ .name = "timers", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s3c64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_PWM, ++ }, { ++ .name = "uart", ++ .id = 0, ++ .parent = &clk_p, ++ .enable = s3c64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_UART0, ++ }, { ++ .name = "uart", ++ .id = 1, ++ .parent = &clk_p, ++ .enable = s3c64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_UART1, ++ }, { ++ .name = "uart", ++ .id = 2, ++ .parent = &clk_p, ++ .enable = s3c64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_UART2, ++ }, { ++ .name = "uart", ++ .id = 3, ++ .parent = &clk_p, ++ .enable = s3c64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_UART3, ++ }, { ++ .name = "rtc", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s3c64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_RTC, ++ }, { ++ .name = "watchdog", ++ .id = -1, ++ .parent = &clk_p, ++ .ctrlbit = S3C_CLKCON_PCLK_WDT, ++ }, { ++ .name = "ac97", ++ .id = -1, ++ .parent = &clk_p, ++ .ctrlbit = S3C_CLKCON_PCLK_AC97, ++ }, { ++ .name = "fimc", ++ .id = -1, ++ .parent = &clk_h, ++ .ctrlbit = S3C_CLKCON_HCLK_CAMIF, ++ }, { ++ .name = "hclk_mfc", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s3c64xx_hclk_ctrl, ++ .ctrlbit = S3C_CLKCON_HCLK_MFC, ++ }, { ++ .name = "sclk_mfc", ++ .id = -1, ++ .parent = &clk_hx2, ++ .enable = s3c64xx_sclk_ctrl, ++ .ctrlbit = S3C_CLKCON_SCLK_MFC, ++ .usage = 0, ++ .rate = 48*1000*1000, ++ }, { ++ .name = "pclk_mfc", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s3c64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_MFC, ++ ++ }, { ++ .name = "hclk_jpeg", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s3c64xx_hclk_ctrl, ++ .ctrlbit = S3C_CLKCON_HCLK_JPEG, ++ }, { ++ .name = "sclk_jpeg", ++ .id = -1, ++ .parent = &clk_hx2, ++ .enable = s3c64xx_sclk_ctrl, ++ .ctrlbit = S3C_CLKCON_SCLK_JPEG, ++ .usage = 0, ++ .rate = 48*1000*1000, ++ }, { ++ .name = "sclk_cam", ++ .id = -1, ++ .parent = &clk_hx2, ++ .enable = s3c64xx_sclk_ctrl, ++ .ctrlbit = S3C_CLKCON_SCLK_CAM, ++ .set_rate = s3c64xx_setrate_sclk_cam, ++ }, ++}; ++ ++static struct clk *clks[] __initdata = { ++ &clk_ext, ++ &clk_epll, ++ &clk_27m, ++ &clk_48m, ++ &clk_cpu, ++}; ++ ++void __init s3c64xx_register_clocks(void) ++{ ++ struct clk *clkp; ++ int ret; ++ int ptr; ++ ++ s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); ++ ++ clkp = init_clocks; ++ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { ++ ret = s3c24xx_register_clock(clkp); ++ if (ret < 0) { ++ printk(KERN_ERR "Failed to register clock %s (%d)\n", ++ clkp->name, ret); ++ } ++ } ++ ++ clkp = init_clocks_disable; ++ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { ++ ++ ret = s3c24xx_register_clock(clkp); ++ if (ret < 0) { ++ printk(KERN_ERR "Failed to register clock %s (%d)\n", ++ clkp->name, ret); ++ } ++ ++ (clkp->enable)(clkp, 0); ++ } ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/cpu.c linux-2.6.28.6/arch/arm/plat-s3c64xx/cpu.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/cpu.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/cpu.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,116 @@ ++/* linux/arch/arm/plat-s3c64xx/cpu.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C64XX CPU Support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++/* table of supported CPUs */ ++ ++static const char name_s3c6400[] = "S3C6400"; ++static const char name_s3c6410[] = "S3C6410"; ++ ++static struct cpu_table cpu_ids[] __initdata = { ++ { ++ .idcode = 0x36400000, ++ .idmask = 0xfffff000, ++ .map_io = s3c6400_map_io, ++ .init_clocks = s3c6400_init_clocks, ++ .init_uarts = s3c6400_init_uarts, ++ .init = s3c6400_init, ++ .name = name_s3c6400, ++ }, { ++ .idcode = 0x36410100, ++ .idmask = 0xffffff00, ++ .map_io = s3c6410_map_io, ++ .init_clocks = s3c6410_init_clocks, ++ .init_uarts = s3c6410_init_uarts, ++ .init = s3c6410_init, ++ .name = name_s3c6410, ++ }, ++}; ++ ++/* minimal IO mapping */ ++ ++/* see notes on uart map in arch/arm/mach-s3c6400/include/mach/debug-macro.S */ ++#define UART_OFFS (S3C_PA_UART & 0xfffff) ++ ++static struct map_desc s3c_iodesc[] __initdata = { ++ { ++ .virtual = (unsigned long)S3C_VA_SYS, ++ .pfn = __phys_to_pfn(S3C64XX_PA_SYSCON), ++ .length = SZ_4K, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = (unsigned long)(S3C_VA_UART + UART_OFFS), ++ .pfn = __phys_to_pfn(S3C_PA_UART), ++ .length = SZ_4K, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = (unsigned long)S3C_VA_VIC0, ++ .pfn = __phys_to_pfn(S3C64XX_PA_VIC0), ++ .length = SZ_16K, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = (unsigned long)S3C_VA_VIC1, ++ .pfn = __phys_to_pfn(S3C64XX_PA_VIC1), ++ .length = SZ_16K, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = (unsigned long)S3C_VA_TIMER, ++ .pfn = __phys_to_pfn(S3C_PA_TIMER), ++ .length = SZ_16K, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = (unsigned long)S3C64XX_VA_GPIO, ++ .pfn = __phys_to_pfn(S3C64XX_PA_GPIO), ++ .length = SZ_4K, ++ .type = MT_DEVICE, ++ }, ++}; ++ ++/* read cpu identification code */ ++ ++void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) ++{ ++ unsigned long idcode; ++ ++ /* initialise the io descriptors we need for initialisation */ ++ iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); ++ iotable_init(mach_desc, size); ++ ++ idcode = __raw_readl(S3C_SYS_ID); ++ s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/dev-fimc0.c linux-2.6.28.6/arch/arm/plat-s3c64xx/dev-fimc0.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/dev-fimc0.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/dev-fimc0.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,68 @@ ++/* linux/arch/arm/plat-s5pc1xx/dev-fimc0.c ++ * ++ * Copyright 2009 Samsung Electronics ++ * Jinsung Yang ++ * http://samsungsemi.com/ ++ * ++ * S5PC1XX series device definition for fimc device 0 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++ ++static struct resource s3c_fimc0_resource[] = { ++ [0] = { ++ .start = S3C64XX_PA_FIMC, ++ .end = S3C64XX_PA_FIMC + S3C64XX_SZ_FIMC - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_CAMIF_C, ++ .end = IRQ_CAMIF_C, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++struct platform_device s3c_device_fimc0 = { ++ .name = "s3c-fimc", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(s3c_fimc0_resource), ++ .resource = s3c_fimc0_resource, ++}; ++ ++static struct s3c_platform_fimc default_fimc0_data __initdata = { ++ .srclk_name = "hclk", ++ .clk_name = "fimc", ++ .clockrate = 133000000, ++ .line_length = 720, ++ .nr_frames = 4, ++ .shared_io = 0, ++}; ++ ++void __init s3c_fimc0_set_platdata(struct s3c_platform_fimc *pd) ++{ ++ struct s3c_platform_fimc *npd; ++ ++ if (!pd) ++ pd = &default_fimc0_data; ++ ++ npd = kmemdup(pd, sizeof(struct s3c_platform_fimc), GFP_KERNEL); ++ if (!npd) ++ printk(KERN_ERR "%s: no memory for platform data\n", __func__); ++ else if (!npd->cfg_gpio) ++ npd->cfg_gpio = s3c_fimc0_cfg_gpio; ++ ++ s3c_device_fimc0.dev.platform_data = npd; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/dev-fimc1.c linux-2.6.28.6/arch/arm/plat-s3c64xx/dev-fimc1.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/dev-fimc1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/dev-fimc1.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,68 @@ ++/* linux/arch/arm/plat-s5pc1xx/dev-fimc1.c ++ * ++ * Copyright 2009 Samsung Electronics ++ * Jinsung Yang ++ * http://samsungsemi.com/ ++ * ++ * S5PC1XX series device definition for fimc device 0 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++ ++static struct resource s3c_fimc1_resource[] = { ++ [0] = { ++ .start = S3C64XX_PA_FIMC, ++ .end = S3C64XX_PA_FIMC + S3C64XX_SZ_FIMC - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_CAMIF_P, ++ .end = IRQ_CAMIF_P, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++struct platform_device s3c_device_fimc1 = { ++ .name = "s3c-fimc", ++ .id = 1, ++ .num_resources = ARRAY_SIZE(s3c_fimc1_resource), ++ .resource = s3c_fimc1_resource, ++}; ++ ++static struct s3c_platform_fimc default_fimc1_data __initdata = { ++ .srclk_name = "hclk", ++ .clk_name = "fimc", ++ .clockrate = 133000000, ++ .line_length = 720, ++ .nr_frames = 4, ++ .shared_io = 1, ++}; ++ ++void __init s3c_fimc1_set_platdata(struct s3c_platform_fimc *pd) ++{ ++ struct s3c_platform_fimc *npd; ++ ++ if (!pd) ++ pd = &default_fimc1_data; ++ ++ npd = kmemdup(pd, sizeof(struct s3c_platform_fimc), GFP_KERNEL); ++ if (!npd) ++ printk(KERN_ERR "%s: no memory for platform data\n", __func__); ++ else if (!npd->cfg_gpio) ++ npd->cfg_gpio = s3c_fimc1_cfg_gpio; ++ ++ s3c_device_fimc1.dev.platform_data = npd; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/dev-uart.c linux-2.6.28.6/arch/arm/plat-s3c64xx/dev-uart.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/dev-uart.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/dev-uart.c 2009-10-13 10:53:07.000000000 +0200 +@@ -0,0 +1,176 @@ ++/* linux/arch/arm/plat-s3c64xx/dev-uart.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * Base S3C64XX UART resource and device definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++/* Serial port registrations */ ++ ++/* 64xx uarts are closer together */ ++ ++static struct resource s3c64xx_uart0_resource[] = { ++ [0] = { ++ .start = S3C_PA_UART0, ++ .end = S3C_PA_UART0 + S3C_SZ_UART, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_S3CUART_RX0, ++ .end = IRQ_S3CUART_RX0, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = IRQ_S3CUART_TX0, ++ .end = IRQ_S3CUART_TX0, ++ .flags = IORESOURCE_IRQ, ++ ++ }, ++ [3] = { ++ .start = IRQ_S3CUART_ERR0, ++ .end = IRQ_S3CUART_ERR0, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct resource s3c64xx_uart1_resource[] = { ++ [0] = { ++ .start = S3C_PA_UART1, ++ .end = S3C_PA_UART1 + S3C_SZ_UART, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_S3CUART_RX1, ++ .end = IRQ_S3CUART_RX1, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = IRQ_S3CUART_TX1, ++ .end = IRQ_S3CUART_TX1, ++ .flags = IORESOURCE_IRQ, ++ ++ }, ++ [3] = { ++ .start = IRQ_S3CUART_ERR1, ++ .end = IRQ_S3CUART_ERR1, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct resource s3c64xx_uart2_resource[] = { ++ [0] = { ++ .start = S3C_PA_UART2, ++ .end = S3C_PA_UART2 + S3C_SZ_UART, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_S3CUART_RX2, ++ .end = IRQ_S3CUART_RX2, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = IRQ_S3CUART_TX2, ++ .end = IRQ_S3CUART_TX2, ++ .flags = IORESOURCE_IRQ, ++ ++ }, ++ [3] = { ++ .start = IRQ_S3CUART_ERR2, ++ .end = IRQ_S3CUART_ERR2, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct resource s3c64xx_uart3_resource[] = { ++ [0] = { ++ .start = S3C_PA_UART3, ++ .end = S3C_PA_UART3 + S3C_SZ_UART, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_S3CUART_RX3, ++ .end = IRQ_S3CUART_RX3, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = IRQ_S3CUART_TX3, ++ .end = IRQ_S3CUART_TX3, ++ .flags = IORESOURCE_IRQ, ++ ++ }, ++ [3] = { ++ .start = IRQ_S3CUART_ERR3, ++ .end = IRQ_S3CUART_ERR3, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++ ++struct s3c24xx_uart_resources s3c64xx_uart_resources[] __initdata = { ++ [0] = { ++ .resources = s3c64xx_uart0_resource, ++ .nr_resources = ARRAY_SIZE(s3c64xx_uart0_resource), ++ }, ++ [1] = { ++ .resources = s3c64xx_uart1_resource, ++ .nr_resources = ARRAY_SIZE(s3c64xx_uart1_resource), ++ }, ++ [2] = { ++ .resources = s3c64xx_uart2_resource, ++ .nr_resources = ARRAY_SIZE(s3c64xx_uart2_resource), ++ }, ++ [3] = { ++ .resources = s3c64xx_uart3_resource, ++ .nr_resources = ARRAY_SIZE(s3c64xx_uart3_resource), ++ }, ++}; ++ ++/* uart devices */ ++ ++static struct platform_device s3c24xx_uart_device0 = { ++ .id = 0, ++}; ++ ++static struct platform_device s3c24xx_uart_device1 = { ++ .id = 1, ++}; ++ ++static struct platform_device s3c24xx_uart_device2 = { ++ .id = 2, ++}; ++ ++static struct platform_device s3c24xx_uart_device3 = { ++ .id = 3, ++}; ++ ++struct platform_device *s3c24xx_uart_src[4] = { ++ &s3c24xx_uart_device0, ++ &s3c24xx_uart_device1, ++ &s3c24xx_uart_device2, ++ &s3c24xx_uart_device3, ++}; ++ ++struct platform_device *s3c24xx_uart_devs[4] = { ++}; ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/devs.c linux-2.6.28.6/arch/arm/plat-s3c64xx/devs.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/devs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/devs.c 2010-04-07 07:45:31.000000000 +0200 +@@ -0,0 +1,589 @@ ++/* linux/arch/arm/plat-s3c64xx/devs.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * Base S3C64XX resource and device definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++/* SMC9115 LAN via ROM interface ++ ++static struct resource s3c_smc911x_resources[] = { ++ [0] = { ++ .start = S3C64XX_PA_SMC9115, ++ .end = S3C64XX_PA_SMC9115 + S3C64XX_SZ_SMC9115 - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_EINT(10), ++ .end = IRQ_EINT(10), ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++struct platform_device s3c_device_smc911x = { ++ .name = "smc911x", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_smc911x_resources), ++ .resource = s3c_smc911x_resources, ++}; ++*/ ++static struct resource dm9000_resources[] = { ++ [0] = { ++ .start = S3C64XX_VA_DM9000, ++ .end = S3C64XX_VA_DM9000 + S3C64XX_SZ_DM9000 - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ ++ [1] = { ++ .start = IRQ_EINT(7), ++ .end = IRQ_EINT(7), ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct dm9000_plat_data dm9000_setup = { ++ .flags = DM9000_PLATF_16BITONLY ++}; ++ ++ struct platform_device s3c_device_dm9000 = { ++ .name = "dm9000", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(dm9000_resources), ++ .resource = dm9000_resources, ++ .dev = { ++ .platform_data = &dm9000_setup, ++ } ++}; ++ ++EXPORT_SYMBOL(s3c_device_dm9000); ++ ++/* NAND Controller */ ++ ++static struct resource s3c_nand_resource[] = { ++ [0] = { ++ .start = S3C64XX_PA_NAND, ++ .end = S3C64XX_PA_NAND + S3C64XX_SZ_NAND - 1, ++ .flags = IORESOURCE_MEM, ++ } ++}; ++ ++struct platform_device s3c_device_nand = { ++ .name = "s3c-nand", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_nand_resource), ++ .resource = s3c_nand_resource, ++}; ++ ++EXPORT_SYMBOL(s3c_device_nand); ++ ++/* OneNAND Controller */ ++static struct resource s3c_onenand_resource[] = { ++ [0] = { ++ .start = S3C64XX_PA_ONENAND, ++ .end = S3C64XX_PA_ONENAND + S3C_SZ_ONENAND - 1, ++ .flags = IORESOURCE_MEM, ++ } ++}; ++ ++struct platform_device s3c_device_onenand = { ++ .name = "onenand", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_onenand_resource), ++ .resource = s3c_onenand_resource, ++}; ++ ++EXPORT_SYMBOL(s3c_device_onenand); ++ ++/* USB Host Controller */ ++ ++static struct resource s3c_usb_resource[] = { ++ [0] = { ++ .start = S3C64XX_PA_USBHOST, ++ .end = S3C64XX_PA_USBHOST + S3C64XX_SZ_USBHOST - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_UHOST, ++ .end = IRQ_UHOST, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static u64 s3c_device_usb_dmamask = 0xffffffffUL; ++ ++struct platform_device s3c_device_usb = { ++ .name = "s3c2410-ohci", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_usb_resource), ++ .resource = s3c_usb_resource, ++ .dev = { ++ .dma_mask = &s3c_device_usb_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ ++EXPORT_SYMBOL(s3c_device_usb); ++ ++/* USB Device (Gadget)*/ ++ ++static struct resource s3c_usbgadget_resource[] = { ++ [0] = { ++ .start = S3C_PA_OTG, ++ .end = S3C_PA_OTG + S3C_SZ_OTG - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_OTG, ++ .end = IRQ_OTG, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++struct platform_device s3c_device_usbgadget = { ++ .name = "s3c-usbgadget", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_usbgadget_resource), ++ .resource = s3c_usbgadget_resource, ++}; ++ ++EXPORT_SYMBOL(s3c_device_usbgadget); ++ ++/* USB Device (OTG hcd)*/ ++ ++static struct resource s3c_usb_otghcd_resource[] = { ++ [0] = { ++ .start = S3C_PA_OTG, ++ .end = S3C_PA_OTG + S3C_SZ_OTG - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_OTG, ++ .end = IRQ_OTG, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static u64 s3c_device_usb_otghcd_dmamask = 0xffffffffUL; ++ ++struct platform_device s3c_device_usb_otghcd = { ++ .name = "s3c_otghcd", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_usb_otghcd_resource), ++ .resource = s3c_usb_otghcd_resource, ++ .dev = { ++ .dma_mask = &s3c_device_usb_otghcd_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ ++EXPORT_SYMBOL(s3c_device_usb_otghcd); ++ ++/* LCD Controller */ ++ ++static struct resource s3c_lcd_resource[] = { ++ [0] = { ++ .start = S3C64XX_PA_LCD, ++ .end = S3C64XX_PA_LCD + SZ_1M - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_LCD_VSYNC, ++ .end = IRQ_LCD_SYSTEM, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static u64 s3c_device_lcd_dmamask = 0xffffffffUL; ++ ++struct platform_device s3c_device_lcd = { ++ .name = "s3c-lcd", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_lcd_resource), ++ .resource = s3c_lcd_resource, ++ .dev = { ++ .dma_mask = &s3c_device_lcd_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ ++/* FIMG-2D controller */ ++static struct resource s3c_g2d_resource[] = { ++ [0] = { ++ .start = S3C64XX_PA_G2D, ++ .end = S3C64XX_PA_G2D + S3C64XX_SZ_G2D - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_2D, ++ .end = IRQ_2D, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++struct platform_device s3c_device_g2d = { ++ .name = "s3c-g2d", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_g2d_resource), ++ .resource = s3c_g2d_resource ++}; ++EXPORT_SYMBOL(s3c_device_g2d); ++ ++ ++/* FIMG-3D controller */ ++static struct resource s3c_g3d_resource[] = { ++ [0] = { ++ .start = S3C64XX_PA_G3D, ++ .end = S3C64XX_PA_G3D + S3C64XX_SZ_G3D - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_S3C6410_G3D, ++ .end = IRQ_S3C6410_G3D, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++struct platform_device s3c_device_g3d = { ++ .name = "s3c-g3d", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_g3d_resource), ++ .resource = s3c_g3d_resource ++}; ++EXPORT_SYMBOL(s3c_device_g3d); ++ ++ ++/* VPP controller */ ++static struct resource s3c_vpp_resource[] = { ++ [0] = { ++ .start = S3C6400_PA_VPP, ++ .end = S3C6400_PA_VPP + S3C_SZ_VPP - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_POST0, ++ .end = IRQ_POST0, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++struct platform_device s3c_device_vpp = { ++ .name = "s3c-vpp", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_vpp_resource), ++ .resource = s3c_vpp_resource, ++}; ++EXPORT_SYMBOL(s3c_device_vpp); ++ ++/* TV encoder */ ++static struct resource s3c_tvenc_resource[] = { ++ [0] = { ++ .start = S3C6400_PA_TVENC, ++ .end = S3C6400_PA_TVENC + S3C_SZ_TVENC - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_TVENC, ++ .end = IRQ_TVENC, ++ .flags = IORESOURCE_IRQ, ++ } ++ ++}; ++ ++struct platform_device s3c_device_tvenc = { ++ .name = "s3c-tvenc", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_tvenc_resource), ++ .resource = s3c_tvenc_resource, ++}; ++ ++EXPORT_SYMBOL(s3c_device_tvenc); ++ ++/* MFC controller */ ++static struct resource s3c_mfc_resource[] = { ++ [0] = { ++ .start = S3C6400_PA_MFC, ++ .end = S3C6400_PA_MFC + S3C_SZ_MFC - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_MFC, ++ .end = IRQ_MFC, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++struct platform_device s3c_device_mfc = { ++ .name = "s3c-mfc", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_mfc_resource), ++ .resource = s3c_mfc_resource ++}; ++ ++EXPORT_SYMBOL(s3c_device_mfc); ++ ++/* TV scaler */ ++static struct resource s3c_tvscaler_resource[] = { ++ [0] = { ++ .start = S3C6400_PA_TVSCALER, ++ .end = S3C6400_PA_TVSCALER + S3C_SZ_TVSCALER - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_SCALER, ++ .end = IRQ_SCALER, ++ .flags = IORESOURCE_IRQ, ++ } ++ ++}; ++ ++/* rotator interface */ ++static struct resource s3c_rotator_resource[] = { ++ [0] = { ++ .start = S3C6400_PA_ROTATOR, ++ .end = S3C6400_PA_ROTATOR + S3C_SZ_ROTATOR - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_ROTATOR, ++ .end = IRQ_ROTATOR, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++struct platform_device s3c_device_rotator = { ++ .name = "s3c-rotator", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_rotator_resource), ++ .resource = s3c_rotator_resource ++}; ++ ++EXPORT_SYMBOL(s3c_device_rotator); ++ ++/* JPEG controller */ ++static struct resource s3c_jpeg_resource[] = { ++ [0] = { ++ .start = S3C6400_PA_JPEG, ++ .end = S3C6400_PA_JPEG + S3C_SZ_JPEG - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_JPEG, ++ .end = IRQ_JPEG, ++ .flags = IORESOURCE_IRQ, ++ } ++ ++}; ++ ++struct platform_device s3c_device_jpeg = { ++ .name = "s3c-jpeg", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_jpeg_resource), ++ .resource = s3c_jpeg_resource, ++}; ++ ++struct platform_device s3c_device_tvscaler = { ++ .name = "s3c-tvscaler", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_tvscaler_resource), ++ .resource = s3c_tvscaler_resource, ++}; ++ ++EXPORT_SYMBOL(s3c_device_tvscaler); ++ ++ ++/* ADC */ ++static struct resource s3c_adc_resource[] = { ++ [0] = { ++ .start = S3C_PA_ADC, ++ .end = S3C_PA_ADC + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_PENDN, ++ .end = IRQ_PENDN, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = IRQ_ADC, ++ .end = IRQ_ADC, ++ .flags = IORESOURCE_IRQ, ++ } ++ ++}; ++ ++struct platform_device s3c_device_adc = { ++ .name = "s3c-adc", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_adc_resource), ++ .resource = s3c_adc_resource, ++}; ++ ++void __init s3c_adc_set_platdata(struct s3c_adc_mach_info *pd) ++{ ++ struct s3c_adc_mach_info *npd; ++ ++ npd = kmalloc(sizeof(*npd), GFP_KERNEL); ++ if (npd) { ++ memcpy(npd, pd, sizeof(*npd)); ++ s3c_device_adc.dev.platform_data = npd; ++ } else { ++ printk(KERN_ERR "no memory for ADC platform data\n"); ++ } ++} ++EXPORT_SYMBOL(s3c_device_adc); ++ ++ ++static struct resource s3c_rtc_resource[] = { ++ [0] = { ++ .start = S3C_PA_RTC, ++ .end = S3C_PA_RTC + 0xff, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_RTC_ALARM, ++ .end = IRQ_RTC_ALARM, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = IRQ_RTC_TIC, ++ .end = IRQ_RTC_TIC, ++ .flags = IORESOURCE_IRQ ++ } ++}; ++ ++struct platform_device s3c_device_rtc = { ++ .name = "s3c2410-rtc", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_rtc_resource), ++ .resource = s3c_rtc_resource, ++}; ++ ++EXPORT_SYMBOL(s3c_device_rtc); ++ ++ ++/* Keypad interface */ ++static struct resource s3c_keypad_resource[] = { ++ [0] = { ++ .start = S3C_PA_KEYPAD, ++ .end = S3C_PA_KEYPAD+ S3C_SZ_KEYPAD - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_KEYPAD, ++ .end = IRQ_KEYPAD, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++struct platform_device s3c_device_keypad = { ++ .name = "s3c-keypad", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_keypad_resource), ++ .resource = s3c_keypad_resource, ++}; ++EXPORT_SYMBOL(s3c_device_keypad); ++ ++/* SPI (0) */ ++static struct resource s3c_spi0_resource[] = { ++ [0] = { ++ .start = S3C_PA_SPI0, ++ .end = S3C_PA_SPI0 + S3C_SZ_SPI0 - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_SPI0, ++ .end = IRQ_SPI0, ++ .flags = IORESOURCE_IRQ, ++ } ++ ++}; ++ ++static u64 s3c_device_spi0_dmamask = 0xffffffffUL; ++ ++struct platform_device s3c_device_spi0 = { ++ .name = "sam-spi", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(s3c_spi0_resource), ++ .resource = s3c_spi0_resource, ++ .dev = { ++ .dma_mask = &s3c_device_spi0_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++EXPORT_SYMBOL(s3c_device_spi0); ++ ++/* SPI (1) */ ++static struct resource s3c_spi1_resource[] = { ++ [0] = { ++ .start = S3C_PA_SPI1, ++ .end = S3C_PA_SPI1 + S3C_SZ_SPI1 - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_SPI1, ++ .end = IRQ_SPI1, ++ .flags = IORESOURCE_IRQ, ++ } ++ ++}; ++ ++static u64 s3c_device_spi1_dmamask = 0xffffffffUL; ++ ++struct platform_device s3c_device_spi1 = { ++ .name = "sam-spi", ++ .id = 1, ++ .num_resources = ARRAY_SIZE(s3c_spi1_resource), ++ .resource = s3c_spi1_resource, ++ .dev = { ++ .dma_mask = &s3c_device_spi1_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++EXPORT_SYMBOL(s3c_device_spi1); ++ ++/* Watchdog */ ++static struct resource s3c_wdt_resource[] = { ++ [0] = { ++ .start = S3C64XX_PA_WATCHDOG, ++ .end = S3C64XX_PA_WATCHDOG + S3C64XX_SZ_WATCHDOG - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_WDT, ++ .end = IRQ_WDT, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++struct platform_device s3c_device_wdt = { ++ .name = "s3c2410-wdt", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_wdt_resource), ++ .resource = s3c_wdt_resource, ++}; ++ ++EXPORT_SYMBOL(s3c_device_wdt); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/gpiolib.c linux-2.6.28.6/arch/arm/plat-s3c64xx/gpiolib.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/gpiolib.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/gpiolib.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,420 @@ ++/* arch/arm/plat-s3c64xx/gpiolib.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C64XX - GPIOlib support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++/* GPIO bank summary: ++ * ++ * Bank GPIOs Style SlpCon ExtInt Group ++ * A 8 4Bit Yes 1 ++ * B 7 4Bit Yes 1 ++ * C 8 4Bit Yes 2 ++ * D 5 4Bit Yes 3 ++ * E 5 4Bit Yes None ++ * F 16 2Bit Yes 4 [1] ++ * G 7 4Bit Yes 5 ++ * H 10 4Bit[2] Yes 6 ++ * I 16 2Bit Yes None ++ * J 12 2Bit Yes None ++ * K 16 4Bit[2] No None ++ * L 15 4Bit[2] No None ++ * M 6 4Bit No IRQ_EINT ++ * N 16 2Bit No IRQ_EINT ++ * O 16 2Bit Yes 7 ++ * P 15 2Bit Yes 8 ++ * Q 9 2Bit Yes 9 ++ * ++ * [1] BANKF pins 14,15 do not form part of the external interrupt sources ++ * [2] BANK has two control registers, GPxCON0 and GPxCON1 ++ */ ++ ++#define OFF_GPCON (0x00) ++#define OFF_GPDAT (0x04) ++ ++#define con_4bit_shift(__off) ((__off) * 4) ++ ++#if 1 ++#define gpio_dbg(x...) do { } while(0) ++#else ++#define gpio_dbg(x...) printk(KERN_DEBUG ## x) ++#endif ++ ++/* The s3c64xx_gpiolib_4bit routines are to control the gpio banks where ++ * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the ++ * following example: ++ * ++ * base + 0x00: Control register, 4 bits per gpio ++ * gpio n: 4 bits starting at (4*n) ++ * 0000 = input, 0001 = output, others mean special-function ++ * base + 0x04: Data register, 1 bit per gpio ++ * bit n: data bit n ++ * ++ * Note, since the data register is one bit per gpio and is at base + 0x4 ++ * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of ++ * the output. ++*/ ++ ++static int s3c64xx_gpiolib_4bit_input(struct gpio_chip *chip, unsigned offset) ++{ ++ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); ++ void __iomem *base = ourchip->base; ++ unsigned long con; ++ ++ con = __raw_readl(base + OFF_GPCON); ++ con &= ~(0xf << con_4bit_shift(offset)); ++ __raw_writel(con, base + OFF_GPCON); ++ ++ gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con); ++ ++ return 0; ++} ++ ++static int s3c64xx_gpiolib_4bit_output(struct gpio_chip *chip, ++ unsigned offset, int value) ++{ ++ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); ++ void __iomem *base = ourchip->base; ++ unsigned long con; ++ unsigned long dat; ++ ++ con = __raw_readl(base + OFF_GPCON); ++ con &= ~(0xf << con_4bit_shift(offset)); ++ con |= 0x1 << con_4bit_shift(offset); ++ ++ dat = __raw_readl(base + OFF_GPDAT); ++ if (value) ++ dat |= 1 << offset; ++ else ++ dat &= ~(1 << offset); ++ ++ __raw_writel(dat, base + OFF_GPDAT); ++ __raw_writel(con, base + OFF_GPCON); ++ __raw_writel(dat, base + OFF_GPDAT); ++ ++ gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); ++ ++ return 0; ++} ++ ++/* The next set of routines are for the case where the GPIO configuration ++ * registers are 4 bits per GPIO but there is more than one register (the ++ * bank has more than 8 GPIOs. ++ * ++ * This case is the similar to the 4 bit case, but the registers are as ++ * follows: ++ * ++ * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs) ++ * gpio n: 4 bits starting at (4*n) ++ * 0000 = input, 0001 = output, others mean special-function ++ * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs) ++ * gpio n: 4 bits starting at (4*n) ++ * 0000 = input, 0001 = output, others mean special-function ++ * base + 0x08: Data register, 1 bit per gpio ++ * bit n: data bit n ++ * ++ * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we ++ * store the 'base + 0x4' address so that these routines see the data ++ * register at ourchip->base + 0x04. ++*/ ++ ++static int s3c64xx_gpiolib_4bit2_input(struct gpio_chip *chip, unsigned offset) ++{ ++ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); ++ void __iomem *base = ourchip->base; ++ void __iomem *regcon = base; ++ unsigned long con; ++ ++ if (offset > 7) ++ offset -= 8; ++ else ++ regcon -= 4; ++ ++ con = __raw_readl(regcon); ++ con &= ~(0xf << con_4bit_shift(offset)); ++ __raw_writel(con, regcon); ++ ++ gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con); ++ ++ return 0; ++ ++} ++ ++static int s3c64xx_gpiolib_4bit2_output(struct gpio_chip *chip, ++ unsigned offset, int value) ++{ ++ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); ++ void __iomem *base = ourchip->base; ++ void __iomem *regcon = base; ++ unsigned long con; ++ unsigned long dat; ++ ++ if (offset > 7) ++ offset -= 8; ++ else ++ regcon -= 4; ++ ++ con = __raw_readl(regcon); ++ con &= ~(0xf << con_4bit_shift(offset)); ++ con |= 0x1 << con_4bit_shift(offset); ++ ++ dat = __raw_readl(base + OFF_GPDAT); ++ if (value) ++ dat |= 1 << offset; ++ else ++ dat &= ~(1 << offset); ++ ++ __raw_writel(dat, base + OFF_GPDAT); ++ __raw_writel(con, regcon); ++ __raw_writel(dat, base + OFF_GPDAT); ++ ++ gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); ++ ++ return 0; ++} ++ ++static struct s3c_gpio_cfg gpio_4bit_cfg_noint = { ++ .set_config = s3c_gpio_setcfg_s3c64xx_4bit, ++ .set_pull = s3c_gpio_setpull_updown, ++ .get_pull = s3c_gpio_getpull_updown, ++}; ++ ++static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = { ++ .cfg_eint = 7, ++ .set_config = s3c_gpio_setcfg_s3c64xx_4bit, ++ .set_pull = s3c_gpio_setpull_updown, ++ .get_pull = s3c_gpio_getpull_updown, ++}; ++ ++static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = { ++ .cfg_eint = 3, ++ .set_config = s3c_gpio_setcfg_s3c64xx_4bit, ++ .set_pull = s3c_gpio_setpull_updown, ++ .get_pull = s3c_gpio_getpull_updown, ++}; ++ ++static struct s3c_gpio_chip gpio_4bit[] = { ++ { ++ .base = S3C64XX_GPA_BASE, ++ .config = &gpio_4bit_cfg_eint0111, ++ .chip = { ++ .base = S3C64XX_GPA(0), ++ .ngpio = S3C64XX_GPIO_A_NR, ++ .label = "GPA", ++ }, ++ }, { ++ .base = S3C64XX_GPB_BASE, ++ .config = &gpio_4bit_cfg_eint0111, ++ .chip = { ++ .base = S3C64XX_GPB(0), ++ .ngpio = S3C64XX_GPIO_B_NR, ++ .label = "GPB", ++ }, ++ }, { ++ .base = S3C64XX_GPC_BASE, ++ .config = &gpio_4bit_cfg_eint0111, ++ .chip = { ++ .base = S3C64XX_GPC(0), ++ .ngpio = S3C64XX_GPIO_C_NR, ++ .label = "GPC", ++ }, ++ }, { ++ .base = S3C64XX_GPD_BASE, ++ .config = &gpio_4bit_cfg_eint0111, ++ .chip = { ++ .base = S3C64XX_GPD(0), ++ .ngpio = S3C64XX_GPIO_D_NR, ++ .label = "GPD", ++ }, ++ }, { ++ .base = S3C64XX_GPE_BASE, ++ .config = &gpio_4bit_cfg_noint, ++ .chip = { ++ .base = S3C64XX_GPE(0), ++ .ngpio = S3C64XX_GPIO_E_NR, ++ .label = "GPE", ++ }, ++ }, { ++ .base = S3C64XX_GPG_BASE, ++ .config = &gpio_4bit_cfg_eint0111, ++ .chip = { ++ .base = S3C64XX_GPG(0), ++ .ngpio = S3C64XX_GPIO_G_NR, ++ .label = "GPG", ++ }, ++ }, { ++ .base = S3C64XX_GPM_BASE, ++ .config = &gpio_4bit_cfg_eint0011, ++ .chip = { ++ .base = S3C64XX_GPM(0), ++ .ngpio = S3C64XX_GPIO_M_NR, ++ .label = "GPM", ++ }, ++ }, ++}; ++ ++static struct s3c_gpio_chip gpio_4bit2[] = { ++ { ++ .base = S3C64XX_GPH_BASE + 0x4, ++ .config = &gpio_4bit_cfg_eint0111, ++ .chip = { ++ .base = S3C64XX_GPH(0), ++ .ngpio = S3C64XX_GPIO_H_NR, ++ .label = "GPH", ++ }, ++ }, { ++ .base = S3C64XX_GPK_BASE + 0x4, ++ .config = &gpio_4bit_cfg_noint, ++ .chip = { ++ .base = S3C64XX_GPK(0), ++ .ngpio = S3C64XX_GPIO_K_NR, ++ .label = "GPK", ++ }, ++ }, { ++ .base = S3C64XX_GPL_BASE + 0x4, ++ .config = &gpio_4bit_cfg_eint0011, ++ .chip = { ++ .base = S3C64XX_GPL(0), ++ .ngpio = S3C64XX_GPIO_L_NR, ++ .label = "GPL", ++ }, ++ }, ++}; ++ ++static struct s3c_gpio_cfg gpio_2bit_cfg_noint = { ++ .set_config = s3c_gpio_setcfg_s3c24xx, ++ .set_pull = s3c_gpio_setpull_updown, ++ .get_pull = s3c_gpio_getpull_updown, ++}; ++ ++static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = { ++ .cfg_eint = 2, ++ .set_config = s3c_gpio_setcfg_s3c24xx, ++ .set_pull = s3c_gpio_setpull_updown, ++ .get_pull = s3c_gpio_getpull_updown, ++}; ++ ++static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = { ++ .cfg_eint = 3, ++ .set_config = s3c_gpio_setcfg_s3c24xx, ++ .set_pull = s3c_gpio_setpull_updown, ++ .get_pull = s3c_gpio_getpull_updown, ++}; ++ ++static struct s3c_gpio_chip gpio_2bit[] = { ++ { ++ .base = S3C64XX_GPF_BASE, ++ .config = &gpio_2bit_cfg_eint11, ++ .chip = { ++ .base = S3C64XX_GPF(0), ++ .ngpio = S3C64XX_GPIO_F_NR, ++ .label = "GPF", ++ }, ++ }, { ++ .base = S3C64XX_GPI_BASE, ++ .config = &gpio_2bit_cfg_noint, ++ .chip = { ++ .base = S3C64XX_GPI(0), ++ .ngpio = S3C64XX_GPIO_I_NR, ++ .label = "GPI", ++ }, ++ }, { ++ .base = S3C64XX_GPJ_BASE, ++ .config = &gpio_2bit_cfg_noint, ++ .chip = { ++ .base = S3C64XX_GPJ(0), ++ .ngpio = S3C64XX_GPIO_J_NR, ++ .label = "GPJ", ++ }, ++ }, { ++ .base = S3C64XX_GPN_BASE, ++ .config = &gpio_2bit_cfg_eint10, ++ .chip = { ++ .base = S3C64XX_GPN(0), ++ .ngpio = S3C64XX_GPIO_N_NR, ++ .label = "GPN", ++ }, ++ }, { ++ .base = S3C64XX_GPO_BASE, ++ .config = &gpio_2bit_cfg_eint11, ++ .chip = { ++ .base = S3C64XX_GPO(0), ++ .ngpio = S3C64XX_GPIO_O_NR, ++ .label = "GPO", ++ }, ++ }, { ++ .base = S3C64XX_GPP_BASE, ++ .config = &gpio_2bit_cfg_eint11, ++ .chip = { ++ .base = S3C64XX_GPP(0), ++ .ngpio = S3C64XX_GPIO_P_NR, ++ .label = "GPP", ++ }, ++ }, { ++ .base = S3C64XX_GPQ_BASE, ++ .config = &gpio_2bit_cfg_eint11, ++ .chip = { ++ .base = S3C64XX_GPQ(0), ++ .ngpio = S3C64XX_GPIO_Q_NR, ++ .label = "GPQ", ++ }, ++ }, ++}; ++ ++static __init void s3c64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip) ++{ ++ chip->chip.direction_input = s3c64xx_gpiolib_4bit_input; ++ chip->chip.direction_output = s3c64xx_gpiolib_4bit_output; ++} ++ ++static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip) ++{ ++ chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input; ++ chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output; ++} ++ ++static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips, ++ int nr_chips, ++ void (*fn)(struct s3c_gpio_chip *)) ++{ ++ for (; nr_chips > 0; nr_chips--, chips++) { ++ if (fn) ++ (fn)(chips); ++ s3c_gpiolib_add(chips); ++ } ++} ++ ++static __init int s3c64xx_gpiolib_init(void) ++{ ++ s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit), ++ s3c64xx_gpiolib_add_4bit); ++ ++ s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2), ++ s3c64xx_gpiolib_add_4bit2); ++ ++ s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), NULL); ++ ++ return 0; ++} ++ ++arch_initcall(s3c64xx_gpiolib_init); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/dma.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/dma.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/dma.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/dma.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,12 @@ ++/* linux/arch/arm/plat-s3c64xx/include/plat/dma.h ++ * ++ * Copyright (C) 2006 Simtec Electronics ++ * Ben Dooks ++ * ++ * Samsung S3C64XX DMA support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++#include +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/fimc.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/fimc.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/fimc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/fimc.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,39 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/fimc.h ++ * ++ * Platform header file for Samsung Camera Interface (FIMC) driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _FIMC_H ++#define _FIMC_H ++ ++struct platform_device; ++ ++struct s3c_platform_fimc { ++ const char srclk_name[16]; ++ const char clk_name[16]; ++ u32 clockrate; ++ int line_length; ++ int nr_frames; ++ int shared_io; ++ ++ void (*cfg_gpio)(struct platform_device *dev); ++}; ++ ++extern void s3c_fimc0_set_platdata(struct s3c_platform_fimc *fimc); ++extern void s3c_fimc1_set_platdata(struct s3c_platform_fimc *fimc); ++ ++/* defined by architecture to configure gpio */ ++extern void s3c_fimc0_cfg_gpio(struct platform_device *dev); ++extern void s3c_fimc1_cfg_gpio(struct platform_device *dev); ++ ++extern void s3c_fimc_reset_camera(void); ++ ++#endif /* _FIMC_H */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,48 @@ ++/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank A register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S3C64XX_GPACON (S3C64XX_GPA_BASE + 0x00) ++#define S3C64XX_GPADAT (S3C64XX_GPA_BASE + 0x04) ++#define S3C64XX_GPAPUD (S3C64XX_GPA_BASE + 0x08) ++#define S3C64XX_GPACONSLP (S3C64XX_GPA_BASE + 0x0c) ++#define S3C64XX_GPAPUDSLP (S3C64XX_GPA_BASE + 0x10) ++ ++#define S3C64XX_GPA_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S3C64XX_GPA_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S3C64XX_GPA_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S3C64XX_GPA0_UART_RXD0 (0x02 << 0) ++#define S3C64XX_GPA0_EINT_G1_0 (0x07 << 0) ++ ++#define S3C64XX_GPA1_UART_TXD0 (0x02 << 4) ++#define S3C64XX_GPA1_EINT_G1_1 (0x07 << 4) ++ ++#define S3C64XX_GPA2_UART_nCTS0 (0x02 << 8) ++#define S3C64XX_GPA2_EINT_G1_2 (0x07 << 8) ++ ++#define S3C64XX_GPA3_UART_nRTS0 (0x02 << 12) ++#define S3C64XX_GPA3_EINT_G1_3 (0x07 << 12) ++ ++#define S3C64XX_GPA4_UART_RXD1 (0x02 << 16) ++#define S3C64XX_GPA4_EINT_G1_4 (0x07 << 16) ++ ++#define S3C64XX_GPA5_UART_TXD1 (0x02 << 20) ++#define S3C64XX_GPA5_EINT_G1_5 (0x07 << 20) ++ ++#define S3C64XX_GPA6_UART_nCTS1 (0x02 << 24) ++#define S3C64XX_GPA6_EINT_G1_6 (0x07 << 24) ++ ++#define S3C64XX_GPA7_UART_nRTS1 (0x02 << 28) ++#define S3C64XX_GPA7_EINT_G1_7 (0x07 << 28) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,60 @@ ++/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank B register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S3C64XX_GPBCON (S3C64XX_GPB_BASE + 0x00) ++#define S3C64XX_GPBDAT (S3C64XX_GPB_BASE + 0x04) ++#define S3C64XX_GPBPUD (S3C64XX_GPB_BASE + 0x08) ++#define S3C64XX_GPBCONSLP (S3C64XX_GPB_BASE + 0x0c) ++#define S3C64XX_GPBPUDSLP (S3C64XX_GPB_BASE + 0x10) ++ ++#define S3C64XX_GPB_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S3C64XX_GPB_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S3C64XX_GPB_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S3C64XX_GPB0_UART_RXD2 (0x02 << 0) ++#define S3C64XX_GPB0_EXTDMA_REQ (0x03 << 0) ++#define S3C64XX_GPB0_IrDA_RXD (0x04 << 0) ++#define S3C64XX_GPB0_ADDR_CF0 (0x05 << 0) ++#define S3C64XX_GPB0_EINT_G1_8 (0x07 << 0) ++ ++#define S3C64XX_GPB1_UART_TXD2 (0x02 << 4) ++#define S3C64XX_GPB1_EXTDMA_ACK (0x03 << 4) ++#define S3C64XX_GPB1_IrDA_TXD (0x04 << 4) ++#define S3C64XX_GPB1_ADDR_CF1 (0x05 << 4) ++#define S3C64XX_GPB1_EINT_G1_9 (0x07 << 4) ++ ++#define S3C64XX_GPB2_UART_RXD3 (0x02 << 8) ++#define S3C64XX_GPB2_IrDA_RXD (0x03 << 8) ++#define S3C64XX_GPB2_EXTDMA_REQ (0x04 << 8) ++#define S3C64XX_GPB2_ADDR_CF2 (0x05 << 8) ++#define S3C64XX_GPB2_I2C_SCL1 (0x06 << 8) ++#define S3C64XX_GPB2_EINT_G1_10 (0x07 << 8) ++ ++#define S3C64XX_GPB3_UART_TXD3 (0x02 << 12) ++#define S3C64XX_GPB3_IrDA_TXD (0x03 << 12) ++#define S3C64XX_GPB3_EXTDMA_ACK (0x04 << 12) ++#define S3C64XX_GPB3_I2C_SDA1 (0x06 << 12) ++#define S3C64XX_GPB3_EINT_G1_11 (0x07 << 12) ++ ++#define S3C64XX_GPB4_IrDA_SDBW (0x02 << 16) ++#define S3C64XX_GPB4_CAM_FIELD (0x03 << 16) ++#define S3C64XX_GPB4_CF_DATA_DIR (0x04 << 16) ++#define S3C64XX_GPB4_EINT_G1_12 (0x07 << 16) ++ ++#define S3C64XX_GPB5_I2C_SCL0 (0x02 << 20) ++#define S3C64XX_GPB5_EINT_G1_13 (0x07 << 20) ++ ++#define S3C64XX_GPB6_I2C_SDA0 (0x02 << 24) ++#define S3C64XX_GPB6_EINT_G1_14 (0x07 << 24) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,53 @@ ++/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank C register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S3C64XX_GPCCON (S3C64XX_GPC_BASE + 0x00) ++#define S3C64XX_GPCDAT (S3C64XX_GPC_BASE + 0x04) ++#define S3C64XX_GPCPUD (S3C64XX_GPC_BASE + 0x08) ++#define S3C64XX_GPCCONSLP (S3C64XX_GPC_BASE + 0x0c) ++#define S3C64XX_GPCPUDSLP (S3C64XX_GPC_BASE + 0x10) ++ ++#define S3C64XX_GPC_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S3C64XX_GPC_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S3C64XX_GPC_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S3C64XX_GPC0_SPI_MISO0 (0x02 << 0) ++#define S3C64XX_GPC0_EINT_G2_0 (0x07 << 0) ++ ++#define S3C64XX_GPC1_SPI_CLK0 (0x02 << 4) ++#define S3C64XX_GPC1_EINT_G2_1 (0x07 << 4) ++ ++#define S3C64XX_GPC2_SPI_MOSI0 (0x02 << 8) ++#define S3C64XX_GPC2_EINT_G2_2 (0x07 << 8) ++ ++#define S3C64XX_GPC3_SPI_nCS0 (0x02 << 12) ++#define S3C64XX_GPC3_EINT_G2_3 (0x07 << 12) ++ ++#define S3C64XX_GPC4_SPI_MISO1 (0x02 << 16) ++#define S3C64XX_GPC4_MMC2_CMD (0x03 << 16) ++#define S3C64XX_GPC4_I2S_V40_DO0 (0x05 << 16) ++#define S3C64XX_GPC4_EINT_G2_4 (0x07 << 16) ++ ++#define S3C64XX_GPC5_SPI_CLK1 (0x02 << 20) ++#define S3C64XX_GPC5_MMC2_CLK (0x03 << 20) ++#define S3C64XX_GPC5_I2S_V40_DO1 (0x05 << 20) ++#define S3C64XX_GPC5_EINT_G2_5 (0x07 << 20) ++ ++#define S3C64XX_GPC6_SPI_MOSI1 (0x02 << 24) ++#define S3C64XX_GPC6_EINT_G2_6 (0x07 << 24) ++ ++#define S3C64XX_GPC7_SPI_nCS1 (0x02 << 28) ++#define S3C64XX_GPC7_I2S_V40_DO2 (0x05 << 28) ++#define S3C64XX_GPC7_EINT_G2_7 (0x07 << 28) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,49 @@ ++/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank D register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S3C64XX_GPDCON (S3C64XX_GPD_BASE + 0x00) ++#define S3C64XX_GPDDAT (S3C64XX_GPD_BASE + 0x04) ++#define S3C64XX_GPDPUD (S3C64XX_GPD_BASE + 0x08) ++#define S3C64XX_GPDCONSLP (S3C64XX_GPD_BASE + 0x0c) ++#define S3C64XX_GPDPUDSLP (S3C64XX_GPD_BASE + 0x10) ++ ++#define S3C64XX_GPD_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S3C64XX_GPD_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S3C64XX_GPD_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S3C64XX_GPD0_PCM0_SCLK (0x02 << 0) ++#define S3C64XX_GPD0_I2S0_CLK (0x03 << 0) ++#define S3C64XX_GPD0_AC97_BITCLK (0x04 << 0) ++#define S3C64XX_GPD0_EINT_G3_0 (0x07 << 0) ++ ++#define S3C64XX_GPD1_PCM0_EXTCLK (0x02 << 4) ++#define S3C64XX_GPD1_I2S0_CDCLK (0x03 << 4) ++#define S3C64XX_GPD1_AC97_nRESET (0x04 << 4) ++#define S3C64XX_GPD1_EINT_G3_1 (0x07 << 4) ++ ++#define S3C64XX_GPD2_PCM0_FSYNC (0x02 << 8) ++#define S3C64XX_GPD2_I2S0_LRCLK (0x03 << 8) ++#define S3C64XX_GPD2_AC97_SYNC (0x04 << 8) ++#define S3C64XX_GPD2_EINT_G3_2 (0x07 << 8) ++ ++#define S3C64XX_GPD3_PCM0_SIN (0x02 << 12) ++#define S3C64XX_GPD3_I2S0_DI (0x03 << 12) ++#define S3C64XX_GPD3_AC97_SDI (0x04 << 12) ++#define S3C64XX_GPD3_EINT_G3_3 (0x07 << 12) ++ ++#define S3C64XX_GPD4_PCM0_SOUT (0x02 << 16) ++#define S3C64XX_GPD4_I2S0_DO (0x03 << 16) ++#define S3C64XX_GPD4_AC97_SDO (0x04 << 16) ++#define S3C64XX_GPD4_EINT_G3_4 (0x07 << 16) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,44 @@ ++/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank E register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S3C64XX_GPECON (S3C64XX_GPE_BASE + 0x00) ++#define S3C64XX_GPEDAT (S3C64XX_GPE_BASE + 0x04) ++#define S3C64XX_GPEPUD (S3C64XX_GPE_BASE + 0x08) ++#define S3C64XX_GPECONSLP (S3C64XX_GPE_BASE + 0x0c) ++#define S3C64XX_GPEPUDSLP (S3C64XX_GPE_BASE + 0x10) ++ ++#define S3C64XX_GPE_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S3C64XX_GPE_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S3C64XX_GPE_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S3C64XX_GPE0_PCM1_SCLK (0x02 << 0) ++#define S3C64XX_GPE0_I2S1_CLK (0x03 << 0) ++#define S3C64XX_GPE0_AC97_BITCLK (0x04 << 0) ++ ++#define S3C64XX_GPE1_PCM1_EXTCLK (0x02 << 4) ++#define S3C64XX_GPE1_I2S1_CDCLK (0x03 << 4) ++#define S3C64XX_GPE1_AC97_nRESET (0x04 << 4) ++ ++#define S3C64XX_GPE2_PCM1_FSYNC (0x02 << 8) ++#define S3C64XX_GPE2_I2S1_LRCLK (0x03 << 8) ++#define S3C64XX_GPE2_AC97_SYNC (0x04 << 8) ++ ++#define S3C64XX_GPE3_PCM1_SIN (0x02 << 12) ++#define S3C64XX_GPE3_I2S1_DI (0x03 << 12) ++#define S3C64XX_GPE3_AC97_SDI (0x04 << 12) ++ ++#define S3C64XX_GPE4_PCM1_SOUT (0x02 << 16) ++#define S3C64XX_GPE4_I2S1_D0 (0x03 << 16) ++#define S3C64XX_GPE4_AC97_SDO (0x04 << 16) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,71 @@ ++/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank F register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S3C64XX_GPFCON (S3C64XX_GPF_BASE + 0x00) ++#define S3C64XX_GPFDAT (S3C64XX_GPF_BASE + 0x04) ++#define S3C64XX_GPFPUD (S3C64XX_GPF_BASE + 0x08) ++#define S3C64XX_GPFCONSLP (S3C64XX_GPF_BASE + 0x0c) ++#define S3C64XX_GPFPUDSLP (S3C64XX_GPF_BASE + 0x10) ++ ++#define S3C64XX_GPF_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) ++#define S3C64XX_GPF_INPUT(__gpio) (0x0 << ((__gpio) * 2)) ++#define S3C64XX_GPF_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) ++ ++#define S3C64XX_GPF0_CAMIF_CLK (0x02 << 0) ++#define S3C64XX_GPF0_EINT_G4_0 (0x03 << 0) ++ ++#define S3C64XX_GPF1_CAMIF_HREF (0x02 << 2) ++#define S3C64XX_GPF1_EINT_G4_1 (0x03 << 2) ++ ++#define S3C64XX_GPF2_CAMIF_PCLK (0x02 << 4) ++#define S3C64XX_GPF2_EINT_G4_2 (0x03 << 4) ++ ++#define S3C64XX_GPF3_CAMIF_nRST (0x02 << 6) ++#define S3C64XX_GPF3_EINT_G4_3 (0x03 << 6) ++ ++#define S3C64XX_GPF4_CAMIF_VSYNC (0x02 << 8) ++#define S3C64XX_GPF4_EINT_G4_4 (0x03 << 8) ++ ++#define S3C64XX_GPF5_CAMIF_YDATA0 (0x02 << 10) ++#define S3C64XX_GPF5_EINT_G4_5 (0x03 << 10) ++ ++#define S3C64XX_GPF6_CAMIF_YDATA1 (0x02 << 12) ++#define S3C64XX_GPF6_EINT_G4_6 (0x03 << 12) ++ ++#define S3C64XX_GPF7_CAMIF_YDATA2 (0x02 << 14) ++#define S3C64XX_GPF7_EINT_G4_7 (0x03 << 14) ++ ++#define S3C64XX_GPF8_CAMIF_YDATA3 (0x02 << 16) ++#define S3C64XX_GPF8_EINT_G4_8 (0x03 << 16) ++ ++#define S3C64XX_GPF9_CAMIF_YDATA4 (0x02 << 18) ++#define S3C64XX_GPF9_EINT_G4_9 (0x03 << 18) ++ ++#define S3C64XX_GPF10_CAMIF_YDATA5 (0x02 << 20) ++#define S3C64XX_GPF10_EINT_G4_10 (0x03 << 20) ++ ++#define S3C64XX_GPF11_CAMIF_YDATA6 (0x02 << 22) ++#define S3C64XX_GPF11_EINT_G4_11 (0x03 << 22) ++ ++#define S3C64XX_GPF12_CAMIF_YDATA7 (0x02 << 24) ++#define S3C64XX_GPF12_EINT_G4_12 (0x03 << 24) ++ ++#define S3C64XX_GPF13_PWM_ECLK (0x02 << 26) ++#define S3C64XX_GPF13_EINT_G4_13 (0x03 << 26) ++ ++#define S3C64XX_GPF14_PWM_TOUT0 (0x02 << 28) ++#define S3C64XX_GPF14_CLKOUT0 (0x03 << 28) ++ ++#define S3C64XX_GPF15_PWM_TOUT1 (0x02 << 30) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,45 @@ ++/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank G register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S3C64XX_GPGCON (S3C64XX_GPG_BASE + 0x00) ++#define S3C64XX_GPGDAT (S3C64XX_GPG_BASE + 0x04) ++#define S3C64XX_GPGPUD (S3C64XX_GPG_BASE + 0x08) ++#define S3C64XX_GPGCONSLP (S3C64XX_GPG_BASE + 0x0c) ++#define S3C64XX_GPGPUDSLP (S3C64XX_GPG_BASE + 0x10) ++ ++#define S3C64XX_GPG_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S3C64XX_GPG_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S3C64XX_GPG_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S3C64XX_GPG0_MMC0_CLK (0x02 << 0) ++#define S3C64XX_GPG0_EINT_G5_0 (0x07 << 0) ++ ++#define S3C64XX_GPG1_MMC0_CMD (0x02 << 4) ++#define S3C64XX_GPG1_EINT_G5_1 (0x07 << 4) ++ ++#define S3C64XX_GPG2_MMC0_DATA0 (0x02 << 8) ++#define S3C64XX_GPG2_EINT_G5_2 (0x07 << 8) ++ ++#define S3C64XX_GPG3_MMC0_DATA1 (0x02 << 12) ++#define S3C64XX_GPG3_EINT_G5_3 (0x07 << 12) ++ ++#define S3C64XX_GPG4_MMC0_DATA2 (0x02 << 16) ++#define S3C64XX_GPG4_EINT_G5_4 (0x07 << 16) ++ ++#define S3C64XX_GPG5_MMC0_DATA3 (0x02 << 20) ++#define S3C64XX_GPG5_EINT_G5_5 (0x07 << 20) ++ ++#define S3C64XX_GPG6_MMC0_CD (0x02 << 24) ++#define S3C64XX_GPG6_MMC1_CD (0x03 << 24) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,74 @@ ++/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank H register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S3C64XX_GPHCON0 (S3C64XX_GPH_BASE + 0x00) ++#define S3C64XX_GPHCON1 (S3C64XX_GPH_BASE + 0x04) ++#define S3C64XX_GPHDAT (S3C64XX_GPH_BASE + 0x08) ++#define S3C64XX_GPHPUD (S3C64XX_GPH_BASE + 0x0c) ++#define S3C64XX_GPHCONSLP (S3C64XX_GPH_BASE + 0x10) ++#define S3C64XX_GPHPUDSLP (S3C64XX_GPH_BASE + 0x14) ++ ++#define S3C64XX_GPH_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S3C64XX_GPH_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S3C64XX_GPH_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S3C64XX_GPH0_MMC1_CLK (0x02 << 0) ++#define S3C64XX_GPH0_KP_COL0 (0x04 << 0) ++#define S3C64XX_GPH0_EINT_G6_0 (0x07 << 0) ++ ++#define S3C64XX_GPH1_MMC1_CMD (0x02 << 4) ++#define S3C64XX_GPH1_KP_COL1 (0x04 << 4) ++#define S3C64XX_GPH1_EINT_G6_1 (0x07 << 4) ++ ++#define S3C64XX_GPH2_MMC1_DATA0 (0x02 << 8) ++#define S3C64XX_GPH2_KP_COL2 (0x04 << 8) ++#define S3C64XX_GPH2_EINT_G6_2 (0x07 << 8) ++ ++#define S3C64XX_GPH3_MMC1_DATA1 (0x02 << 12) ++#define S3C64XX_GPH3_KP_COL3 (0x04 << 12) ++#define S3C64XX_GPH3_EINT_G6_3 (0x07 << 12) ++ ++#define S3C64XX_GPH4_MMC1_DATA2 (0x02 << 16) ++#define S3C64XX_GPH4_KP_COL4 (0x04 << 16) ++#define S3C64XX_GPH4_EINT_G6_4 (0x07 << 16) ++ ++#define S3C64XX_GPH5_MMC1_DATA3 (0x02 << 20) ++#define S3C64XX_GPH5_KP_COL5 (0x04 << 20) ++#define S3C64XX_GPH5_EINT_G6_5 (0x07 << 20) ++ ++#define S3C64XX_GPH6_MMC1_DATA4 (0x02 << 24) ++#define S3C64XX_GPH6_MMC2_DATA0 (0x03 << 24) ++#define S3C64XX_GPH6_KP_COL6 (0x04 << 24) ++#define S3C64XX_GPH6_I2S_V40_BCLK (0x05 << 24) ++#define S3C64XX_GPH6_ADDR_CF0 (0x06 << 24) ++#define S3C64XX_GPH6_EINT_G6_6 (0x07 << 24) ++ ++#define S3C64XX_GPH7_MMC1_DATA5 (0x02 << 28) ++#define S3C64XX_GPH7_MMC2_DATA1 (0x03 << 28) ++#define S3C64XX_GPH7_KP_COL7 (0x04 << 28) ++#define S3C64XX_GPH7_I2S_V40_CDCLK (0x05 << 28) ++#define S3C64XX_GPH7_ADDR_CF1 (0x06 << 28) ++#define S3C64XX_GPH7_EINT_G6_7 (0x07 << 28) ++ ++#define S3C64XX_GPH8_MMC1_DATA6 (0x02 << 0) ++#define S3C64XX_GPH8_MMC2_DATA2 (0x03 << 0) ++#define S3C64XX_GPH8_I2S_V40_LRCLK (0x05 << 0) ++#define S3C64XX_GPH8_ADDR_CF2 (0x06 << 0) ++#define S3C64XX_GPH8_EINT_G6_8 (0x07 << 0) ++ ++#define S3C64XX_GPH9_MMC1_DATA7 (0x02 << 4) ++#define S3C64XX_GPH9_MMC2_DATA3 (0x03 << 4) ++#define S3C64XX_GPH9_I2S_V40_DI (0x05 << 4) ++#define S3C64XX_GPH9_EINT_G6_9 (0x07 << 4) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,40 @@ ++/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank I register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S3C64XX_GPICON (S3C64XX_GPI_BASE + 0x00) ++#define S3C64XX_GPIDAT (S3C64XX_GPI_BASE + 0x04) ++#define S3C64XX_GPIPUD (S3C64XX_GPI_BASE + 0x08) ++#define S3C64XX_GPICONSLP (S3C64XX_GPI_BASE + 0x0c) ++#define S3C64XX_GPIPUDSLP (S3C64XX_GPI_BASE + 0x10) ++ ++#define S3C64XX_GPI_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) ++#define S3C64XX_GPI_INPUT(__gpio) (0x0 << ((__gpio) * 2)) ++#define S3C64XX_GPI_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) ++ ++#define S3C64XX_GPI0_VD0 (0x02 << 0) ++#define S3C64XX_GPI1_VD1 (0x02 << 2) ++#define S3C64XX_GPI2_VD2 (0x02 << 4) ++#define S3C64XX_GPI3_VD3 (0x02 << 6) ++#define S3C64XX_GPI4_VD4 (0x02 << 8) ++#define S3C64XX_GPI5_VD5 (0x02 << 10) ++#define S3C64XX_GPI6_VD6 (0x02 << 12) ++#define S3C64XX_GPI7_VD7 (0x02 << 14) ++#define S3C64XX_GPI8_VD8 (0x02 << 16) ++#define S3C64XX_GPI9_VD9 (0x02 << 18) ++#define S3C64XX_GPI10_VD10 (0x02 << 20) ++#define S3C64XX_GPI11_VD11 (0x02 << 22) ++#define S3C64XX_GPI12_VD12 (0x02 << 24) ++#define S3C64XX_GPI13_VD13 (0x02 << 26) ++#define S3C64XX_GPI14_VD14 (0x02 << 28) ++#define S3C64XX_GPI15_VD15 (0x02 << 30) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,36 @@ ++/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank J register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S3C64XX_GPJCON (S3C64XX_GPJ_BASE + 0x00) ++#define S3C64XX_GPJDAT (S3C64XX_GPJ_BASE + 0x04) ++#define S3C64XX_GPJPUD (S3C64XX_GPJ_BASE + 0x08) ++#define S3C64XX_GPJCONSLP (S3C64XX_GPJ_BASE + 0x0c) ++#define S3C64XX_GPJPUDSLP (S3C64XX_GPJ_BASE + 0x10) ++ ++#define S3C64XX_GPJ_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) ++#define S3C64XX_GPJ_INPUT(__gpio) (0x0 << ((__gpio) * 2)) ++#define S3C64XX_GPJ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) ++ ++#define S3C64XX_GPJ0_VD16 (0x02 << 0) ++#define S3C64XX_GPJ1_VD17 (0x02 << 2) ++#define S3C64XX_GPJ2_VD18 (0x02 << 4) ++#define S3C64XX_GPJ3_VD19 (0x02 << 6) ++#define S3C64XX_GPJ4_VD20 (0x02 << 8) ++#define S3C64XX_GPJ5_VD21 (0x02 << 10) ++#define S3C64XX_GPJ6_VD22 (0x02 << 12) ++#define S3C64XX_GPJ7_VD23 (0x02 << 14) ++#define S3C64XX_GPJ8_LCD_HSYNC (0x02 << 16) ++#define S3C64XX_GPJ9_LCD_VSYNC (0x02 << 18) ++#define S3C64XX_GPJ10_LCD_VDEN (0x02 << 20) ++#define S3C64XX_GPJ11_LCD_VCLK (0x02 << 22) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-k.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-k.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-k.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-k.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,24 @@ ++/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-kj.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank J register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S3C64XX_GPKCON (S3C64XX_GPK_BASE + 0x00) ++#define S3C64XX_GPKCON1 (S3C64XX_GPK_BASE + 0x04) ++#define S3C64XX_GPKDAT (S3C64XX_GPK_BASE + 0x08) ++#define S3C64XX_GPKPUD (S3C64XX_GPK_BASE + 0x0c) ++ ++#define S3C64XX_GPK_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) ++#define S3C64XX_GPK_INPUT(__gpio) (0x0 << ((__gpio) * 2)) ++#define S3C64XX_GPK_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-l.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-l.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-l.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-l.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,24 @@ ++/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-l.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank J register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S3C64XX_GPLCON (S3C64XX_GPL_BASE + 0x00) ++#define S3C64XX_GPLCON1 (S3C64XX_GPL_BASE + 0x04) ++#define S3C64XX_GPLDAT (S3C64XX_GPL_BASE + 0x08) ++#define S3C64XX_GPLPUD (S3C64XX_GPL_BASE + 0x0c) ++ ++#define S3C64XX_GPL_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) ++#define S3C64XX_GPL_INPUT(__gpio) (0x0 << ((__gpio) * 2)) ++#define S3C64XX_GPL_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-m.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-m.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-m.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-m.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,63 @@ ++/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-m.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank M register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S3C64XX_GPMCON (S3C64XX_GPM_BASE + 0x00) ++#define S3C64XX_GPMDAT (S3C64XX_GPM_BASE + 0x04) ++#define S3C64XX_GPMPUD (S3C64XX_GPM_BASE + 0x08) ++ ++#define S3C64XX_GPM_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) ++#define S3C64XX_GPM_INPUT(__gpio) (0x0 << ((__gpio) * 2)) ++#define S3C64XX_GPM_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) ++ ++#define S3C64XX_GPM0_HOSTIF_CS (0x02 << 0) ++#define S3C64XX_GPM0_EINT23 (0x03 << 0) ++#define S3C64XX_GPM0_RESERVED1 (0x04 << 0) ++#define S3C64XX_GPM0_DATA_CF10 (0x05 << 0) ++#define S3C64XX_GPM0_CE_CF0 (0x06 << 0) ++#define S3C64XX_GPM0_RESERVED2 (0x07 << 0) ++ ++#define S3C64XX_GPM1_HOSTIF_CS_M (0x02 << 0) ++#define S3C64XX_GPM1_EINT24 (0x03 << 0) ++#define S3C64XX_GPM1_RESERVED1 (0x04 << 0) ++#define S3C64XX_GPM1_DATA_CF11 (0x05 << 0) ++#define S3C64XX_GPM1_CE_CF1 (0x06 << 0) ++#define S3C64XX_GPM1_RESERVED2 (0x07 << 0) ++ ++#define S3C64XX_GPM2_HOSTIF_IF_CS_S (0x02 << 0) ++#define S3C64XX_GPM2_EINT25 (0x03 << 0) ++#define S3C64XX_GPM2_HOSTIF_MDP_VSYNC (0x04 << 0) ++#define S3C64XX_GPM2_DATA_CF12 (0x05 << 0) ++#define S3C64XX_GPM2_IORD_CF (0x06 << 0) ++#define S3C64XX_GPM2_RESERVED2 (0x07 << 0) ++ ++#define S3C64XX_GPM3_HOSTIF_WE (0x02 << 0) ++#define S3C64XX_GPM3_EINT26 (0x03 << 0) ++#define S3C64XX_GPM3_RESERVED1 (0x04 << 0) ++#define S3C64XX_GPM3_DATA_CF13 (0x05 << 0) ++#define S3C64XX_GPM3_IOWR_CF (0x06 << 0) ++#define S3C64XX_GPM3_RESERVED2 (0x07 << 0) ++ ++#define S3C64XX_GPM4_HOSTIF_OE (0x02 << 0) ++#define S3C64XX_GPM4_EINT27 (0x03 << 0) ++#define S3C64XX_GPM4_RESERVED1 (0x04 << 0) ++#define S3C64XX_GPM4_DATA_CF14 (0x05 << 0) ++#define S3C64XX_GPM4_IORDY_CF (0x06 << 0) ++#define S3C64XX_GPM4_RESERVED2 (0x07 << 0) ++ ++#define S3C64XX_GPM5_HOSTIF_INTR (0x02 << 0) ++#define S3C64XX_GPM5_CF_DATA_DIR (0x03 << 0) ++#define S3C64XX_GPM5_RESERVED1 (0x04 << 0) ++#define S3C64XX_GPM5_DATA_CF15 (0x05 << 0) ++#define S3C64XX_GPM5_RESERVED2 (0x06 << 0) ++#define S3C64XX_GPM5_RESERVED3 (0x07 << 0) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,54 @@ ++/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank N register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00) ++#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04) ++#define S3C64XX_GPNPUD (S3C64XX_GPN_BASE + 0x08) ++ ++#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) ++#define S3C64XX_GPN_INPUT(__gpio) (0x0 << ((__gpio) * 2)) ++#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) ++ ++#define S3C64XX_GPN0_EINT0 (0x02 << 0) ++#define S3C64XX_GPN0_KP_ROW0 (0x03 << 0) ++ ++#define S3C64XX_GPN1_EINT1 (0x02 << 2) ++#define S3C64XX_GPN1_KP_ROW1 (0x03 << 2) ++ ++#define S3C64XX_GPN2_EINT2 (0x02 << 4) ++#define S3C64XX_GPN2_KP_ROW2 (0x03 << 4) ++ ++#define S3C64XX_GPN3_EINT3 (0x02 << 6) ++#define S3C64XX_GPN3_KP_ROW3 (0x03 << 6) ++ ++#define S3C64XX_GPN4_EINT4 (0x02 << 8) ++#define S3C64XX_GPN4_KP_ROW4 (0x03 << 8) ++ ++#define S3C64XX_GPN5_EINT5 (0x02 << 10) ++#define S3C64XX_GPN5_KP_ROW5 (0x03 << 10) ++ ++#define S3C64XX_GPN6_EINT6 (0x02 << 12) ++#define S3C64XX_GPN6_KP_ROW6 (0x03 << 12) ++ ++#define S3C64XX_GPN7_EINT7 (0x02 << 14) ++#define S3C64XX_GPN7_KP_ROW7 (0x03 << 14) ++ ++#define S3C64XX_GPN8_EINT8 (0x02 << 16) ++#define S3C64XX_GPN9_EINT9 (0x02 << 18) ++#define S3C64XX_GPN10_EINT10 (0x02 << 20) ++#define S3C64XX_GPN11_EINT11 (0x02 << 22) ++#define S3C64XX_GPN12_EINT12 (0x02 << 24) ++#define S3C64XX_GPN13_EINT13 (0x02 << 26) ++#define S3C64XX_GPN14_EINT14 (0x02 << 28) ++#define S3C64XX_GPN15_EINT15 (0x02 << 30) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,70 @@ ++/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank O register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S3C64XX_GPOCON (S3C64XX_GPO_BASE + 0x00) ++#define S3C64XX_GPODAT (S3C64XX_GPO_BASE + 0x04) ++#define S3C64XX_GPOPUD (S3C64XX_GPO_BASE + 0x08) ++#define S3C64XX_GPOCONSLP (S3C64XX_GPO_BASE + 0x0c) ++#define S3C64XX_GPOPUDSLP (S3C64XX_GPO_BASE + 0x10) ++ ++#define S3C64XX_GPO_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) ++#define S3C64XX_GPO_INPUT(__gpio) (0x0 << ((__gpio) * 2)) ++#define S3C64XX_GPO_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) ++ ++#define S3C64XX_GPO0_MEM0_nCS2 (0x02 << 0) ++#define S3C64XX_GPO0_EINT_G7_0 (0x03 << 0) ++ ++#define S3C64XX_GPO1_MEM0_nCS3 (0x02 << 2) ++#define S3C64XX_GPO1_EINT_G7_1 (0x03 << 2) ++ ++#define S3C64XX_GPO2_MEM0_nCS4 (0x02 << 4) ++#define S3C64XX_GPO2_EINT_G7_2 (0x03 << 4) ++ ++#define S3C64XX_GPO3_MEM0_nCS5 (0x02 << 6) ++#define S3C64XX_GPO3_EINT_G7_3 (0x03 << 6) ++ ++#define S3C64XX_GPO4_EINT_G7_4 (0x03 << 8) ++ ++#define S3C64XX_GPO5_EINT_G7_5 (0x03 << 10) ++ ++#define S3C64XX_GPO6_MEM0_ADDR6 (0x02 << 12) ++#define S3C64XX_GPO6_EINT_G7_6 (0x03 << 12) ++ ++#define S3C64XX_GPO7_MEM0_ADDR7 (0x02 << 14) ++#define S3C64XX_GPO7_EINT_G7_7 (0x03 << 14) ++ ++#define S3C64XX_GPO8_MEM0_ADDR8 (0x02 << 16) ++#define S3C64XX_GPO8_EINT_G7_8 (0x03 << 16) ++ ++#define S3C64XX_GPO9_MEM0_ADDR9 (0x02 << 18) ++#define S3C64XX_GPO9_EINT_G7_9 (0x03 << 18) ++ ++#define S3C64XX_GPO10_MEM0_ADDR10 (0x02 << 20) ++#define S3C64XX_GPO10_EINT_G7_10 (0x03 << 20) ++ ++#define S3C64XX_GPO11_MEM0_ADDR11 (0x02 << 22) ++#define S3C64XX_GPO11_EINT_G7_11 (0x03 << 22) ++ ++#define S3C64XX_GPO12_MEM0_ADDR12 (0x02 << 24) ++#define S3C64XX_GPO12_EINT_G7_12 (0x03 << 24) ++ ++#define S3C64XX_GPO13_MEM0_ADDR13 (0x02 << 26) ++#define S3C64XX_GPO13_EINT_G7_13 (0x03 << 26) ++ ++#define S3C64XX_GPO14_MEM0_ADDR14 (0x02 << 28) ++#define S3C64XX_GPO14_EINT_G7_14 (0x03 << 28) ++ ++#define S3C64XX_GPO15_MEM0_ADDR15 (0x02 << 30) ++#define S3C64XX_GPO15_EINT_G7_15 (0x03 << 30) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,69 @@ ++/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank P register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S3C64XX_GPPCON (S3C64XX_GPP_BASE + 0x00) ++#define S3C64XX_GPPDAT (S3C64XX_GPP_BASE + 0x04) ++#define S3C64XX_GPPPUD (S3C64XX_GPP_BASE + 0x08) ++#define S3C64XX_GPPCONSLP (S3C64XX_GPP_BASE + 0x0c) ++#define S3C64XX_GPPPUDSLP (S3C64XX_GPP_BASE + 0x10) ++ ++#define S3C64XX_GPP_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) ++#define S3C64XX_GPP_INPUT(__gpio) (0x0 << ((__gpio) * 2)) ++#define S3C64XX_GPP_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) ++ ++#define S3C64XX_GPP0_MEM0_ADDRV (0x02 << 0) ++#define S3C64XX_GPP0_EINT_G8_0 (0x03 << 0) ++ ++#define S3C64XX_GPP1_MEM0_SMCLK (0x02 << 2) ++#define S3C64XX_GPP1_EINT_G8_1 (0x03 << 2) ++ ++#define S3C64XX_GPP2_MEM0_nWAIT (0x02 << 4) ++#define S3C64XX_GPP2_EINT_G8_2 (0x03 << 4) ++ ++#define S3C64XX_GPP3_MEM0_RDY0_ALE (0x02 << 6) ++#define S3C64XX_GPP3_EINT_G8_3 (0x03 << 6) ++ ++#define S3C64XX_GPP4_MEM0_RDY1_CLE (0x02 << 8) ++#define S3C64XX_GPP4_EINT_G8_4 (0x03 << 8) ++ ++#define S3C64XX_GPP5_MEM0_INTsm0_FWE (0x02 << 10) ++#define S3C64XX_GPP5_EINT_G8_5 (0x03 << 10) ++ ++#define S3C64XX_GPP6_MEM0_(null) (0x02 << 12) ++#define S3C64XX_GPP6_EINT_G8_6 (0x03 << 12) ++ ++#define S3C64XX_GPP7_MEM0_INTsm1_FRE (0x02 << 14) ++#define S3C64XX_GPP7_EINT_G8_7 (0x03 << 14) ++ ++#define S3C64XX_GPP8_MEM0_RPn_RnB (0x02 << 16) ++#define S3C64XX_GPP8_EINT_G8_8 (0x03 << 16) ++ ++#define S3C64XX_GPP9_MEM0_ATA_RESET (0x02 << 18) ++#define S3C64XX_GPP9_EINT_G8_9 (0x03 << 18) ++ ++#define S3C64XX_GPP10_MEM0_ATA_INPACK (0x02 << 20) ++#define S3C64XX_GPP10_EINT_G8_10 (0x03 << 20) ++ ++#define S3C64XX_GPP11_MEM0_ATA_REG (0x02 << 22) ++#define S3C64XX_GPP11_EINT_G8_11 (0x03 << 22) ++ ++#define S3C64XX_GPP12_MEM0_ATA_WE (0x02 << 24) ++#define S3C64XX_GPP12_EINT_G8_12 (0x03 << 24) ++ ++#define S3C64XX_GPP13_MEM0_ATA_OE (0x02 << 26) ++#define S3C64XX_GPP13_EINT_G8_13 (0x03 << 26) ++ ++#define S3C64XX_GPP14_MEM0_ATA_CD (0x02 << 28) ++#define S3C64XX_GPP14_EINT_G8_14 (0x03 << 28) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,46 @@ ++/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank Q register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S3C64XX_GPQCON (S3C64XX_GPQ_BASE + 0x00) ++#define S3C64XX_GPQDAT (S3C64XX_GPQ_BASE + 0x04) ++#define S3C64XX_GPQPUD (S3C64XX_GPQ_BASE + 0x08) ++#define S3C64XX_GPQCONSLP (S3C64XX_GPQ_BASE + 0x0c) ++#define S3C64XX_GPQPUDSLP (S3C64XX_GPQ_BASE + 0x10) ++ ++#define S3C64XX_GPQ_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) ++#define S3C64XX_GPQ_INPUT(__gpio) (0x0 << ((__gpio) * 2)) ++#define S3C64XX_GPQ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) ++ ++#define S3C64XX_GPQ0_MEM0_ADDR18_RAS (0x02 << 0) ++#define S3C64XX_GPQ0_EINT_G9_0 (0x03 << 0) ++ ++#define S3C64XX_GPQ1_MEM0_ADDR19_CAS (0x02 << 2) ++#define S3C64XX_GPQ1_EINT_G9_1 (0x03 << 2) ++ ++#define S3C64XX_GPQ2_EINT_G9_2 (0x03 << 4) ++ ++#define S3C64XX_GPQ3_EINT_G9_3 (0x03 << 6) ++ ++#define S3C64XX_GPQ4_EINT_G9_4 (0x03 << 8) ++ ++#define S3C64XX_GPQ5_EINT_G9_5 (0x03 << 10) ++ ++#define S3C64XX_GPQ6_EINT_G9_6 (0x03 << 12) ++ ++#define S3C64XX_GPQ7_MEM0_ADDR17_WENDMC (0x02 << 14) ++#define S3C64XX_GPQ7_EINT_G9_7 (0x03 << 14) ++ ++#define S3C64XX_GPQ8_MEM0_ADDR16_APDMC (0x02 << 16) ++#define S3C64XX_GPQ8_EINT_G9_8 (0x03 << 16) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/irqs.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/irqs.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/irqs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/irqs.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,201 @@ ++/* linux/arch/arm/plat-s3c64xx/include/plat/irqs.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C64XX - Common IRQ support ++ */ ++ ++#ifndef __ASM_PLAT_S3C64XX_IRQS_H ++#define __ASM_PLAT_S3C64XX_IRQS_H __FILE__ ++ ++/* we keep the first set of CPU IRQs out of the range of ++ * the ISA space, so that the PC104 has them to itself ++ * and we don't end up having to do horrible things to the ++ * standard ISA drivers.... ++ * ++ * note, since we're using the VICs, our start must be a ++ * mulitple of 32 to allow the common code to work ++ */ ++ ++#define S3C_IRQ_OFFSET (32) ++ ++#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) ++ ++#define S3C_VIC0_BASE S3C_IRQ(0) ++#define S3C_VIC1_BASE S3C_IRQ(32) ++ ++/* UART interrupts, each UART has 4 intterupts per channel so ++ * use the space between the ISA and S3C main interrupts. Note, these ++ * are not in the same order as the S3C24XX series! */ ++ ++#define IRQ_S3CUART_BASE0 (16) ++#define IRQ_S3CUART_BASE1 (20) ++#define IRQ_S3CUART_BASE2 (24) ++#define IRQ_S3CUART_BASE3 (28) ++ ++#define UART_IRQ_RXD (0) ++#define UART_IRQ_ERR (1) ++#define UART_IRQ_TXD (2) ++#define UART_IRQ_MODEM (3) ++ ++#define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD) ++#define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD) ++#define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR) ++ ++#define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD) ++#define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD) ++#define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR) ++ ++#define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD) ++#define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD) ++#define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR) ++ ++#define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD) ++#define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD) ++#define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR) ++ ++/* VIC based IRQs */ ++ ++#define S3C64XX_IRQ_VIC0(x) (S3C_VIC0_BASE + (x)) ++#define S3C64XX_IRQ_VIC1(x) (S3C_VIC1_BASE + (x)) ++ ++/* VIC0 */ ++ ++#define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0) ++#define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1) ++#define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2) ++#define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3) ++#define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4) ++#define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5) ++#define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5) ++#define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6) ++#define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6) ++#define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7) ++#define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8) ++#define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8) ++#define IRQ_POST0 S3C64XX_IRQ_VIC0(9) ++#define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10) ++#define IRQ_2D S3C64XX_IRQ_VIC0(11) ++#define IRQ_TVENC S3C64XX_IRQ_VIC0(12) ++#define IRQ_SCALER S3C64XX_IRQ_VIC0(13) ++#define IRQ_BATF S3C64XX_IRQ_VIC0(14) ++#define IRQ_JPEG S3C64XX_IRQ_VIC0(15) ++#define IRQ_MFC S3C64XX_IRQ_VIC0(16) ++#define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17) ++#define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18) ++#define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19) ++#define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20) ++#define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21) ++#define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22) ++#define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23) ++#define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24) ++#define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25) ++#define IRQ_WDT S3C64XX_IRQ_VIC0(26) ++#define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27) ++#define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28) ++#define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29) ++#define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30) ++#define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31) ++ ++/* VIC1 */ ++ ++#define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0) ++#define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1) ++#define IRQ_PCM0 S3C64XX_IRQ_VIC1(2) ++#define IRQ_PCM1 S3C64XX_IRQ_VIC1(3) ++#define IRQ_AC97 S3C64XX_IRQ_VIC1(4) ++#define IRQ_UART0 S3C64XX_IRQ_VIC1(5) ++#define IRQ_UART1 S3C64XX_IRQ_VIC1(6) ++#define IRQ_UART2 S3C64XX_IRQ_VIC1(7) ++#define IRQ_UART3 S3C64XX_IRQ_VIC1(8) ++#define IRQ_DMA0 S3C64XX_IRQ_VIC1(9) ++#define IRQ_DMA1 S3C64XX_IRQ_VIC1(10) ++#define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11) ++#define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12) ++#define IRQ_NFC S3C64XX_IRQ_VIC1(13) ++#define IRQ_CFCON S3C64XX_IRQ_VIC1(14) ++#define IRQ_UHOST S3C64XX_IRQ_VIC1(15) ++#define IRQ_SPI0 S3C64XX_IRQ_VIC1(16) ++#define IRQ_SPI1 S3C64XX_IRQ_VIC1(17) ++#define IRQ_IIC S3C64XX_IRQ_VIC1(18) ++#define IRQ_HSItx S3C64XX_IRQ_VIC1(19) ++#define IRQ_HSIrx S3C64XX_IRQ_VIC1(20) ++#define IRQ_EINT_GROUPS S3C64XX_IRQ_VIC1(21) ++#define IRQ_MSM S3C64XX_IRQ_VIC1(22) ++#define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23) ++#define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24) ++#define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25) ++#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ ++#define IRQ_OTG S3C64XX_IRQ_VIC1(26) ++#define IRQ_IRDA S3C64XX_IRQ_VIC1(27) ++#define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28) ++#define IRQ_SEC S3C64XX_IRQ_VIC1(29) ++#define IRQ_PENDN S3C64XX_IRQ_VIC1(30) ++#define IRQ_TC IRQ_PENDN ++#define IRQ_ADC S3C64XX_IRQ_VIC1(31) ++ ++#define S3C64XX_TIMER_IRQ(x) S3C_IRQ(64 + (x)) ++ ++#define IRQ_TIMER0 S3C64XX_TIMER_IRQ(0) ++#define IRQ_TIMER1 S3C64XX_TIMER_IRQ(1) ++#define IRQ_TIMER2 S3C64XX_TIMER_IRQ(2) ++#define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3) ++#define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4) ++ ++/* compatibility for device defines */ ++ ++#define IRQ_IIC1 IRQ_S3C6410_IIC1 ++ ++/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series ++ * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE ++ * which we place after the pair of VICs. */ ++ ++#define S3C_IRQ_EINT_BASE S3C_IRQ(64+5) ++ ++#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) ++#define IRQ_EINT(x) S3C_EINT(x) ++ ++/* Next the external interrupt groups. These are similar to the IRQ_EINT(x) ++ * that they are sourced from the GPIO pins but with a different scheme for ++ * priority and source indication. ++ * ++ * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO ++ * interrupts, but for historical reasons they are kept apart from these ++ * next interrupts. ++ * ++ * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the ++ * machine specific support files. ++ */ ++ ++#define IRQ_EINT_GROUP1_NR (15) ++#define IRQ_EINT_GROUP2_NR (8) ++#define IRQ_EINT_GROUP3_NR (5) ++#define IRQ_EINT_GROUP4_NR (14) ++#define IRQ_EINT_GROUP5_NR (7) ++#define IRQ_EINT_GROUP6_NR (10) ++#define IRQ_EINT_GROUP7_NR (16) ++#define IRQ_EINT_GROUP8_NR (15) ++#define IRQ_EINT_GROUP9_NR (9) ++ ++#define IRQ_EINT_GROUP_BASE S3C_EINT(28) ++#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00) ++#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) ++#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) ++#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR) ++#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR) ++#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) ++#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) ++#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR) ++#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR) ++ ++#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##_BASE + (no)) ++ ++/* Set the default NR_IRQS */ ++ ++#define NR_IRQS (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) ++ ++#endif /* __ASM_PLAT_S3C64XX_IRQS_H */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/media.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/media.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/media.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/media.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,37 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/media.h ++ * ++ * Copyright 2009 Samsung Electronics ++ * Jinsung Yang ++ * http://samsungsemi.com/ ++ * ++ * Samsung Media device descriptions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef _S3C_MEDIA_H ++#define _S3C_MEDIA_H ++ ++#include ++ ++#define S3C_MDEV_FIMC 0 ++#define S3C_MDEV_POST 1 ++#define S3C_MDEV_TV 2 ++#define S3C_MDEV_MFC 3 ++#define S3C_MDEV_JPEG 4 ++#define S3C_MDEV_CMM 5 ++#define S3C_MDEV_MAX 6 ++ ++struct s3c_media_device { ++ int id; ++ const char *name; ++ size_t memsize; ++ dma_addr_t paddr; ++}; ++ ++extern dma_addr_t s3c_get_media_memory(int dev_id); ++extern size_t s3c_get_media_memsize(int dev_id); ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/pll.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/pll.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/pll.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/pll.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,74 @@ ++/* arch/arm/plat-s3c64xx/include/plat/pll.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C64XX PLL code ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S3C6400_PLL_MDIV_MASK ((1 << (25-16+1)) - 1) ++#define S3C6400_PLL_PDIV_MASK ((1 << (13-8+1)) - 1) ++#define S3C6400_PLL_SDIV_MASK ((1 << (2-0+1)) - 1) ++#define S3C6400_PLL_MDIV_SHIFT (16) ++#define S3C6400_PLL_PDIV_SHIFT (8) ++#define S3C6400_PLL_SDIV_SHIFT (0) ++ ++#include ++ ++static inline unsigned long s3c6400_get_pll(unsigned long baseclk, ++ u32 pllcon) ++{ ++ u32 mdiv, pdiv, sdiv; ++ u64 fvco = baseclk; ++ ++ mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK; ++ pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK; ++ sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK; ++ ++ fvco *= mdiv; ++ do_div(fvco, (pdiv << sdiv)); ++ ++ return (unsigned long)fvco; ++} ++ ++#define S3C6400_EPLL_MDIV_MASK ((1 << (23-16+1)) - 1) ++#define S3C6400_EPLL_PDIV_MASK ((1 << (13-8+1)) - 1) ++#define S3C6400_EPLL_SDIV_MASK ((1 << (2-0+1)) - 1) ++#define S3C6400_EPLL_MDIV_SHIFT (16) ++#define S3C6400_EPLL_PDIV_SHIFT (8) ++#define S3C6400_EPLL_SDIV_SHIFT (0) ++#define S3C6400_EPLL_KDIV_MASK (0xffff) ++ ++static inline unsigned long s3c6400_get_epll(unsigned long baseclk) ++{ ++ unsigned long result; ++ u32 epll0 = __raw_readl(S3C_EPLL_CON0); ++ u32 epll1 = __raw_readl(S3C_EPLL_CON1); ++ u32 mdiv, pdiv, sdiv, kdiv; ++ u64 tmp; ++ ++ mdiv = (epll0 >> S3C6400_EPLL_MDIV_SHIFT) & S3C6400_EPLL_MDIV_MASK; ++ pdiv = (epll0 >> S3C6400_EPLL_PDIV_SHIFT) & S3C6400_EPLL_PDIV_MASK; ++ sdiv = (epll0 >> S3C6400_EPLL_SDIV_SHIFT) & S3C6400_EPLL_SDIV_MASK; ++ kdiv = epll1 & S3C6400_EPLL_KDIV_MASK; ++ ++ /* We need to multiple baseclk by mdiv (the integer part) and kdiv ++ * which is in 2^16ths, so shift mdiv up (does not overflow) and ++ * add kdiv before multiplying. The use of tmp is to avoid any ++ * overflows before shifting bac down into result when multipling ++ * by the mdiv and kdiv pair. ++ */ ++ ++ tmp = baseclk; ++ tmp *= (mdiv << 16) + kdiv; ++ do_div(tmp, (pdiv << sdiv)); ++ result = tmp >> 16; ++ ++ return result; ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/pm.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/pm.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/pm.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/pm.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,82 @@ ++/* linux/include/asm-arm/plat-s3c24xx/pm.h ++ * ++ * Copyright (c) 2004 Simtec Electronics ++ * Written by Ben Dooks, ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++ ++/* s3c2410_pm_init ++ * ++ * called from board at initialisation time to setup the power ++ * management ++*/ ++ ++#ifdef CONFIG_PM ++ ++extern __init int s3c6410_pm_init(void); ++ ++#else ++ ++static inline int s3c6410_pm_init(void) ++{ ++ return 0; ++} ++#endif ++ ++/* configuration for the IRQ mask over sleep */ ++extern unsigned long s3c_irqwake_intmask; ++extern unsigned long s3c_irqwake_eintmask; ++ ++/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */ ++extern unsigned long s3c_irqwake_intallow; ++extern unsigned long s3c_irqwake_eintallow; ++ ++/* per-cpu sleep functions */ ++ ++extern void (*pm_cpu_prep)(void); ++extern void (*pm_cpu_sleep)(void); ++ ++/* Flags for PM Control */ ++ ++extern unsigned long s3c_pm_flags; ++ ++/* from sleep.S */ ++ ++extern int s3c6410_cpu_save(unsigned long *saveblk); ++extern void s3c6410_cpu_suspend(void); ++extern void s3c6410_cpu_resume(void); ++ ++extern unsigned long s3c6410_sleep_save_phys; ++ ++/* sleep save info */ ++ ++struct sleep_save { ++ void __iomem *reg; ++ unsigned long val; ++}; ++ ++struct sleep_save_phy { ++ unsigned long reg; ++ unsigned long val; ++}; ++ ++#define SAVE_ITEM(x) \ ++ { .reg = (x) } ++ ++extern void s3c6410_pm_do_save_phy(struct sleep_save_phy *ptr, int count); ++extern void s3c6410_pm_do_restore_phy(struct sleep_save_phy *ptr, int count); ++extern void s3c6410_pm_do_save(struct sleep_save *ptr, int count); ++extern void s3c6410_pm_do_restore(struct sleep_save *ptr, int count); ++ ++#ifdef CONFIG_PM ++extern int s3c64xx_irq_suspend(struct sys_device *dev, pm_message_t state); ++extern int s3c64xx_irq_resume(struct sys_device *dev); ++#else ++#define s3c64xx_irq_suspend NULL ++#define s3c64xx_irq_resume NULL ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/regs-clock.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/regs-clock.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/regs-clock.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/regs-clock.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,280 @@ ++/* arch/arm/plat-s3c64xx/include/plat/regs-clock.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C64XX clock register definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __PLAT_REGS_CLOCK_H ++#define __PLAT_REGS_CLOCK_H __FILE__ ++ ++#define S3C_CLKREG(x) (S3C_VA_SYS + (x)) ++ ++#define S3C_APLL_LOCK S3C_CLKREG(0x00) ++#define S3C_MPLL_LOCK S3C_CLKREG(0x04) ++#define S3C_EPLL_LOCK S3C_CLKREG(0x08) ++#define S3C_APLL_CON S3C_CLKREG(0x0C) ++#define S3C_MPLL_CON S3C_CLKREG(0x10) ++#define S3C_EPLL_CON0 S3C_CLKREG(0x14) ++#define S3C_EPLL_CON1 S3C_CLKREG(0x18) ++#define S3C_CLK_SRC S3C_CLKREG(0x1C) ++#define S3C_CLK_SRC2 S3C_CLKREG(0x10C) ++#define S3C_CLK_DIV0 S3C_CLKREG(0x20) ++#define S3C_CLK_DIV1 S3C_CLKREG(0x24) ++#define S3C_CLK_DIV2 S3C_CLKREG(0x28) ++#define S3C_CLK_OUT S3C_CLKREG(0x2C) ++#define S3C_HCLK_GATE S3C_CLKREG(0x30) ++#define S3C_PCLK_GATE S3C_CLKREG(0x34) ++#define S3C_SCLK_GATE S3C_CLKREG(0x38) ++#define S3C_SDMA_SEL S3C_CLKREG(0x110) ++#define S3C_SW_RST S3C_CLKREG(0x114) ++#define S3C_SYS_ID S3C_CLKREG(0x118) ++#define S3C_MEM_SYS_CFG S3C_CLKREG(0x120) ++#define S3C_QOS_OVERRIDE0 S3C_CLKREG(0x124) ++#define S3C_QOS_OVERRIDE1 S3C_CLKREG(0x128) ++#define S3C_MEM_CFG_STAT S3C_CLKREG(0x12C) ++#define S3C_PWR_CFG S3C_CLKREG(0x804) ++#define S3C_EINT_MASK S3C_CLKREG(0x808) ++#define S3C_NORMAL_CFG S3C_CLKREG(0x810) ++#define S3C_STOP_CFG S3C_CLKREG(0x814) ++#define S3C_SLEEP_CFG S3C_CLKREG(0x818) ++#define S3C_OSC_FREQ S3C_CLKREG(0x820) ++#define S3C_OSC_STABLE S3C_CLKREG(0x824) ++#define S3C_PWR_STABLE S3C_CLKREG(0x828) ++#define S3C_FPC_STABLE S3C_CLKREG(0x82C) ++#define S3C_MTC_STABLE S3C_CLKREG(0x830) ++#define S3C_OTHERS S3C_CLKREG(0x900) ++#define S3C_RST_STAT S3C_CLKREG(0x904) ++#define S3C_WAKEUP_STAT S3C_CLKREG(0x908) ++#define S3C_BLK_PWR_STAT S3C_CLKREG(0x90C) ++#define S3C_INFORM0 S3C_CLKREG(0xA00) ++#define S3C_INFORM1 S3C_CLKREG(0xA04) ++#define S3C_INFORM2 S3C_CLKREG(0xA08) ++#define S3C_INFORM3 S3C_CLKREG(0xA0C) ++#define S3C_INFORM4 S3C_CLKREG(0xA10) ++#define S3C_INFORM5 S3C_CLKREG(0xA14) ++#define S3C_INFORM6 S3C_CLKREG(0xA18) ++#define S3C_INFORM7 S3C_CLKREG(0xA1C) ++ ++#define S3C64XX_EPLL_CON0_M_SHIFT 16 ++#define S3C64XX_EPLL_CON0_P_SHIFT 8 ++#define S3C64XX_EPLL_CON0_S_SHIFT 0 ++#define S3C64XX_EPLL_CON1_K_SHIFT 0 ++ ++#define S3C64XX_EPLL_CON0_M_MASK (0xff<> 26) & 0x3) ++#define S3C_CICOSTATUS_GET_FRAME_END(x) (((x) >> 17) & 0x1) ++ ++#define S3C_CIPRTRGFMT_TARGETHSIZE(x) ((x) << 16) ++#define S3C_CIPRTRGFMT_TARGETVSIZE(x) ((x) << 0) ++ ++#define S3C_CIPRCTRL_YBURST1(x) ((x) << 19) ++#define S3C_CIPRCTRL_YBURST2(x) ((x) << 14) ++#define S3C_CIPRCTRL_CBURST1(x) ((x) << 9) ++#define S3C_CIPRCTRL_CBURST2(x) ((x) << 4) ++ ++#define S3C_CIPRSCPRERATIO_SHFACTOR(x) ((x) << 28) ++#define S3C_CIPRSCPRERATIO_PREHORRATIO(x) ((x) << 16) ++#define S3C_CIPRSCPRERATIO_PREVERRATIO(x) ((x) << 0) ++ ++#define S3C_CIPRSCPREDST_PREDSTWIDTH(x) ((x) << 16) ++#define S3C_CIPRSCPREDST_PREDSTHEIGHT(x) ((x) << 0) ++ ++#define S3C_CIPRSCCTRL_MAINHORRATIO(x) ((x) << 16) ++#define S3C_CIPRSCCTRL_MAINVERRATIO(x) ((x) << 0) ++ ++#define S3C_CIPRTAREA_TARGET_AREA(x) ((x) << 0) ++ ++#define S3C_CIPRSTATUS_GET_FRAME_COUNT(x) (((x) >> 26) & 0x3) ++#define S3C_CIPRSTATUS_GET_FRAME_END(x) (((x) >> 19) & 0x1) ++ ++#define S3C_CIIMGEFF_PAT_CB(x) ((x) << 13) ++#define S3C_CIIMGEFF_PAT_CR(x) ((x) << 0) ++ ++#define S3C_MSCO_HEIGHT(x) ((x) << 16) ++#define S3C_MSCO_WIDTH(x) ((x) << 0) ++ ++#define S3C_MSPR_HEIGHT(x) ((x) << 16) ++#define S3C_MSPR_WIDTH(x) ((x) << 0) ++ ++/************************************************************************* ++ * Bit definition part ++ ************************************************************************/ ++/* Source format register */ ++#define S3C_CISRCFMT_ITU601_8BIT (1 << 31) ++#define S3C_CISRCFMT_ITU656_8BIT (0 << 31) ++#define S3C_CISRCFMT_ORDER422_YCBYCR (0 << 14) ++#define S3C_CISRCFMT_ORDER422_YCRYCB (1 << 14) ++#define S3C_CISRCFMT_ORDER422_CBYCRY (2 << 14) ++#define S3C_CISRCFMT_ORDER422_CRYCBY (3 << 14) ++ ++/* Window offset register */ ++#define S3C_CIWDOFST_WINOFSEN (1 << 31) ++#define S3C_CIWDOFST_CLROVCOFIY (1 << 30) ++#define S3C_CIWDOFST_CLROVRLB_PR (1 << 28) ++#define S3C_CIWDOFST_CLROVPRFIY (1 << 27) ++#define S3C_CIWDOFST_CLROVCOFICB (1 << 15) ++#define S3C_CIWDOFST_CLROVCOFICR (1 << 14) ++#define S3C_CIWDOFST_CLROVPRFICB (1 << 13) ++#define S3C_CIWDOFST_CLROVPRFICR (1 << 12) ++#define S3C_CIWDOFST_WINHOROFST_MASK (0x7ff << 16) ++#define S3C_CIWDOFST_WINVEROFST_MASK (0x7ff << 0) ++ ++/* Global control register */ ++#define S3C_CIGCTRL_SWRST (1 << 31) ++#define S3C_CIGCTRL_CAMRST (1 << 30) ++#define S3C_CIGCTRL_TESTPATTERN_NORMAL (0 << 27) ++#define S3C_CIGCTRL_TESTPATTERN_COLOR_BAR (1 << 27) ++#define S3C_CIGCTRL_TESTPATTERN_HOR_INC (2 << 27) ++#define S3C_CIGCTRL_TESTPATTERN_VER_INC (3 << 27) ++#define S3C_CIGCTRL_TESTPATTERN_MASK (3 << 27) ++#define S3C_CIGCTRL_TESTPATTERN_SHIFT (27) ++#define S3C_CIGCTRL_INVPOLPCLK (1 << 26) ++#define S3C_CIGCTRL_INVPOLVSYNC (1 << 25) ++#define S3C_CIGCTRL_INVPOLHREF (1 << 24) ++#define S3C_CIGCTRL_IRQ_OVFEN (1 << 22) ++#define S3C_CIGCTRL_HREF_MASK (1 << 21) ++#define S3C_CIGCTRL_IRQ_EDGE (0 << 20) ++#define S3C_CIGCTRL_IRQ_LEVEL (1 << 20) ++#define S3C_CIGCTRL_IRQ_CLR_C (1 << 19) ++#define S3C_CIGCTRL_IRQ_CLR_P (1 << 18) ++#define S3C_CIGCTRL_PROGRESSIVE (0 << 0) ++#define S3C_CIGCTRL_INTERLACE (1 << 0) ++ ++/* Window offset2 register */ ++#define S3C_CIWDOFST_WINHOROFST2_MASK (0xfff << 16) ++#define S3C_CIWDOFST_WINVEROFST2_MASK (0xfff << 16) ++ ++/* Target format register */ ++#define S3C_CICOTRGFMT_OUTFORMAT_YCBCR420 (0 << 29) ++#define S3C_CICOTRGFMT_OUTFORMAT_YCBCR422 (1 << 29) ++#define S3C_CICOTRGFMT_OUTFORMAT_YCBCR422I (2 << 29) ++#define S3C_CICOTRGFMT_OUTFORMAT_RGB (3 << 29) ++#define S3C_CICOTRGFMT_FLIP_SHIFT (14) ++#define S3C_CICOTRGFMT_FLIP_NORMAL (0 << 14) ++#define S3C_CICOTRGFMT_FLIP_X_MIRROR (1 << 14) ++#define S3C_CICOTRGFMT_FLIP_Y_MIRROR (2 << 14) ++#define S3C_CICOTRGFMT_FLIP_180 (3 << 14) ++#define S3C_CICOTRGFMT_FLIP_MASK (3 << 14) ++ ++/* Output DMA control register */ ++#define S3C_CICOCTRL_BURST_MASK (0xfffff << 4) ++#define S3C_CICOCTRL_LASTIRQ_ENABLE (1 << 2) ++#define S3C_CICOCTRL_ORDER422_MASK (3 << 0) ++ ++/* Main scaler control register */ ++#define S3C_CICOSCCTRL_SCALERBYPASS (1 << 31) ++#define S3C_CICOSCCTRL_SCALEUP_H (1 << 30) ++#define S3C_CICOSCCTRL_SCALEUP_V (1 << 29) ++#define S3C_CICOSCCTRL_CSCR2Y_NARROW (0 << 28) ++#define S3C_CICOSCCTRL_CSCR2Y_WIDE (1 << 28) ++#define S3C_CICOSCCTRL_CSCY2R_NARROW (0 << 27) ++#define S3C_CICOSCCTRL_CSCY2R_WIDE (1 << 27) ++#define S3C_CICOSCCTRL_LCDPATHEN_FIFO (1 << 26) ++#define S3C_CICOSCCTRL_PROGRESSIVE (0 << 25) ++#define S3C_CICOSCCTRL_INTERLACE (1 << 25) ++#define S3C_CICOSCCTRL_SCALERSTART (1 << 15) ++#define S3C_CICOSCCTRL_INRGB_FMT_RGB565 (0 << 13) ++#define S3C_CICOSCCTRL_INRGB_FMT_RGB666 (1 << 13) ++#define S3C_CICOSCCTRL_INRGB_FMT_RGB888 (2 << 13) ++#define S3C_CICOSCCTRL_OUTRGB_FMT_RGB565 (0 << 11) ++#define S3C_CICOSCCTRL_OUTRGB_FMT_RGB666 (1 << 11) ++#define S3C_CICOSCCTRL_OUTRGB_FMT_RGB888 (2 << 11) ++#define S3C_CICOSCCTRL_EXTRGB_NORMAL (0 << 10) ++#define S3C_CICOSCCTRL_EXTRGB_EXTENSION (1 << 10) ++#define S3C_CICOSCCTRL_ONE2ONE (1 << 9) ++ ++/* Status register */ ++#define S3C_CICOSTATUS_OVFIY (1 << 31) ++#define S3C_CICOSTATUS_OVFICB (1 << 30) ++#define S3C_CICOSTATUS_OVFICR (1 << 29) ++#define S3C_CICOSTATUS_VSYNC (1 << 28) ++#define S3C_CICOSTATUS_WINOFSTEN (1 << 25) ++#define S3C_CICOSTATUS_IMGCPTEN (1 << 22) ++#define S3C_CICOSTATUS_IMGCPTENSC (1 << 21) ++#define S3C_CICOSTATUS_VSYNC_A (1 << 20) ++#define S3C_CICOSTATUS_FRAMEEND (1 << 17) ++ ++/* Target format register */ ++#define S3C_CIPRTRGFMT_OUTFORMAT_YCBCR420 (0 << 29) ++#define S3C_CIPRTRGFMT_OUTFORMAT_YCBCR422 (1 << 29) ++#define S3C_CIPRTRGFMT_OUTFORMAT_YCBCR422I (2 << 29) ++#define S3C_CIPRTRGFMT_OUTFORMAT_RGB (3 << 29) ++#define S3C_CIPRTRGFMT_FLIP_SHIFT (14) ++#define S3C_CIPRTRGFMT_FLIP_NORMAL (0 << 14) ++#define S3C_CIPRTRGFMT_FLIP_X_MIRROR (1 << 14) ++#define S3C_CIPRTRGFMT_FLIP_Y_MIRROR (2 << 14) ++#define S3C_CIPRTRGFMT_FLIP_180 (3 << 14) ++#define S3C_CIPRTRGFMT_FLIP_MASK (3 << 14) ++#define S3C_CIPRTRGFMT_ROT90_CLOCKWISE (1 << 13) ++ ++/* Output DMA control register */ ++#define S3C_CIPRCTRL_BURST_MASK (0xfffff << 4) ++#define S3C_CIPRCTRL_LASTIRQ_ENABLE (1 << 2) ++#define S3C_CIPRCTRL_ORDER422_MASK (3 << 0) ++ ++/* Main scaler control register */ ++#define S3C_CIPRSCCTRL_SCALERBYPASS (1 << 31) ++#define S3C_CIPRSCCTRL_SCALEUP_H (1 << 30) ++#define S3C_CIPRSCCTRL_SCALEUP_V (1 << 29) ++#define S3C_CIPRSCCTRL_CSCR2Y_NARROW (0 << 28) ++#define S3C_CIPRSCCTRL_CSCR2Y_WIDE (1 << 28) ++#define S3C_CIPRSCCTRL_CSCY2R_NARROW (0 << 27) ++#define S3C_CIPRSCCTRL_CSCY2R_WIDE (1 << 27) ++#define S3C_CIPRSCCTRL_LCDPATHEN_FIFO (1 << 26) ++#define S3C_CIPRSCCTRL_PROGRESSIVE (0 << 25) ++#define S3C_CIPRSCCTRL_INTERLACE (1 << 25) ++#define S3C_CIPRSCCTRL_SCALERSTART (1 << 15) ++#define S3C_CIPRSCCTRL_INRGB_FMT_RGB565 (0 << 13) ++#define S3C_CIPRSCCTRL_INRGB_FMT_RGB666 (1 << 13) ++#define S3C_CIPRSCCTRL_INRGB_FMT_RGB888 (2 << 13) ++#define S3C_CIPRSCCTRL_OUTRGB_FMT_RGB565 (0 << 11) ++#define S3C_CIPRSCCTRL_OUTRGB_FMT_RGB666 (1 << 11) ++#define S3C_CIPRSCCTRL_OUTRGB_FMT_RGB888 (2 << 11) ++#define S3C_CIPRSCCTRL_EXTRGB_NORMAL (0 << 10) ++#define S3C_CIPRSCCTRL_EXTRGB_EXTENSION (1 << 10) ++#define S3C_CIPRSCCTRL_ONE2ONE (1 << 9) ++ ++/* Status register */ ++#define S3C_CIPRSTATUS_OVFIY (1 << 31) ++#define S3C_CIPRSTATUS_OVFICB (1 << 30) ++#define S3C_CIPRSTATUS_OVFICR (1 << 29) ++#define S3C_CIPRSTATUS_VSYNC (1 << 28) ++#define S3C_CIPRSTATUS_WINOFSTEN (1 << 25) ++#define S3C_CIPRSTATUS_IMGCPTEN (1 << 22) ++#define S3C_CIPRSTATUS_IMGCPTENSC (1 << 21) ++#define S3C_CIPRSTATUS_VSYNC_A (1 << 20) ++#define S3C_CIPRSTATUS_FRAMEEND (1 << 19) ++ ++/* Image capture enable register */ ++#define S3C_CIIMGCPT_IMGCPTEN (1 << 31) ++#define S3C_CIIMGCPT_IMGCPTEN_COSC (1 << 30) ++#define S3C_CIIMGCPT_IMGCPTEN_PRSC (1 << 29) ++#define S3C_CIIMGCPT_CPT_FREN_ENABLE_CO (1 << 25) ++#define S3C_CIIMGCPT_CPT_FREN_ENABLE_PR (1 << 24) ++#define S3C_CIIMGCPT_CPT_FRMOD_EN (0 << 18) ++#define S3C_CIIMGCPT_CPT_FRMOD_CNT (1 << 18) ++ ++/* Image effects register */ ++#define S3C_CIIMGEFF_IE_DISABLE_PR (0 << 31) ++#define S3C_CIIMGEFF_IE_ENABLE_PR (1 << 31) ++#define S3C_CIIMGEFF_IE_DISABLE_CO (0 << 30) ++#define S3C_CIIMGEFF_IE_ENABLE_CO (1 << 30) ++#define S3C_CIIMGEFF_IE_SC_BEFORE (0 << 29) ++#define S3C_CIIMGEFF_IE_SC_AFTER (1 << 29) ++#define S3C_CIIMGEFF_FIN_BYPASS (0 << 26) ++#define S3C_CIIMGEFF_FIN_ARBITRARY (1 << 26) ++#define S3C_CIIMGEFF_FIN_NEGATIVE (2 << 26) ++#define S3C_CIIMGEFF_FIN_ARTFREEZE (3 << 26) ++#define S3C_CIIMGEFF_FIN_EMBOSSING (4 << 26) ++#define S3C_CIIMGEFF_FIN_SILHOUETTE (5 << 26) ++#define S3C_CIIMGEFF_FIN_MASK (7 << 26) ++#define S3C_CIIMGEFF_PAT_CBCR_MASK ((0xff < 13) | (0xff < 0)) ++ ++/* Real input DMA size register */ ++#define S3C_MSCOWIDTH_AUTOLOAD_ENABLE (1 << 31) ++ ++/* Input DMA control register */ ++#define S3C_MSCOCTRL_ORDER422_YCBYCR (0 << 4) ++#define S3C_MSCOCTRL_ORDER422_YCRYCB (1 << 4) ++#define S3C_MSCOCTRL_ORDER422_CBYCRY (2 << 4) ++#define S3C_MSCOCTRL_ORDER422_CRYCBY (3 << 4) ++#define S3C_MSCOCTRL_INPUT_EXTCAM (0 << 3) ++#define S3C_MSCOCTRL_INPUT_MEMORY (1 << 3) ++#define S3C_MSCOCTRL_INPUT_MASK (1 << 3) ++#define S3C_MSCOCTRL_INFORMAT_YCBCR420 (0 << 1) ++#define S3C_MSCOCTRL_INFORMAT_YCBCR422 (1 << 1) ++#define S3C_MSCOCTRL_INFORMAT_YCBCR422I (2 << 1) ++#define S3C_MSCOCTRL_INFORMAT_RGB (3 << 1) ++#define S3C_MSCOCTRL_ENVID (1 << 0) ++ ++/* Real input DMA size register */ ++#define S3C_MSPRWIDTH_AUTOLOAD_ENABLE (1 << 31) ++ ++/* Input DMA control register */ ++#define S3C_MSPRCTRL_ORDER422_YCBYCR (0 << 4) ++#define S3C_MSPRCTRL_ORDER422_YCRYCB (1 << 4) ++#define S3C_MSPRCTRL_ORDER422_CBYCRY (2 << 4) ++#define S3C_MSPRCTRL_ORDER422_CRYCBY (3 << 4) ++#define S3C_MSPRCTRL_INPUT_EXTCAM (0 << 3) ++#define S3C_MSPRCTRL_INPUT_MEMORY (1 << 3) ++#define S3C_MSPRCTRL_INPUT_MASK (1 << 3) ++#define S3C_MSPRCTRL_INFORMAT_YCBCR420 (0 << 1) ++#define S3C_MSPRCTRL_INFORMAT_YCBCR422 (1 << 1) ++#define S3C_MSPRCTRL_INFORMAT_YCBCR422I (2 << 1) ++#define S3C_MSPRCTRL_INFORMAT_RGB (3 << 1) ++#define S3C_MSPRCTRL_ENVID (1 << 0) ++ ++#endif /* _REGS_FIMC_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,102 @@ ++/* linux/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C64XX - GPIO register definitions ++ */ ++ ++#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H ++#define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Base addresses for each of the banks */ ++ ++#define S3C64XX_GPA_BASE (S3C64XX_VA_GPIO + 0x0000) ++#define S3C64XX_GPB_BASE (S3C64XX_VA_GPIO + 0x0020) ++#define S3C64XX_GPC_BASE (S3C64XX_VA_GPIO + 0x0040) ++#define S3C64XX_GPD_BASE (S3C64XX_VA_GPIO + 0x0060) ++#define S3C64XX_GPE_BASE (S3C64XX_VA_GPIO + 0x0080) ++#define S3C64XX_GPF_BASE (S3C64XX_VA_GPIO + 0x00A0) ++#define S3C64XX_GPG_BASE (S3C64XX_VA_GPIO + 0x00C0) ++#define S3C64XX_GPH_BASE (S3C64XX_VA_GPIO + 0x00E0) ++#define S3C64XX_GPI_BASE (S3C64XX_VA_GPIO + 0x0100) ++#define S3C64XX_GPJ_BASE (S3C64XX_VA_GPIO + 0x0120) ++#define S3C64XX_GPK_BASE (S3C64XX_VA_GPIO + 0x0800) ++#define S3C64XX_GPL_BASE (S3C64XX_VA_GPIO + 0x0810) ++#define S3C64XX_GPM_BASE (S3C64XX_VA_GPIO + 0x0820) ++#define S3C64XX_GPN_BASE (S3C64XX_VA_GPIO + 0x0830) ++#define S3C64XX_GPO_BASE (S3C64XX_VA_GPIO + 0x0140) ++#define S3C64XX_GPP_BASE (S3C64XX_VA_GPIO + 0x0160) ++#define S3C64XX_GPQ_BASE (S3C64XX_VA_GPIO + 0x0180) ++#define S3C64XX_SPC_BASE (S3C64XX_VA_GPIO + 0x01A0) ++#define S3C64XX_MEM0CONSTOP (S3C64XX_VA_GPIO + 0x01B0) ++#define S3C64XX_MEM1CONSTOP (S3C64XX_VA_GPIO + 0x01B4) ++#define S3C64XX_MEM0CONSLP0 (S3C64XX_VA_GPIO + 0x01C0) ++#define S3C64XX_MEM0CONSLP1 (S3C64XX_VA_GPIO + 0x01C4) ++#define S3C64XX_MEM1CONSLP (S3C64XX_VA_GPIO + 0x01C8) ++#define S3C64XX_MEM0DRVCON (S3C64XX_VA_GPIO + 0x01D0) ++#define S3C64XX_MEM1DRVCON (S3C64XX_VA_GPIO + 0x01D4) ++#define S3C64XX_EINT0CON0 (S3C64XX_VA_GPIO + 0x0900) ++#define S3C64XX_EINT0CON1 (S3C64XX_VA_GPIO + 0x0904) ++#define S3C64XX_EINT0FLTCON0 (S3C64XX_VA_GPIO + 0x0910) ++#define S3C64XX_EINT0FLTCON1 (S3C64XX_VA_GPIO + 0x0914) ++#define S3C64XX_EINT0FLTCON2 (S3C64XX_VA_GPIO + 0x0918) ++#define S3C64XX_EINT0FLTCON3 (S3C64XX_VA_GPIO + 0x091C) ++#define S3C64XX_EINT0MASK (S3C64XX_VA_GPIO + 0x0920) ++#define S3C64XX_EINT0PEND (S3C64XX_VA_GPIO + 0x0924) ++#define S3C64XX_SPCONSLP (S3C64XX_VA_GPIO + 0x0880) ++#define S3C64XX_SLPEN (S3C64XX_VA_GPIO + 0x0930) ++#define S3C64XX_EINT12CON (S3C64XX_VA_GPIO + 0x0200) ++#define S3C64XX_EINT34CON (S3C64XX_VA_GPIO + 0x0204) ++#define S3C64XX_EINT56CON (S3C64XX_VA_GPIO + 0x0208) ++#define S3C64XX_EINT78CON (S3C64XX_VA_GPIO + 0x020C) ++#define S3C64XX_EINT9CON (S3C64XX_VA_GPIO + 0x0210) ++#define S3C64XX_EINT12FLTCON (S3C64XX_VA_GPIO + 0x0220) ++#define S3C64XX_EINT34FLTCON (S3C64XX_VA_GPIO + 0x0224) ++#define S3C64XX_EINT56FLTCON (S3C64XX_VA_GPIO + 0x0228) ++#define S3C64XX_EINT78FLTCON (S3C64XX_VA_GPIO + 0x022C) ++#define S3C64XX_EINT9FLTCON (S3C64XX_VA_GPIO + 0x0230) ++#define S3C64XX_EINT12MASK (S3C64XX_VA_GPIO + 0x0240) ++#define S3C64XX_EINT34MASK (S3C64XX_VA_GPIO + 0x0244) ++#define S3C64XX_EINT56MASK (S3C64XX_VA_GPIO + 0x0248) ++#define S3C64XX_EINT78MASK (S3C64XX_VA_GPIO + 0x024C) ++#define S3C64XX_EINT9MASK (S3C64XX_VA_GPIO + 0x0250) ++#define S3C64XX_EINT12PEND (S3C64XX_VA_GPIO + 0x0260) ++#define S3C64XX_EINT34PEND (S3C64XX_VA_GPIO + 0x0264) ++#define S3C64XX_EINT56PEND (S3C64XX_VA_GPIO + 0x0268) ++#define S3C64XX_EINT78PEND (S3C64XX_VA_GPIO + 0x026C) ++#define S3C64XX_EINT9PEND (S3C64XX_VA_GPIO + 0x0270) ++#define S3C64XX_PRIORITY (S3C64XX_VA_GPIO + 0x0280) ++#define S3C64XX_SERVICE (S3C64XX_VA_GPIO + 0x0284) ++#define S3C64XX_SERVICEPEND (S3C64XX_VA_GPIO + 0x0288) ++ ++/* values for S3C_EXTINT0 */ ++#define S3C64XX_EXTINT_LOWLEV (0x00) ++#define S3C64XX_EXTINT_HILEV (0x01) ++#define S3C64XX_EXTINT_FALLEDGE (0x02) ++#define S3C64XX_EXTINT_RISEEDGE (0x04) ++#define S3C64XX_EXTINT_BOTHEDGE (0x06) ++ ++#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/regs-iis.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/regs-iis.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/regs-iis.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/regs-iis.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,115 @@ ++/* linux/arch/arm/plat-s3c/include/plat/regs-iis.h ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C64XX IIS register definition ++*/ ++ ++#ifndef __ASM_ARCH_REGS_S3C64XX_IIS_H ++#define __ASM_ARCH_REGS_S3C64XX_IIS_H ++ ++#define S3C64XX_IISCON (0x00) ++#define S3C64XX_IISMOD (0x04) ++#define S3C64XX_IISFIC (0x08) ++#define S3C64XX_IISPSR (0x0C) ++#define S3C64XX_IISTXD (0x10) ++#define S3C64XX_IISRXD (0x14) ++ ++#define S3C64XX_IISCON_I2SACTIVE (0x1<<0) ++#define S3C64XX_IISCON_RXDMACTIVE (0x1<<1) ++#define S3C64XX_IISCON_TXDMACTIVE (0x1<<2) ++#define S3C64XX_IISCON_RXCHPAUSE (0x1<<3) ++#define S3C64XX_IISCON_TXCHPAUSE (0x1<<4) ++#define S3C64XX_IISCON_RXDMAPAUSE (0x1<<5) ++#define S3C64XX_IISCON_TXDMAPAUSE (0x1<<6) ++#define S3C64XX_IISCON_FRXFULL (0x1<<7) ++#ifdef IIS_V40 ++#define S3C64XX_IISCON_FTX0FULL (0x1<<8) ++#else ++#define S3C64XX_IISCON_FTXFULL (0x1<<8) ++#endif ++#define S3C64XX_IISCON_FRXEMPT (0x1<<9) ++#define S3C64XX_IISCON_FTX0EMPT (0x1<<10) ++#define S3C64XX_IISCON_LRI (0x1<<11) ++#ifdef IIS_V40 ++#define S3C64XX_IISCON_FTX1FULL (0x1<<12) ++#define S3C64XX_IISCON_FTX2FULL (0x1<<13) ++#define S3C64XX_IISCON_FTX1EMPT (0x1<<14) ++#define S3C64XX_IISCON_FTX2EMPT (0x1<<15) ++#endif ++#define S3C64XX_IISCON_FTXURINTEN (0x1<<16) ++#define S3C64XX_IISCON_FTXURSTATUS (0x1<<17) ++#ifndef IIS_V40 ++#define S3C6410_IISCON_FRXORINTEN (0x1<<18) ++#define S3C6410_IISCON_FRXORSTATUS (0x1<<19) ++#endif ++ ++#define S3C64XX_IISMOD_BFSMASK (3<<1) ++#define S3C64XX_IISMOD_32FS (0<<1) ++#define S3C64XX_IISMOD_48FS (1<<1) ++#define S3C64XX_IISMOD_16FS (2<<1) ++#define S3C64XX_IISMOD_24FS (3<<1) ++ ++#define S3C64XX_IISMOD_RFSMASK (3<<3) ++#define S3C64XX_IISMOD_256FS (0<<3) ++#define S3C64XX_IISMOD_512FS (1<<3) ++#define S3C64XX_IISMOD_384FS (2<<3) ++#define S3C64XX_IISMOD_768FS (3<<3) ++ ++#define S3C64XX_IISMOD_SDFMASK (3<<5) ++#define S3C64XX_IISMOD_IIS (0<<5) ++#define S3C64XX_IISMOD_MSB (1<<5) ++#define S3C64XX_IISMOD_LSB (2<<5) ++ ++#define S3C64XX_IISMOD_LRP (1<<7) ++ ++#define S3C64XX_IISMOD_TXRMASK (3<<8) ++#define S3C64XX_IISMOD_TX (0<<8) ++#define S3C64XX_IISMOD_RX (1<<8) ++#define S3C64XX_IISMOD_TXRX (2<<8) ++ ++#define S3C64XX_IISMOD_IMSMASK (3<<10) ++#define S3C64XX_IISMOD_MSTPCLK (0<<10) ++#define S3C64XX_IISMOD_MSTCLKAUDIO (1<<10) ++#define S3C64XX_IISMOD_SLVPCLK (2<<10) ++#define S3C64XX_IISMOD_SLVI2SCLK (3<<10) ++ ++#define S3C64XX_IISMOD_CDCLKCON (1<<12) ++ ++#define S3C64XX_IISMOD_BLCMASK (3<<13) ++#define S3C64XX_IISMOD_16BIT (0<<13) ++#define S3C64XX_IISMOD_8BIT (1<<13) ++#define S3C64XX_IISMOD_24BIT (2<<13) ++ ++#ifdef IIS_V40 ++ ++#define S3C64XX_IISMOD_SD1EN (1<<16) ++#define S3C64XX_IISMOD_SD2EN (1<<17) ++ ++#define S3C64XX_IISMOD_CCD1MASK (3<<18) ++#define S3C64XX_IISMOD_CCD1ND (0<<18) ++#define S3C64XX_IISMOD_CCD11STD (1<<18) ++#define S3C64XX_IISMOD_CCD12NDD (2<<18) ++ ++#define S3C64XX_IISMOD_CCD2MASK (3<<20) ++#define S3C64XX_IISMOD_CCD2ND (0<<20) ++#define S3C64XX_IISMOD_CCD21STD (1<<20) ++#define S3C64XX_IISMOD_CCD22NDD (2<<20) ++ ++#endif ++ ++#define S3C64XX_IISFIC_FRXCNTMSK (0xf<<0) ++#define S3C64XX_IISFIC_RFLUSH (1<<7) ++#define S3C64XX_IISFIC_FTX0CNTMSK (0xf<<8) ++#define S3C64XX_IISFIC_TFLUSH (1<<15) ++#ifdef IIS_V40 ++#define S3C64XX_IISFIC_FTX1CNTMSK (0xf<<16) ++#define S3C64XX_IISFIC_FTX2CNTMSK (0xf<<24) ++#endif ++ ++#define S3C64XX_IISPSR_PSVALA (0x3f<<8) ++#define S3C64XX_IISPSR_PSRAEN (1<<15) ++ ++#endif /* __ASM_ARCH_REGS_S3C64XX_IIS_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/regs-mfc.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/regs-mfc.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/regs-mfc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/regs-mfc.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,325 @@ ++/* linux/include/asm-arm/arch-s3c2410/regs-mfc.h ++ * ++ * Copyright (c) 2009 Samsung Electronics ++ * http://www.samsung.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C MFC Controller ++*/ ++ ++#ifndef __ASM_ARCH_REGS_MFC_H ++#define __ASM_ARCH_REGS_MFC_H __FILE__ ++ ++/* ++ * MFC Interface ++ */ ++#define S3C_MFC(x) (x) ++ ++#define S3C_MFC_CODE_RUN S3C_MFC(0x000) /* [0] 1=Start the bit processor, 0=Stop. */ ++#define S3C_MFC_CODE_DN_LOAD S3C_MFC(0x004) /* [15:0] [28:16] */ ++#define S3C_MFC_HOST_INTR S3C_MFC(0x008) /* [0] Write '1' to this bit to request an interrupt to BIT */ ++#define S3C_MFC_BITS_INT_CLEAR S3C_MFC(0x00c) ++#define S3C_MFC_BITS_INT_STAT S3C_MFC(0x010) /* [0] 1 means that BIT interrupt to the host is asserted. */ ++#define S3C_MFC_BITS_CODE_RESET S3C_MFC(0x014) ++#define S3C_MFC_BITS_CUR_PC S3C_MFC(0x018) ++#define S3C_MFC_RESERVED1 S3C_MFC(0x01c) /* 0x01c ~ 0x0fc */ ++#define S3C_MFC_CODE_BUF_ADDR S3C_MFC(0x100) ++#define S3C_MFC_WORK_BUF_ADDR S3C_MFC(0x104) ++#define S3C_MFC_PARA_BUF_ADDR S3C_MFC(0x108) ++#define S3C_MFC_STRM_BUF_CTRL S3C_MFC(0x10c) ++#define S3C_MFC_FRME_BUF_CTRL S3C_MFC(0x110) ++#define S3C_MFC_DEC_FUNC_CTRL S3C_MFC(0x114) /* 7th fw */ ++#define S3C_MFC_RESERVED2 S3C_MFC(0x118) /* 0x118 */ ++#define S3C_MFC_WORK_BUF_CTRL S3C_MFC(0x11c) /* 7th fw */ ++ ++#define S3C_MFC_BIT_STR_BASE_PTR0 S3C_MFC(0x120) ++#define S3C_MFC_BIT_STR_RD_PTR0 S3C_MFC(0x120) ++#define S3C_MFC_BIT_STR_WR_PTR0 S3C_MFC(0x124) ++ ++#define S3C_MFC_BIT_STR_BASE_PTR1 S3C_MFC(0x128) ++#define S3C_MFC_BIT_STR_RD_PTR1 S3C_MFC(0x128) ++#define S3C_MFC_BIT_STR_WR_PTR1 S3C_MFC(0x12c) ++ ++#define S3C_MFC_BIT_STR_BASE_PTR2 S3C_MFC(0x130) ++#define S3C_MFC_BIT_STR_RD_PTR2 S3C_MFC(0x130) ++#define S3C_MFC_BIT_STR_WR_PTR2 S3C_MFC(0x134) ++ ++#define S3C_MFC_BIT_STR_BASE_PTR3 S3C_MFC(0x138) ++#define S3C_MFC_BIT_STR_RD_PTR3 S3C_MFC(0x138) ++#define S3C_MFC_BIT_STR_WR_PTR3 S3C_MFC(0x13c) ++ ++#define S3C_MFC_BIT_STR_BASE_PTR4 S3C_MFC(0x140) ++#define S3C_MFC_BIT_STR_RD_PTR4 S3C_MFC(0x140) ++#define S3C_MFC_BIT_STR_WR_PTR4 S3C_MFC(0x144) ++ ++#define S3C_MFC_BIT_STR_BASE_PTR5 S3C_MFC(0x148) ++#define S3C_MFC_BIT_STR_RD_PTR5 S3C_MFC(0x148) ++#define S3C_MFC_BIT_STR_WR_PTR5 S3C_MFC(0x14c) ++ ++#define S3C_MFC_BIT_STR_BASE_PTR6 S3C_MFC(0x150) ++#define S3C_MFC_BIT_STR_RD_PTR6 S3C_MFC(0x150) ++#define S3C_MFC_BIT_STR_WR_PTR6 S3C_MFC(0x154) ++ ++#define S3C_MFC_BIT_STR_BASE_PTR7 S3C_MFC(0x158) ++#define S3C_MFC_BIT_STR_RD_PTR7 S3C_MFC(0x158) ++#define S3C_MFC_BIT_STR_WR_PTR7 S3C_MFC(0x15c) ++ ++#define S3C_MFC_BUSY_FLAG S3C_MFC(0x160) ++#define S3C_MFC_RUN_CMD S3C_MFC(0x164) ++#define S3C_MFC_RUN_INDEX S3C_MFC(0x168) ++#define S3C_MFC_RUN_COD_STD S3C_MFC(0x16c) ++#define S3C_MFC_INT_ENABLE S3C_MFC(0x170) ++#define S3C_MFC_INT_REASON S3C_MFC(0x174) ++ ++#define S3C_MFC_RESERVED3 S3C_MFC(0x178) /* 0x178 ,0x17c */ ++ ++#define S3C_MFC_PARAM S3C_MFC(0x180) ++ ++/* Parameter regester decode sequence init */ ++#define S3C_MFC_PARAM_DEC_SEQ_INIT S3C_MFC_PARAM ++#define S3C_MFC_PARAM_DEC_SEQ_BIT_BUF_ADDR S3C_MFC(0x180) ++#define S3C_MFC_PARAM_DEC_SEQ_BIT_BUF_SIZE S3C_MFC(0x184) ++#define S3C_MFC_PARAM_DEC_SEQ_OPTION S3C_MFC(0x188) ++#define S3C_MFC_PARAM_DEC_SEQ_PRO_BUF S3C_MFC(0x18c) ++#define S3C_MFC_PARAM_DEC_SEQ_TMP_BUF_1 S3C_MFC(0x190) ++#define S3C_MFC_PARAM_DEC_SEQ_TMP_BUF_2 S3C_MFC(0x194) ++#define S3C_MFC_PARAM_DEC_SEQ_TMP_BUF_3 S3C_MFC(0x198) ++#define S3C_MFC_PARAM_DEC_SEQ_TMP_BUF_4 S3C_MFC(0x19c) ++#define S3C_MFC_PARAM_DEC_SEQ_TMP_BUF_5 S3C_MFC(0x1a0) ++#define S3C_MFC_PARAM_DEC_SEQ_START_BYTE S3C_MFC(0x1a4) ++#define S3C_MFC_PARAM_DEC_SEQ_RESERVED S3C_MFC(0x1a8) ++/* output return */ ++#define S3C_MFC_PARAM_RET_DEC_SEQ_SUCCESS S3C_MFC(0x1c0) ++#define S3C_MFC_PARAM_RET_DEC_SEQ_SRC_SIZE S3C_MFC(0x1c4) ++#define S3C_MFC_PARAM_RET_DEC_SEQ_SRC_FRAME_RATE S3C_MFC(0x1c8) ++#define S3C_MFC_PARAM_RET_DEC_SEQ_FRAME_NEED_COUNT S3C_MFC(0x1cc) ++#define S3C_MFC_PARAM_RET_DEC_SEQ_FRAME_DELAY S3C_MFC(0x1d0) ++#define S3C_MFC_PARAM_RET_DEC_SEQ_INFO S3C_MFC(0x1d4) ++#define S3C_MFC_PARAM_RET_DEC_SEQ_TIME_RES S3C_MFC(0x1d8) ++ ++/* Paramete register encode sequence init */ ++#define S3C_MFC_PARAM_ENC_SEQ_INIT S3C_MFC_PARAM ++#define S3C_MFC_PARAM_ENC_SEQ_BIT_BUF_ADDR S3C_MFC(0x180) ++#define S3C_MFC_PARAM_ENC_SEQ_BIT_BUF_SIZE S3C_MFC(0x184) ++#define S3C_MFC_PARAM_ENC_SEQ_OPTION S3C_MFC(0x188) ++#define S3C_MFC_PARAM_ENC_SEQ_COD_STD S3C_MFC(0x18c) ++#define S3C_MFC_PARAM_ENC_SEQ_SRC_SIZE S3C_MFC(0x190) ++#define S3C_MFC_PARAM_ENC_SEQ_SRC_F_RATE S3C_MFC(0x194) ++#define S3C_MFC_PARAM_ENC_SEQ_MP4_PARA S3C_MFC(0x198) ++#define S3C_MFC_PARAM_ENC_SEQ_263_PARA S3C_MFC(0x19c) ++#define S3C_MFC_PARAM_ENC_SEQ_264_PARA S3C_MFC(0x1a0) ++#define S3C_MFC_PARAM_ENC_SEQ_SLICE_MODE S3C_MFC(0x1a4) ++#define S3C_MFC_PARAM_ENC_SEQ_GOP_NUM S3C_MFC(0x1a8) ++#define S3C_MFC_PARAM_ENC_SEQ_RC_PARA S3C_MFC(0x1ac) ++#define S3C_MFC_PARAM_ENC_SEQ_RC_BUF_SIZE S3C_MFC(0x1b0) ++#define S3C_MFC_PARAM_ENC_SEQ_INTRA_MB S3C_MFC(0x1b4) ++#define S3C_MFC_PARAM_ENC_SEQ_FMO S3C_MFC(0x1b8) ++#define S3C_MFC_PARAM_ENC_SEQ_INTRA_QP S3C_MFC(0x1bc) ++/* output return */ ++#define S3C_MFC_PARAM_RET_ENC_SEQ_SUCCESS S3C_MFC(0x1c0) ++ ++#define S3C_MFC_PARAM_ENC_SEQ_RC_OPTION S3C_MFC(0x1c4) ++#define S3C_MFC_PARAM_ENC_SEQ_RC_QP_MAX S3C_MFC(0x1c8) ++#define S3C_MFC_PARAM_ENC_SEQ_RC_GAMMA S3C_MFC(0x1cc) /* 0x1cc float? */ ++#define S3C_MFC_PARAM_ENC_SEQ_TMP_BUF1 S3C_MFC(0x1d0) ++#define S3C_MFC_PARAM_ENC_SEQ_TMP_BUF2 S3C_MFC(0x1d4) ++#define S3C_MFC_PARAM_ENC_SEQ_TMP_BUF3 S3C_MFC(0x1d8) ++#define S3C_MFC_PARAM_ENC_SEQ_TMP_BUF4 S3C_MFC(0x1dc) ++ ++/* Parameter register set frame buf */ ++#define S3C_MFC_PARAM_REG_SET_FRAME_BUF S3C_MFC_PARAM ++#define S3C_MFC_PARAM_SET_FRAME_BUF_NUM S3C_MFC(0x180) ++#define S3C_MFC_PARAM_SET_FRAME_BUF_STRIDE S3C_MFC(0x184) ++ ++ ++/* Parameter register decode pic run */ ++#define S3C_MFC_PARAM_DEC_PIC_RUN S3C_MFC_PARAM ++#define S3C_MFC_PARAM_DEC_PIC_ROT_MODE S3C_MFC(0x180) /* Display frame post-rotator mode */ ++#define S3C_MFC_PARAM_DEC_PIC_ROT_ADDR_Y S3C_MFC(0x184) /* Post-rotated frame store Y address */ ++#define S3C_MFC_PARAM_DEC_PIC_ROT_ADDR_CB S3C_MFC(0x188) /* Post-rotated frame store Cb address */ ++#define S3C_MFC_PARAM_DEC_PIC_ROT_ADDR_CR S3C_MFC(0x18c) /* Post-rotated frame store Cr address */ ++#define S3C_MFC_PARAM_DEC_PIC_DBK_ADDR_Y S3C_MFC(0x190) /* Deblocked frame store Y address */ ++#define S3C_MFC_PARAM_DEC_PIC_DBK_ADDR_CB S3C_MFC(0x194) /* Deblocked frame store Cb address */ ++#define S3C_MFC_PARAM_DEC_PIC_DBK_ADDR_CR S3C_MFC(0x198) /* Deblocked frame store Cr address */ ++#define S3C_MFC_PARAM_DEC_PIC_ROT_STRIDE S3C_MFC(0x19c) /* Post-rotated frame stride */ ++#define S3C_MFC_PARAM_DEC_PIC_OPTION S3C_MFC(0x1a0) /* Decoding option */ ++#define S3C_MFC_PARAM_DEC_PIC_RESERVED1 S3C_MFC(0x1a4) ++#define S3C_MFC_PARAM_DEC_PIC_CHUNK_SIZE S3C_MFC(0x1a8) /* Frame chunk size */ ++#define S3C_MFC_PARAM_DEC_PIC_BB_START S3C_MFC(0x1ac) /* 4-byte aligned start address of picture stream buffer */ ++#define S3C_MFC_PARAM_DEC_PIC_START_BYTE S3C_MFC(0x1b0) /* Start byte of valid stream data */ ++#define S3C_MFC_PARAM_DEC_PIC_MV_ADDR S3C_MFC(0x1b4) /* Base address for Motion Vector data */ ++#define S3C_MFC_PARAM_DEC_PIC_MBTYPE_ADDR S3C_MFC(0x1b8) /* Base address for MBType data */ ++#define S3C_MFC_PARAM_DEC_PIC_RESERVED2 S3C_MFC(0x1bc) ++/* output return */ ++#define S3C_MFC_PARAM_RET_DEC_PIC_FRAME_NUM S3C_MFC(0x1c0) /* Decoded frame number */ ++#define S3C_MFC_PARAM_RET_DEC_PIC_IDX S3C_MFC(0x1c4) /* Display frame index */ ++#define S3C_MFC_PARAM_RET_DEC_PIC_ERR_MB_NUM S3C_MFC(0x1c8) /* Error MB number in decodec picture */ ++#define S3C_MFC_PARAM_RET_DEC_PIC_TYPE S3C_MFC(0x1cc) /* Decoded picture type */ ++#define S3C_MFC_PARAM_DEC_PIC_RESERVED3 S3C_MFC(0x1d0) /* 0x1d0 ~ 0x1d4 */ ++#define S3C_MFC_PARAM_RET_DEC_PIC_SUCCESS S3C_MFC(0x1d8) /* Command executing result status */ ++#define S3C_MFC_PARAM_RET_DEC_PIC_CUR_IDX S3C_MFC(0x1dc) /* Decoded frame index */ ++#define S3C_MFC_PARAM_RET_DEC_PIC_FCODE_FWD S3C_MFC(0x1e0) /* FCODE value */ ++#define S3C_MFC_PARAM_RET_DEC_PIC_TRD S3C_MFC(0x1e4) /* TRD value */ ++#define S3C_MFC_PARAM_RET_DEC_PIC_TIME_BASE_LAST S3C_MFC(0x1e8) /* TIME_BASE_LAST value */ ++#define S3C_MFC_PARAM_RET_DEC_PIC_NONB_TIME_LAST S3C_MFC(0x1ec) /* NONB_TIME_LAST value */ ++#define S3C_MFC_PARAM_RET_DEC_PIC_BCNT S3C_MFC(0x1f0) /* the size of frame consumed */ ++ ++/* Parameter register encode pic run */ ++#define S3C_MFC_PARAM_ENC_PIC_RUN S3C_MFC_PARAM ++#define S3C_MFC_PARAM_ENC_PIC_SRC_ADDR_Y S3C_MFC(0x180) ++#define S3C_MFC_PARAM_ENC_PIC_SRC_ADDR_CB S3C_MFC(0x184) ++#define S3C_MFC_PARAM_ENC_PIC_SRC_ADDR_CR S3C_MFC(0x188) ++#define S3C_MFC_PARAM_ENC_PIC_QS S3C_MFC(0x18c) ++#define S3C_MFC_PARAM_ENC_PIC_ROT_MODE S3C_MFC(0x190) ++#define S3C_MFC_PARAM_ENC_PIC_OPTION S3C_MFC(0x194) ++#define S3C_MFC_PARAM_ENC_PIC_BB_START S3C_MFC(0x198) ++#define S3C_MFC_PARAM_ENC_PIC_BB_SIZE S3C_MFC(0x19c) ++#define S3C_MFC_PARAM_ENC_PIC_RESERVED S3C_MFC(0x1a0) /* 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc */ ++/* output return */ ++#define S3C_MFC_PARAM_RET_ENC_PIC_FRAME_NUM S3C_MFC(0x1c0) ++#define S3C_MFC_PARAM_RET_ENC_PIC_TYPE S3C_MFC(0x1c4) ++#define S3C_MFC_PARAM_RET_ENC_PIC_IDX S3C_MFC(0x1c8) ++#define S3C_MFC_PARAM_RET_ENC_PIC_SLICE_NUM S3C_MFC(0x1cc) ++#define S3C_MFC_PARAM_RET_ENC_PIC_FLAG S3C_MFC(0x1d0) ++ ++/* Parameter register encode parameter set */ ++#define S3C_MFC_PARAM_ENC_PARA_SET S3C_MFC_PARAM ++#define S3C_MFC_PARAM_ENC_PARA_SET_TYPE S3C_MFC(0x180) ++#define S3C_MFC_PARAM_ENC_RESERVED S3C_MFC(0x184) ++/* output return */ ++#define S3C_MFC_PARAM_RET_ENC_PARA_SET_SIZE S3C_MFC(0x1c0) ++ ++/* Parameter register encode header */ ++#define S3C_MFC_PARAM_ENC_HEADER S3C_MFC_PARAM ++#define S3C_MFC_PARAM_ENC_HEADER_CODE S3C_MFC(0x180) ++#define S3C_MFC_PARAM_ENC_HEADER_BB_START S3C_MFC(0x184) ++#define S3C_MFC_PARAM_ENC_HEADER_BB_SIZE S3C_MFC(0x188) ++#define S3C_MFC_PARAM_ENC_HEADER_NUM S3C_MFC(0x18c) ++#define S3C_MFC_PARAM_ENC_HEADER_RESERVED S3C_MFC(0x190) ++ ++ ++/* Parameter register encode parameter change */ ++#define S3C_MFC_PARAM_ENC_CHANGE S3C_MFC_PARAM ++#define S3C_MFC_PARAM_ENC_CHANGE_ENABLE S3C_MFC(0x180) ++#define S3C_MFC_PARAM_ENC_CHANGE_GOP_NUM S3C_MFC(0x184) ++#define S3C_MFC_PARAM_ENC_CHANGE_INTRA_QP S3C_MFC(0x188) ++#define S3C_MFC_PARAM_ENC_CHANGE_BITRATE S3C_MFC(0x18c) ++#define S3C_MFC_PARAM_ENC_CHANGE_F_RATE S3C_MFC(0x190) ++#define S3C_MFC_PARAM_ENC_CHANGE_INTRA_REFRESH S3C_MFC(0x194) ++#define S3C_MFC_PARAM_ENC_CHANGE_SLICE_MODE S3C_MFC(0x198) ++#define S3C_MFC_PARAM_ENC_CHANGE_HEC_MODE S3C_MFC(0x19c) ++#define S3C_MFC_PARAM_ENC_CHANGE_RESERVED S3C_MFC(0x1a0) /* 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc */ ++#define S3C_MFC_PARAM_ENC_CHANGE_RESERVED0 S3C_MFC(0x1a0) ++#define S3C_MFC_PARAM_ENC_CHANGE_RESERVED1 S3C_MFC(0x1a4) ++#define S3C_MFC_PARAM_ENC_CHANGE_RESERVED2 S3C_MFC(0x1a8) ++#define S3C_MFC_PARAM_ENC_CHANGE_RESERVED3 S3C_MFC(0x1ac) ++#define S3C_MFC_PARAM_ENC_CHANGE_RESERVED4 S3C_MFC(0x1b0) ++#define S3C_MFC_PARAM_ENC_CHANGE_RESERVED5 S3C_MFC(0x1b4) ++#define S3C_MFC_PARAM_ENC_CHANGE_RESERVED6 S3C_MFC(0x1b8) ++#define S3C_MFC_PARAM_ENC_CHANGE_RESERVED7 S3C_MFC(0x1bc) ++ ++#define S3C_MFC_PARAM_RET_ENC_CHANGE_SUCCESS S3C_MFC(0x1c0) ++ ++/* Parameter register firmware version */ ++#define S3C_MFC_PARAM_FIRMWARE_VER S3C_MFC_PARAM ++#define S3C_MFC_PARAM_FIRMWARE_VER_RESERVED S3C_MFC(0x180) /* 0x180 ~ 0x1bc */ ++#define S3C_MFC_PARAM_FIRMWARE_VER_GET_FW_VER S3C_MFC(0x1c0) ++ ++ ++/* ++ * Because SW_RESET register is located apart(address 0xe00), unlike other MFC_SFR registers, ++ * I have excluded it in S3C_MFC_SFR struct and defined relative address only. ++ * When do virtual memory mapping in setting up memory, we have to map until this SW_RESET register. ++ */ ++#define S3C_MFC_SFR_SW_RESET_ADDR S3C_MFC(0x0e00) ++#define S3C_MFC_SFR_SIZE S3C_MFC(0x0e00) ++ ++ ++/************************************************************************* ++ * Bit definition part ++ ************************************************************************/ ++ ++/* SDRAM buffer control options */ ++#define STREAM_ENDIAN_LITTLE (0<<0) ++#define STREAM_ENDIAN_BIG (1<<0) ++#define BUF_STATUS_FULL_EMPTY_CHECK_BIT (0<<1) ++#define BUF_STATUS_NO_CHECK_BIT (1<<1) ++ ++/* FRAME_BUF_CTRL (0x110) */ ++#define FRAME_MEM_ENDIAN_LITTLE (0<<0) ++#define FRAME_MEM_ENDIAN_BIG (1<<0) ++ ++/* ++ * PRiSM-CX Video Codec IP's Register ++ * V178 ++ */ ++ ++/* DEC_SEQ_INIT Parameter Register */ ++/* DEC_SEQ_OPTION (0x18c) */ ++#define MP4_DBK_DISABLE (0<<0) ++#define MP4_DBK_ENABLE (1<<0) ++#define REORDER_DISABLE (0<<1) ++#define REORDER_ENABLE (1<<1) ++#define FILEPLAY_ENABLE (1<<2) ++#define FILEPLAY_DISABLE (0<<2) ++#define DYNBUFALLOC_ENABLE (1<<3) ++#define DYNBUFALLOC_DISABLE (0<<3) ++ ++/* ENC_SEQ_INIT Parameter Register */ ++/* ENC_SEQ_OPTION (0x188) */ ++#define MB_BIT_REPORT_DISABLE (0<<0) ++#define MB_BIT_REPORT_ENABLE (1<<0) ++#define SLICE_INFO_REPORT_DISABLE (0<<1) ++#define SLICE_INFO_REPORT_ENABLE (1<<1) ++#define AUD_DISABLE (0<<2) ++#define AUD_ENABLE (1<<2) ++#define MB_QP_REPORT_DISABLE (0<<3) ++#define MB_QP_REPORT_ENBLE (1<<3) ++#define CONST_QP_DISABLE (0<<5) ++#define CONST_QP_ENBLE (1<<5) ++ ++/* ENC_SEQ_COD_STD (0x18C) */ ++#define MPEG4_ENCODE 0 ++#define H263_ENCODE 1 ++#define H264_ENCODE 2 ++ ++/* ENC_SEQ_MP4_PARA (0x198) */ ++#define DATA_PART_DISABLE (0<<0) ++#define DATA_PART_ENABLE (1<<0) ++ ++/* ENC_SEQ_263_PARA (0x19C) */ ++#define ANNEX_T_OFF (0<<0) ++#define ANNEX_T_ON (1<<0) ++#define ANNEX_K_OFF (0<<1) ++#define ANNEX_K_ON (1<<1) ++#define ANNEX_J_OFF (0<<2) ++#define ANNEX_J_ON (1<<2) ++#define ANNEX_I_OFF (0<<3) ++#define ANNEX_I_ON (1<<3) ++ ++/* ENC_SEQ_SLICE_MODE (0x1A4) */ ++#define SLICE_MODE_ONE (0<<0) ++#define SLICE_MODE_MULTIPLE (1<<0) ++ ++/* ENC_SEQ_RC_PARA (0x1AC) */ ++#define RC_DISABLE (0<<0) /* RC means rate control */ ++#define RC_ENABLE (1<<0) ++#define SKIP_DISABLE (1<<31) ++#define SKIP_ENABLE (0<<31) ++ ++/* ENC_SEQ_FMO (0x1B8) */ ++#define FMO_DISABLE (0<<0) ++#define FMO_ENABLE (1<<0) ++ ++/* ENC_SEQ_RC_OPTION (0x1C4) */ ++#define USER_QP_MAX_DISABLE (0<<0) ++#define USER_QP_MAX_ENABLE (1<<0) ++#define USE_GAMMA_DISABLE (0<<1) ++#define USE_GAMMA_ENABLE (1<<1) ++ ++ ++ ++#endif /* __ASM_ARCH_REGS_MFC_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/s3c6400.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/s3c6400.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/s3c6400.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/s3c6400.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,35 @@ ++/* arch/arm/plat-s3c64xx/include/plat/s3c6400.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * Header file for s3c6400 cpu support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++/* Common init code for S3C6400 related SoCs */ ++ ++extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); ++extern void s3c6400_register_clocks(void); ++extern void s3c6400_setup_clocks(void); ++ ++#ifdef CONFIG_CPU_S3C6400 ++ ++extern int s3c6400_init(void); ++extern void s3c6400_map_io(void); ++extern void s3c6400_init_clocks(int xtal); ++ ++#define s3c6400_init_uarts s3c6400_common_init_uarts ++ ++#else ++#define s3c6400_init_clocks NULL ++#define s3c6400_init_uarts NULL ++#define s3c6400_map_io NULL ++#define s3c6400_init NULL ++#endif ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/s3c6410.h linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/s3c6410.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/include/plat/s3c6410.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/include/plat/s3c6410.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,29 @@ ++/* arch/arm/plat-s3c64xx/include/plat/s3c6410.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * Header file for s3c6410 cpu support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifdef CONFIG_CPU_S3C6410 ++ ++extern int s3c6410_init(void); ++extern void s3c6410_init_irq(void); ++extern void s3c6410_map_io(void); ++extern void s3c6410_init_clocks(int xtal); ++ ++#define s3c6410_init_uarts s3c6400_common_init_uarts ++ ++#else ++#define s3c6410_init_clocks NULL ++#define s3c6410_init_uarts NULL ++#define s3c6410_map_io NULL ++#define s3c6410_init NULL ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/irq-eint-group.c linux-2.6.28.6/arch/arm/plat-s3c64xx/irq-eint-group.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/irq-eint-group.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/irq-eint-group.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,378 @@ ++/* arch/arm/plat-s3c64xx/irq-eint-group.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C64XX - Interrupt handling for IRQ_EINT(x) ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++ ++#define S3C64XX_EINT_MAX_SOURCES 16 ++ ++struct s3c_eint_group_t { ++ int sources; ++ int base; ++ void __iomem *cont_reg; ++ void __iomem *mask_reg; ++ void __iomem *pend_reg; ++ int mask_ofs; ++ int pend_ofs; ++ ++ /* start offset in control register for each source */ ++ int cont_map[S3C64XX_EINT_MAX_SOURCES]; ++}; ++ ++static struct s3c_eint_group_t eint_groups[] = { ++ [0] = { ++ .sources = 0, ++ .base = 0, ++ .cont_reg = 0x0, ++ .mask_reg = 0x0, ++ .pend_reg = 0x0, ++ .mask_ofs = 0, ++ .pend_ofs = 0, ++ .cont_map = { ++ -1, -1, -1, -1, -1, -1, -1, -1, ++ -1, -1, -1, -1, -1, -1, -1, -1, ++ }, ++ }, ++ [1] = { ++ .sources = IRQ_EINT_GROUP1_NR, ++ .base = IRQ_EINT_GROUP1_BASE, ++ .cont_reg = S3C64XX_VA_GPIO + 0x200, ++ .mask_reg = S3C64XX_VA_GPIO + 0x240, ++ .pend_reg = S3C64XX_VA_GPIO + 0x260, ++ .mask_ofs = 0, ++ .pend_ofs = 0, ++ .cont_map = { ++ 0, 0, 0, 0, 4, 4, 4, 4, ++ 8, 8, 8, 8, 12, 12, 12, -1, ++ }, ++ }, ++ [2] = { ++ .sources = IRQ_EINT_GROUP2_NR, ++ .base = IRQ_EINT_GROUP2_BASE, ++ .cont_reg = S3C64XX_VA_GPIO + 0x200, ++ .mask_reg = S3C64XX_VA_GPIO + 0x240, ++ .pend_reg = S3C64XX_VA_GPIO + 0x260, ++ .mask_ofs = 16, ++ .pend_ofs = 16, ++ .cont_map = { ++ 16, 16, 16, 16, 20, 20, 20, 20, ++ -1, -1, -1, -1, -1, -1, -1, -1, ++ }, ++ }, ++ [3] = { ++ .sources = IRQ_EINT_GROUP3_NR, ++ .base = IRQ_EINT_GROUP3_BASE, ++ .cont_reg = S3C64XX_VA_GPIO + 0x204, ++ .mask_reg = S3C64XX_VA_GPIO + 0x244, ++ .pend_reg = S3C64XX_VA_GPIO + 0x264, ++ .mask_ofs = 0, ++ .pend_ofs = 0, ++ .cont_map = { ++ 0, 0, 0, 0, 4, -1, -1, -1, ++ -1, -1, -1, -1, -1, -1, -1, -1, ++ }, ++ }, ++ [4] = { ++ .sources = IRQ_EINT_GROUP4_NR, ++ .base = IRQ_EINT_GROUP4_BASE, ++ .cont_reg = S3C64XX_VA_GPIO + 0x204, ++ .mask_reg = S3C64XX_VA_GPIO + 0x244, ++ .pend_reg = S3C64XX_VA_GPIO + 0x264, ++ .mask_ofs = 16, ++ .pend_ofs = 16, ++ .cont_map = { ++ 16, 16, 16, 16, 20, 20, 20, 20, ++ 24, 24, 24, 24, 28, 28, -1, -1, ++ }, ++ }, ++ [5] = { ++ .sources = IRQ_EINT_GROUP5_NR, ++ .base = IRQ_EINT_GROUP5_BASE, ++ .cont_reg = S3C64XX_VA_GPIO + 0x208, ++ .mask_reg = S3C64XX_VA_GPIO + 0x248, ++ .pend_reg = S3C64XX_VA_GPIO + 0x268, ++ .mask_ofs = 0, ++ .pend_ofs = 0, ++ .cont_map = { ++ 0, 0, 0, 0, 4, 4, 4, -1 ++ -1, -1, -1, -1, -1, -1, -1, -1, ++ }, ++ }, ++ [6] = { ++ .sources = IRQ_EINT_GROUP6_NR, ++ .base = IRQ_EINT_GROUP6_BASE, ++ .cont_reg = S3C64XX_VA_GPIO + 0x208, ++ .mask_reg = S3C64XX_VA_GPIO + 0x248, ++ .pend_reg = S3C64XX_VA_GPIO + 0x268, ++ .mask_ofs = 16, ++ .pend_ofs = 16, ++ .cont_map = { ++ 16, 16, 16, 16, 20, 20, 20, 20, ++ 24, 24, -1, -1, -1, -1, -1, -1, ++ }, ++ }, ++ [7] = { ++ .sources = IRQ_EINT_GROUP7_NR, ++ .base = IRQ_EINT_GROUP7_BASE, ++ .cont_reg = S3C64XX_VA_GPIO + 0x20c, ++ .mask_reg = S3C64XX_VA_GPIO + 0x24c, ++ .pend_reg = S3C64XX_VA_GPIO + 0x26c, ++ .mask_ofs = 0, ++ .pend_ofs = 0, ++ .cont_map = { ++ 0, 0, 0, 0, 4, 4, 4, 4, ++ 8, 8, 8, 8, 12, 12, 12, 12, ++ }, ++ }, ++ [8] = { ++ .sources = IRQ_EINT_GROUP8_NR, ++ .base = IRQ_EINT_GROUP8_BASE, ++ .cont_reg = S3C64XX_VA_GPIO + 0x20c, ++ .mask_reg = S3C64XX_VA_GPIO + 0x24c, ++ .pend_reg = S3C64XX_VA_GPIO + 0x26c, ++ .mask_ofs = 16, ++ .pend_ofs = 16, ++ .cont_map = { ++ 16, 16, 16, 16, 20, 20, 20, 20, ++ 24, 24, 24, 24, 28, 28, 28, -1, ++ }, ++ }, ++ [9] = { ++ .sources = IRQ_EINT_GROUP9_NR, ++ .base = IRQ_EINT_GROUP9_BASE, ++ .cont_reg = S3C64XX_VA_GPIO + 0x210, ++ .mask_reg = S3C64XX_VA_GPIO + 0x250, ++ .pend_reg = S3C64XX_VA_GPIO + 0x270, ++ .mask_ofs = 0, ++ .pend_ofs = 0, ++ .cont_map = { ++ 0, 0, 0, 0, 4, 4, 4, 4, ++ 4, -1, -1, -1, -1, -1, -1, -1, ++ }, ++ }, ++}; ++ ++#define S3C_EINT_GROUPS (sizeof(eint_groups) / sizeof(eint_groups[0])) ++ ++static int to_group_number(unsigned int irq) ++{ ++ int grp, found; ++ ++ for (grp = 1; grp < S3C_EINT_GROUPS; grp++) { ++ if (irq >= eint_groups[grp].base + eint_groups[grp].sources) ++ continue; ++ else { ++ found = 1; ++ break; ++ } ++ } ++ ++ if (!found) { ++ printk(KERN_ERR "failed to find out the eint group number\n"); ++ grp = 0; ++ } ++ ++ return grp; ++} ++ ++static inline int to_irq_number(int grp, unsigned int irq) ++{ ++ return irq - eint_groups[grp].base; ++} ++ ++static inline int to_bit_offset(int grp, unsigned int irq) ++{ ++ int offset; ++ ++ offset = eint_groups[grp].cont_map[to_irq_number(grp, irq)]; ++ ++ if (offset == -1) { ++ printk(KERN_ERR "invalid bit offset\n"); ++ offset = 0; ++ } ++ ++ return offset; ++} ++ ++static inline void s3c_irq_eint_group_mask(unsigned int irq) ++{ ++ struct s3c_eint_group_t *group; ++ int grp; ++ u32 mask; ++ ++ grp = to_group_number(irq); ++ group = &eint_groups[grp]; ++ ++ mask = __raw_readl(group->mask_reg); ++ mask |= (1 << (group->mask_ofs + to_irq_number(grp, irq))); ++ ++ __raw_writel(mask, group->mask_reg); ++} ++ ++static void s3c_irq_eint_group_unmask(unsigned int irq) ++{ ++ struct s3c_eint_group_t *group; ++ int grp; ++ u32 mask; ++ ++ grp = to_group_number(irq); ++ group = &eint_groups[grp]; ++ ++ mask = __raw_readl(group->mask_reg); ++ mask &= ~(1 << (group->mask_ofs + to_irq_number(grp, irq))); ++ ++ __raw_writel(mask, group->mask_reg); ++} ++ ++static inline void s3c_irq_eint_group_ack(unsigned int irq) ++{ ++ struct s3c_eint_group_t *group; ++ int grp; ++ u32 pend; ++ ++ grp = to_group_number(irq); ++ group = &eint_groups[grp]; ++ ++ pend = (1 << (group->pend_ofs + to_irq_number(grp, irq))); ++ ++ __raw_writel(pend, group->pend_reg); ++} ++ ++static void s3c_irq_eint_group_maskack(unsigned int irq) ++{ ++ /* compiler should in-line these */ ++ s3c_irq_eint_group_mask(irq); ++ s3c_irq_eint_group_ack(irq); ++} ++ ++static int s3c_irq_eint_group_set_type(unsigned int irq, unsigned int type) ++{ ++ struct s3c_eint_group_t *group; ++ int grp, shift; ++ u32 ctrl, mask, newvalue = 0; ++ ++ grp = to_group_number(irq); ++ group = &eint_groups[grp]; ++ ++ switch (type) { ++ case IRQ_TYPE_NONE: ++ printk(KERN_WARNING "No edge setting!\n"); ++ break; ++ ++ case IRQ_TYPE_EDGE_RISING: ++ newvalue = S3C2410_EXTINT_RISEEDGE; ++ break; ++ ++ case IRQ_TYPE_EDGE_FALLING: ++ newvalue = S3C2410_EXTINT_FALLEDGE; ++ break; ++ ++ case IRQ_TYPE_EDGE_BOTH: ++ newvalue = S3C2410_EXTINT_BOTHEDGE; ++ break; ++ ++ case IRQ_TYPE_LEVEL_LOW: ++ newvalue = S3C2410_EXTINT_LOWLEV; ++ break; ++ ++ case IRQ_TYPE_LEVEL_HIGH: ++ newvalue = S3C2410_EXTINT_HILEV; ++ break; ++ ++ default: ++ printk(KERN_ERR "No such irq type %d", type); ++ return -1; ++ } ++ ++ shift = to_bit_offset(grp, irq); ++ mask = 0x7 << shift; ++ ++ ctrl = __raw_readl(group->cont_reg); ++ ctrl &= ~mask; ++ ctrl |= newvalue << shift; ++ __raw_writel(ctrl, group->cont_reg); ++ ++ return 0; ++} ++ ++static struct irq_chip s3c_irq_eint_group = { ++ .name = "s3c-eint-group", ++ .mask = s3c_irq_eint_group_mask, ++ .unmask = s3c_irq_eint_group_unmask, ++ .mask_ack = s3c_irq_eint_group_maskack, ++ .ack = s3c_irq_eint_group_ack, ++ .set_type = s3c_irq_eint_group_set_type, ++}; ++ ++/* ++ * s3c_irq_demux_eint_group ++*/ ++static inline void s3c_irq_demux_eint_group(unsigned int irq, struct irq_desc *desc) ++{ ++ struct s3c_eint_group_t *group; ++ u32 status, mask, newirq; ++ int grp, src; ++ ++ for (grp = 1; grp < S3C_EINT_GROUPS; grp++) { ++ group = &eint_groups[grp]; ++ status = __raw_readl(group->pend_reg); ++ mask = __raw_readl(group->mask_reg); ++ ++ status &= ~mask; ++ status >>= group->pend_ofs; ++ status &= 0xffff; ++ ++ if (!status) ++ continue; ++ ++ for (src = 0; src < S3C64XX_EINT_MAX_SOURCES; src++) { ++ if (status & 1) { ++ newirq = group->base + src; ++ generic_handle_irq(newirq); ++ } ++ ++ status >>= 1; ++ } ++ } ++} ++ ++int __init s3c64xx_init_irq_eint_group(void) ++{ ++ int irq; ++ ++ for (irq = IRQ_EINT_GROUP_BASE; irq < NR_IRQS; irq++) { ++ set_irq_chip(irq, &s3c_irq_eint_group); ++ set_irq_handler(irq, handle_level_irq); ++ set_irq_flags(irq, IRQF_VALID); ++ } ++ ++ set_irq_chained_handler(IRQ_EINT_GROUPS, s3c_irq_demux_eint_group); ++ ++ return 0; ++} ++ ++arch_initcall(s3c64xx_init_irq_eint_group); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/irq-eint.c linux-2.6.28.6/arch/arm/plat-s3c64xx/irq-eint.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/irq-eint.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/irq-eint.c 2009-12-09 14:34:33.000000000 +0100 +@@ -0,0 +1,211 @@ ++/* arch/arm/plat-s3c64xx/irq-eint.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C64XX - Interrupt handling for IRQ_EINT(x) ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#define eint_offset(irq) ((irq) - IRQ_EINT(0)) ++#define eint_irq_to_bit(irq) (1 << eint_offset(irq)) ++ ++static inline void s3c_irq_eint_mask(unsigned int irq) ++{ ++ u32 mask; ++ ++ mask = __raw_readl(S3C64XX_EINT0MASK); ++ mask |= eint_irq_to_bit(irq); ++ __raw_writel(mask, S3C64XX_EINT0MASK); ++} ++ ++static void s3c_irq_eint_unmask(unsigned int irq) ++{ ++ u32 mask; ++ ++ mask = __raw_readl(S3C64XX_EINT0MASK); ++ mask &= ~(eint_irq_to_bit(irq)); ++ __raw_writel(mask, S3C64XX_EINT0MASK); ++} ++ ++static inline void s3c_irq_eint_ack(unsigned int irq) ++{ ++ __raw_writel(eint_irq_to_bit(irq), S3C64XX_EINT0PEND); ++} ++ ++static void s3c_irq_eint_maskack(unsigned int irq) ++{ ++ /* compiler should in-line these */ ++ s3c_irq_eint_mask(irq); ++ s3c_irq_eint_ack(irq); ++} ++ ++static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) ++{ ++ int offs = eint_offset(irq); ++ int shift; ++ u32 ctrl, mask; ++ u32 newvalue = 0; ++ void __iomem *reg; ++ ++ if (offs > 27) ++ return -EINVAL; ++ ++ /* fixed by jsgood */ ++ ++ ++ if (offs > 15) ++ reg = S3C64XX_EINT0CON1; /* org: reg = S3C64XX_EINT0CON0; */ ++ else ++ reg = S3C64XX_EINT0CON0; /* org: reg = S3C64XX_EINT0CON1; */ ++ ++ ++ switch (type) { ++ case IRQ_TYPE_NONE: ++ printk(KERN_WARNING "No edge setting!\n"); ++ break; ++ ++ case IRQ_TYPE_EDGE_RISING: ++ newvalue = S3C2410_EXTINT_RISEEDGE; ++ break; ++ ++ case IRQ_TYPE_EDGE_FALLING: ++ newvalue = S3C2410_EXTINT_FALLEDGE; ++ break; ++ ++ case IRQ_TYPE_EDGE_BOTH: ++ newvalue = S3C2410_EXTINT_BOTHEDGE; ++ break; ++ ++ case IRQ_TYPE_LEVEL_LOW: ++ newvalue = S3C2410_EXTINT_LOWLEV; ++ break; ++ ++ case IRQ_TYPE_LEVEL_HIGH: ++ newvalue = S3C2410_EXTINT_HILEV; ++ break; ++ ++ default: ++ printk(KERN_ERR "No such irq type %d", type); ++ return -1; ++ } ++ ++ /* fixed by jsgood */ ++ shift = ((offs % 16) / 2) * 4; /* org: shift = (offs / 2) * 4; */ ++ mask = 0x7 << shift; ++ ++ ctrl = __raw_readl(reg); ++ ctrl &= ~mask; ++ ctrl |= newvalue << shift; ++ __raw_writel(ctrl, reg); ++ ++ if (offs < 16) ++ s3c_gpio_cfgpin(S3C64XX_GPN(offs), 0x2 << (offs * 2)); ++ else if (offs < 23) ++ s3c_gpio_cfgpin(S3C64XX_GPL(offs - 8), S3C_GPIO_SFN(3)); ++ else ++ s3c_gpio_cfgpin(S3C64XX_GPM(offs - 23), S3C_GPIO_SFN(3)); ++ ++ return 0; ++} ++ ++ ++ ++ ++ ++ ++ ++static struct irq_chip s3c_irq_eint = { ++ .name = "s3c-eint", ++ .mask = s3c_irq_eint_mask, ++ .unmask = s3c_irq_eint_unmask, ++ .mask_ack = s3c_irq_eint_maskack, ++ .ack = s3c_irq_eint_ack, ++ .set_type = s3c_irq_eint_set_type, ++}; ++ ++/* s3c_irq_demux_eint ++ * ++ * This function demuxes the IRQ from the group0 external interrupts, ++ * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into ++ * the specific handlers s3c_irq_demux_eintX_Y. ++ */ ++static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end) ++{ ++ u32 status = __raw_readl(S3C64XX_EINT0PEND); ++ u32 mask = __raw_readl(S3C64XX_EINT0MASK); ++ unsigned int irq; ++ ++ status &= ~mask; ++ status >>= start; ++ status &= (1 << (end - start + 1)) - 1; ++ ++ for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) { ++ if (status & 1) ++ generic_handle_irq(irq); ++ ++ status >>= 1; ++ } ++} ++ ++static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_eint(0, 3); ++} ++ ++static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_eint(4, 11); ++} ++ ++static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_eint(12, 19); ++} ++ ++static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_eint(20, 27); ++} ++ ++int __init s3c64xx_init_irq_eint(void) ++{ ++ int irq; ++ ++ for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { ++ set_irq_chip(irq, &s3c_irq_eint); ++ set_irq_handler(irq, handle_level_irq); ++ set_irq_flags(irq, IRQF_VALID); ++ } ++ ++ set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3); ++ set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11); ++ set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19); ++ set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27); ++ ++ return 0; ++} ++ ++arch_initcall(s3c64xx_init_irq_eint); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/irq.c linux-2.6.28.6/arch/arm/plat-s3c64xx/irq.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/irq.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/irq.c 2009-12-08 17:25:02.000000000 +0100 +@@ -0,0 +1,322 @@ ++/* arch/arm/plat-s3c64xx/irq.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C64XX - Interrupt handling ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Timer interrupt handling */ ++ ++static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq) ++{ ++ generic_handle_irq(sub_irq); ++} ++ ++static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_timer(irq, IRQ_TIMER0); ++} ++ ++static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_timer(irq, IRQ_TIMER1); ++} ++ ++static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_timer(irq, IRQ_TIMER2); ++} ++ ++static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_timer(irq, IRQ_TIMER3); ++} ++ ++static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_timer(irq, IRQ_TIMER4); ++} ++ ++/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ ++ ++static void s3c_irq_timer_mask(unsigned int irq) ++{ ++ u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); ++ ++ reg &= 0x1f; /* mask out pending interrupts */ ++ reg &= ~(1 << (irq - IRQ_TIMER0)); ++ __raw_writel(reg, S3C64XX_TINT_CSTAT); ++} ++ ++static void s3c_irq_timer_unmask(unsigned int irq) ++{ ++ u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); ++ ++ reg &= 0x1f; /* mask out pending interrupts */ ++ reg |= 1 << (irq - IRQ_TIMER0); ++ __raw_writel(reg, S3C64XX_TINT_CSTAT); ++} ++ ++static void s3c_irq_timer_ack(unsigned int irq) ++{ ++ u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); ++ ++ reg &= 0x1f; ++ reg |= (1 << 5) << (irq - IRQ_TIMER0); ++ __raw_writel(reg, S3C64XX_TINT_CSTAT); ++} ++ ++static struct irq_chip s3c_irq_timer = { ++ .name = "s3c-timer", ++ .mask = s3c_irq_timer_mask, ++ .unmask = s3c_irq_timer_unmask, ++ .ack = s3c_irq_timer_ack, ++}; ++ ++struct uart_irq { ++ void __iomem *regs; ++ unsigned int base_irq; ++ unsigned int parent_irq; ++}; ++ ++/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] ++ * are consecutive when looking up the interrupt in the demux routines. ++ */ ++static struct uart_irq uart_irqs[] = { ++ [0] = { ++ .regs = S3C_VA_UART0, ++ .base_irq = IRQ_S3CUART_BASE0, ++ .parent_irq = IRQ_UART0, ++ }, ++ [1] = { ++ .regs = S3C_VA_UART1, ++ .base_irq = IRQ_S3CUART_BASE1, ++ .parent_irq = IRQ_UART1, ++ }, ++ [2] = { ++ .regs = S3C_VA_UART2, ++ .base_irq = IRQ_S3CUART_BASE2, ++ .parent_irq = IRQ_UART2, ++ }, ++ [3] = { ++ .regs = S3C_VA_UART3, ++ .base_irq = IRQ_S3CUART_BASE3, ++ .parent_irq = IRQ_UART3, ++ }, ++}; ++ ++static inline void __iomem *s3c_irq_uart_base(unsigned int irq) ++{ ++ struct uart_irq *uirq = get_irq_chip_data(irq); ++ return uirq->regs; ++} ++ ++static inline unsigned int s3c_irq_uart_bit(unsigned int irq) ++{ ++ return irq & 3; ++} ++ ++/* UART interrupt registers, not worth adding to seperate include header */ ++#define S3C64XX_UINTP 0x30 ++#define S3C64XX_UINTSP 0x34 ++#define S3C64XX_UINTM 0x38 ++ ++static void s3c_irq_uart_mask(unsigned int irq) ++{ ++ void __iomem *regs = s3c_irq_uart_base(irq); ++ unsigned int bit = s3c_irq_uart_bit(irq); ++ u32 reg; ++ ++ reg = __raw_readl(regs + S3C64XX_UINTM); ++ reg |= (1 << bit); ++ __raw_writel(reg, regs + S3C64XX_UINTM); ++} ++ ++static void s3c_irq_uart_maskack(unsigned int irq) ++{ ++ void __iomem *regs = s3c_irq_uart_base(irq); ++ unsigned int bit = s3c_irq_uart_bit(irq); ++ u32 reg; ++ ++ reg = __raw_readl(regs + S3C64XX_UINTM); ++ reg |= (1 << bit); ++ __raw_writel(reg, regs + S3C64XX_UINTM); ++ __raw_writel(1 << bit, regs + S3C64XX_UINTP); ++} ++ ++static void s3c_irq_uart_unmask(unsigned int irq) ++{ ++ void __iomem *regs = s3c_irq_uart_base(irq); ++ unsigned int bit = s3c_irq_uart_bit(irq); ++ u32 reg; ++ ++ reg = __raw_readl(regs + S3C64XX_UINTM); ++ reg &= ~(1 << bit); ++ __raw_writel(reg, regs + S3C64XX_UINTM); ++} ++ ++static void s3c_irq_uart_ack(unsigned int irq) ++{ ++ void __iomem *regs = s3c_irq_uart_base(irq); ++ unsigned int bit = s3c_irq_uart_bit(irq); ++ ++ __raw_writel(1 << bit, regs + S3C64XX_UINTP); ++} ++ ++static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) ++{ ++ struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0]; ++ u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP); ++ int base = uirq->base_irq; ++ ++ if (pend & (1 << 0)) ++ generic_handle_irq(base); ++ if (pend & (1 << 1)) ++ generic_handle_irq(base + 1); ++ if (pend & (1 << 2)) ++ generic_handle_irq(base + 2); ++ if (pend & (1 << 3)) ++ generic_handle_irq(base + 3); ++} ++ ++static struct irq_chip s3c_irq_uart = { ++ .name = "s3c-uart", ++ .mask = s3c_irq_uart_mask, ++ .unmask = s3c_irq_uart_unmask, ++ .mask_ack = s3c_irq_uart_maskack, ++ .ack = s3c_irq_uart_ack, ++}; ++ ++static void __init s3c64xx_uart_irq(struct uart_irq *uirq) ++{ ++ void *reg_base = uirq->regs; ++ unsigned int irq; ++ int offs; ++ ++ /* mask all interrupts at the start. */ ++ __raw_writel(0xf, reg_base + S3C64XX_UINTM); ++ ++ for (offs = 0; offs < 3; offs++) { ++ irq = uirq->base_irq + offs; ++ ++ set_irq_chip(irq, &s3c_irq_uart); ++ set_irq_chip_data(irq, uirq); ++ set_irq_handler(irq, handle_level_irq); ++ set_irq_flags(irq, IRQF_VALID); ++ } ++ ++ set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); ++} ++#ifdef CONFIG_PM ++static struct sleep_save extirq_save[] = { ++ SAVE_ITEM(S3C64XX_EINT0CON0), ++ SAVE_ITEM(S3C64XX_EINT0CON1), ++ SAVE_ITEM(S3C64XX_EINT0FLTCON0), ++ SAVE_ITEM(S3C64XX_EINT0FLTCON1), ++ SAVE_ITEM(S3C64XX_EINT0FLTCON2), ++ SAVE_ITEM(S3C64XX_EINT0FLTCON3), ++ SAVE_ITEM(S3C64XX_EINT0MASK), ++ SAVE_ITEM(S3C64XX_EINT12CON), ++ SAVE_ITEM(S3C64XX_EINT34CON), ++ SAVE_ITEM(S3C64XX_EINT56CON), ++ SAVE_ITEM(S3C64XX_EINT78CON), ++ SAVE_ITEM(S3C64XX_EINT9CON), ++ SAVE_ITEM(S3C64XX_EINT12FLTCON), ++ SAVE_ITEM(S3C64XX_EINT34FLTCON), ++ SAVE_ITEM(S3C64XX_EINT56FLTCON), ++ SAVE_ITEM(S3C64XX_EINT78FLTCON), ++ SAVE_ITEM(S3C64XX_EINT9FLTCON), ++ SAVE_ITEM(S3C64XX_EINT12MASK), ++ SAVE_ITEM(S3C64XX_EINT34MASK), ++ SAVE_ITEM(S3C64XX_EINT56MASK), ++ SAVE_ITEM(S3C64XX_EINT78MASK), ++ SAVE_ITEM(S3C64XX_EINT9MASK), ++ SAVE_ITEM(S3C64XX_EINT34FLTCON), ++ SAVE_ITEM(S3C64XX_EINT56FLTCON), ++ SAVE_ITEM(S3C64XX_EINT78FLTCON), ++ SAVE_ITEM(S3C64XX_EINT9FLTCON), ++}; ++ ++int s3c64xx_irq_suspend(struct sys_device *dev, pm_message_t state) ++{ ++ s3c6410_pm_do_save(extirq_save, ARRAY_SIZE(extirq_save)); ++ return 0; ++} ++ ++int s3c64xx_irq_resume(struct sys_device *dev) ++{ ++ int irqno; ++ int irqindex = 0; ++ /* For writing the IRQ number into the VICVECTADDR */ ++ s3c6410_pm_do_restore(extirq_save, ARRAY_SIZE(extirq_save)); ++ ++ for (irqno = IRQ_EINT0_3; irqno <= IRQ_LCD_SYSTEM; irqno++) { ++ __raw_writel(irqno, S3C64XX_VIC0VECTADDR0 + irqindex); ++ irqindex = irqindex + 4; ++ } ++ ++ irqindex = 0; ++ for (irqno = IRQ_EINT12_19; irqno <= IRQ_ADC; irqno++) { ++ __raw_writel(irqno, S3C64XX_VIC1VECTADDR0 + irqindex); ++ irqindex = irqindex + 4; ++ } ++ return 0; ++} ++#else ++#define s3c64xx_irq_suspend NULL ++#define s3c64xx_irq_resume NULL ++#endif ++ ++void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) ++{ ++ int uart, irq; ++ ++ printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); ++ ++ /* initialise the pair of VICs */ ++ vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid); ++ vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid); ++ ++ /* add the timer sub-irqs */ ++ ++ set_irq_chained_handler(IRQ_TIMER0_VIC, s3c_irq_demux_timer0); ++ set_irq_chained_handler(IRQ_TIMER1_VIC, s3c_irq_demux_timer1); ++ set_irq_chained_handler(IRQ_TIMER2_VIC, s3c_irq_demux_timer2); ++ set_irq_chained_handler(IRQ_TIMER3_VIC, s3c_irq_demux_timer3); ++ set_irq_chained_handler(IRQ_TIMER4_VIC, s3c_irq_demux_timer4); ++ ++ for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) { ++ set_irq_chip(irq, &s3c_irq_timer); ++ set_irq_handler(irq, handle_level_irq); ++ set_irq_flags(irq, IRQF_VALID); ++ } ++ ++ for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++) ++ s3c64xx_uart_irq(&uart_irqs[uart]); ++} ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/ltc3714.c linux-2.6.28.6/arch/arm/plat-s3c64xx/ltc3714.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/ltc3714.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/ltc3714.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,152 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#define ARM_LE 0 ++#define INT_LE 1 ++ ++/* ltc3714 voltage table */ ++static const unsigned int voltage_table[32] = { ++ 1750, 1700, 1650, 1600, 1550, 1500, 1450, 1400, ++ 1350, 1300, 1250, 1200, 1150, 1100, 1050, 1000, ++ 975, 950, 925, 900, 875, 850, 825, 800, ++ 775, 750, 725, 700, 675, 650, 625, 600, ++}; ++ ++/* frequency voltage matching table */ ++static const unsigned int frequency_match[][3] = { ++/* frequency, Mathced VDD ARM voltage , Matched VDD INT*/ ++ {667000, 1200, 1300}, ++ {333000, 1100, 1200}, ++ {222000, 1050, 1200}, ++ {133000, 1000, 1200}, ++ {66000, 1000, 1000}, ++}; ++ ++/* LTC3714 Setting Routine */ ++static int ltc3714_gpio_setting(void) ++{ ++ gpio_direction_output(S3C64XX_GPN(11), 0); ++ gpio_direction_output(S3C64XX_GPN(12), 0); ++ gpio_direction_output(S3C64XX_GPN(13), 0); ++ gpio_direction_output(S3C64XX_GPN(14), 0); ++ gpio_direction_output(S3C64XX_GPN(15), 0); ++ gpio_direction_output(S3C64XX_GPL(8), 0); ++ gpio_direction_output(S3C64XX_GPL(9), 0); ++ gpio_direction_output(S3C64XX_GPL(10), 0); ++ ++ s3c_gpio_setpull(S3C64XX_GPN(11), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S3C64XX_GPN(13), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S3C64XX_GPN(14), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S3C64XX_GPN(15), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S3C64XX_GPL(8), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S3C64XX_GPL(9), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S3C64XX_GPL(10), S3C_GPIO_PULL_NONE); ++ ++ return 0; ++} ++ ++static int set_ltc3714(unsigned int pwr, unsigned int index) ++{ ++ int position = 0; ++ ++ int voltage = frequency_match[index][pwr + 1]; ++ ++ if(voltage > voltage_table[0] || voltage < voltage_table[31]) { ++ printk("[ERROR]: voltage value over limits!!!"); ++ return -EINVAL; ++ } ++ ++ if(voltage > voltage_table[16]) { // 1750 ~ 1000 mV ++ for(position = 15; position >= 0; position --) { ++ if(voltage_table[position] == voltage) break; ++ } ++ ++ } ++ else if(voltage >= voltage_table[31]) { //975 ~ 600 mV ++ for(position = 31; position >= 16; position --) { ++ if(voltage_table[position] == voltage) break; ++ } ++ } ++ else { ++ printk("[error]: Can't find adquate voltage table list value\n"); ++ return -EINVAL; ++ } ++ ++ position &=0x1f; ++ ++ gpio_set_value(S3C64XX_GPN(11),(position >> 0)&0x1); ++ gpio_set_value(S3C64XX_GPN(12),(position >> 1)&0x1); ++ gpio_set_value(S3C64XX_GPN(13),(position >> 2)&0x1); ++ gpio_set_value(S3C64XX_GPN(14),(position >> 3)&0x1); ++ gpio_set_value(S3C64XX_GPN(15),(position >> 4)&0x1); ++ ++ if(pwr == ARM_LE) { ++ gpio_set_value(S3C64XX_GPL(8), 1); ++ udelay(10); ++ gpio_set_value(S3C64XX_GPL(8), 0); ++ } else if(pwr == INT_LE) { ++ gpio_set_value(S3C64XX_GPL(10), 1); ++ udelay(10); ++ gpio_set_value(S3C64XX_GPL(10), 0); ++ } else { ++ printk("[error]: set_power, check mode [pwr] value\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int find_voltage(int freq) ++{ ++ int index = 0; ++ ++ if(freq > frequency_match[0][0]){ ++ printk(KERN_ERR "frequecy is over then support frequency\n"); ++ return 0; ++ } ++ ++ for(index = 0 ; index < ARRAY_SIZE(frequency_match) ; index++){ ++ if(freq >= frequency_match[index][0]) ++ return index; ++ } ++ ++ printk("Cannot find matched voltage on table\n"); ++ ++ return 0; ++} ++ ++int set_power(unsigned int freq) ++{ ++ int index; ++ ++ index = find_voltage(freq); ++ ++ set_ltc3714(ARM_LE, index); ++ ++ return 0; ++} ++ ++EXPORT_SYMBOL(set_power); ++ ++void ltc3714_init(void) ++{ ++ ltc3714_gpio_setting(); ++ set_power(532000); ++ gpio_set_value(S3C64XX_GPL(9), 1); ++} ++ ++EXPORT_SYMBOL(ltc3714_init); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/pm.c linux-2.6.28.6/arch/arm/plat-s3c64xx/pm.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/pm.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/pm.c 2009-12-08 12:07:59.000000000 +0100 +@@ -0,0 +1,672 @@ ++/* linux/arch/arm/plat-s3c24xx/pm.c ++ * ++ * Copyright (c) 2004,2006 Simtec Electronics ++ * Ben Dooks ++ * ++ * S3C24XX Power Manager (Suspend-To-RAM) support ++ * ++ * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * Parts based on arch/arm/mach-pxa/pm.c ++ * ++ * Thanks to Dimitry Andric for debugging ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++ ++/* for external use */ ++ ++unsigned long s3c_pm_flags; ++ ++#define PFX "s3c64xx-pm: " ++static struct sleep_save core_save[] = { ++ SAVE_ITEM(S3C_SDMA_SEL), ++}; ++ ++static struct sleep_save gpio_save[] = { ++ SAVE_ITEM(S3C64XX_GPACON), ++ SAVE_ITEM(S3C64XX_GPADAT), ++ SAVE_ITEM(S3C64XX_GPAPUD), ++ SAVE_ITEM(S3C64XX_GPBCON), ++ SAVE_ITEM(S3C64XX_GPBDAT), ++ SAVE_ITEM(S3C64XX_GPBPUD), ++ SAVE_ITEM(S3C64XX_GPCCON), ++ SAVE_ITEM(S3C64XX_GPCDAT), ++ SAVE_ITEM(S3C64XX_GPCPUD), ++ SAVE_ITEM(S3C64XX_GPDCON), ++ SAVE_ITEM(S3C64XX_GPDDAT), ++ SAVE_ITEM(S3C64XX_GPDPUD), ++ SAVE_ITEM(S3C64XX_GPECON), ++ SAVE_ITEM(S3C64XX_GPEDAT), ++ SAVE_ITEM(S3C64XX_GPEPUD), ++ SAVE_ITEM(S3C64XX_GPFCON), ++ SAVE_ITEM(S3C64XX_GPFDAT), ++ SAVE_ITEM(S3C64XX_GPFPUD), ++ SAVE_ITEM(S3C64XX_GPGCON), ++ SAVE_ITEM(S3C64XX_GPGDAT), ++ SAVE_ITEM(S3C64XX_GPGPUD), ++ SAVE_ITEM(S3C64XX_GPHCON0), ++ SAVE_ITEM(S3C64XX_GPHCON1), ++ SAVE_ITEM(S3C64XX_GPHDAT), ++ SAVE_ITEM(S3C64XX_GPHPUD), ++ SAVE_ITEM(S3C64XX_GPICON), ++ SAVE_ITEM(S3C64XX_GPIDAT), ++ SAVE_ITEM(S3C64XX_GPIPUD), ++ SAVE_ITEM(S3C64XX_GPJCON), ++ SAVE_ITEM(S3C64XX_GPJDAT), ++ SAVE_ITEM(S3C64XX_GPJPUD), ++ SAVE_ITEM(S3C64XX_GPKCON), ++ SAVE_ITEM(S3C64XX_GPKDAT), ++ SAVE_ITEM(S3C64XX_GPKPUD), ++ SAVE_ITEM(S3C64XX_GPLCON), ++ SAVE_ITEM(S3C64XX_GPLDAT), ++ SAVE_ITEM(S3C64XX_GPLPUD), ++ SAVE_ITEM(S3C64XX_GPMCON), ++ SAVE_ITEM(S3C64XX_GPMDAT), ++ SAVE_ITEM(S3C64XX_GPMPUD), ++ SAVE_ITEM(S3C64XX_GPNCON), ++ SAVE_ITEM(S3C64XX_GPNDAT), ++ SAVE_ITEM(S3C64XX_GPNPUD), ++ SAVE_ITEM(S3C64XX_GPOCON), ++ SAVE_ITEM(S3C64XX_GPODAT), ++ SAVE_ITEM(S3C64XX_GPOPUD), ++ SAVE_ITEM(S3C64XX_GPPCON), ++ SAVE_ITEM(S3C64XX_GPPDAT), ++ SAVE_ITEM(S3C64XX_GPPPUD), ++ SAVE_ITEM(S3C64XX_GPQCON), ++ SAVE_ITEM(S3C64XX_GPQDAT), ++ SAVE_ITEM(S3C64XX_GPQPUD), ++ SAVE_ITEM(S3C64XX_PRIORITY), ++ ++ /* Special register */ ++ SAVE_ITEM(S3C64XX_SPC_BASE), ++ SAVE_ITEM(S3C64XX_MEM0CONSTOP), ++ SAVE_ITEM(S3C64XX_MEM1CONSTOP), ++ SAVE_ITEM(S3C64XX_MEM0CONSLP0), ++ SAVE_ITEM(S3C64XX_MEM0CONSLP1), ++ SAVE_ITEM(S3C64XX_MEM1CONSLP), ++ SAVE_ITEM(S3C64XX_MEM0DRVCON), ++ SAVE_ITEM(S3C64XX_MEM1DRVCON), ++}; ++ ++/* this lot should be really saved by the IRQ code */ ++/* VICXADDRESSXX initilaization to be needed */ ++static struct sleep_save irq_save[] = { ++ SAVE_ITEM(S3C64XX_VIC0INTSELECT), ++ SAVE_ITEM(S3C64XX_VIC1INTSELECT), ++ SAVE_ITEM(S3C64XX_VIC0INTENABLE), ++ SAVE_ITEM(S3C64XX_VIC1INTENABLE), ++ SAVE_ITEM(S3C64XX_VIC0SOFTINT), ++ SAVE_ITEM(S3C64XX_VIC1SOFTINT), ++}; ++ ++static struct sleep_save sromc_save[] = { ++ SAVE_ITEM(S3C64XX_SROM_BW), ++ SAVE_ITEM(S3C64XX_SROM_BC0), ++ SAVE_ITEM(S3C64XX_SROM_BC1), ++ SAVE_ITEM(S3C64XX_SROM_BC2), ++ SAVE_ITEM(S3C64XX_SROM_BC3), ++ SAVE_ITEM(S3C64XX_SROM_BC4), ++ SAVE_ITEM(S3C64XX_SROM_BC5), ++}; ++ ++#ifdef CONFIG_S3C2410_PM_DEBUG ++ ++#define SAVE_UART(va) \ ++ SAVE_ITEM((va) + S3C2410_ULCON), \ ++ SAVE_ITEM((va) + S3C2410_UCON), \ ++ SAVE_ITEM((va) + S3C2410_UFCON), \ ++ SAVE_ITEM((va) + S3C2410_UMCON), \ ++ SAVE_ITEM((va) + S3C2410_UBRDIV) ++ ++static struct sleep_save uart_save[] = { ++ SAVE_UART(S3C24XX_VA_UART0), ++ SAVE_UART(S3C24XX_VA_UART1), ++#ifndef CONFIG_CPU_S3C2400 ++ SAVE_UART(S3C24XX_VA_UART2), ++#endif ++}; ++ ++/* debug ++ * ++ * we send the debug to printascii() to allow it to be seen if the ++ * system never wakes up from the sleep ++*/ ++ ++extern void printascii(const char *); ++ ++void pm_dbg(const char *fmt, ...) ++{ ++ va_list va; ++ char buff[256]; ++ ++ va_start(va, fmt); ++ vsprintf(buff, fmt, va); ++ va_end(va); ++ ++ printascii(buff); ++} ++ ++static void s3c2410_pm_debug_init(void) ++{ ++ unsigned long tmp = __raw_readl(S3C2410_CLKCON); ++ ++ /* re-start uart clocks */ ++ tmp |= S3C2410_CLKCON_UART0; ++ tmp |= S3C2410_CLKCON_UART1; ++ tmp |= S3C2410_CLKCON_UART2; ++ ++ __raw_writel(tmp, S3C2410_CLKCON); ++ udelay(10); ++} ++ ++#define DBG(fmt...) pm_dbg(fmt) ++#else ++#define DBG(fmt...) ++ ++#define s3c6410_pm_debug_init() do { } while(0) ++#endif ++ ++#if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0 ++ ++/* suspend checking code... ++ * ++ * this next area does a set of crc checks over all the installed ++ * memory, so the system can verify if the resume was ok. ++ * ++ * CONFIG_S3C6410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC, ++ * increasing it will mean that the area corrupted will be less easy to spot, ++ * and reducing the size will cause the CRC save area to grow ++*/ ++ ++#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024) ++ ++static u32 crc_size; /* size needed for the crc block */ ++static u32 *crcs; /* allocated over suspend/resume */ ++ ++typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg); ++ ++/* s3c6410_pm_run_res ++ * ++ * go thorugh the given resource list, and look for system ram ++*/ ++ ++static void s3c6410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg) ++{ ++ while (ptr != NULL) { ++ if (ptr->child != NULL) ++ s3c6410_pm_run_res(ptr->child, fn, arg); ++ ++ if ((ptr->flags & IORESOURCE_MEM) && ++ strcmp(ptr->name, "System RAM") == 0) { ++ DBG("Found system RAM at %08lx..%08lx\n", ++ ptr->start, ptr->end); ++ arg = (fn)(ptr, arg); ++ } ++ ++ ptr = ptr->sibling; ++ } ++} ++ ++static void s3c6410_pm_run_sysram(run_fn_t fn, u32 *arg) ++{ ++ s3c6410_pm_run_res(&iomem_resource, fn, arg); ++} ++ ++static u32 *s3c6410_pm_countram(struct resource *res, u32 *val) ++{ ++ u32 size = (u32)(res->end - res->start)+1; ++ ++ size += CHECK_CHUNKSIZE-1; ++ size /= CHECK_CHUNKSIZE; ++ ++ DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size); ++ ++ *val += size * sizeof(u32); ++ return val; ++} ++ ++/* s3c6410_pm_prepare_check ++ * ++ * prepare the necessary information for creating the CRCs. This ++ * must be done before the final save, as it will require memory ++ * allocating, and thus touching bits of the kernel we do not ++ * know about. ++*/ ++ ++static void s3c6410_pm_check_prepare(void) ++{ ++ crc_size = 0; ++ ++ s3c6410_pm_run_sysram(s3c6410_pm_countram, &crc_size); ++ ++ DBG("s3c6410_pm_prepare_check: %u checks needed\n", crc_size); ++ ++ crcs = kmalloc(crc_size+4, GFP_KERNEL); ++ if (crcs == NULL) ++ printk(KERN_ERR "Cannot allocated CRC save area\n"); ++} ++ ++static u32 *s3c6410_pm_makecheck(struct resource *res, u32 *val) ++{ ++ unsigned long addr, left; ++ ++ for (addr = res->start; addr < res->end; ++ addr += CHECK_CHUNKSIZE) { ++ left = res->end - addr; ++ ++ if (left > CHECK_CHUNKSIZE) ++ left = CHECK_CHUNKSIZE; ++ ++ *val = crc32_le(~0, phys_to_virt(addr), left); ++ val++; ++ } ++ ++ return val; ++} ++ ++/* s3c6410_pm_check_store ++ * ++ * compute the CRC values for the memory blocks before the final ++ * sleep. ++*/ ++ ++static void s3c6410_pm_check_store(void) ++{ ++ if (crcs != NULL) ++ s3c6410_pm_run_sysram(s3c6410_pm_makecheck, crcs); ++} ++ ++/* in_region ++ * ++ * return TRUE if the area defined by ptr..ptr+size contatins the ++ * what..what+whatsz ++*/ ++ ++static inline int in_region(void *ptr, int size, void *what, size_t whatsz) ++{ ++ if ((what+whatsz) < ptr) ++ return 0; ++ ++ if (what > (ptr+size)) ++ return 0; ++ ++ return 1; ++} ++ ++static u32 *s3c6410_pm_runcheck(struct resource *res, u32 *val) ++{ ++ void *save_at = phys_to_virt(s3c6410_sleep_save_phys); ++ unsigned long addr; ++ unsigned long left; ++ void *ptr; ++ u32 calc; ++ ++ for (addr = res->start; addr < res->end; ++ addr += CHECK_CHUNKSIZE) { ++ left = res->end - addr; ++ ++ if (left > CHECK_CHUNKSIZE) ++ left = CHECK_CHUNKSIZE; ++ ++ ptr = phys_to_virt(addr); ++ ++ if (in_region(ptr, left, crcs, crc_size)) { ++ DBG("skipping %08lx, has crc block in\n", addr); ++ goto skip_check; ++ } ++ ++ if (in_region(ptr, left, save_at, 32*4 )) { ++ DBG("skipping %08lx, has save block in\n", addr); ++ goto skip_check; ++ } ++ ++ /* calculate and check the checksum */ ++ ++ calc = crc32_le(~0, ptr, left); ++ if (calc != *val) { ++ printk(KERN_ERR PFX "Restore CRC error at " ++ "%08lx (%08x vs %08x)\n", addr, calc, *val); ++ ++ DBG("Restore CRC error at %08lx (%08x vs %08x)\n", ++ addr, calc, *val); ++ } ++ ++ skip_check: ++ val++; ++ } ++ ++ return val; ++} ++ ++/* s3c6410_pm_check_restore ++ * ++ * check the CRCs after the restore event and free the memory used ++ * to hold them ++*/ ++ ++static void s3c6410_pm_check_restore(void) ++{ ++ if (crcs != NULL) { ++ s3c6410_pm_run_sysram(s3c6410_pm_runcheck, crcs); ++ kfree(crcs); ++ crcs = NULL; ++ } ++} ++ ++#else ++ ++#define s3c6410_pm_check_prepare() do { } while(0) ++#define s3c6410_pm_check_restore() do { } while(0) ++#define s3c6410_pm_check_store() do { } while(0) ++#endif ++ ++/* helper functions to save and restore register state */ ++ ++void s3c6410_pm_do_save(struct sleep_save *ptr, int count) ++{ ++ for (; count > 0; count--, ptr++) { ++ ptr->val = __raw_readl(ptr->reg); ++ //DBG("saved %p value %08lx\n", ptr->reg, ptr->val); ++ } ++} ++ ++/* s3c6410_pm_do_restore ++ * ++ * restore the system from the given list of saved registers ++ * ++ * Note, we do not use DBG() in here, as the system may not have ++ * restore the UARTs state yet ++*/ ++ ++void s3c6410_pm_do_restore(struct sleep_save *ptr, int count) ++{ ++ for (; count > 0; count--, ptr++) { ++ //printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n", ++ //ptr->reg, ptr->val, __raw_readl(ptr->reg)); ++ ++ __raw_writel(ptr->val, ptr->reg); ++ } ++} ++ ++/* s3c6410_pm_do_restore_core ++ * ++ * similar to s36410_pm_do_restore_core ++ * ++ * WARNING: Do not put any debug in here that may effect memory or use ++ * peripherals, as things may be changing! ++*/ ++ ++/* s3c6410_pm_do_save_phy ++ * ++ * save register of system ++ * ++ * Note, I made this function to support driver with ioremap. ++ * If you want to use this function, you should to input as first parameter ++ * struct sleep_save_phy type ++*/ ++ ++int s3c2410_pm_do_save_phy(struct sleep_save_phy *ptr, struct platform_device *pdev, int count) ++{ ++ void __iomem *target_reg; ++ struct resource *res; ++ u32 reg_size; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if(res == NULL){ ++ printk(KERN_ERR "%s resource get error\n",__FUNCTION__); ++ return 0; ++ } ++ reg_size = res->end - res->start + 1; ++ target_reg = ioremap(res->start,reg_size); ++ ++ for (; count > 0; count--, ptr++) { ++ ptr->val = readl(target_reg + (ptr->reg)); ++ } ++ ++ return 0; ++} ++ ++/* s3c6410_pm_do_restore_phy ++ * ++ * restore register of system ++ * ++ * Note, I made this function to support driver with ioremap. ++ * If you want to use this function, you should to input as first parameter ++ * struct sleep_save_phy type ++*/ ++ ++int s3c2410_pm_do_restore_phy(struct sleep_save_phy *ptr, struct platform_device *pdev, int count) ++{ ++ void __iomem *target_reg; ++ struct resource *res; ++ u32 reg_size; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if(res == NULL){ ++ printk(KERN_ERR "%s resource get error\n",__FUNCTION__); ++ return 0; ++ } ++ reg_size = res->end - res->start + 1; ++ target_reg = ioremap(res->start,reg_size); ++ ++ for (; count > 0; count--, ptr++) { ++ writel(ptr->val, (target_reg + ptr->reg)); ++ } ++ ++ return 0; ++} ++ ++static void s3c6410_pm_do_restore_core(struct sleep_save *ptr, int count) ++{ ++ for (; count > 0; count--, ptr++) { ++ __raw_writel(ptr->val, ptr->reg); ++ } ++} ++ ++static void s3c6410_pm_configure_extint(void) ++{ ++ ++ /* for each of the external interrupts (EINT0..EINT15) we ++ * need to check wether it is an external interrupt source, ++ * and then configure it as an input if it is not ++ */ ++ ++ ++ ++ ++ ++ ++ s3c_gpio_cfgpin(S3C64XX_GPN(10), S3C64XX_GPN10_EINT10); ++ s3c_gpio_setpull(S3C64XX_GPN(10), S3C_GPIO_PULL_UP); ++ udelay(50); ++ ++ ++ ++ __raw_writel((__raw_readl(S3C64XX_EINT0CON0) & ~(0x7 << 20)) | ++ (S3C64XX_EXTINT_FALLEDGE << 20), S3C64XX_EINT0CON0); ++ ++ __raw_writel(1UL << (IRQ_EINT(10) - IRQ_EINT(0)), S3C64XX_EINT0PEND); ++ __raw_writel(__raw_readl(S3C64XX_EINT0MASK)&~(1UL << (IRQ_EINT(10) - IRQ_EINT(0))), S3C64XX_EINT0MASK); ++ ++ __raw_writel((0x0fffffff&~(3<<9)), S3C_EINT_MASK); ++} ++ ++void (*pm_cpu_prep)(void); ++void (*pm_cpu_sleep)(void); ++ ++#define any_allowed(mask, allow) (((mask) & (allow)) != (allow)) ++ ++/* s3c6410_pm_enter ++ * ++ * central control for sleep/resume process ++*/ ++ ++static int s3c6410_pm_enter(suspend_state_t state) ++{ ++ unsigned long regs_save[16]; ++ unsigned int tmp; ++ ++ /* ensure the debug is initialised (if enabled) */ ++ ++ DBG("s3c6410_pm_enter(%d)\n", state); ++ ++ if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) { ++ printk(KERN_ERR PFX "error: no cpu sleep functions set\n"); ++ return -EINVAL; ++ } ++ ++ /* prepare check area if configured */ ++ s3c6410_pm_check_prepare(); ++ ++ /* store the physical address of the register recovery block */ ++ s3c6410_sleep_save_phys = virt_to_phys(regs_save); ++ ++ printk("s3c6410_sleep_save_phys=0x%08lx\n", s3c6410_sleep_save_phys); ++ ++ /* save all necessary core registers not covered by the drivers */ ++ ++ s3c6410_pm_do_save(gpio_save, ARRAY_SIZE(gpio_save)); ++ s3c6410_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); ++ s3c6410_pm_do_save(core_save, ARRAY_SIZE(core_save)); ++ s3c6410_pm_do_save(sromc_save, ARRAY_SIZE(sromc_save)); ++ ++ /* ensure INF_REG0 has the resume address */ ++ __raw_writel(virt_to_phys(s3c6410_cpu_resume), S3C_INFORM0); ++ ++ /* set the irq configuration for wake */ ++ s3c6410_pm_configure_extint(); ++ ++ /* call cpu specific preperation */ ++ ++ pm_cpu_prep(); ++ ++ /* flush cache back to ram */ ++ ++ flush_cache_all(); ++ ++ s3c6410_pm_check_store(); ++ ++ /* send the cpu to sleep... */ ++ ++ __raw_writel(0xffffffff, S3C64XX_VIC0INTENCLEAR); ++ __raw_writel(0xffffffff, S3C64XX_VIC1INTENCLEAR); ++ __raw_writel(0xffffffff, S3C64XX_VIC0SOFTINTCLEAR); ++ __raw_writel(0xffffffff, S3C64XX_VIC1SOFTINTCLEAR); ++ ++ __raw_writel(1, S3C_OSC_STABLE); ++ __raw_writel(1, S3C_PWR_STABLE); ++ ++ /* Set WFI instruction to SLEEP mode */ ++ ++ tmp = __raw_readl(S3C_PWR_CFG); ++ tmp &= ~(0x60<<0); ++ tmp |= (0x3<<5); ++ __raw_writel(tmp, S3C_PWR_CFG); ++ ++ tmp = __raw_readl(S3C_SLEEP_CFG); ++ tmp &= ~(0x61<<0); ++ __raw_writel(tmp, S3C_SLEEP_CFG); ++ ++ /* Clear WAKEUP_STAT register for next wakeup -jc.lee */ ++ /* If this register do not be cleared, Wakeup will be failed */ ++ tmp = __raw_readl(S3C_WAKEUP_STAT); ++ __raw_writel(tmp, S3C_WAKEUP_STAT); ++ ++ /* ALL sub block "ON" before enterring sleep mode - EVT0 bug*/ ++ __raw_writel(0xffffff00, S3C_NORMAL_CFG); ++ ++ /* Open all clock gate to enter sleep mode - EVT0 bug*/ ++ __raw_writel(0xffffffff, S3C_HCLK_GATE); ++ __raw_writel(0xffffffff, S3C_PCLK_GATE); ++ __raw_writel(0xffffffff, S3C_SCLK_GATE); ++ ++ /* s3c6410_cpu_save will also act as our return point from when ++ * we resume as it saves its own register state, so use the return ++ * code to differentiate return from save and return from sleep */ ++ ++ if (s3c6410_cpu_save(regs_save) == 0) { ++ flush_cache_all(); ++ pm_cpu_sleep(); ++ } ++ ++ /* restore the cpu state */ ++ cpu_init(); ++ ++ /* restore the system state */ ++ s3c6410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); ++ s3c6410_pm_do_restore(sromc_save, ARRAY_SIZE(sromc_save)); ++ s3c6410_pm_do_restore(gpio_save, ARRAY_SIZE(gpio_save)); ++ s3c6410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); ++ ++ tmp = __raw_readl(S3C64XX_EINT0PEND); ++ __raw_writel(tmp, S3C64XX_EINT0PEND); ++ ++ DBG("post sleep, preparing to return\n"); ++ ++ s3c6410_pm_check_restore(); ++ ++ /* ok, let's return from sleep */ ++ DBG("S3C6410 PM Resume (post-restore)\n"); ++ return 0; ++} ++ ++static struct platform_suspend_ops s3c6410_pm_ops = { ++ .enter = s3c6410_pm_enter, ++ .valid = suspend_valid_only_mem, ++}; ++ ++/* s3c6410_pm_init ++ * ++ * Attach the power management functions. This should be called ++ * from the board specific initialisation if the board supports ++ * it. ++*/ ++ ++int __init s3c6410_pm_init(void) ++{ ++ printk("S3C6410 Power Management, (c) 2008 Samsung Electronics\n"); ++ ++ suspend_set_ops(&s3c6410_pm_ops); ++ return 0; ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/pwm-s3c6410.c linux-2.6.28.6/arch/arm/plat-s3c64xx/pwm-s3c6410.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/pwm-s3c6410.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/pwm-s3c6410.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,375 @@ ++/* arch/arm/plat-s3c64xx/pwm-s3c6410.c ++ * ++ * (c) 2003-2005 Simtec Electronics ++ * Ben Dooks ++ * ++ * S3C6410 PWM core ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * Changelog: ++ * This file is based on the Sangwook Lee/Samsung patches, re-written due ++ * to various ommisions from the code (such as flexible pwm configuration) ++ * for use with the BAST system board. ++ * ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "pwm-s3c6410.h" ++ ++s3c6410_pwm_chan_t s3c_chans[S3C_PWM_CHANNELS]; ++ ++static inline void ++s3c6410_pwm_buffdone(s3c6410_pwm_chan_t *chan, void *dev) ++{ ++ ++ if (chan->callback_fn != NULL) { ++ (chan->callback_fn)( dev); ++ } ++} ++ ++ ++static int s3c6410_pwm_start (int channel) ++{ ++ unsigned long tcon; ++ tcon = __raw_readl(S3C_TCON); ++ switch(channel) ++ { ++ case 0: ++ tcon |= S3C_TCON_T0START; ++ tcon &= ~S3C_TCON_T0MANUALUPD; ++ break; ++ case 1: ++ tcon |= S3C_TCON_T1START; ++ tcon &= ~S3C_TCON_T1MANUALUPD; ++ break; ++ case 2: ++ tcon |= S3C_TCON_T2START; ++ tcon &= ~S3C_TCON_T2MANUALUPD; ++ break; ++ case 3: ++ tcon |= S3C_TCON_T3START; ++ tcon &= ~S3C_TCON_T3MANUALUPD; ++ break; ++ case 4: ++ tcon |= S3C_TCON_T4START; ++ tcon &= ~S3C_TCON_T4MANUALUPD; ++ break; ++ } ++ __raw_writel(tcon, S3C_TCON); ++ ++ return 0; ++} ++ ++ ++int s3c6410_timer_setup (int channel, int usec, unsigned long g_tcnt, unsigned long g_tcmp) ++{ ++ unsigned long tcon; ++ unsigned long tcnt; ++ unsigned long tcmp; ++ unsigned long tcfg1; ++ unsigned long tcfg0; ++ unsigned long pclk; ++ struct clk *clk; ++ ++ printk("\nPWM channel %d set g_tcnt = %ld, g_tcmp = %ld \n", channel, g_tcnt, g_tcmp); ++ ++ tcnt = 0xffffffff; /* default value for tcnt */ ++ ++ /* read the current timer configuration bits */ ++ tcon = __raw_readl(S3C_TCON); ++ tcfg1 = __raw_readl(S3C_TCFG1); ++ tcfg0 = __raw_readl(S3C_TCFG0); ++ ++ clk = clk_get(NULL, "timers"); ++ if (IS_ERR(clk)) ++ panic("failed to get clock for pwm timer"); ++ ++ clk_enable(clk); ++ ++ pclk = clk_get_rate(clk); ++ ++ /* configure clock tick */ ++ switch(channel) ++ { ++ case 0: ++ /* set gpio as PWM TIMER0 to signal output*/ ++ s3c_gpio_cfgpin(S3C64XX_GPF(14),S3C64XX_GPF14_PWM_TOUT0); ++ ++ tcfg1 &= ~S3C_TCFG1_MUX0_MASK; ++ tcfg1 |= S3C_TCFG1_MUX1_DIV2; ++ ++ tcfg0 &= ~S3C_TCFG_PRESCALER0_MASK; ++ tcfg0 |= (PRESCALER) << S3C_TCFG_PRESCALER0_SHIFT; ++ tcon &= ~(7<<0); ++ tcon |= S3C_TCON_T0RELOAD; ++ break; ++ ++ case 1: ++ /* set gpio as PWM TIMER1 to signal output*/ ++ s3c_gpio_cfgpin(S3C64XX_GPF(15),S3C64XX_GPF15_PWM_TOUT1); ++ ++ tcfg1 &= ~S3C_TCFG1_MUX1_MASK; ++ tcfg1 |= S3C_TCFG1_MUX1_DIV2; ++ ++ tcfg0 &= ~S3C_TCFG_PRESCALER0_MASK; ++ tcfg0 |= (PRESCALER) << S3C_TCFG_PRESCALER0_SHIFT; ++ ++ tcon &= ~(7<<8); ++ tcon |= S3C_TCON_T1RELOAD; ++ break; ++ case 2: ++ tcfg1 &= ~S3C_TCFG1_MUX2_MASK; ++ tcfg1 |= S3C_TCFG1_MUX2_DIV2; ++ ++ tcfg0 &= ~S3C_TCFG_PRESCALER1_MASK; ++ tcfg0 |= (PRESCALER) << S3C_TCFG_PRESCALER1_SHIFT; ++ ++ tcon &= ~(7<<12); ++ tcon |= S3C_TCON_T2RELOAD; ++ break; ++ case 3: ++ tcfg1 &= ~S3C_TCFG1_MUX3_MASK; ++ tcfg1 |= S3C_TCFG1_MUX3_DIV2; ++ ++ tcfg0 &= ~S3C_TCFG_PRESCALER1_MASK; ++ tcfg0 |= (PRESCALER) << S3C_TCFG_PRESCALER1_SHIFT; ++ tcon &= ~(7<<16); ++ tcon |= S3C_TCON_T3RELOAD; ++ break; ++ case 4: ++ tcfg1 &= ~S3C_TCFG1_MUX4_MASK; ++ tcfg1 |= S3C_TCFG1_MUX4_DIV2; ++ ++ tcfg0 &= ~S3C_TCFG_PRESCALER1_MASK; ++ tcfg0 |= (PRESCALER) << S3C_TCFG_PRESCALER1_SHIFT; ++ tcon &= ~(7<<20); ++ tcon |= S3C_TCON_T3RELOAD; ++ break; ++ } ++ ++ __raw_writel(tcfg1, S3C_TCFG1); ++ __raw_writel(tcfg0, S3C_TCFG0); ++ ++ ++ __raw_writel(tcon, S3C_TCON); ++ ++ /*tcnt = 160; ++ __raw_writel(tcnt, S3C_TCNTB(channel)); ++ tcmp = 110; ++ __raw_writel(tcmp, S3C_TCMPB(channel));*/ ++ ++ switch(channel) ++ { ++ case 0: ++ tcon |= S3C_TCON_T0MANUALUPD; ++ break; ++ case 1: ++ tcon |= S3C_TCON_T1MANUALUPD; ++ break; ++ case 2: ++ tcon |= S3C_TCON_T2MANUALUPD; ++ break; ++ case 3: ++ tcon |= S3C_TCON_T3MANUALUPD; ++ break; ++ case 4: ++ tcon |= S3C_TCON_T4MANUALUPD; ++ break; ++ } ++ __raw_writel(tcon, S3C_TCON); ++ ++ tcnt = g_tcnt; ++ __raw_writel(tcnt, S3C_TCNTB(channel)); ++ ++ tcmp = g_tcmp; ++ __raw_writel(tcmp, S3C_TCMPB(channel)); ++ ++ /* start the timer running */ ++ s3c6410_pwm_start ( channel); ++ ++ return 0; ++} ++ ++ ++static irqreturn_t s3c6410_pwm_irq(int irq, void *devpw) ++{ ++ s3c6410_pwm_chan_t *chan = (s3c6410_pwm_chan_t *)devpw; ++ void *dev=chan->dev; ++ ++ /* modify the channel state */ ++ s3c6410_pwm_buffdone(chan, dev); ++ ++ return IRQ_HANDLED; ++} ++ ++ ++int s3c6410_pwm_request(pwmch_t channel, s3c_pwm_client_t *client, void *dev) ++{ ++ s3c6410_pwm_chan_t *chan = &s3c_chans[channel]; ++ unsigned long flags; ++ int err; ++ ++ pr_debug("pwm%d: s3c_request_pwm: client=%s, dev=%p\n", ++ channel, client->name, dev); ++ ++ ++ local_irq_save(flags); ++ ++ ++ if (chan->in_use) { ++ if (client != chan->client) { ++ printk(KERN_ERR "pwm%d: already in use\n", channel); ++ local_irq_restore(flags); ++ return -EBUSY; ++ } else { ++ printk(KERN_ERR "pwm%d: client already has channel\n", channel); ++ } ++ } ++ ++ chan->client = client; ++ chan->in_use = 1; ++ chan->dev = dev; ++ ++ if (!chan->irq_claimed) { ++ pr_debug("pwm%d: %s : requesting irq %d\n", ++ channel, __FUNCTION__, chan->irq); ++ ++ err = request_irq(chan->irq, s3c6410_pwm_irq, IRQF_DISABLED, ++ client->name, (void *)chan); ++ ++ if (err) { ++ chan->in_use = 0; ++ local_irq_restore(flags); ++ ++ printk(KERN_ERR "%s: cannot get IRQ %d for PWM %d\n", ++ client->name, chan->irq, chan->number); ++ return err; ++ } ++ ++ chan->irq_claimed = 1; ++ chan->irq_enabled = 1; ++ } ++ ++ local_irq_restore(flags); ++ ++ /* need to setup */ ++ ++ pr_debug("%s: channel initialised, %p\n", __FUNCTION__, chan); ++ ++ return 0; ++} ++ ++int s3c6410_pwm_free (pwmch_t channel, s3c_pwm_client_t *client) ++{ ++ s3c6410_pwm_chan_t *chan = &s3c_chans[channel]; ++ unsigned long flags; ++ ++ ++ local_irq_save(flags); ++ ++ if (chan->client != client) { ++ printk(KERN_WARNING "pwm%d: possible free from different client (channel %p, passed %p)\n", ++ channel, chan->client, client); ++ } ++ ++ /* sort out stopping and freeing the channel */ ++ ++ ++ chan->client = NULL; ++ chan->in_use = 0; ++ ++ if (chan->irq_claimed) ++ free_irq(chan->irq, (void *)chan); ++ chan->irq_claimed = 0; ++ ++ local_irq_restore(flags); ++ ++ return 0; ++} ++ ++ ++int s3c6410_pwm_set_buffdone_fn(pwmch_t channel, s3c_pwm_cbfn_t rtn) ++{ ++ s3c6410_pwm_chan_t *chan = &s3c_chans[channel]; ++ ++ ++ pr_debug("%s: chan=%d, callback rtn=%p\n", __FUNCTION__, channel, rtn); ++ ++ chan->callback_fn = rtn; ++ ++ return 0; ++} ++ ++ ++#define s3c6410_pwm_suspend NULL ++#define s3c6410_pwm_resume NULL ++ ++struct sysdev_class pwm_sysclass = { ++ .name = "s3c-pwm", ++ .suspend = s3c6410_pwm_suspend, ++ .resume = s3c6410_pwm_resume, ++}; ++ ++ ++/* initialisation code */ ++ ++static int __init s3c6410_init_pwm(void) ++{ ++ s3c6410_pwm_chan_t *cp; ++ int channel; ++ int ret; ++ ++ printk("S3C PWM Driver, (c) 2006-2007 Samsung Electronics\n"); ++ ++ ret = sysdev_class_register(&pwm_sysclass); ++ if (ret != 0) { ++ printk(KERN_ERR "pwm sysclass registration failed\n"); ++ return -ENODEV; ++ } ++ ++ for (channel = 0; channel < S3C_PWM_CHANNELS; channel++) { ++ cp = &s3c_chans[channel]; ++ ++ memset(cp, 0, sizeof(s3c6410_pwm_chan_t)); ++ ++ cp->number = channel; ++ /* pwm channel irqs are in order.. */ ++ cp->irq = channel + IRQ_TIMER0; ++ ++ /* register system device */ ++ ++ ret = sysdev_register(&cp->sysdev); ++ ++ pr_debug("PWM channel %d , irq %d\n", ++ cp->number, cp->irq); ++ } ++ ++ return ret; ++} ++__initcall(s3c6410_init_pwm); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/pwm-s3c6410.h linux-2.6.28.6/arch/arm/plat-s3c64xx/pwm-s3c6410.h +--- linux-2.6.28/arch/arm/plat-s3c64xx/pwm-s3c6410.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/pwm-s3c6410.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,78 @@ ++/* arch/arm/plat-s3c64xx/pwm-s3c6410.h ++ * ++ * Copyright (C) 2003,2004 Simtec Electronics ++ * Ben Dooks ++ * ++ * Samsung S3C PWM support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * Changelog: ++ * ??-May-2003 BJD Created file ++ * ??-Jun-2003 BJD Added more dma functionality to go with arch ++ * 10-Nov-2004 BJD Added sys_device support ++*/ ++ ++#ifndef __ASM_ARCH_DMA_H ++#define __ASM_ARCH_DMA_H __FILE__ ++ ++#include ++#include ++ ++ ++#define pwmch_t int ++ ++/* we have 4 pwm channels */ ++#define S3C_PWM_CHANNELS 5 ++#define PRESCALER ((4-1)/2) ++ ++struct s3c_pwm_client { ++ char *name; ++}; ++ ++typedef struct s3c_pwm_client s3c_pwm_client_t; ++ ++ ++typedef struct s3c_pwm_chan_s s3c6410_pwm_chan_t; ++ ++/* s3c_pwm_cbfn_t ++ * ++ * buffer callback routine type ++*/ ++ ++typedef void (*s3c_pwm_cbfn_t)(void *buf); ++ ++ ++ ++/* struct s3c_pwm_chan_s ++ * ++ * full state information for each DMA channel ++*/ ++ ++struct s3c_pwm_chan_s { ++ /* channel state flags and information */ ++ unsigned char number; /* number of this dma channel */ ++ unsigned char in_use; /* channel allocated */ ++ unsigned char irq_claimed; /* irq claimed for channel */ ++ unsigned char irq_enabled; /* irq enabled for channel */ ++ ++ /* channel state */ ++ ++ s3c_pwm_client_t *client; ++ void *dev; ++ /* channel configuration */ ++ unsigned int flags; /* channel flags */ ++ ++ /* channel's hardware position and configuration */ ++ unsigned int irq; /* channel irq */ ++ ++ /* driver handles */ ++ s3c_pwm_cbfn_t callback_fn; /* buffer done callback */ ++ ++ /* system device */ ++ struct sys_device sysdev; ++}; ++ ++#endif /* __ASM_ARCH_DMA_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/pwm.c linux-2.6.28.6/arch/arm/plat-s3c64xx/pwm.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/pwm.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/pwm.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,432 @@ ++/* arch/arm/plat-s3c24xx/pwm.c ++ * ++ * Copyright (c) 2007 Ben Dooks ++ * Copyright (c) 2008 Simtec Electronics ++ * Ben Dooks , ++ * ++ * S3C24XX PWM device core ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct pwm_device { ++ struct list_head list; ++ struct platform_device *pdev; ++ ++ struct clk *clk_div; ++ struct clk *clk; ++ const char *label; ++ ++ unsigned int period_ns; ++ unsigned int duty_ns; ++ ++ unsigned char tcon_base; ++ unsigned char running; ++ unsigned char use_count; ++ unsigned char pwm_id; ++}; ++ ++#define pwm_dbg(_pwm, msg...) dev_dbg(&(_pwm)->pdev->dev, msg) ++ ++static struct clk *clk_scaler[2]; ++ ++/* Standard setup for a timer block. */ ++ ++#define TIMER_RESOURCE_SIZE (1) ++ ++#define TIMER_RESOURCE(_tmr, _irq) \ ++ (struct resource [TIMER_RESOURCE_SIZE]) { \ ++ [0] = { \ ++ .start = _irq, \ ++ .end = _irq, \ ++ .flags = IORESOURCE_IRQ \ ++ } \ ++ } ++ ++#define DEFINE_S3C_TIMER(_tmr_no, _irq) \ ++ .name = "s3c24xx-pwm", \ ++ .id = _tmr_no, \ ++ .num_resources = TIMER_RESOURCE_SIZE, \ ++ .resource = TIMER_RESOURCE(_tmr_no, _irq), \ ++ ++/* since we already have an static mapping for the timer, we do not ++ * bother setting any IO resource for the base. ++ */ ++ ++struct platform_device s3c_device_timer[] = { ++ [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) }, ++ [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) }, ++ [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) }, ++ [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) }, ++ [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) }, ++}; ++ ++static inline int pwm_is_tdiv(struct pwm_device *pwm) ++{ ++ return clk_get_parent(pwm->clk) == pwm->clk_div; ++} ++ ++static DEFINE_MUTEX(pwm_lock); ++static LIST_HEAD(pwm_list); ++ ++struct pwm_device *pwm_request(int pwm_id, const char *label) ++{ ++ struct pwm_device *pwm; ++ int found = 0; ++ ++ mutex_lock(&pwm_lock); ++ ++ list_for_each_entry(pwm, &pwm_list, list) { ++ if (pwm->pwm_id == pwm_id) { ++ found = 1; ++ break; ++ } ++ } ++ ++ if (found) { ++ if (pwm->use_count == 0) { ++ pwm->use_count = 1; ++ pwm->label = label; ++ } else ++ pwm = ERR_PTR(-EBUSY); ++ } else ++ pwm = ERR_PTR(-ENOENT); ++ ++ mutex_unlock(&pwm_lock); ++ return pwm; ++} ++ ++EXPORT_SYMBOL(pwm_request); ++ ++ ++void pwm_free(struct pwm_device *pwm) ++{ ++ mutex_lock(&pwm_lock); ++ ++ if (pwm->use_count) { ++ pwm->use_count--; ++ pwm->label = NULL; ++ } else ++ printk(KERN_ERR "PWM%d device already freed\n", pwm->pwm_id); ++ ++ mutex_unlock(&pwm_lock); ++} ++ ++EXPORT_SYMBOL(pwm_free); ++ ++#define pwm_tcon_start(pwm) (1 << (pwm->tcon_base + 0)) ++#define pwm_tcon_invert(pwm) (1 << (pwm->tcon_base + 2)) ++#define pwm_tcon_autoreload(pwm) (1 << (pwm->tcon_base + 3)) ++#define pwm_tcon_manulupdate(pwm) (1 << (pwm->tcon_base + 1)) ++ ++int pwm_enable(struct pwm_device *pwm) ++{ ++ unsigned long flags; ++ unsigned long tcon; ++ ++ local_irq_save(flags); ++ ++ tcon = __raw_readl(S3C2410_TCON); ++ tcon |= pwm_tcon_start(pwm); ++ __raw_writel(tcon, S3C2410_TCON); ++ ++ local_irq_restore(flags); ++ ++ pwm->running = 1; ++ return 0; ++} ++ ++EXPORT_SYMBOL(pwm_enable); ++ ++void pwm_disable(struct pwm_device *pwm) ++{ ++ unsigned long flags; ++ unsigned long tcon; ++ ++ local_irq_save(flags); ++ ++ tcon = __raw_readl(S3C2410_TCON); ++ tcon &= ~pwm_tcon_start(pwm); ++ __raw_writel(tcon, S3C2410_TCON); ++ ++ local_irq_restore(flags); ++ ++ pwm->running = 0; ++} ++ ++EXPORT_SYMBOL(pwm_disable); ++ ++static unsigned long pwm_calc_tin(struct pwm_device *pwm, unsigned long freq) ++{ ++ unsigned long tin_parent_rate; ++ unsigned int div; ++ ++ tin_parent_rate = clk_get_rate(clk_get_parent(pwm->clk_div)); ++ pwm_dbg(pwm, "tin parent at %lu\n", tin_parent_rate); ++ ++ for (div = 2; div <= 16; div *= 2) { ++ if ((tin_parent_rate / (div << 16)) < freq) ++ return tin_parent_rate / div; ++ } ++ ++ return tin_parent_rate / 16; ++} ++ ++#define NS_IN_HZ (1000000000UL) ++ ++int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) ++{ ++ unsigned long tin_rate; ++ unsigned long tin_ns; ++ unsigned long period; ++ unsigned long flags; ++ unsigned long tcon; ++ unsigned long tcnt; ++ long tcmp; ++ ++ /* We currently avoid using 64bit arithmetic by using the ++ * fact that anything faster than 1Hz is easily representable ++ * by 32bits. */ ++ ++ if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ) ++ return -ERANGE; ++ ++ if (duty_ns > period_ns) ++ return -EINVAL; ++ ++ if (period_ns == pwm->period_ns && ++ duty_ns == pwm->duty_ns) ++ return 0; ++ ++ /* The TCMP and TCNT can be read without a lock, they're not ++ * shared between the timers. */ ++ ++ tcmp = __raw_readl(S3C2410_TCMPB(pwm->pwm_id)); ++ tcnt = __raw_readl(S3C2410_TCNTB(pwm->pwm_id)); ++ ++ period = NS_IN_HZ / period_ns; ++ ++ pwm_dbg(pwm, "duty_ns=%d, period_ns=%d (%lu)\n", ++ duty_ns, period_ns, period); ++ ++ /* Check to see if we are changing the clock rate of the PWM */ ++ ++ if (pwm->period_ns != period_ns) { ++ if (pwm_is_tdiv(pwm)) { ++ tin_rate = pwm_calc_tin(pwm, period); ++ clk_set_rate(pwm->clk_div, tin_rate); ++ } else ++ tin_rate = clk_get_rate(pwm->clk); ++ ++ pwm->period_ns = period_ns; ++ ++ pwm_dbg(pwm, "tin_rate=%lu\n", tin_rate); ++ ++ tin_ns = NS_IN_HZ / tin_rate; ++ tcnt = period_ns / tin_ns; ++ } else ++ tin_ns = NS_IN_HZ / clk_get_rate(pwm->clk); ++ ++ /* Note, counters count down */ ++ ++ tcmp = duty_ns / tin_ns; ++ tcmp = tcnt - tcmp; ++ ++ pwm_dbg(pwm, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt); ++ ++ if (tcmp < 0) ++ tcmp = 0; ++ ++ /* Update the PWM register block. */ ++ ++ local_irq_save(flags); ++ ++ __raw_writel(tcmp, S3C2410_TCMPB(pwm->pwm_id)); ++ __raw_writel(tcnt, S3C2410_TCNTB(pwm->pwm_id)); ++ ++ tcon = __raw_readl(S3C2410_TCON); ++ tcon |= pwm_tcon_manulupdate(pwm); ++ tcon |= pwm_tcon_autoreload(pwm); ++ __raw_writel(tcon, S3C2410_TCON); ++ ++ tcon &= ~pwm_tcon_manulupdate(pwm); ++ __raw_writel(tcon, S3C2410_TCON); ++ ++ local_irq_restore(flags); ++ ++ return 0; ++} ++ ++EXPORT_SYMBOL(pwm_config); ++ ++static int pwm_register(struct pwm_device *pwm) ++{ ++ pwm->duty_ns = -1; ++ pwm->period_ns = -1; ++ ++ mutex_lock(&pwm_lock); ++ list_add_tail(&pwm->list, &pwm_list); ++ mutex_unlock(&pwm_lock); ++ ++ return 0; ++} ++ ++static int s3c_pwm_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct pwm_device *pwm; ++ unsigned long flags; ++ unsigned long tcon; ++ unsigned int id = pdev->id; ++ int ret; ++ ++ if (id == 0) { ++ if(gpio_is_valid(S3C64XX_GPF(14))) { ++ ret = gpio_request(S3C64XX_GPF(14), "GPF"); ++ ++ if (ret) { ++ printk(KERN_ERR "failed to request GPF for PWM-OUT 0\n"); ++ } ++ s3c_gpio_cfgpin(S3C64XX_GPF(14),S3C64XX_GPF14_PWM_TOUT0); ++ } ++ } else if(id == 1) { ++ if(gpio_is_valid(S3C64XX_GPF(15))) { ++ ret = gpio_request(S3C64XX_GPF(15), "GPF"); ++ ++ if (ret) { ++ printk(KERN_ERR "failed to request GPF for PWM-OUT 1\n"); ++ } ++ s3c_gpio_cfgpin(S3C64XX_GPF(15),S3C64XX_GPF15_PWM_TOUT1); ++ } ++ ++ } else { ++ printk(KERN_ERR "This PWM dosen't support PWM out\n"); ++ } ++ ++ if (id == 4) { ++ dev_err(dev, "TIMER4 is currently not supported\n"); ++ return -ENXIO; ++ } ++ ++ pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); ++ if (pwm == NULL) { ++ dev_err(dev, "failed to allocate pwm_device\n"); ++ return -ENOMEM; ++ } ++ ++ pwm->pdev = pdev; ++ pwm->pwm_id = id; ++ ++ /* calculate base of control bits in TCON */ ++ pwm->tcon_base = id == 0 ? 0 : (id * 4) + 4; ++ ++ pwm->clk = clk_get(dev, "pwm-tin"); ++ if (IS_ERR(pwm->clk)) { ++ dev_err(dev, "failed to get pwm tin clk\n"); ++ ret = PTR_ERR(pwm->clk); ++ goto err_alloc; ++ } ++ ++ pwm->clk_div = clk_get(dev, "pwm-tdiv"); ++ if (IS_ERR(pwm->clk_div)) { ++ dev_err(dev, "failed to get pwm tdiv clk\n"); ++ ret = PTR_ERR(pwm->clk_div); ++ goto err_clk_tin; ++ } ++ ++ local_irq_save(flags); ++ ++ tcon = __raw_readl(S3C2410_TCON); ++ tcon |= pwm_tcon_invert(pwm); ++ __raw_writel(tcon, S3C2410_TCON); ++ ++ local_irq_restore(flags); ++ ++ ++ ret = pwm_register(pwm); ++ if (ret) { ++ dev_err(dev, "failed to register pwm\n"); ++ goto err_clk_tdiv; ++ } ++ ++ pwm_dbg(pwm, "config bits %02x\n", ++ (__raw_readl(S3C2410_TCON) >> pwm->tcon_base) & 0x0f); ++ ++ dev_info(dev, "tin at %lu, tdiv at %lu, tin=%sclk, base %d\n", ++ clk_get_rate(pwm->clk), ++ clk_get_rate(pwm->clk_div), ++ pwm_is_tdiv(pwm) ? "div" : "ext", pwm->tcon_base); ++ ++ platform_set_drvdata(pdev, pwm); ++ return 0; ++ ++ err_clk_tdiv: ++ clk_put(pwm->clk_div); ++ ++ err_clk_tin: ++ clk_put(pwm->clk); ++ ++ err_alloc: ++ kfree(pwm); ++ return ret; ++} ++ ++static int s3c_pwm_remove(struct platform_device *pdev) ++{ ++ struct pwm_device *pwm = platform_get_drvdata(pdev); ++ ++ clk_put(pwm->clk_div); ++ clk_put(pwm->clk); ++ kfree(pwm); ++ ++ return 0; ++} ++ ++static struct platform_driver s3c_pwm_driver = { ++ .driver = { ++ .name = "s3c24xx-pwm", ++ .owner = THIS_MODULE, ++ }, ++ .probe = s3c_pwm_probe, ++ .remove = __devexit_p(s3c_pwm_remove), ++}; ++ ++static int __init pwm_init(void) ++{ ++ int ret; ++ ++ clk_scaler[0] = clk_get(NULL, "pwm-scaler0"); ++ clk_scaler[1] = clk_get(NULL, "pwm-scaler1"); ++ ++ if (IS_ERR(clk_scaler[0]) || IS_ERR(clk_scaler[1])) { ++ printk(KERN_ERR "%s: failed to get scaler clocks\n", __func__); ++ return -EINVAL; ++ } ++ ++ ret = platform_driver_register(&s3c_pwm_driver); ++ if (ret) ++ printk(KERN_ERR "%s: failed to add pwm driver\n", __func__); ++ ++ return ret; ++} ++ ++arch_initcall(pwm_init); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/s3c6400-clock.c linux-2.6.28.6/arch/arm/plat-s3c64xx/s3c6400-clock.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/s3c6400-clock.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/s3c6400-clock.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,902 @@ ++/* linux/arch/arm/plat-s3c64xx/s3c6400-clock.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C6400 based common clock support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call ++ * ext_xtal_mux for want of an actual name from the manual. ++*/ ++ ++struct clk clk_ext_xtal_mux = { ++ .name = "ext_xtal", ++ .id = -1, ++}; ++ ++#define clk_fin_apll clk_ext_xtal_mux ++#define clk_fin_mpll clk_ext_xtal_mux ++#define clk_fin_epll clk_ext_xtal_mux ++ ++#define clk_fout_mpll clk_mpll ++ ++struct clk_sources { ++ unsigned int nr_sources; ++ struct clk **sources; ++}; ++ ++struct clksrc_clk { ++ struct clk clk; ++ unsigned int mask; ++ unsigned int shift; ++ ++ struct clk_sources *sources; ++ ++ unsigned int divider_shift; ++ void __iomem *reg_divider; ++}; ++ ++struct clk clk_fout_apll = { ++ .name = "fout_apll", ++ .id = -1, ++}; ++ ++static struct clk *clk_src_apll_list[] = { ++ [0] = &clk_fin_apll, ++ [1] = &clk_fout_apll, ++}; ++ ++static struct clk_sources clk_src_apll = { ++ .sources = clk_src_apll_list, ++ .nr_sources = ARRAY_SIZE(clk_src_apll_list), ++}; ++ ++struct clksrc_clk clk_mout_apll = { ++ .clk = { ++ .name = "mout_apll", ++ .id = -1, ++ }, ++ .shift = S3C6400_CLKSRC_APLL_MOUT_SHIFT, ++ .mask = S3C6400_CLKSRC_APLL_MOUT, ++ .sources = &clk_src_apll, ++}; ++ ++static inline struct clksrc_clk *to_clksrc(struct clk *clk) ++{ ++ return container_of(clk, struct clksrc_clk, clk); ++} ++ ++int fout_enable(struct clk *clk, int enable) ++{ ++ unsigned int ctrlbit = clk->ctrlbit; ++ unsigned int epll_con0 = __raw_readl(S3C_EPLL_CON0) & ~ ctrlbit; ++ ++ if(enable) ++ __raw_writel(epll_con0 | ctrlbit, S3C_EPLL_CON0); ++ else ++ __raw_writel(epll_con0, S3C_EPLL_CON0); ++ ++ return 0; ++} ++ ++unsigned long fout_get_rate(struct clk *clk) ++{ ++ return clk->rate; ++} ++ ++int fout_set_rate(struct clk *clk, unsigned long rate) ++{ ++ unsigned int epll_con0, epll_con1; ++ ++ if(clk->rate == rate) /* Return if nothing changed */ ++ return 0; ++ ++ epll_con0 = __raw_readl(S3C_EPLL_CON0); ++ epll_con1 = __raw_readl(S3C_EPLL_CON1); ++ ++ epll_con0 &= ~(S3C64XX_EPLL_CON0_M_MASK | S3C64XX_EPLL_CON0_P_MASK | S3C64XX_EPLL_CON0_S_MASK); ++ epll_con1 &= ~(S3C64XX_EPLL_CON1_K_MASK); ++ ++ switch (rate){ ++ case 36000000: ++ epll_con1 |= (0 << S3C64XX_EPLL_CON1_K_SHIFT); ++ epll_con0 |= (48 << S3C64XX_EPLL_CON0_M_SHIFT) | ++ (1 << S3C64XX_EPLL_CON0_P_SHIFT) | ++ (4 << S3C64XX_EPLL_CON0_S_SHIFT); ++ break; ++ case 48000000: ++ epll_con1 |= (0 << S3C64XX_EPLL_CON1_K_SHIFT); ++ epll_con0 |= (32 << S3C64XX_EPLL_CON0_M_SHIFT) | ++ (1 << S3C64XX_EPLL_CON0_P_SHIFT) | ++ (3 << S3C64XX_EPLL_CON0_S_SHIFT); ++ break; ++ case 60000000: ++ epll_con1 |= (0 << S3C64XX_EPLL_CON1_K_SHIFT); ++ epll_con0 |= (40 << S3C64XX_EPLL_CON0_M_SHIFT) | ++ (1 << S3C64XX_EPLL_CON0_P_SHIFT) | ++ (3 << S3C64XX_EPLL_CON0_S_SHIFT); ++ break; ++ case 72000000: ++ epll_con1 |= (0 << S3C64XX_EPLL_CON1_K_SHIFT); ++ epll_con0 |= (48 << S3C64XX_EPLL_CON0_M_SHIFT) | ++ (1 << S3C64XX_EPLL_CON0_P_SHIFT) | ++ (3 << S3C64XX_EPLL_CON0_S_SHIFT); ++ break; ++ case 84000000: ++ epll_con1 |= (0 << S3C64XX_EPLL_CON1_K_SHIFT); ++ epll_con0 |= (28 << S3C64XX_EPLL_CON0_M_SHIFT) | ++ (1 << S3C64XX_EPLL_CON0_P_SHIFT) | ++ (2 << S3C64XX_EPLL_CON0_S_SHIFT); ++ break; ++ case 96000000: ++ epll_con1 |= (0 << S3C64XX_EPLL_CON1_K_SHIFT); ++ epll_con0 |= (32 << S3C64XX_EPLL_CON0_M_SHIFT) | ++ (1 << S3C64XX_EPLL_CON0_P_SHIFT) | ++ (2 << S3C64XX_EPLL_CON0_S_SHIFT); ++ break; ++ case 32768000: ++ epll_con1 |= (45264 << S3C64XX_EPLL_CON1_K_SHIFT); ++ epll_con0 |= (43 << S3C64XX_EPLL_CON0_M_SHIFT) | ++ (1 << S3C64XX_EPLL_CON0_P_SHIFT) | ++ (4 << S3C64XX_EPLL_CON0_S_SHIFT); ++ break; ++ case 45158000: ++ epll_con1 |= (6903 << S3C64XX_EPLL_CON1_K_SHIFT); ++ epll_con0 |= (30 << S3C64XX_EPLL_CON0_M_SHIFT) | ++ (1 << S3C64XX_EPLL_CON0_P_SHIFT) | ++ (3 << S3C64XX_EPLL_CON0_S_SHIFT); ++ break; ++ case 49152000: ++ epll_con1 |= (50332 << S3C64XX_EPLL_CON1_K_SHIFT); ++ epll_con0 |= (32 << S3C64XX_EPLL_CON0_M_SHIFT) | ++ (1 << S3C64XX_EPLL_CON0_P_SHIFT) | ++ (3 << S3C64XX_EPLL_CON0_S_SHIFT); ++ break; ++ case 67738000: ++ epll_con1 |= (10398 << S3C64XX_EPLL_CON1_K_SHIFT); ++ epll_con0 |= (45 << S3C64XX_EPLL_CON0_M_SHIFT) | ++ (1 << S3C64XX_EPLL_CON0_P_SHIFT) | ++ (3 << S3C64XX_EPLL_CON0_S_SHIFT); ++ break; ++ case 73728000: ++ epll_con1 |= (9961 << S3C64XX_EPLL_CON1_K_SHIFT); ++ epll_con0 |= (49 << S3C64XX_EPLL_CON0_M_SHIFT) | ++ (1 << S3C64XX_EPLL_CON0_P_SHIFT) | ++ (3 << S3C64XX_EPLL_CON0_S_SHIFT); ++ break; ++ default: ++ printk(KERN_ERR "Invalid Clock Freq!\n"); ++ return -EINVAL; ++ } ++ ++ __raw_writel(epll_con0, S3C_EPLL_CON0); ++ __raw_writel(epll_con1, S3C_EPLL_CON1); ++ ++ clk->rate = rate; ++ ++ return 0; ++} ++ ++struct clk clk_fout_epll = { ++ .name = "fout_epll", ++ .id = -1, ++ .ctrlbit = (1<<31), ++ .enable = fout_enable, ++ .get_rate = fout_get_rate, ++ .set_rate = fout_set_rate, ++}; ++ ++int mout_set_parent(struct clk *clk, struct clk *parent) ++{ ++ int src_nr = -1; ++ int ptr; ++ u32 clksrc; ++ struct clksrc_clk *sclk = to_clksrc(clk); ++ struct clk_sources *srcs = sclk->sources; ++ ++ clksrc = __raw_readl(S3C_CLK_SRC); ++ ++ for (ptr = 0; ptr < srcs->nr_sources; ptr++) ++ if (srcs->sources[ptr] == parent) { ++ src_nr = ptr; ++ break; ++ } ++ ++ if (src_nr >= 0) { ++ clksrc &= ~sclk->mask; ++ clksrc |= src_nr << sclk->shift; ++ __raw_writel(clksrc, S3C_CLK_SRC); ++ clk->parent = parent; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static struct clk *clk_src_epll_list[] = { ++ [0] = &clk_fin_epll, ++ [1] = &clk_fout_epll, ++}; ++ ++static struct clk_sources clk_src_epll = { ++ .sources = clk_src_epll_list, ++ .nr_sources = ARRAY_SIZE(clk_src_epll_list), ++}; ++ ++struct clksrc_clk clk_mout_epll = { ++ .clk = { ++ .name = "mout_epll", ++ .id = -1, ++ .set_parent = mout_set_parent, ++ }, ++ .shift = S3C6400_CLKSRC_EPLL_MOUT_SHIFT, ++ .mask = S3C6400_CLKSRC_EPLL_MOUT, ++ .sources = &clk_src_epll, ++}; ++ ++static struct clk *clk_src_mpll_list[] = { ++ [0] = &clk_fin_mpll, ++ [1] = &clk_fout_mpll, ++}; ++ ++static struct clk_sources clk_src_mpll = { ++ .sources = clk_src_mpll_list, ++ .nr_sources = ARRAY_SIZE(clk_src_mpll_list), ++}; ++ ++struct clksrc_clk clk_mout_mpll = { ++ .clk = { ++ .name = "mout_mpll", ++ .id = -1, ++ }, ++ .shift = S3C6400_CLKSRC_MPLL_MOUT_SHIFT, ++ .mask = S3C6400_CLKSRC_MPLL_MOUT, ++ .sources = &clk_src_mpll, ++}; ++ ++static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk) ++{ ++ unsigned long rate = clk_get_rate(clk->parent); ++ ++ printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); ++ ++ if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK) ++ rate /= 2; ++ ++ return rate; ++} ++ ++struct clk clk_dout_mpll = { ++ .name = "dout_mpll", ++ .id = -1, ++ .parent = &clk_mout_mpll.clk, ++ .get_rate = s3c64xx_clk_doutmpll_get_rate, ++}; ++ ++static struct clk *clkset_spi_mmc_list[] = { ++ &clk_mout_epll.clk, ++ &clk_dout_mpll, ++ &clk_fin_epll, ++ &clk_27m, ++}; ++ ++static struct clk_sources clkset_spi_mmc = { ++ .sources = clkset_spi_mmc_list, ++ .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), ++}; ++ ++static struct clk *clkset_irda_list[] = { ++ &clk_mout_epll.clk, ++ &clk_dout_mpll, ++ NULL, ++ &clk_27m, ++}; ++ ++static struct clk_sources clkset_irda = { ++ .sources = clkset_irda_list, ++ .nr_sources = ARRAY_SIZE(clkset_irda_list), ++}; ++ ++static struct clk *clkset_uart_list[] = { ++ &clk_mout_epll.clk, ++ &clk_dout_mpll, ++ NULL, ++ NULL ++}; ++ ++static struct clk_sources clkset_uart = { ++ .sources = clkset_uart_list, ++ .nr_sources = ARRAY_SIZE(clkset_uart_list), ++}; ++ ++static struct clk *clkset_uhost_list[] = { ++ &clk_mout_epll.clk, ++ &clk_dout_mpll, ++ &clk_fin_epll, ++ &clk_48m, ++}; ++ ++static struct clk_sources clkset_uhost = { ++ .sources = clkset_uhost_list, ++ .nr_sources = ARRAY_SIZE(clkset_uhost_list), ++}; ++ ++ ++/* The peripheral clocks are all controlled via clocksource followed ++ * by an optional divider and gate stage. We currently roll this into ++ * one clock which hides the intermediate clock from the mux. ++ * ++ * Note, the JPEG clock can only be an even divider... ++ * ++ * The scaler and LCD clocks depend on the S3C64XX version, and also ++ * have a common parent divisor so are not included here. ++ */ ++ ++static unsigned long s3c64xx_getrate_clksrc(struct clk *clk) ++{ ++ struct clksrc_clk *sclk = to_clksrc(clk); ++ unsigned long rate = clk_get_rate(clk->parent); ++ u32 clkdiv = __raw_readl(sclk->reg_divider); ++ ++ clkdiv >>= sclk->divider_shift; ++ clkdiv &= 0xf; ++ clkdiv++; ++ ++ rate /= clkdiv; ++ return rate; ++} ++ ++static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate) ++{ ++ struct clksrc_clk *sclk = to_clksrc(clk); ++ void __iomem *reg = sclk->reg_divider; ++ unsigned int div; ++ u32 val; ++ ++ rate = clk_round_rate(clk, rate); ++ div = clk_get_rate(clk->parent) / rate; ++ ++ val = __raw_readl(reg); ++ val &= ~(0xf << sclk->divider_shift); ++ val |= ((div - 1) << sclk->divider_shift); ++ __raw_writel(val, reg); ++ ++ return 0; ++} ++ ++static struct clksrc_clk clk_audio2; ++ ++static int s3c64xx_setparent_clksrc(struct clk *clk, struct clk *parent) ++{ ++ int src_nr = -1; ++ int ptr; ++ u32 clksrc; ++ struct clksrc_clk *sclk = to_clksrc(clk); ++ struct clk_sources *srcs = sclk->sources; ++ ++#ifdef CONFIG_CPU_S3C6410 ++ if (sclk == &clk_audio2) ++ clksrc = __raw_readl(S3C_CLK_SRC2); ++ else ++#endif ++ clksrc = __raw_readl(S3C_CLK_SRC); ++ ++ for (ptr = 0; ptr < srcs->nr_sources; ptr++) ++ if (srcs->sources[ptr] == parent) { ++ src_nr = ptr; ++ break; ++ } ++ ++ if (src_nr >= 0) { ++ clksrc &= ~sclk->mask; ++ clksrc |= src_nr << sclk->shift; ++ ++#ifdef CONFIG_CPU_S3C6410 ++ if (sclk == &clk_audio2) ++ __raw_writel(clksrc, S3C_CLK_SRC2); ++ else ++#endif ++ __raw_writel(clksrc, S3C_CLK_SRC); ++ ++ clk->parent = parent; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk, ++ unsigned long rate) ++{ ++ unsigned long parent_rate = clk_get_rate(clk->parent); ++ int div; ++ ++ if (rate > parent_rate) ++ rate = parent_rate; ++ else { ++ div = rate / parent_rate; ++ ++ if (div == 0) ++ div = 1; ++ if (div > 16) ++ div = 16; ++ ++ rate = parent_rate / div; ++ } ++ ++ return rate; ++} ++ ++static struct clksrc_clk clk_mmc0 = { ++ .clk = { ++ .name = "mmc_bus", ++ .id = 0, ++ .ctrlbit = S3C_CLKCON_SCLK_MMC0, ++ .enable = s3c64xx_sclk_ctrl, ++ .set_parent = s3c64xx_setparent_clksrc, ++ .get_rate = s3c64xx_getrate_clksrc, ++ .set_rate = s3c64xx_setrate_clksrc, ++ .round_rate = s3c64xx_roundrate_clksrc, ++ }, ++ .shift = S3C6400_CLKSRC_MMC0_SHIFT, ++ .mask = S3C6400_CLKSRC_MMC0_MASK, ++ .sources = &clkset_spi_mmc, ++ .divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT, ++ .reg_divider = S3C_CLK_DIV1, ++}; ++ ++static struct clksrc_clk clk_mmc1 = { ++ .clk = { ++ .name = "mmc_bus", ++ .id = 1, ++ .ctrlbit = S3C_CLKCON_SCLK_MMC1, ++ .enable = s3c64xx_sclk_ctrl, ++ .get_rate = s3c64xx_getrate_clksrc, ++ .set_rate = s3c64xx_setrate_clksrc, ++ .set_parent = s3c64xx_setparent_clksrc, ++ .round_rate = s3c64xx_roundrate_clksrc, ++ }, ++ .shift = S3C6400_CLKSRC_MMC1_SHIFT, ++ .mask = S3C6400_CLKSRC_MMC1_MASK, ++ .sources = &clkset_spi_mmc, ++ .divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT, ++ .reg_divider = S3C_CLK_DIV1, ++}; ++ ++static struct clksrc_clk clk_mmc2 = { ++ .clk = { ++ .name = "mmc_bus", ++ .id = 2, ++ .ctrlbit = S3C_CLKCON_SCLK_MMC2, ++ .enable = s3c64xx_sclk_ctrl, ++ .get_rate = s3c64xx_getrate_clksrc, ++ .set_rate = s3c64xx_setrate_clksrc, ++ .set_parent = s3c64xx_setparent_clksrc, ++ .round_rate = s3c64xx_roundrate_clksrc, ++ }, ++ .shift = S3C6400_CLKSRC_MMC2_SHIFT, ++ .mask = S3C6400_CLKSRC_MMC2_MASK, ++ .sources = &clkset_spi_mmc, ++ .divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT, ++ .reg_divider = S3C_CLK_DIV1, ++}; ++ ++static struct clksrc_clk clk_usbhost = { ++ .clk = { ++ .name = "usb-host-bus", ++ .id = -1, ++ .ctrlbit = S3C_CLKCON_SCLK_UHOST, ++ .enable = s3c64xx_sclk_ctrl, ++ .set_parent = s3c64xx_setparent_clksrc, ++ .get_rate = s3c64xx_getrate_clksrc, ++ .set_rate = s3c64xx_setrate_clksrc, ++ .round_rate = s3c64xx_roundrate_clksrc, ++ }, ++ .shift = S3C6400_CLKSRC_UHOST_SHIFT, ++ .mask = S3C6400_CLKSRC_UHOST_MASK, ++ .sources = &clkset_uhost, ++ .divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT, ++ .reg_divider = S3C_CLK_DIV1, ++}; ++ ++static struct clksrc_clk clk_uart_uclk1 = { ++ .clk = { ++ .name = "uclk1", ++ .id = -1, ++ .ctrlbit = S3C_CLKCON_SCLK_UART, ++ .enable = s3c64xx_sclk_ctrl, ++ .set_parent = s3c64xx_setparent_clksrc, ++ .get_rate = s3c64xx_getrate_clksrc, ++ .set_rate = s3c64xx_setrate_clksrc, ++ .round_rate = s3c64xx_roundrate_clksrc, ++ }, ++ .shift = S3C6400_CLKSRC_UART_SHIFT, ++ .mask = S3C6400_CLKSRC_UART_MASK, ++ .sources = &clkset_uart, ++ .divider_shift = S3C6400_CLKDIV2_UART_SHIFT, ++ .reg_divider = S3C_CLK_DIV2, ++}; ++ ++/* Where does UCLK0 come from? */ ++ ++static struct clksrc_clk clk_spi0 = { ++ .clk = { ++ .name = "spi-bus", ++ .id = 0, ++ .ctrlbit = S3C_CLKCON_SCLK_SPI0, ++ .enable = s3c64xx_sclk_ctrl, ++ .set_parent = s3c64xx_setparent_clksrc, ++ .get_rate = s3c64xx_getrate_clksrc, ++ .set_rate = s3c64xx_setrate_clksrc, ++ .round_rate = s3c64xx_roundrate_clksrc, ++ }, ++ .shift = S3C6400_CLKSRC_SPI0_SHIFT, ++ .mask = S3C6400_CLKSRC_SPI0_MASK, ++ .sources = &clkset_spi_mmc, ++ .divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT, ++ .reg_divider = S3C_CLK_DIV2, ++}; ++ ++static struct clksrc_clk clk_spi1 = { ++ .clk = { ++ .name = "spi-bus", ++ .id = 1, ++ .ctrlbit = S3C_CLKCON_SCLK_SPI1, ++ .enable = s3c64xx_sclk_ctrl, ++ .set_parent = s3c64xx_setparent_clksrc, ++ .get_rate = s3c64xx_getrate_clksrc, ++ .set_rate = s3c64xx_setrate_clksrc, ++ .round_rate = s3c64xx_roundrate_clksrc, ++ }, ++ .shift = S3C6400_CLKSRC_SPI1_SHIFT, ++ .mask = S3C6400_CLKSRC_SPI1_MASK, ++ .sources = &clkset_spi_mmc, ++ .divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT, ++ .reg_divider = S3C_CLK_DIV2, ++}; ++ ++static struct clk clk_iis_cd0 = { ++ .name = "iis_cdclk0", ++ .id = -1, ++}; ++ ++static struct clk clk_iis_cd1 = { ++ .name = "iis_cdclk1", ++ .id = -1, ++}; ++ ++static struct clk clk_iis_cd_v40 = { ++ .name = "iis_cdclk_v40", ++ .id = -1, ++}; ++ ++static struct clk clk_pcm_cd0 = { ++ .name = "pcm_cdclk0", ++ .id = -1, ++}; ++ ++#ifdef CONFIG_CPU_S3C6410 ++static struct clk clk_pcm_cd1 = { ++ .name = "pcm_cdclk1", ++ .id = -1, ++}; ++#endif ++ ++static struct clk *clkset_audio0_list[] = { ++ [0] = &clk_mout_epll.clk, ++ [1] = &clk_dout_mpll, ++ [2] = &clk_fin_epll, ++ [3] = &clk_iis_cd0, ++ [4] = &clk_pcm_cd0, ++}; ++ ++static struct clk_sources clkset_audio0 = { ++ .sources = clkset_audio0_list, ++ .nr_sources = ARRAY_SIZE(clkset_audio0_list), ++}; ++ ++static struct clksrc_clk clk_audio0 = { ++ .clk = { ++ .name = "audio-bus0", ++ .id = -1, ++ .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, ++ .enable = s3c64xx_sclk_ctrl, ++ .set_parent = s3c64xx_setparent_clksrc, ++ .get_rate = s3c64xx_getrate_clksrc, ++ .set_rate = s3c64xx_setrate_clksrc, ++ .round_rate = s3c64xx_roundrate_clksrc, ++ }, ++ .shift = S3C6400_CLKSRC_AUDIO0_SHIFT, ++ .mask = S3C6400_CLKSRC_AUDIO0_MASK, ++ .sources = &clkset_audio0, ++ .divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT, ++ .reg_divider = S3C_CLK_DIV2, ++}; ++ ++static struct clk *clkset_audio1_list[] = { ++ [0] = &clk_mout_epll.clk, ++ [1] = &clk_dout_mpll, ++ [2] = &clk_fin_epll, ++ [3] = &clk_iis_cd1, ++#ifdef CONFIG_CPU_S3C6410 ++ [4] = &clk_pcm_cd1, ++#else ++ [4] = &clk_pcm_cd0, ++#endif ++}; ++ ++static struct clk_sources clkset_audio1 = { ++ .sources = clkset_audio1_list, ++ .nr_sources = ARRAY_SIZE(clkset_audio1_list), ++}; ++ ++static struct clksrc_clk clk_audio1 = { ++ .clk = { ++ .name = "audio-bus1", ++ .id = -1, ++ .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, ++ .enable = s3c64xx_sclk_ctrl, ++ .set_parent = s3c64xx_setparent_clksrc, ++ .get_rate = s3c64xx_getrate_clksrc, ++ .set_rate = s3c64xx_setrate_clksrc, ++ .round_rate = s3c64xx_roundrate_clksrc, ++ }, ++ .shift = S3C6400_CLKSRC_AUDIO1_SHIFT, ++ .mask = S3C6400_CLKSRC_AUDIO1_MASK, ++ .sources = &clkset_audio1, ++ .divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT, ++ .reg_divider = S3C_CLK_DIV2, ++}; ++ ++#ifdef CONFIG_CPU_S3C6410 ++static struct clk *clkset_audio2_list[] = { ++ [0] = &clk_mout_epll.clk, ++ [1] = &clk_dout_mpll, ++ [2] = &clk_fin_epll, ++ [3] = &clk_iis_cd_v40, ++ [4] = &clk_pcm_cd1, ++}; ++ ++static struct clk_sources clkset_audio2 = { ++ .sources = clkset_audio2_list, ++ .nr_sources = ARRAY_SIZE(clkset_audio2_list), ++}; ++ ++static struct clksrc_clk clk_audio2 = { ++ .clk = { ++ .name = "audio-bus2", ++ .id = -1, ++ .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2, ++ .enable = s3c64xx_sclk_ctrl, ++ .set_parent = s3c64xx_setparent_clksrc, ++ .get_rate = s3c64xx_getrate_clksrc, ++ .set_rate = s3c64xx_setrate_clksrc, ++ .round_rate = s3c64xx_roundrate_clksrc, ++ }, ++ .shift = S3C6410_CLKSRC2_AUDIO2_SHIFT, ++ .mask = S3C6410_CLKSRC2_AUDIO2_MASK, ++ .sources = &clkset_audio2, ++ .divider_shift = S3C6410_CLKDIV2_AUDIO2_SHIFT, ++ .reg_divider = S3C_CLK_DIV2, ++}; ++#endif ++ ++static struct clksrc_clk clk_irda = { ++ .clk = { ++ .name = "irda-bus", ++ .id = 0, ++ .ctrlbit = S3C_CLKCON_SCLK_IRDA, ++ .enable = s3c64xx_sclk_ctrl, ++ .set_parent = s3c64xx_setparent_clksrc, ++ .get_rate = s3c64xx_getrate_clksrc, ++ .set_rate = s3c64xx_setrate_clksrc, ++ .round_rate = s3c64xx_roundrate_clksrc, ++ }, ++ .shift = S3C6400_CLKSRC_IRDA_SHIFT, ++ .mask = S3C6400_CLKSRC_IRDA_MASK, ++ .sources = &clkset_irda, ++ .divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT, ++ .reg_divider = S3C_CLK_DIV2, ++}; ++ ++/* Clock initialisation code */ ++ ++static struct clksrc_clk *init_parents[] = { ++ &clk_mout_apll, ++ &clk_mout_epll, ++ &clk_mout_mpll, ++ &clk_mmc0, ++ &clk_mmc1, ++ &clk_mmc2, ++ &clk_usbhost, ++ &clk_uart_uclk1, ++ &clk_spi0, ++ &clk_spi1, ++ &clk_audio0, ++ &clk_audio1, ++#ifdef CONFIG_CPU_S3C6410 ++ &clk_audio2, ++#endif ++ &clk_irda, ++}; ++ ++static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk) ++{ ++ struct clk_sources *srcs = clk->sources; ++ u32 clksrc; ++ ++#ifdef CONFIG_CPU_S3C6410 ++ if(clk == &clk_audio2) ++ clksrc = __raw_readl(S3C_CLK_SRC2); ++ else ++#endif ++ clksrc = __raw_readl(S3C_CLK_SRC); ++ ++ ++ clksrc &= clk->mask; ++ clksrc >>= clk->shift; ++ ++ if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) { ++ printk(KERN_ERR "%s: bad source %d\n", ++ clk->clk.name, clksrc); ++ return; ++ } ++ ++ clk->clk.parent = srcs->sources[clksrc]; ++ ++ printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", ++ clk->clk.name, clk->clk.parent->name, clksrc, ++ clk_get_rate(&clk->clk)); ++} ++ ++#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) ++ ++void __init_or_cpufreq s3c6400_setup_clocks(void) ++{ ++ struct clk *xtal_clk; ++ unsigned long xtal; ++ unsigned long fclk; ++ unsigned long hclk; ++ unsigned long hclkx2; ++ unsigned long pclk; ++ unsigned long epll; ++ unsigned long apll; ++ unsigned long mpll; ++ unsigned int ptr; ++ u32 clkdiv0; ++ ++ printk(KERN_DEBUG "%s: registering clocks\n", __func__); ++ ++ clkdiv0 = __raw_readl(S3C_CLK_DIV0); ++ printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0); ++ ++ xtal_clk = clk_get(NULL, "xtal"); ++ BUG_ON(IS_ERR(xtal_clk)); ++ ++ xtal = clk_get_rate(xtal_clk); ++ clk_put(xtal_clk); ++ ++ printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); ++ ++ epll = s3c6400_get_epll(xtal); ++ mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON)); ++ apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON)); ++ ++ fclk = apll / GET_DIV(clkdiv0, S3C6410_CLKDIV0_ARM); ++ ++ printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n", ++ apll, mpll, epll); ++ ++ if(__raw_readl(S3C_OTHERS) & S3C_OTHERS_SYNCMUXSEL_SYNC) { ++ /* Synchronous mode */ ++ hclkx2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); ++ } else { ++ /* Asynchronous mode */ ++ hclkx2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); ++ } ++ ++ hclk = hclkx2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK); ++ pclk = hclkx2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK); ++ ++ printk(KERN_INFO "S3C64XX: HCLKx2=%ld, HCLK=%ld, PCLK=%ld\n", ++ hclkx2, hclk, pclk); ++ ++ clk_fout_mpll.rate = mpll; ++ clk_fout_epll.rate = epll; ++ clk_fout_apll.rate = apll; ++ ++ clk_hx2.rate = hclkx2; ++ clk_h.rate = hclk; ++ clk_p.rate = pclk; ++ clk_f.rate = fclk; ++ ++ /* mod by scsuh */ ++#if 1 ++ { ++ u32 tmp; ++ ++ tmp = readl(S3C_CLK_SRC); ++ writel(tmp | 0x00540000, S3C_CLK_SRC); ++ tmp = readl(S3C_CLK_DIV1); ++ writel(tmp | 0x00000555, S3C_CLK_DIV1); ++ printk("div1: %08x\n", readl(S3C_CLK_DIV1)); ++ } ++#endif ++ ++ for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) ++ s3c6400_set_clksrc(init_parents[ptr]); ++} ++ ++static struct clk *clks[] __initdata = { ++ &clk_ext_xtal_mux, ++ &clk_iis_cd0, ++ &clk_iis_cd1, ++ &clk_iis_cd_v40, ++ &clk_pcm_cd0, ++#ifdef CONFIG_CPU_S3C6410 ++ &clk_pcm_cd1, ++#endif ++ &clk_mout_epll.clk, ++ &clk_fout_epll, ++ &clk_mout_mpll.clk, ++ &clk_dout_mpll, ++ &clk_mmc0.clk, ++ &clk_mmc1.clk, ++ &clk_mmc2.clk, ++ &clk_usbhost.clk, ++ &clk_uart_uclk1.clk, ++ &clk_spi0.clk, ++ &clk_spi1.clk, ++ &clk_audio0.clk, ++ &clk_audio1.clk, ++#ifdef CONFIG_CPU_S3C6410 ++ &clk_audio2.clk, ++#endif ++ &clk_irda.clk, ++}; ++ ++void __init s3c6400_register_clocks(void) ++{ ++ struct clk *clkp; ++ int ret; ++ int ptr; ++ ++ for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { ++ clkp = clks[ptr]; ++ ret = s3c24xx_register_clock(clkp); ++ if (ret < 0) { ++ printk(KERN_ERR "Failed to register clock %s (%d)\n", ++ clkp->name, ret); ++ } ++ } ++ ++// clk_mpll.parent = &clk_mout_mpll.clk; ++ clk_epll.parent = &clk_mout_epll.clk; ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/s3c6400-init.c linux-2.6.28.6/arch/arm/plat-s3c64xx/s3c6400-init.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/s3c6400-init.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/s3c6400-init.c 2009-10-13 10:06:38.000000000 +0200 +@@ -0,0 +1,29 @@ ++/* linux/arch/arm/plat-s3c64xx/s3c6400-init.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C6400 - CPU initialisation (common with other S3C64XX chips) ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++/* uart registration process */ ++ ++void __init s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) ++{ ++ s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no); ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c linux-2.6.28.6/arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,201 @@ ++/* ++ * linux/arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c ++ * ++ * CPU frequency scaling for S3C64XX ++ * ++ * Copyright (C) 2008 Samsung Electronics ++ * ++ * Based on cpu-sa1110.c, Copyright (C) 2001 Russell King ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//#include ++#include ++ ++#define USE_FREQ_TABLE ++#define USE_DVS ++#define VERY_HI_RATE 532*1000*1000 ++#define APLL_GEN_CLK 532*1000 //khz ++#define KHZ_T 1000 ++ ++#define MPU_CLK "clk_cpu" ++ ++/* definition for power setting function */ ++extern int set_power(unsigned int freq); ++extern void ltc3714_init(void); ++ ++#define ARM_LE 0 ++#define INT_LE 1 ++ ++/* frequency */ ++static struct cpufreq_frequency_table s3c6410_freq_table[] = { ++ {APLL_GEN_CLK, APLL_GEN_CLK}, ++ {APLL_GEN_CLK, APLL_GEN_CLK/2}, ++ {APLL_GEN_CLK, APLL_GEN_CLK/4}, ++ {0, CPUFREQ_TABLE_END}, ++}; ++ ++/* TODO: Add support for SDRAM timing changes */ ++ ++int s3c6410_verify_speed(struct cpufreq_policy *policy) ++{ ++#ifndef USE_FREQ_TABLE ++ struct clk *mpu_clk; ++#endif ++ ++ if (policy->cpu) ++ return -EINVAL; ++#ifdef USE_FREQ_TABLE ++ return cpufreq_frequency_table_verify(policy, s3c6410_freq_table); ++#else ++ cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, ++ policy->cpuinfo.max_freq); ++ mpu_clk = clk_get(NULL, MPU_CLK); ++ if (IS_ERR(mpu_clk)) ++ return PTR_ERR(mpu_clk); ++ ++ policy->min = clk_round_rate(mpu_clk, policy->min * KHZ_T) / KHZ_T; ++ policy->max = clk_round_rate(mpu_clk, policy->max * KHZ_T) / KHZ_T; ++ ++ cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, ++ policy->cpuinfo.max_freq); ++ ++ clk_put(mpu_clk); ++ ++ return 0; ++#endif ++} ++ ++unsigned int s3c6410_getspeed(unsigned int cpu) ++{ ++ struct clk * mpu_clk; ++ unsigned long rate; ++ ++ if (cpu) ++ return 0; ++ ++ mpu_clk = clk_get(NULL, MPU_CLK); ++ if (IS_ERR(mpu_clk)) ++ return 0; ++ rate = clk_get_rate(mpu_clk) / KHZ_T; ++ ++ clk_put(mpu_clk); ++ ++ return rate; ++} ++ ++static int s3c6410_target(struct cpufreq_policy *policy, ++ unsigned int target_freq, ++ unsigned int relation) ++{ ++ struct clk * mpu_clk; ++ struct cpufreq_freqs freqs; ++ int ret = 0; ++ unsigned long arm_clk; ++ unsigned int index; ++ ++ mpu_clk = clk_get(NULL, MPU_CLK); ++ if (IS_ERR(mpu_clk)) ++ return PTR_ERR(mpu_clk); ++ ++ freqs.old = s3c6410_getspeed(0); ++#ifdef USE_FREQ_TABLE ++ if (cpufreq_frequency_table_target(policy, s3c6410_freq_table, target_freq, relation, &index)) ++ return -EINVAL; ++ ++ arm_clk = s3c6410_freq_table[index].frequency; ++ ++ freqs.new = arm_clk; ++#else ++ freqs.new = clk_round_rate(mpu_clk, target_freq * KHZ_T) / KHZ_T; ++#endif ++ freqs.cpu = 0; ++ ++ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); ++#ifdef USE_DVS ++ if(freqs.new < freqs.old){ ++ /* frequency scaling */ ++ ret = clk_set_rate(mpu_clk, target_freq * KHZ_T); ++ if(ret != 0) ++ printk("frequency scaling error\n"); ++ /* voltage scaling */ ++ set_power(freqs.new); ++ }else{ ++ /* voltage scaling */ ++ set_power(freqs.new); ++ ++ /* frequency scaling */ ++ ret = clk_set_rate(mpu_clk, target_freq * KHZ_T); ++ if(ret != 0) ++ printk("frequency scaling error\n"); ++ } ++ ++ ++#else ++ ret = clk_set_rate(mpu_clk, target_freq * KHZ_T); ++ if(ret != 0) ++ printk("frequency scaling error\n"); ++ ++#endif ++ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); ++ clk_put(mpu_clk); ++ return ret; ++} ++ ++static int __init s3c6410_cpu_init(struct cpufreq_policy *policy) ++{ ++ struct clk * mpu_clk; ++ ++#ifdef USE_DVS ++ ltc3714_init(); ++#endif ++ mpu_clk = clk_get(NULL, MPU_CLK); ++ if (IS_ERR(mpu_clk)) ++ return PTR_ERR(mpu_clk); ++ ++ if (policy->cpu != 0) ++ return -EINVAL; ++ policy->cur = policy->min = policy->max = s3c6410_getspeed(0); ++#ifdef USE_FREQ_TABLE ++ cpufreq_frequency_table_get_attr(s3c6410_freq_table, policy->cpu); ++#else ++ policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / KHZ_T; ++ policy->cpuinfo.max_freq = clk_round_rate(mpu_clk, VERY_HI_RATE) / KHZ_T; ++#endif ++ policy->cpuinfo.transition_latency = 40000; //1us ++ ++ ++ clk_put(mpu_clk); ++#ifdef USE_FREQ_TABLE ++ return cpufreq_frequency_table_cpuinfo(policy, s3c6410_freq_table); ++#else ++ return 0; ++#endif ++} ++ ++static struct cpufreq_driver s3c6410_driver = { ++ .flags = CPUFREQ_STICKY, ++ .verify = s3c6410_verify_speed, ++ .target = s3c6410_target, ++ .get = s3c6410_getspeed, ++ .init = s3c6410_cpu_init, ++ .name = "s3c6410", ++}; ++ ++static int __init s3c6410_cpufreq_init(void) ++{ ++ return cpufreq_register_driver(&s3c6410_driver); ++} ++ ++arch_initcall(s3c6410_cpufreq_init); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/setup-fimc0.c linux-2.6.28.6/arch/arm/plat-s3c64xx/setup-fimc0.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/setup-fimc0.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/setup-fimc0.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,46 @@ ++/* linux/arch/arm/plat-s5pc1xx/setup-fimc0.c ++ * ++ * Copyright 2009 Samsung Electronics ++ * Jinsung Yang ++ * http://samsungsemi.com/ ++ * ++ * Base S5PC1XX FIMC controller 0 gpio configuration ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct platform_device; /* don't need the contents */ ++ ++void s3c_fimc0_cfg_gpio(struct platform_device *dev) ++{ ++ int i; ++ ++ s3c_gpio_cfgpin(S3C64XX_GPF(0), S3C64XX_GPF0_CAMIF_CLK); ++ s3c_gpio_cfgpin(S3C64XX_GPF(1), S3C64XX_GPF1_CAMIF_HREF); ++ s3c_gpio_cfgpin(S3C64XX_GPF(2), S3C64XX_GPF2_CAMIF_PCLK); ++ s3c_gpio_cfgpin(S3C64XX_GPF(3), S3C64XX_GPF3_CAMIF_nRST); ++ s3c_gpio_cfgpin(S3C64XX_GPF(4), S3C64XX_GPF4_CAMIF_VSYNC); ++ s3c_gpio_cfgpin(S3C64XX_GPF(5), S3C64XX_GPF5_CAMIF_YDATA0); ++ s3c_gpio_cfgpin(S3C64XX_GPF(6), S3C64XX_GPF6_CAMIF_YDATA1); ++ s3c_gpio_cfgpin(S3C64XX_GPF(7), S3C64XX_GPF7_CAMIF_YDATA2); ++ s3c_gpio_cfgpin(S3C64XX_GPF(8), S3C64XX_GPF8_CAMIF_YDATA3); ++ s3c_gpio_cfgpin(S3C64XX_GPF(9), S3C64XX_GPF9_CAMIF_YDATA4); ++ s3c_gpio_cfgpin(S3C64XX_GPF(10), S3C64XX_GPF10_CAMIF_YDATA5); ++ s3c_gpio_cfgpin(S3C64XX_GPF(11), S3C64XX_GPF11_CAMIF_YDATA6); ++ s3c_gpio_cfgpin(S3C64XX_GPF(12), S3C64XX_GPF12_CAMIF_YDATA7); ++ s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C64XX_GPB4_CAM_FIELD); ++ ++ for (i = 0; i < 12; i++) ++ s3c_gpio_setpull(S3C64XX_GPF(i), S3C_GPIO_PULL_UP); ++ ++ s3c_gpio_setpull(S3C64XX_GPB(4), S3C_GPIO_PULL_UP); ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/setup-fimc1.c linux-2.6.28.6/arch/arm/plat-s3c64xx/setup-fimc1.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/setup-fimc1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/setup-fimc1.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,26 @@ ++/* linux/arch/arm/plat-s5pc1xx/setup-fimc0.c ++ * ++ * Copyright 2009 Samsung Electronics ++ * Jinsung Yang ++ * http://samsungsemi.com/ ++ * ++ * Base S5PC1XX FIMC controller 0 gpio configuration ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct platform_device; /* don't need the contents */ ++ ++void s3c_fimc1_cfg_gpio(struct platform_device *dev) ++{ ++ /* nothing to do */ ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/setup-i2c0.c linux-2.6.28.6/arch/arm/plat-s3c64xx/setup-i2c0.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/setup-i2c0.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/setup-i2c0.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,31 @@ ++/* linux/arch/arm/plat-s3c64xx/setup-i2c0.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * Base S3C64XX I2C bus 0 gpio configuration ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++ ++struct platform_device; /* don't need the contents */ ++ ++#include ++#include ++#include ++#include ++ ++void s3c_i2c0_cfg_gpio(struct platform_device *dev) ++{ ++ s3c_gpio_cfgpin(S3C64XX_GPB(5), S3C64XX_GPB5_I2C_SCL0); ++ s3c_gpio_cfgpin(S3C64XX_GPB(6), S3C64XX_GPB6_I2C_SDA0); ++ s3c_gpio_setpull(S3C64XX_GPB(5), S3C_GPIO_PULL_UP); ++ s3c_gpio_setpull(S3C64XX_GPB(6), S3C_GPIO_PULL_UP); ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/setup-i2c1.c linux-2.6.28.6/arch/arm/plat-s3c64xx/setup-i2c1.c +--- linux-2.6.28/arch/arm/plat-s3c64xx/setup-i2c1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/setup-i2c1.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,31 @@ ++/* linux/arch/arm/plat-s3c64xx/setup-i2c1.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * Base S3C64XX I2C bus 1 gpio configuration ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++ ++struct platform_device; /* don't need the contents */ ++ ++#include ++#include ++#include ++#include ++ ++void s3c_i2c1_cfg_gpio(struct platform_device *dev) ++{ ++ s3c_gpio_cfgpin(S3C64XX_GPB(2), S3C64XX_GPB2_I2C_SCL1); ++ s3c_gpio_cfgpin(S3C64XX_GPB(3), S3C64XX_GPB3_I2C_SDA1); ++ s3c_gpio_setpull(S3C64XX_GPB(2), S3C_GPIO_PULL_UP); ++ s3c_gpio_setpull(S3C64XX_GPB(3), S3C_GPIO_PULL_UP); ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s3c64xx/sleep.S linux-2.6.28.6/arch/arm/plat-s3c64xx/sleep.S +--- linux-2.6.28/arch/arm/plat-s3c64xx/sleep.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s3c64xx/sleep.S 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,144 @@ ++/* linux/0arch/arm/plat-s3c64xx/sleep.S ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C64XX CPU sleep code ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++ ++#undef S3C64XX_VA_GPIO ++#define S3C64XX_VA_GPIO (0x0) ++ ++#include ++#include ++ ++#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT)) ++ ++ .text ++ ++ /* s3c_cpu_save ++ * ++ * Save enough processor state to allow the restart of the pm.c ++ * code after resume. ++ * ++ * entry: ++ * r0 = pointer to the save block ++ * exit: ++ * r0 = exit code: 1 => stored data ++ * 0 => resumed from sleep ++ */ ++ ++ENTRY(s3c6410_cpu_save) ++ stmfd sp!, { r4 - r12, lr } ++ ++ mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID ++ mrc p15, 0, r5, c3, c0, 0 @ Domain ID ++ mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 ++ mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 ++ mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control ++ mrc p15, 0, r9, c1, c0, 0 @ Control register ++ mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register ++ mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls ++ ++ stmia r0, { r4 - r13 } @ Save CP registers and SP ++ mov r0, #0 ++ ldmfd sp, { r4 - r12, pc } @ return, not disturbing SP ++ ++ @@ return to the caller, after the MMU is turned on. ++ @@ restore the last bits of the stack and return. ++resume_with_mmu: ++ mov r0, #1 ++ ldmfd sp!, { r4 - r12, pc } @ return, from sp from s3c_cpu_save ++ ++ .data ++ ++ /* the next bit is code, but it requires easy access to the ++ * s3c_sleep_save_phys data before the MMU is switched on, so ++ * we store the code that needs this variable in the .data where ++ * the value can be written to (the .text segment is RO). ++ */ ++ ++ .global s3c6410_sleep_save_phys ++s3c6410_sleep_save_phys: ++ .word 0 ++ ++ /* Sleep magic, the word before the resume entry point so that the ++ * bootloader can check for a resumeable image. */ ++ ++ .word 0x2bedf00d ++ ++ /* s3c_cpu_reusme ++ * ++ * This is the entry point, stored by whatever method the bootloader ++ * requires to get the kernel runnign again. This code expects to be ++ * entered with no caches live and the MMU disabled. It will then ++ * restore the MMU and other basic CP registers saved and restart ++ * the kernel C code to finish the resume code. ++ */ ++ ++ENTRY(s3c6410_cpu_resume) ++ msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE ++ ldr r2, =LL_UART /* for debug */ ++ ++#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK ++ /* Initialise the GPIO state if we are debugging via the SMDK LEDs, ++ * as the uboot version supplied resets these to inputs during the ++ * resume checks. ++ */ ++ ++ ldr r3, =S3C64XX_PA_GPIO ++ ldr r0, [ r3, #S3C64XX_GPNCON ] ++ bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \ ++ S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15)) ++ orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \ ++ S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15)) ++ str r0, [ r3, #S3C64XX_GPNCON ] ++ ++ ldr r0, [ r3, #S3C64XX_GPNDAT ] ++ bic r0, r0, #0xf << 12 @ GPN12..15 ++ orr r0, r0, #1 << 15 @ GPN15 ++ str r0, [ r3, #S3C64XX_GPNDAT ] ++#endif ++ ++ /* __v6_setup from arch/arm/mm/proc-v6.S, ensure that the caches ++ * are thoroughly cleaned just in case the bootloader didn't do it ++ * for us. */ ++ mov r0, #0 ++ mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache ++ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache ++ mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache ++ mcr p15, 0, r0, c7, c10, 4 @ drain write buffer ++ @@mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs ++ @@mcr p15, 0, r0, c7, c7, 0 @ Invalidate I + D caches ++ ++ ldr r0, s3c6410_sleep_save_phys ++ ldmia r0, { r4 - r13 } ++ ++ mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID ++ mcr p15, 0, r5, c3, c0, 0 @ Domain ID ++ mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 ++ mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 ++ mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control ++ mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register ++ ++ mov r0, #0 @ restore copro access controls ++ mcr p15, 0, r11, c1, c0, 2 @ Co-processor access controls ++ mcr p15, 0, r0, c7, c5, 4 ++ ++ ldr r2, =resume_with_mmu ++ mcr p15, 0, r9, c1, c0, 0 /* turn mmu back on */ ++ nop ++ mov pc, r2 /* jump back */ ++ ++ .end ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/Kconfig linux-2.6.28.6/arch/arm/plat-s5p64xx/Kconfig +--- linux-2.6.28/arch/arm/plat-s5p64xx/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/Kconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,68 @@ ++# arch/arm/plat-s5p64xx/Kconfig ++# ++# Copyright 2008 Openmoko, Inc. ++# Copyright 2008 Simtec Electronics ++# Ben Dooks ++# ++# Licensed under GPLv2 ++ ++config PLAT_S5P64XX ++ bool ++ depends on ARCH_S5P64XX ++ select PLAT_S3C ++ select ARM_VIC ++ default y ++ select NO_IOPORT ++ select ARCH_REQUIRE_GPIOLIB ++ select S3C_GPIO_TRACK ++ select S3C_GPIO_PULL_UPDOWN ++ select S3C_GPIO_CFG_S3C24XX ++ select S3C_GPIO_CFG_S3C64XX ++ help ++ Base platform code for any Samsung S5P64XX device ++ ++if PLAT_S5P64XX ++ ++# Configuration options shared by all S5P64XX implementations ++ ++config CPU_S5P6440_INIT ++ bool ++ help ++ Initialisation code for the S5P6440. ++ ++config CPU_S5P6440_CLOCK ++ bool ++ help ++ Clock support code for the S5P6440. ++ ++# platform specific device setup ++ ++config S5P64XX_SETUP_I2C0 ++ bool ++ default y ++ help ++ Common setup code for i2c bus 0. ++ ++ Note, currently since i2c0 is always compiled, this setup helper ++ is always compiled with it. ++ ++config S5P64XX_SETUP_I2C1 ++ bool ++ help ++ Common setup code for i2c bus 1. ++ ++config S5P64XX_ADC ++ bool "S5P64XX ADC D/D support" ++ help ++ Analog to Digital conversion(ADC) D/D for S5P64XX support ++ ++config S5P64XX_PWM ++ bool "PWM device support" ++ default n ++ select HAVE_PWM ++ help ++ Support for exporting the PWM timer blocks via the pwm device ++ system. ++ ++ ++endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/Makefile linux-2.6.28.6/arch/arm/plat-s5p64xx/Makefile +--- linux-2.6.28/arch/arm/plat-s5p64xx/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/Makefile 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,38 @@ ++# arch/arm/plat-s5p64xx/Makefile ++# ++# Copyright 2008 Openmoko, Inc. ++# Copyright 2008 Simtec Electronics ++# ++# Licensed under GPLv2 ++ ++obj-y := ++obj-m := ++obj-n := dummy.o ++obj- := ++ ++# Core files ++ ++obj-y += dev-uart.o devs.o ++obj-y += cpu.o ++obj-y += irq.o ++obj-y += irq-eint.o ++obj-y += clock.o ++obj-y += gpiolib.o ++obj-y += bootmem.o ++ ++# CPU support ++ ++obj-$(CONFIG_CPU_S5P6440_INIT) += s5p6440-init.o ++obj-$(CONFIG_CPU_S5P6440_CLOCK) += s5p6440-clock.o ++obj-$(CONFIG_CPU_FREQ) += s5p64xx-cpufreq.o ltc3714.o ++obj-$(CONFIG_PM) += pm.o ++obj-$(CONFIG_PM) += sleep.o ++ ++# Device setup ++ ++obj-$(CONFIG_S5P64XX_SETUP_I2C0) += setup-i2c0.o ++obj-$(CONFIG_S5P64XX_SETUP_I2C1) += setup-i2c1.o ++obj-$(CONFIG_S5P64XX_DEV_POST) += dev-post.o ++obj-$(CONFIG_S5P64XX_SETUP_POST) += setup-post.o ++obj-$(CONFIG_S5P64XX_ADC) += adc.o ++obj-$(CONFIG_HAVE_PWM) += pwm.o +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/adc.c linux-2.6.28.6/arch/arm/plat-s5p64xx/adc.c +--- linux-2.6.28/arch/arm/plat-s5p64xx/adc.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/adc.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,363 @@ ++/* linux/arch/arm/plat-s5p64xx/adc.c ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * Copyright (c) 2004 Arnaud Patard ++ * iPAQ H1940 touchscreen support ++ * ++ * ChangeLog ++ * ++ * 2004-09-05: Herbert Pötzl ++ * - added clock (de-)allocation code ++ * ++ * 2005-03-06: Arnaud Patard ++ * - h1940_ -> s3c24xx (this driver is now also used on the n30 ++ * machines :P) ++ * - Debug messages are now enabled with the config option ++ * TOUCHSCREEN_S3C_DEBUG ++ * - Changed the way the value are read ++ * - Input subsystem should now work ++ * - Use ioremap and readl/writel ++ * ++ * 2005-03-23: Arnaud Patard ++ * - Make use of some undocumented features of the touchscreen ++ * controller ++ * ++ */ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#define ADC_MINOR 131 ++#define ADC_INPUT_PIN _IOW('S', 0x0c, unsigned long) ++ ++#undef ADC_WITH_TOUCHSCREEN ++ ++static struct clk *adc_clock; ++static struct resource *adc_mem; ++static void __iomem *base_addr; ++static int adc_port = 0; ++struct s3c_adc_mach_info *plat_data; ++ ++#ifdef ADC_WITH_TOUCHSCREEN ++static DEFINE_MUTEX(adc_mutex); ++ ++static unsigned long data_for_ADCCON; ++static unsigned long data_for_ADCTSC; ++ ++static void s3c_adc_save_SFR_on_ADC(void) ++{ ++ data_for_ADCCON = readl(base_addr + S3C_ADCCON); ++ data_for_ADCTSC = readl(base_addr + S3C_ADCTSC); ++} ++ ++static void s3c_adc_restore_SFR_on_ADC(void) ++{ ++ writel(data_for_ADCCON, base_addr + S3C_ADCCON); ++ writel(data_for_ADCTSC, base_addr + S3C_ADCTSC); ++} ++#endif ++ ++static int s3c_adc_open(struct inode *inode, struct file *file) ++{ ++ printk(KERN_INFO " s3c_adc_open() entered\n"); ++ return 0; ++} ++ ++unsigned int s3c_adc_convert(void) ++{ ++ unsigned int adc_return = 0; ++ unsigned long data0; ++ unsigned long data1; ++ ++ writel(adc_port , base_addr + S3C_ADCMUX); ++ ++ udelay(10); ++ ++ writel(readl(base_addr + S3C_ADCCON) | S3C_ADCCON_ENABLE_START, base_addr + S3C_ADCCON); ++ ++ do { ++ data0 = readl(base_addr + S3C_ADCCON); ++ } while(!(data0 & S3C_ADCCON_ECFLG)); ++ ++ data1 = readl(base_addr + S3C_ADCDAT0); ++ ++ if (plat_data->resolution == 12) ++ adc_return = data1 & S3C_ADCDAT0_XPDATA_MASK_12BIT; ++ else ++ adc_return = data1 & S3C_ADCDAT0_XPDATA_MASK; ++ ++ return adc_return; ++} ++ ++ ++static int s3c_adc_get(struct s3c_adc_request *req) ++{ ++ unsigned adc_channel = req->channel; ++ int adc_value_ret = 0; ++ ++ adc_value_ret = s3c_adc_convert(); ++ ++ req->callback(adc_channel,req->param,adc_value_ret); ++ ++ return 0; ++} ++ ++static ssize_t ++s3c_adc_read(struct file *file, char __user * buffer, ++ size_t size, loff_t * pos) ++{ ++ int adc_value = 0; ++ ++ printk(KERN_INFO " s3c_adc_read() entered\n"); ++ ++#ifdef ADC_WITH_TOUCHSCREEN ++ mutex_lock(&adc_mutex); ++ s3c_adc_save_SFR_on_ADC(); ++#endif ++ ++ adc_value = s3c_adc_convert(); ++ ++#ifdef ADC_WITH_TOUCHSCREEN ++ s3c_adc_restore_SFR_on_ADC(); ++ mutex_unlock(&adc_mutex); ++#endif ++ ++ printk(KERN_INFO " Converted Value: %03d\n", adc_value); ++ ++ if (copy_to_user(buffer, &adc_value, sizeof(unsigned int))) { ++ return -EFAULT; ++ } ++ return sizeof(unsigned int); ++} ++ ++ ++static int s3c_adc_ioctl(struct inode *inode, struct file *file, ++ unsigned int cmd, unsigned long arg) ++{ ++ ++ printk(KERN_INFO " s3c_adc_ioctl(cmd:: %d) entered\n", cmd); ++ ++ switch (cmd) { ++ case ADC_INPUT_PIN: ++ adc_port = (unsigned int) arg; ++ ++ if (adc_port >= 4) ++ printk(" %d is already reserved for TouchScreen\n", adc_port); ++ return 0; ++ ++ default: ++ return -ENOIOCTLCMD; ++ } ++} ++ ++static struct file_operations s3c_adc_fops = { ++ .owner = THIS_MODULE, ++ .read = s3c_adc_read, ++ .open = s3c_adc_open, ++ .ioctl = s3c_adc_ioctl, ++}; ++ ++static struct miscdevice s3c_adc_miscdev = { ++ .minor = ADC_MINOR, ++ .name = "adc", ++ .fops = &s3c_adc_fops, ++}; ++ ++static struct s3c_adc_mach_info *s3c_adc_get_platdata(struct device *dev) ++{ ++ if(dev->platform_data != NULL) ++ { ++ printk(KERN_INFO "ADC platform data read\n"); ++ return (struct s3c_adc_mach_info*) dev->platform_data; ++ }else{ ++ printk(KERN_INFO "No ADC platform data \n"); ++ return 0; ++ } ++} ++ ++/* ++ * The functions for inserting/removing us as a module. ++ */ ++ ++static int __init s3c_adc_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ struct device *dev; ++ int ret; ++ int size; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ dev = &pdev->dev; ++ ++ if(res == NULL){ ++ dev_err(dev,"no memory resource specified\n"); ++ return -ENOENT; ++ } ++ ++ size = (res->end - res->start) + 1; ++ ++#ifdef ADC_WITH_TOUCHSCREEN ++ adc_mem = request_mem_region(res->start, size, pdev->name); ++ if(adc_mem == NULL){ ++ dev_err(dev, "failed to get memory region\n"); ++ ret = -ENOENT; ++ goto err_req; ++ } ++#endif ++ ++ base_addr = ioremap(res->start, size); ++ if(base_addr == NULL){ ++ dev_err(dev,"fail to ioremap() region\n"); ++ ret = -ENOENT; ++ goto err_map; ++ } ++ ++ adc_clock = clk_get(&pdev->dev, "adc"); ++ ++ if(IS_ERR(adc_clock)){ ++ dev_err(dev,"failed to fine ADC clock source\n"); ++ ret = PTR_ERR(adc_clock); ++ goto err_clk; ++ } ++ ++ clk_enable(adc_clock); ++ ++ /* read platform data from device struct */ ++ plat_data = s3c_adc_get_platdata(&pdev->dev); ++ ++ if ((plat_data->presc & 0xff) > 0) ++ writel(S3C_ADCCON_PRSCEN | S3C_ADCCON_PRSCVL(plat_data->presc & 0xff), base_addr + S3C_ADCCON); ++ else ++ writel(0, base_addr + S3C_ADCCON); ++ ++ /* Initialise registers */ ++ if ((plat_data->delay & 0xffff) > 0) ++ writel(plat_data->delay & 0xffff, base_addr + S3C_ADCDLY); ++ ++ if (plat_data->resolution == 12) ++ writel(readl(base_addr + S3C_ADCCON) | S3C_ADCCON_RESSEL_12BIT, base_addr + S3C_ADCCON); ++ ++ ret = misc_register(&s3c_adc_miscdev); ++ if (ret) { ++ printk (KERN_ERR "cannot register miscdev on minor=%d (%d)\n", ++ ADC_MINOR, ret); ++ goto err_clk; ++ } ++ ++ printk(KERN_INFO "S5P64XX ADC driver successfully probed\n"); ++ ++ return 0; ++ ++err_clk: ++ clk_disable(adc_clock); ++ clk_put(adc_clock); ++ ++err_map: ++ iounmap(base_addr); ++ ++err_req: ++ release_resource(adc_mem); ++ kfree(adc_mem); ++ ++ return ret; ++} ++ ++ ++static int s3c_adc_remove(struct platform_device *dev) ++{ ++ printk(KERN_INFO "s3c_adc_remove() of ADC called !\n"); ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static unsigned int adccon, adctsc, adcdly; ++ ++static int s3c_adc_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ adccon = readl(base_addr + S3C_ADCCON); ++ adctsc = readl(base_addr + S3C_ADCTSC); ++ adcdly = readl(base_addr + S3C_ADCDLY); ++ ++ clk_disable(adc_clock); ++ ++ return 0; ++} ++ ++static int s3c_adc_resume(struct platform_device *pdev) ++{ ++ clk_enable(adc_clock); ++ ++ writel(adccon, base_addr + S3C_ADCCON); ++ writel(adctsc, base_addr + S3C_ADCTSC); ++ writel(adcdly, base_addr + S3C_ADCDLY); ++ ++ return 0; ++} ++#else ++#define s3c_adc_suspend NULL ++#define s3c_adc_resume NULL ++#endif ++ ++static struct platform_driver s3c_adc_driver = { ++ .probe = s3c_adc_probe, ++ .remove = s3c_adc_remove, ++ .suspend = s3c_adc_suspend, ++ .resume = s3c_adc_resume, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "s3c-adc", ++ }, ++}; ++ ++static char banner[] __initdata = KERN_INFO "S5P64XX ADC driver, (c) 2007 Samsung Electronics\n"; ++ ++int __init s3c_adc_init(void) ++{ ++ printk(banner); ++ return platform_driver_register(&s3c_adc_driver); ++} ++ ++void __exit s3c_adc_exit(void) ++{ ++ platform_driver_unregister(&s3c_adc_driver); ++} ++ ++module_init(s3c_adc_init); ++module_exit(s3c_adc_exit); ++ ++MODULE_AUTHOR("boyko.lee@samsung.com"); ++MODULE_DESCRIPTION("S5P64XX ADC driver"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/bootmem.c linux-2.6.28.6/arch/arm/plat-s5p64xx/bootmem.c +--- linux-2.6.28/arch/arm/plat-s5p64xx/bootmem.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/bootmem.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,115 @@ ++/* linux/arch/arm/plat-s5p64xx/bootmem.c ++ * ++ * Copyright 2009 Samsung Electronics ++ * Jinsung Yang ++ * http://samsungsemi.com/ ++ * ++ * Bootmem helper functions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "plat/media.h" ++ ++static struct s3c_media_device s3c_mdevs[S3C_MDEV_MAX] = { ++ { ++ .id = S3C_MDEV_POST, ++ .name = "post", ++ ++#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_POST ++ .memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_POST * SZ_1K, ++#else ++ .memsize = 0, ++#endif ++ .paddr = 0, ++ }, ++}; ++ ++static struct s3c_media_device *s3c_get_media_device(int dev_id) ++{ ++ struct s3c_media_device *mdev = NULL; ++ int i, found; ++ ++ if (dev_id < 0 || dev_id >= S3C_MDEV_MAX) ++ return NULL; ++ ++ i = 0; ++ found = 0; ++ while (!found && (i < S3C_MDEV_MAX)) { ++ mdev = &s3c_mdevs[i]; ++ if (mdev->id == dev_id) ++ found = 1; ++ else ++ i++; ++ } ++ ++ if (!found) ++ mdev = NULL; ++ ++ return mdev; ++} ++ ++dma_addr_t s3c_get_media_memory(int dev_id) ++{ ++ struct s3c_media_device *mdev; ++ ++ mdev = s3c_get_media_device(dev_id); ++ if (!mdev){ ++ printk(KERN_ERR "invalid media device\n"); ++ return 0; ++ } ++ ++ if (!mdev->paddr) { ++ printk(KERN_ERR "no memory for %s\n", mdev->name); ++ return 0; ++ } ++ ++ return mdev->paddr; ++} ++ ++size_t s3c_get_media_memsize(int dev_id) ++{ ++ struct s3c_media_device *mdev; ++ ++ mdev = s3c_get_media_device(dev_id); ++ if (!mdev){ ++ printk(KERN_ERR "invalid media device\n"); ++ return 0; ++ } ++ ++ return mdev->memsize; ++} ++ ++void s3c64xx_reserve_bootmem(void) ++{ ++ struct s3c_media_device *mdev; ++ int i; ++ ++ for(i = 0; i < sizeof(s3c_mdevs) / sizeof(s3c_mdevs[0]); i++) { ++ mdev = &s3c_mdevs[i]; ++ if (mdev->memsize > 0) { ++ mdev->paddr = virt_to_phys(alloc_bootmem_low(mdev->memsize)); ++ printk(KERN_INFO \ ++ "s3c64xx: %lu bytes SDRAM reserved " ++ "for %s at 0x%08x\n", ++ (unsigned long) mdev->memsize, \ ++ mdev->name, mdev->paddr); ++ } ++ } ++} ++ ++/* FIXME: temporary implementation to avoid compile error */ ++int dma_needs_bounce(struct device *dev, dma_addr_t addr, size_t size) ++{ ++ return 0; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/clock.c linux-2.6.28.6/arch/arm/plat-s5p64xx/clock.c +--- linux-2.6.28/arch/arm/plat-s5p64xx/clock.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/clock.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,448 @@ ++/* linux/arch/arm/plat-s5p64xx/clock.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5P64XX Base clock support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++/* definition for cpu freq */ ++ ++#define ARM_PLL_CON S3C_APLL_CON ++#define ARM_CLK_DIV S3C_CLK_DIV0 ++ ++#define ARM_DIV_RATIO_BIT 0 ++#define ARM_DIV_MASK (0xf<> 16) & 0x3ff; ++ p = (apll_con >> 8) & 0x3f; ++ s = apll_con & 0x3; ++ ++ ret = (m * (INIT_XTAL / (p * (1 << s)))); ++ ++ return (ret / (clk_div0_tmp + 1)); ++} ++ ++unsigned long s3c_fclk_round_rate(struct clk *clk, unsigned long rate) ++{ ++ u32 iter; ++ ++ for(iter = 1 ; iter < ARRAY_SIZE(s3c_cpu_clock_table) ; iter++){ ++ if(rate > s3c_cpu_clock_table[iter][0]) ++ return s3c_cpu_clock_table[iter-1][0]; ++ } ++ ++ return s3c_cpu_clock_table[ARRAY_SIZE(s3c_cpu_clock_table) - 1][0]; ++} ++ ++int s3c_fclk_set_rate(struct clk *clk, unsigned long rate) ++{ ++ u32 round_tmp; ++ u32 iter; ++ u32 clk_div0_tmp,tmp,flag; ++ u32 cur_clk = s3c_fclk_get_rate(); ++ ++ round_tmp = s3c_fclk_round_rate(clk,rate); ++ ++ if(round_tmp == cur_clk) ++ return 0; ++ ++ ++ for (iter = 0 ; iter < ARRAY_SIZE(s3c_cpu_clock_table) ; iter++){ ++ if(round_tmp == s3c_cpu_clock_table[iter][0]) ++ break; ++ } ++ ++ if(iter >= ARRAY_SIZE(s3c_cpu_clock_table)) ++ iter = ARRAY_SIZE(s3c_cpu_clock_table) - 1; ++ ++ tmp = 0x1000; ++#if 0 ++ if(cur_clk > round_tmp) { ++ clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK); ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ ++ : : "r" (clk_div0_tmp) : "memory"); ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ ++ : : "r" (clk_div0_tmp) : "memory"); ++ do { ++ tmp--; ++ if(tmp == 0x800) { ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ ++ : : "r" (clk_div0_tmp) : "memory"); ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ ++ : : "r" (clk_div0_tmp) : "memory"); ++ ++ clk_div0_tmp |= s3c_cpu_clock_table[iter][1]; ++ __raw_writel(clk_div0_tmp, ARM_CLK_DIV); ++ ++ clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(HCLK_DIV_MASK); ++ clk_div0_tmp |= s3c_cpu_clock_table[iter][2]; ++ __raw_writel(clk_div0_tmp, ARM_CLK_DIV); ++ } ++ if(tmp <= 0) ++ break; ++ } while(1); ++ ++ } else { ++ ++ clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(HCLK_DIV_MASK); ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ ++ : : "r" (clk_div0_tmp) : "memory"); ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ ++ : : "r" (clk_div0_tmp) : "memory"); ++ do { ++ tmp--; ++ if(tmp == 0x800) { ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ ++ : : "r" (clk_div0_tmp) : "memory"); ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ ++ : : "r" (clk_div0_tmp) : "memory"); ++ clk_div0_tmp |= s3c_cpu_clock_table[iter][2]; ++ __raw_writel(clk_div0_tmp, ARM_CLK_DIV); ++ ++ clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK); ++ clk_div0_tmp |= s3c_cpu_clock_table[iter][1]; ++ __raw_writel(clk_div0_tmp, ARM_CLK_DIV); ++ } ++ if(tmp <= 0) ++ break; ++ } while(1); ++ } ++#else ++ local_irq_save(flag); ++ clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK); ++ clk_div0_tmp |= s3c_cpu_clock_table[iter][1]; ++ clk_div0_tmp &= ~(HCLK_DIV_MASK); ++ clk_div0_tmp |= s3c_cpu_clock_table[iter][2]; ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ ++ : : "r" (clk_div0_tmp) : "memory"); ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ ++ : : "r" (clk_div0_tmp) : "memory"); ++ do { ++ tmp--; ++ if(tmp == 0xC00) { ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ ++ : : "r" (clk_div0_tmp) : "memory"); ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ ++ : : "r" (clk_div0_tmp) : "memory"); ++ ++ __raw_writel(clk_div0_tmp, ARM_CLK_DIV); ++ } ++ if(tmp <= 0) ++ break; ++ } while(1); ++ ++#endif ++ local_irq_restore(flag); ++ printk("ARM_CLK:%d, iter:%d\n",round_tmp,iter); ++ ++ clk->rate = s3c_cpu_clock_table[iter][0]; ++ ++ return 0; ++} ++ ++struct clk clk_cpu = { ++ .name = "clk_cpu", ++ .id = -1, ++ .rate = 0, ++ .parent = &clk_mpll, ++ .ctrlbit = 0, ++ .set_rate = s3c_fclk_set_rate, ++ .round_rate = s3c_fclk_round_rate, ++}; ++ ++static int inline s5p64xx_gate(void __iomem *reg, ++ struct clk *clk, ++ int enable) ++{ ++ unsigned int ctrlbit = clk->ctrlbit; ++ u32 con; ++ ++ con = __raw_readl(reg); ++ ++ if (enable) ++ con |= ctrlbit; ++ else ++ con &= ~ctrlbit; ++ ++ __raw_writel(con, reg); ++ return 0; ++} ++ ++static int s5p64xx_pclk_ctrl(struct clk *clk, int enable) ++{ ++ return s5p64xx_gate(S3C_CLK_GATE_PCLK, clk, enable); ++} ++ ++static int s5p64xx_hclk_ctrl(struct clk *clk, int enable) ++{ ++ return s5p64xx_gate(S3C_CLK_GATE_HCLK0, clk, enable); ++} ++ ++int s5p64xx_sclk_ctrl(struct clk *clk, int enable) ++{ ++ return s5p64xx_gate(S3C_CLK_GATE_SCLK0, clk, enable); ++} ++ ++static struct clk init_clocks_disable[] = { ++ { ++ .name = "nand", ++ .id = -1, ++ .parent = &clk_h, ++ }, { ++ .name = "adc", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5p64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_TSADC, ++ }, { ++ .name = "i2c", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5p64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_IIC0, ++ }, { ++ .name = "iis_v40", ++ .id = 0, ++ .parent = &clk_p, ++ .enable = s5p64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_IIS2, ++ }, { ++ .name = "spi", ++ .id = 0, ++ .parent = &clk_p, ++ .enable = s5p64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_SPI0, ++ }, { ++ .name = "spi", ++ .id = 1, ++ .parent = &clk_p, ++ .enable = s5p64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_SPI1, ++ }, { ++ .name = "48m", ++ .id = 0, ++ .parent = &clk_48m, ++ .enable = s5p64xx_sclk_ctrl, ++ .ctrlbit = S3C_CLKCON_SCLK0_MMC0_48, ++ }, { ++ .name = "48m", ++ .id = 1, ++ .parent = &clk_48m, ++ .enable = s5p64xx_sclk_ctrl, ++ .ctrlbit = S3C_CLKCON_SCLK0_MMC1_48, ++ }, { ++ .name = "48m", ++ .id = 2, ++ .parent = &clk_48m, ++ .enable = s5p64xx_sclk_ctrl, ++ .ctrlbit = S3C_CLKCON_SCLK0_MMC2_48, ++ }, { ++ .name = "otg", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s5p64xx_hclk_ctrl, ++ .ctrlbit = S3C_CLKCON_HCLK0_USB ++ }, { ++ .name = "post", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s5p64xx_hclk_ctrl, ++ .ctrlbit = S3C_CLKCON_HCLK0_POST0 ++ }, ++ ++}; ++ ++static struct clk init_clocks[] = { ++ { ++ .name = "lcd", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s5p64xx_hclk_ctrl, ++ .ctrlbit = S3C_CLKCON_HCLK1_DISPCON, ++ }, { ++ .name = "gpio", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5p64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_GPIO, ++ }, { ++ .name = "hsmmc", ++ .id = 0, ++ .parent = &clk_h, ++ .enable = s5p64xx_hclk_ctrl, ++ .ctrlbit = S3C_CLKCON_HCLK0_HSMMC0, ++ }, { ++ .name = "hsmmc", ++ .id = 1, ++ .parent = &clk_h, ++ .enable = s5p64xx_hclk_ctrl, ++ .ctrlbit = S3C_CLKCON_HCLK0_HSMMC1, ++ }, { ++ .name = "hsmmc", ++ .id = 2, ++ .parent = &clk_h, ++ .enable = s5p64xx_hclk_ctrl, ++ .ctrlbit = S3C_CLKCON_HCLK0_HSMMC2, ++ }, { ++ .name = "timers", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5p64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_PWM, ++ }, { ++ .name = "uart", ++ .id = 0, ++ .parent = &clk_p, ++ .enable = s5p64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_UART0, ++ }, { ++ .name = "uart", ++ .id = 1, ++ .parent = &clk_p, ++ .enable = s5p64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_UART1, ++ }, { ++ .name = "uart", ++ .id = 2, ++ .parent = &clk_p, ++ .enable = s5p64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_UART2, ++ }, { ++ .name = "uart", ++ .id = 3, ++ .parent = &clk_p, ++ .enable = s5p64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_UART3, ++ }, { ++ .name = "rtc", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5p64xx_pclk_ctrl, ++ .ctrlbit = S3C_CLKCON_PCLK_RTC, ++ }, { ++ .name = "watchdog", ++ .id = -1, ++ .parent = &clk_p, ++ .ctrlbit = S3C_CLKCON_PCLK_WDT, ++ } ++}; ++ ++static struct clk *clks[] __initdata = { ++ &clk_ext, ++ &clk_epll, ++ &clk_27m, ++ &clk_48m, ++ &clk_cpu, ++}; ++ ++void __init s5p64xx_register_clocks(void) ++{ ++ struct clk *clkp; ++ int ret; ++ int ptr; ++ ++ s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); ++ ++ clkp = init_clocks; ++ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { ++ ret = s3c24xx_register_clock(clkp); ++ if (ret < 0) { ++ printk(KERN_ERR "Failed to register clock %s (%d)\n", ++ clkp->name, ret); ++ } ++ } ++ ++ clkp = init_clocks_disable; ++ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { ++ ++ ret = s3c24xx_register_clock(clkp); ++ if (ret < 0) { ++ printk(KERN_ERR "Failed to register clock %s (%d)\n", ++ clkp->name, ret); ++ } ++ ++ (clkp->enable)(clkp, 0); ++ } ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/cpu.c linux-2.6.28.6/arch/arm/plat-s5p64xx/cpu.c +--- linux-2.6.28/arch/arm/plat-s5p64xx/cpu.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/cpu.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,106 @@ ++/* linux/arch/arm/plat-s5p64xx/cpu.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5P64XX CPU Support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++/* table of supported CPUs */ ++ ++static const char name_s5p6440[] = "S5P6440"; ++ ++static struct cpu_table cpu_ids[] __initdata = { ++ { ++ .idcode = 0x56440100, ++ .idmask = 0xffffff00, ++ .map_io = s5p6440_map_io, ++ .init_clocks = s5p6440_init_clocks, ++ .init_uarts = s5p6440_init_uarts, ++ .init = s5p6440_init, ++ .name = name_s5p6440, ++ }, ++}; ++ ++/* minimal IO mapping */ ++ ++/* see notes on uart map in arch/arm/mach-s5p6440/include/mach/debug-macro.S */ ++#define UART_OFFS (S3C_PA_UART & 0xfffff) ++ ++static struct map_desc s3c_iodesc[] __initdata = { ++ { ++ .virtual = (unsigned long)S3C_VA_SYS, ++ .pfn = __phys_to_pfn(S5P64XX_PA_SYSCON), ++ .length = SZ_4K, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = (unsigned long)(S3C_VA_UART + UART_OFFS), ++ .pfn = __phys_to_pfn(S3C_PA_UART), ++ .length = SZ_4K, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = (unsigned long)S3C_VA_VIC0, ++ .pfn = __phys_to_pfn(S5P64XX_PA_VIC0), ++ .length = SZ_16K, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = (unsigned long)S3C_VA_VIC1, ++ .pfn = __phys_to_pfn(S5P64XX_PA_VIC1), ++ .length = SZ_16K, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = (unsigned long)S3C_VA_TIMER, ++ .pfn = __phys_to_pfn(S3C_PA_TIMER), ++ .length = SZ_16K, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = (unsigned long)S5P64XX_VA_GPIO, ++ .pfn = __phys_to_pfn(S5P64XX_PA_GPIO), ++ .length = SZ_4K, ++ .type = MT_DEVICE, ++ }, ++}; ++ ++/* read cpu identification code */ ++ ++void __init s5p64xx_init_io(struct map_desc *mach_desc, int size) ++{ ++ unsigned long idcode; ++ ++ /* initialise the io descriptors we need for initialisation */ ++ iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); ++ iotable_init(mach_desc, size); ++ ++ idcode = __raw_readl(S3C_SYS_ID); ++ s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/dev-post.c linux-2.6.28.6/arch/arm/plat-s5p64xx/dev-post.c +--- linux-2.6.28/arch/arm/plat-s5p64xx/dev-post.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/dev-post.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,66 @@ ++/* linux/arch/arm/plat-s5p64xx/dev-post.c ++ * ++ * Copyright 2009 Samsung Electronics ++ * Jinsung Yang ++ * http://samsungsemi.com/ ++ * ++ * S5P64XX series device definition for post processor ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++ ++static struct resource s3c_post_resource[] = { ++ [0] = { ++ .start = S5P64XX_PA_POST, ++ .end = S5P64XX_PA_POST + S5P64XX_SZ_POST - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_POST0, ++ .end = IRQ_POST0, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++struct platform_device s3c_device_post = { ++ .name = "s3c-post", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_post_resource), ++ .resource = s3c_post_resource, ++}; ++ ++static struct s3c_platform_post default_post_data __initdata = { ++ .clk_name = "post", ++ .clockrate = 133000000, ++ .line_length = 1280, ++ .nr_frames = 4, ++}; ++ ++void __init s3c_post_set_platdata(struct s3c_platform_post *pd) ++{ ++ struct s3c_platform_post *npd; ++ ++ if (!pd) ++ pd = &default_post_data; ++ ++ npd = kmemdup(pd, sizeof(struct s3c_platform_post), GFP_KERNEL); ++ if (!npd) ++ printk(KERN_ERR "%s: no memory for platform data\n", __func__); ++ else if (!npd->cfg_gpio) ++ npd->cfg_gpio = s3c_post_cfg_gpio; ++ ++ s3c_device_post.dev.platform_data = npd; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/dev-uart.c linux-2.6.28.6/arch/arm/plat-s5p64xx/dev-uart.c +--- linux-2.6.28/arch/arm/plat-s5p64xx/dev-uart.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/dev-uart.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,176 @@ ++/* linux/arch/arm/plat-s5p64xx/dev-uart.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * Base S5P64XX UART resource and device definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++/* Serial port registrations */ ++ ++/* 64xx uarts are closer together */ ++ ++static struct resource s5p64xx_uart0_resource[] = { ++ [0] = { ++ .start = S3C_PA_UART0, ++ .end = S3C_PA_UART0 + S3C_SZ_UART, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_S3CUART_RX0, ++ .end = IRQ_S3CUART_RX0, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = IRQ_S3CUART_TX0, ++ .end = IRQ_S3CUART_TX0, ++ .flags = IORESOURCE_IRQ, ++ ++ }, ++ [3] = { ++ .start = IRQ_S3CUART_ERR0, ++ .end = IRQ_S3CUART_ERR0, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct resource s5p64xx_uart1_resource[] = { ++ [0] = { ++ .start = S3C_PA_UART1, ++ .end = S3C_PA_UART1 + S3C_SZ_UART, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_S3CUART_RX1, ++ .end = IRQ_S3CUART_RX1, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = IRQ_S3CUART_TX1, ++ .end = IRQ_S3CUART_TX1, ++ .flags = IORESOURCE_IRQ, ++ ++ }, ++ [3] = { ++ .start = IRQ_S3CUART_ERR1, ++ .end = IRQ_S3CUART_ERR1, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct resource s5p64xx_uart2_resource[] = { ++ [0] = { ++ .start = S3C_PA_UART2, ++ .end = S3C_PA_UART2 + S3C_SZ_UART, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_S3CUART_RX2, ++ .end = IRQ_S3CUART_RX2, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = IRQ_S3CUART_TX2, ++ .end = IRQ_S3CUART_TX2, ++ .flags = IORESOURCE_IRQ, ++ ++ }, ++ [3] = { ++ .start = IRQ_S3CUART_ERR2, ++ .end = IRQ_S3CUART_ERR2, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct resource s5p64xx_uart3_resource[] = { ++ [0] = { ++ .start = S3C_PA_UART3, ++ .end = S3C_PA_UART3 + S3C_SZ_UART, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_S3CUART_RX3, ++ .end = IRQ_S3CUART_RX3, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = IRQ_S3CUART_TX3, ++ .end = IRQ_S3CUART_TX3, ++ .flags = IORESOURCE_IRQ, ++ ++ }, ++ [3] = { ++ .start = IRQ_S3CUART_ERR3, ++ .end = IRQ_S3CUART_ERR3, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++ ++struct s3c24xx_uart_resources s5p64xx_uart_resources[] __initdata = { ++ [0] = { ++ .resources = s5p64xx_uart0_resource, ++ .nr_resources = ARRAY_SIZE(s5p64xx_uart0_resource), ++ }, ++ [1] = { ++ .resources = s5p64xx_uart1_resource, ++ .nr_resources = ARRAY_SIZE(s5p64xx_uart1_resource), ++ }, ++ [2] = { ++ .resources = s5p64xx_uart2_resource, ++ .nr_resources = ARRAY_SIZE(s5p64xx_uart2_resource), ++ }, ++ [3] = { ++ .resources = s5p64xx_uart3_resource, ++ .nr_resources = ARRAY_SIZE(s5p64xx_uart3_resource), ++ }, ++}; ++ ++/* uart devices */ ++ ++static struct platform_device s3c24xx_uart_device0 = { ++ .id = 0, ++}; ++ ++static struct platform_device s3c24xx_uart_device1 = { ++ .id = 1, ++}; ++ ++static struct platform_device s3c24xx_uart_device2 = { ++ .id = 2, ++}; ++ ++static struct platform_device s3c24xx_uart_device3 = { ++ .id = 3, ++}; ++ ++struct platform_device *s3c24xx_uart_src[4] = { ++ &s3c24xx_uart_device0, ++ &s3c24xx_uart_device1, ++ &s3c24xx_uart_device2, ++ &s3c24xx_uart_device3, ++}; ++ ++struct platform_device *s3c24xx_uart_devs[4] = { ++}; ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/devs.c linux-2.6.28.6/arch/arm/plat-s5p64xx/devs.c +--- linux-2.6.28/arch/arm/plat-s5p64xx/devs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/devs.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,303 @@ ++/* linux/arch/arm/plat-s5p64xx/devs.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * Base S5P64XX resource and device definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++/* SMC9115 LAN via ROM interface */ ++ ++static struct resource s3c_smc911x_resources[] = { ++ [0] = { ++ .start = S5P64XX_PA_SMC9115, ++ .end = S5P64XX_PA_SMC9115 + S5P64XX_SZ_SMC9115 - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_EINT(10), ++ .end = IRQ_EINT(10), ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++struct platform_device s3c_device_smc911x = { ++ .name = "smc911x", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_smc911x_resources), ++ .resource = s3c_smc911x_resources, ++}; ++ ++/* NAND Controller */ ++ ++static struct resource s3c_nand_resource[] = { ++ [0] = { ++ .start = S5P64XX_PA_NAND, ++ .end = S5P64XX_PA_NAND + S5P64XX_SZ_NAND - 1, ++ .flags = IORESOURCE_MEM, ++ } ++}; ++ ++struct platform_device s3c_device_nand = { ++ .name = "s3c-nand", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_nand_resource), ++ .resource = s3c_nand_resource, ++}; ++ ++EXPORT_SYMBOL(s3c_device_nand); ++ ++/* USB Device (Gadget)*/ ++ ++static struct resource s3c_usbgadget_resource[] = { ++ [0] = { ++ .start = S3C_PA_OTG, ++ .end = S3C_PA_OTG + S3C_SZ_OTG - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_OTG, ++ .end = IRQ_OTG, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++struct platform_device s3c_device_usbgadget = { ++ .name = "s3c-usbgadget", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_usbgadget_resource), ++ .resource = s3c_usbgadget_resource, ++}; ++ ++EXPORT_SYMBOL(s3c_device_usbgadget); ++ ++/* USB Device (OTG hcd)*/ ++ ++static struct resource s3c_usb_otghcd_resource[] = { ++ [0] = { ++ .start = S3C_PA_OTG, ++ .end = S3C_PA_OTG + S3C_SZ_OTG - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_OTG, ++ .end = IRQ_OTG, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static u64 s3c_device_usb_otghcd_dmamask = 0xffffffffUL; ++ ++struct platform_device s3c_device_usb_otghcd = { ++ .name = "s3c_otghcd", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_usb_otghcd_resource), ++ .resource = s3c_usb_otghcd_resource, ++ .dev = { ++ .dma_mask = &s3c_device_usb_otghcd_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ ++EXPORT_SYMBOL(s3c_device_usb_otghcd); ++ ++/* SPI (0) */ ++static struct resource s3c_spi0_resource[] = { ++ [0] = { ++ .start = S3C_PA_SPI0, ++ .end = S3C_PA_SPI0 + S3C_SZ_SPI0 - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_SPI0, ++ .end = IRQ_SPI0, ++ .flags = IORESOURCE_IRQ, ++ } ++ ++}; ++ ++static u64 s3c_device_spi0_dmamask = 0xffffffffUL; ++ ++struct platform_device s3c_device_spi0 = { ++ .name = "sam-spi", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(s3c_spi0_resource), ++ .resource = s3c_spi0_resource, ++ .dev = { ++ .dma_mask = &s3c_device_spi0_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++EXPORT_SYMBOL(s3c_device_spi0); ++ ++/* SPI (1) */ ++static struct resource s3c_spi1_resource[] = { ++ [0] = { ++ .start = S3C_PA_SPI1, ++ .end = S3C_PA_SPI1 + S3C_SZ_SPI1 - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_SPI1, ++ .end = IRQ_SPI1, ++ .flags = IORESOURCE_IRQ, ++ } ++ ++}; ++ ++static u64 s3c_device_spi1_dmamask = 0xffffffffUL; ++ ++struct platform_device s3c_device_spi1 = { ++ .name = "sam-spi", ++ .id = 1, ++ .num_resources = ARRAY_SIZE(s3c_spi1_resource), ++ .resource = s3c_spi1_resource, ++ .dev = { ++ .dma_mask = &s3c_device_spi1_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++EXPORT_SYMBOL(s3c_device_spi1); ++ ++/* LCD Controller */ ++ ++static struct resource s3c_lcd_resource[] = { ++ [0] = { ++ .start = S5P64XX_PA_LCD, ++ .end = S5P64XX_PA_LCD + SZ_1M - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_DISPCON1, ++ .end = IRQ_DISPCON2, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static u64 s3c_device_lcd_dmamask = 0xffffffffUL; ++ ++struct platform_device s3c_device_lcd = { ++ .name = "s3c-lcd", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_lcd_resource), ++ .resource = s3c_lcd_resource, ++ .dev = { ++ .dma_mask = &s3c_device_lcd_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ ++/* ADC */ ++static struct resource s3c_adc_resource[] = { ++ [0] = { ++ .start = S3C_PA_ADC, ++ .end = S3C_PA_ADC + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_PENDN, ++ .end = IRQ_PENDN, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = IRQ_ADC, ++ .end = IRQ_ADC, ++ .flags = IORESOURCE_IRQ, ++ } ++ ++}; ++ ++struct platform_device s3c_device_adc = { ++ .name = "s3c-adc", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_adc_resource), ++ .resource = s3c_adc_resource, ++}; ++ ++void __init s3c_adc_set_platdata(struct s3c_adc_mach_info *pd) ++{ ++ struct s3c_adc_mach_info *npd; ++ ++ npd = kmalloc(sizeof(*npd), GFP_KERNEL); ++ if (npd) { ++ memcpy(npd, pd, sizeof(*npd)); ++ s3c_device_adc.dev.platform_data = npd; ++ } else { ++ printk(KERN_ERR "no memory for ADC platform data\n"); ++ } ++} ++ ++static struct resource s3c_rtc_resource[] = { ++ [0] = { ++ .start = S3C_PA_RTC, ++ .end = S3C_PA_RTC + 0xff, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_RTC_ALARM, ++ .end = IRQ_RTC_ALARM, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = IRQ_RTC_TIC, ++ .end = IRQ_RTC_TIC, ++ .flags = IORESOURCE_IRQ ++ } ++}; ++ ++struct platform_device s3c_device_rtc = { ++ .name = "s3c2410-rtc", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_rtc_resource), ++ .resource = s3c_rtc_resource, ++}; ++ ++EXPORT_SYMBOL(s3c_device_rtc); ++ ++/* Watchdog */ ++static struct resource s3c_wdt_resource[] = { ++ [0] = { ++ .start = S5P64XX_PA_WATCHDOG, ++ .end = S5P64XX_PA_WATCHDOG + S5P64XX_SZ_WATCHDOG - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_WDT, ++ .end = IRQ_WDT, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++struct platform_device s3c_device_wdt = { ++ .name = "s3c2410-wdt", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_wdt_resource), ++ .resource = s3c_wdt_resource, ++}; ++ ++EXPORT_SYMBOL(s3c_device_wdt); ++ ++ ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/gpiolib.c linux-2.6.28.6/arch/arm/plat-s5p64xx/gpiolib.c +--- linux-2.6.28/arch/arm/plat-s5p64xx/gpiolib.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/gpiolib.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,372 @@ ++/* arch/arm/plat-s5p64xx/gpiolib.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5P64XX - GPIOlib support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++/* GPIO bank summary: ++ * ++ * Bank GPIOs Style SlpCon ExtInt Group ++ * A 8 4Bit Yes 1 ++ * B 7 4Bit Yes 1 ++ * C 8 4Bit Yes 2 ++ * D 5 4Bit Yes 3 ++ * E 5 4Bit Yes None ++ * F 16 2Bit Yes 4 [1] ++ * G 7 4Bit Yes 5 ++ * H 10 4Bit[2] Yes 6 ++ * I 16 2Bit Yes None ++ * J 12 2Bit Yes None ++ * K 16 4Bit[2] No None ++ * L 15 4Bit[2] No None ++ * M 6 4Bit No IRQ_EINT ++ * N 16 2Bit No IRQ_EINT ++ * O 16 2Bit Yes 7 ++ * P 15 2Bit Yes 8 ++ * Q 9 2Bit Yes 9 ++ * ++ * [1] BANKF pins 14,15 do not form part of the external interrupt sources ++ * [2] BANK has two control registers, GPxCON0 and GPxCON1 ++ */ ++ ++#define OFF_GPCON (0x00) ++#define OFF_GPDAT (0x04) ++ ++#define con_4bit_shift(__off) ((__off) * 4) ++ ++#if 1 ++#define gpio_dbg(x...) do { } while(0) ++#else ++#define gpio_dbg(x...) printk(KERN_DEBUG ## x) ++#endif ++ ++/* The s5p64xx_gpiolib_4bit routines are to control the gpio banks where ++ * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the ++ * following example: ++ * ++ * base + 0x00: Control register, 4 bits per gpio ++ * gpio n: 4 bits starting at (4*n) ++ * 0000 = input, 0001 = output, others mean special-function ++ * base + 0x04: Data register, 1 bit per gpio ++ * bit n: data bit n ++ * ++ * Note, since the data register is one bit per gpio and is at base + 0x4 ++ * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of ++ * the output. ++*/ ++ ++static int s5p64xx_gpiolib_4bit_input(struct gpio_chip *chip, unsigned offset) ++{ ++ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); ++ void __iomem *base = ourchip->base; ++ unsigned long con; ++ ++ con = __raw_readl(base + OFF_GPCON); ++ con &= ~(0xf << con_4bit_shift(offset)); ++ __raw_writel(con, base + OFF_GPCON); ++ ++ gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con); ++ ++ return 0; ++} ++ ++static int s5p64xx_gpiolib_4bit_output(struct gpio_chip *chip, ++ unsigned offset, int value) ++{ ++ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); ++ void __iomem *base = ourchip->base; ++ unsigned long con; ++ unsigned long dat; ++ ++ con = __raw_readl(base + OFF_GPCON); ++ con &= ~(0xf << con_4bit_shift(offset)); ++ con |= 0x1 << con_4bit_shift(offset); ++ ++ dat = __raw_readl(base + OFF_GPDAT); ++ if (value) ++ dat |= 1 << offset; ++ else ++ dat &= ~(1 << offset); ++ ++ __raw_writel(dat, base + OFF_GPDAT); ++ __raw_writel(con, base + OFF_GPCON); ++ __raw_writel(dat, base + OFF_GPDAT); ++ ++ gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); ++ ++ return 0; ++} ++ ++/* The next set of routines are for the case where the GPIO configuration ++ * registers are 4 bits per GPIO but there is more than one register (the ++ * bank has more than 8 GPIOs. ++ * ++ * This case is the similar to the 4 bit case, but the registers are as ++ * follows: ++ * ++ * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs) ++ * gpio n: 4 bits starting at (4*n) ++ * 0000 = input, 0001 = output, others mean special-function ++ * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs) ++ * gpio n: 4 bits starting at (4*n) ++ * 0000 = input, 0001 = output, others mean special-function ++ * base + 0x08: Data register, 1 bit per gpio ++ * bit n: data bit n ++ * ++ * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we ++ * store the 'base + 0x4' address so that these routines see the data ++ * register at ourchip->base + 0x04. ++*/ ++ ++static int s5p64xx_gpiolib_4bit2_input(struct gpio_chip *chip, unsigned offset) ++{ ++ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); ++ void __iomem *base = ourchip->base; ++ void __iomem *regcon = base; ++ unsigned long con; ++ ++ if (offset > 7) ++ offset -= 8; ++ else ++ regcon -= 4; ++ ++ con = __raw_readl(regcon); ++ con &= ~(0xf << con_4bit_shift(offset)); ++ __raw_writel(con, regcon); ++ ++ gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con); ++ ++ return 0; ++ ++} ++ ++static int s5p64xx_gpiolib_4bit2_output(struct gpio_chip *chip, ++ unsigned offset, int value) ++{ ++ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); ++ void __iomem *base = ourchip->base; ++ void __iomem *regcon = base; ++ unsigned long con; ++ unsigned long dat; ++ ++ if (offset > 7) ++ offset -= 8; ++ else ++ regcon -= 4; ++ ++ con = __raw_readl(regcon); ++ con &= ~(0xf << con_4bit_shift(offset)); ++ con |= 0x1 << con_4bit_shift(offset); ++ ++ dat = __raw_readl(base + OFF_GPDAT); ++ if (value) ++ dat |= 1 << offset; ++ else ++ dat &= ~(1 << offset); ++ ++ __raw_writel(dat, base + OFF_GPDAT); ++ __raw_writel(con, regcon); ++ __raw_writel(dat, base + OFF_GPDAT); ++ ++ gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); ++ ++ return 0; ++} ++ ++static struct s3c_gpio_cfg gpio_4bit_cfg_noint = { ++ .set_config = s3c_gpio_setcfg_s3c64xx_4bit, ++ .set_pull = s3c_gpio_setpull_updown, ++ .get_pull = s3c_gpio_getpull_updown, ++}; ++ ++static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = { ++ .cfg_eint = 7, ++ .set_config = s3c_gpio_setcfg_s3c64xx_4bit, ++ .set_pull = s3c_gpio_setpull_updown, ++ .get_pull = s3c_gpio_getpull_updown, ++}; ++ ++static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = { ++ .cfg_eint = 3, ++ .set_config = s3c_gpio_setcfg_s3c64xx_4bit, ++ .set_pull = s3c_gpio_setpull_updown, ++ .get_pull = s3c_gpio_getpull_updown, ++}; ++ ++static struct s3c_gpio_chip gpio_4bit[] = { ++ { ++ .base = S5P64XX_GPA_BASE, ++ .config = &gpio_4bit_cfg_eint0111, ++ .chip = { ++ .base = S5P64XX_GPA(0), ++ .ngpio = S5P64XX_GPIO_A_NR, ++ .label = "GPA", ++ }, ++ }, { ++ .base = S5P64XX_GPB_BASE, ++ .config = &gpio_4bit_cfg_eint0111, ++ .chip = { ++ .base = S5P64XX_GPB(0), ++ .ngpio = S5P64XX_GPIO_B_NR, ++ .label = "GPB", ++ }, ++ }, { ++ .base = S5P64XX_GPC_BASE, ++ .config = &gpio_4bit_cfg_eint0111, ++ .chip = { ++ .base = S5P64XX_GPC(0), ++ .ngpio = S5P64XX_GPIO_C_NR, ++ .label = "GPC", ++ }, ++ }, { ++ .base = S5P64XX_GPG_BASE, ++ .config = &gpio_4bit_cfg_eint0111, ++ .chip = { ++ .base = S5P64XX_GPG(0), ++ .ngpio = S5P64XX_GPIO_G_NR, ++ .label = "GPG", ++ }, ++ }, ++}; ++ ++static struct s3c_gpio_chip gpio_4bit2[] = { ++ { ++ .base = S5P64XX_GPH_BASE + 0x4, ++ .config = &gpio_4bit_cfg_eint0111, ++ .chip = { ++ .base = S5P64XX_GPH(0), ++ .ngpio = S5P64XX_GPIO_H_NR, ++ .label = "GPH", ++ }, ++ }, { ++ .base = S5P64XX_GPR_BASE + 0x4, ++ .config = &gpio_4bit_cfg_eint0011, ++ .chip = { ++ .base = S5P64XX_GPR(0), ++ .ngpio = S5P64XX_GPIO_R_NR, ++ .label = "GPR", ++ }, ++ }, ++}; ++ ++static struct s3c_gpio_cfg gpio_2bit_cfg_noint = { ++ .set_config = s3c_gpio_setcfg_s3c24xx, ++ .set_pull = s3c_gpio_setpull_updown, ++ .get_pull = s3c_gpio_getpull_updown, ++}; ++ ++static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = { ++ .cfg_eint = 2, ++ .set_config = s3c_gpio_setcfg_s3c24xx, ++ .set_pull = s3c_gpio_setpull_updown, ++ .get_pull = s3c_gpio_getpull_updown, ++}; ++ ++static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = { ++ .cfg_eint = 3, ++ .set_config = s3c_gpio_setcfg_s3c24xx, ++ .set_pull = s3c_gpio_setpull_updown, ++ .get_pull = s3c_gpio_getpull_updown, ++}; ++ ++static struct s3c_gpio_chip gpio_2bit[] = { ++ { ++ .base = S5P64XX_GPF_BASE, ++ .config = &gpio_2bit_cfg_eint11, ++ .chip = { ++ .base = S5P64XX_GPF(0), ++ .ngpio = S5P64XX_GPIO_F_NR, ++ .label = "GPF", ++ }, ++ }, { ++ .base = S5P64XX_GPI_BASE, ++ .config = &gpio_2bit_cfg_noint, ++ .chip = { ++ .base = S5P64XX_GPI(0), ++ .ngpio = S5P64XX_GPIO_I_NR, ++ .label = "GPI", ++ }, ++ }, { ++ .base = S5P64XX_GPJ_BASE, ++ .config = &gpio_2bit_cfg_noint, ++ .chip = { ++ .base = S5P64XX_GPJ(0), ++ .ngpio = S5P64XX_GPIO_J_NR, ++ .label = "GPJ", ++ }, ++ }, { ++ .base = S5P64XX_GPN_BASE, ++ .config = &gpio_2bit_cfg_eint10, ++ .chip = { ++ .base = S5P64XX_GPN(0), ++ .ngpio = S5P64XX_GPIO_N_NR, ++ .label = "GPN", ++ }, ++ }, { ++ .base = S5P64XX_GPP_BASE, ++ .config = &gpio_2bit_cfg_eint11, ++ .chip = { ++ .base = S5P64XX_GPP(0), ++ .ngpio = S5P64XX_GPIO_P_NR, ++ .label = "GPP", ++ }, ++ }, ++}; ++ ++static __init void s5p64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip) ++{ ++ chip->chip.direction_input = s5p64xx_gpiolib_4bit_input; ++ chip->chip.direction_output = s5p64xx_gpiolib_4bit_output; ++} ++ ++static __init void s5p64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip) ++{ ++ chip->chip.direction_input = s5p64xx_gpiolib_4bit2_input; ++ chip->chip.direction_output = s5p64xx_gpiolib_4bit2_output; ++} ++ ++static __init void s5p64xx_gpiolib_add(struct s3c_gpio_chip *chips, ++ int nr_chips, ++ void (*fn)(struct s3c_gpio_chip *)) ++{ ++ for (; nr_chips > 0; nr_chips--, chips++) { ++ if (fn) ++ (fn)(chips); ++ s3c_gpiolib_add(chips); ++ } ++} ++ ++static __init int s5p64xx_gpiolib_init(void) ++{ ++ s5p64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit), ++ s5p64xx_gpiolib_add_4bit); ++ ++ s5p64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2), ++ s5p64xx_gpiolib_add_4bit2); ++ ++ s5p64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), NULL); ++ ++ return 0; ++} ++ ++arch_initcall(s5p64xx_gpiolib_init); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/dma.h linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/dma.h +--- linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/dma.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/dma.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,12 @@ ++/* linux/arch/arm/plat-s5p64xx/include/plat/dma.h ++ * ++ * Copyright (C) 2006 Simtec Electronics ++ * Ben Dooks ++ * ++ * Samsung S5P64XX DMA support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++#include +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/gpio-bank-a.h linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/gpio-bank-a.h +--- linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/gpio-bank-a.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/gpio-bank-a.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,42 @@ ++/* linux/arch/arm/plat-s5p64xx/include/plat/gpio-bank-a.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank A register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5P64XX_GPACON (S5P64XX_GPA_BASE + 0x00) ++#define S5P64XX_GPADAT (S5P64XX_GPA_BASE + 0x04) ++#define S5P64XX_GPAPUD (S5P64XX_GPA_BASE + 0x08) ++#define S5P64XX_GPACONSLP (S5P64XX_GPA_BASE + 0x0c) ++#define S5P64XX_GPAPUDSLP (S5P64XX_GPA_BASE + 0x10) ++ ++#define S5P64XX_GPA_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5P64XX_GPA_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5P64XX_GPA_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5P64XX_GPA0_UART_RXD0 (0x02 << 0) ++#define S5P64XX_GPA0_EINT_G1_0 (0x07 << 0) ++ ++#define S5P64XX_GPA1_UART_TXD0 (0x02 << 4) ++#define S5P64XX_GPA1_EINT_G1_1 (0x07 << 4) ++ ++#define S5P64XX_GPA2_UART_nCTS0 (0x02 << 8) ++#define S5P64XX_GPA2_EINT_G1_2 (0x07 << 8) ++ ++#define S5P64XX_GPA3_UART_nRTS0 (0x02 << 12) ++#define S5P64XX_GPA3_EINT_G1_3 (0x07 << 12) ++ ++#define S5P64XX_GPA4_UART_RXD1 (0x02 << 16) ++#define S5P64XX_GPA4_EINT_G1_4 (0x07 << 16) ++ ++#define S5P64XX_GPA5_UART_TXD1 (0x02 << 20) ++#define S5P64XX_GPA5_EINT_G1_5 (0x07 << 20) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/gpio-bank-b.h linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/gpio-bank-b.h +--- linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/gpio-bank-b.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/gpio-bank-b.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,49 @@ ++/* linux/arch/arm/plat-s5p64xx/include/plat/gpio-bank-b.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank B register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5P64XX_GPBCON (S5P64XX_GPB_BASE + 0x00) ++#define S5P64XX_GPBDAT (S5P64XX_GPB_BASE + 0x04) ++#define S5P64XX_GPBPUD (S5P64XX_GPB_BASE + 0x08) ++#define S5P64XX_GPBCONSLP (S5P64XX_GPB_BASE + 0x0c) ++#define S5P64XX_GPBPUDSLP (S5P64XX_GPB_BASE + 0x10) ++ ++#define S5P64XX_GPB_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5P64XX_GPB_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5P64XX_GPB_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5P64XX_GPB0_UART_RXD2 (0x02 << 0) ++#define S5P64XX_GPB0_EINT_G1_8 (0x07 << 0) ++ ++#define S5P64XX_GPB1_UART_TXD2 (0x02 << 4) ++#define S5P64XX_GPB1_EINT_G1_9 (0x07 << 4) ++ ++#define S5P64XX_GPB2_UART_RXD3 (0x02 << 8) ++#define S5P64XX_GPB2_I2C_SCL1 (0x06 << 8) ++#define S5P64XX_GPB2_EINT_G1_10 (0x07 << 8) ++ ++#define S5P64XX_GPB3_UART_TXD3 (0x02 << 12) ++#define S5P64XX_GPB3_I2C_SDA1 (0x06 << 12) ++#define S5P64XX_GPB3_EINT_G1_11 (0x07 << 12) ++ ++#define S5P64XX_GPB4_ts_ERROR (0x06 << 16) ++#define S5P64XX_GPB4_EINT_G1_12 (0x07 << 16) ++ ++#define S5P64XX_GPB5_I2C_SCL0 (0x02 << 20) ++#define S5P64XX_GPB5_UART_nCTS1 (0x03 << 20) ++#define S5P64XX_GPB5_EINT_G1_13 (0x07 << 20) ++ ++#define S5P64XX_GPB6_I2C_SDA0 (0x02 << 24) ++#define S5P64XX_GPB6_UART_nRTS1 (0x03 << 24) ++#define S5P64XX_GPB6_EINT_G1_14 (0x07 << 24) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/gpio-bank-c.h linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/gpio-bank-c.h +--- linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/gpio-bank-c.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/gpio-bank-c.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,57 @@ ++/* linux/arch/arm/plat-s5p64xx/include/plat/gpio-bank-c.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank C register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5P64XX_GPCCON (S5P64XX_GPC_BASE + 0x00) ++#define S5P64XX_GPCDAT (S5P64XX_GPC_BASE + 0x04) ++#define S5P64XX_GPCPUD (S5P64XX_GPC_BASE + 0x08) ++#define S5P64XX_GPCCONSLP (S5P64XX_GPC_BASE + 0x0c) ++#define S5P64XX_GPCPUDSLP (S5P64XX_GPC_BASE + 0x10) ++ ++#define S5P64XX_GPC_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5P64XX_GPC_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5P64XX_GPC_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5P64XX_GPC0_SPI_MISO0 (0x02 << 0) ++#define S5P64XX_GPC0_ts_CLK (0x03 << 0) ++#define S5P64XX_GPC0_EINT_G2_0 (0x07 << 0) ++ ++#define S5P64XX_GPC1_SPI_CLK0 (0x02 << 4) ++#define S5P64XX_GPC1_ts_SYNC (0x03 << 4) ++#define S5P64XX_GPC1_EINT_G2_1 (0x07 << 4) ++ ++#define S5P64XX_GPC2_SPI_MOSI0 (0x02 << 8) ++#define S5P64XX_GPC2_ts_VALID (0x03 << 8) ++#define S5P64XX_GPC2_EINT_G2_2 (0x07 << 8) ++ ++#define S5P64XX_GPC3_SPI_nCS0 (0x02 << 12) ++#define S5P64XX_GPC3_ts_DATA (0x03 << 12) ++#define S5P64XX_GPC3_EINT_G2_3 (0x07 << 12) ++ ++#define S5P64XX_GPC4_SPI_MISO1 (0x02 << 16) ++#define S5P64XX_GPC4_MMC2_CMD (0x03 << 16) ++#define S5P64XX_GPC4_I2S_V40_DO0 (0x05 << 16) ++#define S5P64XX_GPC4_EINT_G2_4 (0x07 << 16) ++ ++#define S5P64XX_GPC5_SPI_CLK1 (0x02 << 20) ++#define S5P64XX_GPC5_MMC2_CLK (0x03 << 20) ++#define S5P64XX_GPC5_I2S_V40_DO1 (0x05 << 20) ++#define S5P64XX_GPC5_EINT_G2_5 (0x07 << 20) ++ ++#define S5P64XX_GPC6_SPI_MOSI1 (0x02 << 24) ++#define S5P64XX_GPC6_EINT_G2_6 (0x07 << 24) ++ ++#define S5P64XX_GPC7_SPI_nCS1 (0x02 << 28) ++#define S5P64XX_GPC7_I2S_V40_DO2 (0x05 << 28) ++#define S5P64XX_GPC7_EINT_G2_7 (0x07 << 28) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/gpio-bank-f.h linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/gpio-bank-f.h +--- linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/gpio-bank-f.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/gpio-bank-f.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,28 @@ ++/* linux/arch/arm/plat-s5p64xx/include/plat/gpio-bank-f.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank F register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5P64XX_GPFCON (S5P64XX_GPF_BASE + 0x00) ++#define S5P64XX_GPFDAT (S5P64XX_GPF_BASE + 0x04) ++#define S5P64XX_GPFPUD (S5P64XX_GPF_BASE + 0x08) ++#define S5P64XX_GPFCONSLP (S5P64XX_GPF_BASE + 0x0c) ++#define S5P64XX_GPFPUDSLP (S5P64XX_GPF_BASE + 0x10) ++ ++#define S5P64XX_GPF_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) ++#define S5P64XX_GPF_INPUT(__gpio) (0x0 << ((__gpio) * 2)) ++#define S5P64XX_GPF_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) ++ ++#define S5P64XX_GPF14_PWM_TOUT0 (0x02 << 28) ++ ++#define S5P64XX_GPF15_PWM_TOUT1 (0x02 << 30) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/gpio-bank-g.h linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/gpio-bank-g.h +--- linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/gpio-bank-g.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/gpio-bank-g.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,45 @@ ++/* linux/arch/arm/plat-s5p64xx/include/plat/gpio-bank-g.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank G register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5P64XX_GPGCON (S5P64XX_GPG_BASE + 0x00) ++#define S5P64XX_GPGDAT (S5P64XX_GPG_BASE + 0x04) ++#define S5P64XX_GPGPUD (S5P64XX_GPG_BASE + 0x08) ++#define S5P64XX_GPGCONSLP (S5P64XX_GPG_BASE + 0x0c) ++#define S5P64XX_GPGPUDSLP (S5P64XX_GPG_BASE + 0x10) ++ ++#define S5P64XX_GPG_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5P64XX_GPG_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5P64XX_GPG_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5P64XX_GPG0_MMC0_CLK (0x02 << 0) ++#define S5P64XX_GPG0_EINT_G5_0 (0x07 << 0) ++ ++#define S5P64XX_GPG1_MMC0_CMD (0x02 << 4) ++#define S5P64XX_GPG1_EINT_G5_1 (0x07 << 4) ++ ++#define S5P64XX_GPG2_MMC0_DATA0 (0x02 << 8) ++#define S5P64XX_GPG2_EINT_G5_2 (0x07 << 8) ++ ++#define S5P64XX_GPG3_MMC0_DATA1 (0x02 << 12) ++#define S5P64XX_GPG3_EINT_G5_3 (0x07 << 12) ++ ++#define S5P64XX_GPG4_MMC0_DATA2 (0x02 << 16) ++#define S5P64XX_GPG4_EINT_G5_4 (0x07 << 16) ++ ++#define S5P64XX_GPG5_MMC0_DATA3 (0x02 << 20) ++#define S5P64XX_GPG5_EINT_G5_5 (0x07 << 20) ++ ++#define S5P64XX_GPG6_MMC0_CDn (0x02 << 24) ++#define S5P64XX_GPG6_MMC1_CDn (0x03 << 24) ++#define S5P64XX_GPG6_EINT_G5_6 (0x07 << 24) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/gpio-bank-h.h linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/gpio-bank-h.h +--- linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/gpio-bank-h.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/gpio-bank-h.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,63 @@ ++/* linux/arch/arm/plat-s5p64xx/include/plat/gpio-bank-h.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank H register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5P64XX_GPHCON0 (S5P64XX_GPH_BASE + 0x00) ++#define S5P64XX_GPHCON1 (S5P64XX_GPH_BASE + 0x04) ++#define S5P64XX_GPHDAT (S5P64XX_GPH_BASE + 0x08) ++#define S5P64XX_GPHPUD (S5P64XX_GPH_BASE + 0x0c) ++#define S5P64XX_GPHCONSLP (S5P64XX_GPH_BASE + 0x10) ++#define S5P64XX_GPHPUDSLP (S5P64XX_GPH_BASE + 0x14) ++ ++#define S5P64XX_GPH_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5P64XX_GPH_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5P64XX_GPH_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5P64XX_GPH0_MMC1_CLK (0x02 << 0) ++#define S5P64XX_GPH0_EINT_G6_0 (0x07 << 0) ++ ++#define S5P64XX_GPH1_MMC1_CMD (0x02 << 4) ++#define S5P64XX_GPH1_EINT_G6_1 (0x07 << 4) ++ ++#define S5P64XX_GPH2_MMC1_DATA0 (0x02 << 8) ++#define S5P64XX_GPH2_EINT_G6_2 (0x07 << 8) ++ ++#define S5P64XX_GPH3_MMC1_DATA1 (0x02 << 12) ++#define S5P64XX_GPH3_EINT_G6_3 (0x07 << 12) ++ ++#define S5P64XX_GPH4_MMC1_DATA2 (0x02 << 16) ++#define S5P64XX_GPH4_EINT_G6_4 (0x07 << 16) ++ ++#define S5P64XX_GPH5_MMC1_DATA3 (0x02 << 20) ++#define S5P64XX_GPH5_EINT_G6_5 (0x07 << 20) ++ ++#define S5P64XX_GPH6_MMC1_DATA4 (0x02 << 24) ++#define S5P64XX_GPH6_MMC2_DATA0 (0x03 << 24) ++#define S5P64XX_GPH6_I2S_V40_BCLK (0x05 << 24) ++#define S5P64XX_GPH6_EINT_G6_6 (0x07 << 24) ++ ++#define S5P64XX_GPH7_MMC1_DATA5 (0x02 << 28) ++#define S5P64XX_GPH7_MMC2_DATA1 (0x03 << 28) ++#define S5P64XX_GPH7_I2S_V40_CDCLK (0x05 << 28) ++#define S5P64XX_GPH7_EINT_G6_7 (0x07 << 28) ++ ++#define S5P64XX_GPH8_MMC1_DATA6 (0x02 << 0) ++#define S5P64XX_GPH8_MMC2_DATA2 (0x03 << 0) ++#define S5P64XX_GPH8_I2S_V40_LRCLK (0x05 << 0) ++#define S5P64XX_GPH8_EINT_G6_8 (0x07 << 0) ++ ++#define S5P64XX_GPH9_MMC1_DATA7 (0x02 << 4) ++#define S5P64XX_GPH9_MMC2_DATA3 (0x03 << 4) ++#define S5P64XX_GPH9_I2S_V40_DI (0x05 << 4) ++#define S5P64XX_GPH9_EINT_G6_9 (0x07 << 4) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/gpio-bank-i.h linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/gpio-bank-i.h +--- linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/gpio-bank-i.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/gpio-bank-i.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,71 @@ ++/* linux/arch/arm/plat-s5p64xx/include/plat/gpio-bank-i.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank I register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5P64XX_GPICON (S5P64XX_GPI_BASE + 0x00) ++#define S5P64XX_GPIDAT (S5P64XX_GPI_BASE + 0x04) ++#define S5P64XX_GPIPUD (S5P64XX_GPI_BASE + 0x08) ++#define S5P64XX_GPICONSLP (S5P64XX_GPI_BASE + 0x0c) ++#define S5P64XX_GPIPUDSLP (S5P64XX_GPI_BASE + 0x10) ++ ++#define S5P64XX_GPI_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) ++#define S5P64XX_GPI_INPUT(__gpio) (0x0 << ((__gpio) * 2)) ++#define S5P64XX_GPI_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) ++ ++#define S5P64XX_GPI0_VD0 (0x02 << 0) ++#define S5P64XX_GPI0_EXTSRAM_DATA0 (0x03 << 0) ++ ++#define S5P64XX_GPI1_VD1 (0x02 << 2) ++#define S5P64XX_GPI1_EXTSRAM_DATA1 (0x03 << 2) ++ ++#define S5P64XX_GPI2_VD2 (0x02 << 4) ++#define S5P64XX_GPI2_EXTSRAM_DATA2 (0x03 << 4) ++ ++#define S5P64XX_GPI3_VD3 (0x02 << 6) ++#define S5P64XX_GPI3_EXTSRAM_DATA3 (0x03 << 6) ++ ++#define S5P64XX_GPI4_VD4 (0x02 << 8) ++#define S5P64XX_GPI4_EXTSRAM_DATA4 (0x03 << 8) ++ ++#define S5P64XX_GPI5_VD5 (0x02 << 10) ++#define S5P64XX_GPI5_EXTSRAM_DATA5 (0x03 << 10) ++ ++#define S5P64XX_GPI6_VD6 (0x02 << 12) ++#define S5P64XX_GPI6_EXTSRAM_DATA6 (0x03 << 12) ++ ++#define S5P64XX_GPI7_VD7 (0x02 << 14) ++#define S5P64XX_GPI7_EXTSRAM_DATA7 (0x03 << 14) ++ ++#define S5P64XX_GPI8_VD8 (0x02 << 16) ++#define S5P64XX_GPI8_EXTSRAM_DATA8 (0x03 << 16) ++ ++#define S5P64XX_GPI9_VD9 (0x02 << 18) ++#define S5P64XX_GPI9_EXTSRAM_DATA9 (0x03 << 18) ++ ++#define S5P64XX_GPI10_VD10 (0x02 << 20) ++#define S5P64XX_GPI10_EXTSRAM_DATA10 (0x03 << 20) ++ ++#define S5P64XX_GPI11_VD11 (0x02 << 22) ++#define S5P64XX_GPI11_EXTSRAM_DATA11 (0x03 << 22) ++ ++#define S5P64XX_GPI12_VD12 (0x02 << 24) ++#define S5P64XX_GPI12_EXTSRAM_DATA12 (0x03 << 24) ++ ++#define S5P64XX_GPI13_VD13 (0x02 << 26) ++#define S5P64XX_GPI13_EXTSRAM_DATA13 (0x03 << 26) ++ ++#define S5P64XX_GPI14_VD14 (0x02 << 28) ++#define S5P64XX_GPI14_EXTSRAM_DATA14 (0x03 << 28) ++ ++#define S5P64XX_GPI15_VD15 (0x02 << 30) ++#define S5P64XX_GPI15_EXTSRAM_DATA15 (0x03 << 30) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/gpio-bank-j.h linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/gpio-bank-j.h +--- linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/gpio-bank-j.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/gpio-bank-j.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,59 @@ ++/* linux/arch/arm/plat-s5p64xx/include/plat/gpio-bank-j.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank J register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5P64XX_GPJCON (S5P64XX_GPJ_BASE + 0x00) ++#define S5P64XX_GPJDAT (S5P64XX_GPJ_BASE + 0x04) ++#define S5P64XX_GPJPUD (S5P64XX_GPJ_BASE + 0x08) ++#define S5P64XX_GPJCONSLP (S5P64XX_GPJ_BASE + 0x0c) ++#define S5P64XX_GPJPUDSLP (S5P64XX_GPJ_BASE + 0x10) ++ ++#define S5P64XX_GPJ_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) ++#define S5P64XX_GPJ_INPUT(__gpio) (0x0 << ((__gpio) * 2)) ++#define S5P64XX_GPJ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) ++ ++#define S5P64XX_GPJ0_VD16 (0x02 << 0) ++#define S5P64XX_GPJ0_EXTSRAM_nCS (0x03 << 0) ++ ++#define S5P64XX_GPJ1_VD17 (0x02 << 2) ++#define S5P64XX_GPJ1_EXTSRAM_nOE (0x03 << 2) ++ ++#define S5P64XX_GPJ2_VD18 (0x02 << 4) ++#define S5P64XX_GPJ2_EXTSRAM_nWE (0x03 << 4) ++ ++#define S5P64XX_GPJ3_VD19 (0x02 << 6) ++#define S5P64XX_GPJ3_EXTSRAM_nBE0 (0x03 << 6) ++ ++#define S5P64XX_GPJ4_VD20 (0x02 << 8) ++#define S5P64XX_GPJ4_EXTSRAM_nBE1 (0x03 << 8) ++ ++#define S5P64XX_GPJ5_VD21 (0x02 << 10) ++#define S5P64XX_GPJ5_EXTSRAM_ADDR1 (0x03 << 10) ++ ++#define S5P64XX_GPJ6_VD22 (0x02 << 12) ++#define S5P64XX_GPJ6_EXTSRAM_ADDR2 (0x03 << 12) ++ ++#define S5P64XX_GPJ7_VD23 (0x02 << 14) ++#define S5P64XX_GPJ7_EXTSRAM_ADDR3 (0x03 << 14) ++ ++#define S5P64XX_GPJ8_LCD_HSYNC (0x02 << 16) ++#define S5P64XX_GPJ8_EXTSRAM_ADDR4 (0x03 << 16) ++ ++#define S5P64XX_GPJ9_LCD_VSYNC (0x02 << 18) ++#define S5P64XX_GPJ9_EXTSRAM_ADDR5 (0x03 << 18) ++ ++#define S5P64XX_GPJ10_LCD_VDEN (0x02 << 20) ++#define S5P64XX_GPJ10_EXTSRAM_ADDR6 (0x03 << 20) ++ ++#define S5P64XX_GPJ11_LCD_VCLK (0x02 << 22) ++#define S5P64XX_GPJ11_EXTSRAM_ADDR7 (0x03 << 22) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/gpio-bank-n.h linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/gpio-bank-n.h +--- linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/gpio-bank-n.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/gpio-bank-n.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,38 @@ ++/* linux/arch/arm/plat-s5p64xx/include/plat/gpio-bank-n.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank N register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5P64XX_GPNCON (S5P64XX_GPN_BASE + 0x00) ++#define S5P64XX_GPNDAT (S5P64XX_GPN_BASE + 0x04) ++#define S5P64XX_GPNPUD (S5P64XX_GPN_BASE + 0x08) ++ ++#define S5P64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) ++#define S5P64XX_GPN_INPUT(__gpio) (0x0 << ((__gpio) * 2)) ++#define S5P64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) ++ ++#define S5P64XX_GPN0_EINT0 (0x02 << 0) ++#define S5P64XX_GPN1_EINT1 (0x02 << 2) ++#define S5P64XX_GPN2_EINT2 (0x02 << 4) ++#define S5P64XX_GPN3_EINT3 (0x02 << 6) ++#define S5P64XX_GPN4_EINT4 (0x02 << 8) ++#define S5P64XX_GPN5_EINT5 (0x02 << 10) ++#define S5P64XX_GPN6_EINT6 (0x02 << 12) ++#define S5P64XX_GPN7_EINT7 (0x02 << 14) ++#define S5P64XX_GPN8_EINT8 (0x02 << 16) ++#define S5P64XX_GPN9_EINT9 (0x02 << 18) ++#define S5P64XX_GPN10_EINT10 (0x02 << 20) ++#define S5P64XX_GPN11_EINT11 (0x02 << 22) ++#define S5P64XX_GPN12_EINT12 (0x02 << 24) ++#define S5P64XX_GPN13_EINT13 (0x02 << 26) ++#define S5P64XX_GPN14_EINT14 (0x02 << 28) ++#define S5P64XX_GPN15_EINT15 (0x02 << 30) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/gpio-bank-p.h linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/gpio-bank-p.h +--- linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/gpio-bank-p.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/gpio-bank-p.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,45 @@ ++/* linux/arch/arm/plat-s5p64xx/include/plat/gpio-bank-p.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank P register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5P64XX_GPPCON (S5P64XX_GPP_BASE + 0x00) ++#define S5P64XX_GPPDAT (S5P64XX_GPP_BASE + 0x04) ++#define S5P64XX_GPPPUD (S5P64XX_GPP_BASE + 0x08) ++#define S5P64XX_GPPCONSLP (S5P64XX_GPP_BASE + 0x0c) ++#define S5P64XX_GPPPUDSLP (S5P64XX_GPP_BASE + 0x10) ++#define S5P64XX_GPPCON_GPS (S5P64XX_GPP_BASE + 0x14) ++ ++#define S5P64XX_GPP_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) ++#define S5P64XX_GPP_INPUT(__gpio) (0x0 << ((__gpio) * 2)) ++#define S5P64XX_GPP_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) ++ ++#define S5P64XX_GPP3_MEM0_ALE (0x02 << 6) ++#define S5P64XX_GPP3_EINT_G8_3 (0x03 << 6) ++ ++#define S5P64XX_GPP4_MEM0_CLE (0x02 << 8) ++#define S5P64XX_GPP4_EINT_G8_4 (0x03 << 8) ++ ++#define S5P64XX_GPP5_MEM0_FWE (0x02 << 10) ++#define S5P64XX_GPP5_EINT_G8_5 (0x03 << 10) ++ ++#define S5P64XX_GPP6_MEM0_FRE (0x02 << 12) ++#define S5P64XX_GPP6_EINT_G8_6 (0x03 << 12) ++ ++#define S5P64XX_GPP7_MEM0_RnB (0x02 << 14) ++#define S5P64XX_GPP7_EINT_G8_7 (0x03 << 14) ++ ++#define S5P64XX_GPP8_EINT_G8_8 (0x03 << 16) ++ ++#define S5P64XX_GPP9_EINT_G8_9 (0x03 << 18) ++ ++#define S5P64XX_GPP10_EINT_G8_10 (0x03 << 20) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/gpio-bank-r.h linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/gpio-bank-r.h +--- linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/gpio-bank-r.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/gpio-bank-r.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,51 @@ ++/* linux/arch/arm/plat-s5p64xx/include/plat/gpio-bank-r.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank R register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5P64XX_GPRCON0 (S5P64XX_GPR_BASE + 0x00) ++#define S5P64XX_GPRCON1 (S5P64XX_GPR_BASE + 0x04) ++#define S5P64XX_GPRDAT (S5P64XX_GPR_BASE + 0x08) ++#define S5P64XX_GPRPUD (S5P64XX_GPR_BASE + 0x0c) ++#define S5P64XX_GPRCONSLP (S5P64XX_GPR_BASE + 0x10) ++#define S5P64XX_GPRPUDSLP (S5P64XX_GPR_BASE + 0x14) ++ ++#define S5P64XX_GPR_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5P64XX_GPR_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5P64XX_GPR_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5P64XX_GPR4_I2S_V40_DO0 (0x05 << 16) ++ ++#define S5P64XX_GPR5_I2S_V40_DO1 (0x05 << 20) ++ ++#define S5P64XX_GPR6_PCM_SOUT (0x02 << 28) ++#define S5P64XX_GPR6_I2S_V40_DO2 (0x05 << 28) ++ ++#define S5P64XX_GPR7_PCM_DCLK (0x02 << 0) ++#define S5P64XX_GPR7_I2S_V40_LRCLK (0x05 << 0) ++ ++#define S5P64XX_GPR8_PCM_SIN (0x02 << 4) ++#define S5P64XX_GPR8_I2S_V40_DI (0x05 << 4) ++ ++#define S5P64XX_GPR9_I2C_SCL1 (0x06 << 8) ++ ++#define S5P64XX_GPR10_I2C_SDA1 (0x06 << 12) ++ ++#define S5P64XX_GPR11_MMC2_CMD (0x03 << 16) ++ ++#define S5P64XX_GPR12_MMC2_CLK (0x03 << 20) ++ ++#define S5P64XX_GPR13_PCM_EXTCLK (0x02 << 24) ++#define S5P64XX_GPR13_I2S_V40_BCLK (0x05 << 24) ++ ++#define S5P64XX_GPR14_PCM_FSYNC (0x02 << 28) ++#define S5P64XX_GPR14_I2S_V40_CDCLK (0x05 << 28) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/irqs.h linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/irqs.h +--- linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/irqs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/irqs.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,170 @@ ++/* linux/arch/arm/plat-s5p64xx/include/plat/irqs.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5P64XX - Common IRQ support ++ */ ++ ++#ifndef __ASM_PLAT_S5P64XX_IRQS_H ++#define __ASM_PLAT_S5P64XX_IRQS_H __FILE__ ++ ++/* we keep the first set of CPU IRQs out of the range of ++ * the ISA space, so that the PC104 has them to itself ++ * and we don't end up having to do horrible things to the ++ * standard ISA drivers.... ++ * ++ * note, since we're using the VICs, our start must be a ++ * mulitple of 32 to allow the common code to work ++ */ ++ ++#define S3C_IRQ_OFFSET (32) ++ ++#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) ++ ++#define S3C_VIC0_BASE S3C_IRQ(0) ++#define S3C_VIC1_BASE S3C_IRQ(32) ++ ++/* UART interrupts, each UART has 4 intterupts per channel so ++ * use the space between the ISA and S3C main interrupts. Note, these ++ * are not in the same order as the S3C24XX series! */ ++ ++#define IRQ_S3CUART_BASE0 (16) ++#define IRQ_S3CUART_BASE1 (20) ++#define IRQ_S3CUART_BASE2 (24) ++#define IRQ_S3CUART_BASE3 (28) ++ ++#define UART_IRQ_RXD (0) ++#define UART_IRQ_ERR (1) ++#define UART_IRQ_TXD (2) ++#define UART_IRQ_MODEM (3) ++ ++#define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD) ++#define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD) ++#define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR) ++ ++#define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD) ++#define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD) ++#define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR) ++ ++#define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD) ++#define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD) ++#define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR) ++ ++#define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD) ++#define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD) ++#define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR) ++ ++/* VIC based IRQs */ ++ ++#define S5P64XX_IRQ_VIC0(x) (S3C_VIC0_BASE + (x)) ++#define S5P64XX_IRQ_VIC1(x) (S3C_VIC1_BASE + (x)) ++ ++/* VIC0 */ ++ ++#define IRQ_EINT0_3 S5P64XX_IRQ_VIC0(0) ++#define IRQ_EINT4_11 S5P64XX_IRQ_VIC0(1) ++#define IRQ_RTC_TIC S5P64XX_IRQ_VIC0(2) ++#define IRQ_IIC1 S5P64XX_IRQ_VIC0(5) ++#define IRQ_IISV40 S5P64XX_IRQ_VIC0(6) ++#define IRQ_GPS S5P64XX_IRQ_VIC0(7) ++#define IRQ_POST0 S5P64XX_IRQ_VIC0(9) ++#define IRQ_2D S5P64XX_IRQ_VIC0(11) ++#define IRQ_TIMER0_VIC S5P64XX_IRQ_VIC0(23) ++#define IRQ_TIMER1_VIC S5P64XX_IRQ_VIC0(24) ++#define IRQ_TIMER2_VIC S5P64XX_IRQ_VIC0(25) ++#define IRQ_WDT S5P64XX_IRQ_VIC0(26) ++#define IRQ_TIMER3_VIC S5P64XX_IRQ_VIC0(27) ++#define IRQ_TIMER4_VIC S5P64XX_IRQ_VIC0(28) ++#define IRQ_DISPCON0 S5P64XX_IRQ_VIC0(29) ++#define IRQ_DISPCON1 S5P64XX_IRQ_VIC0(30) ++#define IRQ_DISPCON2 S5P64XX_IRQ_VIC0(31) ++ ++/* VIC1 */ ++ ++#define IRQ_EINT12_15 S5P64XX_IRQ_VIC1(0) ++#define IRQ_PCM0 S5P64XX_IRQ_VIC1(2) ++#define IRQ_UART0 S5P64XX_IRQ_VIC1(5) ++#define IRQ_UART1 S5P64XX_IRQ_VIC1(6) ++#define IRQ_UART2 S5P64XX_IRQ_VIC1(7) ++#define IRQ_UART3 S5P64XX_IRQ_VIC1(8) ++#define IRQ_DMA0 S5P64XX_IRQ_VIC1(9) ++#define IRQ_NFC S5P64XX_IRQ_VIC1(13) ++#define IRQ_SPI0 S5P64XX_IRQ_VIC1(16) ++#define IRQ_SPI1 S5P64XX_IRQ_VIC1(17) ++#define IRQ_IIC S5P64XX_IRQ_VIC1(18) ++#define IRQ_DISPCON3 S5P64XX_IRQ_VIC1(19) ++#define IRQ_FIMGVG S5P64XX_IRQ_VIC1(20) ++#define IRQ_EINTG1_G9 S5P64XX_IRQ_VIC1(21) ++#define IRQ_PMUIRQ S5P64XX_IRQ_VIC1(23) ++#define IRQ_HSMMC0 S5P64XX_IRQ_VIC1(24) ++#define IRQ_HSMMC1 S5P64XX_IRQ_VIC1(25) ++#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ ++#define IRQ_OTG S5P64XX_IRQ_VIC1(26) ++#define IRQ_DSI S5P64XX_IRQ_VIC1(27) ++#define IRQ_RTC_ALARM S5P64XX_IRQ_VIC1(28) ++#define IRQ_TSI S5P64XX_IRQ_VIC1(29) ++#define IRQ_PENDN S5P64XX_IRQ_VIC1(30) ++#define IRQ_TC IRQ_PENDN ++#define IRQ_ADC S5P64XX_IRQ_VIC1(31) ++ ++#define S5P64XX_TIMER_IRQ(x) S3C_IRQ(64 + (x)) ++ ++#define IRQ_TIMER0 S5P64XX_TIMER_IRQ(0) ++#define IRQ_TIMER1 S5P64XX_TIMER_IRQ(1) ++#define IRQ_TIMER2 S5P64XX_TIMER_IRQ(2) ++#define IRQ_TIMER3 S5P64XX_TIMER_IRQ(3) ++#define IRQ_TIMER4 S5P64XX_TIMER_IRQ(4) ++ ++/* Since the IRQ_EINT(x) are a linear mapping on current s5p64xx series ++ * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE ++ * which we place after the pair of VICs. */ ++ ++#define S3C_IRQ_EINT_BASE S3C_IRQ(64+5) ++ ++#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) ++#define IRQ_EINT(x) S3C_EINT(x) ++ ++/* Next the external interrupt groups. These are similar to the IRQ_EINT(x) ++ * that they are sourced from the GPIO pins but with a different scheme for ++ * priority and source indication. ++ * ++ * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO ++ * interrupts, but for historical reasons they are kept apart from these ++ * next interrupts. ++ * ++ * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the ++ * machine specific support files. ++ */ ++ ++#define IRQ_EINT_GROUP1_NR (15) ++#define IRQ_EINT_GROUP2_NR (8) ++#define IRQ_EINT_GROUP3_NR (5) ++#define IRQ_EINT_GROUP4_NR (14) ++#define IRQ_EINT_GROUP5_NR (7) ++#define IRQ_EINT_GROUP6_NR (10) ++#define IRQ_EINT_GROUP7_NR (16) ++#define IRQ_EINT_GROUP8_NR (15) ++#define IRQ_EINT_GROUP9_NR (9) ++ ++#define IRQ_EINT_GROUP_BASE S3C_EINT(28) ++#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00) ++#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) ++#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) ++#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR) ++#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR) ++#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) ++#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) ++#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR) ++#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR) ++ ++#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##__BASE + (x)) ++ ++/* Set the default NR_IRQS */ ++ ++#define NR_IRQS (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) ++ ++#endif /* __ASM_PLAT_S5P64XX_IRQS_H */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/media.h linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/media.h +--- linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/media.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/media.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,32 @@ ++/* linux/arch/arm/plat-s5p64xx/include/plat/media.h ++ * ++ * Copyright 2009 Samsung Electronics ++ * Jinsung Yang ++ * http://samsungsemi.com/ ++ * ++ * Samsung Media device descriptions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef _S3C_MEDIA_H ++#define _S3C_MEDIA_H ++ ++#include ++ ++#define S3C_MDEV_POST 0 ++#define S3C_MDEV_MAX 1 ++ ++struct s3c_media_device { ++ int id; ++ const char *name; ++ size_t memsize; ++ dma_addr_t paddr; ++}; ++ ++extern dma_addr_t s3c_get_media_memory(int dev_id); ++extern size_t s3c_get_media_memsize(int dev_id); ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/pll.h linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/pll.h +--- linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/pll.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/pll.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,74 @@ ++/* arch/arm/plat-s5p64xx/include/plat/pll.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5P64XX PLL code ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5P6440_PLL_MDIV_MASK ((1 << (25-16+1)) - 1) ++#define S5P6440_PLL_PDIV_MASK ((1 << (13-8+1)) - 1) ++#define S5P6440_PLL_SDIV_MASK ((1 << (2-0+1)) - 1) ++#define S5P6440_PLL_MDIV_SHIFT (16) ++#define S5P6440_PLL_PDIV_SHIFT (8) ++#define S5P6440_PLL_SDIV_SHIFT (0) ++ ++#include ++ ++static inline unsigned long s5p6440_get_pll(unsigned long baseclk, ++ u32 pllcon) ++{ ++ u32 mdiv, pdiv, sdiv; ++ u64 fvco = baseclk; ++ ++ mdiv = (pllcon >> S5P6440_PLL_MDIV_SHIFT) & S5P6440_PLL_MDIV_MASK; ++ pdiv = (pllcon >> S5P6440_PLL_PDIV_SHIFT) & S5P6440_PLL_PDIV_MASK; ++ sdiv = (pllcon >> S5P6440_PLL_SDIV_SHIFT) & S5P6440_PLL_SDIV_MASK; ++ ++ fvco *= mdiv; ++ do_div(fvco, (pdiv << sdiv)); ++ ++ return (unsigned long)fvco; ++} ++ ++#define S5P6440_EPLL_MDIV_MASK ((1 << (23-16+1)) - 1) ++#define S5P6440_EPLL_PDIV_MASK ((1 << (13-8+1)) - 1) ++#define S5P6440_EPLL_SDIV_MASK ((1 << (2-0+1)) - 1) ++#define S5P6440_EPLL_MDIV_SHIFT (16) ++#define S5P6440_EPLL_PDIV_SHIFT (8) ++#define S5P6440_EPLL_SDIV_SHIFT (0) ++#define S5P6440_EPLL_KDIV_MASK (0xffff) ++ ++static inline unsigned long s5p6440_get_epll(unsigned long baseclk) ++{ ++ unsigned long result; ++ u32 epll0 = __raw_readl(S3C_EPLL_CON); ++ u32 epll1 = __raw_readl(S3C_EPLL_CON_K); ++ u32 mdiv, pdiv, sdiv, kdiv; ++ u64 tmp; ++ ++ mdiv = (epll0 >> S5P6440_EPLL_MDIV_SHIFT) & S5P6440_EPLL_MDIV_MASK; ++ pdiv = (epll0 >> S5P6440_EPLL_PDIV_SHIFT) & S5P6440_EPLL_PDIV_MASK; ++ sdiv = (epll0 >> S5P6440_EPLL_SDIV_SHIFT) & S5P6440_EPLL_SDIV_MASK; ++ kdiv = epll1 & S5P6440_EPLL_KDIV_MASK; ++ ++ /* We need to multiple baseclk by mdiv (the integer part) and kdiv ++ * which is in 2^16ths, so shift mdiv up (does not overflow) and ++ * add kdiv before multiplying. The use of tmp is to avoid any ++ * overflows before shifting bac down into result when multipling ++ * by the mdiv and kdiv pair. ++ */ ++ ++ tmp = baseclk; ++ tmp *= (mdiv << 16) + kdiv; ++ do_div(tmp, (pdiv << sdiv)); ++ result = tmp >> 16; ++ ++ return result; ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/pm.h linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/pm.h +--- linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/pm.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/pm.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,82 @@ ++/* linux/include/asm-arm/plat-s3c24xx/pm.h ++ * ++ * Copyright (c) 2004 Simtec Electronics ++ * Written by Ben Dooks, ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++ ++/* s3c2410_pm_init ++ * ++ * called from board at initialisation time to setup the power ++ * management ++*/ ++ ++#ifdef CONFIG_PM ++ ++extern __init int s5p6440_pm_init(void); ++ ++#else ++ ++static inline int s5p6440_pm_init(void) ++{ ++ return 0; ++} ++#endif ++ ++/* configuration for the IRQ mask over sleep */ ++extern unsigned long s3c_irqwake_intmask; ++extern unsigned long s3c_irqwake_eintmask; ++ ++/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */ ++extern unsigned long s3c_irqwake_intallow; ++extern unsigned long s3c_irqwake_eintallow; ++ ++/* per-cpu sleep functions */ ++ ++extern void (*pm_cpu_prep)(void); ++extern void (*pm_cpu_sleep)(void); ++ ++/* Flags for PM Control */ ++ ++extern unsigned long s3c_pm_flags; ++ ++/* from sleep.S */ ++ ++extern int s5p6440_cpu_save(unsigned long *saveblk); ++extern void s5p6440_cpu_suspend(void); ++extern void s5p6440_cpu_resume(void); ++ ++extern unsigned long s5p6440_sleep_save_phys; ++ ++/* sleep save info */ ++ ++struct sleep_save { ++ void __iomem *reg; ++ unsigned long val; ++}; ++ ++struct sleep_save_phy { ++ unsigned long reg; ++ unsigned long val; ++}; ++ ++#define SAVE_ITEM(x) \ ++ { .reg = (x) } ++ ++extern void s5p6440_pm_do_save_phy(struct sleep_save_phy *ptr, int count); ++extern void s5p6440_pm_do_restore_phy(struct sleep_save_phy *ptr, int count); ++extern void s5p6440_pm_do_save(struct sleep_save *ptr, int count); ++extern void s5p6440_pm_do_restore(struct sleep_save *ptr, int count); ++ ++#ifdef CONFIG_PM ++extern int s3c64xx_irq_suspend(struct sys_device *dev, pm_message_t state); ++extern int s3c64xx_irq_resume(struct sys_device *dev); ++#else ++#define s3c64xx_irq_suspend NULL ++#define s3c64xx_irq_resume NULL ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/post.h linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/post.h +--- linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/post.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/post.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,33 @@ ++/* linux/arch/arm/plat-s5p64xx/include/plat/post.h ++ * ++ * Platform header file for Samsung Post Processor driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _POST_H ++#define _POST_H ++ ++struct platform_device; ++ ++struct s3c_platform_post { ++ const char clk_name[16]; ++ u32 clockrate; ++ int line_length; ++ int nr_frames; ++ ++ void (*cfg_gpio)(struct platform_device *dev); ++}; ++ ++extern void s3c_post_set_platdata(struct s3c_platform_post *post); ++ ++/* defined by architecture to configure gpio */ ++extern void s3c_post_cfg_gpio(struct platform_device *dev); ++ ++#endif /* _POST_H */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/regs-clock.h linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/regs-clock.h +--- linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/regs-clock.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/regs-clock.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,212 @@ ++/* arch/arm/plat-s5p64xx/include/plat/regs-clock.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5P64XX clock register definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __PLAT_REGS_CLOCK_H ++#define __PLAT_REGS_CLOCK_H __FILE__ ++ ++#define S3C_CLKREG(x) (S3C_VA_SYS + (x)) ++ ++#define S3C_APLL_LOCK S3C_CLKREG(0x00) ++#define S3C_MPLL_LOCK S3C_CLKREG(0x04) ++#define S3C_EPLL_LOCK S3C_CLKREG(0x08) ++#define S3C_APLL_CON S3C_CLKREG(0x0C) ++#define S3C_MPLL_CON S3C_CLKREG(0x10) ++#define S3C_EPLL_CON S3C_CLKREG(0x14) ++#define S3C_EPLL_CON_K S3C_CLKREG(0x18) ++#define S3C_CLK_SRC0 S3C_CLKREG(0x1C) ++#define S3C_CLK_DIV0 S3C_CLKREG(0x20) ++#define S3C_CLK_DIV1 S3C_CLKREG(0x24) ++#define S3C_CLK_DIV2 S3C_CLKREG(0x28) ++#define S3C_CLK_OUT S3C_CLKREG(0x2C) ++#define S3C_CLK_GATE_HCLK0 S3C_CLKREG(0x30) ++#define S3C_CLK_GATE_PCLK S3C_CLKREG(0x34) ++#define S3C_CLK_GATE_SCLK0 S3C_CLKREG(0x38) ++#define S3C_CLK_GATE_MEM0 S3C_CLKREG(0x3C) ++#define S3C_CLK_DIV3 S3C_CLKREG(0x40) ++#define S3C_CLK_GATE_HCLK1 S3C_CLKREG(0x44) ++#define S3C_CLK_GATE_SCLK1 S3C_CLKREG(0x48) ++#define S3C_AHB_CON0 S3C_CLKREG(0x100) ++#define S3C_CLK_SRC1 S3C_CLKREG(0x10C) ++#define S3C_SWRESET S3C_CLKREG(0x114) ++#define S3C_SYS_ID S3C_CLKREG(0x118) ++#define S3C_SYS_OTHERS S3C_CLKREG(0x11C) ++#define S3C_MEM_CFG_STAT S3C_CLKREG(0x12C) ++#define S3C_PWR_CFG S3C_CLKREG(0x804) ++#define S3C_EINT_WAKEUP_MASK S3C_CLKREG(0x808) ++#define S3C_NORMAL_CFG S3C_CLKREG(0x810) ++#define S3C_STOP_CFG S3C_CLKREG(0x814) ++#define S3C_SLEEP_CFG S3C_CLKREG(0x818) ++#define S3C_OSC_FREQ S3C_CLKREG(0x820) ++#define S3C_OSC_STABLE S3C_CLKREG(0x824) ++#define S3C_PWR_STABLE S3C_CLKREG(0x828) ++#define S3C_MTC_STABLE S3C_CLKREG(0x830) ++#define S3C_OTHERS S3C_CLKREG(0x900) ++#define S3C_RST_STAT S3C_CLKREG(0x904) ++#define S3C_WAKEUP_STAT S3C_CLKREG(0x908) ++#define S3C_INFORM0 S3C_CLKREG(0xA00) ++#define S3C_INFORM1 S3C_CLKREG(0xA04) ++#define S3C_INFORM2 S3C_CLKREG(0xA08) ++#define S3C_INFORM3 S3C_CLKREG(0xA0C) ++ ++#define S3C_EPLL_CON_M_SHIFT 16 ++#define S3C_EPLL_CON_P_SHIFT 8 ++#define S3C_EPLL_CON_S_SHIFT 0 ++#define S3C_EPLL_CON_K_SHIFT 0 ++ ++#define S3C_EPLL_CON_M_MASK (0xff< ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5P64XX - GPIO register definitions ++ */ ++ ++#ifndef __ASM_PLAT_S5P64XX_REGS_GPIO_H ++#define __ASM_PLAT_S5P64XX_REGS_GPIO_H __FILE__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Base addresses for each of the banks */ ++ ++#define S5P64XX_GPA_BASE (S5P64XX_VA_GPIO + 0x0000) ++#define S5P64XX_GPB_BASE (S5P64XX_VA_GPIO + 0x0020) ++#define S5P64XX_GPC_BASE (S5P64XX_VA_GPIO + 0x0040) ++#define S5P64XX_GPF_BASE (S5P64XX_VA_GPIO + 0x00A0) ++#define S5P64XX_GPG_BASE (S5P64XX_VA_GPIO + 0x00C0) ++#define S5P64XX_GPH_BASE (S5P64XX_VA_GPIO + 0x00E0) ++#define S5P64XX_GPI_BASE (S5P64XX_VA_GPIO + 0x0100) ++#define S5P64XX_GPJ_BASE (S5P64XX_VA_GPIO + 0x0120) ++#define S5P64XX_GPN_BASE (S5P64XX_VA_GPIO + 0x0830) ++#define S5P64XX_GPP_BASE (S5P64XX_VA_GPIO + 0x0160) ++#define S5P64XX_GPR_BASE (S5P64XX_VA_GPIO + 0x0290) ++#define S5P64XX_SPC_BASE (S5P64XX_VA_GPIO + 0x01A0) ++#define S5P64XX_SPC1_BASE (S5P64XX_VA_GPIO + 0x02B0) ++ ++#define S5P64XX_EINT0CON0 (S5P64XX_VA_GPIO + 0x900) ++#define S5P64XX_EINT0FLTCON0 (S5P64XX_VA_GPIO + 0x910) ++#define S5P64XX_EINT0FLTCON1 (S5P64XX_VA_GPIO + 0x914) ++ ++#define S5P64XX_EINT0MASK (S5P64XX_VA_GPIO + 0x920) ++#define S5P64XX_EINT0PEND (S5P64XX_VA_GPIO + 0x924) ++ ++#endif /* __ASM_PLAT_S5P64XX_REGS_GPIO_H */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/regs-iis.h linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/regs-iis.h +--- linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/regs-iis.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/regs-iis.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,115 @@ ++/* linux/arch/arm/plat-s5p/include/plat/regs-iis.h ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S5P64XX IIS register definition ++*/ ++ ++#ifndef __ASM_ARCH_REGS_S5P64XX_IIS_H ++#define __ASM_ARCH_REGS_S5P64XX_IIS_H ++ ++#define S5P64XX_IISCON (0x00) ++#define S5P64XX_IISMOD (0x04) ++#define S5P64XX_IISFIC (0x08) ++#define S5P64XX_IISPSR (0x0C) ++#define S5P64XX_IISTXD (0x10) ++#define S5P64XX_IISRXD (0x14) ++ ++#define S5P64XX_IISCON_I2SACTIVE (0x1<<0) ++#define S5P64XX_IISCON_RXDMACTIVE (0x1<<1) ++#define S5P64XX_IISCON_TXDMACTIVE (0x1<<2) ++#define S5P64XX_IISCON_RXCHPAUSE (0x1<<3) ++#define S5P64XX_IISCON_TXCHPAUSE (0x1<<4) ++#define S5P64XX_IISCON_RXDMAPAUSE (0x1<<5) ++#define S5P64XX_IISCON_TXDMAPAUSE (0x1<<6) ++#define S5P64XX_IISCON_FRXFULL (0x1<<7) ++#ifdef IIS_V40 ++#define S5P64XX_IISCON_FTX0FULL (0x1<<8) ++#else ++#define S5P64XX_IISCON_FTXFULL (0x1<<8) ++#endif ++#define S5P64XX_IISCON_FRXEMPT (0x1<<9) ++#define S5P64XX_IISCON_FTX0EMPT (0x1<<10) ++#define S5P64XX_IISCON_LRI (0x1<<11) ++#ifdef IIS_V40 ++#define S5P64XX_IISCON_FTX1FULL (0x1<<12) ++#define S5P64XX_IISCON_FTX2FULL (0x1<<13) ++#define S5P64XX_IISCON_FTX1EMPT (0x1<<14) ++#define S5P64XX_IISCON_FTX2EMPT (0x1<<15) ++#endif ++#define S5P64XX_IISCON_FTXURINTEN (0x1<<16) ++#define S5P64XX_IISCON_FTXURSTATUS (0x1<<17) ++#ifndef IIS_V40 ++#define S5P6440_IISCON_FRXORINTEN (0x1<<18) ++#define S5P6440_IISCON_FRXORSTATUS (0x1<<19) ++#endif ++ ++#define S5P64XX_IISMOD_BFSMASK (3<<1) ++#define S5P64XX_IISMOD_32FS (0<<1) ++#define S5P64XX_IISMOD_48FS (1<<1) ++#define S5P64XX_IISMOD_16FS (2<<1) ++#define S5P64XX_IISMOD_24FS (3<<1) ++ ++#define S5P64XX_IISMOD_RFSMASK (3<<3) ++#define S5P64XX_IISMOD_256FS (0<<3) ++#define S5P64XX_IISMOD_512FS (1<<3) ++#define S5P64XX_IISMOD_384FS (2<<3) ++#define S5P64XX_IISMOD_768FS (3<<3) ++ ++#define S5P64XX_IISMOD_SDFMASK (3<<5) ++#define S5P64XX_IISMOD_IIS (0<<5) ++#define S5P64XX_IISMOD_MSB (1<<5) ++#define S5P64XX_IISMOD_LSB (2<<5) ++ ++#define S5P64XX_IISMOD_LRP (1<<7) ++ ++#define S5P64XX_IISMOD_TXRMASK (3<<8) ++#define S5P64XX_IISMOD_TX (0<<8) ++#define S5P64XX_IISMOD_RX (1<<8) ++#define S5P64XX_IISMOD_TXRX (2<<8) ++ ++#define S5P64XX_IISMOD_IMSMASK (3<<10) ++#define S5P64XX_IISMOD_MSTPCLK (0<<10) ++#define S5P64XX_IISMOD_MSTCLKAUDIO (1<<10) ++#define S5P64XX_IISMOD_SLVPCLK (2<<10) ++#define S5P64XX_IISMOD_SLVI2SCLK (3<<10) ++ ++#define S5P64XX_IISMOD_CDCLKCON (1<<12) ++ ++#define S5P64XX_IISMOD_BLCMASK (3<<13) ++#define S5P64XX_IISMOD_16BIT (0<<13) ++#define S5P64XX_IISMOD_8BIT (1<<13) ++#define S5P64XX_IISMOD_24BIT (2<<13) ++ ++#ifdef IIS_V40 ++ ++#define S5P64XX_IISMOD_SD1EN (1<<16) ++#define S5P64XX_IISMOD_SD2EN (1<<17) ++ ++#define S5P64XX_IISMOD_CCD1MASK (3<<18) ++#define S5P64XX_IISMOD_CCD1ND (0<<18) ++#define S5P64XX_IISMOD_CCD11STD (1<<18) ++#define S5P64XX_IISMOD_CCD12NDD (2<<18) ++ ++#define S5P64XX_IISMOD_CCD2MASK (3<<20) ++#define S5P64XX_IISMOD_CCD2ND (0<<20) ++#define S5P64XX_IISMOD_CCD21STD (1<<20) ++#define S5P64XX_IISMOD_CCD22NDD (2<<20) ++ ++#endif ++ ++#define S5P64XX_IISFIC_FRXCNTMSK (0xf<<0) ++#define S5P64XX_IISFIC_RFLUSH (1<<7) ++#define S5P64XX_IISFIC_FTX0CNTMSK (0xf<<8) ++#define S5P64XX_IISFIC_TFLUSH (1<<15) ++#ifdef IIS_V40 ++#define S5P64XX_IISFIC_FTX1CNTMSK (0xf<<16) ++#define S5P64XX_IISFIC_FTX2CNTMSK (0xf<<24) ++#endif ++ ++#define S5P64XX_IISPSR_PSVALA (0x3f<<8) ++#define S5P64XX_IISPSR_PSRAEN (1<<15) ++ ++#endif /* __ASM_ARCH_REGS_S5P64XX_IIS_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/regs-post.h linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/regs-post.h +--- linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/regs-post.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/regs-post.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,230 @@ ++/* linux/arch/arm/plat-s5p64xx/include/plat/regs-post.h ++ * ++ * Register definition file for Samsung Post Processor (POST) driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef _REGS_POST_H ++#define _REGS_POST_H ++ ++#define S3C_POSTREG(x) (x) ++ ++/************************************************************************* ++ * Register part ++ ************************************************************************/ ++#define S3C_CIOYSA(__x) S3C_POSTREG(0x18 + (__x) * 4) ++#define S3C_CIOCBSA(__x) S3C_POSTREG(0x28 + (__x) * 4) ++#define S3C_CIOCRSA(__x) S3C_POSTREG(0x38 + (__x) * 4) ++ ++#define S3C_CIGCTRL S3C_POSTREG(0x08) /* Global control */ ++#define S3C_CIOYSA1 S3C_POSTREG(0x18) /* Y 1st frame start address for output DMA */ ++#define S3C_CIOYSA2 S3C_POSTREG(0x1c) /* Y 2nd frame start address for output DMA */ ++#define S3C_CIOYSA3 S3C_POSTREG(0x20) /* Y 3rd frame start address for output DMA */ ++#define S3C_CIOYSA4 S3C_POSTREG(0x24) /* Y 4th frame start address for output DMA */ ++#define S3C_CIOCBSA1 S3C_POSTREG(0x28) /* Cb 1st frame start address for output DMA */ ++#define S3C_CIOCBSA2 S3C_POSTREG(0x2c) /* Cb 2nd frame start address for output DMA */ ++#define S3C_CIOCBSA3 S3C_POSTREG(0x30) /* Cb 3rd frame start address for output DMA */ ++#define S3C_CIOCBSA4 S3C_POSTREG(0x34) /* Cb 4th frame start address for output DMA */ ++#define S3C_CIOCRSA1 S3C_POSTREG(0x38) /* Cr 1st frame start address for output DMA */ ++#define S3C_CIOCRSA2 S3C_POSTREG(0x3c) /* Cr 2nd frame start address for output DMA */ ++#define S3C_CIOCRSA3 S3C_POSTREG(0x40) /* Cr 3rd frame start address for output DMA */ ++#define S3C_CIOCRSA4 S3C_POSTREG(0x44) /* Cr 4th frame start address for output DMA */ ++#define S3C_CITRGFMT S3C_POSTREG(0x48) /* Target image format */ ++#define S3C_CIOCTRL S3C_POSTREG(0x4c) /* Output DMA control */ ++#define S3C_CISCPRERATIO S3C_POSTREG(0x50) /* Pre-scaler control 1 */ ++#define S3C_CISCPREDST S3C_POSTREG(0x54) /* Pre-scaler control 2 */ ++#define S3C_CISCCTRL S3C_POSTREG(0x58) /* Main scaler control */ ++#define S3C_CITAREA S3C_POSTREG(0x5c) /* Target area */ ++#define S3C_CISTATUS S3C_POSTREG(0x64) /* Status */ ++#define S3C_CIIMGCPT S3C_POSTREG(0xc0) /* Image capture enable command */ ++#define S3C_CICPTSEQ S3C_POSTREG(0xc4) /* Capture sequence */ ++#define S3C_CIIMGEFF S3C_POSTREG(0xd0) /* Image effects */ ++#define S3C_CIIYSA0 S3C_POSTREG(0xd4) /* Y frame start address 0 for input DMA */ ++#define S3C_CIICBSA0 S3C_POSTREG(0xd8) /* Cb frame start address 0 for input DMA */ ++#define S3C_CIICRSA0 S3C_POSTREG(0xdc) /* Cr frame start address 0 for input DMA */ ++#define S3C_CIREAL_ISIZE S3C_POSTREG(0xf8) /* Real input DMA image size */ ++#define S3C_MSCTRL S3C_POSTREG(0xfc) /* Input DMA control */ ++#define S3C_CIIYSA1 S3C_POSTREG(0x144) /* Y frame start address 1 for input DMA */ ++#define S3C_CIICBSA1 S3C_POSTREG(0x148) /* Cb frame start address 1 for input DMA */ ++#define S3C_CIICRSA1 S3C_POSTREG(0x14c) /* Cr frame start address 1 for input DMA */ ++#define S3C_CIOYOFF S3C_POSTREG(0x168) /* Output DMA Y offset */ ++#define S3C_CIOCBOFF S3C_POSTREG(0x16c) /* Output DMA CB offset */ ++#define S3C_CIOCROFF S3C_POSTREG(0x170) /* Output DMA CR offset */ ++#define S3C_CIIYOFF S3C_POSTREG(0x174) /* Input DMA Y offset */ ++#define S3C_CIICBOFF S3C_POSTREG(0x178) /* Input DMA CB offset */ ++#define S3C_CIICROFF S3C_POSTREG(0x17c) /* Input DMA CR offset */ ++#define S3C_ORGISIZE S3C_POSTREG(0x180) /* Input DMA original image size */ ++#define S3C_ORGOSIZE S3C_POSTREG(0x184) /* Output DMA original image size */ ++#define S3C_CIEXTEN S3C_POSTREG(0x188) /* Real output DMA image size */ ++#define S3C_CIDMAPARAM S3C_POSTREG(0x18c) /* DMA parameter */ ++ ++/************************************************************************* ++ * Macro part ++ ************************************************************************/ ++#define S3C_CITRGFMT_TARGETHSIZE(x) ((x) << 16) ++#define S3C_CITRGFMT_TARGETVSIZE(x) ((x) << 0) ++ ++#define S3C_CISCPRERATIO_SHFACTOR(x) ((x) << 28) ++#define S3C_CISCPRERATIO_PREHORRATIO(x) ((x) << 16) ++#define S3C_CISCPRERATIO_PREVERRATIO(x) ((x) << 0) ++ ++#define S3C_CISCPREDST_PREDSTWIDTH(x) ((x) << 16) ++#define S3C_CISCPREDST_PREDSTHEIGHT(x) ((x) << 0) ++ ++#define S3C_CISCCTRL_MAINHORRATIO(x) ((x) << 16) ++#define S3C_CISCCTRL_MAINVERRATIO(x) ((x) << 0) ++ ++#define S3C_CITAREA_TARGET_AREA(x) ((x) << 0) ++ ++#define S3C_CISTATUS_GET_FRAME_COUNT(x) (((x) >> 26) & 0x3) ++#define S3C_CISTATUS_GET_FRAME_END(x) (((x) >> 17) & 0x1) ++ ++#define S3C_CIREAL_ISIZE_HEIGHT(x) ((x) << 16) ++#define S3C_CIREAL_ISIZE_WIDTH(x) ((x) << 0) ++ ++#define S3C_MSCTRL_SUCCESSIVE_COUNT(x) ((x) << 24) ++ ++#define S3C_CIOYOFF_VERTICAL(x) ((x) << 16) ++#define S3C_CIOYOFF_HORIZONTAL(x) ((x) << 0) ++ ++#define S3C_CIOCBOFF_VERTICAL(x) ((x) << 16) ++#define S3C_CIOCBOFF_HORIZONTAL(x) ((x) << 0) ++ ++#define S3C_CIOCROFF_VERTICAL(x) ((x) << 16) ++#define S3C_CIOCROFF_HORIZONTAL(x) ((x) << 0) ++ ++#define S3C_CIIYOFF_VERTICAL(x) ((x) << 16) ++#define S3C_CIIYOFF_HORIZONTAL(x) ((x) << 0) ++ ++#define S3C_CIICBOFF_VERTICAL(x) ((x) << 16) ++#define S3C_CIICBOFF_HORIZONTAL(x) ((x) << 0) ++ ++#define S3C_CIICROFF_VERTICAL(x) ((x) << 16) ++#define S3C_CIICROFF_HORIZONTAL(x) ((x) << 0) ++ ++#define S3C_ORGISIZE_VERTICAL(x) ((x) << 16) ++#define S3C_ORGISIZE_HORIZONTAL(x) ((x) << 0) ++ ++#define S3C_ORGOSIZE_VERTICAL(x) ((x) << 16) ++#define S3C_ORGOSIZE_HORIZONTAL(x) ((x) << 0) ++ ++ ++/************************************************************************* ++ * Bit definition part ++ ************************************************************************/ ++/* Global control register */ ++#define S3C_CIGCTRL_SWRST (1 << 31) ++#define S3C_CIGCTRL_IRQ_OVFEN (1 << 22) ++#define S3C_CIGCTRL_IRQ_EDGE (0 << 20) ++#define S3C_CIGCTRL_IRQ_LEVEL (1 << 20) ++#define S3C_CIGCTRL_IRQ_CLR (1 << 19) ++#define S3C_CIGCTRL_IRQ_DISABLE (0 << 16) ++#define S3C_CIGCTRL_IRQ_ENABLE (1 << 16) ++ ++/* Target format register */ ++#define S3C_CITRGFMT_OUTFORMAT_YCBCR420 (0 << 29) ++#define S3C_CITRGFMT_OUTFORMAT_YCBCR422 (1 << 29) ++#define S3C_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE (2 << 29) ++#define S3C_CITRGFMT_OUTFORMAT_RGB (3 << 29) ++ ++/* Output DMA control register */ ++#define S3C_CIOCTRL_ORDER2P_SHIFT (24) ++#define S3C_CIOCTRL_ORDER2P_MASK (3 << 24) ++#define S3C_CIOCTRL_YCBCR_3PLANE (0 << 3) ++#define S3C_CIOCTRL_YCBCR_2PLANE (1 << 3) ++#define S3C_CIOCTRL_YCBCR_PLANE_MASK (1 << 3) ++#define S3C_CIOCTRL_ORDER422_MASK (3 << 0) ++ ++/* Main scaler control register */ ++#define S3C_CISCCTRL_SCALEUP_H (1 << 30) ++#define S3C_CISCCTRL_SCALEUP_V (1 << 29) ++#define S3C_CISCCTRL_CSCR2Y_NARROW (0 << 28) ++#define S3C_CISCCTRL_CSCR2Y_WIDE (1 << 28) ++#define S3C_CISCCTRL_CSCY2R_NARROW (0 << 27) ++#define S3C_CISCCTRL_CSCY2R_WIDE (1 << 27) ++#define S3C_CISCCTRL_LCDPATHEN_FIFO (1 << 26) ++#define S3C_CISCCTRL_PROGRESSIVE (0 << 25) ++#define S3C_CISCCTRL_INTERLACE (1 << 25) ++#define S3C_CISCCTRL_SCALERSTART (1 << 15) ++#define S3C_CISCCTRL_INRGB_FMT_RGB565 (0 << 13) ++#define S3C_CISCCTRL_INRGB_FMT_RGB666 (1 << 13) ++#define S3C_CISCCTRL_INRGB_FMT_RGB888 (2 << 13) ++#define S3C_CISCCTRL_OUTRGB_FMT_RGB565 (0 << 11) ++#define S3C_CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11) ++#define S3C_CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11) ++#define S3C_CISCCTRL_EXTRGB_NORMAL (0 << 10) ++#define S3C_CISCCTRL_EXTRGB_EXTENSION (1 << 10) ++#define S3C_CISCCTRL_ONE2ONE (1 << 9) ++ ++/* Status register */ ++#define S3C_CISTATUS_IMGCPTENSC (1 << 21) ++#define S3C_CISTATUS_FRAMEEND (1 << 17) ++ ++/* Image capture enable register */ ++#define S3C_CIIMGCPT_IMGCPTEN (1 << 31) ++#define S3C_CIIMGCPT_IMGCPTEN_SC (1 << 30) ++#define S3C_CIIMGCPT_CPT_FREN_ENABLE (1 << 25) ++#define S3C_CIIMGCPT_CPT_FRMOD_EN (0 << 18) ++#define S3C_CIIMGCPT_CPT_FRMOD_CNT (1 << 18) ++ ++/* Real input DMA size register */ ++#define S3C_CIREAL_ISIZE_AUTOLOAD_ENABLE (1 << 31) ++#define S3C_CIREAL_ISIZE_ADDR_CH_DISABLE (1 << 30) ++ ++/* Input DMA control register */ ++#define S3C_MSCTRL_2PLANE_SHIFT (16) ++#define S3C_MSCTRL_C_INT_IN_3PLANE (0 << 15) ++#define S3C_MSCTRL_C_INT_IN_2PLANE (1 << 15) ++#define S3C_MSCTRL_ORDER422_CRYCBY (0 << 4) ++#define S3C_MSCTRL_ORDER422_YCRYCB (1 << 4) ++#define S3C_MSCTRL_ORDER422_CBYCRY (2 << 4) ++#define S3C_MSCTRL_ORDER422_YCBYCR (3 << 4) ++#define S3C_MSCTRL_INFORMAT_YCBCR420 (0 << 1) ++#define S3C_MSCTRL_INFORMAT_YCBCR422 (1 << 1) ++#define S3C_MSCTRL_INFORMAT_YCBCR422_1PLANE (2 << 1) ++#define S3C_MSCTRL_INFORMAT_RGB (3 << 1) ++#define S3C_MSCTRL_ENVID (1 << 0) ++ ++/* DMA parameter register */ ++#define S3C_CIDMAPARAM_R_MODE_LINEAR (0 << 29) ++#define S3C_CIDMAPARAM_R_MODE_CONFTILE (1 << 29) ++#define S3C_CIDMAPARAM_R_MODE_16X16 (2 << 29) ++#define S3C_CIDMAPARAM_R_MODE_64X32 (3 << 29) ++#define S3C_CIDMAPARAM_R_TILE_HSIZE_64 (0 << 24) ++#define S3C_CIDMAPARAM_R_TILE_HSIZE_128 (1 << 24) ++#define S3C_CIDMAPARAM_R_TILE_HSIZE_256 (2 << 24) ++#define S3C_CIDMAPARAM_R_TILE_HSIZE_512 (3 << 24) ++#define S3C_CIDMAPARAM_R_TILE_HSIZE_1024 (4 << 24) ++#define S3C_CIDMAPARAM_R_TILE_HSIZE_2048 (5 << 24) ++#define S3C_CIDMAPARAM_R_TILE_HSIZE_4096 (6 << 24) ++#define S3C_CIDMAPARAM_R_TILE_VSIZE_1 (0 << 20) ++#define S3C_CIDMAPARAM_R_TILE_VSIZE_2 (1 << 20) ++#define S3C_CIDMAPARAM_R_TILE_VSIZE_4 (2 << 20) ++#define S3C_CIDMAPARAM_R_TILE_VSIZE_8 (3 << 20) ++#define S3C_CIDMAPARAM_R_TILE_VSIZE_16 (4 << 20) ++#define S3C_CIDMAPARAM_R_TILE_VSIZE_32 (5 << 20) ++#define S3C_CIDMAPARAM_W_MODE_LINEAR (0 << 13) ++#define S3C_CIDMAPARAM_W_MODE_CONFTILE (1 << 13) ++#define S3C_CIDMAPARAM_W_MODE_16X16 (2 << 13) ++#define S3C_CIDMAPARAM_W_MODE_64X32 (3 << 13) ++#define S3C_CIDMAPARAM_W_TILE_HSIZE_64 (0 << 8) ++#define S3C_CIDMAPARAM_W_TILE_HSIZE_128 (1 << 8) ++#define S3C_CIDMAPARAM_W_TILE_HSIZE_256 (2 << 8) ++#define S3C_CIDMAPARAM_W_TILE_HSIZE_512 (3 << 8) ++#define S3C_CIDMAPARAM_W_TILE_HSIZE_1024 (4 << 8) ++#define S3C_CIDMAPARAM_W_TILE_HSIZE_2048 (5 << 8) ++#define S3C_CIDMAPARAM_W_TILE_HSIZE_4096 (6 << 8) ++#define S3C_CIDMAPARAM_W_TILE_VSIZE_1 (0 << 4) ++#define S3C_CIDMAPARAM_W_TILE_VSIZE_2 (1 << 4) ++#define S3C_CIDMAPARAM_W_TILE_VSIZE_4 (2 << 4) ++#define S3C_CIDMAPARAM_W_TILE_VSIZE_8 (3 << 4) ++#define S3C_CIDMAPARAM_W_TILE_VSIZE_16 (4 << 4) ++#define S3C_CIDMAPARAM_W_TILE_VSIZE_32 (5 << 4) ++ ++#endif /* _REGS_POST_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/regs-pp.h linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/regs-pp.h +--- linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/regs-pp.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/regs-pp.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,377 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-fimc.h ++ * ++ * Register definition file for Samsung Camera Interface (FIMC) driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef _REGS_FIMC_H ++#define _REGS_FIMC_H ++ ++#define S3C_FIMCREG(x) (x) ++ ++/************************************************************************* ++ * Register part ++ ************************************************************************/ ++#define S3C_CICOYSA(__x) S3C_FIMCREG(0x18 + (__x) * 4) ++#define S3C_CICOCBSA(__x) S3C_FIMCREG(0x28 + (__x) * 4) ++#define S3C_CICOCRSA(__x) S3C_FIMCREG(0x38 + (__x) * 4) ++#define S3C_CIPRYSA(__x) S3C_FIMCREG(0x6c + (__x) * 4) ++#define S3C_CIPRCBSA(__x) S3C_FIMCREG(0x7c + (__x) * 4) ++#define S3C_CIPRCRSA(__x) S3C_FIMCREG(0x8c + (__x) * 4) ++ ++#define S3C_CISRCFMT S3C_FIMCREG(0x00) /* Input source format */ ++#define S3C_CIWDOFST S3C_FIMCREG(0x04) /* Window offset */ ++#define S3C_CIGCTRL S3C_FIMCREG(0x08) /* Global control */ ++#define S3C_CIWDOFST2 S3C_FIMCREG(0x14) /* Window offset 2 */ ++#define S3C_CICOYSA1 S3C_FIMCREG(0x18) /* Y 1st frame start address for output DMA */ ++#define S3C_CICOYSA2 S3C_FIMCREG(0x1c) /* Y 2nd frame start address for output DMA */ ++#define S3C_CICOYSA3 S3C_FIMCREG(0x20) /* Y 3rd frame start address for output DMA */ ++#define S3C_CICOYSA4 S3C_FIMCREG(0x24) /* Y 4th frame start address for output DMA */ ++#define S3C_CICOCBSA1 S3C_FIMCREG(0x28) /* Cb 1st frame start address for output DMA */ ++#define S3C_CICOCBSA2 S3C_FIMCREG(0x2c) /* Cb 2nd frame start address for output DMA */ ++#define S3C_CICOCBSA3 S3C_FIMCREG(0x30) /* Cb 3rd frame start address for output DMA */ ++#define S3C_CICOCBSA4 S3C_FIMCREG(0x34) /* Cb 4th frame start address for output DMA */ ++#define S3C_CICOCRSA1 S3C_FIMCREG(0x38) /* Cr 1st frame start address for output DMA */ ++#define S3C_CICOCRSA2 S3C_FIMCREG(0x3c) /* Cr 2nd frame start address for output DMA */ ++#define S3C_CICOCRSA3 S3C_FIMCREG(0x40) /* Cr 3rd frame start address for output DMA */ ++#define S3C_CICOCRSA4 S3C_FIMCREG(0x44) /* Cr 4th frame start address for output DMA */ ++#define S3C_CICOTRGFMT S3C_FIMCREG(0x48) /* Target image format */ ++#define S3C_CICOCTRL S3C_FIMCREG(0x4c) /* Output DMA control */ ++#define S3C_CICOSCPRERATIO S3C_FIMCREG(0x50) /* Pre-scaler control 1 */ ++#define S3C_CICOSCPREDST S3C_FIMCREG(0x54) /* Pre-scaler control 2 */ ++#define S3C_CICOSCCTRL S3C_FIMCREG(0x58) /* Main scaler control */ ++#define S3C_CICOTAREA S3C_FIMCREG(0x5c) /* Target area */ ++#define S3C_CICOSTATUS S3C_FIMCREG(0x64) /* Status */ ++#define S3C_CIPRYSA1 S3C_FIMCREG(0x6c) /* Y 1st frame start address for output DMA */ ++#define S3C_CIPRYSA2 S3C_FIMCREG(0x70) /* Y 2nd frame start address for output DMA */ ++#define S3C_CIPRYSA3 S3C_FIMCREG(0x74) /* Y 3rd frame start address for output DMA */ ++#define S3C_CIPRYSA4 S3C_FIMCREG(0x78) /* Y 4th frame start address for output DMA */ ++#define S3C_CIPRCBSA1 S3C_FIMCREG(0x7c) /* Cb 1st frame start address for output DMA */ ++#define S3C_CIPRCBSA2 S3C_FIMCREG(0x80) /* Cb 2nd frame start address for output DMA */ ++#define S3C_CIPRCBSA3 S3C_FIMCREG(0x84) /* Cb 3rd frame start address for output DMA */ ++#define S3C_CIPRCBSA4 S3C_FIMCREG(0x88) /* Cb 4th frame start address for output DMA */ ++#define S3C_CIPRCRSA1 S3C_FIMCREG(0x8c) /* Cr 1st frame start address for output DMA */ ++#define S3C_CIPRCRSA2 S3C_FIMCREG(0x90) /* Cr 2nd frame start address for output DMA */ ++#define S3C_CIPRCRSA3 S3C_FIMCREG(0x94) /* Cr 3rd frame start address for output DMA */ ++#define S3C_CIPRCRSA4 S3C_FIMCREG(0x98) /* Cr 4th frame start address for output DMA */ ++#define S3C_CIPRTRGFMT S3C_FIMCREG(0x9c) /* Target image format */ ++#define S3C_CIPRCTRL S3C_FIMCREG(0xa0) /* Output DMA control */ ++#define S3C_CIPRSCPRERATIO S3C_FIMCREG(0xa4) /* Pre-scaler control 1 */ ++#define S3C_CIPRSCPREDST S3C_FIMCREG(0xa8) /* Pre-scaler control 2 */ ++#define S3C_CIPRSCCTRL S3C_FIMCREG(0xac) /* Main scaler control */ ++#define S3C_CIPRTAREA S3C_FIMCREG(0xb0) /* Target area */ ++#define S3C_CIPRSTATUS S3C_FIMCREG(0xb8) /* Status */ ++#define S3C_CIIMGCPT S3C_FIMCREG(0xc0) /* Image capture enable command */ ++#define S3C_CICPTSEQ S3C_FIMCREG(0xc4) /* Capture sequence */ ++#define S3C_CIIMGEFF S3C_FIMCREG(0xd0) /* Image effects */ ++#define S3C_MSCOY0SA S3C_FIMCREG(0xd4) /* Y frame start address for input DMA */ ++#define S3C_MSCOCB0SA S3C_FIMCREG(0xd8) /* Cb frame start address for input DMA */ ++#define S3C_MSCOCR0SA S3C_FIMCREG(0xdc) /* Cr frame start address for input DMA */ ++#define S3C_MSCOY0END S3C_FIMCREG(0xe0) /* Y frame end address for input DMA */ ++#define S3C_MSCOCB0END S3C_FIMCREG(0xe4) /* Cb frame end address for input DMA */ ++#define S3C_MSCOCR0END S3C_FIMCREG(0xe8) /* Cr frame end address for input DMA */ ++#define S3C_MSCOYOFF S3C_FIMCREG(0xec) /* Y offset */ ++#define S3C_MSCOCBOFF S3C_FIMCREG(0xf0) /* CB offset */ ++#define S3C_MSCOCROFF S3C_FIMCREG(0xf4) /* CR offset */ ++#define S3C_MSCOWIDTH S3C_FIMCREG(0xf8) /* Real input DMA image size */ ++#define S3C_MSCOCTRL S3C_FIMCREG(0xfc) /* Input DMA control */ ++#define S3C_MSPRY0SA S3C_FIMCREG(0x100) /* Y frame start address for input DMA */ ++#define S3C_MSPRCB0SA S3C_FIMCREG(0x104) /* Cb frame start address for input DMA */ ++#define S3C_MSPRCR0SA S3C_FIMCREG(0x108) /* Cr frame start address for input DMA */ ++#define S3C_MSPRY0END S3C_FIMCREG(0x10c) /* Y frame end address for input DMA */ ++#define S3C_MSPRCB0END S3C_FIMCREG(0x110) /* Cb frame end address for input DMA */ ++#define S3C_MSPRCR0END S3C_FIMCREG(0x114) /* Cr frame end address for input DMA */ ++#define S3C_MSPRYOFF S3C_FIMCREG(0x118) /* Y offset */ ++#define S3C_MSPRCBOFF S3C_FIMCREG(0x11c) /* CB offset */ ++#define S3C_MSPRCROFF S3C_FIMCREG(0x120) /* CR offset */ ++#define S3C_MSPRWIDTH S3C_FIMCREG(0x124) /* Real input DMA image size */ ++#define S3C_MSPRCTRL S3C_FIMCREG(0x128) /* Input DMA control */ ++#define S3C_CICOSCOSY S3C_FIMCREG(0x12c) ++#define S3C_CICOSCOSCB S3C_FIMCREG(0x130) ++#define S3C_CICOSCOSCR S3C_FIMCREG(0x134) ++#define S3C_CIPRSPRSY S3C_FIMCREG(0x138) ++#define S3C_CIPRSPRSCB S3C_FIMCREG(0x13c) ++#define S3C_CIPRSPRSCR S3C_FIMCREG(0x140) ++ ++/************************************************************************* ++ * Macro part ++ ************************************************************************/ ++#define S3C_CISRCFMT_SOURCEHSIZE(x) ((x) << 16) ++#define S3C_CISRCFMT_SOURCEVSIZE(x) ((x) << 0) ++ ++#define S3C_CIWDOFST_WINHOROFST(x) ((x) << 16) ++#define S3C_CIWDOFST_WINVEROFST(x) ((x) << 0) ++ ++#define S3C_CIWDOFST2_WINHOROFST2(x) ((x) << 16) ++#define S3C_CIWDOFST2_WINVEROFST2(x) ((x) << 0) ++ ++#define S3C_CICOTRGFMT_TARGETHSIZE(x) ((x) << 16) ++#define S3C_CICOTRGFMT_TARGETVSIZE(x) ((x) << 0) ++ ++#define S3C_CICOCTRL_YBURST1(x) ((x) << 19) ++#define S3C_CICOCTRL_YBURST2(x) ((x) << 14) ++#define S3C_CICOCTRL_CBURST1(x) ((x) << 9) ++#define S3C_CICOCTRL_CBURST2(x) ((x) << 4) ++ ++#define S3C_CICOSCPRERATIO_SHFACTOR(x) ((x) << 28) ++#define S3C_CICOSCPRERATIO_PREHORRATIO(x) ((x) << 16) ++#define S3C_CICOSCPRERATIO_PREVERRATIO(x) ((x) << 0) ++ ++#define S3C_CICOSCPREDST_PREDSTWIDTH(x) ((x) << 16) ++#define S3C_CICOSCPREDST_PREDSTHEIGHT(x) ((x) << 0) ++ ++#define S3C_CICOSCCTRL_MAINHORRATIO(x) ((x) << 16) ++#define S3C_CICOSCCTRL_MAINVERRATIO(x) ((x) << 0) ++ ++#define S3C_CICOTAREA_TARGET_AREA(x) ((x) << 0) ++ ++#define S3C_CICOSTATUS_GET_FRAME_COUNT(x) (((x) >> 26) & 0x3) ++#define S3C_CICOSTATUS_GET_FRAME_END(x) (((x) >> 17) & 0x1) ++ ++#define S3C_CIPRTRGFMT_TARGETHSIZE(x) ((x) << 16) ++#define S3C_CIPRTRGFMT_TARGETVSIZE(x) ((x) << 0) ++ ++#define S3C_CIPRCTRL_YBURST1(x) ((x) << 19) ++#define S3C_CIPRCTRL_YBURST2(x) ((x) << 14) ++#define S3C_CIPRCTRL_CBURST1(x) ((x) << 9) ++#define S3C_CIPRCTRL_CBURST2(x) ((x) << 4) ++ ++#define S3C_CIPRSCPRERATIO_SHFACTOR(x) ((x) << 28) ++#define S3C_CIPRSCPRERATIO_PREHORRATIO(x) ((x) << 16) ++#define S3C_CIPRSCPRERATIO_PREVERRATIO(x) ((x) << 0) ++ ++#define S3C_CIPRSCPREDST_PREDSTWIDTH(x) ((x) << 16) ++#define S3C_CIPRSCPREDST_PREDSTHEIGHT(x) ((x) << 0) ++ ++#define S3C_CIPRSCCTRL_MAINHORRATIO(x) ((x) << 16) ++#define S3C_CIPRSCCTRL_MAINVERRATIO(x) ((x) << 0) ++ ++#define S3C_CIPRTAREA_TARGET_AREA(x) ((x) << 0) ++ ++#define S3C_CIPRSTATUS_GET_FRAME_COUNT(x) (((x) >> 26) & 0x3) ++#define S3C_CIPRSTATUS_GET_FRAME_END(x) (((x) >> 19) & 0x1) ++ ++#define S3C_CIIMGEFF_PAT_CB(x) ((x) << 13) ++#define S3C_CIIMGEFF_PAT_CR(x) ((x) << 0) ++ ++#define S3C_MSCO_HEIGHT(x) ((x) << 16) ++#define S3C_MSCO_WIDTH(x) ((x) << 0) ++ ++#define S3C_MSPR_HEIGHT(x) ((x) << 16) ++#define S3C_MSPR_WIDTH(x) ((x) << 0) ++ ++/************************************************************************* ++ * Bit definition part ++ ************************************************************************/ ++/* Source format register */ ++#define S3C_CISRCFMT_ITU601_8BIT (1 << 31) ++#define S3C_CISRCFMT_ITU656_8BIT (0 << 31) ++#define S3C_CISRCFMT_ORDER422_YCBYCR (0 << 14) ++#define S3C_CISRCFMT_ORDER422_YCRYCB (1 << 14) ++#define S3C_CISRCFMT_ORDER422_CBYCRY (2 << 14) ++#define S3C_CISRCFMT_ORDER422_CRYCBY (3 << 14) ++ ++/* Window offset register */ ++#define S3C_CIWDOFST_WINOFSEN (1 << 31) ++#define S3C_CIWDOFST_CLROVCOFIY (1 << 30) ++#define S3C_CIWDOFST_CLROVRLB_PR (1 << 28) ++#define S3C_CIWDOFST_CLROVPRFIY (1 << 27) ++#define S3C_CIWDOFST_CLROVCOFICB (1 << 15) ++#define S3C_CIWDOFST_CLROVCOFICR (1 << 14) ++#define S3C_CIWDOFST_CLROVPRFICB (1 << 13) ++#define S3C_CIWDOFST_CLROVPRFICR (1 << 12) ++#define S3C_CIWDOFST_WINHOROFST_MASK (0x7ff << 16) ++#define S3C_CIWDOFST_WINVEROFST_MASK (0x7ff << 0) ++ ++/* Global control register */ ++#define S3C_CIGCTRL_SWRST (1 << 31) ++#define S3C_CIGCTRL_CAMRST (1 << 30) ++#define S3C_CIGCTRL_TESTPATTERN_NORMAL (0 << 27) ++#define S3C_CIGCTRL_TESTPATTERN_COLOR_BAR (1 << 27) ++#define S3C_CIGCTRL_TESTPATTERN_HOR_INC (2 << 27) ++#define S3C_CIGCTRL_TESTPATTERN_VER_INC (3 << 27) ++#define S3C_CIGCTRL_TESTPATTERN_MASK (3 << 27) ++#define S3C_CIGCTRL_TESTPATTERN_SHIFT (27) ++#define S3C_CIGCTRL_INVPOLPCLK (1 << 26) ++#define S3C_CIGCTRL_INVPOLVSYNC (1 << 25) ++#define S3C_CIGCTRL_INVPOLHREF (1 << 24) ++#define S3C_CIGCTRL_IRQ_OVFEN (1 << 22) ++#define S3C_CIGCTRL_HREF_MASK (1 << 21) ++#define S3C_CIGCTRL_IRQ_EDGE (0 << 20) ++#define S3C_CIGCTRL_IRQ_LEVEL (1 << 20) ++#define S3C_CIGCTRL_IRQ_CLR_C (1 << 19) ++#define S3C_CIGCTRL_IRQ_CLR_P (1 << 18) ++#define S3C_CIGCTRL_PROGRESSIVE (0 << 0) ++#define S3C_CIGCTRL_INTERLACE (1 << 0) ++ ++/* Window offset2 register */ ++#define S3C_CIWDOFST_WINHOROFST2_MASK (0xfff << 16) ++#define S3C_CIWDOFST_WINVEROFST2_MASK (0xfff << 16) ++ ++/* Target format register */ ++#define S3C_CICOTRGFMT_OUTFORMAT_YCBCR420 (0 << 29) ++#define S3C_CICOTRGFMT_OUTFORMAT_YCBCR422 (1 << 29) ++#define S3C_CICOTRGFMT_OUTFORMAT_YCBCR422I (2 << 29) ++#define S3C_CICOTRGFMT_OUTFORMAT_RGB (3 << 29) ++#define S3C_CICOTRGFMT_FLIP_SHIFT (14) ++#define S3C_CICOTRGFMT_FLIP_NORMAL (0 << 14) ++#define S3C_CICOTRGFMT_FLIP_X_MIRROR (1 << 14) ++#define S3C_CICOTRGFMT_FLIP_Y_MIRROR (2 << 14) ++#define S3C_CICOTRGFMT_FLIP_180 (3 << 14) ++#define S3C_CICOTRGFMT_FLIP_MASK (3 << 14) ++ ++/* Output DMA control register */ ++#define S3C_CICOCTRL_BURST_MASK (0xfffff << 4) ++#define S3C_CICOCTRL_LASTIRQ_ENABLE (1 << 2) ++#define S3C_CICOCTRL_ORDER422_MASK (3 << 0) ++ ++/* Main scaler control register */ ++#define S3C_CICOSCCTRL_SCALERBYPASS (1 << 31) ++#define S3C_CICOSCCTRL_SCALEUP_H (1 << 30) ++#define S3C_CICOSCCTRL_SCALEUP_V (1 << 29) ++#define S3C_CICOSCCTRL_CSCR2Y_NARROW (0 << 28) ++#define S3C_CICOSCCTRL_CSCR2Y_WIDE (1 << 28) ++#define S3C_CICOSCCTRL_CSCY2R_NARROW (0 << 27) ++#define S3C_CICOSCCTRL_CSCY2R_WIDE (1 << 27) ++#define S3C_CICOSCCTRL_LCDPATHEN_FIFO (1 << 26) ++#define S3C_CICOSCCTRL_PROGRESSIVE (0 << 25) ++#define S3C_CICOSCCTRL_INTERLACE (1 << 25) ++#define S3C_CICOSCCTRL_SCALERSTART (1 << 15) ++#define S3C_CICOSCCTRL_INRGB_FMT_RGB565 (0 << 13) ++#define S3C_CICOSCCTRL_INRGB_FMT_RGB666 (1 << 13) ++#define S3C_CICOSCCTRL_INRGB_FMT_RGB888 (2 << 13) ++#define S3C_CICOSCCTRL_OUTRGB_FMT_RGB565 (0 << 11) ++#define S3C_CICOSCCTRL_OUTRGB_FMT_RGB666 (1 << 11) ++#define S3C_CICOSCCTRL_OUTRGB_FMT_RGB888 (2 << 11) ++#define S3C_CICOSCCTRL_EXTRGB_NORMAL (0 << 10) ++#define S3C_CICOSCCTRL_EXTRGB_EXTENSION (1 << 10) ++#define S3C_CICOSCCTRL_ONE2ONE (1 << 9) ++ ++/* Status register */ ++#define S3C_CICOSTATUS_OVFIY (1 << 31) ++#define S3C_CICOSTATUS_OVFICB (1 << 30) ++#define S3C_CICOSTATUS_OVFICR (1 << 29) ++#define S3C_CICOSTATUS_VSYNC (1 << 28) ++#define S3C_CICOSTATUS_WINOFSTEN (1 << 25) ++#define S3C_CICOSTATUS_IMGCPTEN (1 << 22) ++#define S3C_CICOSTATUS_IMGCPTENSC (1 << 21) ++#define S3C_CICOSTATUS_VSYNC_A (1 << 20) ++#define S3C_CICOSTATUS_FRAMEEND (1 << 17) ++ ++/* Target format register */ ++#define S3C_CIPRTRGFMT_OUTFORMAT_YCBCR420 (0 << 29) ++#define S3C_CIPRTRGFMT_OUTFORMAT_YCBCR422 (1 << 29) ++#define S3C_CIPRTRGFMT_OUTFORMAT_YCBCR422I (2 << 29) ++#define S3C_CIPRTRGFMT_OUTFORMAT_RGB (3 << 29) ++#define S3C_CIPRTRGFMT_FLIP_SHIFT (14) ++#define S3C_CIPRTRGFMT_FLIP_NORMAL (0 << 14) ++#define S3C_CIPRTRGFMT_FLIP_X_MIRROR (1 << 14) ++#define S3C_CIPRTRGFMT_FLIP_Y_MIRROR (2 << 14) ++#define S3C_CIPRTRGFMT_FLIP_180 (3 << 14) ++#define S3C_CIPRTRGFMT_FLIP_MASK (3 << 14) ++#define S3C_CIPRTRGFMT_ROT90_CLOCKWISE (1 << 13) ++ ++/* Output DMA control register */ ++#define S3C_CIPRCTRL_BURST_MASK (0xfffff << 4) ++#define S3C_CIPRCTRL_LASTIRQ_ENABLE (1 << 2) ++#define S3C_CIPRCTRL_ORDER422_MASK (3 << 0) ++ ++/* Main scaler control register */ ++#define S3C_CIPRSCCTRL_SCALERBYPASS (1 << 31) ++#define S3C_CIPRSCCTRL_SCALEUP_H (1 << 30) ++#define S3C_CIPRSCCTRL_SCALEUP_V (1 << 29) ++#define S3C_CIPRSCCTRL_CSCR2Y_NARROW (0 << 28) ++#define S3C_CIPRSCCTRL_CSCR2Y_WIDE (1 << 28) ++#define S3C_CIPRSCCTRL_CSCY2R_NARROW (0 << 27) ++#define S3C_CIPRSCCTRL_CSCY2R_WIDE (1 << 27) ++#define S3C_CIPRSCCTRL_LCDPATHEN_FIFO (1 << 26) ++#define S3C_CIPRSCCTRL_PROGRESSIVE (0 << 25) ++#define S3C_CIPRSCCTRL_INTERLACE (1 << 25) ++#define S3C_CIPRSCCTRL_SCALERSTART (1 << 15) ++#define S3C_CIPRSCCTRL_INRGB_FMT_RGB565 (0 << 13) ++#define S3C_CIPRSCCTRL_INRGB_FMT_RGB666 (1 << 13) ++#define S3C_CIPRSCCTRL_INRGB_FMT_RGB888 (2 << 13) ++#define S3C_CIPRSCCTRL_OUTRGB_FMT_RGB565 (0 << 11) ++#define S3C_CIPRSCCTRL_OUTRGB_FMT_RGB666 (1 << 11) ++#define S3C_CIPRSCCTRL_OUTRGB_FMT_RGB888 (2 << 11) ++#define S3C_CIPRSCCTRL_EXTRGB_NORMAL (0 << 10) ++#define S3C_CIPRSCCTRL_EXTRGB_EXTENSION (1 << 10) ++#define S3C_CIPRSCCTRL_ONE2ONE (1 << 9) ++ ++/* Status register */ ++#define S3C_CIPRSTATUS_OVFIY (1 << 31) ++#define S3C_CIPRSTATUS_OVFICB (1 << 30) ++#define S3C_CIPRSTATUS_OVFICR (1 << 29) ++#define S3C_CIPRSTATUS_VSYNC (1 << 28) ++#define S3C_CIPRSTATUS_WINOFSTEN (1 << 25) ++#define S3C_CIPRSTATUS_IMGCPTEN (1 << 22) ++#define S3C_CIPRSTATUS_IMGCPTENSC (1 << 21) ++#define S3C_CIPRSTATUS_VSYNC_A (1 << 20) ++#define S3C_CIPRSTATUS_FRAMEEND (1 << 19) ++ ++/* Image capture enable register */ ++#define S3C_CIIMGCPT_IMGCPTEN (1 << 31) ++#define S3C_CIIMGCPT_IMGCPTEN_COSC (1 << 30) ++#define S3C_CIIMGCPT_IMGCPTEN_PRSC (1 << 29) ++#define S3C_CIIMGCPT_CPT_FREN_ENABLE_CO (1 << 25) ++#define S3C_CIIMGCPT_CPT_FREN_ENABLE_PR (1 << 24) ++#define S3C_CIIMGCPT_CPT_FRMOD_EN (0 << 18) ++#define S3C_CIIMGCPT_CPT_FRMOD_CNT (1 << 18) ++ ++/* Image effects register */ ++#define S3C_CIIMGEFF_IE_DISABLE_PR (0 << 31) ++#define S3C_CIIMGEFF_IE_ENABLE_PR (1 << 31) ++#define S3C_CIIMGEFF_IE_DISABLE_CO (0 << 30) ++#define S3C_CIIMGEFF_IE_ENABLE_CO (1 << 30) ++#define S3C_CIIMGEFF_IE_SC_BEFORE (0 << 29) ++#define S3C_CIIMGEFF_IE_SC_AFTER (1 << 29) ++#define S3C_CIIMGEFF_FIN_BYPASS (0 << 26) ++#define S3C_CIIMGEFF_FIN_ARBITRARY (1 << 26) ++#define S3C_CIIMGEFF_FIN_NEGATIVE (2 << 26) ++#define S3C_CIIMGEFF_FIN_ARTFREEZE (3 << 26) ++#define S3C_CIIMGEFF_FIN_EMBOSSING (4 << 26) ++#define S3C_CIIMGEFF_FIN_SILHOUETTE (5 << 26) ++#define S3C_CIIMGEFF_FIN_MASK (7 << 26) ++#define S3C_CIIMGEFF_PAT_CBCR_MASK ((0xff < 13) | (0xff < 0)) ++ ++/* Real input DMA size register */ ++#define S3C_MSCOWIDTH_AUTOLOAD_ENABLE (1 << 31) ++ ++/* Input DMA control register */ ++#define S3C_MSCOCTRL_ORDER422_YCBYCR (0 << 4) ++#define S3C_MSCOCTRL_ORDER422_YCRYCB (1 << 4) ++#define S3C_MSCOCTRL_ORDER422_CBYCRY (2 << 4) ++#define S3C_MSCOCTRL_ORDER422_CRYCBY (3 << 4) ++#define S3C_MSCOCTRL_INPUT_EXTCAM (0 << 3) ++#define S3C_MSCOCTRL_INPUT_MEMORY (1 << 3) ++#define S3C_MSCOCTRL_INPUT_MASK (1 << 3) ++#define S3C_MSCOCTRL_INFORMAT_YCBCR420 (0 << 1) ++#define S3C_MSCOCTRL_INFORMAT_YCBCR422 (1 << 1) ++#define S3C_MSCOCTRL_INFORMAT_YCBCR422I (2 << 1) ++#define S3C_MSCOCTRL_INFORMAT_RGB (3 << 1) ++#define S3C_MSCOCTRL_ENVID (1 << 0) ++ ++/* Real input DMA size register */ ++#define S3C_MSPRWIDTH_AUTOLOAD_ENABLE (1 << 31) ++ ++/* Input DMA control register */ ++#define S3C_MSPRCTRL_ORDER422_YCBYCR (0 << 4) ++#define S3C_MSPRCTRL_ORDER422_YCRYCB (1 << 4) ++#define S3C_MSPRCTRL_ORDER422_CBYCRY (2 << 4) ++#define S3C_MSPRCTRL_ORDER422_CRYCBY (3 << 4) ++#define S3C_MSPRCTRL_INPUT_EXTCAM (0 << 3) ++#define S3C_MSPRCTRL_INPUT_MEMORY (1 << 3) ++#define S3C_MSPRCTRL_INPUT_MASK (1 << 3) ++#define S3C_MSPRCTRL_INFORMAT_YCBCR420 (0 << 1) ++#define S3C_MSPRCTRL_INFORMAT_YCBCR422 (1 << 1) ++#define S3C_MSPRCTRL_INFORMAT_YCBCR422I (2 << 1) ++#define S3C_MSPRCTRL_INFORMAT_RGB (3 << 1) ++#define S3C_MSPRCTRL_ENVID (1 << 0) ++ ++#endif /* _REGS_FIMC_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/s5p6440.h linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/s5p6440.h +--- linux-2.6.28/arch/arm/plat-s5p64xx/include/plat/s5p6440.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/include/plat/s5p6440.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,33 @@ ++/* arch/arm/plat-s5p64xx/include/plat/s5p6440.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * Header file for s5p6440 cpu support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifdef CONFIG_CPU_S5P6440 ++ ++extern void s5p6440_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); ++extern void s5p6440_register_clocks(void); ++extern void s5p6440_setup_clocks(void); ++ ++extern int s5p6440_init(void); ++extern void s5p6440_init_irq(void); ++extern void s5p6440_map_io(void); ++extern void s5p6440_init_clocks(int xtal); ++ ++#define s5p6440_init_uarts s5p6440_common_init_uarts ++ ++#else ++#define s5p6440_init_clocks NULL ++#define s5p6440_init_uarts NULL ++#define s5p6440_map_io NULL ++#define s5p6440_init NULL ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/irq-eint.c linux-2.6.28.6/arch/arm/plat-s5p64xx/irq-eint.c +--- linux-2.6.28/arch/arm/plat-s5p64xx/irq-eint.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/irq-eint.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,197 @@ ++/* arch/arm/plat-s5p64xx/irq-eint.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5P64XX - Interrupt handling for IRQ_EINT(x) ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++ ++ ++/* GPIO is 0x7F008xxx, */ ++#define S5P64XX_GPIOREG(x) (S5P64XX_VA_GPIO + (x)) ++ ++#define S5P64XX_EINT0CON0 S5P64XX_GPIOREG(0x900) ++#define S5P64XX_EINT0FLTCON0 S5P64XX_GPIOREG(0x910) ++#define S5P64XX_EINT0FLTCON1 S5P64XX_GPIOREG(0x914) ++ ++#define S5P64XX_EINT0MASK S5P64XX_GPIOREG(0x920) ++#define S5P64XX_EINT0PEND S5P64XX_GPIOREG(0x924) ++ ++ ++#define eint_offset(irq) ((irq) - IRQ_EINT(0)) ++#define eint_irq_to_bit(irq) (1 << eint_offset(irq)) ++ ++static inline void s3c_irq_eint_mask(unsigned int irq) ++{ ++ u32 mask; ++ ++ mask = __raw_readl(S5P64XX_EINT0MASK); ++ mask |= eint_irq_to_bit(irq); ++ __raw_writel(mask, S5P64XX_EINT0MASK); ++} ++ ++static void s3c_irq_eint_unmask(unsigned int irq) ++{ ++ u32 mask; ++ ++ mask = __raw_readl(S5P64XX_EINT0MASK); ++ mask &= ~(eint_irq_to_bit(irq)); ++ __raw_writel(mask, S5P64XX_EINT0MASK); ++} ++ ++static inline void s3c_irq_eint_ack(unsigned int irq) ++{ ++ __raw_writel(eint_irq_to_bit(irq), S5P64XX_EINT0PEND); ++} ++ ++static void s3c_irq_eint_maskack(unsigned int irq) ++{ ++ /* compiler should in-line these */ ++ s3c_irq_eint_mask(irq); ++ s3c_irq_eint_ack(irq); ++} ++ ++static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) ++{ ++ int offs = eint_offset(irq); ++ int shift; ++ u32 ctrl, mask; ++ u32 newvalue = 0; ++ void __iomem *reg; ++ ++ if (offs > 15) ++ return -EINVAL; ++ else ++ reg = S5P64XX_EINT0CON0; ++ ++ switch (type) { ++ case IRQ_TYPE_NONE: ++ printk(KERN_WARNING "No edge setting!\n"); ++ break; ++ ++ case IRQ_TYPE_EDGE_RISING: ++ newvalue = S3C2410_EXTINT_RISEEDGE; ++ break; ++ ++ case IRQ_TYPE_EDGE_FALLING: ++ newvalue = S3C2410_EXTINT_FALLEDGE; ++ break; ++ ++ case IRQ_TYPE_EDGE_BOTH: ++ newvalue = S3C2410_EXTINT_BOTHEDGE; ++ break; ++ ++ case IRQ_TYPE_LEVEL_LOW: ++ newvalue = S3C2410_EXTINT_LOWLEV; ++ break; ++ ++ case IRQ_TYPE_LEVEL_HIGH: ++ newvalue = S3C2410_EXTINT_HILEV; ++ break; ++ ++ default: ++ printk(KERN_ERR "No such irq type %d", type); ++ return -1; ++ } ++ ++ shift = (offs / 2) * 4; ++ mask = 0x7 << shift; ++ ++ ctrl = __raw_readl(reg); ++ ctrl &= ~mask; ++ ctrl |= newvalue << shift; ++ __raw_writel(ctrl, reg); ++ ++ s3c_gpio_cfgpin(S5P64XX_GPN(offs), 0x2 << (offs * 2)); ++ ++ return 0; ++} ++ ++static struct irq_chip s3c_irq_eint = { ++ .name = "s3c-eint", ++ .mask = s3c_irq_eint_mask, ++ .unmask = s3c_irq_eint_unmask, ++ .mask_ack = s3c_irq_eint_maskack, ++ .ack = s3c_irq_eint_ack, ++ .set_type = s3c_irq_eint_set_type, ++}; ++ ++/* s3c_irq_demux_eint ++ * ++ * This function demuxes the IRQ from the group0 external interrupts, ++ * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into ++ * the specific handlers s3c_irq_demux_eintX_Y. ++ */ ++static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end) ++{ ++ u32 status = __raw_readl(S5P64XX_EINT0PEND); ++ u32 mask = __raw_readl(S5P64XX_EINT0MASK); ++ unsigned int irq; ++ ++ status &= ~mask; ++ status >>= start; ++ status &= (1 << (end - start + 1)) - 1; ++ ++ for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) { ++ if (status & 1) ++ generic_handle_irq(irq); ++ ++ status >>= 1; ++ } ++} ++ ++static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_eint(0, 3); ++} ++ ++static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_eint(4, 11); ++} ++ ++static void s3c_irq_demux_eint12_15(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_eint(12, 15); ++} ++ ++int __init s5p64xx_init_irq_eint(void) ++{ ++ int irq; ++ ++ for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++) { ++ set_irq_chip(irq, &s3c_irq_eint); ++ set_irq_handler(irq, handle_level_irq); ++ set_irq_flags(irq, IRQF_VALID); ++ } ++ ++ set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3); ++ set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11); ++ set_irq_chained_handler(IRQ_EINT12_15, s3c_irq_demux_eint12_15); ++ ++ return 0; ++} ++ ++arch_initcall(s5p64xx_init_irq_eint); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/irq.c linux-2.6.28.6/arch/arm/plat-s5p64xx/irq.c +--- linux-2.6.28/arch/arm/plat-s5p64xx/irq.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/irq.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,257 @@ ++/* arch/arm/plat-s5p64xx/irq.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5P64XX - Interrupt handling ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++ ++/* Timer interrupt handling */ ++ ++static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq) ++{ ++ generic_handle_irq(sub_irq); ++} ++ ++static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_timer(irq, IRQ_TIMER0); ++} ++ ++static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_timer(irq, IRQ_TIMER1); ++} ++ ++static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_timer(irq, IRQ_TIMER2); ++} ++ ++static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_timer(irq, IRQ_TIMER3); ++} ++ ++static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_timer(irq, IRQ_TIMER4); ++} ++ ++/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ ++ ++static void s3c_irq_timer_mask(unsigned int irq) ++{ ++ u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); ++ ++ reg &= 0x1f; /* mask out pending interrupts */ ++ reg &= ~(1 << (irq - IRQ_TIMER0)); ++ __raw_writel(reg, S3C64XX_TINT_CSTAT); ++} ++ ++static void s3c_irq_timer_unmask(unsigned int irq) ++{ ++ u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); ++ ++ reg &= 0x1f; /* mask out pending interrupts */ ++ reg |= 1 << (irq - IRQ_TIMER0); ++ __raw_writel(reg, S3C64XX_TINT_CSTAT); ++} ++ ++static void s3c_irq_timer_ack(unsigned int irq) ++{ ++ u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); ++ ++ reg &= 0x1f; ++ reg |= (1 << 5) << (irq - IRQ_TIMER0); ++ __raw_writel(reg, S3C64XX_TINT_CSTAT); ++} ++ ++static struct irq_chip s3c_irq_timer = { ++ .name = "s3c-timer", ++ .mask = s3c_irq_timer_mask, ++ .unmask = s3c_irq_timer_unmask, ++ .ack = s3c_irq_timer_ack, ++}; ++ ++struct uart_irq { ++ void __iomem *regs; ++ unsigned int base_irq; ++ unsigned int parent_irq; ++}; ++ ++/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] ++ * are consecutive when looking up the interrupt in the demux routines. ++ */ ++static struct uart_irq uart_irqs[] = { ++ [0] = { ++ .regs = S3C_VA_UART0, ++ .base_irq = IRQ_S3CUART_BASE0, ++ .parent_irq = IRQ_UART0, ++ }, ++ [1] = { ++ .regs = S3C_VA_UART1, ++ .base_irq = IRQ_S3CUART_BASE1, ++ .parent_irq = IRQ_UART1, ++ }, ++ [2] = { ++ .regs = S3C_VA_UART2, ++ .base_irq = IRQ_S3CUART_BASE2, ++ .parent_irq = IRQ_UART2, ++ }, ++ [3] = { ++ .regs = S3C_VA_UART3, ++ .base_irq = IRQ_S3CUART_BASE3, ++ .parent_irq = IRQ_UART3, ++ }, ++}; ++ ++static inline void __iomem *s3c_irq_uart_base(unsigned int irq) ++{ ++ struct uart_irq *uirq = get_irq_chip_data(irq); ++ return uirq->regs; ++} ++ ++static inline unsigned int s3c_irq_uart_bit(unsigned int irq) ++{ ++ return irq & 3; ++} ++ ++/* UART interrupt registers, not worth adding to seperate include header */ ++#define S5P64XX_UINTP 0x30 ++#define S5P64XX_UINTSP 0x34 ++#define S5P64XX_UINTM 0x38 ++ ++static void s3c_irq_uart_mask(unsigned int irq) ++{ ++ void __iomem *regs = s3c_irq_uart_base(irq); ++ unsigned int bit = s3c_irq_uart_bit(irq); ++ u32 reg; ++ ++ reg = __raw_readl(regs + S5P64XX_UINTM); ++ reg |= (1 << bit); ++ __raw_writel(reg, regs + S5P64XX_UINTM); ++} ++ ++static void s3c_irq_uart_maskack(unsigned int irq) ++{ ++ void __iomem *regs = s3c_irq_uart_base(irq); ++ unsigned int bit = s3c_irq_uart_bit(irq); ++ u32 reg; ++ ++ reg = __raw_readl(regs + S5P64XX_UINTM); ++ reg |= (1 << bit); ++ __raw_writel(reg, regs + S5P64XX_UINTM); ++ __raw_writel(1 << bit, regs + S5P64XX_UINTP); ++} ++ ++static void s3c_irq_uart_unmask(unsigned int irq) ++{ ++ void __iomem *regs = s3c_irq_uart_base(irq); ++ unsigned int bit = s3c_irq_uart_bit(irq); ++ u32 reg; ++ ++ reg = __raw_readl(regs + S5P64XX_UINTM); ++ reg &= ~(1 << bit); ++ __raw_writel(reg, regs + S5P64XX_UINTM); ++} ++ ++static void s3c_irq_uart_ack(unsigned int irq) ++{ ++ void __iomem *regs = s3c_irq_uart_base(irq); ++ unsigned int bit = s3c_irq_uart_bit(irq); ++ ++ __raw_writel(1 << bit, regs + S5P64XX_UINTP); ++} ++ ++static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) ++{ ++ struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0]; ++ u32 pend = __raw_readl(uirq->regs + S5P64XX_UINTP); ++ int base = uirq->base_irq; ++ ++ if (pend & (1 << 0)) ++ generic_handle_irq(base); ++ if (pend & (1 << 1)) ++ generic_handle_irq(base + 1); ++ if (pend & (1 << 2)) ++ generic_handle_irq(base + 2); ++ if (pend & (1 << 3)) ++ generic_handle_irq(base + 3); ++} ++ ++static struct irq_chip s3c_irq_uart = { ++ .name = "s3c-uart", ++ .mask = s3c_irq_uart_mask, ++ .unmask = s3c_irq_uart_unmask, ++ .mask_ack = s3c_irq_uart_maskack, ++ .ack = s3c_irq_uart_ack, ++}; ++ ++static void __init s5p64xx_uart_irq(struct uart_irq *uirq) ++{ ++ void *reg_base = uirq->regs; ++ unsigned int irq; ++ int offs; ++ ++ /* mask all interrupts at the start. */ ++ __raw_writel(0xf, reg_base + S5P64XX_UINTM); ++ ++ for (offs = 0; offs < 3; offs++) { ++ irq = uirq->base_irq + offs; ++ ++ set_irq_chip(irq, &s3c_irq_uart); ++ set_irq_chip_data(irq, uirq); ++ set_irq_handler(irq, handle_level_irq); ++ set_irq_flags(irq, IRQF_VALID); ++ } ++ ++ set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); ++} ++ ++void __init s5p64xx_init_irq(u32 vic0_valid, u32 vic1_valid) ++{ ++ int uart, irq; ++ ++ printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); ++ ++ /* initialise the pair of VICs */ ++ vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid); ++ vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid); ++ ++ /* add the timer sub-irqs */ ++ ++ set_irq_chained_handler(IRQ_TIMER0_VIC, s3c_irq_demux_timer0); ++ set_irq_chained_handler(IRQ_TIMER1_VIC, s3c_irq_demux_timer1); ++ set_irq_chained_handler(IRQ_TIMER2_VIC, s3c_irq_demux_timer2); ++ set_irq_chained_handler(IRQ_TIMER3_VIC, s3c_irq_demux_timer3); ++ set_irq_chained_handler(IRQ_TIMER4_VIC, s3c_irq_demux_timer4); ++ ++ for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) { ++ set_irq_chip(irq, &s3c_irq_timer); ++ set_irq_handler(irq, handle_level_irq); ++ set_irq_flags(irq, IRQF_VALID); ++ } ++ ++ for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++) ++ s5p64xx_uart_irq(&uart_irqs[uart]); ++} ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/ltc3714.c linux-2.6.28.6/arch/arm/plat-s5p64xx/ltc3714.c +--- linux-2.6.28/arch/arm/plat-s5p64xx/ltc3714.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/ltc3714.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,147 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#define ARM_LE 0 ++#define INT_LE 1 ++ ++enum PMIC_VOLTAGE { ++ VOUT_1_00, ++ VOUT_1_05, ++ VOUT_1_10, ++ VOUT_1_15, ++ VOUT_1_20, ++ VOUT_1_25, ++ VOUT_1_30, ++ VOUT_1_35, ++ VOUT_1_40, ++ VOUT_1_45, ++ VOUT_1_50 ++}; ++ ++/* ltc3714 voltage table */ ++static const unsigned int voltage_table[11] = { ++ 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9, ++ 0x8, 0x7, 0x6, 0x5, ++}; ++ ++#define L0 532*1000 ++#define L1 266*1000 ++#define L2 133*1000 ++ ++/* frequency voltage matching table */ ++static const unsigned int frequency_match[][3] = { ++/* frequency, Mathced VDD ARM voltage , Matched VDD INT*/ ++ {L0, VOUT_1_10, VOUT_1_10}, ++ {L1, VOUT_1_10, VOUT_1_10}, ++ {L2, VOUT_1_10, VOUT_1_10}, ++}; ++ ++/* LTC3714 Setting Routine */ ++static int ltc3714_gpio_setting(void) ++{ ++ gpio_direction_output(S5P64XX_GPN(11), 0); ++ gpio_direction_output(S5P64XX_GPN(12), 0); ++ gpio_direction_output(S5P64XX_GPN(13), 0); ++ gpio_direction_output(S5P64XX_GPN(14), 0); ++ gpio_direction_output(S5P64XX_GPN(15), 0); ++ gpio_direction_output(S5P64XX_GPR(0), 0); ++ gpio_direction_output(S5P64XX_GPR(1), 0); ++ gpio_direction_output(S5P64XX_GPR(2), 0); ++ ++ s3c_gpio_setpull(S5P64XX_GPN(11), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S5P64XX_GPN(12), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S5P64XX_GPN(13), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S5P64XX_GPN(14), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S5P64XX_GPN(15), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S5P64XX_GPR(8), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S5P64XX_GPR(9), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S5P64XX_GPR(10), S3C_GPIO_PULL_NONE); ++ ++ return 0; ++} ++ ++static int set_ltc3714(unsigned int pwr, unsigned int index) ++{ ++ int position = 0; ++ int gpio_val; ++ int voltage = frequency_match[index][pwr + 1]; ++ ++ gpio_val = voltage_table[voltage]; ++ ++ gpio_val &=0x1f; ++ ++ gpio_set_value(S5P64XX_GPN(11),(position >> 0)&0x1); ++ gpio_set_value(S5P64XX_GPN(12),(position >> 1)&0x1); ++ gpio_set_value(S5P64XX_GPN(13),(position >> 2)&0x1); ++ gpio_set_value(S5P64XX_GPN(14),(position >> 3)&0x1); ++ gpio_set_value(S5P64XX_GPN(15),(position >> 4)&0x1); ++ ++ if(pwr == ARM_LE) { ++ gpio_set_value(S5P64XX_GPR(8), 1); ++ udelay(10); ++ gpio_set_value(S5P64XX_GPR(8), 0); ++ } else if(pwr == INT_LE) { ++ gpio_set_value(S5P64XX_GPR(10), 1); ++ udelay(10); ++ gpio_set_value(S5P64XX_GPR(10), 0); ++ } else { ++ printk("[error]: set_power, check mode [pwr] value\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int find_voltage(int freq) ++{ ++ int index = 0; ++ ++ if(freq > frequency_match[0][0]){ ++ printk(KERN_ERR "frequecy is over then support frequency\n"); ++ return 0; ++ } ++ ++ for(index = 0 ; index < ARRAY_SIZE(frequency_match) ; index++){ ++ if(freq >= frequency_match[index][0]) ++ return index; ++ } ++ ++ printk("Cannot find matched voltage on table\n"); ++ ++ return 0; ++} ++ ++int set_power(unsigned int freq) ++{ ++ int index; ++ ++ index = find_voltage(freq); ++ ++ set_ltc3714(ARM_LE, index); ++ ++ return 0; ++} ++ ++EXPORT_SYMBOL(set_power); ++ ++void ltc3714_init(void) ++{ ++ ltc3714_gpio_setting(); ++ set_power(L0); ++ gpio_set_value(S5P64XX_GPR(9), 1); ++} ++ ++EXPORT_SYMBOL(ltc3714_init); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/pm.c linux-2.6.28.6/arch/arm/plat-s5p64xx/pm.c +--- linux-2.6.28/arch/arm/plat-s5p64xx/pm.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/pm.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,652 @@ ++/* linux/arch/arm/plat-s3c24xx/pm.c ++ * ++ * Copyright (c) 2004,2006 Simtec Electronics ++ * Ben Dooks ++ * ++ * S3C24XX Power Manager (Suspend-To-RAM) support ++ * ++ * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * Parts based on arch/arm/mach-pxa/pm.c ++ * ++ * Thanks to Dimitry Andric for debugging ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++ ++/* for external use */ ++ ++unsigned long s3c_pm_flags; ++ ++#define PFX "s3c64xx-pm: " ++static struct sleep_save core_save[] = { ++// SAVE_ITEM(S3C_SDMA_SEL), ++}; ++ ++static struct sleep_save gpio_save[] = { ++ SAVE_ITEM(S5P64XX_GPACON), ++ SAVE_ITEM(S5P64XX_GPADAT), ++ SAVE_ITEM(S5P64XX_GPAPUD), ++ SAVE_ITEM(S5P64XX_GPBCON), ++ SAVE_ITEM(S5P64XX_GPBDAT), ++ SAVE_ITEM(S5P64XX_GPBPUD), ++ SAVE_ITEM(S5P64XX_GPCCON), ++ SAVE_ITEM(S5P64XX_GPCDAT), ++ SAVE_ITEM(S5P64XX_GPCPUD), ++ SAVE_ITEM(S5P64XX_GPFCON), ++ SAVE_ITEM(S5P64XX_GPFDAT), ++ SAVE_ITEM(S5P64XX_GPFPUD), ++ SAVE_ITEM(S5P64XX_GPGCON), ++ SAVE_ITEM(S5P64XX_GPGDAT), ++ SAVE_ITEM(S5P64XX_GPGPUD), ++ SAVE_ITEM(S5P64XX_GPHCON0), ++ SAVE_ITEM(S5P64XX_GPHCON1), ++ SAVE_ITEM(S5P64XX_GPHDAT), ++ SAVE_ITEM(S5P64XX_GPHPUD), ++ SAVE_ITEM(S5P64XX_GPICON), ++ SAVE_ITEM(S5P64XX_GPIDAT), ++ SAVE_ITEM(S5P64XX_GPIPUD), ++ SAVE_ITEM(S5P64XX_GPJCON), ++ SAVE_ITEM(S5P64XX_GPJDAT), ++ SAVE_ITEM(S5P64XX_GPJPUD), ++ SAVE_ITEM(S5P64XX_GPNCON), ++ SAVE_ITEM(S5P64XX_GPNDAT), ++ SAVE_ITEM(S5P64XX_GPNPUD), ++ SAVE_ITEM(S5P64XX_GPPCON), ++ SAVE_ITEM(S5P64XX_GPPDAT), ++ SAVE_ITEM(S5P64XX_GPPPUD), ++ ++ /* Special register */ ++ SAVE_ITEM(S5P64XX_SPC_BASE), ++}; ++ ++/* this lot should be really saved by the IRQ code */ ++/* VICXADDRESSXX initilaization to be needed */ ++static struct sleep_save irq_save[] = { ++ SAVE_ITEM(S5P64XX_VIC0INTSELECT), ++ SAVE_ITEM(S5P64XX_VIC1INTSELECT), ++ SAVE_ITEM(S5P64XX_VIC0INTENABLE), ++ SAVE_ITEM(S5P64XX_VIC1INTENABLE), ++ SAVE_ITEM(S5P64XX_VIC0SOFTINT), ++ SAVE_ITEM(S5P64XX_VIC1SOFTINT), ++}; ++ ++static struct sleep_save sromc_save[] = { ++ SAVE_ITEM(S5P64XX_SROM_BW), ++ SAVE_ITEM(S5P64XX_SROM_BC0), ++ SAVE_ITEM(S5P64XX_SROM_BC1), ++ SAVE_ITEM(S5P64XX_SROM_BC2), ++ SAVE_ITEM(S5P64XX_SROM_BC3), ++ SAVE_ITEM(S5P64XX_SROM_BC4), ++ SAVE_ITEM(S5P64XX_SROM_BC5), ++}; ++ ++#ifdef CONFIG_S3C2410_PM_DEBUG ++ ++#define SAVE_UART(va) \ ++ SAVE_ITEM((va) + S3C2410_ULCON), \ ++ SAVE_ITEM((va) + S3C2410_UCON), \ ++ SAVE_ITEM((va) + S3C2410_UFCON), \ ++ SAVE_ITEM((va) + S3C2410_UMCON), \ ++ SAVE_ITEM((va) + S3C2410_UBRDIV) ++ ++static struct sleep_save uart_save[] = { ++ SAVE_UART(S3C24XX_VA_UART0), ++ SAVE_UART(S3C24XX_VA_UART1), ++#ifndef CONFIG_CPU_S3C2400 ++ SAVE_UART(S3C24XX_VA_UART2), ++#endif ++}; ++ ++/* debug ++ * ++ * we send the debug to printascii() to allow it to be seen if the ++ * system never wakes up from the sleep ++*/ ++ ++extern void printascii(const char *); ++ ++void pm_dbg(const char *fmt, ...) ++{ ++ va_list va; ++ char buff[256]; ++ ++ va_start(va, fmt); ++ vsprintf(buff, fmt, va); ++ va_end(va); ++ ++ printascii(buff); ++} ++ ++static void s3c2410_pm_debug_init(void) ++{ ++ unsigned long tmp = __raw_readl(S3C2410_CLKCON); ++ ++ /* re-start uart clocks */ ++ tmp |= S3C2410_CLKCON_UART0; ++ tmp |= S3C2410_CLKCON_UART1; ++ tmp |= S3C2410_CLKCON_UART2; ++ ++ __raw_writel(tmp, S3C2410_CLKCON); ++ udelay(10); ++} ++ ++#define DBG(fmt...) pm_dbg(fmt) ++#else ++#define DBG(fmt...) ++ ++#define s5p6440_pm_debug_init() do { } while(0) ++#endif ++ ++#if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0 ++ ++/* suspend checking code... ++ * ++ * this next area does a set of crc checks over all the installed ++ * memory, so the system can verify if the resume was ok. ++ * ++ * CONFIG_S3C6410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC, ++ * increasing it will mean that the area corrupted will be less easy to spot, ++ * and reducing the size will cause the CRC save area to grow ++*/ ++ ++#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024) ++ ++static u32 crc_size; /* size needed for the crc block */ ++static u32 *crcs; /* allocated over suspend/resume */ ++ ++typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg); ++ ++/* s5p6440_pm_run_res ++ * ++ * go thorugh the given resource list, and look for system ram ++*/ ++ ++static void s5p6440_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg) ++{ ++ while (ptr != NULL) { ++ if (ptr->child != NULL) ++ s5p6440_pm_run_res(ptr->child, fn, arg); ++ ++ if ((ptr->flags & IORESOURCE_MEM) && ++ strcmp(ptr->name, "System RAM") == 0) { ++ DBG("Found system RAM at %08lx..%08lx\n", ++ ptr->start, ptr->end); ++ arg = (fn)(ptr, arg); ++ } ++ ++ ptr = ptr->sibling; ++ } ++} ++ ++static void s5p6440_pm_run_sysram(run_fn_t fn, u32 *arg) ++{ ++ s5p6440_pm_run_res(&iomem_resource, fn, arg); ++} ++ ++static u32 *s5p6440_pm_countram(struct resource *res, u32 *val) ++{ ++ u32 size = (u32)(res->end - res->start)+1; ++ ++ size += CHECK_CHUNKSIZE-1; ++ size /= CHECK_CHUNKSIZE; ++ ++ DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size); ++ ++ *val += size * sizeof(u32); ++ return val; ++} ++ ++/* s5p6440_pm_prepare_check ++ * ++ * prepare the necessary information for creating the CRCs. This ++ * must be done before the final save, as it will require memory ++ * allocating, and thus touching bits of the kernel we do not ++ * know about. ++*/ ++ ++static void s5p6440_pm_check_prepare(void) ++{ ++ crc_size = 0; ++ ++ s5p6440_pm_run_sysram(s5p6440_pm_countram, &crc_size); ++ ++ DBG("s5p6440_pm_prepare_check: %u checks needed\n", crc_size); ++ ++ crcs = kmalloc(crc_size+4, GFP_KERNEL); ++ if (crcs == NULL) ++ printk(KERN_ERR "Cannot allocated CRC save area\n"); ++} ++ ++static u32 *s5p6440_pm_makecheck(struct resource *res, u32 *val) ++{ ++ unsigned long addr, left; ++ ++ for (addr = res->start; addr < res->end; ++ addr += CHECK_CHUNKSIZE) { ++ left = res->end - addr; ++ ++ if (left > CHECK_CHUNKSIZE) ++ left = CHECK_CHUNKSIZE; ++ ++ *val = crc32_le(~0, phys_to_virt(addr), left); ++ val++; ++ } ++ ++ return val; ++} ++ ++/* s5p6440_pm_check_store ++ * ++ * compute the CRC values for the memory blocks before the final ++ * sleep. ++*/ ++ ++static void s5p6440_pm_check_store(void) ++{ ++ if (crcs != NULL) ++ s5p6440_pm_run_sysram(s5p6440_pm_makecheck, crcs); ++} ++ ++/* in_region ++ * ++ * return TRUE if the area defined by ptr..ptr+size contatins the ++ * what..what+whatsz ++*/ ++ ++static inline int in_region(void *ptr, int size, void *what, size_t whatsz) ++{ ++ if ((what+whatsz) < ptr) ++ return 0; ++ ++ if (what > (ptr+size)) ++ return 0; ++ ++ return 1; ++} ++ ++static u32 *s5p6440_pm_runcheck(struct resource *res, u32 *val) ++{ ++ void *save_at = phys_to_virt(s5p6440_sleep_save_phys); ++ unsigned long addr; ++ unsigned long left; ++ void *ptr; ++ u32 calc; ++ ++ for (addr = res->start; addr < res->end; ++ addr += CHECK_CHUNKSIZE) { ++ left = res->end - addr; ++ ++ if (left > CHECK_CHUNKSIZE) ++ left = CHECK_CHUNKSIZE; ++ ++ ptr = phys_to_virt(addr); ++ ++ if (in_region(ptr, left, crcs, crc_size)) { ++ DBG("skipping %08lx, has crc block in\n", addr); ++ goto skip_check; ++ } ++ ++ if (in_region(ptr, left, save_at, 32*4 )) { ++ DBG("skipping %08lx, has save block in\n", addr); ++ goto skip_check; ++ } ++ ++ /* calculate and check the checksum */ ++ ++ calc = crc32_le(~0, ptr, left); ++ if (calc != *val) { ++ printk(KERN_ERR PFX "Restore CRC error at " ++ "%08lx (%08x vs %08x)\n", addr, calc, *val); ++ ++ DBG("Restore CRC error at %08lx (%08x vs %08x)\n", ++ addr, calc, *val); ++ } ++ ++ skip_check: ++ val++; ++ } ++ ++ return val; ++} ++ ++/* s5p6440_pm_check_restore ++ * ++ * check the CRCs after the restore event and free the memory used ++ * to hold them ++*/ ++ ++static void s5p6440_pm_check_restore(void) ++{ ++ if (crcs != NULL) { ++ s5p6440_pm_run_sysram(s5p6440_pm_runcheck, crcs); ++ kfree(crcs); ++ crcs = NULL; ++ } ++} ++ ++#else ++ ++#define s5p6440_pm_check_prepare() do { } while(0) ++#define s5p6440_pm_check_restore() do { } while(0) ++#define s5p6440_pm_check_store() do { } while(0) ++#endif ++ ++/* helper functions to save and restore register state */ ++ ++void s5p6440_pm_do_save(struct sleep_save *ptr, int count) ++{ ++ for (; count > 0; count--, ptr++) { ++ ptr->val = __raw_readl(ptr->reg); ++ //DBG("saved %p value %08lx\n", ptr->reg, ptr->val); ++ } ++} ++ ++/* s5p6440_pm_do_restore ++ * ++ * restore the system from the given list of saved registers ++ * ++ * Note, we do not use DBG() in here, as the system may not have ++ * restore the UARTs state yet ++*/ ++ ++void s5p6440_pm_do_restore(struct sleep_save *ptr, int count) ++{ ++ for (; count > 0; count--, ptr++) { ++ //printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n", ++ //ptr->reg, ptr->val, __raw_readl(ptr->reg)); ++ ++ __raw_writel(ptr->val, ptr->reg); ++ } ++} ++ ++/* s5p6440_pm_do_restore_core ++ * ++ * similar to s36410_pm_do_restore_core ++ * ++ * WARNING: Do not put any debug in here that may effect memory or use ++ * peripherals, as things may be changing! ++*/ ++ ++/* s5p6440_pm_do_save_phy ++ * ++ * save register of system ++ * ++ * Note, I made this function to support driver with ioremap. ++ * If you want to use this function, you should to input as first parameter ++ * struct sleep_save_phy type ++*/ ++ ++int s3c2410_pm_do_save_phy(struct sleep_save_phy *ptr, struct platform_device *pdev, int count) ++{ ++ void __iomem *target_reg; ++ struct resource *res; ++ u32 reg_size; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if(res == NULL){ ++ printk(KERN_ERR "%s resource get error\n",__FUNCTION__); ++ return 0; ++ } ++ reg_size = res->end - res->start + 1; ++ target_reg = ioremap(res->start,reg_size); ++ ++ for (; count > 0; count--, ptr++) { ++ ptr->val = readl(target_reg + (ptr->reg)); ++ } ++ ++ return 0; ++} ++ ++/* s5p6440_pm_do_restore_phy ++ * ++ * restore register of system ++ * ++ * Note, I made this function to support driver with ioremap. ++ * If you want to use this function, you should to input as first parameter ++ * struct sleep_save_phy type ++*/ ++ ++int s3c2410_pm_do_restore_phy(struct sleep_save_phy *ptr, struct platform_device *pdev, int count) ++{ ++ void __iomem *target_reg; ++ struct resource *res; ++ u32 reg_size; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if(res == NULL){ ++ printk(KERN_ERR "%s resource get error\n",__FUNCTION__); ++ return 0; ++ } ++ reg_size = res->end - res->start + 1; ++ target_reg = ioremap(res->start,reg_size); ++ ++ for (; count > 0; count--, ptr++) { ++ writel(ptr->val, (target_reg + ptr->reg)); ++ } ++ ++ return 0; ++} ++ ++static void s5p6440_pm_do_restore_core(struct sleep_save *ptr, int count) ++{ ++ for (; count > 0; count--, ptr++) { ++ __raw_writel(ptr->val, ptr->reg); ++ } ++} ++ ++static void s5p6440_pm_configure_extint(void) ++{ ++#if 0 ++ s3c_gpio_cfgpin(S5P64XX_GPN(10), S5P64XX_GPN10_EINT10); ++ s3c_gpio_setpull(S5P64XX_GPN(10), S3C_GPIO_PULL_UP); ++#else ++ __raw_writel((__raw_readl(S5P64XX_GPNCON) & ~(0x3 << 20)) | ++ (0x2 << 20), S5P64XX_GPNCON); ++ __raw_writel((__raw_readl(S5P64XX_GPNPUD) & ~(0x3 << 20)) | ++ (0x2 << 20), S5P64XX_GPNPUD); ++#endif ++ udelay(50); ++ ++ __raw_writel((__raw_readl(S5P64XX_EINT0CON0) & ~(0x7 << 20)) | ++ (0x2 << 20), S5P64XX_EINT0CON0); ++ ++ __raw_writel(1UL << (IRQ_EINT(10) - IRQ_EINT(0)), S5P64XX_EINT0PEND); ++ __raw_writel(__raw_readl(S5P64XX_EINT0MASK)&~(1UL << (IRQ_EINT(10) - IRQ_EINT(0))), S5P64XX_EINT0MASK); ++ ++} ++ ++static void s5p64xx_pm_configure_extint(void) ++{ ++#if 0 ++ s3c_gpio_cfgpin(S5P64XX_GPN(10), S5P64XX_GPN10_EINT10); ++ s3c_gpio_setpull(S5P64XX_GPN(10), S3C_GPIO_PULL_UP); ++#else ++ __raw_writel((__raw_readl(S5P64XX_GPNCON) & ~(0x3 << 20)) | ++ (0x2 << 20), S5P64XX_GPNCON); ++ __raw_writel((__raw_readl(S5P64XX_GPNPUD) & ~(0x3 << 20)) | ++ (0x2 << 20), S5P64XX_GPNPUD); ++#endif ++ udelay(50); ++ ++ __raw_writel((__raw_readl(S5P64XX_EINT0CON0) & ~(0x7 << 20)) | ++ (0x2 << 20), S5P64XX_EINT0CON0); ++ ++ __raw_writel(1UL << (IRQ_EINT(10) - IRQ_EINT(0)), S5P64XX_EINT0PEND); ++ __raw_writel(__raw_readl(S5P64XX_EINT0MASK)&~(1UL << (IRQ_EINT(10) - IRQ_EINT(0))), S5P64XX_EINT0MASK); ++ ++} ++ ++void (*pm_cpu_prep)(void); ++void (*pm_cpu_sleep)(void); ++ ++#define any_allowed(mask, allow) (((mask) & (allow)) != (allow)) ++ ++/* s5p6440_pm_enter ++ * ++ * central control for sleep/resume process ++*/ ++ ++static int s5p6440_pm_enter(suspend_state_t state) ++{ ++ unsigned long regs_save[16]; ++ unsigned int tmp; ++ ++ /* ensure the debug is initialised (if enabled) */ ++ ++ DBG("s5p6440_pm_enter(%d)\n", state); ++ ++ if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) { ++ printk(KERN_ERR PFX "error: no cpu sleep functions set\n"); ++ return -EINVAL; ++ } ++ ++ /* prepare check area if configured */ ++ s5p6440_pm_check_prepare(); ++ ++ /* store the physical address of the register recovery block */ ++ s5p6440_sleep_save_phys = virt_to_phys(regs_save); ++ ++ printk("s5p6440_sleep_save_phys=0x%08lx\n", s5p6440_sleep_save_phys); ++ ++ /* save all necessary core registers not covered by the drivers */ ++ ++ s5p6440_pm_do_save(gpio_save, ARRAY_SIZE(gpio_save)); ++ s5p6440_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); ++ s5p6440_pm_do_save(core_save, ARRAY_SIZE(core_save)); ++ s5p6440_pm_do_save(sromc_save, ARRAY_SIZE(sromc_save)); ++ ++ /* ensure INF_REG0 has the resume address */ ++ __raw_writel(virt_to_phys(s5p6440_cpu_resume), S3C_INFORM0); ++ ++ /* set the irq configuration for wake */ ++ s5p6440_pm_configure_extint(); ++ ++ /* call cpu specific preperation */ ++ ++ pm_cpu_prep(); ++ ++ /* flush cache back to ram */ ++ ++ flush_cache_all(); ++ ++ s5p6440_pm_check_store(); ++ ++ /* send the cpu to sleep... */ ++ ++ __raw_writel(0xffffffff, S5P64XX_VIC0INTENCLEAR); ++ __raw_writel(0xffffffff, S5P64XX_VIC1INTENCLEAR); ++ __raw_writel(0xffffffff, S5P64XX_VIC0SOFTINTCLEAR); ++ __raw_writel(0xffffffff, S5P64XX_VIC1SOFTINTCLEAR); ++ ++ __raw_writel(1, S3C_OSC_STABLE); ++ __raw_writel(1, S3C_PWR_STABLE); ++ ++ /* Set WFI instruction to SLEEP mode */ ++ ++ tmp = __raw_readl(S3C_PWR_CFG); ++ tmp &= ~(0x60<<0); ++ tmp |= (0x3<<5); ++ __raw_writel(tmp, S3C_PWR_CFG); ++ ++ tmp = __raw_readl(S3C_SLEEP_CFG); ++ tmp &= ~(0x61<<0); ++ __raw_writel(tmp, S3C_SLEEP_CFG); ++ ++ /* Clear WAKEUP_STAT register for next wakeup -jc.lee */ ++ /* If this register do not be cleared, Wakeup will be failed */ ++ tmp = __raw_readl(S3C_WAKEUP_STAT); ++ __raw_writel(tmp, S3C_WAKEUP_STAT); ++ ++ /* s5p6440_cpu_save will also act as our return point from when ++ * we resume as it saves its own register state, so use the return ++ * code to differentiate return from save and return from sleep */ ++ ++ if (s5p6440_cpu_save(regs_save) == 0) { ++ flush_cache_all(); ++ pm_cpu_sleep(); ++ } ++ ++ /* restore the cpu state */ ++ cpu_init(); ++ ++ /* restore the system state */ ++ s5p6440_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); ++ s5p6440_pm_do_restore(sromc_save, ARRAY_SIZE(sromc_save)); ++ s5p6440_pm_do_restore(gpio_save, ARRAY_SIZE(gpio_save)); ++ s5p6440_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); ++ ++#if 0 ++ tmp = __raw_readl(S3C64XX_EINT0PEND); ++ __raw_writel(tmp, S5P64XX_EINT0PEND); ++#endif ++ ++ DBG("post sleep, preparing to return\n"); ++ ++ s5p6440_pm_check_restore(); ++ ++ /* ok, let's return from sleep */ ++ DBG("S3C6410 PM Resume (post-restore)\n"); ++ return 0; ++} ++ ++static struct platform_suspend_ops s5p6440_pm_ops = { ++ .enter = s5p6440_pm_enter, ++ .valid = suspend_valid_only_mem, ++}; ++ ++/* s5p6440_pm_init ++ * ++ * Attach the power management functions. This should be called ++ * from the board specific initialisation if the board supports ++ * it. ++*/ ++ ++int __init s5p6440_pm_init(void) ++{ ++ printk("S5P6440 Power Management, (c) 2008 Samsung Electronics\n"); ++ ++ suspend_set_ops(&s5p6440_pm_ops); ++ return 0; ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/pwm.c linux-2.6.28.6/arch/arm/plat-s5p64xx/pwm.c +--- linux-2.6.28/arch/arm/plat-s5p64xx/pwm.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/pwm.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,432 @@ ++/* arch/arm/plat-s3c24xx/pwm.c ++ * ++ * Copyright (c) 2007 Ben Dooks ++ * Copyright (c) 2008 Simtec Electronics ++ * Ben Dooks , ++ * ++ * S3C24XX PWM device core ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct pwm_device { ++ struct list_head list; ++ struct platform_device *pdev; ++ ++ struct clk *clk_div; ++ struct clk *clk; ++ const char *label; ++ ++ unsigned int period_ns; ++ unsigned int duty_ns; ++ ++ unsigned char tcon_base; ++ unsigned char running; ++ unsigned char use_count; ++ unsigned char pwm_id; ++}; ++ ++#define pwm_dbg(_pwm, msg...) dev_dbg(&(_pwm)->pdev->dev, msg) ++ ++static struct clk *clk_scaler[2]; ++ ++/* Standard setup for a timer block. */ ++ ++#define TIMER_RESOURCE_SIZE (1) ++ ++#define TIMER_RESOURCE(_tmr, _irq) \ ++ (struct resource [TIMER_RESOURCE_SIZE]) { \ ++ [0] = { \ ++ .start = _irq, \ ++ .end = _irq, \ ++ .flags = IORESOURCE_IRQ \ ++ } \ ++ } ++ ++#define DEFINE_S3C_TIMER(_tmr_no, _irq) \ ++ .name = "s3c24xx-pwm", \ ++ .id = _tmr_no, \ ++ .num_resources = TIMER_RESOURCE_SIZE, \ ++ .resource = TIMER_RESOURCE(_tmr_no, _irq), \ ++ ++/* since we already have an static mapping for the timer, we do not ++ * bother setting any IO resource for the base. ++ */ ++ ++struct platform_device s3c_device_timer[] = { ++ [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) }, ++ [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) }, ++ [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) }, ++ [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) }, ++ [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) }, ++}; ++ ++static inline int pwm_is_tdiv(struct pwm_device *pwm) ++{ ++ return clk_get_parent(pwm->clk) == pwm->clk_div; ++} ++ ++static DEFINE_MUTEX(pwm_lock); ++static LIST_HEAD(pwm_list); ++ ++struct pwm_device *pwm_request(int pwm_id, const char *label) ++{ ++ struct pwm_device *pwm; ++ int found = 0; ++ ++ mutex_lock(&pwm_lock); ++ ++ list_for_each_entry(pwm, &pwm_list, list) { ++ if (pwm->pwm_id == pwm_id) { ++ found = 1; ++ break; ++ } ++ } ++ ++ if (found) { ++ if (pwm->use_count == 0) { ++ pwm->use_count = 1; ++ pwm->label = label; ++ } else ++ pwm = ERR_PTR(-EBUSY); ++ } else ++ pwm = ERR_PTR(-ENOENT); ++ ++ mutex_unlock(&pwm_lock); ++ return pwm; ++} ++ ++EXPORT_SYMBOL(pwm_request); ++ ++ ++void pwm_free(struct pwm_device *pwm) ++{ ++ mutex_lock(&pwm_lock); ++ ++ if (pwm->use_count) { ++ pwm->use_count--; ++ pwm->label = NULL; ++ } else ++ printk(KERN_ERR "PWM%d device already freed\n", pwm->pwm_id); ++ ++ mutex_unlock(&pwm_lock); ++} ++ ++EXPORT_SYMBOL(pwm_free); ++ ++#define pwm_tcon_start(pwm) (1 << (pwm->tcon_base + 0)) ++#define pwm_tcon_invert(pwm) (1 << (pwm->tcon_base + 2)) ++#define pwm_tcon_autoreload(pwm) (1 << (pwm->tcon_base + 3)) ++#define pwm_tcon_manulupdate(pwm) (1 << (pwm->tcon_base + 1)) ++ ++int pwm_enable(struct pwm_device *pwm) ++{ ++ unsigned long flags; ++ unsigned long tcon; ++ ++ local_irq_save(flags); ++ ++ tcon = __raw_readl(S3C2410_TCON); ++ tcon |= pwm_tcon_start(pwm); ++ __raw_writel(tcon, S3C2410_TCON); ++ ++ local_irq_restore(flags); ++ ++ pwm->running = 1; ++ return 0; ++} ++ ++EXPORT_SYMBOL(pwm_enable); ++ ++void pwm_disable(struct pwm_device *pwm) ++{ ++ unsigned long flags; ++ unsigned long tcon; ++ ++ local_irq_save(flags); ++ ++ tcon = __raw_readl(S3C2410_TCON); ++ tcon &= ~pwm_tcon_start(pwm); ++ __raw_writel(tcon, S3C2410_TCON); ++ ++ local_irq_restore(flags); ++ ++ pwm->running = 0; ++} ++ ++EXPORT_SYMBOL(pwm_disable); ++ ++static unsigned long pwm_calc_tin(struct pwm_device *pwm, unsigned long freq) ++{ ++ unsigned long tin_parent_rate; ++ unsigned int div; ++ ++ tin_parent_rate = clk_get_rate(clk_get_parent(pwm->clk_div)); ++ pwm_dbg(pwm, "tin parent at %lu\n", tin_parent_rate); ++ ++ for (div = 2; div <= 16; div *= 2) { ++ if ((tin_parent_rate / (div << 16)) < freq) ++ return tin_parent_rate / div; ++ } ++ ++ return tin_parent_rate / 16; ++} ++ ++#define NS_IN_HZ (1000000000UL) ++ ++int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) ++{ ++ unsigned long tin_rate; ++ unsigned long tin_ns; ++ unsigned long period; ++ unsigned long flags; ++ unsigned long tcon; ++ unsigned long tcnt; ++ long tcmp; ++ ++ /* We currently avoid using 64bit arithmetic by using the ++ * fact that anything faster than 1Hz is easily representable ++ * by 32bits. */ ++ ++ if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ) ++ return -ERANGE; ++ ++ if (duty_ns > period_ns) ++ return -EINVAL; ++ ++ if (period_ns == pwm->period_ns && ++ duty_ns == pwm->duty_ns) ++ return 0; ++ ++ /* The TCMP and TCNT can be read without a lock, they're not ++ * shared between the timers. */ ++ ++ tcmp = __raw_readl(S3C2410_TCMPB(pwm->pwm_id)); ++ tcnt = __raw_readl(S3C2410_TCNTB(pwm->pwm_id)); ++ ++ period = NS_IN_HZ / period_ns; ++ ++ pwm_dbg(pwm, "duty_ns=%d, period_ns=%d (%lu)\n", ++ duty_ns, period_ns, period); ++ ++ /* Check to see if we are changing the clock rate of the PWM */ ++ ++ if (pwm->period_ns != period_ns) { ++ if (pwm_is_tdiv(pwm)) { ++ tin_rate = pwm_calc_tin(pwm, period); ++ clk_set_rate(pwm->clk_div, tin_rate); ++ } else ++ tin_rate = clk_get_rate(pwm->clk); ++ ++ pwm->period_ns = period_ns; ++ ++ pwm_dbg(pwm, "tin_rate=%lu\n", tin_rate); ++ ++ tin_ns = NS_IN_HZ / tin_rate; ++ tcnt = period_ns / tin_ns; ++ } else ++ tin_ns = NS_IN_HZ / clk_get_rate(pwm->clk); ++ ++ /* Note, counters count down */ ++ ++ tcmp = duty_ns / tin_ns; ++ tcmp = tcnt - tcmp; ++ ++ pwm_dbg(pwm, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt); ++ ++ if (tcmp < 0) ++ tcmp = 0; ++ ++ /* Update the PWM register block. */ ++ ++ local_irq_save(flags); ++ ++ __raw_writel(tcmp, S3C2410_TCMPB(pwm->pwm_id)); ++ __raw_writel(tcnt, S3C2410_TCNTB(pwm->pwm_id)); ++ ++ tcon = __raw_readl(S3C2410_TCON); ++ tcon |= pwm_tcon_manulupdate(pwm); ++ tcon |= pwm_tcon_autoreload(pwm); ++ __raw_writel(tcon, S3C2410_TCON); ++ ++ tcon &= ~pwm_tcon_manulupdate(pwm); ++ __raw_writel(tcon, S3C2410_TCON); ++ ++ local_irq_restore(flags); ++ ++ return 0; ++} ++ ++EXPORT_SYMBOL(pwm_config); ++ ++static int pwm_register(struct pwm_device *pwm) ++{ ++ pwm->duty_ns = -1; ++ pwm->period_ns = -1; ++ ++ mutex_lock(&pwm_lock); ++ list_add_tail(&pwm->list, &pwm_list); ++ mutex_unlock(&pwm_lock); ++ ++ return 0; ++} ++ ++static int s3c_pwm_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct pwm_device *pwm; ++ unsigned long flags; ++ unsigned long tcon; ++ unsigned int id = pdev->id; ++ int ret; ++ ++ if (id == 0) { ++ if(gpio_is_valid(S5P64XX_GPF(14))) { ++ ret = gpio_request(S5P64XX_GPF(14), "GPF"); ++ ++ if (ret) { ++ printk(KERN_ERR "failed to request GPF for PWM-OUT 0\n"); ++ } ++ s3c_gpio_cfgpin(S5P64XX_GPF(14),S5P64XX_GPF14_PWM_TOUT0); ++ } ++ } else if(id == 1) { ++ if(gpio_is_valid(S5P64XX_GPF(15))) { ++ ret = gpio_request(S5P64XX_GPF(15), "GPF"); ++ ++ if (ret) { ++ printk(KERN_ERR "failed to request GPF for PWM-OUT 1\n"); ++ } ++ s3c_gpio_cfgpin(S5P64XX_GPF(15),S5P64XX_GPF15_PWM_TOUT1); ++ } ++ ++ } else { ++ printk(KERN_ERR "This PWM dosen't support PWM out\n"); ++ } ++ ++ if (id == 4) { ++ dev_err(dev, "TIMER4 is currently not supported\n"); ++ return -ENXIO; ++ } ++ ++ pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); ++ if (pwm == NULL) { ++ dev_err(dev, "failed to allocate pwm_device\n"); ++ return -ENOMEM; ++ } ++ ++ pwm->pdev = pdev; ++ pwm->pwm_id = id; ++ ++ /* calculate base of control bits in TCON */ ++ pwm->tcon_base = id == 0 ? 0 : (id * 4) + 4; ++ ++ pwm->clk = clk_get(dev, "pwm-tin"); ++ if (IS_ERR(pwm->clk)) { ++ dev_err(dev, "failed to get pwm tin clk\n"); ++ ret = PTR_ERR(pwm->clk); ++ goto err_alloc; ++ } ++ ++ pwm->clk_div = clk_get(dev, "pwm-tdiv"); ++ if (IS_ERR(pwm->clk_div)) { ++ dev_err(dev, "failed to get pwm tdiv clk\n"); ++ ret = PTR_ERR(pwm->clk_div); ++ goto err_clk_tin; ++ } ++ ++ local_irq_save(flags); ++ ++ tcon = __raw_readl(S3C2410_TCON); ++ tcon |= pwm_tcon_invert(pwm); ++ __raw_writel(tcon, S3C2410_TCON); ++ ++ local_irq_restore(flags); ++ ++ ++ ret = pwm_register(pwm); ++ if (ret) { ++ dev_err(dev, "failed to register pwm\n"); ++ goto err_clk_tdiv; ++ } ++ ++ pwm_dbg(pwm, "config bits %02x\n", ++ (__raw_readl(S3C2410_TCON) >> pwm->tcon_base) & 0x0f); ++ ++ dev_info(dev, "tin at %lu, tdiv at %lu, tin=%sclk, base %d\n", ++ clk_get_rate(pwm->clk), ++ clk_get_rate(pwm->clk_div), ++ pwm_is_tdiv(pwm) ? "div" : "ext", pwm->tcon_base); ++ ++ platform_set_drvdata(pdev, pwm); ++ return 0; ++ ++ err_clk_tdiv: ++ clk_put(pwm->clk_div); ++ ++ err_clk_tin: ++ clk_put(pwm->clk); ++ ++ err_alloc: ++ kfree(pwm); ++ return ret; ++} ++ ++static int s3c_pwm_remove(struct platform_device *pdev) ++{ ++ struct pwm_device *pwm = platform_get_drvdata(pdev); ++ ++ clk_put(pwm->clk_div); ++ clk_put(pwm->clk); ++ kfree(pwm); ++ ++ return 0; ++} ++ ++static struct platform_driver s3c_pwm_driver = { ++ .driver = { ++ .name = "s3c24xx-pwm", ++ .owner = THIS_MODULE, ++ }, ++ .probe = s3c_pwm_probe, ++ .remove = __devexit_p(s3c_pwm_remove), ++}; ++ ++static int __init pwm_init(void) ++{ ++ int ret; ++ ++ clk_scaler[0] = clk_get(NULL, "pwm-scaler0"); ++ clk_scaler[1] = clk_get(NULL, "pwm-scaler1"); ++ ++ if (IS_ERR(clk_scaler[0]) || IS_ERR(clk_scaler[1])) { ++ printk(KERN_ERR "%s: failed to get scaler clocks\n", __func__); ++ return -EINVAL; ++ } ++ ++ ret = platform_driver_register(&s3c_pwm_driver); ++ if (ret) ++ printk(KERN_ERR "%s: failed to add pwm driver\n", __func__); ++ ++ return ret; ++} ++ ++arch_initcall(pwm_init); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/s5p6440-clock.c linux-2.6.28.6/arch/arm/plat-s5p64xx/s5p6440-clock.c +--- linux-2.6.28/arch/arm/plat-s5p64xx/s5p6440-clock.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/s5p6440-clock.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,730 @@ ++/* linux/arch/arm/plat-s5p64xx/s5p6440-clock.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5P6440 based common clock support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call ++ * ext_xtal_mux for want of an actual name from the manual. ++*/ ++ ++struct clk clk_ext_xtal_mux = { ++ .name = "ext_xtal", ++ .id = -1, ++}; ++ ++#define clk_fin_apll clk_ext_xtal_mux ++#define clk_fin_mpll clk_ext_xtal_mux ++#define clk_fin_epll clk_ext_xtal_mux ++ ++#define clk_fout_mpll clk_mpll ++ ++struct clk_sources { ++ unsigned int nr_sources; ++ struct clk **sources; ++}; ++ ++struct clksrc_clk { ++ struct clk clk; ++ unsigned int mask; ++ unsigned int shift; ++ ++ struct clk_sources *sources; ++ ++ unsigned int divider_shift; ++ void __iomem *reg_divider; ++}; ++ ++struct clk clk_fout_apll = { ++ .name = "fout_apll", ++ .id = -1, ++}; ++ ++static struct clk *clk_src_apll_list[] = { ++ [0] = &clk_fin_apll, ++ [1] = &clk_fout_apll, ++}; ++ ++static struct clk_sources clk_src_apll = { ++ .sources = clk_src_apll_list, ++ .nr_sources = ARRAY_SIZE(clk_src_apll_list), ++}; ++ ++struct clksrc_clk clk_mout_apll = { ++ .clk = { ++ .name = "mout_apll", ++ .id = -1, ++ }, ++ .shift = S3C_CLKSRC_APLL_MOUT_SHIFT, ++ .mask = S3C_CLKSRC_APLL_MOUT, ++ .sources = &clk_src_apll, ++}; ++ ++static inline struct clksrc_clk *to_clksrc(struct clk *clk) ++{ ++ return container_of(clk, struct clksrc_clk, clk); ++} ++ ++int fout_enable(struct clk *clk, int enable) ++{ ++ unsigned int ctrlbit = clk->ctrlbit; ++ unsigned int epll_con0 = __raw_readl(S3C_EPLL_CON) & ~ ctrlbit; ++ ++ if(enable) ++ __raw_writel(epll_con0 | ctrlbit, S3C_EPLL_CON); ++ else ++ __raw_writel(epll_con0, S3C_EPLL_CON); ++ ++ return 0; ++} ++ ++unsigned long fout_get_rate(struct clk *clk) ++{ ++ return clk->rate; ++} ++ ++int fout_set_rate(struct clk *clk, unsigned long rate) ++{ ++ unsigned int epll_con0, epll_con1; ++ ++ if(clk->rate == rate) /* Return if nothing changed */ ++ return 0; ++ ++ epll_con0 = __raw_readl(S3C_EPLL_CON); ++ epll_con1 = __raw_readl(S3C_EPLL_CON_K); ++ ++ epll_con0 &= ~(S3C_EPLL_CON_M_MASK | S3C_EPLL_CON_P_MASK | S3C_EPLL_CON_S_MASK); ++ epll_con1 &= ~(S3C_EPLL_CON_K_MASK); ++ ++ switch(rate){ ++ case 36000000: ++ epll_con1 |= (0 << S3C_EPLL_CON_K_SHIFT); ++ epll_con0 |= (48 << S3C_EPLL_CON_M_SHIFT) | ++ (1 << S3C_EPLL_CON_P_SHIFT) | (4 << S3C_EPLL_CON_S_SHIFT); ++ break; ++ case 48000000: ++ epll_con1 |= (0 << S3C_EPLL_CON_K_SHIFT); ++ epll_con0 |= (32 << S3C_EPLL_CON_M_SHIFT) | ++ (1 << S3C_EPLL_CON_P_SHIFT) | (3 << S3C_EPLL_CON_S_SHIFT); ++ break; ++ case 60000000: ++ epll_con1 |= (0 << S3C_EPLL_CON_K_SHIFT); ++ epll_con0 |= (40 << S3C_EPLL_CON_M_SHIFT) | ++ (1 << S3C_EPLL_CON_P_SHIFT) | (3 << S3C_EPLL_CON_S_SHIFT); ++ break; ++ case 72000000: ++ epll_con1 |= (0 << S3C_EPLL_CON_K_SHIFT); ++ epll_con0 |= (48 << S3C_EPLL_CON_M_SHIFT) | ++ (1 << S3C_EPLL_CON_P_SHIFT) | (3 << S3C_EPLL_CON_S_SHIFT); ++ break; ++ case 84000000: ++ epll_con1 |= (0 << S3C_EPLL_CON_K_SHIFT); ++ epll_con0 |= (28 << S3C_EPLL_CON_M_SHIFT) | ++ (1 << S3C_EPLL_CON_P_SHIFT) | (2 << S3C_EPLL_CON_S_SHIFT); ++ break; ++ case 96000000: ++ epll_con1 |= (0 << S3C_EPLL_CON_K_SHIFT); ++ epll_con0 |= (32 << S3C_EPLL_CON_M_SHIFT) | ++ (1 << S3C_EPLL_CON_P_SHIFT) | (2 << S3C_EPLL_CON_S_SHIFT); ++ break; ++ case 32768000: ++ epll_con1 |= (45264 << S3C_EPLL_CON_K_SHIFT); ++ epll_con0 |= (43 << S3C_EPLL_CON_M_SHIFT) | ++ (1 << S3C_EPLL_CON_P_SHIFT) | (4 << S3C_EPLL_CON_S_SHIFT); ++ break; ++ case 45158000: ++ epll_con1 |= (6903 << S3C_EPLL_CON_K_SHIFT); ++ epll_con0 |= (30 << S3C_EPLL_CON_M_SHIFT) | ++ (1 << S3C_EPLL_CON_P_SHIFT) | (3 << S3C_EPLL_CON_S_SHIFT); ++ break; ++ case 49152000: ++ epll_con1 |= (50332 << S3C_EPLL_CON_K_SHIFT); ++ epll_con0 |= (32 << S3C_EPLL_CON_M_SHIFT) | ++ (1 << S3C_EPLL_CON_P_SHIFT) | (3 << S3C_EPLL_CON_S_SHIFT); ++ break; ++ case 67738000: ++ epll_con1 |= (10398 << S3C_EPLL_CON_K_SHIFT); ++ epll_con0 |= (45 << S3C_EPLL_CON_M_SHIFT) | ++ (1 << S3C_EPLL_CON_P_SHIFT) | (3 << S3C_EPLL_CON_S_SHIFT); ++ break; ++ case 73728000: ++ epll_con1 |= (9961 << S3C_EPLL_CON_K_SHIFT); ++ epll_con0 |= (49 << S3C_EPLL_CON_M_SHIFT) | ++ (1 << S3C_EPLL_CON_P_SHIFT) | (3 << S3C_EPLL_CON_S_SHIFT); ++ break; ++ default: ++ printk(KERN_ERR "Invalid Clock Freq!\n"); ++ return -EINVAL; ++ } ++ ++ __raw_writel(epll_con0, S3C_EPLL_CON); ++ __raw_writel(epll_con1, S3C_EPLL_CON_K); ++ ++ clk->rate = rate; ++ ++ return 0; ++} ++ ++struct clk clk_fout_epll = { ++ .name = "fout_epll", ++ .id = -1, ++ .ctrlbit = (1<<31), ++ .enable = fout_enable, ++ .get_rate = fout_get_rate, ++ .set_rate = fout_set_rate, ++}; ++ ++int mout_set_parent(struct clk *clk, struct clk *parent) ++{ ++ int src_nr = -1; ++ int ptr; ++ u32 clksrc; ++ struct clksrc_clk *sclk = to_clksrc(clk); ++ struct clk_sources *srcs = sclk->sources; ++ ++ clksrc = __raw_readl(S3C_CLK_SRC0); ++ ++ for (ptr = 0; ptr < srcs->nr_sources; ptr++) ++ if (srcs->sources[ptr] == parent) { ++ src_nr = ptr; ++ break; ++ } ++ ++ if (src_nr >= 0) { ++ clksrc &= ~sclk->mask; ++ clksrc |= src_nr << sclk->shift; ++ __raw_writel(clksrc, S3C_CLK_SRC0); ++ clk->parent = parent; ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static struct clk *clk_src_epll_list[] = { ++ [0] = &clk_fin_epll, ++ [1] = &clk_fout_epll, ++}; ++ ++static struct clk_sources clk_src_epll = { ++ .sources = clk_src_epll_list, ++ .nr_sources = ARRAY_SIZE(clk_src_epll_list), ++}; ++ ++struct clksrc_clk clk_mout_epll = { ++ .clk = { ++ .name = "mout_epll", ++ .id = -1, ++ .set_parent = mout_set_parent, ++ }, ++ .shift = S3C_CLKSRC_EPLL_MOUT_SHIFT, ++ .mask = S3C_CLKSRC_EPLL_MOUT, ++ .sources = &clk_src_epll, ++}; ++ ++static struct clk *clk_src_mpll_list[] = { ++ [0] = &clk_fin_mpll, ++ [1] = &clk_fout_mpll, ++}; ++ ++static struct clk_sources clk_src_mpll = { ++ .sources = clk_src_mpll_list, ++ .nr_sources = ARRAY_SIZE(clk_src_mpll_list), ++}; ++ ++struct clksrc_clk clk_mout_mpll = { ++ .clk = { ++ .name = "mout_mpll", ++ .id = -1, ++ }, ++ .shift = S3C_CLKSRC_MPLL_MOUT_SHIFT, ++ .mask = S3C_CLKSRC_MPLL_MOUT, ++ .sources = &clk_src_mpll, ++}; ++ ++static unsigned long s5p64xx_clk_doutmpll_get_rate(struct clk *clk) ++{ ++ unsigned long rate = clk_get_rate(clk->parent); ++ ++ printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); ++ ++ if (__raw_readl(S3C_CLK_DIV0) & S3C_CLKDIV0_MPLL_MASK) ++ rate /= 2; ++ ++ return rate; ++} ++ ++struct clk clk_dout_mpll = { ++ .name = "dout_mpll", ++ .id = -1, ++ .parent = &clk_mout_mpll.clk, ++ .get_rate = s5p64xx_clk_doutmpll_get_rate, ++}; ++ ++static struct clk clk_iis_cd_v40 = { ++ .name = "iis_cdclk_v40", ++ .id = -1, ++}; ++ ++static struct clk clk_pcm_cd = { ++ .name = "pcm_cdclk", ++ .id = -1, ++}; ++ ++static struct clk *clkset_audio2_list[] = { ++ [0] = &clk_mout_epll.clk, ++ [1] = &clk_dout_mpll, ++ [2] = &clk_fin_epll, ++ [3] = &clk_iis_cd_v40, ++ [4] = &clk_pcm_cd, ++}; ++ ++static struct clk_sources clkset_audio2 = { ++ .sources = clkset_audio2_list, ++ .nr_sources = ARRAY_SIZE(clkset_audio2_list), ++}; ++ ++static struct clk *clkset_spi_mmc_list[] = { ++ &clk_mout_epll.clk, ++ &clk_dout_mpll, ++ &clk_fin_epll, ++}; ++ ++static struct clk_sources clkset_spi_mmc = { ++ .sources = clkset_spi_mmc_list, ++ .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), ++}; ++ ++static struct clk *clkset_uart_list[] = { ++ &clk_mout_epll.clk, ++ &clk_dout_mpll, ++ NULL, ++ NULL ++}; ++ ++static struct clk_sources clkset_uart = { ++ .sources = clkset_uart_list, ++ .nr_sources = ARRAY_SIZE(clkset_uart_list), ++}; ++ ++/* The peripheral clocks are all controlled via clocksource followed ++ * by an optional divider and gate stage. We currently roll this into ++ * one clock which hides the intermediate clock from the mux. ++ * ++ * Note, the JPEG clock can only be an even divider... ++ * ++ * The scaler and LCD clocks depend on the S5P64XX version, and also ++ * have a common parent divisor so are not included here. ++ */ ++ ++static unsigned long s5p64xx_getrate_clksrc(struct clk *clk) ++{ ++ struct clksrc_clk *sclk = to_clksrc(clk); ++ unsigned long rate = clk_get_rate(clk->parent); ++ u32 clkdiv = __raw_readl(sclk->reg_divider); ++ ++ clkdiv >>= sclk->divider_shift; ++ clkdiv &= 0xf; ++ clkdiv++; ++ ++ rate /= clkdiv; ++ return rate; ++} ++ ++static int s5p64xx_setrate_clksrc(struct clk *clk, unsigned long rate) ++{ ++ struct clksrc_clk *sclk = to_clksrc(clk); ++ void __iomem *reg = sclk->reg_divider; ++ unsigned int div; ++ u32 val; ++ ++ rate = clk_round_rate(clk, rate); ++ div = clk_get_rate(clk->parent) / rate; ++ ++ val = __raw_readl(reg); ++ val &= ~(0xf << sclk->divider_shift); ++ val |= ((div - 1) << sclk->divider_shift); ++ __raw_writel(val, reg); ++ ++ return 0; ++} ++ ++static struct clksrc_clk clk_audio2; ++ ++static int s5p64xx_setparent_clksrc(struct clk *clk, struct clk *parent) ++{ ++ int ptr; ++ int src_nr = -1; ++ u32 clksrc; ++ struct clksrc_clk *sclk = to_clksrc(clk); ++ struct clk_sources *srcs = sclk->sources; ++ ++ if(sclk == &clk_audio2) ++ clksrc = __raw_readl(S3C_CLK_SRC1); ++ else ++ clksrc = __raw_readl(S3C_CLK_SRC0); ++ ++ for (ptr = 0; ptr < srcs->nr_sources; ptr++) ++ if (srcs->sources[ptr] == parent) { ++ src_nr = ptr; ++ break; ++ } ++ ++ if (src_nr >= 0) { ++ clksrc &= ~sclk->mask; ++ clksrc |= src_nr << sclk->shift; ++ ++ if(sclk == &clk_audio2) ++ __raw_writel(clksrc, S3C_CLK_SRC1); ++ else ++ __raw_writel(clksrc, S3C_CLK_SRC0); ++ ++ clk->parent = parent; ++ ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static unsigned long s5p64xx_roundrate_clksrc(struct clk *clk, ++ unsigned long rate) ++{ ++ unsigned long parent_rate = clk_get_rate(clk->parent); ++ int div; ++ ++ if (rate > parent_rate) ++ rate = parent_rate; ++ else { ++ div = rate / parent_rate; ++ ++ if (div == 0) ++ div = 1; ++ if (div > 16) ++ div = 16; ++ ++ rate = parent_rate / div; ++ } ++ ++ return rate; ++} ++ ++static struct clksrc_clk clk_mmc0 = { ++ .clk = { ++ .name = "mmc_bus", ++ .id = 0, ++ .ctrlbit = S3C_CLKCON_SCLK0_MMC0, ++ .enable = s5p64xx_sclk_ctrl, ++ .set_parent = s5p64xx_setparent_clksrc, ++ .get_rate = s5p64xx_getrate_clksrc, ++ .set_rate = s5p64xx_setrate_clksrc, ++ .round_rate = s5p64xx_roundrate_clksrc, ++ }, ++ .shift = S3C_CLKSRC_MMC0_SHIFT, ++ .mask = S3C_CLKSRC_MMC0_MASK, ++ .sources = &clkset_spi_mmc, ++ .divider_shift = S3C_CLKDIV1_MMC0_SHIFT, ++ .reg_divider = S3C_CLK_DIV1, ++}; ++ ++static struct clksrc_clk clk_mmc1 = { ++ .clk = { ++ .name = "mmc_bus", ++ .id = 1, ++ .ctrlbit = S3C_CLKCON_SCLK0_MMC1, ++ .enable = s5p64xx_sclk_ctrl, ++ .get_rate = s5p64xx_getrate_clksrc, ++ .set_rate = s5p64xx_setrate_clksrc, ++ .set_parent = s5p64xx_setparent_clksrc, ++ .round_rate = s5p64xx_roundrate_clksrc, ++ }, ++ .shift = S3C_CLKSRC_MMC1_SHIFT, ++ .mask = S3C_CLKSRC_MMC1_MASK, ++ .sources = &clkset_spi_mmc, ++ .divider_shift = S3C_CLKDIV1_MMC1_SHIFT, ++ .reg_divider = S3C_CLK_DIV1, ++}; ++ ++static struct clksrc_clk clk_mmc2 = { ++ .clk = { ++ .name = "mmc_bus", ++ .id = 2, ++ .ctrlbit = S3C_CLKCON_SCLK0_MMC2, ++ .enable = s5p64xx_sclk_ctrl, ++ .get_rate = s5p64xx_getrate_clksrc, ++ .set_rate = s5p64xx_setrate_clksrc, ++ .set_parent = s5p64xx_setparent_clksrc, ++ .round_rate = s5p64xx_roundrate_clksrc, ++ }, ++ .shift = S3C_CLKSRC_MMC2_SHIFT, ++ .mask = S3C_CLKSRC_MMC2_MASK, ++ .sources = &clkset_spi_mmc, ++ .divider_shift = S3C_CLKDIV1_MMC2_SHIFT, ++ .reg_divider = S3C_CLK_DIV1, ++}; ++ ++static struct clksrc_clk clk_uart_uclk1 = { ++ .clk = { ++ .name = "uclk1", ++ .id = -1, ++ .ctrlbit = S3C_CLKCON_SCLK0_UART, ++ .enable = s5p64xx_sclk_ctrl, ++ .set_parent = s5p64xx_setparent_clksrc, ++ .get_rate = s5p64xx_getrate_clksrc, ++ .set_rate = s5p64xx_setrate_clksrc, ++ .round_rate = s5p64xx_roundrate_clksrc, ++ }, ++ .shift = S3C_CLKSRC_UART_SHIFT, ++ .mask = S3C_CLKSRC_UART_MASK, ++ .sources = &clkset_uart, ++ .divider_shift = S3C_CLKDIV2_UART_SHIFT, ++ .reg_divider = S3C_CLK_DIV2, ++}; ++ ++static struct clksrc_clk clk_audio2 = { ++ .clk = { ++ .name = "audio-bus2", ++ .id = -1, ++ .ctrlbit = S3C_CLKCON_SCLK0_AUDIO2, ++ .enable = s5p64xx_sclk_ctrl, ++ .set_parent = s5p64xx_setparent_clksrc, ++ .get_rate = s5p64xx_getrate_clksrc, ++ .set_rate = s5p64xx_setrate_clksrc, ++ .round_rate = s5p64xx_roundrate_clksrc, ++ }, ++ .shift = S3C_CLKSRC1_AUDIO2_SHIFT, ++ .mask = S3C_CLKSRC1_AUDIO2_MASK, ++ .sources = &clkset_audio2, ++ .divider_shift = S3C_CLKDIV2_AUDIO2_SHIFT, ++ .reg_divider = S3C_CLK_DIV2, ++}; ++ ++/* Where does UCLK0 come from? */ ++ ++static struct clksrc_clk clk_spi0 = { ++ .clk = { ++ .name = "spi-bus", ++ .id = 0, ++ .ctrlbit = S3C_CLKCON_SCLK0_SPI0, ++ .enable = s5p64xx_sclk_ctrl, ++ .set_parent = s5p64xx_setparent_clksrc, ++ .get_rate = s5p64xx_getrate_clksrc, ++ .set_rate = s5p64xx_setrate_clksrc, ++ .round_rate = s5p64xx_roundrate_clksrc, ++ }, ++ .shift = S3C_CLKSRC_SPI0_SHIFT, ++ .mask = S3C_CLKSRC_SPI0_MASK, ++ .sources = &clkset_spi_mmc, ++ .divider_shift = S3C_CLKDIV2_SPI0_SHIFT, ++ .reg_divider = S3C_CLK_DIV2, ++}; ++ ++static struct clksrc_clk clk_spi1 = { ++ .clk = { ++ .name = "spi-bus", ++ .id = 1, ++ .ctrlbit = S3C_CLKCON_SCLK0_SPI1, ++ .enable = s5p64xx_sclk_ctrl, ++ .set_parent = s5p64xx_setparent_clksrc, ++ .get_rate = s5p64xx_getrate_clksrc, ++ .set_rate = s5p64xx_setrate_clksrc, ++ .round_rate = s5p64xx_roundrate_clksrc, ++ }, ++ .shift = S3C_CLKSRC_SPI1_SHIFT, ++ .mask = S3C_CLKSRC_SPI1_MASK, ++ .sources = &clkset_spi_mmc, ++ .divider_shift = S3C_CLKDIV2_SPI1_SHIFT, ++ .reg_divider = S3C_CLK_DIV2, ++}; ++ ++/* Clock initialisation code */ ++ ++static struct clksrc_clk *init_parents[] = { ++ &clk_mout_apll, ++ &clk_mout_epll, ++ &clk_mout_mpll, ++ &clk_mmc0, ++ &clk_mmc1, ++ &clk_mmc2, ++ &clk_uart_uclk1, ++ &clk_spi0, ++ &clk_spi1, ++ &clk_audio2, ++}; ++ ++static void __init_or_cpufreq s5p6440_set_clksrc(struct clksrc_clk *clk) ++{ ++ u32 clksrc; ++ struct clk_sources *srcs = clk->sources; ++ ++ if(clk == &clk_audio2) ++ clksrc = __raw_readl(S3C_CLK_SRC1); ++ else ++ clksrc = __raw_readl(S3C_CLK_SRC0); ++ ++ clksrc &= clk->mask; ++ clksrc >>= clk->shift; ++ ++ if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) { ++ printk(KERN_ERR "%s: bad source %d\n", ++ clk->clk.name, clksrc); ++ return; ++ } ++ ++ clk->clk.parent = srcs->sources[clksrc]; ++ ++ printk(KERN_INFO "%s: source is %s (%d), rate is %ld.%ldMHz\n", ++ clk->clk.name, clk->clk.parent->name, clksrc, ++ print_mhz(clk_get_rate(&clk->clk))); ++} ++ ++#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) ++ ++void __init_or_cpufreq s5p6440_setup_clocks(void) ++{ ++ struct clk *xtal_clk; ++ unsigned long xtal; ++ unsigned long fclk; ++ unsigned long hclk; ++ unsigned long hclk_low; ++ unsigned long pclk; ++ unsigned long pclk_low; ++ unsigned long epll; ++ unsigned long apll; ++ unsigned long mpll; ++ unsigned int ptr; ++ u32 clkdiv0; ++ u32 clkdiv3; ++ u32 clkdiv1; ++ ++ printk(KERN_DEBUG "%s: registering clocks\n", __func__); ++ ++ clkdiv0 = __raw_readl(S3C_CLK_DIV0); ++ printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0); ++ ++ clkdiv3 = __raw_readl(S3C_CLK_DIV3); ++ printk(KERN_DEBUG "%s: clkdiv3 = %08x\n", __func__, clkdiv3); ++ ++ /* init mmc_clock source */ ++ s5p64xx_setparent_clksrc(&clk_mmc0.clk, &clk_dout_mpll); ++ s5p64xx_setparent_clksrc(&clk_mmc1.clk, &clk_dout_mpll); ++ s5p64xx_setparent_clksrc(&clk_mmc2.clk, &clk_dout_mpll); ++ ++ /* init mmc_clock divider */ ++ clkdiv1 = __raw_readl(S3C_CLK_DIV1); ++ clkdiv1 &= ~0x00000fff; ++ writel(clkdiv1 | 0x777, S3C_CLK_DIV1); ++ clkdiv1 = __raw_readl(S3C_CLK_DIV1); ++ ++ xtal_clk = clk_get(NULL, "xtal"); ++ BUG_ON(IS_ERR(xtal_clk)); ++ ++ xtal = clk_get_rate(xtal_clk); ++ clk_put(xtal_clk); ++ ++ printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); ++ ++ epll = s5p6440_get_epll(xtal); ++ mpll = s5p6440_get_pll(xtal, __raw_readl(S3C_MPLL_CON)); ++ apll = s5p6440_get_pll(xtal, __raw_readl(S3C_APLL_CON)); ++ ++ printk(KERN_INFO "S5P64XX: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \ ++ " E=%ld.%ldMHz\n", ++ print_mhz(apll), print_mhz(mpll), print_mhz(epll)); ++ ++ fclk = apll / GET_DIV(clkdiv0, S3C_CLKDIV0_ARM); ++ hclk = fclk / GET_DIV(clkdiv0, S3C_CLKDIV0_HCLK); ++ pclk = hclk / GET_DIV(clkdiv0, S3C_CLKDIV0_PCLK); ++ ++ if(__raw_readl(S3C_OTHERS) & S3C_OTHERS_HCLK_LOW_SEL_MPLL) { ++ /* Synchronous mode */ ++ hclk_low = apll / GET_DIV(clkdiv3, S3C_CLKDIV3_HCLK_LOW); ++ } else { ++ /* Asynchronous mode */ ++ hclk_low = mpll / GET_DIV(clkdiv3, S3C_CLKDIV3_HCLK_LOW); ++ } ++ ++ pclk_low = hclk_low / GET_DIV(clkdiv3, S3C_CLKDIV3_PCLK_LOW); ++ ++ printk(KERN_INFO "S5P64XX: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \ ++ " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n", ++ print_mhz(hclk), print_mhz(hclk_low), ++ print_mhz(pclk), print_mhz(pclk_low)); ++ ++ clk_fout_mpll.rate = mpll; ++ clk_fout_epll.rate = epll; ++ clk_fout_apll.rate = apll; ++ ++ clk_f.rate = fclk; ++ clk_h.rate = hclk; ++ clk_p.rate = pclk; ++ clk_h_low.rate = hclk_low; ++ clk_p_low.rate = pclk_low; ++ ++ for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) ++ s5p6440_set_clksrc(init_parents[ptr]); ++} ++ ++static struct clk *clks[] __initdata = { ++ &clk_ext_xtal_mux, ++ &clk_mout_epll.clk, ++ &clk_fout_epll, ++ &clk_mout_mpll.clk, ++ &clk_dout_mpll, ++ &clk_iis_cd_v40, ++ &clk_pcm_cd, ++ &clk_mmc0.clk, ++ &clk_mmc1.clk, ++ &clk_mmc2.clk, ++ &clk_uart_uclk1.clk, ++ &clk_spi0.clk, ++ &clk_spi1.clk, ++ &clk_audio2.clk, ++}; ++ ++void __init s5p6440_register_clocks(void) ++{ ++ struct clk *clkp; ++ int ret; ++ int ptr; ++ ++ for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { ++ clkp = clks[ptr]; ++ ret = s3c24xx_register_clock(clkp); ++ if (ret < 0) { ++ printk(KERN_ERR "Failed to register clock %s (%d)\n", ++ clkp->name, ret); ++ } ++ } ++ ++// clk_mpll.parent = &clk_mout_mpll.clk; ++ clk_epll.parent = &clk_mout_epll.clk; ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/s5p6440-init.c linux-2.6.28.6/arch/arm/plat-s5p64xx/s5p6440-init.c +--- linux-2.6.28/arch/arm/plat-s5p64xx/s5p6440-init.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/s5p6440-init.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,28 @@ ++/* linux/arch/arm/plat-s5p64xx/s5p6440-init.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5P6440 - CPU initialisation (common with other S5P64XX chips) ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++/* uart registration process */ ++ ++void __init s5p6440_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) ++{ ++ s3c24xx_init_uartdevs("s3c6400-uart", s5p64xx_uart_resources, cfg, no); ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/s5p64xx-cpufreq.c linux-2.6.28.6/arch/arm/plat-s5p64xx/s5p64xx-cpufreq.c +--- linux-2.6.28/arch/arm/plat-s5p64xx/s5p64xx-cpufreq.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/s5p64xx-cpufreq.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,214 @@ ++/* ++ * linux/arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c ++ * ++ * CPU frequency scaling for S3C64XX ++ * ++ * Copyright (C) 2008 Samsung Electronics ++ * ++ * Based on cpu-sa1110.c, Copyright (C) 2001 Russell King ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#define USE_FREQ_TABLE ++#define USE_DVS ++#define VERY_HI_RATE 532*1000*1000 ++#define APLL_GEN_CLK 532*1000 //khz ++#define KHZ_T 1000 ++ ++#define MPU_CLK "clk_cpu" ++ ++/* definition for power setting function */ ++extern int set_power(unsigned int freq); ++extern void ltc3714_init(void); ++ ++#define ARM_LE 0 ++#define INT_LE 1 ++ ++//#define CLK_PROBING ++ ++/* frequency */ ++static struct cpufreq_frequency_table s5p6440_freq_table[] = { ++ {APLL_GEN_CLK, APLL_GEN_CLK}, ++ {APLL_GEN_CLK, APLL_GEN_CLK/2}, ++ {APLL_GEN_CLK, APLL_GEN_CLK/4}, ++ {0, CPUFREQ_TABLE_END}, ++}; ++ ++/* TODO: Add support for SDRAM timing changes */ ++ ++int s5p6440_verify_speed(struct cpufreq_policy *policy) ++{ ++#ifndef USE_FREQ_TABLE ++ struct clk *mpu_clk; ++#endif ++ ++ if (policy->cpu) ++ return -EINVAL; ++#ifdef USE_FREQ_TABLE ++ return cpufreq_frequency_table_verify(policy, s5p6440_freq_table); ++#else ++ cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, ++ policy->cpuinfo.max_freq); ++ mpu_clk = clk_get(NULL, MPU_CLK); ++ if (IS_ERR(mpu_clk)) ++ return PTR_ERR(mpu_clk); ++ ++ policy->min = clk_round_rate(mpu_clk, policy->min * KHZ_T) / KHZ_T; ++ policy->max = clk_round_rate(mpu_clk, policy->max * KHZ_T) / KHZ_T; ++ ++ cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, ++ policy->cpuinfo.max_freq); ++ ++ clk_put(mpu_clk); ++ ++ return 0; ++#endif ++} ++ ++unsigned int s5p6440_getspeed(unsigned int cpu) ++{ ++ struct clk * mpu_clk; ++ unsigned long rate; ++ ++ if (cpu) ++ return 0; ++ ++ mpu_clk = clk_get(NULL, MPU_CLK); ++ if (IS_ERR(mpu_clk)) ++ return 0; ++ rate = clk_get_rate(mpu_clk) / KHZ_T; ++ ++ clk_put(mpu_clk); ++ ++ return rate; ++} ++ ++static int s5p6440_target(struct cpufreq_policy *policy, ++ unsigned int target_freq, ++ unsigned int relation) ++{ ++ struct clk * mpu_clk; ++ struct cpufreq_freqs freqs; ++ int ret = 0; ++ unsigned long arm_clk; ++ unsigned int index; ++ ++ mpu_clk = clk_get(NULL, MPU_CLK); ++ if (IS_ERR(mpu_clk)) ++ return PTR_ERR(mpu_clk); ++ ++ freqs.old = s5p6440_getspeed(0); ++#ifdef USE_FREQ_TABLE ++ if (cpufreq_frequency_table_target(policy, s5p6440_freq_table, target_freq, relation, &index)) ++ return -EINVAL; ++ ++ arm_clk = s5p6440_freq_table[index].frequency; ++ ++ freqs.new = arm_clk; ++#else ++ freqs.new = clk_round_rate(mpu_clk, target_freq * KHZ_T) / KHZ_T; ++#endif ++ freqs.cpu = 0; ++ ++ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); ++#ifdef USE_DVS ++ if(freqs.new < freqs.old){ ++ /* frequency scaling */ ++ ret = clk_set_rate(mpu_clk, target_freq * KHZ_T); ++ if(ret != 0) ++ printk("frequency scaling error\n"); ++ /* voltage scaling */ ++ set_power(freqs.new); ++ }else{ ++ /* voltage scaling */ ++ set_power(freqs.new); ++ ++ /* frequency scaling */ ++ ret = clk_set_rate(mpu_clk, target_freq * KHZ_T); ++ if(ret != 0) ++ printk("frequency scaling error\n"); ++ } ++ ++ ++#else ++ ret = clk_set_rate(mpu_clk, target_freq * KHZ_T); ++ if(ret != 0) ++ printk("frequency scaling error\n"); ++ ++#endif ++ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); ++ clk_put(mpu_clk); ++ return ret; ++} ++ ++static int __init s5p6440_cpu_init(struct cpufreq_policy *policy) ++{ ++ struct clk * mpu_clk; ++ ++#ifdef USE_DVS ++ ltc3714_init(); ++#endif ++ ++#ifdef CLK_PROBING ++ __raw_writel((__raw_readl(S5P64XX_GPFCON)&~(0x3<<28))|(0x3<<28), S5P64XX_GPFCON); ++ __raw_writel((__raw_readl(S3C_CLK_OUT)&~(0xf<<12)), S3C_CLK_OUT); ++#endif ++ mpu_clk = clk_get(NULL, MPU_CLK); ++ if (IS_ERR(mpu_clk)) ++ return PTR_ERR(mpu_clk); ++ ++ if (policy->cpu != 0) ++ return -EINVAL; ++ policy->cur = policy->min = policy->max = s5p6440_getspeed(0); ++#ifdef USE_FREQ_TABLE ++ cpufreq_frequency_table_get_attr(s5p6440_freq_table, policy->cpu); ++#else ++ policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / KHZ_T; ++ policy->cpuinfo.max_freq = clk_round_rate(mpu_clk, VERY_HI_RATE) / KHZ_T; ++#endif ++ policy->cpuinfo.transition_latency = 40000; //1us ++ ++ ++ clk_put(mpu_clk); ++#ifdef USE_FREQ_TABLE ++ return cpufreq_frequency_table_cpuinfo(policy, s5p6440_freq_table); ++#else ++ return 0; ++#endif ++} ++ ++static struct cpufreq_driver s5p6440_driver = { ++ .flags = CPUFREQ_STICKY, ++ .verify = s5p6440_verify_speed, ++ .target = s5p6440_target, ++ .get = s5p6440_getspeed, ++ .init = s5p6440_cpu_init, ++ .name = "s5p6440", ++}; ++ ++static int __init s5p6440_cpufreq_init(void) ++{ ++ return cpufreq_register_driver(&s5p6440_driver); ++} ++ ++arch_initcall(s5p6440_cpufreq_init); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/setup-i2c0.c linux-2.6.28.6/arch/arm/plat-s5p64xx/setup-i2c0.c +--- linux-2.6.28/arch/arm/plat-s5p64xx/setup-i2c0.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/setup-i2c0.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,31 @@ ++/* linux/arch/arm/plat-s5p64xx/setup-i2c0.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * Base S5P64XX I2C bus 0 gpio configuration ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++ ++struct platform_device; /* don't need the contents */ ++ ++#include ++#include ++#include ++#include ++ ++void s3c_i2c0_cfg_gpio(struct platform_device *dev) ++{ ++ s3c_gpio_cfgpin(S5P64XX_GPB(5), S5P64XX_GPB5_I2C_SCL0); ++ s3c_gpio_cfgpin(S5P64XX_GPB(6), S5P64XX_GPB6_I2C_SDA0); ++ s3c_gpio_setpull(S5P64XX_GPB(5), S3C_GPIO_PULL_UP); ++ s3c_gpio_setpull(S5P64XX_GPB(6), S3C_GPIO_PULL_UP); ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/setup-i2c1.c linux-2.6.28.6/arch/arm/plat-s5p64xx/setup-i2c1.c +--- linux-2.6.28/arch/arm/plat-s5p64xx/setup-i2c1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/setup-i2c1.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,31 @@ ++/* linux/arch/arm/plat-s5p64xx/setup-i2c1.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * Base S5P64XX I2C bus 1 gpio configuration ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++ ++struct platform_device; /* don't need the contents */ ++ ++#include ++#include ++#include ++#include ++ ++void s3c_i2c1_cfg_gpio(struct platform_device *dev) ++{ ++ s3c_gpio_cfgpin(S5P64XX_GPB(2), S5P64XX_GPB2_I2C_SCL1); ++ s3c_gpio_cfgpin(S5P64XX_GPB(3), S5P64XX_GPB3_I2C_SDA1); ++ s3c_gpio_setpull(S5P64XX_GPB(2), S3C_GPIO_PULL_UP); ++ s3c_gpio_setpull(S5P64XX_GPB(3), S3C_GPIO_PULL_UP); ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/setup-post.c linux-2.6.28.6/arch/arm/plat-s5p64xx/setup-post.c +--- linux-2.6.28/arch/arm/plat-s5p64xx/setup-post.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/setup-post.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,26 @@ ++/* linux/arch/arm/plat-s5p64xx/setup-post.c ++ * ++ * Copyright 2009 Samsung Electronics ++ * Jinsung Yang ++ * http://samsungsemi.com/ ++ * ++ * Base Post Processor gpio configuration ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct platform_device; /* don't need the contents */ ++ ++void s3c_post_cfg_gpio(struct platform_device *dev) ++{ ++ /* nothing to do */ ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5p64xx/sleep.S linux-2.6.28.6/arch/arm/plat-s5p64xx/sleep.S +--- linux-2.6.28/arch/arm/plat-s5p64xx/sleep.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5p64xx/sleep.S 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,117 @@ ++/* linux/0arch/arm/plat-s3c64xx/sleep.S ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S3C64XX CPU sleep code ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++ ++#include ++ ++ .text ++ ++ /* s3c_cpu_save ++ * ++ * Save enough processor state to allow the restart of the pm.c ++ * code after resume. ++ * ++ * entry: ++ * r0 = pointer to the save block ++ * exit: ++ * r0 = exit code: 1 => stored data ++ * 0 => resumed from sleep ++ */ ++ ++ENTRY(s5p6440_cpu_save) ++ stmfd sp!, { r4 - r12, lr } ++ ++ mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID ++ mrc p15, 0, r5, c3, c0, 0 @ Domain ID ++ mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 ++ mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 ++ mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control ++ mrc p15, 0, r9, c1, c0, 0 @ Control register ++ mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register ++ mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls ++ ++ stmia r0, { r4 - r13 } @ Save CP registers and SP ++ mov r0, #0 ++ ldmfd sp, { r4 - r12, pc } @ return, not disturbing SP ++ ++ @@ return to the caller, after the MMU is turned on. ++ @@ restore the last bits of the stack and return. ++resume_with_mmu: ++ mov r0, #1 ++ ldmfd sp!, { r4 - r12, pc } @ return, from sp from s3c_cpu_save ++ ++ .data ++ ++ /* the next bit is code, but it requires easy access to the ++ * s3c_sleep_save_phys data before the MMU is switched on, so ++ * we store the code that needs this variable in the .data where ++ * the value can be written to (the .text segment is RO). ++ */ ++ ++ .global s5p6440_sleep_save_phys ++s5p6440_sleep_save_phys: ++ .word 0 ++ ++ /* Sleep magic, the word before the resume entry point so that the ++ * bootloader can check for a resumeable image. */ ++ ++ .word 0x2bedf00d ++ ++ /* s3c_cpu_reusme ++ * ++ * This is the entry point, stored by whatever method the bootloader ++ * requires to get the kernel runnign again. This code expects to be ++ * entered with no caches live and the MMU disabled. It will then ++ * restore the MMU and other basic CP registers saved and restart ++ * the kernel C code to finish the resume code. ++ */ ++ ++ENTRY(s5p6440_cpu_resume) ++ msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE ++ ++ /* __v6_setup from arch/arm/mm/proc-v6.S, ensure that the caches ++ * are thoroughly cleaned just in case the bootloader didn't do it ++ * for us. */ ++ mov r0, #0 ++ mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache ++ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache ++ mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache ++ mcr p15, 0, r0, c7, c10, 4 @ drain write buffer ++ @@mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs ++ @@mcr p15, 0, r0, c7, c7, 0 @ Invalidate I + D caches ++ ++ ldr r0, s5p6440_sleep_save_phys ++ ldmia r0, { r4 - r13 } ++ ++ mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID ++ mcr p15, 0, r5, c3, c0, 0 @ Domain ID ++ mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 ++ mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 ++ mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control ++ mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register ++ ++ mov r0, #0 @ restore copro access controls ++ mcr p15, 0, r11, c1, c0, 2 @ Co-processor access controls ++ mcr p15, 0, r0, c7, c5, 4 ++ ++ ldr r2, =resume_with_mmu ++ mcr p15, 0, r9, c1, c0, 0 /* turn mmu back on */ ++ nop ++ mov pc, r2 /* jump back */ ++ ++ .end ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/Kconfig linux-2.6.28.6/arch/arm/plat-s5pc1xx/Kconfig +--- linux-2.6.28/arch/arm/plat-s5pc1xx/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/Kconfig 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,134 @@ ++# arch/arm/plat-s5pc1xx/Kconfig ++# ++# Copyright 2008 Openmoko, Inc. ++# Copyright 2008 Simtec Electronics ++# Ben Dooks ++# ++# Licensed under GPLv2 ++ ++config PLAT_S5PC1XX ++ bool ++ depends on ARCH_S5PC1XX ++ select PLAT_S3C ++ select ARM_VIC ++ default y ++ select NO_IOPORT ++ select ARCH_REQUIRE_GPIOLIB ++ select S3C_GPIO_TRACK ++ select S3C_GPIO_PULL_UPDOWN ++ select S3C_GPIO_CFG_S5PC1XX ++ select DMABOUNCE ++ help ++ Base platform code for any Samsung S5PC1XX device ++ ++ ++if PLAT_S5PC1XX ++# Configuration options shared by all S5PC1XX implementations ++ ++config CPU_S5PC100_INIT ++ bool ++ help ++ Common initialisation code for the S5PC100 that is shared ++ by other CPUs in the series, such as the S5PC100. ++ ++config CPU_S5PC100_CLOCK ++ bool ++ help ++ Common clock support code for the S3C6400 that is shared ++ by other CPUs in the series, such as the S3C6410. ++ ++# platform specific device setup ++ ++config S5PC1XX_SETUP_I2C0 ++ bool ++ default y ++ help ++ Common setup code for i2c bus 0. ++ ++ Note, currently since i2c0 is always compiled, this setup helper ++ is always compiled with it. ++ ++config S5PC1XX_SETUP_I2C1 ++ bool ++ default y ++ help ++ Common setup code for i2c bus 1. ++ ++config S5PC1XX_ADC ++ bool "S5PC1XX ADC Driver" ++ depends on PLAT_S5PC1XX ++ help ++ ADC (A/D Conversion) driver for Samsung S5PC1XX. ++ ++# FIMC part ++config S5PC1XX_DEV_FIMC0 ++ bool ++ default y ++ help ++ Compile in platform device definitions for FIMC controller 0 ++ ++config S5PC1XX_DEV_FIMC1 ++ bool ++ default y ++ help ++ Compile in platform device definitions for FIMC controller 1 ++ ++config S5PC1XX_DEV_FIMC2 ++ bool ++ default y ++ help ++ Compile in platform device definitions for FIMC controller 2 ++ ++config S5PC1XX_SETUP_FIMC0 ++ bool ++ default y ++ help ++ Common setup code for FIMC controller 0. ++ ++config S5PC1XX_SETUP_FIMC1 ++ bool ++ default y ++ help ++ Common setup code for FIMC controller 1. ++ ++config S5PC1XX_SETUP_FIMC2 ++ bool ++ default y ++ help ++ Common setup code for FIMC controller 2. ++ ++# MIPI-CSIS part ++config S5PC1XX_DEV_CSIS ++ bool ++ default y ++ help ++ Compile in platform device definitions for MIPI-CSIS ++ ++config S5PC1XX_SETUP_CSIS ++ bool ++ default y ++ help ++ Common setup code for MIPI-CSIS ++ ++choice ++ prompt "PWM device support" ++ default NO_PWM ++ ++config S5PC1XX_PWM ++ bool "Support Old API" ++ help ++ Support for exporting the PWM timer blocks via old type API ++ ++config TIMER_PWM ++ bool "PWM device support" ++ help ++ Support for exporting the PWM timer blocks via the pwm device ++ ++config NO_PWM ++ bool "No PWM support" ++ help ++ PWM is not supported ++ ++endchoice ++ ++endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/Makefile linux-2.6.28.6/arch/arm/plat-s5pc1xx/Makefile +--- linux-2.6.28/arch/arm/plat-s5pc1xx/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/Makefile 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,50 @@ ++# arch/arm/plat-s5pc1xx/Makefile ++# ++# Copyright 2008 Openmoko, Inc. ++# Copyright 2008 Simtec Electronics ++# ++# Licensed under GPLv2 ++ ++obj-y := ++obj-m := ++obj-n := dummy.o ++obj- := ++ ++# Core files ++ ++obj-y += dev-uart.o devs.o ++obj-y += cpu.o ++obj-y += s5pc1xx-time.o ++obj-y += irq.o ++obj-y += irq-eint.o ++obj-y += clock.o ++obj-y += gpiolib.o ++obj-y += bootmem.o ++ ++# CPU support ++ ++obj-$(CONFIG_CPU_S5PC100_INIT) += s5pc100-init.o ++obj-$(CONFIG_CPU_S5PC100_CLOCK) += s5pc100-clock.o changediv.o ++obj-$(CONFIG_PM) += pm.o ++obj-$(CONFIG_PM) += sleep.o ++obj-$(CONFIG_CPU_FREQ) += s5pc1xx-cpufreq.o ltc3714.o ++ ++# Device setup ++obj-$(CONFIG_S5PC1XX_SETUP_I2C0) += setup-i2c0.o ++obj-$(CONFIG_S5PC1XX_SETUP_I2C1) += setup-i2c1.o ++obj-$(CONFIG_S5PC1XX_ADC) += adc.o ++obj-$(CONFIG_TIMER_PWM) += pwm.o ++obj-$(CONFIG_S5PC1XX_PWM) += pwm-s5pc100.o ++ ++# Device setup - FIMC ++obj-$(CONFIG_S5PC1XX_DEV_FIMC0) += dev-fimc0.o ++obj-$(CONFIG_S5PC1XX_DEV_FIMC1) += dev-fimc1.o ++obj-$(CONFIG_S5PC1XX_DEV_FIMC2) += dev-fimc2.o ++obj-$(CONFIG_S5PC1XX_SETUP_FIMC0) += setup-fimc0.o ++obj-$(CONFIG_S5PC1XX_SETUP_FIMC1) += setup-fimc1.o ++obj-$(CONFIG_S5PC1XX_SETUP_FIMC2) += setup-fimc2.o ++ ++# Device setup - MIPI-CSI2 ++obj-$(CONFIG_S5PC1XX_DEV_CSIS) += dev-csis.o ++obj-$(CONFIG_S5PC1XX_SETUP_CSIS) += setup-csis.o ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/adc.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/adc.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/adc.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/adc.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,369 @@ ++/* linux/arch/arm/plat-s5c1xx/adc.c ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * Copyright (c) 2004 Arnaud Patard ++ * iPAQ H1940 touchscreen support ++ * ++ * ChangeLog ++ * ++ * 2004-09-05: Herbert Pötzl ++ * - added clock (de-)allocation code ++ * ++ * 2005-03-06: Arnaud Patard ++ * - h1940_ -> s3c24xx (this driver is now also used on the n30 ++ * machines :P) ++ * - Debug messages are now enabled with the config option ++ * TOUCHSCREEN_S3C_DEBUG ++ * - Changed the way the value are read ++ * - Input subsystem should now work ++ * - Use ioremap and readl/writel ++ * ++ * 2005-03-23: Arnaud Patard ++ * - Make use of some undocumented features of the touchscreen ++ * controller ++ * ++ */ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#define ADC_MINOR 131 ++#define ADC_INPUT_PIN _IOW('S', 0x0c, unsigned long) ++ ++#define ADC_WITH_TOUCHSCREEN ++ ++static struct clk *adc_clock; ++ ++static void __iomem *base_addr; ++static int adc_port = 0; ++struct s3c_adc_mach_info *plat_data; ++ ++ ++#ifdef ADC_WITH_TOUCHSCREEN ++static DEFINE_MUTEX(adc_mutex); ++ ++static unsigned long data_for_ADCCON; ++static unsigned long data_for_ADCTSC; ++ ++static void s3c_adc_save_SFR_on_ADC(void) ++{ ++ data_for_ADCCON = readl(base_addr + S3C_ADCCON); ++ data_for_ADCTSC = readl(base_addr + S3C_ADCTSC); ++} ++ ++static void s3c_adc_restore_SFR_on_ADC(void) ++{ ++ writel(data_for_ADCCON, base_addr + S3C_ADCCON); ++ writel(data_for_ADCTSC, base_addr + S3C_ADCTSC); ++} ++#else ++static struct resource *adc_mem; ++#endif ++ ++static int s3c_adc_open(struct inode *inode, struct file *file) ++{ ++ printk(KERN_INFO " s3c_adc_open() entered\n"); ++ return 0; ++} ++ ++unsigned int s3c_adc_convert(void) ++{ ++ unsigned int adc_return = 0; ++ unsigned long data0; ++ unsigned long data1; ++ ++ writel(readl(base_addr + S3C_ADCCON) | S3C_ADCCON_SELMUX(adc_port), base_addr + S3C_ADCCON); ++ ++ udelay(10); ++ ++ writel(readl(base_addr + S3C_ADCCON) | S3C_ADCCON_ENABLE_START, base_addr + S3C_ADCCON); ++ ++ do { ++ data0 = readl(base_addr + S3C_ADCCON); ++ } while(!(data0 & S3C_ADCCON_ECFLG)); ++ ++ data1 = readl(base_addr + S3C_ADCDAT0); ++ ++ if (plat_data->resolution == 12) ++ adc_return = data1 & S3C_ADCDAT0_XPDATA_MASK_12BIT; ++ else ++ adc_return = data1 & S3C_ADCDAT0_XPDATA_MASK; ++ ++ return adc_return; ++} ++ ++ ++int s3c_adc_get(struct s3c_adc_request *req) ++{ ++ unsigned adc_channel = req->channel; ++ int adc_value_ret = 0; ++ ++ adc_value_ret = s3c_adc_convert(); ++ ++ req->callback(adc_channel, req->param, adc_value_ret); ++ ++ return 0; ++} ++EXPORT_SYMBOL(s3c_adc_get); ++ ++static ssize_t ++s3c_adc_read(struct file *file, char __user * buffer, ++ size_t size, loff_t * pos) ++{ ++ int adc_value = 0; ++ ++ printk(KERN_INFO " s3c_adc_read() entered\n"); ++ ++#ifdef ADC_WITH_TOUCHSCREEN ++ mutex_lock(&adc_mutex); ++ s3c_adc_save_SFR_on_ADC(); ++#endif ++ ++ adc_value = s3c_adc_convert(); ++ ++#ifdef ADC_WITH_TOUCHSCREEN ++ s3c_adc_restore_SFR_on_ADC(); ++ mutex_unlock(&adc_mutex); ++#endif ++ ++ printk(KERN_INFO " Converted Value: %03d\n", adc_value); ++ ++ if (copy_to_user(buffer, &adc_value, sizeof(unsigned int))) { ++ return -EFAULT; ++ } ++ return sizeof(unsigned int); ++} ++ ++ ++static int s3c_adc_ioctl(struct inode *inode, struct file *file, ++ unsigned int cmd, unsigned long arg) ++{ ++ ++ printk(KERN_INFO " s3c_adc_ioctl(cmd:: %d) entered\n", cmd); ++ ++ switch (cmd) { ++ case ADC_INPUT_PIN: ++ adc_port = (unsigned int) arg; ++ ++ if (adc_port >= 4) ++ printk(" %d is already reserved for TouchScreen\n", adc_port); ++ return 0; ++ ++ default: ++ return -ENOIOCTLCMD; ++ } ++} ++ ++static struct file_operations s3c_adc_fops = { ++ .owner = THIS_MODULE, ++ .read = s3c_adc_read, ++ .open = s3c_adc_open, ++ .ioctl = s3c_adc_ioctl, ++}; ++ ++static struct miscdevice s3c_adc_miscdev = { ++ .minor = ADC_MINOR, ++ .name = "adc", ++ .fops = &s3c_adc_fops, ++}; ++ ++static struct s3c_adc_mach_info *s3c_adc_get_platdata(struct device *dev) ++{ ++ if(dev->platform_data != NULL) ++ { ++ printk(KERN_INFO "ADC platform data read\n"); ++ return (struct s3c_adc_mach_info*) dev->platform_data; ++ } else { ++ printk(KERN_INFO "No ADC platform data \n"); ++ return 0; ++ } ++} ++ ++/* ++ * The functions for inserting/removing us as a module. ++ */ ++ ++static int __init s3c_adc_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ struct device *dev; ++ int ret; ++ int size; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ dev = &pdev->dev; ++ ++ if(res == NULL){ ++ dev_err(dev,"no memory resource specified\n"); ++ return -ENOENT; ++ } ++ ++ size = (res->end - res->start) + 1; ++ ++#if !defined(ADC_WITH_TOUCHSCREEN) ++ adc_mem = request_mem_region(res->start, size, pdev->name); ++ if(adc_mem == NULL){ ++ dev_err(dev, "failed to get memory region\n"); ++ ret = -ENOENT; ++ goto err_req; ++ } ++#endif ++ ++ base_addr = ioremap(res->start, size); ++ if(base_addr == NULL){ ++ dev_err(dev,"fail to ioremap() region\n"); ++ ret = -ENOENT; ++ goto err_map; ++ } ++ ++ adc_clock = clk_get(&pdev->dev, "adc"); ++ ++ if(IS_ERR(adc_clock)){ ++ dev_err(dev,"failed to fine ADC clock source\n"); ++ ret = PTR_ERR(adc_clock); ++ goto err_clk; ++ } ++ ++ clk_enable(adc_clock); ++ ++ /* read platform data from device struct */ ++ plat_data = s3c_adc_get_platdata(&pdev->dev); ++ ++ if ((plat_data->presc & 0xff) > 0) ++ writel(S3C_ADCCON_PRSCEN | S3C_ADCCON_PRSCVL(plat_data->presc & 0xff), base_addr + S3C_ADCCON); ++ else ++ writel(0, base_addr + S3C_ADCCON); ++ ++ /* Initialise registers */ ++ if ((plat_data->delay & 0xffff) > 0) ++ writel(plat_data->delay & 0xffff, base_addr + S3C_ADCDLY); ++ ++ if (plat_data->resolution == 12) ++ writel(readl(base_addr + S3C_ADCCON) | S3C_ADCCON_RESSEL_12BIT, base_addr + S3C_ADCCON); ++ ++ ret = misc_register(&s3c_adc_miscdev); ++ if (ret) { ++ printk (KERN_ERR "cannot register miscdev on minor=%d (%d)\n", ++ ADC_MINOR, ret); ++ goto err_clk; ++ } ++ ++ printk(KERN_INFO "S5PC1XX ADC driver successfully probed\n"); ++ ++ return 0; ++ ++err_clk: ++ clk_disable(adc_clock); ++ clk_put(adc_clock); ++ ++err_map: ++ iounmap(base_addr); ++ ++#if !defined(ADC_WITH_TOUCHSCREEN) ++err_req: ++ release_resource(adc_mem); ++ kfree(adc_mem); ++#endif ++ ++ return ret; ++} ++ ++ ++static int s3c_adc_remove(struct platform_device *dev) ++{ ++ printk(KERN_INFO "s3c_adc_remove() of ADC called !\n"); ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static unsigned int adccon, adctsc, adcdly; ++ ++static int s3c_adc_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ adccon = readl(base_addr + S3C_ADCCON); ++ adctsc = readl(base_addr + S3C_ADCTSC); ++ adcdly = readl(base_addr + S3C_ADCDLY); ++ ++ clk_disable(adc_clock); ++ ++ return 0; ++} ++ ++static int s3c_adc_resume(struct platform_device *pdev) ++{ ++ clk_enable(adc_clock); ++ ++ writel(adccon, base_addr + S3C_ADCCON); ++ writel(adctsc, base_addr + S3C_ADCTSC); ++ writel(adcdly, base_addr + S3C_ADCDLY); ++ ++ return 0; ++} ++#else ++#define s3c_adc_suspend NULL ++#define s3c_adc_resume NULL ++#endif ++ ++static struct platform_driver s3c_adc_driver = { ++ .probe = s3c_adc_probe, ++ .remove = s3c_adc_remove, ++ .suspend = s3c_adc_suspend, ++ .resume = s3c_adc_resume, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "s3c-adc", ++ }, ++}; ++ ++static char banner[] __initdata = KERN_INFO "S5PC1XX ADC driver, (c) 2008 Samsung Electronics\n"; ++ ++int __init s3c_adc_init(void) ++{ ++ printk(banner); ++ return platform_driver_register(&s3c_adc_driver); ++} ++ ++void __exit s3c_adc_exit(void) ++{ ++ platform_driver_unregister(&s3c_adc_driver); ++} ++ ++module_init(s3c_adc_init); ++module_exit(s3c_adc_exit); ++ ++MODULE_AUTHOR("boyko.lee@samsung.com"); ++MODULE_DESCRIPTION("S5PC1XX ADC driver"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/bootmem.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/bootmem.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/bootmem.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/bootmem.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,159 @@ ++/* linux/arch/arm/plat-s5pc1xx/bootmem.c ++ * ++ * Copyright 2009 Samsung Electronics ++ * Jinsung Yang ++ * http://samsungsemi.com/ ++ * ++ * Bootmem helper functions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "plat/media.h" ++ ++static struct s3c_media_device s3c_mdevs[] = { ++#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC ++ { ++ .id = S3C_MDEV_FIMC, ++ .name = "fimc", ++ .memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC * SZ_1K, ++ .paddr = 0, ++ }, ++#endif ++ ++#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_POST ++ { ++ .id = S3C_MDEV_POST, ++ .name = "pp", ++ .memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_POST * SZ_1K, ++ .paddr = 0, ++ }, ++#endif ++ ++#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV ++ { ++ .id = S3C_MDEV_TV, ++ .name = "tv", ++ .memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV * SZ_1K, ++ .paddr = 0, ++ }, ++#endif ++ ++#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC ++ { ++ .id = S3C_MDEV_MFC, ++ .name = "mfc", ++ .memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC * SZ_1K, ++ .paddr = 0, ++ }, ++#endif ++ ++#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG ++ { ++ .id = S3C_MDEV_JPEG, ++ .name = "jpeg", ++ .memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG * SZ_1K, ++ .paddr = 0, ++ }, ++#endif ++ ++#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_CMM ++ { ++ .id = S3C_MDEV_CMM, ++ .name = "cmm", ++ .memsize = CONFIG_VIDEO_SAMSUNG_MEMSIZE_CMM * SZ_1K, ++ .paddr = 0, ++ } ++#endif ++}; ++ ++static struct s3c_media_device *s3c_get_media_device(int dev_id) ++{ ++ struct s3c_media_device *mdev = NULL; ++ int i, found; ++ ++ if (dev_id < 0 || dev_id >= S3C_MDEV_MAX) ++ return NULL; ++ ++ i = 0; ++ found = 0; ++ while (!found && (i < S3C_MDEV_MAX)) { ++ mdev = &s3c_mdevs[i]; ++ if (mdev->id == dev_id) ++ found = 1; ++ else ++ i++; ++ } ++ ++ if (!found) ++ mdev = NULL; ++ ++ return mdev; ++} ++ ++dma_addr_t s3c_get_media_memory(int dev_id) ++{ ++ struct s3c_media_device *mdev; ++ ++ mdev = s3c_get_media_device(dev_id); ++ if (!mdev){ ++ printk(KERN_ERR "invalid media device\n"); ++ return 0; ++ } ++ ++ if (!mdev->paddr) { ++ printk(KERN_ERR "no memory for %s\n", mdev->name); ++ return 0; ++ } ++ ++ return mdev->paddr; ++} ++EXPORT_SYMBOL(s3c_get_media_memory); ++ ++size_t s3c_get_media_memsize(int dev_id) ++{ ++ struct s3c_media_device *mdev; ++ ++ mdev = s3c_get_media_device(dev_id); ++ if (!mdev){ ++ printk(KERN_ERR "invalid media device\n"); ++ return 0; ++ } ++ ++ return mdev->memsize; ++} ++EXPORT_SYMBOL(s3c_get_media_memsize); ++ ++void s5pc1xx_reserve_bootmem(void) ++{ ++ struct s3c_media_device *mdev; ++ int i; ++ ++ for(i = 0; i < sizeof(s3c_mdevs) / sizeof(s3c_mdevs[0]); i++) { ++ mdev = &s3c_mdevs[i]; ++ if (mdev->memsize > 0) { ++ mdev->paddr = virt_to_phys(alloc_bootmem_low(mdev->memsize)); ++ printk(KERN_INFO \ ++ "s5pc1xx: %lu bytes SDRAM reserved " ++ "for %s at 0x%08x\n", ++ (unsigned long) mdev->memsize, \ ++ mdev->name, mdev->paddr); ++ } ++ } ++} ++ ++/* FIXME: temporary implementation to avoid compile error */ ++int dma_needs_bounce(struct device *dev, dma_addr_t addr, size_t size) ++{ ++ return 0; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/changediv.S linux-2.6.28.6/arch/arm/plat-s5pc1xx/changediv.S +--- linux-2.6.28/arch/arm/plat-s5pc1xx/changediv.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/changediv.S 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,89 @@ ++/* linux/arch/arm/plat-s5pc1xx/changediv.S ++ * ++ * Copyright (c) 2004 Simtec Electronics ++ * Ben Dooks ++ * ++ * S5PC100 Clock Change (DVFS) support ++ * ++ * Based on PXA/SA1100 sleep code by: ++ * Nicolas Pitre, (c) 2002 Monta Vista Software Inc ++ * Cliff Brake, (c) 2001 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++*/ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++ ++/* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not ++ * reset the UART configuration, only enable if you really need this! ++*/ ++ .text ++ ++ /* ChangeClkDiv0 ++ * ++ * save enough of the CPU state to allow us to re-start ++ * pm.c code. as we store items like the sp/lr, we will ++ * end up returning from this function when the cpu resumes ++ * so the return value is set to mark this. ++ * ++ * This arangement means we avoid having to flush the cache ++ * from this code. ++ * ++ * entry: ++ * r0 = pointer to save block ++ * ++ * exit: ++ * r0 = 0 => we stored everything ++ * 1 => resumed from sleep ++ */ ++ ++ENTRY(ChangeClkDiv0) ++ stmfd sp!, { r0 - r5 } ++ ++ ldr r1, =S5P_CLK_DIV0 ++ ldr r2, [r1] ++ mov r3, #0 ++ ++loopcd: ++ add r3, r3, #1 ++ mov r4, #0 ++ ++ mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier instruction ++ mcr p15, 0, r2, c7, c10, 5 @ data memory barrier operation ++ ++ cmp r3, #2 ++ streq r0, [r1] ++ ++loop1000: ++ add r4, r4, #1 ++ cmp r4, #0x2000 ++ bne loop1000 ++ cmp r3, #2 ++ bne loopcd ++ ++ ldmfd sp!, { r0 - r5 } ++ mov pc, lr ++ ++ .ltorg ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/clock.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/clock.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/clock.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/clock.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,751 @@ ++/* linux/arch/arm/plat-s5pc1xx/clock.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5PC1XX Base clock support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++struct clk clk_27m = { ++ .name = "clk_27m", ++ .id = -1, ++ .rate = 27000000, ++}; ++ ++static int clk_48m_ctrl(struct clk *clk, int enable) ++{ ++ unsigned long flags; ++ u32 val; ++ ++ local_irq_save(flags); ++ ++ val = __raw_readl(S5P_CLK_SRC1); ++ if (enable) ++ val |= S5P_CLKSRC1_CLK48M_MASK; ++ else ++ val &= ~S5P_CLKSRC1_CLK48M_MASK; ++ ++ __raw_writel(val, S5P_CLK_SRC1); ++ local_irq_restore(flags); ++ ++ return 0; ++} ++ ++struct clk clk_48m = { ++ .name = "clk_48m", ++ .id = -1, ++ .rate = 48000000, ++ .enable = clk_48m_ctrl, ++}; ++ ++struct clk clk_54m = { ++ .name = "clk_54m", ++ .id = -1, ++ .rate = 54000000, ++}; ++ ++static int inline s5pc1xx_clk_gate(void __iomem *reg, ++ struct clk *clk, ++ int enable) ++{ ++ unsigned int ctrlbit = clk->ctrlbit; ++ u32 con; ++ ++ con = __raw_readl(reg); ++ ++ if (enable) ++ con |= ctrlbit; ++ else ++ con &= ~ctrlbit; ++ ++ __raw_writel(con, reg); ++ return 0; ++} ++ ++static int s5pc1xx_setrate_sclk_cam(struct clk *clk, unsigned long rate) ++{ ++ u32 shift = 24; ++ u32 cam_div, cfg; ++ unsigned long src_clk = clk_get_rate(clk->parent); ++ ++ cam_div = src_clk / rate; ++ ++ if (cam_div > 32) ++ cam_div = 32; ++ ++ cfg = __raw_readl(S5P_CLK_DIV1); ++ cfg &= ~(0x1f << shift); ++ cfg |= ((cam_div - 1) << shift); ++ __raw_writel(cfg, S5P_CLK_DIV1); ++ ++ printk("parent clock for camera: %ld.%03ld MHz, divisor: %d\n", \ ++ print_mhz(src_clk), cam_div); ++ ++ return 0; ++} ++ ++static int s5pc1xx_clk_d00_ctrl(struct clk *clk, int enable) ++{ ++ return s5pc1xx_clk_gate(S5P_CLKGATE_D00, clk, enable); ++} ++ ++static int s5pc1xx_clk_d01_ctrl(struct clk *clk, int enable) ++{ ++ return s5pc1xx_clk_gate(S5P_CLKGATE_D01, clk, enable); ++} ++ ++static int s5pc1xx_clk_d02_ctrl(struct clk *clk, int enable) ++{ ++ return s5pc1xx_clk_gate(S5P_CLKGATE_D02, clk, enable); ++} ++ ++static int s5pc1xx_clk_d10_ctrl(struct clk *clk, int enable) ++{ ++ return s5pc1xx_clk_gate(S5P_CLKGATE_D10, clk, enable); ++} ++ ++static int s5pc1xx_clk_d11_ctrl(struct clk *clk, int enable) ++{ ++ return s5pc1xx_clk_gate(S5P_CLKGATE_D11, clk, enable); ++} ++ ++static int s5pc1xx_clk_d12_ctrl(struct clk *clk, int enable) ++{ ++ return s5pc1xx_clk_gate(S5P_CLKGATE_D12, clk, enable); ++} ++ ++static int s5pc1xx_clk_d13_ctrl(struct clk *clk, int enable) ++{ ++ return s5pc1xx_clk_gate(S5P_CLKGATE_D13, clk, enable); ++} ++ ++static int s5pc1xx_clk_d14_ctrl(struct clk *clk, int enable) ++{ ++ return s5pc1xx_clk_gate(S5P_CLKGATE_D14, clk, enable); ++} ++ ++static int s5pc1xx_clk_d15_ctrl(struct clk *clk, int enable) ++{ ++ return s5pc1xx_clk_gate(S5P_CLKGATE_D15, clk, enable); ++} ++ ++static int s5pc1xx_clk_d20_ctrl(struct clk *clk, int enable) ++{ ++ return s5pc1xx_clk_gate(S5P_CLKGATE_D20, clk, enable); ++} ++ ++int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable) ++{ ++ return s5pc1xx_clk_gate(S5P_SCLKGATE0, clk, enable); ++} ++ ++int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable) ++{ ++ return s5pc1xx_clk_gate(S5P_SCLKGATE1, clk, enable); ++} ++ ++static struct clk init_clocks_disable[] = { ++ { ++ .name = "mipi-dsim", ++ .id = -1, ++ .parent = &clk_27m, ++ .enable = s5pc1xx_clk_d11_ctrl, ++ .ctrlbit = S5P_CLKGATE_D11_DSI, ++ }, { ++ .name = "mipi-csis", ++ .id = -1, ++ .parent = &clk_27m, ++ .enable = s5pc1xx_clk_d11_ctrl, ++ .ctrlbit = S5P_CLKGATE_D11_CSI, ++ }, { ++ .name = "ccan", ++ .id = 0, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d14_ctrl, ++ .ctrlbit = S5P_CLKGATE_D14_CCAN0, ++ }, { ++ .name = "ccan", ++ .id = 1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d14_ctrl, ++ .ctrlbit = S5P_CLKGATE_D14_CCAN1, ++ }, { ++ .name = "keypad", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d15_ctrl, ++ .ctrlbit = S5P_CLKGATE_D15_KEYIF, ++ }, { ++ .name = "hclkd2", ++ .id = -1, ++ .parent = NULL, ++ .enable = s5pc1xx_clk_d20_ctrl, ++ .ctrlbit = S5P_CLKGATE_D20_HCLKD2, ++ }, { ++ .name = "iis-d2", ++ .id = -1, ++ .parent = NULL, ++ .enable = s5pc1xx_clk_d20_ctrl, ++ .ctrlbit = S5P_CLKGATE_D20_I2SD2, ++ }, { ++ .name = "otg", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s5pc1xx_clk_d10_ctrl, ++ .ctrlbit = S5P_CLKGATE_D10_USBOTG, ++ }, ++}; ++ ++static struct clk init_clocks[] = { ++ /* System1 (D0_0) devices */ ++ { ++ .name = "intc", ++ .id = -1, ++ .parent = &clk_hd0, ++ .enable = s5pc1xx_clk_d00_ctrl, ++ .ctrlbit = S5P_CLKGATE_D00_INTC, ++ }, { ++ .name = "tzic", ++ .id = -1, ++ .parent = &clk_hd0, ++ .enable = s5pc1xx_clk_d00_ctrl, ++ .ctrlbit = S5P_CLKGATE_D00_TZIC, ++ }, { ++ .name = "cf-ata", ++ .id = -1, ++ .parent = &clk_hd0, ++ .enable = s5pc1xx_clk_d00_ctrl, ++ .ctrlbit = S5P_CLKGATE_D00_CFCON, ++ }, { ++ .name = "mdma", ++ .id = -1, ++ .parent = &clk_hd0, ++ .enable = s5pc1xx_clk_d00_ctrl, ++ .ctrlbit = S5P_CLKGATE_D00_MDMA, ++ }, { ++ .name = "g2d", ++ .id = -1, ++ .parent = &clk_hd0, ++ .enable = s5pc1xx_clk_d00_ctrl, ++ .ctrlbit = S5P_CLKGATE_D00_G2D, ++ }, { ++ .name = "secss", ++ .id = -1, ++ .parent = &clk_hd0, ++ .enable = s5pc1xx_clk_d00_ctrl, ++ .ctrlbit = S5P_CLKGATE_D00_SECSS, ++ }, { ++ .name = "cssys", ++ .id = -1, ++ .parent = &clk_hd0, ++ .enable = s5pc1xx_clk_d00_ctrl, ++ .ctrlbit = S5P_CLKGATE_D00_CSSYS, ++ }, ++ ++ /* Memory (D0_1) devices */ ++ { ++ .name = "dmc", ++ .id = -1, ++ .parent = &clk_hd0, ++ .enable = s5pc1xx_clk_d01_ctrl, ++ .ctrlbit = S5P_CLKGATE_D01_DMC, ++ }, { ++ .name = "sromc", ++ .id = -1, ++ .parent = &clk_hd0, ++ .enable = s5pc1xx_clk_d01_ctrl, ++ .ctrlbit = S5P_CLKGATE_D01_SROMC, ++ }, { ++ .name = "onenand", ++ .id = -1, ++ .parent = &clk_hd0, ++ .enable = s5pc1xx_clk_d01_ctrl, ++ .ctrlbit = S5P_CLKGATE_D01_ONENAND, ++ }, { ++ .name = "nand", ++ .id = -1, ++ .parent = &clk_hd0, ++ .enable = s5pc1xx_clk_d01_ctrl, ++ .ctrlbit = S5P_CLKGATE_D01_NFCON, ++ }, { ++ .name = "intmem", ++ .id = -1, ++ .parent = &clk_hd0, ++ .enable = s5pc1xx_clk_d01_ctrl, ++ .ctrlbit = S5P_CLKGATE_D01_INTMEM, ++ }, { ++ .name = "ebi", ++ .id = -1, ++ .parent = &clk_hd0, ++ .enable = s5pc1xx_clk_d01_ctrl, ++ .ctrlbit = S5P_CLKGATE_D01_EBI, ++ }, ++ ++ /* System2 (D0_2) devices */ ++ { ++ .name = "seckey", ++ .id = -1, ++ .parent = &clk_pd0, ++ .enable = s5pc1xx_clk_d02_ctrl, ++ .ctrlbit = S5P_CLKGATE_D02_SECKEY, ++ }, { ++ .name = "sdm", ++ .id = -1, ++ .parent = &clk_hd0, ++ .enable = s5pc1xx_clk_d02_ctrl, ++ .ctrlbit = S5P_CLKGATE_D02_SDM, ++ }, ++ ++ /* File (D1_0) devices */ ++ { ++ .name = "pdma0", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s5pc1xx_clk_d10_ctrl, ++ .ctrlbit = S5P_CLKGATE_D10_PDMA0, ++ }, { ++ .name = "pdma1", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s5pc1xx_clk_d10_ctrl, ++ .ctrlbit = S5P_CLKGATE_D10_PDMA1, ++ }, { ++ .name = "usb-host", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s5pc1xx_clk_d10_ctrl, ++ .ctrlbit = S5P_CLKGATE_D10_USBHOST, ++ }, { ++ .name = "modem", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s5pc1xx_clk_d10_ctrl, ++ .ctrlbit = S5P_CLKGATE_D10_MODEMIF, ++ }, { ++ .name = "hsmmc", ++ .id = 0, ++ .parent = &clk_h, ++ .enable = s5pc1xx_clk_d10_ctrl, ++ .ctrlbit = S5P_CLKGATE_D10_HSMMC0, ++ }, { ++ .name = "hsmmc", ++ .id = 1, ++ .parent = &clk_h, ++ .enable = s5pc1xx_clk_d10_ctrl, ++ .ctrlbit = S5P_CLKGATE_D10_HSMMC1, ++ }, { ++ .name = "hsmmc", ++ .id = 2, ++ .parent = &clk_h, ++ .enable = s5pc1xx_clk_d10_ctrl, ++ .ctrlbit = S5P_CLKGATE_D10_HSMMC2, ++ }, ++ ++ /* Multimedia1 (D1_1) devices */ ++ { ++ .name = "lcd", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s5pc1xx_clk_d11_ctrl, ++ .ctrlbit = S5P_CLKGATE_D11_LCD, ++ }, { ++ .name = "rotator", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s5pc1xx_clk_d11_ctrl, ++ .ctrlbit = S5P_CLKGATE_D11_ROTATOR, ++ }, { ++ .name = "fimc0", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s5pc1xx_clk_d11_ctrl, ++ .ctrlbit = S5P_CLKGATE_D11_FIMC0, ++ }, { ++ .name = "fimc1", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s5pc1xx_clk_d11_ctrl, ++ .ctrlbit = S5P_CLKGATE_D11_FIMC1, ++ }, { ++ .name = "fimc2", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s5pc1xx_clk_d11_ctrl, ++ .ctrlbit = S5P_CLKGATE_D11_FIMC2, ++ }, { ++ .name = "jpeg", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s5pc1xx_clk_d11_ctrl, ++ .ctrlbit = S5P_CLKGATE_D11_JPEG, ++ }, { ++ .name = "g3d", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s5pc1xx_clk_d11_ctrl, ++ .ctrlbit = S5P_CLKGATE_D11_G3D, ++ }, ++ ++ /* Multimedia2 (D1_2) devices */ ++ { ++ .name = "tv", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s5pc1xx_clk_d12_ctrl, ++ .ctrlbit = S5P_CLKGATE_D12_TV, ++ }, { ++ .name = "vp", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s5pc1xx_clk_d12_ctrl, ++ .ctrlbit = S5P_CLKGATE_D12_VP, ++ }, { ++ .name = "mixer", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s5pc1xx_clk_d12_ctrl, ++ .ctrlbit = S5P_CLKGATE_D12_MIXER, ++ }, { ++ .name = "hdmi", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s5pc1xx_clk_d12_ctrl, ++ .ctrlbit = S5P_CLKGATE_D12_HDMI, ++ }, { ++ .name = "mfc", ++ .id = -1, ++ .parent = &clk_h, ++ .enable = s5pc1xx_clk_d12_ctrl, ++ .ctrlbit = S5P_CLKGATE_D12_MFC, ++ }, ++ ++ /* System (D1_3) devices */ ++ { ++ .name = "chipid", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d13_ctrl, ++ .ctrlbit = S5P_CLKGATE_D13_CHIPID, ++ }, { ++ .name = "gpio", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d13_ctrl, ++ .ctrlbit = S5P_CLKGATE_D13_GPIO, ++ }, { ++ .name = "apc", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d13_ctrl, ++ .ctrlbit = S5P_CLKGATE_D13_APC, ++ }, { ++ .name = "iec", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d13_ctrl, ++ .ctrlbit = S5P_CLKGATE_D13_IEC, ++ }, { ++ .name = "timers", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d13_ctrl, ++ .ctrlbit = S5P_CLKGATE_D13_PWM, ++ }, { ++ .name = "systimer", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d13_ctrl, ++ .ctrlbit = S5P_CLKGATE_D13_SYSTIMER, ++ }, { ++ .name = "watchdog", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d13_ctrl, ++ .ctrlbit = S5P_CLKGATE_D13_WDT, ++ }, { ++ .name = "rtc", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d13_ctrl, ++ .ctrlbit = S5P_CLKGATE_D13_RTC, ++ }, ++ ++ /* Connectivity (D1_4) devices */ ++ { ++ .name = "uart", ++ .id = 0, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d14_ctrl, ++ .ctrlbit = S5P_CLKGATE_D14_UART0, ++ }, { ++ .name = "uart", ++ .id = 1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d14_ctrl, ++ .ctrlbit = S5P_CLKGATE_D14_UART1, ++ }, { ++ .name = "uart", ++ .id = 2, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d14_ctrl, ++ .ctrlbit = S5P_CLKGATE_D14_UART2, ++ }, { ++ .name = "uart", ++ .id = 3, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d14_ctrl, ++ .ctrlbit = S5P_CLKGATE_D14_UART3, ++ }, { ++ .name = "i2c", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d14_ctrl, ++ .ctrlbit = S5P_CLKGATE_D14_IIC, ++ }, { ++ .name = "hdmi-i2c", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d14_ctrl, ++ .ctrlbit = S5P_CLKGATE_D14_HDMI_IIC, ++ }, { ++ .name = "spi", ++ .id = 0, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d14_ctrl, ++ .ctrlbit = S5P_CLKGATE_D14_SPI0, ++ }, { ++ .name = "spi", ++ .id = 1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d14_ctrl, ++ .ctrlbit = S5P_CLKGATE_D14_SPI1, ++ }, { ++ .name = "spi", ++ .id = 2, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d14_ctrl, ++ .ctrlbit = S5P_CLKGATE_D14_SPI2, ++ }, { ++ .name = "irda", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d14_ctrl, ++ .ctrlbit = S5P_CLKGATE_D14_IRDA, ++ }, { ++ .name = "hsitx", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d14_ctrl, ++ .ctrlbit = S5P_CLKGATE_D14_HSITX, ++ }, { ++ .name = "hsirx", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d14_ctrl, ++ .ctrlbit = S5P_CLKGATE_D14_HSIRX, ++ }, ++ ++ /* Audio (D1_5) devices */ ++ { ++ .name = "iis", ++ .id = 0, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d15_ctrl, ++ .ctrlbit = S5P_CLKGATE_D15_IIS0, ++ }, { ++ .name = "iis", ++ .id = 1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d15_ctrl, ++ .ctrlbit = S5P_CLKGATE_D15_IIS1, ++ }, { ++ .name = "iis", ++ .id = 2, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d15_ctrl, ++ .ctrlbit = S5P_CLKGATE_D15_IIS2, ++ }, { ++ .name = "ac97", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d15_ctrl, ++ .ctrlbit = S5P_CLKGATE_D15_AC97, ++ }, { ++ .name = "pcm", ++ .id = 0, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d15_ctrl, ++ .ctrlbit = S5P_CLKGATE_D15_PCM0, ++ }, { ++ .name = "pcm", ++ .id = 1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d15_ctrl, ++ .ctrlbit = S5P_CLKGATE_D15_PCM1, ++ }, { ++ .name = "spdif", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d15_ctrl, ++ .ctrlbit = S5P_CLKGATE_D15_SPDIF, ++ }, { ++ .name = "adc", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d15_ctrl, ++ .ctrlbit = S5P_CLKGATE_D15_TSADC, ++ }, { ++ .name = "keyif", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d15_ctrl, ++ .ctrlbit = S5P_CLKGATE_D15_KEYIF, ++ }, { ++ .name = "cg", ++ .id = -1, ++ .parent = &clk_p, ++ .enable = s5pc1xx_clk_d15_ctrl, ++ .ctrlbit = S5P_CLKGATE_D15_CG, ++ }, ++ ++ /* Audio (D2_0) devices: all disabled */ ++ ++ /* Special Clocks 1 */ ++ { ++ .name = "sclk_hpm", ++ .id = -1, ++ .parent = NULL, ++ .enable = s5pc1xx_sclk0_ctrl, ++ .ctrlbit = S5P_CLKGATE_SCLK0_HPM, ++ }, { ++ .name = "sclk_onenand", ++ .id = -1, ++ .parent = NULL, ++ .enable = s5pc1xx_sclk0_ctrl, ++ .ctrlbit = S5P_CLKGATE_SCLK0_ONENAND, ++ }, { ++ .name = "sclk_spi_48", ++ .id = 0, ++ .parent = &clk_48m, ++ .enable = s5pc1xx_sclk0_ctrl, ++ .ctrlbit = S5P_CLKGATE_SCLK0_SPI0_48, ++ }, { ++ .name = "sclk_spi_48", ++ .id = 1, ++ .parent = &clk_48m, ++ .enable = s5pc1xx_sclk0_ctrl, ++ .ctrlbit = S5P_CLKGATE_SCLK0_SPI1_48, ++ }, { ++ .name = "sclk_spi_48", ++ .id = 2, ++ .parent = &clk_48m, ++ .enable = s5pc1xx_sclk0_ctrl, ++ .ctrlbit = S5P_CLKGATE_SCLK0_SPI2_48, ++ }, { ++ .name = "sclk_mmc_48", ++ .id = 0, ++ .parent = &clk_48m, ++ .enable = s5pc1xx_sclk0_ctrl, ++ .ctrlbit = S5P_CLKGATE_SCLK0_MMC0_48, ++ }, { ++ .name = "sclk_mmc_48", ++ .id = 1, ++ .parent = &clk_48m, ++ .enable = s5pc1xx_sclk0_ctrl, ++ .ctrlbit = S5P_CLKGATE_SCLK0_MMC1_48, ++ }, { ++ .name = "sclk_mmc_48", ++ .id = 2, ++ .parent = &clk_48m, ++ .enable = s5pc1xx_sclk0_ctrl, ++ .ctrlbit = S5P_CLKGATE_SCLK0_MMC2_48, ++ }, ++ ++ /* Special Clocks 2 */ ++ { ++ .name = "sclk_tv_54", ++ .id = -1, ++ .parent = &clk_54m, ++ .enable = s5pc1xx_sclk1_ctrl, ++ .ctrlbit = S5P_CLKGATE_SCLK1_TV54, ++ }, { ++ .name = "sclk_vdac_54", ++ .id = -1, ++ .parent = &clk_54m, ++ .enable = s5pc1xx_sclk1_ctrl, ++ .ctrlbit = S5P_CLKGATE_SCLK1_VDAC54, ++ }, { ++ .name = "sclk_spdif", ++ .id = -1, ++ .parent = NULL, ++ .enable = s5pc1xx_sclk1_ctrl, ++ .ctrlbit = S5P_CLKGATE_SCLK1_SPDIF, ++ }, { ++ .name = "sclk_cam", ++ .id = 0, ++ .parent = &clk_dout_mpll2, ++ .enable = s5pc1xx_sclk1_ctrl, ++ .ctrlbit = S5P_CLKGATE_SCLK1_CAM, ++ .set_rate = s5pc1xx_setrate_sclk_cam, ++ }, ++}; ++ ++static struct clk *clks[] __initdata = { ++ &clk_ext, ++ &clk_epll, ++ &clk_27m, ++ &clk_48m, ++ &clk_54m, ++}; ++ ++void __init s5pc1xx_register_clocks(void) ++{ ++ struct clk *clkp; ++ int ret; ++ int ptr; ++ ++ s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); ++ ++ clkp = init_clocks; ++ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { ++ ret = s3c24xx_register_clock(clkp); ++ if (ret < 0) { ++ printk(KERN_ERR "Failed to register clock %s (%d)\n", ++ clkp->name, ret); ++ } ++ } ++ ++ clkp = init_clocks_disable; ++ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { ++ ++ ret = s3c24xx_register_clock(clkp); ++ if (ret < 0) { ++ printk(KERN_ERR "Failed to register clock %s (%d)\n", ++ clkp->name, ret); ++ } ++ ++ (clkp->enable)(clkp, 0); ++ } ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/cpu.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/cpu.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/cpu.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/cpu.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,125 @@ ++/* linux/arch/arm/plat-s5pc1xx/cpu.c ++ * ++ * Copyright 2008 Samsung Electonics Co. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5PC1XX CPU Support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++/* table of supported CPUs */ ++ ++static const char name_s5pc100[] = "S5PC100"; ++static const char name_s5pc100_pop[] = "S5PC100[POP]"; ++ ++static struct cpu_table cpu_ids[] __initdata = { ++ { ++ .idcode = 0x43100000, ++ .idmask = 0xfffffff0, ++ .map_io = s5pc100_map_io, ++ .init_clocks = s5pc100_init_clocks, ++ .init_uarts = s5pc100_init_uarts, ++ .init = s5pc100_init, ++ .name = name_s5pc100 ++ }, ++ { ++ .idcode = 0x43100200, ++ .idmask = 0xfffffff0, ++ .map_io = s5pc100_map_io, ++ .init_clocks = s5pc100_init_clocks, ++ .init_uarts = s5pc100_init_uarts, ++ .init = s5pc100_init, ++ .name = name_s5pc100_pop ++ }, ++ ++}; ++ ++/* minimal IO mapping */ ++ ++/* see notes on uart map in arch/arm/mach-s3c6400/include/mach/debug-macro.S */ ++#define UART_OFFS (S3C_PA_UART & 0xfffff) ++ ++static struct map_desc s3c_iodesc[] __initdata = { ++ { ++ .virtual = (unsigned long)S3C_VA_SYS, ++ .pfn = __phys_to_pfn(S5PC1XX_PA_SYSCON), ++ .length = SZ_4K, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = (unsigned long)(S3C_VA_UART + UART_OFFS), ++ .pfn = __phys_to_pfn(S3C_PA_UART), ++ .length = SZ_4K, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = (unsigned long)S3C_VA_VIC0, ++ .pfn = __phys_to_pfn(S5PC1XX_PA_VIC0), ++ .length = SZ_16K, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = (unsigned long)S3C_VA_VIC1, ++ .pfn = __phys_to_pfn(S5PC1XX_PA_VIC1), ++ .length = SZ_16K, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = (unsigned long)S3C_VA_VIC2, ++ .pfn = __phys_to_pfn(S5PC1XX_PA_VIC2), ++ .length = SZ_16K, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = (unsigned long)S3C_VA_TIMER, ++ .pfn = __phys_to_pfn(S3C_PA_TIMER), ++ .length = SZ_16K, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = (unsigned long)S5PC1XX_VA_GPIO, ++ .pfn = __phys_to_pfn(S5PC1XX_PA_GPIO), ++ .length = SZ_4K, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = (unsigned long)S5PC1XX_VA_CHIPID, ++ .pfn = __phys_to_pfn(S5PC1XX_PA_CHIPID), ++ .length = SZ_4K, ++ .type = MT_DEVICE, ++ }, ++}; ++ ++/* read cpu identification code */ ++ ++void __init s5pc1xx_init_io(struct map_desc *mach_desc, int size) ++{ ++ unsigned long idcode; ++ ++ /* initialise the io descriptors we need for initialisation */ ++ iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); ++ iotable_init(mach_desc, size); ++ ++ idcode = __raw_readl(S5PC1XX_VA_CHIPID); ++ s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/dev-csis.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/dev-csis.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/dev-csis.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/dev-csis.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,64 @@ ++/* linux/arch/arm/plat-s5pc1xx/dev-csis.c ++ * ++ * Copyright 2009 Samsung Electronics ++ * Jinsung Yang ++ * http://samsungsemi.com/ ++ * ++ * S5PC1XX series device definition for MIPI-CSI2 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++ ++static struct resource s3c_csis_resource[] = { ++ [0] = { ++ .start = S5PC1XX_PA_CSIS, ++ .end = S5PC1XX_PA_CSIS + S5PC1XX_SZ_CSIS - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_MIPICSI, ++ .end = IRQ_MIPICSI, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++struct platform_device s3c_device_csis = { ++ .name = "s3c-csis", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(s3c_csis_resource), ++ .resource = s3c_csis_resource, ++}; ++ ++static struct s3c_platform_csis default_csis_data __initdata = { ++ .clk_name = "mipi-csis", ++}; ++ ++void __init s3c_csis_set_platdata(struct s3c_platform_csis *pd) ++{ ++ struct s3c_platform_csis *npd; ++ ++ if (!pd) ++ pd = &default_csis_data; ++ ++ npd = kmemdup(pd, sizeof(struct s3c_platform_csis), GFP_KERNEL); ++ if (!npd) ++ printk(KERN_ERR "%s: no memory for platform data\n", __func__); ++ ++ npd->cfg_gpio = s3c_csis_cfg_gpio; ++ npd->cfg_phy_global = s3c_csis_cfg_phy_global; ++ ++ s3c_device_csis.dev.platform_data = npd; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/dev-fimc0.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/dev-fimc0.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/dev-fimc0.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/dev-fimc0.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,68 @@ ++/* linux/arch/arm/plat-s5pc1xx/dev-fimc0.c ++ * ++ * Copyright 2009 Samsung Electronics ++ * Jinsung Yang ++ * http://samsungsemi.com/ ++ * ++ * S5PC1XX series device definition for fimc device 0 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++ ++static struct resource s3c_fimc_resource[] = { ++ [0] = { ++ .start = S5PC1XX_PA_FIMC0, ++ .end = S5PC1XX_PA_FIMC0 + SZ_1M - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_FIMC0, ++ .end = IRQ_FIMC0, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++struct platform_device s3c_device_fimc0 = { ++ .name = "s3c-fimc", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(s3c_fimc_resource), ++ .resource = s3c_fimc_resource, ++}; ++ ++static struct s3c_platform_fimc default_fimc0_data __initdata = { ++ .srclk_name = "dout_mpll", ++ .clk_name = "sclk_fimc", ++ .clockrate = 133000000, ++ .line_length = 1280, ++ .nr_frames = 4, ++ .shared_io = 0, ++}; ++ ++void __init s3c_fimc0_set_platdata(struct s3c_platform_fimc *pd) ++{ ++ struct s3c_platform_fimc *npd; ++ ++ if (!pd) ++ pd = &default_fimc0_data; ++ ++ npd = kmemdup(pd, sizeof(struct s3c_platform_fimc), GFP_KERNEL); ++ if (!npd) ++ printk(KERN_ERR "%s: no memory for platform data\n", __func__); ++ else if (!npd->cfg_gpio) ++ npd->cfg_gpio = s3c_fimc0_cfg_gpio; ++ ++ s3c_device_fimc0.dev.platform_data = npd; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/dev-fimc1.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/dev-fimc1.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/dev-fimc1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/dev-fimc1.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,68 @@ ++/* linux/arch/arm/plat-s5pc1xx/dev-fimc1.c ++ * ++ * Copyright 2009 Samsung Electronics ++ * Jinsung Yang ++ * http://samsungsemi.com/ ++ * ++ * S5PC1XX series device definition for fimc device 1 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++ ++static struct resource s3c_fimc_resource[] = { ++ [0] = { ++ .start = S5PC1XX_PA_FIMC1, ++ .end = S5PC1XX_PA_FIMC1 + SZ_1M - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_FIMC1, ++ .end = IRQ_FIMC1, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++struct platform_device s3c_device_fimc1 = { ++ .name = "s3c-fimc", ++ .id = 1, ++ .num_resources = ARRAY_SIZE(s3c_fimc_resource), ++ .resource = s3c_fimc_resource, ++}; ++ ++static struct s3c_platform_fimc default_fimc1_data __initdata = { ++ .srclk_name = "dout_mpll", ++ .clk_name = "sclk_fimc", ++ .clockrate = 133000000, ++ .line_length = 1280, ++ .nr_frames = 4, ++ .shared_io = 0, ++}; ++ ++void __init s3c_fimc1_set_platdata(struct s3c_platform_fimc *pd) ++{ ++ struct s3c_platform_fimc *npd; ++ ++ if (!pd) ++ pd = &default_fimc1_data; ++ ++ npd = kmemdup(pd, sizeof(struct s3c_platform_fimc), GFP_KERNEL); ++ if (!npd) ++ printk(KERN_ERR "%s: no memory for platform data\n", __func__); ++ else if (!npd->cfg_gpio) ++ npd->cfg_gpio = s3c_fimc1_cfg_gpio; ++ ++ s3c_device_fimc1.dev.platform_data = npd; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/dev-fimc2.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/dev-fimc2.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/dev-fimc2.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/dev-fimc2.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,68 @@ ++/* linux/arch/arm/plat-s5pc1xx/dev-fimc2.c ++ * ++ * Copyright 2009 Samsung Electronics ++ * Jinsung Yang ++ * http://samsungsemi.com/ ++ * ++ * S5PC1XX series device definition for fimc device 2 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++ ++static struct resource s3c_fimc_resource[] = { ++ [0] = { ++ .start = S5PC1XX_PA_FIMC2, ++ .end = S5PC1XX_PA_FIMC2 + SZ_1M - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_FIMC2, ++ .end = IRQ_FIMC2, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++struct platform_device s3c_device_fimc2 = { ++ .name = "s3c-fimc", ++ .id = 2, ++ .num_resources = ARRAY_SIZE(s3c_fimc_resource), ++ .resource = s3c_fimc_resource, ++}; ++ ++static struct s3c_platform_fimc default_fimc2_data __initdata = { ++ .srclk_name = "dout_mpll", ++ .clk_name = "sclk_fimc", ++ .clockrate = 133000000, ++ .line_length = 1280, ++ .nr_frames = 4, ++ .shared_io = 0, ++}; ++ ++void __init s3c_fimc2_set_platdata(struct s3c_platform_fimc *pd) ++{ ++ struct s3c_platform_fimc *npd; ++ ++ if (!pd) ++ pd = &default_fimc2_data; ++ ++ npd = kmemdup(pd, sizeof(struct s3c_platform_fimc), GFP_KERNEL); ++ if (!npd) ++ printk(KERN_ERR "%s: no memory for platform data\n", __func__); ++ else if (!npd->cfg_gpio) ++ npd->cfg_gpio = s3c_fimc2_cfg_gpio; ++ ++ s3c_device_fimc2.dev.platform_data = npd; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/dev-fimd.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/dev-fimd.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/dev-fimd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/dev-fimd.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,68 @@ ++/* linux/arch/arm/plat-s5pc1xx/dev-fimd.c ++ * ++ * Copyright 2009 Samsung Electronics ++ * Jinsung Yang ++ * http://samsungsemi.com/ ++ * ++ * S5PC1XX series device definition for FIMD ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++ ++static struct resource s3c_fimd_resource[] = { ++ [0] = { ++ .start = S5PC1XX_PA_LCD, ++ .end = S5PC1XX_PA_LCD + S5PC1XX_SZ_LCD - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_LCD0, ++ .end = IRQ_LCD3, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++struct platform_device s3c_device_fimd = { ++ .name = "s3c-fimd", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_fimd_resource), ++ .resource = s3c_fimd_resource, ++}; ++ ++static struct s3c_platform_fimd default_fimd_data __initdata = { ++ .hw_ver = 0x50, ++ .clk_name = "lcd", ++ .clockrate = 66000000, ++ .max_wins = 5, ++ .max_buffers = 2, ++}; ++ ++void __init s3c_fimd_set_platdata(struct s3c_platform_fimd *pd) ++{ ++ struct s3c_platform_fimd *npd; ++ ++ if (!pd) ++ pd = &default_fimd_data; ++ ++ npd = kmemdup(pd, sizeof(struct s3c_platform_fimd), GFP_KERNEL); ++ if (!npd) ++ printk(KERN_ERR "%s: no memory for platform data\n", __func__); ++ ++ npd->cfg_gpio = s3c_fimd_cfg_gpio; ++ npd->backlight_on = s3c_fimd_backlight_on; ++ npd->reset_lcd = s3c_fimd_reset_lcd; ++ ++ s3c_device_fimd.dev.platform_data = npd; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/dev-uart.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/dev-uart.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/dev-uart.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/dev-uart.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,176 @@ ++/* linux/arch/arm/plat-s5pc1xx/dev-uart.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * Base S5PC1XX UART resource and device definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++/* Serial port registrations */ ++ ++/* 64xx uarts are closer together */ ++ ++static struct resource s5pc1xx_uart0_resource[] = { ++ [0] = { ++ .start = S3C_PA_UART0, ++ .end = S3C_PA_UART0 + 0x100, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_S3CUART_RX0, ++ .end = IRQ_S3CUART_RX0, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = IRQ_S3CUART_TX0, ++ .end = IRQ_S3CUART_TX0, ++ .flags = IORESOURCE_IRQ, ++ ++ }, ++ [3] = { ++ .start = IRQ_S3CUART_ERR0, ++ .end = IRQ_S3CUART_ERR0, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct resource s5pc1xx_uart1_resource[] = { ++ [0] = { ++ .start = S3C_PA_UART1, ++ .end = S3C_PA_UART1 + 0x100, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_S3CUART_RX1, ++ .end = IRQ_S3CUART_RX1, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = IRQ_S3CUART_TX1, ++ .end = IRQ_S3CUART_TX1, ++ .flags = IORESOURCE_IRQ, ++ ++ }, ++ [3] = { ++ .start = IRQ_S3CUART_ERR1, ++ .end = IRQ_S3CUART_ERR1, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct resource s5pc1xx_uart2_resource[] = { ++ [0] = { ++ .start = S3C_PA_UART2, ++ .end = S3C_PA_UART2 + 0x100, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_S3CUART_RX2, ++ .end = IRQ_S3CUART_RX2, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = IRQ_S3CUART_TX2, ++ .end = IRQ_S3CUART_TX2, ++ .flags = IORESOURCE_IRQ, ++ ++ }, ++ [3] = { ++ .start = IRQ_S3CUART_ERR2, ++ .end = IRQ_S3CUART_ERR2, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct resource s5pc1xx_uart3_resource[] = { ++ [0] = { ++ .start = S3C_PA_UART3, ++ .end = S3C_PA_UART3 + 0x100, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_S3CUART_RX3, ++ .end = IRQ_S3CUART_RX3, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = IRQ_S3CUART_TX3, ++ .end = IRQ_S3CUART_TX3, ++ .flags = IORESOURCE_IRQ, ++ ++ }, ++ [3] = { ++ .start = IRQ_S3CUART_ERR3, ++ .end = IRQ_S3CUART_ERR3, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++ ++struct s3c24xx_uart_resources s5pc1xx_uart_resources[] __initdata = { ++ [0] = { ++ .resources = s5pc1xx_uart0_resource, ++ .nr_resources = ARRAY_SIZE(s5pc1xx_uart0_resource), ++ }, ++ [1] = { ++ .resources = s5pc1xx_uart1_resource, ++ .nr_resources = ARRAY_SIZE(s5pc1xx_uart1_resource), ++ }, ++ [2] = { ++ .resources = s5pc1xx_uart2_resource, ++ .nr_resources = ARRAY_SIZE(s5pc1xx_uart2_resource), ++ }, ++ [3] = { ++ .resources = s5pc1xx_uart3_resource, ++ .nr_resources = ARRAY_SIZE(s5pc1xx_uart3_resource), ++ }, ++}; ++ ++/* uart devices */ ++ ++static struct platform_device s3c24xx_uart_device0 = { ++ .id = 0, ++}; ++ ++static struct platform_device s3c24xx_uart_device1 = { ++ .id = 1, ++}; ++ ++static struct platform_device s3c24xx_uart_device2 = { ++ .id = 2, ++}; ++ ++static struct platform_device s3c24xx_uart_device3 = { ++ .id = 3, ++}; ++ ++struct platform_device *s3c24xx_uart_src[4] = { ++ &s3c24xx_uart_device0, ++ &s3c24xx_uart_device1, ++ &s3c24xx_uart_device2, ++ &s3c24xx_uart_device3, ++}; ++ ++struct platform_device *s3c24xx_uart_devs[4] = { ++}; ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/devs.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/devs.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/devs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/devs.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,548 @@ ++/* linux/arch/arm/plat-s5pc1xx/devs.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * Base S5PC1XX resource and device definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++ ++/* SMC9115 LAN via ROM interface */ ++ ++static struct resource s3c_smc911x_resources[] = { ++ [0] = { ++ .start = S5PC1XX_PA_SMC9115, ++ .end = S5PC1XX_PA_SMC9115 + 0x1fffffff, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_EINT10, ++ .end = IRQ_EINT10, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++struct platform_device s3c_device_smc911x = { ++ .name = "smc911x", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_smc911x_resources), ++ .resource = s3c_smc911x_resources, ++}; ++ ++/* FIMV MFC interface */ ++static struct resource s3c_mfc_resources[] = { ++ [0] = { ++ .start = S5PC1XX_PA_MFC, ++ .end = S5PC1XX_PA_MFC + S5PC1XX_SZ_MFC - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_MFC, ++ .end = IRQ_MFC, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++struct platform_device s3c_device_mfc = { ++ .name = "s3c-mfc", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_mfc_resources), ++ .resource = s3c_mfc_resources, ++}; ++ ++/* LCD Controller */ ++ ++static struct resource s3c_lcd_resource[] = { ++ [0] = { ++ .start = S5PC1XX_PA_LCD, ++ .end = S5PC1XX_PA_LCD + SZ_1M - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_LCD1, ++ .end = IRQ_LCD3, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static u64 s3c_device_lcd_dmamask = 0xffffffffUL; ++ ++struct platform_device s3c_device_lcd = { ++ .name = "s3c-lcd", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_lcd_resource), ++ .resource = s3c_lcd_resource, ++ .dev = { ++ .dma_mask = &s3c_device_lcd_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ ++/* FIMG-2D controller */ ++static struct resource s3c_g2d_resource[] = { ++ [0] = { ++ .start = S5PC1XX_PA_G2D, ++ .end = S5PC1XX_PA_G2D + S5PC1XX_SZ_G2D - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_2D, ++ .end = IRQ_2D, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++struct platform_device s3c_device_g2d = { ++ .name = "s3c-g2d", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_g2d_resource), ++ .resource = s3c_g2d_resource ++}; ++EXPORT_SYMBOL(s3c_device_g2d); ++ ++/* ADC */ ++static struct resource s3c_adc_resource[] = { ++ [0] = { ++ .start = S3C_PA_ADC, ++ .end = S3C_PA_ADC + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_PENDN, ++ .end = IRQ_PENDN, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = IRQ_ADC, ++ .end = IRQ_ADC, ++ .flags = IORESOURCE_IRQ, ++ } ++ ++}; ++ ++struct platform_device s3c_device_adc = { ++ .name = "s3c-adc", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_adc_resource), ++ .resource = s3c_adc_resource, ++}; ++ ++void __init s3c_adc_set_platdata(struct s3c_adc_mach_info *pd) ++{ ++ struct s3c_adc_mach_info *npd; ++ ++ npd = kmalloc(sizeof(*npd), GFP_KERNEL); ++ if (npd) { ++ memcpy(npd, pd, sizeof(*npd)); ++ s3c_device_adc.dev.platform_data = npd; ++ } else { ++ printk(KERN_ERR "no memory for ADC platform data\n"); ++ } ++} ++ ++/* WATCHDOG TIMER*/ ++ ++static struct resource s3c_wdt_resource[] = { ++ [0] = { ++ .start = S3C_PA_WDT, ++ .end = S3C_PA_WDT + 0xff, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_WDT, ++ .end = IRQ_WDT, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++struct platform_device s3c_device_wdt = { ++ .name = "s3c2410-wdt", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_wdt_resource), ++ .resource = s3c_wdt_resource, ++}; ++ ++EXPORT_SYMBOL(s3c_device_wdt); ++ ++ ++/* NAND Controller */ ++ ++static struct resource s3c_nand_resource[] = { ++ [0] = { ++ .start = S5PC1XX_PA_NAND, ++ .end = S5PC1XX_PA_NAND + S5PC1XX_SZ_NAND - 1, ++ .flags = IORESOURCE_MEM, ++ } ++}; ++ ++struct platform_device s3c_device_nand = { ++ .name = "s3c-nand", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_nand_resource), ++ .resource = s3c_nand_resource, ++}; ++ ++EXPORT_SYMBOL(s3c_device_nand); ++ ++/* USB Host Controller */ ++ ++static struct resource s3c_usb_resource[] = { ++ [0] = { ++ .start = S5PC1XX_PA_USBHOST, ++ .end = S5PC1XX_PA_USBHOST + S5PC1XX_SZ_USBHOST - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_UHOST, ++ .end = IRQ_UHOST, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static u64 s3c_device_usb_dmamask = 0xffffffffUL; ++ ++struct platform_device s3c_device_usb = { ++ .name = "s3c2410-ohci", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_usb_resource), ++ .resource = s3c_usb_resource, ++ .dev = { ++ .dma_mask = &s3c_device_usb_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ ++EXPORT_SYMBOL(s3c_device_usb); ++ ++/* USB Device (Gadget)*/ ++ ++static struct resource s3c_usbgadget_resource[] = { ++ [0] = { ++ .start = S5PC1XX_PA_OTG, ++ .end = S5PC1XX_PA_OTG+S5PC1XX_SZ_OTG-1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_OTG, ++ .end = IRQ_OTG, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++struct platform_device s3c_device_usbgadget = { ++ .name = "s3c-usbgadget", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_usbgadget_resource), ++ .resource = s3c_usbgadget_resource, ++}; ++ ++EXPORT_SYMBOL(s3c_device_usbgadget); ++ ++/* USB Device (OTG hcd)*/ ++ ++static struct resource s3c_usb_otghcd_resource[] = { ++ [0] = { ++ .start = S3C_PA_OTG, ++ .end = S3C_PA_OTG + S3C_SZ_OTG - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_OTG, ++ .end = IRQ_OTG, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static u64 s3c_device_usb_otghcd_dmamask = 0xffffffffUL; ++ ++struct platform_device s3c_device_usb_otghcd = { ++ .name = "s3c_otghcd", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_usb_otghcd_resource), ++ .resource = s3c_usb_otghcd_resource, ++ .dev = { ++ .dma_mask = &s3c_device_usb_otghcd_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ ++EXPORT_SYMBOL(s3c_device_usb_otghcd); ++ ++/* RTC */ ++ ++static struct resource s3c_rtc_resource[] = { ++ [0] = { ++ .start = S3C_PA_RTC, ++ .end = S3C_PA_RTC + 0xff, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_RTC_ALARM, ++ .end = IRQ_RTC_ALARM, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = IRQ_RTC_TIC, ++ .end = IRQ_RTC_TIC, ++ .flags = IORESOURCE_IRQ ++ } ++}; ++ ++struct platform_device s3c_device_rtc = { ++ .name = "s3c2410-rtc", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_rtc_resource), ++ .resource = s3c_rtc_resource, ++}; ++ ++/* OneNAND Controller */ ++static struct resource s3c_onenand_resource[] = { ++ [0] = { ++ .start = S5PC1XX_PA_ONENAND, ++ .end = S5PC1XX_PA_ONENAND + S5PC1XX_SZ_ONENAND - 1, ++ .flags = IORESOURCE_MEM, ++ } ++}; ++ ++struct platform_device s3c_device_onenand = { ++ .name = "onenand", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_onenand_resource), ++ .resource = s3c_onenand_resource, ++}; ++ ++EXPORT_SYMBOL(s3c_device_onenand); ++ ++/* Keypad interface */ ++static struct resource s3c_keypad_resource[] = { ++ [0] = { ++ .start = S3C_PA_KEYPAD, ++ .end = S3C_PA_KEYPAD+ S3C_SZ_KEYPAD - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_KEYPAD, ++ .end = IRQ_KEYPAD, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++struct platform_device s3c_device_keypad = { ++ .name = "s3c-keypad", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_keypad_resource), ++ .resource = s3c_keypad_resource, ++}; ++ ++EXPORT_SYMBOL(s3c_device_keypad); ++ ++/* SPI (0) */ ++ ++static struct resource s3c_spi0_resource[] = { ++ [0] = { ++ .start = S5PC1XX_PA_SPI0, ++ .end = S5PC1XX_PA_SPI0 + S5PC1XX_SZ_SPI - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_SPI0, ++ .end = IRQ_SPI0, ++ .flags = IORESOURCE_IRQ, ++ } ++ ++}; ++ ++static u64 s3c_device_spi0_dmamask = 0xffffffffUL; ++ ++struct platform_device s3c_device_spi0 = { ++ .name = "s3c2410-spi", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(s3c_spi0_resource), ++ .resource = s3c_spi0_resource, ++ .dev = { ++ .dma_mask = &s3c_device_spi0_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ ++EXPORT_SYMBOL(s3c_device_spi0); ++ ++/* SPI (1) */ ++ ++static struct resource s3c_spi1_resource[] = { ++ [0] = { ++ .start = S5PC1XX_PA_SPI1, ++ .end = S5PC1XX_PA_SPI1 + S5PC1XX_SZ_SPI - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_SPI1, ++ .end = IRQ_SPI1, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static u64 s3c_device_spi1_dmamask = 0xffffffffUL; ++ ++struct platform_device s3c_device_spi1 = { ++ .name = "s3c2410-spi", ++ .id = 1, ++ .num_resources = ARRAY_SIZE(s3c_spi1_resource), ++ .resource = s3c_spi1_resource, ++ .dev = { ++ .dma_mask = &s3c_device_spi1_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ ++EXPORT_SYMBOL(s3c_device_spi1); ++ ++/* SPI (2) */ ++ ++static struct resource s3c_spi2_resource[] = { ++ [0] = { ++ .start = S5PC1XX_PA_SPI2, ++ .end = S5PC1XX_PA_SPI2 + S5PC1XX_SZ_SPI - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_SPI2, ++ .end = IRQ_SPI2, ++ .flags = IORESOURCE_IRQ, ++ } ++ ++}; ++ ++static u64 s3c_device_spi2_dmamask = 0xffffffffUL; ++ ++struct platform_device s3c_device_spi2 = { ++ .name = "s3c2410-spi", ++ .id = 2, ++ .num_resources = ARRAY_SIZE(s3c_spi2_resource), ++ .resource = s3c_spi2_resource, ++ .dev = { ++ .dma_mask = &s3c_device_spi2_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ ++EXPORT_SYMBOL(s3c_device_spi2); ++ ++/* AC97 */ ++ ++static struct resource s3c_ac97_resource[] = { ++ [0] = { ++ .start = S5PC1XX_PA_AC97, ++ .end = S5PC1XX_PA_AC97 + S5PC1XX_SZ_AC97 -1, ++ .flags = IORESOURCE_MEM, ++ } ++}; ++ ++static u64 s3c_device_ac97_dmamask = 0xffffffffUL; ++ ++struct platform_device s3c_device_ac97 = { ++ .name = "s3c-ac97", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_ac97_resource), ++ .resource = s3c_ac97_resource, ++ .dev = { ++ .dma_mask = &s3c_device_ac97_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ ++EXPORT_SYMBOL(s3c_device_ac97); ++ ++static struct resource s3c_g3d_resource[] = { ++ [0] = { ++ .start = S5PC1XX_PA_G3D, ++ .end = S5PC1XX_PA_G3D + S5PC1XX_SZ_G3D - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_3D, ++ .end = IRQ_3D, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static u64 s3c_device_g3d_dmamask = 0xffffffffUL; ++ ++struct platform_device s3c_device_g3d = { ++ .name = "s3c-g3d", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_g3d_resource), ++ .resource = s3c_g3d_resource, ++ .dev = { ++ .dma_mask = &s3c_device_g3d_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ ++EXPORT_SYMBOL(s3c_device_g3d); ++ ++/* JPEG controller */ ++static struct resource s3c_jpeg_resource[] = { ++ [0] = { ++ .start = S5PC1XX_PA_JPEG, ++ .end = S5PC1XX_PA_JPEG + S5PC1XX_SZ_JPEG - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_JPEG, ++ .end = IRQ_JPEG, ++ .flags = IORESOURCE_IRQ, ++ } ++ ++}; ++ ++struct platform_device s3c_device_jpeg = { ++ .name = "s3c-jpg", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_jpeg_resource), ++ .resource = s3c_jpeg_resource, ++}; ++EXPORT_SYMBOL(s3c_device_jpeg); ++ ++/* rotator interface */ ++static struct resource s3c_rotator_resource[] = { ++ [0] = { ++ .start = S5PC1XX_PA_ROTATOR, ++ .end = S5PC1XX_PA_ROTATOR + S5PC1XX_SZ_ROTATOR - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_ROTATOR, ++ .end = IRQ_ROTATOR, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++struct platform_device s3c_device_rotator = { ++ .name = "s3c-rotator", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(s3c_rotator_resource), ++ .resource = s3c_rotator_resource ++}; ++EXPORT_SYMBOL(s3c_device_rotator); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/gpiolib.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/gpiolib.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/gpiolib.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/gpiolib.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,409 @@ ++/* arch/arm/plat-s5pc1xx/gpiolib.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5PC1XX - GPIOlib support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#define OFF_GPCON (0x00) ++#define OFF_GPDAT (0x04) ++ ++#define con_4bit_shift(__off) ((__off) * 4) ++ ++#if 1 ++#define gpio_dbg(x...) do { } while(0) ++#else ++#define gpio_dbg(x...) printk(KERN_DEBUG ## x) ++#endif ++ ++/* The s5pc1xx_gpiolib routines are to control the gpio banks where ++ * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the ++ * following example: ++ * ++ * base + 0x00: Control register, 4 bits per gpio ++ * gpio n: 4 bits starting at (4*n) ++ * 0000 = input, 0001 = output, others mean special-function ++ * base + 0x04: Data register, 1 bit per gpio ++ * bit n: data bit n ++ * ++ * Note, since the data register is one bit per gpio and is at base + 0x4 ++ * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of ++ * the output. ++*/ ++ ++static int s5pc1xx_gpiolib_input(struct gpio_chip *chip, unsigned offset) ++{ ++ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); ++ void __iomem *base = ourchip->base; ++ unsigned long con; ++ ++ con = __raw_readl(base + OFF_GPCON); ++ con &= ~(0xf << con_4bit_shift(offset)); ++ __raw_writel(con, base + OFF_GPCON); ++ ++ gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con); ++ ++ return 0; ++} ++ ++static int s5pc1xx_gpiolib_output(struct gpio_chip *chip, ++ unsigned offset, int value) ++{ ++ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); ++ void __iomem *base = ourchip->base; ++ unsigned long con; ++ unsigned long dat; ++ ++ con = __raw_readl(base + OFF_GPCON); ++ con &= ~(0xf << con_4bit_shift(offset)); ++ con |= 0x1 << con_4bit_shift(offset); ++ ++ dat = __raw_readl(base + OFF_GPDAT); ++ if (value) ++ dat |= 1 << offset; ++ else ++ dat &= ~(1 << offset); ++ ++ __raw_writel(dat, base + OFF_GPDAT); ++ __raw_writel(con, base + OFF_GPCON); ++ __raw_writel(dat, base + OFF_GPDAT); ++ ++ gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); ++ ++ return 0; ++} ++ ++static struct s3c_gpio_cfg gpio_cfg = { ++ .cfg_eint = 0xf, ++ .set_config = s3c_gpio_setcfg_s5pc1xx, ++ .set_pull = s3c_gpio_setpull_updown, ++ .get_pull = s3c_gpio_getpull_updown, ++}; ++ ++static struct s3c_gpio_cfg gpio_cfg_noint = { ++ .set_config = s3c_gpio_setcfg_s5pc1xx, ++ .set_pull = s3c_gpio_setpull_updown, ++ .get_pull = s3c_gpio_getpull_updown, ++}; ++ ++static struct s3c_gpio_chip gpio_chips[] = { ++ { ++ .base = S5PC1XX_GPA0_BASE, ++ .config = &gpio_cfg, ++ .chip = { ++ .base = S5PC1XX_GPA0(0), ++ .ngpio = S5PC1XX_GPIO_A0_NR, ++ .label = "GPA0", ++ }, ++ }, { ++ .base = S5PC1XX_GPA1_BASE, ++ .config = &gpio_cfg, ++ .chip = { ++ .base = S5PC1XX_GPA1(0), ++ .ngpio = S5PC1XX_GPIO_A1_NR, ++ .label = "GPA1", ++ }, ++ }, { ++ .base = S5PC1XX_GPB_BASE, ++ .config = &gpio_cfg, ++ .chip = { ++ .base = S5PC1XX_GPB(0), ++ .ngpio = S5PC1XX_GPIO_B_NR, ++ .label = "GPB", ++ }, ++ }, { ++ .base = S5PC1XX_GPC_BASE, ++ .config = &gpio_cfg, ++ .chip = { ++ .base = S5PC1XX_GPC(0), ++ .ngpio = S5PC1XX_GPIO_C_NR, ++ .label = "GPC", ++ }, ++ }, { ++ .base = S5PC1XX_GPD_BASE, ++ .config = &gpio_cfg, ++ .chip = { ++ .base = S5PC1XX_GPD(0), ++ .ngpio = S5PC1XX_GPIO_D_NR, ++ .label = "GPD", ++ }, ++ }, { ++ .base = S5PC1XX_GPE0_BASE, ++ .config = &gpio_cfg, ++ .chip = { ++ .base = S5PC1XX_GPE0(0), ++ .ngpio = S5PC1XX_GPIO_E0_NR, ++ .label = "GPE0", ++ }, ++ }, { ++ .base = S5PC1XX_GPE1_BASE, ++ .config = &gpio_cfg, ++ .chip = { ++ .base = S5PC1XX_GPE1(0), ++ .ngpio = S5PC1XX_GPIO_E1_NR, ++ .label = "GPE1", ++ }, ++ }, { ++ .base = S5PC1XX_GPF0_BASE, ++ .config = &gpio_cfg, ++ .chip = { ++ .base = S5PC1XX_GPF0(0), ++ .ngpio = S5PC1XX_GPIO_F0_NR, ++ .label = "GPF0", ++ }, ++ }, { ++ .base = S5PC1XX_GPF1_BASE, ++ .config = &gpio_cfg, ++ .chip = { ++ .base = S5PC1XX_GPF1(0), ++ .ngpio = S5PC1XX_GPIO_F1_NR, ++ .label = "GPF1", ++ }, ++ }, { ++ .base = S5PC1XX_GPF2_BASE, ++ .config = &gpio_cfg, ++ .chip = { ++ .base = S5PC1XX_GPF2(0), ++ .ngpio = S5PC1XX_GPIO_F2_NR, ++ .label = "GPF2", ++ }, ++ }, { ++ .base = S5PC1XX_GPF3_BASE, ++ .config = &gpio_cfg, ++ .chip = { ++ .base = S5PC1XX_GPF3(0), ++ .ngpio = S5PC1XX_GPIO_F3_NR, ++ .label = "GPF3", ++ }, ++ }, { ++ .base = S5PC1XX_GPG0_BASE, ++ .config = &gpio_cfg, ++ .chip = { ++ .base = S5PC1XX_GPG0(0), ++ .ngpio = S5PC1XX_GPIO_G0_NR, ++ .label = "GPG0", ++ }, ++ }, { ++ .base = S5PC1XX_GPG1_BASE, ++ .config = &gpio_cfg, ++ .chip = { ++ .base = S5PC1XX_GPG1(0), ++ .ngpio = S5PC1XX_GPIO_G1_NR, ++ .label = "GPG1", ++ }, ++ }, { ++ .base = S5PC1XX_GPG2_BASE, ++ .config = &gpio_cfg, ++ .chip = { ++ .base = S5PC1XX_GPG2(0), ++ .ngpio = S5PC1XX_GPIO_G2_NR, ++ .label = "GPG2", ++ }, ++ }, { ++ .base = S5PC1XX_GPG3_BASE, ++ .config = &gpio_cfg, ++ .chip = { ++ .base = S5PC1XX_GPG3(0), ++ .ngpio = S5PC1XX_GPIO_G3_NR, ++ .label = "GPG3", ++ }, ++ }, { ++ .base = S5PC1XX_GPH0_BASE, ++ .config = &gpio_cfg_noint, ++ .chip = { ++ .base = S5PC1XX_GPH0(0), ++ .ngpio = S5PC1XX_GPIO_H0_NR, ++ .label = "GPH0", ++ }, ++ }, { ++ .base = S5PC1XX_GPH1_BASE, ++ .config = &gpio_cfg_noint, ++ .chip = { ++ .base = S5PC1XX_GPH1(0), ++ .ngpio = S5PC1XX_GPIO_H1_NR, ++ .label = "GPH1", ++ }, ++ }, { ++ .base = S5PC1XX_GPH2_BASE, ++ .config = &gpio_cfg_noint, ++ .chip = { ++ .base = S5PC1XX_GPH2(0), ++ .ngpio = S5PC1XX_GPIO_H2_NR, ++ .label = "GPH2", ++ }, ++ }, { ++ .base = S5PC1XX_GPH3_BASE, ++ .config = &gpio_cfg_noint, ++ .chip = { ++ .base = S5PC1XX_GPH3(0), ++ .ngpio = S5PC1XX_GPIO_H3_NR, ++ .label = "GPH3", ++ }, ++ }, { ++ .base = S5PC1XX_GPI_BASE, ++ .config = &gpio_cfg, ++ .chip = { ++ .base = S5PC1XX_GPI(0), ++ .ngpio = S5PC1XX_GPIO_I_NR, ++ .label = "GPI", ++ }, ++ }, { ++ .base = S5PC1XX_GPJ0_BASE, ++ .config = &gpio_cfg, ++ .chip = { ++ .base = S5PC1XX_GPJ0(0), ++ .ngpio = S5PC1XX_GPIO_J0_NR, ++ .label = "GPJ0", ++ }, ++ }, { ++ .base = S5PC1XX_GPJ1_BASE, ++ .config = &gpio_cfg, ++ .chip = { ++ .base = S5PC1XX_GPJ1(0), ++ .ngpio = S5PC1XX_GPIO_J1_NR, ++ .label = "GPJ1", ++ }, ++ }, { ++ .base = S5PC1XX_GPJ2_BASE, ++ .config = &gpio_cfg, ++ .chip = { ++ .base = S5PC1XX_GPJ2(0), ++ .ngpio = S5PC1XX_GPIO_J2_NR, ++ .label = "GPJ2", ++ }, ++ }, { ++ .base = S5PC1XX_GPJ3_BASE, ++ .config = &gpio_cfg, ++ .chip = { ++ .base = S5PC1XX_GPJ3(0), ++ .ngpio = S5PC1XX_GPIO_J3_NR, ++ .label = "GPJ3", ++ }, ++ }, { ++ .base = S5PC1XX_GPJ4_BASE, ++ .config = &gpio_cfg, ++ .chip = { ++ .base = S5PC1XX_GPJ4(0), ++ .ngpio = S5PC1XX_GPIO_J4_NR, ++ .label = "GPJ4", ++ }, ++ }, { ++ .base = S5PC1XX_GPK0_BASE, ++ .config = &gpio_cfg_noint, ++ .chip = { ++ .base = S5PC1XX_GPK0(0), ++ .ngpio = S5PC1XX_GPIO_K0_NR, ++ .label = "GPK0", ++ }, ++ }, { ++ .base = S5PC1XX_GPK1_BASE, ++ .config = &gpio_cfg_noint, ++ .chip = { ++ .base = S5PC1XX_GPK1(0), ++ .ngpio = S5PC1XX_GPIO_K1_NR, ++ .label = "GPK1", ++ }, ++ }, { ++ .base = S5PC1XX_GPK2_BASE, ++ .config = &gpio_cfg_noint, ++ .chip = { ++ .base = S5PC1XX_GPK2(0), ++ .ngpio = S5PC1XX_GPIO_K2_NR, ++ .label = "GPK2", ++ }, ++ }, { ++ .base = S5PC1XX_GPK3_BASE, ++ .config = &gpio_cfg_noint, ++ .chip = { ++ .base = S5PC1XX_GPK3(0), ++ .ngpio = S5PC1XX_GPIO_K3_NR, ++ .label = "GPK3", ++ }, ++ }, { ++ .base = S5PC1XX_MP00_BASE, ++ .config = &gpio_cfg_noint, ++ .chip = { ++ .base = S5PC1XX_MP00(0), ++ .ngpio = S5PC1XX_GPIO_MP00_NR, ++ .label = "MP00", ++ }, ++ }, { ++ .base = S5PC1XX_MP01_BASE, ++ .config = &gpio_cfg_noint, ++ .chip = { ++ .base = S5PC1XX_MP01(0), ++ .ngpio = S5PC1XX_GPIO_MP01_NR, ++ .label = "MP01", ++ }, ++ }, { ++ .base = S5PC1XX_MP02_BASE, ++ .config = &gpio_cfg_noint, ++ .chip = { ++ .base = S5PC1XX_MP02(0), ++ .ngpio = S5PC1XX_GPIO_MP02_NR, ++ .label = "MP02", ++ }, ++ }, { ++ .base = S5PC1XX_MP03_BASE, ++ .config = &gpio_cfg_noint, ++ .chip = { ++ .base = S5PC1XX_MP03(0), ++ .ngpio = S5PC1XX_GPIO_MP03_NR, ++ .label = "MP03", ++ }, ++ }, { ++ .base = S5PC1XX_MP04_BASE, ++ .config = &gpio_cfg_noint, ++ .chip = { ++ .base = S5PC1XX_MP04(0), ++ .ngpio = S5PC1XX_GPIO_MP04_NR, ++ .label = "MP04", ++ }, ++ }, ++}; ++ ++static __init void s5pc1xx_gpiolib_link(struct s3c_gpio_chip *chip) ++{ ++ chip->chip.direction_input = s5pc1xx_gpiolib_input; ++ chip->chip.direction_output = s5pc1xx_gpiolib_output; ++} ++ ++static __init void s5pc1xx_gpiolib_add(struct s3c_gpio_chip *chips, ++ int nr_chips, ++ void (*fn)(struct s3c_gpio_chip *)) ++{ ++ for (; nr_chips > 0; nr_chips--, chips++) { ++ if (fn) ++ (fn)(chips); ++ s3c_gpiolib_add(chips); ++ } ++} ++ ++static __init int s5pc1xx_gpiolib_init(void) ++{ ++ s5pc1xx_gpiolib_add(gpio_chips, ARRAY_SIZE(gpio_chips), ++ s5pc1xx_gpiolib_link); ++ ++ return 0; ++} ++ ++arch_initcall(s5pc1xx_gpiolib_init); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/csis.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/csis.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/csis.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/csis.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,30 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/csis.h ++ * ++ * Platform header file for MIPI-CSI2 driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _CSIS_H ++#define _CSIS_H ++ ++struct platform_device; ++ ++struct s3c_platform_csis { ++ const char clk_name[16]; ++ ++ void (*cfg_gpio)(struct platform_device *dev); ++ void (*cfg_phy_global)(struct platform_device *dev, int on); ++}; ++ ++extern void s3c_csis_set_platdata(struct s3c_platform_csis *csis); ++extern void s3c_csis_cfg_gpio(struct platform_device *dev); ++extern void s3c_csis_cfg_phy_global(struct platform_device *dev, int on); ++ ++#endif /* _CSIS_H */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/dma.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/dma.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/dma.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/dma.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,13 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/dma.h ++ * ++ * Copyright (C) 2006 Simtec Electronics ++ * Ben Dooks ++ * ++ * Samsung S5PC1XX DMA support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++#include ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/fimc.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/fimc.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/fimc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/fimc.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,41 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/fimc.h ++ * ++ * Platform header file for Samsung Camera Interface (FIMC) driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _FIMC_H ++#define _FIMC_H ++ ++struct platform_device; ++ ++struct s3c_platform_fimc { ++ const char srclk_name[16]; ++ const char clk_name[16]; ++ u32 clockrate; ++ int line_length; ++ int nr_frames; ++ int shared_io; ++ ++ void (*cfg_gpio)(struct platform_device *dev); ++}; ++ ++extern void s3c_fimc0_set_platdata(struct s3c_platform_fimc *fimc); ++extern void s3c_fimc1_set_platdata(struct s3c_platform_fimc *fimc); ++extern void s3c_fimc2_set_platdata(struct s3c_platform_fimc *fimc); ++ ++/* defined by architecture to configure gpio */ ++extern void s3c_fimc0_cfg_gpio(struct platform_device *dev); ++extern void s3c_fimc1_cfg_gpio(struct platform_device *dev); ++extern void s3c_fimc2_cfg_gpio(struct platform_device *dev); ++ ++extern void s3c_fimc_reset_camera(void); ++ ++#endif /* _FIMC_H */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/fimd.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/fimd.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/fimd.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/fimd.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,38 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/fimd.h ++ * ++ * Platform header file for Samsung Display Controller (FIMD) driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _FIMD_H ++#define _FIMD_H ++ ++struct platform_device; ++ ++struct s3c_platform_fimd { ++ int hw_ver; ++ const char clk_name[16]; ++ u32 clockrate; ++ int max_wins; ++ int max_buffers; ++ ++ void (*cfg_gpio)(struct platform_device *dev); ++ int (*backlight_on)(struct platform_device *dev); ++ int (*reset_lcd)(struct platform_device *dev); ++}; ++ ++extern void s3c_fimd_set_platdata(struct s3c_platform_fimd *fimd); ++ ++/* defined by architecture to configure gpio */ ++extern void s3c_fimd_cfg_gpio(struct platform_device *dev); ++extern int s3c_fimd_backlight_on(struct platform_device *dev); ++extern int s3c_fimd_reset_lcd(struct platform_device *dev); ++ ++#endif /* _FIMD_H */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-a0.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-a0.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-a0.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-a0.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,49 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-a0.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank A0 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPA0CON (S5PC1XX_GPA0_BASE + 0x00) ++#define S5PC1XX_GPA0DAT (S5PC1XX_GPA0_BASE + 0x04) ++#define S5PC1XX_GPA0PUD (S5PC1XX_GPA0_BASE + 0x08) ++#define S5PC1XX_GPA0DRV (S5PC1XX_GPA0_BASE + 0x0c) ++#define S5PC1XX_GPA0CONPDN (S5PC1XX_GPA0_BASE + 0x10) ++#define S5PC1XX_GPA0PUDPDN (S5PC1XX_GPA0_BASE + 0x14) ++ ++#define S5PC1XX_GPA0_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPA0_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPA0_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPA0_0_UART_0_RXD (0x2 << 0) ++#define S5PC1XX_GPA0_0_GPIO_INT0_0 (0xf << 0) ++ ++#define S5PC1XX_GPA0_1_UART_0_TXD (0x2 << 4) ++#define S5PC1XX_GPA0_1_GPIO_INT0_1 (0xf << 4) ++ ++#define S5PC1XX_GPA0_2_UART_0_CTSn (0x2 << 8) ++#define S5PC1XX_GPA0_2_GPIO_INT0_2 (0xf << 8) ++ ++#define S5PC1XX_GPA0_3_UART_0_RTSn (0x2 << 12) ++#define S5PC1XX_GPA0_3_GPIO_INT0_3 (0xf << 12) ++ ++#define S5PC1XX_GPA0_4_UART_1_RXD (0x2 << 16) ++#define S5PC1XX_GPA0_4_GPIO_INT0_4 (0xf << 16) ++ ++#define S5PC1XX_GPA0_5_UART_1_TXD (0x2 << 20) ++#define S5PC1XX_GPA0_5_GPIO_INT0_5 (0xf << 20) ++ ++#define S5PC1XX_GPA0_6_UART_1_CTSn (0x2 << 24) ++#define S5PC1XX_GPA0_6_GPIO_INT0_6 (0xf << 24) ++ ++#define S5PC1XX_GPA0_7_UART_1_RTSn (0x2 << 28) ++#define S5PC1XX_GPA0_7_GPIO_INT0_7 (0xf << 28) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-a1.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-a1.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-a1.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-a1.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,45 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-a1.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank A1 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPA1CON (S5PC1XX_GPA1_BASE + 0x00) ++#define S5PC1XX_GPA1DAT (S5PC1XX_GPA1_BASE + 0x04) ++#define S5PC1XX_GPA1PUD (S5PC1XX_GPA1_BASE + 0x08) ++#define S5PC1XX_GPA1DRV (S5PC1XX_GPA1_BASE + 0x0c) ++#define S5PC1XX_GPA1CONPDN (S5PC1XX_GPA1_BASE + 0x10) ++#define S5PC1XX_GPA1PUDPDN (S5PC1XX_GPA1_BASE + 0x14) ++ ++#define S5PC1XX_GPA1_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPA1_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPA1_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPA1_0_UART_2_RXD (0x2 << 0) ++#define S5PC1XX_GPA1_0_GPIO_INT1_0 (0xf << 0) ++ ++#define S5PC1XX_GPA1_1_UART_2_TXD (0x2 << 4) ++#define S5PC1XX_GPA1_1_GPIO_INT1_1 (0xf << 4) ++ ++#define S5PC1XX_GPA1_2_UART_3_RXD (0x2 << 8) ++#define S5PC1XX_GPA1_2_UART_2_CTSn (0x3 << 8) ++#define S5PC1XX_GPA1_2_IrDA_RX_DATA (0x4 << 8) ++#define S5PC1XX_GPA1_2_GPIO_INT1_2 (0xf << 8) ++ ++#define S5PC1XX_GPA1_3_UART_3_TXD (0x2 << 12) ++#define S5PC1XX_GPA1_3_UART_2_RTSn (0x3 << 12) ++#define S5PC1XX_GPA1_3_IrDA_TX_DATA (0x4 << 12) ++#define S5PC1XX_GPA1_3_GPIO_INT1_3 (0xf << 12) ++ ++#define S5PC1XX_GPA1_4_UARTCLK (0x2 << 16) ++#define S5PC1XX_GPA1_4_IrDA_SDBW (0x4 << 16) ++#define S5PC1XX_GPA1_4_GPIO_INT1_4 (0xf << 16) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-b.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-b.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-b.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-b.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,49 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-b.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank B register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPBCON (S5PC1XX_GPB_BASE + 0x00) ++#define S5PC1XX_GPBDAT (S5PC1XX_GPB_BASE + 0x04) ++#define S5PC1XX_GPBPUD (S5PC1XX_GPB_BASE + 0x08) ++#define S5PC1XX_GPBDRV (S5PC1XX_GPB_BASE + 0x0c) ++#define S5PC1XX_GPBCONPDN (S5PC1XX_GPB_BASE + 0x10) ++#define S5PC1XX_GPBPUDPDN (S5PC1XX_GPB_BASE + 0x14) ++ ++#define S5PC1XX_GPB_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPB_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPB_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPB0_SPI_0_MISO (0x2 << 0) ++#define S5PC1XX_GPB0_GPIO_INT2_0 (0xf << 0) ++ ++#define S5PC1XX_GPB1_SPI_0_CLK (0x2 << 4) ++#define S5PC1XX_GPB1_GPIO_INT2_1 (0xf << 4) ++ ++#define S5PC1XX_GPB2_SPI_0_MOSI (0x2 << 8) ++#define S5PC1XX_GPB2_GPIO_INT2_2 (0xf << 8) ++ ++#define S5PC1XX_GPB3_SPI_0_nSS (0x2 << 12) ++#define S5PC1XX_GPB3_GPIO_INT2_3 (0xf << 12) ++ ++#define S5PC1XX_GPB4_SPI_1_MISO (0x2 << 16) ++#define S5PC1XX_GPB4_GPIO_INT2_4 (0xf << 16) ++ ++#define S5PC1XX_GPB5_SPI_1_CLK (0x2 << 20) ++#define S5PC1XX_GPB5_GPIO_INT2_5 (0xf << 20) ++ ++#define S5PC1XX_GPB6_SPI_1_MOSI (0x2 << 24) ++#define S5PC1XX_GPB6_GPIO_INT2_6 (0xf << 24) ++ ++#define S5PC1XX_GPB7_SPI_1_nSS (0x2 << 28) ++#define S5PC1XX_GPB7_GPIO_INT2_7 (0xf << 28) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-c.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-c.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-c.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-c.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,64 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-c.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank C register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPCCON (S5PC1XX_GPC_BASE + 0x00) ++#define S5PC1XX_GPCDAT (S5PC1XX_GPC_BASE + 0x04) ++#define S5PC1XX_GPCPUD (S5PC1XX_GPC_BASE + 0x08) ++#define S5PC1XX_GPCDRV (S5PC1XX_GPC_BASE + 0x0c) ++#define S5PC1XX_GPCCONPDN (S5PC1XX_GPC_BASE + 0x10) ++#define S5PC1XX_GPCPUDPDN (S5PC1XX_GPC_BASE + 0x14) ++ ++#define S5PC1XX_GPC_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPC_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPC_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPC0_I2S_1_SCLK (0x2 << 0) ++#define S5PC1XX_GPC0_PCM_1_SCLK (0x3 << 0) ++#define S5PC1XX_GPC0_AC97_BITCLK (0x4 << 0) ++#define S5PC1XX_GPC0_GPIO_INT3_0 (0xf << 0) ++ ++#define S5PC1XX_GPC1_I2S_1_CDCLK (0x2 << 4) ++#define S5PC1XX_GPC1_PCM_1_EXTCLK (0x3 << 4) ++#define S5PC1XX_GPC1_AC97_RESETn (0x4 << 4) ++#define S5PC1XX_GPC1_GPIO_INT3_1 (0xf << 4) ++ ++#define S5PC1XX_GPC2_I2S_1_LRCK (0x2 << 8) ++#define S5PC1XX_GPC2_PCM_1_FSYNC (0x3 << 8) ++#define S5PC1XX_GPC2_AC97_SYNC (0x4 << 8) ++#define S5PC1XX_GPC2_GPIO_INT3_2 (0xf << 8) ++ ++#define S5PC1XX_GPC3_I2S_1_SDI (0x2 << 12) ++#define S5PC1XX_GPC3_PCM_1_SIN (0x3 << 12) ++#define S5PC1XX_GPC3_AC97_SDI (0x4 << 12) ++#define S5PC1XX_GPC3_GPIO_INT3_3 (0xf << 12) ++ ++#define S5PC1XX_GPC4_I2S_1_SDO (0x2 << 16) ++#define S5PC1XX_GPC4_PCM_1_SOUT (0x3 << 16) ++#define S5PC1XX_GPC4_AC97_SDO (0x4 << 16) ++#define S5PC1XX_GPC4_GPIO_INT3_4 (0xf << 16) ++ ++#define S5PC1XX_GPB0_SPI_MISO0 (2<<0) ++#define S5PC1XX_GPB1_SPI_CLK0 (2<<4) ++#define S5PC1XX_GPB2_SPI_MOSI0 (2<<8) ++#define S5PC1XX_GPB3_SPI_CS0 (2<<12) ++ ++#define S5PC1XX_GPB4_SPI_MISO1 (2<<16) ++#define S5PC1XX_GPB5_SPI_CLK1 (2<<20) ++#define S5PC1XX_GPB6_SPI_MOSI1 (2<<24) ++#define S5PC1XX_GPB7_SPI_CS1 (2<<28) ++ ++#define S5PC1XX_GPG3_0SPI_CLK2 (3<<0) ++#define S5PC1XX_GPG3_1SPI_CS2 (3<<4) ++#define S5PC1XX_GPG3_2SPI_MISO2 (3<<8) ++#define S5PC1XX_GPG3_3SPI_MOSI2 (3<<12) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-d.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-d.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-d.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-d.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,51 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-d.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank D register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPDCON (S5PC1XX_GPD_BASE + 0x00) ++#define S5PC1XX_GPDDAT (S5PC1XX_GPD_BASE + 0x04) ++#define S5PC1XX_GPDPUD (S5PC1XX_GPD_BASE + 0x08) ++#define S5PC1XX_GPDDRV (S5PC1XX_GPD_BASE + 0x0c) ++#define S5PC1XX_GPDCONPDN (S5PC1XX_GPD_BASE + 0x10) ++#define S5PC1XX_GPDPUDPDN (S5PC1XX_GPD_BASE + 0x14) ++ ++#define S5PC1XX_GPD_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPD_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPD_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPD0_TOUT_0 (0x2 << 0) ++#define S5PC1XX_GPD0_PWM_TCLK (0x3 << 0) ++#define S5PC1XX_GPD0_GPIO_INT4_0 (0xf << 0) ++ ++#define S5PC1XX_GPD1_TOUT_1 (0x2 << 4) ++#define S5PC1XX_GPD1_EX_DMA_REQn (0x3 << 4) ++#define S5PC1XX_GPD1_GPIO_INT4_1 (0xf << 4) ++ ++#define S5PC1XX_GPD2_TOUT_2 (0x2 << 8) ++#define S5PC1XX_GPD2_EX_DMA_ACKn (0x3 << 8) ++#define S5PC1XX_GPD2_GPIO_INT4_2 (0xf << 8) ++ ++#define S5PC1XX_GPD3_I2C0_SDA (0x2 << 12) ++#define S5PC1XX_GPD3_GPIO_INT4_3 (0xf << 12) ++ ++#define S5PC1XX_GPD4_I2C0_SCL (0x2 << 16) ++#define S5PC1XX_GPD4_GPIO_INT4_4 (0xf << 16) ++ ++#define S5PC1XX_GPD5_I2C1_SDA (0x2 << 20) ++#define S5PC1XX_GPD5_SPDIF0_OUT (0x3 << 20) ++#define S5PC1XX_GPD5_GPIO_INT4_5 (0xf << 20) ++ ++#define S5PC1XX_GPD6_I2C1_SCL (0x2 << 24) ++#define S5PC1XX_GPD6_SPDIF_EXTCLK (0x3 << 24) ++#define S5PC1XX_GPD6_GPIO_INT4_6 (0xf << 24) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-e0.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-e0.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-e0.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-e0.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,57 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-e0.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank E0 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPE0CON (S5PC1XX_GPE0_BASE + 0x00) ++#define S5PC1XX_GPE0DAT (S5PC1XX_GPE0_BASE + 0x04) ++#define S5PC1XX_GPE0PUD (S5PC1XX_GPE0_BASE + 0x08) ++#define S5PC1XX_GPE0DRV (S5PC1XX_GPE0_BASE + 0x0c) ++#define S5PC1XX_GPE0CONPDN (S5PC1XX_GPE0_BASE + 0x10) ++#define S5PC1XX_GPE0PUDPDN (S5PC1XX_GPE0_BASE + 0x14) ++ ++#define S5PC1XX_GPE0_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPE0_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPE0_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPE0_0_CAM_A_PCLK (0x2 << 0) ++#define S5PC1XX_GPE0_0_SD_1_CLK (0x3 << 0) ++#define S5PC1XX_GPE0_0_GPIO_INT5_0 (0xf << 0) ++ ++#define S5PC1XX_GPE0_1_CAM_A_VSYNC (0x2 << 4) ++#define S5PC1XX_GPE0_1_SD_1_CDn (0x3 << 4) ++#define S5PC1XX_GPE0_1_GPIO_INT5_1 (0xf << 4) ++ ++#define S5PC1XX_GPE0_2_CAM_A_HREF (0x2 << 8) ++#define S5PC1XX_GPE0_2_SD_1_CMD (0x3 << 8) ++#define S5PC1XX_GPE0_2_GPIO_INT5_2 (0xf << 8) ++ ++#define S5PC1XX_GPE0_3_CAM_A_DATA_0 (0x2 << 12) ++#define S5PC1XX_GPE0_3_SD_1_DATA_0 (0x3 << 12) ++#define S5PC1XX_GPE0_3_GPIO_INT5_3 (0xf << 12) ++ ++#define S5PC1XX_GPE0_4_CAM_A_DATA_1 (0x2 << 16) ++#define S5PC1XX_GPE0_4_SD_1_DATA_1 (0x3 << 16) ++#define S5PC1XX_GPE0_4_GPIO_INT5_4 (0xf << 16) ++ ++#define S5PC1XX_GPE0_5_CAM_A_DATA_2 (0x2 << 20) ++#define S5PC1XX_GPE0_5_SD_1_DATA_2 (0x3 << 20) ++#define S5PC1XX_GPE0_5_GPIO_INT5_5 (0xf << 20) ++ ++#define S5PC1XX_GPE0_6_CAM_A_DATA_3 (0x2 << 24) ++#define S5PC1XX_GPE0_6_SD_1_DATA_3 (0x3 << 24) ++#define S5PC1XX_GPE0_6_GPIO_INT5_6 (0xf << 24) ++ ++#define S5PC1XX_GPE0_7_CAM_A_DATA_4 (0x2 << 28) ++#define S5PC1XX_GPE0_7_SD_1_DATA_4 (0x3 << 28) ++#define S5PC1XX_GPE0_7_GPIO_INT5_7 (0xf << 28) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-e1.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-e1.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-e1.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-e1.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,46 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-e1.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank E1 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPE1CON (S5PC1XX_GPE1_BASE + 0x00) ++#define S5PC1XX_GPE1DAT (S5PC1XX_GPE1_BASE + 0x04) ++#define S5PC1XX_GPE1PUD (S5PC1XX_GPE1_BASE + 0x08) ++#define S5PC1XX_GPE1DRV (S5PC1XX_GPE1_BASE + 0x0c) ++#define S5PC1XX_GPE1CONPDN (S5PC1XX_GPE1_BASE + 0x10) ++#define S5PC1XX_GPE1PUDPDN (S5PC1XX_GPE1_BASE + 0x14) ++ ++#define S5PC1XX_GPE1_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPE1_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPE1_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPE1_0_CAM_A_DATA_5 (0x2 << 0) ++#define S5PC1XX_GPE1_0_SD_1_DATA_5 (0x3 << 0) ++#define S5PC1XX_GPE1_0_GPIO_INT6_0 (0xf << 0) ++ ++#define S5PC1XX_GPE1_1_CAM_A_DATA_6 (0x2 << 4) ++#define S5PC1XX_GPE1_1_SD_1_DATA_6 (0x3 << 4) ++#define S5PC1XX_GPE1_1_GPIO_INT6_1 (0xf << 4) ++ ++#define S5PC1XX_GPE1_2_CAM_A_DATA_7 (0x2 << 8) ++#define S5PC1XX_GPE1_2_SD_1_DATA_7 (0x3 << 8) ++#define S5PC1XX_GPE1_2_GPIO_INT6_2 (0xf << 8) ++ ++#define S5PC1XX_GPE1_3_CAM_A_CLKOUT (0x2 << 12) ++#define S5PC1XX_GPE1_3_GPIO_INT6_3 (0xf << 12) ++ ++#define S5PC1XX_GPE1_4_CAM_A_RESET (0x2 << 16) ++#define S5PC1XX_GPE1_4_GPIO_INT6_4 (0xf << 16) ++ ++#define S5PC1XX_GPE1_5_CAM_A_FIELD (0x2 << 20) ++#define S5PC1XX_GPE1_5_GPIO_INT6_5 (0xf << 20) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f0.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f0.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f0.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f0.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,65 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f0.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank F0 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPF0CON (S5PC1XX_GPF0_BASE + 0x00) ++#define S5PC1XX_GPF0DAT (S5PC1XX_GPF0_BASE + 0x04) ++#define S5PC1XX_GPF0PUD (S5PC1XX_GPF0_BASE + 0x08) ++#define S5PC1XX_GPF0DRV (S5PC1XX_GPF0_BASE + 0x0c) ++#define S5PC1XX_GPF0CONPDN (S5PC1XX_GPF0_BASE + 0x10) ++#define S5PC1XX_GPF0PUDPDN (S5PC1XX_GPF0_BASE + 0x14) ++ ++#define S5PC1XX_GPF0_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPF0_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPF0_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPF0_0_LCD_HSYNC (0x2 << 0) ++#define S5PC1XX_GPF0_0_SYS_CS0 (0x3 << 0) ++#define S5PC1XX_GPF0_0_VEN_HSYNC (0x4 << 0) ++#define S5PC1XX_GPF0_0_GPIO_INT7_0 (0xf << 0) ++ ++#define S5PC1XX_GPF0_1_LCD_VSYNC (0x2 << 4) ++#define S5PC1XX_GPF0_1_SYS_CS1 (0x3 << 4) ++#define S5PC1XX_GPF0_1_VEN_VSYNC (0x4 << 4) ++#define S5PC1XX_GPF0_1_GPIO_INT7_1 (0xf << 4) ++ ++#define S5PC1XX_GPF0_2_LCD_VDEN (0x2 << 8) ++#define S5PC1XX_GPF0_2_SYS_RS (0x3 << 8) ++#define S5PC1XX_GPF0_2_VEN_HREF (0x4 << 8) ++#define S5PC1XX_GPF0_2_GPIO_INT7_2 (0xf << 8) ++ ++#define S5PC1XX_GPF0_3_LCD_VCLK (0x2 << 12) ++#define S5PC1XX_GPF0_3_SYS_WE (0x3 << 12) ++#define S5PC1XX_GPF0_3_V601_CLK (0x4 << 12) ++#define S5PC1XX_GPF0_3_GPIO_INT7_3 (0xf << 12) ++ ++#define S5PC1XX_GPF0_4_LCD_VD_0 (0x2 << 16) ++#define S5PC1XX_GPF0_4_SYS_VD_0 (0x3 << 16) ++#define S5PC1XX_GPF0_4_VEN_DATA_0 (0x4 << 16) ++#define S5PC1XX_GPF0_4_GPIO_INT7_4 (0xf << 16) ++ ++#define S5PC1XX_GPF0_5_LCD_VD_1 (0x2 << 20) ++#define S5PC1XX_GPF0_5_SYS_VD_1 (0x3 << 20) ++#define S5PC1XX_GPF0_5_VEN_DATA_1 (0x4 << 20) ++#define S5PC1XX_GPF0_5_GPIO_INT7_5 (0xf << 20) ++ ++#define S5PC1XX_GPF0_6_LCD_VD_2 (0x2 << 24) ++#define S5PC1XX_GPF0_6_SYS_VD_2 (0x3 << 24) ++#define S5PC1XX_GPF0_6_VEN_DATA_2 (0x4 << 24) ++#define S5PC1XX_GPF0_6_GPIO_INT7_6 (0xf << 24) ++ ++#define S5PC1XX_GPF0_7_LCD_VD_3 (0x2 << 28) ++#define S5PC1XX_GPF0_7_SYS_VD_3 (0x3 << 28) ++#define S5PC1XX_GPF0_7_VEN_DATA_3 (0x4 << 28) ++#define S5PC1XX_GPF0_7_GPIO_INT7_7 (0xf << 28) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f1.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f1.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f1.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f1.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,65 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f1.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank F1 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPF1CON (S5PC1XX_GPF1_BASE + 0x00) ++#define S5PC1XX_GPF1DAT (S5PC1XX_GPF1_BASE + 0x04) ++#define S5PC1XX_GPF1PUD (S5PC1XX_GPF1_BASE + 0x08) ++#define S5PC1XX_GPF1DRV (S5PC1XX_GPF1_BASE + 0x0c) ++#define S5PC1XX_GPF1CONPDN (S5PC1XX_GPF1_BASE + 0x10) ++#define S5PC1XX_GPF1PUDPDN (S5PC1XX_GPF1_BASE + 0x14) ++ ++#define S5PC1XX_GPF1_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPF1_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPF1_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPF1_0_LCD_VD_4 (0x2 << 0) ++#define S5PC1XX_GPF1_0_SYS_VD_4 (0x3 << 0) ++#define S5PC1XX_GPF1_0_VEN_DATA_4 (0x4 << 0) ++#define S5PC1XX_GPF1_0_GPIO_INT8_0 (0xf << 0) ++ ++#define S5PC1XX_GPF1_1_LCD_VD_5 (0x2 << 4) ++#define S5PC1XX_GPF1_1_SYS_VD_5 (0x3 << 4) ++#define S5PC1XX_GPF1_1_VEN_DATA_5 (0x4 << 4) ++#define S5PC1XX_GPF1_1_GPIO_INT8_1 (0xf << 4) ++ ++#define S5PC1XX_GPF1_2_LCD_VD_6 (0x2 << 8) ++#define S5PC1XX_GPF1_2_SYS_VD_6 (0x3 << 8) ++#define S5PC1XX_GPF1_2_VEN_DATA_6 (0x4 << 8) ++#define S5PC1XX_GPF1_2_GPIO_INT8_2 (0xf << 8) ++ ++#define S5PC1XX_GPF1_3_LCD_VD_7 (0x2 << 12) ++#define S5PC1XX_GPF1_3_SYS_VD_7 (0x3 << 12) ++#define S5PC1XX_GPF1_3_VEN_DATA_7 (0x4 << 12) ++#define S5PC1XX_GPF1_3_GPIO_INT8_3 (0xf << 12) ++ ++#define S5PC1XX_GPF1_4_LCD_VD_8 (0x2 << 16) ++#define S5PC1XX_GPF1_4_SYS_VD_8 (0x3 << 16) ++#define S5PC1XX_GPF1_4_V656_DATA_0 (0x4 << 16) ++#define S5PC1XX_GPF1_4_GPIO_INT8_4 (0xf << 16) ++ ++#define S5PC1XX_GPF1_5_LCD_VD_9 (0x2 << 20) ++#define S5PC1XX_GPF1_5_SYS_VD_9 (0x3 << 20) ++#define S5PC1XX_GPF1_5_V656_DATA_1 (0x4 << 20) ++#define S5PC1XX_GPF1_5_GPIO_INT8_5 (0xf << 20) ++ ++#define S5PC1XX_GPF1_6_LCD_VD_10 (0x2 << 24) ++#define S5PC1XX_GPF1_6_SYS_VD_10 (0x3 << 24) ++#define S5PC1XX_GPF1_6_V656_DATA_2 (0x4 << 24) ++#define S5PC1XX_GPF1_6_GPIO_INT8_6 (0xf << 24) ++ ++#define S5PC1XX_GPF1_7_LCD_VD_11 (0x2 << 28) ++#define S5PC1XX_GPF1_7_SYS_VD_11 (0x3 << 28) ++#define S5PC1XX_GPF1_7_V656_DATA_3 (0x4 << 28) ++#define S5PC1XX_GPF1_7_GPIO_INT8_7 (0xf << 28) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f2.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f2.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f2.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f2.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,59 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f2.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank F2 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPF2CON (S5PC1XX_GPF2_BASE + 0x00) ++#define S5PC1XX_GPF2DAT (S5PC1XX_GPF2_BASE + 0x04) ++#define S5PC1XX_GPF2PUD (S5PC1XX_GPF2_BASE + 0x08) ++#define S5PC1XX_GPF2DRV (S5PC1XX_GPF2_BASE + 0x0c) ++#define S5PC1XX_GPF2CONPDN (S5PC1XX_GPF2_BASE + 0x10) ++#define S5PC1XX_GPF2PUDPDN (S5PC1XX_GPF2_BASE + 0x14) ++ ++#define S5PC1XX_GPF2_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPF2_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPF2_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPF2_0_LCD_VD_12 (0x2 << 0) ++#define S5PC1XX_GPF2_0_SYS_VD_12 (0x3 << 0) ++#define S5PC1XX_GPF2_0_V656_DATA_4 (0x4 << 0) ++#define S5PC1XX_GPF2_0_GPIO_INT9_0 (0xf << 0) ++ ++#define S5PC1XX_GPF2_1_LCD_VD_13 (0x2 << 4) ++#define S5PC1XX_GPF2_1_SYS_VD_13 (0x3 << 4) ++#define S5PC1XX_GPF2_1_V656_DATA_5 (0x4 << 4) ++#define S5PC1XX_GPF2_1_GPIO_INT9_1 (0xf << 4) ++ ++#define S5PC1XX_GPF2_2_LCD_VD_14 (0x2 << 8) ++#define S5PC1XX_GPF2_2_SYS_VD_14 (0x3 << 8) ++#define S5PC1XX_GPF2_2_V656_DATA_6 (0x4 << 8) ++#define S5PC1XX_GPF2_2_GPIO_INT9_2 (0xf << 8) ++ ++#define S5PC1XX_GPF2_3_LCD_VD_15 (0x2 << 12) ++#define S5PC1XX_GPF2_3_SYS_VD_15 (0x3 << 12) ++#define S5PC1XX_GPF2_3_V656_DATA_7 (0x4 << 12) ++#define S5PC1XX_GPF2_3_GPIO_INT9_3 (0xf << 12) ++ ++#define S5PC1XX_GPF2_4_LCD_VD_16 (0x2 << 16) ++#define S5PC1XX_GPF2_4_SYS_VD_16 (0x3 << 16) ++#define S5PC1XX_GPF2_4_GPIO_INT9_4 (0xf << 16) ++ ++#define S5PC1XX_GPF2_5_LCD_VD_17 (0x2 << 20) ++#define S5PC1XX_GPF2_5_SYS_VD_17 (0x3 << 20) ++#define S5PC1XX_GPF2_5_GPIO_INT9_5 (0xf << 20) ++ ++#define S5PC1XX_GPF2_6_LCD_VD_18 (0x2 << 24) ++#define S5PC1XX_GPF2_6_GPIO_INT9_6 (0xf << 24) ++ ++#define S5PC1XX_GPF2_7_LCD_VD_19 (0x2 << 28) ++#define S5PC1XX_GPF2_7_GPIO_INT9_7 (0xf << 28) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f3.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f3.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f3.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f3.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,41 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-f3.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank F3 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPF3CON (S5PC1XX_GPF3_BASE + 0x00) ++#define S5PC1XX_GPF3DAT (S5PC1XX_GPF3_BASE + 0x04) ++#define S5PC1XX_GPF3PUD (S5PC1XX_GPF3_BASE + 0x08) ++#define S5PC1XX_GPF3DRV (S5PC1XX_GPF3_BASE + 0x0c) ++#define S5PC1XX_GPF3CONPDN (S5PC1XX_GPF3_BASE + 0x10) ++#define S5PC1XX_GPF3PUDPDN (S5PC1XX_GPF3_BASE + 0x14) ++ ++#define S5PC1XX_GPF3_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPF3_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPF3_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPF3_0_LCD_VD_20 (0x2 << 0) ++#define S5PC1XX_GPF3_0_GPIO_INT10_0 (0xf << 0) ++ ++#define S5PC1XX_GPF3_1_LCD_VD_21 (0x2 << 4) ++#define S5PC1XX_GPF3_1_GPIO_INT10_1 (0xf << 4) ++ ++#define S5PC1XX_GPF3_2_LCD_VD_22 (0x2 << 8) ++#define S5PC1XX_GPF3_2_VSYNC_LDI (0x3 << 8) ++#define S5PC1XX_GPF3_2_V656_CLK (0x4 << 8) ++#define S5PC1XX_GPF3_2_GPIO_INT10_2 (0xf << 8) ++ ++#define S5PC1XX_GPF3_3_LCD_VD_23 (0x2 << 12) ++#define S5PC1XX_GPF3_3_SYS_OE (0x3 << 12) ++#define S5PC1XX_GPF3_3_VEN_FIELD (0x4 << 12) ++#define S5PC1XX_GPF3_3_GPIO_INT10_3 (0xf << 12) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g0.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g0.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g0.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g0.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,49 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g0.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank G0 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPG0CON (S5PC1XX_GPG0_BASE + 0x00) ++#define S5PC1XX_GPG0DAT (S5PC1XX_GPG0_BASE + 0x04) ++#define S5PC1XX_GPG0PUD (S5PC1XX_GPG0_BASE + 0x08) ++#define S5PC1XX_GPG0DRV (S5PC1XX_GPG0_BASE + 0x0c) ++#define S5PC1XX_GPG0CONPDN (S5PC1XX_GPG0_BASE + 0x10) ++#define S5PC1XX_GPG0PUDPDN (S5PC1XX_GPG0_BASE + 0x14) ++ ++#define S5PC1XX_GPG0_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPG0_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPG0_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPG0_0_SD_0_CLK (0x2 << 0) ++#define S5PC1XX_GPG0_0_GPIO_INT11_0 (0xf << 0) ++ ++#define S5PC1XX_GPG0_1_SD_0_CMD (0x2 << 4) ++#define S5PC1XX_GPG0_1_GPIO_INT11_1 (0xf << 4) ++ ++#define S5PC1XX_GPG0_2_SD_0_DATA_0 (0x2 << 8) ++#define S5PC1XX_GPG0_2_GPIO_INT11_2 (0xf << 8) ++ ++#define S5PC1XX_GPG0_3_SD_0_DATA_1 (0x2 << 12) ++#define S5PC1XX_GPG0_3_GPIO_INT11_3 (0xf << 12) ++ ++#define S5PC1XX_GPG0_4_SD_0_DATA_2 (0x2 << 16) ++#define S5PC1XX_GPG0_4_GPIO_INT11_4 (0xf << 16) ++ ++#define S5PC1XX_GPG0_5_SD_0_DATA_3 (0x2 << 20) ++#define S5PC1XX_GPG0_5_GPIO_INT11_5 (0xf << 20) ++ ++#define S5PC1XX_GPG0_6_SD_0_DATA_4 (0x2 << 24) ++#define S5PC1XX_GPG0_6_GPIO_INT11_6 (0xf << 24) ++ ++#define S5PC1XX_GPG0_7_SD_0_DATA_5 (0x2 << 28) ++#define S5PC1XX_GPG0_7_GPIO_INT11_7 (0xf << 28) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g1.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g1.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g1.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g1.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,34 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g1.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank G1 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPG1CON (S5PC1XX_GPG1_BASE + 0x00) ++#define S5PC1XX_GPG1DAT (S5PC1XX_GPG1_BASE + 0x04) ++#define S5PC1XX_GPG1PUD (S5PC1XX_GPG1_BASE + 0x08) ++#define S5PC1XX_GPG1DRV (S5PC1XX_GPG1_BASE + 0x0c) ++#define S5PC1XX_GPG1CONPDN (S5PC1XX_GPG1_BASE + 0x10) ++#define S5PC1XX_GPG1PUDPDN (S5PC1XX_GPG1_BASE + 0x14) ++ ++#define S5PC1XX_GPG1_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPG1_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPG1_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPG1_0_SD_0_DATA_6 (0x2 << 0) ++#define S5PC1XX_GPG1_0_GPIO_INT12_0 (0xf << 0) ++ ++#define S5PC1XX_GPG1_1_SD_0_DATA_7 (0x2 << 4) ++#define S5PC1XX_GPG1_1_GPIO_INT12_1 (0xf << 4) ++ ++#define S5PC1XX_GPG1_2_SD_0_CDn (0x2 << 8) ++#define S5PC1XX_GPG1_2_GPIO_INT12_2 (0xf << 8) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g2.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g2.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g2.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g2.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,46 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g2.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank G2 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPG2CON (S5PC1XX_GPG2_BASE + 0x00) ++#define S5PC1XX_GPG2DAT (S5PC1XX_GPG2_BASE + 0x04) ++#define S5PC1XX_GPG2PUD (S5PC1XX_GPG2_BASE + 0x08) ++#define S5PC1XX_GPG2DRV (S5PC1XX_GPG2_BASE + 0x0c) ++#define S5PC1XX_GPG2CONPDN (S5PC1XX_GPG2_BASE + 0x10) ++#define S5PC1XX_GPG2PUDPDN (S5PC1XX_GPG2_BASE + 0x14) ++ ++#define S5PC1XX_GPG2_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPG2_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPG2_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPG2_0_SD_1_CLK (0x2 << 0) ++#define S5PC1XX_GPG2_0_GPIO_INT13_0 (0xf << 0) ++ ++#define S5PC1XX_GPG2_1_SD_1_CMD (0x2 << 4) ++#define S5PC1XX_GPG2_1_GPIO_INT13_1 (0xf << 4) ++ ++#define S5PC1XX_GPG2_2_SD_1_DATA_0 (0x2 << 8) ++#define S5PC1XX_GPG2_2_GPIO_INT13_2 (0xf << 8) ++ ++#define S5PC1XX_GPG2_3_SD_1_DATA_1 (0x2 << 12) ++#define S5PC1XX_GPG2_3_GPIO_INT13_3 (0xf << 12) ++ ++#define S5PC1XX_GPG2_4_SD_1_DATA_2 (0x2 << 16) ++#define S5PC1XX_GPG2_4_GPIO_INT13_4 (0xf << 16) ++ ++#define S5PC1XX_GPG2_5_SD_1_DATA_3 (0x2 << 20) ++#define S5PC1XX_GPG2_5_GPIO_INT13_5 (0xf << 20) ++ ++#define S5PC1XX_GPG2_6_SD_1_CDn (0x2 << 24) ++#define S5PC1XX_GPG2_6_GPIO_INT13_6 (0xf << 24) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g3.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g3.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g3.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g3.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,62 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-g3.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank G3 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPG3CON (S5PC1XX_GPG3_BASE + 0x00) ++#define S5PC1XX_GPG3DAT (S5PC1XX_GPG3_BASE + 0x04) ++#define S5PC1XX_GPG3PUD (S5PC1XX_GPG3_BASE + 0x08) ++#define S5PC1XX_GPG3DRV (S5PC1XX_GPG3_BASE + 0x0c) ++#define S5PC1XX_GPG3CONPDN (S5PC1XX_GPG3_BASE + 0x10) ++#define S5PC1XX_GPG3PUDPDN (S5PC1XX_GPG3_BASE + 0x14) ++ ++#define S5PC1XX_GPG3_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPG3_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPG3_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPG3_0_SD_2_CLK (0x2 << 0) ++#define S5PC1XX_GPG3_0_SPI_2_CLK (0x3 << 0) ++#define S5PC1XX_GPG3_0_I2S_2_SCLK (0x4 << 0) ++#define S5PC1XX_GPG3_0_PCM_0_SCLK (0x5 << 0) ++#define S5PC1XX_GPG3_0_GPIO_INT14_0 (0xf << 0) ++ ++#define S5PC1XX_GPG3_1_SD_2_CMD (0x2 << 4) ++#define S5PC1XX_GPG3_1_SPI_2_nSS (0x3 << 4) ++#define S5PC1XX_GPG3_1_I2S_2_CDCLK (0x4 << 4) ++#define S5PC1XX_GPG3_1_PCM_0_EXTCLK (0x5 << 4) ++#define S5PC1XX_GPG3_1_GPIO_INT14_1 (0xf << 4) ++ ++#define S5PC1XX_GPG3_2_SD_2_DATA0 (0x2 << 8) ++#define S5PC1XX_GPG3_2_SPI_2_MISO (0x3 << 8) ++#define S5PC1XX_GPG3_2_I2S_2_LRCK (0x4 << 8) ++#define S5PC1XX_GPG3_2_PCM_0_FSYNC (0x5 << 8) ++#define S5PC1XX_GPG3_2_GPIO_INT14_2 (0xf << 8) ++ ++#define S5PC1XX_GPG3_3_SD_2_DATA1 (0x2 << 12) ++#define S5PC1XX_GPG3_3_SPI_2_MOSI (0x3 << 12) ++#define S5PC1XX_GPG3_3_I2S_2_SDI (0x4 << 12) ++#define S5PC1XX_GPG3_3_PCM_0_SIN (0x5 << 12) ++#define S5PC1XX_GPG3_3_GPIO_INT14_3 (0xf << 12) ++ ++#define S5PC1XX_GPG3_4_SD_2_DATA2 (0x2 << 16) ++#define S5PC1XX_GPG3_4_I2S_2_SDO (0x4 << 16) ++#define S5PC1XX_GPG3_4_PCM_0_SOUT (0x5 << 16) ++#define S5PC1XX_GPG3_4_GPIO_INT14_4 (0xf << 16) ++ ++#define S5PC1XX_GPG3_5_SD_2_DATA3 (0x2 << 20) ++#define S5PC1XX_GPG3_5_SPDIF0_OUT (0x5 << 20) ++#define S5PC1XX_GPG3_5_GPIO_INT14_5 (0xf << 20) ++ ++#define S5PC1XX_GPG3_6_SD_2_CDn (0x2 << 24) ++#define S5PC1XX_GPG3_6_SPDIF_EXTCLK (0x5 << 24) ++#define S5PC1XX_GPG3_6_GPIO_INT14_6 (0xf << 24) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h0.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h0.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h0.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h0.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,33 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h0.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank H0 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPH0CON (S5PC1XX_GPH0_BASE + 0x00) ++#define S5PC1XX_GPH0DAT (S5PC1XX_GPH0_BASE + 0x04) ++#define S5PC1XX_GPH0PUD (S5PC1XX_GPH0_BASE + 0x08) ++#define S5PC1XX_GPH0DRV (S5PC1XX_GPH0_BASE + 0x0c) ++#define S5PC1XX_GPH0CONPDN (S5PC1XX_GPH0_BASE + 0x10) ++#define S5PC1XX_GPH0PUDPDN (S5PC1XX_GPH0_BASE + 0x14) ++ ++#define S5PC1XX_GPH0_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPH0_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPH0_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPH0_0_WAKEUP_INT_0 (0x2 << 0) ++#define S5PC1XX_GPH0_1_WAKEUP_INT_1 (0x2 << 4) ++#define S5PC1XX_GPH0_2_WAKEUP_INT_2 (0x2 << 8) ++#define S5PC1XX_GPH0_3_WAKEUP_INT_3 (0x2 << 12) ++#define S5PC1XX_GPH0_4_WAKEUP_INT_4 (0x2 << 16) ++#define S5PC1XX_GPH0_5_WAKEUP_INT_5 (0x2 << 20) ++#define S5PC1XX_GPH0_6_WAKEUP_INT_6 (0x2 << 24) ++#define S5PC1XX_GPH0_7_WAKEUP_INT_7 (0x2 << 28) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h1.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h1.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h1.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h1.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,47 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h1.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank H1 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPH1CON (S5PC1XX_GPH1_BASE + 0x00) ++#define S5PC1XX_GPH1DAT (S5PC1XX_GPH1_BASE + 0x04) ++#define S5PC1XX_GPH1PUD (S5PC1XX_GPH1_BASE + 0x08) ++#define S5PC1XX_GPH1DRV (S5PC1XX_GPH1_BASE + 0x0c) ++#define S5PC1XX_GPH1CONPDN (S5PC1XX_GPH1_BASE + 0x10) ++#define S5PC1XX_GPH1PUDPDN (S5PC1XX_GPH1_BASE + 0x14) ++ ++#define S5PC1XX_GPH1_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPH1_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPH1_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPH1_0_WAKEUP_INT_8 (0x2 << 0) ++ ++#define S5PC1XX_GPH1_1_WAKEUP_INT_9 (0x2 << 4) ++ ++#define S5PC1XX_GPH1_2_WAKEUP_INT_10 (0x2 << 8) ++#define S5PC1XX_GPH1_2_CG_REALIN (0x3 << 8) ++ ++#define S5PC1XX_GPH1_3_WAKEUP_INT_11 (0x2 << 12) ++#define S5PC1XX_GPH1_3_CG_IMGIN (0x3 << 12) ++ ++#define S5PC1XX_GPH1_4_WAKEUP_INT_12 (0x2 << 16) ++#define S5PC1XX_GPH1_4_CG_GPO0 (0x3 << 16) ++ ++#define S5PC1XX_GPH1_5_WAKEUP_INT_13 (0x2 << 20) ++#define S5PC1XX_GPH1_5_CG_GPO1 (0x3 << 20) ++ ++#define S5PC1XX_GPH1_6_WAKEUP_INT_14 (0x2 << 24) ++#define S5PC1XX_GPH1_6_CG_GPO2 (0x3 << 24) ++ ++#define S5PC1XX_GPH1_7_WAKEUP_INT_15 (0x2 << 28) ++#define S5PC1XX_GPH1_7_CG_GPO3 (0x3 << 28) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h2.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h2.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h2.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h2.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,57 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h2.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank H2 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPH2CON (S5PC1XX_GPH2_BASE + 0x00) ++#define S5PC1XX_GPH2DAT (S5PC1XX_GPH2_BASE + 0x04) ++#define S5PC1XX_GPH2PUD (S5PC1XX_GPH2_BASE + 0x08) ++#define S5PC1XX_GPH2DRV (S5PC1XX_GPH2_BASE + 0x0c) ++#define S5PC1XX_GPH2CONPDN (S5PC1XX_GPH2_BASE + 0x10) ++#define S5PC1XX_GPH2PUDPDN (S5PC1XX_GPH2_BASE + 0x14) ++ ++#define S5PC1XX_GPH2_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPH2_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPH2_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPH2_0_WAKEUP_INT_16 (0x2 << 0) ++#define S5PC1XX_GPH2_0_KEYPAD_COL_0 (0x3 << 0) ++#define S5PC1XX_GPH2_0_CAM_B_DATA_0 (0x4 << 0) ++ ++#define S5PC1XX_GPH2_1_WAKEUP_INT_17 (0x2 << 4) ++#define S5PC1XX_GPH2_1_KEYPAD_COL_1 (0x3 << 4) ++#define S5PC1XX_GPH2_1_CAM_B_DATA_1 (0x4 << 4) ++ ++#define S5PC1XX_GPH2_2_WAKEUP_INT_18 (0x2 << 8) ++#define S5PC1XX_GPH2_2_KEYPAD_COL_2 (0x3 << 8) ++#define S5PC1XX_GPH2_2_CAM_B_DATA_2 (0x4 << 8) ++ ++#define S5PC1XX_GPH2_3_WAKEUP_INT_19 (0x2 << 12) ++#define S5PC1XX_GPH2_3_KEYPAD_COL_3 (0x3 << 12) ++#define S5PC1XX_GPH2_3_CAM_B_DATA_3 (0x4 << 12) ++ ++#define S5PC1XX_GPH2_4_WAKEUP_INT_20 (0x2 << 16) ++#define S5PC1XX_GPH2_4_KEYPAD_COL_4 (0x3 << 16) ++#define S5PC1XX_GPH2_4_CAM_B_DATA_4 (0x4 << 16) ++ ++#define S5PC1XX_GPH2_5_WAKEUP_INT_21 (0x2 << 20) ++#define S5PC1XX_GPH2_5_KEYPAD_COL_5 (0x3 << 20) ++#define S5PC1XX_GPH2_5_CAM_B_DATA_5 (0x4 << 20) ++ ++#define S5PC1XX_GPH2_6_WAKEUP_INT_22 (0x2 << 24) ++#define S5PC1XX_GPH2_6_KEYPAD_COL_6 (0x3 << 24) ++#define S5PC1XX_GPH2_6_CAM_B_DATA_6 (0x4 << 24) ++ ++#define S5PC1XX_GPH2_7_WAKEUP_INT_23 (0x2 << 28) ++#define S5PC1XX_GPH2_7_KEYPAD_COL_7 (0x3 << 28) ++#define S5PC1XX_GPH2_7_CAM_B_DATA_7 (0x4 << 28) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h3.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h3.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h3.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h3.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,57 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-h3.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank H3 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPH3CON (S5PC1XX_GPH3_BASE + 0x00) ++#define S5PC1XX_GPH3DAT (S5PC1XX_GPH3_BASE + 0x04) ++#define S5PC1XX_GPH3PUD (S5PC1XX_GPH3_BASE + 0x08) ++#define S5PC1XX_GPH3DRV (S5PC1XX_GPH3_BASE + 0x0c) ++#define S5PC1XX_GPH3CONPDN (S5PC1XX_GPH3_BASE + 0x10) ++#define S5PC1XX_GPH3PUDPDN (S5PC1XX_GPH3_BASE + 0x14) ++ ++#define S5PC1XX_GPH3_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPH3_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPH3_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPH3_0_WAKEUP_INT_24 (0x2 << 0) ++#define S5PC1XX_GPH3_0_KEYPAD_ROW_0 (0x3 << 0) ++#define S5PC1XX_GPH3_0_CAM_B_PCLK (0x4 << 0) ++ ++#define S5PC1XX_GPH3_1_WAKEUP_INT_25 (0x2 << 4) ++#define S5PC1XX_GPH3_1_KEYPAD_ROW_1 (0x3 << 4) ++#define S5PC1XX_GPH3_1_CAM_B_VSYNC (0x4 << 4) ++ ++#define S5PC1XX_GPH3_2_WAKEUP_INT_26 (0x2 << 8) ++#define S5PC1XX_GPH3_2_KEYPAD_ROW_2 (0x3 << 8) ++#define S5PC1XX_GPH3_2_CAM_B_HREF (0x4 << 8) ++ ++#define S5PC1XX_GPH3_3_WAKEUP_INT_27 (0x2 << 12) ++#define S5PC1XX_GPH3_3_KEYPAD_ROW_3 (0x3 << 12) ++#define S5PC1XX_GPH3_3_CAM_B_FIELD (0x4 << 12) ++ ++#define S5PC1XX_GPH3_4_WAKEUP_INT_28 (0x2 << 16) ++#define S5PC1XX_GPH3_4_KEYPAD_ROW_4 (0x3 << 16) ++#define S5PC1XX_GPH3_4_CAN0_TX (0x4 << 16) ++ ++#define S5PC1XX_GPH3_5_WAKEUP_INT_29 (0x2 << 20) ++#define S5PC1XX_GPH3_5_KEYPAD_ROW_5 (0x3 << 20) ++#define S5PC1XX_GPH3_5_CAN0_RX (0x4 << 20) ++ ++#define S5PC1XX_GPH3_6_WAKEUP_INT_30 (0x2 << 24) ++#define S5PC1XX_GPH3_6_KEYPAD_ROW_6 (0x3 << 24) ++#define S5PC1XX_GPH3_6_CAN1_TX (0x4 << 24) ++ ++#define S5PC1XX_GPH3_7_WAKEUP_INT_31 (0x2 << 28) ++#define S5PC1XX_GPH3_7_KEYPAD_ROW_7 (0x3 << 28) ++#define S5PC1XX_GPH3_7_CAN1_RX (0x4 << 28) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-i.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-i.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-i.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-i.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,49 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-i.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank I register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPICON (S5PC1XX_GPI_BASE + 0x00) ++#define S5PC1XX_GPIDAT (S5PC1XX_GPI_BASE + 0x04) ++#define S5PC1XX_GPIPUD (S5PC1XX_GPI_BASE + 0x08) ++#define S5PC1XX_GPIDRV (S5PC1XX_GPI_BASE + 0x0c) ++#define S5PC1XX_GPICONPDN (S5PC1XX_GPI_BASE + 0x10) ++#define S5PC1XX_GPIPUDPDN (S5PC1XX_GPI_BASE + 0x14) ++ ++#define S5PC1XX_GPI_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPI_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPI_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPI0_IEM_SCLK (0x2 << 0) ++#define S5PC1XX_GPI0_GPIO_INT15_0 (0xf << 0) ++ ++#define S5PC1XX_GPI1_IEM_SPWI (0x2 << 4) ++#define S5PC1XX_GPI1_GPIO_INT15_1 (0xf << 4) ++ ++#define S5PC1XX_GPI2_BOOT_OPT_0 (0x2 << 8) ++#define S5PC1XX_GPI2_GPIO_INT15_2 (0xf << 8) ++ ++#define S5PC1XX_GPI3_BOOT_OPT_1 (0x2 << 12) ++#define S5PC1XX_GPI3_GPIO_INT15_3 (0xf << 12) ++ ++#define S5PC1XX_GPI4_BOOT_OPT_2 (0x2 << 16) ++#define S5PC1XX_GPI4_GPIO_INT15_4 (0xf << 16) ++ ++#define S5PC1XX_GPI5_BOOT_OPT_3 (0x2 << 20) ++#define S5PC1XX_GPI5_GPIO_INT15_5 (0xf << 20) ++ ++#define S5PC1XX_GPI6_BOOT_OPT_4 (0x2 << 24) ++#define S5PC1XX_GPI6_GPIO_INT15_6 (0xf << 24) ++ ++#define S5PC1XX_GPI7_BOOT_OPT_5 (0x2 << 28) ++#define S5PC1XX_GPI7_GPIO_INT15_7 (0xf << 28) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j0.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j0.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j0.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j0.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,65 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j0.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank J0 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPJ0CON (S5PC1XX_GPJ0_BASE + 0x00) ++#define S5PC1XX_GPJ0DAT (S5PC1XX_GPJ0_BASE + 0x04) ++#define S5PC1XX_GPJ0PUD (S5PC1XX_GPJ0_BASE + 0x08) ++#define S5PC1XX_GPJ0DRV (S5PC1XX_GPJ0_BASE + 0x0c) ++#define S5PC1XX_GPJ0CONPDN (S5PC1XX_GPJ0_BASE + 0x10) ++#define S5PC1XX_GPJ0PUDPDN (S5PC1XX_GPJ0_BASE + 0x14) ++ ++#define S5PC1XX_GPJ0_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPJ0_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPJ0_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPJ0_0_MSM_ADDR_0 (0x2 << 0) ++#define S5PC1XX_GPJ0_0_HSI_TX_DATA (0x3 << 0) ++#define S5PC1XX_GPJ0_0_CF_ADDR_0 (0x4 << 0) ++#define S5PC1XX_GPJ0_0_GPIO_INT16_0 (0xf << 0) ++ ++#define S5PC1XX_GPJ0_1_MSM_ADDR_1 (0x2 << 4) ++#define S5PC1XX_GPJ0_1_HSI_TX_FLAG (0x3 << 4) ++#define S5PC1XX_GPJ0_1_CF_ADDR_1 (0x4 << 4) ++#define S5PC1XX_GPJ0_1_GPIO_INT16_1 (0xf << 4) ++ ++#define S5PC1XX_GPJ0_2_MSM_ADDR_2 (0x2 << 8) ++#define S5PC1XX_GPJ0_2_HSI_TX_WAKE (0x3 << 8) ++#define S5PC1XX_GPJ0_2_CF_ADDR_2 (0x4 << 8) ++#define S5PC1XX_GPJ0_2_GPIO_INT16_2 (0xf << 8) ++ ++#define S5PC1XX_GPJ0_3_MSM_ADDR_3 (0x2 << 12) ++#define S5PC1XX_GPJ0_3_HSI_TX_READY (0x3 << 12) ++#define S5PC1XX_GPJ0_3_CF_IORDY (0x4 << 12) ++#define S5PC1XX_GPJ0_3_GPIO_INT16_3 (0xf << 12) ++ ++#define S5PC1XX_GPJ0_4_MSM_ADDR_4 (0x2 << 16) ++#define S5PC1XX_GPJ0_4_HSI_RX_DATA (0x3 << 16) ++#define S5PC1XX_GPJ0_4_CF_INTRQ (0x4 << 16) ++#define S5PC1XX_GPJ0_4_GPIO_INT16_4 (0xf << 16) ++ ++#define S5PC1XX_GPJ0_5_MSM_ADDR_5 (0x2 << 20) ++#define S5PC1XX_GPJ0_5_HSI_RX_FLAG (0x3 << 20) ++#define S5PC1XX_GPJ0_5_CF_INPACKn (0x4 << 20) ++#define S5PC1XX_GPJ0_5_GPIO_INT16_5 (0xf << 20) ++ ++#define S5PC1XX_GPJ0_6_MSM_ADDR_6 (0x2 << 24) ++#define S5PC1XX_GPJ0_6_HSI_RX_WAKE (0x3 << 24) ++#define S5PC1XX_GPJ0_6_CF_RESET (0x4 << 24) ++#define S5PC1XX_GPJ0_6_GPIO_INT16_6 (0xf << 24) ++ ++#define S5PC1XX_GPJ0_7_MSM_ADDR_7 (0x2 << 28) ++#define S5PC1XX_GPJ0_7_HSI_RX_READY (0x3 << 28) ++#define S5PC1XX_GPJ0_7_CF_REG (0x4 << 28) ++#define S5PC1XX_GPJ0_7_GPIO_INT16_7 (0xf << 28) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j1.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j1.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j1.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j1.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,40 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j1.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank J1 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPJ1CON (S5PC1XX_GPJ1_BASE + 0x00) ++#define S5PC1XX_GPJ1DAT (S5PC1XX_GPJ1_BASE + 0x04) ++#define S5PC1XX_GPJ1PUD (S5PC1XX_GPJ1_BASE + 0x08) ++#define S5PC1XX_GPJ1DRV (S5PC1XX_GPJ1_BASE + 0x0c) ++#define S5PC1XX_GPJ1CONPDN (S5PC1XX_GPJ1_BASE + 0x10) ++#define S5PC1XX_GPJ1PUDPDN (S5PC1XX_GPJ1_BASE + 0x14) ++ ++#define S5PC1XX_GPJ1_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPJ1_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPJ1_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPJ1_0_MSM_ADDR_8 (0x2 << 0) ++#define S5PC1XX_GPJ1_0_GPIO_INT17_0 (0xf << 0) ++ ++#define S5PC1XX_GPJ1_1_MSM_ADDR_9 (0x2 << 4) ++#define S5PC1XX_GPJ1_1_GPIO_INT17_1 (0xf << 4) ++ ++#define S5PC1XX_GPJ1_2_MSM_ADDR_10 (0x2 << 8) ++#define S5PC1XX_GPJ1_2_GPIO_INT17_2 (0xf << 8) ++ ++#define S5PC1XX_GPJ1_3_MSM_ADDR_11 (0x2 << 12) ++#define S5PC1XX_GPJ1_3_GPIO_INT17_3 (0xf << 12) ++ ++#define S5PC1XX_GPJ1_4_MSM_ADDR_12 (0x2 << 16) ++#define S5PC1XX_GPJ1_4_GPIO_INT17_4 (0xf << 16) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j2.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j2.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j2.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j2.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,57 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j2.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank J2 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPJ2CON (S5PC1XX_GPJ2_BASE + 0x00) ++#define S5PC1XX_GPJ2DAT (S5PC1XX_GPJ2_BASE + 0x04) ++#define S5PC1XX_GPJ2PUD (S5PC1XX_GPJ2_BASE + 0x08) ++#define S5PC1XX_GPJ2DRV (S5PC1XX_GPJ2_BASE + 0x0c) ++#define S5PC1XX_GPJ2CONPDN (S5PC1XX_GPJ2_BASE + 0x10) ++#define S5PC1XX_GPJ2PUDPDN (S5PC1XX_GPJ2_BASE + 0x14) ++ ++#define S5PC1XX_GPJ2_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPJ2_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPJ2_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPJ2_0_MSM_DATA_0 (0x2 << 0) ++#define S5PC1XX_GPJ2_0_CF_DATA_0 (0x4 << 0) ++#define S5PC1XX_GPJ2_0_GPIO_INT18_0 (0xf << 0) ++ ++#define S5PC1XX_GPJ2_1_MSM_DATA_1 (0x2 << 4) ++#define S5PC1XX_GPJ2_1_CF_DATA_1 (0x4 << 4) ++#define S5PC1XX_GPJ2_1_GPIO_INT18_1 (0xf << 4) ++ ++#define S5PC1XX_GPJ2_2_MSM_DATA_2 (0x2 << 8) ++#define S5PC1XX_GPJ2_2_CF_DATA_2 (0x4 << 8) ++#define S5PC1XX_GPJ2_2_GPIO_INT18_2 (0xf << 8) ++ ++#define S5PC1XX_GPJ2_3_MSM_DATA_3 (0x2 << 12) ++#define S5PC1XX_GPJ2_3_CF_DATA_3 (0x4 << 12) ++#define S5PC1XX_GPJ2_3_GPIO_INT18_3 (0xf << 12) ++ ++#define S5PC1XX_GPJ2_4_MSM_DATA_4 (0x2 << 16) ++#define S5PC1XX_GPJ2_4_CF_DATA_4 (0x4 << 16) ++#define S5PC1XX_GPJ2_4_GPIO_INT18_4 (0xf << 16) ++ ++#define S5PC1XX_GPJ2_5_MSM_DATA_5 (0x2 << 20) ++#define S5PC1XX_GPJ2_5_CF_DATA_5 (0x4 << 20) ++#define S5PC1XX_GPJ2_5_GPIO_INT18_5 (0xf << 20) ++ ++#define S5PC1XX_GPJ2_6_MSM_DATA_6 (0x2 << 24) ++#define S5PC1XX_GPJ2_6_CF_DATA_6 (0x4 << 24) ++#define S5PC1XX_GPJ2_6_GPIO_INT18_6 (0xf << 24) ++ ++#define S5PC1XX_GPJ2_7_MSM_DATA_7 (0x2 << 28) ++#define S5PC1XX_GPJ2_7_CF_DATA_7 (0x4 << 28) ++#define S5PC1XX_GPJ2_7_GPIO_INT18_7 (0xf << 28) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j3.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j3.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j3.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j3.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,57 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j3.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank J3 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPJ3CON (S5PC1XX_GPJ3_BASE + 0x00) ++#define S5PC1XX_GPJ3DAT (S5PC1XX_GPJ3_BASE + 0x04) ++#define S5PC1XX_GPJ3PUD (S5PC1XX_GPJ3_BASE + 0x08) ++#define S5PC1XX_GPJ3DRV (S5PC1XX_GPJ3_BASE + 0x0c) ++#define S5PC1XX_GPJ3CONPDN (S5PC1XX_GPJ3_BASE + 0x10) ++#define S5PC1XX_GPJ3PUDPDN (S5PC1XX_GPJ3_BASE + 0x14) ++ ++#define S5PC1XX_GPJ3_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPJ3_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPJ3_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPJ3_0_MSM_DATA_8 (0x2 << 0) ++#define S5PC1XX_GPJ3_0_CF_DATA_8 (0x4 << 0) ++#define S5PC1XX_GPJ3_0_GPIO_INT19_0 (0xf << 0) ++ ++#define S5PC1XX_GPJ3_1_MSM_DATA_9 (0x2 << 4) ++#define S5PC1XX_GPJ3_1_CF_DATA_9 (0x4 << 4) ++#define S5PC1XX_GPJ3_1_GPIO_INT19_1 (0xf << 4) ++ ++#define S5PC1XX_GPJ3_2_MSM_DATA_10 (0x2 << 8) ++#define S5PC1XX_GPJ3_2_CF_DATA_10 (0x4 << 8) ++#define S5PC1XX_GPJ3_2_GPIO_INT19_2 (0xf << 8) ++ ++#define S5PC1XX_GPJ3_3_MSM_DATA_11 (0x2 << 12) ++#define S5PC1XX_GPJ3_3_CF_DATA_11 (0x4 << 12) ++#define S5PC1XX_GPJ3_3_GPIO_INT19_3 (0xf << 12) ++ ++#define S5PC1XX_GPJ3_4_MSM_DATA_12 (0x2 << 16) ++#define S5PC1XX_GPJ3_4_CF_DATA_12 (0x4 << 16) ++#define S5PC1XX_GPJ3_4_GPIO_INT19_4 (0xf << 16) ++ ++#define S5PC1XX_GPJ3_5_MSM_DATA_13 (0x2 << 20) ++#define S5PC1XX_GPJ3_5_CF_DATA_13 (0x4 << 20) ++#define S5PC1XX_GPJ3_5_GPIO_INT19_5 (0xf << 20) ++ ++#define S5PC1XX_GPJ3_6_MSM_DATA_14 (0x2 << 24) ++#define S5PC1XX_GPJ3_6_CF_DATA_14 (0x4 << 24) ++#define S5PC1XX_GPJ3_6_GPIO_INT19_6 (0xf << 24) ++ ++#define S5PC1XX_GPJ3_7_MSM_DATA_15 (0x2 << 28) ++#define S5PC1XX_GPJ3_7_CF_DATA_15 (0x4 << 28) ++#define S5PC1XX_GPJ3_7_GPIO_INT19_7 (0xf << 28) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j4.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j4.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j4.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j4.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,41 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-j4.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank J4 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPJ4CON (S5PC1XX_GPJ4_BASE + 0x00) ++#define S5PC1XX_GPJ4DAT (S5PC1XX_GPJ4_BASE + 0x04) ++#define S5PC1XX_GPJ4PUD (S5PC1XX_GPJ4_BASE + 0x08) ++#define S5PC1XX_GPJ4DRV (S5PC1XX_GPJ4_BASE + 0x0c) ++#define S5PC1XX_GPJ4CONPDN (S5PC1XX_GPJ4_BASE + 0x10) ++#define S5PC1XX_GPJ4PUDPDN (S5PC1XX_GPJ4_BASE + 0x14) ++ ++#define S5PC1XX_GPJ4_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPJ4_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPJ4_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPJ4_0_MSM_CSn (0x2 << 0) ++#define S5PC1XX_GPJ4_0_CF_CSn_0 (0x4 << 0) ++#define S5PC1XX_GPJ4_0_GPIO_INT20_0 (0xf << 0) ++ ++#define S5PC1XX_GPJ4_1_MSM_WEn (0x2 << 4) ++#define S5PC1XX_GPJ4_1_CF_CSn_1 (0x4 << 4) ++#define S5PC1XX_GPJ4_1_GPIO_INT20_1 (0xf << 4) ++ ++#define S5PC1XX_GPJ4_2_MSM_Rn (0x2 << 8) ++#define S5PC1XX_GPJ4_2_CF_IORD_CFn (0x4 << 8) ++#define S5PC1XX_GPJ4_2_GPIO_INT20_2 (0xf << 8) ++ ++#define S5PC1XX_GPJ4_3_MSM_IRQn (0x2 << 12) ++#define S5PC1XX_GPJ4_3_CF_IOWR_CFn (0x4 << 12) ++#define S5PC1XX_GPJ4_3_GPIO_INT20_3 (0xf << 12) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k0.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k0.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k0.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k0.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,49 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k0.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank K0 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPK0CON (S5PC1XX_GPK0_BASE + 0x00) ++#define S5PC1XX_GPK0DAT (S5PC1XX_GPK0_BASE + 0x04) ++#define S5PC1XX_GPK0PUD (S5PC1XX_GPK0_BASE + 0x08) ++#define S5PC1XX_GPK0DRV (S5PC1XX_GPK0_BASE + 0x0c) ++#define S5PC1XX_GPK0CONPDN (S5PC1XX_GPK0_BASE + 0x10) ++#define S5PC1XX_GPK0PUDPDN (S5PC1XX_GPK0_BASE + 0x14) ++ ++#define S5PC1XX_GPK0_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPK0_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPK0_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPK0_0_SROM_CSn0 (0x2 << 0) ++ ++#define S5PC1XX_GPK0_1_SROM_CSn1 (0x2 << 4) ++ ++#define S5PC1XX_GPK0_2_SROM_CSn2 (0x2 << 8) ++#define S5PC1XX_GPK0_2_NF_CSn0 (0x3 << 8) ++#define S5PC1XX_GPK0_2_ONENAND_CSn0 (0x5 << 8) ++ ++#define S5PC1XX_GPK0_3_SROM_CSn3 (0x2 << 12) ++#define S5PC1XX_GPK0_3_NF_CSn1 (0x3 << 12) ++#define S5PC1XX_GPK0_3_ONENAND_CSn1 (0x5 << 12) ++#define S5PC1XX_GPK0_3_MASK (0xf << 12) ++ ++#define S5PC1XX_GPK0_4_SROM_CSn4 (0x2 << 16) ++#define S5PC1XX_GPK0_4_NF_CSn2 (0x3 << 16) ++#define S5PC1XX_GPK0_4_CF_CSn0 (0x4 << 16) ++ ++#define S5PC1XX_GPK0_5_SROM_CSn5 (0x2 << 20) ++#define S5PC1XX_GPK0_5_NF_CSn3 (0x3 << 20) ++#define S5PC1XX_GPK0_5_CF_CSn1 (0x4 << 20) ++ ++#define S5PC1XX_GPK0_6_EBI_OEn (0x2 << 24) ++ ++#define S5PC1XX_GPK0_7_EBI_WEn (0x2 << 28) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k1.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k1.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k1.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k1.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,32 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k1.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank K1 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPK1CON (S5PC1XX_GPK1_BASE + 0x00) ++#define S5PC1XX_GPK1DAT (S5PC1XX_GPK1_BASE + 0x04) ++#define S5PC1XX_GPK1PUD (S5PC1XX_GPK1_BASE + 0x08) ++#define S5PC1XX_GPK1DRV (S5PC1XX_GPK1_BASE + 0x0c) ++#define S5PC1XX_GPK1CONPDN (S5PC1XX_GPK1_BASE + 0x10) ++#define S5PC1XX_GPK1PUDPDN (S5PC1XX_GPK1_BASE + 0x14) ++ ++#define S5PC1XX_GPK1_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPK1_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPK1_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPK1_0_EBI_BEn0 (0x2 << 0) ++#define S5PC1XX_GPK1_1_EBI_BEn1 (0x2 << 4) ++#define S5PC1XX_GPK1_2_SROM_WAITn (0x2 << 8) ++#define S5PC1XX_GPK1_3_EBI_DATA_RDn (0x2 << 12) ++#define S5PC1XX_GPK1_4_CF_OEn (0x2 << 16) ++#define S5PC1XX_GPK1_5_CF_WEn (0x2 << 20) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k2.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k2.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k2.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k2.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,45 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k2.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank K2 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPK2CON (S5PC1XX_GPK2_BASE + 0x00) ++#define S5PC1XX_GPK2DAT (S5PC1XX_GPK2_BASE + 0x04) ++#define S5PC1XX_GPK2PUD (S5PC1XX_GPK2_BASE + 0x08) ++#define S5PC1XX_GPK2DRV (S5PC1XX_GPK2_BASE + 0x0c) ++#define S5PC1XX_GPK2CONPDN (S5PC1XX_GPK2_BASE + 0x10) ++#define S5PC1XX_GPK2PUDPDN (S5PC1XX_GPK2_BASE + 0x14) ++ ++#define S5PC1XX_GPK2_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPK2_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPK2_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPK2_0_NF_CLE (0x3 << 0) ++#define S5PC1XX_GPK2_0_ONAND_ADDRVALID (0x5 << 0) ++ ++#define S5PC1XX_GPK2_1_NF_ALE (0x3 << 4) ++#define S5PC1XX_GPK2_1_ONAND_SMCLK (0x5 << 4) ++ ++#define S5PC1XX_GPK2_2_NF_FWEn (0x3 << 8) ++#define S5PC1XX_GPK2_2_ONAND_RPn (0x5 << 8) ++ ++#define S5PC1XX_GPK2_3_NF_FREn (0x3 << 12) ++ ++#define S5PC1XX_GPK2_4_NF_RnB_0 (0x2 << 16) ++#define S5PC1XX_GPK2_4_ONAND_INT_0 (0x5 << 16) ++ ++#define S5PC1XX_GPK2_5_NF_RnB_1 (0x2 << 20) ++#define S5PC1XX_GPK2_5_ONAND_INT_1 (0x5 << 20) ++ ++#define S5PC1XX_GPK2_6_NF_RnB_2 (0x2 << 24) ++ ++#define S5PC1XX_GPK2_7_NF_RnB_3 (0x2 << 28) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k3.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k3.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k3.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k3.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,33 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-k3.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank K3 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_GPK3CON (S5PC1XX_GPK3_BASE + 0x00) ++#define S5PC1XX_GPK3DAT (S5PC1XX_GPK3_BASE + 0x04) ++#define S5PC1XX_GPK3PUD (S5PC1XX_GPK3_BASE + 0x08) ++#define S5PC1XX_GPK3DRV (S5PC1XX_GPK3_BASE + 0x0c) ++#define S5PC1XX_GPK3CONPDN (S5PC1XX_GPK3_BASE + 0x10) ++#define S5PC1XX_GPK3PUDPDN (S5PC1XX_GPK3_BASE + 0x14) ++ ++#define S5PC1XX_GPK3_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_GPK3_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_GPK3_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_GPK3_0_CF_IORDY (0x2 << 0) ++#define S5PC1XX_GPK3_1_CF_INTRQ (0x2 << 4) ++#define S5PC1XX_GPK3_2_CF_RESET (0x2 << 8) ++#define S5PC1XX_GPK3_3_CF_INPACKn (0x2 << 12) ++#define S5PC1XX_GPK3_4_CF_REG (0x2 << 16) ++#define S5PC1XX_GPK3_5_CF_CDn (0x2 << 20) ++#define S5PC1XX_GPK3_6_CF_IORD_CFn (0x2 << 24) ++#define S5PC1XX_GPK3_7_CF_IOWR_CFn (0x2 << 28) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp00.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp00.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp00.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp00.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,34 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp00.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank MP00 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_MP00CON (S5PC1XX_MP00_BASE + 0x00) ++#define S5PC1XX_MP00DAT (S5PC1XX_MP00_BASE + 0x04) ++#define S5PC1XX_MP00PUD (S5PC1XX_MP00_BASE + 0x08) ++#define S5PC1XX_MP00DRV (S5PC1XX_MP00_BASE + 0x0c) ++#define S5PC1XX_MP00CONPDN (S5PC1XX_MP00_BASE + 0x10) ++#define S5PC1XX_MP00PUDPDN (S5PC1XX_MP00_BASE + 0x14) ++ ++#define S5PC1XX_MP00_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_MP00_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_MP00_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_MP00_0_EBI_ADDR_0 (0x2 << 0) ++#define S5PC1XX_MP00_1_EBI_ADDR_1 (0x2 << 4) ++#define S5PC1XX_MP00_2_EBI_ADDR_2 (0x2 << 8) ++#define S5PC1XX_MP00_3_EBI_ADDR_3 (0x2 << 12) ++#define S5PC1XX_MP00_4_EBI_ADDR_4 (0x2 << 16) ++#define S5PC1XX_MP00_5_EBI_ADDR_5 (0x2 << 20) ++#define S5PC1XX_MP00_6_EBI_ADDR_6 (0x2 << 24) ++#define S5PC1XX_MP00_7_EBI_ADDR_7 (0x2 << 28) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp01.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp01.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp01.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp01.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,33 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp01.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank MP01 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_MP01CON (S5PC1XX_MP01_BASE + 0x00) ++#define S5PC1XX_MP01DAT (S5PC1XX_MP01_BASE + 0x04) ++#define S5PC1XX_MP01PUD (S5PC1XX_MP01_BASE + 0x08) ++#define S5PC1XX_MP01DRV (S5PC1XX_MP01_BASE + 0x0c) ++#define S5PC1XX_MP01CONPDN (S5PC1XX_MP01_BASE + 0x10) ++#define S5PC1XX_MP01PUDPDN (S5PC1XX_MP01_BASE + 0x14) ++ ++#define S5PC1XX_MP01_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_MP01_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_MP01_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_MP01_0_EBI_ADDR_8 (0x2 << 0) ++#define S5PC1XX_MP01_1_EBI_ADDR_9 (0x2 << 4) ++#define S5PC1XX_MP01_2_EBI_ADDR_10 (0x2 << 8) ++#define S5PC1XX_MP01_3_EBI_ADDR_11 (0x2 << 12) ++#define S5PC1XX_MP01_4_EBI_ADDR_12 (0x2 << 16) ++#define S5PC1XX_MP01_5_EBI_ADDR_13 (0x2 << 20) ++#define S5PC1XX_MP01_6_EBI_ADDR_14 (0x2 << 24) ++#define S5PC1XX_MP01_7_EBI_ADDR_15 (0x2 << 28) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp02.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp02.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp02.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp02.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,34 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp02.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank MP02 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_MP02CON (S5PC1XX_MP02_BASE + 0x00) ++#define S5PC1XX_MP02DAT (S5PC1XX_MP02_BASE + 0x04) ++#define S5PC1XX_MP02PUD (S5PC1XX_MP02_BASE + 0x08) ++#define S5PC1XX_MP02DRV (S5PC1XX_MP02_BASE + 0x0c) ++#define S5PC1XX_MP02CONPDN (S5PC1XX_MP02_BASE + 0x10) ++#define S5PC1XX_MP02PUDPDN (S5PC1XX_MP02_BASE + 0x14) ++ ++#define S5PC1XX_MP02_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_MP02_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_MP02_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_MP02_0_EBI_ADDR_16 (0x2 << 0) ++#define S5PC1XX_MP02_1_EBI_ADDR_17 (0x2 << 4) ++#define S5PC1XX_MP02_2_EBI_ADDR_18 (0x2 << 8) ++#define S5PC1XX_MP02_3_EBI_ADDR_19 (0x2 << 12) ++#define S5PC1XX_MP02_4_EBI_ADDR_20 (0x2 << 16) ++#define S5PC1XX_MP02_5_EBI_DATA_0 (0x2 << 20) ++#define S5PC1XX_MP02_6_EBI_DATA_1 (0x2 << 24) ++#define S5PC1XX_MP02_7_EBI_DATA_2 (0x2 << 28) ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp03.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp03.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp03.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp03.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,33 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp03.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank MP03 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_MP03CON (S5PC1XX_MP03_BASE + 0x00) ++#define S5PC1XX_MP03DAT (S5PC1XX_MP03_BASE + 0x04) ++#define S5PC1XX_MP03PUD (S5PC1XX_MP03_BASE + 0x08) ++#define S5PC1XX_MP03DRV (S5PC1XX_MP03_BASE + 0x0c) ++#define S5PC1XX_MP03CONPDN (S5PC1XX_MP03_BASE + 0x10) ++#define S5PC1XX_MP03PUDPDN (S5PC1XX_MP03_BASE + 0x14) ++ ++#define S5PC1XX_MP03_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_MP03_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_MP03_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_MP03_0_EBI_DATA_3 (0x2 << 0) ++#define S5PC1XX_MP03_1_EBI_DATA_4 (0x2 << 4) ++#define S5PC1XX_MP03_2_EBI_DATA_5 (0x2 << 8) ++#define S5PC1XX_MP03_3_EBI_DATA_6 (0x2 << 12) ++#define S5PC1XX_MP03_4_EBI_DATA_7 (0x2 << 16) ++#define S5PC1XX_MP03_5_EBI_DATA_8 (0x2 << 20) ++#define S5PC1XX_MP03_6_EBI_DATA_9 (0x2 << 24) ++#define S5PC1XX_MP03_7_EBI_DATA_10 (0x2 << 28) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp04.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp04.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp04.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp04.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,30 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-bank-mp04.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * GPIO Bank MP04 register and configuration definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5PC1XX_MP04CON (S5PC1XX_MP04_BASE + 0x00) ++#define S5PC1XX_MP04DAT (S5PC1XX_MP04_BASE + 0x04) ++#define S5PC1XX_MP04PUD (S5PC1XX_MP04_BASE + 0x08) ++#define S5PC1XX_MP04DRV (S5PC1XX_MP04_BASE + 0x0c) ++#define S5PC1XX_MP04CONPDN (S5PC1XX_MP04_BASE + 0x10) ++#define S5PC1XX_MP04PUDPDN (S5PC1XX_MP04_BASE + 0x14) ++ ++#define S5PC1XX_MP04_CONMASK(__gpio) (0xf << ((__gpio) * 4)) ++#define S5PC1XX_MP04_INPUT(__gpio) (0x0 << ((__gpio) * 4)) ++#define S5PC1XX_MP04_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) ++ ++#define S5PC1XX_MP04_0_EBI_DATA_11 (0x2 << 0) ++#define S5PC1XX_MP04_1_EBI_DATA_12 (0x2 << 4) ++#define S5PC1XX_MP04_2_EBI_DATA_13 (0x2 << 8) ++#define S5PC1XX_MP04_3_EBI_DATA_14 (0x2 << 12) ++#define S5PC1XX_MP04_4_EBI_DATA_15 (0x2 << 16) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/irqs.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/irqs.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/irqs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/irqs.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,223 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/irqs.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5PC1XX - Common IRQ support ++ */ ++ ++#ifndef __ASM_PLAT_S5PC1XX_IRQS_H ++#define __ASM_PLAT_S5PC1XX_IRQS_H __FILE__ ++ ++/* we keep the first set of CPU IRQs out of the range of ++ * the ISA space, so that the PC104 has them to itself ++ * and we don't end up having to do horrible things to the ++ * standard ISA drivers.... ++ * ++ * note, since we're using the VICs, our start must be a ++ * mulitple of 32 to allow the common code to work ++ */ ++ ++#define S3C_IRQ_OFFSET (32) ++ ++#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) ++ ++#define S3C_VIC0_BASE S3C_IRQ(0) ++#define S3C_VIC1_BASE S3C_IRQ(32) ++#define S3C_VIC2_BASE S3C_IRQ(64) ++ ++/* UART interrupts, each UART has 4 intterupts per channel so ++ * use the space between the ISA and S3C main interrupts. Note, these ++ * are not in the same order as the S3C24XX series! */ ++ ++#define IRQ_S3CUART_BASE0 (16) ++#define IRQ_S3CUART_BASE1 (20) ++#define IRQ_S3CUART_BASE2 (24) ++#define IRQ_S3CUART_BASE3 (28) ++ ++#define UART_IRQ_RXD (0) ++#define UART_IRQ_ERR (1) ++#define UART_IRQ_TXD (2) ++#define UART_IRQ_MODEM (3) ++ ++#define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD) ++#define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD) ++#define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR) ++ ++#define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD) ++#define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD) ++#define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR) ++ ++#define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD) ++#define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD) ++#define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR) ++ ++#define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD) ++#define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD) ++#define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR) ++ ++/* VIC based IRQs */ ++ ++#define S5PC1XX_IRQ_VIC0(x) (S3C_VIC0_BASE + (x)) ++#define S5PC1XX_IRQ_VIC1(x) (S3C_VIC1_BASE + (x)) ++#define S5PC1XX_IRQ_VIC2(x) (S3C_VIC2_BASE + (x)) ++ ++/* ++ * VIC0: system, DMA, timer ++ */ ++#define IRQ_EINT0 S5PC1XX_IRQ_VIC0(0) ++#define IRQ_EINT1 S5PC1XX_IRQ_VIC0(1) ++#define IRQ_EINT2 S5PC1XX_IRQ_VIC0(2) ++#define IRQ_EINT3 S5PC1XX_IRQ_VIC0(3) ++#define IRQ_EINT4 S5PC1XX_IRQ_VIC0(4) ++#define IRQ_EINT5 S5PC1XX_IRQ_VIC0(5) ++#define IRQ_EINT6 S5PC1XX_IRQ_VIC0(6) ++#define IRQ_EINT7 S5PC1XX_IRQ_VIC0(7) ++#define IRQ_EINT8 S5PC1XX_IRQ_VIC0(8) ++#define IRQ_EINT9 S5PC1XX_IRQ_VIC0(9) ++#define IRQ_EINT10 S5PC1XX_IRQ_VIC0(10) ++#define IRQ_EINT11 S5PC1XX_IRQ_VIC0(11) ++#define IRQ_EINT12 S5PC1XX_IRQ_VIC0(12) ++#define IRQ_EINT13 S5PC1XX_IRQ_VIC0(13) ++#define IRQ_EINT14 S5PC1XX_IRQ_VIC0(14) ++#define IRQ_EINT15 S5PC1XX_IRQ_VIC0(15) ++#define IRQ_EINT16_31 S5PC1XX_IRQ_VIC0(16) ++#define IRQ_BATF S5PC1XX_IRQ_VIC0(17) ++#define IRQ_MDMA S5PC1XX_IRQ_VIC0(18) ++#define IRQ_PDMA0 S5PC1XX_IRQ_VIC0(19) ++#define IRQ_PDMA1 S5PC1XX_IRQ_VIC0(20) ++#define IRQ_TIMER0 S5PC1XX_IRQ_VIC0(21) ++#define IRQ_TIMER1 S5PC1XX_IRQ_VIC0(22) ++#define IRQ_TIMER2 S5PC1XX_IRQ_VIC0(23) ++#define IRQ_TIMER3 S5PC1XX_IRQ_VIC0(24) ++#define IRQ_TIMER4 S5PC1XX_IRQ_VIC0(25) ++#define IRQ_SYSTIMER S5PC1XX_IRQ_VIC0(26) ++#define IRQ_WDT S5PC1XX_IRQ_VIC0(27) ++#define IRQ_RTC_ALARM S5PC1XX_IRQ_VIC0(28) ++#define IRQ_RTC_TIC S5PC1XX_IRQ_VIC0(29) ++#define IRQ_GPIOINT S5PC1XX_IRQ_VIC0(30) ++ ++/* ++ * VIC1: ARM, power, memory, connectivity ++ */ ++#define IRQ_CORTEX0 S5PC1XX_IRQ_VIC1(0) ++#define IRQ_CORTEX1 S5PC1XX_IRQ_VIC1(1) ++#define IRQ_CORTEX2 S5PC1XX_IRQ_VIC1(2) ++#define IRQ_CORTEX3 S5PC1XX_IRQ_VIC1(3) ++#define IRQ_CORTEX4 S5PC1XX_IRQ_VIC1(4) ++#define IRQ_IEMAPC S5PC1XX_IRQ_VIC1(5) ++#define IRQ_IEMIEC S5PC1XX_IRQ_VIC1(6) ++#define IRQ_ONENAND S5PC1XX_IRQ_VIC1(7) ++#define IRQ_NFC S5PC1XX_IRQ_VIC1(8) ++#define IRQ_CFC S5PC1XX_IRQ_VIC1(9) ++#define IRQ_UART0 S5PC1XX_IRQ_VIC1(10) ++#define IRQ_UART1 S5PC1XX_IRQ_VIC1(11) ++#define IRQ_UART2 S5PC1XX_IRQ_VIC1(12) ++#define IRQ_UART3 S5PC1XX_IRQ_VIC1(13) ++#define IRQ_IIC S5PC1XX_IRQ_VIC1(14) ++#define IRQ_SPI0 S5PC1XX_IRQ_VIC1(15) ++#define IRQ_SPI1 S5PC1XX_IRQ_VIC1(16) ++#define IRQ_SPI2 S5PC1XX_IRQ_VIC1(17) ++#define IRQ_IRDA S5PC1XX_IRQ_VIC1(18) ++#define IRQ_CAN0 S5PC1XX_IRQ_VIC1(19) ++#define IRQ_CAN1 S5PC1XX_IRQ_VIC1(20) ++#define IRQ_HSIRX S5PC1XX_IRQ_VIC1(21) ++#define IRQ_HSITX S5PC1XX_IRQ_VIC1(22) ++#define IRQ_UHOST S5PC1XX_IRQ_VIC1(23) ++#define IRQ_OTG S5PC1XX_IRQ_VIC1(24) ++#define IRQ_MSM S5PC1XX_IRQ_VIC1(25) ++#define IRQ_HSMMC0 S5PC1XX_IRQ_VIC1(26) ++#define IRQ_HSMMC1 S5PC1XX_IRQ_VIC1(27) ++#define IRQ_HSMMC2 S5PC1XX_IRQ_VIC1(28) ++#define IRQ_MIPICSI S5PC1XX_IRQ_VIC1(29) ++#define IRQ_MIPIDSI S5PC1XX_IRQ_VIC1(30) ++ ++/* ++ * VIC2: multimedia, audio, security ++ */ ++#define IRQ_LCD0 S5PC1XX_IRQ_VIC2(0) ++#define IRQ_LCD1 S5PC1XX_IRQ_VIC2(1) ++#define IRQ_LCD2 S5PC1XX_IRQ_VIC2(2) ++#define IRQ_LCD3 S5PC1XX_IRQ_VIC2(3) ++#define IRQ_ROTATOR S5PC1XX_IRQ_VIC2(4) ++#define IRQ_FIMC0 S5PC1XX_IRQ_VIC2(5) ++#define IRQ_FIMC1 S5PC1XX_IRQ_VIC2(6) ++#define IRQ_FIMC2 S5PC1XX_IRQ_VIC2(7) ++#define IRQ_JPEG S5PC1XX_IRQ_VIC2(8) ++#define IRQ_2D S5PC1XX_IRQ_VIC2(9) ++#define IRQ_3D S5PC1XX_IRQ_VIC2(10) ++#define IRQ_MIXER S5PC1XX_IRQ_VIC2(11) ++#define IRQ_HDMI S5PC1XX_IRQ_VIC2(12) ++#define IRQ_IIC1 S5PC1XX_IRQ_VIC2(13) ++#define IRQ_MFC S5PC1XX_IRQ_VIC2(14) ++#define IRQ_TVENC S5PC1XX_IRQ_VIC2(15) ++#define IRQ_I2S0 S5PC1XX_IRQ_VIC2(16) ++#define IRQ_I2S1 S5PC1XX_IRQ_VIC2(17) ++#define IRQ_I2S2 S5PC1XX_IRQ_VIC2(18) ++#define IRQ_AC97 S5PC1XX_IRQ_VIC2(19) ++#define IRQ_PCM0 S5PC1XX_IRQ_VIC2(20) ++#define IRQ_PCM1 S5PC1XX_IRQ_VIC2(21) ++#define IRQ_SPDIF S5PC1XX_IRQ_VIC2(22) ++#define IRQ_ADC S5PC1XX_IRQ_VIC2(23) ++#define IRQ_PENDN S5PC1XX_IRQ_VIC2(24) ++#define IRQ_TC IRQ_PENDN ++#define IRQ_KEYPAD S5PC1XX_IRQ_VIC2(25) ++#define IRQ_CG S5PC1XX_IRQ_VIC2(26) ++#define IRQ_SEC S5PC1XX_IRQ_VIC2(27) ++#define IRQ_SECRX S5PC1XX_IRQ_VIC2(28) ++#define IRQ_SECTX S5PC1XX_IRQ_VIC2(29) ++#define IRQ_SDMIRQ S5PC1XX_IRQ_VIC2(30) ++#define IRQ_SDMFIQ S5PC1XX_IRQ_VIC2(31) ++ ++#define S3C_IRQ_EINT_BASE IRQ_SDMFIQ+1 ++ ++#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) ++#define IRQ_EINT(x) S3C_EINT(x) ++ ++#define NR_IRQS (IRQ_EINT(31)+1) ++ ++#if 0 ++/* Next the external interrupt groups. These are similar to the IRQ_EINT(x) ++ * that they are sourced from the GPIO pins but with a different scheme for ++ * priority and source indication. ++ * ++ * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO ++ * interrupts, but for historical reasons they are kept apart from these ++ * next interrupts. ++ * ++ * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the ++ * machine specific support files. ++ */ ++ ++#define IRQ_EINT_GROUP1_NR (15) ++#define IRQ_EINT_GROUP2_NR (8) ++#define IRQ_EINT_GROUP3_NR (5) ++#define IRQ_EINT_GROUP4_NR (14) ++#define IRQ_EINT_GROUP5_NR (7) ++#define IRQ_EINT_GROUP6_NR (10) ++#define IRQ_EINT_GROUP7_NR (16) ++#define IRQ_EINT_GROUP8_NR (15) ++#define IRQ_EINT_GROUP9_NR (9) ++ ++#define IRQ_EINT_GROUP_BASE S3C_EINT(28) ++#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00) ++#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) ++#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) ++#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR) ++#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR) ++#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) ++#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) ++#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR) ++#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR) ++ ++#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##__BASE + (x)) ++ ++/* Set the default NR_IRQS */ ++ ++#define NR_IRQS (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) ++#endif ++ ++#endif /* __ASM_PLAT_S5PC1XX_IRQS_H */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/media.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/media.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/media.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/media.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,38 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/media.h ++ * ++ * Copyright 2009 Samsung Electronics ++ * Jinsung Yang ++ * http://samsungsemi.com/ ++ * ++ * Samsung Media device descriptions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef _S3C_MEDIA_H ++#define _S3C_MEDIA_H ++ ++#include ++ ++#define S3C_MDEV_FIMC 0 ++#define S3C_MDEV_POST 1 ++#define S3C_MDEV_TV 2 ++#define S3C_MDEV_MFC 3 ++#define S3C_MDEV_JPEG 4 ++#define S3C_MDEV_CMM 5 ++#define S3C_MDEV_MAX 6 ++ ++struct s3c_media_device { ++ int id; ++ const char *name; ++ size_t memsize; ++ dma_addr_t paddr; ++}; ++ ++extern dma_addr_t s3c_get_media_memory(int dev_id); ++extern size_t s3c_get_media_memsize(int dev_id); ++ ++#endif ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/pll.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/pll.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/pll.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/pll.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,40 @@ ++/* arch/arm/plat-s5pc1xx/include/plat/pll.h ++ * ++ * Copyright 2008 Samsung Electronics ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5PC1XX PLL code ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#define S5P_PLL_MDIV_MASK ((1 << (25-16+1)) - 1) ++#define S5P_PLL_PDIV_MASK ((1 << (13-8+1)) - 1) ++#define S5P_PLL_SDIV_MASK ((1 << (2-0+1)) - 1) ++#define S5P_PLL_MDIV_SHIFT (16) ++#define S5P_PLL_PDIV_SHIFT (8) ++#define S5P_PLL_SDIV_SHIFT (0) ++ ++#include ++ ++static inline unsigned long s5pc1xx_get_pll(unsigned long baseclk, ++ u32 pllcon) ++{ ++ u32 mdiv, pdiv, sdiv; ++ u64 fvco = baseclk; ++ ++ mdiv = (pllcon >> S5P_PLL_MDIV_SHIFT) & S5P_PLL_MDIV_MASK; ++ pdiv = (pllcon >> S5P_PLL_PDIV_SHIFT) & S5P_PLL_PDIV_MASK; ++ sdiv = (pllcon >> S5P_PLL_SDIV_SHIFT) & S5P_PLL_SDIV_MASK; ++ ++ fvco *= mdiv ; ++ do_div(fvco, (pdiv << sdiv)); ++ ++ return (unsigned long)fvco; ++ ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/pm.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/pm.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/pm.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/pm.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,74 @@ ++/* linux/include/asm-arm/plat-s3c24xx/pm.h ++ * ++ * Copyright (c) 2004 Simtec Electronics ++ * Written by Ben Dooks, ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifdef CONFIG_PM ++ ++extern __init int s5pc1xx_pm_init(void); ++ ++#else ++ ++static inline int s5pc1xx_pm_init(void) ++{ ++ return 0; ++} ++#endif ++ ++/* configuration for the IRQ mask over sleep */ ++extern unsigned long s5pc1xx_irqwake_intmask; ++extern unsigned long s5pc1xx_irqwake_eintmask; ++ ++/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */ ++extern unsigned long s5pc1xx_irqwake_intallow; ++extern unsigned long s5pc1xx_irqwake_eintallow; ++ ++/* per-cpu sleep functions */ ++ ++extern void (*pm_cpu_prep)(void); ++extern void (*pm_cpu_sleep)(void); ++ ++/* Flags for PM Control */ ++ ++extern unsigned long s5pc100_pm_flags; ++ ++/* from sleep.S */ ++ ++extern int s5pc100_cpu_save(unsigned long *saveblk); ++extern void s5pc100_cpu_suspend(void); ++extern void s5pc100_cpu_resume(void); ++ ++extern unsigned long s5pc100_sleep_save_phys; ++ ++/* sleep save info */ ++ ++struct sleep_save { ++ void __iomem *reg; ++ unsigned long val; ++}; ++ ++struct sleep_save_phy { ++ unsigned long reg; ++ unsigned long val; ++}; ++ ++#define SAVE_ITEM(x) \ ++ { .reg = (x) } ++ ++extern void s5pc1xx_pm_do_save_phy(struct sleep_save_phy *ptr, struct platform_device *pdev, int count); ++extern void s5pc1xx_pm_do_restore_phy(struct sleep_save_phy *ptr, struct platform_device *pdev, int count); ++extern void s5pc1xx_pm_do_save(struct sleep_save *ptr, int count); ++extern void s5pc1xx_pm_do_restore(struct sleep_save *ptr, int count); ++ ++#ifdef CONFIG_PM ++extern int s5pc1xx_irq_suspend(struct sys_device *dev, pm_message_t state); ++extern int s5pc1xx_irq_resume(struct sys_device *dev); ++#else ++#define s5pc1xx_irq_suspend NULL ++#define s5pc1xx_irq_resume NULL ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,422 @@ ++/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h ++ * ++ * Copyright 2008 Samsung Electronics ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5PC1XX clock register definitions ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __PLAT_REGS_CLOCK_H ++#define __PLAT_REGS_CLOCK_H __FILE__ ++ ++#define S5P_CLKREG(x) (S3C_VA_SYS + (x)) ++ ++#define S5P_APLL_LOCK S5P_CLKREG(0x00) ++#define S5P_MPLL_LOCK S5P_CLKREG(0x04) ++#define S5P_EPLL_LOCK S5P_CLKREG(0x08) ++#define S5P_HPLL_LOCK S5P_CLKREG(0x0C) ++ ++#define S5P_APLL_CON S5P_CLKREG(0x100) ++#define S5P_MPLL_CON S5P_CLKREG(0x104) ++#define S5P_EPLL_CON S5P_CLKREG(0x108) ++#define S5P_HPLL_CON S5P_CLKREG(0x10C) ++ ++#define S5P_CLK_SRC0 S5P_CLKREG(0x200) ++#define S5P_CLK_SRC1 S5P_CLKREG(0x204) ++#define S5P_CLK_SRC2 S5P_CLKREG(0x208) ++#define S5P_CLK_SRC3 S5P_CLKREG(0x20C) ++ ++#define S5P_CLK_DIV0 S5P_CLKREG(0x300) ++#define S5P_CLK_DIV1 S5P_CLKREG(0x304) ++#define S5P_CLK_DIV2 S5P_CLKREG(0x308) ++#define S5P_CLK_DIV3 S5P_CLKREG(0x30C) ++#define S5P_CLK_DIV4 S5P_CLKREG(0x310) ++ ++#define S5P_CLK_OUT S5P_CLKREG(0x400) ++ ++#define S5P_CLKGATE_D00 S5P_CLKREG(0x500) ++#define S5P_CLKGATE_D01 S5P_CLKREG(0x504) ++#define S5P_CLKGATE_D02 S5P_CLKREG(0x508) ++ ++#define S5P_CLKGATE_D10 S5P_CLKREG(0x520) ++#define S5P_CLKGATE_D11 S5P_CLKREG(0x524) ++#define S5P_CLKGATE_D12 S5P_CLKREG(0x528) ++#define S5P_CLKGATE_D13 S5P_CLKREG(0x52C) ++#define S5P_CLKGATE_D14 S5P_CLKREG(0x530) ++#define S5P_CLKGATE_D15 S5P_CLKREG(0x534) ++ ++#define S5P_CLKGATE_D20 S5P_CLKREG(0x540) ++ ++#define S5P_SCLKGATE0 S5P_CLKREG(0x560) ++#define S5P_SCLKGATE1 S5P_CLKREG(0x564) ++ ++#define S5P_OTHERS S5P_CLKREG(0x8200) ++ ++#define S5P_EPLL_EN (1<<31) ++#define S5P_EPLL_MASK 0xffffffff ++#define S5P_EPLLVAL(_m,_p,_s) ((_m) << 16 | ((_p) << 8) | ((_s))) ++ ++/* CLKSRC0 */ ++#define S5P_CLKSRC0_APLL_MASK (0x1<<0) ++#define S5P_CLKSRC0_APLL_SHIFT (0) ++#define S5P_CLKSRC0_MPLL_MASK (0x1<<4) ++#define S5P_CLKSRC0_MPLL_SHIFT (4) ++#define S5P_CLKSRC0_EPLL_MASK (0x1<<8) ++#define S5P_CLKSRC0_EPLL_SHIFT (8) ++#define S5P_CLKSRC0_HPLL_MASK (0x1<<12) ++#define S5P_CLKSRC0_HPLL_SHIFT (12) ++#define S5P_CLKSRC0_AMMUX_MASK (0x1<<16) ++#define S5P_CLKSRC0_AMMUX_SHIFT (16) ++#define S5P_CLKSRC0_HREF_MASK (0x1<<20) ++#define S5P_CLKSRC0_HREF_SHIFT (20) ++#define S5P_CLKSRC0_ONENAND_MASK (0x1<<24) ++#define S5P_CLKSRC0_ONENAND_SHIFT (24) ++ ++/* CLKSRC1 */ ++#define S5P_CLKSRC1_UART_MASK (0x1<<0) ++#define S5P_CLKSRC1_UART_SHIFT (0) ++#define S5P_CLKSRC1_SPI0_MASK (0x3<<4) ++#define S5P_CLKSRC1_SPI0_SHIFT (4) ++#define S5P_CLKSRC1_SPI1_MASK (0x3<<8) ++#define S5P_CLKSRC1_SPI1_SHIFT (8) ++#define S5P_CLKSRC1_SPI2_MASK (0x3<<12) ++#define S5P_CLKSRC1_SPI2_SHIFT (12) ++#define S5P_CLKSRC1_IRDA_MASK (0x3<<16) ++#define S5P_CLKSRC1_IRDA_SHIFT (16) ++#define S5P_CLKSRC1_UHOST_MASK (0x3<<20) ++#define S5P_CLKSRC1_UHOST_SHIFT (20) ++#define S5P_CLKSRC1_CLK48M_MASK (0x1<<24) ++#define S5P_CLKSRC1_CLK48M_SHIFT (24) ++ ++/* CLKSRC2 */ ++#define S5P_CLKSRC2_MMC0_MASK (0x3<<0) ++#define S5P_CLKSRC2_MMC0_SHIFT (0) ++#define S5P_CLKSRC2_MMC1_MASK (0x3<<4) ++#define S5P_CLKSRC2_MMC1_SHIFT (4) ++#define S5P_CLKSRC2_MMC2_MASK (0x3<<8) ++#define S5P_CLKSRC2_MMC2_SHIFT (8) ++#define S5P_CLKSRC2_LCD_MASK (0x3<<12) ++#define S5P_CLKSRC2_LCD_SHIFT (12) ++#define S5P_CLKSRC2_FIMC0_MASK (0x3<<16) ++#define S5P_CLKSRC2_FIMC0_SHIFT (16) ++#define S5P_CLKSRC2_FIMC1_MASK (0x3<<20) ++#define S5P_CLKSRC2_FIMC1_SHIFT (20) ++#define S5P_CLKSRC2_FIMC2_MASK (0x3<<24) ++#define S5P_CLKSRC2_FIMC2_SHIFT (24) ++#define S5P_CLKSRC2_MIXER_MASK (0x3<<28) ++#define S5P_CLKSRC2_MIXER_SHIFT (28) ++ ++/* CLKSRC3 */ ++#define S5P_CLKSRC3_PWI_MASK (0x3<<0) ++#define S5P_CLKSRC3_PWI_SHIFT (0) ++#define S5P_CLKSRC3_HCLKD2_MASK (0x1<<4) ++#define S5P_CLKSRC3_HCLKD2_SHIFT (4) ++#define S5P_CLKSRC3_I2SD2_MASK (0x3<<8) ++#define S5P_CLKSRC3_I2SD2_SHIFT (8) ++#define S5P_CLKSRC3_AUDIO0_MASK (0x7<<12) ++#define S5P_CLKSRC3_AUDIO0_SHIFT (12) ++#define S5P_CLKSRC3_AUDIO1_MASK (0x7<<16) ++#define S5P_CLKSRC3_AUDIO1_SHIFT (16) ++#define S5P_CLKSRC3_AUDIO2_MASK (0x7<<20) ++#define S5P_CLKSRC3_AUDIO2_SHIFT (20) ++#define S5P_CLKSRC3_SPDIF_MASK (0x3<<24) ++#define S5P_CLKSRC3_SPDIF_SHIFT (24) ++ ++ ++/* CLKDIV0 */ ++#define S5P_CLKDIV0_APLL_MASK (0x1<<0) ++#define S5P_CLKDIV0_APLL_SHIFT (0) ++#define S5P_CLKDIV0_ARM_MASK (0x7<<4) ++#define S5P_CLKDIV0_ARM_SHIFT (4) ++#define S5P_CLKDIV0_D0_MASK (0x7<<8) ++#define S5P_CLKDIV0_D0_SHIFT (8) ++#define S5P_CLKDIV0_PCLKD0_MASK (0x7<<12) ++#define S5P_CLKDIV0_PCLKD0_SHIFT (12) ++#define S5P_CLKDIV0_SECSS_MASK (0x7<<16) ++#define S5P_CLKDIV0_SECSS_SHIFT (16) ++ ++/* CLKDIV1 */ ++#define S5P_CLKDIV1_AM_MASK (0x7<<0) ++#define S5P_CLKDIV1_AM_SHIFT (0) ++#define S5P_CLKDIV1_MPLL_MASK (0x3<<4) ++#define S5P_CLKDIV1_MPLL_SHIFT (4) ++#define S5P_CLKDIV1_MPLL2_MASK (0x1<<8) ++#define S5P_CLKDIV1_MPLL2_SHIFT (8) ++#define S5P_CLKDIV1_D1_MASK (0x7<<12) ++#define S5P_CLKDIV1_D1_SHIFT (12) ++#define S5P_CLKDIV1_PCLKD1_MASK (0x7<<16) ++#define S5P_CLKDIV1_PCLKD1_SHIFT (16) ++#define S5P_CLKDIV1_ONENAND_MASK (0x3<<20) ++#define S5P_CLKDIV1_ONENAND_SHIFT (20) ++#define S5P_CLKDIV1_CAM_MASK (0x1F<<24) ++#define S5P_CLKDIV1_CAM_SHIFT (24) ++ ++/* CLKDIV2 */ ++#define S5P_CLKDIV2_UART_MASK (0x7<<0) ++#define S5P_CLKDIV2_UART_SHIFT (0) ++#define S5P_CLKDIV2_SPI0_MASK (0xf<<4) ++#define S5P_CLKDIV2_SPI0_SHIFT (4) ++#define S5P_CLKDIV2_SPI1_MASK (0xf<<8) ++#define S5P_CLKDIV2_SPI1_SHIFT (8) ++#define S5P_CLKDIV2_SPI2_MASK (0xf<<12) ++#define S5P_CLKDIV2_SPI2_SHIFT (12) ++#define S5P_CLKDIV2_IRDA_MASK (0xf<<16) ++#define S5P_CLKDIV2_IRDA_SHIFT (16) ++#define S5P_CLKDIV2_UHOST_MASK (0xf<<20) ++#define S5P_CLKDIV2_UHOST_SHIFT (20) ++ ++/* CLKDIV3 */ ++#define S5P_CLKDIV3_MMC0_MASK (0xf<<0) ++#define S5P_CLKDIV3_MMC0_SHIFT (0) ++#define S5P_CLKDIV3_MMC1_MASK (0xf<<4) ++#define S5P_CLKDIV3_MMC1_SHIFT (4) ++#define S5P_CLKDIV3_MMC2_MASK (0xf<<8) ++#define S5P_CLKDIV3_MMC2_SHIFT (8) ++#define S5P_CLKDIV3_LCD_MASK (0xf<<12) ++#define S5P_CLKDIV3_LCD_SHIFT (12) ++#define S5P_CLKDIV3_FIMC0_MASK (0xf<<16) ++#define S5P_CLKDIV3_FIMC0_SHIFT (16) ++#define S5P_CLKDIV3_FIMC1_MASK (0xf<<20) ++#define S5P_CLKDIV3_FIMC1_SHIFT (20) ++#define S5P_CLKDIV3_FIMC2_MASK (0xf<<24) ++#define S5P_CLKDIV3_FIMC2_SHIFT (24) ++#define S5P_CLKDIV3_HDMI_MASK (0xf<<28) ++#define S5P_CLKDIV3_HDMI_SHIFT (28) ++ ++/* CLKDIV4 */ ++#define S5P_CLKDIV4_PWI_MASK (0x7<<0) ++#define S5P_CLKDIV4_PWI_SHIFT (0) ++#define S5P_CLKDIV4_HCLKD2_MASK (0x7<<4) ++#define S5P_CLKDIV4_HCLKD2_SHIFT (4) ++#define S5P_CLKDIV4_I2SD2_MASK (0xf<<8) ++#define S5P_CLKDIV4_I2SD2_SHIFT (8) ++#define S5P_CLKDIV4_AUDIO0_MASK (0xf<<12) ++#define S5P_CLKDIV4_AUDIO0_SHIFT (12) ++#define S5P_CLKDIV4_AUDIO1_MASK (0xf<<16) ++#define S5P_CLKDIV4_AUDIO1_SHIFT (16) ++#define S5P_CLKDIV4_AUDIO2_MASK (0xf<<20) ++#define S5P_CLKDIV4_AUDIO2_SHIFT (20) ++ ++ ++/* HCLKD0/PCLKD0 Clock Gate 0 Registers */ ++#define S5P_CLKGATE_D00_INTC (1<<0) ++#define S5P_CLKGATE_D00_TZIC (1<<1) ++#define S5P_CLKGATE_D00_CFCON (1<<2) ++#define S5P_CLKGATE_D00_MDMA (1<<3) ++#define S5P_CLKGATE_D00_G2D (1<<4) ++#define S5P_CLKGATE_D00_SECSS (1<<5) ++#define S5P_CLKGATE_D00_CSSYS (1<<6) ++ ++/* HCLKD0/PCLKD0 Clock Gate 1 Registers */ ++#define S5P_CLKGATE_D01_DMC (1<<0) ++#define S5P_CLKGATE_D01_SROMC (1<<1) ++#define S5P_CLKGATE_D01_ONENAND (1<<2) ++#define S5P_CLKGATE_D01_NFCON (1<<3) ++#define S5P_CLKGATE_D01_INTMEM (1<<4) ++#define S5P_CLKGATE_D01_EBI (1<<5) ++ ++/* PCLKD0 Clock Gate 2 Registers */ ++#define S5P_CLKGATE_D02_SECKEY (1<<1) ++#define S5P_CLKGATE_D02_SDM (1<<2) ++ ++/* HCLKD1/PCLKD1 Clock Gate 0 Registers */ ++#define S5P_CLKGATE_D10_PDMA0 (1<<0) ++#define S5P_CLKGATE_D10_PDMA1 (1<<1) ++#define S5P_CLKGATE_D10_USBHOST (1<<2) ++#define S5P_CLKGATE_D10_USBOTG (1<<3) ++#define S5P_CLKGATE_D10_MODEMIF (1<<4) ++#define S5P_CLKGATE_D10_HSMMC0 (1<<5) ++#define S5P_CLKGATE_D10_HSMMC1 (1<<6) ++#define S5P_CLKGATE_D10_HSMMC2 (1<<7) ++ ++/* HCLKD1/PCLKD1 Clock Gate 1 Registers */ ++#define S5P_CLKGATE_D11_LCD (1<<0) ++#define S5P_CLKGATE_D11_ROTATOR (1<<1) ++#define S5P_CLKGATE_D11_FIMC0 (1<<2) ++#define S5P_CLKGATE_D11_FIMC1 (1<<3) ++#define S5P_CLKGATE_D11_FIMC2 (1<<4) ++#define S5P_CLKGATE_D11_JPEG (1<<5) ++#define S5P_CLKGATE_D11_DSI (1<<6) ++#define S5P_CLKGATE_D11_CSI (1<<7) ++#define S5P_CLKGATE_D11_G3D (1<<8) ++ ++/* HCLKD1/PCLKD1 Clock Gate 2 Registers */ ++#define S5P_CLKGATE_D12_TV (1<<0) ++#define S5P_CLKGATE_D12_VP (1<<1) ++#define S5P_CLKGATE_D12_MIXER (1<<2) ++#define S5P_CLKGATE_D12_HDMI (1<<3) ++#define S5P_CLKGATE_D12_MFC (1<<4) ++ ++/* HCLKD1/PCLKD1 Clock Gate 3 Registers */ ++#define S5P_CLKGATE_D13_CHIPID (1<<0) ++#define S5P_CLKGATE_D13_GPIO (1<<1) ++#define S5P_CLKGATE_D13_APC (1<<2) ++#define S5P_CLKGATE_D13_IEC (1<<3) ++#define S5P_CLKGATE_D13_PWM (1<<6) ++#define S5P_CLKGATE_D13_SYSTIMER (1<<7) ++#define S5P_CLKGATE_D13_WDT (1<<8) ++#define S5P_CLKGATE_D13_RTC (1<<9) ++ ++/* HCLKD1/PCLKD1 Clock Gate 4 Registers */ ++#define S5P_CLKGATE_D14_UART0 (1<<0) ++#define S5P_CLKGATE_D14_UART1 (1<<1) ++#define S5P_CLKGATE_D14_UART2 (1<<2) ++#define S5P_CLKGATE_D14_UART3 (1<<3) ++#define S5P_CLKGATE_D14_IIC (1<<4) ++#define S5P_CLKGATE_D14_HDMI_IIC (1<<5) ++#define S5P_CLKGATE_D14_SPI0 (1<<6) ++#define S5P_CLKGATE_D14_SPI1 (1<<7) ++#define S5P_CLKGATE_D14_SPI2 (1<<8) ++#define S5P_CLKGATE_D14_IRDA (1<<9) ++#define S5P_CLKGATE_D14_CCAN0 (1<<10) ++#define S5P_CLKGATE_D14_CCAN1 (1<<11) ++#define S5P_CLKGATE_D14_HSITX (1<<12) ++#define S5P_CLKGATE_D14_HSIRX (1<<13) ++ ++/* HCLKD1/PCLKD1 Clock Gate 5 Registers */ ++#define S5P_CLKGATE_D15_IIS0 (1<<0) ++#define S5P_CLKGATE_D15_IIS1 (1<<1) ++#define S5P_CLKGATE_D15_IIS2 (1<<2) ++#define S5P_CLKGATE_D15_AC97 (1<<3) ++#define S5P_CLKGATE_D15_PCM0 (1<<4) ++#define S5P_CLKGATE_D15_PCM1 (1<<5) ++#define S5P_CLKGATE_D15_SPDIF (1<<6) ++#define S5P_CLKGATE_D15_TSADC (1<<7) ++#define S5P_CLKGATE_D15_KEYIF (1<<8) ++#define S5P_CLKGATE_D15_CG (1<<9) ++ ++/* HCLKD2 Clock Gate 0 Registers */ ++#define S5P_CLKGATE_D20_HCLKD2 (1<<0) ++#define S5P_CLKGATE_D20_I2SD2 (1<<1) ++ ++/* Special Clock Gate 0 Registers */ ++#define S5P_CLKGATE_SCLK0_HPM (1<<0) ++#define S5P_CLKGATE_SCLK0_PWI (1<<1) ++#define S5P_CLKGATE_SCLK0_ONENAND (1<<2) ++#define S5P_CLKGATE_SCLK0_UART (1<<3) ++#define S5P_CLKGATE_SCLK0_SPI0 (1<<4) ++#define S5P_CLKGATE_SCLK0_SPI1 (1<<5) ++#define S5P_CLKGATE_SCLK0_SPI2 (1<<6) ++#define S5P_CLKGATE_SCLK0_SPI0_48 (1<<7) ++#define S5P_CLKGATE_SCLK0_SPI1_48 (1<<8) ++#define S5P_CLKGATE_SCLK0_SPI2_48 (1<<9) ++#define S5P_CLKGATE_SCLK0_IRDA (1<<10) ++#define S5P_CLKGATE_SCLK0_USBHOST (1<<11) ++#define S5P_CLKGATE_SCLK0_MMC0 (1<<12) ++#define S5P_CLKGATE_SCLK0_MMC1 (1<<13) ++#define S5P_CLKGATE_SCLK0_MMC2 (1<<14) ++#define S5P_CLKGATE_SCLK0_MMC0_48 (1<<15) ++#define S5P_CLKGATE_SCLK0_MMC1_48 (1<<16) ++#define S5P_CLKGATE_SCLK0_MMC2_48 (1<<17) ++ ++/* Special Clock Gate 1 Registers */ ++#define S5P_CLKGATE_SCLK1_LCD (1<<0) ++#define S5P_CLKGATE_SCLK1_FIMC0 (1<<1) ++#define S5P_CLKGATE_SCLK1_FIMC1 (1<<2) ++#define S5P_CLKGATE_SCLK1_FIMC2 (1<<3) ++#define S5P_CLKGATE_SCLK1_TV54 (1<<4) ++#define S5P_CLKGATE_SCLK1_VDAC54 (1<<5) ++#define S5P_CLKGATE_SCLK1_MIXER (1<<6) ++#define S5P_CLKGATE_SCLK1_HDMI (1<<7) ++#define S5P_CLKGATE_SCLK1_AUDIO0 (1<<8) ++#define S5P_CLKGATE_SCLK1_AUDIO1 (1<<9) ++#define S5P_CLKGATE_SCLK1_AUDIO2 (1<<10) ++#define S5P_CLKGATE_SCLK1_SPDIF (1<<11) ++#define S5P_CLKGATE_SCLK1_CAM (1<<12) ++ ++/* register for power management */ ++#define S5P_PWR_CFG S5P_CLKREG(0x8000) ++#define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0x8004) ++#define S5P_NORMAL_CFG S5P_CLKREG(0x8010) ++#define S5P_STOP_CFG S5P_CLKREG(0x8014) ++#define S5P_SLEEP_CFG S5P_CLKREG(0x8018) ++#define S5P_STOP_MEM_CFG S5P_CLKREG(0x801C) ++#define S5P_OSC_FREQ S5P_CLKREG(0x8100) ++#define S5P_OSC_STABLE S5P_CLKREG(0x8104) ++#define S5P_PWR_STABLE S5P_CLKREG(0x8108) ++#define S5P_MTC_STABLE S5P_CLKREG(0x8110) ++#define S5P_CLAMP_STABLE S5P_CLKREG(0x8114) ++#define S5P_OTHERS S5P_CLKREG(0x8200) ++#define S5P_RST_STAT S5P_CLKREG(0x8300) ++#define S5P_WAKEUP_STAT S5P_CLKREG(0x8304) ++#define S5P_BLK_PWR_STAT S5P_CLKREG(0x8308) ++#define S5P_INFORM0 S5P_CLKREG(0x8400) ++#define S5P_INFORM1 S5P_CLKREG(0x8404) ++#define S5P_INFORM2 S5P_CLKREG(0x8408) ++#define S5P_INFORM3 S5P_CLKREG(0x840C) ++#define S5P_INFORM4 S5P_CLKREG(0x8410) ++#define S5P_INFORM5 S5P_CLKREG(0x8414) ++#define S5P_INFORM6 S5P_CLKREG(0x8418) ++#define S5P_INFORM7 S5P_CLKREG(0x841C) ++#define S5P_DCGIDX_MAP0 S5P_CLKREG(0x8500) ++#define S5P_DCGIDX_MAP1 S5P_CLKREG(0x8504) ++#define S5P_DCGIDX_MAP2 S5P_CLKREG(0x8508) ++#define S5P_DCGPERF_MAP0 S5P_CLKREG(0x850C) ++#define S5P_DCGPERF_MAP1 S5P_CLKREG(0x8510) ++#define S5P_DVCIDX_MAP S5P_CLKREG(0x8514) ++#define S5P_FREQ_CPU S5P_CLKREG(0x8518) ++#define S5P_FREQ_DPM S5P_CLKREG(0x851C) ++#define S5P_DVSEMCLK_EN S5P_CLKREG(0x8520) ++#define S5P_APLL_CON_L8 S5P_CLKREG(0x8600) ++#define S5P_APLL_CON_L7 S5P_CLKREG(0x8604) ++#define S5P_APLL_CON_L6 S5P_CLKREG(0x8608) ++#define S5P_APLL_CON_L5 S5P_CLKREG(0x860C) ++#define S5P_APLL_CON_L4 S5P_CLKREG(0x8610) ++#define S5P_APLL_CON_L3 S5P_CLKREG(0x8614) ++#define S5P_APLL_CON_L2 S5P_CLKREG(0x8618) ++#define S5P_APLL_CON_L1 S5P_CLKREG(0x861C) ++#define S5P_IEM_CONTROL S5P_CLKREG(0x8620) ++#define S5P_CLKDIV_IEM_L8 S5P_CLKREG(0x8700) ++#define S5P_CLKDIV_IEM_L7 S5P_CLKREG(0x8704) ++#define S5P_CLKDIV_IEM_L6 S5P_CLKREG(0x8708) ++#define S5P_CLKDIV_IEM_L5 S5P_CLKREG(0x870C) ++#define S5P_CLKDIV_IEM_L4 S5P_CLKREG(0x8710) ++#define S5P_CLKDIV_IEM_L3 S5P_CLKREG(0x8714) ++#define S5P_CLKDIV_IEM_L2 S5P_CLKREG(0x8718) ++#define S5P_CLKDIV_IEM_L1 S5P_CLKREG(0x871C) ++#define S5P_IEM_HPMCLK_DIV S5P_CLKREG(0x8724) ++ ++#define S5P_SWRESET S5P_CLKREG(0x100000) ++#define S5P_OND_SWRESET S5P_CLKREG(0x100008) ++#define S5P_GEN_CTRL S5P_CLKREG(0x100100) ++#define S5P_GEN_STATUS S5P_CLKREG(0x100104) ++#define S5P_MEM_SYS_CFG S5P_CLKREG(0x100200) ++#define S5P_CAM_MUX_SEL S5P_CLKREG(0x100300) ++#define S5P_MIXER_OUT_SEL S5P_CLKREG(0x100304) ++#define S5P_LPMP_MODE_SEL S5P_CLKREG(0x100308) ++#define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x100400) ++#define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x100414) ++#define S5P_HDMI_PHY_CON0 S5P_CLKREG(0x100420) ++ ++#define S5P_CFG_WFI_CLEAN ~(3<<5) ++#define S5P_CFG_WFI_IDLE (1<<5) ++#define S5P_CFG_WFI_STOP (2<<5) ++#define S5P_CFG_WFI_SLEEP (3<<5) ++ ++#define S5P_OTHER_SYS_INT 24 ++#define S5P_OTHER_STA_TYPE 23 ++#define STA_TYPE_EXPON 0 ++#define STA_TYPE_SFR 1 ++ ++#define S5P_PWR_STA_EXP_SCALE 0 ++#define S5P_PWR_STA_CNT 4 ++ ++#define S5P_PWR_STABLE_COUNT 85500 ++ ++#define S5P_SLEEP_CFG_OSC_EN 0 ++ ++/* OTHERS Resgister */ ++#define S5P_OTHERS_USB_SIG_MASK (1 << 16) ++#define S5P_OTHERS_MIPI_DPHY_EN (1 << 28) ++ ++/* MIPI D-PHY Control Register 0 */ ++#define S5P_MIPI_PHY_CON0_M_RESETN (1 << 1) ++#define S5P_MIPI_PHY_CON0_S_RESETN (1 << 0) ++ ++#endif /* _PLAT_REGS_CLOCK_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/regs-csis.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/regs-csis.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/regs-csis.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/regs-csis.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,89 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-csis.h ++ * ++ * Register definition file for MIPI-CSI2 Driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef _REGS_CSIS_H ++#define _REGS_CSIS_H ++ ++#define S3C_CSISREG(x) (x) ++ ++/************************************************************************* ++ * Registers ++ ************************************************************************/ ++#define S3C_CSIS_CONTROL S3C_CSISREG(0x00) ++#define S3C_CSIS_DPHYCTRL S3C_CSISREG(0x04) ++#define S3C_CSIS_CONFIG S3C_CSISREG(0x08) ++#define S3C_CSIS_DPHYSTS S3C_CSISREG(0x0c) ++#define S3C_CSIS_INTMSK S3C_CSISREG(0x10) ++#define S3C_CSIS_INTSRC S3C_CSISREG(0x14) ++ ++/************************************************************************* ++ * Bit Definitions ++ ************************************************************************/ ++/* Control Register */ ++#define S3C_CSIS_CONTROL_DPDN_DEFAULT (0 << 31) ++#define S3C_CSIS_CONTROL_DPDN_SWAP (1 << 31) ++#define S3C_CSIS_CONTROL_RESET (1 << 4) ++#define S3C_CSIS_CONTROL_DISABLE (0 << 0) ++#define S3C_CSIS_CONTROL_ENABLE (1 << 0) ++ ++/* D-PHY Control Register */ ++#define S3C_CSIS_DPHYCTRL_DISABLE (0 << 0) ++#define S3C_CSIS_DPHYCTRL_ENABLE (1 << 0) ++ ++/* Configuration Register */ ++#define S3C_CSIS_CONFIG_NR_LANE_1 (0 << 0) ++#define S3C_CSIS_CONFIG_NR_LANE_2 (1 << 0) ++#define S3C_CSIS_CONFIG_NR_LANE_MASK (1 << 0) ++ ++/* D-PHY Status Register */ ++#define S3C_CSIS_DPHYSTS_STOPSTATE_LANE1 (1 << 5) ++#define S3C_CSIS_DPHYSTS_STOPSTATE_LANE0 (1 << 4) ++#define S3C_CSIS_DPHYSTS_STOPSTATE_CLOCK (1 << 0) ++ ++/* Interrupt Mask Register */ ++#define S3C_CSIS_INTMSK_EVEN_BEFORE_DISABLE (0 << 31) ++#define S3C_CSIS_INTMSK_EVEN_BEFORE_ENABLE (1 << 31) ++#define S3C_CSIS_INTMSK_EVEN_AFTER_DISABLE (0 << 30) ++#define S3C_CSIS_INTMSK_EVEN_AFTER_ENABLE (1 << 30) ++#define S3C_CSIS_INTMSK_ODD_BEFORE_DISABLE (0 << 29) ++#define S3C_CSIS_INTMSK_ODD_BEFORE_ENABLE (1 << 29) ++#define S3C_CSIS_INTMSK_ODD_AFTER_DISABLE (0 << 28) ++#define S3C_CSIS_INTMSK_ODD_AFTER_ENABLE (1 << 28) ++#define S3C_CSIS_INTMSK_ERR_SOT_HS_DISABLE (0 << 12) ++#define S3C_CSIS_INTMSK_ERR_SOT_HS_ENABLE (1 << 12) ++#define S3C_CSIS_INTMSK_ERR_ESC_DISABLE (0 << 8) ++#define S3C_CSIS_INTMSK_ERR_ESC_ENABLE (1 << 8) ++#define S3C_CSIS_INTMSK_ERR_CTRL_DISABLE (0 << 4) ++#define S3C_CSIS_INTMSK_ERR_CTRL_ENABLE (1 << 4) ++#define S3C_CSIS_INTMSK_ERR_ECC_DISABLE (0 << 2) ++#define S3C_CSIS_INTMSK_ERR_ECC_ENABLE (1 << 2) ++#define S3C_CSIS_INTMSK_ERR_CRC_DISABLE (0 << 1) ++#define S3C_CSIS_INTMSK_ERR_CRC_ENABLE (1 << 1) ++#define S3C_CSIS_INTMSK_ERR_ID_DISABLE (0 << 0) ++#define S3C_CSIS_INTMSK_ERR_ID_ENABLE (1 << 0) ++ ++/* Interrupt Source Register */ ++#define S3C_CSIS_INTSRC_EVEN_BEFORE (1 << 31) ++#define S3C_CSIS_INTSRC_EVEN_AFTER (1 << 30) ++#define S3C_CSIS_INTSRC_ODD_BEFORE (1 << 29) ++#define S3C_CSIS_INTSRC_ODD_AFTER (1 << 28) ++#define S3C_CSIS_INTSRC_ERR_SOT_HS_LANE1 (1 << 13) ++#define S3C_CSIS_INTSRC_ERR_SOT_HS_LANE0 (1 << 12) ++#define S3C_CSIS_INTSRC_ERR_ESC_LANE1 (1 << 9) ++#define S3C_CSIS_INTSRC_ERR_ESC_LANE0 (1 << 8) ++#define S3C_CSIS_INTSRC_ERR_CTRL1 (1 << 5) ++#define S3C_CSIS_INTSRC_ERR_CTRL0 (1 << 4) ++#define S3C_CSIS_INTSRC_ERR_ECC (1 << 2) ++#define S3C_CSIS_INTSRC_ERR_CRC (1 << 1) ++#define S3C_CSIS_INTSRC_ERR_ID (1 << 0) ++ ++#endif /* _REGS_CSIS_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/regs-fimc.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/regs-fimc.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/regs-fimc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/regs-fimc.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,330 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-fimc.h ++ * ++ * Register definition file for Samsung Camera Interface (FIMC) driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef _REGS_FIMC_H ++#define _REGS_FIMC_H ++ ++#define S3C_FIMCREG(x) (x) ++ ++/************************************************************************* ++ * Register part ++ ************************************************************************/ ++#define S3C_CIOYSA(__x) S3C_FIMCREG(0x18 + (__x) * 4) ++#define S3C_CIOCBSA(__x) S3C_FIMCREG(0x28 + (__x) * 4) ++#define S3C_CIOCRSA(__x) S3C_FIMCREG(0x38 + (__x) * 4) ++ ++#define S3C_CISRCFMT S3C_FIMCREG(0x00) /* Input source format */ ++#define S3C_CIWDOFST S3C_FIMCREG(0x04) /* Window offset */ ++#define S3C_CIGCTRL S3C_FIMCREG(0x08) /* Global control */ ++#define S3C_CIWDOFST2 S3C_FIMCREG(0x14) /* Window offset 2 */ ++#define S3C_CIOYSA1 S3C_FIMCREG(0x18) /* Y 1st frame start address for output DMA */ ++#define S3C_CIOYSA2 S3C_FIMCREG(0x1c) /* Y 2nd frame start address for output DMA */ ++#define S3C_CIOYSA3 S3C_FIMCREG(0x20) /* Y 3rd frame start address for output DMA */ ++#define S3C_CIOYSA4 S3C_FIMCREG(0x24) /* Y 4th frame start address for output DMA */ ++#define S3C_CIOCBSA1 S3C_FIMCREG(0x28) /* Cb 1st frame start address for output DMA */ ++#define S3C_CIOCBSA2 S3C_FIMCREG(0x2c) /* Cb 2nd frame start address for output DMA */ ++#define S3C_CIOCBSA3 S3C_FIMCREG(0x30) /* Cb 3rd frame start address for output DMA */ ++#define S3C_CIOCBSA4 S3C_FIMCREG(0x34) /* Cb 4th frame start address for output DMA */ ++#define S3C_CIOCRSA1 S3C_FIMCREG(0x38) /* Cr 1st frame start address for output DMA */ ++#define S3C_CIOCRSA2 S3C_FIMCREG(0x3c) /* Cr 2nd frame start address for output DMA */ ++#define S3C_CIOCRSA3 S3C_FIMCREG(0x40) /* Cr 3rd frame start address for output DMA */ ++#define S3C_CIOCRSA4 S3C_FIMCREG(0x44) /* Cr 4th frame start address for output DMA */ ++#define S3C_CITRGFMT S3C_FIMCREG(0x48) /* Target image format */ ++#define S3C_CIOCTRL S3C_FIMCREG(0x4c) /* Output DMA control */ ++#define S3C_CISCPRERATIO S3C_FIMCREG(0x50) /* Pre-scaler control 1 */ ++#define S3C_CISCPREDST S3C_FIMCREG(0x54) /* Pre-scaler control 2 */ ++#define S3C_CISCCTRL S3C_FIMCREG(0x58) /* Main scaler control */ ++#define S3C_CITAREA S3C_FIMCREG(0x5c) /* Target area */ ++#define S3C_CISTATUS S3C_FIMCREG(0x64) /* Status */ ++#define S3C_CIIMGCPT S3C_FIMCREG(0xc0) /* Image capture enable command */ ++#define S3C_CICPTSEQ S3C_FIMCREG(0xc4) /* Capture sequence */ ++#define S3C_CIIMGEFF S3C_FIMCREG(0xd0) /* Image effects */ ++#define S3C_CIIYSA0 S3C_FIMCREG(0xd4) /* Y frame start address for input DMA */ ++#define S3C_CIICBSA0 S3C_FIMCREG(0xd8) /* Cb frame start address for input DMA */ ++#define S3C_CIICRSA0 S3C_FIMCREG(0xdc) /* Cr frame start address for input DMA */ ++#define S3C_CIREAL_ISIZE S3C_FIMCREG(0xf8) /* Real input DMA image size */ ++#define S3C_MSCTRL S3C_FIMCREG(0xfc) /* Input DMA control */ ++#define S3C_CIOYOFF S3C_FIMCREG(0x168) /* Output DMA Y offset */ ++#define S3C_CIOCBOFF S3C_FIMCREG(0x16c) /* Output DMA CB offset */ ++#define S3C_CIOCROFF S3C_FIMCREG(0x170) /* Output DMA CR offset */ ++#define S3C_CIIYOFF S3C_FIMCREG(0x174) /* Input DMA Y offset */ ++#define S3C_CIICBOFF S3C_FIMCREG(0x178) /* Input DMA CB offset */ ++#define S3C_CIICROFF S3C_FIMCREG(0x17c) /* Input DMA CR offset */ ++#define S3C_ORGISIZE S3C_FIMCREG(0x180) /* Input DMA original image size */ ++#define S3C_ORGOSIZE S3C_FIMCREG(0x184) /* Output DMA original image size */ ++#define S3C_CIEXTEN S3C_FIMCREG(0x188) /* Real output DMA image size */ ++#define S3C_CIDMAPARAM S3C_FIMCREG(0x18c) /* DMA parameter */ ++#define S3C_CSIIMGFMT S3C_FIMCREG(0x194) /* MIPI CSI image format */ ++ ++/************************************************************************* ++ * Macro part ++ ************************************************************************/ ++#define S3C_CISRCFMT_SOURCEHSIZE(x) ((x) << 16) ++#define S3C_CISRCFMT_SOURCEVSIZE(x) ((x) << 0) ++ ++#define S3C_CIWDOFST_WINHOROFST(x) ((x) << 16) ++#define S3C_CIWDOFST_WINVEROFST(x) ((x) << 0) ++ ++#define S3C_CIWDOFST2_WINHOROFST2(x) ((x) << 16) ++#define S3C_CIWDOFST2_WINVEROFST2(x) ((x) << 0) ++ ++#define S3C_CITRGFMT_TARGETHSIZE(x) ((x) << 16) ++#define S3C_CITRGFMT_TARGETVSIZE(x) ((x) << 0) ++ ++#define S3C_CISCPRERATIO_SHFACTOR(x) ((x) << 28) ++#define S3C_CISCPRERATIO_PREHORRATIO(x) ((x) << 16) ++#define S3C_CISCPRERATIO_PREVERRATIO(x) ((x) << 0) ++ ++#define S3C_CISCPREDST_PREDSTWIDTH(x) ((x) << 16) ++#define S3C_CISCPREDST_PREDSTHEIGHT(x) ((x) << 0) ++ ++#define S3C_CISCCTRL_MAINHORRATIO(x) ((x) << 16) ++#define S3C_CISCCTRL_MAINVERRATIO(x) ((x) << 0) ++ ++#define S3C_CITAREA_TARGET_AREA(x) ((x) << 0) ++ ++#define S3C_CISTATUS_GET_FRAME_COUNT(x) (((x) >> 26) & 0x3) ++#define S3C_CISTATUS_GET_FRAME_END(x) (((x) >> 17) & 0x1) ++ ++#define S3C_CIIMGEFF_PAT_CB(x) ((x) << 13) ++#define S3C_CIIMGEFF_PAT_CR(x) ((x) << 0) ++ ++#define S3C_CIREAL_ISIZE_HEIGHT(x) ((x) << 16) ++#define S3C_CIREAL_ISIZE_WIDTH(x) ((x) << 0) ++ ++#define S3C_MSCTRL_SUCCESSIVE_COUNT(x) ((x) << 24) ++ ++#define S3C_CIOYOFF_VERTICAL(x) ((x) << 16) ++#define S3C_CIOYOFF_HORIZONTAL(x) ((x) << 0) ++ ++#define S3C_CIOCBOFF_VERTICAL(x) ((x) << 16) ++#define S3C_CIOCBOFF_HORIZONTAL(x) ((x) << 0) ++ ++#define S3C_CIOCROFF_VERTICAL(x) ((x) << 16) ++#define S3C_CIOCROFF_HORIZONTAL(x) ((x) << 0) ++ ++#define S3C_CIIYOFF_VERTICAL(x) ((x) << 16) ++#define S3C_CIIYOFF_HORIZONTAL(x) ((x) << 0) ++ ++#define S3C_CIICBOFF_VERTICAL(x) ((x) << 16) ++#define S3C_CIICBOFF_HORIZONTAL(x) ((x) << 0) ++ ++#define S3C_CIICROFF_VERTICAL(x) ((x) << 16) ++#define S3C_CIICROFF_HORIZONTAL(x) ((x) << 0) ++ ++#define S3C_ORGISIZE_VERTICAL(x) ((x) << 16) ++#define S3C_ORGISIZE_HORIZONTAL(x) ((x) << 0) ++ ++#define S3C_ORGOSIZE_VERTICAL(x) ((x) << 16) ++#define S3C_ORGOSIZE_HORIZONTAL(x) ((x) << 0) ++ ++ ++/************************************************************************* ++ * Bit definition part ++ ************************************************************************/ ++/* Source format register */ ++#define S3C_CISRCFMT_ITU601_8BIT (1 << 31) ++#define S3C_CISRCFMT_ITU656_8BIT (0 << 31) ++#define S3C_CISRCFMT_ITU601_16BIT (1 << 29) ++#define S3C_CISRCFMT_ORDER422_YCBYCR (0 << 14) ++#define S3C_CISRCFMT_ORDER422_YCRYCB (1 << 14) ++#define S3C_CISRCFMT_ORDER422_CBYCRY (2 << 14) ++#define S3C_CISRCFMT_ORDER422_CRYCBY (3 << 14) ++#define S3C_CISRCFMT_ORDER422_Y4CBCRCBCR (0 << 14) /* ITU601 16bit only */ ++#define S3C_CISRCFMT_ORDER422_Y4CRCBCRCB (1 << 14) /* ITU601 16bit only */ ++ ++/* Window offset register */ ++#define S3C_CIWDOFST_WINOFSEN (1 << 31) ++#define S3C_CIWDOFST_CLROVFIY (1 << 30) ++#define S3C_CIWDOFST_CLROVRLB (1 << 29) ++#define S3C_CIWDOFST_WINHOROFST_MASK (0x7ff << 16) ++#define S3C_CIWDOFST_CLROVFICB (1 << 15) ++#define S3C_CIWDOFST_CLROVFICR (1 << 14) ++#define S3C_CIWDOFST_WINVEROFST_MASK (0xfff << 0) ++ ++/* Global control register */ ++#define S3C_CIGCTRL_SWRST (1 << 31) ++#define S3C_CIGCTRL_CAMRST_A (1 << 30) ++#define S3C_CIGCTRL_SELCAM_ITU_B (0 << 29) ++#define S3C_CIGCTRL_SELCAM_ITU_A (1 << 29) ++#define S3C_CIGCTRL_SELCAM_ITU_MASK (1 << 29) ++#define S3C_CIGCTRL_TESTPATTERN_NORMAL (0 << 27) ++#define S3C_CIGCTRL_TESTPATTERN_COLOR_BAR (1 << 27) ++#define S3C_CIGCTRL_TESTPATTERN_HOR_INC (2 << 27) ++#define S3C_CIGCTRL_TESTPATTERN_VER_INC (3 << 27) ++#define S3C_CIGCTRL_TESTPATTERN_MASK (3 << 27) ++#define S3C_CIGCTRL_TESTPATTERN_SHIFT (27) ++#define S3C_CIGCTRL_INVPOLPCLK (1 << 26) ++#define S3C_CIGCTRL_INVPOLVSYNC (1 << 25) ++#define S3C_CIGCTRL_INVPOLHREF (1 << 24) ++#define S3C_CIGCTRL_IRQ_OVFEN (1 << 22) ++#define S3C_CIGCTRL_HREF_MASK (1 << 21) ++#define S3C_CIGCTRL_IRQ_EDGE (0 << 20) ++#define S3C_CIGCTRL_IRQ_LEVEL (1 << 20) ++#define S3C_CIGCTRL_IRQ_CLR (1 << 19) ++#define S3C_CIGCTRL_IRQ_DISABLE (0 << 16) ++#define S3C_CIGCTRL_IRQ_ENABLE (1 << 16) ++#define S3C_CIGCTRL_INVPOLHSYNC (1 << 4) ++#define S3C_CIGCTRL_SELCAM_ITU (0 << 3) ++#define S3C_CIGCTRL_SELCAM_MIPI (1 << 3) ++#define S3C_CIGCTRL_PROGRESSIVE (0 << 0) ++#define S3C_CIGCTRL_INTERLACE (1 << 0) ++ ++/* Window offset2 register */ ++#define S3C_CIWDOFST_WINHOROFST2_MASK (0xfff << 16) ++#define S3C_CIWDOFST_WINVEROFST2_MASK (0xfff << 16) ++ ++/* Target format register */ ++#define S3C_CITRGFMT_INROT90_CLOCKWISE (1 << 31) ++#define S3C_CITRGFMT_OUTFORMAT_YCBCR420 (0 << 29) ++#define S3C_CITRGFMT_OUTFORMAT_YCBCR422 (1 << 29) ++#define S3C_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE (2 << 29) ++#define S3C_CITRGFMT_OUTFORMAT_RGB (3 << 29) ++#define S3C_CITRGFMT_FLIP_SHIFT (14) ++#define S3C_CITRGFMT_FLIP_NORMAL (0 << 14) ++#define S3C_CITRGFMT_FLIP_X_MIRROR (1 << 14) ++#define S3C_CITRGFMT_FLIP_Y_MIRROR (2 << 14) ++#define S3C_CITRGFMT_FLIP_180 (3 << 14) ++#define S3C_CITRGFMT_FLIP_MASK (3 << 14) ++#define S3C_CITRGFMT_OUTROT90_CLOCKWISE (1 << 13) ++ ++/* Output DMA control register */ ++#define S3C_CIOCTRL_ORDER2P_SHIFT (24) ++#define S3C_CIOCTRL_ORDER2P_MASK (3 << 24) ++#define S3C_CIOCTRL_YCBCR_3PLANE (0 << 3) ++#define S3C_CIOCTRL_YCBCR_2PLANE (1 << 3) ++#define S3C_CIOCTRL_YCBCR_PLANE_MASK (1 << 3) ++#define S3C_CIOCTRL_LASTIRQ_ENABLE (1 << 2) ++#define S3C_CIOCTRL_ORDER422_MASK (3 << 0) ++ ++/* Main scaler control register */ ++#define S3C_CISCCTRL_SCALERBYPASS (1 << 31) ++#define S3C_CISCCTRL_SCALEUP_H (1 << 30) ++#define S3C_CISCCTRL_SCALEUP_V (1 << 29) ++#define S3C_CISCCTRL_CSCR2Y_NARROW (0 << 28) ++#define S3C_CISCCTRL_CSCR2Y_WIDE (1 << 28) ++#define S3C_CISCCTRL_CSCY2R_NARROW (0 << 27) ++#define S3C_CISCCTRL_CSCY2R_WIDE (1 << 27) ++#define S3C_CISCCTRL_LCDPATHEN_FIFO (1 << 26) ++#define S3C_CISCCTRL_PROGRESSIVE (0 << 25) ++#define S3C_CISCCTRL_INTERLACE (1 << 25) ++#define S3C_CISCCTRL_SCALERSTART (1 << 15) ++#define S3C_CISCCTRL_INRGB_FMT_RGB565 (0 << 13) ++#define S3C_CISCCTRL_INRGB_FMT_RGB666 (1 << 13) ++#define S3C_CISCCTRL_INRGB_FMT_RGB888 (2 << 13) ++#define S3C_CISCCTRL_OUTRGB_FMT_RGB565 (0 << 11) ++#define S3C_CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11) ++#define S3C_CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11) ++#define S3C_CISCCTRL_EXTRGB_NORMAL (0 << 10) ++#define S3C_CISCCTRL_EXTRGB_EXTENSION (1 << 10) ++#define S3C_CISCCTRL_ONE2ONE (1 << 9) ++ ++/* Status register */ ++#define S3C_CISTATUS_OVFIY (1 << 31) ++#define S3C_CISTATUS_OVFICB (1 << 30) ++#define S3C_CISTATUS_OVFICR (1 << 29) ++#define S3C_CISTATUS_VSYNC (1 << 28) ++#define S3C_CISTATUS_WINOFSTEN (1 << 25) ++#define S3C_CISTATUS_IMGCPTEN (1 << 22) ++#define S3C_CISTATUS_IMGCPTENSC (1 << 21) ++#define S3C_CISTATUS_VSYNC_A (1 << 20) ++#define S3C_CISTATUS_VSYNC_B (1 << 19) ++#define S3C_CISTATUS_OVRLB (1 << 18) ++#define S3C_CISTATUS_FRAMEEND (1 << 17) ++#define S3C_CISTATUS_LASTCAPTUREEND (1 << 16) ++#define S3C_CISTATUS_VVALID_A (1 << 15) ++#define S3C_CISTATUS_VVALID_B (1 << 14) ++ ++/* Image capture enable register */ ++#define S3C_CIIMGCPT_IMGCPTEN (1 << 31) ++#define S3C_CIIMGCPT_IMGCPTEN_SC (1 << 30) ++#define S3C_CIIMGCPT_CPT_FREN_ENABLE (1 << 25) ++#define S3C_CIIMGCPT_CPT_FRMOD_EN (0 << 18) ++#define S3C_CIIMGCPT_CPT_FRMOD_CNT (1 << 18) ++ ++/* Image effects register */ ++#define S3C_CIIMGEFF_IE_DISABLE (0 << 30) ++#define S3C_CIIMGEFF_IE_ENABLE (1 << 30) ++#define S3C_CIIMGEFF_IE_SC_BEFORE (0 << 29) ++#define S3C_CIIMGEFF_IE_SC_AFTER (1 << 29) ++#define S3C_CIIMGEFF_FIN_BYPASS (0 << 26) ++#define S3C_CIIMGEFF_FIN_ARBITRARY (1 << 26) ++#define S3C_CIIMGEFF_FIN_NEGATIVE (2 << 26) ++#define S3C_CIIMGEFF_FIN_ARTFREEZE (3 << 26) ++#define S3C_CIIMGEFF_FIN_EMBOSSING (4 << 26) ++#define S3C_CIIMGEFF_FIN_SILHOUETTE (5 << 26) ++#define S3C_CIIMGEFF_FIN_MASK (7 << 26) ++#define S3C_CIIMGEFF_PAT_CBCR_MASK ((0xff < 13) | (0xff < 0)) ++ ++/* Real input DMA size register */ ++#define S3C_CIREAL_ISIZE_AUTOLOAD_ENABLE (1 << 31) ++#define S3C_CIREAL_ISIZE_ADDR_CH_DISABLE (1 << 30) ++ ++/* Input DMA control register */ ++#define S3C_MSCTRL_2PLANE_SHIFT (16) ++#define S3C_MSCTRL_C_INT_IN_3PLANE (0 << 15) ++#define S3C_MSCTRL_C_INT_IN_2PLANE (1 << 15) ++#define S3C_MSCTRL_FLIP_SHIFT (13) ++#define S3C_MSCTRL_FLIP_NORMAL (0 << 13) ++#define S3C_MSCTRL_FLIP_X_MIRROR (1 << 13) ++#define S3C_MSCTRL_FLIP_Y_MIRROR (2 << 13) ++#define S3C_MSCTRL_FLIP_180 (3 << 13) ++#define S3C_MSCTRL_ORDER422_CRYCBY (0 << 4) ++#define S3C_MSCTRL_ORDER422_YCRYCB (1 << 4) ++#define S3C_MSCTRL_ORDER422_CBYCRY (2 << 4) ++#define S3C_MSCTRL_ORDER422_YCBYCR (3 << 4) ++#define S3C_MSCTRL_INPUT_EXTCAM (0 << 3) ++#define S3C_MSCTRL_INPUT_MEMORY (1 << 3) ++#define S3C_MSCTRL_INPUT_MASK (1 << 3) ++#define S3C_MSCTRL_INFORMAT_YCBCR420 (0 << 1) ++#define S3C_MSCTRL_INFORMAT_YCBCR422 (1 << 1) ++#define S3C_MSCTRL_INFORMAT_YCBCR422_1PLANE (2 << 1) ++#define S3C_MSCTRL_INFORMAT_RGB (3 << 1) ++#define S3C_MSCTRL_ENVID (1 << 0) ++ ++/* DMA parameter register */ ++#define S3C_CIDMAPARAM_R_MODE_LINEAR (0 << 29) ++#define S3C_CIDMAPARAM_R_MODE_CONFTILE (1 << 29) ++#define S3C_CIDMAPARAM_R_MODE_16X16 (2 << 29) ++#define S3C_CIDMAPARAM_R_MODE_64X32 (3 << 29) ++#define S3C_CIDMAPARAM_R_TILE_HSIZE_64 (0 << 24) ++#define S3C_CIDMAPARAM_R_TILE_HSIZE_128 (1 << 24) ++#define S3C_CIDMAPARAM_R_TILE_HSIZE_256 (2 << 24) ++#define S3C_CIDMAPARAM_R_TILE_HSIZE_512 (3 << 24) ++#define S3C_CIDMAPARAM_R_TILE_HSIZE_1024 (4 << 24) ++#define S3C_CIDMAPARAM_R_TILE_HSIZE_2048 (5 << 24) ++#define S3C_CIDMAPARAM_R_TILE_HSIZE_4096 (6 << 24) ++#define S3C_CIDMAPARAM_R_TILE_VSIZE_1 (0 << 20) ++#define S3C_CIDMAPARAM_R_TILE_VSIZE_2 (1 << 20) ++#define S3C_CIDMAPARAM_R_TILE_VSIZE_4 (2 << 20) ++#define S3C_CIDMAPARAM_R_TILE_VSIZE_8 (3 << 20) ++#define S3C_CIDMAPARAM_R_TILE_VSIZE_16 (4 << 20) ++#define S3C_CIDMAPARAM_R_TILE_VSIZE_32 (5 << 20) ++#define S3C_CIDMAPARAM_W_MODE_LINEAR (0 << 13) ++#define S3C_CIDMAPARAM_W_MODE_CONFTILE (1 << 13) ++#define S3C_CIDMAPARAM_W_MODE_16X16 (2 << 13) ++#define S3C_CIDMAPARAM_W_MODE_64X32 (3 << 13) ++#define S3C_CIDMAPARAM_W_TILE_HSIZE_64 (0 << 8) ++#define S3C_CIDMAPARAM_W_TILE_HSIZE_128 (1 << 8) ++#define S3C_CIDMAPARAM_W_TILE_HSIZE_256 (2 << 8) ++#define S3C_CIDMAPARAM_W_TILE_HSIZE_512 (3 << 8) ++#define S3C_CIDMAPARAM_W_TILE_HSIZE_1024 (4 << 8) ++#define S3C_CIDMAPARAM_W_TILE_HSIZE_2048 (5 << 8) ++#define S3C_CIDMAPARAM_W_TILE_HSIZE_4096 (6 << 8) ++#define S3C_CIDMAPARAM_W_TILE_VSIZE_1 (0 << 4) ++#define S3C_CIDMAPARAM_W_TILE_VSIZE_2 (1 << 4) ++#define S3C_CIDMAPARAM_W_TILE_VSIZE_4 (2 << 4) ++#define S3C_CIDMAPARAM_W_TILE_VSIZE_8 (3 << 4) ++#define S3C_CIDMAPARAM_W_TILE_VSIZE_16 (4 << 4) ++#define S3C_CIDMAPARAM_W_TILE_VSIZE_32 (5 << 4) ++ ++#endif /* _REGS_FIMC_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/regs-fimd.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/regs-fimd.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/regs-fimd.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/regs-fimd.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,343 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-fimd.h ++ * ++ * Register definition file for Samsung Display Controller (FIMD) driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef _REGS_FIMD_H ++#define _REGS_FIMD_H ++ ++#define S3C_LCDREG(x) (x) ++ ++/* ++ * Register Map ++*/ ++#define S3C_VIDCON0 S3C_LCDREG(0x0000) /* Video control 0 */ ++#define S3C_VIDCON1 S3C_LCDREG(0x0004) /* Video control 1 */ ++#define S3C_VIDCON2 S3C_LCDREG(0x0008) /* Video control 2 */ ++#define S3C_PRTCON S3C_LCDREG(0x000C) /* Protect control */ ++ ++#define S3C_VIDTCON0 S3C_LCDREG(0x0010) /* Video time control 0 */ ++#define S3C_VIDTCON1 S3C_LCDREG(0x0014) /* Video time control 1 */ ++#define S3C_VIDTCON2 S3C_LCDREG(0x0018) /* Video time control 2 */ ++ ++#define S3C_WINCON0 S3C_LCDREG(0x0020) /* Window control 0 */ ++#define S3C_WINCON1 S3C_LCDREG(0x0024) /* Window control 1 */ ++#define S3C_WINCON2 S3C_LCDREG(0x0028) /* Window control 2 */ ++#define S3C_WINCON3 S3C_LCDREG(0x002C) /* Window control 3 */ ++#define S3C_WINCON4 S3C_LCDREG(0x0030) /* Window control 4 */ ++ ++#define S3C_VIDOSD0A S3C_LCDREG(0x0040) /* Video Window 0 position control */ ++#define S3C_VIDOSD0B S3C_LCDREG(0x0044) /* Video Window 0 position control1 */ ++#define S3C_VIDOSD0C S3C_LCDREG(0x0048) /* Video Window 0 position control */ ++ ++#define S3C_VIDOSD1A S3C_LCDREG(0x0050) /* Video Window 1 position control */ ++#define S3C_VIDOSD1B S3C_LCDREG(0x0054) /* Video Window 1 position control */ ++#define S3C_VIDOSD1C S3C_LCDREG(0x0058) /* Video Window 1 position control */ ++#define S3C_VIDOSD1D S3C_LCDREG(0x005C) /* Video Window 1 position control */ ++ ++#define S3C_VIDOSD2A S3C_LCDREG(0x0060) /* Video Window 2 position control */ ++#define S3C_VIDOSD2B S3C_LCDREG(0x0064) /* Video Window 2 position control */ ++#define S3C_VIDOSD2C S3C_LCDREG(0x0068) /* Video Window 2 position control */ ++#define S3C_VIDOSD2D S3C_LCDREG(0x006C) /* Video Window 2 position control */ ++ ++#define S3C_VIDOSD3A S3C_LCDREG(0x0070) /* Video Window 3 position control */ ++#define S3C_VIDOSD3B S3C_LCDREG(0x0074) /* Video Window 3 position control */ ++#define S3C_VIDOSD3C S3C_LCDREG(0x0078) /* Video Window 3 position control */ ++ ++#define S3C_VIDOSD4A S3C_LCDREG(0x0080) /* Video Window 4 position control */ ++#define S3C_VIDOSD4B S3C_LCDREG(0x0084) /* Video Window 4 position control */ ++#define S3C_VIDOSD4C S3C_LCDREG(0x0088) /* Video Window 4 position control */ ++ ++#define S3C_VIDW00ADD0B0 S3C_LCDREG(0x00A0) /* Window 0 buffer start address, buffer 0 */ ++#define S3C_VIDW00ADD0B1 S3C_LCDREG(0x00A4) /* Window 0 buffer start address, buffer 1 */ ++#define S3C_VIDW01ADD0B0 S3C_LCDREG(0x00A8) /* Window 1 buffer start address, buffer 0 */ ++#define S3C_VIDW01ADD0B1 S3C_LCDREG(0x00AC) /* Window 1 buffer start address, buffer 1 */ ++#define S3C_VIDW02ADD0 S3C_LCDREG(0x00B0) /* Window 2 buffer start address, buffer 0 */ ++#define S3C_VIDW03ADD0 S3C_LCDREG(0x00B8) /* Window 3 buffer start address, buffer 0 */ ++#define S3C_VIDW04ADD0 S3C_LCDREG(0x00C0) /* Window 4 buffer start address, buffer 0 */ ++#define S3C_VIDW00ADD1B0 S3C_LCDREG(0x00D0) /* Window 0 buffer end address, buffer 0 */ ++#define S3C_VIDW00ADD1B1 S3C_LCDREG(0x00D4) /* Window 0 buffer end address, buffer 1 */ ++#define S3C_VIDW01ADD1B0 S3C_LCDREG(0x00D8) /* Window 1 buffer end address, buffer 0 */ ++#define S3C_VIDW01ADD1B1 S3C_LCDREG(0x00DC) /* Window 1 buffer end address, buffer 1 */ ++#define S3C_VIDW02ADD1 S3C_LCDREG(0x00E0) /* Window 2 buffer end address */ ++#define S3C_VIDW03ADD1 S3C_LCDREG(0x00E8) /* Window 3 buffer end address */ ++#define S3C_VIDW04ADD1 S3C_LCDREG(0x00F0) /* Window 4 buffer end address */ ++#define S3C_VIDW00ADD2 S3C_LCDREG(0x0100) /* Window 0 buffer size */ ++#define S3C_VIDW01ADD2 S3C_LCDREG(0x0104) /* Window 1 buffer size */ ++#define S3C_VIDW02ADD2 S3C_LCDREG(0x0108) /* Window 2 buffer size */ ++#define S3C_VIDW03ADD2 S3C_LCDREG(0x010C) /* Window 3 buffer size */ ++#define S3C_VIDW04ADD2 S3C_LCDREG(0x0110) /* Window 4 buffer size */ ++ ++#define S3C_VP1TCON0 S3C_LCDREG(0x0118) /* VP1 interface timing control 0 */ ++#define S3C_VP1TCON1 S3C_LCDREG(0x011C) /* VP1 interface timing control 1 */ ++ ++#define S3C_VIDINTCON0 S3C_LCDREG(0x0130) /* Indicate the Video interrupt control */ ++#define S3C_VIDINTCON1 S3C_LCDREG(0x0134) /* Video Interrupt Pending */ ++ ++#define S3C_W1KEYCON0 S3C_LCDREG(0x0140) /* Color key control */ ++#define S3C_W1KEYCON1 S3C_LCDREG(0x0144) /* Color key value (transparent value) */ ++#define S3C_W2KEYCON0 S3C_LCDREG(0x0148) /* Color key control */ ++#define S3C_W2KEYCON1 S3C_LCDREG(0x014C) /* Color key value (transparent value) */ ++#define S3C_W3KEYCON0 S3C_LCDREG(0x0150) /* Color key control */ ++#define S3C_W3KEYCON1 S3C_LCDREG(0x0154) /* Color key value (transparent value) */ ++#define S3C_W4KEYCON0 S3C_LCDREG(0x0158) /* Color key control */ ++#define S3C_W4KEYCON1 S3C_LCDREG(0x015C) /* Color key value (transparent value) */ ++ ++#define S3C_W1KEYALPHA S3C_LCDREG(0x0160) /* Color key alpha value */ ++#define S3C_W2KEYALPHA S3C_LCDREG(0x0164) /* Color key alpha value */ ++#define S3C_W3KEYALPHA S3C_LCDREG(0x0168) /* Color key alpha value */ ++#define S3C_W4KEYALPHA S3C_LCDREG(0x016C) /* Color key alpha value */ ++ ++#define S3C_DITHMODE S3C_LCDREG(0x0170) /* Dithering mode */ ++ ++#define S3C_WIN0MAP S3C_LCDREG(0x0180) /* Window color control */ ++#define S3C_WIN1MAP S3C_LCDREG(0x0184) /* Window color control */ ++#define S3C_WIN2MAP S3C_LCDREG(0x0188) /* Window color control */ ++#define S3C_WIN3MAP S3C_LCDREG(0x018C) /* Window color control */ ++#define S3C_WIN4MAP S3C_LCDREG(0x0190) /* Window color control */ ++ ++#define S3C_WPALCON_H S3C_LCDREG(0x019C) /* Window Palette control */ ++#define S3C_WPALCON_L S3C_LCDREG(0x01A0) /* Window Palette control */ ++ ++#define S3C_VIDW0ALPHA0 S3C_LCDREG(0x0200) /* Window 0 alpha value 0 */ ++#define S3C_VIDW0ALPHA1 S3C_LCDREG(0x0204) /* Window 0 alpha value 1 */ ++#define S3C_VIDW1ALPHA0 S3C_LCDREG(0x0208) /* Window 1 alpha value 0 */ ++#define S3C_VIDW1ALPHA1 S3C_LCDREG(0x020C) /* Window 1 alpha value 1 */ ++#define S3C_VIDW2ALPHA0 S3C_LCDREG(0x0210) /* Window 2 alpha value 0 */ ++#define S3C_VIDW2ALPHA1 S3C_LCDREG(0x0214) /* Window 2 alpha value 1 */ ++#define S3C_VIDW3ALPHA0 S3C_LCDREG(0x0218) /* Window 3 alpha value 0 */ ++#define S3C_VIDW3ALPHA1 S3C_LCDREG(0x021C) /* Window 3 alpha value 1 */ ++#define S3C_VIDW4ALPHA0 S3C_LCDREG(0x0220) /* Window 4 alpha value 0 */ ++#define S3C_VIDW4ALPHA1 S3C_LCDREG(0x0224) /* Window 4 alpha value 1 */ ++ ++#define S3C_BLENDEQ1 S3C_LCDREG(0x0244) /* Window 1 blending equation control */ ++#define S3C_BLENDEQ2 S3C_LCDREG(0x0248) /* Window 2 blending equation control */ ++#define S3C_BLENDEQ3 S3C_LCDREG(0x024C) /* Window 3 blending equation control */ ++#define S3C_BLENDEQ4 S3C_LCDREG(0x0250) /* Window 4 blending equation control */ ++#define S3C_BLENDCON S3C_LCDREG(0x0260) /* Blending control */ ++ ++/* ++ * Bit Definitions ++*/ ++ ++/* VIDCON0 */ ++#define S3C_VIDCON0_DSI_DISABLE (0 << 30) ++#define S3C_VIDCON0_DSI_ENABLE (1 << 30) ++#define S3C_VIDCON0_SCAN_PROGRESSIVE (0 << 29) ++#define S3C_VIDCON0_SCAN_INTERLACE (1 << 29) ++#define S3C_VIDCON0_SCAN_MASK (1 << 29) ++#define S3C_VIDCON0_VIDOUT_RGB (0 << 26) ++#define S3C_VIDCON0_VIDOUT_ITU (1 << 26) ++#define S3C_VIDCON0_VIDOUT_I80LDI0 (2 << 26) ++#define S3C_VIDCON0_VIDOUT_I80LDI1 (3 << 26) ++#define S3C_VIDCON0_VIDOUT_MASK (3 << 26) ++#define S3C_VIDCON0_PNRMODE_RGB_P (0 << 17) ++#define S3C_VIDCON0_PNRMODE_BGR_P (1 << 17) ++#define S3C_VIDCON0_PNRMODE_RGB_S (2 << 17) ++#define S3C_VIDCON0_PNRMODE_BGR_S (3 << 17) ++#define S3C_VIDCON0_PNRMODE_SHIFT (17) ++#define S3C_VIDCON0_CLKVALUP_ALWAYS (0 << 16) ++#define S3C_VIDCON0_CLKVALUP_START_FRAME (1 << 16) ++#define S3C_VIDCON0_CLKVALUP_MASK (1 << 16) ++#define S3C_VIDCON0_CLKVAL_F(x) (((x) & 0xff) << 6) ++#define S3C_VIDCON0_VCLKEN_NORMAL (0 << 5) ++#define S3C_VIDCON0_VCLKEN_FREERUN (1 << 5) ++#define S3C_VIDCON0_VCLKEN_MASK (1 << 5) ++#define S3C_VIDCON0_CLKDIR_DIRECTED (0 << 4) ++#define S3C_VIDCON0_CLKDIR_DIVIDED (1 << 4) ++#define S3C_VIDCON0_CLKDIR_MASK (1 << 4) ++#define S3C_VIDCON0_CLKSEL_HCLK (0 << 2) ++#define S3C_VIDCON0_CLKSEL_SCLK (1 << 2) ++#define S3C_VIDCON0_CLKSEL_MASK (1 << 2) ++#define S3C_VIDCON0_ENVID_ENABLE (1 << 1) ++#define S3C_VIDCON0_ENVID_DISABLE (0 << 1) ++#define S3C_VIDCON0_ENVID_F_ENABLE (1 << 0) ++#define S3C_VIDCON0_ENVID_F_DISABLE (0 << 0) ++ ++/* VIDCON1 */ ++#define S3C_VIDCON1_IVCLK_FALLING_EDGE (0 << 7) ++#define S3C_VIDCON1_IVCLK_RISING_EDGE (1 << 7) ++#define S3C_VIDCON1_IHSYNC_NORMAL (0 << 6) ++#define S3C_VIDCON1_IHSYNC_INVERT (1 << 6) ++#define S3C_VIDCON1_IVSYNC_NORMAL (0 << 5) ++#define S3C_VIDCON1_IVSYNC_INVERT (1 << 5) ++#define S3C_VIDCON1_IVDEN_NORMAL (0 << 4) ++#define S3C_VIDCON1_IVDEN_INVERT (1 << 4) ++ ++/* VIDCON2 */ ++#define S3C_VIDCON2_EN601_DISABLE (0 << 23) ++#define S3C_VIDCON2_EN601_ENABLE (1 << 23) ++#define S3C_VIDCON2_EN601_MASK (1 << 23) ++#define S3C_VIDCON2_ORGYUV_YCBCR (0 << 8) ++#define S3C_VIDCON2_ORGYUV_CBCRY (1 << 8) ++#define S3C_VIDCON2_ORGYUV_MASK (1 << 8) ++#define S3C_VIDCON2_YUVORD_CBCR (0 << 7) ++#define S3C_VIDCON2_YUVORD_CRCB (1 << 7) ++#define S3C_VIDCON2_YUVORD_MASK (1 << 7) ++ ++/* PRTCON */ ++#define S3C_PRTCON_UPDATABLE (0 << 11) ++#define S3C_PRTCON_PROTECT (1 << 11) ++ ++/* VIDTCON0 */ ++#define S3C_VIDTCON0_VBPDE(x) (((x) & 0xff) << 24) ++#define S3C_VIDTCON0_VBPD(x) (((x) & 0xff) << 16) ++#define S3C_VIDTCON0_VFPD(x) (((x) & 0xff) << 8) ++#define S3C_VIDTCON0_VSPW(x) (((x) & 0xff) << 0) ++ ++/* VIDTCON1 */ ++#define S3C_VIDTCON1_VFPDE(x) (((x) & 0xff) << 24) ++#define S3C_VIDTCON1_HBPD(x) (((x) & 0xff) << 16) ++#define S3C_VIDTCON1_HFPD(x) (((x) & 0xff) << 8) ++#define S3C_VIDTCON1_HSPW(x) (((x) & 0xff) << 0) ++ ++/* VIDTCON2 */ ++#define S3C_VIDTCON2_LINEVAL(x) (((x) & 0x7ff) << 11) ++#define S3C_VIDTCON2_HOZVAL(x) (((x) & 0x7ff) << 0) ++ ++/* Window 0~4 Control - WINCONx */ ++#define S3C_WINCON_DATAPATH_DMA (0 << 22) ++#define S3C_WINCON_DATAPATH_LOCAL (1 << 22) ++#define S3C_WINCON_DATAPATH_MASK (1 << 22) ++#define S3C_WINCON_BUFSEL_0 (0 << 20) ++#define S3C_WINCON_BUFSEL_1 (1 << 20) ++#define S3C_WINCON_BUFSEL_MASK (1 << 20) ++#define S3C_WINCON_BUFAUTO_DISABLE (0 << 19) ++#define S3C_WINCON_BUFAUTO_ENABLE (1 << 19) ++#define S3C_WINCON_BUFAUTO_MASK (1 << 19) ++#define S3C_WINCON_BITSWP_DISABLE (0 << 18) ++#define S3C_WINCON_BITSWP_ENABLE (1 << 18) ++#define S3C_WINCON_BYTSWP_DISABLE (0 << 17) ++#define S3C_WINCON_BYTSWP_ENABLE (1 << 17) ++#define S3C_WINCON_HAWSWP_DISABLE (0 << 16) ++#define S3C_WINCON_HAWSWP_ENABLE (1 << 16) ++#define S3C_WINCON_WSWP_DISABLE (0 << 15) ++#define S3C_WINCON_WSWP_ENABLE (1 << 15) ++#define S3C_WINCON_INRGB_RGB (0 << 13) ++#define S3C_WINCON_INRGB_YUV (1 << 13) ++#define S3C_WINCON_INRGB_MASK (1 << 13) ++#define S3C_WINCON_BURSTLEN_16WORD (0 << 9) ++#define S3C_WINCON_BURSTLEN_8WORD (1 << 9) ++#define S3C_WINCON_BURSTLEN_4WORD (2 << 9) ++#define S3C_WINCON_ALPHA_MULTI_DISABLE (0 << 7) ++#define S3C_WINCON_ALPHA_MULTI_ENABLE (1 << 7) ++#define S3C_WINCON_BLD_PLANE (0 << 6) ++#define S3C_WINCON_BLD_PIXEL (1 << 6) ++#define S3C_WINCON_BLD_MASK (1 << 6) ++#define S3C_WINCON_BPPMODE_1BPP (0 << 2) ++#define S3C_WINCON_BPPMODE_2BPP (1 << 2) ++#define S3C_WINCON_BPPMODE_4BPP (2 << 2) ++#define S3C_WINCON_BPPMODE_8BPP_PAL (3 << 2) ++#define S3C_WINCON_BPPMODE_8BPP (4 << 2) ++#define S3C_WINCON_BPPMODE_16BPP_565 (5 << 2) ++#define S3C_WINCON_BPPMODE_16BPP_A555 (6 << 2) ++#define S3C_WINCON_BPPMODE_18BPP_666 (8 << 2) ++#define S3C_WINCON_BPPMODE_18BPP_A665 (9 << 2) ++#define S3C_WINCON_BPPMODE_24BPP_888 (0xb << 2) ++#define S3C_WINCON_BPPMODE_24BPP_A887 (0xc << 2) ++#define S3C_WINCON_BPPMODE_32BPP (0xd << 2) ++#define S3C_WINCON_BPPMODE_28BPP_A888 (0xd << 2) ++#define S3C_WINCON_BPPMODE_16BPP_A444 (0xe << 2) ++#define S3C_WINCON_BPPMODE_15BPP_555 (0xf << 2) ++#define S3C_WINCON_BPPMODE_MASK (0xf << 2) ++#define S3C_WINCON_ALPHA0_SEL (0 << 1) ++#define S3C_WINCON_ALPHA1_SEL (1 << 1) ++#define S3C_WINCON_ALPHA_SEL_MASK (1 << 1) ++#define S3C_WINCON_ENWIN_DISABLE (0 << 0) ++#define S3C_WINCON_ENWIN_ENABLE (1 << 0) ++ ++/* WINCON1 special */ ++#define S3C_WINCON1_VP_DISABLE (0 << 24) ++#define S3C_WINCON1_VP_ENABLE (1 << 24) ++#define S3C_WINCON1_LOCALSEL_FIMC1 (0 << 23) ++#define S3C_WINCON1_LOCALSEL_VP (1 << 23) ++#define S3C_WINCON1_LOCALSEL_MASK (1 << 23) ++ ++/* VIDOSDxA, VIDOSDxB */ ++#define S3C_VIDOSD_LEFT_X(x) (((x) & 0x7ff) << 11) ++#define S3C_VIDOSD_TOP_Y(x) (((x) & 0x7ff) << 0) ++#define S3C_VIDOSD_RIGHT_X(x) (((x) & 0x7ff) << 11) ++#define S3C_VIDOSD_BOTTOM_Y(x) (((x) & 0x7ff) << 0) ++ ++/* VIDOSD0C, VIDOSDxD */ ++#define S3C_VIDOSD_SIZE(x) (((x) & 0xffffff) << 0) ++ ++/* VIDOSDxC (1~4) */ ++#define S3C_VIDOSD_ALPHA0_R(x) (((x) & 0xf) << 20) ++#define S3C_VIDOSD_ALPHA0_G(x) (((x) & 0xf) << 16) ++#define S3C_VIDOSD_ALPHA0_B(x) (((x) & 0xf) << 12) ++#define S3C_VIDOSD_ALPHA1_R(x) (((x) & 0xf) << 8) ++#define S3C_VIDOSD_ALPHA1_G(x) (((x) & 0xf) << 4) ++#define S3C_VIDOSD_ALPHA1_B(x) (((x) & 0xf) << 0) ++ ++/* Start Address */ ++#define S3C_ADDR_START_VBANK(x) (((x) & 0xff) << 24) ++#define S3C_ADDR_START_VBASEU(x) (((x) & 0xffffff) << 0) ++ ++/* End Address */ ++#define S3C_ADDR_END_VBASEL(x) (((x) & 0xffffff) << 0) ++ ++/* Buffer Size */ ++#define S3C_ADDR_OFFSIZE(x) (((x) & 0x1fff) << 13) ++#define S3C_ADDR_PAGEWIDTH(x) (((x) & 0x1fff) << 0) ++ ++/* VIDINTCON0 */ ++#define S3C_VIDINTCON0_SYSMAINCON_DISABLE (0 << 19) ++#define S3C_VIDINTCON0_SYSMAINCON_ENABLE (1 << 19) ++#define S3C_VIDINTCON0_SYSSUBCON_DISABLE (0 << 18) ++#define S3C_VIDINTCON0_SYSSUBCON_ENABLE (1 << 18) ++#define S3C_VIDINTCON0_SYSIFDONE_DISABLE (0 << 17) ++#define S3C_VIDINTCON0_SYSIFDONE_ENABLE (1 << 17) ++#define S3C_VIDINTCON0_FRAMESEL0_BACK (0 << 15) ++#define S3C_VIDINTCON0_FRAMESEL0_VSYNC (1 << 15) ++#define S3C_VIDINTCON0_FRAMESEL0_ACTIVE (2 << 15) ++#define S3C_VIDINTCON0_FRAMESEL0_FRONT (3 << 15) ++#define S3C_VIDINTCON0_FRAMESEL0_MASK (3 << 15) ++#define S3C_VIDINTCON0_FRAMESEL1_NONE (0 << 13) ++#define S3C_VIDINTCON0_FRAMESEL1_BACK (1 << 13) ++#define S3C_VIDINTCON0_FRAMESEL1_VSYNC (2 << 13) ++#define S3C_VIDINTCON0_FRAMESEL1_FRONT (3 << 13) ++#define S3C_VIDINTCON0_INTFRMEN_DISABLE (0 << 12) ++#define S3C_VIDINTCON0_INTFRMEN_ENABLE (1 << 12) ++#define S3C_VIDINTCON0_FIFOSEL_WIN4 (1 << 11) ++#define S3C_VIDINTCON0_FIFOSEL_WIN3 (1 << 10) ++#define S3C_VIDINTCON0_FIFOSEL_WIN2 (1 << 9) ++#define S3C_VIDINTCON0_FIFOSEL_WIN1 (1 << 6) ++#define S3C_VIDINTCON0_FIFOSEL_WIN0 (1 << 5) ++#define S3C_VIDINTCON0_FIFOSEL_ALL (0x73 << 5) ++#define S3C_VIDINTCON0_FIFOLEVEL_25 (0 << 2) ++#define S3C_VIDINTCON0_FIFOLEVEL_50 (1 << 2) ++#define S3C_VIDINTCON0_FIFOLEVEL_75 (2 << 2) ++#define S3C_VIDINTCON0_FIFOLEVEL_EMPTY (3 << 2) ++#define S3C_VIDINTCON0_FIFOLEVEL_FULL (4 << 2) ++#define S3C_VIDINTCON0_INTFIFO_DISABLE (0 << 1) ++#define S3C_VIDINTCON0_INTFIFO_ENABLE (1 << 1) ++#define S3C_VIDINTCON0_INT_DISABLE (0 << 0) ++#define S3C_VIDINTCON0_INT_ENABLE (1 << 0) ++#define S3C_VIDINTCON0_INT_MASK (1 << 0) ++ ++/* VIDINTCON1 */ ++#define S3C_VIDINTCON1_INTI80PEND (0 << 2) ++#define S3C_VIDINTCON1_INTFRMPEND (1 << 1) ++#define S3C_VIDINTCON1_INTFIFOPEND (1 << 0) ++ ++/* WxKEYCON0 (1~4) */ ++#define S3C_KEYCON0_KEYBLEN_DISABLE (0 << 26) ++#define S3C_KEYCON0_KEYBLEN_ENABLE (1 << 26) ++#define S3C_KEYCON0_KEY_DISABLE (0 << 25) ++#define S3C_KEYCON0_KEY_ENABLE (1 << 25) ++#define S3C_KEYCON0_DIRCON_MATCH_FG (0 << 24) ++#define S3C_KEYCON0_DIRCON_MATCH_BG (1 << 24) ++#define S3C_KEYCON0_COMPKEY(x) (((x) & 0xffffff) << 0) ++ ++/* WxKEYCON1 (1~4) */ ++#define S3C_KEYCON1_COLVAL(x) (((x) & 0xffffff) << 0) ++ ++#endif /* _REGS_FIMD_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,56 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5PC1XX - GPIO register definitions ++ */ ++ ++#ifndef __ASM_PLAT_S5PC1XX_REGS_GPIO_H ++#define __ASM_PLAT_S5PC1XX_REGS_GPIO_H __FILE__ ++ ++/* Base addresses for each of the banks */ ++ ++#define S5PC1XX_GPA0_BASE (S5PC1XX_VA_GPIO + 0x0000) ++#define S5PC1XX_GPA1_BASE (S5PC1XX_VA_GPIO + 0x0020) ++#define S5PC1XX_GPB_BASE (S5PC1XX_VA_GPIO + 0x0040) ++#define S5PC1XX_GPC_BASE (S5PC1XX_VA_GPIO + 0x0060) ++#define S5PC1XX_GPD_BASE (S5PC1XX_VA_GPIO + 0x0080) ++#define S5PC1XX_GPE0_BASE (S5PC1XX_VA_GPIO + 0x00A0) ++#define S5PC1XX_GPE1_BASE (S5PC1XX_VA_GPIO + 0x00C0) ++#define S5PC1XX_GPF0_BASE (S5PC1XX_VA_GPIO + 0x00E0) ++#define S5PC1XX_GPF1_BASE (S5PC1XX_VA_GPIO + 0x0100) ++#define S5PC1XX_GPF2_BASE (S5PC1XX_VA_GPIO + 0x0120) ++#define S5PC1XX_GPF3_BASE (S5PC1XX_VA_GPIO + 0x0140) ++#define S5PC1XX_GPG0_BASE (S5PC1XX_VA_GPIO + 0x0160) ++#define S5PC1XX_GPG1_BASE (S5PC1XX_VA_GPIO + 0x0180) ++#define S5PC1XX_GPG2_BASE (S5PC1XX_VA_GPIO + 0x01A0) ++#define S5PC1XX_GPG3_BASE (S5PC1XX_VA_GPIO + 0x01C0) ++#define S5PC1XX_GPH0_BASE (S5PC1XX_VA_GPIO + 0x0C00) ++#define S5PC1XX_GPH1_BASE (S5PC1XX_VA_GPIO + 0x0C20) ++#define S5PC1XX_GPH2_BASE (S5PC1XX_VA_GPIO + 0x0C40) ++#define S5PC1XX_GPH3_BASE (S5PC1XX_VA_GPIO + 0x0C60) ++#define S5PC1XX_GPI_BASE (S5PC1XX_VA_GPIO + 0x01E0) ++#define S5PC1XX_GPJ0_BASE (S5PC1XX_VA_GPIO + 0x0200) ++#define S5PC1XX_GPJ1_BASE (S5PC1XX_VA_GPIO + 0x0220) ++#define S5PC1XX_GPJ2_BASE (S5PC1XX_VA_GPIO + 0x0240) ++#define S5PC1XX_GPJ3_BASE (S5PC1XX_VA_GPIO + 0x0260) ++#define S5PC1XX_GPJ4_BASE (S5PC1XX_VA_GPIO + 0x0280) ++#define S5PC1XX_GPK0_BASE (S5PC1XX_VA_GPIO + 0x02A0) ++#define S5PC1XX_GPK1_BASE (S5PC1XX_VA_GPIO + 0x02C0) ++#define S5PC1XX_GPK2_BASE (S5PC1XX_VA_GPIO + 0x02E0) ++#define S5PC1XX_GPK3_BASE (S5PC1XX_VA_GPIO + 0x0300) ++#define S5PC1XX_MP00_BASE (S5PC1XX_VA_GPIO + 0x0320) ++#define S5PC1XX_MP01_BASE (S5PC1XX_VA_GPIO + 0x0340) ++#define S5PC1XX_MP02_BASE (S5PC1XX_VA_GPIO + 0x0360) ++#define S5PC1XX_MP03_BASE (S5PC1XX_VA_GPIO + 0x0380) ++#define S5PC1XX_MP04_BASE (S5PC1XX_VA_GPIO + 0x03A0) ++ ++ ++#define S5PC1XX_UHOST (S5PC1XX_VA_GPIO + 0x0B68) ++#define S5PC1XX_PDNEN (S5PC1XX_VA_GPIO + 0x0F80) ++ ++#endif /* __ASM_PLAT_S5PC1XX_REGS_GPIO_H */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/regs-mfc.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/regs-mfc.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/regs-mfc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/regs-mfc.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,167 @@ ++/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-fimv.h ++ * ++ * Register definition file for Samsung MFC V4.0 Interface (FIMV) driver ++ * ++ * PyoungJae Jung, JiUn Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef _REGS_FIMV_H ++#define _REGS_FIMV_H ++ ++#define S3C_FIMV_REG_SIZE (S3C_FIMV_END_ADDR - S3C_FIMV_START_ADDR) ++#define S3C_FIMV_REG_COUNT ((S3C_FIMV_END_ADDR - S3C_FIMV_START_ADDR) / 4) ++ ++#define S3C_FIMVREG(x) (x) ++ ++#define S3C_FIMV_START_ADDR S3C_FIMVREG(0x000) ++#define S3C_FIMV_END_ADDR S3C_FIMVREG(0xd0c) ++ ++#define S3C_FIMV_DMA_START S3C_FIMVREG(0x000) ++#define S3C_FIMV_RESERVE1 /* 0x004 */ ++#define S3C_FIMV_DMA_INTERNAL_ADDR S3C_FIMVREG(0x008) ++#define S3C_FIMV_BOOTCODE_SIZE S3C_FIMVREG(0x00c) ++#define S3C_FIMV_RESERVE2 /* 0x010 */ ++#define S3C_FIMV_DMA_EXTADDR S3C_FIMVREG(0x014) ++#define S3C_FIMV_EXT_BUF_START_ADDR S3C_FIMVREG(0x018) /* StreamBuf0 START */ ++#define S3C_FIMV_EXT_BUF_END_ADDR S3C_FIMVREG(0x01c) /* StreamBuf0 END */ ++#define S3C_FIMV_DMA_INTADDR S3C_FIMVREG(0x020) ++#define S3C_FIMV_HOST_PTR S3C_FIMVREG(0x024) ++#define S3C_FIMV_LAST_DEC S3C_FIMVREG(0x028) ++#define S3C_FIMV_DONE_M S3C_FIMVREG(0x02c) ++#define S3C_FIMV_RESERVE3 /* 0x030 */ ++#define S3C_FIMV_CODEC_PTR S3C_FIMVREG(0x034) ++#define S3C_FIMV_ENC_ENDADDR S3C_FIMVREG(0x038) ++#define S3C_FIMV_RESERVE4 /* 0x03c - 0x40 */ ++#define S3C_FIMV_BITS_ENDIAN S3C_FIMVREG(0x044) ++#define S3C_FIMV_RESERVE5 /* [(0x054 -0x044)/4 - 1 ] */ ++ ++#define S3C_FIMV_DEC_UNIT_SIZE S3C_FIMVREG(0x054) ++#define S3C_FIMV_ENC_UNIT_SIZE S3C_FIMVREG(0x058) ++#define S3C_FIMV_START_BYTE_NUM S3C_FIMVREG(0x05c) ++#define S3C_FIMV_ENC_HEADER_SIZE S3C_FIMVREG(0x060) ++#define S3C_FIMV_RESERVE6 /* [(0x100 -0x060)/4 -1 ] */ ++ ++/* Commn */ ++#define S3C_FIMV_STANDARD_SEL S3C_FIMVREG(0x100) ++#define S3C_FIMV_CH_ID S3C_FIMVREG(0x104) ++#define S3C_FIMV_CPU_RESET S3C_FIMVREG(0x108) ++#define S3C_FIMV_FW_END S3C_FIMVREG(0x10c) ++#define S3C_FIMV_BUS_MASTER S3C_FIMVREG(0x110) ++#define S3C_FIMV_FRAME_START S3C_FIMVREG(0x114) ++#define S3C_FIMV_IMG_SIZE_X S3C_FIMVREG(0x118) ++#define S3C_FIMV_IMG_SIZE_Y S3C_FIMVREG(0x11c) ++#define S3C_FIMV_RESERVE7 /* 0x120 */ ++#define S3C_FIMV_POST_ON S3C_FIMVREG(0x124) ++#define S3C_FIMV_FRAME_RATE S3C_FIMVREG(0x128) ++#define S3C_FIMV_SEQ_START S3C_FIMVREG(0x12c) ++#define S3C_FIMV_SW_RESET S3C_FIMVREG(0x130) ++#define S3C_FIMV_FW_START S3C_FIMVREG(0x134) ++#define S3C_FIMV_ARM_ENDIAN S3C_FIMVREG(0x138) ++#define S3C_FIMV_RESERVE8 /* [(0x200-0x138)/4-1] */ ++ ++/* Firmare loading */ ++#define S3C_FIMV_FW_STT_ADR_0 S3C_FIMVREG(0x200) /* MPEG4 encoder */ ++#define S3C_FIMV_FW_STT_ADR_1 S3C_FIMVREG(0x204) /* MPEG4 decoder */ ++#define S3C_FIMV_FW_STT_ADR_2 S3C_FIMVREG(0x208) /* H.264 encoder */ ++#define S3C_FIMV_FW_STT_ADR_3 S3C_FIMVREG(0x20c) /* H.264 decoder */ ++#define S3C_FIMV_FW_STT_ADR_4 S3C_FIMVREG(0x210) /* VC-1 decoder */ ++#define S3C_FIMV_FW_STT_ADR_5 S3C_FIMVREG(0x214) /* MPEG2 decoder */ ++#define S3C_FIMV_FW_STT_ADR_6 S3C_FIMVREG(0x218) /* H.263 decoder */ ++#define S3C_FIMV_RESERVE9 /* [(0x230-0x218)/4-1] */ ++#define S3C_FIMV_VSP_BUF_ADDR S3C_FIMVREG(0x230) ++#define S3C_FIMV_DB_STT_ADDR S3C_FIMVREG(0x234) ++#define S3C_FIMV_RESERVE10 /* [(0x300-0x234)/4-1] */ ++ ++/* Initencoder */ ++#define S3C_FIMV_PROFILE S3C_FIMVREG(0x300) ++#define S3C_FIMV_IDR_PERIOD S3C_FIMVREG(0x304) ++#define S3C_FIMV_I_PERIOD S3C_FIMVREG(0x308) ++#define S3C_FIMV_FRAME_QP_INIT S3C_FIMVREG(0x30c) ++#define S3C_FIMV_ENTROPY_CON S3C_FIMVREG(0x310) ++#define S3C_FIMV_DEBLOCK_FILTER_OPTION S3C_FIMVREG(0x314) ++#define S3C_FIMV_SHORT_HD_ON S3C_FIMVREG(0x318) ++#define S3C_FIMV_MSLICE_ENA S3C_FIMVREG(0x31c) ++#define S3C_FIMV_MSLICE_SEL S3C_FIMVREG(0x320) ++#define S3C_FIMV_MSLICE_MB S3C_FIMVREG(0x324) ++#define S3C_FIMV_MSLICE_BYTE S3C_FIMVREG(0x328) ++#define S3C_FIMV_RESERVE11 /* [(0x400-0x328)/4-1] */ ++ ++/* Initdecoder */ ++#define S3C_FIMV_DISPLAY_Y_ADR S3C_FIMVREG(0x400) ++#define S3C_FIMV_DISPLAY_C_ADR S3C_FIMVREG(0x404) ++#define S3C_FIMV_DISPLAY_STATUS S3C_FIMVREG(0x408) ++#define S3C_FIMV_HEADER_DONE S3C_FIMVREG(0x40c) ++#define S3C_FIMV_FRAME_NUM S3C_FIMVREG(0x410) ++#define S3C_FIMV_RESERVE12 /* [(0x500-0x410)/4-1] */ ++ ++/* Commn Interrupt */ ++#define S3C_FIMV_INT_OFF S3C_FIMVREG(0x500) ++#define S3C_FIMV_INT_MODE S3C_FIMVREG(0x504) ++#define S3C_FIMV_INT_DONE_CLEAR S3C_FIMVREG(0x508) ++#define S3C_FIMV_OPERATION_DONE S3C_FIMVREG(0x50c) ++#define S3C_FIMV_FW_DONE S3C_FIMVREG(0x510) ++#define S3C_FIMV_INT_STATUS S3C_FIMVREG(0x514) ++#define S3C_FIMV_INT_MASK S3C_FIMVREG(0x518) ++#define S3C_FIMV_RESERVE13 /* [(0x600-0x518)/4-1] */ ++ ++/* Mem onfig */ ++#define S3C_FIMV_TILE_MODE S3C_FIMVREG(0x600) ++#define S3C_FIMV_RESERVE14 /* [(0x700-0x600)/4-1] */ ++ ++/* DEBU (will be removed) */ ++#define S3C_FIMV_ENC_STATUS_RDY S3C_FIMVREG(0x700) ++#define S3C_FIMV_DEC_STATUS_RDY S3C_FIMVREG(0x704) ++#define S3C_FIMV_RESERVE15 /* [(0x800-0x704)/4-1] */ ++ ++/* Run ncoder */ ++#define S3C_FIMV_ENC_CUR_Y_ADR S3C_FIMVREG(0x800) ++#define S3C_FIMV_ENC_CUR_CBCR_ADR S3C_FIMVREG(0x804) ++#define S3C_FIMV_RESERVE16 /* 0x808 */ ++#define S3C_FIMV_ENC_DPB_ADR S3C_FIMVREG(0x80c) ++#define S3C_FIMV_CIR_MB_NUM S3C_FIMVREG(0x810) ++#define S3C_FIMV_RESERVE17 /* [(0x900-0x810)/4-1] */ ++ ++/* Run ecoder */ ++#define S3C_FIMV_DEC_DPB_ADR S3C_FIMVREG(0x900) ++#define S3C_FIMV_DPB_COMV_ADR S3C_FIMVREG(0x904) ++#define S3C_FIMV_POST_ADR S3C_FIMVREG(0x908) ++#define S3C_FIMV_DPB_SIZE S3C_FIMVREG(0x90c) ++#define S3C_FIMV_RESERVE18 /* [(0xA00-0x90C)/4-1] */ ++ ++/* Rat Control */ ++#define S3C_FIMV_RC_CONFIG S3C_FIMVREG(0xa00) ++#define S3C_FIMV_RC_FRAME_RATE S3C_FIMVREG(0xa04) ++#define S3C_FIMV_RC_BIT_RATE S3C_FIMVREG(0xa08) ++#define S3C_FIMV_RC_QBOUND S3C_FIMVREG(0xa0c) ++#define S3C_FIMV_RC_RPARA S3C_FIMVREG(0xa10) ++#define S3C_FIMV_RC_MB_CTRL S3C_FIMVREG(0xa14) ++#define S3C_FIMV_RC_QOUT S3C_FIMVREG(0xa18) ++#define S3C_FIMV_RC_FQCTRL S3C_FIMVREG(0xa1c) ++#define S3C_FIMV_RC_VBFULL S3C_FIMVREG(0xa20) ++#define S3C_FIMV_RC_RSEQ S3C_FIMVREG(0xa24) ++#define S3C_FIMV_RC_ACT_CONTROL S3C_FIMVREG(0xa28) ++#define S3C_FIMV_RC_ACT_SCALE S3C_FIMVREG(0xa2C) ++#define S3C_FIMV_RC_ACT_LIMIT S3C_FIMVREG(0xa30) ++#define S3C_FIMV_RC_ACT_SUM S3C_FIMVREG(0xa34) ++#define S3C_FIMV_RC_ACT_STATIC S3C_FIMVREG(0xa38) ++#define S3C_FIMV_RC_FLAT S3C_FIMVREG(0xa3c) ++#define S3C_FIMV_RC_FLAT_LIMIT S3C_FIMVREG(0xa40) ++#define S3C_FIMV_RC_DARK S3C_FIMVREG(0xa44) ++#define S3C_FIMV_RESERVE19 /* [(0xC00-0xA44)/4-1] */ ++ ++#define S3C_FIMV_CROP_INFO1 S3C_FIMVREG(0xc00) /* Left[15:0]Right[31:16] OFFSET */ ++#define S3C_FIMV_CROP_INFO2 S3C_FIMVREG(0xc04) /* Top[15:0]Bottom[31:16] OFFSET */ ++#define S3C_FIMV_RET_VALUE S3C_FIMVREG(0xc08) /* decoding size for decoder, frame vop type for encoder */ ++#define S3C_FIMV_FRAME_TYPE S3C_FIMVREG(0xc0C) ++#define S3C_FIMV_RESERVE20 /* [(0xD00-0xC0C)/4-1] */ ++ ++#define S3C_FIMV_COMMAND_TYPE S3C_FIMVREG(0xd00) ++#define S3C_FIMV_NUM_EXTRA_BUF S3C_FIMVREG(0xd04) ++#define S3C_FIMV_CODEC_COMMAND S3C_FIMVREG(0xd08) ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/regs-power.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/regs-power.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/regs-power.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/regs-power.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,53 @@ ++/* arch/arm/plat-s5pc1xx/include/plat/regs-power.h ++ * ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S5PC1XX power control register definitions ++*/ ++ ++#ifndef __ASM_ARM_REGS_PWR ++#define __ASM_ARM_REGS_PWR __FILE__ ++ ++/* register for EINT on PM Driver */ ++#define S5P_APM_GPIO (S5PC1XX_PA_GPIO + 0xC00) ++#define S5P_APM_REG(x) ((x) + S5P_APM_GPIO) ++ ++#define S5P_APM_BASE S5P_APM_REG(0x000) ++#define S5P_APM_GPH1CON (0x020) ++#define S5P_APM_GPH1DAT (0x024) ++#define S5P_APM_GPH1PUD (0x028) ++#define S5P_APM_GPH1DRV (0x02C) ++#define S5P_APM_GPH2CON (0x040) ++#define S5P_APM_GPH2DAT (0x044) ++#define S5P_APM_GPH2PUD (0x048) ++#define S5P_APM_GPH2DRV (0x04C) ++#define S5P_APM_GPH3CON (0x060) ++#define S5P_APM_GPH3DAT (0x064) ++#define S5P_APM_GPH3PUD (0x068) ++#define S5P_APM_GPH3DRV (0x06C) ++#define S5P_APM_WEINT0_CON (0x200) ++#define S5P_APM_WEINT1_CON (0x204) ++#define S5P_APM_WEINT2_CON (0x208) ++#define S5P_APM_WEINT3_CON (0x20C) ++#define S5P_APM_WEINT0_FLTCON0 (0x280) ++#define S5P_APM_WEINT0_FLTCON1 (0x284) ++#define S5P_APM_WEINT1_FLTCON0 (0x288) ++#define S5P_APM_WEINT1_FLTCON1 (0x28C) ++#define S5P_APM_WEINT2_FLTCON0 (0x290) ++#define S5P_APM_WEINT2_FLTCON1 (0x294) ++#define S5P_APM_WEINT3_FLTCON0 (0x298) ++#define S5P_APM_WEINT3_FLTCON1 (0x29C) ++#define S5P_APM_WEINT0_MASK (0x300) ++#define S5P_APM_WEINT1_MASK (0x304) ++#define S5P_APM_WEINT2_MASK (0x308) ++#define S5P_APM_WEINT3_MASK (0x30C) ++#define S5P_APM_WEINT0_PEND (0x340) ++#define S5P_APM_WEINT1_PEND (0x344) ++#define S5P_APM_WEINT2_PEND (0x348) ++#define S5P_APM_WEINT3_PEND (0x34C) ++ ++#endif /* __ASM_ARM_REGS_PWR */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/regs-sys-timer.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/regs-sys-timer.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/regs-sys-timer.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/regs-sys-timer.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,61 @@ ++/* arch/arm/plat-s5pc1xx/include/plat/regs-sys-timer.h ++ * ++ * Copyright (c) 2008 Samsung Electronics ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S5PC1XX System Timer configuration ++*/ ++ ++#ifndef __ASM_ARCH_REGS_SYS_TIMER_H ++#define __ASM_ARCH_REGS_SYS_TIMER_H ++ ++#define S3C_SYSTIMERREG(x) (S3C_VA_SYSTIMER + (x)) ++ ++#define S3C_SYSTIMER_TCFG S3C_SYSTIMERREG(0x00) ++#define S3C_SYSTIMER_TCON S3C_SYSTIMERREG(0x04) ++#define S3C_SYSTIMER_TCNTB S3C_SYSTIMERREG(0x08) ++#define S3C_SYSTIMER_TCNTO S3C_SYSTIMERREG(0x0c) ++#define S3C_SYSTIMER_ICNTB S3C_SYSTIMERREG(0x10) ++#define S3C_SYSTIMER_ICNTO S3C_SYSTIMERREG(0x14) ++#define S3C_SYSTIMER_INT_CSTAT S3C_SYSTIMERREG(0x18) ++ ++/* Value for TCFG */ ++#define S3C_SYSTIMER_TCLK_MASK (3<<12) ++#define S3C_SYSTIMER_TCLK_XXTI (0<<12) ++#define S3C_SYSTIMER_TCLK_RTC (1<<12) ++#define S3C_SYSTIMER_TCLK_USB (2<<12) ++#define S3C_SYSTIMER_TCLK_PCLK (3<<12) ++ ++#define S3C_SYSTIMER_DIV_MASK (7<<8) ++#define S3C_SYSTIMER_DIV_1 (0<<8) ++#define S3C_SYSTIMER_DIV_2 (1<<8) ++#define S3C_SYSTIMER_DIV_4 (2<<8) ++#define S3C_SYSTIMER_DIV_8 (3<<8) ++#define S3C_SYSTIMER_DIV_16 (4<<8) ++ ++#define S3C_SYSTIMER_INT_IWIE (1<<7) ++#define S3C_SYSTIMER_INT_TWIE (1<<6) ++ ++#define S3C_SYSTIMER_TARGET_HZ 1000 ++#define S3C_SYSTIMER_PRESCALER 5 ++#define S3C_SYSTIMER_PRESCALER_MASK (0x3f<<0) ++ ++/* value for TCON */ ++#define S3C_SYSTIMER_INT_AUTO (1<<5) ++#define S3C_SYSTIMER_INT_IMM (1<<4) ++#define S3C_SYSTIMER_INT_START (1<<3) ++#define S3C_SYSTIMER_AUTO_RELOAD (1<<2) ++#define S3C_SYSTIMER_IMM_UPDATE (1<<1) ++#define S3C_SYTIMERS_START (1<<0) ++ ++/* Value for INT_CSTAT */ ++#define S3C_SYSTIMER_INT_TCON (1<<4) ++#define S3C_SYSTIMER_INT_ICNTB (1<<3) ++#define S3C_SYSTIMER_INT_TCNTB (1<<2) ++#define S3C_SYSTIMER_INT_STATS (1<<1) ++#define S3C_SYSTIMER_INT_ICNTEIE (1<<0) ++ ++#endif /* __ASM_ARCH_REGS_TIMER_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,27 @@ ++/* arch/arm/plat-s5pc1xx/include/plat/s5pc100.h ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * Header file for s5pc100 cpu support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++/* Common init code for S5PC100 related SoCs */ ++ ++extern void s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); ++extern void s5pc100_register_clocks(void); ++extern void s5pc100_setup_clocks(void); ++ ++extern int s5pc100_init(void); ++extern void s5pc100_init_irq(void); ++extern void s5pc100_map_io(void); ++extern void s5pc100_init_clocks(int xtal); ++ ++#define s5pc100_init_uarts s5pc100_common_init_uarts ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/irq-eint.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/irq-eint.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/irq-eint.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/irq-eint.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,269 @@ ++/* arch/arm/plat-s5pc1xx/irq-eint.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5PC1XX - Interrupt handling for IRQ_EINT(x) ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define S5PC1XX_GPIOREG(x) (S5PC1XX_VA_GPIO + (x)) ++ ++#define S5PC1XX_EINT0CON S5PC1XX_GPIOREG(0xE00) /* EINT0 ~ EINT7 */ ++#define S5PC1XX_EINT1CON S5PC1XX_GPIOREG(0xE04) /* EINT8 ~ EINT15 */ ++#define S5PC1XX_EINT2CON S5PC1XX_GPIOREG(0xE08) /* EINT16 ~ EINT23 */ ++#define S5PC1XX_EINT3CON S5PC1XX_GPIOREG(0xE0C) /* EINT24 ~ EINT31 */ ++#define S5PC1XX_EINTCON(x) (S5PC1XX_EINT0CON+x*0x4) /* EINT0 ~ EINT31 */ ++ ++#define S5PC1XX_EINT0FLTCON0 S5PC1XX_GPIOREG(0xE80) /* EINT0 ~ EINT3 */ ++#define S5PC1XX_EINT0FLTCON1 S5PC1XX_GPIOREG(0xE84) ++#define S5PC1XX_EINT1FLTCON0 S5PC1XX_GPIOREG(0xE88) /* EINT8 ~ EINT11 */ ++#define S5PC1XX_EINT1FLTCON1 S5PC1XX_GPIOREG(0xE8C) ++#define S5PC1XX_EINT2FLTCON0 S5PC1XX_GPIOREG(0xE90) ++#define S5PC1XX_EINT2FLTCON1 S5PC1XX_GPIOREG(0xE94) ++#define S5PC1XX_EINT3FLTCON0 S5PC1XX_GPIOREG(0xE98) ++#define S5PC1XX_EINT3FLTCON1 S5PC1XX_GPIOREG(0xE9C) ++#define S5PC1XX_EINTFLTCON(x) (S5PC1XX_EINT0FLTCON0+x*0x4) /* EINT0 ~ EINT31 */ ++ ++#define S5PC1XX_EINT0MASK S5PC1XX_GPIOREG(0xF00) /* EINT0 ~ EINT7 */ ++#define S5PC1XX_EINT1MASK S5PC1XX_GPIOREG(0xF04) /* EINT8 ~ EINT15 */ ++#define S5PC1XX_EINT2MASK S5PC1XX_GPIOREG(0xF08) /* EINT16 ~ EINT23 */ ++#define S5PC1XX_EINT3MASK S5PC1XX_GPIOREG(0xF0C) /* EINT24 ~ EINT31 */ ++#define S5PC1XX_EINTMASK(x) (S5PC1XX_EINT0MASK+x*0x4) /* EINT0 ~ EINT31 */ ++ ++#define S5PC1XX_EINT0PEND S5PC1XX_GPIOREG(0xF40) /* EINT0 ~ EINT7 */ ++#define S5PC1XX_EINT1PEND S5PC1XX_GPIOREG(0xF44) /* EINT8 ~ EINT15 */ ++#define S5PC1XX_EINT2PEND S5PC1XX_GPIOREG(0xF48) /* EINT16 ~ EINT23 */ ++#define S5PC1XX_EINT3PEND S5PC1XX_GPIOREG(0xF4C) /* EINT24 ~ EINT31 */ ++#define S5PC1XX_EINTPEND(x) (S5PC1XX_EINT0PEND+x*04) /* EINT0 ~ EINT31 */ ++ ++#define eint_offset(irq) ((irq) < IRQ_EINT16_31 ? ((irq)-IRQ_EINT0) : \ ++ ((irq-S3C_IRQ_EINT_BASE)+IRQ_EINT16_31-IRQ_EINT0)) ++ ++#define eint_irq_to_bit(irq) (1 << (eint_offset(irq) & 0x7)) ++ ++#define eint_conf_reg(irq) ((eint_offset(irq)) >> 3) ++#define eint_filt_reg(irq) ((eint_offset(irq)) >> 2) ++#define eint_mask_reg(irq) ((eint_offset(irq)) >> 3) ++#define eint_pend_reg(irq) ((eint_offset(irq)) >> 3) ++ ++static inline void s3c_irq_eint_mask(unsigned int irq) ++{ ++ u32 mask; ++ ++ mask = __raw_readl(S5PC1XX_EINTMASK(eint_mask_reg(irq))); ++ mask |= eint_irq_to_bit(irq); ++ __raw_writel(mask, S5PC1XX_EINTMASK(eint_mask_reg(irq))); ++} ++ ++static void s3c_irq_eint_unmask(unsigned int irq) ++{ ++ u32 mask; ++ ++ mask = __raw_readl(S5PC1XX_EINTMASK(eint_mask_reg(irq))); ++ mask &= ~(eint_irq_to_bit(irq)); ++ __raw_writel(mask, S5PC1XX_EINTMASK(eint_mask_reg(irq))); ++} ++ ++static inline void s3c_irq_eint_ack(unsigned int irq) ++{ ++ __raw_writel(eint_irq_to_bit(irq), S5PC1XX_EINTPEND(eint_pend_reg(irq))); ++} ++ ++static void s3c_irq_eint_maskack(unsigned int irq) ++{ ++ /* compiler should in-line these */ ++ s3c_irq_eint_mask(irq); ++ s3c_irq_eint_ack(irq); ++} ++ ++static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) ++{ ++ int offs = eint_offset(irq); ++ int shift; ++ u32 ctrl, mask; ++ u32 newvalue = 0; ++ ++ switch (type) { ++ case IRQ_TYPE_NONE: ++ printk(KERN_WARNING "No edge setting!\n"); ++ break; ++ ++ case IRQ_TYPE_EDGE_RISING: ++ newvalue = S3C2410_EXTINT_RISEEDGE; ++ break; ++ ++ case IRQ_TYPE_EDGE_FALLING: ++ newvalue = S3C2410_EXTINT_FALLEDGE; ++ break; ++ ++ case IRQ_TYPE_EDGE_BOTH: ++ newvalue = S3C2410_EXTINT_BOTHEDGE; ++ break; ++ ++ case IRQ_TYPE_LEVEL_LOW: ++ newvalue = S3C2410_EXTINT_LOWLEV; ++ break; ++ ++ case IRQ_TYPE_LEVEL_HIGH: ++ newvalue = S3C2410_EXTINT_HILEV; ++ break; ++ ++ default: ++ printk(KERN_ERR "No such irq type %d", type); ++ return -1; ++ } ++ ++ shift = (offs & 0x7) * 4; ++ mask = 0x7 << shift; ++ ++ ctrl = __raw_readl(S5PC1XX_EINTCON(eint_conf_reg(irq))); ++ ctrl &= ~mask; ++ ctrl |= newvalue << shift; ++ __raw_writel(ctrl, S5PC1XX_EINTCON(eint_conf_reg(irq))); ++ ++ if((0 <= offs) && (offs < 8)) ++ s3c_gpio_cfgpin(S5PC1XX_GPH0(offs&0x7), 0x2<<((offs&0x7)*4)); ++ else if((8 <= offs) && (offs < 16)) ++ s3c_gpio_cfgpin(S5PC1XX_GPH1(offs&0x7), 0x2<<((offs&0x7)*4)); ++ else if((16 <= offs) && (offs < 24)) ++ s3c_gpio_cfgpin(S5PC1XX_GPH2(offs&0x7), 0x2<<((offs&0x7)*4)); ++ else if((24 <= offs) && (offs < 32)) ++ s3c_gpio_cfgpin(S5PC1XX_GPH3(offs&0x7), 0x2<<((offs&0x7)*4)); ++ else ++ printk(KERN_ERR "No such irq number %d", offs); ++ ++ return 0; ++} ++ ++ ++static struct irq_chip s3c_irq_eint = { ++ .name = "s3c-eint", ++ .mask = s3c_irq_eint_mask, ++ .unmask = s3c_irq_eint_unmask, ++ .mask_ack = s3c_irq_eint_maskack, ++ .ack = s3c_irq_eint_ack, ++ .set_type = s3c_irq_eint_set_type, ++}; ++ ++/* s3c_irq_demux_eint ++ * ++ * This function demuxes the IRQ from the group0 external interrupts, ++ * from IRQ_EINT(16) to IRQ_EINT(31). It is designed to be inlined into ++ * the specific handlers s3c_irq_demux_eintX_Y. ++ */ ++static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end) ++{ ++ u32 status = __raw_readl(S5PC1XX_EINTPEND((start >> 3))); ++ u32 mask = __raw_readl(S5PC1XX_EINTMASK((start >> 3))); ++ unsigned int irq; ++ ++ status &= ~mask; ++ status >>= start; ++ status &= (1 << (end - start + 1)) - 1; ++ ++ for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) { ++ if (status & 1) ++ generic_handle_irq(irq); ++ ++ status >>= 1; ++ } ++} ++ ++static void s3c_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_eint(16, 23); ++ s3c_irq_demux_eint(24, 31); ++} ++ ++/*---------------------------- EINT0 ~ EINT15 -------------------------------------*/ ++static void s3c_irq_vic_eint_mask(unsigned int irq) ++{ ++ void __iomem *base = get_irq_chip_data(irq); ++ ++ s3c_irq_eint_mask(irq); ++ ++ irq &= 31; ++ writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); ++} ++ ++ ++static void s3c_irq_vic_eint_unmask(unsigned int irq) ++{ ++ void __iomem *base = get_irq_chip_data(irq); ++ ++ s3c_irq_eint_unmask(irq); ++ ++ irq &= 31; ++ writel(1 << irq, base + VIC_INT_ENABLE); ++} ++ ++ ++static inline void s3c_irq_vic_eint_ack(unsigned int irq) ++{ ++ __raw_writel(eint_irq_to_bit(irq), S5PC1XX_EINTPEND(eint_pend_reg(irq))); ++} ++ ++ ++static void s3c_irq_vic_eint_maskack(unsigned int irq) ++{ ++ /* compiler should in-line these */ ++ s3c_irq_vic_eint_mask(irq); ++ s3c_irq_vic_eint_ack(irq); ++} ++ ++ ++static struct irq_chip s3c_irq_vic_eint = { ++ .name = "s3c_vic_eint", ++ .mask = s3c_irq_vic_eint_mask, ++ .unmask = s3c_irq_vic_eint_unmask, ++ .mask_ack = s3c_irq_vic_eint_maskack, ++ .ack = s3c_irq_vic_eint_ack, ++ .set_type = s3c_irq_eint_set_type, ++}; ++ ++ ++int __init s5pc1xx_init_irq_eint(void) ++{ ++ int irq; ++ ++ for (irq = IRQ_EINT0; irq <= IRQ_EINT15; irq++) { ++ set_irq_chip(irq, &s3c_irq_vic_eint); ++ } ++ ++ for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) { ++ set_irq_chip(irq, &s3c_irq_eint); ++ set_irq_handler(irq, handle_level_irq); ++ set_irq_flags(irq, IRQF_VALID); ++ } ++ ++ set_irq_chained_handler(IRQ_EINT16_31, s3c_irq_demux_eint16_31); ++ return 0; ++} ++ ++arch_initcall(s5pc1xx_init_irq_eint); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/irq.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/irq.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/irq.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/irq.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,258 @@ ++/* arch/arm/plat-s5pc1xx/irq.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5PC1XX - Interrupt handling ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++ ++/* Timer interrupt handling */ ++ ++static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq) ++{ ++ generic_handle_irq(sub_irq); ++} ++ ++static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_timer(irq, IRQ_TIMER0); ++} ++ ++static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_timer(irq, IRQ_TIMER1); ++} ++ ++static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_timer(irq, IRQ_TIMER2); ++} ++ ++static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_timer(irq, IRQ_TIMER3); ++} ++ ++static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc) ++{ ++ s3c_irq_demux_timer(irq, IRQ_TIMER4); ++} ++ ++/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ ++ ++static void s3c_irq_timer_mask(unsigned int irq) ++{ ++ u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); ++ ++ reg &= 0x1f; /* mask out pending interrupts */ ++ reg &= ~(1 << (irq - IRQ_TIMER0)); ++ __raw_writel(reg, S3C64XX_TINT_CSTAT); ++} ++ ++static void s3c_irq_timer_unmask(unsigned int irq) ++{ ++ u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); ++ ++ reg &= 0x1f; /* mask out pending interrupts */ ++ reg |= 1 << (irq - IRQ_TIMER0); ++ __raw_writel(reg, S3C64XX_TINT_CSTAT); ++} ++ ++static void s3c_irq_timer_ack(unsigned int irq) ++{ ++ u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); ++ ++ reg &= 0x1f; ++ reg |= (1 << 5) << (irq - IRQ_TIMER0); ++ __raw_writel(reg, S3C64XX_TINT_CSTAT); ++} ++ ++static struct irq_chip s3c_irq_timer = { ++ .name = "s3c-timer", ++ .mask = s3c_irq_timer_mask, ++ .unmask = s3c_irq_timer_unmask, ++ .ack = s3c_irq_timer_ack, ++}; ++ ++struct uart_irq { ++ void __iomem *regs; ++ unsigned int base_irq; ++ unsigned int parent_irq; ++}; ++ ++/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] ++ * are consecutive when looking up the interrupt in the demux routines. ++ */ ++static struct uart_irq uart_irqs[] = { ++ [0] = { ++ .regs = S3C_VA_UART0, ++ .base_irq = IRQ_S3CUART_BASE0, ++ .parent_irq = IRQ_UART0, ++ }, ++ [1] = { ++ .regs = S3C_VA_UART1, ++ .base_irq = IRQ_S3CUART_BASE1, ++ .parent_irq = IRQ_UART1, ++ }, ++ [2] = { ++ .regs = S3C_VA_UART2, ++ .base_irq = IRQ_S3CUART_BASE2, ++ .parent_irq = IRQ_UART2, ++ }, ++ [3] = { ++ .regs = S3C_VA_UART3, ++ .base_irq = IRQ_S3CUART_BASE3, ++ .parent_irq = IRQ_UART3, ++ }, ++}; ++ ++static inline void __iomem *s3c_irq_uart_base(unsigned int irq) ++{ ++ struct uart_irq *uirq = get_irq_chip_data(irq); ++ return uirq->regs; ++} ++ ++static inline unsigned int s3c_irq_uart_bit(unsigned int irq) ++{ ++ return irq & 3; ++} ++ ++/* UART interrupt registers, not worth adding to seperate include header */ ++#define S5P_UINTP 0x30 ++#define S5P_UINTSP 0x34 ++#define S5P_UINTM 0x38 ++ ++static void s3c_irq_uart_mask(unsigned int irq) ++{ ++ void __iomem *regs = s3c_irq_uart_base(irq); ++ unsigned int bit = s3c_irq_uart_bit(irq); ++ u32 reg; ++ ++ reg = __raw_readl(regs + S5P_UINTM); ++ reg |= (1 << bit); ++ __raw_writel(reg, regs + S5P_UINTM); ++} ++ ++static void s3c_irq_uart_maskack(unsigned int irq) ++{ ++ void __iomem *regs = s3c_irq_uart_base(irq); ++ unsigned int bit = s3c_irq_uart_bit(irq); ++ u32 reg; ++ ++ reg = __raw_readl(regs + S5P_UINTM); ++ reg |= (1 << bit); ++ __raw_writel(reg, regs + S5P_UINTM); ++ __raw_writel(1 << bit, regs + S5P_UINTP); ++} ++ ++static void s3c_irq_uart_unmask(unsigned int irq) ++{ ++ void __iomem *regs = s3c_irq_uart_base(irq); ++ unsigned int bit = s3c_irq_uart_bit(irq); ++ u32 reg; ++ ++ reg = __raw_readl(regs + S5P_UINTM); ++ reg &= ~(1 << bit); ++ __raw_writel(reg, regs + S5P_UINTM); ++} ++ ++static void s3c_irq_uart_ack(unsigned int irq) ++{ ++ void __iomem *regs = s3c_irq_uart_base(irq); ++ unsigned int bit = s3c_irq_uart_bit(irq); ++ ++ __raw_writel(1 << bit, regs + S5P_UINTP); ++} ++ ++static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) ++{ ++ struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0]; ++ u32 pend = __raw_readl(uirq->regs + S5P_UINTP); ++ int base = uirq->base_irq; ++ ++ if (pend & (1 << 0)) ++ generic_handle_irq(base); ++ if (pend & (1 << 1)) ++ generic_handle_irq(base + 1); ++ if (pend & (1 << 2)) ++ generic_handle_irq(base + 2); ++ if (pend & (1 << 3)) ++ generic_handle_irq(base + 3); ++} ++ ++static struct irq_chip s3c_irq_uart = { ++ .name = "s3c-uart", ++ .mask = s3c_irq_uart_mask, ++ .unmask = s3c_irq_uart_unmask, ++ .mask_ack = s3c_irq_uart_maskack, ++ .ack = s3c_irq_uart_ack, ++}; ++ ++static void __init s5p_uart_irq(struct uart_irq *uirq) ++{ ++ void *reg_base = uirq->regs; ++ unsigned int irq; ++ int offs; ++ ++ /* mask all interrupts at the start. */ ++ __raw_writel(0xf, reg_base + S5P_UINTM); ++ ++ for (offs = 0; offs < 3; offs++) { ++ irq = uirq->base_irq + offs; ++ ++ set_irq_chip(irq, &s3c_irq_uart); ++ set_irq_chip_data(irq, uirq); ++ set_irq_handler(irq, handle_level_irq); ++ set_irq_flags(irq, IRQF_VALID); ++ } ++ ++ set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); ++} ++ ++void __init s5pc1xx_init_irq(u32 vic0_valid, u32 vic1_valid, u32 vic2_valid) ++{ ++ int uart, irq; ++ ++ printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); ++ ++ /* initialise the pair of VICs */ ++ vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid); ++ vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid); ++ vic_init(S3C_VA_VIC2, S3C_VIC2_BASE, vic2_valid); ++ ++ /* add the timer sub-irqs */ ++ ++ set_irq_chained_handler(IRQ_TIMER0, s3c_irq_demux_timer0); ++ set_irq_chained_handler(IRQ_TIMER1, s3c_irq_demux_timer1); ++ set_irq_chained_handler(IRQ_TIMER2, s3c_irq_demux_timer2); ++ set_irq_chained_handler(IRQ_TIMER3, s3c_irq_demux_timer3); ++ set_irq_chained_handler(IRQ_TIMER4, s3c_irq_demux_timer4); ++ ++ for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) { ++ set_irq_chip(irq, &s3c_irq_timer); ++ set_irq_handler(irq, handle_level_irq); ++ set_irq_flags(irq, IRQF_VALID); ++ } ++ ++ for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++) ++ s5p_uart_irq(&uart_irqs[uart]); ++} ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/ltc3714.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/ltc3714.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/ltc3714.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/ltc3714.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,217 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#define PMIC_ARM 0 ++#define PMIC_INT 1 ++#define PMIC_BOTH 2 ++ ++#define SER_BIT 0 ++#define SRCLK_BIT 1 ++#define RCLK_ARM_BIT 2 ++#define RCLK_INT_BIT 3 ++#define VID_CTRL_BIT 4 ++ ++unsigned int step_curr; ++ ++enum PMIC_VOLTAGE { ++ VOUT_1_00, ++ VOUT_1_05, ++ VOUT_1_10, ++ VOUT_1_15, ++ VOUT_1_20, ++ VOUT_1_25, ++ VOUT_1_30, ++ VOUT_1_35, ++ VOUT_1_40, ++ VOUT_1_45, ++ VOUT_1_50 ++}; ++ ++/* ltc3714 voltage table */ ++static const unsigned int voltage_table[11] = { ++ 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9, ++ 0x8, 0x7, 0x6, 0x5, ++}; ++ ++ ++/* frequency voltage matching table */ ++static const unsigned int frequency_match[][3] = { ++/* frequency, Mathced VDD ARM voltage , Matched VDD INT*/ ++ {666000, VOUT_1_20, VOUT_1_20}, ++ {333000, VOUT_1_10, VOUT_1_20}, ++ {166500, VOUT_1_05, VOUT_1_20}, ++}; ++ ++/* LTC3714 Setting Routine */ ++static int ltc3714_gpio_setting(void) ++{ ++ int iter, err; ++ ++ for(iter = SER_BIT; iter <= VID_CTRL_BIT ; iter++) { ++ if (gpio_is_valid(S5PC1XX_GPH0(iter))) { ++ ++ err = gpio_request(S5PC1XX_GPH0(iter), "GPH0"); ++ ++ if (err) { ++ printk(KERN_ERR "failed to request GPF0 port(%d) for LTC3714 control\n", iter); ++ return err; ++ } ++ ++ if(iter == VID_CTRL_BIT) { ++ gpio_direction_output(S5PC1XX_GPH0(iter), 1); ++ udelay(10); ++ } else { ++ gpio_direction_output(S5PC1XX_GPH0(iter), 0); ++ } ++ ++ s3c_gpio_setpull(S5PC1XX_GPH0(iter), S3C_GPIO_PULL_NONE); ++ ++ } else { ++ printk(KERN_ERR "Invalid GPIO (%d) number\n", S5PC1XX_GPH0(iter)); ++ } ++ } ++ ++ return 0; ++} ++ ++static int set_ltc3714(unsigned int pwr, unsigned int index) ++{ ++ int iter = 0; ++ int voltage; ++ int gpio_val; ++ ++ if(pwr == PMIC_ARM) { ++ voltage = frequency_match[index][pwr + 1]; ++ gpio_val = voltage_table[voltage]; ++ gpio_set_value(S5PC1XX_GPH0(RCLK_ARM_BIT), 0); ++ gpio_set_value(S5PC1XX_GPH0(VID_CTRL_BIT), 1); ++ ++ udelay(10); ++ ++ } else if(pwr == PMIC_INT) { ++ voltage = frequency_match[index][pwr + 1]; ++ gpio_val = voltage_table[voltage]; ++ gpio_set_value(S5PC1XX_GPH0(RCLK_INT_BIT), 0); ++ gpio_set_value(S5PC1XX_GPH0(SRCLK_BIT), 0); ++ gpio_set_value(S5PC1XX_GPH0(VID_CTRL_BIT), 1); ++ ++ udelay(10); ++ ++ gpio_set_value(S5PC1XX_GPH0(RCLK_INT_BIT), 0); ++ ++ } else if(pwr == PMIC_BOTH) { ++ voltage = frequency_match[index][1]; ++ gpio_val = voltage_table[voltage]; ++ gpio_set_value(S5PC1XX_GPH0(RCLK_ARM_BIT), 0); ++ gpio_set_value(S5PC1XX_GPH0(RCLK_INT_BIT), 0); ++ gpio_set_value(S5PC1XX_GPH0(VID_CTRL_BIT), 1); ++ ++ udelay(10); ++ ++ }else { ++ printk("[error]: set_power, check mode [pwr] value\n"); ++ return -EINVAL; ++ } ++ ++ //printk("gpio_val = 0x%x\n", gpio_val); ++ for (iter = 8; iter > 0; iter --) { ++ gpio_set_value(S5PC1XX_GPH0(SRCLK_BIT), 0); ++ gpio_set_value(S5PC1XX_GPH0(SER_BIT), (gpio_val>>(iter-1))&0x01); ++ udelay(10); ++ gpio_set_value(S5PC1XX_GPH0(SRCLK_BIT), 1); ++ udelay(10); ++ } ++ ++ gpio_set_value(S5PC1XX_GPH0(SRCLK_BIT), 0); ++ gpio_set_value(S5PC1XX_GPH0(SER_BIT), 0); ++ ++ udelay(10); ++ ++ gpio_set_value(S5PC1XX_GPH0(VID_CTRL_BIT), 0); ++ ++ switch(pwr) { ++ case PMIC_ARM: ++ gpio_set_value(S5PC1XX_GPH0(RCLK_ARM_BIT), 1); ++ udelay(10); ++ gpio_set_value(S5PC1XX_GPH0(RCLK_ARM_BIT), 0); ++ break; ++ case PMIC_INT: ++ gpio_set_value(S5PC1XX_GPH0(RCLK_INT_BIT), 1); ++ udelay(10); ++ gpio_set_value(S5PC1XX_GPH0(RCLK_INT_BIT), 0); ++ break; ++ case PMIC_BOTH: ++ gpio_set_value(S5PC1XX_GPH0(RCLK_ARM_BIT), 1); ++ gpio_set_value(S5PC1XX_GPH0(RCLK_INT_BIT), 1); ++ udelay(10); ++ gpio_set_value(S5PC1XX_GPH0(RCLK_ARM_BIT), 0); ++ gpio_set_value(S5PC1XX_GPH0(RCLK_INT_BIT), 0); ++ break; ++ default: ++ break; ++ ++ } ++ ++ udelay(10); ++ //printk("%s : end\n", __FUNCTION__); ++ return 0; ++} ++ ++static int find_voltage(int freq) ++{ ++ int index = 0; ++ ++ if(freq > frequency_match[0][0]){ ++ printk(KERN_ERR "frequecy is over then support frequency\n"); ++ return 0; ++ } ++ ++ for(index = 0 ; index < ARRAY_SIZE(frequency_match) ; index++){ ++ if(freq >= frequency_match[index][0]) ++ return index; ++ } ++ ++ printk("Cannot find matched voltage on table\n"); ++ ++ return 0; ++} ++ ++int set_power(unsigned int freq) ++{ ++ int index; ++ ++ index = find_voltage(freq); ++ ++ printk("%s : index = %d\n", __FUNCTION__, index); ++ if(step_curr != index) { ++ set_ltc3714(PMIC_ARM, index); ++ set_ltc3714(PMIC_INT, index); ++ ++ step_curr = index; ++ } ++ return 0; ++} ++ ++EXPORT_SYMBOL(set_power); ++ ++void ltc3714_init(void) ++{ ++ step_curr = 0; ++ ltc3714_gpio_setting(); ++ set_power(666000); ++} ++ ++EXPORT_SYMBOL(ltc3714_init); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/pm.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/pm.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/pm.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/pm.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,667 @@ ++/* linux/arch/arm/plat-s3c24xx/pm.c ++ * ++ * Copyright (c) 2004,2006 Simtec Electronics ++ * Ben Dooks ++ * ++ * S3C24XX Power Manager (Suspend-To-RAM) support ++ * ++ * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * Parts based on arch/arm/mach-pxa/pm.c ++ * ++ * Thanks to Dimitry Andric for debugging ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++ ++/* for external use */ ++ ++unsigned long s5pc1xx_pm_flags; ++void __iomem *weint_base; ++ ++enum PLL_TYPE ++{ ++ PM_APLL, ++ PM_MPLL, ++ PM_EPLL, ++ PM_HPLL ++}; ++ ++#define PFX "s5pc1xx-pm: " ++static struct sleep_save core_save[] = { ++ SAVE_ITEM(S5P_CLK_SRC0), ++ SAVE_ITEM(S5P_CLK_SRC1), ++ SAVE_ITEM(S5P_CLK_SRC2), ++ SAVE_ITEM(S5P_CLK_SRC3), ++ ++ SAVE_ITEM(S5P_CLK_DIV0), ++ SAVE_ITEM(S5P_CLK_DIV1), ++ SAVE_ITEM(S5P_CLK_DIV2), ++ SAVE_ITEM(S5P_CLK_DIV3), ++ SAVE_ITEM(S5P_CLK_DIV4), ++ ++ SAVE_ITEM(S5P_CLK_OUT), ++ ++ SAVE_ITEM(S5P_CLKGATE_D00), ++ SAVE_ITEM(S5P_CLKGATE_D01), ++ SAVE_ITEM(S5P_CLKGATE_D02), ++ ++ SAVE_ITEM(S5P_CLKGATE_D10), ++ SAVE_ITEM(S5P_CLKGATE_D11), ++ SAVE_ITEM(S5P_CLKGATE_D12), ++ SAVE_ITEM(S5P_CLKGATE_D13), ++ SAVE_ITEM(S5P_CLKGATE_D14), ++ SAVE_ITEM(S5P_CLKGATE_D15), ++ ++ SAVE_ITEM(S5P_CLKGATE_D20), ++ ++ SAVE_ITEM(S5P_SCLKGATE0), ++ SAVE_ITEM(S5P_SCLKGATE1), ++ ++ SAVE_ITEM(S5P_MEM_SYS_CFG), ++ SAVE_ITEM(S5P_CAM_MUX_SEL), ++ SAVE_ITEM(S5P_MIXER_OUT_SEL), ++ ++ SAVE_ITEM(S5P_LPMP_MODE_SEL), ++ SAVE_ITEM(S5P_MIPI_PHY_CON0), ++ SAVE_ITEM(S5P_MIPI_PHY_CON1), ++ SAVE_ITEM(S5P_HDMI_PHY_CON0), ++}; ++ ++static struct sleep_save gpio_save[] = { ++ SAVE_ITEM(S5PC1XX_GPA0CON), ++ SAVE_ITEM(S5PC1XX_GPA0DAT), ++ SAVE_ITEM(S5PC1XX_GPA0PUD), ++ SAVE_ITEM(S5PC1XX_GPA1CON), ++ SAVE_ITEM(S5PC1XX_GPA1DAT), ++ SAVE_ITEM(S5PC1XX_GPA1PUD), ++ SAVE_ITEM(S5PC1XX_GPBCON), ++ SAVE_ITEM(S5PC1XX_GPBDAT), ++ SAVE_ITEM(S5PC1XX_GPBPUD), ++ SAVE_ITEM(S5PC1XX_GPCCON), ++ SAVE_ITEM(S5PC1XX_GPCDAT), ++ SAVE_ITEM(S5PC1XX_GPCPUD), ++ SAVE_ITEM(S5PC1XX_GPDCON), ++ SAVE_ITEM(S5PC1XX_GPDDAT), ++ SAVE_ITEM(S5PC1XX_GPDPUD), ++ SAVE_ITEM(S5PC1XX_GPE0CON), ++ SAVE_ITEM(S5PC1XX_GPE0DAT), ++ SAVE_ITEM(S5PC1XX_GPE0PUD), ++ SAVE_ITEM(S5PC1XX_GPE1CON), ++ SAVE_ITEM(S5PC1XX_GPE1DAT), ++ SAVE_ITEM(S5PC1XX_GPE1PUD), ++ SAVE_ITEM(S5PC1XX_GPF0CON), ++ SAVE_ITEM(S5PC1XX_GPF0DAT), ++ SAVE_ITEM(S5PC1XX_GPF0PUD), ++ SAVE_ITEM(S5PC1XX_GPF1CON), ++ SAVE_ITEM(S5PC1XX_GPF1DAT), ++ SAVE_ITEM(S5PC1XX_GPF1PUD), ++ SAVE_ITEM(S5PC1XX_GPF2CON), ++ SAVE_ITEM(S5PC1XX_GPF2DAT), ++ SAVE_ITEM(S5PC1XX_GPF2PUD), ++ SAVE_ITEM(S5PC1XX_GPF3CON), ++ SAVE_ITEM(S5PC1XX_GPF3DAT), ++ SAVE_ITEM(S5PC1XX_GPF3PUD), ++ SAVE_ITEM(S5PC1XX_GPG0CON), ++ SAVE_ITEM(S5PC1XX_GPG0DAT), ++ SAVE_ITEM(S5PC1XX_GPG0PUD), ++ SAVE_ITEM(S5PC1XX_GPG1CON), ++ SAVE_ITEM(S5PC1XX_GPG1DAT), ++ SAVE_ITEM(S5PC1XX_GPG1PUD), ++ SAVE_ITEM(S5PC1XX_GPG2CON), ++ SAVE_ITEM(S5PC1XX_GPG2DAT), ++ SAVE_ITEM(S5PC1XX_GPG2PUD), ++ SAVE_ITEM(S5PC1XX_GPG3CON), ++ SAVE_ITEM(S5PC1XX_GPG3DAT), ++ SAVE_ITEM(S5PC1XX_GPG3PUD), ++ SAVE_ITEM(S5PC1XX_GPH0CON), ++ SAVE_ITEM(S5PC1XX_GPH0DAT), ++ SAVE_ITEM(S5PC1XX_GPH0PUD), ++ SAVE_ITEM(S5PC1XX_GPH1CON), ++ SAVE_ITEM(S5PC1XX_GPH1DAT), ++ SAVE_ITEM(S5PC1XX_GPH1PUD), ++ SAVE_ITEM(S5PC1XX_GPH2CON), ++ SAVE_ITEM(S5PC1XX_GPH2DAT), ++ SAVE_ITEM(S5PC1XX_GPH2PUD), ++ SAVE_ITEM(S5PC1XX_GPH3CON), ++ SAVE_ITEM(S5PC1XX_GPH3DAT), ++ SAVE_ITEM(S5PC1XX_GPH3PUD), ++ SAVE_ITEM(S5PC1XX_GPICON), ++ SAVE_ITEM(S5PC1XX_GPIDAT), ++ SAVE_ITEM(S5PC1XX_GPIPUD), ++ SAVE_ITEM(S5PC1XX_GPJ0CON), ++ SAVE_ITEM(S5PC1XX_GPJ0DAT), ++ SAVE_ITEM(S5PC1XX_GPJ0PUD), ++ SAVE_ITEM(S5PC1XX_GPJ1CON), ++ SAVE_ITEM(S5PC1XX_GPJ1DAT), ++ SAVE_ITEM(S5PC1XX_GPJ1PUD), ++ SAVE_ITEM(S5PC1XX_GPJ2CON), ++ SAVE_ITEM(S5PC1XX_GPJ2DAT), ++ SAVE_ITEM(S5PC1XX_GPJ2PUD), ++ SAVE_ITEM(S5PC1XX_GPJ3CON), ++ SAVE_ITEM(S5PC1XX_GPJ3DAT), ++ SAVE_ITEM(S5PC1XX_GPJ3PUD), ++ SAVE_ITEM(S5PC1XX_GPK0CON), ++ SAVE_ITEM(S5PC1XX_GPK0DAT), ++ SAVE_ITEM(S5PC1XX_GPK0PUD), ++ SAVE_ITEM(S5PC1XX_GPK1CON), ++ SAVE_ITEM(S5PC1XX_GPK1DAT), ++ SAVE_ITEM(S5PC1XX_GPK1PUD), ++ SAVE_ITEM(S5PC1XX_GPK2CON), ++ SAVE_ITEM(S5PC1XX_GPK2DAT), ++ SAVE_ITEM(S5PC1XX_GPK2PUD), ++ SAVE_ITEM(S5PC1XX_GPK3CON), ++ SAVE_ITEM(S5PC1XX_GPK3DAT), ++ SAVE_ITEM(S5PC1XX_GPK3PUD), ++}; ++ ++/* this lot should be really saved by the IRQ code */ ++/* VICXADDRESSXX initilaization to be needed */ ++static struct sleep_save irq_save[] = { ++ SAVE_ITEM(S5PC100_VIC0INTSELECT), ++ SAVE_ITEM(S5PC100_VIC1INTSELECT), ++ SAVE_ITEM(S5PC100_VIC2INTSELECT), ++ SAVE_ITEM(S5PC100_VIC0INTENABLE), ++ SAVE_ITEM(S5PC100_VIC1INTENABLE), ++ SAVE_ITEM(S5PC100_VIC2INTENABLE), ++ SAVE_ITEM(S5PC100_VIC0SOFTINT), ++ SAVE_ITEM(S5PC100_VIC1SOFTINT), ++ SAVE_ITEM(S5PC100_VIC2SOFTINT), ++}; ++ ++static struct sleep_save sromc_save[] = { ++ SAVE_ITEM(S5PC1XX_SROM_BW), ++ SAVE_ITEM(S5PC1XX_SROM_BC0), ++ SAVE_ITEM(S5PC1XX_SROM_BC1), ++ SAVE_ITEM(S5PC1XX_SROM_BC2), ++ SAVE_ITEM(S5PC1XX_SROM_BC3), ++ SAVE_ITEM(S5PC1XX_SROM_BC4), ++ SAVE_ITEM(S5PC1XX_SROM_BC5), ++}; ++ ++/* NAND control registers */ ++#define PM_NFCONF (S3C_VA_NAND + 0x00) ++#define PM_NFCONT (S3C_VA_NAND + 0x04) ++ ++static struct sleep_save nand_save[] = { ++ SAVE_ITEM(PM_NFCONF), ++ SAVE_ITEM(PM_NFCONT), ++}; ++ ++#define SAVE_UART(va) \ ++ SAVE_ITEM((va) + S3C2410_ULCON), \ ++ SAVE_ITEM((va) + S3C2410_UCON), \ ++ SAVE_ITEM((va) + S3C2410_UFCON), \ ++ SAVE_ITEM((va) + S3C2410_UMCON), \ ++ SAVE_ITEM((va) + S3C2410_UBRDIV), \ ++ SAVE_ITEM((va) + S3C2410_UDIVSLOT), \ ++ SAVE_ITEM((va) + S3C2410_UINTMSK) ++ ++ ++static struct sleep_save uart_save[] = { ++ SAVE_UART(S3C24XX_VA_UART0), ++}; ++ ++#define DBG(fmt...) ++ ++#define s5pc1xx_pm_debug_init() do { } while(0) ++#define s5pc1xx_pm_check_prepare() do { } while(0) ++#define s5pc1xx_pm_check_restore() do { } while(0) ++#define s5pc1xx_pm_check_store() do { } while(0) ++ ++/* helper functions to save and restore register state */ ++ ++void s5pc1xx_pm_do_save(struct sleep_save *ptr, int count) ++{ ++ for (; count > 0; count--, ptr++) { ++ ptr->val = __raw_readl(ptr->reg); ++ //DBG("saved %p value %08lx\n", ptr->reg, ptr->val); ++ } ++} ++ ++/* s5pc1xx_pm_do_restore ++ * ++ * restore the system from the given list of saved registers ++ * ++ * Note, we do not use DBG() in here, as the system may not have ++ * restore the UARTs state yet ++*/ ++ ++void s5pc1xx_pm_do_restore(struct sleep_save *ptr, int count) ++{ ++ for (; count > 0; count--, ptr++) { ++ //printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n", ++ //ptr->reg, ptr->val, __raw_readl(ptr->reg)); ++ ++ __raw_writel(ptr->val, ptr->reg); ++ } ++} ++ ++/* s5pc1xx_pm_do_restore_core ++ * ++ * similar to s36410_pm_do_restore_core ++ * ++ * WARNING: Do not put any debug in here that may effect memory or use ++ * peripherals, as things may be changing! ++*/ ++ ++/* s5pc1xx_pm_do_save_phy ++ * ++ * save register of system ++ * ++ * Note, I made this function to support driver with ioremap. ++ * If you want to use this function, you should to input as first parameter ++ * struct sleep_save_phy type ++*/ ++ ++void s5pc1xx_pm_do_save_phy(struct sleep_save_phy *ptr, struct platform_device *pdev, int count) ++{ ++ void __iomem *target_reg; ++ struct resource *res; ++ u32 reg_size; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ reg_size = res->end - res->start + 1; ++ target_reg = ioremap(res->start,reg_size); ++ ++ for (; count > 0; count--, ptr++) { ++ ptr->val = readl(target_reg + (ptr->reg)); ++ } ++} ++ ++/* s5pc1xx_pm_do_restore_phy ++ * ++ * restore register of system ++ * ++ * Note, I made this function to support driver with ioremap. ++ * If you want to use this function, you should to input as first parameter ++ * struct sleep_save_phy type ++*/ ++ ++void s5pc1xx_pm_do_restore_phy(struct sleep_save_phy *ptr, struct platform_device *pdev, int count) ++{ ++ void __iomem *target_reg; ++ struct resource *res; ++ u32 reg_size; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ reg_size = res->end - res->start + 1; ++ target_reg = ioremap(res->start,reg_size); ++ ++ for (; count > 0; count--, ptr++) { ++ writel(ptr->val, (target_reg + ptr->reg)); ++ } ++} ++ ++static void s5pc1xx_pm_do_restore_core(struct sleep_save *ptr, int count) ++{ ++ for (; count > 0; count--, ptr++) { ++ __raw_writel(ptr->val, ptr->reg); ++ } ++} ++ ++/* s5pc1xx_pm_show_resume_irqs ++ * ++ * print any IRQs asserted at resume time (ie, we woke from) ++*/ ++ ++static void s5pc1xx_pm_show_resume_irqs(int start, unsigned long which, ++ unsigned long mask) ++{ ++ int i; ++ ++ which &= ~mask; ++ ++ for (i = 0; i <= 31; i++) { ++ if ((which) & (1L<> 30) & 0x1)){} ++} ++ ++/* s5pc1xx_pm_enter ++ * ++ * central control for sleep/resume process ++*/ ++ ++static int s5pc1xx_pm_enter(suspend_state_t state) ++{ ++ unsigned long regs_save[16]; ++ unsigned int tmp; ++ ++ /* ensure the debug is initialised (if enabled) */ ++ ++ DBG("s5pc1xx_pm_enter(%d)\n", state); ++ ++ if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) { ++ printk(KERN_ERR PFX "error: no cpu sleep functions set\n"); ++ return -EINVAL; ++ } ++ ++ /* store the physical address of the register recovery block */ ++ s5pc100_sleep_save_phys = virt_to_phys(regs_save); ++ ++ DBG("s5pc1xx_sleep_save_phys=0x%08lx\n", s5pc100_sleep_save_phys); ++ ++ s5pc1xx_pm_do_save(gpio_save, ARRAY_SIZE(gpio_save)); ++ s5pc1xx_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); ++ s5pc1xx_pm_do_save(core_save, ARRAY_SIZE(core_save)); ++ s5pc1xx_pm_do_save(sromc_save, ARRAY_SIZE(sromc_save)); ++ s5pc1xx_pm_do_save(nand_save, ARRAY_SIZE(nand_save)); ++ s5pc1xx_pm_do_save(uart_save, ARRAY_SIZE(uart_save)); ++ ++ /* ensure INF_REG0 has the resume address */ ++ __raw_writel(virt_to_phys(s5pc100_cpu_resume), S5P_INFORM0); ++ ++ /* call cpu specific preperation */ ++ ++ pm_cpu_prep(); ++ ++ /* flush cache back to ram */ ++ flush_cache_all(); ++ ++ /* send the cpu to sleep... */ ++ __raw_writel(0xffffffff, S5PC100_VIC0INTENCLEAR); ++ __raw_writel(0xffffffff, S5PC100_VIC1INTENCLEAR); ++ __raw_writel(0xffffffff, S5PC100_VIC2INTENCLEAR); ++ __raw_writel(0xffffffff, S5PC100_VIC0SOFTINTCLEAR); ++ __raw_writel(0xffffffff, S5PC100_VIC1SOFTINTCLEAR); ++ __raw_writel(0xffffffff, S5PC100_VIC2SOFTINTCLEAR); ++ ++ /* Mask all wake up source */ ++ tmp = __raw_readl(S5P_PWR_CFG); ++ tmp &= ~(0x1 << 7); ++ tmp |= (0x7ff << 8); ++ /* unmask alarm wakeup source */ ++ tmp &= ~(0x1 << 10); ++ __raw_writel(tmp , S5P_PWR_CFG); ++ __raw_writel(0xffffffff , S5P_EINT_WAKEUP_MASK); ++ ++ /* Wake up source setting */ ++ s5pc1xx_pm_configure_extint(); ++ ++ /* : USB Power Control */ ++ /* - USB PHY Disable */ ++ /* - Make USB Tranceiver PAD to Suspend */ ++ tmp = __raw_readl(S5P_OTHERS); ++ tmp &= ~(1<<16); /* USB Signal Mask Clear */ ++ __raw_writel(tmp, S5P_OTHERS); ++ ++ tmp = __raw_readl(S5PC1XX_UHOST); ++ tmp |= (1<<0); ++ __raw_writel(tmp, S5PC1XX_UHOST); ++ ++ /* Sleep Mode Pad Configuration */ ++ __raw_writel(0x2, S5PC1XX_PDNEN); /* Controlled by SLPEN Bit (You Should Clear SLPEN Bit in Wake Up Process...) */ ++ ++ /* Set WFI instruction to SLEEP mode */ ++ tmp = __raw_readl(S5P_PWR_CFG); ++ tmp &= S5P_CFG_WFI_CLEAN; ++ tmp |= S5P_CFG_WFI_SLEEP; ++ __raw_writel(tmp, S5P_PWR_CFG); ++ ++ /* Clear WAKEUP_STAT register for next wakeup */ ++ tmp = __raw_readl(S5P_WAKEUP_STAT); ++ __raw_writel(tmp, S5P_WAKEUP_STAT); ++ ++#if 1 ++ /* Set Power Stable Count */ ++ tmp = __raw_readl(S5P_OTHERS); ++ tmp &=~(1 << S5P_OTHER_STA_TYPE); ++ tmp |= (STA_TYPE_SFR << S5P_OTHER_STA_TYPE); ++ __raw_writel(tmp , S5P_OTHERS); ++ ++ __raw_writel(((S5P_PWR_STABLE_COUNT << S5P_PWR_STA_CNT) | (1 << S5P_PWR_STA_EXP_SCALE)), S5P_PWR_STABLE); ++ ++ /* Set Syscon Interrupt */ ++ tmp = __raw_readl(S5P_OTHERS); ++ tmp |= (1 << S5P_OTHER_SYS_INT); ++ __raw_writel(tmp, S5P_OTHERS); ++ ++ /* Disable OSC_EN (Disable X-tal Osc Pad in Sleep mode) */ ++ tmp = __raw_readl(S5P_SLEEP_CFG); ++ tmp &= ~(1 << 0); ++ __raw_writel(tmp, S5P_SLEEP_CFG); ++#endif ++ ++ /* s5pc1xx_cpu_save will also act as our return point from when ++ * we resume as it saves its own register state, so use the return ++ * code to differentiate return from save and return from sleep */ ++ ++ if (s5pc100_cpu_save(regs_save) == 0) { ++ flush_cache_all(); ++ /* This function for Chip bug on EVT0 */ ++#if 0 ++ s5pc1xx_pm_clk(PM_APLL, 512 , 2 , 5); ++ s5pc1xx_pm_clk(PM_MPLL, 128 , 2 , 5); ++ s5pc1xx_pm_clk(PM_EPLL, 128 , 2 , 5); ++ s5pc1xx_pm_clk(PM_HPLL, 128 , 2 , 5); ++#endif ++ pm_cpu_sleep(); ++ } ++ ++ /* restore the cpu state */ ++ cpu_init(); ++ ++ /* Sleep Mode Pad Configuration */ ++ __raw_writel(0x2, S5PC1XX_PDNEN); /* Clear SLPEN Bit for Pad back to Normal Mode */ ++ ++ /* MTC IO OFF | MTC IO SD-MMC OFF | USB Phy Enable */ ++ tmp = __raw_readl(S5P_OTHERS); ++ tmp |= (1<<31); ++ __raw_writel(tmp, S5P_OTHERS); ++ ++ tmp = __raw_readl(S5P_OTHERS); ++ tmp |= ((1<<22)|(1<<16)); ++ __raw_writel(tmp, S5P_OTHERS); ++ ++ tmp = __raw_readl(S5PC1XX_UHOST); ++ tmp &= ~(1<<0); ++ __raw_writel(tmp, S5PC1XX_UHOST); ++ ++ ++ s5pc1xx_pm_do_restore(gpio_save, ARRAY_SIZE(gpio_save)); ++ s5pc1xx_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); ++ s5pc1xx_pm_do_restore(core_save, ARRAY_SIZE(core_save)); ++ s5pc1xx_pm_do_restore(sromc_save, ARRAY_SIZE(sromc_save)); ++ s5pc1xx_pm_do_restore(nand_save, ARRAY_SIZE(nand_save)); ++ s5pc1xx_pm_do_restore(uart_save, ARRAY_SIZE(uart_save)); ++ ++ tmp = readl(weint_base + S5P_APM_WEINT1_PEND); ++ writel(tmp , weint_base + S5P_APM_WEINT1_PEND); ++ ++ DBG("post sleep, preparing to return\n"); ++ ++ s5pc1xx_pm_check_restore(); ++ ++ /* ok, let's return from sleep */ ++ DBG("S3C6410 PM Resume (post-restore)\n"); ++ return 0; ++} ++ ++ ++static struct platform_suspend_ops s5pc1xx_pm_ops = { ++ .enter = s5pc1xx_pm_enter, ++ .valid = suspend_valid_only_mem, ++}; ++ ++/* s5pc1xx_pm_init ++ * ++ * Attach the power management functions. This should be called ++ * from the board specific initialisation if the board supports ++ * it. ++*/ ++ ++int __init s5pc1xx_pm_init(void) ++{ ++ printk("s5pc1xx Power Management, (c) 2008 Samsung Electronics\n"); ++ /* set the irq configuration for wake */ ++ suspend_set_ops(&s5pc1xx_pm_ops); ++ return 0; ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/pwm-s5pc100.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/pwm-s5pc100.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/pwm-s5pc100.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/pwm-s5pc100.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,378 @@ ++/* linux/arch/arm/plat-s5pc1xx/pwm-s5pc100.c ++ * ++ * (c) 2003-2005 Simtec Electronics ++ * Ben Dooks ++ * ++ * S5PC1XX PWM core ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * Changelog: ++ * This file is based on the Sangwook Lee/Samsung patches, re-written due ++ * to various ommisions from the code (such as flexible pwm configuration) ++ * for use with the BAST system board. ++ * ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "pwm-s5pc100.h" ++ ++s5pc100_pwm_chan_t s3c_chans[S3C_PWM_CHANNELS]; ++ ++static inline void ++s5pc100_pwm_buffdone(s5pc100_pwm_chan_t *chan, void *dev) ++{ ++ ++ if (chan->callback_fn != NULL) { ++ (chan->callback_fn)( dev); ++ } ++} ++ ++ ++static int s5pc100_pwm_start (int channel) ++{ ++ unsigned long tcon; ++ tcon = __raw_readl(S3C_TCON); ++ switch(channel) ++ { ++ case 0: ++ tcon |= S3C_TCON_T0START; ++ tcon &= ~S3C_TCON_T0MANUALUPD; ++ break; ++ case 1: ++ tcon |= S3C_TCON_T1START; ++ tcon &= ~S3C_TCON_T1MANUALUPD; ++ break; ++ case 2: ++ tcon |= S3C_TCON_T2START; ++ tcon &= ~S3C_TCON_T2MANUALUPD; ++ break; ++ case 3: ++ tcon |= S3C_TCON_T3START; ++ tcon &= ~S3C_TCON_T3MANUALUPD; ++ break; ++ case 4: ++ tcon |= S3C_TCON_T4START; ++ tcon &= ~S3C_TCON_T4MANUALUPD; ++ break; ++ } ++ __raw_writel(tcon, S3C_TCON); ++ ++ return 0; ++} ++ ++ ++int s5pc100_timer_setup (int channel, int usec, unsigned long g_tcnt, unsigned long g_tcmp) ++{ ++ unsigned long tcon; ++ unsigned long tcnt; ++ unsigned long tcmp; ++ unsigned long tcfg1; ++ unsigned long tcfg0; ++ unsigned long pclk; ++ struct clk *clk; ++ ++ printk("\nPWM channel %d set g_tcnt = %ld, g_tcmp = %ld \n", channel, g_tcnt, g_tcmp); ++ ++ tcnt = 0xffffffff; /* default value for tcnt */ ++ ++ /* read the current timer configuration bits */ ++ tcon = __raw_readl(S3C_TCON); ++ tcfg1 = __raw_readl(S3C_TCFG1); ++ tcfg0 = __raw_readl(S3C_TCFG0); ++ ++ clk = clk_get(NULL, "timers"); ++ if (IS_ERR(clk)) ++ panic("failed to get clock for pwm timer"); ++ ++ clk_enable(clk); ++ ++ pclk = clk_get_rate(clk); ++ ++ /* configure clock tick */ ++ switch(channel) ++ { ++ case 0: ++ /* set gpio as PWM TIMER0 to signal output*/ ++ s3c_gpio_cfgpin(S5PC1XX_GPD(0), S5PC1XX_GPD0_TOUT_0); ++ gpio_set_value(S5PC1XX_GPD(0), 0); ++ tcfg1 &= ~S3C_TCFG1_MUX0_MASK; ++ tcfg1 |= S3C_TCFG1_MUX1_DIV2; ++ ++ tcfg0 &= ~S3C_TCFG_PRESCALER0_MASK; ++ tcfg0 |= (PRESCALER) << S3C_TCFG_PRESCALER0_SHIFT; ++ tcon &= ~(7<<0); ++ tcon |= S3C_TCON_T0RELOAD; ++ break; ++ ++ case 1: ++ /* set gpio as PWM TIMER1 to signal output*/ ++ s3c_gpio_cfgpin(S5PC1XX_GPD(1), S5PC1XX_GPD1_TOUT_1); ++ gpio_set_value(S5PC1XX_GPD(1), 0); ++ tcfg1 &= ~S3C_TCFG1_MUX1_MASK; ++ tcfg1 |= S3C_TCFG1_MUX1_DIV2; ++ ++ tcfg0 &= ~S3C_TCFG_PRESCALER0_MASK; ++ tcfg0 |= (PRESCALER) << S3C_TCFG_PRESCALER0_SHIFT; ++ ++ tcon &= ~(7<<8); ++ tcon |= S3C_TCON_T1RELOAD; ++ break; ++ case 2: ++ /* set gpio as PWM TIMER2 to signal output*/ ++ s3c_gpio_cfgpin(S5PC1XX_GPD(2), S5PC1XX_GPD0_TOUT_0); ++ gpio_set_value(S5PC1XX_GPD(2), 0); ++ tcfg1 &= ~S3C_TCFG1_MUX2_MASK; ++ tcfg1 |= S3C_TCFG1_MUX2_DIV2; ++ ++ tcfg0 &= ~S3C_TCFG_PRESCALER1_MASK; ++ tcfg0 |= (PRESCALER) << S3C_TCFG_PRESCALER1_SHIFT; ++ ++ tcon &= ~(7<<12); ++ tcon |= S3C_TCON_T2RELOAD; ++ break; ++ case 3: ++ tcfg1 &= ~S3C_TCFG1_MUX3_MASK; ++ tcfg1 |= S3C_TCFG1_MUX3_DIV2; ++ ++ tcfg0 &= ~S3C_TCFG_PRESCALER1_MASK; ++ tcfg0 |= (PRESCALER) << S3C_TCFG_PRESCALER1_SHIFT; ++ tcon &= ~(7<<16); ++ tcon |= S3C_TCON_T3RELOAD; ++ break; ++ case 4: ++ tcfg1 &= ~S3C_TCFG1_MUX4_MASK; ++ tcfg1 |= S3C_TCFG1_MUX4_DIV2; ++ ++ tcfg0 &= ~S3C_TCFG_PRESCALER1_MASK; ++ tcfg0 |= (PRESCALER) << S3C_TCFG_PRESCALER1_SHIFT; ++ tcon &= ~(7<<20); ++ tcon |= S3C_TCON_T3RELOAD; ++ break; ++ } ++ ++ __raw_writel(tcfg1, S3C_TCFG1); ++ __raw_writel(tcfg0, S3C_TCFG0); ++ ++ ++ __raw_writel(tcon, S3C_TCON); ++ ++ /*tcnt = 160; ++ __raw_writel(tcnt, S3C_TCNTB(channel)); ++ tcmp = 110; ++ __raw_writel(tcmp, S3C_TCMPB(channel));*/ ++ ++ switch(channel) ++ { ++ case 0: ++ tcon |= S3C_TCON_T0MANUALUPD; ++ break; ++ case 1: ++ tcon |= S3C_TCON_T1MANUALUPD; ++ break; ++ case 2: ++ tcon |= S3C_TCON_T2MANUALUPD; ++ break; ++ case 3: ++ tcon |= S3C_TCON_T3MANUALUPD; ++ break; ++ case 4: ++ tcon |= S3C_TCON_T4MANUALUPD; ++ break; ++ } ++ __raw_writel(tcon, S3C_TCON); ++ ++ tcnt = g_tcnt; ++ __raw_writel(tcnt, S3C_TCNTB(channel)); ++ ++ tcmp = g_tcmp; ++ __raw_writel(tcmp, S3C_TCMPB(channel)); ++ ++ /* start the timer running */ ++ s5pc100_pwm_start ( channel); ++ ++ return 0; ++} ++ ++ ++static irqreturn_t s5pc100_pwm_irq(int irq, void *devpw) ++{ ++ s5pc100_pwm_chan_t *chan = (s5pc100_pwm_chan_t *)devpw; ++ void *dev=chan->dev; ++ ++ /* modify the channel state */ ++ s5pc100_pwm_buffdone(chan, dev); ++ ++ return IRQ_HANDLED; ++} ++ ++ ++int s5pc100_pwm_request(pwmch_t channel, s3c_pwm_client_t *client, void *dev) ++{ ++ s5pc100_pwm_chan_t *chan = &s3c_chans[channel]; ++ unsigned long flags; ++ int err; ++ ++ pr_debug("pwm%d: s3c_request_pwm: client=%s, dev=%p\n", ++ channel, client->name, dev); ++ ++ ++ local_irq_save(flags); ++ ++ ++ if (chan->in_use) { ++ if (client != chan->client) { ++ printk(KERN_ERR "pwm%d: already in use\n", channel); ++ local_irq_restore(flags); ++ return -EBUSY; ++ } else { ++ printk(KERN_ERR "pwm%d: client already has channel\n", channel); ++ } ++ } ++ ++ chan->client = client; ++ chan->in_use = 1; ++ chan->dev = dev; ++ ++ if (!chan->irq_claimed) { ++ pr_debug("pwm%d: %s : requesting irq %d\n", ++ channel, __FUNCTION__, chan->irq); ++ ++ err = request_irq(chan->irq, s5pc100_pwm_irq, IRQF_DISABLED, ++ client->name, (void *)chan); ++ ++ if (err) { ++ chan->in_use = 0; ++ local_irq_restore(flags); ++ ++ printk(KERN_ERR "%s: cannot get IRQ %d for PWM %d\n", ++ client->name, chan->irq, chan->number); ++ return err; ++ } ++ ++ chan->irq_claimed = 1; ++ chan->irq_enabled = 1; ++ } ++ ++ local_irq_restore(flags); ++ ++ /* need to setup */ ++ ++ pr_debug("%s: channel initialised, %p\n", __FUNCTION__, chan); ++ ++ return 0; ++} ++ ++int s5pc100_pwm_free (pwmch_t channel, s3c_pwm_client_t *client) ++{ ++ s5pc100_pwm_chan_t *chan = &s3c_chans[channel]; ++ unsigned long flags; ++ ++ ++ local_irq_save(flags); ++ ++ if (chan->client != client) { ++ printk(KERN_WARNING "pwm%d: possible free from different client (channel %p, passed %p)\n", ++ channel, chan->client, client); ++ } ++ ++ /* sort out stopping and freeing the channel */ ++ ++ ++ chan->client = NULL; ++ chan->in_use = 0; ++ ++ if (chan->irq_claimed) ++ free_irq(chan->irq, (void *)chan); ++ chan->irq_claimed = 0; ++ ++ local_irq_restore(flags); ++ ++ return 0; ++} ++ ++ ++int s5pc100_pwm_set_buffdone_fn(pwmch_t channel, s3c_pwm_cbfn_t rtn) ++{ ++ s5pc100_pwm_chan_t *chan = &s3c_chans[channel]; ++ ++ ++ pr_debug("%s: chan=%d, callback rtn=%p\n", __FUNCTION__, channel, rtn); ++ ++ chan->callback_fn = rtn; ++ ++ return 0; ++} ++ ++ ++#define s5pc100_pwm_suspend NULL ++#define s5pc100_pwm_resume NULL ++ ++struct sysdev_class pwm_sysclass = { ++ .name = "s3c-pwm", ++ .suspend = s5pc100_pwm_suspend, ++ .resume = s5pc100_pwm_resume, ++}; ++ ++ ++/* initialisation code */ ++ ++static int __init s5pc100_init_pwm(void) ++{ ++ s5pc100_pwm_chan_t *cp; ++ int channel; ++ int ret; ++ ++ printk("S3C PWM Driver, (c) 2006-2007 Samsung Electronics\n"); ++ ++ ret = sysdev_class_register(&pwm_sysclass); ++ if (ret != 0) { ++ printk(KERN_ERR "pwm sysclass registration failed\n"); ++ return -ENODEV; ++ } ++ ++ for (channel = 0; channel < S3C_PWM_CHANNELS; channel++) { ++ cp = &s3c_chans[channel]; ++ ++ memset(cp, 0, sizeof(s5pc100_pwm_chan_t)); ++ ++ cp->number = channel; ++ /* pwm channel irqs are in order.. */ ++ cp->irq = channel + IRQ_TIMER0; ++ ++ /* register system device */ ++ ++ ret = sysdev_register(&cp->sysdev); ++ ++ pr_debug("PWM channel %d , irq %d\n", ++ cp->number, cp->irq); ++ } ++ ++ return ret; ++} ++__initcall(s5pc100_init_pwm); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/pwm-s5pc100.h linux-2.6.28.6/arch/arm/plat-s5pc1xx/pwm-s5pc100.h +--- linux-2.6.28/arch/arm/plat-s5pc1xx/pwm-s5pc100.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/pwm-s5pc100.h 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,78 @@ ++/* arch/arm/plat-s5pc1xx/pwm-s5pc100.h ++ * ++ * Copyright (C) 2003,2004 Simtec Electronics ++ * Ben Dooks ++ * ++ * Samsung S5PC1XX PWM support ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * Changelog: ++ * ??-May-2003 BJD Created file ++ * ??-Jun-2003 BJD Added more dma functionality to go with arch ++ * 10-Nov-2004 BJD Added sys_device support ++*/ ++ ++#ifndef __ASM_ARCH_DMA_H ++#define __ASM_ARCH_DMA_H __FILE__ ++ ++#include ++#include ++ ++ ++#define pwmch_t int ++ ++/* we have 4 pwm channels */ ++#define S3C_PWM_CHANNELS 5 ++#define PRESCALER ((4-1)/2) ++ ++struct s3c_pwm_client { ++ char *name; ++}; ++ ++typedef struct s3c_pwm_client s3c_pwm_client_t; ++ ++ ++typedef struct s3c_pwm_chan_s s5pc100_pwm_chan_t; ++ ++/* s3c_pwm_cbfn_t ++ * ++ * buffer callback routine type ++*/ ++ ++typedef void (*s3c_pwm_cbfn_t)(void *buf); ++ ++ ++ ++/* struct s3c_pwm_chan_s ++ * ++ * full state information for each DMA channel ++*/ ++ ++struct s3c_pwm_chan_s { ++ /* channel state flags and information */ ++ unsigned char number; /* number of this dma channel */ ++ unsigned char in_use; /* channel allocated */ ++ unsigned char irq_claimed; /* irq claimed for channel */ ++ unsigned char irq_enabled; /* irq enabled for channel */ ++ ++ /* channel state */ ++ ++ s3c_pwm_client_t *client; ++ void *dev; ++ /* channel configuration */ ++ unsigned int flags; /* channel flags */ ++ ++ /* channel's hardware position and configuration */ ++ unsigned int irq; /* channel irq */ ++ ++ /* driver handles */ ++ s3c_pwm_cbfn_t callback_fn; /* buffer done callback */ ++ ++ /* system device */ ++ struct sys_device sysdev; ++}; ++ ++#endif /* __ASM_ARCH_DMA_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/pwm.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/pwm.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/pwm.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/pwm.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,432 @@ ++/* arch/arm/plat-s5pc1xx/pwm.c ++ * ++ * Copyright (c) 2007 Ben Dooks ++ * Copyright (c) 2008 Simtec Electronics ++ * Ben Dooks , ++ * ++ * S5PC1XX PWM device core ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct pwm_device { ++ struct list_head list; ++ struct platform_device *pdev; ++ ++ struct clk *clk_div; ++ struct clk *clk; ++ const char *label; ++ ++ unsigned int period_ns; ++ unsigned int duty_ns; ++ ++ unsigned char tcon_base; ++ unsigned char running; ++ unsigned char use_count; ++ unsigned char pwm_id; ++}; ++ ++#define pwm_dbg(_pwm, msg...) dev_dbg(&(_pwm)->pdev->dev, msg) ++ ++static struct clk *clk_scaler[2]; ++ ++/* Standard setup for a timer block. */ ++ ++#define TIMER_RESOURCE_SIZE (1) ++ ++#define TIMER_RESOURCE(_tmr, _irq) \ ++ (struct resource [TIMER_RESOURCE_SIZE]) { \ ++ [0] = { \ ++ .start = _irq, \ ++ .end = _irq, \ ++ .flags = IORESOURCE_IRQ \ ++ } \ ++ } ++ ++#define DEFINE_S3C_TIMER(_tmr_no, _irq) \ ++ .name = "s3c24xx-pwm", \ ++ .id = _tmr_no, \ ++ .num_resources = TIMER_RESOURCE_SIZE, \ ++ .resource = TIMER_RESOURCE(_tmr_no, _irq), \ ++ ++/* since we already have an static mapping for the timer, we do not ++ * bother setting any IO resource for the base. ++ */ ++ ++struct platform_device s3c_device_timer[] = { ++ [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) }, ++ [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) }, ++ [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) }, ++ [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) }, ++ [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) }, ++}; ++ ++static inline int pwm_is_tdiv(struct pwm_device *pwm) ++{ ++ return clk_get_parent(pwm->clk) == pwm->clk_div; ++} ++ ++static DEFINE_MUTEX(pwm_lock); ++static LIST_HEAD(pwm_list); ++ ++struct pwm_device *pwm_request(int pwm_id, const char *label) ++{ ++ struct pwm_device *pwm; ++ int found = 0; ++ ++ mutex_lock(&pwm_lock); ++ ++ list_for_each_entry(pwm, &pwm_list, list) { ++ if (pwm->pwm_id == pwm_id) { ++ found = 1; ++ break; ++ } ++ } ++ ++ if (found) { ++ if (pwm->use_count == 0) { ++ pwm->use_count = 1; ++ pwm->label = label; ++ } else ++ pwm = ERR_PTR(-EBUSY); ++ } else ++ pwm = ERR_PTR(-ENOENT); ++ ++ mutex_unlock(&pwm_lock); ++ return pwm; ++} ++ ++EXPORT_SYMBOL(pwm_request); ++ ++ ++void pwm_free(struct pwm_device *pwm) ++{ ++ mutex_lock(&pwm_lock); ++ ++ if (pwm->use_count) { ++ pwm->use_count--; ++ pwm->label = NULL; ++ } else ++ printk(KERN_ERR "PWM%d device already freed\n", pwm->pwm_id); ++ ++ mutex_unlock(&pwm_lock); ++} ++ ++EXPORT_SYMBOL(pwm_free); ++ ++#define pwm_tcon_start(pwm) (1 << (pwm->tcon_base + 0)) ++#define pwm_tcon_invert(pwm) (1 << (pwm->tcon_base + 2)) ++#define pwm_tcon_autoreload(pwm) (1 << (pwm->tcon_base + 3)) ++#define pwm_tcon_manulupdate(pwm) (1 << (pwm->tcon_base + 1)) ++ ++int pwm_enable(struct pwm_device *pwm) ++{ ++ unsigned long flags; ++ unsigned long tcon; ++ ++ local_irq_save(flags); ++ ++ tcon = __raw_readl(S3C2410_TCON); ++ tcon |= pwm_tcon_start(pwm); ++ __raw_writel(tcon, S3C2410_TCON); ++ ++ local_irq_restore(flags); ++ ++ pwm->running = 1; ++ return 0; ++} ++ ++EXPORT_SYMBOL(pwm_enable); ++ ++void pwm_disable(struct pwm_device *pwm) ++{ ++ unsigned long flags; ++ unsigned long tcon; ++ ++ local_irq_save(flags); ++ ++ tcon = __raw_readl(S3C2410_TCON); ++ tcon &= ~pwm_tcon_start(pwm); ++ __raw_writel(tcon, S3C2410_TCON); ++ ++ local_irq_restore(flags); ++ ++ pwm->running = 0; ++} ++ ++EXPORT_SYMBOL(pwm_disable); ++ ++static unsigned long pwm_calc_tin(struct pwm_device *pwm, unsigned long freq) ++{ ++ unsigned long tin_parent_rate; ++ unsigned int div; ++ ++ tin_parent_rate = clk_get_rate(clk_get_parent(pwm->clk_div)); ++ pwm_dbg(pwm, "tin parent at %lu\n", tin_parent_rate); ++ ++ for (div = 2; div <= 16; div *= 2) { ++ if ((tin_parent_rate / (div << 16)) < freq) ++ return tin_parent_rate / div; ++ } ++ ++ return tin_parent_rate / 16; ++} ++ ++#define NS_IN_HZ (1000000000UL) ++ ++int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) ++{ ++ unsigned long tin_rate; ++ unsigned long tin_ns; ++ unsigned long period; ++ unsigned long flags; ++ unsigned long tcon; ++ unsigned long tcnt; ++ long tcmp; ++ ++ /* We currently avoid using 64bit arithmetic by using the ++ * fact that anything faster than 1Hz is easily representable ++ * by 32bits. */ ++ ++ if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ) ++ return -ERANGE; ++ ++ if (duty_ns > period_ns) ++ return -EINVAL; ++ ++ if (period_ns == pwm->period_ns && ++ duty_ns == pwm->duty_ns) ++ return 0; ++ ++ /* The TCMP and TCNT can be read without a lock, they're not ++ * shared between the timers. */ ++ ++ tcmp = __raw_readl(S3C2410_TCMPB(pwm->pwm_id)); ++ tcnt = __raw_readl(S3C2410_TCNTB(pwm->pwm_id)); ++ ++ period = NS_IN_HZ / period_ns; ++ ++ pwm_dbg(pwm, "duty_ns=%d, period_ns=%d (%lu)\n", ++ duty_ns, period_ns, period); ++ ++ /* Check to see if we are changing the clock rate of the PWM */ ++ ++ if (pwm->period_ns != period_ns) { ++ if (pwm_is_tdiv(pwm)) { ++ tin_rate = pwm_calc_tin(pwm, period); ++ clk_set_rate(pwm->clk_div, tin_rate); ++ } else ++ tin_rate = clk_get_rate(pwm->clk); ++ ++ pwm->period_ns = period_ns; ++ ++ pwm_dbg(pwm, "tin_rate=%lu\n", tin_rate); ++ ++ tin_ns = NS_IN_HZ / tin_rate; ++ tcnt = period_ns / tin_ns; ++ } else ++ tin_ns = NS_IN_HZ / clk_get_rate(pwm->clk); ++ ++ /* Note, counters count down */ ++ ++ tcmp = duty_ns / tin_ns; ++ tcmp = tcnt - tcmp; ++ ++ pwm_dbg(pwm, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt); ++ ++ if (tcmp < 0) ++ tcmp = 0; ++ ++ /* Update the PWM register block. */ ++ ++ local_irq_save(flags); ++ ++ __raw_writel(tcmp, S3C2410_TCMPB(pwm->pwm_id)); ++ __raw_writel(tcnt, S3C2410_TCNTB(pwm->pwm_id)); ++ ++ tcon = __raw_readl(S3C2410_TCON); ++ tcon |= pwm_tcon_manulupdate(pwm); ++ tcon |= pwm_tcon_autoreload(pwm); ++ __raw_writel(tcon, S3C2410_TCON); ++ ++ tcon &= ~pwm_tcon_manulupdate(pwm); ++ __raw_writel(tcon, S3C2410_TCON); ++ ++ local_irq_restore(flags); ++ ++ return 0; ++} ++ ++EXPORT_SYMBOL(pwm_config); ++ ++static int pwm_register(struct pwm_device *pwm) ++{ ++ pwm->duty_ns = -1; ++ pwm->period_ns = -1; ++ ++ mutex_lock(&pwm_lock); ++ list_add_tail(&pwm->list, &pwm_list); ++ mutex_unlock(&pwm_lock); ++ ++ return 0; ++} ++ ++static int s3c_pwm_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct pwm_device *pwm; ++ unsigned long flags; ++ unsigned long tcon; ++ unsigned int id = pdev->id; ++ int ret; ++ ++ if (id == 0) { ++ if(gpio_is_valid(S5PC1XX_GPD(0))) { ++ ret = gpio_request(S5PC1XX_GPD(0), "GPD"); ++ ++ if (ret) { ++ printk(KERN_ERR "failed to request GPD for PWM-OUT 0\n"); ++ } ++ s3c_gpio_cfgpin(S5PC1XX_GPD(0), S5PC1XX_GPD0_TOUT_0); ++ } ++ } else if(id == 1) { ++ if(gpio_is_valid(S5PC1XX_GPD(1))) { ++ ret = gpio_request(S5PC1XX_GPD(1), "GPD"); ++ ++ if (ret) { ++ printk(KERN_ERR "failed to request GPD for PWM-OUT 1\n"); ++ } ++ s3c_gpio_cfgpin(S5PC1XX_GPD(1), S5PC1XX_GPD1_TOUT_1); ++ } ++ ++ } else { ++ printk(KERN_ERR "This PWM dosen't support PWM out\n"); ++ } ++ ++ if (id == 4) { ++ dev_err(dev, "TIMER4 is currently not supported\n"); ++ return -ENXIO; ++ } ++ ++ pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); ++ if (pwm == NULL) { ++ dev_err(dev, "failed to allocate pwm_device\n"); ++ return -ENOMEM; ++ } ++ ++ pwm->pdev = pdev; ++ pwm->pwm_id = id; ++ ++ /* calculate base of control bits in TCON */ ++ pwm->tcon_base = id == 0 ? 0 : (id * 4) + 4; ++ ++ pwm->clk = clk_get(dev, "pwm-tin"); ++ if (IS_ERR(pwm->clk)) { ++ dev_err(dev, "failed to get pwm tin clk\n"); ++ ret = PTR_ERR(pwm->clk); ++ goto err_alloc; ++ } ++ ++ pwm->clk_div = clk_get(dev, "pwm-tdiv"); ++ if (IS_ERR(pwm->clk_div)) { ++ dev_err(dev, "failed to get pwm tdiv clk\n"); ++ ret = PTR_ERR(pwm->clk_div); ++ goto err_clk_tin; ++ } ++ ++ local_irq_save(flags); ++ ++ tcon = __raw_readl(S3C2410_TCON); ++ tcon |= pwm_tcon_invert(pwm); ++ __raw_writel(tcon, S3C2410_TCON); ++ ++ local_irq_restore(flags); ++ ++ ++ ret = pwm_register(pwm); ++ if (ret) { ++ dev_err(dev, "failed to register pwm\n"); ++ goto err_clk_tdiv; ++ } ++ ++ pwm_dbg(pwm, "config bits %02x\n", ++ (__raw_readl(S3C2410_TCON) >> pwm->tcon_base) & 0x0f); ++ ++ dev_info(dev, "tin at %lu, tdiv at %lu, tin=%sclk, base %d\n", ++ clk_get_rate(pwm->clk), ++ clk_get_rate(pwm->clk_div), ++ pwm_is_tdiv(pwm) ? "div" : "ext", pwm->tcon_base); ++ ++ platform_set_drvdata(pdev, pwm); ++ return 0; ++ ++ err_clk_tdiv: ++ clk_put(pwm->clk_div); ++ ++ err_clk_tin: ++ clk_put(pwm->clk); ++ ++ err_alloc: ++ kfree(pwm); ++ return ret; ++} ++ ++static int s3c_pwm_remove(struct platform_device *pdev) ++{ ++ struct pwm_device *pwm = platform_get_drvdata(pdev); ++ ++ clk_put(pwm->clk_div); ++ clk_put(pwm->clk); ++ kfree(pwm); ++ ++ return 0; ++} ++ ++static struct platform_driver s3c_pwm_driver = { ++ .driver = { ++ .name = "s3c24xx-pwm", ++ .owner = THIS_MODULE, ++ }, ++ .probe = s3c_pwm_probe, ++ .remove = __devexit_p(s3c_pwm_remove), ++}; ++ ++static int __init pwm_init(void) ++{ ++ int ret; ++ ++ clk_scaler[0] = clk_get(NULL, "pwm-scaler0"); ++ clk_scaler[1] = clk_get(NULL, "pwm-scaler1"); ++ ++ if (IS_ERR(clk_scaler[0]) || IS_ERR(clk_scaler[1])) { ++ printk(KERN_ERR "%s: failed to get scaler clocks\n", __func__); ++ return -EINVAL; ++ } ++ ++ ret = platform_driver_register(&s3c_pwm_driver); ++ if (ret) ++ printk(KERN_ERR "%s: failed to add pwm driver\n", __func__); ++ ++ return ret; ++} ++ ++arch_initcall(pwm_init); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/s5pc100-clock.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/s5pc100-clock.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/s5pc100-clock.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/s5pc100-clock.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,1181 @@ ++/* linux/arch/arm/plat-s5pc1xx/s5pc100-clock.c ++ * ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++/* For S5PC100 EVT0 workaround ++ * When we modify DIVarm value to change ARM speed D0_BUS parent clock is also changed ++ * If we prevent from unwanted changing of bus clock, we should modify DIVd0_bus value also. ++ */ ++#define PREVENT_BUS_CLOCK_CHANGE ++ ++extern void ChangeClkDiv0(unsigned int val); ++ ++/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call ++ * ext_xtal_mux for want of an actual name from the manual. ++*/ ++static unsigned long s5pc1xx_roundrate_clksrc(struct clk *clk, unsigned long rate); ++ ++struct clk clk_ext_xtal_mux = { ++ .name = "ext_xtal", ++ .id = -1, ++}; ++ ++#define clk_fin_apll clk_ext_xtal_mux ++#define clk_fin_mpll clk_ext_xtal_mux ++#define clk_fin_epll clk_ext_xtal_mux ++#define clk_fin_hpll clk_ext_xtal_mux ++ ++#define clk_fout_mpll clk_mpll ++ ++struct clk_sources { ++ unsigned int nr_sources; ++ struct clk **sources; ++}; ++ ++struct clksrc_clk { ++ struct clk clk; ++ unsigned int mask; ++ unsigned int shift; ++ ++ struct clk_sources *sources; ++ ++ unsigned int divider_shift; ++ void __iomem *reg_divider; ++ void __iomem *reg_source; ++}; ++ ++struct clk clk_srclk = { ++ .name = "srclk", ++ .id = -1, ++}; ++ ++struct clk clk_fout_apll = { ++ .name = "fout_apll", ++ .id = -1, ++}; ++ ++static struct clk *clk_src_apll_list[] = { ++ [0] = &clk_fin_apll, ++ [1] = &clk_fout_apll, ++}; ++ ++static struct clk_sources clk_src_apll = { ++ .sources = clk_src_apll_list, ++ .nr_sources = ARRAY_SIZE(clk_src_apll_list), ++}; ++ ++struct clksrc_clk clk_mout_apll = { ++ .clk = { ++ .name = "mout_apll", ++ .id = -1, ++ }, ++ .shift = S5P_CLKSRC0_APLL_SHIFT, ++ .mask = S5P_CLKSRC0_APLL_MASK, ++ .sources = &clk_src_apll, ++ .reg_source = S5P_CLK_SRC0, ++}; ++ ++ ++static unsigned long s5pc1xx_clk_doutapll_get_rate(struct clk *clk) ++{ ++ unsigned long rate = clk_get_rate(clk->parent); ++ ++ rate /= (((__raw_readl(S5P_CLK_DIV0) & S5P_CLKDIV0_APLL_MASK) >> S5P_CLKDIV0_APLL_SHIFT) + 1); ++ ++ return rate; ++} ++ ++int s5pc1xx_clk_doutapll_set_rate(struct clk *clk, unsigned long rate) ++{ ++ struct clk *temp_clk = clk; ++ unsigned int div; ++ u32 val; ++ ++ rate = clk_round_rate(temp_clk, rate); ++ div = clk_get_rate(temp_clk->parent) / rate; ++ ++ val = __raw_readl(S5P_CLK_DIV0); ++ val &=~ S5P_CLKDIV0_APLL_MASK; ++ val |= (div - 1) << S5P_CLKDIV0_APLL_SHIFT; ++ __raw_writel(val, S5P_CLK_DIV0); ++ ++ return 0; ++} ++ ++struct clk clk_dout_apll = { ++ .name = "dout_apll", ++ .id = -1, ++ .parent = &clk_mout_apll.clk, ++ .get_rate = s5pc1xx_clk_doutapll_get_rate, ++ .set_rate = s5pc1xx_clk_doutapll_set_rate, ++}; ++ ++static unsigned long s5pc1xx_clk_doutarm_get_rate(struct clk *clk) ++{ ++ unsigned long rate = clk_get_rate(clk->parent); ++ ++ rate /= (((__raw_readl(S5P_CLK_DIV0) & S5P_CLKDIV0_ARM_MASK) >> S5P_CLKDIV0_ARM_SHIFT) + 1); ++ ++ return rate; ++} ++ ++static unsigned long s5pc1xx_doutarm_roundrate(struct clk *clk, ++ unsigned long rate) ++{ ++ unsigned long parent_rate = clk_get_rate(clk->parent); ++ int div; ++ ++ if (rate > parent_rate) ++ rate = parent_rate; ++ else { ++ div = parent_rate / rate; ++ ++ div ++; ++ ++ rate = parent_rate / div; ++ } ++ ++ return rate; ++} ++ ++int s5pc1xx_clk_doutarm_set_rate(struct clk *clk, unsigned long rate) ++{ ++ struct clk *temp_clk = clk; ++ unsigned int div_arm; ++ unsigned int val; ++#ifdef PREVENT_BUS_CLOCK_CHANGE ++ unsigned int d0_bus_ratio, arm_ratio_old, ratio; ++ val = __raw_readl(S5P_CLK_DIV0); ++ d0_bus_ratio = (val & S5P_CLKDIV0_D0_MASK) >> S5P_CLKDIV0_D0_SHIFT; ++ arm_ratio_old = (val & S5P_CLKDIV0_ARM_MASK) >> S5P_CLKDIV0_ARM_SHIFT; ++ ratio = (arm_ratio_old + 1) * (d0_bus_ratio + 1); ++#endif ++ div_arm = clk_get_rate(temp_clk->parent) / rate; ++ ++#ifndef PREVENT_BUS_CLOCK_CHANGE ++ val = __raw_readl(S5P_CLK_DIV0); ++ val &=~ S5P_CLKDIV0_ARM_MASK; ++ val |= (div_arm - 1) << S5P_CLKDIV0_ARM_SHIFT; ++#else ++ d0_bus_ratio = (ratio / div_arm) -1; ++ val &=~ (S5P_CLKDIV0_ARM_MASK | S5P_CLKDIV0_D0_MASK); ++ val |= (div_arm - 1) << S5P_CLKDIV0_ARM_SHIFT; ++ val |= d0_bus_ratio << S5P_CLKDIV0_D0_SHIFT; ++ //printk(KERN_INFO "d0_bus_ratio : %08d ,arm_ratio: %08d\n",d0_bus_ratio, (div_arm-1)); ++ ++#endif ++ ++#ifdef PREVENT_BUS_CLOCK_CHANGE ++ ++#if 0 ++ iter = 0x4000; ++ flag = __raw_readl(S5P_CLK_DIV0); ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ ++ : : "r" (flag) : "memory"); ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ ++ : : "r" (flag) : "memory"); ++ ++ do { ++ iter--; ++ if(iter == 0x2000) { ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ ++ : : "r" (flag) : "memory"); ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ ++ : : "r" (flag) : "memory"); ++ __raw_writel(val, S5P_CLK_DIV0); ++ } ++ if(iter <= 0) ++ break; ++ ++ } while(1); ++#else ++ /* Clock Down */ ++ if(arm_ratio_old < (div_arm - 1)) { ++ val = __raw_readl(S5P_CLK_DIV0); ++ val &=~ S5P_CLKDIV0_ARM_MASK; ++ val |= (div_arm - 1) << S5P_CLKDIV0_ARM_SHIFT; ++ __raw_writel(val, S5P_CLK_DIV0); ++ ++ val = __raw_readl(S5P_CLK_DIV0); ++ val &=~ S5P_CLKDIV0_D0_MASK; ++ val |= d0_bus_ratio << S5P_CLKDIV0_D0_SHIFT; ++ __raw_writel(val, S5P_CLK_DIV0); ++ ++ } else { ++ val = __raw_readl(S5P_CLK_DIV0); ++ val &=~ S5P_CLKDIV0_D0_MASK; ++ val |= d0_bus_ratio << S5P_CLKDIV0_D0_SHIFT; ++ __raw_writel(val, S5P_CLK_DIV0); ++ ++ val = __raw_readl(S5P_CLK_DIV0); ++ val &=~ S5P_CLKDIV0_ARM_MASK; ++ val |= (div_arm - 1) << S5P_CLKDIV0_ARM_SHIFT; ++ __raw_writel(val, S5P_CLK_DIV0); ++ } ++ ++#endif ++ ++#else ++ __raw_writel(val, S5P_CLK_DIV0); ++#endif ++ return 0; ++} ++ ++struct clk clk_dout_arm = { ++ .name = "dout_arm", ++ .id = -1, ++ .parent = &clk_dout_apll, ++ .get_rate = s5pc1xx_clk_doutarm_get_rate, ++ .set_rate = s5pc1xx_clk_doutarm_set_rate, ++ .round_rate = s5pc1xx_doutarm_roundrate, ++}; ++ ++struct clk clk_fout_epll = { ++ .name = "fout_epll", ++ .id = -1, ++}; ++ ++static struct clk *clk_src_epll_list[] = { ++ [0] = &clk_fin_epll, ++ [1] = &clk_fout_epll, ++}; ++ ++static struct clk_sources clk_src_epll = { ++ .sources = clk_src_epll_list, ++ .nr_sources = ARRAY_SIZE(clk_src_epll_list), ++}; ++ ++struct clksrc_clk clk_mout_epll = { ++ .clk = { ++ .name = "mout_epll", ++ .id = -1, ++ }, ++ .shift = S5P_CLKSRC0_EPLL_SHIFT, ++ .mask = S5P_CLKSRC0_EPLL_MASK, ++ .sources = &clk_src_epll, ++ .reg_source = S5P_CLK_SRC0, ++}; ++ ++static struct clk *clk_src_hpll_list[] = { ++ [0] = &clk_27m, ++ [1] = &clk_srclk, ++}; ++ ++static struct clk_sources clk_src_hpll = { ++ .sources = clk_src_hpll_list, ++ .nr_sources = ARRAY_SIZE(clk_src_hpll_list), ++}; ++ ++struct clksrc_clk clk_mout_hpll = { ++ .clk = { ++ .name = "mout_hpll", ++ .id = -1, ++ }, ++ .shift = S5P_CLKSRC0_HPLL_SHIFT, ++ .mask = S5P_CLKSRC0_HPLL_MASK, ++ .sources = &clk_src_hpll, ++ .reg_source = S5P_CLK_SRC0, ++}; ++ ++static struct clk *clk_src_mpll_list[] = { ++ [0] = &clk_fin_mpll, ++ [1] = &clk_fout_mpll, ++}; ++ ++static struct clk_sources clk_src_mpll = { ++ .sources = clk_src_mpll_list, ++ .nr_sources = ARRAY_SIZE(clk_src_mpll_list), ++}; ++ ++struct clksrc_clk clk_mout_mpll = { ++ .clk = { ++ .name = "mout_mpll", ++ .id = -1, ++ }, ++ .shift = S5P_CLKSRC0_MPLL_SHIFT, ++ .mask = S5P_CLKSRC0_MPLL_MASK, ++ .sources = &clk_src_mpll, ++ .reg_source = S5P_CLK_SRC0, ++}; ++ ++static unsigned long s5pc1xx_clk_doutmpll_get_rate(struct clk *clk) ++{ ++ unsigned long rate = clk_get_rate(clk->parent); ++ ++ /* printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); */ ++ ++ rate /= (((__raw_readl(S5P_CLK_DIV1) & S5P_CLKDIV1_MPLL_MASK) >> S5P_CLKDIV1_MPLL_SHIFT) + 1); ++ ++ return rate; ++} ++ ++struct clk clk_dout_mpll = { ++ .name = "dout_mpll", ++ .id = -1, ++ .parent = &clk_mout_mpll.clk, ++ .get_rate = s5pc1xx_clk_doutmpll_get_rate, ++}; ++ ++static unsigned long s5pc1xx_clk_doutmpll2_get_rate(struct clk *clk) ++{ ++ unsigned long rate = clk_get_rate(clk->parent); ++ ++ printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); ++ ++ rate /= (((__raw_readl(S5P_CLK_DIV1) & S5P_CLKDIV1_MPLL2_MASK) >> S5P_CLKDIV1_MPLL2_SHIFT) + 1); ++ ++ return rate; ++} ++ ++struct clk clk_dout_mpll2 = { ++ .name = "dout_mpll2", ++ .id = -1, ++ .parent = &clk_mout_mpll.clk, ++ .get_rate = s5pc1xx_clk_doutmpll2_get_rate, ++}; ++ ++static unsigned long s5pc1xx_clk_sclk_hdmi_get_rate(struct clk *clk) ++{ ++ unsigned long rate = clk_get_rate(clk->parent); ++ ++ printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); ++ ++ rate /= (((__raw_readl(S5P_CLK_DIV3) & S5P_CLKDIV3_HDMI_MASK) >> S5P_CLKDIV3_HDMI_SHIFT) + 1); ++ ++ return rate; ++} ++ ++struct clk clk_sclk_hdmi = { ++ .name = "sclk_hdmi", ++ .id = -1, ++ .parent = &clk_mout_hpll.clk, ++ .get_rate = s5pc1xx_clk_sclk_hdmi_get_rate, ++}; ++ ++static struct clk *clkset_spi_list[] = { ++ &clk_mout_epll.clk, ++ &clk_dout_mpll2, ++ &clk_fin_epll, ++ &clk_mout_hpll.clk, ++}; ++ ++static struct clk_sources clkset_spi = { ++ .sources = clkset_spi_list, ++ .nr_sources = ARRAY_SIZE(clkset_spi_list), ++}; ++ ++static struct clk *clkset_uart_list[] = { ++ &clk_mout_epll.clk, ++ &clk_dout_mpll, ++ NULL, ++ NULL, ++}; ++ ++static struct clk_sources clkset_uart = { ++ .sources = clkset_uart_list, ++ .nr_sources = ARRAY_SIZE(clkset_uart_list), ++}; ++ ++static struct clk *clkset_irda_list[] = { ++ &clk_mout_epll.clk, ++ &clk_dout_mpll, ++ &clk_mout_hpll.clk, ++ &clk_48m, ++}; ++ ++static struct clk_sources clkset_irda = { ++ .sources = clkset_irda_list, ++ .nr_sources = ARRAY_SIZE(clkset_irda_list), ++}; ++ ++static struct clk *clkset_uhost_list[] = { ++ &clk_mout_epll.clk, ++ &clk_dout_mpll, ++ &clk_mout_hpll.clk, ++ &clk_48m, ++}; ++ ++static struct clk_sources clkset_uhost = { ++ .sources = clkset_uhost_list, ++ .nr_sources = ARRAY_SIZE(clkset_uhost_list), ++}; ++ ++static struct clk *clkset_mmc0_list[] = { ++ &clk_mout_epll.clk, ++ &clk_dout_mpll, ++ &clk_fin_epll, ++ NULL, ++}; ++ ++static struct clk_sources clkset_mmc0 = { ++ .sources = clkset_mmc0_list, ++ .nr_sources = ARRAY_SIZE(clkset_mmc0_list), ++}; ++ ++static struct clk *clkset_mmc1_list[] = { ++ &clk_mout_epll.clk, ++ &clk_dout_mpll, ++ &clk_fin_epll, ++ &clk_mout_hpll.clk, ++}; ++ ++static struct clk_sources clkset_mmc1 = { ++ .sources = clkset_mmc1_list, ++ .nr_sources = ARRAY_SIZE(clkset_mmc1_list), ++}; ++ ++static struct clk *clkset_mmc2_list[] = { ++ &clk_mout_epll.clk, ++ &clk_dout_mpll, ++ &clk_fin_epll, ++ &clk_mout_hpll.clk, ++}; ++ ++static struct clk_sources clkset_mmc2 = { ++ .sources = clkset_mmc2_list, ++ .nr_sources = ARRAY_SIZE(clkset_mmc2_list), ++}; ++ ++static struct clk *clkset_lcd_list[] = { ++ &clk_mout_epll.clk, ++ &clk_dout_mpll, ++ &clk_mout_hpll.clk, ++ &clk_54m, ++}; ++ ++static struct clk_sources clkset_lcd = { ++ .sources = clkset_lcd_list, ++ .nr_sources = ARRAY_SIZE(clkset_lcd_list), ++}; ++ ++static struct clk *clkset_fimc_list[] = { ++ &clk_mout_epll.clk, ++ &clk_dout_mpll, ++ &clk_mout_hpll.clk, ++ &clk_54m, ++}; ++ ++static struct clk_sources clkset_fimc = { ++ .sources = clkset_fimc_list, ++ .nr_sources = ARRAY_SIZE(clkset_fimc_list), ++}; ++ ++static struct clk *clkset_mixer_list[] = { ++ &clk_27m, ++ &clk_54m, ++ &clk_sclk_hdmi, ++ NULL, ++}; ++ ++static struct clk_sources clkset_mixer = { ++ .sources = clkset_mixer_list, ++ .nr_sources = ARRAY_SIZE(clkset_mixer_list), ++}; ++ ++static struct clk *clkset_pwi_list[] = { ++ &clk_srclk, ++ &clk_mout_epll.clk, ++ &clk_dout_mpll, ++ NULL, ++}; ++ ++static struct clk_sources clkset_pwi = { ++ .sources = clkset_pwi_list, ++ .nr_sources = ARRAY_SIZE(clkset_pwi_list), ++}; ++ ++/* The peripheral clocks are all controlled via clocksource followed ++ * by an optional divider and gate stage. We currently roll this into ++ * one clock which hides the intermediate clock from the mux. ++ * ++ * Note, the JPEG clock can only be an even divider... ++ * ++ * The scaler and LCD clocks depend on the S3C64XX version, and also ++ * have a common parent divisor so are not included here. ++ */ ++ ++static inline struct clksrc_clk *to_clksrc(struct clk *clk) ++{ ++ return container_of(clk, struct clksrc_clk, clk); ++} ++ ++static unsigned long s5pc1xx_getrate_clksrc(struct clk *clk) ++{ ++ struct clksrc_clk *sclk = to_clksrc(clk); ++ unsigned long rate = clk_get_rate(clk->parent); ++ u32 clkdiv = __raw_readl(sclk->reg_divider); ++ ++ clkdiv >>= sclk->divider_shift; ++ clkdiv &= 0xf; ++ clkdiv++; ++ ++ rate /= clkdiv; ++ return rate; ++} ++ ++static int s5pc1xx_setrate_clksrc(struct clk *clk, unsigned long rate) ++{ ++ struct clksrc_clk *sclk = to_clksrc(clk); ++ void __iomem *reg = sclk->reg_divider; ++ unsigned int div; ++ u32 val; ++ ++ rate = clk_round_rate(clk, rate); ++ div = clk_get_rate(clk->parent) / rate; ++ ++ val = __raw_readl(reg); ++ val &= ~sclk->mask; ++ val |= (div - 1) << sclk->shift; ++ __raw_writel(val, reg); ++ ++ return 0; ++} ++ ++static int s5pc1xx_setparent_clksrc(struct clk *clk, struct clk *parent) ++{ ++ struct clksrc_clk *sclk = to_clksrc(clk); ++ struct clk_sources *srcs = sclk->sources; ++ u32 clksrc = __raw_readl(sclk->reg_source); ++ int src_nr = -1; ++ int ptr; ++ ++ for (ptr = 0; ptr < srcs->nr_sources; ptr++) ++ if (srcs->sources[ptr] == parent) { ++ src_nr = ptr; ++ break; ++ } ++ ++ if (src_nr >= 0) { ++ clksrc &= ~sclk->mask; ++ clksrc |= src_nr << sclk->shift; ++ ++ __raw_writel(clksrc, sclk->reg_source); ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static unsigned long s5pc1xx_roundrate_clksrc(struct clk *clk, ++ unsigned long rate) ++{ ++ unsigned long parent_rate = clk_get_rate(clk->parent); ++ int div; ++ ++ if (rate > parent_rate) ++ rate = parent_rate; ++ else { ++ div = rate / parent_rate; ++ ++ if (div == 0) ++ div = 1; ++ if (div > 16) ++ div = 16; ++ ++ rate = parent_rate / div; ++ } ++ ++ return rate; ++} ++ ++static struct clksrc_clk clk_mmc0 = { ++ .clk = { ++ .name = "mmc_bus", ++ .id = 0, ++ .ctrlbit = S5P_CLKGATE_SCLK0_MMC0, ++ .enable = s5pc1xx_sclk0_ctrl, ++ .set_parent = s5pc1xx_setparent_clksrc, ++ .get_rate = s5pc1xx_getrate_clksrc, ++ .set_rate = s5pc1xx_setrate_clksrc, ++ .round_rate = s5pc1xx_roundrate_clksrc, ++ }, ++ .shift = S5P_CLKSRC2_MMC0_SHIFT, ++ .mask = S5P_CLKSRC2_MMC0_MASK, ++ .sources = &clkset_mmc0, ++ .divider_shift = S5P_CLKDIV3_MMC0_SHIFT, ++ .reg_divider = S5P_CLK_DIV3, ++ .reg_source = S5P_CLK_SRC2, ++}; ++ ++static struct clksrc_clk clk_mmc1 = { ++ .clk = { ++ .name = "mmc_bus", ++ .id = 1, ++ .ctrlbit = S5P_CLKGATE_SCLK0_MMC1, ++ .enable = s5pc1xx_sclk0_ctrl, ++ .set_parent = s5pc1xx_setparent_clksrc, ++ .get_rate = s5pc1xx_getrate_clksrc, ++ .set_rate = s5pc1xx_setrate_clksrc, ++ .round_rate = s5pc1xx_roundrate_clksrc, ++ }, ++ .shift = S5P_CLKSRC2_MMC1_SHIFT, ++ .mask = S5P_CLKSRC2_MMC1_MASK, ++ .sources = &clkset_mmc1, ++ .divider_shift = S5P_CLKDIV3_MMC1_SHIFT, ++ .reg_divider = S5P_CLK_DIV3, ++ .reg_source = S5P_CLK_SRC2, ++}; ++ ++static struct clksrc_clk clk_mmc2 = { ++ .clk = { ++ .name = "mmc_bus", ++ .id = 2, ++ .ctrlbit = S5P_CLKGATE_SCLK0_MMC2, ++ .enable = s5pc1xx_sclk0_ctrl, ++ .set_parent = s5pc1xx_setparent_clksrc, ++ .get_rate = s5pc1xx_getrate_clksrc, ++ .set_rate = s5pc1xx_setrate_clksrc, ++ .round_rate = s5pc1xx_roundrate_clksrc, ++ }, ++ .shift = S5P_CLKSRC2_MMC2_SHIFT, ++ .mask = S5P_CLKSRC2_MMC2_MASK, ++ .sources = &clkset_mmc2, ++ .divider_shift = S5P_CLKDIV3_MMC2_SHIFT, ++ .reg_divider = S5P_CLK_DIV3, ++ .reg_source = S5P_CLK_SRC2, ++}; ++ ++static struct clksrc_clk clk_usbhost = { ++ .clk = { ++ .name = "usb-host-bus", ++ .id = -1, ++ .ctrlbit = S5P_CLKGATE_SCLK0_USBHOST, ++ .enable = s5pc1xx_sclk0_ctrl, ++ .set_parent = s5pc1xx_setparent_clksrc, ++ .get_rate = s5pc1xx_getrate_clksrc, ++ .set_rate = s5pc1xx_setrate_clksrc, ++ .round_rate = s5pc1xx_roundrate_clksrc, ++ }, ++ .shift = S5P_CLKSRC1_UHOST_SHIFT, ++ .mask = S5P_CLKSRC1_UHOST_MASK, ++ .sources = &clkset_uhost, ++ .divider_shift = S5P_CLKDIV2_UHOST_SHIFT, ++ .reg_divider = S5P_CLK_DIV2, ++ .reg_source = S5P_CLK_SRC1, ++}; ++ ++static struct clksrc_clk clk_uart_uclk1 = { ++ .clk = { ++ .name = "uclk1", ++ .id = -1, ++ .ctrlbit = S5P_CLKGATE_SCLK0_UART, ++ .enable = s5pc1xx_sclk0_ctrl, ++ .set_parent = s5pc1xx_setparent_clksrc, ++ .get_rate = s5pc1xx_getrate_clksrc, ++ .set_rate = s5pc1xx_setrate_clksrc, ++ .round_rate = s5pc1xx_roundrate_clksrc, ++ }, ++ .shift = S5P_CLKSRC1_UART_SHIFT, ++ .mask = S5P_CLKSRC1_UART_MASK, ++ .sources = &clkset_uart, ++ .divider_shift = S5P_CLKDIV2_UART_SHIFT, ++ .reg_divider = S5P_CLK_DIV2, ++ .reg_source = S5P_CLK_SRC1, ++}; ++ ++static struct clksrc_clk clk_spi0 = { ++ .clk = { ++ .name = "spi-bus", ++ .id = 0, ++ .ctrlbit = S5P_CLKGATE_SCLK0_SPI0, ++ .enable = s5pc1xx_sclk0_ctrl, ++ .set_parent = s5pc1xx_setparent_clksrc, ++ .get_rate = s5pc1xx_getrate_clksrc, ++ .set_rate = s5pc1xx_setrate_clksrc, ++ .round_rate = s5pc1xx_roundrate_clksrc, ++ }, ++ .shift = S5P_CLKSRC1_SPI0_SHIFT, ++ .mask = S5P_CLKSRC1_SPI0_MASK, ++ .sources = &clkset_spi, ++ .divider_shift = S5P_CLKDIV2_SPI0_SHIFT, ++ .reg_divider = S5P_CLK_DIV2, ++ .reg_source = S5P_CLK_SRC1, ++}; ++ ++static struct clksrc_clk clk_spi1 = { ++ .clk = { ++ .name = "spi-bus", ++ .id = 1, ++ .ctrlbit = S5P_CLKGATE_SCLK0_SPI1, ++ .enable = s5pc1xx_sclk0_ctrl, ++ .set_parent = s5pc1xx_setparent_clksrc, ++ .get_rate = s5pc1xx_getrate_clksrc, ++ .set_rate = s5pc1xx_setrate_clksrc, ++ .round_rate = s5pc1xx_roundrate_clksrc, ++ }, ++ .shift = S5P_CLKSRC1_SPI1_SHIFT, ++ .mask = S5P_CLKSRC1_SPI1_MASK, ++ .sources = &clkset_spi, ++ .divider_shift = S5P_CLKDIV2_SPI1_SHIFT, ++ .reg_divider = S5P_CLK_DIV2, ++ .reg_source = S5P_CLK_SRC1, ++}; ++ ++static struct clksrc_clk clk_spi2 = { ++ .clk = { ++ .name = "spi-bus", ++ .id = 2, ++ .ctrlbit = S5P_CLKGATE_SCLK0_SPI2, ++ .enable = s5pc1xx_sclk0_ctrl, ++ .set_parent = s5pc1xx_setparent_clksrc, ++ .get_rate = s5pc1xx_getrate_clksrc, ++ .set_rate = s5pc1xx_setrate_clksrc, ++ .round_rate = s5pc1xx_roundrate_clksrc, ++ }, ++ .shift = S5P_CLKSRC1_SPI2_SHIFT, ++ .mask = S5P_CLKSRC1_SPI2_MASK, ++ .sources = &clkset_spi, ++ .divider_shift = S5P_CLKDIV2_SPI2_SHIFT, ++ .reg_divider = S5P_CLK_DIV2, ++ .reg_source = S5P_CLK_SRC1, ++}; ++ ++static struct clksrc_clk clk_irda = { ++ .clk = { ++ .name = "sclk_irda", ++ .id = -1, ++ .ctrlbit = S5P_CLKGATE_SCLK0_IRDA, ++ .enable = s5pc1xx_sclk0_ctrl, ++ .set_parent = s5pc1xx_setparent_clksrc, ++ .get_rate = s5pc1xx_getrate_clksrc, ++ .set_rate = s5pc1xx_setrate_clksrc, ++ .round_rate = s5pc1xx_roundrate_clksrc, ++ }, ++ .shift = S5P_CLKSRC1_IRDA_SHIFT, ++ .mask = S5P_CLKSRC1_IRDA_MASK, ++ .sources = &clkset_irda, ++ .divider_shift = S5P_CLKDIV2_IRDA_SHIFT, ++ .reg_divider = S5P_CLK_DIV2, ++ .reg_source = S5P_CLK_SRC1, ++}; ++ ++static struct clksrc_clk clk_pwi = { ++ .clk = { ++ .name = "sclk_pwi", ++ .id = -1, ++ .ctrlbit = S5P_CLKGATE_SCLK0_PWI, ++ .enable = s5pc1xx_sclk0_ctrl, ++ .set_parent = s5pc1xx_setparent_clksrc, ++ .get_rate = s5pc1xx_getrate_clksrc, ++ .set_rate = s5pc1xx_setrate_clksrc, ++ .round_rate = s5pc1xx_roundrate_clksrc, ++ }, ++ .shift = S5P_CLKSRC3_PWI_SHIFT, ++ .mask = S5P_CLKSRC3_PWI_MASK, ++ .sources = &clkset_pwi, ++ .divider_shift = S5P_CLKDIV4_PWI_SHIFT, ++ .reg_divider = S5P_CLK_DIV4, ++ .reg_source = S5P_CLK_SRC3, ++}; ++ ++static struct clksrc_clk clk_lcd = { ++ .clk = { ++ .name = "sclk_lcd", ++ .id = -1, ++ .ctrlbit = S5P_CLKGATE_SCLK1_LCD, ++ .enable = s5pc1xx_sclk1_ctrl, ++ .set_parent = s5pc1xx_setparent_clksrc, ++ .get_rate = s5pc1xx_getrate_clksrc, ++ .set_rate = s5pc1xx_setrate_clksrc, ++ .round_rate = s5pc1xx_roundrate_clksrc, ++ }, ++ .shift = S5P_CLKSRC2_LCD_SHIFT, ++ .mask = S5P_CLKSRC2_LCD_MASK, ++ .sources = &clkset_lcd, ++ .divider_shift = S5P_CLKDIV3_LCD_SHIFT, ++ .reg_divider = S5P_CLK_DIV3, ++ .reg_source = S5P_CLK_SRC2, ++}; ++ ++static struct clksrc_clk clk_fimc0 = { ++ .clk = { ++ .name = "sclk_fimc", ++ .id = 0, ++ .ctrlbit = S5P_CLKGATE_SCLK1_FIMC0, ++ .enable = s5pc1xx_sclk1_ctrl, ++ .set_parent = s5pc1xx_setparent_clksrc, ++ .get_rate = s5pc1xx_getrate_clksrc, ++ .set_rate = s5pc1xx_setrate_clksrc, ++ .round_rate = s5pc1xx_roundrate_clksrc, ++ }, ++ .shift = S5P_CLKSRC2_FIMC0_SHIFT, ++ .mask = S5P_CLKSRC2_FIMC0_MASK, ++ .sources = &clkset_fimc, ++ .divider_shift = S5P_CLKDIV3_FIMC0_SHIFT, ++ .reg_divider = S5P_CLK_DIV3, ++ .reg_source = S5P_CLK_SRC2, ++}; ++ ++static struct clksrc_clk clk_fimc1 = { ++ .clk = { ++ .name = "sclk_fimc", ++ .id = 1, ++ .ctrlbit = S5P_CLKGATE_SCLK1_FIMC1, ++ .enable = s5pc1xx_sclk1_ctrl, ++ .set_parent = s5pc1xx_setparent_clksrc, ++ .get_rate = s5pc1xx_getrate_clksrc, ++ .set_rate = s5pc1xx_setrate_clksrc, ++ .round_rate = s5pc1xx_roundrate_clksrc, ++ }, ++ .shift = S5P_CLKSRC2_FIMC1_SHIFT, ++ .mask = S5P_CLKSRC2_FIMC1_MASK, ++ .sources = &clkset_fimc, ++ .divider_shift = S5P_CLKDIV3_FIMC1_SHIFT, ++ .reg_divider = S5P_CLK_DIV3, ++ .reg_source = S5P_CLK_SRC2, ++}; ++ ++static struct clksrc_clk clk_fimc2 = { ++ .clk = { ++ .name = "sclk_fimc", ++ .id = 2, ++ .ctrlbit = S5P_CLKGATE_SCLK1_FIMC2, ++ .enable = s5pc1xx_sclk1_ctrl, ++ .set_parent = s5pc1xx_setparent_clksrc, ++ .get_rate = s5pc1xx_getrate_clksrc, ++ .set_rate = s5pc1xx_setrate_clksrc, ++ .round_rate = s5pc1xx_roundrate_clksrc, ++ }, ++ .shift = S5P_CLKSRC2_FIMC2_SHIFT, ++ .mask = S5P_CLKSRC2_FIMC2_MASK, ++ .sources = &clkset_fimc, ++ .divider_shift = S5P_CLKDIV3_FIMC2_SHIFT, ++ .reg_divider = S5P_CLK_DIV3, ++ .reg_source = S5P_CLK_SRC2, ++}; ++ ++static struct clksrc_clk clk_mixer = { ++ .clk = { ++ .name = "sclk_mixer", ++ .id = -1, ++ .ctrlbit = S5P_CLKGATE_SCLK1_MIXER, ++ .enable = s5pc1xx_sclk1_ctrl, ++ .set_parent = s5pc1xx_setparent_clksrc, ++ .get_rate = s5pc1xx_getrate_clksrc, ++ .set_rate = s5pc1xx_setrate_clksrc, ++ .round_rate = s5pc1xx_roundrate_clksrc, ++ }, ++ .shift = S5P_CLKSRC2_MIXER_SHIFT, ++ .mask = S5P_CLKSRC2_MIXER_MASK, ++ .sources = &clkset_mixer, ++ .divider_shift = S5P_CLKDIV3_HDMI_SHIFT, ++ .reg_divider = S5P_CLK_DIV3, ++ .reg_source = S5P_CLK_SRC2, ++}; ++ ++struct clk clk_iis_cd0 = { ++ .name = "iis_cdclk0", ++ .id = -1, ++}; ++ ++struct clk clk_iis_cd1 = { ++ .name = "iiscd_cdclk1", ++ .id = -1, ++}; ++ ++struct clk clk_iis_cd2 = { ++ .name = "iiscd_cdclk2", ++ .id = -1, ++}; ++ ++struct clk clk_pcm_cd0 = { ++ .name = "pcmcd_cdclk0", ++ .id = -1, ++}; ++ ++struct clk clk_pcm_cd1 = { ++ .name = "pcmcd_cdclk1", ++ .id = -1, ++}; ++ ++static struct clk *clkset_audio0_list[] = { ++ [0] = &clk_mout_epll.clk, ++ [1] = &clk_dout_mpll, ++ [2] = &clk_fin_epll, ++ [3] = &clk_iis_cd0, ++ [4] = &clk_pcm_cd0, ++ [5] = &clk_mout_hpll.clk, ++}; ++ ++static struct clk_sources clkset_audio0 = { ++ .sources = clkset_audio0_list, ++ .nr_sources = ARRAY_SIZE(clkset_audio0_list), ++}; ++ ++static struct clksrc_clk clk_audio0 = { ++ .clk = { ++ .name = "audio-bus", ++ .id = 0, ++ .ctrlbit = S5P_CLKGATE_SCLK1_AUDIO0, ++ .enable = s5pc1xx_sclk1_ctrl, ++ .set_parent = s5pc1xx_setparent_clksrc, ++ .get_rate = s5pc1xx_getrate_clksrc, ++ .set_rate = s5pc1xx_setrate_clksrc, ++ .round_rate = s5pc1xx_roundrate_clksrc, ++ }, ++ .shift = S5P_CLKSRC3_AUDIO0_SHIFT, ++ .mask = S5P_CLKSRC3_AUDIO0_MASK, ++ .sources = &clkset_audio0, ++ .divider_shift = S5P_CLKDIV4_AUDIO0_SHIFT, ++ .reg_divider = S5P_CLK_DIV4, ++ .reg_source = S5P_CLK_SRC3, ++}; ++ ++static struct clk *clkset_audio1_list[] = { ++ [0] = &clk_mout_epll.clk, ++ [1] = &clk_dout_mpll, ++ [2] = &clk_fin_epll, ++ [3] = &clk_iis_cd1, ++ [4] = &clk_pcm_cd1, ++ [5] = &clk_mout_hpll.clk, ++}; ++ ++static struct clk_sources clkset_audio1 = { ++ .sources = clkset_audio1_list, ++ .nr_sources = ARRAY_SIZE(clkset_audio1_list), ++}; ++ ++static struct clksrc_clk clk_audio1 = { ++ .clk = { ++ .name = "audio-bus", ++ .id = 1, ++ .ctrlbit = S5P_CLKGATE_SCLK1_AUDIO1, ++ .enable = s5pc1xx_sclk1_ctrl, ++ .set_parent = s5pc1xx_setparent_clksrc, ++ .get_rate = s5pc1xx_getrate_clksrc, ++ .set_rate = s5pc1xx_setrate_clksrc, ++ .round_rate = s5pc1xx_roundrate_clksrc, ++ }, ++ .shift = S5P_CLKSRC3_AUDIO1_SHIFT, ++ .mask = S5P_CLKSRC3_AUDIO1_MASK, ++ .sources = &clkset_audio1, ++ .divider_shift = S5P_CLKDIV4_AUDIO1_SHIFT, ++ .reg_divider = S5P_CLK_DIV4, ++ .reg_source = S5P_CLK_SRC3, ++}; ++ ++static struct clk *clkset_audio2_list[] = { ++ [0] = &clk_mout_epll.clk, ++ [1] = &clk_dout_mpll, ++ [2] = &clk_fin_epll, ++ [3] = &clk_iis_cd2, ++ [4] = &clk_mout_hpll.clk, ++}; ++ ++static struct clk_sources clkset_audio2 = { ++ .sources = clkset_audio2_list, ++ .nr_sources = ARRAY_SIZE(clkset_audio2_list), ++}; ++ ++static struct clksrc_clk clk_audio2 = { ++ .clk = { ++ .name = "audio-bus", ++ .id = 2, ++ .ctrlbit = S5P_CLKGATE_SCLK1_AUDIO2, ++ .enable = s5pc1xx_sclk1_ctrl, ++ .set_parent = s5pc1xx_setparent_clksrc, ++ .get_rate = s5pc1xx_getrate_clksrc, ++ .set_rate = s5pc1xx_setrate_clksrc, ++ .round_rate = s5pc1xx_roundrate_clksrc, ++ }, ++ .shift = S5P_CLKSRC3_AUDIO2_SHIFT, ++ .mask = S5P_CLKSRC3_AUDIO2_MASK, ++ .sources = &clkset_audio2, ++ .divider_shift = S5P_CLKDIV4_AUDIO2_SHIFT, ++ .reg_divider = S5P_CLK_DIV4, ++ .reg_source = S5P_CLK_SRC3, ++}; ++ ++/* Clock initialisation code */ ++ ++static struct clksrc_clk *init_parents[] = { ++ &clk_mout_apll, ++ &clk_mout_epll, ++ &clk_mout_mpll, ++ &clk_mout_hpll, ++ &clk_mmc0, ++ &clk_mmc1, ++ &clk_mmc2, ++ &clk_usbhost, ++ &clk_uart_uclk1, ++ &clk_spi0, ++ &clk_spi1, ++ &clk_spi2, ++ &clk_audio0, ++ &clk_audio1, ++ &clk_audio2, ++ &clk_irda, ++ &clk_pwi, ++ &clk_lcd, ++ &clk_fimc0, ++ &clk_fimc1, ++ &clk_fimc2, ++ &clk_mixer, ++}; ++ ++static void __init_or_cpufreq s5pc1xx_set_clksrc(struct clksrc_clk *clk) ++{ ++ struct clk_sources *srcs = clk->sources; ++ u32 clksrc = __raw_readl(clk->reg_source); ++ ++ clksrc &= clk->mask; ++ clksrc >>= clk->shift; ++ ++ if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) { ++ printk(KERN_ERR "%s: bad source %d\n", ++ clk->clk.name, clksrc); ++ return; ++ } ++ ++ clk->clk.parent = srcs->sources[clksrc]; ++ ++ printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", ++ clk->clk.name, clk->clk.parent->name, clksrc, ++ clk_get_rate(&clk->clk)); ++} ++ ++#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) ++ ++void __init_or_cpufreq s5pc100_setup_clocks(void) ++{ ++ struct clk *xtal_clk; ++ unsigned long xtal; ++ unsigned long armclk; ++ unsigned long hclkd0; ++ unsigned long hclk; ++ unsigned long pclkd0; ++ unsigned long pclk; ++ unsigned long apll; ++ unsigned long mpll; ++ unsigned long hpll; ++ unsigned long epll; ++ unsigned int ptr; ++ u32 clkdiv0, clkdiv1; ++ ++ printk(KERN_DEBUG "%s: registering clocks\n", __func__); ++ ++ clkdiv0 = __raw_readl(S5P_CLK_DIV0); ++ clkdiv1 = __raw_readl(S5P_CLK_DIV1); ++ ++ printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", __func__, clkdiv0, clkdiv1); ++ ++ xtal_clk = clk_get(NULL, "xtal"); ++ BUG_ON(IS_ERR(xtal_clk)); ++ ++ xtal = clk_get_rate(xtal_clk); ++ clk_put(xtal_clk); ++ ++ printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); ++ ++ apll = s5pc1xx_get_pll(xtal, __raw_readl(S5P_APLL_CON)); ++ mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5P_MPLL_CON)); ++ epll = s5pc1xx_get_pll(xtal, __raw_readl(S5P_EPLL_CON)); ++ hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5P_HPLL_CON)); ++ ++ printk(KERN_INFO "S5PC100: PLL settings, A=%ld, M=%ld, E=%ld, H=%ld\n", ++ apll, mpll, epll, hpll); ++ ++ armclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_APLL); ++ armclk = armclk / GET_DIV(clkdiv0, S5P_CLKDIV0_ARM); ++ hclkd0 = armclk / GET_DIV(clkdiv0, S5P_CLKDIV0_D0); ++ pclkd0 = hclkd0 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLKD0); ++ hclk = mpll / GET_DIV(clkdiv1, S5P_CLKDIV1_D1); ++ pclk = hclk / GET_DIV(clkdiv1, S5P_CLKDIV1_PCLKD1); ++ ++ printk(KERN_INFO "S5PC100: ARMCLK=%ld, HCLKD0=%ld, PCLKD0=%ld, HCLK=%ld, PCLK=%ld\n", ++ armclk, hclkd0, pclkd0, hclk, pclk); ++ ++ clk_fout_apll.rate = apll; ++ clk_fout_mpll.rate = mpll; ++ clk_fout_epll.rate = epll; ++ clk_mout_hpll.clk.rate = hpll; ++ ++ clk_f.rate = armclk; ++ clk_hd0.rate = hclkd0; ++ clk_pd0.rate = pclkd0; ++ clk_h.rate = hclk; ++ clk_p.rate = pclk; ++ ++ for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) ++ s5pc1xx_set_clksrc(init_parents[ptr]); ++} ++ ++static struct clk *clks[] __initdata = { ++ &clk_ext_xtal_mux, ++ &clk_iis_cd0, ++ &clk_iis_cd1, ++ &clk_iis_cd2, ++ &clk_pcm_cd0, ++ &clk_pcm_cd1, ++ &clk_mout_epll.clk, ++ &clk_fout_epll, ++ &clk_mout_mpll.clk, ++ &clk_dout_mpll, ++ &clk_dout_mpll2, ++ &clk_mout_hpll.clk, ++ &clk_sclk_hdmi, ++ &clk_srclk, ++ &clk_mmc0.clk, ++ &clk_mmc1.clk, ++ &clk_mmc2.clk, ++ &clk_usbhost.clk, ++ &clk_uart_uclk1.clk, ++ &clk_spi0.clk, ++ &clk_spi1.clk, ++ &clk_spi2.clk, ++ &clk_audio0.clk, ++ &clk_audio1.clk, ++ &clk_audio2.clk, ++ &clk_irda.clk, ++ &clk_pwi.clk, ++ &clk_lcd.clk, ++ &clk_fimc0.clk, ++ &clk_fimc1.clk, ++ &clk_fimc2.clk, ++ &clk_mixer.clk, ++ &clk_dout_apll, ++ &clk_dout_arm, ++}; ++ ++void __init s5pc100_register_clocks(void) ++{ ++ struct clk *clkp; ++ int ret; ++ int ptr; ++ ++ for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { ++ clkp = clks[ptr]; ++ ret = s3c24xx_register_clock(clkp); ++ if (ret < 0) { ++ printk(KERN_ERR "Failed to register clock %s (%d)\n", ++ clkp->name, ret); ++ } ++ } ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/s5pc100-init.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/s5pc100-init.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/s5pc100-init.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/s5pc100-init.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,28 @@ ++/* linux/arch/arm/plat-s5pc1xx/s5pc100-init.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * S5PC100 - CPU initialisation (common with other S5PC1XX chips) ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++/* uart registration process */ ++ ++void __init s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) ++{ ++ s3c24xx_init_uartdevs("s5pc100-uart", s5pc1xx_uart_resources, cfg, no); ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/s5pc1xx-cpufreq.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/s5pc1xx-cpufreq.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/s5pc1xx-cpufreq.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/s5pc1xx-cpufreq.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,224 @@ ++/* ++ * linux/arch/arm/plat-s3c64xx/s3c64xx-cpufreq.c ++ * ++ * CPU frequency scaling for S3C64XX ++ * ++ * Copyright (C) 2008 Samsung Electronics ++ * ++ * Based on cpu-sa1110.c, Copyright (C) 2001 Russell King ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//#include ++#include ++ ++#include ++#include ++ ++#include ++ ++#define USE_FREQ_TABLE ++ ++#define USE_DVS ++ ++#define VERY_HI_RATE 666*1000*1000 ++#define APLL_GEN_CLK 666*1000 //khz ++#define KHZ_T 1000 ++ ++#define MPU_CLK "dout_arm" ++ ++/* definition for power setting function */ ++extern int set_power(unsigned int freq); ++extern void ltc3714_init(void); ++ ++#define PMIC_ARM 0 ++#define PMIC_INT 1 ++#define PMIC_BOTH 2 ++ ++#define CLK_OUT_PROBING //TP80 on SMDKC100 board ++ ++ ++/* frequency */ ++static struct cpufreq_frequency_table s5pc100_freq_table[] = { ++ {APLL_GEN_CLK, APLL_GEN_CLK}, ++ {APLL_GEN_CLK, APLL_GEN_CLK/2}, ++ {APLL_GEN_CLK, APLL_GEN_CLK/4}, ++ {0, CPUFREQ_TABLE_END}, ++}; ++ ++/* TODO: Add support for SDRAM timing changes */ ++ ++int s5pc100_verify_speed(struct cpufreq_policy *policy) ++{ ++#ifndef USE_FREQ_TABLE ++ struct clk *mpu_clk; ++#endif ++ ++ if (policy->cpu) ++ return -EINVAL; ++#ifdef USE_FREQ_TABLE ++ return cpufreq_frequency_table_verify(policy, s5pc100_freq_table); ++#else ++ cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, ++ policy->cpuinfo.max_freq); ++ mpu_clk = clk_get(NULL, MPU_CLK); ++ if (IS_ERR(mpu_clk)) ++ return PTR_ERR(mpu_clk); ++ ++ policy->min = clk_round_rate(mpu_clk, policy->min * KHZ_T) / KHZ_T; ++ policy->max = clk_round_rate(mpu_clk, policy->max * KHZ_T) / KHZ_T; ++ ++ cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, ++ policy->cpuinfo.max_freq); ++ ++ clk_put(mpu_clk); ++ ++ return 0; ++#endif ++} ++ ++unsigned int s5pc100_getspeed(unsigned int cpu) ++{ ++ struct clk * mpu_clk; ++ unsigned long rate; ++ ++ if (cpu) ++ return 0; ++ ++ mpu_clk = clk_get(NULL, MPU_CLK); ++ if (IS_ERR(mpu_clk)) ++ return 0; ++ rate = clk_get_rate(mpu_clk) / KHZ_T; ++ ++ clk_put(mpu_clk); ++ ++ return rate; ++} ++ ++static int s5pc100_target(struct cpufreq_policy *policy, ++ unsigned int target_freq, ++ unsigned int relation) ++{ ++ struct clk * mpu_clk; ++ struct cpufreq_freqs freqs; ++ int ret = 0; ++ unsigned long arm_clk; ++ unsigned int index; ++ ++ mpu_clk = clk_get(NULL, MPU_CLK); ++ if (IS_ERR(mpu_clk)) ++ return PTR_ERR(mpu_clk); ++ ++ freqs.old = s5pc100_getspeed(0); ++#ifdef USE_FREQ_TABLE ++ if (cpufreq_frequency_table_target(policy, s5pc100_freq_table, target_freq, relation, &index)) ++ return -EINVAL; ++ ++ arm_clk = s5pc100_freq_table[index].frequency; ++ ++ freqs.new = arm_clk; ++#else ++ freqs.new = clk_round_rate(mpu_clk, target_freq * KHZ_T) / KHZ_T; ++#endif ++ freqs.cpu = 0; ++ ++ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); ++#ifdef USE_DVS ++ if(freqs.new < freqs.old){ ++ /* frequency scaling */ ++ ret = clk_set_rate(mpu_clk, target_freq * KHZ_T); ++ if(ret != 0) ++ printk("frequency scaling error\n"); ++ /* voltage scaling */ ++ set_power(freqs.new); ++ }else{ ++ /* voltage scaling */ ++ set_power(freqs.new); ++ ++ /* frequency scaling */ ++ ret = clk_set_rate(mpu_clk, target_freq * KHZ_T); ++ if(ret != 0) ++ printk("frequency scaling error\n"); ++ } ++ ++ ++#else ++ if(freqs.new != freqs.old) { ++ ret = clk_set_rate(mpu_clk, target_freq * KHZ_T); ++ if(ret != 0) ++ printk("frequency scaling error\n"); ++ } ++ ++#endif ++ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); ++ clk_put(mpu_clk); ++ return ret; ++} ++ ++static int __init s5pc100_cpu_init(struct cpufreq_policy *policy) ++{ ++ struct clk * mpu_clk; ++ u32 reg; ++ ++#ifdef USE_DVS ++ ltc3714_init(); ++#endif ++ ++#ifdef CLK_OUT_PROBING ++ ++ reg = __raw_readl(S5P_CLK_OUT); ++ reg &=~(0x1f << 12 | 0xf << 20); // Mask Out CLKSEL bit field and DIVVAL ++ reg |= (0x9 << 12 | 0x1 << 20); // CLKSEL = ARMCLK/4, DIVVAL = 1 ++ __raw_writel(reg, S5P_CLK_OUT); ++#endif ++ mpu_clk = clk_get(NULL, MPU_CLK); ++ if (IS_ERR(mpu_clk)) ++ return PTR_ERR(mpu_clk); ++ ++ if (policy->cpu != 0) ++ return -EINVAL; ++ policy->cur = policy->min = policy->max = s5pc100_getspeed(0); ++#ifdef USE_FREQ_TABLE ++ cpufreq_frequency_table_get_attr(s5pc100_freq_table, policy->cpu); ++#else ++ policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / KHZ_T; ++ policy->cpuinfo.max_freq = clk_round_rate(mpu_clk, VERY_HI_RATE) / KHZ_T; ++#endif ++ policy->cpuinfo.transition_latency = 40000; //1us ++ ++ ++ clk_put(mpu_clk); ++#ifdef USE_FREQ_TABLE ++ return cpufreq_frequency_table_cpuinfo(policy, s5pc100_freq_table); ++#else ++ return 0; ++#endif ++} ++ ++static struct cpufreq_driver s5pc100_driver = { ++ .flags = CPUFREQ_STICKY, ++ .verify = s5pc100_verify_speed, ++ .target = s5pc100_target, ++ .get = s5pc100_getspeed, ++ .init = s5pc100_cpu_init, ++ .name = "s5pc100", ++}; ++ ++static int __init s5pc100_cpufreq_init(void) ++{ ++ return cpufreq_register_driver(&s5pc100_driver); ++} ++ ++arch_initcall(s5pc100_cpufreq_init); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/s5pc1xx-time.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/s5pc1xx-time.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/s5pc1xx-time.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/s5pc1xx-time.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,314 @@ ++/* linux/arch/arm/plat-s5pc1xx/s5pc1xx-time.c ++ * ++ * Copyright (C) 2003-2005 Simtec Electronics ++ * Jongpill Lee, ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * This code is based on plat-s3c/time.c ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++static unsigned long timer_startval; ++static unsigned long timer_usec_ticks; ++ ++#ifndef TICK_MAX ++#define TICK_MAX (0xffff) ++#endif ++ ++//#define T32_DEBUG_GPD ++//#define CLK_OUT_PROBING ++ ++#define TIMER_USEC_SHIFT 16 ++ ++static unsigned int s5pc1xx_systimer_read(unsigned int *reg_offset) ++{ ++ return __raw_readl(reg_offset); ++} ++ ++static unsigned int s5pc1xx_systimer_write(unsigned int *reg_offset, unsigned int value) ++{ ++ unsigned int temp_regs; ++ ++ __raw_writel(value, reg_offset); ++ ++ if (reg_offset == S3C_SYSTIMER_TCON) { ++ while(!(__raw_readl(S3C_SYSTIMER_INT_CSTAT) & S3C_SYSTIMER_INT_TCON)); ++ temp_regs = __raw_readl(S3C_SYSTIMER_INT_CSTAT); ++ temp_regs |= S3C_SYSTIMER_INT_TCON; ++ __raw_writel(temp_regs, S3C_SYSTIMER_INT_CSTAT); ++ ++ } else if (reg_offset == S3C_SYSTIMER_ICNTB) { ++ while(!(__raw_readl(S3C_SYSTIMER_INT_CSTAT) & S3C_SYSTIMER_INT_ICNTB)); ++ temp_regs = __raw_readl(S3C_SYSTIMER_INT_CSTAT); ++ temp_regs |= S3C_SYSTIMER_INT_ICNTB; ++ __raw_writel(temp_regs, S3C_SYSTIMER_INT_CSTAT); ++ ++ } else if (reg_offset == S3C_SYSTIMER_TCNTB) { ++ while(!(__raw_readl(S3C_SYSTIMER_INT_CSTAT) & S3C_SYSTIMER_INT_TCNTB)); ++ temp_regs = __raw_readl(S3C_SYSTIMER_INT_CSTAT); ++ temp_regs |= S3C_SYSTIMER_INT_TCNTB; ++ __raw_writel(temp_regs, S3C_SYSTIMER_INT_CSTAT); ++ } ++ ++ return 0; ++} ++ ++/* ++ * S5PC1XX has system timer to use as OS tick Timer. ++ * System Timer provides two distincive feature. Accurate timer which provides ++ * exact 1ms time tick at any power mode except sleep mode. Second one is chageable ++ * interrupt interval without stopping reference tick timer. ++ */ ++ ++/* ++ * timer_mask_usec_ticks ++ * ++ * given a clock and divisor, make the value to pass into timer_ticks_to_usec ++ * to scale the ticks into usecs ++ */ ++static inline unsigned long timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk) ++{ ++ unsigned long den = pclk / 1000; ++ ++ return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den; ++} ++ ++/* ++ * timer_ticks_to_usec ++ * ++ * convert timer ticks to usec. ++ */ ++static inline unsigned long timer_ticks_to_usec(unsigned long ticks) ++{ ++ unsigned long res; ++ ++ res = ticks * timer_usec_ticks; ++ res += 1 << (TIMER_USEC_SHIFT - 4); /* round up slightly */ ++ ++ return res >> TIMER_USEC_SHIFT; ++} ++ ++/* ++ * Returns microsecond since last clock interrupt. Note that interrupts ++ * will have been disabled by do_gettimeoffset() ++ * IRQs are disabled before entering here from do_gettimeofday() ++ */ ++static unsigned long s5pc1xx_gettimeoffset (void) ++{ ++ unsigned long tdone; ++ unsigned long tval; ++ ++ /* work out how many ticks have gone since last timer interrupt */ ++ tval = s5pc1xx_systimer_read(S3C_SYSTIMER_TCNTO); ++ tdone = timer_startval - tval; ++ ++ /* check to see if there is an interrupt pending */ ++ if (s5pc1xx_ostimer_pending()) { ++ /* re-read the timer, and try and fix up for the missed ++ * interrupt. Note, the interrupt may go off before the ++ * timer has re-loaded from wrapping. ++ */ ++ ++ tval = s5pc1xx_systimer_read(S3C_SYSTIMER_TCNTO); ++ tdone = timer_startval - tval; ++ ++ if (tval != 0) ++ tdone += timer_startval; ++ } ++ ++ return timer_ticks_to_usec(tdone); ++} ++ ++ ++/* ++ * IRQ handler for the timer ++ */ ++static irqreturn_t s5pc1xx_timer_interrupt(int irq, void *dev_id) ++{ ++ volatile unsigned int temp_cstat; ++ ++ temp_cstat = s5pc1xx_systimer_read(S3C_SYSTIMER_INT_CSTAT); ++ temp_cstat |= S3C_SYSTIMER_INT_STATS; ++ ++ s5pc1xx_systimer_write(S3C_SYSTIMER_INT_CSTAT, temp_cstat); ++#ifdef T32_DEBUG_GPD ++ u32 tmp; ++ tmp = __raw_readl(S5PC1XX_GPDDAT); ++ tmp |= (0x1<<1); ++ __raw_writel(tmp, S5PC1XX_GPDDAT); ++ ++#endif ++ ++#if 0 ++ do { ++ if(!(s5pc1xx_systimer_read(S3C_SYSTIMER_INT_CSTAT) & S3C_SYSTIMER_INT_STATS)) ++ break; ++ } while(1); ++#endif ++ ++#ifdef T32_DEBUG_GPD ++ tmp = __raw_readl(S5PC1XX_GPDDAT); ++ tmp &=~(0x1<<1); ++ __raw_writel(tmp, S5PC1XX_GPDDAT); ++ ++#endif ++ timer_tick(); ++ ++ return IRQ_HANDLED; ++} ++ ++static struct irqaction s5pc1xx_timer_irq = { ++ .name = "S5PC1XX System Timer", ++ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, ++ .handler = s5pc1xx_timer_interrupt, ++}; ++ ++/* ++ * Set up timer interrupt, and return the current time in seconds. ++ * ++ */ ++static void s5pc1xx_timer_setup (void) ++{ ++ unsigned long tcon; ++ unsigned long tcnt; ++ unsigned long tcfg; ++ unsigned long icntb; ++ ++ /* clock configuration setting and enable */ ++ unsigned long pclk; ++ struct clk *clk; ++ ++ unsigned long reg; ++ ++#ifdef T32_DEBUG_GPD ++ reg = __raw_readl(S5PC1XX_GPDCON); ++ reg &=~(0xf << 4); ++ reg |= (0x1 << 4); ++ __raw_writel(reg, S5PC1XX_GPDCON); ++ ++ reg = __raw_readl(S5PC1XX_GPDDAT); ++ reg &=~(0x1<<1); ++ __raw_writel(reg, S5PC1XX_GPDDAT); ++ ++#endif ++ ++#ifdef CLK_OUT_PROBING ++ reg = __raw_readl(S5P_CLK_OUT); ++ reg &=~(0x1f<<12); ++ reg |= (0x6<<12); ++ __raw_writel(reg, S5P_CLK_OUT); ++#endif ++ ++ tcnt = TICK_MAX; /* default value for tcnt */ ++ ++ /* initialize system timer clock */ ++ tcfg = s5pc1xx_systimer_read(S3C_SYSTIMER_TCFG); ++ ++ tcfg &= ~S3C_SYSTIMER_TCLK_MASK; ++ tcfg |= S3C_SYSTIMER_TCLK_PCLK; ++ ++ s5pc1xx_systimer_write(S3C_SYSTIMER_TCFG, tcfg); ++ ++ /* TCFG must not be changed at run-time. If you want to change TCFG, stop timer(TCON[0] = 0) */ ++ s5pc1xx_systimer_write(S3C_SYSTIMER_TCON, 0); ++ ++ /* read the current timer configuration bits */ ++ tcon = s5pc1xx_systimer_read(S3C_SYSTIMER_TCON); ++ tcfg = s5pc1xx_systimer_read(S3C_SYSTIMER_TCFG); ++ icntb = s5pc1xx_systimer_read(S3C_SYSTIMER_ICNTB); ++ ++ clk = clk_get(NULL, "systimer"); ++ if (IS_ERR(clk)) ++ panic("failed to get clock for system timer"); ++ ++ clk_enable(clk); ++ ++ pclk = clk_get_rate(clk); ++ ++ /* configure clock tick */ ++ timer_usec_ticks = timer_mask_usec_ticks(S3C_SYSTIMER_PRESCALER, pclk); ++ ++ tcfg &= ~S3C_SYSTIMER_TCLK_MASK; ++ tcfg |= S3C_SYSTIMER_TCLK_PCLK; ++ tcfg &= ~S3C_SYSTIMER_PRESCALER_MASK; ++ tcfg |= S3C_SYSTIMER_PRESCALER - 1; ++ ++ tcnt = ((pclk / S3C_SYSTIMER_PRESCALER) / S3C_SYSTIMER_TARGET_HZ) - 1; ++ ++ /* check to see if timer is within 16bit range... */ ++ if (tcnt > TICK_MAX) { ++ panic("setup_timer: HZ is too small, cannot configure timer!"); ++ return; ++ } ++ ++ s5pc1xx_systimer_write(S3C_SYSTIMER_TCFG, tcfg); ++ ++ timer_startval = tcnt; ++ s5pc1xx_systimer_write(S3C_SYSTIMER_TCNTB, tcnt); ++ ++ /* set Interrupt tick value */ ++ icntb = (S3C_SYSTIMER_TARGET_HZ / HZ) - 1; ++ s5pc1xx_systimer_write(S3C_SYSTIMER_ICNTB, icntb); ++ ++ tcon = S3C_SYSTIMER_INT_AUTO | S3C_SYTIMERS_START | S3C_SYSTIMER_INT_START | S3C_SYSTIMER_AUTO_RELOAD; ++ s5pc1xx_systimer_write(S3C_SYSTIMER_TCON, tcon); ++ ++ printk("timer tcon=%08lx, tcnt %04lx, icnt %04lx, tcfg %08lx, usec %08lx\n", ++ tcon, tcnt, icntb, tcfg, timer_usec_ticks); ++ ++ /* Interrupt Start and Enable */ ++ s5pc1xx_systimer_write(S3C_SYSTIMER_INT_CSTAT, (S3C_SYSTIMER_INT_ICNTEIE)); ++} ++ ++static void __init s5pc1xx_timer_init(void) ++{ ++ s5pc1xx_timer_setup(); ++ setup_irq(IRQ_SYSTIMER, &s5pc1xx_timer_irq); ++} ++ ++struct sys_timer s5pc1xx_timer = { ++ .init = s5pc1xx_timer_init, ++ .offset = s5pc1xx_gettimeoffset, ++ .resume = s5pc1xx_timer_setup ++}; ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/setup-csis.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/setup-csis.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/setup-csis.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/setup-csis.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,47 @@ ++/* linux/arch/arm/plat-s5pc1xx/setup-csis.c ++ * ++ * Copyright 2009 Samsung Electronics ++ * Jinsung Yang ++ * http://samsungsemi.com/ ++ * ++ * Base S5PC1XX MIPI-CSI2 gpio configuration ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++ ++struct platform_device; /* don't need the contents */ ++ ++void s3c_csis_cfg_gpio(struct platform_device *dev) ++{ ++ return; ++} ++ ++void s3c_csis_cfg_phy_global(struct platform_device *dev, int on) ++{ ++ u32 cfg; ++ ++ if (on) { ++ /* MIPI Power Enable */ ++ cfg = __raw_readl(S5P_OTHERS); ++ cfg |= S5P_OTHERS_MIPI_DPHY_EN; ++ __raw_writel(cfg, S5P_OTHERS); ++ ++ /* MIPI CSIS Part Reset */ ++ cfg = __raw_readl(S5P_MIPI_PHY_CON0); ++ cfg |= S5P_MIPI_PHY_CON0_S_RESETN; ++ __raw_writel(cfg, S5P_MIPI_PHY_CON0); ++ } else { ++ /* MIPI Power Disable */ ++ cfg = __raw_readl(S5P_OTHERS); ++ cfg &= ~S5P_OTHERS_MIPI_DPHY_EN; ++ __raw_writel(cfg, S5P_OTHERS); ++ } ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/setup-fimc0.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/setup-fimc0.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/setup-fimc0.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/setup-fimc0.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,69 @@ ++/* linux/arch/arm/plat-s5pc1xx/setup-fimc0.c ++ * ++ * Copyright 2009 Samsung Electronics ++ * Jinsung Yang ++ * http://samsungsemi.com/ ++ * ++ * Base S5PC1XX FIMC controller 0 gpio configuration ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct platform_device; /* don't need the contents */ ++ ++void s3c_fimc0_cfg_gpio(struct platform_device *dev) ++{ ++ int i; ++ ++ s3c_gpio_cfgpin(S5PC1XX_GPE0(0), S5PC1XX_GPE0_0_CAM_A_PCLK); ++ s3c_gpio_cfgpin(S5PC1XX_GPE0(1), S5PC1XX_GPE0_1_CAM_A_VSYNC); ++ s3c_gpio_cfgpin(S5PC1XX_GPE0(2), S5PC1XX_GPE0_2_CAM_A_HREF); ++ s3c_gpio_cfgpin(S5PC1XX_GPE0(3), S5PC1XX_GPE0_3_CAM_A_DATA_0); ++ s3c_gpio_cfgpin(S5PC1XX_GPE0(4), S5PC1XX_GPE0_4_CAM_A_DATA_1); ++ s3c_gpio_cfgpin(S5PC1XX_GPE0(5), S5PC1XX_GPE0_5_CAM_A_DATA_2); ++ s3c_gpio_cfgpin(S5PC1XX_GPE0(6), S5PC1XX_GPE0_6_CAM_A_DATA_3); ++ s3c_gpio_cfgpin(S5PC1XX_GPE0(7), S5PC1XX_GPE0_7_CAM_A_DATA_4); ++ s3c_gpio_cfgpin(S5PC1XX_GPE1(0), S5PC1XX_GPE1_0_CAM_A_DATA_5); ++ s3c_gpio_cfgpin(S5PC1XX_GPE1(1), S5PC1XX_GPE1_1_CAM_A_DATA_6); ++ s3c_gpio_cfgpin(S5PC1XX_GPE1(2), S5PC1XX_GPE1_2_CAM_A_DATA_7); ++ s3c_gpio_cfgpin(S5PC1XX_GPE1(3), S5PC1XX_GPE1_3_CAM_A_CLKOUT); ++ s3c_gpio_cfgpin(S5PC1XX_GPE1(4), S5PC1XX_GPE1_4_CAM_A_RESET); ++ s3c_gpio_cfgpin(S5PC1XX_GPE1(5), S5PC1XX_GPE1_5_CAM_A_FIELD); ++ ++ for (i = 0; i < 8; i++) ++ s3c_gpio_setpull(S5PC1XX_GPE0(i), S3C_GPIO_PULL_UP); ++ ++ for (i = 0; i < 6; i++) ++ s3c_gpio_setpull(S5PC1XX_GPE1(i), S3C_GPIO_PULL_UP); ++ ++ s3c_gpio_cfgpin(S5PC1XX_GPH2(0), S5PC1XX_GPH2_0_CAM_B_DATA_0); ++ s3c_gpio_cfgpin(S5PC1XX_GPH2(1), S5PC1XX_GPH2_1_CAM_B_DATA_1); ++ s3c_gpio_cfgpin(S5PC1XX_GPH2(2), S5PC1XX_GPH2_2_CAM_B_DATA_2); ++ s3c_gpio_cfgpin(S5PC1XX_GPH2(3), S5PC1XX_GPH2_3_CAM_B_DATA_3); ++ s3c_gpio_cfgpin(S5PC1XX_GPH2(4), S5PC1XX_GPH2_4_CAM_B_DATA_4); ++ s3c_gpio_cfgpin(S5PC1XX_GPH2(5), S5PC1XX_GPH2_5_CAM_B_DATA_5); ++ s3c_gpio_cfgpin(S5PC1XX_GPH2(6), S5PC1XX_GPH2_6_CAM_B_DATA_6); ++ s3c_gpio_cfgpin(S5PC1XX_GPH2(7), S5PC1XX_GPH2_7_CAM_B_DATA_7); ++ s3c_gpio_cfgpin(S5PC1XX_GPH3(0), S5PC1XX_GPH3_0_CAM_B_PCLK); ++ s3c_gpio_cfgpin(S5PC1XX_GPH3(1), S5PC1XX_GPH3_1_CAM_B_VSYNC); ++ s3c_gpio_cfgpin(S5PC1XX_GPH3(2), S5PC1XX_GPH3_2_CAM_B_HREF); ++ s3c_gpio_cfgpin(S5PC1XX_GPH3(3), S5PC1XX_GPH3_3_CAM_B_FIELD); ++ s3c_gpio_cfgpin(S5PC1XX_GPE1(3), S5PC1XX_GPE1_3_CAM_A_CLKOUT); ++ ++ for (i = 0; i < 8; i++) ++ s3c_gpio_setpull(S5PC1XX_GPH2(i), S3C_GPIO_PULL_UP); ++ ++ for (i = 0; i < 4; i++) ++ s3c_gpio_setpull(S5PC1XX_GPH3(i), S3C_GPIO_PULL_UP); ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/setup-fimc1.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/setup-fimc1.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/setup-fimc1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/setup-fimc1.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,22 @@ ++/* linux/arch/arm/plat-s5pc1xx/setup-fimc1.c ++ * ++ * Copyright 2009 Samsung Electronics ++ * Jinsung Yang ++ * http://samsungsemi.com/ ++ * ++ * Base S5PC1XX FIMC controller 1 gpio configuration ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++ ++struct platform_device; /* don't need the contents */ ++ ++#include ++#include ++ ++void s3c_fimc1_cfg_gpio(struct platform_device *dev) { } +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/setup-fimc2.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/setup-fimc2.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/setup-fimc2.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/setup-fimc2.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,22 @@ ++/* linux/arch/arm/plat-s5pc1xx/setup-fimc2.c ++ * ++ * Copyright 2009 Samsung Electronics ++ * Jinsung Yang ++ * http://samsungsemi.com/ ++ * ++ * Base S5PC1XX FIMC controller 2 gpio configuration ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++ ++struct platform_device; /* don't need the contents */ ++ ++#include ++#include ++ ++void s3c_fimc2_cfg_gpio(struct platform_device *dev) { } +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/setup-fimd.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/setup-fimd.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/setup-fimd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/setup-fimd.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,87 @@ ++/* linux/arch/arm/plat-s5pc1xx/setup-fimd.c ++ * ++ * Copyright 2009 Samsung Electronics ++ * Jinsung Yang ++ * http://samsungsemi.com/ ++ * ++ * Base S5PC1XX FIMD gpio configuration ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++ ++struct platform_device; /* don't need the contents */ ++ ++void s3c_fimd_cfg_gpio(struct platform_device *dev) ++{ ++ int i; ++ ++ for (i = 0; i < 8; i++) ++ s3c_gpio_cfgpin(S5PC1XX_GPF0(i), S3C_GPIO_SFN(2)); ++ ++ for (i = 0; i < 8; i++) ++ s3c_gpio_cfgpin(S5PC1XX_GPF1(i), S3C_GPIO_SFN(2)); ++ ++ for (i = 0; i < 8; i++) ++ s3c_gpio_cfgpin(S5PC1XX_GPF2(i), S3C_GPIO_SFN(2)); ++ ++ for (i = 0; i < 4; i++) ++ s3c_gpio_cfgpin(S5PC1XX_GPF3(i), S3C_GPIO_SFN(2)); ++} ++ ++int s3c_fimd_backlight_on(struct platform_device *dev) ++{ ++ int err; ++ ++ if (gpio_is_valid(S5PC1XX_GPD(0))) { ++ err = gpio_request(S5PC1XX_GPD(0), "GPD"); ++ ++ if (err) { ++ printk(KERN_ERR "failed to request GPD for " ++ "lcd backlight control\n"); ++ return err; ++ } ++ ++ gpio_direction_output(S5PC1XX_GPD(0), 1); ++ } ++ ++ return 0; ++} ++ ++int s3c_fimd_reset_lcd(struct platform_device *dev) ++{ ++ int err; ++ ++ if (gpio_is_valid(S5PC1XX_GPH0(6))) { ++ err = gpio_request(S5PC1XX_GPH0(6), "GPH0"); ++ ++ if (err) { ++ printk(KERN_ERR "failed to request GPH0 for " ++ "lcd reset control\n"); ++ return err; ++ } ++ ++ gpio_direction_output(S5PC1XX_GPH0(6), 1); ++ } ++ ++ mdelay(100); ++ ++ gpio_set_value(S5PC1XX_GPH0(6), 0); ++ mdelay(10); ++ ++ gpio_set_value(S5PC1XX_GPH0(6), 1); ++ mdelay(10); ++ ++ gpio_free(S5PC1XX_GPH0(6)); ++ gpio_free(S5PC1XX_GPD(0)); ++ ++ return 0; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/setup-i2c0.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/setup-i2c0.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/setup-i2c0.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/setup-i2c0.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,31 @@ ++/* linux/arch/arm/plat-s5pc1xx/setup-i2c0.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * Base S3C64XX I2C bus 0 gpio configuration ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++ ++struct platform_device; /* don't need the contents */ ++ ++#include ++#include ++#include ++#include ++ ++void s3c_i2c0_cfg_gpio(struct platform_device *dev) ++{ ++ s3c_gpio_cfgpin(S5PC1XX_GPD(3), S5PC1XX_GPD3_I2C0_SDA); ++ s3c_gpio_cfgpin(S5PC1XX_GPD(4), S5PC1XX_GPD4_I2C0_SCL); ++ s3c_gpio_setpull(S5PC1XX_GPD(3), S3C_GPIO_PULL_UP); ++ s3c_gpio_setpull(S5PC1XX_GPD(4), S3C_GPIO_PULL_UP); ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/setup-i2c1.c linux-2.6.28.6/arch/arm/plat-s5pc1xx/setup-i2c1.c +--- linux-2.6.28/arch/arm/plat-s5pc1xx/setup-i2c1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/setup-i2c1.c 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,31 @@ ++/* linux/arch/arm/plat-s5pc1xx/setup-i2c0.c ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * Base S5PC1XX I2C bus 0 gpio configuration ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++ ++struct platform_device; /* don't need the contents */ ++ ++#include ++#include ++#include ++#include ++ ++void s3c_i2c1_cfg_gpio(struct platform_device *dev) ++{ ++ s3c_gpio_cfgpin(S5PC1XX_GPD(5), S5PC1XX_GPD5_I2C1_SDA); ++ s3c_gpio_cfgpin(S5PC1XX_GPD(6), S5PC1XX_GPD6_I2C1_SCL); ++ s3c_gpio_setpull(S5PC1XX_GPD(5), S3C_GPIO_PULL_UP); ++ s3c_gpio_setpull(S5PC1XX_GPD(6), S3C_GPIO_PULL_UP); ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/plat-s5pc1xx/sleep.S linux-2.6.28.6/arch/arm/plat-s5pc1xx/sleep.S +--- linux-2.6.28/arch/arm/plat-s5pc1xx/sleep.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/plat-s5pc1xx/sleep.S 2009-04-30 09:36:37.000000000 +0200 +@@ -0,0 +1,245 @@ ++/* linux/arch/arm/plat-s3c64xx/sleep.S ++ * ++ * Copyright (c) 2004 Simtec Electronics ++ * Ben Dooks ++ * ++ * S3C6410 Power Manager (Suspend-To-RAM) support ++ * ++ * Based on PXA/SA1100 sleep code by: ++ * Nicolas Pitre, (c) 2002 Monta Vista Software Inc ++ * Cliff Brake, (c) 2001 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++*/ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#define S5P_INFORM0 0xE0108400 ++ ++/* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not ++ * reset the UART configuration, only enable if you really need this! ++*/ ++ .text ++ ++ /* s5pc100_cpu_save ++ * ++ * save enough of the CPU state to allow us to re-start ++ * pm.c code. as we store items like the sp/lr, we will ++ * end up returning from this function when the cpu resumes ++ * so the return value is set to mark this. ++ * ++ * This arangement means we avoid having to flush the cache ++ * from this code. ++ * ++ * entry: ++ * r0 = pointer to save block ++ * ++ * exit: ++ * r0 = 0 => we stored everything ++ * 1 => resumed from sleep ++ */ ++ ++ENTRY(s5pc100_cpu_save) ++#if 0 ++ stmfd sp!, { r4 - r12, lr } ++ ++ @@ store co-processor registers ++ ++ mrc p15, 0, r4, c13, c0, 0 @ Read FCSE PID ++ mrc p15, 0, r5, c3, c0, 0 @ Read Domain ID ++ mrc p15, 0, r6, c2, c0, 0 @ Read translation table base address ++ mrc p15, 0, r7, c1, c0, 0 @ Read control register ++ ++ stmia r0, { r4 - r13 } ++ ++ mov r0, #0 ++ ldmfd sp, { r4 - r12, pc } ++#else ++ stmfd sp!, { r3 - r12, lr } ++ ++ mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID ++ mrc p15, 0, r5, c3, c0, 0 @ Domain ID ++ mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 ++ mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 ++ mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control ++ mrc p15, 0, r9, c1, c0, 0 @ Control register ++ mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register ++ mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls ++ mrc p15, 0, r12, c10, c2, 0 @ Read PRRR ++ mrc p15, 0, r3, c10, c2, 1 @ READ NMRR ++ ++ stmia r0, { r3 - r13 } ++ ++ mov r0, #0 ++ ldmfd sp, { r3 - r12, pc } ++#endif ++ @@ return to the caller, after having the MMU ++ @@ turned on, this restores the last bits from the ++ @@ stack ++resume_with_mmu: ++ mov r0, #1 ++ ++ /* delete added mmu table list */ ++ ldr r9 ,=0xC0000000 ++ bic r8, r8, #0xF0000000 ++ orr r8, r8, r9 ++ str r12, [r8] ++#if 0 ++ ldmfd sp!, { r4 - r12, pc } ++#else ++ ldmfd sp!, { r3 - r12, pc } ++#endif ++ .ltorg ++ ++ @@ the next bits sit in the .data segment, even though they ++ @@ happen to be code... the s5pc100_sleep_save_phys needs to be ++ @@ accessed by the resume code before it can restore the MMU. ++ @@ This means that the variable has to be close enough for the ++ @@ code to read it... since the .text segment needs to be RO, ++ @@ the data segment can be the only place to put this code. ++ ++ .data ++ ++ .global s5pc100_sleep_save_phys ++s5pc100_sleep_save_phys: ++ .word 0 ++ ++ ++ /* sleep magic, to allow the bootloader to check for an valid ++ * image to resume to. Must be the first word before the ++ * s5pc100_cpu_resume entry. ++ */ ++ ++ .word 0x2bedf00d ++ ++ /* s5pc100_cpu_resume ++ * ++ * resume code entry for bootloader to call ++ * ++ * we must put this code here in the data segment as we have no ++ * other way of restoring the stack pointer after sleep, and we ++ * must not write to the code segment (code is read-only) ++ */ ++ ++ENTRY(s5pc100_cpu_resume) ++ mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE ++ msr cpsr_c, r0 ++ ++ @@ load UART to allow us to print the two characters for ++ @@ resume debug ++ ++ mov r1, #0 ++ mcr p15, 0, r1, c8, c7, 0 @@ invalidate TLBs ++ mcr p15, 0, r1, c7, c5, 0 @@ invalidate I Cache ++ ++ ldr r0, s5pc100_sleep_save_phys @ address of restore block ++#if 0 ++ ++ ldmia r0, { r4 - r13 } ++ mcr p15, 0, r4, c13, c0, 0 @ PID ++ mcr p15, 0, r5, c3, c0, 0 @ Domain ID ++ mcr p15, 0, r6, c2, c0, 0 @ translation table base ++ ++ /* calculate first section address into r8 */ ++ mov r8, r6 ++ ldr r10, =0x3fff ++ bic r8, r8, r10 ++ ldr r11, =S5P_INFORM0 ++ ldr r9, [r11, #0] ++ mov r9, r9 ,LSR #18 ++ bic r9, r9, #0x3 ++ orr r8, r8, r9 ++ ++ /* calculate mmu list value into r9 */ ++ mov r9, r9, LSL #18 ++ ldr r10, =0x40e ++ orr r9, r9, r10 ++ ++ /* back up originally data */ ++ ++ ldr r12, [r8] ++ ++ /* Added list about mmu */ ++ str r9, [r8] ++ ++ ldr r2, =resume_with_mmu ++ mcr p15, 0, r7, c1, c0, 0 @ turn on MMU, etc ++ nop @ second-to-last before mmu ++ mov pc, r2 @ go back to virtual address ++#else ++ ldmia r0, { r3 - r13 } ++ ++ mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID ++ mcr p15, 0, r5, c3, c0, 0 @ Domain ID ++ ++ mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control ++ mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1 ++ mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0 ++ ++ mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register ++ ++ mov r0, #0 ++ mcr p15, 0, r0, c8, c7, 0 @ Invalidate I & D TLB ++ ++ mov r0, #0 @ restore copro access controls ++ mcr p15, 0, r11, c1, c0, 2 @ Co-processor access controls ++ mcr p15, 0, r0, c7, c5, 4 ++ ++ mcr p15, 0, r12, c10, c2, 0 @ write PRRR ++ mcr p15, 0, r3, c10, c2, 1 @ write NMRR ++ ++ /* calculate first section address into r8 */ ++ mov r4, r6 ++ ldr r5, =0x3fff ++ bic r4, r4, r5 ++ ldr r11, =S5P_INFORM0 ++ ldr r10, [r11, #0] ++ mov r10, r10 ,LSR #18 ++ bic r10, r10, #0x3 ++ orr r4, r4, r10 ++ ++ /* calculate mmu list value into r9 */ ++ mov r10, r10, LSL #18 ++ ldr r5, =0x40e ++ orr r10, r10, r5 ++ ++ /* back up originally data */ ++ ++ ldr r12, [r4] ++ ++ /* Added list about mmu */ ++ str r10, [r4] ++ ++ ldr r2, =resume_with_mmu ++ mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, etc ++ ++ nop ++ nop ++ nop ++ nop ++ nop @ second-to-last before mmu ++ ++ mov pc, r2 @ go back to virtual address ++ b . ++#endif ++ .ltorg +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/arch/arm/tools/mach-types linux-2.6.28.6/arch/arm/tools/mach-types +--- linux-2.6.28/arch/arm/tools/mach-types 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/arch/arm/tools/mach-types 2010-04-15 08:33:43.000000000 +0200 +@@ -12,7 +12,7 @@ + # + # http://www.arm.linux.org.uk/developer/machines/?action=new + # +-# Last update: Thu Sep 25 10:10:50 2008 ++# Last update: Wed Nov 25 22:14:58 2009 + # + # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number + # +@@ -916,7 +916,7 @@ + apf9328 MACH_APF9328 APF9328 906 + omap_wipoq MACH_OMAP_WIPOQ OMAP_WIPOQ 907 + omap_twip MACH_OMAP_TWIP OMAP_TWIP 908 +-palmt650 MACH_PALMT650 PALMT650 909 ++treo650 MACH_TREO650 TREO650 909 + acumen MACH_ACUMEN ACUMEN 910 + xp100 MACH_XP100 XP100 911 + fs2410 MACH_FS2410 FS2410 912 +@@ -928,7 +928,7 @@ + palmtc MACH_PALMTC PALMTC 918 + omap_apollon MACH_OMAP_APOLLON OMAP_APOLLON 919 + mxc30030evb MACH_MXC30030EVB MXC30030EVB 920 +-rea_2d MACH_REA_2D REA_2D 921 ++rea_cpu2 MACH_REA_2D REA_2D 921 + eti3e524 MACH_TI3E524 TI3E524 922 + ateb9200 MACH_ATEB9200 ATEB9200 923 + auckland MACH_AUCKLAND AUCKLAND 924 +@@ -1232,7 +1232,7 @@ + vpac270 MACH_VPAC270 VPAC270 1227 + rd129 MACH_RD129 RD129 1228 + htcwizard MACH_HTCWIZARD HTCWIZARD 1229 +-xscale_treo680 MACH_XSCALE_TREO680 XSCALE_TREO680 1230 ++treo680 MACH_TREO680 TREO680 1230 + tecon_tmezon MACH_TECON_TMEZON TECON_TMEZON 1231 + zylonite MACH_ZYLONITE ZYLONITE 1233 + gene1270 MACH_GENE1270 GENE1270 1234 +@@ -1380,7 +1380,7 @@ + olip8 MACH_OLIP8 OLIP8 1378 + ghi270hg MACH_GHI270HG GHI270HG 1379 + davinci_dm6467_evm MACH_DAVINCI_DM6467_EVM DAVINCI_DM6467_EVM 1380 +-davinci_dm355_evm MACH_DAVINCI_DM350_EVM DAVINCI_DM350_EVM 1381 ++davinci_dm355_evm MACH_DAVINCI_DM355_EVM DAVINCI_DM355_EVM 1381 + blackriver MACH_BLACKRIVER BLACKRIVER 1383 + sandgate_wp MACH_SANDGATEWP SANDGATEWP 1384 + cdotbwsg MACH_CDOTBWSG CDOTBWSG 1385 +@@ -1418,10 +1418,10 @@ + cnty_titan MACH_CNTY_TITAN CNTY_TITAN 1418 + app3xx MACH_APP3XX APP3XX 1419 + sideoatsgrama MACH_SIDEOATSGRAMA SIDEOATSGRAMA 1420 +-palmtreo700p MACH_PALMTREO700P PALMTREO700P 1421 +-palmtreo700w MACH_PALMTREO700W PALMTREO700W 1422 +-palmtreo750 MACH_PALMTREO750 PALMTREO750 1423 +-palmtreo755p MACH_PALMTREO755P PALMTREO755P 1424 ++treo700p MACH_TREO700P TREO700P 1421 ++treo700w MACH_TREO700W TREO700W 1422 ++treo750 MACH_TREO750 TREO750 1423 ++treo755p MACH_TREO755P TREO755P 1424 + ezreganut9200 MACH_EZREGANUT9200 EZREGANUT9200 1425 + sarge MACH_SARGE SARGE 1426 + a696 MACH_A696 A696 1427 +@@ -1455,7 +1455,7 @@ + h6044 MACH_H6044 H6044 1458 + app MACH_APP APP 1459 + tct_hammer MACH_TCT_HAMMER TCT_HAMMER 1460 +-herald MACH_HERMES HERMES 1461 ++herald MACH_HERALD HERALD 1461 + artemis MACH_ARTEMIS ARTEMIS 1462 + htctitan MACH_HTCTITAN HTCTITAN 1463 + qranium MACH_QRANIUM QRANIUM 1464 +@@ -1638,7 +1638,7 @@ + aml_m8050 MACH_AML_M8050 AML_M8050 1644 + mx35_3ds MACH_MX35_3DS MX35_3DS 1645 + mars MACH_MARS MARS 1646 +-ntosd_644xa MACH_NTOSD_644XA NTOSD_644XA 1647 ++neuros_osd2 MACH_NEUROS_OSD2 NEUROS_OSD2 1647 + badger MACH_BADGER BADGER 1648 + trizeps4wl MACH_TRIZEPS4WL TRIZEPS4WL 1649 + trizeps5 MACH_TRIZEPS5 TRIZEPS5 1650 +@@ -1654,7 +1654,7 @@ + zoran43xx MACH_ZORAN43XX ZORAN43XX 1660 + sonix926 MACH_SONIX926 SONIX926 1661 + celestialsemi MACH_CELESTIALSEMI CELESTIALSEMI 1662 +-cc9m2443 MACH_CC9M2443 CC9M2443 1663 ++cc9m2443js MACH_CC9M2443JS CC9M2443JS 1663 + tw5334 MACH_TW5334 TW5334 1664 + omap_htcartemis MACH_HTCARTEMIS HTCARTEMIS 1665 + nal_hlite MACH_NAL_HLITE NAL_HLITE 1666 +@@ -1721,7 +1721,7 @@ + csb637xo MACH_CSB637XO CSB637XO 1730 + evisiong MACH_EVISIONG EVISIONG 1731 + stmp37xx MACH_STMP37XX STMP37XX 1732 +-stmp378x MACH_STMP38XX STMP38XX 1733 ++stmp378x MACH_STMP378X STMP378X 1733 + tnt MACH_TNT TNT 1734 + tbxt MACH_TBXT TBXT 1735 + playmate MACH_PLAYMATE PLAYMATE 1736 +@@ -1769,9 +1769,9 @@ + mi424wr MACH_MI424WR MI424WR 1778 + axs_ultrax MACH_AXS_ULTRAX AXS_ULTRAX 1779 + at572d940deb MACH_AT572D940DEB AT572D940DEB 1780 +-davinci_da8xx_evm MACH_DAVINCI_DA8XX_EVM DAVINCI_DA8XX_EVM 1781 ++davinci_da830_evm MACH_DAVINCI_DA830_EVM DAVINCI_DA830_EVM 1781 + ep9302 MACH_EP9302 EP9302 1782 +-at572d940hfeb MACH_AT572D940HFEB AT572D940HFEB 1783 ++at572d940hfek MACH_AT572D940HFEB AT572D940HFEB 1783 + cybook3 MACH_CYBOOK3 CYBOOK3 1784 + wdg002 MACH_WDG002 WDG002 1785 + sg560adsl MACH_SG560ADSL SG560ADSL 1786 +@@ -1802,7 +1802,7 @@ + rd88f5181l_ge MACH_RD88F5181L_GE RD88F5181L_GE 1812 + sifmain MACH_SIFMAIN SIFMAIN 1813 + sam9_l9261 MACH_SAM9_L9261 SAM9_L9261 1814 +-cc9m2443js MACH_CC9M2443JS CC9M2443JS 1815 ++cc9m2443 MACH_CC9M2443 CC9M2443 1815 + xaria300 MACH_XARIA300 XARIA300 1816 + it9200 MACH_IT9200 IT9200 1817 + rd88f5181l_fxo MACH_RD88F5181L_FXO RD88F5181L_FXO 1818 +@@ -1811,13 +1811,13 @@ + jade MACH_JADE JADE 1821 + ks8695_softplc MACH_KS8695_SOFTPLC KS8695_SOFTPLC 1822 + gprisc3 MACH_GPRISC3 GPRISC3 1823 +-stamp9260 MACH_STAMP9260 STAMP9260 1824 ++stamp9g20 MACH_STAMP9G20 STAMP9G20 1824 + smdk6430 MACH_SMDK6430 SMDK6430 1825 + smdkc100 MACH_SMDKC100 SMDKC100 1826 + tavorevb MACH_TAVOREVB TAVOREVB 1827 + saar MACH_SAAR SAAR 1828 + deister_eyecam MACH_DEISTER_EYECAM DEISTER_EYECAM 1829 +-at91sam9m10ek MACH_AT91SAM9M10EK AT91SAM9M10EK 1830 ++at91sam9m10g45ek MACH_AT91SAM9M10G45EK AT91SAM9M10G45EK 1830 + linkstation_produo MACH_LINKSTATION_PRODUO LINKSTATION_PRODUO 1831 + hit_b0 MACH_HIT_B0 HIT_B0 1832 + adx_rmu MACH_ADX_RMU ADX_RMU 1833 +@@ -1899,3 +1899,640 @@ + asusp535 MACH_ASUSP535 ASUSP535 1909 + htcraphael MACH_HTCRAPHAEL HTCRAPHAEL 1910 + sygdg1 MACH_SYGDG1 SYGDG1 1911 ++sygdg2 MACH_SYGDG2 SYGDG2 1912 ++seoul MACH_SEOUL SEOUL 1913 ++salerno MACH_SALERNO SALERNO 1914 ++ucn_s3c64xx MACH_UCN_S3C64XX UCN_S3C64XX 1915 ++msm7201a MACH_MSM7201A MSM7201A 1916 ++lpr1 MACH_LPR1 LPR1 1917 ++armadillo500fx MACH_ARMADILLO500FX ARMADILLO500FX 1918 ++g3evm MACH_G3EVM G3EVM 1919 ++z3_dm355 MACH_Z3_DM355 Z3_DM355 1920 ++w90p910evb MACH_W90P910EVB W90P910EVB 1921 ++w90p920evb MACH_W90P920EVB W90P920EVB 1922 ++w90p950evb MACH_W90P950EVB W90P950EVB 1923 ++w90n960evb MACH_W90N960EVB W90N960EVB 1924 ++camhd MACH_CAMHD CAMHD 1925 ++mvc100 MACH_MVC100 MVC100 1926 ++electrum_200 MACH_ELECTRUM_200 ELECTRUM_200 1927 ++htcjade MACH_HTCJADE HTCJADE 1928 ++memphis MACH_MEMPHIS MEMPHIS 1929 ++imx27sbc MACH_IMX27SBC IMX27SBC 1930 ++lextar MACH_LEXTAR LEXTAR 1931 ++mv88f6281gtw_ge MACH_MV88F6281GTW_GE MV88F6281GTW_GE 1932 ++ncp MACH_NCP NCP 1933 ++z32an_series MACH_Z32AN Z32AN 1934 ++tmq_capd MACH_TMQ_CAPD TMQ_CAPD 1935 ++omap3_wl MACH_OMAP3_WL OMAP3_WL 1936 ++chumby MACH_CHUMBY CHUMBY 1937 ++atsarm9 MACH_ATSARM9 ATSARM9 1938 ++davinci_dm365_evm MACH_DAVINCI_DM365_EVM DAVINCI_DM365_EVM 1939 ++bahamas MACH_BAHAMAS BAHAMAS 1940 ++das MACH_DAS DAS 1941 ++minidas MACH_MINIDAS MINIDAS 1942 ++vk1000 MACH_VK1000 VK1000 1943 ++centro MACH_CENTRO CENTRO 1944 ++ctera_2bay MACH_CTERA_2BAY CTERA_2BAY 1945 ++edgeconnect MACH_EDGECONNECT EDGECONNECT 1946 ++nd27000 MACH_ND27000 ND27000 1947 ++cobra MACH_GEMALTO_COBRA GEMALTO_COBRA 1948 ++ingelabs_comet MACH_INGELABS_COMET INGELABS_COMET 1949 ++pollux_wiz MACH_POLLUX_WIZ POLLUX_WIZ 1950 ++blackstone MACH_BLACKSTONE BLACKSTONE 1951 ++topaz MACH_TOPAZ TOPAZ 1952 ++aixle MACH_AIXLE AIXLE 1953 ++mw998 MACH_MW998 MW998 1954 ++nokia_rx51 MACH_NOKIA_RX51 NOKIA_RX51 1955 ++vsc5605ev MACH_VSC5605EV VSC5605EV 1956 ++nt98700dk MACH_NT98700DK NT98700DK 1957 ++icontact MACH_ICONTACT ICONTACT 1958 ++swarco_frcpu MACH_SWARCO_FRCPU SWARCO_FRCPU 1959 ++swarco_scpu MACH_SWARCO_SCPU SWARCO_SCPU 1960 ++bbox_p16 MACH_BBOX_P16 BBOX_P16 1961 ++bstd MACH_BSTD BSTD 1962 ++sbc2440ii MACH_SBC2440II SBC2440II 1963 ++pcm034 MACH_PCM034 PCM034 1964 ++neso MACH_NESO NESO 1965 ++wlnx_9g20 MACH_WLNX_9G20 WLNX_9G20 1966 ++omap_zoom2 MACH_OMAP_ZOOM2 OMAP_ZOOM2 1967 ++totemnova MACH_TOTEMNOVA TOTEMNOVA 1968 ++c5000 MACH_C5000 C5000 1969 ++unipo_at91sam9263 MACH_UNIPO_AT91SAM9263 UNIPO_AT91SAM9263 1970 ++ethernut5 MACH_ETHERNUT5 ETHERNUT5 1971 ++arm11 MACH_ARM11 ARM11 1972 ++cpuat9260 MACH_CPUAT9260 CPUAT9260 1973 ++cpupxa255 MACH_CPUPXA255 CPUPXA255 1974 ++eukrea_cpuimx27 MACH_CPUIMX27 CPUIMX27 1975 ++cheflux MACH_CHEFLUX CHEFLUX 1976 ++eb_cpux9k2 MACH_EB_CPUX9K2 EB_CPUX9K2 1977 ++opcotec MACH_OPCOTEC OPCOTEC 1978 ++yt MACH_YT YT 1979 ++motoq MACH_MOTOQ MOTOQ 1980 ++bsb1 MACH_BSB1 BSB1 1981 ++acs5k MACH_ACS5K ACS5K 1982 ++milan MACH_MILAN MILAN 1983 ++quartzv2 MACH_QUARTZV2 QUARTZV2 1984 ++rsvp MACH_RSVP RSVP 1985 ++rmp200 MACH_RMP200 RMP200 1986 ++snapper_9260 MACH_SNAPPER_9260 SNAPPER_9260 1987 ++dsm320 MACH_DSM320 DSM320 1988 ++adsgcm MACH_ADSGCM ADSGCM 1989 ++ase2_400 MACH_ASE2_400 ASE2_400 1990 ++pizza MACH_PIZZA PIZZA 1991 ++spot_ngpl MACH_SPOT_NGPL SPOT_NGPL 1992 ++armata MACH_ARMATA ARMATA 1993 ++exeda MACH_EXEDA EXEDA 1994 ++mx31sf005 MACH_MX31SF005 MX31SF005 1995 ++f5d8231_4_v2 MACH_F5D8231_4_V2 F5D8231_4_V2 1996 ++q2440 MACH_Q2440 Q2440 1997 ++qq2440 MACH_QQ2440 QQ2440 1998 ++mini2440 MACH_MINI2440 MINI2440 1999 ++colibri300 MACH_COLIBRI300 COLIBRI300 2000 ++jades MACH_JADES JADES 2001 ++spark MACH_SPARK SPARK 2002 ++benzina MACH_BENZINA BENZINA 2003 ++blaze MACH_BLAZE BLAZE 2004 ++linkstation_ls_hgl MACH_LINKSTATION_LS_HGL LINKSTATION_LS_HGL 2005 ++htckovsky MACH_HTCVENUS HTCVENUS 2006 ++sony_prs505 MACH_SONY_PRS505 SONY_PRS505 2007 ++hanlin_v3 MACH_HANLIN_V3 HANLIN_V3 2008 ++sapphira MACH_SAPPHIRA SAPPHIRA 2009 ++dack_sda_01 MACH_DACK_SDA_01 DACK_SDA_01 2010 ++armbox MACH_ARMBOX ARMBOX 2011 ++harris_rvp MACH_HARRIS_RVP HARRIS_RVP 2012 ++ribaldo MACH_RIBALDO RIBALDO 2013 ++agora MACH_AGORA AGORA 2014 ++omap3_mini MACH_OMAP3_MINI OMAP3_MINI 2015 ++a9sam6432_b MACH_A9SAM6432_B A9SAM6432_B 2016 ++usg2410 MACH_USG2410 USG2410 2017 ++pc72052_i10_revb MACH_PC72052_I10_REVB PC72052_I10_REVB 2018 ++mx35_exm32 MACH_MX35_EXM32 MX35_EXM32 2019 ++topas910 MACH_TOPAS910 TOPAS910 2020 ++hyena MACH_HYENA HYENA 2021 ++pospax MACH_POSPAX POSPAX 2022 ++hdl_gx MACH_HDL_GX HDL_GX 2023 ++ctera_4bay MACH_CTERA_4BAY CTERA_4BAY 2024 ++ctera_plug_c MACH_CTERA_PLUG_C CTERA_PLUG_C 2025 ++crwea_plug_i MACH_CRWEA_PLUG_I CRWEA_PLUG_I 2026 ++egauge2 MACH_EGAUGE2 EGAUGE2 2027 ++didj MACH_DIDJ DIDJ 2028 ++m_s3c2443 MACH_MEISTER MEISTER 2029 ++htcblackstone MACH_HTCBLACKSTONE HTCBLACKSTONE 2030 ++cpuat9g20 MACH_CPUAT9G20 CPUAT9G20 2031 ++smdk6440 MACH_SMDK6440 SMDK6440 2032 ++omap_35xx_mvp MACH_OMAP_35XX_MVP OMAP_35XX_MVP 2033 ++ctera_plug_i MACH_CTERA_PLUG_I CTERA_PLUG_I 2034 ++pvg610_100 MACH_PVG610 PVG610 2035 ++hprw6815 MACH_HPRW6815 HPRW6815 2036 ++omap3_oswald MACH_OMAP3_OSWALD OMAP3_OSWALD 2037 ++nas4220b MACH_NAS4220B NAS4220B 2038 ++htcraphael_cdma MACH_HTCRAPHAEL_CDMA HTCRAPHAEL_CDMA 2039 ++htcdiamond_cdma MACH_HTCDIAMOND_CDMA HTCDIAMOND_CDMA 2040 ++scaler MACH_SCALER SCALER 2041 ++zylonite2 MACH_ZYLONITE2 ZYLONITE2 2042 ++aspenite MACH_ASPENITE ASPENITE 2043 ++teton MACH_TETON TETON 2044 ++ttc_dkb MACH_TTC_DKB TTC_DKB 2045 ++bishop2 MACH_BISHOP2 BISHOP2 2046 ++ippv5 MACH_IPPV5 IPPV5 2047 ++farm926 MACH_FARM926 FARM926 2048 ++mmccpu MACH_MMCCPU MMCCPU 2049 ++sgmsfl MACH_SGMSFL SGMSFL 2050 ++tt8000 MACH_TT8000 TT8000 2051 ++zrn4300lp MACH_ZRN4300LP ZRN4300LP 2052 ++mptc MACH_MPTC MPTC 2053 ++h6051 MACH_H6051 H6051 2054 ++pvg610_101 MACH_PVG610_101 PVG610_101 2055 ++stamp9261_pc_evb MACH_STAMP9261_PC_EVB STAMP9261_PC_EVB 2056 ++pelco_odysseus MACH_PELCO_ODYSSEUS PELCO_ODYSSEUS 2057 ++tny_a9260 MACH_TNY_A9260 TNY_A9260 2058 ++tny_a9g20 MACH_TNY_A9G20 TNY_A9G20 2059 ++aesop_mp2530f MACH_AESOP_MP2530F AESOP_MP2530F 2060 ++dx900 MACH_DX900 DX900 2061 ++cpodc2 MACH_CPODC2 CPODC2 2062 ++tilt_8925 MACH_TILT_8925 TILT_8925 2063 ++davinci_dm357_evm MACH_DAVINCI_DM357_EVM DAVINCI_DM357_EVM 2064 ++swordfish MACH_SWORDFISH SWORDFISH 2065 ++corvus MACH_CORVUS CORVUS 2066 ++taurus MACH_TAURUS TAURUS 2067 ++axm MACH_AXM AXM 2068 ++axc MACH_AXC AXC 2069 ++baby MACH_BABY BABY 2070 ++mp200 MACH_MP200 MP200 2071 ++pcm043 MACH_PCM043 PCM043 2072 ++hanlin_v3c MACH_HANLIN_V3C HANLIN_V3C 2073 ++kbk9g20 MACH_KBK9G20 KBK9G20 2074 ++adsturbog5 MACH_ADSTURBOG5 ADSTURBOG5 2075 ++avenger_lite1 MACH_AVENGER_LITE1 AVENGER_LITE1 2076 ++suc82x MACH_SUC SUC 2077 ++at91sam7s256 MACH_AT91SAM7S256 AT91SAM7S256 2078 ++mendoza MACH_MENDOZA MENDOZA 2079 ++kira MACH_KIRA KIRA 2080 ++mx1hbm MACH_MX1HBM MX1HBM 2081 ++quatro43xx MACH_QUATRO43XX QUATRO43XX 2082 ++quatro4230 MACH_QUATRO4230 QUATRO4230 2083 ++nsb400 MACH_NSB400 NSB400 2084 ++drp255 MACH_DRP255 DRP255 2085 ++thoth MACH_THOTH THOTH 2086 ++firestone MACH_FIRESTONE FIRESTONE 2087 ++asusp750 MACH_ASUSP750 ASUSP750 2088 ++ctera_dl MACH_CTERA_DL CTERA_DL 2089 ++socr MACH_SOCR SOCR 2090 ++htcoxygen MACH_HTCOXYGEN HTCOXYGEN 2091 ++heroc MACH_HEROC HEROC 2092 ++zeno6800 MACH_ZENO6800 ZENO6800 2093 ++sc2mcs MACH_SC2MCS SC2MCS 2094 ++gene100 MACH_GENE100 GENE100 2095 ++as353x MACH_AS353X AS353X 2096 ++sheevaplug MACH_SHEEVAPLUG SHEEVAPLUG 2097 ++at91sam9g20 MACH_AT91SAM9G20 AT91SAM9G20 2098 ++mv88f6192gtw_fe MACH_MV88F6192GTW_FE MV88F6192GTW_FE 2099 ++cc9200 MACH_CC9200 CC9200 2100 ++sm9200 MACH_SM9200 SM9200 2101 ++tp9200 MACH_TP9200 TP9200 2102 ++snapperdv MACH_SNAPPERDV SNAPPERDV 2103 ++avengers_lite MACH_AVENGERS_LITE AVENGERS_LITE 2104 ++avengers_lite1 MACH_AVENGERS_LITE1 AVENGERS_LITE1 2105 ++omap3axon MACH_OMAP3AXON OMAP3AXON 2106 ++ma8xx MACH_MA8XX MA8XX 2107 ++mp201ek MACH_MP201EK MP201EK 2108 ++davinci_tux MACH_DAVINCI_TUX DAVINCI_TUX 2109 ++mpa1600 MACH_MPA1600 MPA1600 2110 ++pelco_troy MACH_PELCO_TROY PELCO_TROY 2111 ++nsb667 MACH_NSB667 NSB667 2112 ++rovers5_4mpix MACH_ROVERS5_4MPIX ROVERS5_4MPIX 2113 ++twocom MACH_TWOCOM TWOCOM 2114 ++ubisys_p9_rcu3r2 MACH_UBISYS_P9_RCU3R2 UBISYS_P9_RCU3R2 2115 ++hero_espresso MACH_HERO_ESPRESSO HERO_ESPRESSO 2116 ++afeusb MACH_AFEUSB AFEUSB 2117 ++t830 MACH_T830 T830 2118 ++spd8020_cc MACH_SPD8020_CC SPD8020_CC 2119 ++om_3d7k MACH_OM_3D7K OM_3D7K 2120 ++picocom2 MACH_PICOCOM2 PICOCOM2 2121 ++uwg4mx27 MACH_UWG4MX27 UWG4MX27 2122 ++uwg4mx31 MACH_UWG4MX31 UWG4MX31 2123 ++cherry MACH_CHERRY CHERRY 2124 ++mx51_babbage MACH_MX51_BABBAGE MX51_BABBAGE 2125 ++s3c2440turkiye MACH_S3C2440TURKIYE S3C2440TURKIYE 2126 ++tx37 MACH_TX37 TX37 2127 ++sbc2800_9g20 MACH_SBC2800_9G20 SBC2800_9G20 2128 ++benzglb MACH_BENZGLB BENZGLB 2129 ++benztd MACH_BENZTD BENZTD 2130 ++cartesio_plus MACH_CARTESIO_PLUS CARTESIO_PLUS 2131 ++solrad_g20 MACH_SOLRAD_G20 SOLRAD_G20 2132 ++mx27wallace MACH_MX27WALLACE MX27WALLACE 2133 ++fmzwebmodul MACH_FMZWEBMODUL FMZWEBMODUL 2134 ++rd78x00_masa MACH_RD78X00_MASA RD78X00_MASA 2135 ++smallogger MACH_SMALLOGGER SMALLOGGER 2136 ++ccw9p9215 MACH_CCW9P9215 CCW9P9215 2137 ++dm355_leopard MACH_DM355_LEOPARD DM355_LEOPARD 2138 ++ts219 MACH_TS219 TS219 2139 ++tny_a9263 MACH_TNY_A9263 TNY_A9263 2140 ++apollo MACH_APOLLO APOLLO 2141 ++at91cap9stk MACH_AT91CAP9STK AT91CAP9STK 2142 ++spc300 MACH_SPC300 SPC300 2143 ++eko MACH_EKO EKO 2144 ++ccw9m2443 MACH_CCW9M2443 CCW9M2443 2145 ++ccw9m2443js MACH_CCW9M2443JS CCW9M2443JS 2146 ++m2m_router_device MACH_M2M_ROUTER_DEVICE M2M_ROUTER_DEVICE 2147 ++str9104nas MACH_STAR9104NAS STAR9104NAS 2148 ++pca100 MACH_PCA100 PCA100 2149 ++z3_dm365_mod_01 MACH_Z3_DM365_MOD_01 Z3_DM365_MOD_01 2150 ++hipox MACH_HIPOX HIPOX 2151 ++omap3_piteds MACH_OMAP3_PITEDS OMAP3_PITEDS 2152 ++bm150r MACH_BM150R BM150R 2153 ++tbone MACH_TBONE TBONE 2154 ++merlin MACH_MERLIN MERLIN 2155 ++falcon MACH_FALCON FALCON 2156 ++davinci_da850_evm MACH_DAVINCI_DA850_EVM DAVINCI_DA850_EVM 2157 ++s5p6440 MACH_S5P6440 S5P6440 2158 ++at91sam9g10ek MACH_AT91SAM9G10EK AT91SAM9G10EK 2159 ++omap_4430sdp MACH_OMAP_4430SDP OMAP_4430SDP 2160 ++lpc313x MACH_LPC313X LPC313X 2161 ++magx_zn5 MACH_MAGX_ZN5 MAGX_ZN5 2162 ++magx_em30 MACH_MAGX_EM30 MAGX_EM30 2163 ++magx_ve66 MACH_MAGX_VE66 MAGX_VE66 2164 ++meesc MACH_MEESC MEESC 2165 ++otc570 MACH_OTC570 OTC570 2166 ++bcu2412 MACH_BCU2412 BCU2412 2167 ++beacon MACH_BEACON BEACON 2168 ++actia_tgw MACH_ACTIA_TGW ACTIA_TGW 2169 ++e4430 MACH_E4430 E4430 2170 ++ql300 MACH_QL300 QL300 2171 ++btmavb101 MACH_BTMAVB101 BTMAVB101 2172 ++btmawb101 MACH_BTMAWB101 BTMAWB101 2173 ++sq201 MACH_SQ201 SQ201 2174 ++quatro45xx MACH_QUATRO45XX QUATRO45XX 2175 ++openpad MACH_OPENPAD OPENPAD 2176 ++tx25 MACH_TX25 TX25 2177 ++omap3_torpedo MACH_OMAP3_TORPEDO OMAP3_TORPEDO 2178 ++htcraphael_k MACH_HTCRAPHAEL_K HTCRAPHAEL_K 2179 ++lal43 MACH_LAL43 LAL43 2181 ++htcraphael_cdma500 MACH_HTCRAPHAEL_CDMA500 HTCRAPHAEL_CDMA500 2182 ++anw6410 MACH_ANW6410 ANW6410 2183 ++htcprophet MACH_HTCPROPHET HTCPROPHET 2185 ++cfa_10022 MACH_CFA_10022 CFA_10022 2186 ++imx27_visstrim_m10 MACH_IMX27_VISSTRIM_M10 IMX27_VISSTRIM_M10 2187 ++px2imx27 MACH_PX2IMX27 PX2IMX27 2188 ++stm3210e_eval MACH_STM3210E_EVAL STM3210E_EVAL 2189 ++dvs10 MACH_DVS10 DVS10 2190 ++portuxg20 MACH_PORTUXG20 PORTUXG20 2191 ++arm_spv MACH_ARM_SPV ARM_SPV 2192 ++smdkc110 MACH_SMDKC110 SMDKC110 2193 ++cabespresso MACH_CABESPRESSO CABESPRESSO 2194 ++hmc800 MACH_HMC800 HMC800 2195 ++sholes MACH_SHOLES SHOLES 2196 ++btmxc31 MACH_BTMXC31 BTMXC31 2197 ++dt501 MACH_DT501 DT501 2198 ++ktx MACH_KTX KTX 2199 ++omap3517evm MACH_OMAP3517EVM OMAP3517EVM 2200 ++netspace_v2 MACH_NETSPACE_V2 NETSPACE_V2 2201 ++netspace_max_v2 MACH_NETSPACE_MAX_V2 NETSPACE_MAX_V2 2202 ++d2net_v2 MACH_D2NET_V2 D2NET_V2 2203 ++net2big_v2 MACH_NET2BIG_V2 NET2BIG_V2 2204 ++net4big_v2 MACH_NET4BIG_V2 NET4BIG_V2 2205 ++net5big_v2 MACH_NET5BIG_V2 NET5BIG_V2 2206 ++endb2443 MACH_ENDB2443 ENDB2443 2207 ++inetspace_v2 MACH_INETSPACE_V2 INETSPACE_V2 2208 ++tros MACH_TROS TROS 2209 ++pelco_homer MACH_PELCO_HOMER PELCO_HOMER 2210 ++ofsp8 MACH_OFSP8 OFSP8 2211 ++at91sam9g45ekes MACH_AT91SAM9G45EKES AT91SAM9G45EKES 2212 ++guf_cupid MACH_GUF_CUPID GUF_CUPID 2213 ++eab1r MACH_EAB1R EAB1R 2214 ++desirec MACH_DESIREC DESIREC 2215 ++cordoba MACH_CORDOBA CORDOBA 2216 ++irvine MACH_IRVINE IRVINE 2217 ++sff772 MACH_SFF772 SFF772 2218 ++pelco_milano MACH_PELCO_MILANO PELCO_MILANO 2219 ++pc7302 MACH_PC7302 PC7302 2220 ++bip6000 MACH_BIP6000 BIP6000 2221 ++silvermoon MACH_SILVERMOON SILVERMOON 2222 ++vc0830 MACH_VC0830 VC0830 2223 ++dt430 MACH_DT430 DT430 2224 ++ji42pf MACH_JI42PF JI42PF 2225 ++gnet_ksm MACH_GNET_KSM GNET_KSM 2226 ++gnet_sgm MACH_GNET_SGM GNET_SGM 2227 ++gnet_sgr MACH_GNET_SGR GNET_SGR 2228 ++omap3_icetekevm MACH_OMAP3_ICETEKEVM OMAP3_ICETEKEVM 2229 ++pnp MACH_PNP PNP 2230 ++ctera_2bay_k MACH_CTERA_2BAY_K CTERA_2BAY_K 2231 ++ctera_2bay_u MACH_CTERA_2BAY_U CTERA_2BAY_U 2232 ++sas_c MACH_SAS_C SAS_C 2233 ++vma2315 MACH_VMA2315 VMA2315 2234 ++vcs MACH_VCS VCS 2235 ++spear600 MACH_SPEAR600 SPEAR600 2236 ++spear300 MACH_SPEAR300 SPEAR300 2237 ++spear1300 MACH_SPEAR1300 SPEAR1300 2238 ++lilly1131 MACH_LILLY1131 LILLY1131 2239 ++arvoo_ax301 MACH_ARVOO_AX301 ARVOO_AX301 2240 ++mapphone MACH_MAPPHONE MAPPHONE 2241 ++legend MACH_LEGEND LEGEND 2242 ++salsa MACH_SALSA SALSA 2243 ++lounge MACH_LOUNGE LOUNGE 2244 ++vision MACH_VISION VISION 2245 ++vmb20 MACH_VMB20 VMB20 2246 ++hy2410 MACH_HY2410 HY2410 2247 ++hy9315 MACH_HY9315 HY9315 2248 ++bullwinkle MACH_BULLWINKLE BULLWINKLE 2249 ++arm_ultimator2 MACH_ARM_ULTIMATOR2 ARM_ULTIMATOR2 2250 ++vs_v210 MACH_VS_V210 VS_V210 2252 ++vs_v212 MACH_VS_V212 VS_V212 2253 ++hmt MACH_HMT HMT 2254 ++suen3 MACH_SUEN3 SUEN3 2255 ++vesper MACH_VESPER VESPER 2256 ++str9 MACH_STR9 STR9 2257 ++omap3_wl_ff MACH_OMAP3_WL_FF OMAP3_WL_FF 2258 ++simcom MACH_SIMCOM SIMCOM 2259 ++mcwebio MACH_MCWEBIO MCWEBIO 2260 ++omap3_phrazer MACH_OMAP3_PHRAZER OMAP3_PHRAZER 2261 ++darwin MACH_DARWIN DARWIN 2262 ++oratiscomu MACH_ORATISCOMU ORATISCOMU 2263 ++rtsbc20 MACH_RTSBC20 RTSBC20 2264 ++sgh_i780 MACH_I780 I780 2265 ++gemini324 MACH_GEMINI324 GEMINI324 2266 ++oratislan MACH_ORATISLAN ORATISLAN 2267 ++oratisalog MACH_ORATISALOG ORATISALOG 2268 ++oratismadi MACH_ORATISMADI ORATISMADI 2269 ++oratisot16 MACH_ORATISOT16 ORATISOT16 2270 ++oratisdesk MACH_ORATISDESK ORATISDESK 2271 ++v2_ca9 MACH_V2P_CA9 V2P_CA9 2272 ++sintexo MACH_SINTEXO SINTEXO 2273 ++cm3389 MACH_CM3389 CM3389 2274 ++omap3_cio MACH_OMAP3_CIO OMAP3_CIO 2275 ++sgh_i900 MACH_SGH_I900 SGH_I900 2276 ++bst100 MACH_BST100 BST100 2277 ++passion MACH_PASSION PASSION 2278 ++indesign_at91sam MACH_INDESIGN_AT91SAM INDESIGN_AT91SAM 2279 ++c4_badger MACH_C4_BADGER C4_BADGER 2280 ++c4_viper MACH_C4_VIPER C4_VIPER 2281 ++d2net MACH_D2NET D2NET 2282 ++bigdisk MACH_BIGDISK BIGDISK 2283 ++notalvision MACH_NOTALVISION NOTALVISION 2284 ++omap3_kboc MACH_OMAP3_KBOC OMAP3_KBOC 2285 ++cyclone MACH_CYCLONE CYCLONE 2286 ++ninja MACH_NINJA NINJA 2287 ++at91sam9g20ek_2mmc MACH_AT91SAM9G20EK_2MMC AT91SAM9G20EK_2MMC 2288 ++bcmring MACH_BCMRING BCMRING 2289 ++resol_dl2 MACH_RESOL_DL2 RESOL_DL2 2290 ++ifosw MACH_IFOSW IFOSW 2291 ++htcrhodium MACH_HTCRHODIUM HTCRHODIUM 2292 ++htctopaz MACH_HTCTOPAZ HTCTOPAZ 2293 ++matrix504 MACH_MATRIX504 MATRIX504 2294 ++mrfsa MACH_MRFSA MRFSA 2295 ++sc_p270 MACH_SC_P270 SC_P270 2296 ++atlas5_evb MACH_ATLAS5_EVB ATLAS5_EVB 2297 ++pelco_lobox MACH_PELCO_LOBOX PELCO_LOBOX 2298 ++dilax_pcu200 MACH_DILAX_PCU200 DILAX_PCU200 2299 ++leonardo MACH_LEONARDO LEONARDO 2300 ++zoran_approach7 MACH_ZORAN_APPROACH7 ZORAN_APPROACH7 2301 ++dp6xx MACH_DP6XX DP6XX 2302 ++bcm2153_vesper MACH_BCM2153_VESPER BCM2153_VESPER 2303 ++mahimahi MACH_MAHIMAHI MAHIMAHI 2304 ++clickc MACH_CLICKC CLICKC 2305 ++zb_gateway MACH_ZB_GATEWAY ZB_GATEWAY 2306 ++tazcard MACH_TAZCARD TAZCARD 2307 ++tazdev MACH_TAZDEV TAZDEV 2308 ++annax_cb_arm MACH_ANNAX_CB_ARM ANNAX_CB_ARM 2309 ++annax_dm3 MACH_ANNAX_DM3 ANNAX_DM3 2310 ++cerebric MACH_CEREBRIC CEREBRIC 2311 ++orca MACH_ORCA ORCA 2312 ++pc9260 MACH_PC9260 PC9260 2313 ++ems285a MACH_EMS285A EMS285A 2314 ++gec2410 MACH_GEC2410 GEC2410 2315 ++gec2440 MACH_GEC2440 GEC2440 2316 ++mw903 MACH_ARCH_MW903 ARCH_MW903 2317 ++mw2440 MACH_MW2440 MW2440 2318 ++ecac2378 MACH_ECAC2378 ECAC2378 2319 ++tazkiosk MACH_TAZKIOSK TAZKIOSK 2320 ++whiterabbit_mch MACH_WHITERABBIT_MCH WHITERABBIT_MCH 2321 ++sbox9263 MACH_SBOX9263 SBOX9263 2322 ++oreo MACH_OREO OREO 2323 ++smdk6442 MACH_SMDK6442 SMDK6442 2324 ++openrd_base MACH_OPENRD_BASE OPENRD_BASE 2325 ++incredible MACH_INCREDIBLE INCREDIBLE 2326 ++incrediblec MACH_INCREDIBLEC INCREDIBLEC 2327 ++heroct MACH_HEROCT HEROCT 2328 ++mmnet1000 MACH_MMNET1000 MMNET1000 2329 ++devkit8000 MACH_DEVKIT8000 DEVKIT8000 2330 ++devkit9000 MACH_DEVKIT9000 DEVKIT9000 2331 ++mx31txtr MACH_MX31TXTR MX31TXTR 2332 ++u380 MACH_U380 U380 2333 ++oamp3_hualu MACH_HUALU_BOARD HUALU_BOARD 2334 ++npcmx50 MACH_NPCMX50 NPCMX50 2335 ++mx51_lange51 MACH_MX51_LANGE51 MX51_LANGE51 2336 ++mx51_lange52 MACH_MX51_LANGE52 MX51_LANGE52 2337 ++riom MACH_RIOM RIOM 2338 ++comcas MACH_COMCAS COMCAS 2339 ++wsi_mx27 MACH_WSI_MX27 WSI_MX27 2340 ++cm_t35 MACH_CM_T35 CM_T35 2341 ++net2big MACH_NET2BIG NET2BIG 2342 ++motorola_a1600 MACH_MOTOROLA_A1600 MOTOROLA_A1600 2343 ++igep0020 MACH_IGEP0020 IGEP0020 2344 ++igep0010 MACH_IGEP0010 IGEP0010 2345 ++mv6281gtwge2 MACH_MV6281GTWGE2 MV6281GTWGE2 2346 ++scat100 MACH_SCAT100 SCAT100 2347 ++sanmina MACH_SANMINA SANMINA 2348 ++momento MACH_MOMENTO MOMENTO 2349 ++nuc9xx MACH_NUC9XX NUC9XX 2350 ++nuc910evb MACH_NUC910EVB NUC910EVB 2351 ++nuc920evb MACH_NUC920EVB NUC920EVB 2352 ++nuc950evb MACH_NUC950EVB NUC950EVB 2353 ++nuc945evb MACH_NUC945EVB NUC945EVB 2354 ++nuc960evb MACH_NUC960EVB NUC960EVB 2355 ++nuc932evb MACH_NUC932EVB NUC932EVB 2356 ++nuc900 MACH_NUC900 NUC900 2357 ++sd1soc MACH_SD1SOC SD1SOC 2358 ++ln2440bc MACH_LN2440BC LN2440BC 2359 ++rsbc MACH_RSBC RSBC 2360 ++openrd_client MACH_OPENRD_CLIENT OPENRD_CLIENT 2361 ++hpipaq11x MACH_HPIPAQ11X HPIPAQ11X 2362 ++wayland MACH_WAYLAND WAYLAND 2363 ++acnbsx102 MACH_ACNBSX102 ACNBSX102 2364 ++hwat91 MACH_HWAT91 HWAT91 2365 ++at91sam9263cs MACH_AT91SAM9263CS AT91SAM9263CS 2366 ++csb732 MACH_CSB732 CSB732 2367 ++u8500 MACH_U8500 U8500 2368 ++huqiu MACH_HUQIU HUQIU 2369 ++mx51_kunlun MACH_MX51_KUNLUN MX51_KUNLUN 2370 ++pmt1g MACH_PMT1G PMT1G 2371 ++htcelf MACH_HTCELF HTCELF 2372 ++armadillo420 MACH_ARMADILLO420 ARMADILLO420 2373 ++armadillo440 MACH_ARMADILLO440 ARMADILLO440 2374 ++u_chip_dual_arm MACH_U_CHIP_DUAL_ARM U_CHIP_DUAL_ARM 2375 ++csr_bdb3 MACH_CSR_BDB3 CSR_BDB3 2376 ++dolby_cat1018 MACH_DOLBY_CAT1018 DOLBY_CAT1018 2377 ++hy9307 MACH_HY9307 HY9307 2378 ++aspire_easystore MACH_A_ES A_ES 2379 ++davinci_irif MACH_DAVINCI_IRIF DAVINCI_IRIF 2380 ++agama9263 MACH_AGAMA9263 AGAMA9263 2381 ++marvell_jasper MACH_MARVELL_JASPER MARVELL_JASPER 2382 ++flint MACH_FLINT FLINT 2383 ++tavorevb3 MACH_TAVOREVB3 TAVOREVB3 2384 ++sch_m490 MACH_SCH_M490 SCH_M490 2386 ++rbl01 MACH_RBL01 RBL01 2387 ++omnifi MACH_OMNIFI OMNIFI 2388 ++otavalo MACH_OTAVALO OTAVALO 2389 ++sienna MACH_SIENNA SIENNA 2390 ++htc_excalibur_s620 MACH_HTC_EXCALIBUR_S620 HTC_EXCALIBUR_S620 2391 ++htc_opal MACH_HTC_OPAL HTC_OPAL 2392 ++touchbook MACH_TOUCHBOOK TOUCHBOOK 2393 ++latte MACH_LATTE LATTE 2394 ++xa200 MACH_XA200 XA200 2395 ++nimrod MACH_NIMROD NIMROD 2396 ++cc9p9215_3g MACH_CC9P9215_3G CC9P9215_3G 2397 ++cc9p9215_3gjs MACH_CC9P9215_3GJS CC9P9215_3GJS 2398 ++tk71 MACH_TK71 TK71 2399 ++comham3525 MACH_COMHAM3525 COMHAM3525 2400 ++mx31erebus MACH_MX31EREBUS MX31EREBUS 2401 ++mcardmx27 MACH_MCARDMX27 MCARDMX27 2402 ++paradise MACH_PARADISE PARADISE 2403 ++tide MACH_TIDE TIDE 2404 ++wzl2440 MACH_WZL2440 WZL2440 2405 ++sdrdemo MACH_SDRDEMO SDRDEMO 2406 ++ethercan2 MACH_ETHERCAN2 ETHERCAN2 2407 ++ecmimg20 MACH_ECMIMG20 ECMIMG20 2408 ++omap_dragon MACH_OMAP_DRAGON OMAP_DRAGON 2409 ++halo MACH_HALO HALO 2410 ++huangshan MACH_HUANGSHAN HUANGSHAN 2411 ++vl_ma2sc MACH_VL_MA2SC VL_MA2SC 2412 ++raumfeld_rc MACH_RAUMFELD_RC RAUMFELD_RC 2413 ++raumfeld_connector MACH_RAUMFELD_CONNECTOR RAUMFELD_CONNECTOR 2414 ++raumfeld_speaker MACH_RAUMFELD_SPEAKER RAUMFELD_SPEAKER 2415 ++multibus_master MACH_MULTIBUS_MASTER MULTIBUS_MASTER 2416 ++multibus_pbk MACH_MULTIBUS_PBK MULTIBUS_PBK 2417 ++tnetv107x MACH_TNETV107X TNETV107X 2418 ++snake MACH_SNAKE SNAKE 2419 ++cwmx27 MACH_CWMX27 CWMX27 2420 ++sch_m480 MACH_SCH_M480 SCH_M480 2421 ++platypus MACH_PLATYPUS PLATYPUS 2422 ++pss2 MACH_PSS2 PSS2 2423 ++davinci_apm150 MACH_DAVINCI_APM150 DAVINCI_APM150 2424 ++str9100 MACH_STR9100 STR9100 2425 ++net5big MACH_NET5BIG NET5BIG 2426 ++seabed9263 MACH_SEABED9263 SEABED9263 2427 ++mx51_m2id MACH_MX51_M2ID MX51_M2ID 2428 ++octvocplus_eb MACH_OCTVOCPLUS_EB OCTVOCPLUS_EB 2429 ++klk_firefox MACH_KLK_FIREFOX KLK_FIREFOX 2430 ++klk_wirma_module MACH_KLK_WIRMA_MODULE KLK_WIRMA_MODULE 2431 ++klk_wirma_mmi MACH_KLK_WIRMA_MMI KLK_WIRMA_MMI 2432 ++supersonic MACH_SUPERSONIC SUPERSONIC 2433 ++liberty MACH_LIBERTY LIBERTY 2434 ++mh355 MACH_MH355 MH355 2435 ++pc7802 MACH_PC7802 PC7802 2436 ++gnet_sgc MACH_GNET_SGC GNET_SGC 2437 ++einstein15 MACH_EINSTEIN15 EINSTEIN15 2438 ++cmpd MACH_CMPD CMPD 2439 ++davinci_hase1 MACH_DAVINCI_HASE1 DAVINCI_HASE1 2440 ++lgeincitephone MACH_LGEINCITEPHONE LGEINCITEPHONE 2441 ++ea313x MACH_EA313X EA313X 2442 ++fwbd_39064 MACH_FWBD_39064 FWBD_39064 2443 ++fwbd_390128 MACH_FWBD_390128 FWBD_390128 2444 ++pelco_moe MACH_PELCO_MOE PELCO_MOE 2445 ++minimix27 MACH_MINIMIX27 MINIMIX27 2446 ++omap3_thunder MACH_OMAP3_THUNDER OMAP3_THUNDER 2447 ++passionc MACH_PASSIONC PASSIONC 2448 ++mx27amata MACH_MX27AMATA MX27AMATA 2449 ++bgat1 MACH_BGAT1 BGAT1 2450 ++buzz MACH_BUZZ BUZZ 2451 ++mb9g20 MACH_MB9G20 MB9G20 2452 ++yushan MACH_YUSHAN YUSHAN 2453 ++lizard MACH_LIZARD LIZARD 2454 ++omap3polycom MACH_OMAP3POLYCOM OMAP3POLYCOM 2455 ++smdkv210 MACH_SMDKV210 SMDKV210 2456 ++bravo MACH_BRAVO BRAVO 2457 ++siogentoo1 MACH_SIOGENTOO1 SIOGENTOO1 2458 ++siogentoo2 MACH_SIOGENTOO2 SIOGENTOO2 2459 ++sm3k MACH_SM3K SM3K 2460 ++acer_tempo_f900 MACH_ACER_TEMPO_F900 ACER_TEMPO_F900 2461 ++sst61vc010_dev MACH_SST61VC010_DEV SST61VC010_DEV 2462 ++glittertind MACH_GLITTERTIND GLITTERTIND 2463 ++omap_zoom3 MACH_OMAP_ZOOM3 OMAP_ZOOM3 2464 ++omap_3630sdp MACH_OMAP_3630SDP OMAP_3630SDP 2465 ++cybook2440 MACH_CYBOOK2440 CYBOOK2440 2466 ++torino_s MACH_TORINO_S TORINO_S 2467 ++havana MACH_HAVANA HAVANA 2468 ++beaumont_11 MACH_BEAUMONT_11 BEAUMONT_11 2469 ++vanguard MACH_VANGUARD VANGUARD 2470 ++s5pc110_draco MACH_S5PC110_DRACO S5PC110_DRACO 2471 ++cartesio_two MACH_CARTESIO_TWO CARTESIO_TWO 2472 ++aster MACH_ASTER ASTER 2473 ++voguesv210 MACH_VOGUESV210 VOGUESV210 2474 ++acm500x MACH_ACM500X ACM500X 2475 ++km9260 MACH_KM9260 KM9260 2476 ++nideflexg1 MACH_NIDEFLEXG1 NIDEFLEXG1 2477 ++ctera_plug_io MACH_CTERA_PLUG_IO CTERA_PLUG_IO 2478 ++smartq7 MACH_SMARTQ7 SMARTQ7 2479 ++at91sam9g10ek2 MACH_AT91SAM9G10EK2 AT91SAM9G10EK2 2480 ++asusp527 MACH_ASUSP527 ASUSP527 2481 ++at91sam9g20mpm2 MACH_AT91SAM9G20MPM2 AT91SAM9G20MPM2 2482 ++topasa900 MACH_TOPASA900 TOPASA900 2483 ++electrum_100 MACH_ELECTRUM_100 ELECTRUM_100 2484 ++mx51grb MACH_MX51GRB MX51GRB 2485 ++xea300 MACH_XEA300 XEA300 2486 ++htcstartrek MACH_HTCSTARTREK HTCSTARTREK 2487 ++lima MACH_LIMA LIMA 2488 ++csb740 MACH_CSB740 CSB740 2489 ++usb_s8815 MACH_USB_S8815 USB_S8815 2490 ++watson_efm_plugin MACH_WATSON_EFM_PLUGIN WATSON_EFM_PLUGIN 2491 ++milkyway MACH_MILKYWAY MILKYWAY 2492 ++g4evm MACH_G4EVM G4EVM 2493 ++picomod6 MACH_PICOMOD6 PICOMOD6 2494 ++omapl138_hawkboard MACH_OMAPL138_HAWKBOARD OMAPL138_HAWKBOARD 2495 ++ip6000 MACH_IP6000 IP6000 2496 ++ip6010 MACH_IP6010 IP6010 2497 ++utm400 MACH_UTM400 UTM400 2498 ++omap3_zybex MACH_OMAP3_ZYBEX OMAP3_ZYBEX 2499 ++wireless_space MACH_WIRELESS_SPACE WIRELESS_SPACE 2500 ++sx560 MACH_SX560 SX560 2501 ++ts41x MACH_TS41X TS41X 2502 ++elphel10373 MACH_ELPHEL10373 ELPHEL10373 2503 ++rhobot MACH_RHOBOT RHOBOT 2504 ++mx51_refresh MACH_MX51_REFRESH MX51_REFRESH 2505 ++ls9260 MACH_LS9260 LS9260 2506 ++shank MACH_SHANK SHANK 2507 ++qsd8x50_st1 MACH_QSD8X50_ST1 QSD8X50_ST1 2508 ++at91sam9m10ekes MACH_AT91SAM9M10EKES AT91SAM9M10EKES 2509 ++hiram MACH_HIRAM HIRAM 2510 ++phy3250 MACH_PHY3250 PHY3250 2511 ++ea3250 MACH_EA3250 EA3250 2512 ++fdi3250 MACH_FDI3250 FDI3250 2513 ++whitestone MACH_WHITESTONE WHITESTONE 2514 ++at91sam9263nit MACH_AT91SAM9263NIT AT91SAM9263NIT 2515 ++ccmx51 MACH_CCMX51 CCMX51 2516 ++ccmx51js MACH_CCMX51JS CCMX51JS 2517 ++ccwmx51 MACH_CCWMX51 CCWMX51 2518 ++ccwmx51js MACH_CCWMX51JS CCWMX51JS 2519 ++mini6410 MACH_MINI6410 MINI6410 2520 ++tiny6410 MACH_TINY6410 TINY6410 2521 ++nano6410 MACH_NANO6410 NANO6410 2522 ++at572d940hfnldb MACH_AT572D940HFNLDB AT572D940HFNLDB 2523 ++htcleo MACH_HTCLEO HTCLEO 2524 ++avp13 MACH_AVP13 AVP13 2525 ++xxsvideod MACH_XXSVIDEOD XXSVIDEOD 2526 ++vpnext MACH_VPNEXT VPNEXT 2527 ++swarco_itc3 MACH_SWARCO_ITC3 SWARCO_ITC3 2528 ++tx51 MACH_TX51 TX51 2529 ++dolby_cat1021 MACH_DOLBY_CAT1021 DOLBY_CAT1021 2530 ++mx28evk MACH_MX28EVK MX28EVK 2531 ++phoenix260 MACH_PHOENIX260 PHOENIX260 2532 ++uvaca_stork MACH_UVACA_STORK UVACA_STORK 2533 ++smartq5 MACH_SMARTQ5 SMARTQ5 2534 ++all3078 MACH_ALL3078 ALL3078 2535 ++ctera_2bay_ds MACH_CTERA_2BAY_DS CTERA_2BAY_DS 2536 ++siogentoo3 MACH_SIOGENTOO3 SIOGENTOO3 2537 ++epb5000 MACH_EPB5000 EPB5000 2538 ++hy9263 MACH_HY9263 HY9263 2539 ++acer_tempo_m900 MACH_ACER_TEMPO_M900 ACER_TEMPO_M900 2540 ++acer_tempo_dx650 MACH_ACER_TEMPO_DX900 ACER_TEMPO_DX900 2541 ++acer_tempo_x960 MACH_ACER_TEMPO_X960 ACER_TEMPO_X960 2542 ++acer_eten_v900 MACH_ACER_ETEN_V900 ACER_ETEN_V900 2543 ++acer_eten_x900 MACH_ACER_ETEN_X900 ACER_ETEN_X900 2544 ++bonnell MACH_BONNELL BONNELL 2545 ++oht_mx27 MACH_OHT_MX27 OHT_MX27 2546 ++htcquartz MACH_HTCQUARTZ HTCQUARTZ 2547 ++davinci_dm6467tevm MACH_DAVINCI_DM6467TEVM DAVINCI_DM6467TEVM 2548 ++c3ax03 MACH_C3AX03 C3AX03 2549 ++mxt_td60 MACH_MXT_TD60 MXT_TD60 2550 ++esyx MACH_ESYX ESYX 2551 ++bulldog MACH_BULLDOG BULLDOG 2553 +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/config_mini6410_a70 linux-2.6.28.6/config_mini6410_a70 +--- linux-2.6.28/config_mini6410_a70 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/config_mini6410_a70 2010-07-20 11:50:21.000000000 +0200 +@@ -0,0 +1,1742 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28.6 ++# Tue Jul 20 17:50:09 2010 ++# ++CONFIG_ARM=y ++# CONFIG_HAVE_PWM is not set ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++CONFIG_NO_IOPORT=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_ZONE_DMA=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="-FriendlyARM" ++CONFIG_LOCALVERSION_AUTO=y ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="scripts/FriendlyARM.cpio" ++CONFIG_INITRAMFS_ROOT_UID=0 ++CONFIG_INITRAMFS_ROOT_GID=0 ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_COMPAT_BRK=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++# CONFIG_LBD is not set ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_LSF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++# CONFIG_IOSCHED_AS is not set ++# CONFIG_IOSCHED_DEADLINE is not set ++# CONFIG_IOSCHED_CFQ is not set ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++# CONFIG_DEFAULT_CFQ is not set ++CONFIG_DEFAULT_NOOP=y ++CONFIG_DEFAULT_IOSCHED="noop" ++CONFIG_CLASSIC_RCU=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++CONFIG_ARCH_S3C64XX=y ++# CONFIG_ARCH_S5P64XX is not set ++# CONFIG_ARCH_S5PC1XX is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_PLAT_S3C64XX=y ++CONFIG_CPU_S3C6400_INIT=y ++CONFIG_CPU_S3C6400_CLOCK=y ++CONFIG_S3C64XX_SETUP_I2C0=y ++# CONFIG_S3C64XX_ADC is not set ++CONFIG_S3C64XX_DEV_FIMC0=y ++CONFIG_S3C64XX_DEV_FIMC1=y ++CONFIG_S3C64XX_SETUP_FIMC0=y ++CONFIG_S3C64XX_SETUP_FIMC1=y ++# CONFIG_S3C6410_PWM is not set ++CONFIG_NONE_PWM=y ++CONFIG_PLAT_S3C=y ++ ++# ++# Boot options ++# ++# CONFIG_S3C_BOOT_WATCHDOG is not set ++CONFIG_S3C_BOOT_ERROR_RESET=y ++ ++# ++# Power management ++# ++CONFIG_S3C_LOWLEVEL_UART_PORT=0 ++# CONFIG_SPLIT_ROOT_FILESYSTEM is not set ++CONFIG_S3C_GPIO_SPACE=0 ++CONFIG_S3C_GPIO_TRACK=y ++CONFIG_S3C_GPIO_PULL_UPDOWN=y ++CONFIG_S3C_GPIO_CFG_S3C24XX=y ++CONFIG_S3C_GPIO_CFG_S3C64XX=y ++CONFIG_S3C_DEV_HSMMC=y ++CONFIG_S3C_DEV_HSMMC1=y ++CONFIG_S3C_DEV_HSMMC2=y ++CONFIG_S3C_DMA_PL080=y ++CONFIG_CPU_S3C6410=y ++CONFIG_S3C6410_SETUP_SDHCI=y ++CONFIG_MACH_SMDK6410=y ++ ++# ++# SMDK6410 MMC/SD slot setup ++# ++CONFIG_SMDK6410_SD_CH0=y ++# CONFIG_SMDK6410_SD_CH1 is not set ++# CONFIG_SMDK6410_SD_CH2 is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_THUMB is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++CONFIG_ARM_VIC=y ++CONFIG_DMABOUNCE=y ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=200 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++# CONFIG_UNEVICTABLE_LRU is not set ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_CMDLINE="" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_FREQ is not set ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_FPE_NWFPE=y ++# CONFIG_FPE_NWFPE_XP is not set ++# CONFIG_FPE_FASTFPE is not set ++# CONFIG_VFP is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++ ++# ++# Power management options ++# ++# CONFIG_PM is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_PACKET is not set ++CONFIG_UNIX=y ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_BOOTP=y ++CONFIG_IP_PNP_RARP=y ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_CONCAT is not set ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_VERIFY_WRITE is not set ++# CONFIG_MTD_NAND_ECC_SMC is not set ++# CONFIG_MTD_NAND_MUSEUM_IDS is not set ++# CONFIG_MTD_NAND_GPIO is not set ++CONFIG_MTD_NAND_IDS=y ++CONFIG_MTD_NAND_S3C=y ++# CONFIG_MTD_NAND_S3C_DEBUG is not set ++CONFIG_MTD_NAND_S3C_HWECC=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ALAUDA is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# UBI - Unsorted block images ++# ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_RESERVE=1 ++# CONFIG_MTD_UBI_GLUEBI is not set ++ ++# ++# UBI debugging options ++# ++# CONFIG_MTD_UBI_DEBUG is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++# CONFIG_BLK_DEV_RAM is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++# CONFIG_SCSI_MULTI_LUN is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_PHYLIB is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_AX88796 is not set ++# CONFIG_SMC91X is not set ++CONFIG_DM9000=y ++CONFIG_DM9000_DEBUGLEVEL=4 ++# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set ++# CONFIG_SMC911X is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=800 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_S3C=y ++# CONFIG_TOUCHSCREEN_NEW is not set ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_WM97XX is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++# CONFIG_DEVKMEM is not set ++CONFIG_LEDS_MINI6410=y ++CONFIG_MINI6410_HELLO_MODULE=m ++CONFIG_MINI6410_BUTTONS=y ++CONFIG_MINI6410_BUZZER=y ++# CONFIG_MINI6410_ADC is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_SAMSUNG=y ++CONFIG_SERIAL_SAMSUNG_UARTS=4 ++# CONFIG_SERIAL_SAMSUNG_DEBUG is not set ++CONFIG_SERIAL_SAMSUNG_CONSOLE=y ++CONFIG_SERIAL_S3C6400=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_S3C_MEM is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_HELPER_AUTO is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++CONFIG_I2C_S3C2410=y ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_AT24 is not set ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++# CONFIG_DEBUG_GPIO is not set ++# CONFIG_GPIO_SYSFS is not set ++ ++# ++# Memory mapped GPIO expanders: ++# ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++CONFIG_S3C2410_WATCHDOG=y ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_UCB1400_CORE is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2_COMMON=y ++# CONFIG_VIDEO_ALLOW_V4L1 is not set ++CONFIG_VIDEO_V4L1_COMPAT=y ++# CONFIG_DVB_CORE is not set ++CONFIG_VIDEO_MEDIA=y ++ ++# ++# Multimedia drivers ++# ++# CONFIG_MEDIA_ATTACH is not set ++CONFIG_MEDIA_TUNER=y ++# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set ++CONFIG_MEDIA_TUNER_SIMPLE=y ++CONFIG_MEDIA_TUNER_TDA8290=y ++CONFIG_MEDIA_TUNER_TDA9887=y ++CONFIG_MEDIA_TUNER_TEA5761=y ++CONFIG_MEDIA_TUNER_TEA5767=y ++CONFIG_MEDIA_TUNER_MT20XX=y ++CONFIG_MEDIA_TUNER_XC2028=y ++CONFIG_MEDIA_TUNER_XC5000=y ++CONFIG_VIDEO_V4L2=y ++CONFIG_VIDEOBUF_GEN=y ++CONFIG_VIDEOBUF_VMALLOC=y ++CONFIG_VIDEO_IR=y ++CONFIG_VIDEO_TVEEPROM=y ++CONFIG_VIDEO_TUNER=y ++CONFIG_VIDEO_CAPTURE_DRIVERS=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++CONFIG_VIDEO_FIXED_MINOR_RANGES=y ++# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set ++CONFIG_VIDEO_IR_I2C=y ++ ++# ++# Encoders/decoders and other helper chips ++# ++ ++# ++# Audio decoders ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TDA9875 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++CONFIG_VIDEO_MSP3400=y ++# CONFIG_VIDEO_CS5345 is not set ++CONFIG_VIDEO_CS53L32A=y ++# CONFIG_VIDEO_M52790 is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++CONFIG_VIDEO_WM8775=y ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_TCM825X is not set ++CONFIG_VIDEO_SAA711X=y ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++ ++# ++# Video and audio decoders ++# ++CONFIG_VIDEO_CX25840=y ++ ++# ++# MPEG video encoders ++# ++CONFIG_VIDEO_CX2341X=y ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++# CONFIG_VIDEO_VIVI is not set ++# CONFIG_VIDEO_SAA5246A is not set ++# CONFIG_VIDEO_SAA5249 is not set ++# CONFIG_SOC_CAMERA is not set ++CONFIG_V4L_USB_DRIVERS=y ++CONFIG_USB_VIDEO_CLASS=y ++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y ++CONFIG_USB_GSPCA=y ++CONFIG_USB_M5602=y ++CONFIG_USB_GSPCA_CONEX=y ++CONFIG_USB_GSPCA_ETOMS=y ++CONFIG_USB_GSPCA_FINEPIX=y ++CONFIG_USB_GSPCA_MARS=y ++CONFIG_USB_GSPCA_OV519=y ++CONFIG_USB_GSPCA_PAC207=y ++CONFIG_USB_GSPCA_PAC7311=y ++CONFIG_USB_GSPCA_SONIXB=y ++CONFIG_USB_GSPCA_SONIXJ=y ++CONFIG_USB_GSPCA_SPCA500=y ++CONFIG_USB_GSPCA_SPCA501=y ++CONFIG_USB_GSPCA_SPCA505=y ++CONFIG_USB_GSPCA_SPCA506=y ++CONFIG_USB_GSPCA_SPCA508=y ++CONFIG_USB_GSPCA_SPCA561=y ++CONFIG_USB_GSPCA_STK014=y ++CONFIG_USB_GSPCA_SUNPLUS=y ++CONFIG_USB_GSPCA_T613=y ++CONFIG_USB_GSPCA_TV8532=y ++CONFIG_USB_GSPCA_VC032X=y ++CONFIG_USB_GSPCA_ZC3XX=y ++CONFIG_VIDEO_PVRUSB2=y ++CONFIG_VIDEO_PVRUSB2_SYSFS=y ++# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set ++CONFIG_VIDEO_EM28XX=y ++# CONFIG_VIDEO_EM28XX_ALSA is not set ++CONFIG_VIDEO_USBVISION=y ++CONFIG_USB_ET61X251=y ++CONFIG_USB_SN9C102=y ++CONFIG_USB_ZC0301=y ++CONFIG_USB_ZR364XX=y ++CONFIG_USB_STKWEBCAM=y ++CONFIG_USB_S2255=y ++CONFIG_VIDEO_SAMSUNG=y ++ ++# ++# FIMC configurations ++# ++CONFIG_VIDEO_FIMC=y ++CONFIG_VIDEO_FIMC_DEBUG=y ++# CONFIG_S5K4BA is not set ++# CONFIG_S5K3BA is not set ++CONFIG_OV965X=y ++CONFIG_OV965X_VGA=y ++# CONFIG_OV965X_QVGA is not set ++# CONFIG_OV965X_SVGA is not set ++# CONFIG_OV965X_SXGA is not set ++CONFIG_VIDEO_FIMC_CAM_CH=0 ++CONFIG_VIDEO_FIMC_CAM_RESET=1 ++CONFIG_VIDEO_POST=y ++CONFIG_VIDEO_MFC10=y ++CONFIG_VIDEO_MFC_DEBUG=y ++CONFIG_VIDEO_JPEG=y ++CONFIG_VIDEO_TV=y ++CONFIG_VIDEO_ROTATOR=y ++CONFIG_VIDEO_G2D=y ++CONFIG_VIDEO_G3D=y ++CONFIG_VIDEO_CMM=y ++ ++# ++# Reserved memory configurations ++# ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC=15360 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_POST=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC=6144 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_CMM=8192 ++# CONFIG_RADIO_ADAPTERS is not set ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++CONFIG_FB_S3C=y ++# CONFIG_FB_S3C_TFT480272 is not set ++CONFIG_FB_S3C_TFT800480=y ++# CONFIG_FB_S3C_T240320 is not set ++# CONFIG_FB_S3C_TFT640480 is not set ++# CONFIG_FB_S3C_VGA1024768 is not set ++# CONFIG_FB_S3C_VGA800600 is not set ++# CONFIG_FB_S3C_VGA640480 is not set ++# CONFIG_FB_S3C_EZVGA800600 is not set ++CONFIG_FB_S3C_BPP=y ++# CONFIG_FB_S3C_BPP_8 is not set ++CONFIG_FB_S3C_BPP_16=y ++# CONFIG_FB_S3C_BPP_24 is not set ++# CONFIG_FB_S3C_BPP_28 is not set ++# CONFIG_FB_S3C_BPP_32 is not set ++CONFIG_FB_S3C_NUM=4 ++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set ++CONFIG_FB_S3C_DOUBLE_BUFFERING=y ++# CONFIG_FB_S1D13XXX is not set ++CONFIG_BACKLIGHT_FRIENDLY_ARM=y ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_LOGO_LINUX_CLUT224=y ++# CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224 is not set ++CONFIG_SOUND=y ++CONFIG_SOUND_OSS_CORE=y ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++CONFIG_SND_OSSEMUL=y ++CONFIG_SND_MIXER_OSS=y ++CONFIG_SND_PCM_OSS=y ++CONFIG_SND_PCM_OSS_PLUGINS=y ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_VMASTER=y ++CONFIG_SND_AC97_CODEC=y ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++# CONFIG_SND_AC97_POWER_SAVE is not set ++CONFIG_SND_ARM=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_CAIAQ is not set ++CONFIG_SND_SOC=y ++CONFIG_SND_SOC_AC97_BUS=y ++ ++# ++# SoC Audio for the Samsung S3C ++# ++CONFIG_SND_S3C64XX_SOC=y ++CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713=y ++# CONFIG_SOUND_WM9713_INPUT_STREAM_LINE is not set ++CONFIG_SOUND_WM9713_INPUT_STREAM_MIC=y ++CONFIG_SND_S3C6410_SOC_AC97=y ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8580 is not set ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990 is not set ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_S5M8751 is not set ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM9713=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_AC97_BUS=y ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_BRIGHT=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_DELL=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++CONFIG_USB_DEBUG=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++CONFIG_USB_DEVICE_CLASS=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_S3C_OTG_HOST is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_DPCM is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++CONFIG_USB_SERIAL=y ++# CONFIG_USB_SERIAL_CONSOLE is not set ++# CONFIG_USB_EZUSB is not set ++# CONFIG_USB_SERIAL_GENERIC is not set ++# CONFIG_USB_SERIAL_AIRCABLE is not set ++# CONFIG_USB_SERIAL_ARK3116 is not set ++# CONFIG_USB_SERIAL_BELKIN is not set ++# CONFIG_USB_SERIAL_CH341 is not set ++# CONFIG_USB_SERIAL_WHITEHEAT is not set ++# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set ++# CONFIG_USB_SERIAL_CP2101 is not set ++# CONFIG_USB_SERIAL_CYPRESS_M8 is not set ++# CONFIG_USB_SERIAL_EMPEG is not set ++# CONFIG_USB_SERIAL_FTDI_SIO is not set ++# CONFIG_USB_SERIAL_FUNSOFT is not set ++# CONFIG_USB_SERIAL_VISOR is not set ++# CONFIG_USB_SERIAL_IPAQ is not set ++# CONFIG_USB_SERIAL_IR is not set ++# CONFIG_USB_SERIAL_EDGEPORT is not set ++# CONFIG_USB_SERIAL_EDGEPORT_TI is not set ++# CONFIG_USB_SERIAL_GARMIN is not set ++# CONFIG_USB_SERIAL_IPW is not set ++# CONFIG_USB_SERIAL_IUU is not set ++# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set ++# CONFIG_USB_SERIAL_KEYSPAN is not set ++# CONFIG_USB_SERIAL_KLSI is not set ++# CONFIG_USB_SERIAL_KOBIL_SCT is not set ++# CONFIG_USB_SERIAL_MCT_U232 is not set ++# CONFIG_USB_SERIAL_MOS7720 is not set ++# CONFIG_USB_SERIAL_MOS7840 is not set ++# CONFIG_USB_SERIAL_MOTOROLA is not set ++# CONFIG_USB_SERIAL_NAVMAN is not set ++CONFIG_USB_SERIAL_PL2303=y ++# CONFIG_USB_SERIAL_OTI6858 is not set ++# CONFIG_USB_SERIAL_SPCP8X5 is not set ++# CONFIG_USB_SERIAL_HP4X is not set ++# CONFIG_USB_SERIAL_SAFE is not set ++# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set ++# CONFIG_USB_SERIAL_TI is not set ++# CONFIG_USB_SERIAL_CYBERJACK is not set ++# CONFIG_USB_SERIAL_XIRCOM is not set ++# CONFIG_USB_SERIAL_OPTION is not set ++# CONFIG_USB_SERIAL_OMNINET is not set ++# CONFIG_USB_SERIAL_DEBUG is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++CONFIG_USB_GADGET_S3C_OTGD=y ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++ ++# ++# NOTE: S3C OTG device role enables the controller driver below ++# ++CONFIG_USB_S3C_OTGD=y ++CONFIG_USB_GADGET_S3C_OTGD_DMA_MODE=y ++# CONFIG_USB_GADGET_S3C_OTGD_SLAVE_MODE is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FILE_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++CONFIG_SDIO_UART=y ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_S3C=y ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_NEW_LEDS is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_DRV_S3C=y ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++# CONFIG_EXT2_FS is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++CONFIG_GENERIC_ACL=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=936 ++CONFIG_FAT_DEFAULT_IOCHARSET="utf8" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_YAFFS_FS=y ++CONFIG_YAFFS_YAFFS1=y ++# CONFIG_YAFFS_9BYTE_TAGS is not set ++# CONFIG_YAFFS_DOES_ECC is not set ++CONFIG_YAFFS_YAFFS2=y ++CONFIG_YAFFS_AUTO_YAFFS2=y ++# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set ++# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set ++# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set ++CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y ++# CONFIG_JFFS2_FS is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_XATTR=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++CONFIG_UBIFS_FS_ZLIB=y ++# CONFIG_UBIFS_FS_DEBUG is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++# CONFIG_NFS_V3_ACL is not set ++# CONFIG_NFS_V4 is not set ++CONFIG_ROOT_NFS=y ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++CONFIG_NLS_CODEPAGE_936=y ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_PI_LIST=y ++# CONFIG_RT_MUTEX_TESTER is not set ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++CONFIG_DEBUG_SPINLOCK_SLEEP=y ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_DEBUG_USER=y ++CONFIG_DEBUG_ERRORS=y ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++CONFIG_DEBUG_S3C_PORT=y ++CONFIG_DEBUG_S3C_UART=0 ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++# CONFIG_CRYPTO_MANAGER is not set ++# CONFIG_CRYPTO_MANAGER2 is not set ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++# CONFIG_CRYPTO_MD5 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_DMA=y +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/config_mini6410_ezvga linux-2.6.28.6/config_mini6410_ezvga +--- linux-2.6.28/config_mini6410_ezvga 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/config_mini6410_ezvga 2010-07-20 12:04:15.000000000 +0200 +@@ -0,0 +1,1741 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28.6 ++# Tue Jul 20 18:03:47 2010 ++# ++CONFIG_ARM=y ++# CONFIG_HAVE_PWM is not set ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++CONFIG_NO_IOPORT=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_ZONE_DMA=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="-FriendlyARM" ++CONFIG_LOCALVERSION_AUTO=y ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="scripts/FriendlyARM.cpio" ++CONFIG_INITRAMFS_ROOT_UID=0 ++CONFIG_INITRAMFS_ROOT_GID=0 ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_COMPAT_BRK=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++# CONFIG_LBD is not set ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_LSF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++# CONFIG_IOSCHED_AS is not set ++# CONFIG_IOSCHED_DEADLINE is not set ++# CONFIG_IOSCHED_CFQ is not set ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++# CONFIG_DEFAULT_CFQ is not set ++CONFIG_DEFAULT_NOOP=y ++CONFIG_DEFAULT_IOSCHED="noop" ++CONFIG_CLASSIC_RCU=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++CONFIG_ARCH_S3C64XX=y ++# CONFIG_ARCH_S5P64XX is not set ++# CONFIG_ARCH_S5PC1XX is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_PLAT_S3C64XX=y ++CONFIG_CPU_S3C6400_INIT=y ++CONFIG_CPU_S3C6400_CLOCK=y ++CONFIG_S3C64XX_SETUP_I2C0=y ++# CONFIG_S3C64XX_ADC is not set ++CONFIG_S3C64XX_DEV_FIMC0=y ++CONFIG_S3C64XX_DEV_FIMC1=y ++CONFIG_S3C64XX_SETUP_FIMC0=y ++CONFIG_S3C64XX_SETUP_FIMC1=y ++# CONFIG_S3C6410_PWM is not set ++CONFIG_NONE_PWM=y ++CONFIG_PLAT_S3C=y ++ ++# ++# Boot options ++# ++# CONFIG_S3C_BOOT_WATCHDOG is not set ++CONFIG_S3C_BOOT_ERROR_RESET=y ++ ++# ++# Power management ++# ++CONFIG_S3C_LOWLEVEL_UART_PORT=0 ++# CONFIG_SPLIT_ROOT_FILESYSTEM is not set ++CONFIG_S3C_GPIO_SPACE=0 ++CONFIG_S3C_GPIO_TRACK=y ++CONFIG_S3C_GPIO_PULL_UPDOWN=y ++CONFIG_S3C_GPIO_CFG_S3C24XX=y ++CONFIG_S3C_GPIO_CFG_S3C64XX=y ++CONFIG_S3C_DEV_HSMMC=y ++CONFIG_S3C_DEV_HSMMC1=y ++CONFIG_S3C_DEV_HSMMC2=y ++CONFIG_S3C_DMA_PL080=y ++CONFIG_CPU_S3C6410=y ++CONFIG_S3C6410_SETUP_SDHCI=y ++CONFIG_MACH_SMDK6410=y ++ ++# ++# SMDK6410 MMC/SD slot setup ++# ++CONFIG_SMDK6410_SD_CH0=y ++# CONFIG_SMDK6410_SD_CH1 is not set ++# CONFIG_SMDK6410_SD_CH2 is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_THUMB is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++CONFIG_ARM_VIC=y ++CONFIG_DMABOUNCE=y ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=200 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++# CONFIG_UNEVICTABLE_LRU is not set ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_CMDLINE="" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_FREQ is not set ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_FPE_NWFPE=y ++# CONFIG_FPE_NWFPE_XP is not set ++# CONFIG_FPE_FASTFPE is not set ++# CONFIG_VFP is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++ ++# ++# Power management options ++# ++# CONFIG_PM is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_PACKET is not set ++CONFIG_UNIX=y ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_BOOTP=y ++CONFIG_IP_PNP_RARP=y ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_CONCAT is not set ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_VERIFY_WRITE is not set ++# CONFIG_MTD_NAND_ECC_SMC is not set ++# CONFIG_MTD_NAND_MUSEUM_IDS is not set ++# CONFIG_MTD_NAND_GPIO is not set ++CONFIG_MTD_NAND_IDS=y ++CONFIG_MTD_NAND_S3C=y ++# CONFIG_MTD_NAND_S3C_DEBUG is not set ++CONFIG_MTD_NAND_S3C_HWECC=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ALAUDA is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# UBI - Unsorted block images ++# ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_RESERVE=1 ++# CONFIG_MTD_UBI_GLUEBI is not set ++ ++# ++# UBI debugging options ++# ++# CONFIG_MTD_UBI_DEBUG is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++# CONFIG_BLK_DEV_RAM is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++# CONFIG_SCSI_MULTI_LUN is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_PHYLIB is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_AX88796 is not set ++# CONFIG_SMC91X is not set ++CONFIG_DM9000=y ++CONFIG_DM9000_DEBUGLEVEL=4 ++# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set ++# CONFIG_SMC911X is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=800 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=600 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++# CONFIG_TOUCHSCREEN_S3C is not set ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_WM97XX is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++# CONFIG_DEVKMEM is not set ++CONFIG_LEDS_MINI6410=y ++CONFIG_MINI6410_HELLO_MODULE=m ++CONFIG_MINI6410_BUTTONS=y ++CONFIG_MINI6410_BUZZER=y ++# CONFIG_MINI6410_ADC is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_SAMSUNG=y ++CONFIG_SERIAL_SAMSUNG_UARTS=4 ++# CONFIG_SERIAL_SAMSUNG_DEBUG is not set ++CONFIG_SERIAL_SAMSUNG_CONSOLE=y ++CONFIG_SERIAL_S3C6400=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_S3C_MEM is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_HELPER_AUTO is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++CONFIG_I2C_S3C2410=y ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_AT24 is not set ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++# CONFIG_DEBUG_GPIO is not set ++# CONFIG_GPIO_SYSFS is not set ++ ++# ++# Memory mapped GPIO expanders: ++# ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++CONFIG_S3C2410_WATCHDOG=y ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_UCB1400_CORE is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2_COMMON=y ++# CONFIG_VIDEO_ALLOW_V4L1 is not set ++CONFIG_VIDEO_V4L1_COMPAT=y ++# CONFIG_DVB_CORE is not set ++CONFIG_VIDEO_MEDIA=y ++ ++# ++# Multimedia drivers ++# ++# CONFIG_MEDIA_ATTACH is not set ++CONFIG_MEDIA_TUNER=y ++# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set ++CONFIG_MEDIA_TUNER_SIMPLE=y ++CONFIG_MEDIA_TUNER_TDA8290=y ++CONFIG_MEDIA_TUNER_TDA9887=y ++CONFIG_MEDIA_TUNER_TEA5761=y ++CONFIG_MEDIA_TUNER_TEA5767=y ++CONFIG_MEDIA_TUNER_MT20XX=y ++CONFIG_MEDIA_TUNER_XC2028=y ++CONFIG_MEDIA_TUNER_XC5000=y ++CONFIG_VIDEO_V4L2=y ++CONFIG_VIDEOBUF_GEN=y ++CONFIG_VIDEOBUF_VMALLOC=y ++CONFIG_VIDEO_IR=y ++CONFIG_VIDEO_TVEEPROM=y ++CONFIG_VIDEO_TUNER=y ++CONFIG_VIDEO_CAPTURE_DRIVERS=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++CONFIG_VIDEO_FIXED_MINOR_RANGES=y ++# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set ++CONFIG_VIDEO_IR_I2C=y ++ ++# ++# Encoders/decoders and other helper chips ++# ++ ++# ++# Audio decoders ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TDA9875 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++CONFIG_VIDEO_MSP3400=y ++# CONFIG_VIDEO_CS5345 is not set ++CONFIG_VIDEO_CS53L32A=y ++# CONFIG_VIDEO_M52790 is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++CONFIG_VIDEO_WM8775=y ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_TCM825X is not set ++CONFIG_VIDEO_SAA711X=y ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++ ++# ++# Video and audio decoders ++# ++CONFIG_VIDEO_CX25840=y ++ ++# ++# MPEG video encoders ++# ++CONFIG_VIDEO_CX2341X=y ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++# CONFIG_VIDEO_VIVI is not set ++# CONFIG_VIDEO_SAA5246A is not set ++# CONFIG_VIDEO_SAA5249 is not set ++# CONFIG_SOC_CAMERA is not set ++CONFIG_V4L_USB_DRIVERS=y ++CONFIG_USB_VIDEO_CLASS=y ++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y ++CONFIG_USB_GSPCA=y ++CONFIG_USB_M5602=y ++CONFIG_USB_GSPCA_CONEX=y ++CONFIG_USB_GSPCA_ETOMS=y ++CONFIG_USB_GSPCA_FINEPIX=y ++CONFIG_USB_GSPCA_MARS=y ++CONFIG_USB_GSPCA_OV519=y ++CONFIG_USB_GSPCA_PAC207=y ++CONFIG_USB_GSPCA_PAC7311=y ++CONFIG_USB_GSPCA_SONIXB=y ++CONFIG_USB_GSPCA_SONIXJ=y ++CONFIG_USB_GSPCA_SPCA500=y ++CONFIG_USB_GSPCA_SPCA501=y ++CONFIG_USB_GSPCA_SPCA505=y ++CONFIG_USB_GSPCA_SPCA506=y ++CONFIG_USB_GSPCA_SPCA508=y ++CONFIG_USB_GSPCA_SPCA561=y ++CONFIG_USB_GSPCA_STK014=y ++CONFIG_USB_GSPCA_SUNPLUS=y ++CONFIG_USB_GSPCA_T613=y ++CONFIG_USB_GSPCA_TV8532=y ++CONFIG_USB_GSPCA_VC032X=y ++CONFIG_USB_GSPCA_ZC3XX=y ++CONFIG_VIDEO_PVRUSB2=y ++CONFIG_VIDEO_PVRUSB2_SYSFS=y ++# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set ++CONFIG_VIDEO_EM28XX=y ++# CONFIG_VIDEO_EM28XX_ALSA is not set ++CONFIG_VIDEO_USBVISION=y ++CONFIG_USB_ET61X251=y ++CONFIG_USB_SN9C102=y ++CONFIG_USB_ZC0301=y ++CONFIG_USB_ZR364XX=y ++CONFIG_USB_STKWEBCAM=y ++CONFIG_USB_S2255=y ++CONFIG_VIDEO_SAMSUNG=y ++ ++# ++# FIMC configurations ++# ++CONFIG_VIDEO_FIMC=y ++CONFIG_VIDEO_FIMC_DEBUG=y ++# CONFIG_S5K4BA is not set ++# CONFIG_S5K3BA is not set ++CONFIG_OV965X=y ++CONFIG_OV965X_VGA=y ++# CONFIG_OV965X_QVGA is not set ++# CONFIG_OV965X_SVGA is not set ++# CONFIG_OV965X_SXGA is not set ++CONFIG_VIDEO_FIMC_CAM_CH=0 ++CONFIG_VIDEO_FIMC_CAM_RESET=1 ++CONFIG_VIDEO_POST=y ++CONFIG_VIDEO_MFC10=y ++CONFIG_VIDEO_MFC_DEBUG=y ++CONFIG_VIDEO_JPEG=y ++CONFIG_VIDEO_TV=y ++CONFIG_VIDEO_ROTATOR=y ++CONFIG_VIDEO_G2D=y ++CONFIG_VIDEO_G3D=y ++CONFIG_VIDEO_CMM=y ++ ++# ++# Reserved memory configurations ++# ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC=15360 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_POST=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC=6144 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_CMM=8192 ++# CONFIG_RADIO_ADAPTERS is not set ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++CONFIG_FB_S3C=y ++# CONFIG_FB_S3C_TFT480272 is not set ++# CONFIG_FB_S3C_TFT800480 is not set ++# CONFIG_FB_S3C_T240320 is not set ++# CONFIG_FB_S3C_TFT640480 is not set ++# CONFIG_FB_S3C_VGA1024768 is not set ++# CONFIG_FB_S3C_VGA800600 is not set ++# CONFIG_FB_S3C_VGA640480 is not set ++CONFIG_FB_S3C_EZVGA800600=y ++CONFIG_FB_S3C_BPP=y ++# CONFIG_FB_S3C_BPP_8 is not set ++CONFIG_FB_S3C_BPP_16=y ++# CONFIG_FB_S3C_BPP_24 is not set ++# CONFIG_FB_S3C_BPP_28 is not set ++# CONFIG_FB_S3C_BPP_32 is not set ++CONFIG_FB_S3C_NUM=4 ++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set ++CONFIG_FB_S3C_DOUBLE_BUFFERING=y ++# CONFIG_FB_S1D13XXX is not set ++CONFIG_BACKLIGHT_FRIENDLY_ARM=y ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_LOGO_LINUX_CLUT224=y ++# CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224 is not set ++CONFIG_SOUND=y ++CONFIG_SOUND_OSS_CORE=y ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++CONFIG_SND_OSSEMUL=y ++CONFIG_SND_MIXER_OSS=y ++CONFIG_SND_PCM_OSS=y ++CONFIG_SND_PCM_OSS_PLUGINS=y ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_VMASTER=y ++CONFIG_SND_AC97_CODEC=y ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++# CONFIG_SND_AC97_POWER_SAVE is not set ++CONFIG_SND_ARM=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_CAIAQ is not set ++CONFIG_SND_SOC=y ++CONFIG_SND_SOC_AC97_BUS=y ++ ++# ++# SoC Audio for the Samsung S3C ++# ++CONFIG_SND_S3C64XX_SOC=y ++CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713=y ++# CONFIG_SOUND_WM9713_INPUT_STREAM_LINE is not set ++CONFIG_SOUND_WM9713_INPUT_STREAM_MIC=y ++CONFIG_SND_S3C6410_SOC_AC97=y ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8580 is not set ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990 is not set ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_S5M8751 is not set ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM9713=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_AC97_BUS=y ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_BRIGHT=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_DELL=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++CONFIG_USB_DEBUG=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++CONFIG_USB_DEVICE_CLASS=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_S3C_OTG_HOST is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_DPCM is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++CONFIG_USB_SERIAL=y ++# CONFIG_USB_SERIAL_CONSOLE is not set ++# CONFIG_USB_EZUSB is not set ++# CONFIG_USB_SERIAL_GENERIC is not set ++# CONFIG_USB_SERIAL_AIRCABLE is not set ++# CONFIG_USB_SERIAL_ARK3116 is not set ++# CONFIG_USB_SERIAL_BELKIN is not set ++# CONFIG_USB_SERIAL_CH341 is not set ++# CONFIG_USB_SERIAL_WHITEHEAT is not set ++# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set ++# CONFIG_USB_SERIAL_CP2101 is not set ++# CONFIG_USB_SERIAL_CYPRESS_M8 is not set ++# CONFIG_USB_SERIAL_EMPEG is not set ++# CONFIG_USB_SERIAL_FTDI_SIO is not set ++# CONFIG_USB_SERIAL_FUNSOFT is not set ++# CONFIG_USB_SERIAL_VISOR is not set ++# CONFIG_USB_SERIAL_IPAQ is not set ++# CONFIG_USB_SERIAL_IR is not set ++# CONFIG_USB_SERIAL_EDGEPORT is not set ++# CONFIG_USB_SERIAL_EDGEPORT_TI is not set ++# CONFIG_USB_SERIAL_GARMIN is not set ++# CONFIG_USB_SERIAL_IPW is not set ++# CONFIG_USB_SERIAL_IUU is not set ++# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set ++# CONFIG_USB_SERIAL_KEYSPAN is not set ++# CONFIG_USB_SERIAL_KLSI is not set ++# CONFIG_USB_SERIAL_KOBIL_SCT is not set ++# CONFIG_USB_SERIAL_MCT_U232 is not set ++# CONFIG_USB_SERIAL_MOS7720 is not set ++# CONFIG_USB_SERIAL_MOS7840 is not set ++# CONFIG_USB_SERIAL_MOTOROLA is not set ++# CONFIG_USB_SERIAL_NAVMAN is not set ++CONFIG_USB_SERIAL_PL2303=y ++# CONFIG_USB_SERIAL_OTI6858 is not set ++# CONFIG_USB_SERIAL_SPCP8X5 is not set ++# CONFIG_USB_SERIAL_HP4X is not set ++# CONFIG_USB_SERIAL_SAFE is not set ++# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set ++# CONFIG_USB_SERIAL_TI is not set ++# CONFIG_USB_SERIAL_CYBERJACK is not set ++# CONFIG_USB_SERIAL_XIRCOM is not set ++# CONFIG_USB_SERIAL_OPTION is not set ++# CONFIG_USB_SERIAL_OMNINET is not set ++# CONFIG_USB_SERIAL_DEBUG is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++CONFIG_USB_GADGET_S3C_OTGD=y ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++ ++# ++# NOTE: S3C OTG device role enables the controller driver below ++# ++CONFIG_USB_S3C_OTGD=y ++CONFIG_USB_GADGET_S3C_OTGD_DMA_MODE=y ++# CONFIG_USB_GADGET_S3C_OTGD_SLAVE_MODE is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FILE_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++CONFIG_SDIO_UART=y ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_S3C=y ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_NEW_LEDS is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_DRV_S3C=y ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++# CONFIG_EXT2_FS is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++CONFIG_GENERIC_ACL=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=936 ++CONFIG_FAT_DEFAULT_IOCHARSET="utf8" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_YAFFS_FS=y ++CONFIG_YAFFS_YAFFS1=y ++# CONFIG_YAFFS_9BYTE_TAGS is not set ++# CONFIG_YAFFS_DOES_ECC is not set ++CONFIG_YAFFS_YAFFS2=y ++CONFIG_YAFFS_AUTO_YAFFS2=y ++# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set ++# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set ++# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set ++CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y ++# CONFIG_JFFS2_FS is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_XATTR=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++CONFIG_UBIFS_FS_ZLIB=y ++# CONFIG_UBIFS_FS_DEBUG is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++# CONFIG_NFS_V3_ACL is not set ++# CONFIG_NFS_V4 is not set ++CONFIG_ROOT_NFS=y ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++CONFIG_NLS_CODEPAGE_936=y ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_PI_LIST=y ++# CONFIG_RT_MUTEX_TESTER is not set ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++CONFIG_DEBUG_SPINLOCK_SLEEP=y ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_DEBUG_USER=y ++CONFIG_DEBUG_ERRORS=y ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++CONFIG_DEBUG_S3C_PORT=y ++CONFIG_DEBUG_S3C_UART=0 ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++# CONFIG_CRYPTO_MANAGER is not set ++# CONFIG_CRYPTO_MANAGER2 is not set ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++# CONFIG_CRYPTO_MD5 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_DMA=y +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/config_mini6410_l80 linux-2.6.28.6/config_mini6410_l80 +--- linux-2.6.28/config_mini6410_l80 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/config_mini6410_l80 2010-07-20 11:55:20.000000000 +0200 +@@ -0,0 +1,1742 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28.6 ++# Tue Jul 20 17:55:10 2010 ++# ++CONFIG_ARM=y ++# CONFIG_HAVE_PWM is not set ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++CONFIG_NO_IOPORT=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_ZONE_DMA=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="-FriendlyARM" ++CONFIG_LOCALVERSION_AUTO=y ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="scripts/FriendlyARM.cpio" ++CONFIG_INITRAMFS_ROOT_UID=0 ++CONFIG_INITRAMFS_ROOT_GID=0 ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_COMPAT_BRK=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++# CONFIG_LBD is not set ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_LSF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++# CONFIG_IOSCHED_AS is not set ++# CONFIG_IOSCHED_DEADLINE is not set ++# CONFIG_IOSCHED_CFQ is not set ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++# CONFIG_DEFAULT_CFQ is not set ++CONFIG_DEFAULT_NOOP=y ++CONFIG_DEFAULT_IOSCHED="noop" ++CONFIG_CLASSIC_RCU=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++CONFIG_ARCH_S3C64XX=y ++# CONFIG_ARCH_S5P64XX is not set ++# CONFIG_ARCH_S5PC1XX is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_PLAT_S3C64XX=y ++CONFIG_CPU_S3C6400_INIT=y ++CONFIG_CPU_S3C6400_CLOCK=y ++CONFIG_S3C64XX_SETUP_I2C0=y ++# CONFIG_S3C64XX_ADC is not set ++CONFIG_S3C64XX_DEV_FIMC0=y ++CONFIG_S3C64XX_DEV_FIMC1=y ++CONFIG_S3C64XX_SETUP_FIMC0=y ++CONFIG_S3C64XX_SETUP_FIMC1=y ++# CONFIG_S3C6410_PWM is not set ++CONFIG_NONE_PWM=y ++CONFIG_PLAT_S3C=y ++ ++# ++# Boot options ++# ++# CONFIG_S3C_BOOT_WATCHDOG is not set ++CONFIG_S3C_BOOT_ERROR_RESET=y ++ ++# ++# Power management ++# ++CONFIG_S3C_LOWLEVEL_UART_PORT=0 ++# CONFIG_SPLIT_ROOT_FILESYSTEM is not set ++CONFIG_S3C_GPIO_SPACE=0 ++CONFIG_S3C_GPIO_TRACK=y ++CONFIG_S3C_GPIO_PULL_UPDOWN=y ++CONFIG_S3C_GPIO_CFG_S3C24XX=y ++CONFIG_S3C_GPIO_CFG_S3C64XX=y ++CONFIG_S3C_DEV_HSMMC=y ++CONFIG_S3C_DEV_HSMMC1=y ++CONFIG_S3C_DEV_HSMMC2=y ++CONFIG_S3C_DMA_PL080=y ++CONFIG_CPU_S3C6410=y ++CONFIG_S3C6410_SETUP_SDHCI=y ++CONFIG_MACH_SMDK6410=y ++ ++# ++# SMDK6410 MMC/SD slot setup ++# ++CONFIG_SMDK6410_SD_CH0=y ++# CONFIG_SMDK6410_SD_CH1 is not set ++# CONFIG_SMDK6410_SD_CH2 is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_THUMB is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++CONFIG_ARM_VIC=y ++CONFIG_DMABOUNCE=y ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=200 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++# CONFIG_UNEVICTABLE_LRU is not set ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_CMDLINE="" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_FREQ is not set ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_FPE_NWFPE=y ++# CONFIG_FPE_NWFPE_XP is not set ++# CONFIG_FPE_FASTFPE is not set ++# CONFIG_VFP is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++ ++# ++# Power management options ++# ++# CONFIG_PM is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_PACKET is not set ++CONFIG_UNIX=y ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_BOOTP=y ++CONFIG_IP_PNP_RARP=y ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_CONCAT is not set ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_VERIFY_WRITE is not set ++# CONFIG_MTD_NAND_ECC_SMC is not set ++# CONFIG_MTD_NAND_MUSEUM_IDS is not set ++# CONFIG_MTD_NAND_GPIO is not set ++CONFIG_MTD_NAND_IDS=y ++CONFIG_MTD_NAND_S3C=y ++# CONFIG_MTD_NAND_S3C_DEBUG is not set ++CONFIG_MTD_NAND_S3C_HWECC=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ALAUDA is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# UBI - Unsorted block images ++# ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_RESERVE=1 ++# CONFIG_MTD_UBI_GLUEBI is not set ++ ++# ++# UBI debugging options ++# ++# CONFIG_MTD_UBI_DEBUG is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++# CONFIG_BLK_DEV_RAM is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++# CONFIG_SCSI_MULTI_LUN is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_PHYLIB is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_AX88796 is not set ++# CONFIG_SMC91X is not set ++CONFIG_DM9000=y ++CONFIG_DM9000_DEBUGLEVEL=4 ++# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set ++# CONFIG_SMC911X is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=640 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_S3C=y ++# CONFIG_TOUCHSCREEN_NEW is not set ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_WM97XX is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++# CONFIG_DEVKMEM is not set ++CONFIG_LEDS_MINI6410=y ++CONFIG_MINI6410_HELLO_MODULE=m ++CONFIG_MINI6410_BUTTONS=y ++CONFIG_MINI6410_BUZZER=y ++# CONFIG_MINI6410_ADC is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_SAMSUNG=y ++CONFIG_SERIAL_SAMSUNG_UARTS=4 ++# CONFIG_SERIAL_SAMSUNG_DEBUG is not set ++CONFIG_SERIAL_SAMSUNG_CONSOLE=y ++CONFIG_SERIAL_S3C6400=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_S3C_MEM is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_HELPER_AUTO is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++CONFIG_I2C_S3C2410=y ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_AT24 is not set ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++# CONFIG_DEBUG_GPIO is not set ++# CONFIG_GPIO_SYSFS is not set ++ ++# ++# Memory mapped GPIO expanders: ++# ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++CONFIG_S3C2410_WATCHDOG=y ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_UCB1400_CORE is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2_COMMON=y ++# CONFIG_VIDEO_ALLOW_V4L1 is not set ++CONFIG_VIDEO_V4L1_COMPAT=y ++# CONFIG_DVB_CORE is not set ++CONFIG_VIDEO_MEDIA=y ++ ++# ++# Multimedia drivers ++# ++# CONFIG_MEDIA_ATTACH is not set ++CONFIG_MEDIA_TUNER=y ++# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set ++CONFIG_MEDIA_TUNER_SIMPLE=y ++CONFIG_MEDIA_TUNER_TDA8290=y ++CONFIG_MEDIA_TUNER_TDA9887=y ++CONFIG_MEDIA_TUNER_TEA5761=y ++CONFIG_MEDIA_TUNER_TEA5767=y ++CONFIG_MEDIA_TUNER_MT20XX=y ++CONFIG_MEDIA_TUNER_XC2028=y ++CONFIG_MEDIA_TUNER_XC5000=y ++CONFIG_VIDEO_V4L2=y ++CONFIG_VIDEOBUF_GEN=y ++CONFIG_VIDEOBUF_VMALLOC=y ++CONFIG_VIDEO_IR=y ++CONFIG_VIDEO_TVEEPROM=y ++CONFIG_VIDEO_TUNER=y ++CONFIG_VIDEO_CAPTURE_DRIVERS=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++CONFIG_VIDEO_FIXED_MINOR_RANGES=y ++# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set ++CONFIG_VIDEO_IR_I2C=y ++ ++# ++# Encoders/decoders and other helper chips ++# ++ ++# ++# Audio decoders ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TDA9875 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++CONFIG_VIDEO_MSP3400=y ++# CONFIG_VIDEO_CS5345 is not set ++CONFIG_VIDEO_CS53L32A=y ++# CONFIG_VIDEO_M52790 is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++CONFIG_VIDEO_WM8775=y ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_TCM825X is not set ++CONFIG_VIDEO_SAA711X=y ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++ ++# ++# Video and audio decoders ++# ++CONFIG_VIDEO_CX25840=y ++ ++# ++# MPEG video encoders ++# ++CONFIG_VIDEO_CX2341X=y ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++# CONFIG_VIDEO_VIVI is not set ++# CONFIG_VIDEO_SAA5246A is not set ++# CONFIG_VIDEO_SAA5249 is not set ++# CONFIG_SOC_CAMERA is not set ++CONFIG_V4L_USB_DRIVERS=y ++CONFIG_USB_VIDEO_CLASS=y ++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y ++CONFIG_USB_GSPCA=y ++CONFIG_USB_M5602=y ++CONFIG_USB_GSPCA_CONEX=y ++CONFIG_USB_GSPCA_ETOMS=y ++CONFIG_USB_GSPCA_FINEPIX=y ++CONFIG_USB_GSPCA_MARS=y ++CONFIG_USB_GSPCA_OV519=y ++CONFIG_USB_GSPCA_PAC207=y ++CONFIG_USB_GSPCA_PAC7311=y ++CONFIG_USB_GSPCA_SONIXB=y ++CONFIG_USB_GSPCA_SONIXJ=y ++CONFIG_USB_GSPCA_SPCA500=y ++CONFIG_USB_GSPCA_SPCA501=y ++CONFIG_USB_GSPCA_SPCA505=y ++CONFIG_USB_GSPCA_SPCA506=y ++CONFIG_USB_GSPCA_SPCA508=y ++CONFIG_USB_GSPCA_SPCA561=y ++CONFIG_USB_GSPCA_STK014=y ++CONFIG_USB_GSPCA_SUNPLUS=y ++CONFIG_USB_GSPCA_T613=y ++CONFIG_USB_GSPCA_TV8532=y ++CONFIG_USB_GSPCA_VC032X=y ++CONFIG_USB_GSPCA_ZC3XX=y ++CONFIG_VIDEO_PVRUSB2=y ++CONFIG_VIDEO_PVRUSB2_SYSFS=y ++# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set ++CONFIG_VIDEO_EM28XX=y ++# CONFIG_VIDEO_EM28XX_ALSA is not set ++CONFIG_VIDEO_USBVISION=y ++CONFIG_USB_ET61X251=y ++CONFIG_USB_SN9C102=y ++CONFIG_USB_ZC0301=y ++CONFIG_USB_ZR364XX=y ++CONFIG_USB_STKWEBCAM=y ++CONFIG_USB_S2255=y ++CONFIG_VIDEO_SAMSUNG=y ++ ++# ++# FIMC configurations ++# ++CONFIG_VIDEO_FIMC=y ++CONFIG_VIDEO_FIMC_DEBUG=y ++# CONFIG_S5K4BA is not set ++# CONFIG_S5K3BA is not set ++CONFIG_OV965X=y ++CONFIG_OV965X_VGA=y ++# CONFIG_OV965X_QVGA is not set ++# CONFIG_OV965X_SVGA is not set ++# CONFIG_OV965X_SXGA is not set ++CONFIG_VIDEO_FIMC_CAM_CH=0 ++CONFIG_VIDEO_FIMC_CAM_RESET=1 ++CONFIG_VIDEO_POST=y ++CONFIG_VIDEO_MFC10=y ++CONFIG_VIDEO_MFC_DEBUG=y ++CONFIG_VIDEO_JPEG=y ++CONFIG_VIDEO_TV=y ++CONFIG_VIDEO_ROTATOR=y ++CONFIG_VIDEO_G2D=y ++CONFIG_VIDEO_G3D=y ++CONFIG_VIDEO_CMM=y ++ ++# ++# Reserved memory configurations ++# ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC=15360 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_POST=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC=6144 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_CMM=8192 ++# CONFIG_RADIO_ADAPTERS is not set ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++CONFIG_FB_S3C=y ++# CONFIG_FB_S3C_TFT480272 is not set ++# CONFIG_FB_S3C_TFT800480 is not set ++# CONFIG_FB_S3C_T240320 is not set ++CONFIG_FB_S3C_TFT640480=y ++# CONFIG_FB_S3C_VGA1024768 is not set ++# CONFIG_FB_S3C_VGA800600 is not set ++# CONFIG_FB_S3C_VGA640480 is not set ++# CONFIG_FB_S3C_EZVGA800600 is not set ++CONFIG_FB_S3C_BPP=y ++# CONFIG_FB_S3C_BPP_8 is not set ++CONFIG_FB_S3C_BPP_16=y ++# CONFIG_FB_S3C_BPP_24 is not set ++# CONFIG_FB_S3C_BPP_28 is not set ++# CONFIG_FB_S3C_BPP_32 is not set ++CONFIG_FB_S3C_NUM=4 ++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set ++CONFIG_FB_S3C_DOUBLE_BUFFERING=y ++# CONFIG_FB_S1D13XXX is not set ++CONFIG_BACKLIGHT_FRIENDLY_ARM=y ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_LOGO_LINUX_CLUT224=y ++# CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224 is not set ++CONFIG_SOUND=y ++CONFIG_SOUND_OSS_CORE=y ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++CONFIG_SND_OSSEMUL=y ++CONFIG_SND_MIXER_OSS=y ++CONFIG_SND_PCM_OSS=y ++CONFIG_SND_PCM_OSS_PLUGINS=y ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_VMASTER=y ++CONFIG_SND_AC97_CODEC=y ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++# CONFIG_SND_AC97_POWER_SAVE is not set ++CONFIG_SND_ARM=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_CAIAQ is not set ++CONFIG_SND_SOC=y ++CONFIG_SND_SOC_AC97_BUS=y ++ ++# ++# SoC Audio for the Samsung S3C ++# ++CONFIG_SND_S3C64XX_SOC=y ++CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713=y ++# CONFIG_SOUND_WM9713_INPUT_STREAM_LINE is not set ++CONFIG_SOUND_WM9713_INPUT_STREAM_MIC=y ++CONFIG_SND_S3C6410_SOC_AC97=y ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8580 is not set ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990 is not set ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_S5M8751 is not set ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM9713=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_AC97_BUS=y ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_BRIGHT=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_DELL=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++CONFIG_USB_DEBUG=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++CONFIG_USB_DEVICE_CLASS=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_S3C_OTG_HOST is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_DPCM is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++CONFIG_USB_SERIAL=y ++# CONFIG_USB_SERIAL_CONSOLE is not set ++# CONFIG_USB_EZUSB is not set ++# CONFIG_USB_SERIAL_GENERIC is not set ++# CONFIG_USB_SERIAL_AIRCABLE is not set ++# CONFIG_USB_SERIAL_ARK3116 is not set ++# CONFIG_USB_SERIAL_BELKIN is not set ++# CONFIG_USB_SERIAL_CH341 is not set ++# CONFIG_USB_SERIAL_WHITEHEAT is not set ++# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set ++# CONFIG_USB_SERIAL_CP2101 is not set ++# CONFIG_USB_SERIAL_CYPRESS_M8 is not set ++# CONFIG_USB_SERIAL_EMPEG is not set ++# CONFIG_USB_SERIAL_FTDI_SIO is not set ++# CONFIG_USB_SERIAL_FUNSOFT is not set ++# CONFIG_USB_SERIAL_VISOR is not set ++# CONFIG_USB_SERIAL_IPAQ is not set ++# CONFIG_USB_SERIAL_IR is not set ++# CONFIG_USB_SERIAL_EDGEPORT is not set ++# CONFIG_USB_SERIAL_EDGEPORT_TI is not set ++# CONFIG_USB_SERIAL_GARMIN is not set ++# CONFIG_USB_SERIAL_IPW is not set ++# CONFIG_USB_SERIAL_IUU is not set ++# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set ++# CONFIG_USB_SERIAL_KEYSPAN is not set ++# CONFIG_USB_SERIAL_KLSI is not set ++# CONFIG_USB_SERIAL_KOBIL_SCT is not set ++# CONFIG_USB_SERIAL_MCT_U232 is not set ++# CONFIG_USB_SERIAL_MOS7720 is not set ++# CONFIG_USB_SERIAL_MOS7840 is not set ++# CONFIG_USB_SERIAL_MOTOROLA is not set ++# CONFIG_USB_SERIAL_NAVMAN is not set ++CONFIG_USB_SERIAL_PL2303=y ++# CONFIG_USB_SERIAL_OTI6858 is not set ++# CONFIG_USB_SERIAL_SPCP8X5 is not set ++# CONFIG_USB_SERIAL_HP4X is not set ++# CONFIG_USB_SERIAL_SAFE is not set ++# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set ++# CONFIG_USB_SERIAL_TI is not set ++# CONFIG_USB_SERIAL_CYBERJACK is not set ++# CONFIG_USB_SERIAL_XIRCOM is not set ++# CONFIG_USB_SERIAL_OPTION is not set ++# CONFIG_USB_SERIAL_OMNINET is not set ++# CONFIG_USB_SERIAL_DEBUG is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++CONFIG_USB_GADGET_S3C_OTGD=y ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++ ++# ++# NOTE: S3C OTG device role enables the controller driver below ++# ++CONFIG_USB_S3C_OTGD=y ++CONFIG_USB_GADGET_S3C_OTGD_DMA_MODE=y ++# CONFIG_USB_GADGET_S3C_OTGD_SLAVE_MODE is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FILE_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++CONFIG_SDIO_UART=y ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_S3C=y ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_NEW_LEDS is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_DRV_S3C=y ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++# CONFIG_EXT2_FS is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++CONFIG_GENERIC_ACL=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=936 ++CONFIG_FAT_DEFAULT_IOCHARSET="utf8" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_YAFFS_FS=y ++CONFIG_YAFFS_YAFFS1=y ++# CONFIG_YAFFS_9BYTE_TAGS is not set ++# CONFIG_YAFFS_DOES_ECC is not set ++CONFIG_YAFFS_YAFFS2=y ++CONFIG_YAFFS_AUTO_YAFFS2=y ++# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set ++# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set ++# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set ++CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y ++# CONFIG_JFFS2_FS is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_XATTR=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++CONFIG_UBIFS_FS_ZLIB=y ++# CONFIG_UBIFS_FS_DEBUG is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++# CONFIG_NFS_V3_ACL is not set ++# CONFIG_NFS_V4 is not set ++CONFIG_ROOT_NFS=y ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++CONFIG_NLS_CODEPAGE_936=y ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_PI_LIST=y ++# CONFIG_RT_MUTEX_TESTER is not set ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++CONFIG_DEBUG_SPINLOCK_SLEEP=y ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_DEBUG_USER=y ++CONFIG_DEBUG_ERRORS=y ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++CONFIG_DEBUG_S3C_PORT=y ++CONFIG_DEBUG_S3C_UART=0 ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++# CONFIG_CRYPTO_MANAGER is not set ++# CONFIG_CRYPTO_MANAGER2 is not set ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++# CONFIG_CRYPTO_MD5 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_DMA=y +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/config_mini6410_n43 linux-2.6.28.6/config_mini6410_n43 +--- linux-2.6.28/config_mini6410_n43 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/config_mini6410_n43 2010-07-20 11:49:32.000000000 +0200 +@@ -0,0 +1,1742 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28.6 ++# Tue Jul 20 17:49:07 2010 ++# ++CONFIG_ARM=y ++# CONFIG_HAVE_PWM is not set ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++CONFIG_NO_IOPORT=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_ZONE_DMA=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="-FriendlyARM" ++CONFIG_LOCALVERSION_AUTO=y ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="scripts/FriendlyARM.cpio" ++CONFIG_INITRAMFS_ROOT_UID=0 ++CONFIG_INITRAMFS_ROOT_GID=0 ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_COMPAT_BRK=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++# CONFIG_LBD is not set ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_LSF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++# CONFIG_IOSCHED_AS is not set ++# CONFIG_IOSCHED_DEADLINE is not set ++# CONFIG_IOSCHED_CFQ is not set ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++# CONFIG_DEFAULT_CFQ is not set ++CONFIG_DEFAULT_NOOP=y ++CONFIG_DEFAULT_IOSCHED="noop" ++CONFIG_CLASSIC_RCU=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++CONFIG_ARCH_S3C64XX=y ++# CONFIG_ARCH_S5P64XX is not set ++# CONFIG_ARCH_S5PC1XX is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_PLAT_S3C64XX=y ++CONFIG_CPU_S3C6400_INIT=y ++CONFIG_CPU_S3C6400_CLOCK=y ++CONFIG_S3C64XX_SETUP_I2C0=y ++# CONFIG_S3C64XX_ADC is not set ++CONFIG_S3C64XX_DEV_FIMC0=y ++CONFIG_S3C64XX_DEV_FIMC1=y ++CONFIG_S3C64XX_SETUP_FIMC0=y ++CONFIG_S3C64XX_SETUP_FIMC1=y ++# CONFIG_S3C6410_PWM is not set ++CONFIG_NONE_PWM=y ++CONFIG_PLAT_S3C=y ++ ++# ++# Boot options ++# ++# CONFIG_S3C_BOOT_WATCHDOG is not set ++CONFIG_S3C_BOOT_ERROR_RESET=y ++ ++# ++# Power management ++# ++CONFIG_S3C_LOWLEVEL_UART_PORT=0 ++# CONFIG_SPLIT_ROOT_FILESYSTEM is not set ++CONFIG_S3C_GPIO_SPACE=0 ++CONFIG_S3C_GPIO_TRACK=y ++CONFIG_S3C_GPIO_PULL_UPDOWN=y ++CONFIG_S3C_GPIO_CFG_S3C24XX=y ++CONFIG_S3C_GPIO_CFG_S3C64XX=y ++CONFIG_S3C_DEV_HSMMC=y ++CONFIG_S3C_DEV_HSMMC1=y ++CONFIG_S3C_DEV_HSMMC2=y ++CONFIG_S3C_DMA_PL080=y ++CONFIG_CPU_S3C6410=y ++CONFIG_S3C6410_SETUP_SDHCI=y ++CONFIG_MACH_SMDK6410=y ++ ++# ++# SMDK6410 MMC/SD slot setup ++# ++CONFIG_SMDK6410_SD_CH0=y ++# CONFIG_SMDK6410_SD_CH1 is not set ++# CONFIG_SMDK6410_SD_CH2 is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_THUMB is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++CONFIG_ARM_VIC=y ++CONFIG_DMABOUNCE=y ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=200 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++# CONFIG_UNEVICTABLE_LRU is not set ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_CMDLINE="" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_FREQ is not set ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_FPE_NWFPE=y ++# CONFIG_FPE_NWFPE_XP is not set ++# CONFIG_FPE_FASTFPE is not set ++# CONFIG_VFP is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++ ++# ++# Power management options ++# ++# CONFIG_PM is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_PACKET is not set ++CONFIG_UNIX=y ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_BOOTP=y ++CONFIG_IP_PNP_RARP=y ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_CONCAT is not set ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_VERIFY_WRITE is not set ++# CONFIG_MTD_NAND_ECC_SMC is not set ++# CONFIG_MTD_NAND_MUSEUM_IDS is not set ++# CONFIG_MTD_NAND_GPIO is not set ++CONFIG_MTD_NAND_IDS=y ++CONFIG_MTD_NAND_S3C=y ++# CONFIG_MTD_NAND_S3C_DEBUG is not set ++CONFIG_MTD_NAND_S3C_HWECC=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ALAUDA is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# UBI - Unsorted block images ++# ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_RESERVE=1 ++# CONFIG_MTD_UBI_GLUEBI is not set ++ ++# ++# UBI debugging options ++# ++# CONFIG_MTD_UBI_DEBUG is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++# CONFIG_BLK_DEV_RAM is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++# CONFIG_SCSI_MULTI_LUN is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_PHYLIB is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_AX88796 is not set ++# CONFIG_SMC91X is not set ++CONFIG_DM9000=y ++CONFIG_DM9000_DEBUGLEVEL=4 ++# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set ++# CONFIG_SMC911X is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=480 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=272 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_S3C=y ++# CONFIG_TOUCHSCREEN_NEW is not set ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_WM97XX is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++# CONFIG_DEVKMEM is not set ++CONFIG_LEDS_MINI6410=y ++CONFIG_MINI6410_HELLO_MODULE=m ++CONFIG_MINI6410_BUTTONS=y ++CONFIG_MINI6410_BUZZER=y ++# CONFIG_MINI6410_ADC is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_SAMSUNG=y ++CONFIG_SERIAL_SAMSUNG_UARTS=4 ++# CONFIG_SERIAL_SAMSUNG_DEBUG is not set ++CONFIG_SERIAL_SAMSUNG_CONSOLE=y ++CONFIG_SERIAL_S3C6400=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_S3C_MEM is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_HELPER_AUTO is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++CONFIG_I2C_S3C2410=y ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_AT24 is not set ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++# CONFIG_DEBUG_GPIO is not set ++# CONFIG_GPIO_SYSFS is not set ++ ++# ++# Memory mapped GPIO expanders: ++# ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++CONFIG_S3C2410_WATCHDOG=y ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_UCB1400_CORE is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2_COMMON=y ++# CONFIG_VIDEO_ALLOW_V4L1 is not set ++CONFIG_VIDEO_V4L1_COMPAT=y ++# CONFIG_DVB_CORE is not set ++CONFIG_VIDEO_MEDIA=y ++ ++# ++# Multimedia drivers ++# ++# CONFIG_MEDIA_ATTACH is not set ++CONFIG_MEDIA_TUNER=y ++# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set ++CONFIG_MEDIA_TUNER_SIMPLE=y ++CONFIG_MEDIA_TUNER_TDA8290=y ++CONFIG_MEDIA_TUNER_TDA9887=y ++CONFIG_MEDIA_TUNER_TEA5761=y ++CONFIG_MEDIA_TUNER_TEA5767=y ++CONFIG_MEDIA_TUNER_MT20XX=y ++CONFIG_MEDIA_TUNER_XC2028=y ++CONFIG_MEDIA_TUNER_XC5000=y ++CONFIG_VIDEO_V4L2=y ++CONFIG_VIDEOBUF_GEN=y ++CONFIG_VIDEOBUF_VMALLOC=y ++CONFIG_VIDEO_IR=y ++CONFIG_VIDEO_TVEEPROM=y ++CONFIG_VIDEO_TUNER=y ++CONFIG_VIDEO_CAPTURE_DRIVERS=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++CONFIG_VIDEO_FIXED_MINOR_RANGES=y ++# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set ++CONFIG_VIDEO_IR_I2C=y ++ ++# ++# Encoders/decoders and other helper chips ++# ++ ++# ++# Audio decoders ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TDA9875 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++CONFIG_VIDEO_MSP3400=y ++# CONFIG_VIDEO_CS5345 is not set ++CONFIG_VIDEO_CS53L32A=y ++# CONFIG_VIDEO_M52790 is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++CONFIG_VIDEO_WM8775=y ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_TCM825X is not set ++CONFIG_VIDEO_SAA711X=y ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++ ++# ++# Video and audio decoders ++# ++CONFIG_VIDEO_CX25840=y ++ ++# ++# MPEG video encoders ++# ++CONFIG_VIDEO_CX2341X=y ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++# CONFIG_VIDEO_VIVI is not set ++# CONFIG_VIDEO_SAA5246A is not set ++# CONFIG_VIDEO_SAA5249 is not set ++# CONFIG_SOC_CAMERA is not set ++CONFIG_V4L_USB_DRIVERS=y ++CONFIG_USB_VIDEO_CLASS=y ++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y ++CONFIG_USB_GSPCA=y ++CONFIG_USB_M5602=y ++CONFIG_USB_GSPCA_CONEX=y ++CONFIG_USB_GSPCA_ETOMS=y ++CONFIG_USB_GSPCA_FINEPIX=y ++CONFIG_USB_GSPCA_MARS=y ++CONFIG_USB_GSPCA_OV519=y ++CONFIG_USB_GSPCA_PAC207=y ++CONFIG_USB_GSPCA_PAC7311=y ++CONFIG_USB_GSPCA_SONIXB=y ++CONFIG_USB_GSPCA_SONIXJ=y ++CONFIG_USB_GSPCA_SPCA500=y ++CONFIG_USB_GSPCA_SPCA501=y ++CONFIG_USB_GSPCA_SPCA505=y ++CONFIG_USB_GSPCA_SPCA506=y ++CONFIG_USB_GSPCA_SPCA508=y ++CONFIG_USB_GSPCA_SPCA561=y ++CONFIG_USB_GSPCA_STK014=y ++CONFIG_USB_GSPCA_SUNPLUS=y ++CONFIG_USB_GSPCA_T613=y ++CONFIG_USB_GSPCA_TV8532=y ++CONFIG_USB_GSPCA_VC032X=y ++CONFIG_USB_GSPCA_ZC3XX=y ++CONFIG_VIDEO_PVRUSB2=y ++CONFIG_VIDEO_PVRUSB2_SYSFS=y ++# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set ++CONFIG_VIDEO_EM28XX=y ++# CONFIG_VIDEO_EM28XX_ALSA is not set ++CONFIG_VIDEO_USBVISION=y ++CONFIG_USB_ET61X251=y ++CONFIG_USB_SN9C102=y ++CONFIG_USB_ZC0301=y ++CONFIG_USB_ZR364XX=y ++CONFIG_USB_STKWEBCAM=y ++CONFIG_USB_S2255=y ++CONFIG_VIDEO_SAMSUNG=y ++ ++# ++# FIMC configurations ++# ++CONFIG_VIDEO_FIMC=y ++CONFIG_VIDEO_FIMC_DEBUG=y ++# CONFIG_S5K4BA is not set ++# CONFIG_S5K3BA is not set ++CONFIG_OV965X=y ++CONFIG_OV965X_VGA=y ++# CONFIG_OV965X_QVGA is not set ++# CONFIG_OV965X_SVGA is not set ++# CONFIG_OV965X_SXGA is not set ++CONFIG_VIDEO_FIMC_CAM_CH=0 ++CONFIG_VIDEO_FIMC_CAM_RESET=1 ++CONFIG_VIDEO_POST=y ++CONFIG_VIDEO_MFC10=y ++CONFIG_VIDEO_MFC_DEBUG=y ++CONFIG_VIDEO_JPEG=y ++CONFIG_VIDEO_TV=y ++CONFIG_VIDEO_ROTATOR=y ++CONFIG_VIDEO_G2D=y ++CONFIG_VIDEO_G3D=y ++CONFIG_VIDEO_CMM=y ++ ++# ++# Reserved memory configurations ++# ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC=15360 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_POST=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC=6144 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_CMM=8192 ++# CONFIG_RADIO_ADAPTERS is not set ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++CONFIG_FB_S3C=y ++CONFIG_FB_S3C_TFT480272=y ++# CONFIG_FB_S3C_TFT800480 is not set ++# CONFIG_FB_S3C_T240320 is not set ++# CONFIG_FB_S3C_TFT640480 is not set ++# CONFIG_FB_S3C_VGA1024768 is not set ++# CONFIG_FB_S3C_VGA800600 is not set ++# CONFIG_FB_S3C_VGA640480 is not set ++# CONFIG_FB_S3C_EZVGA800600 is not set ++CONFIG_FB_S3C_BPP=y ++# CONFIG_FB_S3C_BPP_8 is not set ++CONFIG_FB_S3C_BPP_16=y ++# CONFIG_FB_S3C_BPP_24 is not set ++# CONFIG_FB_S3C_BPP_28 is not set ++# CONFIG_FB_S3C_BPP_32 is not set ++CONFIG_FB_S3C_NUM=4 ++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set ++CONFIG_FB_S3C_DOUBLE_BUFFERING=y ++# CONFIG_FB_S1D13XXX is not set ++CONFIG_BACKLIGHT_FRIENDLY_ARM=y ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_LOGO_LINUX_CLUT224=y ++# CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224 is not set ++CONFIG_SOUND=y ++CONFIG_SOUND_OSS_CORE=y ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++CONFIG_SND_OSSEMUL=y ++CONFIG_SND_MIXER_OSS=y ++CONFIG_SND_PCM_OSS=y ++CONFIG_SND_PCM_OSS_PLUGINS=y ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_VMASTER=y ++CONFIG_SND_AC97_CODEC=y ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++# CONFIG_SND_AC97_POWER_SAVE is not set ++CONFIG_SND_ARM=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_CAIAQ is not set ++CONFIG_SND_SOC=y ++CONFIG_SND_SOC_AC97_BUS=y ++ ++# ++# SoC Audio for the Samsung S3C ++# ++CONFIG_SND_S3C64XX_SOC=y ++CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713=y ++# CONFIG_SOUND_WM9713_INPUT_STREAM_LINE is not set ++CONFIG_SOUND_WM9713_INPUT_STREAM_MIC=y ++CONFIG_SND_S3C6410_SOC_AC97=y ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8580 is not set ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990 is not set ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_S5M8751 is not set ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM9713=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_AC97_BUS=y ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_BRIGHT=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_DELL=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++CONFIG_USB_DEBUG=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++CONFIG_USB_DEVICE_CLASS=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_S3C_OTG_HOST is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_DPCM is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++CONFIG_USB_SERIAL=y ++# CONFIG_USB_SERIAL_CONSOLE is not set ++# CONFIG_USB_EZUSB is not set ++# CONFIG_USB_SERIAL_GENERIC is not set ++# CONFIG_USB_SERIAL_AIRCABLE is not set ++# CONFIG_USB_SERIAL_ARK3116 is not set ++# CONFIG_USB_SERIAL_BELKIN is not set ++# CONFIG_USB_SERIAL_CH341 is not set ++# CONFIG_USB_SERIAL_WHITEHEAT is not set ++# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set ++# CONFIG_USB_SERIAL_CP2101 is not set ++# CONFIG_USB_SERIAL_CYPRESS_M8 is not set ++# CONFIG_USB_SERIAL_EMPEG is not set ++# CONFIG_USB_SERIAL_FTDI_SIO is not set ++# CONFIG_USB_SERIAL_FUNSOFT is not set ++# CONFIG_USB_SERIAL_VISOR is not set ++# CONFIG_USB_SERIAL_IPAQ is not set ++# CONFIG_USB_SERIAL_IR is not set ++# CONFIG_USB_SERIAL_EDGEPORT is not set ++# CONFIG_USB_SERIAL_EDGEPORT_TI is not set ++# CONFIG_USB_SERIAL_GARMIN is not set ++# CONFIG_USB_SERIAL_IPW is not set ++# CONFIG_USB_SERIAL_IUU is not set ++# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set ++# CONFIG_USB_SERIAL_KEYSPAN is not set ++# CONFIG_USB_SERIAL_KLSI is not set ++# CONFIG_USB_SERIAL_KOBIL_SCT is not set ++# CONFIG_USB_SERIAL_MCT_U232 is not set ++# CONFIG_USB_SERIAL_MOS7720 is not set ++# CONFIG_USB_SERIAL_MOS7840 is not set ++# CONFIG_USB_SERIAL_MOTOROLA is not set ++# CONFIG_USB_SERIAL_NAVMAN is not set ++CONFIG_USB_SERIAL_PL2303=y ++# CONFIG_USB_SERIAL_OTI6858 is not set ++# CONFIG_USB_SERIAL_SPCP8X5 is not set ++# CONFIG_USB_SERIAL_HP4X is not set ++# CONFIG_USB_SERIAL_SAFE is not set ++# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set ++# CONFIG_USB_SERIAL_TI is not set ++# CONFIG_USB_SERIAL_CYBERJACK is not set ++# CONFIG_USB_SERIAL_XIRCOM is not set ++# CONFIG_USB_SERIAL_OPTION is not set ++# CONFIG_USB_SERIAL_OMNINET is not set ++# CONFIG_USB_SERIAL_DEBUG is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++CONFIG_USB_GADGET_S3C_OTGD=y ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++ ++# ++# NOTE: S3C OTG device role enables the controller driver below ++# ++CONFIG_USB_S3C_OTGD=y ++CONFIG_USB_GADGET_S3C_OTGD_DMA_MODE=y ++# CONFIG_USB_GADGET_S3C_OTGD_SLAVE_MODE is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FILE_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++CONFIG_SDIO_UART=y ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_S3C=y ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_NEW_LEDS is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_DRV_S3C=y ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++# CONFIG_EXT2_FS is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++CONFIG_GENERIC_ACL=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=936 ++CONFIG_FAT_DEFAULT_IOCHARSET="utf8" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_YAFFS_FS=y ++CONFIG_YAFFS_YAFFS1=y ++# CONFIG_YAFFS_9BYTE_TAGS is not set ++# CONFIG_YAFFS_DOES_ECC is not set ++CONFIG_YAFFS_YAFFS2=y ++CONFIG_YAFFS_AUTO_YAFFS2=y ++# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set ++# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set ++# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set ++CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y ++# CONFIG_JFFS2_FS is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_XATTR=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++CONFIG_UBIFS_FS_ZLIB=y ++# CONFIG_UBIFS_FS_DEBUG is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++# CONFIG_NFS_V3_ACL is not set ++# CONFIG_NFS_V4 is not set ++CONFIG_ROOT_NFS=y ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++CONFIG_NLS_CODEPAGE_936=y ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_PI_LIST=y ++# CONFIG_RT_MUTEX_TESTER is not set ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++CONFIG_DEBUG_SPINLOCK_SLEEP=y ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_DEBUG_USER=y ++CONFIG_DEBUG_ERRORS=y ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++CONFIG_DEBUG_S3C_PORT=y ++CONFIG_DEBUG_S3C_UART=0 ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++# CONFIG_CRYPTO_MANAGER is not set ++# CONFIG_CRYPTO_MANAGER2 is not set ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++# CONFIG_CRYPTO_MD5 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_DMA=y +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/config_mini6410_t35 linux-2.6.28.6/config_mini6410_t35 +--- linux-2.6.28/config_mini6410_t35 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/config_mini6410_t35 2010-07-20 11:53:57.000000000 +0200 +@@ -0,0 +1,1742 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28.6 ++# Tue Jul 20 17:53:21 2010 ++# ++CONFIG_ARM=y ++# CONFIG_HAVE_PWM is not set ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++CONFIG_NO_IOPORT=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_ZONE_DMA=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="-FriendlyARM" ++CONFIG_LOCALVERSION_AUTO=y ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="scripts/FriendlyARM.cpio" ++CONFIG_INITRAMFS_ROOT_UID=0 ++CONFIG_INITRAMFS_ROOT_GID=0 ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_COMPAT_BRK=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++# CONFIG_LBD is not set ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_LSF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++# CONFIG_IOSCHED_AS is not set ++# CONFIG_IOSCHED_DEADLINE is not set ++# CONFIG_IOSCHED_CFQ is not set ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++# CONFIG_DEFAULT_CFQ is not set ++CONFIG_DEFAULT_NOOP=y ++CONFIG_DEFAULT_IOSCHED="noop" ++CONFIG_CLASSIC_RCU=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++CONFIG_ARCH_S3C64XX=y ++# CONFIG_ARCH_S5P64XX is not set ++# CONFIG_ARCH_S5PC1XX is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_PLAT_S3C64XX=y ++CONFIG_CPU_S3C6400_INIT=y ++CONFIG_CPU_S3C6400_CLOCK=y ++CONFIG_S3C64XX_SETUP_I2C0=y ++# CONFIG_S3C64XX_ADC is not set ++CONFIG_S3C64XX_DEV_FIMC0=y ++CONFIG_S3C64XX_DEV_FIMC1=y ++CONFIG_S3C64XX_SETUP_FIMC0=y ++CONFIG_S3C64XX_SETUP_FIMC1=y ++# CONFIG_S3C6410_PWM is not set ++CONFIG_NONE_PWM=y ++CONFIG_PLAT_S3C=y ++ ++# ++# Boot options ++# ++# CONFIG_S3C_BOOT_WATCHDOG is not set ++CONFIG_S3C_BOOT_ERROR_RESET=y ++ ++# ++# Power management ++# ++CONFIG_S3C_LOWLEVEL_UART_PORT=0 ++# CONFIG_SPLIT_ROOT_FILESYSTEM is not set ++CONFIG_S3C_GPIO_SPACE=0 ++CONFIG_S3C_GPIO_TRACK=y ++CONFIG_S3C_GPIO_PULL_UPDOWN=y ++CONFIG_S3C_GPIO_CFG_S3C24XX=y ++CONFIG_S3C_GPIO_CFG_S3C64XX=y ++CONFIG_S3C_DEV_HSMMC=y ++CONFIG_S3C_DEV_HSMMC1=y ++CONFIG_S3C_DEV_HSMMC2=y ++CONFIG_S3C_DMA_PL080=y ++CONFIG_CPU_S3C6410=y ++CONFIG_S3C6410_SETUP_SDHCI=y ++CONFIG_MACH_SMDK6410=y ++ ++# ++# SMDK6410 MMC/SD slot setup ++# ++CONFIG_SMDK6410_SD_CH0=y ++# CONFIG_SMDK6410_SD_CH1 is not set ++# CONFIG_SMDK6410_SD_CH2 is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_THUMB is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++CONFIG_ARM_VIC=y ++CONFIG_DMABOUNCE=y ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=200 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++# CONFIG_UNEVICTABLE_LRU is not set ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_CMDLINE="" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_FREQ is not set ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_FPE_NWFPE=y ++# CONFIG_FPE_NWFPE_XP is not set ++# CONFIG_FPE_FASTFPE is not set ++# CONFIG_VFP is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++ ++# ++# Power management options ++# ++# CONFIG_PM is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_PACKET is not set ++CONFIG_UNIX=y ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_BOOTP=y ++CONFIG_IP_PNP_RARP=y ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_CONCAT is not set ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_VERIFY_WRITE is not set ++# CONFIG_MTD_NAND_ECC_SMC is not set ++# CONFIG_MTD_NAND_MUSEUM_IDS is not set ++# CONFIG_MTD_NAND_GPIO is not set ++CONFIG_MTD_NAND_IDS=y ++CONFIG_MTD_NAND_S3C=y ++# CONFIG_MTD_NAND_S3C_DEBUG is not set ++CONFIG_MTD_NAND_S3C_HWECC=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ALAUDA is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# UBI - Unsorted block images ++# ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_RESERVE=1 ++# CONFIG_MTD_UBI_GLUEBI is not set ++ ++# ++# UBI debugging options ++# ++# CONFIG_MTD_UBI_DEBUG is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++# CONFIG_BLK_DEV_RAM is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++# CONFIG_SCSI_MULTI_LUN is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_PHYLIB is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_AX88796 is not set ++# CONFIG_SMC91X is not set ++CONFIG_DM9000=y ++CONFIG_DM9000_DEBUGLEVEL=4 ++# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set ++# CONFIG_SMC911X is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=240 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_S3C=y ++# CONFIG_TOUCHSCREEN_NEW is not set ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_WM97XX is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++# CONFIG_DEVKMEM is not set ++CONFIG_LEDS_MINI6410=y ++CONFIG_MINI6410_HELLO_MODULE=m ++CONFIG_MINI6410_BUTTONS=y ++CONFIG_MINI6410_BUZZER=y ++# CONFIG_MINI6410_ADC is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_SAMSUNG=y ++CONFIG_SERIAL_SAMSUNG_UARTS=4 ++# CONFIG_SERIAL_SAMSUNG_DEBUG is not set ++CONFIG_SERIAL_SAMSUNG_CONSOLE=y ++CONFIG_SERIAL_S3C6400=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_S3C_MEM is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_HELPER_AUTO is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++CONFIG_I2C_S3C2410=y ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_AT24 is not set ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++# CONFIG_DEBUG_GPIO is not set ++# CONFIG_GPIO_SYSFS is not set ++ ++# ++# Memory mapped GPIO expanders: ++# ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++CONFIG_S3C2410_WATCHDOG=y ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_UCB1400_CORE is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2_COMMON=y ++# CONFIG_VIDEO_ALLOW_V4L1 is not set ++CONFIG_VIDEO_V4L1_COMPAT=y ++# CONFIG_DVB_CORE is not set ++CONFIG_VIDEO_MEDIA=y ++ ++# ++# Multimedia drivers ++# ++# CONFIG_MEDIA_ATTACH is not set ++CONFIG_MEDIA_TUNER=y ++# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set ++CONFIG_MEDIA_TUNER_SIMPLE=y ++CONFIG_MEDIA_TUNER_TDA8290=y ++CONFIG_MEDIA_TUNER_TDA9887=y ++CONFIG_MEDIA_TUNER_TEA5761=y ++CONFIG_MEDIA_TUNER_TEA5767=y ++CONFIG_MEDIA_TUNER_MT20XX=y ++CONFIG_MEDIA_TUNER_XC2028=y ++CONFIG_MEDIA_TUNER_XC5000=y ++CONFIG_VIDEO_V4L2=y ++CONFIG_VIDEOBUF_GEN=y ++CONFIG_VIDEOBUF_VMALLOC=y ++CONFIG_VIDEO_IR=y ++CONFIG_VIDEO_TVEEPROM=y ++CONFIG_VIDEO_TUNER=y ++CONFIG_VIDEO_CAPTURE_DRIVERS=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++CONFIG_VIDEO_FIXED_MINOR_RANGES=y ++# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set ++CONFIG_VIDEO_IR_I2C=y ++ ++# ++# Encoders/decoders and other helper chips ++# ++ ++# ++# Audio decoders ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TDA9875 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++CONFIG_VIDEO_MSP3400=y ++# CONFIG_VIDEO_CS5345 is not set ++CONFIG_VIDEO_CS53L32A=y ++# CONFIG_VIDEO_M52790 is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++CONFIG_VIDEO_WM8775=y ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_TCM825X is not set ++CONFIG_VIDEO_SAA711X=y ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++ ++# ++# Video and audio decoders ++# ++CONFIG_VIDEO_CX25840=y ++ ++# ++# MPEG video encoders ++# ++CONFIG_VIDEO_CX2341X=y ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++# CONFIG_VIDEO_VIVI is not set ++# CONFIG_VIDEO_SAA5246A is not set ++# CONFIG_VIDEO_SAA5249 is not set ++# CONFIG_SOC_CAMERA is not set ++CONFIG_V4L_USB_DRIVERS=y ++CONFIG_USB_VIDEO_CLASS=y ++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y ++CONFIG_USB_GSPCA=y ++CONFIG_USB_M5602=y ++CONFIG_USB_GSPCA_CONEX=y ++CONFIG_USB_GSPCA_ETOMS=y ++CONFIG_USB_GSPCA_FINEPIX=y ++CONFIG_USB_GSPCA_MARS=y ++CONFIG_USB_GSPCA_OV519=y ++CONFIG_USB_GSPCA_PAC207=y ++CONFIG_USB_GSPCA_PAC7311=y ++CONFIG_USB_GSPCA_SONIXB=y ++CONFIG_USB_GSPCA_SONIXJ=y ++CONFIG_USB_GSPCA_SPCA500=y ++CONFIG_USB_GSPCA_SPCA501=y ++CONFIG_USB_GSPCA_SPCA505=y ++CONFIG_USB_GSPCA_SPCA506=y ++CONFIG_USB_GSPCA_SPCA508=y ++CONFIG_USB_GSPCA_SPCA561=y ++CONFIG_USB_GSPCA_STK014=y ++CONFIG_USB_GSPCA_SUNPLUS=y ++CONFIG_USB_GSPCA_T613=y ++CONFIG_USB_GSPCA_TV8532=y ++CONFIG_USB_GSPCA_VC032X=y ++CONFIG_USB_GSPCA_ZC3XX=y ++CONFIG_VIDEO_PVRUSB2=y ++CONFIG_VIDEO_PVRUSB2_SYSFS=y ++# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set ++CONFIG_VIDEO_EM28XX=y ++# CONFIG_VIDEO_EM28XX_ALSA is not set ++CONFIG_VIDEO_USBVISION=y ++CONFIG_USB_ET61X251=y ++CONFIG_USB_SN9C102=y ++CONFIG_USB_ZC0301=y ++CONFIG_USB_ZR364XX=y ++CONFIG_USB_STKWEBCAM=y ++CONFIG_USB_S2255=y ++CONFIG_VIDEO_SAMSUNG=y ++ ++# ++# FIMC configurations ++# ++CONFIG_VIDEO_FIMC=y ++CONFIG_VIDEO_FIMC_DEBUG=y ++# CONFIG_S5K4BA is not set ++# CONFIG_S5K3BA is not set ++CONFIG_OV965X=y ++CONFIG_OV965X_VGA=y ++# CONFIG_OV965X_QVGA is not set ++# CONFIG_OV965X_SVGA is not set ++# CONFIG_OV965X_SXGA is not set ++CONFIG_VIDEO_FIMC_CAM_CH=0 ++CONFIG_VIDEO_FIMC_CAM_RESET=1 ++CONFIG_VIDEO_POST=y ++CONFIG_VIDEO_MFC10=y ++CONFIG_VIDEO_MFC_DEBUG=y ++CONFIG_VIDEO_JPEG=y ++CONFIG_VIDEO_TV=y ++CONFIG_VIDEO_ROTATOR=y ++CONFIG_VIDEO_G2D=y ++CONFIG_VIDEO_G3D=y ++CONFIG_VIDEO_CMM=y ++ ++# ++# Reserved memory configurations ++# ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC=15360 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_POST=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC=6144 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_CMM=8192 ++# CONFIG_RADIO_ADAPTERS is not set ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++CONFIG_FB_S3C=y ++# CONFIG_FB_S3C_TFT480272 is not set ++# CONFIG_FB_S3C_TFT800480 is not set ++CONFIG_FB_S3C_T240320=y ++# CONFIG_FB_S3C_TFT640480 is not set ++# CONFIG_FB_S3C_VGA1024768 is not set ++# CONFIG_FB_S3C_VGA800600 is not set ++# CONFIG_FB_S3C_VGA640480 is not set ++# CONFIG_FB_S3C_EZVGA800600 is not set ++CONFIG_FB_S3C_BPP=y ++# CONFIG_FB_S3C_BPP_8 is not set ++CONFIG_FB_S3C_BPP_16=y ++# CONFIG_FB_S3C_BPP_24 is not set ++# CONFIG_FB_S3C_BPP_28 is not set ++# CONFIG_FB_S3C_BPP_32 is not set ++CONFIG_FB_S3C_NUM=4 ++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set ++CONFIG_FB_S3C_DOUBLE_BUFFERING=y ++# CONFIG_FB_S1D13XXX is not set ++CONFIG_BACKLIGHT_FRIENDLY_ARM=y ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_LOGO_LINUX_CLUT224=y ++# CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224 is not set ++CONFIG_SOUND=y ++CONFIG_SOUND_OSS_CORE=y ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++CONFIG_SND_OSSEMUL=y ++CONFIG_SND_MIXER_OSS=y ++CONFIG_SND_PCM_OSS=y ++CONFIG_SND_PCM_OSS_PLUGINS=y ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_VMASTER=y ++CONFIG_SND_AC97_CODEC=y ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++# CONFIG_SND_AC97_POWER_SAVE is not set ++CONFIG_SND_ARM=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_CAIAQ is not set ++CONFIG_SND_SOC=y ++CONFIG_SND_SOC_AC97_BUS=y ++ ++# ++# SoC Audio for the Samsung S3C ++# ++CONFIG_SND_S3C64XX_SOC=y ++CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713=y ++# CONFIG_SOUND_WM9713_INPUT_STREAM_LINE is not set ++CONFIG_SOUND_WM9713_INPUT_STREAM_MIC=y ++CONFIG_SND_S3C6410_SOC_AC97=y ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8580 is not set ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990 is not set ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_S5M8751 is not set ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM9713=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_AC97_BUS=y ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_BRIGHT=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_DELL=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++CONFIG_USB_DEBUG=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++CONFIG_USB_DEVICE_CLASS=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_S3C_OTG_HOST is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_DPCM is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++CONFIG_USB_SERIAL=y ++# CONFIG_USB_SERIAL_CONSOLE is not set ++# CONFIG_USB_EZUSB is not set ++# CONFIG_USB_SERIAL_GENERIC is not set ++# CONFIG_USB_SERIAL_AIRCABLE is not set ++# CONFIG_USB_SERIAL_ARK3116 is not set ++# CONFIG_USB_SERIAL_BELKIN is not set ++# CONFIG_USB_SERIAL_CH341 is not set ++# CONFIG_USB_SERIAL_WHITEHEAT is not set ++# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set ++# CONFIG_USB_SERIAL_CP2101 is not set ++# CONFIG_USB_SERIAL_CYPRESS_M8 is not set ++# CONFIG_USB_SERIAL_EMPEG is not set ++# CONFIG_USB_SERIAL_FTDI_SIO is not set ++# CONFIG_USB_SERIAL_FUNSOFT is not set ++# CONFIG_USB_SERIAL_VISOR is not set ++# CONFIG_USB_SERIAL_IPAQ is not set ++# CONFIG_USB_SERIAL_IR is not set ++# CONFIG_USB_SERIAL_EDGEPORT is not set ++# CONFIG_USB_SERIAL_EDGEPORT_TI is not set ++# CONFIG_USB_SERIAL_GARMIN is not set ++# CONFIG_USB_SERIAL_IPW is not set ++# CONFIG_USB_SERIAL_IUU is not set ++# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set ++# CONFIG_USB_SERIAL_KEYSPAN is not set ++# CONFIG_USB_SERIAL_KLSI is not set ++# CONFIG_USB_SERIAL_KOBIL_SCT is not set ++# CONFIG_USB_SERIAL_MCT_U232 is not set ++# CONFIG_USB_SERIAL_MOS7720 is not set ++# CONFIG_USB_SERIAL_MOS7840 is not set ++# CONFIG_USB_SERIAL_MOTOROLA is not set ++# CONFIG_USB_SERIAL_NAVMAN is not set ++CONFIG_USB_SERIAL_PL2303=y ++# CONFIG_USB_SERIAL_OTI6858 is not set ++# CONFIG_USB_SERIAL_SPCP8X5 is not set ++# CONFIG_USB_SERIAL_HP4X is not set ++# CONFIG_USB_SERIAL_SAFE is not set ++# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set ++# CONFIG_USB_SERIAL_TI is not set ++# CONFIG_USB_SERIAL_CYBERJACK is not set ++# CONFIG_USB_SERIAL_XIRCOM is not set ++# CONFIG_USB_SERIAL_OPTION is not set ++# CONFIG_USB_SERIAL_OMNINET is not set ++# CONFIG_USB_SERIAL_DEBUG is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++CONFIG_USB_GADGET_S3C_OTGD=y ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++ ++# ++# NOTE: S3C OTG device role enables the controller driver below ++# ++CONFIG_USB_S3C_OTGD=y ++CONFIG_USB_GADGET_S3C_OTGD_DMA_MODE=y ++# CONFIG_USB_GADGET_S3C_OTGD_SLAVE_MODE is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FILE_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++CONFIG_SDIO_UART=y ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_S3C=y ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_NEW_LEDS is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_DRV_S3C=y ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++# CONFIG_EXT2_FS is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++CONFIG_GENERIC_ACL=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=936 ++CONFIG_FAT_DEFAULT_IOCHARSET="utf8" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_YAFFS_FS=y ++CONFIG_YAFFS_YAFFS1=y ++# CONFIG_YAFFS_9BYTE_TAGS is not set ++# CONFIG_YAFFS_DOES_ECC is not set ++CONFIG_YAFFS_YAFFS2=y ++CONFIG_YAFFS_AUTO_YAFFS2=y ++# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set ++# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set ++# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set ++CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y ++# CONFIG_JFFS2_FS is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_XATTR=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++CONFIG_UBIFS_FS_ZLIB=y ++# CONFIG_UBIFS_FS_DEBUG is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++# CONFIG_NFS_V3_ACL is not set ++# CONFIG_NFS_V4 is not set ++CONFIG_ROOT_NFS=y ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++CONFIG_NLS_CODEPAGE_936=y ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_PI_LIST=y ++# CONFIG_RT_MUTEX_TESTER is not set ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++CONFIG_DEBUG_SPINLOCK_SLEEP=y ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_DEBUG_USER=y ++CONFIG_DEBUG_ERRORS=y ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++CONFIG_DEBUG_S3C_PORT=y ++CONFIG_DEBUG_S3C_UART=0 ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++# CONFIG_CRYPTO_MANAGER is not set ++# CONFIG_CRYPTO_MANAGER2 is not set ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++# CONFIG_CRYPTO_MD5 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_DMA=y +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/config_mini6410_vga1024x768 linux-2.6.28.6/config_mini6410_vga1024x768 +--- linux-2.6.28/config_mini6410_vga1024x768 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/config_mini6410_vga1024x768 2010-07-20 11:59:04.000000000 +0200 +@@ -0,0 +1,1741 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28.6 ++# Tue Jul 20 17:58:28 2010 ++# ++CONFIG_ARM=y ++# CONFIG_HAVE_PWM is not set ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++CONFIG_NO_IOPORT=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_ZONE_DMA=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="-FriendlyARM" ++CONFIG_LOCALVERSION_AUTO=y ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="scripts/FriendlyARM.cpio" ++CONFIG_INITRAMFS_ROOT_UID=0 ++CONFIG_INITRAMFS_ROOT_GID=0 ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_COMPAT_BRK=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++# CONFIG_LBD is not set ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_LSF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++# CONFIG_IOSCHED_AS is not set ++# CONFIG_IOSCHED_DEADLINE is not set ++# CONFIG_IOSCHED_CFQ is not set ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++# CONFIG_DEFAULT_CFQ is not set ++CONFIG_DEFAULT_NOOP=y ++CONFIG_DEFAULT_IOSCHED="noop" ++CONFIG_CLASSIC_RCU=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++CONFIG_ARCH_S3C64XX=y ++# CONFIG_ARCH_S5P64XX is not set ++# CONFIG_ARCH_S5PC1XX is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_PLAT_S3C64XX=y ++CONFIG_CPU_S3C6400_INIT=y ++CONFIG_CPU_S3C6400_CLOCK=y ++CONFIG_S3C64XX_SETUP_I2C0=y ++# CONFIG_S3C64XX_ADC is not set ++CONFIG_S3C64XX_DEV_FIMC0=y ++CONFIG_S3C64XX_DEV_FIMC1=y ++CONFIG_S3C64XX_SETUP_FIMC0=y ++CONFIG_S3C64XX_SETUP_FIMC1=y ++# CONFIG_S3C6410_PWM is not set ++CONFIG_NONE_PWM=y ++CONFIG_PLAT_S3C=y ++ ++# ++# Boot options ++# ++# CONFIG_S3C_BOOT_WATCHDOG is not set ++CONFIG_S3C_BOOT_ERROR_RESET=y ++ ++# ++# Power management ++# ++CONFIG_S3C_LOWLEVEL_UART_PORT=0 ++# CONFIG_SPLIT_ROOT_FILESYSTEM is not set ++CONFIG_S3C_GPIO_SPACE=0 ++CONFIG_S3C_GPIO_TRACK=y ++CONFIG_S3C_GPIO_PULL_UPDOWN=y ++CONFIG_S3C_GPIO_CFG_S3C24XX=y ++CONFIG_S3C_GPIO_CFG_S3C64XX=y ++CONFIG_S3C_DEV_HSMMC=y ++CONFIG_S3C_DEV_HSMMC1=y ++CONFIG_S3C_DEV_HSMMC2=y ++CONFIG_S3C_DMA_PL080=y ++CONFIG_CPU_S3C6410=y ++CONFIG_S3C6410_SETUP_SDHCI=y ++CONFIG_MACH_SMDK6410=y ++ ++# ++# SMDK6410 MMC/SD slot setup ++# ++CONFIG_SMDK6410_SD_CH0=y ++# CONFIG_SMDK6410_SD_CH1 is not set ++# CONFIG_SMDK6410_SD_CH2 is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_THUMB is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++CONFIG_ARM_VIC=y ++CONFIG_DMABOUNCE=y ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=200 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++# CONFIG_UNEVICTABLE_LRU is not set ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_CMDLINE="" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_FREQ is not set ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_FPE_NWFPE=y ++# CONFIG_FPE_NWFPE_XP is not set ++# CONFIG_FPE_FASTFPE is not set ++# CONFIG_VFP is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++ ++# ++# Power management options ++# ++# CONFIG_PM is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_PACKET is not set ++CONFIG_UNIX=y ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_BOOTP=y ++CONFIG_IP_PNP_RARP=y ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_CONCAT is not set ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_VERIFY_WRITE is not set ++# CONFIG_MTD_NAND_ECC_SMC is not set ++# CONFIG_MTD_NAND_MUSEUM_IDS is not set ++# CONFIG_MTD_NAND_GPIO is not set ++CONFIG_MTD_NAND_IDS=y ++CONFIG_MTD_NAND_S3C=y ++# CONFIG_MTD_NAND_S3C_DEBUG is not set ++CONFIG_MTD_NAND_S3C_HWECC=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ALAUDA is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# UBI - Unsorted block images ++# ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_RESERVE=1 ++# CONFIG_MTD_UBI_GLUEBI is not set ++ ++# ++# UBI debugging options ++# ++# CONFIG_MTD_UBI_DEBUG is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++# CONFIG_BLK_DEV_RAM is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++# CONFIG_SCSI_MULTI_LUN is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_PHYLIB is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_AX88796 is not set ++# CONFIG_SMC91X is not set ++CONFIG_DM9000=y ++CONFIG_DM9000_DEBUGLEVEL=4 ++# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set ++# CONFIG_SMC911X is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++# CONFIG_TOUCHSCREEN_S3C is not set ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_WM97XX is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++# CONFIG_DEVKMEM is not set ++CONFIG_LEDS_MINI6410=y ++CONFIG_MINI6410_HELLO_MODULE=m ++CONFIG_MINI6410_BUTTONS=y ++CONFIG_MINI6410_BUZZER=y ++# CONFIG_MINI6410_ADC is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_SAMSUNG=y ++CONFIG_SERIAL_SAMSUNG_UARTS=4 ++# CONFIG_SERIAL_SAMSUNG_DEBUG is not set ++CONFIG_SERIAL_SAMSUNG_CONSOLE=y ++CONFIG_SERIAL_S3C6400=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_S3C_MEM is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_HELPER_AUTO is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++CONFIG_I2C_S3C2410=y ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_AT24 is not set ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++# CONFIG_DEBUG_GPIO is not set ++# CONFIG_GPIO_SYSFS is not set ++ ++# ++# Memory mapped GPIO expanders: ++# ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++CONFIG_S3C2410_WATCHDOG=y ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_UCB1400_CORE is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2_COMMON=y ++# CONFIG_VIDEO_ALLOW_V4L1 is not set ++CONFIG_VIDEO_V4L1_COMPAT=y ++# CONFIG_DVB_CORE is not set ++CONFIG_VIDEO_MEDIA=y ++ ++# ++# Multimedia drivers ++# ++# CONFIG_MEDIA_ATTACH is not set ++CONFIG_MEDIA_TUNER=y ++# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set ++CONFIG_MEDIA_TUNER_SIMPLE=y ++CONFIG_MEDIA_TUNER_TDA8290=y ++CONFIG_MEDIA_TUNER_TDA9887=y ++CONFIG_MEDIA_TUNER_TEA5761=y ++CONFIG_MEDIA_TUNER_TEA5767=y ++CONFIG_MEDIA_TUNER_MT20XX=y ++CONFIG_MEDIA_TUNER_XC2028=y ++CONFIG_MEDIA_TUNER_XC5000=y ++CONFIG_VIDEO_V4L2=y ++CONFIG_VIDEOBUF_GEN=y ++CONFIG_VIDEOBUF_VMALLOC=y ++CONFIG_VIDEO_IR=y ++CONFIG_VIDEO_TVEEPROM=y ++CONFIG_VIDEO_TUNER=y ++CONFIG_VIDEO_CAPTURE_DRIVERS=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++CONFIG_VIDEO_FIXED_MINOR_RANGES=y ++# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set ++CONFIG_VIDEO_IR_I2C=y ++ ++# ++# Encoders/decoders and other helper chips ++# ++ ++# ++# Audio decoders ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TDA9875 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++CONFIG_VIDEO_MSP3400=y ++# CONFIG_VIDEO_CS5345 is not set ++CONFIG_VIDEO_CS53L32A=y ++# CONFIG_VIDEO_M52790 is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++CONFIG_VIDEO_WM8775=y ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_TCM825X is not set ++CONFIG_VIDEO_SAA711X=y ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++ ++# ++# Video and audio decoders ++# ++CONFIG_VIDEO_CX25840=y ++ ++# ++# MPEG video encoders ++# ++CONFIG_VIDEO_CX2341X=y ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++# CONFIG_VIDEO_VIVI is not set ++# CONFIG_VIDEO_SAA5246A is not set ++# CONFIG_VIDEO_SAA5249 is not set ++# CONFIG_SOC_CAMERA is not set ++CONFIG_V4L_USB_DRIVERS=y ++CONFIG_USB_VIDEO_CLASS=y ++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y ++CONFIG_USB_GSPCA=y ++CONFIG_USB_M5602=y ++CONFIG_USB_GSPCA_CONEX=y ++CONFIG_USB_GSPCA_ETOMS=y ++CONFIG_USB_GSPCA_FINEPIX=y ++CONFIG_USB_GSPCA_MARS=y ++CONFIG_USB_GSPCA_OV519=y ++CONFIG_USB_GSPCA_PAC207=y ++CONFIG_USB_GSPCA_PAC7311=y ++CONFIG_USB_GSPCA_SONIXB=y ++CONFIG_USB_GSPCA_SONIXJ=y ++CONFIG_USB_GSPCA_SPCA500=y ++CONFIG_USB_GSPCA_SPCA501=y ++CONFIG_USB_GSPCA_SPCA505=y ++CONFIG_USB_GSPCA_SPCA506=y ++CONFIG_USB_GSPCA_SPCA508=y ++CONFIG_USB_GSPCA_SPCA561=y ++CONFIG_USB_GSPCA_STK014=y ++CONFIG_USB_GSPCA_SUNPLUS=y ++CONFIG_USB_GSPCA_T613=y ++CONFIG_USB_GSPCA_TV8532=y ++CONFIG_USB_GSPCA_VC032X=y ++CONFIG_USB_GSPCA_ZC3XX=y ++CONFIG_VIDEO_PVRUSB2=y ++CONFIG_VIDEO_PVRUSB2_SYSFS=y ++# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set ++CONFIG_VIDEO_EM28XX=y ++# CONFIG_VIDEO_EM28XX_ALSA is not set ++CONFIG_VIDEO_USBVISION=y ++CONFIG_USB_ET61X251=y ++CONFIG_USB_SN9C102=y ++CONFIG_USB_ZC0301=y ++CONFIG_USB_ZR364XX=y ++CONFIG_USB_STKWEBCAM=y ++CONFIG_USB_S2255=y ++CONFIG_VIDEO_SAMSUNG=y ++ ++# ++# FIMC configurations ++# ++CONFIG_VIDEO_FIMC=y ++CONFIG_VIDEO_FIMC_DEBUG=y ++# CONFIG_S5K4BA is not set ++# CONFIG_S5K3BA is not set ++CONFIG_OV965X=y ++CONFIG_OV965X_VGA=y ++# CONFIG_OV965X_QVGA is not set ++# CONFIG_OV965X_SVGA is not set ++# CONFIG_OV965X_SXGA is not set ++CONFIG_VIDEO_FIMC_CAM_CH=0 ++CONFIG_VIDEO_FIMC_CAM_RESET=1 ++CONFIG_VIDEO_POST=y ++CONFIG_VIDEO_MFC10=y ++CONFIG_VIDEO_MFC_DEBUG=y ++CONFIG_VIDEO_JPEG=y ++CONFIG_VIDEO_TV=y ++CONFIG_VIDEO_ROTATOR=y ++CONFIG_VIDEO_G2D=y ++CONFIG_VIDEO_G3D=y ++CONFIG_VIDEO_CMM=y ++ ++# ++# Reserved memory configurations ++# ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC=15360 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_POST=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC=6144 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_CMM=8192 ++# CONFIG_RADIO_ADAPTERS is not set ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++CONFIG_FB_S3C=y ++# CONFIG_FB_S3C_TFT480272 is not set ++# CONFIG_FB_S3C_TFT800480 is not set ++# CONFIG_FB_S3C_T240320 is not set ++# CONFIG_FB_S3C_TFT640480 is not set ++CONFIG_FB_S3C_VGA1024768=y ++# CONFIG_FB_S3C_VGA800600 is not set ++# CONFIG_FB_S3C_VGA640480 is not set ++# CONFIG_FB_S3C_EZVGA800600 is not set ++CONFIG_FB_S3C_BPP=y ++# CONFIG_FB_S3C_BPP_8 is not set ++CONFIG_FB_S3C_BPP_16=y ++# CONFIG_FB_S3C_BPP_24 is not set ++# CONFIG_FB_S3C_BPP_28 is not set ++# CONFIG_FB_S3C_BPP_32 is not set ++CONFIG_FB_S3C_NUM=4 ++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set ++CONFIG_FB_S3C_DOUBLE_BUFFERING=y ++# CONFIG_FB_S1D13XXX is not set ++CONFIG_BACKLIGHT_FRIENDLY_ARM=y ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_LOGO_LINUX_CLUT224=y ++# CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224 is not set ++CONFIG_SOUND=y ++CONFIG_SOUND_OSS_CORE=y ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++CONFIG_SND_OSSEMUL=y ++CONFIG_SND_MIXER_OSS=y ++CONFIG_SND_PCM_OSS=y ++CONFIG_SND_PCM_OSS_PLUGINS=y ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_VMASTER=y ++CONFIG_SND_AC97_CODEC=y ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++# CONFIG_SND_AC97_POWER_SAVE is not set ++CONFIG_SND_ARM=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_CAIAQ is not set ++CONFIG_SND_SOC=y ++CONFIG_SND_SOC_AC97_BUS=y ++ ++# ++# SoC Audio for the Samsung S3C ++# ++CONFIG_SND_S3C64XX_SOC=y ++CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713=y ++# CONFIG_SOUND_WM9713_INPUT_STREAM_LINE is not set ++CONFIG_SOUND_WM9713_INPUT_STREAM_MIC=y ++CONFIG_SND_S3C6410_SOC_AC97=y ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8580 is not set ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990 is not set ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_S5M8751 is not set ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM9713=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_AC97_BUS=y ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_BRIGHT=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_DELL=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++CONFIG_USB_DEBUG=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++CONFIG_USB_DEVICE_CLASS=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_S3C_OTG_HOST is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_DPCM is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++CONFIG_USB_SERIAL=y ++# CONFIG_USB_SERIAL_CONSOLE is not set ++# CONFIG_USB_EZUSB is not set ++# CONFIG_USB_SERIAL_GENERIC is not set ++# CONFIG_USB_SERIAL_AIRCABLE is not set ++# CONFIG_USB_SERIAL_ARK3116 is not set ++# CONFIG_USB_SERIAL_BELKIN is not set ++# CONFIG_USB_SERIAL_CH341 is not set ++# CONFIG_USB_SERIAL_WHITEHEAT is not set ++# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set ++# CONFIG_USB_SERIAL_CP2101 is not set ++# CONFIG_USB_SERIAL_CYPRESS_M8 is not set ++# CONFIG_USB_SERIAL_EMPEG is not set ++# CONFIG_USB_SERIAL_FTDI_SIO is not set ++# CONFIG_USB_SERIAL_FUNSOFT is not set ++# CONFIG_USB_SERIAL_VISOR is not set ++# CONFIG_USB_SERIAL_IPAQ is not set ++# CONFIG_USB_SERIAL_IR is not set ++# CONFIG_USB_SERIAL_EDGEPORT is not set ++# CONFIG_USB_SERIAL_EDGEPORT_TI is not set ++# CONFIG_USB_SERIAL_GARMIN is not set ++# CONFIG_USB_SERIAL_IPW is not set ++# CONFIG_USB_SERIAL_IUU is not set ++# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set ++# CONFIG_USB_SERIAL_KEYSPAN is not set ++# CONFIG_USB_SERIAL_KLSI is not set ++# CONFIG_USB_SERIAL_KOBIL_SCT is not set ++# CONFIG_USB_SERIAL_MCT_U232 is not set ++# CONFIG_USB_SERIAL_MOS7720 is not set ++# CONFIG_USB_SERIAL_MOS7840 is not set ++# CONFIG_USB_SERIAL_MOTOROLA is not set ++# CONFIG_USB_SERIAL_NAVMAN is not set ++CONFIG_USB_SERIAL_PL2303=y ++# CONFIG_USB_SERIAL_OTI6858 is not set ++# CONFIG_USB_SERIAL_SPCP8X5 is not set ++# CONFIG_USB_SERIAL_HP4X is not set ++# CONFIG_USB_SERIAL_SAFE is not set ++# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set ++# CONFIG_USB_SERIAL_TI is not set ++# CONFIG_USB_SERIAL_CYBERJACK is not set ++# CONFIG_USB_SERIAL_XIRCOM is not set ++# CONFIG_USB_SERIAL_OPTION is not set ++# CONFIG_USB_SERIAL_OMNINET is not set ++# CONFIG_USB_SERIAL_DEBUG is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++CONFIG_USB_GADGET_S3C_OTGD=y ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++ ++# ++# NOTE: S3C OTG device role enables the controller driver below ++# ++CONFIG_USB_S3C_OTGD=y ++CONFIG_USB_GADGET_S3C_OTGD_DMA_MODE=y ++# CONFIG_USB_GADGET_S3C_OTGD_SLAVE_MODE is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FILE_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++CONFIG_SDIO_UART=y ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_S3C=y ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_NEW_LEDS is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_DRV_S3C=y ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++# CONFIG_EXT2_FS is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++CONFIG_GENERIC_ACL=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=936 ++CONFIG_FAT_DEFAULT_IOCHARSET="utf8" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_YAFFS_FS=y ++CONFIG_YAFFS_YAFFS1=y ++# CONFIG_YAFFS_9BYTE_TAGS is not set ++# CONFIG_YAFFS_DOES_ECC is not set ++CONFIG_YAFFS_YAFFS2=y ++CONFIG_YAFFS_AUTO_YAFFS2=y ++# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set ++# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set ++# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set ++CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y ++# CONFIG_JFFS2_FS is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_XATTR=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++CONFIG_UBIFS_FS_ZLIB=y ++# CONFIG_UBIFS_FS_DEBUG is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++# CONFIG_NFS_V3_ACL is not set ++# CONFIG_NFS_V4 is not set ++CONFIG_ROOT_NFS=y ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++CONFIG_NLS_CODEPAGE_936=y ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_PI_LIST=y ++# CONFIG_RT_MUTEX_TESTER is not set ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++CONFIG_DEBUG_SPINLOCK_SLEEP=y ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_DEBUG_USER=y ++CONFIG_DEBUG_ERRORS=y ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++CONFIG_DEBUG_S3C_PORT=y ++CONFIG_DEBUG_S3C_UART=0 ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++# CONFIG_CRYPTO_MANAGER is not set ++# CONFIG_CRYPTO_MANAGER2 is not set ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++# CONFIG_CRYPTO_MD5 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_DMA=y +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/config_mini6410_vga640x480 linux-2.6.28.6/config_mini6410_vga640x480 +--- linux-2.6.28/config_mini6410_vga640x480 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/config_mini6410_vga640x480 2010-07-20 12:02:09.000000000 +0200 +@@ -0,0 +1,1741 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28.6 ++# Tue Jul 20 18:01:28 2010 ++# ++CONFIG_ARM=y ++# CONFIG_HAVE_PWM is not set ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++CONFIG_NO_IOPORT=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_ZONE_DMA=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="-FriendlyARM" ++CONFIG_LOCALVERSION_AUTO=y ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="scripts/FriendlyARM.cpio" ++CONFIG_INITRAMFS_ROOT_UID=0 ++CONFIG_INITRAMFS_ROOT_GID=0 ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_COMPAT_BRK=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++# CONFIG_LBD is not set ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_LSF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++# CONFIG_IOSCHED_AS is not set ++# CONFIG_IOSCHED_DEADLINE is not set ++# CONFIG_IOSCHED_CFQ is not set ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++# CONFIG_DEFAULT_CFQ is not set ++CONFIG_DEFAULT_NOOP=y ++CONFIG_DEFAULT_IOSCHED="noop" ++CONFIG_CLASSIC_RCU=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++CONFIG_ARCH_S3C64XX=y ++# CONFIG_ARCH_S5P64XX is not set ++# CONFIG_ARCH_S5PC1XX is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_PLAT_S3C64XX=y ++CONFIG_CPU_S3C6400_INIT=y ++CONFIG_CPU_S3C6400_CLOCK=y ++CONFIG_S3C64XX_SETUP_I2C0=y ++# CONFIG_S3C64XX_ADC is not set ++CONFIG_S3C64XX_DEV_FIMC0=y ++CONFIG_S3C64XX_DEV_FIMC1=y ++CONFIG_S3C64XX_SETUP_FIMC0=y ++CONFIG_S3C64XX_SETUP_FIMC1=y ++# CONFIG_S3C6410_PWM is not set ++CONFIG_NONE_PWM=y ++CONFIG_PLAT_S3C=y ++ ++# ++# Boot options ++# ++# CONFIG_S3C_BOOT_WATCHDOG is not set ++CONFIG_S3C_BOOT_ERROR_RESET=y ++ ++# ++# Power management ++# ++CONFIG_S3C_LOWLEVEL_UART_PORT=0 ++# CONFIG_SPLIT_ROOT_FILESYSTEM is not set ++CONFIG_S3C_GPIO_SPACE=0 ++CONFIG_S3C_GPIO_TRACK=y ++CONFIG_S3C_GPIO_PULL_UPDOWN=y ++CONFIG_S3C_GPIO_CFG_S3C24XX=y ++CONFIG_S3C_GPIO_CFG_S3C64XX=y ++CONFIG_S3C_DEV_HSMMC=y ++CONFIG_S3C_DEV_HSMMC1=y ++CONFIG_S3C_DEV_HSMMC2=y ++CONFIG_S3C_DMA_PL080=y ++CONFIG_CPU_S3C6410=y ++CONFIG_S3C6410_SETUP_SDHCI=y ++CONFIG_MACH_SMDK6410=y ++ ++# ++# SMDK6410 MMC/SD slot setup ++# ++CONFIG_SMDK6410_SD_CH0=y ++# CONFIG_SMDK6410_SD_CH1 is not set ++# CONFIG_SMDK6410_SD_CH2 is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_THUMB is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++CONFIG_ARM_VIC=y ++CONFIG_DMABOUNCE=y ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=200 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++# CONFIG_UNEVICTABLE_LRU is not set ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_CMDLINE="" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_FREQ is not set ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_FPE_NWFPE=y ++# CONFIG_FPE_NWFPE_XP is not set ++# CONFIG_FPE_FASTFPE is not set ++# CONFIG_VFP is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++ ++# ++# Power management options ++# ++# CONFIG_PM is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_PACKET is not set ++CONFIG_UNIX=y ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_BOOTP=y ++CONFIG_IP_PNP_RARP=y ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_CONCAT is not set ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_VERIFY_WRITE is not set ++# CONFIG_MTD_NAND_ECC_SMC is not set ++# CONFIG_MTD_NAND_MUSEUM_IDS is not set ++# CONFIG_MTD_NAND_GPIO is not set ++CONFIG_MTD_NAND_IDS=y ++CONFIG_MTD_NAND_S3C=y ++# CONFIG_MTD_NAND_S3C_DEBUG is not set ++CONFIG_MTD_NAND_S3C_HWECC=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ALAUDA is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# UBI - Unsorted block images ++# ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_RESERVE=1 ++# CONFIG_MTD_UBI_GLUEBI is not set ++ ++# ++# UBI debugging options ++# ++# CONFIG_MTD_UBI_DEBUG is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++# CONFIG_BLK_DEV_RAM is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++# CONFIG_SCSI_MULTI_LUN is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_PHYLIB is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_AX88796 is not set ++# CONFIG_SMC91X is not set ++CONFIG_DM9000=y ++CONFIG_DM9000_DEBUGLEVEL=4 ++# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set ++# CONFIG_SMC911X is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=640 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++# CONFIG_TOUCHSCREEN_S3C is not set ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_WM97XX is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++# CONFIG_DEVKMEM is not set ++CONFIG_LEDS_MINI6410=y ++CONFIG_MINI6410_HELLO_MODULE=m ++CONFIG_MINI6410_BUTTONS=y ++CONFIG_MINI6410_BUZZER=y ++# CONFIG_MINI6410_ADC is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_SAMSUNG=y ++CONFIG_SERIAL_SAMSUNG_UARTS=4 ++# CONFIG_SERIAL_SAMSUNG_DEBUG is not set ++CONFIG_SERIAL_SAMSUNG_CONSOLE=y ++CONFIG_SERIAL_S3C6400=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_S3C_MEM is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_HELPER_AUTO is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++CONFIG_I2C_S3C2410=y ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_AT24 is not set ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++# CONFIG_DEBUG_GPIO is not set ++# CONFIG_GPIO_SYSFS is not set ++ ++# ++# Memory mapped GPIO expanders: ++# ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++CONFIG_S3C2410_WATCHDOG=y ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_UCB1400_CORE is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2_COMMON=y ++# CONFIG_VIDEO_ALLOW_V4L1 is not set ++CONFIG_VIDEO_V4L1_COMPAT=y ++# CONFIG_DVB_CORE is not set ++CONFIG_VIDEO_MEDIA=y ++ ++# ++# Multimedia drivers ++# ++# CONFIG_MEDIA_ATTACH is not set ++CONFIG_MEDIA_TUNER=y ++# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set ++CONFIG_MEDIA_TUNER_SIMPLE=y ++CONFIG_MEDIA_TUNER_TDA8290=y ++CONFIG_MEDIA_TUNER_TDA9887=y ++CONFIG_MEDIA_TUNER_TEA5761=y ++CONFIG_MEDIA_TUNER_TEA5767=y ++CONFIG_MEDIA_TUNER_MT20XX=y ++CONFIG_MEDIA_TUNER_XC2028=y ++CONFIG_MEDIA_TUNER_XC5000=y ++CONFIG_VIDEO_V4L2=y ++CONFIG_VIDEOBUF_GEN=y ++CONFIG_VIDEOBUF_VMALLOC=y ++CONFIG_VIDEO_IR=y ++CONFIG_VIDEO_TVEEPROM=y ++CONFIG_VIDEO_TUNER=y ++CONFIG_VIDEO_CAPTURE_DRIVERS=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++CONFIG_VIDEO_FIXED_MINOR_RANGES=y ++# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set ++CONFIG_VIDEO_IR_I2C=y ++ ++# ++# Encoders/decoders and other helper chips ++# ++ ++# ++# Audio decoders ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TDA9875 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++CONFIG_VIDEO_MSP3400=y ++# CONFIG_VIDEO_CS5345 is not set ++CONFIG_VIDEO_CS53L32A=y ++# CONFIG_VIDEO_M52790 is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++CONFIG_VIDEO_WM8775=y ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_TCM825X is not set ++CONFIG_VIDEO_SAA711X=y ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++ ++# ++# Video and audio decoders ++# ++CONFIG_VIDEO_CX25840=y ++ ++# ++# MPEG video encoders ++# ++CONFIG_VIDEO_CX2341X=y ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++# CONFIG_VIDEO_VIVI is not set ++# CONFIG_VIDEO_SAA5246A is not set ++# CONFIG_VIDEO_SAA5249 is not set ++# CONFIG_SOC_CAMERA is not set ++CONFIG_V4L_USB_DRIVERS=y ++CONFIG_USB_VIDEO_CLASS=y ++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y ++CONFIG_USB_GSPCA=y ++CONFIG_USB_M5602=y ++CONFIG_USB_GSPCA_CONEX=y ++CONFIG_USB_GSPCA_ETOMS=y ++CONFIG_USB_GSPCA_FINEPIX=y ++CONFIG_USB_GSPCA_MARS=y ++CONFIG_USB_GSPCA_OV519=y ++CONFIG_USB_GSPCA_PAC207=y ++CONFIG_USB_GSPCA_PAC7311=y ++CONFIG_USB_GSPCA_SONIXB=y ++CONFIG_USB_GSPCA_SONIXJ=y ++CONFIG_USB_GSPCA_SPCA500=y ++CONFIG_USB_GSPCA_SPCA501=y ++CONFIG_USB_GSPCA_SPCA505=y ++CONFIG_USB_GSPCA_SPCA506=y ++CONFIG_USB_GSPCA_SPCA508=y ++CONFIG_USB_GSPCA_SPCA561=y ++CONFIG_USB_GSPCA_STK014=y ++CONFIG_USB_GSPCA_SUNPLUS=y ++CONFIG_USB_GSPCA_T613=y ++CONFIG_USB_GSPCA_TV8532=y ++CONFIG_USB_GSPCA_VC032X=y ++CONFIG_USB_GSPCA_ZC3XX=y ++CONFIG_VIDEO_PVRUSB2=y ++CONFIG_VIDEO_PVRUSB2_SYSFS=y ++# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set ++CONFIG_VIDEO_EM28XX=y ++# CONFIG_VIDEO_EM28XX_ALSA is not set ++CONFIG_VIDEO_USBVISION=y ++CONFIG_USB_ET61X251=y ++CONFIG_USB_SN9C102=y ++CONFIG_USB_ZC0301=y ++CONFIG_USB_ZR364XX=y ++CONFIG_USB_STKWEBCAM=y ++CONFIG_USB_S2255=y ++CONFIG_VIDEO_SAMSUNG=y ++ ++# ++# FIMC configurations ++# ++CONFIG_VIDEO_FIMC=y ++CONFIG_VIDEO_FIMC_DEBUG=y ++# CONFIG_S5K4BA is not set ++# CONFIG_S5K3BA is not set ++CONFIG_OV965X=y ++CONFIG_OV965X_VGA=y ++# CONFIG_OV965X_QVGA is not set ++# CONFIG_OV965X_SVGA is not set ++# CONFIG_OV965X_SXGA is not set ++CONFIG_VIDEO_FIMC_CAM_CH=0 ++CONFIG_VIDEO_FIMC_CAM_RESET=1 ++CONFIG_VIDEO_POST=y ++CONFIG_VIDEO_MFC10=y ++CONFIG_VIDEO_MFC_DEBUG=y ++CONFIG_VIDEO_JPEG=y ++CONFIG_VIDEO_TV=y ++CONFIG_VIDEO_ROTATOR=y ++CONFIG_VIDEO_G2D=y ++CONFIG_VIDEO_G3D=y ++CONFIG_VIDEO_CMM=y ++ ++# ++# Reserved memory configurations ++# ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC=15360 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_POST=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC=6144 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_CMM=8192 ++# CONFIG_RADIO_ADAPTERS is not set ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++CONFIG_FB_S3C=y ++# CONFIG_FB_S3C_TFT480272 is not set ++# CONFIG_FB_S3C_TFT800480 is not set ++# CONFIG_FB_S3C_T240320 is not set ++# CONFIG_FB_S3C_TFT640480 is not set ++# CONFIG_FB_S3C_VGA1024768 is not set ++# CONFIG_FB_S3C_VGA800600 is not set ++CONFIG_FB_S3C_VGA640480=y ++# CONFIG_FB_S3C_EZVGA800600 is not set ++CONFIG_FB_S3C_BPP=y ++# CONFIG_FB_S3C_BPP_8 is not set ++CONFIG_FB_S3C_BPP_16=y ++# CONFIG_FB_S3C_BPP_24 is not set ++# CONFIG_FB_S3C_BPP_28 is not set ++# CONFIG_FB_S3C_BPP_32 is not set ++CONFIG_FB_S3C_NUM=4 ++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set ++CONFIG_FB_S3C_DOUBLE_BUFFERING=y ++# CONFIG_FB_S1D13XXX is not set ++CONFIG_BACKLIGHT_FRIENDLY_ARM=y ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_LOGO_LINUX_CLUT224=y ++# CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224 is not set ++CONFIG_SOUND=y ++CONFIG_SOUND_OSS_CORE=y ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++CONFIG_SND_OSSEMUL=y ++CONFIG_SND_MIXER_OSS=y ++CONFIG_SND_PCM_OSS=y ++CONFIG_SND_PCM_OSS_PLUGINS=y ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_VMASTER=y ++CONFIG_SND_AC97_CODEC=y ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++# CONFIG_SND_AC97_POWER_SAVE is not set ++CONFIG_SND_ARM=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_CAIAQ is not set ++CONFIG_SND_SOC=y ++CONFIG_SND_SOC_AC97_BUS=y ++ ++# ++# SoC Audio for the Samsung S3C ++# ++CONFIG_SND_S3C64XX_SOC=y ++CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713=y ++# CONFIG_SOUND_WM9713_INPUT_STREAM_LINE is not set ++CONFIG_SOUND_WM9713_INPUT_STREAM_MIC=y ++CONFIG_SND_S3C6410_SOC_AC97=y ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8580 is not set ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990 is not set ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_S5M8751 is not set ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM9713=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_AC97_BUS=y ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_BRIGHT=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_DELL=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++CONFIG_USB_DEBUG=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++CONFIG_USB_DEVICE_CLASS=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_S3C_OTG_HOST is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_DPCM is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++CONFIG_USB_SERIAL=y ++# CONFIG_USB_SERIAL_CONSOLE is not set ++# CONFIG_USB_EZUSB is not set ++# CONFIG_USB_SERIAL_GENERIC is not set ++# CONFIG_USB_SERIAL_AIRCABLE is not set ++# CONFIG_USB_SERIAL_ARK3116 is not set ++# CONFIG_USB_SERIAL_BELKIN is not set ++# CONFIG_USB_SERIAL_CH341 is not set ++# CONFIG_USB_SERIAL_WHITEHEAT is not set ++# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set ++# CONFIG_USB_SERIAL_CP2101 is not set ++# CONFIG_USB_SERIAL_CYPRESS_M8 is not set ++# CONFIG_USB_SERIAL_EMPEG is not set ++# CONFIG_USB_SERIAL_FTDI_SIO is not set ++# CONFIG_USB_SERIAL_FUNSOFT is not set ++# CONFIG_USB_SERIAL_VISOR is not set ++# CONFIG_USB_SERIAL_IPAQ is not set ++# CONFIG_USB_SERIAL_IR is not set ++# CONFIG_USB_SERIAL_EDGEPORT is not set ++# CONFIG_USB_SERIAL_EDGEPORT_TI is not set ++# CONFIG_USB_SERIAL_GARMIN is not set ++# CONFIG_USB_SERIAL_IPW is not set ++# CONFIG_USB_SERIAL_IUU is not set ++# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set ++# CONFIG_USB_SERIAL_KEYSPAN is not set ++# CONFIG_USB_SERIAL_KLSI is not set ++# CONFIG_USB_SERIAL_KOBIL_SCT is not set ++# CONFIG_USB_SERIAL_MCT_U232 is not set ++# CONFIG_USB_SERIAL_MOS7720 is not set ++# CONFIG_USB_SERIAL_MOS7840 is not set ++# CONFIG_USB_SERIAL_MOTOROLA is not set ++# CONFIG_USB_SERIAL_NAVMAN is not set ++CONFIG_USB_SERIAL_PL2303=y ++# CONFIG_USB_SERIAL_OTI6858 is not set ++# CONFIG_USB_SERIAL_SPCP8X5 is not set ++# CONFIG_USB_SERIAL_HP4X is not set ++# CONFIG_USB_SERIAL_SAFE is not set ++# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set ++# CONFIG_USB_SERIAL_TI is not set ++# CONFIG_USB_SERIAL_CYBERJACK is not set ++# CONFIG_USB_SERIAL_XIRCOM is not set ++# CONFIG_USB_SERIAL_OPTION is not set ++# CONFIG_USB_SERIAL_OMNINET is not set ++# CONFIG_USB_SERIAL_DEBUG is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++CONFIG_USB_GADGET_S3C_OTGD=y ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++ ++# ++# NOTE: S3C OTG device role enables the controller driver below ++# ++CONFIG_USB_S3C_OTGD=y ++CONFIG_USB_GADGET_S3C_OTGD_DMA_MODE=y ++# CONFIG_USB_GADGET_S3C_OTGD_SLAVE_MODE is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FILE_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++CONFIG_SDIO_UART=y ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_S3C=y ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_NEW_LEDS is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_DRV_S3C=y ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++# CONFIG_EXT2_FS is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++CONFIG_GENERIC_ACL=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=936 ++CONFIG_FAT_DEFAULT_IOCHARSET="utf8" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_YAFFS_FS=y ++CONFIG_YAFFS_YAFFS1=y ++# CONFIG_YAFFS_9BYTE_TAGS is not set ++# CONFIG_YAFFS_DOES_ECC is not set ++CONFIG_YAFFS_YAFFS2=y ++CONFIG_YAFFS_AUTO_YAFFS2=y ++# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set ++# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set ++# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set ++CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y ++# CONFIG_JFFS2_FS is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_XATTR=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++CONFIG_UBIFS_FS_ZLIB=y ++# CONFIG_UBIFS_FS_DEBUG is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++# CONFIG_NFS_V3_ACL is not set ++# CONFIG_NFS_V4 is not set ++CONFIG_ROOT_NFS=y ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++CONFIG_NLS_CODEPAGE_936=y ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_PI_LIST=y ++# CONFIG_RT_MUTEX_TESTER is not set ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++CONFIG_DEBUG_SPINLOCK_SLEEP=y ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_DEBUG_USER=y ++CONFIG_DEBUG_ERRORS=y ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++CONFIG_DEBUG_S3C_PORT=y ++CONFIG_DEBUG_S3C_UART=0 ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++# CONFIG_CRYPTO_MANAGER is not set ++# CONFIG_CRYPTO_MANAGER2 is not set ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++# CONFIG_CRYPTO_MD5 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_DMA=y +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/config_mini6410_vga800x600 linux-2.6.28.6/config_mini6410_vga800x600 +--- linux-2.6.28/config_mini6410_vga800x600 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/config_mini6410_vga800x600 2010-07-20 12:00:29.000000000 +0200 +@@ -0,0 +1,1741 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.28.6 ++# Tue Jul 20 18:00:05 2010 ++# ++CONFIG_ARM=y ++# CONFIG_HAVE_PWM is not set ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_GENERIC_TIME is not set ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++CONFIG_NO_IOPORT=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_ZONE_DMA=y ++CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_LOCALVERSION="-FriendlyARM" ++CONFIG_LOCALVERSION_AUTO=y ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_GROUP_SCHED is not set ++CONFIG_SYSFS_DEPRECATED=y ++CONFIG_SYSFS_DEPRECATED_V2=y ++# CONFIG_RELAY is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="scripts/FriendlyARM.cpio" ++CONFIG_INITRAMFS_ROOT_UID=0 ++CONFIG_INITRAMFS_ROOT_GID=0 ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_COMPAT_BRK=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++# CONFIG_MARKERS is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++CONFIG_BLOCK=y ++# CONFIG_LBD is not set ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_LSF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++# CONFIG_IOSCHED_AS is not set ++# CONFIG_IOSCHED_DEADLINE is not set ++# CONFIG_IOSCHED_CFQ is not set ++# CONFIG_DEFAULT_AS is not set ++# CONFIG_DEFAULT_DEADLINE is not set ++# CONFIG_DEFAULT_CFQ is not set ++CONFIG_DEFAULT_NOOP=y ++CONFIG_DEFAULT_IOSCHED="noop" ++CONFIG_CLASSIC_RCU=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_LOKI is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++CONFIG_ARCH_S3C64XX=y ++# CONFIG_ARCH_S5P64XX is not set ++# CONFIG_ARCH_S5PC1XX is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_ARCH_MSM is not set ++CONFIG_PLAT_S3C64XX=y ++CONFIG_CPU_S3C6400_INIT=y ++CONFIG_CPU_S3C6400_CLOCK=y ++CONFIG_S3C64XX_SETUP_I2C0=y ++# CONFIG_S3C64XX_ADC is not set ++CONFIG_S3C64XX_DEV_FIMC0=y ++CONFIG_S3C64XX_DEV_FIMC1=y ++CONFIG_S3C64XX_SETUP_FIMC0=y ++CONFIG_S3C64XX_SETUP_FIMC1=y ++# CONFIG_S3C6410_PWM is not set ++CONFIG_NONE_PWM=y ++CONFIG_PLAT_S3C=y ++ ++# ++# Boot options ++# ++# CONFIG_S3C_BOOT_WATCHDOG is not set ++CONFIG_S3C_BOOT_ERROR_RESET=y ++ ++# ++# Power management ++# ++CONFIG_S3C_LOWLEVEL_UART_PORT=0 ++# CONFIG_SPLIT_ROOT_FILESYSTEM is not set ++CONFIG_S3C_GPIO_SPACE=0 ++CONFIG_S3C_GPIO_TRACK=y ++CONFIG_S3C_GPIO_PULL_UPDOWN=y ++CONFIG_S3C_GPIO_CFG_S3C24XX=y ++CONFIG_S3C_GPIO_CFG_S3C64XX=y ++CONFIG_S3C_DEV_HSMMC=y ++CONFIG_S3C_DEV_HSMMC1=y ++CONFIG_S3C_DEV_HSMMC2=y ++CONFIG_S3C_DMA_PL080=y ++CONFIG_CPU_S3C6410=y ++CONFIG_S3C6410_SETUP_SDHCI=y ++CONFIG_MACH_SMDK6410=y ++ ++# ++# SMDK6410 MMC/SD slot setup ++# ++CONFIG_SMDK6410_SD_CH0=y ++# CONFIG_SMDK6410_SD_CH1 is not set ++# CONFIG_SMDK6410_SD_CH2 is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_NOIFAR=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_THUMB is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++CONFIG_ARM_VIC=y ++CONFIG_DMABOUNCE=y ++ ++# ++# Bus support ++# ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=200 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_ARCH_FLATMEM_HAS_HOLES=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++CONFIG_VIRT_TO_BUS=y ++# CONFIG_UNEVICTABLE_LRU is not set ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_CMDLINE="" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# CPU Power Management ++# ++# CONFIG_CPU_FREQ is not set ++# CONFIG_CPU_IDLE is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_FPE_NWFPE=y ++# CONFIG_FPE_NWFPE_XP is not set ++# CONFIG_FPE_FASTFPE is not set ++# CONFIG_VFP is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++ ++# ++# Power management options ++# ++# CONFIG_PM is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_PACKET is not set ++CONFIG_UNIX=y ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_BOOTP=y ++CONFIG_IP_PNP_RARP=y ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_PHONET is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_STANDALONE=y ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++# CONFIG_MTD_CONCAT is not set ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_VERIFY_WRITE is not set ++# CONFIG_MTD_NAND_ECC_SMC is not set ++# CONFIG_MTD_NAND_MUSEUM_IDS is not set ++# CONFIG_MTD_NAND_GPIO is not set ++CONFIG_MTD_NAND_IDS=y ++CONFIG_MTD_NAND_S3C=y ++# CONFIG_MTD_NAND_S3C_DEBUG is not set ++CONFIG_MTD_NAND_S3C_HWECC=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ALAUDA is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# UBI - Unsorted block images ++# ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_RESERVE=1 ++# CONFIG_MTD_UBI_GLUEBI is not set ++ ++# ++# UBI debugging options ++# ++# CONFIG_MTD_UBI_DEBUG is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++# CONFIG_BLK_DEV_RAM is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++# CONFIG_SCSI_MULTI_LUN is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_PHYLIB is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=y ++# CONFIG_AX88796 is not set ++# CONFIG_SMC91X is not set ++CONFIG_DM9000=y ++CONFIG_DM9000_DEBUGLEVEL=4 ++# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set ++# CONFIG_SMC911X is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++# CONFIG_WLAN_80211 is not set ++# CONFIG_IWLWIFI_LEDS is not set ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_WAN is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=800 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=600 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++# CONFIG_TOUCHSCREEN_S3C is not set ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_WM97XX is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++# CONFIG_DEVKMEM is not set ++CONFIG_LEDS_MINI6410=y ++CONFIG_MINI6410_HELLO_MODULE=m ++CONFIG_MINI6410_BUTTONS=y ++CONFIG_MINI6410_BUZZER=y ++# CONFIG_MINI6410_ADC is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_SAMSUNG=y ++CONFIG_SERIAL_SAMSUNG_UARTS=4 ++# CONFIG_SERIAL_SAMSUNG_DEBUG is not set ++CONFIG_SERIAL_SAMSUNG_CONSOLE=y ++CONFIG_SERIAL_S3C6400=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_NVRAM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_S3C_MEM is not set ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_HELPER_AUTO is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++CONFIG_I2C_S3C2410=y ++# CONFIG_I2C_SIMTEC is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_STUB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_DS1682 is not set ++# CONFIG_AT24 is not set ++# CONFIG_SENSORS_EEPROM is not set ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_PCF8575 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++# CONFIG_SPI is not set ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++# CONFIG_DEBUG_GPIO is not set ++# CONFIG_GPIO_SYSFS is not set ++ ++# ++# Memory mapped GPIO expanders: ++# ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_THERMAL_HWMON is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++CONFIG_S3C2410_WATCHDOG=y ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_UCB1400_CORE is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM8350_I2C is not set ++ ++# ++# Multimedia devices ++# ++ ++# ++# Multimedia core support ++# ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2_COMMON=y ++# CONFIG_VIDEO_ALLOW_V4L1 is not set ++CONFIG_VIDEO_V4L1_COMPAT=y ++# CONFIG_DVB_CORE is not set ++CONFIG_VIDEO_MEDIA=y ++ ++# ++# Multimedia drivers ++# ++# CONFIG_MEDIA_ATTACH is not set ++CONFIG_MEDIA_TUNER=y ++# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set ++CONFIG_MEDIA_TUNER_SIMPLE=y ++CONFIG_MEDIA_TUNER_TDA8290=y ++CONFIG_MEDIA_TUNER_TDA9887=y ++CONFIG_MEDIA_TUNER_TEA5761=y ++CONFIG_MEDIA_TUNER_TEA5767=y ++CONFIG_MEDIA_TUNER_MT20XX=y ++CONFIG_MEDIA_TUNER_XC2028=y ++CONFIG_MEDIA_TUNER_XC5000=y ++CONFIG_VIDEO_V4L2=y ++CONFIG_VIDEOBUF_GEN=y ++CONFIG_VIDEOBUF_VMALLOC=y ++CONFIG_VIDEO_IR=y ++CONFIG_VIDEO_TVEEPROM=y ++CONFIG_VIDEO_TUNER=y ++CONFIG_VIDEO_CAPTURE_DRIVERS=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++CONFIG_VIDEO_FIXED_MINOR_RANGES=y ++# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set ++CONFIG_VIDEO_IR_I2C=y ++ ++# ++# Encoders/decoders and other helper chips ++# ++ ++# ++# Audio decoders ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TDA9875 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++CONFIG_VIDEO_MSP3400=y ++# CONFIG_VIDEO_CS5345 is not set ++CONFIG_VIDEO_CS53L32A=y ++# CONFIG_VIDEO_M52790 is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++CONFIG_VIDEO_WM8775=y ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_TCM825X is not set ++CONFIG_VIDEO_SAA711X=y ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++ ++# ++# Video and audio decoders ++# ++CONFIG_VIDEO_CX25840=y ++ ++# ++# MPEG video encoders ++# ++CONFIG_VIDEO_CX2341X=y ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++# CONFIG_VIDEO_VIVI is not set ++# CONFIG_VIDEO_SAA5246A is not set ++# CONFIG_VIDEO_SAA5249 is not set ++# CONFIG_SOC_CAMERA is not set ++CONFIG_V4L_USB_DRIVERS=y ++CONFIG_USB_VIDEO_CLASS=y ++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y ++CONFIG_USB_GSPCA=y ++CONFIG_USB_M5602=y ++CONFIG_USB_GSPCA_CONEX=y ++CONFIG_USB_GSPCA_ETOMS=y ++CONFIG_USB_GSPCA_FINEPIX=y ++CONFIG_USB_GSPCA_MARS=y ++CONFIG_USB_GSPCA_OV519=y ++CONFIG_USB_GSPCA_PAC207=y ++CONFIG_USB_GSPCA_PAC7311=y ++CONFIG_USB_GSPCA_SONIXB=y ++CONFIG_USB_GSPCA_SONIXJ=y ++CONFIG_USB_GSPCA_SPCA500=y ++CONFIG_USB_GSPCA_SPCA501=y ++CONFIG_USB_GSPCA_SPCA505=y ++CONFIG_USB_GSPCA_SPCA506=y ++CONFIG_USB_GSPCA_SPCA508=y ++CONFIG_USB_GSPCA_SPCA561=y ++CONFIG_USB_GSPCA_STK014=y ++CONFIG_USB_GSPCA_SUNPLUS=y ++CONFIG_USB_GSPCA_T613=y ++CONFIG_USB_GSPCA_TV8532=y ++CONFIG_USB_GSPCA_VC032X=y ++CONFIG_USB_GSPCA_ZC3XX=y ++CONFIG_VIDEO_PVRUSB2=y ++CONFIG_VIDEO_PVRUSB2_SYSFS=y ++# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set ++CONFIG_VIDEO_EM28XX=y ++# CONFIG_VIDEO_EM28XX_ALSA is not set ++CONFIG_VIDEO_USBVISION=y ++CONFIG_USB_ET61X251=y ++CONFIG_USB_SN9C102=y ++CONFIG_USB_ZC0301=y ++CONFIG_USB_ZR364XX=y ++CONFIG_USB_STKWEBCAM=y ++CONFIG_USB_S2255=y ++CONFIG_VIDEO_SAMSUNG=y ++ ++# ++# FIMC configurations ++# ++CONFIG_VIDEO_FIMC=y ++CONFIG_VIDEO_FIMC_DEBUG=y ++# CONFIG_S5K4BA is not set ++# CONFIG_S5K3BA is not set ++CONFIG_OV965X=y ++CONFIG_OV965X_VGA=y ++# CONFIG_OV965X_QVGA is not set ++# CONFIG_OV965X_SVGA is not set ++# CONFIG_OV965X_SXGA is not set ++CONFIG_VIDEO_FIMC_CAM_CH=0 ++CONFIG_VIDEO_FIMC_CAM_RESET=1 ++CONFIG_VIDEO_POST=y ++CONFIG_VIDEO_MFC10=y ++CONFIG_VIDEO_MFC_DEBUG=y ++CONFIG_VIDEO_JPEG=y ++CONFIG_VIDEO_TV=y ++CONFIG_VIDEO_ROTATOR=y ++CONFIG_VIDEO_G2D=y ++CONFIG_VIDEO_G3D=y ++CONFIG_VIDEO_CMM=y ++ ++# ++# Reserved memory configurations ++# ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC=15360 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_POST=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_TV=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC=6144 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_JPEG=8192 ++CONFIG_VIDEO_SAMSUNG_MEMSIZE_CMM=8192 ++# CONFIG_RADIO_ADAPTERS is not set ++# CONFIG_DAB is not set ++ ++# ++# Graphics support ++# ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++CONFIG_FB_S3C=y ++# CONFIG_FB_S3C_TFT480272 is not set ++# CONFIG_FB_S3C_TFT800480 is not set ++# CONFIG_FB_S3C_T240320 is not set ++# CONFIG_FB_S3C_TFT640480 is not set ++# CONFIG_FB_S3C_VGA1024768 is not set ++CONFIG_FB_S3C_VGA800600=y ++# CONFIG_FB_S3C_VGA640480 is not set ++# CONFIG_FB_S3C_EZVGA800600 is not set ++CONFIG_FB_S3C_BPP=y ++# CONFIG_FB_S3C_BPP_8 is not set ++CONFIG_FB_S3C_BPP_16=y ++# CONFIG_FB_S3C_BPP_24 is not set ++# CONFIG_FB_S3C_BPP_28 is not set ++# CONFIG_FB_S3C_BPP_32 is not set ++CONFIG_FB_S3C_NUM=4 ++# CONFIG_FB_S3C_VIRTUAL_SCREEN is not set ++CONFIG_FB_S3C_DOUBLE_BUFFERING=y ++# CONFIG_FB_S1D13XXX is not set ++CONFIG_BACKLIGHT_FRIENDLY_ARM=y ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_LOGO_LINUX_CLUT224=y ++# CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224 is not set ++CONFIG_SOUND=y ++CONFIG_SOUND_OSS_CORE=y ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_SEQUENCER is not set ++CONFIG_SND_OSSEMUL=y ++CONFIG_SND_MIXER_OSS=y ++CONFIG_SND_PCM_OSS=y ++CONFIG_SND_PCM_OSS_PLUGINS=y ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++CONFIG_SND_VMASTER=y ++CONFIG_SND_AC97_CODEC=y ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++# CONFIG_SND_AC97_POWER_SAVE is not set ++CONFIG_SND_ARM=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_CAIAQ is not set ++CONFIG_SND_SOC=y ++CONFIG_SND_SOC_AC97_BUS=y ++ ++# ++# SoC Audio for the Samsung S3C ++# ++CONFIG_SND_S3C64XX_SOC=y ++CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713=y ++# CONFIG_SOUND_WM9713_INPUT_STREAM_LINE is not set ++CONFIG_SOUND_WM9713_INPUT_STREAM_MIC=y ++CONFIG_SND_S3C6410_SOC_AC97=y ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8580 is not set ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990 is not set ++# CONFIG_SND_S3C64XX_SOC_SMDK6410_S5M8751 is not set ++# CONFIG_SND_SOC_ALL_CODECS is not set ++CONFIG_SND_SOC_WM9713=y ++# CONFIG_SOUND_PRIME is not set ++CONFIG_AC97_BUS=y ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++CONFIG_HID_DEBUG=y ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_COMPAT is not set ++CONFIG_HID_A4TECH=y ++CONFIG_HID_APPLE=y ++CONFIG_HID_BELKIN=y ++CONFIG_HID_BRIGHT=y ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++CONFIG_HID_CYPRESS=y ++CONFIG_HID_DELL=y ++CONFIG_HID_EZKEY=y ++CONFIG_HID_GYRATION=y ++CONFIG_HID_LOGITECH=y ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++CONFIG_HID_PANTHERLORD=y ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=y ++CONFIG_HID_SAMSUNG=y ++CONFIG_HID_SONY=y ++CONFIG_HID_SUNPLUS=y ++# CONFIG_THRUSTMASTER_FF is not set ++# CONFIG_ZEROPLUS_FF is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++CONFIG_USB_DEBUG=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++CONFIG_USB_DEVICE_CLASS=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set ++# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++# CONFIG_USB_S3C_OTG_HOST is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_GADGET_MUSB_HDRC is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; ++# ++ ++# ++# see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_DPCM is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++CONFIG_USB_SERIAL=y ++# CONFIG_USB_SERIAL_CONSOLE is not set ++# CONFIG_USB_EZUSB is not set ++# CONFIG_USB_SERIAL_GENERIC is not set ++# CONFIG_USB_SERIAL_AIRCABLE is not set ++# CONFIG_USB_SERIAL_ARK3116 is not set ++# CONFIG_USB_SERIAL_BELKIN is not set ++# CONFIG_USB_SERIAL_CH341 is not set ++# CONFIG_USB_SERIAL_WHITEHEAT is not set ++# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set ++# CONFIG_USB_SERIAL_CP2101 is not set ++# CONFIG_USB_SERIAL_CYPRESS_M8 is not set ++# CONFIG_USB_SERIAL_EMPEG is not set ++# CONFIG_USB_SERIAL_FTDI_SIO is not set ++# CONFIG_USB_SERIAL_FUNSOFT is not set ++# CONFIG_USB_SERIAL_VISOR is not set ++# CONFIG_USB_SERIAL_IPAQ is not set ++# CONFIG_USB_SERIAL_IR is not set ++# CONFIG_USB_SERIAL_EDGEPORT is not set ++# CONFIG_USB_SERIAL_EDGEPORT_TI is not set ++# CONFIG_USB_SERIAL_GARMIN is not set ++# CONFIG_USB_SERIAL_IPW is not set ++# CONFIG_USB_SERIAL_IUU is not set ++# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set ++# CONFIG_USB_SERIAL_KEYSPAN is not set ++# CONFIG_USB_SERIAL_KLSI is not set ++# CONFIG_USB_SERIAL_KOBIL_SCT is not set ++# CONFIG_USB_SERIAL_MCT_U232 is not set ++# CONFIG_USB_SERIAL_MOS7720 is not set ++# CONFIG_USB_SERIAL_MOS7840 is not set ++# CONFIG_USB_SERIAL_MOTOROLA is not set ++# CONFIG_USB_SERIAL_NAVMAN is not set ++CONFIG_USB_SERIAL_PL2303=y ++# CONFIG_USB_SERIAL_OTI6858 is not set ++# CONFIG_USB_SERIAL_SPCP8X5 is not set ++# CONFIG_USB_SERIAL_HP4X is not set ++# CONFIG_USB_SERIAL_SAFE is not set ++# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set ++# CONFIG_USB_SERIAL_TI is not set ++# CONFIG_USB_SERIAL_CYBERJACK is not set ++# CONFIG_USB_SERIAL_XIRCOM is not set ++# CONFIG_USB_SERIAL_OPTION is not set ++# CONFIG_USB_SERIAL_OMNINET is not set ++# CONFIG_USB_SERIAL_DEBUG is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_BERRY_CHARGE is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_VST is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_SELECTED=y ++# CONFIG_USB_GADGET_AT91 is not set ++# CONFIG_USB_GADGET_ATMEL_USBA is not set ++# CONFIG_USB_GADGET_FSL_USB2 is not set ++# CONFIG_USB_GADGET_LH7A40X is not set ++# CONFIG_USB_GADGET_OMAP is not set ++# CONFIG_USB_GADGET_PXA25X is not set ++# CONFIG_USB_GADGET_PXA27X is not set ++# CONFIG_USB_GADGET_S3C2410 is not set ++CONFIG_USB_GADGET_S3C_OTGD=y ++# CONFIG_USB_GADGET_M66592 is not set ++# CONFIG_USB_GADGET_AMD5536UDC is not set ++# CONFIG_USB_GADGET_FSL_QE is not set ++# CONFIG_USB_GADGET_NET2280 is not set ++# CONFIG_USB_GADGET_GOKU is not set ++# CONFIG_USB_GADGET_DUMMY_HCD is not set ++ ++# ++# NOTE: S3C OTG device role enables the controller driver below ++# ++CONFIG_USB_S3C_OTGD=y ++CONFIG_USB_GADGET_S3C_OTGD_DMA_MODE=y ++# CONFIG_USB_GADGET_S3C_OTGD_SLAVE_MODE is not set ++CONFIG_USB_GADGET_DUALSPEED=y ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FILE_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++# CONFIG_USB_CDC_COMPOSITE is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_BOUNCE=y ++CONFIG_SDIO_UART=y ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_S3C=y ++# CONFIG_MEMSTICK is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_NEW_LEDS is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++ ++# ++# SPI RTC drivers ++# ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++CONFIG_RTC_DRV_S3C=y ++# CONFIG_DMADEVICES is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_UIO is not set ++ ++# ++# File systems ++# ++# CONFIG_EXT2_FS is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4_FS is not set ++CONFIG_JBD=y ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++# CONFIG_XFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++CONFIG_GENERIC_ACL=y ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=936 ++CONFIG_FAT_DEFAULT_IOCHARSET="utf8" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_YAFFS_FS=y ++CONFIG_YAFFS_YAFFS1=y ++# CONFIG_YAFFS_9BYTE_TAGS is not set ++# CONFIG_YAFFS_DOES_ECC is not set ++CONFIG_YAFFS_YAFFS2=y ++CONFIG_YAFFS_AUTO_YAFFS2=y ++# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set ++# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set ++# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set ++CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y ++# CONFIG_JFFS2_FS is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_XATTR=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++CONFIG_UBIFS_FS_ZLIB=y ++# CONFIG_UBIFS_FS_DEBUG is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++# CONFIG_NFS_V3_ACL is not set ++# CONFIG_NFS_V4 is not set ++CONFIG_ROOT_NFS=y ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_REGISTER_V4 is not set ++# CONFIG_RPCSEC_GSS_KRB5 is not set ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++CONFIG_NLS_CODEPAGE_936=y ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++CONFIG_MAGIC_SYSRQ=y ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++CONFIG_DETECT_SOFTLOCKUP=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_PI_LIST=y ++# CONFIG_RT_MUTEX_TESTER is not set ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++CONFIG_DEBUG_SPINLOCK_SLEEP=y ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_SG is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_CPU_STALL_DETECTOR is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_HAVE_FUNCTION_TRACER=y ++ ++# ++# Tracers ++# ++# CONFIG_FUNCTION_TRACER is not set ++# CONFIG_SCHED_TRACER is not set ++# CONFIG_CONTEXT_SWITCH_TRACER is not set ++# CONFIG_BOOT_TRACER is not set ++# CONFIG_STACK_TRACER is not set ++# CONFIG_DYNAMIC_PRINTK_DEBUG is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_DEBUG_USER=y ++CONFIG_DEBUG_ERRORS=y ++# CONFIG_DEBUG_STACK_USAGE is not set ++CONFIG_DEBUG_LL=y ++# CONFIG_DEBUG_ICEDCC is not set ++CONFIG_DEBUG_S3C_PORT=y ++CONFIG_DEBUG_S3C_UART=0 ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++# CONFIG_SECURITY_FILE_CAPABILITIES is not set ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++# CONFIG_CRYPTO_FIPS is not set ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++# CONFIG_CRYPTO_MANAGER is not set ++# CONFIG_CRYPTO_MANAGER2 is not set ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_MD4 is not set ++# CONFIG_CRYPTO_MD5 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_HW=y ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_PLIST=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_DMA=y +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/char/Kconfig linux-2.6.28.6/drivers/char/Kconfig +--- linux-2.6.28/drivers/char/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/char/Kconfig 2010-04-01 07:47:50.000000000 +0200 +@@ -97,6 +97,42 @@ + kind of kernel debugging operations. + When in doubt, say "N". + ++config LEDS_MINI6410 ++ tristate "LED Support for Mini6410 GPIO LEDs" ++ depends on CPU_S3C6410 ++ default y ++ help ++ This option enables support for LEDs connected to GPIO lines ++ on Mini6410 boards. ++ ++config MINI6410_HELLO_MODULE ++ tristate "Mini6410 module sample" ++ depends on CPU_S3C6410 ++ help ++ Mini6410 module sample. ++ ++config MINI6410_BUTTONS ++ tristate "Buttons driver for FriendlyARM Mini6410 development boards" ++ depends on CPU_S3C6410 ++ default y ++ help ++ this is buttons driver for FriendlyARM Mini6410 development boards ++ ++config MINI6410_BUZZER ++ tristate "Buzzer driver for FriendlyARM Mini6410 development boards" ++ depends on CPU_S3C6410 ++ default y ++ help ++ this is buzzer driver for FriendlyARM Mini6410 development boards ++ ++config MINI6410_ADC ++ bool "ADC driver for FriendlyARM Mini6410 development boards" ++ depends on CPU_S3C6410 ++ default y ++ help ++ this is ADC driver for FriendlyARM Mini6410 development boards ++ Notes: the touch-screen-driver required this option ++ + config SERIAL_NONSTANDARD + bool "Non-standard serial port support" + depends on HAS_IOMEM +@@ -1073,5 +1109,14 @@ + + source "drivers/s390/char/Kconfig" + ++config S3C_MEM ++ bool "Support for /dev/s3c-mem" ++ default y ++ ---help--- ++ If you do say Y here, you can allocate physically linear memories from system memory. ++ And you can share the memory at the other process using re-allocation ioctl. ++ ++ If unsure, say Y. ++ + endmenu + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/char/Makefile linux-2.6.28.6/drivers/char/Makefile +--- linux-2.6.28/drivers/char/Makefile 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/char/Makefile 2010-04-01 07:39:48.000000000 +0200 +@@ -109,6 +109,14 @@ + obj-$(CONFIG_JS_RTC) += js-rtc.o + js-rtc-y = rtc.o + ++obj-$(CONFIG_S3C_MEM) += s3c_mem.o ++ ++obj-$(CONFIG_LEDS_MINI6410) += mini6410_leds.o ++obj-$(CONFIG_MINI6410_HELLO_MODULE) += mini6410_hello_module.o ++obj-$(CONFIG_MINI6410_BUTTONS) += mini6410_buttons.o ++obj-$(CONFIG_MINI6410_BUZZER) += mini6410_pwm.o ++obj-$(CONFIG_MINI6410_ADC) += mini6410_adc.o ++ + # Files generated that shall be removed upon make clean + clean-files := consolemap_deftbl.c defkeymap.c + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/char/mem.c linux-2.6.28.6/drivers/char/mem.c +--- linux-2.6.28/drivers/char/mem.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/char/mem.c 2009-04-30 09:36:38.000000000 +0200 +@@ -866,6 +866,16 @@ + }; + #endif + ++#ifdef CONFIG_S3C_MEM ++extern int s3c_mem_mmap(struct file* filp, struct vm_area_struct *vma); ++extern int s3c_mem_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg); ++ ++static const struct file_operations s3c_mem_fops = { ++ .ioctl = s3c_mem_ioctl, ++ .mmap = s3c_mem_mmap, ++}; ++#endif ++ + static ssize_t kmsg_write(struct file * file, const char __user * buf, + size_t count, loff_t *ppos) + { +@@ -938,6 +948,12 @@ + filp->f_op = &oldmem_fops; + break; + #endif ++ ++#ifdef CONFIG_S3C_MEM ++ case 13: ++ filp->f_op = &s3c_mem_fops; ++ break; ++#endif + default: + unlock_kernel(); + return -ENXIO; +@@ -974,6 +990,9 @@ + #ifdef CONFIG_CRASH_DUMP + {12,"oldmem", S_IRUSR | S_IWUSR | S_IRGRP, &oldmem_fops}, + #endif ++#ifdef CONFIG_S3C_MEM ++ {13,"s3c-mem", S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IROTH | S_IWOTH, &s3c_mem_fops}, ++#endif + }; + + static struct class *mem_class; +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/char/mini6410_adc.c linux-2.6.28.6/drivers/char/mini6410_adc.c +--- linux-2.6.28/drivers/char/mini6410_adc.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/char/mini6410_adc.c 2010-04-01 07:52:10.000000000 +0200 +@@ -0,0 +1,198 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "s3c24xx-adc.h" ++ ++#undef DEBUG ++//#define DEBUG ++#ifdef DEBUG ++#define DPRINTK(x...) {printk(__FUNCTION__"(%d): ",__LINE__);printk(##x);} ++#else ++#define DPRINTK(x...) (void)(0) ++#endif ++ ++#define DEVICE_NAME "adc" ++ ++static void __iomem *base_addr; ++ ++typedef struct { ++ wait_queue_head_t wait; ++ int channel; ++ int prescale; ++}ADC_DEV; ++ ++DECLARE_MUTEX(ADC_LOCK); ++static int OwnADC = 0; ++ ++static ADC_DEV adcdev; ++static volatile int ev_adc = 0; ++static int adc_data; ++ ++static struct clk *adc_clock; ++ ++#define ADCCON (*(volatile unsigned long *)(base_addr + S3C2410_ADCCON)) //ADC control ++#define ADCTSC (*(volatile unsigned long *)(base_addr + S3C2410_ADCTSC)) //ADC touch screen control ++#define ADCDLY (*(volatile unsigned long *)(base_addr + S3C2410_ADCDLY)) //ADC start or Interval Delay ++#define ADCDAT0 (*(volatile unsigned long *)(base_addr + S3C2410_ADCDAT0)) //ADC conversion data 0 ++#define ADCDAT1 (*(volatile unsigned long *)(base_addr + S3C2410_ADCDAT1)) //ADC conversion data 1 ++#define ADCUPDN (*(volatile unsigned long *)(base_addr + 0x14)) //Stylus Up/Down interrupt status ++ ++#define PRESCALE_DIS (0 << 14) ++#define PRESCALE_EN (1 << 14) ++#define PRSCVL(x) ((x) << 6) ++#define ADC_INPUT(x) ((x) << 3) ++#define ADC_START (1 << 0) ++#define ADC_ENDCVT (1 << 15) ++ ++#define START_ADC_AIN(ch, prescale) \ ++ do{ \ ++ ADCCON = PRESCALE_EN | PRSCVL(prescale) | ADC_INPUT((ch)) ; \ ++ ADCCON |= ADC_START; \ ++ }while(0) ++ ++ ++static irqreturn_t adcdone_int_handler(int irq, void *dev_id) ++{ ++ if (OwnADC) { ++ adc_data = ADCDAT0 & 0x3ff; ++ ++ ev_adc = 1; ++ wake_up_interruptible(&adcdev.wait); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static ssize_t s3c2410_adc_read(struct file *filp, char *buffer, size_t count, loff_t *ppos) ++{ ++ char str[20]; ++ int value; ++ size_t len; ++ if (down_trylock(&ADC_LOCK) == 0) { ++ OwnADC = 1; ++ START_ADC_AIN(adcdev.channel, adcdev.prescale); ++ wait_event_interruptible(adcdev.wait, ev_adc); ++ ++ ev_adc = 0; ++ ++ DPRINTK("AIN[%d] = 0x%04x, %d\n", adcdev.channel, adc_data, ADCCON & 0x80 ? 1:0); ++ ++ value = adc_data; ++ sprintf(str,"%5d", adc_data); ++ copy_to_user(buffer, (char *)&adc_data, sizeof(adc_data)); ++ ++ OwnADC = 0; ++ up(&ADC_LOCK); ++ } else { ++ value = -1; ++ } ++ ++ len = sprintf(str, "%d\n", value); ++ if (count >= len) { ++ int r = copy_to_user(buffer, str, len); ++ return r ? r : len; ++ } else { ++ return -EINVAL; ++ } ++} ++ ++static int s3c2410_adc_open(struct inode *inode, struct file *filp) ++{ ++ init_waitqueue_head(&(adcdev.wait)); ++ ++ adcdev.channel=0; ++ adcdev.prescale=0xff; ++ ++ DPRINTK( "adc opened\n"); ++ return 0; ++} ++ ++static int s3c2410_adc_release(struct inode *inode, struct file *filp) ++{ ++ DPRINTK( "adc closed\n"); ++ return 0; ++} ++ ++ ++static struct file_operations dev_fops = { ++ owner: THIS_MODULE, ++ open: s3c2410_adc_open, ++ read: s3c2410_adc_read, ++ release: s3c2410_adc_release, ++}; ++ ++static struct miscdevice misc = { ++ .minor = MISC_DYNAMIC_MINOR, ++ .name = DEVICE_NAME, ++ .fops = &dev_fops, ++}; ++ ++static int __init dev_init(void) ++{ ++ int ret; ++ ++ base_addr=ioremap(S3C2410_PA_ADC,0x20); ++ if (base_addr == NULL) { ++ printk(KERN_ERR "Failed to remap register block\n"); ++ return -ENOMEM; ++ } ++ ++ adc_clock = clk_get(NULL, "adc"); ++ if (!adc_clock) { ++ printk(KERN_ERR "failed to get adc clock source\n"); ++ return -ENOENT; ++ } ++ clk_enable(adc_clock); ++ ++ /* normal ADC */ ++ ADCTSC = 0; ++ ++ ret = request_irq(IRQ_ADC, adcdone_int_handler, IRQF_SHARED, DEVICE_NAME, &adcdev); ++ if (ret) { ++ iounmap(base_addr); ++ return ret; ++ } ++ ++ ret = misc_register(&misc); ++ ++ printk (DEVICE_NAME"\tinitialized\n"); ++ return ret; ++} ++ ++static void __exit dev_exit(void) ++{ ++ free_irq(IRQ_ADC, &adcdev); ++ iounmap(base_addr); ++ ++ if (adc_clock) { ++ clk_disable(adc_clock); ++ clk_put(adc_clock); ++ adc_clock = NULL; ++ } ++ ++ misc_deregister(&misc); ++} ++ ++EXPORT_SYMBOL(ADC_LOCK); ++module_init(dev_init); ++module_exit(dev_exit); ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("FriendlyARM Inc."); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/char/mini6410_buttons.c linux-2.6.28.6/drivers/char/mini6410_buttons.c +--- linux-2.6.28/drivers/char/mini6410_buttons.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/char/mini6410_buttons.c 2010-05-17 07:20:14.000000000 +0200 +@@ -0,0 +1,190 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++#define DEVICE_NAME "buttons" ++ ++struct button_irq_desc { ++ int irq; ++ int number; ++ char *name; ++}; ++ ++static struct button_irq_desc button_irqs [] = { ++ {IRQ_EINT( 0), 0, "KEY0"}, ++ {IRQ_EINT( 1), 1, "KEY1"}, ++ {IRQ_EINT( 2), 2, "KEY2"}, ++ {IRQ_EINT( 3), 3, "KEY3"}, ++ {IRQ_EINT( 4), 4, "KEY4"}, ++ {IRQ_EINT( 5), 5, "KEY5"}, ++ {IRQ_EINT(19), 6, "KEY6"}, ++ {IRQ_EINT(20), 7, "KEY7"}, ++}; ++static volatile char key_values [] = {'0', '0', '0', '0', '0', '0', '0', '0'}; ++ ++static DECLARE_WAIT_QUEUE_HEAD(button_waitq); ++ ++static volatile int ev_press = 0; ++ ++ ++static irqreturn_t buttons_interrupt(int irq, void *dev_id) ++{ ++ struct button_irq_desc *button_irqs = (struct button_irq_desc *)dev_id; ++ int down; ++ int number; ++ unsigned tmp; ++ ++ udelay(0); ++ number = button_irqs->number; ++ switch(number) { ++ case 0: case 1: case 2: case 3: case 4: case 5: ++ tmp = readl(S3C64XX_GPNDAT); ++ down = !(tmp & (1<= 0; i--) { ++ if (button_irqs[i].irq < 0) { ++ continue; ++ } ++ disable_irq(button_irqs[i].irq); ++ free_irq(button_irqs[i].irq, (void *)&button_irqs[i]); ++ } ++ return -EBUSY; ++ } ++ ++ ev_press = 1; ++ ++ return 0; ++} ++ ++ ++static int s3c64xx_buttons_close(struct inode *inode, struct file *file) ++{ ++ int i; ++ ++ for (i = 0; i < sizeof(button_irqs)/sizeof(button_irqs[0]); i++) { ++ if (button_irqs[i].irq < 0) { ++ continue; ++ } ++ free_irq(button_irqs[i].irq, (void *)&button_irqs[i]); ++ } ++ ++ return 0; ++} ++ ++ ++static int s3c64xx_buttons_read(struct file *filp, char __user *buff, size_t count, loff_t *offp) ++{ ++ unsigned long err; ++ ++ if (!ev_press) { ++ if (filp->f_flags & O_NONBLOCK) ++ return -EAGAIN; ++ else ++ wait_event_interruptible(button_waitq, ev_press); ++ } ++ ++ ev_press = 0; ++ ++ err = copy_to_user((void *)buff, (const void *)(&key_values), min(sizeof(key_values), count)); ++ ++ return err ? -EFAULT : min(sizeof(key_values), count); ++} ++ ++static unsigned int s3c64xx_buttons_poll( struct file *file, struct poll_table_struct *wait) ++{ ++ unsigned int mask = 0; ++ poll_wait(file, &button_waitq, wait); ++ if (ev_press) ++ mask |= POLLIN | POLLRDNORM; ++ return mask; ++} ++ ++ ++static struct file_operations dev_fops = { ++ .owner = THIS_MODULE, ++ .open = s3c64xx_buttons_open, ++ .release = s3c64xx_buttons_close, ++ .read = s3c64xx_buttons_read, ++ .poll = s3c64xx_buttons_poll, ++}; ++ ++static struct miscdevice misc = { ++ .minor = MISC_DYNAMIC_MINOR, ++ .name = DEVICE_NAME, ++ .fops = &dev_fops, ++}; ++ ++static int __init dev_init(void) ++{ ++ int ret; ++ ++ ret = misc_register(&misc); ++ ++ printk (DEVICE_NAME"\tinitialized\n"); ++ ++ return ret; ++} ++ ++static void __exit dev_exit(void) ++{ ++ misc_deregister(&misc); ++} ++ ++module_init(dev_init); ++module_exit(dev_exit); ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("FriendlyARM Inc."); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/char/mini6410_hello_module.c linux-2.6.28.6/drivers/char/mini6410_hello_module.c +--- linux-2.6.28/drivers/char/mini6410_hello_module.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/char/mini6410_hello_module.c 2010-04-01 07:54:11.000000000 +0200 +@@ -0,0 +1,18 @@ ++#include ++#include ++ ++ ++static int __init mini6410_hello_module_init(void) ++{ ++ printk("Hello, Mini6410 module is installed !\n"); ++ return 0; ++} ++ ++static void __exit mini6410_hello_module_cleanup(void) ++{ ++ printk("Good-bye, Mini6410 module was removed!\n"); ++} ++ ++module_init(mini6410_hello_module_init); ++module_exit(mini6410_hello_module_cleanup); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/char/mini6410_leds.c linux-2.6.28.6/drivers/char/mini6410_leds.c +--- linux-2.6.28/drivers/char/mini6410_leds.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/char/mini6410_leds.c 2010-04-01 04:47:34.000000000 +0200 +@@ -0,0 +1,99 @@ ++#include ++#include ++#include ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++#define DEVICE_NAME "leds" ++ ++static int sbc2440_leds_ioctl( ++ struct inode *inode, ++ struct file *file, ++ unsigned int cmd, ++ unsigned long arg) ++{ ++ switch(cmd) { ++ unsigned tmp; ++ case 0: ++ case 1: ++ if (arg > 4) { ++ return -EINVAL; ++ } ++ tmp = readl(S3C64XX_GPKDAT); ++ tmp &= ~(1 << (4 + arg)); ++ tmp |= ( (!cmd) << (4 + arg) ); ++ writel(tmp, S3C64XX_GPKDAT); ++ //printk (DEVICE_NAME": %d %d\n", arg, cmd); ++ return 0; ++ default: ++ return -EINVAL; ++ } ++} ++ ++static struct file_operations dev_fops = { ++ .owner = THIS_MODULE, ++ .ioctl = sbc2440_leds_ioctl, ++}; ++ ++static struct miscdevice misc = { ++ .minor = MISC_DYNAMIC_MINOR, ++ .name = DEVICE_NAME, ++ .fops = &dev_fops, ++}; ++ ++static int __init dev_init(void) ++{ ++ int ret; ++ ++ { ++ unsigned tmp; ++ tmp = readl(S3C64XX_GPKCON); ++ tmp = (tmp & ~(0xffffU<<16))|(0x1111U<<16); ++ writel(tmp, S3C64XX_GPKCON); ++ ++ tmp = readl(S3C64XX_GPKDAT); ++ tmp |= (0xF << 4); ++ writel(tmp, S3C64XX_GPKDAT); ++ } ++ ++ ret = misc_register(&misc); ++ ++ printk (DEVICE_NAME"\tinitialized\n"); ++ ++ return ret; ++} ++ ++static void __exit dev_exit(void) ++{ ++ misc_deregister(&misc); ++} ++ ++module_init(dev_init); ++module_exit(dev_exit); ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("FriendlyARM Inc."); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/char/mini6410_pwm.c linux-2.6.28.6/drivers/char/mini6410_pwm.c +--- linux-2.6.28/drivers/char/mini6410_pwm.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/char/mini6410_pwm.c 2010-04-01 09:24:09.000000000 +0200 +@@ -0,0 +1,162 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#define DEVICE_NAME "pwm" ++ ++#define PWM_IOCTL_SET_FREQ 1 ++#define PWM_IOCTL_STOP 0 ++ ++static struct semaphore lock; ++ ++/* freq: pclk/50/16/65536 ~ pclk/50/16 ++ * if pclk = 50MHz, freq is 1Hz to 62500Hz ++ * human ear : 20Hz~ 20000Hz ++ */ ++static void PWM_Set_Freq( unsigned long freq ) ++{ ++ unsigned long tcon; ++ unsigned long tcnt; ++ unsigned long tcfg1; ++ unsigned long tcfg0; ++ ++ struct clk *clk_p; ++ unsigned long pclk; ++ ++ unsigned tmp; ++ ++ tmp = readl(S3C64XX_GPFCON); ++ tmp &= ~(0x3U << 28); ++ tmp |= (0x2U << 28); ++ writel(tmp, S3C64XX_GPFCON); ++ ++ tcon = __raw_readl(S3C_TCON); ++ tcfg1 = __raw_readl(S3C_TCFG1); ++ tcfg0 = __raw_readl(S3C_TCFG0); ++ ++ //prescaler = 50 ++ tcfg0 &= ~S3C_TCFG_PRESCALER0_MASK; ++ tcfg0 |= (50 - 1); ++ ++ //mux = 1/16 ++ tcfg1 &= ~S3C_TCFG1_MUX0_MASK; ++ tcfg1 |= S3C_TCFG1_MUX0_DIV16; ++ ++ __raw_writel(tcfg1, S3C_TCFG1); ++ __raw_writel(tcfg0, S3C_TCFG0); ++ ++ clk_p = clk_get(NULL, "pclk"); ++ pclk = clk_get_rate(clk_p); ++ tcnt = (pclk/50/16)/freq; ++ ++ __raw_writel(tcnt, S3C_TCNTB(0)); ++ __raw_writel(tcnt/2, S3C_TCMPB(0)); ++ ++ tcon &= ~0x1f; ++ tcon |= 0xb; //disable deadzone, auto-reload, inv-off, update TCNTB0&TCMPB0, start timer 0 ++ __raw_writel(tcon, S3C_TCON); ++ ++ tcon &= ~2; //clear manual update bit ++ __raw_writel(tcon, S3C_TCON); ++} ++ ++void PWM_Stop( void ) ++{ ++ unsigned tmp; ++ tmp = readl(S3C64XX_GPFCON); ++ tmp &= ~(0x3U << 28); ++ writel(tmp, S3C64XX_GPFCON); ++} ++ ++static int s3c64xx_pwm_open(struct inode *inode, struct file *file) ++{ ++ if (!down_trylock(&lock)) ++ return 0; ++ else ++ return -EBUSY; ++} ++ ++ ++static int s3c64xx_pwm_close(struct inode *inode, struct file *file) ++{ ++ up(&lock); ++ return 0; ++} ++ ++ ++static int s3c64xx_pwm_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ switch (cmd) { ++ case PWM_IOCTL_SET_FREQ: ++ if (arg == 0) ++ return -EINVAL; ++ PWM_Set_Freq(arg); ++ break; ++ ++ case PWM_IOCTL_STOP: ++ default: ++ PWM_Stop(); ++ break; ++ } ++ ++ return 0; ++} ++ ++ ++static struct file_operations dev_fops = { ++ .owner = THIS_MODULE, ++ .open = s3c64xx_pwm_open, ++ .release = s3c64xx_pwm_close, ++ .ioctl = s3c64xx_pwm_ioctl, ++}; ++ ++static struct miscdevice misc = { ++ .minor = MISC_DYNAMIC_MINOR, ++ .name = DEVICE_NAME, ++ .fops = &dev_fops, ++}; ++ ++static int __init dev_init(void) ++{ ++ int ret; ++ ++ init_MUTEX(&lock); ++ ret = misc_register(&misc); ++ ++ printk (DEVICE_NAME"\tinitialized\n"); ++ return ret; ++} ++ ++static void __exit dev_exit(void) ++{ ++ misc_deregister(&misc); ++} ++ ++module_init(dev_init); ++module_exit(dev_exit); ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("FriendlyARM Inc."); ++MODULE_DESCRIPTION("S3C6410 PWM Driver"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/char/s3c_mem.c linux-2.6.28.6/drivers/char/s3c_mem.c +--- linux-2.6.28/drivers/char/s3c_mem.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/char/s3c_mem.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,397 @@ ++/* ++ * drivers/char/s3c_mem.c ++ * ++ * Revision 1.0 ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive for ++ * more details. ++ * ++ * S3C MEM driver for /dev/mem ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* error codes */ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++ ++#include "s3c_mem.h" ++ ++/*----------------------------------------------------------------------*/ ++/* M2M DMA client */ ++/*--------------------------------------------------------------------- */ ++ ++static struct s3c2410_dma_client s3c_m2m_dma_client = { ++ .name = "s3c-m2m-dma", ++}; ++ ++DECLARE_COMPLETION_ONSTACK(s3c_m2m_dma_complete); ++ ++static void *s3c_m2m_dma_done = &s3c_m2m_dma_complete; /* completion */ ++ ++static void s3c_m2m_dma_finish(struct s3c2410_dma_chan *dma_ch, void *buf_id, ++ int size, enum s3c2410_dma_buffresult result) ++{ ++ //printk("s3c_m2m_dma_finish() called\n"); ++ complete(s3c_m2m_dma_done); ++} ++/*----------------------------------------------------------------------*/ ++ ++static int flag = 0; ++ ++static unsigned int physical_address; ++ ++int s3c_mem_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ unsigned long *virt_addr; ++ struct mm_struct *mm = current->mm; ++ struct s3c_mem_alloc param; ++ struct s3c_mem_dma_param dma_param; ++ ++ switch (cmd) { ++ case S3C_MEM_ALLOC: ++ mutex_lock(&mem_alloc_lock); ++ if(copy_from_user(¶m, (struct s3c_mem_alloc *)arg, sizeof(struct s3c_mem_alloc))){ ++ mutex_unlock(&mem_alloc_lock); ++ return -EFAULT; ++ } ++ flag = MEM_ALLOC; ++ param.vir_addr = do_mmap(file, 0, param.size, PROT_READ|PROT_WRITE, MAP_SHARED, 0); ++ DEBUG("param.vir_addr = %08x, %d\n", param.vir_addr, __LINE__); ++ if(param.vir_addr == -EINVAL) { ++ printk("S3C_MEM_ALLOC FAILED\n"); ++ flag = 0; ++ mutex_unlock(&mem_alloc_lock); ++ return -EFAULT; ++ } ++ param.phy_addr = physical_address; ++ DEBUG("KERNEL MALLOC : param.phy_addr = 0x%X \t size = %d \t param.vir_addr = 0x%X, %d\n", param.phy_addr, param.size, param.vir_addr, __LINE__); ++ ++ if(copy_to_user((struct s3c_mem_alloc *)arg, ¶m, sizeof(struct s3c_mem_alloc))){ ++ flag = 0; ++ mutex_unlock(&mem_alloc_lock); ++ return -EFAULT; ++ } ++ flag = 0; ++ mutex_unlock(&mem_alloc_lock); ++ ++ break; ++ ++ case S3C_MEM_CACHEABLE_ALLOC: ++ mutex_lock(&mem_cacheable_alloc_lock); ++ if(copy_from_user(¶m, (struct s3c_mem_alloc *)arg, sizeof(struct s3c_mem_alloc))){ ++ mutex_unlock(&mem_cacheable_alloc_lock); ++ return -EFAULT; ++ } ++ flag = MEM_ALLOC_CACHEABLE; ++ param.vir_addr = do_mmap(file, 0, param.size, PROT_READ|PROT_WRITE, MAP_SHARED, 0); ++ DEBUG("param.vir_addr = %08x, %d\n", param.vir_addr, __LINE__); ++ if(param.vir_addr == -EINVAL) { ++ printk("S3C_MEM_ALLOC FAILED\n"); ++ flag = 0; ++ mutex_unlock(&mem_cacheable_alloc_lock); ++ return -EFAULT; ++ } ++ param.phy_addr = physical_address; ++ DEBUG("KERNEL MALLOC : param.phy_addr = 0x%X \t size = %d \t param.vir_addr = 0x%X, %d\n", param.phy_addr, param.size, param.vir_addr, __LINE__); ++ ++ if(copy_to_user((struct s3c_mem_alloc *)arg, ¶m, sizeof(struct s3c_mem_alloc))){ ++ flag = 0; ++ mutex_unlock(&mem_cacheable_alloc_lock); ++ return -EFAULT; ++ } ++ flag = 0; ++ mutex_unlock(&mem_cacheable_alloc_lock); ++ ++ break; ++ ++ case S3C_MEM_SHARE_ALLOC: ++ mutex_lock(&mem_share_alloc_lock); ++ if(copy_from_user(¶m, (struct s3c_mem_alloc *)arg, sizeof(struct s3c_mem_alloc))){ ++ mutex_unlock(&mem_share_alloc_lock); ++ return -EFAULT; ++ } ++ flag = MEM_ALLOC_SHARE; ++ physical_address = param.phy_addr; ++ DEBUG("param.phy_addr = %08x, %d\n", physical_address, __LINE__); ++ param.vir_addr = do_mmap(file, 0, param.size, PROT_READ|PROT_WRITE, MAP_SHARED, 0); ++ DEBUG("param.vir_addr = %08x, %d\n", param.vir_addr, __LINE__); ++ if(param.vir_addr == -EINVAL) { ++ printk("S3C_MEM_SHARE_ALLOC FAILED\n"); ++ flag = 0; ++ mutex_unlock(&mem_share_alloc_lock); ++ return -EFAULT; ++ } ++ DEBUG("MALLOC_SHARE : param.phy_addr = 0x%X \t size = %d \t param.vir_addr = 0x%X, %d\n", param.phy_addr, param.size, param.vir_addr, __LINE__); ++ ++ if(copy_to_user((struct s3c_mem_alloc *)arg, ¶m, sizeof(struct s3c_mem_alloc))){ ++ flag = 0; ++ mutex_unlock(&mem_share_alloc_lock); ++ return -EFAULT; ++ } ++ flag = 0; ++ mutex_unlock(&mem_share_alloc_lock); ++ ++ break; ++ ++ case S3C_MEM_CACHEABLE_SHARE_ALLOC: ++ mutex_lock(&mem_cacheable_share_alloc_lock); ++ if(copy_from_user(¶m, (struct s3c_mem_alloc *)arg, sizeof(struct s3c_mem_alloc))){ ++ mutex_unlock(&mem_cacheable_share_alloc_lock); ++ return -EFAULT; ++ } ++ flag = MEM_ALLOC_CACHEABLE_SHARE; ++ physical_address = param.phy_addr; ++ DEBUG("param.phy_addr = %08x, %d\n", physical_address, __LINE__); ++ param.vir_addr = do_mmap(file, 0, param.size, PROT_READ|PROT_WRITE, MAP_SHARED, 0); ++ DEBUG("param.vir_addr = %08x, %d\n", param.vir_addr, __LINE__); ++ if(param.vir_addr == -EINVAL) { ++ printk("S3C_MEM_SHARE_ALLOC FAILED\n"); ++ flag = 0; ++ mutex_unlock(&mem_cacheable_share_alloc_lock); ++ return -EFAULT; ++ } ++ DEBUG("MALLOC_SHARE : param.phy_addr = 0x%X \t size = %d \t param.vir_addr = 0x%X, %d\n", param.phy_addr, param.size, param.vir_addr, __LINE__); ++ ++ if(copy_to_user((struct s3c_mem_alloc *)arg, ¶m, sizeof(struct s3c_mem_alloc))){ ++ flag = 0; ++ mutex_unlock(&mem_cacheable_share_alloc_lock); ++ return -EFAULT; ++ } ++ flag = 0; ++ mutex_unlock(&mem_cacheable_share_alloc_lock); ++ ++ break; ++ ++ case S3C_MEM_FREE: ++ mutex_lock(&mem_free_lock); ++ if(copy_from_user(¶m, (struct s3c_mem_alloc *)arg, sizeof(struct s3c_mem_alloc))){ ++ mutex_unlock(&mem_free_lock); ++ return -EFAULT; ++ } ++ ++ DEBUG("KERNEL FREE : param.phy_addr = 0x%X \t size = %d \t param.vir_addr = 0x%X, %d\n", param.phy_addr, param.size, param.vir_addr, __LINE__); ++ ++ if (do_munmap(mm, param.vir_addr, param.size) < 0) { ++ printk("do_munmap() failed !!\n"); ++ mutex_unlock(&mem_free_lock); ++ return -EINVAL; ++ } ++ virt_addr = (unsigned long *)phys_to_virt(param.phy_addr); ++ ++ kfree(virt_addr); ++ param.size = 0; ++ DEBUG("do_munmap() succeed !!\n"); ++ ++ if(copy_to_user((struct s3c_mem_alloc *)arg, ¶m, sizeof(struct s3c_mem_alloc))){ ++ mutex_unlock(&mem_free_lock); ++ return -EFAULT; ++ } ++ ++ mutex_unlock(&mem_free_lock); ++ ++ break; ++ ++ case S3C_MEM_SHARE_FREE: ++ mutex_lock(&mem_share_free_lock); ++ if(copy_from_user(¶m, (struct s3c_mem_alloc *)arg, sizeof(struct s3c_mem_alloc))){ ++ mutex_unlock(&mem_share_free_lock); ++ return -EFAULT; ++ } ++ ++ DEBUG("MEM_SHARE_FREE : param.phy_addr = 0x%X \t size = %d \t param.vir_addr = 0x%X, %d\n", param.phy_addr, param.size, param.vir_addr, __LINE__); ++ ++ if (do_munmap(mm, param.vir_addr, param.size) < 0) { ++ printk("do_munmap() failed - MEM_SHARE_FREE!!\n"); ++ mutex_unlock(&mem_share_free_lock); ++ return -EINVAL; ++ } ++ ++ param.vir_addr = 0; ++ DEBUG("do_munmap() succeed !! - MEM_SHARE_FREE\n"); ++ ++ if(copy_to_user((struct s3c_mem_alloc *)arg, ¶m, sizeof(struct s3c_mem_alloc))){ ++ mutex_unlock(&mem_share_free_lock); ++ return -EFAULT; ++ } ++ ++ mutex_unlock(&mem_share_free_lock); ++ ++ break; ++ ++ ++ case S3C_MEM_DMA_COPY: ++ if(copy_from_user(&dma_param, (struct s3c_mem_dma_param *)arg, sizeof(struct s3c_mem_dma_param))) { ++ return -EFAULT; ++ } ++ //printk("S3C_MEM_DMA_COPY called\n"); ++ ++ if (s3c2410_dma_request(DMACH_3D_M2M, &s3c_m2m_dma_client, NULL)) { ++ printk(KERN_WARNING "Unable to get DMA channel.\n"); ++ return -1; ++ } ++ ++ s3c2410_dma_set_buffdone_fn(DMACH_3D_M2M, s3c_m2m_dma_finish); ++ ++ //dma_cache_maint(dma_param.src_addr,sizeof(unsigned long long), DMA_BIDIRECTIONAL); ++ ++ // printk("MEMCPY src=%p,dst=%p,size=%d\n", dma_param.src_addr,dma_param.dst_addr, dma_param.size); ++ ++ /* Source address */ ++ s3c2410_dma_devconfig(DMACH_3D_M2M, S3C_DMA_MEM2MEM, 1, dma_param.src_addr); ++ s3c2410_dma_config(DMACH_3D_M2M, 8, 0); ++ ++ /* Destination address : Data buffer address */ ++ s3c2410_dma_enqueue(DMACH_3D_M2M, 0, dma_param.dst_addr, dma_param.size); ++ s3c2410_dma_ctrl(DMACH_3D_M2M, S3C2410_DMAOP_START); ++ ++ wait_for_completion(&s3c_m2m_dma_complete); ++#if 0 ++ /* Destination address : Data buffer address */ ++ s3c2410_dma_enqueue(DMACH_3D_M2M, 0, 0x27a00000, 0x4000); ++ s3c2410_dma_enqueue(DMACH_3D_M2M, 0, 0x27a00000+0x10000, 0x4000); ++ s3c2410_dma_enqueue(DMACH_3D_M2M, 0, 0x27a00000+0x20000, 0x4000); ++ s3c2410_dma_ctrl(DMACH_3D_M2M, S3C2410_DMAOP_START); ++ ++ wait_for_completion(&s3c_m2m_dma_complete); ++ //wait_for_completion(&s3c_m2m_dma_complete); ++ //wait_for_completion(&s3c_m2m_dma_complete); ++ ++ s3c2410_dma_enqueue(DMACH_3D_M2M, 0, 0x27a00000+0x30000, 0x4000); ++ s3c2410_dma_enqueue(DMACH_3D_M2M, 0, 0x27a00000+0x40000, 0x4000); ++ s3c2410_dma_ctrl(DMACH_3D_M2M, S3C2410_DMAOP_START); ++ wait_for_completion(&s3c_m2m_dma_complete); ++ //wait_for_completion(&s3c_m2m_dma_complete); ++ ++ s3c2410_dma_enqueue(DMACH_3D_M2M, 0, 0x27a00000+0x50000, 0x4000); ++ s3c2410_dma_ctrl(DMACH_3D_M2M, S3C2410_DMAOP_START); ++ wait_for_completion(&s3c_m2m_dma_complete); ++#endif ++ ++ s3c2410_dma_free(DMACH_3D_M2M, &s3c_m2m_dma_client); ++ ++ if(copy_to_user((struct s3c_mem_dma_param *)arg, &dma_param, sizeof(struct s3c_mem_dma_param))) { ++ return -EFAULT; ++ } ++ ++ break; ++ ++ case S3C_MEM_DMA_SET: ++ if(copy_from_user(&dma_param, (struct s3c_mem_dma_param *)arg, sizeof(struct s3c_mem_dma_param))) { ++ return -EFAULT; ++ } ++ ++ if (s3c2410_dma_request(DMACH_3D_M2M, &s3c_m2m_dma_client, NULL)) { ++ printk(KERN_WARNING "Unable to get DMA channel.\n"); ++ return -1; ++ } ++ ++ s3c2410_dma_set_buffdone_fn(DMACH_3D_M2M, s3c_m2m_dma_finish); ++ ++ //dma_cache_maint(dma_param.src_addr,sizeof(unsigned long long), DMA_BIDIRECTIONAL); ++ ++// printk("MEMSET src=%p,dst=%p,size=%d\n", dma_param.src_addr,dma_param.dst_addr, dma_param.size); ++ ++ /* Source address */ ++ s3c2410_dma_devconfig(DMACH_3D_M2M, S3C_DMA_MEM2MEM_SET, 1,dma_param.src_addr); ++ s3c2410_dma_config(DMACH_3D_M2M, 8, 0); ++ ++ /* Destination address : Data buffer address */ ++ s3c2410_dma_enqueue(DMACH_3D_M2M, 0, dma_param.dst_addr, dma_param.size); ++ s3c2410_dma_ctrl(DMACH_3D_M2M, S3C2410_DMAOP_START); ++ ++ wait_for_completion(&s3c_m2m_dma_complete); ++ ++ s3c2410_dma_free(DMACH_3D_M2M, &s3c_m2m_dma_client); ++ ++ if(copy_to_user((struct s3c_mem_dma_param *)arg, &dma_param, sizeof(struct s3c_mem_dma_param))) { ++ return -EFAULT; ++ } ++ break; ++ ++ default: ++ DEBUG("s3c_mem_ioctl() : default !!\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++int s3c_mem_mmap(struct file* filp, struct vm_area_struct *vma) ++{ ++ unsigned long pageFrameNo=0, size, phys_addr; ++ unsigned long *virt_addr; ++ ++ size = vma->vm_end - vma->vm_start; ++ ++ switch (flag) { ++ case MEM_ALLOC : ++ case MEM_ALLOC_CACHEABLE : ++ virt_addr = (unsigned long *)kmalloc(size, GFP_DMA|GFP_ATOMIC); ++ ++ if (virt_addr == NULL) { ++ printk("kmalloc() failed !\n"); ++ return -EINVAL; ++ } ++ DEBUG("MMAP_KMALLOC : virt addr = 0x%08x, size = %d, %d\n", virt_addr, size, __LINE__); ++ phys_addr = virt_to_phys((unsigned long *)virt_addr); ++ physical_address = (unsigned int)phys_addr; ++ ++ pageFrameNo = __phys_to_pfn(phys_addr); ++ break; ++ ++ case MEM_ALLOC_SHARE : ++ case MEM_ALLOC_CACHEABLE_SHARE : ++ DEBUG("MMAP_KMALLOC_SHARE : phys addr = 0x%08x, %d\n", physical_address, __LINE__); ++ ++ // page frame number of the address for the physical_address to be shared. ++ pageFrameNo = __phys_to_pfn(physical_address); ++ DEBUG("MMAP_KMALLOC_SHARE : vma->end = 0x%08x, vma->start = 0x%08x, size = %d, %d\n", vma->vm_end, vma->vm_start, size, __LINE__); ++ break; ++ ++ default : ++ break; ++ } ++ ++ if( (flag == MEM_ALLOC) || (flag == MEM_ALLOC_SHARE) ) ++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ ++ vma->vm_flags |= VM_RESERVED; ++ ++ if (remap_pfn_range(vma, vma->vm_start, pageFrameNo, size, vma->vm_page_prot)) { ++ printk("s3c_mem_mmap() : remap_pfn_range() failed !\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++EXPORT_SYMBOL(s3c_mem_ioctl); ++EXPORT_SYMBOL(s3c_mem_mmap); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/char/s3c_mem.h linux-2.6.28.6/drivers/char/s3c_mem.h +--- linux-2.6.28/drivers/char/s3c_mem.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/char/s3c_mem.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,52 @@ ++#define DEBUG_S3C_MEM ++#undef DEBUG_S3C_MEM ++ ++#ifdef DEBUG_S3C_MEM ++#define DEBUG(fmt,args...) printk(fmt, ##args) ++#else ++#define DEBUG(fmt,args...) do {} while(0) ++#endif ++ ++#define MEM_IOCTL_MAGIC 'M' ++ ++#define S3C_MEM_ALLOC _IOWR(MEM_IOCTL_MAGIC, 310, struct s3c_mem_alloc) ++#define S3C_MEM_FREE _IOWR(MEM_IOCTL_MAGIC, 311, struct s3c_mem_alloc) ++ ++#define S3C_MEM_SHARE_ALLOC _IOWR(MEM_IOCTL_MAGIC, 314, struct s3c_mem_alloc) ++#define S3C_MEM_SHARE_FREE _IOWR(MEM_IOCTL_MAGIC, 315, struct s3c_mem_alloc) ++ ++#define S3C_MEM_CACHEABLE_ALLOC _IOWR(MEM_IOCTL_MAGIC, 316, struct s3c_mem_alloc) ++#define S3C_MEM_CACHEABLE_SHARE_ALLOC _IOWR(MEM_IOCTL_MAGIC, 317, struct s3c_mem_alloc) ++ ++#define S3C_MEM_DMA_COPY _IOWR(MEM_IOCTL_MAGIC, 318, struct s3c_mem_dma_param) ++#define S3C_MEM_DMA_SET _IOWR(MEM_IOCTL_MAGIC, 319, struct s3c_mem_dma_param) ++ ++#define MEM_ALLOC 1 ++#define MEM_ALLOC_SHARE 2 ++#define MEM_ALLOC_CACHEABLE 3 ++#define MEM_ALLOC_CACHEABLE_SHARE 4 ++ ++#define S3C_MEM_MINOR 13 ++ ++static DEFINE_MUTEX(mem_alloc_lock); ++static DEFINE_MUTEX(mem_free_lock); ++ ++static DEFINE_MUTEX(mem_share_alloc_lock); ++static DEFINE_MUTEX(mem_share_free_lock); ++ ++static DEFINE_MUTEX(mem_cacheable_alloc_lock); ++static DEFINE_MUTEX(mem_cacheable_share_alloc_lock); ++ ++struct s3c_mem_alloc { ++ int size; ++ unsigned int vir_addr; ++ unsigned int phy_addr; ++}; ++ ++struct s3c_mem_dma_param { ++ int size; ++ unsigned int src_addr; ++ unsigned int dst_addr; ++ int cfg; ++}; ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/i2c/busses/Kconfig linux-2.6.28.6/drivers/i2c/busses/Kconfig +--- linux-2.6.28/drivers/i2c/busses/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/i2c/busses/Kconfig 2009-04-30 09:36:38.000000000 +0200 +@@ -455,11 +455,12 @@ + I2C bus. + + config I2C_S3C2410 +- tristate "S3C2410 I2C Driver" +- depends on ARCH_S3C2410 ++ tristate "Samsung SoC I2C Driver (S3C24XX, S3C64XX and S5PC1XX series)" ++ depends on ARCH_S3C2410 || ARCH_S3C64XX || ARCH_S5PC1XX || ARCH_S5P64XX + help + Say Y here to include support for I2C controller in the +- Samsung S3C2410 based System-on-Chip devices. ++ Samsung S3C based System-on-Chip devices such as the S3C2410, ++ S3C2440, S3C2442, S3C2443 and S3C6410. + + config I2C_SH7760 + tristate "Renesas SH7760 I2C Controller" +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/i2c/busses/i2c-s3c2410.c linux-2.6.28.6/drivers/i2c/busses/i2c-s3c2410.c +--- linux-2.6.28/drivers/i2c/busses/i2c-s3c2410.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/i2c/busses/i2c-s3c2410.c 2009-04-30 09:36:38.000000000 +0200 +@@ -34,14 +34,12 @@ + #include + #include + #include ++#include + +-#include + #include +-#include + +-#include +-#include +-#include ++#include ++#include + + /* i2c controller state */ + +@@ -64,6 +62,7 @@ + unsigned int msg_ptr; + + unsigned int tx_setup; ++ unsigned int irq; + + enum s3c24xx_i2c_state state; + unsigned long clkrate; +@@ -71,7 +70,6 @@ + void __iomem *regs; + struct clk *clk; + struct device *dev; +- struct resource *irq; + struct resource *ioarea; + struct i2c_adapter adap; + +@@ -80,16 +78,7 @@ + #endif + }; + +-/* default platform data to use if not supplied in the platform_device +-*/ +- +-static struct s3c2410_platform_i2c s3c24xx_i2c_default_platform = { +- .flags = 0, +- .slave_addr = 0x10, +- .bus_freq = 100*1000, +- .max_freq = 400*1000, +- .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON, +-}; ++/* default platform data removed, dev should always carry data. */ + + /* s3c24xx_i2c_is2440() + * +@@ -103,21 +92,6 @@ + return !strcmp(pdev->name, "s3c2440-i2c"); + } + +- +-/* s3c24xx_i2c_get_platformdata +- * +- * get the platform data associated with the given device, or return +- * the default if there is none +-*/ +- +-static inline struct s3c2410_platform_i2c *s3c24xx_i2c_get_platformdata(struct device *dev) +-{ +- if (dev->platform_data != NULL) +- return (struct s3c2410_platform_i2c *)dev->platform_data; +- +- return &s3c24xx_i2c_default_platform; +-} +- + /* s3c24xx_i2c_master_complete + * + * complete the message and wake up the caller, using the given return code, +@@ -130,7 +104,7 @@ + + i2c->msg_ptr = 0; + i2c->msg = NULL; +- i2c->msg_idx ++; ++ i2c->msg_idx++; + i2c->msg_num = 0; + if (ret) + i2c->msg_idx = ret; +@@ -199,7 +171,7 @@ + if (msg->flags & I2C_M_REV_DIR_ADDR) + addr ^= 1; + +- // todo - check for wether ack wanted or not ++ /* todo - check for wether ack wanted or not */ + s3c24xx_i2c_enable_ack(i2c); + + iiccon = readl(i2c->regs + S3C2410_IICCON); +@@ -227,7 +199,7 @@ + dev_dbg(i2c->dev, "STOP\n"); + + /* stop the transfer */ +- iicstat &= ~ S3C2410_IICSTAT_START; ++ iicstat &= ~S3C2410_IICSTAT_START; + writel(iicstat, i2c->regs + S3C2410_IICSTAT); + + i2c->state = STATE_STOP; +@@ -359,7 +331,7 @@ + dev_dbg(i2c->dev, "WRITE: Next Message\n"); + + i2c->msg_ptr = 0; +- i2c->msg_idx ++; ++ i2c->msg_idx++; + i2c->msg++; + + /* check to see if we need to do another message */ +@@ -375,7 +347,6 @@ + + goto retry_write; + } else { +- + /* send the new start */ + s3c24xx_i2c_message_start(i2c, i2c->msg); + i2c->state = STATE_START; +@@ -450,7 +421,7 @@ + status = readl(i2c->regs + S3C2410_IICSTAT); + + if (status & S3C2410_IICSTAT_ARBITR) { +- // deal with arbitration loss ++ /* deal with arbitration loss */ + dev_err(i2c->dev, "deal with arbitration loss\n"); + } + +@@ -492,9 +463,6 @@ + msleep(1); + } + +- dev_dbg(i2c->dev, "timeout: GPEDAT is %08x\n", +- __raw_readl(S3C2410_GPEDAT)); +- + return -ETIMEDOUT; + } + +@@ -503,7 +471,8 @@ + * this starts an i2c transfer + */ + +-static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, struct i2c_msg *msgs, int num) ++static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, ++ struct i2c_msg *msgs, int num) + { + unsigned long timeout; + int ret; +@@ -591,19 +560,6 @@ + .functionality = s3c24xx_i2c_func, + }; + +-static struct s3c24xx_i2c s3c24xx_i2c = { +- .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_i2c.lock), +- .wait = __WAIT_QUEUE_HEAD_INITIALIZER(s3c24xx_i2c.wait), +- .tx_setup = 50, +- .adap = { +- .name = "s3c2410-i2c", +- .owner = THIS_MODULE, +- .algo = &s3c24xx_i2c_algorithm, +- .retries = 2, +- .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, +- }, +-}; +- + /* s3c24xx_i2c_calcdivisor + * + * return the divisor settings for a given frequency +@@ -643,7 +599,7 @@ + { + int diff = freq - wanted; + +- return (diff >= -2 && diff <= 2); ++ return diff >= -2 && diff <= 2; + } + + /* s3c24xx_i2c_clockrate +@@ -655,7 +611,7 @@ + + static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got) + { +- struct s3c2410_platform_i2c *pdata; ++ struct s3c2410_platform_i2c *pdata = i2c->dev->platform_data; + unsigned long clkin = clk_get_rate(i2c->clk); + unsigned int divs, div1; + u32 iiccon; +@@ -663,8 +619,6 @@ + int start, end; + + i2c->clkrate = clkin; +- +- pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent); + clkin /= 1000; /* clkin now in KHz */ + + dev_dbg(i2c->dev, "pdata %p, freq %lu %lu..%lu\n", +@@ -785,12 +739,12 @@ + + /* get the plafrom data */ + +- pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent); ++ pdata = i2c->dev->platform_data; + + /* inititalise the gpio */ + +- s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA); +- s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL); ++ if (pdata->cfg_gpio) ++ pdata->cfg_gpio(to_platform_device(i2c->dev)); + + /* write slave address */ + +@@ -831,12 +785,32 @@ + + static int s3c24xx_i2c_probe(struct platform_device *pdev) + { +- struct s3c24xx_i2c *i2c = &s3c24xx_i2c; ++ struct s3c24xx_i2c *i2c; + struct s3c2410_platform_i2c *pdata; + struct resource *res; + int ret; + +- pdata = s3c24xx_i2c_get_platformdata(&pdev->dev); ++ pdata = pdev->dev.platform_data; ++ if (!pdata) { ++ dev_err(&pdev->dev, "no platform data\n"); ++ return -EINVAL; ++ } ++ ++ i2c = kzalloc(sizeof(struct s3c24xx_i2c), GFP_KERNEL); ++ if (!i2c) { ++ dev_err(&pdev->dev, "no memory for state\n"); ++ return -ENOMEM; ++ } ++ ++ strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); ++ i2c->adap.owner = THIS_MODULE; ++ i2c->adap.algo = &s3c24xx_i2c_algorithm; ++ i2c->adap.retries = 2; ++ i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; ++ i2c->tx_setup = 50; ++ ++ spin_lock_init(&i2c->lock); ++ init_waitqueue_head(&i2c->wait); + + /* find the clock and enable it */ + +@@ -878,7 +852,8 @@ + goto err_ioarea; + } + +- dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", i2c->regs, i2c->ioarea, res); ++ dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", ++ i2c->regs, i2c->ioarea, res); + + /* setup info block for the i2c core */ + +@@ -895,26 +870,20 @@ + * ensure no current IRQs pending + */ + +- res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); +- if (res == NULL) { ++ i2c->irq = ret = platform_get_irq(pdev, 0); ++ if (ret <= 0) { + dev_err(&pdev->dev, "cannot find IRQ\n"); +- ret = -ENOENT; + goto err_iomap; + } + +- ret = request_irq(res->start, s3c24xx_i2c_irq, IRQF_DISABLED, +- pdev->name, i2c); ++ ret = request_irq(i2c->irq, s3c24xx_i2c_irq, IRQF_DISABLED, ++ dev_name(&pdev->dev), i2c); + + if (ret != 0) { +- dev_err(&pdev->dev, "cannot claim IRQ\n"); ++ dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); + goto err_iomap; + } + +- i2c->irq = res; +- +- dev_dbg(&pdev->dev, "irq resource %p (%lu)\n", res, +- (unsigned long)res->start); +- + ret = s3c24xx_i2c_register_cpufreq(i2c); + if (ret < 0) { + dev_err(&pdev->dev, "failed to register cpufreq notifier\n"); +@@ -944,7 +913,7 @@ + s3c24xx_i2c_deregister_cpufreq(i2c); + + err_irq: +- free_irq(i2c->irq->start, i2c); ++ free_irq(i2c->irq, i2c); + + err_iomap: + iounmap(i2c->regs); +@@ -958,6 +927,7 @@ + clk_put(i2c->clk); + + err_noclk: ++ kfree(i2c); + return ret; + } + +@@ -973,7 +943,7 @@ + s3c24xx_i2c_deregister_cpufreq(i2c); + + i2c_del_adapter(&i2c->adap); +- free_irq(i2c->irq->start, i2c); ++ free_irq(i2c->irq, i2c); + + clk_disable(i2c->clk); + clk_put(i2c->clk); +@@ -982,6 +952,7 @@ + + release_resource(i2c->ioarea); + kfree(i2c->ioarea); ++ kfree(i2c); + + return 0; + } +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/input/keyboard/Kconfig linux-2.6.28.6/drivers/input/keyboard/Kconfig +--- linux-2.6.28/drivers/input/keyboard/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/input/keyboard/Kconfig 2009-04-30 09:36:38.000000000 +0200 +@@ -295,6 +295,16 @@ + To compile this driver as a module, choose M here: the + module will be called gpio-keys. + ++config KEYPAD_S3C ++ tristate "S3C keypad support" ++ depends on (CPU_S3C6400 || CPU_S3C6410 || CPU_S5PC100) ++ default n ++ help ++ Say Y here if you want to use the S3C SMDK keypad. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called s3c-keypad. ++ + config KEYBOARD_MAPLE + tristate "Maple bus keyboard" + depends on SH_DREAMCAST && MAPLE +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/input/keyboard/Makefile linux-2.6.28.6/drivers/input/keyboard/Makefile +--- linux-2.6.28/drivers/input/keyboard/Makefile 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/input/keyboard/Makefile 2009-04-30 09:36:38.000000000 +0200 +@@ -27,3 +27,4 @@ + obj-$(CONFIG_KEYBOARD_MAPLE) += maple_keyb.o + obj-$(CONFIG_KEYBOARD_BFIN) += bf54x-keys.o + obj-$(CONFIG_KEYBOARD_SH_KEYSC) += sh_keysc.o ++obj-$(CONFIG_KEYPAD_S3C) += s3c-keypad.o +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/input/keyboard/s3c-keypad.c linux-2.6.28.6/drivers/input/keyboard/s3c-keypad.c +--- linux-2.6.28/drivers/input/keyboard/s3c-keypad.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/input/keyboard/s3c-keypad.c 2009-10-24 17:20:48.000000000 +0200 +@@ -0,0 +1,409 @@ ++/* drivers/input/keyboard/s3c-keypad.c ++ * ++ * Driver core for Samsung SoC onboard UARTs. ++ * ++ * Kim Kyoungil, Copyright (c) 2006-2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "s3c-keypad.h" ++ ++#undef S3C_KEYPAD_DEBUG ++//#define S3C_KEYPAD_DEBUG ++ ++#ifdef S3C_KEYPAD_DEBUG ++#define DPRINTK(x...) printk("S3C-Keypad " x) ++#else ++#define DPRINTK(x...) /* !!!! */ ++#endif ++ ++#define DEVICE_NAME "s3c-keypad" ++ ++#define TRUE 1 ++#define FALSE 0 ++ ++static struct timer_list keypad_timer; ++static int is_timer_on = FALSE; ++static struct clk *keypad_clock; ++ ++static int keypad_scan(u32 *keymask_low, u32 *keymask_high) ++{ ++ int i,j = 0; ++ u32 cval,rval; ++ ++ for (i=0; idev; ++ ++ keypad_scan(&keymask_low, &keymask_high); ++ ++ DPRINTK("[KEY]keypad_timer_handler.kl=%x,kh=%x\n",keymask_low, keymask_high); ++ ++ if (keymask_low != prevmask_low) { ++ press_mask_low = ++ ((keymask_low ^ prevmask_low) & keymask_low); ++ release_mask_low = ++ ((keymask_low ^ prevmask_low) & prevmask_low); ++ ++ i = 0; ++ while (press_mask_low) { ++ if (press_mask_low & 1) { ++ input_report_key(dev,pdata->keycodes[i],1); ++ DPRINTK("low Pressed : %d\n",i); ++ } ++ press_mask_low >>= 1; ++ i++; ++ } ++ ++ i = 0; ++ while (release_mask_low) { ++ if (release_mask_low & 1) { ++ input_report_key(dev,pdata->keycodes[i],0); ++ DPRINTK("low Released : %d\n",i); ++ } ++ release_mask_low >>= 1; ++ i++; ++ } ++ prevmask_low = keymask_low; ++ } ++ ++ if (keymask_high != prevmask_high) { ++ press_mask_high = ++ ((keymask_high ^ prevmask_high) & keymask_high); ++ release_mask_high = ++ ((keymask_high ^ prevmask_high) & prevmask_high); ++ ++ i = 0; ++ while (press_mask_high) { ++ if (press_mask_high & 1) { ++ input_report_key(dev,pdata->keycodes[i+MAX_KEYMASK_NR],1); ++ DPRINTK("high Pressed : %d %d\n",pdata->keycodes[i+MAX_KEYMASK_NR],i); ++ } ++ press_mask_high >>= 1; ++ i++; ++ } ++ ++ i = 0; ++ while (release_mask_high) { ++ if (release_mask_high & 1) { ++ input_report_key(dev,pdata->keycodes[i+MAX_KEYMASK_NR],0); ++ DPRINTK("high Released : %d\n",pdata->keycodes[i+MAX_KEYMASK_NR]); ++ } ++ release_mask_high >>= 1; ++ i++; ++ } ++ prevmask_high = keymask_high; ++ } ++ ++ if (keymask_low | keymask_high) { ++ mod_timer(&keypad_timer,jiffies + HZ/10); ++ } else { ++ writel(KEYIFCON_INIT, key_base+S3C_KEYIFCON); ++ is_timer_on = FALSE; ++ } ++} ++ ++static irqreturn_t s3c_keypad_isr(int irq, void *dev_id) ++{ ++ //printk("[KEY]s3c_keypad_isr.\n"); ++ /* disable keypad interrupt and schedule for keypad timer handler */ ++ writel(readl(key_base+S3C_KEYIFCON) & ~(INT_F_EN|INT_R_EN), key_base+S3C_KEYIFCON); ++ ++ keypad_timer.expires = jiffies + (HZ/100); ++ if ( is_timer_on == FALSE) { ++ add_timer(&keypad_timer); ++ is_timer_on = TRUE; ++ } else { ++ mod_timer(&keypad_timer,keypad_timer.expires); ++ } ++ /*Clear the keypad interrupt status*/ ++ writel(KEYIFSTSCLR_CLEAR, key_base+S3C_KEYIFSTSCLR); ++ ++ return IRQ_HANDLED; ++} ++ ++ ++ ++static int __init s3c_keypad_probe(struct platform_device *pdev) ++{ ++ struct resource *res, *keypad_mem, *keypad_irq; ++ struct input_dev *input_dev; ++ struct s3c_keypad *s3c_keypad; ++ int ret, size; ++ int key, code; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (res == NULL) { ++ dev_err(&pdev->dev,"no memory resource specified\n"); ++ return -ENOENT; ++ } ++ ++ size = (res->end - res->start) + 1; ++ ++ keypad_mem = request_mem_region(res->start, size, pdev->name); ++ if (keypad_mem == NULL) { ++ dev_err(&pdev->dev, "failed to get memory region\n"); ++ ret = -ENOENT; ++ goto err_req; ++ } ++ ++ key_base = ioremap(res->start, size); ++ if (key_base == NULL) { ++ printk(KERN_ERR "Failed to remap register block\n"); ++ ret = -ENOMEM; ++ goto err_map; ++ } ++ ++ keypad_clock = clk_get(&pdev->dev, "keypad"); ++ if (IS_ERR(keypad_clock)) { ++ dev_err(&pdev->dev, "failed to find keypad clock source\n"); ++ ret = PTR_ERR(keypad_clock); ++ goto err_clk; ++ } ++ ++ clk_enable(keypad_clock); ++ ++ s3c_keypad = kzalloc(sizeof(struct s3c_keypad), GFP_KERNEL); ++ input_dev = input_allocate_device(); ++ ++ if (!s3c_keypad || !input_dev) { ++ ret = -ENOMEM; ++ goto err_alloc; ++ } ++ ++ platform_set_drvdata(pdev, s3c_keypad); ++ s3c_keypad->dev = input_dev; ++ ++ writel(KEYIFCON_INIT, key_base+S3C_KEYIFCON); ++ writel(KEYIFFC_DIV, key_base+S3C_KEYIFFC); ++ ++ /* Set GPIO Port for keypad mode and pull-up disable*/ ++ s3c_setup_keypad_cfg_gpio(KEYPAD_ROWS, KEYPAD_COLUMNS); ++ ++ writel(KEYIFCOL_CLEAR, key_base+S3C_KEYIFCOL); ++ ++ /* create and register the input driver */ ++ set_bit(EV_KEY, input_dev->evbit); ++ set_bit(EV_REP, input_dev->evbit); ++ s3c_keypad->nr_rows = KEYPAD_ROWS; ++ s3c_keypad->no_cols = KEYPAD_COLUMNS; ++ s3c_keypad->total_keys = MAX_KEYPAD_NR; ++ ++ for(key = 0; key < s3c_keypad->total_keys; key++){ ++ code = s3c_keypad->keycodes[key] = keypad_keycode[key]; ++ if(code<=0) ++ continue; ++ set_bit(code & KEY_MAX, input_dev->keybit); ++ } ++ ++ input_dev->name = DEVICE_NAME; ++ input_dev->phys = "s3c-keypad/input0"; ++ ++ input_dev->id.bustype = BUS_HOST; ++ input_dev->id.vendor = 0x0001; ++ input_dev->id.product = 0x0001; ++ input_dev->id.version = 0x0001; ++ ++ input_dev->keycode = keypad_keycode; ++ ++ /* Scan timer init */ ++ init_timer(&keypad_timer); ++ keypad_timer.function = keypad_timer_handler; ++ keypad_timer.data = (unsigned long)s3c_keypad; ++ ++ /* For IRQ_KEYPAD */ ++ keypad_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (keypad_irq == NULL) { ++ dev_err(&pdev->dev, "no irq resource specified\n"); ++ ret = -ENOENT; ++ goto err_irq; ++ } ++ ++ ret = request_irq(keypad_irq->start, s3c_keypad_isr, IRQF_SAMPLE_RANDOM, ++ DEVICE_NAME, (void *) pdev); ++ if (ret) { ++ printk("request_irq failed (IRQ_KEYPAD) !!!\n"); ++ ret = -EIO; ++ goto err_irq; ++ } ++ ++ ret = input_register_device(input_dev); ++ if (ret) { ++ printk("Unable to register s3c-keypad input device!!!\n"); ++ goto out; ++ } ++ ++/* keypad_timer.expires = jiffies + (HZ/10); ++ ++ if (is_timer_on == FALSE) { ++ add_timer(&keypad_timer); ++ is_timer_on = TRUE; ++ } else { ++ mod_timer(&keypad_timer,keypad_timer.expires); ++ } ++*/ ++ printk( DEVICE_NAME " Initialized\n"); ++ return 0; ++ ++out: ++ free_irq(keypad_irq->start, input_dev); ++ free_irq(keypad_irq->end, input_dev); ++ ++err_irq: ++ input_free_device(input_dev); ++ kfree(s3c_keypad); ++ ++err_alloc: ++ clk_disable(keypad_clock); ++ clk_put(keypad_clock); ++ ++err_clk: ++ iounmap(key_base); ++ ++err_map: ++ release_resource(keypad_mem); ++ kfree(keypad_mem); ++ ++err_req: ++ return ret; ++} ++ ++static int s3c_keypad_remove(struct platform_device *pdev) ++{ ++ struct input_dev *input_dev = platform_get_drvdata(pdev); ++ writel(KEYIFCON_CLEAR, key_base+S3C_KEYIFCON); ++ ++ if(keypad_clock) { ++ clk_disable(keypad_clock); ++ clk_put(keypad_clock); ++ keypad_clock = NULL; ++ } ++ ++ input_unregister_device(input_dev); ++ iounmap(key_base); ++ kfree(pdev->dev.platform_data); ++ free_irq(IRQ_KEYPAD, (void *) pdev); ++ ++ del_timer(&keypad_timer); ++ printk(DEVICE_NAME " Removed.\n"); ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static unsigned int keyifcon, keyiffc; ++ ++static int s3c_keypad_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ keyifcon = readl(key_base+S3C_KEYIFCON); ++ keyiffc = readl(key_base+S3C_KEYIFFC); ++ ++ disable_irq(IRQ_KEYPAD); ++ ++ clk_disable(keypad_clock); ++ ++ return 0; ++} ++ ++static int s3c_keypad_resume(struct platform_device *dev) ++{ ++ clk_enable(keypad_clock); ++ ++ writel(keyifcon, key_base+S3C_KEYIFCON); ++ writel(keyiffc, key_base+S3C_KEYIFFC); ++ ++ enable_irq(IRQ_KEYPAD); ++ ++ return 0; ++} ++#else ++#define s3c_keypad_suspend NULL ++#define s3c_keypad_resume NULL ++#endif /* CONFIG_PM */ ++ ++static struct platform_driver s3c_keypad_driver = { ++ .probe = s3c_keypad_probe, ++ .remove = s3c_keypad_remove, ++ .suspend = s3c_keypad_suspend, ++ .resume = s3c_keypad_resume, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "s3c-keypad", ++ }, ++}; ++ ++static int __init s3c_keypad_init(void) ++{ ++ int ret; ++ ++ ret = platform_driver_register(&s3c_keypad_driver); ++ ++ if(!ret) ++ printk(KERN_INFO "S3C Keypad Driver\n"); ++ ++ return ret; ++} ++ ++static void __exit s3c_keypad_exit(void) ++{ ++ platform_driver_unregister(&s3c_keypad_driver); ++} ++ ++module_init(s3c_keypad_init); ++module_exit(s3c_keypad_exit); ++ ++MODULE_AUTHOR("Samsung"); ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("KeyPad interface for Samsung S3C"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/input/keyboard/s3c-keypad.h linux-2.6.28.6/drivers/input/keyboard/s3c-keypad.h +--- linux-2.6.28/drivers/input/keyboard/s3c-keypad.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/input/keyboard/s3c-keypad.h 2010-04-21 06:37:01.000000000 +0200 +@@ -0,0 +1,66 @@ ++/* linux/drivers/input/keyboard/s3c-keypad.h ++ * ++ * Driver header for Samsung SoC keypad. ++ * ++ * Kim Kyoungil, Copyright (c) 2006-2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++ ++#ifndef _S3C_KEYPAD_H_ ++#define _S3C_KEYPAD_H_ ++ ++static void __iomem *key_base; ++ ++#define KEYPAD_COLUMNS 8 ++#define KEYPAD_ROWS 8 ++#define MAX_KEYPAD_NR 64 /* 8*8 */ ++#define MAX_KEYMASK_NR 32 ++ ++/*int keypad_keycode[] = { ++ 1, 2, KEY_1, KEY_Q, KEY_A, 6, 7, KEY_LEFT, ++ 9, 10, KEY_2, KEY_W, KEY_S, KEY_Z, KEY_RIGHT, 16, ++ 17, 18, KEY_3, KEY_E, KEY_D, KEY_X, 23, KEY_UP, ++ 25, 26, KEY_4, KEY_R, KEY_F, KEY_C, 31, 32, ++ 33, KEY_O, KEY_5, KEY_T, KEY_G, KEY_V, KEY_DOWN, KEY_BACKSPACE, ++ KEY_P, KEY_0, KEY_6, KEY_Y, KEY_H, KEY_SPACE, 47, 48, ++ KEY_M, KEY_L, KEY_7, KEY_U, KEY_J, KEY_N, 55, KEY_ENTER, ++ KEY_LEFTSHIFT, KEY_9, KEY_8, KEY_I, KEY_K, KEY_B, 63, KEY_COMMA ++ }; ++*/ ++int keypad_keycode[] = { ++ 1, 2, KEY_1, KEY_Q, KEY_A, 6, 7, KEY_LEFT, ++ 9, 10, KEY_2, KEY_W, KEY_S, KEY_Z, KEY_RIGHT, 16, ++ 17, 18, KEY_3, KEY_E, KEY_D, KEY_X, 23, KEY_UP, ++ KEY_F1, KEY_UP, KEY_4, KEY_R, KEY_F, KEY_C, 31, 32, ++ KEY_F2, KEY_LEFT,KEY_5, KEY_T, KEY_G, KEY_V, KEY_DOWN, KEY_BACKSPACE, ++ KEY_F3,KEY_ENTER,KEY_6, KEY_Y, KEY_H, KEY_SPACE, 47, 48, ++ KEY_BACKSPACE,KEY_DOWN,KEY_7, KEY_U, KEY_J, KEY_N, 55, KEY_ENTER, ++ KEY_LEFT,KEY_RIGHT,KEY_9, KEY_8, KEY_I, KEY_K, KEY_B, 63, KEY_COMMA ++ }; ++ ++#ifdef CONFIG_CPU_S3C6410 ++#define KEYPAD_DELAY (50) ++#elif CONFIG_CPU_S5PC100 ++#define KEYPAD_DELAY (600) ++#endif ++ ++#define KEYIFCOL_CLEAR (readl(key_base+S3C_KEYIFCOL) & ~0xffff) ++#define KEYIFCON_CLEAR (readl(key_base+S3C_KEYIFCON) & ~0x1f) ++#define KEYIFFC_DIV (readl(key_base+S3C_KEYIFFC) | 0x1) ++ ++struct s3c_keypad { ++ struct input_dev *dev; ++ int nr_rows; ++ int no_cols; ++ int total_keys; ++ int keycodes[MAX_KEYPAD_NR]; ++}; ++ ++extern void s3c_setup_keypad_cfg_gpio(int rows, int columns); ++ ++#endif /* _S3C_KEYIF_H_ */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/input/touchscreen/Kconfig linux-2.6.28.6/drivers/input/touchscreen/Kconfig +--- linux-2.6.28/drivers/input/touchscreen/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/input/touchscreen/Kconfig 2009-04-30 09:36:38.000000000 +0200 +@@ -58,6 +58,30 @@ + NOTE: this driver is deprecated, try enable SPI and generic + ADS7846-based touchscreen driver. + ++config TOUCHSCREEN_S3C ++ tristate "S3C touchscreen driver" ++ depends on ARCH_S3C2410 || ARCH_S3C64XX || ARCH_S5P64XX || ARCH_S5PC1XX ++ default y ++ help ++ Say Y here to enable the driver for the touchscreen on the ++ S3C SMDK board. ++ ++ If unsure, say N. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called s3c_ts. ++ ++config TOUCHSCREEN_NEW ++ bool "new flip touch" ++ depends on TOUCHSCREEN_S3C ++ default y ++ help ++ Say Y here to enable the driver for the new version touchscreen on the ++ S3C SMDK board. ++ ++ Say N here to enable the driver for the old version touchscreen on the ++ S3C SMDK board. ++ + config TOUCHSCREEN_FUJITSU + tristate "Fujitsu serial touchscreen" + select SERIO +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/input/touchscreen/Makefile linux-2.6.28.6/drivers/input/touchscreen/Makefile +--- linux-2.6.28/drivers/input/touchscreen/Makefile 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/input/touchscreen/Makefile 2009-04-30 09:36:38.000000000 +0200 +@@ -31,3 +31,4 @@ + wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9712) += wm9712.o + wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9713) += wm9713.o + obj-$(CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE) += mainstone-wm97xx.o ++obj-$(CONFIG_TOUCHSCREEN_S3C) += s3c-ts.o +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/input/touchscreen/s3c-ts.c linux-2.6.28.6/drivers/input/touchscreen/s3c-ts.c +--- linux-2.6.28/drivers/input/touchscreen/s3c-ts.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/input/touchscreen/s3c-ts.c 2010-04-09 08:05:25.000000000 +0200 +@@ -0,0 +1,519 @@ ++/* linux/drivers/input/touchscreen/s3c-ts.c ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * Copyright (c) 2004 Arnaud Patard ++ * iPAQ H1940 touchscreen support ++ * ++ * ChangeLog ++ * ++ * 2004-09-05: Herbert Potzl ++ * - added clock (de-)allocation code ++ * ++ * 2005-03-06: Arnaud Patard ++ * - h1940_ -> s3c24xx (this driver is now also used on the n30 ++ * machines :P) ++ * - Debug messages are now enabled with the config option ++ * TOUCHSCREEN_S3C_DEBUG ++ * - Changed the way the value are read ++ * - Input subsystem should now work ++ * - Use ioremap and readl/writel ++ * ++ * 2005-03-23: Arnaud Patard ++ * - Make use of some undocumented features of the touchscreen ++ * controller ++ * ++ * 2006-09-05: Ryu Euiyoul ++ * - added power management suspend and resume code ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#define CONFIG_TOUCHSCREEN_S3C_DEBUG ++#undef CONFIG_TOUCHSCREEN_S3C_DEBUG ++ ++/* For ts->dev.id.version */ ++#define S3C_TSVERSION 0x0101 ++ ++#define WAIT4INT(x) (((x)<<8) | \ ++ S3C_ADCTSC_YM_SEN | S3C_ADCTSC_YP_SEN | S3C_ADCTSC_XP_SEN | \ ++ S3C_ADCTSC_XY_PST(3)) ++ ++#define AUTOPST (S3C_ADCTSC_YM_SEN | S3C_ADCTSC_YP_SEN | S3C_ADCTSC_XP_SEN | \ ++ S3C_ADCTSC_AUTO_PST | S3C_ADCTSC_XY_PST(0)) ++ ++ ++#define DEBUG_LVL KERN_DEBUG ++ ++ ++/* Touchscreen default configuration */ ++struct s3c_ts_mach_info s3c_ts_default_cfg __initdata = { ++ .delay = 10000, ++ .presc = 49, ++ .oversampling_shift = 2, ++ .resol_bit = 10 ++}; ++ ++/* ++ * Definitions & global arrays. ++ */ ++static char *s3c_ts_name = "S3C TouchScreen"; ++static void __iomem *ts_base; ++static struct resource *ts_mem; ++static struct resource *ts_irq; ++static struct clk *ts_clock; ++static struct s3c_ts_info *ts; ++ ++static int downflag=0; ++ ++static void touch_timer_fire(unsigned long data) ++{ ++ unsigned long data0; ++ unsigned long data1; ++ int updown; ++ ++ data0 = readl(ts_base+S3C_ADCDAT0); ++ data1 = readl(ts_base+S3C_ADCDAT1); ++ ++ updown = (!(data0 & S3C_ADCDAT0_UPDOWN)) && (!(data1 & S3C_ADCDAT1_UPDOWN)); ++ ++ if (0) { ++ unsigned tmp; ++ tmp = readl(S3C64XX_GPBCON); ++ printk("GPBCON: 0x%X\n", tmp); ++ } ++ ++ if (updown) { ++ if (ts->count) { ++ ++#ifdef CONFIG_TOUCHSCREEN_S3C_DEBUG ++ { ++ struct timeval tv; ++ do_gettimeofday(&tv); ++ printk(KERN_INFO "T: %06d, X: %03ld, Y: %03ld\n", (int)tv.tv_usec, ts->xp, ts->yp); ++ } ++#endif ++ if(downflag==0) ++ { ++ input_report_abs(ts->dev, ABS_X, ts->xp); ++ input_report_abs(ts->dev, ABS_Y, ts->yp); ++ ++ input_report_key(ts->dev, BTN_TOUCH, 1); ++ input_report_abs(ts->dev, ABS_PRESSURE, 1); ++ input_sync(ts->dev); ++ } ++ else ++ { ++ downflag=0; ++ } ++ } ++ ++ ts->xp = 0; ++ ts->yp = 0; ++ ts->count = 0; ++ ++ writel(S3C_ADCTSC_PULL_UP_DISABLE | AUTOPST, ts_base+S3C_ADCTSC); ++ writel(readl(ts_base+S3C_ADCCON) | S3C_ADCCON_ENABLE_START, ts_base+S3C_ADCCON); ++ } ++ else { ++ ++ ts->xp = 0; ++ ts->yp = 0; ++ ts->count = 0; ++ ++ input_report_key(ts->dev, BTN_TOUCH, 0); ++ input_report_abs(ts->dev, ABS_PRESSURE, 0); ++ input_sync(ts->dev); ++ ++ writel(WAIT4INT(0), ts_base+S3C_ADCTSC); ++ } ++} ++ ++static struct timer_list touch_timer = ++ TIMER_INITIALIZER(touch_timer_fire, 0, 0); ++ ++static irqreturn_t stylus_updown(int irqno, void *param) ++{ ++ unsigned long data0; ++ unsigned long data1; ++ int updown; ++ ++ data0 = readl(ts_base+S3C_ADCDAT0); ++ data1 = readl(ts_base+S3C_ADCDAT1); ++ ++ updown = (!(data0 & S3C_ADCDAT0_UPDOWN)) && (!(data1 & S3C_ADCDAT1_UPDOWN)); ++ ++#ifdef CONFIG_TOUCHSCREEN_S3C_DEBUG ++ printk(KERN_INFO " %c\n", updown ? 'D' : 'U'); ++#endif ++ ++ /* TODO we should never get an interrupt with updown set while ++ * the timer is running, but maybe we ought to verify that the ++ * timer isn't running anyways. */ ++ ++ if (updown) ++ { ++ downflag=1; ++ touch_timer_fire(0); ++ } ++ ++ if(ts->s3c_adc_con==ADC_TYPE_2) { ++ __raw_writel(0x0, ts_base+S3C_ADCCLRWK); ++ __raw_writel(0x0, ts_base+S3C_ADCCLRINT); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t stylus_action(int irqno, void *param) ++{ ++ unsigned long data0; ++ unsigned long data1; ++ ++ ++ data0 = readl(ts_base+S3C_ADCDAT0); ++ data1 = readl(ts_base+S3C_ADCDAT1); ++ ++ if(ts->resol_bit==12) { ++#if defined(CONFIG_TOUCHSCREEN_NEW) ++ ts->yp += S3C_ADCDAT0_XPDATA_MASK_12BIT - (data0 & S3C_ADCDAT0_XPDATA_MASK_12BIT); ++ ts->xp += S3C_ADCDAT1_YPDATA_MASK_12BIT - (data1 & S3C_ADCDAT1_YPDATA_MASK_12BIT); ++#else ++ ts->xp += data0 & S3C_ADCDAT0_XPDATA_MASK_12BIT; ++ ts->yp += data1 & S3C_ADCDAT1_YPDATA_MASK_12BIT; ++#endif ++ } ++ else { ++#if defined(CONFIG_TOUCHSCREEN_NEW) ++ ts->yp += S3C_ADCDAT0_XPDATA_MASK - (data0 & S3C_ADCDAT0_XPDATA_MASK); ++ ts->xp += S3C_ADCDAT1_YPDATA_MASK - (data1 & S3C_ADCDAT1_YPDATA_MASK); ++#else ++ ts->xp += data0 & S3C_ADCDAT0_XPDATA_MASK; ++ ts->yp += data1 & S3C_ADCDAT1_YPDATA_MASK; ++#endif ++ } ++ ++ ts->count++; ++ ++ if (ts->count < (1<shift)) { ++ writel(S3C_ADCTSC_PULL_UP_DISABLE | AUTOPST, ts_base+S3C_ADCTSC); ++ writel(readl(ts_base+S3C_ADCCON) | S3C_ADCCON_ENABLE_START, ts_base+S3C_ADCCON); ++ } else { ++ mod_timer(&touch_timer, jiffies+1); ++ writel(WAIT4INT(1), ts_base+S3C_ADCTSC); ++ } ++ ++ if(ts->s3c_adc_con==ADC_TYPE_2) { ++ __raw_writel(0x0, ts_base+S3C_ADCCLRWK); ++ __raw_writel(0x0, ts_base+S3C_ADCCLRINT); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++ ++static struct s3c_ts_mach_info *s3c_ts_get_platdata (struct device *dev) ++{ ++ if (dev->platform_data != NULL) ++ return (struct s3c_ts_mach_info *)dev->platform_data; ++ ++ return &s3c_ts_default_cfg; ++} ++ ++/* ++ * The functions for inserting/removing us as a module. ++ */ ++static int __init s3c_ts_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ struct device *dev; ++ struct input_dev *input_dev; ++ struct s3c_ts_mach_info * s3c_ts_cfg; ++ int ret, size; ++ ++ dev = &pdev->dev; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (res == NULL) { ++ dev_err(dev,"no memory resource specified\n"); ++ return -ENOENT; ++ } ++ ++ size = (res->end - res->start) + 1; ++ ts_mem = request_mem_region(res->start, size, pdev->name); ++ if (ts_mem == NULL) { ++ dev_err(dev, "failed to get memory region\n"); ++ ret = -ENOENT; ++ goto err_req; ++ } ++ ++ ts_base = ioremap(res->start, size); ++ if (ts_base == NULL) { ++ dev_err(dev, "failed to ioremap() region\n"); ++ ret = -EINVAL; ++ goto err_map; ++ } ++ ++ ts_clock = clk_get(&pdev->dev, "adc"); ++ if (IS_ERR(ts_clock)) { ++ dev_err(dev, "failed to find watchdog clock source\n"); ++ ret = PTR_ERR(ts_clock); ++ goto err_clk; ++ } ++ ++ clk_enable(ts_clock); ++ ++ s3c_ts_cfg = s3c_ts_get_platdata(&pdev->dev); ++ ++ if ((s3c_ts_cfg->presc&0xff) > 0) ++ writel(S3C_ADCCON_PRSCEN | S3C_ADCCON_PRSCVL(s3c_ts_cfg->presc&0xFF),\ ++ ts_base+S3C_ADCCON); ++ else ++ writel(0, ts_base+S3C_ADCCON); ++ ++ ++ /* Initialise registers */ ++ if ((s3c_ts_cfg->delay&0xffff) > 0) ++ writel(s3c_ts_cfg->delay & 0xffff, ts_base+S3C_ADCDLY); ++ ++ if (s3c_ts_cfg->resol_bit==12) { ++ switch(s3c_ts_cfg->s3c_adc_con) { ++ case ADC_TYPE_2: ++ writel(readl(ts_base+S3C_ADCCON)|S3C_ADCCON_RESSEL_12BIT, ts_base+S3C_ADCCON); ++ break; ++ ++ case ADC_TYPE_1: ++ writel(readl(ts_base+S3C_ADCCON)|S3C_ADCCON_RESSEL_12BIT_1, ts_base+S3C_ADCCON); ++ break; ++ ++ default: ++ dev_err(dev, "Touchscreen over this type of AP isn't supported !\n"); ++ break; ++ } ++ } ++ ++ writel(WAIT4INT(0), ts_base+S3C_ADCTSC); ++ ++ ts = kzalloc(sizeof(struct s3c_ts_info), GFP_KERNEL); ++ ++ input_dev = input_allocate_device(); ++ ++ if (!input_dev) { ++ ret = -ENOMEM; ++ goto err_alloc; ++ } ++ ++ ts->dev = input_dev; ++ ++ ts->dev->evbit[0] = ts->dev->evbit[0] = BIT_MASK(EV_SYN) | BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS); ++ ts->dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH); ++ ++ if (s3c_ts_cfg->resol_bit==12) { ++ input_set_abs_params(ts->dev, ABS_X, 0, 0xFFF, 0, 0); ++ input_set_abs_params(ts->dev, ABS_Y, 0, 0xFFF, 0, 0); ++ } ++ else { ++ input_set_abs_params(ts->dev, ABS_X, 0, 0x3FF, 0, 0); ++ input_set_abs_params(ts->dev, ABS_Y, 0, 0x3FF, 0, 0); ++ } ++ ++ input_set_abs_params(ts->dev, ABS_PRESSURE, 0, 1, 0, 0); ++ ++ sprintf(ts->phys, "input(ts)"); ++ ++ ts->dev->name = s3c_ts_name; ++ ts->dev->phys = ts->phys; ++ ts->dev->id.bustype = BUS_RS232; ++ ts->dev->id.vendor = 0xDEAD; ++ ts->dev->id.product = 0xBEEF; ++ ts->dev->id.version = S3C_TSVERSION; ++ ++ ts->shift = s3c_ts_cfg->oversampling_shift; ++ ts->resol_bit = s3c_ts_cfg->resol_bit; ++ ts->s3c_adc_con = s3c_ts_cfg->s3c_adc_con; ++ ++ /* For IRQ_PENDUP */ ++ ts_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (ts_irq == NULL) { ++ dev_err(dev, "no irq resource specified\n"); ++ ret = -ENOENT; ++ goto err_irq; ++ } ++ ++ ret = request_irq(ts_irq->start, stylus_updown, IRQF_SAMPLE_RANDOM, "s3c_updown", ts); ++ if (ret != 0) { ++ dev_err(dev,"s3c_ts.c: Could not allocate ts IRQ_PENDN !\n"); ++ ret = -EIO; ++ goto err_irq; ++ } ++ ++ /* For IRQ_ADC */ ++ ts_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 1); ++ if (ts_irq == NULL) { ++ dev_err(dev, "no irq resource specified\n"); ++ ret = -ENOENT; ++ goto err_irq; ++ } ++ ++ ret = request_irq(ts_irq->start, stylus_action, IRQF_SAMPLE_RANDOM, "s3c_action", ts); ++ if (ret != 0) { ++ dev_err(dev, "s3c_ts.c: Could not allocate ts IRQ_ADC !\n"); ++ ret = -EIO; ++ goto err_irq; ++ } ++ ++ printk(KERN_INFO "%s got loaded successfully : %d bits\n", s3c_ts_name, s3c_ts_cfg->resol_bit); ++ ++ /* All went ok, so register to the input system */ ++ ret = input_register_device(ts->dev); ++ ++ if(ret) { ++ dev_err(dev, "s3c_ts.c: Could not register input device(touchscreen)!\n"); ++ ret = -EIO; ++ goto fail; ++ } ++ ++ return 0; ++ ++fail: ++ free_irq(ts_irq->start, ts->dev); ++ free_irq(ts_irq->end, ts->dev); ++ ++err_irq: ++ input_free_device(input_dev); ++ kfree(ts); ++ ++err_alloc: ++ clk_disable(ts_clock); ++ clk_put(ts_clock); ++ ++err_clk: ++ iounmap(ts_base); ++ ++err_map: ++ release_resource(ts_mem); ++ kfree(ts_mem); ++ ++err_req: ++ return ret; ++} ++ ++static int s3c_ts_remove(struct platform_device *dev) ++{ ++ printk(KERN_INFO "s3c_ts_remove() of TS called !\n"); ++ ++ disable_irq(IRQ_ADC); ++ disable_irq(IRQ_PENDN); ++ ++ free_irq(IRQ_PENDN, ts->dev); ++ free_irq(IRQ_ADC, ts->dev); ++ ++ if (ts_clock) { ++ clk_disable(ts_clock); ++ clk_put(ts_clock); ++ ts_clock = NULL; ++ } ++ ++ input_unregister_device(ts->dev); ++ iounmap(ts_base); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static unsigned int adccon, adctsc, adcdly; ++ ++static int s3c_ts_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ adccon = readl(ts_base+S3C_ADCCON); ++ adctsc = readl(ts_base+S3C_ADCTSC); ++ adcdly = readl(ts_base+S3C_ADCDLY); ++ ++ disable_irq(IRQ_ADC); ++ disable_irq(IRQ_PENDN); ++ ++ clk_disable(ts_clock); ++ ++ return 0; ++} ++ ++static int s3c_ts_resume(struct platform_device *pdev) ++{ ++ clk_enable(ts_clock); ++ ++ writel(adccon, ts_base+S3C_ADCCON); ++ writel(adctsc, ts_base+S3C_ADCTSC); ++ writel(adcdly, ts_base+S3C_ADCDLY); ++ writel(WAIT4INT(0), ts_base+S3C_ADCTSC); ++ ++ enable_irq(IRQ_ADC); ++ enable_irq(IRQ_PENDN); ++ return 0; ++} ++#else ++#define s3c_ts_suspend NULL ++#define s3c_ts_resume NULL ++#endif ++ ++static struct platform_driver s3c_ts_driver = { ++ .probe = s3c_ts_probe, ++ .remove = s3c_ts_remove, ++ .suspend = s3c_ts_suspend, ++ .resume = s3c_ts_resume, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "s3c-ts", ++ }, ++}; ++ ++static char banner[] __initdata = KERN_INFO "S3C Touchscreen driver, (c) 2008 Samsung Electronics\n"; ++ ++static int __init s3c_ts_init(void) ++{ ++ printk(banner); ++ return platform_driver_register(&s3c_ts_driver); ++} ++ ++static void __exit s3c_ts_exit(void) ++{ ++ platform_driver_unregister(&s3c_ts_driver); ++} ++ ++module_init(s3c_ts_init); ++module_exit(s3c_ts_exit); ++ ++MODULE_AUTHOR("Samsung AP"); ++MODULE_DESCRIPTION("S3C touchscreen driver"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/Kconfig linux-2.6.28.6/drivers/media/video/Kconfig +--- linux-2.6.28/drivers/media/video/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/Kconfig 2009-04-30 09:36:38.000000000 +0200 +@@ -893,4 +893,6 @@ + + endif # V4L_USB_DRIVERS + ++source "drivers/media/video/samsung/Kconfig" ++ + endif # VIDEO_CAPTURE_DRIVERS +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/Makefile linux-2.6.28.6/drivers/media/video/Makefile +--- linux-2.6.28/drivers/media/video/Makefile 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/Makefile 2009-04-30 09:36:38.000000000 +0200 +@@ -136,6 +136,7 @@ + obj-$(CONFIG_SOC_CAMERA_PLATFORM) += soc_camera_platform.o + + obj-$(CONFIG_VIDEO_AU0828) += au0828/ ++obj-$(CONFIG_VIDEO_SAMSUNG) += samsung/ + + obj-$(CONFIG_USB_VIDEO_CLASS) += uvc/ + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/Kconfig linux-2.6.28.6/drivers/media/video/samsung/Kconfig +--- linux-2.6.28/drivers/media/video/samsung/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/Kconfig 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,76 @@ ++config VIDEO_SAMSUNG ++ bool "Samsung Multimedia Devices" ++ depends on VIDEO_CAPTURE_DRIVERS && VIDEO_V4L2 ++ select VIDEO_FIXED_MINOR_RANGES ++ default n ++ ---help--- ++ This is a representative video4linux configuration for Samsung multimedia devices. ++ ++source "drivers/media/video/samsung/fimc/Kconfig" ++source "drivers/media/video/samsung/post/Kconfig" ++ ++if CPU_S3C6410 ++source "drivers/media/video/samsung/mfc10/Kconfig" ++source "drivers/media/video/samsung/jpeg/Kconfig" ++endif ++ ++if CPU_S5PC100 ++source "drivers/media/video/samsung/mfc40/Kconfig" ++source "drivers/media/video/samsung/jpeg_v2/Kconfig" ++endif ++ ++source "drivers/media/video/samsung/tv/Kconfig" ++source "drivers/media/video/samsung/rotator/Kconfig" ++source "drivers/media/video/samsung/g2d/Kconfig" ++source "drivers/media/video/samsung/g3d/Kconfig" ++source "drivers/media/video/samsung/cmm/Kconfig" ++ ++if VIDEO_SAMSUNG ++ ++comment "Reserved memory configurations" ++ ++config VIDEO_SAMSUNG_MEMSIZE_FIMC ++ int "Memory size in kbytes for FIMC" ++ depends on VIDEO_FIMC ++ default "10240" ++ ++config VIDEO_SAMSUNG_MEMSIZE_POST ++ int "Memory size in kbytes for Post Processor" ++ depends on VIDEO_POST ++ default "8192" ++ ++config VIDEO_SAMSUNG_MEMSIZE_TV ++ int "Memory size in kbytes for TV" ++ depends on VIDEO_TV ++ default "8192" ++ ++if CPU_S3C6410 ++config VIDEO_SAMSUNG_MEMSIZE_MFC ++ int "Memory size in kbytes for MFC" ++ depends on VIDEO_MFC10 ++ default "6144" ++ ++config VIDEO_SAMSUNG_MEMSIZE_JPEG ++ int "Memory size in kbytes for JPEG" ++ depends on VIDEO_JPEG ++ default "4096" ++endif ++ ++if ARCH_S5PC1XX ++config VIDEO_SAMSUNG_MEMSIZE_MFC ++ int "Memory size in kbytes for MFC" ++ depends on VIDEO_MFC40 ++ default "32768" ++ ++config VIDEO_SAMSUNG_MEMSIZE_JPEG ++ int "Memory size in kbytes for JPEG" ++ depends on VIDEO_JPEG_V2 ++ default "32768" ++endif ++ ++config VIDEO_SAMSUNG_MEMSIZE_CMM ++ int "Memory size in kbytes for CMM" ++ depends on VIDEO_CMM && CPU_S3C6410 ++ default "0" ++endif ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/Makefile linux-2.6.28.6/drivers/media/video/samsung/Makefile +--- linux-2.6.28/drivers/media/video/samsung/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/Makefile 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,14 @@ ++obj-$(CONFIG_VIDEO_FIMC) += fimc/ ++obj-$(CONFIG_VIDEO_MFC10) += mfc10/ ++obj-$(CONFIG_VIDEO_MFC40) += mfc40/ ++obj-$(CONFIG_VIDEO_POST) += post/ ++obj-$(CONFIG_VIDEO_POST) += tv/ ++obj-$(CONFIG_VIDEO_ROTATOR) += rotator/ ++obj-$(CONFIG_VIDEO_JPEG) += jpeg/ ++obj-$(CONFIG_VIDEO_JPEG_V2) += jpeg_v2/ ++obj-$(CONFIG_VIDEO_G2D) += g2d/ ++obj-$(CONFIG_VIDEO_G3D) += g3d/ ++obj-$(CONFIG_VIDEO_CMM) += cmm/ ++ ++EXTRA_CFLAGS += -Idrivers/media/video ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/cmm/Kconfig linux-2.6.28.6/drivers/media/video/samsung/cmm/Kconfig +--- linux-2.6.28/drivers/media/video/samsung/cmm/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/cmm/Kconfig 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,11 @@ ++# ++# Configuration for CMM ++# ++ ++config VIDEO_CMM ++ bool "Samsung CMM Driver" ++ depends on VIDEO_SAMSUNG && CPU_S3C6410 ++ default n ++ ---help--- ++ This is a CMM driver for Samsung S3C6410. ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/cmm/Makefile linux-2.6.28.6/drivers/media/video/samsung/cmm/Makefile +--- linux-2.6.28/drivers/media/video/samsung/cmm/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/cmm/Makefile 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,10 @@ ++################################################# ++# Makefile for CMM ++# 2009 (C) Samsung Electronics ++# Author : satish ++################################################# ++ ++obj-$(CONFIG_VIDEO_CMM) += s3c_cmm.o ++ ++EXTRA_CFLAGS += -Idrivers/media/video ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/cmm/s3c_cmm.c linux-2.6.28.6/drivers/media/video/samsung/cmm/s3c_cmm.c +--- linux-2.6.28/drivers/media/video/samsung/cmm/s3c_cmm.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/cmm/s3c_cmm.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,848 @@ ++/* linux/driver/media/video/samsung/cmm/s3c_cmm.c ++ * ++ * C file for Samsung CMM (Codec Memory Management) driver ++ * ++ * Satish, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "s3c_cmm.h" ++ ++/*#define CMM_DEBUG */ ++#ifdef CMM_DEBUG ++#define CMM_MSG printk ++#else ++#define CMM_MSG(format,args...) ++#endif ++ ++static int s3c_cmm_instanceNo[S3C_CMM_MAX_INSTANCE_NUM]; ++static struct mutex *s3c_cmm_mutex = NULL; ++ ++dma_addr_t s3c_cmm_buffer_start; ++ ++s3c_cmm_alloc_mem_t *s3c_cmm_allocmem_head; ++s3c_cmm_alloc_mem_t *s3c_cmm_allocmem_tail; ++s3c_cmm_free_mem_t *s3c_cmm_freemem_head; ++s3c_cmm_free_mem_t *s3c_cmm_freemem_tail; ++ ++unsigned char *s3c_cmm_cached_vir_addr; ++unsigned char *s3c_cmm_noncached_vir_addr; ++ ++static void insertnode_alloclist(s3c_cmm_alloc_mem_t *node, int inst_no); ++static void insertnode_freelist(s3c_cmm_free_mem_t *node, int inst_no); ++static void deletenode_alloclist(s3c_cmm_alloc_mem_t *node, int inst_no); ++static void deletenode_freelist( s3c_cmm_free_mem_t *node, int inst_no); ++static void release_alloc_mem(s3c_cmm_alloc_mem_t *node, ++ s3c_cmm_codec_mem_ctx_t *CodecMem); ++static void merge_fragmented_mem(int inst_no); ++static unsigned int get_mem_area(int allocSize, int inst_no, char cache_flag); ++static s3c_cmm_alloc_mem_t * get_codec_virt_addr(int inst_no, ++ s3c_cmm_codec_mem_alloc_arg_t *in_param); ++static int get_instance_num(void); ++static void return_instance_num(int inst_no); ++static void print_list(void); ++ ++static int s3c_cmm_open(struct inode *inode, struct file *file) ++{ ++ s3c_cmm_codec_mem_ctx_t *CodecMem; ++ int inst_no; ++ ++ ++ mutex_lock(s3c_cmm_mutex); ++ ++ /* check the number of instance */ ++ if((inst_no = get_instance_num()) < 0){ ++ printk(KERN_ERR "\n%s: Instance Number error-too many instance\r\n" ++ , __FUNCTION__); ++ mutex_unlock(s3c_cmm_mutex); ++ return FALSE; ++ } ++ ++ CodecMem = (s3c_cmm_codec_mem_ctx_t *) ++ kmalloc(sizeof(s3c_cmm_codec_mem_ctx_t), GFP_KERNEL); ++ if(CodecMem == NULL){ ++ printk(KERN_ERR "\n%s: CodecMem application failed\n", __FUNCTION__); ++ mutex_unlock(s3c_cmm_mutex); ++ return FALSE; ++ } ++ ++ memset(CodecMem, 0x00, sizeof(s3c_cmm_codec_mem_ctx_t)); ++ ++ CodecMem->inst_no = inst_no; ++ CMM_MSG(KERN_DEBUG "\n****************************\n[CMM_Open]" ++ "s3c_cmm_instanceNo : %d\n****************************\n", ++ CodecMem->inst_no); ++ print_list(); ++ ++ file->private_data = (s3c_cmm_codec_mem_ctx_t*)CodecMem; ++ ++ mutex_unlock(s3c_cmm_mutex); ++ ++ return 0; ++} ++ ++ ++static int s3c_cmm_release(struct inode *inode, struct file *file) ++{ ++ s3c_cmm_codec_mem_ctx_t *CodecMem; ++ s3c_cmm_alloc_mem_t *node, *tmp_node; ++ ++ ++ mutex_lock(s3c_cmm_mutex); ++ ++ CodecMem = (s3c_cmm_codec_mem_ctx_t *)file->private_data; ++ CMM_MSG(KERN_DEBUG "\n%s: [%d][CMM Close] \n", __FUNCTION__, ++ CodecMem->inst_no); ++ ++ if(!CodecMem){ ++ printk(KERN_ERR "\n%s: CMM Invalid Input Handle\r\n", __FUNCTION__); ++ mutex_unlock(s3c_cmm_mutex); ++ return FALSE; ++ } ++ ++ CMM_MSG(KERN_DEBUG "\n%s: CodecMem->inst_no : %d\n", __FUNCTION__ ++ , CodecMem->inst_no); ++ ++ /* release u_addr and v_addr accoring to inst_no */ ++ for(node = s3c_cmm_allocmem_head; node != s3c_cmm_allocmem_tail; ++ node = node->next){ ++ if(node->inst_no == CodecMem->inst_no){ ++ tmp_node = node; ++ node = node->prev; ++ release_alloc_mem(tmp_node, CodecMem); ++ } ++ } ++ ++ CMM_MSG(KERN_DEBUG "\n%s: [%d]instance merge_fragmented_mem\n", ++ __FUNCTION__, CodecMem->inst_no); ++ merge_fragmented_mem(CodecMem->inst_no); ++ ++ return_instance_num(CodecMem->inst_no); ++ ++ kfree(CodecMem); ++ mutex_unlock(s3c_cmm_mutex); ++ ++ return 0; ++} ++ ++ ++static ssize_t s3c_cmm_write (struct file *file, const char *buf, size_t count, loff_t *pos) ++{ ++ return 0; ++} ++ ++static ssize_t s3c_cmm_read(struct file *file, char *buf, size_t count, loff_t *pos) ++{ ++ return 0; ++} ++ ++static int s3c_cmm_ioctl(struct inode *inode, struct file *file, unsigned ++ int cmd, unsigned long arg) ++{ ++ int ret; ++ s3c_cmm_codec_mem_ctx_t *CodecMem; ++ s3c_cmm_codec_mem_alloc_arg_t codec_mem_alloc_arg; ++ s3c_cmm_codec_cache_flush_arg_t codec_cache_flush_arg; ++ s3c_cmm_codec_get_phy_addr_arg_t codec_get_phy_addr_arg; ++ BOOL result = TRUE; ++ void *start, *end; ++ s3c_cmm_alloc_mem_t *node; ++ s3c_cmm_codec_mem_free_arg_t codec_mem_free_arg; ++ ++ CodecMem = (s3c_cmm_codec_mem_ctx_t *)file->private_data; ++ if (!CodecMem) { ++ printk(KERN_ERR "\n%s: CMM Invalid Input Handle\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ mutex_lock(s3c_cmm_mutex); ++ ++ switch (cmd){ ++ case S3C_CMM_IOCTL_CODEC_MEM_ALLOC: ++ CMM_MSG(KERN_DEBUG"\n%s: S3C_CMM_IOCTL_CODEC_MEM_ALLOC\n", ++ __FUNCTION__); ++ ++ ret = copy_from_user(&codec_mem_alloc_arg, ++ (s3c_cmm_codec_mem_alloc_arg_t *)arg ++ , sizeof(s3c_cmm_codec_mem_alloc_arg_t)); ++ ++ node = get_codec_virt_addr(CodecMem->inst_no, ++ &codec_mem_alloc_arg); ++ if(node == NULL){ ++ result = FALSE; ++ break; ++ } ++ ++ ret = copy_to_user((void *)arg, (void *)&codec_mem_alloc_arg ++ , sizeof(s3c_cmm_codec_mem_alloc_arg_t)); ++ break; ++ ++ case S3C_CMM_IOCTL_CODEC_MEM_FREE: ++ CMM_MSG(KERN_DEBUG "\n%s: S3C_CMM_IOCTL_CODEC_MEM_FREE\n", ++ __FUNCTION__); ++ ++ ret = copy_from_user(&codec_mem_free_arg, ++ (s3c_cmm_codec_mem_free_arg_t *)arg ++ , sizeof(s3c_cmm_codec_mem_free_arg_t)); ++ ++ for(node = s3c_cmm_allocmem_head; ++ node != s3c_cmm_allocmem_tail; node = node->next) { ++ if(node->u_addr == (unsigned char *)codec_mem_free_arg.u_addr) ++ break; ++ } ++ ++ if(node == s3c_cmm_allocmem_tail){ ++ CMM_MSG(KERN_DEBUG "\n%s: invalid virtual address(0x%x)\r\n" ++ , __FUNCTION__,codec_mem_free_arg.u_addr); ++ result = FALSE; ++ break; ++ } ++ ++ release_alloc_mem(node, CodecMem); ++ break; ++ ++ ++ case S3C_CMM_IOCTL_CODEC_GET_PHY_ADDR: ++ ret = copy_from_user(&codec_get_phy_addr_arg, ++ (s3c_cmm_codec_get_phy_addr_arg_t *)arg ++ , sizeof(s3c_cmm_codec_get_phy_addr_arg_t)); ++ ++ for(node = s3c_cmm_allocmem_head; ++ node != s3c_cmm_allocmem_tail; node = node->next) { ++ if(node->u_addr == ++ (unsigned char *)codec_get_phy_addr_arg.u_addr) ++ break; ++ } ++ ++ if(node == s3c_cmm_allocmem_tail){ ++ CMM_MSG(KERN_DEBUG "\n%s: invalid virtual address(0x%x)\r\n" ++ , __FUNCTION__, codec_get_phy_addr_arg.u_addr); ++ result = FALSE; ++ break; ++ } ++ ++ if(node->cacheFlag) ++ codec_get_phy_addr_arg.p_addr = node->cached_p_addr; ++ else ++ codec_get_phy_addr_arg.p_addr = node->uncached_p_addr; ++ ++ ret = copy_to_user((void *)arg, (void *)&codec_get_phy_addr_arg ++ , sizeof(s3c_cmm_codec_get_phy_addr_arg_t)); ++ ++ break; ++ case S3C_CMM_IOCTL_CODEC_MERGE_FRAGMENTATION: ++ ++ merge_fragmented_mem(CodecMem->inst_no); ++ ++ break; ++ ++ case S3C_CMM_IOCTL_CODEC_CACHE_FLUSH: ++ case S3C_CMM_IOCTL_CODEC_CACHE_INVALIDATE: ++ CMM_MSG(KERN_DEBUG "\n%s: S3C_CMM_IOCTL_CODEC_CACHE_INVALIDATE\n", ++ __FUNCTION__); ++ ++ ret = copy_from_user(&codec_cache_flush_arg, ++ (s3c_cmm_codec_cache_flush_arg_t *)arg ++ , sizeof(s3c_cmm_codec_cache_flush_arg_t)); ++ ++ for(node = s3c_cmm_allocmem_head; ++ node != s3c_cmm_allocmem_tail; node = node->next) { ++ if(node->u_addr == ++ (unsigned char *)codec_cache_flush_arg.u_addr) ++ break; ++ } ++ ++ if(node == s3c_cmm_allocmem_tail){ ++ CMM_MSG(KERN_DEBUG "\n%s: invalid virtual address(0x%x)\r\n" ++ , __FUNCTION__,codec_cache_flush_arg.u_addr); ++ result = FALSE; ++ break; ++ } ++ ++ start = node->v_addr; ++ end = start + codec_cache_flush_arg.size; ++ dma_cache_maint(start,codec_cache_flush_arg.size,DMA_FROM_DEVICE); ++ ++ break; ++ ++ case S3C_CMM_IOCTL_CODEC_CACHE_CLEAN: ++ CMM_MSG(KERN_DEBUG "\n%s: S3C_CMM_IOCTL_CODEC_CACHE_CLEAN\n", ++ __FUNCTION__); ++ ++ ret = copy_from_user(&codec_cache_flush_arg, ++ (s3c_cmm_codec_cache_flush_arg_t *)arg ++ , sizeof(s3c_cmm_codec_cache_flush_arg_t)); ++ ++ for(node = s3c_cmm_allocmem_head; ++ node != s3c_cmm_allocmem_tail; node = node->next) { ++ if(node->u_addr == ++ (unsigned char *)codec_cache_flush_arg.u_addr) ++ break; ++ } ++ ++ if(node == s3c_cmm_allocmem_tail){ ++ CMM_MSG(KERN_DEBUG "\n%s: invalid virtual address(0x%x)\r\n" ++ , __FUNCTION__, codec_cache_flush_arg.u_addr); ++ result = FALSE; ++ break; ++ } ++ ++ start = node->v_addr; ++ end = start + codec_cache_flush_arg.size; ++ dma_cache_maint(start,codec_cache_flush_arg.size,DMA_TO_DEVICE); ++ break; ++ ++ case S3C_CMM_IOCTL_CODEC_CACHE_CLEAN_INVALIDATE: ++ CMM_MSG(KERN_DEBUG "\n%s: S3C_CMM_IOCTL_CODEC_CACHE_CLEAN_INVALIDATE\n", ++ __FUNCTION__); ++ ++ ret = copy_from_user(&codec_cache_flush_arg, ++ (s3c_cmm_codec_cache_flush_arg_t *)arg ++ , sizeof(s3c_cmm_codec_cache_flush_arg_t)); ++ ++ for(node = s3c_cmm_allocmem_head; ++ node != s3c_cmm_allocmem_tail; node = node->next) { ++ if(node->u_addr == ++ (unsigned char *)codec_cache_flush_arg.u_addr) ++ break; ++ } ++ ++ if(node == s3c_cmm_allocmem_tail){ ++ CMM_MSG(KERN_DEBUG "\n%s: invalid virtual address(0x%x)\r\n" ++ , __FUNCTION__, codec_cache_flush_arg.u_addr); ++ result = FALSE; ++ break; ++ } ++ ++ start = node->v_addr; ++ end = start + codec_cache_flush_arg.size; ++ dma_cache_maint(start,codec_cache_flush_arg.size,DMA_BIDIRECTIONAL); ++ ++ break; ++ ++ default : ++ printk(KERN_ERR "\n%s: DD::CMM Invalid ioctl : 0x%X\r\n", ++ __FUNCTION__, cmd); ++ } ++ ++ mutex_unlock(s3c_cmm_mutex); ++ return result; ++} ++ ++ ++int s3c_cmm_mmap(struct file *filp, struct vm_area_struct *vma) ++{ ++ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; ++ unsigned long size; ++ unsigned long maxSize; ++ unsigned long pageFrameNo = 0; ++ ++ ++ CMM_MSG(KERN_DEBUG "\n%s: vma->vm_end - vma->vm_start = %d\n", ++ __FUNCTION__, offset); ++ ++ if(offset == 0) { ++ pageFrameNo = __phys_to_pfn(s3c_cmm_buffer_start); ++ maxSize = S3C_CMM_CODEC_CACHED_MEM_SIZE + PAGE_SIZE - ++ (S3C_CMM_CODEC_CACHED_MEM_SIZE % PAGE_SIZE); ++ vma->vm_flags |= VM_RESERVED | VM_IO; ++ size = S3C_CMM_CODEC_CACHED_MEM_SIZE; ++ } ++ else if(offset == S3C_CMM_CODEC_CACHED_MEM_SIZE) { ++ pageFrameNo = __phys_to_pfn(s3c_cmm_buffer_start + ++ S3C_CMM_CODEC_CACHED_MEM_SIZE); ++ maxSize = S3C_CMM_CODEC_NON_CACHED_MEM_SIZE + PAGE_SIZE - ++ (S3C_CMM_CODEC_NON_CACHED_MEM_SIZE % PAGE_SIZE); ++ vma->vm_flags |= VM_RESERVED | VM_IO; ++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ size = S3C_CMM_CODEC_NON_CACHED_MEM_SIZE; ++ } ++ ++ if( remap_pfn_range(vma, vma->vm_start, pageFrameNo, size, \ ++ vma->vm_page_prot) ) { ++ printk(KERN_ERR "\n%s: cmm remap error \n", __FUNCTION__); ++ return -EAGAIN; ++ } ++ ++ return 0; ++} ++ ++ ++static struct file_operations s3c_cmm_fops = { ++owner: THIS_MODULE, ++ open: s3c_cmm_open, ++ release: s3c_cmm_release, ++ ioctl: s3c_cmm_ioctl, ++ read: s3c_cmm_read, ++ write: s3c_cmm_write, ++ mmap: s3c_cmm_mmap, ++}; ++ ++ ++ ++static struct miscdevice s3c_cmm_miscdev = { ++minor: 250, ++ name: "s3c-cmm", ++ fops: &s3c_cmm_fops ++}; ++ ++static char banner[] __initdata = KERN_INFO "S3C CMM Driver, (c) 2008 Samsung Electronics\n"; ++ ++static int __init s3c_cmm_init(void) ++{ ++ int ret; ++ s3c_cmm_free_mem_t *node; ++ s3c_cmm_alloc_mem_t *alloc_node; ++ ++ printk(banner); ++ ++ /* mutex creation and initialization */ ++ s3c_cmm_mutex = (struct mutex *)kmalloc(sizeof(struct mutex), GFP_KERNEL); ++ if (s3c_cmm_mutex == NULL) { ++ printk(KERN_ERR "\n%s: CMM mutex initialize error\n", __FUNCTION__); ++ return -ENOMEM; ++ } ++ ++ mutex_init(s3c_cmm_mutex); ++ ++ mutex_lock(s3c_cmm_mutex); ++ ++ ret = misc_register(&s3c_cmm_miscdev); ++ ++ s3c_cmm_buffer_start = s3c_get_media_memory(S3C_MDEV_CMM); ++ ++ /* First 4MB will use cacheable memory */ ++ s3c_cmm_cached_vir_addr = (unsigned char *)phys_to_virt(s3c_cmm_buffer_start); ++ CMM_MSG(KERN_DEBUG "\n%s: cached_vir_addr 0x%x\n", ++ __FUNCTION__,s3c_cmm_cached_vir_addr); ++ ++ /* Second 4MB will use non-cacheable memory */ ++ s3c_cmm_noncached_vir_addr = (unsigned char *) ++ phys_to_virt (s3c_cmm_buffer_start + ++ S3C_CMM_CODEC_CACHED_MEM_SIZE); ++ ++ /* init alloc list, if(s3c_cmm_allocmem_head == s3c_cmm_allocmem_tail) ++ * then, the list is NULL */ ++ alloc_node = (s3c_cmm_alloc_mem_t *)kmalloc(sizeof(s3c_cmm_alloc_mem_t), ++ GFP_KERNEL); ++ memset(alloc_node, 0x00, sizeof(s3c_cmm_alloc_mem_t)); ++ alloc_node->next = alloc_node; ++ alloc_node->prev = alloc_node; ++ s3c_cmm_allocmem_head = alloc_node; ++ s3c_cmm_allocmem_tail = s3c_cmm_allocmem_head; ++ ++ /* init free list, if(s3c_cmm_freemem_head == s3c_cmm_freemem_tail) ++ * then, the list is NULL */ ++ node = (s3c_cmm_free_mem_t *)kmalloc(sizeof(s3c_cmm_free_mem_t), ++ GFP_KERNEL); ++ memset(node, 0x00, sizeof(s3c_cmm_free_mem_t)); ++ node->next = node; ++ node->prev = node; ++ s3c_cmm_freemem_head = node; ++ s3c_cmm_freemem_tail = s3c_cmm_freemem_head; ++ ++ node = (s3c_cmm_free_mem_t *)kmalloc(sizeof(s3c_cmm_free_mem_t), GFP_KERNEL); ++ memset(node, 0x00, sizeof(s3c_cmm_free_mem_t)); ++ node->startAddr = s3c_cmm_buffer_start; ++ node->cacheFlag = 1; ++ node->size = S3C_CMM_CODEC_CACHED_MEM_SIZE; ++ insertnode_freelist(node, -1); ++ ++ node = (s3c_cmm_free_mem_t *)kmalloc(sizeof(s3c_cmm_free_mem_t), GFP_KERNEL); ++ memset(node, 0x00, sizeof(s3c_cmm_free_mem_t)); ++ node->startAddr = s3c_cmm_buffer_start + S3C_CMM_CODEC_CACHED_MEM_SIZE; ++ node->cacheFlag = 0; ++ node->size = S3C_CMM_CODEC_NON_CACHED_MEM_SIZE; ++ insertnode_freelist(node, -1); ++ ++ mutex_unlock(s3c_cmm_mutex); ++ ++ return 0; ++} ++ ++static void __exit s3c_cmm_exit(void) ++{ ++ ++ CMM_MSG(KERN_DEBUG "\n%s: CMM_Deinit\n", __FUNCTION__); ++ ++ mutex_destroy(s3c_cmm_mutex); ++ ++ misc_deregister(&s3c_cmm_miscdev); ++ ++ printk("S3C CMM driver module exit\n"); ++} ++ ++ ++/* insert node ahead of s3c_cmm_allocmem_head */ ++static void insertnode_alloclist(s3c_cmm_alloc_mem_t *node, int inst_no) ++{ ++ CMM_MSG(KERN_DEBUG "\n%s: [%d]instance (cached_p_addr : 0x%08x uncached_p_addr" ++ " : 0x%08x size:%ld cacheflag : %d)\n", __FUNCTION__ ++ ,inst_no, node->cached_p_addr, node->uncached_p_addr ++ , node->size, node->cacheFlag); ++ node->next = s3c_cmm_allocmem_head; ++ node->prev = s3c_cmm_allocmem_head->prev; ++ s3c_cmm_allocmem_head->prev->next = node; ++ s3c_cmm_allocmem_head->prev = node; ++ s3c_cmm_allocmem_head = node; ++ CMM_MSG(KERN_DEBUG "\n%s: Finished insertnode_alloclist\n", __FUNCTION__); ++} ++ ++/* insert node ahead of s3c_cmm_freemem_head */ ++static void insertnode_freelist(s3c_cmm_free_mem_t *node, int inst_no) ++{ ++ CMM_MSG(KERN_DEBUG "\n%s: [%d]instance(startAddr : 0x%08x size:%ld" ++ " cached flag : %d)\n", __FUNCTION__,inst_no ++ , node->startAddr, node->size, node->cacheFlag); ++ node->next = s3c_cmm_freemem_head; ++ node->prev = s3c_cmm_freemem_head->prev; ++ s3c_cmm_freemem_head->prev->next = node; ++ s3c_cmm_freemem_head->prev = node; ++ s3c_cmm_freemem_head = node; ++ ++ print_list(); ++} ++ ++static void deletenode_alloclist(s3c_cmm_alloc_mem_t *node, int inst_no) ++{ ++ CMM_MSG(KERN_DEBUG "\n%s: [%d]instance (uncached_p_addr : 0x%08x cached_p_addr" ++ " : 0x%08x size:%ld cacheflag : %d)\n", __FUNCTION__ ++ ,inst_no,node->uncached_p_addr, node->cached_p_addr ++ , node->size, node->cacheFlag); ++ ++ if(node == s3c_cmm_allocmem_tail){ ++ CMM_MSG(KERN_DEBUG "\n%s: InValid node\n", __FUNCTION__); ++ return; ++ } ++ ++ if(node == s3c_cmm_allocmem_head) ++ s3c_cmm_allocmem_head = node->next; ++ ++ node->prev->next = node->next; ++ node->next->prev = node->prev; ++ ++ kfree(node); ++ ++ print_list(); ++} ++ ++static void deletenode_freelist( s3c_cmm_free_mem_t *node, int inst_no) ++{ ++ CMM_MSG(KERN_DEBUG "\n%s: [%d]deletenode_freelist(startAddr : 0x%08x size:%ld)\n" ++ , __FUNCTION__, inst_no, node->startAddr, node->size); ++ if(node == s3c_cmm_freemem_tail){ ++ printk(KERN_ERR "\n%s: InValid node\n", __FUNCTION__); ++ return; ++ } ++ ++ if(node == s3c_cmm_freemem_head) ++ s3c_cmm_freemem_head = node->next; ++ ++ node->prev->next = node->next; ++ node->next->prev = node->prev; ++ ++ kfree(node); ++} ++ ++/* Releae cacheable memory */ ++static void release_alloc_mem( s3c_cmm_alloc_mem_t *node, ++ s3c_cmm_codec_mem_ctx_t *CodecMem) ++{ ++ s3c_cmm_free_mem_t *free_node; ++ ++ ++ free_node = (s3c_cmm_free_mem_t *)kmalloc(sizeof(s3c_cmm_free_mem_t), GFP_KERNEL); ++ ++ if(node->cacheFlag) { ++ free_node->startAddr = node->cached_p_addr; ++ free_node->cacheFlag = 1; ++ } ++ else { ++ free_node->startAddr = node->uncached_p_addr; ++ free_node->cacheFlag = 0; ++ } ++ ++ free_node->size = node->size; ++ insertnode_freelist(free_node, CodecMem->inst_no); ++ ++ /* Delete from AllocMem list */ ++ deletenode_alloclist(node, CodecMem->inst_no); ++} ++ ++ ++ ++/* Remove Fragmentation in FreeMemList */ ++static void merge_fragmented_mem(int inst_no) ++{ ++ s3c_cmm_free_mem_t *node1, *node2; ++ ++ node1 = s3c_cmm_freemem_head; ++ ++ while(node1 != s3c_cmm_freemem_tail){ ++ node2 = s3c_cmm_freemem_head; ++ while(node2 != s3c_cmm_freemem_tail){ ++ if( (node1->startAddr + node1->size == node2->startAddr) ++ && (node1->cacheFlag == node2->cacheFlag) ){ ++ node1->size += node2->size; ++ CMM_MSG(KERN_DEBUG "\n%s: find merge area !! ( node1->startAddr +" ++ " node1->size == node2->startAddr)\n", __FUNCTION__); ++ deletenode_freelist(node2, inst_no); ++ break; ++ } ++ else if( (node1->startAddr == node2->startAddr + node2->size) ++ && (node1->cacheFlag == node2->cacheFlag) ){ ++ CMM_MSG(KERN_DEBUG "\n%s: find merge area !! ( node1->startAddr == " ++ "node2->startAddr + node2->size)\n", __FUNCTION__); ++ node1->startAddr = node2->startAddr; ++ node1->size += node2->size; ++ deletenode_freelist(node2, inst_no); ++ break; ++ } ++ node2 = node2->next; ++ } ++ node1 = node1->next; ++ } ++} ++ ++static unsigned int get_mem_area(int allocSize, int inst_no, char cache_flag) ++{ ++ s3c_cmm_free_mem_t *node, *match_node = NULL; ++ unsigned int allocAddr = 0; ++ ++ ++ CMM_MSG(KERN_DEBUG "\n%s: request Size : %ld\n", __FUNCTION__, allocSize); ++ ++ if(s3c_cmm_freemem_head == s3c_cmm_freemem_tail){ ++ printk(KERN_ERR "\n%s: all memory is gone\n", __FUNCTION__); ++ return(allocAddr); ++ } ++ ++ /* find best chunk of memory */ ++ for(node = s3c_cmm_freemem_head; ++ node != s3c_cmm_freemem_tail; node = node->next) { ++ if(match_node != NULL) ++ { ++ if(cache_flag) ++ { ++ if( (node->size >= allocSize) && ++ (node->size < match_node->size) ++ && (node->cacheFlag) ) ++ match_node = node; ++ } ++ else ++ { ++ if( (node->size >= allocSize) && ++ (node->size < match_node->size) ++ && (!node->cacheFlag) ) ++ match_node = node; ++ } ++ } ++ else ++ { ++ if(cache_flag) ++ { ++ if( (node->size >= allocSize) && (node->cacheFlag) ) ++ match_node = node; ++ } ++ else ++ { ++ if( (node->size >= allocSize) && (!node->cacheFlag) ) ++ match_node = node; ++ } ++ } ++ } ++ ++ if(match_node != NULL) { ++ CMM_MSG(KERN_DEBUG "\n%s: match : startAddr(0x%08x) size(%ld) cache flag(%d)\n" ++ , __FUNCTION__,match_node->startAddr ++ ,match_node->size, match_node->cacheFlag); ++ } ++ ++ /* rearange FreeMemArea */ ++ if(match_node != NULL){ ++ allocAddr = match_node->startAddr; ++ match_node->startAddr += allocSize; ++ match_node->size -= allocSize; ++ ++ if(match_node->size == 0) /* delete match_node */ ++ deletenode_freelist(match_node, inst_no); ++ ++ return(allocAddr); ++ }else { ++ printk("there is no suitable chunk\n"); ++ return 0; ++ } ++ ++ return(allocAddr); ++} ++ ++ ++static s3c_cmm_alloc_mem_t * get_codec_virt_addr(int inst_no, ++ s3c_cmm_codec_mem_alloc_arg_t *in_param) ++{ ++ ++ unsigned int p_startAddr; ++ s3c_cmm_alloc_mem_t *p_allocMem; ++ ++ ++ /* if user request cachable area, allocate from reserved area */ ++ /* if user request uncachable area, allocate dynamically */ ++ p_startAddr = get_mem_area((int)in_param->buffSize, ++ inst_no, in_param->cacheFlag); ++ ++ if(!p_startAddr){ ++ CMM_MSG(KERN_DEBUG "\n%s: There is no more memory\n\r", ++ __FUNCTION__); ++ in_param->out_addr = -1; ++ return NULL; ++ } ++ ++ p_allocMem = (s3c_cmm_alloc_mem_t *)kmalloc(sizeof(s3c_cmm_alloc_mem_t), GFP_KERNEL); ++ memset(p_allocMem, 0x00, sizeof(s3c_cmm_alloc_mem_t)); ++ ++ ++ if(in_param->cacheFlag) { ++ p_allocMem->cached_p_addr = p_startAddr; ++ p_allocMem->v_addr = s3c_cmm_cached_vir_addr + ++ (p_allocMem->cached_p_addr - ++ s3c_cmm_buffer_start); ++ p_allocMem->u_addr = (unsigned char *)(in_param->cached_mapped_addr + ++ (p_allocMem->cached_p_addr - s3c_cmm_buffer_start)); ++ ++ if (p_allocMem->v_addr == NULL) { ++ CMM_MSG(KERN_DEBUG "\n%s: Mapping Failed [PA:0x%08x]\n\r" ++ , __FUNCTION__, p_allocMem->cached_p_addr); ++ return NULL; ++ } ++ } ++ else { ++ p_allocMem->uncached_p_addr = p_startAddr; ++ p_allocMem->v_addr = s3c_cmm_noncached_vir_addr + ++ (p_allocMem->uncached_p_addr - s3c_cmm_buffer_start ++ - S3C_CMM_CODEC_CACHED_MEM_SIZE); ++ p_allocMem->u_addr = (unsigned char *)(in_param->non_cached_mapped_addr + ++ (p_allocMem->uncached_p_addr - s3c_cmm_buffer_start ++ - S3C_CMM_CODEC_CACHED_MEM_SIZE)); ++ ++ if (p_allocMem->v_addr == NULL) ++ { ++ CMM_MSG(KERN_DEBUG "\n%s: Mapping Failed [PA:0x%08x]\n\r" ++ , __FUNCTION__, p_allocMem->uncached_p_addr); ++ return NULL; ++ } ++ } ++ ++ in_param->out_addr = (unsigned int)p_allocMem->u_addr; ++ CMM_MSG(KERN_DEBUG "\n%s: u_addr : 0x%x v_addr : 0x%x cached_p_addr : 0x%x," ++ " uncached_p_addr : 0x%x\n", __FUNCTION__,p_allocMem->u_addr ++ , p_allocMem->v_addr, p_allocMem->cached_p_addr ++ , p_allocMem->uncached_p_addr); ++ ++ ++ p_allocMem->size = (int)in_param->buffSize; ++ p_allocMem->inst_no = inst_no; ++ p_allocMem->cacheFlag = in_param->cacheFlag; ++ ++ insertnode_alloclist(p_allocMem, inst_no); ++ ++ return(p_allocMem); ++} ++ ++static int get_instance_num(void) ++{ ++ int i; ++ ++ for(i = 0; i < S3C_CMM_MAX_INSTANCE_NUM; i++) ++ { ++ if(s3c_cmm_instanceNo[i] == FALSE){ ++ s3c_cmm_instanceNo[i] = TRUE; ++ return i; ++ } ++ } ++ ++ if(i == S3C_CMM_MAX_INSTANCE_NUM) ++ return -1; ++ ++ return i; ++} ++ ++ ++static void return_instance_num(int inst_no) ++{ ++ s3c_cmm_instanceNo[inst_no] = FALSE; ++} ++ ++ ++static void print_list() ++{ ++ s3c_cmm_alloc_mem_t *node1; ++ s3c_cmm_free_mem_t *node2; ++ int count = 0; ++ unsigned int p_addr; ++ ++ for(node1 = s3c_cmm_allocmem_head; ++ node1 != s3c_cmm_allocmem_tail; node1 = node1->next){ ++ if(node1->cacheFlag) ++ p_addr = node1->cached_p_addr; ++ else ++ p_addr = (unsigned int)node1->uncached_p_addr; ++ ++ CMM_MSG(KERN_DEBUG "\n%s: [AllocList][%d] inst_no : %d p_addr : 0x%08x " ++ "v_addr:0x%08x size:%ld cacheflag : %d\n", __FUNCTION__ ++ ,count++, node1->inst_no, p_addr, node1->v_addr ++ , node1->size, node1->cacheFlag); ++ } ++ ++ count = 0; ++ for(node2 = s3c_cmm_freemem_head; ++ node2 != s3c_cmm_freemem_tail; node2 = node2->next){ ++ CMM_MSG(KERN_DEBUG "\n%s: [FreeList][%d] startAddr : 0x%08x size:%ld\n" ++ , __FUNCTION__, count++, node2->startAddr , node2->size); ++ ++ } ++} ++ ++module_init(s3c_cmm_init); ++module_exit(s3c_cmm_exit); ++ ++MODULE_AUTHOR("Jiun, Yu"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/cmm/s3c_cmm.h linux-2.6.28.6/drivers/media/video/samsung/cmm/s3c_cmm.h +--- linux-2.6.28/drivers/media/video/samsung/cmm/s3c_cmm.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/cmm/s3c_cmm.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,90 @@ ++/* linux/driver/media/video/cmm/s3c_cmm.h ++ * ++ * Header file for Samsung CMM (Codec Memory Management) driver ++ * ++ * Satish, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_CMM_H ++#define _S3C_CMM_H ++ ++ ++#define S3C_CMM_MAX_INSTANCE_NUM 10 ++ ++#define S3C_CMM_CODEC_CACHED_MEM_SIZE (4*1024*1024) ++#define S3C_CMM_CODEC_NON_CACHED_MEM_SIZE (4*1024*1024) ++#define S3C_CMM_CODEC_MEM_SIZE (8*1024*1024) ++ ++#define S3C_CMM_IOCTL_CODEC_MEM_ALLOC 0x0000001A ++#define S3C_CMM_IOCTL_CODEC_MEM_FREE 0x0000001B ++#define S3C_CMM_IOCTL_CODEC_CACHE_FLUSH 0x0000001C ++#define S3C_CMM_IOCTL_CODEC_GET_PHY_ADDR 0x0000001D ++#define S3C_CMM_IOCTL_CODEC_MERGE_FRAGMENTATION 0x0000001E ++#define S3C_CMM_IOCTL_CODEC_CACHE_INVALIDATE 0x0000001F ++#define S3C_CMM_IOCTL_CODEC_CACHE_CLEAN 0x00000020 ++#define S3C_CMM_IOCTL_CODEC_CACHE_CLEAN_INVALIDATE 0x00000021 ++ ++ ++typedef enum {FALSE, TRUE} BOOL; ++ ++typedef struct { ++ char cacheFlag; /* Cache or noncache flag */ ++ int size; /* memory size */ ++}s3c_cmm_alloc_pram_t; ++ ++typedef struct { ++ int inst_no; ++ int callerProcess; ++}s3c_cmm_codec_mem_ctx_t; ++ ++typedef struct alloc_mem_t { ++ struct alloc_mem_t *prev; ++ struct alloc_mem_t *next; ++ union{ ++ unsigned int cached_p_addr; /* physical address of cacheable area */ ++ unsigned int uncached_p_addr;/* physical address of non-cacheable area */ ++ }; ++ unsigned char *v_addr; /* virtual address in cached area */ ++ unsigned char *u_addr; /* copyed virtual address for user mode process */ ++ int size; /* memory size */ ++ int inst_no; ++ char cacheFlag; ++}s3c_cmm_alloc_mem_t; ++ ++typedef struct free_mem_t { ++ struct free_mem_t *prev; ++ struct free_mem_t *next; ++ unsigned int startAddr; ++ unsigned int size; ++ char cacheFlag; ++}s3c_cmm_free_mem_t; ++ ++/* ioctl arguments */ ++typedef struct { ++ char cacheFlag; ++ int buffSize; ++ unsigned int cached_mapped_addr; ++ unsigned int non_cached_mapped_addr; ++ unsigned int out_addr; ++}s3c_cmm_codec_mem_alloc_arg_t; ++ ++typedef struct { ++ unsigned int u_addr; ++}s3c_cmm_codec_mem_free_arg_t; ++ ++typedef struct { ++ unsigned int u_addr; ++ int size; ++}s3c_cmm_codec_cache_flush_arg_t; ++ ++typedef struct { ++ unsigned int u_addr; ++ unsigned int p_addr; ++}s3c_cmm_codec_get_phy_addr_arg_t; ++ ++#endif /* _S3C_CMM_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimc/Kconfig linux-2.6.28.6/drivers/media/video/samsung/fimc/Kconfig +--- linux-2.6.28/drivers/media/video/samsung/fimc/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimc/Kconfig 2009-10-21 20:23:48.000000000 +0200 +@@ -0,0 +1,57 @@ ++ ++if VIDEO_FIMC ++comment "FIMC configurations" ++endif ++ ++config VIDEO_FIMC ++ bool "Samsung Camera Interface (FIMC) driver" ++ depends on VIDEO_SAMSUNG && (ARCH_S3C64XX || ARCH_S5PC1XX) ++ default n ++ ---help--- ++ This is a video4linux driver for Samsung FIMC device. ++ ++config VIDEO_FIMC_DEBUG ++ bool "FIMC driver debug messages" ++ depends on VIDEO_FIMC ++ ++config VIDEO_FIMC_MIPI ++ bool "FIMC works with MIPI-CSI2 (Rx)" ++ depends on VIDEO_FIMC && ARCH_S5PC1XX ++ ++source "drivers/media/video/samsung/fimc/Kconfig-camera" ++ ++choice ++depends on OV965X ++prompt "Select source resolution" ++default OV965X_VGA ++config OV965X_VGA ++ bool "VGA(640X480)" ++ ---help--- ++ LIYUTAI OV965X camera module support. ++ ++config OV965X_QVGA ++ bool "QVGA(320X240)" ++ ---help--- ++ LIYUTAI OV965X camera module support. ++ ++config OV965X_SVGA ++ bool "SVGA(800X600)" ++ ---help--- ++ LIYUTAI OV965X camera module support. ++ ++config OV965X_SXGA ++ bool "SXGA(1280X1024)" ++ ---help--- ++ LIYUTAI OV965X camera module support. ++endchoice ++ ++config VIDEO_FIMC_CAM_CH ++ int "External Camera channel (0=A, 1=B)" ++ depends on VIDEO_FIMC ++ default "0" ++ ++config VIDEO_FIMC_CAM_RESET ++ int "Reset Type (0=low, 1=high)" ++ depends on VIDEO_FIMC ++ default "0" ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimc/Kconfig-camera linux-2.6.28.6/drivers/media/video/samsung/fimc/Kconfig-camera +--- linux-2.6.28/drivers/media/video/samsung/fimc/Kconfig-camera 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimc/Kconfig-camera 2009-10-21 20:15:20.000000000 +0200 +@@ -0,0 +1,23 @@ ++choice ++ prompt "External Camera" ++ depends on VIDEO_FIMC ++ ++config S5K4BA ++ bool "Samsung S5K4BA" ++ depends on VIDEO_FIMC ++ ---help--- ++ Samsung S5K4BA mobile camera support ++ ++config S5K3BA ++ bool "Samsung S5K3BA" ++ depends on VIDEO_FIMC ++ ---help--- ++ Samsung S5K3BA mobile camera support ++ ++config OV965X ++ bool "OVT OV965X" ++ depends on VIDEO_FIMC ++ ---help--- ++ LYT OV965X camera module support ++ ++endchoice +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimc/Makefile linux-2.6.28.6/drivers/media/video/samsung/fimc/Makefile +--- linux-2.6.28/drivers/media/video/samsung/fimc/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimc/Makefile 2009-10-21 20:27:50.000000000 +0200 +@@ -0,0 +1,13 @@ ++obj-$(CONFIG_VIDEO_FIMC) += s3c_fimc_core.o s3c_fimc_v4l2.o s3c_fimc_cfg.o ++obj-$(CONFIG_VIDEO_FIMC_MIPI) += s3c_csis.o ++obj-$(CONFIG_ARCH_S3C64XX) += s3c_fimc3x_regs.o ++obj-$(CONFIG_ARCH_S5PC1XX) += s3c_fimc4x_regs.o ++obj-$(CONFIG_S5K3BA) += s5k3ba.o ++obj-$(CONFIG_S5K4BA) += s5k4ba.o ++obj-$(CONFIG_OV965X) += ov965x.o ++ ++EXTRA_CFLAGS += -Idrivers/media/video ++ ++ifeq ($(CONFIG_VIDEO_FIMC_DEBUG),y) ++EXTRA_CFLAGS += -DDEBUG ++endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimc/ov965x.c linux-2.6.28.6/drivers/media/video/samsung/fimc/ov965x.c +--- linux-2.6.28/drivers/media/video/samsung/fimc/ov965x.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimc/ov965x.c 2009-10-23 17:06:20.000000000 +0200 +@@ -0,0 +1,195 @@ ++/* linux/drivers/media/video/samsung/ov965x.c ++ * ++ * Samsung ov965x CMOS Image Sensor driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "s3c_fimc.h" ++#include "ov965x.h" ++ ++#define OV965X_I2C_ADDR 0x60//0x5a ++ ++const static u16 ignore[] = { I2C_CLIENT_END }; ++const static u16 normal_addr[] = { (OV965X_I2C_ADDR >> 1), I2C_CLIENT_END }; ++const static u16 *forces[] = { NULL }; ++static struct i2c_driver ov965x_i2c_driver; ++ ++static struct s3c_fimc_camera ov965x_data = { ++ .id = CONFIG_VIDEO_FIMC_CAM_CH, ++ .type = CAM_TYPE_ITU, ++ .mode = ITU_601_YCBCR422_8BIT, ++ .order422 = CAM_ORDER422_8BIT_YCBYCR,//YCRYCB, ++ .clockrate = 24000000, ++ .width = 640,//800, ++ .height = 480,//600, ++ .offset = { ++ .h1 = 0, ++ .h2 = 0, ++ .v1 = 0, ++ .v2 = 0, ++ }, ++ ++ .polarity = { ++ .pclk = 0, ++ .vsync = 1, ++ .href = 0, ++ .hsync = 0, ++ }, ++ ++ .initialized = 0, ++}; ++ ++static struct i2c_client_address_data addr_data = { ++ .normal_i2c = normal_addr, ++ .probe = ignore, ++ .ignore = ignore, ++ .forces = forces, ++}; ++ ++static void ov965x_start(struct i2c_client *client) ++{ ++ int i; ++ ++ //printk("[CAM] OV965X init reg start...\n"); ++ for (i = 0; i < OV965X_INIT_REGS; i++) { ++ s3c_fimc_i2c_write(client, OV965X_init_reg[i].subaddr, \ ++ OV965X_init_reg[i].value); ++ } ++ //printk("[CAM] OV965X init reg end.\n"); ++} ++ ++static int ov965x_attach(struct i2c_adapter *adap, int addr, int kind) ++{ ++ struct i2c_client *c; ++ ++ c = kmalloc(sizeof(*c), GFP_KERNEL); ++ if (!c) ++ return -ENOMEM; ++ ++ memset(c, 0, sizeof(struct i2c_client)); ++ ++ strcpy(c->name, "ov965x"); ++ c->addr = addr; ++ c->adapter = adap; ++ c->driver = &ov965x_i2c_driver; ++ ++ ov965x_data.client = c; ++ ++ info("OV965X attached successfully\n"); ++ ++ return i2c_attach_client(c); ++} ++ ++static int ov965x_attach_adapter(struct i2c_adapter *adap) ++{ ++ int ret = 0; ++ //printk("[OV965X]ov965x_attach_adapter.\n"); ++ ++ s3c_fimc_register_camera(&ov965x_data); ++ ++ ret = i2c_probe(adap, &addr_data, ov965x_attach); ++ if (ret) { ++ err("failed to attach ov965x driver\n"); ++ ret = -ENODEV; ++ } ++ ++ return ret; ++} ++ ++static int ov965x_detach(struct i2c_client *client) ++{ ++ i2c_detach_client(client); ++ ++ return 0; ++} ++ ++static int ov965x_change_resolution(struct i2c_client *client, int res) ++{ ++ switch (res) { ++ case CAM_RES_DEFAULT: /* fall through */ ++ case CAM_RES_MAX: /* fall through */ ++ break; ++ ++ default: ++ err("unexpect value\n"); ++ } ++ ++ return 0; ++} ++ ++static int ov965x_change_whitebalance(struct i2c_client *client, enum s3c_fimc_wb_t type) ++{ ++ //s3c_fimc_i2c_write(client, 0xfc, 0x0); ++ //s3c_fimc_i2c_write(client, 0x30, type); ++ ++ return 0; ++} ++ ++static int ov965x_command(struct i2c_client *client, u32 cmd, void *arg) ++{ ++ switch (cmd) { ++ case I2C_CAM_INIT: ++ ///s3c_fimc_reset_camera(); ++ ov965x_start(client); ++ info("external camera initialized\n"); ++ break; ++ ++ case I2C_CAM_RESOLUTION: ++ ov965x_change_resolution(client, (int) arg); ++ break; ++ ++ case I2C_CAM_WB: ++ ov965x_change_whitebalance(client, (enum s3c_fimc_wb_t) arg); ++ break; ++ ++ default: ++ err("unexpect command\n"); ++ break; ++ } ++ ++ return 0; ++} ++ ++static struct i2c_driver ov965x_i2c_driver = { ++ .driver = { ++ .name = "ov965x", ++ }, ++ .id = I2C_DRIVERID_OV965X, ++ .attach_adapter = ov965x_attach_adapter, ++ .detach_client = ov965x_detach, ++ .command = ov965x_command, ++}; ++ ++static __init int ov965x_init(void) ++{ ++ return i2c_add_driver(&ov965x_i2c_driver); ++} ++ ++static __init void ov965x_exit(void) ++{ ++ i2c_del_driver(&ov965x_i2c_driver); ++} ++ ++module_init(ov965x_init) ++module_exit(ov965x_exit) ++ ++MODULE_AUTHOR("Jinsung, Yang "); ++MODULE_DESCRIPTION("Samsung ov965x I2C based CMOS Image Sensor driver"); ++MODULE_LICENSE("GPL"); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimc/ov965x.h linux-2.6.28.6/drivers/media/video/samsung/fimc/ov965x.h +--- linux-2.6.28/drivers/media/video/samsung/fimc/ov965x.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimc/ov965x.h 2009-10-21 20:38:23.000000000 +0200 +@@ -0,0 +1,360 @@ ++/* linux/drivers/media/video/samsung/OV965X.h ++ * ++ * Header file for Samsung OV965X CMOS Image Sensor driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++/******************************************************************************************* ++ # Display resolution standards # ++ ++ QCIF: 176 x 144 ++ CIF: 352 x 288 ++ QVGA: 320 x 240 ++ VGA: 640 x 480 ++ SVGA: 800 x 600 ++ XGA: 1024 x 768 ++ WXGA: 1280 x 800 ++ QVGA: 1280 x 960 ++ SXGA: 1280 x 1024 ++ SXGA+: 1400 x 1050 ++ WSXGA+: 1680 x 1050 ++ UXGA: 1600 x 1200 ++ WUXGA: 1920 x 1200 ++ QXGA: 2048 x 1536 ++********************************************************************************************/ ++ ++#ifndef _OV965X_H_ ++#define _OV965X_H_ ++ ++#define CHIP_DELAY 0xFF ++ ++typedef struct s3c_fimc_i2c_value { ++ u8 subaddr; ++ u8 value; ++} OV965X_t; ++ ++/* init */ ++#if defined(CONFIG_OV965X_VGA) ++OV965X_t OV965X_init_reg[] = ++{ ++ {0x12, 0x80}, // Camera Soft reset. Self cleared after reset. ++ {CHIP_DELAY, 10}, ++ //{0x11,0x80}, ++ {0x6a,0x3e}, ++ {0x3b,0x09},//09 ++ {0x13,0x8f},//e0//8f ++ {0x01,0x80}, ++ {0x02,0x80}, ++ {0x00,0x00}, ++ {0x10,0x00}, ++ {0x35,0x91}, ++ {0x0e,0xa0}, ++ {0x1e,0x34},//14 ++ {0xA8,0x80}, ++ //////////////VGA////////// ++ {0x04,0x00}, ++ {0x0c,0x04}, ++ {0x0d,0x80}, ++ {0x11,0x81}, ++ {0x12,0x40}, ++ {0x37,0x91}, ++ {0x38,0x12}, ++ {0x39,0x43}, ++ /////////////END///Square_Chiu ++ {0x18,0xc6}, ++ {0x17,0x26}, ++ {0x32,0xad}, ++ {0x03,0x00}, ++ {0x1a,0x3d}, ++ {0x19,0x01}, ++ {0x3f,0xa6}, ++ {0x14,0x2e}, ++ {0x15,0x10}, ++ {0x41,0x02}, ++ {0x42,0x08}, ++ {0x1b,0x00}, ++ {0x16,0x06}, ++ {0x33,0xe2}, ++ {0x34,0xbf}, ++ {0x96,0x04}, ++ {0x3a,0x00}, ++ {0x8e,0x00}, ++ {0x3c,0x77}, ++ {0x8B,0x06}, ++ {0x94,0x88}, ++ {0x95,0x88}, ++ {0x40,0xc1}, ++ {0x29,0x3f}, ++ {0x0f,0x42}, ++ {0x3d,0x92}, ++ {0x69,0x40}, ++ {0x5C,0xb9}, ++ {0x5D,0x96}, ++ {0x5E,0x10}, ++ {0x59,0xc0}, ++ {0x5A,0xaf}, ++ {0x5B,0x55}, ++ {0x43,0xf0}, ++ {0x44,0x10}, ++ {0x45,0x68}, ++ {0x46,0x96}, ++ {0x47,0x60}, ++ {0x48,0x80}, ++ {0x5F,0xe0}, ++ {0x60,0x8c}, ++ {0x61,0x20}, ++ {0xa5,0xd9}, ++ {0xa4,0x74}, ++ {0x8d,0x02}, ++ //{0x13,0xe7}, ++ {0x4f,0x3a}, ++ {0x50,0x3d}, ++ {0x51,0x03}, ++ {0x52,0x12}, ++ {0x53,0x26}, ++ {0x54,0x36}, ++ {0x55,0x45}, ++ {0x56,0x40}, ++ {0x57,0x40}, ++ {0x58,0x0d}, ++ {0x8C,0x23}, ++ {0x3E,0x02}, ++ {0xa9,0xb8}, ++ {0xaa,0x92}, ++ {0xab,0x0a}, ++ {0x8f,0xdf}, ++ {0x90,0x00}, ++ {0x91,0x00}, ++ {0x9f,0x00}, ++ {0xa0,0x00}, ++ {0x3A,0x01}, ++ {0x24,0x70}, ++ {0x25,0x64}, ++ {0x26,0xc3}, ++ {0x2a,0x00}, ++ {0x2b,0x00}, ++ {0x6c,0x40}, ++ {0x6d,0x30}, ++ {0x6e,0x4b}, ++ {0x6f,0x60}, ++ {0x70,0x70}, ++ {0x71,0x70}, ++ {0x72,0x70}, ++ {0x73,0x70}, ++ {0x74,0x60}, ++ {0x75,0x60}, ++ {0x76,0x50}, ++ {0x77,0x48}, ++ {0x78,0x3a}, ++ {0x79,0x2e}, ++ {0x7a,0x28}, ++ {0x7b,0x22}, ++ {0x7c,0x04}, ++ {0x7d,0x07}, ++ {0x7e,0x10}, ++ {0x7f,0x28}, ++ {0x80,0x36}, ++ {0x81,0x44}, ++ {0x82,0x52}, ++ {0x83,0x60}, ++ {0x84,0x6c}, ++ {0x85,0x78}, ++ {0x86,0x8c}, ++ {0x87,0x9e}, ++ {0x88,0xbb}, ++ {0x89,0xd2}, ++ {0x8a,0xe6}, ++ //{0x15, 0x12}, // PCLK reverse ++ ++}; ++#elif defined(CONFIG_OV965X_QVGA) ++OV965X_t OV965X_init_reg[] = ++{ ++ {0x12, 0x80}, // Camera Soft reset. Self cleared after reset. ++ {CHIP_DELAY, 10}, ++ {0x11,0x80}, ++ {0x6a,0x3e}, ++ {0x3b,0x09},//09 ++ {0x13,0x8f},//e0//8f ++ {0x01,0x80}, ++ {0x02,0x80}, ++ {0x00,0x00}, ++ {0x10,0x00}, ++ {0x39,0x43}, ++ {0x38,0x12}, ++ {0x37,0x00}, ++ {0x35,0x91}, ++ {0x0e,0xa0}, ++ {0x1e,0x14}, ++ {0xA8,0x80}, ++ {0x12,0x40}, ++ {0x04,0x00}, ++ {0x0c,0x04}, ++ {0x0d,0x80}, ++ {0x18,0xc6}, ++ {0x17,0x26}, ++ {0x32,0xad}, ++ {0x03,0x00}, ++ {0x1a,0x3d}, ++ {0x19,0x01}, ++ {0x3f,0xa6}, ++ {0x14,0x2e}, ++ {0x15,0x10}, ++ {0x41,0x02}, ++ {0x42,0x08}, ++ {0x1b,0x00}, ++ {0x16,0x06}, ++ {0x33,0xe2}, ++ {0x34,0xbf}, ++ {0x96,0x04}, ++ {0x3a,0x00}, ++ {0x8e,0x00}, ++ {0x3c,0x77}, ++ {0x8B,0x06}, ++ {0x94,0x88}, ++ {0x95,0x88}, ++ {0x40,0xc1}, ++ {0x29,0x3f}, ++ {0x0f,0x42}, ++ {0x3d,0x92}, ++ {0x69,0x40}, ++ {0x5C,0xb9}, ++ {0x5D,0x96}, ++ {0x5E,0x10}, ++ {0x59,0xc0}, ++ {0x5A,0xaf}, ++ {0x5B,0x55}, ++ {0x43,0xf0}, ++ {0x44,0x10}, ++ {0x45,0x68}, ++ {0x46,0x96}, ++ {0x47,0x60}, ++ {0x48,0x80}, ++ {0x5F,0xe0}, ++ {0x60,0x8c}, ++ {0x61,0x20}, ++ {0xa5,0xd9}, ++ {0xa4,0x74}, ++ {0x8d,0x02}, ++ //{0x13,0xe7}, ++ {0x4f,0x3a}, ++ {0x50,0x3d}, ++ {0x51,0x03}, ++ {0x52,0x12}, ++ {0x53,0x26}, ++ {0x54,0x36}, ++ {0x55,0x45}, ++ {0x56,0x40}, ++ {0x57,0x40}, ++ {0x58,0x0d}, ++ {0x8C,0x23}, ++ {0x3E,0x02}, ++ {0xa9,0xb8}, ++ {0xaa,0x92}, ++ {0xab,0x0a}, ++ {0x8f,0xdf}, ++ {0x90,0x00}, ++ {0x91,0x00}, ++ {0x9f,0x00}, ++ {0xa0,0x00}, ++ {0x3A,0x01}, ++ {0x24,0x70}, ++ {0x25,0x64}, ++ {0x26,0xc3}, ++ {0x2a,0x00}, ++ {0x2b,0x00}, ++ {0x6c,0x40}, ++ {0x6d,0x30}, ++ {0x6e,0x4b}, ++ {0x6f,0x60}, ++ {0x70,0x70}, ++ {0x71,0x70}, ++ {0x72,0x70}, ++ {0x73,0x70}, ++ {0x74,0x60}, ++ {0x75,0x60}, ++ {0x76,0x50}, ++ {0x77,0x48}, ++ {0x78,0x3a}, ++ {0x79,0x2e}, ++ {0x7a,0x28}, ++ {0x7b,0x22}, ++ {0x7c,0x04}, ++ {0x7d,0x07}, ++ {0x7e,0x10}, ++ {0x7f,0x28}, ++ {0x80,0x36}, ++ {0x81,0x44}, ++ {0x82,0x52}, ++ {0x83,0x60}, ++ {0x84,0x6c}, ++ {0x85,0x78}, ++ {0x86,0x8c}, ++ {0x87,0x9e}, ++ {0x88,0xbb}, ++ {0x89,0xd2}, ++ {0x8a,0xe6}, ++ //{0x15, 0x12}, // PCLK reverse ++}; ++#elif defined(CONFIG_OV965X_SVGA) ++OV965X_t OV965X_init_reg[] = ++{ ++ /* Only for VGA Mode */ ++ {0x25,0x64}, ++ {0x26,0xc3}, ++ {0x2a,0x00}, ++ {0x2b,0x00}, ++ {0x6c,0x40}, ++ {0x6d,0x30}, ++ {0x6e,0x4b}, ++ {0x6f,0x60}, ++ {0x70,0x70}, ++ {0x71,0x70}, ++ {0x72,0x70}, ++ {0x73,0x70}, ++ {0x74,0x60}, ++ {0x75,0x60}, ++ {0x76,0x50}, ++ {0x77,0x48}, ++ {0x78,0x3a}, ++ {0x79,0x2e}, ++ {0x7a,0x28}, ++ {0x7b,0x22}, ++ //YONGKAL ++}; ++#elif defined(CONFIG_OV965X_SXGA) ++OV965X_t OV965X_init_reg[] = ++{ ++ {0x25,0x64}, ++ {0x26,0xc3}, ++ {0x2a,0x00}, ++ {0x2b,0x00}, ++ {0x6c,0x40}, ++ {0x6d,0x30}, ++ {0x6e,0x4b}, ++ {0x6f,0x60}, ++ {0x70,0x70}, ++ {0x71,0x70}, ++ {0x72,0x70}, ++ {0x73,0x70}, ++ {0x74,0x60}, ++ {0x75,0x60}, ++ {0x76,0x50}, ++ {0x77,0x48}, ++ {0x78,0x3a}, ++ {0x79,0x2e}, ++ {0x7a,0x28}, ++ {0x7b,0x22}, ++}; ++#endif ++ ++#define OV965X_INIT_REGS (sizeof(OV965X_init_reg) / sizeof(OV965X_init_reg[0])) ++ ++#endif ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimc/s3c_csis.c linux-2.6.28.6/drivers/media/video/samsung/fimc/s3c_csis.c +--- linux-2.6.28/drivers/media/video/samsung/fimc/s3c_csis.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimc/s3c_csis.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,276 @@ ++/* linux/drivers/media/video/samsung/s3c_csis.c ++ * ++ * MIPI-CSI2 Support file for FIMC driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "s3c_csis.h" ++ ++static struct s3c_csis_info *s3c_csis; ++ ++static struct s3c_platform_csis *to_csis_plat(struct device *dev) ++{ ++ struct platform_device *pdev = to_platform_device(dev); ++ ++ return (struct s3c_platform_csis *) pdev->dev.platform_data; ++} ++ ++static int s3c_csis_set_info(void) ++{ ++ s3c_csis = (struct s3c_csis_info *) \ ++ kmalloc(sizeof(struct s3c_csis_info), GFP_KERNEL); ++ if (!s3c_csis) { ++ err("no memory for configuration\n"); ++ return -ENOMEM; ++ } ++ ++ strcpy(s3c_csis->name, S3C_CSIS_NAME); ++ s3c_csis->nr_lanes = S3C_CSIS_NR_LANES; ++ ++ return 0; ++} ++ ++static void s3c_csis_reset(void) ++{ ++ u32 cfg; ++ ++ cfg = readl(s3c_csis->regs + S3C_CSIS_CONTROL); ++ cfg |= S3C_CSIS_CONTROL_RESET; ++ writel(cfg, s3c_csis->regs + S3C_CSIS_CONTROL); ++} ++ ++static void s3c_csis_set_nr_lanes(int lanes) ++{ ++ u32 cfg; ++ ++ cfg = readl(s3c_csis->regs + S3C_CSIS_CONFIG); ++ cfg &= ~S3C_CSIS_CONFIG_NR_LANE_MASK; ++ ++ if (lanes == 1) ++ cfg |= S3C_CSIS_CONFIG_NR_LANE_1; ++ else ++ cfg |= S3C_CSIS_CONFIG_NR_LANE_2; ++ ++ writel(cfg, s3c_csis->regs + S3C_CSIS_CONFIG); ++} ++ ++static void s3c_csis_enable_interrupt(void) ++{ ++ u32 cfg = 0; ++ ++ /* enable all interrupts */ ++ cfg |= S3C_CSIS_INTMSK_EVEN_BEFORE_ENABLE | \ ++ S3C_CSIS_INTMSK_EVEN_AFTER_ENABLE | \ ++ S3C_CSIS_INTMSK_ODD_BEFORE_ENABLE | \ ++ S3C_CSIS_INTMSK_ODD_AFTER_ENABLE | \ ++ S3C_CSIS_INTMSK_ERR_SOT_HS_ENABLE | \ ++ S3C_CSIS_INTMSK_ERR_ESC_ENABLE | \ ++ S3C_CSIS_INTMSK_ERR_CTRL_ENABLE | \ ++ S3C_CSIS_INTMSK_ERR_ECC_ENABLE | \ ++ S3C_CSIS_INTMSK_ERR_CRC_ENABLE | \ ++ S3C_CSIS_INTMSK_ERR_ID_ENABLE; ++ ++ writel(cfg, s3c_csis->regs + S3C_CSIS_INTMSK); ++} ++ ++static void s3c_csis_disable_interrupt(void) ++{ ++ /* disable all interrupts */ ++ writel(0, s3c_csis->regs + S3C_CSIS_INTMSK); ++} ++ ++static void s3c_csis_system_on(void) ++{ ++ u32 cfg; ++ ++ cfg = readl(s3c_csis->regs + S3C_CSIS_CONTROL); ++ cfg |= S3C_CSIS_CONTROL_ENABLE; ++ writel(cfg, s3c_csis->regs + S3C_CSIS_CONTROL); ++} ++ ++static void s3c_csis_system_off(void) ++{ ++ u32 cfg; ++ ++ cfg = readl(s3c_csis->regs + S3C_CSIS_CONTROL); ++ cfg &= ~S3C_CSIS_CONTROL_ENABLE; ++ writel(cfg, s3c_csis->regs + S3C_CSIS_CONTROL); ++} ++ ++static void s3c_csis_phy_on(void) ++{ ++ u32 cfg; ++ ++ cfg = readl(s3c_csis->regs + S3C_CSIS_DPHYCTRL); ++ cfg |= S3C_CSIS_DPHYCTRL_ENABLE; ++ writel(cfg, s3c_csis->regs + S3C_CSIS_DPHYCTRL); ++} ++ ++static void s3c_csis_phy_off(void) ++{ ++ u32 cfg; ++ ++ cfg = readl(s3c_csis->regs + S3C_CSIS_DPHYCTRL); ++ cfg &= ~S3C_CSIS_DPHYCTRL_ENABLE; ++ writel(cfg, s3c_csis->regs + S3C_CSIS_DPHYCTRL); ++} ++ ++static void s3c_csis_start(struct platform_device *pdev) ++{ ++ struct s3c_platform_csis *plat; ++ ++ plat = to_csis_plat(&pdev->dev); ++ if (plat->cfg_phy_global) ++ plat->cfg_phy_global(pdev, 1); ++ ++ s3c_csis_reset(); ++ s3c_csis_set_nr_lanes(S3C_CSIS_NR_LANES); ++ s3c_csis_enable_interrupt(); ++ s3c_csis_system_on(); ++ s3c_csis_phy_on(); ++} ++ ++static void s3c_csis_stop(struct platform_device *pdev) ++{ ++ struct s3c_platform_csis *plat; ++ ++ s3c_csis_disable_interrupt(); ++ s3c_csis_system_off(); ++ s3c_csis_phy_off(); ++ ++ plat = to_csis_plat(&pdev->dev); ++ if (plat->cfg_phy_global) ++ plat->cfg_phy_global(pdev, 0); ++} ++ ++static irqreturn_t s3c_csis_irq(int irq, void *dev_id) ++{ ++ u32 cfg; ++ ++ /* just clearing the pends */ ++ cfg = readl(s3c_csis->regs + S3C_CSIS_INTSRC); ++ writel(cfg, s3c_csis->regs + S3C_CSIS_INTSRC); ++ ++ return IRQ_HANDLED; ++} ++ ++static int s3c_csis_probe(struct platform_device *pdev) ++{ ++ struct s3c_platform_csis *pdata; ++ struct resource *res; ++ ++ s3c_csis_set_info(); ++ ++ pdata = to_csis_plat(&pdev->dev); ++ if (pdata->cfg_gpio) ++ pdata->cfg_gpio(pdev); ++ ++ s3c_csis->clock = clk_get(&pdev->dev, pdata->clk_name); ++ if (IS_ERR(s3c_csis->clock)) { ++ err("failed to get csis clock source\n"); ++ return -EINVAL; ++ } ++ ++ clk_enable(s3c_csis->clock); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ err("failed to get io memory region\n"); ++ return -EINVAL; ++ } ++ ++ res = request_mem_region(res->start, res->end - res->start + 1, pdev->name); ++ if (!res) { ++ err("failed to request io memory region\n"); ++ return -EINVAL; ++ } ++ ++ /* ioremap for register block */ ++ s3c_csis->regs = ioremap(res->start, res->end - res->start + 1); ++ if (!s3c_csis->regs) { ++ err("failed to remap io region\n"); ++ return -EINVAL; ++ } ++ ++ /* irq */ ++ s3c_csis->irq = platform_get_irq(pdev, 0); ++ if (request_irq(s3c_csis->irq, s3c_csis_irq, IRQF_DISABLED, \ ++ s3c_csis->name, s3c_csis)) ++ err("request_irq failed\n"); ++ ++ info("Samsung MIPI-CSI2 driver probed successfully\n"); ++ ++ s3c_csis_start(pdev); ++ info("Samsung MIPI-CSI2 operation started\n"); ++ ++ return 0; ++} ++ ++static int s3c_csis_remove(struct platform_device *pdev) ++{ ++ s3c_csis_stop(pdev); ++ kfree(s3c_csis); ++ ++ return 0; ++} ++ ++int s3c_csis_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ return 0; ++} ++ ++int s3c_csis_resume(struct platform_device *dev) ++{ ++ return 0; ++} ++ ++static struct platform_driver s3c_csis_driver = { ++ .probe = s3c_csis_probe, ++ .remove = s3c_csis_remove, ++ .suspend = s3c_csis_suspend, ++ .resume = s3c_csis_resume, ++ .driver = { ++ .name = "s3c-csis", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int s3c_csis_register(void) ++{ ++ platform_driver_register(&s3c_csis_driver); ++ ++ return 0; ++} ++ ++static void s3c_csis_unregister(void) ++{ ++ platform_driver_unregister(&s3c_csis_driver); ++} ++ ++module_init(s3c_csis_register); ++module_exit(s3c_csis_unregister); ++ ++MODULE_AUTHOR("Jinsung, Yang "); ++MODULE_DESCRIPTION("MIPI-CSI2 support for FIMC driver"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimc/s3c_csis.h linux-2.6.28.6/drivers/media/video/samsung/fimc/s3c_csis.h +--- linux-2.6.28/drivers/media/video/samsung/fimc/s3c_csis.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimc/s3c_csis.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,32 @@ ++/* linux/drivers/media/video/samsung/s3c_csis.h ++ * ++ * Header file for Samsung MIPI-CSI2 driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef _S3C_CSIS_H ++#define _S3C_CSIS_H ++ ++#define S3C_CSIS_NAME "s3c-csis" ++#define S3C_CSIS_NR_LANES 2 ++ ++#define info(args...) do { printk(KERN_INFO S3C_CSIS_NAME ": " args); } while (0) ++#define err(args...) do { printk(KERN_ERR S3C_CSIS_NAME ": " args); } while (0) ++ ++ ++struct s3c_csis_info { ++ char name[16]; ++ struct device *dev; ++ struct clk *clock; ++ void __iomem *regs; ++ int irq; ++ int nr_lanes; ++}; ++ ++#endif /* _S3C_CSIS_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimc/s3c_fimc.h linux-2.6.28.6/drivers/media/video/samsung/fimc/s3c_fimc.h +--- linux-2.6.28/drivers/media/video/samsung/fimc/s3c_fimc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimc/s3c_fimc.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,675 @@ ++/* linux/drivers/media/video/samsung/s3c_fimc.h ++ * ++ * Header file for Samsung Camera Interface (FIMC) driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef _S3C_FIMC_H ++#define _S3C_FIMC_H ++ ++#ifdef __KERNEL__ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#endif ++ ++/* ++ * P I X E L F O R M A T G U I D E ++ * ++ * The 'x' means 'DO NOT CARE' ++ * The '*' means 'FIMC SPECIFIC' ++ * For some fimc formats, we couldn't find equivalent format in the V4L2 FOURCC. ++ * ++ * FIMC TYPE PLANES ORDER V4L2_PIX_FMT ++ * --------------------------------------------------------- ++ * RGB565 x x V4L2_PIX_FMT_RGB565 ++ * RGB888 x x V4L2_PIX_FMT_RGB24 ++ * YUV420 2 LSB_CBCR V4L2_PIX_FMT_NV12 ++ * YUV420 2 LSB_CRCB V4L2_PIX_FMT_NV21 ++ * YUV420 2 MSB_CBCR V4L2_PIX_FMT_NV21X* ++ * YUV420 2 MSB_CRCB V4L2_PIX_FMT_NV12X* ++ * YUV420 3 x V4L2_PIX_FMT_YUV420 ++ * YUV422 1 YCBYCR V4L2_PIX_FMT_YUYV ++ * YUV422 1 YCRYCB V4L2_PIX_FMT_YVYU ++ * YUV422 1 CBYCRY V4L2_PIX_FMT_UYVY ++ * YUV422 1 CRYCBY V4L2_PIX_FMT_VYUY* ++ * YUV422 2 LSB_CBCR V4L2_PIX_FMT_NV16* ++ * YUV422 2 LSB_CRCB V4L2_PIX_FMT_NV61* ++ * YUV422 2 MSB_CBCR V4L2_PIX_FMT_NV16X* ++ * YUV422 2 MSB_CRCB V4L2_PIX_FMT_NV61X* ++ * YUV422 3 x V4L2_PIX_FMT_YUV422P ++ * ++*/ ++ ++/* ++ * C O M M O N D E F I N I T I O N S ++ * ++*/ ++#define S3C_FIMC_NAME "s3c-fimc" ++ ++#define info(args...) do { printk(KERN_INFO S3C_FIMC_NAME ": " args); } while (0) ++#define err(args...) do { printk(KERN_ERR S3C_FIMC_NAME ": " args); } while (0) ++ ++#define S3C_FIMC_FRAME_SKIP 0 ++#define S3C_FIMC_FRAME_TAKE 1 ++ ++#define S3C_FIMC_MAX_CTRLS 3 ++#define S3C_FIMC_MAX_FRAMES 4 ++ ++/* including 1 more for test pattern */ ++#define S3C_FIMC_MAX_CAMS 4 ++#define S3C_FIMC_TPID (S3C_FIMC_MAX_CAMS - 1) ++ ++#define S3C_FIMC_ZOOM_PIXELS 32 ++ ++#define S3C_FIMC_CROP_DEF_WIDTH 352 ++#define S3C_FIMC_CROP_DEF_HEIGHT 272 ++ ++/* S flag: global status flags */ ++#define S3C_FIMC_FLAG_RUNNING 0x0001 ++#define S3C_FIMC_FLAG_STOP 0x0002 ++#define S3C_FIMC_FLAG_HANDLE_IRQ 0x0004 ++#define S3C_FIMC_STA_MASK 0x000f ++ ++/* U flag: use case flags */ ++#define S3C_FIMC_FLAG_PREVIEW 0x0010 ++#define S3C_FIMC_FLAG_CAPTURE 0x0020 ++#define S3C_FIMC_USE_MASK 0x00f0 ++ ++/* I flag: IRQ flags */ ++#define S3C_FIMC_FLAG_IRQ_NORMAL 0x0100 ++#define S3C_FIMC_FLAG_IRQ_X 0x0200 ++#define S3C_FIMC_FLAG_IRQ_Y 0x0400 ++#define S3C_FIMC_FLAG_IRQ_LAST 0x0800 ++#define S3C_FIMC_IRQ_MASK 0x0f00 ++ ++#define UNMASK_STATUS(x) (x->flag &= ~S3C_FIMC_STA_MASK) ++#define UNMASK_USAGE(x) (x->flag &= ~S3C_FIMC_USE_MASK) ++#define UNMASK_IRQ(x) (x->flag &= ~S3C_FIMC_IRQ_MASK) ++ ++#define FSET_RUNNING(x) UNMASK_STATUS(x); (x->flag |= S3C_FIMC_FLAG_RUNNING) ++#define FSET_STOP(x) UNMASK_STATUS(x); (x->flag |= S3C_FIMC_FLAG_STOP) ++#define FSET_HANDLE_IRQ(x) UNMASK_STATUS(x); (x->flag |= S3C_FIMC_FLAG_HANDLE_IRQ) ++ ++#define FSET_PREVIEW(x) UNMASK_USAGE(x); (x->flag |= S3C_FIMC_FLAG_PREVIEW) ++#define FSET_CAPTURE(x) UNMASK_USAGE(x); (x->flag |= S3C_FIMC_FLAG_CAPTURE) ++ ++#define FSET_IRQ_NORMAL(x) UNMASK_IRQ(x); (x->flag |= S3C_FIMC_FLAG_IRQ_NORMAL) ++#define FSET_IRQ_X(x) UNMASK_IRQ(x); (x->flag |= S3C_FIMC_FLAG_IRQ_X) ++#define FSET_IRQ_Y(x) UNMASK_IRQ(x); (x->flag |= S3C_FIMC_FLAG_IRQ_Y) ++#define FSET_IRQ_LAST(x) UNMASK_IRQ(x); (x->flag |= S3C_FIMC_FLAG_IRQ_LAST) ++ ++#define IS_RUNNING(x) (x->flag & S3C_FIMC_FLAG_RUNNING) ++#define IS_IRQ_HANDLING(x) (x->flag & S3C_FIMC_FLAG_HANDLE_IRQ) ++ ++#define IS_PREVIEW(x) (x->flag & S3C_FIMC_FLAG_PREVIEW) ++#define IS_CAPTURE(x) (x->flag & S3C_FIMC_FLAG_CAPTURE) ++ ++#define IS_IRQ_NORMAL(x) (x->flag & S3C_FIMC_FLAG_IRQ_NORMAL) ++#define IS_IRQ_X(x) (x->flag & S3C_FIMC_FLAG_IRQ_X) ++#define IS_IRQ_Y(x) (x->flag & S3C_FIMC_FLAG_IRQ_Y) ++#define IS_IRQ_LAST(x) (x->flag & S3C_FIMC_FLAG_IRQ_LAST) ++ ++#define PAT_CB(x) ((x >> 8) & 0xff) ++#define PAT_CR(x) (x & 0xff) ++ ++ ++/* ++ * E N U M E R A T I O N S ++ * ++*/ ++enum s3c_fimc_cam_t { ++ CAM_TYPE_ITU = 0, ++ CAM_TYPE_MIPI = 1, ++}; ++ ++enum s3c_fimc_cam_mode_t { ++ ITU_601_YCBCR422_8BIT = (1 << 31), ++ ITU_656_YCBCR422_8BIT = (0 << 31), ++ ITU_601_YCBCR422_16BIT = (1 << 29), ++ MIPI_CSI_YCBCR422_8BIT = 0x1e, ++ MIPI_CSI_RAW8 = 0x2a, ++ MIPI_CSI_RAW10 = 0x2b, ++ MIPI_CSI_RAW12 = 0x2c, ++}; ++ ++enum s3c_fimc_order422_cam_t { ++ CAM_ORDER422_8BIT_YCBYCR = (0 << 14), ++ CAM_ORDER422_8BIT_YCRYCB = (1 << 14), ++ CAM_ORDER422_8BIT_CBYCRY = (2 << 14), ++ CAM_ORDER422_8BIT_CRYCBY = (3 << 14), ++ CAM_ORDER422_16BIT_Y4CBCRCBCR = (0 << 14), ++ CAM_ORDER422_16BIT_Y4CRCBCRCB = (1 << 14), ++}; ++ ++enum s3c_fimc_order422_in_t { ++ IN_ORDER422_CRYCBY = (0 << 4), ++ IN_ORDER422_YCRYCB = (1 << 4), ++ IN_ORDER422_CBYCRY = (2 << 4), ++ IN_ORDER422_YCBYCR = (3 << 4), ++}; ++ ++enum s3c_fimc_order422_out_t { ++ OUT_ORDER422_YCBYCR = (0 << 0), ++ OUT_ORDER422_YCRYCB = (1 << 0), ++ OUT_ORDER422_CBYCRY = (2 << 0), ++ OUT_ORDER422_CRYCBY = (3 << 0), ++}; ++ ++enum s3c_fimc_2plane_order_t { ++ LSB_CBCR = 0, ++ LSB_CRCB = 1, ++ MSB_CRCB = 2, ++ MSB_CBCR = 3, ++}; ++ ++enum s3c_fimc_itu_cam_ch_t { ++ ITU_CAM_A = 1, ++ ITU_CAM_B = 0, ++}; ++ ++enum s3c_fimc_scan_t { ++ SCAN_TYPE_PROGRESSIVE = 0, ++ SCAN_TYPE_INTERLACE = 1, ++}; ++ ++enum s3c_fimc_format_t { ++ FORMAT_RGB565, ++ FORMAT_RGB666, ++ FORMAT_RGB888, ++ FORMAT_YCBCR420, ++ FORMAT_YCBCR422, ++}; ++ ++enum s3c_fimc_flip_t { ++ FLIP_ORIGINAL = 0, ++ FLIP_X_AXIS = 1, ++ FLIP_Y_AXIS = 2, ++ FLIP_XY_AXIS = 3, ++}; ++ ++enum s3c_fimc_path_in_t { ++ PATH_IN_ITU_CAMERA, ++ PATH_IN_MIPI_CAMERA, ++ PATH_IN_DMA, ++}; ++ ++enum s3c_fimc_path_out_t { ++ PATH_OUT_DMA, ++ PATH_OUT_LCDFIFO, ++}; ++ ++enum s3c_fimc_effect_t { ++ EFFECT_ORIGINAL = (0 << 26), ++ EFFECT_ARBITRARY = (1 << 26), ++ EFFECT_NEGATIVE = (2 << 26), ++ EFFECT_ARTFREEZE = (3 << 26), ++ EFFECT_EMBOSSING = (4 << 26), ++ EFFECT_SILHOUETTE = (5 << 26), ++}; ++ ++enum s3c_fimc_wb_t { ++ WB_AUTO = 0, ++ WB_INDOOR_3001 = 1, ++ WB_OUTDOOR_5100 = 2, ++ WB_INDOOR_2000 = 3, ++ WB_HALT = 4, ++ WB_CLOUDY = 5, ++ WB_SUNNY = 6, ++}; ++ ++enum s3c_fimc_i2c_cmd_t { ++ I2C_CAM_INIT, ++ I2C_CAM_RESOLUTION, ++ I2C_CAM_WB, ++}; ++ ++enum s3c_fimc_cam_res_t { ++ CAM_RES_DEFAULT, ++ CAM_RES_QSVGA, ++ CAM_RES_VGA, ++ CAM_RES_SVGA, ++ CAM_RES_SXGA, ++ CAM_RES_UXGA, ++ CAM_RES_MAX, ++}; ++ ++ ++/* ++ * F I M C S T R U C T U R E S ++ * ++*/ ++ ++/* ++ * struct s3c_fimc_frame_addr ++ * @phys_rgb: physical start address of rgb buffer ++ * @phys_y: physical start address of y buffer ++ * @phys_cb: physical start address of u buffer ++ * @phys_cr: physical start address of v buffer ++ * @virt_y: virtual start address of y buffer ++ * @virt_rgb: virtual start address of rgb buffer ++ * @virt_cb: virtual start address of u buffer ++ * @virt_cr: virtual start address of v buffer ++*/ ++struct s3c_fimc_frame_addr { ++ union { ++ dma_addr_t phys_rgb; ++ dma_addr_t phys_y; ++ }; ++ ++ dma_addr_t phys_cb; ++ dma_addr_t phys_cr; ++ ++ union { ++ u8 *virt_rgb; ++ u8 *virt_y; ++ }; ++ ++ u8 *virt_cb; ++ u8 *virt_cr; ++}; ++ ++/* ++ * struct s3c_fimc_window_offset ++ * @h1: left side offset of source ++ * @h2: right side offset of source ++ * @v1: upper side offset of source ++ * @v2: lower side offset of source ++*/ ++struct s3c_fimc_window_offset { ++ int h1; ++ int h2; ++ int v1; ++ int v2; ++}; ++ ++/* ++ * struct s3c_fimc_dma_offset ++ * @y_h: y value horizontal offset ++ * @y_v: y value vertical offset ++ * @cb_h: cb value horizontal offset ++ * @cb_v: cb value vertical offset ++ * @cr_h: cr value horizontal offset ++ * @cr_v: cr value vertical offset ++ * ++*/ ++struct s3c_fimc_dma_offset { ++ int y_h; ++ int y_v; ++ int cb_h; ++ int cb_v; ++ int cr_h; ++ int cr_v; ++}; ++ ++/* ++ * struct s3c_fimc_polarity ++ * @pclk: 1 if PCLK polarity is inverse ++ * @vsync: 1 if VSYNC polarity is inverse ++ * @href: 1 if HREF polarity is inverse ++ * @hsync: 1 if HSYNC polarity is inverse ++*/ ++struct s3c_fimc_polarity { ++ u32 pclk; ++ u32 vsync; ++ u32 href; ++ u32 hsync; ++}; ++ ++/* ++ * struct s3c_fimc_effect ++ * @type: effect type ++ * @pat_cb: cr value when type == arbitrary ++ * @pat_cR: cr value when type == arbitrary ++ * ++*/ ++struct s3c_fimc_effect { ++ enum s3c_fimc_effect_t type; ++ u8 pat_cb; ++ u8 pat_cr; ++}; ++ ++/* ++ * struct s3c_fimc_scaler ++ * @bypass: 1 when pass the original source with no scaling ++ * @hfactor: horizontal shift factor to scale up/down ++ * @vfactor: vertical shift factor to scale up/down ++ * @pre_hratio: horizontal ratio for pre-scaler ++ * @pre_vratio: vertical ratio for pre-scaler ++ * @pre_dst_width: destination width for pre-scaler ++ * @pre_dst_height: destination height for pre-scaler ++ * @scaleup_h: 1 if we have to scale up for the horizontal ++ * @scaleup_v: 1 if we have to scale up for the vertical ++ * @main_hratio: horizontal ratio for main scaler ++ * @main_vratio: vertical ratio for main scaler ++ * @real_width: src_width - offset ++ * @real_height: src_height - offset ++ * @line_length: line buffer length from platform_data ++ * @zoom_depth: current zoom depth (0 = original) ++*/ ++struct s3c_fimc_scaler { ++ u32 bypass; ++ u32 hfactor; ++ u32 vfactor; ++ u32 pre_hratio; ++ u32 pre_vratio; ++ u32 pre_dst_width; ++ u32 pre_dst_height; ++ u32 scaleup_h; ++ u32 scaleup_v; ++ u32 main_hratio; ++ u32 main_vratio; ++ u32 real_width; ++ u32 real_height; ++ u32 line_length; ++ u32 zoom_depth; ++}; ++ ++/* ++ * struct s3c_fimc_camera: abstraction for input camera ++ * @id: cam id (0-2) ++ * @type: type of camera (ITU or MIPI) ++ * @mode: mode of input source ++ * @order422: YCBCR422 order ++ * @clockrate: camera clockrate ++ * @width: source width ++ * @height: source height ++ * @offset: offset information ++ * @polarity polarity information ++ * @reset_type: reset type (high or low) ++ * @reset_delay: delay time in microseconds (udelay) ++ * @client: i2c client ++ * @initialized: whether already initialized ++*/ ++struct s3c_fimc_camera { ++ int id; ++ enum s3c_fimc_cam_t type; ++ enum s3c_fimc_cam_mode_t mode; ++ enum s3c_fimc_order422_cam_t order422; ++ u32 clockrate; ++ int width; ++ int height; ++ struct s3c_fimc_window_offset offset; ++ struct s3c_fimc_polarity polarity; ++ struct i2c_client *client; ++ int initialized; ++}; ++ ++/* ++ * struct s3c_fimc_in_frame: abstraction for frame data ++ * @addr: address information of frame data ++ * @width: width ++ * @height: height ++ * @offset: dma offset ++ * @format: pixel format ++ * @planes: YCBCR planes (1, 2 or 3) ++ * @order_1p 1plane YCBCR order ++ * @order_2p: 2plane YCBCR order ++ * @flip: flip mode ++*/ ++struct s3c_fimc_in_frame { ++ u32 buf_size; ++ struct s3c_fimc_frame_addr addr; ++ int width; ++ int height; ++ struct s3c_fimc_dma_offset offset; ++ enum s3c_fimc_format_t format; ++ int planes; ++ enum s3c_fimc_order422_in_t order_1p; ++ enum s3c_fimc_2plane_order_t order_2p; ++ enum s3c_fimc_flip_t flip; ++}; ++ ++/* ++ * struct s3c_fimc_out_frame: abstraction for frame data ++ * @cfn: current frame number ++ * @buf_size: 1 buffer size ++ * @addr[]: address information of frames ++ * @nr_frams: how many output frames used ++ * @skip_frames: current streamed frames (for capture) ++ * @width: width ++ * @height: height ++ * @offset: offset for output dma ++ * @format: pixel format ++ * @planes: YCBCR planes (1, 2 or 3) ++ * @order_1p 1plane YCBCR order ++ * @order_2p: 2plane YCBCR order ++ * @scan: output scan method (progressive, interlace) ++ * @flip: flip mode ++ * @effect: output effect ++*/ ++struct s3c_fimc_out_frame { ++ int cfn; ++ u32 buf_size; ++ struct s3c_fimc_frame_addr addr[S3C_FIMC_MAX_FRAMES]; ++ int nr_frames; ++ int skip_frames; ++ int width; ++ int height; ++ struct s3c_fimc_dma_offset offset; ++ enum s3c_fimc_format_t format; ++ int planes; ++ enum s3c_fimc_order422_out_t order_1p; ++ enum s3c_fimc_2plane_order_t order_2p; ++ enum s3c_fimc_scan_t scan; ++ enum s3c_fimc_flip_t flip; ++ struct s3c_fimc_effect effect; ++}; ++ ++/* ++ * struct s3c_fimc_v4l2 ++*/ ++struct s3c_fimc_v4l2 { ++ struct v4l2_fmtdesc *fmtdesc; ++ struct v4l2_framebuffer frmbuf; ++ struct v4l2_input *input; ++ struct v4l2_output *output; ++ struct v4l2_rect crop_bounds; ++ struct v4l2_rect crop_defrect; ++ struct v4l2_rect crop_current; ++}; ++ ++/* ++ * struct s3c_fimc_control: abstraction for FIMC controller ++ * @id: id number (= minor number) ++ * @name: name for video_device ++ * @flag: status, usage, irq flag (S, U, I flag) ++ * @lock: mutex lock ++ * @waitq: waitqueue ++ * @pdata: platform data ++ * @clock: fimc clock ++ * @regs: virtual address of SFR ++ * @in_use: 1 when resource is occupied ++ * @irq: irq number ++ * @vd: video_device ++ * @v4l2: v4l2 info ++ * @scaler: scaler related information ++ * @in_type: type of input ++ * @in_cam: camera structure pointer if input is camera else null ++ * @in_frame: frame structure pointer if input is dma else null ++ * @out_type: type of output ++ * @out_frame: frame structure pointer if output is dma ++ * @rot90: 1 if clockwise 90 degree for output ++ * ++ * @open_lcdfifo: function pointer to open lcd fifo path (display driver) ++ * @close_lcdfifo: function pointer to close fifo path (display driver) ++*/ ++struct s3c_fimc_control { ++ /* general */ ++ int id; ++ char name[16]; ++ u32 flag; ++ struct mutex lock; ++ wait_queue_head_t waitq; ++ struct device *dev; ++ struct clk *clock; ++ void __iomem *regs; ++ atomic_t in_use; ++ int irq; ++ struct video_device *vd; ++ struct s3c_fimc_v4l2 v4l2; ++ struct s3c_fimc_scaler scaler; ++ ++ /* input */ ++ enum s3c_fimc_path_in_t in_type; ++ struct s3c_fimc_camera *in_cam; ++ struct s3c_fimc_in_frame in_frame; ++ ++ /* output */ ++ enum s3c_fimc_path_out_t out_type; ++ struct s3c_fimc_out_frame out_frame; ++ int rot90; ++ ++ /* functions */ ++ void (*open_lcdfifo)(int win, int in_yuv, int sel); ++ void (*close_lcdfifo)(int win); ++}; ++ ++/* ++ * struct s3c_fimc_config ++*/ ++struct s3c_fimc_config { ++ struct s3c_fimc_control ctrl[S3C_FIMC_MAX_CTRLS]; ++ struct s3c_fimc_camera *camera[S3C_FIMC_MAX_CAMS]; ++ struct clk *cam_clock; ++ dma_addr_t dma_start; ++ dma_addr_t dma_current; ++ u32 dma_total; ++}; ++ ++ ++/* ++ * V 4 L 2 F I M C E X T E N S I O N S ++ * ++*/ ++#define V4L2_INPUT_TYPE_MEMORY 10 ++#define V4L2_OUTPUT_TYPE_MEMORY 20 ++#define V4L2_OUTPUT_TYPE_LCDFIFO 21 ++ ++#define FORMAT_FLAGS_PACKED 1 ++#define FORMAT_FLAGS_PLANAR 2 ++ ++#define V4L2_FMT_IN 0 ++#define V4L2_FMT_OUT 1 ++ ++#define TPATTERN_COLORBAR 1 ++#define TPATTERN_HORIZONTAL 2 ++#define TPATTERN_VERTICAL 3 ++ ++/* FOURCC for FIMC specific */ ++#define V4L2_PIX_FMT_NV12X v4l2_fourcc('N', '1', '2', 'X') ++#define V4L2_PIX_FMT_NV21X v4l2_fourcc('N', '2', '1', 'X') ++#define V4L2_PIX_FMT_VYUY v4l2_fourcc('V', 'Y', 'U', 'Y') ++#define V4L2_PIX_FMT_NV16 v4l2_fourcc('N', 'V', '1', '6') ++#define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') ++#define V4L2_PIX_FMT_NV16X v4l2_fourcc('N', '1', '6', 'X') ++#define V4L2_PIX_FMT_NV61X v4l2_fourcc('N', '6', '1', 'X') ++ ++/* CID extensions */ ++#define V4L2_CID_ACTIVE_CAMERA (V4L2_CID_PRIVATE_BASE + 0) ++#define V4L2_CID_NR_FRAMES (V4L2_CID_PRIVATE_BASE + 1) ++#define V4L2_CID_RESET (V4L2_CID_PRIVATE_BASE + 2) ++#define V4L2_CID_TEST_PATTERN (V4L2_CID_PRIVATE_BASE + 3) ++#define V4L2_CID_SCALER_BYPASS (V4L2_CID_PRIVATE_BASE + 4) ++#define V4L2_CID_JPEG_INPUT (V4L2_CID_PRIVATE_BASE + 5) ++#define V4L2_CID_OUTPUT_ADDR (V4L2_CID_PRIVATE_BASE + 10) ++#define V4L2_CID_INPUT_ADDR (V4L2_CID_PRIVATE_BASE + 20) ++#define V4L2_CID_INPUT_ADDR_RGB (V4L2_CID_PRIVATE_BASE + 21) ++#define V4L2_CID_INPUT_ADDR_Y (V4L2_CID_PRIVATE_BASE + 22) ++#define V4L2_CID_INPUT_ADDR_CB (V4L2_CID_PRIVATE_BASE + 23) ++#define V4L2_CID_INPUT_ADDR_CBCR (V4L2_CID_PRIVATE_BASE + 24) ++#define V4L2_CID_INPUT_ADDR_CR (V4L2_CID_PRIVATE_BASE + 25) ++#define V4L2_CID_EFFECT_ORIGINAL (V4L2_CID_PRIVATE_BASE + 30) ++#define V4L2_CID_EFFECT_ARBITRARY (V4L2_CID_PRIVATE_BASE + 31) ++#define V4L2_CID_EFFECT_NEGATIVE (V4L2_CID_PRIVATE_BASE + 33) ++#define V4L2_CID_EFFECT_ARTFREEZE (V4L2_CID_PRIVATE_BASE + 34) ++#define V4L2_CID_EFFECT_EMBOSSING (V4L2_CID_PRIVATE_BASE + 35) ++#define V4L2_CID_EFFECT_SILHOUETTE (V4L2_CID_PRIVATE_BASE + 36) ++#define V4L2_CID_ROTATE_ORIGINAL (V4L2_CID_PRIVATE_BASE + 40) ++#define V4L2_CID_ROTATE_90 (V4L2_CID_PRIVATE_BASE + 41) ++#define V4L2_CID_ROTATE_180 (V4L2_CID_PRIVATE_BASE + 42) ++#define V4L2_CID_ROTATE_270 (V4L2_CID_PRIVATE_BASE + 43) ++#define V4L2_CID_ROTATE_90_HFLIP (V4L2_CID_PRIVATE_BASE + 44) ++#define V4L2_CID_ROTATE_90_VFLIP (V4L2_CID_PRIVATE_BASE + 45) ++#define V4L2_CID_ZOOM_IN (V4L2_CID_PRIVATE_BASE + 51) ++#define V4L2_CID_ZOOM_OUT (V4L2_CID_PRIVATE_BASE + 52) ++ ++ ++/* ++ * E X T E R N S ++ * ++*/ ++extern struct s3c_fimc_config s3c_fimc; ++extern const struct v4l2_ioctl_ops s3c_fimc_v4l2_ops; ++extern struct video_device s3c_fimc_video_device[]; ++ ++extern struct s3c_platform_fimc *to_fimc_plat(struct device *dev); ++extern u8 s3c_fimc_i2c_read(struct i2c_client *client, u8 subaddr); ++extern int s3c_fimc_i2c_write(struct i2c_client *client, u8 subaddr, u8 val); ++extern void s3c_fimc_i2c_command(struct s3c_fimc_control *ctrl, u32 cmd, int arg); ++extern void s3c_fimc_register_camera(struct s3c_fimc_camera *cam); ++extern void s3c_fimc_set_active_camera(struct s3c_fimc_control *ctrl, int id); ++extern void s3c_fimc_init_camera(struct s3c_fimc_control *ctrl); ++extern int s3c_fimc_alloc_input_memory(struct s3c_fimc_in_frame *info, dma_addr_t addr); ++extern int s3c_fimc_alloc_output_memory(struct s3c_fimc_out_frame *info); ++extern int s3c_fimc_alloc_y_memory(struct s3c_fimc_in_frame *info, dma_addr_t addr); ++extern int s3c_fimc_alloc_cb_memory(struct s3c_fimc_in_frame *info, dma_addr_t addr); ++extern int s3c_fimc_alloc_cr_memory(struct s3c_fimc_in_frame *info, dma_addr_t addr); ++extern void s3c_fimc_free_output_memory(struct s3c_fimc_out_frame *info); ++extern int s3c_fimc_set_input_frame(struct s3c_fimc_control *ctrl, struct v4l2_pix_format *fmt); ++extern int s3c_fimc_set_output_frame(struct s3c_fimc_control *ctrl, struct v4l2_pix_format *fmt); ++extern int s3c_fimc_frame_handler(struct s3c_fimc_control *ctrl); ++extern u8 *s3c_fimc_get_current_frame(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_set_nr_frames(struct s3c_fimc_control *ctrl, int nr); ++extern int s3c_fimc_set_scaler_info(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_start_dma(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_stop_dma(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_restart_dma(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_change_resolution(struct s3c_fimc_control *ctrl, enum s3c_fimc_cam_res_t res); ++extern int s3c_fimc_check_zoom(struct s3c_fimc_control *ctrl, int type); ++extern void s3c_fimc_clear_irq(struct s3c_fimc_control *ctrl); ++extern int s3c_fimc_check_fifo(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_select_camera(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_set_test_pattern(struct s3c_fimc_control *ctrl, int type); ++extern void s3c_fimc_set_source_format(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_set_window_offset(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_reset(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_set_polarity(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_set_target_format(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_set_output_dma(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_enable_lastirq(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_disable_lastirq(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_set_prescaler(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_set_scaler(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_start_scaler(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_stop_scaler(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_enable_capture(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_disable_capture(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_set_effect(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_set_input_dma(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_start_input_dma(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_stop_input_dma(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_set_input_path(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_set_output_path(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_set_input_address(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_set_output_address(struct s3c_fimc_control *ctrl); ++extern int s3c_fimc_get_frame_count(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_wait_frame_end(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_change_effect(struct s3c_fimc_control *ctrl); ++extern void s3c_fimc_change_rotate(struct s3c_fimc_control *ctrl); ++ ++/* FIMD externs */ ++extern void s3cfb_enable_local(int win, int in_yuv, int sel); ++extern void s3cfb_enable_dma(int win); ++ ++#endif /* _S3C_FIMC_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimc/s3c_fimc3x_regs.c linux-2.6.28.6/drivers/media/video/samsung/fimc/s3c_fimc3x_regs.c +--- linux-2.6.28/drivers/media/video/samsung/fimc/s3c_fimc3x_regs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimc/s3c_fimc3x_regs.c 2009-10-23 13:12:44.000000000 +0200 +@@ -0,0 +1,1196 @@ ++/* linux/drivers/media/video/samsung/s3c_fimc4x_regs.c ++ * ++ * Register interface file for Samsung Camera Interface (FIMC) driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "s3c_fimc.h" ++ ++void s3c_fimc_clear_irq(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CIGCTRL); ++ ++ if (ctrl->id == 1) ++ cfg |= S3C_CIGCTRL_IRQ_CLR_P; ++ else ++ cfg |= S3C_CIGCTRL_IRQ_CLR_C; ++ ++ writel(cfg, ctrl->regs + S3C_CIGCTRL); ++} ++ ++static int s3c_fimc_check_fifo_co(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg, status, flag; ++ ++ status = readl(ctrl->regs + S3C_CICOSTATUS); ++ flag = S3C_CICOSTATUS_OVFIY | S3C_CICOSTATUS_OVFICB | S3C_CICOSTATUS_OVFICR; ++ ++ if (status & flag) { ++ cfg = readl(ctrl->regs + S3C_CIWDOFST); ++ cfg |= (S3C_CIWDOFST_CLROVCOFIY | S3C_CIWDOFST_CLROVCOFICB | \ ++ S3C_CIWDOFST_CLROVCOFICR); ++ writel(cfg, ctrl->regs + S3C_CIWDOFST); ++ ++ cfg = readl(ctrl->regs + S3C_CIWDOFST); ++ cfg &= ~(S3C_CIWDOFST_CLROVCOFIY | S3C_CIWDOFST_CLROVCOFICB | \ ++ S3C_CIWDOFST_CLROVCOFICR); ++ writel(cfg, ctrl->regs + S3C_CIWDOFST); ++ } ++ ++ return 0; ++} ++ ++static int s3c_fimc_check_fifo_pr(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg, status, flag; ++ ++ status = readl(ctrl->regs + S3C_CIPRSTATUS); ++ flag = S3C_CIPRSTATUS_OVFIY | S3C_CIPRSTATUS_OVFICB | S3C_CIPRSTATUS_OVFICR; ++ ++ if (status & flag) { ++ cfg = readl(ctrl->regs + S3C_CIWDOFST); ++ cfg |= (S3C_CIWDOFST_CLROVPRFIY | S3C_CIWDOFST_CLROVPRFICB | \ ++ S3C_CIWDOFST_CLROVPRFICR); ++ writel(cfg, ctrl->regs + S3C_CIWDOFST); ++ ++ cfg = readl(ctrl->regs + S3C_CIWDOFST); ++ cfg &= ~(S3C_CIWDOFST_CLROVPRFIY | S3C_CIWDOFST_CLROVPRFICB | \ ++ S3C_CIWDOFST_CLROVPRFICR); ++ writel(cfg, ctrl->regs + S3C_CIWDOFST); ++ } ++ ++ return 0; ++} ++ ++int s3c_fimc_check_fifo(struct s3c_fimc_control *ctrl) ++{ ++ if (ctrl->id == 1) ++ return s3c_fimc_check_fifo_pr(ctrl); ++ else ++ return s3c_fimc_check_fifo_co(ctrl); ++} ++ ++void s3c_fimc_select_camera(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CIGCTRL); ++ ++ cfg &= ~S3C_CIGCTRL_TESTPATTERN_MASK; ++ writel(cfg, ctrl->regs + S3C_CIGCTRL); ++} ++ ++void s3c_fimc_set_test_pattern(struct s3c_fimc_control *ctrl, int type) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CIGCTRL); ++ ++ cfg &= ~S3C_CIGCTRL_TESTPATTERN_MASK; ++ cfg |= type << S3C_CIGCTRL_TESTPATTERN_SHIFT; ++ ++ writel(cfg, ctrl->regs + S3C_CIGCTRL); ++} ++ ++void s3c_fimc_set_source_format(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_camera *cam = ctrl->in_cam; ++ u32 cfg = 0; ++ ++ cfg |= (cam->mode | cam->order422); ++ ++ cfg |= S3C_CISRCFMT_SOURCEHSIZE(cam->width); ++ cfg |= S3C_CISRCFMT_SOURCEVSIZE(cam->height); ++ ++ writel(cfg, ctrl->regs + S3C_CISRCFMT); ++ ++} ++ ++void s3c_fimc_set_window_offset(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_window_offset *offset = &ctrl->in_cam->offset; ++ u32 cfg; ++ ++ cfg = readl(ctrl->regs + S3C_CIWDOFST); ++ cfg &= ~(S3C_CIWDOFST_WINHOROFST_MASK | S3C_CIWDOFST_WINVEROFST_MASK); ++ cfg |= S3C_CIWDOFST_WINHOROFST(offset->h1); ++ cfg |= S3C_CIWDOFST_WINVEROFST(offset->v1); ++ cfg |= S3C_CIWDOFST_WINOFSEN; ++ writel(cfg, ctrl->regs + S3C_CIWDOFST); ++ ++ cfg = 0; ++ cfg |= S3C_CIWDOFST2_WINHOROFST2(offset->h2); ++ cfg |= S3C_CIWDOFST2_WINVEROFST2(offset->v2); ++ writel(cfg, ctrl->regs + S3C_CIWDOFST2); ++} ++ ++static void s3c_fimc_reset_cfg(struct s3c_fimc_control *ctrl) ++{ ++ int i; ++ u32 cfg[][2] = { ++ { 0x018, 0x00000000 }, { 0x01c, 0x00000000 }, ++ { 0x020, 0x00000000 }, { 0x024, 0x00000000 }, ++ { 0x028, 0x00000000 }, { 0x02c, 0x00000000 }, ++ { 0x030, 0x00000000 }, { 0x034, 0x00000000 }, ++ { 0x038, 0x00000000 }, { 0x03c, 0x00000000 }, ++ { 0x040, 0x00000000 }, { 0x044, 0x00000000 }, ++ { 0x048, 0x00000000 }, { 0x04c, 0x00000000 }, ++ { 0x050, 0x00000000 }, { 0x054, 0x00000000 }, ++ { 0x058, 0x18000000 }, { 0x05c, 0x00000000 }, ++ { 0x068, 0x00000000 }, { 0x06c, 0x00000000 }, ++ { 0x070, 0x00000000 }, { 0x074, 0x00000000 }, ++ { 0x078, 0x18000000 }, { 0x07c, 0x00000000 }, ++ { 0x080, 0x00000000 }, { 0x084, 0x00000000 }, ++ { 0x088, 0x00000000 }, { 0x08c, 0x00000000 }, ++ { 0x090, 0x00000000 }, { 0x094, 0x00000000 }, ++ { 0x098, 0x18000000 }, { 0x0a0, 0x00000000 }, ++ { 0x0a4, 0x00000000 }, { 0x0a8, 0x00000000 }, ++ { 0x0ac, 0x18000000 }, { 0x0b0, 0x00000000 }, ++ { 0x0c0, 0x00000000 }, { 0x0c4, 0xffffffff }, ++ { 0x0d0, 0x00100080 }, { 0x0d4, 0x00000000 }, ++ { 0x0d8, 0x00000000 }, { 0x0dc, 0x00000000 }, ++ { 0x0e0, 0x00000000 }, { 0x0e4, 0x00000000 }, ++ { 0x0e8, 0x00000000 }, { 0x0ec, 0x00000000 }, ++ { 0x0f0, 0x00000000 }, { 0x0f4, 0x00000000 }, ++ { 0x0f8, 0x00000000 }, { 0x0fc, 0x00000000 }, ++ { 0x100, 0x00000000 }, { 0x104, 0x00000000 }, ++ { 0x108, 0x00000000 }, { 0x10c, 0x00000000 }, ++ { 0x110, 0x00000000 }, { 0x114, 0x00000000 }, ++ { 0x118, 0x00000000 }, { 0x11c, 0x00000000 }, ++ { 0x120, 0x00000000 }, { 0x124, 0x00000000 }, ++ { 0x128, 0x00000000 }, { 0x12c, 0x00000000 }, ++ { 0x130, 0x00000000 }, { 0x134, 0x00000000 }, ++ { 0x138, 0x00000000 }, { 0x13c, 0x00000000 }, ++ { 0x140, 0x00000000 }, ++ }; ++ ++ for (i = 0; i < sizeof(cfg) / 8; i++) ++ writel(cfg[i][1], ctrl->regs + cfg[i][0]); ++} ++ ++void s3c_fimc_reset(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg; ++ ++ /* ++ * we have to write 1 to the CISRCFMT[31] before ++ * getting started the sw reset ++ * ++ */ ++ cfg = readl(ctrl->regs + S3C_CISRCFMT); ++ cfg |= S3C_CISRCFMT_ITU601_8BIT; ++ writel(cfg, ctrl->regs + S3C_CISRCFMT); ++ ++ /* s/w reset */ ++ cfg = readl(ctrl->regs + S3C_CIGCTRL); ++ cfg |= (S3C_CIGCTRL_SWRST | S3C_CIGCTRL_IRQ_LEVEL); ++ writel(cfg, ctrl->regs + S3C_CIGCTRL); ++ mdelay(1); ++ ++ cfg = readl(ctrl->regs + S3C_CIGCTRL); ++ cfg &= ~S3C_CIGCTRL_SWRST; ++ writel(cfg, ctrl->regs + S3C_CIGCTRL); ++ ++ /* in case of ITU656, CISRCFMT[31] should be 0 */ ++ if (ctrl->in_cam && ctrl->in_cam->mode == ITU_656_YCBCR422_8BIT) { ++ cfg = readl(ctrl->regs + S3C_CISRCFMT); ++ cfg &= ~S3C_CISRCFMT_ITU601_8BIT; ++ writel(cfg, ctrl->regs + S3C_CISRCFMT); ++ } ++ ++ s3c_fimc_reset_cfg(ctrl); ++} ++ ++void s3c_fimc_reset_camera(void) ++{ ++ void __iomem *regs = ioremap(S3C64XX_PA_FIMC, SZ_4K); ++ u32 cfg; ++ ++#if (CONFIG_VIDEO_FIMC_CAM_RESET == 1) ++ printk("[CAM]RESET CAM.");//FIXME!can't be delete!!! ++ cfg = readl(regs + S3C_CIGCTRL); ++ cfg |= S3C_CIGCTRL_CAMRST; ++ writel(cfg, regs + S3C_CIGCTRL); ++ //udelay(200); ++ mdelay(200); ++ ++ cfg = readl(regs + S3C_CIGCTRL); ++ cfg &= ~S3C_CIGCTRL_CAMRST; ++ writel(cfg, regs + S3C_CIGCTRL); ++ udelay(2000); ++#else ++ cfg = readl(regs + S3C_CIGCTRL); ++ cfg &= ~S3C_CIGCTRL_CAMRST; ++ writel(cfg, regs + S3C_CIGCTRL); ++ udelay(200); ++ ++ cfg = readl(regs + S3C_CIGCTRL); ++ cfg |= S3C_CIGCTRL_CAMRST; ++ writel(cfg, regs + S3C_CIGCTRL); ++ udelay(2000); ++#endif ++ ++ iounmap(regs); ++} ++ ++void s3c_fimc_set_polarity(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_camera *cam = ctrl->in_cam; ++ u32 cfg; ++ ++ cfg = readl(ctrl->regs + S3C_CIGCTRL); ++ ++ cfg &= ~(S3C_CIGCTRL_INVPOLPCLK | S3C_CIGCTRL_INVPOLVSYNC | \ ++ S3C_CIGCTRL_INVPOLHREF); ++ ++ if (cam->polarity.pclk) ++ cfg |= S3C_CIGCTRL_INVPOLPCLK; ++ ++ if (cam->polarity.vsync) ++ cfg |= S3C_CIGCTRL_INVPOLVSYNC; ++ ++ if (cam->polarity.href) ++ cfg |= S3C_CIGCTRL_INVPOLHREF; ++ ++ writel(cfg, ctrl->regs + S3C_CIGCTRL); ++} ++ ++static void s3c_fimc_set_rot90(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = 0; ++ ++ if (ctrl->id == 1) { ++ cfg = readl(ctrl->regs + S3C_CIPRCTRL); ++ cfg &= ~S3C_CIPRCTRL_BURST_MASK; ++ cfg |= S3C_CIPRCTRL_YBURST1(4) | S3C_CIPRCTRL_YBURST2(4); ++ writel(cfg, ctrl->regs + S3C_CIPRCTRL); ++ ++ cfg = readl(ctrl->regs + S3C_CIPRTRGFMT); ++ cfg |= S3C_CIPRTRGFMT_ROT90_CLOCKWISE; ++ writel(cfg, ctrl->regs + S3C_CIPRTRGFMT); ++ } ++} ++ ++static void s3c_fimc_set_target_format_pr(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ u32 cfg = 0; ++ ++ switch (frame->format) { ++ case FORMAT_RGB565: /* fall through */ ++ case FORMAT_RGB666: /* fall through */ ++ case FORMAT_RGB888: ++ cfg |= S3C_CIPRTRGFMT_OUTFORMAT_RGB; ++ break; ++ ++ case FORMAT_YCBCR420: ++ cfg |= S3C_CIPRTRGFMT_OUTFORMAT_YCBCR420; ++ break; ++ ++ case FORMAT_YCBCR422: ++ if (frame->planes == 1) ++ cfg |= S3C_CIPRTRGFMT_OUTFORMAT_YCBCR422I; ++ else ++ cfg |= S3C_CIPRTRGFMT_OUTFORMAT_YCBCR422; ++ ++ break; ++ } ++ ++ cfg |= S3C_CIPRTRGFMT_TARGETHSIZE(frame->width); ++ cfg |= S3C_CIPRTRGFMT_TARGETVSIZE(frame->height); ++ cfg |= (frame->flip << S3C_CIPRTRGFMT_FLIP_SHIFT); ++ ++ writel(cfg, ctrl->regs + S3C_CIPRTRGFMT); ++ ++ if (ctrl->rot90) ++ s3c_fimc_set_rot90(ctrl); ++ ++ cfg = S3C_CIPRTAREA_TARGET_AREA(frame->width * frame->height); ++ writel(cfg, ctrl->regs + S3C_CIPRTAREA); ++} ++ ++static void s3c_fimc_set_target_format_co(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ u32 cfg = 0; ++ ++ switch (frame->format) { ++ case FORMAT_RGB565: /* fall through */ ++ case FORMAT_RGB666: /* fall through */ ++ case FORMAT_RGB888: ++ cfg |= S3C_CICOTRGFMT_OUTFORMAT_RGB; ++ break; ++ ++ case FORMAT_YCBCR420: ++ cfg |= S3C_CICOTRGFMT_OUTFORMAT_YCBCR420; ++ break; ++ ++ case FORMAT_YCBCR422: ++ if (frame->planes == 1) ++ cfg |= S3C_CICOTRGFMT_OUTFORMAT_YCBCR422I; ++ else ++ cfg |= S3C_CICOTRGFMT_OUTFORMAT_YCBCR422; ++ ++ break; ++ } ++ ++ cfg |= S3C_CICOTRGFMT_TARGETHSIZE(frame->width); ++ cfg |= S3C_CICOTRGFMT_TARGETVSIZE(frame->height); ++ cfg |= (frame->flip << S3C_CICOTRGFMT_FLIP_SHIFT); ++ ++ writel(cfg, ctrl->regs + S3C_CICOTRGFMT); ++ ++ cfg = S3C_CICOTAREA_TARGET_AREA(frame->width * frame->height); ++ writel(cfg, ctrl->regs + S3C_CICOTAREA); ++} ++ ++void s3c_fimc_set_target_format(struct s3c_fimc_control *ctrl) ++{ ++ if (ctrl->id == 1) ++ s3c_fimc_set_target_format_pr(ctrl); ++ else ++ s3c_fimc_set_target_format_co(ctrl); ++} ++ ++static void s3c_fimc_get_burst_422i(u32 width, u32 *mburst, u32 *rburst) ++{ ++ unsigned int tmp, wanted; ++ ++ tmp = (width / 2) & 0xf; ++ ++ switch (tmp) { ++ case 0: ++ wanted = 16; ++ break; ++ ++ case 4: ++ wanted = 4; ++ break; ++ ++ case 8: ++ wanted = 8; ++ break; ++ ++ default: ++ wanted = 4; ++ break; ++ } ++ ++ *mburst = wanted / 2; ++ *rburst = wanted / 2; ++} ++ ++static void s3c_fimc_get_burst(u32 width, u32 *mburst, u32 *rburst) ++{ ++ unsigned int tmp; ++ ++ tmp = (width / 4) & 0xf; ++ ++ switch (tmp) { ++ case 0: ++ *mburst = 16; ++ *rburst = 16; ++ break; ++ ++ case 4: ++ *mburst = 16; ++ *rburst = 4; ++ break; ++ ++ case 8: ++ *mburst = 16; ++ *rburst = 8; ++ break; ++ ++ default: ++ tmp = (width / 4) % 8; ++ ++ if (tmp == 0) { ++ *mburst = 8; ++ *rburst = 8; ++ } else if (tmp == 4) { ++ *mburst = 8; ++ *rburst = 4; ++ } else { ++ tmp = (width / 4) % 4; ++ *mburst = 4; ++ *rburst = (tmp) ? tmp : 4; ++ } ++ ++ break; ++ } ++} ++ ++static void s3c_fimc_set_output_dma_pr(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ u32 cfg, yburst_m, yburst_r; ++ ++ /* for output dma control */ ++ cfg = readl(ctrl->regs + S3C_CIPRCTRL); ++ ++ cfg &= ~(S3C_CIPRCTRL_BURST_MASK | S3C_CIPRCTRL_ORDER422_MASK); ++ cfg |= frame->order_1p; ++ ++ if (ctrl->rot90) { ++ yburst_m = 4; ++ yburst_r = 4; ++ } else { ++ if (frame->format == FORMAT_RGB888) ++ s3c_fimc_get_burst(frame->width * 4, &yburst_m, &yburst_r); ++ else ++ s3c_fimc_get_burst(frame->width * 2, &yburst_m, &yburst_r); ++ } ++ ++ cfg |= (S3C_CIPRCTRL_YBURST1(yburst_m) | S3C_CIPRCTRL_YBURST2(yburst_r)); ++ ++ writel(cfg, ctrl->regs + S3C_CIPRCTRL); ++} ++ ++static void s3c_fimc_set_output_dma_co(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ u32 cfg, yburst_m, yburst_r, cburst_m, cburst_r; ++ ++ /* for output dma control */ ++ cfg = readl(ctrl->regs + S3C_CICOCTRL); ++ ++ cfg &= ~(S3C_CICOCTRL_BURST_MASK | S3C_CICOCTRL_ORDER422_MASK); ++ cfg |= frame->order_1p; ++ ++ if (frame->format == FORMAT_YCBCR422 && frame->planes == 1) { ++ s3c_fimc_get_burst_422i(frame->width, &yburst_m, &yburst_r); ++ cburst_m = yburst_m / 2; ++ cburst_r = yburst_r / 2; ++ } else { ++ s3c_fimc_get_burst(frame->width, &yburst_m, &yburst_r); ++ s3c_fimc_get_burst(frame->width / 2, &cburst_m, &cburst_r); ++ } ++ ++ cfg |= (S3C_CICOCTRL_YBURST1(yburst_m) | S3C_CICOCTRL_YBURST2(yburst_r)); ++ cfg |= (S3C_CICOCTRL_CBURST1(cburst_m) | S3C_CICOCTRL_CBURST2(cburst_r)); ++ ++ writel(cfg, ctrl->regs + S3C_CICOCTRL); ++} ++ ++void s3c_fimc_set_output_dma(struct s3c_fimc_control *ctrl) ++{ ++ if (ctrl->id == 1) ++ s3c_fimc_set_output_dma_pr(ctrl); ++ else ++ s3c_fimc_set_output_dma_co(ctrl); ++} ++ ++static void s3c_fimc_enable_lastirq_pr(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CIPRCTRL); ++ ++ cfg |= S3C_CIPRCTRL_LASTIRQ_ENABLE; ++ writel(cfg, ctrl->regs + S3C_CIPRCTRL); ++} ++ ++static void s3c_fimc_enable_lastirq_co(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CICOCTRL); ++ ++ cfg |= S3C_CICOCTRL_LASTIRQ_ENABLE; ++ writel(cfg, ctrl->regs + S3C_CICOCTRL); ++} ++ ++void s3c_fimc_enable_lastirq(struct s3c_fimc_control *ctrl) ++{ ++ if (ctrl->id == 1) ++ s3c_fimc_enable_lastirq_pr(ctrl); ++ else ++ s3c_fimc_enable_lastirq_co(ctrl); ++} ++ ++static void s3c_fimc_disable_lastirq_pr(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CIPRCTRL); ++ ++ cfg &= ~S3C_CIPRCTRL_LASTIRQ_ENABLE; ++ writel(cfg, ctrl->regs + S3C_CIPRCTRL); ++} ++ ++static void s3c_fimc_disable_lastirq_co(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CICOCTRL); ++ ++ cfg &= ~S3C_CICOCTRL_LASTIRQ_ENABLE; ++ writel(cfg, ctrl->regs + S3C_CICOCTRL); ++} ++ ++void s3c_fimc_disable_lastirq(struct s3c_fimc_control *ctrl) ++{ ++ if (ctrl->id == 1) ++ s3c_fimc_disable_lastirq_pr(ctrl); ++ else ++ s3c_fimc_disable_lastirq_co(ctrl); ++} ++ ++static void s3c_fimc_set_prescaler_pr(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_scaler *sc = &ctrl->scaler; ++ u32 cfg = 0, shfactor; ++ ++ shfactor = 10 - (sc->hfactor + sc->vfactor); ++ ++ cfg |= S3C_CIPRSCPRERATIO_SHFACTOR(shfactor); ++ cfg |= S3C_CIPRSCPRERATIO_PREHORRATIO(sc->pre_hratio); ++ cfg |= S3C_CIPRSCPRERATIO_PREVERRATIO(sc->pre_vratio); ++ ++ writel(cfg, ctrl->regs + S3C_CIPRSCPRERATIO); ++ ++ cfg = 0; ++ cfg |= S3C_CIPRSCPREDST_PREDSTWIDTH(sc->pre_dst_width); ++ cfg |= S3C_CIPRSCPREDST_PREDSTHEIGHT(sc->pre_dst_height); ++ ++ writel(cfg, ctrl->regs + S3C_CIPRSCPREDST); ++} ++ ++static void s3c_fimc_set_prescaler_co(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_scaler *sc = &ctrl->scaler; ++ u32 cfg = 0, shfactor; ++ ++ shfactor = 10 - (sc->hfactor + sc->vfactor); ++ ++ cfg |= S3C_CICOSCPRERATIO_SHFACTOR(shfactor); ++ cfg |= S3C_CICOSCPRERATIO_PREHORRATIO(sc->pre_hratio); ++ cfg |= S3C_CICOSCPRERATIO_PREVERRATIO(sc->pre_vratio); ++ ++ writel(cfg, ctrl->regs + S3C_CICOSCPRERATIO); ++ ++ cfg = 0; ++ cfg |= S3C_CICOSCPREDST_PREDSTWIDTH(sc->pre_dst_width); ++ cfg |= S3C_CICOSCPREDST_PREDSTHEIGHT(sc->pre_dst_height); ++ ++ writel(cfg, ctrl->regs + S3C_CICOSCPREDST); ++} ++ ++void s3c_fimc_set_prescaler(struct s3c_fimc_control *ctrl) ++{ ++ if (ctrl->id == 1) ++ s3c_fimc_set_prescaler_pr(ctrl); ++ else ++ s3c_fimc_set_prescaler_co(ctrl); ++} ++ ++static void s3c_fimc_set_scaler_pr(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_scaler *sc = &ctrl->scaler; ++ u32 cfg = (S3C_CIPRSCCTRL_CSCR2Y_WIDE | S3C_CIPRSCCTRL_CSCY2R_WIDE); ++ ++ if (sc->bypass) ++ cfg |= S3C_CIPRSCCTRL_SCALERBYPASS; ++ ++ if (sc->scaleup_h) ++ cfg |= S3C_CIPRSCCTRL_SCALEUP_H; ++ ++ if (sc->scaleup_v) ++ cfg |= S3C_CIPRSCCTRL_SCALEUP_V; ++ ++ if (ctrl->in_type == PATH_IN_DMA) { ++ if (ctrl->in_frame.format == FORMAT_RGB565) ++ cfg |= S3C_CIPRSCCTRL_INRGB_FMT_RGB565; ++ else if (ctrl->in_frame.format == FORMAT_RGB666) ++ cfg |= S3C_CIPRSCCTRL_INRGB_FMT_RGB666; ++ else if (ctrl->in_frame.format == FORMAT_RGB888) ++ cfg |= S3C_CIPRSCCTRL_INRGB_FMT_RGB888; ++ } ++ ++ if (ctrl->out_type == PATH_OUT_DMA) { ++ if (ctrl->out_frame.format == FORMAT_RGB565) ++ cfg |= S3C_CIPRSCCTRL_OUTRGB_FMT_RGB565; ++ else if (ctrl->out_frame.format == FORMAT_RGB666) ++ cfg |= S3C_CIPRSCCTRL_OUTRGB_FMT_RGB666; ++ else if (ctrl->out_frame.format == FORMAT_RGB888) ++ cfg |= S3C_CIPRSCCTRL_OUTRGB_FMT_RGB888; ++ } else { ++ cfg |= S3C_CIPRSCCTRL_OUTRGB_FMT_RGB888; ++ ++ if (ctrl->out_frame.scan == SCAN_TYPE_INTERLACE) ++ cfg |= S3C_CIPRSCCTRL_INTERLACE; ++ else ++ cfg |= S3C_CIPRSCCTRL_PROGRESSIVE; ++ } ++ ++ cfg |= S3C_CIPRSCCTRL_MAINHORRATIO(sc->main_hratio); ++ cfg |= S3C_CIPRSCCTRL_MAINVERRATIO(sc->main_vratio); ++ ++ writel(cfg, ctrl->regs + S3C_CIPRSCCTRL); ++} ++ ++static void s3c_fimc_set_scaler_co(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_scaler *sc = &ctrl->scaler; ++ u32 cfg = (S3C_CICOSCCTRL_CSCR2Y_WIDE | S3C_CICOSCCTRL_CSCY2R_WIDE); ++ ++ if (sc->bypass) ++ cfg |= S3C_CICOSCCTRL_SCALERBYPASS; ++ ++ if (sc->scaleup_h) ++ cfg |= S3C_CICOSCCTRL_SCALEUP_H; ++ ++ if (sc->scaleup_v) ++ cfg |= S3C_CICOSCCTRL_SCALEUP_V; ++ ++ if (ctrl->in_type == PATH_IN_DMA) { ++ if (ctrl->in_frame.format == FORMAT_RGB565) ++ cfg |= S3C_CICOSCCTRL_INRGB_FMT_RGB565; ++ else if (ctrl->in_frame.format == FORMAT_RGB666) ++ cfg |= S3C_CICOSCCTRL_INRGB_FMT_RGB666; ++ else if (ctrl->in_frame.format == FORMAT_RGB888) ++ cfg |= S3C_CICOSCCTRL_INRGB_FMT_RGB888; ++ } ++ ++ if (ctrl->out_type == PATH_OUT_DMA) { ++ if (ctrl->out_frame.format == FORMAT_RGB565) ++ cfg |= S3C_CICOSCCTRL_OUTRGB_FMT_RGB565; ++ else if (ctrl->out_frame.format == FORMAT_RGB666) ++ cfg |= S3C_CICOSCCTRL_OUTRGB_FMT_RGB666; ++ else if (ctrl->out_frame.format == FORMAT_RGB888) ++ cfg |= S3C_CICOSCCTRL_OUTRGB_FMT_RGB888; ++ } else { ++ cfg |= S3C_CICOSCCTRL_OUTRGB_FMT_RGB888; ++ ++ if (ctrl->out_frame.scan == SCAN_TYPE_INTERLACE) ++ cfg |= S3C_CICOSCCTRL_INTERLACE; ++ else ++ cfg |= S3C_CICOSCCTRL_PROGRESSIVE; ++ } ++ ++ cfg |= S3C_CICOSCCTRL_MAINHORRATIO(sc->main_hratio); ++ cfg |= S3C_CICOSCCTRL_MAINVERRATIO(sc->main_vratio); ++ ++ writel(cfg, ctrl->regs + S3C_CICOSCCTRL); ++} ++ ++void s3c_fimc_set_scaler(struct s3c_fimc_control *ctrl) ++{ ++ if (ctrl->id == 1) ++ s3c_fimc_set_scaler_pr(ctrl); ++ else ++ s3c_fimc_set_scaler_co(ctrl); ++} ++ ++static void s3c_fimc_start_scaler_pr(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CIPRSCCTRL); ++ ++ cfg |= S3C_CIPRSCCTRL_SCALERSTART; ++ writel(cfg, ctrl->regs + S3C_CIPRSCCTRL); ++ ++ if (ctrl->out_type == PATH_OUT_LCDFIFO) ++ ctrl->open_lcdfifo(1, 0, S3C_WINCON1_LOCALSEL_CAMERA); ++} ++ ++static void s3c_fimc_start_scaler_co(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CICOSCCTRL); ++ ++ cfg |= S3C_CICOSCCTRL_SCALERSTART; ++ writel(cfg, ctrl->regs + S3C_CICOSCCTRL); ++ ++ if (ctrl->out_type == PATH_OUT_LCDFIFO) ++ ctrl->open_lcdfifo(2, 1, S3C_WINCON2_LOCALSEL_CAMERA); ++} ++ ++void s3c_fimc_start_scaler(struct s3c_fimc_control *ctrl) ++{ ++ if (ctrl->id == 1) ++ s3c_fimc_start_scaler_pr(ctrl); ++ else ++ s3c_fimc_start_scaler_co(ctrl); ++} ++ ++static void s3c_fimc_stop_scaler_pr(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CIPRSCCTRL); ++ ++ if (ctrl->out_type == PATH_OUT_LCDFIFO) ++ ctrl->close_lcdfifo(ctrl->id); ++ ++ cfg &= ~S3C_CIPRSCCTRL_SCALERSTART; ++ writel(cfg, ctrl->regs + S3C_CIPRSCCTRL); ++} ++ ++static void s3c_fimc_stop_scaler_co(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CICOSCCTRL); ++ ++ if (ctrl->out_type == PATH_OUT_LCDFIFO) ++ ctrl->close_lcdfifo(ctrl->id); ++ ++ cfg &= ~S3C_CICOSCCTRL_SCALERSTART; ++ writel(cfg, ctrl->regs + S3C_CICOSCCTRL); ++} ++ ++void s3c_fimc_stop_scaler(struct s3c_fimc_control *ctrl) ++{ ++ if (ctrl->id == 1) ++ s3c_fimc_stop_scaler_pr(ctrl); ++ else ++ s3c_fimc_stop_scaler_co(ctrl); ++} ++ ++void s3c_fimc_enable_capture(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CIIMGCPT); ++ ++ if (ctrl->id == 1) { ++ cfg &= ~S3C_CIIMGCPT_CPT_FREN_ENABLE_PR; ++ cfg |= S3C_CIIMGCPT_IMGCPTEN; ++ ++ if (!ctrl->scaler.bypass) ++ cfg |= S3C_CIIMGCPT_IMGCPTEN_PRSC; ++ } else { ++ cfg &= ~S3C_CIIMGCPT_CPT_FREN_ENABLE_CO; ++ cfg |= S3C_CIIMGCPT_IMGCPTEN; ++ ++ if (!ctrl->scaler.bypass) ++ cfg |= S3C_CIIMGCPT_IMGCPTEN_COSC; ++ } ++ ++ writel(cfg, ctrl->regs + S3C_CIIMGCPT); ++} ++ ++void s3c_fimc_disable_capture(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CIIMGCPT); ++ ++ if (ctrl->id == 1) ++ cfg &= ~S3C_CIIMGCPT_IMGCPTEN_PRSC; ++ else ++ cfg &= ~S3C_CIIMGCPT_IMGCPTEN_COSC; ++ ++ if (!(cfg & (S3C_CIIMGCPT_IMGCPTEN_PRSC | S3C_CIIMGCPT_IMGCPTEN_COSC))) ++ cfg &= ~S3C_CIIMGCPT_IMGCPTEN; ++ ++ writel(cfg, ctrl->regs + S3C_CIIMGCPT); ++} ++ ++void s3c_fimc_set_effect(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_effect *effect = &ctrl->out_frame.effect; ++ u32 cfg = S3C_CIIMGEFF_IE_SC_AFTER; ++ ++ if (ctrl->id == 1) ++ cfg |= S3C_CIIMGEFF_IE_ENABLE_PR; ++ else ++ cfg |= S3C_CIIMGEFF_IE_ENABLE_CO; ++ ++ cfg |= effect->type; ++ ++ if (effect->type == EFFECT_ARBITRARY) { ++ cfg |= S3C_CIIMGEFF_PAT_CB(effect->pat_cb); ++ cfg |= S3C_CIIMGEFF_PAT_CR(effect->pat_cr); ++ } ++ ++ writel(cfg, ctrl->regs + S3C_CIIMGEFF); ++} ++ ++static void s3c_fimc_set_input_dma_size_pr(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_in_frame *frame = &ctrl->in_frame; ++ int ofs_h = frame->offset.y_h * 2; ++ int ofs_v = frame->offset.y_v * 2; ++ u32 cfg = S3C_MSPRWIDTH_AUTOLOAD_ENABLE; ++ ++ cfg |= S3C_MSPR_WIDTH(frame->width - ofs_h); ++ cfg |= S3C_MSPR_HEIGHT(frame->height - ofs_v); ++ ++ writel(cfg, ctrl->regs + S3C_MSPRWIDTH); ++} ++ ++static void s3c_fimc_set_input_dma_pr(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_in_frame *frame = &ctrl->in_frame; ++ u32 cfg; ++ ++ /* for original & real size */ ++ s3c_fimc_set_input_dma_size_pr(ctrl); ++ ++ /* for input dma control */ ++ cfg = S3C_MSPRCTRL_INPUT_MEMORY; ++ ++ switch (frame->format) { ++ case FORMAT_RGB565: /* fall through */ ++ case FORMAT_RGB666: /* fall through */ ++ case FORMAT_RGB888: ++ cfg |= S3C_MSPRCTRL_INFORMAT_RGB; ++ break; ++ ++ case FORMAT_YCBCR420: ++ cfg |= S3C_MSPRCTRL_INFORMAT_YCBCR420; ++ break; ++ ++ case FORMAT_YCBCR422: ++ if (frame->planes == 1) { ++ cfg |= S3C_MSPRCTRL_INFORMAT_YCBCR422I; ++ cfg |= frame->order_1p; ++ } else ++ cfg |= S3C_MSPRCTRL_INFORMAT_YCBCR422; ++ ++ break; ++ } ++ ++ writel(cfg, ctrl->regs + S3C_MSPRCTRL); ++} ++ ++static void s3c_fimc_set_input_dma_size_co(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_in_frame *frame = &ctrl->in_frame; ++ int ofs_h = frame->offset.y_h * 2; ++ int ofs_v = frame->offset.y_v * 2; ++ u32 cfg = S3C_MSCOWIDTH_AUTOLOAD_ENABLE; ++ ++ cfg |= S3C_MSCO_WIDTH(frame->width - ofs_h); ++ cfg |= S3C_MSCO_HEIGHT(frame->height - ofs_v); ++ ++ writel(cfg, ctrl->regs + S3C_MSCOWIDTH); ++} ++ ++static void s3c_fimc_set_input_dma_co(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_in_frame *frame = &ctrl->in_frame; ++ u32 cfg; ++ ++ /* for original & real size */ ++ s3c_fimc_set_input_dma_size_co(ctrl); ++ ++ /* for input dma control */ ++ cfg = S3C_MSCOCTRL_INPUT_MEMORY; ++ ++ switch (frame->format) { ++ case FORMAT_RGB565: /* fall through */ ++ case FORMAT_RGB666: /* fall through */ ++ case FORMAT_RGB888: ++ cfg |= S3C_MSCOCTRL_INFORMAT_RGB; ++ break; ++ ++ case FORMAT_YCBCR420: ++ cfg |= S3C_MSCOCTRL_INFORMAT_YCBCR420; ++ break; ++ ++ case FORMAT_YCBCR422: ++ if (frame->planes == 1) ++ cfg |= S3C_MSCOCTRL_INFORMAT_YCBCR422I; ++ else ++ cfg |= S3C_MSCOCTRL_INFORMAT_YCBCR422; ++ ++ break; ++ } ++ ++ writel(cfg, ctrl->regs + S3C_MSCOCTRL); ++} ++ ++void s3c_fimc_set_input_dma(struct s3c_fimc_control *ctrl) ++{ ++ if (ctrl->id == 1) ++ s3c_fimc_set_input_dma_pr(ctrl); ++ else ++ s3c_fimc_set_input_dma_co(ctrl); ++} ++ ++static void s3c_fimc_start_input_dma_pr(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_MSPRCTRL); ++ ++ cfg |= S3C_MSPRCTRL_ENVID; ++ writel(cfg, ctrl->regs + S3C_MSPRCTRL); ++} ++ ++static void s3c_fimc_start_input_dma_co(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_MSCOCTRL); ++ ++ cfg |= S3C_MSCOCTRL_ENVID; ++ writel(cfg, ctrl->regs + S3C_MSCOCTRL); ++} ++ ++void s3c_fimc_start_input_dma(struct s3c_fimc_control *ctrl) ++{ ++ if (ctrl->id == 1) ++ s3c_fimc_start_input_dma_pr(ctrl); ++ else ++ s3c_fimc_start_input_dma_co(ctrl); ++} ++ ++static void s3c_fimc_stop_input_dma_pr(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_MSPRCTRL); ++ ++ cfg &= ~S3C_MSPRCTRL_ENVID; ++ writel(cfg, ctrl->regs + S3C_MSPRCTRL); ++} ++ ++static void s3c_fimc_stop_input_dma_co(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_MSCOCTRL); ++ ++ cfg &= ~S3C_MSCOCTRL_ENVID; ++ writel(cfg, ctrl->regs + S3C_MSCOCTRL); ++} ++ ++void s3c_fimc_stop_input_dma(struct s3c_fimc_control *ctrl) ++{ ++ if (ctrl->id == 1) ++ s3c_fimc_stop_input_dma_pr(ctrl); ++ else ++ s3c_fimc_stop_input_dma_co(ctrl); ++} ++ ++static void s3c_fimc_set_input_path_pr(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_MSPRCTRL); ++ ++ cfg &= ~S3C_MSPRCTRL_INPUT_MASK; ++ ++ if (ctrl->in_type == PATH_IN_DMA) ++ cfg |= S3C_MSPRCTRL_INPUT_MEMORY; ++ else ++ cfg |= S3C_MSPRCTRL_INPUT_EXTCAM; ++ ++ writel(cfg, ctrl->regs + S3C_MSPRCTRL); ++} ++ ++static void s3c_fimc_set_input_path_co(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_MSCOCTRL); ++ ++ cfg &= ~S3C_MSCOCTRL_INPUT_MASK; ++ ++ if (ctrl->in_type == PATH_IN_DMA) ++ cfg |= S3C_MSCOCTRL_INPUT_MEMORY; ++ else ++ cfg |= S3C_MSCOCTRL_INPUT_EXTCAM; ++ ++ writel(cfg, ctrl->regs + S3C_MSCOCTRL); ++} ++ ++void s3c_fimc_set_input_path(struct s3c_fimc_control *ctrl) ++{ ++ if (ctrl->id == 1) ++ s3c_fimc_set_input_path_pr(ctrl); ++ else ++ s3c_fimc_set_input_path_co(ctrl); ++} ++ ++static void s3c_fimc_set_output_path_pr(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CIPRSCCTRL); ++ ++ cfg &= ~S3C_CIPRSCCTRL_LCDPATHEN_FIFO; ++ ++ if (ctrl->out_type == PATH_OUT_LCDFIFO) ++ cfg |= S3C_CIPRSCCTRL_LCDPATHEN_FIFO; ++ ++ writel(cfg, ctrl->regs + S3C_CIPRSCCTRL); ++} ++ ++static void s3c_fimc_set_output_path_co(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CICOSCCTRL); ++ ++ cfg &= ~S3C_CICOSCCTRL_LCDPATHEN_FIFO; ++ ++ if (ctrl->out_type == PATH_OUT_LCDFIFO) ++ cfg |= S3C_CICOSCCTRL_LCDPATHEN_FIFO; ++ ++ writel(cfg, ctrl->regs + S3C_CICOSCCTRL); ++} ++ ++void s3c_fimc_set_output_path(struct s3c_fimc_control *ctrl) ++{ ++ if (ctrl->id == 1) ++ s3c_fimc_set_output_path_pr(ctrl); ++ else ++ s3c_fimc_set_output_path_co(ctrl); ++} ++ ++void s3c_fimc_set_input_address(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_in_frame *frame = &ctrl->in_frame; ++ struct s3c_fimc_frame_addr *addr = &ctrl->in_frame.addr; ++ u32 width = frame->width; ++ u32 height = frame->height; ++ dma_addr_t start_y = addr->phys_y, start_cb = 0, start_cr = 0; ++ dma_addr_t end_y = 0, end_cb = 0, end_cr = 0; ++ ++ if (frame->planes == 1) ++ end_y = start_y + frame->buf_size; ++ else { ++ start_cb = addr->phys_cb; ++ start_cr = addr->phys_cr; ++ ++ if (frame->format == FORMAT_YCBCR420) { ++ end_y = start_y + (width * height); ++ end_cb = start_cb + (width * height / 4); ++ end_cr = start_cr + (width * height / 4); ++ } else { ++ end_y = start_y + (width * height); ++ end_cb = start_cb + (width * height / 2); ++ end_cr = start_cr + (width * height / 2); ++ } ++ } ++ ++ addr->phys_y = start_y; ++ addr->phys_cb = start_cb; ++ addr->phys_cr = start_cr; ++ ++ if (ctrl->id == 1) { ++ writel(start_y, ctrl->regs + S3C_MSPRY0SA); ++ writel(start_cb, ctrl->regs + S3C_MSPRCB0SA); ++ writel(start_cr, ctrl->regs + S3C_MSPRCR0SA); ++ writel(end_y, ctrl->regs + S3C_MSPRY0END); ++ writel(end_cb, ctrl->regs + S3C_MSPRCB0END); ++ writel(end_cr, ctrl->regs + S3C_MSPRCR0END); ++ } else { ++ writel(start_y, ctrl->regs + S3C_MSCOY0SA); ++ writel(start_cb, ctrl->regs + S3C_MSCOCB0SA); ++ writel(start_cr, ctrl->regs + S3C_MSCOCR0SA); ++ writel(end_y, ctrl->regs + S3C_MSCOY0END); ++ writel(end_cb, ctrl->regs + S3C_MSCOCB0END); ++ writel(end_cr, ctrl->regs + S3C_MSCOCR0END); ++ } ++} ++ ++static void s3c_fimc_set_output_address_pr(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ struct s3c_fimc_frame_addr *addr; ++ int i; ++ ++ for (i = 0; i < S3C_FIMC_MAX_FRAMES; i++) { ++ addr = &frame->addr[i]; ++ writel(addr->phys_rgb, ctrl->regs + S3C_CIPRYSA(i)); ++ writel(0, ctrl->regs + S3C_CIPRCBSA(i)); ++ writel(0, ctrl->regs + S3C_CIPRCRSA(i)); ++ } ++} ++ ++static void s3c_fimc_set_output_address_co(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ struct s3c_fimc_frame_addr *addr; ++ int i; ++ ++ for (i = 0; i < S3C_FIMC_MAX_FRAMES; i++) { ++ addr = &frame->addr[i]; ++ writel(addr->phys_y, ctrl->regs + S3C_CICOYSA(i)); ++ writel(addr->phys_cb, ctrl->regs + S3C_CICOCBSA(i)); ++ writel(addr->phys_cr, ctrl->regs + S3C_CICOCRSA(i)); ++ } ++} ++ ++void s3c_fimc_set_output_address(struct s3c_fimc_control *ctrl) ++{ ++ if (ctrl->id == 1) ++ s3c_fimc_set_output_address_pr(ctrl); ++ else ++ s3c_fimc_set_output_address_co(ctrl); ++} ++ ++int s3c_fimc_get_frame_count(struct s3c_fimc_control *ctrl) ++{ ++ if (ctrl->id == 1) { ++ return S3C_CIPRSTATUS_GET_FRAME_COUNT( \ ++ readl(ctrl->regs + S3C_CIPRSTATUS)); ++ } else { ++ return S3C_CICOSTATUS_GET_FRAME_COUNT( \ ++ readl(ctrl->regs + S3C_CICOSTATUS)); ++ } ++} ++ ++void s3c_fimc_wait_frame_end(struct s3c_fimc_control *ctrl) ++{ ++ unsigned long timeo = jiffies; ++ unsigned int frame_cnt = 0; ++ u32 cfg; ++ ++ timeo += 20; /* waiting for 100mS */ ++ ++ if (ctrl->id == 1) { ++ while (time_before(jiffies, timeo)) { ++ cfg = readl(ctrl->regs + S3C_CIPRSTATUS); ++ ++ if (S3C_CIPRSTATUS_GET_FRAME_END(cfg)) { ++ cfg &= ~S3C_CIPRSTATUS_FRAMEEND; ++ writel(cfg, ctrl->regs + S3C_CIPRSTATUS); ++ ++ if (frame_cnt == 2) ++ break; ++ else ++ frame_cnt++; ++ } ++ cond_resched(); ++ } ++ } else { ++ while (time_before(jiffies, timeo)) { ++ cfg = readl(ctrl->regs + S3C_CICOSTATUS); ++ ++ if (S3C_CICOSTATUS_GET_FRAME_END(cfg)) { ++ cfg &= ~S3C_CICOSTATUS_FRAMEEND; ++ writel(cfg, ctrl->regs + S3C_CICOSTATUS); ++ ++ if (frame_cnt == 2) ++ break; ++ else ++ frame_cnt++; ++ } ++ cond_resched(); ++ } ++ } ++} ++ ++void s3c_fimc_change_effect(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_effect *effect = &ctrl->out_frame.effect; ++ u32 cfg = readl(ctrl->regs + S3C_CIIMGEFF); ++ ++ cfg &= ~S3C_CIIMGEFF_FIN_MASK; ++ cfg |= effect->type; ++ ++ if (ctrl->id == 1) ++ cfg |= S3C_CIIMGEFF_IE_ENABLE_PR; ++ else ++ cfg |= S3C_CIIMGEFF_IE_ENABLE_CO; ++ ++ if (effect->type == EFFECT_ARBITRARY) { ++ cfg &= ~S3C_CIIMGEFF_PAT_CBCR_MASK; ++ cfg |= S3C_CIIMGEFF_PAT_CB(effect->pat_cb); ++ cfg |= S3C_CIIMGEFF_PAT_CR(effect->pat_cr); ++ } ++ ++ writel(cfg, ctrl->regs + S3C_CIIMGEFF); ++} ++ ++void s3c_fimc_change_rotate(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg; ++ ++ if (ctrl->rot90) ++ s3c_fimc_set_rot90(ctrl); ++ ++ if (ctrl->out_type == PATH_OUT_DMA) { ++ cfg = readl(ctrl->regs + S3C_CIPRTRGFMT); ++ cfg &= ~S3C_CIPRTRGFMT_FLIP_MASK; ++ cfg |= (ctrl->out_frame.flip << S3C_CIPRTRGFMT_FLIP_SHIFT); ++ ++ writel(cfg, ctrl->regs + S3C_CIPRTRGFMT); ++ } ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimc/s3c_fimc4x_regs.c linux-2.6.28.6/drivers/media/video/samsung/fimc/s3c_fimc4x_regs.c +--- linux-2.6.28/drivers/media/video/samsung/fimc/s3c_fimc4x_regs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimc/s3c_fimc4x_regs.c 2009-10-22 02:12:08.000000000 +0200 +@@ -0,0 +1,715 @@ ++/* linux/drivers/media/video/samsung/s3c_fimc4x_regs.c ++ * ++ * Register interface file for Samsung Camera Interface (FIMC) driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "s3c_fimc.h" ++ ++void s3c_fimc_clear_irq(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CIGCTRL); ++ ++ cfg |= S3C_CIGCTRL_IRQ_CLR; ++ ++ writel(cfg, ctrl->regs + S3C_CIGCTRL); ++} ++ ++int s3c_fimc_check_fifo(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg, status, flag; ++ ++ status = readl(ctrl->regs + S3C_CISTATUS); ++ flag = S3C_CISTATUS_OVFIY | S3C_CISTATUS_OVFICB | S3C_CISTATUS_OVFICR; ++ ++ if (status & flag) { ++ cfg = readl(ctrl->regs + S3C_CIWDOFST); ++ cfg |= (S3C_CIWDOFST_CLROVFIY | S3C_CIWDOFST_CLROVFICB | S3C_CIWDOFST_CLROVFICR); ++ writel(cfg, ctrl->regs + S3C_CIWDOFST); ++ ++ cfg = readl(ctrl->regs + S3C_CIWDOFST); ++ cfg &= ~(S3C_CIWDOFST_CLROVFIY | S3C_CIWDOFST_CLROVFICB | S3C_CIWDOFST_CLROVFICR); ++ writel(cfg, ctrl->regs + S3C_CIWDOFST); ++ } ++ ++ return 0; ++} ++ ++void s3c_fimc_select_camera(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CIGCTRL); ++ ++ cfg &= ~(S3C_CIGCTRL_TESTPATTERN_MASK | S3C_CIGCTRL_SELCAM_ITU_MASK); ++ ++ if (ctrl->in_cam->id == 0) ++ cfg |= S3C_CIGCTRL_SELCAM_ITU_A; ++ else ++ cfg |= S3C_CIGCTRL_SELCAM_ITU_B; ++ ++ writel(cfg, ctrl->regs + S3C_CIGCTRL); ++} ++ ++void s3c_fimc_set_test_pattern(struct s3c_fimc_control *ctrl, int type) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CIGCTRL); ++ ++ cfg &= ~S3C_CIGCTRL_TESTPATTERN_MASK; ++ cfg |= type << S3C_CIGCTRL_TESTPATTERN_SHIFT; ++ ++ writel(cfg, ctrl->regs + S3C_CIGCTRL); ++} ++ ++void s3c_fimc_set_source_format(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_camera *cam = ctrl->in_cam; ++ u32 cfg = 0; ++ ++ cfg |= (cam->mode | cam->order422); ++ cfg |= S3C_CISRCFMT_SOURCEHSIZE(cam->width); ++ cfg |= S3C_CISRCFMT_SOURCEVSIZE(cam->height); ++ ++ writel(cfg, ctrl->regs + S3C_CISRCFMT); ++ ++} ++ ++void s3c_fimc_set_window_offset(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_window_offset *offset = &ctrl->in_cam->offset; ++ u32 cfg; ++ ++ cfg = readl(ctrl->regs + S3C_CIWDOFST); ++ cfg &= ~(S3C_CIWDOFST_WINHOROFST_MASK | S3C_CIWDOFST_WINVEROFST_MASK); ++ cfg |= S3C_CIWDOFST_WINHOROFST(offset->h1); ++ cfg |= S3C_CIWDOFST_WINVEROFST(offset->v1); ++ cfg |= S3C_CIWDOFST_WINOFSEN; ++ writel(cfg, ctrl->regs + S3C_CIWDOFST); ++ ++ cfg = 0; ++ cfg |= S3C_CIWDOFST2_WINHOROFST2(offset->h2); ++ cfg |= S3C_CIWDOFST2_WINVEROFST2(offset->v2); ++ writel(cfg, ctrl->regs + S3C_CIWDOFST2); ++} ++ ++static void s3c_fimc_reset_cfg(struct s3c_fimc_control *ctrl) ++{ ++ int i; ++ u32 cfg[][2] = { ++ { 0x018, 0x00000000 }, { 0x01c, 0x00000000 }, ++ { 0x020, 0x00000000 }, { 0x024, 0x00000000 }, ++ { 0x028, 0x00000000 }, { 0x02c, 0x00000000 }, ++ { 0x030, 0x00000000 }, { 0x034, 0x00000000 }, ++ { 0x038, 0x00000000 }, { 0x03c, 0x00000000 }, ++ { 0x040, 0x00000000 }, { 0x044, 0x00000000 }, ++ { 0x048, 0x00000000 }, { 0x04c, 0x00000000 }, ++ { 0x050, 0x00000000 }, { 0x054, 0x00000000 }, ++ { 0x058, 0x18000000 }, { 0x05c, 0x00000000 }, ++ { 0x0c0, 0x00000000 }, { 0x0c4, 0xffffffff }, ++ { 0x0d0, 0x00100080 }, { 0x0d4, 0x00000000 }, ++ { 0x0d8, 0x00000000 }, { 0x0dc, 0x00000000 }, ++ { 0x0f8, 0x00000000 }, { 0x0fc, 0x04000000 }, ++ { 0x168, 0x00000000 }, { 0x16c, 0x00000000 }, ++ { 0x170, 0x00000000 }, { 0x174, 0x00000000 }, ++ { 0x178, 0x00000000 }, { 0x17c, 0x00000000 }, ++ { 0x180, 0x00000000 }, { 0x184, 0x00000000 }, ++ { 0x188, 0x00000000 }, { 0x18c, 0x00000000 }, ++ { 0x194, 0x0000001e }, ++ }; ++ ++ for (i = 0; i < sizeof(cfg) / 8; i++) ++ writel(cfg[i][1], ctrl->regs + cfg[i][0]); ++} ++ ++void s3c_fimc_reset(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg; ++ ++ /* ++ * we have to write 1 to the CISRCFMT[31] before ++ * getting started the sw reset ++ * ++ */ ++ cfg = readl(ctrl->regs + S3C_CISRCFMT); ++ cfg |= S3C_CISRCFMT_ITU601_8BIT; ++ writel(cfg, ctrl->regs + S3C_CISRCFMT); ++ ++ /* s/w reset */ ++ cfg = readl(ctrl->regs + S3C_CIGCTRL); ++ cfg |= (S3C_CIGCTRL_SWRST | S3C_CIGCTRL_IRQ_LEVEL); ++ writel(cfg, ctrl->regs + S3C_CIGCTRL); ++ mdelay(1); ++ ++ cfg = readl(ctrl->regs + S3C_CIGCTRL); ++ cfg &= ~S3C_CIGCTRL_SWRST; ++ writel(cfg, ctrl->regs + S3C_CIGCTRL); ++ ++ /* in case of ITU656, CISRCFMT[31] should be 0 */ ++ if (ctrl->in_cam && ctrl->in_cam->mode == ITU_656_YCBCR422_8BIT) { ++ cfg = readl(ctrl->regs + S3C_CISRCFMT); ++ cfg &= ~S3C_CISRCFMT_ITU601_8BIT; ++ writel(cfg, ctrl->regs + S3C_CISRCFMT); ++ } ++ ++ s3c_fimc_reset_cfg(ctrl); ++} ++ ++void s3c_fimc_reset_camera(void) ++{ ++ void __iomem *regs = ioremap(S5PC1XX_PA_FIMC0, SZ_4K); ++ u32 cfg; ++ ++ ++#if (CONFIG_VIDEO_FIMC_CAM_RESET == 1) ++ printk("[CAM]Reset camera1.\n"); ++ cfg = readl(regs + S3C_CIGCTRL); ++ cfg |= S3C_CIGCTRL_CAMRST_A; ++ writel(cfg, regs + S3C_CIGCTRL); ++ udelay(200); ++ ++ cfg = readl(regs + S3C_CIGCTRL); ++ cfg &= ~S3C_CIGCTRL_CAMRST_A; ++ writel(cfg, regs + S3C_CIGCTRL); ++ udelay(2000); ++#else ++ printk("[CAM]Reset camera2.\n"); ++ cfg = readl(regs + S3C_CIGCTRL); ++ cfg &= ~S3C_CIGCTRL_CAMRST_A; ++ writel(cfg, regs + S3C_CIGCTRL); ++ udelay(200); ++ ++ cfg = readl(regs + S3C_CIGCTRL); ++ cfg |= S3C_CIGCTRL_CAMRST_A; ++ writel(cfg, regs + S3C_CIGCTRL); ++ udelay(2000); ++#endif ++ ++#if (CONFIG_VIDEO_FIMC_CAM_CH == 1) ++ cfg = readl(S5PC1XX_GPH3CON); ++ cfg &= ~S5PC1XX_GPH3_CONMASK(6); ++ cfg |= S5PC1XX_GPH3_OUTPUT(6); ++ writel(cfg, S5PC1XX_GPH3CON); ++ ++ cfg = readl(S5PC1XX_GPH3DAT); ++ cfg &= ~(0x1 << 6); ++ writel(cfg, S5PC1XX_GPH3DAT); ++ udelay(200); ++ ++ cfg |= (0x1 << 6); ++ writel(cfg, S5PC1XX_GPH3DAT); ++ udelay(2000); ++#endif ++ ++ iounmap(regs); ++} ++ ++void s3c_fimc_set_polarity(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_camera *cam = ctrl->in_cam; ++ u32 cfg; ++ ++ cfg = readl(ctrl->regs + S3C_CIGCTRL); ++ ++ cfg &= ~(S3C_CIGCTRL_INVPOLPCLK | S3C_CIGCTRL_INVPOLVSYNC | \ ++ S3C_CIGCTRL_INVPOLHREF | S3C_CIGCTRL_INVPOLHSYNC); ++ ++ if (cam->polarity.pclk) ++ cfg |= S3C_CIGCTRL_INVPOLPCLK; ++ ++ if (cam->polarity.vsync) ++ cfg |= S3C_CIGCTRL_INVPOLVSYNC; ++ ++ if (cam->polarity.href) ++ cfg |= S3C_CIGCTRL_INVPOLHREF; ++ ++ if (cam->polarity.hsync) ++ cfg |= S3C_CIGCTRL_INVPOLHSYNC; ++ ++ writel(cfg, ctrl->regs + S3C_CIGCTRL); ++} ++ ++static void s3c_fimc_set_rot90(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CITRGFMT); ++ ++ cfg &= ~(S3C_CITRGFMT_INROT90_CLOCKWISE | \ ++ S3C_CITRGFMT_OUTROT90_CLOCKWISE); ++ ++ /* ++ * We use Input Rotator when output is LCD FIFO only. ++ * When LCD FIFO is enabled, input should be DMA. ++ */ ++ if (ctrl->out_type == PATH_OUT_LCDFIFO) ++ cfg |= S3C_CITRGFMT_INROT90_CLOCKWISE; ++ else ++ cfg |= S3C_CITRGFMT_OUTROT90_CLOCKWISE; ++ ++ writel(cfg, ctrl->regs + S3C_CITRGFMT); ++} ++ ++void s3c_fimc_set_target_format(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ u32 cfg = 0; ++ ++ switch (frame->format) { ++ case FORMAT_RGB565: /* fall through */ ++ case FORMAT_RGB666: /* fall through */ ++ case FORMAT_RGB888: ++ cfg |= S3C_CITRGFMT_OUTFORMAT_RGB; ++ break; ++ ++ case FORMAT_YCBCR420: ++ cfg |= S3C_CITRGFMT_OUTFORMAT_YCBCR420; ++ break; ++ ++ case FORMAT_YCBCR422: ++ if (frame->planes == 1) ++ cfg |= S3C_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE; ++ else ++ cfg |= S3C_CITRGFMT_OUTFORMAT_YCBCR422; ++ ++ break; ++ } ++ ++ cfg |= S3C_CITRGFMT_TARGETHSIZE(frame->width); ++ cfg |= S3C_CITRGFMT_TARGETVSIZE(frame->height); ++ cfg |= (frame->flip << S3C_CITRGFMT_FLIP_SHIFT); ++ ++ writel(cfg, ctrl->regs + S3C_CITRGFMT); ++ ++ if (ctrl->rot90) ++ s3c_fimc_set_rot90(ctrl); ++ ++ cfg = S3C_CITAREA_TARGET_AREA(frame->width * frame->height); ++ writel(cfg, ctrl->regs + S3C_CITAREA); ++} ++ ++static void s3c_fimc_set_output_dma_size(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ int ofs_h = frame->offset.y_h * 2; ++ int ofs_v = frame->offset.y_v * 2; ++ u32 cfg = 0; ++ ++ if (ctrl->rot90) { ++ cfg |= S3C_ORGOSIZE_HORIZONTAL(frame->height - ofs_v); ++ cfg |= S3C_ORGOSIZE_VERTICAL(frame->width - ofs_h); ++ } else { ++ cfg |= S3C_ORGOSIZE_HORIZONTAL(frame->width - ofs_h); ++ cfg |= S3C_ORGOSIZE_VERTICAL(frame->height - ofs_v); ++ } ++ ++ writel(cfg, ctrl->regs + S3C_ORGOSIZE); ++} ++ ++void s3c_fimc_set_output_dma(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ u32 cfg; ++ ++ /* for offsets */ ++ cfg = 0; ++ cfg |= S3C_CIOYOFF_HORIZONTAL(frame->offset.y_h); ++ cfg |= S3C_CIOYOFF_VERTICAL(frame->offset.y_v); ++ writel(cfg, ctrl->regs + S3C_CIOYOFF); ++ ++ cfg = 0; ++ cfg |= S3C_CIOCBOFF_HORIZONTAL(frame->offset.cb_h); ++ cfg |= S3C_CIOCBOFF_VERTICAL(frame->offset.cb_v); ++ writel(cfg, ctrl->regs + S3C_CIOCBOFF); ++ ++ cfg = 0; ++ cfg |= S3C_CIOCROFF_HORIZONTAL(frame->offset.cr_h); ++ cfg |= S3C_CIOCROFF_VERTICAL(frame->offset.cr_v); ++ writel(cfg, ctrl->regs + S3C_CIOCROFF); ++ ++ /* for original size */ ++ s3c_fimc_set_output_dma_size(ctrl); ++ ++ /* for output dma control */ ++ cfg = readl(ctrl->regs + S3C_CIOCTRL); ++ ++ cfg &= ~(S3C_CIOCTRL_ORDER2P_MASK | S3C_CIOCTRL_ORDER422_MASK | \ ++ S3C_CIOCTRL_YCBCR_PLANE_MASK); ++ ++ if (frame->planes == 1) ++ cfg |= frame->order_1p; ++ else if (frame->planes == 2) ++ cfg |= (S3C_CIOCTRL_YCBCR_2PLANE | \ ++ (frame->order_2p << S3C_CIOCTRL_ORDER2P_SHIFT)); ++ else if (frame->planes == 3) ++ cfg |= S3C_CIOCTRL_YCBCR_3PLANE; ++ ++ writel(cfg, ctrl->regs + S3C_CIOCTRL); ++} ++ ++void s3c_fimc_enable_lastirq(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CIOCTRL); ++ ++ cfg |= S3C_CIOCTRL_LASTIRQ_ENABLE; ++ writel(cfg, ctrl->regs + S3C_CIOCTRL); ++} ++ ++void s3c_fimc_disable_lastirq(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CIOCTRL); ++ ++ cfg &= ~S3C_CIOCTRL_LASTIRQ_ENABLE; ++ writel(cfg, ctrl->regs + S3C_CIOCTRL); ++} ++ ++void s3c_fimc_set_prescaler(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_scaler *sc = &ctrl->scaler; ++ u32 cfg = 0, shfactor; ++ ++ shfactor = 10 - (sc->hfactor + sc->vfactor); ++ ++ cfg |= S3C_CISCPRERATIO_SHFACTOR(shfactor); ++ cfg |= S3C_CISCPRERATIO_PREHORRATIO(sc->pre_hratio); ++ cfg |= S3C_CISCPRERATIO_PREVERRATIO(sc->pre_vratio); ++ ++ writel(cfg, ctrl->regs + S3C_CISCPRERATIO); ++ ++ cfg = 0; ++ cfg |= S3C_CISCPREDST_PREDSTWIDTH(sc->pre_dst_width); ++ cfg |= S3C_CISCPREDST_PREDSTHEIGHT(sc->pre_dst_height); ++ ++ writel(cfg, ctrl->regs + S3C_CISCPREDST); ++} ++ ++void s3c_fimc_set_scaler(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_scaler *sc = &ctrl->scaler; ++ u32 cfg = (S3C_CISCCTRL_CSCR2Y_WIDE | S3C_CISCCTRL_CSCY2R_WIDE); ++ ++ if (sc->bypass) ++ cfg |= S3C_CISCCTRL_SCALERBYPASS; ++ ++ if (sc->scaleup_h) ++ cfg |= S3C_CISCCTRL_SCALEUP_H; ++ ++ if (sc->scaleup_v) ++ cfg |= S3C_CISCCTRL_SCALEUP_V; ++ ++ if (ctrl->in_type == PATH_IN_DMA) { ++ if (ctrl->in_frame.format == FORMAT_RGB565) ++ cfg |= S3C_CISCCTRL_INRGB_FMT_RGB565; ++ else if (ctrl->in_frame.format == FORMAT_RGB666) ++ cfg |= S3C_CISCCTRL_INRGB_FMT_RGB666; ++ else if (ctrl->in_frame.format == FORMAT_RGB888) ++ cfg |= S3C_CISCCTRL_INRGB_FMT_RGB888; ++ } ++ ++ if (ctrl->out_type == PATH_OUT_DMA) { ++ if (ctrl->out_frame.format == FORMAT_RGB565) ++ cfg |= S3C_CISCCTRL_OUTRGB_FMT_RGB565; ++ else if (ctrl->out_frame.format == FORMAT_RGB666) ++ cfg |= S3C_CISCCTRL_OUTRGB_FMT_RGB666; ++ else if (ctrl->out_frame.format == FORMAT_RGB888) ++ cfg |= S3C_CISCCTRL_OUTRGB_FMT_RGB888; ++ } else { ++ cfg |= S3C_CISCCTRL_OUTRGB_FMT_RGB888; ++ ++ if (ctrl->out_frame.scan == SCAN_TYPE_INTERLACE) ++ cfg |= S3C_CISCCTRL_INTERLACE; ++ else ++ cfg |= S3C_CISCCTRL_PROGRESSIVE; ++ } ++ ++ cfg |= S3C_CISCCTRL_MAINHORRATIO(sc->main_hratio); ++ cfg |= S3C_CISCCTRL_MAINVERRATIO(sc->main_vratio); ++ ++ writel(cfg, ctrl->regs + S3C_CISCCTRL); ++} ++ ++void s3c_fimc_start_scaler(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CISCCTRL); ++ ++ cfg |= S3C_CISCCTRL_SCALERSTART; ++ writel(cfg, ctrl->regs + S3C_CISCCTRL); ++ ++ if (ctrl->out_type == PATH_OUT_LCDFIFO) ++ ctrl->open_lcdfifo(ctrl->id, 0, 0); ++} ++ ++void s3c_fimc_stop_scaler(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CISCCTRL); ++ ++ if (ctrl->out_type == PATH_OUT_LCDFIFO) ++ ctrl->close_lcdfifo(ctrl->id); ++ ++ cfg &= ~S3C_CISCCTRL_SCALERSTART; ++ writel(cfg, ctrl->regs + S3C_CISCCTRL); ++} ++ ++void s3c_fimc_enable_capture(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CIIMGCPT); ++ ++ cfg &= ~S3C_CIIMGCPT_CPT_FREN_ENABLE; ++ cfg |= S3C_CIIMGCPT_IMGCPTEN; ++ ++ if (!ctrl->scaler.bypass) ++ cfg |= S3C_CIIMGCPT_IMGCPTEN_SC; ++ ++ writel(cfg, ctrl->regs + S3C_CIIMGCPT); ++} ++ ++void s3c_fimc_disable_capture(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CIIMGCPT); ++ ++ cfg &= ~(S3C_CIIMGCPT_IMGCPTEN | S3C_CIIMGCPT_IMGCPTEN_SC); ++ writel(cfg, ctrl->regs + S3C_CIIMGCPT); ++} ++ ++void s3c_fimc_set_effect(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_effect *effect = &ctrl->out_frame.effect; ++ u32 cfg = (S3C_CIIMGEFF_IE_ENABLE | S3C_CIIMGEFF_IE_SC_AFTER); ++ ++ cfg |= effect->type; ++ ++ if (effect->type == EFFECT_ARBITRARY) { ++ cfg |= S3C_CIIMGEFF_PAT_CB(effect->pat_cb); ++ cfg |= S3C_CIIMGEFF_PAT_CR(effect->pat_cr); ++ } ++ ++ writel(cfg, ctrl->regs + S3C_CIIMGEFF); ++} ++ ++static void s3c_fimc_set_input_dma_size(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_in_frame *frame = &ctrl->in_frame; ++ int ofs_h = frame->offset.y_h * 2; ++ int ofs_v = frame->offset.y_v * 2; ++ u32 cfg_o = 0, cfg_r = S3C_CIREAL_ISIZE_AUTOLOAD_ENABLE; ++ ++ cfg_o |= S3C_ORGISIZE_HORIZONTAL(frame->width - ofs_h); ++ cfg_o |= S3C_ORGISIZE_VERTICAL(frame->height - ofs_v); ++ cfg_r |= S3C_CIREAL_ISIZE_WIDTH(frame->width - ofs_h); ++ cfg_r |= S3C_CIREAL_ISIZE_HEIGHT(frame->height - ofs_v); ++ ++ writel(cfg_o, ctrl->regs + S3C_ORGISIZE); ++ writel(cfg_r, ctrl->regs + S3C_CIREAL_ISIZE); ++} ++ ++void s3c_fimc_set_input_dma(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_in_frame *frame = &ctrl->in_frame; ++ u32 cfg; ++ ++ /* for offsets */ ++ cfg = 0; ++ cfg |= S3C_CIIYOFF_HORIZONTAL(frame->offset.y_h); ++ cfg |= S3C_CIIYOFF_VERTICAL(frame->offset.y_v); ++ writel(cfg, ctrl->regs + S3C_CIIYOFF); ++ ++ cfg = 0; ++ cfg |= S3C_CIICBOFF_HORIZONTAL(frame->offset.cb_h); ++ cfg |= S3C_CIICBOFF_VERTICAL(frame->offset.cb_v); ++ writel(cfg, ctrl->regs + S3C_CIICBOFF); ++ ++ cfg = 0; ++ cfg |= S3C_CIICROFF_HORIZONTAL(frame->offset.cr_h); ++ cfg |= S3C_CIICROFF_VERTICAL(frame->offset.cr_v); ++ writel(cfg, ctrl->regs + S3C_CIICROFF); ++ ++ /* for original & real size */ ++ s3c_fimc_set_input_dma_size(ctrl); ++ ++ /* for input dma control */ ++ cfg = (S3C_MSCTRL_SUCCESSIVE_COUNT(4) | S3C_MSCTRL_INPUT_MEMORY); ++ ++ switch (frame->format) { ++ case FORMAT_RGB565: /* fall through */ ++ case FORMAT_RGB666: /* fall through */ ++ case FORMAT_RGB888: ++ cfg |= S3C_MSCTRL_INFORMAT_RGB; ++ break; ++ ++ case FORMAT_YCBCR420: ++ cfg |= S3C_MSCTRL_INFORMAT_YCBCR420; ++ ++ if (frame->planes == 2) ++ cfg |= (S3C_MSCTRL_C_INT_IN_2PLANE | \ ++ (frame->order_2p << S3C_MSCTRL_2PLANE_SHIFT)); ++ else ++ cfg |= S3C_MSCTRL_C_INT_IN_3PLANE; ++ ++ break; ++ ++ case FORMAT_YCBCR422: ++ if (frame->planes == 1) ++ cfg |= (frame->order_1p | \ ++ S3C_MSCTRL_INFORMAT_YCBCR422_1PLANE); ++ else { ++ cfg |= S3C_MSCTRL_INFORMAT_YCBCR422; ++ ++ if (frame->planes == 2) ++ cfg |= (S3C_MSCTRL_C_INT_IN_2PLANE | \ ++ (frame->order_2p << S3C_MSCTRL_2PLANE_SHIFT)); ++ else ++ cfg |= S3C_MSCTRL_C_INT_IN_3PLANE; ++ } ++ ++ break; ++ } ++ ++ writel(cfg, ctrl->regs + S3C_MSCTRL); ++} ++ ++void s3c_fimc_start_input_dma(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_MSCTRL); ++ ++ cfg |= S3C_MSCTRL_ENVID; ++ writel(cfg, ctrl->regs + S3C_MSCTRL); ++} ++ ++void s3c_fimc_stop_input_dma(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_MSCTRL); ++ ++ cfg &= ~S3C_MSCTRL_ENVID; ++ writel(cfg, ctrl->regs + S3C_MSCTRL); ++} ++ ++void s3c_fimc_set_input_path(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_MSCTRL); ++ ++ cfg &= ~S3C_MSCTRL_INPUT_MASK; ++ ++ if (ctrl->in_type == PATH_IN_DMA) ++ cfg |= S3C_MSCTRL_INPUT_MEMORY; ++ else ++ cfg |= S3C_MSCTRL_INPUT_EXTCAM; ++ ++ writel(cfg, ctrl->regs + S3C_MSCTRL); ++} ++ ++void s3c_fimc_set_output_path(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CISCCTRL); ++ ++ cfg &= ~S3C_CISCCTRL_LCDPATHEN_FIFO; ++ ++ if (ctrl->out_type == PATH_OUT_LCDFIFO) ++ cfg |= S3C_CISCCTRL_LCDPATHEN_FIFO; ++ ++ writel(cfg, ctrl->regs + S3C_CISCCTRL); ++} ++ ++void s3c_fimc_set_input_address(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_frame_addr *addr = &ctrl->in_frame.addr; ++ u32 cfg = 0; ++ ++ cfg = readl(ctrl->regs + S3C_CIREAL_ISIZE); ++ cfg |= S3C_CIREAL_ISIZE_ADDR_CH_DISABLE; ++ writel(cfg, ctrl->regs + S3C_CIREAL_ISIZE); ++ ++ writel(addr->phys_y, ctrl->regs + S3C_CIIYSA0); ++ writel(addr->phys_cb, ctrl->regs + S3C_CIICBSA0); ++ writel(addr->phys_cr, ctrl->regs + S3C_CIICRSA0); ++ ++ cfg &= ~S3C_CIREAL_ISIZE_ADDR_CH_DISABLE; ++ writel(cfg, ctrl->regs + S3C_CIREAL_ISIZE); ++} ++ ++void s3c_fimc_set_output_address(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ struct s3c_fimc_frame_addr *addr; ++ int i; ++ ++ for (i = 0; i < S3C_FIMC_MAX_FRAMES; i++) { ++ addr = &frame->addr[i]; ++ writel(addr->phys_y, ctrl->regs + S3C_CIOYSA(i)); ++ writel(addr->phys_cb, ctrl->regs + S3C_CIOCBSA(i)); ++ writel(addr->phys_cr, ctrl->regs + S3C_CIOCRSA(i)); ++ } ++} ++ ++int s3c_fimc_get_frame_count(struct s3c_fimc_control *ctrl) ++{ ++ return S3C_CISTATUS_GET_FRAME_COUNT(readl(ctrl->regs + S3C_CISTATUS)); ++} ++ ++void s3c_fimc_wait_frame_end(struct s3c_fimc_control *ctrl) ++{ ++ unsigned long timeo = jiffies; ++ unsigned int frame_cnt = 0; ++ u32 cfg; ++ ++ timeo += 20; /* waiting for 100mS */ ++ ++ while (time_before(jiffies, timeo)) { ++ cfg = readl(ctrl->regs + S3C_CISTATUS); ++ ++ if (S3C_CISTATUS_GET_FRAME_END(cfg)) { ++ cfg &= ~S3C_CISTATUS_FRAMEEND; ++ writel(cfg, ctrl->regs + S3C_CISTATUS); ++ ++ if (frame_cnt == 2) ++ break; ++ else ++ frame_cnt++; ++ } ++ cond_resched(); ++ } ++} ++ ++void s3c_fimc_change_effect(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_effect *effect = &ctrl->out_frame.effect; ++ u32 cfg = readl(ctrl->regs + S3C_CIIMGEFF); ++ ++ cfg &= ~S3C_CIIMGEFF_FIN_MASK; ++ cfg |= (effect->type | S3C_CIIMGEFF_IE_ENABLE); ++ ++ if (effect->type == EFFECT_ARBITRARY) { ++ cfg &= ~S3C_CIIMGEFF_PAT_CBCR_MASK; ++ cfg |= S3C_CIIMGEFF_PAT_CB(effect->pat_cb); ++ cfg |= S3C_CIIMGEFF_PAT_CR(effect->pat_cr); ++ } ++ ++ writel(cfg, ctrl->regs + S3C_CIIMGEFF); ++} ++ ++void s3c_fimc_change_rotate(struct s3c_fimc_control *ctrl) ++{ ++ u32 cfg; ++ ++ if (ctrl->rot90) ++ s3c_fimc_set_rot90(ctrl); ++ ++ if (ctrl->out_type == PATH_OUT_DMA) { ++ cfg = readl(ctrl->regs + S3C_CITRGFMT); ++ cfg &= ~S3C_CITRGFMT_FLIP_MASK; ++ cfg |= (ctrl->out_frame.flip << S3C_CITRGFMT_FLIP_SHIFT); ++ ++ writel(cfg, ctrl->regs + S3C_CITRGFMT); ++ s3c_fimc_set_output_dma_size(ctrl); ++ } ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimc/s3c_fimc_cfg.c linux-2.6.28.6/drivers/media/video/samsung/fimc/s3c_fimc_cfg.c +--- linux-2.6.28/drivers/media/video/samsung/fimc/s3c_fimc_cfg.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimc/s3c_fimc_cfg.c 2009-10-23 11:06:16.000000000 +0200 +@@ -0,0 +1,887 @@ ++/* linux/drivers/media/video/samsung/s3c_fimc_cfg.c ++ * ++ * Configuration support file for Samsung Camera Interface (FIMC) driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "s3c_fimc.h" ++ ++#if (CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC > 0) ++static dma_addr_t s3c_fimc_get_dma_region(u32 bytes) ++{ ++ dma_addr_t end, addr, *curr; ++ ++ end = s3c_fimc.dma_start + s3c_fimc.dma_total; ++ curr = &s3c_fimc.dma_current; ++ ++ if (*curr + bytes > end) { ++ addr = 0; ++ } else { ++ addr = *curr; ++ *curr += bytes; ++ } ++ ++ return addr; ++} ++ ++static void s3c_fimc_put_dma_region(u32 bytes) ++{ ++ s3c_fimc.dma_current -= bytes; ++} ++ ++void s3c_fimc_free_output_memory(struct s3c_fimc_out_frame *info) ++{ ++ struct s3c_fimc_frame_addr *frame; ++ int i; ++ ++ for (i = 0; i < info->nr_frames; i++) { ++ frame = &info->addr[i]; ++ ++ if (frame->phys_y) ++ s3c_fimc_put_dma_region(info->buf_size); ++ ++ memset(frame, 0, sizeof(*frame)); ++ } ++ ++ info->buf_size = 0; ++} ++ ++static int s3c_fimc_alloc_rgb_memory(struct s3c_fimc_out_frame *info) ++{ ++ struct s3c_fimc_frame_addr *frame; ++ int i, ret, nr_frames = info->nr_frames; ++ ++ for (i = 0; i < nr_frames; i++) { ++ frame = &info->addr[i]; ++ ++ frame->phys_rgb = s3c_fimc_get_dma_region(info->buf_size); ++ if (frame->phys_rgb == 0) { ++ ret = -ENOMEM; ++ goto alloc_fail; ++ } ++ ++ frame->virt_rgb = phys_to_virt(frame->phys_rgb); ++ } ++ ++ for (i = nr_frames; i < S3C_FIMC_MAX_FRAMES; i++) { ++ frame = &info->addr[i]; ++ frame->phys_rgb = info->addr[i - nr_frames].phys_rgb; ++ frame->virt_rgb = info->addr[i - nr_frames].virt_rgb; ++ } ++ ++ return 0; ++ ++alloc_fail: ++ s3c_fimc_free_output_memory(info); ++ return ret; ++} ++ ++static int s3c_fimc_alloc_yuv_memory(struct s3c_fimc_out_frame *info) ++{ ++ struct s3c_fimc_frame_addr *frame; ++ int i, ret, nr_frames = info->nr_frames; ++ u32 size = info->width * info->height, cbcr_size; ++ ++ if (info->format == FORMAT_YCBCR420) ++ cbcr_size = size / 4; ++ else ++ cbcr_size = size / 2; ++ ++ for (i = 0; i < nr_frames; i++) { ++ frame = &info->addr[i]; ++ ++ frame->phys_y = s3c_fimc_get_dma_region(info->buf_size); ++ if (frame->phys_y == 0) { ++ ret = -ENOMEM; ++ goto alloc_fail; ++ } ++ ++ frame->phys_cb = frame->phys_y + size; ++ frame->phys_cr = frame->phys_cb + cbcr_size; ++ ++ frame->virt_y = phys_to_virt(frame->phys_y); ++ frame->virt_cb = frame->virt_y + size; ++ frame->virt_cr = frame->virt_cb + cbcr_size; ++ } ++ ++ for (i = nr_frames; i < S3C_FIMC_MAX_FRAMES; i++) { ++ frame = &info->addr[i]; ++ frame->phys_y = info->addr[i - nr_frames].phys_y; ++ frame->phys_cb = info->addr[i - nr_frames].phys_cb; ++ frame->phys_cr = info->addr[i - nr_frames].phys_cr; ++ frame->virt_y = info->addr[i - nr_frames].virt_y; ++ frame->virt_cb = info->addr[i - nr_frames].virt_cb; ++ frame->virt_cr = info->addr[i - nr_frames].virt_cr; ++ } ++ ++ return 0; ++ ++alloc_fail: ++ s3c_fimc_free_output_memory(info); ++ return ret; ++} ++ ++#else ++void s3c_fimc_free_output_memory(struct s3c_fimc_out_frame *info) ++{ ++ struct s3c_fimc_frame_addr *frame; ++ int i; ++ ++ for (i = 0; i < info->nr_frames; i++) { ++ frame = &info->addr[i]; ++ ++ if (frame->virt_y) ++ kfree(frame->virt_y); ++ ++ memset(frame, 0, sizeof(*frame)); ++ } ++ ++ info->buf_size = 0; ++} ++ ++static int s3c_fimc_alloc_rgb_memory(struct s3c_fimc_out_frame *info) ++{ ++ struct s3c_fimc_frame_addr *frame; ++ int i, ret, nr_frames = info->nr_frames; ++ ++ for (i = 0; i < nr_frames; i++) { ++ frame = &info->addr[i]; ++ ++ frame->virt_rgb = kmalloc(info->buf_size, GFP_DMA); ++ if (frame->virt_rgb == NULL) { ++ ret = -ENOMEM; ++ goto alloc_fail; ++ } ++ ++ frame->phys_rgb = virt_to_phys(frame->virt_rgb); ++ } ++ ++ for (i = nr_frames; i < S3C_FIMC_MAX_FRAMES; i++) { ++ frame = &info->addr[i]; ++ frame->virt_rgb = info->addr[i - nr_frames].virt_rgb; ++ frame->phys_rgb = info->addr[i - nr_frames].phys_rgb; ++ } ++ ++ return 0; ++ ++alloc_fail: ++ s3c_fimc_free_output_memory(info); ++ return ret; ++} ++ ++static int s3c_fimc_alloc_yuv_memory(struct s3c_fimc_out_frame *info) ++{ ++ struct s3c_fimc_frame_addr *frame; ++ int i, ret, nr_frames = info->nr_frames; ++ u32 size = info->width * info->height, cbcr_size; ++ ++ if (info->format == FORMAT_YCBCR420) ++ cbcr_size = size / 4; ++ else ++ cbcr_size = size / 2; ++ ++ for (i = 0; i < nr_frames; i++) { ++ frame = &info->addr[i]; ++ ++ frame->virt_y = kmalloc(info->buf_size, GFP_DMA); ++ if (frame->virt_y == NULL) { ++ ret = -ENOMEM; ++ goto alloc_fail; ++ } ++ ++ frame->virt_cb = frame->virt_y + size; ++ frame->virt_cr = frame->virt_cb + cbcr_size; ++ ++ frame->phys_y = virt_to_phys(frame->virt_y); ++ frame->phys_cb = frame->phys_y + size; ++ frame->phys_cr = frame->phys_cb + cbcr_size; ++ } ++ ++ for (i = nr_frames; i < S3C_FIMC_MAX_FRAMES; i++) { ++ frame = &info->addr[i]; ++ frame->phys_y = info->addr[i - nr_frames].phys_y; ++ frame->phys_cb = info->addr[i - nr_frames].phys_cb; ++ frame->phys_cr = info->addr[i - nr_frames].phys_cr; ++ frame->virt_y = info->addr[i - nr_frames].virt_y; ++ frame->virt_cb = info->addr[i - nr_frames].virt_cb; ++ frame->virt_cr = info->addr[i - nr_frames].virt_cr; ++ } ++ ++ return 0; ++ ++alloc_fail: ++ s3c_fimc_free_output_memory(info); ++ return ret; ++} ++#endif ++ ++static u32 s3c_fimc_get_buffer_size(int width, int height, enum s3c_fimc_format_t fmt) ++{ ++ u32 size = width * height; ++ u32 cbcr_size = 0, *buf_size = NULL, one_p_size; ++ ++ switch (fmt) { ++ case FORMAT_RGB565: ++ size *= 2; ++ buf_size = &size; ++ break; ++ ++ case FORMAT_RGB666: /* fall through */ ++ case FORMAT_RGB888: ++ size *= 4; ++ buf_size = &size; ++ break; ++ ++ case FORMAT_YCBCR420: ++ cbcr_size = size / 4; ++ one_p_size = size + (2 * cbcr_size); ++ buf_size = &one_p_size; ++ break; ++ ++ case FORMAT_YCBCR422: ++ cbcr_size = size / 2; ++ one_p_size = size + (2 * cbcr_size); ++ buf_size = &one_p_size; ++ break; ++ } ++ ++ if (*buf_size % PAGE_SIZE != 0) ++ *buf_size = (*buf_size / PAGE_SIZE + 1) * PAGE_SIZE; ++ ++ return *buf_size; ++} ++ ++int s3c_fimc_alloc_output_memory(struct s3c_fimc_out_frame *info) ++{ ++ int ret; ++ ++ info->buf_size = s3c_fimc_get_buffer_size(info->width, info->height, \ ++ info->format); ++ ++ if (info->format == FORMAT_YCBCR420 || info->format == FORMAT_YCBCR422) ++ ret = s3c_fimc_alloc_yuv_memory(info); ++ else ++ ret = s3c_fimc_alloc_rgb_memory(info); ++ ++ return ret; ++} ++ ++int s3c_fimc_alloc_input_memory(struct s3c_fimc_in_frame *info, dma_addr_t addr) ++{ ++ struct s3c_fimc_frame_addr *frame; ++ u32 size = info->width * info->height, cbcr_size; ++ ++ if (info->format == FORMAT_YCBCR420) ++ cbcr_size = size / 4; ++ else ++ cbcr_size = size / 2; ++ ++ info->buf_size = s3c_fimc_get_buffer_size(info->width, info->height, \ ++ info->format); ++ ++ switch (info->format) { ++ case FORMAT_RGB565: /* fall through */ ++ case FORMAT_RGB666: /* fall through */ ++ case FORMAT_RGB888: ++ info->addr.phys_rgb = addr; ++ break; ++ ++ case FORMAT_YCBCR420: /* fall through */ ++ case FORMAT_YCBCR422: ++ frame = &info->addr; ++ frame->phys_y = addr; ++ frame->phys_cb = frame->phys_y + size; ++ frame->phys_cr = frame->phys_cb + cbcr_size; ++ break; ++ } ++ ++ return 0; ++} ++ ++int s3c_fimc_alloc_y_memory(struct s3c_fimc_in_frame *info, ++ dma_addr_t addr) ++{ ++ info->addr.phys_y = addr; ++ info->buf_size = s3c_fimc_get_buffer_size(info->width, \ ++ info->height, info->format); ++ ++ return 0; ++} ++ ++int s3c_fimc_alloc_cb_memory(struct s3c_fimc_in_frame *info, ++ dma_addr_t addr) ++{ ++ info->addr.phys_cb = addr; ++ info->buf_size = s3c_fimc_get_buffer_size(info->width, \ ++ info->height, info->format); ++ ++ return 0; ++} ++ ++int s3c_fimc_alloc_cr_memory(struct s3c_fimc_in_frame *info, ++ dma_addr_t addr) ++{ ++ info->addr.phys_cr = addr; ++ info->buf_size = s3c_fimc_get_buffer_size(info->width, \ ++ info->height, info->format); ++ ++ return 0; ++} ++ ++void s3c_fimc_set_nr_frames(struct s3c_fimc_control *ctrl, int nr) ++{ ++ if (nr == 3) ++ ctrl->out_frame.nr_frames = 2; ++ else ++ ctrl->out_frame.nr_frames = nr; ++} ++ ++static void s3c_fimc_set_input_format(struct s3c_fimc_control *ctrl, ++ struct v4l2_pix_format *fmt) ++{ ++ struct s3c_fimc_in_frame *frame = &ctrl->in_frame; ++ ++ frame->width = fmt->width; ++ frame->height = fmt->height; ++ ++ switch (fmt->pixelformat) { ++ case V4L2_PIX_FMT_RGB565: ++ frame->format = FORMAT_RGB565; ++ frame->planes = 1; ++ break; ++ ++ case V4L2_PIX_FMT_RGB24: ++ frame->format = FORMAT_RGB888; ++ frame->planes = 1; ++ break; ++ ++ case V4L2_PIX_FMT_NV12: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = LSB_CBCR; ++ break; ++ ++ case V4L2_PIX_FMT_NV21: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = LSB_CRCB; ++ break; ++ ++ case V4L2_PIX_FMT_NV12X: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = MSB_CBCR; ++ break; ++ ++ case V4L2_PIX_FMT_NV21X: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = MSB_CRCB; ++ break; ++ ++ case V4L2_PIX_FMT_YUV420: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 3; ++ break; ++ ++ case V4L2_PIX_FMT_YUYV: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = IN_ORDER422_YCBYCR; ++ break; ++ ++ case V4L2_PIX_FMT_YVYU: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = IN_ORDER422_YCRYCB; ++ break; ++ ++ case V4L2_PIX_FMT_UYVY: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = IN_ORDER422_CBYCRY; ++ break; ++ ++ case V4L2_PIX_FMT_VYUY: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = IN_ORDER422_CRYCBY; ++ break; ++ ++ case V4L2_PIX_FMT_NV16: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = LSB_CBCR; ++ break; ++ ++ case V4L2_PIX_FMT_NV61: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = LSB_CRCB; ++ break; ++ ++ case V4L2_PIX_FMT_NV16X: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = MSB_CBCR; ++ break; ++ ++ case V4L2_PIX_FMT_NV61X: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = MSB_CRCB; ++ break; ++ ++ case V4L2_PIX_FMT_YUV422P: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 3; ++ break; ++ } ++} ++ ++int s3c_fimc_set_input_frame(struct s3c_fimc_control *ctrl, ++ struct v4l2_pix_format *fmt) ++{ ++ s3c_fimc_set_input_format(ctrl, fmt); ++ ++ return 0; ++} ++ ++static int s3c_fimc_set_output_format(struct s3c_fimc_control *ctrl, ++ struct v4l2_pix_format *fmt) ++{ ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ int depth = 0; ++ ++ frame->width = fmt->width; ++ frame->height = fmt->height; ++ ++ switch (fmt->pixelformat) { ++ case V4L2_PIX_FMT_RGB565: ++ frame->format = FORMAT_RGB565; ++ frame->planes = 1; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_RGB24: ++ frame->format = FORMAT_RGB888; ++ frame->planes = 1; ++ depth = 24; ++ break; ++ ++ case V4L2_PIX_FMT_NV12: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = LSB_CBCR; ++ depth = 12; ++ break; ++ ++ case V4L2_PIX_FMT_NV21: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = LSB_CRCB; ++ depth = 12; ++ break; ++ ++ case V4L2_PIX_FMT_NV12X: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = MSB_CBCR; ++ depth = 12; ++ break; ++ ++ case V4L2_PIX_FMT_NV21X: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = MSB_CRCB; ++ depth = 12; ++ break; ++ ++ case V4L2_PIX_FMT_YUV420: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 3; ++ depth = 12; ++ break; ++ ++ case V4L2_PIX_FMT_YUYV: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = OUT_ORDER422_YCBYCR; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_YVYU: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = OUT_ORDER422_YCRYCB; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_UYVY: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = OUT_ORDER422_CBYCRY; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_VYUY: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = OUT_ORDER422_CRYCBY; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_NV16: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = LSB_CBCR; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_NV61: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = LSB_CRCB; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_NV16X: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = MSB_CBCR; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_NV61X: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = MSB_CRCB; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_YUV422P: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 3; ++ depth = 16; ++ break; ++ } ++ ++ switch (fmt->field) { ++ case V4L2_FIELD_INTERLACED: ++ case V4L2_FIELD_INTERLACED_TB: ++ case V4L2_FIELD_INTERLACED_BT: ++ frame->scan = SCAN_TYPE_INTERLACE; ++ break; ++ ++ default: ++ frame->scan = SCAN_TYPE_PROGRESSIVE; ++ break; ++ } ++ ++ return depth; ++} ++ ++int s3c_fimc_set_output_frame(struct s3c_fimc_control *ctrl, ++ struct v4l2_pix_format *fmt) ++{ ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ int depth = 0; ++ ++ depth = s3c_fimc_set_output_format(ctrl, fmt); ++ ++ if (ctrl->out_type == PATH_OUT_DMA && frame->addr[0].virt_y == NULL) { ++ if (s3c_fimc_alloc_output_memory(frame)) ++ err("cannot allocate memory\n"); ++ } ++ ++ return depth; ++} ++ ++int s3c_fimc_frame_handler(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ int ret; ++ ++ frame->skip_frames++; ++ dev_dbg(ctrl->dev, "irq is being handled by frame hander\n"); ++ ++ switch (ctrl->flag & S3C_FIMC_IRQ_MASK) { ++ case S3C_FIMC_FLAG_IRQ_NORMAL: ++ dev_dbg(ctrl->dev, "irq flag is normal\n"); ++ FSET_RUNNING(ctrl); ++ FSET_IRQ_X(ctrl); ++ ret = S3C_FIMC_FRAME_SKIP; ++ break; ++ ++ case S3C_FIMC_FLAG_IRQ_X: ++ dev_dbg(ctrl->dev, "irq flag is x\n"); ++ s3c_fimc_enable_lastirq(ctrl); ++ s3c_fimc_disable_lastirq(ctrl); ++ FSET_HANDLE_IRQ(ctrl); ++ FSET_IRQ_LAST(ctrl); ++ ret = S3C_FIMC_FRAME_SKIP; ++ break; ++ ++ case S3C_FIMC_FLAG_IRQ_LAST: ++ dev_dbg(ctrl->dev, "irq flag is last\n"); ++ FSET_HANDLE_IRQ(ctrl); ++ FSET_IRQ_X(ctrl); ++ ret = S3C_FIMC_FRAME_TAKE; ++ break; ++ ++ default: ++ dev_dbg(ctrl->dev, "unknown irq state\n"); ++ ret = S3C_FIMC_FRAME_SKIP; ++ break; ++ } ++ ++ return ret; ++} ++ ++u8 *s3c_fimc_get_current_frame(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ ++ return frame->addr[frame->cfn].virt_y; ++} ++ ++static int s3c_fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift) ++{ ++ if (src >= tar * 64) { ++ err("out of pre-scaler range\n"); ++ return -EINVAL; ++ } else if (src >= tar * 32) { ++ *ratio = 32; ++ *shift = 5; ++ } else if (src >= tar * 16) { ++ *ratio = 16; ++ *shift = 4; ++ } else if (src >= tar * 8) { ++ *ratio = 8; ++ *shift = 3; ++ } else if (src >= tar * 4) { ++ *ratio = 4; ++ *shift = 2; ++ } else if (src >= tar * 2) { ++ *ratio = 2; ++ *shift = 1; ++ } else { ++ *ratio = 1; ++ *shift = 0; ++ } ++ ++ return 0; ++} ++ ++int s3c_fimc_set_scaler_info(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_scaler *sc = &ctrl->scaler; ++ struct s3c_fimc_window_offset *w_ofs = &ctrl->in_cam->offset; ++ struct s3c_fimc_dma_offset *d_ofs = &ctrl->in_frame.offset; ++ int ret, tx, ty, sx, sy; ++ int width, height, h_ofs, v_ofs; ++ ++ if (ctrl->in_type == PATH_IN_DMA) { ++ /* input rotator case */ ++ if (ctrl->rot90 && ctrl->out_type == PATH_OUT_LCDFIFO) { ++ width = ctrl->in_frame.height; ++ height = ctrl->in_frame.width; ++ h_ofs = d_ofs->y_v * 2; ++ v_ofs = d_ofs->y_h * 2; ++ } else { ++ width = ctrl->in_frame.width; ++ height = ctrl->in_frame.height; ++ h_ofs = d_ofs->y_h * 2; ++ v_ofs = d_ofs->y_v * 2; ++ } ++ } else { ++ width = ctrl->in_cam->width; ++ height = ctrl->in_cam->height; ++ h_ofs = w_ofs->h1 + w_ofs->h2; ++ v_ofs = w_ofs->v1 + w_ofs->v2; ++ } ++ ++ tx = ctrl->out_frame.width; ++ ty = ctrl->out_frame.height; ++ ++ if (tx <= 0 || ty <= 0) { ++ err("invalid target size\n"); ++ ret = -EINVAL; ++ goto err_size; ++ } ++ ++ sx = width - h_ofs; ++ sy = height - v_ofs; ++ ++ sc->real_width = sx; ++ sc->real_height = sy; ++ ++ if (sx <= 0 || sy <= 0) { ++ err("invalid source size\n"); ++ ret = -EINVAL; ++ goto err_size; ++ } ++ ++ s3c_fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor); ++ s3c_fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor); ++ ++ if (IS_PREVIEW(ctrl) && (sx / sc->pre_hratio > sc->line_length)) ++ info("line buffer size overflow\n"); ++ ++ sc->pre_dst_width = sx / sc->pre_hratio; ++ sc->pre_dst_height = sy / sc->pre_vratio; ++ ++ sc->main_hratio = (sx << 8) / (tx << sc->hfactor); ++ sc->main_vratio = (sy << 8) / (ty << sc->vfactor); ++ ++ sc->scaleup_h = (tx >= sx) ? 1 : 0; ++ sc->scaleup_v = (ty >= sy) ? 1 : 0; ++ ++ s3c_fimc_set_prescaler(ctrl); ++ s3c_fimc_set_scaler(ctrl); ++ ++ return 0; ++ ++err_size: ++ return ret; ++} ++ ++/* CAUTION: many sequence dependencies */ ++void s3c_fimc_start_dma(struct s3c_fimc_control *ctrl) ++{ ++ s3c_fimc_set_input_path(ctrl); ++ ++ if (ctrl->in_type == PATH_IN_DMA) { ++ s3c_fimc_set_input_address(ctrl); ++ s3c_fimc_set_input_dma(ctrl); ++ } else { ++ s3c_fimc_set_source_format(ctrl); ++ s3c_fimc_set_window_offset(ctrl); ++ s3c_fimc_set_polarity(ctrl); ++ } ++ ++ s3c_fimc_set_scaler_info(ctrl); ++ s3c_fimc_set_target_format(ctrl); ++ s3c_fimc_set_output_path(ctrl); ++ ++ if (ctrl->out_type == PATH_OUT_DMA) { ++ s3c_fimc_set_output_address(ctrl); ++ s3c_fimc_set_output_dma(ctrl); ++ } ++ ++ if (!ctrl->scaler.bypass) ++ s3c_fimc_start_scaler(ctrl); ++ ++ s3c_fimc_enable_capture(ctrl); ++ ++ if (ctrl->in_type == PATH_IN_DMA) ++ s3c_fimc_start_input_dma(ctrl); ++} ++ ++void s3c_fimc_stop_dma(struct s3c_fimc_control *ctrl) ++{ ++ if (ctrl->in_type == PATH_IN_DMA) ++ s3c_fimc_stop_input_dma(ctrl); ++ ++ s3c_fimc_stop_scaler(ctrl); ++ s3c_fimc_disable_capture(ctrl); ++ s3c_fimc_wait_frame_end(ctrl); ++} ++ ++void s3c_fimc_restart_dma(struct s3c_fimc_control *ctrl) ++{ ++ s3c_fimc_stop_dma(ctrl); ++ s3c_fimc_start_dma(ctrl); ++} ++ ++void s3c_fimc_change_resolution(struct s3c_fimc_control *ctrl, ++ enum s3c_fimc_cam_res_t res) ++{ ++ struct s3c_fimc_camera *cam = ctrl->in_cam; ++ ++ s3c_fimc_stop_scaler(ctrl); ++ s3c_fimc_i2c_command(ctrl, I2C_CAM_RESOLUTION, res); ++ ++ switch (res) { ++ case CAM_RES_QSVGA: ++ info("resolution changed to QSVGA (400x300) mode\n"); ++ cam->width = 400; ++ cam->height = 300; ++ break; ++ ++ case CAM_RES_VGA: ++ info("resolution changed to VGA (640x480) mode\n"); ++ cam->width = 640; ++ cam->height = 480; ++ break; ++ ++ case CAM_RES_SVGA: ++ info("resolution changed to SVGA (800x600) mode\n"); ++ cam->width = 800; ++ cam->height = 600; ++ break; ++ ++ case CAM_RES_SXGA: ++ info("resolution changed to SXGA (1280x1024) mode\n"); ++ cam->width = 1280; ++ cam->height = 1024; ++ break; ++ ++ case CAM_RES_UXGA: ++ info("resolution changed to UXGA (1600x1200) mode\n"); ++ cam->width = 1600; ++ cam->height = 1200; ++ break; ++ ++ case CAM_RES_DEFAULT: /* fall through */ ++ case CAM_RES_MAX: ++ /* nothing to do */ ++ break; ++ } ++} ++ ++int s3c_fimc_check_zoom(struct s3c_fimc_control *ctrl, int type) ++{ ++ struct s3c_fimc_scaler *sc = &ctrl->scaler; ++ struct s3c_fimc_window_offset *offset = &ctrl->in_cam->offset; ++ int sx = sc->real_width; ++ int zoom_pixels = S3C_FIMC_ZOOM_PIXELS * 2; ++ int zoom_size = sx - (offset->h1 + offset->h2 + zoom_pixels); ++ ++ switch (type) { ++ case V4L2_CID_ZOOM_IN: ++ if (zoom_size / sc->pre_hratio > sc->line_length) { ++ err("already reached to zoom-in boundary\n"); ++ return -EINVAL; ++ } ++ ++ sc->zoom_depth++; ++ break; ++ ++ case V4L2_CID_ZOOM_OUT: ++ if (sc->zoom_depth > 0) ++ sc->zoom_depth--; ++ else { ++ err("already reached to zoom-out boundary\n"); ++ return -EINVAL; ++ } ++ ++ break; ++ } ++ ++ return 0; ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimc/s3c_fimc_core.c linux-2.6.28.6/drivers/media/video/samsung/fimc/s3c_fimc_core.c +--- linux-2.6.28/drivers/media/video/samsung/fimc/s3c_fimc_core.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimc/s3c_fimc_core.c 2010-04-21 06:37:12.000000000 +0200 +@@ -0,0 +1,588 @@ ++/* linux/drivers/media/video/samsung/s3c_fimc_core.c ++ * ++ * Core file for Samsung Camera Interface (FIMC) driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "s3c_fimc.h" ++ ++static struct s3c_fimc_camera test_pattern = { ++ .id = S3C_FIMC_TPID, ++ .type = CAM_TYPE_ITU, ++ .mode = ITU_601_YCBCR422_8BIT, ++ .order422 = CAM_ORDER422_8BIT_YCBYCR, ++ .clockrate = 0, ++ .width = 640, ++ .height = 480, ++ .offset = { ++ .h1 = 0, ++ .h2 = 0, ++ .v1 = 0, ++ .v2 = 0, ++ }, ++ ++ .polarity = { ++ .pclk = 0, ++ .vsync = 0, ++ .href = 0, ++ .hsync = 0, ++ }, ++ ++ .initialized = 0, ++}; ++ ++struct s3c_fimc_config s3c_fimc; ++ ++struct s3c_platform_fimc *to_fimc_plat(struct device *dev) ++{ ++ struct platform_device *pdev = to_platform_device(dev); ++ ++ return (struct s3c_platform_fimc *) pdev->dev.platform_data; ++} ++ ++u8 s3c_fimc_i2c_read(struct i2c_client *client, u8 subaddr) ++{ ++ u8 buf[1]; ++ struct i2c_msg msg = {client->addr, 0, 1, buf}; ++ int ret; ++ ++ buf[0] = subaddr; ++ ++ ret = i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO; ++ if (ret == -EIO) { ++ err("i2c transfer error\n"); ++ return -EIO; ++ } ++ ++ msg.flags = I2C_M_RD; ++ ret = i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO; ++ ++ return buf[0]; ++} ++ ++int s3c_fimc_i2c_write(struct i2c_client *client, u8 subaddr, u8 val) ++{ ++ u8 buf[2]; ++ struct i2c_msg msg = {client->addr, 0, 2, buf}; ++ ++ buf[0] = subaddr; ++ buf[1] = val; ++ ++ return i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO; ++} ++ ++void s3c_fimc_i2c_command(struct s3c_fimc_control *ctrl, u32 cmd, int arg) ++{ ++ struct i2c_client *client = ctrl->in_cam->client; ++ ++ if (client) ++ client->driver->command(client, cmd, (void *) arg); ++ else ++ err("i2c client is not registered\n"); ++} ++ ++void s3c_fimc_register_camera(struct s3c_fimc_camera *cam) ++{ ++ int i; ++ static int once=0; ++ //printk("[CAM]s3c_fimc_register_camera,cam->id=%d\n",cam->id); ++ s3c_fimc.camera[cam->id] = cam; ++ ++ for (i = 0; i < S3C_FIMC_MAX_CTRLS; i++) { ++ s3c_fimc.ctrl[i].in_cam = s3c_fimc.camera[cam->id]; ++ } ++ clk_disable(s3c_fimc.cam_clock); ++ clk_set_rate(s3c_fimc.cam_clock, cam->clockrate); ++ clk_enable(s3c_fimc.cam_clock); ++ ++ s3c_fimc_reset_camera();//comment by ur better ++ ++ ++ //printk("[CAM]Reset and init reg!1cam->client=%x\n",cam->client); ++ /*printk("[CAM]Reset and init reg!1\n"); ++ if((once==0)&&(cam->client!=0)) ++ { ++ printk("[CAM]Reset and init reg!2\n"); ++ //s3c_fimc_reset_camera(); ++ for (i = 0; i < S3C_FIMC_MAX_CTRLS; i++) { ++ s3c_fimc_init_camera(&s3c_fimc.ctrl[i]); ++ } ++ once = 1; ++ } ++ printk("[CAM]Reset and init reg!3\n"); ++ */ ++ ++} ++ ++void s3c_fimc_unregister_camera(struct s3c_fimc_camera *cam) ++{ ++ int i = 0; ++ ++ for (i = 0; i < S3C_FIMC_MAX_CTRLS; i++) { ++ if (s3c_fimc.ctrl[i].in_cam == cam) ++ s3c_fimc.ctrl[i].in_cam = NULL; ++ } ++ ++ s3c_fimc.camera[cam->id] = NULL; ++} ++ ++void s3c_fimc_set_active_camera(struct s3c_fimc_control *ctrl, int id) ++{ ++ //printk("[CAM]s3c_fimc_set_active_camera,id=%d\n",id); ++ ctrl->in_cam = s3c_fimc.camera[id]; ++ //printk("ctrl->in_cam=%x,s3c_fimc.camera[id]=%x.\n",ctrl->in_cam,s3c_fimc.camera[id]); ++ ++ if (ctrl->in_cam && id < S3C_FIMC_TPID) ++ s3c_fimc_select_camera(ctrl); ++} ++ ++void s3c_fimc_init_camera(struct s3c_fimc_control *ctrl) ++{ ++ //printk("[CAM]s3c_fimc_init_camera"); ++ struct s3c_fimc_camera *cam = ctrl->in_cam; ++ ++ if (cam && cam->id != S3C_FIMC_TPID && !cam->initialized) { ++ //printk("[CAM]I2C_CAM_INIT.\n"); ++ s3c_fimc_i2c_command(ctrl, I2C_CAM_INIT, 0); ++ s3c_fimc_change_resolution(ctrl, CAM_RES_DEFAULT); ++ cam->initialized = 1; ++ } ++} ++ ++static irqreturn_t s3c_fimc_irq(int irq, void *dev_id) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) dev_id; ++ ++ s3c_fimc_clear_irq(ctrl); ++ s3c_fimc_check_fifo(ctrl); ++ ++ if (IS_CAPTURE(ctrl)) { ++ dev_dbg(ctrl->dev, "irq is in capture state\n"); ++ ++ if (s3c_fimc_frame_handler(ctrl) == S3C_FIMC_FRAME_SKIP) ++ return IRQ_HANDLED; ++ ++ wake_up_interruptible(&ctrl->waitq); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static ++struct s3c_fimc_control *s3c_fimc_register_controller(struct platform_device *pdev) ++{ ++ struct s3c_platform_fimc *pdata; ++ struct s3c_fimc_control *ctrl; ++ struct resource *res; ++ int i = S3C_FIMC_MAX_CTRLS - 1; ++ int id = pdev->id; ++ ++ pdata = to_fimc_plat(&pdev->dev); ++ ++ //printk("[CAM]s3c_fimc_register_controller.id=%d\n",id); ++ ++ ctrl = &s3c_fimc.ctrl[id]; ++ ctrl->id = id; ++ ctrl->dev = &pdev->dev; ++ ctrl->vd = &s3c_fimc_video_device[id]; ++ ctrl->rot90 = 0; ++ ctrl->vd->minor = id; ++ ctrl->out_frame.nr_frames = pdata->nr_frames; ++ ctrl->out_frame.skip_frames = 0; ++ ctrl->scaler.line_length = pdata->line_length; ++ ++ sprintf(ctrl->name, "%s%d", S3C_FIMC_NAME, id); ++ strcpy(ctrl->vd->name, ctrl->name); ++ ++ ctrl->open_lcdfifo = s3cfb_enable_local; ++ ctrl->close_lcdfifo = s3cfb_enable_dma; ++ ++ atomic_set(&ctrl->in_use, 0); ++ mutex_init(&ctrl->lock); ++ init_waitqueue_head(&ctrl->waitq); ++ ++ /* get resource for io memory */ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ err("failed to get io memory region\n"); ++ return NULL; ++ } ++ ++ if (!pdata->shared_io) { ++ /* request mem region */ ++ res = request_mem_region(res->start, res->end - res->start + 1, pdev->name); ++ if (!res) { ++ err("failed to request io memory region\n"); ++ return NULL; ++ } ++ ++ /* ioremap for register block */ ++ ctrl->regs = ioremap(res->start, res->end - res->start + 1); ++ } else { ++ while (i >= 0 && ctrl->regs == NULL) { ++ ctrl->regs = s3c_fimc.ctrl[i].regs; ++ i--; ++ } ++ } ++ ++ if (!ctrl->regs) { ++ err("failed to remap io region\n"); ++ return NULL; ++ } ++ ++ /* irq */ ++ ctrl->irq = platform_get_irq(pdev, 0); ++ if (request_irq(ctrl->irq, s3c_fimc_irq, IRQF_DISABLED, ctrl->name, ctrl)) ++ err("request_irq failed\n"); ++ ++ s3c_fimc_reset(ctrl); ++ s3c_fimc_set_active_camera(ctrl, 0);//note: only one camera type ++ ++ return ctrl; ++} ++ ++static int s3c_fimc_unregister_controller(struct platform_device *pdev) ++{ ++ struct s3c_fimc_control *ctrl; ++ struct s3c_platform_fimc *pdata; ++ int id = pdev->id; ++ ++ ctrl = &s3c_fimc.ctrl[id]; ++ ++ s3c_fimc_free_output_memory(&ctrl->out_frame); ++ ++ pdata = to_fimc_plat(ctrl->dev); ++ ++ if (!pdata->shared_io) ++ iounmap(ctrl->regs); ++ ++ memset(ctrl, 0, sizeof(*ctrl)); ++ ++ return 0; ++} ++ ++static int s3c_fimc_mmap(struct file* filp, struct vm_area_struct *vma) ++{ ++ struct s3c_fimc_control *ctrl = filp->private_data; ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ ++ u32 size = vma->vm_end - vma->vm_start; ++ u32 pfn, total_size = frame->buf_size; ++ ++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ vma->vm_flags |= VM_RESERVED; ++ ++ /* page frame number of the address for a source frame to be stored at. */ ++ pfn = __phys_to_pfn(frame->addr[vma->vm_pgoff].phys_y); ++ ++ if (size > total_size) { ++ err("the size of mapping is too big\n"); ++ return -EINVAL; ++ } ++ ++ if ((vma->vm_flags & VM_WRITE) && !(vma->vm_flags & VM_SHARED)) { ++ err("writable mapping must be shared\n"); ++ return -EINVAL; ++ } ++ ++ if (remap_pfn_range(vma, vma->vm_start, pfn, size, vma->vm_page_prot)) { ++ err("mmap fail\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static u32 s3c_fimc_poll(struct file *filp, poll_table *wait) ++{ ++ struct s3c_fimc_control *ctrl = filp->private_data; ++ u32 mask = 0; ++ ++ poll_wait(filp, &ctrl->waitq, wait); ++ ++ if (IS_IRQ_HANDLING(ctrl)) ++ mask = POLLIN | POLLRDNORM; ++ ++ FSET_STOP(ctrl); ++ ++ return mask; ++} ++ ++static ++ssize_t s3c_fimc_read(struct file *filp, char *buf, size_t count, loff_t *pos) ++{ ++ struct s3c_fimc_control *ctrl = filp->private_data; ++ size_t end; ++ ++ if (IS_CAPTURE(ctrl)) { ++ if (wait_event_interruptible(ctrl->waitq, IS_IRQ_HANDLING(ctrl))) ++ return -ERESTARTSYS; ++ ++ FSET_STOP(ctrl); ++ } ++ //printk("[CAM]ctrl->out_frame.buf_size=%d,count=%d.\n",ctrl->out_frame.buf_size,count); ++ ++ end = min_t(size_t, ctrl->out_frame.buf_size, count); ++ ++ if (copy_to_user(buf, s3c_fimc_get_current_frame(ctrl), end)) ++ return -EFAULT; ++ ++ return end; ++} ++ ++static ++ssize_t s3c_fimc_write(struct file *filp, const char *b, size_t c, loff_t *offset) ++{ ++ return 0; ++} ++ ++static int s3c_fimc_open(struct inode *inode, struct file *filp) ++{ ++ struct s3c_fimc_control *ctrl; ++ int id, ret; ++ ++ id = MINOR(inode->i_rdev); ++ //printk("[CAM]s3c_fimc_open.id=%d\n",id); ++ ctrl = &s3c_fimc.ctrl[id]; ++ //printk("ctrl->in_cam=%x",ctrl->in_cam); ++ ++ //printk("[CAM]ctrl->in_cam->width=%d\n",ctrl->in_cam->width); ++ ++ mutex_lock(&ctrl->lock); ++ ++ if (atomic_read(&ctrl->in_use)) { ++ ret = -EBUSY; ++ goto resource_busy; ++ } else { ++ atomic_inc(&ctrl->in_use); ++ s3c_fimc_reset(ctrl); ++ filp->private_data = ctrl; ++ } ++ ++ mutex_unlock(&ctrl->lock); ++ ++ return 0; ++ ++resource_busy: ++ mutex_unlock(&ctrl->lock); ++ return ret; ++} ++ ++static int s3c_fimc_release(struct inode *inode, struct file *filp) ++{ ++ struct s3c_fimc_control *ctrl; ++ int id; ++ ++ id = MINOR(inode->i_rdev); ++ ctrl = &s3c_fimc.ctrl[id]; ++ ++ mutex_lock(&ctrl->lock); ++ ++ atomic_dec(&ctrl->in_use); ++ filp->private_data = NULL; ++ ++ mutex_unlock(&ctrl->lock); ++ ++ return 0; ++} ++ ++static const struct file_operations s3c_fimc_fops = { ++ .owner = THIS_MODULE, ++ .open = s3c_fimc_open, ++ .release = s3c_fimc_release, ++ .ioctl = video_ioctl2, ++ .read = s3c_fimc_read, ++ .write = s3c_fimc_write, ++ .mmap = s3c_fimc_mmap, ++ .poll = s3c_fimc_poll, ++}; ++ ++static void s3c_fimc_vdev_release(struct video_device *vdev) ++{ ++ kfree(vdev); ++} ++ ++struct video_device s3c_fimc_video_device[S3C_FIMC_MAX_CTRLS] = { ++ [0] = { ++ .vfl_type = VID_TYPE_OVERLAY | VID_TYPE_CAPTURE | VID_TYPE_CLIPPING | VID_TYPE_SCALES, ++ .fops = &s3c_fimc_fops, ++ .ioctl_ops = &s3c_fimc_v4l2_ops, ++ .release = s3c_fimc_vdev_release, ++ }, ++ [1] = { ++ .vfl_type = VID_TYPE_OVERLAY | VID_TYPE_CAPTURE | VID_TYPE_CLIPPING | VID_TYPE_SCALES, ++ .fops = &s3c_fimc_fops, ++ .ioctl_ops = &s3c_fimc_v4l2_ops, ++ .release = s3c_fimc_vdev_release, ++ }, ++ [2] = { ++ .vfl_type = VID_TYPE_OVERLAY | VID_TYPE_CAPTURE | VID_TYPE_CLIPPING | VID_TYPE_SCALES, ++ .fops = &s3c_fimc_fops, ++ .ioctl_ops = &s3c_fimc_v4l2_ops, ++ .release = s3c_fimc_vdev_release, ++ }, ++}; ++ ++static int s3c_fimc_init_global(struct platform_device *pdev) ++{ ++ /* camera clock */ ++ s3c_fimc.cam_clock = clk_get(&pdev->dev, "sclk_cam"); ++ if (IS_ERR(s3c_fimc.cam_clock)) { ++ err("failed to get camera clock source\n"); ++ return -EINVAL; ++ } ++ ++ s3c_fimc.dma_start = s3c_get_media_memory(S3C_MDEV_FIMC); ++ s3c_fimc.dma_total = s3c_get_media_memsize(S3C_MDEV_FIMC); ++ s3c_fimc.dma_current = s3c_fimc.dma_start; ++ ++ /* test pattern */ ++ s3c_fimc.camera[test_pattern.id] = &test_pattern; ++ ++ return 0; ++} ++ ++static int s3c_fimc_probe(struct platform_device *pdev) ++{ ++ struct s3c_platform_fimc *pdata; ++ struct s3c_fimc_control *ctrl; ++ struct clk *srclk; ++ int ret; ++ ++ ctrl = s3c_fimc_register_controller(pdev); ++ if (!ctrl) { ++ err("cannot register fimc controller\n"); ++ goto err_fimc; ++ } ++ ++ pdata = to_fimc_plat(&pdev->dev); ++ if (pdata->cfg_gpio) ++ pdata->cfg_gpio(pdev); ++ ++ /* fimc source clock */ ++ srclk = clk_get(&pdev->dev, pdata->srclk_name); ++ if (IS_ERR(srclk)) { ++ err("failed to get source clock of fimc\n"); ++ goto err_clk_io; ++ } ++ ++ /* fimc clock */ ++ ctrl->clock = clk_get(&pdev->dev, pdata->clk_name); ++ if (IS_ERR(ctrl->clock)) { ++ err("failed to get fimc clock source\n"); ++ goto err_clk_io; ++ } ++ ++ /* set parent clock */ ++ if (ctrl->clock->set_parent) ++ ctrl->clock->set_parent(ctrl->clock, srclk); ++ ++ /* set clockrate for FIMC interface block */ ++ if (ctrl->clock->set_rate) ++ ctrl->clock->set_rate(ctrl->clock, pdata->clockrate); ++ ++ clk_enable(ctrl->clock); ++ ++ /* things to initialize once */ ++ if (ctrl->id == 0) { ++ ret = s3c_fimc_init_global(pdev); ++ if (ret) ++ goto err_global; ++ } ++ ++ ret = video_register_device(ctrl->vd, VFL_TYPE_GRABBER, ctrl->id); ++ if (ret) { ++ err("cannot register video driver\n"); ++ goto err_video; ++ } ++ ++ info("controller %d registered successfully\n", ctrl->id); ++ ++ return 0; ++ ++err_video: ++ clk_put(s3c_fimc.cam_clock); ++ ++err_global: ++ clk_disable(ctrl->clock); ++ clk_put(ctrl->clock); ++ ++err_clk_io: ++ s3c_fimc_unregister_controller(pdev); ++ ++err_fimc: ++ return -EINVAL; ++ ++} ++ ++static int s3c_fimc_remove(struct platform_device *pdev) ++{ ++ s3c_fimc_unregister_controller(pdev); ++ ++ return 0; ++} ++ ++int s3c_fimc_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ return 0; ++} ++ ++int s3c_fimc_resume(struct platform_device *dev) ++{ ++ return 0; ++} ++ ++static struct platform_driver s3c_fimc_driver = { ++ .probe = s3c_fimc_probe, ++ .remove = s3c_fimc_remove, ++ .suspend = s3c_fimc_suspend, ++ .resume = s3c_fimc_resume, ++ .driver = { ++ .name = "s3c-fimc", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int s3c_fimc_register(void) ++{ ++ platform_driver_register(&s3c_fimc_driver); ++ ++ return 0; ++} ++ ++static void s3c_fimc_unregister(void) ++{ ++ platform_driver_unregister(&s3c_fimc_driver); ++} ++ ++module_init(s3c_fimc_register); ++module_exit(s3c_fimc_unregister); ++ ++MODULE_AUTHOR("Jinsung, Yang "); ++MODULE_DESCRIPTION("Samsung Camera Interface (FIMC) driver"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimc/s3c_fimc_v4l2.c linux-2.6.28.6/drivers/media/video/samsung/fimc/s3c_fimc_v4l2.c +--- linux-2.6.28/drivers/media/video/samsung/fimc/s3c_fimc_v4l2.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimc/s3c_fimc_v4l2.c 2010-04-21 06:38:01.000000000 +0200 +@@ -0,0 +1,763 @@ ++/* linux/drivers/media/video/samsung/s3c_fimc_v4l2.c ++ * ++ * V4L2 interface support file for Samsung Camera Interface (FIMC) driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "s3c_fimc.h" ++ ++static struct v4l2_input s3c_fimc_input_types[] = { ++ { ++ .index = 0, ++ .name = "External Camera Input", ++ .type = V4L2_INPUT_TYPE_CAMERA, ++ .audioset = 1, ++ .tuner = 0, ++ .std = V4L2_STD_PAL_BG | V4L2_STD_NTSC_M, ++ .status = 0, ++ }, ++ { ++ .index = 1, ++ .name = "Memory Input", ++ .type = V4L2_INPUT_TYPE_MEMORY, ++ .audioset = 2, ++ .tuner = 0, ++ .std = V4L2_STD_PAL_BG | V4L2_STD_NTSC_M, ++ .status = 0, ++ } ++}; ++ ++static struct v4l2_output s3c_fimc_output_types[] = { ++ { ++ .index = 0, ++ .name = "Memory Output", ++ .type = V4L2_OUTPUT_TYPE_MEMORY, ++ .audioset = 0, ++ .modulator = 0, ++ .std = 0, ++ }, ++ { ++ .index = 1, ++ .name = "LCD FIFO Output", ++ .type = V4L2_OUTPUT_TYPE_LCDFIFO, ++ .audioset = 0, ++ .modulator = 0, ++ .std = 0, ++ } ++}; ++ ++const static struct v4l2_fmtdesc s3c_fimc_capture_formats[] = { ++ { ++ .index = 0, ++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, ++ .flags = FORMAT_FLAGS_PLANAR, ++ .description = "4:2:0, planar, Y-Cb-Cr", ++ .pixelformat = V4L2_PIX_FMT_YUV420, ++ }, ++ { ++ .index = 1, ++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, ++ .flags = FORMAT_FLAGS_PLANAR, ++ .description = "4:2:2, planar, Y-Cb-Cr", ++ .pixelformat = V4L2_PIX_FMT_YUV422P, ++ ++ }, ++ { ++ .index = 2, ++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, ++ .flags = FORMAT_FLAGS_PACKED, ++ .description = "4:2:2, packed, YCBYCR", ++ .pixelformat = V4L2_PIX_FMT_YUYV, ++ }, ++ { ++ .index = 3, ++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, ++ .flags = FORMAT_FLAGS_PACKED, ++ .description = "4:2:2, packed, CBYCRY", ++ .pixelformat = V4L2_PIX_FMT_UYVY, ++ } ++}; ++ ++const static struct v4l2_fmtdesc s3c_fimc_overlay_formats[] = { ++ { ++ .index = 0, ++ .type = V4L2_BUF_TYPE_VIDEO_OVERLAY, ++ .flags = FORMAT_FLAGS_PACKED, ++ .description = "16 bpp RGB, le", ++ .pixelformat = V4L2_PIX_FMT_RGB565, ++ }, ++ { ++ .index = 1, ++ .type = V4L2_BUF_TYPE_VIDEO_OVERLAY, ++ .flags = FORMAT_FLAGS_PACKED, ++ .description = "24 bpp RGB, le", ++ .pixelformat = V4L2_PIX_FMT_RGB24, ++ }, ++}; ++ ++#define S3C_FIMC_MAX_INPUT_TYPES ARRAY_SIZE(s3c_fimc_input_types) ++#define S3C_FIMC_MAX_OUTPUT_TYPES ARRAY_SIZE(s3c_fimc_output_types) ++#define S3C_FIMC_MAX_CAPTURE_FORMATS ARRAY_SIZE(s3c_fimc_capture_formats) ++#define S3C_FIMC_MAX_OVERLAY_FORMATS ARRAY_SIZE(s3c_fimc_overlay_formats) ++ ++static int s3c_fimc_v4l2_querycap(struct file *filp, void *fh, ++ struct v4l2_capability *cap) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ strcpy(cap->driver, "Samsung FIMC Driver"); ++ strlcpy(cap->card, ctrl->vd->name, sizeof(cap->card)); ++ sprintf(cap->bus_info, "FIMC AHB-bus"); ++ ++ cap->version = 0; ++ cap->capabilities = (V4L2_CAP_VIDEO_OVERLAY | \ ++ V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING); ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_g_fbuf(struct file *filp, void *fh, ++ struct v4l2_framebuffer *fb) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ *fb = ctrl->v4l2.frmbuf; ++ ++ fb->base = ctrl->v4l2.frmbuf.base; ++ fb->capability = V4L2_FBUF_CAP_LIST_CLIPPING; ++ ++ fb->fmt.pixelformat = ctrl->v4l2.frmbuf.fmt.pixelformat; ++ fb->fmt.width = ctrl->v4l2.frmbuf.fmt.width; ++ fb->fmt.height = ctrl->v4l2.frmbuf.fmt.height; ++ fb->fmt.bytesperline = ctrl->v4l2.frmbuf.fmt.bytesperline; ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_s_fbuf(struct file *filp, void *fh, ++ struct v4l2_framebuffer *fb) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ struct v4l2_framebuffer *frmbuf = &(ctrl->v4l2.frmbuf); ++ int i, bpp; ++ ++ for (i = 0; i < S3C_FIMC_MAX_OVERLAY_FORMATS; i++) { ++ if (s3c_fimc_overlay_formats[i].pixelformat == fb->fmt.pixelformat) ++ break; ++ } ++ ++ if (i == S3C_FIMC_MAX_OVERLAY_FORMATS) ++ return -EINVAL; ++ ++ bpp = s3c_fimc_set_output_frame(ctrl, &fb->fmt); ++ ++ frmbuf->base = fb->base; ++ frmbuf->flags = fb->flags; ++ frmbuf->capability = fb->capability; ++ frmbuf->fmt.width = fb->fmt.width; ++ frmbuf->fmt.height = fb->fmt.height; ++ frmbuf->fmt.field = fb->fmt.field; ++ frmbuf->fmt.pixelformat = fb->fmt.pixelformat; ++ frmbuf->fmt.bytesperline = fb->fmt.width * bpp / 8; ++ frmbuf->fmt.sizeimage = fb->fmt.width * frmbuf->fmt.bytesperline; ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_enum_fmt_vid_cap(struct file *filp, void *fh, ++ struct v4l2_fmtdesc *f) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ int index = f->index; ++ ++ if (index >= S3C_FIMC_MAX_CAPTURE_FORMATS) ++ return -EINVAL; ++ ++ memset(f, 0, sizeof(*f)); ++ memcpy(f, ctrl->v4l2.fmtdesc + index, sizeof(*f)); ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_g_fmt_vid_cap(struct file *filp, void *fh, ++ struct v4l2_format *f) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ int size = sizeof(struct v4l2_pix_format); ++ ++ memset(&f->fmt.pix, 0, size); ++ memcpy(&f->fmt.pix, &(ctrl->v4l2.frmbuf.fmt), size); ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_s_fmt_vid_cap(struct file *filp, void *fh, ++ struct v4l2_format *f) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ ctrl->v4l2.frmbuf.fmt = f->fmt.pix; ++ ++ if (f->fmt.pix.priv == V4L2_FMT_IN) ++ s3c_fimc_set_input_frame(ctrl, &f->fmt.pix); ++ else ++ s3c_fimc_set_output_frame(ctrl, &f->fmt.pix); ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_try_fmt_vid_cap(struct file *filp, void *fh, ++ struct v4l2_format *f) ++{ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_try_fmt_overlay(struct file *filp, void *fh, ++ struct v4l2_format *f) ++{ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_overlay(struct file *filp, void *fh, unsigned int i) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ //printk("[CAM]s3c_fimc_v4l2_overlay.\n"); ++ ++ if (i) { ++ if (ctrl->in_type != PATH_IN_DMA) ++ s3c_fimc_init_camera(ctrl); ++ ++ //printk("[CAM]s3c_fimc_init_camera(ctrl);.\n"); ++ FSET_PREVIEW(ctrl); ++ //printk("[CAM]FSET_PREVIEW(ctrl);.\n"); ++ s3c_fimc_start_dma(ctrl); ++ //printk("[CAM]s3c_fimc_start_dma(ctrl);.\n"); ++ } else { ++ s3c_fimc_stop_dma(ctrl); ++ ++ if (ctrl->out_type != PATH_OUT_LCDFIFO) { ++ s3c_fimc_free_output_memory(&ctrl->out_frame); ++ s3c_fimc_set_output_address(ctrl); ++ } ++ } ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_g_ctrl(struct file *filp, void *fh, ++ struct v4l2_control *c) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ ++ switch (c->id) { ++ case V4L2_CID_OUTPUT_ADDR: ++ c->value = frame->addr[c->value].phys_y; ++ break; ++ ++ default: ++ err("invalid control id: %d\n", c->id); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_s_ctrl(struct file *filp, void *fh, ++ struct v4l2_control *c) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ struct s3c_fimc_window_offset *offset = &ctrl->in_cam->offset; ++ ++ switch (c->id) { ++ case V4L2_CID_EFFECT_ORIGINAL: ++ frame->effect.type = EFFECT_ORIGINAL; ++ s3c_fimc_change_effect(ctrl); ++ break; ++ ++ case V4L2_CID_EFFECT_NEGATIVE: ++ frame->effect.type = EFFECT_NEGATIVE; ++ s3c_fimc_change_effect(ctrl); ++ break; ++ ++ case V4L2_CID_EFFECT_EMBOSSING: ++ frame->effect.type = EFFECT_EMBOSSING; ++ s3c_fimc_change_effect(ctrl); ++ break; ++ ++ case V4L2_CID_EFFECT_ARTFREEZE: ++ frame->effect.type = EFFECT_ARTFREEZE; ++ s3c_fimc_change_effect(ctrl); ++ break; ++ ++ case V4L2_CID_EFFECT_SILHOUETTE: ++ frame->effect.type = EFFECT_SILHOUETTE; ++ s3c_fimc_change_effect(ctrl); ++ break; ++ ++ case V4L2_CID_EFFECT_ARBITRARY: ++ frame->effect.type = EFFECT_ARBITRARY; ++ frame->effect.pat_cb = PAT_CB(c->value); ++ frame->effect.pat_cr = PAT_CR(c->value); ++ s3c_fimc_change_effect(ctrl); ++ break; ++ ++ case V4L2_CID_ROTATE_ORIGINAL: ++ frame->flip = FLIP_ORIGINAL; ++ ctrl->rot90 = 0; ++ s3c_fimc_change_rotate(ctrl); ++ break; ++ ++ case V4L2_CID_HFLIP: ++ frame->flip = FLIP_X_AXIS; ++ ctrl->rot90 = 0; ++ s3c_fimc_change_rotate(ctrl); ++ break; ++ ++ case V4L2_CID_VFLIP: ++ frame->flip = FLIP_Y_AXIS; ++ ctrl->rot90 = 0; ++ s3c_fimc_change_rotate(ctrl); ++ break; ++ ++ case V4L2_CID_ROTATE_180: ++ frame->flip = FLIP_XY_AXIS; ++ ctrl->rot90 = 0; ++ s3c_fimc_change_rotate(ctrl); ++ break; ++ ++ case V4L2_CID_ROTATE_90: ++ frame->flip = FLIP_ORIGINAL; ++ ctrl->rot90 = 1; ++ s3c_fimc_change_rotate(ctrl); ++ break; ++ ++ case V4L2_CID_ROTATE_270: ++ frame->flip = FLIP_XY_AXIS; ++ ctrl->rot90 = 1; ++ s3c_fimc_change_rotate(ctrl); ++ break; ++ ++ case V4L2_CID_ROTATE_90_HFLIP: ++ frame->flip = FLIP_X_AXIS; ++ ctrl->rot90 = 1; ++ s3c_fimc_change_rotate(ctrl); ++ break; ++ ++ case V4L2_CID_ROTATE_90_VFLIP: ++ frame->flip = FLIP_Y_AXIS; ++ ctrl->rot90 = 1; ++ s3c_fimc_change_rotate(ctrl); ++ break; ++ ++ case V4L2_CID_ZOOM_IN: ++ if (s3c_fimc_check_zoom(ctrl, c->id) == 0) { ++ offset->h1 += S3C_FIMC_ZOOM_PIXELS; ++ offset->h2 += S3C_FIMC_ZOOM_PIXELS; ++ offset->v1 += S3C_FIMC_ZOOM_PIXELS; ++ offset->v2 += S3C_FIMC_ZOOM_PIXELS; ++ s3c_fimc_restart_dma(ctrl); ++ } ++ ++ break; ++ ++ case V4L2_CID_ZOOM_OUT: ++ if (s3c_fimc_check_zoom(ctrl, c->id) == 0) { ++ offset->h1 -= S3C_FIMC_ZOOM_PIXELS; ++ offset->h2 -= S3C_FIMC_ZOOM_PIXELS; ++ offset->v1 -= S3C_FIMC_ZOOM_PIXELS; ++ offset->v2 -= S3C_FIMC_ZOOM_PIXELS; ++ s3c_fimc_restart_dma(ctrl); ++ } ++ ++ break; ++ ++ case V4L2_CID_AUTO_WHITE_BALANCE: ++ s3c_fimc_i2c_command(ctrl, I2C_CAM_WB, c->value); ++ break; ++ ++ case V4L2_CID_ACTIVE_CAMERA: ++ s3c_fimc_set_active_camera(ctrl, c->value); ++ s3c_fimc_i2c_command(ctrl, I2C_CAM_WB, WB_AUTO); ++ break; ++ ++ case V4L2_CID_TEST_PATTERN: ++ s3c_fimc_set_active_camera(ctrl, S3C_FIMC_TPID); ++ s3c_fimc_set_test_pattern(ctrl, c->value); ++ break; ++ ++ case V4L2_CID_NR_FRAMES: ++ s3c_fimc_set_nr_frames(ctrl, c->value); ++ break; ++ ++ case V4L2_CID_INPUT_ADDR: ++ s3c_fimc_alloc_input_memory(&ctrl->in_frame, \ ++ (dma_addr_t) c->value); ++ s3c_fimc_set_input_address(ctrl); ++ break; ++ ++ case V4L2_CID_INPUT_ADDR_Y: ++ case V4L2_CID_INPUT_ADDR_RGB: ++ s3c_fimc_alloc_y_memory(&ctrl->in_frame, \ ++ (dma_addr_t) c->value); ++ s3c_fimc_set_input_address(ctrl); ++ break; ++ ++ case V4L2_CID_INPUT_ADDR_CB: /* fall through */ ++ case V4L2_CID_INPUT_ADDR_CBCR: ++ s3c_fimc_alloc_cb_memory(&ctrl->in_frame, \ ++ (dma_addr_t) c->value); ++ s3c_fimc_set_input_address(ctrl); ++ break; ++ ++ case V4L2_CID_INPUT_ADDR_CR: ++ s3c_fimc_alloc_cr_memory(&ctrl->in_frame, \ ++ (dma_addr_t) c->value); ++ s3c_fimc_set_input_address(ctrl); ++ break; ++ ++ case V4L2_CID_RESET: ++ ctrl->rot90 = 0; ++ ctrl->in_frame.flip = FLIP_ORIGINAL; ++ ctrl->out_frame.flip = FLIP_ORIGINAL; ++ ctrl->out_frame.effect.type = EFFECT_ORIGINAL; ++ ctrl->scaler.bypass = 0; ++ s3c_fimc_reset(ctrl); ++ break; ++ ++ case V4L2_CID_JPEG_INPUT: /* fall through */ ++ case V4L2_CID_SCALER_BYPASS: ++ ctrl->scaler.bypass = 1; ++ break; ++ ++ default: ++ err("invalid control id: %d\n", c->id); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_streamon(struct file *filp, void *fh, ++ enum v4l2_buf_type i) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ if (i != V4L2_BUF_TYPE_VIDEO_CAPTURE) ++ return -EINVAL; ++ ++ if (ctrl->in_type != PATH_IN_DMA) ++ s3c_fimc_init_camera(ctrl); ++ ++ ctrl->out_frame.skip_frames = 0; ++ FSET_CAPTURE(ctrl); ++ FSET_IRQ_NORMAL(ctrl); ++ s3c_fimc_start_dma(ctrl); ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_streamoff(struct file *filp, void *fh, ++ enum v4l2_buf_type i) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ /*if (i != V4L2_BUF_TYPE_VIDEO_CAPTURE) ++ { ++ printk("[CAM]s3c_fimc_v4l2_streamoff return -1.\n"); ++ return -EINVAL; ++ }*///FIXME! for H.264 encode ++ ++ FSET_STOP(ctrl); ++ UNMASK_USAGE(ctrl); ++ UNMASK_IRQ(ctrl); ++ ++ s3c_fimc_stop_dma(ctrl); ++ s3c_fimc_free_output_memory(&ctrl->out_frame); ++ s3c_fimc_set_output_address(ctrl); ++ printk("[CAM]s3c_fimc_v4l2_streamoff return 0.\n"); ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_g_input(struct file *filp, void *fh, ++ unsigned int *i) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ *i = ctrl->v4l2.input->index; ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_s_input(struct file *filp, void *fh, ++ unsigned int i) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ if (i >= S3C_FIMC_MAX_INPUT_TYPES) ++ return -EINVAL; ++ ++ ctrl->v4l2.input = &s3c_fimc_input_types[i]; ++ ++ if (s3c_fimc_input_types[i].type == V4L2_INPUT_TYPE_CAMERA) ++ ctrl->in_type = PATH_IN_ITU_CAMERA; ++ else ++ ctrl->in_type = PATH_IN_DMA; ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_g_output(struct file *filp, void *fh, ++ unsigned int *i) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ *i = ctrl->v4l2.output->index; ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_s_output(struct file *filp, void *fh, ++ unsigned int i) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ if (i >= S3C_FIMC_MAX_OUTPUT_TYPES) ++ return -EINVAL; ++ ++ ctrl->v4l2.output = &s3c_fimc_output_types[i]; ++ ++ if (s3c_fimc_output_types[i].type == V4L2_OUTPUT_TYPE_MEMORY) ++ ctrl->out_type = PATH_OUT_DMA; ++ else ++ ctrl->out_type = PATH_OUT_LCDFIFO; ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_enum_input(struct file *filp, void *fh, ++ struct v4l2_input *i) ++{ ++ if (i->index >= S3C_FIMC_MAX_INPUT_TYPES) ++ return -EINVAL; ++ ++ memcpy(i, &s3c_fimc_input_types[i->index], sizeof(struct v4l2_input)); ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_enum_output(struct file *filp, void *fh, ++ struct v4l2_output *o) ++{ ++ if ((o->index) >= S3C_FIMC_MAX_OUTPUT_TYPES) ++ return -EINVAL; ++ ++ memcpy(o, &s3c_fimc_output_types[o->index], sizeof(struct v4l2_output)); ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_reqbufs(struct file *filp, void *fh, ++ struct v4l2_requestbuffers *b) ++{ ++ if (b->memory != V4L2_MEMORY_MMAP) { ++ err("V4L2_MEMORY_MMAP is only supported\n"); ++ return -EINVAL; ++ } ++ ++ /* control user input */ ++ if (b->count > 4) ++ b->count = 4; ++ else if (b->count < 1) ++ b->count = 1; ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_querybuf(struct file *filp, void *fh, ++ struct v4l2_buffer *b) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ if (b->type != V4L2_BUF_TYPE_VIDEO_OVERLAY && \ ++ b->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) ++ return -EINVAL; ++ ++ if (b->memory != V4L2_MEMORY_MMAP) ++ return -EINVAL; ++ ++ b->length = ctrl->out_frame.buf_size; ++ ++ /* ++ * NOTE: we use the m.offset as an index for multiple frames out. ++ * Because all frames are not contiguous, we cannot use it as ++ * original purpose. ++ * The index value used to find out which frame user wants to mmap. ++ */ ++ b->m.offset = b->index * PAGE_SIZE; ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_qbuf(struct file *filp, void *fh, ++ struct v4l2_buffer *b) ++{ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_dqbuf(struct file *filp, void *fh, ++ struct v4l2_buffer *b) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ ++ ctrl->out_frame.cfn = s3c_fimc_get_frame_count(ctrl); ++ b->index = (frame->cfn + 2) % frame->nr_frames; ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_cropcap(struct file *filp, void *fh, ++ struct v4l2_cropcap *a) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && ++ a->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) ++ return -EINVAL; ++ ++ /* crop limitations */ ++ ctrl->v4l2.crop_bounds.left = 0; ++ ctrl->v4l2.crop_bounds.top = 0; ++ ctrl->v4l2.crop_bounds.width = ctrl->in_cam->width; ++ ctrl->v4l2.crop_bounds.height = ctrl->in_cam->height; ++ ++ /* crop default values */ ++ ctrl->v4l2.crop_defrect.left = \ ++ (ctrl->in_cam->width - S3C_FIMC_CROP_DEF_WIDTH) / 2; ++ ++ ctrl->v4l2.crop_defrect.top = \ ++ (ctrl->in_cam->height - S3C_FIMC_CROP_DEF_HEIGHT) / 2; ++ ++ ctrl->v4l2.crop_defrect.width = S3C_FIMC_CROP_DEF_WIDTH; ++ ctrl->v4l2.crop_defrect.height = S3C_FIMC_CROP_DEF_HEIGHT; ++ ++ a->bounds = ctrl->v4l2.crop_bounds; ++ a->defrect = ctrl->v4l2.crop_defrect; ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_g_crop(struct file *filp, void *fh, ++ struct v4l2_crop *a) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && ++ a->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) ++ return -EINVAL; ++ ++ a->c = ctrl->v4l2.crop_current; ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_s_crop(struct file *filp, void *fh, ++ struct v4l2_crop *a) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ struct s3c_fimc_camera *cam = ctrl->in_cam; ++ ++ if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && ++ a->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) ++ return -EINVAL; ++ ++ if (a->c.height < 0) ++ return -EINVAL; ++ ++ if (a->c.width < 0) ++ return -EINVAL; ++ ++ if ((a->c.left + a->c.width > cam->width) || \ ++ (a->c.top + a->c.height > cam->height)) ++ return -EINVAL; ++ ++ ctrl->v4l2.crop_current = a->c; ++ ++ cam->offset.h1 = (cam->width - a->c.width) / 2; ++ cam->offset.v1 = (cam->height - a->c.height) / 2; ++ ++ cam->offset.h2 = cam->offset.h1; ++ cam->offset.v2 = cam->offset.v1; ++ ++ s3c_fimc_restart_dma(ctrl); ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_s_parm(struct file *filp, void *fh, ++ struct v4l2_streamparm *a) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) ++ return -EINVAL; ++ ++ if (a->parm.capture.capturemode == V4L2_MODE_HIGHQUALITY) { ++ info("changing to max resolution\n"); ++ s3c_fimc_change_resolution(ctrl, CAM_RES_MAX); ++ } else { ++ info("changing to default resolution\n"); ++ s3c_fimc_change_resolution(ctrl, CAM_RES_DEFAULT); ++ } ++ ++ s3c_fimc_restart_dma(ctrl); ++ ++ return 0; ++} ++ ++const struct v4l2_ioctl_ops s3c_fimc_v4l2_ops = { ++ .vidioc_querycap = s3c_fimc_v4l2_querycap, ++ .vidioc_g_fbuf = s3c_fimc_v4l2_g_fbuf, ++ .vidioc_s_fbuf = s3c_fimc_v4l2_s_fbuf, ++ .vidioc_enum_fmt_vid_cap = s3c_fimc_v4l2_enum_fmt_vid_cap, ++ .vidioc_g_fmt_vid_cap = s3c_fimc_v4l2_g_fmt_vid_cap, ++ .vidioc_s_fmt_vid_cap = s3c_fimc_v4l2_s_fmt_vid_cap, ++ .vidioc_try_fmt_vid_cap = s3c_fimc_v4l2_try_fmt_vid_cap, ++ .vidioc_try_fmt_vid_overlay = s3c_fimc_v4l2_try_fmt_overlay, ++ .vidioc_overlay = s3c_fimc_v4l2_overlay, ++ .vidioc_g_ctrl = s3c_fimc_v4l2_g_ctrl, ++ .vidioc_s_ctrl = s3c_fimc_v4l2_s_ctrl, ++ .vidioc_streamon = s3c_fimc_v4l2_streamon, ++ .vidioc_streamoff = s3c_fimc_v4l2_streamoff, ++ .vidioc_g_input = s3c_fimc_v4l2_g_input, ++ .vidioc_s_input = s3c_fimc_v4l2_s_input, ++ .vidioc_g_output = s3c_fimc_v4l2_g_output, ++ .vidioc_s_output = s3c_fimc_v4l2_s_output, ++ .vidioc_enum_input = s3c_fimc_v4l2_enum_input, ++ .vidioc_enum_output = s3c_fimc_v4l2_enum_output, ++ .vidioc_reqbufs = s3c_fimc_v4l2_reqbufs, ++ .vidioc_querybuf = s3c_fimc_v4l2_querybuf, ++ .vidioc_qbuf = s3c_fimc_v4l2_qbuf, ++ .vidioc_dqbuf = s3c_fimc_v4l2_dqbuf, ++ .vidioc_cropcap = s3c_fimc_v4l2_cropcap, ++ .vidioc_g_crop = s3c_fimc_v4l2_g_crop, ++ .vidioc_s_crop = s3c_fimc_v4l2_s_crop, ++ .vidioc_s_parm = s3c_fimc_v4l2_s_parm, ++}; +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimc/s5k3ba.c linux-2.6.28.6/drivers/media/video/samsung/fimc/s5k3ba.c +--- linux-2.6.28/drivers/media/video/samsung/fimc/s5k3ba.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimc/s5k3ba.c 2009-10-21 19:53:15.000000000 +0200 +@@ -0,0 +1,191 @@ ++/* linux/drivers/media/video/samsung/s5k3ba.c ++ * ++ * Samsung S5K3BA CMOS Image Sensor driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "s3c_fimc.h" ++#include "s5k3ba.h" ++ ++#define S5K3BA_I2C_ADDR 0x5a ++ ++const static u16 ignore[] = { I2C_CLIENT_END }; ++const static u16 normal_addr[] = { (S5K3BA_I2C_ADDR >> 1), I2C_CLIENT_END }; ++const static u16 *forces[] = { NULL }; ++static struct i2c_driver s5k3ba_i2c_driver; ++ ++static struct s3c_fimc_camera s5k3ba_data = { ++ .id = CONFIG_VIDEO_FIMC_CAM_CH, ++ .type = CAM_TYPE_ITU, ++ .mode = ITU_601_YCBCR422_8BIT, ++ .order422 = CAM_ORDER422_8BIT_YCRYCB, ++ .clockrate = 24000000, ++ .width = 800, ++ .height = 600, ++ .offset = { ++ .h1 = 0, ++ .h2 = 0, ++ .v1 = 0, ++ .v2 = 0, ++ }, ++ ++ .polarity = { ++ .pclk = 0, ++ .vsync = 1, ++ .href = 0, ++ .hsync = 0, ++ }, ++ ++ .initialized = 0, ++}; ++ ++static struct i2c_client_address_data addr_data = { ++ .normal_i2c = normal_addr, ++ .probe = ignore, ++ .ignore = ignore, ++ .forces = forces, ++}; ++ ++static void s5k3ba_start(struct i2c_client *client) ++{ ++ int i; ++ ++ for (i = 0; i < S5K3BA_INIT_REGS; i++) { ++ s3c_fimc_i2c_write(client, s5k3ba_init_reg[i].subaddr, \ ++ s5k3ba_init_reg[i].value); ++ } ++} ++ ++static int s5k3ba_attach(struct i2c_adapter *adap, int addr, int kind) ++{ ++ struct i2c_client *c; ++ ++ c = kmalloc(sizeof(*c), GFP_KERNEL); ++ if (!c) ++ return -ENOMEM; ++ ++ memset(c, 0, sizeof(struct i2c_client)); ++ ++ strcpy(c->name, "s5k3ba"); ++ c->addr = addr; ++ c->adapter = adap; ++ c->driver = &s5k3ba_i2c_driver; ++ ++ s5k3ba_data.client = c; ++ ++ info("s5k3ba attached successfully\n"); ++ ++ return i2c_attach_client(c); ++} ++ ++static int s5k3ba_attach_adapter(struct i2c_adapter *adap) ++{ ++ int ret = 0; ++ ++ s3c_fimc_register_camera(&s5k3ba_data); ++ ++ ret = i2c_probe(adap, &addr_data, s5k3ba_attach); ++ if (ret) { ++ err("failed to attach s5k3ba driver\n"); ++ ret = -ENODEV; ++ } ++ ++ return ret; ++} ++ ++static int s5k3ba_detach(struct i2c_client *client) ++{ ++ i2c_detach_client(client); ++ ++ return 0; ++} ++ ++static int s5k3ba_change_resolution(struct i2c_client *client, int res) ++{ ++ switch (res) { ++ case CAM_RES_DEFAULT: /* fall through */ ++ case CAM_RES_MAX: /* fall through */ ++ break; ++ ++ default: ++ err("unexpect value\n"); ++ } ++ ++ return 0; ++} ++ ++static int s5k3ba_change_whitebalance(struct i2c_client *client, enum s3c_fimc_wb_t type) ++{ ++ s3c_fimc_i2c_write(client, 0xfc, 0x0); ++ s3c_fimc_i2c_write(client, 0x30, type); ++ ++ return 0; ++} ++ ++static int s5k3ba_command(struct i2c_client *client, u32 cmd, void *arg) ++{ ++ switch (cmd) { ++ case I2C_CAM_INIT: ++ s5k3ba_start(client); ++ info("external camera initialized\n"); ++ break; ++ ++ case I2C_CAM_RESOLUTION: ++ s5k3ba_change_resolution(client, (int) arg); ++ break; ++ ++ case I2C_CAM_WB: ++ s5k3ba_change_whitebalance(client, (enum s3c_fimc_wb_t) arg); ++ break; ++ ++ default: ++ err("unexpect command\n"); ++ break; ++ } ++ ++ return 0; ++} ++ ++static struct i2c_driver s5k3ba_i2c_driver = { ++ .driver = { ++ .name = "s5k3ba", ++ }, ++ .id = I2C_DRIVERID_S5K3BA, ++ .attach_adapter = s5k3ba_attach_adapter, ++ .detach_client = s5k3ba_detach, ++ .command = s5k3ba_command, ++}; ++ ++static __init int s5k3ba_init(void) ++{ ++ return i2c_add_driver(&s5k3ba_i2c_driver); ++} ++ ++static __init void s5k3ba_exit(void) ++{ ++ i2c_del_driver(&s5k3ba_i2c_driver); ++} ++ ++module_init(s5k3ba_init) ++module_exit(s5k3ba_exit) ++ ++MODULE_AUTHOR("Jinsung, Yang "); ++MODULE_DESCRIPTION("Samsung S5K3BA I2C based CMOS Image Sensor driver"); ++MODULE_LICENSE("GPL"); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimc/s5k3ba.h linux-2.6.28.6/drivers/media/video/samsung/fimc/s5k3ba.h +--- linux-2.6.28/drivers/media/video/samsung/fimc/s5k3ba.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimc/s5k3ba.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,811 @@ ++/* linux/drivers/media/video/samsung/s5k3ba.h ++ * ++ * Header file for Samsung S5K3BA CMOS Image Sensor driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef _S5K3BA_H_ ++#define _S5K3BA_H_ ++ ++typedef struct s3c_fimc_i2c_value { ++ u8 subaddr; ++ u8 value; ++} s5k3ba_t; ++ ++/* init */ ++s5k3ba_t s5k3ba_init_reg[] = ++{ ++ //1. initial setting ++ {0xfc, 0x01}, ++ {0x04, 0x03}, //ARM Clock divider(1/4) ++ ++ //{0xfc, 0x02}, ++ //{0x52, 0x80}, // PLL M ++ //{0x50, 0x14}, //1b // PLL S,P (15fps) ++ //In case of PCLK = 64MHz ++ ++ {0xfc, 0x02}, ++ {0x52, 0x80}, //PLL M M= 128 setting. ++ /* ++ //case 200: ++ {0xfc, 0x02}, ++ {0x50, 0x19}, //PLL S= 0 , P = 25 PCLK=128/2=64Mhz 15 Frmae Setting ++// {0x50, 0x14}, //PLL S= 0 , P = 20 PCLK=128/2=64Mhz 15 Frmae Setting ++// {0x50, 0x59}, //PLL S= 1 , P = 25 PCLK=64/2=32Mhz , 7~8Frame Setting ++ */ ++ //case 266: ++ {0xfc, 0x02}, ++ {0x50, 0x1A}, ++ ++ {0xfc, 0x07}, ++ {0x58, 0x10}, ++ {0x59, 0x00}, ++ {0x5A, 0x00}, ++ {0x5B, 0x6c}, ++ ++ {0xfc, 0xf0}, ++ {0x00, 0x40}, ++ ++ {0xfc, 0x00}, ++ {0x62, 0x02}, ++ {0xbc, 0xe0}, // AWB_AE_DIFF ++ ++ {0xfc, 0x03}, //************************************************* ++ {0x2d, 0x03}, ++ {0xfc, 0x01}, ++ {0x02, 0x02}, // YCbCr Order ++ ++ {0xfc, 0x02}, ++ {0x4a, 0xc1}, // SC type selection ++ {0x37, 0x18}, //16 // SC type global gain ++ {0x47, 0xc4}, // r-ramp by chin ++ ++ {0xfc, 0x01}, //AWB Window Area (except sky) ++ {0xc4, 0x01}, ++ {0xc5, 0x4e}, ++ {0xc7, 0x6e}, ++ ++ {0xfc, 0x02}, ++ {0x30, 0x84}, //Analog offset ++ ++ {0xfc, 0x00}, ++ {0x3d, 0x10}, //AWB Low Y limit ++ ++ {0xfc, 0x02}, ++ {0x3d, 0x06}, //ADLC OFF ++ {0x44, 0x5b}, //clamp enable ++ {0x55, 0x03}, ++ ++ {0xfc, 0x06}, ++ {0x0c, 0x01}, ++ {0x0d, 0x4e}, ++ {0x0f, 0x6e}, ++ ++ {0xfc, 0x00}, ++ {0x78, 0x58}, //AGC MAX (30lux_Micron¹à±âY=60code) ++ ++ {0xfc, 0x02}, ++ {0x45, 0x8c}, //CDS timing_ÀúÁ¶µµ greenish ÇØ°á(15fps) ++ {0x49, 0x80}, // APS Current 2uA ++ ++ {0xfc, 0x01}, ++ {0x25, 0x14}, //10 //Digital Clamp ++ ++ {0xfc, 0x00}, ++ {0x6d, 0x01}, //AE target high (Macbeth white=240) ++ {0x6c, 0x00}, //AE target (Macbeth white=240) ++ //{0x6d, 0x00}, ++ ++ //2. ISP tuning //****************************************** ++ //ISP_tuning ++// {0xfc, 0x00}, ++// {0x01, 0x00}, // I2C hold mode off ++ ++ {0xfc, 0x01}, ++ {0x00, 0x00}, // ISP BPR Off ++ {0x0c, 0x02}, // Full YC ++ {0xc8, 0x19}, // AWB Y Max ++ ++ {0xfc, 0x00}, ++ {0x81, 0x00}, // AWB G gain suppress disable ++ {0x29, 0x04}, ++ {0x2a, 0x00}, ++ {0x2b, 0x04}, // color level ++ {0x2c, 0x00}, ++ ++ {0xfc, 0x07}, ++ {0x11, 0x00}, // G offset ++ {0x37, 0x00}, // Flicker Add ++ ++ {0xfc, 0x00}, ++ {0x72, 0xa0}, // Flicker for 32MHz ++ {0x74, 0x18}, // Flicker ++ {0x73, 0x00}, // Frame AE ++ ++ {0xfc, 0x05}, ++ {0x64, 0x00}, // Darkslice R ++ {0x65, 0x00}, // Darkslice G ++ {0x66, 0x00}, // Darkslice B ++ ++ //Edge ++ {0xfc, 0x05}, ++ {0x2c, 0x0a}, //14 // positive gain ++ {0x30, 0x0a}, //10 // negative edge gain ++ {0x34, 0x1a}, // APTCLP ++ {0x35, 0x10}, //0a // APTSC ++ {0x36, 0x0b}, // ENHANCE ++ {0x3f, 0x00}, // NON-LIN ++ {0x45, 0x30}, // EGREF ++ {0x47, 0x00}, // LLREF ++ {0x48, 0x08}, // by chin ++ {0x49, 0x39}, // CSSEL EGSEL CS_DLY by ++ {0x40, 0x41}, // Y delay ++ ++ //////////////////////////////////// ++ {0xfc, 0x00}, ++ {0x7e, 0xfc}, ++ //s7e8c //NR GrGb off ++ // [7]: BPR [6]:Noise Filter(1D/NR) [4]: GrGb Enable [3]:BPR Data Threshold ++ // [2]: color suppress [1]: Y gain suppress [0]: Digital Clamp ++ /////////////////////////////////// ++ //////////////////////////////////// ++ // GrGb Correction setting ++ {0xfc, 0x01}, ++ {0x44, 0x0c}, ++ ++ //s4400 ++ /// [4]: GrGb full [3]: GrGb On ++ /// [2]: GrGb Rb On ++ {0xfc, 0x0b}, ++ {0x21, 0x00}, // Start AGC ++ {0x22, 0x10}, // AGCMIN ++ {0x23, 0x50}, // AGCMAX ++ {0x24, 0x18}, // G Th AGCMIN(23d) ++ {0x25, 0x52}, // G Th AGCMAX(50d) ++ {0x26, 0x38}, // RB Th AGCMIN ++ {0x27, 0x52}, // RB Th AGCMAX ++ // GrGb Correction setting End ++ ++ /////////////////////////////////// ++ // BPR Setting ++ {0xfc, 0x01}, ++ {0x3f, 0x00}, // setting because S/W bug ++ ++ {0xfc, 0x0b}, ++ {0x0b, 0x00}, // ISP BPR On Start ++ {0x0c, 0x00}, // Th13 AGC Min ++ {0x0d, 0x5a}, // Th13 AGC Max ++ {0x0e, 0x01}, //00 // Th1 Max H for AGCMIN ++ {0x0f, 0xff}, //c0 // Th1 Max L for AGCMIN ++ {0x10, 0x00}, // Th1 Min H for AGCMAX ++ {0x11, 0x10}, //00 // Th1 Min L for AGCMAX ++ {0x12, 0xff}, // Th3 Max H for AGCMIN ++ {0x13, 0xff}, // Th3 Max L for AGCMIN ++ {0x14, 0xff}, // Th3 Min H for AGCMAX ++ {0x15, 0xff}, // Th3 Min L for AGCMAX ++ /////////////////////////////////////////// ++ ++ // NR Setting ++ {0xfc, 0x01}, ++ {0x4b, 0x01}, // NR Enable ++ //s4b00 // NR Enable ++ ++ {0xfc, 0x0b}, ++ {0x28, 0x00}, //NR Start AGC ++ {0x29, 0x00}, // SIG Th AGCMIN H ++ {0x2a, 0x0a}, //14 // SIG Th AGCMIN L ++ {0x2b, 0x00}, // SIG Th AGCMAX H ++ {0x2c, 0x0a}, //14 // SIG Th AGCMAX L ++ {0x2d, 0x00}, // PRE Th AGCMIN H ++ {0x2e, 0xc0}, //64 // PRE Th AGCMIN L(100d) ++ {0x2f, 0x01}, // PRE Th AGCMAX H(300d) ++ {0x30, 0x2c}, // PRE Th AGCMAX L ++ {0x31, 0x00}, // POST Th AGCMIN H ++ {0x32, 0xe0}, //64 // POST Th AGCMIN L(100d) ++ {0x33, 0x01}, // POST Th AGCMAX H(300d) ++ {0x34, 0x2c}, // POST Th AGCMAX L ++ // NR Setting End ++ ++ //////////////////////////////// ++ // Color suppress setting ++ {0xfc, 0x0b}, ++ {0x08, 0x50}, // C suppress AGC MIN ++ {0x09, 0x03}, // C suppress MIN H ++ {0x0a, 0x80}, // C suppress MIN L ++ // C Suppress Setting End ++ ++ {0xfc, 0x05}, ++ {0x4a, 0x00}, //01 // Edge Color Suppress, 9/13 ++ /////////////////////////////// ++ ++ // 1D Y LPF Filter ++ {0xfc, 0x01}, ++ //s05e0 // Default s60 ++ {0x05, 0x60}, // Default s60 ++ //[7]: Y LPF filter On [6]: Clap On ++ ++ {0xfc, 0x0b}, ++ {0x35, 0x00}, // YLPF Start AGC ++ {0x36, 0x50}, // YLPF01 AGCMIN ++ {0x37, 0x50}, // YLPF01 AGCMAX ++ {0x38, 0x00}, // YLPF SIG01 Th AGCMINH ++ {0x39, 0x90}, //00 // YLPF SIG01 Th AGCMINL ++ {0x3a, 0x01}, // YLPF SIG01 Th AGCMAXH ++ {0x3b, 0xa0}, // YLPF SIG01 Th AGCMAXL ++ {0x3c, 0x50}, // YLPF02 AGCMIN ++ {0x3d, 0x50}, // YLPF02 AGCMAX ++ {0x3e, 0x00}, // YLPF SIG02 Th AGCMINH ++ {0x3f, 0xa0}, //00 // YLPF SIG02 Th AGCMINL ++ {0x40, 0x01}, // YLPF SIG02 Th AGCMAXH s73 ++ {0x41, 0xb0}, // YLPF SIG02 Th AGCMAXL ++ // Y LPF Filter setting End ++ ++ // SET EDGE COLOR SUPPRESS AND Y-LPF(¾ö Ã¥ÀÓ´Ô mail Ãß°¡)************************************ ++ {0xfc, 0x05}, ++ {0x42, 0x1F}, ++ {0x43, 0x1F}, ++ {0x44, 0x0E}, ++ {0x45, 0x8C}, //´õ suppresÇÏ°íÀÚÇϸé 5a, 0x ±× ÀÌÇÏ´Â side effect ¶§¹®¿¡ ¾ÈµÊ. ++ {0x46, 0x7A}, ++ {0x47, 0x60}, ++ {0x48, 0x0C}, ++ {0x49, 0x39}, ++ {0x4A, 0x01}, ++ {0x4B, 0xB1}, ++ {0x4C, 0x3B}, ++ {0x4D, 0x14}, ++ //******************************************************************************************* ++ /////////////////////////////////////////// ++ // NR Setting ++ {0xfc, 0x01}, ++ {0x4b, 0x01}, // NR Enable ++ // Set multipliers (which are not suppressed)_(¾ö Ã¥ÀÓ´Ô mail Ãß°¡)************************** ++ {0xfc, 0x01}, ++ {0x48, 0x11}, ++ // Suppressed parameters ++ ++ {0xfc, 0x0B}, ++ {0x21, 0x00}, ++ {0x22, 0x10}, ++ {0x23, 0x60}, ++ {0x24, 0x10}, ++ {0x25, 0x28}, ++ {0x26, 0x08}, ++ {0x27, 0x20}, ++ {0x28, 0x00}, //NR Start AGC ++ {0x29, 0x00}, // SIG Th AGCMIN H ++ {0x2A, 0x02}, // SIG Th AGCMIN L ++ {0x2B, 0x00}, // SIG Th AGCMAX H ++ {0x2C, 0x14}, // SIG Th AGCMAX L ++ {0x2D, 0x03}, // PRE Th AGCMIN H ++ {0x2E, 0x84}, // PRE Th AGCMIN L ++ {0x2F, 0x03}, // PRE Th AGCMAX H ++ {0x30, 0x84}, // PRE Th AGCMAX L ++ {0x31, 0x00}, // POST Th AGCMIN H ++ {0x32, 0x00}, // POST Th AGCMIN L ++ {0x33, 0x00}, // POST Th AGCMAX H ++ {0x34, 0xC8}, // POST Th AGCMAX L ++ {0x35, 0x00}, //1D Y filter setting ++ {0x36, 0x10}, ++ {0x37, 0x50}, ++ {0x38, 0x00}, ++ {0x39, 0x14}, ++ {0x3A, 0x00}, ++ {0x3B, 0x50}, ++ {0x3C, 0x10}, ++ {0x3D, 0x50}, ++ {0x3E, 0x00}, ++ {0x3F, 0x28}, ++ {0x40, 0x00}, ++ {0x41, 0xA0}, ++ //******************************************************************************************* ++ ++ //¾ö Ã¥ÀÓ´Ô mail Ãß°¡ *********************************************************************** ++ // To avoid AWB tracking @ max AGC gain even though AE is unstable state ++ {0xfc, 0x00}, ++ {0xba, 0x50}, // AE Target minus AE Average ++ {0xbb, 0x00}, ++ {0xbc, 0x00}, ++ //******************************************************************************************* ++ ++ //3. AE weight & etc linear ++ // AE Window Weight linear(EVT1)0929 ++ {0xfc, 0x20}, // upper window weight zero ++ {0x60, 0x11}, ++ {0x61, 0x11}, ++ {0x62, 0x11}, ++ {0x63, 0x11}, ++ {0x64, 0x11}, ++ {0x65, 0x11}, ++ {0x66, 0x11}, ++ {0x67, 0x11}, ++ {0x68, 0x11}, ++ {0x69, 0x11}, ++ {0x6a, 0x11}, ++ {0x6b, 0x11}, ++ {0x6c, 0x11}, ++ {0x6d, 0x11}, ++ {0x6e, 0x11}, ++ {0x6f, 0x11}, ++ {0x70, 0x11}, ++ {0x71, 0x11}, ++ {0x72, 0x11}, ++ {0x73, 0x11}, ++ {0x74, 0x11}, ++ {0x75, 0x11}, ++ {0x76, 0x11}, ++ {0x77, 0x11}, ++ {0x78, 0x11}, ++ {0x79, 0x11}, ++ {0x7a, 0x11}, ++ {0x7b, 0x11}, ++ {0x7c, 0x11}, ++ {0x7d, 0x11}, ++ {0x7e, 0x11}, ++ {0x7f, 0x11}, ++ ++ // AE window Weight setting End ++ //hue gain linear // ++ {0xfc, 0x00}, ++ {0x48, 0x40}, ++ {0x49, 0x40}, ++ {0x4a, 0x00}, ++ {0x4b, 0x00}, ++ {0x4c, 0x40}, ++ {0x4d, 0x40}, ++ {0x4e, 0x00}, ++ {0x4f, 0x00}, ++ {0x50, 0x40}, ++ {0x51, 0x40}, ++ {0x52, 0x00}, ++ {0x53, 0x00}, ++ {0x54, 0x40}, ++ {0x55, 0x40}, ++ {0x56, 0x00}, ++ {0x57, 0x00}, ++ {0x58, 0x40}, ++ {0x59, 0x40}, ++ {0x5a, 0x00}, ++ {0x5b, 0x00}, ++ {0x5c, 0x40}, ++ {0x5d, 0x40}, ++ {0x5e, 0x00}, ++ {0x5f, 0x00}, ++ {0x62, 0x00}, //hue enable OFF ++ ++ //4. shading (FlexÇâ 3000K manual shading) ++ {0xfc, 0x09}, ++ // DSP9_SH_WIDTH_H ++ {0x01, 0x06}, ++ {0x02, 0x40}, ++ // DSP9_SH_HEIGHT_H ++ {0x03, 0x04}, ++ {0x04, 0xB0}, ++ {0x05, 0x03}, ++ {0x06, 0x13}, ++ {0x07, 0x02}, ++ {0x08, 0x5A}, ++ {0x09, 0x03}, ++ {0x0A, 0x15}, ++ {0x0B, 0x02}, ++ {0x0C, 0x5B}, ++ {0x0D, 0x03}, ++ {0x0E, 0x0D}, ++ {0x0F, 0x02}, ++ {0x10, 0x5D}, ++ {0x1D, 0x80}, ++ {0x1E, 0x00}, ++ {0x1F, 0x80}, ++ {0x20, 0x00}, ++ {0x23, 0x80}, ++ {0x24, 0x00}, ++ {0x21, 0x80}, ++ {0x22, 0x00}, ++ {0x25, 0x80}, ++ {0x26, 0x00}, ++ {0x27, 0x80}, ++ {0x28, 0x00}, ++ {0x2B, 0x80}, ++ {0x2C, 0x00}, ++ {0x29, 0x80}, ++ {0x2A, 0x00}, ++ {0x2D, 0x80}, ++ {0x2E, 0x00}, ++ {0x2F, 0x80}, ++ {0x30, 0x00}, ++ {0x33, 0x80}, ++ {0x34, 0x00}, ++ {0x31, 0x80}, ++ {0x32, 0x00}, ++ // DSP9_SH_VAL_R0H ++ {0x35, 0x01}, ++ {0x36, 0x00}, ++ {0x37, 0x01}, ++ {0x38, 0x0F}, ++ {0x39, 0x01}, ++ {0x3A, 0x42}, ++ {0x3B, 0x01}, ++ {0x3C, 0x9C}, ++ {0x3D, 0x01}, ++ {0x3E, 0xD0}, ++ {0x3F, 0x02}, ++ {0x40, 0x0F}, ++ {0x41, 0x02}, ++ {0x42, 0x3D}, ++ {0x43, 0x02}, ++ {0x44, 0x5E}, ++ {0x45, 0x01}, ++ {0x46, 0x00}, ++ {0x47, 0x01}, ++ {0x48, 0x0A}, ++ {0x49, 0x01}, ++ {0x4A, 0x2E}, ++ {0x4B, 0x01}, ++ {0x4C, 0x66}, ++ {0x4D, 0x01}, ++ {0x4E, 0x89}, ++ {0x4F, 0x01}, ++ {0x50, 0xB7}, ++ {0x51, 0x01}, ++ {0x52, 0xD8}, ++ {0x53, 0x01}, ++ {0x54, 0xFA}, ++ // DS9_SH_VAL_B0H ++ {0x55, 0x01}, ++ {0x56, 0x00}, ++ {0x57, 0x01}, ++ {0x58, 0x0A}, ++ {0x59, 0x01}, ++ {0x5A, 0x28}, ++ {0x5B, 0x01}, ++ {0x5C, 0x59}, ++ {0x5D, 0x01}, ++ {0x5E, 0x7A}, ++ {0x5F, 0x01}, ++ {0x60, 0xA1}, ++ {0x61, 0x01}, ++ {0x62, 0xC0}, ++ {0x63, 0x01}, ++ {0x64, 0xDC}, ++ // DSP9_SH_M_R2_R1H ++ {0x65, 0x00}, ++ {0x66, 0x9F}, ++ {0x67, 0xE6}, ++ {0x68, 0x02}, ++ {0x69, 0x7F}, ++ {0x6A, 0x9B}, ++ {0x6B, 0x05}, ++ {0x6C, 0x9F}, ++ {0x6D, 0x1E}, ++ {0x6E, 0x07}, ++ {0x6F, 0xA6}, ++ {0x70, 0xCC}, ++ {0x71, 0x09}, ++ {0x72, 0xFE}, ++ {0x73, 0x6E}, ++ {0x74, 0x0C}, ++ {0x75, 0xA6}, ++ {0x76, 0x04}, ++ {0x77, 0x0F}, ++ {0x78, 0x9D}, ++ {0x79, 0x8C}, ++ // DSP9_SH_M_R2_G1H ++ {0x7A, 0x00}, ++ {0x7B, 0x9F}, ++ {0x7C, 0x95}, ++ {0x7D, 0x02}, ++ {0x7E, 0x7E}, ++ {0x7F, 0x54}, ++ {0x80, 0x05}, ++ {0x81, 0x9C}, ++ {0x82, 0x3E}, ++ {0x83, 0x07}, ++ {0x84, 0xA2}, ++ {0x85, 0xE3}, ++ {0x86, 0x09}, ++ {0x87, 0xF9}, ++ {0x88, 0x53}, ++ {0x89, 0x0C}, ++ {0x8A, 0x9F}, ++ {0x8B, 0x8D}, ++ {0x8C, 0x0F}, ++ {0x8D, 0x95}, ++ {0x8E, 0x91}, ++ // DSP9_SH_M_R2_B1H ++ {0x8F, 0x00}, ++ {0x90, 0xA1}, ++ {0x91, 0xFF}, ++ {0x92, 0x02}, ++ {0x93, 0x87}, ++ {0x94, 0xFD}, ++ {0x95, 0x05}, ++ {0x96, 0xB1}, ++ {0x97, 0xFA}, ++ {0x98, 0x07}, ++ {0x99, 0xC0}, ++ {0x9A, 0x79}, ++ {0x9B, 0x0A}, ++ {0x9C, 0x1F}, ++ {0x9D, 0xF6}, ++ {0x9E, 0x0C}, ++ {0x9F, 0xD0}, ++ {0xA0, 0x74}, ++ {0xA1, 0x0F}, ++ {0xA2, 0xD1}, ++ {0xA3, 0xF1}, ++ // DSP9_SH_SUB_RR0H ++ {0xA4, 0x66}, ++ {0xA5, 0x76}, ++ {0xA6, 0x22}, ++ {0xA7, 0x27}, ++ {0xA8, 0x14}, ++ {0xA9, 0x7E}, ++ {0xAA, 0x1F}, ++ {0xAB, 0x86}, ++ {0xAC, 0x1B}, ++ {0xAD, 0x52}, ++ {0xAE, 0x18}, ++ {0xAF, 0x1B}, ++ {0xB0, 0x15}, ++ {0xB1, 0x92}, ++ // DSP9_SH_SUB_RG0H ++ {0xB2, 0x66}, ++ {0xB3, 0xAA}, ++ {0xB4, 0x22}, ++ {0xB5, 0x38}, ++ {0xB6, 0x14}, ++ {0xB7, 0x88}, ++ {0xB8, 0x1F}, ++ {0xB9, 0x97}, ++ {0xBA, 0x1B}, ++ {0xBB, 0x60}, ++ {0xBC, 0x18}, ++ {0xBD, 0x28}, ++ {0xBE, 0x15}, ++ {0xBF, 0x9D}, ++ // DSP9_SH_SUB_RB0H ++ {0xC0, 0x65}, ++ {0xC1, 0x23}, ++ {0xC2, 0x21}, ++ {0xC3, 0xB6}, ++ {0xC4, 0x14}, ++ {0xC5, 0x3A}, ++ {0xC6, 0x1F}, ++ {0xC7, 0x1E}, ++ {0xC8, 0x1A}, ++ {0xC9, 0xF8}, ++ {0xCA, 0x17}, ++ {0xCB, 0xCC}, ++ {0xCC, 0x15}, ++ {0xCD, 0x4A}, ++ {0x00, 0x02}, // shading on ++ ++ {0xfc, 0x00}, ++ {0x79, 0xf4}, ++ {0x7a, 0x09}, ++ ++ //5.color correction ++ //1229 CCM ++ //2.0251 -1.0203 -0.0048 ++ //-0.7080 1.8970 -0.1889 ++ //-0.468 -0.444 1.912 ++ {0xfc, 0x01}, ++ {0x51, 0x08}, //R ++ {0x52, 0x18}, ++ {0x53, 0xfb}, ++ {0x54, 0xec}, ++ {0x55, 0xff}, ++ {0x56, 0xfc}, ++ {0x57, 0xfd}, //G ++ {0x58, 0x2c}, ++ {0x59, 0x07}, ++ {0x5a, 0x95}, ++ {0x5b, 0xff}, ++ {0x5c, 0x3f}, ++ {0x5d, 0xfe}, //B ++ {0x5e, 0x22}, ++ {0x5f, 0xfe}, ++ {0x60, 0x3a}, ++ {0x61, 0x07}, ++ {0x62, 0xa5}, ++ ++ //6.gamma ++ //Gamma ++ {0xfc, 0x01}, ++ // R ++ {0x6F, 0x05}, ++ {0x70, 0x14}, ++ {0x71, 0x3c}, ++ {0x72, 0x96}, ++ {0x73, 0x00}, ++ {0x74, 0x2c}, ++ {0x75, 0xa2}, ++ {0x76, 0xfc}, ++ {0x77, 0x44}, ++ {0x78, 0x56}, ++ {0x79, 0x80}, ++ {0x7A, 0xb7}, ++ {0x7B, 0xed}, ++ {0x7C, 0x16}, ++ {0x7D, 0xab}, ++ {0x7E, 0x3c}, ++ {0x7F, 0x61}, ++ {0x80, 0x83}, ++ {0x81, 0xa4}, ++ {0x82, 0xff}, ++ {0x83, 0xc4}, ++ {0x84, 0xe2}, ++ {0x85, 0xff}, ++ {0x86, 0xff}, ++ // G ++ {0x87, 0x05}, ++ {0x88, 0x14}, ++ {0x89, 0x3c}, ++ {0x8A, 0x96}, ++ {0x8B, 0x00}, ++ {0x8C, 0x2c}, ++ {0x8D, 0xa2}, ++ {0x8E, 0xfc}, ++ {0x8F, 0x44}, ++ {0x90, 0x56}, ++ {0x91, 0x80}, ++ {0x92, 0xb7}, ++ {0x93, 0xed}, ++ {0x94, 0x16}, ++ {0x95, 0xab}, ++ {0x96, 0x3c}, ++ {0x97, 0x61}, ++ {0x98, 0x83}, ++ {0x99, 0xa4}, ++ {0x9A, 0xff}, ++ {0x9B, 0xc4}, ++ {0x9C, 0xe2}, ++ {0x9D, 0xff}, ++ {0x9E, 0xff}, ++ //B ++ {0x9F, 0x05}, ++ {0xA0, 0x10}, ++ {0xA1, 0x30}, ++ {0xA2, 0x70}, ++ {0xA3, 0x00}, ++ {0xA4, 0x2c}, ++ {0xA5, 0xa2}, ++ {0xA6, 0xfc}, ++ {0xA7, 0x44}, ++ {0xA8, 0x56}, ++ ++ {0xA9, 0x80}, ++ {0xAA, 0xb7}, ++ {0xAB, 0xed}, ++ {0xAC, 0x16}, ++ {0xAD, 0xab}, ++ ++ {0xAE, 0x3c}, ++ {0xAF, 0x61}, ++ {0xB0, 0x83}, ++ {0xB1, 0xa4}, ++ {0xB2, 0xff}, ++ ++ {0xB3, 0xc4}, ++ {0xB4, 0xe2}, ++ {0xB5, 0xff}, ++ {0xB6, 0xff}, ++ ++ //7.hue ++ {0xFC, 0x00}, ++ {0x62, 0x00}, // hue auto control off ++ ++ {0xFC, 0x05}, ++ {0x4E, 0x60}, ++ {0x4F, 0xA0}, ++ {0x50, 0x35}, ++ {0x51, 0xA0}, ++ {0x52, 0x20}, ++ {0x53, 0x01}, ++ {0x54, 0xE0}, ++ {0x55, 0xE0}, ++ {0x56, 0x54}, ++ {0x57, 0x20}, ++ {0x58, 0x20}, ++ {0x59, 0xF0}, ++ ++ //8.white point ++ //AWB Start Point ++ {0xfc, 0x07}, ++ {0x05, 0x00}, ++ {0x06, 0x08}, ++ {0x07, 0x1b}, ++ {0x08, 0xf0}, ++ {0x09, 0x00}, // R ++ {0x0a, 0xa8}, ++ {0x0b, 0x00}, // B ++ {0x0c, 0xb0}, ++ {0x0d, 0x00}, // G ++ {0x0e, 0x40}, ++ ++ {0xfc, 0x00}, ++ {0x70, 0x02}, ++ ++ {0x40, 0x8a}, //2000K ++ {0x41, 0xe5}, ++ {0x42, 0x95}, //3100K ++ {0x43, 0xba}, ++ {0x44, 0xbc}, //5100K ++ {0x45, 0x99}, ++ ++ {0x34, 0x24}, ++ {0x35, 0x10}, ++ {0x36, 0x13}, ++ {0x37, 0x04}, ++ {0x38, 0x10}, ++ {0x39, 0x28}, ++ {0x3a, 0x1e}, ++ {0x3b, 0x2a}, ++ ++ {0x31, 0x00}, // skin tone[6], CW delete[5] ++}; ++ ++#if 0 ++s5k3ba_t s5k3ba_vga_reg[] = ++{ ++ /* Only for VGA Mode */ ++ {0xec,0x07}, //bpr by pyo ++ {0x21,0x9c}, ++ {0x22,0x58}, ++ {0xec,0x00}, ++ {0x87,0x00}, ++ {0x86,0x48}, //bpr by pyo ++ ++ {0xec,0x02}, ++ {0x02,0x0d}, //9bit ++ {0x1f,0x07}, //global gain ++ ++ {0xec,0x01}, ++ {0x21,0x40}, ++ {0x22,0x40}, ++ {0x23,0x00}, ++ {0x24,0x00}, ++ ++ {0xec,0x00}, ++ {0x7b,0x00}, ++ {0x73,0x51}, ++ {0x02,0x31}, ++}; ++ ++/* SXGA */ ++s5k3ba_t s5k3ba_sxga_reg[] = ++{ ++ {0xec,0x07}, ++ {0x21,0x90}, ++ {0x22,0x60}, ++ {0xec,0x00}, ++ {0x87,0x00}, ++ {0x86,0x20}, ++ ++ {0xec,0x02}, ++ {0x02,0x0f}, ++ {0x1f,0x0f}, ++ {0xec,0x01}, ++ {0x21,0x50}, ++ {0x22,0x50}, ++ {0x23,0x10}, ++ {0x24,0x10}, ++ {0xec,0x00}, ++ {0x7b,0xff}, ++ {0x73,0x00}, ++ {0x02,0x00}, ++}; ++#endif ++ ++#define S5K3BA_INIT_REGS (sizeof(s5k3ba_init_reg) / sizeof(s5k3ba_init_reg[0])) ++#define S5K3BA_VGA_REGS (sizeof(s5k3ba_vga_reg) / sizeof(s5k3ba_vga_reg[0])) ++#define S5K3BA_SXGA_REGS (sizeof(s5k3ba_sxga_reg) / sizeof(s5k3ba_sxga_reg[0])) ++ ++#endif ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimc/s5k4ba.c linux-2.6.28.6/drivers/media/video/samsung/fimc/s5k4ba.c +--- linux-2.6.28/drivers/media/video/samsung/fimc/s5k4ba.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimc/s5k4ba.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,211 @@ ++/* linux/drivers/media/video/samsung/s5k4ba.c ++ * ++ * Samsung S5K4BA CMOS Image Sensor driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "s3c_fimc.h" ++#include "s5k4ba.h" ++ ++#define S5K4BA_I2C_ADDR 0x5a ++ ++const static u16 ignore[] = { I2C_CLIENT_END }; ++const static u16 normal_addr[] = { (S5K4BA_I2C_ADDR >> 1), I2C_CLIENT_END }; ++const static u16 *forces[] = { NULL }; ++static struct i2c_driver s5k4ba_i2c_driver; ++ ++static struct s3c_fimc_camera s5k4ba_data = { ++ .id = CONFIG_VIDEO_FIMC_CAM_CH, ++ .type = CAM_TYPE_ITU, ++ .mode = ITU_601_YCBCR422_8BIT, ++ .order422 = CAM_ORDER422_8BIT_YCBYCR, ++ ++ /* ++ * 20 fps: 44 MHz ++ * 12 fps: 26 MHz (more stable) ++ */ ++ .clockrate = 44000000, ++ ++ .width = 800, ++ .height = 600, ++ .offset = { ++ .h1 = 0, ++ .h2 = 0, ++ .v1 = 0, ++ .v2 = 0, ++ }, ++ ++ .polarity = { ++ .pclk = 0, ++ .vsync = 1, ++ .href = 0, ++ .hsync = 0, ++ }, ++ ++ .initialized = 0, ++}; ++ ++static struct i2c_client_address_data addr_data = { ++ .normal_i2c = normal_addr, ++ .probe = ignore, ++ .ignore = ignore, ++ .forces = forces, ++}; ++ ++static void s5k4ba_start(struct i2c_client *client) ++{ ++ int i; ++ ++ for (i = 0; i < S5K4BA_INIT_REGS; i++) { ++ s3c_fimc_i2c_write(client, s5k4ba_init_reg[i].subaddr, \ ++ s5k4ba_init_reg[i].value); ++ } ++} ++ ++static int s5k4ba_attach(struct i2c_adapter *adap, int addr, int kind) ++{ ++ struct i2c_client *c; ++ ++ c = kmalloc(sizeof(*c), GFP_KERNEL); ++ if (!c) ++ return -ENOMEM; ++ ++ memset(c, 0, sizeof(struct i2c_client)); ++ ++ strcpy(c->name, "s5k4ba"); ++ c->addr = addr; ++ c->adapter = adap; ++ c->driver = &s5k4ba_i2c_driver; ++ ++ s5k4ba_data.client = c; ++ ++ info("s5k4ba attached successfully\n"); ++ ++ return i2c_attach_client(c); ++} ++ ++static int s5k4ba_attach_adapter(struct i2c_adapter *adap) ++{ ++ int ret = 0; ++ ++ s3c_fimc_register_camera(&s5k4ba_data); ++ ++ ret = i2c_probe(adap, &addr_data, s5k4ba_attach); ++ if (ret) { ++ err("failed to attach s5k4ba driver\n"); ++ ret = -ENODEV; ++ } ++ ++ return ret; ++} ++ ++static int s5k4ba_detach(struct i2c_client *client) ++{ ++ i2c_detach_client(client); ++ ++ return 0; ++} ++ ++static int s5k4ba_change_resolution(struct i2c_client *client, int res) ++{ ++ int i; ++ ++ switch (res) { ++ case CAM_RES_QSVGA: ++ for (i = 0; i < S5K4BA_QSVGA_REGS; i++) { ++ s3c_fimc_i2c_write(client, s5k4ba_qsvga_reg[i].subaddr, ++ s5k4ba_qsvga_reg[i].value); ++ } ++ break; ++ ++ case CAM_RES_MAX: /* fall through */ ++ case CAM_RES_DEFAULT: /* fall through */ ++ case CAM_RES_SVGA: ++ for (i = 0; i < S5K4BA_SVGA_REGS; i++) { ++ s3c_fimc_i2c_write(client, s5k4ba_svga_reg[i].subaddr, ++ s5k4ba_svga_reg[i].value); ++ } ++ break; ++ ++ default: ++ err("unexpect value\n"); ++ } ++ ++ return 0; ++} ++ ++static int s5k4ba_change_whitebalance(struct i2c_client *client, enum s3c_fimc_wb_t type) ++{ ++ s3c_fimc_i2c_write(client, 0xfc, 0x0); ++ s3c_fimc_i2c_write(client, 0x30, type); ++ ++ return 0; ++} ++ ++static int s5k4ba_command(struct i2c_client *client, u32 cmd, void *arg) ++{ ++ switch (cmd) { ++ case I2C_CAM_INIT: ++ s5k4ba_start(client); ++ info("external camera initialized\n"); ++ break; ++ ++ case I2C_CAM_RESOLUTION: ++ s5k4ba_change_resolution(client, (int) arg); ++ break; ++ ++ case I2C_CAM_WB: ++ s5k4ba_change_whitebalance(client, (enum s3c_fimc_wb_t) arg); ++ break; ++ ++ default: ++ err("unexpect command\n"); ++ break; ++ } ++ ++ return 0; ++} ++ ++static struct i2c_driver s5k4ba_i2c_driver = { ++ .driver = { ++ .name = "s5k4ba", ++ }, ++ .id = I2C_DRIVERID_S5K4BA, ++ .attach_adapter = s5k4ba_attach_adapter, ++ .detach_client = s5k4ba_detach, ++ .command = s5k4ba_command, ++}; ++ ++static __init int s5k4ba_init(void) ++{ ++ return i2c_add_driver(&s5k4ba_i2c_driver); ++} ++ ++static __init void s5k4ba_exit(void) ++{ ++ i2c_del_driver(&s5k4ba_i2c_driver); ++} ++ ++module_init(s5k4ba_init) ++module_exit(s5k4ba_exit) ++ ++MODULE_AUTHOR("Jinsung, Yang "); ++MODULE_DESCRIPTION("Samsung S5K4BA I2C based CMOS Image Sensor driver"); ++MODULE_LICENSE("GPL"); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimc/s5k4ba.h linux-2.6.28.6/drivers/media/video/samsung/fimc/s5k4ba.h +--- linux-2.6.28/drivers/media/video/samsung/fimc/s5k4ba.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimc/s5k4ba.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,2284 @@ ++/* linux/drivers/media/video/samsung/s5k4ba.h ++ * ++ * Header file for Samsung S5K4BA CMOS Image Sensor driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef _S5K4BA_H_ ++#define _S5K4BA_H_ ++ ++typedef struct s3c_fimc_i2c_value { ++ u8 subaddr; ++ u8 value; ++} s5k4ba_t; ++ ++/* SVGA init */ ++#if 1 ++s5k4ba_t s5k4ba_init_reg[] = ++{ ++ {0xfc,0x07}, ++ {0x66,0x01}, // Watch Dog Time On ++ {0xfc,0x00}, ++ {0x00,0xAA}, // For EDS Check ++ {0x21,0x03}, // peter0223 ++ {0xfc,0x01}, ++ {0x04,0x01}, // ARM Clock Divider ++ ++ {0xfc,0x02}, ++ {0x30,0x90}, // Analog offset ++ {0x37,0x0d}, // Global Gain ++ {0x2d,0x48}, // Double Shutter ++ {0x60,0x00}, // Blank_Adrs ++ ++ {0x45,0x1e}, //0e// CDS Timing for Average Sub_Sampling ++ {0x47,0x2f}, ++ {0x02,0x0e}, // ADC Resolution ++ {0x3d,0x06}, // Frame ADLC ++ {0x4d,0x08}, // Doubler Volatage ++ {0x54,0x02}, // Double Shutter ++ {0x55,0x1e}, // Line ADLC ++ {0x56,0x30}, // ++ {0x59,0x00}, // LineADLC offset ++ {0x5b,0x08}, // R_Ref_Ctrl ++ {0x44,0x63}, // CLP_EN ++ {0x4A,0x10}, // Clamp Control ++ {0x42,0x02}, // ++ {0x43,0xef}, // ++ ++ //========================================================== ++ // Table Set for Sub-Sampling ++ //========================================================== ++ {0xfc,0x03}, ++ {0x2c,0x00}, // crcb_sel for Sub-Sampling Table ++ {0x05,0x46}, // Output Image Size Set for Capture ++ {0x07,0xb6}, ++ {0x0e,0x04}, ++ {0x12,0x03}, ++ ++ {0xfc,0x04}, ++ {0x32,0x04}, ++ {0x33,0xbc}, ++ ++ {0xfc,0x04}, ++ {0xc5,0x26}, // Output Image Size Set for Preview ++ {0xc7,0x5e}, ++ {0xce,0x04}, ++ {0xd2,0x04}, ++ ++ {0xec,0x06}, //CrCb sel = YCBYCR(0x06) by jsgood ++ {0xc0,0x06}, ++ {0xc1,0x70}, ++ {0xc2,0x02}, ++ {0xc3,0x87}, ++ ++ {0xfc,0x07}, ++ {0x05,0x00}, ++ {0x06,0x00}, ++ {0x07,0x8b}, ++ {0x08,0xf5}, ++ {0x09,0x00}, ++ {0x0a,0xb4}, ++ {0x0b,0x00}, ++ {0x0c,0xea}, ++ {0x0d,0x00}, ++ {0x0e,0x40}, ++ ++ {0xfc,0x00}, ++ {0x70,0x02}, ++ ++ // Jeongyun added still shot cbcr_sel ++ {0xfc,0x03}, ++ {0x2c,0x00}, ++ {0x5c,0x00}, ++ {0x8c,0x00}, ++ {0xbc,0x00}, ++ {0xfc,0x04}, ++ {0x5c,0x00}, ++ ++ ++ //========================================================== ++ // COMMAND SET ++ //========================================================== ++ {0xfc,0x00}, ++ {0x73,0x21}, // Frmae AE Enable peter ++ {0x20,0x02}, // Change AWB Mode ++ ++ {0xfc,0x00}, ++ {0x6c,0xb0}, // AE target ++ {0x6d,0x00}, ++ ++ {0xfc,0x20}, ++ {0x16,0x5a}, // for Prevating AE Hunting ++ ++ {0xfc,0x00}, ++ {0x78,0x6a}, // AGC Max ++ {0xfc,0x20}, ++ {0x16,0x60}, // Frame AE Start ++ ++ {0xfc,0x20}, ++ {0x57,0x18}, // Stable_Frame_AE ++ {0x2C,0x30}, // For Forbidden Area ++ {0x2E,0x00}, // For Forbidden Area ++ {0x14,0x70}, ++ {0x01,0x00}, // Stepless_Off ++ ++ {0xfc,0x07}, ++ {0x11,0x02}, // AWB G Gain offset ++ ++ {0xfc,0x07}, ++ {0x3e,0x0a}, // AWB Cut R max ++ ++ {0xfc,0x01}, ++ {0xc8,0xd0}, // AWB Y Max e0 ++ {0xfc,0x00}, ++ {0x3e,0x20}, //30 AWB Y_min ++ {0x3d,0x10}, // AWB Y_min Low ++ {0xfc,0x22}, ++ {0x8c,0x04}, // AWB Min Y Weight ++ {0x8d,0x16}, // AWB Max Y Weight ++ ++ {0xfc,0x00}, ++ {0x32,0x04}, // AWB moving average 8 frame ++ {0x81,0x10}, // AWB G gain suppress Disable ++ {0xbc,0xf0}, ++ ++ {0x29,0x04}, // Y level H ++ {0x2a,0x00}, // Y level L ++ {0x2b,0x03}, // color level H ++ {0x2c,0xc8}, // color level L ++ ++ {0xfc,0x07}, ++ {0x37,0x00}, // Flicker Add for 32Mhz ++ {0xfc,0x00}, ++ {0x72,0xa0}, // Flicker for 32MHz ++ {0x74,0x08}, // flicker 60Hz Fix ++ ++ {0xfc,0x20}, ++ {0x02,0x02}, // Flicker Dgain Mode ++ ++ {0xfc,0x00}, ++ //{0x23,0x40}, // Mirror Option ++ {0x62,0x0a}, // Mirror Option ++ ++ {0xfc,0x02}, ++ {0x4e,0x00}, // IO current 8mA set ++ {0x4e,0x00}, // IO current 8mA set ++ {0x4e,0x00}, // IO current 8mA set ++ {0x4e,0x00}, // IO current 8mA set ++ {0x4f,0x0a}, // 2a IO current 48mA set ++ {0x4f,0x0a}, // IO current 48mA set ++ {0x4f,0x0a}, // IO current 48mA set ++ {0x4f,0x0a}, // IO current 48mA set ++ ++ {0xfc,0x01}, ++ {0x0c,0x03}, // Full YC Enable ++ //{0x0c,03}, // Full YC Enable ++ //{0x02,02}, // crcb_sel ++ //{0x02,02}, // crcb_sel peter0222 ++ //{0x01,01}, // pclk peter0222 ++ //{0x01,01}, ++ ++ //========================================================== ++ // COLOR MATRIX ++ //========================================================== ++ {0xfc,0x01}, // color matrix ++ {0x51,0x0A}, ++ {0x52,0x42}, ++ {0x53,0xF9}, ++ {0x54,0x80}, ++ {0x55,0x00}, ++ {0x56,0x3D}, ++ ++ {0x57,0xFE}, ++ {0x58,0x0B}, ++ {0x59,0x06}, ++ {0x5A,0x9C}, ++ {0x5B,0xFF}, ++ {0x5C,0x59}, ++ ++ {0x5D,0xFF}, ++ {0x5E,0xD8}, ++ {0x5F,0xFC}, ++ {0x60,0x2E}, ++ {0x61,0x07}, ++ {0x62,0xFA}, ++ ++ //========================================================== ++ // EDGE ENHANCEMENT ++ //========================================================== ++ {0xfc,0x00}, ++ {0x89,0x03}, // Edge Suppress On ++ {0xfc,0x0b}, ++ {0x42,0x50}, // Edge AGC MIN ++ {0x43,0x60}, // Edge AGC MAX ++ {0x45,0x18}, // positive gain AGC MIN ++ {0x49,0x0a}, // positive gain AGC MAX ++ {0x4d,0x18}, // negative gain AGC MIN ++ {0x51,0x0a}, // negative gain AGC MAX ++ ++ {0xfc,0x05}, ++ {0x34,0x20}, // APTCLP ++ {0x35,0x09}, // APTSC ++ {0x36,0x0b}, // ENHANCE ++ {0x3f,0x00}, // NON-LIN ++ {0x42,0x10}, // EGFALL ++ {0x43,0x00}, // HLFALL ++ {0x45,0xa0}, // EGREF ++ {0x46,0x7a}, // HLREF ++ {0x47,0x40}, // LLREF ++ {0x48,0x0c}, ++ {0x49,0x31}, // CSSEL EGSEL CS_DLY ++ ++ {0x40,0x41}, // Y delay ++ ++ //========================================================== ++ // GAMMA ++ //========================================================== - ++ {0xfc,0x01}, ++ ++ {0x6F,0x0A}, // R ++ {0x70,0x1A}, ++ {0x71,0x7A}, ++ {0x72,0xF8}, ++ {0x73,0x00}, ++ ++ {0x74,0xA0}, ++ {0x75,0x18}, ++ {0x76,0x65}, ++ {0x77,0xAD}, ++ {0x78,0x6A}, ++ ++ {0x79,0xE2}, ++ {0x7A,0x12}, ++ {0x7B,0x3D}, ++ {0x7C,0x5A}, ++ {0x7D,0xBF}, ++ ++ {0x7E,0x72}, ++ {0x7F,0x88}, ++ {0x80,0x9D}, ++ {0x81,0xB0}, ++ {0x82,0xFF}, ++ ++ {0x83,0xC0}, ++ {0x84,0xCF}, ++ {0x85,0xDA}, ++ {0x86,0xFC}, ++ ++ {0x87,0x08}, //G ++ {0x88,0x12}, ++ {0x89,0x42}, ++ {0x8A,0xBA}, ++ {0x8B,0x00}, ++ ++ {0x8C,0x75}, ++ {0x8D,0xED}, ++ {0x8E,0x42}, ++ {0x8F,0x80}, ++ {0x90,0x5A}, ++ ++ {0x91,0xB5}, ++ {0x92,0xE5}, ++ {0x93,0x10}, ++ {0x94,0x35}, ++ {0x95,0xAF}, ++ ++ {0x96,0x55}, ++ {0x97,0x70}, ++ {0x98,0x88}, ++ {0x99,0x9D}, ++ {0x9A,0xFF}, ++ ++ {0x9B,0xB1}, ++ {0x9C,0xC4}, ++ {0x9D,0xD5}, ++ {0x9E,0xFC}, ++ ++ {0x9F,0x05}, //B ++ {0xA0,0x18}, ++ {0xA1,0x42}, ++ {0xA2,0xd7}, ++ {0xA3,0x00}, ++ ++ {0xA4,0xB6}, ++ {0xA5,0x3b}, ++ {0xA6,0x88}, ++ {0xA7,0xC8}, ++ {0xA8,0x6A}, ++ ++ {0xA9,0x00}, ++ {0xAA,0x30}, ++ {0xAB,0x58}, ++ {0xAC,0x78}, ++ {0xAD,0xFF}, ++ ++ {0xAE,0x90}, ++ {0xAF,0xA5}, ++ {0xB0,0xB6}, ++ {0xB1,0xC5}, ++ {0xB2,0xFF}, ++ ++ {0xB3,0xD0}, ++ {0xB4,0xD6}, ++ {0xB5,0xDA}, ++ {0xB6,0xFC}, ++ ++ //========================================================== ++ // HUE CONTROL ++ //========================================================== ++ {0xfc,0x00}, ++ {0x48,0x34}, // 2000K ++ {0x49,0x34}, ++ {0x4a,0xf4}, ++ {0x4b,0x00}, ++ {0x4c,0x44}, ++ {0x4d,0x3c}, ++ {0x4e,0xf0}, ++ {0x4f,0x0c}, ++ ++ {0x50,0x34}, // 3000K ++ {0x51,0x34}, ++ {0x52,0xf4}, ++ {0x53,0x00}, ++ {0x54,0x44}, ++ {0x55,0x3c}, ++ {0x56,0xf0}, ++ {0x57,0x0c}, ++ ++ {0x58,0x34}, // 5100K ++ {0x59,0x30}, ++ {0x5a,0x00}, ++ {0x5b,0x04}, ++ {0x5c,0x40}, ++ {0x5d,0x2c}, ++ {0x5e,0xfc}, ++ {0x5f,0x04}, ++ //========================================================== ++ // UPPRE0x0x FUNCTION ++ //========================================================== ++ {0xfc,0x00}, ++ {0x7e,0xf4}, ++ ++ //========================================================== ++ // BPR ++ //========================================================== ++ {0xfc,0x01}, ++ {0x3d,0x10}, ++ ++ {0xfc,0x0b}, ++ {0x0b,0x00}, // ISP BPR On start ++ {0x0c,0x20}, // Th13 AGC Min ++ {0x0d,0x40}, // Th13 AGC Max ++ {0x0e,0x00}, // Th1 Max H for AGCMIN ++ {0x0f,0x20}, // Th1 Max L for AGCMIN ++ {0x10,0x00}, // Th1 Min H for AGCMAX ++ {0x11,0x10}, // Th1 Min L for AGCMAX ++ {0x12,0x00}, // Th3 Max H for AGCMIN ++ {0x13,0x00}, // Th3 Max L for AGCMIN ++ {0x14,0xff}, // Th3 Min H for AGCMAX ++ {0x15,0xff}, // Th3 Min L for AGCMAX ++ {0x16,0x20}, // Th57 AGC Min ++ {0x17,0x40}, // Th57 AGC Max ++ {0x18,0x00}, // Th5 Max H for AGCMIN ++ {0x19,0x00}, // Th5 Max L for AGCMIN ++ {0x1a,0x00}, // Th5 Min H for AGCMAX ++ {0x1b,0x20}, // Th5 Min L for AGCMAX ++ {0x1c,0x00}, // Th7 Max H for AGCMIN ++ {0x1d,0x00}, // Th7 Max L for AGCMIN ++ {0x1e,0x00}, // Th7 Min H for AGCMAX ++ {0x1f,0x20}, // Th7 Min L for AGCMAX ++ ++ //========================================================== ++ // GR/GB CORRECTION ++ //========================================================== ++ {0xfc,0x01}, ++ {0x45,0x0c}, ++ ++ {0xfc,0x0b}, ++ {0x21,0x00}, // start AGC ++ {0x22,0x18}, // AGCMIN ++ {0x23,0x58}, // AGCMAX ++ {0x24,0x0d}, // G Th AGCMIN ++ {0x25,0x30}, // G Th AGCMAX ++ {0x26,0x0d}, // RB Th AGCMIN ++ {0x27,0x30}, // RB Th AGCMAX ++ ++ //========================================================== ++ // NR ++ //========================================================== ++ {0xfc,0x01}, ++ {0x4C,0x01}, // NR Enable ++ {0x49,0x15}, // Sig_Th Mult ++ {0x4B,0x0A}, // Pre_Th Mult ++ ++ {0xfc,0x0b}, ++ {0x28,0x00}, // NR start AGC ++ {0x29,0x00}, // SIG Th AGCMIN H ++ {0x2a,0x14}, // SIG Th AGCMIN L ++ {0x2b,0x00}, // SIG Th AGCMAX H ++ {0x2c,0x14}, // SIG Th AGCMAX L ++ {0x2d,0x00}, // PRE Th AGCMIN H ++ {0x2e,0x90}, // PRE Th AGCMIN L ++ {0x2f,0x01}, // PRE Th AGCMAX H ++ {0x30,0x00}, // PRE Th AGCMAX L ++ {0x31,0x00}, // POST Th AGCMIN H ++ {0x32,0xa0}, // POST Th AGCMIN L ++ {0x33,0x01}, // POST Th AGCMAX H ++ {0x34,0x10}, // POST Th AGCMAX L ++ ++ //========================================================== ++ // 1D-Y/C-SIGMA-LPF ++ //========================================================== ++ {0xfc,0x01}, ++ {0x05,0xc0}, ++ ++ {0xfc,0x0b}, ++ {0x35,0x00}, // YLPF start AGC ++ {0x36,0x40}, // YLPF01 AGCMIN ++ {0x37,0x60}, // YLPF01 AGCMAX ++ {0x38,0x00}, // YLPF SIG01 Th AGCMINH ++ {0x39,0x18}, // YLPF SIG01 Th AGCMINL ++ {0x3a,0x00}, // YLPF SIG01 Th AGCMAXH ++ {0x3b,0x40}, // YLPF SIG01 Th AGCMAXH ++ {0x3c,0x50}, // YLPF02 AGCMIN ++ {0x3d,0x60}, // YLPF02 AGCMAX ++ {0x3e,0x00}, // YLPF SIG02 Th AGCMINH ++ {0x3f,0x30}, // YLPF SIG02 Th AGCMINL ++ {0x40,0x00}, // YLPF SIG02 Th AGCMAXH ++ {0x41,0x40}, // YLPF SIG02 Th AGCMAXH ++ {0xd4,0x40}, // CLPF AGCMIN ++ {0xd5,0x60}, // CLPF AGCMAX ++ {0xd6,0xb0}, // CLPF SIG01 Th AGCMIN ++ {0xd7,0xf0}, // CLPF SIG01 Th AGCMAX ++ {0xd8,0xb0}, // CLPF SIG02 Th AGCMIN ++ {0xd9,0xf0}, // CLPF SIG02 Th AGCMAX ++ ++ //========================================================== ++ // COLOR SUPPRESS ++ //========================================================== ++ {0xfc,0x0b}, ++ {0x08,0x58}, // Color suppress AGC MIN ++ {0x09,0x03}, // Color suppress MIN H ++ {0x0a,0x80}, // Color suppress MIN L ++ ++ //========================================================== ++ // SHADING ++ //========================================================== ++ {0xfc,0x09}, ++ //Shading file for 3BAFX ++ //s90000// shading off ++ // DSP9_SH_WIDTH_H ++ {0x01,0x06}, ++ {0x02,0x40}, ++ // DSP9_SH_HEIGHT_H ++ {0x03,0x04}, ++ {0x04,0xB0}, ++ // DSP9_SH_XCH_R ++ {0x05,0x03}, ++ {0x06,0x1A}, ++ {0x07,0x02}, ++ {0x08,0x4E}, ++ // DSP9_SH_XCH_G ++ {0x09,0x03}, ++ {0x0A,0x27}, ++ {0x0B,0x02}, ++ {0x0C,0x11}, ++ // DSP9_SH_XCH_B ++ {0x0D,0x03}, ++ {0x0E,0x15}, ++ {0x0F,0x01}, ++ {0x10,0xE3}, ++ // DSP9_SH_Del_eH_R ++ {0x1D,0x85}, ++ {0x1E,0x55}, ++ {0x1F,0x77}, ++ {0x20,0x9E}, ++ {0x23,0x7F}, ++ {0x24,0xE6}, ++ {0x21,0x7F}, ++ {0x22,0xE6}, ++ // DSP9_SH_Del_eH_G ++ {0x25,0x82}, ++ {0x26,0x9A}, ++ {0x27,0x78}, ++ {0x28,0xC0}, ++ {0x2B,0x76}, ++ {0x2C,0x07}, ++ {0x29,0x86}, ++ {0x2A,0x09}, ++ // DSP9_SH_Del_eH_B ++ {0x2D,0x85}, ++ {0x2E,0x55}, ++ {0x2F,0x75}, ++ {0x30,0x6D}, ++ {0x33,0x74}, ++ {0x34,0xA2}, ++ {0x31,0x84}, ++ {0x32,0xA2}, ++ // DSP9_SH_VAL_R0H ++ {0x35,0x01}, ++ {0x36,0x01}, ++ {0x37,0x01}, ++ {0x38,0x14}, ++ {0x39,0x01}, ++ {0x3A,0x45}, ++ {0x3B,0x01}, ++ {0x3C,0x8A}, ++ {0x3D,0x01}, ++ {0x3E,0xA3}, ++ {0x3F,0x01}, ++ {0x40,0xB9}, ++ {0x41,0x01}, ++ {0x42,0xD9}, ++ {0x43,0x01}, ++ {0x44,0xF6}, ++ // DSP9_SH_VAL_G0H ++ {0x45,0x01}, ++ {0x46,0x00}, ++ {0x47,0x01}, ++ {0x48,0x0E}, ++ {0x49,0x01}, ++ {0x4A,0x34}, ++ {0x4B,0x01}, ++ {0x4C,0x68}, ++ {0x4D,0x01}, ++ {0x4E,0x76}, ++ {0x4F,0x01}, ++ {0x50,0x94}, ++ {0x51,0x01}, ++ {0x52,0xAB}, ++ {0x53,0x01}, ++ {0x54,0xC3}, ++ // DSP9_SH_VAL_B0H ++ {0x55,0x01}, ++ {0x56,0x00}, ++ {0x57,0x01}, ++ {0x58,0x0C}, ++ {0x59,0x01}, ++ {0x5A,0x2B}, ++ {0x5B,0x01}, ++ {0x5C,0x5D}, ++ {0x5D,0x01}, ++ {0x5E,0x70}, ++ {0x5F,0x01}, ++ {0x60,0x8A}, ++ {0x61,0x01}, ++ {0x62,0xA1}, ++ {0x63,0x01}, ++ {0x64,0xB3}, ++ // DSP9_SH_M_R2_R1H ++ {0x65,0x00}, ++ {0x66,0x98}, ++ {0x67,0x2C}, ++ {0x68,0x02}, ++ {0x69,0x60}, ++ {0x6A,0xB0}, ++ {0x6B,0x05}, ++ {0x6C,0x59}, ++ {0x6D,0x8C}, ++ {0x6E,0x07}, ++ {0x6F,0x48}, ++ {0x70,0x1B}, ++ {0x71,0x09}, ++ {0x72,0x82}, ++ {0x73,0xC0}, ++ {0x74,0x0C}, ++ {0x75,0x09}, ++ {0x76,0x7B}, ++ {0x77,0x0E}, ++ {0x78,0xDC}, ++ {0x79,0x4D}, ++ // DSP9_SH_M_R2_G1H ++ {0x7A,0x00}, ++ {0x7B,0xAD}, ++ {0x7C,0x76}, ++ {0x7D,0x02}, ++ {0x7E,0xB5}, ++ {0x7F,0xD7}, ++ {0x80,0x06}, ++ {0x81,0x19}, ++ {0x82,0x23}, ++ {0x83,0x08}, ++ {0x84,0x4C}, ++ {0x85,0xE2}, ++ {0x86,0x0A}, ++ {0x87,0xD7}, ++ {0x88,0x5C}, ++ {0x89,0x0D}, ++ {0x8A,0xB8}, ++ {0x8B,0x90}, ++ {0x8C,0x10}, ++ {0x8D,0xF0}, ++ {0x8E,0x7F}, ++ // DSP9_SH_M_R2_B1H ++ {0x8F,0x00}, ++ {0x90,0xC1}, ++ {0x91,0xD0}, ++ {0x92,0x03}, ++ {0x93,0x07}, ++ {0x94,0x3F}, ++ {0x95,0x06}, ++ {0x96,0xD0}, ++ {0x97,0x4F}, ++ {0x98,0x09}, ++ {0x99,0x46}, ++ {0x9A,0x32}, ++ {0x9B,0x0C}, ++ {0x9C,0x1C}, ++ {0x9D,0xFE}, ++ {0x9E,0x0F}, ++ {0x9F,0x54}, ++ {0xA0,0xB1}, ++ {0xA1,0x12}, ++ {0xA2,0xED}, ++ {0xA3,0x4C}, ++ // DSP9_SH_SUB_RR0H ++ {0xA4,0x6B}, ++ {0xA5,0xAA}, ++ {0xA6,0x23}, ++ {0xA7,0xE3}, ++ {0xA8,0x15}, ++ {0xA9,0x88}, ++ {0xAA,0x21}, ++ {0xAB,0x20}, ++ {0xAC,0x1C}, ++ {0xAD,0xB6}, ++ {0xAE,0x19}, ++ {0xAF,0x55}, ++ {0xB0,0x16}, ++ {0xB1,0xAA}, ++ // DSP9_SH_SUB_RG0H ++ {0xB2,0x5E}, ++ {0xB3,0x74}, ++ {0xB4,0x1F}, ++ {0xB5,0x7C}, ++ {0xB6,0x12}, ++ {0xB7,0xE4}, ++ {0xB8,0x1D}, ++ {0xB9,0x10}, ++ {0xBA,0x19}, ++ {0xBB,0x30}, ++ {0xBC,0x16}, ++ {0xBD,0x39}, ++ {0xBE,0x13}, ++ {0xBF,0xE2}, ++ // DSP9_SH_SUB_RB0H ++ {0xC0,0x54}, ++ {0xC1,0x89}, ++ {0xC2,0x1C}, ++ {0xC3,0x2D}, ++ {0xC4,0x10}, ++ {0xC5,0xE8}, ++ {0xC6,0x1A}, ++ {0xC7,0x02}, ++ {0xC8,0x16}, ++ {0xC9,0x8A}, ++ {0xCA,0x13}, ++ {0xCB,0xE4}, ++ {0xCC,0x11}, ++ {0xCD,0xCC}, ++ ++ {0x00,0x02}, // {0xhading on ++ ++ //========================================================== ++ // X-SHADING ++ //========================================================== ++ {0xfc,0x1B}, ++ {0x80,0x01}, ++ {0x81,0x00}, ++ {0x82,0x4C}, ++ {0x83,0x00}, ++ {0x84,0x86}, ++ {0x85,0x03}, ++ {0x86,0x5E}, ++ {0x87,0x00}, ++ {0x88,0x07}, ++ {0x89,0xA4}, ++ {0x90,0x00}, ++ {0x91,0x12}, ++ {0x92,0x00}, ++ {0x93,0x12}, ++ {0x94,0x00}, ++ {0x95,0x12}, ++ {0x96,0x00}, ++ {0x97,0x12}, ++ {0x98,0x00}, ++ {0x99,0x12}, ++ {0x9A,0x00}, ++ {0x9B,0x12}, ++ {0x9C,0x00}, ++ {0x9D,0x12}, ++ {0x9E,0x00}, ++ {0x9F,0x12}, ++ {0xA0,0x00}, ++ {0xA1,0x12}, ++ {0xA2,0x00}, ++ {0xA3,0x12}, ++ {0xA4,0x00}, ++ {0xA5,0x12}, ++ {0xA6,0x00}, ++ {0xA7,0x12}, ++ {0xA8,0x00}, ++ {0xA9,0x12}, ++ {0xAA,0x00}, ++ {0xAB,0x12}, ++ {0xAC,0x00}, ++ {0xAD,0x12}, ++ {0xAE,0x00}, ++ {0xAF,0x12}, ++ {0xB0,0x00}, ++ {0xB1,0x12}, ++ {0xB2,0x00}, ++ {0xB3,0x12}, ++ {0xB4,0x00}, ++ {0xB5,0x12}, ++ {0xB6,0x00}, ++ {0xB7,0x15}, ++ {0xB8,0x00}, ++ {0xB9,0x12}, ++ {0xBA,0x00}, ++ {0xBB,0x12}, ++ {0xBC,0x00}, ++ {0xBD,0x12}, ++ {0xBE,0x00}, ++ {0xBF,0x12}, ++ {0xC0,0x00}, ++ {0xC1,0x12}, ++ {0xC2,0x00}, ++ {0xC3,0x12}, ++ {0xC4,0x00}, ++ {0xC5,0x12}, ++ {0xC6,0x00}, ++ {0xC7,0x12}, ++ {0xC8,0x00}, ++ {0xC9,0x12}, ++ {0xCA,0x00}, ++ {0xCB,0x12}, ++ {0xCC,0x00}, ++ {0xCD,0x12}, ++ {0xCE,0x00}, ++ {0xCF,0x12}, ++ {0xD0,0x00}, ++ {0xD1,0x12}, ++ {0xD2,0x00}, ++ {0xD3,0x12}, ++ {0xD4,0x00}, ++ {0xD5,0x12}, ++ // x-shading temp. correlation factor ++ {0xfc,0x0b}, ++ {0xda,0x00}, // t0(3100K) ++ {0xdb,0xac}, ++ {0xdc,0x01}, // tc(5100K) ++ {0xdd,0x30}, // default eeh ++ ++ {0xfc,0x00}, ++ {0x81,0x10}, // xshading tem ++ ++ {0xfc,0x1b}, ++ {0x80,0x01}, // X-Shading On ++ ++ //========================================================== ++ // AE WINDOW WEIGHT ++ //========================================================== ++ {0xfc,0x00}, ++ {0x03,0x4b}, // AE Suppress On ++ ++ {0xfc,0x06}, ++ {0x01,0x35}, // UXGA AE Window ++ {0x03,0xc2}, ++ {0x05,0x48}, ++ {0x07,0xb8}, ++ {0x31,0x2a}, // Subsampling AE Window ++ {0x33,0x61}, ++ {0x35,0x28}, ++ {0x37,0x5c}, ++ {0x39,0x28}, ++ {0x3B,0x5A}, ++ {0x3D,0x10}, // 1c ++ {0x3F,0x44}, ++ ++ {0xfc,0x20}, ++ {0x60,0x11}, ++ {0x61,0x11}, ++ {0x62,0x11}, ++ {0x63,0x11}, ++ {0x64,0x11}, ++ {0x65,0x22}, ++ {0x66,0x22}, ++ {0x67,0x11}, ++ {0x68,0x11}, ++ {0x69,0x33}, ++ {0x6a,0x33}, ++ {0x6b,0x11}, ++ {0x6c,0x12}, ++ {0x6d,0x55}, ++ {0x6e,0x55}, ++ {0x6f,0x21}, ++ {0x70,0x13}, ++ {0x71,0x55}, ++ {0x72,0x55}, ++ {0x73,0x31}, ++ {0x74,0x33}, ++ {0x75,0x33}, ++ {0x76,0x33}, ++ {0x77,0x33}, ++ ++ //========================================================== ++ // SAIT AWB ++ //========================================================== ++ //================================= ++ // White Point ++ //================================= ++ {0xfc,0x22}, // White Point (For Hue Control & MWB) ++ {0x01,0xD0}, // D65 ++ {0x03,0x9B}, ++ {0x05,0xC0}, // 5000K ++ {0x07,0xB8}, ++ {0x09,0xA7}, // CWF ++ {0x0b,0xDC}, ++ {0x0d,0x98}, // 3000K ++ {0x0f,0xE0}, ++ {0x11,0x85}, // A ++ {0x12,0x00}, ++ {0x13,0xF6}, ++ {0x15,0x80}, // 2000K ++ {0x16,0x01}, ++ {0x17,0x00}, ++ ++ //================================= ++ // Basic Setting ++ //================================= ++ {0xfc,0x22}, ++ {0xA0,0x01}, ++ {0xA1,0x3F}, ++ {0xA2,0x0E}, ++ {0xA3,0x65}, ++ {0xA4,0x07}, ++ {0xA5,0xF4}, ++ {0xA6,0x11}, ++ {0xA7,0xC8}, ++ {0xA9,0x02}, ++ {0xAA,0x43}, ++ {0xAB,0x26}, ++ {0xAC,0x1F}, ++ {0xAD,0x02}, ++ {0xAE,0x2C}, ++ {0xAF,0x19}, ++ {0xB0,0x0F}, ++ ++ {0x94,0x3C}, ++ {0x95,0xCC}, ++ {0x96,0x5C}, ++ {0x97,0x4D}, ++ {0xD0,0xA8}, ++ {0xD1,0x29}, ++ {0xD2,0x39}, ++ {0xD3,0x22}, ++ {0xD4,0x30}, ++ {0xDB,0x29}, ++ {0xDC,0x7E}, ++ {0xDD,0x22}, ++ ++ {0xE7,0x00}, ++ {0xE8,0xca}, ++ {0xE9,0x00}, ++ {0xEA,0x62}, ++ {0xEB,0x00}, ++ {0xEC,0x00}, ++ {0xEE,0x97}, ++ ++ //================================= ++ // Pixel Filter Setting ++ //================================= ++ {0xFC,0x07}, ++ {0x95,0x8F}, ++ ++ {0xfc,0x01}, ++ {0xD3,0x4B}, ++ {0xD4,0x00}, ++ {0xD5,0x38}, ++ {0xD6,0x00}, ++ {0xD7,0x60}, ++ {0xD8,0x00}, ++ {0xD9,0x4E}, ++ {0xDA,0x00}, ++ {0xDB,0x27}, ++ {0xDC,0x15}, ++ {0xDD,0x23}, ++ {0xDE,0xAD}, ++ {0xDF,0x24}, ++ {0xE0,0x01}, ++ {0xE1,0x17}, ++ {0xE2,0x4A}, ++ {0xE3,0x36}, ++ {0xE4,0x40}, ++ {0xE5,0x40}, ++ {0xE6,0x40}, ++ {0xE7,0x40}, ++ {0xE8,0x30}, ++ {0xE9,0x3D}, ++ {0xEA,0x17}, ++ {0xEB,0x01}, ++ ++ //================================= ++ // Polygon AWB Region Tune ++ //================================= ++ {0xfc,0x22}, ++ {0x18,0x00}, // 1 ++ {0x19,0x5a}, ++ {0x1a,0xf8}, ++ {0x1b,0x00}, // 2 ++ {0x1c,0x59}, ++ {0x1d,0xCC}, ++ {0x1e,0x00}, // 3 ++ {0x1f,0x74}, ++ {0x20,0xB3}, ++ {0x21,0x00}, // 4 ++ {0x22,0x86}, ++ {0x23,0xA2}, ++ {0x24,0x00}, // 5 ++ {0x25,0x94}, ++ {0x26,0x89}, ++ {0x27,0x00}, // 6 ++ {0x28,0xA6}, ++ {0x29,0x76}, ++ {0x2A,0x00}, // 7 ++ {0x2B,0xd0}, ++ {0x2C,0x5e}, ++ {0x2D,0x00}, // 8 ++ {0x2E,0xfa}, ++ {0x2F,0x47}, ++ {0x30,0x00}, // 9 ++ {0x31,0xfD}, ++ {0x32,0x5D}, ++ {0x33,0x00}, // 10 ++ {0x34,0xBB}, ++ {0x35,0x7c}, ++ {0x36,0x00}, // 11 ++ {0x37,0xAD}, ++ {0x38,0x88}, ++ {0x39,0x00}, // 12 ++ {0x3A,0x9A}, ++ {0x3B,0xA3}, ++ {0x3C,0x00}, // 13 ++ {0x3D,0x7C}, ++ {0x3E,0xDD}, ++ {0x3F,0x00}, // 14 ++ {0x40,0x00}, ++ {0x41,0x00}, ++ ++ //================================= ++ // Moving Equation Weight ++ //================================= ++ {0xfc,0x22}, ++ {0x98,0x07}, ++ ++ //================================= ++ // EIT Threshold ++ //================================= ++ {0xfc,0x22}, ++ {0xb1,0x00}, // {0xunny ++ {0xb2,0x03}, ++ {0xb3,0x00}, ++ {0xb4,0xc1}, ++ ++ {0xb5,0x00}, // Cloudy ++ {0xb6,0x05}, ++ {0xb7,0xc9}, ++ {0xb9,0x81}, ++ ++ {0xd7,0x00}, // Shade ++ {0xd8,0x35}, ++ {0xd9,0x20}, ++ {0xda,0x81}, ++ ++ //================================= ++ // Gain Offset ++ //================================= ++ {0xfc,0x00}, ++ {0x79,0xF9}, ++ {0x7A,0x02}, // Global AWB gain off{0xet ++ ++ {0xfc,0x22}, ++ {0x58,0xf6}, // D65 R Off{0xet ++ {0x59,0xff}, // D65 B Off{0xet ++ {0x5A,0xfa}, // 5000K R Off{0xet ++ {0x5B,0xFe}, // 5000K B Off{0xet ++ {0x5C,0xfb}, // CWF R Off{0xet ++ {0x5D,0xFe}, // CWF B Off{0xet ++ {0x5E,0xfb}, // 3000K R Off{0xet ++ {0x5F,0xFb}, // 3000K B Off{0xet ++ {0x60,0xfb}, // A R Off0xet ++ {0x61,0xfb}, // A B Off0xet ++ {0x62,0xfb}, // 2000K R Off0xet ++ {0x63,0xfb}, // 2000K B Off0xet ++ ++ {0xde,0x00}, // LARGE OBJECT BUG FIX ++ {0xf0,0x6a}, // RB Ratio ++ //================================= ++ // Green Stablity Enhance ++ //================================= ++ {0xfc,0x22}, ++ {0xb9,0x00}, ++ {0xba,0x00}, ++ {0xbb,0x00}, ++ {0xbc,0x00}, ++ {0xe5,0x01}, ++ {0xe6,0xff}, ++ ++ {0xbd,0x90}, ++ ++ //========================================================== ++ // Special Effect ++ //========================================================== ++ {0xfc,0x07}, // Special Effect ++ {0x30,0xc0}, ++ {0x31,0x20}, ++ {0x32,0x40}, ++ {0x33,0xc0}, ++ {0x34,0x00}, ++ {0x35,0xb0}, ++ ++ {0xfc,0x00}, ++ {0x73,0x21}, // Frmae AE Enable}, peter0223 À§Ä¡ º¯°æ ++ ++ {0xfc,0x04}, ++ {0xc0,0x06}, ++ {0xc1,0x70}, ++ {0xFF,0xFF} // REGISTER END ++}; ++#else ++s5k4ba_t s5k4ba_svga[] = ++{ ++//========================================================== ++// CAMERA INITIAL (Analog & Clock Setting) ++//========================================================== ++ {0xfc, 0x07}, ++ {0x66, 0x01},// WDT ++ {0xfc, 0x00}, ++ {0x00, 0xaa},// For EDS Check ++ {0x21, 0x03},// peter0223 added ++ ++ {0xfc, 0x01}, ++ {0x04, 0x01},// ARM Clock Divider ++ ++ {0xfc, 0x02},// Analog setting ++ {0x55, 0x1e},// LineADLC on(s551a), off(s550a) ++ {0x56, 0x10},// BPR 16code ++ {0x30, 0x82},// Analog offset (capture =?h) ++ {0x37, 0x25},// Global Gain (default:31) ++ ++ {0x57, 0x80},// // LineADLC Roffset ++ {0x58, 0x80},//89 //90 // LineADLC Goffset ++ {0x59, 0x80},//90 // LineADLC offset don't care ++ ++ {0x44, 0x64},//clamp en[6]=1 on ++ {0x4a, 0x30},//clamp level 0011h [7]~[4] ++ ++ {0x2d, 0x48},// double shutter (default:00) ++ {0x4d, 0x08},// Voltage doubler (default:04) ++ {0x4e, 0x00},// IO current 8mA set ++ {0x4f, 0x8a},// IO current 48mA set ++ ++ {0x66, 0x41},// 1st comp current 2uA ++ {0x43, 0xef},// ec_comp ++ {0x62, 0x60},// LD control , CFPN_EN off ++ ++//========================================================== ++// Table Set for Sub-Sampling ++//========================================================== ++ {0xfc, 0x03}, ++ {0x01, 0x60}, ++ //{0x2e, 0x00}, ++ {0x2e, 0x03},//DHL ++ {0x05, 0x46},// Output Image Size Set for Capture ++ {0x07, 0xb6}, ++ {0x0e, 0x04}, ++ {0x12, 0x03}, ++ ++ {0xfc, 0x04}, ++ {0xc5, 0x26},// Output Image Size Set for Preview ++ {0xc7, 0x5e}, ++ {0xce, 0x04}, ++ {0xd2, 0x04}, ++ //{0xee, 0x00},//DHL ++ {0xee, 0x01}, ++ {0xc0, 0x06}, ++ {0xc1, 0x60},//frame_H ++ {0xc2, 0x02}, ++ {0xc3, 0x8d},//frame_V ++ ++ {0xfc, 0x07}, ++ {0x05, 0x00}, ++ {0x06, 0x00}, ++ {0x07, 0x8b}, ++ {0x08, 0xf5}, ++ {0x09, 0x00}, ++ {0x0a, 0xb4}, ++ {0x0b, 0x00}, ++ {0x0c, 0xea}, ++ {0x0d, 0x00}, ++ {0x0e, 0x40}, ++ ++#if 1 ++//========================================================== ++// COMMAND SET ++//========================================================== ++ {0xfc, 0x00}, ++ {0x70, 0x02}, ++ ++ {0xfc, 0x00}, ++ {0x73, 0x11},//21 Frmae AE Enable, peter0223 ++ {0x20, 0x02},// Change AWB Mode ++ ++ {0xfc, 0x00}, ++ {0x78, 0x6a},// AGC Max ++ ++ {0xfc, 0x00}, ++ {0x6c, 0xa0},// AE target ++ {0x6d, 0x00}, ++ ++ {0xfc, 0x20}, ++ {0x16, 0x5a},// AGC frame AE start _for Prevating AE Hunting ++ {0x57, 0x18},// Stable_Frame_AE ++ ++ {0xfc, 0x00}, ++ {0x83, 0x06},//low condition shutter off // Double shutter off ++ ++ {0xfc, 0x0b}, ++ {0x5c, 0x69},//70 //AGC value to start shutter on/off suppress ++ {0x5d, 0x65},//60 //AGC value to start double shutter on/off suppress ++ ++ {0xfc, 0x20}, ++ {0x25, 0x00},// CINTR Min ++ {0x2a, 0x01},// forbidden ++ {0x2b, 0x02},// For Forbidden Area ++ {0x2c, 0x0a}, ++ {0x2d, 0x00},// For Forbidden Area ++ {0x2e, 0x00}, ++ {0x2f, 0x05},// forbidden ++ {0x14, 0x78},//70 ++ {0x01, 0x00},// Stepless_Off ++ ++ {0xfc, 0x00}, ++ {0x29, 0x04},// Y level ++ {0x2a, 0x00}, ++ {0x2b, 0x03},// C level ++ {0x2c, 0x80},//60 ++ ++ {0xfc, 0x07}, ++ {0x37, 0x00},// Flicker ++ ++ {0xfc, 0x00}, ++ {0x72, 0xa0},// Flicker for 32MHz ++ {0x74, 0x08},// flicker 60Hz fix ++ {0xfc, 0x20}, ++ {0x02, 0x12},//02 Flicker Dgain Mode ++ {0xfc, 0x00}, ++ {0x62, 0x02},// Hue Control Enable ++ ++ {0xfc, 0x01}, ++ //{0x0c, 0x02},// Full YC Enable ++ {0x0C, 0x03},//Donghoon ++ ++ ++//========================================================== ++// COLOR MATRIX ++//========================================================== ++ {0xfc, 0x01}, //DL gain 60 ++ {0x51, 0x08}, //06 //08 07 ++ {0x52, 0xe8}, //df //9B E7 ++ {0x53, 0xfc}, //fd //FC FB ++ {0x54, 0x33}, //09 //07 B9 ++ {0x55, 0xfe}, //00 //FF 00 ++ {0x56, 0xe6}, //17 //5E 5F ++ {0x57, 0xfe}, //fe //FD FD ++ {0x58, 0x3d}, //4f //0E 46 ++ {0x59, 0x08}, //06 //07 05 ++ {0x5a, 0x21}, //9b //EE E6 ++ {0x5b, 0xfd}, //ff //FF 00 ++ {0x5c, 0xa3}, //17 //05 D3 ++ {0x5d, 0xff}, //ff //FF FF ++ {0x5e, 0xbc}, //81 //7A 53 ++ {0x5f, 0xfc}, //fd //FC FB ++ {0x60, 0x96}, //5b //23 B1 ++ {0x61, 0x07}, //07 //08 08 ++ {0x62, 0xaf}, //24 //64 FD ++ ++//========================================================== ++// EDGE ENHANCEMENT ++//========================================================== ++ {0xfc, 0x05}, ++ {0x12, 0x3d}, ++ {0x13, 0x3b}, ++ {0x14, 0x38}, ++ {0x15, 0x3b}, ++ {0x16, 0x3d}, ++ ++ {0x17, 0x3b}, ++ {0x18, 0x05}, ++ {0x19, 0x09}, ++ {0x1a, 0x05}, ++ {0x1b, 0x3b}, ++ ++ {0x1c, 0x38}, ++ {0x1d, 0x09}, ++ {0x1e, 0x1c}, ++ {0x1f, 0x09}, ++ {0x20, 0x38}, ++ ++ {0x21, 0x3b}, ++ {0x22, 0x05}, ++ {0x23, 0x09}, ++ {0x24, 0x05}, ++ {0x25, 0x3b}, ++ ++ {0x26, 0x3d}, ++ {0x27, 0x3b}, ++ {0x28, 0x38}, ++ {0x29, 0x3b}, ++ {0x2a, 0x3d}, ++ ++ {0xfc, 0x00}, ++ {0x89, 0x00},// Edge Suppress On ++ {0xfc, 0x0b}, ++ {0x42, 0x50},// Edge AGC MIN ++ {0x43, 0x60},// Edge AGC MAX ++ {0x45, 0x18},// positive gain AGC MIN ++ {0x49, 0x06},// positive gain AGC MAX ++ {0x4d, 0x18},// negative gain AGC MIN ++ {0x51, 0x06},// negative gain AGC MAX ++ ++ {0xfc, 0x05}, ++ {0x34, 0x28},// APTCLP ++ {0x35, 0x03},// APTSC ++ {0x36, 0x0b},// ENHANCE ++ {0x3f, 0x00},// NON-LIN ++ {0x42, 0x10},// EGFALL ++ {0x43, 0x00},// HLFALL ++ {0x45, 0xa0},// EGREF ++ {0x46, 0x7a},// HLREF ++ {0x47, 0x40},// LLREF ++ {0x48, 0x0c}, ++ {0x49, 0x31},// CSSEL EGSEL CS_DLY ++ ++ {0x40, 0x41},// Y delay ++ ++ // New Wide Luma Edge ++ {0xfc, 0x1d}, ++ {0x86, 0x00}, ++ {0x87, 0x60}, ++ {0x88, 0x01}, ++ {0x89, 0x20}, ++ {0x8a, 0x00}, ++ {0x8b, 0x00}, ++ {0x8c, 0x00}, ++ {0x8d, 0x00}, ++ {0x8e, 0x00}, ++ {0x8f, 0x20}, ++ {0x90, 0x00}, ++ {0x91, 0x00}, ++ {0x92, 0x00}, ++ {0x93, 0x0a}, ++ {0x94, 0x00}, ++ {0x95, 0x00}, ++ {0x96, 0x00}, ++ {0x97, 0x20}, ++ {0x98, 0x00}, ++ {0x99, 0x00}, ++ {0x9a, 0xff}, ++ {0x9b, 0xea}, ++ {0x9c, 0xaa}, ++ {0x9d, 0xab}, ++ {0x9e, 0xff}, ++ {0x9f, 0xf1}, ++ {0xa0, 0x55}, ++ {0xa1, 0x56}, ++ {0xa2, 0x07}, ++ ++ {0x85, 0x01}, ++ ++//========================================================== ++// GAMMA ++//========================================================== ++ {0xfc, 0x1d}, ++ {0x00, 0x0b}, ++ {0x01, 0x18}, ++ {0x02, 0x3d}, ++ {0x03, 0x9c}, ++ {0x04, 0x00}, ++ {0x05, 0x0c}, ++ {0x06, 0x76}, ++ {0x07, 0xc2}, ++ {0x08, 0x00}, ++ {0x09, 0x56}, ++ {0x0a, 0x34}, ++ {0x0b, 0x60}, ++ {0x0c, 0x85}, ++ {0x0d, 0xa7}, ++ {0x0e, 0xaa}, ++ {0x0f, 0xc6}, ++ {0x10, 0xe2}, ++ {0x11, 0xfc}, ++ {0x12, 0x13}, ++ {0x13, 0xab}, ++ {0x14, 0x29}, ++ {0x15, 0x3c}, ++ {0x16, 0x4b}, ++ {0x17, 0x5a}, ++ {0x18, 0xff}, ++ {0x19, 0x69}, ++ {0x1a, 0x78}, ++ {0x1b, 0x84}, ++ {0x1c, 0x91}, ++ {0x1d, 0xff}, ++ {0x1e, 0x9c}, ++ {0x1f, 0xa7}, ++ {0x20, 0xb2}, ++ {0x21, 0xbd}, ++ {0x22, 0xff}, ++ {0x23, 0xc7}, ++ {0x24, 0xd2}, ++ {0x25, 0xdb}, ++ {0x26, 0xe4}, ++ {0x27, 0xff}, ++ {0x28, 0xec}, ++ {0x29, 0xf5}, ++ {0x2a, 0xf0}, ++ {0x2b, 0x0b}, ++ {0x2c, 0x18}, ++ {0x2d, 0x3d}, ++ {0x2e, 0x9c}, ++ {0x2f, 0x00}, ++ {0x30, 0x0c}, ++ {0x31, 0x76}, ++ {0x32, 0xc2}, ++ {0x33, 0x00}, ++ {0x34, 0x56}, ++ {0x35, 0x34}, ++ {0x36, 0x60}, ++ {0x37, 0x85}, ++ {0x38, 0xa7}, ++ {0x39, 0xaa}, ++ {0x3a, 0xc6}, ++ {0x3b, 0xe2}, ++ {0x3c, 0xfc}, ++ {0x3d, 0x13}, ++ {0x3e, 0xab}, ++ {0x3f, 0x29}, ++ {0x40, 0x3c}, ++ {0x41, 0x4b}, ++ {0x42, 0x5a}, ++ {0x43, 0xff}, ++ {0x44, 0x69}, ++ {0x45, 0x78}, ++ {0x46, 0x84}, ++ {0x47, 0x91}, ++ {0x48, 0xff}, ++ {0x49, 0x9c}, ++ {0x4a, 0xa7}, ++ {0x4b, 0xb2}, ++ {0x4c, 0xbd}, ++ {0x4d, 0xff}, ++ {0x4e, 0xc7}, ++ {0x4f, 0xd2}, ++ {0x50, 0xdb}, ++ {0x51, 0xe4}, ++ {0x52, 0xff}, ++ {0x53, 0xec}, ++ {0x54, 0xf5}, ++ {0x55, 0xf0}, ++ {0x56, 0x0b}, ++ {0x57, 0x18}, ++ {0x58, 0x3d}, ++ {0x59, 0x9c}, ++ {0x5a, 0x00}, ++ {0x5b, 0x0c}, ++ {0x5c, 0x76}, ++ {0x5d, 0xc2}, ++ {0x5e, 0x00}, ++ {0x5f, 0x56}, ++ {0x60, 0x34}, ++ {0x61, 0x60}, ++ {0x62, 0x85}, ++ {0x63, 0xa7}, ++ {0x64, 0xaa}, ++ {0x65, 0xc6}, ++ {0x66, 0xe2}, ++ {0x67, 0xfc}, ++ {0x68, 0x13}, ++ {0x69, 0xab}, ++ {0x6a, 0x29}, ++ {0x6b, 0x3c}, ++ {0x6c, 0x4b}, ++ {0x6d, 0x5a}, ++ {0x6e, 0xff}, ++ {0x6f, 0x69}, ++ {0x70, 0x78}, ++ {0x71, 0x84}, ++ {0x72, 0x91}, ++ {0x73, 0xff}, ++ {0x74, 0x9c}, ++ {0x75, 0xa7}, ++ {0x76, 0xb2}, ++ {0x77, 0xbd}, ++ {0x78, 0xff}, ++ {0x79, 0xc7}, ++ {0x7a, 0xd2}, ++ {0x7b, 0xdb}, ++ {0x7c, 0xe4}, ++ {0x7d, 0xff}, ++ {0x7e, 0xec}, ++ {0x7f, 0xf5}, ++ {0x80, 0xf0}, ++ ++//========================================================== ++// HUE CONTROL ++//========================================================== ++ {0xfc, 0x00}, ++ {0x48, 0x40},// 2000K ++ {0x49, 0x30}, ++ {0x4a, 0x00}, ++ {0x4b, 0x00}, ++ {0x4c, 0x30}, ++ {0x4d, 0x38}, ++ {0x4e, 0x00}, ++ {0x4f, 0x00}, ++ ++ {0x50, 0x40},// 3000K ++ {0x51, 0x30}, ++ {0x52, 0x00}, ++ {0x53, 0x00}, ++ {0x54, 0x30}, ++ {0x55, 0x38}, ++ {0x56, 0x00}, ++ {0x57, 0x00}, ++ ++ {0x58, 0x3c},//40 // 5100K ++ {0x59, 0x30},//4a //40 ++ {0x5a, 0x00},//0c //00 ++ {0x5b, 0x00},//00 ++ {0x5c, 0x30},//4a ++ {0x5d, 0x38},//40 ++ {0x5e, 0x00},//f6 //15 ++ {0x5f, 0xfc},//00 ++ ++//========================================================== ++// SUPPRESS FUNCTION ++//========================================================== ++ {0xfc, 0x00}, ++ {0x7e, 0xf4}, ++ ++//========================================================== ++// BPR ++//========================================================== ++ {0xfc, 0x0b}, ++ {0x3d, 0x10}, ++ ++ {0xfc, 0x0b}, ++ {0x0b, 0x00}, ++ {0x0c, 0x40}, ++ {0x0d, 0x5a}, ++ {0x0e, 0x00}, ++ {0x0f, 0x20}, ++ {0x10, 0x00}, ++ {0x11, 0x10}, ++ {0x12, 0x00}, ++ {0x13, 0x7f}, ++ {0x14, 0x03}, ++ {0x15, 0xff}, ++ {0x16, 0x48}, ++ {0x17, 0x60}, ++ {0x18, 0x00}, ++ {0x19, 0x00}, ++ {0x1a, 0x00}, ++ {0x1b, 0x20}, ++ {0x1c, 0x00}, ++ {0x1d, 0x00}, ++ {0x1e, 0x00}, ++ {0x1f, 0x20}, ++ ++//========================================================== ++// GR/GB CORRECTION ++//========================================================== ++ {0xfc, 0x01}, ++ {0x45, 0x0c}, ++ {0xfc, 0x0b}, ++ {0x21, 0x00}, ++ {0x22, 0x40}, ++ {0x23, 0x60}, ++ {0x24, 0x0d}, ++ {0x25, 0x20}, ++ {0x26, 0x0d}, ++ {0x27, 0x20}, ++ ++//========================================================== ++// NR ++//========================================================== ++ {0xfc, 0x01}, ++ {0x4c, 0x01}, ++ {0x49, 0x15}, ++ {0x4b, 0x0a}, ++ ++ {0xfc, 0x0b}, ++ {0x28, 0x00}, ++ {0x29, 0x00}, ++ {0x2a, 0x14}, ++ {0x2b, 0x00}, ++ {0x2c, 0x14}, ++ {0x2d, 0x00}, ++ {0x2e, 0xD0}, ++ {0x2f, 0x02}, ++ {0x30, 0x00}, ++ {0x31, 0x00}, ++ {0x32, 0xa0}, ++ {0x33, 0x00}, ++ {0x34, 0xe0}, ++ ++//========================================================== ++// 1D-Y/C-SIGMA-LPF ++//========================================================== ++ {0xfc, 0x01}, ++ {0x05, 0xC0}, ++ ++ {0xfc, 0x0b}, ++ {0x35, 0x00}, ++ {0x36, 0x40}, ++ {0x37, 0x60}, ++ {0x38, 0x00}, ++ {0x39, 0x18}, ++ {0x3a, 0x00}, ++ {0x3b, 0x40}, ++ {0x3c, 0x50}, ++ {0x3d, 0x60}, ++ {0x3e, 0x00}, ++ {0x3f, 0x30}, ++ {0x40, 0x00}, ++ {0x41, 0x40}, ++ {0xd4, 0x40}, ++ {0xd5, 0x60}, ++ {0xd6, 0xb0}, ++ {0xd7, 0xf0}, ++ {0xd8, 0xb0}, ++ {0xd9, 0xf0}, ++ ++//========================================================== ++// COLOR SUPPRESS ++//========================================================== ++ {0xfc, 0x0b}, ++ {0x08, 0x58}, ++ {0x09, 0x03}, ++ {0x0a, 0x00}, ++ ++//========================================================== ++// SHADING ++//========================================================== ++ {0xfc, 0x09}, ++ ++ {0x01, 0x06}, ++ {0x02, 0x40}, ++ ++ {0x03, 0x04}, ++ {0x04, 0xB0}, ++ ++ {0x05, 0x03}, ++ {0x06, 0x20}, ++ {0x07, 0x02}, ++ {0x08, 0x91}, ++ ++ {0x09, 0x03}, ++ {0x0A, 0x25}, ++ {0x0B, 0x02}, ++ {0x0C, 0x64}, ++ ++ {0x0D, 0x03}, ++ {0x0E, 0x0F}, ++ {0x0F, 0x02}, ++ {0x10, 0x4E}, ++ ++ {0x1D, 0x80}, ++ {0x1E, 0x00}, ++ {0x1F, 0x80}, ++ {0x20, 0x00}, ++ {0x23, 0x85}, ++ {0x24, 0x52}, ++ {0x21, 0x79}, ++ {0x22, 0xE6}, ++ ++ {0x25, 0x80}, ++ {0x26, 0x00}, ++ {0x27, 0x80}, ++ {0x28, 0x00}, ++ {0x2B, 0x81}, ++ {0x2C, 0x48}, ++ {0x29, 0x81}, ++ {0x2A, 0x48}, ++ ++ {0x2D, 0x80}, ++ {0x2E, 0x00}, ++ {0x2F, 0x80}, ++ {0x30, 0x00}, ++ {0x33, 0x7C}, ++ {0x34, 0x45}, ++ {0x31, 0x7D}, ++ {0x32, 0x7D}, ++ ++ {0x35, 0x01}, ++ {0x36, 0x00}, ++ {0x37, 0x01}, ++ {0x38, 0x11}, ++ {0x39, 0x01}, ++ {0x3A, 0x4E}, ++ {0x3B, 0x01}, ++ {0x3C, 0xAB}, ++ {0x3D, 0x01}, ++ {0x3E, 0xDC}, ++ {0x3F, 0x02}, ++ {0x40, 0x1A}, ++ {0x41, 0x02}, ++ {0x42, 0x6A}, ++ {0x43, 0x02}, ++ {0x44, 0xD3}, ++ ++ {0x45, 0x01}, ++ {0x46, 0x00}, ++ {0x47, 0x01}, ++ {0x48, 0x0E}, ++ {0x49, 0x01}, ++ {0x4A, 0x40}, ++ {0x4B, 0x01}, ++ {0x4C, 0x8A}, ++ {0x4D, 0x01}, ++ {0x4E, 0xB5}, ++ {0x4F, 0x01}, ++ {0x50, 0xE8}, ++ {0x51, 0x02}, ++ {0x52, 0x27}, ++ {0x53, 0x02}, ++ {0x54, 0x84}, ++ ++ {0x55, 0x01}, ++ {0x56, 0x00}, ++ {0x57, 0x01}, ++ {0x58, 0x0C}, ++ {0x59, 0x01}, ++ {0x5A, 0x37}, ++ {0x5B, 0x01}, ++ {0x5C, 0x74}, ++ {0x5D, 0x01}, ++ {0x5E, 0x96}, ++ {0x5F, 0x01}, ++ {0x60, 0xC9}, ++ {0x61, 0x02}, ++ {0x62, 0x04}, ++ {0x63, 0x02}, ++ {0x64, 0x4B}, ++ ++ {0x65, 0x00}, ++ {0x66, 0x9A}, ++ {0x67, 0x2D}, ++ {0x68, 0x02}, ++ {0x69, 0x68}, ++ {0x6A, 0xB6}, ++ {0x6B, 0x05}, ++ {0x6C, 0x6B}, ++ {0x6D, 0x99}, ++ {0x6E, 0x07}, ++ {0x6F, 0x60}, ++ {0x70, 0xAD}, ++ {0x71, 0x09}, ++ {0x72, 0xA2}, ++ {0x73, 0xD7}, ++ {0x74, 0x0C}, ++ {0x75, 0x32}, ++ {0x76, 0x19}, ++ {0x77, 0x0F}, ++ {0x78, 0x0E}, ++ {0x79, 0x70}, ++ ++ {0x7A, 0x00}, ++ {0x7B, 0x9C}, ++ {0x7C, 0x9F}, ++ {0x7D, 0x02}, ++ {0x7E, 0x72}, ++ {0x7F, 0x7A}, ++ {0x80, 0x05}, ++ {0x81, 0x81}, ++ {0x82, 0x94}, ++ {0x83, 0x07}, ++ {0x84, 0x7E}, ++ {0x85, 0x97}, ++ {0x86, 0x09}, ++ {0x87, 0xC9}, ++ {0x88, 0xEA}, ++ {0x89, 0x0C}, ++ {0x8A, 0x63}, ++ {0x8B, 0x8C}, ++ {0x8C, 0x0F}, ++ {0x8D, 0x4B}, ++ {0x8E, 0x7E}, ++ ++ {0x8F, 0x00}, ++ {0x90, 0x9E}, ++ {0x91, 0xBD}, ++ {0x92, 0x02}, ++ {0x93, 0x7A}, ++ {0x94, 0xF5}, ++ {0x95, 0x05}, ++ {0x96, 0x94}, ++ {0x97, 0xA8}, ++ {0x98, 0x07}, ++ {0x99, 0x98}, ++ {0x9A, 0x8F}, ++ {0x9B, 0x09}, ++ {0x9C, 0xEB}, ++ {0x9D, 0xD5}, ++ {0x9E, 0x0C}, ++ {0x9F, 0x8E}, ++ {0xA0, 0x7A}, ++ {0xA1, 0x0F}, ++ {0xA2, 0x80}, ++ {0xA3, 0x7D}, ++ ++ {0xA4, 0x6A}, ++ {0xA5, 0x44}, ++ {0xA6, 0x23}, ++ {0xA7, 0x6C}, ++ {0xA8, 0x15}, ++ {0xA9, 0x40}, ++ {0xAA, 0x20}, ++ {0xAB, 0xB2}, ++ {0xAC, 0x1C}, ++ {0xAD, 0x56}, ++ {0xAE, 0x19}, ++ {0xAF, 0x01}, ++ {0xB0, 0x16}, ++ {0xB1, 0x5F}, ++ ++ {0xB2, 0x68}, ++ {0xB3, 0x9C}, ++ {0xB4, 0x22}, ++ {0xB5, 0xDE}, ++ {0xB6, 0x14}, ++ {0xB7, 0xEC}, ++ {0xB8, 0x20}, ++ {0xB9, 0x30}, ++ {0xBA, 0x1B}, ++ {0xBB, 0xE5}, ++ {0xBC, 0x18}, ++ {0xBD, 0x9D}, ++ {0xBE, 0x16}, ++ {0xBF, 0x05}, ++ ++ {0xC0, 0x67}, ++ {0xC1, 0x36}, ++ {0xC2, 0x22}, ++ {0xC3, 0x67}, ++ {0xC4, 0x14}, ++ {0xC5, 0xA4}, ++ {0xC6, 0x1F}, ++ {0xC7, 0xC2}, ++ {0xC8, 0x1B}, ++ {0xC9, 0x86}, ++ {0xCA, 0x18}, ++ {0xCB, 0x49}, ++ {0xCC, 0x15}, ++ {0xCD, 0xBA}, ++ ++ {0x00, 0x02},// shading on ++ ++//========================================================== ++// X-SHADING ++//========================================================== ++ {0xfc, 0x1B}, ++ {0x80, 0x01}, ++ {0x81, 0x00}, ++ {0x82, 0x4C}, ++ {0x83, 0x00}, ++ {0x84, 0x86}, ++ {0x85, 0x03}, ++ {0x86, 0x5E}, ++ {0x87, 0x00}, ++ {0x88, 0x07}, ++ {0x89, 0xA4}, ++ {0x90, 0x00}, ++ {0x91, 0x88}, ++ {0x92, 0x00}, ++ {0x93, 0xC1}, ++ {0x94, 0x00}, ++ {0x95, 0xF7}, ++ {0x96, 0x01}, ++ {0x97, 0x21}, ++ {0x98, 0x01}, ++ {0x99, 0x37}, ++ {0x9A, 0x01}, ++ {0x9B, 0x0C}, ++ {0x9C, 0x00}, ++ {0x9D, 0xCE}, ++ {0x9E, 0x00}, ++ {0x9F, 0x3B}, ++ {0xA0, 0x00}, ++ {0xA1, 0x5B}, ++ {0xA2, 0x00}, ++ {0xA3, 0x7A}, ++ {0xA4, 0x00}, ++ {0xA5, 0x92}, ++ {0xA6, 0x00}, ++ {0xA7, 0x91}, ++ {0xA8, 0x00}, ++ {0xA9, 0x81}, ++ {0xAA, 0x00}, ++ {0xAB, 0x60}, ++ {0xAC, 0x07}, ++ {0xAD, 0xCB}, ++ {0xAE, 0x07}, ++ {0xAF, 0xC5}, ++ {0xB0, 0x07}, ++ {0xB1, 0xBB}, ++ {0xB2, 0x07}, ++ {0xB3, 0xAA}, ++ {0xB4, 0x07}, ++ {0xB5, 0xA9}, ++ {0xB6, 0x07}, ++ {0xB7, 0xB2}, ++ {0xB8, 0x07}, ++ {0xB9, 0xBF}, ++ {0xBA, 0x07}, ++ {0xBB, 0x5E}, ++ {0xBC, 0x07}, ++ {0xBD, 0x3C}, ++ {0xBE, 0x06}, ++ {0xBF, 0xF9}, ++ {0xC0, 0x06}, ++ {0xC1, 0xBD}, ++ {0xC2, 0x06}, ++ {0xC3, 0xB8}, ++ {0xC4, 0x06}, ++ {0xC5, 0xE2}, ++ {0xC6, 0x07}, ++ {0xC7, 0x1A}, ++ {0xC8, 0x07}, ++ {0xC9, 0x15}, ++ {0xCA, 0x06}, ++ {0xCB, 0xDE}, ++ {0xCC, 0x06}, ++ {0xCD, 0x9C}, ++ {0xCE, 0x06}, ++ {0xCF, 0x6F}, ++ {0xD0, 0x06}, ++ {0xD1, 0x5E}, ++ {0xD2, 0x06}, ++ {0xD3, 0x84}, ++ {0xD4, 0x06}, ++ {0xD5, 0xCA}, ++ ++ {0xfc, 0x0b}, ++ {0xda, 0x00}, ++ {0xdb, 0x9c}, ++ {0xdc, 0x00}, ++ {0xdd, 0xd1}, ++ ++ {0xfc, 0x1b}, ++ {0x80, 0x01}, ++ ++//========================================================== ++// AE WINDOW WEIGHT ++//========================================================== ++ {0xfc, 0x00}, ++ {0x03, 0x4b}, ++ {0xfc, 0x06}, ++ {0x01, 0x35}, ++ {0x03, 0xc2}, ++ {0x05, 0x48}, ++ {0x07, 0xb8}, ++ {0x31, 0x2a}, ++ {0x33, 0x61}, ++ {0x35, 0x28}, ++ {0x37, 0x5c}, ++ ++ {0xfc, 0x20}, ++ {0x60, 0x11}, ++ {0x61, 0x11}, ++ {0x62, 0x11}, ++ {0x63, 0x11}, ++ {0x64, 0x11}, ++ {0x65, 0x22}, ++ {0x66, 0x22}, ++ {0x67, 0x11}, ++ {0x68, 0x11}, ++ {0x69, 0x33}, ++ {0x6a, 0x33}, ++ {0x6b, 0x11}, ++ {0x6c, 0x12}, ++ {0x6d, 0x55}, ++ {0x6e, 0x55}, ++ {0x6f, 0x21}, ++ {0x70, 0x13}, ++ {0x71, 0x55}, ++ {0x72, 0x55}, ++ {0x73, 0x31}, ++ {0x74, 0x33}, ++ {0x75, 0x33}, ++ {0x76, 0x33}, ++ {0x77, 0x33}, ++ ++//========================================================== ++// SAIT AWB ++//========================================================== ++ {0xfc, 0x00}, ++ {0x7b, 0x00}, ++ ++ {0xfc, 0x07}, ++ {0x3c, 0x10}, ++ {0x3d, 0x10}, ++ {0x3e, 0x10}, ++ {0x3f, 0x10}, ++ ++ {0xfc, 0x01}, ++ {0xc8, 0xe0}, ++ {0xfc, 0x00}, ++ {0x3e, 0x10}, ++ ++ {0xfc, 0x00}, ++ {0x3e, 0x10}, ++ {0x3d, 0x04}, ++ {0x32, 0x02}, ++ {0x81, 0x10}, ++ {0xbc, 0xf0}, ++ {0xfc, 0x22}, ++ {0x8c, 0x04}, ++ {0x8d, 0x06}, ++ ++ {0xfc, 0x07}, ++ {0x97, 0x00}, ++ ++//================================= ++// White Point ++//================================= ++ {0xfc, 0x22}, ++ {0x01, 0xD8}, ++ {0x03, 0xA1}, ++ {0x05, 0xCA}, ++ {0x07, 0xC8}, ++ {0x09, 0xB3}, ++ {0x0b, 0xE2}, ++ {0x0d, 0xA0}, ++ {0x0f, 0xF0}, ++ {0x11, 0x94}, ++ {0x12, 0x00}, ++ {0x13, 0xFD}, ++ {0x15, 0x88}, ++ {0x16, 0x01}, ++ {0x17, 0x10}, ++ ++//================================= ++// Basic Setting ++//================================= ++ {0xfc, 0x22}, ++ {0xA8, 0xFF}, ++ ++ {0xA0, 0x01}, ++ {0xA1, 0x38}, ++ {0xA2, 0x0E}, ++ {0xA3, 0x6D}, ++ {0xA4, 0x07}, ++ {0xA5, 0xF5}, ++ {0xA6, 0x11}, ++ {0xA7, 0xBE}, ++ {0xA9, 0x02}, ++ {0xAA, 0xD2}, ++ {0xAB, 0x00}, ++ {0xAC, 0x00}, ++ {0xAD, 0x02}, ++ {0xAE, 0x3F}, ++ {0xAF, 0x19}, ++ {0xB0, 0x91}, ++ {0x94, 0x3D}, ++ {0x95, 0x00}, ++ {0x96, 0x58}, ++ {0x97, 0x80}, ++ {0xD0, 0xA2}, ++ {0xD1, 0x2E}, ++ {0xD2, 0x4D}, ++ {0xD3, 0x28}, ++ {0xD4, 0x90}, ++ {0xDB, 0x2E}, ++ {0xDC, 0x7A}, ++ {0xDD, 0x28}, ++ {0xE7, 0x00}, ++ {0xE8, 0xc7}, ++ {0xE9, 0x00}, ++ {0xEA, 0x62}, ++ {0xEB, 0xD2}, ++ {0xEC, 0xD9}, ++ {0xEE, 0xA6}, ++ ++ {0xfc, 0x00}, ++ {0x8a, 0x02}, ++ ++//================================= ++// Pixel Filter Setting ++//================================= ++ {0xFC, 0x07}, ++ {0x95, 0xCF}, ++ ++ {0xfc, 0x01}, ++ {0xd3, 0x4f}, ++ {0xd4, 0x00}, ++ {0xd5, 0x3c}, ++ {0xd6, 0x80}, ++ {0xd7, 0x61}, ++ {0xd8, 0x00}, ++ {0xd9, 0x49}, ++ {0xda, 0x00}, ++ {0xdb, 0x24}, ++ {0xdc, 0x4b}, ++ {0xdd, 0x23}, ++ {0xde, 0xf2}, ++ {0xdf, 0x20}, ++ {0xe0, 0x73}, ++ {0xe1, 0x18}, ++ {0xe2, 0x69}, ++ {0xe3, 0x31}, ++ {0xe4, 0x40}, ++ {0xe5, 0x34}, ++ {0xe6, 0x40}, ++ {0xe7, 0x40}, ++ {0xe8, 0x32}, ++ {0xe9, 0x40}, ++ {0xea, 0x1c}, ++ {0xeb, 0x00}, ++ ++//================================= ++// Polygon AWB Region Tune ++//================================= ++ ++ // AWB3 - Polygon Region ++ {0xfc, 0x22}, ++ {0x18, 0x00}, ++ {0x19, 0x4b}, ++ {0x1a, 0xfd}, ++ {0x1b, 0x00}, ++ {0x1c, 0x41}, ++ {0x1d, 0xd9}, ++ {0x1e, 0x00}, ++ {0x1f, 0x66}, ++ {0x20, 0xa9}, ++ {0x21, 0x00}, ++ {0x22, 0x8b}, ++ {0x23, 0x82}, ++ {0x24, 0x00}, ++ {0x25, 0xa4}, ++ {0x26, 0x6c}, ++ {0x27, 0x00}, ++ {0x28, 0xbd}, ++ {0x29, 0x5d}, ++ {0x2a, 0x00}, ++ {0x2b, 0xdc}, ++ {0x2c, 0x4d}, ++ {0x2d, 0x00}, ++ {0x2e, 0xdc}, ++ {0x2f, 0x63}, ++ {0x30, 0x00}, ++ {0x31, 0xc1}, ++ {0x32, 0x72}, ++ {0x33, 0x00}, ++ {0x34, 0xab}, ++ {0x35, 0x84}, ++ {0x36, 0x00}, ++ {0x37, 0x99}, ++ {0x38, 0xa0}, ++ {0x39, 0x00}, ++ {0x3a, 0x81}, ++ {0x3b, 0xe9}, ++ {0x3c, 0x00}, ++ {0x3d, 0x00}, ++ {0x3e, 0x00}, ++ {0x3f, 0x00}, ++ {0x40, 0x00}, ++ {0x41, 0x00}, ++ ++//================================= ++// Moving Equation Weight ++//================================= ++ {0xfc, 0x22}, ++ {0x98, 0x07}, ++ ++//================================= ++// EIT Threshold ++//================================= ++ {0xfc, 0x22}, ++ {0xb1, 0x00}, ++ {0xb2, 0x02}, ++ {0xb3, 0x00}, ++ {0xb4, 0xC1}, ++ ++ {0xb5, 0x00}, ++ {0xb6, 0x02}, ++ {0xb7, 0x00}, ++ {0xb9, 0xc2}, ++ ++ {0xd7, 0x00}, ++ {0xd8, 0x35}, ++ {0xd9, 0x20}, ++ {0xda, 0x81}, ++ ++//================================= ++// Gain Offset ++//================================= ++ {0xfc, 0x00}, ++ {0x79, 0xf8}, ++ {0x7a, 0x08}, ++ ++ {0xfc, 0x07}, ++ {0x11, 0x01}, ++ ++ {0xfc, 0x22}, ++ {0x58, 0xf8}, ++ {0x59, 0x00}, ++ {0x5A, 0xfc}, ++ {0x5B, 0x00}, ++ {0x5C, 0x00}, ++ {0x5D, 0x00}, ++ {0x5E, 0x00}, ++ {0x5F, 0x00}, ++ {0x60, 0x00}, ++ {0x61, 0xf8}, ++ {0x62, 0x00}, ++ {0x63, 0xf0}, ++ ++ {0xde, 0x00}, ++ {0xf0, 0x6a}, ++ ++//================================= ++// Green Stablity Enhance ++//================================= ++ {0xfc, 0x22}, ++ {0xb9, 0x00}, ++ {0xba, 0x00}, ++ {0xbb, 0x00}, ++ {0xbc, 0x00}, ++ {0xe5, 0x01}, ++ {0xe6, 0xff}, ++ {0xbd, 0x8c}, ++ ++//========================================================== ++// Special Effect ++//========================================================== ++ {0xfc, 0x07}, ++ {0x30, 0xc0}, ++ {0x31, 0x20}, ++ {0x32, 0x40}, ++ {0x33, 0xc0}, ++ {0x34, 0x00}, ++ {0x35, 0xb0}, ++#endif ++//========================================================== ++// ETC ++//========================================================== ++ {0xfc, 0x01}, ++ {0x01, 0x01}, ++ {0x00, 0x90}, ++ {0xfc, 0x02}, ++ {0x03, 0x20}, ++ ++ {0xfc, 0x20}, ++ {0x0f, 0x00}, ++ ++ {0xfc, 0x00}, ++ {0x02, 0x09}, ++ ++ {0xfc, 0x01}, ++ //{0x02, 0x00}, ++ {0x02, 0x02},//Donghoon ++}; ++#endif ++ ++// For SVGA ( 800 x 600) on 4BA module ++s5k4ba_t s5k4ba_svga_reg[] = ++{ ++ {0xfc,0x02}, ++ {0x2d,0x48}, ++ {0x44,0x63}, ++ ++ {0xfc,0x03}, ++ {0x02,0x04}, ++ {0xfc,0x20}, ++ {0x14,0x70}, ++ ++ {0xfc,0x00}, ++ {0x03,0x4b}, // AE/AWB On ++ {0x7e,0xf4}, // Suppress On ++ {0x89,0x03}, // Edge Suppress On ++ ++ {0xfc,0x02}, ++ {0x02,0x0e},//sensor BPRoff ++ ++ {0xfc,0x20}, ++ {0x16,0x60}, // Frame AE Start ++ ++ {0xfc,0x02}, ++ {0x30,0x90}, // Analog offset ++ {0x37,0x0d}, // Global Gain ++ {0x60,0x00}, // Blank_Adrs ++ {0x45,0x0e}, // CDS Timing for Average Sub_Sampling ++ {0x47,0x2f}, ++ ++ {0xfc,0x01}, ++ {0x9F,0x05}, //B ++ {0xA0,0x18}, ++ {0xA1,0x42}, ++ {0xA2,0xd7}, ++ {0xA3,0x00}, ++ ++ {0xA4,0xB6}, ++ {0xA5,0x3b}, ++ {0xA6,0x88}, ++ {0xA7,0xC8}, ++ {0xA8,0x6A}, ++ ++ {0xfc,0x05}, ++ {0x34,0x20}, // APTCLP ++ {0x35,0x08}, //9 //APTSC ++ ++ {0xfc,0x00}, // flash 0821 ++ {0x32,0x04}, // AWB moving average 8 frame ++ ++ {0xfc,0x01}, ++ {0x01,0x01}, // Pclk inversion ++ ++ {0xfc,0x00}, ++ {0x02,0x09}, // 800 x 600 ++ ++ ++ {0xFF,0xFF} // REGISTER END ++}; ++ ++/* SQVGA */ ++s5k4ba_t s5k4ba_qsvga_reg[] = ++{ ++ // Pclk inversion ++ {0xfc,0x01}, ++ {0x01,0x01}, ++ ++ // To setting CbCr selection on Table 14h ++ {0xfc, 0x14}, ++ {0x5c, 0x00}, ++ ++ // To load table_11 H4V4 ++ {0xfc, 0x00}, ++ {0x02, 0x0B} ++}; ++ ++#define S5K4BA_INIT_REGS (sizeof(s5k4ba_init_reg) / sizeof(s5k4ba_init_reg[0])) ++#define S5K4BA_SVGA_REGS (sizeof(s5k4ba_svga_reg) / sizeof(s5k4ba_svga_reg[0])) ++#define S5K4BA_QSVGA_REGS (sizeof(s5k4ba_qsvga_reg) / sizeof(s5k4ba_qsvga_reg[0])) ++ ++#endif ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimd/Kconfig linux-2.6.28.6/drivers/media/video/samsung/fimd/Kconfig +--- linux-2.6.28/drivers/media/video/samsung/fimd/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimd/Kconfig 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,32 @@ ++ ++if VIDEO_FIMC ++comment "FIMC configurations" ++endif ++ ++config VIDEO_FIMC ++ bool "Samsung Camera Interface (FIMC) driver" ++ depends on VIDEO_SAMSUNG ++ default n ++ ---help--- ++ This is a video4linux driver for Samsung FIMC device. ++ ++config VIDEO_FIMC_DEBUG ++ bool "FIMC driver debug messages" ++ depends on VIDEO_FIMC ++ ++config VIDEO_FIMC_MIPI ++ bool "FIMC works with MIPI-CSI2 (Rx)" ++ depends on VIDEO_FIMC && ARCH_S5PC1XX ++ ++source "drivers/media/video/samsung/fimc/Kconfig-camera" ++ ++config VIDEO_FIMC_CAM_CH ++ int "External Camera channel (0=A, 1=B)" ++ depends on VIDEO_FIMC ++ default "0" ++ ++config VIDEO_FIMC_CAM_RESET ++ int "Reset Type (0=low, 1=high)" ++ depends on VIDEO_FIMC ++ default "0" ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimd/Makefile linux-2.6.28.6/drivers/media/video/samsung/fimd/Makefile +--- linux-2.6.28/drivers/media/video/samsung/fimd/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimd/Makefile 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,8 @@ ++obj-$(CONFIG_VIDEO_FIMD) += s3c_fimd_core.o s3c_fimd_v4l2.o s3c_fimd_cfg.o ++obj-$(CONFIG_ARCH_S5PC1XX) += s3c_fimd4x_regs.o ++ ++EXTRA_CFLAGS += -Idrivers/media/video ++ ++ifeq ($(CONFIG_VIDEO_FIMC_DEBUG),y) ++EXTRA_CFLAGS += -DDEBUG ++endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimd/s3c_fimd.h linux-2.6.28.6/drivers/media/video/samsung/fimd/s3c_fimd.h +--- linux-2.6.28/drivers/media/video/samsung/fimd/s3c_fimd.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimd/s3c_fimd.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,284 @@ ++/* linux/drivers/media/video/samsung/s3c_fimc.h ++ * ++ * Header file for Samsung Camera Interface (FIMC) driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef _S3C_FIMD_H ++#define _S3C_FIMD_H ++ ++#ifdef __KERNEL__ ++#include ++#include ++#include ++#include ++#include ++#include ++#endif ++ ++/* ++ * C O M M O N D E F I N I T I O N S ++ * ++*/ ++#define S3C_FIMD_NAME "s3c-fimd" ++ ++#define info(args...) do { printk(KERN_INFO S3C_FIMD_NAME ": " args); } while (0) ++#define err(args...) do { printk(KERN_ERR S3C_FIMD_NAME ": " args); } while (0) ++ ++ ++/* ++ * E N U M E R A T I O N S ++ * ++*/ ++enum s3c_fimd_data_path_t { ++ DATA_PATH_DMA, ++ DATA_PATH_FIFO, ++}; ++ ++enum s3c_fimd_alpha_t { ++ PLANE_BLENDING, ++ PIXEL_BLENDING, ++}; ++ ++enum s3c_fimd_chroma_dir_t { ++ CHROMA_FG, ++ CHROMA_BG, ++}; ++ ++enum s3c_fimd_output_t { ++ OUTPUT_RGB, ++ OUTPUT_ITU, ++ OUTPUT_I80LDI0, ++ OUTPUT_I80LDI1, ++ OUTPUT_TV, ++ OUTPUT_TV_RGB, ++ OUTPUT_TV_I80LDI0, ++ OUTPUT_TV_I80LDI1, ++}; ++ ++enum s3c_fimd_rgb_mode_t { ++ MDOE_RGB_P = 0, ++ MODE_BGR_P = 1, ++ MODE_RGB_S = 2, ++ MODE_BGR_S = 3, ++}; ++ ++ ++/* ++ * F I M D S T R U C T U R E S ++ * ++*/ ++ ++/* ++ * struct s3c_fimd_buffer ++ * @width: horizontal resolution ++ * @height: vertical resolution ++ * @ofs_x: left horizontal offset ++ * @ofs_y: top vertical offset ++ * @auto_sel: if auto buffer change enabled by hardware ++ * @vs: if virtual screen enabled ++ * @current: current activated buffer ++ * @paddr: physical address of frame buffer ++*/ ++struct s3c_fimd_buffer { ++ int width; ++ int height; ++ int ofs_x; ++ int ofs_y; ++ int auto_sel; ++ int vs; ++ int current; ++ u8 **paddr; ++}; ++ ++/* ++ * struct s3c_fimd_alpha ++ * @mode: blending method (plane/pixel) ++ * @channel: alpha channel (0/1) ++ * @multiple: if multiple alpha blending enabled ++ * @alpha_value: alpha value ++*/ ++struct s3c_fimd_alpha { ++ enum s3c_fimd_alpha_t mode; ++ int channel; ++ int multiple; ++ int alpha_value; ++}; ++ ++/* ++ * struct s3c_fimd_chroma ++ * @enabled: if chroma key function enabled ++ * @blended: if chroma key alpha blending enabled ++ * @dir: chroma key direction (fore/back) ++ * @chroma_key: chroma value to be applied ++ * @alpha_value: alpha value for chroma ++ * ++*/ ++struct s3c_fimd_chroma { ++ int enabled; ++ int blended; ++ u32 comp_key; ++ u32 chroma_key; ++ u32 alpha_value; ++ enum s3c_fimd_chroma_dir_t dir; ++}; ++ ++/* ++ * struct s3c_fimd_lcd_polarity ++ * @vclk: if VCLK polarity is inversed ++ * @hsync: if HSYNC polarity is inversed ++ * @vsync: if VSYNC polarity is inversed ++ * @vden: if VDEN polarity is inversed ++*/ ++struct s3c_fimd_lcd_polarity { ++ int vclk; ++ int hsync; ++ int vsync; ++ int vden; ++}; ++ ++/* ++ * struct s3c_fimd_lcd_timing ++ * @h_fp: horizontal front porch ++ * @h_fpe: horizontal front porch for even field ++ * @h_bp: horizontal back porch ++ * @h_sw: horizontal sync width ++ * @v_fp: vertical front porch ++ * @v_fpe: vertical front porch for even field ++ * @v_bp: vertical back porch ++ * @v_bpe: vertical back porch for even field ++*/ ++struct s3c_fimd_lcd_timing { ++ int h_fp; ++ int h_fpe; ++ int h_bp; ++ int h_sw; ++ int v_fp; ++ int v_fpe; ++ int v_bp; ++ int v_bpe; ++}; ++ ++/* ++ * struct s3c_fimd_lcd ++ * @width: horizontal resolution ++ * @height: vertical resolution ++ * @bpp: bits per pixel ++ * @freq: vframe frequency ++ * @initialized: if initialized ++ * @timing: timing values ++ * @polarity: polarity settings ++ * @init_ldi: pointer to LDI init function ++ * ++*/ ++struct s3c_fimd_lcd { ++ int width; ++ int height; ++ int bpp; ++ int freq; ++ int initialized; ++ struct s3c_fimd_lcd_timing timing; ++ struct s3c_fimd_lcd_polarity polarity; ++ ++ void (*init_ldi)(void); ++}; ++ ++/* ++ * struct s3c_fimd_window ++ * @id: window id ++ * @enabled: if enabled ++ * @shadow_lock: current lock status for updating next frame ++ * @path: data path (dma/fifo) ++ * @bit_swap: if bit swap enabled ++ * @byte_swap: if byte swap enabled ++ * @halfword_swap: if halfword swap enabled ++ * @word_swap: if word swap enabled ++ * @dma_burst: dma burst length (4/8/16) ++ * @bpp: bits per pixel ++ * @unpacked: if unpacked format is ++ * @buffer: frame buffer structure ++ * @alpha: alpha blending structure ++ * @chroma: chroma key structure ++*/ ++struct s3c_fimd_window { ++ int id; ++ int enabled; ++ int shadow_lock; ++ enum s3c_fimd_data_path_t path; ++ int bit_swap; ++ int byte_swap; ++ int halfword_swap; ++ int word_swap; ++ int dma_burst; ++ int bpp; ++ int unpacked; ++ struct s3c_fimd_buffer buffer; ++ struct s3c_fimd_alpha alpha; ++ struct s3c_fimd_chroma chroma; ++}; ++ ++/* ++ * struct s3c_fimd_v4l2 ++*/ ++struct s3c_fimd_v4l2 { ++ struct v4l2_fmtdesc *fmtdesc; ++ struct v4l2_framebuffer frmbuf; ++ struct v4l2_input *input; ++ struct v4l2_output *output; ++ struct v4l2_rect crop_bounds; ++ struct v4l2_rect crop_defrect; ++ struct v4l2_rect crop_current; ++}; ++ ++/* ++ * struct s3c_fimd_global ++ * ++ * @enabled: if signal output enabled ++ * @dsi: if mipi-dsim enabled ++ * @interlace: if interlace format is used ++ * @output: output path (RGB/I80/Etc) ++ * @rgb_serial: if RGB signal output is serialized ++ * @vclk_freerun: if vclk is free-run mode ++ * @alps_enabled: if ALPS enabled (over FIMD 6.0) ++ * @gamma_enabled: if gamma control enabled (over FIMD 6.0) ++ * @gain_enabled: if gain control enabled (over FIMD 6.0) ++ * @win: pointer to window structure ++ * @lcd: pointer to lcd structure ++*/ ++struct s3c_fimd_global { ++ /* general */ ++ void __iomem *regs; ++ struct mutex lock; ++ struct device *dev; ++ struct clk *clock; ++ int irq; ++ struct video_device *vd; ++ struct s3c_fimd_v4l2 v4l2; ++ ++ /* fimd */ ++ int enabled; ++ int dsi; ++ int interlace; ++ enum s3c_fimd_output_t output; ++ enum s3c_fimd_rgb_mode_t rgb_mode; ++ int vclk_freerun; ++ int alps_enabled; ++ int gamma_enabled; ++ int gain_enabled; ++ struct s3c_fimd_window **win; ++ struct s3c_fimd_lcd *lcd; ++}; ++ ++ ++/* ++ * E X T E R N S ++ * ++*/ ++ ++#endif /* _S3C_FIMD_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimd/s3c_fimd5x_regs.c linux-2.6.28.6/drivers/media/video/samsung/fimd/s3c_fimd5x_regs.c +--- linux-2.6.28/drivers/media/video/samsung/fimd/s3c_fimd5x_regs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimd/s3c_fimd5x_regs.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,137 @@ ++/* linux/drivers/media/video/samsung/fimd/s3c_fimd5x_regs.c ++ * ++ * Register interface file for Samsung Display Controller (FIMD) driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "s3c_fimd.h" ++ ++int s3c_fimd_set_output(struct s3c_fimd_global *ctrl) ++{ ++ u32 cfg; ++ ++ cfg = readl(ctrl->regs + S3C_VIDCON0); ++ cfg &= ~S3C_VIDCON0_VIDOUT_MASK; ++ ++ if (ctrl->output == OUTPUT_RGB) ++ cfg |= S3C_VIDCON0_VIDOUT_RGB; ++ else if (ctrl->out == OUTPUT_ITU) ++ cfg |= S3C_VIDCON0_VIDOUT_ITU; ++ else if (ctrl->out == OUTPUT_I80LDI0) ++ cfg |= S3C_VIDCON0_VIDOUT_I80LDI0; ++ else if (ctrl->out == OUTPUT_I80LDI1) ++ cfg |= S3C_VIDCON0_VIDOUT_I80LDI1; ++ else { ++ err("invalid output type: %d\n", ctrl->output); ++ return -EINVAL; ++ } ++ ++ writel(cfg, ctrl->regs + S3C_VIDCON0); ++ ++ return 0; ++} ++ ++int s3c_fimd_set_display_mode(struct s3c_fimd_global *ctrl) ++{ ++ u32 cfg; ++ ++ cfg = readl(ctrl->regs + S3C_VIDCON0); ++ cfg &= ~S3C_VIDCON0_PNRMODE_MASK; ++ cfg |= (ctrl->rgb_mode << S3C_VIDCON0_PNRMODE_SHIFT); ++ ++ return 0; ++} ++ ++int s3c_fimd_display_on(struct s3c_fimd_global *ctrl) ++{ ++ u32 cfg; ++ ++ cfg = readl(ctrl->regs + S3C_VIDCON0); ++ cfg |= (S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE); ++ writel(cfg, ctrl->regs + S3C_VIDCON0); ++ ++ dev_dbg(ctrl->dev, "global display is on\n"); ++ ++ return 0; ++} ++ ++int s3c_fimd_display_off(struct s3c_fimd_global *ctrl) ++{ ++ u32 cfg; ++ ++ cfg = readl(ctrl->regs + S3C_VIDCON0); ++ cfg &= ~S3C_VIDCON0_ENVID_ENABLE; ++ writel(cfg, ctrl->regs + S3C_VIDCON0); ++ ++ cfg &= ~S3C_VIDCON0_ENVID_F_ENABLE; ++ writel(cfg, ctrl->regs + S3C_VIDCON0); ++ ++ dev_dbg(ctrl->dev, "global display is off\n"); ++ ++ return 0; ++} ++ ++int s3c_fimd_frame_off(struct s3c_fimd_global *ctrl) ++{ ++ u32 cfg; ++ ++ cfg = readl(ctrl->regs + S3C_VIDCON0); ++ cfg &= ~S3C_VIDCON0_ENVID_F_ENABLE; ++ writel(cfg, ctrl->regs + S3C_VIDCON0); ++ ++ dev_dbg(ctrl->dev, "current frame display is off\n"); ++ ++ return 0; ++} ++ ++int s3c_fimd_set_clock(struct s3c_fimd_global *ctrl) ++{ ++ struct s3c_platform_fimd *plat; ++ u32 cfg, maxclk, src_clk, vclk, div; ++ ++ plat = to_fimd_plat(ctrl->dev) ++ maxclk = 66 * 1000000; ++ ++ /* fixed clock source: hclk */ ++ cfg = readl(ctrl->regs + S3C_VIDCON0); ++ cfg &= ~(S3C_VIDCON0_CLKSEL_MASK | S3C_VIDCON0_CLKVALUP_MASK | \ ++ S3C_VIDCON0_VCLKEN_MASK | S3C_VIDCON0_CLKDIR_MASK); ++ cfg |= (S3C_VIDCON0_CLKSEL_HCLK | S3C_VIDCON0_CLKVALUP_ALWAYS | \ ++ S3C_VIDCON0_VCLKEN_NORMAL | S3C_VIDCON0_CLKDIR_DIVIDED); ++ ++ src_clk = ctrl->clock->parent->rate; ++ vclk = plat->clockrate; ++ ++ if (vclk > maxclk) ++ vclk = maxclk; ++ ++ div = (int) (src_clk / vclk); ++ ++ cfg |= S3C_VIDCON0_CLKVAL_F(div - 1); ++ writel(cfg, ctrl->regs + S3C_VIDCON0); ++ ++ return 0; ++} ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimd/s3c_fimd_cfg.c linux-2.6.28.6/drivers/media/video/samsung/fimd/s3c_fimd_cfg.c +--- linux-2.6.28/drivers/media/video/samsung/fimd/s3c_fimd_cfg.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimd/s3c_fimd_cfg.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,887 @@ ++/* linux/drivers/media/video/samsung/s3c_fimc_cfg.c ++ * ++ * Configuration support file for Samsung Camera Interface (FIMC) driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "s3c_fimc.h" ++ ++#if (CONFIG_VIDEO_SAMSUNG_MEMSIZE_FIMC > 0) ++static dma_addr_t s3c_fimc_get_dma_region(u32 bytes) ++{ ++ dma_addr_t end, addr, *curr; ++ ++ end = s3c_fimc.dma_start + s3c_fimc.dma_total; ++ curr = &s3c_fimc.dma_current; ++ ++ if (*curr + bytes > end) { ++ addr = 0; ++ } else { ++ addr = *curr; ++ *curr += bytes; ++ } ++ ++ return addr; ++} ++ ++static void s3c_fimc_put_dma_region(u32 bytes) ++{ ++ s3c_fimc.dma_current -= bytes; ++} ++ ++void s3c_fimc_free_output_memory(struct s3c_fimc_out_frame *info) ++{ ++ struct s3c_fimc_frame_addr *frame; ++ int i; ++ ++ for (i = 0; i < info->nr_frames; i++) { ++ frame = &info->addr[i]; ++ ++ if (frame->phys_y) ++ s3c_fimc_put_dma_region(info->buf_size); ++ ++ memset(frame, 0, sizeof(*frame)); ++ } ++ ++ info->buf_size = 0; ++} ++ ++static int s3c_fimc_alloc_rgb_memory(struct s3c_fimc_out_frame *info) ++{ ++ struct s3c_fimc_frame_addr *frame; ++ int i, ret, nr_frames = info->nr_frames; ++ ++ for (i = 0; i < nr_frames; i++) { ++ frame = &info->addr[i]; ++ ++ frame->phys_rgb = s3c_fimc_get_dma_region(info->buf_size); ++ if (frame->phys_rgb == 0) { ++ ret = -ENOMEM; ++ goto alloc_fail; ++ } ++ ++ frame->virt_rgb = phys_to_virt(frame->phys_rgb); ++ } ++ ++ for (i = nr_frames; i < S3C_FIMC_MAX_FRAMES; i++) { ++ frame = &info->addr[i]; ++ frame->phys_rgb = info->addr[i - nr_frames].phys_rgb; ++ frame->virt_rgb = info->addr[i - nr_frames].virt_rgb; ++ } ++ ++ return 0; ++ ++alloc_fail: ++ s3c_fimc_free_output_memory(info); ++ return ret; ++} ++ ++static int s3c_fimc_alloc_yuv_memory(struct s3c_fimc_out_frame *info) ++{ ++ struct s3c_fimc_frame_addr *frame; ++ int i, ret, nr_frames = info->nr_frames; ++ u32 size = info->width * info->height, cbcr_size; ++ ++ if (info->format == FORMAT_YCBCR420) ++ cbcr_size = size / 4; ++ else ++ cbcr_size = size / 2; ++ ++ for (i = 0; i < nr_frames; i++) { ++ frame = &info->addr[i]; ++ ++ frame->phys_y = s3c_fimc_get_dma_region(info->buf_size); ++ if (frame->phys_y == 0) { ++ ret = -ENOMEM; ++ goto alloc_fail; ++ } ++ ++ frame->phys_cb = frame->phys_y + size; ++ frame->phys_cr = frame->phys_cb + cbcr_size; ++ ++ frame->virt_y = phys_to_virt(frame->phys_y); ++ frame->virt_cb = frame->virt_y + size; ++ frame->virt_cr = frame->virt_cb + cbcr_size; ++ } ++ ++ for (i = nr_frames; i < S3C_FIMC_MAX_FRAMES; i++) { ++ frame = &info->addr[i]; ++ frame->phys_y = info->addr[i - nr_frames].phys_y; ++ frame->phys_cb = info->addr[i - nr_frames].phys_cb; ++ frame->phys_cr = info->addr[i - nr_frames].phys_cr; ++ frame->virt_y = info->addr[i - nr_frames].virt_y; ++ frame->virt_cb = info->addr[i - nr_frames].virt_cb; ++ frame->virt_cr = info->addr[i - nr_frames].virt_cr; ++ } ++ ++ return 0; ++ ++alloc_fail: ++ s3c_fimc_free_output_memory(info); ++ return ret; ++} ++ ++#else ++void s3c_fimc_free_output_memory(struct s3c_fimc_out_frame *info) ++{ ++ struct s3c_fimc_frame_addr *frame; ++ int i; ++ ++ for (i = 0; i < info->nr_frames; i++) { ++ frame = &info->addr[i]; ++ ++ if (frame->virt_y) ++ kfree(frame->virt_y); ++ ++ memset(frame, 0, sizeof(*frame)); ++ } ++ ++ info->buf_size = 0; ++} ++ ++static int s3c_fimc_alloc_rgb_memory(struct s3c_fimc_out_frame *info) ++{ ++ struct s3c_fimc_frame_addr *frame; ++ int i, ret, nr_frames = info->nr_frames; ++ ++ for (i = 0; i < nr_frames; i++) { ++ frame = &info->addr[i]; ++ ++ frame->virt_rgb = kmalloc(info->buf_size, GFP_DMA); ++ if (frame->virt_rgb == NULL) { ++ ret = -ENOMEM; ++ goto alloc_fail; ++ } ++ ++ frame->phys_rgb = virt_to_phys(frame->virt_rgb); ++ } ++ ++ for (i = nr_frames; i < S3C_FIMC_MAX_FRAMES; i++) { ++ frame = &info->addr[i]; ++ frame->virt_rgb = info->addr[i - nr_frames].virt_rgb; ++ frame->phys_rgb = info->addr[i - nr_frames].phys_rgb; ++ } ++ ++ return 0; ++ ++alloc_fail: ++ s3c_fimc_free_output_memory(info); ++ return ret; ++} ++ ++static int s3c_fimc_alloc_yuv_memory(struct s3c_fimc_out_frame *info) ++{ ++ struct s3c_fimc_frame_addr *frame; ++ int i, ret, nr_frames = info->nr_frames; ++ u32 size = info->width * info->height, cbcr_size; ++ ++ if (info->format == FORMAT_YCBCR420) ++ cbcr_size = size / 4; ++ else ++ cbcr_size = size / 2; ++ ++ for (i = 0; i < nr_frames; i++) { ++ frame = &info->addr[i]; ++ ++ frame->virt_y = kmalloc(info->buf_size, GFP_DMA); ++ if (frame->virt_y == NULL) { ++ ret = -ENOMEM; ++ goto alloc_fail; ++ } ++ ++ frame->virt_cb = frame->virt_y + size; ++ frame->virt_cr = frame->virt_cb + cbcr_size; ++ ++ frame->phys_y = virt_to_phys(frame->virt_y); ++ frame->phys_cb = frame->phys_y + size; ++ frame->phys_cr = frame->phys_cb + cbcr_size; ++ } ++ ++ for (i = nr_frames; i < S3C_FIMC_MAX_FRAMES; i++) { ++ frame = &info->addr[i]; ++ frame->phys_y = info->addr[i - nr_frames].phys_y; ++ frame->phys_cb = info->addr[i - nr_frames].phys_cb; ++ frame->phys_cr = info->addr[i - nr_frames].phys_cr; ++ frame->virt_y = info->addr[i - nr_frames].virt_y; ++ frame->virt_cb = info->addr[i - nr_frames].virt_cb; ++ frame->virt_cr = info->addr[i - nr_frames].virt_cr; ++ } ++ ++ return 0; ++ ++alloc_fail: ++ s3c_fimc_free_output_memory(info); ++ return ret; ++} ++#endif ++ ++static u32 s3c_fimc_get_buffer_size(int width, int height, enum s3c_fimc_format_t fmt) ++{ ++ u32 size = width * height; ++ u32 cbcr_size = 0, *buf_size = NULL, one_p_size; ++ ++ switch (fmt) { ++ case FORMAT_RGB565: ++ size *= 2; ++ buf_size = &size; ++ break; ++ ++ case FORMAT_RGB666: /* fall through */ ++ case FORMAT_RGB888: ++ size *= 4; ++ buf_size = &size; ++ break; ++ ++ case FORMAT_YCBCR420: ++ cbcr_size = size / 4; ++ one_p_size = size + (2 * cbcr_size); ++ buf_size = &one_p_size; ++ break; ++ ++ case FORMAT_YCBCR422: ++ cbcr_size = size / 2; ++ one_p_size = size + (2 * cbcr_size); ++ buf_size = &one_p_size; ++ break; ++ } ++ ++ if (*buf_size % PAGE_SIZE != 0) ++ *buf_size = (*buf_size / PAGE_SIZE + 1) * PAGE_SIZE; ++ ++ return *buf_size; ++} ++ ++int s3c_fimc_alloc_output_memory(struct s3c_fimc_out_frame *info) ++{ ++ int ret; ++ ++ info->buf_size = s3c_fimc_get_buffer_size(info->width, info->height, \ ++ info->format); ++ ++ if (info->format == FORMAT_YCBCR420 || info->format == FORMAT_YCBCR422) ++ ret = s3c_fimc_alloc_yuv_memory(info); ++ else ++ ret = s3c_fimc_alloc_rgb_memory(info); ++ ++ return ret; ++} ++ ++int s3c_fimc_alloc_input_memory(struct s3c_fimc_in_frame *info, dma_addr_t addr) ++{ ++ struct s3c_fimc_frame_addr *frame; ++ u32 size = info->width * info->height, cbcr_size; ++ ++ if (info->format == FORMAT_YCBCR420) ++ cbcr_size = size / 4; ++ else ++ cbcr_size = size / 2; ++ ++ info->buf_size = s3c_fimc_get_buffer_size(info->width, info->height, \ ++ info->format); ++ ++ switch (info->format) { ++ case FORMAT_RGB565: /* fall through */ ++ case FORMAT_RGB666: /* fall through */ ++ case FORMAT_RGB888: ++ info->addr.phys_rgb = addr; ++ break; ++ ++ case FORMAT_YCBCR420: /* fall through */ ++ case FORMAT_YCBCR422: ++ frame = &info->addr; ++ frame->phys_y = addr; ++ frame->phys_cb = frame->phys_y + size; ++ frame->phys_cr = frame->phys_cb + cbcr_size; ++ break; ++ } ++ ++ return 0; ++} ++ ++int s3c_fimc_alloc_y_memory(struct s3c_fimc_in_frame *info, ++ dma_addr_t addr) ++{ ++ info->addr.phys_y = addr; ++ info->buf_size = s3c_fimc_get_buffer_size(info->width, \ ++ info->height, info->format); ++ ++ return 0; ++} ++ ++int s3c_fimc_alloc_cb_memory(struct s3c_fimc_in_frame *info, ++ dma_addr_t addr) ++{ ++ info->addr.phys_cb = addr; ++ info->buf_size = s3c_fimc_get_buffer_size(info->width, \ ++ info->height, info->format); ++ ++ return 0; ++} ++ ++int s3c_fimc_alloc_cr_memory(struct s3c_fimc_in_frame *info, ++ dma_addr_t addr) ++{ ++ info->addr.phys_cr = addr; ++ info->buf_size = s3c_fimc_get_buffer_size(info->width, \ ++ info->height, info->format); ++ ++ return 0; ++} ++ ++void s3c_fimc_set_nr_frames(struct s3c_fimc_control *ctrl, int nr) ++{ ++ if (nr == 3) ++ ctrl->out_frame.nr_frames = 2; ++ else ++ ctrl->out_frame.nr_frames = nr; ++} ++ ++static void s3c_fimc_set_input_format(struct s3c_fimc_control *ctrl, ++ struct v4l2_pix_format *fmt) ++{ ++ struct s3c_fimc_in_frame *frame = &ctrl->in_frame; ++ ++ frame->width = fmt->width; ++ frame->height = fmt->height; ++ ++ switch (fmt->pixelformat) { ++ case V4L2_PIX_FMT_RGB565: ++ frame->format = FORMAT_RGB565; ++ frame->planes = 1; ++ break; ++ ++ case V4L2_PIX_FMT_RGB24: ++ frame->format = FORMAT_RGB888; ++ frame->planes = 1; ++ break; ++ ++ case V4L2_PIX_FMT_NV12: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = LSB_CBCR; ++ break; ++ ++ case V4L2_PIX_FMT_NV21: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = LSB_CRCB; ++ break; ++ ++ case V4L2_PIX_FMT_NV12X: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = MSB_CBCR; ++ break; ++ ++ case V4L2_PIX_FMT_NV21X: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = MSB_CRCB; ++ break; ++ ++ case V4L2_PIX_FMT_YUV420: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 3; ++ break; ++ ++ case V4L2_PIX_FMT_YUYV: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = IN_ORDER422_YCBYCR; ++ break; ++ ++ case V4L2_PIX_FMT_YVYU: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = IN_ORDER422_YCRYCB; ++ break; ++ ++ case V4L2_PIX_FMT_UYVY: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = IN_ORDER422_CBYCRY; ++ break; ++ ++ case V4L2_PIX_FMT_VYUY: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = IN_ORDER422_CRYCBY; ++ break; ++ ++ case V4L2_PIX_FMT_NV16: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = LSB_CBCR; ++ break; ++ ++ case V4L2_PIX_FMT_NV61: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = LSB_CRCB; ++ break; ++ ++ case V4L2_PIX_FMT_NV16X: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = MSB_CBCR; ++ break; ++ ++ case V4L2_PIX_FMT_NV61X: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = MSB_CRCB; ++ break; ++ ++ case V4L2_PIX_FMT_YUV422P: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 3; ++ break; ++ } ++} ++ ++int s3c_fimc_set_input_frame(struct s3c_fimc_control *ctrl, ++ struct v4l2_pix_format *fmt) ++{ ++ s3c_fimc_set_input_format(ctrl, fmt); ++ ++ return 0; ++} ++ ++static int s3c_fimc_set_output_format(struct s3c_fimc_control *ctrl, ++ struct v4l2_pix_format *fmt) ++{ ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ int depth = 0; ++ ++ frame->width = fmt->width; ++ frame->height = fmt->height; ++ ++ switch (fmt->pixelformat) { ++ case V4L2_PIX_FMT_RGB565: ++ frame->format = FORMAT_RGB565; ++ frame->planes = 1; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_RGB24: ++ frame->format = FORMAT_RGB888; ++ frame->planes = 1; ++ depth = 24; ++ break; ++ ++ case V4L2_PIX_FMT_NV12: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = LSB_CBCR; ++ depth = 12; ++ break; ++ ++ case V4L2_PIX_FMT_NV21: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = LSB_CRCB; ++ depth = 12; ++ break; ++ ++ case V4L2_PIX_FMT_NV12X: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = MSB_CBCR; ++ depth = 12; ++ break; ++ ++ case V4L2_PIX_FMT_NV21X: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = MSB_CRCB; ++ depth = 12; ++ break; ++ ++ case V4L2_PIX_FMT_YUV420: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 3; ++ depth = 12; ++ break; ++ ++ case V4L2_PIX_FMT_YUYV: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = OUT_ORDER422_YCBYCR; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_YVYU: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = OUT_ORDER422_YCRYCB; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_UYVY: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = OUT_ORDER422_CBYCRY; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_VYUY: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = OUT_ORDER422_CRYCBY; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_NV16: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = LSB_CBCR; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_NV61: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = LSB_CRCB; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_NV16X: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = MSB_CBCR; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_NV61X: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = MSB_CRCB; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_YUV422P: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 3; ++ depth = 16; ++ break; ++ } ++ ++ switch (fmt->field) { ++ case V4L2_FIELD_INTERLACED: ++ case V4L2_FIELD_INTERLACED_TB: ++ case V4L2_FIELD_INTERLACED_BT: ++ frame->scan = SCAN_TYPE_INTERLACE; ++ break; ++ ++ default: ++ frame->scan = SCAN_TYPE_PROGRESSIVE; ++ break; ++ } ++ ++ return depth; ++} ++ ++int s3c_fimc_set_output_frame(struct s3c_fimc_control *ctrl, ++ struct v4l2_pix_format *fmt) ++{ ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ int depth = 0; ++ ++ depth = s3c_fimc_set_output_format(ctrl, fmt); ++ ++ if (ctrl->out_type == PATH_OUT_DMA && frame->addr[0].virt_y == NULL) { ++ if (s3c_fimc_alloc_output_memory(frame)) ++ err("cannot allocate memory\n"); ++ } ++ ++ return depth; ++} ++ ++int s3c_fimc_frame_handler(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ int ret; ++ ++ frame->skip_frames++; ++ dev_dbg(ctrl->dev, "irq is being handled by frame hander\n"); ++ ++ switch (ctrl->flag & S3C_FIMC_IRQ_MASK) { ++ case S3C_FIMC_FLAG_IRQ_NORMAL: ++ dev_dbg(ctrl->dev, "irq flag is normal\n"); ++ FSET_RUNNING(ctrl); ++ FSET_IRQ_X(ctrl); ++ ret = S3C_FIMC_FRAME_SKIP; ++ break; ++ ++ case S3C_FIMC_FLAG_IRQ_X: ++ dev_dbg(ctrl->dev, "irq flag is x\n"); ++ s3c_fimc_enable_lastirq(ctrl); ++ s3c_fimc_disable_lastirq(ctrl); ++ FSET_HANDLE_IRQ(ctrl); ++ FSET_IRQ_LAST(ctrl); ++ ret = S3C_FIMC_FRAME_SKIP; ++ break; ++ ++ case S3C_FIMC_FLAG_IRQ_LAST: ++ dev_dbg(ctrl->dev, "irq flag is last\n"); ++ FSET_HANDLE_IRQ(ctrl); ++ FSET_IRQ_X(ctrl); ++ ret = S3C_FIMC_FRAME_TAKE; ++ break; ++ ++ default: ++ dev_dbg(ctrl->dev, "unknown irq state\n"); ++ ret = S3C_FIMC_FRAME_SKIP; ++ break; ++ } ++ ++ return ret; ++} ++ ++u8 *s3c_fimc_get_current_frame(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ ++ return frame->addr[frame->cfn].virt_y; ++} ++ ++static int s3c_fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift) ++{ ++ if (src >= tar * 64) { ++ err("out of pre-scaler range\n"); ++ return -EINVAL; ++ } else if (src >= tar * 32) { ++ *ratio = 32; ++ *shift = 5; ++ } else if (src >= tar * 16) { ++ *ratio = 16; ++ *shift = 4; ++ } else if (src >= tar * 8) { ++ *ratio = 8; ++ *shift = 3; ++ } else if (src >= tar * 4) { ++ *ratio = 4; ++ *shift = 2; ++ } else if (src >= tar * 2) { ++ *ratio = 2; ++ *shift = 1; ++ } else { ++ *ratio = 1; ++ *shift = 0; ++ } ++ ++ return 0; ++} ++ ++int s3c_fimc_set_scaler_info(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_scaler *sc = &ctrl->scaler; ++ struct s3c_fimc_window_offset *w_ofs = &ctrl->in_cam->offset; ++ struct s3c_fimc_dma_offset *d_ofs = &ctrl->in_frame.offset; ++ int ret, tx, ty, sx, sy; ++ int width, height, h_ofs, v_ofs; ++ ++ if (ctrl->in_type == PATH_IN_DMA) { ++ /* input rotator case */ ++ if (ctrl->rot90 && ctrl->out_type == PATH_OUT_LCDFIFO) { ++ width = ctrl->in_frame.height; ++ height = ctrl->in_frame.width; ++ h_ofs = d_ofs->y_v * 2; ++ v_ofs = d_ofs->y_h * 2; ++ } else { ++ width = ctrl->in_frame.width; ++ height = ctrl->in_frame.height; ++ h_ofs = d_ofs->y_h * 2; ++ v_ofs = d_ofs->y_v * 2; ++ } ++ } else { ++ width = ctrl->in_cam->width; ++ height = ctrl->in_cam->height; ++ h_ofs = w_ofs->h1 + w_ofs->h2; ++ v_ofs = w_ofs->v1 + w_ofs->v2; ++ } ++ ++ tx = ctrl->out_frame.width; ++ ty = ctrl->out_frame.height; ++ ++ if (tx <= 0 || ty <= 0) { ++ err("invalid target size\n"); ++ ret = -EINVAL; ++ goto err_size; ++ } ++ ++ sx = width - h_ofs; ++ sy = height - v_ofs; ++ ++ sc->real_width = sx; ++ sc->real_height = sy; ++ ++ if (sx <= 0 || sy <= 0) { ++ err("invalid source size\n"); ++ ret = -EINVAL; ++ goto err_size; ++ } ++ ++ s3c_fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor); ++ s3c_fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor); ++ ++ if (IS_PREVIEW(ctrl) && (sx / sc->pre_hratio > sc->line_length)) ++ info("line buffer size overflow\n"); ++ ++ sc->pre_dst_width = sx / sc->pre_hratio; ++ sc->pre_dst_height = sy / sc->pre_vratio; ++ ++ sc->main_hratio = (sx << 8) / (tx << sc->hfactor); ++ sc->main_vratio = (sy << 8) / (ty << sc->vfactor); ++ ++ sc->scaleup_h = (tx >= sx) ? 1 : 0; ++ sc->scaleup_v = (ty >= sy) ? 1 : 0; ++ ++ s3c_fimc_set_prescaler(ctrl); ++ s3c_fimc_set_scaler(ctrl); ++ ++ return 0; ++ ++err_size: ++ return ret; ++} ++ ++/* CAUTION: many sequence dependencies */ ++void s3c_fimc_start_dma(struct s3c_fimc_control *ctrl) ++{ ++ s3c_fimc_set_input_path(ctrl); ++ ++ if (ctrl->in_type == PATH_IN_DMA) { ++ s3c_fimc_set_input_address(ctrl); ++ s3c_fimc_set_input_dma(ctrl); ++ } else { ++ s3c_fimc_set_source_format(ctrl); ++ s3c_fimc_set_window_offset(ctrl); ++ s3c_fimc_set_polarity(ctrl); ++ } ++ ++ s3c_fimc_set_scaler_info(ctrl); ++ s3c_fimc_set_target_format(ctrl); ++ s3c_fimc_set_output_path(ctrl); ++ ++ if (ctrl->out_type == PATH_OUT_DMA) { ++ s3c_fimc_set_output_address(ctrl); ++ s3c_fimc_set_output_dma(ctrl); ++ } ++ ++ if (!ctrl->scaler.bypass) ++ s3c_fimc_start_scaler(ctrl); ++ ++ s3c_fimc_enable_capture(ctrl); ++ ++ if (ctrl->in_type == PATH_IN_DMA) ++ s3c_fimc_start_input_dma(ctrl); ++} ++ ++void s3c_fimc_stop_dma(struct s3c_fimc_control *ctrl) ++{ ++ if (ctrl->in_type == PATH_IN_DMA) ++ s3c_fimc_stop_input_dma(ctrl); ++ ++ s3c_fimc_stop_scaler(ctrl); ++ s3c_fimc_disable_capture(ctrl); ++ s3c_fimc_wait_frame_end(ctrl); ++} ++ ++void s3c_fimc_restart_dma(struct s3c_fimc_control *ctrl) ++{ ++ s3c_fimc_stop_dma(ctrl); ++ s3c_fimc_start_dma(ctrl); ++} ++ ++void s3c_fimc_change_resolution(struct s3c_fimc_control *ctrl, ++ enum s3c_fimc_cam_res_t res) ++{ ++ struct s3c_fimc_camera *cam = ctrl->in_cam; ++ ++ s3c_fimc_stop_scaler(ctrl); ++ s3c_fimc_i2c_command(ctrl, I2C_CAM_RESOLUTION, res); ++ ++ switch (res) { ++ case CAM_RES_QSVGA: ++ info("resolution changed to QSVGA (400x300) mode\n"); ++ cam->width = 400; ++ cam->height = 300; ++ break; ++ ++ case CAM_RES_VGA: ++ info("resolution changed to VGA (640x480) mode\n"); ++ cam->width = 640; ++ cam->height = 480; ++ break; ++ ++ case CAM_RES_SVGA: ++ info("resolution changed to SVGA (800x600) mode\n"); ++ cam->width = 800; ++ cam->height = 600; ++ break; ++ ++ case CAM_RES_SXGA: ++ info("resolution changed to SXGA (1280x1024) mode\n"); ++ cam->width = 1280; ++ cam->height = 1024; ++ break; ++ ++ case CAM_RES_UXGA: ++ info("resolution changed to UXGA (1600x1200) mode\n"); ++ cam->width = 1600; ++ cam->height = 1200; ++ break; ++ ++ case CAM_RES_DEFAULT: /* fall through */ ++ case CAM_RES_MAX: ++ /* nothing to do */ ++ break; ++ } ++} ++ ++int s3c_fimc_check_zoom(struct s3c_fimc_control *ctrl, int type) ++{ ++ struct s3c_fimc_scaler *sc = &ctrl->scaler; ++ struct s3c_fimc_window_offset *offset = &ctrl->in_cam->offset; ++ int sx = sc->real_width; ++ int zoom_pixels = S3C_FIMC_ZOOM_PIXELS * 2; ++ int zoom_size = sx - (offset->h1 + offset->h2 + zoom_pixels); ++ ++ switch (type) { ++ case V4L2_CID_ZOOM_IN: ++ if (zoom_size / sc->pre_hratio > sc->line_length) { ++ err("already reached to zoom-in boundary\n"); ++ return -EINVAL; ++ } ++ ++ sc->zoom_depth++; ++ break; ++ ++ case V4L2_CID_ZOOM_OUT: ++ if (sc->zoom_depth > 0) ++ sc->zoom_depth--; ++ else { ++ err("already reached to zoom-out boundary\n"); ++ return -EINVAL; ++ } ++ ++ break; ++ } ++ ++ return 0; ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimd/s3c_fimd_core.c linux-2.6.28.6/drivers/media/video/samsung/fimd/s3c_fimd_core.c +--- linux-2.6.28/drivers/media/video/samsung/fimd/s3c_fimd_core.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimd/s3c_fimd_core.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,555 @@ ++/* linux/drivers/media/video/samsung/s3c_fimc_core.c ++ * ++ * Core file for Samsung Camera Interface (FIMC) driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "s3c_fimc.h" ++ ++static struct s3c_fimc_camera test_pattern = { ++ .id = S3C_FIMC_TPID, ++ .type = CAM_TYPE_ITU, ++ .mode = ITU_601_YCBCR422_8BIT, ++ .order422 = CAM_ORDER422_8BIT_YCBYCR, ++ .clockrate = 0, ++ .width = 640, ++ .height = 480, ++ .offset = { ++ .h1 = 0, ++ .h2 = 0, ++ .v1 = 0, ++ .v2 = 0, ++ }, ++ ++ .polarity = { ++ .pclk = 0, ++ .vsync = 0, ++ .href = 0, ++ .hsync = 0, ++ }, ++ ++ .initialized = 0, ++}; ++ ++struct s3c_fimc_config s3c_fimc; ++ ++struct s3c_platform_fimc *to_fimc_plat(struct device *dev) ++{ ++ struct platform_device *pdev = to_platform_device(dev); ++ ++ return (struct s3c_platform_fimc *) pdev->dev.platform_data; ++} ++ ++u8 s3c_fimc_i2c_read(struct i2c_client *client, u8 subaddr) ++{ ++ u8 buf[1]; ++ struct i2c_msg msg = {client->addr, 0, 1, buf}; ++ int ret; ++ ++ buf[0] = subaddr; ++ ++ ret = i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO; ++ if (ret == -EIO) { ++ err("i2c transfer error\n"); ++ return -EIO; ++ } ++ ++ msg.flags = I2C_M_RD; ++ ret = i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO; ++ ++ return buf[0]; ++} ++ ++int s3c_fimc_i2c_write(struct i2c_client *client, u8 subaddr, u8 val) ++{ ++ u8 buf[2]; ++ struct i2c_msg msg = {client->addr, 0, 2, buf}; ++ ++ buf[0] = subaddr; ++ buf[1] = val; ++ ++ return i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO; ++} ++ ++void s3c_fimc_i2c_command(struct s3c_fimc_control *ctrl, u32 cmd, int arg) ++{ ++ struct i2c_client *client = ctrl->in_cam->client; ++ ++ if (client) ++ client->driver->command(client, cmd, (void *) arg); ++ else ++ err("i2c client is not registered\n"); ++} ++ ++void s3c_fimc_register_camera(struct s3c_fimc_camera *cam) ++{ ++ s3c_fimc.camera[cam->id] = cam; ++ ++ clk_disable(s3c_fimc.cam_clock); ++ clk_set_rate(s3c_fimc.cam_clock, cam->clockrate); ++ clk_enable(s3c_fimc.cam_clock); ++ ++ s3c_fimc_reset_camera(); ++} ++ ++void s3c_fimc_unregister_camera(struct s3c_fimc_camera *cam) ++{ ++ int i = 0; ++ ++ for (i = 0; i < S3C_FIMC_MAX_CTRLS; i++) { ++ if (s3c_fimc.ctrl[i].in_cam == cam) ++ s3c_fimc.ctrl[i].in_cam = NULL; ++ } ++ ++ s3c_fimc.camera[cam->id] = NULL; ++} ++ ++void s3c_fimc_set_active_camera(struct s3c_fimc_control *ctrl, int id) ++{ ++ ctrl->in_cam = s3c_fimc.camera[id]; ++ ++ if (ctrl->in_cam && id < S3C_FIMC_TPID) ++ s3c_fimc_select_camera(ctrl); ++} ++ ++void s3c_fimc_init_camera(struct s3c_fimc_control *ctrl) ++{ ++ struct s3c_fimc_camera *cam = ctrl->in_cam; ++ ++ if (cam && cam->id != S3C_FIMC_TPID && !cam->initialized) { ++ s3c_fimc_i2c_command(ctrl, I2C_CAM_INIT, 0); ++ s3c_fimc_change_resolution(ctrl, CAM_RES_DEFAULT); ++ cam->initialized = 1; ++ } ++} ++ ++static irqreturn_t s3c_fimc_irq(int irq, void *dev_id) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) dev_id; ++ ++ s3c_fimc_clear_irq(ctrl); ++ s3c_fimc_check_fifo(ctrl); ++ ++ if (IS_CAPTURE(ctrl)) { ++ dev_dbg(ctrl->dev, "irq is in capture state\n"); ++ ++ if (s3c_fimc_frame_handler(ctrl) == S3C_FIMC_FRAME_SKIP) ++ return IRQ_HANDLED; ++ ++ wake_up_interruptible(&ctrl->waitq); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static ++struct s3c_fimc_control *s3c_fimc_register_controller(struct platform_device *pdev) ++{ ++ struct s3c_platform_fimc *pdata; ++ struct s3c_fimc_control *ctrl; ++ struct resource *res; ++ int i = S3C_FIMC_MAX_CTRLS - 1; ++ int id = pdev->id; ++ ++ pdata = to_fimc_plat(&pdev->dev); ++ ++ ctrl = &s3c_fimc.ctrl[id]; ++ ctrl->id = id; ++ ctrl->dev = &pdev->dev; ++ ctrl->vd = &s3c_fimc_video_device[id]; ++ ctrl->rot90 = 0; ++ ctrl->vd->minor = id; ++ ctrl->out_frame.nr_frames = pdata->nr_frames; ++ ctrl->out_frame.skip_frames = 0; ++ ctrl->scaler.line_length = pdata->line_length; ++ ++ sprintf(ctrl->name, "%s%d", S3C_FIMC_NAME, id); ++ strcpy(ctrl->vd->name, ctrl->name); ++ ++ ctrl->open_lcdfifo = s3cfb_enable_local; ++ ctrl->close_lcdfifo = s3cfb_enable_dma; ++ ++ atomic_set(&ctrl->in_use, 0); ++ mutex_init(&ctrl->lock); ++ init_waitqueue_head(&ctrl->waitq); ++ ++ /* get resource for io memory */ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ err("failed to get io memory region\n"); ++ return NULL; ++ } ++ ++ if (!pdata->shared_io) { ++ /* request mem region */ ++ res = request_mem_region(res->start, res->end - res->start + 1, pdev->name); ++ if (!res) { ++ err("failed to request io memory region\n"); ++ return NULL; ++ } ++ ++ /* ioremap for register block */ ++ ctrl->regs = ioremap(res->start, res->end - res->start + 1); ++ } else { ++ while (i >= 0 && ctrl->regs == NULL) { ++ ctrl->regs = s3c_fimc.ctrl[i].regs; ++ i--; ++ } ++ } ++ ++ if (!ctrl->regs) { ++ err("failed to remap io region\n"); ++ return NULL; ++ } ++ ++ /* irq */ ++ ctrl->irq = platform_get_irq(pdev, 0); ++ if (request_irq(ctrl->irq, s3c_fimc_irq, IRQF_DISABLED, ctrl->name, ctrl)) ++ err("request_irq failed\n"); ++ ++ s3c_fimc_reset(ctrl); ++ s3c_fimc_set_active_camera(ctrl, 0); ++ ++ return ctrl; ++} ++ ++static int s3c_fimc_unregister_controller(struct platform_device *pdev) ++{ ++ struct s3c_fimc_control *ctrl; ++ struct s3c_platform_fimc *pdata; ++ int id = pdev->id; ++ ++ ctrl = &s3c_fimc.ctrl[id]; ++ ++ s3c_fimc_free_output_memory(&ctrl->out_frame); ++ ++ pdata = to_fimc_plat(ctrl->dev); ++ ++ if (!pdata->shared_io) ++ iounmap(ctrl->regs); ++ ++ memset(ctrl, 0, sizeof(*ctrl)); ++ ++ return 0; ++} ++ ++static int s3c_fimc_mmap(struct file* filp, struct vm_area_struct *vma) ++{ ++ struct s3c_fimc_control *ctrl = filp->private_data; ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ ++ u32 size = vma->vm_end - vma->vm_start; ++ u32 pfn, total_size = frame->buf_size; ++ ++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ vma->vm_flags |= VM_RESERVED; ++ ++ /* page frame number of the address for a source frame to be stored at. */ ++ pfn = __phys_to_pfn(frame->addr[vma->vm_pgoff].phys_y); ++ ++ if (size > total_size) { ++ err("the size of mapping is too big\n"); ++ return -EINVAL; ++ } ++ ++ if ((vma->vm_flags & VM_WRITE) && !(vma->vm_flags & VM_SHARED)) { ++ err("writable mapping must be shared\n"); ++ return -EINVAL; ++ } ++ ++ if (remap_pfn_range(vma, vma->vm_start, pfn, size, vma->vm_page_prot)) { ++ err("mmap fail\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static u32 s3c_fimc_poll(struct file *filp, poll_table *wait) ++{ ++ struct s3c_fimc_control *ctrl = filp->private_data; ++ u32 mask = 0; ++ ++ poll_wait(filp, &ctrl->waitq, wait); ++ ++ if (IS_IRQ_HANDLING(ctrl)) ++ mask = POLLIN | POLLRDNORM; ++ ++ FSET_STOP(ctrl); ++ ++ return mask; ++} ++ ++static ++ssize_t s3c_fimc_read(struct file *filp, char *buf, size_t count, loff_t *pos) ++{ ++ struct s3c_fimc_control *ctrl = filp->private_data; ++ size_t end; ++ ++ if (IS_CAPTURE(ctrl)) { ++ if (wait_event_interruptible(ctrl->waitq, IS_IRQ_HANDLING(ctrl))) ++ return -ERESTARTSYS; ++ ++ FSET_STOP(ctrl); ++ } ++ ++ end = min_t(size_t, ctrl->out_frame.buf_size, count); ++ ++ if (copy_to_user(buf, s3c_fimc_get_current_frame(ctrl), end)) ++ return -EFAULT; ++ ++ return end; ++} ++ ++static ++ssize_t s3c_fimc_write(struct file *filp, const char *b, size_t c, loff_t *offset) ++{ ++ return 0; ++} ++ ++static int s3c_fimc_open(struct inode *inode, struct file *filp) ++{ ++ struct s3c_fimc_control *ctrl; ++ int id, ret; ++ ++ id = MINOR(inode->i_rdev); ++ ctrl = &s3c_fimc.ctrl[id]; ++ ++ mutex_lock(&ctrl->lock); ++ ++ if (atomic_read(&ctrl->in_use)) { ++ ret = -EBUSY; ++ goto resource_busy; ++ } else { ++ atomic_inc(&ctrl->in_use); ++ s3c_fimc_reset(ctrl); ++ filp->private_data = ctrl; ++ } ++ ++ mutex_unlock(&ctrl->lock); ++ ++ return 0; ++ ++resource_busy: ++ mutex_unlock(&ctrl->lock); ++ return ret; ++} ++ ++static int s3c_fimc_release(struct inode *inode, struct file *filp) ++{ ++ struct s3c_fimc_control *ctrl; ++ int id; ++ ++ id = MINOR(inode->i_rdev); ++ ctrl = &s3c_fimc.ctrl[id]; ++ ++ mutex_lock(&ctrl->lock); ++ ++ atomic_dec(&ctrl->in_use); ++ filp->private_data = NULL; ++ ++ mutex_unlock(&ctrl->lock); ++ ++ return 0; ++} ++ ++static const struct file_operations s3c_fimc_fops = { ++ .owner = THIS_MODULE, ++ .open = s3c_fimc_open, ++ .release = s3c_fimc_release, ++ .ioctl = video_ioctl2, ++ .read = s3c_fimc_read, ++ .write = s3c_fimc_write, ++ .mmap = s3c_fimc_mmap, ++ .poll = s3c_fimc_poll, ++}; ++ ++static void s3c_fimc_vdev_release(struct video_device *vdev) ++{ ++ kfree(vdev); ++} ++ ++struct video_device s3c_fimc_video_device[S3C_FIMC_MAX_CTRLS] = { ++ [0] = { ++ .vfl_type = VID_TYPE_OVERLAY | VID_TYPE_CAPTURE | VID_TYPE_CLIPPING | VID_TYPE_SCALES, ++ .fops = &s3c_fimc_fops, ++ .ioctl_ops = &s3c_fimc_v4l2_ops, ++ .release = s3c_fimc_vdev_release, ++ }, ++ [1] = { ++ .vfl_type = VID_TYPE_OVERLAY | VID_TYPE_CAPTURE | VID_TYPE_CLIPPING | VID_TYPE_SCALES, ++ .fops = &s3c_fimc_fops, ++ .ioctl_ops = &s3c_fimc_v4l2_ops, ++ .release = s3c_fimc_vdev_release, ++ }, ++ [2] = { ++ .vfl_type = VID_TYPE_OVERLAY | VID_TYPE_CAPTURE | VID_TYPE_CLIPPING | VID_TYPE_SCALES, ++ .fops = &s3c_fimc_fops, ++ .ioctl_ops = &s3c_fimc_v4l2_ops, ++ .release = s3c_fimc_vdev_release, ++ }, ++}; ++ ++static int s3c_fimc_init_global(struct platform_device *pdev) ++{ ++ /* camera clock */ ++ s3c_fimc.cam_clock = clk_get(&pdev->dev, "sclk_cam"); ++ if (IS_ERR(s3c_fimc.cam_clock)) { ++ err("failed to get camera clock source\n"); ++ return -EINVAL; ++ } ++ ++ s3c_fimc.dma_start = s3c_get_media_memory(S3C_MDEV_FIMC); ++ s3c_fimc.dma_total = s3c_get_media_memsize(S3C_MDEV_FIMC); ++ s3c_fimc.dma_current = s3c_fimc.dma_start; ++ ++ /* test pattern */ ++ s3c_fimc.camera[test_pattern.id] = &test_pattern; ++ ++ return 0; ++} ++ ++static int s3c_fimc_probe(struct platform_device *pdev) ++{ ++ struct s3c_platform_fimc *pdata; ++ struct s3c_fimc_control *ctrl; ++ struct clk *srclk; ++ int ret; ++ ++ ctrl = s3c_fimc_register_controller(pdev); ++ if (!ctrl) { ++ err("cannot register fimc controller\n"); ++ goto err_fimc; ++ } ++ ++ pdata = to_fimc_plat(&pdev->dev); ++ if (pdata->cfg_gpio) ++ pdata->cfg_gpio(pdev); ++ ++ /* fimc source clock */ ++ srclk = clk_get(&pdev->dev, pdata->srclk_name); ++ if (IS_ERR(srclk)) { ++ err("failed to get source clock of fimc\n"); ++ goto err_clk_io; ++ } ++ ++ /* fimc clock */ ++ ctrl->clock = clk_get(&pdev->dev, pdata->clk_name); ++ if (IS_ERR(ctrl->clock)) { ++ err("failed to get fimc clock source\n"); ++ goto err_clk_io; ++ } ++ ++ /* set parent clock */ ++ if (ctrl->clock->set_parent) ++ ctrl->clock->set_parent(ctrl->clock, srclk); ++ ++ /* set clockrate for FIMC interface block */ ++ if (ctrl->clock->set_rate) ++ ctrl->clock->set_rate(ctrl->clock, pdata->clockrate); ++ ++ clk_enable(ctrl->clock); ++ ++ /* things to initialize once */ ++ if (ctrl->id == 0) { ++ ret = s3c_fimc_init_global(pdev); ++ if (ret) ++ goto err_global; ++ } ++ ++ ret = video_register_device(ctrl->vd, VFL_TYPE_GRABBER, ctrl->id); ++ if (ret) { ++ err("cannot register video driver\n"); ++ goto err_video; ++ } ++ ++ info("controller %d registered successfully\n", ctrl->id); ++ ++ return 0; ++ ++err_video: ++ clk_put(s3c_fimc.cam_clock); ++ ++err_global: ++ clk_disable(ctrl->clock); ++ clk_put(ctrl->clock); ++ ++err_clk_io: ++ s3c_fimc_unregister_controller(pdev); ++ ++err_fimc: ++ return -EINVAL; ++ ++} ++ ++static int s3c_fimc_remove(struct platform_device *pdev) ++{ ++ s3c_fimc_unregister_controller(pdev); ++ ++ return 0; ++} ++ ++int s3c_fimc_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ return 0; ++} ++ ++int s3c_fimc_resume(struct platform_device *dev) ++{ ++ return 0; ++} ++ ++static struct platform_driver s3c_fimc_driver = { ++ .probe = s3c_fimc_probe, ++ .remove = s3c_fimc_remove, ++ .suspend = s3c_fimc_suspend, ++ .resume = s3c_fimc_resume, ++ .driver = { ++ .name = "s3c-fimc", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int s3c_fimc_register(void) ++{ ++ platform_driver_register(&s3c_fimc_driver); ++ ++ return 0; ++} ++ ++static void s3c_fimc_unregister(void) ++{ ++ platform_driver_unregister(&s3c_fimc_driver); ++} ++ ++module_init(s3c_fimc_register); ++module_exit(s3c_fimc_unregister); ++ ++MODULE_AUTHOR("Jinsung, Yang "); ++MODULE_DESCRIPTION("Samsung Camera Interface (FIMC) driver"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/fimd/s3c_fimd_v4l2.c linux-2.6.28.6/drivers/media/video/samsung/fimd/s3c_fimd_v4l2.c +--- linux-2.6.28/drivers/media/video/samsung/fimd/s3c_fimd_v4l2.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/fimd/s3c_fimd_v4l2.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,755 @@ ++/* linux/drivers/media/video/samsung/s3c_fimc_v4l2.c ++ * ++ * V4L2 interface support file for Samsung Camera Interface (FIMC) driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "s3c_fimc.h" ++ ++static struct v4l2_input s3c_fimc_input_types[] = { ++ { ++ .index = 0, ++ .name = "External Camera Input", ++ .type = V4L2_INPUT_TYPE_CAMERA, ++ .audioset = 1, ++ .tuner = 0, ++ .std = V4L2_STD_PAL_BG | V4L2_STD_NTSC_M, ++ .status = 0, ++ }, ++ { ++ .index = 1, ++ .name = "Memory Input", ++ .type = V4L2_INPUT_TYPE_MEMORY, ++ .audioset = 2, ++ .tuner = 0, ++ .std = V4L2_STD_PAL_BG | V4L2_STD_NTSC_M, ++ .status = 0, ++ } ++}; ++ ++static struct v4l2_output s3c_fimc_output_types[] = { ++ { ++ .index = 0, ++ .name = "Memory Output", ++ .type = V4L2_OUTPUT_TYPE_MEMORY, ++ .audioset = 0, ++ .modulator = 0, ++ .std = 0, ++ }, ++ { ++ .index = 1, ++ .name = "LCD FIFO Output", ++ .type = V4L2_OUTPUT_TYPE_LCDFIFO, ++ .audioset = 0, ++ .modulator = 0, ++ .std = 0, ++ } ++}; ++ ++const static struct v4l2_fmtdesc s3c_fimc_capture_formats[] = { ++ { ++ .index = 0, ++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, ++ .flags = FORMAT_FLAGS_PLANAR, ++ .description = "4:2:0, planar, Y-Cb-Cr", ++ .pixelformat = V4L2_PIX_FMT_YUV420, ++ }, ++ { ++ .index = 1, ++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, ++ .flags = FORMAT_FLAGS_PLANAR, ++ .description = "4:2:2, planar, Y-Cb-Cr", ++ .pixelformat = V4L2_PIX_FMT_YUV422P, ++ ++ }, ++ { ++ .index = 2, ++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, ++ .flags = FORMAT_FLAGS_PACKED, ++ .description = "4:2:2, packed, YCBYCR", ++ .pixelformat = V4L2_PIX_FMT_YUYV, ++ }, ++ { ++ .index = 3, ++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, ++ .flags = FORMAT_FLAGS_PACKED, ++ .description = "4:2:2, packed, CBYCRY", ++ .pixelformat = V4L2_PIX_FMT_UYVY, ++ } ++}; ++ ++const static struct v4l2_fmtdesc s3c_fimc_overlay_formats[] = { ++ { ++ .index = 0, ++ .type = V4L2_BUF_TYPE_VIDEO_OVERLAY, ++ .flags = FORMAT_FLAGS_PACKED, ++ .description = "16 bpp RGB, le", ++ .pixelformat = V4L2_PIX_FMT_RGB565, ++ }, ++ { ++ .index = 1, ++ .type = V4L2_BUF_TYPE_VIDEO_OVERLAY, ++ .flags = FORMAT_FLAGS_PACKED, ++ .description = "24 bpp RGB, le", ++ .pixelformat = V4L2_PIX_FMT_RGB24, ++ }, ++}; ++ ++#define S3C_FIMC_MAX_INPUT_TYPES ARRAY_SIZE(s3c_fimc_input_types) ++#define S3C_FIMC_MAX_OUTPUT_TYPES ARRAY_SIZE(s3c_fimc_output_types) ++#define S3C_FIMC_MAX_CAPTURE_FORMATS ARRAY_SIZE(s3c_fimc_capture_formats) ++#define S3C_FIMC_MAX_OVERLAY_FORMATS ARRAY_SIZE(s3c_fimc_overlay_formats) ++ ++static int s3c_fimc_v4l2_querycap(struct file *filp, void *fh, ++ struct v4l2_capability *cap) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ strcpy(cap->driver, "Samsung FIMC Driver"); ++ strlcpy(cap->card, ctrl->vd->name, sizeof(cap->card)); ++ sprintf(cap->bus_info, "FIMC AHB-bus"); ++ ++ cap->version = 0; ++ cap->capabilities = (V4L2_CAP_VIDEO_OVERLAY | \ ++ V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING); ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_g_fbuf(struct file *filp, void *fh, ++ struct v4l2_framebuffer *fb) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ *fb = ctrl->v4l2.frmbuf; ++ ++ fb->base = ctrl->v4l2.frmbuf.base; ++ fb->capability = V4L2_FBUF_CAP_LIST_CLIPPING; ++ ++ fb->fmt.pixelformat = ctrl->v4l2.frmbuf.fmt.pixelformat; ++ fb->fmt.width = ctrl->v4l2.frmbuf.fmt.width; ++ fb->fmt.height = ctrl->v4l2.frmbuf.fmt.height; ++ fb->fmt.bytesperline = ctrl->v4l2.frmbuf.fmt.bytesperline; ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_s_fbuf(struct file *filp, void *fh, ++ struct v4l2_framebuffer *fb) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ struct v4l2_framebuffer *frmbuf = &(ctrl->v4l2.frmbuf); ++ int i, bpp; ++ ++ for (i = 0; i < S3C_FIMC_MAX_OVERLAY_FORMATS; i++) { ++ if (s3c_fimc_overlay_formats[i].pixelformat == fb->fmt.pixelformat) ++ break; ++ } ++ ++ if (i == S3C_FIMC_MAX_OVERLAY_FORMATS) ++ return -EINVAL; ++ ++ bpp = s3c_fimc_set_output_frame(ctrl, &fb->fmt); ++ ++ frmbuf->base = fb->base; ++ frmbuf->flags = fb->flags; ++ frmbuf->capability = fb->capability; ++ frmbuf->fmt.width = fb->fmt.width; ++ frmbuf->fmt.height = fb->fmt.height; ++ frmbuf->fmt.field = fb->fmt.field; ++ frmbuf->fmt.pixelformat = fb->fmt.pixelformat; ++ frmbuf->fmt.bytesperline = fb->fmt.width * bpp / 8; ++ frmbuf->fmt.sizeimage = fb->fmt.width * frmbuf->fmt.bytesperline; ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_enum_fmt_vid_cap(struct file *filp, void *fh, ++ struct v4l2_fmtdesc *f) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ int index = f->index; ++ ++ if (index >= S3C_FIMC_MAX_CAPTURE_FORMATS) ++ return -EINVAL; ++ ++ memset(f, 0, sizeof(*f)); ++ memcpy(f, ctrl->v4l2.fmtdesc + index, sizeof(*f)); ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_g_fmt_vid_cap(struct file *filp, void *fh, ++ struct v4l2_format *f) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ int size = sizeof(struct v4l2_pix_format); ++ ++ memset(&f->fmt.pix, 0, size); ++ memcpy(&f->fmt.pix, &(ctrl->v4l2.frmbuf.fmt), size); ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_s_fmt_vid_cap(struct file *filp, void *fh, ++ struct v4l2_format *f) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ ctrl->v4l2.frmbuf.fmt = f->fmt.pix; ++ ++ if (f->fmt.pix.priv == V4L2_FMT_IN) ++ s3c_fimc_set_input_frame(ctrl, &f->fmt.pix); ++ else ++ s3c_fimc_set_output_frame(ctrl, &f->fmt.pix); ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_try_fmt_vid_cap(struct file *filp, void *fh, ++ struct v4l2_format *f) ++{ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_try_fmt_overlay(struct file *filp, void *fh, ++ struct v4l2_format *f) ++{ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_overlay(struct file *filp, void *fh, unsigned int i) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ if (i) { ++ if (ctrl->in_type != PATH_IN_DMA) ++ s3c_fimc_init_camera(ctrl); ++ ++ FSET_PREVIEW(ctrl); ++ s3c_fimc_start_dma(ctrl); ++ } else { ++ s3c_fimc_stop_dma(ctrl); ++ ++ if (ctrl->out_type != PATH_OUT_LCDFIFO) { ++ s3c_fimc_free_output_memory(&ctrl->out_frame); ++ s3c_fimc_set_output_address(ctrl); ++ } ++ } ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_g_ctrl(struct file *filp, void *fh, ++ struct v4l2_control *c) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ ++ switch (c->id) { ++ case V4L2_CID_OUTPUT_ADDR: ++ c->value = frame->addr[c->value].phys_y; ++ break; ++ ++ default: ++ err("invalid control id: %d\n", c->id); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_s_ctrl(struct file *filp, void *fh, ++ struct v4l2_control *c) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ struct s3c_fimc_window_offset *offset = &ctrl->in_cam->offset; ++ ++ switch (c->id) { ++ case V4L2_CID_EFFECT_ORIGINAL: ++ frame->effect.type = EFFECT_ORIGINAL; ++ s3c_fimc_change_effect(ctrl); ++ break; ++ ++ case V4L2_CID_EFFECT_NEGATIVE: ++ frame->effect.type = EFFECT_NEGATIVE; ++ s3c_fimc_change_effect(ctrl); ++ break; ++ ++ case V4L2_CID_EFFECT_EMBOSSING: ++ frame->effect.type = EFFECT_EMBOSSING; ++ s3c_fimc_change_effect(ctrl); ++ break; ++ ++ case V4L2_CID_EFFECT_ARTFREEZE: ++ frame->effect.type = EFFECT_ARTFREEZE; ++ s3c_fimc_change_effect(ctrl); ++ break; ++ ++ case V4L2_CID_EFFECT_SILHOUETTE: ++ frame->effect.type = EFFECT_SILHOUETTE; ++ s3c_fimc_change_effect(ctrl); ++ break; ++ ++ case V4L2_CID_EFFECT_ARBITRARY: ++ frame->effect.type = EFFECT_ARBITRARY; ++ frame->effect.pat_cb = PAT_CB(c->value); ++ frame->effect.pat_cr = PAT_CR(c->value); ++ s3c_fimc_change_effect(ctrl); ++ break; ++ ++ case V4L2_CID_ROTATE_ORIGINAL: ++ frame->flip = FLIP_ORIGINAL; ++ ctrl->rot90 = 0; ++ s3c_fimc_change_rotate(ctrl); ++ break; ++ ++ case V4L2_CID_HFLIP: ++ frame->flip = FLIP_X_AXIS; ++ ctrl->rot90 = 0; ++ s3c_fimc_change_rotate(ctrl); ++ break; ++ ++ case V4L2_CID_VFLIP: ++ frame->flip = FLIP_Y_AXIS; ++ ctrl->rot90 = 0; ++ s3c_fimc_change_rotate(ctrl); ++ break; ++ ++ case V4L2_CID_ROTATE_180: ++ frame->flip = FLIP_XY_AXIS; ++ ctrl->rot90 = 0; ++ s3c_fimc_change_rotate(ctrl); ++ break; ++ ++ case V4L2_CID_ROTATE_90: ++ frame->flip = FLIP_ORIGINAL; ++ ctrl->rot90 = 1; ++ s3c_fimc_change_rotate(ctrl); ++ break; ++ ++ case V4L2_CID_ROTATE_270: ++ frame->flip = FLIP_XY_AXIS; ++ ctrl->rot90 = 1; ++ s3c_fimc_change_rotate(ctrl); ++ break; ++ ++ case V4L2_CID_ROTATE_90_HFLIP: ++ frame->flip = FLIP_X_AXIS; ++ ctrl->rot90 = 1; ++ s3c_fimc_change_rotate(ctrl); ++ break; ++ ++ case V4L2_CID_ROTATE_90_VFLIP: ++ frame->flip = FLIP_Y_AXIS; ++ ctrl->rot90 = 1; ++ s3c_fimc_change_rotate(ctrl); ++ break; ++ ++ case V4L2_CID_ZOOM_IN: ++ if (s3c_fimc_check_zoom(ctrl, c->id) == 0) { ++ offset->h1 += S3C_FIMC_ZOOM_PIXELS; ++ offset->h2 += S3C_FIMC_ZOOM_PIXELS; ++ offset->v1 += S3C_FIMC_ZOOM_PIXELS; ++ offset->v2 += S3C_FIMC_ZOOM_PIXELS; ++ s3c_fimc_restart_dma(ctrl); ++ } ++ ++ break; ++ ++ case V4L2_CID_ZOOM_OUT: ++ if (s3c_fimc_check_zoom(ctrl, c->id) == 0) { ++ offset->h1 -= S3C_FIMC_ZOOM_PIXELS; ++ offset->h2 -= S3C_FIMC_ZOOM_PIXELS; ++ offset->v1 -= S3C_FIMC_ZOOM_PIXELS; ++ offset->v2 -= S3C_FIMC_ZOOM_PIXELS; ++ s3c_fimc_restart_dma(ctrl); ++ } ++ ++ break; ++ ++ case V4L2_CID_AUTO_WHITE_BALANCE: ++ s3c_fimc_i2c_command(ctrl, I2C_CAM_WB, c->value); ++ break; ++ ++ case V4L2_CID_ACTIVE_CAMERA: ++ s3c_fimc_set_active_camera(ctrl, c->value); ++ s3c_fimc_i2c_command(ctrl, I2C_CAM_WB, WB_AUTO); ++ break; ++ ++ case V4L2_CID_TEST_PATTERN: ++ s3c_fimc_set_active_camera(ctrl, S3C_FIMC_TPID); ++ s3c_fimc_set_test_pattern(ctrl, c->value); ++ break; ++ ++ case V4L2_CID_NR_FRAMES: ++ s3c_fimc_set_nr_frames(ctrl, c->value); ++ break; ++ ++ case V4L2_CID_INPUT_ADDR: ++ s3c_fimc_alloc_input_memory(&ctrl->in_frame, \ ++ (dma_addr_t) c->value); ++ s3c_fimc_set_input_address(ctrl); ++ break; ++ ++ case V4L2_CID_INPUT_ADDR_Y: ++ case V4L2_CID_INPUT_ADDR_RGB: ++ s3c_fimc_alloc_y_memory(&ctrl->in_frame, \ ++ (dma_addr_t) c->value); ++ s3c_fimc_set_input_address(ctrl); ++ break; ++ ++ case V4L2_CID_INPUT_ADDR_CB: /* fall through */ ++ case V4L2_CID_INPUT_ADDR_CBCR: ++ s3c_fimc_alloc_cb_memory(&ctrl->in_frame, \ ++ (dma_addr_t) c->value); ++ s3c_fimc_set_input_address(ctrl); ++ break; ++ ++ case V4L2_CID_INPUT_ADDR_CR: ++ s3c_fimc_alloc_cr_memory(&ctrl->in_frame, \ ++ (dma_addr_t) c->value); ++ s3c_fimc_set_input_address(ctrl); ++ break; ++ ++ case V4L2_CID_RESET: ++ ctrl->rot90 = 0; ++ ctrl->in_frame.flip = FLIP_ORIGINAL; ++ ctrl->out_frame.flip = FLIP_ORIGINAL; ++ ctrl->out_frame.effect.type = EFFECT_ORIGINAL; ++ ctrl->scaler.bypass = 0; ++ s3c_fimc_reset(ctrl); ++ break; ++ ++ case V4L2_CID_JPEG_INPUT: /* fall through */ ++ case V4L2_CID_SCALER_BYPASS: ++ ctrl->scaler.bypass = 1; ++ break; ++ ++ default: ++ err("invalid control id: %d\n", c->id); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_streamon(struct file *filp, void *fh, ++ enum v4l2_buf_type i) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ if (i != V4L2_BUF_TYPE_VIDEO_CAPTURE) ++ return -EINVAL; ++ ++ if (ctrl->in_type != PATH_IN_DMA) ++ s3c_fimc_init_camera(ctrl); ++ ++ ctrl->out_frame.skip_frames = 0; ++ FSET_CAPTURE(ctrl); ++ FSET_IRQ_NORMAL(ctrl); ++ s3c_fimc_start_dma(ctrl); ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_streamoff(struct file *filp, void *fh, ++ enum v4l2_buf_type i) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ if (i != V4L2_BUF_TYPE_VIDEO_CAPTURE) ++ return -EINVAL; ++ ++ FSET_STOP(ctrl); ++ UNMASK_USAGE(ctrl); ++ UNMASK_IRQ(ctrl); ++ ++ s3c_fimc_stop_dma(ctrl); ++ s3c_fimc_free_output_memory(&ctrl->out_frame); ++ s3c_fimc_set_output_address(ctrl); ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_g_input(struct file *filp, void *fh, ++ unsigned int *i) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ *i = ctrl->v4l2.input->index; ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_s_input(struct file *filp, void *fh, ++ unsigned int i) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ if (i >= S3C_FIMC_MAX_INPUT_TYPES) ++ return -EINVAL; ++ ++ ctrl->v4l2.input = &s3c_fimc_input_types[i]; ++ ++ if (s3c_fimc_input_types[i].type == V4L2_INPUT_TYPE_CAMERA) ++ ctrl->in_type = PATH_IN_ITU_CAMERA; ++ else ++ ctrl->in_type = PATH_IN_DMA; ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_g_output(struct file *filp, void *fh, ++ unsigned int *i) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ *i = ctrl->v4l2.output->index; ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_s_output(struct file *filp, void *fh, ++ unsigned int i) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ if (i >= S3C_FIMC_MAX_OUTPUT_TYPES) ++ return -EINVAL; ++ ++ ctrl->v4l2.output = &s3c_fimc_output_types[i]; ++ ++ if (s3c_fimc_output_types[i].type == V4L2_OUTPUT_TYPE_MEMORY) ++ ctrl->out_type = PATH_OUT_DMA; ++ else ++ ctrl->out_type = PATH_OUT_LCDFIFO; ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_enum_input(struct file *filp, void *fh, ++ struct v4l2_input *i) ++{ ++ if (i->index >= S3C_FIMC_MAX_INPUT_TYPES) ++ return -EINVAL; ++ ++ memcpy(i, &s3c_fimc_input_types[i->index], sizeof(struct v4l2_input)); ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_enum_output(struct file *filp, void *fh, ++ struct v4l2_output *o) ++{ ++ if ((o->index) >= S3C_FIMC_MAX_OUTPUT_TYPES) ++ return -EINVAL; ++ ++ memcpy(o, &s3c_fimc_output_types[o->index], sizeof(struct v4l2_output)); ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_reqbufs(struct file *filp, void *fh, ++ struct v4l2_requestbuffers *b) ++{ ++ if (b->memory != V4L2_MEMORY_MMAP) { ++ err("V4L2_MEMORY_MMAP is only supported\n"); ++ return -EINVAL; ++ } ++ ++ /* control user input */ ++ if (b->count > 4) ++ b->count = 4; ++ else if (b->count < 1) ++ b->count = 1; ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_querybuf(struct file *filp, void *fh, ++ struct v4l2_buffer *b) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ if (b->type != V4L2_BUF_TYPE_VIDEO_OVERLAY && \ ++ b->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) ++ return -EINVAL; ++ ++ if (b->memory != V4L2_MEMORY_MMAP) ++ return -EINVAL; ++ ++ b->length = ctrl->out_frame.buf_size; ++ ++ /* ++ * NOTE: we use the m.offset as an index for multiple frames out. ++ * Because all frames are not contiguous, we cannot use it as ++ * original purpose. ++ * The index value used to find out which frame user wants to mmap. ++ */ ++ b->m.offset = b->index * PAGE_SIZE; ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_qbuf(struct file *filp, void *fh, ++ struct v4l2_buffer *b) ++{ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_dqbuf(struct file *filp, void *fh, ++ struct v4l2_buffer *b) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ struct s3c_fimc_out_frame *frame = &ctrl->out_frame; ++ ++ ctrl->out_frame.cfn = s3c_fimc_get_frame_count(ctrl); ++ b->index = (frame->cfn + 2) % frame->nr_frames; ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_cropcap(struct file *filp, void *fh, ++ struct v4l2_cropcap *a) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && ++ a->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) ++ return -EINVAL; ++ ++ /* crop limitations */ ++ ctrl->v4l2.crop_bounds.left = 0; ++ ctrl->v4l2.crop_bounds.top = 0; ++ ctrl->v4l2.crop_bounds.width = ctrl->in_cam->width; ++ ctrl->v4l2.crop_bounds.height = ctrl->in_cam->height; ++ ++ /* crop default values */ ++ ctrl->v4l2.crop_defrect.left = \ ++ (ctrl->in_cam->width - S3C_FIMC_CROP_DEF_WIDTH) / 2; ++ ++ ctrl->v4l2.crop_defrect.top = \ ++ (ctrl->in_cam->height - S3C_FIMC_CROP_DEF_HEIGHT) / 2; ++ ++ ctrl->v4l2.crop_defrect.width = S3C_FIMC_CROP_DEF_WIDTH; ++ ctrl->v4l2.crop_defrect.height = S3C_FIMC_CROP_DEF_HEIGHT; ++ ++ a->bounds = ctrl->v4l2.crop_bounds; ++ a->defrect = ctrl->v4l2.crop_defrect; ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_g_crop(struct file *filp, void *fh, ++ struct v4l2_crop *a) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && ++ a->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) ++ return -EINVAL; ++ ++ a->c = ctrl->v4l2.crop_current; ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_s_crop(struct file *filp, void *fh, ++ struct v4l2_crop *a) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ struct s3c_fimc_camera *cam = ctrl->in_cam; ++ ++ if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && ++ a->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) ++ return -EINVAL; ++ ++ if (a->c.height < 0) ++ return -EINVAL; ++ ++ if (a->c.width < 0) ++ return -EINVAL; ++ ++ if ((a->c.left + a->c.width > cam->width) || \ ++ (a->c.top + a->c.height > cam->height)) ++ return -EINVAL; ++ ++ ctrl->v4l2.crop_current = a->c; ++ ++ cam->offset.h1 = (cam->width - a->c.width) / 2; ++ cam->offset.v1 = (cam->height - a->c.height) / 2; ++ ++ cam->offset.h2 = cam->offset.h1; ++ cam->offset.v2 = cam->offset.v1; ++ ++ s3c_fimc_restart_dma(ctrl); ++ ++ return 0; ++} ++ ++static int s3c_fimc_v4l2_s_parm(struct file *filp, void *fh, ++ struct v4l2_streamparm *a) ++{ ++ struct s3c_fimc_control *ctrl = (struct s3c_fimc_control *) fh; ++ ++ if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) ++ return -EINVAL; ++ ++ if (a->parm.capture.capturemode == V4L2_MODE_HIGHQUALITY) { ++ info("changing to max resolution\n"); ++ s3c_fimc_change_resolution(ctrl, CAM_RES_MAX); ++ } else { ++ info("changing to default resolution\n"); ++ s3c_fimc_change_resolution(ctrl, CAM_RES_DEFAULT); ++ } ++ ++ s3c_fimc_restart_dma(ctrl); ++ ++ return 0; ++} ++ ++const struct v4l2_ioctl_ops s3c_fimc_v4l2_ops = { ++ .vidioc_querycap = s3c_fimc_v4l2_querycap, ++ .vidioc_g_fbuf = s3c_fimc_v4l2_g_fbuf, ++ .vidioc_s_fbuf = s3c_fimc_v4l2_s_fbuf, ++ .vidioc_enum_fmt_vid_cap = s3c_fimc_v4l2_enum_fmt_vid_cap, ++ .vidioc_g_fmt_vid_cap = s3c_fimc_v4l2_g_fmt_vid_cap, ++ .vidioc_s_fmt_vid_cap = s3c_fimc_v4l2_s_fmt_vid_cap, ++ .vidioc_try_fmt_vid_cap = s3c_fimc_v4l2_try_fmt_vid_cap, ++ .vidioc_try_fmt_vid_overlay = s3c_fimc_v4l2_try_fmt_overlay, ++ .vidioc_overlay = s3c_fimc_v4l2_overlay, ++ .vidioc_g_ctrl = s3c_fimc_v4l2_g_ctrl, ++ .vidioc_s_ctrl = s3c_fimc_v4l2_s_ctrl, ++ .vidioc_streamon = s3c_fimc_v4l2_streamon, ++ .vidioc_streamoff = s3c_fimc_v4l2_streamoff, ++ .vidioc_g_input = s3c_fimc_v4l2_g_input, ++ .vidioc_s_input = s3c_fimc_v4l2_s_input, ++ .vidioc_g_output = s3c_fimc_v4l2_g_output, ++ .vidioc_s_output = s3c_fimc_v4l2_s_output, ++ .vidioc_enum_input = s3c_fimc_v4l2_enum_input, ++ .vidioc_enum_output = s3c_fimc_v4l2_enum_output, ++ .vidioc_reqbufs = s3c_fimc_v4l2_reqbufs, ++ .vidioc_querybuf = s3c_fimc_v4l2_querybuf, ++ .vidioc_qbuf = s3c_fimc_v4l2_qbuf, ++ .vidioc_dqbuf = s3c_fimc_v4l2_dqbuf, ++ .vidioc_cropcap = s3c_fimc_v4l2_cropcap, ++ .vidioc_g_crop = s3c_fimc_v4l2_g_crop, ++ .vidioc_s_crop = s3c_fimc_v4l2_s_crop, ++ .vidioc_s_parm = s3c_fimc_v4l2_s_parm, ++}; +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/g2d/Kconfig linux-2.6.28.6/drivers/media/video/samsung/g2d/Kconfig +--- linux-2.6.28/drivers/media/video/samsung/g2d/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/g2d/Kconfig 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,11 @@ ++# ++# Configuration for FIMG-2D ++# ++ ++config VIDEO_G2D ++ bool "Samsung FIMG-2D Driver" ++ depends on VIDEO_SAMSUNG && (CPU_S3C6410 || CPU_S5PC100) ++ default n ++ ---help--- ++ This is a FIMG-2D(2D accelerator) driver for Samsung S3C6410 and S5PC100. ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/g2d/Makefile linux-2.6.28.6/drivers/media/video/samsung/g2d/Makefile +--- linux-2.6.28/drivers/media/video/samsung/g2d/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/g2d/Makefile 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,10 @@ ++################################################# ++# Makefile for FIMG-2D ++# 2009 (C) Samsung Electronics ++# Author : Jonghun Han ++################################################# ++ ++obj-$(CONFIG_VIDEO_G2D) += s3c_fimg2d2x.o ++ ++EXTRA_CFLAGS += -Idrivers/media/video ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/g2d/s3c_fimg2d2x.c linux-2.6.28.6/drivers/media/video/samsung/g2d/s3c_fimg2d2x.c +--- linux-2.6.28/drivers/media/video/samsung/g2d/s3c_fimg2d2x.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/g2d/s3c_fimg2d2x.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,611 @@ ++/* linux/drivers/media/video/samsung/g2d/s3c_fimg2d2x.c ++ * ++ * Driver file for Samsung 2D Accelerator(FIMG-2D) ++ * ++ * Jonghun Han, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "s3c_fimg2d2x.h" ++ ++static struct clk *s3c_g2d_clock; ++static struct clk *h_clk; ++ ++static int s3c_g2d_irq_num = NO_IRQ; ++static struct resource *s3c_g2d_mem; ++static void __iomem *s3c_g2d_base; ++static wait_queue_head_t waitq_g2d; ++ ++static struct mutex *h_rot_mutex; ++ ++static u16 s3c_g2d_poll_flag = 0; ++ ++void s3c_g2d_check_fifo(int empty_fifo) ++{ ++ u32 val; ++ ++ val = __raw_readl(s3c_g2d_base + S3C_G2D_FIFO_STAT_REG); ++ while( S3C_G2D_FIFO_USED(val) > (FIFO_NUM - empty_fifo)); ++} ++ ++ ++static int s3c_g2d_init_regs(s3c_g2d_params *params) ++{ ++ u32 bpp_mode; ++ u32 tmp_reg; ++ s3c_g2d_check_fifo(25); ++ ++ ++ switch(params->bpp) { ++ case ARGB8: ++ bpp_mode = S3C_G2D_COLOR_MODE_REG_C0_15BPP; ++ break; ++ ++ case RGB16: ++ bpp_mode = S3C_G2D_COLOR_RGB_565; ++ break; ++ ++ case RGB18: ++ bpp_mode = S3C_G2D_COLOR_MODE_REG_C2_18BPP; ++ break; ++ ++ case RGB24: ++ bpp_mode = S3C_G2D_COLOR_XRGB_8888; ++ break; ++ ++ default: ++ bpp_mode = S3C_G2D_COLOR_MODE_REG_C3_24BPP; ++ break; ++ } ++ ++ /*set register for soruce image ===============================*/ ++ __raw_writel(params->src_base_addr, s3c_g2d_base + S3C_G2D_SRC_BASE_ADDR); ++ __raw_writel(params->src_full_width, s3c_g2d_base + S3C_G2D_HORI_RES_REG); ++ __raw_writel(params->src_full_height, s3c_g2d_base + S3C_G2D_VERT_RES_REG); ++ __raw_writel((S3C_G2D_FULL_V(params->src_full_height) | ++ S3C_G2D_FULL_H(params->src_full_width)), ++ s3c_g2d_base+S3C_G2D_SRC_RES_REG); ++ __raw_writel(bpp_mode, s3c_g2d_base + S3C_G2D_SRC_COLOR_MODE); ++ ++ /*set register for destination image =============================*/ ++ __raw_writel(params->dst_base_addr, s3c_g2d_base + S3C_G2D_DST_BASE_ADDR); ++ __raw_writel(params->dst_full_width, s3c_g2d_base + S3C_G2D_SC_HORI_REG); ++ __raw_writel(params->dst_full_height, s3c_g2d_base + S3C_G2D_SC_VERT_REG); ++ __raw_writel((S3C_G2D_FULL_V(params->dst_full_height) | ++ S3C_G2D_FULL_H(params->dst_full_width)), ++ s3c_g2d_base+S3C_G2D_SC_RES_REG); ++ __raw_writel(bpp_mode, s3c_g2d_base + S3C_G2D_DST_COLOR_MODE); ++ ++ /*set register for clipping window===============================*/ ++ __raw_writel(params->cw_x1, s3c_g2d_base + S3C_G2D_CW_LT_X_REG); ++ __raw_writel(params->cw_y1, s3c_g2d_base + S3C_G2D_CW_LT_Y_REG); ++ __raw_writel(params->cw_x2, s3c_g2d_base + S3C_G2D_CW_RB_X_REG); ++ __raw_writel(params->cw_y2, s3c_g2d_base + S3C_G2D_CW_RB_Y_REG); ++ ++ /*set register for color=======================================*/ ++ __raw_writel(params->color_val[G2D_WHITE], s3c_g2d_base + S3C_G2D_FG_COLOR_REG); /* set color to both font and foreground color */ ++ __raw_writel(params->color_val[G2D_BLACK], s3c_g2d_base + S3C_G2D_BG_COLOR_REG); ++ __raw_writel(params->color_val[G2D_BLUE], s3c_g2d_base + S3C_G2D_BS_COLOR_REG); /* Set blue color to blue screen color */ ++ ++ /*set register for ROP & Alpha==================================*/ ++ if(params->alpha_mode == TRUE) { ++ if(params->alpha_val > ALPHA_VALUE_MAX) { ++ printk(KERN_ALERT "s3c g2d dirver error: exceed alpha value range 0~255\n"); ++ return -ENOENT; ++ } ++ ++ __raw_writel(S3C_G2D_ROP_REG_OS_FG_COLOR | ++ S3C_G2D_ROP_REG_ABM_REGISTER | ++ S3C_G2D_ROP_REG_T_OPAQUE_MODE | ++ G2D_ROP_SRC_ONLY, ++ s3c_g2d_base + S3C_G2D_ROP_REG); ++ __raw_writel(S3C_G2D_ALPHA(params->alpha_val), s3c_g2d_base + S3C_G2D_ALPHA_REG); ++ } else { ++ __raw_writel(S3C_G2D_ROP_REG_OS_FG_COLOR | ++ S3C_G2D_ROP_REG_ABM_NO_BLENDING | ++ S3C_G2D_ROP_REG_T_OPAQUE_MODE | ++ G2D_ROP_SRC_ONLY, ++ s3c_g2d_base + S3C_G2D_ROP_REG); ++ __raw_writel(S3C_G2D_ALPHA(0x00), s3c_g2d_base + S3C_G2D_ALPHA_REG); ++ } ++ ++ /*set register for color key====================================*/ ++ if(params->color_key_mode == TRUE) { ++ tmp_reg = __raw_readl(s3c_g2d_base + S3C_G2D_ROP_REG); ++ tmp_reg |= S3C_G2D_ROP_REG_T_TRANSP_MODE ; ++ __raw_writel(tmp_reg , s3c_g2d_base + S3C_G2D_ROP_REG); ++ __raw_writel(params->color_key_val, s3c_g2d_base + S3C_G2D_BS_COLOR_REG); ++ } ++ ++ /*set register for rotation=====================================*/ ++ __raw_writel(S3C_G2D_ROTATRE_REG_R0_0, s3c_g2d_base + S3C_G2D_ROT_OC_X_REG); ++ __raw_writel(S3C_G2D_ROTATRE_REG_R0_0, s3c_g2d_base + S3C_G2D_ROT_OC_Y_REG); ++ __raw_writel(S3C_G2D_ROTATRE_REG_R0_0, s3c_g2d_base + S3C_G2D_ROTATE_REG); ++ ++ return 0; ++} ++ ++ ++void s3c_g2d_bitblt(u16 src_x1, u16 src_y1, u16 src_x2, u16 src_y2, ++ u16 dst_x1, u16 dst_y1, u16 dst_x2, u16 dst_y2) ++{ ++ u32 cmd_reg_val; ++ ++ s3c_g2d_check_fifo(25); ++ ++ __raw_writel(src_x1, s3c_g2d_base + S3C_G2D_COORD0_X_REG); ++ __raw_writel(src_y1, s3c_g2d_base + S3C_G2D_COORD0_Y_REG); ++ __raw_writel(src_x2, s3c_g2d_base + S3C_G2D_COORD1_X_REG); ++ __raw_writel(src_y2, s3c_g2d_base + S3C_G2D_COORD1_Y_REG); ++ ++ __raw_writel(dst_x1, s3c_g2d_base + S3C_G2D_COORD2_X_REG); ++ __raw_writel(dst_y1, s3c_g2d_base + S3C_G2D_COORD2_Y_REG); ++ __raw_writel(dst_x2, s3c_g2d_base + S3C_G2D_COORD3_X_REG); ++ __raw_writel(dst_y2, s3c_g2d_base + S3C_G2D_COORD3_Y_REG); ++ ++ cmd_reg_val = readl(s3c_g2d_base + S3C_G2D_CMD1_REG); ++ cmd_reg_val = ~(S3C_G2D_CMD1_REG_S|S3C_G2D_CMD1_REG_N); ++ cmd_reg_val |= S3C_G2D_CMD1_REG_N; ++ __raw_writel(cmd_reg_val, s3c_g2d_base + S3C_G2D_CMD1_REG); ++} ++ ++ ++static void s3c_g2d_rotate_with_bitblt(s3c_g2d_params *params, ROT_DEG rot_degree) ++{ ++ u16 org_x=0, org_y=0; ++ u32 rot_reg_val = 0; ++ u32 src_x1, src_y1, src_x2, src_y2, dst_x1, dst_y1, dst_x2, dst_y2; ++ ++ src_x1 = params->src_start_x; ++ src_y1 = params->src_start_y; ++ src_x2 = params->src_start_x + params->src_work_width; ++ src_y2 = params->src_start_y + params->src_work_height; ++ dst_x1 = params->dst_start_x; ++ dst_y1 = params->dst_start_y; ++ dst_x2 = params->dst_start_x + params->dst_work_width; ++ dst_y2 = params->dst_start_y + params->dst_work_height; ++ ++ s3c_g2d_check_fifo(25); ++ __raw_writel(S3C_G2D_INTEN_REG_CCF, s3c_g2d_base + S3C_G2D_INTEN_REG); ++ ++ s3c_g2d_get_rotation_origin(src_x1, src_y1, src_x2, src_y2, ++ dst_x1, dst_y1, rot_degree, &org_x, &org_y); ++ if(rot_degree != (ROT_0||ROT_X_FLIP||ROT_Y_FLIP)){ ++ org_x += 1; ++ org_y += 1; ++ } ++ __raw_writel(org_x, s3c_g2d_base + S3C_G2D_ROT_OC_X_REG); ++ __raw_writel(org_y, s3c_g2d_base + S3C_G2D_ROT_OC_Y_REG); ++ ++ switch(rot_degree) { ++ case ROT_0: ++ rot_reg_val = S3C_G2D_ROTATRE_REG_R0_0; ++ break; ++ ++ case ROT_90: ++ rot_reg_val = S3C_G2D_ROTATRE_REG_R1_90; ++ break; ++ ++ case ROT_180: ++ rot_reg_val = S3C_G2D_ROTATRE_REG_R2_180; ++ break; ++ ++ case ROT_270: ++ rot_reg_val = S3C_G2D_ROTATRE_REG_R3_270; ++ break; ++ ++ case ROT_X_FLIP: ++ rot_reg_val = S3C_G2D_ROTATRE_REG_FX; ++ break; ++ ++ case ROT_Y_FLIP: ++ rot_reg_val = S3C_G2D_ROTATRE_REG_FY; ++ break; ++ ++ default: ++ printk(KERN_ERR "[%s : %d] Wrong rotation degree\n", __FUNCTION__, __LINE__); ++ break; ++ } ++ __raw_writel(rot_reg_val, s3c_g2d_base + S3C_G2D_ROTATE_REG); ++ ++ switch(rot_degree) { ++ case ROT_0: /* fall through */ ++ case ROT_X_FLIP: /* fall through */ ++ case ROT_Y_FLIP: ++ s3c_g2d_bitblt(src_x1, src_y1, src_x2, src_y2, ++ dst_x1, dst_y1, dst_x2, dst_y2); ++ break; ++ ++ case ROT_90: ++ s3c_g2d_bitblt(src_x1, src_y1, src_x2, src_y2, src_x1, ++ src_y1+1, src_x2, src_y2+1); ++ break; ++ ++ case ROT_180: ++ s3c_g2d_bitblt(src_x1, src_y1, src_x2, src_y2, src_x1+1, ++ src_y1+1, src_x2+1, src_y2+1); ++ break; ++ ++ case ROT_270: ++ s3c_g2d_bitblt(src_x1, src_y1, src_x2, src_y2, src_x1+1, ++ src_y1, src_x2+1, src_y2); ++ break; ++ ++ default: ++ break; ++ } ++} ++ ++ ++static void s3c_g2d_get_rotation_origin(u16 src_x1, u16 src_y1, ++ u16 src_x2, u16 src_y2, ++ u16 dst_x1, u16 dst_y1, ++ ROT_DEG rot_degree, ++ u16* org_x, u16* org_y) ++{ ++ s3c_g2d_check_fifo(25); ++ ++ switch(rot_degree) { ++ case ROT_90: ++ *org_x = ((dst_x1 - dst_y1 + src_x1 + src_y2)>>1); ++ *org_y = ((dst_x1 + dst_y1 - src_x1 + src_y2)>>1); ++ break; ++ ++ case ROT_180: /* fall through */ ++ case ROT_X_FLIP: /* fall through */ ++ case ROT_Y_FLIP: ++ *org_x = ((dst_x1 + src_x2)>>1); ++ *org_y = ((dst_y1 + src_y2)>>1); ++ break; ++ ++ case ROT_270: ++ *org_x = ((dst_x1 + dst_y1 + src_x2 - src_y1)>>1); ++ *org_y = ((dst_y1 - dst_x1 + src_x2 + src_y1)>>1); ++ break; ++ ++ case ROT_0: /* fall through */ ++ default: ++ break; ++ } ++} ++ ++ ++static void s3c_g2d_rotator_start(s3c_g2d_params *params, ROT_DEG rot_degree) ++{ ++ ++ s3c_g2d_init_regs(params); ++ s3c_g2d_rotate_with_bitblt(params, rot_degree); ++} ++ ++ ++irqreturn_t s3c_g2d_irq(int irq, void *dev_id) ++{ ++ if(__raw_readl(s3c_g2d_base + S3C_G2D_INTC_PEND_REG) & S3C_G2D_PEND_REG_INTP_CMD_FIN) { ++ __raw_writel ( S3C_G2D_PEND_REG_INTP_CMD_FIN, s3c_g2d_base + S3C_G2D_INTC_PEND_REG ); ++ wake_up_interruptible(&waitq_g2d); ++ s3c_g2d_poll_flag = 1; ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++ ++int s3c_g2d_open(struct inode *inode, struct file *file) ++{ ++ s3c_g2d_params *params; ++ params = (s3c_g2d_params *)kmalloc(sizeof(s3c_g2d_params), GFP_KERNEL); ++ if(params == NULL) { ++ printk(KERN_ERR "Instance memory allocation was failed\n"); ++ return -1; ++ } ++ ++ memset(params, 0, sizeof(s3c_g2d_params)); ++ ++ file->private_data = (s3c_g2d_params *)params; ++ ++ printk("s3c_g2d_open() \n"); ++ ++ return 0; ++} ++ ++ ++int s3c_g2d_release(struct inode *inode, struct file *file) ++{ ++ s3c_g2d_params *params; ++ ++ params = (s3c_g2d_params *)file->private_data; ++ if (params == NULL) { ++ printk(KERN_ERR "Can't release s3c_rotator!!\n"); ++ return -1; ++ } ++ ++ kfree(params); ++ ++ printk("s3c_g2d_release() \n"); ++ ++ return 0; ++} ++ ++ ++int s3c_g2d_mmap(struct file* filp, struct vm_area_struct *vma) ++{ ++ unsigned long pageFrameNo = 0; ++ unsigned long size; ++ ++ size = vma->vm_end - vma->vm_start; ++ ++ // page frame number of the address for a source G2D_SFR_SIZE to be stored at. ++ pageFrameNo = __phys_to_pfn(s3c_g2d_mem->start); ++ ++ if(size > G2D_SFR_SIZE) { ++ printk("The size of G2D_SFR_SIZE mapping is too big!\n"); ++ return -EINVAL; ++ } ++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ ++ if((vma->vm_flags & VM_WRITE) && !(vma->vm_flags & VM_SHARED)) { ++ printk("Writable G2D_SFR_SIZE mapping must be shared !\n"); ++ return -EINVAL; ++ } ++ ++ if(remap_pfn_range(vma, vma->vm_start, pageFrameNo, size, vma->vm_page_prot)) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++ ++static int s3c_g2d_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ s3c_g2d_params *params; ++ ROT_DEG rot_degree; ++ ++ params = (s3c_g2d_params*)file->private_data; ++ if (copy_from_user(params, (s3c_g2d_params*)arg, sizeof(s3c_g2d_params))) ++ return -EFAULT; ++ ++ mutex_lock(h_rot_mutex); ++ ++ switch(cmd) { ++ case S3C_G2D_ROTATOR_0: ++ rot_degree = ROT_0; ++ s3c_g2d_rotator_start(params, rot_degree); ++ break; ++ ++ case S3C_G2D_ROTATOR_90: ++ rot_degree = ROT_90; ++ s3c_g2d_rotator_start(params, rot_degree); ++ break; ++ ++ case S3C_G2D_ROTATOR_180: ++ rot_degree = ROT_180; ++ s3c_g2d_rotator_start(params, rot_degree); ++ break; ++ ++ case S3C_G2D_ROTATOR_270: ++ rot_degree = ROT_270; ++ s3c_g2d_rotator_start(params, rot_degree); ++ break; ++ ++ case S3C_G2D_ROTATOR_X_FLIP: ++ rot_degree = ROT_X_FLIP; ++ s3c_g2d_rotator_start(params, rot_degree); ++ break; ++ ++ case S3C_G2D_ROTATOR_Y_FLIP: ++ rot_degree = ROT_Y_FLIP; ++ s3c_g2d_rotator_start(params, rot_degree); ++ break; ++ ++ default: ++ mutex_unlock(h_rot_mutex); ++ return -EINVAL; ++ } ++ ++ if(!(file->f_flags & O_NONBLOCK)) { ++ if (interruptible_sleep_on_timeout(&waitq_g2d, G2D_TIMEOUT) == 0) { ++ printk(KERN_ERR "\n%s: Waiting for interrupt is timeout\n", __FUNCTION__); ++ } ++ } ++ ++ mutex_unlock(h_rot_mutex); ++ ++ return 0; ++ ++} ++ ++ ++static unsigned int s3c_g2d_poll(struct file *file, poll_table *wait) ++{ ++ unsigned int mask = 0; ++ ++ poll_wait(file, &waitq_g2d, wait); ++ if(s3c_g2d_poll_flag == 1) { ++ mask = POLLOUT|POLLWRNORM; ++ s3c_g2d_poll_flag = 0; ++ } ++ ++ return mask; ++} ++ ++ ++struct file_operations s3c_g2d_fops = { ++ .owner = THIS_MODULE, ++ .open = s3c_g2d_open, ++ .release = s3c_g2d_release, ++ .mmap = s3c_g2d_mmap, ++ .ioctl = s3c_g2d_ioctl, ++ .poll = s3c_g2d_poll, ++}; ++ ++ ++static struct miscdevice s3c_g2d_dev = { ++ .minor = G2D_MINOR, ++ .name = "s3c-g2d", ++ .fops = &s3c_g2d_fops, ++}; ++ ++ ++int s3c_g2d_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ int ret; ++ printk(KERN_ALERT"s3c_g2d_probe called\n"); ++ ++ /* find the IRQs */ ++ s3c_g2d_irq_num = platform_get_irq(pdev, 0); ++ if(s3c_g2d_irq_num <= 0) { ++ printk(KERN_ERR "failed to get irq resouce\n"); ++ return -ENOENT; ++ } ++ ++ ret = request_irq(s3c_g2d_irq_num, s3c_g2d_irq, IRQF_DISABLED, pdev->name, NULL); ++ if (ret) { ++ printk("request_irq(g2d) failed.\n"); ++ return ret; ++ } ++ ++ ++ /* get the memory region */ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if(res == NULL) { ++ printk(KERN_ERR "failed to get memory region resouce\n"); ++ return -ENOENT; ++ } ++ ++ s3c_g2d_mem = request_mem_region(res->start, res->end-res->start+1, pdev->name); ++ if(s3c_g2d_mem == NULL) { ++ printk(KERN_ERR "failed to reserve memory region\n"); ++ return -ENOENT; ++ } ++ ++ ++ s3c_g2d_base = ioremap(s3c_g2d_mem->start, s3c_g2d_mem->end - res->start + 1); ++ if(s3c_g2d_base == NULL) { ++ printk(KERN_ERR "failed ioremap\n"); ++ return -ENOENT; ++ } ++ ++ s3c_g2d_clock = clk_get(&pdev->dev, "g2d"); ++ if(s3c_g2d_clock == NULL) { ++ printk(KERN_ERR "failed to find g2d clock source\n"); ++ return -ENOENT; ++ } ++ ++ clk_enable(s3c_g2d_clock); ++ ++ h_clk = clk_get(&pdev->dev, "hclk"); ++ if(h_clk == NULL) { ++ printk(KERN_ERR "failed to find h_clk clock source\n"); ++ return -ENOENT; ++ } ++ ++ init_waitqueue_head(&waitq_g2d); ++ ++ ret = misc_register(&s3c_g2d_dev); ++ if (ret) { ++ printk (KERN_ERR "cannot register miscdev on minor=%d (%d)\n", ++ G2D_MINOR, ret); ++ return ret; ++ } ++ ++ h_rot_mutex = (struct mutex *)kmalloc(sizeof(struct mutex), GFP_KERNEL); ++ if (h_rot_mutex == NULL) ++ return -1; ++ ++ mutex_init(h_rot_mutex); ++ ++ printk(KERN_ALERT" s3c_g2d_probe Success\n"); ++ ++ return 0; ++} ++ ++ ++static int s3c_g2d_remove(struct platform_device *dev) ++{ ++ printk(KERN_INFO "s3c_g2d_remove called !\n"); ++ ++ free_irq(s3c_g2d_irq_num, NULL); ++ ++ if (s3c_g2d_mem != NULL) { ++ printk(KERN_INFO "S3C Rotator Driver, releasing resource\n"); ++ iounmap(s3c_g2d_base); ++ release_resource(s3c_g2d_mem); ++ kfree(s3c_g2d_mem); ++ } ++ ++ misc_deregister(&s3c_g2d_dev); ++ printk(KERN_INFO "s3c_g2d_remove Success !\n"); ++ return 0; ++} ++ ++ ++static int s3c_g2d_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ clk_disable(s3c_g2d_clock); ++ return 0; ++} ++ ++ ++static int s3c_g2d_resume(struct platform_device *pdev) ++{ ++ clk_enable(s3c_g2d_clock); ++ return 0; ++} ++ ++ ++static struct platform_driver s3c_g2d_driver = { ++ .probe = s3c_g2d_probe, ++ .remove = s3c_g2d_remove, ++ .suspend = s3c_g2d_suspend, ++ .resume = s3c_g2d_resume, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "s3c-g2d", ++ }, ++}; ++ ++ ++int __init s3c_g2d_init(void) ++{ ++ if(platform_driver_register(&s3c_g2d_driver) != 0) { ++ printk("platform device register Failed \n"); ++ return -1; ++ } ++ ++ printk(" S3C G2D Init : Done\n"); ++ return 0; ++} ++ ++ ++void s3c_g2d_exit(void) ++{ ++ platform_driver_unregister(&s3c_g2d_driver); ++ mutex_destroy(h_rot_mutex); ++} ++ ++module_init(s3c_g2d_init); ++module_exit(s3c_g2d_exit); ++ ++MODULE_AUTHOR("Jonghun Han "); ++MODULE_DESCRIPTION("S3C FIMG-2D Device Driver"); ++MODULE_LICENSE("GPL"); +\ No newline at end of file +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/g2d/s3c_fimg2d2x.h linux-2.6.28.6/drivers/media/video/samsung/g2d/s3c_fimg2d2x.h +--- linux-2.6.28/drivers/media/video/samsung/g2d/s3c_fimg2d2x.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/g2d/s3c_fimg2d2x.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,147 @@ ++/* linux/drivers/media/video/samsung/g2d/s3c_fimg2d2x.h ++ * ++ * Driver header file for Samsung 2D Accelerator(FIMG-2D) ++ * ++ * Jonghun Han, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_G2D_DRIVER_H_ ++#define _S3C_G2D_DRIVER_H_ ++ ++#define G2D_SFR_SIZE 0x1000 ++ ++#define TRUE 1 ++#define FALSE 0 ++ ++#define G2D_MINOR 220 // Just some number ++ ++#define G2D_IOCTL_MAGIC 'G' ++ ++#define S3C_G2D_ROTATOR_0 _IO(G2D_IOCTL_MAGIC,0) ++#define S3C_G2D_ROTATOR_90 _IO(G2D_IOCTL_MAGIC,1) ++#define S3C_G2D_ROTATOR_180 _IO(G2D_IOCTL_MAGIC,2) ++#define S3C_G2D_ROTATOR_270 _IO(G2D_IOCTL_MAGIC,3) ++#define S3C_G2D_ROTATOR_X_FLIP _IO(G2D_IOCTL_MAGIC,4) ++#define S3C_G2D_ROTATOR_Y_FLIP _IO(G2D_IOCTL_MAGIC,5) ++ ++#define FIFO_NUM 32 ++ ++#define G2D_TIMEOUT 100 ++#define ALPHA_VALUE_MAX 255 ++ ++#define G2D_MAX_WIDTH (2048) ++#define G2D_MAX_HEIGHT (2048) ++ ++#define G2D_ROP_SRC_ONLY (0xf0) ++#define G2D_ROP_3RD_OPRND_ONLY (0xaa) ++#define G2D_ROP_DST_ONLY (0xcc) ++#define G2D_ROP_SRC_OR_DST (0xfc) ++#define G2D_ROP_SRC_OR_3RD_OPRND (0xfa) ++#define G2D_ROP_SRC_AND_DST (0xc0) //(pat==1)? src:dst ++#define G2D_ROP_SRC_AND_3RD_OPRND (0xa0) ++#define G2D_ROP_SRC_XOR_3RD_OPRND (0x5a) ++#define G2D_ROP_DST_OR_3RD_OPRND (0xee) ++ ++#define ABS(v) (((v)>=0) ? (v):(-(v))) ++ ++typedef enum ++{ ++ ROT_0, ROT_90, ROT_180, ROT_270, ROT_X_FLIP, ROT_Y_FLIP ++} ROT_DEG; ++ ++ ++typedef enum ++{ ++ ROP_DST_ONLY, ++ ROP_SRC_ONLY, ++ ROP_3RD_OPRND_ONLY, ++ ROP_SRC_AND_DST, ++ ROP_SRC_AND_3RD_OPRND, ++ ROP_SRC_OR_DST, ++ ROP_SRC_OR_3RD_OPRND, ++ ROP_DST_OR_3RD, ++ ROP_SRC_XOR_3RD_OPRND ++ ++} G2D_ROP_TYPE; ++ ++typedef enum ++{ ++ G2D_NO_ALPHA_MODE, ++ G2D_PP_ALPHA_SOURCE_MODE, ++ G2D_ALPHA_MODE, ++ G2D_FADING_MODE ++} G2D_ALPHA_BLENDING_MODE; ++ ++typedef enum ++{ ++ G2D_BLACK = 0, G2D_RED = 1, G2D_GREEN = 2, G2D_BLUE = 3, G2D_WHITE = 4, ++ G2D_YELLOW = 5, G2D_CYAN = 6, G2D_MAGENTA = 7 ++} G2D_COLOR; ++ ++ ++typedef enum ++{ ++ PAL1, PAL2, PAL4, PAL8, ++ RGB8, ARGB8, RGB16, ARGB16, RGB18, RGB24, RGB30, ARGB24,RGBA16,RGBX24,RGBA24, ++ YC420, YC422, // Non-interleave ++ CRYCBY, CBYCRY, YCRYCB, YCBYCR, YUV444 // Interleave ++} G2D_COLOR_SPACE; ++ ++typedef struct ++{ ++ u32 src_base_addr; //Base address of the source image ++ u32 src_full_width; //source image full width ++ u32 src_full_height; //source image full height ++ u32 src_start_x; //coordinate start x of source image ++ u32 src_start_y; //coordinate start y of source image ++ u32 src_work_width; //source image width for work ++ u32 src_work_height; //source image height for work ++ ++ u32 dst_base_addr; //Base address of the destination image ++ u32 dst_full_width; //destination screen full width ++ u32 dst_full_height; //destination screen full width ++ u32 dst_start_x; //coordinate start x of destination screen ++ u32 dst_start_y; //coordinate start y of destination screen ++ u32 dst_work_width; //destination screen width for work ++ u32 dst_work_height; //destination screen height for work ++ ++ // Coordinate (X, Y) of clipping window ++ u32 cw_x1, cw_y1; ++ u32 cw_x2, cw_y2; ++ ++ u32 color_val[8]; ++ G2D_COLOR_SPACE bpp; ++ ++ u32 alpha_mode; //true : enable, false : disable ++ u32 alpha_val; ++ u32 color_key_mode; //treu : enable, false : disable ++ u32 color_key_val; //transparent color value ++ ++}s3c_g2d_params; ++ ++/**** function declearation***************************/ ++static int s3c_g2d_init_regs(s3c_g2d_params *params); ++void s3c_g2d_bitblt(u16 src_x1, u16 src_y1, u16 src_x2, u16 src_y2, ++ u16 dst_x1, u16 dst_y1, u16 dst_x2, u16 dst_y2); ++static void s3c_g2d_rotate_with_bitblt(s3c_g2d_params *params, ROT_DEG rot_degree); ++static void s3c_g2d_get_rotation_origin(u16 src_x1, u16 src_y1, ++ u16 src_x2, u16 src_y2, ++ u16 dst_x1, u16 dst_y1, ++ ROT_DEG rot_degree, ++ u16* org_x, u16* org_y); ++void s3c_g2d_set_xy_incr_format(u32 uDividend, u32 uDivisor, u32* uResult); ++static void s3c_g2d_rotator_start(s3c_g2d_params *params,ROT_DEG rot_degree); ++void s3c_g2d_check_fifo(int empty_fifo); ++int s3c_g2d_open(struct inode *inode, struct file *file); ++int s3c_g2d_release(struct inode *inode, struct file *file); ++int s3c_g2d_mmap(struct file* filp, struct vm_area_struct *vma) ; ++static int s3c_g2d_ioctl(struct inode *inode, struct file *file, ++ unsigned int cmd, unsigned long arg); ++static unsigned int s3c_g2d_poll(struct file *file, poll_table *wait); ++ ++#endif /*_S3C_G2D_DRIVER_H_*/ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/g3d/Kconfig linux-2.6.28.6/drivers/media/video/samsung/g3d/Kconfig +--- linux-2.6.28/drivers/media/video/samsung/g3d/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/g3d/Kconfig 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,11 @@ ++# ++# Configuration for FIMG-3D ++# ++ ++config VIDEO_G3D ++ bool "Samsung FIMG-3D Driver" ++ depends on VIDEO_SAMSUNG && (CPU_S3C6410 || CPU_S5PC100) ++ default n ++ ---help--- ++ This is a FIMG-3D(3D accelerator) driver for Samsung S3C6410 and S5PC100. ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/g3d/Makefile linux-2.6.28.6/drivers/media/video/samsung/g3d/Makefile +--- linux-2.6.28/drivers/media/video/samsung/g3d/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/g3d/Makefile 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,10 @@ ++################################################# ++# Makefile for FIMG-3D ++# 2009 (C) Samsung Electronics ++# Author : Jonghun Han ++################################################# ++ ++obj-$(CONFIG_VIDEO_G3D) += s3c_fimg3d.o ++ ++EXTRA_CFLAGS += -Idrivers/media/video ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/g3d/s3c_fimg3d.c linux-2.6.28.6/drivers/media/video/samsung/g3d/s3c_fimg3d.c +--- linux-2.6.28/drivers/media/video/samsung/g3d/s3c_fimg3d.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/g3d/s3c_fimg3d.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,787 @@ ++/* linux/drivers/video/samsung/g3d/s3c_fimg3d.c ++ * ++ * Driver file for Samsung 3D Accelerator(FIMG-3D) ++ * ++ * Jegeon Jung, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "s3c_fimg3d.h" ++ ++#define DEBUG_S3C_G3D ++#undef DEBUG_S3C_G3D ++ ++#ifdef DEBUG_S3C_G3D ++#define DEBUG(fmt,args...) printk(fmt, ##args) ++#else ++#define DEBUG(fmt,args...) do {} while(0) ++#endif ++ ++static DWORD BACKUP_FGHI_CONTROL; ++//static DWORD BACKUP_FGHI_IDXOFFSET; ++//static DWORD BACKUP_FGHI_VBADDR; ++static DWORD BACKUP_FGHI_ATTRIBS[10]; ++//static DWORD BACKUP_FGHI_ATTRIBS_VBCTRL[10]; ++//static DWORD BACKUP_FGHI_ATTRIBS_VBBASE[10]; ++ ++static DWORD BACKUP_FGVS_INSTMEM[2048]; ++static DWORD BACKUP_FGVS_CFLOAT[1024]; ++static DWORD BACKUP_FGVS_CINT[16]; ++static DWORD BACKUP_FGVS_CBOOL; ++static DWORD BACKUP_FGVS_CONFIG; ++static DWORD BACKUP_FGVS_PCRANGE_OUTATTR[8]; ++ ++static DWORD BACKUP_FGPE[7]; ++ ++static DWORD BACKUP_FGRA_PIXSAMP_YCLIP[7]; ++static DWORD BACKUP_FGRA_LODCTL; ++static DWORD BACKUP_FGRA_CLIPX; ++static DWORD BACKUP_FGRA_PWIDTH_LWIDTH[5]; ++ ++static DWORD BACKUP_FGPS_INSTMEM[2048]; ++static DWORD BACKUP_FGPS_CFLOAT[1024]; ++static DWORD BACKUP_FGPS_CINT[16]; ++static DWORD BACKUP_FGPS_CBOOL; ++static DWORD BACKUP_FGPS_EXEMODE_ATTRIBUTENUM[5]; ++ ++static DWORD BACKUP_FGTU_TEXTURE0[18]; ++static DWORD BACKUP_FGTU_TEXTURE1[18]; ++static DWORD BACKUP_FGTU_TEXTURE2[18]; ++static DWORD BACKUP_FGTU_TEXTURE3[18]; ++static DWORD BACKUP_FGTU_TEXTURE4[18]; ++static DWORD BACKUP_FGTU_TEXTURE5[18]; ++static DWORD BACKUP_FGTU_TEXTURE6[18]; ++static DWORD BACKUP_FGTU_TEXTURE7[18]; ++static DWORD BACKUP_FGTU_COLORKEYS[6]; ++static DWORD BACKUP_FGVTU_STATUSES_VTBADDRS[8]; ++ ++static DWORD BACKUP_FGPF[15]; ++ ++ ++#define G3D_IOCTL_MAGIC 'S' ++#define GET_CONFIG _IO(G3D_IOCTL_MAGIC, 101) ++#define WAIT_FOR_FLUSH _IO(G3D_IOCTL_MAGIC, 100) ++ ++#define S3C_3D_MEM_ALLOC _IOWR(G3D_IOCTL_MAGIC, 310, struct s3c_3d_mem_alloc) ++#define S3C_3D_MEM_FREE _IOWR(G3D_IOCTL_MAGIC, 311, struct s3c_3d_mem_alloc) ++#define S3C_3D_SFR_LOCK _IO(G3D_IOCTL_MAGIC, 312) ++#define S3C_3D_SFR_UNLOCK _IO(G3D_IOCTL_MAGIC, 313) ++#define S3C_3D_MEM_ALLOC_SHARE _IOWR(G3D_IOCTL_MAGIC, 314, struct s3c_3d_mem_alloc) ++#define S3C_3D_MEM_SHARE_FREE _IOWR(G3D_IOCTL_MAGIC, 315, struct s3c_3d_mem_alloc) ++ ++#define MEM_ALLOC 1 ++#define MEM_ALLOC_SHARE 2 ++ ++#define PFX "s3c_g3d" ++#define G3D_MINOR 249 ++ ++static wait_queue_head_t waitq; ++static struct resource *s3c_g3d_mem; ++static void __iomem *s3c_g3d_base; ++static int s3c_g3d_irq; ++static struct clk *g3d_clock; ++static struct clk *h_clk; ++ ++static DEFINE_MUTEX(mem_alloc_lock); ++static DEFINE_MUTEX(mem_free_lock); ++static DEFINE_MUTEX(mem_sfr_lock); ++ ++static DEFINE_MUTEX(mem_alloc_share_lock); ++static DEFINE_MUTEX(mem_share_free_lock); ++ ++void *dma_3d_done; ++ ++struct s3c_3d_mem_alloc { ++ int size; ++ unsigned int vir_addr; ++ unsigned int phy_addr; ++}; ++ ++static unsigned int mutex_lock_processID = 0; ++ ++static int flag = 0; ++ ++static unsigned int physical_address; ++ ++int interrupt_already_recevied; ++ ++unsigned int s3c_g3d_base_physical; ++ ++ ++///////////// for check memory leak ++//*-------------------------------------------------------------------------*/ ++typedef struct _memalloc_desc ++{ ++ int size; ++ unsigned int vir_addr; ++ unsigned int phy_addr; ++ struct _memalloc_desc* next; ++} Memalloc_desc; ++ ++typedef struct _openContext ++{ ++ Memalloc_desc* allocatedList; ++} OpenContext; ++ ++void grabageCollect(int *newid); ++///////////////////////////////////// ++ ++ ++irqreturn_t s3c_g3d_isr(int irq, void *dev_id) ++{ ++ __raw_writel(0, s3c_g3d_base + FGGB_INTPENDING); ++ ++ interrupt_already_recevied = 1; ++ wake_up_interruptible(&waitq); ++ ++ return IRQ_HANDLED; ++} ++ ++ ++int s3c_g3d_open(struct inode *inode, struct file *file) ++{ ++ int *newid; ++ newid = (int*)vmalloc(sizeof(OpenContext)); ++ memset(newid, 0x0, sizeof(OpenContext)); ++ ++ file->private_data = newid; ++ return 0; ++} ++ ++int s3c_g3d_release(struct inode *inode, struct file *file) ++{ ++ int *newid = file->private_data; ++ if(mutex_lock_processID != 0 && mutex_lock_processID == (unsigned int)file->private_data) ++ { ++ mutex_unlock(&mem_sfr_lock); ++ printk("Abnormal close of pid # %d\n", task_pid_nr(current)); ++ } ++ ++ grabageCollect(newid); ++ vfree((OpenContext*)newid); ++ ++ return 0; ++} ++ ++ ++static int s3c_g3d_ioctl(struct inode *inode, struct file *file, ++ unsigned int cmd, unsigned long arg) ++{ ++ u32 val; ++ DECLARE_COMPLETION_ONSTACK(complete); ++ ++ unsigned long *virt_addr; ++ struct mm_struct *mm = current->mm; ++ struct s3c_3d_mem_alloc param; ++ ++ Memalloc_desc *memdesc, *curDesc, *prevDesc; ++ OpenContext* pOpenCtx = (OpenContext*)file->private_data; ++ ++ switch (cmd) { ++ case WAIT_FOR_FLUSH: ++ ++ //if fifo has already been flushed, return; ++ val = __raw_readl(s3c_g3d_base+FGGB_PIPESTATE); ++ //printk("read pipestate = 0x%x\n",val); ++ if((val & arg) ==0) break; ++ ++ // enable interrupt ++ interrupt_already_recevied = 0; ++ __raw_writel(0x0001171f,s3c_g3d_base+FGGB_PIPEMASK); ++ __raw_writel(1,s3c_g3d_base+FGGB_INTMASK); ++ ++ //printk("wait for flush (arg=0x%lx)\n",arg); ++ ++ ++ while(1) { ++ wait_event_interruptible(waitq, (interrupt_already_recevied>0)); ++ __raw_writel(0,s3c_g3d_base+FGGB_INTMASK); ++ interrupt_already_recevied = 0; ++ //if(interrupt_already_recevied==0)interruptible_sleep_on(&waitq); ++ val = __raw_readl(s3c_g3d_base+FGGB_PIPESTATE); ++ //printk("in while read pipestate = 0x%x\n",val); ++ if(val & arg) { ++ } else { ++ break; ++ } ++ __raw_writel(1,s3c_g3d_base+FGGB_INTMASK); ++ } ++ break; ++ ++ case GET_CONFIG: ++// copy_to_user((void *)arg,&g3d_config,sizeof(G3D_CONFIG_STRUCT)); ++ break; ++ ++ case S3C_3D_MEM_ALLOC: ++ mutex_lock(&mem_alloc_lock); ++ if(copy_from_user(¶m, (struct s3c_3d_mem_alloc *)arg, sizeof(struct s3c_3d_mem_alloc))) { ++ mutex_unlock(&mem_alloc_lock); ++ return -EFAULT; ++ } ++ flag = MEM_ALLOC; ++ ++ param.vir_addr = do_mmap(file, 0, param.size, PROT_READ|PROT_WRITE, MAP_SHARED, 0); ++ DEBUG("param.vir_addr = %08x\n", param.vir_addr); ++ ++ if(param.vir_addr == -EINVAL) { ++ printk("S3C_3D_MEM_ALLOC FAILED\n"); ++ flag = 0; ++ mutex_unlock(&mem_alloc_lock); ++ return -EFAULT; ++ } ++ param.phy_addr = physical_address; ++ ++ // printk("alloc %d\n", param.size); ++ DEBUG("KERNEL MALLOC : param.phy_addr = 0x%X \t size = %d \t param.vir_addr = 0x%X\n", param.phy_addr, param.size, param.vir_addr); ++ ++ if(copy_to_user((struct s3c_3d_mem_alloc *)arg, ¶m, sizeof(struct s3c_3d_mem_alloc))) { ++ flag = 0; ++ mutex_unlock(&mem_alloc_lock); ++ return -EFAULT; ++ } ++ ++ flag = 0; ++ ++ ////////////////////////////////// ++ // for memory leak ++ memdesc = (Memalloc_desc*)vmalloc(sizeof(Memalloc_desc)); ++ memdesc->size = param.size; ++ memdesc->vir_addr = param.vir_addr; ++ memdesc->phy_addr = param.phy_addr; ++ memdesc->next = NULL; ++ prevDesc = NULL; ++ for(curDesc = pOpenCtx->allocatedList; curDesc != NULL; curDesc = curDesc->next) { ++ prevDesc = curDesc; ++ } ++ ++ if(prevDesc == NULL) pOpenCtx->allocatedList = memdesc; ++ else prevDesc->next = memdesc; ++ ////////////////////////////////// ++ ++ mutex_unlock(&mem_alloc_lock); ++ ++ break; ++ ++ case S3C_3D_MEM_FREE: ++ mutex_lock(&mem_free_lock); ++ if(copy_from_user(¶m, (struct s3c_3d_mem_alloc *)arg, sizeof(struct s3c_3d_mem_alloc))) { ++ mutex_unlock(&mem_free_lock); ++ return -EFAULT; ++ } ++ ++ DEBUG("KERNEL FREE : param.phy_addr = 0x%X \t size = %d \t param.vir_addr = 0x%X\n", param.phy_addr, param.size, param.vir_addr); ++ ++ if (do_munmap(mm, param.vir_addr, param.size) < 0) { ++ printk("do_munmap() failed !!\n"); ++ mutex_unlock(&mem_free_lock); ++ return -EINVAL; ++ } ++ virt_addr = (unsigned long *)phys_to_virt(param.phy_addr); ++ //printk("KERNEL : virt_addr = 0x%X\n", virt_addr); ++ //printk("free %d\n", param.size); ++ ++ kfree(virt_addr); ++ param.size = 0; ++ DEBUG("do_munmap() succeed !!\n"); ++ ++ if(copy_to_user((struct s3c_3d_mem_alloc *)arg, ¶m, sizeof(struct s3c_3d_mem_alloc))) { ++ mutex_unlock(&mem_free_lock); ++ return -EFAULT; ++ } ++ ++ ////////////////////////////////// ++ // for memory leak ++ prevDesc = NULL; ++ for(curDesc = pOpenCtx->allocatedList; curDesc != NULL; curDesc = curDesc->next) { ++ if(curDesc->vir_addr == param.vir_addr) break; ++ prevDesc = curDesc; ++ } ++ ++ if(prevDesc != NULL) ++ prevDesc->next = curDesc->next; ++ else ++ pOpenCtx->allocatedList = NULL; ++ ++ vfree(curDesc); ++ ////////////////////////////////// ++ ++ mutex_unlock(&mem_free_lock); ++ ++ break; ++ ++ case S3C_3D_SFR_LOCK: ++ mutex_lock(&mem_sfr_lock); ++ mutex_lock_processID = (unsigned int)file->private_data; ++ DEBUG("s3c_g3d_ioctl() : You got a muxtex lock !!\n"); ++ break; ++ ++ case S3C_3D_SFR_UNLOCK: ++ mutex_lock_processID = 0; ++ mutex_unlock(&mem_sfr_lock); ++ DEBUG("s3c_g3d_ioctl() : The muxtex unlock called !!\n"); ++ break; ++ ++ case S3C_3D_MEM_ALLOC_SHARE: ++ mutex_lock(&mem_alloc_share_lock); ++ if(copy_from_user(¶m, (struct s3c_3d_mem_alloc *)arg, sizeof(struct s3c_3d_mem_alloc))) { ++ mutex_unlock(&mem_alloc_share_lock); ++ return -EFAULT; ++ } ++ flag = MEM_ALLOC_SHARE; ++ ++ physical_address = param.phy_addr; ++ DEBUG("param.phy_addr = %08x\n", physical_address); ++ ++ param.vir_addr = do_mmap(file, 0, param.size, PROT_READ|PROT_WRITE, MAP_SHARED, 0); ++ DEBUG("param.vir_addr = %08x\n", param.vir_addr); ++ ++ if(param.vir_addr == -EINVAL) { ++ printk("S3C_3D_MEM_ALLOC_SHARE FAILED\n"); ++ flag = 0; ++ mutex_unlock(&mem_alloc_share_lock); ++ return -EFAULT; ++ } ++ ++ DEBUG("MALLOC_SHARE : param.phy_addr = 0x%X \t size = %d \t param.vir_addr = 0x%X\n", param.phy_addr, param.size, param.vir_addr); ++ ++ if(copy_to_user((struct s3c_3d_mem_alloc *)arg, ¶m, sizeof(struct s3c_3d_mem_alloc))) { ++ flag = 0; ++ mutex_unlock(&mem_alloc_share_lock); ++ return -EFAULT; ++ } ++ ++ flag = 0; ++ ++ mutex_unlock(&mem_alloc_share_lock); ++ ++ break; ++ ++ case S3C_3D_MEM_SHARE_FREE: ++ mutex_lock(&mem_share_free_lock); ++ if(copy_from_user(¶m, (struct s3c_3d_mem_alloc *)arg, sizeof(struct s3c_3d_mem_alloc))) { ++ mutex_unlock(&mem_share_free_lock); ++ return -EFAULT; ++ } ++ ++ DEBUG("MEM_SHARE_FREE : param.phy_addr = 0x%X \t size = %d \t param.vir_addr = 0x%X\n", param.phy_addr, param.size, param.vir_addr); ++ ++ if (do_munmap(mm, param.vir_addr, param.size) < 0) { ++ printk("do_munmap() failed - MEM_SHARE_FREE!!\n"); ++ mutex_unlock(&mem_share_free_lock); ++ return -EINVAL; ++ } ++ ++ param.vir_addr = 0; ++ DEBUG("do_munmap() succeed !! - MEM_SHARE_FREE\n"); ++ ++ if(copy_to_user((struct s3c_3d_mem_alloc *)arg, ¶m, sizeof(struct s3c_3d_mem_alloc))) { ++ mutex_unlock(&mem_share_free_lock); ++ return -EFAULT; ++ } ++ ++ mutex_unlock(&mem_share_free_lock); ++ ++ break; ++ ++ default: ++ DEBUG("s3c_g3d_ioctl() : default !!\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++ ++int s3c_g3d_mmap(struct file* filp, struct vm_area_struct *vma) ++{ ++ unsigned long pageFrameNo, size, phys_addr; ++ unsigned long *virt_addr; ++ ++ size = vma->vm_end - vma->vm_start; ++ ++ switch (flag) { ++ case MEM_ALLOC : ++ virt_addr = (unsigned long *)kmalloc(size, GFP_KERNEL); ++ ++ if (virt_addr == NULL) { ++ printk("kmalloc() failed !\n"); ++ return -EINVAL; ++ } ++ DEBUG("MMAP_KMALLOC : virt addr = 0x%p, size = %d\n", virt_addr, size); ++ phys_addr = virt_to_phys(virt_addr); ++ physical_address = (unsigned int)phys_addr; ++ ++ //DEBUG("MMAP_KMALLOC : phys addr = 0x%p\n", phys_addr); ++ pageFrameNo = __phys_to_pfn(phys_addr); ++ //DEBUG("MMAP_KMALLOC : PFN = 0x%x\n", pageFrameNo); ++ break; ++ ++ case MEM_ALLOC_SHARE : ++ DEBUG("MMAP_KMALLOC_SHARE : phys addr = 0x%p\n", physical_address); ++ ++ // page frame number of the address for the physical_address to be shared. ++ pageFrameNo = __phys_to_pfn(physical_address); ++ //DEBUG("MMAP_KMALLOC_SHARE: PFN = 0x%x\n", pageFrameNo); ++ DEBUG("MMAP_KMALLOC_SHARE : vma->end = 0x%p, vma->start = 0x%p, size = %d\n", vma->vm_end, vma->vm_start, size); ++ break; ++ ++ default : ++ // page frame number of the address for a source G2D_SFR_SIZE to be stored at. ++ pageFrameNo = __phys_to_pfn(s3c_g3d_base_physical); ++ DEBUG("MMAP : vma->end = 0x%p, vma->start = 0x%p, size = %d\n", vma->vm_end, vma->vm_start, size); ++ ++ if(size > (s3c_g3d_mem->end-s3c_g3d_mem->start+1)) { ++ printk("The size of G3D_SFR_SIZE mapping is too big!\n"); ++ return -EINVAL; ++ } ++ break; ++ } ++ ++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ ++ if ((vma->vm_flags & VM_WRITE) && !(vma->vm_flags & VM_SHARED)) { ++ printk("s3c_g3d_mmap() : Writable G3D_SFR_SIZE mapping must be shared !\n"); ++ return -EINVAL; ++ } ++ ++ if (remap_pfn_range(vma, vma->vm_start, pageFrameNo, size, vma->vm_page_prot)) { ++ printk("s3c_g3d_mmap() : remap_pfn_range() failed !\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++ ++void grabageCollect(int* newid) ++{ ++ unsigned long *virt_addr; ++ struct mm_struct *mm = current->mm; ++ OpenContext* pOpenCtx = (OpenContext*)newid; ++ Memalloc_desc *curDesc, *nextDesc; ++ ++ mutex_lock(&mem_free_lock); ++ for(curDesc = pOpenCtx->allocatedList;curDesc != NULL; ) { ++ nextDesc = curDesc->next; ++ printk("Deleting garbage address=0x%x size=%d\n", curDesc->vir_addr, curDesc->size); ++ if (do_munmap(mm, curDesc->vir_addr, curDesc->size) < 0) { ++ printk("do_munmap() failed !!\n"); ++ } ++ ++ virt_addr = (unsigned long *)phys_to_virt(curDesc->phy_addr); ++ kfree(virt_addr); ++ ++ vfree(curDesc); ++ curDesc = 0; ++ ++ curDesc = nextDesc; ++ } ++ ++ mutex_unlock(&mem_free_lock); ++} ++ ++ ++static struct file_operations s3c_g3d_fops = { ++ .owner = THIS_MODULE, ++ .ioctl = s3c_g3d_ioctl, ++ .open = s3c_g3d_open, ++ .release = s3c_g3d_release, ++ .mmap = s3c_g3d_mmap, ++}; ++ ++ ++static struct miscdevice s3c_g3d_dev = { ++ .minor = G3D_MINOR, ++ .name = "s3c-g3d", ++ .fops = &s3c_g3d_fops, ++}; ++ ++ ++static int s3c_g3d_remove(struct platform_device *dev) ++{ ++ //clk_disable(g3d_clock); ++ printk(KERN_INFO "s3c_g3d_remove called !\n"); ++ ++ free_irq(s3c_g3d_irq, NULL); ++ ++ if (s3c_g3d_mem != NULL) { ++ pr_debug("s3c_g3d: releasing s3c_post_mem\n"); ++ iounmap(s3c_g3d_base); ++ release_resource(s3c_g3d_mem); ++ kfree(s3c_g3d_mem); ++ } ++ ++ misc_deregister(&s3c_g3d_dev); ++ printk(KERN_INFO "s3c_g3d_remove Success !\n"); ++ return 0; ++} ++ ++int s3c_g3d_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ ++ int ret; ++ int i; ++ ++ DEBUG("s3c_g3d probe() called\n"); ++ ++ s3c_g3d_irq = platform_get_irq(pdev, 0); ++ if(s3c_g3d_irq <= 0) { ++ printk(KERN_ERR PFX "failed to get irq resouce\n"); ++ return -ENOENT; ++ } ++ ++ ret = request_irq(s3c_g3d_irq, s3c_g3d_isr, IRQF_DISABLED, pdev->name, NULL); ++ if (ret) { ++ printk("request_irq(S3D) failed.\n"); ++ return ret; ++ } ++ ++ /* get the memory region for the post processor driver */ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if(res == NULL) { ++ printk(KERN_ERR PFX "failed to get memory region resouce\n"); ++ return -ENOENT; ++ } ++ ++ s3c_g3d_base_physical = (unsigned int)res->start; ++ ++ s3c_g3d_mem = request_mem_region(res->start, res->end-res->start+1, pdev->name); ++ if(s3c_g3d_mem == NULL) { ++ printk(KERN_ERR PFX "failed to reserve memory region\n"); ++ return -ENOENT; ++ } ++ ++ ++ s3c_g3d_base = ioremap(s3c_g3d_mem->start, s3c_g3d_mem->end - res->start + 1); ++ if(s3c_g3d_base == NULL) { ++ printk(KERN_ERR PFX "failed ioremap\n"); ++ return -ENOENT; ++ } ++ ++ g3d_clock = clk_get(&pdev->dev, "post"); ++ if(g3d_clock == NULL) { ++ printk(KERN_ERR PFX "failed to find post clock source\n"); ++ return -ENOENT; ++ } ++ ++ clk_enable(g3d_clock); ++ ++ h_clk = clk_get(&pdev->dev, "hclk"); ++ if(h_clk == NULL) { ++ printk(KERN_ERR PFX "failed to find h_clk clock source\n"); ++ return -ENOENT; ++ } ++ ++ init_waitqueue_head(&waitq); ++ ++ ret = misc_register(&s3c_g3d_dev); ++ if (ret) { ++ printk (KERN_ERR "cannot register miscdev on minor=%d (%d)\n", ++ G3D_MINOR, ret); ++ return ret; ++ } ++ ++ // device reset ++ __raw_writel(1,s3c_g3d_base+FGGB_RST); ++ for(i=0;i<1000;i++); ++ __raw_writel(0,s3c_g3d_base+FGGB_RST); ++ for(i=0;i<1000;i++); ++ ++ printk("s3c_g3d version : 0x%x\n",__raw_readl(s3c_g3d_base + FGGB_VERSION)); ++ ++ /* check to see if everything is setup correctly */ ++ return 0; ++} ++ ++static int s3c_g3d_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ // backup Registers ++ // backup host interface registers. ++ ++ BACKUP_FGHI_CONTROL = __raw_readl(s3c_g3d_base + FGHI_HI_CTRL); ++// READREGP(FGHI_IDX_OFFSET, BACKUP_FGHI_IDXOFFSET); // currently not used ++// READREGP(FGHI_VTXBUF_ADDR, BACKUP_FGHI_VBADDR); // currently not used ++ memcpy(BACKUP_FGHI_ATTRIBS, (DWORD*)(s3c_g3d_base + FGHI_ATTR0), sizeof(DWORD)*10); ++// memcpy(BACKUP_FGHI_ATTRIBS_VBCTRL, (DWORD*)FGHI_VTXBUF_CTRL0, sizeof(DWORD)*10); // currently not used ++// memcpy(BACKUP_FGHI_ATTRIBS_VBBASE, (DWORD*)BACKUP_FGHI_ATTRIBS_VBBASE, sizeof(DWORD)*10); // currently not used ++ ++ ++ // backup vertex shader registers ++ memcpy(BACKUP_FGVS_INSTMEM, (DWORD*)(s3c_g3d_base + FGVS_INSTMEM_SADDR), sizeof(DWORD)*2048); ++ memcpy(BACKUP_FGVS_CFLOAT, (DWORD*)(s3c_g3d_base + FGVS_CFLOAT_SADDR), sizeof(DWORD)*1024); ++ memcpy(BACKUP_FGVS_CINT, (DWORD*)(s3c_g3d_base + FGVS_CINT_SADDR), sizeof(DWORD)*16); ++ BACKUP_FGVS_CBOOL = __raw_readl(s3c_g3d_base + FGVS_CBOOL_SADDR); ++ BACKUP_FGVS_CONFIG = __raw_readl(s3c_g3d_base + FGVS_CONFIG); ++ memcpy(BACKUP_FGVS_PCRANGE_OUTATTR, (DWORD*)(s3c_g3d_base + FGVS_PC_RANGE), sizeof(DWORD)*8); ++ ++ ++ // backup primitive engine registers ++ memcpy(BACKUP_FGPE, (DWORD*)(s3c_g3d_base + FGPE_VTX_CONTEXT), sizeof(DWORD)*7); ++ ++ ++ // backup raster engine registers ++ memcpy(BACKUP_FGRA_PIXSAMP_YCLIP, (DWORD*)(s3c_g3d_base + FGRA_PIXEL_SAMPOS), sizeof(DWORD)*7); ++ BACKUP_FGRA_LODCTL = __raw_readl(s3c_g3d_base + FGRA_LOD_CTRL); ++ BACKUP_FGRA_CLIPX = __raw_readl(s3c_g3d_base + FGRA_CLIP_XCORD); ++ memcpy(BACKUP_FGRA_PWIDTH_LWIDTH, (DWORD*)(s3c_g3d_base + FGRA_POINT_WIDTH), sizeof(DWORD)*5); ++ ++ // backup pixel shader registers ++ memcpy(BACKUP_FGPS_INSTMEM, (DWORD*)(s3c_g3d_base + FGPS_INSTMEM_SADDR), sizeof(DWORD)*2048); ++ memcpy(BACKUP_FGPS_CFLOAT, (DWORD*)(s3c_g3d_base + FGPS_CFLOAT_SADDR), sizeof(DWORD)*1024); ++ memcpy(BACKUP_FGPS_CINT, (DWORD*)(s3c_g3d_base + FGPS_CINT_SADDR), sizeof(DWORD)*16); ++ BACKUP_FGPS_CBOOL = __raw_readl((s3c_g3d_base + FGPS_CBOOL_SADDR)); ++ memcpy(BACKUP_FGPS_EXEMODE_ATTRIBUTENUM, (DWORD*)(s3c_g3d_base + FGPS_EXE_MODE), sizeof(DWORD)*5); ++ ++ // backup texture unit registers ++ memcpy(BACKUP_FGTU_TEXTURE0, (DWORD*)(s3c_g3d_base + FGTU_TEX0_CTRL), sizeof(DWORD)*18); ++ memcpy(BACKUP_FGTU_TEXTURE1, (DWORD*)(s3c_g3d_base + FGTU_TEX1_CTRL), sizeof(DWORD)*18); ++ memcpy(BACKUP_FGTU_TEXTURE2, (DWORD*)(s3c_g3d_base + FGTU_TEX2_CTRL), sizeof(DWORD)*18); ++ memcpy(BACKUP_FGTU_TEXTURE3, (DWORD*)(s3c_g3d_base + FGTU_TEX3_CTRL), sizeof(DWORD)*18); ++ memcpy(BACKUP_FGTU_TEXTURE4, (DWORD*)(s3c_g3d_base + FGTU_TEX4_CTRL), sizeof(DWORD)*18); ++ memcpy(BACKUP_FGTU_TEXTURE5, (DWORD*)(s3c_g3d_base + FGTU_TEX5_CTRL), sizeof(DWORD)*18); ++ memcpy(BACKUP_FGTU_TEXTURE6, (DWORD*)(s3c_g3d_base + FGTU_TEX6_CTRL), sizeof(DWORD)*18); ++ memcpy(BACKUP_FGTU_TEXTURE7, (DWORD*)(s3c_g3d_base + FGTU_TEX7_CTRL), sizeof(DWORD)*18); ++ ++ memcpy(BACKUP_FGTU_COLORKEYS, (DWORD*)(s3c_g3d_base + FGTU_COLOR_KEY1), sizeof(DWORD)*6); ++ memcpy(BACKUP_FGVTU_STATUSES_VTBADDRS, (DWORD*)(s3c_g3d_base + FGTU_VTXTEX0_CTRL), sizeof(DWORD)*8); ++ ++ ++ // backup per-fragment unit registers ++ memcpy(BACKUP_FGPF, (DWORD*)(s3c_g3d_base + FGPF_SCISSOR_XCORD), sizeof(DWORD)*15); ++ ++ return 0; ++} ++static int s3c_g3d_resume(struct platform_device *pdev) ++{ ++ //clk_enable(g3d_clock); ++ int i; ++ ++ // restore host interface registers. ++ ++ __raw_writel(0, s3c_g3d_base+FGHI_HI_CTRL); ++ ++// WRITEREG(FGHI_IDX_OFFSET, BACKUP_FGHI_IDXOFFSET); // currently not used ++// WRITEREG(FGHI_VTXBUF_ADDR, BACKUP_FGHI_VBADDR); // currently not used ++ memcpy((DWORD*)(s3c_g3d_base+FGHI_ATTR0), BACKUP_FGHI_ATTRIBS, sizeof(DWORD)*10); ++// memcpy((DWORD*)FGHI_VTXBUF_CTRL0, BACKUP_FGHI_ATTRIBS_VBCTRL, sizeof(DWORD)*10); // currently not used ++// memcpy((DWORD*)BACKUP_FGHI_ATTRIBS_VBBASE, BACKUP_FGHI_ATTRIBS_VBBASE, sizeof(DWORD)*10); // currently not used ++ ++ ++ // restore vertex shader registers ++ memcpy((DWORD*)(s3c_g3d_base+FGVS_INSTMEM_SADDR), BACKUP_FGVS_INSTMEM, sizeof(DWORD)*2048); ++ memcpy((DWORD*)(s3c_g3d_base+FGVS_CFLOAT_SADDR), BACKUP_FGVS_CFLOAT, sizeof(DWORD)*1024); ++ memcpy((DWORD*)(s3c_g3d_base+FGVS_CINT_SADDR), BACKUP_FGVS_CINT, sizeof(DWORD)*16); ++ __raw_writel(BACKUP_FGVS_CBOOL, s3c_g3d_base+FGVS_CBOOL_SADDR); ++ __raw_writel(BACKUP_FGVS_CONFIG, s3c_g3d_base+FGVS_CONFIG); ++ memcpy((DWORD*)(s3c_g3d_base+FGVS_PC_RANGE), BACKUP_FGVS_PCRANGE_OUTATTR, sizeof(DWORD)*8); ++ ++ ++ // restore primitive engine registers ++ memcpy((DWORD*)(s3c_g3d_base+FGPE_VTX_CONTEXT), BACKUP_FGPE, sizeof(DWORD)*7); ++ ++ ++ // restore raster engine registers ++ memcpy((DWORD*)(s3c_g3d_base+FGRA_PIXEL_SAMPOS), BACKUP_FGRA_PIXSAMP_YCLIP, sizeof(DWORD)*7); ++ __raw_writel(BACKUP_FGRA_LODCTL, s3c_g3d_base+FGRA_LOD_CTRL); ++ __raw_writel(BACKUP_FGRA_CLIPX, s3c_g3d_base+FGRA_CLIP_XCORD); ++ memcpy((DWORD*)(s3c_g3d_base+FGRA_POINT_WIDTH), BACKUP_FGRA_PWIDTH_LWIDTH, sizeof(DWORD)*5); ++ ++ // restore pixel shader registers ++ memcpy((DWORD*)(s3c_g3d_base+FGPS_INSTMEM_SADDR), BACKUP_FGPS_INSTMEM, sizeof(DWORD)*2048); ++ memcpy((DWORD*)(s3c_g3d_base+FGPS_CFLOAT_SADDR), BACKUP_FGPS_CFLOAT, sizeof(DWORD)*1024); ++ memcpy((DWORD*)(s3c_g3d_base+FGPS_CINT_SADDR), BACKUP_FGPS_CINT, sizeof(DWORD)*16); ++ __raw_writel(BACKUP_FGPS_CBOOL, s3c_g3d_base+FGPS_CBOOL_SADDR); ++ memcpy((DWORD*)(s3c_g3d_base+FGPS_EXE_MODE), BACKUP_FGPS_EXEMODE_ATTRIBUTENUM, sizeof(DWORD)*5); ++ ++ ++ // backup texture unit registers ++ memcpy((DWORD*)(s3c_g3d_base+FGTU_TEX0_CTRL), BACKUP_FGTU_TEXTURE0, sizeof(DWORD)*18); ++ memcpy((DWORD*)(s3c_g3d_base+FGTU_TEX1_CTRL), BACKUP_FGTU_TEXTURE1, sizeof(DWORD)*18); ++ memcpy((DWORD*)(s3c_g3d_base+FGTU_TEX2_CTRL), BACKUP_FGTU_TEXTURE2, sizeof(DWORD)*18); ++ memcpy((DWORD*)(s3c_g3d_base+FGTU_TEX3_CTRL), BACKUP_FGTU_TEXTURE3, sizeof(DWORD)*18); ++ memcpy((DWORD*)(s3c_g3d_base+FGTU_TEX4_CTRL), BACKUP_FGTU_TEXTURE4, sizeof(DWORD)*18); ++ memcpy((DWORD*)(s3c_g3d_base+FGTU_TEX5_CTRL), BACKUP_FGTU_TEXTURE5, sizeof(DWORD)*18); ++ memcpy((DWORD*)(s3c_g3d_base+FGTU_TEX6_CTRL), BACKUP_FGTU_TEXTURE6, sizeof(DWORD)*18); ++ memcpy((DWORD*)(s3c_g3d_base+FGTU_TEX7_CTRL), BACKUP_FGTU_TEXTURE7, sizeof(DWORD)*18); ++ ++ memcpy((DWORD*)(s3c_g3d_base+FGTU_COLOR_KEY1), BACKUP_FGTU_COLORKEYS, sizeof(DWORD)*6); ++ memcpy((DWORD*)(s3c_g3d_base+FGTU_VTXTEX0_CTRL), BACKUP_FGVTU_STATUSES_VTBADDRS, sizeof(DWORD)*8); ++ ++ ++ ++ // backup per-fragment unit registers ++ memcpy((DWORD*)(s3c_g3d_base+FGPF_SCISSOR_XCORD), BACKUP_FGPF, sizeof(DWORD)*15); ++ ++ ++ __raw_writel(1,s3c_g3d_base+FGGB_RST); ++ for(i=0;i<1000;i++); ++ __raw_writel(0,s3c_g3d_base+FGGB_RST); ++ for(i=0;i<1000;i++); ++ ++ ++ return 0; ++} ++ ++static struct platform_driver s3c_g3d_driver = { ++ .probe = s3c_g3d_probe, ++ .remove = s3c_g3d_remove, ++ .suspend = s3c_g3d_suspend, ++ .resume = s3c_g3d_resume, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "s3c-g3d", ++ }, ++}; ++ ++static char banner[] __initdata = KERN_INFO "S3C G3D Driver, (c) 2007-2009 Samsung Electronics\n"; ++ ++static char init_error[] __initdata = KERN_ERR "Intialization of S3C G3D driver is failed\n"; ++ ++int __init s3c_g3d_init(void) ++{ ++ printk(banner); ++ ++ if(platform_driver_register(&s3c_g3d_driver)!=0) { ++ printk(init_error); ++ return -1; ++ } ++ ++ printk(" S3C G3D Init : Done\n"); ++ return 0; ++} ++ ++void s3c_g3d_exit(void) ++{ ++ platform_driver_unregister(&s3c_g3d_driver); ++ ++ printk("S3C G3D module exit\n"); ++} ++ ++module_init(s3c_g3d_init); ++module_exit(s3c_g3d_exit); ++ ++MODULE_AUTHOR("jegeon.jung@samsung.com"); ++MODULE_DESCRIPTION("S3C G3D Device Driver"); ++MODULE_LICENSE("GPL"); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/g3d/s3c_fimg3d.h linux-2.6.28.6/drivers/media/video/samsung/g3d/s3c_fimg3d.h +--- linux-2.6.28/drivers/media/video/samsung/g3d/s3c_fimg3d.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/g3d/s3c_fimg3d.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,60 @@ ++/* linux/drivers/video/samsung/g3d/s3c_fimg3d.h ++ * ++ * Driver header file for Samsung 3D Accelerator(FIMG-3D) ++ * ++ * Jegeon Jung, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_G3D_DRIVER_H_ ++#define _S3C_G3D_DRIVER_H_ ++ ++#define FIMG_PHY_SIZE 0x90000 ++ ++#define DWORD unsigned int ++ ++#define FGGB_CACHECTL (0x04) ++#define FGGB_HOSTINTERFACE (0xc000) ++#define FGGB_PIPESTATE (0x00) ++#define FGHI_HI_CTRL (0x8008) ++#define FGHI_ATTR0 (0x8040) ++#define FGVS_INSTMEM_SADDR (0x10000) ++#define FGVS_CFLOAT_SADDR (0x14000) ++#define FGVS_CINT_SADDR (0x18000) ++#define FGVS_CBOOL_SADDR (0x18400) ++#define FGVS_CONFIG (0x1C800) ++#define FGVS_PC_RANGE (0x20000) ++#define FGPE_VTX_CONTEXT (0x30000) ++#define FGRA_PIXEL_SAMPOS (0x38000) ++#define FGRA_LOD_CTRL (0x3C000) ++#define FGRA_POINT_WIDTH (0x3801C) ++#define FGPS_INSTMEM_SADDR (0x40000) ++#define FGPS_CFLOAT_SADDR (0x44000) ++#define FGPS_CINT_SADDR (0x48000) ++#define FGPS_CBOOL_SADDR (0x48400) ++#define FGPS_EXE_MODE (0x4C800) ++#define FGTU_TEX0_CTRL (0x60000) /* R/W */ ++#define FGTU_TEX1_CTRL (0x60050) ++#define FGTU_TEX2_CTRL (0x600A0) ++#define FGTU_TEX3_CTRL (0x600F0) ++#define FGTU_TEX4_CTRL (0x60140) ++#define FGTU_TEX5_CTRL (0x60190) ++#define FGTU_TEX6_CTRL (0x601E0) ++#define FGTU_TEX7_CTRL (0x60230) ++#define FGRA_CLIP_XCORD (0x3C004) ++#define FGTU_COLOR_KEY1 (0x60280) /* R/W Color Key1 */ ++#define FGTU_VTXTEX0_CTRL (0x602C0) ++#define FGPF_SCISSOR_XCORD (0x70000) ++#define FGPF_STENCIL_DEPTH_MASK (0x70028) ++#define FGGB_PIPEMASK (0x48) ++#define FGGB_INTMASK (0x44) ++#define FGGB_INTPENDING (0x40) ++#define FGGB_RST (0x8) ++#define FGGB_VERSION (0x10) ++#define FGGB_PIPEINTSTATE (0x50) ++ ++#endif /*_S3C_G2D_DRIVER_H_*/ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg/Kconfig linux-2.6.28.6/drivers/media/video/samsung/jpeg/Kconfig +--- linux-2.6.28/drivers/media/video/samsung/jpeg/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg/Kconfig 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,10 @@ ++# ++# Configuration for JPEG ++# ++ ++config VIDEO_JPEG ++ bool "Samsung JPEG driver" ++ depends on VIDEO_SAMSUNG && CPU_S3C6410 ++ default n ++ ---help--- ++ This is a JPEG for Samsung S3C6410. +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg/Makefile linux-2.6.28.6/drivers/media/video/samsung/jpeg/Makefile +--- linux-2.6.28/drivers/media/video/samsung/jpeg/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg/Makefile 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,10 @@ ++################################################# ++# Makefile for JPEG ++# 2009 (C) Samsung Electronics ++# Author : Jaeryul peter Oh ++################################################# ++ ++obj-$(CONFIG_VIDEO_JPEG) += jpg_mem.o jpg_misc.o jpg_opr.o log_msg.o s3c-jpeg.o ++ ++EXTRA_CFLAGS += -Idrivers/media/video ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg/jpg_conf.h linux-2.6.28.6/drivers/media/video/samsung/jpeg/jpg_conf.h +--- linux-2.6.28/drivers/media/video/samsung/jpeg/jpg_conf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg/jpg_conf.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,281 @@ ++/* linux/drivers/media/video/samsung/jpeg/jpg-conf.h ++ * ++ * Configuration file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __JPG_CONF_H__ ++#define __JPG_CONF_H__ ++ ++ ++const unsigned char QTBL_Luminance[4][64]= ++{ ++ // level 1 - high quality ++ { ++ 8, 6, 6, 8, 12, 14, 16, 17, ++ 6, 6, 6, 8, 10, 13, 12, 15, ++ 6, 6, 7, 8, 13, 14, 18, 24, ++ 8, 8, 8, 14, 13, 19, 24, 35, ++ 12, 10, 13, 13, 20, 26, 34, 39, ++ 14, 13, 14, 19, 26, 34, 39, 39, ++ 16, 12, 18, 24, 34, 39, 39, 39, ++ 17, 15, 24, 35, 39, 39, 39, 39 ++ }, ++ ++ // level 2 ++ { ++ 12, 8, 8, 12, 17, 21, 24, 23, ++ 8, 9, 9, 11, 15, 19, 18, 23, ++ 8, 9, 10, 12, 19, 20, 27, 36, ++ 12, 11, 12, 21, 20, 28, 36, 53, ++ 17, 15, 19, 20, 30, 39, 51, 59, ++ 21, 19, 20, 28, 39, 51, 59, 59, ++ 24, 18, 27, 36, 51, 59, 59, 59, ++ 23, 23, 36, 53, 59, 59, 59, 59 ++ }, ++ ++ // level 3 ++ { ++ 16, 11, 11, 16, 23, 27, 31, 30, ++ 11, 12, 12, 15, 20, 23, 23, 30, ++ 11, 12, 13, 16, 23, 26, 35, 47, ++ 16, 15, 16, 23, 26, 37, 47, 64, ++ 23, 20, 23, 26, 39, 51, 64, 64, ++ 27, 23, 26, 37, 51, 64, 64, 64, ++ 31, 23, 35, 47, 64, 64, 64, 64, ++ 30, 30, 47, 64, 64, 64, 64, 64 ++ ++ }, ++ ++ // level 4 - low quality ++ { ++ 20, 16, 25, 39, 50, 46, 62, 68, ++ 16, 18, 23, 38, 38, 53, 65, 68, ++ 25, 23, 31, 38, 53, 65, 68, 68, ++ 39, 38, 38, 53, 65, 68, 68, 68, ++ 50, 38, 53, 65, 68, 68, 68, 68, ++ 46, 53, 65, 68, 68, 68, 68, 68, ++ 62, 65, 68, 68, 68, 68, 68, 68, ++ 68, 68, 68, 68, 68, 68, 68, 68 ++ } ++ ++ ++}; ++ ++const unsigned char QTBL_Chrominance[4][64]= ++{ ++ // level 1 - high quality ++ { ++ 9, 8, 9, 11, 14, 17, 19, 24, ++ 8, 10, 9, 11, 14, 13, 17, 22, ++ 9, 9, 13, 14, 13, 15, 23, 26, ++ 11, 11, 14, 14, 15, 20, 26, 33, ++ 14, 14, 13, 15, 20, 24, 33, 39, ++ 17, 13, 15, 20, 24, 32, 39, 39, ++ 19, 17, 23, 26, 33, 39, 39, 39, ++ 24, 22, 26, 33, 39, 39, 39, 39 ++ }, ++ ++ // level 2 ++ { ++ 13, 11, 13, 16, 20, 20, 29, 37, ++ 11, 14, 14, 14, 16, 20, 26, 32, ++ 13, 14, 15, 17, 20, 23, 35, 40, ++ 16, 14, 17, 21, 23, 30, 40, 50, ++ 20, 16, 20, 23, 30, 37, 50, 59, ++ 20, 20, 23, 30, 37, 48, 59, 59, ++ 29, 26, 35, 40, 50, 59, 59, 59, ++ 37, 32, 40, 50, 59, 59, 59, 59 ++ }, ++ ++ ++ // level 3 ++ { ++ 17, 15, 17, 21, 20, 26, 38, 48, ++ 15, 19, 18, 17, 20, 26, 35, 43, ++ 17, 18, 20, 22, 26, 30, 46, 53, ++ 21, 17, 22, 28, 30, 39, 53, 64, ++ 20, 20, 26, 30, 39, 48, 64, 64, ++ 26, 26, 30, 39, 48, 63, 64, 64, ++ 38, 35, 46, 53, 64, 64, 64, 64, ++ 48, 43, 53, 64, 64, 64, 64, 64 ++ ++ ++ }, ++ ++ // level 4 - low quality ++ { ++ 21, 25, 32, 38, 54, 68, 68, 68, ++ 25, 28, 24, 38, 54, 68, 68, 68, ++ 32, 24, 32, 43, 66, 68, 68, 68, ++ 38, 38, 43, 53, 68, 68, 68, 68, ++ 54, 54, 66, 68, 68, 68, 68, 68, ++ 68, 68, 68, 68, 68, 68, 68, 68, ++ 68, 68, 68, 68, 68, 68, 68, 68, ++ 68, 68, 68, 68, 68, 68, 68, 68 ++ ++ } ++ ++}; ++ ++ ++ ++const unsigned char QTBL0[64]= ++{ ++#if 1 ++ 0x10, 0x0B, 0x0A, 0x10, 0x18, 0x28, 0x33, 0x3D, ++ 0x0C, 0x0C, 0x0E, 0x13, 0x1A, 0x3A, 0x3C, 0x37, ++ 0x0E, 0x0D, 0x10, 0x18, 0x28, 0x39, 0x45, 0x38, ++ 0x0E, 0x11, 0x16, 0x1D, 0x33, 0x57, 0x50, 0x3E, ++ 0x12, 0x16, 0x25, 0x38, 0x44, 0x6D, 0x67, 0x4D, ++ 0x18, 0x23, 0x37, 0x40, 0x51, 0x68, 0x71, 0x5C, ++ 0x31, 0x40, 0x4E, 0x57, 0x67, 0x79, 0x78, 0x65, ++ 0x48, 0x5C, 0x5F, 0x62, 0x70, 0x64, 0x67, 0x63 ++#else ++ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, ++ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, ++ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, ++ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, ++ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, ++ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, ++ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, ++ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 ++#endif ++}; ++ ++//Added Quantization Table ++const unsigned char std_chrominance_quant_tbl_plus[64]= ++{ ++ 0x11, 0x12, 0x18, 0x2F, 0x63, 0x63, 0x63, 0x63, ++ 0x12, 0x15, 0x1A, 0x42, 0x63, 0x63, 0x63, 0x63, ++ 0x18, 0x1A, 0x38, 0x63, 0x63, 0x63, 0x63, 0x63, ++ 0x2F, 0x42, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, ++ 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, ++ 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, ++ 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, ++ 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63 ++}; ++ ++//Quantization Table0 ++unsigned char std_luminance_quant_tbl[64] = ++{ ++ 1, 1, 2, 1, 1, 2, 2, 2, ++ 2, 3, 2, 2, 3, 3, 6, 4, ++ 3, 3, 3, 3, 7, 5, 8, 4, ++ 6, 8, 8, 10, 9, 8, 7, 11, ++ 8, 10, 14, 13, 11, 10, 10, 12, ++ 10, 8, 8, 11, 16, 12, 12, 13, ++ 15, 15, 15, 15, 9, 11, 16, 17, ++ 15, 14, 17, 13, 14, 14, 14, 1 ++ }; ++ ++//Quantization Table1 ++unsigned char std_chrominance_quant_tbl[64] = ++{ ++ 4, 4, 4, 5, 4, 5, 9, 5, ++ 5, 9, 15, 10, 8, 10, 15, 26, ++ 19, 9, 9, 19, 26, 26, 26, 26, ++ 13, 26, 26, 26, 26, 26, 26, 26, ++ 26, 26, 26, 26, 26, 26, 26, 26, ++ 26, 26, 26, 26, 26, 26, 26, 26, ++ 26, 26, 26, 26, 26, 26, 26, 26, ++ 26, 26, 26, 26, 26, 26, 26, 26 ++}; ++ ++//Huffman Table ++unsigned char HDCTBL0[16] = {0, 1, 5, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0}; ++unsigned char HDCTBLG0[12] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb}; ++ ++unsigned char HACTBL0[16]= {0, 2, 1, 3, 3, 2, 4, 3, 5, 5, 4, 4, 0, 0, 1, 0x7d}; ++const unsigned char HACTBLG0[162]= ++{ ++ 0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, ++ 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, ++ 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08, ++ 0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0, ++ 0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16, ++ 0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28, ++ 0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++ 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, ++ 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, ++ 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, ++ 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, ++ 0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, ++ 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, ++ 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, ++ 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, ++ 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5, ++ 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4, ++ 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2, ++ 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, ++ 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, ++ 0xf9, 0xfa ++}; ++ ++//Huffman Table0 ++unsigned char len_dc_luminance[16] ={ 0, 1, 5, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 }; ++unsigned char val_dc_luminance[12] ={ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 }; ++ ++unsigned char len_ac_luminance[16] ={ 0, 2, 1, 3, 3, 2, 4, 3, 5, 5, 4, 4, 0, 0, 1, 0x7d }; ++unsigned char val_ac_luminance[162] = ++{ ++ 0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, ++ 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, ++ 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08, ++ 0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0, ++ 0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16, ++ 0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28, ++ 0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++ 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, ++ 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, ++ 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, ++ 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, ++ 0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, ++ 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, ++ 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, ++ 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, ++ 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5, ++ 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4, ++ 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2, ++ 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, ++ 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, ++ 0xf9, 0xfa ++}; ++ ++//Huffman Table1 ++unsigned char len_dc_chrominance[16] ={ 0, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 }; ++unsigned char val_dc_chrominance[12] ={ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 }; ++ ++unsigned char len_ac_chrominance[16] ={ 0, 2, 1, 2, 4, 4, 3, 4, 7, 5, 4, 4, 0, 1, 2, 0x77 }; ++unsigned char val_ac_chrominance[162] = ++{ ++ 0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, ++ 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71, ++ 0x13, 0x22, 0x32, 0x81, 0x81, 0x08, 0x14, 0x42, ++ 0x91, 0xa1, 0xb1, 0xc1, 0x09, 0x23, 0x33, 0x52, ++ 0xf0, 0x15, 0x62, 0x72, 0xd1, 0x0a, 0x16, 0x24, ++ 0x34, 0xe1, 0x25, 0xf1, 0x17, 0x18, 0x19, 0x1a, ++ 0x26, 0x27, 0x28, 0x29, 0x2a, 0x35, 0x36, 0x37, ++ 0x38, 0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, ++ 0x48, 0x49, 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, ++ 0x58, 0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, ++ 0x68, 0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, ++ 0x78, 0x79, 0x7a, 0x82, 0x83, 0x84, 0x85, 0x86, ++ 0x87, 0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, ++ 0x96, 0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, ++ 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, ++ 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xc2, ++ 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, ++ 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, ++ 0xda, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, ++ 0xe9, 0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, ++ 0xf8, 0xf9 ++}; ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg/jpg_mem.c linux-2.6.28.6/drivers/media/video/samsung/jpeg/jpg_mem.c +--- linux-2.6.28/drivers/media/video/samsung/jpeg/jpg_mem.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg/jpg_mem.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,116 @@ ++/* linux/drivers/media/video/samsung/jpeg/jpg_mem.c ++ * ++ * Driver file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "jpg_mem.h" ++#include "jpg_misc.h" ++#include "log_msg.h" ++ ++ ++/*---------------------------------------------------------------------------- ++*Function: phy_to_vir_addr ++ ++*Parameters: dwContext : ++*Return Value: True/False ++*Implementation Notes: memory mapping from physical addr to virtual addr ++-----------------------------------------------------------------------------*/ ++void *phy_to_vir_addr(UINT32 phy_addr, int mem_size) ++{ ++ void *reserved_mem; ++ ++ reserved_mem = (void *)ioremap( (unsigned long)phy_addr, (int)mem_size ); ++ ++ if (reserved_mem == NULL) { ++ log_msg(LOG_ERROR, "phy_to_vir_addr", "DD::Phyical to virtual memory mapping was failed!\r\n"); ++ return NULL; ++ } ++ ++ return reserved_mem; ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: jpeg_mem_mapping ++ ++*Parameters: dwContext : ++*Return Value: True/False ++*Implementation Notes: JPG register mapping from physical addr to virtual addr ++-----------------------------------------------------------------------------*/ ++BOOL jpeg_mem_mapping(s3c6400_jpg_ctx *base) ++{ ++ // JPG HOST Register ++ base->v_pJPG_REG = (volatile S3C6400_JPG_HOSTIF_REG *)phy_to_vir_addr(JPG_REG_BASE_ADDR, sizeof(S3C6400_JPG_HOSTIF_REG)); ++ if (base->v_pJPG_REG == NULL) ++ { ++ log_msg(LOG_ERROR, "jpeg_mem_mapping", "DD::v_pJPG_REG: VirtualAlloc failed!\r\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++ ++void jpg_mem_free(s3c6400_jpg_ctx *base) ++{ ++ iounmap((void *)base->v_pJPG_REG); ++ base->v_pJPG_REG = NULL; ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: jpg_buff_mapping ++ ++*Parameters: dwContext : ++*Return Value: True/False ++*Implementation Notes: JPG Buffer mapping from physical addr to virtual addr ++-----------------------------------------------------------------------------*/ ++BOOL jpg_buff_mapping(s3c6400_jpg_ctx *base) ++{ ++ // JPG Data Buffer ++ base->v_pJPGData_Buff = (UINT8 *)phy_to_vir_addr(jpg_data_base_addr, JPG_TOTAL_BUF_SIZE); ++ ++ if (base->v_pJPGData_Buff == NULL) ++ { ++ log_msg(LOG_ERROR, "jpg_buff_mapping", "DD::v_pJPGData_Buff: VirtualAlloc failed!\r\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++void jpg_buff_free(s3c6400_jpg_ctx *base) ++{ ++ iounmap( (void *)base->v_pJPGData_Buff ); ++ base->v_pJPGData_Buff = NULL; ++} ++ ++void *mem_move(void *dst, const void *src, unsigned int size) ++{ ++ return memmove(dst, src, size); ++} ++ ++void *mem_alloc(unsigned int size) ++{ ++ void *alloc_mem; ++ ++ alloc_mem = (void *)kmalloc((int)size, GFP_KERNEL); ++ if (alloc_mem == NULL) { ++ log_msg(LOG_ERROR, "Mem_Alloc", "memory allocation failed!\r\n"); ++ return NULL; ++ } ++ ++ return alloc_mem; ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg/jpg_mem.h linux-2.6.28.6/drivers/media/video/samsung/jpeg/jpg_mem.h +--- linux-2.6.28/drivers/media/video/samsung/jpeg/jpg_mem.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg/jpg_mem.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,125 @@ ++/* linux/drivers/media/video/samsung/jpeg/jpg_mem.h ++ * ++ * Driver header file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __JPG_MEM_H__ ++#define __JPG_MEM_H__ ++ ++#include "jpg_misc.h" ++ ++#include ++#include ++ ++#define JPG_REG_BASE_ADDR (0x78800000) ++#define jpg_data_base_addr (UINT32)s3c_get_media_memory(S3C_MDEV_JPEG) ++ ++#define MAX_JPG_WIDTH 1600 ++#define MAX_JPG_HEIGHT 1200 ++ ++#define MAX_JPG_THUMBNAIL_WIDTH 320 ++#define MAX_JPG_THUMBNAIL_HEIGHT 240 ++ ++#define JPG_STREAM_BUF_SIZE (MAX_JPG_WIDTH * MAX_JPG_HEIGHT) ++#define JPG_STREAM_THUMB_BUF_SIZE (MAX_JPG_THUMBNAIL_WIDTH * MAX_JPG_THUMBNAIL_HEIGHT) ++#define JPG_FRAME_BUF_SIZE (MAX_JPG_WIDTH * MAX_JPG_HEIGHT * 3) ++#define JPG_FRAME_THUMB_BUF_SIZE (MAX_JPG_THUMBNAIL_WIDTH * MAX_JPG_THUMBNAIL_HEIGHT * 3) ++ ++#define JPG_TOTAL_BUF_SIZE (JPG_STREAM_BUF_SIZE + JPG_STREAM_THUMB_BUF_SIZE \ ++ + JPG_FRAME_BUF_SIZE + JPG_FRAME_THUMB_BUF_SIZE) ++ ++#define COEF1_RGB_2_YUV 0x4d971e ++#define COEF2_RGB_2_YUV 0x2c5783 ++#define COEF3_RGB_2_YUV 0x836e13 ++ ++#define ENABLE_MOTION_ENC (0x1<<3) ++#define DISABLE_MOTION_ENC (0x0<<3) ++ ++#define ENABLE_MOTION_DEC (0x1<<0) ++#define DISABLE_MOTION_DEC (0x0<<0) ++ ++#define ENABLE_HW_DEC (0x1<<2) ++#define DISABLE_HW_DEC (0x0<<2) ++ ++#define INCREMENTAL_DEC (0x1<<3) ++#define NORMAL_DEC (0x0<<3) ++#define YCBCR_MEMORY (0x1<<5) ++ ++#define ENABLE_IRQ (0xf<<3) ++ ++typedef struct tagS3C6400_JPG_HOSTIF_REG ++{ ++ UINT32 JPGMod; //0x000 ++ UINT32 JPGStatus; //0x004 ++ UINT32 JPGQTblNo; //0x008 ++ UINT32 JPGRSTPos; //0x00C ++ UINT32 JPGY; //0x010 ++ UINT32 JPGX; //0x014 ++ UINT32 JPGDataSize; //0x018 ++ UINT32 JPGIRQ; //0x01C ++ UINT32 JPGIRQStatus; //0x020 ++ UINT32 dummy0[247]; ++ ++ UINT32 JQTBL0[64]; //0x400 ++ UINT32 JQTBL1[64]; //0x500 ++ UINT32 JQTBL2[64]; //0x600 ++ UINT32 JQTBL3[64]; //0x700 ++ UINT32 JHDCTBL0[16]; //0x800 ++ UINT32 JHDCTBLG0[12]; //0x840 ++ UINT32 dummy1[4]; ++ UINT32 JHACTBL0[16]; //0x880 ++ UINT32 JHACTBLG0[162]; //0x8c0 ++ UINT32 dummy2[46]; ++ UINT32 JHDCTBL1[16]; //0xc00 ++ UINT32 JHDCTBLG1[12]; //0xc40 ++ UINT32 dummy3[4]; ++ UINT32 JHACTBL1[16]; //0xc80 ++ UINT32 JHACTBLG1[162]; //0xcc0 ++ UINT32 dummy4[46]; ++ ++ UINT32 JPGYUVAddr0; //0x1000 ++ UINT32 JPGYUVAddr1; //0x1004 ++ UINT32 JPGFileAddr0; //0x1008 ++ UINT32 JPGFileAddr1; //0x100c ++ UINT32 JPGStart; //0x1010 ++ UINT32 JPGReStart; //0x1014 ++ UINT32 JPGSoftReset; //0x1018 ++ UINT32 JPGCntl; //0x101c ++ UINT32 JPGCOEF1; //0x1020 ++ UINT32 JPGCOEF2; //0x1024 ++ UINT32 JPGCOEF3; //0x1028 ++ UINT32 JPGMISC; //0x102c ++ UINT32 JPGFrameIntv; //0x1030 ++}S3C6400_JPG_HOSTIF_REG; ++ ++typedef struct tags3c6400_jpg_ctx ++{ ++ volatile S3C6400_JPG_HOSTIF_REG *v_pJPG_REG; ++ volatile UINT8 *v_pJPGData_Buff; ++ int callerProcess; ++ unsigned char *strUserBuf; ++ unsigned char *frmUserBuf; ++ unsigned char *strUserThumbBuf; ++ unsigned char *frmUserThumbBuf; ++}s3c6400_jpg_ctx; ++ ++//extern UINT32 jpg_data_base_addr; ++ ++void *phy_to_vir_addr(UINT32 phy_addr, int mem_size); ++BOOL jpeg_mem_mapping(s3c6400_jpg_ctx *base); ++void jpg_mem_free(s3c6400_jpg_ctx *base); ++BOOL jpg_buff_mapping(s3c6400_jpg_ctx *base); ++void jpg_buff_free(s3c6400_jpg_ctx *base); ++BOOL HWPostMemMapping(void); ++void HWPostMemFree(void); ++void *mem_move(void *dst, const void *src, unsigned int size); ++void *mem_alloc(unsigned int size); ++#endif ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg/jpg_misc.c linux-2.6.28.6/drivers/media/video/samsung/jpeg/jpg_misc.c +--- linux-2.6.28/drivers/media/video/samsung/jpeg/jpg_misc.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg/jpg_misc.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,100 @@ ++/* linux/drivers/media/video/samsung/jpeg/jpg_misc.c ++ * ++ * Driver file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "jpg_misc.h" ++#include "jpg_mem.h" ++ ++static HANDLE hMutex = NULL; ++extern wait_queue_head_t WaitQueue_JPEG; ++ ++/*---------------------------------------------------------------------------- ++*Function: create_jpg_mutex ++*Implementation Notes: Create Mutex handle ++-----------------------------------------------------------------------------*/ ++HANDLE create_jpg_mutex(void) ++{ ++ hMutex = (HANDLE)kmalloc(sizeof(struct mutex), GFP_KERNEL); ++ if (hMutex == NULL) ++ return NULL; ++ ++ mutex_init(hMutex); ++ ++ return hMutex; ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: lock_jpg_mutex ++*Implementation Notes: lock mutex ++-----------------------------------------------------------------------------*/ ++DWORD lock_jpg_mutex(void) ++{ ++ mutex_lock(hMutex); ++ return 1; ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: unlock_jpg_mutex ++*Implementation Notes: unlock mutex ++-----------------------------------------------------------------------------*/ ++DWORD unlock_jpg_mutex(void) ++{ ++ mutex_unlock(hMutex); ++ ++ return 1; ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: delete_jpg_mutex ++*Implementation Notes: delete mutex handle ++-----------------------------------------------------------------------------*/ ++void delete_jpg_mutex(void) ++{ ++ if (hMutex == NULL) ++ return; ++ ++ mutex_destroy(hMutex); ++} ++ ++unsigned int get_fb0_addr(void) ++{ ++ return readl(S3C_VIDW00ADD0B0); ++} ++ ++void get_lcd_size(int *width, int *height) ++{ ++ unsigned int tmp; ++ ++ tmp = readl(S3C_VIDTCON2); ++ *height = ((tmp >> 11) & 0x7FF) + 1; ++ *width = (tmp & 0x7FF) + 1; ++} ++ ++void wait_for_interrupt(void) ++{ ++ interruptible_sleep_on_timeout(&WaitQueue_JPEG, 100); ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg/jpg_misc.h linux-2.6.28.6/drivers/media/video/samsung/jpeg/jpg_misc.h +--- linux-2.6.28/drivers/media/video/samsung/jpeg/jpg_misc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg/jpg_misc.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,35 @@ ++/* linux/drivers/media/video/samsung/jpeg/jpg_misc.h ++ * ++ * Driver header file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __JPG_MISC_H__ ++#define __JPG_MISC_H__ ++ ++#include ++ ++typedef unsigned char UCHAR; ++typedef unsigned long ULONG; ++typedef unsigned int UINT; ++typedef struct mutex * HANDLE; ++typedef unsigned long DWORD; ++typedef unsigned int UINT32; ++typedef unsigned char UINT8; ++typedef enum {FALSE, TRUE} BOOL; ++ ++HANDLE create_jpg_mutex(void); ++DWORD lock_jpg_mutex(void); ++DWORD unlock_jpg_mutex(void); ++void delete_jpg_mutex(void); ++unsigned int get_fb0_addr(void); ++void get_lcd_size(int *width, int *height); ++void wait_for_interrupt(void); ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg/jpg_opr.c linux-2.6.28.6/drivers/media/video/samsung/jpeg/jpg_opr.c +--- linux-2.6.28/drivers/media/video/samsung/jpeg/jpg_opr.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg/jpg_opr.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,460 @@ ++/* linux/drivers/media/video/samsung/jpeg/jpg_opr.c ++ * ++ * Driver file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include "jpg_mem.h" ++#include "jpg_misc.h" ++#include "jpg_opr.h" ++#include "jpg_conf.h" ++#include "log_msg.h" ++ ++extern int jpg_irq_reason; ++ ++enum{ ++ UNKNOWN, ++ BASELINE = 0xC0, ++ EXTENDED_SEQ = 0xC1, ++ PROGRESSIVE = 0xC2 ++}JPG_SOF_MARKER; ++ ++ ++/*---------------------------------------------------------------------------- ++*Function: decode_jpg ++ ++*Parameters: jCTX: ++ input_buff: ++ input_size: ++ output_buff: ++ output_size ++*Return Value: ++*Implementation Notes: ++-----------------------------------------------------------------------------*/ ++JPG_RETURN_STATUS decode_jpg(s3c6400_jpg_ctx *jCTX, ++ JPG_DEC_PROC_PARAM *decParam) ++{ ++ volatile int ret; ++ SAMPLE_MODE_T sampleMode; ++ UINT32 width, height, orgwidth, orgheight; ++ BOOL headerFixed = FALSE; ++ ++ log_msg(LOG_TRACE, "decode_jpg", "decode_jpg function\n"); ++ reset_jpg(jCTX); ++ ++ ///////////////////////////////////////////////////////// ++ // Header Parsing // ++ ///////////////////////////////////////////////////////// ++ ++ decode_header(jCTX); ++ wait_for_interrupt(); ++ ret = jpg_irq_reason; ++ ++ if(ret != OK_HD_PARSING){ ++ log_msg(LOG_ERROR, "\ndecode_jpg", "DD::JPG Header Parsing Error(%d)\r\n", ret); ++ return JPG_FAIL; ++ } ++ ++ sampleMode = get_sample_type(jCTX); ++ log_msg(LOG_TRACE, "decode_jpg", "sampleMode : %d\n", sampleMode); ++ if(sampleMode == JPG_SAMPLE_UNKNOWN){ ++ log_msg(LOG_ERROR, "decode_jpg", "DD::JPG has invalid sampleMode\r\n"); ++ return JPG_FAIL; ++ } ++ decParam->sampleMode = sampleMode; ++ ++ getXY(jCTX, &width, &height); ++ log_msg(LOG_TRACE, "decode_jpg", "DD:: width : 0x%x height : 0x%x\n", width, height); ++ if(width <= 0 || width > MAX_JPG_WIDTH || height <= 0 || height > MAX_JPG_HEIGHT){ ++ log_msg(LOG_ERROR, "decode_jpg", "DD::JPG has invalid width/height\n"); ++ return JPG_FAIL; ++ } ++ ++ ///////////////////////////////////////////////////////// ++ // Header Correction // ++ ///////////////////////////////////////////////////////// ++ ++ orgwidth = width; ++ orgheight = height; ++ if(!is_correct_header(sampleMode, &width, &height)){ ++ rewrite_header(jCTX, decParam->fileSize, width, height); ++ headerFixed = TRUE; ++ } ++ ++ ++ ///////////////////////////////////////////////////////// ++ // Body Decoding // ++ ///////////////////////////////////////////////////////// ++ ++ if(headerFixed){ ++ reset_jpg(jCTX); ++ decode_header(jCTX); ++ wait_for_interrupt(); ++ ret = jpg_irq_reason; ++ ++ if(ret != OK_HD_PARSING){ ++ log_msg(LOG_ERROR, "decode_jpg", "JPG Header Parsing Error(%d)\r\n", ret); ++ return JPG_FAIL; ++ } ++ ++ decode_body(jCTX); ++ wait_for_interrupt(); ++ ret = jpg_irq_reason; ++ ++ if(ret != OK_ENC_OR_DEC){ ++ log_msg(LOG_ERROR, "decode_jpg", "JPG Body Decoding Error(%d)\n", ret); ++ return JPG_FAIL; ++ } ++ ++ // for post processor, discard pixel ++ if(orgwidth % 4 != 0) ++ orgwidth = (orgwidth/4)*4; ++ ++ log_msg(LOG_TRACE, "decode_jpg", "orgwidth : %d orgheight : %d\n", orgwidth, orgheight); ++ rewrite_yuv(jCTX, width, orgwidth, height, orgheight); ++ ++ // JPEG H/W IP always return YUV422 ++ decParam->dataSize = getYUVSize(JPG_422, orgwidth, orgheight); ++ decParam->width = orgwidth; ++ decParam->height = orgheight; ++ } ++ else{ ++ decode_body(jCTX); ++ wait_for_interrupt(); ++ ret = jpg_irq_reason; ++ ++ if(ret != OK_ENC_OR_DEC){ ++ log_msg(LOG_ERROR, "decode_jpg", "DD::JPG Body Decoding Error(%d)\n", ret); ++ return JPG_FAIL; ++ } ++ ++ // JPEG H/W IP always return YUV422 ++ decParam->dataSize = getYUVSize(JPG_422, width, height); ++ decParam->width = width; ++ decParam->height = height; ++ } ++ ++ return JPG_SUCCESS; ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: is_correct_header ++ ++*Parameters: sampleMode: ++ width: ++ height: ++*Return Value: ++*Implementation Notes: ++-----------------------------------------------------------------------------*/ ++BOOL is_correct_header(SAMPLE_MODE_T sampleMode, UINT32 *width, UINT32 *height) ++{ ++ BOOL result = FALSE; ++ ++ log_msg(LOG_TRACE, "is_correct_header", "Header is not multiple of MCU\n"); ++ ++ switch(sampleMode){ ++ case JPG_400 : ++ case JPG_444 : if((*width % 8 == 0) && (*height % 8 == 0)) ++ result = TRUE; ++ if(*width % 8 != 0) ++ *width += 8 - (*width % 8); ++ if(*height % 8 != 0) ++ *height += 8 - (*height % 8); ++ break; ++ case JPG_422 : if((*width % 16 == 0) && (*height % 8 == 0)) ++ result = TRUE; ++ if(*width % 16 != 0) ++ *width += 16 - (*width % 16); ++ if(*height % 8 != 0) ++ *height += 8 - (*height % 8); ++ break; ++ case JPG_420 : ++ case JPG_411 : if((*width % 16 == 0) && (*height % 16 == 0)) ++ result = TRUE; ++ if(*width % 16 != 0) ++ *width += 16 - (*width % 16); ++ if(*height % 16 != 0) ++ *height += 16 - (*height % 16); ++ break; ++ default : break; ++ } ++ ++ log_msg(LOG_TRACE, "is_correct_header", "after error correction : width(%x) height(%x)\n", *width, *height); ++ return(result); ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: rewrite_header ++ ++*Parameters: jCTX: ++ file_size: ++ width: ++ height: ++*Return Value: ++*Implementation Notes: ++-----------------------------------------------------------------------------*/ ++void rewrite_header(s3c6400_jpg_ctx *jCTX, UINT32 file_size, UINT32 width, UINT32 height) ++{ ++ UINT32 i; ++ UINT8 *ptr = (UINT8 *)jCTX->v_pJPGData_Buff; ++ UINT8 *SOF1 = NULL, *SOF2 = NULL; ++ UINT8 *header = NULL; ++ ++ log_msg(LOG_TRACE, "rewrite_header", "file size : %d, v_pJPGData_Buff : 0x%X\n", file_size, ptr); ++ ++ for(i=0; i < file_size; i++){ ++ if(*ptr++ == 0xFF){ ++ if((*ptr == BASELINE) || (*ptr == EXTENDED_SEQ) || (*ptr == PROGRESSIVE)){ ++ log_msg(LOG_TRACE, "rewrite_header", "match FFC0(i : %d)\n", i); ++ if(SOF1 == NULL) ++ SOF1 = ++ptr; ++ else{ ++ SOF2 = ++ptr; ++ break; ++ } ++ } ++ } ++ } ++ ++ log_msg(LOG_TRACE, "rewrite_header", "start header correction\n"); ++ if(i <= file_size){ ++ header = (SOF2 == NULL) ? (SOF1) : (SOF2); ++ header += 3; //length(2) + sampling bit(1) ++ *header = (height>>8) & 0xFF; ++ header++; ++ *header = height & 0xFF; ++ header++; ++ *header = (width>>8) & 0xFF; ++ header++; ++ *header = (width & 0xFF); ++ ++ } ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: reset_jpg ++ ++*Parameters: jCTX: ++*Return Value: ++*Implementation Notes: ++-----------------------------------------------------------------------------*/ ++void reset_jpg(s3c6400_jpg_ctx *jCTX) ++{ ++ log_msg(LOG_TRACE, "reset_jpg", "reset_jpg function\n"); ++ jCTX->v_pJPG_REG->JPGSoftReset = 0; //ENABLE ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: decode_header ++ ++*Parameters: jCTX: ++*Return Value: ++*Implementation Notes: ++-----------------------------------------------------------------------------*/ ++void decode_header(s3c6400_jpg_ctx *jCTX) ++{ ++ log_msg(LOG_TRACE, "decode_header", "decode_header function\n"); ++ jCTX->v_pJPG_REG->JPGFileAddr0 = jpg_data_base_addr; ++ jCTX->v_pJPG_REG->JPGFileAddr1 = jpg_data_base_addr; ++ ++ jCTX->v_pJPG_REG->JPGMod = 0x08; //decoding mode ++ jCTX->v_pJPG_REG->JPGIRQ = ENABLE_IRQ; ++ jCTX->v_pJPG_REG->JPGCntl = DISABLE_HW_DEC; ++ jCTX->v_pJPG_REG->JPGMISC = (NORMAL_DEC | YCBCR_MEMORY); ++ jCTX->v_pJPG_REG->JPGStart = 1; ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: decode_body ++ ++*Parameters: jCTX: ++*Return Value: ++*Implementation Notes: ++-----------------------------------------------------------------------------*/ ++void decode_body(s3c6400_jpg_ctx *jCTX) ++{ ++ log_msg(LOG_TRACE, "decode_body", "decode_body function\n"); ++ jCTX->v_pJPG_REG->JPGYUVAddr0 = jpg_data_base_addr + JPG_STREAM_BUF_SIZE + JPG_STREAM_THUMB_BUF_SIZE; ++ jCTX->v_pJPG_REG->JPGYUVAddr1 = jpg_data_base_addr + JPG_STREAM_BUF_SIZE + JPG_STREAM_THUMB_BUF_SIZE; ++ ++ jCTX->v_pJPG_REG->JPGCntl = 0; ++ jCTX->v_pJPG_REG->JPGMISC = 0; ++ jCTX->v_pJPG_REG->JPGReStart = 1; ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: rewrite_yuv ++ ++*Parameters: jCTX: ++ width: ++ orgwidth: ++ height: ++ orgheight: ++*Return Value: ++*Implementation Notes: ++-----------------------------------------------------------------------------*/ ++void rewrite_yuv(s3c6400_jpg_ctx *jCTX, UINT32 width, UINT32 orgwidth, UINT32 height, UINT32 orgheight) ++{ ++ UINT32 src, dst; ++ UINT32 i; ++ UINT8 *streamPtr; ++ ++ log_msg(LOG_TRACE, "rewrite_yuv", "rewrite_yuv function\n"); ++ ++ streamPtr = (UINT8 *)(jCTX->v_pJPGData_Buff + JPG_STREAM_BUF_SIZE + JPG_STREAM_THUMB_BUF_SIZE); ++ src = 2*width; ++ dst = 2*orgwidth; ++ for(i = 1; i < orgheight; i++){ ++ mem_move(&streamPtr[dst], &streamPtr[src], 2*orgwidth); ++ src += 2*width; ++ dst += 2*orgwidth; ++ } ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: get_sample_type ++ ++*Parameters: jCTX: ++*Return Value: ++*Implementation Notes: ++-----------------------------------------------------------------------------*/ ++SAMPLE_MODE_T get_sample_type(s3c6400_jpg_ctx *jCTX) ++{ ++ ULONG jpgMode; ++ SAMPLE_MODE_T sampleMode; ++ ++ jpgMode = jCTX->v_pJPG_REG->JPGMod; ++ ++ sampleMode = ++ ((jpgMode&0x7) == 0) ? JPG_444 : ++ ((jpgMode&0x7) == 1) ? JPG_422 : ++ ((jpgMode&0x7) == 2) ? JPG_420 : ++ ((jpgMode&0x7) == 3) ? JPG_400 : ++ ((jpgMode&0x7) == 6) ? JPG_411 : JPG_SAMPLE_UNKNOWN; ++ ++ return(sampleMode); ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: getXY ++ ++*Parameters: jCTX: ++ x: ++ y: ++*Return Value: ++*Implementation Notes: ++-----------------------------------------------------------------------------*/ ++void getXY(s3c6400_jpg_ctx *jCTX, UINT32 *x, UINT32 *y) ++{ ++ *x = jCTX->v_pJPG_REG->JPGX; ++ *y = jCTX->v_pJPG_REG->JPGY; ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: getYUVSize ++ ++*Parameters: sampleMode: ++ width: ++ height: ++*Return Value: ++*Implementation Notes: ++-----------------------------------------------------------------------------*/ ++UINT32 getYUVSize(SAMPLE_MODE_T sampleMode, UINT32 width, UINT32 height) ++{ ++ switch(sampleMode){ ++ case JPG_444 : return(width*height*3); ++ case JPG_422 : return(width*height*2); ++ case JPG_420 : ++ case JPG_411 : return((width*height*3)>>1); ++ case JPG_400 : return(width*height); ++ default : return(0); ++ } ++ ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: reset_jpg ++ ++*Parameters: jCTX: ++*Return Value: ++*Implementation Notes: ++-----------------------------------------------------------------------------*/ ++JPG_RETURN_STATUS encode_jpg(s3c6400_jpg_ctx *jCTX, ++ JPG_ENC_PROC_PARAM *EncParam) ++{ ++ UINT i, ret; ++ ++ if(EncParam->width <= 0 || EncParam->width > MAX_JPG_WIDTH ++ || EncParam->height <=0 || EncParam->height > MAX_JPG_HEIGHT){ ++ log_msg(LOG_ERROR, "encode_jpg", "DD::Encoder : Invalid width/height\r\n"); ++ return JPG_FAIL; ++ } ++ ++ reset_jpg(jCTX); ++ ++ jCTX->v_pJPG_REG->JPGMod = (EncParam->sampleMode == JPG_422) ? (0x1<<0) : (0x2<<0); ++ jCTX->v_pJPG_REG->JPGRSTPos = 2; // MCU inserts RST marker ++ jCTX->v_pJPG_REG->JPGQTblNo = (1<<12) | (1<<14); ++ jCTX->v_pJPG_REG->JPGX = EncParam->width; ++ jCTX->v_pJPG_REG->JPGY = EncParam->height; ++ ++ log_msg(LOG_TRACE, "encode_jpg", "EncParam->encType : %d\n", EncParam->encType); ++ if(EncParam->encType == JPG_MAIN){ ++ jCTX->v_pJPG_REG->JPGYUVAddr0 = jpg_data_base_addr + JPG_STREAM_BUF_SIZE + JPG_STREAM_THUMB_BUF_SIZE; // Address of input image ++ jCTX->v_pJPG_REG->JPGYUVAddr1 = jpg_data_base_addr + JPG_STREAM_BUF_SIZE + JPG_STREAM_THUMB_BUF_SIZE; // Address of input image ++ jCTX->v_pJPG_REG->JPGFileAddr0 = jpg_data_base_addr; // Address of JPEG stream ++ jCTX->v_pJPG_REG->JPGFileAddr1 = jpg_data_base_addr; // next address of motion JPEG stream ++ } ++ else{ // thumbnail encoding ++ jCTX->v_pJPG_REG->JPGYUVAddr0 = jpg_data_base_addr + JPG_STREAM_BUF_SIZE + JPG_STREAM_THUMB_BUF_SIZE + JPG_FRAME_BUF_SIZE; // Address of input image ++ jCTX->v_pJPG_REG->JPGYUVAddr1 = jpg_data_base_addr + JPG_STREAM_BUF_SIZE + JPG_STREAM_THUMB_BUF_SIZE + JPG_FRAME_BUF_SIZE; // Address of input image ++ jCTX->v_pJPG_REG->JPGFileAddr0 = jpg_data_base_addr + JPG_STREAM_BUF_SIZE; // Address of JPEG stream ++ jCTX->v_pJPG_REG->JPGFileAddr1 = jpg_data_base_addr + JPG_STREAM_BUF_SIZE; // next address of motion JPEG stream ++ } ++ jCTX->v_pJPG_REG->JPGCOEF1 = COEF1_RGB_2_YUV; // Coefficient value 1 for RGB to YCbCr ++ jCTX->v_pJPG_REG->JPGCOEF2 = COEF2_RGB_2_YUV; // Coefficient value 2 for RGB to YCbCr ++ jCTX->v_pJPG_REG->JPGCOEF3 = COEF3_RGB_2_YUV; // Coefficient value 3 for RGB to YCbCr ++ ++ jCTX->v_pJPG_REG->JPGMISC = (1<<5) | (0<<2); ++ jCTX->v_pJPG_REG->JPGCntl = DISABLE_MOTION_ENC; ++ ++ ++ // Quantiazation and Huffman Table setting ++ for (i=0; i<64; i++) ++ jCTX->v_pJPG_REG->JQTBL0[i] = (UINT32)QTBL_Luminance[EncParam->quality][i]; ++ ++ for (i=0; i<64; i++) ++ jCTX->v_pJPG_REG->JQTBL1[i] = (UINT32)QTBL_Chrominance[EncParam->quality][i]; ++ ++ for (i=0; i<16; i++) ++ jCTX->v_pJPG_REG->JHDCTBL0[i] = (UINT32)HDCTBL0[i]; ++ ++ for (i=0; i<12; i++) ++ jCTX->v_pJPG_REG->JHDCTBLG0[i] = (UINT32)HDCTBLG0[i]; ++ ++ for (i=0; i<16; i++) ++ jCTX->v_pJPG_REG->JHACTBL0[i] = (UINT32)HACTBL0[i]; ++ ++ for (i=0; i<162; i++) ++ jCTX->v_pJPG_REG->JHACTBLG0[i] = (UINT32)HACTBLG0[i]; ++ ++ jCTX->v_pJPG_REG->JPGStart = 0; ++ ++ wait_for_interrupt(); ++ ret = jpg_irq_reason; ++ ++ if(ret != OK_ENC_OR_DEC){ ++ log_msg(LOG_ERROR, "encode_jpg", "DD::JPG Encoding Error(%d)\n", ret); ++ return JPG_FAIL; ++ } ++ ++ EncParam->fileSize = jCTX->v_pJPG_REG->JPGDataSize; ++ return JPG_SUCCESS; ++ ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg/jpg_opr.h linux-2.6.28.6/drivers/media/video/samsung/jpeg/jpg_opr.h +--- linux-2.6.28/drivers/media/video/samsung/jpeg/jpg_opr.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg/jpg_opr.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,85 @@ ++/* linux/drivers/media/video/samsung/jpeg/jpg_opr.h ++ * ++ * Driver header file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __JPG_OPR_H__ ++#define __JPG_OPR_H__ ++ ++ ++typedef enum tagJPG_RETURN_STATUS{ ++ JPG_FAIL, ++ JPG_SUCCESS, ++ OK_HD_PARSING, ++ ERR_HD_PARSING, ++ OK_ENC_OR_DEC, ++ ERR_ENC_OR_DEC, ++ ERR_UNKNOWN ++}JPG_RETURN_STATUS; ++ ++typedef enum tagIMAGE_TYPE_T{ ++ JPG_RGB16, ++ JPG_YCBYCR, ++ JPG_TYPE_UNKNOWN ++}IMAGE_TYPE_T; ++ ++typedef enum tagSAMPLE_MODE_T{ ++ JPG_444, ++ JPG_422, ++ JPG_420, ++ JPG_411, ++ JPG_400, ++ JPG_SAMPLE_UNKNOWN ++}SAMPLE_MODE_T; ++ ++typedef enum tagENCDEC_TYPE_T{ ++ JPG_MAIN, ++ JPG_THUMBNAIL ++}ENCDEC_TYPE_T; ++ ++typedef enum tagIMAGE_QUALITY_TYPE_T{ ++ JPG_QUALITY_LEVEL_1 = 0, /*high quality*/ ++ JPG_QUALITY_LEVEL_2, ++ JPG_QUALITY_LEVEL_3, ++ JPG_QUALITY_LEVEL_4 /*low quality*/ ++}IMAGE_QUALITY_TYPE_T; ++ ++typedef struct tagJPG_DEC_PROC_PARAM{ ++ SAMPLE_MODE_T sampleMode; ++ ENCDEC_TYPE_T decType; ++ UINT32 width; ++ UINT32 height; ++ UINT32 dataSize; ++ UINT32 fileSize; ++} JPG_DEC_PROC_PARAM; ++ ++typedef struct tagJPG_ENC_PROC_PARAM{ ++ SAMPLE_MODE_T sampleMode; ++ ENCDEC_TYPE_T encType; ++ IMAGE_QUALITY_TYPE_T quality; ++ UINT32 width; ++ UINT32 height; ++ UINT32 dataSize; ++ UINT32 fileSize; ++} JPG_ENC_PROC_PARAM; ++ ++JPG_RETURN_STATUS decode_jpg(s3c6400_jpg_ctx *jCTX, JPG_DEC_PROC_PARAM *decParam); ++void reset_jpg(s3c6400_jpg_ctx *jCTX); ++void decode_header(s3c6400_jpg_ctx *jCTX); ++void decode_body(s3c6400_jpg_ctx *jCTX); ++SAMPLE_MODE_T get_sample_type(s3c6400_jpg_ctx *jCTX); ++void getXY(s3c6400_jpg_ctx *jCTX, UINT32 *x, UINT32 *y); ++UINT32 getYUVSize(SAMPLE_MODE_T sampleMode, UINT32 width, UINT32 height); ++BOOL is_correct_header(SAMPLE_MODE_T sampleMode, UINT32 *width, UINT32 *height); ++void rewrite_header(s3c6400_jpg_ctx *jCTX, UINT32 file_size, UINT32 width, UINT32 height); ++void rewrite_yuv(s3c6400_jpg_ctx *jCTX, UINT32 width, UINT32 orgwidth, UINT32 height, UINT32 orgheight); ++JPG_RETURN_STATUS encode_jpg(s3c6400_jpg_ctx *jCTX, JPG_ENC_PROC_PARAM *EncParam); ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg/log_msg.c linux-2.6.28.6/drivers/media/video/samsung/jpeg/log_msg.c +--- linux-2.6.28/drivers/media/video/samsung/jpeg/log_msg.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg/log_msg.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,53 @@ ++/* linux/drivers/media/video/samsung/jpeg/jpg_msg.c ++ * ++ * Driver file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "log_msg.h" ++ ++//#define DEBUG ++ ++static const LOG_LEVEL log_level = LOG_TRACE; ++ ++static const char *modulename = "JPEG_DRV"; ++ ++static const char *level_str[] = {"TRACE", "WARNING", "ERROR"}; ++ ++void log_msg(LOG_LEVEL level, const char *func_name, const char *msg, ...) ++{ ++ ++ char buf[256]; ++ va_list argptr; ++ ++ if (level < log_level) ++ return; ++ ++ sprintf(buf, "[%s: %s] %s: ", modulename, level_str[level], func_name); ++ ++ va_start(argptr, msg); ++ vsprintf(buf + strlen(buf), msg, argptr); ++ ++ if(level == LOG_TRACE){ ++ #ifdef DEBUG ++ printk(buf); ++ #endif ++ } else { ++ printk(buf); ++ } ++ ++ va_end(argptr); ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg/log_msg.h linux-2.6.28.6/drivers/media/video/samsung/jpeg/log_msg.h +--- linux-2.6.28/drivers/media/video/samsung/jpeg/log_msg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg/log_msg.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,36 @@ ++/* linux/drivers/media/video/samsung/jpeg/jpg_msg.h ++ * ++ * Driver header file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __SAMSUNG_SYSLSI_APDEV_log_msg_H__ ++#define __SAMSUNG_SYSLSI_APDEV_log_msg_H__ ++ ++ ++typedef enum ++{ ++ LOG_TRACE = 0, ++ LOG_WARNING = 1, ++ LOG_ERROR = 2 ++} LOG_LEVEL; ++ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++ ++void log_msg(LOG_LEVEL level, const char *func_name, const char *msg, ...); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* __SAMSUNG_SYSLSI_APDEV_log_msg_H__ */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg/s3c-jpeg.c linux-2.6.28.6/drivers/media/video/samsung/jpeg/s3c-jpeg.c +--- linux-2.6.28/drivers/media/video/samsung/jpeg/s3c-jpeg.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg/s3c-jpeg.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,505 @@ ++/* linux/drivers/media/video/samsung/jpeg/s3c-jpeg.c ++ * ++ * Driver file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++#include "s3c-jpeg.h" ++#include "jpg_mem.h" ++#include "jpg_misc.h" ++#include "jpg_opr.h" ++#include "log_msg.h" ++ ++ ++static struct clk *jpeg_hclk; ++static struct clk *jpeg_sclk; ++static struct clk *post; ++static struct resource *jpeg_mem; ++static void __iomem *jpeg_base; ++static s3c6400_jpg_ctx JPGMem; ++static int irq_no; ++static int instanceNo = 0; ++volatile int jpg_irq_reason; ++ ++DECLARE_WAIT_QUEUE_HEAD(WaitQueue_JPEG); ++ ++irqreturn_t s3c_jpeg_irq(int irq, void *dev_id, struct pt_regs *regs) ++{ ++ unsigned int intReason; ++ unsigned int status; ++ ++ status = JPGMem.v_pJPG_REG->JPGStatus; ++ intReason = JPGMem.v_pJPG_REG->JPGIRQStatus; ++ ++ if(intReason) { ++ intReason &= ((1<<6)|(1<<4)|(1<<3)); ++ ++ switch(intReason) { ++ case 0x08 : ++ jpg_irq_reason = OK_HD_PARSING; ++ break; ++ case 0x00 : ++ jpg_irq_reason = ERR_HD_PARSING; ++ break; ++ case 0x40 : ++ jpg_irq_reason = OK_ENC_OR_DEC; ++ break; ++ case 0x10 : ++ jpg_irq_reason = ERR_ENC_OR_DEC; ++ break; ++ default : ++ jpg_irq_reason = ERR_UNKNOWN; ++ } ++ wake_up_interruptible(&WaitQueue_JPEG); ++ } ++ else { ++ jpg_irq_reason = ERR_UNKNOWN; ++ wake_up_interruptible(&WaitQueue_JPEG); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int s3c_jpeg_open(struct inode *inode, struct file *file) ++{ ++ s3c6400_jpg_ctx *JPGRegCtx; ++ DWORD ret; ++ ++ clk_enable(jpeg_hclk); ++ clk_enable(jpeg_sclk); ++ ++ log_msg(LOG_TRACE, "s3c_jpeg_open", "JPG_open \r\n"); ++ ++ JPGRegCtx = (s3c6400_jpg_ctx *)mem_alloc(sizeof(s3c6400_jpg_ctx)); ++ memset(JPGRegCtx, 0x00, sizeof(s3c6400_jpg_ctx)); ++ ++ ret = lock_jpg_mutex(); ++ if(!ret){ ++ log_msg(LOG_ERROR, "s3c_jpeg_open", "DD::JPG Mutex Lock Fail\r\n"); ++ unlock_jpg_mutex(); ++ return FALSE; ++ } ++ ++ JPGRegCtx->v_pJPG_REG = JPGMem.v_pJPG_REG; ++ JPGRegCtx->v_pJPGData_Buff = JPGMem.v_pJPGData_Buff; ++ ++ if (instanceNo > MAX_INSTANCE_NUM){ ++ log_msg(LOG_ERROR, "s3c_jpeg_open", "DD::Instance Number error-JPEG is running, instance number is %d\n", instanceNo); ++ unlock_jpg_mutex(); ++ return FALSE; ++ } ++ ++ instanceNo++; ++ ++ unlock_jpg_mutex(); ++ ++ file->private_data = (s3c6400_jpg_ctx *)JPGRegCtx; ++ ++ return 0; ++} ++ ++ ++static int s3c_jpeg_release(struct inode *inode, struct file *file) ++{ ++ DWORD ret; ++ s3c6400_jpg_ctx *JPGRegCtx; ++ ++ log_msg(LOG_TRACE, "s3c_jpeg_release", "JPG_Close\n"); ++ ++ JPGRegCtx = (s3c6400_jpg_ctx *)file->private_data; ++ if(!JPGRegCtx){ ++ log_msg(LOG_ERROR, "s3c_jpeg_release", "DD::JPG Invalid Input Handle\r\n"); ++ return FALSE; ++ } ++ ++ ret = lock_jpg_mutex(); ++ if(!ret){ ++ log_msg(LOG_ERROR, "s3c_jpeg_release", "DD::JPG Mutex Lock Fail\r\n"); ++ return FALSE; ++ } ++ ++ //if((--instanceNo) < 0) ++ instanceNo = 0; ++ ++ unlock_jpg_mutex(); ++ ++ clk_disable(jpeg_hclk); ++ clk_disable(jpeg_sclk); ++ ++ return 0; ++} ++ ++ ++static ssize_t s3c_jpeg_write (struct file *file, const char *buf, size_t ++ count, loff_t *pos) ++{ ++ return 0; ++} ++ ++static ssize_t s3c_jpeg_read(struct file *file, char *buf, size_t count, loff_t *pos) ++{ ++ return 0; ++} ++ ++static int s3c_jpeg_ioctl(struct inode *inode, struct file *file, unsigned ++ int cmd, unsigned long arg) ++{ ++ static s3c6400_jpg_ctx *JPGRegCtx; ++ JPG_DEC_PROC_PARAM DecReturn; ++ JPG_ENC_PROC_PARAM EncParam; ++ BOOL result = TRUE; ++ DWORD ret; ++ int out; ++ ++ ++ JPGRegCtx = (s3c6400_jpg_ctx *)file->private_data; ++ if(!JPGRegCtx){ ++ log_msg(LOG_ERROR, "s3c_jpeg_ioctl", "DD::JPG Invalid Input Handle\r\n"); ++ return FALSE; ++ } ++ ++ ret = lock_jpg_mutex(); ++ if(!ret){ ++ log_msg(LOG_ERROR, "s3c_jpeg_ioctl", "DD::JPG Mutex Lock Fail\r\n"); ++ return FALSE; ++ } ++ ++ switch (cmd) ++ { ++ case IOCTL_JPG_DECODE: ++ ++ log_msg(LOG_TRACE, "s3c_jpeg_ioctl", "IOCTL_JPEG_DECODE\n"); ++ ++ out = copy_from_user(&DecReturn, (JPG_DEC_PROC_PARAM *)arg, sizeof(JPG_DEC_PROC_PARAM)); ++ result = decode_jpg(JPGRegCtx, &DecReturn); ++ ++ log_msg(LOG_TRACE, "s3c_jpeg_ioctl", "width : %d hegiht : %d size : %d\n", ++ DecReturn.width, DecReturn.height, DecReturn.dataSize); ++ ++ out = copy_to_user((void *)arg, (void *)&DecReturn, sizeof(JPG_DEC_PROC_PARAM)); ++ break; ++ ++ case IOCTL_JPG_ENCODE: ++ ++ log_msg(LOG_TRACE, "s3c_jpeg_ioctl", "IOCTL_JPEG_ENCODE\n"); ++ ++ out = copy_from_user(&EncParam, (JPG_ENC_PROC_PARAM *)arg, sizeof(JPG_ENC_PROC_PARAM)); ++ ++ log_msg(LOG_TRACE, "s3c_jpeg_ioctl", "width : %d hegiht : %d\n", ++ EncParam.width, EncParam.height); ++ ++ result = encode_jpg(JPGRegCtx, &EncParam); ++ ++ log_msg(LOG_TRACE, "s3c_jpeg_ioctl", "encoded file size : %d\n", EncParam.fileSize); ++ ++ out = copy_to_user((void *)arg, (void *)&EncParam, sizeof(JPG_ENC_PROC_PARAM)); ++ ++ break; ++ ++ case IOCTL_JPG_GET_STRBUF: ++ log_msg(LOG_TRACE, "s3c_jpeg_ioctl", "IOCTL_JPG_GET_STRBUF\n"); ++ unlock_jpg_mutex(); ++ return arg; ++ ++ case IOCTL_JPG_GET_THUMB_STRBUF: ++ log_msg(LOG_TRACE, "s3c_jpeg_ioctl", "IOCTL_JPG_GET_THUMB_STRBUF\n"); ++ unlock_jpg_mutex(); ++ return arg + JPG_STREAM_BUF_SIZE; ++ ++ case IOCTL_JPG_GET_FRMBUF: ++ log_msg(LOG_TRACE, "s3c_jpeg_ioctl", "IOCTL_JPG_GET_FRMBUF\n"); ++ unlock_jpg_mutex(); ++ return arg + JPG_STREAM_BUF_SIZE + JPG_STREAM_THUMB_BUF_SIZE; ++ ++ case IOCTL_JPG_GET_THUMB_FRMBUF: ++ log_msg(LOG_TRACE, "s3c_jpeg_ioctl", "IOCTL_JPG_GET_THUMB_FRMBUF\n"); ++ unlock_jpg_mutex(); ++ return arg + JPG_STREAM_BUF_SIZE + JPG_STREAM_THUMB_BUF_SIZE + JPG_FRAME_BUF_SIZE; ++ ++ case IOCTL_JPG_GET_PHY_FRMBUF: ++ log_msg(LOG_TRACE, "s3c_jpeg_ioctl", "IOCTL_JPG_GET_PHY_FRMBUF\n"); ++ unlock_jpg_mutex(); ++ return jpg_data_base_addr + JPG_STREAM_BUF_SIZE + JPG_STREAM_THUMB_BUF_SIZE; ++ ++ case IOCTL_JPG_GET_PHY_THUMB_FRMBUF: ++ log_msg(LOG_TRACE, "s3c_jpeg_ioctl", "IOCTL_JPG_GET_PHY_THUMB_FRMBUF\n"); ++ unlock_jpg_mutex(); ++ return jpg_data_base_addr + JPG_STREAM_BUF_SIZE + JPG_STREAM_THUMB_BUF_SIZE + JPG_FRAME_BUF_SIZE; ++ ++ default : ++ log_msg(LOG_ERROR, "s3c_jpeg_ioctl", "DD::JPG Invalid ioctl : 0x%X\r\n", cmd); ++ } ++ ++ unlock_jpg_mutex(); ++ ++ return result; ++} ++ ++ ++int s3c_jpeg_mmap(struct file *filp, struct vm_area_struct *vma) ++{ ++ unsigned long size = vma->vm_end - vma->vm_start; ++ unsigned long maxSize; ++ unsigned long pageFrameNo; ++ ++ pageFrameNo = __phys_to_pfn(jpg_data_base_addr); ++ ++ maxSize = JPG_TOTAL_BUF_SIZE + PAGE_SIZE - (JPG_TOTAL_BUF_SIZE % PAGE_SIZE); ++ ++ if(size > maxSize) { ++ return -EINVAL; ++ } ++ ++ vma->vm_flags |= VM_RESERVED | VM_IO; ++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ ++ if( remap_pfn_range(vma, vma->vm_start, pageFrameNo, size, \ ++ vma->vm_page_prot) ) { ++ log_msg(LOG_ERROR, "s3c_jpeg_mmap", "jpeg remap error"); ++ return -EAGAIN; ++ } ++ ++ return 0; ++} ++ ++ ++static struct file_operations jpeg_fops = { ++owner: THIS_MODULE, ++ open: s3c_jpeg_open, ++ release: s3c_jpeg_release, ++ ioctl: s3c_jpeg_ioctl, ++ read: s3c_jpeg_read, ++ write: s3c_jpeg_write, ++ mmap: s3c_jpeg_mmap, ++}; ++ ++ ++static struct miscdevice s3c_jpeg_miscdev = { ++minor: 254, ++ name: "s3c-jpg", ++ fops: &jpeg_fops ++}; ++ ++static BOOL s3c_jpeg_clock_setup(void) ++{ ++ unsigned int jpg_clk; ++ ++ // JPEG clock was set as 66 MHz ++ jpg_clk = readl(S3C_CLK_DIV0); ++ jpg_clk = (jpg_clk & ~(0xF << 24)) | (3 << 24); ++ __raw_writel(jpg_clk, S3C_CLK_DIV0); ++ ++ return TRUE; ++ ++} ++ ++static int s3c_jpeg_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ static int size; ++ static int ret; ++ HANDLE h_Mutex; ++ unsigned int jpg_clk; ++ ++ ++ // JPEG clock enable ++ jpeg_hclk = clk_get(&pdev->dev, "hclk_jpeg"); ++ if (!jpeg_hclk || IS_ERR(jpeg_hclk)) { ++ printk(KERN_ERR "failed to get jpeg hclk source\n"); ++ return -ENOENT; ++ } ++ clk_enable(jpeg_hclk); ++ ++ jpeg_sclk = clk_get(&pdev->dev, "sclk_jpeg"); ++ if (!jpeg_sclk || IS_ERR(jpeg_sclk)) { ++ printk(KERN_ERR "failed to get jpeg scllk source\n"); ++ return -ENOENT; ++ } ++ clk_enable(jpeg_sclk); ++/* ++ post = clk_get(NULL, "post"); ++ if (!post) { ++ printk(KERN_ERR "failed to get post clock source\n"); ++ return -ENOENT; ++ } ++ clk_enable(post); ++*/ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (res == NULL) { ++ printk(KERN_INFO "failed to get memory region resouce\n"); ++ return -ENOENT; ++ } ++ ++ size = (res->end-res->start)+1; ++ jpeg_mem = request_mem_region(res->start, size, pdev->name); ++ if (jpeg_mem == NULL) { ++ printk(KERN_INFO "failed to get memory region\n"); ++ return -ENOENT; ++ } ++ ++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (res == NULL) { ++ printk(KERN_INFO "failed to get irq resource\n"); ++ return -ENOENT; ++ } ++ ++ irq_no = res->start; ++ ret = request_irq(res->start, s3c_jpeg_irq, 0, pdev->name, pdev); ++ if (ret != 0) { ++ printk(KERN_INFO "failed to install irq (%d)\n", ret); ++ return ret; ++ } ++ ++ jpeg_base = ioremap(res->start, size); ++ if (jpeg_base == 0) { ++ printk(KERN_INFO "failed to ioremap() region\n"); ++ return -EINVAL; ++ } ++ ++ // JPEG clock was set as 66 MHz ++ if (s3c_jpeg_clock_setup() == FALSE) ++ return -ENODEV; ++ ++ log_msg(LOG_TRACE, "s3c_jpeg_probe", "JPG_Init\n"); ++ ++ // Mutex initialization ++ h_Mutex = create_jpg_mutex(); ++ if (h_Mutex == NULL) ++ { ++ log_msg(LOG_ERROR, "s3c_jpeg_probe", "DD::JPG Mutex Initialize error\r\n"); ++ return FALSE; ++ } ++ ++ ret = lock_jpg_mutex(); ++ if (!ret){ ++ log_msg(LOG_ERROR, "s3c_jpeg_probe", "DD::JPG Mutex Lock Fail\n"); ++ return FALSE; ++ } ++ ++ // Memory initialization ++ if( !jpeg_mem_mapping(&JPGMem) ){ ++ log_msg(LOG_ERROR, "s3c_jpeg_probe", "DD::JPEG-HOST-MEMORY Initialize error\r\n"); ++ unlock_jpg_mutex(); ++ return FALSE; ++ } ++ else { ++ if (!jpg_buff_mapping(&JPGMem)){ ++ log_msg(LOG_ERROR, "s3c_jpeg_probe", "DD::JPEG-DATA-MEMORY Initialize error : %d\n"); ++ unlock_jpg_mutex(); ++ return FALSE; ++ } ++ } ++ ++ instanceNo = 0; ++ ++ unlock_jpg_mutex(); ++ ++ ret = misc_register(&s3c_jpeg_miscdev); ++ ++ clk_disable(jpeg_hclk); ++ clk_disable(jpeg_sclk); ++ ++ return 0; ++} ++ ++static int s3c_jpeg_remove(struct platform_device *dev) ++{ ++ if (jpeg_mem != NULL) { ++ release_resource(jpeg_mem); ++ kfree(jpeg_mem); ++ jpeg_mem = NULL; ++ } ++ ++ free_irq(irq_no, dev); ++ misc_deregister(&s3c_jpeg_miscdev); ++ return 0; ++} ++ ++ ++static struct platform_driver s3c_jpeg_driver = { ++ .probe = s3c_jpeg_probe, ++ .remove = s3c_jpeg_remove, ++ .shutdown = NULL, ++ .suspend = NULL, ++ .resume = NULL, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "s3c-jpeg", ++ }, ++}; ++ ++static char banner[] __initdata = KERN_INFO "S3C JPEG Driver, (c) 2007 Samsung Electronics\n"; ++ ++static int __init s3c_jpeg_init(void) ++{ ++ printk(banner); ++ return platform_driver_register(&s3c_jpeg_driver); ++} ++ ++static void __exit s3c_jpeg_exit(void) ++{ ++ DWORD ret; ++ ++ log_msg(LOG_TRACE, "s3c_jpeg_exit", "JPG_Deinit\n"); ++ ++ ret = lock_jpg_mutex(); ++ if(!ret){ ++ log_msg(LOG_ERROR, "s3c_jpeg_exit", "DD::JPG Mutex Lock Fail\r\n"); ++ } ++ ++ jpg_buff_free(&JPGMem); ++ jpg_mem_free(&JPGMem); ++ unlock_jpg_mutex(); ++ ++ delete_jpg_mutex(); ++ ++ platform_driver_unregister(&s3c_jpeg_driver); ++ printk("S3C JPEG driver module exit\n"); ++} ++ ++module_init(s3c_jpeg_init); ++module_exit(s3c_jpeg_exit); ++ ++MODULE_AUTHOR("Peter, Oh"); ++MODULE_DESCRIPTION("S3C JPEG Encoder/Decoder Device Driver"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg/s3c-jpeg.h linux-2.6.28.6/drivers/media/video/samsung/jpeg/s3c-jpeg.h +--- linux-2.6.28/drivers/media/video/samsung/jpeg/s3c-jpeg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg/s3c-jpeg.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,28 @@ ++/* linux/drivers/media/video/samsung/jpeg/s3c-jpeg.h ++ * ++ * Driver header file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __JPEG_DRIVER_H__ ++#define __JPEG_DRIVER_H__ ++ ++#define MAX_INSTANCE_NUM 1 ++ ++#define IOCTL_JPG_DECODE 0x00000002 ++#define IOCTL_JPG_ENCODE 0x00000003 ++#define IOCTL_JPG_GET_STRBUF 0x00000004 ++#define IOCTL_JPG_GET_FRMBUF 0x00000005 ++#define IOCTL_JPG_GET_THUMB_STRBUF 0x0000000A ++#define IOCTL_JPG_GET_THUMB_FRMBUF 0x0000000B ++#define IOCTL_JPG_GET_PHY_FRMBUF 0x0000000C ++#define IOCTL_JPG_GET_PHY_THUMB_FRMBUF 0x0000000D ++ ++ ++#endif /*__JPEG_DRIVER_H__*/ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg_v2/Kconfig linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/Kconfig +--- linux-2.6.28/drivers/media/video/samsung/jpeg_v2/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/Kconfig 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,10 @@ ++# ++# Configuration for JPEG ++# ++ ++config VIDEO_JPEG_V2 ++ bool "Samsung JPEG driver" ++ depends on VIDEO_SAMSUNG && CPU_S5PC100 ++ default n ++ ---help--- ++ This is a JPEG for Samsung S5PC100 +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg_v2/Makefile linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/Makefile +--- linux-2.6.28/drivers/media/video/samsung/jpeg_v2/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/Makefile 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,10 @@ ++################################################# ++# Makefile for JPEG_V2 ++# 2009 (C) Samsung Electronics ++# Author : Jaeryul peter Oh ++################################################# ++ ++obj-$(CONFIG_VIDEO_JPEG_V2) += jpg_mem.o jpg_misc.o jpg_opr.o log_msg.o s3c-jpeg.o ++ ++EXTRA_CFLAGS += -Idrivers/media/video ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg_v2/jpg_conf.h linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/jpg_conf.h +--- linux-2.6.28/drivers/media/video/samsung/jpeg_v2/jpg_conf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/jpg_conf.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,259 @@ ++/* linux/drivers/media/video/samsung/jpeg_v2/jpg-conf.h ++ * ++ * Configuration file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __JPG_CONF_H__ ++#define __JPG_CONF_H__ ++ ++ ++const unsigned char qtbl_luminance[4][64] = { ++ // level 1 - high quality ++ { ++ 8, 6, 6, 8, 12, 14, 16, 17, ++ 6, 6, 6, 8, 10, 13, 12, 15, ++ 6, 6, 7, 8, 13, 14, 18, 24, ++ 8, 8, 8, 14, 13, 19, 24, 35, ++ 12, 10, 13, 13, 20, 26, 34, 39, ++ 14, 13, 14, 19, 26, 34, 39, 39, ++ 16, 12, 18, 24, 34, 39, 39, 39, ++ 17, 15, 24, 35, 39, 39, 39, 39 ++ }, ++ ++ // level 2 ++ { ++ 12, 8, 8, 12, 17, 21, 24, 23, ++ 8, 9, 9, 11, 15, 19, 18, 23, ++ 8, 9, 10, 12, 19, 20, 27, 36, ++ 12, 11, 12, 21, 20, 28, 36, 53, ++ 17, 15, 19, 20, 30, 39, 51, 59, ++ 21, 19, 20, 28, 39, 51, 59, 59, ++ 24, 18, 27, 36, 51, 59, 59, 59, ++ 23, 23, 36, 53, 59, 59, 59, 59 ++ }, ++ ++ // level 3 ++ { ++ 16, 11, 11, 16, 23, 27, 31, 30, ++ 11, 12, 12, 15, 20, 23, 23, 30, ++ 11, 12, 13, 16, 23, 26, 35, 47, ++ 16, 15, 16, 23, 26, 37, 47, 64, ++ 23, 20, 23, 26, 39, 51, 64, 64, ++ 27, 23, 26, 37, 51, 64, 64, 64, ++ 31, 23, 35, 47, 64, 64, 64, 64, ++ 30, 30, 47, 64, 64, 64, 64, 64 ++ ++ }, ++ ++ // level 4 - low quality ++ { ++ 20, 16, 25, 39, 50, 46, 62, 68, ++ 16, 18, 23, 38, 38, 53, 65, 68, ++ 25, 23, 31, 38, 53, 65, 68, 68, ++ 39, 38, 38, 53, 65, 68, 68, 68, ++ 50, 38, 53, 65, 68, 68, 68, 68, ++ 46, 53, 65, 68, 68, 68, 68, 68, ++ 62, 65, 68, 68, 68, 68, 68, 68, ++ 68, 68, 68, 68, 68, 68, 68, 68 ++ } ++ ++ ++}; ++ ++const unsigned char qtbl_chrominance[4][64] = { ++ // level 1 - high quality ++ { ++ 9, 8, 9, 11, 14, 17, 19, 24, ++ 8, 10, 9, 11, 14, 13, 17, 22, ++ 9, 9, 13, 14, 13, 15, 23, 26, ++ 11, 11, 14, 14, 15, 20, 26, 33, ++ 14, 14, 13, 15, 20, 24, 33, 39, ++ 17, 13, 15, 20, 24, 32, 39, 39, ++ 19, 17, 23, 26, 33, 39, 39, 39, ++ 24, 22, 26, 33, 39, 39, 39, 39 ++ }, ++ ++ // level 2 ++ { ++ 13, 11, 13, 16, 20, 20, 29, 37, ++ 11, 14, 14, 14, 16, 20, 26, 32, ++ 13, 14, 15, 17, 20, 23, 35, 40, ++ 16, 14, 17, 21, 23, 30, 40, 50, ++ 20, 16, 20, 23, 30, 37, 50, 59, ++ 20, 20, 23, 30, 37, 48, 59, 59, ++ 29, 26, 35, 40, 50, 59, 59, 59, ++ 37, 32, 40, 50, 59, 59, 59, 59 ++ }, ++ ++ ++ // level 3 ++ { ++ 17, 15, 17, 21, 20, 26, 38, 48, ++ 15, 19, 18, 17, 20, 26, 35, 43, ++ 17, 18, 20, 22, 26, 30, 46, 53, ++ 21, 17, 22, 28, 30, 39, 53, 64, ++ 20, 20, 26, 30, 39, 48, 64, 64, ++ 26, 26, 30, 39, 48, 63, 64, 64, ++ 38, 35, 46, 53, 64, 64, 64, 64, ++ 48, 43, 53, 64, 64, 64, 64, 64 ++ ++ ++ }, ++ ++ // level 4 - low quality ++ { ++ 21, 25, 32, 38, 54, 68, 68, 68, ++ 25, 28, 24, 38, 54, 68, 68, 68, ++ 32, 24, 32, 43, 66, 68, 68, 68, ++ 38, 38, 43, 53, 68, 68, 68, 68, ++ 54, 54, 66, 68, 68, 68, 68, 68, ++ 68, 68, 68, 68, 68, 68, 68, 68, ++ 68, 68, 68, 68, 68, 68, 68, 68, ++ 68, 68, 68, 68, 68, 68, 68, 68 ++ ++ } ++ ++}; ++ ++const unsigned char qtbl0[64] = { ++ 0x10, 0x0B, 0x0A, 0x10, 0x18, 0x28, 0x33, 0x3D, ++ 0x0C, 0x0C, 0x0E, 0x13, 0x1A, 0x3A, 0x3C, 0x37, ++ 0x0E, 0x0D, 0x10, 0x18, 0x28, 0x39, 0x45, 0x38, ++ 0x0E, 0x11, 0x16, 0x1D, 0x33, 0x57, 0x50, 0x3E, ++ 0x12, 0x16, 0x25, 0x38, 0x44, 0x6D, 0x67, 0x4D, ++ 0x18, 0x23, 0x37, 0x40, 0x51, 0x68, 0x71, 0x5C, ++ 0x31, 0x40, 0x4E, 0x57, 0x67, 0x79, 0x78, 0x65, ++ 0x48, 0x5C, 0x5F, 0x62, 0x70, 0x64, 0x67, 0x63 ++}; ++ ++//Added Quantization Table ++const unsigned char std_chrominance_quant_tbl_plus[64] = { ++ 0x11, 0x12, 0x18, 0x2F, 0x63, 0x63, 0x63, 0x63, ++ 0x12, 0x15, 0x1A, 0x42, 0x63, 0x63, 0x63, 0x63, ++ 0x18, 0x1A, 0x38, 0x63, 0x63, 0x63, 0x63, 0x63, ++ 0x2F, 0x42, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, ++ 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, ++ 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, ++ 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, ++ 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63 ++}; ++ ++//Quantization Table0 ++unsigned char std_luminance_quant_tbl[64] = { ++ 1, 1, 2, 1, 1, 2, 2, 2, ++ 2, 3, 2, 2, 3, 3, 6, 4, ++ 3, 3, 3, 3, 7, 5, 8, 4, ++ 6, 8, 8, 10, 9, 8, 7, 11, ++ 8, 10, 14, 13, 11, 10, 10, 12, ++ 10, 8, 8, 11, 16, 12, 12, 13, ++ 15, 15, 15, 15, 9, 11, 16, 17, ++ 15, 14, 17, 13, 14, 14, 14, 1 ++}; ++ ++//Quantization Table1 ++unsigned char std_chrominance_quant_tbl[64] = { ++ 4, 4, 4, 5, 4, 5, 9, 5, ++ 5, 9, 15, 10, 8, 10, 15, 26, ++ 19, 9, 9, 19, 26, 26, 26, 26, ++ 13, 26, 26, 26, 26, 26, 26, 26, ++ 26, 26, 26, 26, 26, 26, 26, 26, ++ 26, 26, 26, 26, 26, 26, 26, 26, ++ 26, 26, 26, 26, 26, 26, 26, 26, ++ 26, 26, 26, 26, 26, 26, 26, 26 ++}; ++ ++//Huffman Table ++unsigned char hdctbl0[16] = {0, 1, 5, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0}; ++unsigned char hdctblg0[12] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb}; ++ ++unsigned char hactbl0[16] = {0, 2, 1, 3, 3, 2, 4, 3, 5, 5, 4, 4, 0, 0, 1, 0x7d}; ++const unsigned char hactblg0[162] = { ++ 0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, ++ 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, ++ 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08, ++ 0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0, ++ 0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16, ++ 0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28, ++ 0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++ 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, ++ 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, ++ 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, ++ 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, ++ 0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, ++ 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, ++ 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, ++ 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, ++ 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5, ++ 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4, ++ 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2, ++ 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, ++ 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, ++ 0xf9, 0xfa ++}; ++ ++//Huffman Table0 ++unsigned char len_dc_luminance[16] = { 0, 1, 5, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 }; ++unsigned char val_dc_luminance[12] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 }; ++ ++unsigned char len_ac_luminance[16] = { 0, 2, 1, 3, 3, 2, 4, 3, 5, 5, 4, 4, 0, 0, 1, 0x7d }; ++unsigned char val_ac_luminance[162] = { ++ 0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, ++ 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, ++ 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08, ++ 0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0, ++ 0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16, ++ 0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28, ++ 0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++ 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, ++ 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, ++ 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, ++ 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, ++ 0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, ++ 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, ++ 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, ++ 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, ++ 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5, ++ 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4, ++ 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2, ++ 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, ++ 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, ++ 0xf9, 0xfa ++}; ++ ++//Huffman Table1 ++unsigned char len_dc_chrominance[16] = { 0, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 }; ++unsigned char val_dc_chrominance[12] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 }; ++ ++unsigned char len_ac_chrominance[16] = { 0, 2, 1, 2, 4, 4, 3, 4, 7, 5, 4, 4, 0, 1, 2, 0x77 }; ++unsigned char val_ac_chrominance[162] = { ++ 0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, ++ 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71, ++ 0x13, 0x22, 0x32, 0x81, 0x81, 0x08, 0x14, 0x42, ++ 0x91, 0xa1, 0xb1, 0xc1, 0x09, 0x23, 0x33, 0x52, ++ 0xf0, 0x15, 0x62, 0x72, 0xd1, 0x0a, 0x16, 0x24, ++ 0x34, 0xe1, 0x25, 0xf1, 0x17, 0x18, 0x19, 0x1a, ++ 0x26, 0x27, 0x28, 0x29, 0x2a, 0x35, 0x36, 0x37, ++ 0x38, 0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, ++ 0x48, 0x49, 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, ++ 0x58, 0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, ++ 0x68, 0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, ++ 0x78, 0x79, 0x7a, 0x82, 0x83, 0x84, 0x85, 0x86, ++ 0x87, 0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, ++ 0x96, 0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, ++ 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, ++ 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xc2, ++ 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, ++ 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, ++ 0xda, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, ++ 0xe9, 0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, ++ 0xf8, 0xf9 ++}; ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg_v2/jpg_mem.c linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/jpg_mem.c +--- linux-2.6.28/drivers/media/video/samsung/jpeg_v2/jpg_mem.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/jpg_mem.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,63 @@ ++/* linux/drivers/media/video/samsung/jpeg_v2/jpg_mem.c ++ * ++ * Driver file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "jpg_mem.h" ++#include "jpg_misc.h" ++#include "log_msg.h" ++ ++ ++/*---------------------------------------------------------------------------- ++*Function: phy_to_vir_addr ++ ++*Parameters: dwContext : ++*Return Value: True/False ++*Implementation Notes: memory mapping from physical addr to virtual addr ++-----------------------------------------------------------------------------*/ ++void *phy_to_vir_addr(UINT32 phy_addr, int mem_size) ++{ ++ void *reserved_mem; ++ ++ reserved_mem = (void *)ioremap((unsigned long)phy_addr, (int)mem_size); ++ ++ if (reserved_mem == NULL) { ++ log_msg(LOG_ERROR, "phy_to_vir_addr", "DD::Phyical to virtual memory mapping was failed!\r\n"); ++ return NULL; ++ } ++ ++ return reserved_mem; ++} ++ ++void *mem_move(void *dst, const void *src, unsigned int size) ++{ ++ return memmove(dst, src, size); ++} ++ ++void *mem_alloc(unsigned int size) ++{ ++ void *alloc_mem; ++ ++ alloc_mem = (void *)kmalloc((int)size, GFP_KERNEL); ++ ++ if (alloc_mem == NULL) { ++ log_msg(LOG_ERROR, "Mem_Alloc", "memory allocation failed!\r\n"); ++ return NULL; ++ } ++ ++ return alloc_mem; ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg_v2/jpg_mem.h linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/jpg_mem.h +--- linux-2.6.28/drivers/media/video/samsung/jpeg_v2/jpg_mem.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/jpg_mem.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,105 @@ ++/* linux/drivers/media/video/samsung/jpeg_v2/jpg_mem.h ++ * ++ * Driver header file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __JPG_MEM_H__ ++#define __JPG_MEM_H__ ++ ++#include "jpg_misc.h" ++ ++#include ++#include ++ ++#define JPG_REG_BASE_ADDR (0xEE500000) ++#define jpg_data_base_addr (UINT32)s3c_get_media_memory(S3C_MDEV_JPEG) ++ ++#define MAX_JPG_WIDTH 3072//3264 ++#define MAX_JPG_HEIGHT 2048//2448 ++ ++#define MAX_JPG_THUMBNAIL_WIDTH 320 ++#define MAX_JPG_THUMBNAIL_HEIGHT 240 ++ ++#define MAX_RGB_WIDTH 800 ++#define MAX_RGB_HEIGHT 480 ++ ++/*******************************************************************************/ ++// define JPG & image memory ++// memory area is 4k(PAGE_SIZE) aligned because of VirtualCopyEx() ++#define JPG_STREAM_BUF_SIZE ((MAX_JPG_WIDTH * MAX_JPG_HEIGHT )/PAGE_SIZE + 1)*PAGE_SIZE ++#define JPG_STREAM_THUMB_BUF_SIZE ((MAX_JPG_THUMBNAIL_WIDTH * MAX_JPG_THUMBNAIL_HEIGHT )/PAGE_SIZE + 1)*PAGE_SIZE ++#define JPG_FRAME_BUF_SIZE ((MAX_JPG_WIDTH * MAX_JPG_HEIGHT * 3)/PAGE_SIZE + 1)*PAGE_SIZE ++#define JPG_FRAME_THUMB_BUF_SIZE ((MAX_JPG_THUMBNAIL_WIDTH * MAX_JPG_THUMBNAIL_HEIGHT * 3)/PAGE_SIZE + 1)*PAGE_SIZE ++#define JPG_RGB_BUF_SIZE ((MAX_RGB_WIDTH * MAX_RGB_HEIGHT*4)/PAGE_SIZE + 1)*PAGE_SIZE ++ ++#define JPG_TOTAL_BUF_SIZE (JPG_STREAM_BUF_SIZE + JPG_STREAM_THUMB_BUF_SIZE \ ++ + JPG_FRAME_BUF_SIZE + JPG_FRAME_THUMB_BUF_SIZE + JPG_RGB_BUF_SIZE) ++ ++#define JPG_MAIN_STRART 0x00 ++#define JPG_THUMB_START JPG_STREAM_BUF_SIZE ++#define IMG_MAIN_START (JPG_STREAM_BUF_SIZE + JPG_STREAM_THUMB_BUF_SIZE) ++#define IMG_THUMB_START (JPG_STREAM_BUF_SIZE + JPG_STREAM_THUMB_BUF_SIZE + JPG_FRAME_BUF_SIZE) ++ ++/*******************************************************************************/ ++#define COEF1_RGB_2_YUV 0x4d971e ++#define COEF2_RGB_2_YUV 0x2c5783 ++#define COEF3_RGB_2_YUV 0x836e13 ++ ++/* ++ * JPEG HW Register Macro Definition ++ */ ++#define JPG_1BIT_MASK 1 ++#define JPG_4BIT_MASK 0xF ++ ++#define JPG_SMPL_MODE_MASK 0x07 // SubSampling_Mode Mask is JPGMOD Register [2:0] bits mask ++ ++#define JPG_RESTART_INTRAVEL 2 // Restart Interval value in JPGDRI Register is 2 ++ ++//#define JPG_JPEG_RATIO_BIT 24 // JPEG_RATIO is CLK_DIV0 Register 24th bit ++#define JPG_HCLK_JPEG_BIT 5 // HCLK_JPEG is CLK_GATE_D1_1 Register 5th bit ++#define JPG_SMPL_MODE_BIT 0 // SubSampling_Mode is JPGMOD Register 0th bit ++#define JPG_QUANT_TABLE1_BIT 8 // Quantization Table #1 is JPGQHNO Register 8th bit ++#define JPG_QUANT_TABLE2_BIT 10 // Quantization Table #2 is JPGQHNO Register 10th bit ++#define JPG_QUANT_TABLE3_BIT 12 // Quantization Table #3 is JPGQHNO Register 12th bit ++#define JPG_MODE_SEL_BIT 5 // Mode Sel is JPGCMOD Register 5th bit ++ ++#define JPG_DECODE (0x1 << 3) ++#define JPG_ENCODE (0x0 << 3) ++ ++#define JPG_RESERVE_ZERO (0b000 << 2) ++ ++#define ENABLE_MOTION_ENC (0x1<<3) ++#define DISABLE_MOTION_ENC (0x0<<3) ++ ++#define ENABLE_MOTION_DEC (0x1<<0) ++#define DISABLE_MOTION_DEC (0x0<<0) ++ ++#define ENABLE_HW_DEC (0x1<<2) ++#define DISABLE_HW_DEC (0x0<<2) ++ ++#define INCREMENTAL_DEC (0x1<<3) ++#define NORMAL_DEC (0x0<<3) ++#define YCBCR_MEMORY (0x1<<5) ++ ++#define ENABLE_IRQ (0xf<<3) ++ ++typedef struct __s5pc100_jpg_ctx { ++ volatile UINT32 jpg_data_addr; ++ volatile UINT32 img_data_addr; ++ volatile UINT32 jpg_thumb_data_addr; ++ volatile UINT32 img_thumb_data_addr; ++ int caller_process; ++} sspc100_jpg_ctx; ++ ++void *phy_to_vir_addr(UINT32 phy_addr, int mem_size); ++void *mem_move(void *dst, const void *src, unsigned int size); ++void *mem_alloc(unsigned int size); ++#endif ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg_v2/jpg_misc.c linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/jpg_misc.c +--- linux-2.6.28/drivers/media/video/samsung/jpeg_v2/jpg_misc.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/jpg_misc.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,96 @@ ++/* linux/drivers/media/video/samsung/jpeg_v2/jpg_misc.c ++ * ++ * Driver file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "jpg_misc.h" ++#include "jpg_mem.h" ++ ++static HANDLE h_mutex = NULL; ++ ++/*---------------------------------------------------------------------------- ++*Function: create_jpg_mutex ++*Implementation Notes: Create Mutex handle ++-----------------------------------------------------------------------------*/ ++HANDLE create_jpg_mutex(void) ++{ ++ h_mutex = (HANDLE)kmalloc(sizeof(struct mutex), GFP_KERNEL); ++ ++ if (h_mutex == NULL) ++ return NULL; ++ ++ mutex_init(h_mutex); ++ ++ return h_mutex; ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: lock_jpg_mutex ++*Implementation Notes: lock mutex ++-----------------------------------------------------------------------------*/ ++DWORD lock_jpg_mutex(void) ++{ ++ mutex_lock(h_mutex); ++ return 1; ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: unlock_jpg_mutex ++*Implementation Notes: unlock mutex ++-----------------------------------------------------------------------------*/ ++DWORD unlock_jpg_mutex(void) ++{ ++ mutex_unlock(h_mutex); ++ ++ return 1; ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: delete_jpg_mutex ++*Implementation Notes: delete mutex handle ++-----------------------------------------------------------------------------*/ ++void delete_jpg_mutex(void) ++{ ++ if (h_mutex == NULL) ++ return; ++ ++ mutex_destroy(h_mutex); ++} ++ ++unsigned int get_fb0_addr(void) ++{ ++ return readl(S3C_VIDW00ADD0B0); ++} ++ ++void get_lcd_size(int *width, int *height) ++{ ++ unsigned int tmp; ++ ++ tmp = readl(S3C_VIDTCON2); ++ *height = ((tmp >> 11) & 0x7FF) + 1; ++ *width = (tmp & 0x7FF) + 1; ++} ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg_v2/jpg_misc.h linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/jpg_misc.h +--- linux-2.6.28/drivers/media/video/samsung/jpeg_v2/jpg_misc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/jpg_misc.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,36 @@ ++/* linux/drivers/media/video/samsung/jpeg_v2/jpg_misc.h ++ * ++ * Driver header file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __JPG_MISC_H__ ++#define __JPG_MISC_H__ ++ ++#include ++ ++typedef unsigned char UCHAR; ++typedef unsigned long ULONG; ++typedef unsigned int UINT; ++typedef struct mutex * HANDLE; ++typedef unsigned long DWORD; ++typedef unsigned int UINT32; ++typedef unsigned char UINT8; ++typedef enum {FALSE, TRUE} BOOL; ++ ++#define INT_TIMEOUT 1000 ++ ++HANDLE create_jpg_mutex(void); ++DWORD lock_jpg_mutex(void); ++DWORD unlock_jpg_mutex(void); ++void delete_jpg_mutex(void); ++unsigned int get_fb0_addr(void); ++void get_lcd_size(int *width, int *height); ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg_v2/jpg_opr.c linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/jpg_opr.c +--- linux-2.6.28/drivers/media/video/samsung/jpeg_v2/jpg_opr.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/jpg_opr.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,346 @@ ++/* linux/drivers/media/video/samsung/jpeg_v2/jpg_opr.c ++ * ++ * Driver file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#include ++#include ++ ++#include "jpg_mem.h" ++#include "jpg_misc.h" ++#include "jpg_opr.h" ++#include "jpg_conf.h" ++#include "log_msg.h" ++ ++#include "regs-jpeg.h" ++ ++extern void __iomem *s3c_jpeg_base; ++extern int jpg_irq_reason; ++ ++enum { ++ UNKNOWN, ++ BASELINE = 0xC0, ++ EXTENDED_SEQ = 0xC1, ++ PROGRESSIVE = 0xC2 ++} jpg_sof_marker; ++ ++/*---------------------------------------------------------------------------- ++*Function: wait_for_interrupt ++ ++*Parameters: void ++*Return Value: ++*Implementation Notes: ++-----------------------------------------------------------------------------*/ ++jpg_return_status wait_for_interrupt(void) ++{ ++ if (interruptible_sleep_on_timeout(&wait_queue_jpeg, INT_TIMEOUT) == 0) { ++ log_msg(LOG_ERROR, "s3c_jpeg_ioctl", "Waiting for interrupt is timeout\n"); ++ } ++ ++ return jpg_irq_reason; ++} ++/*---------------------------------------------------------------------------- ++*Function: decode_jpg ++ ++*Parameters: jpg_ctx: ++ input_buff: ++ input_size: ++ output_buff: ++ output_size ++*Return Value: ++*Implementation Notes: ++-----------------------------------------------------------------------------*/ ++jpg_return_status decode_jpg(sspc100_jpg_ctx *jpg_ctx, ++ jpg_dec_proc_param *dec_param) ++{ ++ volatile int ret; ++ sample_mode_t sample_mode; ++ UINT32 width, height; ++ log_msg(LOG_TRACE, "decode_jpg", "decode_jpg function\n"); ++ ++ if (jpg_ctx) ++ reset_jpg(jpg_ctx); ++ else { ++ log_msg(LOG_ERROR, "\ndecode_jpg", "DD::JPG CTX is NULL\n"); ++ return JPG_FAIL; ++ } ++ ++ //////////////////////////////////////// ++ // Header Parsing // ++ //////////////////////////////////////// ++ ++ decode_header(jpg_ctx, dec_param); ++ ret = wait_for_interrupt(); ++ ++ if (ret != OK_HD_PARSING) { ++ log_msg(LOG_ERROR, "\ndecode_jpg", "DD::JPG Header Parsing Error(%d)\r\n", ret); ++ return JPG_FAIL; ++ } ++ ++ sample_mode = get_sample_type(jpg_ctx); ++ log_msg(LOG_TRACE, "decode_jpg", "sample_mode : %d\n", sample_mode); ++ ++ if (sample_mode == JPG_SAMPLE_UNKNOWN) { ++ log_msg(LOG_ERROR, "decode_jpg", "DD::JPG has invalid sample_mode\r\n"); ++ return JPG_FAIL; ++ } ++ ++ dec_param->sample_mode = sample_mode; ++ ++ get_xy(jpg_ctx, &width, &height); ++ log_msg(LOG_TRACE, "decode_jpg", "DD:: width : %d height : %d\n", width, height); ++ ++ if (width <= 0 || width > MAX_JPG_WIDTH || height <= 0 || height > MAX_JPG_HEIGHT) { ++ log_msg(LOG_ERROR, "decode_jpg", "DD::JPG has invalid width(%d)/height(%d)\n",width, height); ++ return JPG_FAIL; ++ } ++ ++ //////////////////////////////////////// ++ // Body Decoding // ++ //////////////////////////////////////// ++ ++ decode_body(jpg_ctx); ++ ++ ret = wait_for_interrupt(); ++ ++ if (ret != OK_ENC_OR_DEC) { ++ log_msg(LOG_ERROR, "decode_jpg", "DD::JPG Body Decoding Error(%d)\n", ret); ++ return JPG_FAIL; ++ } ++ ++ dec_param->data_size = get_yuv_size(dec_param->out_format, width, height); ++ dec_param->width = width; ++ dec_param->height = height; ++ ++ return JPG_SUCCESS; ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: reset_jpg ++ ++*Parameters: jpg_ctx: ++*Return Value: ++*Implementation Notes: ++-----------------------------------------------------------------------------*/ ++void reset_jpg(sspc100_jpg_ctx *jpg_ctx) ++{ ++ log_msg(LOG_TRACE, "reset_jpg", "s3c_jpeg_base 0x%08x \n", s3c_jpeg_base); ++ __raw_writel(S3C_JPEG_SW_RESET_REG_ENABLE, s3c_jpeg_base + S3C_JPEG_SW_RESET_REG); ++ ++ do { ++ __raw_writel(S3C_JPEG_SW_RESET_REG_ENABLE, s3c_jpeg_base + S3C_JPEG_SW_RESET_REG); ++ } while (((readl(s3c_jpeg_base + S3C_JPEG_SW_RESET_REG)) & S3C_JPEG_SW_RESET_REG_ENABLE) == S3C_JPEG_SW_RESET_REG_ENABLE); ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: decode_header ++ ++*Parameters: jpg_ctx: ++*Return Value: ++*Implementation Notes: ++-----------------------------------------------------------------------------*/ ++void decode_header(sspc100_jpg_ctx *jpg_ctx, jpg_dec_proc_param *dec_param) ++{ ++ log_msg(LOG_TRACE, "decode_header", "decode_header function\n"); ++ __raw_writel(jpg_ctx->jpg_data_addr, s3c_jpeg_base + S3C_JPEG_JPGADR_REG); ++ ++ __raw_writel(__raw_readl(s3c_jpeg_base + S3C_JPEG_MOD_REG) | (S3C_JPEG_MOD_REG_PROC_DEC), s3c_jpeg_base + S3C_JPEG_MOD_REG); //decoding mode ++ __raw_writel(__raw_readl(s3c_jpeg_base + S3C_JPEG_CMOD_REG) & (~S3C_JPEG_CMOD_REG_MOD_HALF_EN_HALF), s3c_jpeg_base + S3C_JPEG_CMOD_REG); ++ __raw_writel(__raw_readl(s3c_jpeg_base + S3C_JPEG_CLKCON_REG) | (S3C_JPEG_CLKCON_REG_POWER_ON_ACTIVATE), s3c_jpeg_base + S3C_JPEG_CLKCON_REG); ++ __raw_writel(__raw_readl(s3c_jpeg_base + S3C_JPEG_INTSE_REG) & ~(0x7f << 0), s3c_jpeg_base + S3C_JPEG_INTSE_REG); ++ __raw_writel(__raw_readl(s3c_jpeg_base + S3C_JPEG_INTSE_REG) | (S3C_JPEG_INTSE_REG_ERR_INT_EN | S3C_JPEG_INTSE_REG_HEAD_INT_EN_ENABLE | S3C_JPEG_INTSE_REG_INT_EN), s3c_jpeg_base + S3C_JPEG_INTSE_REG); ++ __raw_writel(__raw_readl(s3c_jpeg_base + S3C_JPEG_OUTFORM_REG) & ~(S3C_JPEG_OUTFORM_REG_YCBCY420), s3c_jpeg_base + S3C_JPEG_OUTFORM_REG); ++ __raw_writel(__raw_readl(s3c_jpeg_base + S3C_JPEG_OUTFORM_REG) | (dec_param->out_format << 0), s3c_jpeg_base + S3C_JPEG_OUTFORM_REG); ++ __raw_writel(__raw_readl(s3c_jpeg_base + S3C_JPEG_DEC_STREAM_SIZE_REG) & ~(S3C_JPEG_DEC_STREAM_SIZE_REG_PROHIBIT), s3c_jpeg_base + S3C_JPEG_DEC_STREAM_SIZE_REG); ++ //__raw_writel(dec_param->file_size, s3c_jpeg_base + S3C_JPEG_DEC_STREAM_SIZE_REG); ++ __raw_writel(__raw_readl(s3c_jpeg_base + S3C_JPEG_JSTART_REG) | S3C_JPEG_JSTART_REG_ENABLE, s3c_jpeg_base + S3C_JPEG_JSTART_REG); ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: decode_body ++ ++*Parameters: jpg_ctx: ++*Return Value: ++*Implementation Notes: ++-----------------------------------------------------------------------------*/ ++void decode_body(sspc100_jpg_ctx *jpg_ctx) ++{ ++ log_msg(LOG_TRACE, "decode_body", "decode_body function\n"); ++ __raw_writel(jpg_ctx->img_data_addr, s3c_jpeg_base + S3C_JPEG_IMGADR_REG); ++ __raw_writel(__raw_readl(s3c_jpeg_base + S3C_JPEG_JRSTART_REG) | S3C_JPEG_JRSTART_REG_ENABLE, s3c_jpeg_base + S3C_JPEG_JRSTART_REG); ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: get_sample_type ++ ++*Parameters: jpg_ctx: ++*Return Value: ++*Implementation Notes: ++-----------------------------------------------------------------------------*/ ++sample_mode_t get_sample_type(sspc100_jpg_ctx *jpg_ctx) ++{ ++ ULONG jpgMode; ++ sample_mode_t sample_mode = JPG_SAMPLE_UNKNOWN; ++ ++ jpgMode = __raw_readl(s3c_jpeg_base + S3C_JPEG_MOD_REG); ++ ++ sample_mode = ++ ((jpgMode & JPG_SMPL_MODE_MASK) == JPG_444) ? JPG_444 : ++ ((jpgMode & JPG_SMPL_MODE_MASK) == JPG_422) ? JPG_422 : ++ ((jpgMode & JPG_SMPL_MODE_MASK) == JPG_420) ? JPG_420 : ++ ((jpgMode & JPG_SMPL_MODE_MASK) == JPG_400) ? JPG_400 : ++ ((jpgMode & JPG_SMPL_MODE_MASK) == JPG_411) ? JPG_411 : JPG_SAMPLE_UNKNOWN; ++ ++ return(sample_mode); ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: get_xy ++ ++*Parameters: jpg_ctx: ++ x: ++ y: ++*Return Value: ++*Implementation Notes: ++-----------------------------------------------------------------------------*/ ++void get_xy(sspc100_jpg_ctx *jpg_ctx, UINT32 *x, UINT32 *y) ++{ ++ *x = __raw_readl(s3c_jpeg_base + S3C_JPEG_X_REG); ++ *y = __raw_readl(s3c_jpeg_base + S3C_JPEG_Y_REG); ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: get_yuv_size ++ ++*Parameters: sample_mode: ++ width: ++ height: ++*Return Value: ++*Implementation Notes: ++-----------------------------------------------------------------------------*/ ++UINT32 get_yuv_size(out_mode_t out_format, UINT32 width, UINT32 height) ++{ ++ switch (out_format) { ++ case YCBCR_422 : ++ ++ if (width % 16 != 0) ++ width += 16 - (width % 16); ++ ++ if (height % 8 != 0) ++ height += 8 - (height % 8); ++ ++ break; ++ ++ case YCBCR_420 : ++ ++ if (width % 16 != 0) ++ width += 16 - (width % 16); ++ ++ if (height % 16 != 0) ++ height += 16 - (height % 16); ++ ++ break; ++ ++ case YCBCR_SAMPLE_UNKNOWN: ++ break; ++ } ++ ++ log_msg(LOG_TRACE, "get_yuv_size", " width(%d) height(%d)\n", width, height); ++ ++ switch (out_format) { ++ case YCBCR_422 : ++ return(width*height*2); ++ case YCBCR_420 : ++ return((width*height) + (width*height >> 1)); ++ default : ++ return(0); ++ } ++} ++ ++/*---------------------------------------------------------------------------- ++*Function: reset_jpg ++ ++*Parameters: jpg_ctx: ++*Return Value: ++*Implementation Notes: ++-----------------------------------------------------------------------------*/ ++jpg_return_status encode_jpg(sspc100_jpg_ctx *jpg_ctx, ++ jpg_enc_proc_param *enc_param) ++{ ++ ++ UINT i, ret; ++ UINT32 cmd_val; ++ ++ if (enc_param->width <= 0 || enc_param->width > MAX_JPG_WIDTH ++ || enc_param->height <= 0 || enc_param->height > MAX_JPG_HEIGHT) { ++ log_msg(LOG_ERROR, "encode_jpg", "DD::Encoder : width: %d, height: %d \n", enc_param->width, enc_param->height); ++ log_msg(LOG_ERROR, "encode_jpg", "DD::Encoder : Invalid width/height \n"); ++ return JPG_FAIL; ++ } ++ ++ reset_jpg(jpg_ctx); ++ cmd_val = (enc_param->sample_mode == JPG_422) ? (S3C_JPEG_MOD_REG_SUBSAMPLE_422) : (S3C_JPEG_MOD_REG_SUBSAMPLE_420); ++ __raw_writel(cmd_val, s3c_jpeg_base + S3C_JPEG_MOD_REG); ++ __raw_writel(__raw_readl(s3c_jpeg_base + S3C_JPEG_CMOD_REG)& (~S3C_JPEG_CMOD_REG_MOD_HALF_EN_HALF), s3c_jpeg_base + S3C_JPEG_CMOD_REG); ++ __raw_writel(__raw_readl(s3c_jpeg_base + S3C_JPEG_CLKCON_REG) | (S3C_JPEG_CLKCON_REG_POWER_ON_ACTIVATE), s3c_jpeg_base + S3C_JPEG_CLKCON_REG); ++ __raw_writel(__raw_readl(s3c_jpeg_base + S3C_JPEG_CMOD_REG) | (enc_param->in_format << JPG_MODE_SEL_BIT), s3c_jpeg_base + S3C_JPEG_CMOD_REG); ++ __raw_writel(JPG_RESTART_INTRAVEL, s3c_jpeg_base + S3C_JPEG_DRI_REG); ++ __raw_writel(enc_param->width, s3c_jpeg_base + S3C_JPEG_X_REG); ++ __raw_writel(enc_param->height, s3c_jpeg_base + S3C_JPEG_Y_REG); ++ ++ log_msg(LOG_TRACE, "encode_jpg", "enc_param->enc_type : %d\n", enc_param->enc_type); ++ ++ if (enc_param->enc_type == JPG_MAIN) { ++ log_msg(LOG_TRACE, "encode_jpg", "encode image size width: %d, height: %d\n", enc_param->width, enc_param->height); ++ __raw_writel(jpg_ctx->img_data_addr, s3c_jpeg_base + S3C_JPEG_IMGADR_REG); ++ __raw_writel(jpg_ctx->jpg_data_addr, s3c_jpeg_base + S3C_JPEG_JPGADR_REG); ++ } else { // thumbnail encoding ++ log_msg(LOG_TRACE, "encode_jpg", "thumb image size width: %d, height: %d\n", enc_param->width, enc_param->height); ++ __raw_writel(jpg_ctx->img_thumb_data_addr, s3c_jpeg_base + S3C_JPEG_IMGADR_REG); ++ __raw_writel(jpg_ctx->jpg_thumb_data_addr, s3c_jpeg_base + S3C_JPEG_JPGADR_REG); ++ } ++ ++ __raw_writel(COEF1_RGB_2_YUV, s3c_jpeg_base + S3C_JPEG_COEF1_REG); // Coefficient value 1 for RGB to YCbCr ++ __raw_writel(COEF2_RGB_2_YUV, s3c_jpeg_base + S3C_JPEG_COEF2_REG); // Coefficient value 2 for RGB to YCbCr ++ __raw_writel(COEF3_RGB_2_YUV, s3c_jpeg_base + S3C_JPEG_COEF3_REG); // Coefficient value 3 for RGB to YCbCr ++ ++ // Quantiazation and Huffman Table setting ++ for (i = 0; i < 64; i++) ++ __raw_writel((UINT32)qtbl_luminance[enc_param->quality][i], s3c_jpeg_base + S3C_JPEG_QTBL0_REG + (i*0x04)); ++ ++ for (i = 0; i < 64; i++) ++ __raw_writel((UINT32)qtbl_chrominance[enc_param->quality][i], s3c_jpeg_base + S3C_JPEG_QTBL1_REG + (i*0x04)); ++ ++ for (i = 0; i < 16; i++) ++ __raw_writel((UINT32)hdctbl0[i], s3c_jpeg_base + S3C_JPEG_HDCTBL0_REG + (i*0x04)); ++ ++ for (i = 0; i < 12; i++) ++ __raw_writel((UINT32)hdctblg0[i], s3c_jpeg_base + S3C_JPEG_HDCTBLG0_REG + (i*0x04)); ++ ++ for (i = 0; i < 16; i++) ++ __raw_writel((UINT32)hactbl0[i], s3c_jpeg_base + S3C_JPEG_HACTBL0_REG + (i*0x04)); ++ ++ for (i = 0; i < 162; i++) ++ __raw_writel((UINT32)hactblg0[i], s3c_jpeg_base + S3C_JPEG_HACTBLG0_REG + (i*0x04)); ++ ++ __raw_writel(S3C_JPEG_QHTBL_REG_QT_NUM2 | S3C_JPEG_QHTBL_REG_QT_NUM3, s3c_jpeg_base + S3C_JPEG_QHTBL_REG); ++ ++ __raw_writel(__raw_readl(s3c_jpeg_base + S3C_JPEG_JSTART_REG) | S3C_JPEG_JSTART_REG_ENABLE, s3c_jpeg_base + S3C_JPEG_JSTART_REG); ++ ret = wait_for_interrupt(); ++ ++ if (ret != OK_ENC_OR_DEC) { ++ log_msg(LOG_ERROR, "encode_jpg", "DD::JPG Encoding Error(%d)\n", ret); ++ return JPG_FAIL; ++ } ++ ++ enc_param->file_size = __raw_readl(s3c_jpeg_base + S3C_JPEG_CNT_REG); ++ log_msg(LOG_TRACE, "encode_jpg", "encoded file size : %d\n", enc_param->file_size); ++ return JPG_SUCCESS; ++ ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg_v2/jpg_opr.h linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/jpg_opr.h +--- linux-2.6.28/drivers/media/video/samsung/jpeg_v2/jpg_opr.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/jpg_opr.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,122 @@ ++/* linux/drivers/media/video/samsung/jpeg_v2/jpg_opr.h ++ * ++ * Driver header file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __JPG_OPR_H__ ++#define __JPG_OPR_H__ ++ ++#include ++ ++extern wait_queue_head_t wait_queue_jpeg; ++ ++typedef enum { ++ JPG_FAIL, ++ JPG_SUCCESS, ++ OK_HD_PARSING, ++ ERR_HD_PARSING, ++ OK_ENC_OR_DEC, ++ ERR_ENC_OR_DEC, ++ ERR_UNKNOWN ++} jpg_return_status; ++ ++typedef enum { ++ JPG_RGB16, ++ JPG_YCBYCR, ++ JPG_TYPE_UNKNOWN ++} image_type_t; ++ ++typedef enum { ++ JPG_444, ++ JPG_422, ++ JPG_420, ++ JPG_400, ++ RESERVED1, ++ RESERVED2, ++ JPG_411, ++ JPG_SAMPLE_UNKNOWN ++} sample_mode_t; ++ ++typedef enum { ++ YCBCR_422, ++ YCBCR_420, ++ YCBCR_SAMPLE_UNKNOWN ++} out_mode_t; ++ ++typedef enum { ++ JPG_MODESEL_YCBCR = 1, ++ JPG_MODESEL_RGB, ++ JPG_MODESEL_UNKNOWN ++} in_mode_t; ++ ++typedef enum { ++ JPG_MAIN, ++ JPG_THUMBNAIL ++} encode_type_t; ++ ++typedef enum { ++ JPG_QUALITY_LEVEL_1 = 0, /*high quality*/ ++ JPG_QUALITY_LEVEL_2, ++ JPG_QUALITY_LEVEL_3, ++ JPG_QUALITY_LEVEL_4 /*low quality*/ ++} image_quality_type_t; ++ ++typedef struct { ++ sample_mode_t sample_mode; ++ encode_type_t dec_type; ++ out_mode_t out_format; ++ UINT32 width; ++ UINT32 height; ++ UINT32 data_size; ++ UINT32 file_size; ++} jpg_dec_proc_param; ++ ++typedef struct { ++ sample_mode_t sample_mode; ++ encode_type_t enc_type; ++ in_mode_t in_format; ++ image_quality_type_t quality; ++ UINT32 width; ++ UINT32 height; ++ UINT32 data_size; ++ UINT32 file_size; ++} jpg_enc_proc_param; ++ ++typedef struct { ++ char *in_buf; ++ char *phy_in_buf; ++ int in_buf_size; ++ char *out_buf; ++ char *phy_out_buf; ++ int out_buf_size; ++ char *in_thumb_buf; ++ char *phy_in_thumb_buf; ++ int in_thumb_buf_size; ++ char *out_thumb_buf; ++ char *phy_out_thumb_buf; ++ int out_thumb_buf_size; ++ char *mapped_addr; ++ jpg_dec_proc_param *dec_param; ++ jpg_enc_proc_param *enc_param; ++ jpg_enc_proc_param *thumb_enc_param; ++} jpg_args; ++ ++ ++jpg_return_status decode_jpg(sspc100_jpg_ctx *jpg_ctx, jpg_dec_proc_param *dec_param); ++void reset_jpg(sspc100_jpg_ctx *jpg_ctx); ++void decode_header(sspc100_jpg_ctx *jpg_ctx, jpg_dec_proc_param *dec_param); ++void decode_body(sspc100_jpg_ctx *jpg_ctx); ++sample_mode_t get_sample_type(sspc100_jpg_ctx *jpg_ctx); ++void get_xy(sspc100_jpg_ctx *jpg_ctx, UINT32 *x, UINT32 *y); ++UINT32 get_yuv_size(out_mode_t out_format, UINT32 width, UINT32 height); ++jpg_return_status encode_jpg(sspc100_jpg_ctx *jpg_ctx, jpg_enc_proc_param *enc_param); ++jpg_return_status wait_for_interrupt(void); ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg_v2/log_msg.c linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/log_msg.c +--- linux-2.6.28/drivers/media/video/samsung/jpeg_v2/log_msg.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/log_msg.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,53 @@ ++/* linux/drivers/media/video/samsung/jpeg_v2/jpg_msg.c ++ * ++ * Driver file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "log_msg.h" ++ ++//#define DEBUG 1 ++ ++static const log_level g_log_level = LOG_TRACE; ++ ++static const char *module_name = "JPEG_DRV"; ++ ++static const char *level_str[] = {"TRACE", "WARNING", "ERROR"}; ++ ++void log_msg(log_level level, const char *func_name, const char *msg, ...) ++{ ++ ++ char buf[256]; ++ va_list argptr; ++ ++ if (level < g_log_level) ++ return; ++ ++ sprintf(buf, "[%s: %s] %s: ", module_name, level_str[level], func_name); ++ ++ va_start(argptr, msg); ++ vsprintf(buf + strlen(buf), msg, argptr); ++ ++ if (level == LOG_TRACE) { ++#ifdef DEBUG ++ printk(buf); ++#endif ++ } else { ++ printk(buf); ++ } ++ ++ va_end(argptr); ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg_v2/log_msg.h linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/log_msg.h +--- linux-2.6.28/drivers/media/video/samsung/jpeg_v2/log_msg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/log_msg.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,35 @@ ++/* linux/drivers/media/video/samsung/jpeg_v2/jpg_msg.h ++ * ++ * Driver header file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __SAMSUNG_SYSLSI_APDEV_log_msg_H__ ++#define __SAMSUNG_SYSLSI_APDEV_log_msg_H__ ++ ++ ++typedef enum { ++ LOG_TRACE = 0, ++ LOG_WARNING = 1, ++ LOG_ERROR = 2 ++} log_level; ++ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++ ++ void log_msg(log_level level, const char *func_name, const char *msg, ...); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* __SAMSUNG_SYSLSI_APDEV_log_msg_H__ */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg_v2/regs-jpeg.h linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/regs-jpeg.h +--- linux-2.6.28/drivers/media/video/samsung/jpeg_v2/regs-jpeg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/regs-jpeg.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,136 @@ ++/* linux/drivers/media/video/samsung/jpeg/regs-jpeg.h ++ * ++ * Register definition file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef __ASM_ARM_REGS_S3C_JPEG_H ++#define __ASM_ARM_REGS_S3C_JPEG_H ++ ++/************************************************************************/ ++/*JPEG Registers part */ ++/************************************************************************/ ++#define S3C_JPEG_REG(x) ((x)) ++ ++/* JPEG Codec Control Registers */ ++ ++#define S3C_JPEG_MOD_REG S3C_JPEG_REG(0x00) // Sub-sampling Mode Register ++#define S3C_JPEG_OPR_REG S3C_JPEG_REG(0x04) // Operation Status Register ++#define S3C_JPEG_QHTBL_REG S3C_JPEG_REG(0x08) // Quantization Table Number Register and Huffman Table Number Register ++#define S3C_JPEG_DRI_REG S3C_JPEG_REG(0x0c) // MCU which inserts RST marker ++#define S3C_JPEG_Y_REG S3C_JPEG_REG(0x10) // Vertical resolution ++#define S3C_JPEG_X_REG S3C_JPEG_REG(0x14) // Horizontal resolution ++#define S3C_JPEG_CNT_REG S3C_JPEG_REG(0x18) // The amount of the compressed data in bytes ++#define S3C_JPEG_INTSE_REG S3C_JPEG_REG(0x1c) // Interrupt setting register ++#define S3C_JPEG_INTST_REG S3C_JPEG_REG(0x20) // Interrupt status ++ ++#define S3C_JPEG_IMGADR_REG S3C_JPEG_REG(0x50) // Source or destination image addresss ++ ++#define S3C_JPEG_JPGADR_REG S3C_JPEG_REG(0x58) // Source or destination JPEG file address ++#define S3C_JPEG_COEF1_REG S3C_JPEG_REG(0x5c) // Coefficient values for RGB <-> YCbCr converter ++#define S3C_JPEG_COEF2_REG S3C_JPEG_REG(0x60) // Coefficient values for RGB <-> YCbCr converter ++#define S3C_JPEG_COEF3_REG S3C_JPEG_REG(0x64) // Coefficient values for RGB <-> YCbCr converter ++ ++#define S3C_JPEG_CMOD_REG S3C_JPEG_REG(0x68) // Mode selection and core clock setting ++#define S3C_JPEG_CLKCON_REG S3C_JPEG_REG(0x6c) // Power on/off and clock down control ++ ++#define S3C_JPEG_JSTART_REG S3C_JPEG_REG(0x70) // Start compression or decompression ++#define S3C_JPEG_JRSTART_REG S3C_JPEG_REG(0x74) // Restart decompression after header analysis ++#define S3C_JPEG_SW_RESET_REG S3C_JPEG_REG(0x78) // S/W reset ++ ++#define S3C_JPEG_TIMER_SE_REG S3C_JPEG_REG(0x7c) // Internal timer setting register ++#define S3C_JPEG_TIMER_ST_REG S3C_JPEG_REG(0x80) // Internal timer status register ++#define S3C_JPEG_COMSTAT_REG S3C_JPEG_REG(0x84) // Command status register ++#define S3C_JPEG_OUTFORM_REG S3C_JPEG_REG(0x88) // Output color format of decompression ++#define S3C_JPEG_VERSION_REG S3C_JPEG_REG(0x8c) // Version register ++ ++#define S3C_JPEG_DEC_STREAM_SIZE_REG S3C_JPEG_REG(0x94) // Input jpeg stream byte size for decompression ++#define S3C_JPEG_ENC_STREAM_INTSE_REG S3C_JPEG_REG(0x98) // Compressed stream size interrupt setting register ++#define S3C_JPEG_ENC_STREAM_INTST_REG S3C_JPEG_REG(0x9c) // Compressed stream size interrupt status register ++ ++#define S3C_JPEG_QTBL0_REG S3C_JPEG_REG(0x400) // Quantization table 0 ++#define S3C_JPEG_QTBL1_REG S3C_JPEG_REG(0x500) // Quantization table 1 ++#define S3C_JPEG_QTBL2_REG S3C_JPEG_REG(0x600) // Quantization table 2 ++#define S3C_JPEG_QTBL3_REG S3C_JPEG_REG(0x700) // Quantization table 3 ++#define S3C_JPEG_HDCTBL0_REG S3C_JPEG_REG(0x800) // DC huffman table 0 ++#define S3C_JPEG_HDCTBLG0_REG S3C_JPEG_REG(0x840) // DC huffman table group 0 ++#define S3C_JPEG_HACTBL0_REG S3C_JPEG_REG(0x880) // AC huffman table 0 ++#define S3C_JPEG_HACTBLG0_REG S3C_JPEG_REG(0x8c0) // AC huffman table group 0 ++#define S3C_JPEG_HDCTBL1_REG S3C_JPEG_REG(0xc00) // DC huffman table 1 ++#define S3C_JPEG_HDCTBLG1_REG S3C_JPEG_REG(0xc40) // DC huffman table group 1 ++#define S3C_JPEG_HACTBL1_REG S3C_JPEG_REG(0xc80) // AC huffman table 1 ++#define S3C_JPEG_HACTBLG1_REG S3C_JPEG_REG(0xcc0) // AC huffman table group 1 ++ ++/************************************************************************/ ++/* Bit definition part */ ++/************************************************************************/ ++ ++/* JPEG Mode Register bit */ ++#define S3C_JPEG_MOD_REG_PROC_ENC (0<<3) ++#define S3C_JPEG_MOD_REG_PROC_DEC (1<<3) ++ ++#define S3C_JPEG_MOD_REG_SUBSAMPLE_444 (0<<0) ++#define S3C_JPEG_MOD_REG_SUBSAMPLE_422 (1<<0) ++#define S3C_JPEG_MOD_REG_SUBSAMPLE_420 (2<<0) ++#define S3C_JPEG_MOD_REG_SUBSAMPLE_GRAY (3<<0) ++ ++/* JPEG Operation Status Register bit */ ++#define S3C_JPEG_OPR_REG_OPERATE (1<<0) ++#define S3C_JPEG_OPR_REG_NO_OPERATE (0<<0) ++ ++/* Quantization Table And Huffman Table Number Register bit */ ++#define S3C_JPEG_QHTBL_REG_QT_NUM3 (1<<12) ++#define S3C_JPEG_QHTBL_REG_QT_NUM2 (1<<10) ++#define S3C_JPEG_QHTBL_REG_QT_NUM1 (1<<8) ++ ++#define S3C_JPEG_QHTBL_REG_HT_NUM3_AC (1<<5) ++#define S3C_JPEG_QHTBL_REG_HT_NUM3_DC (1<<4) ++#define S3C_JPEG_QHTBL_REG_HT_NUM2_AC (1<<3) ++#define S3C_JPEG_QHTBL_REG_HT_NUM2_DC (1<<2) ++#define S3C_JPEG_QHTBL_REG_HT_NUM1_AC (1<<1) ++#define S3C_JPEG_QHTBL_REG_HT_NUM1_DC (1<<0) ++ ++ ++/* JPEG Color Mode Register bit */ ++#define S3C_JPEG_CMOD_REG_MOD_SEL_RGB (2<<5) ++#define S3C_JPEG_CMOD_REG_MOD_SEL_YCBCR422 (1<<5) ++#define S3C_JPEG_CMOD_REG_MOD_MODE_Y16 (1<<1) ++#define S3C_JPEG_CMOD_REG_MOD_MODE_0 (0<<1) ++#define S3C_JPEG_CMOD_REG_MOD_HALF_EN_HALF (1<<0) ++#define S3C_JPEG_CMOD_REG_MOD_FULL_EN_FULL (0<<0) ++ ++/* JPEG Clock Control Register bit */ ++#define S3C_JPEG_CLKCON_REG_CLK_DOWN_READY_ENABLE (0<<1) ++#define S3C_JPEG_CLKCON_REG_CLK_DOWN_READY_DISABLE (1<<1) ++#define S3C_JPEG_CLKCON_REG_POWER_ON_ACTIVATE (1<<0) ++#define S3C_JPEG_CLKCON_REG_POWER_ON_DISABLE (0<<0) ++ ++/* JPEG Start Register bit */ ++#define S3C_JPEG_JSTART_REG_ENABLE (1<<0) ++ ++/* JPEG Rdstart Register bit */ ++#define S3C_JPEG_JRSTART_REG_ENABLE (1<<0) ++ ++/* JPEG SW Reset Register bit */ ++#define S3C_JPEG_SW_RESET_REG_ENABLE (1<<0) ++ ++/* JPEG Interrupt Setting Register bit */ ++#define S3C_JPEG_INTSE_REG_ERR_INT_EN (7<<4) ++#define S3C_JPEG_INTSE_REG_HEAD_INT_EN_ENABLE (1<<3) ++#define S3C_JPEG_INTSE_REG_HEAD_INT_EN_DISABLE (0<<3) ++#define S3C_JPEG_INTSE_REG_INT_EN (0<<0) ++ ++/* JPEG Decompression Output Format Register bit */ ++#define S3C_JPEG_OUTFORM_REG_YCBCY422 (0<<0) ++#define S3C_JPEG_OUTFORM_REG_YCBCY420 (1<<0) ++ ++/* JPEG Decompression Input Stream Size Register bit */ ++#define S3C_JPEG_DEC_STREAM_SIZE_REG_PROHIBIT (0x1FFFFFFF<<0) ++ ++#endif //__ASM_ARM_REGS_S3C_JPEG_H +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg_v2/s3c-jpeg.c linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/s3c-jpeg.c +--- linux-2.6.28/drivers/media/video/samsung/jpeg_v2/s3c-jpeg.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/s3c-jpeg.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,518 @@ ++/* linux/drivers/media/video/samsung/jpeg_v2/s3c-jpeg.c ++ * ++ * Driver file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++ ++#include ++#include ++ ++#include "s3c-jpeg.h" ++#include "jpg_mem.h" ++#include "jpg_misc.h" ++#include "jpg_opr.h" ++#include "log_msg.h" ++#include "regs-jpeg.h" ++ ++ ++static struct clk *jpeg_hclk; ++static struct clk *jpeg_sclk; ++static struct clk *post; ++static struct clk *s3c_jpeg_clk; ++ ++static struct resource *s3c_jpeg_mem; ++void __iomem *s3c_jpeg_base; ++static int irq_no; ++static int instanceNo = 0; ++volatile int jpg_irq_reason; ++wait_queue_head_t wait_queue_jpeg; ++ ++DECLARE_WAIT_QUEUE_HEAD(WaitQueue_JPEG); ++ ++irqreturn_t s3c_jpeg_irq(int irq, void *dev_id, struct pt_regs *regs) ++{ ++ unsigned int int_status; ++ unsigned int status; ++ ++ log_msg(LOG_TRACE, "s3c_jpeg_irq", "=====enter s3c_jpeg_irq===== \r\n"); ++ ++ int_status = __raw_readl(s3c_jpeg_base + S3C_JPEG_INTST_REG); ++ status = __raw_readl(s3c_jpeg_base + S3C_JPEG_OPR_REG); ++ log_msg(LOG_TRACE, "s3c_jpeg_irq", "int_status : 0x%08x status : 0x%08x\n", int_status, status); ++ ++ if (int_status) { ++ int_status &= ((1 << 6) | (1 << 4) | (1 << 3)); ++ ++ switch (int_status) { ++ case 0x08 : ++ jpg_irq_reason = OK_HD_PARSING; ++ break; ++ case 0x00 : ++ jpg_irq_reason = ERR_HD_PARSING; ++ break; ++ case 0x40 : ++ jpg_irq_reason = OK_ENC_OR_DEC; ++ break; ++ case 0x10 : ++ jpg_irq_reason = ERR_ENC_OR_DEC; ++ break; ++ default : ++ jpg_irq_reason = ERR_UNKNOWN; ++ } ++ ++ wake_up_interruptible(&wait_queue_jpeg); ++ } else { ++ jpg_irq_reason = ERR_UNKNOWN; ++ wake_up_interruptible(&wait_queue_jpeg); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int s3c_jpeg_open(struct inode *inode, struct file *file) ++{ ++ sspc100_jpg_ctx *jpg_reg_ctx; ++ DWORD ret; ++ ++ clk_enable(jpeg_hclk); ++ clk_enable(jpeg_sclk); ++ ++ log_msg(LOG_TRACE, "s3c_jpeg_open", "JPG_open \r\n"); ++ ++ jpg_reg_ctx = (sspc100_jpg_ctx *)mem_alloc(sizeof(sspc100_jpg_ctx)); ++ memset(jpg_reg_ctx, 0x00, sizeof(sspc100_jpg_ctx)); ++ ++ ret = lock_jpg_mutex(); ++ ++ if (!ret) { ++ log_msg(LOG_ERROR, "s3c_jpeg_open", "DD::JPG Mutex Lock Fail\r\n"); ++ unlock_jpg_mutex(); ++ return FALSE; ++ } ++ ++ if (instanceNo > MAX_INSTANCE_NUM) { ++ log_msg(LOG_ERROR, "s3c_jpeg_open", "DD::Instance Number error-JPEG is running, instance number is %d\n", instanceNo); ++ unlock_jpg_mutex(); ++ return FALSE; ++ } ++ ++ instanceNo++; ++ ++ unlock_jpg_mutex(); ++ ++ file->private_data = (sspc100_jpg_ctx *)jpg_reg_ctx; ++ ++ return 0; ++} ++ ++ ++static int s3c_jpeg_release(struct inode *inode, struct file *file) ++{ ++ DWORD ret; ++ sspc100_jpg_ctx *jpg_reg_ctx; ++ ++ log_msg(LOG_TRACE, "s3c_jpeg_release", "JPG_Close\n"); ++ ++ jpg_reg_ctx = (sspc100_jpg_ctx *)file->private_data; ++ ++ if (!jpg_reg_ctx) { ++ log_msg(LOG_ERROR, "s3c_jpeg_release", "DD::JPG Invalid Input Handle\r\n"); ++ return FALSE; ++ } ++ ++ ret = lock_jpg_mutex(); ++ ++ if (!ret) { ++ log_msg(LOG_ERROR, "s3c_jpeg_release", "DD::JPG Mutex Lock Fail\r\n"); ++ return FALSE; ++ } ++ ++ if ((--instanceNo) < 0) ++ instanceNo = 0; ++ ++ unlock_jpg_mutex(); ++ ++ clk_disable(jpeg_hclk); ++ clk_disable(jpeg_sclk); ++ log_msg(LOG_TRACE, "s3c_jpeg_release end ", "JPG_Close\n"); ++ return 0; ++} ++ ++ ++static ssize_t s3c_jpeg_write(struct file *file, const char *buf, size_t count, loff_t *pos) ++{ ++ return 0; ++} ++ ++static ssize_t s3c_jpeg_read(struct file *file, char *buf, size_t count, loff_t *pos) ++{ ++ return 0; ++} ++ ++static int s3c_jpeg_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ static sspc100_jpg_ctx *jpg_reg_ctx; ++ jpg_args param; ++ BOOL result = TRUE; ++ DWORD ret; ++ int out; ++ ++ ++ jpg_reg_ctx = (sspc100_jpg_ctx *)file->private_data; ++ ++ if (!jpg_reg_ctx) { ++ log_msg(LOG_ERROR, "s3c_jpeg_ioctl", "DD::JPG Invalid Input Handle\r\n"); ++ return FALSE; ++ } ++ ++ ret = lock_jpg_mutex(); ++ ++ if (!ret) { ++ log_msg(LOG_ERROR, "s3c_jpeg_ioctl", "DD::JPG Mutex Lock Fail\r\n"); ++ return FALSE; ++ } ++ ++ switch (cmd) { ++ case IOCTL_JPG_DECODE: ++ ++ log_msg(LOG_TRACE, "s3c_jpeg_ioctl", "IOCTL_JPEG_DECODE\n"); ++ ++ out = copy_from_user(¶m, (jpg_args *)arg, sizeof(jpg_args)); ++ ++ jpg_reg_ctx->jpg_data_addr = (UINT32)jpg_data_base_addr; ++ jpg_reg_ctx->img_data_addr = (UINT32)jpg_data_base_addr + JPG_STREAM_BUF_SIZE + JPG_STREAM_THUMB_BUF_SIZE; ++ ++ result = decode_jpg(jpg_reg_ctx, param.dec_param); ++ out = copy_to_user((void *)arg, (void *) & param, sizeof(jpg_args)); ++ break; ++ ++ case IOCTL_JPG_ENCODE: ++ ++ log_msg(LOG_TRACE, "s3c_jpeg_ioctl", "IOCTL_JPEG_ENCODE\n"); ++ ++ out = copy_from_user(¶m, (jpg_args *)arg, sizeof(jpg_args)); ++ ++ log_msg(LOG_TRACE, "s3c_jpeg_ioctl", "width : %d hegiht : %d\n", ++ param.enc_param->width, param.enc_param->height); ++ ++ if (param.enc_param->enc_type == JPG_MAIN) { ++ jpg_reg_ctx->jpg_data_addr = (UINT32)jpg_data_base_addr ; ++ jpg_reg_ctx->img_data_addr = (UINT32)jpg_data_base_addr + JPG_STREAM_BUF_SIZE + JPG_STREAM_THUMB_BUF_SIZE; ++ log_msg(LOG_TRACE, "s3c_jpeg_ioctl", "enc_img_data_addr=0x%08x, enc_jpg_data_addr=0x%08x\n", jpg_reg_ctx->img_data_addr,jpg_reg_ctx->jpg_data_addr); ++ ++ result = encode_jpg(jpg_reg_ctx, param.enc_param); ++ } else { ++ jpg_reg_ctx->img_thumb_data_addr = (UINT32)jpg_data_base_addr + JPG_STREAM_BUF_SIZE + JPG_STREAM_THUMB_BUF_SIZE + JPG_FRAME_BUF_SIZE; ++ jpg_reg_ctx->jpg_thumb_data_addr = (UINT32)jpg_data_base_addr + JPG_STREAM_BUF_SIZE; ++ ++ result = encode_jpg(jpg_reg_ctx, param.thumb_enc_param); ++ } ++ out = copy_to_user((void *)arg, (void *) & param, sizeof(jpg_args)); ++ break; ++ ++ case IOCTL_JPG_GET_STRBUF: ++ log_msg(LOG_TRACE, "s3c_jpeg_ioctl", "IOCTL_JPG_GET_STRBUF\n"); ++ unlock_jpg_mutex(); ++ return arg + JPG_MAIN_STRART; ++ ++ case IOCTL_JPG_GET_THUMB_STRBUF: ++ log_msg(LOG_TRACE, "s3c_jpeg_ioctl", "IOCTL_JPG_GET_THUMB_STRBUF\n"); ++ unlock_jpg_mutex(); ++ return arg + JPG_THUMB_START; ++ ++ case IOCTL_JPG_GET_FRMBUF: ++ log_msg(LOG_TRACE, "s3c_jpeg_ioctl", "IOCTL_JPG_GET_FRMBUF\n"); ++ unlock_jpg_mutex(); ++ return arg + IMG_MAIN_START; ++ ++ case IOCTL_JPG_GET_THUMB_FRMBUF: ++ log_msg(LOG_TRACE, "s3c_jpeg_ioctl", "IOCTL_JPG_GET_THUMB_FRMBUF\n"); ++ unlock_jpg_mutex(); ++ return arg + IMG_THUMB_START; ++ ++ case IOCTL_JPG_GET_PHY_FRMBUF: ++ log_msg(LOG_TRACE, "s3c_jpeg_ioctl", "IOCTL_JPG_GET_PHY_FRMBUF\n"); ++ unlock_jpg_mutex(); ++ return jpg_data_base_addr + JPG_STREAM_BUF_SIZE + JPG_STREAM_THUMB_BUF_SIZE; ++ ++ case IOCTL_JPG_GET_PHY_THUMB_FRMBUF: ++ log_msg(LOG_TRACE, "s3c_jpeg_ioctl", "IOCTL_JPG_GET_PHY_THUMB_FRMBUF\n"); ++ unlock_jpg_mutex(); ++ return jpg_data_base_addr + JPG_STREAM_BUF_SIZE + JPG_STREAM_THUMB_BUF_SIZE + JPG_FRAME_BUF_SIZE; ++ ++ default : ++ log_msg(LOG_ERROR, "s3c_jpeg_ioctl", "DD::JPG Invalid ioctl : 0x%X\n", cmd); ++ } ++ ++ unlock_jpg_mutex(); ++ ++ return result; ++} ++ ++static unsigned int s3c_jpeg_poll(struct file *file, poll_table *wait) ++{ ++ unsigned int mask = 0; ++ ++ log_msg(LOG_TRACE, "s3c_jpeg_poll", "enter poll \n"); ++ poll_wait(file, &wait_queue_jpeg, wait); ++ mask = POLLOUT | POLLWRNORM; ++ return mask; ++} ++int s3c_jpeg_mmap(struct file *filp, struct vm_area_struct *vma) ++{ ++ unsigned long size = vma->vm_end - vma->vm_start; ++ unsigned long max_size; ++ unsigned long page_frame_no; ++ ++ page_frame_no = __phys_to_pfn(jpg_data_base_addr); ++ ++ max_size = JPG_TOTAL_BUF_SIZE + PAGE_SIZE - (JPG_TOTAL_BUF_SIZE % PAGE_SIZE); ++ ++ if (size > max_size) { ++ return -EINVAL; ++ } ++ ++ vma->vm_flags |= VM_RESERVED | VM_IO; ++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ ++ if (remap_pfn_range(vma, vma->vm_start, page_frame_no, size, \ ++ vma->vm_page_prot)) { ++ log_msg(LOG_ERROR, "s3c_jpeg_mmap", "jpeg remap error"); ++ return -EAGAIN; ++ } ++ ++ return 0; ++} ++ ++ ++static struct file_operations jpeg_fops = { ++ owner: THIS_MODULE, ++ open: s3c_jpeg_open, ++ release: s3c_jpeg_release, ++ ioctl: s3c_jpeg_ioctl, ++ read: s3c_jpeg_read, ++ write: s3c_jpeg_write, ++ mmap: s3c_jpeg_mmap, ++ poll: s3c_jpeg_poll, ++}; ++ ++ ++static struct miscdevice s3c_jpeg_miscdev = { ++ minor: 254, ++ name: "s3c-jpg", ++ fops: &jpeg_fops ++}; ++ ++ ++static int s3c_jpeg_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ static int size; ++ static int ret; ++ HANDLE h_mutex; ++ ++ // JPEG clock enable ++ jpeg_hclk = clk_get(NULL, "hclk_jpeg"); ++ ++ if (!jpeg_hclk) { ++ printk(KERN_ERR "failed to get jpeg hclk source\n"); ++ return -ENOENT; ++ } ++ ++ clk_enable(jpeg_hclk); ++ ++ jpeg_sclk = clk_get(NULL, "sclk_jpeg"); ++ ++ if (!jpeg_sclk) { ++ printk(KERN_ERR "failed to get jpeg scllk source\n"); ++ return -ENOENT; ++ } ++ ++ clk_enable(jpeg_sclk); ++ ++ post = clk_get(NULL, "post"); ++ ++ if (!post) { ++ printk(KERN_ERR "failed to get post clock source\n"); ++ return -ENOENT; ++ } ++ ++ clk_enable(post); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ++ if (res == NULL) { ++ printk(KERN_INFO "failed to get memory region resouce\n"); ++ return -ENOENT; ++ } ++ ++ size = (res->end - res->start) + 1; ++ s3c_jpeg_mem = request_mem_region(res->start, size, pdev->name); ++ ++ if (s3c_jpeg_mem == NULL) { ++ printk(KERN_INFO "failed to get memory region\n"); ++ return -ENOENT; ++ } ++ ++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ ++ if (res == NULL) { ++ printk(KERN_INFO "failed to get irq resource\n"); ++ return -ENOENT; ++ } ++ ++ irq_no = res->start; ++ ret = request_irq(res->start, s3c_jpeg_irq, 0, pdev->name, pdev); ++ ++ if (ret != 0) { ++ printk(KERN_INFO "failed to install irq (%d)\n", ret); ++ return ret; ++ } ++ ++ s3c_jpeg_base = ioremap(s3c_jpeg_mem->start, size); ++ ++ if (s3c_jpeg_base == 0) { ++ printk(KERN_INFO "failed to ioremap() region\n"); ++ return -EINVAL; ++ } ++ ++ // JPEG clock was set as 66 MHz ++ s3c_jpeg_clk = clk_get(&pdev->dev, "jpeg"); ++ ++ if (s3c_jpeg_clk == NULL) { ++ printk(KERN_INFO "failed to find jpeg clock source\n"); ++ return -ENOENT; ++ } ++ ++ clk_enable(s3c_jpeg_clk); ++ ++ init_waitqueue_head(&wait_queue_jpeg); ++ ++ log_msg(LOG_TRACE, "s3c_jpeg_probe", "JPG_Init\n"); ++ ++ // Mutex initialization ++ h_mutex = create_jpg_mutex(); ++ ++ if (h_mutex == NULL) { ++ log_msg(LOG_ERROR, "s3c_jpeg_probe", "DD::JPG Mutex Initialize error\r\n"); ++ return FALSE; ++ } ++ ++ ret = lock_jpg_mutex(); ++ ++ if (!ret) { ++ log_msg(LOG_ERROR, "s3c_jpeg_probe", "DD::JPG Mutex Lock Fail\n"); ++ return FALSE; ++ } ++ ++ instanceNo = 0; ++ ++ unlock_jpg_mutex(); ++ ++ ret = misc_register(&s3c_jpeg_miscdev); ++ ++ clk_disable(jpeg_hclk); ++ clk_disable(jpeg_sclk); ++ ++ return 0; ++} ++ ++static int s3c_jpeg_remove(struct platform_device *dev) ++{ ++ if (s3c_jpeg_mem != NULL) { ++ release_resource(s3c_jpeg_mem); ++ kfree(s3c_jpeg_mem); ++ s3c_jpeg_mem = NULL; ++ } ++ ++ free_irq(irq_no, dev); ++ misc_deregister(&s3c_jpeg_miscdev); ++ return 0; ++} ++ ++ ++static struct platform_driver s3c_jpeg_driver = { ++ .probe = s3c_jpeg_probe, ++ .remove = s3c_jpeg_remove, ++ .shutdown = NULL, ++ .suspend = NULL, ++ .resume = NULL, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "s3c-jpg", ++ }, ++}; ++ ++static char banner[] __initdata = KERN_INFO "S3C JPEG Driver, (c) 2007 Samsung Electronics\n"; ++ ++static int __init s3c_jpeg_init(void) ++{ ++ printk(banner); ++ return platform_driver_register(&s3c_jpeg_driver); ++} ++ ++static void __exit s3c_jpeg_exit(void) ++{ ++ DWORD ret; ++ ++ log_msg(LOG_TRACE, "s3c_jpeg_exit", "JPG_Deinit\n"); ++ ++ ret = lock_jpg_mutex(); ++ ++ if (!ret) { ++ log_msg(LOG_ERROR, "s3c_jpeg_exit", "DD::JPG Mutex Lock Fail\r\n"); ++ } ++ ++ unlock_jpg_mutex(); ++ ++ delete_jpg_mutex(); ++ ++ platform_driver_unregister(&s3c_jpeg_driver); ++ printk("S3C JPEG driver module exit\n"); ++} ++ ++module_init(s3c_jpeg_init); ++module_exit(s3c_jpeg_exit); ++ ++MODULE_AUTHOR("Peter, Oh"); ++MODULE_DESCRIPTION("S3C JPEG Encoder/Decoder Device Driver"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/jpeg_v2/s3c-jpeg.h linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/s3c-jpeg.h +--- linux-2.6.28/drivers/media/video/samsung/jpeg_v2/s3c-jpeg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/jpeg_v2/s3c-jpeg.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,30 @@ ++/* linux/drivers/media/video/samsung/jpeg_v2/s3c-jpeg.h ++ * ++ * Driver header file for Samsung JPEG Encoder/Decoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __JPEG_DRIVER_H__ ++#define __JPEG_DRIVER_H__ ++ ++ ++#define MAX_INSTANCE_NUM 1 ++#define MAX_PROCESSING_THRESHOLD 1000 // 1Sec ++ ++#define IOCTL_JPG_DECODE 0x00000002 ++#define IOCTL_JPG_ENCODE 0x00000003 ++#define IOCTL_JPG_GET_STRBUF 0x00000004 ++#define IOCTL_JPG_GET_FRMBUF 0x00000005 ++#define IOCTL_JPG_GET_THUMB_STRBUF 0x0000000A ++#define IOCTL_JPG_GET_THUMB_FRMBUF 0x0000000B ++#define IOCTL_JPG_GET_PHY_FRMBUF 0x0000000C ++#define IOCTL_JPG_GET_PHY_THUMB_FRMBUF 0x0000000D ++#define JPG_CLOCK_DIVIDER_RATIO_QUARTER 4 ++ ++#endif /*__JPEG_DRIVER_H__*/ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/Kconfig linux-2.6.28.6/drivers/media/video/samsung/mfc10/Kconfig +--- linux-2.6.28/drivers/media/video/samsung/mfc10/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/Kconfig 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,15 @@ ++# ++# Configuration for Multi Format Codecs (MFC) ++# ++ ++config VIDEO_MFC10 ++ bool "Samsung FIMV V1.0 - MFC (Multi Format Codec) Driver" ++ depends on VIDEO_SAMSUNG && (CPU_S3C6410 || CPU_S3C6400) ++ default n ++ ---help--- ++ This is a Multi Format Codecs (MFC) driver for Samsung S3C6400 and s3C6410. ++ ++config VIDEO_MFC_DEBUG ++ bool "print MFC debug message" ++ depends on VIDEO_MFC10 ++ default n +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/Makefile linux-2.6.28.6/drivers/media/video/samsung/mfc10/Makefile +--- linux-2.6.28/drivers/media/video/samsung/mfc10/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/Makefile 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,8 @@ ++obj-$(CONFIG_VIDEO_MFC10) += prism_s_v137.o s3c_mfc_bitproc_buf.o s3c_mfc.o s3c_mfc_databuf.o s3c_mfc_init_hw.o s3c_mfc_instance.o s3c_mfc_inst_pool.o s3c_mfc_set_config.o s3c_mfc_sfr.o s3c_mfc_yuv_buf_manager.o ++ ++EXTRA_CFLAGS += -DLINUX ++EXTRA_CFLAGS += -DDIVX_ENABLE ++ ++ifeq ($(CONFIG_VIDEO_MFC_DEBUG),y) ++EXTRA_CFLAGS += -DDEBUG ++endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/prism_s.h linux-2.6.28.6/drivers/media/video/samsung/mfc10/prism_s.h +--- linux-2.6.28/drivers/media/video/samsung/mfc10/prism_s.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/prism_s.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,18 @@ ++/* linux/driver/media/video/mfc/prism_s.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_PRISM_S_H ++#define _S3C_PRISM_S_H ++ ++extern const unsigned short s3c_mfc_bit_code[40960]; ++ ++#endif /* _S3C_PRISM_S_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/prism_s_v137.c linux-2.6.28.6/drivers/media/video/samsung/mfc10/prism_s_v137.c +--- linux-2.6.28/drivers/media/video/samsung/mfc10/prism_s_v137.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/prism_s_v137.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,5137 @@ ++/* linux/driver/media/video/mfc/prism_s_v137.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * BIT ASSEMBLY CODE TABLE ++ * generated with ++ * generated at Mon Sep 08 21:36:59 2008 ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++const unsigned short s3c_mfc_bit_code[40960] = { ++ 0xe40e, 0x0022, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, ++ 0xe470, 0xe190, 0xe40e, 0x0152, 0xe470, 0xe190, 0xe470, 0xe190, ++ 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, ++ 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, ++ 0xf202, 0x1307, 0xc001, 0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, ++ 0x0008, 0xe0c2, 0x0058, 0xa200, 0xe0c2, 0x005a, 0xa2fe, 0x4e71, ++ 0x4e72, 0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d, 0xce00, 0xf11e, ++ 0xe0c0, 0x005c, 0xe0c1, 0x0059, 0x4f70, 0xa203, 0x3570, 0xe052, ++ 0xf08a, 0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00, ++ 0xe41e, 0x0084, 0xe0c0, 0x005b, 0x0c72, 0xe418, 0x00b2, 0xe0c0, ++ 0x0059, 0xa114, 0xf18a, 0xa102, 0xf1da, 0xe0c0, 0x005a, 0x0c71, ++ 0xe418, 0x00ab, 0xe0c0, 0x0059, 0xae02, 0xe000, 0x0152, 0xc000, ++ 0xe67c, 0xc001, 0xe0c0, 0x005a, 0x4e71, 0xe0c0, 0x005b, 0x4e72, ++ 0xe40e, 0x0038, 0x1471, 0xe412, 0x010d, 0xa202, 0x4e73, 0xe40e, ++ 0x0061, 0xe41e, 0x00c6, 0xd101, 0x0001, 0xc71e, 0xa002, 0xa200, ++ 0xe0c2, 0x0083, 0xa202, 0xe0c2, 0x0093, 0xc71e, 0xa002, 0xd071, ++ 0x002a, 0xe181, 0xe40e, 0x0061, 0xa200, 0xe0c2, 0x0059, 0xe0c2, ++ 0x0058, 0xe0c2, 0x0008, 0xe0c0, 0x0059, 0xf7ea, 0xa11e, 0xf168, ++ 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058, 0xe004, 0xf202, 0xae20, ++ 0xe005, 0x1307, 0xe056, 0xe0c2, 0x0070, 0xa200, 0xe0c2, 0x0059, ++ 0xe0c2, 0x0058, 0xe0c2, 0x0008, 0xf67e, 0xa202, 0xe0c2, 0x0008, ++ 0xe0c2, 0x0058, 0xe42e, 0x1471, 0xe424, 0xe41e, 0x010d, 0xe41e, ++ 0x00c6, 0xe42e, 0xe0c0, 0x0040, 0xe0c1, 0x005b, 0xae1d, 0xe042, ++ 0xe000, 0x1000, 0xce20, 0xd111, 0x0800, 0xd112, 0x1000, 0xd113, ++ 0x000b, 0xca28, 0xf7f8, 0xe41e, 0x17e0, 0xe42e, 0xe0c0, 0x0041, ++ 0xe005, 0x0000, 0xae11, 0xe042, 0xe0c1, 0x005a, 0xae19, 0xe042, ++ 0xce20, 0xd111, 0x0000, 0xd112, 0x0800, 0xd113, 0x0003, 0xca28, ++ 0xf7f8, 0xe0c0, 0x0041, 0xe005, 0x0080, 0xae11, 0xe042, 0xe0c1, ++ 0x005a, 0xae15, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0200, ++ 0xd113, 0x0013, 0xca28, 0xf7f8, 0xe161, 0x00f4, 0x8891, 0x0032, ++ 0x8891, 0x0033, 0x8891, 0x0034, 0x8891, 0x0035, 0x8891, 0x0036, ++ 0x8891, 0x0037, 0x1091, 0x2691, 0xcc60, 0x1091, 0x2691, 0xcc62, ++ 0x1091, 0x2691, 0xcc74, 0x1091, 0x2691, 0xcf68, 0x1091, 0x2691, ++ 0xcf64, 0x1091, 0x2691, 0xcf60, 0xe42e, 0xe161, 0x00f4, 0x8991, ++ 0x0032, 0x8991, 0x0033, 0x8991, 0x0034, 0x8991, 0x0035, 0x8991, ++ 0x0036, 0x8991, 0x0037, 0xc860, 0x4891, 0x4e91, 0xc862, 0x4891, ++ 0x4e91, 0xc874, 0x4891, 0x4e91, 0xcb68, 0x4891, 0x4e91, 0xcb64, ++ 0x4891, 0x4e91, 0xcb60, 0x4891, 0x4e91, 0xe0c0, 0x0041, 0xe005, ++ 0x0000, 0xae11, 0xe042, 0x1571, 0xae19, 0xe042, 0xce20, 0xd111, ++ 0x0000, 0xd112, 0x0800, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe0c0, ++ 0x0041, 0xe005, 0x0080, 0xae11, 0xe042, 0x1571, 0xae15, 0xe042, ++ 0xce20, 0xd111, 0x0000, 0xd112, 0x0200, 0xd113, 0x0012, 0xca28, ++ 0xf7f8, 0xe42e, 0xe40e, 0x1212, 0xe40e, 0x0172, 0xe40e, 0x0176, ++ 0xe40e, 0x017a, 0xe40e, 0x017e, 0xe40e, 0x0061, 0xe40e, 0x0061, ++ 0xe40e, 0x0061, 0xe40e, 0x0061, 0xe40e, 0x0061, 0xe40e, 0x0061, ++ 0xe40e, 0x0061, 0xe40e, 0x0061, 0xe40e, 0x0061, 0xe40e, 0x0061, ++ 0xe40e, 0x0061, 0xe41e, 0x0182, 0xe40e, 0x0061, 0xe41e, 0x01dc, ++ 0xe40e, 0x0061, 0xe41e, 0x01dd, 0xe40e, 0x0061, 0xe41e, 0x028f, ++ 0xe40e, 0x0061, 0xa200, 0xcc74, 0x4e4e, 0xc401, 0xe188, 0x07ff, ++ 0x4e91, 0xe41e, 0x02a1, 0xc001, 0xe0c0, 0x0064, 0x4800, 0x4e01, ++ 0xe0c0, 0x0065, 0x4802, 0x4e03, 0xe0c0, 0x0066, 0x4804, 0x4e05, ++ 0xe0c0, 0x0047, 0x4e06, 0xc000, 0xa200, 0x4e6d, 0x4e4c, 0xc001, ++ 0x4e09, 0x4e0d, 0xc000, 0xe0c0, 0x0062, 0x4673, 0xaf04, 0xc001, ++ 0x4608, 0xc000, 0xaf02, 0xc001, 0x460c, 0xc000, 0xe41e, 0x0dec, ++ 0xe41e, 0x11c6, 0xe41e, 0x0a66, 0xf23a, 0xe41e, 0x11e2, 0xe128, ++ 0x1407, 0xae14, 0x260e, 0xe0c2, 0x0071, 0x1621, 0xa102, 0xae20, ++ 0x2620, 0xe0c2, 0x0072, 0x1435, 0xae02, 0x2630, 0xae02, 0x2623, ++ 0xae02, 0x2622, 0xe0c2, 0x0075, 0xa204, 0xe0c2, 0x0073, 0xa200, ++ 0x4e6d, 0xe0c2, 0x0074, 0xa202, 0xe0c2, 0x0070, 0xe42e, 0xa200, ++ 0x4e6d, 0xe0c2, 0x0070, 0xe42e, 0xe42e, 0xa200, 0xcc44, 0xe0c0, ++ 0x0068, 0xc001, 0x4610, 0xaf02, 0x460e, 0xaf02, 0x460f, 0xc000, ++ 0xa2fe, 0xe0c2, 0x0077, 0xc001, 0x1473, 0xf04a, 0xa200, 0x4e0d, ++ 0x4e73, 0xc000, 0xc001, 0x1408, 0xc000, 0xf05a, 0xe41e, 0x1197, ++ 0xe40e, 0x0206, 0xc001, 0x1408, 0xc000, 0xf098, 0xe41e, 0x13e5, ++ 0xf06a, 0xa2fe, 0xe0c2, 0x0071, 0xe40e, 0x027c, 0x1424, 0xf158, ++ 0xc001, 0x140d, 0xc000, 0xf118, 0xa202, 0xc001, 0x4e0d, 0xc000, ++ 0xd101, 0x0001, 0xc71e, 0xa002, 0xa200, 0xe0c2, 0x0083, 0xa202, ++ 0xe0c2, 0x0093, 0xc71e, 0xa002, 0xa200, 0xcc4a, 0xcc4c, 0xcc74, ++ 0xd180, 0x0000, 0xd147, 0x0000, 0xd03b, 0x0000, 0xd008, 0x0000, ++ 0xe16a, 0xa200, 0xcf06, 0xe0c2, 0x0286, 0x4e46, 0x1430, 0xf048, ++ 0xe41e, 0x0a95, 0xf03e, 0xe41e, 0x0aed, 0xe40a, 0x0280, 0xc001, ++ 0x1408, 0xc000, 0xf01a, 0xe41e, 0x0def, 0x142d, 0xf0c8, 0xa200, ++ 0x4e44, 0x1452, 0x4e43, 0xa202, 0x4e42, 0xe41e, 0x044e, 0xa200, ++ 0x4e46, 0xf0be, 0x1436, 0xe016, 0x2230, 0xf048, 0xe41e, 0x0328, ++ 0xf03e, 0xe41e, 0x0362, 0xf2da, 0xe41e, 0x0f6b, 0xe41e, 0x0fb6, ++ 0xe41e, 0x0ff0, 0xe41e, 0x1027, 0xe41e, 0x1053, 0xc875, 0xe0c0, ++ 0x006c, 0xae06, 0xe045, 0xe0c3, 0x007c, 0x164c, 0xa002, 0x4e4c, ++ 0xe0c2, 0x0070, 0x1424, 0xe0c2, 0x0073, 0x1446, 0xe0c2, 0x0072, ++ 0xc84a, 0xc84d, 0xae20, 0xe056, 0xe0c2, 0x0046, 0xc001, 0x1408, ++ 0xc000, 0xf038, 0xe41e, 0x13d4, 0xa202, 0xe0c2, 0x0076, 0xe42e, ++ 0xc875, 0xe0c3, 0x007c, 0xe41e, 0x13d4, 0x1424, 0xe0c2, 0x0073, ++ 0xa2fe, 0xe0c2, 0x0072, 0xa200, 0xe0c2, 0x0076, 0xe42e, 0xe0c0, ++ 0x0042, 0xce20, 0xd111, 0x03f0, 0xd112, 0x0030, 0xd113, 0x0003, ++ 0xca28, 0xf7f8, 0xe0c0, 0x0060, 0x4e4d, 0xe0c0, 0x0061, 0x4e70, ++ 0xe42e, 0xe0c0, 0x0040, 0xe000, 0x3000, 0xce20, 0xd111, 0x02a0, ++ 0xd112, 0x0100, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e, 0x1454, ++ 0xae06, 0xe000, 0x0420, 0xe09e, 0x1458, 0x2659, 0xf028, 0xf09e, ++ 0xd022, 0x0003, 0xe184, 0x02be, 0xa200, 0x4e97, 0x4e97, 0xf13e, ++ 0xe161, 0x03e1, 0x1581, 0x8891, 0x0022, 0xe184, 0x02ca, 0x1091, ++ 0x2691, 0x4897, 0x4e97, 0xf079, 0xd022, 0x0002, 0xe184, 0x02d1, ++ 0x4897, 0x4e97, 0x1454, 0xa002, 0x0c50, 0xe428, 0x1450, 0xae08, ++ 0x4e49, 0x8249, 0x8155, 0xe018, 0xe0c1, 0x006d, 0xe042, 0xce20, ++ 0xd111, 0x0420, 0x1449, 0xaf02, 0xce24, 0xd113, 0x0002, 0xca28, ++ 0xf7f8, 0xe42e, 0x1453, 0xa802, 0xf07a, 0x1559, 0xc001, 0x1411, ++ 0xc000, 0xe056, 0xf0ae, 0x1459, 0xae10, 0xc001, 0x4e11, 0xc000, ++ 0x1553, 0xa003, 0x0d52, 0xe429, 0x1553, 0xe009, 0x00ff, 0xaf03, ++ 0xe001, 0x05a0, 0xe09f, 0x4e87, 0x1453, 0xa002, 0x0c52, 0xf06a, ++ 0x1453, 0xa002, 0xe008, 0x00ff, 0xe428, 0x1453, 0xe008, 0xff00, ++ 0xe0c1, 0x006e, 0xe042, 0xce20, 0xe004, 0x0080, 0x1553, 0xa003, ++ 0x0d52, 0xf078, 0x1453, 0xe008, 0x00ff, 0xa006, 0xe008, 0x00fc, ++ 0xce24, 0xd111, 0x05a0, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, ++ 0xa223, 0x1424, 0xf03a, 0x1528, 0xa021, 0x4f61, 0x1427, 0x4e42, ++ 0xa200, 0x4e2f, 0x4e43, 0x4e44, 0x1444, 0x262f, 0xf14a, 0x1436, ++ 0xf088, 0xe41e, 0x04dc, 0xf0da, 0xe41e, 0x0afa, 0x4e43, 0xf0be, ++ 0xe41e, 0x0516, 0xf06a, 0xa200, 0xe41e, 0x0b30, 0x4e43, 0xf03e, ++ 0x1452, 0x4e43, 0x1444, 0x0c43, 0xf680, 0xf07a, 0xe41e, 0x044e, ++ 0x1443, 0x4e44, 0x0c52, 0xf0da, 0xe41e, 0x1121, 0xa202, 0x4e2f, ++ 0xe41e, 0x03af, 0x1469, 0xa002, 0x4e69, 0x1444, 0x0c52, 0xf554, ++ 0xa202, 0xe42e, 0x1427, 0x4e42, 0xa200, 0x4e43, 0x4e44, 0x4e33, ++ 0xa2fe, 0x4e40, 0xe41e, 0x1121, 0x1444, 0x0c43, 0xf072, 0xe41e, ++ 0x044e, 0x1443, 0x4e44, 0x0c52, 0xf2fa, 0xe41e, 0x03af, 0x1443, ++ 0x0432, 0x4e43, 0x1433, 0xa002, 0x4e33, 0x1444, 0x0c52, 0xf24a, ++ 0x1444, 0x0c43, 0xf094, 0xba20, 0xa102, 0xf678, 0xe41e, 0x1121, ++ 0x1469, 0xa002, 0x4e69, 0xe41e, 0x04f5, 0x1441, 0xf12a, 0xba60, ++ 0xba48, 0x4e41, 0x1440, 0xba43, 0xf038, 0xe046, 0xf758, 0xba48, ++ 0x4e27, 0x1441, 0x4e33, 0x8233, 0x8132, 0xe018, 0x4e43, 0xf4de, ++ 0x1452, 0x4e43, 0xf4ae, 0xa22c, 0xe41e, 0x0479, 0xa17e, 0xf048, ++ 0xe41e, 0x0b63, 0xba6a, 0xe41e, 0x0b63, 0xa202, 0xe42e, 0x1427, ++ 0x4e62, 0x1432, 0x0443, 0x4e45, 0x1422, 0xf1ea, 0x1424, 0xf048, ++ 0xe41e, 0x063a, 0xf03e, 0xe41e, 0x06e4, 0xf048, 0x1443, 0x4e44, ++ 0xe42e, 0x1424, 0xf048, 0xe41e, 0x068e, 0xf03e, 0xe41e, 0x074a, ++ 0xf048, 0x1443, 0x4e44, 0xe42e, 0xe41e, 0x083a, 0xe41e, 0x0850, ++ 0xe12c, 0xa200, 0x4e47, 0x1443, 0x4e53, 0xc70f, 0x3c50, 0x4854, ++ 0x4e55, 0x1453, 0x0c52, 0xe40a, 0x0449, 0xe41e, 0x1141, 0x1453, ++ 0xe002, 0x004f, 0xf028, 0xe190, 0xe41e, 0x0535, 0xe40a, 0x044c, ++ 0x145d, 0x4e62, 0xc001, 0x1410, 0xf05a, 0x140f, 0xc000, 0xe418, ++ 0x02ea, 0xc000, 0xc001, 0x1410, 0xf05a, 0x140e, 0xc000, 0xe418, ++ 0x02af, 0xc000, 0xe41e, 0x0f5d, 0x1453, 0xa002, 0x4e53, 0xc001, ++ 0x1408, 0xc000, 0xf0da, 0x1453, 0x0c52, 0xf0aa, 0xc874, 0xc001, ++ 0x130a, 0x270b, 0xc000, 0xae07, 0xe045, 0xe405, 0x044c, 0xe41e, ++ 0x114d, 0x1422, 0xf168, 0x1436, 0xf1e8, 0x1430, 0xf238, 0xe41e, ++ 0x04c8, 0xe41e, 0x04af, 0xf05a, 0xba40, 0xe41e, 0x0b63, 0xf2ae, ++ 0xe41e, 0x0497, 0xe40a, 0x03d9, 0xba40, 0xe41e, 0x0b63, 0xf22e, ++ 0x1453, 0x0c45, 0xe408, 0x03d9, 0x1447, 0xf1c8, 0xba40, 0xe41e, ++ 0x0b63, 0xf18e, 0xe41e, 0x04d0, 0xe40a, 0x03d9, 0xe41e, 0x0b63, ++ 0xf11e, 0x1453, 0x0c45, 0xe408, 0x03d9, 0x1462, 0x4e27, 0xba20, ++ 0xa102, 0xf08a, 0xa222, 0xe41e, 0x0479, 0xa102, 0xf038, 0xe41e, ++ 0x0b63, 0x1453, 0x4e44, 0xe42e, 0xe16a, 0xf7ce, 0x164c, 0xe016, ++ 0x4e58, 0xe016, 0x4e59, 0x1442, 0x4e5d, 0xa200, 0x4e5b, 0x4e5f, ++ 0x4e5c, 0x1444, 0x4e53, 0xc70f, 0x3c50, 0x4854, 0x4e55, 0x1453, ++ 0x0c43, 0xf132, 0xe41e, 0x1141, 0x1458, 0xe418, 0x1165, 0x1458, ++ 0xe41a, 0x0a59, 0xe41e, 0x0ed9, 0xe41e, 0x0f5d, 0x1453, 0xa002, ++ 0x4e53, 0xe41e, 0x114d, 0xf6ce, 0x1443, 0x0c44, 0x0446, 0x4e46, ++ 0xe42e, 0x4e48, 0xc865, 0xa80f, 0xe042, 0x4e49, 0x5e49, 0xa203, ++ 0x3548, 0xa103, 0xe052, 0xe42e, 0xe41e, 0x04c8, 0xe005, 0x006b, ++ 0xae19, 0xa003, 0xba24, 0xe046, 0xe016, 0xe42e, 0xe41e, 0x04c8, ++ 0xa23f, 0xae19, 0xa003, 0xba20, 0xe046, 0xe016, 0xe42e, 0xc864, ++ 0xa80e, 0xa102, 0xb6e8, 0xa002, 0x4e48, 0x5e48, 0xa203, 0x3548, ++ 0xaf03, 0xa103, 0xe046, 0xe016, 0xe42a, 0xa22e, 0x0448, 0x4e48, ++ 0x5e48, 0xa203, 0xae2f, 0xa103, 0xe052, 0xe016, 0xe42e, 0xc864, ++ 0xa80e, 0xa102, 0xb6e8, 0xa002, 0x4e48, 0x5e48, 0xa203, 0x3548, ++ 0xaf03, 0xa103, 0xe046, 0xe016, 0xe42a, 0x1461, 0x0448, 0x4e48, ++ 0x5e48, 0xa203, 0x3561, 0xa103, 0xe052, 0xa102, 0xe016, 0xe42e, ++ 0x1424, 0xa012, 0x4e48, 0x5e48, 0xa102, 0xe428, 0x5648, 0xf7ce, ++ 0xc865, 0xa80f, 0x4f48, 0x5e48, 0xe016, 0xa023, 0x4f48, 0xe42a, ++ 0x5e48, 0xa102, 0xe016, 0xe42e, 0xe41e, 0x0b63, 0x5e61, 0xa102, ++ 0xe016, 0xe428, 0xba2c, 0xe42a, 0xba4e, 0xc001, 0x1408, 0xc000, ++ 0xf0ca, 0xc874, 0xc001, 0x130a, 0x270b, 0xc000, 0xae07, 0xe045, ++ 0xe403, 0x04f4, 0xa200, 0xe42e, 0xf6ae, 0xba20, 0xa102, 0xf12a, ++ 0xc001, 0x1408, 0xc000, 0xf0ca, 0xc874, 0xc001, 0x130a, 0x270b, ++ 0xc000, 0xae07, 0xe045, 0xe403, 0x0507, 0xa200, 0xe42e, 0xba40, ++ 0xf6de, 0xba2a, 0xa83e, 0x4e41, 0xe42a, 0xa13e, 0xe42a, 0x1441, ++ 0x0c33, 0xf674, 0x1441, 0x0c32, 0xf642, 0xe42e, 0xe41e, 0x0b63, ++ 0xba20, 0xa102, 0xf12a, 0xc001, 0x1408, 0xc000, 0xf0ca, 0xc874, ++ 0xc001, 0x130a, 0x270b, 0xc000, 0xae07, 0xe045, 0xe403, 0x052a, ++ 0xa200, 0xe42e, 0xba4e, 0xf6de, 0xba2a, 0xa83e, 0xe42a, 0xa13e, ++ 0xe42a, 0xa03e, 0xaf08, 0xf68a, 0xe42e, 0x1430, 0xe408, 0x05b2, ++ 0x1422, 0x1524, 0xf05a, 0xe40b, 0x06ab, 0xe40e, 0x07a1, 0xa200, ++ 0x0424, 0x4e00, 0x5624, 0x4e59, 0xe408, 0x059c, 0x5000, 0xa10e, ++ 0xe40d, 0x05a2, 0xf78a, 0xa00e, 0x4658, 0xaf02, 0x465a, 0xaf02, ++ 0x465b, 0xaf02, 0x4e01, 0x5658, 0x4e5c, 0xa20a, 0x0c58, 0x4e00, ++ 0x5000, 0xae04, 0x2601, 0x4e5e, 0xe40d, 0x05a2, 0x145a, 0x1562, ++ 0x4f5d, 0xe418, 0x0926, 0x1458, 0xe41a, 0x0988, 0xf3cd, 0x1458, ++ 0xe418, 0x1165, 0x1458, 0x1562, 0x0d26, 0xb606, 0x4e5f, 0xe41e, ++ 0x0ed9, 0xa214, 0x0c58, 0xe096, 0xa004, 0xe098, 0xe161, 0x03da, ++ 0xd022, 0x0005, 0x145e, 0xe184, 0x057e, 0x4689, 0xaf02, 0xe161, ++ 0x03d5, 0xa200, 0x4e60, 0xd022, 0x0005, 0xe184, 0x0599, 0x1460, ++ 0xce90, 0x145f, 0xd140, 0x0000, 0xf07a, 0xe41e, 0x0902, 0xe008, ++ 0x0fff, 0xf14d, 0xce82, 0x1491, 0xe418, 0x0866, 0xf0fd, 0x1460, ++ 0xa002, 0x4e60, 0xa202, 0xe42e, 0x1462, 0x4e5d, 0xe41e, 0x0631, ++ 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0xe16a, 0xe41e, 0x0f5d, ++ 0x1453, 0xa002, 0x4e53, 0xe41e, 0x114d, 0x1446, 0xa002, 0x4e46, ++ 0xa200, 0xe42e, 0xa200, 0x1524, 0xb452, 0x2335, 0xb432, 0x4e00, ++ 0x5624, 0x4e59, 0xe408, 0x061e, 0x5000, 0xa10e, 0xe40d, 0x0624, ++ 0xf78a, 0xa00e, 0x4658, 0xaf02, 0x465a, 0xaf02, 0x465b, 0xaf02, ++ 0x4e01, 0x1458, 0x2234, 0xf07a, 0xba40, 0x4e5c, 0x575c, 0x345c, ++ 0xe042, 0x4e5c, 0xa20a, 0x0c58, 0x4e00, 0x5000, 0xae04, 0x2601, ++ 0x4e5e, 0xe40d, 0x0624, 0x145a, 0x1562, 0x4f5d, 0xe418, 0x0930, ++ 0x1458, 0xf088, 0x1439, 0xf04a, 0xe41e, 0x09a8, 0xf03e, 0xe41e, ++ 0x0988, 0xf3bd, 0x1458, 0xe418, 0x1165, 0x1434, 0xe016, 0x2258, ++ 0x4e5f, 0xe41e, 0x0ed9, 0xa214, 0x1534, 0x2358, 0xb4b2, 0xe096, ++ 0xe161, 0x03da, 0xd022, 0x0005, 0x145e, 0xe184, 0x0600, 0x4689, ++ 0xaf02, 0xe161, 0x03d5, 0xa200, 0x4e60, 0xd022, 0x0005, 0xe184, ++ 0x061b, 0x1460, 0xce90, 0x145f, 0xd140, 0x0000, 0xf07a, 0xe41e, ++ 0x0918, 0xf16d, 0xe008, 0x0fff, 0xce82, 0x1491, 0xe418, 0x0866, ++ 0xf0fd, 0x1460, 0xa002, 0x4e60, 0xa202, 0xe42e, 0x1462, 0x4e5d, ++ 0xe41e, 0x0631, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0xe16a, ++ 0xe41e, 0x0f5d, 0x1453, 0xa002, 0x4e53, 0xe41e, 0x114d, 0xa200, ++ 0xe42e, 0xe41e, 0x0a59, 0xa200, 0x4e5f, 0x4e58, 0x4e5c, 0xe41e, ++ 0x0ed9, 0xe42e, 0xe41e, 0x0816, 0x1443, 0x4e53, 0x1453, 0x0c52, ++ 0xf3b2, 0x1453, 0xe002, 0x0230, 0xf028, 0xe190, 0xe12c, 0xb800, ++ 0xa10e, 0xe40d, 0x0688, 0xf7ca, 0xa00e, 0x4658, 0xaf02, 0x465a, ++ 0xaf02, 0x465b, 0xaf02, 0x4e01, 0x145a, 0x1562, 0x4f5d, 0xe418, ++ 0x0926, 0xa202, 0x1562, 0x0d26, 0xb606, 0x4e5f, 0x145f, 0xe418, ++ 0x08f2, 0xf27d, 0xe12d, 0x1401, 0xba82, 0x145d, 0xba88, 0x145f, ++ 0xba80, 0xe161, 0x03db, 0xd022, 0x0005, 0xe184, 0x0670, 0x1491, ++ 0xba9e, 0xe12c, 0x145d, 0x4e62, 0x1453, 0xa002, 0x4e53, 0xe41e, ++ 0x0484, 0xe40a, 0x063e, 0xba64, 0xe12d, 0xbabe, 0xe190, 0xbabe, ++ 0x141a, 0xe418, 0x12b5, 0xe12c, 0x1453, 0x4e45, 0xa202, 0xe42e, ++ 0xe16a, 0xe12c, 0x1453, 0x4e45, 0xa200, 0xe42e, 0xe41e, 0x0828, ++ 0x1445, 0x0c43, 0xf12a, 0xa102, 0xcc44, 0xe184, 0x069d, 0xe12c, ++ 0xba40, 0xb809, 0xf0dd, 0xe12e, 0xba80, 0xba87, 0xbabe, 0xe190, ++ 0xbabe, 0x141b, 0xe418, 0x12d9, 0xe12c, 0xa202, 0xe42e, 0xe16a, ++ 0xe12c, 0xa200, 0xe42e, 0xa202, 0x4e58, 0xa212, 0x1523, 0xb492, ++ 0xe096, 0xa216, 0xe098, 0xe161, 0x03d5, 0xe12e, 0xba40, 0x4e5c, ++ 0xba40, 0x4e91, 0xba40, 0x4e91, 0xba40, 0x4e91, 0xba40, 0x4e91, ++ 0xe12d, 0xba40, 0x4e91, 0xba40, 0x4e91, 0xba48, 0x4e5d, 0xba40, ++ 0x4e5f, 0xe161, 0x03db, 0xd022, 0x0005, 0xe184, 0x06d0, 0xba5e, ++ 0x4e91, 0xe41e, 0x0ed9, 0x1447, 0xe12c, 0xe418, 0x0974, 0x1447, ++ 0xf078, 0xe41e, 0x0944, 0xf04c, 0xe16a, 0xa202, 0x4e47, 0x1446, ++ 0x0447, 0x4e46, 0xa202, 0xe42e, 0xe41e, 0x0816, 0x1443, 0x4e53, ++ 0x1453, 0x0c52, 0xe402, 0x0737, 0xe12c, 0xba40, 0xe408, 0x072d, ++ 0xb802, 0xa10e, 0xe40d, 0x0744, 0xf79a, 0xa00e, 0x4e01, 0xa80e, ++ 0x4658, 0xaf02, 0x465a, 0xaf02, 0x465b, 0x1401, 0xaf06, 0x4e01, ++ 0x1458, 0xe161, 0x03a0, 0xf108, 0x145b, 0xb670, 0xcc44, 0xe184, ++ 0x0712, 0xe41e, 0x0a34, 0xe40d, 0x0744, 0x4e91, 0xe41e, 0x0a34, ++ 0xe40d, 0x0744, 0x4e91, 0xe12d, 0xbac0, 0x145b, 0xae02, 0x265a, ++ 0xae02, 0x2658, 0xba84, 0x1401, 0xba82, 0x1458, 0xe161, 0x03a0, ++ 0xe408, 0x072f, 0x145b, 0xb670, 0xcc44, 0xe184, 0x072a, 0x1491, ++ 0xba9c, 0x1491, 0xba9c, 0xe40e, 0x072f, 0xe12d, 0xbae0, 0xe12c, ++ 0x1453, 0xa002, 0x4e53, 0xe41e, 0x048e, 0xe40a, 0x06e8, 0xba60, ++ 0xe12d, 0xbabe, 0xe190, 0xbabe, 0x141a, 0xe418, 0x12b5, 0xe12c, ++ 0x1453, 0x4e45, 0xa202, 0xe42e, 0xe16a, 0xe12c, 0x1453, 0x4e45, ++ 0xa200, 0xe42e, 0xe41e, 0x083a, 0xe41e, 0x0828, 0x1443, 0x4e53, ++ 0x1453, 0xe002, 0x0030, 0xf028, 0xe190, 0xe41e, 0x07fc, 0x1459, ++ 0xe408, 0x078e, 0xe12c, 0x5658, 0x4e5c, 0xa20a, 0x0c58, 0x4e00, ++ 0x5000, 0x4e02, 0xf3bd, 0x145a, 0x1562, 0x4f5d, 0xe418, 0x0926, ++ 0x1458, 0x1562, 0x0d26, 0xb606, 0x4e5f, 0x145f, 0xe418, 0x08f2, ++ 0xe40d, 0x079d, 0xe12e, 0x1402, 0xba86, 0x145d, 0xba88, 0x145f, ++ 0xba80, 0x1458, 0xf0ba, 0x145c, 0xba80, 0xe161, 0x03db, 0xd022, ++ 0x0005, 0xe184, 0x0784, 0x1491, 0xba9e, 0x145d, 0x4e62, 0x1453, ++ 0xa002, 0x4e53, 0x0c45, 0xe408, 0x0750, 0xf06e, 0xe12e, 0x1462, ++ 0x4e5d, 0xba88, 0xf73e, 0xe12e, 0xbabe, 0xe190, 0xbabe, 0x141b, ++ 0xe418, 0x12d9, 0xe12c, 0xa202, 0xe42e, 0xe16a, 0xe12c, 0xa200, ++ 0xe42e, 0xe41e, 0x07fc, 0x1459, 0xe408, 0x07f6, 0xe161, 0x03d5, ++ 0xe12e, 0xba40, 0x4e91, 0xba40, 0x4e91, 0xba40, 0x4e91, 0xba40, ++ 0x4e91, 0x1401, 0xaf02, 0x4e91, 0x1401, 0x4691, 0xba48, 0x4e5d, ++ 0xba40, 0x4e5f, 0x1458, 0xe40a, 0x07de, 0xba40, 0x4e5c, 0xe161, ++ 0x03db, 0xd022, 0x0005, 0xe184, 0x07c6, 0xba5e, 0x4e91, 0xe41e, ++ 0x1165, 0xe41e, 0x0ed9, 0xa212, 0x1523, 0xb492, 0xe096, 0xa216, ++ 0xe098, 0x1447, 0xe12c, 0xe418, 0x0974, 0x1447, 0xf1a8, 0xe41e, ++ 0x0944, 0xf17c, 0xe16a, 0xa202, 0x4e47, 0xf13e, 0xe41e, 0x0a1a, ++ 0xe41e, 0x0ed9, 0xa214, 0x1523, 0xb492, 0xe096, 0xa218, 0xe098, ++ 0xe12c, 0x1447, 0xe41a, 0x0960, 0xf04c, 0xe16a, 0xa202, 0x4e47, ++ 0xe12c, 0x1446, 0x0447, 0x4e46, 0xa202, 0xe42e, 0xe12e, 0xba48, ++ 0x4e5d, 0xe41e, 0x0631, 0xf75e, 0xe12d, 0xba40, 0x4e59, 0xe428, ++ 0xba40, 0x4e5b, 0xba40, 0x4e5a, 0xba40, 0x4e58, 0xba42, 0x4e01, ++ 0x1458, 0xe428, 0xe161, 0x03a0, 0x145b, 0xb670, 0xcc44, 0xe184, ++ 0x0814, 0xba5c, 0x4e91, 0xba5c, 0x4e91, 0xe42e, 0xe41e, 0x11f2, ++ 0xc001, 0x1406, 0xf06a, 0x1002, 0x2603, 0xc000, 0x487e, 0xf03e, ++ 0xe004, 0x0338, 0xc000, 0x4e18, 0xa200, 0x4e1a, 0x4e16, 0xe42e, ++ 0xe41e, 0x1202, 0xc001, 0x1406, 0xf06a, 0x1004, 0x2605, 0xc000, ++ 0x487f, 0xf03e, 0xe004, 0x03f8, 0xc000, 0x4e19, 0xa200, 0x4e1b, ++ 0x4e17, 0xe42e, 0xe41e, 0x11f2, 0xc001, 0x1406, 0xf06a, 0x1002, ++ 0x2603, 0xc000, 0x487e, 0xf03e, 0xe004, 0x0338, 0xc000, 0x4e18, ++ 0x141a, 0xe418, 0x1271, 0xa202, 0x4e16, 0xe12d, 0xe128, 0xe42e, ++ 0xe41e, 0x1202, 0xc001, 0x1406, 0xf06a, 0x1004, 0x2605, 0xc000, ++ 0x487f, 0xf03e, 0xe004, 0x03f8, 0xc000, 0x4e19, 0x141b, 0xe418, ++ 0x1293, 0xa202, 0x4e17, 0xe12e, 0xe128, 0xe42e, 0x9003, 0xe049, ++ 0xaf25, 0xe42d, 0xf04a, 0xce82, 0xf7ab, 0xe42e, 0x1423, 0x1530, ++ 0xe408, 0x08d6, 0xe409, 0x08a8, 0xba40, 0xba01, 0xf03a, 0xf0eb, ++ 0xf1ae, 0xe086, 0xa102, 0xcc90, 0x9003, 0xcc92, 0xe42d, 0xc892, ++ 0xe049, 0xaf25, 0xce82, 0xf63b, 0xe42e, 0xe086, 0xa102, 0xcc90, ++ 0xba40, 0x9003, 0xcc94, 0xe42d, 0xc894, 0xe049, 0xaf25, 0xce82, ++ 0xf56b, 0xe42e, 0xba40, 0xba40, 0xae24, 0xba4b, 0xae19, 0xe056, ++ 0xba41, 0xf0db, 0xba57, 0xe056, 0xe009, 0x07ff, 0xf08b, 0xba41, ++ 0xf06b, 0xce82, 0xaf24, 0xe40a, 0x0866, 0xe42e, 0xe16b, 0xe42e, ++ 0xba40, 0xae24, 0xba4b, 0xae19, 0xe056, 0xba4f, 0x4f6c, 0xf25b, ++ 0xe003, 0x0080, 0xe40b, 0x08c3, 0x156c, 0xaf0f, 0xf07b, 0x156c, ++ 0xe003, 0x0100, 0xe009, 0x0fff, 0x4f6c, 0x266c, 0xce82, 0xaf24, ++ 0xe40a, 0x0866, 0xe42e, 0x1537, 0xf10b, 0xba49, 0x4f6c, 0xba4b, ++ 0xae0b, 0x276c, 0x4f6c, 0xaf15, 0xf71b, 0x156c, 0xe003, 0x0800, ++ 0xe009, 0x0fff, 0x4f6c, 0xf6ae, 0xe16b, 0xe42e, 0xba40, 0xf19a, ++ 0xba40, 0xae24, 0xba4b, 0xae19, 0xe056, 0xba41, 0xf12b, 0xba55, ++ 0x4f6c, 0xba41, 0xf0eb, 0xba49, 0xf06b, 0x156c, 0xe013, 0xe009, ++ 0x0fff, 0x4f6c, 0x266c, 0xce82, 0xaf24, 0xe40a, 0x0866, 0xe42e, ++ 0xe16b, 0xe42e, 0xe161, 0x03db, 0xa200, 0x4e60, 0xd022, 0x0005, ++ 0xe184, 0x0900, 0xe41e, 0x0902, 0xe42d, 0x4e91, 0x1460, 0xa002, ++ 0x4e60, 0xe42e, 0x1460, 0xaf04, 0xa00e, 0x4e6c, 0x506c, 0xe42d, ++ 0xe42a, 0x4e6c, 0xba01, 0x566c, 0xf059, 0xa203, 0x356c, 0xe046, ++ 0xa002, 0x156c, 0xa111, 0xf047, 0xba41, 0xf029, 0xe16b, 0xe42e, ++ 0xba4e, 0xe049, 0xe003, 0x0080, 0xf08a, 0xf07b, 0xe003, 0x007f, ++ 0xe429, 0xe004, 0x0080, 0xe42e, 0xe16b, 0xe42e, 0xba42, 0xe000, ++ 0x02c8, 0xe09e, 0x1487, 0x0462, 0xa402, 0xa53e, 0x4e5d, 0xe42e, ++ 0x1437, 0xe40a, 0x0926, 0xba40, 0xf0da, 0xba40, 0xae0a, 0x0462, ++ 0xe000, 0x02cc, 0xe09e, 0x1487, 0x0462, 0xa402, 0xa53e, 0x4e5d, ++ 0xe42e, 0xba48, 0x4e5d, 0xe42e, 0xa200, 0x4e60, 0xe161, 0x03db, ++ 0xe162, 0x03d5, 0xd022, 0x0005, 0xe184, 0x095e, 0x1460, 0xce90, ++ 0x145f, 0xd140, 0x0000, 0xf05a, 0x1491, 0xe008, 0x0fff, 0xce82, ++ 0x1492, 0xe418, 0x0866, 0xe42d, 0x1460, 0xa002, 0x4e60, 0xe42e, ++ 0xa200, 0x4e60, 0xe161, 0x03d5, 0xd022, 0x0005, 0xe184, 0x0972, ++ 0xd140, 0x0000, 0x1491, 0x1560, 0xce91, 0xa003, 0x4f60, 0xe418, ++ 0x0866, 0xe42d, 0xe190, 0xe42e, 0x145f, 0xe42a, 0xa200, 0x4e60, ++ 0xe161, 0x03db, 0xd022, 0x0005, 0xe184, 0x0986, 0x1460, 0xe0c2, ++ 0x0103, 0x1491, 0xe0c2, 0x0140, 0x1460, 0xa002, 0x4e60, 0xe42e, ++ 0xe41e, 0x1174, 0xe161, 0x03e1, 0x155b, 0xe004, 0x06db, 0xb616, ++ 0xcf04, 0xb673, 0x4f91, 0xcc45, 0xe184, 0x09a4, 0xe41e, 0x0a34, ++ 0xe42d, 0x4e91, 0xe41e, 0x0a34, 0xe42d, 0x4e89, 0x1091, 0x2689, ++ 0xcf0a, 0xe190, 0xcb14, 0x4891, 0x4e91, 0xe41e, 0x1186, 0xe42e, ++ 0xe41e, 0x1174, 0xe161, 0x03e1, 0x155b, 0xe004, 0x06db, 0xb616, ++ 0xcf04, 0xb673, 0x4f91, 0xcc45, 0xe184, 0x0a16, 0x143a, 0xe408, ++ 0x0a02, 0xe41e, 0x0a34, 0xe42d, 0x4e91, 0xe41e, 0x0a34, 0xe42d, ++ 0x4e89, 0x896c, 0x0181, 0x1091, 0x2689, 0xcf0a, 0xe190, 0xcb14, ++ 0x4891, 0x4e89, 0xcb0c, 0xaf20, 0xa140, 0xf086, 0xcb14, 0xaf20, ++ 0xa17e, 0xf046, 0x1481, 0xa180, 0x4e81, 0xcb0c, 0xaf20, 0xa03e, ++ 0xf082, 0xcb14, 0xaf20, 0xa07e, 0xf042, 0x1481, 0xa080, 0x4e81, ++ 0xcb0c, 0xae28, 0xaf28, 0xa140, 0xf0a6, 0xcb14, 0xae28, 0xaf28, ++ 0xa17e, 0xf056, 0x8091, 0x1481, 0xa180, 0x4e89, 0xcb0c, 0xae28, ++ 0xaf28, 0xa03e, 0xf0a2, 0xcb14, 0xae28, 0xaf28, 0xa07e, 0xf052, ++ 0x8091, 0x1481, 0xa080, 0x4e89, 0x146c, 0xcf02, 0x1091, 0x2689, ++ 0xcf08, 0xf14e, 0xe41e, 0x0a40, 0xe42d, 0x4e91, 0xe41e, 0x0a40, ++ 0xe42d, 0x4e89, 0xa102, 0xf058, 0x1481, 0xa102, 0xf028, 0xba40, ++ 0x1091, 0x2689, 0xcf0a, 0xe190, 0xcb14, 0x4891, 0x4e91, 0xe41e, ++ 0x1186, 0xe42e, 0xe41e, 0x1174, 0xe161, 0x03e1, 0x155b, 0xe004, ++ 0x06db, 0xb616, 0xcf04, 0xb673, 0x4f91, 0xcc45, 0xe162, 0x03a0, ++ 0xe184, 0x0a30, 0x1092, 0x2692, 0xcf0a, 0xe190, 0xcb14, 0x4891, ++ 0x4e91, 0xe41e, 0x1186, 0xe42e, 0xb80c, 0xa140, 0xe42d, 0xe42a, ++ 0x3429, 0x5729, 0x0d2a, 0xf030, 0xe046, 0xe046, 0xe042, 0xe42e, ++ 0xba40, 0xe016, 0xe42a, 0xa200, 0x4e3c, 0xba41, 0x4f3d, 0xba41, ++ 0xf0ab, 0xae02, 0x043d, 0x153c, 0xa003, 0x4f3c, 0xa119, 0xf765, ++ 0xe16b, 0xe42e, 0xa203, 0x353c, 0xe042, 0x153d, 0xe42b, 0xe012, ++ 0xe42e, 0xe41e, 0x1174, 0xa200, 0xcf04, 0xcf08, 0xe161, 0x03e1, ++ 0x4e91, 0x4e91, 0x4e91, 0xe41e, 0x1186, 0xe42e, 0xe41e, 0x0b63, ++ 0xba2e, 0xa102, 0xf108, 0x146d, 0xf278, 0xba7e, 0xe002, 0x013f, ++ 0xf780, 0xe000, 0x001f, 0xf754, 0xe41e, 0x0b98, 0xf128, 0xe41e, ++ 0x0b63, 0xf6fe, 0x146d, 0xf188, 0xba2a, 0xa140, 0xf088, 0xba6a, ++ 0xe41e, 0x0cac, 0xf0e8, 0xe41e, 0x0b63, 0xf63e, 0xba4e, 0xf61e, ++ 0xa200, 0x4e30, 0x4e34, 0x4e35, 0x4e36, 0x4e37, 0xa202, 0xe42e, ++ 0xa202, 0x4e30, 0xe42e, 0xa200, 0xe42e, 0xe41e, 0x0b63, 0xc001, ++ 0x1408, 0xc000, 0xf068, 0xe41e, 0x13e5, 0xf03a, 0xa200, 0xe42e, ++ 0xc001, 0x1408, 0xc000, 0xf0ba, 0xc874, 0xc001, 0x130a, 0x270b, ++ 0xc000, 0xae07, 0xe045, 0xf031, 0xa200, 0xe42e, 0xe41e, 0x0b63, ++ 0xba2e, 0xa102, 0xf03a, 0xba4e, 0xf63e, 0xba7e, 0x4e04, 0xe002, ++ 0x01b0, 0xf048, 0xe41e, 0x0b68, 0xf5be, 0x1404, 0xe002, 0x01b5, ++ 0xf058, 0xe41e, 0x0b70, 0xe40e, 0x0a97, 0x1404, 0xe002, 0x0120, ++ 0xf084, 0xe002, 0x001f, 0xf050, 0xe41e, 0x0b98, 0xe40e, 0x0a97, ++ 0x1404, 0xe002, 0x01b3, 0xf0e8, 0xe41e, 0x0c3a, 0xe40e, 0x0a97, ++ 0x1404, 0xe002, 0x0100, 0xf064, 0xe002, 0x001f, 0xf030, 0xe40e, ++ 0x0a97, 0x1404, 0xe002, 0x01b6, 0xe408, 0x0a97, 0xe41e, 0x0c43, ++ 0xf03a, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xe41e, 0x0b63, 0xba2a, ++ 0xa140, 0xf03a, 0xba4e, 0xf7ae, 0xba6a, 0xe41e, 0x0cac, 0xf76a, ++ 0xa202, 0xe42e, 0xba5e, 0x1461, 0xa120, 0x4e48, 0x5648, 0x1452, ++ 0xe41e, 0x0dd4, 0x4e48, 0x5648, 0x4e01, 0xba48, 0x4e27, 0xba40, ++ 0xe40a, 0x0b2e, 0xba40, 0xf7f8, 0xba40, 0xe40a, 0x0b2e, 0x1620, ++ 0xe41e, 0x0dd4, 0x4e48, 0x5648, 0x4e2b, 0xba40, 0xe40a, 0x0b2e, ++ 0xba42, 0x4e24, 0x4e2e, 0xba44, 0xe000, 0x02c0, 0xe09e, 0x1487, ++ 0x4e26, 0x1424, 0xf0ca, 0xba44, 0x4e28, 0xe0c2, 0x0078, 0xcf0e, ++ 0xa102, 0x4e29, 0xa202, 0x3429, 0xa102, 0x4e2a, 0x1401, 0xe42e, ++ 0x4e05, 0xf028, 0xba60, 0xba40, 0xf16a, 0x1452, 0xe41e, 0x0dd4, ++ 0x4e48, 0x5748, 0x4f01, 0xa116, 0xf036, 0xba40, 0xf0ca, 0x1405, ++ 0xf038, 0xba48, 0x4e27, 0xba40, 0xf06a, 0x1405, 0xf028, 0xba42, ++ 0x1401, 0xe42e, 0xa2fe, 0xe42e, 0x1452, 0xe41e, 0x0dd4, 0x4e48, ++ 0x5648, 0xe41e, 0x0b63, 0x5e61, 0xa102, 0xf088, 0xba5e, 0x1461, ++ 0xa120, 0x4e6c, 0x566c, 0x5648, 0xe42e, 0xba2c, 0xf038, 0x1452, ++ 0xe42e, 0xba4e, 0xf71e, 0xc864, 0xa80e, 0x4e49, 0x5649, 0xe42e, ++ 0xba4e, 0xa102, 0xe424, 0xa104, 0xe420, 0xe41e, 0x0daa, 0xe42e, ++ 0xba40, 0xf08a, 0xba46, 0xa102, 0xe424, 0xa102, 0xe420, 0xba46, ++ 0xe42a, 0xba46, 0xa102, 0xe428, 0xba40, 0xf08a, 0xba44, 0xba40, ++ 0xba40, 0xf04a, 0xba4e, 0xba4e, 0xba4e, 0xe41e, 0x0db6, 0xe42a, ++ 0xe41e, 0x0daa, 0xe41e, 0x0db6, 0xe42a, 0xba7e, 0xe42e, 0xa201, ++ 0xba4e, 0xa003, 0xf05a, 0xe04a, 0xa180, 0xf022, 0xf7ae, 0xe42e, ++ 0xa202, 0x4e00, 0xba40, 0xba4e, 0xba40, 0xf0ba, 0xba46, 0xa102, ++ 0xe404, 0x0c38, 0xa102, 0xe400, 0x0c38, 0xa004, 0x4e00, 0xba44, ++ 0xba46, 0xa11e, 0xf078, 0xba4e, 0xe40a, 0x0c38, 0xba4e, 0xe40a, ++ 0x0c38, 0xba40, 0xf1da, 0xba42, 0xa102, 0xe408, 0x0c38, 0xba40, ++ 0xba40, 0xf16a, 0xba5c, 0xba40, 0xe40a, 0x0c38, 0xba5c, 0xba40, ++ 0xe40a, 0x0c38, 0xba5c, 0xba40, 0xe40a, 0x0c38, 0xba44, 0xba54, ++ 0xba40, 0xe40a, 0x0c38, 0xba5c, 0xba40, 0xe40a, 0x0c38, 0xba42, ++ 0xe408, 0x0c38, 0xba40, 0xe40a, 0x0c38, 0xa202, 0x4e21, 0xba5e, ++ 0xe40a, 0x0c38, 0x4e20, 0xe0c2, 0x0076, 0xba40, 0xe40a, 0x0c38, ++ 0xba40, 0xe40a, 0x0beb, 0x1620, 0xe41e, 0x0dd4, 0x4e48, 0x5648, ++ 0xe40a, 0x0c38, 0x4e21, 0xba40, 0xe40a, 0x0c38, 0xba58, 0x4e07, ++ 0xa01e, 0xaf08, 0x4e50, 0xba40, 0xe40a, 0x0c38, 0xba58, 0x4e0e, ++ 0xa01e, 0xaf08, 0x4e51, 0xba40, 0xe40a, 0x0c38, 0xba40, 0xe408, ++ 0x0c38, 0xba40, 0xe40a, 0x0c38, 0x5600, 0xe408, 0x0c38, 0xba40, ++ 0xe408, 0x0c38, 0xba40, 0xf07a, 0xba40, 0xe418, 0x0b8f, 0xba40, ++ 0xe418, 0x0b8f, 0x1400, 0xa102, 0xe40a, 0x0c19, 0xba40, 0xe408, ++ 0x0c38, 0xba40, 0xe40a, 0x0c38, 0xba40, 0xba40, 0x4e22, 0xe40a, ++ 0x0c22, 0xba40, 0x4e23, 0x1400, 0xa102, 0xe40a, 0x0c29, 0xba40, ++ 0xba40, 0x4e2c, 0xba40, 0xe408, 0x0c38, 0xe41e, 0x0db6, 0xe42a, ++ 0xe41e, 0x0daa, 0x8250, 0x8151, 0xe018, 0x4e52, 0xa202, 0xe42e, ++ 0xa200, 0xe42e, 0xba62, 0xba40, 0xba40, 0xe41e, 0x0db6, 0xe42a, ++ 0xe41e, 0x0daa, 0xe42e, 0xa201, 0xc001, 0x4f17, 0xc000, 0xba42, ++ 0x4e24, 0x4e2e, 0xa104, 0xe402, 0x0caa, 0xba40, 0xb431, 0xf7e8, ++ 0xc001, 0x4f17, 0xc000, 0xba40, 0xe40a, 0x0caa, 0x1620, 0xe41e, ++ 0x0dd4, 0xa102, 0xf022, 0xa200, 0xa002, 0x4e48, 0x5648, 0x486c, ++ 0x4e2b, 0xc001, 0x1412, 0xe0c2, 0x007a, 0x0417, 0x4e12, 0x8212, ++ 0xc000, 0x1620, 0xe41e, 0x0dde, 0x116c, 0x272b, 0xe042, 0xc001, ++ 0x4813, 0x4e14, 0x1115, 0x2716, 0xe046, 0xe0c2, 0x0079, 0x1013, ++ 0x2614, 0x4815, 0x4e16, 0xe0c2, 0x007b, 0xc000, 0xba40, 0xe40a, ++ 0x0caa, 0xba40, 0x4e2d, 0xe40a, 0x0ca5, 0x1424, 0xa102, 0xf038, ++ 0xba40, 0x4e25, 0x142c, 0xf04a, 0xba40, 0xe408, 0x0caa, 0xba44, ++ 0xe000, 0x02c0, 0xe09e, 0x1487, 0x4e26, 0xba48, 0x4e27, 0x1424, ++ 0xe40a, 0x0ca5, 0xba44, 0x4e28, 0xcf0e, 0xe40a, 0x0caa, 0xa102, ++ 0x4e29, 0xa202, 0x3429, 0xa102, 0x4e2a, 0x1528, 0xe0c3, 0x0078, ++ 0xa202, 0xe42e, 0xa200, 0xe42e, 0xba4e, 0x4e2b, 0xba40, 0xe40a, ++ 0x0da8, 0xba40, 0xe408, 0x0da8, 0xba40, 0xba40, 0xba40, 0xba44, ++ 0x4e02, 0xa10e, 0xe40a, 0x0cd7, 0xba40, 0x4e24, 0x4e2e, 0xba40, ++ 0x4e39, 0xba44, 0xe408, 0x0da8, 0xba48, 0x4e27, 0xba40, 0xe408, ++ 0x0da8, 0xe41e, 0x0dc1, 0xe40a, 0x0da8, 0xa200, 0x4e34, 0x4e35, ++ 0x4e36, 0x4e37, 0x4e3a, 0x4e25, 0x4e38, 0xe40e, 0x0d60, 0xa202, ++ 0x4e3a, 0xa200, 0x4e02, 0xba44, 0x4e03, 0xa102, 0xe400, 0x0da8, ++ 0xe404, 0x0cff, 0xba44, 0x4e02, 0xa10c, 0xe418, 0x0dc1, 0xba40, ++ 0x4e38, 0xba40, 0x4e39, 0xba42, 0xe408, 0x0da8, 0xba40, 0x4e34, ++ 0xba40, 0x4e35, 0xba40, 0x4e36, 0xba44, 0xe408, 0x0da8, 0xba40, ++ 0x4e37, 0xba40, 0xe40a, 0x0da8, 0xba44, 0xe408, 0x0da8, 0xba44, ++ 0xa102, 0xe400, 0x0da8, 0xa002, 0x4e24, 0x4e2e, 0xba42, 0xe408, ++ 0x0da8, 0xba40, 0x4e25, 0xba44, 0xa102, 0xe408, 0x0da8, 0xba40, ++ 0xe408, 0x0da8, 0x1402, 0xa10c, 0xf228, 0x1403, 0xf20a, 0xba46, ++ 0xa10a, 0xe400, 0x0da8, 0xba50, 0xa002, 0xae04, 0x4e07, 0xaf04, ++ 0xaf04, 0x4e50, 0x4e32, 0xba40, 0xe40a, 0x0da8, 0xba50, 0xae04, ++ 0x4e0e, 0xaf04, 0xaf04, 0x4e51, 0x4e31, 0xa132, 0xe406, 0x0d36, ++ 0x1432, 0xae02, 0x4e32, 0x1431, 0xaf02, 0x4e31, 0x1438, 0x2203, ++ 0xf11a, 0xba40, 0xe000, 0x03e8, 0xba4d, 0xe40b, 0x0da8, 0x4e21, ++ 0x4f20, 0xe004, 0x1b77, 0xae20, 0xe00a, 0x0040, 0xc70f, 0x3c20, ++ 0x4e20, 0x1438, 0xf05a, 0xba42, 0xae10, 0x262b, 0x4e2b, 0x1439, ++ 0x2203, 0xf07a, 0xba40, 0x4e3b, 0xf048, 0xba40, 0xe40a, 0x0da8, ++ 0x1436, 0x2203, 0xf04a, 0xba42, 0xe408, 0x0da8, 0xba48, 0x4e27, ++ 0xba40, 0xf03a, 0xba4e, 0xf7de, 0x8250, 0x8151, 0xe018, 0x4e52, ++ 0x1436, 0xf05a, 0xa202, 0xe41e, 0x0b30, 0xf3b8, 0x1438, 0xf078, ++ 0xe004, 0x03e9, 0x4e21, 0xe004, 0x7530, 0x4e20, 0xa200, 0x4e22, ++ 0x4e23, 0xa202, 0x4e28, 0x4e2d, 0xcf0e, 0xa200, 0x4e29, 0x4e2a, ++ 0xe167, 0x02c0, 0x1487, 0x4e26, 0x1439, 0xf1fa, 0x143a, 0xf048, ++ 0xa200, 0xcf0e, 0xf1ae, 0x143b, 0xf16a, 0xa204, 0x1550, 0xa12d, ++ 0xf057, 0xa002, 0xa12d, 0xf027, 0xa002, 0x4e6c, 0xa204, 0x1551, ++ 0xa125, 0xf057, 0xa002, 0xa125, 0xf027, 0xa002, 0xae06, 0x266c, ++ 0xcf0e, 0xf03e, 0xd187, 0x0000, 0xa202, 0xe42e, 0xa202, 0xe42e, ++ 0xa200, 0xe42e, 0xba3e, 0xe002, 0x01b2, 0xe428, 0xba7e, 0xba2e, ++ 0xa102, 0xe42a, 0x146d, 0xe428, 0xba4e, 0xf7ae, 0xe41e, 0x0b63, ++ 0xba2e, 0xa102, 0xe016, 0xe428, 0xba4e, 0x146d, 0xf028, 0xf79e, ++ 0xe42e, 0x1402, 0xae04, 0xe000, 0x02a0, 0xe09e, 0x1497, 0x4e07, ++ 0xaf08, 0x4e50, 0x1497, 0x4e0e, 0xaf08, 0x4e51, 0x1497, 0x4e32, ++ 0x1487, 0x4e31, 0xe01a, 0xe42e, 0xa102, 0xa201, 0xf04a, 0xaf02, ++ 0xa003, 0xf7e8, 0xe04a, 0xf028, 0xa202, 0xe42e, 0xae02, 0xc001, ++ 0x4818, 0xe008, 0xffff, 0xaf02, 0x4e19, 0x8118, 0xe018, 0xae1e, ++ 0x8119, 0xc000, 0xe01c, 0xe42e, 0xa200, 0x4e4a, 0xe42e, 0xe004, ++ 0x0080, 0xe0c2, 0x0094, 0xc001, 0x1406, 0xf04a, 0x1000, 0x2601, ++ 0xf08e, 0xc000, 0xe0c0, 0x0041, 0xe005, 0x0320, 0xae11, 0xe042, ++ 0xc000, 0xe0c2, 0x0089, 0x1473, 0x1535, 0xb612, 0x4e73, 0xe0c0, ++ 0x0044, 0x4600, 0xe0c0, 0x0067, 0xe0c2, 0x00ff, 0x1470, 0xe0c2, ++ 0x009b, 0xe0c2, 0x009f, 0xe0c2, 0x018b, 0x1435, 0x2673, 0x4e01, ++ 0xa200, 0xe0c2, 0x0100, 0x1451, 0xae20, 0x2650, 0xae08, 0xe0c2, ++ 0x0084, 0x1400, 0xae04, 0x262e, 0xae10, 0x1537, 0xae03, 0x2736, ++ 0xae03, 0x2735, 0xae03, 0x2734, 0xae05, 0x2730, 0xe056, 0xe0c2, ++ 0x0080, 0x1401, 0xae02, 0xe0c1, 0x0060, 0xe009, 0x001f, 0xae0d, ++ 0xe056, 0x1573, 0xae19, 0xe056, 0x1535, 0xae1b, 0xe056, 0xe0c2, ++ 0x00fa, 0x1401, 0xae0a, 0xe0c1, 0x0060, 0xaf09, 0x4f72, 0xf04b, ++ 0xe0c1, 0x0060, 0xa81f, 0xe056, 0xe0c2, 0x00e7, 0xe0c0, 0x0061, ++ 0xe0c2, 0x00fc, 0xe0c0, 0x0062, 0xe0c2, 0x00fd, 0xe0c0, 0x0063, ++ 0xe0c2, 0x00fe, 0x1425, 0xae06, 0x2600, 0xae20, 0x2670, 0xe0c2, ++ 0x0282, 0x1450, 0xae20, 0x2651, 0xae08, 0xe0c2, 0x0283, 0x1450, ++ 0xae0c, 0x2651, 0xe0c2, 0x0183, 0x1473, 0xae02, 0x2601, 0xe0c2, ++ 0x018d, 0x1401, 0xae04, 0xa902, 0xae02, 0x2601, 0xae02, 0x2601, ++ 0xae02, 0xe0c2, 0x0182, 0xa202, 0xae3e, 0xa906, 0xe0c2, 0x00ec, ++ 0xa200, 0xe0c2, 0x0102, 0xa202, 0xe0c2, 0x0102, 0xa204, 0xe0c2, ++ 0x0102, 0x824a, 0xc786, 0xe018, 0xe000, 0x03f0, 0xe09e, 0x1097, ++ 0x2697, 0xe0c2, 0x009c, 0xe0c2, 0x0188, 0x1097, 0x2697, 0xe0c2, ++ 0x009d, 0xe0c2, 0x0189, 0x1097, 0x2697, 0xe0c2, 0x009e, 0xe0c2, ++ 0x018a, 0x1473, 0xf0da, 0xe0c0, 0x0064, 0xe0c2, 0x0188, 0xe0c0, ++ 0x0065, 0xe0c2, 0x0189, 0xe0c0, 0x0066, 0xe0c2, 0x018a, 0x824b, ++ 0xc786, 0xe018, 0xe000, 0x03f0, 0xe09e, 0x1097, 0x2697, 0xe0c2, ++ 0x02c0, 0x1097, 0x2697, 0xe0c2, 0x02c1, 0x1097, 0x2697, 0xe0c2, ++ 0x02c2, 0x144a, 0xe0c2, 0x0071, 0xe0c2, 0x0077, 0x4e4b, 0xa002, ++ 0x4e4a, 0x0c4d, 0xf028, 0x4e4a, 0xa200, 0x4e71, 0xa200, 0x4e56, ++ 0x4e57, 0xa200, 0xe0c2, 0x00a1, 0xa200, 0x4e69, 0xa202, 0x4e78, ++ 0xe42e, 0x1453, 0xe418, 0x1114, 0x1458, 0xe41a, 0x106e, 0x1454, ++ 0xae20, 0x2655, 0xe0c2, 0x0284, 0x1478, 0xae04, 0x2658, 0xaa0a, ++ 0xe0c2, 0x0280, 0x1471, 0xe0c2, 0x0102, 0xe0c2, 0x0101, 0x1435, ++ 0xe418, 0x10a6, 0x1473, 0xe418, 0x10d6, 0xe41e, 0x107e, 0x147c, ++ 0xe0c2, 0x0082, 0xa202, 0x1553, 0xb616, 0x4e77, 0xa103, 0xb616, ++ 0x4e74, 0xa103, 0xb616, 0x4e75, 0xa103, 0xb616, 0x4e05, 0xa103, ++ 0xb616, 0x4e06, 0x1435, 0x1573, 0xf038, 0xf049, 0xf04e, 0x1475, ++ 0xf02e, 0x1405, 0x4e00, 0x1435, 0x1573, 0xf058, 0x1472, 0xf059, ++ 0xf068, 0xf06e, 0x1405, 0xf04e, 0x1406, 0xf02e, 0x1475, 0x4e01, ++ 0x1435, 0x1573, 0xf038, 0xf049, 0xf04e, 0x1405, 0xf02e, 0x1406, ++ 0x4e04, 0x1573, 0x1472, 0x2205, 0xf02b, 0x2206, 0x4e02, 0x1435, ++ 0x2673, 0xe016, 0x2272, 0x2275, 0x4e03, 0xe418, 0x1105, 0x1404, ++ 0xae02, 0x2602, 0xae02, 0x2603, 0xae18, 0x2676, 0xe0c2, 0x00e6, ++ 0x1401, 0xae02, 0x1578, 0xe017, 0x2377, 0xe056, 0xae02, 0x2600, ++ 0xae02, 0x1558, 0xe017, 0xe056, 0xae04, 0x2675, 0xae04, 0x2674, ++ 0xae02, 0x1530, 0xe017, 0x2734, 0x2377, 0xe056, 0xae02, 0xe0c2, ++ 0x0083, 0xa202, 0xe0c2, 0x0093, 0xe42e, 0xe41e, 0x111a, 0x147b, ++ 0x4e7c, 0x1458, 0xae14, 0x265d, 0x4e7b, 0x1458, 0x4e78, 0xe0c0, ++ 0x0184, 0x4e76, 0xe42e, 0xe41e, 0x1114, 0x1478, 0xe016, 0xae04, ++ 0xe0c2, 0x0280, 0x1471, 0xe0c2, 0x0102, 0xe0c2, 0x0101, 0x1435, ++ 0xe418, 0x10a6, 0x1473, 0xe418, 0x10d6, 0xe41e, 0x107e, 0x1435, ++ 0x2673, 0x4e00, 0x1435, 0x2673, 0x2672, 0x4e01, 0x1435, 0x2673, ++ 0x4e04, 0x1472, 0x4e02, 0x1435, 0x2673, 0xe016, 0x2272, 0x4e03, ++ 0x1403, 0xe418, 0x1105, 0x1404, 0xae02, 0x2602, 0xae02, 0x2603, ++ 0xae18, 0x2676, 0xe0c2, 0x00e6, 0x147c, 0xe0c2, 0x0082, 0x1401, ++ 0xae02, 0x1578, 0xe017, 0x2377, 0xe056, 0xae02, 0x2600, 0xae0e, ++ 0xa928, 0x1530, 0xe017, 0x2734, 0xae03, 0xe056, 0xe0c2, 0x0083, ++ 0xa202, 0xe0c2, 0x0093, 0xe41e, 0x0f5d, 0xe42e, 0xe41e, 0x1114, ++ 0x1471, 0xe0c2, 0x0102, 0xe0c2, 0x0101, 0x1435, 0xe418, 0x10a6, ++ 0x1473, 0xe418, 0x10d6, 0x1435, 0x2673, 0x4e00, 0x1435, 0x2673, ++ 0x2672, 0x4e01, 0x1435, 0x2673, 0x4e04, 0x1472, 0x4e02, 0x1435, ++ 0x2673, 0xe016, 0x2272, 0x4e03, 0x1403, 0xe418, 0x1105, 0x1404, ++ 0xae02, 0x2602, 0xae02, 0x2603, 0xae18, 0x2676, 0xe0c2, 0x00e6, ++ 0x147c, 0xe0c2, 0x0082, 0x1401, 0xae04, 0x2600, 0xae0e, 0xa928, ++ 0xe0c2, 0x0083, 0xa202, 0xe0c2, 0x0093, 0xe41e, 0x0f5d, 0xe42e, ++ 0xe41e, 0x1114, 0x1471, 0xe0c2, 0x0102, 0xe0c2, 0x0101, 0x1435, ++ 0xe418, 0x10a6, 0x1473, 0xe418, 0x10d6, 0x1435, 0x2673, 0x4e00, ++ 0x1435, 0x2673, 0x2672, 0x4e01, 0x1435, 0x2673, 0x4e04, 0x1472, ++ 0x4e02, 0x1435, 0x2673, 0xe016, 0x2272, 0x4e03, 0x1403, 0xe418, ++ 0x1105, 0x1404, 0xae02, 0x2602, 0xae02, 0x2603, 0xae18, 0x2676, ++ 0xe0c2, 0x00e6, 0x1401, 0xae04, 0x2600, 0xae0e, 0xa920, 0xe0c2, ++ 0x0083, 0xa202, 0xe0c2, 0x0093, 0xe41e, 0x0f5d, 0xe42e, 0xe41e, ++ 0x1114, 0x1471, 0xe0c2, 0x0102, 0xe0c2, 0x0101, 0x1473, 0xe418, ++ 0x10d6, 0x1473, 0x4e00, 0x1435, 0x2673, 0x2672, 0x4e01, 0x1435, ++ 0x2673, 0x4e04, 0x1472, 0x4e02, 0xa200, 0x4e03, 0x1404, 0xae02, ++ 0x2602, 0xae02, 0x2603, 0xae18, 0x2676, 0xe0c2, 0x00e6, 0x1401, ++ 0xae04, 0x2600, 0xae0e, 0xe0c2, 0x0083, 0xa202, 0xe0c2, 0x0093, ++ 0xe41e, 0x0f5d, 0xe42e, 0xe41e, 0x1114, 0x1471, 0xe0c2, 0x0102, ++ 0xe0c2, 0x0101, 0x1473, 0x2272, 0x4e02, 0x1473, 0xae02, 0x2602, ++ 0xae1a, 0x2676, 0xe0c2, 0x00e6, 0xe004, 0x0200, 0xe0c2, 0x0083, ++ 0xa202, 0xe0c2, 0x0093, 0xe41e, 0x1114, 0xe42e, 0xcb04, 0xe0c2, ++ 0x0285, 0xe161, 0x03e1, 0xe162, 0x02f0, 0xc420, 0x8891, 0x0022, ++ 0xe184, 0x107c, 0x1091, 0x2691, 0x9f32, 0xe42e, 0x1479, 0xe0c2, ++ 0x008a, 0x1469, 0x4e79, 0x1434, 0x1530, 0xf0d8, 0xe429, 0x147a, ++ 0xe0c2, 0x0088, 0x145d, 0xae04, 0x2658, 0xae06, 0x265c, 0xae02, ++ 0x4e7a, 0xe42e, 0x147d, 0xe0c2, 0x0104, 0x145c, 0xaf02, 0x2a5c, ++ 0x1558, 0xb616, 0x4e7d, 0x147a, 0xe0c2, 0x0088, 0x145c, 0xae0a, ++ 0x265d, 0xae04, 0x2658, 0xae08, 0x4e7a, 0xe42e, 0x1567, 0x1466, ++ 0x4e67, 0x1465, 0x4e66, 0x1459, 0xe016, 0xae0a, 0x265d, 0x4e65, ++ 0x1453, 0xa106, 0xe424, 0xe004, 0x03a8, 0x0456, 0xe09c, 0x1437, ++ 0xae0c, 0x2664, 0xae0c, 0x2663, 0xae0c, 0x2686, 0xae0c, 0xe056, ++ 0xe0c2, 0x018c, 0x1486, 0x4e64, 0x4f86, 0x4f63, 0x1456, 0xae0c, ++ 0x2657, 0xe0c2, 0x0184, 0x1456, 0xa002, 0x4e56, 0x0c50, 0xe408, ++ 0x10d5, 0x4e56, 0x1457, 0xa002, 0x4e57, 0xe42e, 0x1568, 0x1467, ++ 0x4e68, 0x1466, 0x4e67, 0x1465, 0x4e66, 0xa202, 0xae0a, 0x265d, ++ 0x4e65, 0x1453, 0xa108, 0xe424, 0xe004, 0x03a8, 0x0456, 0xe09c, ++ 0x1464, 0xae0c, 0x2663, 0xae0c, 0x2686, 0xae0c, 0xe056, 0xe0c2, ++ 0x018c, 0x1486, 0x4e64, 0x4f86, 0x4f63, 0x1456, 0xae0c, 0x2657, ++ 0xe0c2, 0x0184, 0x1456, 0xa002, 0x4e56, 0x0c50, 0xe408, 0x1104, ++ 0x4e56, 0x1457, 0xa002, 0x4e57, 0xe42e, 0x1456, 0xae0c, 0x2657, ++ 0x4e76, 0x1456, 0xa002, 0x4e56, 0x0c50, 0xe408, 0x1113, 0x4e56, ++ 0x1457, 0xa002, 0x4e57, 0xe42e, 0xe0c0, 0x0095, 0xf7ea, 0xe0c2, ++ 0x0095, 0xe42e, 0x1571, 0xa105, 0x1471, 0xa002, 0xb616, 0x4e71, ++ 0xe42e, 0xe161, 0x0268, 0xd022, 0x002d, 0xa2fc, 0x4e6c, 0xe184, ++ 0x112b, 0x1481, 0x226c, 0x4e91, 0xca40, 0x226c, 0xce40, 0xca46, ++ 0x226c, 0xce46, 0xe42e, 0xe004, 0x0268, 0x4e6a, 0xe004, 0x0100, ++ 0x4e6b, 0xa2fd, 0xca40, 0xe052, 0xce40, 0xca46, 0xe052, 0xce46, ++ 0xe42e, 0x1454, 0xe41a, 0x1133, 0x146a, 0xe09c, 0x1496, 0xce42, ++ 0x1486, 0xce44, 0xca4a, 0xcf34, 0xe42e, 0x146a, 0xe09c, 0x1458, ++ 0xae02, 0xa902, 0xce48, 0x4e96, 0xce40, 0xca42, 0xce46, 0xe08c, ++ 0x4e6a, 0x1454, 0xa002, 0x4e54, 0x0c50, 0xe428, 0xa200, 0x4e54, ++ 0x1455, 0xa002, 0x4e55, 0x0c51, 0xe42e, 0x1524, 0xa200, 0xe42b, ++ 0xcf20, 0xcf22, 0xcf24, 0xcf26, 0x146b, 0xe09c, 0xa200, 0xc707, ++ 0x4e96, 0xe08c, 0x4e6b, 0xe42e, 0x146b, 0xe09c, 0x1096, 0x2696, ++ 0xcf28, 0x1096, 0x2696, 0xcf2a, 0x1096, 0x2696, 0xcf2c, 0x1096, ++ 0x2696, 0xcf2e, 0x1096, 0x2696, 0xcf30, 0xe42e, 0x146b, 0xe09c, ++ 0xcb28, 0x4896, 0x4e96, 0xcb2a, 0x4896, 0x4e96, 0xcb2c, 0x4896, ++ 0x4e96, 0xcb2e, 0x4896, 0x4e96, 0xe08c, 0x4e6b, 0xe42e, 0xa200, ++ 0xc001, 0x4e09, 0xc000, 0x486f, 0x4e13, 0x4e6e, 0xe0c1, 0x006a, ++ 0xe0c0, 0x006c, 0xa806, 0xe041, 0xc001, 0x490a, 0x4f0b, 0xc000, ++ 0xc001, 0x140c, 0xc000, 0xf05a, 0xe0c0, 0x006b, 0x4810, 0x4e11, ++ 0x1010, 0x2611, 0xe042, 0xe0c1, 0x005a, 0xae03, 0xe001, 0x0049, ++ 0xe093, 0x9f01, 0xe004, 0xffff, 0x4e12, 0xe41e, 0x11e2, 0xe41e, ++ 0x12fe, 0xe12c, 0xe41e, 0x122b, 0xe128, 0xe42e, 0xa200, 0x4e3e, ++ 0x4e3f, 0x4e1e, 0x4e1f, 0x486f, 0x4e13, 0xe0c0, 0x0060, 0x4810, ++ 0x4e11, 0xe0c0, 0x0061, 0xae04, 0x486e, 0x4e12, 0xe41e, 0x11e2, ++ 0xe41e, 0x12fe, 0xe12c, 0xd071, 0x002a, 0xe181, 0xe41e, 0x122b, ++ 0xe128, 0xe42e, 0xe12c, 0xd030, 0x0000, 0xd032, 0x0000, 0xd033, ++ 0x0000, 0xd034, 0x0000, 0xd035, 0x007f, 0xd036, 0x0000, 0xd037, ++ 0x0000, 0xe42e, 0xe12d, 0xd030, 0x0000, 0xd032, 0x0000, 0xd033, ++ 0x0080, 0xd034, 0x0080, 0xd035, 0x00bf, 0xd036, 0x0080, 0xd037, ++ 0x0000, 0xe42e, 0xe12e, 0xd030, 0x0000, 0xd032, 0x0000, 0xd033, ++ 0x00c0, 0xd034, 0x00c0, 0xd035, 0x00ff, 0xd036, 0x00c0, 0xd037, ++ 0x0000, 0xe42e, 0xc872, 0xc000, 0xf06a, 0xa102, 0xf07a, 0xa102, ++ 0xf0ca, 0xe470, 0xe41e, 0x122b, 0xe470, 0x1416, 0xe41a, 0x12b5, ++ 0x1416, 0xe418, 0x1271, 0xe470, 0x1417, 0xe41a, 0x12d9, 0x1417, ++ 0xe418, 0x1293, 0xe470, 0xd111, 0x0000, 0xe082, 0x4e14, 0xe0c0, ++ 0x005a, 0xae02, 0xe000, 0x0048, 0xe092, 0xe41e, 0x130c, 0x146d, ++ 0xf368, 0x1010, 0x2611, 0x136f, 0x2713, 0xae11, 0xe042, 0xce20, ++ 0xd112, 0x0100, 0xa226, 0xe0c1, 0x0043, 0xa803, 0xf029, 0xa22e, ++ 0xce26, 0xca28, 0xf7f8, 0xc001, 0x1408, 0xc000, 0xf0d8, 0xe41e, ++ 0x136f, 0x154e, 0xa103, 0xf1b1, 0xe004, 0x1000, 0xf035, 0x141c, ++ 0xae06, 0xe41e, 0x13df, 0x126f, 0x2613, 0xe000, 0x0002, 0x486f, ++ 0x4e13, 0x136e, 0x2712, 0xe046, 0xf034, 0x486f, 0x4e13, 0x1010, ++ 0x2611, 0x136f, 0x2713, 0xae11, 0xe042, 0x9f01, 0x1414, 0xe092, ++ 0xe42e, 0xe0c0, 0x0047, 0xf04a, 0x107e, 0x2618, 0xf06e, 0xe0c0, ++ 0x0041, 0x1518, 0xae11, 0xe042, 0xce20, 0xd111, 0x0100, 0xd112, ++ 0x0080, 0xd113, 0x0013, 0xca28, 0xf7f8, 0xe0c0, 0x0047, 0xf07a, ++ 0x107e, 0x2618, 0xe000, 0x0100, 0x487e, 0xf04e, 0x1418, 0xe000, ++ 0x0001, 0x4e18, 0xe42e, 0xe0c0, 0x0047, 0xf04a, 0x107f, 0x2619, ++ 0xf06e, 0xe0c0, 0x0041, 0x1519, 0xae11, 0xe042, 0xce20, 0xd111, ++ 0x0180, 0xd112, 0x0080, 0xd113, 0x0013, 0xca28, 0xf7f8, 0xe0c0, ++ 0x0047, 0xf07a, 0x107f, 0x2619, 0xe000, 0x0100, 0x487f, 0xf04e, ++ 0x1419, 0xe000, 0x0001, 0x4e19, 0xe42e, 0xe0c0, 0x0047, 0xf04a, ++ 0x107e, 0x2618, 0xf06e, 0xe0c0, 0x0041, 0x1518, 0xae11, 0xe042, ++ 0xce20, 0xd111, 0x0100, 0xd112, 0x0080, 0xd113, 0x0012, 0xca28, ++ 0xf7f8, 0xe0c0, 0x0047, 0xf07a, 0x107e, 0x2618, 0xe000, 0x0100, ++ 0x487e, 0xf04e, 0x1418, 0xe000, 0x0001, 0x4e18, 0xa202, 0x4e1a, ++ 0xe42e, 0xe0c0, 0x0047, 0xf04a, 0x107f, 0x2619, 0xf06e, 0xe0c0, ++ 0x0041, 0x1519, 0xae11, 0xe042, 0xce20, 0xd111, 0x0180, 0xd112, ++ 0x0080, 0xd113, 0x0012, 0xca28, 0xe408, 0x12eb, 0xe0c0, 0x0047, ++ 0xf07a, 0x107f, 0x2619, 0xe000, 0x0100, 0x487f, 0xf04e, 0x1419, ++ 0xe000, 0x0001, 0x4e19, 0xa202, 0x4e1b, 0xe42e, 0x1010, 0x2611, ++ 0x136f, 0x2713, 0xae11, 0xe042, 0xe0c1, 0x005a, 0xae03, 0xe001, ++ 0x0048, 0xe093, 0x9f01, 0xe42e, 0xe0c1, 0x0043, 0xa805, 0xe429, ++ 0xc001, 0x1408, 0xc000, 0xf0aa, 0xe0c0, 0x0059, 0xa102, 0xf068, ++ 0xc001, 0x1409, 0xc000, 0xf02a, 0xf27e, 0xa200, 0x4e15, 0xc001, ++ 0x1408, 0xc000, 0xf038, 0x144e, 0xf358, 0x1010, 0x2611, 0x136f, ++ 0x2713, 0xae11, 0xe042, 0x8091, 0x9e89, 0xe045, 0xf053, 0x126e, ++ 0x2612, 0xae10, 0xe041, 0xe003, 0x0200, 0xe423, 0xc001, 0x1408, ++ 0xc000, 0xf0aa, 0xc001, 0x1409, 0xc000, 0xf068, 0xa202, 0xc001, ++ 0x4e09, 0xc000, 0xe42e, 0xe0c0, 0x0059, 0xa102, 0xf068, 0xe0c0, ++ 0x0045, 0x466d, 0x146d, 0xf238, 0xc001, 0x1408, 0xc000, 0xf0d8, ++ 0xe0c0, 0x0059, 0xa106, 0xf098, 0xe0c0, 0x0045, 0xa802, 0xf05a, ++ 0x144e, 0xa002, 0x4e4e, 0xe42e, 0x1415, 0xf488, 0xe0c0, 0x005c, ++ 0xe008, 0x4000, 0xf43a, 0xe0c0, 0x005d, 0xe00a, 0x4000, 0xe0c2, ++ 0x005d, 0xa202, 0xce00, 0x4e15, 0xe40e, 0x1325, 0xe42e, 0x144e, ++ 0xe42a, 0xe085, 0x4f1d, 0xa102, 0xf238, 0x8091, 0x9e09, 0x1110, ++ 0x2711, 0xe046, 0xe008, 0x01ff, 0x4e1c, 0xaf04, 0xe000, 0x0000, ++ 0xe094, 0x141c, 0xe005, 0x0200, 0xe045, 0xa121, 0xf0e3, 0xe41e, ++ 0x13a5, 0xe005, 0x0200, 0x0d1c, 0xe045, 0xe084, 0xcc7a, 0xa200, ++ 0xf12b, 0xcc7c, 0xa109, 0xf7de, 0xe41e, 0x13a5, 0xf03e, 0xe162, ++ 0x0000, 0xe084, 0xcc7a, 0xa200, 0xe005, 0x8000, 0xcc7c, 0xcc7d, ++ 0xcc7c, 0xcc7c, 0x141d, 0xe094, 0xe42e, 0xa806, 0xe42a, 0xa102, ++ 0xf12a, 0xa102, 0xf1da, 0xe084, 0xcc78, 0xcc7a, 0xcc7e, 0xc87c, ++ 0xe005, 0xffff, 0xae21, 0xe00b, 0xff00, 0xe052, 0xcc7c, 0x8092, ++ 0xa202, 0xe42e, 0xe084, 0xcc78, 0xcc7a, 0xcc7e, 0xc87c, 0xe005, ++ 0xff00, 0xae21, 0xe052, 0xcc7c, 0x8092, 0xa206, 0xe42e, 0xe084, ++ 0xcc78, 0xcc7a, 0xcc7e, 0xc87c, 0xe005, 0xffff, 0xae21, 0xe052, ++ 0xcc7c, 0x8092, 0xa204, 0xe42e, 0xc874, 0x111e, 0x271f, 0xe041, ++ 0x491e, 0x4f1f, 0xa201, 0xcc75, 0xe41e, 0x13ef, 0xe42e, 0x113e, ++ 0x273f, 0xe041, 0x493e, 0x4f3f, 0xe42e, 0x144e, 0xe42a, 0x101e, ++ 0x261f, 0x113e, 0x273f, 0xa012, 0xe046, 0xb60c, 0xe42e, 0xe004, ++ 0x4000, 0xae20, 0x111e, 0x271f, 0xe045, 0xe425, 0x113e, 0x273f, ++ 0xe045, 0xe425, 0x493e, 0x4f3f, 0x111e, 0x271f, 0xe045, 0x491e, ++ 0x4f1f, 0xe42e, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe0c0, 0x0040, 0xe0c1, 0x005b, 0xae1d, 0xe042, 0xce20, 0xd111, ++ 0x0000, 0xd112, 0x0800, 0xd113, 0x000b, 0xca28, 0xf7f8, 0xe42e, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0080, 0x0060, 0x0008, 0x0006, ++ 0x00b0, 0x0090, 0x000b, 0x0009, 0x0160, 0x0120, 0x0016, 0x0012, ++ 0x02c0, 0x0240, 0x0058, 0x0012, 0x0580, 0x0480, 0x0160, 0x0012, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0063, 0x000d, 0x000f, 0x0011, 0x0013, 0x0015, 0x0017, 0x0000, ++ 0xffff, 0xfffe, 0x0001, 0x0002, 0x0000, 0x0002, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xfffe, ++ 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, ++ 0xfffe, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd, ++ 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0x0000, 0x0001, 0x0001, 0x0001, ++ 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0002, ++ 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, ++ 0x0002, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, ++ 0x0003, 0x0002, 0x0001, 0xfffb, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe40e, 0x0022, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, ++ 0xe470, 0xe190, 0xe40e, 0x0152, 0xe470, 0xe190, 0xe470, 0xe190, ++ 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, ++ 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, ++ 0xf202, 0x1307, 0xc001, 0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, ++ 0x0008, 0xe0c2, 0x0058, 0xa200, 0xe0c2, 0x005a, 0xa2fe, 0x4e71, ++ 0x4e72, 0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d, 0xce00, 0xf11e, ++ 0xe0c0, 0x005c, 0xe0c1, 0x0059, 0x4f70, 0xa203, 0x3570, 0xe052, ++ 0xf08a, 0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00, ++ 0xe41e, 0x0084, 0xe0c0, 0x005b, 0x0c72, 0xe418, 0x00b2, 0xe0c0, ++ 0x0059, 0xa114, 0xf18a, 0xa102, 0xf1da, 0xe0c0, 0x005a, 0x0c71, ++ 0xe418, 0x00ab, 0xe0c0, 0x0059, 0xae02, 0xe000, 0x0152, 0xc000, ++ 0xe67c, 0xc001, 0xe0c0, 0x005a, 0x4e71, 0xe0c0, 0x005b, 0x4e72, ++ 0xe40e, 0x0038, 0x1471, 0xe412, 0x010d, 0xa202, 0x4e73, 0xe40e, ++ 0x0061, 0xe41e, 0x00c6, 0xd101, 0x0001, 0xc71e, 0xa002, 0xa200, ++ 0xe0c2, 0x0083, 0xa202, 0xe0c2, 0x0093, 0xc71e, 0xa002, 0xd071, ++ 0x002a, 0xe181, 0xe40e, 0x0061, 0xa200, 0xe0c2, 0x0059, 0xe0c2, ++ 0x0058, 0xe0c2, 0x0008, 0xe0c0, 0x0059, 0xf7ea, 0xa11e, 0xf168, ++ 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058, 0xe004, 0xf202, 0xae20, ++ 0xe005, 0x1307, 0xe056, 0xe0c2, 0x0070, 0xa200, 0xe0c2, 0x0059, ++ 0xe0c2, 0x0058, 0xe0c2, 0x0008, 0xf67e, 0xa202, 0xe0c2, 0x0008, ++ 0xe0c2, 0x0058, 0xe42e, 0x1471, 0xe424, 0xe41e, 0x010d, 0xe41e, ++ 0x00c6, 0xe42e, 0xe0c0, 0x0040, 0xe0c1, 0x005b, 0xae1d, 0xe042, ++ 0xe000, 0x1000, 0xce20, 0xd111, 0x0800, 0xd112, 0x1000, 0xd113, ++ 0x000b, 0xca28, 0xf7f8, 0xe41e, 0x17e0, 0xe42e, 0xe0c0, 0x0041, ++ 0xe005, 0x0000, 0xae11, 0xe042, 0xe0c1, 0x005a, 0xae19, 0xe042, ++ 0xce20, 0xd111, 0x0000, 0xd112, 0x0800, 0xd113, 0x0003, 0xca28, ++ 0xf7f8, 0xe0c0, 0x0041, 0xe005, 0x0080, 0xae11, 0xe042, 0xe0c1, ++ 0x005a, 0xae15, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0200, ++ 0xd113, 0x0013, 0xca28, 0xf7f8, 0xe161, 0x00f4, 0x8891, 0x0032, ++ 0x8891, 0x0033, 0x8891, 0x0034, 0x8891, 0x0035, 0x8891, 0x0036, ++ 0x8891, 0x0037, 0x1091, 0x2691, 0xcc60, 0x1091, 0x2691, 0xcc62, ++ 0x1091, 0x2691, 0xcc74, 0x1091, 0x2691, 0xcf68, 0x1091, 0x2691, ++ 0xcf64, 0x1091, 0x2691, 0xcf60, 0xe42e, 0xe161, 0x00f4, 0x8991, ++ 0x0032, 0x8991, 0x0033, 0x8991, 0x0034, 0x8991, 0x0035, 0x8991, ++ 0x0036, 0x8991, 0x0037, 0xc860, 0x4891, 0x4e91, 0xc862, 0x4891, ++ 0x4e91, 0xc874, 0x4891, 0x4e91, 0xcb68, 0x4891, 0x4e91, 0xcb64, ++ 0x4891, 0x4e91, 0xcb60, 0x4891, 0x4e91, 0xe0c0, 0x0041, 0xe005, ++ 0x0000, 0xae11, 0xe042, 0x1571, 0xae19, 0xe042, 0xce20, 0xd111, ++ 0x0000, 0xd112, 0x0800, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe0c0, ++ 0x0041, 0xe005, 0x0080, 0xae11, 0xe042, 0x1571, 0xae15, 0xe042, ++ 0xce20, 0xd111, 0x0000, 0xd112, 0x0200, 0xd113, 0x0012, 0xca28, ++ 0xf7f8, 0xe42e, 0xe40e, 0x1154, 0xe40e, 0x0172, 0xe40e, 0x0176, ++ 0xe40e, 0x017a, 0xe40e, 0x017e, 0xe40e, 0x0182, 0xe40e, 0x0186, ++ 0xe40e, 0x0061, 0xe40e, 0x0061, 0xe40e, 0x018a, 0xe40e, 0x0061, ++ 0xe40e, 0x0061, 0xe40e, 0x0061, 0xe40e, 0x0061, 0xe40e, 0x0061, ++ 0xe40e, 0x0061, 0xe41e, 0x018e, 0xe40e, 0x0061, 0xe41e, 0x01b7, ++ 0xe40e, 0x0061, 0xe41e, 0x01c4, 0xe40e, 0x0061, 0xe41e, 0x023c, ++ 0xe40e, 0x0061, 0xe41e, 0x024e, 0xe40e, 0x0061, 0xe41e, 0x045b, ++ 0xe40e, 0x0061, 0xe41e, 0x048b, 0xe40e, 0x0061, 0xe41e, 0x0280, ++ 0xe41e, 0x044d, 0xc001, 0xe0c0, 0x0074, 0x4851, 0x4e52, 0xe0c0, ++ 0x0075, 0x4853, 0x4e54, 0xe0c0, 0x0076, 0x4855, 0x4e56, 0xe0c0, ++ 0x0047, 0x4e57, 0xc000, 0xe41e, 0x028c, 0xf0ea, 0xe41e, 0x0bdd, ++ 0xe41e, 0x10fb, 0x1441, 0xe418, 0x0e54, 0xe41e, 0x1020, 0xa202, ++ 0xe0c2, 0x0070, 0xe42e, 0xa200, 0xe0c2, 0x0070, 0xe42e, 0x147d, ++ 0xe428, 0x147e, 0xf07a, 0xa200, 0x487b, 0x4e13, 0xe41e, 0x128b, ++ 0xe42e, 0xe41e, 0x1233, 0xe42e, 0xa200, 0xcc4a, 0xcc4c, 0xcc44, ++ 0xe0c2, 0x0074, 0x147e, 0xf11a, 0x147f, 0xf0aa, 0xe0c0, 0x0066, ++ 0x4810, 0x4e11, 0xe0c0, 0x0067, 0xae04, 0x487a, 0x4e12, 0xa200, ++ 0x487b, 0x4e13, 0xe41e, 0x128b, 0xd180, 0x0004, 0xd147, 0x0001, ++ 0xd03b, 0x0000, 0xd008, 0x0000, 0xe16a, 0xa200, 0xcf06, 0xe0c2, ++ 0x0286, 0xe41e, 0x0394, 0xe41e, 0x1027, 0x142c, 0xf07a, 0xc001, ++ 0x144a, 0xa002, 0xa802, 0x4e4a, 0xc000, 0xe41e, 0x0be0, 0xe41e, ++ 0x0d18, 0xe41e, 0x0d2d, 0x1430, 0xe41a, 0x0a03, 0x1430, 0xe418, ++ 0x0a6c, 0xe41e, 0x0568, 0xe41e, 0x0ddf, 0x1441, 0xe418, 0x0ef3, ++ 0x8221, 0x1620, 0xc001, 0xae02, 0x4831, 0xe008, 0xffff, 0xaf02, ++ 0x4e30, 0x8131, 0xe019, 0xae1e, 0x8130, 0xe01d, 0xc000, 0x162b, ++ 0x0421, 0xe045, 0xb616, 0x4e2b, 0x147e, 0xf06a, 0xe41e, 0x1233, ++ 0xe41e, 0x1124, 0xf05e, 0x147d, 0xf03a, 0xe41e, 0x1255, 0x163b, ++ 0xa002, 0x4e3b, 0xe0c2, 0x0070, 0x1424, 0xe0c2, 0x0071, 0x142f, ++ 0xe0c2, 0x0073, 0xd03a, 0x0000, 0xc84a, 0xc84d, 0xae20, 0xe056, ++ 0xe0c2, 0x0046, 0xa202, 0xe42e, 0xe0c0, 0x0042, 0xce20, 0xd111, ++ 0x03f0, 0xd112, 0x0030, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe0c0, ++ 0x0060, 0x4e3c, 0xe0c0, 0x0061, 0x4e70, 0xe42e, 0x1430, 0xe428, ++ 0x147e, 0xf10a, 0x147f, 0xf0aa, 0xe0c0, 0x0061, 0x4810, 0x4e11, ++ 0xe0c0, 0x0062, 0xae04, 0x487a, 0x4e12, 0xa200, 0x4e13, 0xe41e, ++ 0x128b, 0xe0c0, 0x0060, 0xf06a, 0xa102, 0xf09a, 0xa102, 0xf0aa, ++ 0xe42e, 0xe41e, 0x0987, 0xe41e, 0x098c, 0xf07e, 0xe41e, 0x09d2, ++ 0xf04e, 0xe41e, 0x09f5, 0xf01e, 0x147e, 0xf06a, 0xe41e, 0x1233, ++ 0xe41e, 0x1110, 0xf05e, 0x147d, 0xf03a, 0xe41e, 0x1255, 0xe42e, ++ 0xa200, 0xc401, 0xe188, 0x07ff, 0x4e91, 0xa200, 0x4e78, 0x4e79, ++ 0x4e2b, 0x4e3b, 0xcc74, 0xe42e, 0xe0c0, 0x0071, 0xc001, 0x4659, ++ 0xaf02, 0x4658, 0xc000, 0xe0c0, 0x0064, 0xe049, 0xe009, 0x03ff, ++ 0x4f0e, 0xa01f, 0xaf09, 0x4f51, 0xe049, 0xaf15, 0xe009, 0x03ff, ++ 0x4f0d, 0xa01f, 0xaf09, 0x4f50, 0xe0c0, 0x0065, 0x4821, 0x4e20, ++ 0x1421, 0xa002, 0x4e21, 0x1620, 0xc710, 0x3c21, 0xe008, 0xffff, ++ 0xa002, 0xaf02, 0x4e3d, 0xe0c0, 0x0062, 0x462d, 0xaf02, 0x462e, ++ 0xaf04, 0x467c, 0xaf04, 0xc001, 0x4643, 0xe0c0, 0x006f, 0x4e44, ++ 0xc000, 0xe0c0, 0x0063, 0x4630, 0xf198, 0xa200, 0x4e34, 0x4e35, ++ 0x4e36, 0x4e37, 0xe0c0, 0x0066, 0x4622, 0xaf02, 0x4623, 0x1523, ++ 0x2322, 0x4f23, 0xaf02, 0xa80e, 0x4e47, 0xe0c0, 0x0066, 0xaf0a, ++ 0x4649, 0xaf02, 0x460f, 0xe40e, 0x0336, 0xe167, 0x02a4, 0xc420, ++ 0xa202, 0x4e48, 0x1450, 0xae08, 0x0cb7, 0xe40a, 0x0302, 0x1448, ++ 0xa002, 0x4e48, 0xa10a, 0xe408, 0x02e2, 0xe0c0, 0x0067, 0xe40a, ++ 0x0390, 0xa20c, 0x4e48, 0x1450, 0x4e32, 0x1451, 0x4e31, 0xa132, ++ 0xe406, 0x0318, 0x1432, 0xae02, 0x4e32, 0x1431, 0xaf02, 0x4e31, ++ 0xe40e, 0x0318, 0x80af, 0x8097, 0x1451, 0xae08, 0x0c87, 0xe408, ++ 0x02e7, 0x1448, 0xae04, 0xe000, 0x02a0, 0xe09e, 0x1497, 0xaf08, ++ 0x4e50, 0x1497, 0xaf08, 0x4e51, 0x1497, 0x4e32, 0x1487, 0x4e31, ++ 0xe0c0, 0x0067, 0x4637, 0xaf02, 0x4636, 0xaf02, 0x4635, 0xaf02, ++ 0x4634, 0xe408, 0x0390, 0xa200, 0x1520, 0xe003, 0x7530, 0xb632, ++ 0x1521, 0xe003, 0x03e9, 0xb632, 0x4e38, 0xf09a, 0xe0c0, 0x0067, ++ 0xf068, 0x1421, 0xa102, 0xe408, 0x0390, 0x4e38, 0xe0c0, 0x0069, ++ 0x4608, 0xaf02, 0x4609, 0xaf02, 0x4e0a, 0xe0c0, 0x006a, 0x4e40, ++ 0xe0c0, 0x006b, 0x4641, 0xc001, 0x4801, 0xaf02, 0xe008, 0x7fff, ++ 0x4e00, 0xe0c0, 0x006b, 0x1401, 0xaf1e, 0x462c, 0x1401, 0xe008, ++ 0x7fff, 0x4e01, 0xe0c0, 0x006c, 0x4802, 0x4e03, 0xc000, 0xe0c0, ++ 0x006d, 0x4e42, 0x8250, 0x8151, 0xe018, 0x4e52, 0xa201, 0xe002, ++ 0x00c8, 0xb425, 0xe002, 0x0190, 0xb425, 0x4f45, 0xe0c0, 0x0043, ++ 0xaf04, 0x467d, 0xaf02, 0x467e, 0xaf02, 0x467f, 0x1450, 0x1551, ++ 0xaf06, 0xaf07, 0x4e01, 0x4f00, 0x8201, 0x8100, 0xe018, 0xc001, ++ 0x4e4b, 0xa104, 0xc000, 0xf052, 0xa204, 0xc001, 0x4e4b, 0xc000, ++ 0x1451, 0xaf02, 0x4e01, 0x8201, 0x8150, 0xe018, 0xc001, 0x4e4d, ++ 0x4e50, 0xa202, 0x4e4a, 0xc000, 0xa202, 0xe0c2, 0x0070, 0xe42e, ++ 0xa200, 0xe0c2, 0x0070, 0xe42e, 0xa200, 0x4e1f, 0xe0c0, 0x0065, ++ 0xa804, 0xf09a, 0xa200, 0x4e24, 0x4e2c, 0xc001, 0x4e41, 0xe016, ++ 0x4e0d, 0xc000, 0x1440, 0xf068, 0xc001, 0x1641, 0xc000, 0xf0ca, ++ 0xf13e, 0xc001, 0x1441, 0xc000, 0xf07a, 0xc001, 0x1441, 0xc000, ++ 0x1540, 0xe046, 0xf098, 0xa200, 0x4e24, 0x4e2c, 0xa202, 0xc001, ++ 0x4e41, 0xc000, 0xf08e, 0xa202, 0x4e24, 0x4e2c, 0xc001, 0x0441, ++ 0x4e41, 0xc000, 0xe0c0, 0x0065, 0xa802, 0xe418, 0x03d8, 0xe0c0, ++ 0x0063, 0x4e27, 0x1441, 0xf09a, 0x142c, 0xe41a, 0x0eb8, 0xe41e, ++ 0x0eb9, 0x4e27, 0xe419, 0x03d8, 0xa202, 0x4e28, 0xcf0e, 0xe42e, ++ 0xa202, 0x4e24, 0x4e2c, 0x4e1f, 0x823a, 0xc786, 0xe018, 0xe000, ++ 0x03f0, 0xe09e, 0x1097, 0x2697, 0xe0c2, 0x0060, 0x1097, 0x2697, ++ 0xe0c2, 0x0061, 0x1097, 0x2697, 0xe0c2, 0x0062, 0xe42e, 0x1454, ++ 0xe000, 0x0420, 0xe09e, 0xc874, 0x4e87, 0x1454, 0xa002, 0x0c50, ++ 0xe428, 0x1455, 0xae0e, 0xe005, 0x0000, 0xae11, 0xe042, 0xe0c1, ++ 0x0042, 0xe042, 0xce20, 0xd111, 0x0420, 0xd112, 0x002e, 0xd113, ++ 0x0002, 0xca28, 0xf7f8, 0xe42e, 0x1454, 0xe000, 0x046e, 0xe09e, ++ 0x145d, 0x4e87, 0x1454, 0xa002, 0x0c50, 0xe428, 0x1455, 0xae0e, ++ 0xe005, 0x0013, 0xae11, 0xe042, 0xe0c1, 0x0042, 0xe042, 0xce20, ++ 0xd111, 0x046e, 0xd112, 0x002e, 0xd113, 0x0002, 0xca28, 0xf7f8, ++ 0xe42e, 0x1010, 0x2611, 0x137b, 0x2713, 0xae11, 0xe041, 0xe162, ++ 0x0478, 0xc86e, 0xa010, 0x0c30, 0xaf06, 0xe008, 0x01ff, 0xe042, ++ 0x4892, 0x4e92, 0x142f, 0xae04, 0xe005, 0x0012, 0xae11, 0xe042, ++ 0xe0c1, 0x0042, 0xe042, 0xce20, 0xd111, 0x0478, 0xd112, 0x0020, ++ 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0040, 0xe000, ++ 0x7000, 0xce20, 0xd111, 0x02a0, 0xd112, 0x0100, 0xd113, 0x0003, ++ 0xca28, 0xf7f8, 0xe42e, 0xe41e, 0x1134, 0xe0c0, 0x0060, 0xf06a, ++ 0xa102, 0xf09a, 0xa102, 0xf0aa, 0xe42e, 0xe41e, 0x0987, 0xe41e, ++ 0x098c, 0xf06e, 0xe41e, 0x09d2, 0xf03e, 0xe41e, 0x09f5, 0xc864, ++ 0xaf06, 0xc867, 0xe003, 0x0080, 0xae05, 0xe042, 0x4e4c, 0xe0c2, ++ 0x0070, 0xc86c, 0xd036, 0x00c0, 0xbad7, 0xcc6c, 0xe0c0, 0x0042, ++ 0xce20, 0xd111, 0x0100, 0xd112, 0x0080, 0xd113, 0x0012, 0xca28, ++ 0xf7f8, 0xe12c, 0xe42e, 0xe0c1, 0x0060, 0xa803, 0xf05b, 0xe0c0, ++ 0x0061, 0xe41e, 0x0502, 0xe0c1, 0x0060, 0xa805, 0xf05b, 0xe0c0, ++ 0x0062, 0xe41e, 0x0559, 0xe0c1, 0x0060, 0xa809, 0xf05b, 0xe0c0, ++ 0x0063, 0xe41e, 0x052d, 0xe0c1, 0x0060, 0xa811, 0xf05b, 0xe0c0, ++ 0x0064, 0xe41e, 0x04c5, 0xe0c1, 0x0060, 0xa821, 0xf04b, 0xe0c0, ++ 0x0065, 0x4e42, 0xe0c1, 0x0060, 0xa841, 0xf08b, 0xe0c0, 0x0066, ++ 0x4608, 0xaf02, 0x4609, 0xaf02, 0x4e0a, 0xe0c1, 0x0060, 0xa881, ++ 0xf04b, 0xe0c0, 0x0067, 0x4e49, 0xe42e, 0xc001, 0x4848, 0x4e47, ++ 0x1448, 0xa002, 0x4e48, 0x1647, 0xc710, 0x3c48, 0xe008, 0xffff, ++ 0xa002, 0xaf02, 0x4e0b, 0x0c46, 0xe42a, 0x140b, 0x4e46, 0x1447, ++ 0x1548, 0xc000, 0x4e20, 0x4f21, 0xa200, 0x4e2b, 0x8221, 0xe182, ++ 0x7530, 0xe018, 0xae02, 0x1720, 0xc001, 0xe41e, 0x0fdd, 0x4e18, ++ 0x8218, 0x8100, 0xe018, 0xa279, 0xe41e, 0x0fc6, 0x4818, 0x4e19, ++ 0xae06, 0x1504, 0xe41e, 0x0fc6, 0x481e, 0x4e1f, 0xa200, 0x4e40, ++ 0x4822, 0x4e23, 0x1409, 0xe428, 0xe016, 0x4e0a, 0x140b, 0x4e09, ++ 0xc000, 0xe42e, 0xc001, 0x4e42, 0x1509, 0xe046, 0xf038, 0xc000, ++ 0xe42e, 0x1441, 0x1542, 0xe046, 0xf034, 0xa200, 0x4e41, 0x1442, ++ 0x4e09, 0xc000, 0x4e40, 0x1441, 0xe42a, 0xc001, 0x1409, 0xe016, ++ 0x4e0a, 0xf03a, 0x150b, 0x4f09, 0x1509, 0x1441, 0xe045, 0xf0c6, ++ 0x1026, 0x2627, 0xe41e, 0x0fc6, 0x482a, 0x4e2b, 0x0826, 0x0e27, ++ 0xe012, 0x4828, 0x4e29, 0xc000, 0xe42e, 0xc001, 0x4e45, 0xc000, ++ 0x1441, 0xe42a, 0xc001, 0x1400, 0x1545, 0xe046, 0xc000, 0xe42a, ++ 0xc001, 0x4f00, 0xc000, 0x8221, 0xe182, 0x7530, 0xe018, 0xae02, ++ 0x1720, 0xc001, 0xe41e, 0x0fdd, 0x4e18, 0x8218, 0x8100, 0xe018, ++ 0xa279, 0xe41e, 0x0fc6, 0x4818, 0x4e19, 0xae06, 0x1504, 0xe41e, ++ 0x0fc6, 0x481e, 0x4e1f, 0xa200, 0x4e40, 0x4822, 0x4e23, 0xc000, ++ 0xe42e, 0xc000, 0x1541, 0xe42b, 0xc001, 0xf052, 0xa201, 0x4f43, ++ 0xc000, 0xe42e, 0x4e44, 0x4e10, 0xa203, 0x4f43, 0xc000, 0xe42e, ++ 0xe41e, 0x1085, 0x1427, 0x4e62, 0xe41e, 0x079c, 0xe41e, 0x07a7, ++ 0xa200, 0x4e53, 0x4e54, 0x4e55, 0x4e2f, 0x1436, 0xe016, 0x2230, ++ 0xe408, 0x05dc, 0xa223, 0x1424, 0xe40a, 0x0580, 0x1528, 0xa021, ++ 0x4f61, 0xa200, 0x4e0b, 0xcc6e, 0xa202, 0x4e0c, 0x1422, 0xe418, ++ 0x0b17, 0x140b, 0xe418, 0x0646, 0xe41e, 0x10a5, 0x1453, 0xe002, ++ 0x0107, 0xe408, 0x0594, 0xe190, 0xe41e, 0x0620, 0xe41e, 0x07b2, ++ 0x1422, 0xf048, 0x896e, 0x003a, 0xf0de, 0xa201, 0xe12c, 0xc86e, ++ 0xe041, 0xe12d, 0xc86e, 0xe041, 0xe12e, 0xc86e, 0xe12c, 0xe041, ++ 0x4f6e, 0x142d, 0xe418, 0x03ef, 0x147c, 0xe418, 0x040c, 0xe41e, ++ 0x0662, 0x1422, 0xf038, 0xc875, 0xf0ce, 0xa201, 0xe12c, 0xc86e, ++ 0xe041, 0xe12d, 0xc86e, 0xe041, 0xe12e, 0xc86e, 0xe041, 0xe12c, ++ 0x0f6e, 0xe009, 0xffff, 0x4f6f, 0x1541, 0x145d, 0xe419, 0x0f41, ++ 0x1453, 0xa002, 0x4e53, 0xe41e, 0x10b1, 0xe408, 0x0589, 0x1422, ++ 0xe418, 0x0b36, 0xe41e, 0x065b, 0x1436, 0xf048, 0xe41e, 0x0afb, ++ 0xe42e, 0xe41e, 0x0b05, 0xe42e, 0xa200, 0x4e4b, 0xe40e, 0x05ed, ++ 0x1408, 0xf0ca, 0xbacf, 0xe190, 0xbae0, 0x144b, 0xba88, 0xbac1, ++ 0x145d, 0x4e27, 0xba88, 0xe41e, 0x1085, 0xa200, 0x4e4a, 0xe41e, ++ 0x10a5, 0x1453, 0xe002, 0x00e2, 0xe408, 0x05f7, 0xe190, 0xe41e, ++ 0x07b2, 0x896e, 0x003a, 0x142d, 0xe418, 0x03ef, 0x147c, 0xe418, ++ 0x040c, 0xe41e, 0x06ac, 0xc874, 0x0e6e, 0xe008, 0xffff, 0x4e6f, ++ 0x1541, 0x145d, 0xe419, 0x0f41, 0x1453, 0xa002, 0x4e53, 0xe41e, ++ 0x10b1, 0x144a, 0xa002, 0x4e4a, 0x0c32, 0xe408, 0x05ef, 0x144b, ++ 0xa002, 0x4e4b, 0x0c31, 0xe408, 0x05e0, 0xe41e, 0x0b05, 0xe42e, ++ 0x1408, 0x1509, 0xe42a, 0x1422, 0xe409, 0x0638, 0xe408, 0x062d, ++ 0xc86e, 0x0e0a, 0xe424, 0xe40e, 0x0640, 0xc86e, 0xe12d, 0xc86f, ++ 0xe042, 0xe12e, 0xc86f, 0xe042, 0x0e0a, 0xe424, 0xe40e, 0x0640, ++ 0x140c, 0x0c0a, 0x150c, 0xa003, 0x4f0c, 0xe428, 0xa202, 0x4e0c, ++ 0xa202, 0x4e0b, 0x1465, 0xa002, 0x4e65, 0xe42e, 0xe41e, 0x065b, ++ 0x1422, 0xf05a, 0xe41e, 0x0b36, 0xe41e, 0x0b17, 0x1409, 0xf038, ++ 0xd037, 0x0000, 0x145d, 0x4e27, 0xe41e, 0x0a39, 0xe41e, 0x1085, ++ 0xa200, 0x4e0b, 0xe42e, 0x142e, 0xe418, 0x0429, 0x142f, 0xa002, ++ 0x4e2f, 0xe42e, 0x1536, 0x1422, 0xe409, 0x06ac, 0x1524, 0xe40a, ++ 0x066d, 0xe40b, 0x06e6, 0xe40e, 0x071f, 0x1459, 0x5424, 0xe428, ++ 0x145b, 0xae02, 0x265a, 0xae02, 0x2658, 0x4e4f, 0xa200, 0x0424, ++ 0x4e00, 0x145e, 0xa806, 0xae06, 0x264f, 0x5200, 0x145c, 0x5458, ++ 0xa20a, 0x0c58, 0x4e00, 0x145e, 0xaf04, 0x5200, 0x145a, 0xe418, ++ 0x0762, 0x1458, 0xe41a, 0x0773, 0xa214, 0x0c58, 0xe096, 0xa004, ++ 0xe098, 0xa200, 0x4e60, 0xe161, 0x03d5, 0xe162, 0x03db, 0xd022, ++ 0x0005, 0xe184, 0x06aa, 0x1492, 0xce98, 0x8860, 0x0148, 0xd140, ++ 0x0000, 0x145f, 0xd142, 0x0001, 0xe418, 0x095f, 0xe41e, 0x08f1, ++ 0x1460, 0xa002, 0x4e60, 0xe42e, 0x1459, 0x5424, 0xe428, 0x145b, ++ 0xae02, 0x265a, 0xae02, 0x2658, 0x4e4f, 0xa200, 0x0424, 0x0424, ++ 0x0424, 0x4e00, 0x145e, 0xa806, 0xae06, 0x264f, 0x5200, 0xa20a, ++ 0x0c58, 0x4e00, 0x145e, 0xaf04, 0x5200, 0x145a, 0xe418, 0x0767, ++ 0x1458, 0xe41a, 0x0773, 0xa214, 0xe096, 0xa200, 0x4e60, 0xe161, ++ 0x03d5, 0xd022, 0x0005, 0xe184, 0x06e4, 0xa200, 0xce98, 0x8860, ++ 0x0148, 0xd140, 0x0000, 0x145f, 0xd142, 0x0001, 0xe418, 0x097b, ++ 0xe41e, 0x08f1, 0x1460, 0xa002, 0x4e60, 0xe42e, 0xe12c, 0x145b, ++ 0xae02, 0x265a, 0xae02, 0x2658, 0x4e4f, 0x145e, 0xa806, 0xae06, ++ 0x264f, 0xb900, 0x145a, 0xe418, 0x0762, 0xe12d, 0x145c, 0xba80, ++ 0x145e, 0xaf04, 0xb908, 0xa212, 0x1523, 0xb492, 0xe096, 0xa216, ++ 0xe098, 0xa200, 0x4e60, 0xe161, 0x03d5, 0xe162, 0x03db, 0xd022, ++ 0x0005, 0xe184, 0x071c, 0x1492, 0xce98, 0x8860, 0x0148, 0xd140, ++ 0x0000, 0x145f, 0xd142, 0x0001, 0xe12c, 0xe418, 0x095f, 0xe12e, ++ 0xe41e, 0x08f1, 0x1460, 0xa002, 0x4e60, 0xe12c, 0xe42e, 0xe12c, ++ 0x1459, 0xba80, 0xe428, 0x145b, 0xae02, 0x265a, 0xae02, 0x2658, ++ 0x4e4f, 0x145e, 0xa806, 0xae06, 0x264f, 0xb902, 0x1458, 0xe41a, ++ 0x0773, 0xe12d, 0x145c, 0x5458, 0xa20a, 0x0c58, 0x4e00, 0x145e, ++ 0xaf04, 0x5200, 0x145a, 0xe418, 0x0762, 0xa214, 0x0c58, 0x1523, ++ 0xb492, 0xe096, 0xa004, 0xe098, 0xa200, 0x4e60, 0xe161, 0x03d5, ++ 0xe162, 0x03db, 0xd022, 0x0005, 0xe184, 0x075f, 0x1492, 0xce98, ++ 0x8860, 0x0148, 0xd140, 0x0000, 0x145f, 0xd142, 0x0001, 0xe12d, ++ 0xe418, 0x095f, 0xe12e, 0xe41e, 0x08f1, 0x1460, 0xa002, 0x4e60, ++ 0xe12c, 0xe42e, 0x146c, 0xa002, 0xb628, 0xba82, 0xe42e, 0x1437, ++ 0xe40a, 0x0762, 0x146c, 0xa140, 0xe404, 0x0770, 0xba82, 0xe42e, ++ 0x146c, 0xba8a, 0xe42e, 0x145b, 0xb670, 0xcc44, 0xe161, 0x03a0, ++ 0xe184, 0x077f, 0x1491, 0xa040, 0xb90c, 0x1491, 0xa040, 0xb90c, ++ 0xe42e, 0xe40a, 0x0799, 0xe404, 0x078e, 0xa102, 0xe049, 0x3629, ++ 0xa002, 0xa040, 0xb90c, 0x232a, 0x5529, 0xe42e, 0xa002, 0xe012, ++ 0xe049, 0x3629, 0xa002, 0xe012, 0xa040, 0xb90c, 0x232a, 0x5529, ++ 0xe42e, 0xa040, 0xb90c, 0xe42e, 0xe41e, 0x0e40, 0xa2fc, 0x4e53, ++ 0xe41e, 0x07ce, 0xe41e, 0x0d41, 0xe41e, 0x0814, 0xe42e, 0xe41e, ++ 0x0e40, 0xa2fe, 0x4e53, 0xe41e, 0x07ce, 0xe41e, 0x0d6b, 0xe41e, ++ 0x081f, 0xe42e, 0xe41e, 0x0e40, 0xe41e, 0x07ce, 0xe41e, 0x0d6b, ++ 0xe41e, 0x082a, 0x146c, 0xe01a, 0x4e5a, 0x1424, 0xe418, 0x089b, ++ 0xe41e, 0x08d6, 0x1458, 0xe016, 0x226b, 0x226d, 0x155a, 0xe017, ++ 0xe052, 0x4e59, 0x1435, 0xe418, 0x0e0f, 0xe42e, 0x1452, 0x0c53, ++ 0xa104, 0xe426, 0x1424, 0xe016, 0xf0b8, 0xe0c1, 0x00f4, 0xe001, ++ 0x0200, 0x0f6a, 0xb62a, 0x1542, 0xf038, 0xe419, 0x102a, 0x4e58, ++ 0x1541, 0x232c, 0x1427, 0xf0cb, 0xe41e, 0x0f29, 0x1558, 0xe017, ++ 0x2372, 0xf02b, 0x1462, 0x0c62, 0xa504, 0xa4fc, 0x0462, 0x4e5d, ++ 0x1458, 0x1562, 0x0d26, 0xb606, 0x4e5f, 0x145d, 0x0c62, 0x4e6c, ++ 0x1537, 0xf18a, 0xf17b, 0x1462, 0xe000, 0x02cc, 0xe09e, 0xe160, ++ 0x0020, 0x146c, 0x0cb7, 0xe40a, 0x080c, 0x146c, 0x0c87, 0xe40a, ++ 0x080f, 0x145d, 0xe40e, 0x0810, 0xa244, 0xe40e, 0x0810, 0xa246, ++ 0x4e6c, 0x145d, 0x4e62, 0xe42e, 0xe161, 0x03e1, 0x1458, 0x4e91, ++ 0x145f, 0x4e91, 0x145d, 0x4e91, 0x146c, 0x4e91, 0xe42e, 0xe161, ++ 0x03e5, 0x1458, 0x4e91, 0x145f, 0x4e91, 0x145d, 0x4e91, 0x146c, ++ 0x4e91, 0xe42e, 0xe161, 0x03e9, 0x1458, 0x4e91, 0x145f, 0x4e91, ++ 0x145d, 0x4e91, 0x146c, 0x4e91, 0xe161, 0x03e1, 0x1491, 0x4e58, ++ 0x1491, 0x4e5f, 0x1491, 0x4e5d, 0x1491, 0x4e6c, 0xe162, 0x03e1, ++ 0xd022, 0x0007, 0xe184, 0x0845, 0x1491, 0x4e92, 0xe42e, 0x1424, ++ 0x4e5b, 0x4e72, 0xe42a, 0xe0c0, 0x0217, 0x4e6a, 0x1468, 0xe09a, ++ 0xe0c0, 0x0215, 0xe01a, 0x4e5b, 0x4e72, 0x4e95, 0x8095, 0xe162, ++ 0x02f0, 0xe408, 0x086a, 0xe0c0, 0x0214, 0xae28, 0xaf3a, 0x4e95, ++ 0xe0c1, 0x0214, 0xae39, 0xaf3b, 0x4f8d, 0x1095, 0x2695, 0x9f02, ++ 0xe40e, 0x0883, 0xc420, 0xa230, 0x4e4d, 0xd022, 0x0003, 0xe184, ++ 0x0882, 0xe0c0, 0x0211, 0x364d, 0xae38, 0xaf3a, 0x4e95, 0xe0c1, ++ 0x0212, 0x374d, 0xae39, 0xaf3b, 0x4f8d, 0x1095, 0x2695, 0x9f32, ++ 0x144d, 0xa110, 0x4e4d, 0xe08a, 0x4e68, 0xe004, 0x06db, 0x155b, ++ 0xb616, 0xe0c2, 0x0285, 0x1473, 0xae20, 0x2674, 0xe0c2, 0x0284, ++ 0x1473, 0xa002, 0x4e73, 0x0c50, 0xe428, 0xa200, 0x4e73, 0x1474, ++ 0xa002, 0x4e74, 0xe42e, 0x1458, 0xe408, 0x08c0, 0xe41e, 0x10d8, ++ 0xe161, 0x03a0, 0x1469, 0xe09a, 0x1595, 0x8095, 0x4f5b, 0x1095, ++ 0x268d, 0xe016, 0xb612, 0x4e6b, 0xe004, 0x06db, 0xb616, 0xcf04, ++ 0xb673, 0xcc45, 0xe184, 0x08ba, 0x1095, 0x2695, 0xcf08, 0xe190, ++ 0xcb0a, 0x4891, 0x4e91, 0xe08a, 0x4e69, 0xe41e, 0x10ea, 0xe42e, ++ 0xe41e, 0x10c9, 0x1469, 0xe09a, 0x1495, 0x8095, 0x8095, 0x8095, ++ 0xe40a, 0x08d0, 0x8095, 0x8095, 0x8095, 0x8095, 0x8095, 0x8095, ++ 0xe08a, 0x4e69, 0xa200, 0x4e5b, 0x4e6b, 0xe42e, 0x885f, 0x014b, ++ 0xa200, 0x4e60, 0xe161, 0x03d5, 0xe162, 0x03db, 0xa201, 0xd022, ++ 0x0005, 0xe184, 0x08ec, 0x8892, 0x014c, 0x1460, 0xce90, 0xa002, ++ 0x4e60, 0xca8c, 0x4e91, 0xae03, 0xe055, 0x4f5e, 0xe017, 0x4f6d, ++ 0xe42e, 0x1491, 0xe42a, 0xca86, 0x9103, 0xf04d, 0xaf24, 0xf7ca, ++ 0xe42e, 0xe16a, 0x1523, 0xe409, 0x094c, 0x1530, 0xe409, 0x0917, ++ 0xa207, 0xba8d, 0xe190, 0x9104, 0xe40d, 0x090a, 0xaf24, 0xe40a, ++ 0x08f3, 0xe42e, 0xe16a, 0xa207, 0xba83, 0xe049, 0xaf19, 0xba8d, ++ 0xbae0, 0xba96, 0xbae0, 0xaf0d, 0xe40b, 0x08f3, 0xe42e, 0xa207, ++ 0xba8d, 0xe049, 0xaf19, 0xba8d, 0xaf0d, 0x4f03, 0x8a37, 0x0000, ++ 0xae30, 0xaf30, 0xe40d, 0x092e, 0xe005, 0x007f, 0xe066, 0xe013, ++ 0xe062, 0x1503, 0xba8e, 0xe40b, 0x08f3, 0xe42e, 0xe16a, 0x4e02, ++ 0xe002, 0x007f, 0x1502, 0xe001, 0x007f, 0xe400, 0x093f, 0xe405, ++ 0x093f, 0x1503, 0x1402, 0xba8e, 0xe40b, 0x08f3, 0xe42e, 0xe004, ++ 0x0080, 0xba8e, 0x1402, 0xa83e, 0xba88, 0x1402, 0x1503, 0xaf0a, ++ 0xba8a, 0xe40b, 0x08f3, 0xe42e, 0xbac3, 0xbae0, 0xe049, 0xaf19, ++ 0xba8d, 0xbae0, 0xe049, 0xae31, 0xaf31, 0xe011, 0xba95, 0xbae0, ++ 0xbac3, 0xaf16, 0xba80, 0xaf0e, 0xe40a, 0x08f3, 0xe42e, 0xca86, ++ 0xae30, 0xaf30, 0x4e01, 0xe010, 0xa002, 0xe41e, 0x0b0e, 0x1560, ++ 0xaf05, 0xa00f, 0x4f4c, 0x524c, 0xe42a, 0x4e4c, 0x1401, 0xe400, ++ 0x0975, 0xa202, 0x344c, 0xa102, 0x0401, 0x544c, 0x144c, 0xa110, ++ 0xe426, 0xbae0, 0xe42e, 0xca86, 0xae30, 0xaf30, 0xe005, 0x00fe, ++ 0xe066, 0xe049, 0xe003, 0x0080, 0xb7f6, 0xba8e, 0xe42e, 0xbacf, ++ 0xe004, 0x0100, 0xba9e, 0xe42e, 0xa204, 0x150f, 0xf02b, 0xa202, ++ 0x4e00, 0xbacf, 0xe004, 0x0120, 0xba9e, 0xbac0, 0xbae7, 0xbae0, ++ 0x1400, 0xba86, 0xbae2, 0xbae3, 0xbac0, 0xbac1, 0xbae0, 0x1620, ++ 0xba9e, 0xe190, 0xbae0, 0x1421, 0xa102, 0xe01a, 0xba80, 0xf07a, ++ 0x1620, 0xe41e, 0x0b0e, 0x4e4e, 0x1421, 0x544e, 0xbae0, 0x140d, ++ 0xba98, 0xbae0, 0x140e, 0xba98, 0xbae0, 0xbac0, 0xbae0, 0xa200, ++ 0x5400, 0xbac0, 0xbac0, 0x1400, 0xa102, 0xe40a, 0x09c0, 0xbac0, ++ 0xbae0, 0xbac0, 0x1422, 0xba80, 0xe40a, 0x09c8, 0x1423, 0xba80, ++ 0x1400, 0xa102, 0xe40a, 0x09ce, 0xbac0, 0xbac0, 0xbac0, 0xe41e, ++ 0x0afb, 0xe42e, 0xbacf, 0xe004, 0x01b0, 0xba9e, 0x1450, 0xa116, ++ 0xf090, 0x1451, 0xa112, 0xf060, 0x143d, 0xa11e, 0xf030, 0xa202, ++ 0xf13e, 0x1450, 0xa12c, 0xf0f0, 0x1451, 0xa124, 0xf0c0, 0xa204, ++ 0xf0be, 0x143d, 0xa13c, 0xf070, 0xa01e, 0xf030, 0xa204, 0xf04e, ++ 0xa206, 0xf02e, 0xa208, 0xba8e, 0xe42e, 0xbacf, 0xe004, 0x01b5, ++ 0xba9e, 0xbae0, 0xa204, 0xba86, 0xa202, 0xba84, 0xbae3, 0xbac0, ++ 0xe41e, 0x0afb, 0xe42e, 0xbacf, 0xe004, 0x01b6, 0xba9e, 0x1424, ++ 0xba82, 0x163b, 0xf0aa, 0x162b, 0xf038, 0xbae0, 0xf06e, 0x0e20, ++ 0xf046, 0x0c21, 0xf022, 0xbae0, 0xbac0, 0xbae0, 0x1620, 0xe41e, ++ 0x0b0e, 0x4e4e, 0x162b, 0x544e, 0xbae0, 0xbae0, 0x1424, 0xa102, ++ 0xe408, 0x0a24, 0x1425, 0xba80, 0x1447, 0xba84, 0xe000, 0x02c0, ++ 0xe09e, 0x1487, 0x4e26, 0x1427, 0xba88, 0x1424, 0xe40a, 0x0a38, ++ 0x1428, 0xba84, 0xa102, 0x4e29, 0xa202, 0x3429, 0xa102, 0x4e2a, ++ 0xe42e, 0x1436, 0xe408, 0x0ada, 0xe41e, 0x0afb, 0xbacf, 0x1461, ++ 0xa120, 0x4e4e, 0x544e, 0x1452, 0xe41e, 0x0b0e, 0x4e4e, 0x1453, ++ 0x544e, 0x1427, 0xba88, 0x1449, 0xba80, 0xe42a, 0x163b, 0xf0aa, ++ 0x162b, 0xf038, 0xbae0, 0xf06e, 0x0e20, 0xf046, 0x0c21, 0xf022, ++ 0xbae0, 0xbac0, 0xbae0, 0x1620, 0xe41e, 0x0b0e, 0x4e4e, 0x162b, ++ 0x544e, 0xbae0, 0x1424, 0xba82, 0x1447, 0xba84, 0x1424, 0xe40a, ++ 0x0a6b, 0x1428, 0xba84, 0xe42e, 0xe41e, 0x0b05, 0xbacf, 0xa240, ++ 0xba8a, 0x163b, 0xe008, 0x00ff, 0xba8e, 0xbae0, 0xbac0, 0xbac0, ++ 0xbac0, 0xbac0, 0x1434, 0x2635, 0x2636, 0x2637, 0xe408, 0x0a8a, ++ 0x1448, 0xba84, 0x1424, 0xba80, 0xbac3, 0x1427, 0xba88, 0xbac0, ++ 0xe40e, 0x0ac7, 0xa20e, 0xba84, 0xbae2, 0x1448, 0xba84, 0x1438, ++ 0xba80, 0xbac2, 0x1434, 0xba80, 0x1435, 0xba80, 0x1436, 0xba80, ++ 0xbac2, 0x1437, 0xba80, 0xbae0, 0xbac2, 0x1424, 0xba84, 0xbac1, ++ 0x1425, 0xba80, 0xbae2, 0xbac0, 0x1448, 0xa10c, 0xf0b8, 0xa204, ++ 0xba86, 0x140d, 0xaf04, 0xa102, 0xba90, 0xbae0, 0x140e, 0xaf04, ++ 0xba90, 0x1438, 0xf10a, 0x1421, 0xe002, 0x03e9, 0xe016, 0xba80, ++ 0x8221, 0xe182, 0x0708, 0xe018, 0xc70f, 0x3c20, 0xba8c, 0x163b, ++ 0xaf10, 0xba82, 0xa200, 0x5436, 0x5436, 0x1427, 0xba88, 0xbac0, ++ 0xa200, 0x4e53, 0x1436, 0xe418, 0x0ada, 0x1447, 0xe000, 0x02c0, ++ 0xe09e, 0x1487, 0x4e26, 0xa202, 0x4e28, 0xcf0e, 0xa200, 0x4e29, ++ 0x4e2a, 0xe42e, 0x1453, 0xf0da, 0xc864, 0xa80e, 0xf06a, 0xa110, ++ 0xe012, 0x4e4e, 0xa200, 0x544e, 0xe190, 0xba9e, 0xe190, 0xbae0, ++ 0xbae0, 0x1452, 0xe41e, 0x0b0e, 0x4e4e, 0x1553, 0x554e, 0xa116, ++ 0xf026, 0xbae0, 0x1453, 0xf03a, 0x1427, 0xba88, 0xbae0, 0x1453, ++ 0xf02a, 0xbac1, 0xe42e, 0xbac0, 0xc864, 0xa80e, 0xe42a, 0xa110, ++ 0xe012, 0x4e4e, 0xa2fe, 0x544e, 0xe42e, 0xc864, 0xa80e, 0xe42a, ++ 0xa110, 0xe012, 0x4e4e, 0xa200, 0x544e, 0xe42e, 0xa102, 0xa201, ++ 0xf05a, 0xaf02, 0xa003, 0xe408, 0x0b11, 0xe04a, 0xe42e, 0xe41e, ++ 0x1134, 0xe41e, 0x1144, 0xc001, 0x1457, 0xf0ba, 0x1053, 0x2654, ++ 0x1155, 0x2756, 0xc000, 0x483e, 0x4e18, 0x493f, 0x4f19, 0xf08e, ++ 0xc000, 0xe004, 0x0338, 0x4e18, 0xe004, 0x03f8, 0x4e19, 0xa200, ++ 0x4e1a, 0x4e1b, 0x4e16, 0x4e17, 0xe12c, 0xe42e, 0x1424, 0xe12c, ++ 0xe408, 0x0b41, 0xe004, 0x006b, 0xba8c, 0xe190, 0xbaeb, 0xe40e, ++ 0x0b45, 0xa23e, 0xba88, 0xe190, 0xbaeb, 0xe41e, 0x0b4a, 0xe41e, ++ 0x0b86, 0xe42e, 0x141a, 0xe40a, 0x0b7b, 0xc001, 0x1457, 0xf09a, ++ 0x1153, 0x2754, 0xc000, 0x103e, 0x2618, 0xe046, 0xaf10, 0xf05e, ++ 0xc000, 0x1418, 0xe002, 0x0338, 0x4e1c, 0xe41e, 0x11eb, 0xc001, ++ 0x1457, 0xf07a, 0x1053, 0x2654, 0xc000, 0x483e, 0x4e18, 0xf05e, ++ 0xc000, 0xe004, 0x0338, 0x4e18, 0xe41e, 0x11a7, 0xe004, 0x0800, ++ 0x4e1e, 0xe161, 0x0080, 0xe41e, 0x0bc3, 0x141c, 0xa102, 0x4e1c, ++ 0xf748, 0xe41e, 0x11a7, 0xe12d, 0xc86e, 0xe008, 0x07ff, 0x4e1e, ++ 0xe161, 0x0080, 0xbadf, 0xe41e, 0x0bc3, 0xe42e, 0x141b, 0xe40a, ++ 0x0bb8, 0xc001, 0x1457, 0xf09a, 0x1155, 0x2756, 0xc000, 0x103f, ++ 0x2619, 0xe046, 0xaf10, 0xf05e, 0xc000, 0x1419, 0xe002, 0x03f8, ++ 0x4e1c, 0xe41e, 0x120f, 0xc001, 0x1457, 0xf07a, 0x1055, 0x2656, ++ 0xc000, 0x483f, 0x4e19, 0xf05e, 0xc000, 0xe004, 0x03f8, 0x4e19, ++ 0xe41e, 0x11c9, 0xe004, 0x0800, 0x4e1e, 0xe161, 0x00c0, 0xe41e, ++ 0x0bc3, 0x141c, 0xa102, 0x4e1c, 0xe408, 0x0ba8, 0xe41e, 0x11c9, ++ 0xe12e, 0xc86e, 0xe008, 0x07ff, 0x4e1e, 0xe161, 0x00c0, 0xbadf, ++ 0xe41e, 0x0bc3, 0xe42e, 0xe082, 0xcc78, 0xe12c, 0x141e, 0xaf0a, ++ 0xe40a, 0x0bd1, 0xa102, 0xcc44, 0xe184, 0x0bd0, 0xcc7e, 0xc87c, ++ 0xbabe, 0x141e, 0xa83e, 0xe42a, 0x4e1e, 0xa140, 0xe012, 0x4e1d, ++ 0xcc7e, 0xc87c, 0x361d, 0x541e, 0xe42e, 0xa200, 0x4e39, 0xe42e, ++ 0xe004, 0x0080, 0xe0c2, 0x0094, 0xc001, 0x1457, 0xf04a, 0x1051, ++ 0x2652, 0xf08e, 0xc000, 0xe0c0, 0x0041, 0xe005, 0x0320, 0xae11, ++ 0xe042, 0xc000, 0xe0c2, 0x0089, 0xe0c0, 0x0044, 0x4600, 0x1450, ++ 0xae08, 0xe0c2, 0x009f, 0xe0c2, 0x018b, 0xe0c2, 0x020a, 0x151f, ++ 0xf029, 0x1470, 0xe0c2, 0x009b, 0xe0c2, 0x0209, 0x1400, 0xe0c2, ++ 0x0219, 0xa204, 0xe0c2, 0x0100, 0x1451, 0xae20, 0x2650, 0xae08, ++ 0xe0c2, 0x0084, 0xa202, 0xae2a, 0x2600, 0xae04, 0x262c, 0xae10, ++ 0x1537, 0xae03, 0x2736, 0xae03, 0x2735, 0xae03, 0x2734, 0xae05, ++ 0x2730, 0xe056, 0xe0c2, 0x0080, 0x1435, 0xae02, 0xe0c1, 0x0064, ++ 0xa821, 0xf04b, 0xe0c1, 0x0064, 0xa81f, 0xae05, 0xe056, 0x1535, ++ 0xae19, 0xe056, 0x1535, 0xae1b, 0xe056, 0x151f, 0xf03b, 0xe008, ++ 0xffc3, 0xe0c2, 0x00fa, 0x1435, 0xae0a, 0xe0c2, 0x00e7, 0x1425, ++ 0xae06, 0x2600, 0xae20, 0x1550, 0xae09, 0xe056, 0xa203, 0xae2b, ++ 0xe056, 0xe0c2, 0x0282, 0x1450, 0xae20, 0x2651, 0xae08, 0xe0c2, ++ 0x0283, 0x1450, 0xae0c, 0x2651, 0xe0c2, 0x0183, 0x1435, 0xae02, ++ 0x2635, 0xe0c2, 0x018d, 0x1435, 0xae04, 0xa902, 0xae02, 0x2635, ++ 0xae02, 0x2635, 0xae02, 0xe0c2, 0x0182, 0xa202, 0xae3e, 0xa906, ++ 0xe0c2, 0x00ec, 0xa200, 0xe0c2, 0x0102, 0xa202, 0xe0c2, 0x0102, ++ 0xa204, 0xe0c2, 0x0102, 0xe0c0, 0x0060, 0xe0c2, 0x0098, 0xe0c0, ++ 0x0061, 0xe0c2, 0x0099, 0xe0c0, 0x0062, 0xe0c2, 0x009a, 0x8239, ++ 0xc786, 0xe018, 0xe000, 0x03f0, 0xe09e, 0x1097, 0x2697, 0xe0c2, ++ 0x009c, 0xe0c2, 0x0188, 0x1097, 0x2697, 0xe0c2, 0x0189, 0xe0c2, ++ 0x009d, 0x1097, 0x2697, 0xe0c2, 0x018a, 0xe0c2, 0x009e, 0x823a, ++ 0xc786, 0xe018, 0xe000, 0x03f0, 0xe09e, 0x1097, 0x2697, 0xe0c2, ++ 0x02c0, 0x1097, 0x2697, 0xe0c2, 0x02c1, 0x1097, 0x2697, 0xe0c2, ++ 0x02c2, 0x1439, 0xe0c2, 0x0072, 0x4e3a, 0xa002, 0x4e39, 0x0c3c, ++ 0xf028, 0x4e39, 0xe41e, 0x0cbd, 0xa200, 0x4e71, 0xa200, 0x4e56, ++ 0x4e57, 0xa200, 0x4e65, 0x4e71, 0xe42e, 0xa200, 0xe0c2, 0x0207, ++ 0x8250, 0xe182, 0x0340, 0xe018, 0xe0c2, 0x0208, 0x1451, 0xae08, ++ 0xa102, 0xae20, 0x1550, 0xae09, 0xa103, 0xe056, 0xe0c2, 0x0201, ++ 0xa240, 0xae20, 0xe0c2, 0x0204, 0xa220, 0xae20, 0xa020, 0xe0c2, ++ 0x0205, 0xe0c0, 0x0060, 0xe0c2, 0x0202, 0xe0c0, 0x02c0, 0xe0c2, ++ 0x0203, 0x1427, 0xaf02, 0x0445, 0xa51e, 0xe049, 0xae02, 0xe042, ++ 0xe000, 0x030c, 0xe09e, 0x8097, 0x8097, 0x108f, 0x2687, 0xe0c2, ++ 0x0204, 0xa200, 0xe0c2, 0x0205, 0x1497, 0xe0c2, 0x021a, 0xa200, ++ 0xe0c2, 0x021e, 0xe0c2, 0x021f, 0x142c, 0xe016, 0xe0c2, 0x0206, ++ 0xa224, 0x1535, 0xe017, 0x2330, 0xb612, 0xf02e, 0xa24c, 0x262c, ++ 0xe0c2, 0x0200, 0xa200, 0x4e73, 0x4e74, 0xe004, 0x0450, 0x4e68, ++ 0x4e69, 0xd008, 0x000d, 0xd009, 0x0450, 0xd00a, 0x0478, 0xe42e, ++ 0xa202, 0x0c24, 0xae30, 0xe0c2, 0x00a1, 0x1424, 0xe016, 0xae0a, ++ 0xe0c2, 0x0083, 0x1424, 0xf068, 0xa202, 0xe0c2, 0x0093, 0xe41e, ++ 0x0e40, 0x1424, 0xe418, 0x0e46, 0xe42e, 0xe41e, 0x0847, 0xa216, ++ 0x0c24, 0xae30, 0xe0c2, 0x00a1, 0x1424, 0xae0c, 0xa940, 0xe0c2, ++ 0x0083, 0xa202, 0xe0c2, 0x0093, 0x1424, 0xae02, 0xe0c2, 0x0280, ++ 0xe42e, 0x1424, 0xf06a, 0xa202, 0xe0c2, 0x020b, 0xe41e, 0x0e46, ++ 0xe41e, 0x0847, 0x1471, 0xe0c2, 0x0101, 0x145d, 0xae04, 0x2658, ++ 0xae08, 0x4e77, 0xa216, 0x0c24, 0xae30, 0xe0c2, 0x00a1, 0x1458, ++ 0xae14, 0x265d, 0xe0c2, 0x0082, 0x1424, 0xae0c, 0xa94a, 0xe0c2, ++ 0x0083, 0xa202, 0xe0c2, 0x0093, 0x1424, 0xae02, 0xe0c2, 0x0280, ++ 0xe41e, 0x0e4d, 0xe42e, 0xa202, 0x1553, 0xb60a, 0x4e01, 0xb616, ++ 0x4e02, 0xa103, 0xb616, 0x4e03, 0xa202, 0x0d52, 0xa007, 0xb602, ++ 0x4e04, 0xb616, 0x4e05, 0xa003, 0xb616, 0x4e06, 0x1405, 0x2224, ++ 0xf04a, 0xa202, 0xe0c2, 0x020b, 0x1406, 0x2224, 0xe418, 0x0e46, ++ 0x1406, 0x2224, 0xe418, 0x0847, 0x1430, 0xe016, 0x2201, 0xe418, ++ 0x0e01, 0x1430, 0xe016, 0x2204, 0xe418, 0x0df5, 0x1471, 0xe0c2, ++ 0x0101, 0xe0c0, 0x0184, 0x4e00, 0x1402, 0x2235, 0xae1c, 0x2600, ++ 0xe0c2, 0x00e6, 0x1552, 0xa109, 0x0d53, 0xa216, 0xb496, 0xb6aa, ++ 0x0c24, 0xae30, 0xe0c2, 0x00a1, 0x1458, 0xae14, 0x265d, 0xe0c2, ++ 0x0082, 0x1402, 0x2235, 0xae04, 0x1501, 0x2335, 0xe056, 0xae02, ++ 0x1524, 0x2306, 0xe056, 0xae02, 0x1524, 0xe017, 0x2305, 0x2706, ++ 0xe056, 0xae02, 0x2604, 0xae04, 0x2605, 0xae02, 0x1530, 0xe017, ++ 0x2734, 0x2304, 0xe056, 0xae02, 0x2605, 0xe0c2, 0x0083, 0xe41e, ++ 0x0e4d, 0x1435, 0x1553, 0xf03a, 0xf025, 0xe42e, 0xa202, 0xe0c2, ++ 0x0093, 0x1406, 0x2224, 0xae02, 0xe0c2, 0x0280, 0xe42e, 0xe41e, ++ 0x0e40, 0x1435, 0xe42a, 0xe0c0, 0x0184, 0x4e00, 0xa202, 0xae1c, ++ 0x2600, 0xe0c2, 0x00e6, 0xe004, 0x0200, 0xe0c2, 0x0083, 0xa202, ++ 0xe0c2, 0x0093, 0xe41e, 0x0e40, 0xe42e, 0x1465, 0xe0c2, 0x008a, ++ 0x1477, 0xe0c2, 0x0088, 0x145d, 0xae04, 0x2658, 0xae08, 0x4e77, ++ 0xe42e, 0xe0c0, 0x0092, 0x4e5c, 0xe161, 0x03db, 0xe162, 0x008c, ++ 0xd022, 0x0005, 0xe184, 0x0e0d, 0x9e12, 0x4e91, 0xe42e, 0x1559, ++ 0xe017, 0xae0b, 0x275d, 0xe004, 0x03a8, 0x0456, 0xe09c, 0x1437, ++ 0xae0c, 0x2664, 0xae0c, 0x2663, 0xae0c, 0x2686, 0xae0c, 0xe056, ++ 0xe0c2, 0x018c, 0x1486, 0x4e64, 0x4f86, 0x4f63, 0x1456, 0xae0c, ++ 0x2657, 0xe0c2, 0x0184, 0xa202, 0xe0c2, 0x0093, 0x1452, 0x0c53, ++ 0xa106, 0xf056, 0x1424, 0xae02, 0xe0c2, 0x0280, 0x1456, 0xa002, ++ 0x4e56, 0x0c50, 0xf058, 0x4e56, 0x1457, 0xa002, 0x4e57, 0xe42e, ++ 0xe0c0, 0x0095, 0xf7ea, 0xe0c2, 0x0095, 0xe42e, 0xe0c0, 0x0218, ++ 0xf7ea, 0xa200, 0xe0c2, 0x0218, 0xe42e, 0x1571, 0xa105, 0x1471, ++ 0xa002, 0xb616, 0x4e71, 0xe42e, 0xc001, 0xa240, 0x4e04, 0xa204, ++ 0x4e06, 0xa238, 0x1559, 0xf03b, 0xe0c0, 0x0072, 0x4e05, 0xa20c, ++ 0x4e07, 0xe004, 0x033c, 0x4e08, 0xc000, 0x1440, 0x1552, 0xc001, ++ 0x4e09, 0x4f0f, 0xc000, 0x1620, 0xc710, 0x3c21, 0xe008, 0xffff, ++ 0xa002, 0xaf02, 0xc001, 0x4e0b, 0x4e46, 0xe004, 0x1000, 0x1558, ++ 0xf03b, 0xe0c0, 0x0073, 0x4e0c, 0x1409, 0xe016, 0x4e0a, 0xf06a, ++ 0x140b, 0x4e09, 0xe004, 0x1000, 0x4e0c, 0xc000, 0x8221, 0xe182, ++ 0x7530, 0xe018, 0xae02, 0x1720, 0xc001, 0xe41e, 0x0fdd, 0x4e18, ++ 0x8218, 0x8100, 0xe018, 0xa279, 0xe41e, 0x0fc6, 0x4818, 0x4e19, ++ 0xae06, 0x1504, 0xe41e, 0x0fc6, 0x481e, 0x4e1f, 0xa202, 0x4e0d, ++ 0xa205, 0xc000, 0x0d45, 0xc001, 0xae03, 0xa011, 0x4f14, 0x150f, ++ 0x3514, 0xe013, 0x492e, 0x4f2f, 0x1444, 0x1543, 0xf039, 0xe41e, ++ 0x0f6e, 0x4e10, 0xa004, 0x4e11, 0xe41e, 0x0f94, 0xc000, 0xe42e, ++ 0xe42e, 0x142c, 0xc001, 0x4e0e, 0xa201, 0x4f2d, 0xe418, 0x0f50, ++ 0xa200, 0x4e20, 0x4e21, 0x140e, 0xf248, 0x140d, 0xf05a, 0xa200, ++ 0x4e0d, 0x1410, 0xf26e, 0x1409, 0xa102, 0xf7ca, 0x1543, 0xf03b, ++ 0x1410, 0xf1fe, 0x820f, 0x8140, 0xe019, 0xe04a, 0xaf02, 0x0022, ++ 0x0623, 0xe41e, 0x0fdd, 0xa21f, 0x4f14, 0x1509, 0xc70f, 0x3d14, ++ 0xe009, 0xffff, 0xa405, 0xe046, 0x3006, 0x3205, 0x4e10, 0xf09e, ++ 0xa200, 0x4e1c, 0x4e1d, 0x1411, 0x152d, 0xf02b, 0x1405, 0x4e13, ++ 0x152d, 0xc000, 0xe42e, 0xc001, 0xc874, 0xe41e, 0x0f9d, 0x140e, ++ 0xf0ea, 0x1020, 0x2621, 0xc710, 0x3c0f, 0xe008, 0xffff, 0xa002, ++ 0xaf02, 0x4e11, 0x1020, 0x2621, 0x0022, 0x0623, 0x4822, 0x4e23, ++ 0x1440, 0xa002, 0x4e40, 0x140e, 0xf028, 0x4e40, 0x140e, 0xf0f8, ++ 0x1509, 0xa103, 0x1026, 0x2627, 0xe41e, 0x0fc6, 0x482a, 0x4e2b, ++ 0x0826, 0x0e27, 0xe012, 0x4828, 0x4e29, 0xf0ae, 0x1128, 0x2729, ++ 0x092a, 0x0f2b, 0x140a, 0xb606, 0xb611, 0x4928, 0x4f29, 0xc000, ++ 0xe42e, 0xc001, 0x111c, 0x271d, 0x101e, 0x261f, 0xe041, 0xf097, ++ 0xe045, 0xe045, 0x1413, 0xf095, 0x491c, 0x4f1d, 0xa002, 0xf05e, ++ 0x491c, 0x4f1d, 0x1413, 0xa102, 0x3006, 0x3205, 0x4e13, 0xc000, ++ 0xe42e, 0xc001, 0x0020, 0x0621, 0x4820, 0x4e21, 0xc000, 0x146f, ++ 0xc001, 0x0c12, 0x001c, 0x061d, 0x481c, 0x4e1d, 0xc000, 0xe42e, ++ 0x1028, 0x2629, 0x0826, 0x0e27, 0x820c, 0xe41e, 0x1014, 0x0018, ++ 0x0619, 0xf052, 0x152c, 0xf039, 0xa203, 0x4f2d, 0xe41e, 0x0fac, ++ 0x1118, 0x2719, 0xaf07, 0xe062, 0x481a, 0x4e1b, 0xc710, 0x3c0f, ++ 0xe008, 0xffff, 0xa002, 0xaf02, 0x4e12, 0xe42e, 0x8209, 0x1018, ++ 0x2619, 0xe41e, 0x1008, 0x8207, 0xe41e, 0x1008, 0x1509, 0xa103, ++ 0x0507, 0xe41e, 0x0fc6, 0x481a, 0x4e1b, 0x140f, 0xae08, 0x4e30, ++ 0x101a, 0x261b, 0xae04, 0x001a, 0x061b, 0xae02, 0xc70f, 0x3c30, ++ 0xe008, 0xffff, 0xa010, 0xaf08, 0xc000, 0x0445, 0xc001, 0xa51e, ++ 0x0408, 0xe09e, 0x1487, 0xe42e, 0x8200, 0x8101, 0xe018, 0x4824, ++ 0x4e25, 0xa200, 0x4826, 0x4e27, 0xe42e, 0x0818, 0x0e19, 0x0026, ++ 0x0627, 0x4826, 0x4e27, 0x112e, 0x272f, 0xe046, 0xf032, 0x4926, ++ 0x4f27, 0x1026, 0x1427, 0xe42e, 0x1501, 0xe42b, 0x1124, 0x2725, ++ 0x0926, 0x0f27, 0xe066, 0xf051, 0x152c, 0xf039, 0xa203, 0x4f2d, ++ 0x1102, 0x2703, 0xe42b, 0x1124, 0x2725, 0x0926, 0x0f27, 0x0118, ++ 0x0719, 0x0902, 0x0f03, 0xa401, 0xe062, 0xe42e, 0x4f30, 0xa201, ++ 0xf032, 0xe012, 0xa203, 0x4f34, 0x4e31, 0xaf20, 0xc70f, 0x3c30, ++ 0x4e32, 0xaf20, 0xae20, 0x2631, 0xc70f, 0x3c30, 0x4e33, 0x1032, ++ 0x2633, 0x1534, 0xe42b, 0xe012, 0xe42e, 0x4930, 0x4f31, 0xa201, ++ 0x4f32, 0x1130, 0x2731, 0x3532, 0xe045, 0xf061, 0x1532, 0xa003, ++ 0x4f32, 0xa121, 0xf775, 0x1532, 0xf039, 0xa200, 0xe42e, 0xa103, ++ 0x4f32, 0xcc45, 0xa201, 0x4f33, 0xe184, 0x1005, 0x1533, 0xae03, ++ 0x4f33, 0x1130, 0x2731, 0x3532, 0xe045, 0xf061, 0xe013, 0xe04a, ++ 0x1533, 0xa003, 0x4f33, 0x1532, 0xa103, 0x4f32, 0x1433, 0xe42e, ++ 0xae02, 0x4831, 0xe008, 0xffff, 0xaf02, 0x4e30, 0x8131, 0xe018, ++ 0xae1e, 0x8130, 0xe01c, 0xe42e, 0xae02, 0x4831, 0xe008, 0xffff, ++ 0xaf02, 0x4e30, 0x8130, 0xe018, 0xaf1e, 0x8131, 0xe01c, 0xe42e, ++ 0xa200, 0xc001, 0x4e4c, 0x4e4f, 0x4e49, 0xc000, 0xe42e, 0xa200, ++ 0x4e43, 0xe42e, 0xc001, 0x144a, 0xc000, 0xf2a8, 0x1443, 0x0c42, ++ 0xe402, 0x1083, 0x1453, 0xa004, 0xc001, 0x0c4c, 0xc000, 0xe404, ++ 0x1083, 0xc001, 0x144c, 0x044b, 0x0c50, 0xc000, 0xf0d4, 0xc001, ++ 0x144f, 0xa002, 0xc70f, 0x3c4b, 0xaf20, 0x4e4f, 0x4e4c, 0xc000, ++ 0x1442, 0x4e43, 0xf37e, 0x1443, 0xa002, 0x4e43, 0xc001, 0x144c, ++ 0x044b, 0xc70f, 0x3c50, 0xaf20, 0x4e4c, 0xc000, 0xf2be, 0x1443, ++ 0x0c42, 0xf2a2, 0x1453, 0xa004, 0xc001, 0x0c4d, 0xc000, 0xf244, ++ 0xc001, 0x144d, 0x044b, 0xc000, 0x0c52, 0xf0e4, 0xc001, 0x1449, ++ 0xa002, 0xc70f, 0x3c4b, 0xaf20, 0x4e49, 0x0450, 0x4e4d, 0xc000, ++ 0x1442, 0x4e43, 0xf0fe, 0x1443, 0xa002, 0x4e43, 0xc001, 0x144d, ++ 0x044b, 0xc000, 0xc70f, 0x3c52, 0xaf20, 0xc001, 0x4e4d, 0xc000, ++ 0xf01e, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xe161, 0x0268, 0xd022, ++ 0x002d, 0xa2fc, 0x4e4c, 0xe184, 0x108f, 0x1481, 0x224c, 0x4e91, ++ 0xca40, 0x224c, 0xce40, 0xca46, 0x224c, 0xce46, 0xe42e, 0xe004, ++ 0x0268, 0x4e66, 0xe004, 0x0100, 0x4e67, 0xa2fd, 0xca40, 0xe052, ++ 0xce40, 0xca46, 0xe052, 0xce46, 0xe42e, 0x1454, 0xe41a, 0x1097, ++ 0x1466, 0xe09c, 0x1496, 0xce42, 0x1486, 0xce44, 0xca4a, 0xcf34, ++ 0xe42e, 0x1466, 0xe09c, 0x1458, 0xae02, 0xa902, 0xce48, 0x4e96, ++ 0xce40, 0xca42, 0xce46, 0xe08c, 0x4e66, 0x1454, 0xa002, 0x4e54, ++ 0x0c50, 0xe428, 0xa200, 0x4e54, 0x1455, 0xa002, 0x4e55, 0x0c51, ++ 0xe42e, 0x1524, 0xa200, 0xe42b, 0xcf20, 0xcf22, 0xcf24, 0xcf26, ++ 0x1467, 0xe09c, 0xa200, 0xc707, 0x4e96, 0xe08c, 0x4e67, 0xe42e, ++ 0x1467, 0xe09c, 0x1096, 0x2696, 0xcf28, 0x1096, 0x2696, 0xcf2a, ++ 0x1096, 0x2696, 0xcf2c, 0x1096, 0x2696, 0xcf2e, 0x1096, 0x2696, ++ 0xcf30, 0xe42e, 0x1467, 0xe09c, 0xcb28, 0x4896, 0x4e96, 0xcb2a, ++ 0x4896, 0x4e96, 0xcb2c, 0x4896, 0x4e96, 0xcb2e, 0x4896, 0x4e96, ++ 0xe08c, 0x4e67, 0xe42e, 0xa200, 0x487b, 0x4e13, 0xe0c0, 0x0060, ++ 0x4810, 0x4e11, 0xe0c0, 0x0061, 0xae04, 0x487a, 0x4e12, 0xe41e, ++ 0x1124, 0xe41e, 0x128b, 0xe12c, 0xd071, 0x002a, 0xe181, 0xe42e, ++ 0xe12c, 0xd030, 0x0000, 0xd032, 0x0000, 0xd033, 0x0000, 0xd034, ++ 0x0000, 0xd035, 0x007f, 0xd036, 0x0000, 0xc874, 0xa130, 0xcc74, ++ 0xc86e, 0xa130, 0xcc6e, 0xe42e, 0xe12c, 0xd030, 0x0000, 0xd032, ++ 0x0000, 0xd033, 0x0000, 0xd034, 0x0000, 0xd035, 0x007f, 0xd036, ++ 0x0000, 0xd037, 0x0000, 0xe42e, 0xe12d, 0xd030, 0x0000, 0xd032, ++ 0x0000, 0xd033, 0x0080, 0xd034, 0x0080, 0xd035, 0x00bf, 0xd036, ++ 0x0080, 0xd037, 0x0000, 0xe42e, 0xe12e, 0xd030, 0x0000, 0xd032, ++ 0x0000, 0xd033, 0x00c0, 0xd034, 0x00c0, 0xd035, 0x00ff, 0xd036, ++ 0x00c0, 0xd037, 0x0000, 0xe42e, 0xc872, 0xc000, 0xf06a, 0xa102, ++ 0xf07a, 0xa102, 0xf0ca, 0xe470, 0xe41e, 0x116d, 0xe470, 0x1416, ++ 0xe41a, 0x11eb, 0x1416, 0xe418, 0x11a7, 0xe470, 0x1417, 0xe41a, ++ 0x120f, 0x1417, 0xe418, 0x11c9, 0xe470, 0xd111, 0x0000, 0xe082, ++ 0x4e14, 0xe0c0, 0x005a, 0xae02, 0xe000, 0x0048, 0xe092, 0xe41e, ++ 0x1299, 0x1010, 0x2611, 0x137b, 0x2713, 0xae11, 0xe042, 0xce20, ++ 0x8091, 0xd112, 0x0100, 0xa224, 0xe0c1, 0x0043, 0xa803, 0xf029, ++ 0xa22c, 0xce26, 0xca28, 0xf7f8, 0x127b, 0x2613, 0xe000, 0x0002, ++ 0x487b, 0x4e13, 0x137a, 0x2712, 0xe046, 0xf084, 0x157e, 0xf04b, ++ 0xa203, 0xe0c3, 0x0074, 0x4e13, 0x487b, 0x1010, 0x2611, 0x137b, ++ 0x2713, 0xae11, 0xe042, 0x9f01, 0x1414, 0xe092, 0xe42e, 0xe0c0, ++ 0x0047, 0xf04a, 0x103e, 0x2618, 0xf06e, 0xe0c0, 0x0041, 0x1518, ++ 0xae11, 0xe042, 0xce20, 0xd111, 0x0100, 0xd112, 0x0080, 0xd113, ++ 0x0013, 0xca28, 0xf7f8, 0xe0c0, 0x0047, 0xf07a, 0x103e, 0x2618, ++ 0xe000, 0x0100, 0x483e, 0xf04e, 0x1418, 0xe000, 0x0001, 0x4e18, ++ 0xe42e, 0xe0c0, 0x0047, 0xf04a, 0x103f, 0x2619, 0xf06e, 0xe0c0, ++ 0x0041, 0x1519, 0xae11, 0xe042, 0xce20, 0xd111, 0x0180, 0xd112, ++ 0x0080, 0xd113, 0x0013, 0xca28, 0xf7f8, 0xe0c0, 0x0047, 0xf07a, ++ 0x103f, 0x2619, 0xe000, 0x0100, 0x483f, 0xf04e, 0x1419, 0xe000, ++ 0x0001, 0x4e19, 0xe42e, 0xe0c0, 0x0047, 0xf04a, 0x103e, 0x2618, ++ 0xf06e, 0xe0c0, 0x0041, 0x1518, 0xae11, 0xe042, 0xce20, 0xd111, ++ 0x0100, 0xd112, 0x0080, 0xd113, 0x0012, 0xca28, 0xf7f8, 0xe0c0, ++ 0x0047, 0xf07a, 0x103e, 0x2618, 0xe000, 0x0100, 0x483e, 0xf04e, ++ 0x1418, 0xe000, 0x0001, 0x4e18, 0xa202, 0x4e1a, 0xe42e, 0xe0c0, ++ 0x0047, 0xf04a, 0x103f, 0x2619, 0xf06e, 0xe0c0, 0x0041, 0x1519, ++ 0xae11, 0xe042, 0xce20, 0xd111, 0x0180, 0xd112, 0x0080, 0xd113, ++ 0x0012, 0xca28, 0xf7f8, 0xe0c0, 0x0047, 0xf07a, 0x103f, 0x2619, ++ 0xe000, 0x0100, 0x483f, 0xf04e, 0x1419, 0xe000, 0x0001, 0x4e19, ++ 0xa202, 0x4e1b, 0xe42e, 0xc864, 0xaf06, 0xc867, 0xe003, 0x0000, ++ 0xae05, 0xe042, 0x4e4c, 0xc86c, 0xd036, 0x0080, 0xbad7, 0xcc6c, ++ 0xe41e, 0x116d, 0xe0c0, 0x005a, 0xae02, 0xe000, 0x0049, 0xe092, ++ 0x9e01, 0x1110, 0x2711, 0xe045, 0xf049, 0x1110, 0x2711, 0xe042, ++ 0x044c, 0xe002, 0x0200, 0x9f01, 0xe42e, 0xc866, 0xcc7a, 0xe092, ++ 0xc860, 0xcc7c, 0xd111, 0x0000, 0xe0c0, 0x005a, 0xae02, 0xe000, ++ 0x0048, 0xe092, 0xe41e, 0x1299, 0x1010, 0x2611, 0x137b, 0x2713, ++ 0xae11, 0xe042, 0xce20, 0x8091, 0xd112, 0x0100, 0xa224, 0xe0c1, ++ 0x0043, 0xa803, 0xf029, 0xa22c, 0xce26, 0xca28, 0xf7f8, 0xc864, ++ 0xaf06, 0xc867, 0xe003, 0x0000, 0xae05, 0xe042, 0x4e79, 0x1010, ++ 0x2611, 0x137b, 0x2713, 0xae11, 0xe042, 0x1779, 0xe042, 0x9f01, ++ 0xa202, 0x4e78, 0xe42e, 0x1010, 0x2611, 0x137b, 0x2713, 0xae11, ++ 0xe042, 0xe0c1, 0x005a, 0xae03, 0xe001, 0x0049, 0xe093, 0x9f01, ++ 0xe42e, 0xe0c1, 0x0043, 0xa805, 0xe429, 0x157e, 0xe429, 0xa200, ++ 0x4e15, 0x1010, 0x2611, 0x137b, 0x2713, 0xae11, 0xe042, 0x1778, ++ 0xf03b, 0x1779, 0xe042, 0x9e81, 0xe045, 0xf051, 0x127a, 0x2612, ++ 0xae10, 0xe041, 0xe003, 0x0200, 0x1678, 0xf06a, 0x1679, 0xe041, ++ 0xa200, 0x4e78, 0x4e79, 0xe421, 0x1415, 0xf648, 0xe0c0, 0x005c, ++ 0xe008, 0x8000, 0xf5fa, 0xe0c0, 0x005d, 0xe00a, 0x8000, 0xe0c2, ++ 0x005d, 0xa202, 0xce00, 0x4e15, 0xf55e, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe0c0, 0x0040, 0xe0c1, 0x005b, 0xae1d, 0xe042, 0xce20, 0xd111, ++ 0x0000, 0xd112, 0x0800, 0xd113, 0x000b, 0xca28, 0xf7f8, 0xe42e, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0080, 0x0060, 0x0008, 0x0006, ++ 0x00b0, 0x0090, 0x000b, 0x0009, 0x0160, 0x0120, 0x0016, 0x0012, ++ 0x02c0, 0x0240, 0x0058, 0x0012, 0x0580, 0x0480, 0x0160, 0x0012, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0063, 0x000d, 0x000f, 0x0011, 0x0013, 0x0015, 0x0017, 0x0000, ++ 0xffff, 0xfffe, 0x0001, 0x0002, 0x0000, 0x0002, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xfffe, ++ 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, ++ 0xfffe, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd, ++ 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0x0000, 0x0001, 0x0001, 0x0001, ++ 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0002, ++ 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, ++ 0x0002, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, ++ 0x0003, 0x0002, 0x0001, 0xfffb, 0x0200, 0x0000, 0x0008, 0x0200, ++ 0x0000, 0x0010, 0x0200, 0x0008, 0x0020, 0x0200, 0x0010, 0x0040, ++ 0x0200, 0x0020, 0x0080, 0x0200, 0x0040, 0x00c0, 0x0200, 0x0060, ++ 0x0100, 0x0200, 0x0080, 0x0140, 0x0200, 0x00c0, 0x0180, 0x0200, ++ 0x0100, 0x01c0, 0x0200, 0x0140, 0x0200, 0x0200, 0x0180, 0x0280, ++ 0x0200, 0x0200, 0x0300, 0x0200, 0x0200, 0x0300, 0x0200, 0x0200, ++ 0x0300, 0x0200, 0x0200, 0x0300, 0x0014, 0x0012, 0x0010, 0x000e, ++ 0x000c, 0x000b, 0x000a, 0x0009, 0x0008, 0x0007, 0x0006, 0x0005, ++ 0x0004, 0x0004, 0x0003, 0x0003, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe40e, 0x0022, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, ++ 0xe470, 0xe190, 0xe40e, 0x0152, 0xe470, 0xe190, 0xe470, 0xe190, ++ 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, ++ 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, ++ 0xf202, 0x1307, 0xc001, 0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, ++ 0x0008, 0xe0c2, 0x0058, 0xa200, 0xe0c2, 0x005a, 0xa2fe, 0x4e71, ++ 0x4e72, 0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d, 0xce00, 0xf11e, ++ 0xe0c0, 0x005c, 0xe0c1, 0x0059, 0x4f70, 0xa203, 0x3570, 0xe052, ++ 0xf08a, 0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00, ++ 0xe41e, 0x0084, 0xe0c0, 0x005b, 0x0c72, 0xe418, 0x00b2, 0xe0c0, ++ 0x0059, 0xa114, 0xf18a, 0xa102, 0xf1da, 0xe0c0, 0x005a, 0x0c71, ++ 0xe418, 0x00ab, 0xe0c0, 0x0059, 0xae02, 0xe000, 0x0152, 0xc000, ++ 0xe67c, 0xc001, 0xe0c0, 0x005a, 0x4e71, 0xe0c0, 0x005b, 0x4e72, ++ 0xe40e, 0x0038, 0x1471, 0xe412, 0x010d, 0xa202, 0x4e73, 0xe40e, ++ 0x0061, 0xe41e, 0x00c6, 0xd101, 0x0001, 0xc71e, 0xa002, 0xa200, ++ 0xe0c2, 0x0083, 0xa202, 0xe0c2, 0x0093, 0xc71e, 0xa002, 0xd071, ++ 0x002a, 0xe181, 0xe40e, 0x0061, 0xa200, 0xe0c2, 0x0059, 0xe0c2, ++ 0x0058, 0xe0c2, 0x0008, 0xe0c0, 0x0059, 0xf7ea, 0xa11e, 0xf168, ++ 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058, 0xe004, 0xf202, 0xae20, ++ 0xe005, 0x1307, 0xe056, 0xe0c2, 0x0070, 0xa200, 0xe0c2, 0x0059, ++ 0xe0c2, 0x0058, 0xe0c2, 0x0008, 0xf67e, 0xa202, 0xe0c2, 0x0008, ++ 0xe0c2, 0x0058, 0xe42e, 0x1471, 0xe424, 0xe41e, 0x010d, 0xe41e, ++ 0x00c6, 0xe42e, 0xe0c0, 0x0040, 0xe0c1, 0x005b, 0xae1d, 0xe042, ++ 0xe000, 0x1000, 0xce20, 0xd111, 0x0800, 0xd112, 0x1000, 0xd113, ++ 0x000b, 0xca28, 0xf7f8, 0xe41e, 0x17e0, 0xe42e, 0xe0c0, 0x0041, ++ 0xe005, 0x0000, 0xae11, 0xe042, 0xe0c1, 0x005a, 0xae19, 0xe042, ++ 0xce20, 0xd111, 0x0000, 0xd112, 0x0800, 0xd113, 0x0003, 0xca28, ++ 0xf7f8, 0xe0c0, 0x0041, 0xe005, 0x0080, 0xae11, 0xe042, 0xe0c1, ++ 0x005a, 0xae15, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0200, ++ 0xd113, 0x0013, 0xca28, 0xf7f8, 0xe161, 0x00f4, 0x8891, 0x0032, ++ 0x8891, 0x0033, 0x8891, 0x0034, 0x8891, 0x0035, 0x8891, 0x0036, ++ 0x8891, 0x0037, 0x1091, 0x2691, 0xcc60, 0x1091, 0x2691, 0xcc62, ++ 0x1091, 0x2691, 0xcc74, 0x1091, 0x2691, 0xcf68, 0x1091, 0x2691, ++ 0xcf64, 0x1091, 0x2691, 0xcf60, 0xe42e, 0xe161, 0x00f4, 0x8991, ++ 0x0032, 0x8991, 0x0033, 0x8991, 0x0034, 0x8991, 0x0035, 0x8991, ++ 0x0036, 0x8991, 0x0037, 0xc860, 0x4891, 0x4e91, 0xc862, 0x4891, ++ 0x4e91, 0xc874, 0x4891, 0x4e91, 0xcb68, 0x4891, 0x4e91, 0xcb64, ++ 0x4891, 0x4e91, 0xcb60, 0x4891, 0x4e91, 0xe0c0, 0x0041, 0xe005, ++ 0x0000, 0xae11, 0xe042, 0x1571, 0xae19, 0xe042, 0xce20, 0xd111, ++ 0x0000, 0xd112, 0x0800, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe0c0, ++ 0x0041, 0xe005, 0x0080, 0xae11, 0xe042, 0x1571, 0xae15, 0xe042, ++ 0xce20, 0xd111, 0x0000, 0xd112, 0x0200, 0xd113, 0x0012, 0xca28, ++ 0xf7f8, 0xe42e, 0xe40e, 0x0510, 0xe40e, 0x0172, 0xe40e, 0x0176, ++ 0xe40e, 0x017a, 0xe40e, 0x017e, 0xe40e, 0x0061, 0xe40e, 0x0061, ++ 0xe40e, 0x0182, 0xe40e, 0x0061, 0xe40e, 0x0061, 0xe40e, 0x0061, ++ 0xe40e, 0x0061, 0xe40e, 0x0061, 0xe40e, 0x0061, 0xe40e, 0x0061, ++ 0xe40e, 0x0061, 0xe41e, 0x0186, 0xe40e, 0x0061, 0xe41e, 0x0211, ++ 0xe40e, 0x0061, 0xe41e, 0x0212, 0xe40e, 0x0061, 0xe41e, 0x0336, ++ 0xe40e, 0x0061, 0xe41e, 0x034a, 0xe40e, 0x0061, 0xa200, 0xcc74, ++ 0x4e4f, 0x4e6e, 0xc401, 0xe188, 0x07ff, 0x4e91, 0xa202, 0xe0c2, ++ 0x0070, 0xe41e, 0x0366, 0xc00d, 0xe0c0, 0x0063, 0x486a, 0x4e6b, ++ 0xc000, 0xc00d, 0xe0c0, 0x0064, 0x4860, 0x4e61, 0xe0c0, 0x0065, ++ 0x4862, 0x4e63, 0xe0c0, 0x0066, 0x4864, 0x4e65, 0xe0c0, 0x0067, ++ 0x4866, 0x4e67, 0xe0c0, 0x0068, 0x4868, 0x4e69, 0xe0c0, 0x0047, ++ 0x4e6c, 0xc000, 0xa2fe, 0x4e21, 0x4e22, 0x4e3c, 0xa200, 0x4e6f, ++ 0xc00d, 0x4e75, 0xc000, 0x4e34, 0xe0c0, 0x0062, 0xaf02, 0x4633, ++ 0xaf02, 0xc00d, 0x4674, 0xaf02, 0x4676, 0xaf02, 0x4650, 0xc000, ++ 0xe41e, 0x04e2, 0xe41e, 0x0ad3, 0xe41e, 0x1100, 0xe41e, 0x03a2, ++ 0x146f, 0xf388, 0x1431, 0xa10e, 0xf7a8, 0xe41e, 0x0ae8, 0xe41e, ++ 0x0500, 0xe128, 0xe41e, 0x0844, 0xf72a, 0xa2fe, 0x4e21, 0x1450, ++ 0xae14, 0x2651, 0xae08, 0xe0c2, 0x0071, 0xa200, 0xe0c2, 0x0072, ++ 0x1433, 0xf0ea, 0x1411, 0xa104, 0xf0ba, 0xc001, 0x1466, 0xa004, ++ 0xe0c2, 0x0073, 0x1465, 0x4e64, 0xe0c2, 0x0074, 0xf0ae, 0x1413, ++ 0xa004, 0xe0c2, 0x0073, 0xa200, 0xe0c2, 0x0074, 0xc001, 0x4e64, ++ 0xc000, 0xa200, 0x4e6f, 0xe0c0, 0x0070, 0xa902, 0xe0c2, 0x0070, ++ 0xe42e, 0xa200, 0x4e6f, 0xe0c0, 0x0070, 0xa804, 0xe0c2, 0x0070, ++ 0xe42e, 0xe42e, 0xa200, 0xcc44, 0xa2fe, 0xe0c2, 0x0077, 0xc001, ++ 0x1473, 0xf04a, 0xa200, 0x4e1c, 0x4e73, 0xc000, 0xe0c0, 0x0045, ++ 0xa804, 0xc00d, 0x4e77, 0xc000, 0xe408, 0x02ee, 0xc00d, 0x1474, ++ 0xc000, 0xf0d8, 0x146e, 0xe408, 0x02ee, 0xe41e, 0x0642, 0xf07a, ++ 0x1447, 0xf058, 0xa202, 0x4e6e, 0xe40e, 0x02ee, 0xc00d, 0x1474, ++ 0xc000, 0xf04a, 0xe41e, 0x04b5, 0xf01e, 0xa200, 0xcc4a, 0xcc4c, ++ 0x4e35, 0xe41e, 0x1135, 0xe40a, 0x02ee, 0xd180, 0x0001, 0xd147, ++ 0x0002, 0xd03b, 0x0001, 0xd008, 0x0000, 0xe16a, 0xe004, 0x0123, ++ 0xae20, 0xe00a, 0x4567, 0xcf50, 0xe004, 0x89ab, 0xae20, 0xe00a, ++ 0xcdef, 0xcf52, 0x143d, 0xe002, 0x0029, 0xf028, 0xe190, 0x143d, ++ 0xa002, 0x4e3d, 0xa202, 0x4e2a, 0xe41e, 0x0663, 0xe41e, 0x03a2, ++ 0x1431, 0xf7da, 0xa102, 0xe40a, 0x02b3, 0xa108, 0xf784, 0xe40a, ++ 0x02b3, 0xa102, 0xf17a, 0xa102, 0xf0fa, 0xa102, 0xf10a, 0xa102, ++ 0xf14a, 0xa102, 0xf16a, 0xa102, 0xf14a, 0xa102, 0xf1ea, 0xa10e, ++ 0xf662, 0xe40e, 0x02a7, 0xe41e, 0x0ae8, 0xf22e, 0xe41e, 0x0b10, ++ 0xf1fe, 0xe41e, 0x151a, 0xf1ce, 0xba44, 0xe41e, 0x083b, 0xf18e, ++ 0xc00d, 0x1474, 0xc000, 0xf08a, 0x142a, 0xf06a, 0xa2fa, 0xe0c2, ++ 0x0071, 0xe40e, 0x032f, 0xf0ce, 0xba0e, 0xe002, 0x00ff, 0xf058, ++ 0xba4e, 0xe41e, 0x043e, 0xf798, 0xe41e, 0x083b, 0xf40e, 0x142a, ++ 0xe40a, 0x02d9, 0x1474, 0xf068, 0xe41e, 0x0642, 0xf03a, 0xe40e, ++ 0x02ee, 0xe40e, 0x0266, 0x142a, 0xf0ca, 0xe41e, 0x09c3, 0xe40a, ++ 0x0266, 0x1430, 0x4e2c, 0x1432, 0x4e2d, 0xa200, 0x4e2a, 0xf13e, ++ 0x1430, 0xe01a, 0x152c, 0xe01b, 0xe05a, 0xf118, 0x1432, 0x0c2d, ++ 0xf0e8, 0xe41e, 0x0a61, 0xe40a, 0x0266, 0x1401, 0xe408, 0x0266, ++ 0x1400, 0xf058, 0xe41e, 0x066a, 0xe40e, 0x0266, 0xe41e, 0x045d, ++ 0xf01e, 0xc00d, 0x1474, 0xc000, 0xf01a, 0x142c, 0x4e30, 0x142d, ++ 0x4e32, 0xe41e, 0x0382, 0xe41e, 0x0c22, 0xe41e, 0x0374, 0x1430, ++ 0xf048, 0x1438, 0xe41e, 0x1106, 0xe41e, 0x15e8, 0xc00d, 0x1474, ++ 0xf05a, 0x1477, 0xc000, 0xf0f8, 0xf0de, 0xc000, 0xc00d, 0x1477, ++ 0xc000, 0xf088, 0xe41e, 0x064e, 0xe41e, 0x0642, 0xf03a, 0x1447, ++ 0xe016, 0xf04a, 0xe41e, 0x1622, 0xf0ee, 0xe41e, 0x1622, 0xc00d, ++ 0x1574, 0xc000, 0xf06b, 0xf052, 0xa2fa, 0xe0c2, 0x0071, 0xf0be, ++ 0xe404, 0x025a, 0xe0c2, 0x0071, 0x143c, 0xe412, 0x1114, 0xe0c0, ++ 0x0071, 0x4e3c, 0x1420, 0xe0c2, 0x0073, 0x1435, 0xe0c2, 0x0072, ++ 0x1634, 0xa002, 0x4e34, 0xe0c2, 0x0070, 0xc84a, 0xc84d, 0xae20, ++ 0xe056, 0xe0c2, 0x0046, 0xa202, 0xe0c2, 0x0076, 0xe42e, 0xe0c0, ++ 0x0076, 0xaf02, 0xae02, 0xe0c2, 0x0076, 0xe42e, 0xe0c0, 0x0042, ++ 0xce20, 0xd111, 0x0600, 0xd112, 0x0080, 0xd113, 0x0003, 0xca28, ++ 0xf7f8, 0xe0c0, 0x0060, 0xc001, 0x4e42, 0xc000, 0xe0c0, 0x0061, ++ 0x4e70, 0xe42e, 0xe0c0, 0x0042, 0xce20, 0xd111, 0x0000, 0xd112, ++ 0x0100, 0xd113, 0x0013, 0xca28, 0xf7f8, 0xe0c0, 0x0061, 0x4e45, ++ 0xa202, 0x4e42, 0xe41e, 0x0500, 0xe128, 0xe0c0, 0x0060, 0xf048, ++ 0xe41e, 0x0ae8, 0xf03e, 0xe41e, 0x0b10, 0xe42e, 0xe0c0, 0x0040, ++ 0xe000, 0xb000, 0xce20, 0xd111, 0x03b0, 0xd112, 0x0100, 0xd113, ++ 0x0003, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0040, 0xe000, 0xa200, ++ 0xce20, 0xd111, 0x1100, 0xd112, 0x0700, 0xd113, 0x000b, 0xca28, ++ 0xf7f8, 0xe42e, 0xe0c0, 0x0040, 0xe000, 0xb200, 0xce20, 0xd111, ++ 0x1100, 0xd112, 0x0700, 0xd113, 0x000b, 0xca28, 0xf7f8, 0xe42e, ++ 0xe164, 0x0700, 0x1294, 0x2694, 0xcf68, 0xa208, 0x4e40, 0xa200, ++ 0x4e47, 0xd1b2, 0x01ff, 0xd1b3, 0x01ff, 0xd1b0, 0x0700, 0xd1b1, ++ 0x0000, 0xe42e, 0x1447, 0xe408, 0x0487, 0x1440, 0xaf02, 0xe000, ++ 0x0700, 0xe098, 0x1440, 0xa802, 0x4e41, 0xcb68, 0xaf10, 0xa102, ++ 0xf06a, 0xe41e, 0x0421, 0x146f, 0xf268, 0xf78e, 0xcb68, 0xe008, ++ 0x00ff, 0x4e00, 0xaf0e, 0xf768, 0x1400, 0xaf0a, 0x4e30, 0x1400, ++ 0xa83e, 0x4e31, 0xa10a, 0xe016, 0x4e32, 0xe088, 0xe002, 0x0700, ++ 0xae02, 0x0441, 0x4e40, 0xa200, 0x4e46, 0x4e45, 0xd1b9, 0x0000, ++ 0x8840, 0x01b6, 0xe41e, 0x03e0, 0xe41e, 0x0500, 0xe128, 0xa200, ++ 0x4e39, 0xe42e, 0xe42e, 0x8844, 0x01b9, 0xe41e, 0x03e0, 0xe42e, ++ 0xd1b0, 0x0700, 0x8840, 0x01b6, 0xd1b3, 0x01ff, 0xd1b7, 0x0000, ++ 0xd1b8, 0x0000, 0xcb74, 0xf7fa, 0xa106, 0xf0b4, 0xe41e, 0x0524, ++ 0xd1b6, 0x0000, 0xd1b8, 0x0000, 0xcb74, 0xf7fa, 0xa106, 0xf77a, ++ 0xcb74, 0xa802, 0xcb6f, 0xa803, 0xf0f8, 0xf0eb, 0xcb6c, 0xe002, ++ 0x0200, 0xf068, 0xe41e, 0x0524, 0xa200, 0x4e40, 0xcf6c, 0xd1b8, ++ 0x0000, 0xcb74, 0xf7fa, 0xcb74, 0xa802, 0x4e42, 0xcb6c, 0x4e40, ++ 0xcb6e, 0x0046, 0x0645, 0x4846, 0x4e45, 0x8944, 0x01b9, 0x1440, ++ 0xe002, 0x0200, 0xe428, 0xe41e, 0x0524, 0xa200, 0x4e40, 0xcf6c, ++ 0xe42e, 0x1541, 0x1484, 0xf099, 0xaf10, 0xcb69, 0xae11, 0xe055, ++ 0xcf69, 0xa203, 0x4f41, 0xe42e, 0xe008, 0x00ff, 0xcb69, 0xae11, ++ 0xe055, 0xcf69, 0xa201, 0x4f41, 0x8094, 0xe089, 0xe003, 0x0800, ++ 0xe429, 0xe41e, 0x0524, 0xe164, 0x0700, 0xe42e, 0x1442, 0xe016, ++ 0xc86f, 0xa011, 0xe428, 0xaf07, 0xe009, 0x07ff, 0x1445, 0xe008, ++ 0x07ff, 0xe046, 0xf08a, 0xe049, 0xe011, 0xaf15, 0xe421, 0xe420, ++ 0xa200, 0xe42e, 0xc864, 0xa80e, 0xf028, 0xa210, 0x4e00, 0x5e00, ++ 0xa203, 0x3500, 0xaf03, 0xe046, 0xe42e, 0x1430, 0x1532, 0x4e48, ++ 0x4f49, 0x1445, 0x1542, 0x4e4a, 0x4f4b, 0xa202, 0x4e47, 0xe0c0, ++ 0x0047, 0xf0aa, 0xe0c0, 0x0041, 0xe0c1, 0x005a, 0xae19, 0xe042, ++ 0xe005, 0x00a0, 0xf09e, 0xe0c0, 0x0041, 0xe0c1, 0x005a, 0xae1b, ++ 0xe042, 0xe005, 0x00a0, 0xae11, 0xe042, 0xce20, 0xd111, 0x0000, ++ 0xd112, 0x0100, 0xd113, 0x0012, 0xca28, 0xf7f8, 0xe42e, 0x1448, ++ 0x1549, 0x4e30, 0x4f32, 0x144a, 0x154b, 0x4e45, 0x4f42, 0xa200, ++ 0x4e47, 0x4e46, 0xe0c0, 0x0047, 0xf0aa, 0xe0c0, 0x0041, 0xe0c1, ++ 0x005a, 0xae19, 0xe042, 0xe005, 0x00a0, 0xf09e, 0xe0c0, 0x0041, ++ 0xe0c1, 0x005a, 0xae1b, 0xe042, 0xe005, 0x00a0, 0xae11, 0xe042, ++ 0xce20, 0xd111, 0x0000, 0xd112, 0x0100, 0xd113, 0x0013, 0xca28, ++ 0xf7f8, 0xe41e, 0x0500, 0xe128, 0xe42e, 0xa200, 0xc00d, 0x4e75, ++ 0xc000, 0x482f, 0x4e0b, 0x4e2e, 0xc00d, 0x1476, 0xc000, 0xf05a, ++ 0xe0c0, 0x006b, 0x4808, 0x4e09, 0x1008, 0x2609, 0xe0c1, 0x006a, ++ 0xe042, 0xe0c1, 0x006c, 0xa807, 0xf02b, 0xe042, 0xe0c1, 0x005a, ++ 0xae03, 0xe001, 0x0049, 0xe093, 0x9f01, 0xe004, 0xffff, 0x4e0a, ++ 0xe41e, 0x0500, 0xe41e, 0x057d, 0xe12c, 0xe41e, 0x0524, 0xe41e, ++ 0x0390, 0xe42e, 0xa2fe, 0x486c, 0x4e6d, 0xa200, 0x4e6a, 0x4e6b, ++ 0x482f, 0x4e0b, 0xe0c0, 0x0060, 0x4808, 0x4e09, 0xe0c0, 0x0061, ++ 0xae04, 0x482e, 0x4e0a, 0xe41e, 0x0500, 0xe41e, 0x057d, 0xe12c, ++ 0xd071, 0x002a, 0xe181, 0xe41e, 0x0524, 0xe41e, 0x0390, 0xe42e, ++ 0xe12c, 0xd030, 0x0000, 0xd032, 0x0000, 0xd033, 0x0000, 0xd034, ++ 0x0000, 0xd035, 0x007f, 0xd036, 0x0000, 0xd037, 0x0000, 0xe42e, ++ 0xc872, 0xf06a, 0xa102, 0xf0da, 0xa102, 0xf0ba, 0xf0ce, 0xc000, ++ 0x1442, 0xf068, 0x1439, 0xe408, 0x0749, 0xe41e, 0x03db, 0xe470, ++ 0xe40e, 0x0b32, 0xe40e, 0x075f, 0xd111, 0x0700, 0xe082, 0x4e0c, ++ 0xe0c0, 0x005a, 0xae02, 0xe000, 0x0048, 0xe092, 0xe41e, 0x058b, ++ 0x146f, 0xe408, 0x057a, 0x1008, 0x2609, 0x132f, 0x270b, 0xae11, ++ 0xe042, 0xce20, 0xd112, 0x0100, 0xa206, 0xe0c1, 0x0043, 0xa803, ++ 0xb6f6, 0xce26, 0xca28, 0xf7f8, 0xc00d, 0x1474, 0xc000, 0xf0ca, ++ 0xc00d, 0x1475, 0xc000, 0xf08a, 0xe41e, 0x05ed, 0xc00d, 0x1475, ++ 0xa002, 0x4e75, 0xc000, 0xc00d, 0x1474, 0xc000, 0xf0c8, 0xe41e, ++ 0x05ed, 0x154f, 0xa103, 0xf1a1, 0xe004, 0x0200, 0xf025, 0x140e, ++ 0xe41e, 0x063c, 0x122f, 0x260b, 0xe000, 0x0002, 0x482f, 0x4e0b, ++ 0x132e, 0x270a, 0xe046, 0xf034, 0x482f, 0x4e0b, 0x1008, 0x2609, ++ 0x132f, 0x270b, 0xae11, 0xe042, 0x9f01, 0x106c, 0x266d, 0xa002, ++ 0x486c, 0x4e6d, 0x140c, 0xe092, 0xe42e, 0x1008, 0x2609, 0x132f, ++ 0x270b, 0xae11, 0xe042, 0xe0c1, 0x005a, 0xae03, 0xe001, 0x0048, ++ 0xe093, 0x9f01, 0xe42e, 0xe0c1, 0x0043, 0xa805, 0xe429, 0xc00d, ++ 0x1474, 0xc000, 0xf0aa, 0xe0c0, 0x0059, 0xa102, 0xf068, 0xc00d, ++ 0x1475, 0xc000, 0xf02a, 0xf24e, 0xa200, 0x4e0d, 0xc00d, 0x1474, ++ 0xc000, 0xf038, 0x144f, 0xf348, 0x1008, 0x2609, 0x132f, 0x270b, ++ 0xae11, 0xe042, 0x8091, 0x9e89, 0xe045, 0xf053, 0x122e, 0x260a, ++ 0xae10, 0xe041, 0xe003, 0x0200, 0xe423, 0xc00d, 0x1474, 0xc000, ++ 0xf07a, 0xc00d, 0x1475, 0xa002, 0x4e75, 0xc000, 0xe42e, 0xe0c0, ++ 0x0059, 0xe002, 0x0001, 0xf068, 0xe0c0, 0x0045, 0x466f, 0x146f, ++ 0xf248, 0xc00d, 0x1474, 0xc000, 0xf0e8, 0xe0c0, 0x0059, 0xe002, ++ 0x0003, 0xf098, 0xe0c0, 0x0045, 0xa802, 0xf05a, 0x144f, 0xa002, ++ 0x4e4f, 0xe42e, 0x140d, 0xf498, 0xe0c0, 0x005c, 0xe008, 0x4000, ++ 0xf44a, 0xe0c0, 0x005d, 0xe00a, 0x4000, 0xe0c2, 0x005d, 0xa202, ++ 0xce00, 0x4e0d, 0xe40e, 0x05a4, 0xe42e, 0xc00d, 0x1574, 0xc000, ++ 0xf039, 0x144f, 0xe42a, 0xe085, 0x4f0f, 0xa102, 0xf218, 0x8091, ++ 0x9e09, 0x1108, 0x2709, 0xe046, 0xe008, 0x01ff, 0x4e0e, 0xaf02, ++ 0xe005, 0x0700, 0xe042, 0xe094, 0x140e, 0xe005, 0x0200, 0xe045, ++ 0xa121, 0xf0b3, 0xa021, 0xe41e, 0x0624, 0xe045, 0xa200, 0xf12b, ++ 0x4e92, 0x4e92, 0xa109, 0xf7ce, 0xe41e, 0x0624, 0xf03e, 0xe162, ++ 0x0700, 0xa200, 0xc702, 0x4e92, 0xe005, 0x010b, 0x4f92, 0xc703, ++ 0x4e92, 0x140f, 0xe094, 0xe42e, 0xa806, 0xe42a, 0xa102, 0xf09a, ++ 0xa102, 0xf0fa, 0x1482, 0xe008, 0xff00, 0x4e92, 0xa202, 0xe42e, ++ 0x1482, 0xe008, 0xff00, 0x4e92, 0xa200, 0x4e92, 0xa206, 0xe42e, ++ 0xa200, 0x4e92, 0xa204, 0xe42e, 0x116a, 0x276b, 0xe041, 0x496a, ++ 0x4f6b, 0xe42e, 0x144f, 0xe42a, 0x106c, 0x266d, 0xae12, 0x0440, ++ 0x116a, 0x276b, 0xa002, 0xe046, 0xb60c, 0xe42e, 0xe004, 0x4000, ++ 0xae20, 0x116a, 0x276b, 0xe045, 0xe425, 0xaf12, 0x116c, 0x276d, ++ 0xe045, 0xe425, 0x496c, 0x4f6d, 0xae12, 0x116a, 0x276b, 0xe045, ++ 0x496a, 0x4f6b, 0xe42e, 0xc001, 0xa200, 0x4e02, 0x4e00, 0x4e01, ++ 0xc000, 0xe42e, 0xe161, 0x05b0, 0x142b, 0x4e91, 0xc001, 0x1000, ++ 0x2601, 0xae10, 0x4891, 0x4e91, 0x1000, 0x2601, 0xc00d, 0x156c, ++ 0xf04b, 0x1168, 0x2769, 0xf08e, 0xc001, 0xe005, 0x0480, 0xae11, ++ 0xe042, 0xe0c1, 0x0041, 0xc001, 0xe042, 0xce20, 0xce20, 0xd111, ++ 0x0000, 0xd112, 0x0100, 0xd113, 0x0012, 0xca28, 0xf7f8, 0x1000, ++ 0x2601, 0xe000, 0x0200, 0x4800, 0x4e01, 0xc000, 0x1442, 0xf058, ++ 0xe41e, 0x03db, 0xc001, 0xf59e, 0xe161, 0x05b2, 0x1446, 0xe008, ++ 0x00ff, 0x2681, 0x4e91, 0x1445, 0x4e81, 0xc001, 0x1402, 0xe41e, ++ 0x077d, 0x1402, 0xa002, 0x4e02, 0xc000, 0xe42e, 0xc001, 0x4e04, ++ 0x1402, 0xe40a, 0x0701, 0xa102, 0x4e03, 0xe161, 0x05b0, 0xe004, ++ 0x270f, 0x4e08, 0xa2fe, 0x4e0a, 0xe41e, 0x0797, 0x1481, 0x0c04, ++ 0xf11a, 0x1481, 0x0c08, 0xf052, 0x1481, 0x4e08, 0x1403, 0x4e0a, ++ 0x1403, 0xa102, 0x4e03, 0xf712, 0x140a, 0xf344, 0x4e03, 0xe41e, ++ 0x0797, 0x1481, 0xc000, 0x4e2b, 0xc001, 0xe004, 0x270f, 0x4e91, ++ 0x1091, 0x2689, 0xaf10, 0xe41e, 0x07bd, 0x1403, 0xe41e, 0x077d, ++ 0xe004, 0x0000, 0xe005, 0x007f, 0xe41e, 0x07b2, 0x1091, 0x2681, ++ 0xaf10, 0xe000, 0x0200, 0x480b, 0x4e0c, 0x1491, 0xe008, 0x00ff, ++ 0xae20, 0x2681, 0xc000, 0x4846, 0x4e45, 0xe002, 0x0200, 0xc001, ++ 0x480d, 0x4e0e, 0xc000, 0xb604, 0xb628, 0x4e42, 0xa202, 0x4e39, ++ 0xe42e, 0xc000, 0x1452, 0x4e2b, 0xe42e, 0xc001, 0x4e04, 0x4f05, ++ 0x4f07, 0x1402, 0xf0ea, 0xa102, 0x4e03, 0xe161, 0x05b0, 0xe41e, ++ 0x0797, 0x1481, 0x0c04, 0xf07a, 0x1403, 0xa102, 0x4e03, 0xf782, ++ 0xa200, 0xe42e, 0xe004, 0x270f, 0x4e91, 0x1091, 0x2689, 0xaf10, ++ 0x1505, 0xe41e, 0x07d6, 0x1403, 0xe41e, 0x077d, 0x1405, 0xae08, ++ 0xe000, 0x0080, 0xa21f, 0xe41e, 0x07b2, 0x1405, 0xae04, 0xe000, ++ 0x0700, 0xe094, 0x1091, 0x2681, 0xaf10, 0xa080, 0x4892, 0x4e92, ++ 0x1491, 0xe008, 0x00ff, 0xae20, 0x2681, 0xc000, 0x4846, 0x4e45, ++ 0xa180, 0x4892, 0x4e92, 0xb604, 0xb628, 0x4e42, 0xc001, 0xa202, ++ 0xe42e, 0xc001, 0x100b, 0x260c, 0xe41e, 0x07bd, 0x100b, 0x260c, ++ 0xe000, 0x0200, 0x480b, 0x4e0c, 0x100d, 0x260e, 0xe002, 0x0200, ++ 0x480d, 0x4e0e, 0xb604, 0xb628, 0xc000, 0x4e42, 0xe470, 0xe082, ++ 0x4e0c, 0xc001, 0x1407, 0xae04, 0xe000, 0x0700, 0xe092, 0x1091, ++ 0x2689, 0x1507, 0xe41e, 0x07d6, 0x1091, 0x2689, 0xa080, 0x4891, ++ 0x4e91, 0x1091, 0x2689, 0xa180, 0x4891, 0x4e91, 0xb604, 0xb628, ++ 0xc000, 0x4e42, 0x140c, 0xe092, 0xe470, 0xae06, 0xc00d, 0x156c, ++ 0xf04b, 0x1166, 0x2767, 0xf08e, 0xc001, 0xe005, 0x0456, 0xae11, ++ 0xe042, 0xe0c1, 0x0041, 0xc001, 0xe042, 0xce20, 0xd111, 0x05b0, ++ 0xd112, 0x0020, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0x1403, ++ 0xae06, 0xc00d, 0x156c, 0xf04b, 0x1166, 0x2767, 0xf08e, 0xc001, ++ 0xe005, 0x0456, 0xae11, 0xe042, 0xe0c1, 0x0041, 0xc001, 0xe042, ++ 0xce20, 0xd111, 0x05b0, 0xd112, 0x0020, 0xd113, 0x0003, 0xca28, ++ 0xf7f8, 0xe42e, 0xcc66, 0xcc68, 0xcc6c, 0xe042, 0xcc6a, 0xa200, ++ 0xcc60, 0xcc64, 0xcc6e, 0xe128, 0xe42e, 0xc00d, 0x156c, 0xf04b, ++ 0x1168, 0x2769, 0xf08e, 0xc001, 0xe005, 0x0480, 0xae11, 0xe042, ++ 0xe0c1, 0x0041, 0xc001, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, ++ 0x0100, 0xd113, 0x0013, 0xca28, 0xf7f8, 0xe42e, 0xae09, 0xe001, ++ 0x0080, 0xae03, 0xce23, 0xc00d, 0x156c, 0xf04b, 0x1168, 0x2769, ++ 0xf08e, 0xc001, 0xe005, 0x0480, 0xae11, 0xe042, 0xe0c1, 0x0041, ++ 0xc001, 0xe042, 0xce20, 0xd112, 0x0020, 0xd113, 0x0013, 0xca28, ++ 0xf7f8, 0xe42e, 0xba0c, 0xf03a, 0xbcfc, 0xe42e, 0xba4c, 0xa20c, ++ 0x4e4c, 0x144c, 0xa002, 0x4e4c, 0xa140, 0xf0d2, 0xba40, 0xf7aa, ++ 0x344c, 0xa102, 0x4836, 0x4e37, 0x144c, 0xe41e, 0x082f, 0x0036, ++ 0x0637, 0xe42e, 0xe16b, 0xe42e, 0xba0c, 0xf03a, 0xbd7e, 0xe42e, ++ 0xba4c, 0xa20c, 0x4e4c, 0x144c, 0xa002, 0x4e4c, 0xa140, 0xf162, ++ 0xba40, 0xf7aa, 0x344c, 0xa102, 0x4836, 0x4e37, 0x144c, 0xe41e, ++ 0x082f, 0x0036, 0x0637, 0x4e37, 0x8a37, 0x0000, 0xa002, 0xaf02, ++ 0xe012, 0xe42c, 0xe012, 0xe16a, 0xe42e, 0xe16b, 0xe42e, 0xa120, ++ 0xf050, 0xa020, 0x4e4e, 0x564e, 0xe42e, 0x4e4e, 0xba5e, 0x344e, ++ 0x574e, 0xe056, 0xe42e, 0xba40, 0xc864, 0xa80e, 0x4e00, 0xe016, ++ 0xe428, 0x5600, 0xa202, 0xe42e, 0xba4e, 0xa184, 0xba41, 0xf03a, ++ 0xe40b, 0x08db, 0xba40, 0xba40, 0xba48, 0xe408, 0x08db, 0xba4e, ++ 0xbc3e, 0x4e21, 0xbc18, 0xe40d, 0x08db, 0xa008, 0x4e10, 0xbc04, ++ 0x4e11, 0xe40d, 0x08db, 0xa102, 0xf034, 0xf06a, 0xf2ce, 0xbc18, ++ 0xa008, 0x4e12, 0xf28e, 0xba40, 0x4e12, 0xe41e, 0x080c, 0xc001, ++ 0x4868, 0x4e69, 0xc000, 0xe41e, 0x080c, 0xc001, 0x486a, 0x4e6b, ++ 0xc000, 0xe41e, 0x07f2, 0xc001, 0x4e6c, 0xc000, 0xe002, 0x00ff, ++ 0xe400, 0x08db, 0xe000, 0x00ff, 0xf0ea, 0xa102, 0xcc44, 0xe162, ++ 0x0104, 0xe184, 0x0886, 0xe41e, 0x080c, 0x4892, 0x4e92, 0xe41e, ++ 0x091f, 0xf01e, 0xe40d, 0x08db, 0xbc20, 0xe40d, 0x08db, 0x4e13, ++ 0xba40, 0x4e14, 0xbc58, 0xe40d, 0x08db, 0xa002, 0x4e50, 0xe004, ++ 0x0654, 0xc70f, 0x3c50, 0xe008, 0xffff, 0xe005, 0x007e, 0xa003, ++ 0xe066, 0xa102, 0xe092, 0x9401, 0xf37d, 0xa002, 0x4e51, 0x8250, ++ 0x8151, 0xe018, 0x4e52, 0xba40, 0xf2fa, 0xba40, 0xba40, 0xf0aa, ++ 0xe41e, 0x07f2, 0xe41e, 0x07f2, 0xe41e, 0x07f2, 0xe41e, 0x07f2, ++ 0xf23d, 0xa200, 0x4e15, 0x4e16, 0xa220, 0xc001, 0x4e65, 0x4e66, ++ 0xc000, 0xba40, 0xe016, 0xe41a, 0x093f, 0xf16a, 0xe41e, 0x083b, ++ 0xf13a, 0xe004, 0x1fa4, 0xc70f, 0x3c52, 0xe008, 0xffff, 0xc001, ++ 0x1566, 0xe065, 0x4f66, 0x1466, 0x1565, 0xe065, 0x4f65, 0xc000, ++ 0xe16a, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0xe41e, 0x07f2, ++ 0x4e22, 0xbc3e, 0xf3ad, 0x0c21, 0xf09a, 0x0421, 0x4e21, 0xe41e, ++ 0x0aff, 0xe12d, 0xa203, 0x4f3a, 0xf30a, 0xba40, 0xf2e8, 0xba40, ++ 0x4e18, 0xbc0e, 0xf2ad, 0x4e19, 0xf04a, 0xe41e, 0x1332, 0xf25d, ++ 0xbc3e, 0xf23d, 0x4e1a, 0xbc3e, 0xf20d, 0xba40, 0xf1e8, 0xba42, ++ 0xf1c8, 0xbd34, 0xf1ad, 0xa034, 0x4e1b, 0xf174, 0xa168, 0xf152, ++ 0xbd34, 0xf13d, 0xa034, 0xf114, 0xa168, 0xf0f2, 0xbd18, 0xf0dd, ++ 0x4e1c, 0xba40, 0x4e1d, 0xba40, 0x4e1e, 0xba40, 0x4e1f, 0xe41e, ++ 0x083b, 0xf03a, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0xe0c0, ++ 0x0047, 0xf0aa, 0xe0c0, 0x0041, 0xe0c1, 0x005a, 0xae19, 0xe042, ++ 0xe005, 0x00a2, 0xf09e, 0xe0c0, 0x0041, 0xe0c1, 0x005a, 0xae1b, ++ 0xe042, 0xe005, 0x00a2, 0xae11, 0xe042, 0xce20, 0xd111, 0x0104, ++ 0xd112, 0x0200, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0xc00d, ++ 0x1450, 0xc000, 0xf03a, 0xa202, 0xe42e, 0xba40, 0xf08a, 0xba4e, ++ 0xe002, 0x00ff, 0xf048, 0xba5e, 0xe190, 0xba5e, 0xba40, 0xf02a, ++ 0xba40, 0xba40, 0xf09a, 0xba44, 0xba40, 0xba40, 0xf05a, 0xba4e, ++ 0xba4e, 0xe190, 0xba4e, 0xba40, 0xf03a, 0xbc0a, 0xbc0a, 0xba40, ++ 0xf0aa, 0xba5e, 0xae20, 0xba5f, 0xe056, 0xba5e, 0xae20, 0xba5f, ++ 0xe056, 0xba40, 0xba40, 0x4e15, 0xe016, 0xe161, 0x05a6, 0xe41a, ++ 0x09a8, 0xf1ea, 0xba40, 0x4e16, 0xe016, 0xe161, 0x05ab, 0xe41a, ++ 0x09a8, 0xf16a, 0x1415, 0x2616, 0xf02a, 0xba40, 0xba40, 0x4e17, ++ 0xba40, 0xf0ca, 0xba40, 0xbc20, 0xbc20, 0xbc20, 0xbc20, 0xc001, ++ 0xbc20, 0x4e65, 0xbc20, 0x4e66, 0xc000, 0xa202, 0xe42e, 0xa200, ++ 0x4e15, 0x4e16, 0x4e17, 0xa220, 0xc001, 0x4e65, 0x4e66, 0xc000, ++ 0xe0c0, 0x0059, 0xa102, 0xf0b8, 0xe0c0, 0x0070, 0xa904, 0xe0c2, ++ 0x0070, 0xc00d, 0x1450, 0xc000, 0xf02a, 0xf68e, 0xa200, 0xe42e, ++ 0xe41e, 0x07f2, 0xcc44, 0xa002, 0x4e91, 0xba46, 0xba46, 0xe184, ++ 0x09b5, 0xe41e, 0x07f2, 0xe41e, 0x07f2, 0xba40, 0xba48, 0xa002, ++ 0x4e91, 0xba48, 0xa002, 0x4e91, 0xba48, 0xa002, 0x4e91, 0xba48, ++ 0x4e91, 0xa202, 0xe42e, 0xa2fe, 0x4e38, 0xe41e, 0x07f2, 0xe40d, ++ 0x0a54, 0x4e2b, 0x0c52, 0xe402, 0x0a54, 0xbc12, 0xe40d, 0x0a54, ++ 0xa10a, 0xb4a8, 0xf05a, 0xa104, 0xe408, 0x0a54, 0xa204, 0xe016, ++ 0x4e20, 0xe41e, 0x07f2, 0xe40d, 0x0a54, 0xe002, 0x00ff, 0xe400, ++ 0x0a54, 0xe000, 0x00ff, 0x0c22, 0xf0da, 0x0422, 0x4e22, 0xe41e, ++ 0x0b24, 0xf088, 0xe0c0, 0x0076, 0xa904, 0xe0c2, 0x0076, 0xe40e, ++ 0x0a54, 0x5610, 0x4e23, 0x1432, 0xf06a, 0xe41e, 0x07f2, 0xe40d, ++ 0x0a54, 0x4e24, 0x1411, 0xa102, 0xf034, 0xf11a, 0xf25e, 0x5612, ++ 0xc001, 0x4e1a, 0xc000, 0x1418, 0xe418, 0x080c, 0xe40d, 0x0a54, ++ 0xc001, 0x4818, 0x4e19, 0xc000, 0xe40e, 0x0a23, 0x1412, 0xe016, ++ 0xe418, 0x080c, 0xc001, 0x4818, 0x4e19, 0xc000, 0xe40d, 0x0a54, ++ 0x1412, 0xe016, 0x2218, 0xe418, 0x080c, 0xe40d, 0x0a54, 0xc001, ++ 0x481a, 0x4e1b, 0xc000, 0x141f, 0xf07a, 0xe41e, 0x07f2, 0xe40d, ++ 0x0a54, 0xe408, 0x0a54, 0xc00d, 0x1474, 0xc000, 0xf01a, 0x5620, ++ 0xf03a, 0xbc1e, 0xf22d, 0xe41e, 0x1143, 0x5620, 0xf09a, 0xbc06, ++ 0xf1cd, 0xa106, 0xf05a, 0xe41e, 0x07f2, 0xf17d, 0xf79e, 0xe41e, ++ 0x1171, 0xf13a, 0xe41e, 0x080c, 0xf10d, 0x141d, 0xf09a, 0xbc04, ++ 0xf0cd, 0xa102, 0xf05a, 0xbd0c, 0xf08d, 0xbd0c, 0xf06d, 0x1419, ++ 0xe418, 0x135e, 0xa202, 0xe42e, 0xe16a, 0x1438, 0xf094, 0xe41e, ++ 0x1106, 0x1438, 0xe41e, 0x110d, 0x1438, 0xe41e, 0x1114, 0xa200, ++ 0xe42e, 0xa200, 0x4e00, 0xe41e, 0x07f2, 0xe40d, 0x0ad0, 0x4e2b, ++ 0x0c52, 0xe402, 0x0ad0, 0xbc12, 0xe40d, 0x0ad0, 0xa10a, 0xb4a8, ++ 0xf04a, 0xa104, 0xe408, 0x0ad0, 0xe41e, 0x07f2, 0xe40d, 0x0ad0, ++ 0xe002, 0x00ff, 0xe400, 0x0ad0, 0xe000, 0x00ff, 0x0c22, 0xf03a, ++ 0xa202, 0x4e00, 0x5610, 0x0c23, 0xf03a, 0xa202, 0x4e00, 0x1432, ++ 0xf09a, 0xe41e, 0x07f2, 0xe40d, 0x0ad0, 0x0c24, 0xf03a, 0xa202, ++ 0x4e00, 0x1411, 0xa102, 0xf034, 0xf16a, 0xf2de, 0x5612, 0xc001, ++ 0x0e1a, 0xc000, 0xf03a, 0xa202, 0x4e00, 0x1418, 0xf24a, 0xe41e, ++ 0x080c, 0xf2fd, 0xc001, 0x0818, 0x0e19, 0xc000, 0xf03a, 0xa202, ++ 0x4e00, 0xf19e, 0x1412, 0xf178, 0xe41e, 0x080c, 0xf22d, 0xc001, ++ 0x0818, 0x0e19, 0xc000, 0xf03a, 0xa202, 0x4e00, 0x1418, 0xf0ba, ++ 0xe41e, 0x080c, 0xf16d, 0xc001, 0x081a, 0x0e1b, 0xc000, 0xf03a, ++ 0xa202, 0x4e00, 0x141f, 0xf0aa, 0xe41e, 0x07f2, 0xf0ad, 0xa1fe, ++ 0xf080, 0xa0fe, 0xf03a, 0xa201, 0x4f00, 0x4e01, 0xa202, 0xe42e, ++ 0xe16a, 0xa200, 0xe42e, 0xe161, 0x0100, 0xa200, 0x4e91, 0x4e02, ++ 0xd022, 0x011f, 0xe184, 0x0ae0, 0xe41e, 0x0bd9, 0x1402, 0xa002, ++ 0x4e02, 0xa200, 0x4e3a, 0xc001, 0x4e10, 0x4e11, 0xc000, 0xe42e, ++ 0xba4e, 0xba40, 0xba40, 0xba40, 0xba48, 0xba4e, 0xbc3e, 0xf0dd, ++ 0x4e00, 0x0c21, 0xf038, 0xa2fe, 0x4e21, 0x1400, 0xe000, 0x0100, ++ 0xe41e, 0x0b3c, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0xa204, ++ 0x4e3a, 0x1421, 0xe000, 0x0100, 0xe41e, 0x0b9f, 0xe42a, 0xe41e, ++ 0x0844, 0xe42a, 0xe41e, 0x1166, 0xe41e, 0x15e0, 0xa202, 0xe42e, ++ 0xe41e, 0x07f2, 0xf0fd, 0x4e01, 0xe002, 0x00ff, 0xf0b0, 0x1401, ++ 0x0c22, 0xf038, 0xa2fe, 0x4e22, 0x1401, 0xe41e, 0x0b3c, 0xa202, ++ 0xe42e, 0xe16a, 0xa200, 0xe42e, 0xa202, 0x4e3a, 0x1422, 0xe41e, ++ 0x0b9f, 0xe42a, 0xe41e, 0x08de, 0xe12c, 0xa201, 0x4f3a, 0xe42a, ++ 0xa202, 0xe42e, 0xc001, 0x1012, 0x2613, 0xc873, 0xae09, 0xe001, ++ 0x0070, 0xe41e, 0x0c15, 0xe470, 0x4e02, 0xe41e, 0x0bcd, 0xa200, ++ 0x4e03, 0xa200, 0x1445, 0xa87e, 0xf05a, 0x1445, 0xa97e, 0xa002, ++ 0x4e45, 0xe161, 0x0100, 0x1481, 0xa203, 0x4f91, 0xc001, 0xf10a, ++ 0xc000, 0x1445, 0xa006, 0xaf04, 0x0c81, 0xc001, 0xf090, 0x8091, ++ 0x1091, 0x2691, 0x4814, 0x4e15, 0xa202, 0x4e03, 0xf08e, 0x1010, ++ 0x2611, 0x4814, 0x4e15, 0x8091, 0x4891, 0x4e91, 0xe41e, 0x0bff, ++ 0xce20, 0xd111, 0x0000, 0xc000, 0x1445, 0xc001, 0xa006, 0xaf04, ++ 0xae02, 0xce24, 0xd113, 0x0012, 0xca28, 0xf7f8, 0xc000, 0x1442, ++ 0xf158, 0xe41e, 0x03db, 0xc001, 0xa202, 0x1014, 0x2615, 0xe000, ++ 0x0200, 0x4814, 0x4e15, 0xc000, 0x1445, 0xa87e, 0xf05a, 0x1445, ++ 0xa97e, 0xa002, 0x4e45, 0xc001, 0xf5ae, 0x1403, 0xe428, 0xe161, ++ 0x0101, 0x1445, 0xa006, 0xaf04, 0x4e81, 0xae04, 0xc001, 0x0010, ++ 0x0611, 0x4810, 0x4e11, 0xc000, 0xe41e, 0x0bd9, 0xe42e, 0x4e02, ++ 0xe41e, 0x0bcd, 0xe161, 0x0100, 0x1491, 0xe42a, 0x8091, 0x1091, ++ 0x2691, 0xc001, 0x4814, 0x4e15, 0xe41e, 0x0bff, 0xc000, 0x153a, ++ 0xc001, 0xae09, 0xe001, 0x0070, 0xe41e, 0x0c15, 0xc000, 0x143a, ++ 0xa102, 0xf05a, 0xe12e, 0xe004, 0x0090, 0xf04e, 0xe12d, 0xe004, ++ 0x0080, 0xcc66, 0xcc68, 0xcc6c, 0xa01e, 0xcc6a, 0xa200, 0xcc60, ++ 0xcc64, 0xcc6e, 0xe128, 0xa202, 0xe42e, 0xe41e, 0x0be5, 0xce20, ++ 0xd111, 0x0100, 0xd112, 0x0020, 0xd113, 0x0003, 0xca28, 0xf7f8, ++ 0xe42e, 0xe41e, 0x0be5, 0xce20, 0xd111, 0x0100, 0xd112, 0x0020, ++ 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0047, 0xf0aa, ++ 0xe0c0, 0x0041, 0xe0c1, 0x005a, 0xae19, 0xe042, 0xe005, 0x00a6, ++ 0xf09e, 0xe0c0, 0x0041, 0xe0c1, 0x005a, 0xae1b, 0xe042, 0xe005, ++ 0x00a6, 0xae11, 0xe042, 0x1502, 0xae07, 0xe042, 0xe42e, 0xc00d, ++ 0x146c, 0xf04a, 0x106a, 0x266b, 0xf0ce, 0xc001, 0xe0c0, 0x0041, ++ 0xe0c1, 0x005a, 0xae1b, 0xe042, 0xe005, 0x00af, 0xae11, 0xe042, ++ 0xc001, 0x1114, 0x2715, 0xe042, 0xe42e, 0xae03, 0xce20, 0xce23, ++ 0xa080, 0x4812, 0x4e13, 0xd112, 0x0020, 0xd113, 0x0013, 0xca28, ++ 0xf7f8, 0xe42e, 0x1432, 0xf15a, 0xc001, 0x141c, 0xc000, 0xf118, ++ 0xc001, 0xa202, 0x4e1c, 0xc000, 0xd101, 0x0001, 0xc71e, 0xa002, ++ 0xa200, 0xe0c2, 0x0083, 0xa202, 0xe0c2, 0x0093, 0xc71e, 0xa002, ++ 0xe41e, 0x0d42, 0xe41e, 0x15a0, 0xe41e, 0x12db, 0x1419, 0xf04a, ++ 0xe41e, 0x13d2, 0xf19e, 0xa200, 0x4e53, 0x1453, 0x0c52, 0xf142, ++ 0x1453, 0xa201, 0xe41e, 0x06ae, 0x142b, 0x0c53, 0xf774, 0xf06a, ++ 0xe41e, 0x0d0c, 0x142b, 0x0c52, 0xf072, 0xe41e, 0x0c69, 0xf6ea, ++ 0xe41e, 0x0cd9, 0xf6be, 0xe41e, 0x16bd, 0xe41e, 0x16c6, 0xe41e, ++ 0x16ce, 0xe41e, 0x16d4, 0xa200, 0x4e54, 0x4e55, 0xe41e, 0x0d2a, ++ 0xe42e, 0xe41e, 0x07f2, 0x4e2b, 0xbc12, 0xa10a, 0xb4a8, 0xe016, ++ 0x4e20, 0xe41e, 0x07f2, 0x5610, 0x1432, 0xe418, 0x07f2, 0x1411, ++ 0xa102, 0xf034, 0xf07a, 0xf0de, 0x5612, 0x1418, 0xe418, 0x080c, ++ 0xf08e, 0x1412, 0xf068, 0xe41e, 0x080c, 0x1418, 0xe418, 0x080c, ++ 0x141f, 0xe418, 0x07f2, 0x1420, 0xf08a, 0xba41, 0x141a, 0xf04b, ++ 0xbc1e, 0xe40d, 0x0cd6, 0x4e25, 0x1420, 0xe016, 0xe41a, 0x12e1, ++ 0xf3ea, 0x1430, 0xf19a, 0x1432, 0xf04a, 0xba40, 0xba40, 0xf14e, ++ 0xba40, 0xf12a, 0xbc0c, 0xf33d, 0xf0fa, 0xa106, 0xf07a, 0xa104, ++ 0xf7aa, 0xe41e, 0x07f2, 0xf2bd, 0xf76e, 0xe41e, 0x07f2, 0xf27d, ++ 0xbc20, 0xf25d, 0xf70e, 0xe41e, 0x080c, 0xf21d, 0x041b, 0xa400, ++ 0xa566, 0x4e26, 0xa200, 0x4e27, 0x4e28, 0x4e29, 0x141d, 0xf10a, ++ 0xbc04, 0xf15d, 0x4e27, 0xa102, 0xf0ba, 0xbd0c, 0xf10d, 0xae02, ++ 0xa83e, 0x4e28, 0xbd0c, 0xf0bd, 0xae02, 0xa83e, 0x4e29, 0x1419, ++ 0xf04a, 0xc001, 0x562e, 0xc000, 0xa202, 0xe42e, 0xe16a, 0xa200, ++ 0xe42e, 0xa200, 0x4e5b, 0x1426, 0x4e61, 0x142b, 0x4e53, 0xc70f, ++ 0x3c50, 0x4854, 0x4e55, 0x1427, 0xae0a, 0x2628, 0xae0a, 0x2629, ++ 0xce4e, 0xe41e, 0x1225, 0x1453, 0x0c52, 0xf1a2, 0x1453, 0xe002, ++ 0x0007, 0xf028, 0xe190, 0xe41e, 0x124e, 0xe41e, 0x0d5a, 0xf13d, ++ 0xe41e, 0x0e03, 0xe41e, 0x1699, 0x1453, 0xa002, 0x4e53, 0xe41e, ++ 0x1262, 0x145b, 0xa102, 0xf680, 0xe41e, 0x043e, 0xf658, 0xe41e, ++ 0x083b, 0xe42e, 0xe16a, 0xe42e, 0x1426, 0x4e61, 0xa202, 0x4e3b, ++ 0x1453, 0xc70f, 0x3c50, 0x4854, 0x4e55, 0x1453, 0x0c2b, 0xf122, ++ 0xe41e, 0x124e, 0xe41e, 0x0de4, 0xe41e, 0x0e03, 0xe41e, 0x1699, ++ 0x1453, 0xa002, 0x4e53, 0xe41e, 0x1262, 0x1435, 0xa002, 0x4e35, ++ 0xf6de, 0xe42e, 0xe0c0, 0x0047, 0xf06a, 0xe0c0, 0x0041, 0xe005, ++ 0x0120, 0xf05e, 0xe0c0, 0x0041, 0xe005, 0x047e, 0xae11, 0xe042, ++ 0xce20, 0xd111, 0x0700, 0xd112, 0x0100, 0xd113, 0x0003, 0xca28, ++ 0xf7f8, 0xe42e, 0xe0c0, 0x0047, 0xf06a, 0xe0c0, 0x0041, 0xe005, ++ 0x0120, 0xf05e, 0xe0c0, 0x0041, 0xe005, 0x047e, 0xae11, 0xe042, ++ 0xce20, 0xd111, 0x0700, 0xd112, 0x0100, 0xd113, 0x0002, 0xca28, ++ 0xf7f8, 0xe42e, 0x1461, 0xe41e, 0x0e93, 0x1520, 0xa200, 0x4e58, ++ 0x4e5c, 0x4e5d, 0xf0b9, 0xbc32, 0xa203, 0x4f58, 0xe42d, 0xe40a, ++ 0x0da6, 0x4e59, 0xa132, 0xf13a, 0xf24e, 0x145b, 0xe049, 0xb5f0, ++ 0xe41b, 0x07f2, 0x4e5b, 0xe42d, 0xe408, 0x0dc4, 0xbc3c, 0x4e59, ++ 0xa10a, 0xe42d, 0xf3c4, 0xa203, 0x4f58, 0xf6ae, 0xa202, 0x4e5d, ++ 0xa200, 0x4e62, 0xe41e, 0x0e95, 0xa220, 0xe41e, 0x1277, 0xe41e, ++ 0x1293, 0xe41e, 0x129c, 0xe41e, 0x1640, 0xe41e, 0x1100, 0xe42e, ++ 0xa202, 0x4e5c, 0xe41e, 0x0e45, 0xbc06, 0x4e5e, 0xe42d, 0xe41e, ++ 0x0e6d, 0xe41e, 0x0e8a, 0xe42d, 0xe41e, 0x1293, 0xe41e, 0x129c, ++ 0xe41e, 0x1640, 0xe41e, 0x114a, 0xf2ad, 0xe42e, 0xe41e, 0x0e4f, ++ 0xbc06, 0x4e5e, 0xe42d, 0xe41e, 0x0e79, 0xe42d, 0xe41e, 0x129c, ++ 0xe41e, 0x1640, 0xe41e, 0x114a, 0xf1ad, 0xe42e, 0xe41e, 0x0e9e, ++ 0xe42d, 0xe41e, 0x0e79, 0xe42d, 0xe41e, 0x1293, 0xe41e, 0x1640, ++ 0xe41e, 0x114a, 0xf0cd, 0xe42e, 0xe41e, 0x0ef8, 0xa200, 0xe41e, ++ 0x1277, 0xe41e, 0x1293, 0xe41e, 0x1640, 0xe42e, 0x1473, 0xe0c2, ++ 0x0102, 0x1435, 0xa002, 0x4e35, 0x1419, 0xf098, 0xe41e, 0x0e03, ++ 0xe41e, 0x1699, 0x1453, 0xa002, 0x4e53, 0xe42e, 0xe16a, 0xa200, ++ 0xc001, 0x4e30, 0xc000, 0xe42e, 0x1461, 0xe41e, 0x0e93, 0xa200, ++ 0x4e5d, 0x4e5e, 0x1432, 0x4e58, 0x4e5c, 0xf0ca, 0x1453, 0xa802, ++ 0xae08, 0xe000, 0x051b, 0xe092, 0xa204, 0x4e81, 0xe41e, 0x129c, ++ 0xf03e, 0xe41e, 0x0ef8, 0xa200, 0xe41e, 0x1277, 0xe41e, 0x1293, ++ 0xe41e, 0x1640, 0xe42e, 0x1463, 0xae0c, 0x2662, 0xae02, 0x2658, ++ 0xae02, 0xa902, 0xce48, 0x4e5a, 0xcac6, 0xce60, 0xcb12, 0xce62, ++ 0x1454, 0xe01a, 0xe012, 0xe049, 0x147e, 0xe092, 0xd132, 0x0000, ++ 0xca66, 0xe052, 0x4e91, 0xca66, 0x4e91, 0xca66, 0x4e91, 0xca66, ++ 0x4e91, 0x1455, 0xe01a, 0xe012, 0xe049, 0xca66, 0xe052, 0x4e91, ++ 0xca66, 0x4e91, 0xca66, 0x4e91, 0xca66, 0x4e91, 0xd134, 0x0000, ++ 0xca6a, 0x4e91, 0xca6a, 0x4e91, 0xca6a, 0x4e91, 0xca6a, 0x4e91, ++ 0xca6a, 0x4e91, 0xca6a, 0x4e91, 0xe082, 0x4e7e, 0xe002, 0x0575, ++ 0xe005, 0x054b, 0xe428, 0x4f7e, 0xe42e, 0x1473, 0xae08, 0xe000, ++ 0x051b, 0xe092, 0x1459, 0xa102, 0xa806, 0x4e81, 0xe42e, 0x1465, ++ 0xe09c, 0x1486, 0xcece, 0xd160, 0x0000, 0x1473, 0xae08, 0xe000, ++ 0x051b, 0xe094, 0xd022, 0x000f, 0xe184, 0x0e67, 0xba40, 0xcac9, ++ 0xf068, 0xba44, 0xe045, 0xf021, 0xa002, 0xe049, 0xcecb, 0x4f92, ++ 0xcace, 0x4e96, 0xe08c, 0x4e65, 0xe42e, 0xa21e, 0x1559, 0xa119, ++ 0xb60e, 0x4e5f, 0x1459, 0xa102, 0xaf04, 0xa106, 0xb468, 0x4e60, ++ 0xe42e, 0xbc60, 0xe005, 0x03b0, 0xe041, 0xe041, 0x0558, 0xe09d, ++ 0x1486, 0xa81e, 0x4e5f, 0x1486, 0xe049, 0xaf08, 0x4e60, 0xe419, ++ 0x0e8a, 0xe42e, 0xbd34, 0x0461, 0xa269, 0xb605, 0xe042, 0xa168, ++ 0xa269, 0xb605, 0xe042, 0x4e62, 0x4e61, 0x041c, 0xa400, 0xa566, ++ 0xe000, 0x0410, 0xe09c, 0x1486, 0x4e63, 0xe42e, 0xe41e, 0x12b4, ++ 0x1459, 0x1525, 0xa061, 0xe095, 0xe40a, 0x0ef0, 0xa104, 0xe406, ++ 0x0edf, 0xa201, 0xd022, 0x0003, 0xe184, 0x0eb1, 0xbc06, 0xa006, ++ 0xae07, 0xe055, 0xe42d, 0xcf05, 0x1459, 0xa108, 0xe40a, 0x0ec2, ++ 0xa201, 0xd022, 0x0003, 0xe184, 0x0ebf, 0x9002, 0xae09, 0xe055, ++ 0xe42d, 0xe04a, 0xcf06, 0xcb10, 0xcc44, 0xe161, 0x0575, 0x4e91, ++ 0xe184, 0x0eda, 0xcb02, 0x4e91, 0xbd7e, 0xe41d, 0x0f1c, 0x4e91, ++ 0xbd7f, 0xe41d, 0x0f35, 0x4f89, 0x1091, 0x2689, 0xcf0a, 0xe190, ++ 0xcb14, 0x4891, 0x4e91, 0xe42d, 0xe41e, 0x12c8, 0xe42e, 0xe004, ++ 0x0124, 0x3459, 0x2659, 0xcf04, 0x9002, 0xae08, 0x9082, 0xe056, ++ 0xae08, 0xe056, 0xae08, 0xe056, 0xcf06, 0xa202, 0xe40e, 0x0ec4, ++ 0xa200, 0xcf04, 0x9002, 0xae18, 0xcf06, 0xa200, 0xe40e, 0x0ec4, ++ 0xe41e, 0x12b4, 0xa200, 0xcf04, 0xcf06, 0xca4a, 0xa806, 0xa106, ++ 0xe161, 0x0575, 0xf118, 0x1468, 0xe09c, 0x1096, 0x268e, 0xcb21, ++ 0xf0ba, 0xf0ab, 0xa200, 0xcf0a, 0x4e91, 0x4e91, 0xcb14, 0x4891, ++ 0x4e91, 0xe40e, 0x0f19, 0xa200, 0xcf08, 0x4e91, 0x4e91, 0x4891, ++ 0x4e91, 0xe41e, 0x12c8, 0xe42e, 0xba4c, 0xa20c, 0x4e4c, 0x144c, ++ 0xa002, 0x4e4c, 0xa11e, 0xe42a, 0xba40, 0xf7aa, 0x344c, 0xa102, ++ 0x4e4d, 0x564c, 0x044d, 0x4e4d, 0x8a4d, 0x0000, 0xa002, 0xaf02, ++ 0xe012, 0xe42c, 0xe012, 0xe16a, 0xe42e, 0xba4d, 0xa20d, 0x4f4c, ++ 0x154c, 0xa003, 0x4f4c, 0xa11b, 0xe42b, 0xba41, 0xf7ab, 0x354c, ++ 0xa103, 0x4f4d, 0x574c, 0x054d, 0x4f4d, 0x8a4d, 0x0000, 0xa003, ++ 0xaf03, 0xe013, 0xe42c, 0xe013, 0xe16a, 0xe42e, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe161, 0x0490, 0xa200, 0xc713, 0x4e91, 0xe42e, 0xe000, 0x0490, ++ 0xe09e, 0x1487, 0xa80c, 0x4e87, 0xe42e, 0xe000, 0x0490, 0xe09e, ++ 0x1487, 0xa80a, 0x4e87, 0xe42e, 0xc001, 0x4e4a, 0xe000, 0x0490, ++ 0xe09e, 0x1487, 0xa806, 0x4e87, 0x144a, 0xa002, 0x4e4a, 0x0c42, ++ 0xf038, 0xa200, 0x4e4a, 0xc000, 0xe42e, 0xe161, 0x0490, 0x1442, ++ 0xa102, 0xcc44, 0xa200, 0xe184, 0x1130, 0x1591, 0xa807, 0xe01b, ++ 0xe042, 0x0c66, 0xa102, 0xe01a, 0xe42e, 0xe161, 0x0490, 0xc001, ++ 0x1442, 0xc000, 0xa102, 0xcc44, 0xe184, 0x1141, 0x1491, 0xe016, ++ 0xe428, 0xe190, 0xe42e, 0xc001, 0x144a, 0x4e4b, 0x144b, 0xe000, ++ 0x0490, 0xe092, 0x1481, 0xf13a, 0x144b, 0xa002, 0x4e4b, 0x0c42, ++ 0xf038, 0xa200, 0x4e4b, 0x144b, 0x0c4a, 0xf718, 0xa200, 0x4e4a, ++ 0xc000, 0xa2fe, 0x4e38, 0xe0c2, 0x0077, 0xe42e, 0xa20e, 0x4e81, ++ 0x144b, 0xc000, 0x4e38, 0xe0c2, 0x0077, 0xe42e, 0xa202, 0x3410, ++ 0x1513, 0xa403, 0xc001, 0x4e40, 0x4f41, 0xa200, 0x4e4a, 0xc000, ++ 0xe42e, 0xe41e, 0x1214, 0x1438, 0xc001, 0x4e43, 0xa200, 0x4e4c, ++ 0x1444, 0x4e45, 0xc000, 0x1430, 0xe016, 0xe428, 0x1432, 0xc001, ++ 0xf15a, 0xe41e, 0x121f, 0xe161, 0x04a4, 0xba40, 0xba40, 0xb7f0, ++ 0xb634, 0x4e91, 0xa200, 0x4e91, 0x1443, 0x4e91, 0xa200, 0x4e46, ++ 0xa202, 0x4e44, 0xc000, 0xa202, 0xe42e, 0xc000, 0x1414, 0xc001, ++ 0xe418, 0x11f8, 0xc000, 0x1423, 0xc001, 0x4e46, 0x4e49, 0xa202, ++ 0x4e48, 0xba40, 0xe40a, 0x11e7, 0xbc0c, 0xe40a, 0x11e7, 0xa102, ++ 0xf0aa, 0xa102, 0xf15a, 0xa102, 0xf18a, 0xa102, 0xf23a, 0xa102, ++ 0xf26a, 0xf2de, 0xc000, 0xe41e, 0x07f2, 0xa002, 0x0e23, 0xc001, ++ 0xe012, 0xf022, 0x0640, 0xa203, 0xe41e, 0x1237, 0xf66e, 0xbc20, ++ 0xa2ff, 0xe41e, 0x1237, 0xf61e, 0xc000, 0xe41e, 0x07f2, 0xa002, ++ 0x0e23, 0xc001, 0xe012, 0xf022, 0x0640, 0xbc21, 0xe41e, 0x1252, ++ 0xf54e, 0xbc20, 0xa102, 0xe41e, 0x1275, 0xf4fe, 0xe41e, 0x121f, ++ 0xa202, 0x4e4c, 0xa200, 0x4e46, 0x4e49, 0xf47e, 0xbc20, 0x4e49, ++ 0xa2ff, 0xe41e, 0x1237, 0xa2fe, 0x4e48, 0xe40e, 0x11a4, 0x1444, ++ 0x0444, 0x0444, 0xe000, 0x04a4, 0xe09e, 0x1448, 0x4e97, 0x1449, ++ 0x4e97, 0x1443, 0x4e97, 0xe41e, 0x128d, 0xc000, 0xa202, 0xe42e, ++ 0x1446, 0x4e47, 0x1447, 0xa002, 0xc70f, 0x3c40, 0xaf20, 0x4e47, ++ 0xc000, 0x0e23, 0xc001, 0xe42a, 0x1444, 0x0444, 0x0444, 0xe000, ++ 0x04a4, 0xe09e, 0xa202, 0x4e97, 0x1447, 0x4e97, 0xa2fe, 0x4e97, ++ 0xe41e, 0x128d, 0xf68e, 0xe42e, 0xe161, 0x04a4, 0xe162, 0x0460, ++ 0xd022, 0x002f, 0xe184, 0x121d, 0x1491, 0x4e92, 0xe42e, 0xe161, ++ 0x04a4, 0x1444, 0xf0ea, 0xa102, 0xcc44, 0xe184, 0x122e, 0x1491, ++ 0xf05a, 0x8091, 0x1489, 0xe412, 0x1106, 0x8091, 0x8091, 0xe190, ++ 0xa200, 0x4e44, 0xe161, 0x04a4, 0xc732, 0x4e91, 0xe42e, 0x4e50, ++ 0x4f51, 0x1444, 0xe42a, 0xa102, 0xcc44, 0xe161, 0x04a4, 0xe184, ++ 0x1250, 0x1491, 0x1791, 0x0c51, 0x0f50, 0xf0b8, 0xf0a9, 0x8089, ++ 0x8089, 0xa200, 0x4e91, 0x8091, 0x1481, 0xe412, 0x1106, 0xe42e, ++ 0x8091, 0xe42e, 0x4e50, 0x4f51, 0x1444, 0xe42a, 0xa102, 0xcc44, ++ 0xe161, 0x04a4, 0xe184, 0x1273, 0x1491, 0x1789, 0x0f50, 0xf076, ++ 0xf069, 0xa2fe, 0x4e91, 0x1451, 0x4e91, 0xf0ee, 0x1491, 0x1591, ++ 0x0d51, 0xf0a2, 0xf099, 0x8089, 0x8089, 0xa200, 0x4e91, 0x8091, ++ 0x1481, 0xe41e, 0x1106, 0x8091, 0xe42e, 0x4e50, 0x1444, 0xe42a, ++ 0xa102, 0xcc44, 0xe161, 0x04a4, 0xe184, 0x128b, 0x1491, 0x1591, ++ 0x0d50, 0xf0a2, 0xf097, 0x8089, 0x8089, 0xa200, 0x4e91, 0x8091, ++ 0x1481, 0xe41e, 0x1106, 0x8091, 0xe42e, 0xe161, 0x04a4, 0xe162, ++ 0x018a, 0xd022, 0x0032, 0xe184, 0x1296, 0x1491, 0x4e92, 0xe162, ++ 0x04a4, 0x1444, 0xa002, 0x4e44, 0xa200, 0x4e52, 0x4e50, 0x1640, ++ 0xa002, 0xe012, 0x4854, 0x4e55, 0xa2fe, 0x4e56, 0xa200, 0x4e53, ++ 0xe161, 0x018a, 0x1491, 0xf136, 0x1681, 0xc000, 0x0e23, 0xc001, ++ 0xf026, 0x0e40, 0xc000, 0x0623, 0xc001, 0x0854, 0x0e55, 0xf076, ++ 0x0054, 0x0655, 0x4854, 0x4e55, 0x1453, 0x4e56, 0x8091, 0x8091, ++ 0x1453, 0xa002, 0x4e53, 0x0c44, 0xf668, 0x1456, 0xf164, 0x0456, ++ 0x0456, 0xe000, 0x018a, 0xe09e, 0x1487, 0x4e92, 0xa200, 0x4e97, ++ 0x1497, 0x4e92, 0x1497, 0x4e92, 0x1450, 0xa002, 0x4e50, 0x1452, ++ 0xa002, 0x4e52, 0x0c44, 0xf448, 0xa200, 0x4e52, 0x4e51, 0xa220, ++ 0x4e54, 0xa2fe, 0x4e55, 0xa200, 0x4e53, 0xe161, 0x018a, 0x1491, ++ 0xf082, 0x1481, 0x0c54, 0xf052, 0x0454, 0x4e54, 0x1453, 0x4e55, ++ 0x8091, 0x8091, 0x1453, 0xa002, 0x4e53, 0x0c44, 0xf718, 0x1455, ++ 0xf164, 0x0455, 0x0455, 0xe000, 0x018a, 0xe09e, 0x1487, 0x4e92, ++ 0xa200, 0x4e97, 0x1497, 0x4e92, 0x1497, 0x4e92, 0x1451, 0xa002, ++ 0x4e51, 0x1452, 0xa002, 0x4e52, 0x0c44, 0xf528, 0x1450, 0x0451, ++ 0x4e44, 0x0c41, 0xa102, 0xf1e4, 0x1444, 0xa102, 0x4e44, 0x1450, ++ 0x0450, 0x0450, 0xe000, 0x04a4, 0xe094, 0xa106, 0xe092, 0xa004, ++ 0xe09e, 0x1487, 0xe412, 0x1106, 0x1451, 0xf0ca, 0xa102, 0xcc44, ++ 0xe184, 0x132f, 0x1492, 0x4e91, 0x1492, 0x4e91, 0x1492, 0x4e91, ++ 0xe190, 0xe42e, 0x1552, 0xc001, 0x4e22, 0xa002, 0x4e21, 0x4f23, ++ 0xc000, 0x1450, 0x1551, 0xc001, 0x4e24, 0x4f25, 0xbc0c, 0x4e20, ++ 0xc000, 0xe42d, 0xe40a, 0x1381, 0xa102, 0xe40a, 0x13bd, 0xa102, ++ 0xe40a, 0x13dc, 0xa106, 0xe406, 0x1352, 0xa102, 0xe40a, 0x14c6, ++ 0xe16b, 0xe42e, 0xc001, 0xba40, 0x4e2a, 0xc000, 0xe41e, 0x07f2, ++ 0xe42d, 0xc001, 0xa002, 0x4e2b, 0xc000, 0xe42e, 0xc001, 0xa200, ++ 0x4e2e, 0x1420, 0xc000, 0xa106, 0xe424, 0xa104, 0xe420, 0xc001, ++ 0x1423, 0x042b, 0xa102, 0xc70f, 0x3c2b, 0xe008, 0xffff, 0xe41e, ++ 0x1503, 0x4e2e, 0x562e, 0x4e2c, 0x822c, 0x812b, 0xe018, 0x3223, ++ 0x4e2c, 0x1420, 0xa108, 0xe404, 0x1430, 0xe40a, 0x149b, 0xe40e, ++ 0x149b, 0xe161, 0x05b0, 0xc001, 0x8822, 0x0022, 0xc000, 0xe184, ++ 0x138d, 0xe41e, 0x07f2, 0xe42d, 0xa002, 0x4e91, 0xc001, 0xe161, ++ 0x05b0, 0xe162, 0x05c0, 0xa200, 0x4e27, 0x4e37, 0x4e28, 0x4e29, ++ 0x1437, 0xa002, 0x4e37, 0x0c81, 0xf0e6, 0xa200, 0x4e37, 0x1427, ++ 0xa002, 0x4e27, 0x8091, 0x0c22, 0xf746, 0xa200, 0x4e27, 0xe161, ++ 0x05b0, 0xf6fe, 0x1427, 0x4e92, 0x1428, 0xa002, 0x4e28, 0x0c24, ++ 0xf684, 0x4e28, 0xe41e, 0x14e6, 0x1429, 0xa002, 0x4e29, 0x0c25, ++ 0xe162, 0x05c0, 0xf5e4, 0xc000, 0xe42e, 0xc001, 0xa200, 0x4e29, ++ 0xe162, 0x05c0, 0x8229, 0x8121, 0xe018, 0xaf02, 0xc70f, 0x3c21, ++ 0xaf20, 0x1524, 0xa103, 0xcc45, 0xe184, 0x13d2, 0x4e92, 0xa002, ++ 0xe049, 0x0d21, 0xb616, 0xe41e, 0x14e6, 0x1429, 0xa002, 0x4e29, ++ 0x0c25, 0xf674, 0xc000, 0xe42e, 0xe167, 0x05b0, 0xc001, 0x1422, ++ 0xc000, 0xa102, 0xcc44, 0xe184, 0x13ec, 0xe41e, 0x07f2, 0xe42d, ++ 0x4e97, 0xe41e, 0x07f2, 0xe42d, 0x4e97, 0xc001, 0xe162, 0x05c0, ++ 0x1424, 0xa102, 0x4e3b, 0x1421, 0xa102, 0x833b, 0x4e92, 0xa200, ++ 0x4e29, 0xe41e, 0x14e6, 0x1429, 0xa002, 0x4e29, 0x0c25, 0xf7a4, ++ 0x1421, 0xa104, 0x4e27, 0x1427, 0xae02, 0xe000, 0x05b0, 0xe092, ++ 0x1491, 0xc70f, 0x3c24, 0x4837, 0x4e39, 0x1491, 0xc70f, 0x3c24, ++ 0x4838, 0x4e3a, 0x1439, 0x4e29, 0x0c3a, 0xf150, 0xe41e, 0x14e8, ++ 0x1437, 0xe000, 0x05c0, 0xe094, 0x1438, 0x0c37, 0xf054, 0x4e3b, ++ 0x1427, 0x833b, 0x4e92, 0xe41e, 0x14e6, 0x1429, 0xa002, 0x4e29, ++ 0x0c3a, 0xf6d6, 0x1427, 0xa102, 0x4e27, 0xf562, 0xc000, 0xe42e, ++ 0xe162, 0x0124, 0xa2fe, 0xc765, 0x4e92, 0x8224, 0x142c, 0xe40a, ++ 0x1483, 0x1424, 0x0c2a, 0xaf02, 0x4e28, 0x1425, 0x0c2a, 0xaf02, ++ 0x4e29, 0x1424, 0xa102, 0x4e3e, 0x1425, 0xa102, 0x4e3f, 0xa2fe, ++ 0x042a, 0x4e3b, 0xa200, 0x042a, 0x4e3c, 0xa200, 0x4e37, 0x4e38, ++ 0x4e39, 0xa202, 0x4e3a, 0xe41e, 0x150a, 0xf0aa, 0x1481, 0xe05a, ++ 0x4e81, 0x1437, 0xa002, 0x4e37, 0x1437, 0x0c2c, 0xf25a, 0x1428, ++ 0x043b, 0xa400, 0x323e, 0x4e28, 0x1429, 0x043c, 0xa400, 0x323f, ++ 0x4e29, 0x1439, 0xa002, 0x4e39, 0x0c3a, 0xf668, 0x4e39, 0x143a, ++ 0x0438, 0x4e3a, 0xa202, 0x0c38, 0x4e38, 0x142a, 0xf078, 0x143b, ++ 0x153c, 0xe013, 0x4f3b, 0x4e3c, 0xf57e, 0x143b, 0x153c, 0xe012, ++ 0x4f3b, 0x4e3c, 0xf51e, 0xa200, 0x4e29, 0xe162, 0x05c0, 0xa200, ++ 0x4e28, 0xe41e, 0x150a, 0xe01a, 0x4e92, 0x1428, 0xa002, 0x4e28, ++ 0x0c24, 0xf784, 0xe41e, 0x14e6, 0x1429, 0xa002, 0x4e29, 0x0c25, ++ 0xf6d4, 0xc000, 0xe42e, 0x142a, 0xf038, 0x142c, 0xf03e, 0x1423, ++ 0x0c2c, 0x4e37, 0xa200, 0x4e29, 0xe162, 0x05c0, 0xa200, 0x4e28, ++ 0x8224, 0x8129, 0xe018, 0x0428, 0x1520, 0xa109, 0xf05b, 0x8225, ++ 0x8128, 0xe018, 0x0429, 0x0c37, 0x152a, 0xf024, 0xe017, 0x4f92, ++ 0x1428, 0xa002, 0x4e28, 0x0c24, 0xf6c4, 0xe41e, 0x14e6, 0x1429, ++ 0xa002, 0x4e29, 0x0c25, 0xf614, 0xc000, 0xe42e, 0xe41e, 0x07f2, ++ 0xe42d, 0xc001, 0xa002, 0x0c23, 0xe408, 0x1350, 0x1422, 0xe41e, ++ 0x1503, 0x4e37, 0xa200, 0x4e29, 0xe162, 0x05c0, 0x1424, 0xa102, ++ 0xcc44, 0xe184, 0x14dc, 0x5637, 0x4e92, 0xe41e, 0x14e6, 0x1429, ++ 0xa002, 0x4e29, 0x0c25, 0xf714, 0xc000, 0xe42e, 0xa204, 0xf02e, ++ 0xa206, 0x4e35, 0x1429, 0xae0e, 0xe0c1, 0x0047, 0xf04b, 0xe005, ++ 0x0126, 0xf03e, 0xe005, 0x0444, 0xae11, 0xe042, 0xe0c1, 0x0041, ++ 0xe042, 0xce20, 0xd111, 0x05c0, 0xd112, 0x0040, 0x8835, 0x0113, ++ 0xca28, 0xf7f8, 0xe42e, 0xa201, 0xf04a, 0xaf02, 0xa003, 0xf7e8, ++ 0xe04a, 0xe42e, 0x8129, 0xe018, 0x0428, 0x4e26, 0xaf08, 0xe000, ++ 0x0124, 0xe092, 0x1426, 0xa81e, 0x4e3d, 0xa203, 0x353d, 0x1481, ++ 0xe052, 0xe42e, 0xa200, 0xba4f, 0xe042, 0xe003, 0x00ff, 0xf7cb, ++ 0x4e00, 0xa200, 0xba4f, 0xe042, 0xe003, 0x00ff, 0xf7cb, 0x4e01, ++ 0xe41e, 0x1531, 0xe42a, 0xe41e, 0x043e, 0xf6d8, 0xe41e, 0x083b, ++ 0xe42e, 0x1400, 0xf0ba, 0xa102, 0xf0ca, 0xa104, 0xf0da, 0xa102, ++ 0xf0ea, 0xa102, 0xf0fa, 0xa200, 0xe42e, 0xe41e, 0x1554, 0xf0de, ++ 0xe41e, 0x1578, 0xf0ae, 0xe41e, 0x15b8, 0xf07e, 0xe41e, 0x15c8, ++ 0xf04e, 0xe41e, 0x15d6, 0xf01e, 0xe42a, 0xc864, 0xa80e, 0xe016, ++ 0xe428, 0xe41e, 0x083b, 0xe42e, 0xe41e, 0x07f2, 0x0c21, 0xf09a, ++ 0x0421, 0x4e21, 0xe41e, 0x0aff, 0xe12c, 0xa201, 0x4f3a, 0xe42a, ++ 0x1415, 0xe161, 0x05a6, 0xe418, 0x156c, 0x1416, 0xe161, 0x05ab, ++ 0xe418, 0x156c, 0xa202, 0xe42e, 0x1491, 0xa102, 0xcc44, 0xe184, ++ 0x1576, 0x1481, 0xe41e, 0x082f, 0x1481, 0xe41e, 0x082f, 0xe42e, ++ 0x1415, 0xe161, 0x05a8, 0xf038, 0xe161, 0x05ad, 0x2616, 0xf09a, ++ 0x1491, 0xe41e, 0x082f, 0x1491, 0xe41e, 0x082f, 0x1491, 0xf02e, ++ 0xa230, 0x4e02, 0x1417, 0xe016, 0xe428, 0xba46, 0xa112, 0xb604, ++ 0xe42a, 0xe000, 0x044d, 0xe092, 0x1481, 0xa102, 0xcc44, 0xe184, ++ 0x15b5, 0xba40, 0xf1ba, 0xba42, 0xba40, 0xba48, 0xba40, 0x4e03, ++ 0xba40, 0xba40, 0xba4e, 0x1403, 0xf058, 0xba4a, 0xba4a, 0xba48, ++ 0xf0ae, 0xba40, 0xf08a, 0xba4a, 0xba40, 0xf05a, 0xba4a, 0xba40, ++ 0xf02a, 0xba48, 0x1402, 0xe41e, 0x082f, 0xe190, 0xa202, 0xe42e, ++ 0x1401, 0xf0da, 0xa102, 0xcc44, 0xe004, 0x00ff, 0xe184, 0x15c1, ++ 0xba4f, 0xe052, 0xe002, 0x00ff, 0xe016, 0xe42a, 0xa202, 0xe42e, ++ 0xa202, 0xba4f, 0xe003, 0x00ff, 0xf039, 0xba4f, 0xa204, 0xba4f, ++ 0xa002, 0x1501, 0xe045, 0xf7c1, 0xa202, 0xe42e, 0x1401, 0xa420, ++ 0xa102, 0xcc44, 0xe184, 0x15dd, 0xba4e, 0xe190, 0xa202, 0xe42e, ++ 0x1411, 0xa104, 0xe428, 0xc001, 0xe41e, 0x1706, 0xc000, 0xe42e, ++ 0x1433, 0xf05a, 0x1411, 0xa102, 0xf0b4, 0xf0da, 0x1438, 0xc001, ++ 0x4e51, 0xe41e, 0x110d, 0xe41e, 0x1741, 0xc000, 0xe42e, 0xe41e, ++ 0x1641, 0xf03e, 0xe41e, 0x1681, 0x1432, 0xc001, 0x154c, 0xf058, ++ 0xf06b, 0xa200, 0x4856, 0x4e57, 0xe41e, 0x1706, 0x1460, 0xae02, ++ 0xe000, 0x04d7, 0xe092, 0x1056, 0x2657, 0x4891, 0x4e91, 0x1460, ++ 0xe000, 0x04f9, 0xe092, 0xc000, 0x1438, 0xc001, 0x4e91, 0x1460, ++ 0xa002, 0x4e60, 0xe41e, 0x1125, 0xf048, 0xe41e, 0x170b, 0xf7be, ++ 0xc000, 0xe42e, 0xc001, 0xf04a, 0xe41e, 0x1706, 0xf06e, 0x1464, ++ 0xf04a, 0xa102, 0x4e64, 0xf13e, 0x1463, 0xf11a, 0x1462, 0xe000, ++ 0x050a, 0xe092, 0x1462, 0xa002, 0x4e62, 0xa122, 0xf028, 0x4e62, ++ 0x1463, 0xa102, 0x4e63, 0x1481, 0xc000, 0xe42e, 0xa2fe, 0xc000, ++ 0xe42e, 0xa203, 0x3512, 0xaf03, 0x1432, 0xc001, 0x4f68, 0x1569, ++ 0xf078, 0xf099, 0x106a, 0x266b, 0x116c, 0x276d, 0xf07e, 0xa200, ++ 0xa201, 0xf04e, 0xa200, 0x116e, 0x276f, 0x4850, 0x4e51, 0x4952, ++ 0x4f53, 0x171a, 0x0952, 0x0f53, 0xf071, 0xe013, 0x0f68, 0xf085, ++ 0x0668, 0x0668, 0xf05e, 0x0f68, 0xf037, 0x0e68, 0x0e68, 0x4854, ++ 0x4e55, 0x061a, 0xe049, 0x0118, 0x0719, 0xe065, 0x4956, 0x4f57, ++ 0xc000, 0x1530, 0xc001, 0xf0ab, 0x486e, 0x4e6f, 0x1054, 0x2655, ++ 0x486a, 0x4e6b, 0x161a, 0x486c, 0x4e6d, 0x144c, 0x4e69, 0xc000, ++ 0xe42e, 0x1423, 0xa203, 0x3510, 0xc001, 0x4e50, 0x4f51, 0xc000, ++ 0x1432, 0xe016, 0x1530, 0xc001, 0x4f52, 0xf07a, 0x106e, 0x266f, ++ 0x176d, 0x0f50, 0xf027, 0x0651, 0x486e, 0x4e6f, 0x146c, 0xf30a, ++ 0x106e, 0x266f, 0x0650, 0xf2c6, 0x1552, 0xe017, 0xe046, 0xa102, ++ 0xf274, 0xe188, 0x000f, 0x3c6c, 0x4853, 0x4e54, 0xe41e, 0x16e6, ++ 0x146c, 0xa102, 0xcc44, 0xe161, 0x0104, 0xa200, 0xe184, 0x16b1, ++ 0x0091, 0x0691, 0xae02, 0x4856, 0xe008, 0xffff, 0xaf02, 0x4e57, ++ 0x8254, 0x8156, 0xe018, 0xae1e, 0x8157, 0xe01c, 0xe161, 0x0104, ++ 0x8853, 0x0022, 0xe184, 0x16c5, 0x0091, 0x0691, 0xf02e, 0xa200, ++ 0x1552, 0xf039, 0x0068, 0x0669, 0x0018, 0x0619, 0xe049, 0x016a, ++ 0x076b, 0x011a, 0x071b, 0x4956, 0x4f57, 0x1156, 0x2757, 0xe066, ++ 0x4856, 0x4e57, 0x1450, 0x4e6d, 0x144c, 0xc000, 0xe42a, 0xc001, ++ 0xa200, 0x486e, 0x4e6f, 0x4e6d, 0xc000, 0xe42e, 0xe0c0, 0x0047, ++ 0xf0aa, 0xe0c0, 0x0041, 0xe0c1, 0x005a, 0xae19, 0xe042, 0xe005, ++ 0x00a2, 0xf09e, 0xe0c0, 0x0041, 0xe0c1, 0x005a, 0xae1b, 0xe042, ++ 0xe005, 0x00a2, 0xae11, 0xe042, 0xce20, 0xd111, 0x0104, 0xd112, ++ 0x0200, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e, 0x1460, 0xe42a, ++ 0xe41e, 0x170b, 0xf7ce, 0xe161, 0x04d7, 0xe162, 0x04d7, 0x1091, ++ 0x2691, 0xa201, 0x4f50, 0xa203, 0x1460, 0xa104, 0xf0e4, 0xcc44, ++ 0xe184, 0x1723, 0x1092, 0x268a, 0x0891, 0x0e91, 0xf054, 0xe082, ++ 0xa104, 0xe094, 0x4f50, 0xa003, 0xe084, 0xa004, 0xe092, 0x1450, ++ 0xe000, 0x04f9, 0xe098, 0xa002, 0xe096, 0x1484, 0x4e51, 0xe41e, ++ 0x110d, 0x1460, 0x0c50, 0xa104, 0xf0a4, 0xcc44, 0xe184, 0x173d, ++ 0x1491, 0x4e92, 0x1491, 0x4e92, 0x1493, 0x4e94, 0x1460, 0xa102, ++ 0x4e60, 0x1461, 0xe000, 0x050a, 0xe092, 0x1451, 0x4e81, 0x1461, ++ 0xa002, 0x4e61, 0xa122, 0xf028, 0x4e61, 0x1463, 0xa002, 0x4e63, ++ 0xe42e, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe0c0, 0x0040, 0xe0c1, 0x005b, 0xae1d, 0xe042, 0xce20, 0xd111, ++ 0x0000, 0xd112, 0x0800, 0xd113, 0x000b, 0xca28, 0xf7f8, 0xe42e, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0x0000, 0x002f, 0x0010, 0x001f, 0x0001, 0x000f, 0x0002, 0x0000, ++ 0x0004, 0x0017, 0x0008, 0x001b, 0x0020, 0x001d, 0x0003, 0x001e, ++ 0x0005, 0x0007, 0x000a, 0x000b, 0x000c, 0x000d, 0x000f, 0x000e, ++ 0x002f, 0x0027, 0x0007, 0x002b, 0x000b, 0x002d, 0x000d, 0x002e, ++ 0x000e, 0x0010, 0x0006, 0x0003, 0x0009, 0x0005, 0x001f, 0x000a, ++ 0x0023, 0x000c, 0x0025, 0x0013, 0x002a, 0x0015, 0x002c, 0x001a, ++ 0x0021, 0x001c, 0x0022, 0x0023, 0x0024, 0x0025, 0x0028, 0x002a, ++ 0x0027, 0x002c, 0x002b, 0x0001, 0x002d, 0x0002, 0x002e, 0x0004, ++ 0x0011, 0x0008, 0x0012, 0x0011, 0x0014, 0x0012, 0x0018, 0x0014, ++ 0x0013, 0x0018, 0x0015, 0x0006, 0x001a, 0x0009, 0x001c, 0x0016, ++ 0x0017, 0x0019, 0x001b, 0x0020, 0x001d, 0x0021, 0x001e, 0x0022, ++ 0x0016, 0x0024, 0x0019, 0x0028, 0x0026, 0x0026, 0x0029, 0x0029, ++ 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007, ++ 0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f, ++ 0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017, ++ 0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001d, 0x001e, ++ 0x001f, 0x0020, 0x0020, 0x0021, 0x0022, 0x0022, 0x0023, 0x0023, ++ 0x0024, 0x0024, 0x0025, 0x0025, 0x0025, 0x0026, 0x0026, 0x0026, ++ 0x0027, 0x0027, 0x0027, 0x0027, 0x0001, 0x0001, 0x0001, 0x0002, ++ 0x0002, 0x0003, 0x0003, 0x0002, 0x0003, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0xc864, 0xa80e, 0x4e4e, 0x564e, 0xa200, 0x4e00, 0x1400, 0xaf06, ++ 0xa802, 0xae0c, 0x1500, 0xaf05, 0xa803, 0xae09, 0xe042, 0x1500, ++ 0xaf0f, 0xae0f, 0xe042, 0x1500, 0xaf0d, 0xa803, 0xae0b, 0xe042, ++ 0x1500, 0xaf09, 0xa807, 0xae05, 0xe042, 0xce92, 0xd022, 0x0003, ++ 0xe184, 0x1123, 0xba4e, 0xce94, 0x1400, 0xa008, 0x4e00, 0xe002, ++ 0x0100, 0xf5d8, 0x1400, 0xaf04, 0xa802, 0xae08, 0x1500, 0xaf0d, ++ 0xae0d, 0xe042, 0x1500, 0xaf0b, 0xa803, 0xae0b, 0xe042, 0x1500, ++ 0xaf07, 0xa807, 0xae05, 0xe042, 0xce92, 0xd022, 0x0003, 0xe184, ++ 0x1142, 0xba4e, 0xce94, 0x1400, 0xa008, 0x4e00, 0xe002, 0x0180, ++ 0xf628, 0xe42e, 0x145c, 0xe418, 0x1158, 0xe42d, 0xe41e, 0x116b, ++ 0xe42d, 0x1460, 0xe418, 0x11a7, 0xe42d, 0xe41e, 0x11b9, 0xe42e, ++ 0x1466, 0xe09c, 0x1096, 0x268e, 0xced6, 0xd160, 0x0000, 0xcad0, ++ 0xa000, 0x4e03, 0xa2fe, 0xce90, 0xd151, 0x0000, 0xd040, 0x0010, ++ 0xe41e, 0x11ea, 0xe42e, 0x1466, 0xe09c, 0x1096, 0x268e, 0xced6, ++ 0xd160, 0x0000, 0xa220, 0x0c5c, 0xcc80, 0xa200, 0x4e04, 0x4e00, ++ 0x145f, 0xa802, 0xf18a, 0xa200, 0x4e05, 0x1404, 0xce90, 0x885c, ++ 0x0151, 0xcad0, 0xa000, 0x4e03, 0xe41e, 0x11ea, 0xe42d, 0x1401, ++ 0xced2, 0x1405, 0xa002, 0x4e05, 0xa108, 0x1504, 0xa003, 0x4f04, ++ 0xf6d8, 0xf08e, 0xced2, 0xced2, 0xced2, 0xced2, 0x1404, 0xa008, ++ 0x4e04, 0x1400, 0xa002, 0x4e00, 0xa108, 0x155f, 0xaf03, 0x4f5f, ++ 0xf588, 0xcad6, 0x4896, 0x4e96, 0xe08c, 0x4e66, 0xe42e, 0xa208, ++ 0x4e03, 0xd040, 0x0004, 0xa220, 0xce90, 0xd151, 0x0000, 0xe41e, ++ 0x11ea, 0xe42d, 0xa222, 0xce90, 0xd151, 0x0000, 0xe41e, 0x11ea, ++ 0xe42e, 0x1460, 0xa104, 0x1567, 0xe09d, 0xf268, 0x1096, 0x268e, ++ 0xcede, 0xd160, 0x0000, 0xd040, 0x000f, 0xa224, 0x4e04, 0xa200, ++ 0x4e05, 0x1404, 0xce90, 0xd151, 0x0001, 0xcad8, 0xa000, 0x4e03, ++ 0xe41e, 0x11ea, 0xe42d, 0x1401, 0xceda, 0x1405, 0xa002, 0x4e05, ++ 0xa110, 0x1504, 0xa003, 0x4f04, 0xf6d8, 0xcade, 0x4896, 0x4e96, ++ 0xe08c, 0x4e67, 0xe42e, 0xa200, 0xcedc, 0x4e96, 0x4e96, 0xe08c, ++ 0x4e67, 0xe42e, 0xe41e, 0x1200, 0xe42d, 0xbf08, 0x1401, 0xd158, ++ 0x0000, 0xe42d, 0xe42a, 0xa104, 0xcc44, 0xf064, 0xe184, 0x11f9, ++ 0xbf04, 0xcea6, 0xe42d, 0xc88c, 0xcea6, 0xd150, 0x0000, 0xe42e, ++ 0x5003, 0xcea8, 0xe42d, 0xaf04, 0x4e01, 0xcc82, 0xe42a, 0xcaa8, ++ 0xa806, 0x4e02, 0xcc84, 0xe090, 0xd158, 0x0000, 0x1401, 0x0c02, ++ 0x9280, 0xceab, 0xe42a, 0xcaac, 0xcc86, 0xbf00, 0xe42d, 0xbf06, ++ 0xcea4, 0x1401, 0x0c02, 0xa104, 0xcc44, 0xe424, 0xe184, 0x1223, ++ 0xbf02, 0xe42d, 0xbf06, 0xcea4, 0xe42e, 0xe161, 0x0376, 0xd022, ++ 0x002d, 0xa2fc, 0x4e00, 0xe184, 0x122f, 0x1481, 0x2200, 0x4e91, ++ 0xca40, 0x2200, 0xce40, 0xca46, 0x2200, 0xce46, 0xe42e, 0xe004, ++ 0x0376, 0x4e64, 0xe004, 0x0100, 0x4e65, 0xe004, 0x012d, 0x4e66, ++ 0xe004, 0x0187, 0x4e67, 0xe004, 0x01e1, 0x4e68, 0xa2fd, 0xca40, ++ 0xe052, 0xce40, 0xca46, 0xe052, 0xce46, 0xe42e, 0x1454, 0xe41a, ++ 0x1237, 0x1464, 0xe09c, 0x1496, 0xce42, 0x1486, 0xce44, 0xca4a, ++ 0xcec4, 0xcf34, 0xca4c, 0x151e, 0xb7f6, 0xca4b, 0xe052, 0xcec2, ++ 0x4e69, 0xe42e, 0x1464, 0xe09c, 0x145a, 0x4e96, 0xce40, 0xca42, ++ 0xce46, 0xe08c, 0x4e64, 0x1454, 0xa002, 0x4e54, 0x0c50, 0xe428, ++ 0xa200, 0x4e54, 0x1455, 0xa002, 0x4e55, 0x0c51, 0xe42e, 0xe049, ++ 0x1466, 0xe09c, 0x1096, 0x268e, 0xced6, 0xa200, 0xcec0, 0xd022, ++ 0x000f, 0xe184, 0x1284, 0xced3, 0xe190, 0xcad6, 0x4896, 0x4e96, ++ 0xe08c, 0x4e66, 0x1467, 0xe09c, 0xcad6, 0xcedc, 0x4896, 0x4e96, ++ 0xe08c, 0x4e67, 0xe42e, 0x1465, 0xe09c, 0xe004, 0x2222, 0x4e96, ++ 0xcecc, 0xe08c, 0x4e65, 0xe42e, 0x1468, 0xe09c, 0xa220, 0xae34, ++ 0x4896, 0x4e96, 0x4896, 0x4e96, 0x4896, 0x4e96, 0x1196, 0x278e, ++ 0xcf33, 0x4896, 0x4e96, 0xcf20, 0xcf22, 0xcf24, 0xcf26, 0xa200, ++ 0x4e96, 0xe08c, 0x4e68, 0xe42e, 0x1468, 0xe09c, 0x1096, 0x2696, ++ 0xcf28, 0x1096, 0x2696, 0xcf2a, 0x1096, 0x2696, 0xcf2c, 0x1096, ++ 0x2696, 0xcf2e, 0x8896, 0x01ab, 0x1096, 0x2696, 0xcf30, 0xe42e, ++ 0x1468, 0xe09c, 0xcb28, 0x4896, 0x4e96, 0xcb2a, 0x4896, 0x4e96, ++ 0xcb2c, 0x4896, 0x4e96, 0xcb2e, 0x4896, 0x4e96, 0x8996, 0x01ab, ++ 0xe08c, 0x4e68, 0xe42e, 0xe41e, 0x137c, 0xe41e, 0x1390, 0xc000, ++ 0xe42e, 0xc001, 0xba40, 0xf098, 0xe41e, 0x136e, 0xc000, 0xe41e, ++ 0x13ac, 0xa202, 0x4e3b, 0xe42e, 0xc000, 0x1423, 0x1525, 0xc001, ++ 0x4e50, 0x4f53, 0xa200, 0xe163, 0x05b0, 0xc70f, 0x4e93, 0xe162, ++ 0x0450, 0xbc06, 0xe40d, 0x1350, 0xf06a, 0xa102, 0xf12a, 0xa102, ++ 0xf18a, 0xf39e, 0xc000, 0xe41e, 0x07f2, 0xe40d, 0x1350, 0xc001, ++ 0xa002, 0x0e50, 0xe012, 0xf022, 0x0640, 0x4e50, 0xa203, 0xf0be, ++ 0xc000, 0xe41e, 0x07f2, 0xa002, 0xc001, 0x0650, 0x0e40, 0xf74e, ++ 0xbc20, 0xa2ff, 0x4e51, 0x4f52, 0x1445, 0xf33a, 0xa102, 0xcc44, ++ 0xc410, 0xe161, 0x0460, 0xe163, 0x05b0, 0xe184, 0x1338, 0x1491, ++ 0x1791, 0x0c52, 0x0f51, 0xf0c8, 0xf0b9, 0x80a9, 0x80b1, 0x1481, ++ 0x4e92, 0xa202, 0x4e83, 0x1453, 0xa102, 0x4e53, 0xf43e, 0x8091, ++ 0x8093, 0xf17e, 0xc418, 0xe161, 0x045f, 0xe163, 0x05b0, 0x1453, ++ 0xf0a4, 0x1493, 0x80b1, 0xf7e8, 0x1481, 0x4e92, 0x1453, 0xa102, ++ 0x4e53, 0xf76e, 0xc000, 0xe41e, 0x13ac, 0xa202, 0x4e3b, 0xe42e, ++ 0xe16a, 0xc000, 0xa200, 0xe42e, 0x8825, 0x0022, 0xe162, 0x0450, ++ 0xe163, 0x02c0, 0xe184, 0x136c, 0x1482, 0xae04, 0x0482, 0x0492, ++ 0xa400, 0xe000, 0x0600, 0xe09e, 0x1097, 0x2697, 0x9f13, 0x1097, ++ 0x2697, 0x9f13, 0x1097, 0x2697, 0x9f13, 0xe42e, 0x1445, 0xe42a, ++ 0xa102, 0xcc44, 0xc418, 0xe161, 0x0462, 0xe162, 0x0450, 0xe184, ++ 0x137a, 0x14b1, 0x4e92, 0xe42e, 0x1438, 0xae04, 0x0438, 0x0438, ++ 0xe000, 0x0600, 0xe09e, 0x1097, 0x2697, 0xe0c2, 0x0188, 0x1097, ++ 0x2697, 0xe0c2, 0x0189, 0x1097, 0x2697, 0xe0c2, 0x018a, 0xe42e, ++ 0xc001, 0xe41e, 0x136e, 0xe163, 0x078e, 0xa2fe, 0xc71f, 0x4e93, ++ 0x1445, 0xe42a, 0xa102, 0xcc44, 0xe162, 0x0450, 0xa201, 0xe184, ++ 0x13aa, 0x1492, 0xa400, 0xe000, 0x078e, 0xe096, 0x1483, 0xf032, ++ 0x4f83, 0xa003, 0xe190, 0xe42e, 0xe164, 0x05c0, 0xa200, 0xc70f, ++ 0x4e94, 0x8825, 0x0022, 0xe162, 0x0450, 0xe164, 0x05c0, 0xa201, ++ 0xe184, 0x13c0, 0x1492, 0xe000, 0x078e, 0xe096, 0x1483, 0xa81e, ++ 0x4e94, 0xe164, 0x05c0, 0xd022, 0x0007, 0xe184, 0x13c8, 0xae08, ++ 0x2694, 0xcf50, 0xd022, 0x0007, 0xe184, 0x13cf, 0xae08, 0x2694, ++ 0xcf52, 0xe42e, 0xc001, 0xe12f, 0xa200, 0x4e30, 0x4e31, 0xe41e, ++ 0x144c, 0x1431, 0xa002, 0x4e31, 0x0c21, 0xf7a4, 0xa200, 0x4e26, ++ 0x4e28, 0x4e29, 0xe41e, 0x1443, 0x4e31, 0xc001, 0x1426, 0x0c23, ++ 0xe402, 0x143d, 0x1426, 0xe002, 0x000a, 0xf028, 0xe190, 0xc001, ++ 0xe41e, 0x1443, 0x4e27, 0x0c31, 0xe418, 0x1503, 0x1427, 0x4e31, ++ 0x1430, 0xe41a, 0x1508, 0x1426, 0xc000, 0x4e53, 0xc001, 0x1428, ++ 0x1529, 0xc000, 0x4e54, 0x4f55, 0xc001, 0xe41e, 0x153a, 0x1430, ++ 0xc000, 0xf09a, 0xe41e, 0x0d5a, 0xf0bc, 0xe16a, 0xa200, 0xc001, ++ 0x4e30, 0xc000, 0xe41e, 0x0de4, 0x1435, 0xa002, 0x4e35, 0xe41e, ++ 0x0e03, 0xe41e, 0x1699, 0xc001, 0xe41e, 0x1571, 0x1426, 0xa002, ++ 0x4e26, 0x1428, 0xa002, 0x4e28, 0x0c24, 0xf058, 0x4e28, 0x1429, ++ 0xa002, 0x4e29, 0x1430, 0xe40a, 0x13e5, 0xc000, 0x145b, 0xa102, ++ 0xe400, 0x13e5, 0xe41e, 0x043e, 0xe408, 0x13e5, 0xe41e, 0x083b, ++ 0xc001, 0xa200, 0x4e30, 0xe40e, 0x13e5, 0x1426, 0xc000, 0x4e53, ++ 0xe12c, 0xc000, 0xe42e, 0x1428, 0xe41a, 0x1587, 0xe004, 0x074e, ++ 0x0428, 0xe094, 0x1482, 0xe42e, 0xc000, 0xe161, 0x05b0, 0x4e91, ++ 0x1420, 0x4e91, 0x1425, 0x4e91, 0x1426, 0x4e91, 0x1427, 0x4e91, ++ 0x1428, 0x4e91, 0x1429, 0x4e91, 0x145b, 0x4e91, 0x1461, 0x4e91, ++ 0xc001, 0x1430, 0xc000, 0x4e91, 0x1445, 0x4e91, 0x1442, 0x4e91, ++ 0xe162, 0x0450, 0xd022, 0x000f, 0xe184, 0x146f, 0x1492, 0x4e91, ++ 0xcb50, 0x4891, 0x4e91, 0xcb52, 0x4891, 0x4e91, 0x8991, 0x0032, ++ 0x8991, 0x0033, 0xc860, 0x4891, 0x4e91, 0xc862, 0x4891, 0x4e91, ++ 0x8991, 0x0034, 0x8991, 0x0035, 0x8991, 0x0036, 0x8991, 0x0037, ++ 0xc001, 0x1431, 0xae0e, 0xe0c1, 0x0047, 0xf04b, 0xe005, 0x0122, ++ 0xf03e, 0xe005, 0x0440, 0xae11, 0xe042, 0xe0c1, 0x0041, 0xe042, ++ 0xce20, 0xd111, 0x05b0, 0xd112, 0x0040, 0xd113, 0x0002, 0xca28, ++ 0xf7f8, 0xc001, 0xe42e, 0x1427, 0xae0e, 0xe0c1, 0x0047, 0xf04b, ++ 0xe005, 0x0122, 0xf03e, 0xe005, 0x0440, 0xae11, 0xe042, 0xe0c1, ++ 0x0041, 0xe042, 0xce20, 0xd111, 0x05b0, 0xd112, 0x0040, 0xd113, ++ 0x0003, 0xca28, 0xf7f8, 0xe161, 0x05b0, 0xc000, 0x1491, 0x1491, ++ 0x4e20, 0x1491, 0x4e25, 0x1491, 0x4e26, 0x1491, 0x4e27, 0x1491, ++ 0x4e28, 0x1491, 0x4e29, 0x1491, 0x4e5b, 0x1491, 0x4e61, 0x1491, ++ 0xc001, 0x4e30, 0xc000, 0x1491, 0x4e45, 0x1491, 0x4e42, 0xe162, ++ 0x0450, 0xd022, 0x000f, 0xe184, 0x14de, 0x1491, 0x4e92, 0xa202, ++ 0x4e3b, 0x1091, 0x2691, 0xcf50, 0x1091, 0x2691, 0xcf52, 0x1427, ++ 0xae0a, 0x2628, 0xae0a, 0x2629, 0xce4e, 0xc001, 0x1427, 0x4e07, ++ 0x8891, 0x0032, 0x8891, 0x0033, 0x1091, 0x2691, 0xcc60, 0x1091, ++ 0x2691, 0xcc62, 0x8891, 0x0034, 0x8891, 0x0035, 0x8891, 0x0036, ++ 0x8891, 0x0037, 0xe42e, 0xe41e, 0x144c, 0xe41e, 0x14a3, 0xe42e, ++ 0x1426, 0x1527, 0xe41e, 0x0705, 0xe42a, 0xc000, 0xe41e, 0x0c69, ++ 0xe16a, 0xe42a, 0x1426, 0x4e61, 0xa200, 0x4e5b, 0x1427, 0xae0a, ++ 0x2628, 0xae0a, 0x2629, 0xce4e, 0xc001, 0xe41e, 0x1522, 0xa202, ++ 0x4e30, 0xe42e, 0xa203, 0x3527, 0xe00d, 0x00ff, 0xe161, 0x0720, ++ 0x8824, 0x0022, 0xe184, 0x152e, 0x1481, 0xe052, 0x4e91, 0x1432, ++ 0xe052, 0x4e32, 0x1433, 0xe052, 0x4e33, 0xe42e, 0xa200, 0x4e32, ++ 0x4e33, 0xe42e, 0x1428, 0xe41a, 0x1536, 0xc000, 0xe41e, 0x124e, ++ 0xc001, 0x1428, 0xe000, 0x0720, 0xe092, 0xe004, 0xfffe, 0x4e34, ++ 0x1532, 0x3727, 0xa803, 0xca40, 0x2234, 0xe056, 0xce40, 0x1591, ++ 0x3727, 0xa803, 0xca42, 0x2234, 0xe056, 0xce42, 0x1591, 0x3727, ++ 0xa803, 0xca44, 0x2234, 0xe056, 0xce44, 0x1533, 0x3727, 0xa803, ++ 0xca46, 0x2234, 0xe056, 0xce46, 0xca4a, 0xcec4, 0xcf34, 0xc000, ++ 0xca4c, 0x151e, 0xb7f6, 0xca4b, 0xe052, 0xcec2, 0x4e69, 0xc001, ++ 0xe42e, 0x1428, 0xe000, 0x0720, 0xe092, 0x1481, 0x4e33, 0xa202, ++ 0x3427, 0x4e81, 0x4e32, 0xc000, 0x1464, 0xe09c, 0x145a, 0x4e96, ++ 0xce40, 0xca42, 0xce46, 0xe08c, 0x4e64, 0xc001, 0xe42e, 0x1429, ++ 0xae0e, 0xe0c1, 0x0047, 0xf04b, 0xe005, 0x0126, 0xf03e, 0xe005, ++ 0x0444, 0xae11, 0xe042, 0xe0c1, 0x0041, 0xe042, 0xce20, 0xd111, ++ 0x074e, 0xd112, 0x0040, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e, ++ 0xe004, 0x0080, 0xe0c2, 0x0094, 0xe0c0, 0x0044, 0x4600, 0xe0c0, ++ 0x0067, 0xe0c2, 0x00ff, 0x1470, 0xe0c2, 0x009b, 0xe0c2, 0x009f, ++ 0xe0c2, 0x018b, 0xa202, 0xe0c2, 0x0100, 0x1451, 0xae20, 0x2650, ++ 0xae08, 0xe0c2, 0x0084, 0x1400, 0xae04, 0x2620, 0xae10, 0xa904, ++ 0xe0c2, 0x0080, 0xa204, 0xe0c1, 0x0060, 0xa83f, 0xae0d, 0xe056, ++ 0xe00a, 0x0800, 0xe0c2, 0x00fa, 0xe0c0, 0x0061, 0xe0c2, 0x00fc, ++ 0xe0c0, 0x0062, 0xe0c2, 0x00fd, 0xe0c0, 0x0063, 0xe0c2, 0x00fe, ++ 0xa202, 0xae0a, 0xe0c1, 0x0060, 0xaf09, 0x4f71, 0xf04b, 0xe0c1, ++ 0x0060, 0xa81f, 0xe056, 0xe0c2, 0x00e7, 0xa204, 0x2600, 0xae20, ++ 0x2670, 0xe0c2, 0x0282, 0x1450, 0xae20, 0x2651, 0xae08, 0xe0c2, ++ 0x0283, 0x1450, 0xae0c, 0x2651, 0xe0c2, 0x0183, 0xa202, 0xe0c2, ++ 0x018d, 0xa258, 0xe0c2, 0x0182, 0xa202, 0xae3e, 0xa906, 0xe0c2, ++ 0x00ec, 0xa200, 0xe0c2, 0x0102, 0xa202, 0xe0c2, 0x0102, 0xa204, ++ 0xe0c2, 0x0102, 0xc00d, 0x146c, 0xf0ea, 0x1060, 0x2661, 0xe0c2, ++ 0x009c, 0x1062, 0x2663, 0xe0c2, 0x009d, 0x1064, 0x2665, 0xe0c2, ++ 0x009e, 0xf16e, 0xc000, 0xe0c1, 0x0041, 0xe004, 0x0320, 0xae10, ++ 0xe042, 0xe0c2, 0x009c, 0xe004, 0x03b0, 0xae10, 0xe042, 0xe0c2, ++ 0x009d, 0xe004, 0x03f8, 0xae10, 0xe042, 0xe0c2, 0x009e, 0xc000, ++ 0xa200, 0x4e73, 0x4e56, 0x4e57, 0x4e3b, 0xe0c2, 0x00a1, 0xe0c2, ++ 0x00a2, 0xa202, 0x4e7c, 0xe004, 0x054b, 0x4e7e, 0x4e7f, 0xe42e, ++ 0xa202, 0x1553, 0xb616, 0x4e03, 0xa103, 0xb616, 0x4e05, 0xa103, ++ 0xb616, 0x4e06, 0xa103, 0xb616, 0x4e04, 0x1405, 0x227d, 0x4e00, ++ 0x1406, 0x4e01, 0x147c, 0xae02, 0x2658, 0xaa06, 0x4e02, 0x1453, ++ 0xe418, 0x1751, 0x1458, 0xe41a, 0x1764, 0x1454, 0xae20, 0x2655, ++ 0xe0c2, 0x0284, 0x147c, 0xae04, 0x2658, 0xaa0a, 0xe0c2, 0x0280, ++ 0x1400, 0xe418, 0x1716, 0x1401, 0xe418, 0x172e, 0x1473, 0xe0c2, ++ 0x0102, 0xe0c2, 0x0101, 0x1404, 0xae02, 0x1504, 0x2371, 0xe056, ++ 0xae1a, 0x2672, 0xe0c2, 0x00e6, 0x107a, 0x267b, 0xe0c2, 0x0082, ++ 0x1404, 0xae02, 0x157c, 0xe017, 0x2303, 0xe056, 0xae02, 0x2606, ++ 0xae02, 0x1558, 0xe017, 0xe056, 0xae04, 0x2606, 0xae02, 0x2605, ++ 0xae02, 0x2605, 0xae04, 0xe0c2, 0x0083, 0xa202, 0xe0c2, 0x0093, ++ 0xe42e, 0xe41e, 0x1784, 0x1078, 0x2679, 0x487a, 0x4e7b, 0x145d, ++ 0xae04, 0x1558, 0xe017, 0xe056, 0xae02, 0x265c, 0xae10, 0x2662, ++ 0x1563, 0xae19, 0xe056, 0x4878, 0x4e79, 0x1474, 0x4e75, 0x145e, ++ 0x4e74, 0x1476, 0x4e77, 0x1469, 0x4e76, 0x147c, 0x4e7d, 0x1458, ++ 0x4e7c, 0xe0c0, 0x0184, 0x4e72, 0xe42e, 0x147c, 0xe016, 0x4e03, ++ 0x147d, 0x4e07, 0xa202, 0x4e05, 0xe40e, 0x16eb, 0xa200, 0x4e03, ++ 0x147d, 0x4e07, 0xa202, 0x4e05, 0xe40e, 0x16eb, 0xa200, 0x4e03, ++ 0x4e07, 0x4e05, 0xe40e, 0x16eb, 0xe41e, 0x177e, 0x1473, 0xe0c2, ++ 0x0102, 0xe0c2, 0x0101, 0xa204, 0x2671, 0xae1a, 0x2672, 0xe0c2, ++ 0x00e6, 0xe004, 0x0200, 0xe0c2, 0x0083, 0xa202, 0xe0c2, 0x0093, ++ 0xe41e, 0x177e, 0xe42e, 0xe41e, 0x177e, 0x1403, 0xae04, 0xe0c2, ++ 0x0280, 0x1407, 0xe418, 0x1716, 0xe41e, 0x172e, 0x1473, 0xe0c2, ++ 0x0102, 0xe0c2, 0x0101, 0xa204, 0x2671, 0xae1a, 0x2672, 0xe0c2, ++ 0x00e6, 0x107a, 0x267b, 0xe0c2, 0x0082, 0x1403, 0xae10, 0xe00a, ++ 0x0290, 0x1505, 0xae03, 0x2705, 0xae05, 0xe056, 0xe0c2, 0x0083, ++ 0xa202, 0xe0c2, 0x0093, 0xe41e, 0x1699, 0xe42e, 0x1473, 0xa104, ++ 0xb468, 0xae08, 0xe000, 0x051b, 0xe092, 0xe162, 0x00c0, 0xd022, ++ 0x000f, 0xe184, 0x1724, 0x1491, 0x9f12, 0x1475, 0xe0c2, 0x00e4, ++ 0x1477, 0xe0c2, 0x00a0, 0xa200, 0x4e00, 0xe42e, 0xe162, 0x0190, ++ 0x147f, 0xe092, 0xd022, 0x000d, 0xe184, 0x1737, 0x1491, 0x9f12, ++ 0x1456, 0xae0c, 0x2657, 0xe0c2, 0x0184, 0x1456, 0xa002, 0x4e56, ++ 0x0c50, 0xa201, 0x4f01, 0xf058, 0x4e56, 0x1457, 0xa002, 0x4e57, ++ 0xe082, 0x4e7f, 0xe002, 0x0575, 0xe005, 0x054b, 0xe428, 0x4f7f, ++ 0xe42e, 0xe0c0, 0x0095, 0xf0e8, 0xe0c0, 0x0096, 0xaf0e, 0x2201, ++ 0xe418, 0x172e, 0xe0c0, 0x0096, 0xaf06, 0x2200, 0xe418, 0x1716, ++ 0xf71e, 0xe0c2, 0x0095, 0xe42e, 0xcb04, 0xe0c2, 0x0285, 0xcb06, ++ 0xe0c2, 0x0286, 0xe161, 0x0575, 0x8891, 0x0022, 0xe184, 0x1776, ++ 0x1491, 0xe000, 0x02f0, 0xe094, 0x1091, 0x2691, 0x9f02, 0x153b, ++ 0xa200, 0x4e02, 0x4e3b, 0xe419, 0x1354, 0xe42e, 0xe0c0, 0x0095, ++ 0xf7ea, 0xe0c2, 0x0095, 0xe42e, 0x1573, 0xa105, 0x1473, 0xa002, ++ 0xb616, 0x4e73, 0xe42e, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe40e, 0x0022, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, ++ 0xe470, 0xe190, 0xe40e, 0x0152, 0xe470, 0xe190, 0xe470, 0xe190, ++ 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, ++ 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, ++ 0xf202, 0x1307, 0xc001, 0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, ++ 0x0008, 0xe0c2, 0x0058, 0xa200, 0xe0c2, 0x005a, 0xa2fe, 0x4e71, ++ 0x4e72, 0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d, 0xce00, 0xf11e, ++ 0xe0c0, 0x005c, 0xe0c1, 0x0059, 0x4f70, 0xa203, 0x3570, 0xe052, ++ 0xf08a, 0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00, ++ 0xe41e, 0x0084, 0xe0c0, 0x005b, 0x0c72, 0xe418, 0x00b2, 0xe0c0, ++ 0x0059, 0xa114, 0xf18a, 0xa102, 0xf1da, 0xe0c0, 0x005a, 0x0c71, ++ 0xe418, 0x00ab, 0xe0c0, 0x0059, 0xae02, 0xe000, 0x0152, 0xc000, ++ 0xe67c, 0xc001, 0xe0c0, 0x005a, 0x4e71, 0xe0c0, 0x005b, 0x4e72, ++ 0xe40e, 0x0038, 0x1471, 0xe412, 0x010d, 0xa202, 0x4e73, 0xe40e, ++ 0x0061, 0xe41e, 0x00c6, 0xd101, 0x0001, 0xc71e, 0xa002, 0xa200, ++ 0xe0c2, 0x0083, 0xa202, 0xe0c2, 0x0093, 0xc71e, 0xa002, 0xd071, ++ 0x002a, 0xe181, 0xe40e, 0x0061, 0xa200, 0xe0c2, 0x0059, 0xe0c2, ++ 0x0058, 0xe0c2, 0x0008, 0xe0c0, 0x0059, 0xf7ea, 0xa11e, 0xf168, ++ 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058, 0xe004, 0xf202, 0xae20, ++ 0xe005, 0x1307, 0xe056, 0xe0c2, 0x0070, 0xa200, 0xe0c2, 0x0059, ++ 0xe0c2, 0x0058, 0xe0c2, 0x0008, 0xf67e, 0xa202, 0xe0c2, 0x0008, ++ 0xe0c2, 0x0058, 0xe42e, 0x1471, 0xe424, 0xe41e, 0x010d, 0xe41e, ++ 0x00c6, 0xe42e, 0xe0c0, 0x0040, 0xe0c1, 0x005b, 0xae1d, 0xe042, ++ 0xe000, 0x1000, 0xce20, 0xd111, 0x0800, 0xd112, 0x1000, 0xd113, ++ 0x000b, 0xca28, 0xf7f8, 0xe41e, 0x17e0, 0xe42e, 0xe0c0, 0x0041, ++ 0xe005, 0x0000, 0xae11, 0xe042, 0xe0c1, 0x005a, 0xae19, 0xe042, ++ 0xce20, 0xd111, 0x0000, 0xd112, 0x0800, 0xd113, 0x0003, 0xca28, ++ 0xf7f8, 0xe0c0, 0x0041, 0xe005, 0x0080, 0xae11, 0xe042, 0xe0c1, ++ 0x005a, 0xae15, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0200, ++ 0xd113, 0x0013, 0xca28, 0xf7f8, 0xe161, 0x00f4, 0x8891, 0x0032, ++ 0x8891, 0x0033, 0x8891, 0x0034, 0x8891, 0x0035, 0x8891, 0x0036, ++ 0x8891, 0x0037, 0x1091, 0x2691, 0xcc60, 0x1091, 0x2691, 0xcc62, ++ 0x1091, 0x2691, 0xcc74, 0x1091, 0x2691, 0xcf68, 0x1091, 0x2691, ++ 0xcf64, 0x1091, 0x2691, 0xcf60, 0xe42e, 0xe161, 0x00f4, 0x8991, ++ 0x0032, 0x8991, 0x0033, 0x8991, 0x0034, 0x8991, 0x0035, 0x8991, ++ 0x0036, 0x8991, 0x0037, 0xc860, 0x4891, 0x4e91, 0xc862, 0x4891, ++ 0x4e91, 0xc874, 0x4891, 0x4e91, 0xcb68, 0x4891, 0x4e91, 0xcb64, ++ 0x4891, 0x4e91, 0xcb60, 0x4891, 0x4e91, 0xe0c0, 0x0041, 0xe005, ++ 0x0000, 0xae11, 0xe042, 0x1571, 0xae19, 0xe042, 0xce20, 0xd111, ++ 0x0000, 0xd112, 0x0800, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe0c0, ++ 0x0041, 0xe005, 0x0080, 0xae11, 0xe042, 0x1571, 0xae15, 0xe042, ++ 0xce20, 0xd111, 0x0000, 0xd112, 0x0200, 0xd113, 0x0012, 0xca28, ++ 0xf7f8, 0xe42e, 0xe40e, 0x11e3, 0xe40e, 0x0172, 0xe40e, 0x0176, ++ 0xe40e, 0x017a, 0xe40e, 0x0186, 0xe40e, 0x018a, 0xe40e, 0x018e, ++ 0xe40e, 0x0061, 0xe40e, 0x0061, 0xe40e, 0x0192, 0xe40e, 0x0061, ++ 0xe40e, 0x0061, 0xe40e, 0x0061, 0xe40e, 0x0061, 0xe40e, 0x0061, ++ 0xe40e, 0x0061, 0xe41e, 0x0196, 0xe40e, 0x0061, 0xe41e, 0x01db, ++ 0xe40e, 0x0061, 0xc001, 0x145d, 0xc000, 0xf058, 0xe41e, 0x01ed, ++ 0xe40e, 0x0061, 0xe41e, 0x12c5, 0xe40e, 0x0061, 0xe41e, 0x0282, ++ 0xe40e, 0x0061, 0xe41e, 0x0294, 0xe40e, 0x0061, 0xe41e, 0x0311, ++ 0xe40e, 0x0061, 0xe41e, 0x0330, 0xe40e, 0x0061, 0xe41e, 0x0396, ++ 0xe41e, 0x055c, 0xc001, 0xe0c0, 0x0074, 0x4840, 0x4e41, 0xe0c0, ++ 0x0075, 0x4842, 0x4e43, 0xe0c0, 0x0076, 0x4844, 0x4e45, 0xe0c0, ++ 0x0077, 0x4846, 0x4e47, 0xe0c0, 0x0047, 0x4e48, 0xc000, 0xc001, ++ 0xe0c0, 0x006e, 0xa802, 0x4e5d, 0xe0c0, 0x006e, 0xaf02, 0xa81e, ++ 0x4e59, 0xe0c0, 0x006e, 0xaf0a, 0xa80e, 0x4e5e, 0xe0c0, 0x006e, ++ 0xaf10, 0xe008, 0xffff, 0x4e69, 0xc000, 0xe41e, 0x056a, 0xe41e, ++ 0x03a7, 0xf0ea, 0xe41e, 0x0b75, 0xe41e, 0x11b8, 0x1415, 0xe418, ++ 0x0ebe, 0xe41e, 0x1153, 0xa202, 0xe0c2, 0x0070, 0xe42e, 0xa200, ++ 0xe0c2, 0x0070, 0xe42e, 0x147c, 0xe428, 0x147d, 0xf09a, 0xa200, ++ 0xc001, 0x484a, 0xc000, 0x4e4d, 0xe41e, 0x1279, 0xe42e, 0xc001, ++ 0x145d, 0xc000, 0xe41a, 0x1235, 0xe42e, 0xa200, 0xcc4a, 0xcc4c, ++ 0xcc44, 0xe0c2, 0x0074, 0xc001, 0x1473, 0xf05a, 0xa200, 0xe41e, ++ 0x056a, 0x4e73, 0xc000, 0x147b, 0xaa02, 0x4e7b, 0x147d, 0xf15a, ++ 0x147e, 0xf0ca, 0xe0c0, 0x0066, 0x484a, 0x4e4b, 0xe0c0, 0x0067, ++ 0xae04, 0xc001, 0x4849, 0xc000, 0x4e4c, 0xa200, 0xc001, 0x484a, ++ 0xc000, 0x4e4d, 0xe41e, 0x1279, 0xd180, 0x0005, 0xd147, 0x0003, ++ 0xd03b, 0x0001, 0xd008, 0x0000, 0xe16a, 0xe004, 0x0123, 0xae20, ++ 0xe00a, 0x4567, 0xcf50, 0xe004, 0x89ab, 0xae20, 0xe00a, 0xcdef, ++ 0xcf52, 0xa200, 0xcf06, 0xe0c2, 0x0286, 0x141b, 0xe418, 0x0507, ++ 0xe41e, 0x0459, 0xe41e, 0x115a, 0x1428, 0xf07a, 0xc001, 0x143f, ++ 0xa002, 0xa802, 0x4e3f, 0xc000, 0xe41e, 0x0b78, 0xe41e, 0x0cab, ++ 0xe41e, 0x0cbd, 0xe41e, 0x07a4, 0xa200, 0x4e53, 0x4e54, 0x4e55, ++ 0x4e1f, 0xe41e, 0x0367, 0x1453, 0x0c52, 0xf7c4, 0xe41e, 0x0d4f, ++ 0x1415, 0xe418, 0x0f5d, 0x147d, 0xf06a, 0xe41e, 0x1235, 0xe41e, ++ 0x0ae5, 0xf05e, 0x147c, 0xf03a, 0xe41e, 0x124a, 0x162a, 0xa002, ++ 0x4e2a, 0x1633, 0xa002, 0x4e33, 0xe0c2, 0x0070, 0x1428, 0xe0c2, ++ 0x0071, 0x141f, 0xe0c2, 0x0073, 0xc001, 0x1461, 0xf09a, 0x1461, ++ 0xa102, 0x4e61, 0x1462, 0xa002, 0x4e62, 0xa200, 0x4e63, 0xc000, ++ 0xd03a, 0x0000, 0xc84a, 0xc84d, 0xae20, 0xe056, 0xe0c2, 0x0046, ++ 0xa202, 0xe42e, 0xe0c0, 0x0042, 0xce20, 0xd111, 0x0570, 0xd112, ++ 0x0030, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe0c0, 0x0060, 0x4e32, ++ 0xe0c0, 0x0061, 0x4e70, 0xe42e, 0x147d, 0xf15a, 0x147e, 0xf0ca, ++ 0xe0c0, 0x0061, 0x484a, 0x4e4b, 0xe0c0, 0x0062, 0xae04, 0xc001, ++ 0x4849, 0xc000, 0x4e4c, 0xa200, 0xc001, 0x484a, 0xc000, 0x4e4d, ++ 0xe41e, 0x1279, 0xe0c0, 0x0060, 0xf0aa, 0xa102, 0xf0ba, 0xa102, ++ 0xf28a, 0xa102, 0xf28a, 0xa102, 0xf08a, 0xe42e, 0xe41e, 0x04f1, ++ 0xf2ae, 0xe41e, 0x04fc, 0xf27e, 0xe0c0, 0x0063, 0xc001, 0xa102, ++ 0x4e61, 0xc000, 0x1452, 0xc001, 0xc70f, 0x3c61, 0x4862, 0x4e64, ++ 0x1562, 0x1464, 0xf029, 0xa102, 0x4e64, 0x1461, 0xa002, 0x4e61, ++ 0xa200, 0x4e62, 0x4e63, 0x4e65, 0xc000, 0xe41e, 0x0514, 0xf0be, ++ 0xa214, 0xf02e, 0xa216, 0x4e30, 0xa200, 0x4e2f, 0xe41e, 0x0aee, ++ 0xe41e, 0x0b15, 0xc001, 0x145d, 0xc000, 0xf20a, 0x1440, 0xa006, ++ 0xaf04, 0xae04, 0x0c40, 0xf1aa, 0x4e00, 0x1440, 0xaf02, 0xe000, ++ 0x0700, 0xe098, 0x1440, 0xa802, 0x4e41, 0xc874, 0xa010, 0xcc74, ++ 0xa200, 0xe41e, 0x0b5d, 0x1400, 0xa102, 0x4e00, 0xf778, 0xe088, ++ 0xe002, 0x0700, 0xae02, 0x0441, 0x4e40, 0x147d, 0xf06a, 0xe41e, ++ 0x1235, 0xe41e, 0x0ae5, 0xf05e, 0x147c, 0xf03a, 0xe41e, 0x124a, ++ 0xe42e, 0xe41e, 0x11d3, 0xe0c0, 0x0060, 0xf048, 0xe41e, 0x09fe, ++ 0xf03e, 0xe41e, 0x0a22, 0xc86e, 0xaf06, 0x4e45, 0xe0c2, 0x0070, ++ 0xe004, 0x0040, 0xcc6c, 0xbadf, 0xe0c0, 0x0042, 0xce20, 0xd111, ++ 0x0000, 0xd112, 0x0100, 0xd113, 0x0012, 0xca28, 0xf7f8, 0xe42e, ++ 0xe0c1, 0x0060, 0xa803, 0xf05b, 0xe0c0, 0x0061, 0xe41e, 0x05d6, ++ 0xe0c1, 0x0060, 0xa805, 0xf05b, 0xe0c0, 0x0062, 0xe41e, 0x062d, ++ 0xe0c1, 0x0060, 0xa809, 0xf05b, 0xe0c0, 0x0063, 0xe41e, 0x0601, ++ 0xe0c1, 0x0060, 0xa811, 0xf05b, 0xe0c0, 0x0064, 0xe41e, 0x059b, ++ 0xe0c1, 0x0060, 0xa821, 0xf04b, 0xe0c0, 0x0065, 0x4e1c, 0xe0c1, ++ 0x0060, 0xa841, 0xf0cb, 0xc001, 0x155d, 0xc000, 0xf089, 0xe0c0, ++ 0x0066, 0x4637, 0xaf02, 0x4638, 0xaf02, 0x4e39, 0xe42e, 0x1531, ++ 0xa20a, 0xb636, 0x4e30, 0xe41e, 0x0aee, 0xc001, 0x1461, 0xf10a, ++ 0x1463, 0x1562, 0xe046, 0xf068, 0xa200, 0x4e65, 0xa204, 0x4e66, ++ 0xf07e, 0xc000, 0x1428, 0x1529, 0xc001, 0x4e65, 0x4f66, 0xc000, ++ 0xe41e, 0x0a71, 0xe41e, 0x063c, 0xe41e, 0x0ab9, 0xe41e, 0x0b15, ++ 0x141a, 0xe418, 0x04d1, 0x141f, 0xa002, 0x4e1f, 0xc001, 0x1461, ++ 0xf04a, 0x1463, 0xa002, 0x4e63, 0xc000, 0xe42e, 0xa200, 0xc401, ++ 0xe188, 0x07ff, 0x4e91, 0xa200, 0xc001, 0x4e4e, 0x4e4f, 0xc000, ++ 0x4e2a, 0x4e33, 0xd03a, 0x0000, 0xa202, 0x4e7b, 0xe42e, 0xe0c0, ++ 0x0064, 0xe049, 0xe009, 0x03ff, 0xaf09, 0x4f51, 0xe049, 0xaf15, ++ 0xe009, 0x03ff, 0xaf09, 0x4f50, 0xe0c0, 0x0065, 0x4818, 0x4e17, ++ 0x1418, 0xa002, 0x4e18, 0xe0c0, 0x0062, 0x4619, 0xaf02, 0x461a, ++ 0xaf02, 0x461b, 0xc001, 0xaf06, 0x4638, 0xe0c0, 0x006f, 0x4e39, ++ 0xe0c0, 0x0071, 0x466d, 0xaf02, 0x466c, 0xc000, 0xe0c0, 0x0068, ++ 0xe049, 0xa83f, 0xae3f, 0xaf3f, 0x4f24, 0xe049, 0xaf0b, 0x4726, ++ 0xe049, 0xaf0d, 0xa807, 0x4f2c, 0xe049, 0xaf11, 0xa81f, 0xaf41, ++ 0xae41, 0xae03, 0x4f2d, 0xe049, 0xaf19, 0xa81f, 0xaf41, 0xae41, ++ 0xae03, 0x4f2e, 0x142c, 0x262d, 0x262e, 0xe01a, 0x4e25, 0xc001, ++ 0x145d, 0xc000, 0xf088, 0xe0c0, 0x0069, 0x4637, 0xaf02, 0x4638, ++ 0xaf02, 0x4e39, 0xe0c0, 0x006a, 0x4e14, 0xe0c0, 0x006b, 0x4615, ++ 0xc001, 0x4801, 0xaf02, 0xe008, 0x7fff, 0x4e00, 0xe0c0, 0x006b, ++ 0x1401, 0xaf1e, 0x462c, 0x1401, 0xe008, 0x7fff, 0x4e01, 0xe0c0, ++ 0x006c, 0x4802, 0x4e03, 0xc000, 0xe0c0, 0x006d, 0x4e1c, 0xa20a, ++ 0x4e10, 0xa002, 0x4e12, 0xa202, 0x4e13, 0xa102, 0x4e22, 0xa200, ++ 0x4e21, 0x4e20, 0x4e27, 0xa204, 0x4e11, 0xa234, 0x4e23, 0x8250, ++ 0x8151, 0xe018, 0x4e52, 0xa201, 0xe002, 0x00c8, 0xb425, 0xe002, ++ 0x0190, 0xb425, 0x4f36, 0x1450, 0x1551, 0xaf06, 0xaf07, 0x4e07, ++ 0x4f01, 0x8207, 0x8101, 0xe018, 0xc001, 0x4e4b, 0xa104, 0xf032, ++ 0xa204, 0x4e4b, 0xc000, 0x1451, 0xaf02, 0x4e07, 0x8207, 0x8150, ++ 0xe018, 0xc001, 0x4e4d, 0x4e6b, 0xa202, 0x4e3f, 0xc000, 0xe0c0, ++ 0x0043, 0xaf04, 0x467c, 0xaf02, 0x467d, 0xaf02, 0x467e, 0xa202, ++ 0xe42e, 0xa200, 0x4e49, 0xe0c0, 0x0065, 0xa804, 0xf08a, 0xa200, ++ 0x4e2a, 0xc001, 0x4e36, 0xe016, 0x4e0d, 0xc000, 0x1414, 0xf048, ++ 0x162a, 0xf0ca, 0xf12e, 0xc001, 0x1436, 0xc000, 0xf07a, 0xc001, ++ 0x1436, 0xc000, 0x1514, 0xe046, 0xf088, 0xa200, 0x4e28, 0xa202, ++ 0xc001, 0x4e36, 0xc000, 0xf07e, 0xa202, 0x4e28, 0xc001, 0x0436, ++ 0x4e36, 0xc000, 0xe0c0, 0x0065, 0xa802, 0xe418, 0x049e, 0xe0c0, ++ 0x0063, 0x4e2b, 0x1415, 0xf09a, 0x1428, 0xe41a, 0x0f22, 0xe41e, ++ 0x0f23, 0x4e2b, 0xe419, 0x049e, 0x1428, 0xe016, 0xae02, 0x4e29, ++ 0x162a, 0xe016, 0x4e31, 0xa004, 0x4e2f, 0xe42e, 0xa202, 0x4e28, ++ 0x4e49, 0x8235, 0xc786, 0xe018, 0xe000, 0x0570, 0xe09e, 0x1097, ++ 0x2697, 0xe0c2, 0x0060, 0x1097, 0x2697, 0xe0c2, 0x0061, 0x1097, ++ 0x2697, 0xe0c2, 0x0062, 0xe42e, 0x1454, 0xe000, 0x0540, 0xe09e, ++ 0xc874, 0x4e87, 0x1454, 0xa002, 0x0c50, 0xe428, 0x1455, 0xae0e, ++ 0xe005, 0x0000, 0xae11, 0xe042, 0xe0c1, 0x0042, 0xe042, 0xce20, ++ 0xd111, 0x0540, 0xd112, 0x002e, 0xd113, 0x0002, 0xca28, 0xf7f8, ++ 0xe42e, 0x104a, 0x264b, 0xc001, 0x134a, 0xc000, 0x274d, 0xae11, ++ 0xe042, 0x0440, 0xe161, 0x04e4, 0x4891, 0x4e91, 0x141f, 0xae04, ++ 0xe005, 0x0012, 0xae11, 0xe042, 0xe0c1, 0x0042, 0xe042, 0xce20, ++ 0xd111, 0x04e4, 0xd112, 0x0020, 0xd113, 0x0002, 0xca28, 0xf7f8, ++ 0xe42e, 0xa206, 0x4e2f, 0xa20e, 0x4e30, 0xe41e, 0x0aee, 0xe41e, ++ 0x09fe, 0xe41e, 0x0b15, 0xe42e, 0xa206, 0x4e2f, 0xa210, 0x4e30, ++ 0xe41e, 0x0aee, 0xe41e, 0x0a22, 0xe41e, 0x0b15, 0xe42e, 0xa200, ++ 0x4e2f, 0xa212, 0x4e30, 0xe41e, 0x0aee, 0x1429, 0xba84, 0xe41e, ++ 0x0ab9, 0xe41e, 0x0b15, 0xe42e, 0xe41e, 0x11d3, 0xa2fe, 0x4e43, ++ 0xc001, 0x1461, 0xc000, 0xbffc, 0xa200, 0xba80, 0xba80, 0xba82, ++ 0xe41e, 0x0ab9, 0xe41e, 0x0ab9, 0xc866, 0xa100, 0xae04, 0x4e45, ++ 0xc864, 0xaf06, 0x0445, 0x4e45, 0xa200, 0x4e2f, 0xa20c, 0x4e30, ++ 0xc874, 0xa070, 0xcc74, 0x1440, 0xaf02, 0xe000, 0x0700, 0xe098, ++ 0x1440, 0xa802, 0x4e41, 0xa200, 0xe41e, 0x0b5d, 0xa200, 0xe41e, ++ 0x0b5d, 0xa200, 0xe41e, 0x0b5d, 0xa202, 0xe41e, 0x0b5d, 0x142f, ++ 0xae0a, 0x2630, 0xe41e, 0x0b5d, 0xa20c, 0xe41e, 0x0b5d, 0x1445, ++ 0xa102, 0xe41e, 0x0b5d, 0xe088, 0xe002, 0x0700, 0xae02, 0x0441, ++ 0x4e40, 0xe41e, 0x0b15, 0xe42e, 0xe0c0, 0x0040, 0xe000, 0xf000, ++ 0xce20, 0xd111, 0x03b4, 0xd112, 0x0100, 0xd113, 0x0003, 0xca28, ++ 0xf7f8, 0xe42e, 0xe0c0, 0x0040, 0xe000, 0xf200, 0xce20, 0xd111, ++ 0x0700, 0xd112, 0x0100, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe167, ++ 0x0700, 0xa200, 0x4e00, 0xa200, 0x4e01, 0xd022, 0x0008, 0xe184, ++ 0x058c, 0x1400, 0xae08, 0x2601, 0xe0c2, 0x00f0, 0x1097, 0x2697, ++ 0xe0c2, 0x00f1, 0x1401, 0xa002, 0x4e01, 0x1400, 0xa002, 0x4e00, ++ 0xa112, 0xf6a8, 0xe161, 0x05a0, 0xd022, 0x002f, 0xe184, 0x0599, ++ 0x1497, 0x4e91, 0xe42e, 0xc001, 0x483d, 0x4e3c, 0x143d, 0xa002, ++ 0x4e3d, 0x163c, 0xc710, 0x3c3d, 0xe008, 0xffff, 0xa002, 0xaf02, ++ 0x4e0b, 0x0c3b, 0xe42a, 0x140b, 0x4e3b, 0x143c, 0x153d, 0xc000, ++ 0x4e17, 0x4f18, 0x8218, 0xe182, 0x7530, 0xe018, 0xae02, 0x1717, ++ 0xc001, 0xe41e, 0x1047, 0x4e18, 0x8218, 0x8100, 0xe018, 0xa279, ++ 0xe41e, 0x1030, 0x4818, 0x4e19, 0xae06, 0x1504, 0xe41e, 0x1030, ++ 0x481e, 0x4e1f, 0xa200, 0x4e35, 0x4822, 0x4e23, 0x1409, 0xe428, ++ 0xe016, 0x4e0a, 0x140b, 0x4e09, 0xc000, 0xe42e, 0xc001, 0x4e37, ++ 0x1509, 0xe046, 0xf038, 0xc000, 0xe42e, 0x1436, 0x1537, 0xe046, ++ 0xf034, 0xa200, 0x4e36, 0x1437, 0x4e09, 0xc000, 0x4e14, 0x1415, ++ 0xe42a, 0xc001, 0x1409, 0xe016, 0x4e0a, 0xf03a, 0x150b, 0x4f09, ++ 0x1509, 0x1436, 0xe045, 0xf0c6, 0x1026, 0x2627, 0xe41e, 0x1030, ++ 0x482a, 0x4e2b, 0x0826, 0x0e27, 0xe012, 0x4828, 0x4e29, 0xc000, ++ 0xe42e, 0xc001, 0x4e3a, 0xc000, 0x1415, 0xe42a, 0xc001, 0x1400, ++ 0x153a, 0xe046, 0xc000, 0xe42a, 0xc001, 0x4f00, 0xc000, 0x8218, ++ 0xe182, 0x7530, 0xe018, 0xae02, 0x1717, 0xc001, 0xe41e, 0x1047, ++ 0x4e18, 0x8218, 0x8100, 0xe018, 0xa279, 0xe41e, 0x1030, 0x4818, ++ 0x4e19, 0xae06, 0x1504, 0xe41e, 0x1030, 0x481e, 0x4e1f, 0xa200, ++ 0x4e35, 0x4822, 0x4e23, 0xc000, 0xe42e, 0xc000, 0x1515, 0xe42b, ++ 0xc001, 0xf052, 0xa201, 0x4f38, 0xc000, 0xe42e, 0x4e39, 0x4e10, ++ 0xa203, 0x4f38, 0xc000, 0xe42e, 0x142b, 0x4e61, 0x142c, 0xae0a, ++ 0x152d, 0xa83f, 0xe056, 0xae0a, 0x152e, 0xa83f, 0xe056, 0xce4e, ++ 0xe41e, 0x109d, 0xa200, 0x4e5b, 0x4e3a, 0xa202, 0x4e3b, 0xe41e, ++ 0x10c6, 0xc001, 0x1461, 0xc000, 0xf04a, 0xe41e, 0x0688, 0xf03e, ++ 0xe41e, 0x06aa, 0xe41e, 0x07b1, 0x145b, 0x045a, 0x4e5b, 0x896b, ++ 0x003a, 0x1419, 0xe418, 0x04b4, 0xe41e, 0x06fb, 0xc874, 0x0e6b, ++ 0xe008, 0xffff, 0x4e6c, 0x145a, 0xe012, 0x225b, 0x4e5b, 0xe41e, ++ 0x06c1, 0x1515, 0x1462, 0x4e61, 0xe419, 0x0fab, 0x1453, 0xa002, ++ 0x4e53, 0xe41e, 0x10da, 0xf04a, 0x143a, 0xe40a, 0x064f, 0x145b, ++ 0xe418, 0x0ac3, 0x1515, 0x1462, 0xf02b, 0x4e2b, 0xa202, 0xe42e, ++ 0x143b, 0xc001, 0x0c64, 0xc000, 0x153b, 0xa003, 0x4f3b, 0xe428, ++ 0xa202, 0x4e3b, 0xd12a, 0x0001, 0xa202, 0x4e3a, 0xc001, 0x1463, ++ 0x1562, 0xa002, 0xe046, 0xf078, 0xa200, 0x4e67, 0xa204, 0x4e68, ++ 0xc000, 0xe42e, 0xc000, 0x1428, 0x1529, 0xc001, 0x4e67, 0x4f68, ++ 0xc000, 0xe42e, 0x1437, 0x1538, 0xe42a, 0xe409, 0x06b4, 0xc86e, ++ 0x0e39, 0xe424, 0xe40e, 0x06bc, 0x143b, 0x0c39, 0x153b, 0xa003, ++ 0x4f3b, 0xe428, 0xa202, 0x4e3b, 0xd12a, 0x0001, 0xa202, 0x4e3a, ++ 0xe42e, 0x1463, 0xae0c, 0x2662, 0xae02, 0x2658, 0xae02, 0xa902, ++ 0xce48, 0x4e59, 0xcac6, 0xce60, 0xcb12, 0xce62, 0x1454, 0xe01a, ++ 0xe012, 0xe049, 0xe161, 0x04f0, 0xd132, 0x0000, 0xca66, 0xe052, ++ 0x4e91, 0xca66, 0x4e91, 0xca66, 0x4e91, 0xca66, 0x4e91, 0x1455, ++ 0xe01a, 0xe012, 0xe049, 0xca66, 0xe052, 0x4e91, 0xca66, 0x4e91, ++ 0xca66, 0x4e91, 0xca66, 0x4e91, 0xd134, 0x0000, 0xca6a, 0x4e91, ++ 0xca6a, 0x4e91, 0xca6a, 0x4e91, 0xca6a, 0x4e91, 0xca6a, 0x4e91, ++ 0xca6a, 0x4e91, 0xe42e, 0xc001, 0x1561, 0xf049, 0xc000, 0x1529, ++ 0xf03e, 0x1566, 0xc000, 0xe40b, 0x0713, 0x155c, 0xa200, 0xe40b, ++ 0x0730, 0xa202, 0x045d, 0x1560, 0xae05, 0xe042, 0x155f, 0xb5b3, ++ 0xe042, 0xe40e, 0x0743, 0x155a, 0x145b, 0xe409, 0x075c, 0xe41e, ++ 0x0ac3, 0x1558, 0x143d, 0xe409, 0x0722, 0xe049, 0xa107, 0xb436, ++ 0xe40e, 0x074a, 0x155c, 0xa20a, 0xe40b, 0x0730, 0xa20c, 0x045d, ++ 0x1560, 0xae05, 0xe042, 0x155f, 0xb5b3, 0xe042, 0xe40e, 0x0743, ++ 0xbffc, 0xe41e, 0x0760, 0x145e, 0xbffc, 0xe004, 0x03b5, 0x043f, ++ 0x043f, 0xe09c, 0x1486, 0xbffc, 0x146f, 0x156e, 0xe408, 0x0759, ++ 0xbfff, 0xe40e, 0x0759, 0xbffc, 0x145e, 0xbffc, 0x146e, 0xbffe, ++ 0xe40e, 0x0759, 0xbffc, 0xe41e, 0x0791, 0xe004, 0x03b4, 0x043f, ++ 0x043f, 0xe09c, 0x1486, 0xbffc, 0x146f, 0x156e, 0xe408, 0x0759, ++ 0xbfff, 0xe41e, 0x091b, 0xe42e, 0xa200, 0xe41e, 0x10ef, 0xe42e, ++ 0xe161, 0x04d0, 0xe162, 0x04b0, 0xd022, 0x000f, 0xe184, 0x0771, ++ 0x1491, 0x0c82, 0xe049, 0xe016, 0xba80, 0xf048, 0x1482, 0xb5ee, ++ 0xba84, 0x8092, 0xe42e, 0x1465, 0xe09c, 0x1486, 0xcece, 0xe162, ++ 0x04b0, 0xd160, 0x0000, 0xd022, 0x000f, 0xe184, 0x078b, 0xcac8, ++ 0x0c82, 0xe049, 0xe01a, 0xe016, 0xba80, 0xe408, 0x078a, 0x1482, ++ 0xb5ee, 0xba84, 0x1492, 0xceca, 0xcace, 0x4e96, 0xe08c, 0x4e65, ++ 0xe42e, 0x143c, 0xcc44, 0xa106, 0xe161, 0x04e8, 0xe408, 0x079a, ++ 0xa21e, 0xba86, 0xe184, 0x07a2, 0x1491, 0xe41e, 0x0add, 0x1491, ++ 0xe41e, 0x0add, 0xe190, 0xe42e, 0xc001, 0xa200, 0x4e5f, 0xc000, ++ 0xd12a, 0x0001, 0xa2fe, 0x4e53, 0xe41e, 0x0cd5, 0xe41e, 0x0843, ++ 0xe42e, 0xe41e, 0x0cd5, 0xe41e, 0x084e, 0x1462, 0x0c61, 0xa269, ++ 0xa034, 0xb605, 0xe042, 0xa269, 0xa168, 0xb609, 0xe046, 0xa034, ++ 0x4e6e, 0x1428, 0xe418, 0x08df, 0xa200, 0x4e5a, 0xe41e, 0x07d2, ++ 0x1460, 0xae08, 0x265f, 0x4e3f, 0xe01a, 0xe016, 0x4e6f, 0xe418, ++ 0x0825, 0xe42e, 0x885c, 0x014b, 0xa200, 0x4e5f, 0x4e00, 0xd022, ++ 0x0003, 0xe184, 0x07f1, 0x1400, 0xae04, 0xce90, 0xa002, 0xcab3, ++ 0xce90, 0xf0a9, 0xcab3, 0xa002, 0xce90, 0xf069, 0xcab3, 0xa002, ++ 0xce90, 0xf029, 0xcab3, 0xe01b, 0x3500, 0x275f, 0x4f5f, 0x1400, ++ 0xa002, 0x4e00, 0xa224, 0xce90, 0xd022, 0x0006, 0xcab3, 0xe184, ++ 0x07fc, 0xa002, 0xce90, 0xf039, 0xcab3, 0xe190, 0xa204, 0xe409, ++ 0x080a, 0xa220, 0xce90, 0xa002, 0xcab3, 0xce90, 0xe190, 0xcab2, ++ 0xe056, 0xe01a, 0x4e60, 0x146e, 0x155c, 0x275f, 0xf10a, 0x2760, ++ 0xf0e9, 0xa200, 0x4e6e, 0x1461, 0x4e62, 0x0424, 0xa400, 0xa566, ++ 0xe000, 0x0414, 0xe09c, 0x1486, 0x4e63, 0xe42e, 0x155c, 0x145f, ++ 0xe42b, 0xe42a, 0xa21e, 0x4e5f, 0xe42e, 0x1458, 0x156e, 0x273d, ++ 0xe428, 0xe429, 0xca4a, 0xc001, 0x155d, 0xf03b, 0x155b, 0xe052, ++ 0xc000, 0xa806, 0xa106, 0xe161, 0x04e8, 0x153e, 0xe408, 0x0840, ++ 0xe40b, 0x0840, 0x1491, 0x2691, 0xe428, 0xa202, 0x4e5a, 0xe42e, ++ 0x146d, 0x4e5a, 0xe42e, 0xe161, 0x04e0, 0x1458, 0x4e91, 0x145c, ++ 0x4e91, 0x1462, 0x4e91, 0x1463, 0x4e91, 0xe42e, 0xe161, 0x04e0, ++ 0x1481, 0x1558, 0x4f91, 0x4e58, 0x1481, 0x155c, 0x4f91, 0x4e5c, ++ 0x1481, 0x1562, 0x4f91, 0x4e62, 0x1481, 0x1563, 0x4f91, 0x4e63, ++ 0xe42e, 0xa200, 0x4e07, 0xe41e, 0x0eaa, 0xe0c0, 0x0217, 0x4e77, ++ 0x1478, 0xe09a, 0xe0c0, 0x0215, 0x4e3d, 0x4e95, 0xa104, 0xb5f4, ++ 0xa004, 0x4e3c, 0x4e95, 0xa102, 0xe162, 0x02f0, 0xe404, 0x087c, ++ 0xe40a, 0x088b, 0xe40e, 0x08ab, 0xe0c0, 0x0214, 0xae28, 0xaf38, ++ 0x4e95, 0xe0c1, 0x0214, 0xae39, 0xaf39, 0x4f8d, 0x1095, 0x2695, ++ 0x9f02, 0xe40e, 0x08c4, 0xa206, 0x0c3d, 0xae04, 0xe090, 0xe0c0, ++ 0x0213, 0xae08, 0xaf38, 0x4e95, 0xe0c1, 0x0213, 0xae29, 0xaf39, ++ 0x4f8d, 0x1095, 0x2695, 0x9f32, 0xe0c0, 0x0213, 0xae18, 0xaf38, ++ 0x4e95, 0xe0c1, 0x0213, 0xae39, 0xaf39, 0x4f8d, 0x1095, 0x2695, ++ 0x9f02, 0xe40e, 0x08c4, 0xc420, 0xa230, 0x4e6a, 0xd022, 0x0003, ++ 0xe184, 0x08c3, 0xe0c0, 0x0211, 0x366a, 0xae38, 0xaf38, 0x4e95, ++ 0xe0c1, 0x0212, 0x376a, 0xae39, 0xaf39, 0x4f8d, 0x1095, 0x2695, ++ 0x9f32, 0x146a, 0xa110, 0x4e6a, 0xe08a, 0x4e78, 0x143d, 0xae06, ++ 0x263d, 0xae06, 0x263d, 0xae06, 0x263d, 0xe0c2, 0x0285, 0x1472, ++ 0xae20, 0x2673, 0xe0c2, 0x0284, 0x1472, 0xa002, 0x4e72, 0x0c50, ++ 0xe428, 0xa200, 0x4e72, 0x1473, 0xa002, 0x4e73, 0xe42e, 0x1458, ++ 0xe408, 0x090d, 0xe41e, 0x112c, 0xe161, 0x04e8, 0x1479, 0xe09a, ++ 0x1495, 0x4e3d, 0x1495, 0x4e3c, 0xcc44, 0xcb20, 0xe01a, 0xcb29, ++ 0xe01b, 0xe052, 0x4e3e, 0x1095, 0x268d, 0xe016, 0x4e6d, 0x143d, ++ 0xae06, 0x263d, 0xae06, 0x263d, 0xae06, 0x263d, 0xcf04, 0xe184, ++ 0x0907, 0x1095, 0x2695, 0xcf08, 0xe190, 0xcb0a, 0x4891, 0x4e91, ++ 0xe08a, 0x4e79, 0xe41e, 0x1140, 0xe42e, 0xe41e, 0x1114, 0x1479, ++ 0xe09a, 0x8095, 0x1495, 0xcc44, 0xe184, 0x0917, 0x8095, 0x8095, ++ 0xe08a, 0x4e79, 0xe42e, 0x145c, 0xe418, 0x0926, 0xe41e, 0x093d, ++ 0x1460, 0xe418, 0x097c, 0xe41e, 0x0992, 0xe42e, 0x1466, 0xe09c, ++ 0x1096, 0x268e, 0xced6, 0xd160, 0x0000, 0xcad0, 0xa000, 0x4e02, ++ 0xa2fe, 0xce90, 0xd151, 0x0000, 0xd150, 0x0001, 0xd040, 0x0010, ++ 0xe41e, 0x09c8, 0xa202, 0xb61a, 0xe42e, 0x1466, 0xe09c, 0x1096, ++ 0x268e, 0xced6, 0xd160, 0x0000, 0xa220, 0x0c5c, 0xcc80, 0xe164, ++ 0x04c0, 0x145f, 0xc703, 0x4694, 0xaf02, 0xc703, 0x4694, 0xaf02, ++ 0xc703, 0x4694, 0xaf02, 0xc703, 0x4694, 0xe164, 0x04c0, 0xa200, ++ 0x4e03, 0x1494, 0x1503, 0xce91, 0xe40a, 0x096a, 0x885c, 0x0151, ++ 0xd150, 0x0001, 0xcad0, 0xa000, 0x4e02, 0xe41e, 0x09c8, 0xe40d, ++ 0x0978, 0x1400, 0x1503, 0xa003, 0x4f03, 0xa121, 0xced2, 0xe409, ++ 0x0959, 0xcad6, 0x4896, 0x4e96, 0xe08c, 0x4e66, 0xa202, 0xe42e, ++ 0xe16a, 0xa200, 0xe42e, 0xe42e, 0xa208, 0x4e02, 0xd040, 0x0004, ++ 0xa220, 0xce90, 0xd151, 0x0000, 0xd150, 0x0001, 0xe41e, 0x09c8, ++ 0xa222, 0xce90, 0xd151, 0x0000, 0xd150, 0x0001, 0xe41e, 0x09c8, ++ 0xa202, 0xe42e, 0x1460, 0xa104, 0x1567, 0xe09d, 0xe408, 0x09bd, ++ 0x1096, 0x268e, 0xcede, 0xd160, 0x0000, 0xd040, 0x000f, 0xa224, ++ 0x4e03, 0x1403, 0xce90, 0xd151, 0x0001, 0xd150, 0x0001, 0xcad8, ++ 0xa000, 0x4e02, 0xe41e, 0x09c8, 0xe40d, 0x09c5, 0x1503, 0xa003, ++ 0x4f03, 0xa135, 0x1400, 0xceda, 0xe409, 0x09a1, 0xcade, 0x4896, ++ 0x4e96, 0xe08c, 0x4e67, 0xa202, 0xe42e, 0xa200, 0xcedc, 0x4e96, ++ 0x4e96, 0xe08c, 0x4e67, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, ++ 0xe41e, 0x09d8, 0xcaae, 0xcc8c, 0xbf28, 0x1400, 0xa104, 0xcc44, ++ 0xe424, 0xd158, 0x0000, 0xe184, 0x09d6, 0xcaa6, 0xbf24, 0xe42e, ++ 0xcab4, 0xd158, 0x0000, 0xf7d8, 0xcaa8, 0x5202, 0xaf04, 0x4e00, ++ 0xcc82, 0xe42a, 0xcaa8, 0xa806, 0x4e01, 0xcc84, 0xe090, 0x1400, ++ 0x0c01, 0xcaab, 0x9380, 0xe42a, 0xcaac, 0xcc86, 0xcaa4, 0xbf20, ++ 0xe190, 0xbf26, 0x1400, 0x0c01, 0xa104, 0xcc44, 0xe424, 0xe184, ++ 0x09fc, 0xcaa4, 0xbf22, 0xe190, 0xbf26, 0xe42e, 0xe004, 0x0042, ++ 0xba8e, 0xbac0, 0xbac0, 0xbac0, 0xbac4, 0xa23c, 0xba8e, 0xa200, ++ 0xbffc, 0x1410, 0xa108, 0xbffc, 0x1411, 0xbffc, 0x1413, 0xbffc, ++ 0xbac0, 0x1450, 0xa102, 0xbffc, 0x1451, 0xa102, 0xbffc, 0xbae0, ++ 0xbae0, 0xbac0, 0xbac0, 0xe41e, 0x0ab9, 0xa202, 0xe42e, 0xe16a, ++ 0xa200, 0xe42e, 0xa200, 0xe41e, 0x0ac3, 0xa200, 0xbffc, 0xbac0, ++ 0x1420, 0xba80, 0xc001, 0x145d, 0xc000, 0xf068, 0x1421, 0xbffc, ++ 0xe408, 0x0a6e, 0xf25e, 0xc001, 0x1459, 0xa102, 0xbffc, 0x145e, ++ 0xbffc, 0xc000, 0xf1b8, 0xe161, 0x00e1, 0x1450, 0x4e91, 0x4e91, ++ 0x4e91, 0x4e91, 0x4e91, 0x4e91, 0x4e91, 0x4e91, 0xe161, 0x00e1, ++ 0xc001, 0x1459, 0xa102, 0xcc44, 0xc000, 0xe184, 0x0a54, 0x1491, ++ 0xa102, 0xe41e, 0x0ac3, 0xe190, 0xe190, 0xe41e, 0x155e, 0x1422, ++ 0xbffc, 0xa200, 0xbffc, 0xbac0, 0xbac1, 0x1423, 0xa134, 0xbffe, ++ 0xa200, 0xbffe, 0x1424, 0xbffe, 0x1425, 0xba80, 0x1426, 0xba80, ++ 0x1427, 0xba80, 0xe41e, 0x0ab9, 0xa202, 0xe42e, 0xe16a, 0xa200, ++ 0xe42e, 0x1453, 0xe41e, 0x0ac3, 0xc001, 0x1561, 0xf04b, 0x1466, ++ 0xc000, 0xf04e, 0xc000, 0x1429, 0xa00a, 0xbffc, 0xa200, 0xe41e, ++ 0x0ac3, 0x162a, 0x5410, 0x1431, 0xe40a, 0x0a89, 0x147b, 0xe41e, ++ 0x0ac3, 0x1427, 0xe408, 0x0ab7, 0xc001, 0x1561, 0xf04b, 0x1466, ++ 0xc000, 0xf03e, 0xc000, 0x1429, 0xe408, 0x0a98, 0xbac0, 0xbac0, ++ 0x142f, 0xe40a, 0x0aa3, 0x1431, 0xe40a, 0x0aa2, 0xbac0, 0xbac0, ++ 0xe40e, 0x0aa3, 0xbac0, 0x142b, 0x0c23, 0xe41e, 0x0add, 0x1425, ++ 0xe40a, 0x0ab5, 0x142c, 0xbffc, 0xa102, 0xe40a, 0x0ab5, 0x142d, ++ 0xaf02, 0xbffe, 0x142e, 0xaf02, 0xbffe, 0xa202, 0xe42e, 0xa200, ++ 0xe42e, 0xbae0, 0xc864, 0xa80e, 0xe42a, 0xa110, 0xe012, 0x4e48, ++ 0xa200, 0x5448, 0xe42e, 0xe002, 0x007e, 0xe400, 0x0acb, 0xe000, ++ 0x007e, 0xbffc, 0xe42e, 0xe000, 0x007f, 0x4e47, 0xaf0e, 0xa20d, ++ 0xaf02, 0xa003, 0xe408, 0x0ad0, 0x4f46, 0x5446, 0xbae0, 0x1447, ++ 0xa203, 0x3546, 0xe046, 0x5446, 0xe42e, 0xe049, 0xae02, 0xb5e0, ++ 0xe401, 0x0ac3, 0xe012, 0xe40e, 0x0ac3, 0xa200, 0x4e40, 0xd1b2, ++ 0x00ff, 0xd1b0, 0x0700, 0xd1b1, 0x0000, 0xe42e, 0xc874, 0xa050, ++ 0xcc74, 0x1440, 0xaf02, 0xe000, 0x0700, 0xe098, 0x1440, 0xa802, ++ 0x4e41, 0xa200, 0xe41e, 0x0b5d, 0xa200, 0xe41e, 0x0b5d, 0xa200, ++ 0xe41e, 0x0b5d, 0xa202, 0xe41e, 0x0b5d, 0x142f, 0xae0a, 0x2630, ++ 0xe41e, 0x0b5d, 0xe088, 0xe002, 0x0700, 0xae02, 0x0441, 0x4e40, ++ 0xe41e, 0x11d3, 0xa2fe, 0x4e43, 0xe42e, 0xc866, 0xe002, 0x0000, ++ 0xae04, 0x4e45, 0xc864, 0xaf06, 0x0445, 0x4e45, 0xe42a, 0xe004, ++ 0x0040, 0xcc6c, 0xbadf, 0xc86e, 0xa140, 0xcc6e, 0xc874, 0xa140, ++ 0xcc74, 0xe41e, 0x0b32, 0xe42e, 0xe004, 0x0100, 0x4e45, 0xe41e, ++ 0x0b32, 0xe42e, 0xd1b7, 0x0000, 0x8840, 0x01b6, 0x8843, 0x01b5, ++ 0x1445, 0xa102, 0xcf66, 0xd1b9, 0x0000, 0xd1b8, 0x0001, 0xcb74, ++ 0xf7fa, 0xa106, 0xf0e4, 0xe004, 0x0100, 0x4e40, 0xe41e, 0x11e7, ++ 0xd1b6, 0x0000, 0xd1b8, 0x0001, 0xcb74, 0xf7fa, 0xa106, 0xf74a, ++ 0x8940, 0x01b6, 0x8943, 0x01b5, 0x1440, 0xe002, 0x0100, 0xe428, ++ 0xe41e, 0x11e7, 0xa200, 0x4e40, 0xe42e, 0x1541, 0xe409, 0x0b65, ++ 0xae10, 0x4e84, 0xe017, 0x4f41, 0xe42e, 0x2684, 0x4e94, 0xe017, ++ 0x4f41, 0xe089, 0xe003, 0x0780, 0xe429, 0xe004, 0x0100, 0x4e40, ++ 0xe41e, 0x11e7, 0xe164, 0x0700, 0xe42e, 0xa200, 0x4e34, 0xe42e, ++ 0xe004, 0x0080, 0xe0c2, 0x0094, 0xe41e, 0x0e8c, 0xe0c0, 0x0044, ++ 0x4600, 0x1450, 0xae08, 0xe0c2, 0x009f, 0xe0c2, 0x018b, 0xe0c2, ++ 0x020a, 0x1549, 0xf029, 0x1470, 0xe0c2, 0x009b, 0xe0c2, 0x0209, ++ 0x1400, 0xe0c2, 0x0219, 0xa206, 0xe0c2, 0x0100, 0x1451, 0xae20, ++ 0x2650, 0xae08, 0xe0c2, 0x0084, 0xa202, 0xae2a, 0x2600, 0xae04, ++ 0x2628, 0xae10, 0xa904, 0xe0c2, 0x0080, 0xa204, 0xe0c1, 0x0064, ++ 0xa821, 0xf04b, 0xe0c1, 0x0064, 0xa81f, 0xae05, 0xe056, 0xe00a, ++ 0x1800, 0x1549, 0xf03b, 0xe008, 0xffc3, 0xe0c2, 0x00fa, 0xa202, ++ 0xae0a, 0xe0c2, 0x00e7, 0xa204, 0x2600, 0xae20, 0x1550, 0xae09, ++ 0xe056, 0xa203, 0xae2b, 0xe056, 0xe0c2, 0x0282, 0x1450, 0xae20, ++ 0x2651, 0xae08, 0xe0c2, 0x0283, 0x1450, 0xae0c, 0x2651, 0xe0c2, ++ 0x0183, 0xa206, 0xe0c2, 0x018d, 0xa258, 0xe0c2, 0x0182, 0xa202, ++ 0xae3e, 0xa906, 0xe0c2, 0x00ec, 0xa200, 0xe0c2, 0x0102, 0xa202, ++ 0xe0c2, 0x0102, 0xa204, 0xe0c2, 0x0102, 0xe0c0, 0x0060, 0xe0c2, ++ 0x0098, 0xe0c0, 0x0061, 0xe0c2, 0x0099, 0xe0c0, 0x0062, 0xe0c2, ++ 0x009a, 0xc001, 0x1448, 0xf0ea, 0x1040, 0x2641, 0xe0c2, 0x009c, ++ 0x1042, 0x2643, 0xe0c2, 0x009d, 0x1044, 0x2645, 0xe0c2, 0x009e, ++ 0xf16e, 0xc000, 0xe0c1, 0x0041, 0xe004, 0x0350, 0xae10, 0xe042, ++ 0xe0c2, 0x009c, 0xe004, 0x03e0, 0xae10, 0xe042, 0xe0c2, 0x009d, ++ 0xe004, 0x0428, 0xae10, 0xe042, 0xe0c2, 0x009e, 0xc000, 0x8234, ++ 0xc786, 0xe018, 0xe000, 0x0570, 0xe09e, 0x1097, 0x2697, 0xe0c2, ++ 0x0188, 0x1097, 0x2697, 0xe0c2, 0x0189, 0x1097, 0x2697, 0xe0c2, ++ 0x018a, 0x8235, 0xc786, 0xe018, 0xe000, 0x0570, 0xe09e, 0x1097, ++ 0x2697, 0xe0c2, 0x02c0, 0x1097, 0x2697, 0xe0c2, 0x02c1, 0x1097, ++ 0x2697, 0xe0c2, 0x02c2, 0x1434, 0xe0c2, 0x0072, 0x4e35, 0xa002, ++ 0x4e34, 0x0c32, 0xf028, 0x4e34, 0xe41e, 0x0c56, 0xa200, 0x4e71, ++ 0x4e56, 0x4e57, 0xa228, 0xae20, 0xe00a, 0x1111, 0xe0c2, 0x00a2, ++ 0xa200, 0x4e74, 0xce52, 0x1450, 0xce50, 0xe42e, 0xa200, 0xe0c2, ++ 0x0207, 0x8250, 0xe182, 0x0340, 0xe018, 0xe0c2, 0x0208, 0x1451, ++ 0xae08, 0xa102, 0xae20, 0x1550, 0xae09, 0xa103, 0xe056, 0xe0c2, ++ 0x0201, 0xe0c0, 0x0060, 0xe0c2, 0x0202, 0xe0c0, 0x02c0, 0xe0c2, ++ 0x0203, 0x142b, 0xa558, 0xa41c, 0xaf02, 0xa10e, 0x0436, 0xa51e, ++ 0x4e01, 0xae04, 0xe000, 0x0448, 0xe09e, 0x1097, 0x2697, 0xe0c2, ++ 0x0204, 0x1087, 0x2697, 0xe0c2, 0x0205, 0x1497, 0xe0c2, 0x021a, ++ 0x1401, 0xae02, 0x0401, 0xe000, 0x05a0, 0xe09e, 0x1697, 0xe0c2, ++ 0x021f, 0x1097, 0x2697, 0xe0c2, 0x021e, 0x1428, 0xe016, 0xe0c2, ++ 0x0206, 0xa24c, 0x2628, 0xe0c2, 0x0200, 0xa200, 0x4e72, 0x4e73, ++ 0xe004, 0x051a, 0x4e78, 0x4e79, 0xd008, 0x000d, 0xd009, 0x051a, ++ 0xd00a, 0x0542, 0xe42e, 0xa202, 0x0c28, 0xae30, 0xe0c2, 0x00a1, ++ 0x1428, 0xe016, 0xae0a, 0xe0c2, 0x0083, 0x1428, 0xe428, 0xa202, ++ 0xe0c2, 0x0093, 0xe41e, 0x0eb1, 0xe42e, 0x1428, 0xf05a, 0xe41e, ++ 0x0861, 0x1477, 0x4e76, 0xa216, 0x0c28, 0xae30, 0xe0c2, 0x00a1, ++ 0x1428, 0xae0c, 0xa940, 0xe0c2, 0x0083, 0xa202, 0xe0c2, 0x0093, ++ 0x1428, 0xae02, 0xe0c2, 0x0280, 0xe42e, 0xe161, 0x04e0, 0x1491, ++ 0x4e00, 0x1481, 0x4e01, 0xa202, 0x1553, 0xb60a, 0x4e0b, 0xb616, ++ 0x4e0c, 0xa103, 0xb616, 0x4e0d, 0xa202, 0x0d52, 0xa007, 0xb602, ++ 0x4e0e, 0xb616, 0x4e0f, 0x140f, 0x2228, 0x4e07, 0x4e08, 0x140e, ++ 0x4e02, 0x4e04, 0x2228, 0x4e06, 0x140b, 0x4e03, 0x140c, 0x4e05, ++ 0xe41e, 0x0d76, 0x1406, 0xe418, 0x0e86, 0x1405, 0xe418, 0x0dfa, ++ 0x1402, 0xe418, 0x0db2, 0x1403, 0xe418, 0x0e2b, 0x1404, 0xe418, ++ 0x0e18, 0x1407, 0xe418, 0x0861, 0x1401, 0xae08, 0x2671, 0xe0c2, ++ 0x0101, 0x140d, 0xae1c, 0x260a, 0xe0c2, 0x00e6, 0x1552, 0xa107, ++ 0x0d53, 0xa216, 0xb496, 0xb6aa, 0x0c28, 0xae30, 0xe0c2, 0x00a1, ++ 0x1458, 0xe016, 0xae02, 0x265c, 0xae10, 0x2662, 0x1563, 0xae19, ++ 0xe056, 0xe0c2, 0x0082, 0x140d, 0xae04, 0x260c, 0xae02, 0x1528, ++ 0x230f, 0xe056, 0xae02, 0x1528, 0xe017, 0x230e, 0x270f, 0xe056, ++ 0xae02, 0x260b, 0xae02, 0x260e, 0xae02, 0x260e, 0xae04, 0x260e, ++ 0xe0c2, 0x0083, 0xa202, 0xe0c2, 0x0093, 0x1408, 0xae02, 0xe0c2, ++ 0x0280, 0x1471, 0xe016, 0x4e71, 0x1477, 0x4e76, 0xe42e, 0xe41e, ++ 0x0eb1, 0xe41e, 0x0dfa, 0xa200, 0xe0c2, 0x00a1, 0xa202, 0xae1c, ++ 0x260a, 0xe0c2, 0x00e6, 0xe004, 0x0280, 0xe0c2, 0x0083, 0xa202, ++ 0xe0c2, 0x0093, 0xe41e, 0x0eb1, 0xe0c0, 0x0184, 0x4e0a, 0xa202, ++ 0xae1c, 0x260a, 0xe0c2, 0x00e6, 0xe004, 0x0200, 0xe0c2, 0x0083, ++ 0xa202, 0xe0c2, 0x0093, 0xe41e, 0x0eb1, 0xe42e, 0xe0c0, 0x0095, ++ 0xf378, 0xe0c0, 0x0281, 0xaf02, 0x2206, 0xe0c1, 0x0096, 0xe052, ++ 0xe0c1, 0x0096, 0xaf05, 0xe052, 0xe0c1, 0x0096, 0xaf0b, 0xe052, ++ 0xe418, 0x0e86, 0xe0c0, 0x0096, 0xaf0a, 0x2202, 0xe418, 0x0db2, ++ 0xe0c0, 0x0096, 0xaf0e, 0x2205, 0xe418, 0x0dfa, 0xe0c0, 0x0096, ++ 0xaf06, 0x2204, 0x1503, 0x2702, 0xe017, 0xe052, 0xe418, 0x0e18, ++ 0xe0c0, 0x0096, 0xaf06, 0x2203, 0xe418, 0x0e2b, 0xe0c0, 0x0218, ++ 0x2207, 0x1506, 0xe017, 0xe052, 0xe418, 0x0861, 0xf48e, 0xe0c2, ++ 0x0095, 0xe42e, 0xa200, 0x4e02, 0x1515, 0x2328, 0x142b, 0xe419, ++ 0x0f93, 0x4e62, 0x0424, 0xa400, 0xa566, 0xe000, 0x0414, 0xe09c, ++ 0x1486, 0x4e63, 0xe0c0, 0x00f5, 0xe049, 0xaf20, 0xe009, 0xffff, ++ 0xe066, 0xe0c1, 0x00f4, 0xe065, 0x1462, 0xaf04, 0xe000, 0x0488, ++ 0xe09e, 0x0d87, 0xa200, 0xb62a, 0x4e5c, 0xc001, 0x1461, 0xc000, ++ 0xf0ba, 0x143a, 0xf058, 0xc001, 0x1465, 0xc000, 0xf06e, 0xc001, ++ 0x1467, 0xc000, 0xf02e, 0x1428, 0xe016, 0x0587, 0xe408, 0x0df3, ++ 0xe001, 0x0280, 0x0f76, 0xb62a, 0x151c, 0xf068, 0xe419, 0x115d, ++ 0x155c, 0xb615, 0x4f5c, 0x4e58, 0x145c, 0x1562, 0xa109, 0xb60e, ++ 0x4e5c, 0xe42e, 0xe161, 0x04f0, 0xe162, 0x0190, 0xd022, 0x000d, ++ 0xe184, 0x0e03, 0x1491, 0x9f12, 0xe0c0, 0x0184, 0x4e0a, 0x1456, ++ 0xae0c, 0x2657, 0xe0c2, 0x0184, 0x1456, 0xa002, 0x4e56, 0x0c50, ++ 0xa201, 0x4f05, 0xe428, 0x4e56, 0x1457, 0xa002, 0x4e57, 0xe42e, ++ 0x1474, 0xce52, 0x1458, 0xe418, 0x0e5b, 0x1426, 0xe016, 0x2658, ++ 0xce56, 0x1474, 0xa002, 0x4e74, 0x0c50, 0xa201, 0x4f04, 0xe428, ++ 0xa200, 0x4e74, 0xe42e, 0x1400, 0xa201, 0x4f03, 0xe40a, 0x0e58, ++ 0x1401, 0xe408, 0x0e50, 0x1465, 0xe09c, 0x1486, 0xcece, 0xe160, ++ 0x04d0, 0xe161, 0x04b0, 0xe162, 0x00c0, 0xd160, 0x0000, 0xd022, ++ 0x000f, 0xe184, 0x0e47, 0xcac8, 0x4e90, 0x9e12, 0x4e91, 0xceca, ++ 0xcace, 0x4e96, 0xe08c, 0x4e65, 0xe0c0, 0x00e4, 0x4e5e, 0xe42e, ++ 0x1475, 0x4e5d, 0xe0c0, 0x00e4, 0x4e5e, 0xe41e, 0x110b, 0xe42e, ++ 0xe41e, 0x110b, 0xe42e, 0xca58, 0xc001, 0x155d, 0xf02b, 0x225f, ++ 0xc000, 0xe0c2, 0x00a0, 0xca58, 0xc001, 0x155d, 0xf02b, 0x225f, ++ 0xc000, 0x4e09, 0xcacc, 0xe0c2, 0x00a3, 0xe004, 0x0100, 0x0474, ++ 0xe09c, 0x1486, 0xe0c2, 0x00a4, 0xe0c0, 0x00f9, 0xaf20, 0x2209, ++ 0x155c, 0xe0c2, 0x00e4, 0xe42b, 0xe0c0, 0x00f8, 0xaf20, 0x2209, ++ 0xa104, 0xe012, 0xe0c2, 0x00c0, 0x4e75, 0xe42e, 0xa202, 0xe0c2, ++ 0x020b, 0xa200, 0x4e06, 0xe42e, 0xe004, 0x3211, 0xae20, 0xe00a, ++ 0x2100, 0xe0c2, 0x00ee, 0xe004, 0x9211, 0xae20, 0xe00a, 0x2100, ++ 0xe0c2, 0x00d8, 0xe004, 0x1000, 0xae20, 0xe00a, 0x0000, 0xe0c2, ++ 0x00ef, 0xe0c2, 0x00d9, 0xe004, 0x0104, 0xe0c2, 0x00f2, 0xe0c2, ++ 0x00da, 0xe42e, 0xe0c0, 0x0218, 0xf7ea, 0xa200, 0xe0c2, 0x0218, ++ 0xe42e, 0xe0c0, 0x0095, 0xf7ea, 0xe0c2, 0x0095, 0xe42e, 0x1571, ++ 0xa105, 0x1471, 0xa002, 0xb616, 0x4e71, 0xe42e, 0xc001, 0xa268, ++ 0x4e04, 0xa218, 0x4e06, 0xa250, 0x156d, 0xf03b, 0xe0c0, 0x0072, ++ 0x4e05, 0xa210, 0x4e07, 0xe004, 0x0495, 0x4e08, 0xc000, 0x1414, ++ 0x1552, 0xc001, 0x4e09, 0x4f0f, 0xc000, 0x1617, 0xc710, 0x3c18, ++ 0xe008, 0xffff, 0xa002, 0xaf02, 0xc001, 0x4e0b, 0x4e3b, 0xe004, ++ 0x1000, 0x156c, 0xf03b, 0xe0c0, 0x0073, 0x4e0c, 0x1409, 0xe016, ++ 0x4e0a, 0xf06a, 0x140b, 0x4e09, 0xe004, 0x1000, 0x4e0c, 0xc000, ++ 0x8218, 0xe182, 0x7530, 0xe018, 0xae02, 0x1717, 0xc001, 0xe41e, ++ 0x1047, 0x4e18, 0x8218, 0x8100, 0xe018, 0xa279, 0xe41e, 0x1030, ++ 0x4818, 0x4e19, 0xae06, 0x1504, 0xe41e, 0x1030, 0x481e, 0x4e1f, ++ 0xa202, 0x4e0d, 0xa205, 0xc000, 0x0d36, 0xc001, 0xae03, 0xa011, ++ 0x4f14, 0x150f, 0x3514, 0xe013, 0x492e, 0x4f2f, 0x1439, 0x1538, ++ 0xf039, 0xe41e, 0x0fd8, 0x4e10, 0xa004, 0x4e11, 0xe41e, 0x0ffe, ++ 0xc000, 0xe42e, 0xe42e, 0x1428, 0xc001, 0x4e0e, 0xa201, 0x4f2d, ++ 0xe418, 0x0fba, 0xa200, 0x4e20, 0x4e21, 0x140e, 0xf248, 0x140d, ++ 0xf05a, 0xa200, 0x4e0d, 0x1410, 0xf26e, 0x1409, 0xa102, 0xf7ca, ++ 0x1538, 0xf03b, 0x1410, 0xf1fe, 0x820f, 0x8135, 0xe019, 0xe04a, ++ 0xaf02, 0x0022, 0x0623, 0xe41e, 0x1047, 0xa21f, 0x4f14, 0x1509, ++ 0xc70f, 0x3d14, 0xe009, 0xffff, 0xa405, 0xe046, 0x3006, 0x3205, ++ 0x4e10, 0xf09e, 0xa200, 0x4e1c, 0x4e1d, 0x1411, 0x152d, 0xf02b, ++ 0x1405, 0x4e13, 0x152d, 0xc000, 0xe42e, 0xc001, 0xc874, 0xe41e, ++ 0x1007, 0x140e, 0xf0ea, 0x1020, 0x2621, 0xc710, 0x3c0f, 0xe008, ++ 0xffff, 0xa002, 0xaf02, 0x4e11, 0x1020, 0x2621, 0x0022, 0x0623, ++ 0x4822, 0x4e23, 0x1435, 0xa002, 0x4e35, 0x140e, 0xf028, 0x4e35, ++ 0x140e, 0xf0f8, 0x1509, 0xa103, 0x1026, 0x2627, 0xe41e, 0x1030, ++ 0x482a, 0x4e2b, 0x0826, 0x0e27, 0xe012, 0x4828, 0x4e29, 0xf0ae, ++ 0x1128, 0x2729, 0x092a, 0x0f2b, 0x140a, 0xb606, 0xb611, 0x4928, ++ 0x4f29, 0xc000, 0xe42e, 0xc001, 0x111c, 0x271d, 0x101e, 0x261f, ++ 0xe041, 0xf097, 0xe045, 0xe045, 0x1413, 0xf095, 0x491c, 0x4f1d, ++ 0xa002, 0xf05e, 0x491c, 0x4f1d, 0x1413, 0xa102, 0x3006, 0x3205, ++ 0x4e13, 0xc000, 0xe42e, 0xc001, 0x0020, 0x0621, 0x4820, 0x4e21, ++ 0xc000, 0x146c, 0xc001, 0x0c12, 0x001c, 0x061d, 0x481c, 0x4e1d, ++ 0xc000, 0xe42e, 0x1028, 0x2629, 0x0826, 0x0e27, 0x820c, 0xe41e, ++ 0x107e, 0x0018, 0x0619, 0xf052, 0x152c, 0xf039, 0xa203, 0x4f2d, ++ 0xe41e, 0x1016, 0x1118, 0x2719, 0xaf07, 0xe062, 0x481a, 0x4e1b, ++ 0xc710, 0x3c0f, 0xe008, 0xffff, 0xa002, 0xaf02, 0x4e12, 0xe42e, ++ 0x8209, 0x1018, 0x2619, 0xe41e, 0x1072, 0x8207, 0xe41e, 0x1072, ++ 0x1509, 0xa103, 0x0507, 0xe41e, 0x1030, 0x481a, 0x4e1b, 0x140f, ++ 0xae08, 0x4e30, 0x101a, 0x261b, 0xae04, 0x001a, 0x061b, 0xae02, ++ 0xc70f, 0x3c30, 0xe008, 0xffff, 0xa010, 0xaf08, 0xc000, 0x0436, ++ 0xc001, 0xa51e, 0x0408, 0xe09e, 0x1487, 0xe42e, 0x8200, 0x8101, ++ 0xe018, 0x4824, 0x4e25, 0xa200, 0x4826, 0x4e27, 0xe42e, 0x0818, ++ 0x0e19, 0x0026, 0x0627, 0x4826, 0x4e27, 0x112e, 0x272f, 0xe046, ++ 0xf032, 0x4926, 0x4f27, 0x1026, 0x1427, 0xe42e, 0x1501, 0xe42b, ++ 0x1124, 0x2725, 0x0926, 0x0f27, 0xe066, 0xf051, 0x152c, 0xf039, ++ 0xa203, 0x4f2d, 0x1102, 0x2703, 0xe42b, 0x1124, 0x2725, 0x0926, ++ 0x0f27, 0x0118, 0x0719, 0x0902, 0x0f03, 0xa401, 0xe062, 0xe42e, ++ 0x4f30, 0xa201, 0xf032, 0xe012, 0xa203, 0x4f34, 0x4e31, 0xaf20, ++ 0xc70f, 0x3c30, 0x4e32, 0xaf20, 0xae20, 0x2631, 0xc70f, 0x3c30, ++ 0x4e33, 0x1032, 0x2633, 0x1534, 0xe42b, 0xe012, 0xe42e, 0x4930, ++ 0x4f31, 0xa201, 0x4f32, 0x1130, 0x2731, 0x3532, 0xe045, 0xf061, ++ 0x1532, 0xa003, 0x4f32, 0xa121, 0xf775, 0x1532, 0xf039, 0xa200, ++ 0xe42e, 0xa103, 0x4f32, 0xcc45, 0xa201, 0x4f33, 0xe184, 0x106f, ++ 0x1533, 0xae03, 0x4f33, 0x1130, 0x2731, 0x3532, 0xe045, 0xf061, ++ 0xe013, 0xe04a, 0x1533, 0xa003, 0x4f33, 0x1532, 0xa103, 0x4f32, ++ 0x1433, 0xe42e, 0xae02, 0x4831, 0xe008, 0xffff, 0xaf02, 0x4e30, ++ 0x8131, 0xe018, 0xae1e, 0x8130, 0xe01c, 0xe42e, 0xae02, 0x4831, ++ 0xe008, 0xffff, 0xaf02, 0x4e30, 0x8130, 0xe018, 0xaf1e, 0x8131, ++ 0xe01c, 0xe42e, 0xae02, 0x4831, 0xe008, 0xffff, 0xaf02, 0x4e30, ++ 0x8131, 0xe018, 0xa103, 0x4f32, 0x3432, 0x8130, 0xa11f, 0xe013, ++ 0x4f32, 0xe019, 0x3732, 0xe042, 0xe42e, 0xe161, 0x0376, 0xd022, ++ 0x002d, 0xa2fc, 0x4e00, 0xe184, 0x10a7, 0x1481, 0x2200, 0x4e91, ++ 0xca40, 0x2200, 0xce40, 0xca46, 0x2200, 0xce46, 0xe42e, 0xe004, ++ 0x0376, 0x4e64, 0xe004, 0x0100, 0x4e65, 0xe004, 0x012d, 0x4e66, ++ 0xe004, 0x0187, 0x4e67, 0xe004, 0x01e1, 0x4e68, 0xa2fd, 0xca40, ++ 0xe052, 0xce40, 0xca46, 0xe052, 0xce46, 0xe42e, 0x1454, 0xe41a, ++ 0x10af, 0x1464, 0xe09c, 0x1496, 0xce42, 0x1486, 0xce44, 0xca4a, ++ 0xcec4, 0xcf34, 0xca4c, 0x1526, 0xb7f6, 0xca4b, 0xe052, 0xcec2, ++ 0x4e69, 0xe42e, 0x1464, 0xe09c, 0x1459, 0x4e96, 0xce40, 0xca42, ++ 0xce46, 0xe08c, 0x4e64, 0x1454, 0xa002, 0x4e54, 0x0c50, 0xe428, ++ 0xa200, 0x4e54, 0x1455, 0xa002, 0x4e55, 0x0c51, 0xe42e, 0xe049, ++ 0x1466, 0xe09c, 0x1096, 0x268e, 0xced6, 0xa200, 0xcec0, 0xd022, ++ 0x000f, 0xe184, 0x10fc, 0xced3, 0xe190, 0xcad6, 0x4896, 0x4e96, ++ 0xe08c, 0x4e66, 0x1467, 0xe09c, 0xcad6, 0xcedc, 0x4896, 0x4e96, ++ 0xe08c, 0x4e67, 0xe42e, 0x1465, 0xe09c, 0xe004, 0x2222, 0x4e96, ++ 0xcecc, 0xe08c, 0x4e65, 0xe42e, 0x1468, 0xe09c, 0xa220, 0xae34, ++ 0x4896, 0x4e96, 0x4896, 0x4e96, 0x4896, 0x4e96, 0x1196, 0x278e, ++ 0xcf33, 0x4896, 0x4e96, 0xcf20, 0xcf22, 0xcf24, 0xcf26, 0xa200, ++ 0x4e96, 0xe08c, 0x4e68, 0xe42e, 0x1468, 0xe09c, 0x1096, 0x2696, ++ 0xcf28, 0x1096, 0x2696, 0xcf2a, 0x1096, 0x2696, 0xcf2c, 0x1096, ++ 0x2696, 0xcf2e, 0x8896, 0x01ab, 0x1096, 0x2696, 0xcf30, 0xe42e, ++ 0x1468, 0xe09c, 0xcb28, 0x4896, 0x4e96, 0xcb2a, 0x4896, 0x4e96, ++ 0xcb2c, 0x4896, 0x4e96, 0xcb2e, 0x4896, 0x4e96, 0x8996, 0x01ab, ++ 0xe08c, 0x4e68, 0xe42e, 0xa200, 0xc001, 0x4e4c, 0x4e6a, 0x4e3e, ++ 0xc000, 0xe42e, 0xa200, 0x4e1d, 0xe42e, 0xc001, 0x143f, 0xc000, ++ 0xf2a8, 0x141d, 0x0c1c, 0xe402, 0x11b6, 0x1453, 0xa002, 0xc001, ++ 0x0c4c, 0xc000, 0xe404, 0x11b6, 0xc001, 0x144c, 0x044b, 0x0c6b, ++ 0xc000, 0xf0d4, 0xc001, 0x146a, 0xa002, 0xc70f, 0x3c4b, 0xaf20, ++ 0x4e6a, 0x4e4c, 0xc000, 0x141c, 0x4e1d, 0xf37e, 0x141d, 0xa002, ++ 0x4e1d, 0xc001, 0x144c, 0x044b, 0xc70f, 0x3c6b, 0xaf20, 0x4e4c, ++ 0xc000, 0xf2be, 0x141d, 0x0c1c, 0xf2a2, 0x1453, 0xa002, 0xc001, ++ 0x0c4d, 0xc000, 0xf244, 0xc001, 0x144d, 0x044b, 0xc000, 0x0c52, ++ 0xf0e4, 0xc001, 0x143e, 0xa002, 0xc70f, 0x3c4b, 0xaf20, 0x4e3e, ++ 0x046b, 0x4e4d, 0xc000, 0x141c, 0x4e1d, 0xf0fe, 0x141d, 0xa002, ++ 0x4e1d, 0xc001, 0x144d, 0x044b, 0xc000, 0xc70f, 0x3c52, 0xaf20, ++ 0xc001, 0x4e4d, 0xc000, 0xf01e, 0xa202, 0xe42e, 0xa200, 0xe42e, ++ 0xa200, 0xc001, 0x484a, 0xc000, 0x4e4d, 0xe0c0, 0x0060, 0x484a, ++ 0x4e4b, 0xe0c0, 0x0061, 0xae04, 0xc001, 0x4849, 0xc000, 0x4e4c, ++ 0xe41e, 0x11d3, 0xe41e, 0x1279, 0xe12c, 0xd071, 0x002a, 0xe181, ++ 0xe41e, 0x0ae5, 0xe42e, 0xe12c, 0xd030, 0x0000, 0xd032, 0x0000, ++ 0xd033, 0x0000, 0xd034, 0x0000, 0xd035, 0x003f, 0xd036, 0x0000, ++ 0xd037, 0x0000, 0xe42e, 0xc000, 0xe41e, 0x0b2c, 0xe470, 0xc001, ++ 0x145d, 0xc000, 0xf06a, 0xe0c0, 0x0059, 0xa106, 0xe40a, 0x1759, ++ 0xd111, 0x0700, 0xe082, 0x4e4e, 0xe0c0, 0x005a, 0xae02, 0xe000, ++ 0x0048, 0xe092, 0xe41e, 0x1289, 0x104a, 0x264b, 0xc001, 0x134a, ++ 0xc000, 0x274d, 0xae11, 0xe042, 0xce20, 0x8091, 0xd112, 0x0080, ++ 0xa204, 0xe0c1, 0x0043, 0xa803, 0xb6d6, 0xce26, 0xca28, 0xf7f8, ++ 0xc001, 0x124a, 0xc000, 0x264d, 0xe000, 0x0001, 0xc001, 0x484a, ++ 0xc000, 0x4e4d, 0xc001, 0x1349, 0xc000, 0x274c, 0xe046, 0xf0a4, ++ 0x157d, 0xf04b, 0xa203, 0xe0c3, 0x0074, 0xc001, 0x484a, 0xc000, ++ 0x4e4d, 0x104a, 0x264b, 0xc001, 0x134a, 0xc000, 0x274d, 0xae11, ++ 0xe042, 0x9f01, 0x144e, 0xe092, 0xe42e, 0xe41e, 0x11e7, 0xe0c0, ++ 0x005a, 0xae02, 0xe000, 0x0049, 0xe092, 0x9e01, 0x114a, 0x274b, ++ 0xe045, 0xf049, 0x114a, 0x274b, 0xe042, 0x0440, 0xe002, 0x0100, ++ 0x9f01, 0xe42e, 0xd111, 0x0700, 0xe0c0, 0x005a, 0xae02, 0xe000, ++ 0x0048, 0xe092, 0xe41e, 0x1289, 0x104a, 0x264b, 0xc001, 0x134a, ++ 0xc000, 0x274d, 0xae11, 0xe042, 0xce20, 0x8091, 0xd112, 0x0080, ++ 0xa204, 0xe0c1, 0x0043, 0xa803, 0xb6d6, 0xce26, 0xca28, 0xf7f8, ++ 0x104a, 0x264b, 0xc001, 0x134a, 0xc000, 0x274d, 0xae11, 0xe042, ++ 0x0440, 0x9f01, 0x1640, 0xc001, 0x4e4f, 0xa202, 0x4e4e, 0xc000, ++ 0xe42e, 0x104a, 0x264b, 0xc001, 0x134a, 0xc000, 0x274d, 0xae11, ++ 0xe042, 0xe0c1, 0x005a, 0xae03, 0xe001, 0x0049, 0xe093, 0x9f01, ++ 0xe42e, 0xe0c1, 0x0043, 0xa805, 0xe429, 0x157d, 0xe429, 0xa200, ++ 0x4e4f, 0x104a, 0x264b, 0xc001, 0x134a, 0xc000, 0x274d, 0xae11, ++ 0xe042, 0xc001, 0x174e, 0xf03b, 0x174f, 0xe042, 0xc000, 0x9e81, ++ 0xe045, 0xf071, 0xc001, 0x1249, 0xc000, 0x264c, 0xae10, 0xe041, ++ 0xe003, 0x0100, 0xc001, 0x164e, 0xf06a, 0x164f, 0xe041, 0xa200, ++ 0x4e4e, 0x4e4f, 0xc000, 0xe421, 0x144f, 0xf5c8, 0xe0c0, 0x005c, ++ 0xe008, 0x8000, 0xf57a, 0xe0c0, 0x005d, 0xe00a, 0x8000, 0xe0c2, ++ 0x005d, 0xa202, 0xce00, 0x4e4f, 0xf4de, 0xa200, 0xcc4a, 0xcc4c, ++ 0xe0c2, 0x0074, 0x157d, 0x277c, 0xf02b, 0x4e40, 0x147b, 0xaa02, ++ 0x4e7b, 0x147d, 0xf15a, 0x147e, 0xf0ca, 0xe0c0, 0x0066, 0x484a, ++ 0x4e4b, 0xe0c0, 0x0067, 0xae04, 0xc001, 0x4849, 0xc000, 0x4e4c, ++ 0xa200, 0xc001, 0x484a, 0xc000, 0x4e4d, 0xe41e, 0x1279, 0xd180, ++ 0x0005, 0xd147, 0x0003, 0xd03b, 0x0001, 0xd008, 0x0000, 0xe16a, ++ 0xe004, 0x0123, 0xae20, 0xe00a, 0x4567, 0xcf50, 0xe004, 0x89ab, ++ 0xae20, 0xe00a, 0xcdef, 0xcf52, 0xa200, 0xcf06, 0xe0c2, 0x0286, ++ 0x141b, 0xe418, 0x0507, 0xe41e, 0x0459, 0xe41e, 0x115a, 0x1428, ++ 0xf07a, 0xc001, 0x143f, 0xa002, 0xa802, 0x4e3f, 0xc000, 0xe41e, ++ 0x0b78, 0xe41e, 0x0cab, 0xe41e, 0x0cbd, 0xe41e, 0x07a4, 0xa200, ++ 0x4e53, 0x4e54, 0x4e55, 0x4e1f, 0xe41e, 0x155e, 0xe41e, 0x14a0, ++ 0xe41e, 0x15ea, 0xe41e, 0x134a, 0x1453, 0x0c52, 0xf7c4, 0xe41e, ++ 0x0d4f, 0x1415, 0xe418, 0x0f5d, 0xe41e, 0x11e7, 0xe41e, 0x171a, ++ 0x162a, 0xa002, 0x4e2a, 0x1633, 0xa002, 0x4e33, 0xe0c2, 0x0070, ++ 0x1428, 0xe0c2, 0x0071, 0xc001, 0x1459, 0xc000, 0xe0c2, 0x0073, ++ 0xd03a, 0x0000, 0xc84a, 0xc84d, 0xae20, 0xe056, 0xe0c2, 0x0046, ++ 0xa202, 0xe42e, 0xe41e, 0x1408, 0xc001, 0xa200, 0x4e57, 0x4e58, ++ 0xc000, 0x1531, 0xa20a, 0xb636, 0x4e30, 0xe41e, 0x0aee, 0xe41e, ++ 0x1781, 0xe41e, 0x11e7, 0xe41e, 0x143f, 0xc001, 0x1458, 0xa002, ++ 0x4e58, 0x4e57, 0x1559, 0xe046, 0xc000, 0xf6c8, 0xc001, 0xa200, ++ 0x4e58, 0x4e57, 0xc000, 0xe41e, 0x146f, 0xe41e, 0x17a4, 0xe41e, ++ 0x1372, 0xe42e, 0x142c, 0xae0a, 0x152d, 0xa83f, 0xe056, 0xae0a, ++ 0x152e, 0xa83f, 0xe056, 0xce4e, 0xe41e, 0x109d, 0xa200, 0x4e5b, ++ 0x4e3a, 0xa202, 0x4e3b, 0xc001, 0x1457, 0x4e58, 0xc000, 0xe41e, ++ 0x13f5, 0xc001, 0x145a, 0xc000, 0xf078, 0xe41e, 0x0a71, 0xc001, ++ 0xa202, 0x4e5a, 0xc000, 0xe41e, 0x153f, 0xe41e, 0x06aa, 0xe41e, ++ 0x07b1, 0x145b, 0x045a, 0x4e5b, 0x896b, 0x003a, 0x1419, 0xe418, ++ 0x04b4, 0xe41e, 0x06fb, 0xe41e, 0x17c3, 0xe41e, 0x1781, 0xe41e, ++ 0x11e7, 0xc874, 0x0e6b, 0xe008, 0xffff, 0x4e6c, 0x145a, 0xe012, ++ 0x225b, 0x4e5b, 0xe41e, 0x06c1, 0x1515, 0x1462, 0x4e61, 0xe419, ++ 0x0fab, 0x1453, 0xa002, 0x4e53, 0xe41e, 0x14b8, 0xe41e, 0x10da, ++ 0xf03a, 0xe40e, 0x1387, 0xc001, 0x1457, 0x4e58, 0xa200, 0x4e57, ++ 0xc000, 0xe41e, 0x143f, 0xa200, 0xe161, 0x0700, 0xd022, 0x00ff, ++ 0x4e91, 0x4e91, 0x4e91, 0x4e91, 0x4e91, 0x4e91, 0x4e91, 0x4e91, ++ 0x4e91, 0x4e91, 0xe41e, 0x146f, 0xe41e, 0x17a4, 0x145b, 0xe418, ++ 0x0ac3, 0xe41e, 0x0ab9, 0xe41e, 0x17cd, 0xe41e, 0x11e7, 0xc001, ++ 0x1457, 0xa002, 0x4e57, 0x1559, 0xc000, 0xe045, 0xf5d1, 0x1515, ++ 0x1462, 0xf02b, 0x4e2b, 0xa202, 0xe42e, 0xc001, 0x1457, 0x4e58, ++ 0xc000, 0xe41e, 0x15db, 0xc001, 0x1457, 0x1558, 0xc000, 0xe046, ++ 0xf05a, 0xe41e, 0x143f, 0xe41e, 0x146f, 0xe41e, 0x17a4, 0xe42e, ++ 0xc001, 0xe161, 0x07ae, 0xc000, 0xa2fe, 0x4e43, 0xa200, 0x4e5b, ++ 0x4e91, 0xc001, 0x4e50, 0x4e91, 0x4e51, 0x4e91, 0x4e52, 0x4e91, ++ 0x4e5a, 0x4e91, 0xc000, 0x142b, 0x4e61, 0x4e91, 0xc001, 0xa200, ++ 0x4e91, 0x4e91, 0x4e91, 0x4e91, 0x4e91, 0x4e58, 0x1458, 0xae0e, ++ 0xe005, 0x0340, 0xae11, 0xe042, 0xe0c1, 0x0041, 0xe042, 0xce20, ++ 0xd111, 0x07ae, 0xd112, 0x002a, 0xd113, 0x0002, 0xca28, 0xf7f8, ++ 0x1458, 0xa002, 0x4e58, 0xa110, 0xf6a4, 0xc000, 0xe42e, 0xc000, ++ 0xe161, 0x07ae, 0x145b, 0x4e91, 0x1443, 0x4e91, 0xc001, 0x1450, ++ 0x4e91, 0x1451, 0x4e91, 0x1452, 0x4e91, 0x145a, 0x4e91, 0xc000, ++ 0x1461, 0x4e91, 0xc001, 0x8991, 0x0032, 0xc860, 0x4891, 0x4e91, ++ 0xc862, 0x4891, 0x4e91, 0x1458, 0xae0e, 0xe005, 0x0340, 0xae11, ++ 0xe042, 0xe0c1, 0x0041, 0xe042, 0xce20, 0xd111, 0x07ae, 0xd112, ++ 0x002a, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xc000, 0xe42e, 0xc001, ++ 0x1457, 0xae0e, 0xe005, 0x0340, 0xae11, 0xe042, 0xe0c1, 0x0041, ++ 0xe042, 0xce20, 0xd111, 0x07ae, 0xd112, 0x002a, 0xd113, 0x0003, ++ 0xca28, 0xf7f8, 0xe161, 0x07ae, 0xc000, 0x1491, 0x4e5b, 0x1491, ++ 0x4e43, 0xc001, 0x1491, 0x4e50, 0x1491, 0x4e51, 0x1491, 0x4e52, ++ 0x1491, 0x4e5a, 0xc000, 0x1491, 0x4e61, 0xc001, 0x8891, 0x0032, ++ 0x1091, 0x2691, 0xcc60, 0x1091, 0x2691, 0xcc62, 0xc000, 0xe42e, ++ 0xe41e, 0x14a3, 0xe42e, 0xa220, 0xe161, 0x0780, 0xd022, 0x002d, ++ 0xe184, 0x14aa, 0x4e91, 0xc001, 0x4e53, 0x4e54, 0x4e55, 0x4e56, ++ 0xc000, 0xe42e, 0xa220, 0xc001, 0x4e53, 0x4e56, 0xc000, 0xe42e, ++ 0xc001, 0x1457, 0xc000, 0xe005, 0x0780, 0x0554, 0xe093, 0x1581, ++ 0xc001, 0x4f56, 0x4e81, 0x4e81, 0x4e53, 0xc000, 0xe42e, 0xc001, ++ 0x1457, 0xe005, 0x0780, 0xc000, 0x0554, 0xc001, 0xe093, 0x1591, ++ 0x4f54, 0x1591, 0x4f55, 0x1556, 0xe045, 0xe017, 0xae07, 0x4f56, ++ 0x1555, 0xe045, 0xe017, 0xae05, 0x4f55, 0x1554, 0xe045, 0xe017, ++ 0xae03, 0x4f54, 0x1553, 0xe045, 0xe017, 0xae01, 0x4f53, 0x1456, ++ 0x2655, 0x2654, 0x2653, 0x4e5b, 0xc000, 0x1454, 0xa002, 0x0c50, ++ 0xc001, 0xf2aa, 0xe005, 0x05d0, 0xc000, 0x0554, 0xa003, 0xc001, ++ 0xe093, 0x1491, 0xe005, 0x0780, 0xc000, 0x0554, 0xc001, 0xe093, ++ 0x1591, 0xe045, 0xe017, 0xae07, 0x4f56, 0x1591, 0xe045, 0xe017, ++ 0xae03, 0x4f54, 0x1591, 0xe045, 0xe017, 0xae05, 0x4f55, 0x1557, ++ 0xe045, 0xe017, 0xae01, 0x4f53, 0x1456, 0x2655, 0x2654, 0x2653, ++ 0x4e5f, 0xc000, 0xe42e, 0xc000, 0x1455, 0xa002, 0x4e00, 0xe41e, ++ 0x15c6, 0xc001, 0xe005, 0x05d0, 0xe093, 0x1491, 0x4e60, 0xc000, ++ 0x1555, 0x4f00, 0xe41e, 0x15c6, 0xc001, 0xe005, 0x0780, 0xe093, ++ 0x1491, 0x0c60, 0xe016, 0xae02, 0x4e54, 0x1491, 0x0c60, 0xe016, ++ 0xae04, 0x4e55, 0x1455, 0x2654, 0x4e5f, 0xc000, 0xe42e, 0x1454, ++ 0xe41a, 0x10af, 0x1454, 0xe41a, 0x14b2, 0xe41e, 0x14c7, 0x1464, ++ 0xe09c, 0x1496, 0xce42, 0x1486, 0xce44, 0xca4a, 0xc001, 0x225b, ++ 0xc000, 0xcec4, 0xcf34, 0xca4c, 0x1526, 0xb7f6, 0xca4b, 0xe052, ++ 0x4e69, 0xc001, 0x225b, 0xc000, 0xcec2, 0xe42e, 0xc000, 0x1450, ++ 0x1551, 0x4e02, 0x4f03, 0xc001, 0x145e, 0xc000, 0xe40a, 0x156b, ++ 0xa102, 0xe40a, 0x15a1, 0xc001, 0xe161, 0x00e1, 0xe162, 0x05d0, ++ 0xa200, 0x4e57, 0xc000, 0x4e05, 0x4e01, 0x4e00, 0xc000, 0x1405, ++ 0xa002, 0x4e05, 0x0c81, 0xf106, 0xa200, 0x4e05, 0xc001, 0x1457, ++ 0xa002, 0x4e57, 0x8091, 0x0c59, 0xf724, 0xa200, 0xc001, 0x4e57, ++ 0xe161, 0x00e1, 0xf6ce, 0xc001, 0x1457, 0x4e92, 0xc000, 0x1401, ++ 0xa002, 0x4e01, 0x0c02, 0xf634, 0x4e01, 0xe41e, 0x15c4, 0xc000, ++ 0x1400, 0xa002, 0x4e00, 0x0c03, 0xe162, 0x05d0, 0xf584, 0xc000, ++ 0xe42e, 0xa200, 0x4e00, 0xe162, 0x05d0, 0x8200, 0xc001, 0x8159, ++ 0xe018, 0xaf02, 0xc70f, 0xc001, 0x3c59, 0xaf20, 0xc000, 0x1502, ++ 0xa103, 0xcc45, 0xe184, 0x15ba, 0x4e92, 0xa002, 0xe049, 0xc001, ++ 0x0d59, 0xc000, 0xb616, 0xe41e, 0x15c4, 0x1400, 0xa002, 0x4e00, ++ 0x0c03, 0xf624, 0xc000, 0xe42e, 0xa204, 0xf02e, 0xa206, 0x4e04, ++ 0x1400, 0xae0e, 0xe005, 0x0320, 0xae11, 0xe042, 0xe0c1, 0x0041, ++ 0xe042, 0xce20, 0xd111, 0x05d0, 0xd112, 0x002e, 0x8804, 0x0113, ++ 0xca28, 0xf7f8, 0xe42e, 0x1454, 0xf058, 0x1455, 0x4e00, 0xe41e, ++ 0x15c6, 0xe004, 0x05d0, 0x0454, 0xe092, 0x1491, 0xc001, 0x4e57, ++ 0xc000, 0xe42e, 0xe082, 0x4e4e, 0xc001, 0x1448, 0xf04a, 0x1046, ++ 0x2647, 0xf07e, 0xe0c0, 0x0041, 0xe005, 0x0470, 0xae11, 0xe042, ++ 0xc000, 0xe161, 0x03a4, 0xc001, 0x1769, 0xae15, 0xc000, 0xd022, ++ 0x0007, 0xe184, 0x1605, 0x4891, 0x4e91, 0xe042, 0x144e, 0xe092, ++ 0xe42e, 0xc000, 0xe082, 0x4e4e, 0x100b, 0x2602, 0xe406, 0x16b0, ++ 0xe0c0, 0x005a, 0xae02, 0xe000, 0x0048, 0xe092, 0x9e11, 0x4808, ++ 0x4e09, 0x1003, 0x2604, 0xe0c1, 0x005a, 0xae03, 0xe001, 0x0048, ++ 0xe093, 0x8091, 0x9f01, 0xe41e, 0x16c0, 0x1000, 0x2601, 0xce20, ++ 0xd111, 0x0700, 0xd112, 0x0080, 0xd113, 0x0003, 0xca29, 0xf7f9, ++ 0x104a, 0x264b, 0xc001, 0x1149, 0xc000, 0x274c, 0xae11, 0xe041, ++ 0x1003, 0x2604, 0xe000, 0x0100, 0xe046, 0xf164, 0x104a, 0x264b, ++ 0xc001, 0x1149, 0xc000, 0x274c, 0xae11, 0xe041, 0x1003, 0x2604, ++ 0x000b, 0x0602, 0xe046, 0xf084, 0x4e06, 0x100b, 0x2602, 0x0c06, ++ 0x4e05, 0x1406, 0xf2de, 0x1003, 0x2604, 0xce20, 0xd111, 0x0700, ++ 0x100b, 0x2602, 0xe005, 0x0100, 0xe046, 0xf044, 0xd112, 0x0080, ++ 0xf07e, 0x100b, 0x2602, 0xa006, 0xaf04, 0xae02, 0xce24, 0xd113, ++ 0x0002, 0xca28, 0xf7f8, 0x100b, 0x2602, 0xe005, 0x0100, 0xe046, ++ 0xf084, 0x1003, 0x2604, 0xe000, 0x0100, 0x4803, 0x4e04, 0xf2be, ++ 0x1003, 0x2604, 0x000b, 0x0602, 0x4803, 0x4e04, 0xf24e, 0x1405, ++ 0xf0da, 0x1103, 0x2704, 0xce21, 0xd111, 0x0700, 0x1405, 0xaf02, ++ 0xce24, 0xd113, 0x0002, 0xca28, 0xf7f8, 0x157d, 0xf04b, 0xa203, ++ 0xe0c3, 0x0074, 0x104a, 0x264b, 0x4803, 0x4e04, 0x100b, 0x2602, ++ 0x0c05, 0x4e02, 0x480b, 0x1000, 0x2601, 0x0405, 0x4800, 0x4e01, ++ 0xe40e, 0x160c, 0x100b, 0x2602, 0xe002, 0x0100, 0x4e02, 0x480b, ++ 0x1000, 0x2601, 0xe000, 0x0100, 0x4800, 0x4e01, 0xe40e, 0x160c, ++ 0x1003, 0x2604, 0xa006, 0xaf04, 0xae04, 0xe0c1, 0x005a, 0xae03, ++ 0xe001, 0x0048, 0xe093, 0x8091, 0x9f01, 0x144e, 0xe092, 0xe42e, ++ 0xe0c1, 0x0043, 0xa805, 0xe429, 0x157d, 0xe429, 0xa200, 0x4e4f, ++ 0xe0c0, 0x005a, 0xae02, 0xe000, 0x0048, 0xe092, 0x9e11, 0x4808, ++ 0x4e09, 0x1003, 0x2604, 0x1108, 0x2709, 0xe046, 0xf114, 0x1003, ++ 0x2604, 0x1108, 0x2709, 0xe046, 0xc001, 0x1149, 0xc000, 0x274c, ++ 0xae11, 0xe045, 0xe004, 0x0100, 0xe045, 0xe421, 0xf0ae, 0x1003, ++ 0x2604, 0x1108, 0x2709, 0xe045, 0xe004, 0x0100, 0xe045, 0xe421, ++ 0x144f, 0xf578, 0xe0c0, 0x005c, 0xe008, 0x8000, 0xf52a, 0xe0c0, ++ 0x005d, 0xe00a, 0x8000, 0xe0c2, 0x005d, 0xa202, 0xce00, 0x4e4f, ++ 0xf48e, 0x100b, 0x2602, 0xe161, 0x04e4, 0x4891, 0x4e91, 0x1407, ++ 0xae04, 0xe005, 0x0012, 0xae11, 0xe042, 0xe0c1, 0x0042, 0xe042, ++ 0xce20, 0xd111, 0x04e4, 0xd112, 0x0020, 0xd113, 0x0002, 0xca28, ++ 0xf7f8, 0xe42e, 0xe082, 0x4e4e, 0xa200, 0x4e07, 0xe0c0, 0x005a, ++ 0xae02, 0xe000, 0x0048, 0xe092, 0xe162, 0x03a4, 0xd022, 0x0007, ++ 0xe184, 0x1755, 0x9e11, 0x4808, 0x4e09, 0x9e09, 0x4803, 0x4e04, ++ 0xc001, 0x1448, 0xf04a, 0x1046, 0x2647, 0xf07e, 0xe0c0, 0x0041, ++ 0xe005, 0x0470, 0xae11, 0xe042, 0xc000, 0xc001, 0x8269, 0xc000, ++ 0x8107, 0xe019, 0xae15, 0xe042, 0x4800, 0x4e01, 0x1192, 0x2792, ++ 0xe045, 0xa007, 0xaf05, 0xae05, 0x4f02, 0x490b, 0x141a, 0xe418, ++ 0x1701, 0xe41e, 0x1609, 0xa202, 0x0407, 0x4e07, 0x144e, 0xe092, ++ 0xe42e, 0xe082, 0x4e4e, 0xd111, 0x0700, 0xc001, 0x1457, 0xc000, ++ 0xae02, 0xe005, 0x03a4, 0xe042, 0xe092, 0x1091, 0x2689, 0xce20, ++ 0x1440, 0xf15a, 0xa006, 0xaf04, 0xae02, 0xce24, 0xa204, 0xe0c1, ++ 0x0043, 0xa803, 0xb6d6, 0xce26, 0xca28, 0xf7f8, 0x1091, 0x2689, ++ 0x1540, 0xe042, 0x4891, 0x4e89, 0xa200, 0x4e40, 0x144e, 0xe092, ++ 0xe42e, 0x1440, 0xa806, 0xc001, 0x4e52, 0xc000, 0x1540, 0xe045, ++ 0x4f40, 0xe004, 0x0700, 0x1540, 0xaf03, 0xe042, 0xe092, 0xc001, ++ 0xe004, 0x0004, 0x1552, 0xe046, 0xae06, 0x4e50, 0xe005, 0xffff, ++ 0xae21, 0xe00b, 0xffff, 0x3550, 0x1491, 0xae20, 0x2691, 0xe052, ++ 0x4850, 0x4e51, 0xc000, 0xe42e, 0xc001, 0xa208, 0x1552, 0xe046, ++ 0xae06, 0x4e5c, 0xe005, 0xffff, 0xae21, 0xe00b, 0xffff, 0x355c, ++ 0xe004, 0x0700, 0xe092, 0x1050, 0x2651, 0xe052, 0x4891, 0x4e91, ++ 0x1452, 0xc000, 0x4e40, 0xe42e, 0xc001, 0xa200, 0x4e50, 0x4e51, ++ 0x4e52, 0xc000, 0xe42e, 0xc866, 0xa100, 0xae04, 0x4e45, 0xe42a, ++ 0xe41e, 0x0b32, 0xa200, 0xcc66, 0xe42e, 0xc866, 0xa100, 0xae04, ++ 0x4e45, 0xc864, 0xaf06, 0x0445, 0x4e45, 0xe42a, 0xa2fe, 0xbabe, ++ 0xc86e, 0xa180, 0xcc74, 0xe41e, 0x0b32, 0xa200, 0xcc66, 0xe42e, ++ 0xe0c0, 0x0040, 0xe0c1, 0x005b, 0xae1d, 0xe042, 0xce20, 0xd111, ++ 0x0000, 0xd112, 0x0800, 0xd113, 0x000b, 0xca28, 0xf7f8, 0xe42e, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0x0000, 0x0003, 0x0002, 0x001d, 0x0003, 0x001e, 0x0007, 0x0011, ++ 0x0004, 0x001f, 0x0008, 0x0012, 0x0011, 0x0025, 0x000d, 0x0008, ++ 0x0005, 0x0020, 0x0012, 0x0026, 0x0009, 0x0013, 0x000e, 0x0009, ++ 0x000a, 0x0014, 0x000f, 0x000a, 0x0010, 0x000b, 0x000b, 0x0002, ++ 0x0001, 0x0010, 0x0020, 0x0021, 0x0021, 0x0022, 0x0024, 0x0015, ++ 0x0022, 0x0023, 0x0025, 0x0016, 0x002c, 0x0027, 0x0028, 0x0004, ++ 0x0023, 0x0024, 0x002d, 0x0028, 0x0026, 0x0017, 0x0029, 0x0005, ++ 0x0027, 0x0018, 0x002a, 0x0006, 0x002b, 0x0007, 0x0013, 0x0001, ++ 0x0006, 0x0029, 0x0018, 0x002a, 0x0019, 0x002b, 0x0014, 0x0019, ++ 0x001a, 0x002c, 0x0015, 0x001a, 0x002e, 0x002e, 0x001c, 0x000c, ++ 0x001b, 0x002d, 0x002f, 0x002f, 0x0016, 0x001b, 0x001d, 0x000d, ++ 0x0017, 0x001c, 0x001e, 0x000e, 0x001f, 0x000f, 0x000c, 0x0000, ++ 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007, ++ 0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f, ++ 0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017, ++ 0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001d, 0x001e, ++ 0x001f, 0x0020, 0x0020, 0x0021, 0x0022, 0x0022, 0x0023, 0x0023, ++ 0x0024, 0x0024, 0x0025, 0x0025, 0x0025, 0x0026, 0x0026, 0x0026, ++ 0x0027, 0x0027, 0x0027, 0x0027, 0x0020, 0x0008, 0x0008, 0x0008, ++ 0x0030, 0x0008, 0x0010, 0x0008, 0x0030, 0x0008, 0x0010, 0x0008, ++ 0x0040, 0x0008, 0x0018, 0x0008, 0x0050, 0x0010, 0x0018, 0x0010, ++ 0x0060, 0x0018, 0x0020, 0x0018, 0x0080, 0x0018, 0x0040, 0x0018, ++ 0x00a0, 0x0020, 0x0060, 0x0020, 0x00c0, 0x0030, 0x0080, 0x0030, ++ 0x0100, 0x0040, 0x00c0, 0x0040, 0x0140, 0x0060, 0x0100, 0x0060, ++ 0x0180, 0x0070, 0x0140, 0x0070, 0x01c0, 0x0080, 0x0180, 0x0080, ++ 0x0200, 0x00a0, 0x01c0, 0x00a0, 0x0300, 0x0180, 0x0200, 0x0180, ++ 0x0400, 0x0200, 0x0240, 0x0200, 0x0080, 0x00a0, 0x00c0, 0x0100, ++ 0x0180, 0x0200, 0x0300, 0x0400, 0x0500, 0x0600, 0x0800, 0x0a00, ++ 0x0c00, 0x0023, 0x0022, 0x0021, 0x0020, 0x001f, 0x001f, 0x001e, ++ 0x001e, 0x001d, 0x001d, 0x001c, 0x001c, 0x001b, 0x001a, 0x0019, ++ 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0715, 0x4236, 0x0127, 0x5836, 0x0217, 0x5346, 0x0712, 0x3548, ++ 0x0215, 0x4736, 0x0574, 0x1236, 0x0127, 0x6584, 0x0753, 0x1428, ++ 0x7012, 0x3856, 0x1087, 0x6452, 0x1680, 0x2734, 0x1620, 0x8347, ++ 0x1687, 0x3205, 0x1602, 0x4587, 0x1054, 0x7683, 0x1680, 0x2475, ++ 0x1078, 0x3654, 0x1862, 0x0734, 0x0157, 0x4236, 0x2106, 0x8753, ++ 0x2107, 0x3658, 0x1270, 0x3856, 0x2104, 0x5673, 0x5014, 0x7623, ++ 0x1260, 0x4375, 0x0712, 0x5348, 0x1238, 0x7065, 0x0712, 0x3568, ++ 0x1230, 0x8674, 0x1203, 0x7864, 0x3172, 0x0586, 0x3127, 0x0564, ++ 0x0713, 0x5624, 0x1236, 0x5087, 0x7301, 0x2586, 0x3182, 0x7065, ++ 0x0154, 0x7638, 0x1260, 0x4853, 0x1204, 0x6538, 0x3102, 0x7645, ++ 0x4156, 0x0378, 0x5401, 0x7638, 0x6415, 0x0238, 0x1075, 0x6342, ++ 0x1326, 0x4087, 0x0517, 0x4632, 0x1205, 0x6378, 0x2057, 0x1463, ++ 0x0152, 0x7458, 0x5401, 0x6732, 0x5047, 0x1263, 0x1026, 0x5473, ++ 0x0751, 0x4236, 0x1026, 0x5783, 0x0186, 0x4351, 0x1680, 0x2347, ++ 0x1620, 0x8435, 0x1683, 0x7045, 0x1645, 0x0287, 0x1504, 0x7632, ++ 0x1642, 0x8307, 0x1076, 0x3845, 0x1683, 0x0247, 0x0721, 0x3584, ++ 0x1270, 0x3865, 0x2071, 0x3856, 0x7320, 0x1854, 0x7320, 0x1854, ++ 0x0751, 0x2348, 0x1072, 0x6358, 0x7032, 0x1854, 0x1730, 0x8256, ++ 0x1087, 0x2653, 0x1860, 0x2537, 0x1820, 0x3674, 0x1837, 0x2065, ++ 0x1820, 0x5367, 0x1807, 0x5264, 0x1863, 0x2705, 0x1837, 0x0526, ++ 0x1832, 0x6705, 0x0d0b, 0x0907, 0x0501, 0x0d0b, 0x0907, 0x0501, ++ 0x1a16, 0x120e, 0x0a02, 0x1a16, 0x120e, 0x0a02, 0x2721, 0x1b15, ++ 0x0f03, 0x342c, 0x241c, 0x1404, 0x4137, 0x2d23, 0x1905, 0x4e42, ++ 0x362a, 0x1e06, 0x5b4d, 0x3f31, 0x2307, 0x6858, 0x4838, 0x2808, ++ 0x7563, 0x513f, 0x2d09, 0x8f79, 0x634d, 0x370b, 0xa98f, 0x755b, ++ 0x410d, 0xc3a5, 0x8769, 0x4b0f, 0xc3a5, 0x8769, 0x4b0f, 0xc3a5, ++ 0x8769, 0x4b0f, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe40e, 0x0022, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, ++ 0xe470, 0xe190, 0xe40e, 0x0152, 0xe470, 0xe190, 0xe470, 0xe190, ++ 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, ++ 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, ++ 0xf202, 0x1307, 0xc001, 0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, ++ 0x0008, 0xe0c2, 0x0058, 0xa200, 0xe0c2, 0x005a, 0xa2fe, 0x4e71, ++ 0x4e72, 0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d, 0xce00, 0xf11e, ++ 0xe0c0, 0x005c, 0xe0c1, 0x0059, 0x4f70, 0xa203, 0x3570, 0xe052, ++ 0xf08a, 0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00, ++ 0xe41e, 0x0084, 0xe0c0, 0x005b, 0x0c72, 0xe418, 0x00b2, 0xe0c0, ++ 0x0059, 0xa114, 0xf18a, 0xa102, 0xf1da, 0xe0c0, 0x005a, 0x0c71, ++ 0xe418, 0x00ab, 0xe0c0, 0x0059, 0xae02, 0xe000, 0x0152, 0xc000, ++ 0xe67c, 0xc001, 0xe0c0, 0x005a, 0x4e71, 0xe0c0, 0x005b, 0x4e72, ++ 0xe40e, 0x0038, 0x1471, 0xe412, 0x010d, 0xa202, 0x4e73, 0xe40e, ++ 0x0061, 0xe41e, 0x00c6, 0xd101, 0x0001, 0xc71e, 0xa002, 0xa200, ++ 0xe0c2, 0x0083, 0xa202, 0xe0c2, 0x0093, 0xc71e, 0xa002, 0xd071, ++ 0x002a, 0xe181, 0xe40e, 0x0061, 0xa200, 0xe0c2, 0x0059, 0xe0c2, ++ 0x0058, 0xe0c2, 0x0008, 0xe0c0, 0x0059, 0xf7ea, 0xa11e, 0xf168, ++ 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058, 0xe004, 0xf202, 0xae20, ++ 0xe005, 0x1307, 0xe056, 0xe0c2, 0x0070, 0xa200, 0xe0c2, 0x0059, ++ 0xe0c2, 0x0058, 0xe0c2, 0x0008, 0xf67e, 0xa202, 0xe0c2, 0x0008, ++ 0xe0c2, 0x0058, 0xe42e, 0x1471, 0xe424, 0xe41e, 0x010d, 0xe41e, ++ 0x00c6, 0xe42e, 0xe0c0, 0x0040, 0xe0c1, 0x005b, 0xae1d, 0xe042, ++ 0xe000, 0x1000, 0xce20, 0xd111, 0x0800, 0xd112, 0x1000, 0xd113, ++ 0x000b, 0xca28, 0xf7f8, 0xe41e, 0x17e0, 0xe42e, 0xe0c0, 0x0041, ++ 0xe005, 0x0000, 0xae11, 0xe042, 0xe0c1, 0x005a, 0xae19, 0xe042, ++ 0xce20, 0xd111, 0x0000, 0xd112, 0x0800, 0xd113, 0x0003, 0xca28, ++ 0xf7f8, 0xe0c0, 0x0041, 0xe005, 0x0080, 0xae11, 0xe042, 0xe0c1, ++ 0x005a, 0xae15, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0200, ++ 0xd113, 0x0013, 0xca28, 0xf7f8, 0xe161, 0x00f4, 0x8891, 0x0032, ++ 0x8891, 0x0033, 0x8891, 0x0034, 0x8891, 0x0035, 0x8891, 0x0036, ++ 0x8891, 0x0037, 0x1091, 0x2691, 0xcc60, 0x1091, 0x2691, 0xcc62, ++ 0x1091, 0x2691, 0xcc74, 0x1091, 0x2691, 0xcf68, 0x1091, 0x2691, ++ 0xcf64, 0x1091, 0x2691, 0xcf60, 0xe42e, 0xe161, 0x00f4, 0x8991, ++ 0x0032, 0x8991, 0x0033, 0x8991, 0x0034, 0x8991, 0x0035, 0x8991, ++ 0x0036, 0x8991, 0x0037, 0xc860, 0x4891, 0x4e91, 0xc862, 0x4891, ++ 0x4e91, 0xc874, 0x4891, 0x4e91, 0xcb68, 0x4891, 0x4e91, 0xcb64, ++ 0x4891, 0x4e91, 0xcb60, 0x4891, 0x4e91, 0xe0c0, 0x0041, 0xe005, ++ 0x0000, 0xae11, 0xe042, 0x1571, 0xae19, 0xe042, 0xce20, 0xd111, ++ 0x0000, 0xd112, 0x0800, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe0c0, ++ 0x0041, 0xe005, 0x0080, 0xae11, 0xe042, 0x1571, 0xae15, 0xe042, ++ 0xce20, 0xd111, 0x0000, 0xd112, 0x0200, 0xd113, 0x0012, 0xca28, ++ 0xf7f8, 0xe42e, 0xe40e, 0x046a, 0xe40e, 0x0172, 0xe40e, 0x0176, ++ 0xe40e, 0x017a, 0xe40e, 0x017e, 0xe40e, 0x0061, 0xe40e, 0x0061, ++ 0xe40e, 0x0061, 0xe40e, 0x0061, 0xe40e, 0x0061, 0xe40e, 0x0061, ++ 0xe40e, 0x0061, 0xe40e, 0x0061, 0xe40e, 0x0061, 0xe40e, 0x0061, ++ 0xe40e, 0x0061, 0xe41e, 0x0182, 0xe40e, 0x0061, 0xe41e, 0x01e7, ++ 0xe40e, 0x0061, 0xe41e, 0x02ae, 0xe40e, 0x0061, 0xe41e, 0x029c, ++ 0xe40e, 0x0061, 0xa200, 0xc001, 0x4e06, 0xc000, 0xc001, 0xe0c0, ++ 0x0063, 0x4810, 0x4e11, 0xe0c0, 0x0064, 0x4812, 0x4e13, 0xe0c0, ++ 0x0065, 0x4814, 0x4e15, 0xe0c0, 0x0047, 0x4e16, 0xc000, 0xe41e, ++ 0x01ed, 0xe41e, 0x03ff, 0xa200, 0xc001, 0x4e1a, 0xc000, 0xe0c0, ++ 0x0062, 0xaf04, 0xc001, 0x4619, 0xaf02, 0x461e, 0xc000, 0xe41e, ++ 0x059c, 0xe41e, 0x043b, 0xc001, 0x1419, 0xc000, 0xf08a, 0xe0c0, ++ 0x0069, 0xa806, 0xae06, 0xf03a, 0xe092, 0x9201, 0xe41e, 0x01f8, ++ 0xe41e, 0x0266, 0xe0c0, 0x0062, 0xaf0c, 0x4666, 0x1004, 0x2605, ++ 0xe008, 0x03ff, 0xae14, 0x1102, 0x2703, 0xe009, 0x03ff, 0xe056, ++ 0xe0c2, 0x0071, 0x100a, 0x260b, 0xe008, 0xffff, 0xe0c2, 0x0072, ++ 0x1453, 0xaf0a, 0xa80e, 0xe0c2, 0x0073, 0x1453, 0xaf06, 0xa806, ++ 0xe0c2, 0x0074, 0xc001, 0x4e0d, 0xc000, 0xa202, 0xe0c2, 0x0070, ++ 0xc001, 0x1419, 0xc000, 0xf038, 0xe41e, 0x0568, 0xe42e, 0xa202, ++ 0xe42e, 0xa200, 0xe0c2, 0x0070, 0xe42e, 0xa200, 0xc401, 0xe188, ++ 0x07ff, 0x4e91, 0xc001, 0x4e1f, 0xc000, 0xd03a, 0x0000, 0xe42e, ++ 0xe41e, 0x03fa, 0xe41e, 0x025e, 0xf068, 0xe004, 0x00ff, 0xae20, ++ 0xe00a, 0xffff, 0x4800, 0x4e01, 0xba4e, 0xc001, 0x4e18, 0xc000, ++ 0xe002, 0x0085, 0xf08a, 0xc001, 0x1418, 0xc000, 0xe002, 0x00c5, ++ 0xe408, 0x0251, 0xe41e, 0x0253, 0xa108, 0xe408, 0x0251, 0xba5e, ++ 0x4e0c, 0xba5e, 0x4e0d, 0xe41e, 0x0253, 0x4802, 0x4e03, 0xe41e, ++ 0x0253, 0x4804, 0x4e05, 0xc001, 0x1418, 0xc000, 0xe002, 0x0085, ++ 0xf26a, 0xe41e, 0x0253, 0xc001, 0x4e17, 0xc000, 0xa118, 0xf138, ++ 0xba4e, 0xe092, 0xe41e, 0x025e, 0xe083, 0xae31, 0xe056, 0x4806, ++ 0x4e07, 0xe41e, 0x0253, 0x4808, 0x4e09, 0xe41e, 0x0253, 0x480a, ++ 0x4e0b, 0xf0de, 0xc001, 0x1417, 0xf0aa, 0xa110, 0xf030, 0x5617, ++ 0xf06e, 0xba4e, 0x1417, 0xa110, 0x4e17, 0xf75e, 0xc000, 0xa202, ++ 0xe42e, 0xa200, 0xe42e, 0xba4e, 0xba4f, 0xae11, 0xe056, 0xba4f, ++ 0xae21, 0xe056, 0xba4f, 0xae31, 0xe056, 0xe42e, 0xba4e, 0xba4f, ++ 0xae11, 0xe056, 0xba4f, 0xae21, 0xe056, 0xe42e, 0xa200, 0x140c, ++ 0xaf02, 0xa802, 0xae04, 0xa904, 0x150d, 0xaf09, 0xa80f, 0xb432, ++ 0x4e53, 0xa204, 0x8a53, 0x0000, 0x1553, 0xa80d, 0xb45a, 0xb452, ++ 0x1553, 0xa10d, 0xb436, 0xae0a, 0x2653, 0x4e53, 0x140d, 0xaf08, ++ 0xa80e, 0xb630, 0xae06, 0x2653, 0x4e53, 0x8a53, 0x0000, 0xe004, ++ 0x1235, 0xae20, 0xe00a, 0x4067, 0xf06c, 0xe004, 0x1243, 0xae20, ++ 0xe00a, 0x5067, 0x4854, 0x4e55, 0x1463, 0x1553, 0xaf07, 0xa807, ++ 0xe046, 0x4e63, 0x4e3a, 0xe42e, 0xe0c0, 0x0042, 0xce20, 0xd111, ++ 0x0140, 0xd112, 0x0070, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe0c0, ++ 0x0060, 0x4e64, 0xe0c0, 0x0061, 0x4e50, 0xe42e, 0xa200, 0xcc44, ++ 0xa2fe, 0xe0c2, 0x0077, 0xc001, 0x1473, 0xf04a, 0xa200, 0x4e1f, ++ 0x4e73, 0xc000, 0xe0c0, 0x0045, 0xa804, 0xf17a, 0xc001, 0x140d, ++ 0xc000, 0xf0ea, 0xa102, 0xc001, 0x4e0d, 0xc000, 0xa003, 0x493b, ++ 0x4f62, 0x1456, 0xaf18, 0xe0c2, 0x0071, 0xe40e, 0x0367, 0xa2fe, ++ 0xe0c2, 0x0071, 0xe40e, 0x0367, 0xc001, 0x1419, 0xc000, 0xf398, ++ 0xe0c0, 0x0045, 0xf36a, 0xe41e, 0x0b95, 0xf1aa, 0x1453, 0xaf06, ++ 0xa806, 0x113b, 0x2762, 0xa003, 0xe045, 0x1000, 0x2601, 0xe046, ++ 0xf0a4, 0xa003, 0x493b, 0x4f62, 0x1456, 0xaf18, 0xe0c2, 0x0071, ++ 0xe40e, 0x0367, 0xa2fe, 0xe0c2, 0x0071, 0xe40e, 0x0367, 0xe41e, ++ 0x057b, 0xf17a, 0xc001, 0x140d, 0xc000, 0xf0ea, 0xa102, 0xc001, ++ 0x4e0d, 0xc000, 0xa003, 0x493b, 0x4f62, 0x1456, 0xaf18, 0xe0c2, ++ 0x0071, 0xe40e, 0x0367, 0xa2fe, 0xe0c2, 0x0071, 0xe40e, 0x0367, ++ 0xa200, 0xcc4a, 0xcc4c, 0xc001, 0x1419, 0xc000, 0xf10a, 0x103b, ++ 0x2662, 0xf03a, 0xe41e, 0x040f, 0xe0c0, 0x006a, 0xe0c1, 0x006c, ++ 0xa807, 0xe042, 0xc001, 0x481b, 0x4e1c, 0xc000, 0xd180, 0x0002, ++ 0xd147, 0x0004, 0xd03b, 0x0002, 0xd008, 0x0000, 0xe16a, 0xa200, ++ 0xcf06, 0xe0c2, 0x0286, 0xc001, 0x1419, 0xc000, 0xf048, 0xe0c0, ++ 0x0045, 0xf038, 0xe41e, 0x037e, 0xe41e, 0x039b, 0xc001, 0x1419, ++ 0xf01a, 0xc000, 0x103b, 0x2662, 0xa002, 0x483b, 0x4e62, 0x1463, ++ 0xa114, 0xf03a, 0xa016, 0x4e63, 0xc001, 0x1419, 0xc000, 0xf07a, ++ 0x1663, 0xa102, 0xf042, 0xa2fa, 0xe0c2, 0x0071, 0x143a, 0xa002, ++ 0x4e3a, 0xe0c2, 0x0070, 0x1414, 0xe0c2, 0x0073, 0xa200, 0xe0c2, ++ 0x0072, 0xc84a, 0xc84d, 0xae20, 0xe056, 0xe0c2, 0x0046, 0xc001, ++ 0x1419, 0xc000, 0xf05a, 0xa202, 0xe0c2, 0x0076, 0xe42e, 0x1466, ++ 0x1563, 0xb622, 0xe40a, 0x02ae, 0xc001, 0x1419, 0xc000, 0xf038, ++ 0xe41e, 0x0568, 0xa202, 0xe0c2, 0x0076, 0xe42e, 0xe005, 0x00ff, ++ 0xae21, 0xe00b, 0xffff, 0x1000, 0x2601, 0xe045, 0xe42b, 0x113b, ++ 0x2762, 0xe046, 0xe420, 0xe41e, 0x03fa, 0xba3e, 0xe008, 0x00ff, ++ 0xe002, 0x00c5, 0xf03a, 0xba4e, 0xf79e, 0xe41e, 0x01f8, 0xa200, ++ 0x493b, 0x4f62, 0xe42e, 0xe41e, 0x0b95, 0xe408, 0x03f4, 0xe41e, ++ 0x0b74, 0xe41e, 0x0ba6, 0x1414, 0xf188, 0xc001, 0x141f, 0xc000, ++ 0xf148, 0xa202, 0xc001, 0x4e1f, 0xc000, 0xd101, 0x0001, 0xc71e, ++ 0xa002, 0xa200, 0xe0c2, 0x0083, 0xa202, 0xe0c2, 0x0093, 0xc71e, ++ 0xa002, 0xa200, 0xe0c2, 0x0286, 0xc001, 0x1419, 0xc000, 0xf038, ++ 0xe41e, 0x0568, 0xe41e, 0x0b82, 0x1010, 0x2611, 0xa102, 0xf2d6, ++ 0xe41e, 0x0bb9, 0xc001, 0x1419, 0xc000, 0xf01a, 0xe41e, 0x0c1f, ++ 0xe41e, 0x0c4d, 0xe41e, 0x05b1, 0x1514, 0xa101, 0xe41b, 0x1321, ++ 0x1514, 0xa107, 0xe41b, 0x1321, 0x1514, 0xa103, 0xe41b, 0x134c, ++ 0x1514, 0xa105, 0xe41b, 0x134c, 0xe41e, 0x087d, 0xe41e, 0x08d4, ++ 0xe41e, 0x0920, 0xe41e, 0x094d, 0x1417, 0xaf16, 0xa806, 0xe418, ++ 0x074f, 0xe41e, 0x0c4c, 0xf01e, 0xe41e, 0x06be, 0xe41e, 0x0b85, ++ 0xa202, 0xe42e, 0xc864, 0xa80e, 0x4e68, 0x5668, 0xe42e, 0xe0c0, ++ 0x0040, 0xe005, 0x9800, 0xae03, 0xe042, 0xce20, 0xd111, 0x0540, ++ 0xd112, 0x0100, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e, 0xa200, ++ 0xc001, 0x4e1a, 0x480f, 0x4e03, 0x4e0e, 0x141e, 0xf05a, 0xe0c0, ++ 0x006b, 0x4800, 0x4e01, 0x1000, 0x2601, 0xe0c1, 0x006a, 0xe042, ++ 0xe0c1, 0x005a, 0xae03, 0xe001, 0x0049, 0xe093, 0x9f01, 0xe004, ++ 0xffff, 0x4e02, 0xc000, 0xe41e, 0x045a, 0xe41e, 0x04b1, 0xe12c, ++ 0xe41e, 0x046d, 0xe128, 0xe0c0, 0x006c, 0xa806, 0xae06, 0xf03a, ++ 0xe092, 0x9201, 0xe42e, 0xc001, 0xa200, 0x4e09, 0x4e0a, 0x4e0b, ++ 0x4e0c, 0x4e0d, 0x480f, 0x4e03, 0xe0c0, 0x0060, 0x4800, 0x4e01, ++ 0xe0c0, 0x0061, 0xae04, 0x480e, 0x4e02, 0xc000, 0xe41e, 0x045a, ++ 0xe41e, 0x04b1, 0xe12c, 0xd071, 0x002a, 0xe181, 0xe41e, 0x046d, ++ 0xe128, 0xe42e, 0xe12c, 0xd030, 0x0000, 0xd032, 0x0000, 0xd033, ++ 0x0000, 0xd034, 0x0000, 0xd035, 0x007f, 0xd036, 0x0000, 0xd037, ++ 0x0000, 0xe42e, 0xe41e, 0x046d, 0xe470, 0xd111, 0x0000, 0xc001, ++ 0xe082, 0x4e04, 0xe0c0, 0x005a, 0xae02, 0xe000, 0x0048, 0xe092, ++ 0xe41e, 0x04c1, 0x1000, 0x2601, 0x130f, 0x2703, 0xae11, 0xe042, ++ 0xce20, 0xd112, 0x0100, 0xa226, 0xe0c1, 0x0043, 0xa803, 0xf029, ++ 0xa22e, 0xce26, 0xca28, 0xf7f8, 0x1419, 0xf0d8, 0xe41e, 0x0503, ++ 0x1506, 0xa103, 0xf1b1, 0xe004, 0x1000, 0xf035, 0x1407, 0xae06, ++ 0xe41e, 0x0575, 0x120f, 0x2603, 0xe000, 0x0002, 0x480f, 0x4e03, ++ 0x130e, 0x2702, 0xe046, 0xf034, 0x480f, 0x4e03, 0x1000, 0x2601, ++ 0x130f, 0x2703, 0xae11, 0xe042, 0x9f01, 0x1404, 0xe092, 0xc000, ++ 0xe42e, 0xc001, 0x1000, 0x2601, 0x130f, 0x2703, 0xae11, 0xe042, ++ 0xc000, 0xe0c1, 0x005a, 0xae03, 0xe001, 0x0048, 0xe093, 0x9f01, ++ 0xe42e, 0xe0c1, 0x0043, 0xa805, 0xe429, 0xa200, 0x4e05, 0x1419, ++ 0xf038, 0x1406, 0xf258, 0x1000, 0x2601, 0x130f, 0x2703, 0xae11, ++ 0xe042, 0x8091, 0x9e89, 0xe045, 0xf053, 0x120e, 0x2602, 0xae10, ++ 0xe041, 0xe003, 0x0200, 0xe423, 0x1419, 0xf06a, 0x141a, 0xf048, ++ 0xa202, 0x4e1a, 0xe42e, 0x1419, 0xf0e8, 0xe0c0, 0x0059, 0xe002, ++ 0x0003, 0xf098, 0xe0c0, 0x0045, 0xa802, 0xf05a, 0x1406, 0xa002, ++ 0x4e06, 0xe42e, 0x1405, 0xf588, 0xe0c0, 0x005c, 0xe008, 0x4000, ++ 0xf53a, 0xe0c0, 0x005d, 0xe00a, 0x4000, 0xe0c2, 0x005d, 0xa202, ++ 0xce00, 0x4e05, 0xf49e, 0x1406, 0xe42a, 0xe085, 0x4f08, 0xa102, ++ 0xf238, 0x8091, 0x9e09, 0x1100, 0x2701, 0xe046, 0xe008, 0x01ff, ++ 0x4e07, 0xaf04, 0xe000, 0x0000, 0xe094, 0x1407, 0xe005, 0x0200, ++ 0xe045, 0xa121, 0xf0e3, 0xe41e, 0x0539, 0xe005, 0x0200, 0x0d07, ++ 0xe045, 0xe084, 0xcc7a, 0xa200, 0xf12b, 0xcc7c, 0xa109, 0xf7de, ++ 0xe41e, 0x0539, 0xf03e, 0xe162, 0x0000, 0xe084, 0xcc7a, 0xa200, ++ 0xe005, 0x0000, 0xcc7c, 0xcc7d, 0xcc7c, 0xcc7c, 0x1408, 0xe094, ++ 0xe42e, 0xa806, 0xe42a, 0xa102, 0xf12a, 0xa102, 0xf1da, 0xe084, ++ 0xcc78, 0xcc7a, 0xcc7e, 0xc87c, 0xe005, 0xffff, 0xae21, 0xe00b, ++ 0xff00, 0xe052, 0xcc7c, 0x8092, 0xa202, 0xe42e, 0xe084, 0xcc78, ++ 0xcc7a, 0xcc7e, 0xc87c, 0xe005, 0xff00, 0xae21, 0xe052, 0xcc7c, ++ 0x8092, 0xa206, 0xe42e, 0xe084, 0xcc78, 0xcc7a, 0xcc7e, 0xc87c, ++ 0xe005, 0xffff, 0xae21, 0xe052, 0xcc7c, 0x8092, 0xa204, 0xe42e, ++ 0xc874, 0xc001, 0x1109, 0x270a, 0xe041, 0x4909, 0x4f0a, 0xa201, ++ 0xcc75, 0xe41e, 0x0589, 0xc000, 0xe42e, 0x110b, 0x270c, 0xe041, ++ 0x490b, 0x4f0c, 0xe42e, 0xc001, 0x1406, 0xc000, 0xe42a, 0xc001, ++ 0x1009, 0x260a, 0x110b, 0x270c, 0xa002, 0xe046, 0xb60c, 0xc000, ++ 0xe42e, 0xe004, 0x4000, 0xae20, 0x1109, 0x270a, 0xe045, 0xe425, ++ 0x110b, 0x270c, 0xe045, 0xe425, 0x490b, 0x4f0c, 0x1109, 0x270a, ++ 0xe045, 0x4909, 0x4f0a, 0xe42e, 0xe004, 0x0080, 0xe0c2, 0x0094, ++ 0xc001, 0x1416, 0xf04a, 0x1012, 0x2613, 0xf08e, 0xc000, 0xe0c0, ++ 0x0041, 0xe005, 0x0320, 0xae11, 0xe042, 0xc000, 0xe0c2, 0x0089, ++ 0xe42e, 0xe41e, 0x059c, 0xa200, 0xe0c2, 0x00a1, 0xe0c0, 0x0044, ++ 0x4651, 0x1451, 0xe0c2, 0x0219, 0x1450, 0xe0c2, 0x009b, 0xe0c2, ++ 0x009f, 0xe0c2, 0x018b, 0xe0c2, 0x0209, 0xe0c2, 0x020a, 0xa200, ++ 0xe0c2, 0x0100, 0x1416, 0xae20, 0x2615, 0xae08, 0xe0c2, 0x0084, ++ 0xa200, 0xae02, 0xae18, 0x1517, 0xaf15, 0xa803, 0xe056, 0xae02, ++ 0x1517, 0xaf11, 0xa803, 0xe056, 0xae02, 0x1519, 0xaf15, 0xa803, ++ 0xe056, 0xae0a, 0x1519, 0xaf0b, 0xa83f, 0xe056, 0xae02, 0x2651, ++ 0xae04, 0x1514, 0xa807, 0xe056, 0xae10, 0xa906, 0xe0c2, 0x0080, ++ 0xa200, 0xa201, 0xe0c0, 0x0060, 0xe049, 0xaf09, 0xa803, 0xa81e, ++ 0xb616, 0x4e59, 0x1417, 0xaf14, 0xa802, 0xe055, 0x4f58, 0x140c, ++ 0xaf06, 0xa802, 0x1517, 0xaf11, 0xa803, 0xe056, 0x4e57, 0xa200, ++ 0x150c, 0xaf07, 0xa803, 0xe056, 0xae02, 0x1517, 0xaf11, 0xa803, ++ 0xe056, 0xae08, 0x2659, 0xe0c2, 0x00e7, 0xa200, 0xe0c0, 0x0060, ++ 0xe008, 0x001f, 0xae0c, 0x1557, 0xae03, 0xe056, 0xe0c2, 0x00fa, ++ 0xa200, 0x150e, 0xaf05, 0xa803, 0xe056, 0xae04, 0xa904, 0xae02, ++ 0x2651, 0xae20, 0x2650, 0xe0c2, 0x0282, 0x1415, 0xae20, 0x2616, ++ 0xae08, 0xe0c2, 0x0283, 0x140f, 0xa87e, 0xae10, 0x150f, 0xaf0d, ++ 0xa87f, 0xe056, 0xae1c, 0x150e, 0xaf1b, 0xa803, 0xe056, 0xae02, ++ 0x150f, 0xaf1b, 0xa803, 0xe056, 0xae02, 0x150f, 0xaf19, 0xa803, ++ 0xe056, 0xe0c2, 0x0287, 0x1415, 0xae0c, 0x2616, 0xe0c2, 0x0183, ++ 0xa202, 0xe0c2, 0x018d, 0xa200, 0x150c, 0xaf07, 0xa803, 0xe056, ++ 0xae02, 0x1517, 0xaf11, 0xa803, 0xe056, 0xae02, 0x2657, 0xae06, ++ 0xe0c2, 0x0182, 0x1419, 0xaf0a, 0xa83e, 0xe0c2, 0x019f, 0xa202, ++ 0xae3e, 0xa906, 0xe0c2, 0x00ec, 0xa200, 0xe0c2, 0x0102, 0xa202, ++ 0xe0c2, 0x0102, 0xa204, 0xe0c2, 0x0102, 0xc001, 0x1416, 0xf04a, ++ 0x1014, 0x2615, 0xf08e, 0xc000, 0xe0c0, 0x0041, 0xe005, 0x0338, ++ 0xae11, 0xe042, 0xc000, 0xe0c2, 0x01a8, 0xe41e, 0x06cb, 0x1414, ++ 0xa102, 0xe41a, 0x06fa, 0x1414, 0xa104, 0xe41a, 0x06fa, 0x1458, ++ 0xe418, 0x071b, 0xa200, 0x4e5a, 0xa200, 0x4e5c, 0xa200, 0xe166, ++ 0x0584, 0xc715, 0x4e96, 0xe166, 0x05be, 0x4e96, 0x1414, 0xa102, ++ 0xf19a, 0xe004, 0x0f0f, 0xae20, 0xe00a, 0x0f0f, 0xe0c2, 0x01a0, ++ 0xe0c2, 0x01a1, 0xe0c2, 0x01a2, 0xe0c2, 0x01a3, 0xe004, 0x3333, ++ 0xe0c2, 0x01a4, 0xe0c2, 0x01a5, 0xe0c2, 0x01a6, 0xe0c2, 0x01a7, ++ 0xe42e, 0xe004, 0x059a, 0x4e29, 0x4e2a, 0xe42e, 0x1456, 0xaf18, ++ 0xa81e, 0x1553, 0xaf07, 0xa807, 0xf04b, 0x1456, 0xaf10, 0xa81e, ++ 0xe0c2, 0x0071, 0xe42e, 0x1454, 0xaf18, 0xa81e, 0x1514, 0xa101, ++ 0xf10b, 0x1514, 0xa103, 0xf0db, 0xa201, 0x1517, 0xaf17, 0xa807, ++ 0xb633, 0x2b58, 0x1455, 0xaf18, 0xa81e, 0xf039, 0x1454, 0xa81e, ++ 0xe0c2, 0x0077, 0xe41e, 0x0a2a, 0xe000, 0x0140, 0xe092, 0x1091, ++ 0x2691, 0xe0c2, 0x009c, 0xe0c2, 0x0188, 0x1091, 0x2691, 0xe0c2, ++ 0x009d, 0xe0c2, 0x0189, 0x1091, 0x2691, 0xe0c2, 0x009e, 0xe0c2, ++ 0x018a, 0xe42e, 0xe162, 0x02c0, 0x1454, 0xaf10, 0xa81e, 0xe41e, ++ 0x0a2a, 0xe000, 0x0140, 0xe092, 0xd022, 0x0002, 0xe184, 0x070a, ++ 0x1091, 0x2691, 0x9f12, 0x1454, 0xaf18, 0xa81e, 0xe41e, 0x0a2a, ++ 0xe000, 0x0140, 0xe092, 0xd022, 0x0002, 0xe184, 0x0719, 0x1091, ++ 0x2691, 0x9f12, 0xe42e, 0xe0c0, 0x0060, 0xaf08, 0xa802, 0xf06a, ++ 0xe0c0, 0x0067, 0xe0c2, 0x00ff, 0xf04e, 0x1450, 0xe0c2, 0x00ff, ++ 0x1455, 0xaf18, 0xa81e, 0xa201, 0x1517, 0xaf17, 0xa807, 0xb633, ++ 0x2b58, 0xf0cb, 0x1454, 0xa81e, 0x1514, 0xa105, 0xf07b, 0x1514, ++ 0xa107, 0xf04b, 0x1454, 0xaf08, 0xa81e, 0xe41e, 0x0a2a, 0xe000, ++ 0x0140, 0xe092, 0x1091, 0x2691, 0xe0c2, 0x00fc, 0x1091, 0x2691, ++ 0xe0c2, 0x00fd, 0x1091, 0x2691, 0xe0c2, 0x00fe, 0xe42e, 0x1450, ++ 0xe0c2, 0x0303, 0xe0c2, 0x0307, 0x1004, 0x2605, 0xe008, 0x07ff, ++ 0xae16, 0x1102, 0x2703, 0xe009, 0x07ff, 0xe056, 0xe0c2, 0x0308, ++ 0x8a59, 0x0000, 0xf0dd, 0x1451, 0xae02, 0x1517, 0xaf17, 0xa803, ++ 0xe056, 0xae02, 0x1517, 0xaf19, 0xa803, 0xe056, 0xf07e, 0x1451, ++ 0xae04, 0x1517, 0xaf17, 0xa807, 0xe056, 0xe0c2, 0x0309, 0x1455, ++ 0xaf18, 0xa81e, 0x1514, 0xa105, 0xf09b, 0x1514, 0xa107, 0xf06b, ++ 0x1558, 0xf049, 0x1454, 0xaf18, 0xa81e, 0xe41e, 0x0a2a, 0xe000, ++ 0x0140, 0xe092, 0x1091, 0x2691, 0xe0c2, 0x0300, 0x1091, 0x2691, ++ 0xe0c2, 0x0301, 0x1091, 0x2691, 0xe0c2, 0x0302, 0x1454, 0xaf08, ++ 0xa81e, 0x1514, 0xa101, 0xf06b, 0x1514, 0xa103, 0xf03b, 0x1454, ++ 0xa81e, 0xe41e, 0x0a2a, 0xe000, 0x0140, 0xe092, 0x1091, 0x2691, ++ 0xe0c2, 0x0304, 0x1091, 0x2691, 0xe0c2, 0x0305, 0x1091, 0x2691, ++ 0xe0c2, 0x0306, 0xa202, 0xe0c2, 0x030a, 0xe0c0, 0x030b, 0xf7ea, ++ 0xe42e, 0x1442, 0xe418, 0x0a1d, 0xa202, 0x1549, 0xa17f, 0xb616, ++ 0x4e5b, 0x145b, 0xe418, 0x0968, 0x1440, 0xae20, 0x2641, 0xe0c2, ++ 0x0284, 0x145c, 0xae04, 0x265b, 0xe0c2, 0x0280, 0xa202, 0x1542, ++ 0xb616, 0x4e5d, 0xa103, 0xb616, 0x4e5e, 0xa103, 0xb616, 0x4e5f, ++ 0x4e60, 0xa103, 0xb616, 0x4e61, 0x1457, 0x2260, 0x4e60, 0x1457, ++ 0xe016, 0x225f, 0x4e5f, 0x1457, 0x2658, 0x2261, 0x4e61, 0xe41e, ++ 0x0a07, 0x1460, 0xe418, 0x09dd, 0xe41e, 0x09c5, 0x145a, 0xe0c2, ++ 0x0102, 0xe0c2, 0x0101, 0xe167, 0x058a, 0x1097, 0x2697, 0xe049, ++ 0xe009, 0x003f, 0xe0c3, 0x010a, 0xaf0c, 0xe0c2, 0x010b, 0xe166, ++ 0x0588, 0x1096, 0x2696, 0xe0c2, 0x0082, 0x1097, 0x2697, 0xe0c2, ++ 0x00ed, 0x1458, 0x225f, 0x2661, 0xae02, 0x155c, 0x235d, 0xe056, ++ 0xae02, 0x2660, 0xae02, 0x265b, 0xae04, 0x265f, 0xae04, 0x265e, ++ 0xae02, 0x265d, 0xae02, 0xe0c2, 0x0083, 0xa202, 0xe0c2, 0x0093, ++ 0xe42e, 0xe41e, 0x0a23, 0xe166, 0x0586, 0x1096, 0x2696, 0x4896, ++ 0x4e96, 0xe167, 0x058a, 0x1097, 0x2697, 0x4897, 0x4e97, 0xa202, ++ 0x1549, 0xa17f, 0xb616, 0x4e5b, 0x1445, 0xae02, 0x2646, 0xae18, ++ 0x155b, 0xe017, 0xae15, 0xe056, 0x2645, 0xe166, 0x0586, 0x4896, ++ 0x4e96, 0xe166, 0x056c, 0xd022, 0x0005, 0xa200, 0xe184, 0x0849, ++ 0xae04, 0x2696, 0xae0c, 0x2649, 0xe167, 0x058a, 0x4897, 0x4e97, ++ 0x145b, 0x4e5c, 0xe166, 0x05be, 0xe167, 0x0594, 0x1487, 0x4e86, ++ 0xe166, 0x0593, 0xe167, 0x0596, 0xd022, 0x0005, 0xe184, 0x0861, ++ 0x148e, 0x4e8f, 0xe166, 0x058e, 0x1440, 0xae0c, 0x2641, 0x4e96, ++ 0x8a17, 0x0008, 0xe42c, 0x1523, 0xe09f, 0xa200, 0x1587, 0xae21, ++ 0xe056, 0xe167, 0x022d, 0x1597, 0xae31, 0xe056, 0x1587, 0xae11, ++ 0xe056, 0x2649, 0x4896, 0x4e96, 0xe42e, 0xe41e, 0x0a1d, 0x145c, ++ 0xae04, 0xe0c2, 0x0280, 0xa202, 0x4e5d, 0xa202, 0x1542, 0xa103, ++ 0xb616, 0x4e5e, 0xa103, 0xb616, 0x4e5f, 0x4e60, 0xa103, 0xb616, ++ 0x4e61, 0x1457, 0x2260, 0x4e60, 0x1457, 0xe016, 0x225f, 0x4e5f, ++ 0x1457, 0x2658, 0x2261, 0x4e61, 0xe41e, 0x0a07, 0x1460, 0xe418, ++ 0x09dd, 0xe41e, 0x09c5, 0x145a, 0xe0c2, 0x0102, 0xe0c2, 0x0101, ++ 0xe167, 0x058a, 0x1097, 0x2697, 0xe049, 0xe009, 0x003f, 0xe0c3, ++ 0x010a, 0xaf0c, 0xe0c2, 0x010b, 0xe166, 0x0588, 0x1096, 0x2696, ++ 0xe0c2, 0x0082, 0x1097, 0x2697, 0xe0c2, 0x00ed, 0x1458, 0x225f, ++ 0x2661, 0xae02, 0x265c, 0xae02, 0x2660, 0xae06, 0x265f, 0xae04, ++ 0x265e, 0xae02, 0x265d, 0xae02, 0xe0c2, 0x0083, 0xa202, 0xe0c2, ++ 0x0093, 0xe41e, 0x0821, 0xe42e, 0xe41e, 0x0a1d, 0xa200, 0x4e5d, ++ 0xa202, 0x4e5e, 0xa202, 0x1542, 0xa105, 0xb616, 0x4e5f, 0x4e60, ++ 0xa103, 0xb616, 0x4e61, 0x1457, 0x2260, 0x4e60, 0x1457, 0xe016, ++ 0x225f, 0x4e5f, 0x1457, 0x2658, 0x2261, 0x4e61, 0xe41e, 0x0a07, ++ 0x1460, 0xe418, 0x09dd, 0x145a, 0xe0c2, 0x0102, 0xe0c2, 0x0101, ++ 0xe167, 0x058a, 0x1097, 0x2697, 0xe049, 0xe009, 0x003f, 0xe0c3, ++ 0x010a, 0xaf0c, 0xe0c2, 0x010b, 0xe166, 0x0588, 0x1096, 0x2696, ++ 0xe0c2, 0x0082, 0x1097, 0x2697, 0xe0c2, 0x00ed, 0x1458, 0x225f, ++ 0x2661, 0xae04, 0x2660, 0xae06, 0x265f, 0xae04, 0x265e, 0xae04, ++ 0xe0c2, 0x0083, 0xa202, 0xe0c2, 0x0093, 0xe41e, 0x0821, 0xe42e, ++ 0xe41e, 0x0a1d, 0xa200, 0x4e5d, 0x4e5e, 0xa202, 0x1542, 0xa107, ++ 0xb616, 0x4e61, 0x1457, 0x4e60, 0x1457, 0xe016, 0x4e5f, 0x1457, ++ 0x2658, 0x2261, 0x4e61, 0xe41e, 0x0a07, 0x1460, 0xe418, 0x09dd, ++ 0x145a, 0xe0c2, 0x0102, 0xe0c2, 0x0101, 0x1458, 0x225f, 0x2661, ++ 0xae04, 0x2660, 0xae06, 0x265f, 0xae08, 0xe0c2, 0x0083, 0xa202, ++ 0xe0c2, 0x0093, 0xe41e, 0x0821, 0xe42e, 0xe41e, 0x0a1d, 0xa200, ++ 0x4e5d, 0x4e5e, 0x4e5f, 0x4e60, 0x1457, 0x2658, 0x4e61, 0xe41e, ++ 0x0a07, 0x145a, 0xe0c2, 0x0102, 0xe0c2, 0x0101, 0x1461, 0xae12, ++ 0xe0c2, 0x0083, 0xa202, 0xe0c2, 0x0093, 0xe41e, 0x0a1d, 0xe42e, ++ 0xa200, 0x1517, 0xaf05, 0xa807, 0xb656, 0xa803, 0xe056, 0xae02, ++ 0x2643, 0xe049, 0xae0c, 0xe056, 0xae06, 0xe0c2, 0x0285, 0xa200, ++ 0x1514, 0xa105, 0xb636, 0xae02, 0x1544, 0xa103, 0xb432, 0xae02, ++ 0x1544, 0xa101, 0xb432, 0xae20, 0x1549, 0xe015, 0xe009, 0x003f, ++ 0xe056, 0xe0c2, 0x0288, 0xc420, 0xe161, 0x0578, 0xe162, 0x057e, ++ 0xe163, 0x02f0, 0x1444, 0x1543, 0xf1ea, 0xa102, 0xf11a, 0x1091, ++ 0x2692, 0x9f33, 0xc418, 0xe164, 0x02f8, 0x11b1, 0x27b2, 0x1091, ++ 0x2692, 0x9f03, 0x9f94, 0x1081, 0x2682, 0x9f14, 0xe42e, 0x8091, ++ 0x8092, 0xe163, 0x02f8, 0x10b1, 0x26b2, 0x9f13, 0x1081, 0x2682, ++ 0x9f03, 0xe42e, 0xf089, 0x10b1, 0x26b2, 0x9f33, 0x1081, 0x2682, ++ 0x9f03, 0xe42e, 0xd022, 0x0003, 0xe184, 0x09c0, 0x1091, 0x2692, ++ 0x9f13, 0x1081, 0x2682, 0x9f03, 0xe42e, 0xa200, 0xe0c2, 0x008a, ++ 0xe165, 0x0584, 0x1095, 0x2695, 0xe0c2, 0x0088, 0x1449, 0xae0a, ++ 0x2645, 0xae02, 0x2646, 0xae0e, 0x2645, 0xae0a, 0x2648, 0xae02, ++ 0xe165, 0x0584, 0x4895, 0x4e95, 0xe42e, 0xe166, 0x0594, 0x1496, ++ 0xe0c2, 0x0184, 0x8a17, 0x0008, 0xf05c, 0x1096, 0x2696, 0xe0c2, ++ 0x019e, 0x8a0c, 0x0003, 0xe42c, 0x1414, 0xa102, 0xe162, 0x01a0, ++ 0xe428, 0xe163, 0x01a4, 0x1429, 0xe092, 0xd022, 0x0003, 0xe184, ++ 0x09fd, 0x1091, 0x2691, 0x9f12, 0x1491, 0x9f13, 0xe082, 0x4e29, ++ 0xe002, 0x05be, 0xe005, 0x059a, 0xe428, 0x4f29, 0xe42e, 0x1457, ++ 0xe166, 0x05be, 0xf058, 0x1458, 0xe166, 0x0594, 0xe42a, 0x1457, ++ 0xae02, 0x1558, 0x2361, 0xe056, 0xae02, 0x1558, 0x235f, 0xe056, ++ 0xae18, 0x2686, 0xe0c2, 0x00e6, 0xe42e, 0xe0c0, 0x0095, 0xf7ea, ++ 0xe0c2, 0x0095, 0xe42e, 0x155a, 0xa105, 0x145a, 0xa002, 0xb616, ++ 0x4e5a, 0xe42e, 0xe049, 0xae03, 0xe042, 0xae02, 0xe42e, 0xa200, ++ 0xe166, 0x0200, 0xe188, 0x002e, 0x4e96, 0xe166, 0x022f, 0xe188, ++ 0x0059, 0x4e96, 0xe166, 0x0289, 0xe188, 0x00b5, 0x4e96, 0xe166, ++ 0x033f, 0xe188, 0x005b, 0x4e96, 0xa2fc, 0xe166, 0x039b, 0xc72d, ++ 0x4e96, 0xa200, 0xe166, 0x03c9, 0xe188, 0x0086, 0x4e96, 0xa202, ++ 0xcf94, 0xa2fd, 0xca40, 0xe052, 0xce40, 0xca46, 0xe052, 0xce46, ++ 0xe42e, 0xe004, 0x0200, 0x4e23, 0xe004, 0x022f, 0x4e24, 0xe004, ++ 0x0289, 0x4e25, 0xe004, 0x033f, 0x4e26, 0xe004, 0x039b, 0x4e27, ++ 0xa200, 0xcf94, 0xcf20, 0xcf22, 0xcf24, 0xcf26, 0xcf38, 0xe166, ++ 0x0450, 0xc705, 0x4e96, 0xa2fd, 0xca40, 0xe052, 0xce40, 0xca46, ++ 0xe052, 0xce46, 0xe42e, 0x1423, 0xe09c, 0x1496, 0xcf82, 0x1424, ++ 0xe09c, 0x1096, 0x2696, 0xcf8a, 0x1427, 0xe09c, 0x1496, 0xce42, ++ 0x1486, 0xce44, 0xca4a, 0xcf34, 0x1425, 0xe09c, 0x1096, 0x2696, ++ 0xcf28, 0xcf2a, 0x1096, 0x2696, 0xcf2c, 0xcf2e, 0x1096, 0x2696, ++ 0xcf30, 0x1096, 0x2696, 0xcf3c, 0x1426, 0xe09c, 0x1096, 0x2696, ++ 0xcf3a, 0xe42e, 0x1423, 0xe09c, 0xe167, 0x022d, 0x1486, 0x4e97, ++ 0xcb82, 0x4e87, 0x4e96, 0xe08c, 0x4e23, 0x1424, 0xe09c, 0xcb8a, ++ 0x4896, 0x4e96, 0xe08c, 0x4e24, 0x1425, 0xe09c, 0xcb28, 0x4896, ++ 0x4e96, 0xcb2c, 0x4896, 0x4e96, 0xe08c, 0x4e25, 0x1426, 0xe09c, ++ 0xcb3a, 0x4896, 0x4e96, 0xe08c, 0x4e26, 0x1427, 0xe09c, 0xa202, ++ 0x4e96, 0xce40, 0xca42, 0xce46, 0xe08c, 0x4e27, 0xe42e, 0xa202, ++ 0xae32, 0x1533, 0xae31, 0xe056, 0x151b, 0xaf0d, 0xae21, 0xe056, ++ 0x150d, 0xaf1f, 0xa803, 0xae1f, 0xe056, 0x1514, 0xa803, 0xe017, ++ 0xae1d, 0xe056, 0x1517, 0xa807, 0xae19, 0xe056, 0x1515, 0xae0d, ++ 0xe056, 0x2616, 0xcf16, 0x1443, 0xae18, 0x1540, 0xae0d, 0xe056, ++ 0x2641, 0xcf18, 0xe42e, 0x1449, 0xcf80, 0x144a, 0xcf88, 0xe42e, ++ 0xcf92, 0xe190, 0xcb88, 0xe42e, 0xcb90, 0xe42e, 0x1580, 0xf0b9, ++ 0xba01, 0xcf1b, 0xcf0a, 0xe190, 0xcb1b, 0xa803, 0xcb46, 0xe42b, ++ 0xba41, 0xe42e, 0xa201, 0xcf09, 0xe42e, 0x1449, 0xae02, 0xcf1a, ++ 0xa200, 0xcf40, 0xe190, 0xcb42, 0xcb1b, 0xaf03, 0x4f49, 0xcb47, ++ 0x4984, 0x4f85, 0xcf37, 0xe42e, 0x8a0c, 0x0003, 0xe42c, 0x1542, ++ 0x1443, 0xe016, 0xf049, 0x1549, 0xaf0b, 0x4f28, 0x2228, 0xcfa2, ++ 0xcb12, 0xcfa6, 0xe161, 0x056c, 0xe162, 0x0572, 0xd1d0, 0x0000, ++ 0xd022, 0x0005, 0xe184, 0x0b37, 0x1491, 0xae08, 0x2692, 0xcfa4, ++ 0xe004, 0x03c9, 0x0440, 0x0440, 0x0440, 0xe092, 0x142a, 0xe094, ++ 0xe163, 0x0450, 0xd022, 0x0002, 0xe184, 0x0b47, 0x1493, 0x4e92, ++ 0xe163, 0x0450, 0xd022, 0x0002, 0xe184, 0x0b50, 0x1491, 0x4e92, ++ 0x4e93, 0x8089, 0x8089, 0x8089, 0xe163, 0x0453, 0xd022, 0x0002, ++ 0xe184, 0x0b5b, 0x1493, 0x4e92, 0xe163, 0x0453, 0xcba8, 0x4892, ++ 0x4e92, 0x4893, 0x4e93, 0x4891, 0x4e91, 0xcbaa, 0x4e92, 0x4e93, ++ 0x4e91, 0xe084, 0x4e2a, 0xe002, 0x05be, 0xe005, 0x059a, 0xe428, ++ 0x4f2a, 0xe42e, 0xcf96, 0xe42e, 0xa200, 0xe166, 0x0010, 0xc712, ++ 0x4e96, 0xe166, 0x0460, 0xc76b, 0x4e96, 0xe166, 0x04cc, 0xc76b, ++ 0x4e96, 0xe42e, 0xd03a, 0x0000, 0xe42e, 0x1110, 0x2711, 0xae07, ++ 0xc874, 0xe012, 0xe042, 0xa83e, 0xf03a, 0x4e68, 0x5668, 0xc874, ++ 0xe046, 0xe422, 0xba7e, 0xf7ce, 0xe42e, 0xe005, 0x00ff, 0xae21, ++ 0xe00b, 0xffff, 0x1000, 0x2601, 0xe045, 0xf07b, 0x113b, 0x2762, ++ 0xe046, 0xf030, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xe41e, 0x03fa, ++ 0xe41e, 0x025e, 0x4810, 0x4e11, 0xba4e, 0xc001, 0x1418, 0xc000, ++ 0xe002, 0x0085, 0xf05a, 0xe41e, 0x0253, 0x4812, 0x4e13, 0xa202, ++ 0xe42e, 0x8a0d, 0x0001, 0xf02c, 0xba40, 0xba42, 0x8a0d, 0x0007, ++ 0xf04c, 0xba40, 0xae14, 0x4e17, 0xe41e, 0x0d5a, 0x1514, 0xa103, ++ 0xf05b, 0x1514, 0xa105, 0xf02b, 0xba4c, 0xe41e, 0x0d7c, 0x8a0d, ++ 0x000e, 0xf05c, 0xb802, 0x1517, 0xe055, 0x4f17, 0xe41e, 0x0db1, ++ 0x1514, 0xa101, 0xf0ab, 0x1514, 0xa107, 0xf07b, 0xe41e, 0x0ddc, ++ 0xe41e, 0x0e29, 0xe41e, 0x0e6f, 0xe41e, 0x0e8b, 0x1417, 0xa806, ++ 0xae04, 0x4e6c, 0xe004, 0xdca9, 0x366c, 0xa81e, 0x0c33, 0x4e34, ++ 0xe004, 0xba98, 0x366c, 0xa81e, 0x0c33, 0x4e35, 0x140d, 0xaf12, ++ 0xa802, 0x1514, 0xa105, 0xb616, 0x1519, 0xaf0b, 0xa83f, 0xa113, ++ 0xb60a, 0xae10, 0x2617, 0x4e17, 0x140e, 0xaf04, 0xa802, 0x1514, ++ 0xa101, 0xb636, 0x1514, 0xa107, 0xb636, 0x1514, 0xa103, 0xf029, ++ 0xe016, 0xa203, 0xae05, 0xe015, 0x230e, 0x4f0e, 0xe049, 0xae05, ++ 0x270e, 0x4f0e, 0xae12, 0x2617, 0x4e17, 0xa202, 0xe42e, 0x1414, ++ 0xa104, 0xe42a, 0x1414, 0xa106, 0xe42a, 0x140e, 0xe008, 0x0037, ++ 0x150f, 0xaf1b, 0xa80f, 0xae1b, 0xe056, 0x4e0e, 0x1417, 0xaf14, ++ 0xa80e, 0xae1a, 0x261c, 0x4e0f, 0x1417, 0xaf14, 0xa802, 0xe0c1, ++ 0x0060, 0xaf09, 0xa803, 0xe056, 0x1517, 0xaf17, 0xa807, 0xb632, ++ 0xae12, 0x1553, 0xaf13, 0xa803, 0xae11, 0xe056, 0x1553, 0xe009, ++ 0x00ff, 0xe056, 0x4e53, 0xe42e, 0xe42e, 0x8a53, 0x0000, 0xf08d, ++ 0x1553, 0xa80d, 0xf19b, 0xa809, 0xf2ab, 0xe40e, 0x0c9e, 0x1553, ++ 0xa80d, 0x1414, 0xa104, 0xf0ca, 0x1414, 0xa106, 0xf09a, 0xe40b, ++ 0x0c6b, 0x8a53, 0x0008, 0xe40d, 0x0cbe, 0xe40e, 0x0cd9, 0xe40b, ++ 0x0cfc, 0xe40e, 0x0d16, 0x1454, 0xaf10, 0xa81e, 0xae38, 0x1554, ++ 0xaf19, 0xa81f, 0xae31, 0xe056, 0x1554, 0xe009, 0x00ff, 0xae21, ++ 0xe056, 0x2655, 0x4854, 0x4e55, 0xe40e, 0x0d30, 0x1455, 0xaf10, ++ 0xa81e, 0xae38, 0x1554, 0xaf11, 0xe009, 0x00ff, 0xae29, 0xe056, ++ 0x1554, 0xa81f, 0xae21, 0xe056, 0x1555, 0xaf19, 0xa81f, 0xae19, ++ 0xe056, 0x1554, 0xaf09, 0xa81f, 0xae11, 0xe056, 0x1555, 0xe009, ++ 0x00ff, 0xe056, 0x4854, 0x4e55, 0xe40e, 0x0d30, 0x1455, 0xaf18, ++ 0xa81e, 0xae38, 0x1554, 0xaf11, 0xe009, 0x00ff, 0xae29, 0xe056, ++ 0x1554, 0xa81f, 0xae21, 0xe056, 0x1555, 0xaf11, 0xa81f, 0xae19, ++ 0xe056, 0x1554, 0xaf09, 0xa81f, 0xae11, 0xe056, 0x1555, 0xe009, ++ 0x00ff, 0xe056, 0x4854, 0x4e55, 0xe40e, 0x0d30, 0x1455, 0xaf18, ++ 0xa81e, 0xae38, 0x1554, 0xaf09, 0xe009, 0x0fff, 0xae21, 0xe056, ++ 0x1555, 0xaf11, 0xa81f, 0xae19, 0xe056, 0x1554, 0xa81f, 0xae11, ++ 0xe056, 0x1555, 0xe009, 0x00ff, 0xe056, 0x4854, 0x4e55, 0xe40e, ++ 0x0d30, 0x1455, 0xaf18, 0xa81e, 0xae38, 0x1554, 0xaf19, 0xa81f, ++ 0xae31, 0xe056, 0x1554, 0xa81f, 0xae29, 0xe056, 0x1554, 0xaf09, ++ 0xa81f, 0xae21, 0xe056, 0x1555, 0xaf11, 0xa81f, 0xae19, 0xe056, ++ 0x1554, 0xaf11, 0xa81f, 0xae11, 0xe056, 0x1555, 0xe009, 0x00ff, ++ 0xe056, 0x4854, 0x4e55, 0xf35e, 0x1454, 0xaf08, 0xe008, 0x0fff, ++ 0xae28, 0x1555, 0xaf11, 0xa81f, 0xae21, 0xe056, 0x1555, 0xaf19, ++ 0xa81f, 0xae19, 0xe056, 0x1554, 0xa81f, 0xae11, 0xe056, 0x1555, ++ 0xe009, 0x00ff, 0xe056, 0x4854, 0x4e55, 0xf36e, 0x1454, 0xaf08, ++ 0xe008, 0x0fff, 0xae28, 0x1555, 0xaf19, 0xa81f, 0xae21, 0xe056, ++ 0x1555, 0xaf11, 0xa81f, 0xae19, 0xe056, 0x1554, 0xa81f, 0xae11, ++ 0xe056, 0x1555, 0xe009, 0x00ff, 0xe056, 0x4854, 0x4e55, 0xf1ce, ++ 0x8a53, 0x0009, 0x1454, 0xaf18, 0xa81e, 0xf04c, 0x1454, 0xaf08, ++ 0xa81e, 0xae18, 0x1556, 0xaf09, 0xe009, 0x0fff, 0xe056, 0x4e56, ++ 0x1563, 0xe423, 0xe049, 0xe008, 0xf0ff, 0xaf19, 0xa81f, 0xae11, ++ 0xe056, 0x4e56, 0xe42e, 0x1456, 0xaf18, 0xa81e, 0xae18, 0x1554, ++ 0xa81f, 0xae11, 0xe056, 0x1556, 0xaf09, 0xe009, 0x00ff, 0xe056, ++ 0x4e56, 0xe42e, 0x140d, 0xaf08, 0xa80e, 0xf038, 0xba40, 0xf02e, ++ 0xb800, 0xe049, 0xa105, 0x4e14, 0xf069, 0xb807, 0x4f1b, 0xa12d, ++ 0xb676, 0x4e14, 0xe004, 0x0019, 0xae20, 0xe00a, 0xc595, 0x361b, ++ 0xa802, 0xae0a, 0x151b, 0xe001, 0x0540, 0xe09d, 0x1586, 0xae0d, ++ 0xe056, 0x261b, 0x4e1b, 0xe42e, 0xba48, 0x4e69, 0xa110, 0xf040, ++ 0xba40, 0xae16, 0x4e19, 0x150d, 0xaf05, 0xa807, 0xf1b9, 0x1469, ++ 0xe049, 0xa111, 0xb5a2, 0xe049, 0xa133, 0xb422, 0xe049, 0xa137, ++ 0xb422, 0xe049, 0xa13b, 0xb422, 0xae0a, 0x2619, 0x4e19, 0xa202, ++ 0x1569, 0xa111, 0xb602, 0x1569, 0xb616, 0xae14, 0x2619, 0x4e19, ++ 0xe42e, 0xa103, 0x1469, 0xae0a, 0x2619, 0x4e19, 0xf069, 0xba40, ++ 0xae14, 0x2619, 0x4e19, 0xe42e, 0xa103, 0xae15, 0x2719, 0x4f19, ++ 0xe42e, 0xe051, 0x140f, 0xaf1c, 0xa806, 0x1514, 0xa107, 0xf08b, ++ 0x1514, 0xa105, 0xf05b, 0x8a0c, 0x0001, 0xf02c, 0xba42, 0xae16, ++ 0x2617, 0x4e17, 0x1405, 0xa01e, 0xaf08, 0x1517, 0xaf17, 0xa803, ++ 0xf04b, 0xae06, 0xa01e, 0xaf08, 0x4e15, 0xa006, 0xaf04, 0x4e1e, ++ 0x1403, 0xa01e, 0xaf08, 0x1517, 0xaf17, 0xa805, 0xf04b, 0xae06, ++ 0xa01e, 0xaf08, 0x4e16, 0xe42e, 0xa202, 0x1514, 0xa103, 0xf1d9, ++ 0xb808, 0xe049, 0xa809, 0xae02, 0x4e6b, 0xf0cb, 0xb80a, 0xae02, ++ 0x4e6b, 0xa202, 0xae18, 0xba4b, 0xae0d, 0xe056, 0xba4b, 0xe056, ++ 0x4e1c, 0xe004, 0xe42d, 0x1519, 0xaf0b, 0xa83f, 0xa119, 0xf027, ++ 0xaf10, 0x366b, 0xa806, 0xf02e, 0xba40, 0xae04, 0x1517, 0xe055, ++ 0x4f17, 0x1417, 0xaf04, 0xa806, 0xa802, 0xe016, 0x4e33, 0x1517, ++ 0xaf05, 0xa807, 0xa107, 0xf079, 0xe161, 0x0460, 0xe41e, 0x0eca, ++ 0xae0c, 0x4e1a, 0x1514, 0xa105, 0xf079, 0xe161, 0x0460, 0xe41e, ++ 0x0eca, 0x261a, 0x4e1a, 0xe161, 0x04cc, 0xe41e, 0x0eca, 0xae06, ++ 0x261a, 0x4e1a, 0xba42, 0xa052, 0x4e2d, 0xba42, 0xa032, 0x4e2c, ++ 0xe42e, 0xa200, 0x4e18, 0x140d, 0xaf18, 0xa806, 0xa102, 0xf04a, ++ 0xa102, 0xf0da, 0xe42e, 0xba40, 0xe42a, 0xba42, 0xf08a, 0xa102, ++ 0xf0aa, 0xa102, 0xf14a, 0xa102, 0xf1ea, 0xe42e, 0xe004, 0x008f, ++ 0x4e18, 0xf1fe, 0xba42, 0xae04, 0x4e6a, 0xe005, 0x936c, 0x376a, ++ 0xa81f, 0xe004, 0x00a0, 0xe056, 0x4e18, 0xf13e, 0xba42, 0xae04, ++ 0x4e6a, 0xe005, 0x1248, 0x376a, 0xa81f, 0xe004, 0x00c0, 0xe056, ++ 0x4e18, 0xf07e, 0xba40, 0xe049, 0xa91c, 0xae08, 0x4e18, 0xe42b, ++ 0x1419, 0xaf0a, 0xa83e, 0xba45, 0xe042, 0xa10f, 0xa002, 0xf029, ++ 0xba48, 0x1519, 0xaf0b, 0xae0b, 0xe055, 0x4f19, 0xe42e, 0xe004, ++ 0x0006, 0x1519, 0xaf0b, 0xa83f, 0xa10b, 0xb426, 0x1519, 0xaf0b, ++ 0xa83f, 0xa11b, 0xb426, 0x4e2b, 0x8a0d, 0x000b, 0xa202, 0xa201, ++ 0xf04c, 0xba40, 0xf02a, 0xba43, 0xae0e, 0xae09, 0xe056, 0x1517, ++ 0xe055, 0x4f17, 0xe42e, 0x1469, 0xa110, 0xa201, 0xb66d, 0xb804, ++ 0xb611, 0xe042, 0xa042, 0x4e31, 0x1514, 0xa103, 0xf0db, 0x1514, ++ 0xa105, 0xf0ab, 0x1469, 0xa110, 0xa201, 0xb66d, 0xb804, 0xb611, ++ 0xe042, 0xa042, 0x4e32, 0xba40, 0xa03a, 0x4e30, 0xa21a, 0x1519, ++ 0xaf0b, 0xa83f, 0xa10b, 0xb426, 0xa111, 0xb426, 0x4e2e, 0xa200, ++ 0x1519, 0xaf0b, 0xa83f, 0xa10b, 0xb426, 0xa111, 0xb426, 0x4e2f, ++ 0xa202, 0x4e36, 0xa200, 0x4e38, 0x4e39, 0xa202, 0x1519, 0xaf0b, ++ 0xa83f, 0xa10f, 0xb60e, 0x1518, 0xaf0f, 0xa803, 0xb612, 0xa016, ++ 0x4e37, 0xe42e, 0xba40, 0xb7f0, 0xe008, 0x003f, 0x4e6d, 0xb82a, ++ 0x4e6b, 0xa100, 0xf31a, 0x146d, 0x4e6c, 0x146b, 0xa102, 0xe41a, ++ 0x0f05, 0xa200, 0x4e6c, 0x146b, 0xa104, 0xe41a, 0x0f05, 0x146d, ++ 0x4e6c, 0x146b, 0xa104, 0xe41a, 0x1131, 0x146d, 0x4e6c, 0x146b, ++ 0xa106, 0xe41a, 0x0f5f, 0xa200, 0x4e6c, 0x146b, 0xa108, 0xe41a, ++ 0x0f5f, 0x146d, 0x4e6c, 0x146b, 0xa108, 0xe41a, 0x1131, 0x146d, ++ 0x4e6c, 0x146b, 0xa10a, 0xe41a, 0x10b9, 0x146d, 0x4e6c, 0x146b, ++ 0xa10c, 0xe41a, 0x10f5, 0x146b, 0xe42e, 0xa200, 0x4e78, 0x4e79, ++ 0xa21e, 0x4e7c, 0x4e7d, 0xa200, 0x4e75, 0x4e76, 0x1415, 0x1516, ++ 0xa802, 0xa803, 0xe052, 0xf11a, 0xba41, 0x2b6c, 0xa803, 0x357d, ++ 0xe082, 0x0479, 0xe09c, 0x1486, 0xe056, 0x4e86, 0x147d, 0xa102, ++ 0x4e7d, 0x1475, 0xa002, 0x4e75, 0xb82d, 0x2b6c, 0xa807, 0x4f72, ++ 0xa202, 0x4e77, 0x1572, 0x3777, 0xa803, 0x357d, 0xe082, 0x0479, ++ 0xe09c, 0x1486, 0xe056, 0x4e86, 0x1475, 0xa002, 0x4e75, 0x0c15, ++ 0xf0e2, 0x157d, 0xa807, 0x1479, 0xb436, 0x4e79, 0x147d, 0xe049, ++ 0xa818, 0xa007, 0xa807, 0xe056, 0x4e7d, 0xf12e, 0x157c, 0xa819, ++ 0x141e, 0xb612, 0x0478, 0x4e78, 0x4e79, 0x147c, 0xa018, 0xa81e, ++ 0x4e7c, 0x4e7d, 0xa200, 0x4e75, 0x1476, 0xa002, 0x4e76, 0x1477, ++ 0xa102, 0x4e77, 0xf502, 0x1476, 0x0c16, 0xf474, 0xe42e, 0x1415, ++ 0xa106, 0xf7f2, 0xa006, 0x4e70, 0x1516, 0xa107, 0xf7f3, 0xa007, ++ 0x4f71, 0xe40a, 0x0fdc, 0xe409, 0x0fdc, 0x1415, 0xa802, 0x4e70, ++ 0xa200, 0x4e78, 0x4e79, 0xa21e, 0x0c70, 0x4e7c, 0x4e7d, 0x1471, ++ 0x4e76, 0x1470, 0x4e75, 0x1479, 0x4e7a, 0x4e7b, 0x147d, 0x4e7e, ++ 0x4e7f, 0xb82e, 0x2a6c, 0xa87e, 0x4e72, 0xa200, 0x4e77, 0x1572, ++ 0xa803, 0x357f, 0xe082, 0x047b, 0xe09c, 0x1486, 0xe056, 0x4e86, ++ 0x1572, 0xaf03, 0x4f72, 0x1477, 0xa802, 0xf0e8, 0x157f, 0xa807, ++ 0x147b, 0xb436, 0x4e7b, 0x147f, 0xe049, 0xa818, 0xa007, 0xa807, ++ 0xe056, 0x4e7f, 0xf0de, 0x157e, 0xa819, 0x141e, 0xb612, 0x047a, ++ 0x4e7a, 0x4e7b, 0x147e, 0xa018, 0xa81e, 0x4e7e, 0x4e7f, 0x1477, ++ 0xa002, 0x4e77, 0xa10c, 0xf544, 0x157d, 0xa807, 0xa105, 0x1479, ++ 0xb42a, 0x4e79, 0x147d, 0xe049, 0xa818, 0xa005, 0xa807, 0xe056, ++ 0x4e7d, 0x1475, 0xa004, 0x4e75, 0x0c15, 0xe404, 0x0f7b, 0x157c, ++ 0xa819, 0xa119, 0x141e, 0xb606, 0x0478, 0x4e78, 0x4e79, 0x147c, ++ 0xa008, 0xa81e, 0x4e7c, 0x4e7d, 0x1476, 0xa006, 0x4e76, 0x0c16, ++ 0xe404, 0x0f79, 0xe40e, 0x104e, 0x1416, 0xa802, 0x4e71, 0xa200, ++ 0x4e78, 0x4e79, 0xa21e, 0x1571, 0xb592, 0x0c70, 0x4e7c, 0x4e7d, ++ 0x1471, 0x4e76, 0x1470, 0x4e75, 0x1479, 0x4e7a, 0x4e7b, 0x147d, ++ 0x4e7e, 0x4e7f, 0xb82e, 0x2a6c, 0xa87e, 0x4e72, 0xa200, 0x4e77, ++ 0x1572, 0xa803, 0x357f, 0xe082, 0x047b, 0xe09c, 0x1486, 0xe056, ++ 0x4e86, 0x1572, 0xaf03, 0x4f72, 0x1477, 0xa104, 0xf11a, 0x1477, ++ 0xa10a, 0xf0ea, 0x157f, 0xa807, 0x147b, 0xb436, 0x4e7b, 0x147f, ++ 0xe049, 0xa818, 0xa007, 0xa807, 0xe056, 0x4e7f, 0xf0de, 0x157e, ++ 0xa819, 0x141e, 0xb612, 0x047a, 0x4e7a, 0x4e7b, 0x147e, 0xa018, ++ 0xa81e, 0x4e7e, 0x4e7f, 0x1477, 0xa002, 0x4e77, 0xa10c, 0xf514, ++ 0x157d, 0xa807, 0xa107, 0x1479, 0xb42a, 0x4e79, 0x147d, 0xe049, ++ 0xa818, 0xa003, 0xa807, 0xe056, 0x4e7d, 0x1475, 0xa006, 0x4e75, ++ 0x0c15, 0xe404, 0x0fec, 0x157c, 0xa819, 0xa111, 0x141e, 0xb606, ++ 0x0478, 0x4e78, 0x4e79, 0x147c, 0xa010, 0xa81e, 0x4e7c, 0x4e7d, ++ 0x1476, 0xa004, 0x4e76, 0x0c16, 0xe404, 0x0fea, 0x1470, 0xe406, ++ 0x108d, 0xa200, 0x4e78, 0x4e79, 0xa21e, 0x4e7c, 0x4e7d, 0xa200, ++ 0x4e75, 0xa200, 0x4e76, 0xba40, 0x4e6e, 0xa201, 0x146e, 0xf02a, ++ 0xba41, 0x2b6c, 0xa803, 0x357d, 0xe082, 0x0479, 0xe09c, 0x1486, ++ 0xe056, 0x4e86, 0x157d, 0xa819, 0x141e, 0xb612, 0x0479, 0x4e79, ++ 0x147d, 0xa018, 0xa81e, 0x4e7d, 0x1476, 0xa002, 0x4e76, 0x0c16, ++ 0xe404, 0x105d, 0x157c, 0xa807, 0x1478, 0xb436, 0x4e78, 0x4e79, ++ 0x147c, 0xe049, 0xa818, 0xa007, 0xa807, 0xe056, 0x4e7c, 0x4e7d, ++ 0x1475, 0xa002, 0x4e75, 0x0c70, 0xf4d4, 0x1471, 0xf2aa, 0xa200, ++ 0x4e78, 0x4e79, 0xa21e, 0x0c70, 0x4e7c, 0x4e7d, 0x1470, 0x4e75, ++ 0xba40, 0x4e6f, 0xa201, 0x146f, 0xf02a, 0xba41, 0x2b6c, 0xa803, ++ 0x357d, 0xe082, 0x0479, 0xe09c, 0x1486, 0xe056, 0x4e86, 0x157d, ++ 0xa807, 0x1479, 0xb436, 0x4e79, 0x147d, 0xe049, 0xa819, 0xa006, ++ 0xa806, 0xe056, 0x4e7d, 0x1475, 0xa002, 0x4e75, 0x0c15, 0xf634, ++ 0xe42e, 0xa200, 0x4e78, 0x4e79, 0xa21e, 0x4e7c, 0x4e7d, 0xa200, ++ 0x4e76, 0xba40, 0x4e6f, 0xa200, 0x4e75, 0xa201, 0x146f, 0xf02a, ++ 0xba41, 0x2b6c, 0xa803, 0x357d, 0xe082, 0x0479, 0xe09c, 0x1486, ++ 0xe056, 0x4e86, 0x157d, 0xa807, 0x1479, 0xb436, 0x4e79, 0x147d, ++ 0xe049, 0xa818, 0xa007, 0xa807, 0xe056, 0x4e7d, 0x1475, 0xa002, ++ 0x4e75, 0x0c15, 0xf634, 0x157c, 0xa819, 0x141e, 0xb612, 0x0478, ++ 0x4e78, 0x4e79, 0x147c, 0xa018, 0xa81e, 0x4e7c, 0x4e7d, 0x1476, ++ 0xa002, 0x4e76, 0x0c16, 0xf4e4, 0xe42e, 0xa200, 0x4e78, 0x4e79, ++ 0xa21e, 0x4e7c, 0x4e7d, 0xa200, 0x4e75, 0xba40, 0x4e6e, 0xa200, ++ 0x4e76, 0xa201, 0x146e, 0xf02a, 0xba41, 0x2b6c, 0xa803, 0x357d, ++ 0xe082, 0x0479, 0xe09c, 0x1486, 0xe056, 0x4e86, 0x157d, 0xa819, ++ 0x141e, 0xb612, 0x0479, 0x4e79, 0x147d, 0xa018, 0xa81e, 0x4e7d, ++ 0x1476, 0xa002, 0x4e76, 0x0c16, 0xf654, 0x157c, 0xa807, 0x1478, ++ 0xb436, 0x4e78, 0x4e79, 0x147c, 0xe049, 0xa818, 0xa007, 0xa807, ++ 0xe056, 0x4e7c, 0x4e7d, 0x1475, 0xa002, 0x4e75, 0x0c15, 0xf4e4, ++ 0xe42e, 0xa200, 0x4e78, 0x4e79, 0xa21e, 0x4e7c, 0x4e7d, 0xa200, ++ 0x4e76, 0xa200, 0x4e75, 0x157d, 0xa807, 0xa107, 0x1479, 0xb5f6, ++ 0xe083, 0xe041, 0xe09d, 0x147d, 0xe049, 0xa818, 0xa003, 0xa807, ++ 0xe056, 0x4e7e, 0x1486, 0x367e, 0xa802, 0x4e73, 0x157d, 0xa819, ++ 0xa119, 0x141e, 0xb612, 0x1579, 0xe045, 0xe082, 0xe042, 0xe09c, ++ 0x147d, 0xa008, 0xa81e, 0x4e7e, 0x1486, 0x367e, 0xa802, 0x4e74, ++ 0x1475, 0x2676, 0xf048, 0x146c, 0x4e72, 0xf10e, 0x1475, 0xf048, ++ 0x1474, 0x4e72, 0xf0be, 0x1476, 0xf076, 0x1473, 0x0c74, 0xf04a, ++ 0x146c, 0x4e72, 0xf03e, 0x1473, 0x4e72, 0xe082, 0x0479, 0xe09c, ++ 0x1486, 0xe049, 0x377d, 0x2b72, 0xa803, 0x357d, 0x4f72, 0xa203, ++ 0x357d, 0xe015, 0xe052, 0x2672, 0x4e86, 0x157d, 0xa807, 0x1479, ++ 0xb436, 0x4e79, 0x147d, 0xe049, 0xa818, 0xa007, 0xa807, 0xe056, ++ 0x4e7d, 0x1475, 0xa002, 0x4e75, 0x0c15, 0xe404, 0x113b, 0x157c, ++ 0xa819, 0x141e, 0xb612, 0x0478, 0x4e78, 0x4e79, 0x147c, 0xa018, ++ 0xa81e, 0x4e7c, 0x4e7d, 0x1476, 0xa002, 0x4e76, 0x0c16, 0xe404, ++ 0x1139, 0xe42e, 0x1414, 0xa102, 0x1543, 0xe41a, 0x11b4, 0x1414, ++ 0xa104, 0xe41a, 0x1213, 0xe42e, 0xf259, 0xd182, 0x0000, 0xe160, ++ 0x0560, 0xe161, 0x0566, 0xa200, 0x4e80, 0x144a, 0xaf0a, 0x4e81, ++ 0xe164, 0x0578, 0xe165, 0x057e, 0xe418, 0x129d, 0xe41e, 0x0afe, ++ 0x4884, 0x4e85, 0x1481, 0x4e70, 0xa27e, 0x1580, 0xb616, 0x4e49, ++ 0xe164, 0x057c, 0xe165, 0x0582, 0xe41e, 0x0b0d, 0xe41e, 0x12c4, ++ 0xe42e, 0xe160, 0x0565, 0xe161, 0x056b, 0x1449, 0x154a, 0xd022, ++ 0x0005, 0xe184, 0x11e6, 0x4688, 0xaf02, 0x4789, 0xaf03, 0xe160, ++ 0x0560, 0xe161, 0x0566, 0xe164, 0x0578, 0xe165, 0x057e, 0xd182, ++ 0x06db, 0xd022, 0x0003, 0xe184, 0x11fd, 0x1481, 0xe418, 0x129d, ++ 0xe41e, 0x0afe, 0x4894, 0x4e95, 0x8090, 0x8091, 0xe161, 0x0560, ++ 0xe162, 0x0566, 0xa200, 0xa201, 0xd022, 0x0005, 0xe184, 0x120b, ++ 0xae02, 0x2691, 0xae03, 0x2792, 0x4e49, 0x4f4a, 0xe41e, 0x0b0d, ++ 0xe41e, 0x12c4, 0xe42e, 0xd182, 0x06db, 0xe41e, 0x12f3, 0x1444, ++ 0xa106, 0xe40a, 0x126d, 0xe160, 0x0561, 0xe161, 0x0567, 0xa200, ++ 0x4e80, 0x144a, 0xaf08, 0x4681, 0xe164, 0x0579, 0xe165, 0x057f, ++ 0xe418, 0x129d, 0x1580, 0x4884, 0x4e85, 0xe409, 0x127c, 0xb812, ++ 0xae02, 0x151b, 0xaf0b, 0xa803, 0xb4d2, 0x4e6d, 0xe004, 0x0864, ++ 0x366d, 0xa806, 0x4e44, 0xf16a, 0xa102, 0xf24a, 0x1489, 0x4e81, ++ 0x8088, 0xe418, 0x129d, 0xcf0a, 0x118c, 0x278d, 0xe190, 0xcb46, ++ 0xcf0b, 0x4894, 0x4e95, 0xe190, 0xcb47, 0x4994, 0x4f95, 0x8090, ++ 0xf34e, 0x1488, 0x4e90, 0x108c, 0x268d, 0xcf0a, 0xe190, 0xe190, ++ 0xe190, 0xcb46, 0x4894, 0x4e95, 0xcb4c, 0xcf08, 0x4894, 0x4e95, ++ 0xf24e, 0xcb4a, 0xcf08, 0x118c, 0x278d, 0xcf0b, 0x4894, 0x4e95, ++ 0xe190, 0xcb47, 0x4994, 0x4f95, 0xf18e, 0xe164, 0x0578, 0xe165, ++ 0x057e, 0xcb4a, 0xcf08, 0x4894, 0x4e95, 0xcb4c, 0xcf08, 0x4894, ++ 0x4e95, 0x144a, 0x4e70, 0xf0fe, 0x1481, 0x4e70, 0xa200, 0xcf08, ++ 0xa27f, 0x4f49, 0xcf08, 0xe42e, 0x1481, 0x4e70, 0xa27e, 0x1580, ++ 0xb616, 0x4e49, 0xe164, 0x057c, 0xe165, 0x0582, 0xa200, 0xcf40, ++ 0xe190, 0xe190, 0xcb46, 0x4894, 0x4e95, 0xa202, 0xcf40, 0xe190, ++ 0xe190, 0xcb46, 0x4894, 0x4e95, 0xe42e, 0xa200, 0x4e80, 0x502d, ++ 0xa002, 0xa14a, 0xf042, 0xa04a, 0xa201, 0x4f81, 0xe049, 0xa147, ++ 0xe42a, 0xae02, 0x2633, 0xf035, 0xf0bb, 0xf13e, 0xcc8e, 0xe190, ++ 0xbf40, 0x4e71, 0xbf42, 0x4e72, 0x1071, 0x2672, 0xe42e, 0x5634, ++ 0x3433, 0x4e71, 0x5635, 0x3433, 0x4e72, 0x1071, 0x2672, 0xe42e, ++ 0xa202, 0x4e80, 0xa200, 0xe42e, 0x1542, 0xe009, 0x007f, 0xae03, ++ 0xe001, 0x0600, 0xe09d, 0x4896, 0x4e96, 0x1542, 0xe009, 0x007f, ++ 0xe003, 0x007f, 0xe429, 0xc001, 0x1416, 0xf04a, 0x1010, 0x2611, ++ 0xf0ce, 0xc000, 0xe0c0, 0x0041, 0xe005, 0x00a0, 0xae11, 0xe042, ++ 0xe0c1, 0x005a, 0xae1b, 0xe042, 0xc000, 0x1542, 0xaf0f, 0xae13, ++ 0xe042, 0xce20, 0xd111, 0x0600, 0xd112, 0x0100, 0xd113, 0x0002, ++ 0xca28, 0xf7f8, 0xe42e, 0x1542, 0xe009, 0x007f, 0xf1f9, 0xc001, ++ 0x1416, 0xf04a, 0x1010, 0x2611, 0xf0ce, 0xc000, 0xe0c0, 0x0041, ++ 0xe005, 0x00a0, 0xae11, 0xe042, 0xe0c1, 0x005a, 0xae1b, 0xe042, ++ 0xc000, 0x1542, 0xae05, 0xe042, 0xce20, 0xd111, 0x0600, 0xd112, ++ 0x0100, 0xd113, 0x0003, 0xca28, 0xf7f8, 0x1542, 0xe009, 0x007f, ++ 0xae03, 0xe001, 0x0600, 0xe09d, 0x1096, 0x2696, 0xcf48, 0xe190, ++ 0xe42e, 0xa200, 0x4e40, 0x4e41, 0x4e42, 0xe41e, 0x0a2f, 0xe41e, ++ 0x1377, 0x1442, 0xe002, 0x0117, 0xf028, 0xe190, 0x1440, 0xe41a, ++ 0x0a59, 0xe41e, 0x13c9, 0xe41e, 0x138a, 0x1442, 0xa002, 0x4e42, ++ 0x1440, 0xa002, 0x4e40, 0x0c15, 0xf6d4, 0xa200, 0x4e40, 0x1441, ++ 0xa002, 0x4e41, 0x0c16, 0xf042, 0xe41e, 0x13a8, 0xf63e, 0x1414, ++ 0xa106, 0xe418, 0x12d3, 0xe42e, 0xa200, 0x4e40, 0x4e41, 0x4e42, ++ 0xe41e, 0x0a2f, 0xe41e, 0x1377, 0x1442, 0xe002, 0x0040, 0xf028, ++ 0xe190, 0x1440, 0xe41a, 0x0a59, 0xe41e, 0x13f2, 0xe41e, 0x138a, ++ 0x1442, 0xa002, 0x4e42, 0x1440, 0xa002, 0x4e40, 0x0c15, 0xf6d4, ++ 0xa200, 0x4e40, 0x1441, 0xa002, 0x4e41, 0x0c16, 0xf042, 0xe41e, ++ 0x13a8, 0xf63e, 0x1414, 0xa104, 0xe418, 0x12d3, 0xe42e, 0xa200, ++ 0x4e1f, 0x4e20, 0xa21e, 0x4e21, 0x4e22, 0xe42e, 0xe085, 0xa101, ++ 0xf08b, 0xe083, 0x0520, 0xe09d, 0x1486, 0x3622, 0xa802, 0xe42e, ++ 0xba40, 0xe42e, 0x1440, 0xa002, 0x0c15, 0xf0e2, 0x1522, 0xa807, ++ 0x1420, 0xb436, 0x4e20, 0x1422, 0xe049, 0xa818, 0xa007, 0xa807, ++ 0xe056, 0x4e22, 0xe42e, 0x1521, 0xa819, 0x141e, 0xb612, 0x041f, ++ 0x4e1f, 0x4e20, 0x1421, 0xa018, 0xa81e, 0x4e21, 0x4e22, 0xe42e, ++ 0x8a0d, 0x0008, 0xf1dc, 0xba40, 0xf1b8, 0xe41e, 0x03fa, 0xa200, ++ 0xba4f, 0xae10, 0xe056, 0xba4f, 0xae10, 0xe056, 0xe002, 0x00aa, ++ 0xf0aa, 0xa102, 0xf03a, 0xa200, 0xe42e, 0xba4e, 0xba4e, 0xba4e, ++ 0xba4e, 0xba4e, 0xba4e, 0xba4e, 0xba4e, 0xba4e, 0xba4e, 0xa202, ++ 0xe42e, 0xe41e, 0x1425, 0xe41e, 0x0a7b, 0xe41e, 0x1486, 0xa27e, ++ 0x4e49, 0xb830, 0xe41e, 0x0af8, 0x4e4a, 0x1514, 0xa107, 0xa200, ++ 0xe419, 0x12c4, 0xba40, 0x4e48, 0xe162, 0x056b, 0x154a, 0xd022, ++ 0x0005, 0xe184, 0x13e4, 0x478a, 0xaf03, 0xe41e, 0x07b9, 0xe41e, ++ 0x14ee, 0xe41e, 0x0af3, 0xe41e, 0x0b72, 0xe41e, 0x0821, 0xe41e, ++ 0x0aa2, 0xe42e, 0xe41e, 0x1425, 0xe41e, 0x0a7b, 0xe41e, 0x1486, ++ 0xe41e, 0x14c5, 0xe41e, 0x142f, 0xe41e, 0x0acf, 0xe41e, 0x0af3, ++ 0xe41e, 0x11aa, 0xe41e, 0x0af3, 0xe41e, 0x1460, 0xe161, 0x0565, ++ 0xe162, 0x056b, 0x1449, 0x154a, 0xd022, 0x0005, 0xe184, 0x1413, ++ 0x4689, 0xaf02, 0x478a, 0xaf03, 0xe41e, 0x07b9, 0xe41e, 0x1537, ++ 0xe41e, 0x0af3, 0x1414, 0xa102, 0xe41a, 0x0b1c, 0xe41e, 0x0b72, ++ 0xe41e, 0x0821, 0xe41e, 0x0aa2, 0xe42e, 0xa200, 0xe166, 0x0043, ++ 0xc70c, 0x4e96, 0xe166, 0x0560, 0xc723, 0x4e96, 0xe42e, 0xa200, ++ 0x4e43, 0xa200, 0x4e44, 0xa200, 0x4e49, 0x1517, 0xaf05, 0xa807, ++ 0xa107, 0xf0a9, 0xe161, 0x0460, 0x151a, 0xaf0d, 0xa80f, 0xe095, ++ 0xe41e, 0x137e, 0x4e43, 0x1514, 0xa105, 0xf0a9, 0xe161, 0x0460, ++ 0x151a, 0xa80f, 0xe095, 0xe41e, 0x137e, 0xb670, 0x4e44, 0xe161, ++ 0x04cc, 0x151a, 0xaf07, 0xa80f, 0xe095, 0xe41e, 0x137e, 0xa27f, ++ 0xb611, 0x4f4a, 0x1443, 0xe42b, 0xe42a, 0x502c, 0x4e4a, 0xe42e, ++ 0x1443, 0xf178, 0x1470, 0x1549, 0xf098, 0xf05b, 0xe41e, 0x1494, ++ 0xba40, 0x4e48, 0xa200, 0x4e4a, 0xe42e, 0xf03b, 0xba40, 0x4e48, ++ 0x502c, 0x4e4a, 0xe41e, 0x1494, 0xa202, 0xe41e, 0x14d0, 0xe42e, ++ 0x1449, 0x264a, 0xe418, 0x1494, 0x1449, 0xe418, 0x0afc, 0xf03a, ++ 0xba40, 0x4e48, 0x144a, 0xe41e, 0x14d0, 0xe42e, 0x1519, 0xe04a, ++ 0xaf0a, 0xa83e, 0x4e45, 0xe04a, 0xaf16, 0xa802, 0x4e46, 0xe04a, ++ 0xaf14, 0xa802, 0x4e47, 0xe42e, 0x8a18, 0x0007, 0xe42c, 0x1418, ++ 0xaf0a, 0xa806, 0xa106, 0xf15a, 0xa200, 0x1540, 0xb496, 0x0d15, ++ 0xa003, 0xb436, 0xae02, 0x1541, 0xb496, 0x0d16, 0xa003, 0xb436, ++ 0x2218, 0xe42a, 0x1419, 0xa83e, 0x4e45, 0xa200, 0x4e46, 0xe42e, ++ 0x8a18, 0x0004, 0xf09c, 0xba40, 0xe42a, 0x1419, 0xa83e, 0x4e45, ++ 0xa200, 0x4e46, 0xe42e, 0xba45, 0xe04a, 0xa10f, 0x0445, 0xf029, ++ 0xba48, 0x4e45, 0xa200, 0x4e46, 0xe42e, 0x1417, 0xaf0e, 0xa802, ++ 0x4e4d, 0x1417, 0xaf08, 0xa806, 0x4e4c, 0xa200, 0x4e4e, 0xe42e, ++ 0x8a17, 0x0007, 0x1549, 0xe015, 0xe051, 0xe42d, 0xe42b, 0x512b, ++ 0xe04a, 0xaf06, 0x4e4d, 0xa80f, 0xae03, 0x4f6e, 0xe004, 0xea54, ++ 0x366e, 0xa806, 0x4e4c, 0xae03, 0x4f6e, 0xe004, 0x0a82, 0xae20, ++ 0xe00a, 0xa828, 0x366e, 0xa81e, 0x4e4e, 0xe42e, 0xa200, 0x1545, ++ 0xa103, 0xb456, 0xa103, 0xb436, 0x4e74, 0xa010, 0x4e73, 0xe166, ++ 0x056c, 0xe167, 0x0572, 0xa200, 0xc705, 0x4e96, 0xc705, 0x4e97, ++ 0xa200, 0x4e75, 0xe162, 0x0566, 0x1430, 0xe096, 0x1432, 0xe098, ++ 0xa202, 0x4e4b, 0xd022, 0x0003, 0xe184, 0x151c, 0x1475, 0xce90, ++ 0xd140, 0x0000, 0xe41e, 0x15cc, 0xe008, 0x0fff, 0xce82, 0x1492, ++ 0xe418, 0x15e5, 0x1475, 0xa002, 0x4e75, 0x1430, 0xa004, 0xe096, ++ 0x1431, 0xa008, 0xe098, 0xd022, 0x0001, 0xe184, 0x1535, 0x1475, ++ 0xce90, 0xd140, 0x0000, 0xe41e, 0x15cc, 0xe008, 0x0fff, 0xce82, ++ 0x1492, 0xe418, 0x15e5, 0x1475, 0xa002, 0x4e75, 0xe42e, 0xa200, ++ 0x1545, 0xa103, 0xb456, 0xa103, 0xb436, 0x4e74, 0xa010, 0x4e73, ++ 0xe166, 0x056c, 0xe167, 0x0572, 0xa200, 0xc705, 0x4e96, 0xc705, ++ 0x4e97, 0xa200, 0x4e75, 0xe161, 0x0560, 0xe162, 0x0566, 0xe166, ++ 0x056c, 0xe167, 0x0572, 0x1430, 0xe096, 0x1431, 0xe098, 0xa008, ++ 0xe09a, 0xa202, 0x4e4b, 0xd022, 0x0003, 0xe184, 0x158f, 0x1475, ++ 0xce90, 0x1491, 0x1582, 0xf0ca, 0xd140, 0x0000, 0xe41e, 0x15cc, ++ 0x1582, 0xe008, 0x0fff, 0xce82, 0xe419, 0x15e5, 0xf1ce, 0xf1bb, ++ 0xe41e, 0x1669, 0x8a87, 0x0003, 0xd140, 0x0000, 0xe41d, 0x1627, ++ 0x8a87, 0x0002, 0xd140, 0x0010, 0xe41d, 0x1627, 0x8a87, 0x0001, ++ 0xd140, 0x0020, 0xe41d, 0x1627, 0x8a87, 0x0000, 0xd140, 0x0030, ++ 0xe41d, 0x1627, 0x8092, 0x8096, 0x8097, 0x1475, 0xa002, 0x4e75, ++ 0x1430, 0xa004, 0xe096, 0x1431, 0xa008, 0xe098, 0xd022, 0x0001, ++ 0xe184, 0x15ca, 0x1475, 0xce90, 0x1491, 0x1582, 0xf0ca, 0xd140, ++ 0x0000, 0xe41e, 0x15cc, 0x1582, 0xe008, 0x0fff, 0xce82, 0xe419, ++ 0x15e5, 0xf1ce, 0xf1bb, 0xe41e, 0x1669, 0x8a87, 0x0003, 0xd140, ++ 0x0000, 0xe41d, 0x15e5, 0x8a87, 0x0002, 0xd140, 0x0010, 0xe41d, ++ 0x15e5, 0x8a87, 0x0001, 0xd140, 0x0020, 0xe41d, 0x15e5, 0x8a87, ++ 0x0000, 0xd140, 0x0030, 0xe41d, 0x15e5, 0x8092, 0x8096, 0x8097, ++ 0x1475, 0xa002, 0x4e75, 0xe42e, 0x9003, 0xe049, 0xa1ff, 0xe42a, ++ 0xf10b, 0x1574, 0xf059, 0xba41, 0xe42b, 0xe012, 0xe42e, 0xa102, ++ 0x3474, 0xa002, 0x5774, 0xe042, 0xba41, 0xe42b, 0xe012, 0xe42e, ++ 0x5673, 0xba41, 0xe42b, 0xe012, 0xe42e, 0x9004, 0xe049, 0xaf25, ++ 0xf04a, 0xce82, 0xf7bb, 0xe42e, 0xba40, 0xba01, 0xf038, 0xf0e9, ++ 0xf1ae, 0x9004, 0xe089, 0xa143, 0xcc91, 0xcc92, 0xe190, 0xc892, ++ 0xe049, 0xaf25, 0xce82, 0xf6ab, 0xe42e, 0xba40, 0x9004, 0xe089, ++ 0xa143, 0xcc91, 0xcc94, 0xe190, 0xc894, 0xe049, 0xaf25, 0xce82, ++ 0xf5db, 0xe42e, 0xba40, 0x1536, 0xba40, 0xae24, 0xf08b, 0xa201, ++ 0x4f36, 0x5137, 0x4f38, 0xba43, 0xa007, 0x4f39, 0x5739, 0xae19, ++ 0xe056, 0xba41, 0xf06b, 0x5738, 0xe013, 0xe009, 0x0fff, 0xf02e, ++ 0x5738, 0xe056, 0xe049, 0xaf25, 0xce82, 0xf40b, 0xe42e, 0x9005, ++ 0xe049, 0xaf25, 0xf04a, 0xce82, 0xf7bb, 0xe42e, 0xba40, 0xba01, ++ 0xf038, 0xf0e9, 0xf1ae, 0x9005, 0xe08b, 0xa143, 0xcc91, 0xcc92, ++ 0xe190, 0xc892, 0xe049, 0xaf25, 0xce82, 0xf6ab, 0xe42e, 0xba40, ++ 0x9005, 0xe08b, 0xa143, 0xcc91, 0xcc94, 0xe190, 0xc894, 0xe049, ++ 0xaf25, 0xce82, 0xf5db, 0xe42e, 0xba40, 0x1536, 0xba40, 0xae24, ++ 0xf08b, 0xa201, 0x4f36, 0x5137, 0x4f38, 0xba43, 0xa007, 0x4f39, ++ 0x5739, 0xae19, 0xe056, 0xba41, 0xf06b, 0x5738, 0xe013, 0xe009, ++ 0x0fff, 0xf02e, 0x5738, 0xe056, 0xe049, 0xaf25, 0xce82, 0xf40b, ++ 0xe42e, 0x144c, 0x154d, 0x274b, 0xb696, 0x4e86, 0x144e, 0x154b, ++ 0xb616, 0x4e87, 0xa200, 0x4e4b, 0x1486, 0xa108, 0x1587, 0xf148, ++ 0x502e, 0xae02, 0x4e6f, 0xe005, 0xea54, 0x376f, 0xa807, 0x4f86, ++ 0xae02, 0x4e6f, 0xe005, 0x0a82, 0xae21, 0xe00b, 0xa828, 0x376f, ++ 0xa81f, 0x4f87, 0x1486, 0xe429, 0x1486, 0xa211, 0xf0aa, 0x142f, ++ 0x1586, 0xa107, 0xb612, 0xe000, 0x000f, 0x0486, 0xe090, 0x9080, ++ 0x4f87, 0xe42e, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe0c0, 0x0040, 0xe0c1, 0x005b, 0xae1d, 0xe042, 0xce20, 0xd111, ++ 0x0000, 0xd112, 0x0800, 0xd113, 0x000b, 0xca28, 0xf7f8, 0xe42e, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0x0080, 0x0055, 0x00aa, 0x0040, 0x00c0, 0x0033, 0x0066, 0x0099, ++ 0x00cc, 0x002b, 0x00d7, 0x0025, 0x004a, 0x006f, 0x0094, 0x00b9, ++ 0x00de, 0x0020, 0x0060, 0x00a0, 0x00e0, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++ 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, ++}; +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc.c linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc.c +--- linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc.c 2009-10-21 16:06:52.000000000 +0200 +@@ -0,0 +1,969 @@ ++/* linux/driver/media/video/mfc/s3c_mfc.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++ ++#ifdef CONFIG_S3C6400_PDFW ++#include ++#if defined(CONFIG_S3C6400_KDPMD) || defined(CONFIG_S3C6400_KDPMD_MODULE) ++#include ++#endif ++#endif ++ ++#define S3C_MFC_PHYS_BUFFER_SET ++ ++#include "s3c_mfc_base.h" ++#include "s3c_mfc_config.h" ++#include "s3c_mfc_init_hw.h" ++#include "s3c_mfc_instance.h" ++#include "s3c_mfc_inst_pool.h" ++#include "s3c_mfc.h" ++#include "s3c_mfc_yuv_buf_manager.h" ++#include "s3c_mfc_databuf.h" ++#include "s3c_mfc_sfr.h" ++#include "s3c_mfc_intr_noti.h" ++#include "s3c_mfc_params.h" ++ ++static struct clk *s3c_mfc_hclk; ++static struct clk *s3c_mfc_sclk; ++static struct clk *s3c_mfc_pclk; ++ ++static int s3c_mfc_openhandle_count = 0; ++ ++static struct mutex *s3c_mfc_mutex = NULL; ++unsigned int s3c_mfc_intr_type = 0; ++ ++#define S3C_MFC_SAVE_START_ADDR 0x100 ++#define S3C_MFC_SAVE_END_ADDR 0x200 ++static unsigned int s3c_mfc_save[S3C_MFC_SAVE_END_ADDR - S3C_MFC_SAVE_START_ADDR]; ++ ++extern int s3c_mfc_get_config_params(s3c_mfc_inst_context_t *pMfcInst, s3c_mfc_args_t *args); ++extern int s3c_mfc_set_config_params(s3c_mfc_inst_context_t *pMfcInst, s3c_mfc_args_t *args); ++ ++typedef struct _MFC_HANDLE { ++ s3c_mfc_inst_context_t *mfc_inst; ++ ++#if (defined(DIVX_ENABLE) && (DIVX_ENABLE == 1)) ++ unsigned char *pMV; ++ unsigned char *pMBType; ++#endif ++} s3c_mfc_handle_t; ++ ++ ++#ifdef CONFIG_S3C6400_PDFW ++int s3c_mfc_before_pdoff(void) ++{ ++ mfc_debug("mfc context saving before pdoff\n"); ++ return 0; ++} ++ ++int s3c_mfc_after_pdon(void) ++{ ++ mfc_debug("mfc initialization after pdon\n"); ++ return 0; ++} ++ ++struct pm_devtype s3c_mfc_pmdev = { ++ name: "mfc", ++ state: DEV_IDLE, ++ before_pdoff: s3c_mfc_before_pdoff, ++ after_pdon: s3c_mfc_after_pdon, ++}; ++#endif ++ ++ ++DECLARE_WAIT_QUEUE_HEAD(s3c_mfc_wait_queue); ++ ++static struct resource *s3c_mfc_mem; ++void __iomem *s3c_mfc_sfr_base_virt_addr; ++ ++dma_addr_t s3c_mfc_phys_buffer; ++ ++static irqreturn_t s3c_mfc_irq(int irq, void *dev_id) ++{ ++ unsigned int intReason; ++ s3c_mfc_inst_context_t *pMfcInst; ++ ++ ++ pMfcInst = (s3c_mfc_inst_context_t *)dev_id; ++ ++ intReason = s3c_mfc_intr_reason(); ++ ++ /* if PIC_RUN, buffer full and buffer empty interrupt */ ++ if (intReason & S3C_MFC_INTR_ENABLE_RESET) { ++ s3c_mfc_intr_type = intReason; ++ wake_up_interruptible(&s3c_mfc_wait_queue); ++ } ++ ++ s3c_mfc_clear_intr(); ++ ++ return IRQ_HANDLED; ++} ++ ++static int s3c_mfc_open(struct inode *inode, struct file *file) ++{ ++ s3c_mfc_handle_t *handle; ++ ++ /* ++ * Mutex Lock ++ */ ++ mutex_lock(s3c_mfc_mutex); ++ ++ clk_enable(s3c_mfc_hclk); ++ clk_enable(s3c_mfc_sclk); ++ clk_enable(s3c_mfc_pclk); ++ ++ s3c_mfc_openhandle_count++; ++ if (s3c_mfc_openhandle_count == 1) { ++#if defined(CONFIG_S3C6400_KDPMD) || defined(CONFIG_S3C6400_KDPMD_MODULE) ++ kdpmd_set_event(s3c_mfc_pmdev.devid, KDPMD_DRVOPEN); ++ kdpmd_wakeup(); ++ kdpmd_wait(s3c_mfc_pmdev.devid); ++ s3c_mfc_pmdev.state = DEV_RUNNING; ++ mfc_debug("mfc_open woke up\n"); ++#endif ++ ++ /* ++ * 3. MFC Hardware Initialization ++ */ ++ if (s3c_mfc_init_hw() == FALSE) ++ return -ENODEV; ++ } ++ ++ ++ handle = (s3c_mfc_handle_t *)kmalloc(sizeof(s3c_mfc_handle_t), GFP_KERNEL); ++ if (!handle) { ++ mfc_debug("mfc open error\n"); ++ mutex_unlock(s3c_mfc_mutex); ++ return -ENOMEM; ++ } ++ memset(handle, 0, sizeof(s3c_mfc_handle_t)); ++ ++ ++ /* ++ * MFC Instance creation ++ */ ++ handle->mfc_inst = s3c_mfc_inst_create(); ++ if (handle->mfc_inst == NULL) { ++ mfc_err("fail to mfc instance allocation\n"); ++ mutex_unlock(s3c_mfc_mutex); ++ return -EPERM; ++ } ++ ++ /* ++ * MFC supports multi-instance. so each instance have own data structure ++ * It saves file->private_data ++ */ ++ file->private_data = (s3c_mfc_handle_t *)handle; ++ ++ mutex_unlock(s3c_mfc_mutex); ++ ++ mfc_debug("mfc open success\n"); ++ ++ return 0; ++} ++ ++ ++static int s3c_mfc_release(struct inode *inode, struct file *file) ++{ ++ s3c_mfc_handle_t *handle = NULL; ++ ++ mutex_lock(s3c_mfc_mutex); ++ ++ handle = (s3c_mfc_handle_t *)file->private_data; ++ if (handle->mfc_inst == NULL) { ++ mutex_unlock(s3c_mfc_mutex); ++ return -EPERM; ++ }; ++ ++ mfc_debug("deleting instance number = %d\n", handle->mfc_inst->inst_no); ++ ++ s3c_mfc_inst_del(handle->mfc_inst); ++ ++ s3c_mfc_openhandle_count--; ++ if (s3c_mfc_openhandle_count == 0) { ++ ++#if defined(CONFIG_S3C6400_KDPMD) || defined(CONFIG_S3C6400_KDPMD_MODULE) ++ s3c_mfc_pmdev.state = DEV_IDLE; ++ kdpmd_set_event(s3c_mfc_pmdev.devid, KDPMD_DRVCLOSE); ++ kdpmd_wakeup(); ++ kdpmd_wait(s3c_mfc_pmdev.devid); ++#endif ++ ++ clk_disable(s3c_mfc_hclk); ++ clk_disable(s3c_mfc_sclk); ++ clk_disable(s3c_mfc_pclk); ++ } ++ ++ mutex_unlock(s3c_mfc_mutex); ++ ++ return 0; ++} ++ ++ ++static ssize_t s3c_mfc_write(struct file *file, const char *buf, size_t count, loff_t *pos) ++{ ++ return 0; ++} ++ ++static ssize_t s3c_mfc_read(struct file *file, char *buf, size_t count, loff_t *pos) ++{ ++ return 0; ++} ++ ++static int s3c_mfc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ int ret = 0; ++ int buf_size; ++ int nStrmLen, nHdrLen; ++ int out; ++ int yuv_size; ++ int size; ++ ++ void *temp; ++ unsigned int vir_mv_addr; ++ unsigned int vir_mb_type_addr; ++ unsigned int tmp; ++ unsigned int in_usr_data, yuv_buffer, run_index, out_buf_size, databuf_vaddr, offset; ++ unsigned int yuv_buff_cnt, databuf_paddr; ++ unsigned char *OutBuf = NULL; ++ unsigned char *start, *end; ++ ++ s3c_mfc_inst_context_t *pMfcInst; ++ s3c_mfc_handle_t *handle; ++ s3c_mfc_codec_mode_t codec_mode = 0; ++ s3c_mfc_args_t args; ++ s3c_mfc_enc_info_t enc_info; ++ ++ /* ++ * Parameter Check ++ */ ++ handle = (s3c_mfc_handle_t *)file->private_data; ++ if (handle->mfc_inst == NULL) { ++ return -EFAULT; ++ } ++ ++ pMfcInst = handle->mfc_inst; ++ ++ switch (cmd) { ++ case S3C_MFC_IOCTL_MFC_MPEG4_ENC_INIT: ++ case S3C_MFC_IOCTL_MFC_H264_ENC_INIT: ++ case S3C_MFC_IOCTL_MFC_H263_ENC_INIT: ++ mutex_lock(s3c_mfc_mutex); ++ ++ mfc_debug("cmd = %d\n", cmd); ++ ++ out = copy_from_user(&args.enc_init, (s3c_mfc_enc_init_arg_t *)arg, ++ sizeof(s3c_mfc_enc_init_arg_t)); ++ ++ if ( cmd == S3C_MFC_IOCTL_MFC_MPEG4_ENC_INIT ) ++ codec_mode = MP4_ENC; ++ else if ( cmd == S3C_MFC_IOCTL_MFC_H264_ENC_INIT ) ++ codec_mode = AVC_ENC; ++ else if ( cmd == S3C_MFC_IOCTL_MFC_H263_ENC_INIT ) ++ codec_mode = H263_ENC; ++ ++ /* ++ * Initialize MFC Instance ++ */ ++ enc_info.width = args.enc_init.in_width; ++ enc_info.height = args.enc_init.in_height; ++ enc_info.bitrate = args.enc_init.in_bitrate; ++ enc_info.gop_number = args.enc_init.in_gopNum; ++ enc_info.frame_rate_residual = args.enc_init.in_frameRateRes; ++ enc_info.frame_rate_division = args.enc_init.in_frameRateDiv; ++ ++ /* ++ enc_info.intraqp = args.enc_init.in_intraqp; ++ enc_info.qpmax = args.enc_init.in_qpmax; ++ enc_info.gamma = args.enc_init.in_gamma; ++ */ ++ ++ ret = s3c_mfc_instance_init_enc(pMfcInst, codec_mode, &enc_info); ++ ++ args.enc_init.ret_code = ret; ++ out = copy_to_user((s3c_mfc_enc_init_arg_t *)arg, &args.enc_init, ++ sizeof(s3c_mfc_enc_init_arg_t)); ++ ++ mutex_unlock(s3c_mfc_mutex); ++ break; ++ ++ case S3C_MFC_IOCTL_MFC_MPEG4_ENC_EXE: ++ case S3C_MFC_IOCTL_MFC_H264_ENC_EXE: ++ case S3C_MFC_IOCTL_MFC_H263_ENC_EXE: ++ mutex_lock(s3c_mfc_mutex); ++ ++ out = copy_from_user(&args.enc_exe, (s3c_mfc_enc_exe_arg_t *)arg, ++ sizeof(s3c_mfc_enc_exe_arg_t)); ++ ++ tmp = (pMfcInst->width * pMfcInst->height * 3) >> 1; ++ ++ start = pMfcInst->yuv_buffer; ++ size = tmp * pMfcInst->yuv_buffer_count; ++ dma_cache_maint(start, size, DMA_TO_DEVICE); ++ ++ /* ++ * Encode MFC Instance ++ */ ++ ret = s3c_mfc_inst_enc(pMfcInst, &nStrmLen, &nHdrLen); ++ ++ start = pMfcInst->stream_buffer; ++ size = pMfcInst->stream_buffer_size; ++ dma_cache_maint(start, size, DMA_FROM_DEVICE); ++ ++ args.enc_exe.ret_code = ret; ++ if (ret == S3C_MFC_INST_RET_OK) { ++ args.enc_exe.out_encoded_size = nStrmLen; ++ args.enc_exe.out_header_size = nHdrLen; ++ } ++ out = copy_to_user((s3c_mfc_enc_exe_arg_t *)arg, &args.enc_exe, ++ sizeof(s3c_mfc_enc_exe_arg_t)); ++ ++ mutex_unlock(s3c_mfc_mutex); ++ break; ++ ++ case S3C_MFC_IOCTL_MFC_MPEG4_DEC_INIT: ++ case S3C_MFC_IOCTL_MFC_H264_DEC_INIT: ++ case S3C_MFC_IOCTL_MFC_H263_DEC_INIT: ++ case S3C_MFC_IOCTL_MFC_VC1_DEC_INIT: ++ mutex_lock(s3c_mfc_mutex); ++ ++ out = copy_from_user(&args.dec_init, (s3c_mfc_dec_init_arg_t *)arg, ++ sizeof(s3c_mfc_dec_init_arg_t)); ++ ++ if ( cmd == S3C_MFC_IOCTL_MFC_MPEG4_DEC_INIT ) ++ codec_mode = MP4_DEC; ++ else if ( cmd == S3C_MFC_IOCTL_MFC_H264_DEC_INIT ) ++ codec_mode = AVC_DEC; ++ else if ( cmd == S3C_MFC_IOCTL_MFC_H263_DEC_INIT) ++ codec_mode = H263_DEC; ++ else { ++ codec_mode = VC1_DEC; ++ } ++ ++ /* ++ * Initialize MFC Instance ++ */ ++ ret = s3c_mfc_inst_init_dec(pMfcInst, codec_mode, ++ args.dec_init.in_strmSize); ++ ++ args.dec_init.ret_code = ret; ++ if (ret == S3C_MFC_INST_RET_OK) { ++ args.dec_init.out_width = pMfcInst->width; ++ args.dec_init.out_height = pMfcInst->height; ++ args.dec_init.out_buf_width = pMfcInst->buf_width; ++ args.dec_init.out_buf_height = pMfcInst->buf_height; ++ } ++ out = copy_to_user((s3c_mfc_dec_init_arg_t *)arg, &args.dec_init, ++ sizeof(s3c_mfc_dec_init_arg_t)); ++ ++ mutex_unlock(s3c_mfc_mutex); ++ break; ++ ++ case S3C_MFC_IOCTL_MFC_MPEG4_DEC_EXE: ++ case S3C_MFC_IOCTL_MFC_H264_DEC_EXE: ++ case S3C_MFC_IOCTL_MFC_H263_DEC_EXE: ++ case S3C_MFC_IOCTL_MFC_VC1_DEC_EXE: ++ mutex_lock(s3c_mfc_mutex); ++ ++ out = copy_from_user(&args.dec_exe, (s3c_mfc_dec_exe_arg_t *)arg, ++ sizeof(s3c_mfc_dec_exe_arg_t)); ++ ++ tmp = (pMfcInst->width * pMfcInst->height * 3) >> 1; ++ ++ start = pMfcInst->stream_buffer; ++ size = pMfcInst->stream_buffer_size; ++ dma_cache_maint(start, size, DMA_TO_DEVICE); ++ ++ ret = s3c_mfc_inst_dec(pMfcInst, args.dec_exe.in_strmSize); ++ ++ start = pMfcInst->yuv_buffer; ++ size = tmp * pMfcInst->yuv_buffer_count; ++ dma_cache_maint(start, size, DMA_FROM_DEVICE); ++ ++ args.dec_exe.ret_code = ret; ++ out = copy_to_user((s3c_mfc_dec_exe_arg_t *)arg, &args.dec_exe, ++ sizeof(s3c_mfc_dec_exe_arg_t)); ++ ++ mutex_unlock(s3c_mfc_mutex); ++ break; ++ ++ case S3C_MFC_IOCTL_MFC_GET_LINE_BUF_ADDR: ++ mutex_lock(s3c_mfc_mutex); ++ ++ out = copy_from_user(&args.get_buf_addr, ++ (s3c_mfc_get_buf_addr_arg_t *)arg, sizeof(s3c_mfc_get_buf_addr_arg_t)); ++ ++ ret = s3c_mfc_inst_get_line_buff(pMfcInst, &OutBuf, &buf_size); ++ ++ args.get_buf_addr.out_buf_size = buf_size; ++ args.get_buf_addr.out_buf_addr = args.get_buf_addr.in_usr_data + (OutBuf - s3c_mfc_get_databuf_virt_addr()); ++ args.get_buf_addr.ret_code = ret; ++ ++ out = copy_to_user((s3c_mfc_get_buf_addr_arg_t *)arg, ++ &args.get_buf_addr, sizeof(s3c_mfc_get_buf_addr_arg_t)); ++ ++ mutex_unlock(s3c_mfc_mutex); ++ break; ++ ++ case S3C_MFC_IOCTL_MFC_GET_YUV_BUF_ADDR: ++ mutex_lock(s3c_mfc_mutex); ++ ++ out = copy_from_user(&args.get_buf_addr, ++ (s3c_mfc_get_buf_addr_arg_t *)arg, ++ sizeof(s3c_mfc_get_buf_addr_arg_t)); ++ ++ if (pMfcInst->yuv_buffer == NULL) { ++ mfc_err("mfc frame buffer is not internally allocated yet\n"); ++ mutex_unlock(s3c_mfc_mutex); ++ return -EFAULT; ++ } ++ ++ /* FRAM_BUF address is calculated differently for Encoder and Decoder. */ ++ switch (pMfcInst->codec_mode) { ++ case MP4_DEC: ++ case AVC_DEC: ++ case VC1_DEC: ++ case H263_DEC: ++ /* Decoder case */ ++ yuv_size = (pMfcInst->buf_width * pMfcInst->buf_height * 3) >> 1; ++ args.get_buf_addr.out_buf_size = yuv_size; ++ ++ in_usr_data = (unsigned int)args.get_buf_addr.in_usr_data; ++ yuv_buffer = (unsigned int)pMfcInst->yuv_buffer; ++ run_index = pMfcInst->run_index; ++ out_buf_size = args.get_buf_addr.out_buf_size; ++ databuf_vaddr = (unsigned int)s3c_mfc_get_databuf_virt_addr(); ++ offset = yuv_buffer + run_index * out_buf_size - databuf_vaddr; ++ ++#if (S3C_MFC_ROTATE_ENABLE == 1) ++ if ((pMfcInst->codec_mode != VC1_DEC) && ++ (pMfcInst->post_rotation_mode & 0x0010)) { ++ yuv_buff_cnt = pMfcInst->yuv_buffer_count; ++ offset = yuv_buffer + yuv_buff_cnt * out_buf_size - databuf_vaddr; ++ } ++#endif ++ args.get_buf_addr.out_buf_addr = in_usr_data + offset; ++ break; ++ ++ case MP4_ENC: ++ case AVC_ENC: ++ case H263_ENC: ++ /* Encoder case */ ++ yuv_size = (pMfcInst->width * pMfcInst->height * 3) >> 1; ++ in_usr_data = args.get_buf_addr.in_usr_data; ++ run_index = pMfcInst->run_index; ++ yuv_buffer = (unsigned int)pMfcInst->yuv_buffer; ++ databuf_vaddr = (unsigned int)s3c_mfc_get_databuf_virt_addr(); ++ offset = run_index * yuv_size + (yuv_buffer - databuf_vaddr); ++ ++ args.get_buf_addr.out_buf_addr = in_usr_data + offset; ++ break; ++ } /* end of switch (codec_mode) */ ++ ++ args.get_buf_addr.ret_code = S3C_MFC_INST_RET_OK; ++ out = copy_to_user((s3c_mfc_get_buf_addr_arg_t *)arg, &args.get_buf_addr, sizeof(s3c_mfc_get_buf_addr_arg_t)); ++ ++ mutex_unlock(s3c_mfc_mutex); ++ break; ++ ++ case S3C_MFC_IOCTL_MFC_GET_PHY_FRAM_BUF_ADDR: ++ mutex_lock(s3c_mfc_mutex); ++ ++ out = copy_from_user(&args.get_buf_addr, ++ (s3c_mfc_get_buf_addr_arg_t *)arg, ++ sizeof(s3c_mfc_get_buf_addr_arg_t)); ++ ++ yuv_size = (pMfcInst->buf_width * pMfcInst->buf_height * 3) >> 1; ++ args.get_buf_addr.out_buf_size = yuv_size; ++ yuv_buffer = (unsigned int)pMfcInst->yuv_buffer; ++ run_index = pMfcInst->run_index; ++ out_buf_size = args.get_buf_addr.out_buf_size; ++ databuf_vaddr = (unsigned int)s3c_mfc_get_databuf_virt_addr(); ++ databuf_paddr = (unsigned int)S3C_MFC_BASEADDR_DATA_BUF; ++ offset = yuv_buffer + run_index * out_buf_size - databuf_vaddr; ++ ++#if (S3C_MFC_ROTATE_ENABLE == 1) ++ if ((pMfcInst->codec_mode != VC1_DEC) && (pMfcInst->post_rotation_mode & 0x0010)) { ++ yuv_buff_cnt = pMfcInst->yuv_buffer_count; ++ offset = yuv_buffer + yuv_buff_cnt * out_buf_size - databuf_vaddr; ++ } ++#endif ++ args.get_buf_addr.out_buf_addr = databuf_paddr + offset; ++ args.get_buf_addr.ret_code = S3C_MFC_INST_RET_OK; ++ ++ out = copy_to_user((s3c_mfc_get_buf_addr_arg_t *)arg, ++ &args.get_buf_addr, sizeof(s3c_mfc_get_buf_addr_arg_t)); ++ ++ mutex_unlock(s3c_mfc_mutex); ++ break; ++ ++ case S3C_MFC_IOCTL_MFC_GET_MPEG4_ASP_PARAM: ++#if (defined(DIVX_ENABLE) && (DIVX_ENABLE == 1)) ++ ++ out = copy_from_user(&args.mpeg4_asp_param, (s3c_mfc_get_mpeg4asp_arg_t *)arg, \ ++ sizeof(s3c_mfc_get_mpeg4asp_arg_t)); ++ ++ ret = S3C_MFC_INST_RET_OK; ++ args.mpeg4_asp_param.ret_code = S3C_MFC_INST_RET_OK; ++ args.mpeg4_asp_param.mp4asp_vop_time_res = pMfcInst->RET_DEC_SEQ_INIT_BAK_MP4ASP_VOP_TIME_RES; ++ args.mpeg4_asp_param.byte_consumed = pMfcInst->RET_DEC_PIC_RUN_BAK_BYTE_CONSUMED; ++ args.mpeg4_asp_param.mp4asp_fcode = pMfcInst->RET_DEC_PIC_RUN_BAK_MP4ASP_FCODE; ++ args.mpeg4_asp_param.mp4asp_time_base_last = pMfcInst->RET_DEC_PIC_RUN_BAK_MP4ASP_TIME_BASE_LAST; ++ args.mpeg4_asp_param.mp4asp_nonb_time_last = pMfcInst->RET_DEC_PIC_RUN_BAK_MP4ASP_NONB_TIME_LAST; ++ args.mpeg4_asp_param.mp4asp_trd = pMfcInst->RET_DEC_PIC_RUN_BAK_MP4ASP_MP4ASP_TRD; ++ ++ args.mpeg4_asp_param.mv_addr = (args.mpeg4_asp_param.in_usr_mapped_addr + S3C_MFC_STREAM_BUF_SIZE) \ ++ + (pMfcInst->mv_mbyte_addr - pMfcInst->phys_addr_yuv_buffer); ++ args.mpeg4_asp_param.mb_type_addr = args.mpeg4_asp_param.mv_addr + S3C_MFC_MAX_MV_SIZE; ++ args.mpeg4_asp_param.mv_size = S3C_MFC_MAX_MV_SIZE; ++ args.mpeg4_asp_param.mb_type_size = S3C_MFC_MAX_MBYTE_SIZE; ++ ++ vir_mv_addr = (unsigned int)((pMfcInst->stream_buffer + S3C_MFC_STREAM_BUF_SIZE) + \ ++ (pMfcInst->mv_mbyte_addr - pMfcInst->phys_addr_yuv_buffer)); ++ vir_mb_type_addr = vir_mv_addr + S3C_MFC_MAX_MV_SIZE; ++ ++ out = copy_to_user((s3c_mfc_get_mpeg4asp_arg_t *)arg, &args.mpeg4_asp_param, \ ++ sizeof(s3c_mfc_get_mpeg4asp_arg_t)); ++#endif ++ break; ++ ++ case S3C_MFC_IOCTL_MFC_GET_CONFIG: ++ mutex_lock(s3c_mfc_mutex); ++ ++ out = copy_from_user(&args, (s3c_mfc_args_t *)arg, sizeof(s3c_mfc_args_t)); ++ ++ ret = s3c_mfc_get_config_params(pMfcInst, &args); ++ ++ out = copy_to_user((s3c_mfc_args_t *)arg, &args, sizeof(s3c_mfc_args_t)); ++ ++ mutex_unlock(s3c_mfc_mutex); ++ break; ++ ++ case S3C_MFC_IOCTL_MFC_SET_CONFIG: ++ mutex_lock(s3c_mfc_mutex); ++ ++ out = copy_from_user(&args, (s3c_mfc_args_t *)arg, sizeof(s3c_mfc_args_t)); ++ ++ ret = s3c_mfc_set_config_params(pMfcInst, &args); ++ ++ out = copy_to_user((s3c_mfc_args_t *)arg, &args, sizeof(s3c_mfc_args_t)); ++ ++ mutex_unlock(s3c_mfc_mutex); ++ break; ++ ++ case S3C_MFC_IOCTL_VIRT_TO_PHYS: ++ temp = __virt_to_phys((void *)arg); ++ return (int)temp; ++ break; ++ ++ default: ++ mutex_lock(s3c_mfc_mutex); ++ mfc_debug("requested ioctl command is not defined (ioctl cmd = 0x%x)\n", cmd); ++ mutex_unlock(s3c_mfc_mutex); ++ return -ENOIOCTLCMD; ++ } ++ ++ switch (ret) { ++ case S3C_MFC_INST_RET_OK: ++ return 0; ++ default: ++ return -EPERM; ++ } ++ return -EPERM; ++} ++ ++int s3c_mfc_mmap(struct file *filp, struct vm_area_struct *vma) ++{ ++ unsigned long size = vma->vm_end - vma->vm_start; ++ unsigned long maxSize; ++ unsigned long pageFrameNo; ++ ++ pageFrameNo = __phys_to_pfn(S3C_MFC_BASEADDR_DATA_BUF); ++ ++ maxSize = S3C_MFC_DATA_BUF_SIZE + PAGE_SIZE - (S3C_MFC_DATA_BUF_SIZE % PAGE_SIZE); ++ ++ if (size > maxSize) { ++ return -EINVAL; ++ } ++ ++ vma->vm_flags |= VM_RESERVED | VM_IO; ++ ++ /* nocached setup. ++ * vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ */ ++ ++ if (remap_pfn_range(vma, vma->vm_start, pageFrameNo, size, vma->vm_page_prot)) { ++ mfc_err("fail to remap\n"); ++ return -EAGAIN; ++ } ++ ++ return 0; ++} ++ ++ ++static struct file_operations s3c_mfc_fops = { ++ owner: THIS_MODULE, ++ open: s3c_mfc_open, ++ release: s3c_mfc_release, ++ ioctl: s3c_mfc_ioctl, ++ read: s3c_mfc_read, ++ write: s3c_mfc_write, ++ mmap: s3c_mfc_mmap, ++}; ++ ++ ++static struct miscdevice s3c_mfc_miscdev = { ++ minor: 252, ++ name: "s3c-mfc", ++ fops: &s3c_mfc_fops ++}; ++ ++static BOOL s3c_mfc_setup_clock(void) ++{ ++ unsigned int mfc_clk; ++ ++ /* mfc clock set 133 Mhz */ ++ mfc_clk = readl(S3C_CLK_DIV0); ++ mfc_clk |= (1 << 28); ++ __raw_writel(mfc_clk, S3C_CLK_DIV0); ++ ++ return TRUE; ++ ++} ++ ++static int s3c_mfc_probe(struct platform_device *pdev) ++{ ++ int size; ++ int ret; ++ struct resource *res; ++ unsigned int mfc_clk; ++ ++ /* mfc clock enable */ ++ s3c_mfc_hclk = clk_get(&pdev->dev, "hclk_mfc"); ++ if (!s3c_mfc_hclk || IS_ERR(s3c_mfc_hclk)) { ++ mfc_err("failed to get mfc hclk source\n"); ++ return -ENOENT; ++ } ++ clk_enable(s3c_mfc_hclk); ++ ++ s3c_mfc_sclk = clk_get(&pdev->dev, "sclk_mfc"); ++ if (!s3c_mfc_sclk || IS_ERR(s3c_mfc_sclk)) { ++ mfc_err("failed to get mfc sclk source\n"); ++ return -ENOENT; ++ } ++ clk_enable(s3c_mfc_sclk); ++ ++ s3c_mfc_pclk = clk_get(&pdev->dev, "pclk_mfc"); ++ if (!s3c_mfc_pclk || IS_ERR(s3c_mfc_pclk)) { ++ mfc_err("failed to get mfc pclk source\n"); ++ return -ENOENT; ++ } ++ clk_enable(s3c_mfc_pclk); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (res == NULL) { ++ mfc_err("failed to get memory region resouce\n"); ++ return -ENOENT; ++ } ++ ++ size = (res->end-res->start)+1; ++ s3c_mfc_mem = request_mem_region(res->start, size, pdev->name); ++ if (s3c_mfc_mem == NULL) { ++ mfc_err("failed to get memory region\n"); ++ return -ENOENT; ++ } ++ ++ s3c_mfc_sfr_base_virt_addr = ioremap_nocache(res->start, size); ++ if (s3c_mfc_sfr_base_virt_addr == 0) { ++ mfc_err("failed to ioremap() region\n"); ++ return -EINVAL; ++ } ++ ++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (res == NULL) { ++ mfc_err("failed to get irq resource\n"); ++ return -ENOENT; ++ } ++ ++ ret = request_irq(res->start, s3c_mfc_irq, IRQF_DISABLED, pdev->name, pdev); ++ if (ret != 0) { ++ mfc_err("failed to install irq (%d)\n", ret); ++ return ret; ++ } ++ ++ s3c_mfc_phys_buffer = s3c_get_media_memory(S3C_MDEV_MFC); ++ ++ /* mutex creation and initialization */ ++ s3c_mfc_mutex = (struct mutex *)kmalloc(sizeof(struct mutex), GFP_KERNEL); ++ if (s3c_mfc_mutex == NULL) ++ return -ENOMEM; ++ ++ mutex_init(s3c_mfc_mutex); ++ ++ /* mfc clock set 133 Mhz */ ++ if (s3c_mfc_setup_clock() == FALSE) ++ return -ENODEV; ++ ++ /* ++ * 2. MFC Memory Setup ++ */ ++ if (s3c_mfc_setup_memory() == FALSE) ++ return -ENOMEM; ++ ++ /* ++ * 3. MFC Hardware Initialization ++ */ ++ if (s3c_mfc_init_hw() == FALSE) ++ return -ENODEV; ++ ++ ret = misc_register(&s3c_mfc_miscdev); ++ ++ clk_disable(s3c_mfc_hclk); ++ clk_disable(s3c_mfc_sclk); ++ clk_disable(s3c_mfc_pclk); ++ ++ return 0; ++} ++ ++static int s3c_mfc_remove(struct platform_device *dev) ++{ ++ if (s3c_mfc_mem != NULL) { ++ release_resource(s3c_mfc_mem); ++ kfree(s3c_mfc_mem); ++ s3c_mfc_mem = NULL; ++ } ++ ++ free_irq(IRQ_MFC, dev); ++ ++ misc_deregister(&s3c_mfc_miscdev); ++ return 0; ++} ++ ++static int s3c_mfc_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ ++ int inst_no; ++ int is_mfc_on = 0; ++ int i, index = 0; ++ ++ s3c_mfc_inst_context_t *mfcinst_ctx; ++ unsigned int dwMfcBase; ++ ++ mutex_lock(s3c_mfc_mutex); ++ ++ is_mfc_on = 0; ++ ++ /* ++ * 1. Power Off state ++ * Invalidate all the MFC Instances ++ */ ++ for (inst_no = 0; inst_no < S3C_MFC_NUM_INSTANCES_MAX; inst_no++) { ++ mfcinst_ctx = s3c_mfc_inst_get_context(inst_no); ++ if (mfcinst_ctx) { ++ is_mfc_on = 1; ++ ++ /* ++ * On Power Down, the MFC instance is invalidated. ++ * Then the MFC operations (DEC_EXE, ENC_EXE, etc.) will not be performed ++ * until it is validated by entering Power up state transition ++ */ ++ s3c_mfc_inst_pow_off_state(mfcinst_ctx); ++ mfc_err("mfc suspend %d-th instance is invalidated\n", inst_no); ++ } ++ } ++ ++ /* 2. Command MFC sleep and save MFC SFR */ ++ if (is_mfc_on) { ++ dwMfcBase = s3c_mfc_sfr_base_virt_addr; ++ ++ for (i = S3C_MFC_SAVE_START_ADDR; i <= S3C_MFC_SAVE_END_ADDR; i += 4) { ++ s3c_mfc_save[index] = readl(dwMfcBase + i); ++ index++; ++ } ++ ++ s3c_mfc_sleep(); ++ } ++ ++ ++ /* 3. Disable MFC clock */ ++ clk_disable(s3c_mfc_hclk); ++ clk_disable(s3c_mfc_sclk); ++ clk_disable(s3c_mfc_pclk); ++ ++ mutex_unlock(s3c_mfc_mutex); ++ ++ return 0; ++} ++ ++static int s3c_mfc_resume(struct platform_device *pdev) ++{ ++ ++ int i, index = 0; ++ int inst_no; ++ int is_mfc_on = 0; ++ unsigned int mfc_pwr, dwMfcBase; ++ unsigned int domain_v_ready; ++ ++ s3c_mfc_inst_context_t *mfcinst_ctx; ++ ++ mutex_lock(s3c_mfc_mutex); ++ ++ clk_enable(s3c_mfc_hclk); ++ clk_enable(s3c_mfc_sclk); ++ clk_enable(s3c_mfc_pclk); ++ ++ /* 1. MFC Power On(Domain V) */ ++ mfc_pwr = readl(S3C_NORMAL_CFG); ++ mfc_pwr |= (1 << 9); ++ __raw_writel(mfc_pwr, S3C_NORMAL_CFG); ++ ++ /* 2. Check MFC power on */ ++ do { ++ domain_v_ready = readl(S3C_BLK_PWR_STAT); ++ mfc_debug("domain v ready = 0x%X\n", domain_v_ready); ++ msleep(1); ++ } while (!(domain_v_ready & (1 << 1))); ++ ++ /* 3. MFC clock set 133 Mhz */ ++ if (s3c_mfc_setup_clock() == FALSE) ++ return -ENODEV; ++ ++ /* 4. Firmware download */ ++ s3c_mfc_download_boot_firmware(); ++ ++ /* ++ * 5. Power On state ++ * Validate all the MFC Instances ++ */ ++ for (inst_no = 0; inst_no < S3C_MFC_NUM_INSTANCES_MAX; inst_no++) { ++ mfcinst_ctx = s3c_mfc_inst_get_context(inst_no); ++ if (mfcinst_ctx) { ++ is_mfc_on = 1; ++ ++ /* ++ * When MFC Power On, the MFC instance is validated. ++ * Then the MFC operations (DEC_EXE, ENC_EXE, etc.) will be performed again ++ */ ++ s3c_mfc_inst_pow_on_state(mfcinst_ctx); ++ mfc_debug("mfc resume %d-th instance is validated\n", inst_no); ++ } ++ } ++ ++ if (is_mfc_on) { ++ /* 5. Restore MFC SFR */ ++ dwMfcBase = s3c_mfc_sfr_base_virt_addr; ++ for (i = S3C_MFC_SAVE_START_ADDR; i <= S3C_MFC_SAVE_END_ADDR; i += 4 ) { ++ writel(s3c_mfc_save[index], dwMfcBase + i); ++ index++; ++ } ++ ++ /* 6. Command MFC wakeup */ ++ s3c_mfc_wakeup(); ++ } ++ ++ mutex_unlock(s3c_mfc_mutex); ++ ++ return 0; ++} ++ ++static struct platform_driver s3c_mfc_driver = { ++ .probe = s3c_mfc_probe, ++ .remove = s3c_mfc_remove, ++ .shutdown = NULL, ++ .suspend = s3c_mfc_suspend, ++ .resume = s3c_mfc_resume, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "s3c-mfc", ++ }, ++}; ++ ++ ++static char banner[] __initdata = "S3C6400 MFC Driver, (c) 2007 Samsung Electronics\n"; ++ ++static int __init s3c_mfc_init(void) ++{ ++ printk(banner); ++ ++#ifdef CONFIG_S3C6400_PDFW ++ pd_register_dev(&s3c_mfc_pmdev, "domain_v"); ++ mfc_info("mfc devid = %d\n", s3c_mfc_pmdev.devid); ++#endif ++ ++ if (platform_driver_register(&s3c_mfc_driver) != 0) { ++ mfc_err("fail to register platform device\n"); ++ return -EPERM; ++ } ++ ++ mfc_info("%s", banner); ++ ++ return 0; ++} ++ ++static void __exit s3c_mfc_exit(void) ++{ ++ mutex_destroy(s3c_mfc_mutex); ++ ++#ifdef CONFIG_S3C6400_PDFW ++ pd_unregister_dev(&s3c_mfc_pmdev); ++#endif ++ ++ platform_driver_unregister(&s3c_mfc_driver); ++ mfc_debug("S3C64XX MFC driver exit.\n"); ++} ++ ++ ++module_init(s3c_mfc_init); ++module_exit(s3c_mfc_exit); ++ ++MODULE_AUTHOR("Jiun, Yu"); ++MODULE_LICENSE("GPL"); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc.h linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc.h +--- linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,120 @@ ++/* linux/driver/media/video/mfc/s3c_mfc.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_MFC_H ++#define _S3C_MFC_H ++ ++#include ++#include ++ ++#define S3C_MFC_IOCTL_MFC_MPEG4_DEC_INIT (0x00800001) ++#define S3C_MFC_IOCTL_MFC_MPEG4_ENC_INIT (0x00800002) ++#define S3C_MFC_IOCTL_MFC_MPEG4_DEC_EXE (0x00800003) ++#define S3C_MFC_IOCTL_MFC_MPEG4_ENC_EXE (0x00800004) ++ ++#define S3C_MFC_IOCTL_MFC_H264_DEC_INIT (0x00800005) ++#define S3C_MFC_IOCTL_MFC_H264_ENC_INIT (0x00800006) ++#define S3C_MFC_IOCTL_MFC_H264_DEC_EXE (0x00800007) ++#define S3C_MFC_IOCTL_MFC_H264_ENC_EXE (0x00800008) ++ ++#define S3C_MFC_IOCTL_MFC_H263_DEC_INIT (0x00800009) ++#define S3C_MFC_IOCTL_MFC_H263_ENC_INIT (0x0080000A) ++#define S3C_MFC_IOCTL_MFC_H263_DEC_EXE (0x0080000B) ++#define S3C_MFC_IOCTL_MFC_H263_ENC_EXE (0x0080000C) ++ ++#define S3C_MFC_IOCTL_MFC_VC1_DEC_INIT (0x0080000D) ++#define S3C_MFC_IOCTL_MFC_VC1_DEC_EXE (0x0080000E) ++ ++#define S3C_MFC_IOCTL_MFC_GET_LINE_BUF_ADDR (0x0080000F) ++#define S3C_MFC_IOCTL_MFC_GET_RING_BUF_ADDR (0x00800010) ++#define S3C_MFC_IOCTL_MFC_GET_YUV_BUF_ADDR (0x00800011) ++#define S3C_MFC_IOCTL_MFC_GET_POST_BUF_ADDR (0x00800012) ++#define S3C_MFC_IOCTL_MFC_GET_PHY_FRAM_BUF_ADDR (0x00800013) ++#define S3C_MFC_IOCTL_MFC_GET_CONFIG (0x00800016) ++#define S3C_MFC_IOCTL_MFC_GET_MPEG4_ASP_PARAM (0x00800017) ++ ++#define S3C_MFC_IOCTL_MFC_SET_H263_MULTIPLE_SLICE (0x00800014) ++#define S3C_MFC_IOCTL_MFC_SET_CONFIG (0x00800015) ++ ++#define S3C_MFC_IOCTL_MFC_SET_DISP_CONFIG (0x00800111) ++#define S3C_MFC_IOCTL_MFC_GET_YUV_SIZE (0x00800112) ++#define S3C_MFC_IOCTL_MFC_SET_PP_DISP_SIZE (0x00800113) ++#define S3C_MFC_IOCTL_MFC_SET_DEC_INBUF_TYPE (0x00800114) ++ ++#define S3C_MFC_IOCTL_VIRT_TO_PHYS 0x12345678 ++ ++#if (defined(DIVX_ENABLE) && (DIVX_ENABLE == 1)) ++#define S3C_MFC_IOCTL_CACHE_FLUSH_B_YUV (0x00800115) ++#define S3C_MFC_IOCTL_MFC_GET_PHY_B_YUV_BUF_ADDR (0x00800116) ++#define S3C_MFC_IOCTL_MFC_GET_B_YUV_BUF_ADDR (0x00800117) ++#endif ++ ++typedef struct ++{ ++ int rotate; ++ int deblockenable; ++} s3c_mfc_decode_options_t; ++ ++#define S3C_MFC_DRV_RET_OK (0) ++#define S3C_MFC_DRV_RET_ERR_INVALID_PARAM (-1001) ++#define S3C_MFC_DRV_RET_ERR_HANDLE_INVALIDATED (-1004) ++#define S3C_MFC_DRV_RET_ERR_OTHERS (-9001) ++ ++/* '25920' is the maximum MV size (=45*36*16) */ ++#define S3C_MFC_MAX_MV_SIZE (45 * 36 * 16) ++/* '1620' is the maximum MBTYE size (=45*36*1) */ ++#define S3C_MFC_MAX_MBYTE_SIZE (45 * 36 * 1) ++ ++/* debug macros */ ++#define MFC_DEBUG(fmt, ...) \ ++ do { \ ++ printk(KERN_DEBUG \ ++ "%s: " fmt, __func__, ##__VA_ARGS__); \ ++ } while(0) ++ ++#define MFC_ERROR(fmt, ...) \ ++ do { \ ++ printk(KERN_ERR \ ++ "%s: " fmt, __func__, ##__VA_ARGS__); \ ++ } while (0) ++ ++#define MFC_NOTICE(fmt, ...) \ ++ do { \ ++ printk(KERN_NOTICE \ ++ "%s: " fmt, __func__, ##__VA_ARGS__); \ ++ } while (0) ++ ++#define MFC_INFO(fmt, ...) \ ++ do { \ ++ printk(KERN_INFO \ ++ fmt, ##__VA_ARGS__); \ ++ } while (0) ++ ++#define MFC_WARN(fmt, ...) \ ++ do { \ ++ printk(KERN_WARNING \ ++ fmt, ##__VA_ARGS__); \ ++ } while (0) ++ ++ ++#ifdef VIDEO_MFC_DEBUG ++#define mfc_debug(fmt, ...) MFC_DEBUG(fmt, ##__VA_ARGS__) ++#else ++#define mfc_debug(fmt, ...) ++#endif ++ ++#define mfc_err(fmt, ...) MFC_ERROR(fmt, ##__VA_ARGS__) ++#define mfc_notice(fmt, ...) MFC_NOTICE(fmt, ##__VA_ARGS__) ++#define mfc_info(fmt, ...) MFC_INFO(fmt, ##__VA_ARGS__) ++#define mfc_warn(fmt, ...) MFC_WARN(fmt, ##__VA_ARGS__) ++ ++#endif /* _S3C_MFC_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_base.h linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_base.h +--- linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_base.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_base.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,136 @@ ++/* linux/driver/media/video/mfc/s3c_mfc_base.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_MFC_BASE_H ++#define _S3C_MFC_BASE_H ++ ++ ++/* SDRAM buffer control options */ ++#define S3C_MFC_STREAM_ENDIAN_LITTLE (0<<0) ++#define S3C_MFC_STREAM_ENDIAN_BIG (1<<0) ++#define S3C_MFC_BUF_STATUS_FULL_EMPTY_CHECK_BIT (0<<1) ++#define S3C_MFC_BUF_STATUS_NO_CHECK_BIT (1<<1) ++ ++/* FRAME_BUF_CTRL (0x110) */ ++#define S3C_MFC_YUV_MEM_ENDIAN_LITTLE (0<<0) ++#define S3C_MFC_YUV_MEM_ENDIAN_BIG (1<<0) ++ ++/* ++ * PRiSM-CX Video Codec IP's Register ++ * V178 ++ */ ++ ++/* ++ * DEC_SEQ_INIT Parameter Register ++ * DEC_SEQ_OPTION (0x18c) ++ */ ++#define S3C_MFC_MP4_DBK_DISABLE (0<<0) ++#define S3C_MFC_MP4_DBK_ENABLE (1<<0) ++#define S3C_MFC_REORDER_DISABLE (0<<1) ++#define S3C_MFC_REORDER_ENABLE (1<<1) ++#define S3C_MFC_FILEPLAY_ENABLE (1<<2) ++#define S3C_MFC_FILEPLAY_DISABLE (0<<2) ++#define S3C_MFC_DYNBUFALLOC_ENABLE (1<<3) ++#define S3C_MFC_DYNBUFALLOC_DISABLE (0<<3) ++ ++/* ++ * ENC_SEQ_INIT Parameter Register ++ * ENC_SEQ_OPTION (0x188) ++ */ ++#define S3C_MFC_MB_BIT_REPORT_DISABLE (0<<0) ++#define S3C_MFC_MB_BIT_REPORT_ENABLE (1<<0) ++#define S3C_MFC_SLICE_INFO_REPORT_DISABLE (0<<1) ++#define S3C_MFC_SLICE_INFO_REPORT_ENABLE (1<<1) ++#define S3C_MFC_AUD_DISABLE (0<<2) ++#define S3C_MFC_AUD_ENABLE (1<<2) ++#define S3C_MFC_MB_QP_REPORT_DISABLE (0<<3) ++#define S3C_MFC_MB_QP_REPORT_ENBLE (1<<3) ++#define S3C_MFC_CONST_QP_DISABLE (0<<5) ++#define S3C_MFC_CONST_QP_ENBLE (1<<5) ++ ++/* ENC_SEQ_COD_STD (0x18C) */ ++#define S3C_MFC_MPEG4_ENCODE 0 ++#define S3C_MFC_H263_ENCODE 1 ++#define S3C_MFC_H264_ENCODE 2 ++ ++/* ENC_SEQ_MP4_PARA (0x198) */ ++#define S3C_MFC_DATA_PART_DISABLE (0<<0) ++#define S3C_MFC_DATA_PART_ENABLE (1<<0) ++ ++/* ENC_SEQ_263_PARA (0x19C) */ ++#define S3C_MFC_ANNEX_T_OFF (0<<0) ++#define S3C_MFC_ANNEX_T_ON (1<<0) ++#define S3C_MFC_ANNEX_K_OFF (0<<1) ++#define S3C_MFC_ANNEX_K_ON (1<<1) ++#define S3C_MFC_ANNEX_J_OFF (0<<2) ++#define S3C_MFC_ANNEX_J_ON (1<<2) ++#define S3C_MFC_ANNEX_I_OFF (0<<3) ++#define S3C_MFC_ANNEX_I_ON (1<<3) ++ ++/* ENC_SEQ_SLICE_MODE (0x1A4) */ ++#define S3C_MFC_SLICE_MODE_ONE (0<<0) ++#define S3C_MFC_SLICE_MODE_MULTIPLE (1<<0) ++ ++/* ENC_SEQ_RC_PARA (0x1AC) */ ++#define S3C_MFC_RC_DISABLE (0<<0) /* RC means rate control */ ++#define S3C_MFC_RC_ENABLE (1<<0) ++#define S3C_MFC_SKIP_DISABLE (1<<31) ++#define S3C_MFC_SKIP_ENABLE (0<<31) ++ ++/* ENC_SEQ_FMO (0x1B8) */ ++#define S3C_MFC_FMO_DISABLE (0<<0) ++#define S3C_MFC_FMO_ENABLE (1<<0) ++ ++/* ENC_SEQ_RC_OPTION (0x1C4) */ ++#define S3C_MFC_USER_QP_MAX_DISABLE (0<<0) ++#define S3C_MFC_USER_QP_MAX_ENABLE (1<<0) ++#define S3C_MFC_USE_GAMMA_DISABLE (0<<1) ++#define S3C_MFC_USE_GAMMA_ENABLE (1<<1) ++ ++ ++typedef enum __MFC_CODEC_MODE { ++ MP4_DEC = 0, ++ MP4_ENC = 1, ++ AVC_DEC = 2, ++ AVC_ENC = 3, ++ VC1_DEC = 4, ++ H263_DEC = 5, ++ H263_ENC = 6 ++} s3c_mfc_codec_mode_t; ++ ++typedef enum __MFC_COMMAND { ++ SEQ_INIT = 0x01, ++ SEQ_END = 0x02, ++ PIC_RUN = 0x03, ++ SET_FRAME_BUF = 0x04, ++ ENC_HEADER = 0x05, ++ ENC_PARA_SET = 0x06, ++ DEC_PARA_SET = 0x07, ++ ENC_PARAM_CHANGE = 0x09, ++ SLEEP = 0x0A, ++ WAKEUP = 0x0B, ++ GET_FW_VER = 0x0F ++} s3c_mfc_command_t; ++ ++/* ++ * Because SW_RESET register is located apart(address 0xe00), unlike other MFC_SFR registers, ++ * I have excluded it in S3C6400_MFC_SFR struct and defined relative address only. ++ * When do virtual memory mapping in setting up memory, we have to map until this SW_RESET register. ++ * ++ * #define S3C6400_MFC_SFR_SW_RESET_ADDR (0x0e00) ++ * #define S3C6400_MFC_SFR_SIZE (0x0e00) ++ */ ++ ++ ++#endif /* _S3C_MFC_BASE_H */ ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_bitproc_buf.c linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_bitproc_buf.c +--- linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_bitproc_buf.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_bitproc_buf.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,84 @@ ++/* linux/driver/media/video/mfc/s3c_mfc_bitproc_buf.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include "s3c_mfc_base.h" ++#include "s3c_mfc_bitproc_buf.h" ++#include "s3c_mfc_config.h" ++#include "prism_s.h" ++#include "s3c_mfc.h" ++ ++static volatile unsigned char *s3c_mfc_virt_bitproc_buff = NULL; ++static unsigned int s3c_mfc_phys_bitproc_buff = 0; ++ ++ ++BOOL s3c_mfc_memmap_bitproc_buff() ++{ ++ BOOL ret = FALSE; ++ ++ /* FIRWARE/WORKING/PARAMETER BUFFER <-- virtual bitprocessor buffer address mapping */ ++ s3c_mfc_virt_bitproc_buff = (volatile unsigned char *)ioremap_nocache(S3C_MFC_BASEADDR_BITPROC_BUF, \ ++ S3C_MFC_BITPROC_BUF_SIZE); ++ if (s3c_mfc_virt_bitproc_buff == NULL) { ++ mfc_err("fail to mapping bitprocessor buffer\n"); ++ return ret; ++ } ++ ++ /* Physical register address mapping */ ++ s3c_mfc_phys_bitproc_buff = S3C_MFC_BASEADDR_BITPROC_BUF; ++ ++ ret = TRUE; ++ ++ return ret; ++} ++ ++volatile unsigned char *s3c_mfc_get_bitproc_buff_virt_addr() ++{ ++ volatile unsigned char *pBitProcBuf; ++ ++ pBitProcBuf = s3c_mfc_virt_bitproc_buff; ++ ++ return pBitProcBuf; ++} ++ ++unsigned char *s3c_mfc_get_param_buff_virt_addr() ++{ ++ unsigned char *pParamBuf; ++ ++ pParamBuf = (unsigned char *)(s3c_mfc_virt_bitproc_buff + ++ S3C_MFC_CODE_BUF_SIZE + S3C_MFC_WORK_BUF_SIZE); ++ ++ return pParamBuf; ++} ++ ++void s3c_mfc_put_firmware_into_codebuff() ++{ ++ unsigned int i, j; ++ unsigned int data; ++ ++ unsigned int *uAddrFirmwareCode; ++ ++ uAddrFirmwareCode = (unsigned int *)s3c_mfc_virt_bitproc_buff; ++ ++ /* ++ * Putting the Boot & Firmware code into SDRAM ++ * Boot code(1KB) + Codec Firmware (79KB) ++ * ++ */ ++ for (i = j = 0 ; i < sizeof(s3c_mfc_bit_code) / sizeof(s3c_mfc_bit_code[0]); i += 2, j++) { ++ data = (s3c_mfc_bit_code[i] << 16) | s3c_mfc_bit_code[i + 1]; ++ ++ *(uAddrFirmwareCode + j) = data; ++ } ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_bitproc_buf.h linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_bitproc_buf.h +--- linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_bitproc_buf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_bitproc_buf.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,24 @@ ++/* linux/driver/media/video/mfc/s3c_mfc_bitproc_buf.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_MFC_BITPROC_BUF_H ++#define _S3C_MFC_BITPROC_BUF_H ++ ++#include "s3c_mfc_types.h" ++ ++BOOL s3c_mfc_memmap_bitproc_buff(void); ++volatile unsigned char *s3c_mfc_get_bitproc_buff_virt_addr(void); ++unsigned char *s3c_mfc_get_param_buff_virt_addr(void); ++ ++void s3c_mfc_put_firmware_into_codebuff(void); ++ ++#endif /* _S3C_MFC_BITPROC_BUF_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_config.h linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_config.h +--- linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_config.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_config.h 2009-10-21 16:21:34.000000000 +0200 +@@ -0,0 +1,92 @@ ++/* linux/driver/media/video/mfc/s3c_mfc_config.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_MFC_CONFIG_H ++#define _S3C_MFC_CONFIG_H ++ ++#include ++ ++/* Physical Base Address for the MFC Host I/F Registers */ ++/* #define S3C6400_BASEADDR_MFC_SFR 0x7e002000 */ ++/* #define MFC_RESERVED_MEM_START 0x57800000 */ ++ ++#ifndef S3C_MFC_PHYS_BUFFER_SET ++extern dma_addr_t s3c_mfc_phys_buffer; ++#endif ++ ++#define MFC_RESERVED_MEM_START s3c_mfc_phys_buffer ++ ++/* ++ * Physical Base Address for the MFC Shared Buffer ++ * Shared Buffer = {CODE_BUF, WORK_BUF, PARA_BUF} ++ */ ++#define S3C_MFC_BASEADDR_BITPROC_BUF MFC_RESERVED_MEM_START ++ ++/* Physical Base Address for the MFC Data Buffer ++ * Data Buffer = {STRM_BUF, FRME_BUF} ++ */ ++#define S3C_MFC_BASEADDR_DATA_BUF (MFC_RESERVED_MEM_START + 0x116000) ++ ++/* Physical Base Address for the MFC Host I/F Registers */ ++#define S3C_MFC_BASEADDR_POST_SFR 0x77000000 ++ ++ ++/* ++ * MFC BITPROC_BUF ++ * ++ * the following three buffers have fixed size ++ * firware buffer is to download boot code and firmware code ++ */ ++#define S3C_MFC_CODE_BUF_SIZE 81920 /* It is fixed depending on the MFC'S FIRMWARE CODE (refer to 'Prism_S_V133.h' file) */ ++ ++/* working buffer is uded for video codec operations by MFC */ ++#define S3C_MFC_WORK_BUF_SIZE 1048576 /* 1024KB = 1024 * 1024 */ ++ ++ ++/* Parameter buffer is allocated to store yuv frame address of output frame buffer. */ ++#define S3C_MFC_PARA_BUF_SIZE 8192 /* Stores the base address of Y , Cb , Cr for each decoded frame */ ++ ++#define S3C_MFC_BITPROC_BUF_SIZE \ ++ (S3C_MFC_CODE_BUF_SIZE + \ ++ S3C_MFC_PARA_BUF_SIZE + \ ++ S3C_MFC_WORK_BUF_SIZE) ++ ++ ++/* ++ * MFC DATA_BUF ++ */ ++#define S3C_MFC_NUM_INSTANCES_MAX 4//2 /* MFC Driver supports 4 instances MAX. */ ++ ++/* ++ * Determine if 'Post Rotate Mode' is enabled. ++ * If it is enabled, the memory size of SD YUV420(720x576x1.5 bytes) is required more. ++ * In case of linux driver, reserved buffer size will be changed. ++ */ ++ ++#define S3C_MFC_ROTATE_ENABLE 0 ++ ++/* ++ * stream buffer size must be a multiple of 512bytes ++ * becasue minimun data transfer unit between stream buffer and internal bitstream handling block ++ * in MFC core is 512bytes ++ */ ++#define S3C_MFC_LINE_BUF_SIZE_PER_INSTANCE (614400) ++ ++ ++#define S3C_MFC_LINE_BUF_SIZE (S3C_MFC_NUM_INSTANCES_MAX * S3C_MFC_LINE_BUF_SIZE_PER_INSTANCE) ++ ++#define S3C_MFC_YUV_BUF_SIZE (720*480*3*4) ++ ++#define S3C_MFC_STREAM_BUF_SIZE (S3C_MFC_LINE_BUF_SIZE) ++#define S3C_MFC_DATA_BUF_SIZE (S3C_MFC_STREAM_BUF_SIZE + S3C_MFC_YUV_BUF_SIZE) ++ ++#endif /* _S3C_MFC_CONFIG_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_databuf.c linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_databuf.c +--- linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_databuf.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_databuf.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,82 @@ ++/* linux/driver/media/video/mfc/s3c_mfc_databuf.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include "s3c_mfc_base.h" ++#include "s3c_mfc_types.h" ++#include "s3c_mfc_databuf.h" ++#include "s3c_mfc_config.h" ++#include "s3c_mfc.h" ++ ++static volatile unsigned char *s3c_mfc_virt_data_buf = NULL; ++static unsigned int s3c_mfc_phys_data_buf = 0; ++ ++ ++BOOL s3c_mfc_memmap_databuf() ++{ ++ BOOL ret = FALSE; ++ ++ s3c_mfc_virt_data_buf = phys_to_virt(s3c_mfc_phys_buffer + S3C_MFC_BITPROC_BUF_SIZE); ++ if (s3c_mfc_virt_data_buf == NULL) { ++ mfc_err("fail to mapping data buffer\n"); ++ return ret; ++ } ++ ++ mfc_debug("virtual address of data buffer = 0x%x\n", \ ++ (unsigned int)s3c_mfc_virt_data_buf); ++ ++ ++ /* Physical register address mapping */ ++ s3c_mfc_phys_data_buf = S3C_MFC_BASEADDR_DATA_BUF; ++ ++ ret = TRUE; ++ ++ return ret; ++} ++ ++volatile unsigned char *s3c_mfc_get_databuf_virt_addr() ++{ ++ volatile unsigned char *data_buf; ++ ++ data_buf = s3c_mfc_virt_data_buf; ++ ++ return data_buf; ++} ++ ++volatile unsigned char *s3c_mfc_get_yuvbuff_virt_addr() ++{ ++ volatile unsigned char *yuv_buff; ++ ++ yuv_buff = s3c_mfc_virt_data_buf + S3C_MFC_STREAM_BUF_SIZE; ++ ++ return yuv_buff; ++} ++ ++unsigned int s3c_mfc_get_databuf_phys_addr() ++{ ++ unsigned int phys_data_buf; ++ ++ phys_data_buf = s3c_mfc_phys_data_buf; ++ ++ return phys_data_buf; ++} ++ ++unsigned int s3c_mfc_get_yuvbuff_phys_addr() ++{ ++ unsigned int phys_yuv_buff; ++ ++ phys_yuv_buff = s3c_mfc_phys_data_buf + S3C_MFC_STREAM_BUF_SIZE; ++ ++ return phys_yuv_buff; ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_databuf.h linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_databuf.h +--- linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_databuf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_databuf.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,25 @@ ++/* linux/driver/media/video/mfc/s3c_mfc_databuf.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_MFC_DATABUF_H ++#define _S3C_MFC_DATABUF_H ++ ++#include "s3c_mfc_types.h" ++ ++BOOL s3c_mfc_memmap_databuf(void); ++ ++volatile unsigned char *s3c_mfc_get_databuf_virt_addr(void); ++volatile unsigned char *s3c_mfc_get_yuvbuff_virt_addr(void); ++unsigned int s3c_mfc_get_databuf_phys_addr(void); ++unsigned int s3c_mfc_get_yuvbuff_phys_addr(void); ++ ++#endif /* _S3C_MFC_DATABUF_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_init_hw.c linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_init_hw.c +--- linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_init_hw.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_init_hw.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,94 @@ ++/* linux/driver/media/video/mfc/s3c_mfc_init_hw.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * This source file is for initializing the MFC's H/W setting. ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++ ++#include "s3c_mfc_base.h" ++#include "s3c_mfc_sfr.h" ++#include "s3c_mfc_bitproc_buf.h" ++#include "s3c_mfc_databuf.h" ++#include "s3c_mfc_types.h" ++#include "s3c_mfc_config.h" ++#include "s3c_mfc_yuv_buf_manager.h" ++#include "s3c_mfc.h" ++ ++BOOL s3c_mfc_setup_memory(void) ++{ ++ BOOL ret_bit, ret_dat; ++ unsigned char *pDataBuf; ++ ++ /* ++ * MFC SFR(Special Function Registers), Bitprocessor buffer, Data bufferÀÇ ++ * physical address ¸¦ virtual address·Î mapping ÇÑ´Ù ++ */ ++ ++ ret_bit = s3c_mfc_memmap_bitproc_buff(); ++ if (ret_bit == FALSE) { ++ mfc_err("fail to mapping bitprocessor buffer memory\n"); ++ return FALSE; ++ } ++ ++ ret_dat = s3c_mfc_memmap_databuf(); ++ if (ret_dat == FALSE) { ++ mfc_err("fail to mapping data buffer memory \n"); ++ return FALSE; ++ } ++ ++ /* FramBufMgr Module Initialization */ ++ pDataBuf = (unsigned char *)s3c_mfc_get_databuf_virt_addr(); ++ s3c_mfc_init_yuvbuf_mgr(pDataBuf + S3C_MFC_STREAM_BUF_SIZE, S3C_MFC_YUV_BUF_SIZE); ++ ++ ++ return TRUE; ++} ++ ++ ++BOOL s3c_mfc_init_hw(void) ++{ ++ /* ++ * 1. Reset the MFC IP ++ */ ++ s3c_mfc_reset(); ++ ++ /* ++ * 2. Download Firmware code into MFC ++ */ ++ s3c_mfc_put_firmware_into_codebuff(); ++ s3c_mfc_download_boot_firmware(); ++ mfc_debug("downloading firmware into bitprocessor\n"); ++ ++ /* ++ * 3. Start Bit Processor ++ */ ++ s3c_mfc_start_bit_processor(); ++ ++ /* ++ * 4. Set the Base Address Registers for the following 3 buffers ++ * (CODE_BUF, WORKING_BUF, PARAMETER_BUF) ++ */ ++ s3c_mfc_config_sfr_bitproc_buffer(); ++ ++ /* ++ * 5. Set the Control Registers ++ * - STRM_BUF_CTRL ++ * - FRME_BUF_CTRL ++ * - DEC_FUNC_CTRL ++ * - WORK_BUF_CTRL ++ */ ++ s3c_mfc_config_sfr_ctrl_opts(); ++ ++ s3c_mfc_get_firmware_ver(); ++ ++ return TRUE; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_init_hw.h linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_init_hw.h +--- linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_init_hw.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_init_hw.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,21 @@ ++/* linux/driver/media/video/mfc/s3c_mfc_init_hw.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_MFC_HW_INIT_H ++#define _S3C_MFC_HW_INIT_H ++ ++#include "s3c_mfc_types.h" ++ ++BOOL s3c_mfc_setup_memory(void); ++BOOL s3c_mfc_init_hw(void); ++ ++#endif /* _S3C_MFC_HW_INIT_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_inst_pool.c linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_inst_pool.c +--- linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_inst_pool.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_inst_pool.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,98 @@ ++/* linux/driver/media/video/mfc/s3c_mfc_inst_pool.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * This file stores information about different instancesof MFC. ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include "s3c_mfc_config.h" ++#include "s3c_mfc_inst_pool.h" ++ ++#if !defined(S3C_MFC_NUM_INSTANCES_MAX) ++#error "S3C_MFC_NUM_INSTANCES_MAX should be defined." ++#endif ++#if ((S3C_MFC_NUM_INSTANCES_MAX <= 0) || (S3C_MFC_NUM_INSTANCES_MAX > 8)) ++#error "S3C_MFC_NUM_INSTANCES_MAX should be in the range of 1 ~ 8." ++#endif ++ ++static int s3c_mfc_inst_no = 0; ++static int s3c_mfc_inst_status[S3C_MFC_NUM_INSTANCES_MAX] = {0, }; ++static int s3c_mfc_num_inst_avail = S3C_MFC_NUM_INSTANCES_MAX; ++ ++int s3c_mfc_get_avail_inst_pool_num(void) ++{ ++ return s3c_mfc_num_inst_avail; ++} ++ ++int s3c_mfc_occupy_inst_pool(void) ++{ ++ int i; ++ ++ if (s3c_mfc_num_inst_avail == 0) ++ return -1; ++ ++ for (i = 0; i < S3C_MFC_NUM_INSTANCES_MAX; i++) { ++ if (s3c_mfc_inst_status[s3c_mfc_inst_no] == 0) { ++ s3c_mfc_num_inst_avail--; ++ s3c_mfc_inst_status[s3c_mfc_inst_no] = 1; ++ return s3c_mfc_inst_no; ++ } ++ ++ s3c_mfc_inst_no = (s3c_mfc_inst_no + 1) % S3C_MFC_NUM_INSTANCES_MAX; ++ } ++ ++ return -1; ++} ++ ++ ++int s3c_mfc_release_inst_pool(int instance_no) ++{ ++ if (instance_no >= S3C_MFC_NUM_INSTANCES_MAX || instance_no < 0) { ++ return -1; ++ } ++ ++ if (s3c_mfc_inst_status[instance_no] == 0) ++ return -1; ++ ++ s3c_mfc_num_inst_avail++; ++ s3c_mfc_inst_status[instance_no] = 0; ++ ++ return instance_no; ++} ++ ++ ++void s3c_mfc_occupy_all_inst_pool(void) ++{ ++ int i; ++ ++ if (s3c_mfc_num_inst_avail == 0) ++ return; ++ ++ for (i = 0; i < S3C_MFC_NUM_INSTANCES_MAX; i++) { ++ if (s3c_mfc_inst_status[i] == 0) { ++ s3c_mfc_num_inst_avail--; ++ s3c_mfc_inst_status[i] = 1; ++ } ++ } ++} ++ ++void s3c_mfc_release_all_inst_pool(void) ++{ ++ int i; ++ ++ if (s3c_mfc_num_inst_avail == S3C_MFC_NUM_INSTANCES_MAX) ++ return; ++ ++ for (i = 0; i < S3C_MFC_NUM_INSTANCES_MAX; i++) { ++ if (s3c_mfc_inst_status[i] == 1) { ++ s3c_mfc_num_inst_avail++; ++ s3c_mfc_inst_status[i] = 0; ++ } ++ } ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_inst_pool.h linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_inst_pool.h +--- linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_inst_pool.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_inst_pool.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,24 @@ ++/* linux/driver/media/video/mfc/s3c_mfc_inst_pool.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_MFC_INST_POOL_H ++#define _S3C_MFC_INST_POOL_H ++ ++int s3c_mfc_get_avail_inst_pool_num(void); ++ ++int s3c_mfc_occupy_inst_pool(void); ++int s3c_mfc_release_inst_pool(int instance_no); ++ ++void s3c_mfc_occupy_all_inst_pool(void); ++void s3c_mfc_release_all_inst_pool(void); ++ ++#endif /* _S3C_MFC_INST_POOL_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_instance.c linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_instance.c +--- linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_instance.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_instance.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,1239 @@ ++/* linux/driver/media/video/mfc/s3c_mfc_instance.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "s3c_mfc_base.h" ++#include "s3c_mfc_instance.h" ++#include "s3c_mfc_databuf.h" ++#include "s3c_mfc_yuv_buf_manager.h" ++#include "s3c_mfc_config.h" ++#include "s3c_mfc_sfr.h" ++#include "s3c_mfc_bitproc_buf.h" ++#include "s3c_mfc_inst_pool.h" ++#include "s3c_mfc.h" ++ ++ ++extern void __iomem *s3c_mfc_sfr_base_virt_addr; ++static s3c_mfc_inst_context_t _mfcinst_ctx[S3C_MFC_NUM_INSTANCES_MAX]; ++ ++ ++s3c_mfc_inst_context_t *s3c_mfc_inst_get_context(int inst_no) ++{ ++ if ((inst_no < 0) || (inst_no >= S3C_MFC_NUM_INSTANCES_MAX)) ++ return NULL; ++ ++ if (S3C_MFC_INST_STATE(&(_mfcinst_ctx[inst_no])) >= S3C_MFC_INST_STATE_CREATED) ++ return &(_mfcinst_ctx[inst_no]); ++ else ++ return NULL; ++} ++ ++static void s3c_mfc_get_stream_buffer_addr(s3c_mfc_inst_context_t *ctx) ++{ ++ ctx->stream_buffer = (unsigned char *)(s3c_mfc_get_databuf_virt_addr() + \ ++ (ctx->inst_no * S3C_MFC_LINE_BUF_SIZE_PER_INSTANCE)); ++ ctx->phys_addr_stream_buffer = (unsigned int)(s3c_mfc_get_databuf_phys_addr() + \ ++ (ctx->inst_no * S3C_MFC_LINE_BUF_SIZE_PER_INSTANCE)); ++ ctx->stream_buffer_size = S3C_MFC_LINE_BUF_SIZE_PER_INSTANCE; ++ ++ mfc_debug("ctx->stream_buffer address 0x%08x\n", \ ++ (unsigned int)ctx->stream_buffer); ++ mfc_debug("ctx->phys_addr_stream_buffer address 0x%08x\n", \ ++ ctx->phys_addr_stream_buffer); ++} ++ ++static BOOL s3c_mfc_get_yuv_buffer_addr(s3c_mfc_inst_context_t *ctx, int buf_size) ++{ ++ unsigned char *instance_yuv_buffer; ++ ++ ++ instance_yuv_buffer = s3c_mfc_commit_yuv_buffer_mgr(ctx->inst_no, buf_size); ++ if (instance_yuv_buffer == NULL) { ++ mfc_err("fail to allocate frame buffer\n"); ++ return FALSE; ++ } ++ ++ s3c_mfc_print_commit_yuv_buffer_info(); ++ ++ ctx->yuv_buffer = instance_yuv_buffer; /* virtual address of frame buffer */ ++ ctx->phys_addr_yuv_buffer = S3C_MFC_BASEADDR_DATA_BUF + \ ++ ((int)instance_yuv_buffer - (int)s3c_mfc_get_databuf_virt_addr()); ++ ctx->yuv_buffer_size = buf_size; ++ ++ mfc_debug("ctx->inst_no : %d\n", ctx->inst_no); ++ mfc_debug("ctx->yuv_buffer : 0x%x\n", (unsigned int)ctx->yuv_buffer); ++ mfc_debug("ctx->phys_addr_yuv_buffer : 0x%x\n", ctx->phys_addr_yuv_buffer); ++ ++ return TRUE; ++} ++ ++int s3c_mfc_inst_get_line_buff(s3c_mfc_inst_context_t *ctx, unsigned char **buffer, int *size) ++{ ++ if (S3C_MFC_INST_STATE_CHECK(ctx, S3C_MFC_INST_STATE_DELETED)) { ++ mfc_err("mfc instance is deleted\n"); ++ return S3C_MFC_INST_ERR_STATE_DELETED; ++ } ++ ++ *buffer = ctx->stream_buffer; ++ *size = S3C_MFC_LINE_BUF_SIZE_PER_INSTANCE; ++ ++ return S3C_MFC_INST_RET_OK; ++} ++ ++int s3c_mfc_inst_get_yuv_buff(s3c_mfc_inst_context_t *ctx, unsigned char **buffer, int *size) ++{ ++ /* checking state */ ++ if (S3C_MFC_INST_STATE_CHECK(ctx, S3C_MFC_INST_STATE_DELETED)) { ++ mfc_err("mfc instance is deleted\n"); ++ return S3C_MFC_INST_ERR_STATE_DELETED; ++ } ++ if (S3C_MFC_INST_STATE_CHECK(ctx, S3C_MFC_INST_STATE_CREATED)) { ++ mfc_err("mfc instance is not initialized\n"); ++ return S3C_MFC_INST_ERR_STATE_CHK; ++ } ++ ++ if (ctx->yuv_buffer == NULL) { ++ mfc_err("mfc frame buffer is not internally allocated yet\n"); ++ return S3C_MFC_INST_ERR_ETC; ++ } ++ ++ *size = (ctx->buf_width * ctx->buf_height * 3) >> 1; /* YUV420 frame size */ ++ ++ if (ctx->run_index < 0) /* RET_DEC_PIC_IDX == -3 (No picture to be displayed) */ ++ *buffer = NULL; ++ else { ++ *buffer = ctx->yuv_buffer + (ctx->run_index) * (*size); ++#if (S3C_MFC_ROTATE_ENABLE == 1) ++ if (ctx->post_rotation_mode & 0x0010) ++ *buffer = ctx->yuv_buffer + (ctx->yuv_buffer_count) * (*size); ++#endif ++ } ++ ++ ++ return S3C_MFC_INST_RET_OK; ++} ++ ++/* it returns the instance number of the 6410 mfc instance context */ ++int s3c_mfc_inst_get_no(s3c_mfc_inst_context_t *ctx) ++{ ++ return ctx->inst_no; ++} ++ ++/* It returns the virtual address of read pointer and write pointer */ ++BOOL s3c_mfc_inst_get_stream_buff_rw_ptrs(s3c_mfc_inst_context_t *ctx, unsigned char **read_ptr, \ ++ unsigned char **write_ptr) ++{ ++ int diff_vir_phy; ++ unsigned int read_pointer = 0; ++ unsigned int write_pointer = 0; ++ ++ ++ if (S3C_MFC_INST_STATE(ctx) < S3C_MFC_INST_STATE_CREATED) ++ return FALSE; ++ ++ if (S3C_MFC_INST_STATE_CHECK(ctx, S3C_MFC_INST_STATE_CREATED)) { ++ /* ++ * if s3c_mfc_inst_context_t is just created and not initialized by s3c_mfc_instance_init, ++ * then the initial read pointer and write pointer are the start address of stream buffer ++ */ ++ *read_ptr = ctx->stream_buffer; ++ *write_ptr = ctx->stream_buffer; ++ } else { ++ /* the physical to virtual address conversion of read pointer and write pointer */ ++ diff_vir_phy = (int)(ctx->stream_buffer - ctx->phys_addr_stream_buffer); ++ ++ switch(ctx->inst_no) { ++ case 0: ++ read_pointer = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR0); ++ write_pointer = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR0); ++ break; ++ case 1: ++ read_pointer = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR1); ++ write_pointer = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR1); ++ break; ++ case 2: ++ read_pointer = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR2); ++ write_pointer = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR2); ++ break; ++ case 3: ++ read_pointer = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR3); ++ write_pointer = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR3); ++ break; ++ case 4: ++ read_pointer = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR4); ++ write_pointer = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR4); ++ break; ++ case 5: ++ read_pointer = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR5); ++ write_pointer = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR5); ++ break; ++ case 6: ++ read_pointer = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR6); ++ write_pointer = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR6); ++ break; ++ case 7: ++ read_pointer = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR7); ++ write_pointer = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR7); ++ break; ++ } ++ ++ *read_ptr = (unsigned char *)(diff_vir_phy + read_pointer); ++ *write_ptr = (unsigned char *)(diff_vir_phy + write_pointer); ++ } ++ ++ return TRUE; ++} ++ ++unsigned int s3c_mfc_inst_set_post_rotate(s3c_mfc_inst_context_t *ctx, unsigned int post_rotmode) ++{ ++ unsigned int old_post_rotmode; ++ ++ old_post_rotmode = ctx->post_rotation_mode; ++ ++ if (post_rotmode & 0x0010) { ++ ctx->post_rotation_mode = post_rotmode; ++ } else ++ ctx->post_rotation_mode = 0; ++ ++ ++ return old_post_rotmode; ++} ++ ++s3c_mfc_inst_context_t *s3c_mfc_inst_create(void) ++{ ++ int inst_no; ++ s3c_mfc_inst_context_t *ctx; ++ ++ ++ /* occupy the 'inst_no' */ ++ /* if it fails, it returns NULL */ ++ inst_no = s3c_mfc_occupy_inst_pool(); ++ if (inst_no == -1) ++ return NULL; ++ ++ ctx = &(_mfcinst_ctx[inst_no]); ++ ++ memset(ctx, 0, sizeof(s3c_mfc_inst_context_t)); ++ ++ ctx->inst_no = inst_no; ++ S3C_MFC_INST_STATE_TRANSITION(ctx, S3C_MFC_INST_STATE_CREATED); ++ ++ s3c_mfc_get_stream_buffer_addr(ctx); ++ ++ mfc_debug("state = %d\n", ctx->state_var); ++ ++ return ctx; ++} ++ ++/* it deletes the 6410 mfc instance */ ++void s3c_mfc_inst_del(s3c_mfc_inst_context_t *ctx) ++{ ++ /* checking state */ ++ if (S3C_MFC_INST_STATE_CHECK(ctx, S3C_MFC_INST_STATE_DELETED)) { ++ mfc_err("mfc instance is already deleted\n"); ++ return; ++ } ++ ++ s3c_mfc_release_inst_pool(ctx->inst_no); ++ s3c_mfc_free_yuv_buffer_mgr(ctx->inst_no); ++ ++ S3C_MFC_INST_STATE_TRANSITION(ctx, S3C_MFC_INST_STATE_DELETED); ++} ++ ++/* it turns on the flag indicating 6410 mfc's power-off */ ++void s3c_mfc_inst_pow_off_state(s3c_mfc_inst_context_t *ctx) ++{ ++ S3C_MFC_INST_STATE_PWR_OFF_FLAG_SET(ctx); ++} ++ ++/* it turns on the flag indicating 6410 mfc's power-off */ ++void s3c_mfc_inst_pow_on_state(s3c_mfc_inst_context_t *ctx) ++{ ++ S3C_MFC_INST_STATE_PWR_OFF_FLAG_CLEAR(ctx); ++} ++ ++/* ++ * it initializes the 6410 mfc instance with the appropriate config stream ++ * the config stream must be copied into stream buffer before this function ++ */ ++int s3c_mfc_inst_init_dec(s3c_mfc_inst_context_t *ctx, s3c_mfc_codec_mode_t codec_mode, unsigned long strm_leng) ++{ ++ int i; ++ int yuv_buf_size; /* required size in yuv buffer */ ++ int frame_size; /* width * height */ ++ int frame_need_count; ++ unsigned char *param_buf; /* PARAM_BUF in BITPROC_BUF */ ++ ++ ++ /* checking state */ ++ if (!S3C_MFC_INST_STATE_CHECK(ctx, S3C_MFC_INST_STATE_CREATED)) { ++ mfc_err("sequence init function was called at an incorrect point\n"); ++ return S3C_MFC_INST_ERR_STATE_CHK; ++ } ++ ++ /* codec_mode */ ++ ctx->codec_mode = codec_mode; ++ ++ /* stream size checking */ ++ if (strm_leng > S3C_MFC_LINE_BUF_SIZE_PER_INSTANCE) { ++ mfc_err("Input buffer size is too small to hold the input stream.\n"); ++ return S3C_MFC_INST_ERR_ETC; ++ } ++ ++ /* ++ * Copy the Config Stream into stream buffer ++ * config stream needs to be in the stream buffer a priori. ++ * read pointer and write pointer are set to point the start and end address of stream buffer ++ * if write pointer is set to [start + config_leng] instead of [end address of stream buffer], ++ * then mfc is not initialized when MPEG4 decoding. ++ */ ++ mfc_debug("strm_leng = %d\n", (int)strm_leng); ++ ++ strm_leng = S3C_MFC_LINE_BUF_SIZE_PER_INSTANCE; ++ ++ switch(ctx->inst_no) { ++ case 0: ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR0); ++ writel(ctx->phys_addr_stream_buffer + strm_leng, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR0); ++ break; ++ case 1: ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR1); ++ writel(ctx->phys_addr_stream_buffer + strm_leng, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR1); ++ break; ++ case 2: ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR2); ++ writel(ctx->phys_addr_stream_buffer + strm_leng, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR2); ++ break; ++ case 3: ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR3); ++ writel(ctx->phys_addr_stream_buffer + strm_leng, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR3); ++ break; ++ case 4: ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR4); ++ writel(ctx->phys_addr_stream_buffer + strm_leng, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR4); ++ break; ++ case 5: ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR5); ++ writel(ctx->phys_addr_stream_buffer + strm_leng, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR5); ++ break; ++ case 6: ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR6); ++ writel(ctx->phys_addr_stream_buffer + strm_leng, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR6); ++ break; ++ case 7: ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR7); ++ writel(ctx->phys_addr_stream_buffer + strm_leng, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR7); ++ break; ++ } ++ ++ /* ++ * issue the SEQ_INIT command ++ * width/height of frame will be obtained ++ * set the Parameters for SEQ_INIT command ++ */ ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_DEC_SEQ_BIT_BUF_ADDR); ++ writel(S3C_MFC_LINE_BUF_SIZE_PER_INSTANCE / 1024, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_DEC_SEQ_BIT_BUF_SIZE); ++ writel(S3C_MFC_FILEPLAY_ENABLE | S3C_MFC_DYNBUFALLOC_ENABLE, s3c_mfc_sfr_base_virt_addr + \ ++ S3C_MFC_PARAM_DEC_SEQ_OPTION); ++ writel(0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_DEC_SEQ_START_BYTE); ++ ++ mfc_debug("ctx->inst_no = %d\n", ctx->inst_no); ++ mfc_debug("ctx->codec_mode = %d\n", ctx->codec_mode); ++ mfc_debug("sequece bit buffer size = %d (kb)\n", \ ++ readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_DEC_SEQ_BIT_BUF_SIZE)); ++ ++ s3c_mfc_set_eos(0); ++ ++ /* SEQ_INIT command */ ++ if (s3c_mfc_issue_command(ctx->inst_no, ctx->codec_mode, SEQ_INIT) == FALSE) { ++ mfc_err("sequence init failed\n"); ++ s3c_mfc_stream_end(); ++ return S3C_MFC_INST_ERR_DEC_INIT_CMD_FAIL; ++ } ++ ++ s3c_mfc_stream_end(); ++ ++ if (readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_DEC_SEQ_SUCCESS) == TRUE) { ++ mfc_debug("RET_DEC_SEQ_SRC_SIZE = %d\n", \ ++ readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_DEC_SEQ_SRC_SIZE)); ++ mfc_debug("RET_DEC_SEQ_SRC_FRAME_RATE = %d\n", \ ++ readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_DEC_SEQ_SRC_FRAME_RATE)); ++ mfc_debug("RET_DEC_SEQ_FRAME_NEED_COUNT = %d\n", \ ++ readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_DEC_SEQ_FRAME_NEED_COUNT)); ++ mfc_debug("RET_DEC_SEQ_FRAME_DELAY = %d\n", \ ++ readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_DEC_SEQ_FRAME_DELAY)); ++ } else { ++ mfc_err("sequece init failed = %d\n", \ ++ readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_DEC_SEQ_SUCCESS)); ++ return S3C_MFC_INST_ERR_DEC_INIT_CMD_FAIL; ++ } ++ ++ frame_need_count = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_DEC_SEQ_FRAME_NEED_COUNT); ++ ++ /* ++ * width and height are obtained from return value of SEQ_INIT command ++ * stride value is multiple of 16 ++ */ ++ ctx->height = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_DEC_SEQ_SRC_SIZE) & 0x03FF; ++ ctx->width = (readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_DEC_SEQ_SRC_SIZE) >> 10) & 0x03FF; ++ ++ /* ++ * if codec mode is VC1_DEC, ++ * width & height value are not from return value of SEQ_INIT command ++ * but extracting from config stream ++ */ ++ if (ctx->codec_mode == VC1_DEC) { ++ memcpy(&(ctx->height), ctx->stream_buffer + 12, 4); ++ memcpy(&(ctx->width), ctx->stream_buffer + 16, 4); ++ } ++ ++ if ((ctx->width & 0x0F) == 0) /* 16 aligned (ctx->width%16 == 0) */ ++ ctx->buf_width = ctx->width; ++ else ++ ctx->buf_width = (ctx->width & 0xFFFFFFF0) + 16; ++ ++ if ((ctx->height & 0x0F) == 0) /* 16 aligned (ctx->height%16 == 0) */ ++ ctx->buf_height = ctx->height; ++ else ++ ctx->buf_height = (ctx->height & 0xFFFFFFF0) + 16; ++ ++#if (defined(DIVX_ENABLE) && (DIVX_ENABLE == 1)) ++ ctx->buf_width += 2 * ctx->padding_size; ++ ctx->buf_height += 2 * ctx->padding_size; ++ ctx->RET_DEC_SEQ_INIT_BAK_MP4ASP_VOP_TIME_RES = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_DEC_SEQ_TIME_RES); ++#endif ++ mfc_debug("width = %d, height = %d, buf_width = %d, buf_height = %d\n", \ ++ ctx->width, ctx->height, ctx->buf_width, ctx->buf_height); ++ ++ /* ++ * getting yuv buffer for this instance ++ * yuv_buf_size is (YUV420 frame size) * (required frame buffer count) ++ */ ++#if (S3C_MFC_ROTATE_ENABLE == 1) ++ /* If rotation is enabled, one more YUV buffer is required */ ++ yuv_buf_size = ((ctx->buf_width * ctx->buf_height * 3) >> 1) * (frame_need_count + 1); ++#else ++ yuv_buf_size = ((ctx->buf_width * ctx->buf_height * 3) >> 1) * frame_need_count; ++#endif ++ yuv_buf_size += 60000; ++ if ( s3c_mfc_get_yuv_buffer_addr(ctx, yuv_buf_size) == FALSE ) { ++ mfc_err("mfc instance init failed (required frame buffer size = %d)\n", \ ++ yuv_buf_size); ++ return S3C_MFC_INST_ERR_ETC; ++ } ++ ++ ctx->yuv_buffer_allocated = 1; ++ ctx->yuv_buffer_count = frame_need_count; ++ ctx->mv_mbyte_addr = ctx->phys_addr_yuv_buffer + (yuv_buf_size - 60000); ++ ++ /* ++ * set the parameters in the parameters buffer for SET_FRAME_BUF command. ++ * buffer address of y, cb, cr will be set in parameters buffer before issuing SET_FRAME_BUF command ++ */ ++ param_buf = (unsigned char *)s3c_mfc_get_param_buff_virt_addr(); ++ frame_size = ctx->buf_width * ctx->buf_height; ++#if (defined(DIVX_ENABLE) && (DIVX_ENABLE == 1)) ++ /* s/w divx use padding area, so mfc frame buffer must have stride */ ++ for (i=0; i < frame_need_count; i++) { ++ *((int *)(param_buf + i * 3 * 4)) = ctx->phys_addr_yuv_buffer + i * ((frame_size * 3) >> 1) + \ ++ (ctx->buf_width)*ctx->padding_size+ ctx->padding_size; ++ *((int *)(param_buf + i * 3 * 4 + 4)) = ctx->phys_addr_yuv_buffer + i * ((frame_size * 3) >> 1) + \ ++ frame_size + ((ctx->buf_width) / 2) * (ctx->padding_size / 2) + (ctx->padding_size / 2); ++ *((int *)(param_buf + i * 3 * 4 + 8)) = ctx->phys_addr_yuv_buffer + i * ((frame_size * 3) >> 1) + \ ++ frame_size + (frame_size >> 2) + ((ctx->buf_width) / 2) * (ctx->padding_size / 2) + (ctx->padding_size / 2); ++ } ++#else ++ for (i=0; i < frame_need_count; i++) { ++ *((int *)(param_buf + i * 3 * 4)) = ctx->phys_addr_yuv_buffer + i * ((frame_size * 3) >> 1); ++ *((int *)(param_buf + i * 3 * 4 + 4)) = ctx->phys_addr_yuv_buffer + i * ((frame_size * 3) >> 1) + frame_size; ++ *((int *)(param_buf + i * 3 * 4 + 8)) = ctx->phys_addr_yuv_buffer + i * ((frame_size * 3) >> 1) + \ ++ frame_size + (frame_size >> 2); ++ } ++#endif ++ ++ /* ++ * issue the SET_FRAME_BUF command ++ * 'SET_FRAME_BUF_NUM' must be greater than or equal to RET_DEC_SEQ_FRAME_NEED_COUNT ++ */ ++ writel(frame_need_count, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_SET_FRAME_BUF_NUM); ++ writel(ctx->buf_width, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_SET_FRAME_BUF_STRIDE); ++ ++ s3c_mfc_issue_command(ctx->inst_no, ctx->codec_mode, SET_FRAME_BUF); ++ ++ /* ++ * changing state ++ * change the state to S3C_MFC_INST_STATE_DEC_INITIALIZED ++ * if the input stream data is less than the 2 PARTUNITs size, ++ * then the state is changed to MFCINST_STATE_DEC_PIC_RUN_RING_BUF_LAST_UNITS ++ */ ++ S3C_MFC_INST_STATE_TRANSITION(ctx, S3C_MFC_INST_STATE_DEC_INITIALIZED); ++ ++ ++ return S3C_MFC_INST_RET_OK; ++} ++ ++ ++int s3c_mfc_instance_init_enc(s3c_mfc_inst_context_t *ctx, s3c_mfc_codec_mode_t codec_mode, s3c_mfc_enc_info_t *enc_info) ++{ ++ int i; ++ int yuv_buffer_size; /* required size in yuv buffer */ ++ int frame_size; /* width * height */ ++ int num_mbs; /* number of MBs */ ++ int slices_mb; /* MB number of slice (only if S3C_MFC_SLICE_MODE_MULTIPLE is selected.) */ ++ unsigned char *param_buf; /* PARAM_BUF in BITPROC_BUF */ ++ ++ ++ /* check parameters from user application */ ++ if ((enc_info->width & 0x0F) || (enc_info->height & 0x0F)) { ++ mfc_err("source picture width and height must be a multiple of 16. width : %d, height : %d\n", \ ++ enc_info->width, enc_info->height); ++ ++ return S3C_MFC_INST_ERR_INVALID_PARAM; ++ } ++ ++ if (codec_mode < 0 || codec_mode > 6) { ++ mfc_err("mfc encoder supports MPEG4, H.264 and H.263\n"); ++ return S3C_MFC_INST_ERR_INVALID_PARAM; ++ } ++ ++ if (enc_info->gop_number > 60) { ++ mfc_err("maximum gop number is 60. GOP number = %d\n", enc_info->gop_number); ++ return S3C_MFC_INST_ERR_INVALID_PARAM; ++ } ++ ++ ctx->width = enc_info->width; ++ ctx->height = enc_info->height; ++ ctx->frame_rate_residual = enc_info->frame_rate_residual; ++ ctx->frame_rate_division = enc_info->frame_rate_division; ++ ctx->gop_number = enc_info->gop_number; ++ ctx->bitrate = enc_info->bitrate; ++ ++ /* ++ * At least 2 frame buffers are needed. ++ * These buffers are used for input buffer in encoder case ++ */ ++ ctx->yuv_buffer_count = 2; ++ ++ /* ++ * this part is not required since the width and the height are checked to be multiples of 16 ++ * in the beginning of this function ++ */ ++ if ((ctx->width & 0x0F) == 0) /* 16 aligned (ctx->width%16 == 0) */ ++ ctx->buf_width = ctx->width; ++ else ++ ctx->buf_width = (ctx->width & 0xFFFFFFF0) + 16; ++ ++ /* codec_mode */ ++ ctx->codec_mode = codec_mode; ++ ++ mfc_debug("ctx->inst_no = %d\n", ctx->inst_no); ++ mfc_debug("ctx->codec_mode = %d\n", ctx->codec_mode); ++ ++ /* ++ * set stream buffer read/write pointer ++ * At first, stream buffer is empty. so write pointer points start of buffer and read pointer points end of buffer ++ */ ++ switch(ctx->inst_no) { ++ case 0: ++ writel(ctx->phys_addr_stream_buffer + S3C_MFC_LINE_BUF_SIZE_PER_INSTANCE, \ ++ s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR0); ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR0); ++ break; ++ case 1: ++ writel(ctx->phys_addr_stream_buffer + S3C_MFC_LINE_BUF_SIZE_PER_INSTANCE, \ ++ s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR1); ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR1); ++ break; ++ case 2: ++ writel(ctx->phys_addr_stream_buffer + S3C_MFC_LINE_BUF_SIZE_PER_INSTANCE, \ ++ s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR2); ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR2); ++ break; ++ case 3: ++ writel(ctx->phys_addr_stream_buffer + S3C_MFC_LINE_BUF_SIZE_PER_INSTANCE, \ ++ s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR3); ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR3); ++ break; ++ case 4: ++ writel(ctx->phys_addr_stream_buffer + S3C_MFC_LINE_BUF_SIZE_PER_INSTANCE, \ ++ s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR4); ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR4); ++ break; ++ case 5: ++ writel(ctx->phys_addr_stream_buffer + S3C_MFC_LINE_BUF_SIZE_PER_INSTANCE, \ ++ s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR5); ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR5); ++ break; ++ case 6: ++ writel(ctx->phys_addr_stream_buffer + S3C_MFC_LINE_BUF_SIZE_PER_INSTANCE, \ ++ s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR6); ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR6); ++ break; ++ case 7: ++ writel(ctx->phys_addr_stream_buffer + S3C_MFC_LINE_BUF_SIZE_PER_INSTANCE, \ ++ s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR7); ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR7); ++ break; ++ } ++ ++ writel(0x1C, s3c_mfc_sfr_base_virt_addr + S3C_MFC_STRM_BUF_CTRL); ++ ++ /* ++ * issue the SEQ_INIT command ++ * frame width/height will be returned ++ * set the parameters for SEQ_INIT command ++ */ ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_BIT_BUF_ADDR); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_BIT_BUF_SIZE); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_OPTION); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_COD_STD); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_SRC_SIZE); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_SRC_F_RATE); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_MP4_PARA); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_263_PARA); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_264_PARA); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_SLICE_MODE); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_GOP_NUM); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_RC_PARA); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_RC_BUF_SIZE); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_INTRA_MB); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_FMO); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_INTRA_QP); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_ENC_SEQ_SUCCESS); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_RC_OPTION); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_RC_QP_MAX); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_RC_GAMMA); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_TMP_BUF1); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_TMP_BUF2); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_TMP_BUF3); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_TMP_BUF4); ++ ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_BIT_BUF_ADDR); ++ writel(S3C_MFC_LINE_BUF_SIZE_PER_INSTANCE / 1024, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_BIT_BUF_SIZE); ++ writel(S3C_MFC_MB_BIT_REPORT_DISABLE | S3C_MFC_SLICE_INFO_REPORT_DISABLE | S3C_MFC_AUD_DISABLE | \ ++ S3C_MFC_MB_QP_REPORT_DISABLE | S3C_MFC_CONST_QP_DISABLE, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_OPTION); ++ writel((ctx->width << 10) | ctx->height, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_SRC_SIZE); ++ writel((ctx->frame_rate_division << 16) | ctx->frame_rate_residual, \ ++ s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_SRC_F_RATE); ++ writel(S3C_MFC_SLICE_MODE_ONE, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_SLICE_MODE); ++ writel(ctx->gop_number, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_GOP_NUM); ++ writel(S3C_MFC_RC_ENABLE | (ctx->bitrate << 1) | (SKIP_ENABLE << 31), \ ++ s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_RC_PARA); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_INTRA_MB); ++ writel(FMO_DISABLE, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_FMO); ++ writel(S3C_MFC_USE_GAMMA_DISABLE, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_RC_OPTION); ++ ++ switch(ctx->codec_mode) { ++ case MP4_ENC: ++ writel(S3C_MFC_MPEG4_ENCODE, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_COD_STD); ++ writel(S3C_MFC_DATA_PART_DISABLE, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_MP4_PARA); ++ break; ++ ++ case H263_ENC: ++ writel(S3C_MFC_H263_ENCODE, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_COD_STD); ++ writel(ctx->h263_annex, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_263_PARA); ++ ++ if (ctx->enc_num_slices){ ++ /* ++ * MB size is 16x16 -> width & height are divided by 16 to get number of MBs ++ * division by 16 == shift right by 4-bit ++ */ ++ num_mbs = (enc_info->width >> 4) * (enc_info->height >> 4); ++ slices_mb = (num_mbs / ctx->enc_num_slices); ++ writel(S3C_MFC_SLICE_MODE_MULTIPLE | (1 << 1) | (slices_mb << 2), \ ++ s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_SLICE_MODE); ++ } else if (ctx->h263_annex == 0) { ++ if (((enc_info->width == 704) && (enc_info->height == 576)) || \ ++ ((enc_info->width == 352) && (enc_info->height == 288))|| \ ++ ((enc_info->width == 176) && (enc_info->height == 144)) || \ ++ ((enc_info->width == 128) && (enc_info->height == 96))) { ++ mfc_debug("ENC_SEQ_263_PARA = 0x%X\n", \ ++ readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_263_PARA)); ++ } else { ++ mfc_err("h.263 encoder supports 4cif, cif, qcif and sub-qcif\n"); ++ mfc_err("when all Annex were off\n"); ++ return S3C_MFC_INST_ERR_INVALID_PARAM; ++ } ++ } ++ ++ break; ++ ++ case AVC_ENC: ++ writel(S3C_MFC_H264_ENCODE, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_COD_STD); ++ writel(~(0xFFFF), s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_264_PARA); ++ if (ctx->enc_num_slices) { ++ /* ++ * MB size is 16x16 -> width & height are divided by 16 to get number of MBs ++ * division by 16 == shift right by 4-bit ++ */ ++ num_mbs = (enc_info->width >> 4) * (enc_info->height >> 4); ++ slices_mb = (num_mbs / ctx->enc_num_slices); ++ writel(S3C_MFC_SLICE_MODE_MULTIPLE | (1 << 1) | (slices_mb<< 2), \ ++ s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_SLICE_MODE); ++ } ++ ++ break; ++ ++ default: ++ mfc_err("mfc encoder supports mpeg4, h.264 and h.263\n"); ++ return S3C_MFC_INST_ERR_INVALID_PARAM; ++ } ++ ++ writel(USER_QP_MAX_DISABLE, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_SEQ_RC_OPTION); ++ ++ /* SEQ_INIT command */ ++ s3c_mfc_issue_command(ctx->inst_no, ctx->codec_mode, SEQ_INIT); ++ ++ if (readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_ENC_SEQ_SUCCESS) == TRUE) { ++ mfc_debug("encoding sequence init success\n"); ++ } else { ++ mfc_err("fail to encoding sequence init\n"); ++ return S3C_MFC_INST_ERR_ENC_INIT_CMD_FAIL; ++ } ++ ++ yuv_buffer_size = ((ctx->width * ctx->height * 3) >> 1) * (ctx->yuv_buffer_count + 1); ++ if (s3c_mfc_get_yuv_buffer_addr(ctx, yuv_buffer_size) == FALSE) { ++ mfc_err("fail to Initialization of MFC instance\n"); ++ mfc_err("fail to mfc instance inititialization (required frame buffer size = %d)\n", \ ++ yuv_buffer_size); ++ return S3C_MFC_INST_ERR_ETC; ++ } ++ ctx->yuv_buffer_allocated = 1; ++ ++ /* ++ * set the parameters in the parameters buffer for SET_FRAME_BUF command ++ * buffer address of y, cb, cr will be set in parameters buffer ++ */ ++ param_buf = (unsigned char *)s3c_mfc_get_param_buff_virt_addr(); ++ frame_size = ctx->width * ctx->height; ++ for (i=0; i < ctx->yuv_buffer_count; i++) { ++ *((int *)(param_buf + i * 3 * 4)) = ctx->phys_addr_yuv_buffer + (i + 1) * ((frame_size * 3) >> 1); ++ *((int *)(param_buf + i * 3 * 4 + 4)) = ctx->phys_addr_yuv_buffer + (i + 1) * ((frame_size * 3) >> 1) + \ ++ frame_size; ++ *((int *)(param_buf + i * 3 * 4 + 8)) = ctx->phys_addr_yuv_buffer + (i + 1) * ((frame_size * 3) >> 1) + \ ++ frame_size + (frame_size >> 2); ++ } ++ ++ /* ++ * issue the SET_FRAME_BUF command ++ * 'SET_FRAME_BUF_NUM' must be greater than or equal to RET_DEC_SEQ_FRAME_NEED_COUNT ++ */ ++ writel(ctx->yuv_buffer_count, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_SET_FRAME_BUF_NUM); ++ writel(ctx->buf_width, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_SET_FRAME_BUF_STRIDE); ++ ++ s3c_mfc_issue_command(ctx->inst_no, ctx->codec_mode, SET_FRAME_BUF); ++ ++ /* ++ * changing state ++ * state change to S3C_MFC_INST_STATE_ENC_INITIALIZED ++ */ ++ S3C_MFC_INST_STATE_TRANSITION(ctx, S3C_MFC_INST_STATE_ENC_INITIALIZED); ++ ++ ++ return S3C_MFC_INST_RET_OK; ++} ++ ++/* this function decodes the input stream and put the decoded frame into the yuv buffer */ ++int s3c_mfc_inst_dec(s3c_mfc_inst_context_t *ctx, unsigned long strm_leng) ++{ ++#if (S3C_MFC_ROTATE_ENABLE == 1) ++ int frame_size; // width * height ++#endif ++ int frm_size; ++ ++ /* checking state */ ++ if (S3C_MFC_INST_STATE_CHECK(ctx, S3C_MFC_INST_STATE_DELETED)) { ++ mfc_err("mfc instance is deleted\n"); ++ return S3C_MFC_INST_ERR_STATE_DELETED; ++ } ++ if (S3C_MFC_INST_STATE_PWR_OFF_FLAG_CHECK(ctx)) { ++ mfc_err("mfc instance is in Power-Off state.\n"); ++ return S3C_MFC_INST_ERR_STATE_POWER_OFF; ++ } ++ if (S3C_MFC_INST_STATE_CHECK(ctx, S3C_MFC_INST_STATE_CREATED)) { ++ mfc_err("mfc instance is not initialized\n"); ++ return S3C_MFC_INST_ERR_STATE_CHK; ++ } ++ ++ /* ++ * (strm_leng > 0) means that the video stream is waiting for being decoded in the STRM_LINE_BUF ++ * otherwise, no more video streams are available and the decode command will flush the decoded YUV data ++ * which are postponed because of B-frame (VC-1) or reordering (H.264). ++ */ ++ if (strm_leng > 0) { ++ switch(ctx->inst_no) { ++ case 0: ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR0); ++ writel(ctx->phys_addr_stream_buffer + strm_leng, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR0); ++ break; ++ case 1: ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR1); ++ writel(ctx->phys_addr_stream_buffer + strm_leng, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR1); ++ break; ++ case 2: ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR2); ++ writel(ctx->phys_addr_stream_buffer + strm_leng, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR2); ++ break; ++ case 3: ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR3); ++ writel(ctx->phys_addr_stream_buffer + strm_leng, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR3); ++ break; ++ case 4: ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR4); ++ writel(ctx->phys_addr_stream_buffer + strm_leng, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR4); ++ break; ++ case 5: ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR5); ++ writel(ctx->phys_addr_stream_buffer + strm_leng, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR5); ++ break; ++ case 6: ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR6); ++ writel(ctx->phys_addr_stream_buffer + strm_leng, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR6); ++ break; ++ case 7: ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_RD_PTR7); ++ writel(ctx->phys_addr_stream_buffer + strm_leng, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR7); ++ break; ++ } ++ ++ /* set the parameters in the parameters buffer for PIC_RUN command */ ++ writel(ctx->post_rotation_mode, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_DEC_PIC_RUN); ++ ++#if (S3C_MFC_ROTATE_ENABLE == 1) ++ if (ctx->post_rotation_mode & 0x0010) { /* the bit of 'post_rotataion_enable' is 1 */ ++ unsigned int dec_pic_rot_addr_y; ++ ++ frame_size = ctx->buf_width * ctx->buf_height; ++ ++ dec_pic_rot_addr_y = ctx->phys_addr_yuv_buffer + ctx->yuv_buffer_count * ((frame_size * 3) >> 1); ++ writel(dec_pic_rot_addr_y, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_DEC_PIC_ROT_ADDR_Y); ++ writel(dec_pic_rot_addr_y + frame_size, s3c_mfc_sfr_base_virt_addr + \ ++ S3C_MFC_PARAM_DEC_PIC_ROT_ADDR_CB); ++ writel(dec_pic_rot_addr_y + frame_size + (frame_size >> 2), \ ++ s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_DEC_PIC_ROT_ADDR_CR); ++ ++ /* rotate angle */ ++ switch (ctx->post_rotation_mode & 0x0003) { ++ case 0: /* 0 degree counterclockwise rotate */ ++ case 2: /* 180 degree counterclockwise rotate */ ++ writel(ctx->buf_width, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_DEC_PIC_ROT_STRIDE); ++ ++ break; ++ ++ case 1: /* 90 degree counterclockwise rotate */ ++ case 3: /* 270 degree counterclockwise rotate */ ++ writel(ctx->buf_height, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_DEC_PIC_ROT_STRIDE); ++ break; ++ } ++ } ++#endif ++ ++#if 1 ++ /* DEC_PIC_OPTION was newly added for MP4ASP */ ++ frm_size = ctx->buf_width * ctx->buf_height; ++ writel(0x7, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_DEC_PIC_OPTION); ++ writel(ctx->mv_mbyte_addr, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_DEC_PIC_MV_ADDR); ++ writel(ctx->mv_mbyte_addr + 25920, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_DEC_PIC_MBTYPE_ADDR); ++#endif ++ writel(ctx->phys_addr_stream_buffer & 0xFFFFFFFC, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_DEC_PIC_BB_START); ++ writel(ctx->phys_addr_stream_buffer & 0x00000003, \ ++ s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_DEC_PIC_START_BYTE); ++ writel(strm_leng, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_DEC_PIC_CHUNK_SIZE); ++ } else { ++ writel(strm_leng, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_DEC_PIC_RUN); ++ s3c_mfc_set_eos(1); ++ } ++ ++ /* issue the PIC_RUN command */ ++ if (!s3c_mfc_issue_command(ctx->inst_no, ctx->codec_mode, PIC_RUN)) { ++ return S3C_MFC_INST_ERR_DEC_PIC_RUN_CMD_FAIL; ++ } ++ ++ if (readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_DEC_PIC_SUCCESS) != 1) { ++ mfc_warn("RET_DEC_PIC_SUCCESS is not value of 1(=SUCCESS) value is %d\n", \ ++ readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_DEC_PIC_SUCCESS)); ++ ++ } ++ ctx->run_index = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_DEC_PIC_IDX); ++ ++ if (ctx->run_index > 30) { ++ if (ctx->run_index == 0xFFFFFFFF) { /* RET_DEC_PIC_IDX == -1 */ ++ mfc_warn("end of stream\n"); ++ return S3C_MFC_INST_ERR_DEC_EOS; ++ } else if (ctx->run_index == 0xFFFFFFFD) { /* RET_DEC_PIC_IDX == -3 */ ++ mfc_debug("no picture to be displayed\n"); ++ } else { ++ mfc_err("fail to decoding, ret = %d\n", ctx->run_index); ++ return S3C_MFC_INST_ERR_DEC_DECODE_FAIL_ETC; ++ } ++ } ++ ++#if (defined(DIVX_ENABLE) && (DIVX_ENABLE == 1)) ++ ctx->RET_DEC_PIC_RUN_BAK_BYTE_CONSUMED = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_DEC_PIC_BCNT); ++ ctx->RET_DEC_PIC_RUN_BAK_MP4ASP_FCODE = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_DEC_PIC_FCODE_FWD); ++ ctx->RET_DEC_PIC_RUN_BAK_MP4ASP_TIME_BASE_LAST = \ ++ readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_DEC_PIC_TIME_BASE_LAST); ++ ctx->RET_DEC_PIC_RUN_BAK_MP4ASP_NONB_TIME_LAST = \ ++ readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_DEC_PIC_NONB_TIME_LAST); ++ ctx->RET_DEC_PIC_RUN_BAK_MP4ASP_MP4ASP_TRD = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_DEC_PIC_TRD); ++#endif ++ ++ /* ++ * changing state ++ * state change to S3C_MFC_INST_STATE_DEC_PIC_RUN_LINE_BUF ++ */ ++ S3C_MFC_INST_STATE_TRANSITION(ctx, S3C_MFC_INST_STATE_DEC_PIC_RUN_LINE_BUF); ++ ++ return S3C_MFC_INST_RET_OK; ++} ++ ++int s3c_mfc_inst_enc(s3c_mfc_inst_context_t *ctx, int *enc_data_size, int *header_size) ++{ ++ int hdr_size, hdr_size2; ++ int size; ++ unsigned int bits_wr_ptr_value = 0; ++ unsigned char *hdr_buf_tmp=NULL; ++ unsigned char *start, *end; ++ ++ /* checking state */ ++ if (!S3C_MFC_INST_STATE_CHECK(ctx, S3C_MFC_INST_STATE_ENC_INITIALIZED) && \ ++ !S3C_MFC_INST_STATE_CHECK(ctx, S3C_MFC_INST_STATE_ENC_PIC_RUN_LINE_BUF)) { ++ mfc_err("mfc encoder instance is not initialized or not using the line buffer\n"); ++ return S3C_MFC_INST_ERR_STATE_CHK; ++ } ++ ++ /* the 1st call of this function (s3c_mfc_inst_enc) will generate the stream header (mpeg4:VOL, h264:SPS/PPS) */ ++ if (S3C_MFC_INST_STATE_CHECK(ctx, S3C_MFC_INST_STATE_ENC_INITIALIZED)) { ++ if (ctx->codec_mode == MP4_ENC) { ++ /* ENC_HEADER command */ ++ s3c_mfc_inst_enc_header(ctx, 0, 0, ctx->phys_addr_stream_buffer, ctx->stream_buffer_size, \ ++ &hdr_size); // VOL ++ ++ /* Backup the stream header in the temporary header buffer */ ++ hdr_buf_tmp = (unsigned char *)kmalloc(hdr_size, GFP_KERNEL); ++ if (hdr_buf_tmp) { ++ memcpy(hdr_buf_tmp, ctx->stream_buffer, hdr_size); ++ ++ start = ctx->stream_buffer; ++ size = hdr_size; ++ dma_cache_maint(start, size, DMA_FROM_DEVICE); ++ } else { ++ return S3C_MFC_INST_ERR_MEMORY_ALLOCATION_FAIL; ++ } ++ } else if (ctx->codec_mode == AVC_ENC) { ++ /* ENC_HEADER command */ ++ s3c_mfc_inst_enc_header(ctx, 0, 0, ctx->phys_addr_stream_buffer, ctx->stream_buffer_size, \ ++ &hdr_size); /* SPS */ ++ s3c_mfc_inst_enc_header(ctx, 1, 0, ctx->phys_addr_stream_buffer + (hdr_size + 3), \ ++ ctx->stream_buffer_size-(hdr_size+3), &hdr_size2); /* PPS */ ++ ++ /* backup the stream header in the temporary header buffer */ ++ hdr_buf_tmp = (unsigned char *)kmalloc(hdr_size + 3 + hdr_size2, GFP_KERNEL); ++ if (hdr_buf_tmp) { ++ memcpy(hdr_buf_tmp, ctx->stream_buffer, hdr_size); ++ ++ start = ctx->stream_buffer; ++ size = hdr_size; ++ dma_cache_maint(start, size, DMA_FROM_DEVICE); ++ ++ memcpy(hdr_buf_tmp + hdr_size, (unsigned char *)((unsigned int)(ctx->stream_buffer + \ ++ (hdr_size + 3)) & 0xFFFFFFFC), hdr_size2); ++ ++ start = ((unsigned int)(ctx->stream_buffer + (hdr_size + 3)) & 0xFFFFFFFC); ++ size = hdr_size2; ++ dma_cache_maint(start, size, DMA_FROM_DEVICE); ++ ++ hdr_size += hdr_size2; ++ } else { ++ return S3C_MFC_INST_ERR_MEMORY_ALLOCATION_FAIL; ++ } ++ } ++ } ++ ++ // Dynamic Change for fps of MPEG4 Encoder ++ if ( (ctx->codec_mode == MP4_ENC) && ++ S3C_MFC_INST_STATE_CHECK(ctx, S3C_MFC_INST_STATE_ENC_PIC_RUN_LINE_BUF) && ++ (ctx->enc_change_framerate == 1) ) { ++ ++ // ENC_HEADER command // ++ s3c_mfc_inst_enc_header(ctx, 0, 0, ctx->phys_addr_stream_buffer, ctx->stream_buffer_size, \ ++ &hdr_size); // VOL ++ ++ // Backup the stream header in the temporary header buffer. ++ hdr_buf_tmp = (unsigned char *)kmalloc(hdr_size, GFP_KERNEL); ++ if (hdr_buf_tmp) { ++ memcpy(hdr_buf_tmp, ctx->stream_buffer, hdr_size); ++ ++ start = ctx->stream_buffer; ++ size = hdr_size; ++ dma_cache_maint(start, size, DMA_FROM_DEVICE); ++ } else ++ return S3C_MFC_INST_ERR_MEMORY_ALLOCATION_FAIL; ++ } ++ ++ /* SEI message with recovery point */ ++ if ((ctx->enc_pic_option & 0x0F000000) && (ctx->codec_mode == AVC_ENC)) { ++ /* ENC_HEADER command */ ++ s3c_mfc_inst_enc_header(ctx, 4, ((ctx->enc_pic_option & 0x0F000000) >> 24), \ ++ ctx->phys_addr_stream_buffer, ctx->stream_buffer_size, &hdr_size); /* SEI */ ++ /* Backup the stream header in the temporary header buffer */ ++ hdr_buf_tmp = (unsigned char *)kmalloc(hdr_size, GFP_KERNEL); ++ if (hdr_buf_tmp) { ++ memcpy(hdr_buf_tmp, ctx->stream_buffer, hdr_size); ++ ++ start = ctx->stream_buffer; ++ size = hdr_size; ++ dma_cache_maint(start, size, DMA_FROM_DEVICE); ++ ++ } else { ++ return S3C_MFC_INST_ERR_MEMORY_ALLOCATION_FAIL; ++ } ++ } ++ ++ /* Set the address of each component of YUV420 */ ++ writel(ctx->phys_addr_yuv_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_PIC_SRC_ADDR_Y); ++ writel(ctx->phys_addr_yuv_buffer + ctx->buf_width * ctx->height, s3c_mfc_sfr_base_virt_addr + \ ++ S3C_MFC_PARAM_ENC_PIC_SRC_ADDR_CB); ++ writel(ctx->phys_addr_yuv_buffer + ((ctx->buf_width * ctx->height * 5) >> 2), \ ++ s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_PIC_SRC_ADDR_CR); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_PIC_ROT_MODE); ++ writel((ctx->enc_pic_option & 0x0000FFFF), s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_PIC_OPTION); ++ writel(ctx->phys_addr_stream_buffer, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_PIC_BB_START); ++ writel(ctx->stream_buffer_size, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_PIC_BB_SIZE); ++ ++ if (!s3c_mfc_issue_command(ctx->inst_no, ctx->codec_mode, PIC_RUN)) { ++ return S3C_MFC_INST_ERR_ENC_PIC_RUN_CMD_FAIL; ++ } ++ ++ ctx->enc_pic_option = 0; /* reset the encoding picture option at every picture */ ++ ctx->run_index = 0; ++ ctx->enc_change_framerate = 0; ++ ++ switch(ctx->inst_no) { ++ case 0: ++ bits_wr_ptr_value = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR0); ++ break; ++ case 1: ++ bits_wr_ptr_value = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR1); ++ break; ++ case 2: ++ bits_wr_ptr_value = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR2); ++ break; ++ case 3: ++ bits_wr_ptr_value = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR3); ++ break; ++ case 4: ++ bits_wr_ptr_value = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR4); ++ break; ++ case 5: ++ bits_wr_ptr_value = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR5); ++ break; ++ case 6: ++ bits_wr_ptr_value = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR6); ++ break; ++ case 7: ++ bits_wr_ptr_value = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR7); ++ break; ++ } ++ ++ *enc_data_size = bits_wr_ptr_value - ctx->phys_addr_stream_buffer; ++ *header_size = 0; ++ ++ if (hdr_buf_tmp) { ++ memmove(ctx->stream_buffer + hdr_size, ctx->stream_buffer, *enc_data_size); ++ ++ start = ctx->stream_buffer; ++ size = hdr_size + (*enc_data_size); ++ dma_cache_maint(start, size, DMA_TO_DEVICE); ++ ++ memcpy(ctx->stream_buffer, hdr_buf_tmp, hdr_size); ++ ++ start = ctx->stream_buffer; ++ size = hdr_size; ++ dma_cache_maint(start, size, DMA_TO_DEVICE); ++ ++ kfree(hdr_buf_tmp); ++ ++ *enc_data_size += hdr_size; ++ *header_size = hdr_size; ++ } ++ ++ /* changing state */ ++ /* state change to S3C_MFC_INST_STATE_ENC_PIC_RUN_LINE_BUF */ ++ S3C_MFC_INST_STATE_TRANSITION(ctx, S3C_MFC_INST_STATE_ENC_PIC_RUN_LINE_BUF); ++ ++ ++ return S3C_MFC_INST_RET_OK; ++} ++ ++/* hdr_code == 0: SPS */ ++/* hdr_code == 1: PPS */ ++/* hdr_code == 4: SEI */ ++int s3c_mfc_inst_enc_header(s3c_mfc_inst_context_t *ctx, int hdr_code, int hdr_num, unsigned int outbuf_physical_addr,\ ++ int outbuf_size, int *hdr_size) ++{ ++ unsigned int bit_wr_ptr_value = 0; ++ ++ ++ if (!S3C_MFC_INST_STATE_CHECK(ctx, S3C_MFC_INST_STATE_ENC_INITIALIZED) && \ ++ !S3C_MFC_INST_STATE_CHECK(ctx, S3C_MFC_INST_STATE_ENC_PIC_RUN_LINE_BUF)) { ++ mfc_err("mfc encoder instance is not initialized or not using the line buffer\n"); ++ return S3C_MFC_INST_ERR_STATE_CHK; ++ } ++ ++ if ((ctx->codec_mode != MP4_ENC) && (ctx->codec_mode != AVC_ENC)) { ++ return S3C_MFC_INST_ERR_WRONG_CODEC_MODE; ++ } ++ ++ /* Set the address of each component of YUV420 */ ++ writel(hdr_code, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_HEADER_CODE); ++ writel(outbuf_physical_addr & 0xFFFFFFFC, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_HEADER_BB_START); ++ writel(outbuf_size, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_HEADER_BB_SIZE); ++ ++ if (hdr_code == 4) /* SEI recovery point */ ++ writel(hdr_num, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_HEADER_NUM); ++ ++ if (!s3c_mfc_issue_command(ctx->inst_no, ctx->codec_mode, ENC_HEADER)) { ++ return S3C_MFC_INST_ERR_ENC_HEADER_CMD_FAIL; ++ } ++ ++ switch (ctx->inst_no) { ++ case 0: ++ bit_wr_ptr_value = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR0); ++ break; ++ case 1: ++ bit_wr_ptr_value = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR1); ++ break; ++ case 2: ++ bit_wr_ptr_value = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR2); ++ break; ++ case 3: ++ bit_wr_ptr_value = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR3); ++ break; ++ case 4: ++ bit_wr_ptr_value = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR4); ++ break; ++ case 5: ++ bit_wr_ptr_value = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR5); ++ break; ++ case 6: ++ bit_wr_ptr_value = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR6); ++ break; ++ case 7: ++ bit_wr_ptr_value = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BIT_STR_WR_PTR7); ++ break; ++ } ++ ++ *hdr_size = bit_wr_ptr_value - readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_HEADER_BB_START); ++ ++ ++ return S3C_MFC_INST_RET_OK; ++} ++ ++ ++int s3c_mfc_inst_enc_param_change(s3c_mfc_inst_context_t *ctx, unsigned int param_change_enable, \ ++ unsigned int param_change_val) ++{ ++ int num_mbs; /* number of MBs */ ++ int slices_mb; /* MB number of slice (only if S3C_MFC_SLICE_MODE_MULTIPLE is selected) */ ++ ++ ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_ENABLE); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_GOP_NUM); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_INTRA_QP); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_BITRATE); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_F_RATE); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_INTRA_REFRESH); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_SLICE_MODE); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_HEC_MODE); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_RESERVED0); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_RESERVED1); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_RESERVED2); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_RESERVED3); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_RESERVED4); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_RESERVED5); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_RESERVED6); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_RESERVED7); ++ writel(0x0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_ENC_CHANGE_SUCCESS); ++ writel(param_change_enable, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_ENABLE); ++ ++ if (param_change_enable == (1 << 0)) { /* gop number */ ++ if (param_change_val > 60) { ++ mfc_err("mfc encoder parameter change value is invalid\n"); ++ return S3C_MFC_INST_ERR_ENC_PARAM_CHANGE_INVALID_VALUE; ++ } ++ writel(param_change_val, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_GOP_NUM); ++ } else if (param_change_enable == (1 << 1)) { /* intra qp */ ++ if (((ctx->codec_mode == MP4_DEC || ctx->codec_mode == H263_DEC) && \ ++ (param_change_val == 0 || param_change_val > 31)) \ ++ || (ctx->codec_mode == AVC_DEC && param_change_val > 51)) { ++ mfc_err("mfc encoder parameter change value is invalid\n"); ++ return S3C_MFC_INST_ERR_ENC_PARAM_CHANGE_INVALID_VALUE; ++ } ++ writel(param_change_val, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_INTRA_QP); ++ } else if (param_change_enable == (1 << 2)) { /* bitrate */ ++ if (param_change_val > 0x07FFF) { ++ mfc_err("mfc encoder parameter change value is invalid\n"); ++ return S3C_MFC_INST_ERR_ENC_PARAM_CHANGE_INVALID_VALUE; ++ } ++ writel(param_change_val, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_BITRATE); ++ } else if (param_change_enable == (1 << 3)) { /* frame rate */ ++ writel(param_change_val, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_F_RATE); ++ ctx->enc_change_framerate = 1; ++ } else if (param_change_enable == (1 << 4)) { /* intra refresh */ ++ if (param_change_val > ((ctx->width * ctx->height) >> 8)) { ++ mfc_err("mfc encoder parameter change value is invalid\n"); ++ return S3C_MFC_INST_ERR_ENC_PARAM_CHANGE_INVALID_VALUE; ++ } ++ writel(param_change_val, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_INTRA_REFRESH); ++ } else if (param_change_enable == (1 << 5)) { /* slice mode */ ++ /* ++ * MB size is 16x16 -> width & height are divided by 16 to get number of MBs ++ * division by 16 == shift right by 4-bit ++ */ ++ num_mbs = (ctx->width >> 4) * (ctx->height >> 4); ++ ++ if (param_change_val > 256 || param_change_val > num_mbs) { ++ mfc_err("mfc encoder parameter change value is invalid\n"); ++ return S3C_MFC_INST_ERR_ENC_PARAM_CHANGE_INVALID_VALUE; ++ } ++ ++ if (param_change_val == 0) { ++ writel(S3C_MFC_SLICE_MODE_ONE, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_SLICE_MODE); ++ } else { ++ slices_mb = (num_mbs / param_change_val); ++ ctx->enc_num_slices = param_change_val; ++ ++ writel(S3C_MFC_SLICE_MODE_MULTIPLE | (1 << 1) | (slices_mb<< 2), \ ++ s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_ENC_CHANGE_SLICE_MODE); ++ } ++ } ++ ++ if (!s3c_mfc_issue_command(ctx->inst_no, ctx->codec_mode, ENC_PARAM_CHANGE)) { ++ return S3C_MFC_INST_ERR_ENC_HEADER_CMD_FAIL; ++ } ++ ++ ++ return S3C_MFC_INST_RET_OK; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_instance.h linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_instance.h +--- linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_instance.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_instance.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,182 @@ ++/* linux/driver/media/video/mfc/s3c_mfc_instance.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_MFC_INSTANCE_H ++#define _S3C_MFC_INSTANCE_H ++ ++ ++#include "s3c_mfc_base.h" ++#include "s3c_mfc_types.h" ++ ++ ++typedef enum ++{ ++ S3C_MFC_INST_STATE_DELETED = 0, /* instance is deleted */ ++ S3C_MFC_INST_STATE_CREATED = 10, /* instance is created but not initialized */ ++ S3C_MFC_INST_STATE_DEC_INITIALIZED = 20, /* instance is initialized for decoding */ ++ S3C_MFC_INST_STATE_DEC_PIC_RUN_LINE_BUF, ++ S3C_MFC_INST_STATE_ENC_INITIALIZED = 30, /* instance is initialized for encoding */ ++ S3C_MFC_INST_STATE_ENC_PIC_RUN_LINE_BUF, ++} s3c_mfc_instance_state_t; ++ ++ ++#define S3C_MFC_INST_STATE_PWR_OFF_FLAG 0x40000000 ++#define S3C_MFC_INST_STATE_BUF_FILL_REQ 0x80000000 ++ ++#define S3C_MFC_INST_STATE_TRANSITION(inst_ctx, state) ((inst_ctx)->state_var = (state)) ++#define S3C_MFC_INST_STATE(inst_ctx) ((inst_ctx)->state_var & 0x0FFFFFFF) ++#define S3C_MFC_INST_STATE_CHECK(inst_ctx, state) (((inst_ctx)->state_var & 0x0FFFFFFF) == (state)) ++ ++#define S3C_MFC_INST_STATE_PWR_OFF_FLAG_SET(inst_ctx) ((inst_ctx)->state_var |= S3C_MFC_INST_STATE_PWR_OFF_FLAG) ++#define S3C_MFC_INST_STATE_PWR_OFF_FLAG_CLEAR(inst_ctx) ((inst_ctx)->state_var &= ~S3C_MFC_INST_STATE_PWR_OFF_FLAG) ++#define S3C_MFC_INST_STATE_PWR_OFF_FLAG_CHECK(inst_ctx) ((inst_ctx)->state_var & S3C_MFC_INST_STATE_PWR_OFF_FLAG) ++#define S3C_MFC_INST_STATE_BUF_FILL_REQ_SET(inst_ctx) ((inst_ctx)->state_var |= S3C_MFC_INST_STATE_BUF_FILL_REQ) ++#define S3C_MFC_INST_STATE_BUF_FILL_REQ_CLEAR(inst_ctx) ((inst_ctx)->state_var &= ~S3C_MFC_INST_STATE_BUF_FILL_REQ) ++#define S3C_MFC_INST_STATE_BUF_FILL_REQ_CHECK(inst_ctx) ((inst_ctx)->state_var & S3C_MFC_INST_STATE_BUF_FILL_REQ) ++ ++ ++typedef struct ++{ ++ int inst_no; ++ ++ s3c_mfc_codec_mode_t codec_mode; ++ ++ unsigned char *stream_buffer; /* stream buffer pointer (virtual address) */ ++ unsigned int phys_addr_stream_buffer; /* stream buffer physical address */ ++ unsigned int stream_buffer_size; /* stream buffer size */ ++ ++ unsigned char *yuv_buffer; /* yuv buffer pointer (virtual address) */ ++ unsigned int phys_addr_yuv_buffer; /* yuv buffer physical address */ ++ unsigned int yuv_buffer_size; /* yuv buffer size */ ++ unsigned int mv_mbyte_addr; /* phyaical address of MV and MByte tables */ ++ ++ ++ int yuv_buffer_allocated; ++ ++ int width, height; ++ int buf_width, buf_height; /* buf_width is stride. */ ++ ++ int yuv_buffer_count; /* decoding case: RET_DEC_SEQ_FRAME_NEED_COUNT */ ++ /* encoding case: fixed at 2 (at lease 2 frame buffers) */ ++ ++ unsigned int post_rotation_mode; ++ ++ unsigned int dec_pic_option; /* 0-th bit : MP4ASP FLAG, */ ++ /* 1-st bit : MV REPORT ENABLE, */ ++ /* 2-nd bit : MBTYPE REPORT ENABLE */ ++ /* encoding configuration info */ ++ int frame_rate_residual; ++ int frame_rate_division; ++ int gop_number; ++ int bitrate; ++ ++ /* encoding configuration info (misc.) */ ++ int h263_annex; ++ int enc_num_slices; ++ ++ /* encoding picture option */ ++ unsigned int enc_pic_option; /* 0-th bit : S3C_ENC_PIC_OPT_SKIP, */ ++ /* 1-st bit : S3C_ENC_PIC_OPT_IDR, */ ++ /* 24-th bit: S3C_ENC_PIC_OPT_RECOVERY */ ++ unsigned int enc_change_framerate; /* when Frame Rate changing */ ++ int frame_num; /* DEC_PIC_FRAME_NUM */ ++ int run_index; /* DEC_PIC_RUN_IDX */ ++ ++ s3c_mfc_instance_state_t state_var; /* State Variable */ ++ ++#if (defined(DIVX_ENABLE) && (DIVX_ENABLE == 1)) ++ ++ unsigned int padding_size; ++ ++ /* RET_DEC_PIC_RUN_BAK_XXXXX : MP4ASP(DivX) related values that is returned */ ++ /* on DEC_PIC_RUN command. */ ++ /* RET_DEC_SEQ_INIT_BAK_XXXXX : MP4ASP(DivX) related values that is returned */ ++ /* on DEC_SEQ_INIT command. */ ++ /* They are maintained in the context structure variable. */ ++ unsigned int RET_DEC_SEQ_INIT_BAK_MP4ASP_VOP_TIME_RES; ++ unsigned int RET_DEC_PIC_RUN_BAK_BYTE_CONSUMED; ++ unsigned int RET_DEC_PIC_RUN_BAK_MP4ASP_FCODE; ++ unsigned int RET_DEC_PIC_RUN_BAK_MP4ASP_TIME_BASE_LAST; ++ unsigned int RET_DEC_PIC_RUN_BAK_MP4ASP_NONB_TIME_LAST; ++ unsigned int RET_DEC_PIC_RUN_BAK_MP4ASP_MP4ASP_TRD; ++#endif ++} s3c_mfc_inst_context_t; ++ ++ ++typedef struct { ++ int width; ++ int height; ++ int frame_rate_residual; ++ int frame_rate_division; ++ int gop_number; ++ int bitrate; ++} s3c_mfc_enc_info_t; ++ ++/* future work ++#define MFCINST_MP4_QPMAX 31 ++#define MFCINST_MP4_QPMIN 1 ++#define MFCINST_H264_QPMAX 51 ++#define MFCINST_H264_QPMIN 0 ++ ++#define MFCINST_GAMMA_FACTOR 0.75 ++#define MFCINST_GAMMA_FACTEE 32768 ++*/ ++ ++s3c_mfc_inst_context_t *s3c_mfc_inst_get_context(int inst_no); ++int s3c_mfc_inst_get_no(s3c_mfc_inst_context_t *ctx); ++BOOL s3c_mfc_inst_get_stream_buff_rw_ptrs(s3c_mfc_inst_context_t *ctx, unsigned char **read_ptr, unsigned char **write_ptr); ++ ++s3c_mfc_inst_context_t *s3c_mfc_inst_create(void); ++void s3c_mfc_inst_del(s3c_mfc_inst_context_t *ctx); ++ ++void s3c_mfc_inst_pow_off_state(s3c_mfc_inst_context_t *ctx); ++void s3c_mfc_inst_pow_on_state(s3c_mfc_inst_context_t *ctx); ++ ++int s3c_mfc_inst_init_dec(s3c_mfc_inst_context_t *ctx, s3c_mfc_codec_mode_t codec_mode, unsigned long strm_leng); ++int s3c_mfc_inst_dec(s3c_mfc_inst_context_t *ctx, unsigned long arg); ++ ++int s3c_mfc_instance_init_enc(s3c_mfc_inst_context_t *ctx, s3c_mfc_codec_mode_t codec_mode, s3c_mfc_enc_info_t *enc_info); ++int s3c_mfc_inst_enc(s3c_mfc_inst_context_t *ctx, int *enc_data_size, int *header_size); ++int s3c_mfc_inst_enc_header(s3c_mfc_inst_context_t *ctx, int hdr_code, int hdr_num, unsigned int outbuf_physical_addr, int outbuf_size, int *hdr_size); ++int s3c_mfc_inst_enc_param_change(s3c_mfc_inst_context_t *ctx, unsigned int param_change_enable, unsigned int param_change_val); ++ ++unsigned int s3c_mfc_inst_set_post_rotate(s3c_mfc_inst_context_t *ctx, unsigned int post_rotmode); ++ ++int s3c_mfc_inst_get_line_buff(s3c_mfc_inst_context_t *ctx, unsigned char **buffer, int *size); ++int s3c_mfc_inst_get_yuv_buff(s3c_mfc_inst_context_t *ctx, unsigned char **buffer, int *size); ++ ++#define S3C_MFC_INST_RET_OK (0) ++ ++#define S3C_MFC_INST_ERR_INVALID_PARAM (-1001) ++#define S3C_MFC_INST_ERR_STATE_CHK (-1002) ++#define S3C_MFC_INST_ERR_STATE_DELETED (-1003) ++#define S3C_MFC_INST_ERR_STATE_POWER_OFF (-1004) ++#define S3C_MFC_INST_ERR_WRONG_CODEC_MODE (-1005) ++ ++#define S3C_MFC_INST_ERR_DEC_INIT_CMD_FAIL (-2001) ++#define S3C_MFC_INST_ERR_DEC_PIC_RUN_CMD_FAIL (-2002) ++#define S3C_MFC_INST_ERR_DEC_DECODE_FAIL_ETC (-2011) ++#define S3C_MFC_INST_ERR_DEC_INVALID_STRM (-2012) ++#define S3C_MFC_INST_ERR_DEC_EOS (-2013) ++#define S3C_MFC_INST_ERR_DEC_BUF_FILL_SIZE_WRONG (-2014) ++ ++#define S3C_MFC_INST_ERR_ENC_INIT_CMD_FAIL (-3001) ++#define S3C_MFC_INST_ERR_ENC_PIC_RUN_CMD_FAIL (-3002) ++#define S3C_MFC_INST_ERR_ENC_HEADER_CMD_FAIL (-3003) ++#define S3C_MFC_INST_ERR_ENC_PARAM_CHANGE_INVALID_VALUE (-3011) ++ ++#define S3C_MFC_INST_ERR_MEMORY_ALLOCATION_FAIL (-4001) ++ ++#define S3C_MFC_INST_ERR_ETC (-9001) ++ ++ ++#endif /* _S3C_MFC_INSTANCE_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_intr_noti.h linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_intr_noti.h +--- linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_intr_noti.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_intr_noti.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,32 @@ ++/* linux/driver/media/video/mfc/s3c_mfc_intr_noti.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_MFC_INTR_NOTI_H ++#define _S3C_MFC_INTR_NOTI_H ++ ++#define S3C_MFC_INTR_NOTI_TIMEOUT 1000 ++ ++/* ++ * MFC Interrupt Enable Macro Definition ++ */ ++#define S3C_MFC_INTR_ENABLE_ALL 0xCCFF ++#define S3C_MFC_INTR_ENABLE_RESET 0xC00E ++ ++/* ++ * MFC Interrupt Reason Macro Definition ++ */ ++#define S3C_MFC_INTR_REASON_NULL 0x0000 ++#define S3C_MFC_INTR_REASON_BUFFER_EMPTY 0xC000 ++#define S3C_MFC_INTR_REASON_INTRNOTI_TIMEOUT (-99) ++ ++ ++#endif /* _S3C_MFC_INTR_NOTI_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_params.h linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_params.h +--- linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_params.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_params.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,143 @@ ++/* linux/driver/media/video/mfc/s3c_mfc_params.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_MFC_PARAMS_H ++#define _S3C_MFC_PARAMS_H ++ ++typedef struct { ++ int ret_code; /* [OUT] Return code */ ++ int in_width; /* [IN] width of YUV420 frame to be encoded */ ++ int in_height; /* [IN] height of YUV420 frame to be encoded */ ++ int in_bitrate; /* [IN] Encoding parameter: Bitrate (kbps) */ ++ int in_gopNum; /* [IN] Encoding parameter: GOP Number (interval of I-frame) */ ++ int in_frameRateRes; /* [IN] Encoding parameter: Frame rate (Res) */ ++ int in_frameRateDiv; /* [IN] Encoding parameter: Frame rate (Divider) */ ++ int in_intraqp; /* [IN] Encoding Parameter: Intra Quantization Parameter */ ++ int in_qpmax; /* [IN] Encoding Paramter: Maximum Quantization Paramter */ ++ float in_gamma; /* [IN] Encoding Paramter: Gamma Factor for Motion Estimation */ ++} s3c_mfc_enc_init_arg_t; ++ ++typedef struct { ++ int ret_code; /* [OUT] Return code */ ++ int out_encoded_size; /* [OUT] Length of Encoded video stream */ ++ int out_header_size; /* [OUT] Length of video stream header */ ++} s3c_mfc_enc_exe_arg_t; ++ ++typedef struct { ++ int ret_code; /* [OUT] Return code */ ++ int in_strmSize; /* [IN] Size of video stream filled in STRM_BUF */ ++ int out_width; /* [OUT] width of YUV420 frame */ ++ int out_height; /* [OUT] height of YUV420 frame */ ++ int out_buf_width; /* [OUT] buffer's width of YUV420 frame */ ++ int out_buf_height; /* [OUT] buffer's height of YUV420 frame */ ++} s3c_mfc_dec_init_arg_t; ++ ++typedef struct { ++ int ret_code; /* [OUT] Return code */ ++ int in_strmSize; /* [IN] Size of video stream filled in STRM_BUF */ ++} s3c_mfc_dec_exe_arg_t; ++ ++typedef struct { ++ int ret_code; /* [OUT] Return code */ ++ int in_usr_data; /* [IN] User data for translating Kernel-mode address to User-mode address */ ++ int in_usr_data2; ++ int out_buf_addr; /* [OUT] Buffer address */ ++ int out_buf_size; /* [OUT] Size of buffer address */ ++} s3c_mfc_get_buf_addr_arg_t; ++ ++typedef struct { ++ int ret_code; /* [OUT] Return code */ ++ int in_config_param; /* [IN] Configurable parameter type */ ++ int in_config_param2; ++ int out_config_value[2]; /* [IN] Values to get for the configurable parameter. */ ++ /* Maximum two integer values can be obtained; */ ++} s3c_mfc_get_config_arg_t; ++ ++typedef struct { ++ int ret_code; /* [OUT] Return code */ ++ int in_config_param; /* [IN] Configurable parameter type */ ++ int in_config_value[3]; /* [IN] Values to be set for the configurable parameter. */ ++ /* Maximum two integer values can be set. */ ++ int out_config_value_old[2]; /* [OUT] Old values of the configurable parameters */ ++} s3c_mfc_set_config_arg_t; ++ ++typedef struct { ++ int in_usr_mapped_addr; ++ int ret_code; /* [OUT] Return code */ ++ int mv_addr; ++ int mb_type_addr; ++ unsigned int mv_size; ++ unsigned int mb_type_size; ++ unsigned int mp4asp_vop_time_res; ++ unsigned int byte_consumed; ++ unsigned int mp4asp_fcode; ++ unsigned int mp4asp_time_base_last; ++ unsigned int mp4asp_nonb_time_last; ++ unsigned int mp4asp_trd; ++} s3c_mfc_get_mpeg4asp_arg_t; ++ ++ ++typedef union { ++ s3c_mfc_enc_init_arg_t enc_init; ++ s3c_mfc_enc_exe_arg_t enc_exe; ++ s3c_mfc_dec_init_arg_t dec_init; ++ s3c_mfc_dec_exe_arg_t dec_exe; ++ s3c_mfc_get_buf_addr_arg_t get_buf_addr; ++ s3c_mfc_get_config_arg_t get_config; ++ s3c_mfc_set_config_arg_t set_config; ++ s3c_mfc_get_mpeg4asp_arg_t mpeg4_asp_param; ++} s3c_mfc_args_t; ++ ++ ++#define S3C_MFC_GET_CONFIG_DEC_YUV_NEED_COUNT (0x0AA0C001) ++#define S3C_MFC_GET_CONFIG_DEC_MP4ASP_MV (0x0AA0C002) ++#define S3C_MFC_GET_CONFIG_DEC_MP4ASP_MBTYPE (0x0AA0C003) ++ ++#if (defined(DIVX_ENABLE) && (DIVX_ENABLE == 1)) ++#define S3C_MFC_GET_CONFIG_DEC_MP4ASP_FCODE (0x0AA0C011) ++#define S3C_MFC_GET_CONFIG_DEC_MP4ASP_VOP_TIME_RES (0x0AA0C012) ++#define S3C_MFC_GET_CONFIG_DEC_MP4ASP_TIME_BASE_LAST (0x0AA0C013) ++#define S3C_MFC_GET_CONFIG_DEC_MP4ASP_NONB_TIME_LAST (0x0AA0C014) ++#define S3C_MFC_GET_CONFIG_DEC_MP4ASP_TRD (0x0AA0C015) ++#define S3C_MFC_GET_CONFIG_DEC_BYTE_CONSUMED (0x0AA0C016) ++#endif ++ ++#define S3C_MFC_SET_CONFIG_DEC_ROTATE (0x0ABDE001) ++#define S3C_MFC_SET_CONFIG_DEC_OPTION (0x0ABDE002) ++ ++#define S3C_MFC_SET_CONFIG_ENC_H263_PARAM (0x0ABDC001) ++#define S3C_MFC_SET_CONFIG_ENC_SLICE_MODE (0x0ABDC002) ++#define S3C_MFC_SET_CONFIG_ENC_PARAM_CHANGE (0x0ABDC003) ++#define S3C_MFC_SET_CONFIG_ENC_CUR_PIC_OPT (0x0ABDC004) ++ ++#define S3C_MFC_SET_CACHE_CLEAN (0x0ABDD001) ++#define S3C_MFC_SET_CACHE_INVALIDATE (0x0ABDD002) ++#define S3C_MFC_SET_CACHE_CLEAN_INVALIDATE (0x0ABDD003) ++ ++#define S3C_MFC_SET_PADDING_SIZE (0x0ABDE003) ++ ++#define S3C_ENC_PARAM_GOP_NUM (0x7000A001) ++#define S3C_ENC_PARAM_INTRA_QP (0x7000A002) ++#define S3C_ENC_PARAM_BITRATE (0x7000A003) ++#define S3C_ENC_PARAM_F_RATE (0x7000A004) ++#define S3C_ENC_PARAM_INTRA_REF (0x7000A005) ++#define S3C_ENC_PARAM_SLICE_MODE (0x7000A006) ++ ++#define S3C_ENC_PIC_OPT_IDR (0x7000B001) ++#define S3C_ENC_PIC_OPT_SKIP (0x7000B002) ++#define S3C_ENC_PIC_OPT_RECOVERY (0x7000B003) ++ ++#define S3C_MFC_DEC_PIC_OPT_MP4ASP (0x7000C001) ++ ++ ++#endif /* _S3C_MFC_PARAMS_H */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_set_config.c linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_set_config.c +--- linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_set_config.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_set_config.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,281 @@ ++/* linux/driver/media/video/mfc/s3c_mfc_set_config.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "s3c_mfc_params.h" ++#include "s3c_mfc_instance.h" ++#include "s3c_mfc_config.h" ++#include "s3c_mfc_sfr.h" ++#include "s3c_mfc.h" ++ ++/* Input arguments for S3C_MFC_IOCTL_MFC_SET_CONFIG */ ++int s3c_mfc_get_config_params(s3c_mfc_inst_context_t *mfc_inst, s3c_mfc_args_t *args ) ++{ ++ int ret; ++ ++ ++ switch (args->get_config.in_config_param) { ++ case S3C_MFC_GET_CONFIG_DEC_YUV_NEED_COUNT: ++ args->get_config.out_config_value[0] = mfc_inst->yuv_buffer_count; ++ ret = S3C_MFC_INST_RET_OK; ++ ++ break; ++ ++ case S3C_MFC_GET_CONFIG_DEC_MP4ASP_MV: ++ case S3C_MFC_GET_CONFIG_DEC_MP4ASP_MBTYPE: ++ /* "S3C_MFC_GET_CONFIG_DEC_MP4ASP_MV" and "S3C_MFC_GET_CONFIG_DEC_MP4ASP_MBTYPE" are processed in the upper function. */ ++ ret = S3C_MFC_INST_RET_OK; ++ ++ break; ++ ++#if (defined(DIVX_ENABLE) && (DIVX_ENABLE == 1)) ++ case S3C_MFC_GET_CONFIG_DEC_BYTE_CONSUMED: ++ args->get_config.out_config_value[0] = (int)mfc_inst->RET_DEC_PIC_RUN_BAK_BYTE_CONSUMED; ++ mfc_debug("S3C_MFC_GET_CONFIG_DEC_BYTE_CONSUMED = %d\n", \ ++ (int)mfc_inst->RET_DEC_PIC_RUN_BAK_BYTE_CONSUMED); ++ ret = S3C_MFC_INST_RET_OK; ++ break; ++ ++ case S3C_MFC_GET_CONFIG_DEC_MP4ASP_FCODE: ++ args->get_config.out_config_value[0] = (int)mfc_inst->RET_DEC_PIC_RUN_BAK_MP4ASP_FCODE; ++ ret = S3C_MFC_INST_RET_OK; ++ break; ++ ++ case S3C_MFC_GET_CONFIG_DEC_MP4ASP_VOP_TIME_RES: ++ args->get_config.out_config_value[0] = (int)mfc_inst->RET_DEC_SEQ_INIT_BAK_MP4ASP_VOP_TIME_RES; ++ ret = S3C_MFC_INST_RET_OK; ++ break; ++ ++ case S3C_MFC_GET_CONFIG_DEC_MP4ASP_TIME_BASE_LAST: ++ args->get_config.out_config_value[0] = (int)mfc_inst->RET_DEC_PIC_RUN_BAK_MP4ASP_TIME_BASE_LAST; ++ ret = S3C_MFC_INST_RET_OK; ++ break; ++ ++ case S3C_MFC_GET_CONFIG_DEC_MP4ASP_NONB_TIME_LAST: ++ args->get_config.out_config_value[0] = (int)mfc_inst->RET_DEC_PIC_RUN_BAK_MP4ASP_NONB_TIME_LAST; ++ ret = S3C_MFC_INST_RET_OK; ++ break; ++ ++ case S3C_MFC_GET_CONFIG_DEC_MP4ASP_TRD: ++ args->get_config.out_config_value[0] = (int)mfc_inst->RET_DEC_PIC_RUN_BAK_MP4ASP_MP4ASP_TRD; ++ ret = S3C_MFC_INST_RET_OK; ++ break; ++#endif ++ ++ default: ++ ret = -1; ++ } ++ ++ ++ /* Output arguments for S3C_MFC_IOCTL_MFC_SET_CONFIG */ ++ args->get_config.ret_code = ret; ++ ++ return S3C_MFC_INST_RET_OK; ++} ++ ++/* Input arguments for S3C_MFC_IOCTL_MFC_SET_CONFIG */ ++int s3c_mfc_set_config_params(s3c_mfc_inst_context_t *mfc_inst, s3c_mfc_args_t *args) ++{ ++ int ret, size; ++ unsigned int param_change_enable = 0, param_change_val; ++ unsigned char *start; ++ unsigned int end, offset; ++ ++ switch (args->set_config.in_config_param) { ++ case S3C_MFC_SET_CONFIG_DEC_ROTATE: ++#if (S3C_MFC_ROTATE_ENABLE == 1) ++ args->set_config.out_config_value_old[0] ++ = s3c_mfc_inst_set_post_rotate(mfc_inst, args->set_config.in_config_value[0]); ++#else ++ mfc_err("S3C_MFC_IOCTL_MFC_SET_CONFIG with S3C_MFC_SET_CONFIG_DEC_ROTATE is not supported\n"); ++ mfc_err("please check if S3C_MFC_ROTATE_ENABLE is defined as 1 in MfcConfig.h file\n"); ++#endif ++ ret = S3C_MFC_INST_RET_OK; ++ break; ++ ++ case S3C_MFC_SET_CONFIG_ENC_H263_PARAM: ++ args->set_config.out_config_value_old[0] = mfc_inst->h263_annex; ++ mfc_inst->h263_annex = args->set_config.in_config_value[0]; ++ mfc_debug("parameter = 0x%x\n", mfc_inst->h263_annex); ++ ret = S3C_MFC_INST_RET_OK; ++ break; ++ ++ case S3C_MFC_SET_CONFIG_ENC_SLICE_MODE: ++ if (mfc_inst->enc_num_slices) { ++ args->set_config.out_config_value_old[0] = 1; ++ args->set_config.out_config_value_old[1] = mfc_inst->enc_num_slices; ++ } else { ++ args->set_config.out_config_value_old[0] = 0; ++ args->set_config.out_config_value_old[1] = 0; ++ } ++ ++ if (args->set_config.in_config_value[0]) ++ mfc_inst->enc_num_slices = args->set_config.in_config_value[1]; ++ else ++ mfc_inst->enc_num_slices = 0; ++ ++ ret = S3C_MFC_INST_RET_OK; ++ break; ++ ++ case S3C_MFC_SET_CONFIG_ENC_PARAM_CHANGE: ++ ++ switch (args->set_config.in_config_value[0]) { ++ case S3C_ENC_PARAM_GOP_NUM: ++ param_change_enable = (1 << 0); ++ break; ++ ++ case S3C_ENC_PARAM_INTRA_QP: ++ param_change_enable = (1 << 1); ++ break; ++ ++ case S3C_ENC_PARAM_BITRATE: ++ param_change_enable = (1 << 2); ++ break; ++ ++ case S3C_ENC_PARAM_F_RATE: ++ param_change_enable = (1 << 3); ++ break; ++ ++ case S3C_ENC_PARAM_INTRA_REF: ++ param_change_enable = (1 << 4); ++ break; ++ ++ case S3C_ENC_PARAM_SLICE_MODE: ++ param_change_enable = (1 << 5); ++ break; ++ ++ default: ++ break; ++ } ++ ++ param_change_val = args->set_config.in_config_value[1]; ++ ret = s3c_mfc_inst_enc_param_change(mfc_inst, param_change_enable, param_change_val); ++ ++ break; ++ ++ case S3C_MFC_SET_CONFIG_ENC_CUR_PIC_OPT: ++ ++ switch (args->set_config.in_config_value[0]) { ++ case S3C_ENC_PIC_OPT_IDR: ++ mfc_inst->enc_pic_option ^= (args->set_config.in_config_value[1] << 1); ++ break; ++ ++ case S3C_ENC_PIC_OPT_SKIP: ++ mfc_inst->enc_pic_option ^= (args->set_config.in_config_value[1] << 0); ++ break; ++ ++ case S3C_ENC_PIC_OPT_RECOVERY: ++ mfc_inst->enc_pic_option ^= (args->set_config.in_config_value[1] << 24); ++ break; ++ ++ default: ++ break; ++ } ++ ++ ret = S3C_MFC_INST_RET_OK; ++ break; ++ ++ case S3C_MFC_SET_CACHE_CLEAN: ++ /* ++ * in_config_value[0] : start address in user layer ++ * in_config_value[1] : offset ++ * in_config_value[2] : start address of stream buffer in user layer ++ */ ++ offset = args->set_config.in_config_value[0] - args->set_config.in_config_value[2]; ++ start = mfc_inst->stream_buffer + offset; ++ size = args->set_config.in_config_value[1]; ++ dma_cache_maint(start, size, DMA_TO_DEVICE); ++ /* ++ offset = args->set_config.in_config_value[0] - args->set_config.in_config_value[2]; ++ start = (unsigned int)mfc_inst->stream_buffer + offset; ++ end = start + args->set_config.in_config_value[1]; ++ dmac_clean_range((void *)start, (void *)end); ++ ++ start = (unsigned int)mfc_inst->phys_addr_stream_buffer + offset; ++ end = start + args->set_config.in_config_value[1]; ++ outer_clean_range((unsigned long)start, (unsigned long)end); ++ */ ++ ++ ret = S3C_MFC_INST_RET_OK; ++ break; ++ ++ case S3C_MFC_SET_CACHE_INVALIDATE: ++ /* ++ * in_config_value[0] : start address in user layer ++ * in_config_value[1] : offset ++ * in_config_value[2] : start address of stream buffer in user layer ++ */ ++ offset = args->set_config.in_config_value[0] - args->set_config.in_config_value[2]; ++ start = mfc_inst->stream_buffer + offset; ++ size = args->set_config.in_config_value[1]; ++ dma_cache_maint(start, size, DMA_FROM_DEVICE); ++ ++ /* ++ offset = args->set_config.in_config_value[0] - args->set_config.in_config_value[2]; ++ start = (unsigned int)mfc_inst->stream_buffer + offset; ++ end = start + args->set_config.in_config_value[1]; ++ dmac_inv_range((void *)start, (void *)end); ++ ++ start = (unsigned int)mfc_inst->phys_addr_stream_buffer + offset; ++ end = start + args->set_config.in_config_value[1]; ++ outer_inv_range((unsigned long)start, (unsigned long)end); ++ */ ++ ret = S3C_MFC_INST_RET_OK; ++ break; ++ ++ case S3C_MFC_SET_CACHE_CLEAN_INVALIDATE: ++ /* ++ * in_config_value[0] : start address in user layer ++ * in_config_value[1] : offset ++ * in_config_value[2] : start address of stream buffer in user layer ++ */ ++ offset = args->set_config.in_config_value[0] - args->set_config.in_config_value[2]; ++ start = mfc_inst->stream_buffer + offset; ++ size = args->set_config.in_config_value[1]; ++ dma_cache_maint(start, size, DMA_BIDIRECTIONAL); ++ ++ /* ++ offset = args->set_config.in_config_value[0] - args->set_config.in_config_value[2]; ++ start = (unsigned int)mfc_inst->stream_buffer + offset; ++ end = start + args->set_config.in_config_value[1]; ++ dmac_flush_range((void *)start, (void *)end); ++ ++ start = (unsigned int)mfc_inst->phys_addr_stream_buffer + offset; ++ end = start + args->set_config.in_config_value[1]; ++ outer_flush_range((unsigned long)start, (unsigned long)end); ++ */ ++ ret = S3C_MFC_INST_RET_OK; ++ break; ++ ++#if (defined(DIVX_ENABLE) && (DIVX_ENABLE == 1)) ++ case S3C_MFC_SET_PADDING_SIZE: ++ mfc_debug("padding size = %d\n", \ ++ args->set_config.in_config_value[0]); ++ mfc_inst->padding_size = args->set_config.in_config_value[0]; ++ ret = S3C_MFC_INST_RET_OK; ++ break; ++#endif ++ ++ default: ++ ret = -1; ++ } ++ ++ /* Output arguments for S3C_MFC_IOCTL_MFC_SET_CONFIG */ ++ args->set_config.ret_code = ret; ++ ++ return S3C_MFC_INST_RET_OK; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_sfr.c linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_sfr.c +--- linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_sfr.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_sfr.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,311 @@ ++/* linux/driver/media/video/mfc/s3c_mfc_sfr.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * This source file is for setting the MFC's registers. ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "s3c_mfc_sfr.h" ++#include "s3c_mfc_config.h" ++#include "prism_s.h" ++#include "s3c_mfc_intr_noti.h" ++#include "s3c_mfc.h" ++ ++extern wait_queue_head_t s3c_mfc_wait_queue; ++extern unsigned int s3c_mfc_intr_type; ++extern void __iomem *s3c_mfc_sfr_base_virt_addr; ++ ++ ++int s3c_mfc_sleep() ++{ ++ /* Wait until finish executing command. */ ++ while (readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BUSY_FLAG) != 0) ++ udelay(1); ++ ++ /* Issue Sleep Command. */ ++ writel(0x01, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BUSY_FLAG); ++ writel(0x0A, s3c_mfc_sfr_base_virt_addr + S3C_MFC_RUN_CMD); ++ ++ while (readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BUSY_FLAG) != 0) ++ udelay(1); ++ ++ return 1; ++} ++ ++int s3c_mfc_wakeup() ++{ ++ /* Bit processor gets started. */ ++ writel(0x01, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BUSY_FLAG); ++ writel(0x01, s3c_mfc_sfr_base_virt_addr + S3C_MFC_CODE_RUN); ++ ++ while (readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BUSY_FLAG) != 0) ++ udelay(1); ++ ++ /* Bit processor wakes up. */ ++ writel(0x01, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BUSY_FLAG); ++ writel(0x0B, s3c_mfc_sfr_base_virt_addr + S3C_MFC_RUN_CMD); ++ ++ while (readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BUSY_FLAG) != 0) ++ udelay(1); ++ ++ return 1; ++} ++ ++ ++static char *s3c_mfc_get_cmd_string(s3c_mfc_command_t mfc_cmd) ++{ ++ switch ((int)mfc_cmd) { ++ case SEQ_INIT: ++ return "SEQ_INIT"; ++ ++ case SEQ_END: ++ return "SEQ_END"; ++ ++ case PIC_RUN: ++ return "PIC_RUN"; ++ ++ case SET_FRAME_BUF: ++ return "SET_FRAME_BUF"; ++ ++ case ENC_HEADER: ++ return "ENC_HEADER"; ++ ++ case ENC_PARA_SET: ++ return "ENC_PARA_SET"; ++ ++ case DEC_PARA_SET: ++ return "DEC_PARA_SET"; ++ ++ case GET_FW_VER: ++ return "GET_FW_VER"; ++ ++ } ++ ++ return "UNDEF CMD"; ++} ++ ++static int s3c_mfc_wait_for_ready(void) ++{ ++ int i; ++ ++ for (i = 0; i < 1000; i++) { ++ if (readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BUSY_FLAG) == 0) { ++ return TRUE; ++ } ++ udelay(100); /* 1/1000 second */ ++ } ++ ++ mfc_debug("timeout in waiting for the bitprocessor available\n"); ++ ++ return FALSE; ++} ++ ++ ++int s3c_mfc_get_firmware_ver(void) ++{ ++ unsigned int prd_no, ver_no; ++ ++ s3c_mfc_wait_for_ready(); ++ ++ writel(GET_FW_VER, s3c_mfc_sfr_base_virt_addr + S3C_MFC_RUN_CMD); ++ ++ mfc_debug("GET_FW_VER command was issued\n"); ++ ++ s3c_mfc_wait_for_ready(); ++ ++ prd_no = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_DEC_SEQ_SUCCESS) >> 16; ++ ver_no = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_DEC_SEQ_SUCCESS) & 0x00FFFF; ++ ++ mfc_debug("GET_FW_VER => 0x%x, 0x%x\n", prd_no, ver_no); ++ mfc_debug("BUSY_FLAG => %d\n", \ ++ readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_BUSY_FLAG)); ++ ++ return readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARAM_RET_DEC_SEQ_SUCCESS); ++} ++ ++ ++BOOL s3c_mfc_issue_command(int inst_no, s3c_mfc_codec_mode_t codec_mode, s3c_mfc_command_t mfc_cmd) ++{ ++ unsigned int intr_reason; ++ ++ writel(inst_no, s3c_mfc_sfr_base_virt_addr + S3C_MFC_RUN_INDEX); ++ ++ if (codec_mode == H263_DEC) { ++ writel(MP4_DEC, s3c_mfc_sfr_base_virt_addr + S3C_MFC_RUN_COD_STD); ++ } else if (codec_mode == H263_ENC) { ++ writel(MP4_ENC, s3c_mfc_sfr_base_virt_addr + S3C_MFC_RUN_COD_STD); ++ } else { ++ writel(codec_mode, s3c_mfc_sfr_base_virt_addr + S3C_MFC_RUN_COD_STD); ++ } ++ ++ switch (mfc_cmd) { ++ case PIC_RUN: ++ case SEQ_INIT: ++ case SEQ_END: ++ writel(mfc_cmd, s3c_mfc_sfr_base_virt_addr + S3C_MFC_RUN_CMD); ++ ++ if(interruptible_sleep_on_timeout(&s3c_mfc_wait_queue, 500) == 0) { ++ s3c_mfc_stream_end(); ++ return FALSE; ++ } ++ ++ intr_reason = s3c_mfc_intr_type; ++ ++ if (intr_reason == S3C_MFC_INTR_REASON_INTRNOTI_TIMEOUT) { ++ mfc_err("command = %s, WaitInterruptNotification returns TIMEOUT\n", \ ++ s3c_mfc_get_cmd_string(mfc_cmd)); ++ return FALSE; ++ } ++ if (intr_reason & S3C_MFC_INTR_REASON_BUFFER_EMPTY) { ++ mfc_err("command = %s, BUFFER EMPTY interrupt was raised\n", \ ++ s3c_mfc_get_cmd_string(mfc_cmd)); ++ return FALSE; ++ } ++ break; ++ ++ default: ++ if (s3c_mfc_wait_for_ready() == FALSE) { ++ mfc_err("command = %s, bitprocessor is busy before issuing the command\n", \ ++ s3c_mfc_get_cmd_string(mfc_cmd)); ++ return FALSE; ++ } ++ ++ writel(mfc_cmd, s3c_mfc_sfr_base_virt_addr + S3C_MFC_RUN_CMD); ++ s3c_mfc_wait_for_ready(); ++ ++ } ++ ++ return TRUE; ++} ++ ++ ++/* Perform the SW_RESET */ ++void s3c_mfc_reset(void) ++{ ++ writel(0x00, s3c_mfc_sfr_base_virt_addr + S3C_MFC_SFR_SW_RESET_ADDR); ++ writel(0x01, s3c_mfc_sfr_base_virt_addr + S3C_MFC_SFR_SW_RESET_ADDR); ++ ++ /* Interrupt is enabled for PIC_RUN command and empty/full STRM_BUF status. */ ++ writel(S3C_MFC_INTR_ENABLE_RESET, s3c_mfc_sfr_base_virt_addr + S3C_MFC_INT_ENABLE); ++ writel(S3C_MFC_INTR_REASON_NULL, s3c_mfc_sfr_base_virt_addr + S3C_MFC_INT_REASON); ++ writel(0x1, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BITS_INT_CLEAR); ++} ++ ++/* ++ * Clear the MFC Interrupt ++ * After catching the MFC Interrupt, ++ * it is required to call this functions for clearing the interrupt-related register. ++ */ ++void s3c_mfc_clear_intr(void) ++{ ++ writel(0x1, s3c_mfc_sfr_base_virt_addr + S3C_MFC_BITS_INT_CLEAR); ++ writel(S3C_MFC_INTR_REASON_NULL, s3c_mfc_sfr_base_virt_addr + S3C_MFC_INT_REASON); ++} ++ ++/* Check INT_REASON register of MFC (the interrupt reason register) */ ++unsigned int s3c_mfc_intr_reason(void) ++{ ++ return readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_INT_REASON); ++} ++ ++/* ++ * Set the MFC's SFR of DEC_FUNC_CTRL to 1. ++ * It means that the data will not be added more to the STRM_BUF. ++ * It is required in RING_BUF mode (VC-1 DEC). ++ */ ++void s3c_mfc_set_eos(int buffer_mode) ++{ ++ if (buffer_mode == 1) { ++ writel(1 << 1, s3c_mfc_sfr_base_virt_addr + S3C_MFC_DEC_FUNC_CTRL); ++ } else { ++ writel(1, s3c_mfc_sfr_base_virt_addr + S3C_MFC_DEC_FUNC_CTRL); ++ } ++} ++ ++void s3c_mfc_stream_end() ++{ ++ writel(0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_DEC_FUNC_CTRL); ++} ++ ++void s3c_mfc_download_boot_firmware(void) ++{ ++ unsigned int i; ++ unsigned int data; ++ ++ /* Download the Boot code into MFC's internal memory */ ++ for (i = 0; i < 512; i++) { ++ data = s3c_mfc_bit_code[i]; ++ writel(((i<<16) | data), s3c_mfc_sfr_base_virt_addr + S3C_MFC_CODE_DN_LOAD); ++ } ++ ++} ++ ++void s3c_mfc_start_bit_processor(void) ++{ ++ writel(0x01, s3c_mfc_sfr_base_virt_addr + S3C_MFC_CODE_RUN); ++} ++ ++ ++void s3c_mfc_stop_bit_processor(void) ++{ ++ writel(0x00, s3c_mfc_sfr_base_virt_addr + S3C_MFC_CODE_RUN); ++} ++ ++void s3c_mfc_config_sfr_bitproc_buffer(void) ++{ ++ unsigned int code; ++ ++ /* ++ * CODE BUFFER ADDRESS (BASE + 0x100) ++ * : Located from the Base address of the BIT PROCESSOR'S Firmware code segment ++ */ ++ writel(S3C_MFC_BASEADDR_BITPROC_BUF, s3c_mfc_sfr_base_virt_addr + S3C_MFC_CODE_BUF_ADDR); ++ ++ ++ /* ++ * WORKING BUFFER ADDRESS (BASE + 0x104) ++ * : Located from the next to the BIT PROCESSOR'S Firmware code segment ++ */ ++ code = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_CODE_BUF_ADDR); ++ writel(code + S3C_MFC_CODE_BUF_SIZE, s3c_mfc_sfr_base_virt_addr + S3C_MFC_WORK_BUF_ADDR); ++ ++ ++ /* PARAMETER BUFFER ADDRESS (BASE + 0x108) ++ * : Located from the next to the WORKING BUFFER ++ */ ++ code = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_WORK_BUF_ADDR); ++ writel(code + S3C_MFC_WORK_BUF_SIZE, s3c_mfc_sfr_base_virt_addr + S3C_MFC_PARA_BUF_ADDR); ++} ++ ++void s3c_mfc_config_sfr_ctrl_opts(void) ++{ ++ unsigned int uRegData; ++ ++ /* BIT STREAM BUFFER CONTROL (BASE + 0x10C) */ ++ uRegData = readl(s3c_mfc_sfr_base_virt_addr + S3C_MFC_STRM_BUF_CTRL); ++ writel((uRegData & ~(0x03)) | S3C_MFC_BUF_STATUS_FULL_EMPTY_CHECK_BIT | S3C_MFC_STREAM_ENDIAN_LITTLE, \ ++ s3c_mfc_sfr_base_virt_addr + S3C_MFC_STRM_BUF_CTRL); ++ ++ /* FRAME MEMORY CONTROL (BASE + 0x110) */ ++ writel(S3C_MFC_YUV_MEM_ENDIAN_LITTLE, s3c_mfc_sfr_base_virt_addr + S3C_MFC_FRME_BUF_CTRL); ++ ++ ++ /* DECODER FUNCTION CONTROL (BASE + 0x114) */ ++ writel(0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_DEC_FUNC_CTRL); ++ ++ /* WORK BUFFER CONTROL (BASE + 0x11C) */ ++ writel(0, s3c_mfc_sfr_base_virt_addr + S3C_MFC_WORK_BUF_CTRL); ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_sfr.h linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_sfr.h +--- linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_sfr.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_sfr.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,36 @@ ++/* linux/driver/media/video/mfc/s3c_mfc_sfr.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_MFC_SFR_H ++#define _S3C_MFC_SFR_H ++ ++#include "s3c_mfc_types.h" ++#include "s3c_mfc_base.h" ++ ++int s3c_mfc_sleep(void); ++int s3c_mfc_wakeup(void); ++BOOL s3c_mfc_issue_command(int inst_no, s3c_mfc_codec_mode_t codec_mode, s3c_mfc_command_t mfc_cmd); ++int s3c_mfc_get_firmware_ver(void); ++ ++void s3c_mfc_reset(void); ++void s3c_mfc_clear_intr(void); ++unsigned int s3c_mfc_intr_reason(void); ++void s3c_mfc_set_eos(int buffer_mode); ++void s3c_mfc_stream_end(void); ++void s3c_mfc_download_boot_firmware(void); ++void s3c_mfc_start_bit_processor(void); ++void s3c_mfc_stop_bit_processor(void); ++void s3c_mfc_config_sfr_bitproc_buffer(void); ++void s3c_mfc_config_sfr_ctrl_opts(void); ++ ++ ++#endif /* _S3C_MFC_SFR_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_types.h linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_types.h +--- linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_types.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_types.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,21 @@ ++/* linux/driver/media/video/mfc/s3c_mfc_types.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_MFC_TYPES_H ++#define _S3C_MFC_TYPES_H ++ ++#include ++ ++typedef enum {FALSE, TRUE} BOOL; ++ ++ ++#endif /* _S3C_MFC_TYPES_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_yuv_buf_manager.c linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_yuv_buf_manager.c +--- linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_yuv_buf_manager.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_yuv_buf_manager.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,300 @@ ++/* linux/driver/media/video/mfc/s3c_mfc_yuv_buf_manager.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * This source file is for managing the YUV buffer. ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include "s3c_mfc_yuv_buf_manager.h" ++#include "s3c_mfc_types.h" ++#include "s3c_mfc.h" ++ ++/* ++ * The size in bytes of the BUF_SEGMENT. ++ * The buffers are fragemented into the segment unit of this size. ++ */ ++#define S3C_MFC_BUF_SEGMENT_SIZE 1024 ++ ++ ++typedef struct { ++ unsigned char *pBaseAddr; ++ int idx_commit; ++} s3c_mfc_segment_info_t; ++ ++ ++typedef struct { ++ int index_base_seg; ++ int num_segs; ++} s3c_mfc_commit_info_t; ++ ++ ++static s3c_mfc_segment_info_t *s3c_mfc_segment_info = NULL; ++static s3c_mfc_commit_info_t *s3c_mfc_commit_info = NULL; ++ ++static unsigned char *s3c_mfc_buffer_base = NULL; ++static int s3c_mfc_buffer_size = 0; ++static int s3c_mfc_num_segments = 0; ++ ++ ++/* ++ * int s3c_mfc_init_yuvbuf_mgr(unsigned char *pBufBase, int nBufSize) ++ * ++ * Description ++ * This function initializes the MfcFramBufMgr(Buffer Segment Manager) ++ * Parameters ++ * pBufBase [IN]: pointer to the buffer which will be managed by this MfcFramBufMgr functions. ++ * nBufSize [IN]: buffer size in bytes ++ * Return Value ++ * 1 : Success ++ * 0 : Fail ++ */ ++BOOL s3c_mfc_init_yuvbuf_mgr(unsigned char *buffer_base, int buffer_size) ++{ ++ int i; ++ ++ if (buffer_base == NULL || buffer_size == 0) ++ return FALSE; ++ ++ if ((s3c_mfc_buffer_base != NULL) && (s3c_mfc_buffer_size != 0)) { ++ if ((buffer_base == s3c_mfc_buffer_base) && (buffer_size == s3c_mfc_buffer_size)) ++ return TRUE; ++ ++ s3c_mfc_yuv_buffer_mgr_final(); ++ } ++ ++ s3c_mfc_buffer_base = buffer_base; ++ s3c_mfc_buffer_size = buffer_size; ++ s3c_mfc_num_segments = buffer_size / S3C_MFC_BUF_SEGMENT_SIZE; ++ ++ s3c_mfc_segment_info = (s3c_mfc_segment_info_t *)kmalloc(s3c_mfc_num_segments * sizeof(s3c_mfc_segment_info_t), \ ++ GFP_KERNEL); ++ for (i = 0; i < s3c_mfc_num_segments; i++) { ++ s3c_mfc_segment_info[i].pBaseAddr = buffer_base + (i * S3C_MFC_BUF_SEGMENT_SIZE); ++ s3c_mfc_segment_info[i].idx_commit = 0; ++ } ++ ++ s3c_mfc_commit_info = (s3c_mfc_commit_info_t *)kmalloc(s3c_mfc_num_segments * sizeof(s3c_mfc_commit_info_t), \ ++ GFP_KERNEL); ++ for (i = 0; i < s3c_mfc_num_segments; i++) { ++ s3c_mfc_commit_info[i].index_base_seg = -1; ++ s3c_mfc_commit_info[i].num_segs = 0; ++ } ++ ++ return TRUE; ++} ++ ++ ++void s3c_mfc_yuv_buffer_mgr_final() ++{ ++ if (s3c_mfc_segment_info != NULL) { ++ kfree(s3c_mfc_segment_info); ++ s3c_mfc_segment_info = NULL; ++ } ++ ++ if (s3c_mfc_commit_info != NULL) { ++ kfree(s3c_mfc_commit_info); ++ s3c_mfc_commit_info = NULL; ++ } ++ ++ s3c_mfc_buffer_base = NULL; ++ s3c_mfc_buffer_size = 0; ++ s3c_mfc_num_segments = 0; ++} ++ ++/* ++ * unsigned char *s3c_mfc_commit_yuv_buffer_mgr(int idx_commit, int commit_size) ++ * ++ * Description ++ * This function requests the commit for commit_size buffer to be reserved. ++ * Parameters ++ * idx_commit [IN]: pointer to the buffer which will be managed by this MfcFramBufMgr functions. ++ * commit_size [IN]: commit size in bytes ++ * Return Value ++ * NULL : Failed to commit (Wrong parameters, commit_size too big, and so on.) ++ * Otherwise it returns the pointer which was committed. ++ */ ++unsigned char *s3c_mfc_commit_yuv_buffer_mgr(int idx_commit, int commit_size) ++{ ++ int i, j; ++ int num_yuv_buf_seg; ++ ++ if (s3c_mfc_segment_info == NULL || s3c_mfc_commit_info == NULL) { ++ return NULL; ++ } ++ ++ /* check parameters */ ++ if (idx_commit < 0 || idx_commit >= s3c_mfc_num_segments) ++ return NULL; ++ if (commit_size <= 0 || commit_size > s3c_mfc_buffer_size) ++ return NULL; ++ ++ if (s3c_mfc_commit_info[idx_commit].index_base_seg != -1) ++ return NULL; ++ ++ ++ if ((commit_size % S3C_MFC_BUF_SEGMENT_SIZE) == 0) ++ num_yuv_buf_seg = commit_size / S3C_MFC_BUF_SEGMENT_SIZE; ++ else ++ num_yuv_buf_seg = (commit_size / S3C_MFC_BUF_SEGMENT_SIZE) + 1; ++ ++ for (i=0; i<(s3c_mfc_num_segments - num_yuv_buf_seg); i++) { ++ if (s3c_mfc_segment_info[i].idx_commit != 0) ++ continue; ++ ++ for (j=0; j= s3c_mfc_num_segments) ++ return; ++ ++ if (s3c_mfc_commit_info[idx_commit].index_base_seg == -1) ++ return; ++ ++ ++ index_base_seg = s3c_mfc_commit_info[idx_commit].index_base_seg; ++ num_yuv_buf_seg = s3c_mfc_commit_info[idx_commit].num_segs; ++ ++ for (i = 0; i < num_yuv_buf_seg; i++) { ++ s3c_mfc_segment_info[index_base_seg + i].idx_commit = 0; ++ } ++ ++ ++ s3c_mfc_commit_info[idx_commit].index_base_seg = -1; ++ s3c_mfc_commit_info[idx_commit].num_segs = 0; ++ ++} ++ ++/* ++ * unsigned char *s3c_mfc_get_yuv_buffer(int idx_commit) ++ * ++ * Description ++ * This function obtains the committed buffer of 'idx_commit'. ++ * Parameters ++ * idx_commit [IN]: commit index of the buffer which will be obtained ++ * Return Value ++ * NULL : Failed to get the indicated buffer (Wrong parameters, not committed, and so on.) ++ * Otherwise it returns the pointer which was committed. ++ */ ++unsigned char *s3c_mfc_get_yuv_buffer(int idx_commit) ++{ ++ int index_base_seg; ++ ++ if (s3c_mfc_segment_info == NULL || s3c_mfc_commit_info == NULL) ++ return NULL; ++ ++ if (idx_commit < 0 || idx_commit >= s3c_mfc_num_segments) ++ return NULL; ++ ++ if (s3c_mfc_commit_info[idx_commit].index_base_seg == -1) ++ return NULL; ++ ++ index_base_seg = s3c_mfc_commit_info[idx_commit].index_base_seg; ++ ++ return s3c_mfc_segment_info[index_base_seg].pBaseAddr; ++} ++ ++/* ++ * int s3c_mfc_get_yuv_buffer_size(int idx_commit) ++ * ++ * Description ++ * This function obtains the size of the committed buffer of 'idx_commit'. ++ * Parameters ++ * idx_commit [IN]: commit index of the buffer which will be obtained ++ * Return Value ++ * 0 : Failed to get the size of indicated buffer (Wrong parameters, not committed, and so on.) ++ * Otherwise it returns the size of the buffer. ++ * Note that the size is multiples of the S3C_MFC_BUF_SEGMENT_SIZE. ++ */ ++int s3c_mfc_get_yuv_buffer_size(int idx_commit) ++{ ++ if (s3c_mfc_segment_info == NULL || s3c_mfc_commit_info == NULL) ++ return 0; ++ ++ if (idx_commit < 0 || idx_commit >= s3c_mfc_num_segments) ++ return 0; ++ ++ if (s3c_mfc_commit_info[idx_commit].index_base_seg == -1) ++ return 0; ++ ++ return (s3c_mfc_commit_info[idx_commit].num_segs * S3C_MFC_BUF_SEGMENT_SIZE); ++} ++ ++/* ++ * void s3c_mfc_print_commit_yuv_buffer_info() ++ * ++ * Description ++ * This function prints the commited information on the console screen. ++ * Parameters ++ * None ++ * Return Value ++ * None ++ */ ++void s3c_mfc_print_commit_yuv_buffer_info() ++{ ++ int i; ++ ++ if (s3c_mfc_segment_info == NULL || s3c_mfc_commit_info == NULL) { ++ mfc_err("fram buffer manager is not initialized\n"); ++ return; ++ } ++ ++ ++ for (i = 0; i < s3c_mfc_num_segments; i++) { ++ if (s3c_mfc_commit_info[i].index_base_seg != -1) { ++ mfc_debug("commit index = %03d, base segment index = %d\n", \ ++ i, s3c_mfc_commit_info[i].index_base_seg); ++ mfc_debug("commit index = %03d, number of segment = %d\n", \ ++ i, s3c_mfc_commit_info[i].num_segs); ++ } ++ } ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_yuv_buf_manager.h linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_yuv_buf_manager.h +--- linux-2.6.28/drivers/media/video/samsung/mfc10/s3c_mfc_yuv_buf_manager.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc10/s3c_mfc_yuv_buf_manager.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,30 @@ ++/* linux/driver/media/video/mfc/s3c_mfc_yuv_buf_manager.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_MFC_YUV_BUF_MANAGER_H ++#define _S3C_MFC_YUV_BUF_MANAGER_H ++ ++#include "s3c_mfc_types.h" ++ ++BOOL s3c_mfc_init_yuvbuf_mgr(unsigned char *pBufBase, int nBufSize); ++void s3c_mfc_yuv_buffer_mgr_final(void); ++ ++unsigned char *s3c_mfc_commit_yuv_buffer_mgr(int idx_commit, int commit_size); ++void s3c_mfc_free_yuv_buffer_mgr(int idx_commit); ++ ++unsigned char *s3c_mfc_get_yuv_buffer(int idx_commit); ++int s3c_mfc_get_yuv_buffer_size(int idx_commit); ++ ++void s3c_mfc_print_commit_yuv_buffer_info(void); ++ ++ ++#endif /* _S3C_MFC_YUV_BUF_MANAGER_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc40/Kconfig linux-2.6.28.6/drivers/media/video/samsung/mfc40/Kconfig +--- linux-2.6.28/drivers/media/video/samsung/mfc40/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/Kconfig 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,21 @@ ++# ++# Configuration for Multi Format Codecs (MFC) ++# ++# ++config VIDEO_MFC40 ++ bool "Samsung MFC (Multi Format Codec - FIMV 4.0) Driver" ++ depends on VIDEO_SAMSUNG && CPU_S5PC100 ++ default n ++ ---help--- ++ This is a Samsung Multi Format Codecs (MFC) FIMV V4.0 - driver for Samsung S5PC100 ++ ++config VIDEO_MFC_MAX_INSTANCE ++ int "Maximum size of MFC instance (1-4)" ++ range 1 4 ++ depends on VIDEO_MFC40 && ARCH_S5PC1XX ++ default 1 ++ ++config VIDEO_MFC40_DEBUG ++ bool "print MFC debug message" ++ depends on VIDEO_MFC40 ++ default n +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc40/Makefile linux-2.6.28.6/drivers/media/video/samsung/mfc40/Makefile +--- linux-2.6.28/drivers/media/video/samsung/mfc40/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/Makefile 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,8 @@ ++obj-$(CONFIG_VIDEO_MFC40) += h263_dec_fw.o h264_dec_fw.o h264_enc_fw.o mp2_dec_fw.o mp4_dec_fw.o mp4_enc_fw.o s3c-mfc.o s3c_mfc_buffer_manager.o s3c_mfc_common.o s3c_mfc_intr.o s3c_mfc_memory.o s3c_mfc_opr.o vc1_dec_fw.o command_control_fw.o ++ ++EXTRA_CFLAGS += -DLINUX ++EXTRA_CFLAGS += -DDIVX_ENABLE ++ ++ifeq ($(CONFIG_VIDEO_MFC40_DEBUG),y) ++EXTRA_CFLAGS += -DDEBUG ++endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc40/command_control_fw.c linux-2.6.28.6/drivers/media/video/samsung/mfc40/command_control_fw.c +--- linux-2.6.28/drivers/media/video/samsung/mfc40/command_control_fw.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/command_control_fw.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,388 @@ ++/* ++ * drivers/media/video/samsung/mfc40/command_control_fw.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++ ++const unsigned char cmd_ctrl_fw[7432] = { ++0x31, 0x00, 0x00, 0xea, 0x06, 0x00, 0x00, 0xea, 0x0b, 0x00, 0x00, 0xea, 0x10, 0x00, 0x00, 0xea, 0x15, 0x00, 0x00, 0xea, ++0xfe, 0xff, 0xff, 0xea, 0x19, 0x00, 0x00, 0xea, 0x1e, 0x00, 0x00, 0xea, 0x23, 0x00, 0x00, 0xea, 0x04, 0xd0, 0x4d, 0xe2, ++0x01, 0x00, 0x2d, 0xe9, 0xa0, 0x00, 0x9f, 0xe5, 0x00, 0x00, 0x90, 0xe5, 0x04, 0x00, 0x8d, 0xe5, 0x01, 0x80, 0xbd, 0xe8, ++0x04, 0xd0, 0x4d, 0xe2, 0x01, 0x00, 0x2d, 0xe9, 0x8c, 0x00, 0x9f, 0xe5, 0x00, 0x00, 0x90, 0xe5, 0x04, 0x00, 0x8d, 0xe5, ++0x01, 0x80, 0xbd, 0xe8, 0x04, 0xd0, 0x4d, 0xe2, 0x01, 0x00, 0x2d, 0xe9, 0x78, 0x00, 0x9f, 0xe5, 0x00, 0x00, 0x90, 0xe5, ++0x04, 0x00, 0x8d, 0xe5, 0x01, 0x80, 0xbd, 0xe8, 0x04, 0xd0, 0x4d, 0xe2, 0x01, 0x00, 0x2d, 0xe9, 0x64, 0x00, 0x9f, 0xe5, ++0x00, 0x00, 0x90, 0xe5, 0x04, 0x00, 0x8d, 0xe5, 0x01, 0x80, 0xbd, 0xe8, 0x04, 0xd0, 0x4d, 0xe2, 0x01, 0x00, 0x2d, 0xe9, ++0x50, 0x00, 0x9f, 0xe5, 0x00, 0x00, 0x90, 0xe5, 0x04, 0x00, 0x8d, 0xe5, 0x01, 0x80, 0xbd, 0xe8, 0x04, 0xd0, 0x4d, 0xe2, ++0x01, 0x00, 0x2d, 0xe9, 0x3c, 0x00, 0x9f, 0xe5, 0x00, 0x00, 0x90, 0xe5, 0x04, 0x00, 0x8d, 0xe5, 0x01, 0x80, 0xbd, 0xe8, ++0x04, 0xd0, 0x4d, 0xe2, 0x01, 0x00, 0x2d, 0xe9, 0x28, 0x00, 0x9f, 0xe5, 0x00, 0x00, 0x90, 0xe5, 0x04, 0x00, 0x8d, 0xe5, ++0x01, 0x80, 0xbd, 0xe8, 0x07, 0x00, 0x00, 0xeb, 0xfe, 0xff, 0xff, 0xea, 0x04, 0x3f, 0x01, 0x00, 0x08, 0x3f, 0x01, 0x00, ++0x0c, 0x3f, 0x01, 0x00, 0x10, 0x3f, 0x01, 0x00, 0x18, 0x3f, 0x01, 0x00, 0x1c, 0x3f, 0x01, 0x00, 0x20, 0x3f, 0x01, 0x00, ++0x00, 0x00, 0x00, 0xea, 0xa5, 0x04, 0x00, 0xea, 0x28, 0x00, 0x8f, 0xe2, 0x00, 0x0c, 0x90, 0xe8, 0x00, 0xa0, 0x8a, 0xe0, ++0x01, 0x70, 0x4a, 0xe2, 0x00, 0xb0, 0x8b, 0xe0, 0x0b, 0x00, 0x5a, 0xe1, 0x9e, 0x04, 0x00, 0x0a, 0x0f, 0x00, 0xba, 0xe8, ++0x14, 0xe0, 0x4f, 0xe2, 0x01, 0x00, 0x13, 0xe3, 0x03, 0xf0, 0x47, 0x10, 0x03, 0xf0, 0xa0, 0xe1, 0xd0, 0x1b, 0x00, 0x00, ++0xe0, 0x1b, 0x00, 0x00, 0x00, 0x30, 0xa0, 0xe3, 0x00, 0x40, 0xa0, 0xe3, 0x00, 0x50, 0xa0, 0xe3, 0x00, 0x60, 0xa0, 0xe3, ++0x10, 0x20, 0x52, 0xe2, 0x78, 0x00, 0xa1, 0x28, 0xfc, 0xff, 0xff, 0x8a, 0x82, 0x2e, 0xb0, 0xe1, 0x30, 0x00, 0xa1, 0x28, ++0x00, 0x30, 0x81, 0x45, 0x0e, 0xf0, 0xa0, 0xe1, 0x04, 0x30, 0x9f, 0xe5, 0x03, 0x30, 0x8f, 0xe0, 0x03, 0xf0, 0xa0, 0xe1, ++0x34, 0x1a, 0x00, 0x00, 0x10, 0x40, 0x2d, 0xe9, 0x52, 0x00, 0x00, 0xeb, 0x00, 0x00, 0xa0, 0xe3, 0x10, 0x80, 0xbd, 0xe8, ++0x70, 0x40, 0x2d, 0xe9, 0x00, 0x40, 0xa0, 0xe1, 0x05, 0x06, 0xa0, 0xe3, 0x30, 0x02, 0x90, 0xe5, 0xb4, 0x01, 0x84, 0xe5, ++0xb4, 0x01, 0x94, 0xe5, 0x0f, 0x0b, 0x80, 0xe2, 0x88, 0x01, 0x84, 0xe5, 0x88, 0x01, 0x94, 0xe5, 0x0f, 0x0b, 0x80, 0xe2, ++0x8c, 0x01, 0x84, 0xe5, 0x8c, 0x01, 0x94, 0xe5, 0x0f, 0x0b, 0x80, 0xe2, 0x90, 0x01, 0x84, 0xe5, 0x90, 0x01, 0x94, 0xe5, ++0x0f, 0x0b, 0x80, 0xe2, 0x94, 0x01, 0x84, 0xe5, 0x1a, 0x0b, 0xa0, 0xe3, 0x8c, 0x00, 0x84, 0xe5, 0x25, 0x0b, 0xa0, 0xe3, ++0x90, 0x00, 0x84, 0xe5, 0x1a, 0x0b, 0xa0, 0xe3, 0x94, 0x00, 0x84, 0xe5, 0x98, 0x00, 0x84, 0xe5, 0x0a, 0x0b, 0xa0, 0xe3, ++0x9c, 0x00, 0x84, 0xe5, 0x15, 0x0b, 0xa0, 0xe3, 0xa0, 0x00, 0x84, 0xe5, 0x07, 0x0a, 0xa0, 0xe3, 0xa4, 0x00, 0x84, 0xe5, ++0x00, 0x00, 0xa0, 0xe3, 0xa8, 0x00, 0x84, 0xe5, 0xac, 0x00, 0x84, 0xe5, 0xb0, 0x00, 0x84, 0xe5, 0xb4, 0x00, 0x84, 0xe5, ++0xb8, 0x00, 0x84, 0xe5, 0xbc, 0x00, 0x84, 0xe5, 0xc0, 0x00, 0x84, 0xe5, 0xc4, 0x00, 0x84, 0xe5, 0xc8, 0x00, 0x84, 0xe5, ++0x03, 0x0a, 0xa0, 0xe3, 0xcc, 0x00, 0x84, 0xe5, 0x15, 0x0b, 0xa0, 0xe3, 0xd0, 0x00, 0x84, 0xe5, 0x00, 0x00, 0xa0, 0xe3, ++0xd4, 0x00, 0x84, 0xe5, 0xd8, 0x00, 0x84, 0xe5, 0x0a, 0x0b, 0xa0, 0xe3, 0xdc, 0x00, 0x84, 0xe5, 0x00, 0x50, 0xa0, 0xe3, ++0x03, 0x00, 0x00, 0xea, 0x00, 0x00, 0xe0, 0xe3, 0xe0, 0x10, 0x84, 0xe2, 0x05, 0x01, 0x81, 0xe7, 0x01, 0x50, 0x85, 0xe2, ++0x15, 0x00, 0x55, 0xe3, 0xf9, 0xff, 0xff, 0xba, 0x0a, 0x1a, 0xa0, 0xe3, 0x01, 0x00, 0xa0, 0xe3, 0x87, 0x03, 0x00, 0xeb, ++0x80, 0x00, 0x84, 0xe5, 0x80, 0x00, 0x94, 0xe5, 0x00, 0x00, 0x50, 0xe3, 0x00, 0x00, 0x00, 0x1a, 0x70, 0x80, 0xbd, 0xe8, ++0x0f, 0x1b, 0xa0, 0xe3, 0x01, 0x00, 0xa0, 0xe3, 0x7f, 0x03, 0x00, 0xeb, 0x88, 0x00, 0x84, 0xe5, 0x88, 0x00, 0x94, 0xe5, ++0x00, 0x00, 0x50, 0xe3, 0x00, 0x00, 0x00, 0x1a, 0xf6, 0xff, 0xff, 0xea, 0x80, 0x00, 0x94, 0xe5, 0xff, 0x10, 0x00, 0xe2, ++0x01, 0x1c, 0x61, 0xe2, 0x01, 0x00, 0x80, 0xe0, 0x84, 0x00, 0x84, 0xe5, 0x84, 0x00, 0x94, 0xe5, 0x98, 0x01, 0x84, 0xe5, ++0xee, 0xff, 0xff, 0xea, 0x70, 0x40, 0x2d, 0xe9, 0x00, 0x50, 0xa0, 0xe3, 0x07, 0x1d, 0xa0, 0xe3, 0x01, 0x00, 0xa0, 0xe3, ++0x6d, 0x03, 0x00, 0xeb, 0x00, 0x40, 0xa0, 0xe1, 0x04, 0x00, 0xa0, 0xe1, 0xa6, 0xff, 0xff, 0xeb, 0x01, 0x00, 0xa0, 0xe3, ++0x52, 0x18, 0xa0, 0xe3, 0xd0, 0x00, 0x81, 0xe5, 0x89, 0x00, 0x00, 0xea, 0x04, 0x00, 0x00, 0xea, 0x05, 0x06, 0xa0, 0xe3, ++0x14, 0x01, 0x90, 0xe5, 0x01, 0x00, 0x50, 0xe3, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00, 0xea, 0xf9, 0xff, 0xff, 0xea, ++0x00, 0x00, 0xa0, 0xe1, 0x04, 0x00, 0x00, 0xea, 0x05, 0x06, 0xa0, 0xe3, 0x14, 0x01, 0x90, 0xe5, 0x00, 0x00, 0x50, 0xe3, ++0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00, 0xea, 0xf9, 0xff, 0xff, 0xea, 0x00, 0x00, 0xa0, 0xe1, 0x05, 0x06, 0xa0, 0xe3, ++0x00, 0x0d, 0x90, 0xe5, 0xa0, 0x01, 0x84, 0xe5, 0xa0, 0x01, 0x94, 0xe5, 0x06, 0x00, 0x50, 0xe3, 0x06, 0x00, 0x00, 0x0a, ++0xa0, 0x01, 0x94, 0xe5, 0x07, 0x00, 0x50, 0xe3, 0x03, 0x00, 0x00, 0x0a, 0x05, 0x06, 0xa0, 0xe3, 0x04, 0x01, 0x90, 0xe5, ++0xa4, 0x01, 0x84, 0xe5, 0x01, 0x00, 0x00, 0xea, 0xa8, 0x01, 0x94, 0xe5, 0xa4, 0x01, 0x84, 0xe5, 0xbc, 0x01, 0x94, 0xe5, ++0x00, 0x00, 0x50, 0xe3, 0x12, 0x00, 0x00, 0x1a, 0x69, 0x1f, 0x84, 0xe2, 0x03, 0x00, 0x91, 0xe8, 0x01, 0x00, 0x50, 0xe1, ++0x0e, 0x00, 0x00, 0x0a, 0xa0, 0x01, 0x94, 0xe5, 0x02, 0x00, 0x50, 0xe3, 0x0b, 0x00, 0x00, 0x0a, 0xa8, 0x21, 0x94, 0xe5, ++0x62, 0x3f, 0x84, 0xe2, 0x02, 0x11, 0x93, 0xe7, 0x0f, 0x2b, 0xa0, 0xe3, 0x88, 0x00, 0x94, 0xe5, 0xd4, 0x02, 0x00, 0xeb, ++0x88, 0x10, 0x94, 0xe5, 0xa4, 0x21, 0x94, 0xe5, 0x62, 0x3f, 0x84, 0xe2, 0x02, 0x01, 0x93, 0xe7, 0x0f, 0x2b, 0xa0, 0xe3, ++0x7f, 0x02, 0x00, 0xeb, 0x01, 0x00, 0xa0, 0xe3, 0xa4, 0x11, 0x94, 0xe5, 0x01, 0x11, 0x81, 0xe0, 0x10, 0x20, 0x84, 0xe2, ++0x01, 0x11, 0x82, 0xe0, 0x04, 0x00, 0x81, 0xe5, 0xbc, 0x01, 0x94, 0xe5, 0x01, 0x00, 0x50, 0xe3, 0x05, 0x00, 0x00, 0x1a, ++0x88, 0x10, 0x94, 0xe5, 0xa4, 0x21, 0x94, 0xe5, 0x62, 0x3f, 0x84, 0xe2, 0x02, 0x01, 0x93, 0xe7, 0x0f, 0x2b, 0xa0, 0xe3, ++0x70, 0x02, 0x00, 0xeb, 0xa0, 0x01, 0x94, 0xe5, 0x07, 0x00, 0x50, 0xe3, 0x00, 0xf1, 0x8f, 0x90, 0x24, 0x00, 0x00, 0xea, ++0x06, 0x00, 0x00, 0xea, 0x09, 0x00, 0x00, 0xea, 0x0c, 0x00, 0x00, 0xea, 0x0f, 0x00, 0x00, 0xea, 0x12, 0x00, 0x00, 0xea, ++0x1e, 0x00, 0x00, 0xea, 0x14, 0x00, 0x00, 0xea, 0x18, 0x00, 0x00, 0xea, 0x00, 0x00, 0xa0, 0xe1, 0x04, 0x00, 0xa0, 0xe1, ++0x39, 0x00, 0x00, 0xeb, 0x1a, 0x00, 0x00, 0xea, 0x00, 0x00, 0xa0, 0xe1, 0x04, 0x00, 0xa0, 0xe1, 0xaa, 0x00, 0x00, 0xeb, ++0x16, 0x00, 0x00, 0xea, 0x00, 0x00, 0xa0, 0xe1, 0x04, 0x00, 0xa0, 0xe1, 0xcb, 0x00, 0x00, 0xeb, 0x12, 0x00, 0x00, 0xea, ++0x00, 0x00, 0xa0, 0xe1, 0x04, 0x00, 0xa0, 0xe1, 0xf4, 0x00, 0x00, 0xeb, 0x0e, 0x00, 0x00, 0xea, 0x00, 0x00, 0xa0, 0xe1, ++0x04, 0x00, 0xa0, 0xe1, 0x7b, 0x01, 0x00, 0xeb, 0x0a, 0x00, 0x00, 0xea, 0x00, 0x00, 0xa0, 0xe1, 0x04, 0x00, 0xa0, 0xe1, ++0x16, 0x02, 0x00, 0xeb, 0x01, 0x50, 0xa0, 0xe3, 0x05, 0x00, 0x00, 0xea, 0x00, 0x00, 0xa0, 0xe1, 0x04, 0x00, 0xa0, 0xe1, ++0x30, 0x02, 0x00, 0xeb, 0x01, 0x00, 0x00, 0xea, 0x00, 0x00, 0xa0, 0xe1, 0x00, 0x00, 0xa0, 0xe1, 0x00, 0x00, 0xa0, 0xe1, ++0xa0, 0x01, 0x94, 0xe5, 0x07, 0x00, 0x50, 0xe3, 0x01, 0x00, 0x00, 0x0a, 0x00, 0x00, 0xa0, 0xe3, 0xbc, 0x01, 0x84, 0xe5, ++0xa4, 0x01, 0x94, 0xe5, 0xa8, 0x01, 0x84, 0xe5, 0x00, 0x00, 0xa0, 0xe3, 0x05, 0x16, 0xa0, 0xe3, 0x0c, 0x04, 0x81, 0xe5, ++0xa0, 0x01, 0x94, 0xe5, 0x04, 0x00, 0x50, 0xe3, 0x01, 0x00, 0x00, 0x0a, 0x01, 0x00, 0xa0, 0xe3, 0x0c, 0x05, 0x81, 0xe5, ++0x00, 0x00, 0xe0, 0xe3, 0xa0, 0x01, 0x84, 0xe5, 0x00, 0x00, 0x55, 0xe3, 0x06, 0x00, 0x00, 0x0a, 0x88, 0x00, 0x94, 0xe5, ++0xd8, 0x02, 0x00, 0xeb, 0x98, 0x01, 0x94, 0xe5, 0xd6, 0x02, 0x00, 0xeb, 0x04, 0x00, 0xa0, 0xe1, 0xd4, 0x02, 0x00, 0xeb, ++0x00, 0x00, 0x00, 0xea, 0x74, 0xff, 0xff, 0xea, 0x00, 0x00, 0xa0, 0xe1, 0x70, 0x80, 0xbd, 0xe8, 0xf0, 0x47, 0x2d, 0xe9, ++0x00, 0x40, 0xa0, 0xe1, 0xa4, 0x61, 0x94, 0xe5, 0x00, 0x80, 0xa0, 0xe3, 0x00, 0x70, 0xa0, 0xe3, 0x00, 0x90, 0xa0, 0xe3, ++0x05, 0x06, 0xa0, 0xe3, 0x00, 0x01, 0x90, 0xe5, 0x1f, 0x00, 0x00, 0xe2, 0x06, 0x01, 0x84, 0xe7, 0x01, 0x00, 0xa0, 0xe3, ++0x06, 0x11, 0x86, 0xe0, 0x10, 0x20, 0x84, 0xe2, 0x01, 0x01, 0x82, 0xe7, 0x00, 0x00, 0xa0, 0xe3, 0x06, 0x11, 0x86, 0xe0, ++0x10, 0x20, 0x84, 0xe2, 0x01, 0x11, 0x82, 0xe0, 0x08, 0x00, 0x81, 0xe5, 0x06, 0x51, 0x94, 0xe7, 0xb0, 0x01, 0x94, 0xe5, ++0x00, 0x00, 0x50, 0xe3, 0x02, 0x00, 0x00, 0x0a, 0xac, 0x01, 0x94, 0xe5, 0x05, 0x00, 0x50, 0xe1, 0x50, 0x00, 0x00, 0x0a, ++0xb0, 0x01, 0x94, 0xe5, 0x02, 0x00, 0x50, 0xe3, 0x4d, 0x00, 0x00, 0xaa, 0x05, 0x00, 0x55, 0xe3, 0x2c, 0x00, 0x00, 0x0a, ++0x06, 0x00, 0x00, 0xca, 0x00, 0x00, 0x55, 0xe3, 0x11, 0x00, 0x00, 0x0a, 0x01, 0x00, 0x55, 0xe3, 0x1b, 0x00, 0x00, 0x0a, ++0x04, 0x00, 0x55, 0xe3, 0x31, 0x00, 0x00, 0x1a, 0x2a, 0x00, 0x00, 0xea, 0x06, 0x00, 0x55, 0xe3, 0x1c, 0x00, 0x00, 0x0a, ++0x10, 0x00, 0x55, 0xe3, 0x02, 0x00, 0x00, 0x0a, 0x11, 0x00, 0x55, 0xe3, 0x2a, 0x00, 0x00, 0x1a, 0x0b, 0x00, 0x00, 0xea, ++0x00, 0x00, 0xa0, 0xe1, 0x05, 0x06, 0xa0, 0xe3, 0x00, 0x02, 0x90, 0xe5, 0x4d, 0x1f, 0x84, 0xe2, 0x05, 0x01, 0x81, 0xe7, ++0x25, 0x00, 0x00, 0xea, 0x00, 0x00, 0xa0, 0xe1, 0x05, 0x06, 0xa0, 0xe3, 0x04, 0x02, 0x90, 0xe5, 0x4d, 0x1f, 0x84, 0xe2, ++0x05, 0x01, 0x81, 0xe7, 0x1f, 0x00, 0x00, 0xea, 0x00, 0x00, 0xa0, 0xe1, 0x05, 0x06, 0xa0, 0xe3, 0x08, 0x02, 0x90, 0xe5, ++0x4d, 0x1f, 0x84, 0xe2, 0x05, 0x01, 0x81, 0xe7, 0x19, 0x00, 0x00, 0xea, 0x00, 0x00, 0xa0, 0xe1, 0x05, 0x06, 0xa0, 0xe3, ++0x0c, 0x02, 0x90, 0xe5, 0x4d, 0x1f, 0x84, 0xe2, 0x05, 0x01, 0x81, 0xe7, 0x13, 0x00, 0x00, 0xea, 0x00, 0x00, 0xa0, 0xe1, ++0x05, 0x06, 0xa0, 0xe3, 0x10, 0x02, 0x90, 0xe5, 0x4d, 0x1f, 0x84, 0xe2, 0x05, 0x01, 0x81, 0xe7, 0x0d, 0x00, 0x00, 0xea, ++0x00, 0x00, 0xa0, 0xe1, 0x05, 0x06, 0xa0, 0xe3, 0x14, 0x02, 0x90, 0xe5, 0x4d, 0x1f, 0x84, 0xe2, 0x05, 0x01, 0x81, 0xe7, ++0x07, 0x00, 0x00, 0xea, 0x00, 0x00, 0xa0, 0xe1, 0x05, 0x06, 0xa0, 0xe3, 0x18, 0x02, 0x90, 0xe5, 0x4d, 0x1f, 0x84, 0xe2, ++0x05, 0x01, 0x81, 0xe7, 0x01, 0x00, 0x00, 0xea, 0x00, 0x00, 0xa0, 0xe1, 0x00, 0x00, 0xa0, 0xe1, 0x00, 0x00, 0xa0, 0xe1, ++0x0f, 0x1b, 0xa0, 0xe3, 0x88, 0x00, 0x94, 0xe5, 0xce, 0x02, 0x00, 0xeb, 0x8c, 0x00, 0x84, 0xe2, 0x05, 0x81, 0x90, 0xe7, ++0x4d, 0x0f, 0x84, 0xe2, 0x05, 0x71, 0x90, 0xe7, 0x98, 0x01, 0x94, 0xe5, 0x60, 0x10, 0x84, 0xe2, 0x06, 0x01, 0x81, 0xe7, ++0x60, 0x00, 0x84, 0xe2, 0x06, 0x11, 0x90, 0xe7, 0x08, 0x20, 0xa0, 0xe1, 0x07, 0x00, 0xa0, 0xe1, 0xbd, 0x01, 0x00, 0xeb, ++0x06, 0x00, 0x00, 0xea, 0xa4, 0x01, 0x94, 0xe5, 0x00, 0x01, 0x94, 0xe7, 0x4d, 0x1f, 0x84, 0xe2, 0x00, 0x71, 0x91, 0xe7, ++0x98, 0x01, 0x94, 0xe5, 0x60, 0x10, 0x84, 0xe2, 0x06, 0x01, 0x81, 0xe7, 0xac, 0x51, 0x84, 0xe5, 0x01, 0x00, 0xa0, 0xe3, ++0xf0, 0x87, 0xbd, 0xe8, 0xf0, 0x47, 0x2d, 0xe9, 0x00, 0x40, 0xa0, 0xe1, 0xa4, 0x61, 0x94, 0xe5, 0xa8, 0x71, 0x94, 0xe5, ++0x62, 0x0f, 0x84, 0xe2, 0x06, 0x81, 0x90, 0xe7, 0x62, 0x0f, 0x84, 0xe2, 0x07, 0x91, 0x90, 0xe7, 0x06, 0x00, 0x57, 0xe1, ++0x07, 0x00, 0x00, 0x0a, 0x0f, 0x2b, 0xa0, 0xe3, 0x09, 0x10, 0xa0, 0xe1, 0x88, 0x00, 0x94, 0xe5, 0xf3, 0x01, 0x00, 0xeb, ++0x0f, 0x2b, 0xa0, 0xe3, 0x08, 0x00, 0xa0, 0xe1, 0x88, 0x10, 0x94, 0xe5, 0xa0, 0x01, 0x00, 0xeb, 0x01, 0x00, 0xa0, 0xe3, ++0x06, 0x11, 0x86, 0xe0, 0x10, 0x20, 0x84, 0xe2, 0x01, 0x11, 0x82, 0xe0, 0x04, 0x00, 0x81, 0xe5, 0x00, 0x50, 0xa0, 0xe3, ++0x07, 0x00, 0x00, 0xea, 0x06, 0x00, 0x55, 0xe1, 0x04, 0x00, 0x00, 0x0a, 0x00, 0x00, 0xa0, 0xe3, 0x05, 0x11, 0x85, 0xe0, ++0x10, 0x20, 0x84, 0xe2, 0x01, 0x11, 0x82, 0xe0, 0x04, 0x00, 0x81, 0xe5, 0x01, 0x50, 0x85, 0xe2, 0x04, 0x00, 0x55, 0xe3, ++0xf5, 0xff, 0xff, 0xba, 0x01, 0x00, 0xa0, 0xe3, 0xf0, 0x87, 0xbd, 0xe8, 0xf0, 0x41, 0x2d, 0xe9, 0x00, 0x40, 0xa0, 0xe1, ++0xa4, 0x51, 0x94, 0xe5, 0xa8, 0x61, 0x94, 0xe5, 0x62, 0x0f, 0x84, 0xe2, 0x05, 0x71, 0x90, 0xe7, 0x62, 0x0f, 0x84, 0xe2, ++0x06, 0x81, 0x90, 0xe7, 0x05, 0x00, 0x56, 0xe1, 0x07, 0x00, 0x00, 0x0a, 0x0f, 0x2b, 0xa0, 0xe3, 0x08, 0x10, 0xa0, 0xe1, ++0x88, 0x00, 0x94, 0xe5, 0xce, 0x01, 0x00, 0xeb, 0x0f, 0x2b, 0xa0, 0xe3, 0x07, 0x00, 0xa0, 0xe1, 0x88, 0x10, 0x94, 0xe5, ++0x7b, 0x01, 0x00, 0xeb, 0x00, 0x00, 0xa0, 0xe3, 0x05, 0x11, 0x85, 0xe0, 0x10, 0x20, 0x84, 0xe2, 0x01, 0x01, 0x82, 0xe7, ++0x05, 0x11, 0x85, 0xe0, 0x10, 0x20, 0x84, 0xe2, 0x01, 0x11, 0x82, 0xe0, 0x0c, 0x00, 0x81, 0xe5, 0x05, 0x11, 0x85, 0xe0, ++0x10, 0x20, 0x84, 0xe2, 0x01, 0x11, 0x82, 0xe0, 0x04, 0x00, 0x81, 0xe5, 0x01, 0x00, 0xa0, 0xe3, 0x05, 0x11, 0x85, 0xe0, ++0x10, 0x20, 0x84, 0xe2, 0x01, 0x11, 0x82, 0xe0, 0x08, 0x00, 0x81, 0xe5, 0x00, 0x00, 0xa0, 0xe3, 0x05, 0x11, 0x85, 0xe0, ++0x10, 0x20, 0x84, 0xe2, 0x01, 0x11, 0x82, 0xe0, 0x10, 0x00, 0x81, 0xe5, 0x0f, 0x1b, 0xa0, 0xe3, 0x88, 0x00, 0x94, 0xe5, ++0x67, 0x02, 0x00, 0xeb, 0x01, 0x00, 0xa0, 0xe3, 0xf0, 0x81, 0xbd, 0xe8, 0xf0, 0x41, 0x2d, 0xe9, 0x00, 0x40, 0xa0, 0xe1, ++0x88, 0x80, 0x94, 0xe5, 0x00, 0x60, 0xa0, 0xe3, 0x00, 0x70, 0xa0, 0xe3, 0x69, 0x1f, 0x84, 0xe2, 0x03, 0x00, 0x91, 0xe8, ++0x01, 0x00, 0x50, 0xe1, 0x02, 0x00, 0x00, 0x1a, 0xbc, 0x01, 0x94, 0xe5, 0x00, 0x00, 0x50, 0xe3, 0x0d, 0x00, 0x00, 0x0a, ++0xa4, 0x01, 0x94, 0xe5, 0x00, 0x01, 0x94, 0xe7, 0x8c, 0x10, 0x84, 0xe2, 0x00, 0x61, 0x91, 0xe7, 0xa4, 0x01, 0x94, 0xe5, ++0x00, 0x01, 0x94, 0xe7, 0x4d, 0x1f, 0x84, 0xe2, 0x00, 0x71, 0x91, 0xe7, 0xa4, 0x01, 0x94, 0xe5, 0x60, 0x20, 0x84, 0xe2, ++0x00, 0x11, 0x92, 0xe7, 0x06, 0x20, 0xa0, 0xe1, 0x07, 0x00, 0xa0, 0xe1, 0x46, 0x01, 0x00, 0xeb, 0x01, 0x00, 0xa0, 0xe3, ++0xa4, 0x11, 0x94, 0xe5, 0x01, 0x11, 0x81, 0xe0, 0x10, 0x20, 0x84, 0xe2, 0x01, 0x11, 0x82, 0xe0, 0x0c, 0x00, 0x81, 0xe5, ++0x00, 0x00, 0xa0, 0xe3, 0x05, 0x16, 0xa0, 0xe3, 0x0c, 0x04, 0x81, 0xe5, 0xa4, 0x01, 0x94, 0xe5, 0x00, 0x01, 0x94, 0xe7, ++0x11, 0x00, 0x50, 0xe3, 0x0d, 0x00, 0x00, 0x1a, 0x00, 0x00, 0xa0, 0xe3, 0x52, 0x18, 0xa0, 0xe3, 0x44, 0x00, 0x81, 0xe5, ++0xb4, 0x00, 0x81, 0xe5, 0x02, 0x0c, 0xa0, 0xe3, 0x04, 0x00, 0x81, 0xe5, 0xa4, 0x01, 0x94, 0xe5, 0x60, 0x10, 0x84, 0xe2, ++0x00, 0x01, 0x91, 0xe7, 0x02, 0x5a, 0x80, 0xe2, 0x61, 0x5e, 0x85, 0xe2, 0x08, 0x00, 0xa0, 0xe1, 0x0f, 0xe0, 0xa0, 0xe1, ++0x15, 0xff, 0x2f, 0xe1, 0xa4, 0x01, 0x94, 0xe5, 0x00, 0x01, 0x94, 0xe7, 0x01, 0x00, 0x50, 0xe3, 0x07, 0x00, 0x00, 0x1a, ++0xa4, 0x01, 0x94, 0xe5, 0x60, 0x10, 0x84, 0xe2, 0x00, 0x01, 0x91, 0xe7, 0x02, 0x59, 0x80, 0xe2, 0xa9, 0x5f, 0x85, 0xe2, ++0x08, 0x00, 0xa0, 0xe1, 0x0f, 0xe0, 0xa0, 0xe1, 0x15, 0xff, 0x2f, 0xe1, 0xa4, 0x01, 0x94, 0xe5, 0x00, 0x01, 0x94, 0xe7, ++0x10, 0x00, 0x50, 0xe3, 0x0c, 0x00, 0x00, 0x1a, 0x00, 0x00, 0xa0, 0xe3, 0x52, 0x18, 0xa0, 0xe3, 0x44, 0x00, 0x81, 0xe5, ++0xb4, 0x00, 0x81, 0xe5, 0x02, 0x0c, 0xa0, 0xe3, 0x04, 0x00, 0x81, 0xe5, 0xa4, 0x01, 0x94, 0xe5, 0x60, 0x10, 0x84, 0xe2, ++0x00, 0x01, 0x91, 0xe7, 0x47, 0x5d, 0x80, 0xe2, 0x08, 0x00, 0xa0, 0xe1, 0x0f, 0xe0, 0xa0, 0xe1, 0x15, 0xff, 0x2f, 0xe1, ++0xa4, 0x01, 0x94, 0xe5, 0x00, 0x01, 0x94, 0xe7, 0x00, 0x00, 0x50, 0xe3, 0x03, 0x00, 0x00, 0x0a, 0xa4, 0x01, 0x94, 0xe5, ++0x00, 0x01, 0x94, 0xe7, 0x02, 0x00, 0x50, 0xe3, 0x06, 0x00, 0x00, 0x1a, 0xa4, 0x01, 0x94, 0xe5, 0x60, 0x10, 0x84, 0xe2, ++0x00, 0x01, 0x91, 0xe7, 0x8f, 0x5e, 0x80, 0xe2, 0x08, 0x00, 0xa0, 0xe1, 0x0f, 0xe0, 0xa0, 0xe1, 0x15, 0xff, 0x2f, 0xe1, ++0xa4, 0x01, 0x94, 0xe5, 0x00, 0x01, 0x94, 0xe7, 0x06, 0x00, 0x50, 0xe3, 0x07, 0x00, 0x00, 0x1a, 0xa4, 0x01, 0x94, 0xe5, ++0x60, 0x10, 0x84, 0xe2, 0x00, 0x01, 0x91, 0xe7, 0x01, 0x5b, 0x80, 0xe2, 0xbc, 0x50, 0x85, 0xe2, 0x08, 0x00, 0xa0, 0xe1, ++0x0f, 0xe0, 0xa0, 0xe1, 0x15, 0xff, 0x2f, 0xe1, 0xa4, 0x01, 0x94, 0xe5, 0x00, 0x01, 0x94, 0xe7, 0x04, 0x00, 0x50, 0xe3, ++0x07, 0x00, 0x00, 0x1a, 0xa4, 0x01, 0x94, 0xe5, 0x60, 0x10, 0x84, 0xe2, 0x00, 0x01, 0x91, 0xe7, 0x03, 0x5b, 0x80, 0xe2, ++0x83, 0x5f, 0x85, 0xe2, 0x08, 0x00, 0xa0, 0xe1, 0x0f, 0xe0, 0xa0, 0xe1, 0x15, 0xff, 0x2f, 0xe1, 0xa4, 0x01, 0x94, 0xe5, ++0x00, 0x01, 0x94, 0xe7, 0x05, 0x00, 0x50, 0xe3, 0x06, 0x00, 0x00, 0x1a, 0xa4, 0x01, 0x94, 0xe5, 0x60, 0x10, 0x84, 0xe2, ++0x00, 0x01, 0x91, 0xe7, 0xe3, 0x5f, 0x80, 0xe2, 0x08, 0x00, 0xa0, 0xe1, 0x0f, 0xe0, 0xa0, 0xe1, 0x15, 0xff, 0x2f, 0xe1, ++0x01, 0x00, 0xa0, 0xe3, 0xa4, 0x11, 0x94, 0xe5, 0x01, 0x11, 0x81, 0xe0, 0x10, 0x20, 0x84, 0xe2, 0x01, 0x11, 0x82, 0xe0, ++0x0c, 0x00, 0x81, 0xe5, 0xf0, 0x81, 0xbd, 0xe8, 0xf0, 0x47, 0x2d, 0xe9, 0x00, 0x40, 0xa0, 0xe1, 0x88, 0x80, 0x94, 0xe5, ++0x00, 0x60, 0xa0, 0xe3, 0x00, 0x70, 0xa0, 0xe3, 0x01, 0x00, 0xa0, 0xe3, 0xa4, 0x11, 0x94, 0xe5, 0x01, 0x11, 0x81, 0xe0, ++0x10, 0x20, 0x84, 0xe2, 0x01, 0x11, 0x82, 0xe0, 0x10, 0x00, 0x81, 0xe5, 0x69, 0x1f, 0x84, 0xe2, 0x03, 0x00, 0x91, 0xe8, ++0x01, 0x00, 0x50, 0xe1, 0x02, 0x00, 0x00, 0x1a, 0xbc, 0x01, 0x94, 0xe5, 0x00, 0x00, 0x50, 0xe3, 0x0d, 0x00, 0x00, 0x0a, ++0xa4, 0x01, 0x94, 0xe5, 0x00, 0x01, 0x94, 0xe7, 0x8c, 0x10, 0x84, 0xe2, 0x00, 0x61, 0x91, 0xe7, 0xa4, 0x01, 0x94, 0xe5, ++0x00, 0x01, 0x94, 0xe7, 0x4d, 0x1f, 0x84, 0xe2, 0x00, 0x71, 0x91, 0xe7, 0xa4, 0x01, 0x94, 0xe5, 0x60, 0x20, 0x84, 0xe2, ++0x00, 0x11, 0x92, 0xe7, 0x06, 0x20, 0xa0, 0xe1, 0x07, 0x00, 0xa0, 0xe1, 0xb5, 0x00, 0x00, 0xeb, 0xa4, 0x01, 0x94, 0xe5, ++0x00, 0x01, 0x94, 0xe7, 0x11, 0x00, 0x50, 0xe3, 0x14, 0x00, 0x00, 0x1a, 0x00, 0x00, 0xa0, 0xe3, 0x52, 0x18, 0xa0, 0xe3, ++0x44, 0x00, 0x81, 0xe5, 0xb4, 0x00, 0x81, 0xe5, 0x02, 0x0c, 0xa0, 0xe3, 0x04, 0x00, 0x81, 0xe5, 0x00, 0x00, 0xa0, 0xe3, ++0x56, 0x18, 0xa0, 0xe3, 0x0c, 0x00, 0x81, 0xe5, 0x10, 0x00, 0x81, 0xe5, 0x02, 0x16, 0xa0, 0xe3, 0x04, 0x00, 0x81, 0xe5, ++0xa4, 0x01, 0x94, 0xe5, 0x60, 0x10, 0x84, 0xe2, 0x00, 0x01, 0x91, 0xe7, 0x06, 0x5b, 0x80, 0xe2, 0xb1, 0x5f, 0x85, 0xe2, ++0x08, 0x00, 0xa0, 0xe1, 0x0f, 0xe0, 0xa0, 0xe1, 0x15, 0xff, 0x2f, 0xe1, 0x00, 0x90, 0xa0, 0xe1, 0xa4, 0x01, 0x94, 0xe5, ++0x00, 0x01, 0x94, 0xe7, 0x01, 0x00, 0x50, 0xe3, 0x0b, 0x00, 0x00, 0x1a, 0x02, 0x00, 0xa0, 0xe3, 0x52, 0x18, 0xa0, 0xe3, ++0x08, 0x00, 0x81, 0xe5, 0xa4, 0x01, 0x94, 0xe5, 0x60, 0x10, 0x84, 0xe2, 0x00, 0x01, 0x91, 0xe7, 0x01, 0x59, 0x80, 0xe2, ++0xea, 0x5d, 0x85, 0xe2, 0x08, 0x00, 0xa0, 0xe1, 0x0f, 0xe0, 0xa0, 0xe1, 0x15, 0xff, 0x2f, 0xe1, 0x00, 0x90, 0xa0, 0xe1, ++0xa4, 0x01, 0x94, 0xe5, 0x00, 0x01, 0x94, 0xe7, 0x10, 0x00, 0x50, 0xe3, 0x14, 0x00, 0x00, 0x1a, 0x00, 0x00, 0xa0, 0xe3, ++0x52, 0x18, 0xa0, 0xe3, 0x44, 0x00, 0x81, 0xe5, 0xb4, 0x00, 0x81, 0xe5, 0x02, 0x0c, 0xa0, 0xe3, 0x04, 0x00, 0x81, 0xe5, ++0x00, 0x00, 0xa0, 0xe3, 0x56, 0x18, 0xa0, 0xe3, 0x0c, 0x00, 0x81, 0xe5, 0x10, 0x00, 0x81, 0xe5, 0x02, 0x16, 0xa0, 0xe3, ++0x04, 0x00, 0x81, 0xe5, 0xa4, 0x01, 0x94, 0xe5, 0x60, 0x10, 0x84, 0xe2, 0x00, 0x01, 0x91, 0xe7, 0x01, 0x5b, 0x80, 0xe2, ++0x64, 0x50, 0x85, 0xe2, 0x08, 0x00, 0xa0, 0xe1, 0x0f, 0xe0, 0xa0, 0xe1, 0x15, 0xff, 0x2f, 0xe1, 0x00, 0x90, 0xa0, 0xe1, ++0xa4, 0x01, 0x94, 0xe5, 0x00, 0x01, 0x94, 0xe7, 0x00, 0x00, 0x50, 0xe3, 0x03, 0x00, 0x00, 0x0a, 0xa4, 0x01, 0x94, 0xe5, ++0x00, 0x01, 0x94, 0xe7, 0x02, 0x00, 0x50, 0xe3, 0x08, 0x00, 0x00, 0x1a, 0xa4, 0x01, 0x94, 0xe5, 0x60, 0x10, 0x84, 0xe2, ++0x00, 0x01, 0x91, 0xe7, 0x05, 0x5b, 0x80, 0xe2, 0x55, 0x5f, 0x85, 0xe2, 0x08, 0x00, 0xa0, 0xe1, 0x0f, 0xe0, 0xa0, 0xe1, ++0x15, 0xff, 0x2f, 0xe1, 0x00, 0x90, 0xa0, 0xe1, 0xa4, 0x01, 0x94, 0xe5, 0x00, 0x01, 0x94, 0xe7, 0x06, 0x00, 0x50, 0xe3, ++0x07, 0x00, 0x00, 0x1a, 0xa4, 0x01, 0x94, 0xe5, 0x60, 0x10, 0x84, 0xe2, 0x00, 0x01, 0x91, 0xe7, 0x66, 0x5e, 0x80, 0xe2, ++0x08, 0x00, 0xa0, 0xe1, 0x0f, 0xe0, 0xa0, 0xe1, 0x15, 0xff, 0x2f, 0xe1, 0x00, 0x90, 0xa0, 0xe1, 0xa4, 0x01, 0x94, 0xe5, ++0x00, 0x01, 0x94, 0xe7, 0x04, 0x00, 0x50, 0xe3, 0x07, 0x00, 0x00, 0x1a, 0xa4, 0x01, 0x94, 0xe5, 0x60, 0x10, 0x84, 0xe2, ++0x00, 0x01, 0x91, 0xe7, 0x81, 0x5f, 0x80, 0xe2, 0x08, 0x00, 0xa0, 0xe1, 0x0f, 0xe0, 0xa0, 0xe1, 0x15, 0xff, 0x2f, 0xe1, ++0x00, 0x90, 0xa0, 0xe1, 0xa4, 0x01, 0x94, 0xe5, 0x00, 0x01, 0x94, 0xe7, 0x05, 0x00, 0x50, 0xe3, 0x07, 0x00, 0x00, 0x1a, ++0xa4, 0x01, 0x94, 0xe5, 0x60, 0x10, 0x84, 0xe2, 0x00, 0x01, 0x91, 0xe7, 0x42, 0x5f, 0x80, 0xe2, 0x08, 0x00, 0xa0, 0xe1, ++0x0f, 0xe0, 0xa0, 0xe1, 0x15, 0xff, 0x2f, 0xe1, 0x00, 0x90, 0xa0, 0xe1, 0x01, 0x00, 0xa0, 0xe3, 0xa4, 0x11, 0x94, 0xe5, ++0x01, 0x11, 0x81, 0xe0, 0x10, 0x20, 0x84, 0xe2, 0x01, 0x11, 0x82, 0xe0, 0x10, 0x00, 0x81, 0xe5, 0x09, 0x00, 0xa0, 0xe1, ++0xf0, 0x87, 0xbd, 0xe8, 0xf0, 0x41, 0x2d, 0xe9, 0x00, 0x40, 0xa0, 0xe1, 0xa4, 0x61, 0x94, 0xe5, 0xa4, 0x01, 0x94, 0xe5, ++0x00, 0x71, 0x94, 0xe7, 0x62, 0x0f, 0x84, 0xe2, 0x06, 0x81, 0x90, 0xe7, 0x0f, 0x2b, 0xa0, 0xe3, 0x08, 0x10, 0xa0, 0xe1, ++0x88, 0x00, 0x94, 0xe5, 0x7a, 0x00, 0x00, 0xeb, 0x01, 0x00, 0xa0, 0xe3, 0xb8, 0x01, 0x84, 0xe5, 0x00, 0x00, 0xa0, 0xe3, ++0xa8, 0x01, 0x84, 0xe5, 0xa4, 0x01, 0x84, 0xe5, 0xa0, 0x01, 0x84, 0xe5, 0xac, 0x01, 0x84, 0xe5, 0x07, 0x5d, 0xa0, 0xe3, ++0xc5, 0x1f, 0xa0, 0xe1, 0xa1, 0x1c, 0x85, 0xe0, 0xc1, 0x13, 0xa0, 0xe1, 0x81, 0x13, 0x45, 0xe0, 0x80, 0x10, 0x61, 0xe2, ++0x05, 0x00, 0xa0, 0xe1, 0x05, 0x50, 0x81, 0xe0, 0x05, 0x20, 0xa0, 0xe1, 0xb4, 0x11, 0x94, 0xe5, 0x04, 0x00, 0xa0, 0xe1, ++0x67, 0x00, 0x00, 0xeb, 0xf0, 0x81, 0xbd, 0xe8, 0x70, 0x40, 0x2d, 0xe9, 0x00, 0x40, 0xa0, 0xe1, 0x05, 0x06, 0xa0, 0xe3, ++0x30, 0x02, 0x90, 0xe5, 0x00, 0x60, 0xa0, 0xe1, 0x07, 0x5d, 0xa0, 0xe3, 0xc5, 0x1f, 0xa0, 0xe1, 0xa1, 0x1c, 0x85, 0xe0, ++0xc1, 0x13, 0xa0, 0xe1, 0x81, 0x13, 0x45, 0xe0, 0x80, 0x10, 0x61, 0xe2, 0x05, 0x00, 0xa0, 0xe1, 0x05, 0x50, 0x81, 0xe0, ++0x05, 0x20, 0xa0, 0xe1, 0x04, 0x10, 0xa0, 0xe1, 0x06, 0x00, 0xa0, 0xe1, 0x06, 0x00, 0x00, 0xeb, 0x07, 0x00, 0xa0, 0xe3, ++0xa0, 0x01, 0x84, 0xe5, 0x00, 0x00, 0xa0, 0xe3, 0xb8, 0x01, 0x84, 0xe5, 0x01, 0x00, 0xa0, 0xe3, 0xbc, 0x01, 0x84, 0xe5, ++0x70, 0x80, 0xbd, 0xe8, 0xf7, 0x4f, 0x2d, 0xe9, 0x02, 0x40, 0xa0, 0xe1, 0x06, 0xb6, 0xa0, 0xe3, 0xa4, 0x93, 0xa0, 0xe1, ++0x7f, 0x80, 0x04, 0xe2, 0x00, 0x70, 0xa0, 0xe3, 0x00, 0x60, 0xa0, 0xe3, 0x00, 0x50, 0xa0, 0xe3, 0x24, 0x00, 0x00, 0xea, ++0x00, 0x00, 0x55, 0xe3, 0x0d, 0x00, 0x00, 0x0a, 0x0c, 0x10, 0xa0, 0xe3, 0x05, 0x00, 0xa0, 0xe1, 0x07, 0x01, 0x00, 0xeb, ++0x00, 0x00, 0x51, 0xe3, 0x08, 0x00, 0x00, 0x1a, 0x00, 0x60, 0xa0, 0xe3, 0x06, 0x0c, 0xa0, 0xe3, 0x04, 0x10, 0x9d, 0xe5, ++0x97, 0x10, 0x2a, 0xe0, 0x06, 0x2c, 0xa0, 0xe3, 0x0b, 0x10, 0xa0, 0xe1, 0x0a, 0x00, 0xa0, 0xe1, 0xa9, 0x00, 0x00, 0xeb, ++0x01, 0x70, 0x87, 0xe2, 0x06, 0x16, 0xa0, 0xe3, 0x86, 0x03, 0x81, 0xe0, 0x05, 0x16, 0xa0, 0xe3, 0x20, 0x00, 0x81, 0xe5, ++0x00, 0x10, 0x9d, 0xe5, 0x85, 0x03, 0x81, 0xe0, 0x05, 0x16, 0xa0, 0xe3, 0x14, 0x00, 0x81, 0xe5, 0x20, 0x00, 0xa0, 0xe3, ++0x0c, 0x00, 0x81, 0xe5, 0x04, 0x00, 0xa0, 0xe3, 0x08, 0x00, 0x81, 0xe5, 0x01, 0x00, 0xa0, 0xe3, 0x00, 0x00, 0x81, 0xe5, ++0x00, 0x00, 0xa0, 0xe1, 0x05, 0x06, 0xa0, 0xe3, 0x30, 0x00, 0x90, 0xe5, 0x01, 0x00, 0x50, 0xe3, 0xfb, 0xff, 0xff, 0x1a, ++0x01, 0x60, 0x86, 0xe2, 0x01, 0x50, 0x85, 0xe2, 0x09, 0x00, 0x55, 0xe1, 0xd8, 0xff, 0xff, 0x3a, 0x06, 0x0c, 0xa0, 0xe3, ++0x04, 0x10, 0x9d, 0xe5, 0x97, 0x10, 0x2a, 0xe0, 0x00, 0x00, 0x58, 0xe3, 0x12, 0x00, 0x00, 0x0a, 0x06, 0x16, 0xa0, 0xe3, ++0x86, 0x03, 0x81, 0xe0, 0x05, 0x16, 0xa0, 0xe3, 0x20, 0x00, 0x81, 0xe5, 0x00, 0x10, 0x9d, 0xe5, 0x85, 0x03, 0x81, 0xe0, ++0x05, 0x16, 0xa0, 0xe3, 0x14, 0x00, 0x81, 0xe5, 0x28, 0x01, 0xa0, 0xe1, 0x0c, 0x00, 0x81, 0xe5, 0x04, 0x00, 0xa0, 0xe3, ++0x08, 0x00, 0x81, 0xe5, 0x01, 0x00, 0xa0, 0xe3, 0x00, 0x00, 0x81, 0xe5, 0x00, 0x00, 0xa0, 0xe1, 0x05, 0x06, 0xa0, 0xe3, ++0x30, 0x00, 0x90, 0xe5, 0x01, 0x00, 0x50, 0xe3, 0xfb, 0xff, 0xff, 0x1a, 0x06, 0xb6, 0xa0, 0xe3, 0x86, 0x23, 0x88, 0xe0, ++0x0b, 0x10, 0xa0, 0xe1, 0x0a, 0x00, 0xa0, 0xe1, 0x74, 0x00, 0x00, 0xeb, 0x00, 0x00, 0xa0, 0xe3, 0xfe, 0x8f, 0xbd, 0xe8, ++0xf7, 0x4f, 0x2d, 0xe9, 0x08, 0xd0, 0x4d, 0xe2, 0x06, 0xb6, 0xa0, 0xe3, 0x10, 0x00, 0x9d, 0xe5, 0xa0, 0x03, 0xa0, 0xe1, ++0x04, 0x00, 0x8d, 0xe5, 0x10, 0x00, 0x9d, 0xe5, 0x7f, 0x70, 0x00, 0xe2, 0x00, 0x80, 0xa0, 0xe3, 0x00, 0x60, 0xa0, 0xe3, ++0x04, 0x50, 0x9d, 0xe5, 0x00, 0x40, 0xa0, 0xe3, 0x2b, 0x00, 0x00, 0xea, 0x0c, 0x10, 0xa0, 0xe3, 0x04, 0x00, 0xa0, 0xe1, ++0xb6, 0x00, 0x00, 0xeb, 0x00, 0x00, 0x51, 0xe3, 0x11, 0x00, 0x00, 0x1a, 0x00, 0x60, 0xa0, 0xe3, 0x80, 0x00, 0xa0, 0xe3, ++0x08, 0x10, 0x9d, 0xe5, 0x94, 0x10, 0x29, 0xe0, 0x06, 0x1c, 0xa0, 0xe3, 0x0b, 0x00, 0xa0, 0xe1, 0x86, 0x00, 0x00, 0xeb, ++0x0c, 0x00, 0x55, 0xe3, 0x01, 0x00, 0x00, 0x2a, 0x85, 0xa3, 0xa0, 0xe1, 0x01, 0x00, 0x00, 0xea, 0x06, 0xac, 0xa0, 0xe3, ++0x0c, 0x50, 0x45, 0xe2, 0x0a, 0x20, 0xa0, 0xe1, 0x09, 0x10, 0xa0, 0xe1, 0x0b, 0x00, 0xa0, 0xe1, 0x4f, 0x00, 0x00, 0xeb, ++0x01, 0x80, 0x88, 0xe2, 0x06, 0x16, 0xa0, 0xe3, 0x86, 0x03, 0x81, 0xe0, 0x05, 0x16, 0xa0, 0xe3, 0x20, 0x00, 0x81, 0xe5, ++0x0c, 0x10, 0x9d, 0xe5, 0x84, 0x03, 0x81, 0xe0, 0x05, 0x16, 0xa0, 0xe3, 0x14, 0x00, 0x81, 0xe5, 0x20, 0x00, 0xa0, 0xe3, ++0x0c, 0x00, 0x81, 0xe5, 0x05, 0x00, 0xa0, 0xe3, 0x08, 0x00, 0x81, 0xe5, 0x01, 0x00, 0xa0, 0xe3, 0x00, 0x00, 0x81, 0xe5, ++0x00, 0x00, 0xa0, 0xe1, 0x05, 0x06, 0xa0, 0xe3, 0x30, 0x00, 0x90, 0xe5, 0x01, 0x00, 0x50, 0xe3, 0xfb, 0xff, 0xff, 0x1a, ++0x01, 0x60, 0x86, 0xe2, 0x01, 0x40, 0x84, 0xe2, 0x04, 0x00, 0x9d, 0xe5, 0x00, 0x00, 0x54, 0xe1, 0xd0, 0xff, 0xff, 0x3a, ++0x80, 0x00, 0xa0, 0xe3, 0x08, 0x10, 0x9d, 0xe5, 0x94, 0x10, 0x29, 0xe0, 0x00, 0x00, 0x57, 0xe3, 0x15, 0x00, 0x00, 0x0a, ++0x07, 0x20, 0xa0, 0xe1, 0x09, 0x10, 0xa0, 0xe1, 0x0b, 0x00, 0xa0, 0xe1, 0x2d, 0x00, 0x00, 0xeb, 0x06, 0x06, 0xa0, 0xe3, ++0x05, 0x16, 0xa0, 0xe3, 0x20, 0x00, 0x81, 0xe5, 0x0c, 0x10, 0x9d, 0xe5, 0x84, 0x03, 0x81, 0xe0, 0x05, 0x16, 0xa0, 0xe3, ++0x14, 0x00, 0x81, 0xe5, 0x27, 0x01, 0xa0, 0xe1, 0x0c, 0x00, 0x81, 0xe5, 0x05, 0x00, 0xa0, 0xe3, 0x08, 0x00, 0x81, 0xe5, ++0x01, 0x00, 0xa0, 0xe3, 0x00, 0x00, 0x81, 0xe5, 0x00, 0x00, 0xa0, 0xe1, 0x05, 0x06, 0xa0, 0xe3, 0x30, 0x00, 0x90, 0xe5, ++0x01, 0x00, 0x50, 0xe3, 0xfb, 0xff, 0xff, 0x1a, 0x00, 0x00, 0xa0, 0xe3, 0x14, 0xd0, 0x8d, 0xe2, 0xf0, 0x8f, 0xbd, 0xe8, ++0x00, 0x00, 0x50, 0xe3, 0x0e, 0xf0, 0xa0, 0x01, 0x10, 0x40, 0x2d, 0xe9, 0x00, 0x40, 0xa0, 0xe1, 0xc0, 0x00, 0x00, 0xeb, ++0x04, 0x10, 0xa0, 0xe1, 0x08, 0x00, 0x90, 0xe5, 0x1a, 0x01, 0x00, 0xeb, 0x10, 0x80, 0xbd, 0xe8, 0x70, 0x40, 0x2d, 0xe9, ++0x90, 0x41, 0x81, 0xe0, 0x01, 0x22, 0xa0, 0xe3, 0x04, 0x00, 0xa0, 0xe1, 0x00, 0x00, 0x51, 0xe3, 0x02, 0x00, 0x50, 0x01, ++0x00, 0x00, 0xa0, 0x23, 0x70, 0x80, 0xbd, 0x28, 0x04, 0x00, 0xa0, 0xe1, 0x06, 0x01, 0x00, 0xeb, 0x00, 0x50, 0xb0, 0xe1, ++0x04, 0x10, 0xa0, 0x11, 0x05, 0x00, 0xa0, 0x11, 0x44, 0x00, 0x00, 0x1b, 0x05, 0x00, 0xa0, 0xe1, 0x70, 0x80, 0xbd, 0xe8, ++0x03, 0x00, 0x52, 0xe3, 0x35, 0x01, 0x00, 0x9a, 0x03, 0xc0, 0x10, 0xe2, 0x08, 0x00, 0x00, 0x0a, 0x01, 0x30, 0xd1, 0xe4, ++0x02, 0x00, 0x5c, 0xe3, 0x0c, 0x20, 0x82, 0xe0, 0x01, 0xc0, 0xd1, 0x94, 0x01, 0x30, 0xc0, 0xe4, 0x01, 0x30, 0xd1, 0x34, ++0x01, 0xc0, 0xc0, 0x94, 0x04, 0x20, 0x42, 0xe2, 0x01, 0x30, 0xc0, 0x34, 0x03, 0x30, 0x11, 0xe2, 0x15, 0x01, 0x00, 0x0a, ++0x04, 0x20, 0x52, 0xe2, 0x26, 0x01, 0x00, 0x3a, 0x03, 0xc0, 0x31, 0xe7, 0x02, 0x00, 0x53, 0xe3, 0x08, 0x00, 0x00, 0x0a, ++0x0f, 0x00, 0x00, 0x8a, 0x2c, 0x34, 0xa0, 0xe1, 0x04, 0xc0, 0xb1, 0xe5, 0x04, 0x20, 0x52, 0xe2, 0x0c, 0x3c, 0x83, 0xe1, ++0x04, 0x30, 0x80, 0xe4, 0xf9, 0xff, 0xff, 0x2a, 0x01, 0x10, 0x81, 0xe2, 0x1a, 0x01, 0x00, 0xea, 0x2c, 0x38, 0xa0, 0xe1, ++0x04, 0xc0, 0xb1, 0xe5, 0x04, 0x20, 0x52, 0xe2, 0x0c, 0x38, 0x83, 0xe1, 0x04, 0x30, 0x80, 0xe4, 0xf9, 0xff, 0xff, 0x2a, ++0x02, 0x10, 0x81, 0xe2, 0x12, 0x01, 0x00, 0xea, 0x2c, 0x3c, 0xa0, 0xe1, 0x04, 0xc0, 0xb1, 0xe5, 0x04, 0x20, 0x52, 0xe2, ++0x0c, 0x34, 0x83, 0xe1, 0x04, 0x30, 0x80, 0xe4, 0xf9, 0xff, 0xff, 0x2a, 0x03, 0x10, 0x81, 0xe2, 0x0a, 0x01, 0x00, 0xea, ++0x00, 0x20, 0xa0, 0xe3, 0x20, 0x10, 0x51, 0xe2, 0x00, 0x40, 0x2d, 0xe9, 0x02, 0xe0, 0xa0, 0xe1, 0x02, 0x30, 0xa0, 0xe1, ++0x02, 0xc0, 0xa0, 0xe1, 0x0c, 0x50, 0xa0, 0x28, 0x0c, 0x50, 0xa0, 0x28, 0x20, 0x10, 0x51, 0x22, 0xfb, 0xff, 0xff, 0x2a, ++0x01, 0x1e, 0xb0, 0xe1, 0x0c, 0x50, 0xa0, 0x28, 0x0c, 0x00, 0xa0, 0x48, 0x01, 0x11, 0xb0, 0xe1, 0x00, 0x40, 0xbd, 0xe8, ++0x04, 0x20, 0x80, 0x24, 0x0e, 0xf0, 0xa0, 0x01, 0x01, 0x20, 0xc0, 0x44, 0x01, 0x20, 0xc0, 0x44, 0x01, 0x01, 0x11, 0xe3, ++0x01, 0x20, 0xc0, 0x14, 0x0e, 0xf0, 0xa0, 0xe1, 0x00, 0x20, 0xa0, 0xe3, 0x04, 0x00, 0x51, 0xe3, 0x08, 0x00, 0x00, 0x3a, ++0x03, 0xc0, 0x10, 0xe2, 0xe5, 0xff, 0xff, 0x0a, 0x04, 0xc0, 0x6c, 0xe2, 0x01, 0x20, 0xc0, 0xe4, 0x02, 0x00, 0x5c, 0xe3, ++0x01, 0x20, 0xc0, 0xa4, 0x0c, 0x10, 0x41, 0xe0, 0x01, 0x20, 0xc0, 0xc4, 0xde, 0xff, 0xff, 0xea, 0x81, 0xcf, 0xb0, 0xe1, ++0x01, 0x20, 0xc0, 0x24, 0x01, 0x20, 0xc0, 0x24, 0x01, 0x20, 0xc0, 0x44, 0x0e, 0xf0, 0xa0, 0xe1, 0x01, 0xc0, 0x90, 0xe1, ++0x21, 0x00, 0x00, 0x4a, 0xa0, 0xc0, 0x71, 0xe0, 0x00, 0x20, 0xa0, 0xe3, 0x1a, 0x00, 0x00, 0x3a, 0x20, 0xc2, 0x71, 0xe0, ++0x0f, 0x00, 0x00, 0x3a, 0x20, 0xc4, 0x71, 0xe0, 0x01, 0x00, 0x00, 0x3a, 0x00, 0x30, 0xa0, 0xe3, 0x20, 0x00, 0x00, 0xea, ++0xa0, 0xc3, 0x71, 0xe0, 0x81, 0x03, 0x40, 0x20, 0x02, 0x20, 0xa2, 0xe0, 0x20, 0xc3, 0x71, 0xe0, 0x01, 0x03, 0x40, 0x20, ++0x02, 0x20, 0xa2, 0xe0, 0xa0, 0xc2, 0x71, 0xe0, 0x81, 0x02, 0x40, 0x20, 0x02, 0x20, 0xa2, 0xe0, 0x20, 0xc2, 0x71, 0xe0, ++0x01, 0x02, 0x40, 0x20, 0x02, 0x20, 0xa2, 0xe0, 0xa0, 0xc1, 0x71, 0xe0, 0x81, 0x01, 0x40, 0x20, 0x02, 0x20, 0xa2, 0xe0, ++0x20, 0xc1, 0x71, 0xe0, 0x01, 0x01, 0x40, 0x20, 0x02, 0x20, 0xb2, 0xe0, 0xa0, 0xc0, 0x71, 0xe0, 0x81, 0x00, 0x40, 0x20, ++0x02, 0x20, 0xa2, 0xe0, 0x01, 0x10, 0x50, 0xe0, 0x00, 0x10, 0xa0, 0x31, 0x02, 0x00, 0xa2, 0xe0, 0x0e, 0xf0, 0xa0, 0xe1, ++0x02, 0x21, 0x11, 0xe2, 0x00, 0x10, 0x61, 0x42, 0x40, 0x30, 0x32, 0xe0, 0x00, 0x00, 0x60, 0x22, 0x20, 0xc2, 0x71, 0xe0, ++0x1d, 0x00, 0x00, 0x3a, 0x20, 0xc4, 0x71, 0xe0, 0x0f, 0x00, 0x00, 0x3a, 0x01, 0x13, 0xa0, 0xe1, 0x20, 0xc4, 0x71, 0xe0, ++0x3f, 0x23, 0x82, 0xe3, 0x0b, 0x00, 0x00, 0x3a, 0x01, 0x13, 0xa0, 0xe1, 0x20, 0xc4, 0x71, 0xe0, 0x3f, 0x26, 0x82, 0xe3, ++0x07, 0x00, 0x00, 0x3a, 0x01, 0x13, 0xa0, 0xe1, 0x20, 0xc4, 0x71, 0xe0, 0x3f, 0x29, 0x82, 0xe3, 0x3f, 0x2c, 0x82, 0x23, ++0x01, 0x13, 0xa0, 0x21, 0x00, 0xc0, 0x71, 0xe2, 0x33, 0x00, 0x00, 0x2a, 0x21, 0x13, 0xa0, 0x21, 0xa0, 0xc3, 0x71, 0xe0, ++0x81, 0x03, 0x40, 0x20, 0x02, 0x20, 0xa2, 0xe0, 0x20, 0xc3, 0x71, 0xe0, 0x01, 0x03, 0x40, 0x20, 0x02, 0x20, 0xa2, 0xe0, ++0xa0, 0xc2, 0x71, 0xe0, 0x81, 0x02, 0x40, 0x20, 0x02, 0x20, 0xa2, 0xe0, 0x20, 0xc2, 0x71, 0xe0, 0x01, 0x02, 0x40, 0x20, ++0x02, 0x20, 0xa2, 0xe0, 0xa0, 0xc1, 0x71, 0xe0, 0x81, 0x01, 0x40, 0x20, 0x02, 0x20, 0xa2, 0xe0, 0x20, 0xc1, 0x71, 0xe0, ++0x01, 0x01, 0x40, 0x20, 0x02, 0x20, 0xb2, 0xe0, 0xeb, 0xff, 0xff, 0x2a, 0xa0, 0xc0, 0x71, 0xe0, 0x81, 0x00, 0x40, 0x20, ++0x02, 0x20, 0xa2, 0xe0, 0x01, 0x10, 0x50, 0xe0, 0x00, 0x10, 0xa0, 0x31, 0x02, 0x00, 0xa2, 0xe0, 0xc3, 0x3f, 0xb0, 0xe1, ++0x00, 0x00, 0x60, 0x42, 0x00, 0x10, 0x61, 0x22, 0x0e, 0xf0, 0xa0, 0xe1, 0x04, 0x00, 0x9f, 0xe5, 0x00, 0x00, 0x8f, 0xe0, ++0x0e, 0xf0, 0xa0, 0xe1, 0x7c, 0x09, 0x00, 0x00, 0x78, 0x01, 0x00, 0xeb, 0xf6, 0x00, 0x00, 0xeb, 0x03, 0x00, 0x2d, 0xe9, ++0x76, 0x01, 0x00, 0xeb, 0x03, 0x00, 0xbd, 0xe8, 0x31, 0x01, 0x00, 0xeb, 0x0f, 0x00, 0x2d, 0xe9, 0x75, 0x01, 0x00, 0xeb, ++0x0f, 0x00, 0xbd, 0xe8, 0x6c, 0xfb, 0xff, 0xeb, 0xdc, 0x00, 0x00, 0xea, 0x01, 0x40, 0x2d, 0xe9, 0x73, 0x01, 0x00, 0xeb, ++0x65, 0x01, 0x00, 0xeb, 0x01, 0x40, 0xbd, 0xe8, 0x00, 0x00, 0x00, 0xea, 0x00, 0x00, 0xe0, 0xe3, 0x7c, 0x00, 0x00, 0xea, ++0x81, 0x00, 0x00, 0xea, 0x0e, 0xf0, 0xa0, 0xe1, 0x0e, 0xf0, 0xa0, 0xe1, 0x10, 0x40, 0x2d, 0xe9, 0x00, 0x40, 0xa0, 0xe1, ++0x01, 0x00, 0xa0, 0xe1, 0x08, 0xd0, 0x4d, 0xe2, 0x04, 0x10, 0x8d, 0xe2, 0xda, 0x00, 0x00, 0xeb, 0x00, 0x00, 0x50, 0xe3, ++0x08, 0xd0, 0x8d, 0x02, 0x10, 0x80, 0xbd, 0x08, 0x00, 0x20, 0xa0, 0xe1, 0x04, 0x10, 0x9d, 0xe5, 0x04, 0x00, 0xa0, 0xe1, ++0xaf, 0x00, 0x00, 0xeb, 0x08, 0xd0, 0x8d, 0xe2, 0x01, 0x00, 0xa0, 0xe3, 0x10, 0x80, 0xbd, 0xe8, 0x01, 0x10, 0xa0, 0xe3, ++0x10, 0x40, 0x2d, 0xe9, 0x09, 0x00, 0xa0, 0xe3, 0x6e, 0x00, 0x00, 0xeb, 0x10, 0x80, 0xbd, 0xe8, 0xf0, 0x40, 0x2d, 0xe9, ++0x00, 0x50, 0xa0, 0xe1, 0x00, 0x00, 0xa0, 0xe3, 0x01, 0x40, 0xa0, 0xe1, 0x04, 0x30, 0x2d, 0xe5, 0x72, 0x00, 0x00, 0xeb, ++0x00, 0x60, 0xa0, 0xe1, 0x00, 0x00, 0x85, 0xe0, 0x04, 0x00, 0x50, 0xe1, 0x0a, 0x00, 0x00, 0x9a, 0x0d, 0x10, 0xa0, 0xe1, ++0x06, 0x00, 0xa0, 0xe1, 0xbe, 0x00, 0x00, 0xeb, 0x00, 0x70, 0xb0, 0xe1, 0x00, 0x10, 0xa0, 0x03, 0x09, 0x00, 0xa0, 0x03, ++0x5c, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x9d, 0xe5, 0x04, 0x00, 0x50, 0xe1, 0x00, 0x50, 0xa0, 0x11, 0x07, 0x40, 0x80, 0xe0, ++0xbb, 0xff, 0xff, 0xeb, 0x07, 0x10, 0x86, 0xe2, 0x07, 0x10, 0xc1, 0xe3, 0x00, 0x70, 0xa0, 0xe1, 0x08, 0x50, 0x80, 0xe5, ++0x05, 0x00, 0xa0, 0xe1, 0x05, 0x60, 0x81, 0xe0, 0x56, 0x00, 0x00, 0xeb, 0x06, 0x00, 0x54, 0xe1, 0xf8, 0x00, 0xbd, 0x08, ++0x04, 0xf0, 0x9d, 0x04, 0x06, 0x10, 0xa0, 0xe1, 0x06, 0x20, 0x44, 0xe0, 0x08, 0x00, 0x97, 0xe5, 0x83, 0x00, 0x00, 0xeb, ++0xf8, 0x00, 0xbd, 0xe8, 0x04, 0xf0, 0x9d, 0xe4, 0x10, 0x40, 0x2d, 0xe9, 0x00, 0x40, 0xa0, 0xe1, 0xa8, 0xff, 0xff, 0xeb, ++0x04, 0x10, 0xa0, 0xe1, 0x08, 0x00, 0x90, 0xe5, 0x4e, 0x00, 0x00, 0xeb, 0x10, 0x80, 0xbd, 0xe8, 0x0e, 0xf0, 0xa0, 0xe1, ++0x0e, 0xf0, 0xa0, 0xe1, 0x04, 0x10, 0x41, 0xe2, 0x00, 0x20, 0xa0, 0xe1, 0x04, 0x00, 0x90, 0xe5, 0x00, 0x00, 0x50, 0xe3, ++0x01, 0x00, 0x50, 0x11, 0xfa, 0xff, 0xff, 0x3a, 0x00, 0x30, 0x92, 0xe5, 0x02, 0xc0, 0x83, 0xe0, 0x01, 0x00, 0x5c, 0xe1, ++0x04, 0x10, 0x82, 0x15, 0x03, 0x00, 0x00, 0x1a, 0x00, 0x10, 0x91, 0xe5, 0x01, 0x10, 0x83, 0xe0, 0x00, 0x10, 0x82, 0xe5, ++0x02, 0x10, 0xa0, 0xe1, 0x00, 0x20, 0x91, 0xe5, 0x01, 0x30, 0x82, 0xe0, 0x00, 0x00, 0x53, 0xe1, 0x04, 0x00, 0x81, 0x15, ++0x0e, 0xf0, 0xa0, 0x11, 0x04, 0x30, 0x90, 0xe5, 0x04, 0x30, 0x81, 0xe5, 0x00, 0x00, 0x90, 0xe5, 0x00, 0x00, 0x82, 0xe0, ++0x00, 0x00, 0x81, 0xe5, 0x0e, 0xf0, 0xa0, 0xe1, 0x79, 0x00, 0x00, 0xeb, 0x20, 0x20, 0x52, 0xe2, 0x10, 0x40, 0x2d, 0xe9, ++0x05, 0x00, 0x00, 0x3a, 0x18, 0x50, 0xb1, 0x28, 0x18, 0x50, 0xa0, 0x28, 0x18, 0x50, 0xb1, 0x28, 0x18, 0x50, 0xa0, 0x28, ++0x20, 0x20, 0x52, 0x22, 0xf9, 0xff, 0xff, 0x2a, 0x02, 0xce, 0xb0, 0xe1, 0x18, 0x50, 0xb1, 0x28, 0x18, 0x50, 0xa0, 0x28, ++0x18, 0x00, 0xb1, 0x48, 0x18, 0x00, 0xa0, 0x48, 0x02, 0xcf, 0xb0, 0xe1, 0x10, 0x40, 0xbd, 0xe8, 0x04, 0x30, 0x91, 0x24, ++0x04, 0x30, 0x80, 0x24, 0x0e, 0xf0, 0xa0, 0x01, 0x82, 0x2f, 0xb0, 0xe1, 0x01, 0x20, 0xd1, 0x44, 0x01, 0x30, 0xd1, 0x24, ++0x01, 0xc0, 0xd1, 0x24, 0x01, 0x20, 0xc0, 0x44, 0x01, 0x30, 0xc0, 0x24, 0x01, 0xc0, 0xc0, 0x24, 0x0e, 0xf0, 0xa0, 0xe1, ++0x0c, 0x10, 0x9f, 0xe5, 0x18, 0x00, 0xa0, 0xe3, 0x56, 0x34, 0x12, 0xef, 0x0e, 0xf0, 0xa0, 0xe1, 0xbc, 0x03, 0x00, 0x00, ++0x26, 0x00, 0x02, 0x00, 0x02, 0x00, 0xa0, 0xe3, 0x02, 0x10, 0xa0, 0xe3, 0x00, 0x00, 0xa0, 0xe1, 0x10, 0x40, 0x2d, 0xe9, ++0xe8, 0x00, 0x00, 0xeb, 0x00, 0x00, 0x50, 0xe3, 0x10, 0x80, 0xbd, 0x08, 0x10, 0x40, 0xbd, 0xe8, 0xf0, 0xff, 0xff, 0xea, ++0x00, 0x10, 0xa0, 0xe3, 0x00, 0x10, 0x80, 0xe5, 0x04, 0x10, 0x80, 0xe5, 0x08, 0x00, 0x80, 0xe5, 0x0e, 0xf0, 0xa0, 0xe1, ++0x10, 0x00, 0xa0, 0xe3, 0x0e, 0xf0, 0xa0, 0xe1, 0x70, 0x40, 0x2d, 0xe9, 0x00, 0x50, 0xa0, 0xe1, 0x04, 0x00, 0x81, 0xe2, ++0x08, 0x00, 0x50, 0xe3, 0x08, 0x00, 0xa0, 0x33, 0x07, 0x00, 0x80, 0xe2, 0x07, 0x40, 0xc0, 0xe3, 0x01, 0x00, 0x41, 0xe2, ++0x00, 0x00, 0x54, 0xe1, 0x1f, 0x00, 0x00, 0x9a, 0x04, 0x00, 0x95, 0xe5, 0x05, 0x10, 0xa0, 0xe1, 0x00, 0x00, 0x50, 0xe3, ++0x16, 0x00, 0x00, 0x0a, 0x00, 0x20, 0x90, 0xe5, 0x04, 0x00, 0x52, 0xe1, 0x0f, 0x00, 0x00, 0x3a, 0x00, 0x20, 0x90, 0xe5, ++0x08, 0x30, 0x84, 0xe2, 0x03, 0x00, 0x52, 0xe1, 0x04, 0x20, 0x90, 0x35, 0x04, 0x20, 0x81, 0x35, 0x07, 0x00, 0x00, 0x3a, ++0x04, 0x30, 0x90, 0xe5, 0x04, 0x20, 0x80, 0xe0, 0x04, 0x30, 0x82, 0xe5, 0x00, 0x30, 0x90, 0xe5, 0x04, 0x30, 0x43, 0xe0, ++0x00, 0x30, 0x82, 0xe5, 0x04, 0x20, 0x81, 0xe5, 0x00, 0x40, 0x80, 0xe5, 0x04, 0x00, 0x80, 0xe2, 0x70, 0x80, 0xbd, 0xe8, ++0x00, 0x10, 0xa0, 0xe1, 0x04, 0x00, 0x90, 0xe5, 0x00, 0x00, 0x50, 0xe3, 0xe8, 0xff, 0xff, 0x1a, 0x04, 0x10, 0xa0, 0xe1, ++0x05, 0x00, 0xa0, 0xe1, 0x47, 0xff, 0xff, 0xeb, 0x00, 0x00, 0x50, 0xe3, 0xdf, 0xff, 0xff, 0x1a, 0x00, 0x00, 0xa0, 0xe3, ++0x70, 0x80, 0xbd, 0xe8, 0x1b, 0x00, 0x00, 0xeb, 0x00, 0xc0, 0xa0, 0xe1, 0x10, 0x40, 0x2d, 0xe9, 0x04, 0x30, 0x90, 0xe5, ++0x01, 0x00, 0x00, 0xea, 0x03, 0xc0, 0xa0, 0xe1, 0x04, 0x30, 0x93, 0xe5, 0x00, 0x00, 0x53, 0xe3, 0x01, 0x00, 0x53, 0x11, ++0xfa, 0xff, 0xff, 0x3a, 0x00, 0x30, 0x9c, 0xe5, 0x0c, 0x30, 0x83, 0xe0, 0x01, 0x00, 0x53, 0xe1, 0x05, 0x00, 0x00, 0x0a, ++0x01, 0x30, 0xa0, 0xe1, 0x03, 0x10, 0x81, 0xe2, 0x07, 0x10, 0xc1, 0xe3, 0x04, 0x10, 0x81, 0xe2, 0x03, 0x30, 0x41, 0xe0, ++0x03, 0x20, 0x42, 0xe0, 0x04, 0x20, 0x81, 0xe4, 0x71, 0xff, 0xff, 0xeb, 0x10, 0x80, 0xbd, 0xe8, 0x10, 0x40, 0x2d, 0xe9, ++0x00, 0x40, 0xa0, 0xe1, 0x00, 0x00, 0xa0, 0xe1, 0x04, 0x00, 0xa0, 0xe1, 0x1d, 0xff, 0xff, 0xeb, 0x10, 0x80, 0xbd, 0xe8, ++0x00, 0x10, 0xa0, 0xe3, 0x10, 0x40, 0x2d, 0xe9, 0x01, 0x00, 0xa0, 0xe3, 0xa5, 0xff, 0xff, 0xeb, 0x80, 0x00, 0x00, 0xeb, ++0x01, 0x00, 0xa0, 0xe3, 0x99, 0xff, 0xff, 0xeb, 0x10, 0x80, 0xbd, 0xe8, 0x10, 0x40, 0x2d, 0xe9, 0x24, 0x00, 0x00, 0xeb, ++0x10, 0x80, 0xbd, 0xe8, 0x0e, 0x50, 0xa0, 0xe1, 0x00, 0xff, 0xff, 0xeb, 0x00, 0x40, 0xa0, 0xe1, 0x07, 0x00, 0xc0, 0xe3, ++0x0d, 0x10, 0xa0, 0xe1, 0x60, 0xd0, 0x80, 0xe2, 0x05, 0xe0, 0xa0, 0xe1, 0x10, 0x40, 0x2d, 0xe9, 0x0a, 0x30, 0xa0, 0xe1, ++0xf1, 0x00, 0x00, 0xeb, 0x00, 0x60, 0xa0, 0xe3, 0x00, 0x70, 0xa0, 0xe3, 0x00, 0x80, 0xa0, 0xe3, 0x00, 0xb0, 0xa0, 0xe3, ++0x10, 0x40, 0xbd, 0xe8, 0x07, 0xd0, 0xc1, 0xe3, 0x04, 0xc0, 0xa0, 0xe1, 0xc0, 0x09, 0xac, 0xe8, 0xc0, 0x09, 0xac, 0xe8, ++0xc0, 0x09, 0xac, 0xe8, 0xc0, 0x09, 0xac, 0xe8, 0x13, 0x40, 0x2d, 0xe9, 0x00, 0x10, 0xa0, 0xe3, 0x00, 0x00, 0xa0, 0xe3, ++0x00, 0x00, 0xa0, 0xe1, 0x40, 0x10, 0x81, 0xe2, 0x01, 0x20, 0x80, 0xe0, 0x11, 0x2e, 0x82, 0xe2, 0x1c, 0x20, 0x84, 0xe5, ++0x01, 0x00, 0xa0, 0xe3, 0x18, 0x10, 0x84, 0xe5, 0x10, 0x00, 0x84, 0xe5, 0x13, 0x40, 0xbd, 0xe8, 0x00, 0x10, 0xa0, 0xe1, ++0x14, 0x00, 0x84, 0xe5, 0x0e, 0xf0, 0xa0, 0xe1, 0x10, 0x40, 0x2d, 0xe9, 0x03, 0x00, 0x2d, 0xe9, 0xdb, 0xfe, 0xff, 0xeb, ++0x00, 0x40, 0xa0, 0xe1, 0x03, 0x00, 0xbd, 0xe8, 0x14, 0x20, 0x94, 0xe5, 0x1c, 0x30, 0x94, 0xe5, 0x00, 0xe0, 0x82, 0xe0, ++0x03, 0x30, 0x4d, 0xe0, 0x03, 0x00, 0x5e, 0xe1, 0x00, 0x20, 0x81, 0xe5, 0x0a, 0x00, 0x00, 0x8a, 0x0e, 0x30, 0x93, 0xe0, ++0x01, 0x1a, 0x8e, 0xe2, 0x07, 0x10, 0x81, 0xe2, 0x63, 0x30, 0xa0, 0xe1, 0x07, 0x30, 0xc3, 0xe3, 0x07, 0x10, 0xc1, 0xe3, ++0x03, 0x00, 0x51, 0xe1, 0x03, 0x10, 0xa0, 0x81, 0x02, 0x00, 0x41, 0xe0, 0x14, 0x10, 0x84, 0xe5, 0x10, 0x80, 0xbd, 0xe8, ++0x00, 0x20, 0xa0, 0xe1, 0x00, 0x00, 0xa0, 0xe3, 0x00, 0x00, 0xa0, 0xe1, 0x10, 0x80, 0xbd, 0xe8, 0xc0, 0x43, 0x2d, 0xe9, ++0x3e, 0x00, 0x2d, 0xe9, 0x01, 0x50, 0xa0, 0xe1, 0x00, 0x40, 0xa0, 0xe1, 0xc6, 0x00, 0x00, 0xeb, 0x00, 0x00, 0xa0, 0xe3, ++0x00, 0x40, 0x8d, 0xe5, 0x04, 0x50, 0x8d, 0xe5, 0x61, 0xff, 0xff, 0xeb, 0x08, 0x00, 0x8d, 0xe5, 0x0d, 0x00, 0xa0, 0xe1, ++0x2e, 0xfa, 0xff, 0xeb, 0x00, 0x40, 0xa0, 0xe1, 0x01, 0x50, 0xa0, 0xe1, 0x03, 0x00, 0x9d, 0xe8, 0x02, 0x60, 0xa0, 0xe1, ++0x03, 0x70, 0xa0, 0xe1, 0xdf, 0xfe, 0xff, 0xeb, 0xc8, 0xfe, 0xff, 0xeb, 0x00, 0x00, 0xa0, 0xe1, 0x00, 0x10, 0xa0, 0xe3, ++0x00, 0x00, 0xa0, 0xe3, 0x00, 0x00, 0xa0, 0xe1, 0x00, 0x80, 0xa0, 0xe1, 0xaa, 0xfe, 0xff, 0xeb, 0x00, 0x90, 0xa0, 0xe1, ++0x20, 0x80, 0x80, 0xe5, 0x00, 0x00, 0xa0, 0xe3, 0x00, 0x10, 0xa0, 0xe3, 0x00, 0x00, 0xa0, 0xe1, 0x01, 0x10, 0x80, 0xe2, ++0x24, 0x10, 0x89, 0xe5, 0x00, 0x10, 0xa0, 0xe3, 0x00, 0x00, 0xa0, 0xe3, 0x00, 0x00, 0xa0, 0xe1, 0x28, 0x00, 0x89, 0xe5, ++0x00, 0x00, 0xa0, 0xe3, 0x00, 0x10, 0xa0, 0xe3, 0x00, 0x00, 0xa0, 0xe1, 0x2c, 0x00, 0x89, 0xe5, 0x00, 0x00, 0xa0, 0xe3, ++0x00, 0x10, 0xa0, 0xe3, 0x00, 0x00, 0xa0, 0xe1, 0x30, 0x00, 0x89, 0xe5, 0x00, 0x00, 0xa0, 0xe1, 0x00, 0x00, 0xa0, 0xe1, ++0x00, 0x00, 0xa0, 0xe1, 0x00, 0x00, 0xa0, 0xe1, 0x00, 0x00, 0xa0, 0xe1, 0x00, 0x00, 0xa0, 0xe1, 0x00, 0x00, 0xa0, 0xe1, ++0x00, 0x00, 0xa0, 0xe1, 0x00, 0x00, 0xa0, 0xe1, 0x0c, 0xd0, 0x8d, 0xe2, 0x04, 0x00, 0xa0, 0xe1, 0x05, 0x10, 0xa0, 0xe1, ++0x06, 0x20, 0xa0, 0xe1, 0x07, 0x30, 0xa0, 0xe1, 0xf0, 0x01, 0xbd, 0xe8, 0x00, 0x82, 0xbd, 0xe8, 0x00, 0x00, 0xa0, 0xe3, ++0x10, 0x40, 0x2d, 0xe9, 0x00, 0x00, 0xa0, 0xe1, 0x00, 0x00, 0xa0, 0xe1, 0x99, 0xfe, 0xff, 0xeb, 0x10, 0x80, 0xbd, 0xe8, ++0x0e, 0xf0, 0xa0, 0xe1, 0x00, 0x00, 0xe0, 0xe3, 0x02, 0x10, 0xe0, 0xe3, 0x0e, 0xf0, 0xa0, 0xe1, 0x10, 0x40, 0x2d, 0xe9, ++0x16, 0x00, 0x00, 0xeb, 0x10, 0x80, 0xbd, 0xe8, 0x0e, 0xf0, 0xa0, 0xe1, 0x0e, 0xf0, 0xa0, 0xe1, 0x70, 0x40, 0x2d, 0xe9, ++0x01, 0x50, 0xa0, 0xe1, 0x00, 0x10, 0xa0, 0xe1, 0x00, 0x40, 0xa0, 0xe1, 0x00, 0x00, 0xe0, 0xe3, 0x00, 0x00, 0xa0, 0xe1, ++0x01, 0x00, 0x70, 0xe3, 0x00, 0x20, 0xa0, 0xe1, 0x03, 0x00, 0x00, 0x1a, 0x05, 0x10, 0xa0, 0xe1, 0x04, 0x00, 0xa0, 0xe1, ++0x0c, 0x00, 0x00, 0xeb, 0x70, 0x80, 0xbd, 0xe8, 0x03, 0x00, 0x72, 0xe3, 0x05, 0x10, 0xa0, 0x11, 0x04, 0x00, 0xa0, 0x11, ++0x0f, 0xe0, 0xa0, 0x11, 0x02, 0xf0, 0xa0, 0x11, 0x00, 0x00, 0xa0, 0xe3, 0x70, 0x80, 0xbd, 0xe8, 0x0e, 0xf0, 0xa0, 0xe1, ++0x10, 0x40, 0x2d, 0xe9, 0x61, 0xfe, 0xff, 0xeb, 0x04, 0x00, 0x80, 0xe2, 0x10, 0x80, 0xbd, 0xe8, 0x01, 0x20, 0x40, 0xe2, ++0x70, 0x40, 0x2d, 0xe9, 0x0e, 0x00, 0x52, 0xe3, 0xc0, 0x50, 0x8f, 0x22, 0xb8, 0x40, 0x8f, 0xe2, 0x1c, 0x00, 0x00, 0x2a, ++0x17, 0x20, 0xa0, 0xe3, 0xc0, 0x30, 0x9f, 0xe5, 0x90, 0x02, 0x02, 0xe0, 0x03, 0x30, 0x8f, 0xe0, 0x02, 0x00, 0x50, 0xe3, ++0x03, 0x20, 0x82, 0xe0, 0x17, 0x50, 0x42, 0xe2, 0x0e, 0x00, 0x00, 0x1a, 0x01, 0x03, 0x11, 0xe3, 0xa4, 0x40, 0x8f, 0x12, ++0x11, 0x00, 0x00, 0x1a, 0x82, 0x03, 0x11, 0xe3, 0xac, 0x40, 0x8f, 0x12, 0x0e, 0x00, 0x00, 0x1a, 0x01, 0x02, 0x11, 0xe3, ++0xb0, 0x40, 0x8f, 0x12, 0x0b, 0x00, 0x00, 0x1a, 0x02, 0x02, 0x11, 0xe3, 0xb0, 0x40, 0x8f, 0x12, 0x08, 0x00, 0x00, 0x1a, ++0x01, 0x01, 0x11, 0xe3, 0xb0, 0x40, 0x8f, 0x12, 0x05, 0x00, 0x00, 0xea, 0x08, 0x00, 0x50, 0xe3, 0x01, 0x40, 0xa0, 0x01, ++0x02, 0x00, 0x00, 0x0a, 0x09, 0x00, 0x50, 0xe3, 0x01, 0x00, 0x51, 0x03, 0xa4, 0x50, 0x8f, 0x02, 0x0a, 0x00, 0xa0, 0xe3, ++0x00, 0x00, 0x00, 0xea, 0x01, 0x50, 0x85, 0xe2, 0x2b, 0x00, 0x00, 0xeb, 0x00, 0x00, 0xd5, 0xe5, 0x00, 0x00, 0x50, 0xe3, ++0xfa, 0xff, 0xff, 0x1a, 0x01, 0x00, 0x00, 0xea, 0x01, 0x40, 0x84, 0xe2, 0x25, 0x00, 0x00, 0xeb, 0x00, 0x00, 0xd4, 0xe5, ++0x00, 0x00, 0x50, 0xe3, 0xfa, 0xff, 0xff, 0x1a, 0x0a, 0x00, 0xa0, 0xe3, 0x20, 0x00, 0x00, 0xeb, 0x01, 0x00, 0xa0, 0xe3, ++0x70, 0x80, 0xbd, 0xe8, 0x00, 0x00, 0x00, 0x00, 0x55, 0x6e, 0x6b, 0x6e, 0x6f, 0x77, 0x6e, 0x20, 0x73, 0x69, 0x67, 0x6e, ++0x61, 0x6c, 0x00, 0x00, 0x88, 0x01, 0x00, 0x00, 0x49, 0x6e, 0x76, 0x61, 0x6c, 0x69, 0x64, 0x20, 0x4f, 0x70, 0x65, 0x72, ++0x61, 0x74, 0x69, 0x6f, 0x6e, 0x00, 0x00, 0x00, 0x44, 0x69, 0x76, 0x69, 0x64, 0x65, 0x20, 0x42, 0x79, 0x20, 0x5a, 0x65, ++0x72, 0x6f, 0x00, 0x00, 0x4f, 0x76, 0x65, 0x72, 0x66, 0x6c, 0x6f, 0x77, 0x00, 0x00, 0x00, 0x00, 0x55, 0x6e, 0x64, 0x65, ++0x72, 0x66, 0x6c, 0x6f, 0x77, 0x00, 0x00, 0x00, 0x49, 0x6e, 0x65, 0x78, 0x61, 0x63, 0x74, 0x20, 0x52, 0x65, 0x73, 0x75, ++0x6c, 0x74, 0x00, 0x00, 0x3a, 0x20, 0x48, 0x65, 0x61, 0x70, 0x20, 0x6d, 0x65, 0x6d, 0x6f, 0x72, 0x79, 0x20, 0x63, 0x6f, ++0x72, 0x72, 0x75, 0x70, 0x74, 0x65, 0x64, 0x00, 0x08, 0x40, 0x2d, 0xe9, 0x0d, 0x10, 0xa0, 0xe1, 0x00, 0x00, 0x8d, 0xe5, ++0x03, 0x00, 0xa0, 0xe3, 0x56, 0x34, 0x12, 0xef, 0x00, 0x90, 0xbd, 0xe8, 0x13, 0x0a, 0xa0, 0xe3, 0xd1, 0xf0, 0x21, 0xe3, ++0x00, 0xd0, 0x40, 0xe2, 0xd2, 0xf0, 0x21, 0xe3, 0x01, 0xdc, 0x40, 0xe2, 0xd7, 0xf0, 0x21, 0xe3, 0x02, 0xdc, 0x40, 0xe2, ++0xdb, 0xf0, 0x21, 0xe3, 0x03, 0xdc, 0x40, 0xe2, 0xd3, 0xf0, 0x21, 0xe3, 0x01, 0x1b, 0x40, 0xe2, 0x00, 0x00, 0x9f, 0xe5, ++0x0e, 0xf0, 0xa0, 0xe1, 0x68, 0x1d, 0x00, 0x00, 0x1e, 0xff, 0x2f, 0xe1, 0x10, 0x40, 0x2d, 0xe9, 0x91, 0xff, 0xff, 0xeb, ++0x00, 0x10, 0xa0, 0xe3, 0x00, 0x10, 0x80, 0xe5, 0x10, 0x80, 0xbd, 0xe8, 0x41, 0x62, 0x6e, 0x6f, 0x72, 0x6d, 0x61, 0x6c, ++0x20, 0x74, 0x65, 0x72, 0x6d, 0x69, 0x6e, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x00, 0x00, 0x00, 0x41, 0x72, 0x69, 0x74, 0x68, ++0x6d, 0x65, 0x74, 0x69, 0x63, 0x20, 0x65, 0x78, 0x63, 0x65, 0x70, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x00, 0x49, 0x6c, ++0x6c, 0x65, 0x67, 0x61, 0x6c, 0x20, 0x69, 0x6e, 0x73, 0x74, 0x72, 0x75, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x00, 0x00, 0x00, ++0x00, 0x49, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x20, 0x72, 0x65, 0x63, 0x65, 0x69, 0x76, 0x65, 0x64, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x49, 0x6c, 0x6c, 0x65, 0x67, 0x61, 0x6c, 0x20, 0x61, 0x64, 0x64, 0x72, 0x65, 0x73, 0x73, 0x00, ++0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x65, 0x72, 0x6d, 0x69, 0x6e, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x20, 0x72, ++0x65, 0x71, 0x75, 0x65, 0x73, 0x74, 0x00, 0x00, 0x00, 0x00, 0x53, 0x74, 0x61, 0x63, 0x6b, 0x20, 0x6f, 0x76, 0x65, 0x72, ++0x66, 0x6c, 0x6f, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x52, 0x65, 0x64, 0x69, 0x72, 0x65, 0x63, ++0x74, 0x3a, 0x20, 0x63, 0x61, 0x6e, 0x27, 0x74, 0x20, 0x6f, 0x70, 0x65, 0x6e, 0x3a, 0x20, 0x00, 0x4f, 0x75, 0x74, 0x20, ++0x6f, 0x66, 0x20, 0x68, 0x65, 0x61, 0x70, 0x20, 0x6d, 0x65, 0x6d, 0x6f, 0x72, 0x79, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, ++0x73, 0x65, 0x72, 0x2d, 0x64, 0x65, 0x66, 0x69, 0x6e, 0x65, 0x64, 0x20, 0x73, 0x69, 0x67, 0x6e, 0x61, 0x6c, 0x20, 0x31, ++0x00, 0x00, 0x55, 0x73, 0x65, 0x72, 0x2d, 0x64, 0x65, 0x66, 0x69, 0x6e, 0x65, 0x64, 0x20, 0x73, 0x69, 0x67, 0x6e, 0x61, ++0x6c, 0x20, 0x32, 0x00, 0x00, 0x50, 0x75, 0x72, 0x65, 0x20, 0x76, 0x69, 0x72, 0x74, 0x75, 0x61, 0x6c, 0x20, 0x66, 0x6e, ++0x20, 0x63, 0x61, 0x6c, 0x6c, 0x65, 0x64, 0x00, 0x43, 0x2b, 0x2b, 0x20, 0x6c, 0x69, 0x62, 0x72, 0x61, 0x72, 0x79, 0x20, ++0x65, 0x78, 0x63, 0x65, 0x70, 0x74, 0x69, 0x6f, 0x6e, 0x00, 0x00, 0x4f, 0x75, 0x74, 0x20, 0x6f, 0x66, 0x20, 0x68, 0x65, ++0x61, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x1d, 0x00, 0x00, ++0x08, 0x1d, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x30, 0x01, 0x00, 0x00}; ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc40/h263_dec_fw.c linux-2.6.28.6/drivers/media/video/samsung/mfc40/h263_dec_fw.c +--- linux-2.6.28/drivers/media/video/samsung/mfc40/h263_dec_fw.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/h263_dec_fw.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,259 @@ ++/* ++ * drivers/media/video/samsung/mfc40/h263_dec_fw.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++ ++ ++const unsigned char h263_dec_mc_fw[9672] = { ++0xea, 0x00, 0x00, 0x31, 0xea, 0x00, 0x00, 0x06, 0xea, 0x00, 0x00, 0x0b, 0xea, 0x00, 0x00, 0x10, 0xea, 0x00, 0x00, 0x15, 0xea, 0xff, 0xff, 0xfe, 0xea, 0x00, 0x00, 0x19, 0xea, 0x00, 0x00, 0x1e, 0xea, 0x00, 0x00, 0x23, 0xe2, 0x4d, 0xd0, 0x04, ++0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 0xa0, 0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x04, 0xe8, 0xbd, 0x80, 0x01, 0xe2, 0x4d, 0xd0, 0x04, 0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 0x8c, 0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x04, ++0xe8, 0xbd, 0x80, 0x01, 0xe2, 0x4d, 0xd0, 0x04, 0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 0x78, 0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x04, 0xe8, 0xbd, 0x80, 0x01, 0xe2, 0x4d, 0xd0, 0x04, 0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 0x64, ++0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x04, 0xe8, 0xbd, 0x80, 0x01, 0xe2, 0x4d, 0xd0, 0x04, 0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 0x50, 0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x04, 0xe8, 0xbd, 0x80, 0x01, 0xe2, 0x4d, 0xd0, 0x04, ++0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 0x3c, 0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x04, 0xe8, 0xbd, 0x80, 0x01, 0xe2, 0x4d, 0xd0, 0x04, 0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 0x28, 0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x04, ++0xe8, 0xbd, 0x80, 0x01, 0xeb, 0x00, 0x00, 0x07, 0xea, 0xff, 0xff, 0xfe, 0x00, 0x07, 0xff, 0x04, 0x00, 0x07, 0xff, 0x08, 0x00, 0x07, 0xff, 0x0c, 0x00, 0x07, 0xff, 0x10, 0x00, 0x07, 0xff, 0x18, 0x00, 0x07, 0xff, 0x1c, 0x00, 0x07, 0xff, 0x20, ++0xe1, 0xa0, 0x00, 0x00, 0xea, 0x00, 0x07, 0x2a, 0xe5, 0x9f, 0x30, 0x04, 0xe0, 0x8f, 0x30, 0x03, 0xe1, 0xa0, 0xf0, 0x03, 0x00, 0x00, 0x23, 0x20, 0xe9, 0x2d, 0x40, 0x10, 0xe3, 0xa0, 0x00, 0x02, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x30, ++0xeb, 0x00, 0x03, 0x6d, 0xe1, 0xa0, 0x00, 0x00, 0xea, 0xff, 0xff, 0xfe, 0xe1, 0xa0, 0x10, 0x00, 0xea, 0x00, 0x00, 0x04, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x34, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x00, 0xea, 0x00, 0x00, 0x00, ++0xea, 0xff, 0xff, 0xf9, 0xe1, 0xa0, 0x00, 0x00, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x80, 0x10, 0x0c, 0xe3, 0xa0, 0x00, 0x01, 0xe3, 0xa0, 0x28, 0x52, 0xe5, 0x82, 0x00, 0x04, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x1c, 0xe1, 0x2f, 0xff, 0x1e, ++0xe1, 0xa0, 0x10, 0x00, 0xe2, 0x41, 0x10, 0x01, 0xe3, 0x51, 0x00, 0x2f, 0xca, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0x00, 0x06, 0xe1, 0x2f, 0xff, 0x1e, 0xe3, 0x51, 0x00, 0x62, 0xca, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0x00, 0x07, 0xea, 0xff, 0xff, 0xfa, ++0xe3, 0x51, 0x0f, 0x63, 0xaa, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0x00, 0x09, 0xea, 0xff, 0xff, 0xf6, 0xe3, 0x51, 0x0e, 0x63, 0xaa, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0x00, 0x0b, 0xea, 0xff, 0xff, 0xf2, 0xe3, 0x51, 0x0d, 0x63, 0xaa, 0x00, 0x00, 0x01, ++0xe3, 0xa0, 0x00, 0x0d, 0xea, 0xff, 0xff, 0xee, 0xe3, 0x51, 0x0b, 0x09, 0xaa, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0x00, 0x0e, 0xea, 0xff, 0xff, 0xea, 0xe3, 0xa0, 0x00, 0x00, 0xea, 0xff, 0xff, 0xe8, 0xe9, 0x2d, 0x40, 0x10, 0xea, 0x00, 0x00, 0x02, ++0xe3, 0xa0, 0x00, 0x01, 0xeb, 0x00, 0x06, 0x7b, 0xe1, 0xa0, 0x40, 0x00, 0xe3, 0xa0, 0x00, 0x11, 0xeb, 0x00, 0x06, 0x6b, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0xff, 0xff, 0xf8, 0xe3, 0xa0, 0x00, 0x01, 0xe8, 0xbd, 0x80, 0x10, 0xe9, 0x2d, 0x4f, 0xf1, ++0xe2, 0x4d, 0xd0, 0x08, 0xe3, 0xa0, 0x40, 0x00, 0xe3, 0xa0, 0x06, 0x05, 0xe5, 0x90, 0x01, 0x0c, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x02, 0xe3, 0xa0, 0x00, 0x01, 0xe5, 0x9d, 0x10, 0x08, 0xe5, 0x81, 0x00, 0x5c, 0xe5, 0x9d, 0x10, 0x08, ++0xe5, 0x91, 0x00, 0x5c, 0xe3, 0x50, 0x00, 0x00, 0x1a, 0x00, 0x02, 0x43, 0xe3, 0xa0, 0x00, 0x02, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x30, 0xe5, 0x9d, 0x10, 0x08, 0xe5, 0x91, 0x00, 0x60, 0xe3, 0xa0, 0x18, 0x55, 0xe5, 0x81, 0x00, 0x00, ++0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x81, 0x00, 0x18, 0xe3, 0xa0, 0x00, 0x04, 0xe5, 0x81, 0x00, 0x1c, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x81, 0x00, 0x20, 0xe3, 0xa0, 0x06, 0x05, 0xe5, 0x90, 0x01, 0x24, 0xe5, 0x81, 0x00, 0x24, 0xe3, 0xa0, 0x00, 0x00, ++0xe3, 0xa0, 0x16, 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01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/h264_dec_fw.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,1000 @@ ++/* ++ * drivers/media/video/samsung/mfc40/h264_dec_fw.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++ ++ ++const unsigned char h264_dec_mc_fw[39296] = { ++0xea, 0x00, 0x00, 0x31, 0xea, 0x00, 0x00, 0x06, 0xea, 0x00, 0x00, 0x0b, 0xea, 0x00, 0x00, 0x10, 0xea, 0x00, 0x00, 0x15, 0xea, 0xff, 0xff, 0xfe, 0xea, 0x00, 0x00, 0x19, 0xea, 0x00, 0x00, 0x1e, 0xea, 0x00, 0x00, 0x23, 0xe2, 0x4d, 0xd0, 0x04, ++0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 0xa0, 0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x04, 0xe8, 0xbd, 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linux-2.6.28/drivers/media/video/samsung/mfc40/h264_enc_fw.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/h264_enc_fw.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,546 @@ ++/* ++ * drivers/media/video/samsung/mfc40/h264_enc_fw.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++ ++const unsigned char h264_enc_mc_fw[21180] = { ++0xea, 0x00, 0x00, 0x31, 0xea, 0x00, 0x00, 0x06, 0xea, 0x00, 0x00, 0x0b, 0xea, 0x00, 0x00, 0x10, 0xea, 0x00, 0x00, 0x15, 0xea, 0xff, 0xff, 0xfe, 0xea, 0x00, 0x00, 0x19, 0xea, 0x00, 0x00, 0x1e, 0xea, 0x00, 0x00, 0x23, 0xe2, 0x4d, 0xd0, 0x04, ++0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 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0x40, 0x05, 0xe1, 0xa0, 0x00, 0x04, 0xeb, 0xff, 0xfd, 0x5f, 0xe5, 0x9d, 0x20, 0x04, 0xe5, 0x92, 0x61, 0xb8, ++0xe3, 0x56, 0x00, 0x10, 0xba, 0x00, 0x00, 0x03, 0xe2, 0x26, 0x00, 0x1f, 0xe2, 0x80, 0x40, 0x01, 0xe2, 0x64, 0x40, 0x00, 0xea, 0x00, 0x00, 0x00, 0xe1, 0xa0, 0x40, 0x06, 0xe1, 0xa0, 0x00, 0x04, 0xeb, 0xff, 0xfd, 0x54, 0xe3, 0xa0, 0x0d, 0x3e, ++0xe0, 0x00, 0x04, 0x05, 0xe1, 0x80, 0x00, 0x07, 0xe3, 0xa0, 0x10, 0x7c, 0xe0, 0x01, 0x11, 0x86, 0xe1, 0x80, 0x00, 0x01, 0xe3, 0xa0, 0x18, 0x55, 0xe5, 0x81, 0x00, 0x80, 0xe5, 0x9d, 0x20, 0x04, 0xe5, 0x82, 0x71, 0x1c, 0xe5, 0x9d, 0x20, 0x04, ++0xe5, 0x92, 0x00, 0xf0, 0xe3, 0x50, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x15, 0xe5, 0x9d, 0x20, 0x04, 0xe5, 0x92, 0x01, 0x2c, 0xe1, 0xa0, 0x02, 0x80, 0xe5, 0x92, 0x10, 0xf0, 0xe1, 0x80, 0x01, 0x81, 0xe1, 0x80, 0x07, 0x8b, 0xe1, 0x80, 0x04, 0x0a, ++0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x48, 0xe5, 0x9d, 0x20, 0x04, 0xe5, 0x92, 0x81, 0x04, 0xe3, 0xa0, 0x05, 0x02, 0xe5, 0x9d, 0x10, 0x0c, 0xe1, 0x80, 0x04, 0x01, 0xe5, 0x9d, 0x20, 0x04, 0xe5, 0x92, 0x11, 0x00, 0xe1, 0x80, 0x03, 0x01, ++0xe1, 0x80, 0x00, 0x08, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x4c, 0xe3, 0xa0, 0x00, 0x10, 0xe5, 0x81, 0x00, 0x00, 0xe2, 0x8d, 0xd0, 0x14, 0xe8, 0xbd, 0x8f, 0xf0, 0xe9, 0x2d, 0x4f, 0xff, 0xe2, 0x4d, 0xd0, 0x4c, 0xe3, 0xa0, 0x00, 0x00, ++0xe5, 0x8d, 0x00, 0x48, 0xe5, 0x8d, 0x00, 0x44, 0xe5, 0x8d, 0x00, 0x38, 0xe5, 0x8d, 0x00, 0x34, 0xe5, 0x8d, 0x00, 0x30, 0xe5, 0x8d, 0x00, 0x2c, 0xe5, 0x8d, 0x00, 0x28, 0xe5, 0x8d, 0x00, 0x24, 0xe5, 0x8d, 0x00, 0x20, 0xe5, 0x8d, 0x00, 0x1c, ++0xe5, 0x8d, 0x00, 0x18, 0xe5, 0x8d, 0x00, 0x14, 0xe3, 0xa0, 0xa0, 0x00, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x10, 0xe3, 0xa0, 0x00, 0x01, 0xe5, 0x81, 0x00, 0x00, 0xe5, 0x9d, 0x00, 0x4c, 0xe5, 0x90, 0x00, 0xf0, 0xe3, 0x50, 0x00, 0x00, ++0x1a, 0x00, 0x00, 0x02, 0xe3, 0xa0, 0x00, 0x04, 0xe5, 0x81, 0x00, 0x08, 0xea, 0x00, 0x00, 0x02, 0xe3, 0xa0, 0x00, 0x80, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x08, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x40, 0xe3, 0xa0, 0x10, 0x00, ++0xe5, 0x8d, 0x10, 0x3c, 0xe5, 0x9d, 0x00, 0x4c, 0xe5, 0x90, 0x00, 0xf0, 0xe3, 0x50, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x02, 0xe3, 0xa0, 0x00, 0x00, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x54, 0xe5, 0x9d, 0x00, 0x4c, 0xe5, 0x90, 0x01, 0x24, ++0xe5, 0x9d, 0x10, 0x4c, 0xe5, 0x91, 0x11, 0x20, 0xe0, 0x00, 0x00, 0x91, 0xe5, 0x8d, 0x00, 0x10, 0xe3, 0xa0, 0x06, 0x05, 0xe5, 0x90, 0x08, 0x10, 0xe1, 0xa0, 0x0a, 0x00, 0xe1, 0xa0, 0x0a, 0x20, 0xe5, 0x9d, 0x10, 0x4c, 0xe5, 0x81, 0x01, 0xa8, ++0xe5, 0x9d, 0x00, 0x4c, 0xe5, 0x90, 0x01, 0xa8, 0xe5, 0x9d, 0x10, 0x4c, 0xe5, 0x91, 0x11, 0xbc, 0xe1, 0x80, 0x08, 0x01, 0xe3, 0xa0, 0x18, 0x55, 0xe5, 0x81, 0x00, 0x4c, 0xe5, 0x9d, 0x00, 0x50, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x06, ++0xe5, 0x9d, 0x00, 0x4c, 0xe5, 0x90, 0x01, 0xbc, 0xe5, 0x9d, 0x10, 0x4c, 0xe5, 0x91, 0x11, 0xa8, 0xe0, 0x80, 0x00, 0x01, 0xe5, 0x9d, 0x10, 0x4c, 0xe5, 0x81, 0x01, 0xbc, 0xe5, 0x9d, 0x00, 0x10, 0xe2, 0x40, 0x00, 0x01, 0xe5, 0x9d, 0x10, 0x4c, ++0xe5, 0x91, 0x11, 0xbc, 0xe1, 0x50, 0x00, 0x01, 0xaa, 0x00, 0x00, 0x02, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x9d, 0x10, 0x4c, 0xe5, 0x81, 0x01, 0xbc, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x18, 0xe5, 0x9d, 0x00, 0x4c, 0xe5, 0x90, 0x01, 0x0c, ++0xe3, 0x50, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x17, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x44, 0xe5, 0x8d, 0x00, 0x20, 0xe2, 0x8d, 0x30, 0x3c, 0xe8, 0x93, 0x00, 0x0c, 0xe8, 0x8d, 0x00, 0x0c, 0xe5, 0x9d, 0x00, 0x4c, 0xe3, 0xa0, 0x30, 0x00, ++0xe5, 0x90, 0x11, 0x84, 0xe5, 0x9d, 0x20, 0x50, 0xeb, 0xff, 0xff, 0x01, 0xe3, 0xa0, 0x00, 0x01, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0xc8, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x44, 0xe5, 0x9d, 0x10, 0x20, 0xe0, 0x40, 0x00, 0x01, ++0xe2, 0x40, 0x00, 0x28, 0xe5, 0x8d, 0x00, 0x20, 0xe5, 0x9d, 0x00, 0x18, 0xe5, 0x9d, 0x10, 0x20, 0xe0, 0x80, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x18, 0xe5, 0x9d, 0x00, 0x4c, 0xe5, 0x90, 0x61, 0x0c, 0xe5, 0x9d, 0x00, 0x4c, 0xe5, 0x90, 0x70, 0xf0, ++0xe3, 0x56, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x83, 0xea, 0x00, 0x00, 0x7d, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x44, 0xe5, 0x8d, 0x00, 0x20, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x9d, 0x10, 0x4c, 0xe5, 0x81, 0x00, 0xd4, 0xe5, 0x8d, 0x00, 0x38, ++0xe5, 0x8d, 0x00, 0x2c, 0xe3, 0xa0, 0x00, 0x01, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0xc8, 0xea, 0x00, 0x00, 0x04, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0xd4, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x00, 0xea, 0x00, 0x00, 0x00, ++0xea, 0xff, 0xff, 0xf9, 0xe1, 0xa0, 0x00, 0x00, 0xe3, 0xa0, 0x00, 0x00, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0xc8, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x9d, 0x10, 0x44, 0xe5, 0x80, 0x10, 0x10, 0xe3, 0x57, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x15, ++0xe5, 0x9d, 0x00, 0x4c, 0xe5, 0x90, 0x01, 0x24, 0xe1, 0xa0, 0x0a, 0x00, 0xe5, 0x9d, 0x10, 0x4c, 0xe5, 0x91, 0x11, 0x20, 0xe1, 0x80, 0x02, 0x01, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x14, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x9d, 0x10, 0x10, ++0xe5, 0x80, 0x10, 0x58, 0xe3, 0xa0, 0x08, 0x01, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x04, 0xea, 0x00, 0x00, 0x04, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x20, 0xe3, 0x50, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0xea, 0x00, 0x00, 0x00, ++0xea, 0xff, 0xff, 0xf9, 0xea, 0x00, 0x00, 0x14, 0xe2, 0x8d, 0x10, 0x4c, 0xe8, 0x91, 0x00, 0x03, 0xeb, 0xff, 0xfe, 0x9b, 0xe5, 0x9d, 0x00, 0x50, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x06, 0xe5, 0x9d, 0x00, 0x4c, 0xe5, 0x90, 0x00, 0xd4, ++0xe3, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x02, 0xe5, 0x9d, 0x00, 0x48, 0xe2, 0x80, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x48, 0xe5, 0x9d, 0x10, 0x50, 0xe5, 0x9d, 0x20, 0x48, 0xe5, 0x9d, 0x30, 0x34, 0xe8, 0x8d, 0x00, 0x0e, 0xe5, 0x9d, 0x00, 0x4c, ++0xe2, 0x8d, 0x30, 0x3c, 0xe8, 0x93, 0x00, 0x0e, 0xeb, 0xff, 0xfe, 0x1e, 0xe5, 0x9d, 0x10, 0x44, 0xe2, 0x81, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x44, 0xe3, 0x57, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x10, 0xe5, 0x9d, 0x00, 0x10, 0xe5, 0x9d, 0x10, 0x44, ++0xe1, 0x51, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x0c, 0xe3, 0xa0, 0x00, 0x01, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x54, 0xe3, 0xa0, 0x08, 0x01, 0xe5, 0x81, 0x00, 0x04, 0xea, 0x00, 0x00, 0x04, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x20, ++0xe3, 0x50, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0xea, 0x00, 0x00, 0x00, 0xea, 0xff, 0xff, 0xf9, 0xe1, 0xa0, 0x00, 0x00, 0xe5, 0x9d, 0x10, 0x3c, 0xe2, 0x81, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x3c, 0xe5, 0x9d, 0x00, 0x4c, 0xe5, 0x90, 0x01, 0x20, ++0xe5, 0x9d, 0x10, 0x3c, 0xe1, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x04, 0xe5, 0x9d, 0x00, 0x40, 0xe2, 0x80, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x40, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x3c, 0xe5, 0x9d, 0x00, 0x50, 0xe3, 0x50, 0x00, 0x01, ++0x1a, 0x00, 0x00, 0x03, 0xe5, 0x9d, 0x00, 0x4c, 0xe5, 0x90, 0x00, 0xd4, 0xe3, 0x50, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x48, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x44, 0xe0, 0x80, 0xa0, 0x0a, ++0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x44, 0xe5, 0x9d, 0x10, 0x20, 0xe0, 0x40, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x20, 0xe5, 0x9d, 0x00, 0x18, 0xe5, 0x9d, 0x10, 0x20, 0xe0, 0x80, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x18, 0xe5, 0x9d, 0x00, 0x10, ++0xe5, 0x9d, 0x10, 0x44, 0xe1, 0x51, 0x00, 0x00, 0xba, 0xff, 0xff, 0x7d, 0xea, 0x00, 0x01, 0xb1, 0xea, 0x00, 0x01, 0xac, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x20, 0xe5, 0x9d, 0x10, 0x4c, 0xe5, 0x81, 0x00, 0xd4, 0xe3, 0x56, 0x00, 0x00, ++0x0a, 0x00, 0x00, 0x19, 0xe5, 0x9d, 0x00, 0x4c, 0xe5, 0x90, 0x01, 0x68, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x91, 0x10, 0x44, 0xe0, 0x80, 0x00, 0x01, 0xe5, 0x9d, 0x10, 0x4c, 0xe5, 0x81, 0x01, 0x68, 0xe2, 0x8d, 0x30, 0x3c, 0xe8, 0x93, 0x00, 0x0c, ++0xe8, 0x8d, 0x00, 0x0c, 0xe5, 0x9d, 0x00, 0x4c, 0xe5, 0x90, 0x11, 0x84, 0xe5, 0x9d, 0x20, 0x50, 0xe5, 0x9d, 0x30, 0x44, 0xeb, 0xff, 0xfe, 0x54, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x48, 0xe5, 0x9d, 0x10, 0x44, 0xe3, 0x51, 0x00, 0x00, ++0x0a, 0x00, 0x00, 0x02, 0xe3, 0xa0, 0x00, 0x02, 0xe3, 0xa0, 0x18, 0x56, 0xe5, 0x81, 0x00, 0x14, 0xe3, 0xa0, 0x00, 0x01, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0xc8, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x38, 0xe5, 0x8d, 0x00, 0x2c, ++0xea, 0x00, 0x01, 0x19, 0xe3, 0x56, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x0e, 0xe5, 0x9d, 0x00, 0x4c, 0xe5, 0x90, 0x01, 0x10, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x0a, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x44, 0xe5, 0x8d, 0x00, 0x28, ++0xe5, 0x9d, 0x00, 0x4c, 0xe5, 0x90, 0x01, 0x14, 0xe5, 0x9d, 0x10, 0x28, 0xe1, 0x50, 0x01, 0xc1, 0xaa, 0x00, 0x00, 0x02, 0xe3, 0xa0, 0x00, 0x01, 0xe3, 0xa0, 0x16, 0x02, 0xe5, 0x81, 0x00, 0xa0, 0xe3, 0xa0, 0x00, 0x01, 0xe3, 0xa0, 0x18, 0x52, ++0xe5, 0x81, 0x00, 0xc8, 0xea, 0x00, 0x00, 0x04, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0xd4, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x00, 0xea, 0x00, 0x00, 0x00, 0xea, 0xff, 0xff, 0xf9, 0xe1, 0xa0, 0x00, 0x00, 0xe3, 0xa0, 0x00, 0x00, ++0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0xc8, 0xe3, 0x56, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x24, 0xe3, 0x57, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x22, 0xe3, 0xa0, 0x06, 0x02, 0xe5, 0x90, 0x00, 0x00, 0xe3, 0x70, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x03, ++0xe3, 0xa0, 0x06, 0x02, 0xe5, 0x90, 0x00, 0x04, 0xe1, 0xa0, 0x0d, 0x20, 0xe5, 0x8d, 0x00, 0x14, 0xe3, 0xa0, 0x06, 0x02, 0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x30, 0xe5, 0x9d, 0x00, 0x30, 0xe3, 0x70, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x0a, ++0xea, 0x00, 0x00, 0x07, 0xe3, 0xa0, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x2c, 0xe5, 0x8d, 0x00, 0x38, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0xdc, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x00, 0xea, 0x00, 0x00, 0x00, 0xea, 0xff, 0xff, 0xf6, ++0xea, 0x00, 0x00, 0x77, 0xe5, 0x9d, 0x00, 0x10, 0xe2, 0x40, 0x00, 0x01, 0xe5, 0x9d, 0x10, 0x44, 0xe1, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x72, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x2c, 0xe3, 0xa0, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x38, ++0xea, 0x00, 0x00, 0x6d, 0xe3, 0x56, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x6b, 0xe3, 0xa0, 0x06, 0x02, 0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x30, 0xe5, 0x9d, 0x00, 0x30, 0xe3, 0x70, 0x00, 0x01, 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0xa0, 0x00, 0x00, ++0xeb, 0xff, 0xfb, 0x7c, 0xea, 0x00, 0x00, 0x03, 0xe3, 0xa0, 0x10, 0x20, 0xe3, 0xe0, 0x00, 0x00, 0xeb, 0xff, 0xfb, 0x78, 0xe2, 0x44, 0x40, 0x20, 0xe3, 0x54, 0x00, 0x20, 0xaa, 0xff, 0xff, 0xf9, 0xea, 0x00, 0x00, 0x03, 0xe3, 0xa0, 0x10, 0x04, ++0xe3, 0xa0, 0x00, 0x0f, 0xeb, 0xff, 0xfb, 0x71, 0xe2, 0x44, 0x40, 0x04, 0xe3, 0x54, 0x00, 0x04, 0xaa, 0xff, 0xff, 0xf9, 0xea, 0x00, 0x00, 0x04, 0x00, 0x00, 0xff, 0xff, 0xe3, 0xa0, 0x10, 0x01, 0xe3, 0xa0, 0x00, 0x01, 0xeb, 0xff, 0xfb, 0x69, ++0xe2, 0x44, 0x40, 0x01, 0xe3, 0x54, 0x00, 0x00, 0x1a, 0xff, 0xff, 0xf9, 0xea, 0x00, 0x00, 0x0f, 0xe3, 0xa0, 0x10, 0x01, 0xe3, 0xa0, 0x00, 0x01, 0xeb, 0xff, 0xfb, 0x62, 0xea, 0x00, 0x00, 0x03, 0xe3, 0xa0, 0x10, 0x10, 0xe3, 0xa0, 0x00, 0x00, ++0xeb, 0xff, 0xfb, 0x5e, 0xe2, 0x44, 0x40, 0x10, 0xe3, 0x54, 0x00, 0x10, 0xaa, 0xff, 0xff, 0xf9, 0xe3, 0x54, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x02, 0xe1, 0xa0, 0x10, 0x04, 0xe3, 0xa0, 0x00, 0x00, 0xeb, 0xff, 0xfb, 0x56, 0xe3, 0xa0, 0x40, 0x00, ++0xe3, 0x58, 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0xe5, 0x99, 0x9a, 0x20, 0xe5, 0x8a, 0x91, 0x60, ++0xe3, 0xa0, 0x96, 0x05, 0xe5, 0x99, 0x9a, 0x24, 0xe5, 0x8a, 0x91, 0x64, 0xe3, 0xa0, 0x96, 0x05, 0xe5, 0x99, 0x9a, 0x28, 0xe5, 0x8a, 0x91, 0x68, 0xe3, 0xa0, 0x96, 0x05, 0xe5, 0x99, 0x9a, 0x2c, 0xe5, 0x8a, 0x91, 0x6c, 0xe3, 0xa0, 0x96, 0x05, ++0xe5, 0x99, 0x9a, 0x30, 0xe5, 0x8a, 0x91, 0x70, 0xe3, 0xa0, 0x96, 0x05, 0xe5, 0x99, 0x9a, 0x38, 0xe5, 0x8a, 0x91, 0x78, 0xe3, 0xa0, 0x96, 0x05, 0xe5, 0x99, 0x9a, 0x3c, 0xe5, 0x8a, 0x91, 0x7c, 0xe3, 0xa0, 0x96, 0x05, 0xe5, 0x99, 0x9a, 0x40, ++0xe5, 0x8a, 0x91, 0x80, 0xe3, 0xa0, 0x96, 0x05, 0xe5, 0x99, 0x9a, 0x44, 0xe5, 0x8a, 0x91, 0x84, 0xe3, 0xa0, 0x96, 0x05, 0xe5, 0x99, 0x9a, 0x00, 0xe1, 0xa0, 0x94, 0xa9, 0xe5, 0x80, 0x91, 0x70, 0xe5, 0x90, 0x91, 0x70, 0xe2, 0x09, 0x90, 0x01, ++0xe5, 0x80, 0x91, 0x70, 0xe3, 0xa0, 0x96, 0x05, 0xe5, 0x99, 0x9a, 0x00, 0xe1, 0xa0, 0x94, 0x29, 0xe5, 0x80, 0x91, 0x74, 0xe5, 0x90, 0x91, 0x74, 0xe2, 0x09, 0x90, 0x01, 0xe5, 0x80, 0x91, 0x74, 0xe5, 0x90, 0x91, 0x0c, 0xe3, 0x59, 0x00, 0x00, ++0x1a, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0x90, 0x00, 0xe5, 0x80, 0x91, 0x18, 0xe3, 0xa0, 0x96, 0x05, 0xe5, 0x99, 0x18, 0x00, 0xe3, 0xa0, 0xa8, 0x55, 0xe5, 0x90, 0x91, 0xa4, 0xe5, 0x8a, 0x90, 0x00, 0xe5, 0x90, 0x91, 0x0c, 0xe3, 0x59, 0x00, 0x00, ++0x0a, 0x00, 0x00, 0x02, 0xe5, 0x90, 0x91, 0x10, 0xe3, 0x59, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0x90, 0x00, 0xe5, 0x80, 0x91, 0x18, 0xe3, 0xa0, 0xa8, 0x55, 0xe5, 0x90, 0x91, 0x18, 0xe5, 0x8a, 0x90, 0x14, 0xe3, 0xa0, 0x96, 0x05, ++0xe5, 0x99, 0x91, 0x20, 0xe5, 0x8a, 0x90, 0x18, 0xe3, 0xa0, 0x90, 0x00, 0xe5, 0x8a, 0x90, 0x1c, 0xe3, 0xa0, 0x90, 0x01, 0xe5, 0x8a, 0x90, 0x20, 0xe3, 0xa0, 0x96, 0x05, 0xe5, 0x99, 0x91, 0x24, 0xe5, 0x8a, 0x90, 0x24, 0xe3, 0xa0, 0x96, 0x05, ++0xe5, 0x99, 0x98, 0x10, 0xe1, 0xa0, 0x9a, 0x09, 0xe1, 0xa0, 0x9a, 0x29, 0xe5, 0x80, 0x91, 0xa8, 0xe5, 0x8a, 0x90, 0x4c, 0xe3, 0xa0, 0x96, 0x05, 0xe5, 0x99, 0x92, 0x34, 0xe5, 0x80, 0x91, 0xac, 0xe5, 0x8a, 0x91, 0x90, 0xe3, 0xa0, 0x96, 0x05, ++0xe5, 0x99, 0x98, 0x0c, 0xe1, 0xa0, 0x10, 0x09, 0xe3, 0xa0, 0x96, 0x05, 0xe5, 0x99, 0x96, 0x00, 0xe5, 0x80, 0x91, 0xa4, 0xe5, 0x90, 0x91, 0x20, 0xe1, 0xa0, 0x92, 0x09, 0xe5, 0x90, 0xa1, 0x24, 0xe1, 0xa0, 0xa2, 0x0a, 0xe0, 0x05, 0x09, 0x9a, ++0xe5, 0x90, 0x91, 0x20, 0xe1, 0xa0, 0x82, 0x09, 0xe5, 0x90, 0x91, 0x24, 0xe1, 0xa0, 0x72, 0x09, 0xe5, 0x90, 0x91, 0xa4, 0xe3, 0x59, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x0e, 0xe3, 0xa0, 0x98, 0x55, 0xe5, 0x89, 0x10, 0x3c, 0xe5, 0x80, 0x11, 0x94, ++0xe0, 0x81, 0x90, 0x05, 0xe3, 0xa0, 0xa8, 0x55, 0xe5, 0x8a, 0x90, 0x40, 0xe5, 0x80, 0x91, 0x98, 0xe0, 0x81, 0x90, 0x85, 0xe5, 0x8a, 0x90, 0x44, 0xe5, 0x80, 0x91, 0x9c, 0xe0, 0x85, 0x91, 0x05, 0xe0, 0x81, 0x90, 0xa9, 0xe5, 0x8a, 0x90, 0x48, ++0xe5, 0x80, 0x91, 0xa0, 0xea, 0x00, 0x00, 0x41, 0xe1, 0xa0, 0x16, 0xa1, 0xe3, 0xa0, 0x30, 0x00, 0xea, 0x00, 0x00, 0x3c, 0xe2, 0x48, 0xc0, 0x01, 0xe3, 0x53, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x01, 0xe2, 0x47, 0x90, 0x01, 0xea, 0x00, 0x00, 0x01, ++0xe3, 0xa0, 0x90, 0x01, 0xe0, 0x69, 0x90, 0xa7, 0xe1, 0xa0, 0xe0, 0x09, 0xe3, 0xa0, 0xa0, 0x01, 0xe0, 0x8a, 0x43, 0xac, 0xe0, 0x8a, 0x63, 0x2e, 0xe3, 0xb0, 0x90, 0x00, 0x0a, 0x00, 0x00, 0x1b, 0xe3, 0xa0, 0x90, 0x7f, 0xe0, 0x09, 0xc4, 0x2c, ++0xe1, 0x89, 0x91, 0x09, 0xe0, 0x09, 0xe3, 0x2e, 0xe3, 0x53, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x0a, 0xe3, 0xa0, 0x20, 0x00, 0xea, 0x00, 0x00, 0x05, 0xe2, 0x80, 0x9f, 0x65, 0xe7, 0x89, 0x11, 0x02, 0xe0, 0x29, 0xce, 0x94, 0xe2, 0x89, 0x90, 0x01, ++0xe0, 0x89, 0x10, 0x01, 0xe2, 0x82, 0x20, 0x01, 0xe3, 0x52, 0x00, 0x02, 0x3a, 0xff, 0xff, 0xf7, 0xea, 0x00, 0x00, 0x1d, 0xe3, 0xa0, 0x20, 0x00, 0xea, 0x00, 0x00, 0x05, 0xe2, 0x80, 0x9f, 0x67, 0xe7, 0x89, 0x11, 0x02, 0xe0, 0x29, 0xce, 0x94, ++0xe2, 0x89, 0x90, 0x01, 0xe0, 0x89, 0x10, 0x01, 0xe2, 0x82, 0x20, 0x01, 0xe3, 0x52, 0x00, 0x02, 0x3a, 0xff, 0xff, 0xf7, 0xea, 0x00, 0x00, 0x12, 0xe3, 0x53, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x08, 0xe3, 0xa0, 0x20, 0x00, 0xea, 0x00, 0x00, 0x03, ++0xe2, 0x80, 0x9f, 0x65, 0xe7, 0x89, 0x11, 0x02, 0xe0, 0x21, 0x14, 0x96, 0xe2, 0x82, 0x20, 0x01, 0xe3, 0x52, 0x00, 0x02, 0x3a, 0xff, 0xff, 0xf9, 0xea, 0x00, 0x00, 0x07, 0xe3, 0xa0, 0x20, 0x00, 0xea, 0x00, 0x00, 0x03, 0xe2, 0x80, 0x9f, 0x67, ++0xe7, 0x89, 0x11, 0x02, 0xe0, 0x21, 0x14, 0x96, 0xe2, 0x82, 0x20, 0x01, 0xe3, 0x52, 0x00, 0x02, 0x3a, 0xff, 0xff, 0xf9, 0xe2, 0x83, 0x30, 0x01, 0xe3, 0x53, 0x00, 0x02, 0x3a, 0xff, 0xff, 0xc0, 0xe8, 0xbd, 0x87, 0xf0, 0xe3, 0xa0, 0x1e, 0x16, ++0xe5, 0x80, 0x10, 0xdc, 0xe3, 0xa0, 0x1e, 0x12, 0xe5, 0x80, 0x10, 0xe0, 0xe3, 0xa0, 0x10, 0x00, 0xe5, 0x80, 0x10, 0xe4, 0xe3, 0xa0, 0x10, 0x42, 0xe5, 0x80, 0x10, 0xe8, 0xe3, 0xa0, 0x10, 0x04, 0xe5, 0x80, 0x10, 0xec, 0xe3, 0xa0, 0x10, 0x00, ++0xe5, 0x80, 0x10, 0xf4, 0xe5, 0x80, 0x10, 0xf8, 0xe5, 0x80, 0x11, 0x00, 0xe5, 0x80, 0x11, 0xb4, 0xe5, 0x80, 0x11, 0xb8, 0xe5, 0x80, 0x10, 0xf0, 0xe5, 0x80, 0x10, 0xfc, 0xe3, 0xa0, 0x10, 0x1a, 0xe5, 0x80, 0x11, 0x04, 0xe3, 0xa0, 0x10, 0x00, ++0xe5, 0x80, 0x11, 0x0c, 0xe3, 0xa0, 0x10, 0x0f, 0xe5, 0x80, 0x11, 0x18, 0xe3, 0xa0, 0x10, 0x0b, 0xe5, 0x80, 0x11, 0x20, 0xe3, 0xa0, 0x10, 0x09, 0xe5, 0x80, 0x11, 0x24, 0xe3, 0xa0, 0x10, 0x01, 0xe5, 0x80, 0x11, 0x2c, 0xe3, 0xa0, 0x10, 0x00, ++0xe5, 0x80, 0x11, 0x5c, 0xe5, 0x80, 0x11, 0x60, 0xe5, 0x80, 0x11, 0x64, 0xe3, 0xa0, 0x10, 0x04, 0xe5, 0x80, 0x11, 0x28, 0xe3, 0xa0, 0x10, 0x00, 0xe5, 0x80, 0x11, 0x30, 0xe5, 0x80, 0x11, 0x38, 0xe5, 0x80, 0x11, 0x40, 0xe5, 0x80, 0x11, 0x44, ++0xe5, 0x80, 0x11, 0x48, 0xe3, 0xa0, 0x10, 0x01, 0xe5, 0x80, 0x11, 0x80, 0xe3, 0xa0, 0x10, 0x00, 0xe5, 0x80, 0x11, 0x84, 0xe5, 0x80, 0x11, 0x8c, 0xe5, 0x80, 0x11, 0x90, 0xe5, 0x80, 0x11, 0x88, 0xe5, 0x80, 0x11, 0x94, 0xe5, 0x80, 0x11, 0x98, ++0xe5, 0x80, 0x11, 0x9c, 0xe5, 0x80, 0x11, 0xa0, 0xe5, 0x80, 0x11, 0xc4, 0xe5, 0x80, 0x11, 0xb0, 0xe5, 0x80, 0x11, 0xbc, 0xe1, 0x2f, 0xff, 0x1e, 0xe9, 0x2d, 0x40, 0x10, 0xe1, 0xa0, 0x40, 0x00, 0xe3, 0xa0, 0x00, 0x14, 0xe3, 0xa0, 0x18, 0x52, ++0xe5, 0x81, 0x00, 0x30, 0xe1, 0xa0, 0x00, 0x04, 0xeb, 0xff, 0xff, 0xbf, 0xe1, 0xa0, 0x00, 0x04, 0xeb, 0xff, 0xfe, 0xbb, 0xe1, 0xa0, 0x00, 0x04, 0xeb, 0xff, 0xfe, 0x95, 0xe8, 0xbd, 0x80, 0x10, 0xe9, 0x2d, 0x40, 0x70, 0xe1, 0xa0, 0x00, 0x00, ++0xe3, 0xa0, 0x0f, 0x9f, 0xeb, 0x00, 0x04, 0x74, 0xe1, 0xa0, 0x60, 0x00, 0xe1, 0xa0, 0x00, 0x06, 0xeb, 0xff, 0xff, 0xec, 0xe3, 0xa0, 0x00, 0x00, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x44, 0xe5, 0x81, 0x00, 0xb4, 0xe3, 0xa0, 0x0c, 0x02, ++0xe5, 0x81, 0x00, 0x04, 0xea, 0x00, 0x00, 0x05, 0xe1, 0xa0, 0x00, 0x06, 0xeb, 0xff, 0xfd, 0x10, 0xe5, 0x96, 0x01, 0xc4, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x00, 0xea, 0x00, 0x00, 0x00, 0xea, 0xff, 0xff, 0xf8, 0xe1, 0xa0, 0x00, 0x00, ++0xea, 0x00, 0x00, 0x04, 0xe3, 0xa0, 0x06, 0x05, 0xe5, 0x90, 0x00, 0x3c, 0xe3, 0x50, 0x00, 0x08, 0x2a, 0x00, 0x00, 0x00, 0xea, 0x00, 0x00, 0x00, 0xea, 0xff, 0xff, 0xf9, 0xe1, 0xa0, 0x00, 0x00, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x30, ++0xe2, 0x20, 0x00, 0x20, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x30, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x50, 0x68, 0xe3, 0x55, 0x00, 0x08, 0x1a, 0x00, 0x00, 0x06, 0xe3, 0xa0, 0x00, 0x01, 0xe3, 0xa0, 0x16, 0x05, 0xe5, 0x81, 0x00, 0x10, ++0xe3, 0xa0, 0x10, 0x18, 0xe3, 0xa0, 0x00, 0x00, 0xeb, 0xff, 0xf6, 0xa2, 0xea, 0x00, 0x00, 0x14, 0xe3, 0x55, 0x00, 0x10, 0x1a, 0x00, 0x00, 0x06, 0xe3, 0xa0, 0x00, 0x02, 0xe3, 0xa0, 0x16, 0x05, 0xe5, 0x81, 0x00, 0x10, 0xe3, 0xa0, 0x10, 0x10, ++0xe3, 0xa0, 0x00, 0x00, 0xeb, 0xff, 0xf6, 0x99, 0xea, 0x00, 0x00, 0x0b, 0xe3, 0x55, 0x00, 0x18, 0x1a, 0x00, 0x00, 0x06, 0xe3, 0xa0, 0x00, 0x03, 0xe3, 0xa0, 0x16, 0x05, 0xe5, 0x81, 0x00, 0x10, 0xe3, 0xa0, 0x10, 0x08, 0xe3, 0xa0, 0x00, 0x00, ++0xeb, 0xff, 0xf6, 0x90, 0xea, 0x00, 0x00, 0x02, 0xe3, 0xa0, 0x00, 0x00, 0xe3, 0xa0, 0x16, 0x05, 0xe5, 0x81, 0x00, 0x10, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x30, 0xe2, 0x20, 0x00, 0x20, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x30, ++0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x44, 0xe2, 0x00, 0x40, 0x1f, 0xe1, 0xa0, 0x00, 0x00, 0xea, 0x00, 0x00, 0x04, 0xe3, 0xa0, 0x06, 0x05, 0xe5, 0x90, 0x00, 0x3c, 0xe3, 0x50, 0x00, 0x08, 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0x02, 0x02, 0x21, 0x11, 0x02, 0xe3, 0xa0, 0x00, 0x00, 0xe1, 0xa0, 0xf0, 0x0e, ++0xe8, 0xbd, 0x40, 0x70, 0xe5, 0x9f, 0x12, 0xec, 0xe3, 0xa0, 0x00, 0x01, 0xe1, 0xa0, 0xf0, 0x0e, 0xe9, 0x2d, 0x49, 0x80, 0xe2, 0x8f, 0x7f, 0x73, 0xe9, 0x2d, 0x00, 0x70, 0xe1, 0xa0, 0x48, 0x23, 0xe1, 0xa0, 0x68, 0x22, 0xe7, 0xd7, 0x74, 0x24, ++0xe1, 0xc2, 0xe8, 0x06, 0xe1, 0xc3, 0x58, 0x04, 0xe0, 0x2c, 0x77, 0x94, 0xe1, 0xb0, 0x10, 0xa1, 0xe1, 0xb0, 0x00, 0x60, 0xe2, 0x6c, 0xc5, 0x02, 0x33, 0xa0, 0xb0, 0x00, 0xe0, 0x07, 0x07, 0x9c, 0xe1, 0xa0, 0xc6, 0xa3, 0x23, 0xa0, 0xb1, 0x02, ++0xe1, 0xa0, 0x79, 0xa7, 0xe2, 0x87, 0x70, 0x02, 0xe0, 0x28, 0x77, 0x9c, 0xe2, 0x68, 0x82, 0x02, 0xe1, 0xa0, 0xc8, 0x28, 0xe1, 0xc8, 0x88, 0x0c, 0xe0, 0x03, 0x07, 0x9c, 0xe0, 0x02, 0x07, 0x98, 0xe1, 0xa0, 0xc7, 0xa1, 0xe0, 0x83, 0x78, 0x22, ++0xe1, 0xa0, 0x73, 0x27, 0xe0, 0x08, 0x0c, 0x97, 0xe1, 0xa0, 0x88, 0x28, 0xe0, 0x0c, 0x06, 0x98, 0xe1, 0xa0, 0x38, 0x08, 0xe0, 0x50, 0x00, 0x0c, 0xe0, 0x0c, 0x08, 0x94, 0xe0, 0xc1, 0x10, 0x0c, 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0x61, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc40/mp2_dec_fw.c linux-2.6.28.6/drivers/media/video/samsung/mfc40/mp2_dec_fw.c +--- linux-2.6.28/drivers/media/video/samsung/mfc40/mp2_dec_fw.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/mp2_dec_fw.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,382 @@ ++/* ++ * drivers/media/video/samsung/mfc40/mp2_dec_fw.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++ ++const unsigned char mp2_dec_mc_fw[14636] = { ++0xea, 0x00, 0x00, 0x31, 0xea, 0x00, 0x00, 0x06, 0xea, 0x00, 0x00, 0x0b, 0xea, 0x00, 0x00, 0x10, 0xea, 0x00, 0x00, 0x15, 0xea, 0xff, 0xff, 0xfe, 0xea, 0x00, 0x00, 0x19, 0xea, 0x00, 0x00, 0x1e, 0xea, 0x00, 0x00, 0x23, 0xe2, 0x4d, 0xd0, 0x04, ++0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 0xa0, 0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x04, 0xe8, 0xbd, 0x80, 0x01, 0xe2, 0x4d, 0xd0, 0x04, 0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 0x8c, 0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x04, ++0xe8, 0xbd, 0x80, 0x01, 0xe2, 0x4d, 0xd0, 0x04, 0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 0x78, 0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x04, 0xe8, 0xbd, 0x80, 0x01, 0xe2, 0x4d, 0xd0, 0x04, 0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 0x64, ++0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x04, 0xe8, 0xbd, 0x80, 0x01, 0xe2, 0x4d, 0xd0, 0x04, 0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 0x50, 0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x04, 0xe8, 0xbd, 0x80, 0x01, 0xe2, 0x4d, 0xd0, 0x04, ++0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 0x3c, 0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x04, 0xe8, 0xbd, 0x80, 0x01, 0xe2, 0x4d, 0xd0, 0x04, 0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 0x28, 0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x04, ++0xe8, 0xbd, 0x80, 0x01, 0xeb, 0x00, 0x00, 0x07, 0xea, 0xff, 0xff, 0xfe, 0x00, 0x00, 0xff, 0x04, 0x00, 0x00, 0xff, 0x08, 0x00, 0x00, 0xff, 0x0c, 0x00, 0x00, 0xff, 0x10, 0x00, 0x00, 0xff, 0x18, 0x00, 0x00, 0xff, 0x1c, 0x00, 0x00, 0xff, 0x20, ++0xe1, 0xa0, 0x00, 0x00, 0xea, 0x00, 0x0b, 0xd5, 0xe5, 0x9f, 0x30, 0x04, 0xe0, 0x8f, 0x30, 0x03, 0xe1, 0xa0, 0xf0, 0x03, 0x00, 0x00, 0x35, 0xcc, 0xe9, 0x2d, 0x40, 0x10, 0xe1, 0xa0, 0x40, 0x00, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x84, 0x02, 0xa0, ++0xe1, 0xa0, 0x00, 0x00, 0xe1, 0xa0, 0x00, 0x04, 0xeb, 0x00, 0x08, 0xb5, 0xe5, 0x94, 0x02, 0xec, 0xe3, 0x50, 0x00, 0x03, 0x0a, 0x00, 0x00, 0x02, 0xe5, 0x94, 0x02, 0xa0, 0xe3, 0x50, 0x00, 0x00, 0x1a, 0xff, 0xff, 0xf7, 0xe8, 0xbd, 0x80, 0x10, ++0xe9, 0x2d, 0x40, 0x10, 0xe1, 0xa0, 0x40, 0x00, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x84, 0x02, 0xa0, 0xe5, 0x84, 0x03, 0x74, 0xe1, 0xa0, 0x00, 0x00, 0xe1, 0xa0, 0x00, 0x04, 0xeb, 0xff, 0xff, 0xe9, 0xe5, 0x94, 0x03, 0x78, 0xe3, 0x50, 0x00, 0x00, ++0x0a, 0xff, 0xff, 0xfa, 0xe5, 0x94, 0x03, 0x7c, 0xe3, 0x50, 0x00, 0x00, 0x0a, 0xff, 0xff, 0xf7, 0xe3, 0xa0, 0x00, 0x01, 0xe8, 0xbd, 0x80, 0x10, 0xe9, 0x2d, 0x40, 0x70, 0xe1, 0xa0, 0x40, 0x00, 0xe3, 0xa0, 0x50, 0x00, 0xe1, 0xa0, 0x00, 0x04, ++0xeb, 0xff, 0xff, 0xea, 0xe1, 0xa0, 0x60, 0x00, 0xe8, 0xbd, 0x80, 0x70, 0xe9, 0x2d, 0x40, 0x30, 0xe2, 0x4d, 0xdf, 0x41, 0xe1, 0xa0, 0x40, 0x00, 0xe3, 0xa0, 0x2c, 0x01, 0xe5, 0x9f, 0x13, 0x38, 0xe0, 0x8f, 0x10, 0x01, 0xe2, 0x8d, 0x00, 0x04, ++0xeb, 0x00, 0x0b, 0x85, 0xe3, 0xa0, 0x00, 0x01, 0xe5, 0x84, 0x00, 0x18, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x84, 0x00, 0x10, 0xe5, 0x84, 0x00, 0x0c, 0xe5, 0x84, 0x00, 0x1c, 0xe5, 0x84, 0x00, 0x14, 0xe5, 0x84, 0x02, 0x14, 0xe5, 0x84, 0x03, 0x08, ++0xe5, 0x84, 0x03, 0x0c, 0xe5, 0x84, 0x00, 0x24, 0xe5, 0x84, 0x00, 0x28, 0xe5, 0x84, 0x00, 0x2c, 0xe3, 0xa0, 0x50, 0x00, 0xea, 0x00, 0x00, 0x05, 0xe3, 0xe0, 0x01, 0x02, 0xe2, 0x84, 0x10, 0x30, 0xe7, 0x81, 0x01, 0x05, 0xe2, 0x84, 0x10, 0x80, ++0xe7, 0x81, 0x01, 0x05, 0xe2, 0x85, 0x50, 0x01, 0xe3, 0x55, 0x00, 0x14, 0xba, 0xff, 0xff, 0xf7, 0xe3, 0xe0, 0x00, 0x00, 0xe5, 0x84, 0x00, 0x00, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x84, 0x00, 0x04, 0xe3, 0xa0, 0x00, 0x01, 0xe5, 0x84, 0x00, 0x08, ++0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x84, 0x00, 0x20, 0xe5, 0x84, 0x02, 0x98, 0xe5, 0x84, 0x02, 0x9c, 0xe5, 0x84, 0x02, 0xa0, 0xe5, 0x84, 0x02, 0xa4, 0xe5, 0x84, 0x02, 0xa8, 0xe5, 0x84, 0x02, 0xac, 0xe5, 0x84, 0x02, 0xb0, 0xe5, 0x84, 0x02, 0xb4, ++0xe5, 0x84, 0x02, 0xb8, 0xe5, 0x84, 0x02, 0xbc, 0xe5, 0x84, 0x02, 0xc0, 0xe5, 0x84, 0x02, 0xc4, 0xe5, 0x84, 0x02, 0xc8, 0xe5, 0x84, 0x02, 0xcc, 0xe5, 0x84, 0x02, 0xd0, 0xe5, 0x84, 0x02, 0xd4, 0xe5, 0x84, 0x02, 0xe8, 0xe5, 0x84, 0x02, 0xec, ++0xe5, 0x84, 0x02, 0xf0, 0xe5, 0x84, 0x02, 0xf4, 0xe5, 0x84, 0x02, 0xf8, 0xe5, 0x84, 0x02, 0xfc, 0xe5, 0x84, 0x03, 0x00, 0xe5, 0x84, 0x03, 0x04, 0xe5, 0x84, 0x03, 0x08, 0xe5, 0x84, 0x03, 0x0c, 0xe5, 0x84, 0x03, 0x10, 0xe5, 0x84, 0x03, 0x14, ++0xe5, 0x84, 0x03, 0x18, 0xe5, 0x84, 0x03, 0x1c, 0xe5, 0x84, 0x03, 0x20, 0xe5, 0x84, 0x03, 0x24, 0xe5, 0x84, 0x03, 0x28, 0xe5, 0x84, 0x03, 0x2c, 0xe5, 0x84, 0x03, 0x30, 0xe5, 0x84, 0x03, 0x34, 0xe5, 0x84, 0x03, 0x38, 0xe5, 0x84, 0x03, 0x3c, ++0xe5, 0x84, 0x03, 0x40, 0xe5, 0x84, 0x03, 0x44, 0xe5, 0x84, 0x03, 0x48, 0xe5, 0x84, 0x03, 0x4c, 0xe5, 0x84, 0x03, 0x50, 0xe5, 0x84, 0x03, 0x54, 0xe5, 0x84, 0x03, 0x58, 0xe5, 0x84, 0x03, 0x5c, 0xe5, 0x84, 0x03, 0x70, 0xe3, 0xa0, 0x50, 0x00, ++0xea, 0x00, 0x00, 0x04, 0xe2, 0x8d, 0x00, 0x04, 0xe7, 0x90, 0x01, 0x05, 0xe2, 0x84, 0x1e, 0x39, 0xe7, 0x81, 0x01, 0x05, 0xe2, 0x85, 0x50, 0x01, 0xe3, 0x55, 0x00, 0x40, 0xba, 0xff, 0xff, 0xf8, 0xe3, 0xa0, 0x50, 0x00, 0xea, 0x00, 0x00, 0x03, ++0xe3, 0xa0, 0x00, 0x10, 0xe2, 0x84, 0x1e, 0x49, 0xe7, 0x81, 0x01, 0x05, 0xe2, 0x85, 0x50, 0x01, 0xe3, 0x55, 0x00, 0x40, 0xba, 0xff, 0xff, 0xf9, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x84, 0x03, 0x60, 0xe5, 0x84, 0x01, 0x70, 0xe5, 0x84, 0x03, 0x64, ++0xe3, 0xe0, 0x00, 0x00, 0xe5, 0x84, 0x03, 0x68, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x84, 0x03, 0x6c, 0xe5, 0x84, 0x03, 0x70, 0xe5, 0x84, 0x03, 0x74, 0xe5, 0x84, 0x03, 0x78, 0xe5, 0x84, 0x03, 0x7c, 0xe5, 0x84, 0x03, 0x80, 0xe5, 0x84, 0x03, 0x84, ++0xe5, 0x84, 0x03, 0x88, 0xe3, 0xa0, 0x00, 0x01, 0xe5, 0x84, 0x03, 0x8c, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x84, 0x05, 0x90, 0xe2, 0x8d, 0xdf, 0x41, 0xe8, 0xbd, 0x80, 0x30, 0xe9, 0x2d, 0x40, 0x70, 0xe1, 0xa0, 0x40, 0x00, 0xe3, 0xa0, 0x00, 0x05, ++0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x30, 0xe3, 0xa0, 0x06, 0x05, 0xe5, 0x90, 0x06, 0x00, 0xe3, 0xa0, 0x18, 0x55, 0xe5, 0x81, 0x00, 0x00, 0xe3, 0xa0, 0x06, 0x05, 0xe5, 0x90, 0x01, 0x20, 0xe5, 0x81, 0x00, 0x18, 0xe3, 0xa0, 0x00, 0x05, ++0xe5, 0x81, 0x00, 0x1c, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x81, 0x00, 0x20, 0xe3, 0xa0, 0x06, 0x05, 0xe5, 0x90, 0x01, 0x24, 0xe5, 0x81, 0x00, 0x24, 0xe1, 0xa0, 0x00, 0x04, 0xeb, 0xff, 0xff, 0x6e, 0xe3, 0xa0, 0x00, 0x00, 0xe3, 0xa0, 0x16, 0x05, ++0xe5, 0x81, 0x01, 0x10, 0xe3, 0xa0, 0x00, 0x02, 0xe5, 0x81, 0x00, 0x08, 0xe3, 0xa0, 0x00, 0x01, 0xe5, 0x81, 0x00, 0x00, 0xe3, 0xa0, 0x0c, 0x01, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x08, 0xe3, 0xa0, 0x00, 0x01, 0xe5, 0x81, 0x00, 0x00, ++0xe3, 0xa0, 0x06, 0x05, 0xe5, 0x90, 0x00, 0x5c, 0xe1, 0xa0, 0x60, 0x00, 0xe3, 0x56, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x06, 0xe2, 0x66, 0x50, 0x08, 0xea, 0x00, 0x00, 0x02, 0xe3, 0xa0, 0x00, 0x08, 0xeb, 0x00, 0x09, 0x20, 0xe2, 0x45, 0x50, 0x01, ++0xe3, 0x55, 0x00, 0x00, 0x1a, 0xff, 0xff, 0xfa, 0xe1, 0xa0, 0x00, 0x04, 0xeb, 0x00, 0x04, 0xa6, 0xe3, 0xa0, 0x0c, 0x02, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x04, 0xe3, 0xa0, 0x00, 0x00, 0xe3, 0xa0, 0x16, 0x05, 0xe5, 0x81, 0x01, 0x10, ++0xe3, 0xa0, 0x00, 0x01, 0xe5, 0x81, 0x00, 0x04, 0xe8, 0xbd, 0x80, 0x70, 0xe9, 0x2d, 0x40, 0x70, 0xe5, 0x9f, 0x00, 0x78, 0xeb, 0x00, 0x0a, 0xcf, 0xe1, 0xa0, 0x40, 0x00, 0xe3, 0xa0, 0x00, 0x01, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0xd0, ++0xea, 0x00, 0x00, 0x04, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0xd8, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x00, 0xea, 0x00, 0x00, 0x00, 0xea, 0xff, 0xff, 0xf9, 0xe1, 0xa0, 0x00, 0x00, 0xea, 0x00, 0x00, 0x04, 0xe3, 0xa0, 0x06, 0x05, ++0xe5, 0x90, 0x01, 0x2c, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x00, 0xea, 0x00, 0x00, 0x00, 0xea, 0xff, 0xff, 0xf9, 0xe1, 0xa0, 0x00, 0x00, 0xe1, 0xa0, 0x00, 0x04, 0xeb, 0xff, 0xff, 0xae, 0xe1, 0xa0, 0x00, 0x04, 0xeb, 0xff, 0xff, 0x29, ++0xe1, 0xa0, 0x50, 0x00, 0xe3, 0xa0, 0x00, 0x01, 0xe3, 0xa0, 0x16, 0x05, 0xe5, 0x81, 0x04, 0x08, 0xe8, 0xbd, 0x80, 0x70, 0x00, 0x00, 0x35, 0x30, 0x00, 0x00, 0x05, 0x98, 0xe5, 0x90, 0x12, 0xd4, 0xe3, 0x51, 0x00, 0x03, 0x0a, 0x00, 0x00, 0x18, ++0xe5, 0x90, 0x12, 0xd0, 0xe5, 0x90, 0x23, 0x84, 0xe1, 0x51, 0x00, 0x02, 0x0a, 0x00, 0x00, 0x14, 0xe5, 0x90, 0x13, 0x80, 0xe3, 0x51, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x04, 0xe5, 0x90, 0x13, 0x64, 0xe2, 0x81, 0x1b, 0x01, 0xe5, 0x80, 0x13, 0x64, ++0xe3, 0xa0, 0x10, 0x00, 0xe5, 0x80, 0x13, 0x80, 0xe5, 0x90, 0x12, 0xd0, 0xe5, 0x90, 0x23, 0x84, 0xe1, 0x51, 0x00, 0x02, 0xaa, 0x00, 0x00, 0x04, 0xe5, 0x90, 0x13, 0x6c, 0xe3, 0x51, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0x10, 0x01, ++0xe5, 0x80, 0x13, 0x80, 0xe5, 0x90, 0x12, 0xd0, 0xe5, 0x80, 0x13, 0x84, 0xe3, 0xa0, 0x10, 0x00, 0xe5, 0x80, 0x13, 0x6c, 0xe5, 0x90, 0x13, 0x64, 0xe5, 0x90, 0x22, 0xd0, 0xe0, 0x81, 0x10, 0x02, 0xe5, 0x80, 0x13, 0x30, 0xe5, 0x90, 0x13, 0x80, ++0xe3, 0x51, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x06, 0xe5, 0x90, 0x12, 0xd0, 0xe5, 0x90, 0x23, 0x84, 0xe1, 0x51, 0x00, 0x02, 0xca, 0x00, 0x00, 0x02, 0xe5, 0x90, 0x13, 0x30, 0xe2, 0x81, 0x1b, 0x01, 0xe5, 0x80, 0x13, 0x30, 0xe5, 0x90, 0x13, 0x30, ++0xe5, 0x90, 0x23, 0x68, 0xe1, 0x51, 0x00, 0x02, 0xda, 0x00, 0x00, 0x01, 0xe5, 0x90, 0x13, 0x30, 0xea, 0x00, 0x00, 0x00, 0xe5, 0x90, 0x13, 0x68, 0xe5, 0x80, 0x13, 0x68, 0xe1, 0x2f, 0xff, 0x1e, 0xe9, 0x2d, 0x40, 0x10, 0xeb, 0x00, 0x08, 0xe0, ++0xe8, 0xbd, 0x80, 0x10, 0xe9, 0x2d, 0x40, 0x10, 0xe3, 0xa0, 0x00, 0x01, 0xeb, 0x00, 0x08, 0xb7, 0xe3, 0xa0, 0x00, 0x08, 0xeb, 0x00, 0x08, 0xb5, 0xe3, 0xa0, 0x00, 0x01, 0xeb, 0x00, 0x08, 0xb3, 0xe3, 0xa0, 0x00, 0x07, 0xeb, 0x00, 0x08, 0xb1, ++0xe3, 0xa0, 0x00, 0x01, 0xeb, 0x00, 0x08, 0xaf, 0xe3, 0xa0, 0x00, 0x14, 0xeb, 0x00, 0x08, 0xad, 0xe3, 0xa0, 0x00, 0x01, 0xeb, 0x00, 0x08, 0xab, 0xe3, 0xa0, 0x00, 0x16, 0xeb, 0x00, 0x08, 0xa9, 0xe3, 0xa0, 0x00, 0x01, 0xeb, 0x00, 0x08, 0xa7, ++0xe3, 0xa0, 0x00, 0x16, 0xeb, 0x00, 0x08, 0xa5, 0xe8, 0xbd, 0x80, 0x10, 0xe9, 0x2d, 0x40, 0x10, 0xe1, 0xa0, 0x40, 0x00, 0xe3, 0xa0, 0x00, 0x04, 0xeb, 0x00, 0x08, 0xa0, 0xe5, 0x84, 0x02, 0xd8, 0xe3, 0xa0, 0x00, 0x04, 0xeb, 0x00, 0x08, 0x9d, ++0xe5, 0x84, 0x02, 0xdc, 0xe3, 0xa0, 0x00, 0x04, 0xeb, 0x00, 0x08, 0x9a, 0xe5, 0x84, 0x02, 0xe0, 0xe3, 0xa0, 0x00, 0x04, 0xeb, 0x00, 0x08, 0x97, 0xe5, 0x84, 0x02, 0xe4, 0xe3, 0xa0, 0x00, 0x02, 0xeb, 0x00, 0x08, 0x94, 0xe5, 0x84, 0x02, 0xe8, ++0xe3, 0xa0, 0x00, 0x02, 0xeb, 0x00, 0x08, 0x91, 0xe5, 0x84, 0x02, 0xec, 0xe3, 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0x10, 0x24, ++0xe2, 0x81, 0x10, 0x01, 0xe5, 0x90, 0x31, 0x70, 0xe1, 0x53, 0x00, 0x01, 0x8a, 0xff, 0xff, 0xf5, 0xe5, 0x90, 0x33, 0x70, 0xe3, 0x53, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x01, 0xe3, 0xe0, 0x30, 0x00, 0xe5, 0x80, 0x30, 0x24, 0xe5, 0x90, 0x30, 0x24, ++0xe2, 0x80, 0xcf, 0x5d, 0xe7, 0x9c, 0x31, 0x03, 0xe3, 0xa0, 0xc6, 0x05, 0xe5, 0x8c, 0x34, 0x00, 0xe5, 0x90, 0x30, 0x24, 0xe2, 0x80, 0xcf, 0x71, 0xe7, 0x9c, 0x31, 0x03, 0xe3, 0xa0, 0xc6, 0x05, 0xe5, 0x8c, 0x34, 0x04, 0xe3, 0xa0, 0x10, 0x00, ++0xea, 0x00, 0x00, 0x05, 0xe2, 0x80, 0x3e, 0x12, 0xe2, 0x81, 0xc0, 0x01, 0xe7, 0x93, 0x31, 0x0c, 0xe2, 0x80, 0xce, 0x12, 0xe7, 0x8c, 0x31, 0x01, 0xe2, 0x81, 0x10, 0x01, 0xe3, 0x51, 0x00, 0x13, 0xba, 0xff, 0xff, 0xf7, 0xe3, 0xa0, 0x10, 0x00, ++0xea, 0x00, 0x00, 0x11, 0xe2, 0x80, 0x3e, 0x12, 0xe7, 0x93, 0x31, 0x01, 0xe3, 0x73, 0x01, 0x06, 0x0a, 0x00, 0x00, 0x08, 0xe2, 0x80, 0x3e, 0x12, 0xe7, 0x93, 0x31, 0x01, 0xe5, 0x90, 0xc0, 0x24, 0xe1, 0x53, 0x00, 0x0c, 0x0a, 0x00, 0x00, 0x03, ++0xe2, 0x80, 0x3e, 0x12, 0xe7, 0x93, 0x31, 0x01, 0xe3, 0x73, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x03, 0xe5, 0x90, 0x30, 0x24, 0xe2, 0x80, 0xce, 0x12, 0xe7, 0x8c, 0x31, 0x01, 0xea, 0x00, 0x00, 0x02, 0xe2, 0x81, 0x10, 0x01, 0xe3, 0x51, 0x00, 0x13, ++0xba, 0xff, 0xff, 0xeb, 0xe1, 0xa0, 0x00, 0x00, 0xe1, 0x2f, 0xff, 0x1e, 0xe9, 0x2d, 0x40, 0x10, 0xe3, 0xa0, 0x00, 0x05, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x30, 0xeb, 0xff, 0xf5, 0x6e, 0xe3, 0xa0, 0x00, 0x01, 0xe3, 0xa0, 0x16, 0x05, ++0xe5, 0x81, 0x05, 0x10, 0xe1, 0xa0, 0x00, 0x00, 0xea, 0xff, 0xff, 0xfe, 0xe1, 0xa0, 0xf0, 0x0e, 0xe1, 0xa0, 0xf0, 0x0e, 0xe9, 0x2d, 0x40, 0x10, 0xe1, 0xa0, 0x40, 0x00, 0xe1, 0xa0, 0x00, 0x01, 0xe2, 0x4d, 0xd0, 0x08, 0xe2, 0x8d, 0x10, 0x04, ++0xeb, 0x00, 0x00, 0xbe, 0xe3, 0x50, 0x00, 0x00, 0x02, 0x8d, 0xd0, 0x08, 0x08, 0xbd, 0x80, 0x10, 0xe1, 0xa0, 0x20, 0x00, 0xe5, 0x9d, 0x10, 0x04, 0xe1, 0xa0, 0x00, 0x04, 0xeb, 0x00, 0x00, 0xa1, 0xe2, 0x8d, 0xd0, 0x08, 0xe3, 0xa0, 0x00, 0x01, ++0xe8, 0xbd, 0x80, 0x10, 0xe3, 0xa0, 0x10, 0x01, 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0x00, 0x03, 0xeb, 0x00, 0x01, 0x27, 0xe8, 0xbd, 0x00, 0x03, 0xeb, 0x00, 0x00, 0xe2, 0xe9, 0x2d, 0x00, 0x0f, 0xeb, 0x00, 0x01, 0x26, ++0xe8, 0xbd, 0x00, 0x0f, 0xeb, 0xff, 0xff, 0x88, 0xea, 0x00, 0x00, 0x7c, 0xe9, 0x2d, 0x40, 0x01, 0xeb, 0x00, 0x01, 0x24, 0xeb, 0x00, 0x01, 0x16, 0xe8, 0xbd, 0x40, 0x01, 0xea, 0x00, 0x00, 0x00, 0xe3, 0xe0, 0x00, 0x00, 0xea, 0x00, 0x00, 0x54, ++0xe9, 0x2d, 0x40, 0x10, 0xeb, 0x00, 0x00, 0x81, 0xe3, 0x50, 0x00, 0x00, 0x08, 0xbd, 0x80, 0x10, 0xe8, 0xbd, 0x40, 0x10, 0xea, 0x00, 0x00, 0x4e, 0xe1, 0xa0, 0xf0, 0x0e, 0xe1, 0xa0, 0xf0, 0x0e, 0xe3, 0xa0, 0x10, 0x00, 0xe5, 0x80, 0x10, 0x00, ++0xe5, 0x80, 0x10, 0x04, 0xe5, 0x80, 0x00, 0x08, 0xe1, 0xa0, 0xf0, 0x0e, 0xe3, 0xa0, 0x00, 0x10, 0xe1, 0xa0, 0xf0, 0x0e, 0xe9, 0x2d, 0x40, 0x70, 0xe1, 0xa0, 0x50, 0x00, 0xe2, 0x81, 0x00, 0x04, 0xe3, 0x50, 0x00, 0x08, 0x33, 0xa0, 0x00, 0x08, ++0xe2, 0x80, 0x00, 0x07, 0xe3, 0xc0, 0x40, 0x07, 0xe2, 0x41, 0x00, 0x01, 0xe1, 0x54, 0x00, 0x00, 0x9a, 0x00, 0x00, 0x1f, 0xe5, 0x95, 0x00, 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0x11, 0x53, 0x00, 0x01, 0x3a, 0xff, 0xff, 0xfa, 0xe5, 0x9c, 0x30, 0x00, ++0xe0, 0x83, 0x30, 0x0c, 0xe1, 0x53, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x05, 0xe1, 0xa0, 0x30, 0x01, 0xe2, 0x81, 0x10, 0x03, 0xe3, 0xc1, 0x10, 0x07, 0xe2, 0x81, 0x10, 0x04, 0xe0, 0x41, 0x30, 0x03, 0xe0, 0x42, 0x20, 0x03, 0xe4, 0x81, 0x20, 0x04, ++0xeb, 0x00, 0x00, 0x09, 0xe8, 0xbd, 0x80, 0x10, 0xe9, 0x2d, 0x40, 0x10, 0xeb, 0x00, 0x00, 0x67, 0xe8, 0xbd, 0x80, 0x10, 0xe5, 0x9f, 0x10, 0x0c, 0xe3, 0xa0, 0x00, 0x18, 0xef, 0x12, 0x34, 0x56, 0xe1, 0xa0, 0xf0, 0x0e, 0x00, 0x00, 0x03, 0x20, ++0x00, 0x02, 0x00, 0x26, 0xe2, 0x41, 0x10, 0x04, 0xe1, 0xa0, 0x20, 0x00, 0xe5, 0x90, 0x00, 0x04, 0xe3, 0x50, 0x00, 0x00, 0x11, 0x50, 0x00, 0x01, 0x3a, 0xff, 0xff, 0xfa, 0xe5, 0x92, 0x30, 0x00, 0xe0, 0x83, 0xc0, 0x02, 0xe1, 0x5c, 0x00, 0x01, ++0x15, 0x82, 0x10, 0x04, 0x1a, 0x00, 0x00, 0x03, 0xe5, 0x91, 0x10, 0x00, 0xe0, 0x83, 0x10, 0x01, 0xe5, 0x82, 0x10, 0x00, 0xe1, 0xa0, 0x10, 0x02, 0xe5, 0x91, 0x20, 0x00, 0xe0, 0x82, 0x30, 0x01, 0xe1, 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linux-2.6.28.6/drivers/media/video/samsung/mfc40/mp4_dec_fw.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,670 @@ ++/* ++ * drivers/media/video/samsung/mfc40/mp4_dec_fw.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++ ++const unsigned char mp4_dec_mc_fw[26148] = { ++0xea, 0x00, 0x00, 0x31, 0xea, 0x00, 0x00, 0x06, 0xea, 0x00, 0x00, 0x0b, 0xea, 0x00, 0x00, 0x10, 0xea, 0x00, 0x00, 0x15, 0xea, 0xff, 0xff, 0xfe, 0xea, 0x00, 0x00, 0x19, 0xea, 0x00, 0x00, 0x1e, 0xea, 0x00, 0x00, 0x23, 0xe2, 0x4d, 0xd0, 0x04, ++0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 0xa0, 0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x04, 0xe8, 0xbd, 0x80, 0x01, 0xe2, 0x4d, 0xd0, 0x04, 0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 0x8c, 0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x04, ++0xe8, 0xbd, 0x80, 0x01, 0xe2, 0x4d, 0xd0, 0x04, 0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 0x78, 0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x04, 0xe8, 0xbd, 0x80, 0x01, 0xe2, 0x4d, 0xd0, 0x04, 0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 0x64, ++0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x04, 0xe8, 0xbd, 0x80, 0x01, 0xe2, 0x4d, 0xd0, 0x04, 0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 0x50, 0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x04, 0xe8, 0xbd, 0x80, 0x01, 0xe2, 0x4d, 0xd0, 0x04, ++0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 0x3c, 0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x04, 0xe8, 0xbd, 0x80, 0x01, 0xe2, 0x4d, 0xd0, 0x04, 0xe9, 0x2d, 0x00, 0x01, 0xe5, 0x9f, 0x00, 0x28, 0xe5, 0x90, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x04, ++0xe8, 0xbd, 0x80, 0x01, 0xeb, 0x00, 0x00, 0x07, 0xea, 0xff, 0xff, 0xfe, 0x00, 0x01, 0x3f, 0x04, 0x00, 0x01, 0x3f, 0x08, 0x00, 0x01, 0x3f, 0x0c, 0x00, 0x01, 0x3f, 0x10, 0x00, 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0x2d, 0x4f, 0xff, 0xe2, 0x4d, 0xd0, 0x04, 0xe5, 0x9d, 0x20, 0x04, 0xe5, 0x92, 0x71, 0x9c, 0xe5, 0x9d, 0x20, 0x04, 0xe3, 0xe0, 0x11, 0x02, 0xe5, 0x92, 0x02, 0xa8, 0xe0, 0x01, 0x80, 0xc0, ++0xe5, 0x9d, 0x20, 0x04, 0xe5, 0x92, 0x02, 0xa8, 0xe2, 0x00, 0x50, 0x01, 0xe5, 0x9d, 0x20, 0x04, 0xe5, 0x92, 0x02, 0xac, 0xe0, 0x01, 0xb0, 0xc0, 0xe5, 0x9d, 0x20, 0x04, 0xe5, 0x92, 0x02, 0xac, 0xe2, 0x00, 0x60, 0x01, 0xe5, 0x9d, 0x20, 0x04, ++0xe5, 0x92, 0x02, 0xa4, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x03, 0xe5, 0x9d, 0x20, 0x08, 0xe0, 0x42, 0x00, 0x08, 0xe5, 0x9d, 0x20, 0x04, 0xe5, 0x82, 0x02, 0xb0, 0xe5, 0x9d, 0x20, 0x04, 0xe5, 0x92, 0x02, 0xb0, 0xe1, 0xa0, 0x40, 0xc0, ++0xe5, 0x9d, 0x20, 0x04, 0xe5, 0x92, 0x12, 0xb0, 0xe5, 0x9d, 0x20, 0x08, 0xe0, 0x42, 0x20, 0x08, 0xe0, 0x82, 0x00, 0x04, 0xeb, 0x00, 0x0b, 0x9f, 0xe1, 0xa0, 0x90, 0x00, 0xe5, 0x9d, 0x20, 0x04, 0xe5, 0x92, 0x12, 0xb0, 0xe0, 0x4b, 0x20, 0x08, ++0xe0, 0x82, 0x00, 0x04, 0xeb, 0x00, 0x0b, 0x99, 0xe1, 0xa0, 0xa0, 0x00, 0xe2, 0x09, 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0x93, 0x31, 0x02, 0xe3, 0xa0, 0xc8, 0x55, 0xe5, 0x8c, 0x30, 0x28, ++0xe2, 0x80, 0x3f, 0x8f, 0xe7, 0x93, 0x31, 0x02, 0xe5, 0x8c, 0x30, 0x2c, 0xe5, 0x90, 0x30, 0x24, 0xe3, 0x53, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x12, 0xe5, 0x90, 0x30, 0x20, 0xe2, 0x80, 0xc0, 0xcc, 0xe7, 0x9c, 0x31, 0x03, 0xe2, 0x43, 0x30, 0x01, ++0xe5, 0x90, 0xc0, 0x20, 0xe2, 0x80, 0xe0, 0xcc, 0xe7, 0x8e, 0x31, 0x0c, 0xe5, 0x90, 0x30, 0x20, 0xe2, 0x80, 0xc0, 0xcc, 0xe7, 0x9c, 0x31, 0x03, 0xe3, 0x53, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x06, 0xe3, 0xe0, 0x31, 0x02, 0xe5, 0x90, 0xc0, 0x20, ++0xe2, 0x80, 0xe0, 0x7c, 0xe7, 0x8e, 0x31, 0x0c, 0xe5, 0x90, 0xc0, 0x20, 0xe2, 0x80, 0xe0, 0x2c, 0xe7, 0x8e, 0x31, 0x0c, 0xe5, 0x90, 0x30, 0x28, 0xe3, 0x53, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x0d, 0xe3, 0xa0, 0x30, 0x00, 0xe5, 0x80, 0x30, 0x28, ++0xe3, 0xa0, 0x20, 0x00, 0xea, 0x00, 0x00, 0x06, 0xe2, 0x80, 0x30, 0x7c, 0xe7, 0x93, 0x31, 0x02, 0xe3, 0x73, 0x01, 0x06, 0x0a, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0x30, 0x01, 0xe5, 0x80, 0x30, 0x28, 0xe2, 0x82, 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0x08, ++0xe3, 0xa0, 0xe0, 0x0b, 0xe0, 0x8e, 0xc0, 0x81, 0xe1, 0x5c, 0x00, 0x02, 0xca, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0x00, 0x01, 0xea, 0x00, 0x00, 0x02, 0xe3, 0xa0, 0x00, 0x00, 0xea, 0x00, 0x00, 0x00, 0xe3, 0xa0, 0x00, 0x01, 0xe4, 0x9d, 0xf0, 0x04, ++0xe9, 0x2d, 0x4f, 0xff, 0xe2, 0x4d, 0xd0, 0x3c, 0xe5, 0x9f, 0x1f, 0x94, 0xe0, 0x8f, 0x10, 0x01, 0xe2, 0x8d, 0x00, 0x2c, 0xe8, 0x91, 0x00, 0x3c, 0xe8, 0x80, 0x00, 0x3c, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x28, 0xe5, 0x9d, 0x00, 0x44, ++0xe5, 0x8d, 0x00, 0x0c, 0xe3, 0xa0, 0x50, 0x01, 0xe1, 0xa0, 0x00, 0x00, 0xe1, 0xa0, 0x00, 0x00, 0xe3, 0xa0, 0x60, 0x00, 0xe5, 0x9d, 0x10, 0x0c, 0xe5, 0x8d, 0x10, 0x08, 0xe3, 0xa0, 0x00, 0x00, 0xeb, 0xff, 0xf9, 0xa4, 0xe5, 0x8d, 0x00, 0x20, ++0xe3, 0xa0, 0x00, 0x07, 0xe5, 0x9d, 0x10, 0x20, 0xe0, 0x00, 0x42, 0x41, 0xe3, 0x74, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x02, 0xe3, 0xa0, 0x00, 0x01, 0xe2, 0x8d, 0xd0, 0x4c, 0xe8, 0xbd, 0x8f, 0xf0, 0xe3, 0x54, 0x00, 0x07, 0x0a, 0x00, 0x00, 0x8f, ++0xe3, 0x54, 0x00, 0x04, 0x1a, 0x00, 0x00, 0x1e, 0xe3, 0xa0, 0x00, 0x02, 0xeb, 0xff, 0xf1, 0x9a, 0xe1, 0xa0, 0x60, 0x00, 0xe2, 0x8d, 0x00, 0x2c, 0xe7, 0x90, 0x01, 0x06, 0xe5, 0x9d, 0x10, 0x0c, 0xe0, 0x80, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x0c, ++0xe5, 0x9d, 0x10, 0x0c, 0xe3, 0x51, 0x00, 0x1f, 0xca, 0x00, 0x00, 0x02, 0xe5, 0x9d, 0x10, 0x0c, 0xe3, 0x51, 0x00, 0x01, 0xaa, 0x00, 0x00, 0x10, 0xe5, 0x9d, 0x10, 0x0c, 0xe3, 0x51, 0x00, 0x1f, 0xda, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0x00, 0x1f, ++0xea, 0x00, 0x00, 0x00, 0xe5, 0x9d, 0x00, 0x0c, 0xe3, 0x50, 0x00, 0x01, 0xaa, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0x00, 0x01, 0xea, 0x00, 0x00, 0x05, 0xe5, 0x9d, 0x10, 0x0c, 0xe3, 0x51, 0x00, 0x1f, 0xda, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0x00, 0x1f, ++0xea, 0x00, 0x00, 0x00, 0xe5, 0x9d, 0x00, 0x0c, 0xe5, 0x8d, 0x00, 0x0c, 0xe3, 0x55, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x01, 0xe5, 0x9d, 0x10, 0x0c, 0xe5, 0x8d, 0x10, 0x08, 0xe1, 0xa0, 0x00, 0x04, 0xe5, 0x9d, 0x10, 0x40, 0xe5, 0x9d, 0x20, 0x08, ++0xeb, 0xff, 0xff, 0xa0, 0xe5, 0x8d, 0x00, 0x04, 0xe5, 0x9d, 0x10, 0x70, 0xe5, 0x91, 0x00, 0x00, 0xe3, 0xa0, 0x10, 0x03, 0xeb, 0x00, 0x05, 0x4b, 0xe5, 0x8d, 0x10, 0x24, 0xe3, 0xa0, 0x00, 0x0a, 0xe5, 0x9d, 0x20, 0x24, 0xe0, 0x02, 0x02, 0x90, ++0xe5, 0x8d, 0x20, 0x18, 0xe5, 0x9d, 0x20, 0x18, 0xe2, 0x82, 0x00, 0x08, 0xe5, 0x8d, 0x00, 0x14, 0xe5, 0x9d, 0x20, 0x24, 0xe3, 0x52, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x02, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x9d, 0x20, 0x3c, 0xe5, 0x82, 0x04, 0x8c, ++0xe5, 0x9d, 0x00, 0x14, 0xe1, 0xa0, 0x00, 0x16, 0xe5, 0x9d, 0x10, 0x20, 0xe5, 0x9d, 0x20, 0x18, 0xe1, 0x80, 0x02, 0x11, 0xe5, 0x9d, 0x20, 0x3c, 0xe5, 0x92, 0x14, 0x8c, 0xe1, 0x80, 0x00, 0x01, 0xe5, 0x82, 0x04, 0x8c, 0xe5, 0x9d, 0x10, 0x70, ++0xe5, 0x91, 0x00, 0x00, 0xe3, 0xa0, 0x10, 0x03, 0xeb, 0x00, 0x05, 0x30, 0xe3, 0xa0, 0x17, 0x16, 0xe5, 0x9d, 0x20, 0x3c, 0xe5, 0x92, 0x24, 0x8c, 0xe7, 0x81, 0x21, 0x00, 0xe5, 0x9d, 0x10, 0x70, 0xe5, 0x91, 0x00, 0x00, 0xe1, 0xa0, 0x02, 0xc0, ++0xe5, 0x8d, 0x00, 0x24, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x9d, 0x20, 0x3c, 0xe2, 0x82, 0x1f, 0xaf, 0xe5, 0x9d, 0x20, 0x24, 0xe7, 0x81, 0x01, 0x02, 0xe5, 0x9d, 0x00, 0x04, 0xe3, 0x50, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x36, 0xe3, 0xa0, 0x30, 0x00, ++0xe5, 0x8d, 0x30, 0x00, 0xe3, 0xa0, 0x30, 0x01, 0xe3, 0xa0, 0x20, 0x00, 0xe3, 0xa0, 0x10, 0x01, 0xe3, 0xa0, 0x00, 0x00, 0xeb, 0xff, 0xf9, 0x27, 0xe5, 0x9d, 0x10, 0x70, 0xe5, 0x91, 0x00, 0x00, 0xe3, 0x50, 0x00, 0x7e, 0xda, 0x00, 0x00, 0x17, ++0xe5, 0x9d, 0x10, 0x70, 0xe5, 0x91, 0x00, 0x00, 0xe2, 0x40, 0x10, 0x7f, 0xe5, 0x8d, 0x10, 0x1c, 0xe5, 0x9d, 0x10, 0x1c, 0xe0, 0x81, 0x00, 0x81, 0xe5, 0x8d, 0x00, 0x20, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x64, 0xe3, 0xa0, 0x18, 0x57, ++0xe5, 0x9d, 0x20, 0x20, 0xe7, 0x81, 0x01, 0x02, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x68, 0xe5, 0x9d, 0x20, 0x20, 0xe0, 0x81, 0x11, 0x02, 0xe5, 0x81, 0x00, 0x04, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x6c, 0xe3, 0xa0, 0x18, 0x57, ++0xe5, 0x9d, 0x20, 0x20, 0xe0, 0x81, 0x11, 0x02, 0xe5, 0x81, 0x00, 0x08, 0xea, 0x00, 0x00, 0x13, 0xe5, 0x9d, 0x10, 0x70, 0xe5, 0x91, 0x00, 0x00, 0xe0, 0x80, 0x00, 0x80, 0xe5, 0x8d, 0x00, 0x20, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x64, ++0xe5, 0x9d, 0x20, 0x20, 0xe5, 0x9f, 0x1d, 0x1c, 0xe7, 0x81, 0x01, 0x02, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x68, 0xe5, 0x9d, 0x20, 0x20, 0xe0, 0x81, 0x11, 0x02, 0xe5, 0x81, 0x00, 0x04, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x6c, ++0xe5, 0x9d, 0x20, 0x20, 0xe5, 0x9f, 0x1c, 0xf4, 0xe0, 0x81, 0x11, 0x02, 0xe5, 0x81, 0x00, 0x08, 0xe3, 0x54, 0x00, 0x07, 0x1a, 0x00, 0x00, 0x04, 0xe3, 0xa0, 0x00, 0x13, 0xeb, 0xff, 0xf0, 0xfd, 0xe2, 0x40, 0xca, 0x6b, 0xe2, 0x5c, 0xc0, 0x01, ++0x1a, 0xff, 0xff, 0x58, 0xe3, 0xa0, 0x50, 0x00, 0xe3, 0x54, 0x00, 0x07, 0x1a, 0x00, 0x00, 0x00, 0xea, 0x00, 0x00, 0x10, 0xe5, 0x9d, 0x10, 0x28, 0xe2, 0x81, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x28, 0xe5, 0x9d, 0x10, 0x70, 0xe5, 0x91, 0x00, 0x00, ++0xe2, 0x80, 0x00, 0x01, 0xe5, 0x81, 0x00, 0x00, 0xe3, 0xa0, 0x00, 0x13, 0xeb, 0xff, 0xf0, 0xed, 0xe2, 0x40, 0xca, 0x6b, 0xe2, 0x5c, 0xc0, 0x01, 0x0a, 0x00, 0x00, 0x04, 0xe5, 0x9d, 0x10, 0x70, 0xe5, 0x91, 0x00, 0x00, 0xe5, 0x9d, 0x10, 0x48, ++0xe1, 0x50, 0x00, 0x01, 0xba, 0xff, 0xff, 0x42, 0xe1, 0xa0, 0x00, 0x00, 0xe5, 0x9d, 0x10, 0x70, 0xe5, 0x91, 0x00, 0x00, 0xe5, 0x9d, 0x10, 0x48, 0xe1, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x0b, 0xe3, 0xa0, 0x00, 0x13, 0xeb, 0xff, 0xf0, 0xdd, ++0xe2, 0x40, 0xca, 0x6b, 0xe2, 0x5c, 0xc0, 0x01, 0x0a, 0x00, 0x00, 0x06, 0xea, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0x00, 0x09, 0xeb, 0xff, 0xf0, 0xe4, 0xe3, 0xa0, 0x00, 0x09, 0xeb, 0xff, 0xf0, 0xd5, 0xe3, 0x50, 0x00, 0x01, 0x0a, 0xff, 0xff, 0xf9, ++0xe3, 0xa0, 0x00, 0x13, 0xeb, 0xff, 0xf0, 0xde, 0xe5, 0x8d, 0x00, 0x20, 0xe5, 0x9d, 0x10, 0x70, 0xe5, 0x91, 0x00, 0x00, 0xe5, 0x9d, 0x10, 0x28, 0xe0, 0x40, 0x10, 0x01, 0xe5, 0x8d, 0x10, 0x10, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x28, ++0xea, 0x00, 0x00, 0x2c, 0xe3, 0xa0, 0x00, 0x01, 0xeb, 0xff, 0xf0, 0xd3, 0xe1, 0xa0, 0x70, 0x00, 0xe3, 0xa0, 0x00, 0x02, 0xeb, 0xff, 0xf8, 0xcb, 0xe5, 0x8d, 0x00, 0x20, 0xe3, 0xa0, 0x10, 0x03, 0xe5, 0x9d, 0x00, 0x10, 0xeb, 0x00, 0x04, 0xa7, ++0xe5, 0x8d, 0x10, 0x24, 0xe3, 0xa0, 0x00, 0x0a, 0xe5, 0x9d, 0x20, 0x24, 0xe0, 0x00, 0x00, 0x92, 0xe5, 0x8d, 0x00, 0x18, 0xe5, 0x9d, 0x20, 0x18, 0xe2, 0x82, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x14, 0xe5, 0x9d, 0x20, 0x24, 0xe3, 0x52, 0x00, 0x00, ++0x1a, 0x00, 0x00, 0x02, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x9d, 0x20, 0x3c, 0xe5, 0x82, 0x04, 0x90, 0xe5, 0x9d, 0x00, 0x14, 0xe5, 0x9d, 0x10, 0x20, 0xe1, 0xa0, 0x00, 0x11, 0xe5, 0x9d, 0x20, 0x18, 0xe1, 0x80, 0x02, 0x17, 0xe5, 0x9d, 0x20, 0x3c, ++0xe5, 0x92, 0x14, 0x90, 0xe1, 0x80, 0x00, 0x01, 0xe5, 0x82, 0x04, 0x90, 0xe3, 0xa0, 0x10, 0x03, 0xe5, 0x9d, 0x00, 0x10, 0xeb, 0x00, 0x04, 0x8d, 0xe3, 0xa0, 0x18, 0x59, 0xe5, 0x9d, 0x20, 0x3c, 0xe5, 0x92, 0x24, 0x90, 0xe7, 0x81, 0x21, 0x00, ++0xe5, 0x9d, 0x10, 0x28, 0xe2, 0x81, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x28, 0xe5, 0x9d, 0x10, 0x10, 0xe2, 0x81, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x10, 0xe5, 0x9d, 0x10, 0x70, 0xe5, 0x91, 0x00, 0x00, 0xe5, 0x9d, 0x10, 0x10, 0xe1, 0x50, 0x00, 0x01, ++0xca, 0xff, 0xff, 0xcd, 0xe5, 0x9d, 0x10, 0x70, 0xe5, 0x91, 0x00, 0x00, 0xe5, 0x9d, 0x10, 0x28, 0xe0, 0x40, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x10, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x28, 0xe5, 0x9d, 0x00, 0x44, 0xe5, 0x8d, 0x00, 0x0c, ++0xe3, 0xa0, 0x50, 0x01, 0xea, 0x00, 0x00, 0xc9, 0xe5, 0x9d, 0x10, 0x0c, 0xe5, 0x8d, 0x10, 0x08, 0xe3, 0xa0, 0x10, 0x03, 0xe5, 0x9d, 0x00, 0x10, 0xeb, 0x00, 0x04, 0x6e, 0xe5, 0x8d, 0x10, 0x24, 0xe3, 0xa0, 0x10, 0x03, 0xe5, 0x9d, 0x00, 0x10, ++0xeb, 0x00, 0x04, 0x6a, 0xe3, 0xa0, 0x17, 0x16, 0xe7, 0x91, 0x81, 0x00, 0xe3, 0xa0, 0x10, 0x03, 0xe5, 0x9d, 0x00, 0x10, 0xeb, 0x00, 0x04, 0x65, 0xe3, 0xa0, 0x18, 0x59, 0xe7, 0x91, 0x91, 0x00, 0xe3, 0xa0, 0x10, 0x03, 0xe5, 0x9d, 0x00, 0x10, ++0xeb, 0x00, 0x04, 0x60, 0xe3, 0x51, 0x00, 0x02, 0x1a, 0x00, 0x00, 0x05, 0xe3, 0xa0, 0x10, 0x03, 0xe5, 0x9d, 0x00, 0x10, 0xeb, 0x00, 0x04, 0x5b, 0xe3, 0xa0, 0x17, 0x16, 0xe3, 0xa0, 0x20, 0x00, 0xe7, 0x81, 0x21, 0x00, 0xe3, 0xa0, 0x00, 0x0a, ++0xe5, 0x9d, 0x20, 0x24, 0xe0, 0x00, 0x00, 0x92, 0xe5, 0x8d, 0x00, 0x18, 0xe5, 0x9d, 0x20, 0x18, 0xe2, 0x82, 0x00, 0x08, 0xe5, 0x8d, 0x00, 0x14, 0xe5, 0x9d, 0x20, 0x18, 0xe1, 0xa0, 0x02, 0x58, 0xe2, 0x00, 0x00, 0xff, 0xe5, 0x8d, 0x00, 0x20, ++0xe5, 0x9d, 0x00, 0x14, 0xe1, 0xa0, 0x00, 0x58, 0xe2, 0x00, 0x60, 0x03, 0xe5, 0x9d, 0x20, 0x18, 0xe2, 0x82, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x14, 0xe5, 0x9d, 0x20, 0x18, 0xe1, 0xa0, 0x02, 0x59, 0xe2, 0x00, 0x70, 0x01, 0xe5, 0x9d, 0x00, 0x14, ++0xe1, 0xa0, 0x00, 0x59, 0xe2, 0x00, 0x00, 0x0f, 0xe5, 0x8d, 0x00, 0x1c, 0xe3, 0xa0, 0x00, 0x07, 0xe5, 0x9d, 0x10, 0x20, 0xe0, 0x00, 0x42, 0x41, 0xe5, 0x9d, 0x10, 0x20, 0xe2, 0x01, 0x00, 0x03, 0xe5, 0x9d, 0x10, 0x1c, 0xe1, 0x80, 0xa1, 0x01, ++0xe3, 0x54, 0x00, 0x04, 0x1a, 0x00, 0x00, 0x1b, 0xe2, 0x8d, 0x00, 0x2c, 0xe7, 0x90, 0x01, 0x06, 0xe5, 0x9d, 0x10, 0x0c, 0xe0, 0x80, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x0c, 0xe5, 0x9d, 0x10, 0x0c, 0xe3, 0x51, 0x00, 0x1f, 0xca, 0x00, 0x00, 0x02, ++0xe5, 0x9d, 0x10, 0x0c, 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0xff, 0xff, 0xf9, 0xe1, 0xa0, 0x00, 0x00, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x9d, 0x10, 0x10, 0xe5, 0x80, 0x10, 0x10, 0xe3, 0x84, 0x00, 0x40, 0xe3, 0xa0, 0x16, 0x02, 0xe5, 0x81, 0x00, 0x00, ++0xe5, 0x9d, 0x10, 0x0c, 0xe1, 0xa0, 0x07, 0x01, 0xe1, 0x80, 0x0a, 0x0a, 0xe3, 0xa0, 0x16, 0x02, 0xe5, 0x81, 0x00, 0x04, 0xe1, 0xa0, 0x0c, 0x07, 0xe5, 0x81, 0x00, 0x10, 0xe3, 0x5b, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x2e, 0xe5, 0x9d, 0x10, 0x10, ++0xe3, 0x51, 0x00, 0x7e, 0xda, 0x00, 0x00, 0x17, 0xe5, 0x9d, 0x10, 0x10, 0xe2, 0x41, 0x00, 0x7f, 0xe5, 0x8d, 0x00, 0x1c, 0xe5, 0x9d, 0x10, 0x1c, 0xe0, 0x81, 0x00, 0x81, 0xe5, 0x8d, 0x00, 0x20, 0xe3, 0xa0, 0x08, 0x57, 0xe5, 0x9d, 0x10, 0x20, ++0xe7, 0x90, 0x01, 0x01, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x64, 0xe3, 0xa0, 0x08, 0x57, 0xe5, 0x9d, 0x10, 0x20, 0xe0, 0x80, 0x01, 0x01, 0xe5, 0x90, 0x00, 0x04, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x68, 0xe3, 0xa0, 0x08, 0x57, ++0xe5, 0x9d, 0x10, 0x20, 0xe0, 0x80, 0x01, 0x01, 0xe5, 0x90, 0x00, 0x08, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x6c, 0xea, 0x00, 0x00, 0x13, 0xe5, 0x9d, 0x10, 0x10, 0xe0, 0x81, 0x00, 0x81, 0xe5, 0x8d, 0x00, 0x20, 0xe5, 0x9d, 0x10, 0x20, ++0xe5, 0x9f, 0x08, 0x98, 0xe7, 0x90, 0x01, 0x01, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x64, 0xe5, 0x9d, 0x10, 0x20, 0xe5, 0x9f, 0x08, 0x84, 0xe0, 0x80, 0x01, 0x01, 0xe5, 0x90, 0x00, 0x04, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x68, ++0xe5, 0x9d, 0x10, 0x20, 0xe5, 0x9f, 0x08, 0x6c, 0xe0, 0x80, 0x01, 0x01, 0xe5, 0x90, 0x00, 0x08, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x6c, 0xe3, 0xa0, 0x30, 0x00, 0xe1, 0xa0, 0x20, 0x0a, 0xe3, 0xa0, 0x10, 0x01, 0xe5, 0x8d, 0xb0, 0x00, ++0xe5, 0x9d, 0x00, 0x04, 0xeb, 0xff, 0xf7, 0xcd, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x90, 0xe3, 0x50, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x07, 0xe5, 0x9d, 0x10, 0x70, 0xe5, 0x91, 0x00, 0x00, 0xe5, 0x9d, 0x10, 0x28, 0xe0, 0x40, 0x00, 0x01, ++0xe5, 0x9d, 0x10, 0x70, 0xe5, 0x81, 0x00, 0x00, 0xe3, 0xa0, 0x00, 0x01, 0xea, 0xff, 0xfe, 0x35, 0xe3, 0xa0, 0x00, 0x01, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0xcc, 0xe3, 0xa0, 0x50, 0x00, 0xe5, 0x9d, 0x10, 0x28, 0xe2, 0x81, 0x00, 0x01, ++0xe5, 0x8d, 0x00, 0x28, 0xe5, 0x9d, 0x10, 0x10, 0xe2, 0x81, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x10, 0xe5, 0x9d, 0x10, 0x70, 0xe5, 0x91, 0x00, 0x00, 0xe5, 0x9d, 0x10, 0x10, 0xe1, 0x50, 0x00, 0x01, 0xca, 0xff, 0xff, 0x30, 0xe5, 0x9d, 0x10, 0x70, ++0xe5, 0x91, 0x00, 0x00, 0xe5, 0x9d, 0x10, 0x48, 0xe1, 0x50, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x0c, 0xea, 0x00, 0x00, 0x04, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0xd8, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x00, 0xea, 0x00, 0x00, 0x00, ++0xea, 0xff, 0xff, 0xf9, 0xe1, 0xa0, 0x00, 0x00, 0xe3, 0xa0, 0x00, 0x01, 0xe3, 0xa0, 0x16, 0x02, 0xe5, 0x81, 0x00, 0xa0, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0xcc, 0xe5, 0x9d, 0x10, 0x70, 0xe5, 0x91, 0x00, 0x00, 0xe5, 0x9d, 0x10, 0x10, ++0xe1, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0x00, 0x00, 0xea, 0xff, 0xfe, 0x0d, 0xe3, 0xa0, 0x00, 0x01, 0xea, 0xff, 0xfe, 0x0b, 0xe9, 0x2d, 0x4f, 0xff, 0xe2, 0x4d, 0xd0, 0x64, 0xe5, 0x9f, 0x17, 0x64, 0xe0, 0x8f, 0x10, 0x01, ++0xe2, 0x8d, 0x00, 0x54, 0xe8, 0x91, 0x00, 0x3c, 0xe8, 0x80, 0x00, 0x3c, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x08, 0xe5, 0x8d, 0x00, 0x50, 0xe1, 0xa0, 0x00, 0x00, 0xe1, 0xa0, 0x00, 0x00, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x48, ++0xe5, 0x8d, 0x00, 0x18, 0xe3, 0xa0, 0x00, 0x01, 0xeb, 0xff, 0xef, 0x9d, 0xe5, 0x8d, 0x00, 0x1c, 0xe5, 0x9d, 0x10, 0x1c, 0xe3, 0x51, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x0c, 0xe3, 0xa0, 0x00, 0x01, 0xeb, 0xff, 0xf7, 0x92, 0xe5, 0x8d, 0x00, 0x48, ++0xe3, 0xa0, 0x00, 0x07, 0xe5, 0x9d, 0x10, 0x48, 0xe0, 0x00, 0x02, 0x41, 0xe5, 0x8d, 0x00, 0x18, 0xe5, 0x9d, 0x10, 0x48, 0xe3, 0x71, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x02, 0xe3, 0xa0, 0x00, 0x01, 0xe2, 0x8d, 0xd0, 0x74, 0xe8, 0xbd, 0x8f, 0xf0, ++0xe5, 0x9d, 0x10, 0x1c, 0xe3, 0x51, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x07, 0xe5, 0x9d, 0x00, 0x18, 0xe3, 0x50, 0x00, 0x07, 0x1a, 0x00, 0x00, 0x04, 0xe3, 0xa0, 0x00, 0x11, 0xeb, 0xff, 0xef, 0x77, 0xe2, 0x40, 0xca, 0x1f, 0xe2, 0x5c, 0xc0, 0x01, ++0x1a, 0xff, 0xff, 0xde, 0xe5, 0x9d, 0x00, 0x18, 0xe3, 0x50, 0x00, 0x07, 0x1a, 0x00, 0x00, 0x00, 0xea, 0x00, 0x00, 0xba, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x10, 0xe5, 0x9d, 0x10, 0x1c, 0xe3, 0x51, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x5b, ++0xe5, 0x9d, 0x20, 0x64, 0xe5, 0x92, 0x01, 0x88, 0xe3, 0x50, 0x00, 0x02, 0x1a, 0x00, 0x00, 0x08, 0xe5, 0x9d, 0x00, 0x9c, 0xe3, 0x50, 0x00, 0x03, 0x1a, 0x00, 0x00, 0x05, 0xe5, 0x9d, 0x00, 0x18, 0xe3, 0x50, 0x00, 0x02, 0xaa, 0x00, 0x00, 0x02, ++0xe3, 0xa0, 0x00, 0x01, 0xeb, 0xff, 0xef, 0x6c, 0xe5, 0x8d, 0x00, 0x10, 0xe5, 0x9d, 0x20, 0x64, 0xe5, 0x92, 0x01, 0x88, 0xe3, 0x50, 0x00, 0x02, 0x1a, 0x00, 0x00, 0x05, 0xe5, 0x9d, 0x00, 0x9c, 0xe3, 0x50, 0x00, 0x03, 0x1a, 0x00, 0x00, 0x02, ++0xe5, 0x9d, 0x00, 0x10, 0xe3, 0x50, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x02, 0xe5, 0x9d, 0x00, 0x18, 0xe3, 0x50, 0x00, 0x02, 0xba, 0x00, 0x00, 0x02, 0xe5, 0x9d, 0x00, 0x18, 0xe3, 0x50, 0x00, 0x02, 0x1a, 0x00, 0x00, 0x3e, 0xe3, 0xa0, 0x10, 0x00, ++0xe5, 0x9d, 0x00, 0x18, 0xeb, 0xff, 0xf7, 0x64, 0xe5, 0x9d, 0x10, 0x98, 0xe5, 0x91, 0x00, 0x00, 0xe3, 0x50, 0x00, 0x5f, 0xda, 0x00, 0x00, 0x1d, 0xe5, 0x9d, 0x10, 0x98, 0xe5, 0x91, 0x00, 0x00, 0xe2, 0x40, 0x10, 0x60, 0xe5, 0x8d, 0x10, 0x44, ++0xe5, 0x9d, 0x10, 0x44, 0xe1, 0xa0, 0x01, 0x01, 0xe5, 0x8d, 0x00, 0x40, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x70, 0xe3, 0xa0, 0x18, 0x57, 0xe5, 0x9d, 0x20, 0x40, 0xe7, 0x81, 0x01, 0x02, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x74, ++0xe5, 0x9d, 0x20, 0x40, 0xe0, 0x81, 0x11, 0x02, 0xe5, 0x81, 0x00, 0x04, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x78, 0xe3, 0xa0, 0x18, 0x57, 0xe5, 0x9d, 0x20, 0x40, 0xe0, 0x81, 0x11, 0x02, 0xe5, 0x81, 0x00, 0x08, 0xe3, 0xa0, 0x08, 0x52, ++0xe5, 0x90, 0x00, 0x7c, 0xe3, 0xa0, 0x18, 0x57, 0xe5, 0x9d, 0x20, 0x40, 0xe0, 0x81, 0x11, 0x02, 0xe5, 0x81, 0x00, 0x0c, 0xea, 0x00, 0x00, 0x19, 0xe5, 0x9d, 0x10, 0x98, 0xe5, 0x91, 0x00, 0x00, 0xe1, 0xa0, 0x01, 0x00, 0xe5, 0x8d, 0x00, 0x40, ++0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x70, 0xe5, 0x9d, 0x20, 0x40, 0xe5, 0x9f, 0x15, 0x6c, 0xe7, 0x81, 0x01, 0x02, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x74, 0xe5, 0x9d, 0x20, 0x40, 0xe0, 0x81, 0x11, 0x02, 0xe5, 0x81, 0x00, 0x04, ++0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x78, 0xe5, 0x9d, 0x20, 0x40, 0xe5, 0x9f, 0x15, 0x44, 0xe0, 0x81, 0x11, 0x02, 0xe5, 0x81, 0x00, 0x08, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x7c, 0xe5, 0x9d, 0x20, 0x40, 0xe5, 0x9f, 0x15, 0x2c, ++0xe0, 0x81, 0x11, 0x02, 0xe5, 0x81, 0x00, 0x0c, 0xe5, 0x9d, 0x10, 0x98, 0xe5, 0x91, 0x00, 0x00, 0xe3, 0xa0, 0x10, 0x03, 0xeb, 0x00, 0x02, 0xf3, 0xe5, 0x8d, 0x10, 0x4c, 0xe3, 0xa0, 0x00, 0x0a, 0xe5, 0x9d, 0x20, 0x4c, 0xe0, 0x00, 0x00, 0x92, ++0xe5, 0x8d, 0x00, 0x3c, 0xe5, 0x9d, 0x20, 0x3c, 0xe2, 0x82, 0x20, 0x01, 0xe5, 0x8d, 0x20, 0x38, 0xe5, 0x9d, 0x20, 0x3c, 0xe2, 0x82, 0x00, 0x09, 0xe5, 0x8d, 0x00, 0x34, 0xe5, 0x9d, 0x20, 0x4c, 0xe3, 0x52, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x02, ++0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x9d, 0x20, 0x64, 0xe5, 0x82, 0x04, 0x94, 0xe5, 0x9d, 0x00, 0x10, 0xe5, 0x9d, 0x10, 0x34, 0xe1, 0xa0, 0x01, 0x10, 0xe5, 0x9d, 0x10, 0x48, 0xe5, 0x9d, 0x20, 0x38, 0xe1, 0x80, 0x02, 0x11, 0xe5, 0x9d, 0x10, 0x1c, ++0xe5, 0x9d, 0x20, 0x3c, 0xe1, 0x80, 0x02, 0x11, 0xe5, 0x9d, 0x20, 0x64, 0xe5, 0x92, 0x14, 0x94, 0xe1, 0x80, 0x00, 0x01, 0xe5, 0x82, 0x04, 0x94, 0xe5, 0x9d, 0x10, 0x98, 0xe5, 0x91, 0x00, 0x00, 0xe3, 0xa0, 0x10, 0x03, 0xeb, 0x00, 0x02, 0xd1, ++0xe3, 0xa0, 0x17, 0x16, 0xe5, 0x9d, 0x20, 0x64, 0xe5, 0x92, 0x24, 0x94, 0xe7, 0x81, 0x21, 0x00, 0xe5, 0x9d, 0x10, 0x98, 0xe5, 0x91, 0x00, 0x00, 0xe1, 0xa0, 0x02, 0xc0, 0xe5, 0x8d, 0x00, 0x4c, 0xe5, 0x9d, 0x10, 0x98, 0xe5, 0x91, 0x00, 0x00, ++0xe2, 0x00, 0x00, 0x1f, 0xe5, 0x8d, 0x00, 0x3c, 0xe5, 0x9d, 0x00, 0x9c, 0xe3, 0x50, 0x00, 0x03, 0x1a, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x1c, 0xe5, 0x9d, 0x20, 0x3c, 0xe3, 0x52, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x02, ++0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x9d, 0x20, 0x64, 0xe5, 0x82, 0x04, 0x88, 0xe5, 0x9d, 0x20, 0x64, 0xe5, 0x92, 0x04, 0x88, 0xe5, 0x9d, 0x10, 0x1c, 0xe5, 0x9d, 0x20, 0x3c, 0xe1, 0x80, 0x02, 0x11, 0xe5, 0x9d, 0x20, 0x64, 0xe5, 0x82, 0x04, 0x88, ++0xe5, 0x9d, 0x20, 0x64, 0xe5, 0x92, 0x04, 0x88, 0xe2, 0x82, 0x1f, 0xaf, 0xe5, 0x9d, 0x20, 0x4c, 0xe7, 0x81, 0x01, 0x02, 0xe5, 0x9d, 0x10, 0x50, 0xe2, 0x81, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x50, 0xe5, 0x9d, 0x10, 0x98, 0xe5, 0x91, 0x00, 0x00, ++0xe2, 0x80, 0x00, 0x01, 0xe5, 0x81, 0x00, 0x00, 0xe3, 0xa0, 0x00, 0x11, 0xeb, 0xff, 0xee, 0xbd, 0xe2, 0x40, 0xca, 0x1f, 0xe2, 0x5c, 0xc0, 0x01, 0x0a, 0x00, 0x00, 0x04, 0xe5, 0x9d, 0x10, 0x98, 0xe5, 0x91, 0x00, 0x00, 0xe5, 0x9d, 0x10, 0x70, ++0xe1, 0x50, 0x00, 0x01, 0xba, 0xff, 0xff, 0x1e, 0xe1, 0xa0, 0x00, 0x00, 0xe5, 0x9d, 0x10, 0x98, 0xe5, 0x91, 0x00, 0x00, 0xe5, 0x9d, 0x10, 0x70, 0xe1, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x0b, 0xe3, 0xa0, 0x00, 0x11, 0xeb, 0xff, 0xee, 0xad, ++0xe2, 0x40, 0xca, 0x1f, 0xe2, 0x5c, 0xc0, 0x01, 0x0a, 0x00, 0x00, 0x06, 0xea, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0x00, 0x0a, 0xeb, 0xff, 0xee, 0xb4, 0xe3, 0xa0, 0x00, 0x0a, 0xeb, 0xff, 0xee, 0xa5, 0xe3, 0x50, 0x00, 0x01, 0x0a, 0xff, 0xff, 0xf9, ++0xe3, 0xa0, 0x00, 0x11, 0xeb, 0xff, 0xee, 0xae, 0xe5, 0x8d, 0x00, 0x48, 0xe5, 0x9d, 0x10, 0x98, 0xe5, 0x91, 0x00, 0x00, 0xe5, 0x9d, 0x10, 0x50, 0xe0, 0x40, 0x10, 0x01, 0xe5, 0x8d, 0x10, 0x30, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x50, ++0xe5, 0x9d, 0x00, 0x6c, 0xe5, 0x8d, 0x00, 0x2c, 0xe3, 0xa0, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x20, 0xea, 0x00, 0x00, 0xd1, 0xe5, 0x9d, 0x10, 0x2c, 0xe5, 0x8d, 0x10, 0x28, 0xe3, 0xa0, 0x10, 0x03, 0xe5, 0x9d, 0x00, 0x30, 0xeb, 0x00, 0x02, 0x77, ++0xe5, 0x8d, 0x10, 0x4c, 0xe3, 0xa0, 0x10, 0x03, 0xe5, 0x9d, 0x00, 0x30, 0xeb, 0x00, 0x02, 0x73, 0xe3, 0xa0, 0x17, 0x16, 0xe7, 0x91, 0x41, 0x00, 0xe3, 0xa0, 0x00, 0x0a, 0xe5, 0x9d, 0x20, 0x4c, 0xe0, 0x00, 0x00, 0x92, 0xe5, 0x8d, 0x00, 0x3c, ++0xe5, 0x9d, 0x20, 0x3c, 0xe2, 0x82, 0x00, 0x05, 0xe5, 0x8d, 0x00, 0x38, 0xe5, 0x9d, 0x20, 0x3c, 0xe1, 0xa0, 0x02, 0x54, 0xe2, 0x00, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x1c, 0xe5, 0x9d, 0x20, 0x38, 0xe1, 0xa0, 0x02, 0x54, 0xe2, 0x00, 0x00, 0x07, ++0xe5, 0x8d, 0x00, 0x18, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x0c, 0xe5, 0x8d, 0x00, 0x14, 0xe5, 0x8d, 0x00, 0x48, 0xe5, 0x9d, 0x10, 0x1c, 0xe3, 0x51, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x7c, 0xe5, 0x9d, 0x00, 0x18, 0xe3, 0x50, 0x00, 0x03, ++0x0a, 0x00, 0x00, 0x02, 0xe5, 0x9d, 0x00, 0x18, 0xe3, 0x50, 0x00, 0x04, 0x1a, 0x00, 0x00, 0x02, 0xe3, 0xa0, 0x00, 0x01, 0xeb, 0xff, 0xee, 0x78, 0xe5, 0x8d, 0x00, 0x0c, 0xe5, 0x9d, 0x00, 0x18, 0xe3, 0x50, 0x00, 0x03, 0x0a, 0x00, 0x00, 0x02, ++0xe5, 0x9d, 0x00, 0x18, 0xe3, 0x50, 0x00, 0x04, 0x1a, 0x00, 0x00, 0x03, 0xe3, 0xa0, 0x00, 0x02, 0xeb, 0xff, 0xf6, 0x6a, 0xe5, 0x8d, 0x00, 0x48, 0xea, 0x00, 0x00, 0x02, 0xe3, 0xa0, 0x00, 0x03, 0xeb, 0xff, 0xf6, 0x66, 0xe5, 0x8d, 0x00, 0x48, ++0xe5, 0x9d, 0x00, 0x18, 0xe3, 0x50, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x02, 0xe5, 0x9d, 0x00, 0x18, 0xe3, 0x50, 0x00, 0x04, 0x1a, 0x00, 0x00, 0x1f, 0xe3, 0xa0, 0x00, 0x02, 0xeb, 0xff, 0xee, 0x62, 0xe5, 0x8d, 0x00, 0x14, 0xe2, 0x8d, 0x00, 0x54, ++0xe5, 0x9d, 0x10, 0x14, 0xe7, 0x90, 0x01, 0x01, 0xe5, 0x9d, 0x10, 0x2c, 0xe0, 0x80, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x2c, 0xe5, 0x9d, 0x10, 0x2c, 0xe3, 0x51, 0x00, 0x1f, 0xca, 0x00, 0x00, 0x02, 0xe5, 0x9d, 0x10, 0x2c, 0xe3, 0x51, 0x00, 0x01, ++0xaa, 0x00, 0x00, 0x10, 0xe5, 0x9d, 0x10, 0x2c, 0xe3, 0x51, 0x00, 0x1f, 0xda, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0x00, 0x1f, 0xea, 0x00, 0x00, 0x00, 0xe5, 0x9d, 0x00, 0x2c, 0xe3, 0x50, 0x00, 0x01, 0xaa, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0x00, 0x01, ++0xea, 0x00, 0x00, 0x05, 0xe5, 0x9d, 0x10, 0x2c, 0xe3, 0x51, 0x00, 0x1f, 0xda, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0x00, 0x1f, 0xea, 0x00, 0x00, 0x00, 0xe5, 0x9d, 0x00, 0x2c, 0xe5, 0x8d, 0x00, 0x2c, 0xe5, 0x9d, 0x00, 0x20, 0xe3, 0x50, 0x00, 0x01, ++0x1a, 0x00, 0x00, 0x01, 0xe5, 0x9d, 0x10, 0x2c, 0xe5, 0x8d, 0x10, 0x28, 0xe5, 0x9d, 0x00, 0x18, 0xe5, 0x9d, 0x10, 0x68, 0xe5, 0x9d, 0x20, 0x28, 0xeb, 0xff, 0xfc, 0x66, 0xe5, 0x8d, 0x00, 0x24, 0xe5, 0x9d, 0x00, 0x24, 0xe3, 0x50, 0x00, 0x00, ++0x1a, 0x00, 0x00, 0x33, 0xe3, 0xa0, 0x30, 0x00, 0xe5, 0x8d, 0x30, 0x00, 0xe3, 0xa0, 0x30, 0x01, 0xe3, 0xa0, 0x20, 0x00, 0xe3, 0xa0, 0x10, 0x01, 0xe3, 0xa0, 0x00, 0x00, 0xeb, 0xff, 0xf6, 0x19, 0xe5, 0x9d, 0x10, 0x30, 0xe3, 0x51, 0x00, 0x5f, ++0xda, 0x00, 0x00, 0x16, 0xe5, 0x9d, 0x10, 0x30, 0xe2, 0x41, 0x00, 0x60, 0xe5, 0x8d, 0x00, 0x44, 0xe5, 0x9d, 0x10, 0x44, 0xe1, 0xa0, 0x01, 0x01, 0xe5, 0x8d, 0x00, 0x40, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x64, 0xe3, 0xa0, 0x18, 0x57, ++0xe5, 0x9d, 0x20, 0x40, 0xe7, 0x81, 0x01, 0x02, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x68, 0xe5, 0x9d, 0x20, 0x40, 0xe0, 0x81, 0x11, 0x02, 0xe5, 0x81, 0x00, 0x04, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x6c, 0xe3, 0xa0, 0x18, 0x57, ++0xe5, 0x9d, 0x20, 0x40, 0xe0, 0x81, 0x11, 0x02, 0xe5, 0x81, 0x00, 0x08, 0xea, 0x00, 0x00, 0x12, 0xe5, 0x9d, 0x10, 0x30, 0xe1, 0xa0, 0x01, 0x01, 0xe5, 0x8d, 0x00, 0x40, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x64, 0xe5, 0x9d, 0x20, 0x40, ++0xe5, 0x9f, 0x10, 0xf0, 0xe7, 0x81, 0x01, 0x02, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x68, 0xe5, 0x9d, 0x20, 0x40, 0xe0, 0x81, 0x11, 0x02, 0xe5, 0x81, 0x00, 0x04, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x6c, 0xe5, 0x9d, 0x20, 0x40, ++0xe5, 0x9f, 0x10, 0xc8, 0xe0, 0x81, 0x11, 0x02, 0xe5, 0x81, 0x00, 0x08, 0xe3, 0xa0, 0x10, 0x03, 0xe5, 0x9d, 0x00, 0x30, 0xeb, 0x00, 0x01, 0xdb, 0xe5, 0x8d, 0x10, 0x4c, 0xe3, 0xa0, 0x00, 0x0a, 0xe5, 0x9d, 0x20, 0x4c, 0xe0, 0x00, 0x00, 0x92, ++0xe5, 0x8d, 0x00, 0x3c, 0xe5, 0x9d, 0x20, 0x3c, 0xe2, 0x82, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x38, 0xe5, 0x9d, 0x20, 0x3c, 0xe2, 0x82, 0x00, 0x05, 0xe5, 0x8d, 0x00, 0x34, 0xe5, 0x9d, 0x20, 0x4c, 0xe3, 0x52, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x02, ++0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x9d, 0x20, 0x64, 0xe5, 0x82, 0x04, 0x98, 0xe5, 0x9d, 0x00, 0x34, 0xe5, 0x9d, 0x10, 0x14, 0xe1, 0xa0, 0x00, 0x11, 0xe5, 0x9d, 0x10, 0x48, 0xe5, 0x9d, 0x20, 0x38, 0xe1, 0x80, 0x02, 0x11, 0xe5, 0x9d, 0x10, 0x0c, ++0xe5, 0x9d, 0x20, 0x3c, 0xe1, 0x80, 0x02, 0x11, 0xe5, 0x9d, 0x20, 0x64, 0xe5, 0x92, 0x14, 0x98, 0xe1, 0x80, 0x00, 0x01, 0xe5, 0x82, 0x04, 0x98, 0xe3, 0xa0, 0x10, 0x03, 0xe5, 0x9d, 0x00, 0x30, 0xeb, 0x00, 0x01, 0xba, 0xe3, 0xa0, 0x18, 0x59, ++0xe5, 0x9d, 0x20, 0x64, 0xe5, 0x92, 0x24, 0x98, 0xe7, 0x81, 0x21, 0x00, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x20, 0xe5, 0x9d, 0x10, 0x30, 0xe2, 0x81, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x30, 0xe5, 0x9d, 0x10, 0x50, 0xe2, 0x81, 0x00, 0x01, ++0xea, 0x00, 0x00, 0x02, 0x00, 0x00, 0x1f, 0x4c, 0x00, 0x60, 0x00, 0x50, 0x00, 0x00, 0x17, 0x24, 0xe5, 0x8d, 0x00, 0x50, 0xe5, 0x9d, 0x10, 0x98, 0xe5, 0x91, 0x00, 0x00, 0xe5, 0x9d, 0x10, 0x30, 0xe1, 0x50, 0x00, 0x01, 0xca, 0xff, 0xff, 0x28, ++0xe5, 0x9d, 0x10, 0x98, 0xe5, 0x91, 0x00, 0x00, 0xe5, 0x9d, 0x10, 0x50, 0xe0, 0x40, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x30, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x50, 0xe5, 0x9d, 0x00, 0x6c, 0xe5, 0x8d, 0x00, 0x2c, 0xe3, 0xa0, 0x00, 0x01, ++0xe5, 0x8d, 0x00, 0x20, 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0x70, 0x61, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc40/mp4_enc_fw.c linux-2.6.28.6/drivers/media/video/samsung/mfc40/mp4_enc_fw.c +--- linux-2.6.28/drivers/media/video/samsung/mfc40/mp4_enc_fw.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/mp4_enc_fw.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,307 @@ ++/* ++ * drivers/media/video/samsung/mfc40/mp4_enc_fw.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++ ++const unsigned char mp4_enc_mc_fw[11628] = { ++0xea, 0x00, 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0x90, 0x01, 0x74, ++0xe3, 0xa0, 0x16, 0x05, 0xe5, 0x81, 0x0a, 0x34, 0xe3, 0xa0, 0x08, 0x55, 0xe5, 0x90, 0x01, 0x58, 0xe2, 0x00, 0x00, 0x3f, 0xe5, 0x81, 0x0a, 0x18, 0xe5, 0x9d, 0xc0, 0x18, 0xe5, 0x9c, 0x00, 0x84, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x07, ++0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x44, 0xe5, 0x9d, 0xc0, 0x18, 0xe5, 0x9c, 0x10, 0x64, 0xe0, 0x40, 0x01, 0x81, 0xe5, 0x8c, 0x00, 0x88, 0xe5, 0x9d, 0x00, 0x18, 0xeb, 0x00, 0x04, 0x3d, 0xea, 0x00, 0x00, 0x04, 0xe3, 0xa0, 0x08, 0x52, ++0xe5, 0x90, 0x00, 0xdc, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x00, 0xea, 0x00, 0x00, 0x00, 0xea, 0xff, 0xff, 0xf9, 0xea, 0x00, 0x00, 0x00, 0xeb, 0xff, 0xfc, 0xd3, 0xe5, 0x9d, 0xc0, 0x18, 0xe5, 0x9c, 0x00, 0x5c, 0xe2, 0x80, 0x00, 0x01, ++0xe5, 0x8c, 0x00, 0x5c, 0xe5, 0x9d, 0xc0, 0x18, 0xe5, 0x9c, 0x00, 0x58, 0xe2, 0x80, 0x00, 0x01, 0xe5, 0x8c, 0x00, 0x58, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x9d, 0xc0, 0x18, 0xe5, 0x8c, 0x00, 0x48, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0x44, ++0xe1, 0xa0, 0x01, 0xa0, 0xe5, 0x9d, 0xc0, 0x18, 0xe5, 0x8c, 0x00, 0x68, 0xe5, 0x9d, 0xc0, 0x18, 0xe3, 0xa0, 0x16, 0x05, 0xe5, 0x9c, 0x00, 0x68, 0xe5, 0x81, 0x00, 0x58, 0xe5, 0x9d, 0xc0, 0x18, 0xe5, 0x9c, 0x00, 0x64, 0xe5, 0x81, 0x00, 0x60, ++0xeb, 0xff, 0xfc, 0x5c, 0xe3, 0x54, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x65, 0xe3, 0xa0, 0x10, 0x03, 0xe5, 0x9d, 0x00, 0x0c, 0xeb, 0x00, 0x04, 0xdc, 0xe5, 0x8d, 0x10, 0x14, 0xe5, 0x9d, 0xc0, 0x18, 0xe5, 0x9c, 0x00, 0x04, 0xe3, 0x50, 0x00, 0x01, ++0x1a, 0x00, 0x00, 0x5d, 0xe5, 0x9d, 0x00, 0x14, 0xe3, 0x50, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x5a, 0xe3, 0xa0, 0x00, 0x00, 0xe3, 0xa0, 0x18, 0x55, 0xe5, 0x81, 0x00, 0x00, 0xe5, 0x81, 0x00, 0x1c, 0xe5, 0x81, 0x00, 0x4c, 0xe5, 0x9f, 0x00, 0x84, ++0xe5, 0x81, 0x01, 0x8c, 0xe5, 0x9d, 0xc0, 0x18, 0xe5, 0x9c, 0x00, 0x4c, 0xe3, 0x50, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x03, 0xe5, 0x9d, 0xc0, 0x18, 0xe5, 0x9c, 0x00, 0x6c, 0xe5, 0x81, 0x01, 0x90, 0xea, 0x00, 0x00, 0x03, 0xe5, 0x9d, 0xc0, 0x18, ++0xe3, 0xa0, 0x18, 0x55, 0xe5, 0x9c, 0x00, 0x70, 0xe5, 0x81, 0x01, 0x90, 0xe3, 0xa0, 0x06, 0x05, 0xe5, 0x90, 0x08, 0x00, 0xe3, 0xa0, 0x18, 0x55, 0xe5, 0x81, 0x00, 0x3c, 0xe3, 0xa0, 0x06, 0x05, 0xe5, 0x90, 0x08, 0x00, 0xe5, 0x81, 0x00, 0x40, ++0xe3, 0xa0, 0x06, 0x05, 0xe5, 0x90, 0x08, 0x04, 0xe5, 0x81, 0x00, 0x44, 0xe3, 0xa0, 0x06, 0x05, 0xe5, 0x90, 0x08, 0x04, 0xe5, 0x81, 0x00, 0x48, 0xe5, 0x9d, 0x00, 0x14, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x08, 0xe5, 0x9f, 0x00, 0x18, ++0xe3, 0xa0, 0x18, 0x56, 0xe5, 0x81, 0x00, 0x00, 0xe3, 0xa0, 0x70, 0x08, 0xea, 0x00, 0x00, 0x07, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x80, 0x20, 0x00, 0x03, 0x00, 0x08, 0x00, 0x01, 0x00, 0x40, 0xe5, 0x9f, 0x04, 0xe0, 0xe3, 0xa0, 0x18, 0x56, ++0xe5, 0x81, 0x00, 0x00, 0xe3, 0xa0, 0x70, 0x04, 0xe5, 0x9d, 0xc0, 0x18, 0xe3, 0xa0, 0x18, 0x56, 0xe5, 0x9c, 0x00, 0x04, 0xe5, 0x81, 0x00, 0x04, 0xe5, 0x9d, 0xc0, 0x18, 0xe2, 0x8c, 0x10, 0x4c, 0xe8, 0x91, 0x00, 0x03, 0xe1, 0x80, 0x0c, 0x01, ++0xe3, 0xa0, 0x18, 0x56, 0xe5, 0x81, 0x00, 0x08, 0xe3, 0xa0, 0x00, 0x03, 0xe5, 0x81, 0x00, 0x14, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x8d, 0x00, 0x10, 0xea, 0x00, 0x00, 0x11, 0xe3, 0xa0, 0x00, 0x01, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0xc8, ++0xea, 0x00, 0x00, 0x04, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0xd4, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x00, 0xea, 0x00, 0x00, 0x00, 0xea, 0xff, 0xff, 0xf9, 0xe1, 0xa0, 0x00, 0x00, 0xe5, 0x9d, 0x00, 0x10, 0xe2, 0x80, 0x00, 0x01, ++0xe5, 0x8d, 0x00, 0x10, 0xe5, 0x9d, 0x00, 0x10, 0xe1, 0x50, 0x00, 0x07, 0x1a, 0x00, 0x00, 0x00, 0xea, 0x00, 0x00, 0x00, 0xea, 0xff, 0xff, 0xec, 0xe1, 0xa0, 0x00, 0x00, 0xea, 0x00, 0x00, 0x04, 0xe3, 0xa0, 0x08, 0x52, 0xe5, 0x90, 0x00, 0xdc, ++0xe3, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x00, 0xea, 0x00, 0x00, 0x00, 0xea, 0xff, 0xff, 0xf9, 0xe1, 0xa0, 0x00, 0x00, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x9d, 0xc0, 0x18, 0xe5, 0x8c, 0x00, 0x64, 0xe5, 0x9d, 0xc0, 0x18, 0xe5, 0x8c, 0x00, 0x68, ++0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x81, 0x00, 0x44, 0xe3, 0xa0, 0x0c, 0x02, 0xe5, 0x81, 0x00, 0x04, 0xe3, 0x54, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x03, 0xe3, 0xa0, 0x00, 0x00, 0xe3, 0xa0, 0x16, 0x05, 0xe5, 0x81, 0x0c, 0x0c, 0xea, 0x00, 0x00, 0x0a, ++0xe5, 0x9d, 0xc0, 0x18, 0xe5, 0x9c, 0x00, 0x04, 0xe3, 0x50, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x03, 0xe3, 0xa0, 0x00, 0x01, 0xe3, 0xa0, 0x16, 0x05, 0xe5, 0x81, 0x0c, 0x0c, 0xea, 0x00, 0x00, 0x02, 0xe3, 0xa0, 0x00, 0x02, 0xe3, 0xa0, 0x16, 0x05, ++0xe5, 0x81, 0x0c, 0x0c, 0xe3, 0xa0, 0x00, 0x01, 0xe3, 0xa0, 0x16, 0x05, 0xe5, 0x81, 0x05, 0x0c, 0xe3, 0xa0, 0x00, 0x00, 0xea, 0xff, 0xfc, 0xb4, 0xe9, 0x2d, 0x47, 0xf0, 0xe3, 0xa0, 0xc0, 0x00, 0xe5, 0x80, 0xc0, 0x00, 0xe3, 0xa0, 0xc6, 0x05, ++0xe5, 0x9c, 0xc1, 0x18, 0xe5, 0x80, 0xc0, 0x08, 0xe3, 0xa0, 0xc6, 0x05, 0xe5, 0x9c, 0xc1, 0x1c, 0xe5, 0x80, 0xc0, 0x0c, 0xe5, 0x90, 0xc0, 0x08, 0xe2, 0x8c, 0xc0, 0x0f, 0xe1, 0xa0, 0xc2, 0x4c, 0xe5, 0x80, 0xc0, 0x10, 0xe5, 0x90, 0xc0, 0x0c, ++0xe2, 0x8c, 0xc0, 0x0f, 0xe1, 0xa0, 0xc2, 0x4c, 0xe5, 0x80, 0xc0, 0x14, 0xe3, 0xa0, 0xc6, 0x05, 0xe5, 0x9c, 0xc3, 0x00, 0xe2, 0x0c, 0xc0, 0x03, 0xe5, 0x80, 0xc0, 0x18, 0xe3, 0xa0, 0xc6, 0x05, 0xe5, 0x9c, 0xc3, 0x08, 0xe5, 0x80, 0xc0, 0x1c, ++0xe5, 0x90, 0x90, 0x1c, 0xe2, 0x49, 0xcc, 0xff, 0xe2, 0x5c, 0xc0, 0xff, 0x0a, 0x00, 0x00, 0x02, 0xe5, 0x90, 0xc0, 0x1c, 0xe2, 0x8c, 0xc0, 0x01, 0xe5, 0x80, 0xc0, 0x1c, 0xe3, 0xa0, 0xc6, 0x05, 0xe5, 0x9c, 0xca, 0x00, 0xe2, 0x0c, 0xc0, 0x3f, ++0xe5, 0x80, 0xc0, 0x20, 0xe3, 0xa0, 0xc0, 0x00, 0xe5, 0x80, 0xc0, 0x28, 0xe3, 0xa0, 0xc6, 0x05, 0xe5, 0x9c, 0xc1, 0x00, 0xe3, 0x5c, 0x00, 0x14, 0x0a, 0x00, 0x00, 0x03, 0xe3, 0xa0, 0xc6, 0x05, 0xe5, 0x9c, 0xc3, 0x18, 0xe3, 0x5c, 0x00, 0x01, ++0x1a, 0x00, 0x00, 0x02, 0xe3, 0xa0, 0xc0, 0x01, 0xe5, 0x80, 0xc0, 0x2c, 0xea, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0xc0, 0x00, 0xe5, 0x80, 0xc0, 0x2c, 0xe3, 0xa0, 0xc6, 0x05, 0xe5, 0x9c, 0xc3, 0x1c, 0xe5, 0x80, 0xc0, 0x30, 0xe3, 0xa0, 0xc6, 0x05, ++0xe5, 0x9c, 0xc3, 0x20, 0xe5, 0x80, 0xc0, 0x34, 0xe3, 0xa0, 0xc6, 0x05, 0xe5, 0x9c, 0xc3, 0x24, 0xe5, 0x80, 0xc0, 0x38, 0xe3, 0xa0, 0xc6, 0x05, 0xe5, 0x9c, 0xc3, 0x28, 0xe2, 0x4c, 0xcd, 0x1e, 0xe5, 0x80, 0xc0, 0x3c, 0xe5, 0x90, 0xc0, 0x2c, ++0xe3, 0x5c, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0xc0, 0x03, 0xea, 0x00, 0x00, 0x00, 0xe3, 0xa0, 0xc0, 0x01, 0xe5, 0x80, 0xc0, 0x40, 0xe5, 0x90, 0xc0, 0x30, 0xe3, 0x5c, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x02, 0xe5, 0x90, 0xc0, 0x34, ++0xe3, 0x5c, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x01, 0xe3, 0xa0, 0xc0, 0x00, 0xe5, 0x80, 0xc0, 0x38, 0xe3, 0xa0, 0xc0, 0x1e, 0xe5, 0x80, 0xc0, 0x44, 0xe3, 0xa0, 0xc0, 0x01, 0xe5, 0x80, 0xc0, 0x48, 0xe3, 0xa0, 0xc0, 0x00, 0xe5, 0x80, 0xc0, 0x4c, ++0xe3, 0xa0, 0xc0, 0x01, 0xe5, 0x80, 0xc0, 0x50, 0xe5, 0x90, 0x90, 0x14, 0xe5, 0x90, 0xc0, 0x10, 0xe0, 0x0c, 0x0c, 0x99, 0xe5, 0x80, 0xc0, 0x54, 0xe3, 0xa0, 0xc0, 0x00, 0xe5, 0x80, 0xc0, 0x58, 0xe5, 0x80, 0xc0, 0x5c, 0xe5, 0x80, 0xc0, 0x60, ++0xe5, 0x80, 0xc0, 0x64, 0xe5, 0x80, 0xc0, 0x68, 0xe3, 0xa0, 0xc6, 0x05, 0xe5, 0x9c, 0xc1, 0x24, 0xe5, 0x80, 0xc0, 0x80, 0xe3, 0xa0, 0xc6, 0x05, 0xe5, 0x9c, 0xc8, 0x10, 0xe5, 0x80, 0xc1, 0x2c, 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PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++#include "s3c_mfc_interface.h" ++#include "s3c_mfc_common.h" ++#include "s3c_mfc_logmsg.h" ++#include "s3c_mfc_opr.h" ++#include "s3c_mfc_intr.h" ++#include "s3c_mfc_memory.h" ++#include "s3c_mfc_buffer_manager.h" ++ ++int isMFCRunning = 0; ++ ++static struct resource *s3c_mfc_mem; ++void __iomem *s3c_mfc_sfr_virt_base; ++volatile unsigned char *s3c_mfc_virt_fw_buf= NULL; ++unsigned int s3c_mfc_int_type = 0; ++ ++static struct mutex s3c_mfc_mutex; ++ ++dma_addr_t s3c_mfc_phys_data_buf; ++unsigned char *s3c_mfc_virt_data_buf; ++ ++DECLARE_WAIT_QUEUE_HEAD(s3c_mfc_wait_queue); ++ ++static int s3c_mfc_open(struct inode *inode, struct file *file) ++{ ++ s3c_mfc_inst_ctx *MfcCtx; ++ int ret; ++ ++ mutex_lock(&s3c_mfc_mutex); ++ ++ MfcCtx = (s3c_mfc_inst_ctx *) kmalloc(sizeof(s3c_mfc_inst_ctx), GFP_KERNEL); ++ if (MfcCtx == NULL) { ++ mfc_err("MFCINST_MEMORY_ALLOC_FAIL\n"); ++ ret = -ENOMEM; ++ goto out_open; ++ } ++ memset(MfcCtx, 0, sizeof(s3c_mfc_inst_ctx)); ++ ++ s3c_mfc_init_hw(); ++ ++ MfcCtx->InstNo = s3c_mfc_get_inst_no(); ++ if (MfcCtx->InstNo < 0) { ++ kfree(MfcCtx); ++ mfc_err("MFCINST_INST_NUM_EXCEEDED\n"); ++ ret = -EPERM; ++ goto out_open; ++ } ++ ++ if (s3c_mfc_set_state(MfcCtx, MFCINST_STATE_OPENED) == 0) { ++ mfc_err("MFCINST_ERR_STATE_INVALID\n"); ++ kfree(MfcCtx); ++ ret = -ENODEV; ++ goto out_open; ++ } ++ ++ MfcCtx->extraDPB = MFC_MAX_EXTRA_DPB; ++ MfcCtx->FrameType = MFC_RET_FRAME_NOT_SET; ++ ++ file->private_data = (s3c_mfc_inst_ctx *)MfcCtx; ++ ret = 0; ++ ++out_open: ++ mutex_unlock(&s3c_mfc_mutex); ++ return ret; ++} ++ ++static int s3c_mfc_release(struct inode *inode, struct file *file) ++{ ++ s3c_mfc_inst_ctx *MfcCtx; ++ int ret; ++ ++ mfc_debug("MFC Release..\n"); ++ mutex_lock(&s3c_mfc_mutex); ++ ++ MfcCtx = (s3c_mfc_inst_ctx *)file->private_data; ++ if (MfcCtx == NULL) { ++ mfc_err("MFCINST_ERR_INVALID_PARAM\n"); ++ ret = -EIO; ++ goto out_release; ++ } ++ ++ s3c_mfc_merge_frag(MfcCtx->InstNo); ++ ++ s3c_mfc_return_inst_no(MfcCtx->InstNo); ++ kfree(MfcCtx); ++ ++ ret = 0; ++ ++out_release: ++ mutex_unlock(&s3c_mfc_mutex); ++ return ret; ++} ++ ++static int s3c_mfc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ int ret, ex_ret; ++ int frameBufSize; ++ int frame_size; ++ s3c_mfc_inst_ctx *MfcCtx = NULL; ++ s3c_mfc_common_args InParm; ++ s3c_mfc_args local_param; ++ ++ ++ mutex_lock(&s3c_mfc_mutex); ++ ++ ret = copy_from_user(&InParm, (s3c_mfc_common_args *)arg, sizeof(s3c_mfc_common_args)); ++ if (ret < 0) { ++ mfc_err("Inparm copy error\n"); ++ ret = -EIO; ++ InParm.ret_code = MFCINST_ERR_INVALID_PARAM; ++ goto out_ioctl; ++ } ++ ++ MfcCtx = (s3c_mfc_inst_ctx *)file->private_data; ++ mutex_unlock(&s3c_mfc_mutex); ++ ++ switch (cmd) { ++ case IOCTL_MFC_ENC_INIT: ++ mutex_lock(&s3c_mfc_mutex); ++ if (!s3c_mfc_set_state(MfcCtx, MFCINST_STATE_ENC_INITIALIZE)) { ++ mfc_err("MFCINST_ERR_STATE_INVALID\n"); ++ InParm.ret_code = MFCINST_ERR_STATE_INVALID; ++ ret = -EINVAL; ++ mutex_unlock(&s3c_mfc_mutex); ++ break; ++ } ++ ++ InParm.ret_code = s3c_mfc_init_encode(MfcCtx, &(InParm.args)); ++ mfc_debug("InParm->ret_code : %d\n", InParm.ret_code); ++ ret = InParm.ret_code; ++ mutex_unlock(&s3c_mfc_mutex); ++ break; ++ ++ case IOCTL_MFC_ENC_EXE: ++ mutex_lock(&s3c_mfc_mutex); ++ if (!s3c_mfc_set_state(MfcCtx, MFCINST_STATE_ENC_EXE)) { ++ mfc_err("MFCINST_ERR_STATE_INVALID\n"); ++ InParm.ret_code = MFCINST_ERR_STATE_INVALID; ++ ret = -EINVAL; ++ mutex_unlock(&s3c_mfc_mutex); ++ break; ++ } ++ ++ InParm.ret_code = s3c_mfc_exe_encode(MfcCtx, &(InParm.args)); ++ mfc_debug("InParm->ret_code : %d\n", InParm.ret_code); ++ ret = InParm.ret_code; ++ mutex_unlock(&s3c_mfc_mutex); ++ break; ++ ++ case IOCTL_MFC_DEC_INIT: ++ mutex_lock(&s3c_mfc_mutex); ++ mfc_debug("IOCTL_MFC_DEC_INIT\n"); ++ if (!s3c_mfc_set_state(MfcCtx, MFCINST_STATE_DEC_INITIALIZE)) { ++ mfc_err("MFCINST_ERR_STATE_INVALID\n"); ++ InParm.ret_code = MFCINST_ERR_STATE_INVALID; ++ ret = -EINVAL; ++ mutex_unlock(&s3c_mfc_mutex); ++ break; ++ } ++ ++ memset(&local_param, 0, sizeof(local_param)); ++ ++ local_param.dec_init.in_codec_type = InParm.args.dec_super_init.in_codec_type; ++ local_param.dec_init.in_strm_size = InParm.args.dec_super_init.in_strm_size; ++ local_param.dec_init.in_strm_buf = InParm.args.dec_super_init.in_strm_buf; ++ local_param.dec_init.in_packed_PB = InParm.args.dec_super_init.in_packed_PB; ++ ++ /* MFC decode init */ ++ InParm.ret_code = s3c_mfc_init_decode(MfcCtx, &local_param); ++ if (InParm.ret_code < 0) { ++ ret = InParm.ret_code; ++ mutex_unlock(&s3c_mfc_mutex); ++ break; ++ } ++ ++ InParm.args.dec_super_init.out_img_width = local_param.dec_init.out_img_width; ++ InParm.args.dec_super_init.out_img_height = local_param.dec_init.out_img_height; ++ InParm.args.dec_super_init.out_buf_width = local_param.dec_init.out_buf_width; ++ InParm.args.dec_super_init.out_buf_height = local_param.dec_init.out_buf_height; ++ InParm.args.dec_super_init.out_dpb_cnt = local_param.dec_init.out_dpb_cnt; ++ if (local_param.dec_init.out_dpb_cnt <=0 ) { ++ mfc_err("MFC out_dpb_cnt error\n"); ++ mutex_unlock(&s3c_mfc_mutex); ++ break; ++ } ++ ++ frame_size = (local_param.dec_init.out_buf_width * ++ local_param.dec_init.out_buf_height * 3) >> 1; ++ frameBufSize = local_param.dec_init.out_dpb_cnt * frame_size; ++ InParm.args.dec_super_init.out_frame_buf_size = frameBufSize; ++ ++ memset(&local_param, 0, sizeof(local_param)); ++ local_param.mem_alloc.buff_size = (frameBufSize + 63) / 64 * 64; ++ local_param.mem_alloc.cached_mapped_addr = InParm.args.dec_super_init.in_cached_mapped_addr; ++ local_param.mem_alloc.non_cached_mapped_addr = InParm.args.dec_super_init.in_non_cached_mapped_addr; ++ local_param.mem_alloc.cache_flag = InParm.args.dec_super_init.in_cache_flag; ++ ++ /* mfc yuv buffer allocation */ ++ InParm.ret_code = s3c_mfc_get_virt_addr(MfcCtx, &local_param); ++ if (InParm.ret_code < 0) { ++ ret = InParm.ret_code; ++ mutex_unlock(&s3c_mfc_mutex); ++ break; ++ } ++ ++ InParm.args.dec_super_init.out_u_addr = local_param.mem_alloc.out_addr; ++ ++ memset(&local_param, 0, sizeof(local_param)); ++ ++ /* get physical yuv buffer address */ ++ local_param.get_phys_addr.u_addr = InParm.args.dec_super_init.out_u_addr; ++ InParm.ret_code = s3c_mfc_get_phys_addr(MfcCtx, &local_param); ++ if (InParm.ret_code < 0) { ++ ret = InParm.ret_code; ++ mutex_unlock(&s3c_mfc_mutex); ++ break; ++ } ++ ++ InParm.args.dec_super_init.out_p_addr = local_param.get_phys_addr.p_addr; ++ ++ if (!s3c_mfc_set_state(MfcCtx, MFCINST_STATE_DEC_SEQ_START)) { ++ mfc_err("MFCINST_STATE_DEC_SEQ_START\n"); ++ InParm.ret_code = MFCINST_ERR_STATE_INVALID; ++ ret = -EINVAL; ++ mutex_unlock(&s3c_mfc_mutex); ++ break; ++ } ++ ++ memset(&local_param, 0, sizeof(local_param)); ++ ++ local_param.dec_seq_start.in_codec_type = InParm.args.dec_super_init.in_codec_type; ++ local_param.dec_seq_start.in_frm_buf = InParm.args.dec_super_init.out_p_addr; ++ local_param.dec_seq_start.in_frm_size = frameBufSize; ++ local_param.dec_seq_start.in_strm_buf = InParm.args.dec_super_init.in_strm_buf; ++ local_param.dec_seq_start.in_strm_size = InParm.args.dec_super_init.in_strm_size; ++ ++ InParm.ret_code = s3c_mfc_start_decode_seq(MfcCtx, &local_param); ++ if (InParm.ret_code < 0) { ++ ret = InParm.ret_code; ++ mutex_unlock(&s3c_mfc_mutex); ++ break; ++ } ++ ++ mutex_unlock(&s3c_mfc_mutex); ++ ++ ++ /* ++ * !!! CAUTION !!! ++ * Don't release mutex at the end of IOCTL_MFC_DEC_INIT. and, ++ * don't lock mutex at the begining of IOCTL_MFC_DEC_SEQ_START ++ * because IOCTL_MFC_DEC_INIT and IOCTL_MFC_DEC_SEQ_START ++ * are atomic operation. ++ * other operation is not allowed between them. ++ */ ++ ++ break; ++ ++ case IOCTL_MFC_DEC_SEQ_START: ++ mfc_debug("IOCTL_MFC_DEC_SEQ_START\n"); ++ if (!s3c_mfc_set_state(MfcCtx, MFCINST_STATE_DEC_SEQ_START)) { ++ mfc_err("MFCINST_STATE_DEC_SEQ_START\n"); ++ InParm.ret_code = MFCINST_ERR_STATE_INVALID; ++ ret = -EINVAL; ++ mutex_unlock(&s3c_mfc_mutex); ++ break; ++ } ++ ++ InParm.ret_code = s3c_mfc_start_decode_seq(MfcCtx, &(InParm.args)); ++ mutex_unlock(&s3c_mfc_mutex); ++ break; ++ ++ case IOCTL_MFC_DEC_EXE: ++ mutex_lock(&s3c_mfc_mutex); ++ mfc_debug("IOCTL_MFC_DEC_EXE\n"); ++ if (!s3c_mfc_set_state(MfcCtx, MFCINST_STATE_DEC_EXE)) { ++ mfc_err("MFCINST_ERR_STATE_INVALID\n"); ++ InParm.ret_code = MFCINST_ERR_STATE_INVALID; ++ ret = -EINVAL; ++ mutex_unlock(&s3c_mfc_mutex); ++ break; ++ } ++ ++ InParm.ret_code = s3c_mfc_exe_decode(MfcCtx, &(InParm.args)); ++ ret = InParm.ret_code; ++ mutex_unlock(&s3c_mfc_mutex); ++ break; ++ ++ case IOCTL_MFC_GET_CONFIG: ++ mutex_lock(&s3c_mfc_mutex); ++ if (MfcCtx->MfcState < MFCINST_STATE_DEC_SEQ_START) { ++ mfc_err("MFCINST_ERR_STATE_INVALID\n"); ++ InParm.ret_code = MFCINST_ERR_STATE_INVALID; ++ ret = -EINVAL; ++ mutex_unlock(&s3c_mfc_mutex); ++ break; ++ } ++ ++ InParm.ret_code = s3c_mfc_get_config(MfcCtx, &(InParm.args)); ++ ret = InParm.ret_code; ++ mutex_unlock(&s3c_mfc_mutex); ++ break; ++ ++ case IOCTL_MFC_SET_CONFIG: ++ mutex_lock(&s3c_mfc_mutex); ++ InParm.ret_code = s3c_mfc_set_config(MfcCtx, &(InParm.args)); ++ ret = InParm.ret_code; ++ mutex_unlock(&s3c_mfc_mutex); ++ break; ++ ++ case IOCTL_MFC_REQ_BUF: ++ ++ if (MfcCtx->MfcState < MFCINST_STATE_OPENED) { ++ mfc_err("MFCINST_ERR_STATE_INVALID\n"); ++ InParm.ret_code = MFCINST_ERR_STATE_INVALID; ++ ret = -EINVAL; ++ ++ break; ++ } ++ ++ InParm.args.mem_alloc.buff_size = (InParm.args.mem_alloc.buff_size + 63) / 64 * 64; ++ InParm.ret_code = s3c_mfc_get_virt_addr(MfcCtx, &(InParm.args)); ++ ret = InParm.ret_code; ++ ++ break; ++ ++ case IOCTL_MFC_FREE_BUF: ++ ++ ++ if (MfcCtx->MfcState < MFCINST_STATE_OPENED) { ++ mfc_err("MFCINST_ERR_STATE_INVALID\n"); ++ InParm.ret_code = MFCINST_ERR_STATE_INVALID; ++ ret = -EINVAL; ++ ++ break; ++ } ++ InParm.ret_code = s3c_mfc_release_alloc_mem(MfcCtx, &(InParm.args)); ++ ret = InParm.ret_code; ++ ++ break; ++ ++ case IOCTL_MFC_GET_PHYS_ADDR: ++ ++ if (MfcCtx->MfcState < MFCINST_STATE_OPENED) { ++ mfc_err("MFCINST_ERR_STATE_INVALID\n"); ++ InParm.ret_code = MFCINST_ERR_STATE_INVALID; ++ ret = -EINVAL; ++ ++ break; ++ } ++ ++ InParm.ret_code = s3c_mfc_get_phys_addr(MfcCtx, &(InParm.args)); ++ ret = InParm.ret_code; ++ ++ break; ++ ++ default: ++ mfc_err("Requested ioctl command is not defined. (ioctl cmd=0x%08x)\n", cmd); ++ InParm.ret_code = MFCINST_ERR_INVALID_PARAM; ++ ret = -EINVAL; ++ ++ } ++ ++ ++out_ioctl: ++ ex_ret = copy_to_user((s3c_mfc_common_args *)arg, &InParm, sizeof(s3c_mfc_common_args)); ++ if (ex_ret < 0) { ++ mfc_err("Outparm copy to user error\n"); ++ ret = -EIO; ++ } ++ ++ mfc_debug("---------------IOCTL return--------------------------%d\n", ret); ++ return ret; ++} ++ ++static int s3c_mfc_mmap(struct file *filp, struct vm_area_struct *vma) ++{ ++ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; ++ unsigned long size = 0; ++ unsigned long pageFrameNo = 0; ++ ++ mfc_debug("vma->vm_end - vma->vm_start = %d\n", offset); ++ ++ pageFrameNo = __phys_to_pfn(s3c_mfc_phys_data_buf); ++ vma->vm_flags |= VM_RESERVED | VM_IO; ++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ size = s3c_get_media_memsize(S3C_MDEV_MFC); ++ ++ if( remap_pfn_range(vma, vma->vm_start, pageFrameNo, size, vma->vm_page_prot) ) { ++ mfc_err("mfc remap error\n"); ++ return -EAGAIN; ++ } ++ ++ return 0; ++ ++} ++ ++static struct file_operations s3c_mfc_fops = { ++ .owner = THIS_MODULE, ++ .open = s3c_mfc_open, ++ .release = s3c_mfc_release, ++ .ioctl = s3c_mfc_ioctl, ++ .mmap = s3c_mfc_mmap ++}; ++ ++ ++static struct miscdevice s3c_mfc_miscdev = { ++ .minor = 252, ++ .name = "s3c-mfc", ++ .fops = &s3c_mfc_fops, ++}; ++ ++static irqreturn_t s3c_mfc_irq(int irq, void *dev_id) ++{ ++ unsigned int intReason; ++ ++ intReason = readl(s3c_mfc_sfr_virt_base + S3C_FIMV_INT_STATUS) & 0x1FF; ++ ++ if (((intReason & MFC_INTR_FRAME_DONE) == MFC_INTR_FRAME_DONE) ++ ||((intReason & MFC_INTR_FW_DONE) == MFC_INTR_FW_DONE) ++ ||((intReason & MFC_INTR_DMA_DONE) == MFC_INTR_DMA_DONE)) { ++ writel(1, s3c_mfc_sfr_virt_base + S3C_FIMV_INT_DONE_CLEAR); ++ s3c_mfc_int_type = intReason; ++ wake_up_interruptible(&s3c_mfc_wait_queue); ++ mfc_debug("Interrupt !! : %d\n", intReason); ++ } else ++ mfc_err("Undefined interrupt : %d\n", intReason); ++ ++ writel(1, s3c_mfc_sfr_virt_base + S3C_FIMV_INT_DONE_CLEAR); ++ ++ return IRQ_HANDLED; ++} ++ ++ ++static int s3c_mfc_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ size_t size; ++ int ret; ++ ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (res == NULL) { ++ dev_err(&pdev->dev, "failed to get memory region resource\n"); ++ ret = -ENOENT; ++ goto probe_out; ++ } ++ ++ size = (res->end - res->start) + 1; ++ s3c_mfc_mem = request_mem_region(res->start, size, pdev->name); ++ if (s3c_mfc_mem == NULL) { ++ dev_err(&pdev->dev, "failed to get memory region\n"); ++ ret = -ENOENT; ++ goto probe_out; ++ } ++ ++ s3c_mfc_sfr_virt_base = ioremap(s3c_mfc_mem->start, s3c_mfc_mem->end - s3c_mfc_mem->start + 1); ++ if (s3c_mfc_sfr_virt_base == NULL) { ++ dev_err(&pdev->dev, "failed to ioremap address region\n"); ++ ret = -ENOENT; ++ goto probe_out; ++ } ++ ++ ++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (res == NULL) { ++ dev_err(&pdev->dev, "failed to get irq resource\n"); ++ ret = -ENOENT; ++ goto probe_out; ++ } ++ ++ ret = request_irq(res->start, s3c_mfc_irq, IRQF_DISABLED, pdev->name, pdev); ++ if (ret != 0) { ++ dev_err(&pdev->dev, "failed to install irq (%d)\n", ret); ++ goto probe_out; ++ } ++ ++ mutex_init(&s3c_mfc_mutex); ++ ++ /* ++ * buffer memory secure ++ */ ++ s3c_mfc_phys_data_buf = s3c_get_media_memory(S3C_MDEV_MFC); ++ s3c_mfc_virt_data_buf = ioremap_nocache(s3c_mfc_phys_data_buf, s3c_get_media_memsize(S3C_MDEV_MFC)); ++ ++ /* ++ * firmware load ++ */ ++ s3c_mfc_virt_fw_buf = kmalloc(MFC_FW_BUF_SIZE, GFP_DMA); ++ if (s3c_mfc_virt_fw_buf == NULL) { ++ mfc_err("firmware buffer allocation was failed\n"); ++ ret = -ENOENT; ++ goto probe_out; ++ } ++ ++ if (s3c_mfc_load_firmware() == FALSE){ ++ mfc_err("MFCINST_ERR_FW_INIT_FAIL\n"); ++ ret = -EPERM; ++ goto probe_out; ++ } ++ ++ s3c_mfc_init_inst_no(); ++ ++ s3c_mfc_init_buffer_manager(); ++ ++ ret = misc_register(&s3c_mfc_miscdev); ++ return 0; ++ ++probe_out: ++ dev_err(&pdev->dev, "not found (%d). \n", ret); ++ return ret; ++} ++ ++static int s3c_mfc_remove(struct platform_device *pdev) ++{ ++ kfree((void *)s3c_mfc_virt_fw_buf); ++ ++ iounmap(s3c_mfc_sfr_virt_base); ++ iounmap(s3c_mfc_virt_data_buf); ++ ++ /* remove memory region */ ++ if (s3c_mfc_mem != NULL) { ++ release_resource(s3c_mfc_mem); ++ kfree(s3c_mfc_mem); ++ s3c_mfc_mem = NULL; ++ } ++ ++ free_irq(IRQ_MFC, pdev); ++ ++ mutex_destroy(&s3c_mfc_mutex); ++ ++ misc_deregister(&s3c_mfc_miscdev); ++ ++ return 0; ++} ++ ++static int s3c_mfc_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ return 0; ++} ++ ++static int s3c_mfc_resume(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++static struct platform_driver s3c_mfc_driver = { ++ .probe = s3c_mfc_probe, ++ .remove = s3c_mfc_remove, ++ .shutdown = NULL, ++ .suspend = s3c_mfc_suspend, ++ .resume = s3c_mfc_resume, ++ ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "s3c-mfc", ++ }, ++}; ++ ++static char banner[] __initdata = KERN_INFO "S5PC100 MFC Driver, (c) 2009 Samsung Electronics\n"; ++ ++static int __init s3c_mfc_init(void) ++{ ++ printk(banner); ++ ++ if (platform_driver_register(&s3c_mfc_driver) != 0) { ++ printk(KERN_ERR "platform device registration failed.. \n"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++static void __exit s3c_mfc_exit(void) ++{ ++ platform_driver_unregister( &s3c_mfc_driver); ++ printk("S5PC100 MFC Driver exit.\n"); ++} ++ ++module_init( s3c_mfc_init ); ++module_exit( s3c_mfc_exit ); ++ ++MODULE_AUTHOR("Jiun, Yu"); ++MODULE_AUTHOR("PyoungJae, Jung"); ++MODULE_DESCRIPTION("S3C MFC (Multi Function Codec - FIMV) Device Driver"); ++MODULE_LICENSE("GPL"); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_buffer_manager.c linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_buffer_manager.c +--- linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_buffer_manager.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_buffer_manager.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,434 @@ ++/* ++ * drivers/media/video/samsung/mfc40/s3c_mfc_buffer_manager.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include "s3c_mfc_buffer_manager.h" ++#include "s3c_mfc_errorno.h" ++#include "s3c_mfc_logmsg.h" ++ ++s3c_mfc_alloc_mem_t *s3c_mfc_alloc_mem_head; ++s3c_mfc_alloc_mem_t *s3c_mfc_alloc_mem_tail; ++s3c_mfc_free_mem_t *s3c_mfc_free_mem_head; ++s3c_mfc_free_mem_t *s3c_mfc_free_mem_tail; ++ ++extern dma_addr_t s3c_mfc_phys_data_buf; ++extern unsigned char *s3c_mfc_virt_data_buf; ++ ++ ++/* insert node ahead of s3c_mfc_alloc_mem_head */ ++static void s3c_mfc_insert_node_to_alloc_list(s3c_mfc_alloc_mem_t *node, int inst_no) ++{ ++ mfc_debug("[%d]instance (cached_p_addr : 0x%08x uncached_p_addr : 0x%08x size:%d cacheflag : %d)\n", ++ inst_no, node->cached_p_addr, node->uncached_p_addr, node->size, node->cache_flag); ++ node->next = s3c_mfc_alloc_mem_head; ++ node->prev = s3c_mfc_alloc_mem_head->prev; ++ s3c_mfc_alloc_mem_head->prev->next = node; ++ s3c_mfc_alloc_mem_head->prev = node; ++ s3c_mfc_alloc_mem_head = node; ++} ++ ++void s3c_mfc_print_list(void) ++{ ++ s3c_mfc_alloc_mem_t *node1; ++ s3c_mfc_free_mem_t *node2; ++ int count = 0; ++ unsigned int p_addr; ++ ++ for (node1 = s3c_mfc_alloc_mem_head; node1 != s3c_mfc_alloc_mem_tail; node1 = node1->next) { ++ if(node1->cache_flag) ++ p_addr = node1->cached_p_addr; ++ else ++ p_addr = (unsigned int)node1->uncached_p_addr; ++ ++ printk("s3c_mfc_print_list [AllocList][%d] inst_no : %d p_addr : 0x%08x v_addr:0x%08x size:%d cacheflag : %d\n", ++ count++, node1->inst_no, p_addr, (unsigned int)node1->v_addr, node1->size, node1->cache_flag); ++ ++ } ++ ++ count = 0; ++ for (node2 = s3c_mfc_free_mem_head; node2 != s3c_mfc_free_mem_tail; node2 = node2->next) { ++ printk("s3c_mfc_print_list [FreeList][%d] startAddr : 0x%08x size:%d\n", ++ count++, node2->start_addr , node2->size); ++ } ++} ++ ++int list_count() ++{ ++ int count = 0; ++ s3c_mfc_free_mem_t *node; ++ ++ node = s3c_mfc_free_mem_head; ++ ++ while (node != s3c_mfc_free_mem_tail) { ++ node = node->next; ++ count++; ++ } ++ ++ return count; ++} ++ ++static void s3c_mfc_insert_first_node_to_free_list(s3c_mfc_free_mem_t *node, int inst_no) ++{ ++ mfc_debug("[%d]instance(startAddr : 0x%08x size:%d cached flag : %d)\n", ++ inst_no, node->start_addr, node->size, node->cache_flag); ++ ++ node->next = s3c_mfc_free_mem_head; ++ node->prev = s3c_mfc_free_mem_head->prev; ++ s3c_mfc_free_mem_head->prev->next = node; ++ s3c_mfc_free_mem_head->prev = node; ++ s3c_mfc_free_mem_head = node; ++ ++} ++ ++/* insert node ahead of s3c_mfc_free_mem_head */ ++static void s3c_mfc_insert_node_to_free_list(s3c_mfc_free_mem_t *node, int inst_no) ++{ ++ s3c_mfc_free_mem_t *itr_node; ++ ++ mfc_debug("[%d]instance(startAddr : 0x%08x size:%d cached flag : %d)\n", ++ inst_no, node->start_addr, node->size, node->cache_flag); ++ ++ itr_node = s3c_mfc_free_mem_head; ++ ++ while (itr_node != s3c_mfc_free_mem_tail) { ++ ++ if (itr_node->start_addr >= node->start_addr) { ++ /* head */ ++ if (itr_node == s3c_mfc_free_mem_head) { ++ node->next = s3c_mfc_free_mem_head; ++ node->prev = s3c_mfc_free_mem_head->prev; ++ s3c_mfc_free_mem_head->prev->next = node; ++ s3c_mfc_free_mem_head->prev = node; ++ s3c_mfc_free_mem_head = node; ++ break; ++ } else { /* mid */ ++ node->next = itr_node; ++ node->prev = itr_node->prev; ++ itr_node->prev->next = node; ++ itr_node->prev = node; ++ break; ++ } ++ ++ } ++ ++ itr_node = itr_node->next; ++ } ++ ++ /* tail */ ++ if (itr_node == s3c_mfc_free_mem_tail) { ++ node->next = s3c_mfc_free_mem_tail; ++ node->prev = s3c_mfc_free_mem_tail->prev; ++ s3c_mfc_free_mem_tail->prev->next = node; ++ s3c_mfc_free_mem_tail->prev = node; ++ } ++ ++} ++ ++static void s3c_mfc_del_node_from_alloc_list(s3c_mfc_alloc_mem_t *node, int inst_no) ++{ ++ mfc_debug("[%d]instance (uncached_p_addr : 0x%08x cached_p_addr : 0x%08x size:%d cacheflag : %d)\n", ++ inst_no, node->uncached_p_addr, node->cached_p_addr, node->size, node->cache_flag); ++ ++ if(node == s3c_mfc_alloc_mem_tail){ ++ mfc_info("InValid node\n"); ++ return; ++ } ++ ++ if(node == s3c_mfc_alloc_mem_head) ++ s3c_mfc_alloc_mem_head = node->next; ++ ++ node->prev->next = node->next; ++ node->next->prev = node->prev; ++ ++ kfree(node); ++} ++ ++ ++ ++static void s3c_mfc_del_node_from_free_list( s3c_mfc_free_mem_t *node, int inst_no) ++{ ++ mfc_debug("[%d]s3c_mfc_del_node_from_free_list(startAddr : 0x%08x size:%d)\n", ++ inst_no, node->start_addr, node->size); ++ if(node == s3c_mfc_free_mem_tail){ ++ mfc_err("InValid node\n"); ++ return; ++ } ++ ++ if(node == s3c_mfc_free_mem_head) ++ s3c_mfc_free_mem_head = node->next; ++ ++ node->prev->next = node->next; ++ node->next->prev = node->prev; ++ ++ kfree(node); ++} ++ ++/* Remove Fragmentation in FreeMemList */ ++void s3c_mfc_merge_frag(int inst_no) ++{ ++ s3c_mfc_free_mem_t *node1, *node2; ++ ++ node1 = s3c_mfc_free_mem_head; ++ ++ while (node1 != s3c_mfc_free_mem_tail) { ++ node2 = s3c_mfc_free_mem_head; ++ while (node2 != s3c_mfc_free_mem_tail) { ++ if ((node1->start_addr + node1->size == node2->start_addr) && (node1->cache_flag == node2->cache_flag)) { ++ node1->size += node2->size; ++ mfc_debug("find merge area !! ( node1->start_addr + node1->size == node2->start_addr)\n"); ++ s3c_mfc_del_node_from_free_list(node2, inst_no); ++ break; ++ } else if((node1->start_addr == node2->start_addr + node2->size) && ++ (node1->cache_flag == node2->cache_flag) ) { ++ mfc_debug("find merge area !! ( node1->start_addr == node2->start_addr + node2->size)\n"); ++ node1->start_addr = node2->start_addr; ++ node1->size += node2->size; ++ s3c_mfc_del_node_from_free_list(node2, inst_no); ++ break; ++ } ++ node2 = node2->next; ++ } ++ node1 = node1->next; ++ } ++} ++ ++static unsigned int s3c_mfc_get_mem_area(int allocSize, int inst_no, char cache_flag) ++{ ++ s3c_mfc_free_mem_t *node, *match_node = NULL; ++ unsigned int allocAddr = 0; ++ ++ ++ mfc_debug("request Size : %ld\n", allocSize); ++ ++ if (s3c_mfc_free_mem_head == s3c_mfc_free_mem_tail) { ++ mfc_err("all memory is gone\n"); ++ return(allocAddr); ++ } ++ ++ /* find best chunk of memory */ ++ for (node = s3c_mfc_free_mem_head; node != s3c_mfc_free_mem_tail; node = node->next) { ++ if (match_node != NULL) { ++ if (cache_flag) { ++ if ((node->size >= allocSize) && (node->size < match_node->size) && (node->cache_flag)) ++ match_node = node; ++ } else { ++ if ((node->size >= allocSize) && (node->size < match_node->size) && (!node->cache_flag)) ++ match_node = node; ++ } ++ } else { ++ if (cache_flag) { ++ if ((node->size >= allocSize) && (node->cache_flag)) ++ match_node = node; ++ } else { ++ if ((node->size >= allocSize) && (!node->cache_flag)) ++ match_node = node; ++ } ++ } ++ } ++ ++ if (match_node != NULL) { ++ mfc_debug("match : startAddr(0x%08x) size(%ld) cache flag(%d)\n", ++ match_node->start_addr, match_node->size, match_node->cache_flag); ++ } ++ ++ /* rearange FreeMemArea */ ++ if (match_node != NULL) { ++ allocAddr = match_node->start_addr; ++ match_node->start_addr += allocSize; ++ match_node->size -= allocSize; ++ ++ if(match_node->size == 0) /* delete match_node. */ ++ s3c_mfc_del_node_from_free_list(match_node, inst_no); ++ ++ return(allocAddr); ++ } else { ++ printk("there is no suitable chunk\n"); ++ return 0; ++ } ++ ++ return(allocAddr); ++} ++ ++ ++int s3c_mfc_init_buffer_manager(void) ++{ ++ s3c_mfc_free_mem_t *free_node; ++ s3c_mfc_alloc_mem_t *alloc_node; ++ ++ /* init alloc list, if(s3c_mfc_alloc_mem_head == s3c_mfc_alloc_mem_tail) then, the list is NULL */ ++ alloc_node = (s3c_mfc_alloc_mem_t *)kmalloc(sizeof(s3c_mfc_alloc_mem_t), GFP_KERNEL); ++ memset(alloc_node, 0x00, sizeof(s3c_mfc_alloc_mem_t)); ++ alloc_node->next = alloc_node; ++ alloc_node->prev = alloc_node; ++ s3c_mfc_alloc_mem_head = alloc_node; ++ s3c_mfc_alloc_mem_tail = s3c_mfc_alloc_mem_head; ++ ++ /* init free list, if(s3c_mfc_free_mem_head == s3c_mfc_free_mem_tail) then, the list is NULL */ ++ free_node = (s3c_mfc_free_mem_t *)kmalloc(sizeof(s3c_mfc_free_mem_t), GFP_KERNEL); ++ memset(free_node, 0x00, sizeof(s3c_mfc_free_mem_t)); ++ free_node->next = free_node; ++ free_node->prev = free_node; ++ s3c_mfc_free_mem_head = free_node; ++ s3c_mfc_free_mem_tail = s3c_mfc_free_mem_head; ++ ++ /* init free head node */ ++ free_node = (s3c_mfc_free_mem_t *)kmalloc(sizeof(s3c_mfc_free_mem_t), GFP_KERNEL); ++ memset(free_node, 0x00, sizeof(s3c_mfc_free_mem_t)); ++ free_node->start_addr = s3c_mfc_phys_data_buf; ++ free_node->cache_flag = 0; ++ free_node->size = s3c_get_media_memsize(S3C_MDEV_MFC); ++ s3c_mfc_insert_first_node_to_free_list(free_node, -1); ++ ++ return 0; ++} ++ ++ ++/* Releae cacheable memory */ ++MFC_ERROR_CODE s3c_mfc_release_alloc_mem(s3c_mfc_inst_ctx *MfcCtx, s3c_mfc_args *args) ++{ ++ int ret; ++ ++ s3c_mfc_free_mem_t *free_node; ++ s3c_mfc_alloc_mem_t *node; ++ ++ for(node = s3c_mfc_alloc_mem_head; node != s3c_mfc_alloc_mem_tail; node = node->next) { ++ if(node->u_addr == (unsigned char *)args->mem_free.u_addr) ++ break; ++ } ++ ++ if (node == s3c_mfc_alloc_mem_tail) { ++ mfc_err("invalid virtual address(0x%x)\r\n", args->mem_free.u_addr); ++ ret = MFCINST_MEMORY_INVAILD_ADDR; ++ goto out_releaseallocmem; ++ } ++ ++ free_node = (s3c_mfc_free_mem_t *)kmalloc(sizeof(s3c_mfc_free_mem_t), GFP_KERNEL); ++ ++ if(node->cache_flag) { ++ free_node->start_addr = node->cached_p_addr; ++ free_node->cache_flag = 1; ++ } else { ++ free_node->start_addr = node->uncached_p_addr; ++ free_node->cache_flag = 0; ++ } ++ ++ free_node->size = node->size; ++ s3c_mfc_insert_node_to_free_list(free_node, MfcCtx->InstNo); ++ ++ /* Delete from AllocMem list */ ++ s3c_mfc_del_node_from_alloc_list(node, MfcCtx->InstNo); ++ ++ ret = MFCINST_RET_OK; ++ ++out_releaseallocmem: ++ return ret; ++} ++ ++MFC_ERROR_CODE s3c_mfc_get_phys_addr(s3c_mfc_inst_ctx *MfcCtx, s3c_mfc_args *args) ++{ ++ int ret; ++ s3c_mfc_alloc_mem_t *node; ++ s3c_mfc_get_phys_addr_arg_t *codec_get_phy_addr_arg = (s3c_mfc_get_phys_addr_arg_t *)args; ++ ++ for(node = s3c_mfc_alloc_mem_head; node != s3c_mfc_alloc_mem_tail; node = node->next) { ++ if(node->u_addr == (unsigned char *)codec_get_phy_addr_arg->u_addr) ++ break; ++ } ++ ++ if(node == s3c_mfc_alloc_mem_tail){ ++ mfc_err("invalid virtual address(0x%x)\r\n", codec_get_phy_addr_arg->u_addr); ++ ret = MFCINST_MEMORY_INVAILD_ADDR; ++ goto out_getphysaddr; ++ } ++ ++ if(node->cache_flag == MFC_MEM_CACHED) ++ codec_get_phy_addr_arg->p_addr = node->cached_p_addr; ++ else ++ codec_get_phy_addr_arg->p_addr = node->uncached_p_addr; ++ ++ ret = MFCINST_RET_OK; ++ ++out_getphysaddr: ++ return ret; ++ ++} ++ ++MFC_ERROR_CODE s3c_mfc_get_virt_addr(s3c_mfc_inst_ctx *MfcCtx, s3c_mfc_args *args) ++{ ++ int ret; ++ int inst_no = MfcCtx->InstNo; ++ unsigned int p_startAddr; ++ s3c_mfc_mem_alloc_arg_t *in_param; ++ s3c_mfc_alloc_mem_t *p_allocMem; ++ ++ ++ in_param = (s3c_mfc_mem_alloc_arg_t *)args; ++ ++ /* if user request cachable area, allocate from reserved area */ ++ /* if user request uncachable area, allocate dynamically */ ++ p_startAddr = s3c_mfc_get_mem_area((int)in_param->buff_size, inst_no, in_param->cache_flag); ++ mfc_debug("p_startAddr = 0x%X\n\r", p_startAddr); ++ ++ if (!p_startAddr) { ++ mfc_debug("There is no more memory\n\r"); ++ in_param->out_addr = -1; ++ ret = MFCINST_MEMORY_ALLOC_FAIL; ++ goto out_getcodecviraddr; ++ } ++ ++ p_allocMem = (s3c_mfc_alloc_mem_t *)kmalloc(sizeof(s3c_mfc_alloc_mem_t), GFP_KERNEL); ++ memset(p_allocMem, 0x00, sizeof(s3c_mfc_alloc_mem_t)); ++ ++ if (in_param->cache_flag == MFC_MEM_CACHED) { ++ p_allocMem->cached_p_addr = p_startAddr; ++ p_allocMem->v_addr = s3c_mfc_virt_data_buf + (p_allocMem->cached_p_addr - s3c_mfc_phys_data_buf); ++ p_allocMem->u_addr = (unsigned char *)(in_param->cached_mapped_addr + ++ (p_allocMem->cached_p_addr - s3c_mfc_phys_data_buf)); ++ ++ if (p_allocMem->v_addr == NULL) { ++ mfc_debug("Mapping Failed [PA:0x%08x]\n\r", p_allocMem->cached_p_addr); ++ ret = MFCINST_MEMORY_MAPPING_FAIL; ++ goto out_getcodecviraddr; ++ } ++ } else { ++ p_allocMem->uncached_p_addr = p_startAddr; ++ p_allocMem->v_addr = s3c_mfc_virt_data_buf + (p_allocMem->uncached_p_addr - s3c_mfc_phys_data_buf); ++ p_allocMem->u_addr = (unsigned char *)(in_param->non_cached_mapped_addr + ++ (p_allocMem->uncached_p_addr - s3c_mfc_phys_data_buf)); ++ mfc_debug("in_param->non_cached_mapped_addr = 0x%X, s3c_mfc_phys_data_buf = 0x%X, data buffer size = 0x%X\n", ++ in_param->non_cached_mapped_addr, s3c_mfc_phys_data_buf, s3c_get_media_memsize(S3C_MDEV_MFC)); ++ if (p_allocMem->v_addr == NULL) { ++ mfc_debug("Mapping Failed [PA:0x%08x]\n\r", p_allocMem->uncached_p_addr); ++ ret = MFCINST_MEMORY_MAPPING_FAIL; ++ goto out_getcodecviraddr; ++ } ++ } ++ ++ in_param->out_addr = (unsigned int)p_allocMem->u_addr; ++ mfc_debug("u_addr : 0x%x v_addr : 0x%x cached_p_addr : 0x%x, uncached_p_addr : 0x%x\n", ++ p_allocMem->u_addr, p_allocMem->v_addr, p_allocMem->cached_p_addr, p_allocMem->uncached_p_addr); ++ ++ p_allocMem->size = (int)in_param->buff_size; ++ p_allocMem->inst_no = inst_no; ++ p_allocMem->cache_flag = in_param->cache_flag; ++ ++ s3c_mfc_insert_node_to_alloc_list(p_allocMem, inst_no); ++ ret = MFCINST_RET_OK; ++ ++out_getcodecviraddr: ++ return ret; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_buffer_manager.h linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_buffer_manager.h +--- linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_buffer_manager.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_buffer_manager.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,55 @@ ++/* ++ * drivers/media/video/samsung/mfc40/s3c_mfc_buffer_manager.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_MFC_BUFFER_MANAGER_H_ ++#define _S3C_MFC_BUFFER_MANAGER_H_ ++ ++#include "s3c_mfc_interface.h" ++#include "s3c_mfc_common.h" ++ ++ ++typedef struct tag_alloc_mem_t ++{ ++ struct tag_alloc_mem_t *prev; ++ struct tag_alloc_mem_t *next; ++ union { ++ unsigned int cached_p_addr; /* physical address of cacheable area */ ++ unsigned int uncached_p_addr; /* physical address of non-cacheable area */ ++ }; ++ unsigned char *v_addr; /* virtual address in cached area */ ++ unsigned char *u_addr; /* copyed virtual address for user mode process */ ++ int size; /* memory size */ ++ int inst_no; ++ char cache_flag; ++} s3c_mfc_alloc_mem_t; ++ ++ ++typedef struct tag_free_mem_t ++{ ++ struct tag_free_mem_t *prev; ++ struct tag_free_mem_t *next; ++ unsigned int start_addr; ++ unsigned int size; ++ char cache_flag; ++} s3c_mfc_free_mem_t; ++ ++int list_count(void); ++void s3c_mfc_print_list(void); ++int s3c_mfc_init_buffer_manager(void); ++void s3c_mfc_merge_frag(int inst_no); ++MFC_ERROR_CODE s3c_mfc_release_alloc_mem(s3c_mfc_inst_ctx *MfcCtx, s3c_mfc_args *args); ++MFC_ERROR_CODE s3c_mfc_get_phys_addr(s3c_mfc_inst_ctx *MfcCtx, s3c_mfc_args *args); ++MFC_ERROR_CODE s3c_mfc_get_virt_addr(s3c_mfc_inst_ctx *MfcCtx, s3c_mfc_args *args); ++ ++#endif /* _S3C_MFC_BUFFER_MANAGER_H_ */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_common.c linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_common.c +--- linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_common.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_common.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,213 @@ ++/* ++ * drivers/media/video/samsung/mfc40/s3c_mfc_common.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++ ++#include ++ ++#include "s3c_mfc_common.h" ++#include "s3c_mfc_interface.h" ++#include "s3c_mfc_memory.h" ++#include "s3c_mfc_logmsg.h" ++#include "s3c_mfc_fw.h" ++ ++static int s3c_mfc_inst_no[MFC_MAX_INSTANCE_NUM]; ++ ++unsigned int s3c_mfc_get_codec_type(MFC_CODEC_TYPE codec_type) ++{ ++ unsigned int standardSel = 0; ++ ++ switch(codec_type) { ++ case MPEG4_DEC: ++ case DIVX_DEC: ++ case XVID_DEC: ++ standardSel = ((0 << 4) | (0 << 0)); ++ break; ++ ++ case H263_ENC: ++ case MPEG4_ENC: ++ standardSel = ((1 << 4) | (0 << 0)); ++ break; ++ ++ case H264_DEC: ++ standardSel = ((0 << 4) | (1 << 0)); ++ break; ++ ++ case H264_ENC: ++ standardSel = ((1 << 4) | (1 << 0)); ++ break; ++ ++ case H263_DEC: ++ standardSel = ((0 << 4) | (4 << 0)); ++ break; ++ ++ case MPEG2_DEC: ++ standardSel = ((0 << 4) | (5 << 0)); ++ break; ++ ++ case VC1_DEC: ++ standardSel = ((0 << 4) | ( 6 << 0)); ++ break; ++ ++ default: ++ break; ++ } ++ ++ return standardSel; ++ ++} ++ ++int s3c_mfc_get_fw_buf_offset(MFC_CODEC_TYPE codecType) ++{ ++ int offset; ++ ++ switch(codecType) { ++ case MPEG4_ENC: ++ case H263_ENC: ++ offset = 0; ++ break; ++ ++ case DIVX_DEC: ++ case XVID_DEC: ++ case MPEG4_DEC: ++ offset = FIRMWARE_CODE_SIZE; ++ break; ++ ++ case H264_ENC: ++ offset = 2 * FIRMWARE_CODE_SIZE; ++ break; ++ ++ case H264_DEC: ++ offset = 3 * FIRMWARE_CODE_SIZE; ++ break; ++ ++ case VC1_DEC: ++ offset = 4 * FIRMWARE_CODE_SIZE; ++ break; ++ ++ case MPEG2_DEC: ++ offset = 5 * FIRMWARE_CODE_SIZE; ++ break; ++ ++ case H263_DEC: ++ offset = 6 * FIRMWARE_CODE_SIZE; ++ break; ++ ++ case COM_CTRL: ++ offset = 7 * FIRMWARE_CODE_SIZE; ++ break; ++ ++ default: ++ offset = -1; ++ mfc_err("unknown codec type\n"); ++ } ++ ++ return offset; ++} ++ ++int s3c_mfc_get_fw_buf_size(MFC_CODEC_TYPE codecType) ++{ ++ int bufSize; ++ ++ switch(codecType) { ++ case MPEG4_ENC: ++ case H263_ENC: ++ bufSize = sizeof(mp4_enc_mc_fw); ++ break; ++ ++ case DIVX_DEC: ++ case XVID_DEC: ++ case MPEG4_DEC: ++ bufSize = sizeof(mp4_dec_mc_fw); ++ break; ++ ++ case H264_ENC: ++ bufSize = sizeof(h264_enc_mc_fw); ++ break; ++ ++ case H264_DEC: ++ bufSize = sizeof(h264_dec_mc_fw); ++ break; ++ ++ case VC1_DEC: ++ bufSize = sizeof(vc1_dec_mc_fw); ++ break; ++ ++ case MPEG2_DEC: ++ bufSize = sizeof(mp2_dec_mc_fw); ++ break; ++ ++ case H263_DEC: ++ bufSize = sizeof(h263_dec_mc_fw); ++ break; ++ ++ case COM_CTRL: ++ bufSize = sizeof(cmd_ctrl_fw); ++ break; ++ ++ default: bufSize = -1; ++ mfc_err("unknown codec type\n"); ++ } ++ ++ return bufSize; ++} ++ ++void s3c_mfc_init_inst_no(void) ++{ ++ memset(&s3c_mfc_inst_no, 0x00, sizeof(s3c_mfc_inst_no)); ++} ++ ++int s3c_mfc_get_inst_no(void) ++{ ++ unsigned int i; ++ ++ for(i = 0; i < MFC_MAX_INSTANCE_NUM; i++) ++ if (s3c_mfc_inst_no[i] == 0) { ++ s3c_mfc_inst_no[i] = 1; ++ return i; ++ } ++ ++ return -1; ++} ++ ++ ++void s3c_mfc_return_inst_no(int inst_no) ++{ ++ if ((inst_no >= 0) && (inst_no < MFC_MAX_INSTANCE_NUM)) ++ s3c_mfc_inst_no[inst_no] = 0; ++ ++} ++ ++ ++BOOL s3c_mfc_is_running(void) ++{ ++ unsigned int i; ++ BOOL ret = FALSE; ++ ++ for(i = 1; i < MFC_MAX_INSTANCE_NUM; i++) ++ if(s3c_mfc_inst_no[i] == 1) ++ ret = TRUE; ++ ++ return ret; ++} ++ ++int s3c_mfc_set_state(s3c_mfc_inst_ctx *ctx, s3c_mfc_inst_state state) ++{ ++ ++ if(ctx->MfcState > state) ++ return 0; ++ ++ ctx->MfcState = state; ++ return 1; ++ ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_common.h linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_common.h +--- linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_common.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_common.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,114 @@ ++/* ++ * drivers/media/video/samsung/mfc40/s3c_mfc_common.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_MFC_COMMON_H_ ++#define _S3C_MFC_COMMON_H_ ++ ++#include ++ ++#include "s3c_mfc_interface.h" ++ ++#define BUF_ALIGN_UNIT (64) ++#define Align(x, alignbyte) (((x)+(alignbyte)-1)/(alignbyte)*(alignbyte)) ++ ++typedef enum ++{ ++ MFCINST_STATE_NULL = 0, ++ ++ /* Instance is created */ ++ MFCINST_STATE_OPENED = 10, ++ ++ /* channel_set and init_codec is completed */ ++ MFCINST_STATE_DEC_INITIALIZE = 20, ++ ++ /* seq_start is completed */ ++ MFCINST_STATE_DEC_SEQ_START = 30, ++ ++ MFCINST_STATE_DEC_EXE, ++ MFCINST_STATE_DEC_EXE_DONE, ++ ++ /* Instance is initialized for encoding */ ++ MFCINST_STATE_ENC_INITIALIZE = 40, ++ MFCINST_STATE_ENC_EXE, ++ MFCINST_STATE_ENC_EXE_DONE ++} s3c_mfc_inst_state; ++ ++typedef enum ++{ ++ MEM_STRUCT_LINEAR = 0, ++ MEM_STRUCT_TILE_ENC = 2, /* 16x16 */ ++ MEM_STRUCT_TILE_DEC = 3 /* 64x32 */ ++} s3c_mfc_mem_type; ++ ++typedef enum ++{ ++ MFC_POLLING_DMA_DONE = 1, ++ MFC_POLLING_HEADER_DONE = 2, ++ MFC_POLLING_OPERATION_DONE = 3, ++ MFC_POLLING_FW_DONE = 4, ++ MFC_INTR_FW_DONE = (1 << 5), ++ MFC_INTR_DMA_DONE = (1 << 7), ++ MFC_INTR_FRAME_DONE = (1 << 8), ++ MFC_INTR_FRAME_FW_DONE = ((1 << 8) | (1 << 5)) ++} s3c_mfc_wait_done_type; ++ ++ ++typedef enum ++{ ++ DECODING_ONLY = 0, ++ DECODING_DISPLAY = 1, ++ DISPLAY_ONLY = 2 ++} s3c_mfc_display_status; ++ ++typedef enum ++{ ++ MFC_RET_FRAME_NOT_SET = -1, ++ MFC_RET_FRAME_NOT_CODED = 0, ++ MFC_RET_FRAME_I_FRAME = 1, ++ MFC_RET_FRAME_P_FRAME = 2, ++ MFC_RET_FRAME_B_FRAME = 3 ++} s3c_mfc_frame_type; ++ ++typedef struct tag_mfc_inst_ctx ++{ ++ unsigned int MfcSfr[S3C_FIMV_REG_COUNT]; ++ ++ int InstNo; ++ unsigned int DPBCnt; ++ unsigned int totalDPBCnt; ++ unsigned int extraDPB; ++ unsigned int displayDelay; ++ unsigned int postEnable; ++ unsigned int endOfFrame; ++ unsigned int forceSetFrameType; ++ unsigned int img_width; ++ unsigned int img_height; ++ unsigned int dwAccess; // for Power Management. ++ unsigned int IsPackedPB; ++ ++ s3c_mfc_frame_type FrameType; ++ MFC_CODEC_TYPE MfcCodecType; ++ s3c_mfc_inst_state MfcState; ++} s3c_mfc_inst_ctx; ++ ++unsigned int s3c_mfc_get_codec_type(MFC_CODEC_TYPE codec_type); ++int s3c_mfc_get_fw_buf_offset(MFC_CODEC_TYPE codecType); ++int s3c_mfc_get_fw_buf_size(MFC_CODEC_TYPE codecType); ++int s3c_mfc_wait_for_done(s3c_mfc_wait_done_type command); ++void s3c_mfc_init_inst_no(void); ++int s3c_mfc_get_inst_no(void); ++void s3c_mfc_return_inst_no(int inst_no); ++int s3c_mfc_set_state(s3c_mfc_inst_ctx *ctx, s3c_mfc_inst_state state); ++ ++#endif /* _S3C_MFC_COMMON_H_ */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_errorno.h linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_errorno.h +--- linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_errorno.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_errorno.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,71 @@ ++/* ++ * drivers/media/video/samsung/mfc40/s3c_mfc_errorno.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_MFC_ERRORNO_H_ ++#define _S3C_MFC_ERRORNO_H_ ++ ++typedef enum ++{ ++ MFCINST_RET_OK = 1, ++ MFCINST_ERR_INVALID_PARAM = -1001, ++ MFCINST_ERR_STATE_INVALID = -1002, ++ MFCINST_ERR_POWER_OFF = -1003, ++ MFCINST_ERR_WRONG_CODEC_MODE = -1004, ++ MFCINST_ERR_INIT_FAIL = -1005, ++ MFCINST_ERR_FILE_OPEN_FAIL = -1006, ++ MFCINST_ERR_INTR_TIME_OUT = -1007, ++ MFCINST_ERR_INTR_INIT_FAIL = -1008, ++ ++ ++ MFCINST_ERR_DEC_INIT_CMD_FAIL = -2001, ++ MFCINST_ERR_DEC_HEADER_DECODE_FAIL = -2002, ++ MFCINST_ERR_DEC_DECODE_CMD_FAIL = -2003, ++ MFCINST_ERR_DEC_DECODE_DONE_FAIL = -2004, ++ MFCINST_ERR_DEC_INVALID_STRM = -2005, ++ MFCINST_ERR_DEC_STRM_SIZE_INVALID = -2006, ++ ++ MFCINST_ERR_ENC_INIT_CMD_FAIL = -3001, ++ MFCINST_ERR_ENC_ENCODE_CMD_FAIL = -3002, ++ MFCINST_ERR_ENC_ENCODE_DONE_FAIL = -3003, ++ MFCINST_ERR_ENC_PARAM_INVALID_VALUE = -3004, ++ ++ MFCINST_ERR_STRM_BUF_INVALID = -4001, ++ MFCINST_ERR_FRM_BUF_INVALID = -4002, ++ MFCINST_ERR_FRM_BUF_SIZE = -4003, ++ ++ MFCINST_ERR_FW_LOAD_FAIL = -5001, ++ MFCINST_ERR_FW_MEMORY_INVALID = -5002, ++ MFCINST_ERR_FW_DMA_SET_FAIL = -5003, ++ MFCINST_ERR_FW_INIT_FAIL = -5004, ++ MFCINST_ERR_SEQ_START_FAIL = -5005, ++ ++ MFCINST_INST_NUM_INVALID = -6001, ++ MFCINST_INST_NUM_EXCEEDED = -6002, ++ MFCINST_ERR_SET_CONF = -6003, ++ ++ ++ MFCINST_MEMORY_ALLOC_FAIL = -8001, ++ MFCINST_MUTEX_CREATE_FAIL = -8002, ++ MFCINST_POWER_INIT_FAIL = -8003, ++ MFCINST_POWER_ON_OFF_FAIL = -8004, ++ MFCINST_POWER_STATE_INVALID = -8005, ++ MFCINST_POWER_MANAGER_ERR = -8006, ++ ++ MFCINST_MEMORY_INVAILD_ADDR = -8101, ++ MFCINST_MEMORY_MAPPING_FAIL = -8102, ++ ++ MFCAPI_RET_FAIL = -9001, ++} MFC_ERROR_CODE; ++ ++#endif /* _S3C_MFC_ERRORNO_H_ */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_fw.h linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_fw.h +--- linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_fw.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_fw.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,27 @@ ++/* ++ * drivers/media/video/samsung/mfc40/s3c_mfc_fw.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_MFC_FW_H_ ++#define _S3C_MFC_FW_H_ ++ ++extern unsigned char mp4_dec_mc_fw[26148]; ++extern unsigned char mp4_enc_mc_fw[11628]; ++extern unsigned char h264_dec_mc_fw[39296]; ++extern unsigned char h264_enc_mc_fw[21180]; ++extern unsigned char h263_dec_mc_fw[9672]; ++extern unsigned char mp2_dec_mc_fw[14636]; ++extern unsigned char vc1_dec_mc_fw[22652]; ++extern unsigned char cmd_ctrl_fw[7432] ; ++ ++#endif /* _S3C_MFC_FW_H_ */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_interface.h linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_interface.h +--- linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_interface.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_interface.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,323 @@ ++/* ++ * drivers/media/video/samsung/mfc40/s3c_mfc_interface.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_MFC_INTERFACE_H_ ++#define _S3C_MFC_INTERFACE_H_ ++ ++#include "s3c_mfc_errorno.h" ++ ++#define IOCTL_MFC_DEC_INIT (0x00800001) ++#define IOCTL_MFC_ENC_INIT (0x00800002) ++#define IOCTL_MFC_DEC_EXE (0x00800003) ++#define IOCTL_MFC_ENC_EXE (0x00800004) ++#define IOCTL_MFC_DEC_SEQ_START (0x00800005) ++ ++#define IOCTL_MFC_REQ_BUF (0x00800010) ++#define IOCTL_MFC_FREE_BUF (0x00800011) ++#define IOCTL_MFC_GET_PHYS_ADDR (0x00800012) ++ ++#define IOCTL_MFC_SET_CONFIG (0x00800101) ++#define IOCTL_MFC_GET_CONFIG (0x00800102) ++ ++#define MFC_CODEC_TYPE_ISENC(x) ((x) & (0x100)) ++#define MFC_CODEC_TYPE_ISDEC(x) ((x) & (0x200)) ++ ++/* MFC H/W support maximum 15 extra DPB. */ ++#define MFC_MAX_EXTRA_DPB (5) ++ ++typedef enum ++{ ++ UNKNOWN_TYPE = 0x0, ++ COM_CTRL = 0x001, ++ MPEG4_ENC = 0x100, ++ H263_ENC, ++ H264_ENC, ++ ++ MPEG4_DEC = 0x200, ++ H264_DEC, ++ H263_DEC, ++ MPEG2_DEC, ++ DIVX_DEC, ++ XVID_DEC, ++ VC1_DEC ++} MFC_CODEC_TYPE; ++ ++typedef enum ++{ ++ DONT_CARE = 0, /* (0<<1)|(0<<0) */ ++ I_FRAME = 1, /* (0<<1)|(1<<0) */ ++ NOT_CODED = 2 /* (1<<1)|(0<<0) */ ++} MFC_FORCE_SET_FRAME_TYPE; ++ ++typedef enum ++{ ++ MFC_DEC_SETCONF_POST_ENABLE = 1, ++ MFC_DEC_SETCONF_EXTRA_BUFFER_NUM, ++ MFC_DEC_SETCONF_DISPLAY_DELAY, ++ MFC_DEC_SETCONF_IS_LAST_FRAME, ++ MFC_DEC_GETCONF_IMG_RESOLUTION, ++ MFC_DEC_GETCONF_PHYS_ADDR ++}SSBSIP_MFC_DEC_CONF; ++ ++typedef enum ++{ ++ MFC_ENC_SETCONF_FRAME_TYPE = 100, ++}SSBSIP_MFC_ENC_CONF; ++ ++/* but, due to lack of memory, MFC driver use 5 as maximum */ ++#define MFC_MEM_NONCACHED 0 ++#define MFC_MEM_CACHED 1 ++ ++typedef struct { ++ MFC_CODEC_TYPE in_codec_type; /* [IN] codec type */ ++ unsigned int in_dpb_addr; /* [IN] DPB buffer address */ ++ int in_width; /* [IN] width of YUV420 frame to be encoded */ ++ int in_height; /* [IN] height of YUV420 frame to be encoded */ ++ int in_profile_level; /* [IN] profile & level */ ++ int in_gop_num; /* [IN] GOP Number (interval of I-frame) */ ++ int in_vop_quant; /* [IN] VOP quant */ ++ ++ int in_RC_enable; /* [IN] RC enable (0:disable, 1:frame level RC) */ ++ int in_RC_framerate; /* [IN] RC parameter (framerate) */ ++ int in_RC_bitrate; /* [IN] RC parameter (bitrate in kbps) */ ++ int in_RC_qbound; /* [IN] RC parameter (Q bound) */ ++ int in_RC_rpara; /* [IN] RC parameter (Reaction Coefficient) */ ++ ++ /* [IN] MB level rate control dark region adaptive feature */ ++ int in_RC_mb_dark_disable; /* (0:enable,1:disable) */ ++ /* [IN] MB level rate control smooth region adaptive feature */ ++ int in_RC_mb_smooth_disable; /* (0:enable,1:disable) */ ++ /* [IN] MB level rate control static region adaptive feature */ ++ int in_RC_mb_static_disable; /* (0:enable,1:disable) */ ++ /* [IN] MB level rate control activity region adaptive feature */ ++ int in_RC_mb_activity_disable; /* (0:enable,1:disable) */ ++ ++ int in_MS_mode; /* [IN] Multi-slice mode (0:single, 1:multiple) */ ++ int in_MS_size_mode; /* [IN] Multislice size mode(0:mb number,1:byte) */ ++ int in_MS_size; /* [IN] Multi-slice size (in num. of mb or byte) */ ++ ++ int in_mb_refresh; /* [IN] Macroblock refresh */ ++ ++} s3c_mfc_enc_init_mpeg4_arg_t; ++ ++typedef s3c_mfc_enc_init_mpeg4_arg_t s3c_mfc_enc_init_h263_arg_t; ++ ++typedef struct { ++ MFC_CODEC_TYPE in_codec_type; /* [IN] codec type */ ++ unsigned int in_dpb_addr; /* [IN] DPB buffer address */ ++ int in_width; /* [IN] width of YUV420 frame to be encoded */ ++ int in_height; /* [IN] height of YUV420 frame to be encoded */ ++ int in_profile_level; /* [IN] profile & level */ ++ int in_gop_num; /* [IN] GOP Number (interval of I-frame) */ ++ int in_vopQuant; /* [IN] VOP quant */ ++ ++ /* [IN] RC enable */ ++ int in_RC_enable; /* (0:disable,1:MB level RC,2:frame level RC) */ ++ int in_RC_framerate; /* [IN] RC parameter (framerate) */ ++ int in_RC_bitrate; /* [IN] RC parameter (bitrate in kbps) */ ++ int in_RC_qbound; /* [IN] RC parameter (Q bound) */ ++ int in_RC_rpara; /* [IN] RC parameter (Reaction Coefficient) */ ++ ++ /* [IN] MB level rate control dark region adaptive feature */ ++ int in_RC_mb_dark_disable; /* (0:enable, 1:disable) */ ++ /* [IN] MB level rate control smooth region adaptive feature */ ++ int in_RC_mb_smooth_disable; /* (0:enable, 1:disable) */ ++ /* [IN] MB level rate control static region adaptive feature */ ++ int in_RC_mb_static_disable; /* (0:enable, 1:disable) */ ++ /* [IN] MB level rate control activity region adaptive feature */ ++ int in_RC_mb_activity_disable; /* (0:enable, 1:disable) */ ++ ++ int in_MS_mode; /* [IN] Multi-slice mode (0:single, 1:multiple) */ ++ int in_MS_size_mode; /* [IN] Multi-slice size mode(0:mb number,1:byte)*/ ++ int in_MS_size; /* [IN] Multi-slice size (in num. of mb or byte) */ ++ ++ int in_mb_refresh; /* [IN] Macroblock refresh */ ++ ++ /* [IN] ( 0 : CAVLC, 1 : CABAC ) */ ++ int in_symbolmode; ++ /* [IN] model number for fixed decision for inter slices (0,1,2) */ ++ int in_model_number; ++ /* [IN] disable deblocking filter idc */ ++ int in_deblock_filt; /* (0: all,1: disable,2: except slice boundary) */ ++ /* [IN] slice alpha C0 offset of deblocking filter */ ++ int in_deblock_alpha_C0; ++ /* [IN] slice beta offset of deblocking filter */ ++ int in_deblock_beta; ++ ++} s3c_mfc_enc_init_h264_arg_t; ++ ++typedef struct { ++ MFC_CODEC_TYPE in_codec_type; /* [IN] codec type */ ++ unsigned int in_Y_addr; /*[IN]In-buffer addr of Y component */ ++ unsigned int in_CbCr_addr;/*[IN]In-buffer addr of CbCr component */ ++ unsigned int in_strm_st; /*[IN]Out-buffer start addr of encoded strm*/ ++ unsigned int in_strm_end; /*[IN]Out-buffer end addr of encoded strm */ ++ unsigned int out_frame_type; /* [OUT] frame type */ ++ int out_encoded_size; /* [OUT] Length of Encoded video stream */ ++ int out_header_size; /* [OUT] Length of video stream header */ ++} s3c_mfc_enc_exe_arg; ++ ++typedef struct { ++ MFC_CODEC_TYPE in_codec_type; /* [IN] codec type */ ++ int in_strm_buf; /* [IN] the physical address of STRM_BUF */ ++ int in_strm_size; /* [IN] Size of video stream filled in STRM_BUF */ ++ ++ /* [IN] Is packed PB frame or not, 1: packedPB 0: unpacked */ ++ int in_packed_PB; ++ ++ int out_img_width; /* [OUT] width of YUV420 frame */ ++ int out_img_height; /* [OUT] height of YUV420 frame */ ++ int out_buf_width; /* [OUT] width of YUV420 frame */ ++ int out_buf_height; /* [OUT] height of YUV420 frame */ ++ ++ /* [OUT] the number of buffers which is nessary during decoding. */ ++ int out_dpb_cnt; ++} s3c_mfc_dec_init_arg_t; ++ ++typedef struct { ++ MFC_CODEC_TYPE in_codec_type; /* [IN] codec type */ ++ int in_strm_buf; /* [IN] the physical address of STRM_BUF */ ++ int in_strm_size; /* [IN] Size of video stream filled in STRM_BUF */ ++ int in_frm_buf; /* [IN] the address of STRM_BUF */ ++ int in_frm_size; /* [IN] Size of video stream filled in STRM_BUF */ ++} s3c_mfc_dec_seq_start_arg_t; ++ ++typedef struct { ++ MFC_CODEC_TYPE in_codec_type; /* [IN] codec type */ ++ int in_strm_buf; /* [IN] the physical address of STRM_BUF */ ++ int in_strm_size; /* [IN] Size of video stream filled in STRM_BUF */ ++ ++ /* [IN] Is packed PB frame or not, 1: packedPB 0: unpacked */ ++ int in_packed_PB; ++ ++ int out_img_width; /* [OUT] width of YUV420 frame */ ++ int out_img_height; /* [OUT] height of YUV420 frame */ ++ int out_buf_width; /* [OUT] width of YUV420 frame */ ++ int out_buf_height; /* [OUT] height of YUV420 frame */ ++ ++ /* [OUT] the number of buffers which is nessary during decoding. */ ++ int out_dpb_cnt; ++ ++ int in_frm_buf; /* [IN] the address of STRM_BUF */ ++ int in_frm_size; /* [IN] Size of video stream filled in STRM_BUF */ ++ ++ char in_cache_flag; ++ //int in_buff_size; ++ unsigned int in_cached_mapped_addr; ++ unsigned int in_non_cached_mapped_addr; ++ unsigned int out_u_addr; ++ ++ unsigned int out_p_addr; ++ ++ int out_frame_buf_size; ++} s3c_mfc_dec_super_init_arg_t; ++ ++typedef struct { ++ MFC_CODEC_TYPE in_codec_type;/* [IN] codec type */ ++ int in_strm_buf; /* [IN] the physical address of STRM_BUF */ ++ int in_strm_size; /* [IN] Size of video stream filled in STRM_BUF */ ++ int in_frm_buf; /* [IN] the address of STRM_BUF */ ++ int in_frm_size; /* [IN] Size of video stream filled in STRM_BUF */ ++ int out_display_Y_addr; /* [OUT] the physical address of display buf */ ++ int out_display_C_addr; /* [OUT] the physical address of display buf */ ++ ++ /* ++ * [OUT] whether display frame exist or not. ++ * (0:no more frame, 1:frame exist) ++ */ ++ int out_display_status; ++} s3c_mfc_dec_exe_arg_t; ++ ++typedef struct { ++ int in_config_param; /* [IN] Configurable parameter type */ ++ ++ /* [IN] Values to get for the configurable parameter. */ ++ int out_config_value[2]; ++ /* Maximum two integer values can be obtained; */ ++} s3c_mfc_get_config_arg_t; ++ ++typedef struct { ++ int in_config_param; /* [IN] Configurable parameter type */ ++ ++ /* [IN] Values to be set for the configurable parameter. */ ++ int in_config_value[2]; ++ /* Maximum two integer values can be set. */ ++ ++ /* [OUT] Old values of the configurable parameters */ ++ int out_config_value_old[2]; ++} s3c_mfc_set_config_arg_t; ++ ++typedef struct tag_get_phys_addr_arg ++{ ++ unsigned int u_addr; ++ unsigned int p_addr; ++} s3c_mfc_get_phys_addr_arg_t; ++ ++typedef struct tag_mem_alloc_arg ++{ ++ char cache_flag; ++ int buff_size; ++ unsigned int cached_mapped_addr; ++ unsigned int non_cached_mapped_addr; ++ unsigned int out_addr; ++} s3c_mfc_mem_alloc_arg_t; ++ ++typedef struct tag_mem_free_arg_t ++{ ++ unsigned int u_addr; ++} s3c_mfc_mem_free_arg_t; ++ ++typedef union { ++ s3c_mfc_enc_init_mpeg4_arg_t enc_init_mpeg4; ++ s3c_mfc_enc_init_h263_arg_t enc_init_h263; ++ s3c_mfc_enc_init_h264_arg_t enc_init_h264; ++ ++ s3c_mfc_enc_exe_arg enc_exe; ++ s3c_mfc_dec_init_arg_t dec_init; ++ s3c_mfc_dec_seq_start_arg_t dec_seq_start; ++ s3c_mfc_dec_super_init_arg_t dec_super_init; ++ s3c_mfc_dec_exe_arg_t dec_exe; ++ s3c_mfc_get_config_arg_t get_config; ++ s3c_mfc_set_config_arg_t set_config; ++ ++ s3c_mfc_mem_alloc_arg_t mem_alloc; ++ s3c_mfc_mem_free_arg_t mem_free; ++ s3c_mfc_get_phys_addr_arg_t get_phys_addr; ++} s3c_mfc_args; ++ ++typedef struct tag_mfc_args{ ++ MFC_ERROR_CODE ret_code; /* [OUT] error code */ ++ s3c_mfc_args args; ++} s3c_mfc_common_args; ++ ++#define ENC_PROFILE_LEVEL(profile, level) ((profile) | ((level) << 8)) ++ ++#define ENC_PROFILE_MPEG4_SP 0 ++#define ENC_PROFILE_MPEG4_ASP 1 ++#define ENC_PROFILE_H264_BP 0 ++#define ENC_PROFILE_H264_MAIN 1 ++#define ENC_PROFILE_H264_HIGH 2 ++ ++ ++#define ENC_RC_DISABLE 0 ++#define ENC_RC_ENABLE_MACROBLOCK 1 ++#define ENC_RC_ENABLE_FRAME 2 ++ ++#define ENC_RC_QBOUND(min_qp, max_qp) ((min_qp) | ((max_qp) << 8)) ++#define ENC_RC_MB_CTRL_DARK_DISABLE (1 << 3) ++#define ENC_RC_MB_CTRL_SMOOTH_DISABLE (1 << 2) ++#define ENC_RC_MB_CTRL_STATIC_DISABLE (1 << 1) ++#define ENC_RC_MB_CTRL_ACTIVITY_DISABLE (1 << 0) ++ ++ ++#endif /* _S3C_MFC_INTERFACE_H_ */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_intr.c linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_intr.c +--- linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_intr.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_intr.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,96 @@ ++/* ++ * drivers/media/video/samsung/mfc40/s3c_mfc_intr.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "s3c_mfc_intr.h" ++#include "s3c_mfc_logmsg.h" ++#include "s3c_mfc_common.h" ++#include "s3c_mfc_types.h" ++#include "s3c_mfc_memory.h" ++ ++extern wait_queue_head_t s3c_mfc_wait_queue; ++extern unsigned int s3c_mfc_int_type; ++ ++extern void __iomem *s3c_mfc_sfr_virt_base; ++ ++static int s3c_mfc_wait_polling(unsigned int PollingRegAddress) ++{ ++ int i; ++ volatile unsigned int uRegData=0; ++ unsigned int waitLoop = 1000; /* 1000msec */ ++ ++ ++ for (i = 0; (i < waitLoop) && (uRegData == 0) ;i++) { ++ mdelay(1); ++ uRegData = readl(s3c_mfc_sfr_virt_base + PollingRegAddress); ++ } ++ ++ if (uRegData == 0) { ++ mfc_err("Polling Time Out(Reg : 0x%x)\n", PollingRegAddress); ++ return 0; ++ } ++ ++ return 1; ++ ++} ++ ++int s3c_mfc_wait_for_done(s3c_mfc_wait_done_type command) ++{ ++ unsigned int retVal = 1; ++ ++ switch(command){ ++ case MFC_POLLING_DMA_DONE : ++ retVal = s3c_mfc_wait_polling(S3C_FIMV_DONE_M); ++ break; ++ ++ case MFC_POLLING_HEADER_DONE : ++ retVal = s3c_mfc_wait_polling(S3C_FIMV_HEADER_DONE); ++ break; ++ ++ case MFC_POLLING_OPERATION_DONE : ++ retVal = s3c_mfc_wait_polling(S3C_FIMV_OPERATION_DONE); ++ break; ++ ++ case MFC_POLLING_FW_DONE : ++ retVal = s3c_mfc_wait_polling(S3C_FIMV_FW_DONE); ++ break; ++ ++ case MFC_INTR_FRAME_DONE : ++ case MFC_INTR_DMA_DONE : ++ case MFC_INTR_FW_DONE : ++ case MFC_INTR_FRAME_FW_DONE: ++ if (interruptible_sleep_on_timeout(&s3c_mfc_wait_queue, 1000) == 0) { ++ retVal = 0; ++ mfc_err("Interrupt Time Out(%d)\n", command); ++ break; ++ } ++ ++ retVal = s3c_mfc_int_type; ++ s3c_mfc_int_type = 0; ++ break; ++ ++ default : ++ mfc_err("undefined command\n"); ++ retVal = 0; ++ } ++ ++ return retVal; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_intr.h linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_intr.h +--- linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_intr.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_intr.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,21 @@ ++/* ++ * drivers/media/video/samsung/mfc40/s3c_mfc_intr.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_MFC_INTR_H_ ++#define _S3C_MFC_INTR_H_ ++ ++#include "s3c_mfc_common.h" ++ ++int s3c_mfc_wait_for_done(s3c_mfc_wait_done_type command); ++ ++#endif /* _S3C_MFC_INTR_H_ */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_logmsg.h linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_logmsg.h +--- linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_logmsg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_logmsg.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,60 @@ ++/* ++ * drivers/media/video/samsung/mfc40/s3c_mfc_logmsg.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_MFC_LOGMSG_H_ ++#define _S3C_MFC_LOGMSG_H_ ++ ++/* debug macros */ ++#define MFC_DEBUG(fmt, ...) \ ++ do { \ ++ printk(KERN_DEBUG \ ++ "%s: " fmt, __func__, ##__VA_ARGS__); \ ++ } while(0) ++ ++#define MFC_ERROR(fmt, ...) \ ++ do { \ ++ printk(KERN_ERR \ ++ "%s: " fmt, __func__, ##__VA_ARGS__); \ ++ } while (0) ++ ++#define MFC_NOTICE(fmt, ...) \ ++ do { \ ++ printk(KERN_NOTICE \ ++ fmt, ##__VA_ARGS__); \ ++ } while (0) ++ ++#define MFC_INFO(fmt, ...) \ ++ do { \ ++ printk(KERN_INFO \ ++ fmt, ##__VA_ARGS__); \ ++ } while (0) ++ ++#define MFC_WARN(fmt, ...) \ ++ do { \ ++ printk(KERN_WARNING \ ++ fmt, ##__VA_ARGS__); \ ++ } while (0) ++ ++ ++#ifdef CONFIG_VIDEO_MFC40_DEBUG ++#define mfc_debug(fmt, ...) MFC_DEBUG(fmt, ##__VA_ARGS__) ++#else ++#define mfc_debug(fmt, ...) ++#endif ++ ++#define mfc_err(fmt, ...) MFC_ERROR(fmt, ##__VA_ARGS__) ++#define mfc_notice(fmt, ...) MFC_NOTICE(fmt, ##__VA_ARGS__) ++#define mfc_info(fmt, ...) MFC_INFO(fmt, ##__VA_ARGS__) ++#define mfc_warn(fmt, ...) MFC_WARN(fmt, ##__VA_ARGS__) ++ ++#endif /* _S3C_MFC_LOGMSG_H_ */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_memory.c linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_memory.c +--- linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_memory.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_memory.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,70 @@ ++/* ++ * drivers/media/video/samsung/mfc40/s3c_mfc_memory.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "s3c_mfc_memory.h" ++#include "s3c_mfc_logmsg.h" ++#include "s3c_mfc_types.h" ++#include "s3c_mfc_interface.h" ++ ++extern volatile unsigned char *s3c_mfc_virt_fw_buf; ++extern void __iomem *s3c_mfc_sfr_virt_base; ++ ++volatile unsigned char *s3c_mfc_get_fw_buf_virt_addr() ++{ ++ return (volatile unsigned char *)s3c_mfc_virt_fw_buf; ++} ++ ++volatile unsigned char *s3c_mfc_get_vsp_buf_virt_addr(int instNo) ++{ ++ volatile unsigned char *virAddr; ++ ++ virAddr = s3c_mfc_virt_fw_buf + MFC_MAX_FW_NUM*FIRMWARE_CODE_SIZE + instNo*VSP_BUF_SIZE; ++ return virAddr; ++} ++ ++unsigned int s3c_mfc_get_sfr_phys_addr() ++{ ++ return (unsigned int)S5PC1XX_PA_MFC; ++} ++ ++unsigned int s3c_mfc_get_fw_buf_phys_addr() ++{ ++ return (unsigned int)__virt_to_phys((unsigned int)s3c_mfc_virt_fw_buf); /* IMAGE_MFC_BUFFER_PA_START; */ ++} ++ ++unsigned int s3c_mfc_get_vsp_buf_phys_addr(int instNo) ++{ ++ unsigned int phyAddr; ++ ++ phyAddr = s3c_mfc_get_fw_buf_phys_addr() + MFC_MAX_FW_NUM*FIRMWARE_CODE_SIZE + instNo * VSP_BUF_SIZE+DB_STT_SIZE; ++ return phyAddr; ++} ++ ++unsigned int s3c_mfc_get_data_buffer_size(void) ++{ ++ unsigned int out = 0; ++#ifdef CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC ++ out = CONFIG_VIDEO_SAMSUNG_MEMSIZE_MFC * SZ_1K; ++#endif ++ return out; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_memory.h linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_memory.h +--- linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_memory.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_memory.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,44 @@ ++/* ++ * drivers/media/video/samsung/mfc40/s3c_mfc_memory.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_MFC_MEMORY_H_ ++#define _S3C_MFC_MEMORY_H_ ++ ++#include "s3c_mfc_common.h" ++#include "s3c_mfc_types.h" ++ ++#ifdef CONFIG_VIDEO_MFC_MAX_INSTANCE ++#define MFC_MAX_INSTANCE_NUM (CONFIG_VIDEO_MFC_MAX_INSTANCE + 1) ++#endif ++ ++#define MFC_MAX_FW_NUM (8) ++#define MFC_MAX_WIDTH (1280) ++#define MFC_MAX_HEIGHT (720) ++ ++/* All buffer size have to be aligned to 64 */ ++#define FIRMWARE_CODE_SIZE (98304) /* 98,304 byte */ ++#define VSP_BUF_SIZE (393216) /* 393,216 byte */ ++#define DB_STT_SIZE (MFC_MAX_WIDTH*4*32) /* 163,840 byte */ ++ ++ ++#define MFC_SFR_BUF_SIZE sizeof(S5PC100_MFC_SFR) ++#define MFC_FW_BUF_SIZE ((MFC_MAX_FW_NUM * FIRMWARE_CODE_SIZE) + (MFC_MAX_INSTANCE_NUM + 1) * (VSP_BUF_SIZE + DB_STT_SIZE)) /* 3,014,656 */ ++ ++volatile unsigned char *s3c_mfc_get_fw_buf_virt_addr(void); ++volatile unsigned char *s3c_mfc_get_vsp_buf_virt_addr(int instNo); ++unsigned int s3c_mfc_get_sfr_phys_addr(void); ++unsigned int s3c_mfc_get_fw_buf_phys_addr(void); ++unsigned int s3c_mfc_get_vsp_buf_phys_addr(int instNo); ++unsigned int s3c_mfc_get_data_buffer_size(void); ++ ++#endif /* _S3C_MFC_MEMORY_H_ */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_opr.c linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_opr.c +--- linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_opr.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_opr.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,820 @@ ++/* ++ * drivers/media/video/samsung/mfc40/s3c_mfc_opr.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "s3c_mfc_common.h" ++#include "s3c_mfc_opr.h" ++#include "s3c_mfc_logmsg.h" ++#include "s3c_mfc_memory.h" ++#include "s3c_mfc_fw.h" ++#include "s3c_mfc_buffer_manager.h" ++#include "s3c_mfc_interface.h" ++ ++extern void __iomem *s3c_mfc_sfr_virt_base; ++extern dma_addr_t s3c_mfc_phys_data_buf; ++extern unsigned char *s3c_mfc_virt_data_buf; ++ ++#define READL(offset) readl(s3c_mfc_sfr_virt_base + (offset)) ++#define WRITEL(data, offset) writel((data), s3c_mfc_sfr_virt_base + (offset)) ++ ++static void s3c_mfc_cmd_reset(void); ++static void s3c_mfc_cmd_fw_start(void); ++static void s3c_mfc_cmd_dma_start(void); ++static void s3c_mfc_cmd_seq_start(void); ++static void s3c_mfc_cmd_frame_start(void); ++static void s3c_mfc_cmd_sleep(void); ++static void s3c_mfc_cmd_wakeup(void); ++static void s3c_mfc_backup_context(s3c_mfc_inst_ctx *MfcCtx); ++static void s3c_mfc_restore_context(s3c_mfc_inst_ctx *MfcCtx); ++static void s3c_mfc_set_codec_firmware(s3c_mfc_inst_ctx *MfcCtx); ++static void s3c_mfc_set_encode_init_param(int inst_no, MFC_CODEC_TYPE mfc_codec_type, s3c_mfc_args *args); ++static MFC_ERROR_CODE s3c_mfc_set_dec_stream_buffer(int buf_addr, unsigned int buf_size); ++static MFC_ERROR_CODE s3c_mfc_set_dec_frame_buffer(s3c_mfc_inst_ctx *MfcCtx, int buf_addr, unsigned int buf_size); ++static MFC_ERROR_CODE s3c_mfc_set_vsp_buffer(int InstNo); ++static MFC_ERROR_CODE s3c_mfc_decode_one_frame(s3c_mfc_inst_ctx *MfcCtx, s3c_mfc_dec_exe_arg_t *DecArg, unsigned int *consumedStrmSize); ++ ++ ++static void s3c_mfc_cmd_reset(void) ++{ ++ WRITEL(1, S3C_FIMV_SW_RESET); ++ mdelay(10); ++ WRITEL(0, S3C_FIMV_SW_RESET); ++ WRITEL(0, S3C_FIMV_LAST_DEC); ++} ++ ++static void s3c_mfc_cmd_fw_start(void) ++{ ++ WRITEL(1, S3C_FIMV_FW_START); ++ WRITEL(1, S3C_FIMV_CPU_RESET); ++ mdelay(100); ++} ++ ++static void s3c_mfc_cmd_dma_start(void) ++{ ++ WRITEL(1, S3C_FIMV_DMA_START); ++} ++ ++static void s3c_mfc_cmd_seq_start(void) ++{ ++ WRITEL(1, S3C_FIMV_SEQ_START); ++} ++ ++static void s3c_mfc_cmd_frame_start(void) ++{ ++ WRITEL(1, S3C_FIMV_FRAME_START); ++} ++ ++static void s3c_mfc_cmd_sleep() ++{ ++ WRITEL(-1, S3C_FIMV_CH_ID); ++ WRITEL(MFC_SLEEP, S3C_FIMV_COMMAND_TYPE); ++} ++ ++static void s3c_mfc_cmd_wakeup() ++{ ++ WRITEL(-1, S3C_FIMV_CH_ID); ++ WRITEL(MFC_WAKEUP, S3C_FIMV_COMMAND_TYPE); ++ mdelay(100); ++} ++ ++static void s3c_mfc_backup_context(s3c_mfc_inst_ctx *MfcCtx) ++{ ++ memcpy(MfcCtx->MfcSfr, s3c_mfc_sfr_virt_base, S3C_FIMV_REG_SIZE); ++} ++ ++static void s3c_mfc_restore_context(s3c_mfc_inst_ctx *MfcCtx) ++{ ++ /* ++ memcpy(s3c_mfc_sfr_virt_base, MfcCtx->MfcSfr, S3C_FIMV_REG_SIZE); ++ */ ++} ++ ++static MFC_ERROR_CODE s3c_mfc_set_dec_stream_buffer(int buf_addr, unsigned int buf_size) ++{ ++ mfc_debug("buf_addr : 0x%08x buf_size : %d\n", buf_addr, buf_size); ++ ++ WRITEL(buf_addr & 0xfffffff8, S3C_FIMV_EXT_BUF_START_ADDR); ++ WRITEL(buf_addr + buf_size + 0x200, S3C_FIMV_EXT_BUF_END_ADDR); ++ WRITEL(buf_addr + buf_size + 0x200, S3C_FIMV_HOST_PTR); ++ WRITEL(8 - (buf_addr & 0x7), S3C_FIMV_START_BYTE_NUM); ++ WRITEL(buf_size, S3C_FIMV_DEC_UNIT_SIZE); ++ ++ return MFCINST_RET_OK; ++} ++ ++ ++static MFC_ERROR_CODE s3c_mfc_set_dec_frame_buffer(s3c_mfc_inst_ctx *MfcCtx, int buf_addr, unsigned int buf_size) ++{ ++ unsigned int Width, Height, FrameSize, dec_dpb_addr; ++ ++ ++ mfc_debug("buf_addr : 0x%08x buf_size : %d\n", buf_addr, buf_size); ++ ++ Width = (MfcCtx->img_width + 15)/16*16; ++ Height = (MfcCtx->img_height + 31)/32*32; ++ FrameSize = (Width*Height*3)>>1; ++ ++ mfc_debug("width : %d height : %d framesize : %d buf_size : %d MfcCtx->DPBCnt :%d\n", \ ++ Width, Height, FrameSize, buf_size, MfcCtx->DPBCnt); ++ if(buf_size < FrameSize*MfcCtx->totalDPBCnt){ ++ mfc_err("MFCINST_ERR_FRM_BUF_SIZE\n"); ++ return MFCINST_ERR_FRM_BUF_SIZE; ++ } ++ ++ WRITEL(Align(buf_addr, BUF_ALIGN_UNIT), S3C_FIMV_DEC_DPB_ADR); ++ dec_dpb_addr = READL(S3C_FIMV_DEC_DPB_ADR); ++ WRITEL(Align(dec_dpb_addr + FrameSize*MfcCtx->DPBCnt, BUF_ALIGN_UNIT), S3C_FIMV_DPB_COMV_ADR); ++ ++ if((MfcCtx->MfcCodecType == MPEG4_DEC) ++ ||(MfcCtx->MfcCodecType == MPEG2_DEC) ++ ||(MfcCtx->MfcCodecType == XVID_DEC) ++ ||(MfcCtx->MfcCodecType == DIVX_DEC) ) { ++ dec_dpb_addr = READL(S3C_FIMV_DEC_DPB_ADR); ++ WRITEL(Align(dec_dpb_addr + ((3*FrameSize*MfcCtx->DPBCnt)>>1), BUF_ALIGN_UNIT), S3C_FIMV_POST_ADR); ++ } ++ ++ mfc_debug("DEC_DPB_ADR : 0x%08x DPB_COMV_ADR : 0x%08x POST_ADR : 0x%08x\n", \ ++ READL(S3C_FIMV_DEC_DPB_ADR), READL(S3C_FIMV_DPB_COMV_ADR), READL(S3C_FIMV_POST_ADR)); ++ ++ ++ return MFCINST_RET_OK; ++} ++ ++static MFC_ERROR_CODE s3c_mfc_set_vsp_buffer(int InstNo) ++{ ++ unsigned int VSPPhyBuf; ++ ++ VSPPhyBuf = s3c_mfc_get_vsp_buf_phys_addr(InstNo); ++ WRITEL(Align(VSPPhyBuf, BUF_ALIGN_UNIT), S3C_FIMV_VSP_BUF_ADDR); ++ WRITEL(Align(VSPPhyBuf + VSP_BUF_SIZE, BUF_ALIGN_UNIT), S3C_FIMV_DB_STT_ADDR); ++ ++ mfc_debug("InstNo : %d VSP_BUF_ADDR : 0x%08x DB_STT_ADDR : 0x%08x\n", \ ++ InstNo, READL(S3C_FIMV_VSP_BUF_ADDR), READL(S3C_FIMV_DB_STT_ADDR)); ++ ++ return MFCINST_RET_OK; ++} ++ ++ ++static void s3c_mfc_set_codec_firmware(s3c_mfc_inst_ctx *MfcCtx) ++{ ++ unsigned int FWPhyBuf; ++ ++ FWPhyBuf = s3c_mfc_get_fw_buf_phys_addr(); ++ ++ WRITEL(FWPhyBuf + s3c_mfc_get_fw_buf_offset(MPEG4_ENC), S3C_FIMV_FW_STT_ADR_0); ++ WRITEL(FWPhyBuf + s3c_mfc_get_fw_buf_offset(MPEG4_DEC), S3C_FIMV_FW_STT_ADR_1); ++ WRITEL(FWPhyBuf + s3c_mfc_get_fw_buf_offset(H264_ENC), S3C_FIMV_FW_STT_ADR_2); ++ WRITEL(FWPhyBuf + s3c_mfc_get_fw_buf_offset(H264_DEC), S3C_FIMV_FW_STT_ADR_3); ++ WRITEL(FWPhyBuf + s3c_mfc_get_fw_buf_offset(VC1_DEC), S3C_FIMV_FW_STT_ADR_4); ++ WRITEL(FWPhyBuf + s3c_mfc_get_fw_buf_offset(MPEG2_DEC), S3C_FIMV_FW_STT_ADR_5); ++ WRITEL(FWPhyBuf + s3c_mfc_get_fw_buf_offset(H263_DEC), S3C_FIMV_FW_STT_ADR_6); ++ WRITEL(s3c_mfc_get_fw_buf_size(MfcCtx->MfcCodecType), S3C_FIMV_BOOTCODE_SIZE); ++} ++ ++ ++/* This function sets the MFC SFR values according to the input arguments. */ ++static void s3c_mfc_set_encode_init_param(int inst_no, MFC_CODEC_TYPE mfc_codec_type, s3c_mfc_args *args) ++{ ++ unsigned int ms_size; ++ ++ s3c_mfc_enc_init_mpeg4_arg_t *EncInitMpeg4Arg; ++ s3c_mfc_enc_init_h264_arg_t *EncInitH264Arg; ++ ++ EncInitMpeg4Arg = (s3c_mfc_enc_init_mpeg4_arg_t *) args; ++ EncInitH264Arg = (s3c_mfc_enc_init_h264_arg_t *) args; ++ ++ mfc_debug("mfc_codec_type : %d\n", mfc_codec_type); ++ ++ s3c_mfc_set_vsp_buffer(inst_no); ++ ++ /* Set the other SFR */ ++ WRITEL(EncInitMpeg4Arg->in_dpb_addr, S3C_FIMV_ENC_DPB_ADR); ++ WRITEL(EncInitMpeg4Arg->in_width, S3C_FIMV_IMG_SIZE_X); ++ WRITEL(EncInitMpeg4Arg->in_height, S3C_FIMV_IMG_SIZE_Y); ++ WRITEL(EncInitMpeg4Arg->in_profile_level, S3C_FIMV_PROFILE); ++ WRITEL(EncInitMpeg4Arg->in_gop_num, S3C_FIMV_IDR_PERIOD); ++ WRITEL(EncInitMpeg4Arg->in_gop_num, S3C_FIMV_I_PERIOD); ++ WRITEL(EncInitMpeg4Arg->in_vop_quant, S3C_FIMV_FRAME_QP_INIT); ++ WRITEL(0, S3C_FIMV_POST_ON); ++ WRITEL(EncInitMpeg4Arg->in_mb_refresh, S3C_FIMV_CIR_MB_NUM); ++ ++ /* Rate Control options */ ++ WRITEL((EncInitMpeg4Arg->in_RC_enable << 8) | (EncInitMpeg4Arg->in_vop_quant & 0x3F), S3C_FIMV_RC_CONFIG); ++ ++ if (READL(S3C_FIMV_RC_CONFIG) & 0x0300) { ++ WRITEL(EncInitMpeg4Arg->in_RC_framerate, S3C_FIMV_RC_FRAME_RATE); ++ WRITEL(EncInitMpeg4Arg->in_RC_bitrate, S3C_FIMV_RC_BIT_RATE); ++ WRITEL(EncInitMpeg4Arg->in_RC_qbound, S3C_FIMV_RC_QBOUND); ++ WRITEL(EncInitMpeg4Arg->in_RC_rpara, S3C_FIMV_RC_RPARA); ++ WRITEL(0, S3C_FIMV_RC_MB_CTRL); ++ } ++ ++ /* Multi-slice options */ ++ WRITEL(EncInitMpeg4Arg->in_MS_mode, S3C_FIMV_MSLICE_ENA); ++ ++ if (EncInitMpeg4Arg->in_MS_mode) { ++ WRITEL(EncInitMpeg4Arg->in_MS_size_mode, S3C_FIMV_MSLICE_SEL); ++ if (EncInitMpeg4Arg->in_MS_size_mode == 0) { ++ WRITEL(EncInitMpeg4Arg->in_MS_size, S3C_FIMV_MSLICE_MB); ++ WRITEL(0, S3C_FIMV_MSLICE_BYTE); ++ } else { ++ ms_size = (mfc_codec_type == H264_ENC) ? EncInitMpeg4Arg->in_MS_size : 0; ++ WRITEL(ms_size, S3C_FIMV_MSLICE_MB); ++ WRITEL(EncInitMpeg4Arg->in_MS_size, S3C_FIMV_MSLICE_BYTE); ++ } ++ } ++ ++ switch (mfc_codec_type) { ++ case MPEG4_ENC: ++ /* MPEG4 encoder */ ++ WRITEL(0, S3C_FIMV_ENTROPY_CON); ++ WRITEL(0, S3C_FIMV_DEBLOCK_FILTER_OPTION); ++ WRITEL(0, S3C_FIMV_SHORT_HD_ON); ++ break; ++ ++ case H263_ENC: ++ /* H263 encoder */ ++ WRITEL(0, S3C_FIMV_ENTROPY_CON); ++ WRITEL(0, S3C_FIMV_DEBLOCK_FILTER_OPTION); ++ WRITEL(1, S3C_FIMV_SHORT_HD_ON); ++ ++ break; ++ ++ case H264_ENC: ++ /* H.264 encoder */ ++ WRITEL((EncInitH264Arg->in_symbolmode & 0x1) | (EncInitH264Arg->in_model_number << 2), S3C_FIMV_ENTROPY_CON); ++ WRITEL((EncInitH264Arg->in_deblock_filt & 0x3) ++ | ((EncInitH264Arg->in_deblock_alpha_C0 & 0x1f) << 7) ++ | ((EncInitH264Arg->in_deblock_beta & 0x1f) << 2), S3C_FIMV_DEBLOCK_FILTER_OPTION); ++ WRITEL(0, S3C_FIMV_SHORT_HD_ON); ++ break; ++ ++ default: ++ mfc_err("Invalid MFC codec type\n"); ++ } ++ ++} ++ ++BOOL s3c_mfc_load_firmware() ++{ ++ volatile unsigned char *FWVirBuf; ++ ++ mfc_debug("s3c_mfc_load_firmware++\n"); ++ ++ FWVirBuf = s3c_mfc_get_fw_buf_virt_addr(); ++ memcpy((void *)FWVirBuf + s3c_mfc_get_fw_buf_offset(MPEG4_ENC), mp4_enc_mc_fw, sizeof(mp4_enc_mc_fw)); ++ memcpy((void *)FWVirBuf + s3c_mfc_get_fw_buf_offset(MPEG4_DEC), mp4_dec_mc_fw, sizeof(mp4_dec_mc_fw)); ++ memcpy((void *)FWVirBuf + s3c_mfc_get_fw_buf_offset(H264_ENC), h264_enc_mc_fw, sizeof(h264_enc_mc_fw)); ++ memcpy((void *)FWVirBuf + s3c_mfc_get_fw_buf_offset(H264_DEC), h264_dec_mc_fw, sizeof(h264_dec_mc_fw)); ++ memcpy((void *)FWVirBuf + s3c_mfc_get_fw_buf_offset(VC1_DEC), vc1_dec_mc_fw, sizeof(vc1_dec_mc_fw)); ++ memcpy((void *)FWVirBuf + s3c_mfc_get_fw_buf_offset(MPEG2_DEC), mp2_dec_mc_fw, sizeof(mp2_dec_mc_fw)); ++ memcpy((void *)FWVirBuf + s3c_mfc_get_fw_buf_offset(H263_DEC), h263_dec_mc_fw, sizeof(h263_dec_mc_fw)); ++ memcpy((void *)FWVirBuf + s3c_mfc_get_fw_buf_offset(COM_CTRL), cmd_ctrl_fw, sizeof(cmd_ctrl_fw)); ++ ++ mfc_debug("s3c_mfc_load_firmware--\n"); ++ return TRUE; ++} ++ ++MFC_ERROR_CODE s3c_mfc_init_hw() ++{ ++ unsigned int FWPhyBuf; ++ unsigned int VSPPhyBuf; ++ ++ mfc_debug("++\n"); ++ ++ FWPhyBuf = s3c_mfc_get_fw_buf_phys_addr(); ++ ++ /* ++ * 0. MFC reset ++ */ ++ s3c_mfc_cmd_reset(); ++ ++ /* 1. DMA start ++ * - load command contrl firmware ++ */ ++ WRITEL(0, S3C_FIMV_BITS_ENDIAN); ++ WRITEL(0, S3C_FIMV_ARM_ENDIAN); ++ WRITEL(1, S3C_FIMV_BUS_MASTER); ++ ++ WRITEL(FWPhyBuf + s3c_mfc_get_fw_buf_offset(COM_CTRL), S3C_FIMV_DMA_EXTADDR); ++ WRITEL(s3c_mfc_get_fw_buf_size(COM_CTRL)/4, S3C_FIMV_BOOTCODE_SIZE); ++ WRITEL(0, S3C_FIMV_DMA_INTADDR); ++ ++ WRITEL(INT_LEVEL_BIT, S3C_FIMV_INT_MODE); ++ WRITEL(0, S3C_FIMV_INT_OFF); ++ WRITEL(1, S3C_FIMV_INT_DONE_CLEAR); ++ WRITEL(INT_MFC_DMA_DONE, S3C_FIMV_INT_MASK); ++ ++ ++ s3c_mfc_cmd_dma_start(); ++ ++ if(s3c_mfc_wait_for_done(MFC_INTR_DMA_DONE) == 0){ ++ mfc_err("MFCINST_ERR_FW_DMA_SET_FAIL\n"); ++ return MFCINST_ERR_FW_DMA_SET_FAIL; ++ } ++ ++ /* 2. FW start ++ * - set VSP buffer for command control ++ * - set memory structure ++ */ ++ VSPPhyBuf = s3c_mfc_get_vsp_buf_phys_addr(MFC_MAX_INSTANCE_NUM); ++ WRITEL(Align(VSPPhyBuf, BUF_ALIGN_UNIT), S3C_FIMV_VSP_BUF_ADDR); ++ ++ WRITEL(0, S3C_FIMV_BUS_MASTER); ++ WRITEL(1, S3C_FIMV_BITS_ENDIAN); ++ WRITEL(1, S3C_FIMV_INT_DONE_CLEAR); ++ WRITEL(INT_MFC_FRAME_DONE | INT_MFC_FW_DONE, S3C_FIMV_INT_MASK); ++ WRITEL(MEM_STRUCT_LINEAR, S3C_FIMV_TILE_MODE); ++ ++ s3c_mfc_cmd_fw_start(); ++ ++ mfc_debug("--", "VSP_BUF_ADDR : 0x%08x DB_STT_ADDR : 0x%08x\n", \ ++ READL(S3C_FIMV_VSP_BUF_ADDR), READL(S3C_FIMV_DB_STT_ADDR)); ++ ++ return MFCINST_RET_OK; ++} ++ ++MFC_ERROR_CODE s3c_mfc_init_encode(s3c_mfc_inst_ctx *MfcCtx, s3c_mfc_args *args) ++{ ++ mfc_debug("++\n"); ++ ++ MfcCtx->MfcCodecType = ((MFC_CODEC_TYPE *) args)[0]; ++ ++ /* 3. CHANNEL SET ++ * - set codec firmware ++ * - set codec_type/channel_id/post_on ++ */ ++ ++ s3c_mfc_set_codec_firmware(MfcCtx); ++ ++ WRITEL(s3c_mfc_get_codec_type(MfcCtx->MfcCodecType), S3C_FIMV_STANDARD_SEL); ++ WRITEL(MFC_CHANNEL_SET, S3C_FIMV_COMMAND_TYPE); ++ WRITEL(MfcCtx->InstNo, S3C_FIMV_CH_ID); ++ WRITEL(0, S3C_FIMV_POST_ON); ++ WRITEL(1, S3C_FIMV_BITS_ENDIAN); ++ ++ WRITEL(INT_LEVEL_BIT, S3C_FIMV_INT_MODE); ++ WRITEL(0, S3C_FIMV_INT_OFF); ++ WRITEL(1, S3C_FIMV_INT_DONE_CLEAR); ++ WRITEL((INT_MFC_FRAME_DONE|INT_MFC_FW_DONE), S3C_FIMV_INT_MASK); ++ ++ s3c_mfc_cmd_frame_start(); ++ ++ if(s3c_mfc_wait_for_done(MFC_INTR_FRAME_DONE) == 0){ ++ mfc_err("MFCINST_ERR_FW_LOAD_FAIL\n"); ++ return MFCINST_ERR_FW_LOAD_FAIL; ++ } ++ ++ /* 4. INIT CODEC ++ * - change Endian(important!!!) ++ * - set Encoder Init SFR ++ */ ++ ++ s3c_mfc_set_encode_init_param(MfcCtx->InstNo, MfcCtx->MfcCodecType, args); ++ ++ WRITEL(s3c_mfc_get_codec_type(MfcCtx->MfcCodecType), S3C_FIMV_STANDARD_SEL); ++ WRITEL(MfcCtx->InstNo, S3C_FIMV_CH_ID); ++ WRITEL(MFC_INIT_CODEC, S3C_FIMV_COMMAND_TYPE); ++ WRITEL(1, S3C_FIMV_BITS_ENDIAN); ++ WRITEL(INT_LEVEL_BIT, S3C_FIMV_INT_MODE); ++ WRITEL(0, S3C_FIMV_INT_OFF); ++ WRITEL(1, S3C_FIMV_INT_DONE_CLEAR); ++ WRITEL((INT_MFC_FRAME_DONE|INT_MFC_FW_DONE), S3C_FIMV_INT_MASK); ++ ++ s3c_mfc_cmd_frame_start(); ++ ++ if(s3c_mfc_wait_for_done(MFC_INTR_FRAME_DONE) == 0){ ++ mfc_err("MFCINST_ERR_FW_LOAD_FAIL\n"); ++ return MFCINST_ERR_FW_LOAD_FAIL; ++ } ++ ++ s3c_mfc_backup_context(MfcCtx); ++ mfc_debug("--\n"); ++ return MFCINST_RET_OK; ++} ++ ++ ++MFC_ERROR_CODE s3c_mfc_exe_encode(s3c_mfc_inst_ctx *MfcCtx, s3c_mfc_args *args) ++{ ++ s3c_mfc_enc_exe_arg *EncExeArg; ++ ++ /* ++ * 5. Encode Frame ++ */ ++ ++ EncExeArg = (s3c_mfc_enc_exe_arg *) args; ++ mfc_debug("++ EncExeArg->in_strm_st : 0x%08x EncExeArg->in_strm_end :0x%08x \r\n", \ ++ EncExeArg->in_strm_st, EncExeArg->in_strm_end); ++ mfc_debug("EncExeArg->in_Y_addr : 0x%08x EncExeArg->in_CbCr_addr :0x%08x \r\n", \ ++ EncExeArg->in_Y_addr, EncExeArg->in_CbCr_addr); ++ ++ s3c_mfc_restore_context(MfcCtx); ++ ++ s3c_mfc_set_vsp_buffer(MfcCtx->InstNo); ++ ++ if ((MfcCtx->forceSetFrameType > DONT_CARE) && \ ++ (MfcCtx->forceSetFrameType <= NOT_CODED)) { ++ WRITEL(MfcCtx->forceSetFrameType, S3C_FIMV_CODEC_COMMAND); ++ MfcCtx->forceSetFrameType = DONT_CARE; ++ } else ++ WRITEL(DONT_CARE, S3C_FIMV_CODEC_COMMAND); ++ /* ++ if((EncExeArg->in_ForceSetFrameType >= DONT_CARE) && (EncExeArg->in_ForceSetFrameType <= NOT_CODED)) ++ WRITEL(EncExeArg->in_ForceSetFrameType, S3C_FIMV_CODEC_COMMAND); ++ */ ++ /* ++ * Set Interrupt ++ */ ++ ++ WRITEL(EncExeArg->in_Y_addr, S3C_FIMV_ENC_CUR_Y_ADR); ++ WRITEL(EncExeArg->in_CbCr_addr, S3C_FIMV_ENC_CUR_CBCR_ADR); ++ WRITEL(EncExeArg->in_strm_st, S3C_FIMV_EXT_BUF_START_ADDR); ++ WRITEL(EncExeArg->in_strm_end, S3C_FIMV_EXT_BUF_END_ADDR); ++ WRITEL(EncExeArg->in_strm_st, S3C_FIMV_HOST_PTR); ++ ++ WRITEL(MFC_FRAME_RUN, S3C_FIMV_COMMAND_TYPE); ++ WRITEL(MfcCtx->InstNo, S3C_FIMV_CH_ID); ++ WRITEL(s3c_mfc_get_codec_type(MfcCtx->MfcCodecType), S3C_FIMV_STANDARD_SEL); ++ ++ WRITEL(INT_LEVEL_BIT, S3C_FIMV_INT_MODE); ++ WRITEL(0, S3C_FIMV_INT_OFF); ++ WRITEL(1, S3C_FIMV_INT_DONE_CLEAR); ++ WRITEL(1, S3C_FIMV_BITS_ENDIAN); ++ WRITEL((INT_MFC_FRAME_DONE|INT_MFC_FW_DONE), S3C_FIMV_INT_MASK); ++ ++ s3c_mfc_cmd_frame_start(); ++ ++ if (s3c_mfc_wait_for_done(MFC_INTR_FRAME_DONE) == 0) { ++ mfc_err("MFCINST_ERR_ENC_ENCODE_DONE_FAIL\n"); ++ return MFCINST_ERR_ENC_ENCODE_DONE_FAIL; ++ } ++ ++ EncExeArg->out_frame_type = READL(S3C_FIMV_RET_VALUE); ++ EncExeArg->out_encoded_size = READL(S3C_FIMV_ENC_UNIT_SIZE); ++ EncExeArg->out_header_size = READL(S3C_FIMV_ENC_HEADER_SIZE); ++ ++ ++ mfc_debug("-- frame type(%d) encodedSize(%d)\r\n", \ ++ EncExeArg->out_frame_type, EncExeArg->out_encoded_size); ++ return MFCINST_RET_OK; ++} ++ ++ ++MFC_ERROR_CODE s3c_mfc_init_decode(s3c_mfc_inst_ctx *MfcCtx, s3c_mfc_args *args) ++{ ++ MFC_ERROR_CODE ret; ++ s3c_mfc_dec_init_arg_t *InitArg; ++ unsigned int FWPhyBuf; ++ ++ mfc_debug("++\n"); ++ InitArg = (s3c_mfc_dec_init_arg_t *)args; ++ FWPhyBuf = s3c_mfc_get_fw_buf_phys_addr(); ++ ++ /* Context setting from input param */ ++ MfcCtx->MfcCodecType = InitArg->in_codec_type; ++ MfcCtx->IsPackedPB = InitArg->in_packed_PB; ++ ++ /* 3. CHANNEL SET ++ * - set codec firmware ++ * - set codec_type/channel_id/post_on ++ */ ++ ++ s3c_mfc_set_codec_firmware(MfcCtx); ++ ++ WRITEL(s3c_mfc_get_codec_type(MfcCtx->MfcCodecType), S3C_FIMV_STANDARD_SEL); ++ WRITEL(MFC_CHANNEL_SET, S3C_FIMV_COMMAND_TYPE); ++ WRITEL(MfcCtx->InstNo, S3C_FIMV_CH_ID); ++ WRITEL(MfcCtx->postEnable, S3C_FIMV_POST_ON); ++ WRITEL(INT_LEVEL_BIT, S3C_FIMV_INT_MODE); ++ WRITEL(0, S3C_FIMV_INT_OFF); ++ WRITEL(1, S3C_FIMV_INT_DONE_CLEAR); ++ WRITEL(INT_MFC_FRAME_DONE | INT_MFC_FW_DONE, S3C_FIMV_INT_MASK); ++ WRITEL(1, S3C_FIMV_BITS_ENDIAN); ++ ++ s3c_mfc_cmd_frame_start(); ++ ++ if((ret = s3c_mfc_wait_for_done(MFC_INTR_FRAME_DONE)) == 0){ ++ mfc_err("MFCINST_ERR_FW_LOAD_FAIL\n"); ++ return MFCINST_ERR_FW_LOAD_FAIL; ++ } ++ ++ /* 4. INIT CODEC ++ * - change Endian(important!!) ++ * - set VSP buffer ++ * - set Input Stream buffer ++ * - set NUM_EXTRA_DPB ++ */ ++ s3c_mfc_set_vsp_buffer(MfcCtx->InstNo); ++ s3c_mfc_set_dec_stream_buffer(InitArg->in_strm_buf, InitArg->in_strm_size); ++ ++ WRITEL(1, S3C_FIMV_BITS_ENDIAN); ++ WRITEL(MfcCtx->InstNo, S3C_FIMV_CH_ID); ++ WRITEL(s3c_mfc_get_codec_type(MfcCtx->MfcCodecType), S3C_FIMV_STANDARD_SEL); ++ WRITEL(MFC_INIT_CODEC, S3C_FIMV_COMMAND_TYPE); ++ WRITEL((MfcCtx->displayDelay<<16)|(0xFFFF & MfcCtx->extraDPB), S3C_FIMV_NUM_EXTRA_BUF); ++ ++ s3c_mfc_cmd_frame_start(); ++ ++ if(s3c_mfc_wait_for_done(MFC_POLLING_HEADER_DONE) == 0){ ++ mfc_err("MFCINST_ERR_DEC_HEADER_DECODE_FAIL\n"); ++ return MFCINST_ERR_DEC_HEADER_DECODE_FAIL; ++ } ++ ++ /* out param & context setting from header decoding result */ ++ MfcCtx->img_width = READL(S3C_FIMV_IMG_SIZE_X); ++ MfcCtx->img_height = READL(S3C_FIMV_IMG_SIZE_Y); ++ ++ InitArg->out_img_width = READL(S3C_FIMV_IMG_SIZE_X); ++ InitArg->out_img_height = READL(S3C_FIMV_IMG_SIZE_Y); ++ ++ /* in the case of VC1 interlace, height will be the multiple of 32 ++ * otherwise, height and width is the mupltiple of 16 ++ */ ++ InitArg->out_buf_width = (READL(S3C_FIMV_IMG_SIZE_X)+ 15)/16*16; ++ InitArg->out_buf_height = (READL(S3C_FIMV_IMG_SIZE_Y) + 31)/32*32; ++ ++ ++ switch (MfcCtx->MfcCodecType) { ++ case H264_DEC: ++ InitArg->out_dpb_cnt = (READL(S3C_FIMV_DPB_SIZE)*3)>>1; ++ MfcCtx->DPBCnt = READL(S3C_FIMV_DPB_SIZE); ++ break; ++ ++ case MPEG4_DEC: ++ case MPEG2_DEC: ++ case DIVX_DEC: ++ case XVID_DEC: ++ InitArg->out_dpb_cnt = ((NUM_MPEG4_DPB * 3) >> 1) + NUM_POST_DPB + MfcCtx->extraDPB; ++ MfcCtx->DPBCnt = NUM_MPEG4_DPB; ++ break; ++ ++ case VC1_DEC: ++ InitArg->out_dpb_cnt = ((NUM_VC1_DPB * 3) >> 1)+ MfcCtx->extraDPB; ++ MfcCtx->DPBCnt = NUM_VC1_DPB + MfcCtx->extraDPB; ++ break; ++ ++ default: ++ InitArg->out_dpb_cnt = ((NUM_MPEG4_DPB * 3) >> 1)+ NUM_POST_DPB + MfcCtx->extraDPB; ++ MfcCtx->DPBCnt = NUM_MPEG4_DPB; ++ } ++ ++ MfcCtx->totalDPBCnt = InitArg->out_dpb_cnt; ++ ++ mfc_debug("buf_width : %d buf_height : %d out_dpb_cnt : %d MfcCtx->DPBCnt : %d\n", \ ++ InitArg->out_img_width, InitArg->out_img_height, InitArg->out_dpb_cnt, MfcCtx->DPBCnt); ++ mfc_debug("img_width : %d img_height : %d\n", \ ++ InitArg->out_img_width, InitArg->out_img_height); ++ ++ s3c_mfc_backup_context(MfcCtx); ++ ++ mfc_debug("--\n"); ++ return MFCINST_RET_OK; ++} ++ ++ ++MFC_ERROR_CODE s3c_mfc_start_decode_seq(s3c_mfc_inst_ctx *MfcCtx, s3c_mfc_args *args) ++{ ++ int ret; ++ s3c_mfc_dec_seq_start_arg_t *seq_arg; ++ ++ /* ++ * 5. SEQ start ++ * - set DPB buffer ++ */ ++ mfc_debug("++\n"); ++ ++ seq_arg = (s3c_mfc_dec_seq_start_arg_t *)args; ++ ++ if ((ret = s3c_mfc_set_dec_frame_buffer(MfcCtx, seq_arg->in_frm_buf, seq_arg->in_frm_size)) != MFCINST_RET_OK) ++ return ret; ++ ++ WRITEL(INT_LEVEL_BIT, S3C_FIMV_INT_MODE); ++ WRITEL(0, S3C_FIMV_INT_OFF); ++ WRITEL(1, S3C_FIMV_INT_DONE_CLEAR); ++ WRITEL(1, S3C_FIMV_BITS_ENDIAN); ++ WRITEL(INT_MFC_FRAME_DONE | INT_MFC_FW_DONE, S3C_FIMV_INT_MASK); ++ ++ s3c_mfc_cmd_seq_start(); ++ ++ ret = s3c_mfc_wait_for_done(MFC_INTR_FRAME_DONE); ++ if(ret == 0) ++ return MFCINST_ERR_SEQ_START_FAIL; ++ ++ ++ return MFCINST_RET_OK; ++} ++ ++static MFC_ERROR_CODE s3c_mfc_decode_one_frame(s3c_mfc_inst_ctx *MfcCtx, s3c_mfc_dec_exe_arg_t *DecArg, unsigned int *consumedStrmSize) ++{ ++ int ret; ++ unsigned int frame_type; ++ static int count = 0; ++ ++ count++; ++ ++ mfc_debug("++ IntNo%d(%d)\r\n", MfcCtx->InstNo, count); ++ ++ s3c_mfc_restore_context(MfcCtx); ++ ++ if(MfcCtx->endOfFrame) { ++ WRITEL(1, S3C_FIMV_LAST_DEC); ++ MfcCtx->endOfFrame = 0; ++ } else { ++ WRITEL(0, S3C_FIMV_LAST_DEC); ++ //s3c_mfc_set_dec_stream_buffer(DecArg->in_strm_buf, DecArg->in_strm_size); ++ } ++ ++ s3c_mfc_set_dec_stream_buffer(DecArg->in_strm_buf, DecArg->in_strm_size); ++ ++ s3c_mfc_set_dec_frame_buffer(MfcCtx, DecArg->in_frm_buf, DecArg->in_frm_size); ++ ++ /* Set VSP */ ++ s3c_mfc_set_vsp_buffer(MfcCtx->InstNo); ++ ++ WRITEL( MfcCtx->InstNo, S3C_FIMV_CH_ID); ++ WRITEL(s3c_mfc_get_codec_type( MfcCtx->MfcCodecType), S3C_FIMV_STANDARD_SEL); ++ WRITEL(s3c_mfc_get_fw_buf_size(MfcCtx->MfcCodecType), S3C_FIMV_BOOTCODE_SIZE); ++ WRITEL(MFC_FRAME_RUN, S3C_FIMV_COMMAND_TYPE); ++ WRITEL(INT_LEVEL_BIT, S3C_FIMV_INT_MODE); ++ WRITEL(0, S3C_FIMV_INT_OFF); ++ WRITEL(1, S3C_FIMV_INT_DONE_CLEAR); ++ WRITEL(1, S3C_FIMV_BITS_ENDIAN); ++ WRITEL((INT_MFC_FRAME_DONE|MFC_INTR_FW_DONE), S3C_FIMV_INT_MASK); ++ ++ s3c_mfc_cmd_frame_start(); ++ ++ ++ if ((ret = s3c_mfc_wait_for_done(MFC_INTR_FRAME_FW_DONE)) == 0) { ++ mfc_err("MFCINST_ERR_DEC_DECODE_DONE_FAIL\n"); ++ return MFCINST_ERR_DEC_DECODE_DONE_FAIL; ++ } ++ ++ if ((READL(S3C_FIMV_DISPLAY_STATUS) & 0x3) == DECODING_ONLY) { ++ DecArg->out_display_Y_addr = 0; ++ DecArg->out_display_C_addr = 0; ++ } else { ++ DecArg->out_display_Y_addr = READL(S3C_FIMV_DISPLAY_Y_ADR); ++ DecArg->out_display_C_addr = READL(S3C_FIMV_DISPLAY_C_ADR); ++ } ++ ++ ++ if ((ret & MFC_INTR_FW_DONE) == MFC_INTR_FW_DONE) { ++ DecArg->out_display_status = 0; /* no more frame to display */ ++ } else ++ DecArg->out_display_status = 1; /* There exist frame to display */ ++ ++ frame_type = READL(S3C_FIMV_FRAME_TYPE); ++ MfcCtx->FrameType = (s3c_mfc_frame_type)(frame_type & 0x3); ++ ++ s3c_mfc_backup_context(MfcCtx); ++ ++ mfc_debug("(Y_ADDR : 0x%08x C_ADDR : 0x%08x)\r\n", \ ++ DecArg->out_display_Y_addr , DecArg->out_display_C_addr); ++ mfc_debug("(in_strmsize : 0x%08x consumed byte : 0x%08x)\r\n", \ ++ DecArg->in_strm_size, READL(S3C_FIMV_RET_VALUE)); ++ ++ *consumedStrmSize = READL(S3C_FIMV_RET_VALUE); ++ return MFCINST_RET_OK; ++} ++ ++ ++MFC_ERROR_CODE s3c_mfc_exe_decode(s3c_mfc_inst_ctx *MfcCtx, s3c_mfc_args *args) ++{ ++ MFC_ERROR_CODE ret; ++ s3c_mfc_dec_exe_arg_t *DecArg; ++ unsigned int consumedStrmSize; ++ ++ /* 6. Decode Frame */ ++ mfc_debug("++\n"); ++ ++ DecArg = (s3c_mfc_dec_exe_arg_t *)args; ++ ret = s3c_mfc_decode_one_frame(MfcCtx, DecArg, &consumedStrmSize); ++ ++ if((MfcCtx->IsPackedPB) && (MfcCtx->FrameType == MFC_RET_FRAME_P_FRAME) \ ++ && (DecArg->in_strm_size - consumedStrmSize > 4)) { ++ mfc_debug("Packed PB\n"); ++ DecArg->in_strm_buf += consumedStrmSize; ++ DecArg->in_strm_size -= consumedStrmSize; ++ ++ ret = s3c_mfc_decode_one_frame(MfcCtx, DecArg, &consumedStrmSize); ++ } ++ mfc_debug("--\n"); ++ ++ return ret; ++} ++ ++MFC_ERROR_CODE s3c_mfc_deinit_hw(s3c_mfc_inst_ctx *MfcCtx) ++{ ++ s3c_mfc_restore_context(MfcCtx); ++ ++ return MFCINST_RET_OK; ++} ++ ++MFC_ERROR_CODE s3c_mfc_get_config(s3c_mfc_inst_ctx *MfcCtx, s3c_mfc_args *args) ++{ ++ return MFCINST_RET_OK; ++} ++ ++ ++MFC_ERROR_CODE s3c_mfc_set_config(s3c_mfc_inst_ctx *MfcCtx, s3c_mfc_args *args) ++{ ++ s3c_mfc_set_config_arg_t *set_cnf_arg; ++ set_cnf_arg = (s3c_mfc_set_config_arg_t *)args; ++ ++ switch (set_cnf_arg->in_config_param) { ++ case MFC_DEC_SETCONF_POST_ENABLE: ++ if (MfcCtx->MfcState >= MFCINST_STATE_DEC_SEQ_START) { ++ mfc_err("MFC_DEC_SETCONF_POST_ENABLE : state is invalid\n"); ++ return MFCINST_ERR_STATE_INVALID; ++ } ++ ++ if((set_cnf_arg->in_config_value[0] == 0) || (set_cnf_arg->in_config_value[0] == 1)) ++ MfcCtx->postEnable = set_cnf_arg->in_config_value[0]; ++ else { ++ mfc_warn("POST_ENABLE should be 0 or 1\n"); ++ MfcCtx->postEnable = 0; ++ } ++ break; ++ ++ ++ case MFC_DEC_SETCONF_EXTRA_BUFFER_NUM: ++ if (MfcCtx->MfcState >= MFCINST_STATE_DEC_SEQ_START) { ++ mfc_err("MFC_DEC_SETCONF_EXTRA_BUFFER_NUM : state is invalid\n"); ++ return MFCINST_ERR_STATE_INVALID; ++ } ++ if ((set_cnf_arg->in_config_value[0] >= 0) || (set_cnf_arg->in_config_value[0] <= MFC_MAX_EXTRA_DPB)) ++ MfcCtx->extraDPB = set_cnf_arg->in_config_value[0]; ++ else { ++ mfc_warn("EXTRA_BUFFER_NUM should be between 0 and 5...It will be set 5 by default\n"); ++ MfcCtx->extraDPB = MFC_MAX_EXTRA_DPB; ++ } ++ break; ++ ++ case MFC_DEC_SETCONF_DISPLAY_DELAY: ++ if (MfcCtx->MfcState >= MFCINST_STATE_DEC_SEQ_START) { ++ mfc_err("MFC_DEC_SETCONF_DISPLAY_DELAY : state is invalid\n"); ++ return MFCINST_ERR_STATE_INVALID; ++ } ++ if (MfcCtx->MfcCodecType == H264_DEC) { ++ if ((set_cnf_arg->in_config_value[0] >= 0) || (set_cnf_arg->in_config_value[0] < 16)) ++ MfcCtx->displayDelay = set_cnf_arg->in_config_value[0]; ++ else { ++ mfc_warn("DISPLAY_DELAY should be between 0 and 16\n"); ++ MfcCtx->displayDelay = 0; ++ } ++ } else { ++ mfc_warn("MFC_DEC_SETCONF_DISPLAY_DELAY is only valid for H.264\n"); ++ MfcCtx->displayDelay = 0; ++ } ++ break; ++ ++ case MFC_DEC_SETCONF_IS_LAST_FRAME: ++ if (MfcCtx->MfcState != MFCINST_STATE_DEC_EXE) { ++ mfc_err("MFC_DEC_SETCONF_IS_LAST_FRAME : state is invalid\n"); ++ return MFCINST_ERR_STATE_INVALID; ++ } ++ ++ if ((set_cnf_arg->in_config_value[0] == 0) || (set_cnf_arg->in_config_value[0] == 1)) ++ MfcCtx->endOfFrame = set_cnf_arg->in_config_value[0]; ++ else { ++ mfc_warn("IS_LAST_FRAME should be 0 or 1\n"); ++ MfcCtx->endOfFrame = 0; ++ } ++ break; ++ ++ case MFC_ENC_SETCONF_FRAME_TYPE: ++ if ((MfcCtx->MfcState < MFCINST_STATE_ENC_INITIALIZE) || (MfcCtx->MfcState > MFCINST_STATE_ENC_EXE)) { ++ mfc_err("MFC_ENC_SETCONF_FRAME_TYPE : state is invalid\n"); ++ return MFCINST_ERR_STATE_INVALID; ++ } ++ ++ if ((set_cnf_arg->in_config_value[0] < DONT_CARE) || (set_cnf_arg->in_config_value[0] > NOT_CODED)) ++ MfcCtx->forceSetFrameType = set_cnf_arg->in_config_value[0]; ++ else { ++ mfc_warn("FRAME_TYPE should be between 0 and 2\n"); ++ MfcCtx->forceSetFrameType = DONT_CARE; ++ } ++ break; ++ ++ default: ++ mfc_err("invalid config param\n"); ++ return MFCINST_ERR_SET_CONF; ++ } ++ ++ return MFCINST_RET_OK; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_opr.h linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_opr.h +--- linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_opr.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_opr.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,59 @@ ++/* ++ * drivers/media/video/samsung/mfc40/s3c_mfc_opr.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _S3C_MFC_OPR_H_ ++#define _S3C_MFC_OPR_H_ ++ ++#include "s3c_mfc_errorno.h" ++#include "s3c_mfc_interface.h" ++#include "s3c_mfc_types.h" ++ ++#define INT_MFC_FW_DONE (0x1 << 5) ++#define INT_MFC_DMA_DONE (0x1 << 7) ++#define INT_MFC_FRAME_DONE (0x1 << 8) ++/* Interrupt on/off (0x500) */ ++#define INT_ENABLE_BIT (0 << 0) ++#define INT_DISABLE_BIT (1 << 0) ++/* Interrupt mode (0x504) */ ++#define INT_LEVEL_BIT (0 << 0) ++#define INT_PULSE_BIT (1 << 0) ++ ++/* Command Types */ ++#define MFC_CHANNEL_SET 0 ++#define MFC_CHANNEL_READ 1 ++#define MFC_CHANNEL_END 2 ++#define MFC_INIT_CODEC 3 ++#define MFC_FRAME_RUN 4 ++#define MFC_SLEEP 6 ++#define MFC_WAKEUP 7 ++ ++/* DPB Count */ ++#define NUM_MPEG4_DPB (2) ++#define NUM_POST_DPB (3) ++#define NUM_VC1_DPB (4) ++ ++BOOL s3c_mfc_load_firmware(void); ++MFC_ERROR_CODE s3c_mfc_init_hw(void); ++MFC_ERROR_CODE s3c_mfc_init_encode(s3c_mfc_inst_ctx *MfcCtx, s3c_mfc_args *args); ++MFC_ERROR_CODE s3c_mfc_exe_encode(s3c_mfc_inst_ctx *MfcCtx, s3c_mfc_args *args); ++MFC_ERROR_CODE s3c_mfc_init_decode(s3c_mfc_inst_ctx *MfcCtx, s3c_mfc_args *args); ++MFC_ERROR_CODE s3c_mfc_start_decode_seq(s3c_mfc_inst_ctx *MfcCtx, s3c_mfc_args *args); ++MFC_ERROR_CODE s3c_mfc_exe_decode(s3c_mfc_inst_ctx *MfcCtx, s3c_mfc_args *args); ++MFC_ERROR_CODE s3c_mfc_get_config(s3c_mfc_inst_ctx *MfcCtx, s3c_mfc_args *args); ++MFC_ERROR_CODE s3c_mfc_set_config(s3c_mfc_inst_ctx *MfcCtx, s3c_mfc_args *args); ++MFC_ERROR_CODE s3c_mfc_deinit_hw(s3c_mfc_inst_ctx *MfcCtx); ++MFC_ERROR_CODE s3c_mfc_set_sleep(s3c_mfc_inst_ctx *MfcCtx); ++MFC_ERROR_CODE s3c_mfc_set_wakeup(s3c_mfc_inst_ctx *MfcCtx); ++ ++#endif /* _S3C_MFC_OPR_H_ */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_types.h linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_types.h +--- linux-2.6.28/drivers/media/video/samsung/mfc40/s3c_mfc_types.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/s3c_mfc_types.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,21 @@ ++/* ++ * drivers/media/video/samsung/mfc40/s3c_mfc_types.h ++ * ++ * Header file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __SAMSUNG_SYSLSI_APDEV_MFC_TYPE_H__ ++#define __SAMSUNG_SYSLSI_APDEV_MFC_TYPE_H__ ++ ++#include ++ ++typedef enum {FALSE, TRUE} BOOL; ++ ++#endif /* __SAMSUNG_SYSLSI_APDEV_MFC_TYPE_H__ */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/mfc40/vc1_dec_fw.c linux-2.6.28.6/drivers/media/video/samsung/mfc40/vc1_dec_fw.c +--- linux-2.6.28/drivers/media/video/samsung/mfc40/vc1_dec_fw.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/mfc40/vc1_dec_fw.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,584 @@ ++/* ++ * drivers/media/video/samsung/mfc40/vc1_dec_fw.c ++ * ++ * C file for Samsung MFC (Multi Function Codec - FIMV) driver ++ * ++ * PyoungJae Jung, Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++ ++ ++const unsigned char vc1_dec_mc_fw[22652] = { ++0xe1, 0xa0, 0x00, 0x00, 0xea, 0x00, 0x11, 0x3e, 0xe5, 0x9f, 0x30, 0x04, 0xe0, 0x8f, 0x30, 0x03, 0xe1, 0xa0, 0xf0, 0x03, 0x00, 0x00, 0x4a, 0xb8, 0xe9, 0x2d, 0x4f, 0xf3, 0xe1, 0xa0, 0x40, 0x00, 0xe5, 0x94, 0x10, 0x38, 0xe5, 0x90, 0x00, 0x3c, ++0xe2, 0x4d, 0xd0, 0x04, 0xe0, 0x08, 0x00, 0x91, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x84, 0x06, 0xe0, 0xe5, 0x84, 0x00, 0x30, 0xe5, 0x94, 0x10, 0x34, 0xe3, 0xa0, 0xa8, 0x52, 0xe3, 0x51, 0x00, 0x00, 0x15, 0x9a, 0x00, 0x90, 0x11, 0xa0, 0x20, 0x0a, ++0xe2, 0x84, 0x5a, 0x01, 0xe3, 0xa0, 0xb6, 0x02, 0xe3, 0xa0, 0x90, 0x01, 0xe3, 0xa0, 0x70, 0x00, 0xe3, 0xa0, 0x60, 0x00, 0x13, 0x50, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x0c, 0xe5, 0x95, 0x00, 0x2c, 0xe5, 0x92, 0x30, 0xd8, 0xe3, 0x53, 0x00, 0x01, ++0x1a, 0xff, 0xff, 0xfc, 0xe5, 0x8b, 0x90, 0x04, 0xe1, 0x50, 0x00, 0x01, 0xb5, 0x8b, 0x90, 0xa4, 0xa5, 0x8b, 0x90, 0xa0, 0xe5, 0x82, 0x90, 0xcc, 0xb2, 0x80, 0x00, 0x01, 0xba, 0xff, 0xff, 0xf5, 0xe3, 0xa0, 0x00, 0x40, 0xe5, 0x82, 0x00, 0x00, ++0xe5, 0x94, 0x00, 0x00, 0xe3, 0x50, 0x00, 0x04, 0x0a, 0x00, 0x00, 0x79, 0xea, 0x00, 0x00, 0x2e, 0xe5, 0x94, 0x00, 0xe4, 0xe3, 0x50, 0x00, 0x03, 0x1a, 0x00, 0x00, 0x03, 0xe5, 0x9d, 0x00, 0x08, 0xeb, 0x00, 0x04, 0xca, 0xe3, 0x50, 0x00, 0x01, ++0x0a, 0x00, 0x00, 0x2d, 0xe5, 0x94, 0x03, 0xd0, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x0e, 0xe5, 0x94, 0x00, 0x00, 0xe3, 0x50, 0x00, 0x01, 0xca, 0x00, 0x00, 0x0b, 0xe5, 0x94, 0x00, 0x30, 0xe3, 0x50, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x08, ++0xe5, 0x9d, 0x00, 0x08, 0xe3, 0xa0, 0x10, 0x01, 0xeb, 0x00, 0x04, 0x82, 0xe3, 0x50, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x03, 0xe5, 0x9d, 0x00, 0x08, 0xeb, 0x00, 0x0a, 0xd3, 0xe3, 0x50, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x5b, 0xe3, 0xa0, 0x00, 0x00, ++0xea, 0x00, 0x00, 0x0a, 0xe5, 0x9d, 0x10, 0x08, 0xe1, 0xa0, 0x00, 0x04, 0xeb, 0x00, 0x06, 0x3d, 0xe5, 0x9a, 0x00, 0x90, 0xe3, 0x50, 0x00, 0x00, 0x05, 0x94, 0x00, 0x2c, 0x02, 0x86, 0x60, 0x01, 0x02, 0x80, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, ++0xe3, 0xa0, 0x70, 0x01, 0xea, 0x00, 0x00, 0x03, 0xe5, 0x84, 0x00, 0x2c, 0xe5, 0x94, 0x10, 0x38, 0xe1, 0x50, 0x00, 0x01, 0x3a, 0xff, 0xff, 0xf0, 0xe5, 0x94, 0x00, 0x30, 0xe3, 0x57, 0x00, 0x01, 0xe2, 0x80, 0x00, 0x01, 0xe5, 0x84, 0x00, 0x30, ++0x0a, 0x00, 0x00, 0x05, 0xe5, 0x94, 0x00, 0x34, 0xe5, 0x94, 0x10, 0x30, 0xe0, 0x80, 0x00, 0x01, 0xe5, 0x94, 0x10, 0x3c, 0xe1, 0x50, 0x00, 0x01, 0x3a, 0xff, 0xff, 0xca, 0xe3, 0xa0, 0x00, 0x40, 0xe5, 0x8a, 0x00, 0x00, 0xe3, 0x57, 0x00, 0x01, ++0x1a, 0x00, 0x00, 0x18, 0xe5, 0x94, 0x00, 0xe4, 0xe3, 0x50, 0x00, 0x03, 0x11, 0xa0, 0x00, 0x0b, 0x1a, 0x00, 0x00, 0x1b, 0xe5, 0x9d, 0x00, 0x08, 0xeb, 0x00, 0x04, 0x69, 0xe5, 0x9a, 0x00, 0xb8, 0xe3, 0x50, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x67, ++0xe5, 0x9d, 0x00, 0x08, 0xe3, 0xa0, 0x10, 0x20, 0xeb, 0x00, 0x04, 0x54, 0xe2, 0x00, 0x00, 0xff, 0xe3, 0x50, 0x00, 0x0b, 0x0a, 0x00, 0x00, 0x08, 0xe5, 0x9a, 0x00, 0xd8, 0xe3, 0x50, 0x00, 0x01, 0x05, 0x8b, 0x90, 0x04, 0x05, 0x8b, 0x90, 0xa4, ++0x05, 0x8a, 0x90, 0xcc, 0x02, 0x86, 0x60, 0x01, 0x01, 0x56, 0x00, 0x08, 0x1a, 0xff, 0xff, 0xf7, 0xea, 0x00, 0x00, 0x0f, 0xe5, 0x85, 0x60, 0x2c, 0xe5, 0x94, 0x00, 0x34, 0xe5, 0x94, 0x10, 0x30, 0xe0, 0x80, 0x00, 0x01, 0xe5, 0x94, 0x10, 0x3c, ++0xe1, 0x50, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x0a, 0xea, 0x00, 0x00, 0x0d, 0xe5, 0x9a, 0x10, 0xd8, 0xe3, 0x51, 0x00, 0x01, 0x05, 0x80, 0x90, 0x04, 0x05, 0x80, 0x90, 0xa4, 0x05, 0x8a, 0x90, 0xcc, 0x02, 0x86, 0x60, 0x01, 0x01, 0x56, 0x00, 0x08, ++0x1a, 0xff, 0xff, 0xf7, 0xe3, 0xa0, 0x00, 0x40, 0xe5, 0x8a, 0x00, 0x00, 0xe5, 0x94, 0x00, 0x00, 0xe3, 0x50, 0x00, 0x04, 0x0a, 0x00, 0x00, 0x12, 0xea, 0x00, 0x00, 0x0e, 0xe5, 0x9a, 0x00, 0xd8, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0xff, 0xff, 0xfc, ++0xe5, 0x8b, 0x90, 0xa0, 0xe5, 0x8a, 0x90, 0xcc, 0xe5, 0x9a, 0x00, 0xdc, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0xff, 0xff, 0xfc, 0xe3, 0xa0, 0x00, 0x02, 0xe3, 0xa0, 0x18, 0x56, 0xe5, 0x81, 0x00, 0x14, 0xe5, 0x9d, 0x00, 0x08, 0xeb, 0x00, 0x04, 0x29, ++0xe3, 0xa0, 0x00, 0x03, 0xe8, 0xbd, 0x8f, 0xfe, 0xe5, 0x9a, 0x00, 0xdc, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0xff, 0xff, 0xfc, 0xe3, 0xa0, 0x60, 0x00, 0xe5, 0x8a, 0x60, 0xdc, 0xe5, 0x9d, 0x00, 0x08, 0xeb, 0x00, 0x04, 0x20, 0xe5, 0x94, 0x00, 0x04, ++0xe3, 0x50, 0x00, 0x02, 0x05, 0x94, 0x00, 0x18, 0x03, 0x50, 0x00, 0x00, 0x03, 0xa0, 0x00, 0x04, 0x08, 0xbd, 0x8f, 0xfe, 0xe5, 0x94, 0x00, 0x00, 0xe3, 0x50, 0x00, 0x01, 0xda, 0x00, 0x00, 0x05, 0xe3, 0x50, 0x00, 0x04, 0x15, 0x95, 0x00, 0x20, ++0x15, 0x85, 0x00, 0x1c, 0x15, 0x95, 0x00, 0x14, 0x15, 0x85, 0x00, 0x20, 0x1a, 0x00, 0x00, 0x0f, 0xe5, 0x85, 0x00, 0x28, 0xe5, 0x95, 0x00, 0x20, 0xe5, 0x85, 0x00, 0x1c, 0xe5, 0x95, 0x00, 0x10, 0xe5, 0x85, 0x00, 0x20, 0xe5, 0x94, 0x10, 0x00, ++0xe5, 0x95, 0x00, 0x18, 0xe3, 0x51, 0x00, 0x04, 0x15, 0x95, 0x10, 0x14, 0x05, 0x95, 0x10, 0x24, 0xe5, 0x85, 0x10, 0x18, 0x05, 0x85, 0x10, 0x14, 0x05, 0x85, 0x10, 0x10, 0xe5, 0x95, 0x10, 0x14, 0xe5, 0x85, 0x00, 0x14, 0xe5, 0x85, 0x10, 0x24, ++0xe5, 0x95, 0x00, 0x1c, 0xe3, 0x70, 0x00, 0x01, 0x15, 0x95, 0x10, 0x20, 0x11, 0x50, 0x00, 0x01, 0x15, 0x80, 0x90, 0x20, 0xe5, 0x94, 0x06, 0xf0, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x05, 0xe5, 0x84, 0x66, 0xf0, 0xe5, 0x94, 0x00, 0xd0, ++0xe3, 0x50, 0x00, 0x00, 0x03, 0xa0, 0x00, 0x01, 0x13, 0xa0, 0x00, 0x02, 0xe8, 0xbd, 0x8f, 0xfe, 0xe3, 0xa0, 0x00, 0x00, 0xe8, 0xbd, 0x8f, 0xfe, 0xe9, 0x2d, 0x40, 0x70, 0xe1, 0xa0, 0x50, 0x01, 0xe1, 0xa0, 0x60, 0x00, 0xe1, 0xa0, 0x40, 0x00, ++0xe1, 0xa0, 0x00, 0x05, 0xe3, 0xa0, 0x10, 0x09, 0xeb, 0x00, 0x03, 0xe2, 0xe5, 0x94, 0x10, 0x18, 0xe3, 0x51, 0x00, 0x00, 0x15, 0x94, 0x10, 0x3c, 0x10, 0x40, 0x00, 0x01, 0xe5, 0x84, 0x00, 0x34, 0xe1, 0xa0, 0x00, 0x05, 0xe3, 0xa0, 0x10, 0x01, ++0xeb, 0x00, 0x03, 0xda, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0x00, 0x00, 0x04, 0xe1, 0xa0, 0x10, 0x05, 0xe1, 0xa0, 0x00, 0x06, 0xeb, 0x00, 0x0b, 0xca, 0xe3, 0x50, 0x00, 0x00, 0x18, 0xbd, 0x80, 0x70, 0xe1, 0xa0, 0x10, 0x05, 0xe1, 0xa0, 0x00, 0x06, ++0xeb, 0xff, 0xff, 0x14, 0xe3, 0x50, 0x00, 0x00, 0xe8, 0xbd, 0x80, 0x70, 0xe1, 0x2f, 0xff, 0x1e, 0xe3, 0xa0, 0x00, 0x03, 0xe3, 0xa0, 0x18, 0x52, 0xe5, 0x2d, 0xe0, 0x04, 0xe5, 0x81, 0x00, 0x30, 0xeb, 0xff, 0xff, 0xf9, 0xe4, 0x9d, 0xf0, 0x04, ++0xe5, 0x90, 0x10, 0x00, 0xe1, 0xa0, 0x34, 0x01, 0xe1, 0xa0, 0x3c, 0x23, 0xe1, 0xa0, 0x2c, 0x21, 0xe1, 0xa0, 0xc8, 0x01, 0xe1, 0xa0, 0xcc, 0x2c, 0xe1, 0x82, 0x24, 0x03, 0xe1, 0x82, 0x28, 0x0c, 0xe1, 0x82, 0x1c, 0x01, 0xe5, 0x80, 0x10, 0x00, ++0xe1, 0x2f, 0xff, 0x1e, 0xe9, 0x2d, 0x40, 0x38, 0xe3, 0x51, 0x00, 0x00, 0xe1, 0xa0, 0x40, 0x00, 0x0a, 0x00, 0x00, 0x0f, 0xe3, 0xa0, 0x10, 0x20, 0xe1, 0xa0, 0x00, 0x04, 0xeb, 0x00, 0x03, 0xb5, 0xe5, 0x8d, 0x00, 0x00, 0xe1, 0xa0, 0x00, 0x0d, ++0xeb, 0xff, 0xff, 0xea, 0xea, 0x00, 0x00, 0x05, 0xe3, 0xa0, 0x10, 0x08, 0xe1, 0xa0, 0x00, 0x04, 0xeb, 0x00, 0x03, 0xae, 0xe5, 0x9d, 0x00, 0x00, 0xe2, 0x40, 0x00, 0x01, 0xe5, 0x8d, 0x00, 0x00, 0xe5, 0x9d, 0x00, 0x00, 0xe3, 0x50, 0x00, 0x00, ++0x1a, 0xff, 0xff, 0xf6, 0xe8, 0xbd, 0x80, 0x38, 0xe9, 0x2d, 0x40, 0x38, 0xe1, 0xa0, 0x50, 0x00, 0xe3, 0xa0, 0x10, 0x18, 0xeb, 0x00, 0x03, 0xa3, 0xe3, 0xa0, 0x10, 0x08, 0xe1, 0xa0, 0x00, 0x05, 0xeb, 0x00, 0x03, 0xa0, 0xe3, 0xc0, 0x10, 0x40, ++0xe3, 0x51, 0x00, 0x85, 0x13, 0xa0, 0x00, 0x0a, 0x1a, 0x00, 0x00, 0x08, 0xe2, 0x00, 0x00, 0x40, 0xe1, 0xa0, 0x43, 0x20, 0xe1, 0xa0, 0x00, 0x05, 0xe3, 0xa0, 0x10, 0x20, 0xeb, 0x00, 0x03, 0x97, 0xe5, 0x8d, 0x00, 0x00, 0xe1, 0xa0, 0x00, 0x0d, ++0xeb, 0xff, 0xff, 0xcc, 0xe1, 0xa0, 0x00, 0x04, 0xe8, 0xbd, 0x80, 0x38, 0xe9, 0x2d, 0x4f, 0xf0, 0xe1, 0xa0, 0x80, 0x00, 0xe3, 0xa0, 0x00, 0x03, 0xe2, 0x4d, 0xd0, 0x2c, 0xe3, 0xa0, 0x68, 0x52, 0xe5, 0x86, 0x00, 0x30, 0xe3, 0xa0, 0x50, 0x00, ++0xe3, 0xa0, 0x96, 0x05, 0xe5, 0x89, 0x51, 0x10, 0xe3, 0xa0, 0xa0, 0x02, 0xe5, 0x89, 0xa0, 0x08, 0xe3, 0xa0, 0x70, 0x01, 0xe5, 0x89, 0x70, 0x00, 0xe5, 0x96, 0x00, 0xd8, 0xe3, 0x50, 0x00, 0x01, 0x1a, 0xff, 0xff, 0xfc, 0xe5, 0x99, 0x16, 0x00, ++0xe3, 0xa0, 0x08, 0x55, 0xe5, 0x80, 0x10, 0x00, 0xe5, 0x99, 0x11, 0x20, 0xe5, 0x80, 0x10, 0x18, 0xe3, 0xa0, 0x10, 0x07, 0xe5, 0x80, 0x10, 0x1c, 0xe5, 0x80, 0x50, 0x20, 0xe5, 0x80, 0x50, 0x24, 0xe3, 0xa0, 0x00, 0x40, 0xe5, 0x86, 0x00, 0x08, ++0xe5, 0x86, 0x50, 0xdc, 0xe5, 0x86, 0x70, 0x00, 0xe3, 0xa0, 0x10, 0x20, 0xe2, 0x8d, 0x00, 0x04, 0xeb, 0x00, 0x03, 0x76, 0xe1, 0xa0, 0xb0, 0x00, 0xe2, 0x88, 0x4a, 0x01, 0xe2, 0x84, 0x00, 0x40, 0xe8, 0x80, 0x00, 0xa0, 0xe5, 0x84, 0x50, 0x48, ++0xe5, 0x84, 0x50, 0x38, 0xe5, 0x88, 0x50, 0xd0, 0xe5, 0x84, 0x50, 0x4c, 0xe5, 0x84, 0x50, 0x50, 0xe5, 0x84, 0x50, 0x54, 0xe1, 0xa0, 0x00, 0x08, 0xe5, 0x84, 0xa0, 0x5c, 0xeb, 0x00, 0x02, 0xc9, 0xe2, 0x0b, 0x00, 0xff, 0xe3, 0x50, 0x00, 0x0f, ++0x1a, 0x00, 0x00, 0x06, 0xe3, 0xa0, 0x10, 0x20, 0xe2, 0x8d, 0x00, 0x04, 0xeb, 0x00, 0x03, 0x5f, 0xe5, 0x96, 0x00, 0x30, 0xe3, 0x80, 0x00, 0x20, 0xe5, 0x86, 0x00, 0x30, 0xea, 0x00, 0x00, 0x03, 0xe2, 0x8d, 0x00, 0x04, 0xeb, 0xff, 0xff, 0xb1, ++0xe5, 0x84, 0x00, 0x3c, 0xe5, 0x84, 0x70, 0x50, 0xe2, 0x8d, 0x10, 0x04, 0xe1, 0xa0, 0x00, 0x08, 0xeb, 0x00, 0x02, 0xe5, 0xe1, 0xa0, 0xa0, 0x00, 0xe5, 0x94, 0x00, 0x50, 0xe3, 0x50, 0x00, 0x00, 0x15, 0x94, 0x10, 0x3c, 0x12, 0x8d, 0x00, 0x04, ++0x1b, 0xff, 0xff, 0x91, 0xe1, 0xa0, 0x00, 0x08, 0xeb, 0x00, 0x0e, 0xbd, 0xe3, 0xa0, 0x0c, 0x02, 0xe5, 0x84, 0x70, 0x48, 0xe5, 0x86, 0x00, 0x04, 0xe5, 0x89, 0x51, 0x10, 0xe5, 0x89, 0x70, 0x04, 0xe1, 0xa0, 0x00, 0x0a, 0xe2, 0x8d, 0xd0, 0x2c, ++0xe8, 0xbd, 0x8f, 0xf0, 0xe9, 0x2d, 0x40, 0xf8, 0xe1, 0xa0, 0x40, 0x01, 0xe3, 0xa0, 0x10, 0x20, 0xe1, 0xa0, 0x60, 0x00, 0xe1, 0xa0, 0x50, 0x02, 0xeb, 0x00, 0x03, 0x3e, 0xe5, 0x8d, 0x00, 0x00, 0xe1, 0xa0, 0x00, 0x0d, 0xeb, 0xff, 0xff, 0x73, ++0xe3, 0x54, 0x00, 0x00, 0x15, 0x9d, 0x00, 0x00, 0x13, 0xa0, 0x10, 0x20, 0x13, 0xc0, 0x02, 0x0f, 0x15, 0x8d, 0x00, 0x00, 0x11, 0xa0, 0x00, 0x06, 0x1b, 0x00, 0x03, 0x34, 0xe5, 0x9d, 0x00, 0x00, 0xe5, 0x85, 0x00, 0x00, 0xe3, 0xa0, 0x06, 0x05, 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0x9f, 0xc4, 0xe0, 0xe3, 0xa0, 0x00, 0x00, 0xe2, 0x8c, 0x2d, 0x05, 0xe5, 0x94, 0x10, 0x60, 0xe2, 0x81, 0x10, 0x04, 0xe1, 0x51, 0x00, 0x00, 0xda, 0x00, 0x00, 0x0a, 0xe0, 0x80, 0x11, 0x80, 0xe0, 0x85, 0x11, 0x81, ++0xe5, 0x91, 0x37, 0x24, 0xe7, 0x82, 0x31, 0x00, 0xe5, 0x91, 0x37, 0x1c, 0xe7, 0x8c, 0x31, 0x00, 0xe5, 0x91, 0x17, 0x20, 0xe5, 0x9f, 0x34, 0xac, 0xe7, 0x83, 0x11, 0x00, 0xe2, 0x80, 0x00, 0x01, 0xea, 0xff, 0xff, 0xf0, 0xe5, 0x94, 0x10, 0x58, ++0xe3, 0xa0, 0x08, 0x55, 0xe5, 0x80, 0x11, 0x90, 0xe5, 0x9a, 0x16, 0x00, 0xe5, 0x80, 0x10, 0x00, 0xe5, 0x9a, 0x11, 0x20, 0xe5, 0x80, 0x10, 0x18, 0xe3, 0xa0, 0x10, 0x07, 0xe5, 0x80, 0x10, 0x1c, 0xe5, 0x80, 0x80, 0x20, 0xe5, 0x80, 0x80, 0x24, ++0xe5, 0x8a, 0x81, 0x10, 0xe3, 0xa0, 0x00, 0x02, 0xe5, 0x8a, 0x00, 0x08, 0xe5, 0x8a, 0x60, 0x00, 0xe3, 0xa0, 0x00, 0x40, 0xe5, 0x8e, 0x00, 0x08, 0xe5, 0x8e, 0x80, 0xdc, 0xe5, 0x8e, 0x60, 0x00, 0xe5, 0x9a, 0x00, 0x5c, 0xe3, 0x50, 0x00, 0x00, ++0x0a, 0x00, 0x00, 0x08, 0xe2, 0x60, 0xa0, 0x08, 0xea, 0x00, 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0xe2, 0x0e, 0xe0, 0x3f, 0xe1, 0x8c, 0xc4, 0x0e, 0xe5, 0x90, 0xe0, 0x90, 0xe2, 0x0e, 0xe0, 0x3f, 0xe1, 0x8c, 0xc8, 0x0e, ++0xe5, 0x90, 0xe0, 0x94, 0xe2, 0x0e, 0xe0, 0x3f, 0xe1, 0x8c, 0xcc, 0x0e, 0xe5, 0x83, 0xc0, 0x1c, 0xe3, 0x51, 0x00, 0x03, 0x1a, 0x00, 0x00, 0x0f, 0xe5, 0x90, 0xc0, 0x48, 0xe5, 0x90, 0xe0, 0x4c, 0xe1, 0xa0, 0xcd, 0x8c, 0xe1, 0xa0, 0xc5, 0xac, ++0xe2, 0x0e, 0xe0, 0x1f, 0xe1, 0x8c, 0xca, 0x8e, 0xe5, 0x83, 0xc0, 0x10, 0xe5, 0x90, 0xc0, 0x50, 0xe5, 0x90, 0xe0, 0x54, 0xe1, 0xa0, 0xcf, 0x0c, 0xe1, 0xa0, 0xc2, 0x2c, 0xe2, 0x0e, 0xe0, 0x03, 0xe1, 0x8c, 0xce, 0x0e, 0xe5, 0x93, 0xe0, 0x10, ++0xe1, 0x8c, 0xc0, 0x0e, 0xe5, 0x83, 0xc0, 0x10, 0xe5, 0x83, 0x10, 0x14, 0xe5, 0x90, 0x10, 0x9c, 0xe5, 0x90, 0x20, 0x98, 0xe2, 0x01, 0x10, 0x03, 0xe2, 0x02, 0x20, 0x03, 0xe1, 0x81, 0x11, 0x02, 0xe5, 0x90, 0x20, 0xa0, 0xe2, 0x02, 0x20, 0x01, ++0xe1, 0x81, 0x12, 0x02, 0xe5, 0x90, 0x20, 0xa4, 0xe2, 0x02, 0x20, 0x01, 0xe1, 0x81, 0x12, 0x82, 0xe5, 0x90, 0x20, 0xa8, 0xe2, 0x02, 0x20, 0x03, 0xe1, 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0x08, 0xe5, 0x80, 0x14, 0x98, ++0xe5, 0x80, 0x15, 0x3c, 0xe5, 0x80, 0x14, 0x88, 0xe5, 0x80, 0x14, 0x8c, 0xe5, 0x80, 0x14, 0x44, 0xe5, 0x80, 0x14, 0x48, 0xe5, 0x80, 0x14, 0x4c, 0xe5, 0x80, 0x14, 0x34, 0xe5, 0x80, 0x14, 0x3c, 0xe5, 0x80, 0x15, 0x40, 0xe5, 0x80, 0x15, 0x44, ++0xe5, 0x80, 0x10, 0x04, 0xe5, 0x80, 0x10, 0x10, 0xe5, 0x80, 0x10, 0x54, 0xe5, 0x80, 0x10, 0x58, 0xe5, 0x80, 0x10, 0x14, 0xe5, 0x80, 0x10, 0x18, 0xe5, 0x80, 0x16, 0x60, 0xe5, 0x80, 0x16, 0xa4, 0xe1, 0x2f, 0xff, 0x1e, 0xe5, 0x2d, 0xe0, 0x04, ++0xe2, 0x80, 0xea, 0x01, 0xe5, 0x9e, 0x20, 0x60, 0xe5, 0x9e, 0x10, 0x64, 0xe2, 0x82, 0x30, 0x04, 0xe2, 0x81, 0x10, 0x01, 0xe1, 0x51, 0x00, 0x03, 0x00, 0x41, 0x10, 0x03, 0xe0, 0x81, 0x21, 0x81, 0xe0, 0x80, 0x21, 0x82, 0xe5, 0x92, 0xc7, 0x2c, ++0xe3, 0x5c, 0x00, 0x00, 0x05, 0x92, 0xc7, 0x30, 0x03, 0x5c, 0x00, 0x01, 0x1a, 0xff, 0xff, 0xf5, 0xe0, 0x81, 0x11, 0x81, 0xe0, 0x80, 0x01, 0x81, 0xe5, 0x90, 0x07, 0x18, 0xe5, 0x8e, 0x00, 0x64, 0xe3, 0xa0, 0x00, 0x00, 0xe5, 0x82, 0x07, 0x30, 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Post Porcessor ++# ++ ++config VIDEO_POST ++ bool "Samsung Post Processor Driver" ++ depends on VIDEO_SAMSUNG && (ARCH_S3C64XX || ARCH_S5P64XX) ++ default n ++ ---help--- ++ This is a post processor driver for Samsung S3C6410 and S5P6440. ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/post/Makefile linux-2.6.28.6/drivers/media/video/samsung/post/Makefile +--- linux-2.6.28/drivers/media/video/samsung/post/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/post/Makefile 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,17 @@ ++################################################# ++# Makefile for Post Processor ++# 2007 (C) Samsung Electronics ++# Author : SungJun Bae ++################################################# ++ ++ifeq ($(CONFIG_ARCH_S5P64XX),y) ++obj-$(CONFIG_VIDEO_POST) += s3c_post_core.o s3c_post_v4l2.o s3c_post_cfg.o s3c_post_regs.o ++else ++obj-$(CONFIG_VIDEO_POST) += s3c_pp_common.o s3c_pp_6400.o ++endif ++ ++EXTRA_CFLAGS += -Idrivers/media/video ++ ++ifeq ($(CONFIG_VIDEO_POST_DEBUG),y) ++EXTRA_CFLAGS += -DDEBUG ++endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/post/s3c_post.h linux-2.6.28.6/drivers/media/video/samsung/post/s3c_post.h +--- linux-2.6.28/drivers/media/video/samsung/post/s3c_post.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/post/s3c_post.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,403 @@ ++/* linux/drivers/media/video/samsung/s3c_post.h ++ * ++ * Header file for Samsung Post Processor driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#ifndef _S3C_CAMIF_H ++#define _S3C_CAMIF_H ++ ++#ifdef __KERNEL__ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#endif ++ ++/* ++ * P I X E L F O R M A T G U I D E ++ * ++ * The 'x' means 'DO NOT CARE' ++ * The '*' means 'POST SPECIFIC' ++ * For some post formats, we couldn't find equivalent format in the V4L2 FOURCC. ++ * ++ * POST TYPE PLANES ORDER V4L2_PIX_FMT ++ * --------------------------------------------------------- ++ * RGB565 x x V4L2_PIX_FMT_RGB565 ++ * RGB888 x x V4L2_PIX_FMT_RGB24 ++ * YUV420 2 LSB_CBCR V4L2_PIX_FMT_NV12 ++ * YUV420 2 LSB_CRCB V4L2_PIX_FMT_NV21 ++ * YUV420 2 MSB_CBCR V4L2_PIX_FMT_NV21X* ++ * YUV420 2 MSB_CRCB V4L2_PIX_FMT_NV12X* ++ * YUV420 3 x V4L2_PIX_FMT_YUV420 ++ * YUV422 1 YCBYCR V4L2_PIX_FMT_YUYV ++ * YUV422 1 YCRYCB V4L2_PIX_FMT_YVYU ++ * YUV422 1 CBYCRY V4L2_PIX_FMT_UYVY ++ * YUV422 1 CRYCBY V4L2_PIX_FMT_VYUY* ++ * YUV422 2 LSB_CBCR V4L2_PIX_FMT_NV16* ++ * YUV422 2 LSB_CRCB V4L2_PIX_FMT_NV61* ++ * YUV422 2 MSB_CBCR V4L2_PIX_FMT_NV16X* ++ * YUV422 2 MSB_CRCB V4L2_PIX_FMT_NV61X* ++ * YUV422 3 x V4L2_PIX_FMT_YUV422P ++ * ++*/ ++ ++/* ++ * C O M M O N D E F I N I T I O N S ++ * ++*/ ++#define S3C_POST_NAME "s3c-post" ++ ++#define info(args...) do { printk(KERN_INFO S3C_POST_NAME ": " args); } while (0) ++#define err(args...) do { printk(KERN_ERR S3C_POST_NAME ": " args); } while (0) ++ ++#define S3C_POST_MINOR 15 ++#define S3C_POST_MAX_FRAMES 4 ++ ++/* ++ * E N U M E R A T I O N S ++ * ++*/ ++enum s3c_post_order422_in_t { ++ IN_ORDER422_CRYCBY = (0 << 4), ++ IN_ORDER422_YCRYCB = (1 << 4), ++ IN_ORDER422_CBYCRY = (2 << 4), ++ IN_ORDER422_YCBYCR = (3 << 4), ++}; ++ ++enum s3c_post_order422_out_t { ++ OUT_ORDER422_YCBYCR = (0 << 0), ++ OUT_ORDER422_YCRYCB = (1 << 0), ++ OUT_ORDER422_CBYCRY = (2 << 0), ++ OUT_ORDER422_CRYCBY = (3 << 0), ++}; ++ ++enum s3c_post_2plane_order_t { ++ LSB_CBCR = 0, ++ LSB_CRCB = 1, ++ MSB_CRCB = 2, ++ MSB_CBCR = 3, ++}; ++ ++enum s3c_post_scan_t { ++ SCAN_TYPE_PROGRESSIVE = 0, ++ SCAN_TYPE_INTERLACE = 1, ++}; ++ ++enum s3c_post_format_t { ++ FORMAT_RGB565, ++ FORMAT_RGB666, ++ FORMAT_RGB888, ++ FORMAT_YCBCR420, ++ FORMAT_YCBCR422, ++}; ++ ++enum s3c_post_path_out_t { ++ PATH_OUT_DMA, ++ PATH_OUT_LCDFIFO, ++}; ++ ++/* ++ * P O S T S T R U C T U R E S ++ * ++*/ ++ ++/* ++ * struct s3c_post_frame_addr ++ * @phys_rgb: physical start address of rgb buffer ++ * @phys_y: physical start address of y buffer ++ * @phys_cb: physical start address of u buffer ++ * @phys_cr: physical start address of v buffer ++ * @virt_y: virtual start address of y buffer ++ * @virt_rgb: virtual start address of rgb buffer ++ * @virt_cb: virtual start address of u buffer ++ * @virt_cr: virtual start address of v buffer ++*/ ++struct s3c_post_frame_addr { ++ union { ++ dma_addr_t phys_rgb; ++ dma_addr_t phys_y; ++ }; ++ ++ dma_addr_t phys_cb; ++ dma_addr_t phys_cr; ++ ++ union { ++ u8 *virt_rgb; ++ u8 *virt_y; ++ }; ++ ++ u8 *virt_cb; ++ u8 *virt_cr; ++}; ++ ++/* ++ * struct s3c_post_dma_offset ++ * @y_h: y value horizontal offset ++ * @y_v: y value vertical offset ++ * @cb_h: cb value horizontal offset ++ * @cb_v: cb value vertical offset ++ * @cr_h: cr value horizontal offset ++ * @cr_v: cr value vertical offset ++ * ++*/ ++struct s3c_post_dma_offset { ++ int y_h; ++ int y_v; ++ int cb_h; ++ int cb_v; ++ int cr_h; ++ int cr_v; ++}; ++ ++/* ++ * struct s3c_post_scaler ++ * @hfactor: horizontal shift factor to scale up/down ++ * @vfactor: vertical shift factor to scale up/down ++ * @pre_hratio: horizontal ratio for pre-scaler ++ * @pre_vratio: vertical ratio for pre-scaler ++ * @pre_dst_width: destination width for pre-scaler ++ * @pre_dst_height: destination height for pre-scaler ++ * @scaleup_h: 1 if we have to scale up for the horizontal ++ * @scaleup_v: 1 if we have to scale up for the vertical ++ * @main_hratio: horizontal ratio for main scaler ++ * @main_vratio: vertical ratio for main scaler ++ * @real_width: src_width - offset ++ * @real_height: src_height - offset ++ * @line_length: line buffer length from platform_data ++*/ ++struct s3c_post_scaler { ++ u32 hfactor; ++ u32 vfactor; ++ u32 pre_hratio; ++ u32 pre_vratio; ++ u32 pre_dst_width; ++ u32 pre_dst_height; ++ u32 scaleup_h; ++ u32 scaleup_v; ++ u32 main_hratio; ++ u32 main_vratio; ++ u32 real_width; ++ u32 real_height; ++ u32 line_length; ++}; ++ ++/* ++ * struct s3c_post_in_frame: abstraction for frame data ++ * @addr: address information of frame data ++ * @width: width ++ * @height: height ++ * @offset: dma offset ++ * @format: pixel format ++ * @planes: YCBCR planes (1, 2 or 3) ++ * @order_1p 1plane YCBCR order ++ * @order_2p: 2plane YCBCR order ++*/ ++struct s3c_post_in_frame { ++ u32 buf_size; ++ struct s3c_post_frame_addr addr; ++ int width; ++ int height; ++ struct s3c_post_dma_offset offset; ++ enum s3c_post_format_t format; ++ int planes; ++ enum s3c_post_order422_in_t order_1p; ++ enum s3c_post_2plane_order_t order_2p; ++}; ++ ++/* ++ * struct s3c_post_out_frame: abstraction for frame data ++ * @cfn: current frame number ++ * @buf_size: 1 buffer size ++ * @addr[]: address information of frames ++ * @nr_frams: how many output frames used ++ * @width: width ++ * @height: height ++ * @offset: offset for output dma ++ * @format: pixel format ++ * @planes: YCBCR planes (1, 2 or 3) ++ * @order_1p 1plane YCBCR order ++ * @order_2p: 2plane YCBCR order ++ * @scan: output scan method (progressive, interlace) ++*/ ++struct s3c_post_out_frame { ++ int cfn; ++ u32 buf_size; ++ struct s3c_post_frame_addr addr[S3C_POST_MAX_FRAMES]; ++ int nr_frames; ++ int width; ++ int height; ++ struct s3c_post_dma_offset offset; ++ enum s3c_post_format_t format; ++ int planes; ++ enum s3c_post_order422_out_t order_1p; ++ enum s3c_post_2plane_order_t order_2p; ++ enum s3c_post_scan_t scan; ++}; ++ ++/* ++ * struct s3c_post_v4l2 ++*/ ++struct s3c_post_v4l2 { ++ struct v4l2_fmtdesc *fmtdesc; ++ struct v4l2_framebuffer frmbuf; ++ struct v4l2_input *input; ++ struct v4l2_output *output; ++ struct v4l2_rect crop_bounds; ++ struct v4l2_rect crop_defrect; ++ struct v4l2_rect crop_current; ++}; ++ ++/* ++ * struct s3c_post_control: abstraction for POST controller ++ * @id: id number (= minor number) ++ * @name: name for video_device ++ * @flag: status, usage, irq flag (S, U, I flag) ++ * @lock: mutex lock ++ * @waitq: waitqueue ++ * @pdata: platform data ++ * @clock: post clock ++ * @regs: virtual address of SFR ++ * @in_use: 1 when resource is occupied ++ * @irq: irq number ++ * @vd: video_device ++ * @v4l2: v4l2 info ++ * @scaler: scaler related information ++ * @in_frame: frame structure pointer if input is dma else null ++ * @out_type: type of output ++ * @out_frame: frame structure pointer if output is dma ++ * ++ * @open_lcdfifo: function pointer to open lcd fifo path (display driver) ++ * @close_lcdfifo: function pointer to close fifo path (display driver) ++*/ ++struct s3c_post_control { ++ /* general */ ++ int id; ++ char name[16]; ++ u32 flag; ++ struct mutex lock; ++ wait_queue_head_t waitq; ++ struct device *dev; ++ struct clk *clock; ++ void __iomem *regs; ++ atomic_t in_use; ++ int irq; ++ struct video_device *vd; ++ struct s3c_post_v4l2 v4l2; ++ struct s3c_post_scaler scaler; ++ ++ struct s3c_post_in_frame in_frame; ++ ++ /* output */ ++ enum s3c_post_path_out_t out_type; ++ struct s3c_post_out_frame out_frame; ++ ++ /* functions */ ++ void (*open_lcdfifo)(int win, int in_yuv, int sel); ++ void (*close_lcdfifo)(int win); ++}; ++ ++/* ++ * struct s3c_post_config ++*/ ++struct s3c_post_config { ++ struct s3c_post_control ctrl; ++ dma_addr_t dma_start; ++ dma_addr_t dma_current; ++ u32 dma_total; ++}; ++ ++ ++/* ++ * V 4 L 2 F I M C E X T E N S I O N S ++ * ++*/ ++#define V4L2_INPUT_TYPE_MEMORY 10 ++#define V4L2_OUTPUT_TYPE_MEMORY 20 ++#define V4L2_OUTPUT_TYPE_LCDFIFO 21 ++ ++#define FORMAT_FLAGS_PACKED 1 ++#define FORMAT_FLAGS_PLANAR 2 ++ ++#define V4L2_FMT_IN 0 ++#define V4L2_FMT_OUT 1 ++ ++/* FOURCC for POST specific */ ++#define V4L2_PIX_FMT_NV12X v4l2_fourcc('N', '1', '2', 'X') ++#define V4L2_PIX_FMT_NV21X v4l2_fourcc('N', '2', '1', 'X') ++#define V4L2_PIX_FMT_VYUY v4l2_fourcc('V', 'Y', 'U', 'Y') ++#define V4L2_PIX_FMT_NV16 v4l2_fourcc('N', 'V', '1', '6') ++#define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') ++#define V4L2_PIX_FMT_NV16X v4l2_fourcc('N', '1', '6', 'X') ++#define V4L2_PIX_FMT_NV61X v4l2_fourcc('N', '6', '1', 'X') ++ ++/* CID extensions */ ++#define V4L2_CID_NR_FRAMES (V4L2_CID_PRIVATE_BASE + 1) ++#define V4L2_CID_RESET (V4L2_CID_PRIVATE_BASE + 2) ++#define V4L2_CID_OUTPUT_ADDR (V4L2_CID_PRIVATE_BASE + 10) ++#define V4L2_CID_INPUT_ADDR (V4L2_CID_PRIVATE_BASE + 20) ++#define V4L2_CID_INPUT_ADDR_RGB (V4L2_CID_PRIVATE_BASE + 21) ++#define V4L2_CID_INPUT_ADDR_Y (V4L2_CID_PRIVATE_BASE + 22) ++#define V4L2_CID_INPUT_ADDR_CB (V4L2_CID_PRIVATE_BASE + 23) ++#define V4L2_CID_INPUT_ADDR_CBCR (V4L2_CID_PRIVATE_BASE + 24) ++#define V4L2_CID_INPUT_ADDR_CR (V4L2_CID_PRIVATE_BASE + 25) ++ ++/* ++ * E X T E R N S ++ * ++*/ ++extern struct s3c_post_config s3c_post; ++extern const struct v4l2_ioctl_ops s3c_post_v4l2_ops; ++extern struct video_device s3c_post_video_device; ++ ++extern struct s3c_platform_post *to_post_plat(struct device *dev); ++extern int s3c_post_alloc_input_memory(struct s3c_post_in_frame *info, dma_addr_t addr); ++extern int s3c_post_alloc_output_memory(struct s3c_post_out_frame *info); ++extern int s3c_post_alloc_y_memory(struct s3c_post_in_frame *info, dma_addr_t addr); ++extern int s3c_post_alloc_cb_memory(struct s3c_post_in_frame *info, dma_addr_t addr); ++extern int s3c_post_alloc_cr_memory(struct s3c_post_in_frame *info, dma_addr_t addr); ++extern void s3c_post_free_output_memory(struct s3c_post_out_frame *info); ++extern int s3c_post_set_input_frame(struct s3c_post_control *ctrl, struct v4l2_pix_format *fmt); ++extern int s3c_post_set_output_frame(struct s3c_post_control *ctrl, struct v4l2_pix_format *fmt); ++extern int s3c_post_frame_handler(struct s3c_post_control *ctrl); ++extern u8 *s3c_post_get_current_frame(struct s3c_post_control *ctrl); ++extern void s3c_post_set_nr_frames(struct s3c_post_control *ctrl, int nr); ++extern int s3c_post_set_scaler_info(struct s3c_post_control *ctrl); ++extern void s3c_post_start_dma(struct s3c_post_control *ctrl); ++extern void s3c_post_stop_dma(struct s3c_post_control *ctrl); ++extern void s3c_post_restart_dma(struct s3c_post_control *ctrl); ++extern void s3c_post_clear_irq(struct s3c_post_control *ctrl); ++extern int s3c_post_check_fifo(struct s3c_post_control *ctrl); ++extern void s3c_post_reset(struct s3c_post_control *ctrl); ++extern void s3c_post_set_target_format(struct s3c_post_control *ctrl); ++extern void s3c_post_set_output_dma(struct s3c_post_control *ctrl); ++extern void s3c_post_set_prescaler(struct s3c_post_control *ctrl); ++extern void s3c_post_set_scaler(struct s3c_post_control *ctrl); ++extern void s3c_post_start_scaler(struct s3c_post_control *ctrl); ++extern void s3c_post_stop_scaler(struct s3c_post_control *ctrl); ++extern void s3c_post_enable_capture(struct s3c_post_control *ctrl); ++extern void s3c_post_disable_capture(struct s3c_post_control *ctrl); ++extern void s3c_post_set_input_dma(struct s3c_post_control *ctrl); ++extern void s3c_post_start_input_dma(struct s3c_post_control *ctrl); ++extern void s3c_post_stop_input_dma(struct s3c_post_control *ctrl); ++extern void s3c_post_set_input_path(struct s3c_post_control *ctrl); ++extern void s3c_post_set_output_path(struct s3c_post_control *ctrl); ++extern void s3c_post_set_input_address(struct s3c_post_control *ctrl); ++extern void s3c_post_set_output_address(struct s3c_post_control *ctrl); ++extern int s3c_post_get_frame_count(struct s3c_post_control *ctrl); ++extern void s3c_post_wait_frame_end(struct s3c_post_control *ctrl); ++ ++/* FIMD externs */ ++extern void s3cfb_enable_local(int win, int in_yuv, int sel); ++extern void s3cfb_enable_dma(int win); ++ ++#endif /* _S3C_CAMIF_H */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/post/s3c_post_cfg.c linux-2.6.28.6/drivers/media/video/samsung/post/s3c_post_cfg.c +--- linux-2.6.28/drivers/media/video/samsung/post/s3c_post_cfg.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/post/s3c_post_cfg.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,736 @@ ++/* linux/drivers/media/video/samsung/s3c_post_cfg.c ++ * ++ * Configuration support file for Samsung Post Processor driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "s3c_post.h" ++ ++#if (CONFIG_VIDEO_SAMSUNG_MEMSIZE_POST > 0) ++static dma_addr_t s3c_post_get_dma_region(u32 bytes) ++{ ++ dma_addr_t end, addr, *curr; ++ ++ end = s3c_post.dma_start + s3c_post.dma_total; ++ curr = &s3c_post.dma_current; ++ ++ if (*curr + bytes > end) { ++ addr = 0; ++ } else { ++ addr = *curr; ++ *curr += bytes; ++ } ++ ++ return addr; ++} ++ ++static void s3c_post_put_dma_region(u32 bytes) ++{ ++ s3c_post.dma_current -= bytes; ++} ++ ++void s3c_post_free_output_memory(struct s3c_post_out_frame *info) ++{ ++ struct s3c_post_frame_addr *frame; ++ int i; ++ ++ for (i = 0; i < info->nr_frames; i++) { ++ frame = &info->addr[i]; ++ ++ if (frame->phys_y) ++ s3c_post_put_dma_region(info->buf_size); ++ ++ memset(frame, 0, sizeof(*frame)); ++ } ++ ++ info->buf_size = 0; ++} ++ ++static int s3c_post_alloc_rgb_memory(struct s3c_post_out_frame *info) ++{ ++ struct s3c_post_frame_addr *frame; ++ int i, ret, nr_frames = info->nr_frames; ++ ++ for (i = 0; i < nr_frames; i++) { ++ frame = &info->addr[i]; ++ ++ frame->phys_rgb = s3c_post_get_dma_region(info->buf_size); ++ if (frame->phys_rgb == 0) { ++ ret = -ENOMEM; ++ goto alloc_fail; ++ } ++ ++ frame->virt_rgb = phys_to_virt(frame->phys_rgb); ++ } ++ ++ for (i = nr_frames; i < S3C_POST_MAX_FRAMES; i++) { ++ frame = &info->addr[i]; ++ frame->phys_rgb = info->addr[i - nr_frames].phys_rgb; ++ frame->virt_rgb = info->addr[i - nr_frames].virt_rgb; ++ } ++ ++ return 0; ++ ++alloc_fail: ++ s3c_post_free_output_memory(info); ++ return ret; ++} ++ ++static int s3c_post_alloc_yuv_memory(struct s3c_post_out_frame *info) ++{ ++ struct s3c_post_frame_addr *frame; ++ int i, ret, nr_frames = info->nr_frames; ++ u32 size = info->width * info->height, cbcr_size; ++ ++ if (info->format == FORMAT_YCBCR420) ++ cbcr_size = size / 4; ++ else ++ cbcr_size = size / 2; ++ ++ for (i = 0; i < nr_frames; i++) { ++ frame = &info->addr[i]; ++ ++ frame->phys_y = s3c_post_get_dma_region(info->buf_size); ++ if (frame->phys_y == 0) { ++ ret = -ENOMEM; ++ goto alloc_fail; ++ } ++ ++ frame->phys_cb = frame->phys_y + size; ++ frame->phys_cr = frame->phys_cb + cbcr_size; ++ ++ frame->virt_y = phys_to_virt(frame->phys_y); ++ frame->virt_cb = frame->virt_y + size; ++ frame->virt_cr = frame->virt_cb + cbcr_size; ++ } ++ ++ for (i = nr_frames; i < S3C_POST_MAX_FRAMES; i++) { ++ frame = &info->addr[i]; ++ frame->phys_y = info->addr[i - nr_frames].phys_y; ++ frame->phys_cb = info->addr[i - nr_frames].phys_cb; ++ frame->phys_cr = info->addr[i - nr_frames].phys_cr; ++ frame->virt_y = info->addr[i - nr_frames].virt_y; ++ frame->virt_cb = info->addr[i - nr_frames].virt_cb; ++ frame->virt_cr = info->addr[i - nr_frames].virt_cr; ++ } ++ ++ return 0; ++ ++alloc_fail: ++ s3c_post_free_output_memory(info); ++ return ret; ++} ++ ++#else ++void s3c_post_free_output_memory(struct s3c_post_out_frame *info) ++{ ++ struct s3c_post_frame_addr *frame; ++ int i; ++ ++ for (i = 0; i < info->nr_frames; i++) { ++ frame = &info->addr[i]; ++ ++ if (frame->virt_y) ++ kfree(frame->virt_y); ++ ++ memset(frame, 0, sizeof(*frame)); ++ } ++ ++ info->buf_size = 0; ++} ++ ++static int s3c_post_alloc_rgb_memory(struct s3c_post_out_frame *info) ++{ ++ struct s3c_post_frame_addr *frame; ++ int i, ret, nr_frames = info->nr_frames; ++ ++ for (i = 0; i < nr_frames; i++) { ++ frame = &info->addr[i]; ++ ++ frame->virt_rgb = kmalloc(info->buf_size, GFP_DMA); ++ if (frame->virt_rgb == NULL) { ++ ret = -ENOMEM; ++ goto alloc_fail; ++ } ++ ++ frame->phys_rgb = virt_to_phys(frame->virt_rgb); ++ } ++ ++ for (i = nr_frames; i < S3C_POST_MAX_FRAMES; i++) { ++ frame = &info->addr[i]; ++ frame->virt_rgb = info->addr[i - nr_frames].virt_rgb; ++ frame->phys_rgb = info->addr[i - nr_frames].phys_rgb; ++ } ++ ++ return 0; ++ ++alloc_fail: ++ s3c_post_free_output_memory(info); ++ return ret; ++} ++ ++static int s3c_post_alloc_yuv_memory(struct s3c_post_out_frame *info) ++{ ++ struct s3c_post_frame_addr *frame; ++ int i, ret, nr_frames = info->nr_frames; ++ u32 size = info->width * info->height, cbcr_size; ++ ++ if (info->format == FORMAT_YCBCR420) ++ cbcr_size = size / 4; ++ else ++ cbcr_size = size / 2; ++ ++ for (i = 0; i < nr_frames; i++) { ++ frame = &info->addr[i]; ++ ++ frame->virt_y = kmalloc(info->buf_size, GFP_DMA); ++ if (frame->virt_y == NULL) { ++ ret = -ENOMEM; ++ goto alloc_fail; ++ } ++ ++ frame->virt_cb = frame->virt_y + size; ++ frame->virt_cr = frame->virt_cb + cbcr_size; ++ ++ frame->phys_y = virt_to_phys(frame->virt_y); ++ frame->phys_cb = frame->phys_y + size; ++ frame->phys_cr = frame->phys_cb + cbcr_size; ++ } ++ ++ for (i = nr_frames; i < S3C_POST_MAX_FRAMES; i++) { ++ frame = &info->addr[i]; ++ frame->phys_y = info->addr[i - nr_frames].phys_y; ++ frame->phys_cb = info->addr[i - nr_frames].phys_cb; ++ frame->phys_cr = info->addr[i - nr_frames].phys_cr; ++ frame->virt_y = info->addr[i - nr_frames].virt_y; ++ frame->virt_cb = info->addr[i - nr_frames].virt_cb; ++ frame->virt_cr = info->addr[i - nr_frames].virt_cr; ++ } ++ ++ return 0; ++ ++alloc_fail: ++ s3c_post_free_output_memory(info); ++ return ret; ++} ++#endif ++ ++static u32 s3c_post_get_buffer_size(int width, int height, enum s3c_post_format_t fmt) ++{ ++ u32 size = width * height; ++ u32 cbcr_size = 0, *buf_size = NULL, one_p_size; ++ ++ switch (fmt) { ++ case FORMAT_RGB565: ++ size *= 2; ++ buf_size = &size; ++ break; ++ ++ case FORMAT_RGB666: /* fall through */ ++ case FORMAT_RGB888: ++ size *= 4; ++ buf_size = &size; ++ break; ++ ++ case FORMAT_YCBCR420: ++ cbcr_size = size / 4; ++ one_p_size = size + (2 * cbcr_size); ++ buf_size = &one_p_size; ++ break; ++ ++ case FORMAT_YCBCR422: ++ cbcr_size = size / 2; ++ one_p_size = size + (2 * cbcr_size); ++ buf_size = &one_p_size; ++ break; ++ } ++ ++ if (*buf_size % PAGE_SIZE != 0) ++ *buf_size = (*buf_size / PAGE_SIZE + 1) * PAGE_SIZE; ++ ++ return *buf_size; ++} ++ ++int s3c_post_alloc_output_memory(struct s3c_post_out_frame *info) ++{ ++ int ret; ++ ++ info->buf_size = s3c_post_get_buffer_size(info->width, info->height, \ ++ info->format); ++ ++ if (info->format == FORMAT_YCBCR420 || info->format == FORMAT_YCBCR422) ++ ret = s3c_post_alloc_yuv_memory(info); ++ else ++ ret = s3c_post_alloc_rgb_memory(info); ++ ++ return ret; ++} ++ ++int s3c_post_alloc_input_memory(struct s3c_post_in_frame *info, dma_addr_t addr) ++{ ++ struct s3c_post_frame_addr *frame; ++ u32 size = info->width * info->height, cbcr_size; ++ ++ if (info->format == FORMAT_YCBCR420) ++ cbcr_size = size / 4; ++ else ++ cbcr_size = size / 2; ++ ++ info->buf_size = s3c_post_get_buffer_size(info->width, info->height, \ ++ info->format); ++ ++ switch (info->format) { ++ case FORMAT_RGB565: /* fall through */ ++ case FORMAT_RGB666: /* fall through */ ++ case FORMAT_RGB888: ++ info->addr.phys_rgb = addr; ++ break; ++ ++ case FORMAT_YCBCR420: /* fall through */ ++ case FORMAT_YCBCR422: ++ frame = &info->addr; ++ frame->phys_y = addr; ++ frame->phys_cb = frame->phys_y + size; ++ frame->phys_cr = frame->phys_cb + cbcr_size; ++ break; ++ } ++ ++ return 0; ++} ++ ++int s3c_post_alloc_y_memory(struct s3c_post_in_frame *info, ++ dma_addr_t addr) ++{ ++ info->addr.phys_y = addr; ++ info->buf_size = s3c_post_get_buffer_size(info->width, \ ++ info->height, info->format); ++ ++ return 0; ++} ++ ++int s3c_post_alloc_cb_memory(struct s3c_post_in_frame *info, ++ dma_addr_t addr) ++{ ++ info->addr.phys_cb = addr; ++ info->buf_size = s3c_post_get_buffer_size(info->width, \ ++ info->height, info->format); ++ ++ return 0; ++} ++ ++int s3c_post_alloc_cr_memory(struct s3c_post_in_frame *info, ++ dma_addr_t addr) ++{ ++ info->addr.phys_cr = addr; ++ info->buf_size = s3c_post_get_buffer_size(info->width, \ ++ info->height, info->format); ++ ++ return 0; ++} ++ ++void s3c_post_set_nr_frames(struct s3c_post_control *ctrl, int nr) ++{ ++ if (nr == 3) ++ ctrl->out_frame.nr_frames = 2; ++ else ++ ctrl->out_frame.nr_frames = nr; ++} ++ ++static void s3c_post_set_input_format(struct s3c_post_control *ctrl, ++ struct v4l2_pix_format *fmt) ++{ ++ struct s3c_post_in_frame *frame = &ctrl->in_frame; ++ ++ frame->width = fmt->width; ++ frame->height = fmt->height; ++ ++ switch (fmt->pixelformat) { ++ case V4L2_PIX_FMT_RGB565: ++ frame->format = FORMAT_RGB565; ++ frame->planes = 1; ++ break; ++ ++ case V4L2_PIX_FMT_RGB24: ++ frame->format = FORMAT_RGB888; ++ frame->planes = 1; ++ break; ++ ++ case V4L2_PIX_FMT_NV12: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = LSB_CBCR; ++ break; ++ ++ case V4L2_PIX_FMT_NV21: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = LSB_CRCB; ++ break; ++ ++ case V4L2_PIX_FMT_NV12X: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = MSB_CBCR; ++ break; ++ ++ case V4L2_PIX_FMT_NV21X: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = MSB_CRCB; ++ break; ++ ++ case V4L2_PIX_FMT_YUV420: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 3; ++ break; ++ ++ case V4L2_PIX_FMT_YUYV: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = IN_ORDER422_YCBYCR; ++ break; ++ ++ case V4L2_PIX_FMT_YVYU: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = IN_ORDER422_YCRYCB; ++ break; ++ ++ case V4L2_PIX_FMT_UYVY: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = IN_ORDER422_CBYCRY; ++ break; ++ ++ case V4L2_PIX_FMT_VYUY: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = IN_ORDER422_CRYCBY; ++ break; ++ ++ case V4L2_PIX_FMT_NV16: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = LSB_CBCR; ++ break; ++ ++ case V4L2_PIX_FMT_NV61: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = LSB_CRCB; ++ break; ++ ++ case V4L2_PIX_FMT_NV16X: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = MSB_CBCR; ++ break; ++ ++ case V4L2_PIX_FMT_NV61X: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = MSB_CRCB; ++ break; ++ ++ case V4L2_PIX_FMT_YUV422P: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 3; ++ break; ++ } ++} ++ ++int s3c_post_set_input_frame(struct s3c_post_control *ctrl, ++ struct v4l2_pix_format *fmt) ++{ ++ s3c_post_set_input_format(ctrl, fmt); ++ ++ return 0; ++} ++ ++static int s3c_post_set_output_format(struct s3c_post_control *ctrl, ++ struct v4l2_pix_format *fmt) ++{ ++ struct s3c_post_out_frame *frame = &ctrl->out_frame; ++ int depth = 0; ++ ++ frame->width = fmt->width; ++ frame->height = fmt->height; ++ ++ switch (fmt->pixelformat) { ++ case V4L2_PIX_FMT_RGB565: ++ frame->format = FORMAT_RGB565; ++ frame->planes = 1; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_RGB24: ++ frame->format = FORMAT_RGB888; ++ frame->planes = 1; ++ depth = 24; ++ break; ++ ++ case V4L2_PIX_FMT_NV12: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = LSB_CBCR; ++ depth = 12; ++ break; ++ ++ case V4L2_PIX_FMT_NV21: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = LSB_CRCB; ++ depth = 12; ++ break; ++ ++ case V4L2_PIX_FMT_NV12X: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = MSB_CBCR; ++ depth = 12; ++ break; ++ ++ case V4L2_PIX_FMT_NV21X: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 2; ++ frame->order_2p = MSB_CRCB; ++ depth = 12; ++ break; ++ ++ case V4L2_PIX_FMT_YUV420: ++ frame->format = FORMAT_YCBCR420; ++ frame->planes = 3; ++ depth = 12; ++ break; ++ ++ case V4L2_PIX_FMT_YUYV: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = OUT_ORDER422_YCBYCR; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_YVYU: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = OUT_ORDER422_YCRYCB; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_UYVY: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = OUT_ORDER422_CBYCRY; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_VYUY: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 1; ++ frame->order_1p = OUT_ORDER422_CRYCBY; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_NV16: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = LSB_CBCR; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_NV61: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = LSB_CRCB; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_NV16X: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = MSB_CBCR; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_NV61X: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 2; ++ frame->order_1p = MSB_CRCB; ++ depth = 16; ++ break; ++ ++ case V4L2_PIX_FMT_YUV422P: ++ frame->format = FORMAT_YCBCR422; ++ frame->planes = 3; ++ depth = 16; ++ break; ++ } ++ ++ switch (fmt->field) { ++ case V4L2_FIELD_INTERLACED: ++ case V4L2_FIELD_INTERLACED_TB: ++ case V4L2_FIELD_INTERLACED_BT: ++ frame->scan = SCAN_TYPE_INTERLACE; ++ break; ++ ++ default: ++ frame->scan = SCAN_TYPE_PROGRESSIVE; ++ break; ++ } ++ ++ return depth; ++} ++ ++int s3c_post_set_output_frame(struct s3c_post_control *ctrl, ++ struct v4l2_pix_format *fmt) ++{ ++ struct s3c_post_out_frame *frame = &ctrl->out_frame; ++ int depth = 0; ++ ++ depth = s3c_post_set_output_format(ctrl, fmt); ++ ++ if (ctrl->out_type == PATH_OUT_DMA && frame->addr[0].virt_y == NULL) { ++ if (s3c_post_alloc_output_memory(frame)) ++ err("cannot allocate memory\n"); ++ } ++ ++ return depth; ++} ++ ++u8 *s3c_post_get_current_frame(struct s3c_post_control *ctrl) ++{ ++ struct s3c_post_out_frame *frame = &ctrl->out_frame; ++ ++ return frame->addr[frame->cfn].virt_y; ++} ++ ++static int s3c_post_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift) ++{ ++ if (src >= tar * 64) { ++ err("out of pre-scaler range\n"); ++ return -EINVAL; ++ } else if (src >= tar * 32) { ++ *ratio = 32; ++ *shift = 5; ++ } else if (src >= tar * 16) { ++ *ratio = 16; ++ *shift = 4; ++ } else if (src >= tar * 8) { ++ *ratio = 8; ++ *shift = 3; ++ } else if (src >= tar * 4) { ++ *ratio = 4; ++ *shift = 2; ++ } else if (src >= tar * 2) { ++ *ratio = 2; ++ *shift = 1; ++ } else { ++ *ratio = 1; ++ *shift = 0; ++ } ++ ++ return 0; ++} ++ ++int s3c_post_set_scaler_info(struct s3c_post_control *ctrl) ++{ ++ struct s3c_post_scaler *sc = &ctrl->scaler; ++ struct s3c_post_dma_offset *d_ofs = &ctrl->in_frame.offset; ++ int ret, tx, ty, sx, sy; ++ int width, height, h_ofs, v_ofs; ++ ++ width = ctrl->in_frame.width; ++ height = ctrl->in_frame.height; ++ h_ofs = d_ofs->y_h * 2; ++ v_ofs = d_ofs->y_v * 2; ++ tx = ctrl->out_frame.width; ++ ty = ctrl->out_frame.height; ++ ++ if (tx <= 0 || ty <= 0) { ++ err("invalid target size\n"); ++ ret = -EINVAL; ++ goto err_size; ++ } ++ ++ sx = width - h_ofs; ++ sy = height - v_ofs; ++ ++ sc->real_width = sx; ++ sc->real_height = sy; ++ ++ if (sx <= 0 || sy <= 0) { ++ err("invalid source size\n"); ++ ret = -EINVAL; ++ goto err_size; ++ } ++ ++ s3c_post_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor); ++ s3c_post_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor); ++ ++ if (sx / sc->pre_hratio > sc->line_length) ++ info("line buffer size overflow\n"); ++ ++ sc->pre_dst_width = sx / sc->pre_hratio; ++ sc->pre_dst_height = sy / sc->pre_vratio; ++ ++ sc->main_hratio = (sx << 8) / (tx << sc->hfactor); ++ sc->main_vratio = (sy << 8) / (ty << sc->vfactor); ++ ++ sc->scaleup_h = (tx >= sx) ? 1 : 0; ++ sc->scaleup_v = (ty >= sy) ? 1 : 0; ++ ++ s3c_post_set_prescaler(ctrl); ++ s3c_post_set_scaler(ctrl); ++ ++ return 0; ++ ++err_size: ++ return ret; ++} ++ ++/* CAUTION: many sequence dependencies */ ++void s3c_post_start_dma(struct s3c_post_control *ctrl) ++{ ++ s3c_post_set_input_address(ctrl); ++ s3c_post_set_input_dma(ctrl); ++ s3c_post_set_scaler_info(ctrl); ++ s3c_post_set_target_format(ctrl); ++ s3c_post_set_output_path(ctrl); ++ ++ if (ctrl->out_type == PATH_OUT_DMA) { ++ s3c_post_set_output_address(ctrl); ++ s3c_post_set_output_dma(ctrl); ++ } ++ ++ s3c_post_start_scaler(ctrl); ++ s3c_post_enable_capture(ctrl); ++ s3c_post_start_input_dma(ctrl); ++} ++ ++void s3c_post_stop_dma(struct s3c_post_control *ctrl) ++{ ++ s3c_post_stop_input_dma(ctrl); ++ s3c_post_stop_scaler(ctrl); ++ s3c_post_disable_capture(ctrl); ++ s3c_post_wait_frame_end(ctrl); ++} ++ ++void s3c_post_restart_dma(struct s3c_post_control *ctrl) ++{ ++ s3c_post_stop_dma(ctrl); ++ s3c_post_start_dma(ctrl); ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/post/s3c_post_core.c linux-2.6.28.6/drivers/media/video/samsung/post/s3c_post_core.c +--- linux-2.6.28/drivers/media/video/samsung/post/s3c_post_core.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/post/s3c_post_core.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,369 @@ ++/* linux/drivers/media/video/samsung/s3c_post_core.c ++ * ++ * Core file for Samsung Post Processor driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "s3c_post.h" ++ ++struct s3c_post_config s3c_post; ++ ++struct s3c_platform_post *to_post_plat(struct device *dev) ++{ ++ struct platform_device *pdev = to_platform_device(dev); ++ ++ return (struct s3c_platform_post *) pdev->dev.platform_data; ++} ++ ++static irqreturn_t s3c_post_irq(int irq, void *dev_id) ++{ ++ struct s3c_post_control *ctrl = (struct s3c_post_control *) dev_id; ++ ++ s3c_post_clear_irq(ctrl); ++ ++ return IRQ_HANDLED; ++} ++ ++static ++struct s3c_post_control *s3c_post_register_controller(struct platform_device *pdev) ++{ ++ struct s3c_platform_post *pdata; ++ struct s3c_post_control *ctrl; ++ struct resource *res; ++ int id = pdev->id; ++ ++ pdata = to_post_plat(&pdev->dev); ++ ++ ctrl = &s3c_post.ctrl; ++ ctrl->id = id; ++ ctrl->dev = &pdev->dev; ++ ctrl->vd = &s3c_post_video_device; ++ ctrl->vd->minor = S3C_POST_MINOR; ++ ctrl->out_frame.nr_frames = pdata->nr_frames; ++ ctrl->scaler.line_length = pdata->line_length; ++ ++ sprintf(ctrl->name, "%s", S3C_POST_NAME); ++ strcpy(ctrl->vd->name, ctrl->name); ++ ++ ctrl->open_lcdfifo = s3cfb_enable_local; ++ ctrl->close_lcdfifo = s3cfb_enable_dma; ++ ++ atomic_set(&ctrl->in_use, 0); ++ mutex_init(&ctrl->lock); ++ init_waitqueue_head(&ctrl->waitq); ++ ++ /* get resource for io memory */ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ err("failed to get io memory region\n"); ++ return NULL; ++ } ++ ++ /* request mem region */ ++ res = request_mem_region(res->start, res->end - res->start + 1, pdev->name); ++ if (!res) { ++ err("failed to request io memory region\n"); ++ return NULL; ++ } ++ ++ /* ioremap for register block */ ++ ctrl->regs = ioremap(res->start, res->end - res->start + 1); ++ if (!ctrl->regs) { ++ err("failed to remap io region\n"); ++ return NULL; ++ } ++ ++ /* irq */ ++ ctrl->irq = platform_get_irq(pdev, 0); ++ if (request_irq(ctrl->irq, s3c_post_irq, IRQF_DISABLED, ctrl->name, ctrl)) ++ err("request_irq failed\n"); ++ ++ s3c_post_reset(ctrl); ++ ++ return ctrl; ++} ++ ++static int s3c_post_unregister_controller(struct platform_device *pdev) ++{ ++ struct s3c_post_control *ctrl; ++ struct s3c_platform_post *pdata; ++ ++ ctrl = &s3c_post.ctrl; ++ ++ s3c_post_free_output_memory(&ctrl->out_frame); ++ ++ pdata = to_post_plat(ctrl->dev); ++ ++ iounmap(ctrl->regs); ++ memset(ctrl, 0, sizeof(*ctrl)); ++ ++ return 0; ++} ++ ++static int s3c_post_mmap(struct file* filp, struct vm_area_struct *vma) ++{ ++ struct s3c_post_control *ctrl = filp->private_data; ++ struct s3c_post_out_frame *frame = &ctrl->out_frame; ++ ++ u32 size = vma->vm_end - vma->vm_start; ++ u32 pfn, total_size = frame->buf_size; ++ ++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ vma->vm_flags |= VM_RESERVED; ++ ++ /* page frame number of the address for a source frame to be stored at. */ ++ pfn = __phys_to_pfn(frame->addr[vma->vm_pgoff].phys_y); ++ ++ if (size > total_size) { ++ err("the size of mapping is too big\n"); ++ return -EINVAL; ++ } ++ ++ if ((vma->vm_flags & VM_WRITE) && !(vma->vm_flags & VM_SHARED)) { ++ err("writable mapping must be shared\n"); ++ return -EINVAL; ++ } ++ ++ if (remap_pfn_range(vma, vma->vm_start, pfn, size, vma->vm_page_prot)) { ++ err("mmap fail\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static u32 s3c_post_poll(struct file *filp, poll_table *wait) ++{ ++ struct s3c_post_control *ctrl = filp->private_data; ++ u32 mask = 0; ++ ++ poll_wait(filp, &ctrl->waitq, wait); ++ ++ /* fixme */ ++ mask = POLLIN | POLLRDNORM; ++ ++ return mask; ++} ++ ++static ++ssize_t s3c_post_read(struct file *filp, char *buf, size_t count, loff_t *pos) ++{ ++ struct s3c_post_control *ctrl = filp->private_data; ++ size_t end; ++ ++ end = min_t(size_t, ctrl->out_frame.buf_size, count); ++ ++ if (copy_to_user(buf, s3c_post_get_current_frame(ctrl), end)) ++ return -EFAULT; ++ ++ return end; ++} ++ ++static ++ssize_t s3c_post_write(struct file *filp, const char *b, size_t c, loff_t *offset) ++{ ++ return 0; ++} ++ ++static int s3c_post_open(struct inode *inode, struct file *filp) ++{ ++ struct s3c_post_control *ctrl; ++ int ret; ++ ++ ctrl = &s3c_post.ctrl; ++ ++ mutex_lock(&ctrl->lock); ++ ++ if (atomic_read(&ctrl->in_use)) { ++ ret = -EBUSY; ++ goto resource_busy; ++ } else { ++ atomic_inc(&ctrl->in_use); ++ s3c_post_reset(ctrl); ++ filp->private_data = ctrl; ++ } ++ ++ mutex_unlock(&ctrl->lock); ++ ++ return 0; ++ ++resource_busy: ++ mutex_unlock(&ctrl->lock); ++ return ret; ++} ++ ++static int s3c_post_release(struct inode *inode, struct file *filp) ++{ ++ struct s3c_post_control *ctrl; ++ ++ ctrl = &s3c_post.ctrl; ++ ++ mutex_lock(&ctrl->lock); ++ ++ atomic_dec(&ctrl->in_use); ++ filp->private_data = NULL; ++ ++ mutex_unlock(&ctrl->lock); ++ ++ return 0; ++} ++ ++static const struct file_operations s3c_post_fops = { ++ .owner = THIS_MODULE, ++ .open = s3c_post_open, ++ .release = s3c_post_release, ++ .ioctl = video_ioctl2, ++ .read = s3c_post_read, ++ .write = s3c_post_write, ++ .mmap = s3c_post_mmap, ++ .poll = s3c_post_poll, ++}; ++ ++static void s3c_post_vdev_release(struct video_device *vdev) ++{ ++ kfree(vdev); ++} ++ ++struct video_device s3c_post_video_device = { ++ .vfl_type = VID_TYPE_CAPTURE | VID_TYPE_CLIPPING | VID_TYPE_SCALES, ++ .fops = &s3c_post_fops, ++ .ioctl_ops = &s3c_post_v4l2_ops, ++ .release = s3c_post_vdev_release, ++}; ++ ++static int s3c_post_init_global(struct platform_device *pdev) ++{ ++ s3c_post.dma_start = s3c_get_media_memory(S3C_MDEV_POST); ++ s3c_post.dma_total = s3c_get_media_memsize(S3C_MDEV_POST); ++ s3c_post.dma_current = s3c_post.dma_start; ++ ++ return 0; ++} ++ ++static int s3c_post_probe(struct platform_device *pdev) ++{ ++ struct s3c_platform_post *pdata; ++ struct s3c_post_control *ctrl; ++ int ret; ++ ++ ctrl = s3c_post_register_controller(pdev); ++ if (!ctrl) { ++ err("cannot register post controller\n"); ++ goto err_post; ++ } ++ ++ pdata = to_post_plat(&pdev->dev); ++ if (pdata->cfg_gpio) ++ pdata->cfg_gpio(pdev); ++ ++ /* post clock */ ++ ctrl->clock = clk_get(&pdev->dev, pdata->clk_name); ++ if (IS_ERR(ctrl->clock)) { ++ err("failed to get post clock source\n"); ++ goto err_clk_io; ++ } ++ /* set clockrate for POST interface block */ ++ if (ctrl->clock->set_rate) ++ ctrl->clock->set_rate(ctrl->clock, pdata->clockrate); ++ ++ clk_enable(ctrl->clock); ++ ++ /* things to initialize once */ ++ ret = s3c_post_init_global(pdev); ++ if (ret) ++ goto err_global; ++ ++ ret = video_register_device(ctrl->vd, VFL_TYPE_GRABBER, pdev->id); ++ if (ret) { ++ err("cannot register video driver\n"); ++ goto err_video; ++ } ++ ++ info("registered successfully\n"); ++ ++ return 0; ++ ++err_video: ++err_global: ++ clk_disable(ctrl->clock); ++ clk_put(ctrl->clock); ++ ++err_clk_io: ++ s3c_post_unregister_controller(pdev); ++ ++err_post: ++ return -EINVAL; ++ ++} ++ ++static int s3c_post_remove(struct platform_device *pdev) ++{ ++ s3c_post_unregister_controller(pdev); ++ ++ return 0; ++} ++ ++int s3c_post_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ return 0; ++} ++ ++int s3c_post_resume(struct platform_device *dev) ++{ ++ return 0; ++} ++ ++static struct platform_driver s3c_post_driver = { ++ .probe = s3c_post_probe, ++ .remove = s3c_post_remove, ++ .suspend = s3c_post_suspend, ++ .resume = s3c_post_resume, ++ .driver = { ++ .name = "s3c-post", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int s3c_post_register(void) ++{ ++ platform_driver_register(&s3c_post_driver); ++ ++ return 0; ++} ++ ++static void s3c_post_unregister(void) ++{ ++ platform_driver_unregister(&s3c_post_driver); ++} ++ ++module_init(s3c_post_register); ++module_exit(s3c_post_unregister); ++ ++MODULE_AUTHOR("Jinsung, Yang "); ++MODULE_DESCRIPTION("Samsung Post Processor driver"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/post/s3c_post_regs.c linux-2.6.28.6/drivers/media/video/samsung/post/s3c_post_regs.c +--- linux-2.6.28/drivers/media/video/samsung/post/s3c_post_regs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/post/s3c_post_regs.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,434 @@ ++/* linux/drivers/media/video/samsung/s3c_post_regs.c ++ * ++ * Register interface file for Samsung Post Processor driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "s3c_post.h" ++ ++void s3c_post_clear_irq(struct s3c_post_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CIGCTRL); ++ ++ cfg |= S3C_CIGCTRL_IRQ_CLR; ++ ++ writel(cfg, ctrl->regs + S3C_CIGCTRL); ++} ++ ++static void s3c_post_reset_cfg(struct s3c_post_control *ctrl) ++{ ++ int i; ++ u32 cfg[][2] = { ++ { 0x018, 0x00000000 }, { 0x01c, 0x00000000 }, ++ { 0x020, 0x00000000 }, { 0x024, 0x00000000 }, ++ { 0x028, 0x00000000 }, { 0x02c, 0x00000000 }, ++ { 0x030, 0x00000000 }, { 0x034, 0x00000000 }, ++ { 0x038, 0x00000000 }, { 0x03c, 0x00000000 }, ++ { 0x040, 0x00000000 }, { 0x044, 0x00000000 }, ++ { 0x048, 0x00000000 }, { 0x04c, 0x00000000 }, ++ { 0x050, 0x00000000 }, { 0x054, 0x00000000 }, ++ { 0x058, 0x18000000 }, { 0x05c, 0x00000000 }, ++ { 0x0c0, 0x00000000 }, { 0x0c4, 0xffffffff }, ++ { 0x0d0, 0x00100080 }, { 0x0d4, 0x00000000 }, ++ { 0x0d8, 0x00000000 }, { 0x0dc, 0x00000000 }, ++ { 0x0f8, 0x00000000 }, { 0x0fc, 0x04000000 }, ++ { 0x144, 0x00000000 }, { 0x148, 0x00000000 }, ++ { 0x14c, 0x00000000 }, { 0x168, 0x00000000 }, ++ { 0x16c, 0x00000000 }, { 0x170, 0x00000000 }, ++ { 0x174, 0x00000000 }, { 0x178, 0x00000000 }, ++ { 0x17c, 0x00000000 }, { 0x180, 0x00000000 }, ++ { 0x184, 0x00000000 }, { 0x188, 0x00000000 }, ++ { 0x18c, 0x00000000 }, ++ }; ++ ++ for (i = 0; i < sizeof(cfg) / 8; i++) ++ writel(cfg[i][1], ctrl->regs + cfg[i][0]); ++} ++ ++void s3c_post_reset(struct s3c_post_control *ctrl) ++{ ++ u32 cfg; ++ ++ /* s/w reset */ ++ cfg = readl(ctrl->regs + S3C_CIGCTRL); ++ cfg |= (S3C_CIGCTRL_SWRST | S3C_CIGCTRL_IRQ_LEVEL); ++ writel(cfg, ctrl->regs + S3C_CIGCTRL); ++ mdelay(1); ++ ++ cfg = readl(ctrl->regs + S3C_CIGCTRL); ++ cfg &= ~S3C_CIGCTRL_SWRST; ++ writel(cfg, ctrl->regs + S3C_CIGCTRL); ++ ++ s3c_post_reset_cfg(ctrl); ++} ++ ++void s3c_post_set_target_format(struct s3c_post_control *ctrl) ++{ ++ struct s3c_post_out_frame *frame = &ctrl->out_frame; ++ u32 cfg = 0; ++ ++ switch (frame->format) { ++ case FORMAT_RGB565: /* fall through */ ++ case FORMAT_RGB666: /* fall through */ ++ case FORMAT_RGB888: ++ cfg |= S3C_CITRGFMT_OUTFORMAT_RGB; ++ break; ++ ++ case FORMAT_YCBCR420: ++ cfg |= S3C_CITRGFMT_OUTFORMAT_YCBCR420; ++ break; ++ ++ case FORMAT_YCBCR422: ++ if (frame->planes == 1) ++ cfg |= S3C_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE; ++ else ++ cfg |= S3C_CITRGFMT_OUTFORMAT_YCBCR422; ++ ++ break; ++ } ++ ++ cfg |= S3C_CITRGFMT_TARGETHSIZE(frame->width); ++ cfg |= S3C_CITRGFMT_TARGETVSIZE(frame->height); ++ ++ writel(cfg, ctrl->regs + S3C_CITRGFMT); ++ ++ cfg = S3C_CITAREA_TARGET_AREA(frame->width * frame->height); ++ writel(cfg, ctrl->regs + S3C_CITAREA); ++} ++ ++static void s3c_post_set_output_dma_size(struct s3c_post_control *ctrl) ++{ ++ struct s3c_post_out_frame *frame = &ctrl->out_frame; ++ int ofs_h = frame->offset.y_h * 2; ++ int ofs_v = frame->offset.y_v * 2; ++ u32 cfg = 0; ++ ++ cfg |= S3C_ORGOSIZE_HORIZONTAL(frame->width - ofs_h); ++ cfg |= S3C_ORGOSIZE_VERTICAL(frame->height - ofs_v); ++ ++ writel(cfg, ctrl->regs + S3C_ORGOSIZE); ++} ++ ++void s3c_post_set_output_dma(struct s3c_post_control *ctrl) ++{ ++ struct s3c_post_out_frame *frame = &ctrl->out_frame; ++ u32 cfg; ++ ++ /* for offsets */ ++ cfg = 0; ++ cfg |= S3C_CIOYOFF_HORIZONTAL(frame->offset.y_h); ++ cfg |= S3C_CIOYOFF_VERTICAL(frame->offset.y_v); ++ writel(cfg, ctrl->regs + S3C_CIOYOFF); ++ ++ cfg = 0; ++ cfg |= S3C_CIOCBOFF_HORIZONTAL(frame->offset.cb_h); ++ cfg |= S3C_CIOCBOFF_VERTICAL(frame->offset.cb_v); ++ writel(cfg, ctrl->regs + S3C_CIOCBOFF); ++ ++ cfg = 0; ++ cfg |= S3C_CIOCROFF_HORIZONTAL(frame->offset.cr_h); ++ cfg |= S3C_CIOCROFF_VERTICAL(frame->offset.cr_v); ++ writel(cfg, ctrl->regs + S3C_CIOCROFF); ++ ++ /* for original size */ ++ s3c_post_set_output_dma_size(ctrl); ++ ++ /* for output dma control */ ++ cfg = readl(ctrl->regs + S3C_CIOCTRL); ++ ++ cfg &= ~(S3C_CIOCTRL_ORDER2P_MASK | S3C_CIOCTRL_ORDER422_MASK | \ ++ S3C_CIOCTRL_YCBCR_PLANE_MASK); ++ ++ if (frame->planes == 1) ++ cfg |= frame->order_1p; ++ else if (frame->planes == 2) ++ cfg |= (S3C_CIOCTRL_YCBCR_2PLANE | \ ++ (frame->order_2p << S3C_CIOCTRL_ORDER2P_SHIFT)); ++ else if (frame->planes == 3) ++ cfg |= S3C_CIOCTRL_YCBCR_3PLANE; ++ ++ writel(cfg, ctrl->regs + S3C_CIOCTRL); ++} ++ ++void s3c_post_set_prescaler(struct s3c_post_control *ctrl) ++{ ++ struct s3c_post_scaler *sc = &ctrl->scaler; ++ u32 cfg = 0, shfactor; ++ ++ shfactor = 10 - (sc->hfactor + sc->vfactor); ++ ++ cfg |= S3C_CISCPRERATIO_SHFACTOR(shfactor); ++ cfg |= S3C_CISCPRERATIO_PREHORRATIO(sc->pre_hratio); ++ cfg |= S3C_CISCPRERATIO_PREVERRATIO(sc->pre_vratio); ++ ++ writel(cfg, ctrl->regs + S3C_CISCPRERATIO); ++ ++ cfg = 0; ++ cfg |= S3C_CISCPREDST_PREDSTWIDTH(sc->pre_dst_width); ++ cfg |= S3C_CISCPREDST_PREDSTHEIGHT(sc->pre_dst_height); ++ ++ writel(cfg, ctrl->regs + S3C_CISCPREDST); ++} ++ ++void s3c_post_set_scaler(struct s3c_post_control *ctrl) ++{ ++ struct s3c_post_scaler *sc = &ctrl->scaler; ++ u32 cfg = (S3C_CISCCTRL_CSCR2Y_WIDE | S3C_CISCCTRL_CSCY2R_WIDE); ++ ++ if (sc->scaleup_h) ++ cfg |= S3C_CISCCTRL_SCALEUP_H; ++ ++ if (sc->scaleup_v) ++ cfg |= S3C_CISCCTRL_SCALEUP_V; ++ ++ if (ctrl->in_frame.format == FORMAT_RGB565) ++ cfg |= S3C_CISCCTRL_INRGB_FMT_RGB565; ++ else if (ctrl->in_frame.format == FORMAT_RGB666) ++ cfg |= S3C_CISCCTRL_INRGB_FMT_RGB666; ++ else if (ctrl->in_frame.format == FORMAT_RGB888) ++ cfg |= S3C_CISCCTRL_INRGB_FMT_RGB888; ++ ++ if (ctrl->out_type == PATH_OUT_DMA) { ++ if (ctrl->out_frame.format == FORMAT_RGB565) ++ cfg |= S3C_CISCCTRL_OUTRGB_FMT_RGB565; ++ else if (ctrl->out_frame.format == FORMAT_RGB666) ++ cfg |= S3C_CISCCTRL_OUTRGB_FMT_RGB666; ++ else if (ctrl->out_frame.format == FORMAT_RGB888) ++ cfg |= S3C_CISCCTRL_OUTRGB_FMT_RGB888; ++ } else { ++ cfg |= S3C_CISCCTRL_OUTRGB_FMT_RGB888; ++ ++ if (ctrl->out_frame.scan == SCAN_TYPE_INTERLACE) ++ cfg |= S3C_CISCCTRL_INTERLACE; ++ else ++ cfg |= S3C_CISCCTRL_PROGRESSIVE; ++ } ++ ++ cfg |= S3C_CISCCTRL_MAINHORRATIO(sc->main_hratio); ++ cfg |= S3C_CISCCTRL_MAINVERRATIO(sc->main_vratio); ++ ++ writel(cfg, ctrl->regs + S3C_CISCCTRL); ++} ++ ++void s3c_post_start_scaler(struct s3c_post_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CISCCTRL); ++ ++ cfg |= S3C_CISCCTRL_SCALERSTART; ++ writel(cfg, ctrl->regs + S3C_CISCCTRL); ++ ++ if (ctrl->out_type == PATH_OUT_LCDFIFO) ++ ctrl->open_lcdfifo(ctrl->id, 0, 0); ++} ++ ++void s3c_post_stop_scaler(struct s3c_post_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CISCCTRL); ++ ++ if (ctrl->out_type == PATH_OUT_LCDFIFO) ++ ctrl->close_lcdfifo(ctrl->id); ++ ++ cfg &= ~S3C_CISCCTRL_SCALERSTART; ++ writel(cfg, ctrl->regs + S3C_CISCCTRL); ++} ++ ++void s3c_post_enable_capture(struct s3c_post_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CIIMGCPT); ++ ++ cfg &= ~S3C_CIIMGCPT_CPT_FREN_ENABLE; ++ cfg |= (S3C_CIIMGCPT_IMGCPTEN | S3C_CIIMGCPT_IMGCPTEN_SC); ++ ++ writel(cfg, ctrl->regs + S3C_CIIMGCPT); ++} ++ ++void s3c_post_disable_capture(struct s3c_post_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CIIMGCPT); ++ ++ cfg &= ~(S3C_CIIMGCPT_IMGCPTEN | S3C_CIIMGCPT_IMGCPTEN_SC); ++ writel(cfg, ctrl->regs + S3C_CIIMGCPT); ++} ++ ++static void s3c_post_set_input_dma_size(struct s3c_post_control *ctrl) ++{ ++ struct s3c_post_in_frame *frame = &ctrl->in_frame; ++ int ofs_h = frame->offset.y_h * 2; ++ int ofs_v = frame->offset.y_v * 2; ++ u32 cfg_o = 0, cfg_r = S3C_CIREAL_ISIZE_AUTOLOAD_ENABLE; ++ ++ cfg_o |= S3C_ORGISIZE_HORIZONTAL(frame->width - ofs_h); ++ cfg_o |= S3C_ORGISIZE_VERTICAL(frame->height - ofs_v); ++ cfg_r |= S3C_CIREAL_ISIZE_WIDTH(frame->width - ofs_h); ++ cfg_r |= S3C_CIREAL_ISIZE_HEIGHT(frame->height - ofs_v); ++ ++ writel(cfg_o, ctrl->regs + S3C_ORGISIZE); ++ writel(cfg_r, ctrl->regs + S3C_CIREAL_ISIZE); ++} ++ ++void s3c_post_set_input_dma(struct s3c_post_control *ctrl) ++{ ++ struct s3c_post_in_frame *frame = &ctrl->in_frame; ++ u32 cfg; ++ ++ /* for offsets */ ++ cfg = 0; ++ cfg |= S3C_CIIYOFF_HORIZONTAL(frame->offset.y_h); ++ cfg |= S3C_CIIYOFF_VERTICAL(frame->offset.y_v); ++ writel(cfg, ctrl->regs + S3C_CIIYOFF); ++ ++ cfg = 0; ++ cfg |= S3C_CIICBOFF_HORIZONTAL(frame->offset.cb_h); ++ cfg |= S3C_CIICBOFF_VERTICAL(frame->offset.cb_v); ++ writel(cfg, ctrl->regs + S3C_CIICBOFF); ++ ++ cfg = 0; ++ cfg |= S3C_CIICROFF_HORIZONTAL(frame->offset.cr_h); ++ cfg |= S3C_CIICROFF_VERTICAL(frame->offset.cr_v); ++ writel(cfg, ctrl->regs + S3C_CIICROFF); ++ ++ /* for original & real size */ ++ s3c_post_set_input_dma_size(ctrl); ++ ++ /* for input dma control */ ++ cfg = S3C_MSCTRL_SUCCESSIVE_COUNT(4); ++ ++ switch (frame->format) { ++ case FORMAT_RGB565: /* fall through */ ++ case FORMAT_RGB666: /* fall through */ ++ case FORMAT_RGB888: ++ cfg |= S3C_MSCTRL_INFORMAT_RGB; ++ break; ++ ++ case FORMAT_YCBCR420: ++ cfg |= S3C_MSCTRL_INFORMAT_YCBCR420; ++ ++ if (frame->planes == 2) ++ cfg |= (S3C_MSCTRL_C_INT_IN_2PLANE | \ ++ (frame->order_2p << S3C_MSCTRL_2PLANE_SHIFT)); ++ else ++ cfg |= S3C_MSCTRL_C_INT_IN_3PLANE; ++ ++ break; ++ ++ case FORMAT_YCBCR422: ++ if (frame->planes == 1) ++ cfg |= (frame->order_1p | \ ++ S3C_MSCTRL_INFORMAT_YCBCR422_1PLANE); ++ else { ++ cfg |= S3C_MSCTRL_INFORMAT_YCBCR422; ++ ++ if (frame->planes == 2) ++ cfg |= (S3C_MSCTRL_C_INT_IN_2PLANE | \ ++ (frame->order_2p << S3C_MSCTRL_2PLANE_SHIFT)); ++ else ++ cfg |= S3C_MSCTRL_C_INT_IN_3PLANE; ++ } ++ ++ break; ++ } ++ ++ writel(cfg, ctrl->regs + S3C_MSCTRL); ++} ++ ++void s3c_post_start_input_dma(struct s3c_post_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_MSCTRL); ++ ++ cfg |= S3C_MSCTRL_ENVID; ++ writel(cfg, ctrl->regs + S3C_MSCTRL); ++} ++ ++void s3c_post_stop_input_dma(struct s3c_post_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_MSCTRL); ++ ++ cfg &= ~S3C_MSCTRL_ENVID; ++ writel(cfg, ctrl->regs + S3C_MSCTRL); ++} ++ ++void s3c_post_set_output_path(struct s3c_post_control *ctrl) ++{ ++ u32 cfg = readl(ctrl->regs + S3C_CISCCTRL); ++ ++ cfg &= ~S3C_CISCCTRL_LCDPATHEN_FIFO; ++ ++ if (ctrl->out_type == PATH_OUT_LCDFIFO) ++ cfg |= S3C_CISCCTRL_LCDPATHEN_FIFO; ++ ++ writel(cfg, ctrl->regs + S3C_CISCCTRL); ++} ++ ++void s3c_post_set_input_address(struct s3c_post_control *ctrl) ++{ ++ struct s3c_post_frame_addr *addr = &ctrl->in_frame.addr; ++ u32 cfg = 0; ++ ++ cfg = readl(ctrl->regs + S3C_CIREAL_ISIZE); ++ cfg |= S3C_CIREAL_ISIZE_ADDR_CH_DISABLE; ++ writel(cfg, ctrl->regs + S3C_CIREAL_ISIZE); ++ ++ writel(addr->phys_y, ctrl->regs + S3C_CIIYSA0); ++ writel(addr->phys_cb, ctrl->regs + S3C_CIICBSA0); ++ writel(addr->phys_cr, ctrl->regs + S3C_CIICRSA0); ++ ++ cfg &= ~S3C_CIREAL_ISIZE_ADDR_CH_DISABLE; ++ writel(cfg, ctrl->regs + S3C_CIREAL_ISIZE); ++} ++ ++void s3c_post_set_output_address(struct s3c_post_control *ctrl) ++{ ++ struct s3c_post_out_frame *frame = &ctrl->out_frame; ++ struct s3c_post_frame_addr *addr; ++ int i; ++ ++ for (i = 0; i < S3C_POST_MAX_FRAMES; i++) { ++ addr = &frame->addr[i]; ++ writel(addr->phys_y, ctrl->regs + S3C_CIOYSA(i)); ++ writel(addr->phys_cb, ctrl->regs + S3C_CIOCBSA(i)); ++ writel(addr->phys_cr, ctrl->regs + S3C_CIOCRSA(i)); ++ } ++} ++ ++int s3c_post_get_frame_count(struct s3c_post_control *ctrl) ++{ ++ return S3C_CISTATUS_GET_FRAME_COUNT(readl(ctrl->regs + S3C_CISTATUS)); ++} ++ ++void s3c_post_wait_frame_end(struct s3c_post_control *ctrl) ++{ ++ unsigned long timeo = jiffies; ++ unsigned int frame_cnt = 0; ++ u32 cfg; ++ ++ timeo += 20; /* waiting for 100mS */ ++ ++ while (time_before(jiffies, timeo)) { ++ cfg = readl(ctrl->regs + S3C_CISTATUS); ++ ++ if (S3C_CISTATUS_GET_FRAME_END(cfg)) { ++ cfg &= ~S3C_CISTATUS_FRAMEEND; ++ writel(cfg, ctrl->regs + S3C_CISTATUS); ++ ++ if (frame_cnt == 2) ++ break; ++ else ++ frame_cnt++; ++ } ++ cond_resched(); ++ } ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/post/s3c_post_v4l2.c linux-2.6.28.6/drivers/media/video/samsung/post/s3c_post_v4l2.c +--- linux-2.6.28/drivers/media/video/samsung/post/s3c_post_v4l2.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/post/s3c_post_v4l2.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,400 @@ ++/* linux/drivers/media/video/samsung/s3c_post_v4l2.c ++ * ++ * V4L2 interface support file for Samsung Post Processor driver ++ * ++ * Jinsung Yang, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "s3c_post.h" ++ ++static struct v4l2_input s3c_post_input_types[] = { ++ { ++ .index = 0, ++ .name = "Memory Input", ++ .type = V4L2_INPUT_TYPE_MEMORY, ++ .audioset = 2, ++ .tuner = 0, ++ .std = V4L2_STD_PAL_BG | V4L2_STD_NTSC_M, ++ .status = 0, ++ } ++}; ++ ++static struct v4l2_output s3c_post_output_types[] = { ++ { ++ .index = 0, ++ .name = "Memory Output", ++ .type = V4L2_OUTPUT_TYPE_MEMORY, ++ .audioset = 0, ++ .modulator = 0, ++ .std = 0, ++ }, ++ { ++ .index = 1, ++ .name = "LCD FIFO Output", ++ .type = V4L2_OUTPUT_TYPE_LCDFIFO, ++ .audioset = 0, ++ .modulator = 0, ++ .std = 0, ++ } ++}; ++ ++const static struct v4l2_fmtdesc s3c_post_capture_formats[] = { ++ { ++ .index = 0, ++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, ++ .flags = FORMAT_FLAGS_PLANAR, ++ .description = "4:2:0, planar, Y-Cb-Cr", ++ .pixelformat = V4L2_PIX_FMT_YUV420, ++ }, ++ { ++ .index = 1, ++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, ++ .flags = FORMAT_FLAGS_PLANAR, ++ .description = "4:2:2, planar, Y-Cb-Cr", ++ .pixelformat = V4L2_PIX_FMT_YUV422P, ++ ++ }, ++ { ++ .index = 2, ++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, ++ .flags = FORMAT_FLAGS_PACKED, ++ .description = "4:2:2, packed, YCBYCR", ++ .pixelformat = V4L2_PIX_FMT_YUYV, ++ }, ++ { ++ .index = 3, ++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, ++ .flags = FORMAT_FLAGS_PACKED, ++ .description = "4:2:2, packed, CBYCRY", ++ .pixelformat = V4L2_PIX_FMT_UYVY, ++ } ++}; ++ ++#define S3C_POST_MAX_INPUT_TYPES ARRAY_SIZE(s3c_post_input_types) ++#define S3C_POST_MAX_OUTPUT_TYPES ARRAY_SIZE(s3c_post_output_types) ++#define S3C_POST_MAX_CAPTURE_FORMATS ARRAY_SIZE(s3c_post_capture_formats) ++ ++static int s3c_post_v4l2_querycap(struct file *filp, void *fh, ++ struct v4l2_capability *cap) ++{ ++ struct s3c_post_control *ctrl = (struct s3c_post_control *) fh; ++ ++ strcpy(cap->driver, "Samsung Post Processor Driver"); ++ strlcpy(cap->card, ctrl->vd->name, sizeof(cap->card)); ++ sprintf(cap->bus_info, "AHB-bus"); ++ ++ cap->version = 0; ++ cap->capabilities = (V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING); ++ ++ return 0; ++} ++ ++static int s3c_post_v4l2_enum_fmt_vid_cap(struct file *filp, void *fh, ++ struct v4l2_fmtdesc *f) ++{ ++ struct s3c_post_control *ctrl = (struct s3c_post_control *) fh; ++ int index = f->index; ++ ++ if (index >= S3C_POST_MAX_CAPTURE_FORMATS) ++ return -EINVAL; ++ ++ memset(f, 0, sizeof(*f)); ++ memcpy(f, ctrl->v4l2.fmtdesc + index, sizeof(*f)); ++ ++ return 0; ++} ++ ++static int s3c_post_v4l2_g_fmt_vid_cap(struct file *filp, void *fh, ++ struct v4l2_format *f) ++{ ++ struct s3c_post_control *ctrl = (struct s3c_post_control *) fh; ++ int size = sizeof(struct v4l2_pix_format); ++ ++ memset(&f->fmt.pix, 0, size); ++ memcpy(&f->fmt.pix, &(ctrl->v4l2.frmbuf.fmt), size); ++ ++ return 0; ++} ++ ++static int s3c_post_v4l2_s_fmt_vid_cap(struct file *filp, void *fh, ++ struct v4l2_format *f) ++{ ++ struct s3c_post_control *ctrl = (struct s3c_post_control *) fh; ++ ++ ctrl->v4l2.frmbuf.fmt = f->fmt.pix; ++ ++ if (f->fmt.pix.priv == V4L2_FMT_IN) ++ s3c_post_set_input_frame(ctrl, &f->fmt.pix); ++ else ++ s3c_post_set_output_frame(ctrl, &f->fmt.pix); ++ ++ return 0; ++} ++ ++static int s3c_post_v4l2_try_fmt_vid_cap(struct file *filp, void *fh, ++ struct v4l2_format *f) ++{ ++ return 0; ++} ++ ++static int s3c_post_v4l2_g_ctrl(struct file *filp, void *fh, ++ struct v4l2_control *c) ++{ ++ struct s3c_post_control *ctrl = (struct s3c_post_control *) fh; ++ struct s3c_post_out_frame *frame = &ctrl->out_frame; ++ ++ switch (c->id) { ++ case V4L2_CID_OUTPUT_ADDR: ++ c->value = frame->addr[c->value].phys_y; ++ break; ++ ++ default: ++ err("invalid control id: %d\n", c->id); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int s3c_post_v4l2_s_ctrl(struct file *filp, void *fh, ++ struct v4l2_control *c) ++{ ++ struct s3c_post_control *ctrl = (struct s3c_post_control *) fh; ++ ++ switch (c->id) { ++ case V4L2_CID_NR_FRAMES: ++ s3c_post_set_nr_frames(ctrl, c->value); ++ break; ++ ++ case V4L2_CID_INPUT_ADDR: ++ s3c_post_alloc_input_memory(&ctrl->in_frame, \ ++ (dma_addr_t) c->value); ++ s3c_post_set_input_address(ctrl); ++ break; ++ ++ case V4L2_CID_INPUT_ADDR_Y: ++ case V4L2_CID_INPUT_ADDR_RGB: ++ s3c_post_alloc_y_memory(&ctrl->in_frame, \ ++ (dma_addr_t) c->value); ++ s3c_post_set_input_address(ctrl); ++ break; ++ ++ case V4L2_CID_INPUT_ADDR_CB: /* fall through */ ++ case V4L2_CID_INPUT_ADDR_CBCR: ++ s3c_post_alloc_cb_memory(&ctrl->in_frame, \ ++ (dma_addr_t) c->value); ++ s3c_post_set_input_address(ctrl); ++ break; ++ ++ case V4L2_CID_INPUT_ADDR_CR: ++ s3c_post_alloc_cr_memory(&ctrl->in_frame, \ ++ (dma_addr_t) c->value); ++ s3c_post_set_input_address(ctrl); ++ break; ++ ++ case V4L2_CID_RESET: ++ s3c_post_reset(ctrl); ++ break; ++ ++ default: ++ err("invalid control id: %d\n", c->id); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int s3c_post_v4l2_streamon(struct file *filp, void *fh, ++ enum v4l2_buf_type i) ++{ ++ struct s3c_post_control *ctrl = (struct s3c_post_control *) fh; ++ ++ if (i != V4L2_BUF_TYPE_VIDEO_CAPTURE) ++ return -EINVAL; ++ ++ s3c_post_start_dma(ctrl); ++ ++ return 0; ++} ++ ++static int s3c_post_v4l2_streamoff(struct file *filp, void *fh, ++ enum v4l2_buf_type i) ++{ ++ struct s3c_post_control *ctrl = (struct s3c_post_control *) fh; ++ ++ if (i != V4L2_BUF_TYPE_VIDEO_CAPTURE) ++ return -EINVAL; ++ ++ s3c_post_stop_dma(ctrl); ++ s3c_post_free_output_memory(&ctrl->out_frame); ++ s3c_post_set_output_address(ctrl); ++ ++ return 0; ++} ++ ++static int s3c_post_v4l2_g_input(struct file *filp, void *fh, ++ unsigned int *i) ++{ ++ struct s3c_post_control *ctrl = (struct s3c_post_control *) fh; ++ ++ *i = ctrl->v4l2.input->index; ++ ++ return 0; ++} ++ ++static int s3c_post_v4l2_s_input(struct file *filp, void *fh, ++ unsigned int i) ++{ ++ struct s3c_post_control *ctrl = (struct s3c_post_control *) fh; ++ ++ if (i >= S3C_POST_MAX_INPUT_TYPES) ++ return -EINVAL; ++ ++ ctrl->v4l2.input = &s3c_post_input_types[i]; ++ ++ return 0; ++} ++ ++static int s3c_post_v4l2_g_output(struct file *filp, void *fh, ++ unsigned int *i) ++{ ++ struct s3c_post_control *ctrl = (struct s3c_post_control *) fh; ++ ++ *i = ctrl->v4l2.output->index; ++ ++ return 0; ++} ++ ++static int s3c_post_v4l2_s_output(struct file *filp, void *fh, ++ unsigned int i) ++{ ++ struct s3c_post_control *ctrl = (struct s3c_post_control *) fh; ++ ++ if (i >= S3C_POST_MAX_OUTPUT_TYPES) ++ return -EINVAL; ++ ++ ctrl->v4l2.output = &s3c_post_output_types[i]; ++ ++ if (s3c_post_output_types[i].type == V4L2_OUTPUT_TYPE_MEMORY) ++ ctrl->out_type = PATH_OUT_DMA; ++ else ++ ctrl->out_type = PATH_OUT_LCDFIFO; ++ ++ return 0; ++} ++ ++static int s3c_post_v4l2_enum_input(struct file *filp, void *fh, ++ struct v4l2_input *i) ++{ ++ if (i->index >= S3C_POST_MAX_INPUT_TYPES) ++ return -EINVAL; ++ ++ memcpy(i, &s3c_post_input_types[i->index], sizeof(struct v4l2_input)); ++ ++ return 0; ++} ++ ++static int s3c_post_v4l2_enum_output(struct file *filp, void *fh, ++ struct v4l2_output *o) ++{ ++ if ((o->index) >= S3C_POST_MAX_OUTPUT_TYPES) ++ return -EINVAL; ++ ++ memcpy(o, &s3c_post_output_types[o->index], sizeof(struct v4l2_output)); ++ ++ return 0; ++} ++ ++static int s3c_post_v4l2_reqbufs(struct file *filp, void *fh, ++ struct v4l2_requestbuffers *b) ++{ ++ if (b->memory != V4L2_MEMORY_MMAP) { ++ err("V4L2_MEMORY_MMAP is only supported\n"); ++ return -EINVAL; ++ } ++ ++ if (b->count > 4) ++ b->count = 4; ++ else if (b->count < 1) ++ b->count = 1; ++ ++ return 0; ++} ++ ++static int s3c_post_v4l2_querybuf(struct file *filp, void *fh, ++ struct v4l2_buffer *b) ++{ ++ struct s3c_post_control *ctrl = (struct s3c_post_control *) fh; ++ ++ if (b->type != V4L2_BUF_TYPE_VIDEO_OVERLAY && \ ++ b->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) ++ return -EINVAL; ++ ++ if (b->memory != V4L2_MEMORY_MMAP) ++ return -EINVAL; ++ ++ b->length = ctrl->out_frame.buf_size; ++ ++ /* ++ * NOTE: we use the m.offset as an index for multiple frames out. ++ * Because all frames are not contiguous, we cannot use it as ++ * original purpose. ++ * The index value used to find out which frame user wants to mmap. ++ */ ++ b->m.offset = b->index * PAGE_SIZE; ++ ++ return 0; ++} ++ ++static int s3c_post_v4l2_qbuf(struct file *filp, void *fh, ++ struct v4l2_buffer *b) ++{ ++ return 0; ++} ++ ++static int s3c_post_v4l2_dqbuf(struct file *filp, void *fh, ++ struct v4l2_buffer *b) ++{ ++ struct s3c_post_control *ctrl = (struct s3c_post_control *) fh; ++ struct s3c_post_out_frame *frame = &ctrl->out_frame; ++ ++ ctrl->out_frame.cfn = s3c_post_get_frame_count(ctrl); ++ b->index = (frame->cfn + 2) % frame->nr_frames; ++ ++ return 0; ++} ++ ++const struct v4l2_ioctl_ops s3c_post_v4l2_ops = { ++ .vidioc_querycap = s3c_post_v4l2_querycap, ++ .vidioc_enum_fmt_vid_cap = s3c_post_v4l2_enum_fmt_vid_cap, ++ .vidioc_g_fmt_vid_cap = s3c_post_v4l2_g_fmt_vid_cap, ++ .vidioc_s_fmt_vid_cap = s3c_post_v4l2_s_fmt_vid_cap, ++ .vidioc_try_fmt_vid_cap = s3c_post_v4l2_try_fmt_vid_cap, ++ .vidioc_g_ctrl = s3c_post_v4l2_g_ctrl, ++ .vidioc_s_ctrl = s3c_post_v4l2_s_ctrl, ++ .vidioc_streamon = s3c_post_v4l2_streamon, ++ .vidioc_streamoff = s3c_post_v4l2_streamoff, ++ .vidioc_g_input = s3c_post_v4l2_g_input, ++ .vidioc_s_input = s3c_post_v4l2_s_input, ++ .vidioc_g_output = s3c_post_v4l2_g_output, ++ .vidioc_s_output = s3c_post_v4l2_s_output, ++ .vidioc_enum_input = s3c_post_v4l2_enum_input, ++ .vidioc_enum_output = s3c_post_v4l2_enum_output, ++ .vidioc_reqbufs = s3c_post_v4l2_reqbufs, ++ .vidioc_querybuf = s3c_post_v4l2_querybuf, ++ .vidioc_qbuf = s3c_post_v4l2_qbuf, ++ .vidioc_dqbuf = s3c_post_v4l2_dqbuf, ++}; +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/post/s3c_pp.h linux-2.6.28.6/drivers/media/video/samsung/post/s3c_pp.h +--- linux-2.6.28/drivers/media/video/samsung/post/s3c_pp.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/post/s3c_pp.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,70 @@ ++#ifndef _S3C_PP_H_ ++#define _S3C_PP_H_ ++ ++typedef enum { ++ DMA_ONESHOT, ++ FIFO_FREERUN ++} s3c_pp_out_path_t; ++ ++typedef enum { ++ PAL1, PAL2, PAL4, PAL8, ++ RGB8, ARGB8, RGB16, ARGB16, RGB18, RGB24, RGB30, ARGB24, ++ YC420, YC422, // Non-interleave ++ CRYCBY, CBYCRY, YCRYCB, YCBYCR, YUV444 // Interleave ++} s3c_color_space_t; ++ ++typedef enum { ++ INTERLACE_MODE, ++ PROGRESSIVE_MODE ++} s3c_pp_scan_mode_t; ++ ++ ++// Structure type for IOCTL commands S3C_PP_SET_PARAMS, S3C_PP_SET_INPUT_BUF_START_ADDR_PHY, ++// S3C_PP_SET_INPUT_BUF_NEXT_START_ADDR_PHY, S3C_PP_SET_OUTPUT_BUF_START_ADDR_PHY. ++typedef struct { ++ unsigned int src_full_width; // Source Image Full Width (Virtual screen size) ++ unsigned int src_full_height; // Source Image Full Height (Virtual screen size) ++ unsigned int src_start_x; // Source Image Start width offset ++ unsigned int src_start_y; // Source Image Start height offset ++ unsigned int src_width; // Source Image Width ++ unsigned int src_height; // Source Image Height ++ unsigned int src_buf_addr_phy; // Base Address of the Source Image : Physical Address ++ unsigned int src_next_buf_addr_phy; // Base Address of Source Image to be displayed next time in FIFO_FREERUN Mode ++ s3c_color_space_t src_color_space; // Color Space of the Source Image ++ ++ unsigned int dst_full_width; // Destination Image Full Width (Virtual screen size) ++ unsigned int dst_full_height; // Destination Image Full Height (Virtual screen size) ++ unsigned int dst_start_x; // Destination Image Start width offset ++ unsigned int dst_start_y; // Destination Image Start height offset ++ unsigned int dst_width; // Destination Image Width ++ unsigned int dst_height; // Destination Image Height ++ unsigned int dst_buf_addr_phy; // Base Address of the Destination Image : Physical Address ++ s3c_color_space_t dst_color_space; // Color Space of the Destination Image ++ ++ s3c_pp_out_path_t out_path; // output and run mode (DMA_ONESHOT or FIFO_FREERUN) ++ s3c_pp_scan_mode_t scan_mode; // INTERLACE_MODE, PROGRESSIVE_MODE ++} s3c_pp_params_t; ++ ++// Structure type for IOCTL commands S3C_PP_ALLOC_KMEM, S3C_PP_FREE_KMEM. ++typedef struct { ++ int size; ++ unsigned int vir_addr; ++ unsigned int phy_addr; ++} s3c_pp_mem_alloc_t; ++ ++#define PP_IOCTL_MAGIC 'P' ++ ++#define S3C_PP_SET_PARAMS _IO(PP_IOCTL_MAGIC, 0) ++#define S3C_PP_START _IO(PP_IOCTL_MAGIC, 1) ++#define S3C_PP_GET_SRC_BUF_SIZE _IO(PP_IOCTL_MAGIC, 2) ++#define S3C_PP_SET_SRC_BUF_ADDR_PHY _IO(PP_IOCTL_MAGIC, 3) ++#define S3C_PP_SET_SRC_BUF_NEXT_ADDR_PHY _IO(PP_IOCTL_MAGIC, 4) ++#define S3C_PP_GET_DST_BUF_SIZE _IO(PP_IOCTL_MAGIC, 5) ++#define S3C_PP_SET_DST_BUF_ADDR_PHY _IO(PP_IOCTL_MAGIC, 6) ++#define S3C_PP_ALLOC_KMEM _IO(PP_IOCTL_MAGIC, 7) ++#define S3C_PP_FREE_KMEM _IO(PP_IOCTL_MAGIC, 8) ++#define S3C_PP_GET_RESERVED_MEM_SIZE _IO(PP_IOCTL_MAGIC, 9) ++#define S3C_PP_GET_RESERVED_MEM_ADDR_PHY _IO(PP_IOCTL_MAGIC, 10) ++ ++#endif // _S3C_PP_H_ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/post/s3c_pp_6400.c linux-2.6.28.6/drivers/media/video/samsung/post/s3c_pp_6400.c +--- linux-2.6.28/drivers/media/video/samsung/post/s3c_pp_6400.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/post/s3c_pp_6400.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,1455 @@ ++/* linux/drivers/media/video/samsung/post/s3c_pp_6400.c ++ * ++ * Driver file for Samsung Post processor ++ * ++ * Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* error codes */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "s3c_pp.h" // ioctl ++#include "s3c_pp_common.h" // internal used struct & type ++#include "plat/media.h" ++ ++//#define DEBUG ++ ++#ifdef DEBUG ++#define dprintk printk ++#else ++#define dprintk(format,args...) ++#endif ++ ++#define PFX "s3c_pp" ++ ++typedef unsigned int UINT32; ++ ++// if you want to modify src/dst buffer size, modify below defined size ++#define PP_RESERVED_MEM_SIZE 8*1024*1024 // 8mb ++#define pp_reserved_mem_addr_phy 0x57800000 ++#define PP_RESERVED_MEM_ADDR_PHY (UINT32)s3c_get_media_memory(S3C_MDEV_POST) ++ ++#define ALLOC_KMEM 1 ++ ++#define PP_MAX_NO_OF_INSTANCES 4 ++ ++#define PP_VALUE_CHANGED_NONE 0x00 ++#define PP_VALUE_CHANGED_PARAMS 0x01 ++#define PP_VALUE_CHANGED_SRC_BUF_ADDR_PHY 0x02 ++#define PP_VALUE_CHANGED_DST_BUF_ADDR_PHY 0x04 ++ ++#define PP_INSTANCE_FREE 0 ++#define PP_INSTANCE_READY 1 ++#define PP_INSTANCE_INUSE_DMA_ONESHOT 2 ++#define PP_INSTANCE_INUSE_FIFO_FREERUN 3 ++ ++#define S3C_PP_SAVE_START_ADDR 0x0 ++#define S3C_PP_SAVE_END_ADDR 0xA0 ++static unsigned int s3c_pp_save[S3C_PP_SAVE_END_ADDR - S3C_PP_SAVE_START_ADDR]; ++ ++typedef struct { ++ int running_instance_no; ++ int last_running_instance_no; ++ int fifo_mode_instance_no; ++ unsigned int wincon0_value_before_fifo_mode; ++ int dma_mode_instance_count; ++ int in_use_instance_count; ++ unsigned char instance_state[PP_MAX_NO_OF_INSTANCES]; ++} s3c_pp_instance_info_t; ++ ++static s3c_pp_instance_info_t s3c_pp_instance_info; ++ ++static struct resource *s3c_pp_mem; ++ ++static void __iomem *s3c_pp_base; ++static int s3c_pp_irq = NO_IRQ; ++ ++static struct clk *pp_clock; ++static struct clk *h_clk; ++ ++static struct mutex *h_mutex; ++static struct mutex *mem_alloc_mutex; ++ ++static wait_queue_head_t waitq; ++ ++static int flag = 0; ++ ++static unsigned int physical_address; ++ ++// int FIFO_mode_down_sequence = 0; //. d: sichoi 090112 (FIFO_FREERUN mode relase without using interrupt) ++ ++void set_scaler_register(s3c_pp_scaler_info_t * scaler_info, s3c_pp_instance_context_t *pp_instance) ++{ ++ __raw_writel((scaler_info->pre_v_ratio<<7)|(scaler_info->pre_h_ratio<<0), s3c_pp_base + S3C_VPP_PRESCALE_RATIO); ++ __raw_writel((scaler_info->pre_dst_height<<12)|(scaler_info->pre_dst_width<<0), s3c_pp_base + S3C_VPP_PRESCALEIMGSIZE); ++ __raw_writel(scaler_info->sh_factor, s3c_pp_base + S3C_VPP_PRESCALE_SHFACTOR); ++ __raw_writel(scaler_info->dx, s3c_pp_base + S3C_VPP_MAINSCALE_H_RATIO); ++ __raw_writel(scaler_info->dy, s3c_pp_base + S3C_VPP_MAINSCALE_V_RATIO); ++ __raw_writel((pp_instance->src_height<<12)|(pp_instance->src_width), s3c_pp_base + S3C_VPP_SRCIMGSIZE); ++ __raw_writel((pp_instance->dst_height<<12)|(pp_instance->dst_width), s3c_pp_base + S3C_VPP_DSTIMGSIZE); ++} ++ ++ ++void set_src_addr_register ( s3c_pp_buf_addr_t *buf_addr, s3c_pp_instance_context_t *pp_instance ) ++{ ++ __raw_writel(buf_addr->src_start_y, s3c_pp_base + S3C_VPP_ADDRSTART_Y); ++ __raw_writel(buf_addr->offset_y, s3c_pp_base + S3C_VPP_OFFSET_Y); ++ __raw_writel(buf_addr->src_end_y, s3c_pp_base + S3C_VPP_ADDREND_Y); ++ ++ if (pp_instance->src_color_space == YC420) ++ { ++ __raw_writel(buf_addr->src_start_cb, s3c_pp_base + S3C_VPP_ADDRSTART_CB); ++ __raw_writel(buf_addr->offset_cr, s3c_pp_base + S3C_VPP_OFFSET_CB); ++ __raw_writel(buf_addr->src_end_cb, s3c_pp_base + S3C_VPP_ADDREND_CB); ++ __raw_writel(buf_addr->src_start_cr, s3c_pp_base + S3C_VPP_ADDRSTART_CR); ++ __raw_writel(buf_addr->offset_cb, s3c_pp_base + S3C_VPP_OFFSET_CR); ++ __raw_writel(buf_addr->src_end_cr, s3c_pp_base + S3C_VPP_ADDREND_CR); ++ } ++} ++ ++void set_dest_addr_register ( s3c_pp_buf_addr_t *buf_addr, s3c_pp_instance_context_t *pp_instance ) ++{ ++ if ( PP_INSTANCE_INUSE_DMA_ONESHOT == s3c_pp_instance_info.instance_state[pp_instance->instance_no] ) ++ { ++ __raw_writel(buf_addr->dst_start_rgb, s3c_pp_base + S3C_VPP_ADDRSTART_RGB); ++ __raw_writel(buf_addr->offset_rgb, s3c_pp_base + S3C_VPP_OFFSET_RGB); ++ __raw_writel(buf_addr->dst_end_rgb, s3c_pp_base + S3C_VPP_ADDREND_RGB); ++ ++ if ( pp_instance->dst_color_space == YC420 ) ++ { ++ __raw_writel(buf_addr->out_src_start_cb, s3c_pp_base + S3C_VPP_ADDRSTART_OCB); ++ __raw_writel(buf_addr->out_offset_cb, s3c_pp_base + S3C_VPP_OFFSET_OCB); ++ __raw_writel(buf_addr->out_src_end_cb, s3c_pp_base + S3C_VPP_ADDREND_OCB); ++ __raw_writel(buf_addr->out_src_start_cr, s3c_pp_base + S3C_VPP_ADDRSTART_OCR); ++ __raw_writel(buf_addr->out_offset_cr, s3c_pp_base + S3C_VPP_OFFSET_OCR); ++ __raw_writel(buf_addr->out_src_end_cr, s3c_pp_base + S3C_VPP_ADDREND_OCR); ++ } ++ } ++} ++ ++void set_src_next_addr_register(s3c_pp_buf_addr_t *buf_addr, s3c_pp_instance_context_t *pp_instance) ++{ ++ __raw_writel(buf_addr->src_start_y, s3c_pp_base + S3C_VPP_NXTADDRSTART_Y); ++ __raw_writel(buf_addr->src_end_y, s3c_pp_base + S3C_VPP_NXTADDREND_Y); ++ ++ if(pp_instance->src_color_space == YC420) { ++ __raw_writel(buf_addr->src_start_cb, s3c_pp_base + S3C_VPP_NXTADDRSTART_CB); ++ __raw_writel(buf_addr->src_end_cb, s3c_pp_base + S3C_VPP_NXTADDREND_CB); ++ __raw_writel(buf_addr->src_start_cr, s3c_pp_base + S3C_VPP_NXTADDRSTART_CR); ++ __raw_writel(buf_addr->src_end_cr, s3c_pp_base + S3C_VPP_NXTADDREND_CR); ++ } ++} ++ ++void set_data_format_register(s3c_pp_instance_context_t *pp_instance) ++{ ++ u32 tmp; ++ ++ tmp = __raw_readl(s3c_pp_base + S3C_VPP_MODE); ++ tmp |= (0x1<<16); ++ tmp |= (0x2<<10); ++ ++ // set the source color space ++ switch(pp_instance->src_color_space) { ++ case YC420: ++ tmp &=~((0x1<<3)|(0x1<<2)); ++ tmp |= (0x1<<8)|(0x1<<1); ++ break; ++ case CRYCBY: ++ tmp &= ~((0x1<<15)|(0x1<<8)|(0x1<<3)|(0x1<<0)); ++ tmp |= (0x1<<2)|(0x1<<1); ++ break; ++ case CBYCRY: ++ tmp &= ~((0x1<<8)|(0x1<<3)|(0x1<<0)); ++ tmp |= (0x1<<15)|(0x1<<2)|(0x1<<1); ++ break; ++ case YCRYCB: ++ tmp &= ~((0x1<<15)|(0x1<<8)|(0x1<<3)); ++ tmp |= (0x1<<2)|(0x1<<1)|(0x1<<0); ++ break; ++ case YCBYCR: ++ tmp &= ~((0x1<<8)|(0x1<<3)); ++ tmp |= (0x1<<15)|(0x1<<2)|(0x1<<1)|(0x1<<0); ++ break; ++ case RGB24: ++ tmp &= ~(0x1<<8); ++ tmp |= (0x1<<3)|(0x1<<2)|(0x1<<1); ++ break; ++ case RGB16: ++ tmp &= ~((0x1<<8)|(0x1<<1)); ++ tmp |= (0x1<<3)|(0x1<<2); ++ break; ++ default: ++ break; ++ } ++ ++ // set the destination color space ++ if ( PP_INSTANCE_INUSE_DMA_ONESHOT == s3c_pp_instance_info.instance_state[pp_instance->instance_no] ) ++ { ++ switch ( pp_instance->dst_color_space ) ++ { ++ case YC420: ++ tmp &= ~(0x1<<18); ++ tmp |= (0x1<<17); ++ break; ++ case CRYCBY: ++ tmp &= ~((0x1<<20)|(0x1<<19)|(0x1<<18)|(0x1<<17)); ++ break; ++ case CBYCRY: ++ tmp &= ~((0x1<<19)|(0x1<<18)|(0x1<<17)); ++ tmp |= (0x1<<20); ++ break; ++ case YCRYCB: ++ tmp &= ~((0x1<<20)|(0x1<<18)|(0x1<<17)); ++ tmp |= (0x1<<19); ++ break; ++ case YCBYCR: ++ tmp &= ~((0x1<<18)|(0x1<<17)); ++ tmp |= (0x1<<20)|(0x1<<19); ++ break; ++ case RGB24: ++ tmp |= (0x1<<18)|(0x1<<4); ++ break; ++ case RGB16: ++ tmp &= ~(0x1<<4); ++ tmp |= (0x1<<18); ++ break; ++ default: ++ break; ++ } ++ } ++ else if ( PP_INSTANCE_INUSE_FIFO_FREERUN == s3c_pp_instance_info.instance_state[pp_instance->instance_no]) ++ { ++ if (pp_instance->dst_color_space == RGB30) ++ { ++ tmp |= (0x1<<18)|(0x1<<13); ++ ++ } ++ else if(pp_instance->dst_color_space == YUV444) ++ { ++ tmp |= (0x1<<13); ++ tmp &= ~(0x1<<18)|(0x1<<17); ++ } ++ } ++ ++ __raw_writel ( tmp, s3c_pp_base + S3C_VPP_MODE ); ++} ++ ++static void set_clock_src ( s3c_pp_clk_src_t clk_src ) ++{ ++ u32 tmp; ++ ++ tmp = __raw_readl(s3c_pp_base + S3C_VPP_MODE); ++ ++ if ( clk_src == HCLK ) ++ { ++ if ( (unsigned int)h_clk > 66000000 ) ++ { ++ tmp &= ~(0x7f<<23); ++ tmp |= (1<<24); ++ tmp |= (1<<23); ++ } ++ else ++ { ++ tmp &=~ (0x7f<<23); ++ } ++ ++ } ++ else if(clk_src == PLL_EXT) ++ { ++ } ++ else ++ { ++ tmp &=~(0x7f<<23); ++ } ++ ++ tmp = (tmp &~ (0x3<<21)) | (clk_src<<21); ++ ++ __raw_writel(tmp, s3c_pp_base + S3C_VPP_MODE); ++} ++ ++ ++static void post_int_enable(u32 int_type) ++{ ++ u32 tmp; ++ ++ tmp = __raw_readl(s3c_pp_base + S3C_VPP_MODE); ++ ++ if(int_type == 0) { //Edge triggering ++ tmp &= ~(S3C_MODE_IRQ_LEVEL); ++ } else if(int_type == 1) { //level triggering ++ tmp |= S3C_MODE_IRQ_LEVEL; ++ } ++ ++ tmp |= S3C_MODE_POST_INT_ENABLE; ++ ++ __raw_writel(tmp, s3c_pp_base + S3C_VPP_MODE); ++} ++ ++static void post_int_disable(void) ++{ ++ u32 tmp; ++ ++ tmp = __raw_readl(s3c_pp_base + S3C_VPP_MODE); ++ ++ tmp &=~ S3C_MODE_POST_INT_ENABLE; ++ ++ __raw_writel(tmp, s3c_pp_base + S3C_VPP_MODE); ++} ++ ++static void start_processing(void) ++{ ++ __raw_writel(0x1<<31, s3c_pp_base + S3C_VPP_POSTENVID); ++} ++ ++s3c_pp_state_t post_get_processing_state(void) ++{ ++ s3c_pp_state_t state; ++ u32 tmp; ++ ++ tmp = __raw_readl(s3c_pp_base + S3C_VPP_POSTENVID); ++ if (tmp & S3C_VPP_POSTENVID) ++ { ++ state = POST_BUSY; ++ } ++ else ++ { ++ state = POST_IDLE; ++ } ++ ++ dprintk("Post processing state = %d\n", state); ++ ++ return state; ++} ++ ++static void s3c_dma_mode ( void ) ++{ ++ unsigned int temp; ++ ++ temp = __raw_readl(s3c_pp_base + S3C_VPP_MODE); ++ temp &=~(0x1<<13); // dma ++ __raw_writel(temp, s3c_pp_base + S3C_VPP_MODE); ++ ++#if 1 ++/* ++ temp = __raw_readl ( S3C_WINCON0 ); ++ temp &= ~(S3C_WINCONx_BPPMODE_F_MASK | (0x3<<9)); ++ temp &= ~(S3C_WINCONx_ENLOCAL_POST | S3C_WINCONx_INRGB_MASK); ++ temp &= ~( S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BYTSWP_ENABLE | S3C_WINCONx_BITSWP_ENABLE ); //swap disable ++ temp |= S3C_WINCONx_HAWSWP_ENABLE; ++ temp |= S3C_WINCONx_BPPMODE_F_16BPP_565; ++ temp |= S3C_WINCONx_ENWIN_F_ENABLE; ++ __raw_writel ( temp, S3C_WINCON0 ); ++ ++ temp = __raw_readl(s3c_pp_base + S3C_VPP_MODE); ++ temp &=~(0x1<<12); // 0: progressive mode, 1: interlace mode ++ temp &=~(0x1<<13); // dma ++ __raw_writel(temp, s3c_pp_base + S3C_VPP_MODE); ++*/ ++#else ++ __raw_writel(0x0<<31, s3c_pp_base + S3C_VPP_POSTENVID); ++ ++ // PP shot mode first ++ temp = __raw_readl(s3c_pp_base + S3C_VPP_MODE); ++ temp &=~(1<<14); // one shot ++ __raw_writel(temp, s3c_pp_base + S3C_VPP_MODE); ++ ++ //.[ display controller setting (DMA mode) ++ temp = __raw_readl ( S3C_VIDCON0 ); ++ temp &= ~( S3C_VIDCON0_ENVID_F_ENABLE | S3C_VIDCON0_ENVID_ENABLE ); ++ __raw_writel ( temp, S3C_VIDCON0 ); ++ ++ temp = __raw_readl ( S3C_WINCON0 ); ++ temp &= ~S3C_WINCONx_ENWIN_F_ENABLE; ++ __raw_writel ( temp, S3C_WINCON0 ); ++ ++ temp = __raw_readl ( S3C_WINCON0 ); ++ temp &= ~(S3C_WINCONx_BPPMODE_F_MASK | (0x3<<9)); ++ temp &= ~(S3C_WINCONx_ENLOCAL_POST | S3C_WINCONx_INRGB_MASK); ++ temp &= ~( S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BYTSWP_ENABLE | S3C_WINCONx_BITSWP_ENABLE ); //swap disable ++ temp |= S3C_WINCONx_HAWSWP_ENABLE; ++ temp |= S3C_WINCONx_BPPMODE_F_16BPP_565; ++ temp |= S3C_WINCONx_ENWIN_F_ENABLE; ++ __raw_writel ( temp, S3C_WINCON0 ); ++ ++ temp = __raw_readl ( S3C_VIDCON0 ); ++ temp |= ( S3C_VIDCON0_ENVID_F_ENABLE | S3C_VIDCON0_ENVID_ENABLE ); ++ __raw_writel ( temp, S3C_VIDCON0 ); ++ //.] display controller setting (DMA mode) ++ ++ i=0; ++ while ( (temp = __raw_readl ( s3c_pp_base + S3C_VPP_POSTENVID )) ) ++ { ++ i++; ++ __raw_writel(0x0<<31, s3c_pp_base + S3C_VPP_POSTENVID); ++ } ++ ++ temp = __raw_readl(s3c_pp_base + S3C_VPP_MODE); ++ ++ temp &=~(0x1<<12); // 0: progressive mode, 1: interlace mode ++ temp &=~(0x1<<31); ++ ++ temp &=~(0x1<<13); // dma ++ ++ __raw_writel(temp, s3c_pp_base + S3C_VPP_MODE); ++#endif ++} ++ ++static void pp_dma_mode_set_and_start ( void ) ++{ ++ unsigned int temp; ++ ++ __raw_writel(0x0<<31, s3c_pp_base + S3C_VPP_POSTENVID); ++ ++ temp = __raw_readl(s3c_pp_base + S3C_VPP_MODE); ++ ++ temp &= ~(0x1<<31); // must be 0 ++ temp &= ~(0x1<<13); // dma ++ temp &= ~(0x1<<14); // per frame mode ++ ++ __raw_writel(temp, s3c_pp_base + S3C_VPP_MODE); ++ ++ __raw_writel(0x1<<31, s3c_pp_base + S3C_VPP_POSTENVID); // PP start ++} ++ ++static void pp_fifo_mode_set_and_start ( s3c_pp_instance_context_t *current_instance ) ++{ ++ unsigned int temp; ++ ++#if 1 ++ // line count check ++ while ( __raw_readl ( S3C_VIDCON1 ) & 0x07FF0000 ) ++ { ++ } ++ ++ //.[ i: sichoi 090112 (FIFO_FREERUN mode relase without using interrupt) ++ temp = __raw_readl ( S3C_WINCON0 ); ++ temp &= ~S3C_WINCONx_ENWIN_F_ENABLE; ++ __raw_writel ( temp, S3C_WINCON0 ); ++ //.] sichoi 090112 (FIFO_FREERUN mode relase without using interrupt) ++ ++ __raw_writel(0x0<<31, s3c_pp_base + S3C_VPP_POSTENVID); ++ ++ temp = __raw_readl(s3c_pp_base + S3C_VPP_MODE); ++ ++ temp &= ~(0x1<<31); ++ if ( PROGRESSIVE_MODE == current_instance->scan_mode ) ++ { ++ temp &= ~(0x1<<12); // 0: progressive mode, 1: interlace mode ++ } ++ else ++ { ++ temp |= (0x1<<12); // 0: progressive mode, 1: interlace mode ++ } ++ ++ temp |= (0x1<<13); // fifo ++ temp |= (0x1<<14); // free run ++ ++ __raw_writel(temp, s3c_pp_base + S3C_VPP_MODE); ++ ++ __raw_writel(0x1<<31, s3c_pp_base + S3C_VPP_POSTENVID); // PP start ++ ++ ++ temp = __raw_readl ( S3C_WINCON0 ); //. i: sichoi 090112 (FIFO_FREERUN mode relase without using interrupt) ++ ++ //.[ d: sichoi 090112 (FIFO_FREERUN mode relase without using interrupt) ++ /* ++ temp &= ~S3C_WINCONx_ENWIN_F_ENABLE; ++ __raw_writel ( temp, S3C_WINCON0 ); ++ */ ++ //.] sichoi 090112 (FIFO_FREERUN mode relase without using interrupt) ++ ++ temp = current_instance->dst_width * current_instance->dst_height; ++ __raw_writel ( temp, S3C_VIDOSD0C ); ++ ++ temp = __raw_readl ( S3C_WINCON0 ); ++ temp &= ~(S3C_WINCONx_BPPMODE_F_MASK | (0x3<<9)); ++ temp &= ~(S3C_WINCONx_ENLOCAL_POST | S3C_WINCONx_INRGB_MASK); ++ temp &= ~( S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BYTSWP_ENABLE | S3C_WINCONx_BITSWP_ENABLE ); //swap disable ++ temp |= S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BURSTLEN_4WORD; ++ temp |= S3C_WINCONx_ENLOCAL_POST | S3C_WINCONx_ENWIN_F_ENABLE; ++ ++ __raw_writel ( temp, S3C_WINCON0 ); ++ ++#else ++ //.[ display controller setting (FIFO mode) ++ // line count check ++ while ( __raw_readl ( S3C_VIDCON1 ) & 0x07FF0000 ) ++ { ++ } ++ ++ __raw_writel(0x0<<31, s3c_pp_base + S3C_VPP_POSTENVID); ++ ++ temp = __raw_readl(s3c_pp_base + S3C_VPP_MODE); ++ ++ temp &=~(0x1<<12); // 0: progressive mode, 1: interlace mode ++ temp &=~(0x1<<31); ++ ++ temp |= (0x1<<13); // fifo ++ temp |= (1<<14); // free run ++ ++ __raw_writel(temp, s3c_pp_base + S3C_VPP_MODE); ++ ++ __raw_writel(0x1<<31, s3c_pp_base + S3C_VPP_POSTENVID); // PP start ++ ++ temp = __raw_readl ( S3C_VIDCON0 ); ++ temp &= ~( S3C_VIDCON0_ENVID_F_ENABLE | S3C_VIDCON0_ENVID_ENABLE ); ++ __raw_writel ( temp, S3C_VIDCON0 ); ++ ++ temp = __raw_readl ( S3C_WINCON0 ); ++ temp &= ~S3C_WINCONx_ENWIN_F_ENABLE; ++ __raw_writel ( temp, S3C_WINCON0 ); ++ ++ temp = __raw_readl ( S3C_WINCON0 ); ++ temp &= ~(S3C_WINCONx_BPPMODE_F_MASK | (0x3<<9)); ++ temp &= ~(S3C_WINCONx_ENLOCAL_POST | S3C_WINCONx_INRGB_MASK); ++ temp &= ~( S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BYTSWP_ENABLE | S3C_WINCONx_BITSWP_ENABLE ); //swap disable ++ temp |= S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BURSTLEN_4WORD; ++ temp |= S3C_WINCONx_ENLOCAL_POST | S3C_WINCONx_ENWIN_F_ENABLE; ++ ++ __raw_writel ( temp, S3C_WINCON0 ); ++ ++ temp = current_instance->dst_width * current_instance->dst_height; ++ __raw_writel ( temp, S3C_VIDOSD0C ); ++ ++ temp = __raw_readl ( S3C_VIDCON0 ); ++ temp |= S3C_VIDCON0_ENVID_F_ENABLE | S3C_VIDCON0_ENVID_ENABLE; ++ __raw_writel ( temp, S3C_VIDCON0 ); ++ //.] display controller setting (FIFO mode) ++#endif ++} ++ ++static irqreturn_t s3c_pp_isr (int irq, void *dev_id, struct pt_regs *regs) ++{ ++ u32 temp; ++ ++ temp = __raw_readl(s3c_pp_base + S3C_VPP_MODE); ++ temp &= ~(S3C_MODE_POST_PENDING | S3C_MODE_POST_INT_ENABLE); // int disable & pending bit clear ++ __raw_writel(temp, s3c_pp_base + S3C_VPP_MODE); ++ ++//.[ d: sichoi 090112 (FIFO_FREERUNmode relase without using interrupt) ++#if 0 ++ switch ( FIFO_mode_down_sequence ) ++ { ++ case 1: ++ temp &= ~S3C_MODE_AUTOLOAD_ENABLE; // set Per Frame mode ++ __raw_writel(temp, s3c_pp_base + S3C_VPP_MODE); ++ break; ++ case 2: ++#if 1 ++ temp = s3c_pp_instance_info.wincon0_value_before_fifo_mode & ~S3C_WINCONx_ENWIN_F_ENABLE; ++ __raw_writel ( temp, S3C_WINCON0 ); ++#else ++ temp = __raw_readl ( S3C_WINCON0 ); ++ temp &= ~S3C_WINCONx_ENWIN_F_ENABLE; ++ temp &= ~(S3C_WINCONx_BPPMODE_F_MASK | (0x3<<9)); ++ temp &= ~(S3C_WINCONx_ENLOCAL_POST | S3C_WINCONx_INRGB_MASK); ++ temp &= ~( S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BYTSWP_ENABLE | S3C_WINCONx_BITSWP_ENABLE ); //swap disable ++ temp |= S3C_WINCONx_HAWSWP_ENABLE; ++ temp |= S3C_WINCONx_BPPMODE_F_16BPP_565; ++ __raw_writel ( temp, S3C_WINCON0 ); ++#endif ++ ++ break; ++ default: ++ break; ++ } ++#endif ++//.] sichoi 090112 (FIFO_FREERUN mode relase without using interrupt) ++ ++ s3c_pp_instance_info.running_instance_no = -1; ++ ++ wake_up_interruptible(&waitq); ++ ++ return IRQ_HANDLED; ++} ++ ++ ++int s3c_pp_open(struct inode *inode, struct file *file) ++{ ++ s3c_pp_instance_context_t *current_instance; ++ int i; ++ ++ mutex_lock(h_mutex); ++ ++ // fifo mode·Î µÇ¾î ÀÖÀ¸¸é ´Ù¸¥ instance Open ºÒ°¡ ++ if ( s3c_pp_instance_info.fifo_mode_instance_no != -1 ) ++ { ++ printk(KERN_ERR "PP instance allocation is fail: Fifo Mode was already opened.\n"); ++ mutex_unlock(h_mutex); ++ return -1; ++ } ++ ++ // check instance pool ++ if (PP_MAX_NO_OF_INSTANCES <= s3c_pp_instance_info.in_use_instance_count) ++ { ++ printk(KERN_ERR "PP instance allocation is fail: No more instance.\n"); ++ mutex_unlock(h_mutex); ++ return -1; ++ } ++ ++ // allocating the post processor instance ++ current_instance = (s3c_pp_instance_context_t *) kmalloc(sizeof(s3c_pp_instance_context_t), GFP_DMA|GFP_ATOMIC ); ++ if (current_instance == NULL) { ++ printk(KERN_ERR "PP instance allocation is fail: Kmalloc failed.\n"); ++ mutex_unlock(h_mutex); ++ return -1; ++ } ++ ++ // Find free instance ++ for (i=0; i < PP_MAX_NO_OF_INSTANCES; i++) ++ { ++ if (PP_INSTANCE_FREE == s3c_pp_instance_info.instance_state[i]) ++ { ++ s3c_pp_instance_info.instance_state[i] = PP_INSTANCE_READY; ++ s3c_pp_instance_info.in_use_instance_count++; ++ break; ++ } ++ } ++ if (PP_MAX_NO_OF_INSTANCES == i) ++ { ++ kfree (current_instance); ++ printk(KERN_ERR "PP instance allocation is fail: No more instance.\n"); ++ mutex_unlock(h_mutex); ++ return -1; ++ } ++ ++ memset (current_instance, 0, sizeof(s3c_pp_instance_context_t)); ++ current_instance->instance_no = i; ++ ++ // check first time ++ if (1 == s3c_pp_instance_info.in_use_instance_count) ++ { ++ // PP HW Initalize or clock enable; for Power Saving ++ } ++ ++ dprintk ( KERN_DEBUG "%s PP instance allocation is success. (%d)\n", __FUNCTION__, i ); ++ ++ file->private_data = (s3c_pp_instance_context_t *) current_instance; ++ ++ mutex_unlock(h_mutex); ++ ++ return 0; ++} ++ ++ ++int s3c_pp_read ( struct file *file, char *buf, size_t count, loff_t *f_pos ) ++{ ++ return 0; ++} ++ ++int s3c_pp_write ( struct file *file, const char *buf, size_t count, loff_t *f_pos ) ++{ ++ return 0; ++} ++ ++int s3c_pp_mmap ( struct file *file, struct vm_area_struct *vma ) ++{ ++ u32 page_frame_no, size, phys_addr, max_size; ++ void *virt_addr; ++ ++ mutex_lock ( mem_alloc_mutex ); ++ ++ size = vma->vm_end - vma->vm_start; ++ ++ switch (flag) ++ { ++ case ALLOC_KMEM : ++ virt_addr = kmalloc ( size, GFP_DMA|GFP_ATOMIC ); // old setting is GFP_KERNEL ++ ++ if ( virt_addr == NULL) ++ { ++ printk ( KERN_ERR "%s kmalloc() failed !\n", __FUNCTION__ ); ++ mutex_unlock(mem_alloc_mutex); ++ return -EINVAL; ++ } ++ ++ dprintk (KERN_DEBUG "MMAP_KMALLOC : virt addr = 0x%p, size = %d\n", virt_addr, (unsigned int) size); ++ ++ phys_addr = virt_to_phys(virt_addr); ++ physical_address = (unsigned int) phys_addr; ++ ++ page_frame_no = __phys_to_pfn(phys_addr); ++ ++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ ++ if ((vma->vm_flags & VM_WRITE) && !(vma->vm_flags & VM_SHARED)) ++ { ++ printk ( KERN_ERR "%s: Writable G3D_SFR_SIZE mapping must be shared !\n", __FUNCTION__ ); ++ mutex_unlock(mem_alloc_mutex); ++ return -EINVAL; ++ } ++ ++ if (remap_pfn_range(vma, vma->vm_start, page_frame_no, size, vma->vm_page_prot)) ++ { ++ printk ( KERN_ERR "%s: remap_pfn_range() failed !\n", __FUNCTION__ ); ++ mutex_unlock(mem_alloc_mutex); ++ return -EINVAL; ++ } ++ break; ++ ++ default : ++ page_frame_no = __phys_to_pfn(PP_RESERVED_MEM_ADDR_PHY); ++ ++ max_size = PP_RESERVED_MEM_SIZE + PAGE_SIZE - (PP_RESERVED_MEM_SIZE % PAGE_SIZE); ++ ++ if ( max_size < size ) ++ { ++ mutex_unlock(mem_alloc_mutex); ++ return -EINVAL; ++ } ++ ++ vma->vm_flags |= VM_RESERVED; ++ ++ if ( remap_pfn_range(vma, vma->vm_start, page_frame_no, size, vma->vm_page_prot) ) ++ { ++ printk(KERN_ERR "%s: mmap_error\n", __FUNCTION__); ++ mutex_unlock(mem_alloc_mutex); ++ return -EAGAIN; ++ } ++ break; ++ } // switch (flag) ++ ++ mutex_unlock(mem_alloc_mutex); ++ ++ return 0; ++} ++ ++ ++int s3c_pp_release ( struct inode *inode, struct file *file ) ++{ ++ s3c_pp_instance_context_t *current_instance; ++ ++ mutex_lock(h_mutex); ++ ++ dprintk ( "%s: Enterance\n", __FUNCTION__ ); ++ ++ current_instance = (s3c_pp_instance_context_t *) file->private_data; ++ if (NULL == current_instance) ++ { ++ mutex_unlock(h_mutex); ++ return -1; ++ } ++ ++ if ( PP_INSTANCE_INUSE_DMA_ONESHOT == s3c_pp_instance_info.instance_state[current_instance->instance_no] ) ++ { ++ s3c_pp_instance_info.dma_mode_instance_count--; ++ } ++ else if ( PP_INSTANCE_INUSE_FIFO_FREERUN == s3c_pp_instance_info.instance_state[current_instance->instance_no] ) ++ { ++ ++ s3c_pp_instance_info.fifo_mode_instance_no = -1; ++ ++ // change Display Controller WIN0 mode to DMA Mode ++ // change Post Processor mode to DMA Mode & turn off Free Run Mode ++ ++//.[ i: sichoi 090112 (FIFO_FREERUN mode relase without using interrupt) ++#if 1 ++ do ++ { ++ unsigned int temp; ++ ++ temp = __raw_readl ( S3C_VIDCON0 ) & ~S3C_VIDCON0_ENVID_ENABLE; ++ __raw_writel ( temp, S3C_VIDCON0 ); ++ ++ while ( __raw_readl ( S3C_VIDCON1 ) & 0x07FF0000 ) ++ { ++ } ++ ++ temp = __raw_readl(s3c_pp_base + S3C_VPP_MODE) & ~S3C_MODE_AUTOLOAD_ENABLE; // set Per Frame mode ++ __raw_writel(temp, s3c_pp_base + S3C_VPP_MODE); ++ ++ temp = s3c_pp_instance_info.wincon0_value_before_fifo_mode & ~S3C_WINCONx_ENWIN_F_ENABLE; ++ __raw_writel ( temp, S3C_WINCON0 ); ++ ++ temp = __raw_readl ( S3C_VIDCON0 ) | S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE; ++ __raw_writel ( temp, S3C_VIDCON0 ); ++ } while ( 0 ); ++#else ++ //.[ i: sichoi 081027 (Safety FIFO Mode Down) ++ FIFO_mode_down_sequence = 1; ++ ++ while ( FIFO_mode_down_sequence < 4 ) ++ { ++ post_int_enable(1); ++ interruptible_sleep_on_timeout(&waitq, 20); ++ ++ FIFO_mode_down_sequence++; ++ } ++ //.] sichoi 081027 ++ ++ FIFO_mode_down_sequence = 0; ++#endif ++//.] sichoi 090112 (FIFO_FREERUN mode relase without using interrupt) ++ } ++ ++ if ( current_instance->instance_no == s3c_pp_instance_info.last_running_instance_no ) ++ { ++ s3c_pp_instance_info.last_running_instance_no = -1; ++ } ++ ++ s3c_pp_instance_info.instance_state[current_instance->instance_no] = PP_INSTANCE_FREE; ++ if ( 0 < s3c_pp_instance_info.in_use_instance_count && s3c_pp_instance_info.in_use_instance_count <= PP_MAX_NO_OF_INSTANCES ) ++ { ++ s3c_pp_instance_info.in_use_instance_count--; ++ if ( 0 == s3c_pp_instance_info.in_use_instance_count ) ++ { ++ s3c_pp_instance_info.last_running_instance_no = -1; ++ ++ // TO DO: PP H/W Deinitialize (optional) ++ } ++ } ++ ++ dprintk ( "%s: handle=%d, count=%d\n", __FUNCTION__, current_instance->instance_no, s3c_pp_instance_info.in_use_instance_count ); ++ ++ kfree(current_instance); ++ ++ mutex_unlock(h_mutex); ++ ++ return 0; ++} ++ ++ ++static int s3c_pp_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ s3c_pp_instance_context_t *current_instance; ++ s3c_pp_params_t *parg; ++ ++ unsigned int temp = 0; ++ ++ mutex_lock(h_mutex); ++ ++ current_instance = (s3c_pp_instance_context_t *) file->private_data; ++ parg = (s3c_pp_params_t *) arg; ++ ++ switch ( cmd ) ++ { ++ case S3C_PP_SET_PARAMS: ++ { ++ s3c_pp_out_path_t temp_out_path; ++ unsigned int temp_src_width, temp_src_height, temp_dst_width, temp_dst_height; ++ s3c_color_space_t temp_src_color_space, temp_dst_color_space; ++ ++ get_user(temp_out_path, &parg->out_path); ++ ++ if ( (-1 != s3c_pp_instance_info.fifo_mode_instance_no ) ++ || ((s3c_pp_instance_info.dma_mode_instance_count) && (FIFO_FREERUN == temp_out_path)) ) ++ { ++ printk ( KERN_ERR "\n%s: S3C_PP_SET_PARAMS can't be executed.\n", __FUNCTION__ ); ++ mutex_unlock(h_mutex); ++ return -EINVAL; ++ } ++ ++ get_user(temp_src_width, &parg->src_width); ++ get_user(temp_src_height, &parg->src_height); ++ get_user(temp_dst_width, &parg->dst_width); ++ get_user(temp_dst_height, &parg->dst_height); ++ ++ // S3C6410 support that the source image is up to 4096 x 4096 ++ // and the destination image is up to 2048 x 2048. ++ if ( (temp_src_width > 4096) || (temp_src_height > 4096) ++ || (temp_dst_width > 2048) || (temp_dst_height > 2048) ) ++ { ++ printk(KERN_ERR "\n%s: Size is too big to be supported.\n", __FUNCTION__); ++ mutex_unlock(h_mutex); ++ return -EINVAL; ++ } ++ ++ get_user(temp_src_color_space, &parg->src_color_space); ++ get_user(temp_dst_color_space, &parg->dst_color_space); ++ ++ if ( ( (temp_src_color_space == YC420) && (temp_src_width % 8) ) ++ || ( (temp_src_color_space == RGB16) && (temp_src_width % 2) ) ++ || ( (temp_out_path == DMA_ONESHOT) && ( ((temp_dst_color_space == YC420) && (temp_dst_width % 8)) ++ || ((temp_dst_color_space == RGB16) && (temp_dst_width % 2)))) ) ++ { ++ printk(KERN_ERR "\n%s: YUV420 image width must be a multiple of 8.\n", __FUNCTION__); ++ printk(KERN_ERR "%s: RGB16 must be a multiple of 2.\n", __FUNCTION__); ++ mutex_unlock(h_mutex); ++ return -EINVAL; ++ } ++ ++ ++ get_user(current_instance->src_full_width, &parg->src_full_width); ++ get_user(current_instance->src_full_height, &parg->src_full_height); ++ get_user(current_instance->src_start_x, &parg->src_start_x); ++ get_user(current_instance->src_start_y, &parg->src_start_y); ++ current_instance->src_width = temp_src_width; ++ current_instance->src_height = temp_src_height; ++ current_instance->src_color_space = temp_src_color_space; ++ ++ get_user(current_instance->dst_full_width, &parg->dst_full_width); ++ get_user(current_instance->dst_full_height, &parg->dst_full_height); ++ get_user(current_instance->dst_start_x, &parg->dst_start_x); ++ get_user(current_instance->dst_start_y, &parg->dst_start_y); ++ current_instance->dst_width = temp_dst_width; ++ current_instance->dst_height = temp_dst_height; ++ current_instance->dst_color_space = temp_dst_color_space; ++ ++ current_instance->out_path = temp_out_path; ++ ++ if ( DMA_ONESHOT == current_instance->out_path ) ++ { ++ s3c_pp_instance_info.instance_state[current_instance->instance_no] = PP_INSTANCE_INUSE_DMA_ONESHOT; ++ s3c_pp_instance_info.dma_mode_instance_count++; ++ } ++ else ++ { ++ get_user(current_instance->scan_mode, &parg->scan_mode); ++ ++ current_instance->dst_color_space = RGB30; ++ ++ s3c_pp_instance_info.instance_state[current_instance->instance_no] = PP_INSTANCE_INUSE_FIFO_FREERUN; ++ s3c_pp_instance_info.fifo_mode_instance_no = current_instance->instance_no; ++ s3c_pp_instance_info.wincon0_value_before_fifo_mode = __raw_readl ( S3C_WINCON0 ); ++ ++ //.[ REDUCE_VCLK_SYOP_TIME ++ if ( current_instance->src_height > current_instance->dst_height ) ++ { ++ int i; ++ ++ for ( i=2; (current_instance->src_height >= (i * current_instance->dst_height)) && (i<8); i++ ) ++ { ++ } ++ ++ current_instance->src_full_width *= i; ++ current_instance->src_full_height /= i; ++ current_instance->src_height /= i; ++ } ++ //.] REDUCE_VCLK_SYOP_TIME ++ } ++ ++ current_instance->value_changed |= PP_VALUE_CHANGED_PARAMS; ++ } ++ break; ++ ++ case S3C_PP_START: ++ dprintk ( "%s: S3C_PP_START last_instance=%d, curr_instance=%d\n", __FUNCTION__, ++ s3c_pp_instance_info.last_running_instance_no, current_instance->instance_no ); ++ ++ if ( PP_INSTANCE_READY == s3c_pp_instance_info.instance_state[current_instance->instance_no] ) ++ { ++ printk ( KERN_ERR "%s: S3C_PP_START must be executed after running S3C_PP_SET_PARAMS.\n", __FUNCTION__ ); ++ mutex_unlock(h_mutex); ++ return -EINVAL; ++ } ++ ++ if ( current_instance->instance_no != s3c_pp_instance_info.last_running_instance_no ) ++ { ++ __raw_writel(0x0<<31, s3c_pp_base + S3C_VPP_POSTENVID); ++ ++ temp = S3C_MODE2_ADDR_CHANGE_DISABLE | S3C_MODE2_CHANGE_AT_FRAME_END | S3C_MODE2_SOFTWARE_TRIGGER; ++ __raw_writel(temp, s3c_pp_base + S3C_VPP_MODE_2); ++ ++ set_clock_src(HCLK); ++ ++ // setting the src/dst color space ++ set_data_format(current_instance); ++ ++ // setting the src/dst size ++ set_scaler(current_instance); ++ ++ // setting the src/dst buffer address ++ set_src_addr(current_instance); ++ set_dest_addr(current_instance); ++ ++ current_instance->value_changed = PP_VALUE_CHANGED_NONE; ++ ++ s3c_pp_instance_info.last_running_instance_no = current_instance->instance_no; ++ s3c_pp_instance_info.running_instance_no = current_instance->instance_no; ++ ++ if ( PP_INSTANCE_INUSE_DMA_ONESHOT == s3c_pp_instance_info.instance_state[current_instance->instance_no] ) ++ { // DMA OneShot Mode ++ dprintk ( "%s: DMA_ONESHOT mode\n", __FUNCTION__ ); ++ ++ post_int_enable(1); ++ pp_dma_mode_set_and_start(); ++ ++ ++ if ( !(file->f_flags & O_NONBLOCK) ) ++ { ++ if (interruptible_sleep_on_timeout(&waitq, 500) == 0) ++ { ++ printk(KERN_ERR "\n%s: Waiting for interrupt is timeout\n", __FUNCTION__); ++ } ++ } ++ } ++ else ++ { // FIFO freerun Mode ++ dprintk ( "%s: FIFO_freerun mode\n", __FUNCTION__ ); ++ s3c_pp_instance_info.fifo_mode_instance_no = current_instance->instance_no; ++ ++ post_int_enable(1); ++ pp_fifo_mode_set_and_start(current_instance); ++ } ++ } ++ else ++ { ++ if ( current_instance->value_changed != PP_VALUE_CHANGED_NONE ) ++ { ++ __raw_writel(0x0<<31, s3c_pp_base + S3C_VPP_POSTENVID); ++ ++ if ( current_instance->value_changed & PP_VALUE_CHANGED_PARAMS ) ++ { ++ set_data_format(current_instance); ++ set_scaler(current_instance); ++ } ++ ++ if ( current_instance->value_changed & PP_VALUE_CHANGED_SRC_BUF_ADDR_PHY ) ++ { ++ set_src_addr(current_instance); ++ } ++ ++ if ( current_instance->value_changed & PP_VALUE_CHANGED_DST_BUF_ADDR_PHY ) ++ { ++ set_dest_addr(current_instance); ++ } ++ ++ current_instance->value_changed = PP_VALUE_CHANGED_NONE; ++ } ++ ++ s3c_pp_instance_info.running_instance_no = current_instance->instance_no; ++ ++ post_int_enable(1); ++ start_processing(); ++ ++ if ( !(file->f_flags & O_NONBLOCK) ) ++ { ++ if (interruptible_sleep_on_timeout(&waitq, 500) == 0) ++ { ++ printk(KERN_ERR "\n%s: Waiting for interrupt is timeout\n", __FUNCTION__); ++ } ++ } ++ } ++ break; ++ ++ case S3C_PP_GET_SRC_BUF_SIZE: ++ ++ if ( PP_INSTANCE_READY == s3c_pp_instance_info.instance_state[current_instance->instance_no] ) ++ { ++ dprintk ( "%s: S3C_PP_GET_SRC_BUF_SIZE must be executed after running S3C_PP_SET_PARAMS.\n", __FUNCTION__ ); ++ mutex_unlock(h_mutex); ++ return -EINVAL; ++ } ++ ++ temp = cal_data_size ( current_instance->src_color_space, current_instance->src_full_width, current_instance->src_full_height ); ++ ++ mutex_unlock(h_mutex); ++ return temp; ++ ++ ++ case S3C_PP_SET_SRC_BUF_ADDR_PHY: ++ ++ get_user(current_instance->src_buf_addr_phy, &parg->src_buf_addr_phy); ++ current_instance->value_changed |= PP_VALUE_CHANGED_SRC_BUF_ADDR_PHY; ++ break; ++ ++ case S3C_PP_SET_SRC_BUF_NEXT_ADDR_PHY: ++ ++ if ( current_instance->instance_no != s3c_pp_instance_info.fifo_mode_instance_no ) ++ { // if FIFO Mode is not Active ++ dprintk (KERN_DEBUG "%s: S3C_PP_SET_SRC_BUF_NEXT_ADDR_PHY can't be executed.\n", __FUNCTION__ ); ++ mutex_unlock(h_mutex); ++ return -EINVAL; ++ } ++ ++ get_user(current_instance->src_next_buf_addr_phy, &parg->src_next_buf_addr_phy); ++ ++ temp = __raw_readl(s3c_pp_base + S3C_VPP_MODE_2); ++ temp |= (0x1<<4); ++ __raw_writel(temp, s3c_pp_base + S3C_VPP_MODE_2); ++ ++ set_src_next_buf_addr(current_instance); ++ ++ temp = __raw_readl(s3c_pp_base + S3C_VPP_MODE_2); ++ temp &= ~(0x1<<4); ++ __raw_writel(temp, s3c_pp_base + S3C_VPP_MODE_2); ++ break; ++ ++ case S3C_PP_GET_DST_BUF_SIZE: ++ ++ if ( PP_INSTANCE_READY == s3c_pp_instance_info.instance_state[current_instance->instance_no] ) ++ { ++ dprintk ( "%s: S3C_PP_GET_DST_BUF_SIZE must be executed after running S3C_PP_SET_PARAMS.\n", __FUNCTION__ ); ++ mutex_unlock(h_mutex); ++ return -EINVAL; ++ } ++ ++ temp = cal_data_size ( current_instance->dst_color_space, current_instance->dst_full_width, current_instance->dst_full_height ); ++ ++ mutex_unlock(h_mutex); ++ return temp; ++ ++ case S3C_PP_SET_DST_BUF_ADDR_PHY: ++ ++ get_user(current_instance->dst_buf_addr_phy, &parg->dst_buf_addr_phy); ++ current_instance->value_changed |= PP_VALUE_CHANGED_DST_BUF_ADDR_PHY; ++ break; ++ ++ ++ case S3C_PP_ALLOC_KMEM: ++ { ++ s3c_pp_mem_alloc_t param; ++ ++ if (copy_from_user(¶m, (s3c_pp_mem_alloc_t *)arg, sizeof(s3c_pp_mem_alloc_t))) ++ { ++ mutex_unlock(h_mutex); ++ return -EFAULT; ++ } ++ ++ flag = ALLOC_KMEM; ++ ++ param.vir_addr = do_mmap(file, 0, param.size, PROT_READ|PROT_WRITE, MAP_SHARED, 0); ++ dprintk (KERN_DEBUG "param.vir_addr = %08x\n", param.vir_addr); ++ ++ flag = 0; ++ ++ if(param.vir_addr == -EINVAL) { ++ printk(KERN_ERR "%s: PP_MEM_ALLOC FAILED\n", __FUNCTION__); ++ mutex_unlock(h_mutex); ++ return -EFAULT; ++ } ++ param.phy_addr = physical_address; ++ ++ dprintk (KERN_DEBUG "KERNEL MALLOC : param.phy_addr = 0x%X \t size = %d \t param.vir_addr = 0x%X\n", param.phy_addr, param.size, param.vir_addr); ++ ++ if (copy_to_user((s3c_pp_mem_alloc_t *)arg, ¶m, sizeof(s3c_pp_mem_alloc_t))) ++ { ++ mutex_unlock(h_mutex); ++ return -EFAULT; ++ } ++ } ++ break; ++ ++ case S3C_PP_FREE_KMEM: ++ { ++ s3c_pp_mem_alloc_t param; ++ struct mm_struct *mm = current->mm; ++ void *virt_addr; ++ ++ if ( copy_from_user(¶m, (s3c_pp_mem_alloc_t *)arg, sizeof(s3c_pp_mem_alloc_t)) ) ++ { ++ mutex_unlock(h_mutex); ++ return -EFAULT; ++ } ++ ++ dprintk (KERN_DEBUG "KERNEL FREE : param.phy_addr = 0x%X \t size = %d \t param.vir_addr = 0x%X\n", param.phy_addr, param.size, param.vir_addr); ++ ++ if ( do_munmap(mm, param.vir_addr, param.size ) < 0 ) ++ { ++ dprintk("do_munmap() failed !!\n"); ++ mutex_unlock(h_mutex); ++ return -EINVAL; ++ } ++ virt_addr = phys_to_virt(param.phy_addr); ++ dprintk ( "KERNEL : virt_addr = 0x%X\n", (unsigned int) virt_addr ); ++ ++ kfree(virt_addr); ++ param.size = 0; ++ ++ dprintk(KERN_DEBUG "do_munmap() succeed !!\n"); ++ } ++ break; ++ ++ case S3C_PP_GET_RESERVED_MEM_SIZE: ++ mutex_unlock(h_mutex); ++ return PP_RESERVED_MEM_SIZE; ++ ++ case S3C_PP_GET_RESERVED_MEM_ADDR_PHY: ++ mutex_unlock(h_mutex); ++ return PP_RESERVED_MEM_ADDR_PHY; ++ ++ default: ++ mutex_unlock(h_mutex); ++ return -EINVAL; ++ } ++ ++ mutex_unlock(h_mutex); ++ ++ return 0; ++} ++ ++static unsigned int s3c_pp_poll(struct file *file, poll_table *wait) ++{ ++ unsigned int mask = 0; ++ s3c_pp_instance_context_t *current_instance; ++ ++ mutex_lock(h_mutex); ++ ++ current_instance = (s3c_pp_instance_context_t *) file->private_data; ++ ++ poll_wait(file, &waitq, wait); ++ ++ if ( -1 == s3c_pp_instance_info.fifo_mode_instance_no ) ++ { ++ if ( -1 == s3c_pp_instance_info.running_instance_no ) ++ { ++ dprintk ( "nw(%d) ", current_instance->instance_no ); ++ ++ mask = POLLOUT|POLLWRNORM; ++ } ++ else ++ { ++ dprintk ( "w(%d) ", current_instance->instance_no ); ++ } ++ } ++ else ++ { ++ dprintk ( "%s : error\n", __FUNCTION__ ); ++ mask = POLLERR; ++ } ++ ++ mutex_unlock(h_mutex); ++ ++ return mask; ++} ++ ++ ++static struct file_operations s3c_pp_fops = { ++ .owner = THIS_MODULE, ++ .ioctl = s3c_pp_ioctl, ++ .open = s3c_pp_open, ++ .read = s3c_pp_read, ++ .write = s3c_pp_write, ++ .mmap = s3c_pp_mmap, ++ .poll = s3c_pp_poll, ++ .release = s3c_pp_release ++}; ++ ++ ++static struct miscdevice s3c_pp_dev = { ++ .minor = PP_MINOR, ++ .name = "s3c-pp", ++ .fops = &s3c_pp_fops, ++}; ++ ++static int s3c_pp_remove(struct platform_device *dev) ++{ ++ clk_disable(pp_clock); ++ ++ free_irq(s3c_pp_irq, NULL); ++ if (s3c_pp_mem != NULL) { ++ pr_debug("s3c_post: releasing s3c_post_mem\n"); ++ iounmap(s3c_pp_base); ++ release_resource(s3c_pp_mem); ++ kfree(s3c_pp_mem); ++ } ++ misc_deregister(&s3c_pp_dev); ++ return 0; ++} ++ ++ ++ ++static int s3c_pp_probe(struct platform_device *pdev) ++{ ++ ++ struct resource *res; ++ ++ int ret; ++ ++ int tmp; ++ int i; ++ ++ // Use DOUTmpll source clock as a scaler clock ++ tmp = __raw_readl(S3C_CLK_SRC); ++ ++ tmp &=~(0x3<<28); ++ tmp |= (0x1<<28); ++ __raw_writel(tmp, S3C_CLK_SRC); ++ ++ /* find the IRQs */ ++ s3c_pp_irq = platform_get_irq(pdev, 0); ++ ++ ++ if(s3c_pp_irq <= 0) { ++ printk(KERN_ERR PFX "failed to get irq resouce\n"); ++ return -ENOENT; ++ } ++ ++ /* get the memory region for the post processor driver */ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if(res == NULL) { ++ printk(KERN_ERR PFX "failed to get memory region resouce\n"); ++ return -ENOENT; ++ } ++ ++ s3c_pp_mem = request_mem_region(res->start, res->end-res->start+1, pdev->name); ++ if(s3c_pp_mem == NULL) { ++ printk(KERN_ERR PFX "failed to reserve memory region\n"); ++ return -ENOENT; ++ } ++ ++ ++ s3c_pp_base = ioremap(s3c_pp_mem->start, s3c_pp_mem->end - res->start + 1); ++ if(s3c_pp_base == NULL) { ++ printk(KERN_ERR PFX "failed ioremap\n"); ++ return -ENOENT; ++ } ++ ++ pp_clock = clk_get(&pdev->dev, "post"); ++ if(pp_clock == NULL) { ++ printk(KERN_ERR PFX "failed to find post clock source\n"); ++ return -ENOENT; ++ } ++ ++ clk_enable(pp_clock); ++ ++ h_clk = clk_get(&pdev->dev, "hclk"); ++ if(h_clk == NULL) { ++ printk(KERN_ERR PFX "failed to find h_clk clock source\n"); ++ return -ENOENT; ++ } ++ ++ init_waitqueue_head(&waitq); ++ ++ ret = misc_register(&s3c_pp_dev); ++ if (ret) { ++ printk (KERN_ERR "cannot register miscdev on minor=%d (%d)\n", ++ PP_MINOR, ret); ++ return ret; ++ } ++ ++ ret = request_irq(s3c_pp_irq, (irq_handler_t) s3c_pp_isr,IRQF_DISABLED, ++ pdev->name, NULL); ++ if (ret) { ++ printk(KERN_ERR "request_irq(PP) failed.\n"); ++ return ret; ++ } ++ ++ h_mutex = (struct mutex *) kmalloc(sizeof(struct mutex), GFP_DMA|GFP_ATOMIC ); ++ if (h_mutex == NULL) ++ return -1; ++ ++ mutex_init(h_mutex); ++ ++ mem_alloc_mutex = (struct mutex *) kmalloc(sizeof(struct mutex), GFP_DMA|GFP_ATOMIC ); ++ if (mem_alloc_mutex == NULL) ++ return -1; ++ ++ mutex_init(mem_alloc_mutex); ++ ++ // initialzie instance infomation ++ s3c_pp_instance_info.running_instance_no = -1; ++ s3c_pp_instance_info.last_running_instance_no = -1; ++ s3c_pp_instance_info.in_use_instance_count = 0; ++ s3c_pp_instance_info.dma_mode_instance_count = 0; ++ s3c_pp_instance_info.fifo_mode_instance_no = -1; ++ for ( i=0; i < PP_MAX_NO_OF_INSTANCES; i++ ) ++ s3c_pp_instance_info.instance_state[i] = PP_INSTANCE_FREE; ++ ++ /* check to see if everything is setup correctly */ ++ return 0; ++} ++ ++static int s3c_pp_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ int post_state; ++ unsigned int dw_pp_base; ++ int i, index = 0; ++ ++ post_state = post_get_processing_state(); ++ while (post_state == POST_BUSY) ++ msleep(1); ++ ++ dw_pp_base = s3c_pp_base; ++ for (i = S3C_PP_SAVE_START_ADDR; i <= S3C_PP_SAVE_END_ADDR; i += 4) { ++ s3c_pp_save[index] = readl(dw_pp_base + i); ++ index++; ++ } ++ ++ clk_disable(pp_clock); ++ return 0; ++} ++ ++static int s3c_pp_resume(struct platform_device *pdev) ++{ ++ unsigned int dw_pp_base; ++ int i, index = 0; ++ ++ dw_pp_base = s3c_pp_base; ++ for (i = S3C_PP_SAVE_START_ADDR; i <= S3C_PP_SAVE_END_ADDR; i += 4) { ++ writel(s3c_pp_save[index], dw_pp_base + i); ++ index++; ++ } ++ ++ clk_enable(pp_clock); ++ return 0; ++} ++ ++static struct platform_driver s3c_pp_driver = { ++ .probe = s3c_pp_probe, ++ .remove = s3c_pp_remove, ++ .suspend = s3c_pp_suspend, ++ .resume = s3c_pp_resume, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "s3c-vpp", ++ }, ++}; ++ ++static char version[] __initdata = "3.12"; ++static char banner[] __initdata = KERN_INFO "S3C PostProcessor Driver v%s, (c) 2009 Samsung Electronics\n"; ++ ++static int __init s3c_pp_init(void) ++{ ++ ++ printk(banner, version); ++ if(platform_driver_register(&s3c_pp_driver)!=0) ++ { ++ printk(KERN_ERR "platform device register Failed \n"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++static void __exit s3c_pp_exit(void) ++{ ++ platform_driver_unregister(&s3c_pp_driver); ++ mutex_destroy(h_mutex); ++ mutex_destroy(mem_alloc_mutex); ++ printk("S3C PostProcessor module exit\n"); ++} ++ ++module_init(s3c_pp_init); ++module_exit(s3c_pp_exit); ++ ++MODULE_AUTHOR("jiun.yu@samsung.com"); ++MODULE_DESCRIPTION("S3C PostProcessor Device Driver"); ++MODULE_LICENSE("GPL"); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/post/s3c_pp_common.c linux-2.6.28.6/drivers/media/video/samsung/post/s3c_pp_common.c +--- linux-2.6.28/drivers/media/video/samsung/post/s3c_pp_common.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/post/s3c_pp_common.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,332 @@ ++/* linux/drivers/media/video/samsung/post/s3c_pp_common.c ++ * ++ * Driver file for Samsung Post processor ++ * ++ * Jiun Yu, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* error codes */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "s3c_pp_common.h" ++ ++#define PFX "s3c_pp" ++ ++// setting the source/destination color space ++void set_data_format(s3c_pp_instance_context_t *pp_instance) ++{ ++ // set the source color space ++ switch(pp_instance->src_color_space) { ++ case YC420: ++ pp_instance->in_pixel_size = 1; ++ break; ++ case YCBYCR: ++ pp_instance->in_pixel_size = 2; ++ break; ++ case YCRYCB: ++ pp_instance->in_pixel_size = 2; ++ break; ++ case CBYCRY: ++ pp_instance->in_pixel_size = 2; ++ break; ++ case CRYCBY: ++ pp_instance->in_pixel_size = 2; ++ break; ++ case RGB24: ++ pp_instance->in_pixel_size = 4; ++ break; ++ case RGB16: ++ pp_instance->in_pixel_size = 2; ++ break; ++ default: ++ break; ++ } ++ ++ // set the destination color space ++ if ( DMA_ONESHOT == pp_instance->out_path ) ++ { ++ switch(pp_instance->dst_color_space) { ++ case YC420: ++ pp_instance->out_pixel_size = 1; ++ break; ++ case YCBYCR: ++ pp_instance->out_pixel_size = 2; ++ break; ++ case YCRYCB: ++ pp_instance->out_pixel_size = 2; ++ break; ++ case CBYCRY: ++ pp_instance->out_pixel_size = 2; ++ break; ++ case CRYCBY: ++ pp_instance->out_pixel_size = 2; ++ break; ++ case RGB24: ++ pp_instance->out_pixel_size = 4; ++ break; ++ case RGB16: ++ pp_instance->out_pixel_size = 2; ++ break; ++ default: ++ break; ++ } ++ } ++ else if ( FIFO_FREERUN == pp_instance->out_path ) ++ { ++ if(pp_instance->dst_color_space == RGB30) ++ { ++ pp_instance->out_pixel_size = 4; ++ } ++ else if(pp_instance->dst_color_space == YUV444) ++ { ++ pp_instance->out_pixel_size = 4; ++ } ++ } ++ ++ // setting the register about src/dst data format ++ set_data_format_register(pp_instance); ++} ++ ++ ++void set_src_addr(s3c_pp_instance_context_t *pp_instance) ++{ ++ s3c_pp_buf_addr_t buf_addr; ++ ++ buf_addr.offset_y = (pp_instance->src_full_width - pp_instance->src_width) * pp_instance->in_pixel_size; ++ buf_addr.start_pos_y = (pp_instance->src_full_width*pp_instance->src_start_y+pp_instance->src_start_x)*pp_instance->in_pixel_size; ++ buf_addr.end_pos_y = pp_instance->src_width*pp_instance->src_height*pp_instance->in_pixel_size + buf_addr.offset_y*(pp_instance->src_height-1); ++ buf_addr.src_frm_start_addr = pp_instance->src_buf_addr_phy; ++ buf_addr.src_start_y = pp_instance->src_buf_addr_phy + buf_addr.start_pos_y; ++ buf_addr.src_end_y = buf_addr.src_start_y + buf_addr.end_pos_y; ++ ++ if (pp_instance->src_color_space == YC420) ++ { ++ buf_addr.offset_cb = buf_addr.offset_cr = ((pp_instance->src_full_width - pp_instance->src_width) / 2) * pp_instance->in_pixel_size; ++ buf_addr.start_pos_cb = pp_instance->src_full_width * pp_instance->src_full_height * 1 \ ++ + (pp_instance->src_full_width * pp_instance->src_start_y / 2 + pp_instance->src_start_x) /2 * 1; ++ ++ buf_addr.end_pos_cb = pp_instance->src_width/2*pp_instance->src_height/2*pp_instance->in_pixel_size \ ++ + (pp_instance->src_height/2 -1)*buf_addr.offset_cb; ++ buf_addr.start_pos_cr = pp_instance->src_full_width * pp_instance->src_full_height *1 \ ++ + pp_instance->src_full_width*pp_instance->src_full_height/4 *1 \ ++ + (pp_instance->src_full_width*pp_instance->src_start_y/2 + pp_instance->src_start_x)/2*1; ++ buf_addr.end_pos_cr = pp_instance->src_width/2*pp_instance->src_height/2*pp_instance->in_pixel_size \ ++ + (pp_instance->src_height/2-1)*buf_addr.offset_cr; ++ ++ buf_addr.src_start_cb = pp_instance->src_buf_addr_phy + buf_addr.start_pos_cb; ++ buf_addr.src_end_cb = buf_addr.src_start_cb + buf_addr.end_pos_cb; ++ ++ buf_addr.src_start_cr = pp_instance->src_buf_addr_phy + buf_addr.start_pos_cr; ++ buf_addr.src_end_cr = buf_addr.src_start_cr + buf_addr.end_pos_cr; ++ } ++ ++ set_src_addr_register ( &buf_addr, pp_instance ); ++} ++ ++void set_dest_addr(s3c_pp_instance_context_t *pp_instance) ++{ ++ s3c_pp_buf_addr_t buf_addr; ++ ++ if ( DMA_ONESHOT == pp_instance->out_path ) ++ { ++ buf_addr.offset_rgb = (pp_instance->dst_full_width - pp_instance->dst_width)*pp_instance->out_pixel_size; ++ buf_addr.start_pos_rgb = (pp_instance->dst_full_width*pp_instance->dst_start_y + pp_instance->dst_start_x)*pp_instance->out_pixel_size; ++ buf_addr.end_pos_rgb = pp_instance->dst_width*pp_instance->dst_height*pp_instance->out_pixel_size \ ++ + buf_addr.offset_rgb*(pp_instance->dst_height - 1); ++ buf_addr.dst_start_rgb = pp_instance->dst_buf_addr_phy + buf_addr.start_pos_rgb; ++ buf_addr.dst_end_rgb = buf_addr.dst_start_rgb + buf_addr.end_pos_rgb; ++ ++ if (pp_instance->dst_color_space == YC420) ++ { ++ buf_addr.out_offset_cb = buf_addr.out_offset_cr = ((pp_instance->dst_full_width - pp_instance->dst_width)/2)*pp_instance->out_pixel_size; ++ buf_addr.out_start_pos_cb = pp_instance->dst_full_width*pp_instance->dst_full_height*1 \ ++ + (pp_instance->dst_full_width*pp_instance->dst_start_y/2 + pp_instance->dst_start_x)/2*1; ++ buf_addr.out_end_pos_cb = pp_instance->dst_width/2*pp_instance->dst_height/2*pp_instance->out_pixel_size \ ++ + (pp_instance->dst_height/2 -1)*buf_addr.out_offset_cr; ++ ++ buf_addr.out_start_pos_cr = pp_instance->dst_full_width*pp_instance->dst_full_height*1 \ ++ + (pp_instance->dst_full_width*pp_instance->dst_full_height/4)*1 \ ++ + (pp_instance->dst_full_width*pp_instance->dst_start_y/2 +pp_instance->dst_start_x)/2*1; ++ buf_addr.out_end_pos_cr = pp_instance->dst_width/2*pp_instance->dst_height/2*pp_instance->out_pixel_size \ ++ + (pp_instance->dst_height/2 -1)*buf_addr.out_offset_cb; ++ ++ buf_addr.out_src_start_cb = pp_instance->dst_buf_addr_phy + buf_addr.out_start_pos_cb; ++ buf_addr.out_src_end_cb = buf_addr.out_src_start_cb + buf_addr.out_end_pos_cb; ++ buf_addr.out_src_start_cr = pp_instance->dst_buf_addr_phy + buf_addr.out_start_pos_cr; ++ buf_addr.out_src_end_cr = buf_addr.out_src_start_cr + buf_addr.out_end_pos_cr; ++ } ++ ++ set_dest_addr_register ( &buf_addr, pp_instance ); ++ } ++} ++ ++void set_src_next_buf_addr(s3c_pp_instance_context_t *pp_instance) ++{ ++ s3c_pp_buf_addr_t buf_addr; ++ ++ ++ buf_addr.offset_y = (pp_instance->src_full_width - pp_instance->src_width) * pp_instance->in_pixel_size; ++ buf_addr.start_pos_y = (pp_instance->src_full_width*pp_instance->src_start_y+pp_instance->src_start_x)*pp_instance->in_pixel_size; ++ buf_addr.end_pos_y = pp_instance->src_width*pp_instance->src_height*pp_instance->in_pixel_size + buf_addr.offset_y*(pp_instance->src_height-1); ++ buf_addr.src_frm_start_addr = pp_instance->src_next_buf_addr_phy; ++ ++ buf_addr.src_start_y = pp_instance->src_next_buf_addr_phy + buf_addr.start_pos_y; ++ buf_addr.src_end_y = buf_addr.src_start_y + buf_addr.end_pos_y; ++ ++ ++ if(pp_instance->src_color_space == YC420) { ++ buf_addr.offset_cb = buf_addr.offset_cr = ((pp_instance->src_full_width - pp_instance->src_width) / 2) * pp_instance->in_pixel_size; ++ buf_addr.start_pos_cb = pp_instance->src_full_width * pp_instance->src_full_height * 1 \ ++ + (pp_instance->src_full_width * pp_instance->src_start_y / 2 + pp_instance->src_start_x) /2 * 1; ++ ++ buf_addr.end_pos_cb = pp_instance->src_width/2*pp_instance->src_height/2*pp_instance->in_pixel_size \ ++ + (pp_instance->src_height/2 -1)*buf_addr.offset_cb; ++ buf_addr.start_pos_cr = pp_instance->src_full_width * pp_instance->src_full_height *1 \ ++ + pp_instance->src_full_width*pp_instance->src_full_height/4 *1 \ ++ + (pp_instance->src_full_width*pp_instance->src_start_y/2 + pp_instance->src_start_x)/2*1; ++ buf_addr.end_pos_cr = pp_instance->src_width/2*pp_instance->src_height/2*pp_instance->in_pixel_size \ ++ + (pp_instance->src_height/2-1)*buf_addr.offset_cr; ++ ++ ++ buf_addr.src_start_cb = pp_instance->src_next_buf_addr_phy + buf_addr.start_pos_cb; ++ buf_addr.src_end_cb = buf_addr.src_start_cb + buf_addr.end_pos_cb; ++ buf_addr.src_start_cr = pp_instance->src_next_buf_addr_phy + buf_addr.start_pos_cr; ++ buf_addr.src_end_cr = buf_addr.src_start_cr + buf_addr.end_pos_cr; ++ ++ } ++ ++ ++ set_src_next_addr_register(&buf_addr, pp_instance); ++} ++ ++ ++ ++// setting the scaling information(source/destination size) ++void set_scaler(s3c_pp_instance_context_t *pp_instance) ++{ ++ s3c_pp_scaler_info_t scaler_info; ++ ++ ++ if (pp_instance->src_width >= (pp_instance->dst_width<<6)) { ++ printk(KERN_ERR "Out of PreScalar range !!!\n"); ++ return; ++ } ++ if(pp_instance->src_width >= (pp_instance->dst_width<<5)) { ++ scaler_info.pre_h_ratio = 32; ++ scaler_info.h_shift = 5; ++ } else if(pp_instance->src_width >= (pp_instance->dst_width<<4)) { ++ scaler_info.pre_h_ratio = 16; ++ scaler_info.h_shift = 4; ++ } else if(pp_instance->src_width >= (pp_instance->dst_width<<3)) { ++ scaler_info.pre_h_ratio = 8; ++ scaler_info.h_shift = 3; ++ } else if(pp_instance->src_width >= (pp_instance->dst_width<<2)) { ++ scaler_info.pre_h_ratio = 4; ++ scaler_info.h_shift = 2; ++ } else if(pp_instance->src_width >= (pp_instance->dst_width<<1)) { ++ scaler_info.pre_h_ratio = 2; ++ scaler_info.h_shift = 1; ++ } else { ++ scaler_info.pre_h_ratio = 1; ++ scaler_info.h_shift = 0; ++ } ++ ++ scaler_info.pre_dst_width = pp_instance->src_width / scaler_info.pre_h_ratio; ++ scaler_info.dx = (pp_instance->src_width<<8) / (pp_instance->dst_width<src_height >= (pp_instance->dst_height<<6)) { ++ printk(KERN_ERR "Out of PreScalar range !!!\n"); ++ return; ++ } ++ if(pp_instance->src_height >= (pp_instance->dst_height<<5)) { ++ scaler_info.pre_v_ratio = 32; ++ scaler_info.v_shift = 5; ++ } else if(pp_instance->src_height >= (pp_instance->dst_height<<4)) { ++ scaler_info.pre_v_ratio = 16; ++ scaler_info.v_shift = 4; ++ } else if(pp_instance->src_height >= (pp_instance->dst_height<<3)) { ++ scaler_info.pre_v_ratio = 8; ++ scaler_info.v_shift = 3; ++ } else if(pp_instance->src_height >= (pp_instance->dst_height<<2)) { ++ scaler_info.pre_v_ratio = 4; ++ scaler_info.v_shift = 2; ++ } else if(pp_instance->src_height >= (pp_instance->dst_height<<1)) { ++ scaler_info.pre_v_ratio = 2; ++ scaler_info.v_shift = 1; ++ } else { ++ scaler_info.pre_v_ratio = 1; ++ scaler_info.v_shift = 0; ++ } ++ ++ scaler_info.pre_dst_height = pp_instance->src_height / scaler_info.pre_v_ratio; ++ scaler_info.dy = (pp_instance->src_height<<8) / (pp_instance->dst_height<> 1; ++ case YCBYCR: ++ return (width * height * 2); ++ case YCRYCB: ++ return (width * height * 2); ++ case CBYCRY: ++ return (width * height * 2); ++ case CRYCBY: ++ return (width * height * 2); ++ case RGB24: ++ return (width * height * 4); ++ case RGB16: ++ return (width * height * 2); ++ default: ++ printk(KERN_ERR "Input parameter is wrong\n"); ++ return -EINVAL; ++ } ++} ++ ++int get_src_data_size(s3c_pp_instance_context_t *pp_instance) ++{ ++ return cal_data_size ( pp_instance->src_color_space, pp_instance->src_full_width, pp_instance->src_full_height ); ++} ++ ++int get_dest_data_size(s3c_pp_instance_context_t *pp_instance) ++{ ++ return cal_data_size ( pp_instance->dst_color_space, pp_instance->dst_full_width, pp_instance->dst_full_height ); ++} ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/post/s3c_pp_common.h linux-2.6.28.6/drivers/media/video/samsung/post/s3c_pp_common.h +--- linux-2.6.28/drivers/media/video/samsung/post/s3c_pp_common.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/post/s3c_pp_common.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,95 @@ ++#ifndef _S3C_PP_COMMON_H_ ++#define _S3C_PP_COMMON_H_ ++ ++#include "s3c_pp.h" ++ ++#define PP_MINOR 253 // post processor is misc device driver ++ ++typedef enum { ++ HCLK = 0, ++ PLL_EXT = 1, ++ EXT_27MHZ = 3 ++} s3c_pp_clk_src_t; ++ ++typedef enum { ++ POST_IDLE = 0, ++ POST_BUSY ++} s3c_pp_state_t; ++ ++typedef struct { ++ unsigned int src_full_width; // Source Image Full Width (Virtual screen size) ++ unsigned int src_full_height; // Source Image Full Height (Virtual screen size) ++ unsigned int src_start_x; // Source Image Start width offset ++ unsigned int src_start_y; // Source Image Start height offset ++ unsigned int src_width; // Source Image Width ++ unsigned int src_height; // Source Image Height ++ unsigned int src_buf_addr_phy; // Base Address of the Source Image : Physical Address ++ unsigned int src_next_buf_addr_phy; // Base Address of Source Image to be displayed next time in FIFO_FREERUN Mode ++ s3c_color_space_t src_color_space; // Color Space of the Source Image ++ ++ unsigned int dst_full_width; // Destination Image Full Width (Virtual screen size) ++ unsigned int dst_full_height; // Destination Image Full Height (Virtual screen size) ++ unsigned int dst_start_x; // Destination Image Start width offset ++ unsigned int dst_start_y; // Destination Image Start height offset ++ unsigned int dst_width; // Destination Image Width ++ unsigned int dst_height; // Destination Image Height ++ unsigned int dst_buf_addr_phy; // Base Address of the Destination Image : Physical Address ++ s3c_color_space_t dst_color_space; // Color Space of the Destination Image ++ ++ s3c_pp_out_path_t out_path; // output and run mode to be used internally ++ s3c_pp_scan_mode_t scan_mode; // INTERLACE_MODE, PROGRESSIVE_MODE ++ ++ unsigned int in_pixel_size; // source format size per pixel ++ unsigned int out_pixel_size; // destination format size per pixel ++ ++ unsigned int instance_no; // Instance No ++ unsigned int value_changed; // 0: Parameter is not changed, 1: Parameter is changed ++ //unsigned int RegisterContext[164]; // Register Context ++} s3c_pp_instance_context_t; ++ ++typedef struct { ++ unsigned int pre_h_ratio, pre_v_ratio, h_shift, v_shift, sh_factor; ++ unsigned int pre_dst_width, pre_dst_height, dx, dy; ++} s3c_pp_scaler_info_t; ++ ++typedef struct { ++ unsigned int offset_y, offset_cb, offset_cr; ++ unsigned int src_start_y, src_start_cb, src_start_cr; ++ unsigned int src_end_y, src_end_cb, src_end_cr; ++ unsigned int start_pos_y, end_pos_y; ++ unsigned int start_pos_cb, end_pos_cb; ++ unsigned int start_pos_cr, end_pos_cr; ++ unsigned int start_pos_rgb, end_pos_rgb; ++ unsigned int dst_start_rgb, dst_end_rgb; ++ unsigned int src_frm_start_addr; ++ ++ unsigned int offset_rgb, out_offset_cb, out_offset_cr; ++ unsigned int out_start_pos_cb, out_start_pos_cr; ++ unsigned int out_end_pos_cb, out_end_pos_cr; ++ unsigned int out_src_start_cb, out_src_start_cr; ++ unsigned int out_src_end_cb, out_src_end_cr; ++} s3c_pp_buf_addr_t; ++ ++ ++ ++ ++ ++// below functions are used for Post Processor commonly ++void set_data_format(s3c_pp_instance_context_t *pp_instance); ++void set_src_addr(s3c_pp_instance_context_t *pp_instance); ++void set_dest_addr(s3c_pp_instance_context_t *pp_instance); ++void set_src_next_buf_addr(s3c_pp_instance_context_t *pp_instance); ++void set_scaler(s3c_pp_instance_context_t *pp_instance); ++int cal_data_size(s3c_color_space_t color_space, unsigned int width, unsigned int height); ++ ++// below functions'body is implemented in each post processor IP file(ex. s3c_pp_6400.c) ++void set_scaler_register(s3c_pp_scaler_info_t *scaler_info, s3c_pp_instance_context_t *pp_instance); ++void set_src_addr_register(s3c_pp_buf_addr_t *buf_addr, s3c_pp_instance_context_t *pp_instance); ++void set_dest_addr_register(s3c_pp_buf_addr_t *buf_addr, s3c_pp_instance_context_t *pp_instance); ++void set_src_next_addr_register(s3c_pp_buf_addr_t *buf_addr, s3c_pp_instance_context_t *pp_instance); ++void set_data_format_register(s3c_pp_instance_context_t *pp_instance); ++ ++s3c_pp_state_t post_get_processing_state(void); ++ ++#endif // _S3C_PP_COMMON_H_ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/rotator/Kconfig linux-2.6.28.6/drivers/media/video/samsung/rotator/Kconfig +--- linux-2.6.28/drivers/media/video/samsung/rotator/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/rotator/Kconfig 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,13 @@ ++# ++# Configuration for rotator ++# ++ ++config VIDEO_ROTATOR ++ bool "Samsung Image Rotator Driver" ++ depends on VIDEO_SAMSUNG && (CPU_S3C6410 || CPU_S5PC100) ++ default n ++ ---help--- ++ This is a Rotator for Samsung S3C6410 and S5PC100. ++ ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/rotator/Makefile linux-2.6.28.6/drivers/media/video/samsung/rotator/Makefile +--- linux-2.6.28/drivers/media/video/samsung/rotator/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/rotator/Makefile 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,10 @@ ++################################################# ++# Makefile for Post Processor ++# 2009 (C) Samsung Electronics ++# Author : Jaeryul peter Oh ++################################################# ++ ++obj-$(CONFIG_VIDEO_ROTATOR) += s3c_rotator.o ++ ++EXTRA_CFLAGS += -Idrivers/media/video ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/rotator/s3c_rotator.c linux-2.6.28.6/drivers/media/video/samsung/rotator/s3c_rotator.c +--- linux-2.6.28/drivers/media/video/samsung/rotator/s3c_rotator.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/rotator/s3c_rotator.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,444 @@ ++/* linux/drivers/media/video/samsung/rotator/s3c_rotator.c ++ * ++ * Driver file for Samsung Image Rotator ++ * ++ * Jonghun Han, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* error codes */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "s3c_rotator_common.h" ++ ++static int s3c_rotator_irq_num = NO_IRQ; ++static struct resource *s3c_rotator_mem; ++static void __iomem *s3c_rotator_base; ++ ++static wait_queue_head_t waitq_rotator; ++ ++static struct mutex *h_rot_mutex; ++ ++static inline void s3c_rotator_set_source(ro_params *params) ++{ ++ __raw_writel(S3C_ROT_SRC_HEIGHT(params->src_height) | ++ S3C_ROT_SRC_WIDTH( params->src_width) , s3c_rotator_base + S3C_ROTATOR_SRCSIZEREG); ++ __raw_writel(params->src_addr_rgb_y, s3c_rotator_base + S3C_ROTATOR_SRCADDRREG0); ++ __raw_writel(params->src_addr_cb, s3c_rotator_base + S3C_ROTATOR_SRCADDRREG1); ++ __raw_writel(params->src_addr_cr, s3c_rotator_base + S3C_ROTATOR_SRCADDRREG2); ++} ++ ++ ++static inline void s3c_rotator_set_dest(ro_params *params) ++{ ++ __raw_writel(params->dst_addr_rgb_y, s3c_rotator_base + S3C_ROTATOR_DESTADDRREG0); ++ __raw_writel(params->dst_addr_cb, s3c_rotator_base + S3C_ROTATOR_DESTADDRREG1); ++ __raw_writel(params->dst_addr_cr, s3c_rotator_base + S3C_ROTATOR_DESTADDRREG2); ++} ++ ++ ++static inline void s3c_rotator_start(ro_params *params, unsigned mode) ++{ ++ u32 cfg = 0; ++ ++ cfg = __raw_readl(s3c_rotator_base + S3C_ROTATOR_CTRLCFG); ++ cfg &= ~S3C_ROTATOR_CTRLREG_MASK; ++ cfg |= params->src_format | mode; ++ ++ __raw_writel(cfg|S3C_ROTATOR_CTRLCFG_START_ROTATE, s3c_rotator_base + S3C_ROTATOR_CTRLCFG); ++} ++ ++ ++static inline unsigned int s3c_rotator_get_status(void) ++{ ++ unsigned int cfg = 0; ++ ++ cfg = __raw_readl(s3c_rotator_base + S3C_ROTATOR_STATCFG); ++ cfg &= S3C_ROTATOR_STATCFG_STATUS_BUSY_MORE; ++ ++ return cfg; ++} ++ ++ ++static void s3c_rotator_enable_int(void) ++{ ++ unsigned int cfg; ++ ++ cfg = __raw_readl(s3c_rotator_base + S3C_ROTATOR_CTRLCFG); ++ cfg |= S3C_ROTATOR_CTRLCFG_ENABLE_INT; ++ ++ __raw_writel(cfg, s3c_rotator_base + S3C_ROTATOR_CTRLCFG); ++} ++ ++ ++static void s3c_rotator_disable_int(void) ++{ ++ unsigned int cfg; ++ ++ cfg = __raw_readl(s3c_rotator_base + S3C_ROTATOR_CTRLCFG); ++ cfg &=~ S3C_ROTATOR_CTRLCFG_ENABLE_INT; ++ ++ __raw_writel(cfg, s3c_rotator_base + S3C_ROTATOR_CTRLCFG); ++} ++ ++ ++#if defined(CONFIG_CPU_S3C6410) ++irqreturn_t s3c_rotator_irq(int irq, void *dev_id) ++{ ++ __raw_readl(s3c_rotator_base + S3C_ROTATOR_STATCFG); ++ ++ wake_up_interruptible(&waitq_rotator); ++ ++ return IRQ_HANDLED; ++} ++#elif defined(CONFIG_CPU_S5PC100) ++irqreturn_t s3c_rotator_irq(int irq, void *dev_id) ++{ ++ unsigned int cfg; ++ ++ cfg = __raw_readl(s3c_rotator_base + S3C_ROTATOR_STATCFG); ++ cfg |= S3C_ROTATOR_STATCFG_INT_PEND; ++ ++ __raw_writel(cfg, s3c_rotator_base + S3C_ROTATOR_STATCFG); ++ ++ wake_up_interruptible(&waitq_rotator); ++ ++ return IRQ_HANDLED; ++} ++#endif ++ ++int s3c_rotator_open(struct inode *inode, struct file *file) ++{ ++ ro_params *params; ++ ++ // allocating the rotator instance ++ params = (ro_params *)kmalloc(sizeof(ro_params), GFP_KERNEL); ++ if (params == NULL) { ++ printk(KERN_ERR "Instance memory allocation was failed\n"); ++ return -ENOMEM; ++ } ++ ++ memset(params, 0, sizeof(ro_params)); ++ ++ file->private_data = (ro_params *)params; ++ ++ return 0; ++} ++ ++ ++int s3c_rotator_release(struct inode *inode, struct file *file) ++{ ++ ro_params *params; ++ ++ params = (ro_params *)file->private_data; ++ if (params == NULL) { ++ printk(KERN_ERR "Can't release s3c_rotator!!\n"); ++ return -1; ++ } ++ ++ kfree(params); ++ ++ return 0; ++} ++ ++ ++static int s3c_rotator_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ ro_params *params; ++ ro_params *parg; ++ unsigned int mode, divisor = 0; ++ ++ mutex_lock(h_rot_mutex); ++ ++ params = (ro_params *)file->private_data; ++ parg = (ro_params *)arg; ++ ++ get_user(params->src_width, &parg->src_width); ++ get_user(params->src_height, &parg->src_height); ++ ++ get_user(params->src_format, &parg->src_format); ++ get_user(params->src_addr_rgb_y,&parg->src_addr_rgb_y); ++ get_user(params->src_addr_cb, &parg->src_addr_cb); ++ get_user(params->src_addr_cr, &parg->src_addr_cr); ++ ++ get_user(params->dst_addr_rgb_y,&parg->dst_addr_rgb_y); ++ get_user(params->dst_addr_cb, &parg->dst_addr_cb); ++ get_user(params->dst_addr_cr, &parg->dst_addr_cr); ++ ++ if( (params->src_width > 2048) || (params->src_height > 2048)) { ++ printk(KERN_ERR "\n%s: maximum width and height size are 2048\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ switch(params->src_format) { ++ case S3C_ROTATOR_CTRLCFG_INPUT_YUV420: ++ divisor = 8; ++ break; ++ ++ case S3C_ROTATOR_CTRLCFG_INPUT_YUV422: /* fall through */ ++ case S3C_ROTATOR_CTRLCFG_INPUT_RGB565: ++ divisor = 2; ++ break; ++ ++ case S3C_ROTATOR_CTRLCFG_INPUT_RGB888: ++ divisor = 1; ++ break; ++ ++ default : ++ printk(KERN_ERR "requested src type is not supported!! plz check src format!!\n"); ++ break; ++ } ++ ++ if((params->src_width % divisor) || (params->src_height % divisor)) { ++ printk(KERN_ERR "\n%s: src & dst size is aligned to %d pixel boundary\n", __FUNCTION__, divisor); ++ mutex_unlock(h_rot_mutex); ++ return -EINVAL; ++ } ++ ++ switch(cmd) { ++ case ROTATOR_90: ++ mode = S3C_ROTATOR_CTRLCFG_DEGREE_90 | S3C_ROTATOR_CTRLCFG_FLIP_BYPASS; ++ break; ++ ++ case ROTATOR_180: ++ mode = S3C_ROTATOR_CTRLCFG_DEGREE_180 | S3C_ROTATOR_CTRLCFG_FLIP_BYPASS; ++ break; ++ ++ case ROTATOR_270: ++ mode = S3C_ROTATOR_CTRLCFG_DEGREE_270 | S3C_ROTATOR_CTRLCFG_FLIP_BYPASS; ++ break; ++ ++ case HFLIP: ++ mode = S3C_ROTATOR_CTRLCFG_DEGREE_BYPASS| S3C_ROTATOR_CTRLCFG_FLIP_HOR; ++ break; ++ ++ case VFLIP: ++ mode = S3C_ROTATOR_CTRLCFG_DEGREE_BYPASS| S3C_ROTATOR_CTRLCFG_FLIP_VER; ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ s3c_rotator_set_source(params); ++ s3c_rotator_set_dest(params); ++ s3c_rotator_start(params, mode); ++ ++ if(!(file->f_flags & O_NONBLOCK)) { ++ if (interruptible_sleep_on_timeout(&waitq_rotator, ROTATOR_TIMEOUT) == 0) { ++ printk(KERN_ERR "\n%s: Waiting for interrupt is timeout\n", __FUNCTION__); ++ } ++ } ++ ++ mutex_unlock(h_rot_mutex); ++ ++ return 0; ++} ++ ++ ++static unsigned int s3c_rotator_poll(struct file *file, poll_table *wait) ++{ ++ unsigned int mask = 0; ++ ++ poll_wait(file, &waitq_rotator, wait); ++ ++ if (S3C_ROTATOR_IDLE == s3c_rotator_get_status()) { ++ mask = POLLOUT|POLLWRNORM; ++ } ++ ++ return mask; ++} ++ ++ ++struct file_operations s3c_rotator_fops = { ++ .owner = THIS_MODULE, ++ .open = s3c_rotator_open, ++ .release = s3c_rotator_release, ++ .ioctl = s3c_rotator_ioctl, ++ .poll = s3c_rotator_poll, ++}; ++ ++ ++static struct miscdevice s3c_rotator_dev = { ++ .minor = ROTATOR_MINOR, ++ .name = "s3c-rotator", ++ .fops = &s3c_rotator_fops, ++}; ++ ++ ++int s3c_rotator_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ int ret; ++ ++ printk(KERN_INFO "s3c_rotator_probe called\n"); ++ ++ /* find the IRQs */ ++ s3c_rotator_irq_num = platform_get_irq(pdev, 0); ++ if(s3c_rotator_irq_num <= 0) { ++ printk(KERN_ERR "failed to get irq resource\n"); ++ return -ENOENT; ++ } ++ ++ ret = request_irq(s3c_rotator_irq_num, s3c_rotator_irq, IRQF_DISABLED, pdev->name, NULL); ++ if (ret) { ++ printk("request_irq(Rotator) failed.\n"); ++ return ret; ++ } ++ ++ /* get the memory region */ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if(res == NULL) { ++ printk(KERN_ERR "failed to get memory region resouce\n"); ++ return -ENOENT; ++ } ++ ++ s3c_rotator_mem = request_mem_region(res->start, res->end - res->start + 1, pdev->name); ++ if(s3c_rotator_mem == NULL) { ++ printk(KERN_ERR "failed to reserved memory region\n"); ++ return -ENOENT; ++ } ++ ++ s3c_rotator_base = ioremap(s3c_rotator_mem->start, s3c_rotator_mem->end - res->start + 1); ++ if(s3c_rotator_base == NULL) { ++ printk(KERN_ERR "failed ioremap\n"); ++ return -ENOENT; ++ } ++ ++ s3c_rotator_enable_int(); ++ ++ init_waitqueue_head(&waitq_rotator); ++ ++ ret = misc_register(&s3c_rotator_dev); ++ if (ret) { ++ printk (KERN_ERR "cannot register miscdev on minor=%d (%d)\n", ROTATOR_MINOR, ret); ++ return ret; ++ } ++ ++ h_rot_mutex = (struct mutex *)kmalloc(sizeof(struct mutex), GFP_KERNEL); ++ if (h_rot_mutex == NULL) { ++ printk (KERN_ERR "cannot allocate rotator mutex\n"); ++ return -ENOENT; ++ } ++ ++ mutex_init(h_rot_mutex); ++ ++ printk("s3c_rotator_probe success\n"); ++ ++ return 0; ++} ++ ++ ++static int s3c_rotator_remove(struct platform_device *dev) ++{ ++ free_irq(s3c_rotator_irq_num, NULL); ++ ++ if (s3c_rotator_mem != NULL) { ++ printk(KERN_INFO "S3C Rotator Driver, releasing resource\n"); ++ iounmap(s3c_rotator_base); ++ release_resource(s3c_rotator_mem); ++ kfree(s3c_rotator_mem); ++ } ++ ++ misc_deregister(&s3c_rotator_dev); ++ ++ return 0; ++} ++ ++ ++static int s3c_rotator_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ return 0; ++} ++ ++ ++static int s3c_rotator_resume(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++ ++static struct platform_driver s3c_rotator_driver = { ++ .probe = s3c_rotator_probe, ++ .remove = s3c_rotator_remove, ++ .suspend = s3c_rotator_suspend, ++ .resume = s3c_rotator_resume, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "s3c-rotator", ++ }, ++}; ++ ++ ++static char banner[] __initdata = KERN_INFO "S3C Rotator Driver, (c) 2008 Samsung Electronics\n"; ++ ++int __init s3c_rotator_init(void) ++{ ++ unsigned int ret; ++ printk(banner); ++ ++ ret = platform_driver_register(&s3c_rotator_driver); ++ if( ret != 0) { ++ printk(KERN_ERR "s3c_rotator_driver platform device register failed\n"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++ ++void s3c_rotator_exit(void) ++{ ++ platform_driver_unregister(&s3c_rotator_driver); ++ mutex_destroy(h_rot_mutex); ++ ++ printk("s3c rotator module exit\n"); ++} ++ ++module_init(s3c_rotator_init); ++module_exit(s3c_rotator_exit); ++ ++MODULE_AUTHOR("Jonghun Han "); ++MODULE_DESCRIPTION("S3C Rotator Device Driver"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/rotator/s3c_rotator_common.h linux-2.6.28.6/drivers/media/video/samsung/rotator/s3c_rotator_common.h +--- linux-2.6.28/drivers/media/video/samsung/rotator/s3c_rotator_common.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/rotator/s3c_rotator_common.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,31 @@ ++#ifndef _S3C_ROTATOR_COMMON_H_ ++#define _S3C_ROTATOR_COMMON_H_ ++ ++#define ROTATOR_IOCTL_MAGIC 'R' ++ ++#define ROTATOR_MINOR 230 ++#define ROTATOR_TIMEOUT 100 // normally 800 * 480 * 2 rotation takes about 20ms ++ ++ ++#define ROTATOR_90 _IO(ROTATOR_IOCTL_MAGIC, 0) ++#define ROTATOR_180 _IO(ROTATOR_IOCTL_MAGIC, 1) ++#define ROTATOR_270 _IO(ROTATOR_IOCTL_MAGIC, 2) ++#define HFLIP _IO(ROTATOR_IOCTL_MAGIC, 3) ++#define VFLIP _IO(ROTATOR_IOCTL_MAGIC, 4) ++ ++ ++typedef struct{ ++ unsigned int src_width; // Source Image Full Width ++ unsigned int src_height; // Source Image Full Height ++ unsigned int src_addr_rgb_y; // Base Address of the Source Image (RGB or Y) : Physical Address ++ unsigned int src_addr_cb; // Base Address of the Source Image (CB Component) : Physical Address ++ unsigned int src_addr_cr; // Base Address of the Source Image (CR Component) : Physical Address ++ unsigned int src_format; // Color Space of the Source Image YUV420(non-interleave)/YUV422(interleave)/RGB565/RGB888 ++ ++ unsigned int dst_addr_rgb_y; // Base Address of the Destination Image (RGB or Y) : Physical Address ++ unsigned int dst_addr_cb; // Base Address of the Destination Image (CB Component) : Physical Address ++ unsigned int dst_addr_cr; // Base Address of the Destination Image (CR Component) : Physical Address ++}ro_params; ++ ++#endif // _S3C_ROTATOR_COMMON_H_ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/tv/Kconfig linux-2.6.28.6/drivers/media/video/samsung/tv/Kconfig +--- linux-2.6.28/drivers/media/video/samsung/tv/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/tv/Kconfig 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,11 @@ ++# ++# Configuration for Post Porcessor ++# ++ ++config VIDEO_TV ++ bool "Samsung TV Driver" ++ depends on VIDEO_SAMSUNG && CPU_S3C6410 ++ default n ++ ---help--- ++ This is a TV driver for Samsung S3C6410. ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/tv/Makefile linux-2.6.28.6/drivers/media/video/samsung/tv/Makefile +--- linux-2.6.28/drivers/media/video/samsung/tv/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/tv/Makefile 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,13 @@ ++################################################# ++# Makefile for Post Processor ++# 2007 (C) Samsung Electronics ++# Author : SungJun Bae ++################################################# ++ ++obj-$(CONFIG_VIDEO_TV) += s3c-tvenc.o s3c-tvscaler.o ++ ++EXTRA_CFLAGS += -Idrivers/media/video ++ ++ifeq ($(CONFIG_VIDEO_TV_DEBUG),y) ++EXTRA_CFLAGS += -DDEBUG ++endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/tv/s3c-tvenc.c linux-2.6.28.6/drivers/media/video/samsung/tv/s3c-tvenc.c +--- linux-2.6.28/drivers/media/video/samsung/tv/s3c-tvenc.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/tv/s3c-tvenc.c 2010-05-19 05:17:26.000000000 +0200 +@@ -0,0 +1,1497 @@ ++/* linux/drivers/media/video/samsung/tv/s3c-tvenc.c ++ * ++ * Driver file for Samsung TV Encoder ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* error codes */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++#include "s3c-tvenc.h" ++ ++#define PFX "s3c_tvenc" ++ ++static struct clk *tvenc_clock; ++static struct clk *h_clk; ++static int s3c_tvenc_irq = NO_IRQ; ++static struct resource *s3c_tvenc_mem; ++static void __iomem *base; ++static wait_queue_head_t waitq; ++static tv_out_params_t tv_param = {0,}; ++ ++/* Backup SFR value */ ++static u32 backup_reg[2]; ++ ++ ++/* Structure that declares the access functions*/ ++ ++static void s3c_tvenc_switch(tv_enc_switch_t sw) ++{ ++ if(sw == OFF) { ++ __raw_writel(__raw_readl(base + S3C_TVCTRL) ++ &~ S3C_TVCTRL_ON, base + S3C_TVCTRL); ++ } else if(sw == ON) { ++ __raw_writel(__raw_readl(base + S3C_TVCTRL) ++ | S3C_TVCTRL_ON, base + S3C_TVCTRL); ++ } else ++ printk("Error func:%s line:%d\n", __FUNCTION__, __LINE__); ++} ++ ++static void s3c_tvenc_set_image_size(u32 width, u32 height) ++{ ++ __raw_writel(IIS_WIDTH(width)| IIS_HEIGHT(height), ++ base + S3C_INIMAGESIZE); ++} ++ ++#if 0 ++static void s3c_tvenc_enable_macrovision(tv_standard_t tvmode, macro_pattern_t pattern) ++{ ++ switch(pattern) { ++ case AGC4L : ++ break; ++ case AGC2L : ++ break; ++ case N01 : ++ break; ++ case N02 : ++ break; ++ case P01 : ++ break; ++ case P02 : ++ break; ++ default : ++ break; ++ } ++} ++ ++static void s3c_tvenc_disable_macrovision(void) ++{ ++ __raw_writel(__raw_readl(base + S3C_MACROVISION0) ++ &~0xff, base + S3C_MACROVISION0); ++} ++#endif ++ ++static void s3c_tvenc_set_tv_mode(tv_standard_t mode, tv_conn_type_t out) ++{ ++ u32 signal_type = 0, output_type = 0; ++ ++ switch(mode) { ++ case PAL_N : ++ __raw_writel(VBP_VEFBPD_PAL|VBP_VOFBPD_PAL, ++ base + S3C_VBPORCH); ++ __raw_writel(HBP_HSPW_PAL|HBP_HBPD_PAL, ++ base + S3C_HBPORCH); ++ __raw_writel(HEO_DTO_PAL|HEO_HEOV_PAL, ++ base + S3C_HENHOFFSET); ++ __raw_writel(EPC_PED_ON, ++ base + S3C_PEDCTRL); ++ __raw_writel(YFB_YBW_26|YFB_CBW_06, ++ base + S3C_YCFILTERBW); ++ __raw_writel(SSC_HSYNC_PAL, ++ base + S3C_SYNCSIZECTRL); ++ __raw_writel(BSC_BEND_PAL|BSC_BSTART_PAL, ++ base + S3C_BURSTCTRL); ++ __raw_writel(MBS_BSTART_PAL, ++ base + S3C_MACROBURSTCTRL); ++ __raw_writel(AVP_AVEND_PAL|AVP_AVSTART_PAL, ++ base + S3C_ACTVIDPOCTRL); ++ break; ++ case PAL_NC : ++ case PAL_BGHID : ++ __raw_writel(VBP_VEFBPD_PAL|VBP_VOFBPD_PAL, ++ base + S3C_VBPORCH); ++ __raw_writel(HBP_HSPW_PAL|HBP_HBPD_PAL, ++ base + S3C_HBPORCH); ++ __raw_writel(HEO_DTO_PAL|HEO_HEOV_PAL, ++ base + S3C_HENHOFFSET); ++ __raw_writel(EPC_PED_OFF, ++ base + S3C_PEDCTRL); ++ __raw_writel(YFB_YBW_26|YFB_CBW_06, ++ base + S3C_YCFILTERBW); ++ __raw_writel(SSC_HSYNC_PAL, ++ base + S3C_SYNCSIZECTRL); ++ __raw_writel(BSC_BEND_PAL|BSC_BSTART_PAL, ++ base + S3C_BURSTCTRL); ++ __raw_writel(MBS_BSTART_PAL, ++ base + S3C_MACROBURSTCTRL); ++ __raw_writel(AVP_AVEND_PAL|AVP_AVSTART_PAL, ++ base + S3C_ACTVIDPOCTRL); ++ break; ++ case NTSC_443 : ++ __raw_writel(VBP_VEFBPD_NTSC|VBP_VOFBPD_NTSC, ++ base + S3C_VBPORCH); ++ __raw_writel(HBP_HSPW_NTSC|HBP_HBPD_NTSC, ++ base + S3C_HBPORCH); ++ __raw_writel(HEO_DTO_NTSC|HEO_HEOV_NTSC, ++ base + S3C_HENHOFFSET); ++ __raw_writel(EPC_PED_ON, ++ base + S3C_PEDCTRL); ++ __raw_writel(YFB_YBW_26|YFB_CBW_06, ++ base + S3C_YCFILTERBW); ++ __raw_writel(SSC_HSYNC_NTSC, ++ base + S3C_SYNCSIZECTRL); ++ __raw_writel(BSC_BEND_NTSC|BSC_BSTART_NTSC, ++ base + S3C_BURSTCTRL); ++ __raw_writel(MBS_BSTART_NTSC, ++ base + S3C_MACROBURSTCTRL); ++ __raw_writel(AVP_AVEND_NTSC|AVP_AVSTART_NTSC, ++ base + S3C_ACTVIDPOCTRL); ++ break; ++ case NTSC_J : ++ __raw_writel(VBP_VEFBPD_NTSC|VBP_VOFBPD_NTSC, ++ base + S3C_VBPORCH); ++ __raw_writel(HBP_HSPW_NTSC|HBP_HBPD_NTSC, ++ base + S3C_HBPORCH); ++ __raw_writel(HEO_DTO_NTSC|HEO_HEOV_NTSC, ++ base + S3C_HENHOFFSET); ++ __raw_writel(EPC_PED_OFF, ++ base + S3C_PEDCTRL); ++ __raw_writel(YFB_YBW_21|YFB_CBW_06, ++ base + S3C_YCFILTERBW); ++ __raw_writel(SSC_HSYNC_NTSC, ++ base + S3C_SYNCSIZECTRL); ++ __raw_writel(BSC_BEND_NTSC|BSC_BSTART_NTSC, ++ base + S3C_BURSTCTRL); ++ __raw_writel(MBS_BSTART_NTSC, ++ base + S3C_MACROBURSTCTRL); ++ __raw_writel(AVP_AVEND_NTSC|AVP_AVSTART_NTSC, ++ base + S3C_ACTVIDPOCTRL); ++ break; ++ case PAL_M : ++ case NTSC_M : ++ default : ++ __raw_writel(VBP_VEFBPD_NTSC|VBP_VOFBPD_NTSC, ++ base + S3C_VBPORCH); ++ __raw_writel(HBP_HSPW_NTSC|HBP_HBPD_NTSC, ++ base + S3C_HBPORCH); ++ __raw_writel(HEO_DTO_NTSC|HEO_HEOV_NTSC, ++ base + S3C_HENHOFFSET); ++ __raw_writel(EPC_PED_ON, ++ base + S3C_PEDCTRL); ++ __raw_writel(YFB_YBW_21|YFB_CBW_06, ++ base + S3C_YCFILTERBW); ++ __raw_writel(SSC_HSYNC_NTSC, ++ base + S3C_SYNCSIZECTRL); ++ __raw_writel(BSC_BEND_NTSC|BSC_BSTART_NTSC, ++ base + S3C_BURSTCTRL); ++ __raw_writel(MBS_BSTART_NTSC, ++ base + S3C_MACROBURSTCTRL); ++ __raw_writel(AVP_AVEND_NTSC|AVP_AVSTART_NTSC, ++ base + S3C_ACTVIDPOCTRL); ++ break; ++ } ++ ++ if(out == S_VIDEO) { ++ __raw_writel(YFB_YBW_60|YFB_CBW_06, ++ base + S3C_YCFILTERBW); ++ output_type = S3C_TVCTRL_OUTTYPE_S; ++ } else ++ output_type = S3C_TVCTRL_OUTTYPE_C; ++ ++ switch(mode) { ++ case NTSC_M : ++ signal_type = S3C_TVCTRL_OUTFMT_NTSC_M; ++ break; ++ case NTSC_J : ++ signal_type = S3C_TVCTRL_OUTFMT_NTSC_J; ++ break; ++ case PAL_BGHID : ++ signal_type = S3C_TVCTRL_OUTFMT_PAL_BDG; ++ break; ++ case PAL_M : ++ signal_type = S3C_TVCTRL_OUTFMT_PAL_M; ++ break; ++ case PAL_NC : ++ signal_type = S3C_TVCTRL_OUTFMT_PAL_NC; ++ break; ++ default: ++ printk("s3c_tvenc_set_tv_mode : No matching signal_type!\n"); ++ break; ++ } ++ ++ __raw_writel((__raw_readl(base + S3C_TVCTRL) ++ &~(0x1f<<4))| output_type | signal_type, ++ base + S3C_TVCTRL); ++ ++ __raw_writel(0x01, base + S3C_FSCAUXCTRL); ++} ++ ++#if 0 ++static void s3c_tvenc_set_pedestal(tv_enc_switch_t sw) ++{ ++ if(sw) ++ __raw_writel(EPC_PED_ON, base + S3C_PEDCTRL); ++ else ++ __raw_writel(EPC_PED_OFF, base + S3C_PEDCTRL); ++} ++ ++static void s3c_tvenc_set_sub_carrier_freq(u32 freq) ++{ ++ __raw_writel(FSC_CTRL(freq), base + S3C_FSCCTRL); ++} ++ ++static void s3c_tvenc_set_fsc_dto(u32 val) ++{ ++ unsigned int temp; ++ ++ temp = (0x1<<31)|(val&0x7fffffff); ++ __raw_writel(temp, base + S3C_FSCDTOMANCTRL); ++} ++ ++static void s3c_tvenc_disable_fsc_dto(void) ++{ ++ __raw_writel(__raw_readl(base + S3C_FSCDTOMANCTRL)&~(1<<31), ++ base + S3C_FSCDTOMANCTRL); ++} ++ ++static void s3c_tvenc_set_bg(u32 soft_mix, u32 color, u32 lum_offset) ++{ ++ unsigned int bg_color; ++ switch(color) { ++ case 0 : ++ bg_color = BGC_BGCS_BLACK; ++ break; ++ case 1 : ++ bg_color = BGC_BGCS_BLUE; ++ break; ++ case 2 : ++ bg_color = BGC_BGCS_RED; ++ break; ++ case 3 : ++ bg_color = BGC_BGCS_MAGENTA; ++ break; ++ case 4 : ++ bg_color = BGC_BGCS_GREEN; ++ break; ++ case 5 : ++ bg_color = BGC_BGCS_CYAN; ++ break; ++ case 6 : ++ bg_color = BGC_BGCS_YELLOW; ++ break; ++ case 7 : ++ bg_color = BGC_BGCS_WHITE; ++ break; ++ } ++ if(soft_mix) ++ __raw_writel(BGC_SME_ENA|bg_color|BGC_BGYOFS(lum_offset), ++ base + S3C_BGCTRL); ++ else ++ __raw_writel(BGC_SME_DIS|bg_color|BGC_BGYOFS(lum_offset), ++ base + S3C_BGCTRL); ++ ++} ++ ++static void s3c_tvenc_set_bg_vav_hav(u32 hav_len, u32 vav_len, u32 hav_st, u32 vav_st) ++{ ++ __raw_writel(BVH_BG_HL(hav_len)|BVH_BG_HS(hav_st)|BVH_BG_VL(vav_len)|BVH_BG_VS(vav_st), ++ base + S3C_BGHVAVCTRL); ++} ++#endif ++ ++static void s3c_tvenc_set_hue_phase(u32 phase_val) ++{ ++ __raw_writel(HUE_CTRL(phase_val), ++ base + S3C_HUECTRL); ++} ++ ++#if 0 ++static u32 s3c_tvenc_get_hue_phase(void) ++{ ++ return __raw_readl(base + S3C_HUECTRL)&0xff; ++} ++#endif ++ ++static void s3c_tvenc_set_contrast(u32 contrast) ++{ ++ u32 temp; ++ ++ temp = __raw_readl(base + S3C_CONTRABRIGHT); ++ ++ __raw_writel((temp &~0xff)|contrast, ++ base + S3C_CONTRABRIGHT); ++} ++ ++#if 0 ++static u32 s3c_tvenc_get_contrast(void) ++{ ++ return (__raw_readl(base + S3C_CONTRABRIGHT)&0xff); ++} ++#endif ++ ++static void s3c_tvenc_set_bright(u32 bright) ++{ ++ u32 temp; ++ ++ temp = __raw_readl(base + S3C_CONTRABRIGHT); ++ ++ __raw_writel((temp &~(0xff<<16))| (bright<<16), ++ base + S3C_CONTRABRIGHT); ++} ++ ++#if 0 ++static u32 s3c_tvenc_get_bright(void) ++{ ++ return ((__raw_readl(base + S3C_CONTRABRIGHT)&(0xff<<16))>>16); ++} ++ ++ ++static void s3c_tvenc_set_cbgain(u32 cbgain) ++{ ++ u32 temp; ++ ++ temp = __raw_readl(base + S3C_CBCRGAINCTRL); ++ ++ __raw_writel((temp &~0xff)|cbgain, ++ base + S3C_CBCRGAINCTRL); ++} ++ ++ ++static u32 s3c_tvenc_get_cbgain(void) ++{ ++ return (__raw_readl(base + S3C_CBCRGAINCTRL)&0xff); ++} ++ ++static void s3c_tvenc_set_crgain(u32 crgain) ++{ ++ u32 temp; ++ ++ temp = __raw_readl(base + S3C_CBCRGAINCTRL); ++ ++ __raw_writel((temp &~(0xff<<16))| (crgain<<16), ++ base + S3C_CBCRGAINCTRL); ++} ++ ++static u32 s3c_tvenc_get_crgain(void) ++{ ++ return ((__raw_readl(base + S3C_CBCRGAINCTRL)&(0xff<<16))>>16); ++} ++#endif ++ ++static void s3c_tvenc_enable_gamma_control(tv_enc_switch_t enable) ++{ ++ u32 temp; ++ ++ temp = __raw_readl(base + S3C_GAMMACTRL); ++ if(enable == ON) ++ temp |= (1<<12); ++ else ++ temp &= ~(1<<12); ++ ++ __raw_writel(temp, base + S3C_GAMMACTRL); ++} ++ ++static void s3c_tvenc_set_gamma_gain(u32 ggain) ++{ ++ u32 temp; ++ ++ temp = __raw_readl(base + S3C_GAMMACTRL); ++ ++ __raw_writel((temp &~(0x7<<8))| (ggain<<8), ++ base + S3C_GAMMACTRL); ++} ++ ++#if 0 ++static u32 s3c_tvenc_get_gamma_gain(void) ++{ ++ return ((__raw_readl(base + S3C_GAMMACTRL)&(0x7<<8))>>8); ++} ++ ++static void s3c_tvenc_enable_mute_control(tv_enc_switch_t enable) ++{ ++ u32 temp; ++ ++ temp = __raw_readl(base + S3C_GAMMACTRL); ++ if(enable == ON) ++ temp |= (1<<12); ++ else ++ temp &= ~(1<<12); ++ ++ __raw_writel(temp, base + S3C_GAMMACTRL); ++} ++ ++static void s3c_tvenc_set_mute(u32 y, u32 cb, u32 cr) ++{ ++ u32 temp; ++ ++ temp = __raw_readl(base + S3C_MUTECTRL); ++ ++ temp &=~(0xffffff<<8); ++ temp |= (cr & 0xff)<<24; ++ temp |= (cb & 0xff)<<16; ++ temp |= (y & 0xff)<<8; ++ ++ __raw_writel(temp, base + S3C_MUTECTRL); ++} ++ ++static void s3c_tvenc_get_mute(u32 *y, u32 *cb, u32 *cr) ++{ ++ u32 temp; ++ ++ temp = __raw_readl(base + S3C_MUTECTRL); ++ ++ *y = (temp&(0xff<<8))>>8; ++ *cb = (temp&(0xff<<16))>>16; ++ *cr = (temp&(0xff<<24))>>24; ++} ++#endif ++ ++static void s3c_tvenc_get_active_win_center(u32 *vert, u32 *horz) ++{ ++ u32 temp; ++ ++ temp = __raw_readl(base + S3C_HENHOFFSET); ++ ++ *vert = (temp&(0x3f<<24))>>24; ++ *horz = (temp&(0xff<<16))>>16; ++} ++ ++static void s3c_tvenc_set_active_win_center(u32 vert, u32 horz) ++{ ++ u32 temp; ++ ++ temp = __raw_readl(base + S3C_HENHOFFSET); ++ ++ temp &=~(0x3ffff<<16); ++ temp |= (vert&0x3f)<<24; ++ temp |= (horz&0xff)<<16; ++ ++ __raw_writel(temp, base + S3C_HENHOFFSET); ++} ++ ++// LCD display controller configuration functions ++static void s3c_lcd_set_output_path(lcd_local_output_t out) ++{ ++#if 0 // peter for 2.6.21 kernel ++ s3c_fb_set_output_path(out); ++#else // peter for 2.6.24 kernel ++ s3cfb_set_output_path(out); ++#endif ++} ++ ++static void s3c_lcd_set_clkval(u32 clkval) ++{ ++#if 0 // peter for 2.6.21 kernel ++ s3c_fb_set_clkval(clkval); ++#else // peter for 2.6.24 kernel ++ s3cfb_set_clock(clkval); ++#endif ++} ++ ++static void s3c_lcd_enable_rgbport(u32 on_off) ++{ ++#if 0 // peter for 2.6.21 kernel ++ s3c_fb_enable_rgbport(on_off); ++#else // peter for 2.6.24 kernel ++ s3cfb_enable_rgbport(on_off); ++#endif ++} ++ ++static void s3c_lcd_start(void) ++{ ++#if 0 // peter for 2.6.21 kernel ++ s3c_fb_start_lcd(); ++#else // peter for 2.6.24 kernel ++ s3cfb_start_lcd(); ++#endif ++} ++ ++static void s3c_lcd_stop(void) ++{ ++#if 0 // peter for 2.6.21 kernel ++ s3c_fb_stop_lcd(); ++#else // peter for 2.6.24 kernel ++ s3cfb_stop_lcd(); ++#endif ++} ++ ++ ++static void s3c_lcd_set_config(void) ++{ ++ backup_reg[0] = __raw_readl(S3C_VIDCON0); ++ backup_reg[1] = __raw_readl(S3C_VIDCON2); ++ ++ s3c_lcd_set_output_path(LCD_TVRGB); ++ tv_param.lcd_output_mode = LCD_TVRGB; ++ ++ s3c_lcd_set_clkval(4); ++ s3c_lcd_enable_rgbport(1); ++} ++ ++static void s3c_lcd_exit_config(void) ++{ ++ __raw_writel(backup_reg[0], S3C_VIDCON0); ++ __raw_writel(backup_reg[1], S3C_VIDCON2); ++ tv_param.lcd_output_mode = LCD_RGB; ++} ++ ++static int scaler_test_start(void) ++{ ++ tv_param.sp.DstFullWidth = 640; ++ tv_param.sp.DstFullHeight= 480; ++ tv_param.sp.DstCSpace = RGB16; ++ ++ s3c_tvscaler_config(&tv_param.sp); ++ ++ s3c_tvscaler_int_enable(1); ++ ++ s3c_tvscaler_start(); ++ ++ return 0; ++} ++ ++static int scaler_test_stop(void) ++{ ++ s3c_tvscaler_int_disable(); ++ ++ return 0; ++} ++ ++ ++static int tvout_start(void) ++{ ++ u32 width, height; ++ tv_standard_t type; ++ tv_conn_type_t conn; ++ ++ tv_param.sp.DstFullWidth *= 2; // For TV OUT ++ ++ width = tv_param.sp.DstFullWidth; ++ height = tv_param.sp.DstFullHeight; ++ type = tv_param.sig_type; ++ conn = tv_param.connect; ++ ++ /* Set TV-SCALER parameter */ ++ switch(tv_param.v2.input->type) { ++ case V4L2_INPUT_TYPE_FIFO: // LCD FIFO-OUT ++ tv_param.sp.Mode = FREE_RUN; ++ tv_param.sp.DstCSpace = YCBYCR; ++ /* Display controller setting */ ++ s3c_lcd_stop(); ++ s3c_lcd_set_config(); ++ break; ++ case V4L2_INPUT_TYPE_MSDMA: // MSDMA ++ tv_param.sp.Mode = FREE_RUN; ++ tv_param.sp.DstCSpace = YCBYCR; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ s3c_tvenc_set_tv_mode(type, conn); ++ s3c_tvenc_set_image_size(width, height); ++ s3c_tvenc_switch(ON); ++ ++ s3c_tvscaler_config(&tv_param.sp); // for setting DstStartX/Y, DstWidth/Height ++ s3c_tvscaler_set_interlace(1); ++ if(tv_param.v2.input->type == V4L2_INPUT_TYPE_FIFO) ++ s3c_tvscaler_int_disable(); ++ else ++ s3c_tvscaler_int_enable(1); ++ s3c_tvscaler_start(); ++ ++ if(tv_param.v2.input->type == V4L2_INPUT_TYPE_FIFO) ++ s3c_lcd_start(); ++ ++ return 0; ++} ++ ++static int tvout_stop(void) ++{ ++ ++ s3c_tvscaler_set_interlace(0); ++ s3c_tvscaler_stop_freerun(); ++ s3c_tvscaler_int_disable(); ++ s3c_tvenc_switch(OFF); ++ ++ switch(tv_param.v2.input->type) { ++ case V4L2_INPUT_TYPE_FIFO: // LCD FIFO-OUT ++ /* Display controller setting */ ++ s3c_lcd_stop(); ++ s3c_lcd_exit_config(); ++ s3c_lcd_start(); ++ break; ++ default: ++ break; ++ } ++ return 0; ++} ++ ++/* ------------------------------------------ V4L2 SUPPORT ----------------------------------------------*/ ++/* ------------- In FIFO and MSDMA, v4l2_input supported by S3C TVENC controller ------------------*/ ++static struct v4l2_input tvenc_inputs[] = { ++ { ++ .index = 0, ++ .name = "LCD FIFO_OUT", ++ .type = V4L2_INPUT_TYPE_FIFO, ++ .audioset = 1, ++ .tuner = 0, /* ignored */ ++ .std = 0, ++ .status = 0, ++ }, ++ { ++ .index = 1, ++ .name = "Memory input (MSDMA)", ++ .type = V4L2_INPUT_TYPE_MSDMA, ++ .audioset = 2, ++ .tuner = 0, ++ .std = 0, ++ .status = 0, ++ } ++}; ++ ++/* ------------ Out FIFO and MADMA, v4l2_output supported by S3C TVENC controller ----------------*/ ++static struct v4l2_output tvenc_outputs[] = { ++ { ++ .index = 0, ++ .name = "TV-OUT", ++ .type = V4L2_OUTPUT_TYPE_ANALOG, ++ .audioset = 0, ++ .modulator = 0, ++ .std = V4L2_STD_PAL | V4L2_STD_NTSC_M, ++ }, ++ { ++ .index = 1, ++ .name = "Memory output (MSDMA)", ++ .type = V4L2_OUTPUT_TYPE_MSDMA, ++ .audioset = 0, ++ .modulator = 0, ++ .std = 0, ++ }, ++ ++}; ++ ++const struct v4l2_fmtdesc tvenc_input_formats[] = { ++ { ++ .index = 0, ++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, ++ .description = "16 bpp RGB, le", ++ .pixelformat = V4L2_PIX_FMT_RGB565, ++ .flags = FORMAT_FLAGS_PACKED, ++ }, ++ { ++ .index = 1, ++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, ++ .flags = FORMAT_FLAGS_PACKED, ++ .description = "24 bpp RGB, le", ++ .pixelformat = V4L2_PIX_FMT_RGB24, ++ }, ++ { ++ .index = 2, ++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, ++ .flags = FORMAT_FLAGS_PLANAR, ++ .description = "4:2:2, planar, Y-Cb-Cr", ++ .pixelformat = V4L2_PIX_FMT_YUV422P, ++ ++ }, ++ { ++ .index = 3, ++ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, ++ .flags = FORMAT_FLAGS_PLANAR, ++ .description = "4:2:0, planar, Y-Cb-Cr", ++ .pixelformat = V4L2_PIX_FMT_YUV420, ++ } ++}; ++ ++ ++const struct v4l2_fmtdesc tvenc_output_formats[] = { ++ { ++ .index = 0, ++ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT, ++ .description = "16 bpp RGB, le", ++ .pixelformat = V4L2_PIX_FMT_RGB565, ++ .flags = FORMAT_FLAGS_PACKED, ++ }, ++ { ++ .index = 1, ++ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT, ++ .flags = FORMAT_FLAGS_PACKED, ++ .description = "24 bpp RGB, le", ++ .pixelformat = V4L2_PIX_FMT_RGB24, ++ }, ++ { ++ .index = 2, ++ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT, ++ .flags = FORMAT_FLAGS_PLANAR, ++ .description = "4:2:2, planar, Y-Cb-Cr", ++ .pixelformat = V4L2_PIX_FMT_YUV422P, ++ ++ }, ++ { ++ .index = 3, ++ .type = V4L2_BUF_TYPE_VIDEO_OUTPUT, ++ .flags = FORMAT_FLAGS_PLANAR, ++ .description = "4:2:0, planar, Y-Cb-Cr", ++ .pixelformat = V4L2_PIX_FMT_YUV420, ++ } ++}; ++ ++const struct v4l2_standard tvout_standards[] = { ++ { ++ .index = 0, ++ .id = V4L2_STD_NTSC_M, ++ .name = "NTSC type", ++ }, ++ { ++ .index = 1, ++ .id = V4L2_STD_PAL, ++ .name = "PAL type", ++ } ++}; ++ ++#define NUMBER_OF_INPUT_FORMATS ARRAY_SIZE(tvenc_input_formats) ++#define NUMBER_OF_OUTPUT_FORMATS ARRAY_SIZE(tvenc_output_formats) ++#define NUMBER_OF_INPUTS ARRAY_SIZE(tvenc_inputs) ++#define NUMBER_OF_OUTPUTS ARRAY_SIZE(tvenc_outputs) ++#define NUMBER_OF_STANDARDS ARRAY_SIZE(tvout_standards) ++ ++static int s3c_tvenc_g_fmt(struct v4l2_format *f) ++{ ++ int size = sizeof(struct v4l2_pix_format); ++ ++ memset(&f->fmt.pix, 0, size); ++ memcpy(&f->fmt.pix, &tv_param.v2.pixfmt, size); ++ ++ return 0; ++} ++ ++static int s3c_tvenc_s_fmt(struct v4l2_format *f) ++{ ++ /* update our state informations */ ++ tv_param.v2.pixfmt= f->fmt.pix; ++ ++ // peter LCD output related operation ++ if (tv_param.v2.pixfmt.pixelformat == V4L2_PIX_FMT_RGB565 ) { ++ ++ tv_param.sp.SrcFullWidth = tv_param.v2.pixfmt.width; ++ tv_param.sp.SrcFullHeight = tv_param.v2.pixfmt.height; ++ tv_param.sp.SrcStartX = 0; ++ tv_param.sp.SrcStartY = 0; ++ tv_param.sp.SrcWidth = tv_param.sp.SrcFullWidth; ++ tv_param.sp.SrcHeight = tv_param.sp.SrcFullHeight; ++ ++ printk("TV-OUT: LCD path operation set\n"); ++ ++ // peter for padded data of mfc output ++ } else if (tv_param.v2.pixfmt.pixelformat == V4L2_PIX_FMT_YUV420) { ++ ++#ifdef DIVX_TEST // padded output ++ tv_param.sp.SrcFullWidth = tv_param.v2.pixfmt.width + 2*16; ++ tv_param.sp.SrcFullHeight = tv_param.v2.pixfmt.height + 2*16; ++ tv_param.sp.SrcStartX = 16; ++ tv_param.sp.SrcStartY = 16; ++ tv_param.sp.SrcWidth = tv_param.sp.SrcFullWidth - 2*tv_param.sp.SrcStartX; ++ tv_param.sp.SrcHeight = tv_param.sp.SrcFullHeight - 2*tv_param.sp.SrcStartY; ++#else // not padded output ++ tv_param.sp.SrcFullWidth = tv_param.v2.pixfmt.width; ++ tv_param.sp.SrcFullHeight = tv_param.v2.pixfmt.height; ++ tv_param.sp.SrcStartX = 0; ++ tv_param.sp.SrcStartY = 0; ++ tv_param.sp.SrcWidth = tv_param.sp.SrcFullWidth; ++ tv_param.sp.SrcHeight = tv_param.sp.SrcFullHeight; ++#endif ++ ++ printk("TV-OUT: MFC path operation set\n"); ++ ++ } ++ ++ switch(tv_param.v2.pixfmt.pixelformat) { ++ case V4L2_PIX_FMT_RGB565: ++ tv_param.sp.SrcCSpace = RGB16; ++ break; ++ case V4L2_PIX_FMT_RGB24: ++ tv_param.sp.SrcCSpace = RGB24; ++ break; ++ case V4L2_PIX_FMT_YUV420: ++ tv_param.sp.SrcCSpace = YC420; ++ break; ++ case V4L2_PIX_FMT_YUV422P: ++ tv_param.sp.SrcCSpace = YC422; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++// camif_convert_into_camif_cfg_t(cfg, 1); ++ return 0; ++} ++ ++static int s3c_tvenc_s_input(int index) ++{ ++ ++ tv_param.v2.input = &tvenc_inputs[index]; ++ switch(tv_param.v2.input->type) { ++ case V4L2_INPUT_TYPE_FIFO: // LCD FIFO-OUT ++ tv_param.sp.InPath = POST_FIFO; ++ break; ++ case V4L2_INPUT_TYPE_MSDMA: // MSDMA ++ tv_param.sp.InPath = POST_DMA; ++ break; ++ default: ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++static int s3c_tvenc_s_output(int index) ++{ ++ tv_param.v2.output = &tvenc_outputs[index]; ++ switch(tv_param.v2.output->type) { ++ case V4L2_OUTPUT_TYPE_ANALOG: // TV-OUT (FIFO-OUT) ++ tv_param.sp.OutPath = POST_FIFO; ++ break; ++ case V4L2_OUTPUT_TYPE_MSDMA: // MSDMA ++ tv_param.sp.OutPath = POST_DMA; ++ break; ++ default: ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++static int s3c_tvenc_s_std(v4l2_std_id *id) ++{ ++// printk("s3c_tvenc_s_std: *id=0x%x",*id); ++ switch(*id) { ++ case V4L2_STD_NTSC_M: ++ tv_param.sig_type = NTSC_M; ++ tv_param.sp.DstFullWidth = 720; ++ tv_param.sp.DstFullHeight = 480; ++ break; ++ case V4L2_STD_PAL: ++ tv_param.sig_type = PAL_M; ++ tv_param.sp.DstFullWidth = 720; ++ tv_param.sp.DstFullHeight = 576; ++ break; ++ default: ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++static int s3c_tvenc_v4l2_control(struct v4l2_control *ctrl) ++{ ++ switch(ctrl->id) { ++ ++ // peter added for MFC related op. ++ case V4L2_CID_MPEG_STREAM_PID_VIDEO: ++ { ++ //printk("[TV]SRCFRMST=%x\n",ctrl->value); ++ tv_param.sp.SrcFrmSt = ctrl->value; ++ return 0; ++ } ++ ++ case V4L2_CID_CONNECT_TYPE: ++ { ++ if(ctrl->value == 0) { // COMPOSITE ++ tv_param.connect = COMPOSITE; ++ } else if(ctrl->value == 1) { //S-VIDEO ++ tv_param.connect = S_VIDEO; ++ } else { ++ return -EINVAL; ++ } ++ return 0; ++ } ++ ++ case V4L2_CID_BRIGHTNESS: ++ { ++ s32 val = ctrl->value; ++ if((val > 0xff)||(val < 0)) ++ return -EINVAL; ++ else ++ s3c_tvenc_set_bright(val); ++ ++ return 0; ++ } ++ ++ case V4L2_CID_CONTRAST: ++ { ++ s32 val = ctrl->value; ++ if((val > 0xff)||(val < 0)) ++ return -EINVAL; ++ else ++ s3c_tvenc_set_contrast(val); ++ ++ return 0; ++ } ++ ++ case V4L2_CID_GAMMA: ++ { ++ s32 val = ctrl->value; ++ if((val > 0x3)||(val < 0)) { ++ return -EINVAL; ++ } else { ++ s3c_tvenc_enable_gamma_control(ON); ++ s3c_tvenc_set_gamma_gain(val); ++ s3c_tvenc_enable_gamma_control(OFF); ++ } ++ return 0; ++ } ++ ++ case V4L2_CID_HUE: ++ { ++ s32 val = ctrl->value; ++ if((val > 0xff)||(val < 0)) ++ return -EINVAL; ++ else ++ s3c_tvenc_set_hue_phase(val); ++ ++ return 0; ++ } ++ ++ case V4L2_CID_HCENTER: ++ { ++ s32 val = ctrl->value; ++ u32 curr_horz, curr_vert; ++ ++ if((val > 0xff)||(val < 0)) { ++ return -EINVAL; ++ } else { ++ s3c_tvenc_get_active_win_center(&curr_vert, &curr_horz); ++ s3c_tvenc_set_active_win_center(curr_vert, val); ++ } ++ ++ return 0; ++ } ++ ++ case V4L2_CID_VCENTER: ++ { ++ s32 val = ctrl->value; ++ u32 curr_horz, curr_vert; ++ ++ if((val > 0x3f)||(val < 0)) { ++ return -EINVAL; ++ } else { ++ s3c_tvenc_get_active_win_center(&curr_vert, &curr_horz); ++ s3c_tvenc_set_active_win_center(val, curr_horz); ++ } ++ ++ return 0; ++ } ++ ++ default: ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++int s3c_tvenc_open(struct inode *inode, struct file *filp) ++{ ++ int err; ++ ++ err = video_exclusive_open(inode, filp); // One function of V4l2 driver ++ ++ if(err < 0) ++ return err; ++ filp->private_data = &tv_param; ++ ++ s3c_tvscaler_init(); ++ ++ /* Success */ ++ return 0; ++} ++ ++int s3c_tvenc_release(struct inode *inode, struct file *filp) ++{ ++ video_exclusive_release(inode, filp); ++ ++ /* Success */ ++ return 0; ++} ++ ++static int s3c_tvenc_do_ioctl(struct inode *inode,struct file *filp,unsigned int cmd,void *arg) ++{ ++ int ret; ++ ++ switch(cmd){ ++ case VIDIOC_QUERYCAP: ++ { ++ struct v4l2_capability *cap = arg; ++ strcpy(cap->driver, "S3C TV-OUT driver"); ++ strlcpy(cap->card, tv_param.v->name, sizeof(cap->card)); ++ sprintf(cap->bus_info, "ARM AHB BUS"); ++ cap->version = 0; ++ cap->capabilities = tv_param.v->type2; ++ return 0; ++ } ++ ++ case VIDIOC_OVERLAY: ++ { ++ int on = *(int *)arg; ++ ++ printk("TV-OUT: VIDIOC_OVERLAY on:%d\n", on); ++ if (on != 0) { ++ ret = tvout_start(); ++ } else { ++ ret = tvout_stop(); ++ } ++ return ret; ++ } ++ ++ case VIDIOC_ENUMINPUT: ++ { ++ struct v4l2_input *i = arg; ++ printk("TV-OUT: VIDIOC_ENUMINPUT : index = %d\n", i->index); ++ ++ if ((i->index) >= NUMBER_OF_INPUTS) { ++ return -EINVAL; ++ } ++ memcpy(i, &tvenc_inputs[i->index], sizeof(struct v4l2_input)); ++ return 0; ++ } ++ ++ case VIDIOC_S_INPUT: // 0 -> LCD FIFO-OUT, 1 -> MSDMA ++ { ++ int index = *((int *)arg); ++ printk("TV-OUT: VIDIOC_S_INPUT \n"); ++ ++ if (index >= NUMBER_OF_INPUTS) { ++ return -EINVAL; ++ } ++ else { ++ s3c_tvenc_s_input(index); ++ return 0; ++ } ++ } ++ ++ case VIDIOC_G_INPUT: ++ { ++ u32 *i = arg; ++ printk("TV-OUT: VIDIOC_G_INPUT \n"); ++ *i = tv_param.v2.input->type; ++ return 0; ++ } ++ ++ case VIDIOC_ENUMOUTPUT: ++ { ++ struct v4l2_output *i = arg; ++ printk("TV-OUT: VIDIOC_ENUMOUTPUT : index = %d\n", i->index); ++ ++ if ((i->index) >= NUMBER_OF_OUTPUTS) { ++ return -EINVAL; ++ } ++ memcpy(i, &tvenc_outputs[i->index], sizeof(struct v4l2_output)); ++ return 0; ++ } ++ ++ case VIDIOC_S_OUTPUT: // 0 -> TV / FIFO , 1 -> MSDMA ++ { ++ int index = *((int *)arg); ++ printk("TV-OUT: VIDIOC_S_OUTPUT \n"); ++ ++ if (index >= NUMBER_OF_OUTPUTS) { ++ return -EINVAL; ++ } ++ else { ++ s3c_tvenc_s_output(index); ++ return 0; ++ } ++ } ++ ++ case VIDIOC_G_OUTPUT: ++ { ++ u32 *i = arg; ++ printk("VIDIOC_G_OUTPUT \n"); ++ *i = tv_param.v2.output->type; ++ return 0; ++ } ++ ++ case VIDIOC_ENUM_FMT: ++ { struct v4l2_fmtdesc *f = arg; ++ enum v4l2_buf_type type = f->type; ++ int index = f->index; ++ ++ printk("C: VIDIOC_ENUM_FMT : index = %d\n", index); ++ if (index >= NUMBER_OF_INPUT_FORMATS) ++ return -EINVAL; ++ ++ switch (type) { ++ case V4L2_BUF_TYPE_VIDEO_CAPTURE: ++ break; ++ case V4L2_BUF_TYPE_VIDEO_OUTPUT: ++ default: ++ return -EINVAL; ++ } ++ memset(f, 0, sizeof(*f)); ++ memcpy(f, tv_param.v2.fmtdesc+index, sizeof(*f)); ++ return 0; ++ } ++ ++ case VIDIOC_G_FMT: ++ { ++ struct v4l2_format *f = arg; ++ printk("C: VIDIOC_G_FMT \n"); ++ ret = s3c_tvenc_g_fmt(f); ++ return ret; ++ } ++ ++ case VIDIOC_S_FMT: ++ { ++ struct v4l2_format *f = arg; ++ printk("C: VIDIOC_S_FMT \n"); ++ ret = s3c_tvenc_s_fmt(f); ++ if(ret != 0) { ++ printk("s3c_tvenc_set_fmt() failed !\n"); ++ return -EINVAL; ++ } ++ return ret; ++ } ++ ++ case VIDIOC_S_CTRL: ++ { ++ struct v4l2_control *ctrl = arg; ++ //printk("P: VIDIOC_S_CTRL \n"); ++ ret = s3c_tvenc_v4l2_control(ctrl); ++ return ret; ++ } ++ ++ case VIDIOC_ENUMSTD: ++ { ++ struct v4l2_standard *e = arg; ++ unsigned int index = e->index; ++ ++ if (index >= NUMBER_OF_STANDARDS) ++ return -EINVAL; ++ v4l2_video_std_construct(e, tvout_standards[e->index].id, ++ tvout_standards[e->index].name); ++ e->index = index; ++ return 0; ++ } ++ ++ case VIDIOC_G_STD: ++ { ++ v4l2_std_id *id = arg; ++ *id = tvout_standards[0].id; ++ return 0; ++ } ++ ++ case VIDIOC_S_STD: ++ { ++ v4l2_std_id *id = arg; ++ unsigned int i; ++ ++ for (i = 0; i < NUMBER_OF_STANDARDS; i++) { ++ //printk("P: *id = %d, tvout_standards[i].id = %d\n", *id, tvout_standards[i].id); ++ if (*id & tvout_standards[i].id) ++ break; ++ } ++ if (i == NUMBER_OF_STANDARDS) ++ return -EINVAL; ++ ++ ret = s3c_tvenc_s_std(id); ++ return ret; ++ } ++ ++ case VIDIOC_S_TVOUT_ON: ++ { ++ //int *SrcFrmSt = arg; ++ //printk("---peter VIDIOC_S_TVOUT_ON : SrcFrmSt = 0x%08x\n", *SrcFrmSt); ++ ret = tvout_start(); ++ return ret; ++ } ++ ++ case VIDIOC_S_TVOUT_OFF: ++ { ++ ret = tvout_stop(); ++ return ret; ++ } ++ ++ case VIDIOC_S_SCALER_TEST: ++ { ++ ret = scaler_test_start(); ++ mdelay(1); ++ ret = scaler_test_stop(); ++ return ret; ++ } ++ ++ default: ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++static int s3c_tvenc_ioctl_v4l2(struct inode *inode, struct file *filp, unsigned int cmd, ++ unsigned long arg) ++{ ++ return video_usercopy(inode, filp, cmd, arg, s3c_tvenc_do_ioctl); ++} ++ ++int s3c_tvenc_read(struct file *filp, char *buf, size_t count, ++ loff_t *f_pos) ++{ ++ return 0; ++} ++ ++int s3c_tvenc_write(struct file *filp, const char *buf, size_t ++ count, loff_t *f_pos) ++{ ++ return 0; ++} ++ ++int s3c_tvenc_mmap(struct file *filp, struct vm_area_struct *vma) ++{ ++ u32 size = vma->vm_end - vma->vm_start; ++ u32 max_size; ++ u32 page_frame_no; ++ ++ page_frame_no = __phys_to_pfn(POST_BUFF_BASE_ADDR); ++ ++ max_size = RESERVE_POST_MEM + PAGE_SIZE - (RESERVE_POST_MEM % PAGE_SIZE); ++ ++ if(size > max_size) { ++ return -EINVAL; ++ } ++ ++ vma->vm_flags |= VM_RESERVED; ++ ++ if( remap_pfn_range(vma, vma->vm_start, page_frame_no, ++ size, vma->vm_page_prot)) { ++ printk(KERN_ERR "%s: mmap_error\n", __FUNCTION__); ++ return -EAGAIN; ++ ++ } ++ ++ return 0; ++} ++ ++struct file_operations s3c_tvenc_fops = { ++ .owner = THIS_MODULE, ++ .open = s3c_tvenc_open, ++ .ioctl = s3c_tvenc_ioctl_v4l2, ++ .release = s3c_tvenc_release, ++ .read = s3c_tvenc_read, ++ .write = s3c_tvenc_write, ++ .mmap = s3c_tvenc_mmap, ++}; ++ ++void s3c_tvenc_vdev_release (struct video_device *vdev) { ++ kfree(vdev); ++} ++ ++struct video_device tvencoder = { ++ .name = "TVENCODER", ++ .vfl_type = VID_TYPE_OVERLAY | VID_TYPE_CAPTURE | VID_TYPE_SCALES, ++ .type2 = V4L2_CAP_VIDEO_OUTPUT| V4L2_CAP_VIDEO_CAPTURE, /* V4L2 */ ++ //.hardware = 0x01, // peter for 2.6.24 kernel ++ .fops = &s3c_tvenc_fops, ++ .release = s3c_tvenc_vdev_release, ++ .minor = TVENC_MINOR, ++}; ++ ++irqreturn_t s3c_tvenc_isr(int irq, void *dev_id, ++ struct pt_regs *regs) ++{ ++ u32 mode; ++ ++ mode = __raw_readl(base + S3C_TVCTRL); ++ ++ // Clear FIFO under-run status pending bit ++ mode |= (1<<12); ++ ++ __raw_writel(mode, base + S3C_TVCTRL); ++ ++ wake_up_interruptible(&waitq); ++ return IRQ_HANDLED; ++} ++ ++static int s3c_tvenc_probe(struct platform_device *pdev) ++{ ++ ++ struct resource *res; ++ ++ int ret; ++ ++ /* find the IRQs */ ++ s3c_tvenc_irq = platform_get_irq(pdev, 0); ++ if(s3c_tvenc_irq <= 0) { ++ printk(KERN_ERR PFX "failed to get irq resouce\n"); ++ return -ENOENT; ++ } ++ ++ /* get the memory region for the tv scaler driver */ ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if(res == NULL) { ++ printk(KERN_ERR PFX "failed to get memory region resouce\n"); ++ return -ENOENT; ++ } ++ ++ s3c_tvenc_mem = request_mem_region(res->start, res->end-res->start+1, pdev->name); ++ if(s3c_tvenc_mem == NULL) { ++ printk(KERN_ERR PFX "failed to reserve memory region\n"); ++ return -ENOENT; ++ } ++ ++ ++ base = ioremap(s3c_tvenc_mem->start, s3c_tvenc_mem->end - res->start + 1); ++ if(s3c_tvenc_mem == NULL) { ++ printk(KERN_ERR PFX "failed ioremap\n"); ++ return -ENOENT; ++ } ++ ++ tvenc_clock = clk_get(&pdev->dev, "tv_encoder"); ++ if(tvenc_clock == NULL) { ++ printk(KERN_ERR PFX "failed to find tvenc clock source\n"); ++ return -ENOENT; ++ } ++ ++ clk_enable(tvenc_clock); ++ ++ h_clk = clk_get(&pdev->dev, "hclk"); ++ if(h_clk == NULL) { ++ printk(KERN_ERR PFX "failed to find h_clk clock source\n"); ++ return -ENOENT; ++ } ++ ++ init_waitqueue_head(&waitq); ++ ++ tv_param.v = video_device_alloc(); ++ if(!tv_param.v) { ++ printk(KERN_ERR "s3c-tvenc: video_device_alloc() failed\n"); ++ return -ENOMEM; ++ } ++ memcpy(tv_param.v, &tvencoder, sizeof(tvencoder)); ++ if(video_register_device(tv_param.v, VFL_TYPE_GRABBER, TVENC_MINOR) != 0) { ++ printk("s3c_camera_driver.c : Couldn't register this codec driver.\n"); ++ return 0; ++ } ++ ++ ret = request_irq(s3c_tvenc_irq, (irq_handler_t) s3c_tvenc_isr, IRQF_DISABLED, ++ "TV_ENCODER", NULL); ++ if (ret) { ++ printk("request_irq(TV_ENCODER) failed.\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int s3c_tvenc_remove(struct platform_device *dev) ++{ ++ printk(KERN_INFO "s3c_tvenc_remove called !\n"); ++ clk_disable(tvenc_clock); ++ free_irq(s3c_tvenc_irq, NULL); ++ if (s3c_tvenc_mem != NULL) { ++ pr_debug("s3-tvenc: releasing s3c_tvenc_mem\n"); ++ iounmap(base); ++ release_resource(s3c_tvenc_mem); ++ kfree(s3c_tvenc_mem); ++ } ++// video_unregister_device(tv_param.v); ++ return 0; ++} ++ ++static int s3c_tvenc_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ clk_disable(tvenc_clock); ++ return 0; ++} ++ ++static int s3c_tvenc_resume(struct platform_device *pdev) ++{ ++ clk_enable(tvenc_clock); ++ return 0; ++} ++ ++static struct platform_driver s3c_tvenc_driver = { ++ .probe = s3c_tvenc_probe, ++ .remove = s3c_tvenc_remove, ++ .suspend = s3c_tvenc_suspend, ++ .resume = s3c_tvenc_resume, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "s3c-tvenc", ++ }, ++}; ++ ++static char banner[] __initdata = KERN_INFO "S3C6410 TV encoder Driver, (c) 2008 Samsung Electronics\n"; ++ ++static int __init s3c_tvenc_init(void) ++{ ++ ++ printk(banner); ++ ++ if(platform_driver_register(&s3c_tvenc_driver) != 0) ++ { ++ printk("Platform Device Register Failed \n"); ++ return -1; ++ } ++ ++ printk(" S3C6410 TV encoder Driver init OK. \n"); ++ return 0; ++} ++ ++static void __exit s3c_tvenc_exit(void) ++{ ++ ++ video_unregister_device(tv_param.v); ++ platform_driver_unregister(&s3c_tvenc_driver); ++ ++ printk("S3C6410 TV encoder Driver module exit. \n"); ++} ++ ++/* ++ * open/release helper functions -- handle exclusive opens ++ * Should be removed soon ++ */ ++int video_exclusive_open(struct inode *inode, struct file *file) ++{ ++ struct video_device *vfl = video_devdata(file); ++ int retval = 0; ++ ++// mutex_lock(&vfl->lock); ++ if (vfl->users) { ++ retval = -EBUSY; ++ } else { ++ vfl->users++; ++ } ++// mutex_unlock(&vfl->lock); ++ return retval; ++} ++ ++int video_exclusive_release(struct inode *inode, struct file *file) ++{ ++ struct video_device *vfl = video_devdata(file); ++ ++ vfl->users--; ++ return 0; ++} ++ ++module_init(s3c_tvenc_init); ++module_exit(s3c_tvenc_exit); ++ ++ ++MODULE_AUTHOR("Peter, Oh"); ++MODULE_DESCRIPTION("S3C TV Encoder Device Driver"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/tv/s3c-tvenc.h linux-2.6.28.6/drivers/media/video/samsung/tv/s3c-tvenc.h +--- linux-2.6.28/drivers/media/video/samsung/tv/s3c-tvenc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/tv/s3c-tvenc.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,171 @@ ++#ifndef __S3CTVENC_H_ ++#define __S3CTVENC_H_ ++ ++#include "s3c-tvscaler.h" ++ ++ ++#define TVENC_IOCTL_MAGIC 'T' ++ ++typedef struct { ++ ++} s3c_tvenc_info; ++ ++#define TV_ON _IO(TVENC_IOCTL_MAGIC, 0) ++#define TV_OFF _IO(TVENC_IOCTL_MAGIC, 1) ++#define SELECT_TV_OUT_FORMAT _IO(TVENC_IOCTL_MAGIC, 2) ++ ++#define TVENC_IOCTL_MAXNR 6 ++ ++#define TVENC_MINOR 14 // Just some number ++ ++typedef enum { ++ OFF, ++ ON ++} tv_enc_switch_t; ++ ++typedef enum { ++ NTSC_M, ++ PAL_M, ++ PAL_BGHID, ++ PAL_N, ++ PAL_NC, ++ PAL_60, ++ NTSC_443, ++ NTSC_J ++} tv_standard_t; ++ ++typedef enum { ++ QCIF, CIF/*352x288*/, ++ QQVGA, QVGA, VGA, SVGA/*800x600*/, SXGA/*1280x1024*/, UXGA/*1600x1200*/, QXGA/*2048x1536*/, ++ WVGA/*854x480*/, HD720/*1280x720*/, HD1080/*1920x1080*/ ++} img_size_t; ++ ++typedef enum { ++ BLACKSTRETCH, WHITESTRETCH, BLUESTRETCH ++} stretch_color_t; ++ ++typedef enum { ++ COMPOSITE, S_VIDEO ++} tv_conn_type_t; ++ ++typedef enum { ++ BLACK, BLUE, RED, MAGENTA, GREEN, CYAN, YELLOW, WHITE ++} bg_color_t; ++ ++typedef enum { ++ MUTE_Y, MUTE_CB, MUTE_CR ++} mute_type_t; ++ ++typedef enum { ++ AGC4L, AGC2L, N01, N02, P01, P02 ++} macro_pattern_t; ++ ++typedef enum { ++ LCD_RGB, LCD_TV, LCD_I80F, LCD_I80S, ++ LCD_TVRGB, LCD_TVI80F, LCD_TVI80S ++} lcd_local_output_t; ++ ++/* when App want to change v4l2 parameter, ++ * we instantly store it into v4l2_t v2 ++ * and then reflect it to hardware ++ */ ++typedef struct v4l2 { ++ struct v4l2_fmtdesc *fmtdesc; ++// struct v4l2_framebuffer frmbuf; /* current frame buffer */ ++ struct v4l2_pix_format pixfmt; ++ struct v4l2_input *input; ++ struct v4l2_output *output; ++// enum v4l2_status status; ++} v4l2_t; ++ ++ ++typedef struct { ++ tv_standard_t sig_type; ++ tv_conn_type_t connect; ++ /* Width of input image. The input value is twice original output image ++ * width. For example, you must set 1440 when the image width is 720. ++ * Max value is 1440 ++ */ ++ unsigned int in_width; ++ /* Height of input image ++ * Max value is 576 ++ */ ++ unsigned int in_height; ++ ++ // Setting value of VIDOUT[28:26] in Display ++ // controller(VIDCON0) ++ lcd_local_output_t lcd_output_mode; ++ // Set CLKVAL_F[13:6] of VIDCON0 with ++ // this value ++ unsigned int lcd_clkval_f; ++ ++ // Flag of lcd rgb port ++ // 0 : disable, 1 : enable ++ unsigned int lcd_rgb_port_flag; ++ ++ scaler_params_t sp; ++ ++ struct video_device *v; ++ v4l2_t v2; ++ ++} tv_out_params_t; ++ ++#define V4L2_INPUT_TYPE_MSDMA 3 ++#define V4L2_INPUT_TYPE_FIFO 4 ++#define V4L2_OUTPUT_TYPE_MSDMA 4 ++ ++#define FORMAT_FLAGS_DITHER 0x01 ++#define FORMAT_FLAGS_PACKED 0x02 ++#define FORMAT_FLAGS_PLANAR 0x04 ++#define FORMAT_FLAGS_RAW 0x08 ++#define FORMAT_FLAGS_CrCb 0x10 ++ ++/**************************************************************** ++* struct v4l2_control ++* Control IDs defined by S3C ++*****************************************************************/ ++ ++/* TV-OUT connector type */ ++#define V4L2_CID_CONNECT_TYPE (V4L2_CID_PRIVATE_BASE+0) ++ ++/**************************************************************** ++* I O C T L C O D E S F O R V I D E O D E V I C E S ++* It's only for S3C ++*****************************************************************/ ++#define VIDIOC_S_TVOUT_ON _IO ('V', BASE_VIDIOC_PRIVATE+0) ++#define VIDIOC_S_TVOUT_OFF _IO ('V', BASE_VIDIOC_PRIVATE+1) ++#define VIDIOC_S_SCALER_TEST _IO ('V', BASE_VIDIOC_PRIVATE+3) ++ ++ ++extern void s3c_tvscaler_config(scaler_params_t * sp); ++extern void s3c_tvscaler_int_enable(unsigned int int_type); ++extern void s3c_tvscaler_int_disable(void); ++extern void s3c_tvscaler_start(void); ++extern void s3c_tvscaler_stop_freerun(void); ++extern void s3c_tvscaler_init(void); ++extern void s3c_tvscaler_set_interlace(unsigned int on_off); ++extern int video_exclusive_release(struct inode * inode, struct file * file); ++extern int video_exclusive_open(struct inode * inode, struct file * file); ++ ++#if 0 // peter for 2.6.21 kernel ++extern void s3c_fb_start_lcd(void); ++extern void s3c_fb_stop_lcd(void); ++extern void s3c_fb_set_output_path(int out); ++extern void s3c_fb_set_clkval(unsigned int clkval); ++extern void s3c_fb_enable_rgbport(unsigned int on_off); ++#else // peter for 2.6.24 kernel ++extern void s3cfb_start_lcd(void); ++extern void s3cfb_stop_lcd(void); ++extern void s3cfb_set_output_path(int out); ++extern void s3cfb_set_clock(unsigned int clkval); ++extern void s3cfb_enable_rgbport(unsigned int on_off); ++extern int v4l2_video_std_construct(struct v4l2_standard *vs, ++ int id, const char *name); ++extern int video_usercopy(struct inode *inode, struct file *file, ++ unsigned int cmd, unsigned long arg, ++ int (*func)(struct inode *inode, struct file *file, ++ unsigned int cmd, void *arg)); ++#endif ++ ++ ++#endif // __S3CTVENC_H_ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/tv/s3c-tvscaler.c linux-2.6.28.6/drivers/media/video/samsung/tv/s3c-tvscaler.c +--- linux-2.6.28/drivers/media/video/samsung/tv/s3c-tvscaler.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/tv/s3c-tvscaler.c 2009-10-23 22:44:15.000000000 +0200 +@@ -0,0 +1,791 @@ ++/* linux/drivers/video/samsung/tv/s3c-tvscaler.c ++ * ++ * Driver file for Samsung TV Controller ++ * ++ * Peter Oh, Copyright (c) 2009 Samsung Electronics ++ * http://www.samsungsemi.com/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* error codes */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "s3c-tvscaler.h" ++ ++#define PFX "s3c_tv_scaler" ++ ++#define SINGLE_BUF 1 // Single buffer mode ++ ++ ++static struct clk *h_clk; ++static struct clk *tvscaler_clock; ++static void __iomem *base; ++static int s3c_tvscaler_irq = NO_IRQ; ++static struct resource *s3c_tvscaler_mem; ++ ++ ++//static unsigned char *addr_start_y; ++//static unsigned char *addr_start_rgb; ++ ++static wait_queue_head_t waitq; ++ ++irqreturn_t s3c_tvscaler_isr(int irq, void *dev_id, ++ struct pt_regs *regs) ++{ ++ u32 mode; ++ mode = __raw_readl(base + S3C_MODE); ++ mode &= ~(1 << 6); /* Clear Source in POST Processor */ ++ __raw_writel(mode, base + S3C_MODE); ++ ++// wake_up_interruptible(&waitq); ++ return IRQ_HANDLED; ++} ++ ++#if 0 ++static buff_addr_t buf_addr = { NULL }; ++ ++ ++static u32 post_alloc_pre_buff(scaler_params_t *sp) ++{ ++ u32 size; ++ ++#ifdef USE_DEDICATED_MEM ++ ++ buf_addr.pre_phy_addr = PHYS_OFFSET + (SYSTEM_RAM - RESERVE_POST_MEM); ++ buf_addr.pre_virt_addr = ioremap_nocache(buf_addr.pre_phy_addr, PRE_BUFF_SIZE); ++ if( !buf_addr.pre_virt_addr ) { ++ printk(KERN_ERR "%s: Failed to allocate pre buffer \n",__FUNCTION__); ++ return -ENOMEM; ++ } ++ ++ sp->SrcFrmSt = buf_addr.pre_phy_addr; ++#else ++ size = sp->SrcWidth * sp->SrcHeight * 2; ++ addr_start_y = kmalloc(size, GFP_DMA); ++ if(addr_start_y != NULL) return -ENOMEM; ++#endif ++ return 0; ++} ++ ++static u32 post_alloc_post_buff(scaler_params_t *sp) ++{ ++ u32 size; ++ ++#ifdef USE_DEDICATED_MEM ++ ++ buf_addr.post_phy_addr = PHYS_OFFSET + (SYSTEM_RAM - RESERVE_POST_MEM + PRE_BUFF_SIZE); ++ buf_addr.post_virt_addr = ioremap_nocache(buf_addr.post_phy_addr, POST_BUFF_SIZE); ++ if( !buf_addr.post_virt_addr ) { ++ printk(KERN_ERR "%s: Failed to allocate post buffer \n",__FUNCTION__); ++ return -ENOMEM; ++ } ++ ++ sp->DstFrmSt = buf_addr.post_phy_addr; ++#else ++ size = sp->DstWidth * sp->DstHeight * 2; ++ addr_start_rgb = kmalloc(size, GFP_DMA); ++ if(addr_start_rgb != NULL) return -ENOMEM; ++#endif ++ return 0; ++} ++ ++static u32 post_free_all_buffer(void) ++{ ++#ifdef USE_DEDICATED_MEM ++ if( buf_addr.pre_virt_addr ) { ++ iounmap(buf_addr.pre_virt_addr); ++ } ++ if( buf_addr.post_virt_addr ) { ++ iounmap(buf_addr.post_virt_addr); ++ } ++#endif ++ return 0; ++} ++#endif ++ ++static void s3c_tvscaler_set_clk_src(scaler_clk_src_t clk_src) ++{ ++ u32 tmp, rate; ++ ++ tmp = __raw_readl(base + S3C_MODE); ++ ++ h_clk = clk_get(NULL, "hclk"); ++ ++ rate = clk_get_rate(h_clk); ++ ++ if(clk_src == HCLK) { ++ if(rate > 66000000) { ++ tmp &= ~(0x7f<<23); ++ tmp |= (1<<24); ++ tmp |= (1<<23); ++ } else { ++ tmp &=~ (0x7f<<23); ++ } ++ ++ } else if(clk_src == PLL_EXT) { ++ } else { ++ tmp &=~(0x7f<<23); ++ } ++ ++ tmp = (tmp &~ (0x3<<21)) | (clk_src<<21); ++ ++ __raw_writel(tmp, base + S3C_MODE); ++} ++ ++static void s3c_tvscaler_set_fmt(cspace_t src, cspace_t dst, s3c_scaler_path_t in, ++ s3c_scaler_path_t out, u32 *in_pixel_size, ++ u32 *out_pixel_size) ++{ ++ u32 tmp; ++ ++ tmp = __raw_readl(base + S3C_MODE); ++ tmp |= (0x1<<16); ++ tmp |= (0x2<<10); ++ ++ if(in == POST_DMA) { ++ ++ switch(src) { ++ case YC420: ++ tmp &=~((0x1<<3)|(0x1<<2)); ++ tmp |= (0x1<<8)|(0x1<<1); ++ *in_pixel_size = 1; ++ break; ++ case CRYCBY: ++ tmp &= ~((0x1<<15)|(0x1<<8)|(0x1<<3)|(0x1<<0)); ++ tmp |= (0x1<<2)|(0x1<<1); ++ *in_pixel_size = 2; ++ break; ++ case CBYCRY: ++ tmp &= ~((0x1<<8)|(0x1<<3)|(0x1<<0)); ++ tmp |= (0x1<<15)|(0x1<<2)|(0x1<<1); ++ *in_pixel_size = 2; ++ break; ++ case YCRYCB: ++ tmp &= ~((0x1<<15)|(0x1<<8)|(0x1<<3)); ++ tmp |= (0x1<<2)|(0x1<<1)|(0x1<<0); ++ *in_pixel_size = 2; ++ break; ++ case YCBYCR: ++ tmp &= ~((0x1<<8)|(0x1<<3)); ++ tmp |= (0x1<<15)|(0x1<<2)|(0x1<<1)|(0x1<<0); ++ *in_pixel_size = 2; ++ break; ++ case RGB24: ++ tmp &= ~(0x1<<8); ++ tmp |= (0x1<<3)|(0x1<<2)|(0x1<<1); ++ *in_pixel_size = 4; ++ break; ++ case RGB16: ++ tmp &= ~((0x1<<8)|(0x1<<1)); ++ tmp |= (0x1<<3)|(0x1<<2); ++ *in_pixel_size = 2; ++ break; ++ default: ++ break; ++ } ++ ++ } ++ else if(in == POST_FIFO) { ++ } ++ ++ if(out == POST_DMA) { ++ switch(dst) { ++ case YC420: ++ tmp &= ~(0x1<<18); ++ tmp |= (0x1<<17); ++ *out_pixel_size = 1; ++ break; ++ case CRYCBY: ++ tmp &= ~((0x1<<20)|(0x1<<19)|(0x1<<18)|(0x1<<17)); ++ *out_pixel_size = 2; ++ break; ++ case CBYCRY: ++ tmp &= ~((0x1<<19)|(0x1<<18)|(0x1<<17)); ++ tmp |= (0x1<<20); ++ *out_pixel_size = 2; ++ break; ++ case YCRYCB: ++ tmp &= ~((0x1<<20)|(0x1<<18)|(0x1<<17)); ++ tmp |= (0x1<<19); ++ *out_pixel_size = 2; ++ break; ++ case YCBYCR: ++ tmp &= ~((0x1<<18)|(0x1<<17)); ++ tmp |= (0x1<<20)|(0x1<<19); ++ *out_pixel_size = 2; ++ break; ++ case RGB24: ++ tmp |= (0x1<<18)|(0x1<<4); ++ *out_pixel_size = 4; ++ break; ++ case RGB16: ++ tmp &= ~(0x1<<4); ++ tmp |= (0x1<<18); ++ *out_pixel_size = 2; ++ break; ++ default: ++ break; ++ } ++ } ++ else if(out == POST_FIFO) { ++ if(dst == RGB24) { ++ tmp |= (0x1<<18)|(0x1<<13); ++ ++ } else if(dst == YCBYCR) { ++ tmp |= (0x1<<13); ++ tmp &= ~(0x1<<18)|(0x1<<17); ++ } else { ++ } ++ } ++ ++ __raw_writel(tmp, base + S3C_MODE); ++} ++ ++static void s3c_tvscaler_set_path(s3c_scaler_path_t in, s3c_scaler_path_t out) ++{ ++ u32 tmp; ++ ++ tmp = __raw_readl(base + S3C_MODE); ++ ++ tmp &=~(0x1<<12); // 0: progressive mode, 1: interlace mode ++ ++ if(in == POST_FIFO) { ++ tmp |= (0x1<<31); ++ } else if(in == POST_DMA) { ++ tmp &=~(0x1<<31); ++ } ++ ++ if(out == POST_FIFO) { ++ tmp |= (0x1<<13); ++ } else if(out == POST_DMA) { ++ tmp &=~(0x1<<13); ++ } ++ ++ __raw_writel(tmp, base + S3C_MODE); ++} ++ ++static void s3c_tvscaler_set_addr(scaler_params_t *sp, u32 in_pixel_size, u32 out_pixel_size) ++{ ++ u32 offset_y, offset_cb, offset_cr; ++ u32 src_start_y, src_start_cb, src_start_cr; ++ u32 src_end_y, src_end_cb, src_end_cr; ++ u32 start_pos_y, end_pos_y; ++ u32 start_pos_cb, end_pos_cb; ++ u32 start_pos_cr, end_pos_cr; ++ u32 start_pos_rgb, end_pos_rgb; ++ u32 dst_start_rgb, dst_end_rgb; ++ u32 src_frm_start_addr; ++ ++ u32 offset_rgb, out_offset_cb, out_offset_cr; ++ u32 out_start_pos_cb, out_start_pos_cr; ++ u32 out_end_pos_cb, out_end_pos_cr; ++ u32 out_src_start_cb, out_src_start_cr; ++ u32 out_src_end_cb, out_src_end_cr; ++ ++ if(sp->InPath == POST_DMA) { ++ offset_y = (sp->SrcFullWidth - sp->SrcWidth) * in_pixel_size; ++ start_pos_y = (sp->SrcFullWidth*sp->SrcStartY+sp->SrcStartX)*in_pixel_size; ++ end_pos_y = sp->SrcWidth*sp->SrcHeight*in_pixel_size + offset_y*(sp->SrcHeight-1); ++ src_frm_start_addr = sp->SrcFrmSt; ++ src_start_y = sp->SrcFrmSt + start_pos_y; ++ src_end_y = src_start_y + end_pos_y; ++ ++ __raw_writel(src_start_y, base + S3C_ADDRSTART_Y); ++ __raw_writel(offset_y, base + S3C_OFFSET_Y); ++ __raw_writel(src_end_y, base + S3C_ADDREND_Y); ++ ++ if(sp->SrcCSpace == YC420) { ++ offset_cb = offset_cr = ((sp->SrcFullWidth - sp->SrcWidth) / 2) * in_pixel_size; ++ start_pos_cb = sp->SrcFullWidth * sp->SrcFullHeight * 1 \ ++ + (sp->SrcFullWidth * sp->SrcStartY / 2 + sp->SrcStartX) /2 * 1; ++ ++ end_pos_cb = sp->SrcWidth/2*sp->SrcHeight/2*in_pixel_size \ ++ + (sp->SrcHeight/2 -1)*offset_cb; ++ start_pos_cr = sp->SrcFullWidth * sp->SrcFullHeight *1 \ ++ + sp->SrcFullWidth*sp->SrcFullHeight/4 *1 \ ++ + (sp->SrcFullWidth*sp->SrcStartY/2 + sp->SrcStartX)/2*1; ++ end_pos_cr = sp->SrcWidth/2*sp->SrcHeight/2*in_pixel_size \ ++ + (sp->SrcHeight/2-1)*offset_cr; ++ ++ src_start_cb = sp->SrcFrmSt + start_pos_cb; ++ src_end_cb = src_start_cb + end_pos_cb; ++ ++ src_start_cr = sp->SrcFrmSt + start_pos_cr; ++ src_end_cr = src_start_cr + end_pos_cr; ++ ++ __raw_writel(src_start_cb, base + S3C_ADDRSTART_CB); ++ __raw_writel(offset_cr, base + S3C_OFFSET_CB); ++ __raw_writel(src_end_cb, base + S3C_ADDREND_CB); ++ __raw_writel(src_start_cr, base + S3C_ADDRSTART_CR); ++ __raw_writel(offset_cb, base + S3C_OFFSET_CR); ++ __raw_writel(src_end_cr, base + S3C_ADDREND_CR); ++ } ++ } ++ if(sp->OutPath == POST_DMA) { ++ offset_rgb = (sp->DstFullWidth - sp->DstWidth)*out_pixel_size; ++ start_pos_rgb = (sp->DstFullWidth*sp->DstStartY + sp->DstStartX)*out_pixel_size; ++ end_pos_rgb = sp->DstWidth*sp->DstHeight*out_pixel_size + offset_rgb*(sp->DstHeight - 1); ++ dst_start_rgb = sp->DstFrmSt + start_pos_rgb; ++ dst_end_rgb = dst_start_rgb + end_pos_rgb; ++ ++ __raw_writel(dst_start_rgb, base + S3C_ADDRSTART_RGB); ++ __raw_writel(offset_rgb, base + S3C_OFFSET_RGB); ++ __raw_writel(dst_end_rgb, base + S3C_ADDREND_RGB); ++ ++ if(sp->DstCSpace == YC420) { ++ out_offset_cb = out_offset_cr = ((sp->DstFullWidth - sp->DstWidth)/2)*out_pixel_size; ++ out_start_pos_cb = sp->DstFullWidth*sp->DstFullHeight*1 \ ++ + (sp->DstFullWidth*sp->DstStartY/2 + sp->DstStartX)/2*1; ++ out_end_pos_cb = sp->DstWidth/2*sp->DstHeight/2*out_pixel_size \ ++ + (sp->DstHeight/2 -1)*out_offset_cr; ++ ++ out_start_pos_cr = sp->DstFullWidth*sp->DstFullHeight*1 \ ++ + (sp->DstFullWidth*sp->DstFullHeight/4)*1 \ ++ + (sp->DstFullWidth*sp->DstStartY/2 +sp->DstStartX)/2*1; ++ out_end_pos_cr = sp->DstWidth/2*sp->DstHeight/2*out_pixel_size \ ++ + (sp->DstHeight/2 -1)*out_offset_cb; ++ ++ out_src_start_cb = sp->DstFrmSt + out_start_pos_cb; ++ out_src_end_cb = out_src_start_cb + out_end_pos_cb; ++ out_src_start_cr = sp->DstFrmSt + out_start_pos_cr; ++ out_src_end_cr = out_src_start_cr + out_end_pos_cr; ++ ++ __raw_writel(out_src_start_cb, base + S3C_ADDRSTART_OCB); ++ __raw_writel(out_offset_cb, base + S3C_OFFSET_OCB); ++ __raw_writel(out_src_end_cb, base + S3C_ADDREND_OCB); ++ __raw_writel(out_src_start_cr, base + S3C_ADDRSTART_OCR); ++ __raw_writel(out_offset_cr, base + S3C_OFFSET_OCR); ++ __raw_writel(out_src_end_cr, base + S3C_ADDREND_OCR); ++ ++ } ++ } ++ ++ ++} ++ ++#if 0 ++static void s3c_tvscaler_set_fifo_in(s3c_scaler_path_t in_path) ++{ ++ u32 tmp; ++ ++ tmp = __raw_readl(base + S3C_MODE); ++ ++ if(in_path == POST_FIFO) tmp |= (0x1<<31); ++ else tmp &=~(0x1<<31); ++ ++ __raw_writel(tmp, base + S3C_MODE); ++ ++} ++#endif ++ ++void s3c_tvscaler_set_interlace(u32 on_off) ++{ ++ u32 tmp; ++ ++ tmp = __raw_readl(base + S3C_MODE); ++ ++ if(on_off == 1) tmp |=(1<<12); ++ else tmp &=~(1<<12); ++ ++ __raw_writel(tmp, base + S3C_MODE); ++} ++EXPORT_SYMBOL(s3c_tvscaler_set_interlace); ++ ++static void s3c_tvscaler_set_size(scaler_params_t *sp) ++{ ++ u32 pre_h_ratio, pre_v_ratio, h_shift, v_shift, sh_factor; ++ u32 pre_dst_width, pre_dst_height, dx, dy; ++ ++ if (sp->SrcWidth >= (sp->DstWidth<<6)) { ++ printk("Out of PreScalar range !!!\n"); ++ return; ++ } ++ if(sp->SrcWidth >= (sp->DstWidth<<5)) { ++ pre_h_ratio = 32; ++ h_shift = 5; ++ } else if(sp->SrcWidth >= (sp->DstWidth<<4)) { ++ pre_h_ratio = 16; ++ h_shift = 4; ++ } else if(sp->SrcWidth >= (sp->DstWidth<<3)) { ++ pre_h_ratio = 8; ++ h_shift = 3; ++ } else if(sp->SrcWidth >= (sp->DstWidth<<2)) { ++ pre_h_ratio = 4; ++ h_shift = 2; ++ } else if(sp->SrcWidth >= (sp->DstWidth<<1)) { ++ pre_h_ratio = 2; ++ h_shift = 1; ++ } else { ++ pre_h_ratio = 1; ++ h_shift = 0; ++ } ++ ++ pre_dst_width = sp->SrcWidth / pre_h_ratio; ++ dx = (sp->SrcWidth<<8) / (sp->DstWidth<SrcHeight >= (sp->DstHeight<<6)) { ++ printk("Out of PreScalar range !!!\n"); ++ return; ++ } ++ if(sp->SrcHeight>= (sp->DstHeight<<5)) { ++ pre_v_ratio = 32; ++ v_shift = 5; ++ } else if(sp->SrcHeight >= (sp->DstHeight<<4)) { ++ pre_v_ratio = 16; ++ v_shift = 4; ++ } else if(sp->SrcHeight >= (sp->DstHeight<<3)) { ++ pre_v_ratio = 8; ++ v_shift = 3; ++ } else if(sp->SrcHeight >= (sp->DstHeight<<2)) { ++ pre_v_ratio = 4; ++ v_shift = 2; ++ } else if(sp->SrcHeight >= (sp->DstHeight<<1)) { ++ pre_v_ratio = 2; ++ v_shift = 1; ++ } else { ++ pre_v_ratio = 1; ++ v_shift = 0; ++ } ++ ++ pre_dst_height = sp->SrcHeight / pre_v_ratio; ++ dy = (sp->SrcHeight<<8) / (sp->DstHeight<SrcHeight<<12)|(sp->SrcWidth), base + S3C_SRCIMGSIZE); ++ __raw_writel((sp->DstHeight<<12)|(sp->DstWidth), base + S3C_DSTIMGSIZE); ++ ++} ++ ++ ++static void s3c_tvscaler_set_auto_load(scaler_params_t *sp) ++{ ++ u32 tmp; ++ ++ tmp = __raw_readl(base + S3C_MODE); ++ ++ if(sp->Mode == FREE_RUN) { ++ tmp |= (1<<14); ++ } else if(sp->Mode == ONE_SHOT) { ++ tmp &=~(1<<14); ++ } ++ ++ __raw_writel(tmp, base + S3C_MODE); ++ ++} ++ ++void s3c_tvscaler_set_base_addr(void __iomem * base_addr) ++{ ++ base = base_addr; ++} ++EXPORT_SYMBOL(s3c_tvscaler_set_base_addr); ++ ++void s3c_tvscaler_free_base_addr(void) ++{ ++ base = NULL; ++} ++EXPORT_SYMBOL(s3c_tvscaler_free_base_addr); ++ ++void s3c_tvscaler_int_enable(u32 int_type) ++{ ++ u32 tmp; ++ ++ tmp = __raw_readl(base + S3C_MODE); ++ ++ if(int_type == 0) { //Edge triggering ++ tmp &= ~(S3C_MODE_IRQ_LEVEL); ++ } else if(int_type == 1) { //level triggering ++ tmp |= S3C_MODE_IRQ_LEVEL; ++ } ++ ++ tmp |= S3C_MODE_POST_INT_ENABLE; ++ ++ __raw_writel(tmp, base + S3C_MODE); ++} ++EXPORT_SYMBOL(s3c_tvscaler_int_enable); ++ ++void s3c_tvscaler_int_disable(void) ++{ ++ u32 tmp; ++ ++ tmp = __raw_readl(base + S3C_MODE); ++ ++ tmp &=~ (S3C_MODE_POST_INT_ENABLE); ++ ++ __raw_writel(tmp, base + S3C_MODE); ++ ++} ++EXPORT_SYMBOL(s3c_tvscaler_int_disable); ++ ++ ++void s3c_tvscaler_start(void) ++{ ++ __raw_writel(S3C_POSTENVID_ENABLE, base + S3C_POSTENVID); ++ ++} ++EXPORT_SYMBOL(s3c_tvscaler_start); ++ ++void s3c_tvscaler_stop_freerun(void) ++{ ++ u32 tmp; ++ ++ tmp = __raw_readl(base + S3C_MODE); ++ ++ tmp &=~(1<<14); ++ ++ __raw_writel(tmp, base + S3C_MODE); ++} ++EXPORT_SYMBOL(s3c_tvscaler_stop_freerun); ++ ++ ++void s3c_tvscaler_config(scaler_params_t *sp) ++{ ++ u32 tmp = 0; ++ u32 in_pixel_size = 0; ++ u32 out_pixel_size = 0; ++ u32 loop = 0; ++ ++ tmp = __raw_readl(base + S3C_POSTENVID); ++ tmp &= ~S3C_POSTENVID_ENABLE; ++ __raw_writel(tmp, base + S3C_POSTENVID); ++#ifdef SINGLE_BUF ++ tmp = S3C_MODE2_ADDR_CHANGE_DISABLE |S3C_MODE2_CHANGE_AT_FRAME_END |S3C_MODE2_SOFTWARE_TRIGGER; ++#else ++ tmp = S3C_MODE2_ADDR_CHANGE_ENABLE |S3C_MODE2_CHANGE_AT_FRAME_END |S3C_MODE2_SOFTWARE_TRIGGER; ++#endif ++ __raw_writel(tmp, base + S3C_MODE2); ++ ++// peter mod. start ++ sp->DstStartX = sp->DstStartY = 0; ++ sp->DstWidth = sp->DstFullWidth; ++ sp->DstHeight = sp->DstFullHeight; ++// peter mod. end ++ ++ sp->DstFrmSt = ( POST_BUFF_BASE_ADDR + PRE_BUFF_SIZE ); ++ printk("\n---peter s3c_tvscaler_config : SrcFrmSt = 0x%08x\n", sp->SrcFrmSt); ++ printk("---peter s3c_tvscaler_config : DstFrmSt = 0x%08x\n", sp->DstFrmSt); ++ ++ s3c_tvscaler_set_clk_src(HCLK); ++ ++ s3c_tvscaler_set_path(sp->InPath, sp->OutPath); ++ ++ s3c_tvscaler_set_fmt(sp->SrcCSpace, sp->DstCSpace, sp->InPath, ++ sp->OutPath, &in_pixel_size, &out_pixel_size); ++ ++ s3c_tvscaler_set_size(sp); ++ ++ s3c_tvscaler_set_addr(sp, in_pixel_size, out_pixel_size); ++ ++ s3c_tvscaler_set_auto_load(sp); ++ ++} ++EXPORT_SYMBOL(s3c_tvscaler_config); ++ ++void s3c_tvscaler_set_param(scaler_params_t *sp) ++{ ++#if 0 ++ param.SrcFullWidth = sp->SrcFullWidth; ++ param.SrcFullHeight = sp->SrcFullHeight; ++ param.SrcStartX = sp->SrcStartX; ++ param.SrcStartY = sp->SrcStartY; ++ param.SrcWidth = sp->SrcWidth; ++ param.SrcHeight = sp->SrcHeight; ++ param.SrcFrmSt = sp->SrcFrmSt; ++ param.SrcCSpace = sp->SrcCSpace; ++ param.DstFullWidth = sp->DstFullWidth; ++ param.DstFullHeight = sp->DstFullHeight; ++ param.DstStartX = sp->DstStartX; ++ param.DstStartY = sp->DstStartY; ++ param.DstWidth = sp->DstWidth; ++ param.DstHeight = sp->DstHeight; ++ param.DstFrmSt = sp->DstFrmSt; ++ param.DstCSpace = sp->DstCSpace; ++ param.SrcFrmBufNum = sp->SrcFrmBufNum; ++ param.DstFrmSt = sp->DstFrmSt; ++ param.Mode = sp->Mode; ++ param.InPath = sp->InPath; ++ param.OutPath = sp->OutPath; ++#endif ++} ++EXPORT_SYMBOL(s3c_tvscaler_set_param); ++ ++void s3c_tvscaler_init(void) ++{ ++ ++ int tmp; ++ ++ // Use DOUTmpll source clock as a scaler clock ++ tmp = __raw_readl(S3C_CLK_SRC); ++ ++ tmp &=~(0x3<<28); ++ tmp |= (0x1<<28); ++ __raw_writel(tmp, S3C_CLK_SRC); ++ ++ printk(" %s \n", __FUNCTION__); ++ ++} ++EXPORT_SYMBOL(s3c_tvscaler_init); ++ ++ ++static int s3c_tvscaler_probe(struct platform_device *pdev) ++{ ++ ++ struct resource *res; ++ ++ int ret; ++ ++ /* find the IRQs */ ++ s3c_tvscaler_irq = platform_get_irq(pdev, 0); ++ if(s3c_tvscaler_irq <= 0) { ++ printk(KERN_ERR PFX "failed to get irq resouce\n"); ++ return -ENOENT; ++ } ++ ++ /* get the memory region for the tv scaler driver */ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if(res == NULL) { ++ printk(KERN_ERR PFX "failed to get memory region resouce\n"); ++ return -ENOENT; ++ } ++ ++ s3c_tvscaler_mem = request_mem_region(res->start, res->end-res->start+1, pdev->name); ++ if(s3c_tvscaler_mem == NULL) { ++ printk(KERN_ERR PFX "failed to reserve memory region\n"); ++ return -ENOENT; ++ } ++ ++ base = ioremap(s3c_tvscaler_mem->start, s3c_tvscaler_mem->end - res->start + 1); ++ if(s3c_tvscaler_mem == NULL) { ++ printk(KERN_ERR PFX "failed ioremap\n"); ++ return -ENOENT; ++ } ++ ++ tvscaler_clock = clk_get(&pdev->dev, "tv_encoder"); ++ if(tvscaler_clock == NULL) { ++ printk(KERN_ERR PFX "failed to find tvscaler clock source\n"); ++ return -ENOENT; ++ } ++ ++ clk_enable(tvscaler_clock); ++ ++ h_clk = clk_get(&pdev->dev, "hclk"); ++ if(h_clk == NULL) { ++ printk(KERN_ERR PFX "failed to find h_clk clock source\n"); ++ return -ENOENT; ++ } ++ ++ init_waitqueue_head(&waitq); ++ ++ ret = request_irq(s3c_tvscaler_irq, s3c_tvscaler_isr, IRQF_DISABLED, ++ "TV_SCALER", NULL); ++ if (ret) { ++ printk("request_irq(TV_SCALER) failed.\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int s3c_tvscaler_remove(struct platform_device *dev) ++{ ++ printk(KERN_INFO "s3c_tvscaler_remove called !\n"); ++ clk_disable(tvscaler_clock); ++ free_irq(s3c_tvscaler_irq, NULL); ++ if (s3c_tvscaler_mem != NULL) { ++ pr_debug("s3-tvscaler: releasing s3c_tvscaler_mem\n"); ++ iounmap(base); ++ release_resource(s3c_tvscaler_mem); ++ kfree(s3c_tvscaler_mem); ++ } ++ ++ return 0; ++} ++ ++static int s3c_tvscaler_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ clk_disable(tvscaler_clock); ++ return 0; ++} ++ ++static int s3c_tvscaler_resume(struct platform_device *pdev) ++{ ++ clk_enable(tvscaler_clock); ++ return 0; ++} ++ ++static struct platform_driver s3c_tvscaler_driver = { ++ .probe = s3c_tvscaler_probe, ++ .remove = s3c_tvscaler_remove, ++ .suspend = s3c_tvscaler_suspend, ++ .resume = s3c_tvscaler_resume, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "s3c-tvscaler", ++ }, ++}; ++ ++static char banner[] __initdata = KERN_INFO "S3C6410 TV scaler Driver, (c) 2008 Samsung Electronics\n"; ++ ++ ++int __init s3c_tvscaler_pre_init(void) ++{ ++ ++ printk(banner); ++ ++ if(platform_driver_register(&s3c_tvscaler_driver) != 0) ++ { ++ printk("platform device register Failed \n"); ++ return -1; ++ } ++ ++ printk(" S3C6410 TV scaler Driver init OK. \n"); ++ ++ return 0; ++} ++ ++void s3c_tvscaler_exit(void) ++{ ++ platform_driver_unregister(&s3c_tvscaler_driver); ++ printk("S3C: tvscaler module exit\n"); ++} ++ ++module_init(s3c_tvscaler_pre_init); ++module_exit(s3c_tvscaler_exit); ++ ++ ++MODULE_AUTHOR("Peter, Oh"); ++MODULE_DESCRIPTION("S3C TV Controller Device Driver"); ++MODULE_LICENSE("GPL"); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/samsung/tv/s3c-tvscaler.h linux-2.6.28.6/drivers/media/video/samsung/tv/s3c-tvscaler.h +--- linux-2.6.28/drivers/media/video/samsung/tv/s3c-tvscaler.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/samsung/tv/s3c-tvscaler.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,95 @@ ++#ifndef __S3CTVSCALER_H_ ++#define __S3CTVSCALER_H_ ++ ++#include "plat/media.h" ++ ++#define TVSCALER_IOCTL_MAGIC 'S' ++ ++#define PPROC_SET_PARAMS _IO(TVSCALER_IOCTL_MAGIC, 0) ++#define PPROC_START _IO(TVSCALER_IOCTL_MAGIC, 1) ++#define PPROC_STOP _IO(TVSCALER_IOCTL_MAGIC, 2) ++#define PPROC_INTERLACE_MODE _IO(TVSCALER_IOCTL_MAGIC, 3) ++#define PPROC_PROGRESSIVE_MODE _IO(TVSCALER_IOCTL_MAGIC, 4) ++ ++ ++#define QVGA_XSIZE 320 ++#define QVGA_YSIZE 240 ++ ++#define LCD_XSIZE 320 ++#define LCD_YSIZE 240 ++ ++#define SCALER_MINOR 251 // Just some number ++ ++//#define SYSTEM_RAM 0x08000000 // 128mb ++#define SYSTEM_RAM 0x07800000 // 120mb ++#define RESERVE_POST_MEM 8*1024*1024 // 8mb ++#define PRE_BUFF_SIZE 4*1024*1024 //4 // 4mb ++#define POST_BUFF_SIZE ( RESERVE_POST_MEM - PRE_BUFF_SIZE ) ++ ++typedef unsigned int UINT32; ++ ++#define post_buff_base_addr 0x55B00000 ++#define POST_BUFF_BASE_ADDR (UINT32)s3c_get_media_memory(S3C_MDEV_TV) ++ ++#define USE_DEDICATED_MEM 1 ++ ++typedef enum { ++ INTERLACE_MODE, ++ PROGRESSIVE_MODE ++} s3c_scaler_scan_mode_t; ++ ++typedef enum { ++ POST_DMA, POST_FIFO ++} s3c_scaler_path_t; ++ ++typedef enum { ++ ONE_SHOT, FREE_RUN ++} s3c_scaler_run_mode_t; ++ ++typedef enum { ++ PAL1, PAL2, PAL4, PAL8, ++ RGB8, ARGB8, RGB16, ARGB16, RGB18, RGB24, RGB30, ARGB24, ++ YC420, YC422, // Non-interleave ++ CRYCBY, CBYCRY, YCRYCB, YCBYCR, YUV444 // Interleave ++} cspace_t; ++ ++typedef enum ++{ ++ HCLK = 0, PLL_EXT = 1, EXT_27MHZ = 3 ++} scaler_clk_src_t; ++ ++typedef struct{ ++ unsigned int SrcFullWidth; // Source Image Full Width(Virtual screen size) ++ unsigned int SrcFullHeight; // Source Image Full Height(Virtual screen size) ++ unsigned int SrcStartX; // Source Image Start width offset ++ unsigned int SrcStartY; // Source Image Start height offset ++ unsigned int SrcWidth; // Source Image Width ++ unsigned int SrcHeight; // Source Image Height ++ unsigned int SrcFrmSt; // Base Address of the Source Image : Physical Address ++ cspace_t SrcCSpace; // Color Space ot the Source Image ++ ++ unsigned int DstFullWidth; // Source Image Full Width(Virtual screen size) ++ unsigned int DstFullHeight; // Source Image Full Height(Virtual screen size) ++ unsigned int DstStartX; // Source Image Start width offset ++ unsigned int DstStartY; // Source Image Start height offset ++ unsigned int DstWidth; // Source Image Width ++ unsigned int DstHeight; // Source Image Height ++ unsigned int DstFrmSt; // Base Address of the Source Image : Physical Address ++ cspace_t DstCSpace; // Color Space ot the Source Image ++ ++ unsigned int SrcFrmBufNum; // Frame buffer number ++ s3c_scaler_run_mode_t Mode; // POST running mode(PER_FRAME or FREE_RUN) ++ s3c_scaler_path_t InPath; // Data path of the source image ++ s3c_scaler_path_t OutPath; // Data path of the desitination image ++ ++}scaler_params_t; ++ ++typedef struct{ ++ unsigned int pre_phy_addr; ++ unsigned char *pre_virt_addr; ++ ++ unsigned int post_phy_addr; ++ unsigned char *post_virt_addr; ++} buff_addr_t; ++ ++#endif //__S3CTVSCALER_H_ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/v4l2-dev.c linux-2.6.28.6/drivers/media/video/v4l2-dev.c +--- linux-2.6.28/drivers/media/video/v4l2-dev.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/v4l2-dev.c 2009-04-30 09:36:38.000000000 +0200 +@@ -34,6 +34,8 @@ + #define VIDEO_NUM_DEVICES 256 + #define VIDEO_NAME "video4linux" + ++/*#define CONFIG_VIDEO_FIXED_MINOR_RANGES */ ++ + /* + * sysfs stuff + */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/media/video/v4l2-ioctl.c linux-2.6.28.6/drivers/media/video/v4l2-ioctl.c +--- linux-2.6.28/drivers/media/video/v4l2-ioctl.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/media/video/v4l2-ioctl.c 2009-10-23 16:36:42.000000000 +0200 +@@ -1012,6 +1012,7 @@ + if (!ops->vidioc_overlay) + break; + dbgarg(cmd, "value=%d\n", *i); ++ //printk("[V4L2]VIDIOC_OVERLAY...\N"); + ret = ops->vidioc_overlay(file, fh, *i); + break; + } +@@ -1057,8 +1058,12 @@ + enum v4l2_buf_type i = *(int *)arg; + + if (!ops->vidioc_streamoff) ++ { ++ printk("[V4L2]break\n"); + break; ++ } + dbgarg(cmd, "type=%s\n", prt_names(i, v4l2_type_names)); ++ + ret = ops->vidioc_streamoff(file, fh, i); + break; + } +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/mmc/core/core.c linux-2.6.28.6/drivers/mmc/core/core.c +--- linux-2.6.28/drivers/mmc/core/core.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/mmc/core/core.c 2009-04-30 09:36:38.000000000 +0200 +@@ -726,6 +726,9 @@ + void mmc_start_host(struct mmc_host *host) + { + mmc_power_off(host); ++ if (host->caps & MMC_CAP_BOOT_ONTHEFLY) ++ mmc_rescan(&host->detect.work); ++ else + mmc_detect_change(host, 0); + } + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/mmc/core/mmc.c linux-2.6.28.6/drivers/mmc/core/mmc.c +--- linux-2.6.28/drivers/mmc/core/mmc.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/mmc/core/mmc.c 2009-04-30 09:36:38.000000000 +0200 +@@ -208,7 +208,7 @@ + } + + ext_csd_struct = ext_csd[EXT_CSD_REV]; +- if (ext_csd_struct > 2) { ++ if (ext_csd_struct > 3) { + printk(KERN_ERR "%s: unrecognised EXT_CSD structure " + "version %d\n", mmc_hostname(card->host), + ext_csd_struct); +@@ -434,13 +434,24 @@ + * Activate wide bus (if supported). + */ + if ((card->csd.mmca_vsn >= CSD_SPEC_VER_4) && +- (host->caps & MMC_CAP_4_BIT_DATA)) { ++ (host->caps & (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA))) { ++ unsigned ext_csd_bit, bus_width; ++ ++ if (host->caps & MMC_CAP_8_BIT_DATA) { ++ ext_csd_bit = EXT_CSD_BUS_WIDTH_8; ++ bus_width = MMC_BUS_WIDTH_8; ++ } else { ++ ext_csd_bit = EXT_CSD_BUS_WIDTH_4; ++ bus_width = MMC_BUS_WIDTH_4; ++ } ++ + err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, +- EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_4); ++ EXT_CSD_BUS_WIDTH, ext_csd_bit); ++ + if (err) + goto free_card; + +- mmc_set_bus_width(card->host, MMC_BUS_WIDTH_4); ++ mmc_set_bus_width(card->host, bus_width); + } + + if (!oldcard) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/mmc/host/Kconfig linux-2.6.28.6/drivers/mmc/host/Kconfig +--- linux-2.6.28/drivers/mmc/host/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/mmc/host/Kconfig 2009-04-30 09:36:38.000000000 +0200 +@@ -48,6 +48,18 @@ + + If unsure, say N. + ++config MMC_SDHCI_S3C ++ tristate "SDHCI support on Samsung S3C SoC" ++ depends on MMC_SDHCI && (PLAT_S3C24XX || PLAT_S3C64XX || PLAT_S5PC1XX || PLAT_S5P64XX ) ++ help ++ This selects the Secure Digital Host Controller Interface (SDHCI) ++ often referrered to as the HSMMC block in some of the Samsung S3C ++ range of SoC. ++ ++ If you have a controller with this interface, say Y or M here. ++ ++ If unsure, say N. ++ + config MMC_RICOH_MMC + tristate "Ricoh MMC Controller Disabler (EXPERIMENTAL)" + depends on MMC_SDHCI_PCI +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/mmc/host/Makefile linux-2.6.28.6/drivers/mmc/host/Makefile +--- linux-2.6.28/drivers/mmc/host/Makefile 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/mmc/host/Makefile 2009-04-30 09:36:38.000000000 +0200 +@@ -11,6 +11,7 @@ + obj-$(CONFIG_MMC_IMX) += imxmmc.o + obj-$(CONFIG_MMC_SDHCI) += sdhci.o + obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o ++obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o + obj-$(CONFIG_MMC_RICOH_MMC) += ricoh_mmc.o + obj-$(CONFIG_MMC_WBSD) += wbsd.o + obj-$(CONFIG_MMC_AU1X) += au1xmmc.o +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/mmc/host/s3c-hsmmc.c linux-2.6.28.6/drivers/mmc/host/s3c-hsmmc.c +--- linux-2.6.28/drivers/mmc/host/s3c-hsmmc.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/mmc/host/s3c-hsmmc.c 2010-04-21 06:36:32.000000000 +0200 +@@ -0,0 +1,1177 @@ ++/* ++ * linux/drivers/mmc/s3c-hsmmc.c - Samsung S5PC1XX HS-MMC driver ++ * ++ * $Id: s3c-hsmmc.c,v 1.54 2008/08/26 01:18:29 ihlee215 Exp $ ++ * ++ * Copyright (C) 2006 Samsung Electronics, All Rights Reserved. ++ * by Suh, Seung-Chull ++ * ++ * This driver is made for High Speed MMC interface. This interface ++ * is adopted and implemented since s3c2443 was made. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * Modified by Ryu,Euiyoul ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#if defined(CONFIG_CPU_S3C6410) ++#include ++#include ++static int card_detect = 0; ++#endif ++ ++#ifdef CONFIG_S3CMMC_DEBUG ++#define DBG(x...) printk(PFX x) ++#else ++#define DBG(x...) do { } while (0) ++#endif ++ ++#include "s3c-hsmmc.h" ++ ++#define DRIVER_NAME "s3c-hsmmc" ++#define PFX DRIVER_NAME ": " ++ ++#define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1) ++ ++#if defined(CONFIG_PM) ++struct s3c_hsmmc_host *global_host[3]; ++#endif ++ ++/*****************************************************************************\ ++ * * ++ * Low level functions * ++ * * ++\*****************************************************************************/ ++ ++static struct s3c_hsmmc_cfg s3c_hsmmc_platform = { ++ .hwport = 0, ++ .enabled = 0, ++ .host_caps = MMC_CAP_4_BIT_DATA, ++ .base = NULL, ++ .highspeed = 0, ++ ++ /* ctrl for mmc */ ++ .fd_ctrl[0] = { ++ .ctrl2 = 0xC0004100, /* ctrl2 for mmc */ ++ .ctrl3[0] = 0x80808080, /* ctrl3 for low speed */ ++ .ctrl3[1] = 0x00000080, /* ctrl3 for high speed */ ++ .ctrl4 = 0, ++ }, ++ ++ /* ctrl for sd */ ++ .fd_ctrl[1] = { ++ .ctrl2 = 0xC0000100, /* ctrl2 for sd */ ++ .ctrl3[0] = 0, /* ctrl3 for low speed */ ++ .ctrl3[1] = 0, /* ctrl3 for high speed */ ++ .ctrl4 = 0, ++ }, ++}; ++ ++/* s3c_hsmmc_get_platdata ++ * ++ * get the platform data associated with the given device, or return ++ * the default if there is none ++ */ ++ ++static struct s3c_hsmmc_cfg *s3c_hsmmc_get_platdata (struct device *dev) ++{ ++ if (dev->platform_data != NULL) ++ return (struct s3c_hsmmc_cfg *)dev->platform_data; ++ ++ return &s3c_hsmmc_platform; ++} ++ ++static void s3c_hsmmc_reset (struct s3c_hsmmc_host *host, u8 mask) ++{ ++ unsigned long timeout; ++ ++ s3c_hsmmc_writeb(mask, S3C_HSMMC_SWRST); ++ ++ if (mask & S3C_HSMMC_RESET_ALL) ++ host->clock = (uint)-1; ++ ++ /* Wait max 100 ms */ ++ timeout = 100; ++ ++ /* hw clears the bit when it's done */ ++ while (s3c_hsmmc_readb(S3C_HSMMC_SWRST) & mask) { ++ if (timeout == 0) { ++ printk("%s: Reset 0x%x never completed. \n", ++ mmc_hostname(host->mmc), (int)mask); ++ return; ++ } ++ timeout--; ++ mdelay(1); ++ } ++ ++} ++ ++static void s3c_hsmmc_ios_init (struct s3c_hsmmc_host *host) ++{ ++ u32 intmask; ++ ++ s3c_hsmmc_reset(host, S3C_HSMMC_RESET_ALL); ++ ++ intmask = S3C_HSMMC_INT_BUS_POWER | S3C_HSMMC_INT_DATA_END_BIT | ++ S3C_HSMMC_INT_DATA_CRC | S3C_HSMMC_INT_DATA_TIMEOUT | S3C_HSMMC_INT_INDEX | ++ S3C_HSMMC_INT_END_BIT | S3C_HSMMC_INT_CRC | S3C_HSMMC_INT_TIMEOUT | ++ S3C_HSMMC_INT_CARD_REMOVE | S3C_HSMMC_INT_CARD_INSERT | ++ S3C_HSMMC_INT_DATA_AVAIL | S3C_HSMMC_INT_SPACE_AVAIL | ++ S3C_HSMMC_INT_DATA_END | S3C_HSMMC_INT_RESPONSE; ++ ++#ifdef CONFIG_HSMMC_SCATTERGATHER ++ intmask |= S3C_HSMMC_INT_DMA_END; ++#endif ++ s3c_hsmmc_writel(intmask, S3C_HSMMC_NORINTSTSEN); ++ s3c_hsmmc_writel(intmask, S3C_HSMMC_NORINTSIGEN); ++} ++ ++/*****************************************************************************\ ++ * * ++ * Tasklets * ++ * * ++\*****************************************************************************/ ++ ++static void s3c_hsmmc_tasklet_card (ulong param) ++{ ++ struct s3c_hsmmc_host *host; ++ unsigned long iflags; ++ ++ host = (struct s3c_hsmmc_host*)param; ++ spin_lock_irqsave(&host->lock, iflags); ++ ++ if (!(s3c_hsmmc_readl(S3C_HSMMC_PRNSTS) & S3C_HSMMC_CARD_PRESENT)) { ++ if (host->mrq) { ++ printk(KERN_ERR "%s: Card removed during transfer!\n", ++ mmc_hostname(host->mmc)); ++ printk(KERN_ERR "%s: Resetting controller.\n", ++ mmc_hostname(host->mmc)); ++ ++ s3c_hsmmc_reset(host, S3C_HSMMC_RESET_CMD); ++ s3c_hsmmc_reset(host, S3C_HSMMC_RESET_DATA); ++ ++ host->mrq->cmd->error = -ENOMEDIUM; ++ tasklet_schedule(&host->finish_tasklet); ++ } ++ } ++ ++ spin_unlock_irqrestore(&host->lock, iflags); ++ ++ mmc_detect_change(host->mmc, msecs_to_jiffies(500)); ++} ++ ++/*****************************************************************************\ ++ * * ++ * Core functions * ++ * * ++\*****************************************************************************/ ++ ++#ifdef CONFIG_HSMMC_SCATTERGATHER ++static inline uint s3c_hsmmc_build_dma_table (struct s3c_hsmmc_host *host, ++ struct mmc_data *data) ++{ ++ uint i; ++ struct scatterlist * sg = data->sg; ++ ++ /* build dma table except the last one */ ++ for (i=0; i<(host->sg_len-1); i++) { ++ host->sdma_descr_tbl[i].dma_address = sg[i].dma_address; ++ host->sdma_descr_tbl[i].length_attr = (sg[i].length << 16) | (S3C_HSMMC_ADMA_ATTR_ACT_TRAN) | ++ (S3C_HSMMC_ADMA_ATTR_VALID); ++ ++ DBG(" ADMA2 descr table[%d] - addr: %08x, size+attr: %08x\n", i, host->sdma_descr_tbl[i].dma_address, ++ host->sdma_descr_tbl[i].length_attr); ++ } ++ ++ /* the last one */ ++ host->sdma_descr_tbl[i].dma_address = sg[i].dma_address; ++ host->sdma_descr_tbl[i].length_attr = (sg[i].length << 16) | (S3C_HSMMC_ADMA_ATTR_ACT_TRAN) | ++ (S3C_HSMMC_ADMA_ATTR_END | S3C_HSMMC_ADMA_ATTR_VALID); ++ ++ DBG(" ADMA2 descr table[%d] - addr: %08x, size+attr: %08x\n", i, host->sdma_descr_tbl[i].dma_address, ++ host->sdma_descr_tbl[i].length_attr); ++ ++ return (i); ++ ++} ++#endif ++ ++static inline void s3c_hsmmc_prepare_data (struct s3c_hsmmc_host *host, ++ struct mmc_command *cmd) ++{ ++ u8 reg8; ++ u32 reg; ++ struct mmc_data *data = cmd->data; ++ ++ if (data == NULL) { ++ reg = s3c_hsmmc_readl(S3C_HSMMC_NORINTSTSEN) | S3C_HSMMC_NIS_CMDCMP; ++ s3c_hsmmc_writel(reg, S3C_HSMMC_NORINTSTSEN); ++ return; ++ } ++ ++ reg = s3c_hsmmc_readl(S3C_HSMMC_NORINTSTSEN) & ~S3C_HSMMC_NIS_CMDCMP; ++ s3c_hsmmc_writel(reg, S3C_HSMMC_NORINTSTSEN); ++ ++ host->dma_dir = (data->flags & MMC_DATA_READ) ++ ? DMA_FROM_DEVICE : DMA_TO_DEVICE; ++ ++#ifdef CONFIG_HSMMC_SCATTERGATHER ++ host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, ++ host->dma_dir); ++ ++ reg = s3c_hsmmc_readl(S3C_HSMMC_NORINTSTSEN); ++ if (host->sg_len == 1) { ++ reg &= ~S3C_HSMMC_NIS_DMA; ++ } else { ++ reg |= S3C_HSMMC_NIS_DMA; ++ } ++ s3c_hsmmc_writel(reg, S3C_HSMMC_NORINTSTSEN); ++ ++ reg8 = s3c_hsmmc_readb(S3C_HSMMC_HOSTCTL); ++ reg8 |= S3C_HSMMC_CTRL_ADMA2_32; ++ s3c_hsmmc_writeb(reg8, S3C_HSMMC_HOSTCTL); ++ DBG("HOSTCTL(0x28) = 0x%02x\n", s3c_hsmmc_readb(S3C_HSMMC_HOSTCTL)); ++ DBG("data->flags(direction) = 0x%x\n", data->flags); ++ DBG("data->blksz: %d\n", data->blksz); ++ DBG("data->blocks: %d\n", data->blocks); ++ DBG("data->sg_len: %d\n", data->sg_len); ++ ++ DBG("data->sg->addr: 0x%x\n", data->sg->dma_address); ++ DBG("data->sg->length: 0x%x\n", data->sg->length); ++ ++ host->dma_blk = s3c_hsmmc_build_dma_table(host, data); ++ host->next_blk = 0; ++#else ++ DBG("data->flags(direction) = 0x%x\n", data->flags); ++ DBG("data->blksz: %d\n", data->blksz); ++ DBG("data->blocks: %d\n", data->blocks); ++ DBG("data->sg_len: %d\n", data->sg_len); ++ dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, ++ host->dma_dir); ++#endif ++} ++ ++static inline void s3c_hsmmc_set_transfer_mode (struct s3c_hsmmc_host *host, ++ struct mmc_data *data) ++{ ++ u16 mode; ++ ++ mode = S3C_HSMMC_TRNS_DMA; ++ ++ if (data->stop) ++ mode |= S3C_HSMMC_TRNS_ACMD12; ++ ++ if (data->blocks > 1) ++ mode |= S3C_HSMMC_TRNS_MULTI | S3C_HSMMC_TRNS_BLK_CNT_EN; ++ if (data->flags & MMC_DATA_READ) ++ mode |= S3C_HSMMC_TRNS_READ; ++ ++ s3c_hsmmc_writew(mode, S3C_HSMMC_TRNMOD); ++} ++ ++static inline void s3c_hsmmc_send_register (struct s3c_hsmmc_host *host) ++{ ++ struct mmc_command *cmd = host->cmd; ++ struct mmc_data *data = cmd->data; ++ ++ u32 cmd_val; ++ ++ if (data) { ++ ++#ifdef CONFIG_HSMMC_SCATTERGATHER ++ s3c_hsmmc_writew(S3C_HSMMC_MAKE_BLKSZ(0x7, data->blksz), S3C_HSMMC_BLKSIZE); ++ s3c_hsmmc_writel(virt_to_phys(host->sdma_descr_tbl), S3C_HSMMC_ADMASYSADDR); ++ DBG("S3C_HSMMC_ADMASYSADDR(0x58) = 0x%08x\n", s3c_hsmmc_readl(S3C_HSMMC_ADMASYSADDR)); ++#else ++ s3c_hsmmc_writew(S3C_HSMMC_MAKE_BLKSZ(0x7, data->blksz), S3C_HSMMC_BLKSIZE); ++ s3c_hsmmc_writel(sg_dma_address(data->sg), S3C_HSMMC_SYSAD); ++#endif ++ s3c_hsmmc_writew(data->blocks, S3C_HSMMC_BLKCNT); ++ s3c_hsmmc_set_transfer_mode(host, data); ++ } ++ ++ s3c_hsmmc_writel(cmd->arg, S3C_HSMMC_ARGUMENT); ++ ++ cmd_val = (cmd->opcode << 8); ++ if (cmd_val == (12<<8)) ++ cmd_val |= (3 << 6); ++ ++ if (cmd->flags & MMC_RSP_136) /* Long RSP */ ++ cmd_val |= S3C_HSMMC_CMD_RESP_LONG; ++ else if (cmd->flags & MMC_RSP_BUSY) /* R1B */ ++ cmd_val |= S3C_HSMMC_CMD_RESP_SHORT_BUSY; ++ else if (cmd->flags & MMC_RSP_PRESENT) /* Normal RSP */ ++ cmd_val |= S3C_HSMMC_CMD_RESP_SHORT; ++ ++ if (cmd->flags & MMC_RSP_OPCODE) ++ cmd_val |= S3C_HSMMC_CMD_INDEX; ++ ++ if (cmd->flags & MMC_RSP_CRC) ++ cmd_val |= S3C_HSMMC_CMD_CRC; ++ ++ if (data) ++ cmd_val |= S3C_HSMMC_CMD_DATA; ++ ++ s3c_hsmmc_writew(cmd_val, S3C_HSMMC_CMDREG); ++} ++ ++static inline void s3c_hsmmc_send_command (struct s3c_hsmmc_host *host, ++ struct mmc_command *cmd) ++{ ++ u32 mask=1; ++ ulong timeout; ++ ++ while (s3c_hsmmc_readl(S3C_HSMMC_CONTROL4) & mask); ++ ++ DBG("Sending cmd=(%d), arg=0x%x\n", cmd->opcode, cmd->arg); ++ ++ /* Wait max 10 ms */ ++ timeout = 10; ++ ++ mask = S3C_HSMMC_CMD_INHIBIT; ++ if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) ++ mask |= S3C_HSMMC_DATA_INHIBIT; ++ ++ while (s3c_hsmmc_readl(S3C_HSMMC_PRNSTS) & mask) { ++ printk("########### waiting controller wakeup\n"); ++ if (timeout == 0) { ++ printk(KERN_ERR "%s: Controller never released " ++ "inhibit bit(s).\n", mmc_hostname(host->mmc)); ++ cmd->error = -EIO; ++ tasklet_schedule(&host->finish_tasklet); ++ return; ++ } ++ timeout--; ++ mdelay(1); ++ } ++ ++ mod_timer(&host->timer, jiffies + 10 * HZ); ++ ++ host->cmd = cmd; ++ ++ s3c_hsmmc_prepare_data(host, cmd); ++ s3c_hsmmc_send_register(host); ++} ++ ++static void s3c_hsmmc_finish_data (struct s3c_hsmmc_host *host) ++{ ++ struct mmc_data *data; ++ u16 blocks; ++ ++ if(!host->data) return; ++ ++ data = host->data; ++ host->data = NULL; ++ ++ dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, ++ (data->flags & MMC_DATA_READ) ++ ? DMA_FROM_DEVICE : DMA_TO_DEVICE); ++ ++ /* ++ * Controller doesn't count down when in single block mode. ++ */ ++ if (data->blocks == 1) ++ blocks = (data->error == 0) ? 0 : 1; ++ else { ++ blocks = s3c_hsmmc_readw(S3C_HSMMC_BLKCNT); ++ } ++ data->bytes_xfered = data->blksz * (data->blocks - blocks); ++ ++ if (!data->error && blocks) { ++ printk(KERN_ERR "%s: Controller signalled completion even " ++ "though there were blocks left. : %d\n", ++ mmc_hostname(host->mmc), blocks); ++ data->error = -EIO; ++ } ++ DBG("data->flags(direction) FINISHED = %d\n", data->flags); ++ DBG("data->blksz FINISHED = %d\n", data->blksz); ++ DBG("data->blocks FINISHED = %d\n", data->blocks); ++ DBG("Not FINISHED blocks = %d\n", blocks); ++ DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered); ++ DBG("\n"); ++ ++ tasklet_schedule(&host->finish_tasklet); ++} ++ ++static void s3c_hsmmc_finish_command (struct s3c_hsmmc_host *host) ++{ ++ int i; ++ ++ if(!host->cmd) return; ++ ++ if (host->cmd->flags & MMC_RSP_PRESENT) { ++ if (host->cmd->flags & MMC_RSP_136) { ++ /* CRC is stripped so we need to do some shifting. */ ++ for (i=0; i<4; i++) { ++ host->cmd->resp[i] = s3c_hsmmc_readl(S3C_HSMMC_RSPREG0+ (3-i)*4) << 8; ++ if (i != 3) ++ host->cmd->resp[i] |= s3c_hsmmc_readb(S3C_HSMMC_RSPREG0 + (3-i)*4-1); ++ DBG("cmd (%d) resp[%d] = 0x%x\n", host->cmd->opcode, i, host->cmd->resp[i]); ++ } ++ } else { ++ host->cmd->resp[0] = s3c_hsmmc_readl(S3C_HSMMC_RSPREG0); ++ DBG("cmd (%d) resp[%d] = 0x%x\n", host->cmd->opcode, 0, host->cmd->resp[0]); ++ } ++ } ++ ++ host->cmd->error = 0; ++ ++ DBG("Ending cmd (%d)\n", host->cmd->opcode); ++ DBG("\n"); ++ ++ if (host->cmd->data) ++ host->data = host->cmd->data; ++ else ++ tasklet_schedule(&host->finish_tasklet); ++ ++ host->cmd = NULL; ++} ++ ++static void s3c_hsmmc_tasklet_finish (unsigned long param) ++{ ++ struct s3c_hsmmc_host *host; ++ unsigned long iflags; ++ struct mmc_request *mrq; ++ ++ host = (struct s3c_hsmmc_host*)param; ++ ++ if(!host->mrq) return; ++ ++ spin_lock_irqsave(&host->lock, iflags); ++ ++ del_timer(&host->timer); ++ ++ mrq = host->mrq; ++ ++ /* ++ * The controller needs a reset of internal state machines ++ * upon error conditions. ++ */ ++ if ((mrq->cmd->error) || (mrq->data && (mrq->data->error)) ) { ++ s3c_hsmmc_reset(host, S3C_HSMMC_RESET_CMD); ++ s3c_hsmmc_reset(host, S3C_HSMMC_RESET_DATA); ++ } ++ ++ host->mrq = NULL; ++ host->cmd = NULL; ++ host->data = NULL; ++ ++ mmiowb(); ++ spin_unlock_irqrestore(&host->lock, iflags); ++ ++ mmc_request_done(host->mmc, mrq); ++} ++ ++/***************************************************************************** ++ * * ++ * Interrupt handling * ++ * * ++ *****************************************************************************/ ++ ++static void s3c_hsmmc_cmd_irq (struct s3c_hsmmc_host *host, u32 intmask) ++{ ++ if (!host->cmd) { ++ printk(KERN_ERR "%s: Got command interrupt 0x%08x even " ++ "though no command operation was in progress.\n", ++ mmc_hostname(host->mmc), (unsigned)intmask); ++ return; ++ } ++ ++ if (intmask & S3C_HSMMC_INT_TIMEOUT) ++ host->cmd->error = -ETIMEDOUT; ++ else if (intmask & (S3C_HSMMC_INT_CRC | S3C_HSMMC_INT_END_BIT | S3C_HSMMC_INT_INDEX)) ++ host->cmd->error = -EILSEQ; ++ ++ if (host->cmd->error) ++ tasklet_schedule(&host->finish_tasklet); ++} ++ ++static void s3c_hsmmc_data_irq (struct s3c_hsmmc_host *host, u32 intmask) ++{ ++ if (!host->data) { ++ /* ++ * A data end interrupt is sent together with the response ++ * for the stop command. ++ */ ++ if (intmask & S3C_HSMMC_INT_DATA_END) ++ return; ++ ++ printk(KERN_ERR "%s: Got data interrupt even though no " ++ "data operation was in progress.\n", ++ mmc_hostname(host->mmc)); ++ return; ++ } ++ ++ if (intmask & S3C_HSMMC_INT_DATA_TIMEOUT) ++ host->data->error = -ETIMEDOUT; ++ else if (intmask & (S3C_HSMMC_INT_DATA_CRC|S3C_HSMMC_INT_DATA_END_BIT)) ++ host->data->error = -EILSEQ; ++ ++ if (host->data->error) ++ s3c_hsmmc_finish_data(host); ++} ++ ++ ++/*****************************************************************************\ ++ * * ++ * Interrupt handling * ++ * * ++\*****************************************************************************/ ++ ++/* ++ * ISR for SDI Interface IRQ ++ * Communication between driver and ISR works as follows: ++ * host->mrq points to current request ++ * host->complete_what tells the ISR when the request is considered done ++ * ++ * 1) Driver sets up host->mrq and host->complete_what ++ * 2) Driver prepares the transfer ++ * 3) Driver enables interrupts ++ * 4) Driver starts transfer ++ * 5) Driver waits for host->complete_rquest ++ * 6) ISR checks for request status (errors and success) ++ * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error ++ * 7) ISR completes host->complete_request ++ * 8) ISR disables interrupts ++ * 9) Driver wakes up and takes care of the request ++ */ ++ ++static irqreturn_t s3c_hsmmc_irq (int irq, void *dev_id) ++{ ++ irqreturn_t result = 0; ++ struct s3c_hsmmc_host *host = dev_id; ++ struct mmc_request *mrq; ++ u32 intsts; ++ ++ uint i, org_irq_sts; ++ ++ spin_lock(&host->lock); ++ ++ mrq = host->mrq; ++ ++ intsts = s3c_hsmmc_readw(S3C_HSMMC_NORINTSTS); ++ ++ /* Sometimes, hsmmc does not update its status bit immediately ++ * when it generates irqs. ++ */ ++ for (i=0; i<0x1000; i++) { ++ if ((intsts = s3c_hsmmc_readw(S3C_HSMMC_NORINTSTS))) ++ break; ++ } ++ ++ if (unlikely(!intsts)) { ++ result = IRQ_NONE; ++ goto out; ++ } ++ intsts = s3c_hsmmc_readl(S3C_HSMMC_NORINTSTS); ++ org_irq_sts = intsts; ++ ++ DBG(PFX "Got interrupt = 0x%08x\n", intsts); ++ ++ if (unlikely(intsts & S3C_HSMMC_INT_CARD_CHANGE)) { ++ u32 reg16; ++ ++ reg16 = s3c_hsmmc_readw(S3C_HSMMC_NORINTSTSEN); ++ s3c_hsmmc_writew(reg16 & ~S3C_HSMMC_INT_CARD_CHANGE, ++ S3C_HSMMC_NORINTSTSEN); ++ s3c_hsmmc_writew(S3C_HSMMC_INT_CARD_CHANGE, S3C_HSMMC_NORINTSTS); ++ s3c_hsmmc_writew(reg16, S3C_HSMMC_NORINTSTSEN); ++ ++ intsts &= ~S3C_HSMMC_INT_CARD_CHANGE; ++ ++ tasklet_schedule(&host->card_tasklet); ++ goto insert; ++ } ++ ++ if (likely(!(intsts & S3C_HSMMC_NIS_ERR))) { ++ s3c_hsmmc_writel(intsts, S3C_HSMMC_NORINTSTS); ++ ++ if (intsts & S3C_HSMMC_NIS_CMDCMP) { ++ DBG("command done\n"); ++ s3c_hsmmc_finish_command(host); ++ } ++ ++ if (intsts & S3C_HSMMC_NIS_TRSCMP) { ++ DBG("transfer done\n\n"); ++ s3c_hsmmc_finish_command(host); ++ s3c_hsmmc_finish_data(host); ++ intsts &= ~S3C_HSMMC_NIS_DMA; ++ } ++ ++ } else { ++ DBG("command FAIL : found bad irq [0x%8x]\n", intsts); ++ DBG("\n"); ++ if (intsts & S3C_HSMMC_INT_CMD_MASK) { ++ s3c_hsmmc_writel(intsts & S3C_HSMMC_INT_CMD_MASK, S3C_HSMMC_NORINTSTS); ++ s3c_hsmmc_cmd_irq(host, intsts & S3C_HSMMC_INT_CMD_MASK); ++ } ++ ++ if (intsts & S3C_HSMMC_INT_DATA_MASK) { ++ s3c_hsmmc_writel(intsts & S3C_HSMMC_INT_DATA_MASK, S3C_HSMMC_NORINTSTS); ++ s3c_hsmmc_finish_command(host); ++ s3c_hsmmc_data_irq(host, intsts & S3C_HSMMC_INT_DATA_MASK); ++ } ++ ++ intsts &= ~(S3C_HSMMC_INT_CMD_MASK | S3C_HSMMC_INT_DATA_MASK); ++ } ++ ++ for (i=0; i<0x1000; i++) { ++ if (org_irq_sts != s3c_hsmmc_readl(S3C_HSMMC_NORINTSTS)) ++ break; ++ } ++ ++insert: ++ result = IRQ_HANDLED; ++ mmiowb(); ++ ++out: ++ spin_unlock(&host->lock); ++ ++ return result; ++} ++ ++#if defined(CONFIG_CPU_S3C6410) ++static irqreturn_t s3c_hsmmc_irq_cd (int irq, void *dev_id) ++{ ++ struct s3c_hsmmc_host *host = dev_id; ++ int ext_CD_int = 0; ++ ++ ext_CD_int = readl(S3C64XX_GPNDAT); ++ //ext_CD_int &= 0x2000; /* GPN13 */ ++ ext_CD_int &= 0x40; ++ ++ if(ext_CD_int && card_detect) { ++ printk("s3c-hsmmc channel-0(EXT): card removed.\n"); ++ set_irq_type(host->irq_cd, IRQ_TYPE_EDGE_FALLING); ++ card_detect = 0; ++ } ++ else if(!ext_CD_int && !card_detect) { ++ printk("s3c-hsmmc channel-0(EXT): card inserted.\n"); ++ set_irq_type(host->irq_cd, IRQ_TYPE_EDGE_RISING); ++ card_detect = 1; ++ } ++ else ++ return IRQ_HANDLED; ++ ++ ++ tasklet_schedule(&host->card_tasklet); ++ mmiowb(); ++ ++ spin_unlock(&host->lock); ++ ++ return IRQ_HANDLED; ++} ++#endif ++ ++static void s3c_hsmmc_check_status (unsigned long data) ++{ ++ struct s3c_hsmmc_host *host = (struct s3c_hsmmc_host *)data; ++ ++ s3c_hsmmc_irq(0, host); ++} ++ ++static void s3c_hsmmc_request (struct mmc_host *mmc, struct mmc_request *mrq) ++{ ++ struct s3c_hsmmc_host *host = mmc_priv(mmc); ++ unsigned long flags; ++ ++ DBG("hsmmc request: [CMD] opcode:%d arg:0x%08x flags:0x%02x retries:%u\n", ++ mrq->cmd->opcode, mrq->cmd->arg, mrq->cmd->flags, mrq->cmd->retries); ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ WARN_ON(host->mrq != NULL); ++ ++ host->mrq = mrq; ++ ++ if ((s3c_hsmmc_readl(S3C_HSMMC_PRNSTS) & S3C_HSMMC_CARD_PRESENT)) { ++ s3c_hsmmc_send_command(host, mrq->cmd); ++ } else { ++ host->mrq->cmd->error = -ENOMEDIUM; ++ tasklet_schedule(&host->finish_tasklet); ++ } ++ ++ mmiowb(); ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++/* return 0: OK ++ * return -1: error ++ */ ++static int s3c_set_bus_width (struct s3c_hsmmc_host *host, uint width) ++{ ++ u8 reg; ++ ++ reg = s3c_hsmmc_readb(S3C_HSMMC_HOSTCTL); ++ ++ switch (width) { ++ case MMC_BUS_WIDTH_1: ++ reg &= ~(S3C_HSMMC_CTRL_4BIT | S3C_HSMMC_CTRL_8BIT); ++ DBG("bus width: 1 bit\n"); ++ break; ++ ++ case MMC_BUS_WIDTH_4: ++ DBG("bus width: 4 bit\n"); ++ reg &= ~(S3C_HSMMC_CTRL_8BIT); ++ reg |= S3C_HSMMC_CTRL_4BIT; ++ break; ++ ++ case MMC_BUS_WIDTH_8: ++ reg |= S3C_HSMMC_CTRL_8BIT; ++ DBG("bus width: 8 bit\n"); ++ break; ++ ++ default: ++ DBG("bus width: Error\n"); ++ return -1; ++ } ++ ++ s3c_hsmmc_writeb(reg, S3C_HSMMC_HOSTCTL); ++ ++ DBG("HOSTCTL(0x28) = 0x%02x\n", s3c_hsmmc_readb(S3C_HSMMC_HOSTCTL)); ++ ++ return 0; ++} ++ ++static void s3c_hsmmc_set_clock (struct s3c_hsmmc_host *host, ulong clock) ++{ ++ struct s3c_hsmmc_cfg *cfg = host->plat_data; ++ int cardtype = 0; ++ u32 val = 0, tmp_clk = 0, sel_clk = 0, i, j; ++ u16 div = (u16)-1; ++ ulong timeout; ++ u8 ctrl; ++ ++ if(host->mmc->card != NULL) ++ cardtype = host->mmc->card->type; ++ ++ /* if we already set, just out. */ ++ if (clock == host->clock) { ++ printk("%p:host->clock0 : %d Hz\n", host->base, host->clock); ++ return; ++ } ++ ++ /* before setting clock, clkcon must be disabled. */ ++ s3c_hsmmc_writew(0, S3C_HSMMC_CLKCON); ++ ++ s3c_hsmmc_writeb(S3C_HSMMC_TIMEOUT_MAX, S3C_HSMMC_TIMEOUTCON); ++ ++ /* change the edge type according to frequency */ ++ ctrl = s3c_hsmmc_readb(S3C_HSMMC_HOSTCTL); ++ ++ if (cfg->highspeed) ++ ctrl |= S3C_HSMMC_CTRL_HIGHSPEED; ++ else ++ ctrl &= ~S3C_HSMMC_CTRL_HIGHSPEED; ++ ++ s3c_hsmmc_writeb(ctrl, S3C_HSMMC_HOSTCTL); ++ ++ if (clock == 0) { ++ DBG(" In case of 0 Hz of clock, I'm afraid DO NOTHING ..\n"); ++ return; ++ } ++ ++ /* calculate optimal clock. by scsuh */ ++ DBG("Requested clock is %ld Hz\n", clock); ++ ++ for (i = 0; i < NUM_OF_HSMMC_CLKSOURCES; i++) { ++ if ((tmp_clk = clk_get_rate(host->clk[i])) <= clock) { ++ if (tmp_clk >= val) { ++ val = tmp_clk; ++ div = 0; ++ sel_clk = i; ++ } ++ } ++ ++ for (j = 0x1; j <= 0x80; j <<= 1) { ++ tmp_clk = clk_get_rate(host->clk[i]) / (j << 1); ++ if ((val < tmp_clk) && (tmp_clk <= clock)) { ++ val = tmp_clk; ++ div = j; ++ sel_clk = i; ++ break; ++ } ++ } ++ DBG(" tmp_val[%d]: %d\n", sel_clk, val); ++ } ++ ++ DBG("Optimal clock : %d Hz, div: 0x%x, SelBaseclk_src: %s(%d)\n", val, div, cfg->clocks[sel_clk].name, cfg->clocks[sel_clk].src); ++ ++ /* CONTROL2 */ ++ s3c_hsmmc_writel(cfg->fd_ctrl[cardtype].ctrl2 | (cfg->clocks[sel_clk].src << 4), S3C_HSMMC_CONTROL2); ++ ++ /* CONTROL3 */ ++ if (clock > 25000000) ++ s3c_hsmmc_writel(cfg->fd_ctrl[cardtype].ctrl3[SPEED_HIGH], S3C_HSMMC_CONTROL3); ++ else ++ s3c_hsmmc_writel(cfg->fd_ctrl[cardtype].ctrl3[SPEED_NORMAL], S3C_HSMMC_CONTROL3); ++ ++ s3c_hsmmc_writel(cfg->fd_ctrl[cardtype].ctrl4 << 16, S3C_HSMMC_CONTROL4); ++ ++ s3c_hsmmc_writew(((div<<8) | S3C_HSMMC_CLOCK_INT_EN), S3C_HSMMC_CLKCON); ++ ++ timeout = 10; ++ while (!((val = s3c_hsmmc_readw(S3C_HSMMC_CLKCON)) ++ & S3C_HSMMC_CLOCK_INT_STABLE)) { ++ if (!timeout) { ++ printk("HSMMC: Error in INTERNAL clock stabilization: %08x\n", val); ++ return; ++ } ++ timeout--; ++ mdelay(1); ++ } ++ ++ s3c_hsmmc_writew(val | S3C_HSMMC_CLOCK_CARD_EN, S3C_HSMMC_CLKCON); ++ ++} ++ ++ ++static void s3c_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) ++{ ++ struct s3c_hsmmc_host *host = mmc_priv(mmc); ++ ++ unsigned long iflags; ++ ++ spin_lock_irqsave(&host->lock, iflags); ++ ++ /* ++ * Reset the chip on each power off. ++ * Should clear out any weird states. ++ */ ++ if (ios->power_mode == MMC_POWER_OFF) { ++ s3c_hsmmc_writew(0, S3C_HSMMC_NORINTSIGEN); ++ s3c_hsmmc_ios_init(host); ++ } ++ ++ if (host->plat_data->enabled) ++ hsmmc_set_gpio(host->plat_data->hwport, host->plat_data->bus_width); ++ ++ DBG("\nios->clock: %d Hz\n", ios->clock); ++ s3c_hsmmc_set_clock(host, ios->clock); ++ ++ DBG("\nios->bus_width: %d\n", ios->bus_width); ++ s3c_set_bus_width(host, ios->bus_width); ++ ++ DBG("S3C_HSMMC_CONTROL2(0x80) = 0x%08x\n", s3c_hsmmc_readl(S3C_HSMMC_CONTROL2)); ++ DBG("S3C_HSMMC_CONTROL3(0x84) = 0x%08x\n", s3c_hsmmc_readl(S3C_HSMMC_CONTROL3)); ++ DBG("S3C_HSMMC_CLKCON (0x2c) = 0x%04x\n", s3c_hsmmc_readw(S3C_HSMMC_CLKCON)); ++ ++ if (ios->power_mode == MMC_POWER_OFF) ++ s3c_hsmmc_writeb(S3C_HSMMC_POWER_OFF, S3C_HSMMC_PWRCON); ++ else ++ s3c_hsmmc_writeb(S3C_HSMMC_POWER_ON_ALL, S3C_HSMMC_PWRCON); ++ ++ udelay(1000); ++ spin_unlock_irqrestore(&host->lock, iflags); ++} ++ ++static struct mmc_host_ops s3c_hsmmc_ops = { ++ .request = s3c_hsmmc_request, ++ .set_ios = s3c_hsmmc_set_ios, ++}; ++ ++static int s3c_hsmmc_probe (struct platform_device *pdev) ++{ ++ struct mmc_host *mmc; ++ struct s3c_hsmmc_host *host; ++ struct s3c_hsmmc_cfg *plat_data; ++ uint i; ++ int ret; ++ ++ mmc = mmc_alloc_host(sizeof(struct s3c_hsmmc_host), &pdev->dev); ++ ++ if (mmc==NULL) { ++ ret = -ENOMEM; ++ printk("Failed to get mmc_alloc_host.\n"); ++ return ret; ++ } ++ ++ plat_data = s3c_hsmmc_get_platdata(&pdev->dev); ++ ++ host = mmc_priv(mmc); ++ ++ host->mmc = mmc; ++ ++ host->plat_data = plat_data; ++ ++ host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!host->mem) { ++ printk("Failed to get io memory region resouce.\n"); ++ ret = -ENOENT; ++ goto probe_free_host; ++ } ++ ++ host->mem = request_mem_region(host->mem->start, ++ RESSIZE(host->mem), pdev->name); ++ if (!host->mem) { ++ printk("Failed to request io memory region.\n"); ++ ret = -ENOENT; ++ goto probe_free_host; ++ } ++ ++ host->base = ioremap(host->mem->start, (host->mem->end - host->mem->start)+1); ++ if (host->base == NULL) { ++ printk(KERN_ERR "Failed to remap register block\n"); ++ return -ENOMEM; ++ } ++ ++ host->irq = platform_get_irq(pdev, 0); ++ if (host->irq == 0) { ++ printk("Failed to get interrupt resouce.\n"); ++ ret = -EINVAL; ++ goto untasklet; ++ } ++ ++#if defined(CONFIG_CPU_S3C6410) ++ /* To detect a card inserted on channel 0, an external interrupt is used. */ ++ if ((plat_data->enabled == 1) && (plat_data->hwport == 0)) { ++ host->irq_cd = platform_get_irq(pdev, 1); ++ if (host->irq_cd == 0) { ++ printk("Failed to get interrupt resouce.\n"); ++ ret = -EINVAL; ++ goto untasklet; ++ } ++ set_irq_type(host->irq_cd, IRQ_TYPE_LEVEL_LOW); ++ } ++#endif ++ ++ host->flags |= S3C_HSMMC_USE_DMA; ++ ++ s3c_hsmmc_reset(host, S3C_HSMMC_RESET_ALL); ++ ++ clk_enable(clk_get(&pdev->dev, "hsmmc")); ++ ++ /* register some clock sources if exist */ ++ for (i=0; iclk[i] = clk_get(&pdev->dev, plat_data->clocks[i].name); ++ if (IS_ERR(host->clk[i])) { ++ ret = PTR_ERR(host->clk[i]); ++ host->clk[i] = ERR_PTR(-ENOENT); ++ } ++ ++ if (clk_enable(host->clk[i])) { ++ host->clk[i] = ERR_PTR(-ENOENT); ++ } ++ ++ if (!IS_ERR(host->clk[i])) { ++ DBG("MMC clock source[%d], %s is %ld Hz\n",i, plat_data->clocks[i].name, clk_get_rate(host->clk[i])); ++ } ++ } ++ ++ mmc->ops = &s3c_hsmmc_ops; ++ mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34; ++ mmc->f_min = 400 * 1000; /* at least 400kHz */ ++ ++ /* you must make sure that our hsmmc block can support ++ * up to 52MHz. ++ */ ++ mmc->f_max = 100 * MHZ; ++ mmc->caps = plat_data->host_caps; ++ DBG("mmc->caps: %08x\n", mmc->caps); ++ ++ spin_lock_init(&host->lock); ++ ++ /* ++ * Maximum number of segments. Hardware cannot do scatter lists. ++ * XXX: must modify later. ++ */ ++#ifdef CONFIG_HSMMC_SCATTERGATHER ++ mmc->max_hw_segs = CONFIG_S3C_HSMMC_MAX_HW_SEGS; ++ mmc->max_phys_segs = CONFIG_S3C_HSMMC_MAX_HW_SEGS; ++#else ++ mmc->max_hw_segs = 1; ++#endif ++ ++ /* ++ * Maximum segment size. Could be one segment with the maximum number ++ * of sectors. ++ */ ++ mmc->max_blk_size = 512; ++ mmc->max_seg_size = 128 * mmc->max_blk_size; ++ ++ mmc->max_blk_count = 128; ++ mmc->max_req_size = mmc->max_seg_size; ++ ++ ++ init_timer(&host->timer); ++ host->timer.data = (unsigned long)host; ++ host->timer.function = s3c_hsmmc_check_status; ++ host->timer.expires = jiffies + HZ; ++ ++ /* ++ * Init tasklets. ++ */ ++ tasklet_init(&host->card_tasklet, ++ s3c_hsmmc_tasklet_card, (unsigned long)host); ++ tasklet_init(&host->finish_tasklet, ++ s3c_hsmmc_tasklet_finish, (unsigned long)host); ++ ++ ret = request_irq(host->irq, s3c_hsmmc_irq, 0, DRIVER_NAME, host); ++ if (ret) ++ goto untasklet; ++ ++#if defined(CONFIG_CPU_S3C6410) ++ if ((plat_data->enabled == 1) && (plat_data->hwport == 0)) { ++ ret = request_irq(host->irq_cd, s3c_hsmmc_irq_cd, 0, DRIVER_NAME, host); ++ if (ret) ++ goto untasklet; ++ } ++#endif ++ ++ s3c_hsmmc_ios_init(host); ++ ++ mmc_add_host(mmc); ++ ++#if defined(CONFIG_PM) ++ global_host[plat_data->hwport] = host; ++#endif ++ ++ printk(KERN_INFO "[s3c_hsmmc_probe]: %s.%d: at 0x%p with irq %d. clk src:", ++ pdev->name, pdev->id, host->base, host->irq); ++ ++ for (i=0; iclk[i])) ++ printk(" %s", host->clk[i]->name); ++ } ++ printk("\n"); ++ ++ return 0; ++ ++untasklet: ++ tasklet_kill(&host->card_tasklet); ++ tasklet_kill(&host->finish_tasklet); ++ ++ for (i=0; iclk[i] != ERR_PTR(-ENOENT)) { ++ clk_disable(host->clk[i]); ++ clk_put(host->clk[i]); ++ } ++ } ++ ++probe_free_host: ++ mmc_free_host(mmc); ++ ++ return ret; ++} ++ ++static int s3c_hsmmc_remove(struct platform_device *dev) ++{ ++ struct mmc_host *mmc = platform_get_drvdata(dev); ++ struct s3c_hsmmc_host *host = mmc_priv(mmc); ++ int i; ++ ++ mmc = host->mmc; ++ ++ mmc_remove_host(mmc); ++ ++ s3c_hsmmc_reset(host, S3C_HSMMC_RESET_ALL); ++ ++ clk_disable(clk_get(&dev->dev, "hsmmc")); ++ ++ for (i=0; iclk[i]); ++ clk_put(host->clk[i]); ++ } ++ ++ free_irq(host->irq, host); ++ ++ del_timer_sync(&host->timer); ++ ++ tasklet_kill(&host->card_tasklet); ++ tasklet_kill(&host->finish_tasklet); ++ ++ mmc_free_host(mmc); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int s3c_hsmmc_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct s3c_hsmmc_host *s3c_host = global_host[pdev->id]; ++ struct mmc_host *host = s3c_host->mmc; ++ ++ mmc_suspend_host(host, state); ++ ++ return 0; ++} ++ ++static int s3c_hsmmc_resume(struct platform_device *pdev) ++{ ++ struct s3c_hsmmc_host *s3c_host = global_host[pdev->id]; ++ struct mmc_host *host = s3c_host->mmc; ++ ++ s3c_hsmmc_ios_init(s3c_host); ++ mmc_resume_host(host); ++ ++ return 0; ++} ++#else ++#define s3c_hsmmc_suspend NULL ++#define s3c_hsmmc_resume NULL ++#endif ++ ++ ++static struct platform_driver s3c_hsmmc_driver = ++{ ++ .probe = s3c_hsmmc_probe, ++ .remove = s3c_hsmmc_remove, ++ .suspend = s3c_hsmmc_suspend, ++ .resume = s3c_hsmmc_resume, ++ .driver = { ++ .name = "s3c-hsmmc", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init s3c_hsmmc_drv_init(void) ++{ ++ return platform_driver_register(&s3c_hsmmc_driver); ++} ++ ++static void __exit s3c_hsmmc_drv_exit(void) ++{ ++ platform_driver_unregister(&s3c_hsmmc_driver); ++} ++ ++ ++module_init(s3c_hsmmc_drv_init); ++module_exit(s3c_hsmmc_drv_exit); ++ ++ ++MODULE_DESCRIPTION("S3C SD HOST I/F 1.0 and 2.0 Driver"); ++MODULE_LICENSE("GPL"); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/mmc/host/s3cmci.c linux-2.6.28.6/drivers/mmc/host/s3cmci.c +--- linux-2.6.28/drivers/mmc/host/s3cmci.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/mmc/host/s3cmci.c 2009-04-30 09:36:38.000000000 +0200 +@@ -25,7 +25,7 @@ + #include + #include + +-#include ++#include + + #include "s3cmci.h" + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/mmc/host/sdhci-pci.c linux-2.6.28.6/drivers/mmc/host/sdhci-pci.c +--- linux-2.6.28/drivers/mmc/host/sdhci-pci.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/mmc/host/sdhci-pci.c 2009-04-30 09:36:38.000000000 +0200 +@@ -391,6 +391,7 @@ + + static struct sdhci_ops sdhci_pci_ops = { + .enable_dma = sdhci_pci_enable_dma, ++ .change_clock = sdhci_change_clock, + }; + + /*****************************************************************************\ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/mmc/host/sdhci-s3c.c linux-2.6.28.6/drivers/mmc/host/sdhci-s3c.c +--- linux-2.6.28/drivers/mmc/host/sdhci-s3c.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/mmc/host/sdhci-s3c.c 2009-10-14 08:54:58.000000000 +0200 +@@ -0,0 +1,440 @@ ++/* linux/drivers/mmc/host/sdhci-s3c.c ++ * ++ * Copyright 2008 Openmoko Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * SDHCI (HSMMC) support for Samsung SoC ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++ ++#include "sdhci.h" ++ ++#define MAX_BUS_CLK (4) ++ ++struct sdhci_s3c { ++ struct sdhci_host *host; ++ struct platform_device *pdev; ++ struct resource *ioarea; ++ struct s3c_sdhci_platdata *pdata; ++ unsigned int cur_clk; ++ ++ struct clk *clk_io; /* clock for io bus */ ++ struct clk *clk_bus[MAX_BUS_CLK]; ++}; ++ ++static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host) ++{ ++ return sdhci_priv(host); ++} ++ ++static u32 get_curclk(u32 ctrl2) ++{ ++ ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; ++ ctrl2 >>= S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; ++ ++ return ctrl2; ++} ++ ++static void sdhci_s3c_check_sclk(struct sdhci_host *host) ++{ ++ struct sdhci_s3c *ourhost = to_s3c(host); ++ u32 tmp = readl(host->ioaddr + S3C_SDHCI_CONTROL2); ++ ++ if (get_curclk(tmp) != ourhost->cur_clk) { ++ dev_dbg(&ourhost->pdev->dev, "restored ctrl2 clock setting\n"); ++ ++ tmp &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK; ++ tmp |= ourhost->cur_clk << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; ++ writel(tmp, host->ioaddr + S3C_SDHCI_CONTROL2); ++ } ++} ++ ++static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host) ++{ ++ struct sdhci_s3c *ourhost = to_s3c(host); ++ struct clk *busclk; ++ unsigned int rate, max; ++ int clk; ++ ++ /* note, a reset will reset the clock source */ ++ ++ sdhci_s3c_check_sclk(host); ++ ++ for (max = 0, clk = 0; clk < MAX_BUS_CLK; clk++) { ++ busclk = ourhost->clk_bus[clk]; ++ if (!busclk) ++ continue; ++ ++ rate = clk_get_rate(busclk); ++ if (rate > max) ++ max = rate; ++ } ++ ++ return max; ++} ++ ++static unsigned int sdhci_s3c_get_timeout_clk(struct sdhci_host *host) ++{ ++#if defined (CONFIG_CPU_S5PC100) ++ return sdhci_s3c_get_max_clk(host) / 3000000; ++#else ++ return sdhci_s3c_get_max_clk(host) / 1000000; ++#endif ++} ++ ++static void sdhci_s3c_set_ios(struct sdhci_host *host, ++ struct mmc_ios *ios) ++{ ++ struct sdhci_s3c *ourhost = to_s3c(host); ++ struct s3c_sdhci_platdata *pdata = ourhost->pdata; ++ int width; ++ ++ sdhci_s3c_check_sclk(host); ++ ++ if (ios->power_mode != MMC_POWER_OFF) { ++ switch (ios->bus_width) { ++ case MMC_BUS_WIDTH_4: ++ width = 4; ++ break; ++ case MMC_BUS_WIDTH_1: ++ width = 1; ++ break; ++ default: ++ BUG(); ++ } ++ ++ if (pdata->cfg_gpio) ++ pdata->cfg_gpio(ourhost->pdev, width); ++ } ++ ++ if (pdata->cfg_card) ++ pdata->cfg_card(ourhost->pdev, host->ioaddr, ++ ios, host->mmc->card); ++} ++ ++static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost, ++ unsigned int src, ++ unsigned int wanted) ++{ ++ unsigned long rate; ++ struct clk *clksrc = ourhost->clk_bus[src]; ++ int div; ++ ++ if (!clksrc) ++ return UINT_MAX; ++ ++ rate = clk_get_rate(clksrc); ++ ++ for (div = 1; div < 256; div *= 2) { ++ if ((rate / div) <= wanted) ++ break; ++ } ++ ++ dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n", ++ src, rate, wanted, rate / div); ++ ++ return (wanted - (rate / div)); ++} ++ ++static void sdhci_s3c_change_clock(struct sdhci_host *host, unsigned int clock) ++{ ++ struct sdhci_s3c *ourhost = to_s3c(host); ++ unsigned int best = UINT_MAX; ++ unsigned int delta; ++ int best_src = 0; ++ int src; ++ u32 ctrl; ++ ++ for (src = 0; src < MAX_BUS_CLK; src++) { ++ delta = sdhci_s3c_consider_clock(ourhost, src, clock); ++ if (delta < best) { ++ best = delta; ++ best_src = src; ++ } ++ } ++ ++ dev_dbg(&ourhost->pdev->dev, ++ "selected source %d, clock %d, delta %d\n", ++ best_src, clock, best); ++ ++ /* turn clock off to card before changing clock source */ ++ writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL); ++ ++ /* select the new clock source */ ++ ++ if (ourhost->cur_clk != best_src) { ++ struct clk *clk = ourhost->clk_bus[best_src]; ++ ++ ourhost->cur_clk = best_src; ++ host->max_clk = clk_get_rate(clk); ++ host->timeout_clk = host->max_clk / 1000; ++ ++ ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); ++ ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK; ++ ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; ++ writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); ++ } ++ ++ sdhci_change_clock(host, clock); ++} ++ ++static struct sdhci_ops sdhci_s3c_ops = { ++ .get_max_clock = sdhci_s3c_get_max_clk, ++ .get_timeout_clock = sdhci_s3c_get_timeout_clk, ++ .change_clock = sdhci_s3c_change_clock, ++ .set_ios = sdhci_s3c_set_ios, ++}; ++ ++irqreturn_t sdhci_irq_cd (int irq, void *dev_id) ++{ ++ struct sdhci_s3c* sc = dev_id; ++ uint detect = sc->pdata->detect_ext_cd(); ++ ++ if (detect) { ++ printk("sdhci: card inserted.\n"); ++ sc->host->flags |= SDHCI_DEVICE_ALIVE; ++ } else { ++ printk("sdhci: card removed.\n"); ++ sc->host->flags &= ~SDHCI_DEVICE_ALIVE; ++ } ++ tasklet_schedule(&sc->host->card_tasklet); ++ ++ return IRQ_HANDLED; ++} ++ ++static int __devinit sdhci_s3c_probe(struct platform_device *pdev) ++{ ++ struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data; ++ struct device *dev = &pdev->dev; ++ struct sdhci_host *host; ++ struct sdhci_s3c *sc; ++ struct resource *res; ++ int ret, irq, ptr, clks; ++ ++ if (!pdata) { ++ dev_err(dev, "no device data specified\n"); ++ return -ENOENT; ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++ dev_err(dev, "no irq specified\n"); ++ return irq; ++ } ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ dev_err(dev, "no memory specified\n"); ++ return -ENOENT; ++ } ++ ++ host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c)); ++ if (IS_ERR(host)) { ++ dev_err(dev, "sdhci_alloc_host() failed\n"); ++ return PTR_ERR(host); ++ } ++ ++ sc = sdhci_priv(host); ++ ++ platform_set_drvdata(pdev, host); ++ ++ sc->host = host; ++ sc->pdev = pdev; ++ sc->pdata = pdata; ++ ++ sc->clk_io = clk_get(dev, "hsmmc"); ++ if (IS_ERR(sc->clk_io)) { ++ dev_err(dev, "failed to get io clock\n"); ++ ret = PTR_ERR(sc->clk_io); ++ goto err_io_clk; ++ } ++ ++ /* enable the local io clock and keep it running for the moment. */ ++ clk_enable(sc->clk_io); ++ ++ for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) { ++ struct clk *clk; ++ char *name = pdata->clocks[ptr]; ++ ++ if (name == NULL) ++ continue; ++ ++ clk = clk_get(dev, name); ++ if (IS_ERR(clk)) { ++ dev_err(dev, "failed to get clock %s\n", name); ++ continue; ++ } ++ ++ clks++; ++ sc->clk_bus[ptr] = clk; ++ clk_enable(clk); ++ ++ dev_info(dev, "clock source %d: %s (%ld Hz)\n", ++ ptr, name, clk_get_rate(clk)); ++ } ++ ++ if (clks == 0) { ++ dev_err(dev, "failed to find any bus clocks\n"); ++ ret = -ENOENT; ++ goto err_no_busclks; ++ } ++ ++ sc->ioarea = request_mem_region(res->start, resource_size(res), ++ mmc_hostname(host->mmc)); ++ if (!sc->ioarea) { ++ dev_err(dev, "failed to reserve register area\n"); ++ ret = -ENXIO; ++ goto err_req_regs; ++ } ++ ++ host->ioaddr = ioremap_nocache(res->start, resource_size(res)); ++ if (!host->ioaddr) { ++ dev_err(dev, "failed to map registers\n"); ++ ret = -ENXIO; ++ goto err_req_regs; ++ } ++ ++ /* Ensure we have minimal gpio selected CMD/CLK/Detect */ ++ if (pdata->cfg_gpio) ++ pdata->cfg_gpio(pdev, 0); ++ ++ sdhci_s3c_check_sclk(host); ++ ++ host->hw_name = "samsung-hsmmc"; ++ host->ops = &sdhci_s3c_ops; ++ host->quirks = 0; ++ host->irq = irq; ++ ++ /* Setup quirks for the controller */ ++ ++ host->flags = SDHCI_USE_DMA; ++ ++ /* It seems we do not get an DATA transfer complete on non-busy ++ * transfers, not sure if this is a problem with this specific ++ * SDHCI block, or a missing configuration that needs to be set. */ ++ host->quirks |= SDHCI_QUIRK_NO_TCIRQ_ON_NOT_BUSY; ++ ++ host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR | ++ SDHCI_QUIRK_32BIT_DMA_SIZE); ++ ++ if (pdata->host_caps) ++ host->mmc->caps = pdata->host_caps; ++ else ++ host->mmc->caps = 0; ++ ++ /* to add external irq as a card detect signal */ ++ printk("[SDHCI]to add external irq as a card detect signal......\n"); ++ if (pdata->cfg_ext_cd) { ++ printk("[SDHCI]if (pdata->cfg_ext_cd)......\n"); ++ pdata->cfg_ext_cd(); ++ if (pdata->detect_ext_cd()) ++ host->flags |= SDHCI_DEVICE_ALIVE; ++ } ++ ++ ret = sdhci_add_host(host); ++ if (ret) { ++ dev_err(dev, "sdhci_add_host() failed\n"); ++ goto err_add_host; ++ } ++ ++ /* register external irq here (after all init is done) */ ++ if (pdata->cfg_ext_cd) { ++ printk("[SDHCI]request_irq......\n"); ++ ret = request_irq(pdata->ext_cd, sdhci_irq_cd, ++ IRQF_SHARED, mmc_hostname(host->mmc), sc); ++ } ++ ++ return 0; ++ ++ err_add_host: ++ release_resource(sc->ioarea); ++ kfree(sc->ioarea); ++ ++ err_req_regs: ++ for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) { ++ clk_disable(sc->clk_bus[ptr]); ++ clk_put(sc->clk_bus[ptr]); ++ } ++ ++ err_no_busclks: ++ clk_disable(sc->clk_io); ++ clk_put(sc->clk_io); ++ ++ err_io_clk: ++ sdhci_free_host(host); ++ ++ return ret; ++} ++ ++static int __devexit sdhci_s3c_remove(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++ ++static int sdhci_s3c_suspend(struct platform_device *dev, pm_message_t pm) ++{ ++ struct sdhci_host *host = platform_get_drvdata(dev); ++ ++ sdhci_suspend_host(host, pm); ++ return 0; ++} ++ ++static int sdhci_s3c_resume(struct platform_device *dev) ++{ ++ struct sdhci_host *host = platform_get_drvdata(dev); ++ ++ sdhci_resume_host(host); ++ return 0; ++} ++ ++#else ++#define sdhci_s3c_suspend NULL ++#define sdhci_s3c_resume NULL ++#endif ++ ++static struct platform_driver sdhci_s3c_driver = { ++ .probe = sdhci_s3c_probe, ++ .remove = __devexit_p(sdhci_s3c_remove), ++ .suspend = sdhci_s3c_suspend, ++ .resume = sdhci_s3c_resume, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "s3c-sdhci", ++ }, ++}; ++ ++static int __init sdhci_s3c_init(void) ++{ ++ return platform_driver_register(&sdhci_s3c_driver); ++} ++ ++static void __exit sdhci_s3c_exit(void) ++{ ++ platform_driver_unregister(&sdhci_s3c_driver); ++} ++ ++module_init(sdhci_s3c_init); ++module_exit(sdhci_s3c_exit); ++ ++MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue"); ++MODULE_AUTHOR("Ben Dooks, "); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:s3c-sdhci"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/mmc/host/sdhci.c linux-2.6.28.6/drivers/mmc/host/sdhci.c +--- linux-2.6.28/drivers/mmc/host/sdhci.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/mmc/host/sdhci.c 2009-04-30 09:36:38.000000000 +0200 +@@ -73,6 +73,11 @@ + readl(host->ioaddr + SDHCI_CAPABILITIES), + readl(host->ioaddr + SDHCI_MAX_CURRENT)); + ++ if (host->flags & SDHCI_USE_ADMA) ++ printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", ++ readl(host->ioaddr + SDHCI_ADMA_ERROR), ++ readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); ++ + printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n"); + } + +@@ -318,16 +323,25 @@ + { + int direction; + ++#if !defined(CONFIG_MMC_SDHCI_S3C) && !defined(CONFIG_MMC_SDHCI_MODULE) + u8 *desc; ++#else ++ struct sdhci_adma2_desc *descriptor; ++#endif + u8 *align; + dma_addr_t addr; + dma_addr_t align_addr; +- int len, offset; ++ uint len; ++#if !defined(CONFIG_MMC_SDHCI_S3C) && !defined(CONFIG_MMC_SDHCI_MODULE) ++ int offset; ++#endif + + struct scatterlist *sg; + int i; ++#if !defined(CONFIG_MMC_SDHCI_S3C) && !defined(CONFIG_MMC_SDHCI_MODULE) + char *buffer; + unsigned long flags; ++#endif + + /* + * The spec does not specify endianness of descriptor table. +@@ -355,7 +369,11 @@ + if (host->sg_count == 0) + goto unmap_align; + ++#if !defined(CONFIG_MMC_SDHCI_S3C) && !defined(CONFIG_MMC_SDHCI_MODULE) + desc = host->adma_desc; ++#else ++ descriptor = (struct sdhci_adma2_desc *)host->adma_desc; ++#endif + align = host->align_buffer; + + align_addr = host->align_addr; +@@ -364,6 +382,7 @@ + addr = sg_dma_address(sg); + len = sg_dma_len(sg); + ++#if !defined(CONFIG_MMC_SDHCI_S3C) && !defined(CONFIG_MMC_SDHCI_MODULE) + /* + * The SDHCI specification states that ADMA + * addresses must be 32-bit aligned. If they +@@ -422,8 +441,14 @@ + * somewhere. :/ + */ + WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4); ++#else ++ descriptor->dma_addr = addr; ++ descriptor->len_attr = (len << 16) | 0x21; ++ descriptor++; ++#endif + } + ++#if !defined(CONFIG_MMC_SDHCI_S3C) && !defined(CONFIG_MMC_SDHCI_MODULE) + /* + * Add a terminating entry. + */ +@@ -437,6 +462,10 @@ + + desc[1] = 0x00; + desc[0] = 0x03; /* nop, end, valid */ ++#else ++ descriptor--; ++ descriptor->len_attr |= 0x2; ++#endif + + /* + * Resync align buffer as we might have changed it. +@@ -547,6 +576,12 @@ + break; + } + ++#if defined(CONFIG_MMC_SDHCI_S3C) || defined(CONFIG_MMC_SDHCI_MODULE) ++ /* workaround for some MMCplus cards. */ ++ if (count == 0x0) ++ count = 0x7; ++#endif ++ + if (count >= 0xF) { + printk(KERN_WARNING "%s: Too large timeout requested!\n", + mmc_hostname(host->mmc)); +@@ -698,6 +733,7 @@ + writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); + } + ++ /* when using PIO mode sg_miter should be initialized. */ + if (!(host->flags & SDHCI_REQ_USE_DMA)) { + sg_miter_start(&host->sg_miter, + data->sg, data->sg_len, SG_MITER_ATOMIC); +@@ -731,6 +767,23 @@ + writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE); + } + ++static void shdci_check_dma_overrun(struct sdhci_host *host, struct mmc_data *data) ++{ ++ u32 dma_pos = readl(host->ioaddr + SDHCI_DMA_ADDRESS); ++ u32 dma_start = sg_dma_address(data->sg); ++ u32 dma_end = dma_start + data->sg->length; ++ ++ /* Test whether we ended up moving more data than ++ * was originally requested. */ ++ ++ if (dma_pos <= dma_end) ++ return; ++ ++ printk(KERN_ERR "%s: dma overrun, dma %08x, req %08x..%08x\n", ++ mmc_hostname(host->mmc), dma_pos, ++ dma_start, dma_end); ++} ++ + static void sdhci_finish_data(struct sdhci_host *host) + { + struct mmc_data *data; +@@ -744,6 +797,8 @@ + if (host->flags & SDHCI_USE_ADMA) + sdhci_adma_table_post(host, data); + else { ++ shdci_check_dma_overrun(host, data); ++ + dma_unmap_sg(mmc_dev(host->mmc), data->sg, + data->sg_len, (data->flags & MMC_DATA_READ) ? + DMA_FROM_DEVICE : DMA_TO_DEVICE); +@@ -883,13 +938,18 @@ + + static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) + { ++ if (clock == host->clock) ++ return; ++ ++ host->ops->change_clock(host, clock); ++} ++ ++void sdhci_change_clock(struct sdhci_host *host, unsigned int clock) ++{ + int div; + u16 clk; + unsigned long timeout; + +- if (clock == host->clock) +- return; +- + writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL); + + if (clock == 0) +@@ -926,6 +986,8 @@ + host->clock = clock; + } + ++EXPORT_SYMBOL_GPL(sdhci_change_clock); ++ + static void sdhci_set_power(struct sdhci_host *host, unsigned short power) + { + u8 pwr; +@@ -1000,13 +1062,16 @@ + + host->mrq = mrq; + ++ if ((mmc->caps & MMC_CAP_ON_BOARD) || (host->flags & SDHCI_DEVICE_ALIVE)) ++ sdhci_send_command(host, mrq->cmd); ++ else { + if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) + || (host->flags & SDHCI_DEVICE_DEAD)) { + host->mrq->cmd->error = -ENOMEDIUM; + tasklet_schedule(&host->finish_tasklet); + } else + sdhci_send_command(host, mrq->cmd); +- ++ } + mmiowb(); + spin_unlock_irqrestore(&host->lock, flags); + } +@@ -1033,6 +1098,9 @@ + sdhci_init(host); + } + ++ if (host->ops->set_ios) ++ host->ops->set_ios(host, ios); ++ + sdhci_set_clock(host, ios->clock); + + if (ios->power_mode == MMC_POWER_OFF) +@@ -1283,11 +1351,24 @@ + * controllers. + */ + if (host->cmd->flags & MMC_RSP_BUSY) { ++ u32 present; ++ + if (host->cmd->data) + DBG("Cannot wait for busy signal when also " + "doing a data transfer"); +- else ++ else if (!(host->quirks & SDHCI_QUIRK_NO_TCIRQ_ON_NOT_BUSY)) + return; ++ ++ /* The Samsung SDHCI does not seem to provide an INT_DATA_END ++ * when the system goes non-busy, so check the state of the ++ * transfer by reading SDHCI_PRESENT_STATE to see if the ++ * controller is ready ++ */ ++ ++ present = readl(host->ioaddr + SDHCI_PRESENT_STATE); ++ DBG("busy? present %08x, intstat %08x\n", present, intmask); ++ ++ /* fall through and take the SDHCI_INT_RESPONSE */ + } + + if (intmask & SDHCI_INT_RESPONSE) +@@ -1384,6 +1465,18 @@ + intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); + + if (intmask & SDHCI_INT_CMD_MASK) { ++#if defined(CONFIG_MMC_SDHCI_S3C) || defined(CONFIG_MMC_SDHCI_MODULE) ++ /* read until all status bit is up. by scsuh */ ++ int i; ++ for (i=0; i<0x1000000; i++) { ++ intmask = readl(host->ioaddr + SDHCI_INT_STATUS); ++ if (intmask & SDHCI_INT_RESPONSE) ++ break; ++ } ++ if (0x1000000 == i) { ++ printk("FAIL: waiting for status update.\n"); ++ } ++#endif + writel(intmask & SDHCI_INT_CMD_MASK, + host->ioaddr + SDHCI_INT_STATUS); + sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); +@@ -1604,15 +1697,21 @@ + mmc_dev(host->mmc)->dma_mask = &host->dma_mask; + } + +- host->max_clk = +- (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; ++ if (host->ops->get_max_clock) ++ host->max_clk = host->ops->get_max_clock(host); ++ else { ++ host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; ++ host->max_clk *= 1000000; ++ } + if (host->max_clk == 0) { + printk(KERN_ERR "%s: Hardware doesn't specify base clock " + "frequency.\n", mmc_hostname(mmc)); + return -ENODEV; + } +- host->max_clk *= 1000000; + ++ if (host->ops->get_timeout_clock) ++ host->timeout_clk = host->ops->get_timeout_clock(host); ++ else + host->timeout_clk = + (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; + if (host->timeout_clk == 0) { +@@ -1629,11 +1728,14 @@ + mmc->ops = &sdhci_ops; + mmc->f_min = host->max_clk / 256; + mmc->f_max = host->max_clk; ++#if defined(CONFIG_MMC_SDHCI_S3C) || defined(CONFIG_MMC_SDHCI_MODULE) ++ mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; ++#else + mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; +- ++#endif + if ((caps & SDHCI_CAN_DO_HISPD) || + (host->quirks & SDHCI_QUIRK_FORCE_HIGHSPEED)) +- mmc->caps |= MMC_CAP_SD_HIGHSPEED; ++ mmc->caps |= (MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED); + + mmc->ocr_avail = 0; + if (caps & SDHCI_CAN_VDD_330) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/mmc/host/sdhci.h linux-2.6.28.6/drivers/mmc/host/sdhci.h +--- linux-2.6.28/drivers/mmc/host/sdhci.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/mmc/host/sdhci.h 2009-04-30 09:36:38.000000000 +0200 +@@ -57,6 +57,7 @@ + #define SDHCI_DATA_AVAILABLE 0x00000800 + #define SDHCI_CARD_PRESENT 0x00010000 + #define SDHCI_WRITE_PROTECT 0x00080000 ++#define SDHCI_DATA_BIT(x) (1 << ((x) + 20)) + + #define SDHCI_HOST_CONTROL 0x28 + #define SDHCI_CTRL_LED 0x01 +@@ -210,6 +211,8 @@ + #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) + /* Controller supports high speed but doesn't have the caps bit set */ + #define SDHCI_QUIRK_FORCE_HIGHSPEED (1<<14) ++/* Controller does not provide transfer-complete interrupt when not busy */ ++#define SDHCI_QUIRK_NO_TCIRQ_ON_NOT_BUSY (1<<15) + + int irq; /* Device IRQ */ + void __iomem * ioaddr; /* Mapped address */ +@@ -231,6 +234,7 @@ + #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ + #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ + #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ ++#define SDHCI_DEVICE_ALIVE (1<<4) /* used on ext card detect */ + + unsigned int version; /* SDHCI spec. version */ + +@@ -264,9 +268,22 @@ + unsigned long private[0] ____cacheline_aligned; + }; + ++/* For ADMA2 */ ++struct sdhci_adma2_desc { ++ u32 len_attr; /* length + attribute */ ++ u32 dma_addr; /* dma address */ ++}; + + struct sdhci_ops { + int (*enable_dma)(struct sdhci_host *host); ++ unsigned int (*get_max_clock)(struct sdhci_host *host); ++ unsigned int (*get_timeout_clock)(struct sdhci_host *host); ++ ++ void (*change_clock)(struct sdhci_host *host, ++ unsigned int clock); ++ ++ void (*set_ios)(struct sdhci_host *host, ++ struct mmc_ios *ios); + }; + + +@@ -274,6 +291,8 @@ + size_t priv_size); + extern void sdhci_free_host(struct sdhci_host *host); + ++extern void sdhci_change_clock(struct sdhci_host *host, unsigned int clock); ++ + static inline void *sdhci_priv(struct sdhci_host *host) + { + return (void *)host->private; +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/mtd/nand/Kconfig linux-2.6.28.6/drivers/mtd/nand/Kconfig +--- linux-2.6.28/drivers/mtd/nand/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/mtd/nand/Kconfig 2009-04-30 09:36:38.000000000 +0200 +@@ -173,6 +173,34 @@ + when the is NAND chip selected or released, but will save + approximately 5mA of power when there is nothing happening. + ++config MTD_NAND_S3C ++ tristate "NAND Flash support for S3C SoC" ++ depends on (ARCH_S3C64XX || ARCH_S5P64XX || ARCH_S5PC1XX) && MTD_NAND ++ help ++ This enables the NAND flash controller on the S3C. ++ ++ No board specfic support is done by this driver, each board ++ must advertise a platform_device for the driver to attach. ++ ++config MTD_NAND_S3C_DEBUG ++ bool "S3C NAND driver debug" ++ depends on MTD_NAND_S3C ++ help ++ Enable debugging of the S3C NAND driver ++ ++config MTD_NAND_S3C_HWECC ++ bool "S3C NAND Hardware ECC" ++ depends on MTD_NAND_S3C ++ help ++ Enable the use of the S3C's internal ECC generator when ++ using NAND. Early versions of the chip have had problems with ++ incorrect ECC generation, and if using these, the default of ++ software ECC is preferable. ++ ++ If you lay down a device with the hardware ECC, then you will ++ currently not be able to switch to software, as there is no ++ implementation for ECC method used by the S3C ++ + config MTD_NAND_DISKONCHIP + tristate "DiskOnChip 2000, Millennium and Millennium Plus (NAND reimplementation) (EXPERIMENTAL)" + depends on EXPERIMENTAL +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/mtd/nand/Makefile linux-2.6.28.6/drivers/mtd/nand/Makefile +--- linux-2.6.28/drivers/mtd/nand/Makefile 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/mtd/nand/Makefile 2009-04-30 09:36:38.000000000 +0200 +@@ -14,6 +14,7 @@ + obj-$(CONFIG_MTD_NAND_BF5XX) += bf5xx_nand.o + obj-$(CONFIG_MTD_NAND_PPCHAMELEONEVB) += ppchameleonevb.o + obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o ++obj-$(CONFIG_MTD_NAND_S3C) += s3c_nand.o + obj-$(CONFIG_MTD_NAND_DISKONCHIP) += diskonchip.o + obj-$(CONFIG_MTD_NAND_H1900) += h1910.o + obj-$(CONFIG_MTD_NAND_RTC_FROM4) += rtc_from4.o +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/mtd/nand/s3c2410.c linux-2.6.28.6/drivers/mtd/nand/s3c2410.c +--- linux-2.6.28/drivers/mtd/nand/s3c2410.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/mtd/nand/s3c2410.c 2009-04-30 09:36:38.000000000 +0200 +@@ -45,8 +45,8 @@ + + #include + +-#include +-#include ++#include ++#include + + #ifdef CONFIG_MTD_NAND_S3C2410_HWECC + static int hardware_ecc = 1; +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/mtd/nand/s3c_nand.c linux-2.6.28.6/drivers/mtd/nand/s3c_nand.c +--- linux-2.6.28/drivers/mtd/nand/s3c_nand.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/mtd/nand/s3c_nand.c 2010-04-22 06:13:29.000000000 +0200 +@@ -0,0 +1,989 @@ ++/* linux/drivers/mtd/nand/s3c_nand.c ++ * ++ * Copyright (c) 2007 Samsung Electronics ++ * ++ * Samsung S3C NAND driver ++ * ++ * $Id: s3c_nand.c,v 1.3 2008/11/19 10:07:24 jsgood Exp $ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * Based on nand driver from Ben Dooks ++ * modified by scsuh. based on au1550nd.c ++ * ++ * Many functions for hardware ecc are implemented by jsgood. ++ */ ++ ++/* Simple H/W Table for Implementation of S3C nand driver ++ * by scsuh ++ * ------------------------------------------------------------------ ++ * | En/Dis CE | required | | ++ * | En/Dis ALE | X | * nand controller does | ++ * | En/Dis CLE | X | * nand controller does | ++ * | Wait/Ready | required | | ++ * | Write Command | required | | ++ * | Write Address | required | | ++ * | Write Data | required | | ++ * | Read Data | required | | ++ * | WP on/off | required | * board specific | ++ * | AP Specific Init | required | | ++ * ------------------------------------------------------------------ ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++ ++enum s3c_cpu_type { ++ TYPE_S3C2450, /* including s3c2416 */ ++ TYPE_S3C6400, ++ TYPE_S3C6410, /* including s3c6430/31 */ ++ TYPE_S5PC100, ++}; ++ ++struct s3c_nand_info { ++ /* mtd info */ ++ struct nand_hw_control controller; ++ struct s3c_nand_mtd_info *mtds; ++ struct s3c2410_platform_nand *platform; ++ ++ /* device info */ ++ struct device *device; ++ struct resource *area; ++ struct clk *clk; ++ void __iomem *regs; ++ void __iomem *sel_reg; ++ int sel_bit; ++ int mtd_count; ++ ++ enum s3c_cpu_type cpu_type; ++}; ++static struct s3c_nand_info s3c_nand; ++ ++static struct mtd_info *s3c_mtd = NULL; ++ ++/* Nand flash definition values by jsgood */ ++#define S3C_NAND_TYPE_UNKNOWN 0x0 ++#define S3C_NAND_TYPE_SLC 0x1 ++#define S3C_NAND_TYPE_MLC 0x2 ++ ++/* ++ * Cached progamming disabled for now, Not sure if its worth the ++ * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s) ++ * ++ * if want to use cached program, define next ++ * by jsgood (modified to keep prevent rule) ++ */ ++#undef CONFIG_MTD_NAND_S3C_CACHEDPROG ++ ++/* Nand flash global values by jsgood */ ++int cur_ecc_mode = 0; ++int nand_type = S3C_NAND_TYPE_UNKNOWN; ++ ++#if defined(CONFIG_MTD_NAND_S3C_HWECC) ++/* Nand flash oob definition for SLC 512b page size by jsgood */ ++static struct nand_ecclayout s3c_nand_oob_16 = { ++ .eccbytes = 4, ++ .eccpos = {1, 2, 3, 4}, ++ .oobfree = { ++ {.offset = 6, ++ .length = 10}} ++}; ++ ++/* Nand flash oob definition for SLC 2k page size by jsgood */ ++static struct nand_ecclayout s3c_nand_oob_64 = { ++ .eccbytes = 16, ++ .eccpos = {40, 41, 42, 43, 44, 45, 46, 47, ++ 48, 49, 50, 51, 52, 53, 54, 55}, ++ .oobfree = { ++ {.offset = 2, ++ .length = 38}} ++}; ++ ++/* Nand flash oob definition for MLC 2k page size by jsgood */ ++static struct nand_ecclayout s3c_nand_oob_mlc_64 = { ++ .eccbytes = 32, ++ .eccpos = { ++ 32, 33, 34, 35, 36, 37, 38, 39, ++ 40, 41, 42, 43, 44, 45, 46, 47, ++ 48, 49, 50, 51, 52, 53, 54, 55, ++ 56, 57, 58, 59, 60, 61, 62, 63}, ++ .oobfree = { ++ {.offset = 2, ++ .length = 28}} ++}; ++#endif ++ ++#if defined(CONFIG_MTD_NAND_S3C_DEBUG) ++/* ++ * Function to print out oob buffer for debugging ++ * Written by jsgood ++ */ ++void print_oob(const char *header, struct mtd_info *mtd) ++{ ++ int i; ++ struct nand_chip *chip = mtd->priv; ++ ++ printk("%s:\t", header); ++ ++ for(i = 0; i < 64; i++) ++ printk("%02x ", chip->oob_poi[i]); ++ ++ printk("\n"); ++} ++EXPORT_SYMBOL(print_oob); ++#endif ++ ++ ++/* ++ * Hardware specific access to control-lines function ++ * Written by jsgood ++ */ ++static void s3c_nand_hwcontrol(struct mtd_info *mtd, int dat, unsigned int ctrl) ++{ ++ unsigned int cur; ++ void __iomem *regs = s3c_nand.regs; ++ ++ if (ctrl & NAND_CTRL_CHANGE) { ++ if (ctrl & NAND_NCE) { ++ if (dat != NAND_CMD_NONE) { ++ cur = readl(regs + S3C_NFCONT); ++ cur &= ~S3C_NFCONT_nFCE0; ++ writel(cur, regs + S3C_NFCONT); ++ } ++ } else { ++ cur = readl(regs + S3C_NFCONT); ++ cur |= S3C_NFCONT_nFCE0; ++ writel(cur, regs + S3C_NFCONT); ++ } ++ } ++ ++ if (dat != NAND_CMD_NONE) { ++ if (ctrl & NAND_CLE) ++ writeb(dat, regs + S3C_NFCMMD); ++ else if (ctrl & NAND_ALE) ++ writeb(dat, regs + S3C_NFADDR); ++ } ++} ++ ++/* ++ * Function for checking device ready pin ++ * Written by jsgood ++ */ ++static int s3c_nand_device_ready(struct mtd_info *mtd) ++{ ++ void __iomem *regs = s3c_nand.regs; ++/* it's to check the RnB nand signal bit and return to device ready condition in nand_base.c */ ++ return ((readl(regs + S3C_NFSTAT) & S3C_NFSTAT_BUSY)); ++} ++ ++/* ++ * We don't use a bad block table ++ */ ++static int s3c_nand_scan_bbt(struct mtd_info *mtdinfo) ++{ ++ return 0; ++} ++ ++#if defined(CONFIG_MTD_NAND_S3C_HWECC) ++#if 0 ++/* ++ * S3C Nand flash chip enable function ++ * Written by jsgood ++ */ ++static void s3c_nand_ce_on(struct mtd_info *mtd) ++{ ++ struct nand_chip *chip = mtd->priv; ++ ++ chip->cmd_ctrl(mtd, 0x0, NAND_NCE | NAND_CTRL_CHANGE); ++ nand_wait_ready(mtd); ++} ++ ++/* ++ * S3C Nand flash chip disable function ++ * Written by jsgood ++ */ ++static void s3c_nand_ce_off(struct mtd_info *mtd) ++{ ++ struct nand_chip *chip = mtd->priv; ++ ++ chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_CTRL_CHANGE); ++ nand_wait_ready(mtd); ++} ++#endif ++ ++/* ++ * Function for checking ECCEncDone in NFSTAT ++ * Written by jsgood ++ */ ++static void s3c_nand_wait_enc(void) ++{ ++ void __iomem *regs = s3c_nand.regs; ++ unsigned long timeo = jiffies; ++ ++ timeo += 16; /* when Hz=200, jiffies interval 1/200=5mS, waiting for 80mS 80/5 = 16 */ ++ ++ /* Apply this short delay always to ensure that we do wait tWB in ++ * any case on any machine. */ ++ ++ while (time_before(jiffies, timeo)) { ++ if (readl(regs + S3C_NFSTAT) & S3C_NFSTAT_ECCENCDONE) ++ break; ++ cond_resched(); ++ } ++} ++ ++/* ++ * Function for checking ECCDecDone in NFSTAT ++ * Written by jsgood ++ */ ++static void s3c_nand_wait_dec(void) ++{ ++ void __iomem *regs = s3c_nand.regs; ++ unsigned long timeo = jiffies; ++ ++ timeo += 16; /* when Hz=200, jiffies interval 1/200=5mS, waiting for 80mS 80/5 = 16 */ ++ ++ /* Apply this short delay always to ensure that we do wait tWB in ++ * any case on any machine. */ ++ ++ while (time_before(jiffies, timeo)) { ++ if (readl(regs + S3C_NFSTAT) & S3C_NFSTAT_ECCDECDONE) ++ break; ++ cond_resched(); ++ } ++} ++ ++/* ++ * Function for checking ECC Busy ++ * Written by jsgood ++ */ ++static void s3c_nand_wait_ecc_busy(void) ++{ ++ void __iomem *regs = s3c_nand.regs; ++ unsigned long timeo = jiffies; ++ ++ timeo += 16; /* when Hz=200, jiffies interval 1/200=5mS, waiting for 80mS 80/5 = 16 */ ++ ++ /* Apply this short delay always to ensure that we do wait tWB in ++ * any case on any machine. */ ++ ++ while (time_before(jiffies, timeo)) { ++ if (!(readl(regs + S3C_NFMECCERR0) & S3C_NFECCERR0_ECCBUSY)) ++ break; ++ cond_resched(); ++ } ++} ++ ++/* ++ * This function is called before encoding ecc codes to ready ecc engine. ++ * Written by jsgood ++ */ ++static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode) ++{ ++ u_long nfcont; ++ u_long nfconf; ++ void __iomem *regs = s3c_nand.regs; ++ ++ cur_ecc_mode = mode; ++ ++ nfconf = readl(regs + S3C_NFCONF); ++ ++ if (s3c_nand.cpu_type == TYPE_S3C6400) { ++ if (nand_type == S3C_NAND_TYPE_SLC) ++ nfconf &= ~S3C_NFCONF_ECC_MLC; /* SLC */ ++ else ++ nfconf |= S3C_NFCONF_ECC_MLC; /* MLC */ ++ } else { ++ nfconf &= ~(0x3 << 23); ++ ++ if (nand_type == S3C_NAND_TYPE_SLC) ++ nfconf |= S3C_NFCONF_ECC_1BIT; ++ else ++ nfconf |= S3C_NFCONF_ECC_4BIT; ++ } ++ ++ writel(nfconf, regs + S3C_NFCONF); ++ ++ /* Init main ECC & unlock */ ++ nfcont = readl(regs + S3C_NFCONT); ++ nfcont |= S3C_NFCONT_INITMECC; ++ nfcont &= ~S3C_NFCONT_MECCLOCK; ++ ++ if (nand_type == S3C_NAND_TYPE_MLC) { ++ if (mode == NAND_ECC_WRITE) ++ nfcont |= S3C_NFCONT_ECC_ENC; ++ else if (mode == NAND_ECC_READ) ++ nfcont &= ~S3C_NFCONT_ECC_ENC; ++ } ++ ++ writel(nfcont, regs + S3C_NFCONT); ++} ++ ++/* ++ * This function is called immediately after encoding ecc codes. ++ * This function returns encoded ecc codes. ++ * Written by jsgood ++ */ ++static int s3c_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) ++{ ++ u_long nfcont, nfmecc0, nfmecc1; ++ void __iomem *regs = s3c_nand.regs; ++ ++ /* Lock */ ++ nfcont = readl(regs + S3C_NFCONT); ++ nfcont |= S3C_NFCONT_MECCLOCK; ++ writel(nfcont, regs + S3C_NFCONT); ++ ++ if (nand_type == S3C_NAND_TYPE_SLC) { ++ nfmecc0 = readl(regs + S3C_NFMECC0); ++ ++ ecc_code[0] = nfmecc0 & 0xff; ++ ecc_code[1] = (nfmecc0 >> 8) & 0xff; ++ ecc_code[2] = (nfmecc0 >> 16) & 0xff; ++ ecc_code[3] = (nfmecc0 >> 24) & 0xff; ++ } else { ++ if (cur_ecc_mode == NAND_ECC_READ) ++ s3c_nand_wait_dec(); ++ else { ++ s3c_nand_wait_enc(); ++ ++ nfmecc0 = readl(regs + S3C_NFMECC0); ++ nfmecc1 = readl(regs + S3C_NFMECC1); ++ ++ ecc_code[0] = nfmecc0 & 0xff; ++ ecc_code[1] = (nfmecc0 >> 8) & 0xff; ++ ecc_code[2] = (nfmecc0 >> 16) & 0xff; ++ ecc_code[3] = (nfmecc0 >> 24) & 0xff; ++ ecc_code[4] = nfmecc1 & 0xff; ++ ecc_code[5] = (nfmecc1 >> 8) & 0xff; ++ ecc_code[6] = (nfmecc1 >> 16) & 0xff; ++ ecc_code[7] = (nfmecc1 >> 24) & 0xff; ++ } ++ } ++ ++ return 0; ++} ++ ++/* ++ * This function determines whether read data is good or not. ++ * If SLC, must write ecc codes to controller before reading status bit. ++ * If MLC, status bit is already set, so only reading is needed. ++ * If status bit is good, return 0. ++ * If correctable errors occured, do that. ++ * If uncorrectable errors occured, return -1. ++ * Written by jsgood ++ */ ++static int s3c_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) ++{ ++ int ret = -1; ++ u_long nfestat0, nfestat1, nfmeccdata0, nfmeccdata1, nfmlcbitpt; ++ u_char err_type; ++ void __iomem *regs = s3c_nand.regs; ++ ++ if (!dat) { ++ printk("No page data\n"); ++ return ret; ++ } ++ ++ if (nand_type == S3C_NAND_TYPE_SLC) { ++ /* SLC: Write ECC data to compare */ ++ nfmeccdata0 = (read_ecc[1] << 16) | read_ecc[0]; ++ nfmeccdata1 = (read_ecc[3] << 16) | read_ecc[2]; ++ writel(nfmeccdata0, regs + S3C_NFMECCDATA0); ++ writel(nfmeccdata1, regs + S3C_NFMECCDATA1); ++ ++ /* Read ECC status */ ++ nfestat0 = readl(regs + S3C_NFMECCERR0); ++ err_type = nfestat0 & 0x3; ++ ++ switch (err_type) { ++ case 0: /* No error */ ++ ret = 0; ++ break; ++ ++ case 1: /* 1 bit error (Correctable) ++ (nfestat0 >> 7) & 0x7ff :error byte number ++ (nfestat0 >> 4) & 0x7 :error bit number */ ++ printk("s3c-nand: 1 bit error detected at byte %ld, correcting from " ++ "0x%02x ", (nfestat0 >> 7) & 0x7ff, dat[(nfestat0 >> 7) & 0x7ff]); ++ dat[(nfestat0 >> 7) & 0x7ff] ^= (1 << ((nfestat0 >> 4) & 0x7)); ++ printk("to 0x%02x...OK\n", dat[(nfestat0 >> 7) & 0x7ff]); ++ ret = 1; ++ break; ++ ++ case 2: /* Multiple error */ ++ case 3: /* ECC area error */ ++ //printk("s3c-nand: ECC uncorrectable error detected\n"); ++ ret = -1; ++ break; ++ } ++ } else { ++ /* MLC: */ ++ s3c_nand_wait_ecc_busy(); ++ ++ nfestat0 = readl(regs + S3C_NFMECCERR0); ++ nfestat1 = readl(regs + S3C_NFMECCERR1); ++ nfmlcbitpt = readl(regs + S3C_NFMLCBITPT); ++ ++ err_type = (nfestat0 >> 26) & 0x7; ++ ++ /* No error, If free page (all 0xff) */ ++ if ((nfestat0 >> 29) & 0x1) { ++ err_type = 0; ++ } else { ++ /* No error, If all 0xff from 17th byte in oob (in case of JFFS2 format) */ ++ if (dat) { ++ if (dat[17] == 0xff && dat[26] == 0xff && dat[35] == 0xff && dat[44] == 0xff && dat[54] == 0xff) ++ err_type = 0; ++ } ++ } ++ ++ switch (err_type) { ++ case 5: /* Uncorrectable */ ++ //printk("s3c-nand: ECC uncorrectable error detected\n"); ++ ret = -1; ++ break; ++ ++ case 4: /* 4 bit error (Correctable) */ ++ dat[(nfestat1 >> 16) & 0x3ff] ^= ((nfmlcbitpt >> 24) & 0xff); ++ ++ case 3: /* 3 bit error (Correctable) */ ++ dat[nfestat1 & 0x3ff] ^= ((nfmlcbitpt >> 16) & 0xff); ++ ++ case 2: /* 2 bit error (Correctable) */ ++ dat[(nfestat0 >> 16) & 0x3ff] ^= ((nfmlcbitpt >> 8) & 0xff); ++ ++ case 1: /* 1 bit error (Correctable) */ ++ printk("s3c-nand: %d bit(s) error detected, corrected successfully\n", err_type); ++ dat[nfestat0 & 0x3ff] ^= (nfmlcbitpt & 0xff); ++ ret = err_type; ++ break; ++ ++ case 0: /* No error */ ++ ret = 0; ++ break; ++ } ++ } ++ ++ return ret; ++} ++ ++static int s3c_nand_write_oob_1bit(struct mtd_info *mtd, struct nand_chip *chip, ++ int page) ++{ ++ uint8_t *ecc_calc = chip->buffers->ecccalc; ++ int status = 0; ++ int eccbytes = chip->ecc.bytes; ++ int secc_start = mtd->oobsize - eccbytes; ++ int i; ++ ++ chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); ++ ++ /* spare area */ ++ chip->ecc.hwctl(mtd, NAND_ECC_WRITE); ++ chip->write_buf(mtd, chip->oob_poi, secc_start); ++ chip->ecc.calculate(mtd, 0, &ecc_calc[chip->ecc.total]); ++ ++ for (i = 0; i < eccbytes; i++) ++ chip->oob_poi[secc_start + i] = ecc_calc[chip->ecc.total + i]; ++ ++ chip->write_buf(mtd, chip->oob_poi + secc_start, eccbytes); ++ ++ /* Send command to program the OOB data */ ++ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); ++ ++ status = chip->waitfunc(mtd, chip); ++ ++ return status & NAND_STATUS_FAIL ? -EIO : 0; ++} ++ ++static int s3c_nand_read_oob_1bit(struct mtd_info *mtd, struct nand_chip *chip, ++ int page, int sndcmd) ++{ ++ uint8_t *ecc_calc = chip->buffers->ecccalc; ++ int eccbytes = chip->ecc.bytes; ++ int secc_start = mtd->oobsize - eccbytes; ++ ++ if (sndcmd) { ++ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); ++ sndcmd = 0; ++ } ++ ++ chip->ecc.hwctl(mtd, NAND_ECC_READ); ++ chip->read_buf(mtd, chip->oob_poi, secc_start); ++ chip->ecc.calculate(mtd, 0, &ecc_calc[chip->ecc.total]); ++ chip->read_buf(mtd, chip->oob_poi + secc_start, eccbytes); ++ ++ /* jffs2 special case */ ++ if (!(chip->oob_poi[2] == 0x85 && chip->oob_poi[3] == 0x19)) ++ chip->ecc.correct(mtd, chip->oob_poi, chip->oob_poi + secc_start, 0); ++ ++ return sndcmd; ++} ++ ++static void s3c_nand_write_page_1bit(struct mtd_info *mtd, struct nand_chip *chip, ++ const uint8_t *buf) ++{ ++ int i, eccsize = chip->ecc.size; ++ int eccbytes = chip->ecc.bytes; ++ int eccsteps = chip->ecc.steps; ++ int secc_start = mtd->oobsize - eccbytes; ++ uint8_t *ecc_calc = chip->buffers->ecccalc; ++ const uint8_t *p = buf; ++ ++ uint32_t *eccpos = chip->ecc.layout->eccpos; ++ ++ /* main area */ ++ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { ++ chip->ecc.hwctl(mtd, NAND_ECC_WRITE); ++ chip->write_buf(mtd, p, eccsize); ++ chip->ecc.calculate(mtd, p, &ecc_calc[i]); ++ } ++ ++ for (i = 0; i < chip->ecc.total; i++) ++ chip->oob_poi[eccpos[i]] = ecc_calc[i]; ++ ++ /* spare area */ ++ chip->ecc.hwctl(mtd, NAND_ECC_WRITE); ++ chip->write_buf(mtd, chip->oob_poi, secc_start); ++ chip->ecc.calculate(mtd, p, &ecc_calc[chip->ecc.total]); ++ ++ for (i = 0; i < eccbytes; i++) ++ chip->oob_poi[secc_start + i] = ecc_calc[chip->ecc.total + i]; ++ ++ chip->write_buf(mtd, chip->oob_poi + secc_start, eccbytes); ++} ++ ++static int s3c_nand_read_page_1bit(struct mtd_info *mtd, struct nand_chip *chip, ++ uint8_t *buf) ++{ ++ int i, stat, eccsize = chip->ecc.size; ++ int eccbytes = chip->ecc.bytes; ++ int eccsteps = chip->ecc.steps; ++ int secc_start = mtd->oobsize - eccbytes; ++ int col = 0; ++ uint8_t *p = buf; ++ uint32_t *mecc_pos = chip->ecc.layout->eccpos; ++ uint8_t *ecc_calc = chip->buffers->ecccalc; ++ ++ col = mtd->writesize; ++ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1); ++ ++ /* spare area */ ++ chip->ecc.hwctl(mtd, NAND_ECC_READ); ++ chip->read_buf(mtd, chip->oob_poi, secc_start); ++ chip->ecc.calculate(mtd, p, &ecc_calc[chip->ecc.total]); ++ chip->read_buf(mtd, chip->oob_poi + secc_start, eccbytes); ++ ++ /* jffs2 special case */ ++ if (!(chip->oob_poi[2] == 0x85 && chip->oob_poi[3] == 0x19)) ++ chip->ecc.correct(mtd, chip->oob_poi, chip->oob_poi + secc_start, 0); ++ ++ col = 0; ++ ++ /* main area */ ++ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { ++ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1); ++ chip->ecc.hwctl(mtd, NAND_ECC_READ); ++ chip->read_buf(mtd, p, eccsize); ++ chip->ecc.calculate(mtd, p, &ecc_calc[i]); ++ ++ stat = chip->ecc.correct(mtd, p, chip->oob_poi + mecc_pos[0] + ((chip->ecc.steps - eccsteps) * eccbytes), 0); ++ if (stat == -1) ++ mtd->ecc_stats.failed++; ++ ++ col = eccsize * (chip->ecc.steps + 1 - eccsteps); ++ } ++ ++ return 0; ++} ++ ++/* ++ * Hardware specific page read function for MLC. ++ * Written by jsgood ++ */ ++static int s3c_nand_read_page_4bit(struct mtd_info *mtd, struct nand_chip *chip, ++ uint8_t *buf) ++{ ++ int i, stat, eccsize = chip->ecc.size; ++ int eccbytes = chip->ecc.bytes; ++ int eccsteps = chip->ecc.steps; ++ int col = 0; ++ uint8_t *p = buf; ++ uint32_t *mecc_pos = chip->ecc.layout->eccpos; ++ ++ /* Step1: read whole oob */ ++ col = mtd->writesize; ++ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1); ++ chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); ++ ++ col = 0; ++ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { ++ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1); ++ chip->ecc.hwctl(mtd, NAND_ECC_READ); ++ chip->read_buf(mtd, p, eccsize); ++ chip->write_buf(mtd, chip->oob_poi + mecc_pos[0] + ((chip->ecc.steps - eccsteps) * eccbytes), eccbytes); ++ chip->ecc.calculate(mtd, 0, 0); ++ stat = chip->ecc.correct(mtd, p, 0, 0); ++ ++ if (stat == -1) ++ mtd->ecc_stats.failed++; ++ ++ col = eccsize * (chip->ecc.steps + 1 - eccsteps); ++ } ++ ++ return 0; ++} ++ ++/* ++ * Hardware specific page write function for MLC. ++ * Written by jsgood ++ */ ++static void s3c_nand_write_page_4bit(struct mtd_info *mtd, struct nand_chip *chip, ++ const uint8_t *buf) ++{ ++ int i, eccsize = chip->ecc.size; ++ int eccbytes = chip->ecc.bytes; ++ int eccsteps = chip->ecc.steps; ++ const uint8_t *p = buf; ++ uint8_t *ecc_calc = chip->buffers->ecccalc; ++ uint32_t *mecc_pos = chip->ecc.layout->eccpos; ++ ++ /* Step1: write main data and encode mecc */ ++ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { ++ chip->ecc.hwctl(mtd, NAND_ECC_WRITE); ++ chip->write_buf(mtd, p, eccsize); ++ chip->ecc.calculate(mtd, p, &ecc_calc[i]); ++ } ++ ++ /* Step2: save encoded mecc */ ++ for (i = 0; i < chip->ecc.total; i++) ++ chip->oob_poi[mecc_pos[i]] = ecc_calc[i]; ++ ++ chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); ++} ++#endif ++ ++/* s3c_nand_probe ++ * ++ * called by device layer when it finds a device matching ++ * one our driver can handled. This code checks to see if ++ * it can allocate all necessary resources then calls the ++ * nand layer to look for devices ++ */ ++static int s3c_nand_probe(struct platform_device *pdev, enum s3c_cpu_type cpu_type) ++{ ++ struct s3c_nand_mtd_info *plat_info = pdev->dev.platform_data; ++ struct mtd_partition *partition_info = (struct mtd_partition *)plat_info->partition; ++ struct nand_chip *nand; ++ struct resource *res; ++ int err = 0; ++ int ret = 0; ++ int i, j, size; ++ ++#if defined(CONFIG_MTD_NAND_S3C_HWECC) ++ struct nand_flash_dev *type = NULL; ++ u_char tmp; ++#endif ++ ++ /* get the clock source and enable it */ ++ ++ s3c_nand.clk = clk_get(&pdev->dev, "nand"); ++ if (IS_ERR(s3c_nand.clk)) { ++ dev_err(&pdev->dev, "failed to get clock"); ++ err = -ENOENT; ++ goto exit_error; ++ } ++ ++ clk_enable(s3c_nand.clk); ++ ++ /* allocate and map the resource */ ++ ++ /* currently we assume we have the one resource */ ++ res = pdev->resource; ++ size = res->end - res->start + 1; ++ ++ s3c_nand.area = request_mem_region(res->start, size, pdev->name); ++ ++ if (s3c_nand.area == NULL) { ++ dev_err(&pdev->dev, "cannot reserve register region\n"); ++ err = -ENOENT; ++ goto exit_error; ++ } ++ ++ s3c_nand.cpu_type = cpu_type; ++ s3c_nand.device = &pdev->dev; ++ s3c_nand.regs = ioremap(res->start, size); ++ ++ if (s3c_nand.regs == NULL) { ++ dev_err(&pdev->dev, "cannot reserve register region\n"); ++ err = -EIO; ++ goto exit_error; ++ } ++ ++ /* allocate memory for MTD device structure and private data */ ++ s3c_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL); ++ ++ if (!s3c_mtd) { ++ printk("Unable to allocate NAND MTD dev structure.\n"); ++ return -ENOMEM; ++ } ++ ++ /* Get pointer to private data */ ++ nand = (struct nand_chip *) (&s3c_mtd[1]); ++ ++ /* Initialize structures */ ++ memset((char *) s3c_mtd, 0, sizeof(struct mtd_info)); ++ memset((char *) nand, 0, sizeof(struct nand_chip)); ++ ++ /* Link the private data with the MTD structure */ ++ s3c_mtd->priv = nand; ++ ++ for (i = 0; i < plat_info->chip_nr; i++) { ++ nand->IO_ADDR_R = (char *)(s3c_nand.regs + S3C_NFDATA); ++ nand->IO_ADDR_W = (char *)(s3c_nand.regs + S3C_NFDATA); ++ nand->cmd_ctrl = s3c_nand_hwcontrol; ++ nand->dev_ready = s3c_nand_device_ready; ++ nand->scan_bbt = s3c_nand_scan_bbt; ++ nand->options = 0; ++ ++#if defined(CONFIG_MTD_NAND_S3C_CACHEDPROG) ++ nand->options |= NAND_CACHEPRG; ++#endif ++ ++#if defined(CONFIG_MTD_NAND_S3C_HWECC) ++ nand->ecc.mode = NAND_ECC_HW; ++ nand->ecc.hwctl = s3c_nand_enable_hwecc; ++ nand->ecc.calculate = s3c_nand_calculate_ecc; ++ nand->ecc.correct = s3c_nand_correct_data; ++ ++ s3c_nand_hwcontrol(0, NAND_CMD_READID, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); ++ s3c_nand_hwcontrol(0, 0x00, NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE); ++ s3c_nand_hwcontrol(0, 0x00, NAND_NCE | NAND_ALE); ++ s3c_nand_hwcontrol(0, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); ++ s3c_nand_device_ready(0); ++ ++ tmp = readb(nand->IO_ADDR_R); /* Maf. ID */ ++ tmp = readb(nand->IO_ADDR_R); /* Device ID */ ++ ++ for (j = 0; nand_flash_ids[j].name != NULL; j++) { ++ if (tmp == nand_flash_ids[j].id) { ++ type = &nand_flash_ids[j]; ++ break; ++ } ++ } ++ ++ if (!type) { ++ printk("Unknown NAND Device.\n"); ++ goto exit_error; ++ } ++ ++ nand->cellinfo = readb(nand->IO_ADDR_R); /* the 3rd byte */ ++ tmp = readb(nand->IO_ADDR_R); /* the 4th byte */ ++ ++ if (!type->pagesize) { ++ if (((nand->cellinfo >> 2) & 0x3) == 0) { ++ nand_type = S3C_NAND_TYPE_SLC; ++ nand->ecc.size = 512; ++ nand->ecc.bytes = 4; ++ ++ if ((1024 << (tmp & 0x3)) > 512) { ++ nand->ecc.read_page = s3c_nand_read_page_1bit; ++ nand->ecc.write_page = s3c_nand_write_page_1bit; ++ nand->ecc.read_oob = s3c_nand_read_oob_1bit; ++ nand->ecc.write_oob = s3c_nand_write_oob_1bit; ++ nand->ecc.layout = &s3c_nand_oob_64; ++ } else { ++ nand->ecc.layout = &s3c_nand_oob_16; ++ } ++ } else { ++ nand_type = S3C_NAND_TYPE_MLC; ++ nand->options |= NAND_NO_SUBPAGE_WRITE; /* NOP = 1 if MLC */ ++ nand->ecc.read_page = s3c_nand_read_page_4bit; ++ nand->ecc.write_page = s3c_nand_write_page_4bit; ++ nand->ecc.size = 512; ++ nand->ecc.bytes = 8; /* really 7 bytes */ ++ nand->ecc.layout = &s3c_nand_oob_mlc_64; ++ } ++ } else { ++ nand_type = S3C_NAND_TYPE_SLC; ++ nand->ecc.size = 512; ++ nand->cellinfo = 0; ++ nand->ecc.bytes = 4; ++ nand->ecc.layout = &s3c_nand_oob_16; ++ } ++ ++ printk("S3C NAND Driver is using hardware ECC.\n"); ++#else ++ nand->ecc.mode = NAND_ECC_SOFT; ++ printk("S3C NAND Driver is using software ECC.\n"); ++#endif ++ if (nand_scan(s3c_mtd, 1)) { ++ ret = -ENXIO; ++ goto exit_error; ++ } ++ ++ /* Register the partitions */ ++ add_mtd_partitions(s3c_mtd, partition_info, plat_info->mtd_part_nr); ++ } ++ ++ pr_debug("initialized ok\n"); ++ return 0; ++ ++exit_error: ++ kfree(s3c_mtd); ++ ++ return ret; ++} ++ ++static int s3c2450_nand_probe(struct platform_device *dev) ++{ ++ return s3c_nand_probe(dev, TYPE_S3C2450); ++} ++ ++static int s3c6400_nand_probe(struct platform_device *dev) ++{ ++ return s3c_nand_probe(dev, TYPE_S3C6400); ++} ++ ++static int s3c6410_nand_probe(struct platform_device *dev) ++{ ++ return s3c_nand_probe(dev, TYPE_S3C6410); ++} ++ ++static int s5pc100_nand_probe(struct platform_device *dev) ++{ ++ return s3c_nand_probe(dev, TYPE_S5PC100); ++} ++ ++/* PM Support */ ++#if defined(CONFIG_PM) ++static int s3c_nand_suspend(struct platform_device *dev, pm_message_t pm) ++{ ++ struct s3c_nand *info = platform_get_drvdata(dev); ++ clk_disable(s3c_nand.clk); ++ return 0; ++} ++ ++static int s3c_nand_resume(struct platform_device *dev) ++{ ++ struct s3c_nand *info = platform_get_drvdata(dev); ++ clk_enable(s3c_nand.clk); ++ return 0; ++} ++ ++#else ++#define s3c_nand_suspend NULL ++#define s3c_nand_resume NULL ++#endif ++ ++/* device management functions */ ++static int s3c_nand_remove(struct platform_device *dev) ++{ ++ platform_set_drvdata(dev, NULL); ++ ++ return 0; ++} ++ ++static struct platform_driver s3c2450_nand_driver = { ++ .probe = s3c2450_nand_probe, ++ .remove = s3c_nand_remove, ++ .suspend = s3c_nand_suspend, ++ .resume = s3c_nand_resume, ++ .driver = { ++ .name = "s3c2450-nand", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct platform_driver s3c6400_nand_driver = { ++ .probe = s3c6400_nand_probe, ++ .remove = s3c_nand_remove, ++ .suspend = s3c_nand_suspend, ++ .resume = s3c_nand_resume, ++ .driver = { ++ .name = "s3c6400-nand", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct platform_driver s3c6410_nand_driver = { ++ .probe = s3c6410_nand_probe, ++ .remove = s3c_nand_remove, ++ .suspend = s3c_nand_suspend, ++ .resume = s3c_nand_resume, ++ .driver = { ++ .name = "s3c6410-nand", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct platform_driver s5pc100_nand_driver = { ++ .probe = s5pc100_nand_probe, ++ .remove = s3c_nand_remove, ++ .suspend = s3c_nand_suspend, ++ .resume = s3c_nand_resume, ++ .driver = { ++ .name = "s5pc100-nand", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init s3c_nand_init(void) ++{ ++ printk("S3C NAND Driver, (c) 2008 Samsung Electronics\n"); ++ ++ platform_driver_register(&s3c2450_nand_driver); ++ platform_driver_register(&s3c6400_nand_driver); ++ platform_driver_register(&s3c6410_nand_driver); ++ return platform_driver_register(&s5pc100_nand_driver); ++} ++ ++static void __exit s3c_nand_exit(void) ++{ ++ platform_driver_unregister(&s3c2450_nand_driver); ++ platform_driver_unregister(&s3c6400_nand_driver); ++ platform_driver_unregister(&s3c6410_nand_driver); ++ platform_driver_unregister(&s5pc100_nand_driver); ++} ++ ++module_init(s3c_nand_init); ++module_exit(s3c_nand_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Jinsung Yang "); ++MODULE_DESCRIPTION("S3C MTD NAND driver"); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/mtd/onenand/Makefile linux-2.6.28.6/drivers/mtd/onenand/Makefile +--- linux-2.6.28/drivers/mtd/onenand/Makefile 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/mtd/onenand/Makefile 2009-04-30 09:36:38.000000000 +0200 +@@ -3,7 +3,7 @@ + # + + # Core functionality. +-obj-$(CONFIG_MTD_ONENAND) += onenand.o ++obj-$(CONFIG_MTD_ONENAND) += onenand.o onenand_bbt.o + + # Board specific. + obj-$(CONFIG_MTD_ONENAND_GENERIC) += generic.o +@@ -12,4 +12,12 @@ + # Simulator + obj-$(CONFIG_MTD_ONENAND_SIM) += onenand_sim.o + +-onenand-objs = onenand_base.o onenand_bbt.o ++ifeq ($(CONFIG_CPU_S3C6400),y) ++onenand-objs = s3c_onenand.o ++else ifeq ($(CONFIG_CPU_S3C6410),y) ++onenand-objs = s3c_onenand.o ++else ifeq ($(CONFIG_CPU_S5PC100),y) ++onenand-objs = s3c_onenand.o ++else ++onenand-objs = onenand_base.o ++endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/mtd/onenand/generic.c linux-2.6.28.6/drivers/mtd/onenand/generic.c +--- linux-2.6.28/drivers/mtd/onenand/generic.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/mtd/onenand/generic.c 2009-04-30 09:36:38.000000000 +0200 +@@ -36,10 +36,9 @@ + struct onenand_chip onenand; + }; + +-static int __devinit generic_onenand_probe(struct device *dev) ++static int __devinit generic_onenand_probe(struct platform_device *pdev) + { + struct onenand_info *info; +- struct platform_device *pdev = to_platform_device(dev); + struct flash_platform_data *pdata = pdev->dev.platform_data; + struct resource *res = pdev->resource; + unsigned long size = res->end - res->start + 1; +@@ -49,7 +48,7 @@ + if (!info) + return -ENOMEM; + +- if (!request_mem_region(res->start, size, dev->driver->name)) { ++ if (!request_mem_region(res->start, size, pdev->name)) { + err = -EBUSY; + goto out_free_info; + } +@@ -96,9 +95,8 @@ + return err; + } + +-static int __devexit generic_onenand_remove(struct device *dev) ++static int __devexit generic_onenand_remove(struct platform_device *pdev) + { +- struct platform_device *pdev = to_platform_device(dev); + struct onenand_info *info = dev_get_drvdata(&pdev->dev); + struct resource *res = pdev->resource; + unsigned long size = res->end - res->start + 1; +@@ -120,23 +118,25 @@ + return 0; + } + +-static struct device_driver generic_onenand_driver = { +- .name = DRIVER_NAME, +- .bus = &platform_bus_type, ++static struct platform_driver generic_onenand_driver = { + .probe = generic_onenand_probe, + .remove = __devexit_p(generic_onenand_remove), ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ }, + }; + + MODULE_ALIAS(DRIVER_NAME); + + static int __init generic_onenand_init(void) + { +- return driver_register(&generic_onenand_driver); ++ return platform_driver_register(&generic_onenand_driver); + } + + static void __exit generic_onenand_exit(void) + { +- driver_unregister(&generic_onenand_driver); ++ platform_driver_unregister(&generic_onenand_driver); + } + + module_init(generic_onenand_init); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/mtd/onenand/onenand_bbt.c linux-2.6.28.6/drivers/mtd/onenand/onenand_bbt.c +--- linux-2.6.28/drivers/mtd/onenand/onenand_bbt.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/mtd/onenand/onenand_bbt.c 2009-04-30 09:36:38.000000000 +0200 +@@ -14,9 +14,16 @@ + + #include + #include ++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S5PC100) ++#include "s3c_onenand.h" ++#else + #include ++#endif ++ + #include + ++extern int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from, ++ struct mtd_oob_ops *ops); + /** + * check_short_pattern - [GENERIC] check if a pattern is in the buffer + * @param buf the buffer to search +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/mtd/onenand/s3c_onenand.c linux-2.6.28.6/drivers/mtd/onenand/s3c_onenand.c +--- linux-2.6.28/drivers/mtd/onenand/s3c_onenand.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/mtd/onenand/s3c_onenand.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,2657 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include "s3c_onenand.h" ++ ++#undef CONFIG_MTD_ONENAND_CHECK_SPEED ++#undef DEBUG_ONENAND ++ ++#ifdef CONFIG_MTD_ONENAND_CHECK_SPEED ++#include ++#endif ++ ++#ifdef DEBUG_ONENAND ++#define dbg(x...) printk(x) ++#else ++#define dbg(x...) do { } while (0) ++#endif ++ ++#if defined(CONFIG_CPU_S3C6400) ++#define onenand_phys_to_virt(x) (void __iomem *)(chip->dev_base + (x & 0xffffff)) ++#define onenand_virt_to_phys(x) (void __iomem *)(ONENAND_AHB_ADDR + (x & 0xffffff)) ++#elif defined(CONFIG_CPU_S5PC100) ++#define onenand_phys_to_virt(x) (void __iomem *)(chip->dev_base + (x & 0xfffffff)) ++#define onenand_virt_to_phys(x) (void __iomem *)(ONENAND_AHB_ADDR + (x & 0xfffffff)) ++#else ++#define onenand_phys_to_virt(x) (void __iomem *)(chip->dev_base + (x & 0x3ffffff)) ++#define onenand_virt_to_phys(x) (void __iomem *)(ONENAND_AHB_ADDR + (x & 0x3ffffff)) ++#endif ++ ++/** ++ * onenand_oob_64 - oob info for large (2KB) page ++ */ ++static struct nand_ecclayout onenand_oob_64 = { ++ .eccbytes = 20, ++ .eccpos = { ++ 8, 9, 10, 11, 12, ++ 24, 25, 26, 27, 28, ++ 40, 41, 42, 43, 44, ++ 56, 57, 58, 59, 60, ++ }, ++ ++ /* For YAFFS2 tag information */ ++ .oobfree = { ++ {2, 6}, {13, 3}, {18, 6}, {29, 3}, ++ {34, 6}, {45, 3}, {50, 6}, {61, 3}} ++#if 0 ++ .oobfree = { ++ {2, 6}, {14, 2}, {18, 6}, {30, 2}, ++ {34, 6}, {46, 2}, {50, 6}} ++ ++ .oobfree = { ++ {2, 3}, {14, 2}, {18, 3}, {30, 2}, ++ {34, 3}, {46, 2}, {50, 3}, {62, 2} ++ } ++#endif ++}; ++ ++/** ++ * onenand_oob_32 - oob info for middle (1KB) page ++ */ ++static struct nand_ecclayout onenand_oob_32 = { ++ .eccbytes = 10, ++ .eccpos = { ++ 8, 9, 10, 11, 12, ++ 24, 25, 26, 27, 28, ++ }, ++ .oobfree = { {2, 3}, {14, 2}, {18, 3}, {30, 2} } ++}; ++ ++static const unsigned char ffchars[] = { ++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 16 */ ++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 32 */ ++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 48 */ ++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, ++ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 64 */ ++}; ++ ++static int onenand_write_oob_nolock(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops); ++ ++ ++#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE ++static int onenand_verify_oob(struct mtd_info *mtd, const u_char *buf, loff_t to, size_t len); ++static int onenand_verify_ops(struct mtd_info *mtd, struct mtd_oob_ops *ops, loff_t to, size_t len); ++#endif ++ ++/** ++ * dma client ++ */ ++static struct s3c2410_dma_client s3c6400onenand_dma_client = { ++ .name = "s3c6400-onenand-dma", ++}; ++ ++static unsigned int onenand_readl(void __iomem *addr) ++{ ++ return readl(addr); ++} ++ ++static void onenand_writel(unsigned int value, void __iomem *addr) ++{ ++ writel(value, addr); ++} ++ ++static void onenand_irq_wait(struct onenand_chip *chip, int stat) ++{ ++ while (!chip->read(chip->base + ONENAND_REG_INT_ERR_STAT) & stat); ++} ++ ++static void onenand_irq_ack(struct onenand_chip *chip, int stat) ++{ ++ chip->write(stat, chip->base + ONENAND_REG_INT_ERR_ACK); ++} ++ ++static int onenand_irq_pend(struct onenand_chip *chip, int stat) ++{ ++ return (chip->read(chip->base + ONENAND_REG_INT_ERR_STAT) & stat); ++} ++ ++static void onenand_irq_wait_ack(struct onenand_chip *chip, int stat) ++{ ++ onenand_irq_wait(chip, stat); ++ onenand_irq_ack(chip, stat); ++} ++ ++static int onenand_blkrw_complete(struct onenand_chip *chip, int cmd) ++{ ++ int cmp_bit = 0, fail_bit = 0, ret = 0; ++ ++ if (cmd == ONENAND_CMD_READ) { ++ cmp_bit = ONENAND_INT_ERR_LOAD_CMP; ++ fail_bit = ONENAND_INT_ERR_LD_FAIL_ECC_ERR; ++ } else if (cmd == ONENAND_CMD_PROG) { ++ cmp_bit = ONENAND_INT_ERR_PGM_CMP; ++ fail_bit = ONENAND_INT_ERR_PGM_FAIL; ++ } else { ++ ret = 1; ++ } ++ ++ onenand_irq_wait_ack(chip, ONENAND_INT_ERR_INT_ACT); ++ onenand_irq_wait_ack(chip, ONENAND_INT_ERR_BLK_RW_CMP); ++ onenand_irq_wait_ack(chip, cmp_bit); ++ ++ if (onenand_irq_pend(chip, fail_bit)) { ++ onenand_irq_ack(chip, fail_bit); ++ ret = 1; ++ } ++ ++ return ret; ++} ++ ++/** ++ * onenand_read_burst ++ * ++ * 16 Burst read: performance is improved up to 40%. ++ */ ++static void onenand_read_burst(void *dest, const void *src, size_t len) ++{ ++ int count; ++ ++ if (len % 16 != 0) ++ return; ++ ++ count = len / 16; ++ ++ __asm__ __volatile__( ++ " stmdb r13!, {r0-r3,r9-r12}\n" ++ " mov r2, %0\n" ++ "read_page:\n" ++ " ldmia r1, {r9-r12}\n" ++ " stmia r0!, {r9-r12}\n" ++ " subs r2, r2, #0x1\n" ++ " bne read_page\n" ++ " ldmia r13!, {r0-r3,r9-r12}\n" ++ ::"r" (count)); ++} ++ ++/** ++ * ++ * onenand_dma_finish ++ * ++ */ ++void onenand_dma_finish(struct s3c2410_dma_chan *dma_ch, void *buf_id, ++ int size, enum s3c2410_dma_buffresult result) ++{ ++ struct onenand_chip *chip = (struct onenand_chip *) buf_id; ++ complete(chip->done); ++} ++ ++/** ++ * ++ * onenand_read_dma ++ * ++ */ ++#if 1 ++static void onenand_read_dma(struct onenand_chip *chip, unsigned int *dst, void __iomem *src, size_t len) ++{ ++ void __iomem *phys_addr = onenand_virt_to_phys((u_int) src); ++ ++ DECLARE_COMPLETION_ONSTACK(complete); ++ chip->done = &complete; ++ ++#if 0 ++ if (s3c_dma_request(chip->dma, chip->dma_ch, &s3c6400onenand_dma_client, NULL)) { ++ printk(KERN_WARNING "Unable to get DMA channel.\n"); ++ return; ++ } ++ ++ s3c_dma_set_buffdone_fn(chip->dma, chip->dma_ch, onenand_dma_finish); ++ s3c_dma_devconfig(chip->dma, chip->dma_ch, S3C_DMA_MEM2MEM, 1, 0, (u_long) phys_addr); ++ s3c_dma_config(chip->dma, chip->dma_ch, ONENAND_DMA_TRANSFER_WORD, ONENAND_DMA_TRANSFER_WORD); ++ s3c_dma_setflags(chip->dma, chip->dma_ch, S3C2410_DMAF_AUTOSTART); ++ consistent_sync((void *) dst, len, DMA_FROM_DEVICE); ++ s3c_dma_enqueue(chip->dma, chip->dma_ch, (void *) chip, (dma_addr_t) virt_to_dma(NULL, dst), len); ++ ++ wait_for_completion(&complete); ++ ++ s3c_dma_free(chip->dma, chip->dma_ch, &s3c6400onenand_dma_client); ++#else ++ if (s3c2410_dma_request(DMACH_ONENAND_IN, &s3c6400onenand_dma_client, NULL)) { ++ printk(KERN_WARNING "Unable to get DMA channel.\n"); ++ return; ++ } ++ ++ s3c2410_dma_set_buffdone_fn(DMACH_ONENAND_IN, onenand_dma_finish); ++ s3c2410_dma_devconfig(DMACH_ONENAND_IN, S3C_DMA_MEM2MEM_P, 1, (u_long) phys_addr); ++ s3c2410_dma_config(DMACH_ONENAND_IN, ONENAND_DMA_TRANSFER_WORD, ONENAND_DMA_TRANSFER_WORD); ++ s3c2410_dma_setflags(DMACH_ONENAND_IN, S3C2410_DMAF_AUTOSTART); ++ dma_cache_maint((void *) dst, len, DMA_FROM_DEVICE); ++ s3c2410_dma_enqueue(DMACH_ONENAND_IN, (void *) chip, (dma_addr_t) virt_to_dma(NULL, dst), len); ++ ++ wait_for_completion(&complete); ++ ++ s3c2410_dma_free(DMACH_ONENAND_IN, &s3c6400onenand_dma_client); ++#endif ++} ++#else ++extern s3c_dma_mainchan_t s3c_mainchans[S3C_DMA_CONTROLLERS]; ++extern void s3c_enable_dmac(unsigned int channel); ++extern void s3c_disable_dmac(unsigned int channel); ++static void onenand_read_dma(struct onenand_chip *chip, unsigned int *dst, void __iomem *src, size_t len) ++{ ++ s3c_dma_mainchan_t *mainchan = &s3c_mainchans[chip->dma]; ++ void __iomem *phys_addr = onenand_virt_to_phys((u_int) src); ++ ++ s3c_enable_dmac(chip->dma); ++ s3c_dma_set_buffdone_fn(chip->dma, chip->dma_ch, onenand_dma_finish); ++ s3c_dma_devconfig(chip->dma, chip->dma_ch, S3C_DMA_MEM2MEM_P, 1, 0, (u_long) phys_addr); ++ s3c_dma_config(chip->dma, chip->dma_ch, ONENAND_DMA_TRANSFER_WORD, ONENAND_DMA_TRANSFER_WORD); ++ s3c_dma_setflags(chip->dma, chip->dma_ch, S3C_DMAF_AUTOSTART); ++ consistent_sync((void *) dst, len, DMA_FROM_DEVICE); ++ s3c_dma_enqueue(chip->dma, chip->dma_ch, (void *) chip, (dma_addr_t) virt_to_dma(NULL, dst), len); ++ ++ while (readl(mainchan->regs + S3C_DMAC_ENBLD_CHANNELS) & (1 << chip->dma_ch)); ++ ++ s3c_dma_ctrl(chip->dma, chip->dma_ch, S3C_DMAOP_STOP); ++ s3c_disable_dmac(chip->dma); ++} ++#endif ++ ++/** ++ * onenand_command_map - [DEFAULT] Get command type ++ * @param cmd command ++ * @return command type (00, 01, 10, 11) ++ * ++ */ ++static int onenand_command_map(int cmd) ++{ ++ int type = ONENAND_CMD_MAP_FF; ++ ++ switch (cmd) { ++ case ONENAND_CMD_READ: ++ case ONENAND_CMD_READOOB: ++ case ONENAND_CMD_PROG: ++ case ONENAND_CMD_PROGOOB: ++ type = ONENAND_CMD_MAP_01; ++ break; ++ ++ case ONENAND_CMD_UNLOCK: ++ case ONENAND_CMD_LOCK: ++ case ONENAND_CMD_LOCK_TIGHT: ++ case ONENAND_CMD_UNLOCK_ALL: ++ case ONENAND_CMD_ERASE: ++ case ONENAND_CMD_OTP_ACCESS: ++ case ONENAND_CMD_PIPELINE_READ: ++ case ONENAND_CMD_PIPELINE_WRITE: ++ type = ONENAND_CMD_MAP_10; ++ break; ++ ++ case ONENAND_CMD_RESET: ++ case ONENAND_CMD_READID: ++ type = ONENAND_CMD_MAP_11; ++ break; ++ default: ++ type = ONENAND_CMD_MAP_FF; ++ break; ++ } ++ ++ return type; ++} ++ ++/** ++ * onenand_addr_field - [DEFAULT] Generate address field ++ * @param dev_id device id ++ * @param fba block number ++ * @param fpa page number ++ * @param fsa sector number ++ * @return address field ++ * ++ * Refer to Table 7-1 MEM_ADDR Fields in S3C6400/10 User's Manual ++ */ ++#if defined(CONFIG_CPU_S3C6400) ++static u_int onenand_addr_field(int dev_id, int fba, int fpa, int fsa) ++{ ++ u_int mem_addr = 0; ++ int ddp, density; ++ ++ ddp = dev_id & ONENAND_DEVICE_IS_DDP; ++ density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT; ++ ++ switch (density & 0xf) { ++ case ONENAND_DEVICE_DENSITY_128Mb: ++ mem_addr = (((fba & ONENAND_FBA_MASK_128Mb) << ONENAND_FBA_SHIFT_128Mb) | \ ++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT_128Mb) | \ ++ (fsa << ONENAND_FSA_SHIFT)); ++ break; ++ ++ case ONENAND_DEVICE_DENSITY_256Mb: ++ mem_addr = (((fba & ONENAND_FBA_MASK_256Mb) << ONENAND_FBA_SHIFT_256Mb) | \ ++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT_256Mb) | \ ++ (fsa << ONENAND_FSA_SHIFT)); ++ break; ++ ++ case ONENAND_DEVICE_DENSITY_512Mb: ++ mem_addr = (((fba & ONENAND_FBA_MASK_512Mb) << ONENAND_FBA_SHIFT_512Mb) | \ ++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT_512Mb) | \ ++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT)); ++ break; ++ ++ case ONENAND_DEVICE_DENSITY_1Gb: ++ if (ddp) { ++ mem_addr = ((ddp << ONENAND_DDP_SHIFT_1Gb) | \ ++ ((fba & ONENAND_FBA_MASK_1Gb_DDP) << ONENAND_FBA_SHIFT_1Gb_DDP) | \ ++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT_1Gb_DDP) | \ ++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT)); ++ } else { ++ mem_addr = (((fba & ONENAND_FBA_MASK_1Gb) << ONENAND_FBA_SHIFT_1Gb) | \ ++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT_1Gb) | \ ++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT)); ++ } ++ ++ break; ++ ++ case ONENAND_DEVICE_DENSITY_2Gb: ++ if (ddp) { ++ mem_addr = ((ddp << ONENAND_DDP_SHIFT_2Gb) | \ ++ ((fba & ONENAND_FBA_MASK_2Gb_DDP) << ONENAND_FBA_SHIFT_2Gb_DDP) | \ ++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT_2Gb_DDP) | \ ++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT)); ++ } else { ++ mem_addr = (((fba & ONENAND_FBA_MASK_2Gb) << ONENAND_FBA_SHIFT_2Gb) | \ ++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT_2Gb) | \ ++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT)); ++ } ++ ++ break; ++ ++ case ONENAND_DEVICE_DENSITY_4Gb: ++ if (ddp) { ++ mem_addr = ((ddp << ONENAND_DDP_SHIFT_4Gb) | \ ++ ((fba & ONENAND_FBA_MASK_4Gb_DDP) << ONENAND_FBA_SHIFT_4Gb_DDP) | \ ++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT_4Gb_DDP) | \ ++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT)); ++ } else { ++ mem_addr = (((fba & ONENAND_FBA_MASK_4Gb) << ONENAND_FBA_SHIFT_4Gb) | \ ++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT_4Gb) | \ ++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT)); ++ } ++ ++ break; ++ } ++ ++ return mem_addr; ++} ++#else ++static u_int onenand_addr_field(int dev_id, int fba, int fpa, int fsa) ++{ ++ u_int mem_addr = 0; ++ int ddp, density; ++ ++ ddp = dev_id & ONENAND_DEVICE_IS_DDP; ++ density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT; ++ ++ switch (density & 0xf) { ++ case ONENAND_DEVICE_DENSITY_128Mb: ++ mem_addr = (((fba & ONENAND_FBA_MASK_128Mb) << ONENAND_FBA_SHIFT) | \ ++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT) | \ ++ (fsa << ONENAND_FSA_SHIFT)); ++ break; ++ ++ case ONENAND_DEVICE_DENSITY_256Mb: ++ mem_addr = (((fba & ONENAND_FBA_MASK_256Mb) << ONENAND_FBA_SHIFT) | \ ++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT) | \ ++ (fsa << ONENAND_FSA_SHIFT)); ++ break; ++ ++ case ONENAND_DEVICE_DENSITY_512Mb: ++ mem_addr = (((fba & ONENAND_FBA_MASK_512Mb) << ONENAND_FBA_SHIFT) | \ ++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT) | \ ++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT)); ++ break; ++ ++ case ONENAND_DEVICE_DENSITY_1Gb: ++ if (ddp) { ++ mem_addr = ((ddp << ONENAND_DDP_SHIFT_1Gb) | \ ++ ((fba & ONENAND_FBA_MASK_1Gb_DDP) << ONENAND_FBA_SHIFT) | \ ++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT) | \ ++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT)); ++ } else { ++ mem_addr = (((fba & ONENAND_FBA_MASK_1Gb) << ONENAND_FBA_SHIFT) | \ ++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT) | \ ++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT)); ++ } ++ ++ break; ++ ++ case ONENAND_DEVICE_DENSITY_2Gb: ++ if (ddp) { ++ mem_addr = ((ddp << ONENAND_DDP_SHIFT_2Gb) | \ ++ ((fba & ONENAND_FBA_MASK_2Gb_DDP) << ONENAND_FBA_SHIFT) | \ ++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT) | \ ++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT)); ++ } else { ++ mem_addr = (((fba & ONENAND_FBA_MASK_2Gb) << ONENAND_FBA_SHIFT) | \ ++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT) | \ ++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT)); ++ } ++ ++ break; ++ ++ case ONENAND_DEVICE_DENSITY_4Gb: ++ if (ddp) { ++ mem_addr = ((ddp << ONENAND_DDP_SHIFT_1Gb) | \ ++ ((fba & ONENAND_FBA_MASK_4Gb_DDP) << ONENAND_FBA_SHIFT) | \ ++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT) | \ ++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT)); ++ } else { ++ mem_addr = (((fba & ONENAND_FBA_MASK_4Gb) << ONENAND_FBA_SHIFT) | \ ++ ((fpa & ONENAND_FPA_MASK) << ONENAND_FPA_SHIFT) | \ ++ ((fsa & ONENAND_FSA_MASK) << ONENAND_FSA_SHIFT)); ++ } ++ ++ break; ++ } ++ ++ return mem_addr; ++} ++#endif ++ ++/** ++ * onenand_command_address - [DEFAULT] Generate command address ++ * @param mtd MTD device structure ++ * @param cmd_type command type ++ * @param fba block number ++ * @param fpa page number ++ * @param fsa sector number ++ * @param onenand_addr onenand device address to access directly (command 00/11) ++ * @return command address ++ * ++ * Refer to 'Command Mapping' in S3C6400/10 User's Manual ++ */ ++static u_int onenand_command_address(struct mtd_info *mtd, int cmd_type, int fba, int fpa, int fsa, int onenand_addr) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ u_int cmd_addr = (ONENAND_AHB_ADDR | (cmd_type << ONENAND_CMD_SHIFT)); ++ int dev_id; ++ ++ dev_id = chip->read(chip->base + ONENAND_REG_DEVICE_ID); ++ ++ switch (cmd_type) { ++ case ONENAND_CMD_MAP_00: ++ cmd_addr |= ((onenand_addr & 0xffff) << 1); ++ break; ++ ++ case ONENAND_CMD_MAP_01: ++ case ONENAND_CMD_MAP_10: ++ cmd_addr |= (onenand_addr_field(dev_id, fba, fpa, fsa) & ONENAND_MEM_ADDR_MASK); ++ break; ++ ++ case ONENAND_CMD_MAP_11: ++ cmd_addr |= ((onenand_addr & 0xffff) << 2); ++ break; ++ ++ default: ++ cmd_addr = 0; ++ break; ++ } ++ ++ return cmd_addr; ++} ++ ++/** ++ * onenand_command - [DEFAULT] Generate command address ++ * @param mtd MTD device structure ++ * @param cmd command ++ * @param addr onenand device address ++ * @return command address ++ * ++ */ ++static u_int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ int sectors = 4, onenand_addr = -1; ++ int cmd_type, fba = 0, fpa = 0, fsa = 0, page; ++ u_int cmd_addr; ++ ++ cmd_type = onenand_command_map(cmd); ++ ++ switch (cmd) { ++ case ONENAND_CMD_UNLOCK: ++ case ONENAND_CMD_UNLOCK_ALL: ++ case ONENAND_CMD_LOCK: ++ case ONENAND_CMD_LOCK_TIGHT: ++ case ONENAND_CMD_ERASE: ++ fba = (int) (addr >> chip->erase_shift); ++ page = -1; ++ break; ++ ++ default: ++ fba = (int) (addr >> chip->erase_shift); ++ page = (int) (addr >> chip->page_shift); ++ page &= chip->page_mask; ++ fpa = page & ONENAND_FPA_MASK; ++ fsa = sectors & ONENAND_FSA_MASK; ++ break; ++ } ++ ++ cmd_addr = onenand_command_address(mtd, cmd_type, fba, fpa, fsa, onenand_addr); ++ ++ if (!cmd_addr) { ++ printk("Command address mapping failed\n"); ++ return -1; ++ } ++ ++ return cmd_addr; ++} ++ ++static int onenand_get_device(struct mtd_info *mtd, int new_state) ++{ ++/* disable now: future work */ ++#if 0 ++ struct onenand_chip *chip = mtd->priv; ++ DECLARE_WAITQUEUE(wait, current); ++ ++ /* ++ * Grab the lock and see if the device is available ++ */ ++ while (1) { ++ spin_lock(&chip->chip_lock); ++ if (chip->state == FL_READY) { ++ chip->state = new_state; ++ spin_unlock(&chip->chip_lock); ++ break; ++ } ++ if (new_state == FL_PM_SUSPENDED) { ++ spin_unlock(&chip->chip_lock); ++ return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN; ++ } ++ set_current_state(TASK_UNINTERRUPTIBLE); ++ add_wait_queue(&chip->wq, &wait); ++ spin_unlock(&chip->chip_lock); ++ schedule(); ++ remove_wait_queue(&chip->wq, &wait); ++ } ++#endif ++ return 0; ++} ++ ++/** ++ * onenand_release_device - [GENERIC] release chip ++ * @param mtd MTD device structure ++ * ++ * Deselect, release chip lock and wake up anyone waiting on the device ++ */ ++static void onenand_release_device(struct mtd_info *mtd) ++{ ++/* disable now: future work */ ++#if 0 ++ struct onenand_chip *chip = mtd->priv; ++ ++ /* Release the chip */ ++ spin_lock(&chip->chip_lock); ++ chip->state = FL_READY; ++ wake_up(&chip->wq); ++ spin_unlock(&chip->chip_lock); ++#endif ++} ++ ++/** ++ * onenand_bbt_read_oob - [MTD Interface] OneNAND read out-of-band for bbt scan ++ * @param mtd MTD device structure ++ * @param from offset to read from ++ * @param ops oob operation description structure ++ * ++ * OneNAND read out-of-band data from the spare area for bbt scan ++ */ ++int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from, ++ struct mtd_oob_ops *ops) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ void __iomem *cmd_addr; ++ int i; ++ size_t len = ops->ooblen; ++ u_char *buf = ops->oobbuf; ++ u_int bbinfo; ++ u_char *bb_poi = (u_char *)&bbinfo; ++ ++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_bbt_read_oob: from = 0x%08x, len = %zi\n", (unsigned int) from, len); ++ ++ /* Initialize return value */ ++ ops->oobretlen = 0; ++ ++ /* Do not allow reads past end of device */ ++ if (unlikely((from + len) > mtd->size)) { ++ printk(KERN_ERR "onenand_bbt_read_oob: Attempt read beyond end of device\n"); ++ return ONENAND_BBT_READ_FATAL_ERROR; ++ } ++ ++ /* Grab the lock and see if the device is available */ ++ onenand_get_device(mtd, FL_READING); ++ ++ /* on the TRANSFER SPARE bit */ ++ chip->write(ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE); ++ ++ /* get start address to read data */ ++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_READ, from)); ++ ++ switch (chip->options & ONENAND_READ_MASK) { ++ case ONENAND_READ_BURST: ++ onenand_read_burst((u_int *)chip->page_buf, cmd_addr, mtd->writesize); ++ onenand_read_burst((u_int *)chip->oob_buf, cmd_addr, mtd->oobsize); ++ buf[0] = chip->oob_buf[0]; ++ buf[1] = chip->oob_buf[1]; ++ break; ++ ++ case ONENAND_READ_DMA: ++ onenand_read_dma(chip, (u_int *)chip->page_buf, cmd_addr, mtd->writesize); ++ onenand_read_dma(chip, (u_int *)chip->oob_buf, cmd_addr, mtd->oobsize); ++ buf[0] = chip->oob_buf[0]; ++ buf[1] = chip->oob_buf[1]; ++ break; ++ ++ case ONENAND_READ_POLLING: ++ /* read main data and throw into garbage box */ ++ for (i = 0; i < (mtd->writesize / 4); i++) ++ chip->read(cmd_addr); ++ ++ /* read first 4 bytes of spare data */ ++ bbinfo = chip->read(cmd_addr); ++ buf[0] = bb_poi[0]; ++ buf[1] = bb_poi[1]; ++ ++ for (i = 0; i < (mtd->oobsize / 4) - 1; i++) ++ chip->read(cmd_addr); ++ break; ++ } ++ ++ onenand_blkrw_complete(chip, ONENAND_CMD_READ); ++ ++ /* off the TRANSFER SPARE bit */ ++ chip->write(~ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE); ++ ++ /* Deselect and wake up anyone waiting on the device */ ++ onenand_release_device(mtd); ++ ++ ops->oobretlen = len; ++ return 0; ++} ++ ++/** ++ * onenand_block_isbad_nolock - [GENERIC] Check if a block is marked bad ++ * @param mtd MTD device structure ++ * @param ofs offset from device start ++ * @param allowbbt 1, if its allowed to access the bbt area ++ * ++ * Check, if the block is bad. Either by reading the bad block table or ++ * calling of the scan function. ++ */ ++static int onenand_block_isbad_nolock(struct mtd_info *mtd, loff_t ofs, int allowbbt) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ ++ if (chip->options & ONENAND_CHECK_BAD) { ++ struct bbm_info *bbm = chip->bbm; ++ ++ /* Return info from the table */ ++ return bbm->isbad_bbt(mtd, ofs, allowbbt); ++ } else ++ return 0; ++} ++ ++/** ++ * onenand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad ++ * @param mtd MTD device structure ++ * @param ofs offset relative to mtd start ++ * ++ * Check whether the block is bad ++ */ ++static int onenand_block_isbad(struct mtd_info *mtd, loff_t ofs) ++{ ++ /* Check for invalid offset */ ++ if (ofs > mtd->size) ++ return -EINVAL; ++ ++ return onenand_block_isbad_nolock(mtd, ofs, 0); ++} ++ ++/** ++ * onenand_default_block_markbad - [DEFAULT] mark a block bad ++ * @param mtd MTD device structure ++ * @param ofs offset from device start ++ * ++ * This is the default implementation, which can be overridden by ++ * a hardware specific driver. ++ */ ++static int onenand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) ++{ ++ struct onenand_chip *this = mtd->priv; ++ struct bbm_info *bbm = this->bbm; ++ u_char buf[2] = {0, 0}; ++ int block; ++ struct mtd_oob_ops ops = { ++ .mode = MTD_OOB_PLACE, ++ .ooblen = 2, ++ .oobbuf = buf, ++ .ooboffs = 0, ++ }; ++ ++ /* Get block number */ ++ block = ((int) ofs) >> bbm->bbt_erase_shift; ++ if (bbm->bbt) ++ bbm->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); ++ ++ /* We write two bytes, so we dont have to mess with 16 bit access */ ++ ofs += mtd->oobsize + (bbm->badblockpos & ~0x01); ++ return onenand_write_oob_nolock(mtd, ofs, &ops); ++} ++ ++ ++/** ++ * onenand_set_pipeline - [MTD Interface] Set pipeline ahead ++ * @param mtd MTD device structure ++ * @param from offset to read from ++ * @param len number of bytes to read ++ * ++ */ ++static int onenand_set_pipeline(struct mtd_info *mtd, loff_t from, size_t len) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ int page_cnt = (int) (len >> chip->page_shift); ++ void __iomem *cmd_addr; ++ ++ if (len % mtd->writesize > 0) ++ page_cnt++; ++ ++ if (page_cnt > 1) { ++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_PIPELINE_READ, from)); ++ chip->write(ONENAND_DATAIN_PIPELINE_READ | page_cnt, cmd_addr); ++ } ++ ++ return 0; ++} ++ ++/** ++ * onenand_read - [MTD Interface] Read data from flash ++ * @param mtd MTD device structure ++ * @param from offset to read from ++ * @param len number of bytes to read ++ * @param retlen pointer to variable to store the number of read bytes ++ * @param buf the databuffer to put data ++ * ++ */ ++static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len, ++ size_t *retlen, u_char *buf) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ struct mtd_ecc_stats stats; ++ int i, ret = 0, read = 0, col, thislen; ++ u_int *buf_poi = (u_int *) chip->page_buf; ++ void __iomem *cmd_addr; ++ ++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_read: from = 0x%08x, len = %i, col = %i\n", (unsigned int) from, (int) len, (int) col); ++ ++ /* Do not allow reads past end of device */ ++ if ((from + len) > mtd->size) { ++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_read: Attempt read beyond end of device\n"); ++ *retlen = 0; ++ return -EINVAL; ++ } ++ ++ /* Grab the lock and see if the device is available */ ++ onenand_get_device(mtd, FL_READING); ++ ++ /* TODO handling oob */ ++ stats = mtd->ecc_stats; ++ ++ /* column (start offset to read) */ ++ col = (int)(from & (mtd->writesize - 1)); ++ ++ if (chip->options & ONENAND_PIPELINE_AHEAD) ++ onenand_set_pipeline(mtd, from, len); ++ ++#ifdef CONFIG_MTD_ONENAND_CHECK_SPEED ++ if (len > 100000) { ++ writel((readl(S3C_GPNCON) & ~(0x3 << 30)) | (0x1 << 30), S3C_GPNCON); ++ writel(1 << 15, S3C_GPNDAT); ++ } ++#endif ++ ++ //while (!ret) { ++ while (1) { ++ if (chip->options & ONENAND_CHECK_BAD) { ++ if (onenand_block_isbad(mtd, from)) { ++ printk (KERN_WARNING "\nonenand_read: skipped to read from a bad block at addr 0x%08x.\n", (unsigned int) from); ++ from += (1 << chip->erase_shift); ++ ++ if (col != 0) ++ col = (int)(from & (mtd->writesize - 1)); ++ ++ continue; ++ } ++ } ++ ++ /* get start address to read data */ ++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_READ, from)); ++ ++ switch (chip->options & ONENAND_READ_MASK) { ++ case ONENAND_READ_BURST: ++ onenand_read_burst(buf_poi, cmd_addr, mtd->writesize); ++ break; ++ ++ case ONENAND_READ_DMA: ++ onenand_read_dma(chip, buf_poi, cmd_addr, mtd->writesize); ++ break; ++ ++ case ONENAND_READ_POLLING: ++ for (i = 0; i < (mtd->writesize / 4); i++) ++ *buf_poi++ = chip->read(cmd_addr); ++ ++ buf_poi -= (mtd->writesize / 4); ++ break; ++ ++ default: ++ printk("onenand_read: read mode undefined.\n"); ++ return -1; ++ } ++ ++ if (onenand_blkrw_complete(chip, ONENAND_CMD_READ)) { ++ printk(KERN_WARNING "onenand_read: Read operation failed:0x%08x.\n", (unsigned int)from); ++#if 0 ++ return -1; ++#endif ++ } ++ ++ thislen = min_t(int, mtd->writesize - col, len - read); ++ memcpy(buf, chip->page_buf + col, thislen); ++ ++ read += thislen; ++ ++ if (read == len) ++ break; ++ ++ buf += thislen; ++ from += mtd->writesize; ++ col = 0; ++ } ++ ++#ifdef CONFIG_MTD_ONENAND_CHECK_SPEED ++ if (len > 100000) { ++ printk("len: %d\n", len); ++ writel(0 << 15, S3C_GPNDAT); ++ } ++#endif ++ ++ /* Deselect and wake up anyone waiting on the device */ ++ onenand_release_device(mtd); ++ ++ /* ++ * Return success, if no ECC failures, else -EBADMSG ++ * fs driver will take care of that, because ++ * retlen == desired len and result == -EBADMSG ++ */ ++ *retlen = read; ++ ++ if (mtd->ecc_stats.failed - stats.failed) ++ return -EBADMSG; ++ ++ if (ret) ++ return ret; ++ ++ return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; ++} ++ ++/** ++ * onenand_transfer_auto_oob - [Internal] oob auto-placement transfer ++ * @param mtd MTD device structure ++ * @param buf destination address ++ * @param column oob offset to read from ++ * @param thislen oob length to read ++ */ ++static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf, int column, ++ int thislen) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ struct nand_oobfree *free; ++ int readcol = column; ++ int readend = column + thislen; ++ int lastgap = 0; ++ uint8_t *oob_buf = chip->oob_buf; ++ ++ for (free = chip->ecclayout->oobfree; free->length; ++free) { ++ if (readcol >= lastgap) ++ readcol += free->offset - lastgap; ++ if (readend >= lastgap) ++ readend += free->offset - lastgap; ++ lastgap = free->offset + free->length; ++ } ++ ++ for (free = chip->ecclayout->oobfree; free->length; ++free) { ++ int free_end = free->offset + free->length; ++ if (free->offset < readend && free_end > readcol) { ++ int st = max_t(int,free->offset,readcol); ++ int ed = min_t(int,free_end,readend); ++ int n = ed - st; ++ memcpy(buf, oob_buf + st, n); ++ buf += n; ++ } else ++ break; ++ } ++ return 0; ++} ++ ++ ++/** ++ * onenand_read_ops_nolock - [OneNAND Interface] OneNAND read main and/or out-of-band ++ * @param mtd MTD device structure ++ * @param from offset to read from ++ * @param ops: oob operation description structure ++ * ++ * OneNAND read main and/or out-of-band data ++ */ ++static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ int read = 0, thislen, column, oobsize; ++ int i, ret = 0; ++ void __iomem *cmd_addr; ++ u_int *buf_poi, *dbuf_poi; ++ ++ int len = ops->ooblen; ++ u_char *buf = ops->datbuf; ++ u_char *sparebuf = ops->oobbuf; ++ ++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_ops_nolock: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); ++ ++ /* Initialize return length value */ ++ ops->retlen = 0; ++ ops->oobretlen = 0; ++ ++ if (ops->mode == MTD_OOB_AUTO) ++ oobsize = chip->ecclayout->oobavail; ++ else ++ oobsize = mtd->oobsize; ++ ++ column = from & (mtd->oobsize - 1); ++ ++ if (unlikely(column >= oobsize)) { ++ printk(KERN_ERR "onenand_read_ops_nolock: Attempted to start read outside oob\n"); ++ return -EINVAL; ++ } ++ ++ /* Do not allow reads past end of device */ ++ if (unlikely(from >= mtd->size || ++ column + len > ((mtd->size >> chip->page_shift) - ++ (from >> chip->page_shift)) * oobsize)) { ++ printk(KERN_ERR "onenand_read_ops_nolock: Attempted to read beyond end of device\n"); ++ return -EINVAL; ++ } ++ ++ /* Grab the lock and see if the device is available */ ++ onenand_get_device(mtd, FL_READING); ++ ++ dbuf_poi = (u_int *)buf; ++ ++ if (chip->options & ONENAND_PIPELINE_AHEAD) ++ onenand_set_pipeline(mtd, from, len); ++ ++ /* on the TRANSFER SPARE bit */ ++ chip->write(ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE); ++ ++ while (read < len) { ++ if (chip->options & ONENAND_CHECK_BAD) { ++ if (onenand_block_isbad(mtd, from)) { ++ printk (KERN_WARNING "onenand_read_ops_nolock: skipped to read oob from a bad block at addr 0x%08x.\n", (unsigned int) from); ++ from += (1 << chip->erase_shift); ++ ++ if (column != 0) ++ column = from & (mtd->oobsize - 1); ++ ++ continue; ++ } ++ } ++ ++ /* get start address to read data */ ++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_READ, from)); ++ ++ thislen = oobsize - column; ++ thislen = min_t(int, thislen, len); ++ ++ //if (ops->mode == MTD_OOB_AUTO) ++ buf_poi = (u_int *)chip->oob_buf; ++ //else ++ //buf_poi = (u_int *)buf; ++ ++ switch (chip->options & ONENAND_READ_MASK) { ++ case ONENAND_READ_BURST: ++ onenand_read_burst(dbuf_poi, cmd_addr, mtd->writesize); ++ onenand_read_burst(buf_poi, cmd_addr, mtd->oobsize); ++ break; ++ ++ case ONENAND_READ_DMA: ++ onenand_read_dma(chip, dbuf_poi, cmd_addr, mtd->writesize); ++ onenand_read_dma(chip, buf_poi, cmd_addr, mtd->oobsize); ++ break; ++ ++ case ONENAND_READ_POLLING: ++ /* read main data and throw into garbage box */ ++ for (i = 0; i < (mtd->writesize / 4); i++) ++ *dbuf_poi = chip->read(cmd_addr); ++ ++ /* read spare data */ ++ for (i = 0; i < (mtd->oobsize / 4); i++) ++ *buf_poi++ = chip->read(cmd_addr); ++ ++ break; ++ } ++ ++ if (onenand_blkrw_complete(chip, ONENAND_CMD_READ)) { ++ printk(KERN_WARNING "onenand_read_ops_nolock: Read operation failed:0x%x\n", (unsigned int)from); ++#if 0 ++ chip->write(~ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE); ++ return -1; ++#endif ++ } ++ ++ if (ops->mode == MTD_OOB_AUTO) ++ onenand_transfer_auto_oob(mtd, sparebuf, column, thislen); ++ ++ read += thislen; ++ ++ if (read == len) ++ break; ++ ++ buf += thislen; ++ ++ /* Read more? */ ++ if (read < len) { ++ /* Page size */ ++ from += mtd->writesize; ++ column = 0; ++ } ++ } ++ ++ /* off the TRANSFER SPARE bit */ ++ chip->write(~ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE); ++ ++ /* Deselect and wake up anyone waiting on the device */ ++ onenand_release_device(mtd); ++ ++ ops->retlen = mtd->writesize; ++ ops->oobretlen = read; ++ ++ return ret; ++} ++ ++ ++/** ++ * onenand_read_oob_nolock - [MTD Interface] OneNAND read out-of-band ++ * @param mtd MTD device structure ++ * @param from offset to read from ++ * @param ops: oob operation description structure ++ * ++ * OneNAND read out-of-band data from the spare area ++ */ ++static int onenand_read_oob_nolock(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ int read = 0, thislen, column, oobsize; ++ int i, ret = 0; ++ void __iomem *cmd_addr; ++ u_int *buf_poi; ++ ++ size_t len = ops->ooblen; ++ mtd_oob_mode_t mode = ops->mode; ++ u_char *buf = ops->oobbuf; ++ ++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_oob_nolock: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); ++ ++ /* Initialize return length value */ ++ ops->oobretlen = 0; ++ ++ if (mode == MTD_OOB_AUTO) ++ oobsize = chip->ecclayout->oobavail; ++ else ++ oobsize = mtd->oobsize; ++ ++ column = from & (mtd->oobsize - 1); ++ ++ if (unlikely(column >= oobsize)) { ++ printk(KERN_ERR "onenand_read_oob_nolock: Attempted to start read outside oob\n"); ++ return -EINVAL; ++ } ++ ++ /* Do not allow reads past end of device */ ++ if (unlikely(from >= mtd->size || ++ column + len > ((mtd->size >> chip->page_shift) - ++ (from >> chip->page_shift)) * oobsize)) { ++ printk(KERN_ERR "onenand_read_oob_nolock: Attempted to read beyond end of device\n"); ++ return -EINVAL; ++ } ++ ++ /* Grab the lock and see if the device is available */ ++ onenand_get_device(mtd, FL_READING); ++ ++ if (chip->options & ONENAND_PIPELINE_AHEAD) ++ onenand_set_pipeline(mtd, from, len); ++ ++ /* on the TRANSFER SPARE bit */ ++ chip->write(ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE); ++ ++ while (read < len) { ++ if (chip->options & ONENAND_CHECK_BAD) { ++ if (onenand_block_isbad(mtd, from)) { ++ printk (KERN_WARNING "\nonenand_do_read_oob: skipped to read oob from a bad block at addr 0x%08x.\n", (unsigned int) from); ++ from += (1 << chip->erase_shift); ++ ++ if (column != 0) ++ column = from & (mtd->oobsize - 1); ++ ++ continue; ++ } ++ } ++ ++ /* get start address to read data */ ++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_READ, from)); ++ ++ thislen = oobsize - column; ++ thislen = min_t(int, thislen, len); ++ ++ if (mode == MTD_OOB_AUTO) ++ buf_poi = (u_int *)chip->oob_buf; ++ else ++ buf_poi = (u_int *)buf; ++ ++ switch (chip->options & ONENAND_READ_MASK) { ++ case ONENAND_READ_BURST: ++ onenand_read_burst(buf_poi, cmd_addr, mtd->writesize); ++ onenand_read_burst(buf_poi, cmd_addr, mtd->oobsize); ++ break; ++ ++ case ONENAND_READ_DMA: ++ onenand_read_dma(chip, buf_poi, cmd_addr, mtd->writesize); ++ onenand_read_dma(chip, buf_poi, cmd_addr, mtd->oobsize); ++ break; ++ ++ case ONENAND_READ_POLLING: ++ /* read main data and throw into garbage box */ ++ for (i = 0; i < (mtd->writesize / 4); i++) ++ *buf_poi = chip->read(cmd_addr); ++ ++ /* read spare data */ ++ for (i = 0; i < (mtd->oobsize / 4); i++) ++ *buf_poi++ = chip->read(cmd_addr); ++ ++ break; ++ } ++ ++ if (onenand_blkrw_complete(chip, ONENAND_CMD_READ)) { ++ printk(KERN_WARNING "onenand_read_oob_nolock: Read operation failed:0x%x\n", (unsigned int)from); ++#if 0 ++ chip->write(~ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE); ++ return -1; ++#endif ++ } ++ ++ if (mode == MTD_OOB_AUTO) ++ onenand_transfer_auto_oob(mtd, buf, column, thislen); ++ ++ read += thislen; ++ ++ if (read == len) ++ break; ++ ++ buf += thislen; ++ ++ /* Read more? */ ++ if (read < len) { ++ /* Page size */ ++ from += mtd->writesize; ++ column = 0; ++ } ++ } ++ ++ /* off the TRANSFER SPARE bit */ ++ chip->write(~ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE); ++ ++ /* Deselect and wake up anyone waiting on the device */ ++ onenand_release_device(mtd); ++ ++ ops->oobretlen = read; ++ return ret; ++} ++ ++/** ++ * onenand_read_oob - [MTD Interface] NAND write data and/or out-of-band ++ * @mtd: MTD device structure ++ * @from: offset to read from ++ * @ops: oob operation description structure ++ */ ++static int onenand_read_oob(struct mtd_info *mtd, loff_t from, ++ struct mtd_oob_ops *ops) ++{ ++ int ret = 0; ++ ++ switch (ops->mode) { ++ case MTD_OOB_PLACE: ++ case MTD_OOB_AUTO: ++ break; ++ case MTD_OOB_RAW: ++ /* Not implemented yet */ ++ default: ++ return -EINVAL; ++ } ++ ++ if (ops->datbuf != NULL) ++ ret = onenand_read_ops_nolock(mtd, from, ops); ++ else ++ ret = onenand_read_oob_nolock(mtd, from, ops); ++ ++ return ret; ++} ++ ++#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE ++/** ++ * onenand_verify_page - [GENERIC] verify the chip contents after a write ++ * @param mtd MTD device structure ++ * @param buf the databuffer to verify ++ * @param addr address to read ++ * @return 0, if ok ++ */ ++static int onenand_verify_page(struct mtd_info *mtd, const u_int *buf, loff_t addr) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ void __iomem *cmd_addr; ++ int i, ret = 0; ++ u_int *written = (u_int *)kmalloc(mtd->writesize, GFP_KERNEL); ++ ++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_READ, addr)); ++ ++ /* write all data of 1 page by 4 bytes at a time */ ++ for (i = 0; i < (mtd->writesize / 4); i++) { ++ *written = chip->read(cmd_addr); ++ written++; ++ } ++ ++ written -= (mtd->writesize / 4); ++ ++ /* Check, if data is same */ ++ if (memcmp(written, buf, mtd->writesize)) ++ ret = -EBADMSG; ++ ++ kfree(written); ++ ++ return ret; ++} ++ ++/** ++ * onenand_verify_oob - [GENERIC] verify the oob contents after a write ++ * @param mtd MTD device structure ++ * @param buf the databuffer to verify ++ * @param to offset to read from ++ * ++ */ ++static int onenand_verify_oob(struct mtd_info *mtd, const u_char *buf, loff_t to, size_t len) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ char oobbuf[64]; ++ u_int *buf_poi, *dbuf_poi; ++ int read = 0, thislen, column, oobsize, i; ++ void __iomem *cmd_addr; ++ mtd_oob_mode_t mode = MTD_OOB_AUTO; ++ ++ if (mode == MTD_OOB_AUTO) ++ oobsize = chip->ecclayout->oobavail; ++ else ++ oobsize = mtd->oobsize; ++ ++ column = to & (mtd->oobsize - 1); ++ dbuf_poi = (u_int *)chip->page_buf; ++ ++ while (read < len) { ++ /* get start address to read data */ ++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_READ, to)); ++ ++ thislen = oobsize - column; ++ thislen = min_t(int, thislen, len); ++ ++ if (mode == MTD_OOB_AUTO) ++ buf_poi = (u_int *)chip->oob_buf; ++ else ++ buf_poi = (u_int *)buf; ++ ++ onenand_read_burst(dbuf_poi, cmd_addr, mtd->writesize); ++ onenand_read_burst(buf_poi, cmd_addr, mtd->oobsize); ++ ++ if (onenand_blkrw_complete(chip, ONENAND_CMD_READ)) { ++ printk(KERN_WARNING "onenand_verify_oob: Read operation failed:0x%x\n", (unsigned int)to); ++#if 0 ++ chip->write(~ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE); ++ return -1; ++#endif ++ } ++ ++ if (mode == MTD_OOB_AUTO) ++ onenand_transfer_auto_oob(mtd, oobbuf, column, thislen); ++ ++ read += thislen; ++ ++ if (read == len) ++ break; ++ ++ } ++ ++ ++ for (i = 0; i < len; i++) ++ if (buf[i] != oobbuf[i]) ++ return -EBADMSG; ++ ++ return 0; ++} ++ ++ ++/** ++ * onenand_verify_ops - [GENERIC] verify the oob contents after a write ++ * @param mtd MTD device structure ++ * @param ops oob operation description structure ++ * @param to offset to read from ++ * @param len number of bytes to read ++ * ++ */ ++static int onenand_verify_ops(struct mtd_info *mtd, struct mtd_oob_ops *ops, loff_t to, size_t len) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ char oobbuf[64]; ++ u_int *buf_poi, *dbuf_poi; ++ int read = 0, thislen, column, oobsize, i; ++ void __iomem *cmd_addr; ++ int ret = 0; ++ ++ if (ops->mode == MTD_OOB_AUTO) ++ oobsize = chip->ecclayout->oobavail; ++ else ++ oobsize = mtd->oobsize; ++ ++ column = to & (mtd->oobsize - 1); ++ ++ while (read < len) { ++ /* get start address to read data */ ++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_READ, to)); ++ ++ thislen = oobsize - column; ++ thislen = min_t(int, thislen, len); ++ ++ dbuf_poi = (u_int *)chip->page_buf; ++ ++ if (ops->mode == MTD_OOB_AUTO) ++ buf_poi = (u_int *)chip->oob_buf; ++ else ++ buf_poi = (u_int *)oobbuf; ++ ++ onenand_read_burst(dbuf_poi, cmd_addr, mtd->writesize); ++ onenand_read_burst(buf_poi, cmd_addr, mtd->oobsize); ++ ++ if (onenand_blkrw_complete(chip, ONENAND_CMD_READ)) { ++ printk(KERN_WARNING "onenand_verify_oob: Read operation failed:0x%x\n", (unsigned int)to); ++ return -EBADMSG; ++ } ++ ++ if (ops->mode == MTD_OOB_AUTO) ++ onenand_transfer_auto_oob(mtd, oobbuf, column, thislen); ++ ++ read += thislen; ++ ++ if (read == len) ++ break; ++ ++ } ++ ++ /* Check, if data is same */ ++ if (memcmp(chip->page_buf, ops->datbuf, mtd->writesize)) { ++ printk("Invalid data buffer : 0x%x\n", (unsigned int)to); ++ ret = -EBADMSG; ++ } ++ ++ for (i = 0; i < len; i++) ++ if (ops->oobbuf[i] != oobbuf[i]) { ++ printk("Invalid OOB buffer :0x%x\n", (unsigned int)to); ++ ret = -EBADMSG; ++ } ++ ++ return ret; ++} ++ ++#endif ++ ++#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) ++ ++/** ++ * onenand_write - [MTD Interface] write buffer to FLASH ++ * @param mtd MTD device structure ++ * @param to offset to write to ++ * @param len number of bytes to write ++ * @param retlen pointer to variable to store the number of written bytes ++ * @param buf the data to write ++ * ++ */ ++int onenand_write(struct mtd_info *mtd, loff_t to, size_t len, ++ size_t *retlen, const u_char *buf) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ int written = 0; ++ int i, ret = 0; ++ void __iomem *cmd_addr; ++ u_int *buf_poi = (u_int *)buf; ++ ++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_write: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); ++ ++ /* Initialize retlen, in case of early exit */ ++ *retlen = 0; ++ ++ /* Do not allow writes past end of device */ ++ if (unlikely((to + len) > mtd->size)) { ++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_write: Attempt write to past end of device\n"); ++ return -EINVAL; ++ } ++ ++ /* Reject writes, which are not page aligned */ ++ if (unlikely(NOTALIGNED(to)) || unlikely(NOTALIGNED(len))) { ++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_write: Attempt to write not page aligned data\n"); ++ return -EINVAL; ++ } ++ ++ /* Grab the lock and see if the device is available */ ++ onenand_get_device(mtd, FL_WRITING); ++ ++ /* Loop until all data write */ ++ while (written < len) { ++ if (chip->options & ONENAND_CHECK_BAD) { ++ if (onenand_block_isbad(mtd, to)) { ++ printk (KERN_WARNING "onenand_write: skipped to write to a bad block at addr 0x%08x.\n", (unsigned int) to); ++ to += (1 << chip->erase_shift); ++ continue; ++ } ++ } ++ ++ /* get start address to write data */ ++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_PROG, to)); ++ ++ /* write all data of 1 page by 4 bytes at a time */ ++ for (i = 0; i < (mtd->writesize / 4); i++) { ++ chip->write(*buf_poi, cmd_addr); ++ buf_poi++; ++ } ++ ++ if (onenand_blkrw_complete(chip, ONENAND_CMD_PROG)) { ++ printk(KERN_WARNING "onenand_write: Program operation failed.\n"); ++ return -1; ++ } ++ ++#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE ++ /* Only check verify write turn on */ ++ ret = onenand_verify_page(mtd, buf_poi - (mtd->writesize / 4), to); ++ ++ if (ret) { ++ printk("onenand_write: verify failed:0x%x.\n", (unsigned int)to); ++ break; ++ } ++#endif ++ written += mtd->writesize; ++ ++ if (written == len) ++ break; ++ ++ to += mtd->writesize; ++ } ++ ++ /* Deselect and wake up anyone waiting on the device */ ++ onenand_release_device(mtd); ++ ++ *retlen = written; ++ ++ return ret; ++} ++ ++/** ++ * onenand_fill_auto_oob - [Internal] oob auto-placement transfer ++ * @param mtd MTD device structure ++ * @param oob_buf oob buffer ++ * @param buf source address ++ * @param column oob offset to write to ++ * @param thislen oob length to write ++ */ ++static int onenand_fill_auto_oob(struct mtd_info *mtd, u_char *oob_buf, ++ const u_char *buf, int column, int thislen) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ struct nand_oobfree *free; ++ int writecol = column; ++ int writeend = column + thislen; ++ int lastgap = 0; ++ ++ for (free = chip->ecclayout->oobfree; free->length; ++free) { ++ if (writecol >= lastgap) ++ writecol += free->offset - lastgap; ++ if (writeend >= lastgap) ++ writeend += free->offset - lastgap; ++ lastgap = free->offset + free->length; ++ } ++ for (free = chip->ecclayout->oobfree; free->length; ++free) { ++ int free_end = free->offset + free->length; ++ if (free->offset < writeend && free_end > writecol) { ++ int st = max_t(int,free->offset,writecol); ++ int ed = min_t(int,free_end,writeend); ++ int n = ed - st; ++ memcpy(oob_buf + st, buf, n); ++ buf += n; ++ } else ++ break; ++ } ++ return 0; ++} ++ ++ ++/** ++ * onenand_write_ops_nolock - [OneNAND Interface] write main and/or out-of-band ++ * @param mtd MTD device structure ++ * @param to offset to write to ++ * @param ops oob operation description structure ++ * ++ * Write main and/or oob with ECC ++ */ ++static int onenand_write_ops_nolock(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ int i, column, ret = 0, oobsize; ++ int written = 0; ++ ++ int len = ops->ooblen; ++ u_char *buf = ops->datbuf; ++ u_char *sparebuf = ops->oobbuf; ++ u_char *oobbuf; ++ ++ void __iomem *cmd_addr; ++ u_int *buf_poi; ++ ++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_ops_nolock: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); ++ ++ /* Initialize retlen, in case of early exit */ ++ ops->retlen = 0; ++ ops->oobretlen = 0; ++ ++ if (ops->mode == MTD_OOB_AUTO) ++ oobsize = chip->ecclayout->oobavail; ++ else ++ oobsize = mtd->oobsize; ++ ++ column = to & (mtd->oobsize - 1); ++ ++ if (unlikely(column >= oobsize)) { ++ printk(KERN_ERR "onenand_write_ops_nolock: Attempted to start write outside oob\n"); ++ return -EINVAL; ++ } ++ ++ /* For compatibility with NAND: Do not allow write past end of page */ ++ if (unlikely(column + len > oobsize)) { ++ printk(KERN_ERR "onenand_write_ops_nolock: " ++ "Attempt to write past end of page\n"); ++ return -EINVAL; ++ } ++ ++ /* Do not allow reads past end of device */ ++ if (unlikely(to >= mtd->size || ++ column + len > ((mtd->size >> chip->page_shift) - ++ (to >> chip->page_shift)) * oobsize)) { ++ printk(KERN_ERR "onenand_write_ops_nolock: Attempted to write past end of device\n"); ++ return -EINVAL; ++ } ++ ++ /* Grab the lock and see if the device is available */ ++ onenand_get_device(mtd, FL_WRITING); ++ ++ oobbuf = chip->oob_buf; ++ buf_poi = (u_int *)buf; ++ ++ /* on the TRANSFER SPARE bit */ ++ chip->write(ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE); ++ ++ /* Loop until all data write */ ++ while (written < len) { ++ int thislen = min_t(int, oobsize, len - written); ++ ++ if (chip->options & ONENAND_CHECK_BAD) { ++ if (onenand_block_isbad(mtd, to)) { ++ printk (KERN_WARNING "onenand_write_ops_nolock: skipped to write oob to a bad block at addr 0x%08x.\n", (unsigned int) to); ++ to += (1 << chip->erase_shift); ++ ++ if (column != 0) ++ column = to & (mtd->oobsize - 1); ++ ++ continue; ++ } ++ } ++ ++ /* get start address to write data */ ++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_PROG, to)); ++ ++ /* write all data of 1 page by 4 bytes at a time */ ++ for (i = 0; i < (mtd->writesize / 4); i++) { ++ chip->write(*buf_poi, cmd_addr); ++ buf_poi++; ++ } ++ ++ /* We send data to spare ram with oobsize ++ * to prevent byte access */ ++ memset(oobbuf, 0xff, mtd->oobsize); ++ ++ if (ops->mode == MTD_OOB_AUTO) ++ onenand_fill_auto_oob(mtd, oobbuf, sparebuf, column, thislen); ++ else ++ memcpy(oobbuf + column, buf, thislen); ++ ++ buf_poi = (u_int *)chip->oob_buf; ++ for (i = 0; i < (mtd->oobsize / 4); i++) { ++ chip->write(*buf_poi, cmd_addr); ++ buf_poi++; ++ } ++ ++ if (onenand_blkrw_complete(chip, ONENAND_CMD_PROG)) { ++ printk(KERN_WARNING "onenand_write_ops_nolock: Program operation failed.\n"); ++ chip->write(~ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE); ++ return -1; ++ } ++ ++ ++#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE ++ ret = onenand_verify_ops(mtd, ops, to, len); ++ ++ if (ret) { ++ printk(KERN_ERR "onenand_write_ops_nolock: verify failed :0x%x\n", (unsigned int)to); ++ break; ++ } ++#endif ++ written += thislen; ++ ++ if (written == len) ++ break; ++ ++ to += mtd->writesize; ++ buf += thislen; ++ column = 0; ++ } ++ ++ /* off the TRANSFER SPARE bit */ ++ chip->write(~ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE); ++ ++ /* Deselect and wake up anyone waiting on the device */ ++ onenand_release_device(mtd); ++ ++ ops->retlen = mtd->writesize; ++ ops->oobretlen = written; ++ ++ return ret; ++} ++ ++ ++/** ++ * onenand_write_oob_nolock - [Internal] OneNAND write out-of-band ++ * @param mtd MTD device structure ++ * @param to offset to write to ++ * @param len number of bytes to write ++ * @param retlen pointer to variable to store the number of written bytes ++ * @param buf the data to write ++ * @param mode operation mode ++ * ++ * OneNAND write out-of-band ++ */ ++static int onenand_write_oob_nolock(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ int i, column, ret = 0, oobsize; ++ int written = 0; ++ u_char *oobbuf, *orgbuf; ++ void __iomem *cmd_addr; ++ u_int *buf_poi; ++ ++ size_t len = ops->ooblen; ++ const u_char *buf = ops->oobbuf; ++ mtd_oob_mode_t mode = ops->mode; ++ ++ ++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_oob_nolock: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); ++ ++ /* Initialize retlen, in case of early exit */ ++ ops->oobretlen = 0; ++ ++ if (mode == MTD_OOB_AUTO) ++ oobsize = chip->ecclayout->oobavail; ++ else ++ oobsize = mtd->oobsize; ++ ++ column = to & (mtd->oobsize - 1); ++ ++ if (unlikely(column >= oobsize)) { ++ printk(KERN_ERR "onenand_write_oob_nolock: Attempted to start write outside oob\n"); ++ return -EINVAL; ++ } ++ ++ /* For compatibility with NAND: Do not allow write past end of page */ ++ if (unlikely(column + len > oobsize)) { ++ printk(KERN_ERR "onenand_write_oob_nolock: " ++ "Attempt to write past end of page\n"); ++ return -EINVAL; ++ } ++ ++ /* Do not allow reads past end of device */ ++ if (unlikely(to >= mtd->size || ++ column + len > ((mtd->size >> chip->page_shift) - ++ (to >> chip->page_shift)) * oobsize)) { ++ printk(KERN_ERR "onenand_write_oob_nolock: Attempted to write past end of device\n"); ++ return -EINVAL; ++ } ++ ++ /* Grab the lock and see if the device is available */ ++ onenand_get_device(mtd, FL_WRITING); ++ ++ orgbuf = buf; ++ oobbuf = chip->oob_buf; ++ buf_poi = (u_int *)chip->oob_buf; ++ ++ /* on the TRANSFER SPARE bit */ ++ chip->write(ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE); ++ ++ /* Loop until all data write */ ++ while (written < len) { ++ int thislen = min_t(int, oobsize, len - written); ++ ++ if (chip->options & ONENAND_CHECK_BAD) { ++ if (onenand_block_isbad(mtd, to)) { ++ printk (KERN_WARNING "\nonenand_do_write_oob: skipped to write oob to a bad block at addr 0x%08x.\n", (unsigned int) to); ++ to += (1 << chip->erase_shift); ++ ++ if (column != 0) ++ column = to & (mtd->oobsize - 1); ++ ++ continue; ++ } ++ } ++ ++ /* get start address to write data */ ++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_PROG, to)); ++ ++ /* We send data to spare ram with oobsize ++ * to prevent byte access */ ++ memset(oobbuf, 0xff, mtd->oobsize); ++ ++ if (mode == MTD_OOB_AUTO) ++ onenand_fill_auto_oob(mtd, oobbuf, buf, column, thislen); ++ else ++ memcpy(oobbuf + column, buf, thislen); ++ ++ for (i = 0; i < (mtd->writesize / 4); i++) ++ chip->write(0xffffffff, cmd_addr); ++ ++ for (i = 0; i < (mtd->oobsize / 4); i++) { ++ chip->write(*buf_poi, cmd_addr); ++ buf_poi++; ++ } ++ ++ if (onenand_blkrw_complete(chip, ONENAND_CMD_PROG)) { ++ printk(KERN_WARNING "onenand_write_oob_nolock: Program operation failed.\n"); ++ chip->write(~ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE); ++ return -1; ++ } ++ ++#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE ++ ret = onenand_verify_oob(mtd, orgbuf, to, len); ++ ++ if (ret) { ++ printk(KERN_ERR "onenand_write_oob_nolock: verify failed :0x%x\n", (unsigned int)to); ++ break; ++ } ++#endif ++ written += thislen; ++ ++ if (written == len) ++ break; ++ ++ to += mtd->writesize; ++ buf += thislen; ++ column = 0; ++ } ++ ++ /* off the TRANSFER SPARE bit */ ++ chip->write(~ONENAND_TRANS_SPARE_TSRF_INC, chip->base + ONENAND_REG_TRANS_SPARE); ++ ++ /* Deselect and wake up anyone waiting on the device */ ++ onenand_release_device(mtd); ++ ++ ops->oobretlen = written; ++ ++ return ret; ++} ++ ++/** ++ * onenand_write_oob - [MTD Interface] NAND write data and/or out-of-band ++ * @param mtd: MTD device structure ++ * @param to: offset to write ++ * @param ops: oob operation description structure ++ */ ++static int onenand_write_oob(struct mtd_info *mtd, loff_t to, ++ struct mtd_oob_ops *ops) ++{ ++ int ret; ++ ++ switch (ops->mode) { ++ case MTD_OOB_PLACE: ++ case MTD_OOB_AUTO: ++ break; ++ case MTD_OOB_RAW: ++ /* Not implemented yet */ ++ default: ++ return -EINVAL; ++ } ++ ++ if (ops->datbuf != NULL) ++ ret = onenand_write_ops_nolock(mtd, to, ops); ++ else ++ ret = onenand_write_oob_nolock(mtd, to, ops); ++ return ret; ++ ++} ++ ++/** ++ * onenand_erase - [MTD Interface] erase block(s) ++ * @param mtd MTD device structure ++ * @param instr erase instruction ++ * ++ * Erase one ore more blocks ++ */ ++static int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ unsigned int block_size; ++ loff_t addr; ++ int len, ret = 0; ++ void __iomem *cmd_addr; ++ ++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len); ++ ++ block_size = (1 << chip->erase_shift); ++ ++ /* Start address must align on block boundary */ ++ if (unlikely(instr->addr & (block_size - 1))) { ++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: Unaligned address\n"); ++ return -EINVAL; ++ } ++ ++ /* Length must align on block boundary */ ++ if (unlikely(instr->len & (block_size - 1))) { ++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: Length not block aligned\n"); ++ return -EINVAL; ++ } ++ ++ /* Do not allow erase past end of device */ ++ if (unlikely((instr->len + instr->addr) > mtd->size)) { ++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: Erase past end of device\n"); ++ return -EINVAL; ++ } ++ ++ instr->fail_addr = 0xffffffff; ++ ++ /* Grab the lock and see if the device is available */ ++ onenand_get_device(mtd, FL_ERASING); ++ ++ /* Loop throught the pages */ ++ len = instr->len; ++ addr = instr->addr; ++ ++ instr->state = MTD_ERASING; ++ ++ while (len) { ++ if (chip->options & ONENAND_CHECK_BAD) { ++ ++ /* Check if we have a bad block, we do not erase bad blocks */ ++ if (onenand_block_isbad_nolock(mtd, addr, 0)) { ++ printk (KERN_WARNING "onenand_erase: attempt to erase a bad block at addr 0x%08x\n", (unsigned int) addr); ++ instr->state = MTD_ERASE_FAILED; ++ goto erase_exit; ++ } ++ } ++ ++ /* get address to erase */ ++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_ERASE, addr)); ++ ++ chip->write(ONENAND_DATAIN_ERASE_SINGLE, cmd_addr); /* single block erase */ ++ ++ /* wait irq */ ++ onenand_irq_wait_ack(chip, ONENAND_INT_ERR_INT_ACT); ++ onenand_irq_wait_ack(chip, ONENAND_INT_ERR_ERS_CMP); ++ ++ chip->write(ONENAND_DATAIN_ERASE_VERIFY, cmd_addr); ++ ++ /* wait irq */ ++ onenand_irq_wait_ack(chip, ONENAND_INT_ERR_INT_ACT); ++ onenand_irq_wait_ack(chip, ONENAND_INT_ERR_ERS_CMP); ++ ++ /* check fail */ ++ if (onenand_irq_pend(chip, ONENAND_INT_ERR_ERS_FAIL)) { ++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: block %d erase verify failed.\n", ((unsigned int)addr >> chip->erase_shift)); ++ onenand_irq_ack(chip, ONENAND_INT_ERR_ERS_FAIL); ++ ++ /* check lock */ ++ if (onenand_irq_pend(chip, ONENAND_INT_ERR_LOCKED_BLK)) { ++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: block %d is locked.\n", ((unsigned int)addr >> chip->erase_shift)); ++ onenand_irq_ack(chip, ONENAND_INT_ERR_LOCKED_BLK); ++ } ++ } ++ ++ len -= block_size; ++ addr += block_size; ++ } ++ ++ instr->state = MTD_ERASE_DONE; ++ ++erase_exit: ++ ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; ++ /* Do call back function */ ++ if (!ret) ++ mtd_erase_callback(instr); ++ ++ /* Deselect and wake up anyone waiting on the device */ ++ onenand_release_device(mtd); ++ ++ return ret; ++} ++ ++/** ++ * onenand_sync - [MTD Interface] sync ++ * @param mtd MTD device structure ++ * ++ * Sync is actually a wait for chip ready function ++ */ ++static void onenand_sync(struct mtd_info *mtd) ++{ ++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_sync: called\n"); ++ ++ /* Grab the lock and see if the device is available */ ++ onenand_get_device(mtd, FL_SYNCING); ++ ++ /* Release it and go back */ ++ onenand_release_device(mtd); ++} ++ ++/** ++ * onenand_do_lock_cmd - [OneNAND Interface] Lock or unlock block(s) ++ * @param mtd MTD device structure ++ * @param ofs offset relative to mtd start ++ * @param len number of bytes to lock or unlock ++ * ++ * Lock or unlock one or more blocks ++ */ ++static int onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs, size_t len, int cmd) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ int start, end, ofs_end, block_size; ++ int datain1, datain2; ++ void __iomem *cmd_addr; ++ ++ start = ofs >> chip->erase_shift; ++ end = len >> chip->erase_shift; ++ block_size = 1 << chip->erase_shift; ++ ofs_end = ofs + len - block_size; ++ ++ if (cmd == ONENAND_CMD_LOCK) { ++ datain1 = ONENAND_DATAIN_LOCK_START; ++ datain2 = ONENAND_DATAIN_LOCK_END; ++ } else { ++ datain1 = ONENAND_DATAIN_UNLOCK_START; ++ datain2 = ONENAND_DATAIN_UNLOCK_END; ++ } ++ ++ if (ofs < ofs_end) { ++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, cmd, ofs)); ++ chip->write(datain1, cmd_addr); ++ } ++ ++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, cmd, ofs)); ++ chip->write(datain2, cmd_addr); ++ ++ if (cmd == ONENAND_CMD_LOCK) { ++ if (!chip->read(chip->base + ONENAND_REG_INT_ERR_STAT) & ONENAND_INT_ERR_LOCKED_BLK) { ++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_do_lock_cmd: lock failed.\n"); ++ return -1; ++ } ++ } else { ++ if (chip->read(chip->base + ONENAND_REG_INT_ERR_STAT) & ONENAND_INT_ERR_LOCKED_BLK) { ++ DEBUG(MTD_DEBUG_LEVEL3, "onenand_do_lock_cmd: unlock failed.\n"); ++ return -1; ++ } ++ } ++ ++ return 0; ++} ++ ++/** ++ * onenand_lock - [MTD Interface] Lock block(s) ++ * @param mtd MTD device structure ++ * @param ofs offset relative to mtd start ++ * @param len number of bytes to lock ++ * ++ * Lock one or more blocks ++ */ ++static int onenand_lock(struct mtd_info *mtd, loff_t ofs, size_t len) ++{ ++ return onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_LOCK); ++} ++ ++/** ++ * onenand_unlock - [MTD Interface] Unlock block(s) ++ * @param mtd MTD device structure ++ * @param ofs offset relative to mtd start ++ * @param len number of bytes to unlock ++ * ++ * Unlock one or more blocks ++ */ ++int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len) ++{ ++ return onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK); ++} ++ ++/** ++ * onenand_check_lock_status - [OneNAND Interface] Check lock status ++ * @param this onenand chip data structure ++ * ++ * Check lock status ++ */ ++static void onenand_check_lock_status(struct mtd_info *mtd) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ unsigned int block, end; ++ void __iomem *cmd_addr; ++ int tmp; ++ ++ end = chip->chipsize >> chip->erase_shift; ++ ++ for (block = 0; block < end; block++) { ++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_READ, block << chip->erase_shift)); ++ tmp = chip->read(cmd_addr); ++ ++ if (chip->read(chip->base + ONENAND_REG_INT_ERR_STAT) & ONENAND_INT_ERR_LOCKED_BLK) { ++ printk(KERN_ERR "block %d is write-protected!\n", block); ++ chip->write(ONENAND_INT_ERR_LOCKED_BLK, chip->base + ONENAND_REG_INT_ERR_ACK); ++ } ++ } ++} ++ ++/** ++ * onenand_unlock_all - [OneNAND Interface] unlock all blocks ++ * @param mtd MTD device structure ++ * ++ * Unlock all blocks ++ */ ++static int onenand_unlock_all(struct mtd_info *mtd) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ void __iomem *cmd_addr; ++ ++ if (chip->options & ONENAND_HAS_UNLOCK_ALL) { ++ /* write unlock command */ ++ cmd_addr = onenand_phys_to_virt(chip->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0)); ++ chip->write(ONENAND_DATAIN_UNLOCK_ALL, cmd_addr); ++ ++ /* Workaround for all block unlock in DDP */ ++ if (chip->device_id & ONENAND_DEVICE_IS_DDP) { ++ loff_t ofs; ++ size_t len; ++ ++ /* 1st block on another chip */ ++ ofs = chip->chipsize >> 1; ++ len = 1 << chip->erase_shift; ++ ++ onenand_unlock(mtd, ofs, len); ++ } ++ ++ onenand_check_lock_status(mtd); ++ ++ return 0; ++ } ++ ++ onenand_unlock(mtd, 0x0, chip->chipsize); ++ ++ return 0; ++} ++ ++/** ++ * onenand_lock_scheme - Check and set OneNAND lock scheme ++ * @param mtd MTD data structure ++ * ++ * Check and set OneNAND lock scheme ++ */ ++static void onenand_lock_scheme(struct mtd_info *mtd) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ unsigned int density, process; ++ ++ /* Lock scheme depends on density and process */ ++ density = chip->device_id >> ONENAND_DEVICE_DENSITY_SHIFT; ++ process = chip->version_id >> ONENAND_VERSION_PROCESS_SHIFT; ++ ++ /* Lock scheme */ ++ if (density >= ONENAND_DEVICE_DENSITY_1Gb) { ++ /* A-Die has all block unlock */ ++ if (process) { ++ printk(KERN_DEBUG "Chip support all block unlock\n"); ++ chip->options |= ONENAND_HAS_UNLOCK_ALL; ++ } ++ } else { ++ /* Some OneNAND has continues lock scheme */ ++ if (!process) { ++ printk(KERN_DEBUG "Lock scheme is Continues Lock\n"); ++ chip->options |= ONENAND_HAS_CONT_LOCK; ++ } ++ } ++} ++ ++/** ++ * onenand_print_device_info - Print device ID ++ * @param device device ID ++ * ++ * Print device ID ++ */ ++void onenand_print_device_info(int device, int version) ++{ ++ int vcc, demuxed, ddp, density; ++ ++ vcc = device & ONENAND_DEVICE_VCC_MASK; ++ demuxed = device & ONENAND_DEVICE_IS_DEMUX; ++ ddp = device & ONENAND_DEVICE_IS_DDP; ++ density = device >> ONENAND_DEVICE_DENSITY_SHIFT; ++ printk(KERN_INFO "%sOneNAND%s %dMB %sV 16-bit (0x%02x)\n", ++ demuxed ? "" : "Muxed ", ++ ddp ? "(DDP)" : "", ++ (16 << density), ++ vcc ? "2.65/3.3" : "1.8", ++ device); ++ printk(KERN_DEBUG "OneNAND version = 0x%04x\n", version); ++} ++ ++static const struct onenand_manufacturers onenand_manuf_ids[] = { ++ {ONENAND_MFR_SAMSUNG, "Samsung"}, ++}; ++ ++/** ++ * onenand_check_maf - Check manufacturer ID ++ * @param manuf manufacturer ID ++ * ++ * Check manufacturer ID ++ */ ++static int onenand_check_maf(int manuf) ++{ ++ int size = ARRAY_SIZE(onenand_manuf_ids); ++ char *name; ++ int i; ++ ++ for (i = 0; i < size; i++) ++ if (manuf == onenand_manuf_ids[i].id) ++ break; ++ ++ if (i < size) ++ name = onenand_manuf_ids[i].name; ++ else ++ name = "Unknown"; ++ ++ printk(KERN_DEBUG "OneNAND Manufacturer: %s (0x%0x)\n", name, manuf); ++ ++ return (i == size); ++} ++ ++/** ++ * onenand_suspend - [MTD Interface] Suspend the OneNAND flash ++ * @param mtd MTD device structure ++ */ ++static int onenand_suspend(struct mtd_info *mtd) ++{ ++ return onenand_get_device(mtd, FL_PM_SUSPENDED); ++} ++ ++/** ++ * onenand_resume - [MTD Interface] Resume the OneNAND flash ++ * @param mtd MTD device structure ++ */ ++static void onenand_resume(struct mtd_info *mtd) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ ++ if (chip->state == FL_PM_SUSPENDED) ++ onenand_release_device(mtd); ++ else ++ printk(KERN_ERR "resume() called for the chip which is not" ++ "in suspended state\n"); ++} ++ ++/* ++ * Setting address width registers ++ * (FBA_WIDTH, FPA_WIDTH, FSA_WIDTH, DFS_DBS_WIDTH) ++ */ ++static void s3c_onenand_width_regs(struct onenand_chip *chip) ++{ ++ int dev_id, ddp, density; ++ int w_dfs_dbs = 0, w_fba = 10, w_fpa = 6, w_fsa = 2; ++ ++ dev_id = readl(chip->base + ONENAND_REG_DEVICE_ID); ++ ++ ddp = dev_id & ONENAND_DEVICE_IS_DDP; ++ density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT; ++ ++ switch (density & 0xf) { ++ case ONENAND_DEVICE_DENSITY_128Mb: ++ w_dfs_dbs = 0; ++ w_fba = 8; ++ w_fpa = 6; ++ w_fsa = 1; ++ break; ++ ++ case ONENAND_DEVICE_DENSITY_256Mb: ++ w_dfs_dbs = 0; ++ w_fba = 9; ++ w_fpa = 6; ++ w_fsa = 1; ++ break; ++ ++ case ONENAND_DEVICE_DENSITY_512Mb: ++ w_dfs_dbs = 0; ++ w_fba = 9; ++ w_fpa = 6; ++ w_fsa = 2; ++ break; ++ ++ case ONENAND_DEVICE_DENSITY_1Gb: ++ if (ddp) { ++ w_dfs_dbs = 1; ++ w_fba = 9; ++ } else { ++ w_dfs_dbs = 0; ++ w_fba = 10; ++ } ++ ++ w_fpa = 6; ++ w_fsa = 2; ++ break; ++ ++ case ONENAND_DEVICE_DENSITY_2Gb: ++ if (ddp) { ++ w_dfs_dbs = 1; ++ w_fba = 10; ++ } else { ++ w_dfs_dbs = 0; ++ w_fba = 11; ++ } ++ ++ w_fpa = 6; ++ w_fsa = 2; ++ break; ++ ++ case ONENAND_DEVICE_DENSITY_4Gb: ++ if (ddp) { ++ w_dfs_dbs = 1; ++ w_fba = 11; ++ } else { ++ w_dfs_dbs = 0; ++ w_fba = 12; ++ } ++ ++ w_fpa = 6; ++ w_fsa = 2; ++ break; ++ } ++ ++ writel(w_fba, chip->base + ONENAND_REG_FBA_WIDTH); ++ writel(w_fpa, chip->base + ONENAND_REG_FPA_WIDTH); ++ writel(w_fsa, chip->base + ONENAND_REG_FSA_WIDTH); ++ writel(w_dfs_dbs, chip->base + ONENAND_REG_DBS_DFS_WIDTH); ++} ++ ++/* ++ * Board-specific NAND initialization. The following members of the ++ * argument are board-specific (per include/linux/mtd/nand.h): ++ * - base : address that OneNAND is located at. ++ * - scan_bbt: board specific bad block scan function. ++ * Members with a "?" were not set in the merged testing-NAND branch, ++ * so they are not set here either. ++ */ ++static int s3c_onenand_init (struct onenand_chip *chip) ++{ ++ int value; ++ ++ chip->options |= (ONENAND_READ_BURST | ONENAND_CHECK_BAD | ONENAND_PIPELINE_AHEAD); ++ ++ /*** Initialize Controller ***/ ++ ++#if defined(CONFIG_CPU_S5PC100) ++ /* D0 Domain OneNAND Clock Gating */ ++ value = readl(S5P_SCLKGATE0); ++ value = (value & ~(1 << 2)) | (1<< 2); ++ writel(value, S5P_SCLKGATE0); ++ ++ /* ONENAND Select */ ++ value = readl(S5P_CLK_SRC0); ++ value = value & ~(1 << 24); ++ value = value & ~(1 << 20); ++ writel(value, S5P_CLK_SRC0); ++ ++ /* SYSCON */ ++ value = readl(S5P_CLK_DIV1); ++ value = (value & ~(3 << 16)) | (1 << 16); ++ writel(value, S5P_CLK_DIV1); ++ ++#elif defined(CONFIG_CPU_S3C6410) ++ /* SYSCON */ ++ value = readl(S3C_CLK_DIV0); ++ value = (value & ~(3 << 16)) | (1 << 16); ++ writel(value, S3C_CLK_DIV0); ++ ++ writel(ONENAND_FLASH_AUX_WD_DISABLE, chip->base + ONENAND_REG_FLASH_AUX_CNTRL); ++#endif ++ ++ /* Cold Reset */ ++ writel(ONENAND_MEM_RESET_COLD, chip->base + ONENAND_REG_MEM_RESET); ++ ++ /* Access Clock Register */ ++ writel(ONENAND_ACC_CLOCK_134_67, chip->base + ONENAND_REG_ACC_CLOCK); ++ ++ /* FBA, FPA, FSA, DBS_DFS Width Register */ ++ s3c_onenand_width_regs(chip); ++ ++ /* Enable Interrupts */ ++ writel(0x3ff, chip->base + ONENAND_REG_INT_ERR_MASK); ++ writel(ONENAND_INT_PIN_ENABLE, chip->base + ONENAND_REG_INT_PIN_ENABLE); ++ writel(readl(chip->base + ONENAND_REG_INT_ERR_MASK) & ~(ONENAND_INT_ERR_RDY_ACT), ++ chip->base + ONENAND_REG_INT_ERR_MASK); ++ ++ /* Memory Device Configuration Register */ ++ value = (ONENAND_MEM_CFG_SYNC_READ | ONENAND_MEM_CFG_BRL_4 | \ ++ ONENAND_MEM_CFG_BL_16| ONENAND_MEM_CFG_IOBE | \ ++ ONENAND_MEM_CFG_INT_HIGH | ONENAND_MEM_CFG_RDY_HIGH); ++ writel(value, chip->base + ONENAND_REG_MEM_CFG); ++ ++ /* Burst Length Register */ ++ writel(ONENAND_BURST_LEN_16, chip->base + ONENAND_REG_BURST_LEN); ++ ++#ifdef CONFIG_MTD_ONENAND_CHECK_SPEED ++ writel((readl(S3C_GPNCON) & ~(0x3 << 30)) | (0x1 << 30), S3C_GPNCON); ++ writel(0 << 15, S3C_GPNDAT); ++#endif ++ ++ return 0; ++} ++ ++/** ++ * onenand_probe - [OneNAND Interface] Probe the OneNAND device ++ * @param mtd MTD device structure ++ * ++ * OneNAND detection method: ++ * Compare the the values from command with ones from register ++ */ ++static int onenand_probe(struct mtd_info *mtd) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ int maf_id, dev_id, ver_id, density; ++ ++ s3c_onenand_init(chip); ++ ++ chip->dev_base = (void __iomem *)ioremap_nocache(ONENAND_AHB_ADDR, SZ_256M); ++ ++ if (!chip->dev_base) { ++ printk("ioremap failed.\n"); ++ return -1; ++ } ++ ++ printk("onenand_probe: OneNAND memory device is remapped at 0x%08x.\n", (u_int) chip->dev_base); ++ ++ chip->dma = ONENAND_DMA_CON; ++ chip->dma_ch = DMACH_ONENAND_IN; ++ ++ /* Read manufacturer and device IDs from Register */ ++ maf_id = chip->read(chip->base + ONENAND_REG_MANUFACT_ID); ++ dev_id = chip->read(chip->base + ONENAND_REG_DEVICE_ID); ++ ver_id = chip->read(chip->base + ONENAND_REG_FLASH_VER_ID); ++ ++ /* Check manufacturer ID */ ++ if (onenand_check_maf(maf_id)) ++ return -ENXIO; ++ ++ /* Flash device information */ ++ onenand_print_device_info(dev_id, ver_id); ++ chip->device_id = dev_id; ++ chip->version_id = ver_id; ++ ++ density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT; ++ chip->chipsize = (16 << density) << 20; ++ /* Set density mask. it is used for DDP */ ++ chip->density_mask = (1 << (density + 6)); ++ ++ /* OneNAND page size & block size */ ++ /* The data buffer size is equal to page size */ ++ mtd->writesize = chip->read(chip->base + ONENAND_REG_DATA_BUF_SIZE); ++ mtd->oobsize = mtd->writesize >> 5; ++ /* Pagers per block is always 64 in OneNAND */ ++ mtd->erasesize = mtd->writesize << 6; ++ ++ chip->erase_shift = ffs(mtd->erasesize) - 1; ++ chip->page_shift = ffs(mtd->writesize) - 1; ++ chip->page_mask = (mtd->erasesize / mtd->writesize) - 1; ++ ++ /* REVIST: Multichip handling */ ++ ++ mtd->size = chip->chipsize; ++ ++ /* Check OneNAND lock scheme */ ++ onenand_lock_scheme(mtd); ++ ++ return 0; ++} ++ ++/** ++ * onenand_block_markbad - [MTD Interface] Mark the block at the given offset as bad ++ * @param mtd MTD device structure ++ * @param ofs offset relative to mtd start ++ * ++ * Mark the block as bad ++ */ ++static int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ int ret; ++ ++ if (chip->options & ONENAND_CHECK_BAD) { ++ ret = onenand_block_isbad(mtd, ofs); ++ if (ret) { ++ /* If it was bad already, return success and do nothing */ ++ if (ret > 0) ++ return 0; ++ return ret; ++ } ++ ++ return chip->block_markbad(mtd, ofs); ++ } else ++ return 0; ++} ++ ++int s3c_onenand_scan_bbt(struct mtd_info *mtd) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ ++ if (chip->options & ONENAND_CHECK_BAD) ++ return onenand_default_bbt(mtd); ++ else ++ return 0; ++} ++ ++/** ++ * onenand_scan - [OneNAND Interface] Scan for the OneNAND device ++ * @param mtd MTD device structure ++ * @param maxchips Number of chips to scan for ++ * ++ * This fills out all the not initialized function pointers ++ * with the defaults. ++ * The flash ID is read and the mtd/chip structures are ++ * filled with the appropriate values. ++ */ ++int onenand_scan(struct mtd_info *mtd, int maxchips) ++{ ++ int i; ++ struct onenand_chip *chip = mtd->priv; ++ ++ if (!chip->read) ++ chip->read = onenand_readl; ++ ++ if (!chip->write) ++ chip->write = onenand_writel; ++ ++ if (!chip->command) ++ chip->command = onenand_command; ++ ++ if (!chip->block_markbad) ++ chip->block_markbad = onenand_default_block_markbad; ++ ++ if (!chip->scan_bbt) ++ chip->scan_bbt = s3c_onenand_scan_bbt; ++ ++ if (onenand_probe(mtd)) ++ return -ENXIO; ++ ++ /* Allocate buffers, if necessary */ ++ if (!chip->page_buf) { ++ size_t len; ++ len = mtd->writesize + mtd->oobsize; ++ chip->page_buf = kmalloc(len, GFP_KERNEL); ++ if (!chip->page_buf) { ++ printk(KERN_ERR "onenand_scan(): Can't allocate page_buf\n"); ++ return -ENOMEM; ++ } ++ chip->options |= ONENAND_PAGEBUF_ALLOC; ++ } ++ ++ if (!chip->oob_buf) { ++ chip->oob_buf = kzalloc(mtd->oobsize, GFP_KERNEL); ++ if (!chip->oob_buf) { ++ printk(KERN_ERR "onenand_scan(): Can't allocate oob_buf\n"); ++ if (chip->options & ONENAND_PAGEBUF_ALLOC) { ++ chip->options &= ~ONENAND_PAGEBUF_ALLOC; ++ kfree(chip->page_buf); ++ } ++ return -ENOMEM; ++ } ++ chip->options |= ONENAND_OOBBUF_ALLOC; ++ } ++ ++ /* ++ * Allow subpage writes up to oobsize. ++ */ ++ switch (mtd->oobsize) { ++ case 64: ++ chip->ecclayout = &onenand_oob_64; ++ mtd->subpage_sft = 2; ++ break; ++ ++ case 32: ++ chip->ecclayout = &onenand_oob_32; ++ mtd->subpage_sft = 1; ++ break; ++ ++ default: ++ printk(KERN_WARNING "No OOB scheme defined for oobsize %d\n", ++ mtd->oobsize); ++ mtd->subpage_sft = 0; ++ /* To prevent kernel oops */ ++ chip->ecclayout = &onenand_oob_32; ++ break; ++ } ++ ++ chip->subpagesize = mtd->writesize >> mtd->subpage_sft; ++ ++ /* ++ * The number of bytes available for a client to place data into ++ * the out of band area ++ */ ++ chip->ecclayout->oobavail = 0; ++ for (i = 0; chip->ecclayout->oobfree[i].length; i++) ++ chip->ecclayout->oobavail += ++ chip->ecclayout->oobfree[i].length; ++ mtd->oobavail = chip->ecclayout->oobavail; ++ ++ mtd->ecclayout = chip->ecclayout; ++ ++ /* Fill in remaining MTD driver data */ ++ mtd->type = MTD_NANDFLASH; ++ mtd->flags = MTD_CAP_NANDFLASH; ++ mtd->erase = onenand_erase; ++ mtd->point = NULL; ++ mtd->unpoint = NULL; ++ mtd->read = onenand_read; ++ mtd->write = onenand_write; ++ mtd->read_oob = onenand_read_oob; ++ mtd->write_oob = onenand_write_oob; ++ mtd->sync = onenand_sync; ++ mtd->lock = onenand_lock; ++ mtd->unlock = onenand_unlock; ++ mtd->block_isbad = onenand_block_isbad; ++ mtd->block_markbad = onenand_block_markbad; ++ mtd->suspend = onenand_suspend; ++ mtd->resume = onenand_resume; ++ mtd->owner = THIS_MODULE; ++ ++ /* Unlock whole block */ ++ onenand_unlock_all(mtd); ++ ++ return chip->scan_bbt(mtd); ++} ++ ++/** ++ * onenand_release - [OneNAND Interface] Free resources held by the OneNAND device ++ * @param mtd MTD device structure ++ */ ++void onenand_release(struct mtd_info *mtd) ++{ ++ struct onenand_chip *chip = mtd->priv; ++ ++#ifdef CONFIG_MTD_PARTITIONS ++ /* Deregister partitions */ ++ del_mtd_partitions (mtd); ++#endif ++ /* Deregister the device */ ++ del_mtd_device (mtd); ++ ++ /* Free bad block table memory, if allocated */ ++ if (chip->bbm) { ++ struct bbm_info *bbm = chip->bbm; ++ kfree(bbm->bbt); ++ kfree(chip->bbm); ++ } ++ ++ /* Buffer allocated by onenand_scan */ ++ if (chip->options & ONENAND_PAGEBUF_ALLOC) ++ kfree(chip->page_buf); ++ if (chip->options & ONENAND_OOBBUF_ALLOC) ++ kfree(chip->oob_buf); ++} ++ ++EXPORT_SYMBOL_GPL(onenand_scan); ++EXPORT_SYMBOL_GPL(onenand_release); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Jinsung Yang "); ++MODULE_DESCRIPTION("S3C OneNAND Controller Driver"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/mtd/onenand/s3c_onenand.h linux-2.6.28.6/drivers/mtd/onenand/s3c_onenand.h +--- linux-2.6.28/drivers/mtd/onenand/s3c_onenand.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/mtd/onenand/s3c_onenand.h 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,159 @@ ++#ifndef __LINUX_MTD_S3C_ONENAND_H ++#define __LINUX_MTD_S3C_ONENAND_H ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MAX_BUFFERRAM 2 ++ ++/* Scan and identify a OneNAND device */ ++extern int onenand_scan(struct mtd_info *mtd, int max_chips); ++/* Free resources held by the OneNAND device */ ++extern void onenand_release(struct mtd_info *mtd); ++ ++/* ++ * onenand_state_t - chip states ++ * Enumeration for OneNAND flash chip state ++ */ ++typedef enum { ++ FL_READY, ++ FL_READING, ++ FL_WRITING, ++ FL_ERASING, ++ FL_SYNCING, ++ FL_LOCKING, ++ FL_RESETING, ++ FL_OTPING, ++ FL_PM_SUSPENDED, ++} onenand_state_t; ++ ++/** ++ * struct onenand_bufferram - OneNAND BufferRAM Data ++ * @block: block address in BufferRAM ++ * @page: page address in BufferRAM ++ * @valid: valid flag ++ */ ++struct onenand_bufferram { ++ int block; ++ int page; ++ int valid; ++}; ++ ++/** ++ * struct onenand_chip - OneNAND Private Flash Chip Data ++ * @base: [BOARDSPECIFIC] address to access OneNAND ++ * @chipsize: [INTERN] the size of one chip for multichip arrays ++ * @device_id: [INTERN] device ID ++ * @density_mask: chip density, used for DDP devices ++ * @verstion_id: [INTERN] version ID ++ * @options: [BOARDSPECIFIC] various chip options. They can ++ * partly be set to inform onenand_scan about ++ * @erase_shift: [INTERN] number of address bits in a block ++ * @page_shift: [INTERN] number of address bits in a page ++ * @page_mask: [INTERN] a page per block mask ++ * @bufferram_index: [INTERN] BufferRAM index ++ * @bufferram: [INTERN] BufferRAM info ++ * @readw: [REPLACEABLE] hardware specific function for read short ++ * @writew: [REPLACEABLE] hardware specific function for write short ++ * @command: [REPLACEABLE] hardware specific function for writing ++ * commands to the chip ++ * @wait: [REPLACEABLE] hardware specific function for wait on ready ++ * @read_bufferram: [REPLACEABLE] hardware specific function for BufferRAM Area ++ * @write_bufferram: [REPLACEABLE] hardware specific function for BufferRAM Area ++ * @read_word: [REPLACEABLE] hardware specific function for read ++ * register of OneNAND ++ * @write_word: [REPLACEABLE] hardware specific function for write ++ * register of OneNAND ++ * @mmcontrol: sync burst read function ++ * @block_markbad: function to mark a block as bad ++ * @scan_bbt: [REPLACEALBE] hardware specific function for scanning ++ * Bad block Table ++ * @chip_lock: [INTERN] spinlock used to protect access to this ++ * structure and the chip ++ * @wq: [INTERN] wait queue to sleep on if a OneNAND ++ * operation is in progress ++ * @state: [INTERN] the current state of the OneNAND device ++ * @page_buf: data buffer ++ * @subpagesize: [INTERN] holds the subpagesize ++ * @ecclayout: [REPLACEABLE] the default ecc placement scheme ++ * @bbm: [REPLACEABLE] pointer to Bad Block Management ++ * @priv: [OPTIONAL] pointer to private chip date ++ */ ++struct onenand_chip { ++ void __iomem *base; /* SFR base address (0x7010_0000 ~) */ ++ void __iomem *dev_base; /* virtual address base for AHB Port Address (0x2000_0000 ~ 0x20FF_FFFF) */ ++ unsigned int chipsize; ++ unsigned int device_id; ++ unsigned int version_id; ++ unsigned int density_mask; ++ unsigned int options; ++ ++ unsigned int erase_shift; ++ unsigned int page_shift; ++ unsigned int page_mask; ++ ++ unsigned int bufferram_index; ++ struct onenand_bufferram bufferram[MAX_BUFFERRAM]; ++ ++ uint (*command)(struct mtd_info *mtd, int cmd, loff_t address); ++ unsigned int (*read)(void __iomem *addr); ++ void (*write)(unsigned int value, void __iomem *addr); ++ int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); ++ int (*scan_bbt)(struct mtd_info *mtd); ++ ++ int irq; ++ ++ spinlock_t chip_lock; ++ wait_queue_head_t wq; ++ onenand_state_t state; ++ ++ unsigned char *page_buf; ++ unsigned char *oob_buf; ++ ++ int subpagesize; ++ struct nand_ecclayout *ecclayout; ++ ++ void *bbm; ++ void *priv; ++ ++ int dma; ++ unsigned int dma_ch; ++ void *done; /* completion */ ++}; ++ ++/* ++ * Options bits ++ */ ++#define ONENAND_HAS_CONT_LOCK (0x0001) ++#define ONENAND_HAS_UNLOCK_ALL (0x0002) ++#define ONENAND_CHECK_BAD (0x0004) ++#define ONENAND_READ_POLLING (0x0010) ++#define ONENAND_READ_BURST (0x0020) ++#define ONENAND_READ_DMA (0x0040) ++#define ONENAND_PIPELINE_AHEAD (0x0100) ++#define ONENAND_READ_MASK (0x00F0) ++#define ONENAND_PAGEBUF_ALLOC (0x1000) ++#define ONENAND_OOBBUF_ALLOC (0x2000) ++ ++/* ++ * OneNAND Flash Manufacturer ID Codes ++ */ ++#define ONENAND_MFR_SAMSUNG 0xec ++ ++/** ++ * struct onenand_manufacturers - NAND Flash Manufacturer ID Structure ++ * @name: Manufacturer name ++ * @id: manufacturer ID code of device. ++*/ ++struct onenand_manufacturers { ++ int id; ++ char *name; ++}; ++ ++#endif /* __LINUX_MTD_ONENAND_H */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/net/Kconfig linux-2.6.28.6/drivers/net/Kconfig +--- linux-2.6.28/drivers/net/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/net/Kconfig 2010-04-07 07:35:34.000000000 +0200 +@@ -918,7 +918,7 @@ + will be called netx-eth. + + config DM9000 +- tristate "DM9000 support" ++ tristate "normal DM9000 support" + depends on ARM || BLACKFIN || MIPS + select CRC32 + select MII +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/net/dm9000.c linux-2.6.28.6/drivers/net/dm9000.c +--- linux-2.6.28/drivers/net/dm9000.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/net/dm9000.c 2010-04-07 07:43:22.000000000 +0200 +@@ -1,5 +1,7 @@ + /* +- * Davicom DM9000 Fast Ethernet driver for Linux. ++ * dm9000.c: Version 1.2 03/18/2003 ++ * ++ * A Davicom DM9000 ISA NIC fast Ethernet driver for Linux. + * Copyright (C) 1997 Sten Wang + * + * This program is free software; you can redistribute it and/or +@@ -12,11 +14,44 @@ + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * +- * (C) Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. ++ * (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. ++ * ++ * V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match ++ * 06/22/2001 Support DM9801 progrmming ++ * E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000 ++ * E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200 ++ * R17 = (R17 & 0xfff0) | NF + 3 ++ * E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200 ++ * R17 = (R17 & 0xfff0) | NF ++ * ++ * v1.00 modify by simon 2001.9.5 ++ * change for kernel 2.4.x ++ * ++ * v1.1 11/09/2001 fix force mode bug ++ * ++ * v1.2 03/18/2003 Weilun Huang : ++ * Fixed phy reset. ++ * Added tx/rx 32 bit mode. ++ * Cleaned up for kernel merge. ++ * ++ * 03/03/2004 Sascha Hauer ++ * Port to 2.6 kernel ++ * ++ * 24-Sep-2004 Ben Dooks ++ * Cleanup of code to remove ifdefs ++ * Allowed platform device data to influence access width ++ * Reformatting areas of code ++ * ++ * 17-Mar-2005 Sascha Hauer ++ * * removed 2.4 style module parameters ++ * * removed removed unused stat counter and fixed ++ * net_device_stats ++ * * introduced tx_timeout function ++ * * reworked locking + * +- * Additional updates, Copyright: +- * Ben Dooks +- * Sascha Hauer ++ * 01-Jul-2005 Ben Dooks ++ * * fixed spinlock call without pointer ++ * * ensure spinlock is initialised + */ + + #include +@@ -28,18 +63,27 @@ + #include + #include + #include +-#include + #include + #include + #include +-#include + + #include + #include + #include + ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ + #include "dm9000.h" + ++ + /* Board/System/Debug information/definition ---------------- */ + + #define DM9000_PHY 0x40 /* PHY address 0x01 */ +@@ -43,9 +87,46 @@ + /* Board/System/Debug information/definition ---------------- */ + + #define DM9000_PHY 0x40 /* PHY address 0x01 */ ++#define DM9000_CMD 0X04 + + #define CARDNAME "dm9000" +-#define DRV_VERSION "1.31" ++#define PFX CARDNAME ": " ++ ++#define DM9000_TIMER_WUT jiffies+(HZ*2) /* timer wakeup time : 2 second */ ++ ++#define DM9000_DEBUG 0 ++ ++#if DM9000_DEBUG > 2 ++#define PRINTK3(args...) printk(CARDNAME ": " args) ++#else ++#define PRINTK3(args...) do { } while(0) ++#endif ++ ++#if DM9000_DEBUG > 1 ++#define PRINTK2(args...) printk(CARDNAME ": " args) ++#else ++#define PRINTK2(args...) do { } while(0) ++#endif ++ ++#if DM9000_DEBUG > 0 ++#define PRINTK1(args...) printk(CARDNAME ": " args) ++#define PRINTK(args...) printk(CARDNAME ": " args) ++#else ++#define PRINTK1(args...) do { } while(0) ++#define PRINTK(args...) printk(KERN_DEBUG args) ++#endif ++ ++#ifdef CONFIG_BLACKFIN ++#define readsb insb ++#define readsw insw ++#define readsl insl ++#define writesb outsb ++#define writesw outsw ++#define writesl outsl ++#define DM9000_IRQ_FLAGS (IRQF_SHARED | IRQF_TRIGGER_HIGH) ++#else ++#define DM9000_IRQ_FLAGS IRQF_SHARED ++#endif + + /* + * Transmit timeout, default 5 seconds. +@@ -54,34 +135,6 @@ + module_param(watchdog, int, 0400); + MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); + +-/* DM9000 register address locking. +- * +- * The DM9000 uses an address register to control where data written +- * to the data register goes. This means that the address register +- * must be preserved over interrupts or similar calls. +- * +- * During interrupt and other critical calls, a spinlock is used to +- * protect the system, but the calls themselves save the address +- * in the address register in case they are interrupting another +- * access to the device. +- * +- * For general accesses a lock is provided so that calls which are +- * allowed to sleep are serialised so that the address register does +- * not need to be saved. This lock also serves to serialise access +- * to the EEPROM and PHY access registers which are shared between +- * these two devices. +- */ +- +-/* The driver supports the original DM9000E, and now the two newer +- * devices, DM9000A and DM9000B. +- */ +- +-enum dm9000_type { +- TYPE_DM9000E, /* original DM9000 */ +- TYPE_DM9000A, +- TYPE_DM9000B +-}; +- + /* Structure/enum declaration ------------------------------- */ + typedef struct board_info { + +@@ -95,58 +148,54 @@ + u16 dbug_cnt; + u8 io_mode; /* 0:word, 2:byte */ + u8 phy_addr; +- u8 imr_all; +- +- unsigned int flags; +- unsigned int in_suspend :1; +- int debug_level; +- +- enum dm9000_type type; + + void (*inblk)(void __iomem *port, void *data, int length); + void (*outblk)(void __iomem *port, void *data, int length); + void (*dumpblk)(void __iomem *port, int length); + +- struct device *dev; /* parent device */ +- + struct resource *addr_res; /* resources found */ + struct resource *data_res; + struct resource *addr_req; /* resources requested */ + struct resource *data_req; + struct resource *irq_res; + +- struct mutex addr_lock; /* phy and eeprom access lock */ +- +- struct delayed_work phy_poll; +- struct net_device *ndev; +- ++ struct timer_list timer; ++ unsigned char srom[128]; + spinlock_t lock; + + struct mii_if_info mii; + u32 msg_enable; + } board_info_t; + +-/* debug code */ +- +-#define dm9000_dbg(db, lev, msg...) do { \ +- if ((lev) < CONFIG_DM9000_DEBUGLEVEL && \ +- (lev) < db->debug_level) { \ +- dev_dbg(db->dev, msg); \ +- } \ +-} while (0) +- +-static inline board_info_t *to_dm9000_board(struct net_device *dev) +-{ +- return dev->priv; +-} +- ++/* function declaration ------------------------------------- */ ++static int dm9000_probe(struct platform_device *); ++static int dm9000_open(struct net_device *); ++static int dm9000_start_xmit(struct sk_buff *, struct net_device *); ++static int dm9000_stop(struct net_device *); ++ ++ ++static void dm9000_timer(unsigned long); ++static void dm9000_init_dm9000(struct net_device *); ++ ++static irqreturn_t dm9000_interrupt(int, void *); ++ ++static int dm9000_phy_read(struct net_device *dev, int phyaddr_unsused, int reg); ++static void dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg, ++ int value); ++static u16 read_srom_word(board_info_t *, int); ++static void dm9000_rx(struct net_device *); ++static void dm9000_hash_table(struct net_device *); ++ ++#undef DM9000_PROGRAM_EEPROM ++#ifdef DM9000_PROGRAM_EEPROM ++static void program_eeprom(board_info_t * db); ++#endif + /* DM9000 network board routine ---------------------------- */ + + static void + dm9000_reset(board_info_t * db) + { +- dev_dbg(db->dev, "resetting device\n"); +- ++ PRINTK1("****************************dm9000x: resetting,ioaddr=%x,iodata=%x\n",db->io_addr,db->io_data); + /* RESET device */ + writeb(DM9000_NCR, db->io_addr); + udelay(200); +@@ -255,6 +304,10 @@ + * routines we want to use + */ + ++ ++ PRINTK1("****************************dm9000x: dm9000_set_io***************************\n"); ++ ++ + switch (byte_width) { + case 1: + db->dumpblk = dm9000_dumpblk_8bit; +@@ -262,10 +315,14 @@ + db->inblk = dm9000_inblk_8bit; + break; + ++ case 2: ++ db->dumpblk = dm9000_dumpblk_16bit; ++ db->outblk = dm9000_outblk_16bit; ++ db->inblk = dm9000_inblk_16bit; ++ break; + + case 3: +- dev_dbg(db->dev, ": 3 byte IO, falling back to 16bit\n"); +- case 2: ++ printk(KERN_ERR PFX ": 3 byte IO, falling back to 16bit\n"); + db->dumpblk = dm9000_dumpblk_16bit; + db->outblk = dm9000_outblk_16bit; + db->inblk = dm9000_inblk_16bit; +@@ -280,395 +337,360 @@ + } + } + +-static void dm9000_schedule_poll(board_info_t *db) +-{ +- if (db->type == TYPE_DM9000E) +- schedule_delayed_work(&db->phy_poll, HZ * 2); +-} + +-static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd) ++/* Our watchdog timed out. Called by the networking layer */ ++static void dm9000_timeout(struct net_device *dev) + { +- board_info_t *dm = to_dm9000_board(dev); ++ board_info_t *db = (board_info_t *) dev->priv; ++ u8 reg_save; ++ unsigned long flags; + +- if (!netif_running(dev)) +- return -EINVAL; + +- return generic_mii_ioctl(&dm->mii, if_mii(req), cmd, NULL); +-} ++ PRINTK1("****************************dm9000x: dm9000_set_timeout ***************************\n"); + +-static unsigned int +-dm9000_read_locked(board_info_t *db, int reg) +-{ +- unsigned long flags; +- unsigned int ret; + +- spin_lock_irqsave(&db->lock, flags); +- ret = ior(db, reg); +- spin_unlock_irqrestore(&db->lock, flags); ++ /* Save previous register address */ ++ reg_save = readb(db->io_addr); ++ spin_lock_irqsave(&db->lock,flags); + +- return ret; ++ netif_stop_queue(dev); ++ dm9000_reset(db); ++ dm9000_init_dm9000(dev); ++ /* We can accept TX packets again */ ++ dev->trans_start = jiffies; ++ netif_wake_queue(dev); ++ ++ /* Restore previous register address */ ++ writeb(reg_save, db->io_addr); ++ spin_unlock_irqrestore(&db->lock,flags); + } + +-static int dm9000_wait_eeprom(board_info_t *db) ++#ifdef CONFIG_NET_POLL_CONTROLLER ++/* ++ *Used by netconsole ++ */ ++static void dm9000_poll_controller(struct net_device *dev) + { +- unsigned int status; +- int timeout = 8; /* wait max 8msec */ ++ disable_irq(dev->irq); ++ dm9000_interrupt(dev->irq,dev); ++ enable_irq(dev->irq); ++} ++#endif + +- /* The DM9000 data sheets say we should be able to +- * poll the ERRE bit in EPCR to wait for the EEPROM +- * operation. From testing several chips, this bit +- * does not seem to work. ++/* dm9000_release_board + * +- * We attempt to use the bit, but fall back to the +- * timeout (which is why we do not return an error +- * on expiry) to say that the EEPROM operation has +- * completed. ++ * release a board, and any mapped resources + */ + +- while (1) { +- status = dm9000_read_locked(db, DM9000_EPCR); +- +- if ((status & EPCR_ERRE) == 0) +- break; +- +- msleep(1); +- +- if (timeout-- < 0) { +- dev_dbg(db->dev, "timeout waiting EEPROM\n"); +- break; +- } +- } +- +- return 0; +-} +- +-/* +- * Read a word data from EEPROM +- */ + static void +-dm9000_read_eeprom(board_info_t *db, int offset, u8 *to) ++dm9000_release_board(struct platform_device *pdev, struct board_info *db) + { +- unsigned long flags; + +- if (db->flags & DM9000_PLATF_NO_EEPROM) { +- to[0] = 0xff; +- to[1] = 0xff; ++PRINTK1("****************************dm9000x: dm9000_release board ***************************\n"); ++ ++ if (db->data_res == NULL) { ++ if (db->addr_res != NULL) ++ release_mem_region((unsigned long)db->io_addr, 4); + return; + } + +- mutex_lock(&db->addr_lock); +- +- spin_lock_irqsave(&db->lock, flags); +- +- iow(db, DM9000_EPAR, offset); +- iow(db, DM9000_EPCR, EPCR_ERPRR); +- +- spin_unlock_irqrestore(&db->lock, flags); +- +- dm9000_wait_eeprom(db); +- +- /* delay for at-least 150uS */ +- msleep(1); +- +- spin_lock_irqsave(&db->lock, flags); ++ /* unmap our resources */ + +- iow(db, DM9000_EPCR, 0x0); ++ iounmap(db->io_addr); ++ iounmap(db->io_data); + +- to[0] = ior(db, DM9000_EPDRL); +- to[1] = ior(db, DM9000_EPDRH); ++ /* release the resources */ + +- spin_unlock_irqrestore(&db->lock, flags); ++ if (db->data_req != NULL) { ++ release_resource(db->data_req); ++ kfree(db->data_req); ++ } + +- mutex_unlock(&db->addr_lock); ++ if (db->addr_req != NULL) { ++ release_resource(db->addr_req); ++ kfree(db->addr_req); ++ } + } + ++#define res_size(_r) (((_r)->end - (_r)->start) + 1) ++ + /* +- * Write a word data to SROM ++ * Search DM9000 board, allocate space and register it + */ +-static void +-dm9000_write_eeprom(board_info_t *db, int offset, u8 *data) ++static int ++dm9000_probe(struct platform_device *pdev) + { +- unsigned long flags; +- +- if (db->flags & DM9000_PLATF_NO_EEPROM) +- return; +- +- mutex_lock(&db->addr_lock); +- +- spin_lock_irqsave(&db->lock, flags); +- iow(db, DM9000_EPAR, offset); +- iow(db, DM9000_EPDRH, data[1]); +- iow(db, DM9000_EPDRL, data[0]); +- iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW); +- spin_unlock_irqrestore(&db->lock, flags); ++ struct dm9000_plat_data *pdata = pdev->dev.platform_data; ++ struct board_info *db; /* Point a board information structure */ ++ struct net_device *ndev; ++ unsigned long base; ++ int ret = 0; ++ int iosize; ++ int i; ++ u32 id_val; + +- dm9000_wait_eeprom(db); + +- mdelay(1); /* wait at least 150uS to clear */ + +- spin_lock_irqsave(&db->lock, flags); +- iow(db, DM9000_EPCR, 0); +- spin_unlock_irqrestore(&db->lock, flags); + +- mutex_unlock(&db->addr_lock); +-} + +-/* ethtool ops */ ++#if 1 ++ unsigned int tmp; ++ printk("%s: dm9000_probe, init GPIO/EINT.\n", CARDNAME); + +-static void dm9000_get_drvinfo(struct net_device *dev, +- struct ethtool_drvinfo *info) +-{ +- board_info_t *dm = to_dm9000_board(dev); ++ tmp = __raw_readl(S3C64XX_SROM_BW); ++ tmp &=~(0xF<<4); ++ tmp |= (1<<7)|(1<<6)|(1<<4); ++ __raw_writel(tmp, S3C64XX_SROM_BW); + +- strcpy(info->driver, CARDNAME); +- strcpy(info->version, DRV_VERSION); +- strcpy(info->bus_info, to_platform_device(dm->dev)->name); +-} ++ __raw_writel(~(0xFFFFFFFF<<0), S3C64XX_SROM_BC1); ++ __raw_writel((0x0<<28)|(0x4<<24)|(0xd<<16)|(0x1<<12)|(0x4<<8)|(0x6<<4)|(0x0<<0), S3C64XX_SROM_BC1); + +-static u32 dm9000_get_msglevel(struct net_device *dev) +-{ +- board_info_t *dm = to_dm9000_board(dev); ++ writel((readl(S3C64XX_GPNCON) & ~(0x3 <<14)) | (0x2 << 14), S3C64XX_GPNCON); /* GPN7 to EINT */ ++ writel((readl(S3C64XX_GPNPUD) &~(0x3<<14)),S3C64XX_GPNPUD); + +- return dm->msg_enable; +-} ++ writel((readl(S3C64XX_EINT0CON0) & ~(0x7 <<12)) | (0x1 << 12), S3C64XX_EINT0CON0); /* EINT7 to high level triggered */ + +-static void dm9000_set_msglevel(struct net_device *dev, u32 value) +-{ +- board_info_t *dm = to_dm9000_board(dev); ++ writel((readl(S3C64XX_EINT0FLTCON0)& ~(0x3 <<6)) | (0x1 << 7), S3C64XX_EINT0FLTCON0); + +- dm->msg_enable = value; +-} ++ writel((readl(S3C64XX_EINT0PEND)&~(0x1<<7)),S3C64XX_EINT0PEND); ++ writel(readl(S3C64XX_EINT0MASK) & ~(0x1 << 7), S3C64XX_EINT0MASK); /* EINT7 unmask */ ++#else ++#endif ++ /* Init network device */ ++ ndev = alloc_etherdev(sizeof (struct board_info)); ++ if (!ndev) { ++ printk("%s: could not allocate device.\n", CARDNAME); ++ return -ENOMEM; ++ } + +-static int dm9000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) +-{ +- board_info_t *dm = to_dm9000_board(dev); ++ SET_NETDEV_DEV(ndev, &pdev->dev); + +- mii_ethtool_gset(&dm->mii, cmd); +- return 0; +-} ++ PRINTK2("dm9000_probe()"); + +-static int dm9000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) +-{ +- board_info_t *dm = to_dm9000_board(dev); ++ /* setup board info structure */ ++ db = (struct board_info *) ndev->priv; ++ memset(db, 0, sizeof (*db)); + +- return mii_ethtool_sset(&dm->mii, cmd); +-} ++ spin_lock_init(&db->lock); + +-static int dm9000_nway_reset(struct net_device *dev) +-{ +- board_info_t *dm = to_dm9000_board(dev); +- return mii_nway_restart(&dm->mii); +-} ++ if (pdev->num_resources < 2) { ++ ret = -ENODEV; ++ goto out; ++ } else if (pdev->num_resources == 2) { ++ base = pdev->resource[0].start; + +-static u32 dm9000_get_link(struct net_device *dev) +-{ +- board_info_t *dm = to_dm9000_board(dev); +- u32 ret; ++ if (!request_mem_region(base, 4, ndev->name)) { ++ ret = -EBUSY; ++ goto out; ++ } + +- if (dm->flags & DM9000_PLATF_EXT_PHY) +- ret = mii_link_ok(&dm->mii); +- else +- ret = dm9000_read_locked(dm, DM9000_NSR) & NSR_LINKST ? 1 : 0; ++ ndev->base_addr = base; ++ ndev->irq = pdev->resource[1].start; ++ db->io_addr = (void __iomem *)base; ++ db->io_data = (void __iomem *)(base + DM9000_CMD); ++ /* ensure at least we have a default set of IO routines */ ++ dm9000_set_io(db, 2); + +- return ret; +-} ++ } else { ++ db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + +-#define DM_EEPROM_MAGIC (0x444D394B) ++ if (db->addr_res == NULL || db->data_res == NULL || ++ db->irq_res == NULL) { ++ printk(KERN_ERR PFX "insufficient resources\n"); ++ ret = -ENOENT; ++ goto out; ++ } + +-static int dm9000_get_eeprom_len(struct net_device *dev) +-{ +- return 128; +-} ++ i = res_size(db->addr_res); ++ db->addr_req = request_mem_region(db->addr_res->start, i, ++ pdev->name); + +-static int dm9000_get_eeprom(struct net_device *dev, +- struct ethtool_eeprom *ee, u8 *data) +-{ +- board_info_t *dm = to_dm9000_board(dev); +- int offset = ee->offset; +- int len = ee->len; +- int i; ++ if (db->addr_req == NULL) { ++ printk(KERN_ERR PFX "cannot claim address reg area\n"); ++ ret = -EIO; ++ goto out; ++ } + +- /* EEPROM access is aligned to two bytes */ ++ db->io_addr = ioremap(db->addr_res->start, i); + +- if ((len & 1) != 0 || (offset & 1) != 0) +- return -EINVAL; ++ if (db->io_addr == NULL) { ++ printk(KERN_ERR "failed to ioremap address reg\n"); ++ ret = -EINVAL; ++ goto out; ++ } + +- if (dm->flags & DM9000_PLATF_NO_EEPROM) +- return -ENOENT; ++ iosize = res_size(db->data_res); ++ db->data_req = request_mem_region(db->data_res->start, iosize, ++ pdev->name); + +- ee->magic = DM_EEPROM_MAGIC; ++ if (db->data_req == NULL) { ++ printk(KERN_ERR PFX "cannot claim data reg area\n"); ++ ret = -EIO; ++ goto out; ++ } + +- for (i = 0; i < len; i += 2) +- dm9000_read_eeprom(dm, (offset + i) / 2, data + i); ++ db->io_data = ioremap(db->data_res->start, iosize); + +- return 0; +-} ++ if (db->io_data == NULL) { ++ printk(KERN_ERR "failed to ioremap data reg\n"); ++ ret = -EINVAL; ++ goto out; ++ } + +-static int dm9000_set_eeprom(struct net_device *dev, +- struct ethtool_eeprom *ee, u8 *data) +-{ +- board_info_t *dm = to_dm9000_board(dev); +- int offset = ee->offset; +- int len = ee->len; +- int i; ++ /* fill in parameters for net-dev structure */ + +- /* EEPROM access is aligned to two bytes */ ++ ndev->base_addr = (unsigned long)db->io_addr; ++ ndev->irq = db->irq_res->start; + +- if ((len & 1) != 0 || (offset & 1) != 0) +- return -EINVAL; ++ /* ensure at least we have a default set of IO routines */ ++ dm9000_set_io(db, iosize); ++ } + +- if (dm->flags & DM9000_PLATF_NO_EEPROM) +- return -ENOENT; ++ /* check to see if anything is being over-ridden */ ++ if (pdata != NULL) { ++ /* check to see if the driver wants to over-ride the ++ * default IO width */ + +- if (ee->magic != DM_EEPROM_MAGIC) +- return -EINVAL; ++ if (pdata->flags & DM9000_PLATF_8BITONLY) ++ dm9000_set_io(db, 1); + +- for (i = 0; i < len; i += 2) +- dm9000_write_eeprom(dm, (offset + i) / 2, data + i); ++ if (pdata->flags & DM9000_PLATF_16BITONLY) ++ dm9000_set_io(db, 2); + +- return 0; +-} ++ if (pdata->flags & DM9000_PLATF_32BITONLY) ++ dm9000_set_io(db, 4); + +-static const struct ethtool_ops dm9000_ethtool_ops = { +- .get_drvinfo = dm9000_get_drvinfo, +- .get_settings = dm9000_get_settings, +- .set_settings = dm9000_set_settings, +- .get_msglevel = dm9000_get_msglevel, +- .set_msglevel = dm9000_set_msglevel, +- .nway_reset = dm9000_nway_reset, +- .get_link = dm9000_get_link, +- .get_eeprom_len = dm9000_get_eeprom_len, +- .get_eeprom = dm9000_get_eeprom, +- .set_eeprom = dm9000_set_eeprom, +-}; ++ /* check to see if there are any IO routine ++ * over-rides */ + +-static void dm9000_show_carrier(board_info_t *db, +- unsigned carrier, unsigned nsr) +-{ +- struct net_device *ndev = db->ndev; +- unsigned ncr = dm9000_read_locked(db, DM9000_NCR); ++ if (pdata->inblk != NULL) ++ db->inblk = pdata->inblk; + +- if (carrier) +- dev_info(db->dev, "%s: link up, %dMbps, %s-duplex, no LPA\n", +- ndev->name, (nsr & NSR_SPEED) ? 10 : 100, +- (ncr & NCR_FDX) ? "full" : "half"); +- else +- dev_info(db->dev, "%s: link down\n", ndev->name); +-} ++ if (pdata->outblk != NULL) ++ db->outblk = pdata->outblk; + +-static void +-dm9000_poll_work(struct work_struct *w) +-{ +- struct delayed_work *dw = container_of(w, struct delayed_work, work); +- board_info_t *db = container_of(dw, board_info_t, phy_poll); +- struct net_device *ndev = db->ndev; ++ if (pdata->dumpblk != NULL) ++ db->dumpblk = pdata->dumpblk; ++ } + +- if (db->flags & DM9000_PLATF_SIMPLE_PHY && +- !(db->flags & DM9000_PLATF_EXT_PHY)) { +- unsigned nsr = dm9000_read_locked(db, DM9000_NSR); +- unsigned old_carrier = netif_carrier_ok(ndev) ? 1 : 0; +- unsigned new_carrier; ++ printk("%s: dm9000_probe2\n", CARDNAME); + +- new_carrier = (nsr & NSR_LINKST) ? 1 : 0; ++ dm9000_reset(db); + +- if (old_carrier != new_carrier) { +- if (netif_msg_link(db)) +- dm9000_show_carrier(db, new_carrier, nsr); ++ printk("%s: dm9000_probe3\n", CARDNAME); + +- if (!new_carrier) +- netif_carrier_off(ndev); +- else +- netif_carrier_on(ndev); ++ /* try two times, DM9000 sometimes gets the first read wrong */ ++ for (i = 0; i < 2; i++) { ++ id_val = ior(db, DM9000_VIDL); ++ id_val |= (u32)ior(db, DM9000_VIDH) << 8; ++ id_val |= (u32)ior(db, DM9000_PIDL) << 16; ++ id_val |= (u32)ior(db, DM9000_PIDH) << 24; ++ ++ if (id_val == DM9000_ID) ++ break; ++ printk("%s: read wrong id 0x%08x\n", CARDNAME, id_val); + } +- } else +- mii_check_media(&db->mii, netif_msg_link(db), 0); + +- if (netif_running(ndev)) +- dm9000_schedule_poll(db); +-} ++ if (id_val != DM9000_ID) { ++ printk("%s: wrong id: 0x%08x\n", CARDNAME, id_val); ++ ret = -ENODEV; ++ goto out; ++ } + +-/* dm9000_release_board +- * +- * release a board, and any mapped resources +- */ ++ /* from this point we assume that we have found a DM9000 */ + +-static void +-dm9000_release_board(struct platform_device *pdev, struct board_info *db) +-{ +- /* unmap our resources */ ++ /* driver system function */ ++ ether_setup(ndev); + +- iounmap(db->io_addr); +- iounmap(db->io_data); ++ ndev->open = &dm9000_open; ++ ndev->hard_start_xmit = &dm9000_start_xmit; ++ ndev->tx_timeout = &dm9000_timeout; ++ ndev->watchdog_timeo = msecs_to_jiffies(watchdog); ++ ndev->stop = &dm9000_stop; ++ ndev->set_multicast_list = &dm9000_hash_table; ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ ndev->poll_controller = &dm9000_poll_controller; ++#endif + +- /* release the resources */ ++#ifdef DM9000_PROGRAM_EEPROM ++ program_eeprom(db); ++#endif ++ db->msg_enable = NETIF_MSG_LINK; ++ db->mii.phy_id_mask = 0x1f; ++ db->mii.reg_num_mask = 0x1f; ++ db->mii.force_media = 0; ++ db->mii.full_duplex = 0; ++ db->mii.dev = ndev; ++ db->mii.mdio_read = dm9000_phy_read; ++ db->mii.mdio_write = dm9000_phy_write; + +- release_resource(db->data_req); +- kfree(db->data_req); ++ memcpy(ndev->dev_addr, "\x08\x90\x90\x90\x90\x90", 6); + +- release_resource(db->addr_req); +- kfree(db->addr_req); +-} ++/***************************************************/ ++ if (!is_valid_ether_addr(ndev->dev_addr)){ ++ printk("%s: Invalid ethernet MAC address. using default config, Please " ++ "set using ifconfig\n", ndev->name); ++ } ++/***************************************************/ + +-static unsigned char dm9000_type_to_char(enum dm9000_type type) +-{ +- switch (type) { +- case TYPE_DM9000E: return 'e'; +- case TYPE_DM9000A: return 'a'; +- case TYPE_DM9000B: return 'b'; ++ if (!is_valid_ether_addr(ndev->dev_addr)) ++ printk("%s: Invalid ethernet MAC address. Please " ++ "set using ifconfig\n", ndev->name); ++ ++ platform_set_drvdata(pdev, ndev); ++ ret = register_netdev(ndev); ++ ++ if (ret == 0) { ++ DECLARE_MAC_BUF(mac); ++ printk("%s: dm9000 at %p,%p IRQ %d MAC: %s\n", ++ ndev->name, db->io_addr, db->io_data, ndev->irq, ++ print_mac(mac, ndev->dev_addr)); + } ++ return 0; ++ ++out: ++ printk("%s: not found (%d).\n", CARDNAME, ret); ++ ++ dm9000_release_board(pdev, db); ++ free_netdev(ndev); + +- return '?'; ++ return ret; + } + + /* +- * Set DM9000 multicast address ++ * Open the interface. ++ * The interface is opened whenever "ifconfig" actives it. + */ +-static void +-dm9000_hash_table(struct net_device *dev) ++static int ++dm9000_open(struct net_device *dev) + { + board_info_t *db = (board_info_t *) dev->priv; +- struct dev_mc_list *mcptr = dev->mc_list; +- int mc_cnt = dev->mc_count; +- int i, oft; +- u32 hash_val; +- u16 hash_table[4]; +- u8 rcr = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN; +- unsigned long flags; + +- dm9000_dbg(db, 1, "entering %s\n", __func__); ++ PRINTK2("entering dm9000_open\n"); + +- spin_lock_irqsave(&db->lock, flags); +- +- for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) +- iow(db, oft, dev->dev_addr[i]); +- +- /* Clear Hash Table */ +- for (i = 0; i < 4; i++) +- hash_table[i] = 0x0; +- +- /* broadcast address */ +- hash_table[3] = 0x8000; ++ if (request_irq(dev->irq, &dm9000_interrupt, DM9000_IRQ_FLAGS, dev->name, dev)) ++ return -EAGAIN; + +- if (dev->flags & IFF_PROMISC) +- rcr |= RCR_PRMSC; ++ /* Initialize DM9000 board */ ++ dm9000_reset(db); ++ dm9000_init_dm9000(dev); + +- if (dev->flags & IFF_ALLMULTI) +- rcr |= RCR_ALL; ++ /* Init driver variable */ ++ db->dbug_cnt = 0; + +- /* the multicast address in Hash Table : 64 bits */ +- for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) { +- hash_val = ether_crc_le(6, mcptr->dmi_addr) & 0x3f; +- hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16); +- } ++ /* set and active a timer process */ ++ init_timer(&db->timer); ++ db->timer.expires = DM9000_TIMER_WUT; ++ db->timer.data = (unsigned long) dev; ++ db->timer.function = &dm9000_timer; ++ add_timer(&db->timer); + +- /* Write the hash table to MAC MD table */ +- for (i = 0, oft = DM9000_MAR; i < 4; i++) { +- iow(db, oft++, hash_table[i]); +- iow(db, oft++, hash_table[i] >> 8); +- } ++ mii_check_media(&db->mii, netif_msg_link(db), 1); ++ netif_start_queue(dev); + +- iow(db, DM9000_RCR, rcr); +- spin_unlock_irqrestore(&db->lock, flags); ++ return 0; + } + + /* +@@ -677,10 +699,9 @@ + static void + dm9000_init_dm9000(struct net_device *dev) + { +- board_info_t *db = dev->priv; +- unsigned int imr; ++ board_info_t *db = (board_info_t *) dev->priv; + +- dm9000_dbg(db, 1, "entering %s\n", __func__); ++ PRINTK1("entering %s\n",__FUNCTION__); + + /* I/O mode */ + db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */ +@@ -690,9 +711,6 @@ + iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */ + iow(db, DM9000_GPR, 0); /* Enable PHY */ + +- if (db->flags & DM9000_PLATF_EXT_PHY) +- iow(db, DM9000_NCR, NCR_EXT_PHY); +- + /* Program operating register */ + iow(db, DM9000_TCR, 0); /* TX Polling clear */ + iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ +@@ -705,14 +723,10 @@ + /* Set address filter table */ + dm9000_hash_table(dev); + +- imr = IMR_PAR | IMR_PTM | IMR_PRM; +- if (db->type != TYPE_DM9000E) +- imr |= IMR_LNKCHNG; +- +- db->imr_all = imr; +- ++ /* Activate DM9000 */ ++ iow(db, DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); + /* Enable TX/RX interrupt mask */ +- iow(db, DM9000_IMR, imr); ++ iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM); + + /* Init Driver variable */ + db->tx_pkt_cnt = 0; +@@ -720,29 +734,6 @@ + dev->trans_start = 0; + } + +-/* Our watchdog timed out. Called by the networking layer */ +-static void dm9000_timeout(struct net_device *dev) +-{ +- board_info_t *db = (board_info_t *) dev->priv; +- u8 reg_save; +- unsigned long flags; +- +- /* Save previous register address */ +- reg_save = readb(db->io_addr); +- spin_lock_irqsave(&db->lock, flags); +- +- netif_stop_queue(dev); +- dm9000_reset(db); +- dm9000_init_dm9000(dev); +- /* We can accept TX packets again */ +- dev->trans_start = jiffies; +- netif_wake_queue(dev); +- +- /* Restore previous register address */ +- writeb(reg_save, db->io_addr); +- spin_unlock_irqrestore(&db->lock, flags); +-} +- + /* + * Hardware start transmission. + * Send a packet to media from the upper layer. +@@ -751,9 +742,9 @@ + dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev) + { + unsigned long flags; +- board_info_t *db = dev->priv; ++ board_info_t *db = (board_info_t *) dev->priv; + +- dm9000_dbg(db, 3, "%s:\n", __func__); ++ PRINTK3("dm9000_start_xmit\n"); + + if (db->tx_pkt_cnt > 1) + return 1; +@@ -770,8 +761,8 @@ + /* TX control: First packet immediately send, second packet queue */ + if (db->tx_pkt_cnt == 1) { + /* Set TX length to DM9000 */ +- iow(db, DM9000_TXPLL, skb->len); +- iow(db, DM9000_TXPLH, skb->len >> 8); ++ iow(db, DM9000_TXPLL, skb->len & 0xff); ++ iow(db, DM9000_TXPLH, (skb->len >> 8) & 0xff); + + /* Issue TX polling command */ + iow(db, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ +@@ -791,12 +782,50 @@ + return 0; + } + ++static void ++dm9000_shutdown(struct net_device *dev) ++{ ++ board_info_t *db = (board_info_t *) dev->priv; ++ ++ /* RESET device */ ++ dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */ ++ iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */ ++ iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */ ++ iow(db, DM9000_RCR, 0x00); /* Disable RX */ ++} ++ ++/* ++ * Stop the interface. ++ * The interface is stopped when it is brought. ++ */ ++static int ++dm9000_stop(struct net_device *ndev) ++{ ++ board_info_t *db = (board_info_t *) ndev->priv; ++ ++ PRINTK1("entering %s\n",__FUNCTION__); ++ ++ /* deleted timer */ ++ del_timer(&db->timer); ++ ++ netif_stop_queue(ndev); ++ netif_carrier_off(ndev); ++ ++ /* free interrupt */ ++ free_irq(ndev->irq, ndev); ++ ++ dm9000_shutdown(ndev); ++ ++ return 0; ++} ++ + /* + * DM9000 interrupt handler + * receive the packet to upper layer, free the transmitted packet + */ + +-static void dm9000_tx_done(struct net_device *dev, board_info_t *db) ++static void ++dm9000_tx_done(struct net_device *dev, board_info_t * db) + { + int tx_status = ior(db, DM9000_NSR); /* Got TX status */ + +@@ -805,13 +834,10 @@ + db->tx_pkt_cnt--; + dev->stats.tx_packets++; + +- if (netif_msg_tx_done(db)) +- dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status); +- + /* Queue packet check & send */ + if (db->tx_pkt_cnt > 0) { +- iow(db, DM9000_TXPLL, db->queue_pkt_len); +- iow(db, DM9000_TXPLH, db->queue_pkt_len >> 8); ++ iow(db, DM9000_TXPLL, db->queue_pkt_len & 0xff); ++ iow(db, DM9000_TXPLH, (db->queue_pkt_len >> 8) & 0xff); + iow(db, DM9000_TCR, TCR_TXREQ); + dev->trans_start = jiffies; + } +@@ -819,10 +845,76 @@ + } + } + ++static irqreturn_t ++dm9000_interrupt(int irq, void *dev_id) ++{ ++ struct net_device *dev = dev_id; ++ board_info_t *db; ++ int int_status; ++ u8 reg_save; ++ ++ PRINTK3("entering %s\n",__FUNCTION__); ++ ++ if (!dev) { ++ PRINTK1("dm9000_interrupt() without DEVICE arg\n"); ++ return IRQ_HANDLED; ++ } ++ ++ /* A real interrupt coming */ ++ db = (board_info_t *) dev->priv; ++ spin_lock(&db->lock); ++ ++ /* Save previous register address */ ++ reg_save = readb(db->io_addr); ++ ++ /* Disable all interrupts */ ++ iow(db, DM9000_IMR, IMR_PAR); ++ ++ /* Got DM9000 interrupt status */ ++ int_status = ior(db, DM9000_ISR); /* Got ISR */ ++ iow(db, DM9000_ISR, int_status); /* Clear ISR status */ ++ ++ /* Received the coming packet */ ++ if (int_status & ISR_PRS) ++ dm9000_rx(dev); ++ ++ /* Trnasmit Interrupt check */ ++ if (int_status & ISR_PTS) ++ dm9000_tx_done(dev, db); ++ ++ /* Re-enable interrupt mask */ ++ iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM); ++ ++ /* Restore previous register address */ ++ writeb(reg_save, db->io_addr); ++ ++ spin_unlock(&db->lock); ++ ++ return IRQ_HANDLED; ++} ++ ++/* ++ * A periodic timer routine ++ * Dynamic media sense, allocated Rx buffer... ++ */ ++static void ++dm9000_timer(unsigned long data) ++{ ++ struct net_device *dev = (struct net_device *) data; ++ board_info_t *db = (board_info_t *) dev->priv; ++ ++ PRINTK3("dm9000_timer()\n"); ++ ++ mii_check_media(&db->mii, netif_msg_link(db), 0); ++ ++ /* Set timer again */ ++ db->timer.expires = DM9000_TIMER_WUT; ++ add_timer(&db->timer); ++} ++ + struct dm9000_rxhdr { +- u8 RxPktReady; +- u8 RxStatus; +- __le16 RxLen; ++ u16 RxStatus; ++ u16 RxLen; + } __attribute__((__packed__)); + + /* +@@ -847,7 +939,7 @@ + + /* Status check: this byte must be 0 or 1 */ + if (rxbyte > DM9000_PKT_RDY) { +- dev_warn(db->dev, "status check fail: %d\n", rxbyte); ++ printk("status check failed: %d\n", rxbyte); + iow(db, DM9000_RCR, 0x00); /* Stop Device */ + iow(db, DM9000_ISR, IMR_PAR); /* Stop INT request */ + return; +@@ -862,41 +954,30 @@ + + (db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr)); + +- RxLen = le16_to_cpu(rxhdr.RxLen); +- +- if (netif_msg_rx_status(db)) +- dev_dbg(db->dev, "RX: status %02x, length %04x\n", +- rxhdr.RxStatus, RxLen); ++ RxLen = rxhdr.RxLen; + + /* Packet Status check */ + if (RxLen < 0x40) { + GoodPacket = false; +- if (netif_msg_rx_err(db)) +- dev_dbg(db->dev, "RX: Bad Packet (runt)\n"); ++ PRINTK1("Bad Packet received (runt)\n"); + } + + if (RxLen > DM9000_PKT_MAX) { +- dev_dbg(db->dev, "RST: RX Len:%x\n", RxLen); ++ PRINTK1("RST: RX Len:%x\n", RxLen); + } + +- /* rxhdr.RxStatus is identical to RSR register. */ +- if (rxhdr.RxStatus & (RSR_FOE | RSR_CE | RSR_AE | +- RSR_PLE | RSR_RWTO | +- RSR_LCS | RSR_RF)) { ++ if (rxhdr.RxStatus & 0xbf00) { + GoodPacket = false; +- if (rxhdr.RxStatus & RSR_FOE) { +- if (netif_msg_rx_err(db)) +- dev_dbg(db->dev, "fifo error\n"); ++ if (rxhdr.RxStatus & 0x100) { ++ PRINTK1("fifo error\n"); + dev->stats.rx_fifo_errors++; + } +- if (rxhdr.RxStatus & RSR_CE) { +- if (netif_msg_rx_err(db)) +- dev_dbg(db->dev, "crc error\n"); ++ if (rxhdr.RxStatus & 0x200) { ++ PRINTK1("crc error\n"); + dev->stats.rx_crc_errors++; + } +- if (rxhdr.RxStatus & RSR_RF) { +- if (netif_msg_rx_err(db)) +- dev_dbg(db->dev, "length error\n"); ++ if (rxhdr.RxStatus & 0x8000) { ++ PRINTK1("length error\n"); + dev->stats.rx_length_errors++; + } + } +@@ -925,120 +1006,116 @@ + } while (rxbyte == DM9000_PKT_RDY); + } + +-static irqreturn_t dm9000_interrupt(int irq, void *dev_id) ++/* ++ * Read a word data from SROM ++ */ ++static u16 ++read_srom_word(board_info_t * db, int offset) + { +- struct net_device *dev = dev_id; +- board_info_t *db = dev->priv; +- int int_status; +- u8 reg_save; ++ iow(db, DM9000_EPAR, offset); ++ iow(db, DM9000_EPCR, EPCR_ERPRR); ++ mdelay(8); /* according to the datasheet 200us should be enough, ++ but it doesn't work */ ++ iow(db, DM9000_EPCR, 0x0); ++ return (ior(db, DM9000_EPDRL) + (ior(db, DM9000_EPDRH) << 8)); ++} + +- dm9000_dbg(db, 3, "entering %s\n", __func__); ++#ifdef DM9000_PROGRAM_EEPROM ++/* ++ * Write a word data to SROM ++ */ ++static void ++write_srom_word(board_info_t * db, int offset, u16 val) ++{ ++ iow(db, DM9000_EPAR, offset); ++ iow(db, DM9000_EPDRH, ((val >> 8) & 0xff)); ++ iow(db, DM9000_EPDRL, (val & 0xff)); ++ iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW); ++ mdelay(8); /* same shit */ ++ iow(db, DM9000_EPCR, 0); ++} + +- /* A real interrupt coming */ ++/* ++ * Only for development: ++ * Here we write static data to the eeprom in case ++ * we don't have valid content on a new board ++ */ ++static void ++program_eeprom(board_info_t * db) ++{ ++ u16 eeprom[] = { 0x0c00, 0x007f, 0x1300, /* MAC Address */ ++ 0x0000, /* Autoload: accept nothing */ ++ 0x0a46, 0x9000, /* Vendor / Product ID */ ++ 0x0000, /* pin control */ ++ 0x0000, ++ }; /* Wake-up mode control */ ++ int i; ++ for (i = 0; i < 8; i++) ++ write_srom_word(db, i, eeprom[i]); ++} ++#endif + +- spin_lock(&db->lock); + +- /* Save previous register address */ +- reg_save = readb(db->io_addr); ++/* ++ * Calculate the CRC valude of the Rx packet ++ * flag = 1 : return the reverse CRC (for the received packet CRC) ++ * 0 : return the normal CRC (for Hash Table index) ++ */ + +- /* Disable all interrupts */ +- iow(db, DM9000_IMR, IMR_PAR); +- +- /* Got DM9000 interrupt status */ +- int_status = ior(db, DM9000_ISR); /* Got ISR */ +- iow(db, DM9000_ISR, int_status); /* Clear ISR status */ +- +- if (netif_msg_intr(db)) +- dev_dbg(db->dev, "interrupt status %02x\n", int_status); +- +- /* Received the coming packet */ +- if (int_status & ISR_PRS) +- dm9000_rx(dev); +- +- /* Trnasmit Interrupt check */ +- if (int_status & ISR_PTS) +- dm9000_tx_done(dev, db); +- +- if (db->type != TYPE_DM9000E) { +- if (int_status & ISR_LNKCHNG) { +- /* fire a link-change request */ +- schedule_delayed_work(&db->phy_poll, 1); +- } +- } +- +- /* Re-enable interrupt mask */ +- iow(db, DM9000_IMR, db->imr_all); +- +- /* Restore previous register address */ +- writeb(reg_save, db->io_addr); ++static unsigned long ++cal_CRC(unsigned char *Data, unsigned int Len, u8 flag) ++{ + +- spin_unlock(&db->lock); ++ u32 crc = ether_crc_le(Len, Data); + +- return IRQ_HANDLED; +-} ++ if (flag) ++ return ~crc; + +-#ifdef CONFIG_NET_POLL_CONTROLLER +-/* +- *Used by netconsole +- */ +-static void dm9000_poll_controller(struct net_device *dev) +-{ +- disable_irq(dev->irq); +- dm9000_interrupt(dev->irq, dev); +- enable_irq(dev->irq); ++ return crc; + } +-#endif + + /* +- * Open the interface. +- * The interface is opened whenever "ifconfig" actives it. ++ * Set DM9000 multicast address + */ +-static int +-dm9000_open(struct net_device *dev) ++static void ++dm9000_hash_table(struct net_device *dev) + { +- board_info_t *db = dev->priv; +- unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK; +- +- if (netif_msg_ifup(db)) +- dev_dbg(db->dev, "enabling %s\n", dev->name); +- +- /* If there is no IRQ type specified, default to something that +- * may work, and tell the user that this is a problem */ ++ board_info_t *db = (board_info_t *) dev->priv; ++ struct dev_mc_list *mcptr = dev->mc_list; ++ int mc_cnt = dev->mc_count; ++ u32 hash_val; ++ u16 i, oft, hash_table[4]; ++ unsigned long flags; + +- if (irqflags == IRQF_TRIGGER_NONE) +- dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n"); ++ PRINTK2("dm9000_hash_table()\n"); + +- irqflags |= IRQF_SHARED; ++ spin_lock_irqsave(&db->lock,flags); + +- if (request_irq(dev->irq, &dm9000_interrupt, irqflags, dev->name, dev)) +- return -EAGAIN; ++ for (i = 0, oft = 0x10; i < 6; i++, oft++) ++ iow(db, oft, dev->dev_addr[i]); + +- /* Initialize DM9000 board */ +- dm9000_reset(db); +- dm9000_init_dm9000(dev); ++ /* Clear Hash Table */ ++ for (i = 0; i < 4; i++) ++ hash_table[i] = 0x0; + +- /* Init driver variable */ +- db->dbug_cnt = 0; ++ /* broadcast address */ ++ hash_table[3] = 0x8000; + +- mii_check_media(&db->mii, netif_msg_link(db), 1); +- netif_start_queue(dev); ++ /* the multicast address in Hash Table : 64 bits */ ++ for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) { ++ hash_val = cal_CRC((char *) mcptr->dmi_addr, 6, 0) & 0x3f; ++ hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16); ++ } + +- dm9000_schedule_poll(db); ++ /* Write the hash table to MAC MD table */ ++ for (i = 0, oft = 0x16; i < 4; i++) { ++ iow(db, oft++, hash_table[i] & 0xff); ++ iow(db, oft++, (hash_table[i] >> 8) & 0xff); ++ } + +- return 0; ++ spin_unlock_irqrestore(&db->lock,flags); + } + +-/* +- * Sleep, either by using msleep() or if we are suspending, then +- * use mdelay() to sleep. +- */ +-static void dm9000_msleep(board_info_t *db, unsigned int ms) +-{ +- if (db->in_suspend) +- mdelay(ms); +- else +- msleep(ms); +-} + + /* + * Read a word from phyxcer +@@ -1051,8 +1128,6 @@ + unsigned int reg_save; + int ret; + +- mutex_lock(&db->addr_lock); +- + spin_lock_irqsave(&db->lock,flags); + + /* Save previous register address */ +@@ -1061,16 +1136,8 @@ + /* Fill the phyxcer register into REG_0C */ + iow(db, DM9000_EPAR, DM9000_PHY | reg); + +- iow(db, DM9000_EPCR, EPCR_ERPRR | EPCR_EPOS); /* Issue phyxcer read command */ +- +- writeb(reg_save, db->io_addr); +- spin_unlock_irqrestore(&db->lock,flags); +- +- dm9000_msleep(db, 1); /* Wait read complete */ +- +- spin_lock_irqsave(&db->lock,flags); +- reg_save = readb(db->io_addr); +- ++ iow(db, DM9000_EPCR, 0xc); /* Issue phyxcer read command */ ++ udelay(100); /* Wait read complete */ + iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */ + + /* The read data keeps on REG_0D & REG_0E */ +@@ -1078,11 +1145,9 @@ + + /* restore the previous address */ + writeb(reg_save, db->io_addr); +- spin_unlock_irqrestore(&db->lock,flags); + +- mutex_unlock(&db->addr_lock); ++ spin_unlock_irqrestore(&db->lock,flags); + +- dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret); + return ret; + } + +@@ -1090,16 +1155,12 @@ + * Write a word to phyxcer + */ + static void +-dm9000_phy_write(struct net_device *dev, +- int phyaddr_unused, int reg, int value) ++dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg, int value) + { + board_info_t *db = (board_info_t *) dev->priv; + unsigned long flags; + unsigned long reg_save; + +- dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value); +- mutex_lock(&db->addr_lock); +- + spin_lock_irqsave(&db->lock,flags); + + /* Save previous register address */ +@@ -1109,310 +1170,25 @@ + iow(db, DM9000_EPAR, DM9000_PHY | reg); + + /* Fill the written data into REG_0D & REG_0E */ +- iow(db, DM9000_EPDRL, value); +- iow(db, DM9000_EPDRH, value >> 8); +- +- iow(db, DM9000_EPCR, EPCR_EPOS | EPCR_ERPRW); /* Issue phyxcer write command */ +- +- writeb(reg_save, db->io_addr); +- spin_unlock_irqrestore(&db->lock, flags); +- +- dm9000_msleep(db, 1); /* Wait write complete */ +- +- spin_lock_irqsave(&db->lock,flags); +- reg_save = readb(db->io_addr); ++ iow(db, DM9000_EPDRL, (value & 0xff)); ++ iow(db, DM9000_EPDRH, ((value >> 8) & 0xff)); + ++ iow(db, DM9000_EPCR, 0xa); /* Issue phyxcer write command */ ++ udelay(500); /* Wait write complete */ + iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */ + + /* restore the previous address */ + writeb(reg_save, db->io_addr); + +- spin_unlock_irqrestore(&db->lock, flags); +- mutex_unlock(&db->addr_lock); +-} +- +-static void +-dm9000_shutdown(struct net_device *dev) +-{ +- board_info_t *db = dev->priv; +- +- /* RESET device */ +- dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */ +- iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */ +- iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */ +- iow(db, DM9000_RCR, 0x00); /* Disable RX */ +-} +- +-/* +- * Stop the interface. +- * The interface is stopped when it is brought. +- */ +-static int +-dm9000_stop(struct net_device *ndev) +-{ +- board_info_t *db = ndev->priv; +- +- if (netif_msg_ifdown(db)) +- dev_dbg(db->dev, "shutting down %s\n", ndev->name); +- +- cancel_delayed_work_sync(&db->phy_poll); +- +- netif_stop_queue(ndev); +- netif_carrier_off(ndev); +- +- /* free interrupt */ +- free_irq(ndev->irq, ndev); +- +- dm9000_shutdown(ndev); +- +- return 0; +-} +- +-#define res_size(_r) (((_r)->end - (_r)->start) + 1) +- +-/* +- * Search DM9000 board, allocate space and register it +- */ +-static int __devinit +-dm9000_probe(struct platform_device *pdev) +-{ +- struct dm9000_plat_data *pdata = pdev->dev.platform_data; +- struct board_info *db; /* Point a board information structure */ +- struct net_device *ndev; +- const unsigned char *mac_src; +- int ret = 0; +- int iosize; +- int i; +- u32 id_val; +- +- /* Init network device */ +- ndev = alloc_etherdev(sizeof(struct board_info)); +- if (!ndev) { +- dev_err(&pdev->dev, "could not allocate device.\n"); +- return -ENOMEM; +- } +- +- SET_NETDEV_DEV(ndev, &pdev->dev); +- +- dev_dbg(&pdev->dev, "dm9000_probe()\n"); +- +- /* setup board info structure */ +- db = ndev->priv; +- memset(db, 0, sizeof(*db)); +- +- db->dev = &pdev->dev; +- db->ndev = ndev; +- +- spin_lock_init(&db->lock); +- mutex_init(&db->addr_lock); +- +- INIT_DELAYED_WORK(&db->phy_poll, dm9000_poll_work); +- +- db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); +- db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); +- +- if (db->addr_res == NULL || db->data_res == NULL || +- db->irq_res == NULL) { +- dev_err(db->dev, "insufficient resources\n"); +- ret = -ENOENT; +- goto out; +- } +- +- iosize = res_size(db->addr_res); +- db->addr_req = request_mem_region(db->addr_res->start, iosize, +- pdev->name); +- +- if (db->addr_req == NULL) { +- dev_err(db->dev, "cannot claim address reg area\n"); +- ret = -EIO; +- goto out; +- } +- +- db->io_addr = ioremap(db->addr_res->start, iosize); +- +- if (db->io_addr == NULL) { +- dev_err(db->dev, "failed to ioremap address reg\n"); +- ret = -EINVAL; +- goto out; +- } +- +- iosize = res_size(db->data_res); +- db->data_req = request_mem_region(db->data_res->start, iosize, +- pdev->name); +- +- if (db->data_req == NULL) { +- dev_err(db->dev, "cannot claim data reg area\n"); +- ret = -EIO; +- goto out; +- } +- +- db->io_data = ioremap(db->data_res->start, iosize); +- +- if (db->io_data == NULL) { +- dev_err(db->dev, "failed to ioremap data reg\n"); +- ret = -EINVAL; +- goto out; +- } +- +- /* fill in parameters for net-dev structure */ +- ndev->base_addr = (unsigned long)db->io_addr; +- ndev->irq = db->irq_res->start; +- +- /* ensure at least we have a default set of IO routines */ +- dm9000_set_io(db, iosize); +- +- /* check to see if anything is being over-ridden */ +- if (pdata != NULL) { +- /* check to see if the driver wants to over-ride the +- * default IO width */ +- +- if (pdata->flags & DM9000_PLATF_8BITONLY) +- dm9000_set_io(db, 1); +- +- if (pdata->flags & DM9000_PLATF_16BITONLY) +- dm9000_set_io(db, 2); +- +- if (pdata->flags & DM9000_PLATF_32BITONLY) +- dm9000_set_io(db, 4); +- +- /* check to see if there are any IO routine +- * over-rides */ +- +- if (pdata->inblk != NULL) +- db->inblk = pdata->inblk; +- +- if (pdata->outblk != NULL) +- db->outblk = pdata->outblk; +- +- if (pdata->dumpblk != NULL) +- db->dumpblk = pdata->dumpblk; +- +- db->flags = pdata->flags; +- } +- +-#ifdef CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL +- db->flags |= DM9000_PLATF_SIMPLE_PHY; +-#endif +- +- dm9000_reset(db); +- +- /* try multiple times, DM9000 sometimes gets the read wrong */ +- for (i = 0; i < 8; i++) { +- id_val = ior(db, DM9000_VIDL); +- id_val |= (u32)ior(db, DM9000_VIDH) << 8; +- id_val |= (u32)ior(db, DM9000_PIDL) << 16; +- id_val |= (u32)ior(db, DM9000_PIDH) << 24; +- +- if (id_val == DM9000_ID) +- break; +- dev_err(db->dev, "read wrong id 0x%08x\n", id_val); +- } +- +- if (id_val != DM9000_ID) { +- dev_err(db->dev, "wrong id: 0x%08x\n", id_val); +- ret = -ENODEV; +- goto out; +- } +- +- /* Identify what type of DM9000 we are working on */ +- +- id_val = ior(db, DM9000_CHIPR); +- dev_dbg(db->dev, "dm9000 revision 0x%02x\n", id_val); +- +- switch (id_val) { +- case CHIPR_DM9000A: +- db->type = TYPE_DM9000A; +- break; +- case CHIPR_DM9000B: +- db->type = TYPE_DM9000B; +- break; +- default: +- dev_dbg(db->dev, "ID %02x => defaulting to DM9000E\n", id_val); +- db->type = TYPE_DM9000E; +- } +- +- /* from this point we assume that we have found a DM9000 */ +- +- /* driver system function */ +- ether_setup(ndev); +- +- ndev->open = &dm9000_open; +- ndev->hard_start_xmit = &dm9000_start_xmit; +- ndev->tx_timeout = &dm9000_timeout; +- ndev->watchdog_timeo = msecs_to_jiffies(watchdog); +- ndev->stop = &dm9000_stop; +- ndev->set_multicast_list = &dm9000_hash_table; +- ndev->ethtool_ops = &dm9000_ethtool_ops; +- ndev->do_ioctl = &dm9000_ioctl; +- +-#ifdef CONFIG_NET_POLL_CONTROLLER +- ndev->poll_controller = &dm9000_poll_controller; +-#endif +- +- db->msg_enable = NETIF_MSG_LINK; +- db->mii.phy_id_mask = 0x1f; +- db->mii.reg_num_mask = 0x1f; +- db->mii.force_media = 0; +- db->mii.full_duplex = 0; +- db->mii.dev = ndev; +- db->mii.mdio_read = dm9000_phy_read; +- db->mii.mdio_write = dm9000_phy_write; +- +- mac_src = "eeprom"; +- +- /* try reading the node address from the attached EEPROM */ +- for (i = 0; i < 6; i += 2) +- dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i); +- +- if (!is_valid_ether_addr(ndev->dev_addr) && pdata != NULL) { +- mac_src = "platform data"; +- memcpy(ndev->dev_addr, pdata->dev_addr, 6); +- } +- +- if (!is_valid_ether_addr(ndev->dev_addr)) { +- /* try reading from mac */ +- +- mac_src = "chip"; +- for (i = 0; i < 6; i++) +- ndev->dev_addr[i] = ior(db, i+DM9000_PAR); +- } +- +- if (!is_valid_ether_addr(ndev->dev_addr)) +- dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please " +- "set using ifconfig\n", ndev->name); +- +- platform_set_drvdata(pdev, ndev); +- ret = register_netdev(ndev); +- +- if (ret == 0) { +- DECLARE_MAC_BUF(mac); +- printk(KERN_INFO "%s: dm9000%c at %p,%p IRQ %d MAC: %s (%s)\n", +- ndev->name, dm9000_type_to_char(db->type), +- db->io_addr, db->io_data, ndev->irq, +- print_mac(mac, ndev->dev_addr), mac_src); +- } +- return 0; +- +-out: +- dev_err(db->dev, "not found (%d).\n", ret); +- +- dm9000_release_board(pdev, db); +- free_netdev(ndev); +- +- return ret; ++ spin_unlock_irqrestore(&db->lock,flags); + } + + static int + dm9000_drv_suspend(struct platform_device *dev, pm_message_t state) + { + struct net_device *ndev = platform_get_drvdata(dev); +- board_info_t *db; + + if (ndev) { +- db = (board_info_t *) ndev->priv; +- db->in_suspend = 1; +- + if (netif_running(ndev)) { + netif_device_detach(ndev); + dm9000_shutdown(ndev); +@@ -1435,13 +1211,11 @@ + + netif_device_attach(ndev); + } +- +- db->in_suspend = 0; + } + return 0; + } + +-static int __devexit ++static int + dm9000_drv_remove(struct platform_device *pdev) + { + struct net_device *ndev = platform_get_drvdata(pdev); +@@ -1452,7 +1226,8 @@ + dm9000_release_board(pdev, (board_info_t *) ndev->priv); + free_netdev(ndev); /* free device structure */ + +- dev_dbg(&pdev->dev, "released and freed device\n"); ++ PRINTK1("clean_module() exit\n"); ++ + return 0; + } + +@@ -1462,7 +1237,7 @@ + .owner = THIS_MODULE, + }, + .probe = dm9000_probe, +- .remove = __devexit_p(dm9000_drv_remove), ++ .remove = dm9000_drv_remove, + .suspend = dm9000_drv_suspend, + .resume = dm9000_drv_resume, + }; +@@ -1470,9 +1245,9 @@ + static int __init + dm9000_init(void) + { +- printk(KERN_INFO "%s Ethernet Driver, V%s\n", CARDNAME, DRV_VERSION); ++ printk(KERN_INFO "%s Ethernet Driver\n", CARDNAME); + +- return platform_driver_register(&dm9000_driver); ++ return platform_driver_register(&dm9000_driver); /* search board and register */ + } + + static void __exit +@@ -1487,4 +1262,3 @@ + MODULE_AUTHOR("Sascha Hauer, Ben Dooks"); + MODULE_DESCRIPTION("Davicom DM9000 network driver"); + MODULE_LICENSE("GPL"); +-MODULE_ALIAS("platform:dm9000"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/net/irda/Kconfig linux-2.6.28.6/drivers/net/irda/Kconfig +--- linux-2.6.28/drivers/net/irda/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/net/irda/Kconfig 2009-04-30 09:36:38.000000000 +0200 +@@ -3,6 +3,12 @@ + + comment "SIR device drivers" + ++config S3C_SIR ++ tristate "S3C Irda SIR device" ++ depends on IRDA ++ help ++ Say Y here if you want to have S3C IRDA support. ++ + config IRTTY_SIR + tristate "IrTTY (uses Linux serial driver)" + depends on IRDA +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/net/irda/Makefile linux-2.6.28.6/drivers/net/irda/Makefile +--- linux-2.6.28/drivers/net/irda/Makefile 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/net/irda/Makefile 2009-04-30 09:36:38.000000000 +0200 +@@ -20,6 +20,7 @@ + obj-$(CONFIG_MCS_FIR) += mcs7780.o + obj-$(CONFIG_AU1000_FIR) += au1k_ir.o + # SIR drivers ++obj-$(CONFIG_S3C_SIR) += s3c-sir.o + obj-$(CONFIG_IRTTY_SIR) += irtty-sir.o sir-dev.o + # dongle drivers for SIR drivers + obj-$(CONFIG_ESI_DONGLE) += esi-sir.o +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/net/irda/s3c-sir.c linux-2.6.28.6/drivers/net/irda/s3c-sir.c +--- linux-2.6.28/drivers/net/irda/s3c-sir.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/net/irda/s3c-sir.c 2009-04-30 09:36:38.000000000 +0200 +@@ -0,0 +1,914 @@ ++/* ++ * drivers/net/irda/s3c-sir.c ++ * Samsung Infra-red driver for the S3C embedded microprocessor ++ * ++ * Copyright (C) 2009 for Samsung Electronics ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#if defined(CONFIG_PLAT_S5PC1XX) ++#include ++#elif defined(CONFIG_PLAT_S3C64XX) ++#include ++#endif ++ ++#include ++#include ++#include ++ ++/* #define S3C_IRDA_DEBUG */ ++ ++#ifdef S3C_IRDA_DEBUG ++#define DBG(x...) printk(PFX x) ++#else ++#define DBG(x...) do { } while (0) ++#endif ++ ++#define DRIVER_NAME "s3c-irda" ++#define PFX DRIVER_NAME ": " ++ ++static int max_rate = 115200; ++ ++struct s3c_irda { ++ unsigned char hscr0; ++ unsigned char utcr4; ++ unsigned char power; ++ unsigned char open; ++ ++ int speed; ++ int newspeed; ++ ++ struct sk_buff *txskb; ++ struct sk_buff *rxskb; ++ ++ struct net_device_stats stats; ++ struct device *dev; ++ struct irda_platform_data *pdata; ++ struct irlap_cb *irlap; ++ struct qos_info qos; ++ ++ iobuff_t tx_buff; ++ iobuff_t rx_buff; ++ unsigned int sir_irq_rx; ++ unsigned int sir_irq_tx; ++ ++ struct resource *sir_mem; ++ struct clk *sir_clk; ++ void __iomem *sir_base; ++ int dma; ++}; ++ ++ ++#define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1) ++#define S3C_SIR_MAX_RXLEN 2047 ++ ++static const unsigned int nSlotTable[16] = {0x0000,0x0080,0x0808,0x8888,0x2222,0x4924,0x4a52,0x54aa, ++ 0x5555,0xd555,0xd5d5,0xddd5,0xdddd,0xdfdd,0xdfdf,0xffdf}; ++ ++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S5PC100) ++/* UART3 port has been reserved for Irda */ ++#define sir_writereg(val,reg) writel(val, (S3C24XX_VA_UART3 + reg)) ++#define sir_readreg(reg) readl(S3C24XX_VA_UART3 + reg) ++#else ++/* UART2 port has been reserved for Irda */ ++#define sir_writereg(val,reg) writel(val, (S3C24XX_VA_UART2 + reg)) ++#define sir_readreg(reg) readl(S3C24XX_VA_UART2 + reg) ++#endif ++ ++ ++extern int clk_enable(struct clk *clk); ++extern unsigned long clk_get_rate(struct clk *clk); ++extern struct clk *clk_get(struct device *dev, const char *id); ++extern void clk_put(struct clk *clk); ++extern void clk_disable(struct clk *clk); ++ ++ ++static void s3c_irda_gpio_conf(void) ++{ ++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) ++ s3c_gpio_cfgpin(S3C64XX_GPB(2), S3C64XX_GPB2_UART_RXD3); ++ s3c_gpio_cfgpin(S3C64XX_GPB(3), S3C64XX_GPB3_UART_TXD3); ++#elif defined(CONFIG_CPU_S5PC100) ++ s3c_gpio_cfgpin(S5PC1XX_GPA1(2), S5PC1XX_GPA1_2_UART_3_RXD); ++ s3c_gpio_cfgpin(S5PC1XX_GPA1(3), S5PC1XX_GPA1_3_UART_3_TXD); ++#endif ++} ++ ++ ++static int s3c_irda_sir_init(struct s3c_irda *si) ++{ ++ u32 ucon, ulcon, ufcon; ++ ++ DBG("%s\r\n", __FUNCTION__); ++ ++ /* Enable uart clock */ ++ clk_enable(si->sir_clk); ++ ++ /* Setup the GPIOs */ ++ s3c_irda_gpio_conf(); ++ ++ ulcon = S3C_LCON_IRM | S3C_LCON_PNONE | S3C_LCON_CS8; ++ ucon = S3C_UCON_PCLK | S3C_UCON_TXILEVEL | S3C_UCON_RXILEVEL | \ ++ S3C_UCON_RXFIFO_TOI| S3C_UCON_RX_ESIE | \ ++ S3C_UCON_LOOP_OPERATION | S3C_UCON_NO_SBS | \ ++ S3C_UCON_RXIRQMODE; ++ ufcon = S3C_UFCON_TXTRIG16 | S3C_UFCON_RXTRIG32 | \ ++ S3C_UFCON_RESETBOTH | S3C_UFCON_FIFO_ENABLE; ++ ++ sir_writereg(ulcon, S3C_ULCON); ++ sir_writereg(ufcon, S3C_UFCON); ++ sir_writereg(ucon, S3C_UCON); ++ ++ return 0; ++} ++ ++ ++static int s3c_irda_sir_stop(struct s3c_irda *si) ++{ ++ DBG("%s\r\n", __FUNCTION__); ++ ++ disable_irq(si->sir_irq_rx); ++ disable_irq(si->sir_irq_tx); ++ ++ sir_writereg(0, S3C_ULCON); ++ sir_writereg(0, S3C_UFCON); ++ sir_writereg(0, S3C_UCON); ++ ++ /* Disable the uart clock */ ++ clk_disable(si->sir_clk); ++ ++ return 0; ++} ++ ++ ++static int s3c_irda_sir_setspeed(struct s3c_irda *si, u32 speed) ++{ ++ u32 ubrdiv, pclk; ++ int slot = -1; ++ ++ DBG("%s\r\n", __FUNCTION__); ++ ++ pclk = clk_get_rate(si->sir_clk); ++ ubrdiv = (int) (pclk/16/speed) - 1; ++ ++ DBG("sir : pclk %d speed %d ubrdiv %d \r\n", pclk, speed, ubrdiv); ++ ++ sir_writereg(ubrdiv, S3C_UBRDIV); ++ ++ if(slot >= 0) { ++ sir_writereg(nSlotTable[slot], S3C_UDIVSLOT); ++ } ++ return 0; ++} ++ ++ ++/* ++ * Set the IrDA communications speed. ++ */ ++static int s3c_irda_set_speed(struct s3c_irda *si, int speed) ++{ ++ unsigned long flags; ++ int ret = -EINVAL; ++ ++ DBG("%s\r\n", __FUNCTION__); ++ ++ switch (speed) { ++ case 9600: case 19200: case 38400: ++ case 57600: case 115200: ++ ++ local_irq_save(flags); ++ s3c_irda_sir_setspeed(si, speed); ++ si->speed = speed; ++ local_irq_restore(flags); ++ ret = 0; ++ break; ++ ++ default: ++ printk(KERN_ERR "Invalid speed requested\n"); ++ break; ++ } ++ ++ return ret; ++ ++} ++ ++ ++/* ++ * Control the power state of the IrDA transmitter. ++ * State: ++ * 0 - off ++ * 1 - short range, lowest power ++ * 2 - medium range, medium power ++ * 3 - maximum range, high power ++ * ++ * Currently, only assabet is known to support this. ++ */ ++static int ++__s3c_irda_set_power(struct s3c_irda *si, unsigned int state) ++{ ++ int ret = 0; ++ DBG("%s\r\n", __FUNCTION__); ++ ++ if(si->pdata->set_power) ++ ret = si->pdata->set_power(si->dev, state); ++ return ret; ++} ++ ++ ++static inline int s3c_set_power(struct s3c_irda *si, unsigned int state) ++{ ++ int ret; ++ DBG("%s\r\n", __FUNCTION__); ++ ++ ret = __s3c_irda_set_power(si, state); ++ if(ret == 0) ++ si->power = state; ++ ++ return ret; ++} ++ ++static int s3c_irda_startup(struct s3c_irda *si) ++{ ++ int ret; ++ ++ DBG("%s\r\n", __FUNCTION__); ++ ++ /* Ensure that the ports for this device are setup correctly */ ++#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) ++ s3c_gpio_setpull(S3C64XX_GPB(2), S3C_GPIO_PULL_UP); ++ s3c_gpio_setpull(S3C64XX_GPB(3), S3C_GPIO_PULL_UP); ++#elif defined(CONFIG_CPU_S5PC100) ++ s3c_gpio_setpull(S5PC1XX_GPA1(2), S3C_GPIO_PULL_UP); ++ s3c_gpio_setpull(S5PC1XX_GPA1(3), S3C_GPIO_PULL_UP); ++#endif ++ ++ ret = s3c_irda_sir_init(si); ++ if(ret) { ++ printk("Irda Startup failed\r\n"); ++ return ret; ++ } ++ ++ ret = s3c_irda_set_speed(si, si->speed = 9600); ++ if(ret) ++ s3c_irda_sir_stop(si); ++ ++ return ret; ++} ++ ++static void s3c_irda_shutdown(struct s3c_irda *si) ++{ ++ DBG("%s\r\n", __FUNCTION__); ++ s3c_irda_sir_stop(si); ++} ++ ++ ++#if defined(CONFIG_PM) ++/* ++ * Suspend the IrDA interface. ++ */ ++static int s3c_irda_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct net_device *dev = platform_get_drvdata(pdev); ++ struct s3c_irda *si; ++ ++ DBG("%s\r\n", __FUNCTION__); ++ ++ if(!dev) ++ return 0; ++ ++ si = dev->priv; ++ if(si->open) { ++ /* Stop the transmit queue */ ++ netif_device_detach(dev); ++ s3c_irda_shutdown(si); ++ __s3c_irda_set_power(si, 0); ++ } ++ ++ return 0; ++} ++ ++ ++/* ++ * Resume the IrDA interface. ++ */ ++static int s3c_irda_resume(struct platform_device *pdev) ++{ ++ struct net_device *dev = platform_get_drvdata(pdev); ++ struct s3c_irda *si; ++ ++ DBG("%s\r\n", __FUNCTION__); ++ ++ if(!dev) ++ return 0; ++ ++ si = dev->priv; ++ if(si->open) { ++ /* ++ * If we missed a speed change, initialise at the new speed ++ * directly. It is debatable whether this is actually ++ * required, but in the interests of continuing from where ++ * we left off it is desireable. The converse argument is ++ * that we should re-negotiate at 9600 baud again. ++ */ ++ if(si->newspeed) { ++ si->speed = si->newspeed; ++ si->newspeed = 0; ++ } ++ ++ s3c_irda_startup(si); ++ __s3c_irda_set_power(si, si->power); ++ ++ ++ /* This automatically wakes up the queue */ ++ netif_device_attach(dev); ++ } ++ ++ return 0; ++} ++#else ++#define s3c_irda_suspend NULL ++#define s3c_irda_resume NULL ++#endif ++ ++ ++/* ++ * SIR format interrupt service routines. ++ */ ++static irqreturn_t s3c_irda_sir_irq(int irq, void *dev_id) ++{ ++ ++ struct net_device *dev = dev_id; ++ struct s3c_irda *si = dev->priv; ++ int err_status; ++ ++ u8 data; ++ u32 ucon, ufcon, ufstat; ++ ++ ++ err_status = sir_readreg(S3C_UERSTAT); ++ ++ if(err_status) { ++ printk("Error : 0x%x\n", sir_readreg(S3C_UERSTAT)); ++ data = sir_readreg(S3C_URXH); ++ si->stats.rx_errors++; ++ si->stats.rx_frame_errors++; ++ } ++ ++ if(irq == si->sir_irq_rx){ ++ DBG("Rx intr : 0x%1x\n", intpnd); ++ ++ while ((sir_readreg(S3C_UFSTAT) & 0X3F) > 0) { ++ data = sir_readreg(S3C_URXH); ++ async_unwrap_char(dev, &si->stats, &si->rx_buff, data); ++ } ++ dev->last_rx = jiffies; ++ ++ /* Clear FIFO */ ++ ufcon = sir_readreg(S3C_UFCON); ++ ufcon |= 3; ++ sir_writereg(ufcon, S3C_UFCON); ++ } ++ ++ if(irq == si->sir_irq_tx) { ++ DBG("Tx intr : 0x%1x\n", intpnd); ++ ++ if(si->tx_buff.len > 0) { ++ ufstat = sir_readreg(S3C_UFSTAT); ++ ++ /* Transmitter FIFO is not full */ ++ while (!(ufstat & (1 << 14)) ) { ++ while(!(sir_readreg(S3C_UTRSTAT) & 0x02)); ++ sir_writereg(*si->tx_buff.data++, S3C_UTXH); ++ if(si->tx_buff.len == 0) ++ break; ++ si->tx_buff.len -= 1; ++ rmb(); ++ ufstat = sir_readreg(S3C_UFSTAT); ++ } ++ ++ if(si->tx_buff.len == 0) { ++ si->stats.tx_packets++; ++ si->stats.tx_bytes += si->tx_buff.data - ++ si->tx_buff.head; ++ ++ /* We need to ensure that transmit has finished */ ++ do { ++ rmb(); ++ ufstat = sir_readreg(S3C_UFSTAT); ++ } while (((ufstat >> 8) & 0x3f) > 0); ++ ++ ++ /* Transmission complete. Now enable the receiver. ++ * Sometimes we get a receive IRQ immediately ++ * after a transmit ++ */ ++ ++ ufcon = sir_readreg(S3C_UFCON); ++ ufcon |= 7; ++ sir_writereg(ufcon, S3C_UFCON); ++ ++ ucon = sir_readreg(S3C_UCON); ++ ucon &= ~( 3 << 2); ++ sir_writereg(ucon, S3C_UCON); ++ ++ if(si->newspeed) { ++ s3c_irda_set_speed(si, si->newspeed); ++ si->newspeed = 0; ++ } ++ ++ if(1) { ++ ucon |= 1; ++ sir_writereg(ucon, S3C_UCON); ++ } ++ ++ netif_wake_queue(dev); ++ } ++ } ++ } ++ return IRQ_HANDLED; ++} ++ ++static int s3c_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev) ++{ ++ struct s3c_irda *si = dev->priv; ++ int speed = irda_get_next_speed(skb); ++ ++ DBG("%s\r\n", __FUNCTION__); ++ ++ /* ++ * Does this packet contain a request to change the interface ++ * speed? If so, remember it until we complete the transmission ++ * of this frame. ++ */ ++ if(speed != si->speed && speed != -1) { ++ DBG("Irda New Speed %d bps\r\n", speed); ++ si->newspeed = speed; ++ } ++ ++ /* If this is an empty frame, we can bypass a lot */ ++ if(skb->len == 0) { ++ if(si->newspeed) { ++ si->newspeed = 0; ++ s3c_irda_set_speed(si, speed); ++ } ++ dev_kfree_skb(skb); ++ return 0; ++ } ++ ++ { ++ u32 ucon, ufcon, len; ++ u8 *cp; ++ ++ netif_stop_queue(dev); ++ ++ cp = si->tx_buff.data = si->tx_buff.head; ++ len = si->tx_buff.len = async_wrap_skb(skb, si->tx_buff.data, ++ si->tx_buff.truesize); ++ ++ /* ++ * Set the transmit interrupt enable. This will fire ++ * off an interrupt immediately. Note that we disable ++ * the receiver so we won't get spurious characteres ++ * received. ++ */ ++ ++ /* Stop Rx ++ * UCON : Receive Mode Disable ++ */ ++ ucon = sir_readreg(S3C_UCON); ++ ucon &= ~( 3); ++ sir_writereg(ucon, S3C_UCON); ++ ++ /* Clear FIFO */ ++ ufcon = sir_readreg(S3C_UFCON); ++ ufcon |= 7; ++ sir_writereg(ufcon, S3C_UFCON); ++ ++ /* UCON : Transmit Mode - 01 - Interrupt request or polling mode */ ++ ucon |= (1 << 2 ); ++ sir_writereg(ucon, S3C_UCON); ++ ++ dev_kfree_skb(skb); ++ } ++ ++ dev->trans_start = jiffies; ++ return 0; ++} ++ ++ ++static int s3c_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd) ++{ ++ struct if_irda_req *rq = (struct if_irda_req *)ifreq; ++ struct s3c_irda *si = dev->priv; ++ int ret = -EOPNOTSUPP; ++ ++ DBG("%s\r\n", __FUNCTION__); ++ ++ switch (cmd) { ++ case SIOCSBANDWIDTH: ++ ++ if(capable(CAP_NET_ADMIN)) { ++ ++ /* We are unable to set the speed if the device is not running */ ++ if(si->open) ++ ret = s3c_irda_set_speed(si, ++ rq->ifr_baudrate); ++ else { ++ DBG("s3c_irda_ioctl: SIOCSBANDWIDTH: !netif_running\n"); ++ ret = 0; ++ } ++ } ++ break; ++ ++ case SIOCSMEDIABUSY: ++ ret = -EPERM; ++ if(capable(CAP_NET_ADMIN)) { ++ irda_device_set_media_busy(dev, TRUE); ++ ret = 0; ++ } ++ break; ++ ++ case SIOCGRECEIVING: ++ rq->ifr_receiving = si->rx_buff.state != OUTSIDE_FRAME; ++ ret = 0; ++ break; ++ ++ default: ++ break; ++ } ++ ++ return ret; ++} ++ ++ ++static struct net_device_stats *s3c_irda_stats(struct net_device *dev) ++{ ++ struct s3c_irda *si = dev->priv; ++ ++ DBG("%s\r\n", __FUNCTION__); ++ return &si->stats; ++} ++ ++static int s3c_irda_start(struct net_device *dev) ++{ ++ struct s3c_irda *si = dev->priv; ++ int err; ++ ++ DBG("%s\r\n", __FUNCTION__); ++ ++ si->speed = 9600; ++ ++ err = request_irq(si->sir_irq_rx, s3c_irda_sir_irq, 0, dev->name, dev); ++ if(err) ++ goto err_irq1; ++ ++ err = request_irq(si->sir_irq_tx, s3c_irda_sir_irq, 0, dev->name, dev); ++ if(err) ++ goto err_irq1; ++ ++ /* The interrupt must remain disabled for now */ ++ disable_irq(si->sir_irq_rx); ++ disable_irq(si->sir_irq_tx); ++ ++ ++ /* Setup the serial port for the specified speed */ ++ err = s3c_irda_startup(si); ++ if(err) ++ goto err_irq2; ++ ++ ++ /* Open a new IrLAP layer instance */ ++ si->irlap = irlap_open(dev, &si->qos, "s3c"); ++ ++ err = -ENOMEM; ++ if(!si->irlap) ++ goto err_irlap; ++ ++ ++ /* Now enable the interrupt and start the queue */ ++ enable_irq(si->sir_irq_rx); ++ enable_irq(si->sir_irq_tx); ++ si->open = 1; ++ netif_start_queue(dev); ++ sir_writereg(0, S3C_UINTMSK); ++ ++ return 0; ++ ++err_irlap: ++ si->open = 0; ++ s3c_irda_shutdown(si); ++err_irq2: ++ free_irq(si->sir_irq_rx, dev); ++ free_irq(si->sir_irq_tx, dev); ++err_irq1: ++ return err; ++} ++ ++static int s3c_irda_stop(struct net_device *dev) ++{ ++ struct s3c_irda *si = dev->priv; ++ ++ DBG("%s\r\n", __FUNCTION__); ++ ++ disable_irq(si->sir_irq_rx); ++ disable_irq(si->sir_irq_tx); ++ ++ s3c_irda_shutdown(si); ++ ++ /* Clean up */ ++ if(si->rxskb) { ++ dev_kfree_skb(si->rxskb); ++ si->rxskb = NULL; ++ } ++ ++ /* Stop IrLAP */ ++ if(si->irlap) { ++ irlap_close(si->irlap); ++ si->irlap = NULL; ++ } ++ ++ netif_stop_queue(dev); ++ si->open = 0; ++ ++ return 0; ++} ++ ++static int s3c_irda_init_iobuf(iobuff_t *io, int size) ++{ ++ DBG("%s\r\n", __FUNCTION__); ++ ++ io->head = kmalloc(size, GFP_KERNEL | GFP_DMA); ++ ++ if(io->head != NULL) { ++ io->truesize = size; ++ io->in_frame = FALSE; ++ io->state = OUTSIDE_FRAME; ++ io->data = io->head; ++ } ++ ++ return io->head ? 0 : -ENOMEM; ++} ++ ++ ++static int s3c_irda_init_mem( struct s3c_irda *si, ++ struct platform_device *pdev) ++{ ++ int ret = 0; ++ ++ DBG("%s\r\n", __FUNCTION__); ++ ++ si->sir_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ++ if(!si->sir_mem) { ++ printk("failed to get io sir_memory region resouce.\n"); ++ return -ENOENT; ++ } ++ ++ if(NULL == request_mem_region(si->sir_mem->start, ++ RESSIZE(si->sir_mem), pdev->name)) { ++ printk("failed to request io sir memory region.\n"); ++ ret = -ENOENT; ++ } ++ ++ return ret; ++} ++ ++ ++static int s3c_irda_free_mem( struct s3c_irda *si) ++{ ++ DBG("%s\r\n", __FUNCTION__); ++ ++ release_mem_region(si->sir_mem->start, RESSIZE(si->sir_mem)); ++ return 0; ++} ++ ++static int s3c_irda_init_clk(struct device *dev, ++ struct s3c_irda *si) ++{ ++ int ret; ++ DBG("%s \r\n", __FUNCTION__); ++ ++ si->sir_clk = clk_get(dev, "uart"); ++ ++ if(IS_ERR(si->sir_clk)) { ++ DBG(KERN_INFO PFX "failed to find sir clock source.\n"); ++ ret = PTR_ERR(si->sir_clk); ++ si->sir_clk = NULL; ++ goto sir_free_si; ++ } ++ ++ if((ret = clk_enable(si->sir_clk))) { ++ printk("failed to use sir clock source.\n"); ++ ret =-ENODEV; ++ goto sir_clk_free; ++ } ++ ++ return 0; ++ ++sir_clk_free: ++ clk_put(si->sir_clk); ++sir_free_si: ++ return ret; ++} ++ ++ ++static int s3c_irda_stop_clk( struct s3c_irda *si) ++{ ++ DBG("%s\r\n", __FUNCTION__); ++ ++ clk_disable(si->sir_clk); ++ clk_put(si->sir_clk); ++ return 0; ++} ++ ++ ++static int s3c_irda_probe(struct platform_device *pdev) ++{ ++ struct net_device *dev; ++ struct s3c_irda *si; ++ unsigned int baudrate_mask; ++ int err; ++ ++ DBG("%s\r\n", __FUNCTION__); ++ ++ dev = alloc_irdadev(sizeof(struct s3c_irda)); ++ if(!dev){ ++ printk("alloc_irdadev Error! \r\n"); ++ return -ENOMEM; ++ } ++ ++ si = dev->priv; ++ si->dev = &pdev->dev; ++ si->pdata = pdev->dev.platform_data; ++ ++ if((err = s3c_irda_init_mem(si, pdev)) != 0) ++ goto err_mem; ++ ++ ++ err = s3c_irda_init_iobuf(&si->rx_buff, 14384); ++ if(err) ++ goto err_iobuf_rx; ++ ++ err = s3c_irda_init_iobuf(&si->tx_buff, 14384); ++ if(err) ++ goto err_iobuf_tx; ++ ++ dev->hard_start_xmit = s3c_irda_hard_xmit; ++ dev->open = s3c_irda_start; ++ dev->stop = s3c_irda_stop; ++ dev->do_ioctl = s3c_irda_ioctl; ++ dev->get_stats = s3c_irda_stats; ++ ++ si->sir_irq_rx = platform_get_irq(pdev, 0); ++ ++ if(si->sir_irq_rx == 0) { ++ printk("failed to get rx interrupt resource.\n"); ++ goto err_irq; ++ } ++ ++ si->sir_irq_tx = platform_get_irq(pdev, 1); ++ ++ if(si->sir_irq_tx == 0) { ++ printk("failed to get tx interrupt resource.\n"); ++ goto err_irq; ++ } ++ ++ if(s3c_irda_init_clk(&pdev->dev, si)!= 0) ++ goto err_irq; ++ ++ irda_init_max_qos_capabilies(&si->qos); ++ ++ baudrate_mask = IR_9600 | IR_19200 | IR_38400 | IR_57600 | IR_115200; ++ ++ switch (max_rate) { ++ case 115200: baudrate_mask |= IR_115200; ++ case 57600: baudrate_mask |= IR_57600; ++ case 38400: baudrate_mask |= IR_38400; ++ case 19200: baudrate_mask |= IR_19200; ++ } ++ ++ si->qos.baud_rate.bits &= baudrate_mask; ++ si->qos.min_turn_time.bits = 7; ++ ++ irda_qos_bits_to_value(&si->qos); ++ ++ sir_writereg(0, S3C_UCON); ++ sir_writereg(0, S3C_ULCON); ++ ++ err = register_netdev(dev); ++ if(err == 0) { ++ platform_set_drvdata(pdev, dev); ++ DBG("%s success \r\n", __FUNCTION__); ++ } ++ ++ if(err) { ++ s3c_irda_stop_clk(si); ++ err_irq: ++ kfree(si->tx_buff.head); ++ err_iobuf_tx: ++ kfree(si->rx_buff.head); ++ err_iobuf_rx: ++ s3c_irda_free_mem(si); ++ err_mem: ++ free_netdev(dev); ++ } ++ return err; ++} ++ ++ ++static int s3c_irda_remove(struct platform_device *pdev) ++{ ++ struct net_device *dev = platform_get_drvdata(pdev); ++ ++ DBG("%s\r\n", __FUNCTION__); ++ ++ if(dev) { ++ struct s3c_irda *si = dev->priv; ++ unregister_netdev(dev); ++ kfree(si->tx_buff.head); ++ kfree(si->rx_buff.head); ++ s3c_irda_free_mem(si); ++ s3c_irda_stop_clk(si); ++ free_netdev(dev); ++ } ++ ++ return 0; ++} ++ ++ ++static struct platform_driver s3c_irda_driver = { ++ .probe = s3c_irda_probe, ++ .remove = s3c_irda_remove, ++ .suspend = s3c_irda_suspend, ++ .resume = s3c_irda_resume, ++ .driver = { ++ .name = "s3c-irda", ++ }, ++}; ++ ++static char banner[] = KERN_INFO "S3C IrDA driver, (c) 2009 Samsung Electronics\n"; ++ ++static int __init s3c_irda_init(void) ++{ ++ printk(banner); ++ return platform_driver_register(&s3c_irda_driver); ++ ++} ++ ++ ++static void __exit s3c_irda_exit(void) ++{ ++ platform_driver_unregister(&s3c_irda_driver); ++} ++ ++ ++module_init(s3c_irda_init); ++module_exit(s3c_irda_exit); ++ ++MODULE_AUTHOR("SAMSUNG"); ++MODULE_DESCRIPTION("S3C IrDA driver"); ++MODULE_LICENSE("GPL"); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/net/smc911x.c linux-2.6.28.6/drivers/net/smc911x.c +--- linux-2.6.28/drivers/net/smc911x.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/net/smc911x.c 2009-04-30 09:36:38.000000000 +0200 +@@ -861,14 +861,13 @@ + SMC_GET_MAC_CR(lp, cr); + if (lp->mii.full_duplex) { + DBG(SMC_DEBUG_MISC, "%s: Configuring for full-duplex mode\n", dev->name); +- bmcr |= BMCR_FULLDPLX; +- cr |= MAC_CR_RCVOWN_; ++ cr &= ~MAC_CR_RCVOWN_; ++ cr |= MAC_CR_FDPX_; + } else { + DBG(SMC_DEBUG_MISC, "%s: Configuring for half-duplex mode\n", dev->name); +- bmcr &= ~BMCR_FULLDPLX; + cr &= ~MAC_CR_RCVOWN_; ++ cr &= ~MAC_CR_FDPX_; + } +- SMC_SET_PHY_BMCR(lp, phyaddr, bmcr); + SMC_SET_MAC_CR(lp, cr); + } + } +@@ -1906,6 +1905,17 @@ + + spin_lock_init(&lp->lock); + ++#if defined(CONFIG_MACH_SMDK6410)||defined(CONFIG_MACH_SMDK2450)||defined(CONFIG_MACH_SMDKC100) ++ dev->dev_addr[0] = 0x00; ++ dev->dev_addr[1] = 0x09; ++ dev->dev_addr[2] = 0xc0; ++ dev->dev_addr[3] = 0xff; ++ dev->dev_addr[4] = 0xec; ++ dev->dev_addr[5] = 0x48; ++ ++ SMC_SET_MAC_ADDR(lp, dev->dev_addr); ++#endif ++ + /* Get the MAC address */ + SMC_GET_MAC_ADDR(lp, dev->dev_addr); + +@@ -1969,7 +1979,7 @@ + + /* Set default parameters */ + lp->msg_enable = NETIF_MSG_LINK; +- lp->ctl_rfduplx = 1; ++ lp->ctl_rfduplx = 0; + lp->ctl_rspeed = 100; + + #ifdef SMC_DYNAMIC_BUS_CONFIG +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/net/smc911x.h linux-2.6.28.6/drivers/net/smc911x.h +--- linux-2.6.28/drivers/net/smc911x.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/net/smc911x.h 2009-04-30 09:36:38.000000000 +0200 +@@ -38,7 +38,8 @@ + #define SMC_USE_16BIT 0 + #define SMC_USE_32BIT 1 + #define SMC_IRQ_SENSE IRQF_TRIGGER_FALLING +-#elif defined(CONFIG_SH_MAGIC_PANEL_R2) ++#elif defined(CONFIG_SH_MAGIC_PANEL_R2)||defined(CONFIG_MACH_SMDK6410)||defined(CONFIG_MACH_SMDK2450)||defined(CONFIG_MACH_SMDKC100) ++ #undef SMC_USE_DMA + #define SMC_USE_16BIT 0 + #define SMC_USE_32BIT 1 + #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/rtc/Kconfig linux-2.6.28.6/drivers/rtc/Kconfig +--- linux-2.6.28/drivers/rtc/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/rtc/Kconfig 2009-04-30 09:36:39.000000000 +0200 +@@ -508,7 +508,7 @@ + + config RTC_DRV_S3C + tristate "Samsung S3C series SoC RTC" +- depends on ARCH_S3C2410 ++ depends on ARCH_S3C2410 || ARCH_S3C64XX || ARCH_S5PC1XX || ARCH_S5P64XX + help + RTC (Realtime Clock) driver for the clock inbuilt into the + Samsung S3C24XX series of SoCs. This can provide periodic +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/rtc/rtc-s3c.c linux-2.6.28.6/drivers/rtc/rtc-s3c.c +--- linux-2.6.28/drivers/rtc/rtc-s3c.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/rtc/rtc-s3c.c 2009-04-30 09:36:39.000000000 +0200 +@@ -26,7 +26,8 @@ + #include + #include + #include +-#include ++#include ++#include + + /* I have yet to find an S3C implementation with more than one + * of these rtc blocks in */ +@@ -36,9 +37,18 @@ + static void __iomem *s3c_rtc_base; + static int s3c_rtc_alarmno = NO_IRQ; + static int s3c_rtc_tickno = NO_IRQ; ++static int s3c_rtc_freq = 1; + + static DEFINE_SPINLOCK(s3c_rtc_pie_lock); ++static unsigned int tick_count; + ++/* common function function */ ++ ++extern void s3c_rtc_set_pie(void __iomem *base, uint to); ++extern void s3c_rtc_set_freq_regs(void __iomem *base, uint freq, uint s3c_freq); ++extern void s3c_rtc_enable_set(struct platform_device *dev,void __iomem *base, int en); ++extern unsigned int s3c_rtc_set_bit_byte(void __iomem *base, uint offset, uint val); ++extern unsigned int s3c_rtc_read_alarm_status(void __iomem *base); + /* IRQ Handlers */ + + static irqreturn_t s3c_rtc_alarmirq(int irq, void *id) +@@ -46,6 +56,9 @@ + struct rtc_device *rdev = id; + + rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF); ++ ++ s3c_rtc_set_bit_byte(s3c_rtc_base,S3C2410_INTP,S3C2410_INTP_ALM); ++ + return IRQ_HANDLED; + } + +@@ -54,6 +67,9 @@ + struct rtc_device *rdev = id; + + rtc_update_irq(rdev, 1, RTC_PF | RTC_IRQF); ++ ++ s3c_rtc_set_bit_byte(s3c_rtc_base,S3C2410_INTP,S3C2410_INTP_TIC); ++ + return IRQ_HANDLED; + } + +@@ -74,17 +91,12 @@ + + static int s3c_rtc_setpie(struct device *dev, int enabled) + { +- unsigned int tmp; +- + pr_debug("%s: pie=%d\n", __func__, enabled); + + spin_lock_irq(&s3c_rtc_pie_lock); +- tmp = readb(s3c_rtc_base + S3C2410_TICNT) & ~S3C2410_TICNT_ENABLE; + +- if (enabled) +- tmp |= S3C2410_TICNT_ENABLE; ++ s3c_rtc_set_pie(s3c_rtc_base,enabled); + +- writeb(tmp, s3c_rtc_base + S3C2410_TICNT); + spin_unlock_irq(&s3c_rtc_pie_lock); + + return 0; +@@ -92,14 +104,10 @@ + + static int s3c_rtc_setfreq(struct device *dev, int freq) + { +- unsigned int tmp; +- + spin_lock_irq(&s3c_rtc_pie_lock); + +- tmp = readb(s3c_rtc_base + S3C2410_TICNT) & S3C2410_TICNT_ENABLE; +- tmp |= (128 / freq)-1; ++ s3c_rtc_set_freq_regs(s3c_rtc_base, freq, s3c_rtc_freq); + +- writeb(tmp, s3c_rtc_base + S3C2410_TICNT); + spin_unlock_irq(&s3c_rtc_pie_lock); + + return 0; +@@ -269,14 +277,55 @@ + + s3c_rtc_setaie(alrm->enabled); + +- if (alrm->enabled) +- enable_irq_wake(s3c_rtc_alarmno); +- else +- disable_irq_wake(s3c_rtc_alarmno); +- + return 0; + } + ++static int s3c_rtc_ioctl(struct device *dev, ++ unsigned int cmd, unsigned long arg) ++{ ++ unsigned int ret = -ENOIOCTLCMD; ++ ++ switch (cmd) { ++ case RTC_AIE_OFF: ++ case RTC_AIE_ON: ++ s3c_rtc_setaie((cmd == RTC_AIE_ON) ? 1 : 0); ++ ret = 0; ++ break; ++ ++ case RTC_PIE_OFF: ++ case RTC_PIE_ON: ++ tick_count = 0; ++ s3c_rtc_setpie(dev,(cmd == RTC_PIE_ON) ? 1 : 0); ++ ret = 0; ++ break; ++ ++ case RTC_IRQP_READ: ++ ret = put_user(s3c_rtc_freq, (unsigned long __user *)arg); ++ break; ++ ++ case RTC_IRQP_SET: ++ /* check for power of 2 */ ++ ++ if ((arg & (arg-1)) != 0 || arg < 1) { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ pr_debug("s3c2410_rtc: setting frequency %ld\n", arg); ++ ++ s3c_rtc_setfreq(dev, arg); ++ ret = 0; ++ break; ++ ++ case RTC_UIE_ON: ++ case RTC_UIE_OFF: ++ ret = -EINVAL; ++ } ++ ++ exit: ++ return ret; ++} ++ + static int s3c_rtc_proc(struct device *dev, struct seq_file *seq) + { + unsigned int ticnt = readb(s3c_rtc_base + S3C2410_TICNT); +@@ -330,6 +379,7 @@ + static const struct rtc_class_ops s3c_rtcops = { + .open = s3c_rtc_open, + .release = s3c_rtc_release, ++ .ioctl = s3c_rtc_ioctl, + .read_time = s3c_rtc_gettime, + .set_time = s3c_rtc_settime, + .read_alarm = s3c_rtc_getalarm, +@@ -342,44 +392,14 @@ + static void s3c_rtc_enable(struct platform_device *pdev, int en) + { + void __iomem *base = s3c_rtc_base; +- unsigned int tmp; + + if (s3c_rtc_base == NULL) + return; + +- if (!en) { +- tmp = readb(base + S3C2410_RTCCON); +- writeb(tmp & ~S3C2410_RTCCON_RTCEN, base + S3C2410_RTCCON); +- +- tmp = readb(base + S3C2410_TICNT); +- writeb(tmp & ~S3C2410_TICNT_ENABLE, base + S3C2410_TICNT); +- } else { +- /* re-enable the device, and check it is ok */ +- +- if ((readb(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0){ +- dev_info(&pdev->dev, "rtc disabled, re-enabling\n"); +- +- tmp = readb(base + S3C2410_RTCCON); +- writeb(tmp|S3C2410_RTCCON_RTCEN, base+S3C2410_RTCCON); +- } +- +- if ((readb(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)){ +- dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n"); +- +- tmp = readb(base + S3C2410_RTCCON); +- writeb(tmp& ~S3C2410_RTCCON_CNTSEL, base+S3C2410_RTCCON); +- } +- +- if ((readb(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)){ +- dev_info(&pdev->dev, "removing RTCCON_CLKRST\n"); +- +- tmp = readb(base + S3C2410_RTCCON); +- writeb(tmp & ~S3C2410_RTCCON_CLKRST, base+S3C2410_RTCCON); +- } +- } ++ s3c_rtc_enable_set(pdev,base,en); + } + +-static int __devexit s3c_rtc_remove(struct platform_device *dev) ++static int s3c_rtc_remove(struct platform_device *dev) + { + struct rtc_device *rtc = platform_get_drvdata(dev); + +@@ -396,11 +416,12 @@ + return 0; + } + +-static int __devinit s3c_rtc_probe(struct platform_device *pdev) ++static int s3c_rtc_probe(struct platform_device *pdev) + { + struct rtc_device *rtc; + struct resource *res; + int ret; ++ unsigned char bcd_tmp,bcd_loop; + + pr_debug("%s: probe=%p\n", __func__, pdev); + +@@ -418,7 +439,7 @@ + return -ENOENT; + } + +- pr_debug("s3c2410_rtc: tick irq %d, alarm irq %d\n", ++ printk("s3c2410_rtc: tick irq %d, alarm irq %d\n", + s3c_rtc_tickno, s3c_rtc_alarmno); + + /* get the memory region */ +@@ -468,9 +489,18 @@ + goto err_nortc; + } + +- rtc->max_user_freq = 128; ++ rtc->max_user_freq = S3C_MAX_CNT; ++ ++ /* check rtc time */ ++ for (bcd_loop = S3C2410_RTCSEC ; bcd_loop <= S3C2410_RTCYEAR ; bcd_loop +=0x4) ++ { ++ bcd_tmp = readb(s3c_rtc_base + bcd_loop); ++ if(((bcd_tmp & 0xf) > 0x9) || ((bcd_tmp & 0xf0) > 0x90)) ++ writeb(0, s3c_rtc_base + bcd_loop); ++ } + + platform_set_drvdata(pdev, rtc); ++ + return 0; + + err_nortc: +@@ -488,19 +518,37 @@ + + /* RTC Power management control */ + ++static struct timespec s3c_rtc_delta; + static int ticnt_save; + + static int s3c_rtc_suspend(struct platform_device *pdev, pm_message_t state) + { ++ struct rtc_time tm; ++ struct timespec time; ++ ++ time.tv_nsec = 0; + /* save TICNT for anyone using periodic interrupts */ + ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT); ++ ++ s3c_rtc_gettime(&pdev->dev, &tm); ++ rtc_tm_to_time(&tm, &time.tv_sec); ++ save_time_delta(&s3c_rtc_delta, &time); ++ + s3c_rtc_enable(pdev, 0); + return 0; + } + + static int s3c_rtc_resume(struct platform_device *pdev) + { ++ struct rtc_time tm; ++ struct timespec time; ++ ++ time.tv_nsec = 0; ++ + s3c_rtc_enable(pdev, 1); ++ s3c_rtc_gettime(&pdev->dev, &tm); ++ rtc_tm_to_time(&tm, &time.tv_sec); ++ restore_time_delta(&s3c_rtc_delta, &time); + writeb(ticnt_save, s3c_rtc_base + S3C2410_TICNT); + return 0; + } +@@ -511,7 +559,7 @@ + + static struct platform_driver s3c2410_rtc_driver = { + .probe = s3c_rtc_probe, +- .remove = __devexit_p(s3c_rtc_remove), ++ .remove = s3c_rtc_remove, + .suspend = s3c_rtc_suspend, + .resume = s3c_rtc_resume, + .driver = { +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/serial/Kconfig linux-2.6.28.6/drivers/serial/Kconfig +--- linux-2.6.28/drivers/serial/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/serial/Kconfig 2009-04-30 09:36:39.000000000 +0200 +@@ -447,7 +447,7 @@ + + config SERIAL_SAMSUNG + tristate "Samsung SoC serial support" +- depends on ARM && PLAT_S3C24XX ++ depends on ARM && PLAT_S3C + select SERIAL_CORE + help + Support for the on-chip UARTs on the Samsung S3C24XX series CPUs, +@@ -455,6 +455,16 @@ + provide all of these ports, depending on how the serial port + pins are configured. + ++config SERIAL_SAMSUNG_UARTS ++ int ++ depends on SERIAL_SAMSUNG ++ default 2 if ARCH_S3C2400 ++ default 4 if ARCH_S3C64XX || ARCH_S5P64XX || CPU_S3C2443 || ARCH_S5PC1XX ++ default 3 ++ help ++ Select the number of available UART ports for the Samsung S3C ++ serial driver ++ + config SERIAL_SAMSUNG_DEBUG + bool "Samsung SoC serial debug" + depends on SERIAL_SAMSUNG && DEBUG_LL +@@ -508,7 +518,34 @@ + help + Serial port support for the Samsung S3C2440 and S3C2442 SoC + ++config SERIAL_S3C24A0 ++ tristate "Samsung S3C24A0 Serial port support" ++ depends on SERIAL_SAMSUNG && CPU_S3C24A0 ++ default y if CPU_S3C24A0 ++ help ++ Serial port support for the Samsung S3C24A0 SoC ++ ++config SERIAL_S3C6400 ++ tristate "Samsung S3C6400/S3C6410/S5P6440 Serial port support" ++ depends on SERIAL_SAMSUNG && (CPU_S3C6400 || CPU_S3C6410 || CPU_S5P6440) ++ default y ++ help ++ Serial port support for the Samsung S3C6400, S3C6410 and S5P6440 ++ SoCs ++ ++config SERIAL_S5PC100 ++ tristate "Samsung S5PC100 Serial port support" ++ depends on SERIAL_SAMSUNG && CPU_S5PC100 ++ default y ++ help ++ Serial port support for the Samsung S5PC100 SoCs + ++config SERIAL_S5PC1XX_HSUART ++ bool "Support for High speed UART(4Mbps) on S5PC1XX serial port" ++ depends on SERIAL_S5PC100=y ++ select SERIAL_CORE ++ help ++ Allow High speed UART on the S5PC1XX on-board serial ports + + config SERIAL_DZ + bool "DECstation DZ serial driver" +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/serial/Makefile linux-2.6.28.6/drivers/serial/Makefile +--- linux-2.6.28/drivers/serial/Makefile 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/serial/Makefile 2009-04-30 09:36:39.000000000 +0200 +@@ -41,6 +41,9 @@ + obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o + obj-$(CONFIG_SERIAL_S3C2412) += s3c2412.o + obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o ++obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o ++obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o ++obj-$(CONFIG_SERIAL_S5PC100) += s5pc100.o + obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o + obj-$(CONFIG_SERIAL_MUX) += mux.o + obj-$(CONFIG_SERIAL_68328) += 68328serial.o +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/serial/s3c24a0.c linux-2.6.28.6/drivers/serial/s3c24a0.c +--- linux-2.6.28/drivers/serial/s3c24a0.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/serial/s3c24a0.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,118 @@ ++/* linux/drivers/serial/s3c24a0.c ++ * ++ * Driver for Samsung S3C24A0 SoC onboard UARTs. ++ * ++ * Based on drivers/serial/s3c2410.c ++ * ++ * Author: Sandeep Patil ++ * ++ * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++ ++#include "samsung.h" ++ ++static int s3c24a0_serial_setsource(struct uart_port *port, ++ struct s3c24xx_uart_clksrc *clk) ++{ ++ unsigned long ucon = rd_regl(port, S3C2410_UCON); ++ ++ if (strcmp(clk->name, "uclk") == 0) ++ ucon |= S3C2410_UCON_UCLK; ++ else ++ ucon &= ~S3C2410_UCON_UCLK; ++ ++ wr_regl(port, S3C2410_UCON, ucon); ++ return 0; ++} ++ ++static int s3c24a0_serial_getsource(struct uart_port *port, ++ struct s3c24xx_uart_clksrc *clk) ++{ ++ unsigned long ucon = rd_regl(port, S3C2410_UCON); ++ ++ clk->divisor = 1; ++ clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk"; ++ ++ return 0; ++} ++ ++static int s3c24a0_serial_resetport(struct uart_port *port, ++ struct s3c2410_uartcfg *cfg) ++{ ++ dbg("s3c24a0_serial_resetport: port=%p (%08lx), cfg=%p\n", ++ port, port->mapbase, cfg); ++ ++ wr_regl(port, S3C2410_UCON, cfg->ucon); ++ wr_regl(port, S3C2410_ULCON, cfg->ulcon); ++ ++ /* reset both fifos */ ++ ++ wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); ++ wr_regl(port, S3C2410_UFCON, cfg->ufcon); ++ ++ return 0; ++} ++ ++static struct s3c24xx_uart_info s3c24a0_uart_inf = { ++ .name = "Samsung S3C24A0 UART", ++ .type = PORT_S3C2410, ++ .fifosize = 16, ++ .rx_fifomask = S3C24A0_UFSTAT_RXMASK, ++ .rx_fifoshift = S3C24A0_UFSTAT_RXSHIFT, ++ .rx_fifofull = S3C24A0_UFSTAT_RXFULL, ++ .tx_fifofull = S3C24A0_UFSTAT_TXFULL, ++ .tx_fifomask = S3C24A0_UFSTAT_TXMASK, ++ .tx_fifoshift = S3C24A0_UFSTAT_TXSHIFT, ++ .get_clksrc = s3c24a0_serial_getsource, ++ .set_clksrc = s3c24a0_serial_setsource, ++ .reset_port = s3c24a0_serial_resetport, ++}; ++ ++static int s3c24a0_serial_probe(struct platform_device *dev) ++{ ++ return s3c24xx_serial_probe(dev, &s3c24a0_uart_inf); ++} ++ ++static struct platform_driver s3c24a0_serial_drv = { ++ .probe = s3c24a0_serial_probe, ++ .remove = s3c24xx_serial_remove, ++ .driver = { ++ .name = "s3c24a0-uart", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++s3c24xx_console_init(&s3c24a0_serial_drv, &s3c24a0_uart_inf); ++ ++static int __init s3c24a0_serial_init(void) ++{ ++ return s3c24xx_serial_init(&s3c24a0_serial_drv, &s3c24a0_uart_inf); ++} ++ ++static void __exit s3c24a0_serial_exit(void) ++{ ++ platform_driver_unregister(&s3c24a0_serial_drv); ++} ++ ++module_init(s3c24a0_serial_init); ++module_exit(s3c24a0_serial_exit); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/serial/s3c6400.c linux-2.6.28.6/drivers/serial/s3c6400.c +--- linux-2.6.28/drivers/serial/s3c6400.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/serial/s3c6400.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,151 @@ ++/* linux/drivers/serial/s3c6400.c ++ * ++ * Driver for Samsung S3C6400 and S3C6410 SoC onboard UARTs. ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++#include "samsung.h" ++ ++static int s3c6400_serial_setsource(struct uart_port *port, ++ struct s3c24xx_uart_clksrc *clk) ++{ ++ unsigned long ucon = rd_regl(port, S3C2410_UCON); ++ ++ if (strcmp(clk->name, "uclk0") == 0) { ++ ucon &= ~S3C6400_UCON_CLKMASK; ++ ucon |= S3C6400_UCON_UCLK0; ++ } else if (strcmp(clk->name, "uclk1") == 0) ++ ucon |= S3C6400_UCON_UCLK1; ++ else if (strcmp(clk->name, "pclk") == 0) { ++ /* See notes about transitioning from UCLK to PCLK */ ++ ucon &= ~S3C6400_UCON_UCLK0; ++ } else { ++ printk(KERN_ERR "unknown clock source %s\n", clk->name); ++ return -EINVAL; ++ } ++ ++ wr_regl(port, S3C2410_UCON, ucon); ++ return 0; ++} ++ ++ ++static int s3c6400_serial_getsource(struct uart_port *port, ++ struct s3c24xx_uart_clksrc *clk) ++{ ++ u32 ucon = rd_regl(port, S3C2410_UCON); ++ ++ clk->divisor = 1; ++ ++ switch (ucon & S3C6400_UCON_CLKMASK) { ++ case S3C6400_UCON_UCLK0: ++ clk->name = "uclk0"; ++ break; ++ ++ case S3C6400_UCON_UCLK1: ++ clk->name = "uclk1"; ++ break; ++ ++ case S3C6400_UCON_PCLK: ++ case S3C6400_UCON_PCLK2: ++ clk->name = "pclk"; ++ break; ++ } ++ ++ return 0; ++} ++ ++static int s3c6400_serial_resetport(struct uart_port *port, ++ struct s3c2410_uartcfg *cfg) ++{ ++ unsigned long ucon = rd_regl(port, S3C2410_UCON); ++ ++ dbg("s3c6400_serial_resetport: port=%p (%08lx), cfg=%p\n", ++ port, port->mapbase, cfg); ++ ++ /* ensure we don't change the clock settings... */ ++ ++ ucon &= S3C6400_UCON_CLKMASK; ++ ++ wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); ++ wr_regl(port, S3C2410_ULCON, cfg->ulcon); ++ ++ /* reset both fifos */ ++ ++ wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); ++ wr_regl(port, S3C2410_UFCON, cfg->ufcon); ++ ++ return 0; ++} ++ ++static struct s3c24xx_uart_info s3c6400_uart_inf = { ++ .name = "Samsung S3C6400 UART", ++ .type = PORT_S3C6400, ++ .fifosize = 64, ++ .rx_fifomask = S3C2440_UFSTAT_RXMASK, ++ .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, ++ .rx_fifofull = S3C2440_UFSTAT_RXFULL, ++ .tx_fifofull = S3C2440_UFSTAT_TXFULL, ++ .tx_fifomask = S3C2440_UFSTAT_TXMASK, ++ .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, ++ .get_clksrc = s3c6400_serial_getsource, ++ .set_clksrc = s3c6400_serial_setsource, ++ .reset_port = s3c6400_serial_resetport, ++}; ++ ++/* device management */ ++ ++static int s3c6400_serial_probe(struct platform_device *dev) ++{ ++ dbg("s3c6400_serial_probe: dev=%p\n", dev); ++ return s3c24xx_serial_probe(dev, &s3c6400_uart_inf); ++} ++ ++static struct platform_driver s3c6400_serial_drv = { ++ .probe = s3c6400_serial_probe, ++ .remove = s3c24xx_serial_remove, ++ .driver = { ++ .name = "s3c6400-uart", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++s3c24xx_console_init(&s3c6400_serial_drv, &s3c6400_uart_inf); ++ ++static int __init s3c6400_serial_init(void) ++{ ++ return s3c24xx_serial_init(&s3c6400_serial_drv, &s3c6400_uart_inf); ++} ++ ++static void __exit s3c6400_serial_exit(void) ++{ ++ platform_driver_unregister(&s3c6400_serial_drv); ++} ++ ++module_init(s3c6400_serial_init); ++module_exit(s3c6400_serial_exit); ++ ++MODULE_DESCRIPTION("Samsung S3C6400,S3C6410 SoC Serial port driver"); ++MODULE_AUTHOR("Ben Dooks "); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:s3c6400-uart"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/serial/s5pc100.c linux-2.6.28.6/drivers/serial/s5pc100.c +--- linux-2.6.28/drivers/serial/s5pc100.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/serial/s5pc100.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,148 @@ ++/* linux/drivers/serial/s3c6400.c ++ * ++ * Driver for Samsung S3C6400 and S3C6410 SoC onboard UARTs. ++ * ++ * Copyright 2008 Openmoko, Inc. ++ * Copyright 2008 Simtec Electronics ++ * Ben Dooks ++ * http://armlinux.simtec.co.uk/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++*/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++#include "samsung.h" ++ ++static int s3c6400_serial_setsource(struct uart_port *port, ++ struct s3c24xx_uart_clksrc *clk) ++{ ++ unsigned long ucon = rd_regl(port, S3C2410_UCON); ++ ++ if (strcmp(clk->name, "uclk0") == 0) { ++ ucon &= ~S3C6400_UCON_CLKMASK; ++ ucon |= S3C6400_UCON_UCLK0; ++ } else if (strcmp(clk->name, "uclk1") == 0) ++ ucon |= S3C6400_UCON_UCLK1; ++ else if (strcmp(clk->name, "pclk") == 0) { ++ /* See notes about transitioning from UCLK to PCLK */ ++ ucon &= ~S3C6400_UCON_UCLK0; ++ } else { ++ printk(KERN_ERR "unknown clock source %s\n", clk->name); ++ return -EINVAL; ++ } ++ ++ wr_regl(port, S3C2410_UCON, ucon); ++ return 0; ++} ++ ++ ++static int s3c6400_serial_getsource(struct uart_port *port, ++ struct s3c24xx_uart_clksrc *clk) ++{ ++ u32 ucon = rd_regl(port, S3C2410_UCON); ++ ++ clk->divisor = 1; ++ ++ switch (ucon & S3C6400_UCON_CLKMASK) { ++ case S3C6400_UCON_UCLK0: ++ clk->name = "uclk0"; ++ break; ++ ++ case S3C6400_UCON_UCLK1: ++ clk->name = "uclk1"; ++ break; ++ ++ case S3C6400_UCON_PCLK: ++ case S3C6400_UCON_PCLK2: ++ clk->name = "pclk"; ++ break; ++ } ++ ++ return 0; ++} ++ ++static int s3c6400_serial_resetport(struct uart_port *port, ++ struct s3c2410_uartcfg *cfg) ++{ ++ unsigned long ucon = rd_regl(port, S3C2410_UCON); ++ ++ dbg("s3c6400_serial_resetport: port=%p (%08lx), cfg=%p\n", ++ port, port->mapbase, cfg); ++ ++ ucon &= S3C6400_UCON_CLKMASK; ++ ++ wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); ++ wr_regl(port, S3C2410_ULCON, cfg->ulcon); ++ ++ /* reset both fifos */ ++ ++ wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); ++ wr_regl(port, S3C2410_UFCON, cfg->ufcon); ++ ++ return 0; ++} ++ ++static struct s3c24xx_uart_info s5p_uart_inf = { ++ .name = "Samsung S5PC100 UART", ++ .type = PORT_S3C6400, ++ .fifosize = 64, ++ .rx_fifomask = S3C2440_UFSTAT_RXMASK, ++ .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, ++ .rx_fifofull = S3C2440_UFSTAT_RXFULL, ++ .tx_fifofull = S3C2440_UFSTAT_TXFULL, ++ .tx_fifomask = S3C2440_UFSTAT_TXMASK, ++ .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, ++ .get_clksrc = s3c6400_serial_getsource, ++ .set_clksrc = s3c6400_serial_setsource, ++ .reset_port = s3c6400_serial_resetport, ++}; ++ ++/* device management */ ++static int s5p_serial_probe(struct platform_device *dev) ++{ ++ dbg("s5p_serial_probe: dev=%p\n", dev); ++ return s3c24xx_serial_probe(dev, &s5p_uart_inf); ++} ++ ++static struct platform_driver s5p_serial_drv = { ++ .probe = s5p_serial_probe, ++ .remove = s3c24xx_serial_remove, ++ .driver = { ++ .name = "s5pc100-uart", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++s3c24xx_console_init(&s5p_serial_drv, &s5p_uart_inf); ++ ++static int __init s5p_serial_init(void) ++{ ++ return s3c24xx_serial_init(&s5p_serial_drv, &s5p_uart_inf); ++} ++ ++static void __exit s5p_serial_exit(void) ++{ ++ platform_driver_unregister(&s5p_serial_drv); ++} ++ ++module_init(s5p_serial_init); ++module_exit(s5p_serial_exit); ++ ++MODULE_DESCRIPTION("Samsung S5PC100 SoC Serial port driver"); ++MODULE_AUTHOR("Ben Dooks "); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:s5pc100-uart"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/serial/samsung.c linux-2.6.28.6/drivers/serial/samsung.c +--- linux-2.6.28/drivers/serial/samsung.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/serial/samsung.c 2009-10-13 08:59:46.000000000 +0200 +@@ -42,13 +42,14 @@ + #include + #include + #include ++#include + + #include + + #include ++#include + + #include +-#include + + #include "samsung.h" + +@@ -58,19 +59,6 @@ + #define S3C24XX_SERIAL_MAJOR 204 + #define S3C24XX_SERIAL_MINOR 64 + +-/* we can support 3 uarts, but not always use them */ +- +-#ifdef CONFIG_CPU_S3C2400 +-#define NR_PORTS (2) +-#else +-#define NR_PORTS (3) +-#endif +- +-/* port irq numbers */ +- +-#define TX_IRQ(port) ((port)->irq + 1) +-#define RX_IRQ(port) ((port)->irq) +- + /* macros to change one thing to another */ + + #define tx_enabled(port) ((port)->unused[0]) +@@ -79,6 +67,9 @@ + /* flag to ignore all characters comming in */ + #define RXSTAT_DUMMY_READ (0x10000000) + ++const unsigned int nSlotTable[16] = {0x0000, 0x0080, 0x0808, 0x0888, 0x2222, 0x4924, 0x4a52, 0x54aa, ++ 0x5555, 0xd555, 0xd5d5, 0xddd5, 0xdddd, 0xdfdd, 0xdfdf, 0xffdf}; ++ + static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port) + { + return container_of(port, struct s3c24xx_uart_port, port); +@@ -136,8 +127,10 @@ + + static void s3c24xx_serial_stop_tx(struct uart_port *port) + { ++ struct s3c24xx_uart_port *ourport = to_ourport(port); ++ + if (tx_enabled(port)) { +- disable_irq(TX_IRQ(port)); ++ disable_irq(ourport->tx_irq); + tx_enabled(port) = 0; + if (port->flags & UPF_CONS_FLOW) + s3c24xx_serial_rx_enable(port); +@@ -146,11 +139,13 @@ + + static void s3c24xx_serial_start_tx(struct uart_port *port) + { ++ struct s3c24xx_uart_port *ourport = to_ourport(port); ++ + if (!tx_enabled(port)) { + if (port->flags & UPF_CONS_FLOW) + s3c24xx_serial_rx_disable(port); + +- enable_irq(TX_IRQ(port)); ++ enable_irq(ourport->tx_irq); + tx_enabled(port) = 1; + } + } +@@ -158,9 +153,11 @@ + + static void s3c24xx_serial_stop_rx(struct uart_port *port) + { ++ struct s3c24xx_uart_port *ourport = to_ourport(port); ++ + if (rx_enabled(port)) { + dbg("s3c24xx_serial_stop_rx: port=%p\n", port); +- disable_irq(RX_IRQ(port)); ++ disable_irq(ourport->rx_irq); + rx_enabled(port) = 0; + } + } +@@ -384,13 +381,13 @@ + struct s3c24xx_uart_port *ourport = to_ourport(port); + + if (ourport->tx_claimed) { +- free_irq(TX_IRQ(port), ourport); ++ free_irq(ourport->tx_irq, ourport); + tx_enabled(port) = 0; + ourport->tx_claimed = 0; + } + + if (ourport->rx_claimed) { +- free_irq(RX_IRQ(port), ourport); ++ free_irq(ourport->rx_irq, ourport); + ourport->rx_claimed = 0; + rx_enabled(port) = 0; + } +@@ -407,12 +404,11 @@ + + rx_enabled(port) = 1; + +- ret = request_irq(RX_IRQ(port), +- s3c24xx_serial_rx_chars, 0, ++ ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0, + s3c24xx_serial_portname(port), ourport); + + if (ret != 0) { +- printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port)); ++ printk(KERN_ERR "cannot get irq %d\n", ourport->rx_irq); + return ret; + } + +@@ -422,12 +418,11 @@ + + tx_enabled(port) = 1; + +- ret = request_irq(TX_IRQ(port), +- s3c24xx_serial_tx_chars, 0, ++ ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0, + s3c24xx_serial_portname(port), ourport); + + if (ret) { +- printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port)); ++ printk(KERN_ERR "cannot get irq %d\n", ourport->tx_irq); + goto err; + } + +@@ -452,6 +447,8 @@ + { + struct s3c24xx_uart_port *ourport = to_ourport(port); + ++ ourport->pm_level = level; ++ + switch (level) { + case 3: + if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL) +@@ -515,6 +512,9 @@ + struct s3c24xx_uart_clksrc *clksrc; + unsigned int calc; + unsigned int quot; ++#if defined(CONFIG_CPU_S5PC100) ++ unsigned int slot; ++#endif + struct clk *src; + }; + +@@ -524,6 +524,9 @@ + unsigned int baud) + { + unsigned long rate; ++#if defined(CONFIG_CPU_S5PC100) ++ unsigned long tempdiv, nslot; ++#endif + + calc->src = clk_get(port->dev, clksrc->name); + if (calc->src == NULL || IS_ERR(calc->src)) +@@ -532,6 +535,12 @@ + rate = clk_get_rate(calc->src); + rate /= clksrc->divisor; + ++#if defined(CONFIG_CPU_S5PC100) ++ tempdiv = (rate*10/(baud*16))-100; ++ nslot = (((tempdiv%100)*16)+50)/100; ++ calc->slot = nSlotTable[nslot]; ++#endif ++ + calc->clksrc = clksrc; + calc->quot = (rate + (8 * baud)) / (16 * baud); + calc->calc = (rate / (calc->quot * 16)); +@@ -540,10 +549,17 @@ + return 1; + } + ++#if defined(CONFIG_CPU_S5PC100) ++static unsigned int s3c24xx_serial_getclk(struct uart_port *port, ++ struct s3c24xx_uart_clksrc **clksrc, ++ struct clk **clk, ++ unsigned int baud, unsigned int *slot) ++#else + static unsigned int s3c24xx_serial_getclk(struct uart_port *port, + struct s3c24xx_uart_clksrc **clksrc, + struct clk **clk, + unsigned int baud) ++#endif + { + struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port); + struct s3c24xx_uart_clksrc *clkp; +@@ -609,12 +625,19 @@ + } + } + ++ if(best) { + /* store results to pass back */ + + *clksrc = best->clksrc; + *clk = best->src; ++#if defined(CONFIG_CPU_S5PC100) ++ *slot = best->slot; ++#endif + + return best->quot; ++ } else { ++ return -EINVAL; ++ } + } + + static void s3c24xx_serial_set_termios(struct uart_port *port, +@@ -629,7 +652,9 @@ + unsigned int baud, quot; + unsigned int ulcon; + unsigned int umcon; +- ++#if defined(CONFIG_CPU_S5PC100) ++ unsigned int slot = 0; ++#endif + /* + * We don't support modem control lines. + */ +@@ -640,12 +665,20 @@ + * Ask the core to calculate the divisor for us. + */ + ++#if defined(CONFIG_CPU_S5PC100) ++ baud = uart_get_baud_rate(port, termios, old, 0, 4000000); ++#else + baud = uart_get_baud_rate(port, termios, old, 0, 115200*8); ++#endif + + if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) + quot = port->custom_divisor; + else ++#if defined(CONFIG_CPU_S5PC100) ++ quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud, &slot); ++#else + quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud); ++#endif + + /* check to see if we need to change clock source */ + +@@ -661,6 +694,7 @@ + + ourport->clksrc = clksrc; + ourport->baudclk = clk; ++ ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0; + } + + switch (termios->c_cflag & CSIZE) { +@@ -706,6 +740,9 @@ + + wr_regl(port, S3C2410_ULCON, ulcon); + wr_regl(port, S3C2410_UBRDIV, quot); ++#if defined(CONFIG_CPU_S5PC100) ++ wr_regl(port, S3C_UDIVSLOT, slot); ++#endif + wr_regl(port, S3C2410_UMCON, umcon); + + dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n", +@@ -752,6 +789,8 @@ + return "S3C2440"; + case PORT_S3C2412: + return "S3C2412"; ++ case PORT_S3C6400: ++ return "S3C6400/10"; + default: + return NULL; + } +@@ -827,14 +866,14 @@ + static struct uart_driver s3c24xx_uart_drv = { + .owner = THIS_MODULE, + .dev_name = "s3c2410_serial", +- .nr = 3, ++ .nr = CONFIG_SERIAL_SAMSUNG_UARTS, + .cons = S3C24XX_SERIAL_CONSOLE, + .driver_name = S3C24XX_SERIAL_NAME, + .major = S3C24XX_SERIAL_MAJOR, + .minor = S3C24XX_SERIAL_MINOR, + }; + +-static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = { ++static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = { + [0] = { + .port = { + .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock), +@@ -859,7 +898,7 @@ + .line = 1, + } + }, +-#if NR_PORTS > 2 ++#if CONFIG_SERIAL_SAMSUNG_UARTS > 2 + + [2] = { + .port = { +@@ -872,6 +911,20 @@ + .flags = UPF_BOOT_AUTOCONF, + .line = 2, + } ++ }, ++#endif ++#if CONFIG_SERIAL_SAMSUNG_UARTS > 3 ++ [3] = { ++ .port = { ++ .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock), ++ .iotype = UPIO_MEM, ++ .irq = IRQ_S3CUART_RX3, ++ .uartclk = 0, ++ .fifosize = 16, ++ .ops = &s3c24xx_serial_ops, ++ .flags = UPF_BOOT_AUTOCONF, ++ .line = 3, ++ } + } + #endif + }; +@@ -890,6 +943,93 @@ + return (info->reset_port)(port, cfg); + } + ++ ++#ifdef CONFIG_CPU_FREQ ++ ++static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb, ++ unsigned long val, void *data) ++{ ++ struct s3c24xx_uart_port *port; ++ struct uart_port *uport; ++ ++ port = container_of(nb, struct s3c24xx_uart_port, freq_transition); ++ uport = &port->port; ++ ++ /* check to see if port is enabled */ ++ ++ if (port->pm_level != 0) ++ return 0; ++ ++ /* try and work out if the baudrate is changing, we can detect ++ * a change in rate, but we do not have support for detecting ++ * a disturbance in the clock-rate over the change. ++ */ ++ ++ if (IS_ERR(port->clk)) ++ goto exit; ++ ++ if (port->baudclk_rate == clk_get_rate(port->clk)) ++ goto exit; ++ ++ if (val == CPUFREQ_PRECHANGE) { ++ /* we should really shut the port down whilst the ++ * frequency change is in progress. */ ++ ++ } else if (val == CPUFREQ_POSTCHANGE) { ++ struct ktermios *termios; ++ struct tty_struct *tty; ++ ++ if (uport->info == NULL) { ++ printk(KERN_WARNING "%s: info NULL\n", __func__); ++ goto exit; ++ } ++ ++ tty = uport->info->port.tty; ++ ++ if (tty == NULL) { ++ printk(KERN_WARNING "%s: tty is NULL\n", __func__); ++ goto exit; ++ } ++ ++ termios = tty->termios; ++ ++ if (termios == NULL) { ++ printk(KERN_WARNING "%s: no termios?\n", __func__); ++ goto exit; ++ } ++ ++ s3c24xx_serial_set_termios(uport, termios, NULL); ++ } ++ ++ exit: ++ return 0; ++} ++ ++static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port) ++{ ++ port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition; ++ ++ return cpufreq_register_notifier(&port->freq_transition, ++ CPUFREQ_TRANSITION_NOTIFIER); ++} ++ ++static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port) ++{ ++ cpufreq_unregister_notifier(&port->freq_transition, ++ CPUFREQ_TRANSITION_NOTIFIER); ++} ++ ++#else ++static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port) ++{ ++ return 0; ++} ++ ++static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port) ++{ ++} ++#endif ++ + /* s3c24xx_serial_init_port + * + * initialise a single serial port from the platform device given +@@ -914,8 +1054,11 @@ + if (port->mapbase != 0) + return 0; + +- if (cfg->hwport > 3) +- return -EINVAL; ++ if (cfg->hwport > CONFIG_SERIAL_SAMSUNG_UARTS) { ++ printk(KERN_ERR "%s: port %d bigger than %d\n", __func__, ++ cfg->hwport, CONFIG_SERIAL_SAMSUNG_UARTS); ++ return -ERANGE; ++ } + + /* setup info for port */ + port->dev = &platdev->dev; +@@ -944,17 +1087,25 @@ + dbg("resource %p (%lx..%lx)\n", res, res->start, res->end); + + port->mapbase = res->start; +- port->membase = S3C24XX_VA_UART + (res->start - S3C24XX_PA_UART); ++ port->membase = S3C_VA_UART + res->start - (S3C_PA_UART & 0xfff00000); + ret = platform_get_irq(platdev, 0); + if (ret < 0) + port->irq = 0; +- else ++ else { + port->irq = ret; ++ ourport->rx_irq = ret; ++ ourport->tx_irq = ret + 1; ++ } ++ ++ ret = platform_get_irq(platdev, 1); ++ if (ret > 0) ++ ourport->tx_irq = ret; + + ourport->clk = clk_get(&platdev->dev, "uart"); + +- dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n", +- port->mapbase, port->membase, port->irq, port->uartclk); ++ dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n", ++ port->mapbase, port->membase, port->irq, ++ ourport->rx_irq, ourport->tx_irq, port->uartclk); + + /* reset the fifos (and setup the uart) */ + s3c24xx_serial_resetport(port, cfg); +@@ -1002,6 +1153,10 @@ + if (ret < 0) + printk(KERN_ERR "%s: failed to add clksrc attr.\n", __func__); + ++ ret = s3c24xx_serial_cpufreq_register(ourport); ++ if (ret < 0) ++ dev_err(&dev->dev, "failed to add cpufreq notifier\n"); ++ + return 0; + + probe_err: +@@ -1015,6 +1170,7 @@ + struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); + + if (port) { ++ s3c24xx_serial_cpufreq_deregister(to_ourport(port)); + device_remove_file(&dev->dev, &dev_attr_clock_source); + uart_remove_one_port(&s3c24xx_uart_drv, port); + } +@@ -1216,10 +1369,11 @@ + int i; + + dbg("s3c24xx_serial_init_ports: initialising ports...\n"); ++ printk("s3c24xx_serial_init_ports: initialising ports=%d...\n",CONFIG_SERIAL_SAMSUNG_UARTS); + + platdev_ptr = s3c24xx_uart_devs; + +- for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) { ++ for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++, ptr++, platdev_ptr++) { + s3c24xx_serial_init_port(ptr, info, *platdev_ptr); + } + +@@ -1240,7 +1394,7 @@ + + /* is this a valid port */ + +- if (co->index == -1 || co->index >= NR_PORTS) ++ if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS) + co->index = 0; + + port = &s3c24xx_serial_ports[co->index].port; +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/serial/samsung.h linux-2.6.28.6/drivers/serial/samsung.h +--- linux-2.6.28/drivers/serial/samsung.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/serial/samsung.h 2009-11-01 10:21:35.000000000 +0100 +@@ -33,12 +33,21 @@ + struct s3c24xx_uart_port { + unsigned char rx_claimed; + unsigned char tx_claimed; ++ unsigned int pm_level; ++ unsigned long baudclk_rate; ++ ++ unsigned int rx_irq; ++ unsigned int tx_irq; + + struct s3c24xx_uart_info *info; + struct s3c24xx_uart_clksrc *clksrc; + struct clk *clk; + struct clk *baudclk; + struct uart_port port; ++ ++#ifdef CONFIG_CPU_FREQ ++ struct notifier_block freq_transition; ++#endif + }; + + /* conversion functions */ +@@ -81,6 +90,8 @@ + #define s3c24xx_console_init(drv, inf) extern void no_console(void) + #endif + ++//#define CONFIG_SERIAL_SAMSUNG_DEBUG ++ + #ifdef CONFIG_SERIAL_SAMSUNG_DEBUG + + extern void printascii(const char *); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/spi/Kconfig linux-2.6.28.6/drivers/spi/Kconfig +--- linux-2.6.28/drivers/spi/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/spi/Kconfig 2009-04-30 09:36:39.000000000 +0200 +@@ -188,6 +188,69 @@ + help + SPI driver for SuperH SCI blocks. + ++config HS_SPI_S3C6410 ++ tristate "S3C6410 SPI Driver" ++ depends on SPI && CPU_S3C6410 ++ help ++ Say Y here to include support for SPI controller in the ++ Samsung S3C6410 based System-on-Chip devices. ++ ++config HS_SPI_S5P6440 ++ tristate "S5P6440 SPI Driver" ++ depends on SPI && CPU_S5P6440 ++ help ++ Say Y here to include support for SPI controller in the ++ Samsung S5P6440 based System-on-Chip devices. ++ ++config HS_SPI_S5PC100 ++ tristate "S5PC100 SPI Driver" ++ depends on SPI && CPU_S5PC100 ++ help ++ Say Y here to include support for SPI controller in the ++ Samsung S5PC100 based System-on-Chip devices. ++ ++choice ++ prompt "SPI Source Clock" ++ depends on (HS_SPI_S3C6410 || HS_SPI_S5P6440 || HS_SPI_S5PC100) ++ ++config SPICLK_SRC_PCLK ++ bool "PCLK" ++ depends on (HS_SPI_S3C6410 || HS_SPI_S5P6440 || HS_SPI_S5PC100) ++ help ++ Say Y here to include support for pclk source. ++ ++config SPICLK_SRC_USB ++ bool "USBCLK" ++ depends on HS_SPI_S3C6410 ++ help ++ Say Y here to include support for USB clock source. ++ ++config SPICLK_SRC_EPLL ++ bool "EPLL Clock" ++ depends on HS_SPI_S3C6410 ++ help ++ Say Y here to include support for EPLL source. ++ ++config SPICLK_SRC_SPIEXT ++ bool "SPI External Clock" ++ depends on HS_SPI_S5P6440 ++ help ++ Say Y here to include support for EPLL source. ++ ++config SPICLK_SRC_SCLK48M ++ bool "SCLK SPI 48M" ++ depends on HS_SPI_S5PC100 ++ help ++ Say Y here to include support for EPLL source. ++ ++config SPICLK_SRC_SCLKSPI ++ bool "SCLK SPI" ++ depends on HS_SPI_S5PC100 ++ help ++ Say Y here to include support for USB clock source. ++ ++endchoice ++ + config SPI_TXX9 + tristate "Toshiba TXx9 SPI controller" + depends on GENERIC_GPIO && CPU_TX49XX +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/spi/Makefile linux-2.6.28.6/drivers/spi/Makefile +--- linux-2.6.28/drivers/spi/Makefile 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/spi/Makefile 2009-04-30 09:36:39.000000000 +0200 +@@ -29,6 +29,9 @@ + obj-$(CONFIG_SPI_TXX9) += spi_txx9.o + obj-$(CONFIG_SPI_XILINX) += xilinx_spi.o + obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.o ++obj-$(CONFIG_HS_SPI_S3C6410) += spi_sam.o ++obj-$(CONFIG_HS_SPI_S5PC100) += spi_sam.o ++obj-$(CONFIG_HS_SPI_S5P6440) += spi_sam-6440.o + # ... add above this line ... + + # SPI protocol drivers (device/link on bus) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/spi/spi-dev.c linux-2.6.28.6/drivers/spi/spi-dev.c +--- linux-2.6.28/drivers/spi/spi-dev.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/spi/spi-dev.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,353 @@ ++/* ++* spi-dev.c - spi-bus driver, char device interface ++* ++* Copyright (C) 2006 Samsung Electronics Co. Ltd. ++* ++* This program is free software; you can redistribute it and/or modify ++* it under the terms of the GNU General Public License as published by ++* the Free Software Foundation; either version 2 of the License, or ++* (at your option) any later version. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++* You should have received a copy of the GNU General Public License ++* along with this program; if not, write to the Free Software ++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "spi-dev.h" ++#include ++ ++#undef debug ++#ifdef debug ++#define CRDEBUG printk("%s :: %d\n",__FUNCTION__,__LINE__) ++#else ++#define CRDEBUG ++#endif ++ ++static struct spi_dev *spi_dev_array[SPI_MINORS]; ++static spinlock_t (spi_dev_array_lock) = SPIN_LOCK_UNLOCKED; ++ ++static struct spi_dev *attach_to_spi_dev_array(struct spi_dev *spi_dev) ++{ ++ CRDEBUG; ++ spin_lock(&spi_dev_array_lock); ++ if (spi_dev_array[spi_dev->minor]) { ++ spin_unlock(&spi_dev_array_lock); ++ dev_err(&spi_dev->dev, "spi-dev already has a device assigned to this adapter\n"); ++ goto error; ++ } ++ spi_dev_array[spi_dev->minor] = spi_dev; ++ spin_unlock(&spi_dev_array_lock); ++ return spi_dev; ++error: ++ return ERR_PTR(-ENODEV); ++} ++ ++static void return_spi_dev(struct spi_dev *spi_dev) ++{ ++ CRDEBUG; ++ spin_lock(&spi_dev_array_lock); ++ spi_dev_array[spi_dev->minor] = NULL; ++ spin_unlock(&spi_dev_array_lock); ++} ++ ++int spi_attach_spidev(struct spi_dev *spidev) ++{ ++ struct spi_dev *spi_dev; ++ ++ CRDEBUG; ++ spi_dev = attach_to_spi_dev_array(spidev); ++ if (IS_ERR(spi_dev)) ++ return PTR_ERR(spi_dev); ++ ++ dev_dbg(&spi_dev->dev, "Registered as minor %d\n", spi_dev->minor); ++ ++ return 0; ++} ++ ++int spi_detach_spidev(struct spi_dev *spi_dev) ++{ ++ CRDEBUG; ++ return_spi_dev(spi_dev); ++ ++ dev_dbg(&spi_dev->dev, "Adapter unregistered\n"); ++ return 0; ++} ++ ++struct spi_dev *spi_dev_get_by_minor(unsigned index) ++{ ++ struct spi_dev *spi_dev; ++ ++ CRDEBUG; ++ spin_lock(&spi_dev_array_lock); ++ spi_dev = spi_dev_array[index]; ++ spin_unlock(&spi_dev_array_lock); ++ return spi_dev; ++} ++ ++int spi_master_recv(struct spi_dev *spi_dev, char *rbuf ,int count) ++{ ++ struct spi_msg msg; ++ int ret; ++ ++ CRDEBUG; ++ if (spi_dev->algo->master_xfer) { ++ msg.flags = spi_dev->flags; ++ msg.len = count; ++ msg.wbuf = NULL; ++ msg.rbuf = rbuf; ++ ++ dev_dbg(&spi_dev->dev, "master_recv: reading %d bytes.\n", ++ count); ++ ++ down(&spi_dev->bus_lock); ++ ret = spi_dev->algo->master_xfer(spi_dev, &msg, 1); ++ up(&spi_dev->bus_lock); ++ ++ dev_dbg(&spi_dev->dev, "master_recv: return:%d (count:%d)\n", ++ ret, count); ++ ++ /* if everything went ok (i.e. 1 msg transmitted), return #bytes ++ * transmitted, else error code. ++ */ ++ return (ret == 1 )? count : ret; ++ } else { ++ dev_err(&spi_dev->dev, "SPI level transfers not supported\n"); ++ return -ENOSYS; ++ } ++} ++ ++int spi_master_send(struct spi_dev *spi_dev, const char *wbuf, int count) ++{ ++ int ret; ++ struct spi_msg msg; ++ ++ CRDEBUG; ++ if (spi_dev->algo->master_xfer) { ++ msg.flags = spi_dev->flags; ++ msg.len = count; ++ msg.wbuf = (char *)wbuf; ++ msg.rbuf = NULL; ++ ++ dev_dbg(&spi_dev->dev, "master_send: writing %d bytes.\n", ++ count); ++ down(&spi_dev->bus_lock); ++ ret = spi_dev->algo->master_xfer(spi_dev, &msg, 1); ++ up(&spi_dev->bus_lock); ++ ++ /* if everything went ok (i.e. 1 msg transmitted), return #bytes ++ * transmitted, else error code. ++ */ ++ return (ret == 1 )? count : ret; ++ } else { ++ dev_err(&spi_dev->dev, "SPI level transfers not supported\n"); ++ return -ENOSYS; ++ } ++} ++ ++static ssize_t spidev_read (struct file *file, char __user *buf, size_t count, ++ loff_t *offset) ++{ ++ char *tmp; ++ int ret; ++ struct spi_dev *spi_dev = (struct spi_dev *)file->private_data; ++#ifdef CONFIG_WORD_TRANSIZE ++ count = count * 4; ++#endif ++ CRDEBUG; ++ if (count > BUFFER_SIZE) ++ count = BUFFER_SIZE; ++ ++ if (spi_dev->flags & SPI_M_DMA_MODE){ ++ tmp = dma_alloc_coherent(NULL, BUFFER_SIZE, ++ &spi_dev->dmabuf, GFP_KERNEL | GFP_DMA); ++ } else { ++ tmp = kmalloc(count,GFP_KERNEL); ++ } ++ if (tmp==NULL) ++ return -ENOMEM; ++ ++ pr_debug("%s: tmp=0x%x dmabuf=0x%x\n", ++ __FUNCTION__,*tmp,spi_dev->dmabuf); ++ pr_debug("spi-dev: spi-%d reading %zd bytes.\n", ++ iminor(file->f_dentry->d_inode), count); ++ ++ ret = spi_master_recv(spi_dev,tmp,count); ++ if (ret >= 0) ++ ret = copy_to_user(buf,tmp,count)?-EFAULT:ret; ++ if (spi_dev->flags & SPI_M_DMA_MODE){ ++ dma_free_coherent(NULL,BUFFER_SIZE,tmp,spi_dev->dmabuf); ++ } else { ++ kfree(tmp); ++ } ++ return ret; ++} ++ ++static ssize_t spidev_write (struct file *file, const char __user *buf, size_t count, ++ loff_t *offset) ++{ ++ int ret; ++ char *tmp; ++ struct spi_dev *spi_dev = (struct spi_dev *)file->private_data; ++#ifdef CONFIG_WORD_TRANSIZE ++ count = count * 4; ++#endif ++ CRDEBUG; ++ if (count > BUFFER_SIZE) ++ count = BUFFER_SIZE; ++ if (spi_dev->flags & SPI_M_DMA_MODE){ ++ tmp = dma_alloc_coherent(NULL, BUFFER_SIZE, ++ &spi_dev->dmabuf, GFP_KERNEL | GFP_DMA); ++ } else { ++ tmp = kmalloc(count,GFP_KERNEL); ++ } ++ ++ if (tmp==NULL) ++ return -ENOMEM; ++ pr_debug("%s: tmp=0x%x dmabuf=0x%x\n", ++ __FUNCTION__,*tmp,spi_dev->dmabuf); ++ ++ if (copy_from_user(tmp, buf, count)) { ++ if (spi_dev->flags & SPI_M_DMA_MODE){ ++ dma_free_coherent(NULL,BUFFER_SIZE,tmp,spi_dev->dmabuf); ++ } else { ++ kfree(tmp); ++ } ++ return -EFAULT; ++ } ++ ++ pr_debug("spi-dev: spi-%d writing %zd bytes.\n", ++ iminor(file->f_dentry->d_inode), count); ++ ++ ret = spi_master_send(spi_dev, tmp, count); ++ if (spi_dev->flags & SPI_M_DMA_MODE){ ++ dma_free_coherent(NULL,BUFFER_SIZE,tmp,spi_dev->dmabuf); ++ } else { ++ kfree(tmp); ++ } ++ return ret; ++} ++ ++int spidev_ioctl (struct inode *inode, struct file *file, unsigned int cmd, ++ unsigned long arg) ++{ ++ struct spi_dev *spi_dev = (struct spi_dev *)file->private_data; ++ ++ CRDEBUG; ++ dev_dbg(&spi_dev->dev, "spi-%d ioctl, cmd: 0x%x, arg: %lx.\n", ++ iminor(inode),cmd, arg); ++ ++ switch (cmd) { ++ case SET_SPI_FLAGS: ++ spi_dev->flags = (unsigned int) arg; ++ break; ++ case SET_SPI_RETRIES: ++ spi_dev->retries = arg; ++ break; ++ case SET_SPI_TIMEOUT: ++ spi_dev->timeout = arg; ++ break; ++ default: ++ printk("Invalid ioctl option\n"); ++ } ++ return 0; ++} ++ ++static int spidev_open(struct inode *inode, struct file *file) ++{ ++ unsigned int minor = iminor(inode); ++ struct spi_dev *spi_dev; ++ ++ CRDEBUG; ++ ++ spi_dev = spi_dev_get_by_minor(minor); ++ if (!spi_dev) ++ return -ENODEV; ++ ++ /* registered with adapter, passed as client to user */ ++ file->private_data = spi_dev; ++ ++ return 0; ++} ++ ++int spi_master_close(struct spi_dev *spi_dev) ++{ ++ int ret; ++ CRDEBUG; ++ ret = spi_dev->algo->close(spi_dev); ++ return 0; ++} ++static int spidev_release(struct inode *inode, struct file *file) ++{ ++ struct spi_dev *spi_dev = (struct spi_dev *)file->private_data; ++ int ret; ++ CRDEBUG; ++ ++ ret = spi_master_close(spi_dev); ++ file->private_data = NULL; ++ ++ return 0; ++} ++ ++static struct file_operations spidev_fops = { ++ .owner = THIS_MODULE, ++ .llseek = no_llseek, ++ .read = spidev_read, ++ .write = spidev_write, ++ .ioctl = spidev_ioctl, ++ .open = spidev_open, ++ .release = spidev_release, ++}; ++ ++static int spi_dev_init(void) ++{ ++ int res; ++ ++ printk(KERN_INFO "spi /dev entries driver\n"); ++ ++#if(SPI_CHANNEL==0) ++ res = register_chrdev(SPI_MAJOR, "spi0", &spidev_fops); ++#elif(SPI_CHANNEL==1) ++ res = register_chrdev(SPI_MAJOR, "spi1", &spidev_fops); ++#else ++ res = register_chrdev(SPI_MAJOR, "spi2", &spidev_fops); ++#endif ++ ++ if (res) ++ goto out; ++ ++ return 0; ++ ++out: ++ printk(KERN_ERR "%s: Driver Initialisation failed\n", __FILE__); ++ return res; ++} ++ ++static void spi_dev_exit(void) ++{ ++ CRDEBUG; ++ unregister_chrdev(SPI_MAJOR,"spi"); ++} ++ ++MODULE_AUTHOR("Samsung Electronics"); ++MODULE_DESCRIPTION("spi /dev entries driver"); ++MODULE_LICENSE("GPL"); ++ ++module_init(spi_dev_init); ++module_exit(spi_dev_exit); ++ ++EXPORT_SYMBOL(spi_attach_spidev); ++EXPORT_SYMBOL(spi_detach_spidev); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/spi/spi-dev.h linux-2.6.28.6/drivers/spi/spi-dev.h +--- linux-2.6.28/drivers/spi/spi-dev.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/spi/spi-dev.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,140 @@ ++/* ------------------------------------------------------------------------- */ ++/* */ ++/* spi.h - definitions for the spi-bus interface */ ++/* */ ++/* ------------------------------------------------------------------------- */ ++/* Copyright (C) 2006 Samsung Electronics Co. ltd. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 2 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, write to the Free Software ++ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ ++/* ------------------------------------------------------------------------- */ ++ ++#ifndef _LINUX_SPI_H ++#define _LINUX_SPI_H ++ ++#include ++#include ++#include /* for struct device */ ++#include ++ ++/* --- General options ------------------------------------------------ */ ++ ++struct spi_msg; ++struct spi_dev; ++struct spi_algorithm; ++ ++/* ++ * The master routines are the ones normally used to transmit data to devices ++ * on a bus (or/and read from them). Apart from these basic transfer functions ++ * to transmit one message at a time, a more complex version can be used to ++ * transmit an arbitrary number of messages without interruption. ++ */ ++extern int spi_master_send(struct spi_dev *,const char* ,int); ++extern int spi_master_recv(struct spi_dev *,char* ,int); ++ ++#define SPI_CHANNEL 0 ++#define BUFFER_SIZE 65536 ++#define SPI_MINORS 2 ++ ++/* ++ * A driver is capable of handling one or more physical devices present on ++ * SPI adapters. This information is used to inform the driver of adapter ++ * events. ++ */ ++ ++struct spi_dev { ++ int minor; ++ ++ dma_addr_t dmabuf; /* handle for DMA transfer */ ++ unsigned int flags; /* flags for the SPI operation */ ++ struct semaphore bus_lock; /* semaphore for bus access */ ++ ++ struct spi_algorithm *algo; /* the algorithm to access the bus */ ++ void *algo_data; /* the bus control struct */ ++ ++ int timeout; ++ int retries; ++ struct device dev; /* the adapter device */ ++}; ++ ++/* ++ * The following structs are for those who like to implement new bus drivers: ++ * spi_algorithm is the interface to a class of hardware solutions which can ++ * be addressed using the same bus algorithms - i.e. bit-banging or the PCF8584 ++ * to name two of the most common. ++ */ ++struct spi_algorithm { ++ char name[32]; /* textual description */ ++ unsigned int id; ++ ++ /* If an adapter algorithm can't to SPI-level access, set master_xfer ++ to NULL. If an adapter algorithm can do SMBus access, set ++ smbus_xfer. If set to NULL, the SMBus protocol is simulated ++ using common SPI messages */ ++ int (*master_xfer)(struct spi_dev *spi_dev,struct spi_msg *msgs, ++ int num); ++ ++ /* --- ioctl like call to set div. parameters. */ ++ int (*algo_control)(struct spi_dev *, unsigned int, unsigned long); ++ ++ /* To determine what the adapter supports */ ++ u32 (*functionality) (struct spi_dev *); ++ int (*close)(struct spi_dev *spi_dev); ++}; ++ ++/* ----- functions exported by spi.o */ ++ ++/* administration... ++ */ ++extern int spi_attach_spidev(struct spi_dev *); ++extern int spi_detach_spidev(struct spi_dev *); ++ ++/* ++ * SPI Message - used for pure spi transaction, also from /dev interface ++ */ ++ ++#define SPI_M_MODE_MASTER 0x001 ++#define SPI_M_MODE_SLAVE 0x002 ++#define SPI_M_USE_FIFO 0x004 ++#define SPI_M_CPOL_ACTHIGH 0x010 ++#define SPI_M_CPOL_ACTLOW 0x020 ++#define SPI_M_CPHA_FORMATA 0x040 ++#define SPI_M_CPHA_FORMATB 0x080 ++#define SPI_M_DMA_MODE 0x100 ++#define SPI_M_INT_MODE 0x200 ++#define SPI_M_POLL_MODE 0x400 ++#define SPI_M_DEBUG 0x800 ++#define SPI_M_FIFO_POLL 0x1000 ++ ++ ++struct spi_msg { ++ __u16 flags; ++ __u16 len; /* msg length */ ++ __u8 *wbuf; /* pointer to msg data to write */ ++ __u8 *rbuf; /* pointer to msg data for read */ ++}; ++ ++/* ----- commands for the ioctl call: */ ++ /* -> spi-adapter specific ioctls */ ++#define SET_SPI_RETRIES 0x0701 /* number of times a device address */ ++ /* should be polled when not */ ++ /* acknowledging */ ++#define SET_SPI_TIMEOUT 0x0702 /* set timeout - call with int */ ++#define SET_SPI_FLAGS 0x0704 /* set flags for h/w settings */ ++ ++#define SPI_MAJOR 153 /* Device major number */ ++ /* minor 0-15 spi0 - spi15 */ ++ ++#endif /* _LINUX_SPI_H */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/spi/spi_s3c24xx.c linux-2.6.28.6/drivers/spi/spi_s3c24xx.c +--- linux-2.6.28/drivers/spi/spi_s3c24xx.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/spi/spi_s3c24xx.c 2009-04-30 09:36:39.000000000 +0200 +@@ -28,7 +28,7 @@ + #include + + #include +-#include ++#include + #include + + struct s3c24xx_spi { +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/spi/spi_sam-6440.c linux-2.6.28.6/drivers/spi/spi_sam-6440.c +--- linux-2.6.28/drivers/spi/spi_sam-6440.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/spi/spi_sam-6440.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,1009 @@ ++/* ++ * spi_sam.c - Samsung SOC SPI controller driver. ++ * By -- Jaswinder Singh ++ * ++ * Copyright (C) 2009 Samsung Electronics Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "spi_sam.h" ++ ++//#define DEBUGSPI ++ ++#ifdef DEBUGSPI ++ ++#define dbg_printk(x...) printk(x) ++ ++static void dump_regs(struct samspi_bus *sspi) ++{ ++ u32 val; ++ ++ val = readl(sspi->regs + SAMSPI_CH_CFG); ++ printk("CHN-%x\t", val); ++ val = readl(sspi->regs + SAMSPI_CLK_CFG); ++ printk("CLK-%x\t", val); ++ val = readl(sspi->regs + SAMSPI_MODE_CFG); ++ printk("MOD-%x\t", val); ++ val = readl(sspi->regs + SAMSPI_SLAVE_SEL); ++ printk("SLVSEL-%x\t", val); ++ val = readl(sspi->regs + SAMSPI_SPI_STATUS); ++ if(val & SPI_STUS_TX_DONE) ++ printk("TX_done\t"); ++ if(val & SPI_STUS_TRAILCNT_ZERO) ++ printk("TrailZ\t"); ++ if(val & SPI_STUS_RX_OVERRUN_ERR) ++ printk("RX_Ovrn\t"); ++ if(val & SPI_STUS_RX_UNDERRUN_ERR) ++ printk("Rx_Unrn\t"); ++ if(val & SPI_STUS_TX_OVERRUN_ERR) ++ printk("Tx_Ovrn\t"); ++ if(val & SPI_STUS_TX_UNDERRUN_ERR) ++ printk("Tx_Unrn\t"); ++ if(val & SPI_STUS_RX_FIFORDY) ++ printk("Rx_Rdy\t"); ++ if(val & SPI_STUS_TX_FIFORDY) ++ printk("Tx_Rdy\t"); ++ printk("Rx/TxLvl=%d,%d\n", (val>>13)&0x7f, (val>>6)&0x7f); ++} ++ ++#else ++ ++#define dump_regs(sspi) do{}while(0) ++#define dbg_printk(x...) do{}while(0) ++ ++#endif ++ ++static struct s3c2410_dma_client samspi_dma_client = { ++ .name = "samspi-dma", ++}; ++ ++void samspi_dma_txcb(struct s3c2410_dma_chan *, void *, int, enum s3c2410_dma_buffresult); ++void samspi_dma_rxcb(struct s3c2410_dma_chan *, void *, int, enum s3c2410_dma_buffresult); ++ ++static int alloc_dma_chan(struct samspi_bus *sspi, struct spi_transfer *xfer) ++{ ++ int ret = 0; ++ ++ if(xfer->tx_buf != NULL){ ++ if(s3c2410_dma_request(sspi->tx_dmach, &samspi_dma_client, NULL)){ ++ dev_err(&sspi->pdev->dev, "cannot get RxDMA\n"); ++ ret = -EBUSY; ++ goto exit; ++ } ++ s3c2410_dma_set_buffdone_fn(sspi->tx_dmach, samspi_dma_txcb); ++ s3c2410_dma_devconfig(sspi->tx_dmach, S3C2410_DMASRC_MEM, 0, sspi->sfr_phyaddr + SAMSPI_SPI_TX_DATA); ++ s3c2410_dma_config(sspi->tx_dmach, sspi->cur_bpw/8, 0); ++ s3c2410_dma_setflags(sspi->tx_dmach, S3C2410_DMAF_AUTOSTART); ++ } ++ ++ if(xfer->rx_buf != NULL){ ++ if(s3c2410_dma_request(sspi->rx_dmach, &samspi_dma_client, NULL)){ ++ dev_err(&sspi->pdev->dev, "cannot get RxDMA\n"); ++ ret = -EBUSY; ++ goto exit; ++ } ++ s3c2410_dma_set_buffdone_fn(sspi->rx_dmach, samspi_dma_rxcb); ++ s3c2410_dma_devconfig(sspi->rx_dmach, S3C2410_DMASRC_HW, 0, sspi->sfr_phyaddr + SAMSPI_SPI_RX_DATA); ++ s3c2410_dma_config(sspi->rx_dmach, sspi->cur_bpw/8, 0); ++ s3c2410_dma_setflags(sspi->rx_dmach, S3C2410_DMAF_AUTOSTART); ++ } ++ ++exit: ++ return ret; ++} ++ ++static void free_dma_chan(struct samspi_bus *sspi, struct spi_transfer *xfer) ++{ ++ if(xfer->tx_buf != NULL) ++ s3c2410_dma_free(sspi->tx_dmach, &samspi_dma_client); ++ if(xfer->rx_buf != NULL) ++ s3c2410_dma_free(sspi->rx_dmach, &samspi_dma_client); ++} ++ ++static inline void enable_spidma(struct samspi_bus *sspi, struct spi_transfer *xfer) ++{ ++ u32 val; ++ ++ val = readl(sspi->regs + SAMSPI_MODE_CFG); ++ val &= ~(SPI_MODE_TXDMA_ON | SPI_MODE_RXDMA_ON); ++ if(xfer->tx_buf != NULL) ++ val |= SPI_MODE_TXDMA_ON; ++ if(xfer->rx_buf != NULL) ++ val |= SPI_MODE_RXDMA_ON; ++ writel(val, sspi->regs + SAMSPI_MODE_CFG); ++} ++ ++static inline void flush_dma(struct samspi_bus *sspi, struct spi_transfer *xfer) ++{ ++ if(xfer->tx_buf != NULL) ++ s3c2410_dma_ctrl(sspi->tx_dmach, S3C2410_DMAOP_FLUSH); ++ if(xfer->rx_buf != NULL) ++ s3c2410_dma_ctrl(sspi->rx_dmach, S3C2410_DMAOP_FLUSH); ++} ++ ++static inline void flush_spi(struct samspi_bus *sspi) ++{ ++ u32 val; ++ ++ val = readl(sspi->regs + SAMSPI_CH_CFG); ++ val |= SPI_CH_SW_RST; ++ val &= ~SPI_CH_HS_EN; ++ if((sspi->cur_speed > 30000000UL) && !(sspi->cur_mode & SPI_SLAVE)) /* TODO ??? */ ++ val |= SPI_CH_HS_EN; ++ writel(val, sspi->regs + SAMSPI_CH_CFG); ++ ++ /* Flush TxFIFO*/ ++ do{ ++ val = readl(sspi->regs + SAMSPI_SPI_STATUS); ++ val = (val>>6) & 0x7f; ++ }while(val); ++ ++ /* Flush RxFIFO*/ ++ val = readl(sspi->regs + SAMSPI_SPI_STATUS); ++ val = (val>>13) & 0x7f; ++ while(val){ ++ readl(sspi->regs + SAMSPI_SPI_RX_DATA); ++ val = readl(sspi->regs + SAMSPI_SPI_STATUS); ++ val = (val>>13) & 0x7f; ++ } ++ ++ val = readl(sspi->regs + SAMSPI_CH_CFG); ++ val &= ~SPI_CH_SW_RST; ++ writel(val, sspi->regs + SAMSPI_CH_CFG); ++} ++ ++static inline void enable_spichan(struct samspi_bus *sspi, struct spi_transfer *xfer) ++{ ++ u32 val; ++ ++ val = readl(sspi->regs + SAMSPI_CH_CFG); ++ val &= ~(SPI_CH_RXCH_ON | SPI_CH_TXCH_ON); ++ if(xfer->tx_buf != NULL){ ++ val |= SPI_CH_TXCH_ON; ++ } ++ if(xfer->rx_buf != NULL){ ++ if(!(sspi->cur_mode & SPI_SLAVE)){ ++ flush_spi(sspi); ++ writel((xfer->len & 0xffff) | SPI_PACKET_CNT_EN, ++ sspi->regs + SAMSPI_PACKET_CNT); /* XXX TODO Bytes or number of SPI-Words? */ ++ } ++ val |= SPI_CH_RXCH_ON; ++ } ++ writel(val, sspi->regs + SAMSPI_CH_CFG); ++} ++ ++static inline void enable_spiintr(struct samspi_bus *sspi, struct spi_transfer *xfer) ++{ ++ u32 val = 0; ++ ++ if(xfer->tx_buf != NULL){ ++ val |= SPI_INT_TX_OVERRUN_EN; ++ if(!(sspi->cur_mode & SPI_SLAVE)) ++ val |= SPI_INT_TX_UNDERRUN_EN; ++ } ++ if(xfer->rx_buf != NULL){ ++ val |= (SPI_INT_RX_UNDERRUN_EN | SPI_INT_RX_OVERRUN_EN | SPI_INT_TRAILING_EN); ++ } ++ writel(val, sspi->regs + SAMSPI_SPI_INT_EN); ++} ++ ++static inline void enable_spienqueue(struct samspi_bus *sspi, struct spi_transfer *xfer) ++{ ++ if(xfer->rx_buf != NULL){ ++ sspi->rx_done = BUSY; ++ s3c2410_dma_config(sspi->rx_dmach, sspi->cur_bpw/8, 0); ++ s3c2410_dma_enqueue(sspi->rx_dmach, (void *)sspi, xfer->rx_dma, xfer->len); ++ } ++ if(xfer->tx_buf != NULL){ ++ sspi->tx_done = BUSY; ++ s3c2410_dma_config(sspi->tx_dmach, sspi->cur_bpw/8, 0); ++ s3c2410_dma_enqueue(sspi->tx_dmach, (void *)sspi, xfer->tx_dma, xfer->len); ++ } ++} ++ ++static inline void enable_spics(struct samspi_bus *sspi, struct spi_transfer *xfer) ++{ ++ u32 val = 0; ++ ++ val = readl(sspi->regs + SAMSPI_SLAVE_SEL); ++ if(sspi->cur_mode & SPI_SLAVE){ ++ val |= SPI_SLAVE_AUTO; /* Auto Mode */ ++ val |= SPI_SLAVE_SIG_INACT; ++ }else{ ++ val &= ~SPI_SLAVE_AUTO; /* Manual Mode */ ++ val &= ~SPI_SLAVE_SIG_INACT; /* Activate CS */ ++ } ++ writel(val, sspi->regs + SAMSPI_SLAVE_SEL); ++} ++ ++static inline void set_polarity(struct samspi_bus *sspi) ++{ ++ u32 val; ++ ++ val = readl(sspi->regs + SAMSPI_CH_CFG); ++ val &= ~(SPI_CH_SLAVE | SPI_CPOL_L | SPI_CPHA_B); ++ if(sspi->cur_mode & SPI_SLAVE) ++ val |= SPI_CH_SLAVE; ++ if(!(sspi->cur_mode & SPI_CPOL)) ++ val |= SPI_CPOL_L; ++ if(sspi->cur_mode & SPI_CPHA) ++ val |= SPI_CPHA_B; ++ writel(val, sspi->regs + SAMSPI_CH_CFG); ++} ++ ++static inline void set_clock(struct samspi_bus *sspi) ++{ ++ u32 val; ++ ++ val = readl(sspi->regs + SAMSPI_CLK_CFG); ++ val &= ~(SPI_CLKSEL_SRCMSK | SPI_ENCLK_ENABLE | 0xff); ++ val |= 0;//SPI_CLKSEL_SRC; jassi ++ if(!(sspi->cur_mode & SPI_SLAVE)){ ++ val |= ((clk_get_rate(sspi->clk) / sspi->cur_speed / 2 - 1) << 0); // PCLK and PSR ++ val |= SPI_ENCLK_ENABLE; ++ } ++ writel(val, sspi->regs + SAMSPI_CLK_CFG); ++} ++ ++static inline void set_dmachan(struct samspi_bus *sspi) ++{ ++ u32 val; ++ ++ val = readl(sspi->regs + SAMSPI_MODE_CFG); ++ val &= ~((0x3<<17) | (0x3<<29)); ++ if(sspi->cur_bpw == 8){ ++ val |= SPI_MODE_CH_TSZ_BYTE; ++ val |= SPI_MODE_BUS_TSZ_BYTE; ++ }else if(sspi->cur_bpw == 16){ ++ val |= SPI_MODE_CH_TSZ_HALFWORD; ++ val |= SPI_MODE_BUS_TSZ_HALFWORD; ++ }else if(sspi->cur_bpw == 32){ ++ val |= SPI_MODE_CH_TSZ_WORD; ++ val |= SPI_MODE_BUS_TSZ_WORD; ++ }else{ ++ printk("Invalid Bits/Word!\n"); ++ } ++ val &= ~(SPI_MODE_4BURST | SPI_MODE_TXDMA_ON | SPI_MODE_RXDMA_ON); ++ writel(val, sspi->regs + SAMSPI_MODE_CFG); ++} ++ ++static void config_sspi(struct samspi_bus *sspi) ++{ ++ /* Set Polarity and Phase */ ++ set_polarity(sspi); ++ ++ /* Configure Clock */ ++ set_clock(sspi); ++ ++ /* Set Channel & DMA Mode */ ++ set_dmachan(sspi); ++} ++ ++static void samspi_hwinit(struct samspi_bus *sspi, int channel) ++{ ++ unsigned int val; ++ ++ writel(SPI_SLAVE_SIG_INACT, sspi->regs + SAMSPI_SLAVE_SEL); ++ ++ /* Disable Interrupts */ ++ writel(0, sspi->regs + SAMSPI_SPI_INT_EN); ++ ++#ifdef CONFIG_CPU_S3C6410 ++ writel((readl(S3C64XX_SPC_BASE) & ~(3<<28)) | (2<<28), S3C64XX_SPC_BASE); ++ writel((readl(S3C64XX_SPC_BASE) & ~(3<<18)) | (2<<18), S3C64XX_SPC_BASE); ++#elif defined (CONFIG_CPU_S5P6440) ++ writel((readl(S5P64XX_SPC_BASE) & ~(3<<28)) | (2<<28), S5P64XX_SPC_BASE); ++ writel((readl(S5P64XX_SPC_BASE) & ~(3<<18)) | (2<<18), S5P64XX_SPC_BASE); ++#elif defined (CONFIG_CPU_S5P6440) ++ /* How to control drive strength, if we must? */ ++#endif ++ ++ writel(0, sspi->regs + SAMSPI_CLK_CFG); ++ writel(0, sspi->regs + SAMSPI_MODE_CFG); ++ writel(SPI_SLAVE_SIG_INACT, sspi->regs + SAMSPI_SLAVE_SEL); ++ writel(0, sspi->regs + SAMSPI_PACKET_CNT); ++ writel(readl(sspi->regs + SAMSPI_PENDING_CLR), sspi->regs + SAMSPI_PENDING_CLR); ++ writel(SPI_FBCLK_0NS, sspi->regs + SAMSPI_FB_CLK); ++ ++ flush_spi(sspi); ++ ++ writel(0, sspi->regs + SAMSPI_SWAP_CFG); ++ writel(SPI_FBCLK_9NS, sspi->regs + SAMSPI_FB_CLK); ++ ++ val = readl(sspi->regs + SAMSPI_MODE_CFG); ++ val &= ~(SPI_MAX_TRAILCNT << SPI_TRAILCNT_OFF); ++ if(channel == 0) ++ SET_MODECFG(val, 0); ++ else ++ SET_MODECFG(val, 1); ++ val |= (SPI_TRAILCNT << SPI_TRAILCNT_OFF); ++ writel(val, sspi->regs + SAMSPI_MODE_CFG); ++ ++ config_sspi(sspi); ++} ++ ++static irqreturn_t samspi_interrupt(int irq, void *dev_id) ++{ ++ u32 val; ++ struct samspi_bus *sspi = (struct samspi_bus *)dev_id; ++ ++ dump_regs(sspi); ++ val = readl(sspi->regs + SAMSPI_PENDING_CLR); ++ printk("PENDING=%x\n", val); ++ writel(val, sspi->regs + SAMSPI_PENDING_CLR); ++ ++ /* We get interrupted only for bad news */ ++ if(sspi->tx_done != PASS){ ++ sspi->tx_done = FAIL; ++ } ++ if(sspi->rx_done != PASS){ ++ sspi->rx_done = FAIL; ++ } ++ sspi->state = STOPPED; ++ complete(&sspi->xfer_completion); ++ ++ return IRQ_HANDLED; ++} ++ ++void samspi_dma_rxcb(struct s3c2410_dma_chan *chan, void *buf_id, int size, enum s3c2410_dma_buffresult res) ++{ ++ struct samspi_bus *sspi = (struct samspi_bus *)buf_id; ++ ++ if(res == S3C2410_RES_OK){ ++ sspi->rx_done = PASS; ++ dbg_printk("DmaRx-%d ", size); ++ }else{ ++ sspi->rx_done = FAIL; ++ dbg_printk("DmaAbrtRx-%d ", size); ++ } ++ ++ if(sspi->tx_done != BUSY && sspi->state != STOPPED) /* If other done and all OK */ ++ complete(&sspi->xfer_completion); ++} ++ ++void samspi_dma_txcb(struct s3c2410_dma_chan *chan, void *buf_id, int size, enum s3c2410_dma_buffresult res) ++{ ++ struct samspi_bus *sspi = (struct samspi_bus *)buf_id; ++ ++ if(res == S3C2410_RES_OK){ ++ sspi->tx_done = PASS; ++ dbg_printk("DmaTx-%d ", size); ++ }else{ ++ sspi->tx_done = FAIL; ++ dbg_printk("DmaAbrtTx-%d ", size); ++ } ++ ++ if(sspi->rx_done != BUSY && sspi->state != STOPPED) /* If other done and all OK */ ++ complete(&sspi->xfer_completion); ++} ++ ++static int wait_for_txshiftout(struct samspi_bus *sspi, unsigned long t) ++{ ++ unsigned long timeout; ++ ++ timeout = jiffies + t; ++ while((__raw_readl(sspi->regs + SAMSPI_SPI_STATUS) >> 6) & 0x7f){ ++ if(time_after(jiffies, timeout)) ++ return -1; ++ cpu_relax(); ++ } ++ return 0; ++} ++ ++static int wait_for_xfer(struct samspi_bus *sspi, struct spi_transfer *xfer) ++{ ++ int status; ++ u32 val; ++ ++ val = msecs_to_jiffies(xfer->len / (sspi->min_speed / 8 / 1000)); /* time to xfer data at min. speed */ ++ if(sspi->cur_mode & SPI_SLAVE) ++ val += msecs_to_jiffies(5000); /* 5secs to switch on the Master */ ++ else ++ val += msecs_to_jiffies(10); /* just some more */ ++ status = wait_for_completion_interruptible_timeout(&sspi->xfer_completion, val); ++ ++ if(status == 0) ++ status = -ETIMEDOUT; ++ else if(status == -ERESTARTSYS) ++ status = -EINTR; ++ else if((sspi->tx_done != PASS) || (sspi->rx_done != PASS)) /* Some Xfer failed */ ++ status = -EIO; ++ else ++ status = 0; /* All OK */ ++ ++ /* When TxLen <= SPI-FifoLen in Slave mode, DMA returns naively */ ++ if(!status && (sspi->cur_mode & SPI_SLAVE) && (xfer->tx_buf != NULL)){ ++ val = msecs_to_jiffies(xfer->len / (sspi->min_speed / 8 / 1000)); /* Be lenient */ ++ val += msecs_to_jiffies(5000); /* 5secs to switch on the Master */ ++ status = wait_for_txshiftout(sspi, val); ++ if(status == -1) ++ status = -ETIMEDOUT; ++ else ++ status = 0; ++ } ++ ++ return status; ++} ++ ++#define INVALID_DMA_ADDRESS 0xffffffff ++/* First, try to map buf onto phys addr as such. ++ * If xfer->r/tx_buf was not on contiguous memory, ++ * allocate from our preallocated DMA buffer. ++ */ ++static int samspi_map_xfer(struct samspi_bus *sspi, struct spi_transfer *xfer) ++{ ++ struct device *dev = &sspi->pdev->dev; ++ ++ sspi->rx_tmp = NULL; ++ sspi->tx_tmp = NULL; ++ ++ xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS; ++ if(xfer->tx_buf != NULL){ ++ xfer->tx_dma = dma_map_single(dev, ++ (void *) xfer->tx_buf, xfer->len, ++ DMA_TO_DEVICE); ++ if(dma_mapping_error(dev, xfer->tx_dma)) ++ goto alloc_from_buffer; ++ } ++ if(xfer->rx_buf != NULL){ ++ xfer->rx_dma = dma_map_single(dev, ++ xfer->rx_buf, xfer->len, ++ DMA_FROM_DEVICE); ++ if(dma_mapping_error(dev, xfer->rx_dma)){ ++ if(xfer->tx_buf) ++ dma_unmap_single(dev, ++ xfer->tx_dma, xfer->len, ++ DMA_TO_DEVICE); ++ goto alloc_from_buffer; ++ } ++ } ++ return 0; ++ ++alloc_from_buffer: /* If the xfer->[r/t]x_buf was not on contiguous memory */ ++ ++ if(xfer->len <= SAMSPI_DMABUF_LEN){ ++ if(xfer->rx_buf != NULL){ ++ xfer->rx_dma = sspi->rx_dma_phys; ++ sspi->rx_tmp = (void *)sspi->rx_dma_cpu; ++ } ++ if(xfer->tx_buf != NULL){ ++ xfer->tx_dma = sspi->tx_dma_phys; ++ sspi->tx_tmp = (void *)sspi->tx_dma_cpu; ++ } ++ }else{ ++ printk("If you plan to use this Xfer size often, increase SAMSPI_DMABUF_LEN\n"); ++ if(xfer->rx_buf != NULL){ ++ sspi->rx_tmp = dma_alloc_coherent(&sspi->pdev->dev, SAMSPI_DMABUF_LEN, ++ &xfer->rx_dma, GFP_KERNEL | GFP_DMA); ++ if(sspi->rx_tmp == NULL) ++ return -ENOMEM; ++ } ++ if(xfer->tx_buf != NULL){ ++ sspi->tx_tmp = dma_alloc_coherent(&sspi->pdev->dev, ++ SAMSPI_DMABUF_LEN, &xfer->tx_dma, GFP_KERNEL | GFP_DMA); ++ if(sspi->tx_tmp == NULL){ ++ if(xfer->rx_buf != NULL) ++ dma_free_coherent(&sspi->pdev->dev, ++ SAMSPI_DMABUF_LEN, sspi->rx_tmp, xfer->rx_dma); ++ return -ENOMEM; ++ } ++ } ++ } ++ ++ if(xfer->tx_buf != NULL) ++ memcpy(sspi->tx_tmp, xfer->tx_buf, xfer->len); ++ ++ return 0; ++} ++ ++static void samspi_unmap_xfer(struct samspi_bus *sspi, struct spi_transfer *xfer) ++{ ++ if((sspi->rx_tmp == NULL) && (sspi->tx_tmp == NULL)) /* if map_single'd */ ++ return; ++ ++ if(xfer->rx_buf != NULL) ++ memcpy(xfer->rx_buf, sspi->rx_tmp, xfer->len); ++ ++ if(xfer->len > SAMSPI_DMABUF_LEN){ ++ if(xfer->rx_buf != NULL) ++ dma_free_coherent(&sspi->pdev->dev, SAMSPI_DMABUF_LEN, sspi->rx_tmp, xfer->rx_dma); ++ if(xfer->tx_buf != NULL) ++ dma_free_coherent(&sspi->pdev->dev, SAMSPI_DMABUF_LEN, sspi->tx_tmp, xfer->tx_dma); ++ }else{ ++ sspi->rx_tmp = NULL; ++ sspi->tx_tmp = NULL; ++ } ++} ++ ++static void handle_msg(struct samspi_bus *sspi, struct spi_message *msg) ++{ ++ u8 bpw; ++ u32 speed, val; ++ int status = 0; ++ struct spi_transfer *xfer; ++ struct spi_device *spi = msg->spi; ++ ++ config_sspi(sspi); ++ ++ dump_regs(sspi); ++ list_for_each_entry (xfer, &msg->transfers, transfer_list) { ++ ++ if(!msg->is_dma_mapped && samspi_map_xfer(sspi, xfer)){ ++ dev_err(&spi->dev, "Xfer: Unable to allocate DMA buffer!\n"); ++ status = -ENOMEM; ++ goto out; ++ } ++ ++ if(alloc_dma_chan(sspi, xfer)){ ++ dev_err(&spi->dev, "Xfer: DMA Alloc Failed!\n"); ++ status = -EBUSY; ++ goto out; ++ } ++ ++ INIT_COMPLETION(sspi->xfer_completion); ++ ++ /* Only BPW and Speed may change across transfers */ ++ bpw = xfer->bits_per_word ? : spi->bits_per_word; ++ speed = xfer->speed_hz ? : spi->max_speed_hz; ++ ++ if(sspi->cur_bpw != bpw || sspi->cur_speed != speed){ ++ sspi->cur_bpw = bpw; ++ sspi->cur_speed = speed; ++ config_sspi(sspi); ++ } ++ ++ /* Pending only which is to be done */ ++ sspi->rx_done = PASS; ++ sspi->tx_done = PASS; ++ sspi->state = RUNNING; ++ ++ /* Enable Interrupts */ ++ enable_spiintr(sspi, xfer); ++ ++ /* Enqueue data on DMA */ ++ enable_spienqueue(sspi, xfer); ++ ++ /* Enable DMA */ ++ enable_spidma(sspi, xfer); ++ ++ /* Enable TX/RX */ ++ enable_spichan(sspi, xfer); ++ ++ /* Slave Select */ ++ enable_spics(sspi, xfer); ++ ++ dump_regs(sspi); ++ status = wait_for_xfer(sspi, xfer); ++ ++ free_dma_chan(sspi, xfer); ++ /************** ++ * Block Here * ++ **************/ ++ ++ if(status == -ETIMEDOUT){ ++ dev_err(&spi->dev, "Xfer: Timeout!\n"); ++ dump_regs(sspi); ++ sspi->state = STOPPED; ++ /* DMA Disable*/ ++ val = readl(sspi->regs + SAMSPI_MODE_CFG); ++ val &= ~(SPI_MODE_TXDMA_ON | SPI_MODE_RXDMA_ON); ++ writel(val, sspi->regs + SAMSPI_MODE_CFG); ++ flush_dma(sspi, xfer); ++ flush_spi(sspi); ++ if(!msg->is_dma_mapped) ++ samspi_unmap_xfer(sspi, xfer); ++ goto out; ++ } ++ if(status == -EINTR){ ++ dev_err(&spi->dev, "Xfer: Interrupted!\n"); ++ dump_regs(sspi); ++ sspi->state = STOPPED; ++ /* DMA Disable*/ ++ val = readl(sspi->regs + SAMSPI_MODE_CFG); ++ val &= ~(SPI_MODE_TXDMA_ON | SPI_MODE_RXDMA_ON); ++ writel(val, sspi->regs + SAMSPI_MODE_CFG); ++ flush_dma(sspi, xfer); ++ flush_spi(sspi); ++ if(!msg->is_dma_mapped) ++ samspi_unmap_xfer(sspi, xfer); ++ goto out; ++ } ++ if(status == -EIO){ /* Some Xfer failed */ ++ dev_err(&spi->dev, "Xfer: Failed!\n"); ++ dump_regs(sspi); ++ sspi->state = STOPPED; ++ /* DMA Disable*/ ++ val = readl(sspi->regs + SAMSPI_MODE_CFG); ++ val &= ~(SPI_MODE_TXDMA_ON | SPI_MODE_RXDMA_ON); ++ writel(val, sspi->regs + SAMSPI_MODE_CFG); ++ flush_dma(sspi, xfer); ++ flush_spi(sspi); ++ if(!msg->is_dma_mapped) ++ samspi_unmap_xfer(sspi, xfer); ++ goto out; ++ } ++ ++ if(xfer->delay_usecs){ ++ udelay(xfer->delay_usecs); ++ dbg_printk("xfer-delay=%u\n", xfer->delay_usecs); ++ } ++ if(xfer->cs_change && !(sspi->cur_mode & SPI_SLAVE)){ ++ writel(readl(sspi->regs + SAMSPI_SLAVE_SEL) | SPI_SLAVE_SIG_INACT, ++ sspi->regs + SAMSPI_SLAVE_SEL); ++ dbg_printk("xfer-cs_chng=%u\n", xfer->cs_change); ++ } ++ ++ msg->actual_length += xfer->len; ++ ++ if(!msg->is_dma_mapped) ++ samspi_unmap_xfer(sspi, xfer); ++ } ++ ++out: ++ /* Slave Deselect */ ++ val = readl(sspi->regs + SAMSPI_SLAVE_SEL); ++ val &= ~SPI_SLAVE_AUTO; ++ val |= SPI_SLAVE_SIG_INACT; ++ writel(val, sspi->regs + SAMSPI_SLAVE_SEL); ++ ++ /* Disable Interrupts */ ++ writel(0, sspi->regs + SAMSPI_SPI_INT_EN); ++ ++ /* Tx/Rx Disable */ ++ val = readl(sspi->regs + SAMSPI_CH_CFG); ++ val &= ~(SPI_CH_RXCH_ON | SPI_CH_TXCH_ON); ++ writel(val, sspi->regs + SAMSPI_CH_CFG); ++ ++ /* DMA Disable*/ ++ val = readl(sspi->regs + SAMSPI_MODE_CFG); ++ val &= ~(SPI_MODE_TXDMA_ON | SPI_MODE_RXDMA_ON); ++ writel(val, sspi->regs + SAMSPI_MODE_CFG); ++ ++ msg->status = status; ++ if(msg->complete) ++ msg->complete(msg->context); ++} ++ ++static void samspi_work(struct work_struct *work) ++{ ++ struct samspi_bus *sspi = container_of(work, struct samspi_bus, work); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&sspi->lock, flags); ++ while (!list_empty(&sspi->queue)) { ++ struct spi_message *msg; ++ ++ msg = container_of(sspi->queue.next, struct spi_message, queue); ++ list_del_init(&msg->queue); ++ spin_unlock_irqrestore(&sspi->lock, flags); ++ ++ handle_msg(sspi, msg); ++ ++ spin_lock_irqsave(&sspi->lock, flags); ++ } ++ spin_unlock_irqrestore(&sspi->lock, flags); ++} ++ ++static void samspi_cleanup(struct spi_device *spi) ++{ ++ dbg_printk("%s:%s:%d\n", __FILE__, __func__, __LINE__); ++} ++ ++static int samspi_transfer(struct spi_device *spi, struct spi_message *msg) ++{ ++ struct spi_master *master = spi->master; ++ struct samspi_bus *sspi = spi_master_get_devdata(master); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&sspi->lock, flags); ++ msg->actual_length = 0; ++ list_add_tail(&msg->queue, &sspi->queue); ++ queue_work(sspi->workqueue, &sspi->work); ++ spin_unlock_irqrestore(&sspi->lock, flags); ++ ++ return 0; ++} ++ ++/* the spi->mode bits understood by this driver: */ ++#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_SLAVE) ++ ++/* ++ * Here we only check the validity of requested configuration and ++ * save the configuration in a local data-structure. ++ * The controller is actually configured only just before ++ * we get a message to transfer _and_ if no other message is pending(already configured). ++ */ ++static int samspi_setup(struct spi_device *spi) ++{ ++ unsigned long flags; ++ unsigned int psr; ++ struct samspi_bus *sspi = spi_master_get_devdata(spi->master); ++ ++ spin_lock_irqsave(&sspi->lock, flags); ++ if(!list_empty(&sspi->queue)){ /* Any pending message? */ ++ spin_unlock_irqrestore(&sspi->lock, flags); ++ dev_dbg(&spi->dev, "setup: attempt while messages in queue!\n"); ++ return -EBUSY; ++ } ++ spin_unlock_irqrestore(&sspi->lock, flags); ++ ++ if (spi->chip_select > spi->master->num_chipselect) { ++ dev_dbg(&spi->dev, "setup: invalid chipselect %u (%u defined)\n", ++ spi->chip_select, spi->master->num_chipselect); ++ return -EINVAL; ++ } ++ ++ spi->bits_per_word = spi->bits_per_word ? : 8; ++ ++ if((spi->bits_per_word != 8) && ++ (spi->bits_per_word != 16) && ++ (spi->bits_per_word != 32)){ ++ dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n", spi->bits_per_word); ++ return -EINVAL; ++ } ++ ++ spi->max_speed_hz = spi->max_speed_hz ? : sspi->max_speed; ++ ++ /* Round-off max_speed_hz */ ++ psr = clk_get_rate(sspi->clk) / spi->max_speed_hz / 2 - 1; ++ psr &= 0xff; ++ if(spi->max_speed_hz < clk_get_rate(sspi->clk) / 2 / (psr + 1)) ++ psr = (psr+1) & 0xff; ++ ++ spi->max_speed_hz = clk_get_rate(sspi->clk) / 2 / (psr + 1); ++ ++ if (spi->max_speed_hz > sspi->max_speed ++ || spi->max_speed_hz < sspi->min_speed){ ++ dev_err(&spi->dev, "setup: req speed(%u) out of range[%u-%u]\n", ++ spi->max_speed_hz, sspi->min_speed, sspi->max_speed); ++ return -EINVAL; ++ } ++ ++ if (spi->mode & ~MODEBITS) { ++ dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", spi->mode & ~MODEBITS); ++ return -EINVAL; ++ } ++ ++ dbg_printk("@%s spi-%p sspi-%p\n", __func__, spi, sspi); ++ dbg_printk("Asked to setup mode:-"); ++ dbg_printk("max_speed_hz = %d\n", spi->max_speed_hz); ++ dbg_printk("chip_select = %d\n", spi->chip_select); ++ dbg_printk("bits_per_word = %d\n", spi->bits_per_word); ++ dbg_printk("irq = %d\n", spi->irq); ++ dbg_printk("Clk Phs = %d\n", spi->mode & SPI_CPHA); ++ dbg_printk("Clk Pol = %d\n", spi->mode & SPI_CPOL); ++ dbg_printk("ChipSelct = %s\n", (spi->mode & (1<<2)) ? "high" : "low" ); ++ dbg_printk("Mode = %s\n", (spi->mode & SPI_SLAVE) ? "Slave" : "Master"); ++ ++ if((sspi->cur_bpw == spi->bits_per_word) && ++ (sspi->cur_speed == spi->max_speed_hz) && ++ (sspi->cur_mode == spi->mode)) /* If no change in configuration, do nothing */ ++ return 0; ++ ++ sspi->cur_bpw = spi->bits_per_word; ++ sspi->cur_speed = spi->max_speed_hz; ++ sspi->cur_mode = spi->mode; ++ ++ return 0; ++} ++ ++static int __init samspi_probe(struct platform_device *pdev) ++{ ++ struct spi_master *master; ++ struct samspi_bus *sspi; ++ int ret = -ENODEV; ++ ++ dbg_printk("%s:%s:%d ID=%d\n", __FILE__, __func__, __LINE__, pdev->id); ++ master = spi_alloc_master(&pdev->dev, sizeof(struct samspi_bus)); /* Allocate contiguous SPI controller */ ++ if (master == NULL) ++ return ret; ++ sspi = spi_master_get_devdata(master); ++ sspi->pdev = pdev; ++ sspi->master = master; ++ platform_set_drvdata(pdev, master); ++ ++ INIT_WORK(&sspi->work, samspi_work); ++ spin_lock_init(&sspi->lock); ++ INIT_LIST_HEAD(&sspi->queue); ++ init_completion(&sspi->xfer_completion); ++ ++ sspi->clk = clk_get(&pdev->dev, "spi"); ++ if (IS_ERR(sspi->clk)) { ++ sspi->clk = NULL; ++ dev_err(&pdev->dev, "cannot acquire clock \n"); ++ ret = -EBUSY; ++ goto lb1; ++ } ++ ret = clk_enable(sspi->clk); ++ if (ret) { ++ clk_put(sspi->clk); ++ sspi->clk = NULL; ++ dev_err(&pdev->dev, "cannot enable clock \n"); ++ ret = -EBUSY; ++ goto lb2; ++ } ++ ++ sspi->cur_mode = SPI_SLAVE; /* Start in Slave mode */ ++ sspi->cur_bpw = 8; ++ sspi->max_speed = clk_get_rate(sspi->clk) / 2 / (0x0 + 1); ++ sspi->min_speed = clk_get_rate(sspi->clk) / 2 / (0xff + 1); ++ ++ /* Get and Map Resources */ ++ sspi->iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (sspi->iores == NULL) { ++ dev_err(&pdev->dev, "cannot find IO resource\n"); ++ ret = -ENOENT; ++ goto lb3; ++ } ++ ++ sspi->ioarea = request_mem_region(sspi->iores->start, sspi->iores->end - sspi->iores->start + 1, pdev->name); ++ if (sspi->ioarea == NULL) { ++ dev_err(&pdev->dev, "cannot request IO\n"); ++ ret = -ENXIO; ++ goto lb4; ++ } ++ ++ sspi->regs = ioremap(sspi->iores->start, sspi->iores->end - sspi->iores->start + 1); ++ if (sspi->regs == NULL) { ++ dev_err(&pdev->dev, "cannot map IO\n"); ++ ret = -ENXIO; ++ goto lb5; ++ } ++ ++ sspi->tx_dma_cpu = dma_alloc_coherent(&pdev->dev, SAMSPI_DMABUF_LEN, &sspi->tx_dma_phys, GFP_KERNEL | GFP_DMA); ++ if(sspi->tx_dma_cpu == NULL){ ++ dev_err(&pdev->dev, "Unable to allocate TX DMA buffers\n"); ++ ret = -ENOMEM; ++ goto lb6; ++ } ++ ++ sspi->rx_dma_cpu = dma_alloc_coherent(&pdev->dev, SAMSPI_DMABUF_LEN, &sspi->rx_dma_phys, GFP_KERNEL | GFP_DMA); ++ if(sspi->rx_dma_cpu == NULL){ ++ dev_err(&pdev->dev, "Unable to allocate RX DMA buffers\n"); ++ ret = -ENOMEM; ++ goto lb7; ++ } ++ ++ sspi->irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if(sspi->irqres == NULL){ ++ dev_err(&pdev->dev, "cannot find IRQ\n"); ++ ret = -ENOENT; ++ goto lb8; ++ } ++ ++ ret = request_irq(sspi->irqres->start, samspi_interrupt, IRQF_DISABLED, ++ pdev->name, sspi); ++ if(ret){ ++ dev_err(&pdev->dev, "cannot acquire IRQ\n"); ++ ret = -EBUSY; ++ goto lb9; ++ } ++ ++ sspi->workqueue = create_singlethread_workqueue(master->dev.parent->bus_id); ++ if(!sspi->workqueue){ ++ dev_err(&pdev->dev, "cannot create workqueue\n"); ++ ret = -EBUSY; ++ goto lb10; ++ } ++ ++ master->bus_num = pdev->id; ++ master->setup = samspi_setup; ++ master->transfer = samspi_transfer; ++ master->cleanup = samspi_cleanup; ++ master->num_chipselect = 1; /* Only 1 Slave connected on SMDK */ ++ ++ if(spi_register_master(master)){ ++ dev_err(&pdev->dev, "cannot register SPI master\n"); ++ ret = -EBUSY; ++ goto lb11; ++ } ++ ++ /* Configure GPIOs */ ++ if(pdev->id == 0) ++ SETUP_SPI(sspi, 0); ++ else if(pdev->id == 1) ++ SETUP_SPI(sspi, 1); ++ ++ /* Setup Deufult Mode */ ++ samspi_hwinit(sspi, pdev->id); ++ ++ printk("Samsung SoC SPI Driver loaded for SPI-%d\n", pdev->id); ++ printk("\tMax,Min-Speed [%d, %d]Hz\n", sspi->max_speed, sspi->min_speed); ++ printk("\tIrq=%d\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n", ++ sspi->irqres->start, ++ sspi->iores->end, sspi->iores->start, ++ sspi->rx_dmach, sspi->tx_dmach); ++ return 0; ++ ++lb12: ++ spi_unregister_master(master); ++lb11: ++ destroy_workqueue(sspi->workqueue); ++lb10: ++ free_irq(sspi->irqres->start, sspi); ++lb9: ++lb8: ++ dma_free_coherent(&pdev->dev, SAMSPI_DMABUF_LEN, sspi->rx_dma_cpu, sspi->rx_dma_phys); ++lb7: ++ dma_free_coherent(&pdev->dev, SAMSPI_DMABUF_LEN, sspi->tx_dma_cpu, sspi->tx_dma_phys); ++lb6: ++ iounmap((void *) sspi->regs); ++lb5: ++ release_mem_region(sspi->iores->start, sspi->iores->end - sspi->iores->start + 1); ++lb4: ++lb3: ++ clk_disable(sspi->clk); ++lb2: ++ clk_put(sspi->clk); ++lb1: ++ platform_set_drvdata(pdev, NULL); ++ spi_master_put(master); ++ ++ return ret; ++} ++ ++static int __exit samspi_remove(struct platform_device *pdev) ++{ ++ struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); ++ struct samspi_bus *sspi = spi_master_get_devdata(master); ++ ++ spi_unregister_master(master); ++ destroy_workqueue(sspi->workqueue); ++ free_irq(sspi->irqres->start, sspi); ++ dma_free_coherent(&pdev->dev, SAMSPI_DMABUF_LEN, sspi->rx_dma_cpu, sspi->rx_dma_phys); ++ dma_free_coherent(&pdev->dev, SAMSPI_DMABUF_LEN, sspi->tx_dma_cpu, sspi->tx_dma_phys); ++ iounmap((void *) sspi->regs); ++ release_mem_region(sspi->iores->start, sspi->iores->end - sspi->iores->start + 1); ++ clk_disable(sspi->clk); ++ clk_put(sspi->clk); ++ platform_set_drvdata(pdev, NULL); ++ spi_master_put(master); ++ ++ return 0; ++} ++ ++static struct platform_driver sam_spi_driver = { ++ .driver = { ++ .name = "sam-spi", ++ .owner = THIS_MODULE, ++ .bus = &platform_bus_type, ++ }, ++// .remove = sam_spi_remove, ++// .shutdown = sam_spi_shutdown, ++// .suspend = sam_spi_suspend, ++// .resume = sam_spi_resume, ++}; ++ ++static int __init sam_spi_init(void) ++{ ++ dbg_printk("%s:%s:%d\n", __FILE__, __func__, __LINE__); ++ return platform_driver_probe(&sam_spi_driver, samspi_probe); ++} ++module_init(sam_spi_init); ++ ++static void __exit sam_spi_exit(void) ++{ ++ platform_driver_unregister(&sam_spi_driver); ++} ++module_exit(sam_spi_exit); ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Jaswinder Singh Brar "); ++MODULE_DESCRIPTION("Samsung SOC SPI Controller"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/spi/spi_sam.c linux-2.6.28.6/drivers/spi/spi_sam.c +--- linux-2.6.28/drivers/spi/spi_sam.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/spi/spi_sam.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,983 @@ ++/* ++ * spi_sam.c - Samsung SOC SPI controller driver. ++ * By -- Jaswinder Singh ++ * ++ * Copyright (C) 2009 Samsung Electronics Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "spi_sam.h" ++ ++//#define DEBUGSPI ++ ++#ifdef DEBUGSPI ++ ++#define dbg_printk(x...) printk(x) ++ ++static void dump_regs(struct samspi_bus *sspi) ++{ ++ u32 val; ++ ++ val = readl(sspi->regs + SAMSPI_CH_CFG); ++ printk("CHN-%x\t", val); ++ val = readl(sspi->regs + SAMSPI_CLK_CFG); ++ printk("CLK-%x\t", val); ++ val = readl(sspi->regs + SAMSPI_MODE_CFG); ++ printk("MOD-%x\t", val); ++ val = readl(sspi->regs + SAMSPI_SLAVE_SEL); ++ printk("SLVSEL-%x\t", val); ++ val = readl(sspi->regs + SAMSPI_SPI_STATUS); ++ if(val & SPI_STUS_TX_DONE) ++ printk("TX_done\t"); ++ if(val & SPI_STUS_TRAILCNT_ZERO) ++ printk("TrailZ\t"); ++ if(val & SPI_STUS_RX_OVERRUN_ERR) ++ printk("RX_Ovrn\t"); ++ if(val & SPI_STUS_RX_UNDERRUN_ERR) ++ printk("Rx_Unrn\t"); ++ if(val & SPI_STUS_TX_OVERRUN_ERR) ++ printk("Tx_Ovrn\t"); ++ if(val & SPI_STUS_TX_UNDERRUN_ERR) ++ printk("Tx_Unrn\t"); ++ if(val & SPI_STUS_RX_FIFORDY) ++ printk("Rx_Rdy\t"); ++ if(val & SPI_STUS_TX_FIFORDY) ++ printk("Tx_Rdy\t"); ++ printk("Rx/TxLvl=%d,%d\n", (val>>13)&0x7f, (val>>6)&0x7f); ++} ++ ++#else ++ ++#define dump_regs(sspi) do{}while(0) ++#define dbg_printk(x...) do{}while(0) ++ ++#endif ++ ++static struct s3c2410_dma_client samspi_dma_client = { ++ .name = "samspi-dma", ++}; ++ ++static inline void enable_spidma(struct samspi_bus *sspi, struct spi_transfer *xfer) ++{ ++ u32 val; ++ ++ val = readl(sspi->regs + SAMSPI_MODE_CFG); ++ val &= ~(SPI_MODE_TXDMA_ON | SPI_MODE_RXDMA_ON); ++ if(xfer->tx_buf != NULL) ++ val |= SPI_MODE_TXDMA_ON; ++ if(xfer->rx_buf != NULL) ++ val |= SPI_MODE_RXDMA_ON; ++ writel(val, sspi->regs + SAMSPI_MODE_CFG); ++} ++ ++static inline void flush_dma(struct samspi_bus *sspi, struct spi_transfer *xfer) ++{ ++ if(xfer->tx_buf != NULL) ++ s3c2410_dma_ctrl(sspi->tx_dmach, S3C2410_DMAOP_FLUSH); ++ if(xfer->rx_buf != NULL) ++ s3c2410_dma_ctrl(sspi->rx_dmach, S3C2410_DMAOP_FLUSH); ++} ++ ++static inline void flush_spi(struct samspi_bus *sspi) ++{ ++ u32 val; ++ ++ val = readl(sspi->regs + SAMSPI_CH_CFG); ++ val |= SPI_CH_SW_RST; ++ val &= ~SPI_CH_HS_EN; ++ if((sspi->cur_speed > 30000000UL) && !(sspi->cur_mode & SPI_SLAVE)) /* TODO ??? */ ++ val |= SPI_CH_HS_EN; ++ writel(val, sspi->regs + SAMSPI_CH_CFG); ++ ++ /* Flush TxFIFO*/ ++ do{ ++ val = readl(sspi->regs + SAMSPI_SPI_STATUS); ++ val = (val>>6) & 0x7f; ++ }while(val); ++ ++ /* Flush RxFIFO*/ ++ val = readl(sspi->regs + SAMSPI_SPI_STATUS); ++ val = (val>>13) & 0x7f; ++ while(val){ ++ readl(sspi->regs + SAMSPI_SPI_RX_DATA); ++ val = readl(sspi->regs + SAMSPI_SPI_STATUS); ++ val = (val>>13) & 0x7f; ++ } ++ ++ val = readl(sspi->regs + SAMSPI_CH_CFG); ++ val &= ~SPI_CH_SW_RST; ++ writel(val, sspi->regs + SAMSPI_CH_CFG); ++} ++ ++static inline void enable_spichan(struct samspi_bus *sspi, struct spi_transfer *xfer) ++{ ++ u32 val; ++ ++ val = readl(sspi->regs + SAMSPI_CH_CFG); ++ val &= ~(SPI_CH_RXCH_ON | SPI_CH_TXCH_ON); ++ if(xfer->tx_buf != NULL){ ++ val |= SPI_CH_TXCH_ON; ++ } ++ if(xfer->rx_buf != NULL){ ++ if(!(sspi->cur_mode & SPI_SLAVE)){ ++ flush_spi(sspi); ++ writel((xfer->len & 0xffff) | SPI_PACKET_CNT_EN, ++ sspi->regs + SAMSPI_PACKET_CNT); /* XXX TODO Bytes or number of SPI-Words? */ ++ } ++ val |= SPI_CH_RXCH_ON; ++ } ++ writel(val, sspi->regs + SAMSPI_CH_CFG); ++} ++ ++static inline void enable_spiintr(struct samspi_bus *sspi, struct spi_transfer *xfer) ++{ ++ u32 val = 0; ++ ++ if(xfer->tx_buf != NULL){ ++ val |= SPI_INT_TX_OVERRUN_EN; ++ if(!(sspi->cur_mode & SPI_SLAVE)) ++ val |= SPI_INT_TX_UNDERRUN_EN; ++ } ++ if(xfer->rx_buf != NULL){ ++ val |= (SPI_INT_RX_UNDERRUN_EN | SPI_INT_RX_OVERRUN_EN | SPI_INT_TRAILING_EN); ++ } ++ writel(val, sspi->regs + SAMSPI_SPI_INT_EN); ++} ++ ++static inline void enable_spienqueue(struct samspi_bus *sspi, struct spi_transfer *xfer) ++{ ++ if(xfer->rx_buf != NULL){ ++ sspi->rx_done = BUSY; ++ s3c2410_dma_config(sspi->rx_dmach, sspi->cur_bpw/8, 0); ++ s3c2410_dma_enqueue(sspi->rx_dmach, (void *)sspi, xfer->rx_dma, xfer->len); ++ } ++ if(xfer->tx_buf != NULL){ ++ sspi->tx_done = BUSY; ++ s3c2410_dma_config(sspi->tx_dmach, sspi->cur_bpw/8, 0); ++ s3c2410_dma_enqueue(sspi->tx_dmach, (void *)sspi, xfer->tx_dma, xfer->len); ++ } ++} ++ ++static inline void enable_spics(struct samspi_bus *sspi, struct spi_transfer *xfer) ++{ ++ u32 val = 0; ++ ++ val = readl(sspi->regs + SAMSPI_SLAVE_SEL); ++ if(sspi->cur_mode & SPI_SLAVE){ ++ val |= SPI_SLAVE_AUTO; /* Auto Mode */ ++ val |= SPI_SLAVE_SIG_INACT; ++ }else{ ++ val &= ~SPI_SLAVE_AUTO; /* Manual Mode */ ++ val &= ~SPI_SLAVE_SIG_INACT; /* Activate CS */ ++ } ++ writel(val, sspi->regs + SAMSPI_SLAVE_SEL); ++} ++ ++static inline void set_polarity(struct samspi_bus *sspi) ++{ ++ u32 val; ++ ++ val = readl(sspi->regs + SAMSPI_CH_CFG); ++ val &= ~(SPI_CH_SLAVE | SPI_CPOL_L | SPI_CPHA_B); ++ if(sspi->cur_mode & SPI_SLAVE) ++ val |= SPI_CH_SLAVE; ++ if(!(sspi->cur_mode & SPI_CPOL)) ++ val |= SPI_CPOL_L; ++ if(sspi->cur_mode & SPI_CPHA) ++ val |= SPI_CPHA_B; ++ writel(val, sspi->regs + SAMSPI_CH_CFG); ++} ++ ++static inline void set_clock(struct samspi_bus *sspi) ++{ ++ u32 val; ++ ++ val = readl(sspi->regs + SAMSPI_CLK_CFG); ++ val &= ~(SPI_CLKSEL_SRCMSK | SPI_ENCLK_ENABLE | 0xff); ++ val |= 0;//SPI_CLKSEL_SRC; jassi ++ if(!(sspi->cur_mode & SPI_SLAVE)){ ++ val |= ((clk_get_rate(sspi->clk) / sspi->cur_speed / 2 - 1) << 0); // PCLK and PSR ++ val |= SPI_ENCLK_ENABLE; ++ } ++ writel(val, sspi->regs + SAMSPI_CLK_CFG); ++} ++ ++static inline void set_dmachan(struct samspi_bus *sspi) ++{ ++ u32 val; ++ ++ val = readl(sspi->regs + SAMSPI_MODE_CFG); ++ val &= ~((0x3<<17) | (0x3<<29)); ++ if(sspi->cur_bpw == 8){ ++ val |= SPI_MODE_CH_TSZ_BYTE; ++ val |= SPI_MODE_BUS_TSZ_BYTE; ++ }else if(sspi->cur_bpw == 16){ ++ val |= SPI_MODE_CH_TSZ_HALFWORD; ++ val |= SPI_MODE_BUS_TSZ_HALFWORD; ++ }else if(sspi->cur_bpw == 32){ ++ val |= SPI_MODE_CH_TSZ_WORD; ++ val |= SPI_MODE_BUS_TSZ_WORD; ++ }else{ ++ printk("Invalid Bits/Word!\n"); ++ } ++ val &= ~(SPI_MODE_4BURST | SPI_MODE_TXDMA_ON | SPI_MODE_RXDMA_ON); ++ writel(val, sspi->regs + SAMSPI_MODE_CFG); ++} ++ ++static void config_sspi(struct samspi_bus *sspi) ++{ ++ /* Set Polarity and Phase */ ++ set_polarity(sspi); ++ ++ /* Configure Clock */ ++ set_clock(sspi); ++ ++ /* Set Channel & DMA Mode */ ++ set_dmachan(sspi); ++} ++ ++static void samspi_hwinit(struct samspi_bus *sspi, int channel) ++{ ++ unsigned int val; ++ ++ writel(SPI_SLAVE_SIG_INACT, sspi->regs + SAMSPI_SLAVE_SEL); ++ ++ /* Disable Interrupts */ ++ writel(0, sspi->regs + SAMSPI_SPI_INT_EN); ++ ++#ifdef CONFIG_CPU_S3C6410 ++ writel((readl(S3C64XX_SPC_BASE) & ~(3<<28)) | (2<<28), S3C64XX_SPC_BASE); ++ writel((readl(S3C64XX_SPC_BASE) & ~(3<<18)) | (2<<18), S3C64XX_SPC_BASE); ++#elif defined (CONFIG_CPU_S5P6440) ++ writel((readl(S5P64XX_SPC_BASE) & ~(3<<28)) | (2<<28), S5P64XX_SPC_BASE); ++ writel((readl(S5P64XX_SPC_BASE) & ~(3<<18)) | (2<<18), S5P64XX_SPC_BASE); ++#elif defined (CONFIG_CPU_S5P6440) ++ /* How to control drive strength, if we must? */ ++#endif ++ ++ writel(0, sspi->regs + SAMSPI_CLK_CFG); ++ writel(0, sspi->regs + SAMSPI_MODE_CFG); ++ writel(SPI_SLAVE_SIG_INACT, sspi->regs + SAMSPI_SLAVE_SEL); ++ writel(0, sspi->regs + SAMSPI_PACKET_CNT); ++ writel(readl(sspi->regs + SAMSPI_PENDING_CLR), sspi->regs + SAMSPI_PENDING_CLR); ++ writel(SPI_FBCLK_0NS, sspi->regs + SAMSPI_FB_CLK); ++ ++ flush_spi(sspi); ++ ++ writel(0, sspi->regs + SAMSPI_SWAP_CFG); ++ writel(SPI_FBCLK_9NS, sspi->regs + SAMSPI_FB_CLK); ++ ++ val = readl(sspi->regs + SAMSPI_MODE_CFG); ++ val &= ~(SPI_MAX_TRAILCNT << SPI_TRAILCNT_OFF); ++ if(channel == 0) ++ SET_MODECFG(val, 0); ++ else ++ SET_MODECFG(val, 1); ++ val |= (SPI_TRAILCNT << SPI_TRAILCNT_OFF); ++ writel(val, sspi->regs + SAMSPI_MODE_CFG); ++ ++ config_sspi(sspi); ++} ++ ++static irqreturn_t samspi_interrupt(int irq, void *dev_id) ++{ ++ u32 val; ++ struct samspi_bus *sspi = (struct samspi_bus *)dev_id; ++ ++ dump_regs(sspi); ++ val = readl(sspi->regs + SAMSPI_PENDING_CLR); ++ printk("PENDING=%x\n", val); ++ writel(val, sspi->regs + SAMSPI_PENDING_CLR); ++ ++ /* We get interrupted only for bad news */ ++ if(sspi->tx_done != PASS){ ++ sspi->tx_done = FAIL; ++ } ++ if(sspi->rx_done != PASS){ ++ sspi->rx_done = FAIL; ++ } ++ sspi->state = STOPPED; ++ complete(&sspi->xfer_completion); ++ ++ return IRQ_HANDLED; ++} ++ ++void samspi_dma_rxcb(struct s3c2410_dma_chan *chan, void *buf_id, int size, enum s3c2410_dma_buffresult res) ++{ ++ struct samspi_bus *sspi = (struct samspi_bus *)buf_id; ++ ++ if(res == S3C2410_RES_OK){ ++ sspi->rx_done = PASS; ++ dbg_printk("DmaRx-%d ", size); ++ }else{ ++ sspi->rx_done = FAIL; ++ dbg_printk("DmaAbrtRx-%d ", size); ++ } ++ ++ if(sspi->tx_done != BUSY && sspi->state != STOPPED) /* If other done and all OK */ ++ complete(&sspi->xfer_completion); ++} ++ ++void samspi_dma_txcb(struct s3c2410_dma_chan *chan, void *buf_id, int size, enum s3c2410_dma_buffresult res) ++{ ++ struct samspi_bus *sspi = (struct samspi_bus *)buf_id; ++ ++ if(res == S3C2410_RES_OK){ ++ sspi->tx_done = PASS; ++ dbg_printk("DmaTx-%d ", size); ++ }else{ ++ sspi->tx_done = FAIL; ++ dbg_printk("DmaAbrtTx-%d ", size); ++ } ++ ++ if(sspi->rx_done != BUSY && sspi->state != STOPPED) /* If other done and all OK */ ++ complete(&sspi->xfer_completion); ++} ++ ++static int wait_for_txshiftout(struct samspi_bus *sspi, unsigned long t) ++{ ++ unsigned long timeout; ++ ++ timeout = jiffies + t; ++ while((__raw_readl(sspi->regs + SAMSPI_SPI_STATUS) >> 6) & 0x7f){ ++ if(time_after(jiffies, timeout)) ++ return -1; ++ cpu_relax(); ++ } ++ return 0; ++} ++ ++static int wait_for_xfer(struct samspi_bus *sspi, struct spi_transfer *xfer) ++{ ++ int status; ++ u32 val; ++ ++ val = msecs_to_jiffies(xfer->len / (sspi->min_speed / 8 / 1000)); /* time to xfer data at min. speed */ ++ if(sspi->cur_mode & SPI_SLAVE) ++ val += msecs_to_jiffies(5000); /* 5secs to switch on the Master */ ++ else ++ val += msecs_to_jiffies(10); /* just some more */ ++ status = wait_for_completion_interruptible_timeout(&sspi->xfer_completion, val); ++ ++ if(status == 0) ++ status = -ETIMEDOUT; ++ else if(status == -ERESTARTSYS) ++ status = -EINTR; ++ else if((sspi->tx_done != PASS) || (sspi->rx_done != PASS)) /* Some Xfer failed */ ++ status = -EIO; ++ else ++ status = 0; /* All OK */ ++ ++ /* When TxLen <= SPI-FifoLen in Slave mode, DMA returns naively */ ++ if(!status && (sspi->cur_mode & SPI_SLAVE) && (xfer->tx_buf != NULL)){ ++ val = msecs_to_jiffies(xfer->len / (sspi->min_speed / 8 / 1000)); /* Be lenient */ ++ val += msecs_to_jiffies(5000); /* 5secs to switch on the Master */ ++ status = wait_for_txshiftout(sspi, val); ++ if(status == -1) ++ status = -ETIMEDOUT; ++ else ++ status = 0; ++ } ++ ++ return status; ++} ++ ++#define INVALID_DMA_ADDRESS 0xffffffff ++/* First, try to map buf onto phys addr as such. ++ * If xfer->r/tx_buf was not on contiguous memory, ++ * allocate from our preallocated DMA buffer. ++ */ ++static int samspi_map_xfer(struct samspi_bus *sspi, struct spi_transfer *xfer) ++{ ++ struct device *dev = &sspi->pdev->dev; ++ ++ sspi->rx_tmp = NULL; ++ sspi->tx_tmp = NULL; ++ ++ xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS; ++ if(xfer->tx_buf != NULL){ ++ xfer->tx_dma = dma_map_single(dev, ++ (void *) xfer->tx_buf, xfer->len, ++ DMA_TO_DEVICE); ++ if(dma_mapping_error(dev, xfer->tx_dma)) ++ goto alloc_from_buffer; ++ } ++ if(xfer->rx_buf != NULL){ ++ xfer->rx_dma = dma_map_single(dev, ++ xfer->rx_buf, xfer->len, ++ DMA_FROM_DEVICE); ++ if(dma_mapping_error(dev, xfer->rx_dma)){ ++ if(xfer->tx_buf) ++ dma_unmap_single(dev, ++ xfer->tx_dma, xfer->len, ++ DMA_TO_DEVICE); ++ goto alloc_from_buffer; ++ } ++ } ++ return 0; ++ ++alloc_from_buffer: /* If the xfer->[r/t]x_buf was not on contiguous memory */ ++ ++ if(xfer->len <= SAMSPI_DMABUF_LEN){ ++ if(xfer->rx_buf != NULL){ ++ xfer->rx_dma = sspi->rx_dma_phys; ++ sspi->rx_tmp = (void *)sspi->rx_dma_cpu; ++ } ++ if(xfer->tx_buf != NULL){ ++ xfer->tx_dma = sspi->tx_dma_phys; ++ sspi->tx_tmp = (void *)sspi->tx_dma_cpu; ++ } ++ }else{ ++ printk("If you plan to use this Xfer size often, increase SAMSPI_DMABUF_LEN\n"); ++ if(xfer->rx_buf != NULL){ ++ sspi->rx_tmp = dma_alloc_coherent(&sspi->pdev->dev, SAMSPI_DMABUF_LEN, ++ &xfer->rx_dma, GFP_KERNEL | GFP_DMA); ++ if(sspi->rx_tmp == NULL) ++ return -ENOMEM; ++ } ++ if(xfer->tx_buf != NULL){ ++ sspi->tx_tmp = dma_alloc_coherent(&sspi->pdev->dev, ++ SAMSPI_DMABUF_LEN, &xfer->tx_dma, GFP_KERNEL | GFP_DMA); ++ if(sspi->tx_tmp == NULL){ ++ if(xfer->rx_buf != NULL) ++ dma_free_coherent(&sspi->pdev->dev, ++ SAMSPI_DMABUF_LEN, sspi->rx_tmp, xfer->rx_dma); ++ return -ENOMEM; ++ } ++ } ++ } ++ ++ if(xfer->tx_buf != NULL) ++ memcpy(sspi->tx_tmp, xfer->tx_buf, xfer->len); ++ ++ return 0; ++} ++ ++static void samspi_unmap_xfer(struct samspi_bus *sspi, struct spi_transfer *xfer) ++{ ++ if((sspi->rx_tmp == NULL) && (sspi->tx_tmp == NULL)) /* if map_single'd */ ++ return; ++ ++ if(xfer->rx_buf != NULL) ++ memcpy(xfer->rx_buf, sspi->rx_tmp, xfer->len); ++ ++ if(xfer->len > SAMSPI_DMABUF_LEN){ ++ if(xfer->rx_buf != NULL) ++ dma_free_coherent(&sspi->pdev->dev, SAMSPI_DMABUF_LEN, sspi->rx_tmp, xfer->rx_dma); ++ if(xfer->tx_buf != NULL) ++ dma_free_coherent(&sspi->pdev->dev, SAMSPI_DMABUF_LEN, sspi->tx_tmp, xfer->tx_dma); ++ }else{ ++ sspi->rx_tmp = NULL; ++ sspi->tx_tmp = NULL; ++ } ++} ++ ++static void handle_msg(struct samspi_bus *sspi, struct spi_message *msg) ++{ ++ u8 bpw; ++ u32 speed, val; ++ int status = 0; ++ struct spi_transfer *xfer; ++ struct spi_device *spi = msg->spi; ++ ++ config_sspi(sspi); ++ ++ dump_regs(sspi); ++ list_for_each_entry (xfer, &msg->transfers, transfer_list) { ++ ++ if(!msg->is_dma_mapped && samspi_map_xfer(sspi, xfer)){ ++ dev_err(&spi->dev, "Xfer: Unable to allocate DMA buffer!\n"); ++ status = -ENOMEM; ++ goto out; ++ } ++ ++ INIT_COMPLETION(sspi->xfer_completion); ++ ++ /* Only BPW and Speed may change across transfers */ ++ bpw = xfer->bits_per_word ? : spi->bits_per_word; ++ speed = xfer->speed_hz ? : spi->max_speed_hz; ++ ++ if(sspi->cur_bpw != bpw || sspi->cur_speed != speed){ ++ sspi->cur_bpw = bpw; ++ sspi->cur_speed = speed; ++ config_sspi(sspi); ++ } ++ ++ /* Pending only which is to be done */ ++ sspi->rx_done = PASS; ++ sspi->tx_done = PASS; ++ sspi->state = RUNNING; ++ ++ /* Enable Interrupts */ ++ enable_spiintr(sspi, xfer); ++ ++ /* Enqueue data on DMA */ ++ enable_spienqueue(sspi, xfer); ++ ++ /* Enable DMA */ ++ enable_spidma(sspi, xfer); ++ ++ /* Enable TX/RX */ ++ enable_spichan(sspi, xfer); ++ ++ /* Slave Select */ ++ enable_spics(sspi, xfer); ++ ++ dump_regs(sspi); ++ status = wait_for_xfer(sspi, xfer); ++ ++ /************** ++ * Block Here * ++ **************/ ++ ++ if(status == -ETIMEDOUT){ ++ dev_err(&spi->dev, "Xfer: Timeout!\n"); ++ dump_regs(sspi); ++ sspi->state = STOPPED; ++ /* DMA Disable*/ ++ val = readl(sspi->regs + SAMSPI_MODE_CFG); ++ val &= ~(SPI_MODE_TXDMA_ON | SPI_MODE_RXDMA_ON); ++ writel(val, sspi->regs + SAMSPI_MODE_CFG); ++ flush_dma(sspi, xfer); ++ flush_spi(sspi); ++ if(!msg->is_dma_mapped) ++ samspi_unmap_xfer(sspi, xfer); ++ goto out; ++ } ++ if(status == -EINTR){ ++ dev_err(&spi->dev, "Xfer: Interrupted!\n"); ++ dump_regs(sspi); ++ sspi->state = STOPPED; ++ /* DMA Disable*/ ++ val = readl(sspi->regs + SAMSPI_MODE_CFG); ++ val &= ~(SPI_MODE_TXDMA_ON | SPI_MODE_RXDMA_ON); ++ writel(val, sspi->regs + SAMSPI_MODE_CFG); ++ flush_dma(sspi, xfer); ++ flush_spi(sspi); ++ if(!msg->is_dma_mapped) ++ samspi_unmap_xfer(sspi, xfer); ++ goto out; ++ } ++ if(status == -EIO){ /* Some Xfer failed */ ++ dev_err(&spi->dev, "Xfer: Failed!\n"); ++ dump_regs(sspi); ++ sspi->state = STOPPED; ++ /* DMA Disable*/ ++ val = readl(sspi->regs + SAMSPI_MODE_CFG); ++ val &= ~(SPI_MODE_TXDMA_ON | SPI_MODE_RXDMA_ON); ++ writel(val, sspi->regs + SAMSPI_MODE_CFG); ++ flush_dma(sspi, xfer); ++ flush_spi(sspi); ++ if(!msg->is_dma_mapped) ++ samspi_unmap_xfer(sspi, xfer); ++ goto out; ++ } ++ ++ if(xfer->delay_usecs){ ++ udelay(xfer->delay_usecs); ++ dbg_printk("xfer-delay=%u\n", xfer->delay_usecs); ++ } ++ if(xfer->cs_change && !(sspi->cur_mode & SPI_SLAVE)){ ++ writel(readl(sspi->regs + SAMSPI_SLAVE_SEL) | SPI_SLAVE_SIG_INACT, ++ sspi->regs + SAMSPI_SLAVE_SEL); ++ dbg_printk("xfer-cs_chng=%u\n", xfer->cs_change); ++ } ++ ++ msg->actual_length += xfer->len; ++ ++ if(!msg->is_dma_mapped) ++ samspi_unmap_xfer(sspi, xfer); ++ } ++ ++out: ++ /* Slave Deselect */ ++ val = readl(sspi->regs + SAMSPI_SLAVE_SEL); ++ val &= ~SPI_SLAVE_AUTO; ++ val |= SPI_SLAVE_SIG_INACT; ++ writel(val, sspi->regs + SAMSPI_SLAVE_SEL); ++ ++ /* Disable Interrupts */ ++ writel(0, sspi->regs + SAMSPI_SPI_INT_EN); ++ ++ /* Tx/Rx Disable */ ++ val = readl(sspi->regs + SAMSPI_CH_CFG); ++ val &= ~(SPI_CH_RXCH_ON | SPI_CH_TXCH_ON); ++ writel(val, sspi->regs + SAMSPI_CH_CFG); ++ ++ /* DMA Disable*/ ++ val = readl(sspi->regs + SAMSPI_MODE_CFG); ++ val &= ~(SPI_MODE_TXDMA_ON | SPI_MODE_RXDMA_ON); ++ writel(val, sspi->regs + SAMSPI_MODE_CFG); ++ ++ msg->status = status; ++ if(msg->complete) ++ msg->complete(msg->context); ++} ++ ++static void samspi_work(struct work_struct *work) ++{ ++ struct samspi_bus *sspi = container_of(work, struct samspi_bus, work); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&sspi->lock, flags); ++ while (!list_empty(&sspi->queue)) { ++ struct spi_message *msg; ++ ++ msg = container_of(sspi->queue.next, struct spi_message, queue); ++ list_del_init(&msg->queue); ++ spin_unlock_irqrestore(&sspi->lock, flags); ++ ++ handle_msg(sspi, msg); ++ ++ spin_lock_irqsave(&sspi->lock, flags); ++ } ++ spin_unlock_irqrestore(&sspi->lock, flags); ++} ++ ++static void samspi_cleanup(struct spi_device *spi) ++{ ++ dbg_printk("%s:%s:%d\n", __FILE__, __func__, __LINE__); ++} ++ ++static int samspi_transfer(struct spi_device *spi, struct spi_message *msg) ++{ ++ struct spi_master *master = spi->master; ++ struct samspi_bus *sspi = spi_master_get_devdata(master); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&sspi->lock, flags); ++ msg->actual_length = 0; ++ list_add_tail(&msg->queue, &sspi->queue); ++ queue_work(sspi->workqueue, &sspi->work); ++ spin_unlock_irqrestore(&sspi->lock, flags); ++ ++ return 0; ++} ++ ++/* the spi->mode bits understood by this driver: */ ++#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_SLAVE) ++ ++/* ++ * Here we only check the validity of requested configuration and ++ * save the configuration in a local data-structure. ++ * The controller is actually configured only just before ++ * we get a message to transfer _and_ if no other message is pending(already configured). ++ */ ++static int samspi_setup(struct spi_device *spi) ++{ ++ unsigned long flags; ++ unsigned int psr; ++ struct samspi_bus *sspi = spi_master_get_devdata(spi->master); ++ ++ spin_lock_irqsave(&sspi->lock, flags); ++ if(!list_empty(&sspi->queue)){ /* Any pending message? */ ++ spin_unlock_irqrestore(&sspi->lock, flags); ++ dev_dbg(&spi->dev, "setup: attempt while messages in queue!\n"); ++ return -EBUSY; ++ } ++ spin_unlock_irqrestore(&sspi->lock, flags); ++ ++ if (spi->chip_select > spi->master->num_chipselect) { ++ dev_dbg(&spi->dev, "setup: invalid chipselect %u (%u defined)\n", ++ spi->chip_select, spi->master->num_chipselect); ++ return -EINVAL; ++ } ++ ++ spi->bits_per_word = spi->bits_per_word ? : 8; ++ ++ if((spi->bits_per_word != 8) && ++ (spi->bits_per_word != 16) && ++ (spi->bits_per_word != 32)){ ++ dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n", spi->bits_per_word); ++ return -EINVAL; ++ } ++ ++ spi->max_speed_hz = spi->max_speed_hz ? : sspi->max_speed; ++ ++ /* Round-off max_speed_hz */ ++ psr = clk_get_rate(sspi->clk) / spi->max_speed_hz / 2 - 1; ++ psr &= 0xff; ++ if(spi->max_speed_hz < clk_get_rate(sspi->clk) / 2 / (psr + 1)) ++ psr = (psr+1) & 0xff; ++ ++ spi->max_speed_hz = clk_get_rate(sspi->clk) / 2 / (psr + 1); ++ ++ if (spi->max_speed_hz > sspi->max_speed ++ || spi->max_speed_hz < sspi->min_speed){ ++ dev_err(&spi->dev, "setup: req speed(%u) out of range[%u-%u]\n", ++ spi->max_speed_hz, sspi->min_speed, sspi->max_speed); ++ return -EINVAL; ++ } ++ ++ if (spi->mode & ~MODEBITS) { ++ dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", spi->mode & ~MODEBITS); ++ return -EINVAL; ++ } ++ ++ dbg_printk("@%s spi-%p sspi-%p\n", __func__, spi, sspi); ++ dbg_printk("Asked to setup mode:-"); ++ dbg_printk("max_speed_hz = %d\n", spi->max_speed_hz); ++ dbg_printk("chip_select = %d\n", spi->chip_select); ++ dbg_printk("bits_per_word = %d\n", spi->bits_per_word); ++ dbg_printk("irq = %d\n", spi->irq); ++ dbg_printk("Clk Phs = %d\n", spi->mode & SPI_CPHA); ++ dbg_printk("Clk Pol = %d\n", spi->mode & SPI_CPOL); ++ dbg_printk("ChipSelct = %s\n", (spi->mode & (1<<2)) ? "high" : "low" ); ++ dbg_printk("Mode = %s\n", (spi->mode & SPI_SLAVE) ? "Slave" : "Master"); ++ ++ if((sspi->cur_bpw == spi->bits_per_word) && ++ (sspi->cur_speed == spi->max_speed_hz) && ++ (sspi->cur_mode == spi->mode)) /* If no change in configuration, do nothing */ ++ return 0; ++ ++ sspi->cur_bpw = spi->bits_per_word; ++ sspi->cur_speed = spi->max_speed_hz; ++ sspi->cur_mode = spi->mode; ++ ++ return 0; ++} ++ ++static int __init samspi_probe(struct platform_device *pdev) ++{ ++ struct spi_master *master; ++ struct samspi_bus *sspi; ++ int ret = -ENODEV; ++ ++ dbg_printk("%s:%s:%d ID=%d\n", __FILE__, __func__, __LINE__, pdev->id); ++ master = spi_alloc_master(&pdev->dev, sizeof(struct samspi_bus)); /* Allocate contiguous SPI controller */ ++ if (master == NULL) ++ return ret; ++ sspi = spi_master_get_devdata(master); ++ sspi->pdev = pdev; ++ sspi->master = master; ++ platform_set_drvdata(pdev, master); ++ ++ INIT_WORK(&sspi->work, samspi_work); ++ spin_lock_init(&sspi->lock); ++ INIT_LIST_HEAD(&sspi->queue); ++ init_completion(&sspi->xfer_completion); ++ ++ sspi->clk = clk_get(&pdev->dev, "spi"); ++ if (IS_ERR(sspi->clk)) { ++ sspi->clk = NULL; ++ dev_err(&pdev->dev, "cannot acquire clock \n"); ++ ret = -EBUSY; ++ goto lb1; ++ } ++ ret = clk_enable(sspi->clk); ++ if (ret) { ++ clk_put(sspi->clk); ++ sspi->clk = NULL; ++ dev_err(&pdev->dev, "cannot enable clock \n"); ++ ret = -EBUSY; ++ goto lb2; ++ } ++ ++ sspi->cur_mode = SPI_SLAVE; /* Start in Slave mode */ ++ sspi->cur_bpw = 8; ++ sspi->max_speed = clk_get_rate(sspi->clk) / 2 / (0x0 + 1); ++ sspi->min_speed = clk_get_rate(sspi->clk) / 2 / (0xff + 1); ++ ++ /* Get and Map Resources */ ++ sspi->iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (sspi->iores == NULL) { ++ dev_err(&pdev->dev, "cannot find IO resource\n"); ++ ret = -ENOENT; ++ goto lb3; ++ } ++ ++ sspi->ioarea = request_mem_region(sspi->iores->start, sspi->iores->end - sspi->iores->start + 1, pdev->name); ++ if (sspi->ioarea == NULL) { ++ dev_err(&pdev->dev, "cannot request IO\n"); ++ ret = -ENXIO; ++ goto lb4; ++ } ++ ++ sspi->regs = ioremap(sspi->iores->start, sspi->iores->end - sspi->iores->start + 1); ++ if (sspi->regs == NULL) { ++ dev_err(&pdev->dev, "cannot map IO\n"); ++ ret = -ENXIO; ++ goto lb5; ++ } ++ ++ sspi->tx_dma_cpu = dma_alloc_coherent(&pdev->dev, SAMSPI_DMABUF_LEN, &sspi->tx_dma_phys, GFP_KERNEL | GFP_DMA); ++ if(sspi->tx_dma_cpu == NULL){ ++ dev_err(&pdev->dev, "Unable to allocate TX DMA buffers\n"); ++ ret = -ENOMEM; ++ goto lb6; ++ } ++ ++ sspi->rx_dma_cpu = dma_alloc_coherent(&pdev->dev, SAMSPI_DMABUF_LEN, &sspi->rx_dma_phys, GFP_KERNEL | GFP_DMA); ++ if(sspi->rx_dma_cpu == NULL){ ++ dev_err(&pdev->dev, "Unable to allocate RX DMA buffers\n"); ++ ret = -ENOMEM; ++ goto lb7; ++ } ++ ++ sspi->irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if(sspi->irqres == NULL){ ++ dev_err(&pdev->dev, "cannot find IRQ\n"); ++ ret = -ENOENT; ++ goto lb8; ++ } ++ ++ ret = request_irq(sspi->irqres->start, samspi_interrupt, IRQF_DISABLED, ++ pdev->name, sspi); ++ if(ret){ ++ dev_err(&pdev->dev, "cannot acquire IRQ\n"); ++ ret = -EBUSY; ++ goto lb9; ++ } ++ ++ sspi->workqueue = create_singlethread_workqueue(master->dev.parent->bus_id); ++ if(!sspi->workqueue){ ++ dev_err(&pdev->dev, "cannot create workqueue\n"); ++ ret = -EBUSY; ++ goto lb10; ++ } ++ ++ master->bus_num = pdev->id; ++ master->setup = samspi_setup; ++ master->transfer = samspi_transfer; ++ master->cleanup = samspi_cleanup; ++ master->num_chipselect = 1; /* Only 1 Slave connected on SMDK */ ++ ++ if(spi_register_master(master)){ ++ dev_err(&pdev->dev, "cannot register SPI master\n"); ++ ret = -EBUSY; ++ goto lb11; ++ } ++ ++ /* Configure GPIOs */ ++ if(pdev->id == 0) ++ SETUP_SPI(sspi, 0); ++ else if(pdev->id == 1) ++ SETUP_SPI(sspi, 1); ++ ++ if(s3c2410_dma_request(sspi->rx_dmach, &samspi_dma_client, NULL)){ ++ dev_err(&pdev->dev, "cannot get RxDMA\n"); ++ ret = -EBUSY; ++ goto lb12; ++ } ++ s3c2410_dma_set_buffdone_fn(sspi->rx_dmach, samspi_dma_rxcb); ++ s3c2410_dma_devconfig(sspi->rx_dmach, S3C2410_DMASRC_HW, 0, sspi->sfr_phyaddr + SAMSPI_SPI_RX_DATA); ++ s3c2410_dma_config(sspi->rx_dmach, sspi->cur_bpw/8, 0); ++ s3c2410_dma_setflags(sspi->rx_dmach, S3C2410_DMAF_AUTOSTART); ++ ++ if(s3c2410_dma_request(sspi->tx_dmach, &samspi_dma_client, NULL)){ ++ dev_err(&pdev->dev, "cannot get TxDMA\n"); ++ ret = -EBUSY; ++ goto lb13; ++ } ++ s3c2410_dma_set_buffdone_fn(sspi->tx_dmach, samspi_dma_txcb); ++ s3c2410_dma_devconfig(sspi->tx_dmach, S3C2410_DMASRC_MEM, 0, sspi->sfr_phyaddr + SAMSPI_SPI_TX_DATA); ++ s3c2410_dma_config(sspi->tx_dmach, sspi->cur_bpw/8, 0); ++ s3c2410_dma_setflags(sspi->tx_dmach, S3C2410_DMAF_AUTOSTART); ++ ++ /* Setup Deufult Mode */ ++ samspi_hwinit(sspi, pdev->id); ++ ++ printk("Samsung SoC SPI Driver loaded for SPI-%d\n", pdev->id); ++ printk("\tMax,Min-Speed [%d, %d]Hz\n", sspi->max_speed, sspi->min_speed); ++ printk("\tIrq=%d\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n", ++ sspi->irqres->start, ++ sspi->iores->end, sspi->iores->start, ++ sspi->rx_dmach, sspi->tx_dmach); ++ return 0; ++ ++lb13: ++ s3c2410_dma_free(sspi->rx_dmach, &samspi_dma_client); ++lb12: ++ spi_unregister_master(master); ++lb11: ++ destroy_workqueue(sspi->workqueue); ++lb10: ++ free_irq(sspi->irqres->start, sspi); ++lb9: ++lb8: ++ dma_free_coherent(&pdev->dev, SAMSPI_DMABUF_LEN, sspi->rx_dma_cpu, sspi->rx_dma_phys); ++lb7: ++ dma_free_coherent(&pdev->dev, SAMSPI_DMABUF_LEN, sspi->tx_dma_cpu, sspi->tx_dma_phys); ++lb6: ++ iounmap((void *) sspi->regs); ++lb5: ++ release_mem_region(sspi->iores->start, sspi->iores->end - sspi->iores->start + 1); ++lb4: ++lb3: ++ clk_disable(sspi->clk); ++lb2: ++ clk_put(sspi->clk); ++lb1: ++ platform_set_drvdata(pdev, NULL); ++ spi_master_put(master); ++ ++ return ret; ++} ++ ++static int __exit samspi_remove(struct platform_device *pdev) ++{ ++ struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); ++ struct samspi_bus *sspi = spi_master_get_devdata(master); ++ ++ s3c2410_dma_free(sspi->tx_dmach, &samspi_dma_client); ++ s3c2410_dma_free(sspi->rx_dmach, &samspi_dma_client); ++ spi_unregister_master(master); ++ destroy_workqueue(sspi->workqueue); ++ free_irq(sspi->irqres->start, sspi); ++ dma_free_coherent(&pdev->dev, SAMSPI_DMABUF_LEN, sspi->rx_dma_cpu, sspi->rx_dma_phys); ++ dma_free_coherent(&pdev->dev, SAMSPI_DMABUF_LEN, sspi->tx_dma_cpu, sspi->tx_dma_phys); ++ iounmap((void *) sspi->regs); ++ release_mem_region(sspi->iores->start, sspi->iores->end - sspi->iores->start + 1); ++ clk_disable(sspi->clk); ++ clk_put(sspi->clk); ++ platform_set_drvdata(pdev, NULL); ++ spi_master_put(master); ++ ++ return 0; ++} ++ ++static struct platform_driver sam_spi_driver = { ++ .driver = { ++ .name = "sam-spi", ++ .owner = THIS_MODULE, ++ .bus = &platform_bus_type, ++ }, ++// .remove = sam_spi_remove, ++// .shutdown = sam_spi_shutdown, ++// .suspend = sam_spi_suspend, ++// .resume = sam_spi_resume, ++}; ++ ++static int __init sam_spi_init(void) ++{ ++ dbg_printk("%s:%s:%d\n", __FILE__, __func__, __LINE__); ++ return platform_driver_probe(&sam_spi_driver, samspi_probe); ++} ++module_init(sam_spi_init); ++ ++static void __exit sam_spi_exit(void) ++{ ++ platform_driver_unregister(&sam_spi_driver); ++} ++module_exit(sam_spi_exit); ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Jaswinder Singh Brar "); ++MODULE_DESCRIPTION("Samsung SOC SPI Controller"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/spi/spi_sam.h linux-2.6.28.6/drivers/spi/spi_sam.h +--- linux-2.6.28/drivers/spi/spi_sam.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/spi/spi_sam.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,286 @@ ++/* ++ * spi_sam.h - Samsung SOC SPI controller driver. ++ * ++ * Copyright (C) 2009 Samsung Electronics Ltd. ++ */ ++ ++#ifndef _LINUX_SPI_SAM_H ++#define _LINUX_SPI_SAM_H ++ ++#define SAMSPI_CH_CFG (0x00) //SPI configuration ++#define SAMSPI_CLK_CFG (0x04) //Clock configuration ++#define SAMSPI_MODE_CFG (0x08) //SPI FIFO control ++#define SAMSPI_SLAVE_SEL (0x0C) //Slave selection ++#define SAMSPI_SPI_INT_EN (0x10) //SPI interrupt enable ++#define SAMSPI_SPI_STATUS (0x14) //SPI status ++#define SAMSPI_SPI_TX_DATA (0x18) //SPI TX data ++#define SAMSPI_SPI_RX_DATA (0x1C) //SPI RX data ++#define SAMSPI_PACKET_CNT (0x20) //count how many data master gets ++#define SAMSPI_PENDING_CLR (0x24) //Pending clear ++#define SAMSPI_SWAP_CFG (0x28) //SWAP config register ++#define SAMSPI_FB_CLK (0x2c) //SWAP FB config register ++ ++#define SPI_CH_HS_EN (1<<6) /* High Speed Enable */ ++#define SPI_CH_SW_RST (1<<5) ++#define SPI_CH_SLAVE (1<<4) ++#define SPI_CPOL_L (1<<3) ++#define SPI_CPHA_B (1<<2) ++#define SPI_CH_RXCH_ON (1<<1) ++#define SPI_CH_TXCH_ON (1<<0) ++ ++#define SPI_CLKSEL_PCLK (0<<9) ++#define SPI_CLKSEL_USBCLK (1<<9) ++#define SPI_CLKSEL_ECLK (2<<9) ++#define SPI_CLKSEL_SRCMSK (3<<9) ++#define SPI_ENCLK_ENABLE (1<<8) ++ ++#ifdef CONFIG_SPICLK_SRC_PCLK ++#define SPI_CLKSEL_SRC (0 << 9) ++#elif defined (CONFIG_SPICLK_SRC_SPIEXT) ++#define SPI_CLKSEL_SRC (1 << 9) ++#elif defined (CONFIG_SPICLK_SRC_USB) ++#define SPI_CLKSEL_SRC (1 << 9) ++#elif defined (CONFIG_SPICLK_SRC_EPLL) ++#define SPI_CLKSEL_SRC (2 << 9) ++#elif defined (CONFIG_SPICLK_SRC_SCLK48M) ++#define SPI_CLKSEL_SRC (1 << 9) ++#elif defined (CONFIG_SPICLK_SRC_SCLKSPI) ++#define SPI_CLKSEL_SRC (2 << 9) ++#endif ++ ++#define SPI_MODE_CH_TSZ_BYTE (0<<29) ++#define SPI_MODE_CH_TSZ_HALFWORD (1<<29) ++#define SPI_MODE_CH_TSZ_WORD (2<<29) ++#define SPI_MODE_BUS_TSZ_BYTE (0<<17) ++#define SPI_MODE_BUS_TSZ_HALFWORD (1<<17) ++#define SPI_MODE_BUS_TSZ_WORD (2<<17) ++#define SPI_MODE_RXDMA_ON (1<<2) ++#define SPI_MODE_TXDMA_ON (1<<1) ++#define SPI_MODE_4BURST (1<<0) ++ ++#define SPI_SLAVE_AUTO (1<<1) ++#define SPI_SLAVE_SIG_INACT (1<<0) ++ ++#define SPI_INT_TRAILING_EN (1<<6) ++#define SPI_INT_RX_OVERRUN_EN (1<<5) ++#define SPI_INT_RX_UNDERRUN_EN (1<<4) ++#define SPI_INT_TX_OVERRUN_EN (1<<3) ++#define SPI_INT_TX_UNDERRUN_EN (1<<2) ++#define SPI_INT_RX_FIFORDY_EN (1<<1) ++#define SPI_INT_TX_FIFORDY_EN (1<<0) ++ ++#define SPI_STUS_TX_DONE (1<<21) ++#define SPI_STUS_TRAILCNT_ZERO (1<<20) ++#define SPI_STUS_RX_OVERRUN_ERR (1<<5) ++#define SPI_STUS_RX_UNDERRUN_ERR (1<<4) ++#define SPI_STUS_TX_OVERRUN_ERR (1<<3) ++#define SPI_STUS_TX_UNDERRUN_ERR (1<<2) ++#define SPI_STUS_RX_FIFORDY (1<<1) ++#define SPI_STUS_TX_FIFORDY (1<<0) ++ ++#define SPI_PACKET_CNT_EN (1<<16) ++ ++#define SPI_PND_TX_UNDERRUN_CLR (1<<4) ++#define SPI_PND_TX_OVERRUN_CLR (1<<3) ++#define SPI_PND_RX_UNDERRUN_CLR (1<<2) ++#define SPI_PND_RX_OVERRUN_CLR (1<<1) ++#define SPI_PND_TRAILING_CLR (1<<0) ++ ++#define SPI_SWAP_RX_HALF_WORD (1<<7) ++#define SPI_SWAP_RX_BYTE (1<<6) ++#define SPI_SWAP_RX_BIT (1<<5) ++#define SPI_SWAP_RX_EN (1<<4) ++#define SPI_SWAP_TX_HALF_WORD (1<<3) ++#define SPI_SWAP_TX_BYTE (1<<2) ++#define SPI_SWAP_TX_BIT (1<<1) ++#define SPI_SWAP_TX_EN (1<<0) ++ ++#define SPI_FBCLK_0NS (0<<0) ++#define SPI_FBCLK_3NS (1<<0) ++#define SPI_FBCLK_6NS (2<<0) ++#define SPI_FBCLK_9NS (3<<0) ++ ++#ifdef CONFIG_CPU_S3C6410 ++#define CH0_TX_MAXBYTES (64) ++#define CH0_RX_MAXBYTES (64) ++#define CH0_PER_UNIT (1) ++#elif defined (CONFIG_CPU_S5P6440) ++#define CH0_TX_MAXBYTES (256) ++#define CH0_RX_MAXBYTES (256) ++#define CH0_PER_UNIT (4) ++#elif defined (CONFIG_CPU_S5PC100) ++#define CH0_TX_MAXBYTES (64) ++#define CH0_RX_MAXBYTES (64) ++#define CH0_PER_UNIT (1) ++#endif ++ ++#define CH1_TX_MAXBYTES (64) ++#define CH1_RX_MAXBYTES (64) ++#define CH1_PER_UNIT (4) ++#define SPI_CH0_TXFIFO_MAXLEN (CH0_TX_MAXBYTES / CH0_PER_UNIT - 1) ++#define SPI_CH0_RXFIFO_MAXLEN (CH0_RX_MAXBYTES / CH0_PER_UNIT - 1) ++#define SPI_CH0_TXFLEN_OFF (5) ++#define SPI_CH0_RXFLEN_OFF (11) ++#define SPI_CH1_TXFIFO_MAXLEN (CH1_TX_MAXBYTES / CH1_PER_UNIT - 1) ++#define SPI_CH1_RXFIFO_MAXLEN (CH1_RX_MAXBYTES / CH1_PER_UNIT - 1) ++#define SPI_CH1_TXFLEN_OFF (5) ++#define SPI_CH1_RXFLEN_OFF (11) ++#define SPI_MAX_TRAILCNT (0x3ff) ++#define SPI_TRAILCNT_OFF (19) ++ ++#define SPI_CH0_TXFIFO_LEN SPI_CH0_TXFIFO_MAXLEN ++#define SPI_CH0_RXFIFO_LEN SPI_CH0_RXFIFO_MAXLEN ++#define SPI_CH1_TXFIFO_LEN SPI_CH1_TXFIFO_MAXLEN ++#define SPI_CH1_RXFIFO_LEN SPI_CH1_RXFIFO_MAXLEN ++#define SPI_TRAILCNT SPI_MAX_TRAILCNT ++ ++#ifdef CONFIG_CPU_S3C6410 ++ ++#define SAMSPI_PA_SPI0 S3C64XX_PA_SPI0 ++#define SAMSPI_PA_SPI1 S3C64XX_PA_SPI1 ++ ++#elif defined (CONFIG_CPU_S5P6440) ++ ++#define SAMSPI_PA_SPI0 S5P64XX_PA_SPI0 ++#define SAMSPI_PA_SPI1 S5P64XX_PA_SPI1 ++ ++#elif defined (CONFIG_CPU_S5PC100) ++ ++#define SAMSPI_PA_SPI0 S5PC1XX_PA_SPI0 ++#define SAMSPI_PA_SPI1 S5PC1XX_PA_SPI1 ++//#define SAMSPI_PA_SPI2 S5PC1XX_PA_SPI2 ++ ++#endif ++ ++#define DMACH_SPIIN_0 DMACH_SPI0_IN ++#define DMACH_SPIOUT_0 DMACH_SPI0_OUT ++#define DMACH_SPIIN_1 DMACH_SPI1_IN ++#define DMACH_SPIOUT_1 DMACH_SPI1_OUT ++ ++#define GPMISO_0 0 ++#define GPCLK_0 1 ++#define GPMOSI_0 2 ++#define GPCS_0 3 ++#define GPMISO_1 4 ++#define GPCLK_1 5 ++#define GPMOSI_1 6 ++#define GPCS_1 7 ++ ++#ifdef CONFIG_CPU_S3C6410 ++ ++#define GPNAME S3C64XX_GPC ++#define GPIO_MISO_0 S3C64XX_GPC0_SPI_MISO0 ++#define GPIO_CLK_0 S3C64XX_GPC1_SPI_CLK0 ++#define GPIO_MOSI_0 S3C64XX_GPC2_SPI_MOSI0 ++#define GPIO_CS_0 S3C64XX_GPC3_SPI_nCS0 ++#define GPIO_MISO_1 S3C64XX_GPC4_SPI_MISO1 ++#define GPIO_CLK_1 S3C64XX_GPC5_SPI_CLK1 ++#define GPIO_MOSI_1 S3C64XX_GPC6_SPI_MOSI1 ++#define GPIO_CS_1 S3C64XX_GPC7_SPI_nCS1 ++ ++#elif defined (CONFIG_CPU_S5P6440) ++ ++#define GPNAME S5P64XX_GPC ++#define GPIO_MISO_0 S5P64XX_GPC0_SPI_MISO0 ++#define GPIO_CLK_0 S5P64XX_GPC1_SPI_CLK0 ++#define GPIO_MOSI_0 S5P64XX_GPC2_SPI_MOSI0 ++#define GPIO_CS_0 S5P64XX_GPC3_SPI_nCS0 ++#define GPIO_MISO_1 S5P64XX_GPC4_SPI_MISO1 ++#define GPIO_CLK_1 S5P64XX_GPC5_SPI_CLK1 ++#define GPIO_MOSI_1 S5P64XX_GPC6_SPI_MOSI1 ++#define GPIO_CS_1 S5P64XX_GPC7_SPI_nCS1 ++ ++#elif defined (CONFIG_CPU_S5PC100) ++ ++//#define DMACH_SPIIN_2 DMACH_SPI2_IN ++//#define DMACH_SPIOUT_2 DMACH_SPI2_OUT ++#define GPNAME S5PC1XX_GPB ++#define GPIO_MISO_0 S5PC1XX_GPB0_SPI_MISO0 ++#define GPIO_CLK_0 S5PC1XX_GPB1_SPI_CLK0 ++#define GPIO_MOSI_0 S5PC1XX_GPB2_SPI_MOSI0 ++#define GPIO_CS_0 S5PC1XX_GPB3_SPI_CS0 ++#define GPIO_MISO_1 S5PC1XX_GPB4_SPI_MISO1 ++#define GPIO_CLK_1 S5PC1XX_GPB5_SPI_CLK1 ++#define GPIO_MOSI_1 S5PC1XX_GPB6_SPI_MOSI1 ++#define GPIO_CS_1 S5PC1XX_GPB7_SPI_CS1 ++//#define GPIO_MISO_2 S5PC1XX_GPG3_2SPI_MISO2 ++//#define GPIO_CLK_2 S5PC1XX_GPG3_0SPI_CLK2 ++//#define GPIO_MOSI_2 S5PC1XX_GPG3_3SPI_MOSI2 ++//#define GPIO_CS_2 S5PC1XX_GPG3_1SPI_CS2 ++//#define GPMISO_2 4 ++//#define GPCLK_2 5 ++//#define GPMOSI_2 6 ++//#define GPCS_2 7 ++ ++#endif ++ ++#define SETUP_SPI(sspi, n) do{ \ ++ sspi->sfr_phyaddr = SAMSPI_PA_SPI##n; \ ++ sspi->rx_dmach = DMACH_SPIIN_##n; \ ++ sspi->tx_dmach = DMACH_SPIOUT_##n; \ ++ s3c_gpio_cfgpin(GPNAME(GPMISO_##n), GPIO_MISO_##n); \ ++ s3c_gpio_cfgpin(GPNAME(GPCLK_##n), GPIO_CLK_##n); \ ++ s3c_gpio_cfgpin(GPNAME(GPMOSI_##n), GPIO_MOSI_##n); \ ++ s3c_gpio_cfgpin(GPNAME(GPCS_##n), GPIO_CS_##n); \ ++ s3c_gpio_setpull(GPNAME(GPMISO_##n), S3C_GPIO_PULL_UP); \ ++ s3c_gpio_setpull(GPNAME(GPCLK_##n), S3C_GPIO_PULL_UP); \ ++ s3c_gpio_setpull(GPNAME(GPMOSI_##n), S3C_GPIO_PULL_UP); \ ++ s3c_gpio_setpull(GPNAME(GPCS_##n), S3C_GPIO_PULL_UP); \ ++ }while(0) ++ ++#define SET_MODECFG(v, n) do{ \ ++ v &= ~((SPI_CH##n##_TXFIFO_MAXLEN << SPI_CH##n##_TXFLEN_OFF) \ ++ | (SPI_CH##n##_RXFIFO_MAXLEN << SPI_CH##n##_RXFLEN_OFF)); \ ++ v |= (SPI_CH##n##_TXFIFO_LEN << SPI_CH##n##_TXFLEN_OFF) \ ++ | (SPI_CH##n##_RXFIFO_LEN << SPI_CH##n##_RXFLEN_OFF); \ ++ }while(0) ++ ++#define SAMSPI_DMABUF_LEN (16*1024) ++ ++enum samspi_state { ++ RUNNING, ++ STOPPED, ++}; ++ ++enum xfer_state { ++ PASS, ++ FAIL, ++ BUSY, ++}; ++ ++/* Structure for each SPI controller of Samsung SOC */ ++struct samspi_bus { ++ struct spi_master *master; ++ struct workqueue_struct *workqueue; ++ struct platform_device *pdev; ++ struct work_struct work; ++ struct list_head queue; ++ spinlock_t lock; /* protect 'queue' */ ++ enum samspi_state state; ++ enum dma_ch rx_dmach; ++ enum dma_ch tx_dmach; ++ u32 sfr_phyaddr; ++ struct resource *irqres; ++ struct resource *ioarea; ++ struct resource *iores; ++ void __iomem *regs; ++ void __iomem *tx_dma_cpu; ++ void __iomem *rx_dma_cpu; ++ void __iomem *rx_tmp; ++ void __iomem *tx_tmp; ++ dma_addr_t tx_dma_phys; ++ dma_addr_t rx_dma_phys; ++ struct clk *parrent_clk; /* PCLK, USBCLK or Epll_CLK */ ++ struct clk *clk; ++ struct completion xfer_completion; ++ enum xfer_state tx_done; ++ enum xfer_state rx_done; ++ u32 max_speed; ++ u32 min_speed; ++ //struct list_head dq; /* List of all devices attached to this bus/controller */ ++ /* Current parameters of the controller due to request from active transfer */ ++ u8 cur_mode, cur_bpw, active_chip; ++ u32 cur_speed; ++}; ++ ++#endif //_LINUX_SPI_SAM_H +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/spi/spidev.c linux-2.6.28.6/drivers/spi/spidev.c +--- linux-2.6.28/drivers/spi/spidev.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/spi/spidev.c 2009-04-30 09:36:39.000000000 +0200 +@@ -66,7 +66,7 @@ + * REVISIT should changing those two modes be privileged? + */ + #define SPI_MODE_MASK (SPI_CPHA | SPI_CPOL | SPI_CS_HIGH \ +- | SPI_LSB_FIRST | SPI_3WIRE | SPI_LOOP) ++ | SPI_LSB_FIRST | SPI_3WIRE | SPI_LOOP | SPI_SLAVE) + + struct spidev_data { + dev_t devt; +@@ -83,7 +83,7 @@ + static LIST_HEAD(device_list); + static DEFINE_MUTEX(device_list_lock); + +-static unsigned bufsiz = 4096; ++static unsigned bufsiz = SPIDEV_MAX_BUFFSIZE; + module_param(bufsiz, uint, S_IRUGO); + MODULE_PARM_DESC(bufsiz, "data bytes in biggest supported SPI message"); + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/Kconfig linux-2.6.28.6/drivers/usb/Kconfig +--- linux-2.6.28/drivers/usb/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/Kconfig 2009-04-30 09:36:39.000000000 +0200 +@@ -32,6 +32,8 @@ + default y if ARCH_OMAP + default y if ARCH_LH7A404 + default y if ARCH_S3C2410 ++ default y if ARCH_S3C64XX ++ default y if ARCH_S5PC1XX + default y if PXA27x + default y if PXA3xx + default y if ARCH_EP93XX +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/Makefile linux-2.6.28.6/drivers/usb/Makefile +--- linux-2.6.28/drivers/usb/Makefile 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/Makefile 2009-04-30 09:36:39.000000000 +0200 +@@ -17,6 +17,7 @@ + obj-$(CONFIG_USB_U132_HCD) += host/ + obj-$(CONFIG_USB_R8A66597_HCD) += host/ + obj-$(CONFIG_USB_HWA_HCD) += host/ ++obj-$(CONFIG_USB_S3C_OTG_HOST) += host/ + + obj-$(CONFIG_USB_C67X00_HCD) += c67x00/ + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/gadget/Kconfig linux-2.6.28.6/drivers/usb/gadget/Kconfig +--- linux-2.6.28/drivers/usb/gadget/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/gadget/Kconfig 2009-04-30 09:36:39.000000000 +0200 +@@ -112,6 +112,7 @@ + choice + prompt "USB Peripheral Controller" + depends on USB_GADGET ++ default USB_GADGET_S3C_OTGD if (PLAT_S3C64XX || PLAT_S5P64XX || PLAT_S5PC1XX) + help + A USB device uses a controller to talk to its host. + Systems should have only one such upstream link. +@@ -291,6 +292,19 @@ + boolean "S3C2410 udc debug messages" + depends on USB_GADGET_S3C2410 + ++config USB_GADGET_S3C_OTGD ++ boolean "S3C HS USB OTG Device" ++ depends on (PLAT_S3C64XX || PLAT_S5P64XX || PLAT_S5PC1XX) && !(USB_S3C_OTG_HOST) ++ help ++ Samsung's S3C64XX processors include high speed USB OTG2.0 ++ controller. It has 15 configurable endpoints, as well as ++ endpoint zero (for control transfers). ++ ++ This driver has been tested on the S3C6410, S5P6440, S5PC100 processor. ++ ++ Say "y" to link the driver statically, or "m" to build a ++ dynamically linked module called "s3c-udc-otg" and force all ++ gadget drivers to also be dynamically linked. + # + # Controllers available in both integrated and discrete versions + # +@@ -458,6 +472,43 @@ + + endchoice + ++comment "NOTE: S3C OTG device role enables the controller driver below" ++ depends on USB_GADGET_S3C_OTGD ++ ++config USB_S3C_OTGD ++ tristate "S3C high speed(2.0, dual-speed) USB OTG device" ++ depends on USB_GADGET && USB_GADGET_S3C_OTGD && !(USB_S3C_OTG_HOST) ++ default y ++ default USB_GADGET ++ select USB_GADGET_SELECTED ++ select USB_GADGET_DUALSPEED ++ help ++ Say "y" to link the driver statically, or "m" to build a ++ dynamically linked module called "s3c-udc-otg-hs" and force all ++ gadget drivers to also be dynamically linked. ++ ++choice ++ prompt "S3C OTGD transfer mode" ++ depends on USB_S3C_OTGD ++ default y ++ help ++ S3C USB OTG conteroller supports DMA mode and Slave mode ++ for the dat transfer. You must slect one for the core ++ operation mode. ++ ++config USB_GADGET_S3C_OTGD_DMA_MODE ++ bool "enabled DMA MODE" ++ depends on USB_GADGET_S3C_OTGD ++ help ++ S3C USB OTG core operates in DMA mode. ++ ++config USB_GADGET_S3C_OTGD_SLAVE_MODE ++ bool "enabled Slave MODE" ++ depends on USB_GADGET_S3C_OTGD ++ help ++ S3C USB OTG core operates in Slave mode. ++endchoice ++ + config USB_GADGET_DUALSPEED + bool + depends on USB_GADGET +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/gadget/Makefile linux-2.6.28.6/drivers/usb/gadget/Makefile +--- linux-2.6.28/drivers/usb/gadget/Makefile 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/gadget/Makefile 2009-04-30 09:36:39.000000000 +0200 +@@ -14,6 +14,7 @@ + obj-$(CONFIG_USB_OMAP) += omap_udc.o + obj-$(CONFIG_USB_LH7A40X) += lh7a40x_udc.o + obj-$(CONFIG_USB_S3C2410) += s3c2410_udc.o ++obj-$(CONFIG_USB_S3C_OTGD) += s3c_udc_otg.o + obj-$(CONFIG_USB_AT91) += at91_udc.o + obj-$(CONFIG_USB_ATMEL_USBA) += atmel_usba_udc.o + obj-$(CONFIG_USB_FSL_USB2) += fsl_usb2_udc.o +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/gadget/epautoconf.c linux-2.6.28.6/drivers/usb/gadget/epautoconf.c +--- linux-2.6.28/drivers/usb/gadget/epautoconf.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/gadget/epautoconf.c 2009-04-30 09:36:39.000000000 +0200 +@@ -275,8 +275,25 @@ + ep = find_ep (gadget, "ep1-bulk"); + if (ep && ep_matches (gadget, ep, desc)) + return ep; +- } + ++ } else if (gadget_is_s3c(gadget)) { ++ if (USB_ENDPOINT_XFER_INT == type) { ++ /* single buffering is enough */ ++ ep = find_ep (gadget, "ep3-int"); ++ if (ep && ep_matches (gadget, ep, desc)) ++ return ep; ++ } else if (USB_ENDPOINT_XFER_BULK == type ++ && (USB_DIR_IN & desc->bEndpointAddress)) { ++ ep = find_ep (gadget, "ep2-bulk"); ++ if (ep && ep_matches (gadget, ep, desc)) ++ return ep; ++ } else if (USB_ENDPOINT_XFER_BULK == type ++ && !(USB_DIR_IN & desc->bEndpointAddress)) { ++ ep = find_ep (gadget, "ep1-bulk"); ++ if (ep && ep_matches (gadget, ep, desc)) ++ return ep; ++ } ++ } + /* Second, look at endpoints until an unclaimed one looks usable */ + list_for_each_entry (ep, &gadget->ep_list, ep_list) { + if (ep_matches (gadget, ep, desc)) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/gadget/f_rndis.c linux-2.6.28.6/drivers/usb/gadget/f_rndis.c +--- linux-2.6.28/drivers/usb/gadget/f_rndis.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/gadget/f_rndis.c 2009-04-30 09:36:39.000000000 +0200 +@@ -172,6 +172,7 @@ + .bDescriptorType = USB_DT_INTERFACE, + + /* .bInterfaceNumber = DYNAMIC */ ++ .bAlternateSetting = 0, + .bNumEndpoints = 2, + .bInterfaceClass = USB_CLASS_CDC_DATA, + .bInterfaceSubClass = 0, +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/gadget/file_storage.c linux-2.6.28.6/drivers/usb/gadget/file_storage.c +--- linux-2.6.28/drivers/usb/gadget/file_storage.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/gadget/file_storage.c 2009-04-30 09:36:39.000000000 +0200 +@@ -4078,6 +4078,7 @@ + + DBG(fsg, "suspend\n"); + set_bit(SUSPENDED, &fsg->atomic_bitflags); ++ fsg->running = 0; + } + + static void fsg_resume(struct usb_gadget *gadget) +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/gadget/gadget_chips.h linux-2.6.28.6/drivers/usb/gadget/gadget_chips.h +--- linux-2.6.28/drivers/usb/gadget/gadget_chips.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/gadget/gadget_chips.h 2009-04-30 09:36:39.000000000 +0200 +@@ -104,6 +104,12 @@ + #define gadget_is_s3c2410(g) 0 + #endif + ++#if CONFIG_USB_GADGET_S3C_OTGD ++#define gadget_is_s3c(g) !strcmp("s3c-udc", (g)->name) ++#else ++#define gadget_is_s3c(g) 0 ++#endif ++ + #ifdef CONFIG_USB_GADGET_AT91 + #define gadget_is_at91(g) !strcmp("at91_udc", (g)->name) + #else +@@ -225,6 +231,8 @@ + return 0x21; + else if (gadget_is_fsl_qe(gadget)) + return 0x22; ++ else if (gadget_is_s3c(gadget)) ++ return 0x23; + return -ENOENT; + } + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/gadget/s3c2410_udc.c linux-2.6.28.6/drivers/usb/gadget/s3c2410_udc.c +--- linux-2.6.28/drivers/usb/gadget/s3c2410_udc.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/gadget/s3c2410_udc.c 2009-04-30 09:36:39.000000000 +0200 +@@ -53,8 +53,8 @@ + #include + #include + +-#include +-#include ++#include ++#include + + + #include "s3c2410_udc.h" +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/gadget/s3c_udc.h linux-2.6.28.6/drivers/usb/gadget/s3c_udc.h +--- linux-2.6.28/drivers/usb/gadget/s3c_udc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/gadget/s3c_udc.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,134 @@ ++/* ++ * drivers/usb/gadget/s3c_udc.h ++ * Samsung S3C on-chip full/high speed USB device controllers ++ * Copyright (C) 2005 for Samsung Electronics ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#ifndef __S3C_USB_GADGET ++#define __S3C_USB_GADGET ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++//#include ++ ++#include ++#include ++ ++// Max packet size ++#if defined(CONFIG_USB_GADGET_S3C_FS) ++#define EP0_FIFO_SIZE 8 ++#define EP_FIFO_SIZE 64 ++#define S3C_MAX_ENDPOINTS 5 ++#elif defined(CONFIG_USB_GADGET_S3C_HS) || defined(CONFIG_PLAT_S5P64XX) ++#define EP0_FIFO_SIZE 64 ++#define EP_FIFO_SIZE 512 ++#define EP_FIFO_SIZE2 1024 ++#define S3C_MAX_ENDPOINTS 9 ++#define DED_TX_FIFO 1 /* Dedicated NPTx fifo for s5p6440 */ ++#else ++#define EP0_FIFO_SIZE 64 ++#define EP_FIFO_SIZE 512 ++#define EP_FIFO_SIZE2 1024 ++#define S3C_MAX_ENDPOINTS 16 ++#endif ++ ++#define WAIT_FOR_SETUP 0 ++#define DATA_STATE_XMIT 1 ++#define DATA_STATE_NEED_ZLP 2 ++#define WAIT_FOR_OUT_STATUS 3 ++#define DATA_STATE_RECV 4 ++#define RegReadErr 5 ++#define FAIL_TO_SETUP 6 ++ ++/* ********************************************************************************************* */ ++/* IO ++ */ ++ ++typedef enum ep_type { ++ ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt ++} ep_type_t; ++ ++struct s3c_ep { ++ struct usb_ep ep; ++ struct s3c_udc *dev; ++ ++ const struct usb_endpoint_descriptor *desc; ++ struct list_head queue; ++ unsigned long pio_irqs; ++ ++ u8 stopped; ++ u8 bEndpointAddress; ++ u8 bmAttributes; ++ ++ ep_type_t ep_type; ++ u32 fifo; ++#ifdef CONFIG_USB_GADGET_S3C_FS ++ u32 csr1; ++ u32 csr2; ++#endif ++}; ++ ++struct s3c_request { ++ struct usb_request req; ++ struct list_head queue; ++}; ++ ++struct s3c_udc { ++ struct usb_gadget gadget; ++ struct usb_gadget_driver *driver; ++ //struct device *dev; ++ struct platform_device *dev; ++ spinlock_t lock; ++ ++ int ep0state; ++ struct s3c_ep ep[S3C_MAX_ENDPOINTS]; ++ ++ unsigned char usb_address; ++ ++ unsigned req_pending:1, req_std:1, req_config:1; ++}; ++ ++extern struct s3c_udc *the_controller; ++ ++#define ep_is_in(EP) (((EP)->bEndpointAddress&USB_DIR_IN)==USB_DIR_IN) ++#define ep_index(EP) ((EP)->bEndpointAddress&0xF) ++#define ep_maxpacket(EP) ((EP)->ep.maxpacket) ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/gadget/s3c_udc_otg.c linux-2.6.28.6/drivers/usb/gadget/s3c_udc_otg.c +--- linux-2.6.28/drivers/usb/gadget/s3c_udc_otg.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/gadget/s3c_udc_otg.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,1093 @@ ++/* ++ * drivers/usb/gadget/s3c_udc_otg.c ++ * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers ++ * ++ * Copyright (C) 2008 for Samsung Electronics ++ * ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include "s3c_udc.h" ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_USB_GADGET_S3C_OTGD_DMA_MODE) /* DMA mode */ ++#define OTG_DMA_MODE 1 ++ ++#elif defined(CONFIG_USB_GADGET_S3C_OTGD_SLAVE_MODE) /* Slave mode */ ++#define OTG_DMA_MODE 0 ++#error " Slave Mode is not implemented to do later" ++#else ++#error " Unknown S3C OTG operation mode, Select a correct operation mode" ++#endif ++ ++#undef DEBUG_S3C_UDC_SETUP ++#undef DEBUG_S3C_UDC_EP0 ++#undef DEBUG_S3C_UDC_ISR ++#undef DEBUG_S3C_UDC_OUT_EP ++#undef DEBUG_S3C_UDC_IN_EP ++#undef DEBUG_S3C_UDC ++ ++//#define DEBUG_S3C_UDC_SETUP ++//#define DEBUG_S3C_UDC_EP0 ++//#define DEBUG_S3C_UDC_ISR ++//#define DEBUG_S3C_UDC_OUT_EP ++//#define DEBUG_S3C_UDC_IN_EP ++//#define DEBUG_S3C_UDC ++ ++#define EP0_CON 0 ++#define EP1_OUT 1 ++#define EP2_IN 2 ++#define EP3_IN 3 ++#define EP_MASK 0xF ++ ++#if defined(DEBUG_S3C_UDC_SETUP) || defined(DEBUG_S3C_UDC_ISR)\ ++ || defined(DEBUG_S3C_UDC_OUT_EP) ++ ++static char *state_names[] = { ++ "WAIT_FOR_SETUP", ++ "DATA_STATE_XMIT", ++ "DATA_STATE_NEED_ZLP", ++ "WAIT_FOR_OUT_STATUS", ++ "DATA_STATE_RECV", ++ }; ++#endif ++ ++#ifdef DEBUG_S3C_UDC_SETUP ++#define DEBUG_SETUP(fmt,args...) printk(fmt, ##args) ++#else ++#define DEBUG_SETUP(fmt,args...) do {} while(0) ++#endif ++ ++#ifdef DEBUG_S3C_UDC_EP0 ++#define DEBUG_EP0(fmt,args...) printk(fmt, ##args) ++#else ++#define DEBUG_EP0(fmt,args...) do {} while(0) ++#endif ++ ++#ifdef DEBUG_S3C_UDC ++#define DEBUG(fmt,args...) printk(fmt, ##args) ++#else ++#define DEBUG(fmt,args...) do {} while(0) ++#endif ++ ++#ifdef DEBUG_S3C_UDC_ISR ++#define DEBUG_ISR(fmt,args...) printk(fmt, ##args) ++#else ++#define DEBUG_ISR(fmt,args...) do {} while(0) ++#endif ++ ++#ifdef DEBUG_S3C_UDC_OUT_EP ++#define DEBUG_OUT_EP(fmt,args...) printk(fmt, ##args) ++#else ++#define DEBUG_OUT_EP(fmt,args...) do {} while(0) ++#endif ++ ++#ifdef DEBUG_S3C_UDC_IN_EP ++#define DEBUG_IN_EP(fmt,args...) printk(fmt, ##args) ++#else ++#define DEBUG_IN_EP(fmt,args...) do {} while(0) ++#endif ++ ++ ++#define DRIVER_DESC "S3C HS USB OTG Device Driver, (c) 2008-2009 Samsung Electronics" ++#define DRIVER_VERSION "15 March 2009" ++ ++struct s3c_udc *the_controller; ++ ++static const char driver_name[] = "s3c-udc"; ++static const char driver_desc[] = DRIVER_DESC; ++static const char ep0name[] = "ep0-control"; ++ ++/* Max packet size*/ ++static unsigned int ep0_fifo_size = 64; ++static unsigned int ep_fifo_size = 512; ++static unsigned int ep_fifo_size2 = 1024; ++static int reset_available = 1; ++ ++extern void otg_phy_init(void); ++extern void otg_phy_off(void); ++extern struct usb_ctrlrequest usb_ctrl; ++ ++/* ++ Local declarations. ++*/ ++static int s3c_ep_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *); ++static int s3c_ep_disable(struct usb_ep *ep); ++static struct usb_request *s3c_alloc_request(struct usb_ep *ep, gfp_t gfp_flags); ++static void s3c_free_request(struct usb_ep *ep, struct usb_request *); ++ ++static int s3c_queue(struct usb_ep *ep, struct usb_request *, gfp_t gfp_flags); ++static int s3c_dequeue(struct usb_ep *ep, struct usb_request *); ++static int s3c_fifo_status(struct usb_ep *ep); ++static void s3c_fifo_flush(struct usb_ep *ep); ++static void s3c_ep0_read(struct s3c_udc *dev); ++static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep); ++static void s3c_handle_ep0(struct s3c_udc *dev); ++static int s3c_ep0_write(struct s3c_udc *dev); ++static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req); ++static void done(struct s3c_ep *ep, struct s3c_request *req, int status); ++static void stop_activity(struct s3c_udc *dev, struct usb_gadget_driver *driver); ++static int udc_enable(struct s3c_udc *dev); ++static void udc_set_address(struct s3c_udc *dev, unsigned char address); ++static void reconfig_usbd(void); ++static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed); ++static void nuke(struct s3c_ep *ep, int status); ++static int s3c_udc_set_halt(struct usb_ep *_ep, int value); ++ ++static struct usb_ep_ops s3c_ep_ops = { ++ .enable = s3c_ep_enable, ++ .disable = s3c_ep_disable, ++ ++ .alloc_request = s3c_alloc_request, ++ .free_request = s3c_free_request, ++ ++ .queue = s3c_queue, ++ .dequeue = s3c_dequeue, ++ ++ .set_halt = s3c_udc_set_halt, ++ .fifo_status = s3c_fifo_status, ++ .fifo_flush = s3c_fifo_flush, ++}; ++ ++#ifdef CONFIG_USB_GADGET_DEBUG_FILES ++ ++static const char proc_node_name[] = "driver/udc"; ++ ++static int ++udc_proc_read(char *page, char **start, off_t off, int count, ++ int *eof, void *_dev) ++{ ++ char *buf = page; ++ struct s3c_udc *dev = _dev; ++ char *next = buf; ++ unsigned size = count; ++ unsigned long flags; ++ int t; ++ ++ if (off != 0) ++ return 0; ++ ++ local_irq_save(flags); ++ ++ /* basic device status */ ++ t = scnprintf(next, size, ++ DRIVER_DESC "\n" ++ "%s version: %s\n" ++ "Gadget driver: %s\n" ++ "\n", ++ driver_name, DRIVER_VERSION, ++ dev->driver ? dev->driver->driver.name : "(none)"); ++ size -= t; ++ next += t; ++ ++ local_irq_restore(flags); ++ *eof = 1; ++ return count - size; ++} ++ ++#define create_proc_files() \ ++ create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev) ++#define remove_proc_files() \ ++ remove_proc_entry(proc_node_name, NULL) ++ ++#else /* !CONFIG_USB_GADGET_DEBUG_FILES */ ++ ++#define create_proc_files() do {} while (0) ++#define remove_proc_files() do {} while (0) ++ ++#endif /* CONFIG_USB_GADGET_DEBUG_FILES */ ++ ++#if OTG_DMA_MODE /* DMA Mode */ ++#include "s3c_udc_otg_xfer_dma.c" ++ ++#else /* Slave Mode */ ++#include "s3c_udc_otg_xfer_slave.c" ++#endif ++ ++/* ++ * udc_disable - disable USB device controller ++ */ ++static void udc_disable(struct s3c_udc *dev) ++{ ++ DEBUG_SETUP("%s: %p\n", __FUNCTION__, dev); ++ ++ udc_set_address(dev, 0); ++ ++ dev->ep0state = WAIT_FOR_SETUP; ++ dev->gadget.speed = USB_SPEED_UNKNOWN; ++ dev->usb_address = 0; ++ ++ otg_phy_off(); ++} ++ ++/* ++ * udc_reinit - initialize software state ++ */ ++static void udc_reinit(struct s3c_udc *dev) ++{ ++ unsigned int i; ++ ++ DEBUG_SETUP("%s: %p\n", __FUNCTION__, dev); ++ ++ /* device/ep0 records init */ ++ INIT_LIST_HEAD(&dev->gadget.ep_list); ++ INIT_LIST_HEAD(&dev->gadget.ep0->ep_list); ++ dev->ep0state = WAIT_FOR_SETUP; ++ ++ /* basic endpoint records init */ ++ for (i = 0; i < S3C_MAX_ENDPOINTS; i++) { ++ struct s3c_ep *ep = &dev->ep[i]; ++ ++ if (i != 0) ++ list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list); ++ ++ ep->desc = 0; ++ ep->stopped = 0; ++ INIT_LIST_HEAD(&ep->queue); ++ ep->pio_irqs = 0; ++ } ++ ++ /* the rest was statically initialized, and is read-only */ ++} ++ ++#define BYTES2MAXP(x) (x / 8) ++#define MAXP2BYTES(x) (x * 8) ++ ++/* until it's enabled, this UDC should be completely invisible ++ * to any USB host. ++ */ ++static int udc_enable(struct s3c_udc *dev) ++{ ++ DEBUG_SETUP("%s: %p\n", __FUNCTION__, dev); ++ ++ otg_phy_init(); ++ reconfig_usbd(); ++ ++ DEBUG_SETUP("S3C USB 2.0 OTG Controller Core Initialized : 0x%x\n", ++ readl(S3C_UDC_OTG_GINTMSK)); ++ ++ dev->gadget.speed = USB_SPEED_UNKNOWN; ++ ++ return 0; ++} ++ ++/* ++ Register entry point for the peripheral controller driver. ++*/ ++int usb_gadget_register_driver(struct usb_gadget_driver *driver) ++{ ++ struct s3c_udc *dev = the_controller; ++ int retval; ++ ++ DEBUG_SETUP("%s: %s\n", __FUNCTION__, driver->driver.name); ++ ++ if (!driver ++ || (driver->speed != USB_SPEED_FULL && driver->speed != USB_SPEED_HIGH) ++ || !driver->bind ++ || !driver->unbind || !driver->disconnect || !driver->setup) ++ return -EINVAL; ++ if (!dev) ++ return -ENODEV; ++ if (dev->driver) ++ return -EBUSY; ++ ++ /* first hook up the driver ... */ ++ dev->driver = driver; ++ dev->gadget.dev.driver = &driver->driver; ++ retval = device_add(&dev->gadget.dev); ++ ++ if(retval) { /* TODO */ ++ printk("target device_add failed, error %d\n", retval); ++ return retval; ++ } ++ ++ retval = driver->bind(&dev->gadget); ++ if (retval) { ++ printk("%s: bind to driver %s --> error %d\n", dev->gadget.name, ++ driver->driver.name, retval); ++ device_del(&dev->gadget.dev); ++ ++ dev->driver = 0; ++ dev->gadget.dev.driver = 0; ++ return retval; ++ } ++ ++ enable_irq(IRQ_OTG); ++ ++ printk("Registered gadget driver '%s'\n", driver->driver.name); ++ udc_enable(dev); ++ ++ return 0; ++} ++ ++EXPORT_SYMBOL(usb_gadget_register_driver); ++ ++/* ++ Unregister entry point for the peripheral controller driver. ++*/ ++int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) ++{ ++ struct s3c_udc *dev = the_controller; ++ unsigned long flags; ++ ++ if (!dev) ++ return -ENODEV; ++ if (!driver || driver != dev->driver) ++ return -EINVAL; ++ ++ spin_lock_irqsave(&dev->lock, flags); ++ dev->driver = 0; ++ stop_activity(dev, driver); ++ spin_unlock_irqrestore(&dev->lock, flags); ++ ++ driver->unbind(&dev->gadget); ++ device_del(&dev->gadget.dev); ++ ++ disable_irq(IRQ_OTG); ++ ++ printk("Unregistered gadget driver '%s'\n", driver->driver.name); ++ ++ udc_disable(dev); ++ ++ return 0; ++} ++ ++EXPORT_SYMBOL(usb_gadget_unregister_driver); ++ ++/* ++ * done - retire a request; caller blocked irqs ++ */ ++static void done(struct s3c_ep *ep, struct s3c_request *req, int status) ++{ ++ unsigned int stopped = ep->stopped; ++ ++ DEBUG("%s: %s %p, req = %p, stopped = %d\n", ++ __FUNCTION__, ep->ep.name, ep, &req->req, stopped); ++ ++ list_del_init(&req->queue); ++ ++ if (likely(req->req.status == -EINPROGRESS)) { ++ req->req.status = status; ++ } else { ++ status = req->req.status; ++ } ++ ++ if (status && status != -ESHUTDOWN) { ++ DEBUG("complete %s req %p stat %d len %u/%u\n", ++ ep->ep.name, &req->req, status, ++ req->req.actual, req->req.length); ++ } ++ ++ /* don't modify queue heads during completion callback */ ++ ep->stopped = 1; ++ ++ spin_unlock(&ep->dev->lock); ++ req->req.complete(&ep->ep, &req->req); ++ spin_lock(&ep->dev->lock); ++ ++ ep->stopped = stopped; ++} ++ ++/* ++ * nuke - dequeue ALL requests ++ */ ++static void nuke(struct s3c_ep *ep, int status) ++{ ++ struct s3c_request *req; ++ ++ DEBUG("%s: %s %p\n", __FUNCTION__, ep->ep.name, ep); ++ ++ /* called with irqs blocked */ ++ while (!list_empty(&ep->queue)) { ++ req = list_entry(ep->queue.next, struct s3c_request, queue); ++ done(ep, req, status); ++ } ++} ++ ++static void stop_activity(struct s3c_udc *dev, ++ struct usb_gadget_driver *driver) ++{ ++ int i; ++ ++ /* don't disconnect drivers more than once */ ++ if (dev->gadget.speed == USB_SPEED_UNKNOWN) ++ driver = 0; ++ dev->gadget.speed = USB_SPEED_UNKNOWN; ++ ++ /* prevent new request submissions, kill any outstanding requests */ ++ for (i = 0; i < S3C_MAX_ENDPOINTS; i++) { ++ struct s3c_ep *ep = &dev->ep[i]; ++ ep->stopped = 1; ++ nuke(ep, -ESHUTDOWN); ++ } ++ ++ /* report disconnect; the driver is already quiesced */ ++ if (driver) { ++ spin_unlock(&dev->lock); ++ driver->disconnect(&dev->gadget); ++ spin_lock(&dev->lock); ++ } ++ ++ /* re-init driver-visible data structures */ ++ udc_reinit(dev); ++} ++ ++static void reconfig_usbd(void) ++{ ++ /* 2. Soft-reset OTG Core and then unreset again. */ ++#ifdef DED_TX_FIFO ++ int i; ++#endif ++ unsigned int uTemp = writel(CORE_SOFT_RESET, S3C_UDC_OTG_GRSTCTL); ++ ++ writel( 0<<15 /* PHY Low Power Clock sel*/ ++ |1<<14 /* Non-Periodic TxFIFO Rewind Enable*/ ++ |0x5<<10 /* Turnaround time*/ ++ |0<<9|0<<8 /* [0:HNP disable, 1:HNP enable][ 0:SRP disable, 1:SRP enable] H1= 1,1*/ ++ |0<<7 /* Ulpi DDR sel*/ ++ |0<<6 /* 0: high speed utmi+, 1: full speed serial*/ ++ |0<<4 /* 0: utmi+, 1:ulpi*/ ++ |1<<3 /* phy i/f 0:8bit, 1:16bit*/ ++ |0x7<<0, /* HS/FS Timeout**/ ++ S3C_UDC_OTG_GUSBCFG); ++ ++ /* 3. Put the OTG device core in the disconnected state.*/ ++ uTemp = readl(S3C_UDC_OTG_DCTL); ++ uTemp |= SOFT_DISCONNECT; ++ writel(uTemp, S3C_UDC_OTG_DCTL); ++ ++ udelay(20); ++ ++ /* 4. Make the OTG device core exit from the disconnected state.*/ ++ uTemp = readl(S3C_UDC_OTG_DCTL); ++ uTemp = uTemp & ~SOFT_DISCONNECT; ++ writel(uTemp, S3C_UDC_OTG_DCTL); ++ ++ /* 5. Configure OTG Core to initial settings of device mode.*/ ++ writel(1<<18|0x0<<0, S3C_UDC_OTG_DCFG); /* [][1: full speed(30Mhz) 0:high speed]*/ ++ ++ mdelay(1); ++ ++ /* 6. Unmask the core interrupts*/ ++ writel(GINTMSK_INIT, S3C_UDC_OTG_GINTMSK); ++ ++ /* 7. Set NAK bit of EP0, EP1, EP2*/ ++ writel(DEPCTL_EPDIS|DEPCTL_SNAK|(0<<0), S3C_UDC_OTG_DOEPCTL(EP0_CON)); ++ writel(DEPCTL_EPDIS|DEPCTL_SNAK|(0<<0), S3C_UDC_OTG_DIEPCTL(EP0_CON)); ++ ++ /* 8. Unmask EPO interrupts*/ ++ writel( ((1<gadget.speed = USB_SPEED_HIGH; ++ } else { ++ ep0_fifo_size = 64; ++ ep_fifo_size = 64; ++ ep_fifo_size2 = 64; ++ dev->gadget.speed = USB_SPEED_FULL; ++ } ++ ++ dev->ep[0].ep.maxpacket = ep0_fifo_size; ++ dev->ep[1].ep.maxpacket = ep_fifo_size; ++ dev->ep[2].ep.maxpacket = ep_fifo_size; ++ dev->ep[3].ep.maxpacket = ep_fifo_size; ++ dev->ep[4].ep.maxpacket = ep_fifo_size; ++ dev->ep[5].ep.maxpacket = ep_fifo_size2; ++ dev->ep[6].ep.maxpacket = ep_fifo_size2; ++ dev->ep[7].ep.maxpacket = ep_fifo_size2; ++ dev->ep[8].ep.maxpacket = ep_fifo_size2; ++ ++ ++ /* EP0 - Control IN (64 bytes)*/ ++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL(EP0_CON)); ++ writel(ep_ctrl|(0<<0), S3C_UDC_OTG_DIEPCTL(EP0_CON)); ++ ++ /* EP0 - Control OUT (64 bytes)*/ ++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL(EP0_CON)); ++ writel(ep_ctrl|(0<<0), S3C_UDC_OTG_DOEPCTL(EP0_CON)); ++} ++ ++static int s3c_ep_enable(struct usb_ep *_ep, ++ const struct usb_endpoint_descriptor *desc) ++{ ++ struct s3c_ep *ep; ++ struct s3c_udc *dev; ++ unsigned long flags; ++ ++ DEBUG("%s: %p\n", __FUNCTION__, _ep); ++ ++ ep = container_of(_ep, struct s3c_ep, ep); ++ if (!_ep || !desc || ep->desc || _ep->name == ep0name ++ || desc->bDescriptorType != USB_DT_ENDPOINT ++ || ep->bEndpointAddress != desc->bEndpointAddress ++ || ep_maxpacket(ep) < le16_to_cpu(desc->wMaxPacketSize)) { ++ ++ DEBUG("%s: bad ep or descriptor\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ /* xfer types must match, except that interrupt ~= bulk */ ++ if (ep->bmAttributes != desc->bmAttributes ++ && ep->bmAttributes != USB_ENDPOINT_XFER_BULK ++ && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { ++ ++ DEBUG("%s: %s type mismatch\n", __FUNCTION__, _ep->name); ++ return -EINVAL; ++ } ++ ++ /* hardware _could_ do smaller, but driver doesn't */ ++ if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK ++ && le16_to_cpu(desc->wMaxPacketSize) != ep_maxpacket(ep)) ++ || !desc->wMaxPacketSize) { ++ ++ DEBUG("%s: bad %s maxpacket\n", __FUNCTION__, _ep->name); ++ return -ERANGE; ++ } ++ ++ dev = ep->dev; ++ if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) { ++ ++ DEBUG("%s: bogus device state\n", __FUNCTION__); ++ return -ESHUTDOWN; ++ } ++ ++ ep->stopped = 0; ++ ep->desc = desc; ++ ep->pio_irqs = 0; ++ ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize); ++ ++ /* Reset halt state */ ++ s3c_udc_set_halt(_ep, 0); ++ ++ spin_lock_irqsave(&ep->dev->lock, flags); ++ s3c_udc_ep_activate(ep); ++ spin_unlock_irqrestore(&ep->dev->lock, flags); ++ ++ DEBUG("%s: enabled %s, stopped = %d, maxpacket = %d\n", ++ __FUNCTION__, _ep->name, ep->stopped, ep->ep.maxpacket); ++ return 0; ++} ++ ++/** Disable EP ++ */ ++static int s3c_ep_disable(struct usb_ep *_ep) ++{ ++ struct s3c_ep *ep; ++ unsigned long flags; ++ ++ DEBUG("%s: %p\n", __FUNCTION__, _ep); ++ ++ ep = container_of(_ep, struct s3c_ep, ep); ++ if (!_ep || !ep->desc) { ++ DEBUG("%s: %s not enabled\n", __FUNCTION__, ++ _ep ? ep->ep.name : NULL); ++ return -EINVAL; ++ } ++ ++ spin_lock_irqsave(&ep->dev->lock, flags); ++ ++ /* Nuke all pending requests */ ++ nuke(ep, -ESHUTDOWN); ++ ++ ep->desc = 0; ++ ep->stopped = 1; ++ ++ spin_unlock_irqrestore(&ep->dev->lock, flags); ++ ++ DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name); ++ return 0; ++} ++ ++static struct usb_request *s3c_alloc_request(struct usb_ep *ep, ++ gfp_t gfp_flags) ++{ ++ struct s3c_request *req; ++ ++ DEBUG("%s: %s %p\n", __FUNCTION__, ep->name, ep); ++ ++ req = kmalloc(sizeof *req, gfp_flags); ++ if (!req) ++ return 0; ++ ++ memset(req, 0, sizeof *req); ++ INIT_LIST_HEAD(&req->queue); ++ ++ return &req->req; ++} ++ ++static void s3c_free_request(struct usb_ep *ep, struct usb_request *_req) ++{ ++ struct s3c_request *req; ++ ++ DEBUG("%s: %p\n", __FUNCTION__, ep); ++ ++ req = container_of(_req, struct s3c_request, req); ++ WARN_ON(!list_empty(&req->queue)); ++ kfree(req); ++} ++ ++/* dequeue JUST ONE request */ ++static int s3c_dequeue(struct usb_ep *_ep, struct usb_request *_req) ++{ ++ struct s3c_ep *ep; ++ struct s3c_request *req; ++ unsigned long flags; ++ ++ DEBUG("%s: %p\n", __FUNCTION__, _ep); ++ ++ ep = container_of(_ep, struct s3c_ep, ep); ++ if (!_ep || ep->ep.name == ep0name) ++ return -EINVAL; ++ ++ spin_lock_irqsave(&ep->dev->lock, flags); ++ ++ /* make sure it's actually queued on this endpoint */ ++ list_for_each_entry(req, &ep->queue, queue) { ++ if (&req->req == _req) ++ break; ++ } ++ if (&req->req != _req) { ++ spin_unlock_irqrestore(&ep->dev->lock, flags); ++ return -EINVAL; ++ } ++ ++ done(ep, req, -ECONNRESET); ++ ++ spin_unlock_irqrestore(&ep->dev->lock, flags); ++ return 0; ++} ++ ++/** Return bytes in EP FIFO ++ */ ++static int s3c_fifo_status(struct usb_ep *_ep) ++{ ++ int count = 0; ++ struct s3c_ep *ep; ++ ++ ep = container_of(_ep, struct s3c_ep, ep); ++ if (!_ep) { ++ DEBUG("%s: bad ep\n", __FUNCTION__); ++ return -ENODEV; ++ } ++ ++ DEBUG("%s: %d\n", __FUNCTION__, ep_index(ep)); ++ ++ /* LPD can't report unclaimed bytes from IN fifos */ ++ if (ep_is_in(ep)) ++ return -EOPNOTSUPP; ++ ++ return count; ++} ++ ++/** Flush EP FIFO ++ */ ++static void s3c_fifo_flush(struct usb_ep *_ep) ++{ ++ struct s3c_ep *ep; ++ ++ ep = container_of(_ep, struct s3c_ep, ep); ++ if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) { ++ DEBUG("%s: bad ep\n", __FUNCTION__); ++ return; ++ } ++ ++ DEBUG("%s: %d\n", __FUNCTION__, ep_index(ep)); ++} ++ ++/* --------------------------------------------------------------------------- ++ * device-scoped parts of the api to the usb controller hardware ++ * --------------------------------------------------------------------------- ++ */ ++ ++static int s3c_udc_get_frame(struct usb_gadget *_gadget) ++{ ++ /*fram count number [21:8]*/ ++ unsigned int frame = readl(S3C_UDC_OTG_DSTS); ++ ++ DEBUG("%s: %p\n", __FUNCTION__, _gadget); ++ return (frame & 0x3ff00); ++} ++ ++static int s3c_udc_wakeup(struct usb_gadget *_gadget) ++{ ++ DEBUG("%s: %p\n", __FUNCTION__, _gadget); ++ return -ENOTSUPP; ++} ++ ++static const struct usb_gadget_ops s3c_udc_ops = { ++ .get_frame = s3c_udc_get_frame, ++ .wakeup = s3c_udc_wakeup, ++ /* current versions must always be self-powered */ ++}; ++ ++static void nop_release(struct device *dev) ++{ ++ DEBUG("%s %s\n", __FUNCTION__, dev->bus_id); ++} ++ ++static struct s3c_udc memory = { ++ .usb_address = 0, ++ ++ .gadget = { ++ .ops = &s3c_udc_ops, ++ .ep0 = &memory.ep[0].ep, ++ .name = driver_name, ++ .dev = { ++ .bus_id = "gadget", ++ .release = nop_release, ++ }, ++ }, ++ ++ /* control endpoint */ ++ .ep[0] = { ++ .ep = { ++ .name = ep0name, ++ .ops = &s3c_ep_ops, ++ .maxpacket = EP0_FIFO_SIZE, ++ }, ++ .dev = &memory, ++ ++ .bEndpointAddress = 0, ++ .bmAttributes = 0, ++ ++ .ep_type = ep_control, ++ .fifo = (unsigned int) S3C_UDC_OTG_EP0_FIFO, ++ }, ++ ++ /* first group of endpoints */ ++ .ep[1] = { ++ .ep = { ++ .name = "ep1-bulk", ++ .ops = &s3c_ep_ops, ++ .maxpacket = EP_FIFO_SIZE, ++ }, ++ .dev = &memory, ++ ++ .bEndpointAddress = 1, ++ .bmAttributes = USB_ENDPOINT_XFER_BULK, ++ ++ .ep_type = ep_bulk_out, ++ .fifo = (unsigned int) S3C_UDC_OTG_EP1_FIFO, ++ }, ++ ++ .ep[2] = { ++ .ep = { ++ .name = "ep2-bulk", ++ .ops = &s3c_ep_ops, ++ .maxpacket = EP_FIFO_SIZE, ++ }, ++ .dev = &memory, ++ ++ .bEndpointAddress = USB_DIR_IN | 2, ++ .bmAttributes = USB_ENDPOINT_XFER_BULK, ++ ++ .ep_type = ep_bulk_in, ++ .fifo = (unsigned int) S3C_UDC_OTG_EP2_FIFO, ++ }, ++ ++ .ep[3] = { /* Though NOT USED XXX*/ ++ .ep = { ++ .name = "ep3-int", ++ .ops = &s3c_ep_ops, ++ .maxpacket = EP_FIFO_SIZE, ++ }, ++ .dev = &memory, ++ ++ .bEndpointAddress = USB_DIR_IN | 3, ++ .bmAttributes = USB_ENDPOINT_XFER_INT, ++ ++ .ep_type = ep_interrupt, ++ .fifo = (unsigned int) S3C_UDC_OTG_EP3_FIFO, ++ }, ++ .ep[4] = { /* Though NOT USED XXX*/ ++ .ep = { ++ .name = "ep4-int", ++ .ops = &s3c_ep_ops, ++ .maxpacket = EP_FIFO_SIZE, ++ }, ++ .dev = &memory, ++ ++ .bEndpointAddress = USB_DIR_IN | 4, ++ .bmAttributes = USB_ENDPOINT_XFER_INT, ++ ++ .ep_type = ep_interrupt, ++ .fifo = (unsigned int) S3C_UDC_OTG_EP4_FIFO, ++ }, ++ .ep[5] = { /* Though NOT USED XXX*/ ++ .ep = { ++ .name = "ep5-int", ++ .ops = &s3c_ep_ops, ++ .maxpacket = EP_FIFO_SIZE2, ++ }, ++ .dev = &memory, ++ ++ .bEndpointAddress = USB_DIR_IN | 5, ++ .bmAttributes = USB_ENDPOINT_XFER_INT, ++ ++ .ep_type = ep_interrupt, ++ .fifo = (unsigned int) S3C_UDC_OTG_EP5_FIFO, ++ }, ++ .ep[6] = { /* Though NOT USED XXX*/ ++ .ep = { ++ .name = "ep6-int", ++ .ops = &s3c_ep_ops, ++ .maxpacket = EP_FIFO_SIZE2, ++ }, ++ .dev = &memory, ++ ++ .bEndpointAddress = USB_DIR_IN | 6, ++ .bmAttributes = USB_ENDPOINT_XFER_INT, ++ ++ .ep_type = ep_interrupt, ++ .fifo = (unsigned int) S3C_UDC_OTG_EP6_FIFO, ++ }, ++ .ep[7] = { /* Though NOT USED XXX*/ ++ .ep = { ++ .name = "ep7-int", ++ .ops = &s3c_ep_ops, ++ .maxpacket = EP_FIFO_SIZE2, ++ }, ++ .dev = &memory, ++ ++ .bEndpointAddress = USB_DIR_IN | 7, ++ .bmAttributes = USB_ENDPOINT_XFER_INT, ++ ++ .ep_type = ep_interrupt, ++ .fifo = (unsigned int) S3C_UDC_OTG_EP7_FIFO, ++ }, ++ .ep[8] = { /* Though NOT USED XXX*/ ++ .ep = { ++ .name = "ep8-int", ++ .ops = &s3c_ep_ops, ++ .maxpacket = EP_FIFO_SIZE2, ++ }, ++ .dev = &memory, ++ ++ .bEndpointAddress = USB_DIR_IN | 8, ++ .bmAttributes = USB_ENDPOINT_XFER_INT, ++ ++ .ep_type = ep_interrupt, ++ .fifo = (unsigned int) S3C_UDC_OTG_EP8_FIFO, ++ }, ++}; ++ ++/* ++ * probe - binds to the platform device ++ */ ++static struct clk *otg_clock = NULL; ++ ++static int s3c_udc_probe(struct platform_device *pdev) ++{ ++ struct s3c_udc *dev = &memory; ++ int retval; ++ ++ DEBUG("%s: %p\n", __FUNCTION__, pdev); ++ ++ spin_lock_init(&dev->lock); ++ dev->dev = pdev; ++ ++ device_initialize(&dev->gadget.dev); ++ dev->gadget.dev.parent = &pdev->dev; ++ ++ dev->gadget.is_dualspeed = 1; /* Hack only*/ ++ dev->gadget.is_otg = 0; ++ dev->gadget.is_a_peripheral = 0; ++ dev->gadget.b_hnp_enable = 0; ++ dev->gadget.a_hnp_support = 0; ++ dev->gadget.a_alt_hnp_support = 0; ++ ++ the_controller = dev; ++ platform_set_drvdata(pdev, dev); ++ ++ otg_clock = clk_get(&pdev->dev, "otg"); ++ if (otg_clock == NULL) { ++ printk(KERN_INFO "failed to find otg clock source\n"); ++ return -ENOENT; ++ } ++ clk_enable(otg_clock); ++ ++ udc_reinit(dev); ++ ++ local_irq_disable(); ++ ++ /* irq setup after old hardware state is cleaned up */ ++ retval = ++ request_irq(IRQ_OTG, s3c_udc_irq, 0, driver_name, dev); ++ ++ if (retval != 0) { ++ DEBUG(KERN_ERR "%s: can't get irq %i, err %d\n", driver_name, ++ IRQ_OTG, retval); ++ return -EBUSY; ++ } ++ ++ disable_irq(IRQ_OTG); ++ local_irq_enable(); ++ create_proc_files(); ++ ++ return retval; ++} ++ ++static int s3c_udc_remove(struct platform_device *pdev) ++{ ++ struct s3c_udc *dev = platform_get_drvdata(pdev); ++ ++ DEBUG("%s: %p\n", __FUNCTION__, pdev); ++ ++ if (otg_clock != NULL) { ++ clk_disable(otg_clock); ++ clk_put(otg_clock); ++ otg_clock = NULL; ++ } ++ ++ remove_proc_files(); ++ usb_gadget_unregister_driver(dev->driver); ++ ++ free_irq(IRQ_OTG, dev); ++ ++ platform_set_drvdata(pdev, 0); ++ ++ the_controller = 0; ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int s3c_udc_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct s3c_udc *dev = the_controller; ++ int i; ++ ++ if (dev->driver) { ++ if (dev->driver->suspend) ++ dev->driver->suspend(&dev->gadget); ++ ++ /* Terminate any outstanding requests */ ++ for (i = 0; i < S3C_MAX_ENDPOINTS; i++) { ++ struct s3c_ep *ep = &dev->ep[i]; ++ if ( ep->dev != NULL ) ++ spin_lock(&ep->dev->lock); ++ ep->stopped = 1; ++ nuke(ep, -ESHUTDOWN); ++ if ( ep->dev != NULL ) ++ spin_unlock(&ep->dev->lock); ++ } ++ ++ disable_irq(IRQ_OTG); ++ udc_disable(dev); ++ clk_disable(otg_clock); ++ } ++ ++ return 0; ++} ++ ++static int s3c_udc_resume(struct platform_device *pdev) ++{ ++ struct s3c_udc *dev = the_controller; ++ ++ if (dev->driver) { ++ clk_enable(otg_clock); ++ udc_reinit(dev); ++ enable_irq(IRQ_OTG); ++ udc_enable(dev); ++ ++ if (dev->driver->resume) ++ dev->driver->resume(&dev->gadget); ++ } ++ ++ return 0; ++} ++#else ++#define s3c_udc_suspend NULL ++#define s3c_udc_resume NULL ++#endif /* CONFIG_PM */ ++ ++/*-------------------------------------------------------------------------*/ ++static struct platform_driver s3c_udc_driver = { ++ .probe = s3c_udc_probe, ++ .remove = s3c_udc_remove, ++ .suspend = s3c_udc_suspend, ++ .resume = s3c_udc_resume, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "s3c-usbgadget", ++ }, ++}; ++ ++static int __init udc_init(void) ++{ ++ int ret; ++ ++ ret = platform_driver_register(&s3c_udc_driver); ++ if(!ret) ++ printk("%s : %s\n" ++ "%s : version %s %s \n", ++ driver_name, DRIVER_DESC, ++ driver_name, DRIVER_VERSION, OTG_DMA_MODE? "(DMA Mode)" : "(Slave Mode)"); ++ ++ return ret; ++} ++ ++static void __exit udc_exit(void) ++{ ++ platform_driver_unregister(&s3c_udc_driver); ++ printk("Unloaded %s version %s\n", driver_name, DRIVER_VERSION); ++} ++ ++module_init(udc_init); ++module_exit(udc_exit); ++ ++MODULE_DESCRIPTION(DRIVER_DESC); ++MODULE_AUTHOR("Samsung"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c linux-2.6.28.6/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c +--- linux-2.6.28/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,1269 @@ ++/* ++ * drivers/usb/gadget/s3c_udc_otg_xfer_dma.c ++ * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers ++ * ++ * Copyright (C) 2009 for Samsung Electronics ++ * ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#define GINTMSK_INIT (INT_OUT_EP|INT_IN_EP|INT_RESUME|INT_ENUMDONE|INT_RESET|INT_SUSPEND) ++#define DOEPMSK_INIT (CTRL_OUT_EP_SETUP_PHASE_DONE|AHB_ERROR|TRANSFER_DONE) ++#define DIEPMSK_INIT (NON_ISO_IN_EP_TIMEOUT|AHB_ERROR|TRANSFER_DONE) ++#define GAHBCFG_INIT (PTXFE_HALF|NPTXFE_HALF|MODE_DMA|BURST_INCR4|GBL_INT_UNMASK) ++ ++static u8 clear_feature_num; ++static int clear_feature_flag = 0; ++static int set_conf_done = 0; ++ ++/* Bulk-Only Mass Storage Reset (class-specific request) */ ++#define GET_MAX_LUN_REQUEST 0xFE ++#define BOT_RESET_REQUEST 0xFF ++ ++void s3c_udc_ep_set_stall(struct s3c_ep *ep); ++ ++static inline void s3c_udc_ep0_zlp(void) ++{ ++ u32 ep_ctrl; ++ ++ writel(virt_to_phys(&usb_ctrl), S3C_UDC_OTG_DIEPDMA(EP0_CON)); ++ writel((1<<19| 0<<0), S3C_UDC_OTG_DIEPTSIZ(EP0_CON)); ++ ++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL(EP0_CON)); ++ writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK, S3C_UDC_OTG_DIEPCTL(EP0_CON)); ++ ++ DEBUG_EP0("%s:EP0 ZLP DIEPCTL0 = 0x%x\n", ++ __func__, readl(S3C_UDC_OTG_DIEPCTL(EP0_CON))); ++} ++ ++static inline void s3c_udc_pre_setup(void) ++{ ++ u32 ep_ctrl; ++ ++ DEBUG_IN_EP("%s : Prepare Setup packets.\n", __func__); ++ ++ writel((1 << 19)|sizeof(struct usb_ctrlrequest), S3C_UDC_OTG_DOEPTSIZ(EP0_CON)); ++ writel(virt_to_phys(&usb_ctrl), S3C_UDC_OTG_DOEPDMA(EP0_CON)); ++ ++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL(EP0_CON)); ++ writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK, S3C_UDC_OTG_DOEPCTL(EP0_CON)); ++} ++ ++static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req) ++{ ++ u32 *buf, ctrl; ++ u32 length, pktcnt; ++ u32 ep_num = ep_index(ep); ++ ++ buf = req->req.buf + req->req.actual; ++ prefetchw(buf); ++ ++ length = req->req.length - req->req.actual; ++ dma_cache_maint(buf, length, DMA_FROM_DEVICE); ++ ++ if(length == 0) ++ pktcnt = 1; ++ else ++ pktcnt = (length - 1)/(ep->ep.maxpacket) + 1; ++ ++ ctrl = readl(S3C_UDC_OTG_DOEPCTL(ep_num)); ++ ++ writel(virt_to_phys(buf), S3C_UDC_OTG_DOEPDMA(ep_num)); ++ writel((pktcnt<<19)|(length<<0), S3C_UDC_OTG_DOEPTSIZ(ep_num)); ++ writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, S3C_UDC_OTG_DOEPCTL(ep_num)); ++ ++ DEBUG_OUT_EP("%s: EP%d RX DMA start : DOEPDMA = 0x%x, DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n" ++ "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n", ++ __func__, ep_num, ++ readl(S3C_UDC_OTG_DOEPDMA(ep_num)), ++ readl(S3C_UDC_OTG_DOEPTSIZ(ep_num)), ++ readl(S3C_UDC_OTG_DOEPCTL(ep_num)), ++ buf, pktcnt, length); ++ return 0; ++ ++} ++ ++static int setdma_tx(struct s3c_ep *ep, struct s3c_request *req) ++{ ++ u32 *buf, ctrl = 0; ++ u32 length, pktcnt; ++ u32 ep_num = ep_index(ep); ++ ++ buf = req->req.buf + req->req.actual; ++ prefetch(buf); ++ length = req->req.length - req->req.actual; ++ ++ if(ep_num == EP0_CON) { ++ length = min(length, (u32)ep_maxpacket(ep)); ++ } ++ ++ req->req.actual += length; ++ dma_cache_maint(buf, length, DMA_TO_DEVICE); ++ ++ if(length == 0) { ++ pktcnt = 1; ++ } else { ++ pktcnt = (length - 1)/(ep->ep.maxpacket) + 1; ++ } ++ ++ ctrl = readl(S3C_UDC_OTG_DIEPCTL(ep_num)); ++ ++ writel(virt_to_phys(buf), S3C_UDC_OTG_DIEPDMA(ep_num)); ++ writel((pktcnt<<19)|(length<<0), S3C_UDC_OTG_DIEPTSIZ(ep_num)); ++ writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, S3C_UDC_OTG_DIEPCTL(ep_num)); ++ ++ ctrl = readl(S3C_UDC_OTG_DIEPCTL(EP0_CON)); ++ ctrl = (ctrl&~(EP_MASK<ep[ep_num]; ++ struct s3c_request *req = NULL; ++ u32 ep_tsr = 0, xfer_size = 0, xfer_length, is_short = 0; ++ ++ if (list_empty(&ep->queue)) { ++ DEBUG_OUT_EP("%s: RX DMA done : NULL REQ on OUT EP-%d\n", ++ __func__, ep_num); ++ return; ++ ++ } ++ ++ req = list_entry(ep->queue.next, struct s3c_request, queue); ++ ++ ep_tsr = readl(S3C_UDC_OTG_DOEPTSIZ(ep_num)); ++ ++ if(ep_num == EP0_CON) { ++ xfer_size = (ep_tsr & 0x7f); ++ ++ } else { ++ xfer_size = (ep_tsr & 0x7fff); ++ } ++ ++ dma_cache_maint(req->req.buf, req->req.length, DMA_FROM_DEVICE); ++ xfer_length = req->req.length - xfer_size; ++ req->req.actual += min(xfer_length, req->req.length - req->req.actual); ++ is_short = (xfer_length < ep->ep.maxpacket); ++ ++ DEBUG_OUT_EP("%s: RX DMA done : ep = %d, rx bytes = %d/%d, " ++ "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n", ++ __func__, ep_num, req->req.actual, req->req.length, ++ is_short, ep_tsr, xfer_size); ++ ++ if (is_short || req->req.actual == xfer_length) { ++ if(ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) { ++ DEBUG_OUT_EP(" => Send ZLP\n"); ++ dev->ep0state = WAIT_FOR_SETUP; ++ s3c_udc_ep0_zlp(); ++ ++ } else { ++ done(ep, req, 0); ++ ++ if(!list_empty(&ep->queue)) { ++ req = list_entry(ep->queue.next, struct s3c_request, queue); ++ DEBUG_OUT_EP("%s: Next Rx request start...\n", __func__); ++ setdma_rx(ep, req); ++ } ++ } ++ } ++} ++ ++static void complete_tx(struct s3c_udc *dev, u8 ep_num) ++{ ++ struct s3c_ep *ep = &dev->ep[ep_num]; ++ struct s3c_request *req; ++ u32 ep_tsr = 0, xfer_size = 0, xfer_length, is_short = 0; ++ u32 last; ++ ++ if (list_empty(&ep->queue)) { ++ DEBUG_IN_EP("%s: TX DMA done : NULL REQ on IN EP-%d\n", ++ __func__, ep_num); ++ return; ++ ++ } ++ ++ req = list_entry(ep->queue.next, struct s3c_request, queue); ++ ++ if(dev->ep0state == DATA_STATE_XMIT) { ++ DEBUG_IN_EP("%s: ep_num = %d, ep0stat == DATA_STATE_XMIT\n", ++ __func__, ep_num); ++ ++ last = write_fifo_ep0(ep, req); ++ ++ if(last) { ++ dev->ep0state = WAIT_FOR_SETUP; ++ } ++ ++ return; ++ } ++ ++ ep_tsr = readl(S3C_UDC_OTG_DIEPTSIZ(ep_num)); ++ ++ if(ep_num == EP0_CON) { ++ xfer_size = (ep_tsr & 0x7f); ++ ++ } else { ++ xfer_size = (ep_tsr & 0x7fff); ++ } ++ ++ req->req.actual = req->req.length - xfer_size; ++ xfer_length = req->req.length - xfer_size; ++ req->req.actual += min(xfer_length, req->req.length - req->req.actual); ++ is_short = (xfer_length < ep->ep.maxpacket); ++ ++ DEBUG_IN_EP("%s: TX DMA done : ep = %d, tx bytes = %d/%d, " ++ "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n", ++ __func__, ep_num, req->req.actual, req->req.length, ++ is_short, ep_tsr, xfer_size); ++ ++ if (req->req.actual == req->req.length) { ++ done(ep, req, 0); ++ ++ if(!list_empty(&ep->queue)) { ++ req = list_entry(ep->queue.next, struct s3c_request, queue); ++ DEBUG_IN_EP("%s: Next Tx request start...\n", __func__); ++ setdma_tx(ep, req); ++ } ++ } ++} ++static inline void s3c_udc_check_tx_queue(struct s3c_udc *dev, u8 ep_num) ++{ ++ struct s3c_ep *ep = &dev->ep[ep_num]; ++ struct s3c_request *req; ++ ++ DEBUG_IN_EP("%s: Check queue, ep_num = %d\n", __func__, ep_num); ++ ++ if (!list_empty(&ep->queue)) { ++ req = list_entry(ep->queue.next, struct s3c_request, queue); ++ DEBUG_IN_EP("%s: Next Tx request(0x%p) start...\n", __func__, req); ++ ++ if (ep_is_in(ep)) ++ setdma_tx(ep, req); ++ else ++ setdma_rx(ep, req); ++ } else { ++ DEBUG_IN_EP("%s: NULL REQ on IN EP-%d\n", __func__, ep_num); ++ ++ return; ++ } ++ ++} ++ ++static void process_ep_in_intr(struct s3c_udc *dev) ++{ ++ u32 ep_intr, ep_intr_status; ++ u8 ep_num = 0; ++ ++ ep_intr = readl(S3C_UDC_OTG_DAINT); ++ DEBUG_IN_EP("*** %s: EP In interrupt : DAINT = 0x%x\n", ++ __func__, ep_intr); ++ ++ ep_intr &= DAINT_MASK; ++ ++ while(ep_intr) { ++ if (ep_intr & 0x1) { ++ ep_intr_status = readl(S3C_UDC_OTG_DIEPINT(ep_num)); ++ DEBUG_IN_EP("\tEP%d-IN : DIEPINT = 0x%x\n", ++ ep_num, ep_intr_status); ++ ++ /* Interrupt Clear */ ++ writel(ep_intr_status, S3C_UDC_OTG_DIEPINT(ep_num)); ++ ++ if (ep_intr_status & TRANSFER_DONE) { ++ complete_tx(dev, ep_num); ++ ++ if (ep_num == 0) { ++ if(dev->ep0state == WAIT_FOR_SETUP) { ++ s3c_udc_pre_setup(); ++ } ++ ++ /* continue transfer after set_clear_halt for DMA mode */ ++ if (clear_feature_flag == 1) { ++ s3c_udc_check_tx_queue(dev, clear_feature_num); ++ clear_feature_flag = 0; ++ } ++ } ++ } ++ } ++ ep_num++; ++ ep_intr >>= 1; ++ } ++ ++} ++ ++static void process_ep_out_intr(struct s3c_udc * dev) ++{ ++ u32 ep_intr, ep_intr_status; ++ u8 ep_num = 0; ++ ++ ep_intr = readl(S3C_UDC_OTG_DAINT); ++ DEBUG_OUT_EP("*** %s: EP OUT interrupt : DAINT = 0x%x\n", ++ __func__, ep_intr); ++ ++ ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK; ++ ++ while(ep_intr) { ++ if (ep_intr & 0x1) { ++ ep_intr_status = readl(S3C_UDC_OTG_DOEPINT(ep_num)); ++ DEBUG_OUT_EP("\tEP%d-OUT : DOEPINT = 0x%x\n", ++ ep_num, ep_intr_status); ++ ++ /* Interrupt Clear */ ++ writel(ep_intr_status, S3C_UDC_OTG_DOEPINT(ep_num)); ++ ++ if (ep_num == 0 ) { ++ if (ep_intr_status & CTRL_OUT_EP_SETUP_PHASE_DONE) { ++ DEBUG_OUT_EP("\tSETUP packet(transaction) arrived\n"); ++ s3c_handle_ep0(dev); ++ } ++ ++ if (ep_intr_status & TRANSFER_DONE) { ++ complete_rx(dev, ep_num); ++ s3c_udc_pre_setup(); ++ } ++ ++ } else { ++ if (ep_intr_status & TRANSFER_DONE) { ++ complete_rx(dev, ep_num); ++ } ++ } ++ } ++ ep_num++; ++ ep_intr >>= 1; ++ } ++} ++ ++/* ++ * usb client interrupt handler. ++ */ ++static irqreturn_t s3c_udc_irq(int irq, void *_dev) ++{ ++ struct s3c_udc *dev = _dev; ++ u32 intr_status; ++ u32 usb_status, gintmsk; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&dev->lock, flags); ++ ++ intr_status = readl(S3C_UDC_OTG_GINTSTS); ++ gintmsk = readl(S3C_UDC_OTG_GINTMSK); ++ ++ DEBUG_ISR("\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x, DAINT : 0x%x, DAINTMSK : 0x%x\n", ++ __func__, intr_status, state_names[dev->ep0state], gintmsk, ++ readl(S3C_UDC_OTG_DAINT), readl(S3C_UDC_OTG_DAINTMSK)); ++ ++ if (!intr_status) { ++ spin_unlock_irqrestore(&dev->lock, flags); ++ return IRQ_HANDLED; ++ } ++ ++ if (intr_status & INT_ENUMDONE) { ++ DEBUG_ISR("\tSpeed Detection interrupt\n"); ++ ++ writel(INT_ENUMDONE, S3C_UDC_OTG_GINTSTS); ++ usb_status = (readl(S3C_UDC_OTG_DSTS) & 0x6); ++ ++ if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) { ++ DEBUG_ISR("\t\tFull Speed Detection\n"); ++ set_max_pktsize(dev, USB_SPEED_FULL); ++ ++ } else { ++ DEBUG_ISR("\t\tHigh Speed Detection : 0x%x\n", usb_status); ++ set_max_pktsize(dev, USB_SPEED_HIGH); ++ } ++ } ++ ++ if (intr_status & INT_EARLY_SUSPEND) { ++ DEBUG_ISR("\tEarly suspend interrupt\n"); ++ writel(INT_EARLY_SUSPEND, S3C_UDC_OTG_GINTSTS); ++ } ++ ++ if (intr_status & INT_SUSPEND) { ++ usb_status = readl(S3C_UDC_OTG_DSTS); ++ DEBUG_ISR("\tSuspend interrupt :(DSTS):0x%x\n", usb_status); ++ writel(INT_SUSPEND, S3C_UDC_OTG_GINTSTS); ++ ++ if (dev->gadget.speed != USB_SPEED_UNKNOWN ++ && dev->driver ++ && dev->driver->suspend) { ++ ++ dev->driver->suspend(&dev->gadget); ++ } ++ } ++ ++ if (intr_status & INT_RESUME) { ++ DEBUG_ISR("\tResume interrupt\n"); ++ writel(INT_RESUME, S3C_UDC_OTG_GINTSTS); ++ ++ if (dev->gadget.speed != USB_SPEED_UNKNOWN ++ && dev->driver ++ && dev->driver->resume) { ++ ++ dev->driver->resume(&dev->gadget); ++ } ++ } ++ ++ if (intr_status & INT_RESET) { ++ usb_status = readl(S3C_UDC_OTG_GOTGCTL); ++ DEBUG_ISR("\tReset interrupt - (GOTGCTL):0x%x\n", usb_status); ++ writel(INT_RESET, S3C_UDC_OTG_GINTSTS); ++ ++ set_conf_done = 0; ++ ++ if((usb_status & 0xc0000) == (0x3 << 18)) { ++ if(reset_available) { ++ DEBUG_ISR("\t\tOTG core got reset (%d)!! \n", reset_available); ++ reconfig_usbd(); ++ dev->ep0state = WAIT_FOR_SETUP; ++ reset_available = 0; ++ s3c_udc_pre_setup(); ++ } ++ ++ } else { ++ reset_available = 1; ++ DEBUG_ISR("\t\tRESET handling skipped\n"); ++ } ++ } ++ ++ if (intr_status & INT_IN_EP) { ++ process_ep_in_intr(dev); ++ } ++ ++ if(intr_status & INT_OUT_EP) { ++ process_ep_out_intr(dev); ++ } ++ ++ spin_unlock_irqrestore(&dev->lock, flags); ++ ++ return IRQ_HANDLED; ++} ++ ++/** Queue one request ++ * Kickstart transfer if needed ++ */ ++static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req, ++ gfp_t gfp_flags) ++{ ++ struct s3c_request *req; ++ struct s3c_ep *ep; ++ struct s3c_udc *dev; ++ unsigned long flags; ++ u32 ep_num, gintsts; ++ ++ req = container_of(_req, struct s3c_request, req); ++ if (unlikely(!_req || !_req->complete || !_req->buf || !list_empty(&req->queue))) { ++ ++ DEBUG("%s: bad params\n", __func__); ++ return -EINVAL; ++ } ++ ++ ep = container_of(_ep, struct s3c_ep, ep); ++ ++ if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) { ++ ++ DEBUG("%s: bad ep\n", __func__); ++ return -EINVAL; ++ } ++ ++ ep_num = ep_index(ep); ++ dev = ep->dev; ++ if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) { ++ ++ DEBUG("%s: bogus device state %p\n", __func__, dev->driver); ++ return -ESHUTDOWN; ++ } ++ ++ spin_lock_irqsave(&dev->lock, flags); ++ ++ _req->status = -EINPROGRESS; ++ _req->actual = 0; ++ ++ /* kickstart this i/o queue? */ ++ DEBUG("\n*** %s: %s-%s req = %p, len = %d, buf = %p" ++ "Q empty = %d, stopped = %d\n", ++ __func__,_ep->name, ep_is_in(ep)? "in" : "out", ++ _req, _req->length,_req->buf, ++ list_empty(&ep->queue), ep->stopped); ++ ++ if (list_empty(&ep->queue) && !ep->stopped) { ++ ++ if (ep_num == 0) { ++ /* EP0 */ ++ list_add_tail(&req->queue, &ep->queue); ++ s3c_ep0_kick(dev, ep); ++ req = 0; ++ ++ } else if (ep_is_in(ep)) { ++ gintsts = readl(S3C_UDC_OTG_GINTSTS); ++ DEBUG_IN_EP("%s: ep_is_in, S3C_UDC_OTG_GINTSTS=0x%x\n", ++ __func__, gintsts); ++ ++ if (set_conf_done == 1) { ++ setdma_tx(ep, req); ++ } else { ++ done(ep, req, 0); ++ DEBUG("%s: Not yet Set_configureation, ep_num = %d, req = %p\n", ++ __func__, ep_num, req); ++ req = 0; ++ } ++ ++ } else { ++ gintsts = readl(S3C_UDC_OTG_GINTSTS); ++ DEBUG_OUT_EP("%s: ep_is_out, S3C_UDC_OTG_GINTSTS=0x%x\n", ++ __func__, gintsts); ++ ++ setdma_rx(ep, req); ++ } ++ } ++ ++ /* pio or dma irq handler advances the queue. */ ++ if (likely(req != 0)) { ++ list_add_tail(&req->queue, &ep->queue); ++ } ++ ++ spin_unlock_irqrestore(&dev->lock, flags); ++ ++ return 0; ++} ++ ++/****************************************************************/ ++/* End Point 0 related functions */ ++/****************************************************************/ ++ ++/* return: 0 = still running, 1 = completed, negative = errno */ ++static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req) ++{ ++ u32 max; ++ unsigned count; ++ int is_last; ++ ++ max = ep_maxpacket(ep); ++ ++ DEBUG_EP0("%s: max = %d\n", __func__, max); ++ ++ count = setdma_tx(ep, req); ++ ++ /* last packet is usually short (or a zlp) */ ++ if (likely(count != max)) ++ is_last = 1; ++ else { ++ if (likely(req->req.length != req->req.actual) || req->req.zero) ++ is_last = 0; ++ else ++ is_last = 1; ++ } ++ ++ DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __func__, ++ ep->ep.name, count, ++ is_last ? "/L" : "", req->req.length - req->req.actual, req); ++ ++ /* requests complete when all IN data is in the FIFO */ ++ if (is_last) { ++ ep->dev->ep0state = WAIT_FOR_SETUP; ++ return 1; ++ } ++ ++ return 0; ++} ++ ++static __inline__ int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max) ++{ ++ u32 bytes; ++ ++ bytes = sizeof(struct usb_ctrlrequest); ++ dma_cache_maint(&usb_ctrl, bytes, DMA_FROM_DEVICE); ++ DEBUG_EP0("%s: bytes=%d, ep_index=%d \n", __func__, bytes, ep_index(ep)); ++ ++ return bytes; ++} ++ ++/** ++ * udc_set_address - set the USB address for this device ++ * @address: ++ * ++ * Called from control endpoint function ++ * after it decodes a set address setup packet. ++ */ ++static void udc_set_address(struct s3c_udc *dev, unsigned char address) ++{ ++ u32 ctrl = readl(S3C_UDC_OTG_DCFG); ++ writel(address << 4 | ctrl, S3C_UDC_OTG_DCFG); ++ ++ s3c_udc_ep0_zlp(); ++ ++ DEBUG_EP0("%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n", ++ __func__, address, readl(S3C_UDC_OTG_DCFG)); ++ ++ dev->usb_address = address; ++} ++ ++static inline void s3c_udc_ep0_set_stall(struct s3c_ep *ep) ++{ ++ struct s3c_udc *dev; ++ u32 ep_ctrl = 0; ++ ++ dev = ep->dev; ++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL(EP0_CON)); ++ ++ /* set the disable and stall bits */ ++ if (ep_ctrl & DEPCTL_EPENA) { ++ ep_ctrl |= DEPCTL_EPDIS; ++ } ++ ep_ctrl |= DEPCTL_STALL; ++ ++ writel(ep_ctrl, S3C_UDC_OTG_DIEPCTL(EP0_CON)); ++ ++ DEBUG_EP0("%s: set ep%d stall, DIEPCTL0 = 0x%x\n", ++ __func__, ep_index(ep), readl(S3C_UDC_OTG_DIEPCTL(EP0_CON))); ++ /* ++ * The application can only set this bit, and the core clears it, ++ * when a SETUP token is received for this endpoint ++ */ ++ dev->ep0state = WAIT_FOR_SETUP; ++ ++ s3c_udc_pre_setup(); ++} ++ ++static void s3c_ep0_read(struct s3c_udc *dev) ++{ ++ struct s3c_request *req; ++ struct s3c_ep *ep = &dev->ep[0]; ++ int ret; ++ ++ if (!list_empty(&ep->queue)) { ++ req = list_entry(ep->queue.next, struct s3c_request, queue); ++ ++ } else { ++ DEBUG("%s: ---> BUG\n", __func__); ++ BUG(); ++ return; ++ } ++ ++ DEBUG_EP0("%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n", ++ __func__, req, req->req.length, req->req.actual); ++ ++ if(req->req.length == 0) { ++ /* zlp for Set_configuration, Set_interface, ++ * or Bulk-Only mass storge reset */ ++ ++ dev->ep0state = WAIT_FOR_SETUP; ++ set_conf_done = 1; ++ s3c_udc_ep0_zlp(); ++ done(ep, req, 0); ++ ++ DEBUG_EP0("%s: req.length = 0, bRequest = %d\n", __func__, usb_ctrl.bRequest); ++ return; ++ } ++ ++ ret = setdma_rx(ep, req); ++} ++ ++/* ++ * DATA_STATE_XMIT ++ */ ++static int s3c_ep0_write(struct s3c_udc *dev) ++{ ++ struct s3c_request *req; ++ struct s3c_ep *ep = &dev->ep[0]; ++ int ret, need_zlp = 0; ++ ++ if (list_empty(&ep->queue)) { ++ req = 0; ++ ++ } else { ++ req = list_entry(ep->queue.next, struct s3c_request, queue); ++ } ++ ++ if (!req) { ++ DEBUG_EP0("%s: NULL REQ\n", __func__); ++ return 0; ++ } ++ ++ DEBUG_EP0("%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n", ++ __func__, req, req->req.length, req->req.actual); ++ ++ if (req->req.length - req->req.actual == ep0_fifo_size) { ++ /* Next write will end with the packet size, */ ++ /* so we need Zero-length-packet */ ++ need_zlp = 1; ++ } ++ ++ ret = write_fifo_ep0(ep, req); ++ ++ if ((ret == 1) && !need_zlp) { ++ /* Last packet */ ++ dev->ep0state = WAIT_FOR_SETUP; ++ DEBUG_EP0("%s: finished, waiting for status\n", __func__); ++ ++ } else { ++ dev->ep0state = DATA_STATE_XMIT; ++ DEBUG_EP0("%s: not finished\n", __func__); ++ } ++ ++ if (need_zlp) { ++ dev->ep0state = DATA_STATE_NEED_ZLP; ++ DEBUG_EP0("%s: Need ZLP!\n", __func__); ++ } ++ ++ return 1; ++} ++ ++u16 g_status; ++ ++static int s3c_udc_get_status(struct s3c_udc *dev, ++ struct usb_ctrlrequest *crq) ++{ ++ u8 ep_num = crq->wIndex & 0x7F; ++ u32 ep_ctrl; ++ ++ DEBUG_SETUP("%s: *** USB_REQ_GET_STATUS \n",__func__); ++ ++ switch (crq->bRequestType & USB_RECIP_MASK) { ++ case USB_RECIP_INTERFACE: ++ g_status = 0; ++ DEBUG_SETUP("\tGET_STATUS: USB_RECIP_INTERFACE, g_stauts = %d\n", g_status); ++ break; ++ ++ case USB_RECIP_DEVICE: ++ g_status = 0x1; /* Self powered */ ++ DEBUG_SETUP("\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n", g_status); ++ break; ++ ++ case USB_RECIP_ENDPOINT: ++ if (ep_num > 4 || crq->wLength > 2) { ++ DEBUG_SETUP("\tGET_STATUS: Not support EP or wLength\n"); ++ return 1; ++ } ++ ++ g_status = dev->ep[ep_num].stopped; ++ DEBUG_SETUP("\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n", g_status); ++ ++ break; ++ ++ default: ++ return 1; ++ } ++ ++ dma_cache_maint(&g_status, 2, DMA_TO_DEVICE); ++ ++ writel(virt_to_phys(&g_status), S3C_UDC_OTG_DIEPDMA(EP0_CON)); ++ writel((1<<19)|(2<<0), S3C_UDC_OTG_DIEPTSIZ(EP0_CON)); ++ ++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL(EP0_CON)); ++ writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK, S3C_UDC_OTG_DIEPCTL(EP0_CON)); ++ dev->ep0state = WAIT_FOR_SETUP; ++ ++ return 0; ++} ++ ++void s3c_udc_ep_set_stall(struct s3c_ep *ep) ++{ ++ u8 ep_num; ++ u32 ep_ctrl = 0; ++ ++ ep_num = ep_index(ep); ++ DEBUG("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type); ++ ++ if (ep_is_in(ep)) { ++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL(ep_num)); ++ ++ /* set the disable and stall bits */ ++ if (ep_ctrl & DEPCTL_EPENA) { ++ ep_ctrl |= DEPCTL_EPDIS; ++ } ++ ep_ctrl |= DEPCTL_STALL; ++ ++ writel(ep_ctrl, S3C_UDC_OTG_DIEPCTL(ep_num)); ++ DEBUG("%s: set stall, DIEPCTL%d = 0x%x\n", ++ __func__, ep_num, readl(S3C_UDC_OTG_DIEPCTL(ep_num))); ++ ++ } else { ++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL(ep_num)); ++ ++ /* set the stall bit */ ++ ep_ctrl |= DEPCTL_STALL; ++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL(ep_num)); ++ ++ writel(ep_ctrl, S3C_UDC_OTG_DOEPCTL(ep_num)); ++ DEBUG("%s: set stall, DOEPCTL%d = 0x%x\n", ++ __func__, ep_num, readl(S3C_UDC_OTG_DOEPCTL(ep_num))); ++ } ++ ++ return; ++} ++ ++void s3c_udc_ep_clear_stall(struct s3c_ep *ep) ++{ ++ u8 ep_num; ++ u32 ep_ctrl = 0; ++ ++ ep_num = ep_index(ep); ++ DEBUG("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type); ++ ++ if (ep_is_in(ep)) { ++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL(ep_num)); ++ ++ /* clear stall bit */ ++ ep_ctrl &= ~DEPCTL_STALL; ++ ++ /* ++ * USB Spec 9.4.5: For endpoints using data toggle, regardless ++ * of whether an endpoint has the Halt feature set, a ++ * ClearFeature(ENDPOINT_HALT) request always results in the ++ * data toggle being reinitialized to DATA0. ++ */ ++ if (ep->bmAttributes == USB_ENDPOINT_XFER_INT ++ || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) { ++ ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */ ++ } ++ ++ writel(ep_ctrl, S3C_UDC_OTG_DIEPCTL(ep_num)); ++ DEBUG("%s: cleared stall, DIEPCTL%d = 0x%x\n", ++ __func__, ep_num, readl(S3C_UDC_OTG_DIEPCTL(ep_num))); ++ ++ } else { ++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL(ep_num)); ++ ++ /* clear stall bit */ ++ ep_ctrl &= ~DEPCTL_STALL; ++ ++ if (ep->bmAttributes == USB_ENDPOINT_XFER_INT ++ || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) { ++ ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */ ++ } ++ ++ writel(ep_ctrl, S3C_UDC_OTG_DOEPCTL(ep_num)); ++ DEBUG("%s: cleared stall, DOEPCTL%d = 0x%x\n", ++ __func__, ep_num, readl(S3C_UDC_OTG_DOEPCTL(ep_num))); ++ } ++ ++ return; ++} ++ ++static int s3c_udc_set_halt(struct usb_ep *_ep, int value) ++{ ++ struct s3c_ep *ep; ++ struct s3c_udc *dev; ++ unsigned long flags; ++ u8 ep_num; ++ ++ ep = container_of(_ep, struct s3c_ep, ep); ++ ++ if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name) || ++ ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) { ++ DEBUG("%s: %s bad ep or descriptor\n", __func__, ep->ep.name); ++ return -EINVAL; ++ } ++ ++ /* Attempt to halt IN ep will fail if any transfer requests ++ * are still queue */ ++ if (value && ep_is_in(ep) && !list_empty(&ep->queue)) { ++ DEBUG("%s: %s queue not empty, req = %p\n", ++ __func__, ep->ep.name, ++ list_entry(ep->queue.next, struct s3c_request, queue)); ++ ++ return -EAGAIN; ++ } ++ ++ dev = ep->dev; ++ ep_num = ep_index(ep); ++ DEBUG("%s: ep_num = %d, value = %d\n", __func__, ep_num, value); ++ ++ spin_lock_irqsave(&dev->lock, flags); ++ ++ if (value == 0) { ++ ep->stopped = 0; ++ s3c_udc_ep_clear_stall(ep); ++ } else { ++ if (ep_num == 0) { ++ dev->ep0state = WAIT_FOR_SETUP; ++ } ++ ++ ep->stopped = 1; ++ s3c_udc_ep_set_stall(ep); ++ } ++ ++ spin_unlock_irqrestore(&dev->lock, flags); ++ ++ return 0; ++} ++ ++void s3c_udc_ep_activate(struct s3c_ep *ep) ++{ ++ u8 ep_num; ++ u32 ep_ctrl = 0, daintmsk = 0; ++ ++ ep_num = ep_index(ep); ++ ++ /* Read DEPCTLn register */ ++ if (ep_is_in(ep)) { ++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL(ep_num)); ++ daintmsk = 1 << ep_num; ++ } else { ++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL(ep_num)); ++ daintmsk = (1 << ep_num) << DAINT_OUT_BIT; ++ } ++ ++ DEBUG("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n", ++ __func__, ep_num, ep_ctrl, ep_is_in(ep)); ++ ++ /* If the EP is already active don't change the EP Control ++ * register. */ ++ if (!(ep_ctrl & DEPCTL_USBACTEP)) { ++ ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK)| (ep->bmAttributes << DEPCTL_TYPE_BIT); ++ ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) | (ep->ep.maxpacket << DEPCTL_MPS_BIT); ++ ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP); ++ ++ if (ep_is_in(ep)) { ++ writel(ep_ctrl, S3C_UDC_OTG_DIEPCTL(ep_num)); ++ DEBUG("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n", ++ __func__, ep_num, ep_num, readl(S3C_UDC_OTG_DIEPCTL(ep_num))); ++ } else { ++ writel(ep_ctrl, S3C_UDC_OTG_DOEPCTL(ep_num)); ++ DEBUG("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n", ++ __func__, ep_num, ep_num, readl(S3C_UDC_OTG_DOEPCTL(ep_num))); ++ } ++ } ++ ++ /* Unmask EP Interrtupt */ ++ writel(readl(S3C_UDC_OTG_DAINTMSK)|daintmsk, S3C_UDC_OTG_DAINTMSK); ++ DEBUG("%s: DAINTMSK = 0x%x\n", __func__, readl(S3C_UDC_OTG_DAINTMSK)); ++ ++} ++ ++static int s3c_udc_clear_feature(struct usb_ep *_ep) ++{ ++ struct s3c_ep *ep; ++ u8 ep_num; ++ ++ ep = container_of(_ep, struct s3c_ep, ep); ++ ep_num = ep_index(ep); ++ ++ DEBUG_SETUP("%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n", ++ __func__, ep_num, ep_is_in(ep), clear_feature_flag); ++ ++ if (usb_ctrl.wLength != 0) { ++ DEBUG_SETUP("\tCLEAR_FEATURE: wLength is not zero.....\n"); ++ return 1; ++ } ++ ++ switch (usb_ctrl.bRequestType & USB_RECIP_MASK) { ++ case USB_RECIP_DEVICE: ++ switch (usb_ctrl.wValue) { ++ case USB_DEVICE_REMOTE_WAKEUP: ++ DEBUG_SETUP("\tCLEAR_FEATURE: USB_DEVICE_REMOTE_WAKEUP\n"); ++ break; ++ ++ case USB_DEVICE_TEST_MODE: ++ DEBUG_SETUP("\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n"); ++ /** @todo Add CLEAR_FEATURE for TEST modes. */ ++ break; ++ } ++ ++ s3c_udc_ep0_zlp(); ++ break; ++ ++ case USB_RECIP_ENDPOINT: ++ DEBUG_SETUP("\tCLEAR_FEATURE: USB_RECIP_ENDPOINT, wValue = %d\n", ++ usb_ctrl.wValue); ++ ++ if (usb_ctrl.wValue == USB_ENDPOINT_HALT) { ++ if (ep == 0) { ++ s3c_udc_ep0_set_stall(ep); ++ return 0; ++ } ++ ++ s3c_udc_ep0_zlp(); ++ ++ s3c_udc_ep_clear_stall(ep); ++ s3c_udc_ep_activate(ep); ++ ep->stopped = 0; ++ ++ clear_feature_num = ep_num; ++ clear_feature_flag = 1; ++ } ++ break; ++ } ++ ++ return 0; ++} ++ ++static int s3c_udc_set_feature(struct usb_ep *_ep) ++{ ++ struct s3c_ep *ep; ++ u8 ep_num; ++ ++ ep = container_of(_ep, struct s3c_ep, ep); ++ ep_num = ep_index(ep); ++ ++ DEBUG_SETUP("%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",__func__, ep_num); ++ ++ if (usb_ctrl.wLength != 0) { ++ DEBUG_SETUP("\tSET_FEATURE: wLength is not zero.....\n"); ++ return 1; ++ } ++ ++ switch (usb_ctrl.bRequestType & USB_RECIP_MASK) { ++ case USB_RECIP_DEVICE: ++ switch (usb_ctrl.wValue) { ++ case USB_DEVICE_REMOTE_WAKEUP: ++ DEBUG_SETUP("\tSET_FEATURE: USB_DEVICE_REMOTE_WAKEUP\n"); ++ break; ++ ++ case USB_DEVICE_TEST_MODE: ++ DEBUG_SETUP("\tSET_FEATURE: USB_DEVICE_TEST_MODE\n"); ++ break; ++ ++ case USB_DEVICE_B_HNP_ENABLE: ++ DEBUG_SETUP("\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n"); ++ break; ++ ++ case USB_DEVICE_A_HNP_SUPPORT: ++ /* RH port supports HNP */ ++ DEBUG_SETUP("\tSET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n"); ++ break; ++ ++ case USB_DEVICE_A_ALT_HNP_SUPPORT: ++ /* other RH port does */ ++ DEBUG_SETUP("\tSET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n"); ++ break; ++ } ++ ++ s3c_udc_ep0_zlp(); ++ return 0; ++ ++ case USB_RECIP_INTERFACE: ++ DEBUG_SETUP("\tSET_FEATURE: USB_RECIP_INTERFACE\n"); ++ break; ++ ++ case USB_RECIP_ENDPOINT: ++ DEBUG_SETUP("\tSET_FEATURE: USB_RECIP_ENDPOINT\n"); ++ if (usb_ctrl.wValue == USB_ENDPOINT_HALT) { ++ if (ep_num == 0) { ++ s3c_udc_ep0_set_stall(ep); ++ return 0; ++ } ++ ep->stopped = 1; ++ s3c_udc_ep_set_stall(ep); ++ } ++ ++ s3c_udc_ep0_zlp(); ++ return 0; ++ } ++ ++ return 1; ++} ++ ++/* ++ * WAIT_FOR_SETUP (OUT_PKT_RDY) ++ */ ++static void s3c_ep0_setup(struct s3c_udc *dev) ++{ ++ struct s3c_ep *ep = &dev->ep[0]; ++ int i, bytes, is_in; ++ u8 ep_num; ++ ++ /* Nuke all previous transfers */ ++ nuke(ep, -EPROTO); ++ ++ /* read control req from fifo (8 bytes) */ ++ bytes = s3c_fifo_read(ep, (u32 *)&usb_ctrl, 8); ++ ++ DEBUG_SETUP("%s: bRequestType = 0x%x(%s), bRequest = 0x%x" ++ "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n", ++ __func__, usb_ctrl.bRequestType, ++ (usb_ctrl.bRequestType & USB_DIR_IN) ? "IN" : "OUT", usb_ctrl.bRequest, ++ usb_ctrl.wLength, usb_ctrl.wValue, usb_ctrl.wIndex); ++ ++ if (usb_ctrl.bRequest == GET_MAX_LUN_REQUEST && usb_ctrl.wLength != 1) { ++ DEBUG_SETUP("\t%s:GET_MAX_LUN_REQUEST:invalid wLength = %d, setup returned\n", ++ __func__, usb_ctrl.wLength); ++ ++ s3c_udc_ep0_set_stall(ep); ++ dev->ep0state = WAIT_FOR_SETUP; ++ ++ return; ++ } ++ else if (usb_ctrl.bRequest == BOT_RESET_REQUEST && usb_ctrl.wLength != 0) { ++ /* Bulk-Only *mass storge reset of class-specific request */ ++ DEBUG_SETUP("\t%s:BOT Rest:invalid wLength = %d, setup returned\n", ++ __func__, usb_ctrl.wLength); ++ ++ s3c_udc_ep0_set_stall(ep); ++ dev->ep0state = WAIT_FOR_SETUP; ++ ++ return; ++ } ++ ++ /* Set direction of EP0 */ ++ if (likely(usb_ctrl.bRequestType & USB_DIR_IN)) { ++ ep->bEndpointAddress |= USB_DIR_IN; ++ is_in = 1; ++ ++ } else { ++ ep->bEndpointAddress &= ~USB_DIR_IN; ++ is_in = 0; ++ } ++ /* cope with automagic for some standard requests. */ ++ dev->req_std = (usb_ctrl.bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD; ++ dev->req_config = 0; ++ dev->req_pending = 1; ++ ++ /* Handle some SETUP packets ourselves */ ++ switch (usb_ctrl.bRequest) { ++ case USB_REQ_SET_ADDRESS: ++ DEBUG_SETUP("%s: *** USB_REQ_SET_ADDRESS (%d)\n", ++ __func__, usb_ctrl.wValue); ++ ++ if (usb_ctrl.bRequestType ++ != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) ++ break; ++ ++ udc_set_address(dev, usb_ctrl.wValue); ++ return; ++ ++ case USB_REQ_SET_CONFIGURATION : ++ DEBUG_SETUP("============================================\n"); ++ DEBUG_SETUP("%s: USB_REQ_SET_CONFIGURATION (%d)\n", ++ __func__, usb_ctrl.wValue); ++ ++ if (usb_ctrl.bRequestType == USB_RECIP_DEVICE) { ++ reset_available = 1; ++ dev->req_config = 1; ++ } ++ break; ++ ++ case USB_REQ_GET_DESCRIPTOR: ++ DEBUG_SETUP("%s: *** USB_REQ_GET_DESCRIPTOR \n",__func__); ++ break; ++ ++ case USB_REQ_SET_INTERFACE: ++ DEBUG_SETUP("%s: *** USB_REQ_SET_INTERFACE (%d)\n", ++ __func__, usb_ctrl.wValue); ++ ++ if (usb_ctrl.bRequestType == USB_RECIP_INTERFACE) { ++ reset_available = 1; ++ dev->req_config = 1; ++ } ++ break; ++ ++ case USB_REQ_GET_CONFIGURATION: ++ DEBUG_SETUP("%s: *** USB_REQ_GET_CONFIGURATION \n",__func__); ++ break; ++ ++ case USB_REQ_GET_STATUS: ++ if (dev->req_std) { ++ if (!s3c_udc_get_status(dev, &usb_ctrl)) { ++ return; ++ } ++ } ++ break; ++ ++ case USB_REQ_CLEAR_FEATURE: ++ ep_num = usb_ctrl.wIndex & 0x7f; ++ ++ if (!s3c_udc_clear_feature(&dev->ep[ep_num].ep)) { ++ return; ++ } ++ break; ++ ++ case USB_REQ_SET_FEATURE: ++ ep_num = usb_ctrl.wIndex & 0x7f; ++ ++ if (!s3c_udc_set_feature(&dev->ep[ep_num].ep)) { ++ return; ++ } ++ break; ++ ++ default: ++ DEBUG_SETUP("%s: *** Default of usb_ctrl.bRequest=0x%x happened.\n", ++ __func__, usb_ctrl.bRequest); ++ break; ++ } ++ ++ if (likely(dev->driver)) { ++ /* device-2-host (IN) or no data setup command, ++ * process immediately */ ++ DEBUG_SETUP("%s: usb_ctrlrequest will be passed to fsg_setup()\n", __func__); ++ ++ spin_unlock(&dev->lock); ++ i = dev->driver->setup(&dev->gadget, &usb_ctrl); ++ spin_lock(&dev->lock); ++ ++ if (i < 0) { ++ if (dev->req_config) { ++ DEBUG_SETUP("\tconfig change 0x%02x fail %d?\n", ++ (u32)&usb_ctrl.bRequest, i); ++ return; ++ } ++ ++ /* setup processing failed, force stall */ ++ s3c_udc_ep0_set_stall(ep); ++ dev->ep0state = WAIT_FOR_SETUP; ++ ++ DEBUG_SETUP("\tdev->driver->setup failed (%d), bRequest = %d\n", ++ i, usb_ctrl.bRequest); ++ ++ ++ } else if (dev->req_pending) { ++ dev->req_pending = 0; ++ DEBUG_SETUP("\tdev->req_pending... \n"); ++ } ++ ++ DEBUG_SETUP("\tep0state = %s\n", state_names[dev->ep0state]); ++ ++ } ++} ++ ++/* ++ * handle ep0 interrupt ++ */ ++static void s3c_handle_ep0(struct s3c_udc *dev) ++{ ++ if (dev->ep0state == WAIT_FOR_SETUP) { ++ DEBUG_OUT_EP("%s: WAIT_FOR_SETUP\n", __func__); ++ s3c_ep0_setup(dev); ++ ++ } else { ++ DEBUG_OUT_EP("%s: strange state!!(state = %s)\n", ++ __func__, state_names[dev->ep0state]); ++ } ++} ++ ++static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep) ++{ ++ DEBUG_EP0("%s: ep_is_in = %d\n", __func__, ep_is_in(ep)); ++ if (ep_is_in(ep)) { ++ dev->ep0state = DATA_STATE_XMIT; ++ s3c_ep0_write(dev); ++ ++ } else { ++ dev->ep0state = DATA_STATE_RECV; ++ s3c_ep0_read(dev); ++ } ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/gadget/s3c_udc_otg_xfer_slave.c linux-2.6.28.6/drivers/usb/gadget/s3c_udc_otg_xfer_slave.c +--- linux-2.6.28/drivers/usb/gadget/s3c_udc_otg_xfer_slave.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/gadget/s3c_udc_otg_xfer_slave.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,971 @@ ++/* ++ * drivers/usb/gadget/s3c_udc_otg_xfer_slave.c ++ * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers ++ * ++ * Copyright (C) 2009 for Samsung Electronics ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#define GINTMSK_INIT (INT_RESUME|INT_ENUMDONE|INT_RESET|INT_SUSPEND|INT_RX_FIFO_NOT_EMPTY) ++#define DOEPMSK_INIT (AHB_ERROR) ++#define DIEPMSK_INIT (NON_ISO_IN_EP_TIMEOUT|AHB_ERROR) ++#define GAHBCFG_INIT (PTXFE_HALF|NPTXFE_HALF|MODE_SLAVE|BURST_SINGLE|GBL_INT_UNMASK) ++ ++u32 tx_ep_num = 2; ++ ++static int set_interface_first = 0; ++ ++/*-------------------------------------------------------------------------*/ ++ ++/** Read to request from FIFO (max read == bytes in fifo) ++ * Return: 0 = still running, 1 = completed, negative = errno ++ */ ++static int read_fifo(struct s3c_ep *ep, struct s3c_request *req) ++{ ++ u32 csr, gintmsk; ++ u32 *buf; ++ u32 bufferspace, count, count_bytes, is_short = 0; ++ u32 fifo = ep->fifo; ++ ++ csr = readl(S3C_UDC_OTG_GRXSTSP); ++ count_bytes = (csr & 0x7ff0)>>4; ++ ++ gintmsk = readl(S3C_UDC_OTG_GINTMSK); ++ ++ if(!count_bytes) { ++ DEBUG_OUT_EP("%s: count_bytes %d bytes\n", __FUNCTION__, count_bytes); ++ ++ // Unmask USB OTG 2.0 interrupt source : INT_RX_FIFO_NOT_EMPTY ++ writel(gintmsk | INT_RX_FIFO_NOT_EMPTY, S3C_UDC_OTG_GINTMSK); ++ return 0; ++ } ++ ++ buf = req->req.buf + req->req.actual; ++ prefetchw(buf); ++ bufferspace = req->req.length - req->req.actual; ++ ++ count = count_bytes / 4; ++ if(count_bytes%4) count = count + 1; ++ ++ req->req.actual += min(count_bytes, bufferspace); ++ ++ is_short = (count_bytes < ep->ep.maxpacket); ++ DEBUG_OUT_EP("%s: read %s, %d bytes%s req %p %d/%d GRXSTSP:0x%x\n", ++ __FUNCTION__, ++ ep->ep.name, count_bytes, ++ is_short ? "/S" : "", req, req->req.actual, req->req.length, csr); ++ ++ while (likely(count-- != 0)) { ++ u32 byte = (u32) readl(fifo); ++ ++ if (unlikely(bufferspace == 0)) { ++ /* this happens when the driver's buffer ++ * is smaller than what the host sent. ++ * discard the extra data. ++ */ ++ if (req->req.status != -EOVERFLOW) ++ printk("%s overflow %d\n", ep->ep.name, count); ++ req->req.status = -EOVERFLOW; ++ } else { ++ *buf++ = byte; ++ bufferspace-=4; ++ } ++ } ++ ++ // Unmask USB OTG 2.0 interrupt source : INT_RX_FIFO_NOT_EMPTY ++ writel(gintmsk | INT_RX_FIFO_NOT_EMPTY, S3C_UDC_OTG_GINTMSK); ++ ++ /* completion */ ++ if (is_short || req->req.actual == req->req.length) { ++ done(ep, req, 0); ++ return 1; ++ } ++ ++ /* finished that packet. the next one may be waiting... */ ++ return 0; ++} ++ ++/* Inline code */ ++static __inline__ int write_packet(struct s3c_ep *ep, ++ struct s3c_request *req, int max) ++{ ++ u32 *buf; ++ int length, count; ++ u32 fifo = ep->fifo, in_ctrl; ++ ++ buf = req->req.buf + req->req.actual; ++ prefetch(buf); ++ ++ length = req->req.length - req->req.actual; ++ length = min(length, max); ++ req->req.actual += length; ++ ++ DEBUG("%s: Write %d (max %d), fifo=0x%x\n", ++ __FUNCTION__, length, max, fifo); ++ ++ if(ep_index(ep) == EP0_CON) { ++ writel((1<<19)|(length<<0), (u32) S3C_UDC_OTG_DIEPTSIZ0); ++ ++ in_ctrl = readl(S3C_UDC_OTG_DIEPCTL0); ++ writel(DEPCTL_EPENA|DEPCTL_CNAK|(EP2_IN<<11)| in_ctrl, (u32) S3C_UDC_OTG_DIEPCTL0); ++ ++ DEBUG_EP0("%s:(DIEPTSIZ0):0x%x, (DIEPCTL0):0x%x, (GNPTXSTS):0x%x\n", __FUNCTION__, ++ readl(S3C_UDC_OTG_DIEPTSIZ0),readl(S3C_UDC_OTG_DIEPCTL0), ++ readl(S3C_UDC_OTG_GNPTXSTS)); ++ ++ udelay(30); ++ ++ } else if ((ep_index(ep) == EP2_IN)) { ++ writel((1<<19)|(length<<0), S3C_UDC_OTG_DIEPTSIZ2); ++ ++ in_ctrl = readl(S3C_UDC_OTG_DIEPCTL2); ++ writel(DEPCTL_EPENA|DEPCTL_CNAK|(EP2_IN<<11)| in_ctrl, (u32) S3C_UDC_OTG_DIEPCTL2); ++ ++ DEBUG_IN_EP("%s:(DIEPTSIZ2):0x%x, (DIEPCTL2):0x%x, (GNPTXSTS):0x%x\n", __FUNCTION__, ++ readl(S3C_UDC_OTG_DIEPTSIZ2),readl(S3C_UDC_OTG_DIEPCTL2), ++ readl(S3C_UDC_OTG_GNPTXSTS)); ++ ++ udelay(30); ++ ++ } else if ((ep_index(ep) == EP3_IN)) { ++ ++ if (set_interface_first == 1) { ++ DEBUG_IN_EP("%s: first packet write skipped after set_interface\n", __FUNCTION__); ++ set_interface_first = 0; ++ return length; ++ } ++ ++ writel((1<<19)|(length<<0), S3C_UDC_OTG_DIEPTSIZ3); ++ ++ in_ctrl = readl(S3C_UDC_OTG_DIEPCTL3); ++ writel(DEPCTL_EPENA|DEPCTL_CNAK|(EP2_IN<<11)| in_ctrl, (u32) S3C_UDC_OTG_DIEPCTL3); ++ ++ DEBUG_IN_EP("%s:(DIEPTSIZ3):0x%x, (DIEPCTL3):0x%x, (GNPTXSTS):0x%x\n", __FUNCTION__, ++ readl(S3C_UDC_OTG_DIEPTSIZ3),readl(S3C_UDC_OTG_DIEPCTL3), ++ readl(S3C_UDC_OTG_GNPTXSTS)); ++ ++ udelay(30); ++ ++ } else { ++ printk("%s: --> Error Unused Endpoint!!\n", ++ __FUNCTION__); ++ BUG(); ++ } ++ ++ for (count=0;countdesc->wMaxPacketSize); ++ count = write_packet(ep, req, max); ++ ++ /* last packet is usually short (or a zlp) */ ++ if (unlikely(count != max)) ++ is_last = is_short = 1; ++ else { ++ if (likely(req->req.length != req->req.actual) ++ || req->req.zero) ++ is_last = 0; ++ else ++ is_last = 1; ++ /* interrupt/iso maxpacket may not fill the fifo */ ++ is_short = unlikely(max < ep_maxpacket(ep)); ++ } ++ ++ DEBUG_IN_EP("%s: wrote %s %d bytes%s%s req %p %d/%d\n", ++ __FUNCTION__, ++ ep->ep.name, count, ++ is_last ? "/L" : "", is_short ? "/S" : "", ++ req, req->req.actual, req->req.length); ++ ++ /* requests complete when all IN data is in the FIFO */ ++ if (is_last) { ++ if(!ep_index(ep)){ ++ printk("%s: --> Error EP0 must not come here!\n", ++ __FUNCTION__); ++ BUG(); ++ } ++ writel(gintmsk&(~INT_NP_TX_FIFO_EMPTY), S3C_UDC_OTG_GINTMSK); ++ done(ep, req, 0); ++ return 1; ++ } ++ ++ // Unmask USB OTG 2.0 interrupt source : INT_NP_TX_FIFO_EMPTY ++ writel(gintmsk | INT_NP_TX_FIFO_EMPTY, S3C_UDC_OTG_GINTMSK); ++ return 0; ++} ++ ++/* ********************************************************************************************* */ ++/* Bulk OUT (recv) ++ */ ++ ++static void s3c_out_epn(struct s3c_udc *dev, u32 ep_idx) ++{ ++ struct s3c_ep *ep = &dev->ep[ep_idx]; ++ struct s3c_request *req; ++ ++ if (unlikely(!(ep->desc))) { ++ /* Throw packet away.. */ ++ printk("%s: No descriptor?!?\n", __FUNCTION__); ++ return; ++ } ++ ++ if (list_empty(&ep->queue)) ++ req = 0; ++ else ++ req = list_entry(ep->queue.next, ++ struct s3c_request, queue); ++ ++ if (unlikely(!req)) { ++ DEBUG_OUT_EP("%s: NULL REQ on OUT EP-%d\n", __FUNCTION__, ep_idx); ++ return; ++ ++ } else { ++ read_fifo(ep, req); ++ } ++ ++} ++ ++/** ++ * s3c_in_epn - handle IN interrupt ++ */ ++static void s3c_in_epn(struct s3c_udc *dev, u32 ep_idx) ++{ ++ struct s3c_ep *ep = &dev->ep[ep_idx]; ++ struct s3c_request *req; ++ ++ if (list_empty(&ep->queue)) ++ req = 0; ++ else ++ req = list_entry(ep->queue.next, struct s3c_request, queue); ++ ++ if (unlikely(!req)) { ++ DEBUG_IN_EP("%s: NULL REQ on IN EP-%d\n", __FUNCTION__, ep_idx); ++ return; ++ } ++ else { ++ write_fifo(ep, req); ++ } ++ ++} ++ ++/* ++ * elfin usb client interrupt handler. ++ */ ++static irqreturn_t s3c_udc_irq(int irq, void *_dev) ++{ ++ struct s3c_udc *dev = _dev; ++ u32 intr_status; ++ u32 usb_status, ep_ctrl, gintmsk; ++ ++ spin_lock(&dev->lock); ++ ++ intr_status = readl(S3C_UDC_OTG_GINTSTS); ++ gintmsk = readl(S3C_UDC_OTG_GINTMSK); ++ ++ DEBUG_ISR("\n**** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x\n", ++ __FUNCTION__, intr_status, state_names[dev->ep0state], gintmsk); ++ ++ if (!intr_status) { ++ spin_unlock(&dev->lock); ++ return IRQ_HANDLED; ++ } ++ ++ if (intr_status & INT_ENUMDONE) { ++ DEBUG_SETUP("####################################\n"); ++ DEBUG_SETUP(" %s: Speed Detection interrupt\n", ++ __FUNCTION__); ++ writel(INT_ENUMDONE, S3C_UDC_OTG_GINTSTS); ++ ++ usb_status = (readl(S3C_UDC_OTG_DSTS) & 0x6); ++ ++ if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) { ++ DEBUG_SETUP(" %s: Full Speed Detection\n",__FUNCTION__); ++ set_max_pktsize(dev, USB_SPEED_FULL); ++ ++ } else { ++ DEBUG_SETUP(" %s: High Speed Detection : 0x%x\n", __FUNCTION__, usb_status); ++ set_max_pktsize(dev, USB_SPEED_HIGH); ++ } ++ } ++ ++ if (intr_status & INT_EARLY_SUSPEND) { ++ DEBUG_SETUP("####################################\n"); ++ DEBUG_SETUP(" %s:Early suspend interrupt\n", __FUNCTION__); ++ writel(INT_EARLY_SUSPEND, S3C_UDC_OTG_GINTSTS); ++ } ++ ++ if (intr_status & INT_SUSPEND) { ++ usb_status = readl(S3C_UDC_OTG_DSTS); ++ DEBUG_SETUP("####################################\n"); ++ DEBUG_SETUP(" %s:Suspend interrupt :(DSTS):0x%x\n", __FUNCTION__, usb_status); ++ writel(INT_SUSPEND, S3C_UDC_OTG_GINTSTS); ++ ++ if (dev->gadget.speed != USB_SPEED_UNKNOWN ++ && dev->driver ++ && dev->driver->suspend) { ++ ++ dev->driver->suspend(&dev->gadget); ++ } ++ } ++ ++ if (intr_status & INT_RESUME) { ++ DEBUG_SETUP("####################################\n"); ++ DEBUG_SETUP(" %s: Resume interrupt\n", __FUNCTION__); ++ writel(INT_RESUME, S3C_UDC_OTG_GINTSTS); ++ ++ if (dev->gadget.speed != USB_SPEED_UNKNOWN ++ && dev->driver ++ && dev->driver->resume) { ++ ++ dev->driver->resume(&dev->gadget); ++ } ++ } ++ ++ if (intr_status & INT_RESET) { ++ usb_status = readl(S3C_UDC_OTG_GOTGCTL); ++ DEBUG_SETUP("####################################\n"); ++ DEBUG_SETUP(" %s: Reset interrupt - (GOTGCTL):0x%x\n", __FUNCTION__, usb_status); ++ writel(INT_RESET, S3C_UDC_OTG_GINTSTS); ++ ++ if((usb_status & 0xc0000) == (0x3 << 18)) { ++ if(reset_available) { ++ DEBUG_SETUP(" ===> OTG core got reset (%d)!! \n", reset_available); ++ reconfig_usbd(); ++ dev->ep0state = WAIT_FOR_SETUP; ++ reset_available = 0; ++ } ++ } else { ++ reset_available = 1; ++ DEBUG_SETUP(" RESET handling skipped : reset_available : %d\n", reset_available); ++ } ++ } ++ ++ if (intr_status & INT_RX_FIFO_NOT_EMPTY) { ++ u32 grx_status, packet_status, ep_num, fifoCntByte = 0; ++ ++ // Mask USB OTG 2.0 interrupt source : INT_RX_FIFO_NOT_EMPTY ++ gintmsk &= ~INT_RX_FIFO_NOT_EMPTY; ++ writel(gintmsk, S3C_UDC_OTG_GINTMSK); ++ ++ grx_status = readl(S3C_UDC_OTG_GRXSTSR); ++ DEBUG_ISR(" INT_RX_FIFO_NOT_EMPTY(GRXSTSR):0x%x, GINTMSK:0x%x\n", grx_status, gintmsk); ++ ++ packet_status = grx_status & 0x1E0000; ++ fifoCntByte = (grx_status & 0x7ff0)>>4; ++ ep_num = grx_status & EP_MASK; ++ ++ if (fifoCntByte) { ++ ++ if (packet_status == SETUP_PKT_RECEIVED) { ++ DEBUG_EP0(" => A SETUP data packet received : %d bytes\n", fifoCntByte); ++ s3c_handle_ep0(dev); ++ ++ // Unmask USB OTG 2.0 interrupt source : INT_RX_FIFO_NOT_EMPTY ++ gintmsk |= INT_RX_FIFO_NOT_EMPTY; ++ ++ } else if (packet_status == OUT_PKT_RECEIVED) { ++ ++ if(ep_num == EP1_OUT) { ++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL1); ++ DEBUG_ISR(" => A Bulk OUT data packet received : %d bytes, (DOEPCTL1):0x%x\n", ++ fifoCntByte, ep_ctrl); ++ s3c_out_epn(dev, 1); ++ gintmsk = readl(S3C_UDC_OTG_GINTMSK); ++ writel(ep_ctrl | DEPCTL_CNAK, S3C_UDC_OTG_DOEPCTL1); ++ } else if (ep_num == EP0_CON) { ++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL0); ++ DEBUG_EP0(" => A CONTROL OUT data packet received : %d bytes, (DOEPCTL0):0x%x\n", ++ fifoCntByte, ep_ctrl); ++ dev->ep0state = DATA_STATE_RECV; ++ s3c_ep0_read(dev); ++ gintmsk |= INT_RX_FIFO_NOT_EMPTY; ++ } else { ++ DEBUG_ISR(" => Unused EP: %d bytes, (GRXSTSR):0x%x\n", fifoCntByte, grx_status); ++ } ++ } else { ++ grx_status = readl(S3C_UDC_OTG_GRXSTSP); ++ ++ // Unmask USB OTG 2.0 interrupt source : INT_RX_FIFO_NOT_EMPTY ++ gintmsk |= INT_RX_FIFO_NOT_EMPTY; ++ ++ DEBUG_ISR(" => A reserved packet received : %d bytes\n", fifoCntByte); ++ } ++ } else { ++ if (dev->ep0state == DATA_STATE_XMIT) { ++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL0); ++ DEBUG_EP0(" => Write ep0 continue... (DOEPCTL0):0x%x\n", ep_ctrl); ++ s3c_ep0_write(dev); ++ } ++ ++ if (packet_status == SETUP_TRANSACTION_COMPLETED) { ++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL0); ++ DEBUG_EP0(" => A SETUP transaction completed (DOEPCTL0):0x%x\n", ep_ctrl); ++ writel(ep_ctrl | DEPCTL_CNAK, S3C_UDC_OTG_DOEPCTL0); ++ ++ } else if (packet_status == OUT_TRANSFER_COMPLELTED) { ++ if (ep_num == EP1_OUT) { ++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL1); ++ DEBUG_ISR(" => An OUT transaction completed (DOEPCTL1):0x%x\n", ep_ctrl); ++ writel(ep_ctrl | DEPCTL_CNAK, S3C_UDC_OTG_DOEPCTL1); ++ } else if (ep_num == EP0_CON) { ++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL0); ++ DEBUG_ISR(" => An OUT transaction completed (DOEPCTL0):0x%x\n", ep_ctrl); ++ writel(ep_ctrl | DEPCTL_CNAK, S3C_UDC_OTG_DOEPCTL0); ++ } else { ++ DEBUG_ISR(" => Unused EP: %d bytes, (GRXSTSR):0x%x\n", fifoCntByte, grx_status); ++ } ++ } else if (packet_status == OUT_PKT_RECEIVED) { ++ DEBUG_ISR(" => A OUT PACKET RECEIVED (NO FIFO CNT BYTE)...(GRXSTSR):0x%x\n", grx_status); ++ } else { ++ DEBUG_ISR(" => A RESERVED PACKET RECEIVED (NO FIFO CNT BYTE)...(GRXSTSR):0x%x\n", grx_status); ++ } ++ ++ grx_status = readl(S3C_UDC_OTG_GRXSTSP); ++ ++ // Unmask USB OTG 2.0 interrupt source : INT_RX_FIFO_NOT_EMPTY ++ gintmsk |= INT_RX_FIFO_NOT_EMPTY; ++ ++ } ++ ++ // Un/Mask USB OTG 2.0 interrupt sources ++ writel(gintmsk, S3C_UDC_OTG_GINTMSK); ++ ++ spin_unlock(&dev->lock); ++ return IRQ_HANDLED; ++ } ++ ++ ++ if (intr_status & INT_NP_TX_FIFO_EMPTY) { ++ DEBUG_ISR(" INT_NP_TX_FIFO_EMPTY (GNPTXSTS):0x%x, (GINTMSK):0x%x, ep_num=%d\n", ++ readl(S3C_UDC_OTG_GNPTXSTS), ++ readl(S3C_UDC_OTG_GINTMSK), ++ tx_ep_num); ++ ++ s3c_in_epn(dev, tx_ep_num); ++ } ++ ++ spin_unlock(&dev->lock); ++ ++ return IRQ_HANDLED; ++} ++ ++/** Queue one request ++ * Kickstart transfer if needed ++ */ ++static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req, ++ gfp_t gfp_flags) ++{ ++ struct s3c_request *req; ++ struct s3c_ep *ep; ++ struct s3c_udc *dev; ++ unsigned long flags; ++ ++ req = container_of(_req, struct s3c_request, req); ++ if (unlikely(!_req || !_req->complete || !_req->buf ++ || !list_empty(&req->queue))) ++ { ++ DEBUG("%s: bad params\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ ep = container_of(_ep, struct s3c_ep, ep); ++ if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) { ++ DEBUG("%s: bad ep\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ dev = ep->dev; ++ if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) { ++ DEBUG("%s: bogus device state %p\n", __FUNCTION__, dev->driver); ++ return -ESHUTDOWN; ++ } ++ ++ DEBUG("\n%s: %s queue req %p, len %d buf %p\n", ++ __FUNCTION__, _ep->name, _req, _req->length, _req->buf); ++ ++ spin_lock_irqsave(&dev->lock, flags); ++ ++ _req->status = -EINPROGRESS; ++ _req->actual = 0; ++ ++ /* kickstart this i/o queue? */ ++ DEBUG("%s: Add to ep=%d, Q empty=%d, stopped=%d\n", ++ __FUNCTION__, ep_index(ep), list_empty(&ep->queue), ep->stopped); ++ ++ if (list_empty(&ep->queue) && likely(!ep->stopped)) { ++ u32 csr; ++ ++ if (unlikely(ep_index(ep) == 0)) { ++ /* EP0 */ ++ list_add_tail(&req->queue, &ep->queue); ++ s3c_ep0_kick(dev, ep); ++ req = 0; ++ ++ } else if (ep_is_in(ep)) { ++ csr = readl((u32) S3C_UDC_OTG_GINTSTS); ++ DEBUG_IN_EP("%s: ep_is_in, S3C_UDC_OTG_GINTSTS=0x%x\n", ++ __FUNCTION__, csr); ++ ++ if((csr & INT_NP_TX_FIFO_EMPTY) && ++ (write_fifo(ep, req) == 1)) { ++ req = 0; ++ } else { ++ DEBUG("++++ IN-list_add_taill::req=%p, ep=%d\n", ++ req, ep_index(ep)); ++ tx_ep_num = ep_index(ep); ++ } ++ } else { ++ csr = readl((u32) S3C_UDC_OTG_GINTSTS); ++ DEBUG_OUT_EP("%s: ep_is_out, S3C_UDC_OTG_GINTSTS=0x%x\n", ++ __FUNCTION__, csr); ++ ++ if((csr & INT_RX_FIFO_NOT_EMPTY) && ++ (read_fifo(ep, req) == 1)) ++ req = 0; ++ else ++ DEBUG("++++ OUT-list_add_taill::req=%p, DOEPCTL1:0x%x\n", ++ req, readl(S3C_UDC_OTG_DOEPCTL1)); ++ } ++ } ++ ++ /* pio or dma irq handler advances the queue. */ ++ if (likely(req != 0)) ++ list_add_tail(&req->queue, &ep->queue); ++ ++ spin_unlock_irqrestore(&dev->lock, flags); ++ ++ return 0; ++} ++ ++/****************************************************************/ ++/* End Point 0 related functions */ ++/****************************************************************/ ++ ++/* return: 0 = still running, 1 = completed, negative = errno */ ++static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req) ++{ ++ u32 max; ++ unsigned count; ++ int is_last; ++ ++ max = ep_maxpacket(ep); ++ ++ DEBUG_EP0("%s: max = %d\n", __FUNCTION__, max); ++ ++ count = write_packet(ep, req, max); ++ ++ /* last packet is usually short (or a zlp) */ ++ if (likely(count != max)) ++ is_last = 1; ++ else { ++ if (likely(req->req.length != req->req.actual) || req->req.zero) ++ is_last = 0; ++ else ++ is_last = 1; ++ } ++ ++ DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__, ++ ep->ep.name, count, ++ is_last ? "/L" : "", req->req.length - req->req.actual, req); ++ ++ /* requests complete when all IN data is in the FIFO */ ++ if (is_last) { ++ return 1; ++ } ++ ++ return 0; ++} ++ ++static __inline__ int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max) ++{ ++ int bytes; ++ int count; ++ u32 grx_status = readl(S3C_UDC_OTG_GRXSTSP); ++ bytes = (grx_status & 0x7ff0)>>4; ++ ++ DEBUG_EP0("%s: GRXSTSP=0x%x, bytes=%d, ep_index=%d, fifo=0x%x\n", ++ __FUNCTION__, grx_status, bytes, ep_index(ep), ep->fifo); ++ ++ // 32 bits interface ++ count = bytes / 4; ++ ++ while (count--) { ++ *cp++ = (u32) readl(S3C_UDC_OTG_EP0_FIFO); ++ } ++ ++ return bytes; ++} ++ ++static int read_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req) ++{ ++ u32 csr; ++ u32 *buf; ++ unsigned bufferspace, count, is_short, bytes; ++ u32 fifo = ep->fifo; ++ ++ DEBUG_EP0("%s\n", __FUNCTION__); ++ ++ csr = readl(S3C_UDC_OTG_GRXSTSP); ++ bytes = (csr & 0x7ff0)>>4; ++ ++ buf = req->req.buf + req->req.actual; ++ prefetchw(buf); ++ bufferspace = req->req.length - req->req.actual; ++ ++ /* read all bytes from this packet */ ++ if (likely((csr & EP_MASK) == EP0_CON)) { ++ count = bytes / 4; ++ req->req.actual += min(bytes, bufferspace); ++ ++ } else { // zlp ++ count = 0; ++ bytes = 0; ++ } ++ ++ is_short = (bytes < ep->ep.maxpacket); ++ DEBUG_EP0("%s: read %s %02x, %d bytes%s req %p %d/%d\n", ++ __FUNCTION__, ++ ep->ep.name, csr, bytes, ++ is_short ? "/S" : "", req, req->req.actual, req->req.length); ++ ++ while (likely(count-- != 0)) { ++ u32 byte = (u32) readl(fifo); ++ ++ if (unlikely(bufferspace == 0)) { ++ /* this happens when the driver's buffer ++ * is smaller than what the host sent. ++ * discard the extra data. ++ */ ++ if (req->req.status != -EOVERFLOW) ++ DEBUG_EP0("%s overflow %d\n", ep->ep.name, ++ count); ++ req->req.status = -EOVERFLOW; ++ } else { ++ *buf++ = byte; ++ bufferspace = bufferspace - 4; ++ } ++ } ++ ++ /* completion */ ++ if (is_short || req->req.actual == req->req.length) { ++ return 1; ++ } ++ ++ return 0; ++} ++ ++/** ++ * udc_set_address - set the USB address for this device ++ * @address: ++ * ++ * Called from control endpoint function ++ * after it decodes a set address setup packet. ++ */ ++static void udc_set_address(struct s3c_udc *dev, unsigned char address) ++{ ++ u32 ctrl = readl(S3C_UDC_OTG_DCFG); ++ writel(address << 4 | ctrl, S3C_UDC_OTG_DCFG); ++ ++ ctrl = readl(S3C_UDC_OTG_DIEPCTL0); ++ writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, S3C_UDC_OTG_DIEPCTL0); /* EP0: Control IN */ ++ ++ DEBUG_EP0("%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n", ++ __FUNCTION__, address, readl(S3C_UDC_OTG_DCFG)); ++ ++ dev->usb_address = address; ++} ++ ++ ++ ++static int first_time = 1; ++ ++static void s3c_ep0_read(struct s3c_udc *dev) ++{ ++ struct s3c_request *req; ++ struct s3c_ep *ep = &dev->ep[0]; ++ int ret; ++ ++ if (!list_empty(&ep->queue)) ++ req = list_entry(ep->queue.next, struct s3c_request, queue); ++ else { ++ printk("%s: ---> BUG\n", __FUNCTION__); ++ BUG(); //logic ensures -jassi ++ return; ++ } ++ ++ DEBUG_EP0("%s: req.length = 0x%x, req.actual = 0x%x\n", ++ __FUNCTION__, req->req.length, req->req.actual); ++ ++ if(req->req.length == 0) { ++ dev->ep0state = WAIT_FOR_SETUP; ++ first_time = 1; ++ done(ep, req, 0); ++ return; ++ } ++ ++ if(!req->req.actual && first_time){ //for SetUp packet ++ first_time = 0; ++ return; ++ } ++ ++ ret = read_fifo_ep0(ep, req); ++ if (ret) { ++ dev->ep0state = WAIT_FOR_SETUP; ++ first_time = 1; ++ done(ep, req, 0); ++ return; ++ } ++ ++} ++ ++/* ++ * DATA_STATE_XMIT ++ */ ++static int s3c_ep0_write(struct s3c_udc *dev) ++{ ++ struct s3c_request *req; ++ struct s3c_ep *ep = &dev->ep[0]; ++ int ret, need_zlp = 0; ++ ++ DEBUG_EP0("%s: ep0 write\n", __FUNCTION__); ++ ++ if (list_empty(&ep->queue)) ++ req = 0; ++ else ++ req = list_entry(ep->queue.next, struct s3c_request, queue); ++ ++ if (!req) { ++ DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__); ++ return 0; ++ } ++ ++ DEBUG_EP0("%s: req.length = 0x%x, req.actual = 0x%x\n", ++ __FUNCTION__, req->req.length, req->req.actual); ++ ++ if (req->req.length == 0) { ++ dev->ep0state = WAIT_FOR_SETUP; ++ done(ep, req, 0); ++ return 1; ++ } ++ ++ if (req->req.length - req->req.actual == ep0_fifo_size) { ++ /* Next write will end with the packet size, */ ++ /* so we need Zero-length-packet */ ++ need_zlp = 1; ++ } ++ ++ ret = write_fifo_ep0(ep, req); ++ ++ if ((ret == 1) && !need_zlp) { ++ /* Last packet */ ++ DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__); ++ dev->ep0state = WAIT_FOR_SETUP; ++ } else { ++ DEBUG_EP0("%s: not finished\n", __FUNCTION__); ++ } ++ ++ if (need_zlp) { ++ DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__); ++ dev->ep0state = DATA_STATE_NEED_ZLP; ++ } ++ ++ if(ret) ++ done(ep, req, 0); ++ ++ return 1; ++} ++ ++static int s3c_udc_set_halt(struct usb_ep *_ep, int value) ++{ ++ struct s3c_ep *ep; ++ u32 ep_num; ++ ep = container_of(_ep, struct s3c_ep, ep); ++ ep_num =ep_index(ep); ++ ++ DEBUG("%s: ep_num = %d, value = %d\n", __FUNCTION__, ep_num, value); ++ /* TODO */ ++ return 0; ++} ++ ++void s3c_udc_ep_activate(struct s3c_ep *ep) ++{ ++ /* TODO */ ++} ++ ++/* ++ * WAIT_FOR_SETUP (OUT_PKT_RDY) ++ */ ++static void s3c_ep0_setup(struct s3c_udc *dev) ++{ ++ struct s3c_ep *ep = &dev->ep[0]; ++ int i, bytes, is_in; ++ u32 ep_ctrl; ++ ++ /* Nuke all previous transfers */ ++ nuke(ep, -EPROTO); ++ ++ /* read control req from fifo (8 bytes) */ ++ bytes = s3c_fifo_read(ep, (u32 *)&usb_ctrl, 8); ++ ++ DEBUG_SETUP("Read CTRL REQ %d bytes\n", bytes); ++ DEBUG_SETUP(" CTRL.bRequestType = 0x%x (is_in %d)\n", usb_ctrl.bRequestType, ++ usb_ctrl.bRequestType & USB_DIR_IN); ++ DEBUG_SETUP(" CTRL.bRequest = 0x%x\n", usb_ctrl.bRequest); ++ DEBUG_SETUP(" CTRL.wLength = 0x%x\n", usb_ctrl.wLength); ++ DEBUG_SETUP(" CTRL.wValue = 0x%x (%d)\n", usb_ctrl.wValue, usb_ctrl.wValue >> 8); ++ DEBUG_SETUP(" CTRL.wIndex = 0x%x\n", usb_ctrl.wIndex); ++ ++ /* Set direction of EP0 */ ++ if (likely(usb_ctrl.bRequestType & USB_DIR_IN)) { ++ ep->bEndpointAddress |= USB_DIR_IN; ++ is_in = 1; ++ } else { ++ ep->bEndpointAddress &= ~USB_DIR_IN; ++ is_in = 0; ++ } ++ ++ dev->req_pending = 1; ++ ++ /* Handle some SETUP packets ourselves */ ++ switch (usb_ctrl.bRequest) { ++ case USB_REQ_SET_ADDRESS: ++ if (usb_ctrl.bRequestType ++ != (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) ++ break; ++ ++ DEBUG_SETUP("%s: *** USB_REQ_SET_ADDRESS (%d)\n", ++ __FUNCTION__, usb_ctrl.wValue); ++ udc_set_address(dev, usb_ctrl.wValue); ++ return; ++ ++ case USB_REQ_SET_CONFIGURATION : ++ DEBUG_SETUP("============================================\n"); ++ DEBUG_SETUP("%s: USB_REQ_SET_CONFIGURATION (%d)\n", ++ __FUNCTION__, usb_ctrl.wValue); ++config_change: ++ // Just to send ZLP(Zero length Packet) to HOST in response to SET CONFIGURATION ++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL0); ++ writel(DEPCTL_EPENA|DEPCTL_CNAK|ep_ctrl, S3C_UDC_OTG_DIEPCTL0); /* EP0: Control IN */ ++ ++ // For Startng EP1 on this new configuration ++ ep_ctrl = readl(S3C_UDC_OTG_DOEPCTL1); ++ writel(DEPCTL_EPDIS|DEPCTL_CNAK|DEPCTL_BULK_TYPE|DEPCTL_USBACTEP|ep_ctrl, S3C_UDC_OTG_DOEPCTL1); /* EP1: Bulk OUT */ ++ ++ // For starting EP2 on this new configuration ++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL2); ++ writel(DEPCTL_BULK_TYPE|DEPCTL_USBACTEP|ep_ctrl, S3C_UDC_OTG_DIEPCTL2); /* EP2: Bulk IN */ ++ ++ // For starting EP3 on this new configuration ++ ep_ctrl = readl(S3C_UDC_OTG_DIEPCTL3); ++ writel(DEPCTL_BULK_TYPE|DEPCTL_USBACTEP|ep_ctrl, S3C_UDC_OTG_DIEPCTL3); /* EP3: INTR IN */ ++ ++ DEBUG_SETUP("%s:(DOEPCTL1):0x%x, (DIEPCTL2):0x%x, (DIEPCTL3):0x%x\n", ++ __FUNCTION__, ++ readl(S3C_UDC_OTG_DOEPCTL1), ++ readl(S3C_UDC_OTG_DIEPCTL2), ++ readl(S3C_UDC_OTG_DIEPCTL3)); ++ ++ DEBUG_SETUP("============================================\n"); ++ ++ reset_available = 1; ++ dev->req_config = 1; ++ break; ++ ++ case USB_REQ_GET_DESCRIPTOR: ++ DEBUG_SETUP("%s: *** USB_REQ_GET_DESCRIPTOR \n",__FUNCTION__); ++ break; ++ ++ case USB_REQ_SET_INTERFACE: ++ DEBUG_SETUP("%s: *** USB_REQ_SET_INTERFACE (%d)\n", ++ __FUNCTION__, usb_ctrl.wValue); ++ ++ set_interface_first = 1; ++ goto config_change; ++ break; ++ ++ case USB_REQ_GET_CONFIGURATION: ++ DEBUG_SETUP("%s: *** USB_REQ_GET_CONFIGURATION \n",__FUNCTION__); ++ break; ++ ++ case USB_REQ_GET_STATUS: ++ DEBUG_SETUP("%s: *** USB_REQ_GET_STATUS \n",__FUNCTION__); ++ break; ++ ++ default: ++ DEBUG_SETUP("%s: *** Default of usb_ctrl.bRequest=0x%x happened.\n", ++ __FUNCTION__, usb_ctrl.bRequest); ++ break; ++ } ++ ++ if (likely(dev->driver)) { ++ /* device-2-host (IN) or no data setup command, ++ * process immediately */ ++ spin_unlock(&dev->lock); ++ DEBUG_SETUP("%s: ctrlrequest will be passed to fsg_setup()\n", __FUNCTION__); ++ i = dev->driver->setup(&dev->gadget, (struct usb_ctrlrequest *)&usb_ctrl); ++ spin_lock(&dev->lock); ++ ++ if (i < 0) { ++ /* setup processing failed, force stall */ ++ DEBUG_SETUP("%s: gadget setup FAILED (stalling), setup returned %d\n", ++ __FUNCTION__, i); ++ /* ep->stopped = 1; */ ++ dev->ep0state = WAIT_FOR_SETUP; ++ } ++ } ++} ++ ++/* ++ * handle ep0 interrupt ++ */ ++static void s3c_handle_ep0(struct s3c_udc *dev) ++{ ++ if (dev->ep0state == WAIT_FOR_SETUP) { ++ DEBUG_EP0("%s: WAIT_FOR_SETUP\n", __FUNCTION__); ++ s3c_ep0_setup(dev); ++ ++ } else { ++ DEBUG_EP0("%s: strange state!!(state = %s)\n", ++ __FUNCTION__, state_names[dev->ep0state]); ++ } ++} ++ ++static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep) ++{ ++ DEBUG_EP0("%s: ep_is_in = %d\n", __FUNCTION__, ep_is_in(ep)); ++ if (ep_is_in(ep)) { ++ dev->ep0state = DATA_STATE_XMIT; ++ s3c_ep0_write(dev); ++ } else { ++ dev->ep0state = DATA_STATE_RECV; ++ s3c_ep0_read(dev); ++ } ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/gadget/u_ether.c linux-2.6.28.6/drivers/usb/gadget/u_ether.c +--- linux-2.6.28/drivers/usb/gadget/u_ether.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/gadget/u_ether.c 2009-04-30 09:36:39.000000000 +0200 +@@ -241,7 +241,12 @@ + size += out->maxpacket - 1; + size -= size % out->maxpacket; + ++#ifdef CONFIG_USB_GADGET_S3C_OTGD_DMA_MODE ++ /* for double word align */ ++ skb = alloc_skb(size + NET_IP_ALIGN + 6, gfp_flags); ++#else + skb = alloc_skb(size + NET_IP_ALIGN, gfp_flags); ++#endif + if (skb == NULL) { + DBG(dev, "no rx skb\n"); + goto enomem; +@@ -251,7 +256,12 @@ + * but on at least one, checksumming fails otherwise. Note: + * RNDIS headers involve variable numbers of LE32 values. + */ ++#ifdef CONFIG_USB_GADGET_S3C_OTGD_DMA_MODE ++ /* for double word align */ ++ skb_reserve(skb, NET_IP_ALIGN + 6); ++#else + skb_reserve(skb, NET_IP_ALIGN); ++#endif + + req->buf = skb->data; + req->length = size; +@@ -461,6 +471,11 @@ + spin_unlock(&dev->req_lock); + dev_kfree_skb_any(skb); + ++#ifdef CONFIG_USB_GADGET_S3C_OTGD_DMA_MODE ++ if(req->buf != skb->data) ++ kfree(req->buf); ++#endif ++ + atomic_dec(&dev->tx_qlen); + if (netif_carrier_ok(dev->net)) + netif_wake_queue(dev->net); +@@ -552,7 +567,21 @@ + skb = skb_new; + length = skb->len; + } ++ ++#ifdef CONFIG_USB_GADGET_S3C_OTGD_DMA_MODE ++ /* for double word align */ ++ req->buf = kmalloc(skb->len, GFP_ATOMIC | GFP_DMA); ++ ++ if (!req->buf) { ++ req->buf = skb->data; ++ printk("%s: fail to kmalloc [req->buf = skb->data]\n", __FUNCTION__); ++ } ++ else ++ memcpy((void *)req->buf, (void *)skb->data, skb->len); ++#else + req->buf = skb->data; ++#endif ++ + req->context = skb; + req->complete = tx_complete; + +@@ -586,6 +615,11 @@ + drop: + dev->net->stats.tx_dropped++; + dev_kfree_skb_any(skb); ++ ++#ifdef CONFIG_USB_GADGET_S3C_OTGD_DMA_MODE ++ if(req->buf != skb->data) ++ kfree(req->buf); ++#endif + spin_lock_irqsave(&dev->req_lock, flags); + if (list_empty(&dev->tx_reqs)) + netif_start_queue(net); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/Kconfig linux-2.6.28.6/drivers/usb/host/Kconfig +--- linux-2.6.28/drivers/usb/host/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/Kconfig 2009-04-30 09:36:39.000000000 +0200 +@@ -321,3 +321,18 @@ + + To compile this driver a module, choose M here: the module + will be called "hwa-hc". ++ ++config USB_S3C_OTG_HOST ++ tristate "S3C USB OTG Host support" ++ depends on USB && (PLAT_S3C64XX || PLAT_S5PC1XX) ++ help ++ Samsung's S3C64XX processors include high speed USB OTG2.0 ++ controller. It has 15 configurable endpoints, as well as ++ endpoint zero (for control transfers). ++ ++ This driver support only OTG Host role. If you want to use ++ OTG Device role, select USB Gadget support and S3C OTG Device. ++ ++ Say "y" to link the driver statically, or "m" to build a ++ dynamically linked module called "s3c_otg_hcd" and force all ++ drivers to also be dynamically linked. +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/Makefile linux-2.6.28.6/drivers/usb/host/Makefile +--- linux-2.6.28/drivers/usb/host/Makefile 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/Makefile 2009-04-30 09:36:39.000000000 +0200 +@@ -22,3 +22,4 @@ + obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o + obj-$(CONFIG_USB_ISP1760_HCD) += isp1760.o + obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o ++obj-$(CONFIG_USB_S3C_OTG_HOST) += s3c-otg/ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/ohci-hcd.c linux-2.6.28.6/drivers/usb/host/ohci-hcd.c +--- linux-2.6.28/drivers/usb/host/ohci-hcd.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/ohci-hcd.c 2009-04-30 09:36:39.000000000 +0200 +@@ -997,7 +997,7 @@ + #define SA1111_DRIVER ohci_hcd_sa1111_driver + #endif + +-#ifdef CONFIG_ARCH_S3C2410 ++#if defined(CONFIG_ARCH_S3C2410) || defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_ARCH_S5PC1XX) + #include "ohci-s3c2410.c" + #define PLATFORM_DRIVER ohci_hcd_s3c2410_driver + #endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/ohci-s3c2410.c linux-2.6.28.6/drivers/usb/host/ohci-s3c2410.c +--- linux-2.6.28/drivers/usb/host/ohci-s3c2410.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/ohci-s3c2410.c 2009-04-30 09:36:39.000000000 +0200 +@@ -27,10 +27,15 @@ + + #define valid_port(idx) ((idx) == 1 || (idx) == 2) + ++extern void usb_host_clk_en(void); ++ + /* clock device associated with the hcd */ + + static struct clk *clk; ++ ++#if defined(CONFIG_ARCH_2410) + static struct clk *usb_clk; ++#endif + + /* forward definitions */ + +@@ -49,8 +54,10 @@ + + dev_dbg(&dev->dev, "s3c2410_start_hc:\n"); + ++#if defined(CONFIG_ARCH_2410) + clk_enable(usb_clk); + mdelay(2); /* let the bus clock stabilise */ ++#endif + + clk_enable(clk); + +@@ -80,7 +87,9 @@ + } + + clk_disable(clk); ++#if defined(CONFIG_ARCH_2410) + clk_disable(usb_clk); ++#endif + } + + /* ohci_s3c2410_hub_status_data +@@ -347,6 +356,10 @@ + struct usb_hcd *hcd = NULL; + int retval; + ++#if !defined(CONFIG_ARCH_2410) ++ usb_host_clk_en(); ++#endif ++ + s3c2410_usb_set_power(dev->dev.platform_data, 1, 1); + s3c2410_usb_set_power(dev->dev.platform_data, 2, 1); + +@@ -370,12 +383,14 @@ + goto err_mem; + } + ++#if defined(CONFIG_ARCH_2410) + usb_clk = clk_get(&dev->dev, "usb-bus-host"); + if (IS_ERR(usb_clk)) { + dev_err(&dev->dev, "cannot get usb-host clock\n"); + retval = -ENOENT; + goto err_clk; + } ++#endif + + s3c2410_start_hc(dev, hcd); + +@@ -397,10 +412,13 @@ + err_ioremap: + s3c2410_stop_hc(dev); + iounmap(hcd->regs); ++ ++#if defined(CONFIG_ARCH_2410) + clk_put(usb_clk); + + err_clk: + clk_put(clk); ++#endif + + err_mem: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/Makefile linux-2.6.28.6/drivers/usb/host/s3c-otg/Makefile +--- linux-2.6.28/drivers/usb/host/s3c-otg/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/Makefile 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,18 @@ ++# ++# Makefile for USB OTG Host Controller Drivers ++# ++ ++obj-$(CONFIG_USB_S3C_OTG_HOST) += s3c_otg_hcd.o ++ ++s3c_otg_hcd-objs += s3c-otg-hcdi-driver.o s3c-otg-hcdi-hcd.o ++s3c_otg_hcd-objs += s3c-otg-transfer-common.o s3c-otg-transfer-nonperiodic.o \ ++ s3c-otg-transfer-periodic.o ++s3c_otg_hcd-objs += s3c-otg-scheduler-ischeduler.o s3c-otg-scheduler-scheduler.o \ ++ s3c-otg-scheduler-readyq.o ++s3c_otg_hcd-objs += s3c-otg-oci.o ++s3c_otg_hcd-objs += s3c-otg-transferchecker-common.o \ ++ s3c-otg-transferchecker-control.o \ ++ s3c-otg-transferchecker-bulk.o \ ++ s3c-otg-transferchecker-interrupt.o ++s3c_otg_hcd-objs += s3c-otg-isr.o ++s3c_otg_hcd-objs += s3c-otg-roothub.o +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-common-common.h linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-common-common.h +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-common-common.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-common-common.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,50 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * @file s3c-otg-common-common.h ++ * @brief it includes common header files for all modules \n ++ * @version ++ * ex)-# Jun 11,2008 v1.0 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Creating the initial version of this code \n ++ * @see None ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#ifndef _S3C_OTG_COMMON_COMMON_H_ ++#define _S3C_OTG_COMMON_COMMON_H_ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++//#include "s3c-otg-common-typedef.h" ++#include "s3c-otg-common-errorcode.h" ++#include ++#include ++ ++//Define OS ++#define LINUX 1 ++ ++//Kernel Version ++#define KERNEL_2_6_21 ++ ++ ++#ifdef __cplusplus ++} ++#endif ++#endif /* _S3C_OTG_COMMON_COMMON_H_ */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-common-const.h linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-common-const.h +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-common-const.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-common-const.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,167 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : s3c-otg-common-const.h ++ * [Description] : The Header file defines constants to be used at sub-modules of S3C6400HCD. ++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com } ++ * [Department] : System LSI Division/System SW Lab ++ * [Created Date]: 2008/06/03 ++ * [Revision History] ++ * (1) 2008/06/03 by Yang Soon Yeal { syatom.yang@samsung.com } ++ * - Created s3c-otg-common-const.h file and defines some constants. ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#ifndef _CONST_TYPE_DEF_H_ ++#define _CONST_TYPE_DEF_H_ ++ ++/* ++// ---------------------------------------------------------------------------- ++// Include files : None. ++// ---------------------------------------------------------------------------- ++*/ ++ ++#include "s3c-otg-common-common.h" ++ ++//#include "s3c-otg-common-regdef.h" ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++/** ++ * @def OTG_PORT_NUMBER ++ * ++ * @brief write~ description ++ * ++ * describe in detail ++ */ ++#define OTG_PORT_NUMBER 0 ++ ++ ++ ++//Defines Stages of Control Transfer ++#define SETUP_STAGE 1 ++#define DATA_STAGE 2 ++#define STATUS_STAGE 3 ++#define COMPLETE_STAGE 4 ++ ++ ++//Defines Direction of Endpoint ++#define EP_IN 1 ++#define EP_OUT 0 ++ ++//Define speed of USB Device ++#define LOW_SPEED_OTG 2 ++#define FULL_SPEED_OTG 1 ++#define HIGH_SPEED_OTG 0 ++#define SUPER_SPEED_OTG 3 ++ ++//Define multiple count of packet in periodic transfer. ++#define MULTI_COUNT_ZERO 0 ++#define MULTI_COUNT_ONE 1 ++#define MULTI_COUNT_TWO 2 ++ ++//Define USB Transfer Types. ++#define CONTROL_TRANSFER 0 ++#define ISOCH_TRANSFER 1 ++#define BULK_TRANSFER 2 ++#define INT_TRANSFER 3 ++ ++#define BULK_TIMEOUT 300 ++ ++//Defines PID ++#define DATA0 0 ++#define DATA1 2 ++#define DATA2 1 ++#define MDATA 3 ++#define SETUP 3 ++ ++//Defines USB Transfer Request Size on USB2.0 ++#define USB_20_STAND_DEV_REQUEST_SIZE 8 ++//Define Max Channel Number ++#define MAX_CH_NUMBER 16 ++//Define Channel Number ++#define CH_0 0 ++#define CH_1 1 ++#define CH_2 2 ++#define CH_3 3 ++#define CH_4 4 ++#define CH_5 5 ++#define CH_6 6 ++#define CH_7 7 ++#define CH_8 8 ++#define CH_9 9 ++#define CH_10 10 ++#define CH_11 11 ++#define CH_12 12 ++#define CH_13 13 ++#define CH_14 14 ++#define CH_15 15 ++#define CH_NONE 20 ++ ++ ++// define the Constant for result of processing the USB Transfer. ++#define RE_TRANSMIT 1 ++#define RE_SCHEDULE 2 ++#define DE_ALLOCATE 3 ++#define NO_ACTION 4 ++ ++//define the threshold value to retransmit USB Transfer ++#define RETRANSMIT_THRESHOLD 2 ++ ++//define the maximum size of data to be tranferred through channel. ++#define MAX_CH_TRANSFER_SIZE 65536//65535 ++ ++//define Max Frame Number which Synopsys OTG suppports. ++#define MAX_FRAME_NUMBER 0x3FFF ++// Channel Interrupt Status ++#define CH_STATUS_DataTglErr (0x1<<10) ++#define CH_STATUS_FrmOvrun (0x1<<9) ++#define CH_STATUS_BblErr (0x1<<8) ++#define CH_STATUS_XactErr (0x1<<7) ++#define CH_STATUS_NYET (0x1<<6) ++#define CH_STATUS_ACK (0x1<<5) ++#define CH_STATUS_NAK (0x1<<4) ++#define CH_STATUS_STALL (0x1<<3) ++#define CH_STATUS_AHBErr (0x1<<2) ++#define CH_STATUS_ChHltd (0x1<<1) ++#define CH_STATUS_XferCompl (0x1<<0) ++#define CH_STATUS_ALL 0x7FF ++ ++ ++//Define USB Transfer Flag.. ++//typedef URB_SHORT_NOT_OK USB_TRANS_FLAG_NOT_SHORT; ++//typedef URB_ISO_ASAP USB_TRANS_FLAG_ISO_ASYNCH; ++ ++#define USB_TRANS_FLAG_NOT_SHORT URB_SHORT_NOT_OK ++#define USB_TRANS_FLAG_ISO_ASYNCH URB_ISO_ASAP ++ ++ ++#define HFNUM_MAX_FRNUM 0x3FFF ++#define SCHEDULE_SLOT 10 ++ ++#ifdef __cplusplus ++} ++#endif ++ ++ ++#endif ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-common-datastruct.h linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-common-datastruct.h +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-common-datastruct.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-common-datastruct.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,870 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : s3c-otg-common-datastruct.h ++ * [Description] : The Header file defines Data Structures to be used at sub-modules of S3C6400HCD. ++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com } ++ * [Department] : System LSI Division/System SW Lab ++ * [Created Date]: 2008/06/03 ++ * [Revision History] ++ * (1) 2008/06/03 by Yang Soon Yeal { syatom.yang@samsung.com } ++ * - Created this file and defines Data Structure to be managed by Transfer. ++ * (2) 2008/08/18 by SeungSoo Yang ( ss1.yang@samsung.com ) ++ * - modifying ED structure ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#ifndef _DATA_STRUCT_DEF_H ++#define _DATA_STRUCT_DEF_H ++ ++/* ++// ---------------------------------------------------------------------------- ++// Include files : None. ++// ---------------------------------------------------------------------------- ++*/ ++ ++//#include "s3c-otg-common-typedef.h" ++#include "s3c-otg-hcdi-list.h" ++ ++//#include "s3c-otg-common-regdef.h" ++//#include "s3c-otg-common-errorcode.h" ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++typedef struct ++{ ++ u32 apll_lock; // 0x00 ++ u32 MPLL_LOCK; // 0x04 ++ u32 EPLL_LOCK; // 0x08 ++ u32 APLL_CON; // 0x0c ++ ++ u32 MPLL_CON; // 0x10 ++ u32 EPLL_CON0; // 0x14 ++ u32 EPLL_CON1; // 0x18 ++ u32 CLK_SRC; // 0x1c ++ ++ u32 CLK_DIV0; // 0x20 ++ u32 CLK_DIV1; // 0x24 ++ u32 CLK_DIV2; // 0x28 ++ u32 CLK_OUT; // 0x2c ++ ++ u32 HCLK_GATE; // 0x30 ++ u32 PCLK_GATE; // 0x34 ++ u32 SCLK_GATE; // 0x38 ++ u32 PAD0; // 0x3c ++ ++ u32 PAD1[48]; // 0x40~0xff ++ ++ u32 AHB_CON0; // 0x100 ++ u32 AHB_CON1; // 0x104 ++ u32 AHB_CON2; // 0x108 ++ u32 PAD2; // 0x10c ++ ++ u32 SDMA_SEL; // 0x110 ++ u32 SW_RST; // 0x114 ++ u32 SYS_ID; // 0x118 ++ u32 PAD3; // 0x11c ++ ++ u32 MEM_SYS_CFG; // 0x120 ++ u32 QOS_OVERRIDE0; // 0x124 ++ u32 QOS_OVERRIDE1; // 0x128 ++ u32 MEM_CFG_STAT; // 0x12c ++ ++ u32 PAD4[436]; // 0x130~0x7ff ++ ++ u32 PAD5; // 0x800 ++ u32 PWR_CFG; // 0x804 ++ u32 EINT_MASK; // 0x808 ++ u32 PAD6; // 0x80c ++ ++ u32 NORMAL_CFG; // 0x810 ++ u32 STOP_CFG; // 0x814 ++ u32 SLEEP_CFG; // 0x818 ++ u32 PAD7; // 0x81c ++ ++ u32 OSC_FREQ; // 0x820 ++ u32 OSC_STABLE; // 0x824 ++ u32 PWR_STABLE; // 0x828 ++ u32 FPC_STABLE; // 0x82c ++ ++ u32 MTC_STABLE; // 0x830 ++ u32 PAD8[3]; // 0x834~0x83f ++ ++ u32 PAD9[48]; // 0x840~0x8ff ++ ++ u32 OTHERS; // 0x900 ++ u32 RST_STAT; // 0x904 ++ u32 WAKEUP_STAT; // 0x908 ++ u32 BLK_PWR_STAT; // 0x90c ++ ++ u32 PAD10[60]; // 0x910~0x9ff ++ ++ u32 INFORM0; // 0xa00 ++ u32 INFORM1; // 0xa04 ++ u32 INFORM2; // 0xa08 ++ u32 INFORM3; // 0xa0c ++ ++ u32 INFORM4; // 0xa10 ++ u32 INFORM5; // 0xa14 ++ u32 INFORM6; // 0xa18 ++ u32 INFORM7; // 0xa1c ++} S3C6400_SYSCON_REG, *PS3C6400_SYSCON_REG; ++ ++typedef union _hcintmsk_t ++{ ++ // raw register data ++ u32 d32; ++ ++ // register bits ++ struct ++ { ++ unsigned xfercompl : 1; ++ unsigned chhltd : 1; ++ unsigned ahberr : 1; ++ unsigned stall : 1; ++ unsigned nak : 1; ++ unsigned ack : 1; ++ unsigned nyet : 1; ++ unsigned xacterr : 1; ++ unsigned bblerr : 1; ++ unsigned frmovrun : 1; ++ unsigned datatglerr : 1; ++ unsigned reserved : 21; ++ } b; ++} hcintmsk_t; ++ ++typedef union _hcintn_t ++{ ++ u32 d32; ++ struct ++ { ++ u32 xfercompl :1; ++ u32 chhltd :1; ++ u32 abherr :1; ++ u32 stall :1; ++ u32 nak :1; ++ u32 ack :1; ++ u32 nyet :1; ++ u32 xacterr :1; ++ u32 bblerr :1; ++ u32 frmovrun :1; ++ u32 datatglerr :1; ++ u32 reserved :21; ++ }b; ++}hcintn_t; ++ ++ ++typedef union _pcgcctl_t ++{ ++ /** raw register data */ ++ u32 d32; ++ /** register bits */ ++ struct ++ { ++ unsigned stoppclk :1; ++ unsigned gatehclk :1; ++ unsigned pwrclmp :1; ++ unsigned rstpdwnmodule :1; ++ unsigned physuspended :1; ++ unsigned Reserved5_31 :27; ++ }b; ++}pcgcctl_t; ++ ++ ++typedef struct isoch_packet_desc ++{ ++ u32 isoch_packiet_start_addr;// start address of buffer is buffer address + uiOffsert. ++ u32 buf_size; ++ u32 transferred_szie; ++ u32 isoch_status; ++}isoch_packet_desc_t;//, *isoch_packet_desc_t *,**isoch_packet_desc_t **; ++ ++ ++typedef struct standard_dev_req_info ++{ ++ bool is_data_stage; ++ u8 conrol_transfer_stage; ++ u32 vir_standard_dev_req_addr; ++ u32 phy_standard_dev_req_addr; ++}standard_dev_req_info_t; ++ ++ ++typedef struct control_data_tgl_t ++{ ++ u8 setup_tgl; ++ u8 data_tgl; ++ u8 status_tgl; ++}control_data_tgl_t; ++ ++ ++ ++typedef struct ed_status ++{ ++ u8 data_tgl; ++ control_data_tgl_t control_data_tgl; ++ bool is_ping_enable; ++ bool is_in_transfer_ready_q; ++ bool is_in_transferring; ++ u32 in_transferring_td; ++ bool is_alloc_resource_for_ed; ++}ed_status_t;//, *ed_status_t *,**ed_status_t **; ++ ++ ++typedef struct ed_desc ++{ ++ u8 device_addr; ++ u8 endpoint_num; ++ bool is_ep_in; ++ u8 dev_speed; ++ u8 endpoint_type; ++ u16 max_packet_size; ++ u8 mc; ++ u8 interval; ++ u32 sched_frame; ++ u32 used_bus_time; ++ u8 hub_addr; ++ u8 hub_port; ++ bool is_do_split; ++}ed_dest_t;//, *ed_dest_t *,**ed_dest_t **; ++ ++ ++//Defines the Data Structures of Transfer. ++typedef struct hc_reg ++{ ++ ++ hcintmsk_t hc_int_msk; ++ hcintn_t hc_int; ++ u32 dma_addr; ++ ++}hc_reg_t;//, *hc_reg_t *, **hc_reg_t **; ++ ++ ++typedef struct stransfer ++{ ++ u32 stransfer_id; ++ u32 parent_td; ++ ed_dest_t *ed_desc_p; ++ ed_status_t *ed_status_p; ++ u32 start_vir_buf_addr; ++ u32 start_phy_buf_addr; ++ u32 buf_size; ++ u32 packet_cnt; ++ u8 alloc_chnum; ++ hc_reg_t hc_reg; ++}stransfer_t;//, *stransfer_t *,**stransfer_t **; ++ ++ ++typedef struct ed ++{ ++ u32 ed_id; ++ bool is_halted; ++ bool is_need_to_insert_scheduler; ++ ed_dest_t ed_desc; ++ ed_status_t ed_status; ++ otg_list_head ed_list_entry; ++ otg_list_head td_list_entry; ++ otg_list_head trans_ready_q_list_entry; ++ u32 num_td; ++ void *ed_private; ++}ed_t;//, *ed_t *, **ed_t **; ++ ++ ++ ++typedef struct td ++{ ++ u32 td_id; ++ ed_t *parent_ed_p; ++ void *call_back_func_p; ++ void *call_back_func_param_p; ++ bool is_transferring; ++ bool is_transfer_done; ++ u32 transferred_szie; ++ bool is_standard_dev_req; ++ standard_dev_req_info_t standard_dev_req_info; ++ u32 vir_buf_addr; ++ u32 phy_buf_addr; ++ u32 buf_size; ++ u32 transfer_flag; ++ stransfer_t cur_stransfer; ++ USB_ERROR_CODE error_code; ++ u32 err_cnt; ++ otg_list_head td_list_entry; ++ ++ //Isochronous Transfer Specific ++ u32 isoch_packet_num; ++ isoch_packet_desc_t *isoch_packet_desc_p; ++ u32 isoch_packet_index; ++ u32 isoch_packet_position; ++ u32 sched_frame; ++ u32 interval; ++ u32 used_total_bus_time; ++ ++ // the private data can be used by S3C6400Interface. ++ void *td_private; ++}td_t;//, *td_t *,**td_t **; ++ ++ ++//Define Data Structures of Scheduler. ++typedef struct trans_ready_q ++{ ++bool is_periodic_transfer; ++otg_list_head trans_ready_q_list_head; ++u32 trans_ready_entry_num; ++ ++//In case of Periodic Transfer ++u32 total_perio_bus_bandwidth; ++u8 total_alloc_chnum; ++}trans_ready_q_t;//, *trans_ready_q_t *,**trans_ready_q_t **; ++ ++ ++//Define USB OTG Reg Data Structure by Kyuhyeok. ++ ++#define MAX_COUNT 10000 ++#define INT_ALL 0xffffffff ++ ++typedef union _haint_t ++{ ++ u32 d32; ++ struct ++ { ++ u32 reserved1 :16; ++ u32 channel_intr_15 :1; ++ u32 channel_intr_14 :1; ++ u32 channel_intr_13 :1; ++ u32 channel_intr_12 :1; ++ u32 channel_intr_11 :1; ++ u32 channel_intr_10 :1; ++ u32 channel_intr_9 :1; ++ u32 channel_intr_8 :1; ++ u32 channel_intr_7 :1; ++ u32 channel_intr_6 :1; ++ u32 channel_intr_5 :1; ++ u32 channel_intr_4 :1; ++ u32 channel_intr_3 :1; ++ u32 channel_intr_2 :1; ++ u32 channel_intr_1 :1; ++ u32 channel_intr_0 :1; ++ }b; ++}haint_t; ++ ++typedef union _gresetctl_t ++{ ++ /** raw register data */ ++ u32 d32; ++ /** register bits */ ++ struct ++ { ++ unsigned csftrst : 1; ++ unsigned hsftrst : 1; ++ unsigned hstfrm : 1; ++ unsigned intknqflsh : 1; ++ unsigned rxfflsh : 1; ++ unsigned txfflsh : 1; ++ unsigned txfnum : 5; ++ unsigned reserved11_29 : 19; ++ unsigned dmareq : 1; ++ unsigned ahbidle : 1; ++ } b; ++} gresetctl_t; ++ ++ ++typedef union _gahbcfg_t ++{ ++ /** raw register data */ ++ u32 d32; ++ /** register bits */ ++ struct ++ { ++ unsigned glblintrmsk : 1; ++#define GAHBCFG_GLBINT_ENABLE 1 ++ unsigned hburstlen : 4; ++#define INT_DMA_MODE_SINGLE 00 ++#define INT_DMA_MODE_INCR 01 ++#define INT_DMA_MODE_INCR4 03 ++#define INT_DMA_MODE_INCR8 05 ++#define INT_DMA_MODE_INCR16 07 ++ unsigned dmaenable : 1; ++#define GAHBCFG_DMAENABLE 1 ++ unsigned reserved : 1; ++ unsigned nptxfemplvl : 1; ++ unsigned ptxfemplvl : 1; ++#define GAHBCFG_TXFEMPTYLVL_EMPTY 1 ++#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 ++ unsigned reserved9_31 : 22; ++ } b; ++} gahbcfg_t; ++ ++typedef union _gusbcfg_t ++{ ++ /** raw register data */ ++ u32 d32; ++ /** register bits */ ++ struct ++ { ++ unsigned toutcal : 3; ++ unsigned phyif : 1; ++ unsigned ulpi_utmi_sel : 1; ++ unsigned fsintf : 1; ++ unsigned physel : 1; ++ unsigned ddrsel : 1; ++ unsigned srpcap : 1; ++ unsigned hnpcap : 1; ++ unsigned usbtrdtim : 4; ++ unsigned nptxfrwnden : 1; ++ unsigned phylpwrclksel : 1; ++ unsigned reserved : 13; ++ unsigned forcehstmode : 1; ++ unsigned reserved2 : 2; ++ } b; ++} gusbcfg_t; ++ ++ ++typedef union _ghwcfg2_t ++{ ++ /** raw register data */ ++ u32 d32; ++ /** register bits */ ++ struct { ++ /* GHWCFG2 */ ++ unsigned op_mode : 3; ++#define MODE_HNP_SRP_CAPABLE 0 ++#define MODE_SRP_ONLY_CAPABLE 1 ++#define MODE_NO_HNP_SRP_CAPABLE 2 ++#define MODE_SRP_CAPABLE_DEVICE 3 ++#define MODE_NO_SRP_CAPABLE_DEVICE 4 ++#define MODE_SRP_CAPABLE_HOST 5 ++#define MODE_NO_SRP_CAPABLE_HOST 6 ++ ++ unsigned architecture : 2; ++#define HWCFG2_ARCH_SLAVE_ONLY 0x00 ++#define HWCFG2_ARCH_EXT_DMA 0x01 ++#define HWCFG2_ARCH_INT_DMA 0x02 ++ ++ unsigned point2point : 1; ++ unsigned hs_phy_type : 2; ++ unsigned fs_phy_type : 2; ++ unsigned num_dev_ep : 4; ++ unsigned num_host_chan : 4; ++ unsigned perio_ep_supported : 1; ++ unsigned dynamic_fifo : 1; ++ unsigned rx_status_q_depth : 2; ++ unsigned nonperio_tx_q_depth : 2; ++ unsigned host_perio_tx_q_depth : 2; ++ unsigned dev_token_q_depth : 5; ++ unsigned reserved31 : 1; ++ } b; ++} ghwcfg2_t; ++ ++typedef union _gintsts_t ++{ ++ /** raw register data */ ++ u32 d32; ++#define SOF_INTR_MASK 0x0008 ++ /** register bits */ ++ struct ++ { ++#define HOST_MODE 1 ++#define DEVICE_MODE 0 ++ unsigned curmode : 1; ++#define OTG_HOST_MODE 1 ++#define OTG_DEVICE_MODE 0 ++ ++ unsigned modemismatch : 1; ++ unsigned otgintr : 1; ++ unsigned sofintr : 1; ++ unsigned rxstsqlvl : 1; ++ unsigned nptxfempty : 1; ++ unsigned ginnakeff : 1; ++ unsigned goutnakeff : 1; ++ unsigned reserved8 : 1; ++ unsigned i2cintr : 1; ++ unsigned erlysuspend : 1; ++ unsigned usbsuspend : 1; ++ unsigned usbreset : 1; ++ unsigned enumdone : 1; ++ unsigned isooutdrop : 1; ++ unsigned eopframe : 1; ++ unsigned intokenrx : 1; ++ unsigned epmismatch : 1; ++ unsigned inepint : 1; ++ unsigned outepintr : 1; ++ unsigned incompisoin : 1; ++ unsigned incompisoout : 1; ++ unsigned reserved22_23 : 2; ++ unsigned portintr : 1; ++ unsigned hcintr : 1; ++ unsigned ptxfempty : 1; ++ unsigned reserved27 : 1; ++ unsigned conidstschng : 1; ++ unsigned disconnect : 1; ++ unsigned sessreqintr : 1; ++ unsigned wkupintr : 1; ++ } b; ++} gintsts_t; ++ ++ ++typedef union _hcfg_t ++{ ++ /** raw register data */ ++ u32 d32; ++ ++ /** register bits */ ++ struct ++ { ++ /** FS/LS Phy Clock Select */ ++ unsigned fslspclksel : 2; ++#define HCFG_30_60_MHZ 0 ++#define HCFG_48_MHZ 1 ++#define HCFG_6_MHZ 2 ++ ++ /** FS/LS Only Support */ ++ unsigned fslssupp : 1; ++ } b; ++} hcfg_t; ++ ++typedef union _hprt_t ++{ ++ /** raw register data */ ++ u32 d32; ++ /** register bits */ ++ struct ++ { ++ unsigned prtconnsts : 1; ++ unsigned prtconndet : 1; ++ unsigned prtena : 1; ++ unsigned prtenchng : 1; ++ unsigned prtovrcurract : 1; ++ unsigned prtovrcurrchng : 1; ++ unsigned prtres : 1; ++ unsigned prtsusp : 1; ++ unsigned prtrst : 1; ++ unsigned reserved9 : 1; ++ unsigned prtlnsts : 2; ++ unsigned prtpwr : 1; ++ unsigned prttstctl : 4; ++ unsigned prtspd : 2; ++#define HPRT0_PRTSPD_HIGH_SPEED 0 ++#define HPRT0_PRTSPD_FULL_SPEED 1 ++#define HPRT0_PRTSPD_LOW_SPEED 2 ++ unsigned reserved19_31 : 13; ++ } b; ++} hprt_t; ++ ++ ++typedef union _gintmsk_t ++{ ++ /** raw register data */ ++ u32 d32; ++ /** register bits */ ++ struct ++ { ++ unsigned reserved0 : 1; ++ unsigned modemismatch : 1; ++ unsigned otgintr : 1; ++ unsigned sofintr : 1; ++ unsigned rxstsqlvl : 1; ++ unsigned nptxfempty : 1; ++ unsigned ginnakeff : 1; ++ unsigned goutnakeff : 1; ++ unsigned reserved8 : 1; ++ unsigned i2cintr : 1; ++ unsigned erlysuspend : 1; ++ unsigned usbsuspend : 1; ++ unsigned usbreset : 1; ++ unsigned enumdone : 1; ++ unsigned isooutdrop : 1; ++ unsigned eopframe : 1; ++ unsigned reserved16 : 1; ++ unsigned epmismatch : 1; ++ unsigned inepintr : 1; ++ unsigned outepintr : 1; ++ unsigned incompisoin : 1; ++ unsigned incompisoout : 1; ++ unsigned reserved22_23 : 2; ++ unsigned portintr : 1; ++ unsigned hcintr : 1; ++ unsigned ptxfempty : 1; ++ unsigned reserved27 : 1; ++ unsigned conidstschng : 1; ++ unsigned disconnect : 1; ++ unsigned sessreqintr : 1; ++ unsigned wkupintr : 1; ++ } b; ++} gintmsk_t; ++ ++ ++typedef struct _hc_t ++{ ++ ++ u8 hc_num; // Host channel number used for register address lookup ++ ++ unsigned dev_addr : 7; // Device to access ++ unsigned ep_is_in : 1; // EP direction; 0: OUT, 1: IN ++ ++ unsigned ep_num : 4; // EP to access ++ unsigned low_speed : 1; // 1: Low speed, 0: Not low speed ++ unsigned ep_type : 2; // Endpoint type. ++ // One of the following values: ++ // - OTG_EP_TYPE_CONTROL: 0 ++ // - OTG_EP_TYPE_ISOC: 1 ++ // - OTG_EP_TYPE_BULK: 2 ++ // - OTG_EP_TYPE_INTR: 3 ++ ++ unsigned rsvdb1 : 1; // 8 bit padding ++ ++ u8 rsvd2; // 4 byte boundary ++ ++ unsigned max_packet : 12; // Max packet size in bytes ++ ++ unsigned data_pid_start : 2; ++#define OTG_HC_PID_DATA0 0 ++#define OTG_HC_PID_DATA2 1 ++#define OTG_HC_PID_DATA1 2 ++#define OTG_HC_PID_MDATA 3 ++#define OTG_HC_PID_SETUP 3 ++ ++ unsigned multi_count : 2; // Number of periodic transactions per (micro)frame ++ ++ ++ // Flag to indicate whether the transfer has been started. Set to 1 if ++ // it has been started, 0 otherwise. ++ u8 xfer_started; ++ ++ ++ // Set to 1 to indicate that a PING request should be issued on this ++ // channel. If 0, process normally. ++ u8 do_ping; ++ ++ // Set to 1 to indicate that the error count for this transaction is ++ // non-zero. Set to 0 if the error count is 0. ++ u8 error_state; ++ u32 *xfer_buff; // Pointer to the current transfer buffer position. ++ u16 start_pkt_count; // Packet count at start of transfer. ++ ++ u32 xfer_len; // Total number of bytes to transfer. ++ u32 xfer_count; // Number of bytes transferred so far. ++ ++ ++ // Set to 1 if the host channel has been halted, but the core is not ++ // finished flushing queued requests. Otherwise 0. ++ u8 halt_pending; ++ u8 halt_status; // Reason for halting the host channel ++ u8 short_read; // Set when the host channel does a short read. ++ u8 rsvd3; // 4 byte boundary ++ ++} hc_t; ++ ++ ++// Port status for the HC ++#define HCD_DRIVE_RESET 0x0001 ++#define HCD_SEND_SETUP 0x0002 ++ ++#define HC_MAX_PKT_COUNT 511 ++#define HC_MAX_TRANSFER_SIZE 65535 ++#define MAXP_SIZE_64BYTE 64 ++#define MAXP_SIZE_512BYTE 512 ++#define MAXP_SIZE_1024BYTE 1024 ++ ++typedef union _hcchar_t ++{ ++ // raw register data ++ u32 d32; ++ ++ // register bits ++ struct ++ { ++ // Maximum packet size in bytes ++ unsigned mps : 11; ++ ++ // Endpoint number ++ unsigned epnum : 4; ++ ++ // 0: OUT, 1: IN ++ unsigned epdir : 1; ++#define HCDIR_OUT 0 ++#define HCDIR_IN 1 ++ ++ unsigned reserved : 1; ++ ++ // 0: Full/high speed device, 1: Low speed device ++ unsigned lspddev : 1; ++ ++ // 0: Control, 1: Isoc, 2: Bulk, 3: Intr ++ unsigned eptype : 2; ++#define OTG_EP_TYPE_CONTROL 0 ++#define OTG_EP_TYPE_ISOC 1 ++#define OTG_EP_TYPE_BULK 2 ++#define OTG_EP_TYPE_INTR 3 ++ ++ // Packets per frame for periodic transfers. 0 is reserved. ++ unsigned multicnt : 2; ++ ++ // Device address ++ unsigned devaddr : 7; ++ ++ // Frame to transmit periodic transaction. ++ // 0: even, 1: odd ++ unsigned oddfrm : 1; ++ ++ // Channel disable ++ unsigned chdis : 1; ++ ++ // Channel enable ++ unsigned chen : 1; ++ } b; ++} hcchar_t; ++ ++typedef union _hctsiz_t ++{ ++ // raw register data ++ u32 d32; ++ ++ // register bits ++ struct ++ { ++ // Total transfer size in bytes ++ unsigned xfersize : 19; ++ ++ // Data packets to transfer ++ unsigned pktcnt : 10; ++ ++ // Packet ID for next data packet ++ // 0: DATA0 ++ // 1: DATA2 ++ // 2: DATA1 ++ // 3: MDATA (non-Control), SETUP (Control) ++ unsigned pid : 2; ++#define HCTSIZ_DATA0 0 ++#define HCTSIZ_DATA1 2 ++#define HCTSIZ_DATA2 1 ++#define HCTSIZ_MDATA 3 ++#define HCTSIZ_SETUP 3 ++ ++ // Do PING protocol when 1 ++ unsigned dopng : 1; ++ } b; ++} hctsiz_t; ++ ++ ++ ++typedef union _grxstsr_t ++{ ++ // raw register data ++ u32 d32; ++ ++ // register bits ++ struct ++ { ++ unsigned Reserved : 11; ++ unsigned pktsts : 4; ++ unsigned dpid : 2; ++ unsigned bcnt : 11; ++ unsigned chnum : 4; ++ } b; ++} grxstsr_t; ++ ++typedef union _hfir_t ++{ ++ // raw register data ++ u32 d32; ++ ++ // register bits ++ struct ++ { ++ unsigned Reserved : 16; ++ unsigned frint : 16; ++ } b; ++} hfir_t; ++ ++typedef union _hfnum_t ++{ ++ // raw register data ++ u32 d32; ++ ++ // register bits ++ struct ++ { ++ unsigned frnum : 16; ++#define HFNUM_MAX_FRNUM 0x3FFF ++ unsigned frrem : 16; ++ } b; ++} hfnum_t; ++ ++typedef union grstctl_t ++{ ++ /** raw register data */ ++ u32 d32; ++ /** register bits */ ++ struct ++ { ++ unsigned csftrst : 1; ++ unsigned hsftrst : 1; ++ unsigned hstfrm : 1; ++ unsigned intknqflsh : 1; ++ unsigned rxfflsh : 1; ++ unsigned txfflsh : 1; ++ unsigned txfnum : 5; ++ unsigned reserved11_29 : 19; ++ unsigned dmareq : 1; ++ unsigned ahbidle : 1; ++ } b; ++} grstctl_t; ++ ++ ++ ++ ++typedef struct hc_info ++{ ++ hcintmsk_t hc_int_msk; ++ hcintn_t hc_int; ++ u32 dma_addr; ++ hcchar_t hc_char; ++ hctsiz_t hc_size; ++}hc_info_t;//, *hc_info_t *, **hc_info_t **; ++ ++#ifndef USB_MAXCHILDREN ++ #define USB_MAXCHILDREN (31) ++#endif ++ ++typedef struct _usb_hub_descriptor_t ++{ ++ u8 desc_length; ++ u8 desc_type; ++ u8 port_number; ++ u16 hub_characteristics; ++ u8 power_on_to_power_good; ++ u8 hub_control_current; ++ /* add 1 bit for hub status change; round to bytes */ ++ u8 DeviceRemovable[(USB_MAXCHILDREN + 1 + 7) / 8]; ++ u8 port_pwr_ctrl_mask[(USB_MAXCHILDREN + 1 + 7) / 8]; ++}usb_hub_descriptor_t; ++ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++ ++#endif ++ ++ ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-common-errorcode.h linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-common-errorcode.h +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-common-errorcode.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-common-errorcode.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,114 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : s3c-otg-common-errorcode.h ++ * [Description] : The Header file defines Error Codes to be used at sub-modules of S3C6400HCD. ++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com } ++ * [Department] : System LSI Division/System SW Lab ++ * [Created Date]: 2008/06/03 ++ * [Revision History] ++ * (1) 2008/06/03 by Yang Soon Yeal { syatom.yang@samsung.com } ++ * - Created this file. ++ * (2) 2008/08/18 by SeungSoo Yang ( ss1.yang@samsung.com ) ++ * - add HCD error code ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#ifndef _ERROR_CODE_DEF_H ++#define _ERROR_CODE_DEF_H ++ ++/* ++// ---------------------------------------------------------------------------- ++// Include files : None. ++// ---------------------------------------------------------------------------- ++*/ ++ ++//#include "s3c-otg-common-typedef.h" ++#include "s3c-otg-common-common.h" ++ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++ ++typedef int USB_ERROR_CODE; ++ ++//General USB Error Code. ++#define USB_ERR_SUCCESS 0 ++#define USB_ERR_FAIL -1 ++ ++#define USB_ERR_NO 1 ++ ++#define USB_ERR_NO_ENTITY -2 ++ ++//S3CTransfer Error Code ++#define USB_ERR_NODEV -ENODEV ++#define USB_ERR_NOMEM -ENOMEM ++#define USB_ERR_NOSPACE -ENOSPC ++ ++//OTG-HCD error code ++#define USB_ERR_NOELEMENT -ENOENT ++#define USB_ERR_ESHUTDOWN -ESHUTDOWN /* unplug */ ++#define USB_ERR_DEQUEUED -ECONNRESET /* unlink */ ++ ++ ++//S3CScheduler Error Code ++#define USB_ERR_ALREADY_EXIST -1 ++#define USB_ERR_NO_RESOURCE -2 ++#define USB_ERR_NO_CHANNEL -3 ++#define USB_ERR_NO_BANDWIDTH -4 ++#define USB_ERR_ALL_RESROUCE -5 ++ ++ ++ ++ ++/************************************************ ++ *Defines the USB Error Status Code of USB Transfer. ++ ************************************************/ ++ ++//#ifdef LINUX ++ ++#define USB_ERR_STATUS_COMPLETE 0 ++#define USB_ERR_STATUS_INPROGRESS -EINPROGRESS ++#define USB_ERR_STATUS_CRC -EILSEQ ++#define USB_ERR_STATUS_XACTERR -EPROTO ++#define USB_ERR_STATUS_STALL -EPIPE ++#define USB_ERR_STATUS_BBLERR -EOVERFLOW ++#define USB_ERR_STATUS_AHBERR -EIO ++#define USB_ERR_STATUS_FRMOVRUN_OUT -ENOSR ++#define USB_ERR_STATUS_FRMOVRUN_IN -ECOMM ++#define USB_ERR_STATUS_SHORTREAD -EREMOTEIO ++ ++//#else ++ ++//#endif ++ ++ ++ ++ ++ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++ ++#endif ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-common-regdef.h linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-common-regdef.h +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-common-regdef.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-common-regdef.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,317 @@ ++/**************************************************************************** ++* (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++* ++* [File Name] : S3C6400_OtgDevice.h ++* [Description] : ++* ++* [Author] : Kyu Hyeok Jang { kyuhyeok.jang@samsung.com } ++* [Department] : System LSI Division/Embedded Software Center ++* [Created Date]: 2007/12/15 ++* [Revision History] ++* (1) 2007/12/15 by Kyu Hyeok Jang { kyuhyeok.jang@samsung.com } ++* - Created ++* ++****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#ifndef _OTG_REG_DEF_H ++#define _OTG_REG_DEF_H ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++//#include "s3c-otg-common-typedef.h" ++ ++#define RegOpenKey(hkey, lpsz, phk) \ ++ RegOpenKeyEx((hkey), (lpsz), 0, 0, (phk)) ++ ++#define OTG_LINK_REG_SIZE 0x11000 ++ ++// "IoBase"=dword:B1800000 ++// "IoLen"=dword:11000 ; chandolp 1000 --> 10000 ++ ++//////////////////////////////////////////////////////////// ++#define S3C6400_BASE_REG_PA_USBOTG_PHY 0x7C100000 ++#define S3C6400_BASE_REG_PA_SYSCON 0x7E00F000 ++//////////////////////////////////////////////////////////// ++ ++typedef struct { ++ u32 OPHYPWR; ++ u32 OPHYCLK; ++ u32 ORSTCON; ++}OTG_PHY_REG, *PS_OTG_PHY_REG; ++ ++#define GOTGCTL 0x000 // OTG Control & Status ++#define GOTGINT 0x004 // OTG Interrupt ++#define GAHBCFG 0x008 // Core AHB Configuration ++#define GUSBCFG 0x00C // Core USB Configuration ++#define GRSTCTL 0x010 // Core Reset ++#define GINTSTS 0x014 // Core Interrupt ++#define GINTMSK 0x018 // Core Interrupt Mask ++#define GRXSTSR 0x01C // Receive Status Debug Read/Status Read ++#define GRXSTSP 0x020 // Receive Status Debug Pop/Status Pop ++#define GRXFSIZ 0x024 // Receive FIFO Size ++#define GNPTXFSIZ 0x028 // Non-Periodic Transmit FIFO Size ++#define GNPTXSTS 0x02C // Non-Periodic Transmit FIFO/Queue Status ++#define GPVNDCTL 0x034 // PHY Vendor Control ++#define GGPIO 0x038 // General Purpose I/O ++#define GUID 0x03C // User ID ++#define GSNPSID 0x040 // Synopsys ID ++#define GHWCFG1 0x044 // User HW Config1 ++#define GHWCFG2 0x048 // User HW Config2 ++#define GHWCFG3 0x04C // User HW Config3 ++#define GHWCFG4 0x050 // User HW Config4 ++ ++#define HPTXFSIZ 0x100 // Host Periodic Transmit FIFO Size ++#define DPTXFSIZ1 0x104 // Device Periodic Transmit FIFO-1 Size ++#define DPTXFSIZ2 0x108 // Device Periodic Transmit FIFO-2 Size ++#define DPTXFSIZ3 0x10C // Device Periodic Transmit FIFO-3 Size ++#define DPTXFSIZ4 0x110 // Device Periodic Transmit FIFO-4 Size ++#define DPTXFSIZ5 0x114 // Device Periodic Transmit FIFO-5 Size ++#define DPTXFSIZ6 0x118 // Device Periodic Transmit FIFO-6 Size ++#define DPTXFSIZ7 0x11C // Device Periodic Transmit FIFO-7 Size ++#define DPTXFSIZ8 0x120 // Device Periodic Transmit FIFO-8 Size ++#define DPTXFSIZ9 0x124 // Device Periodic Transmit FIFO-9 Size ++#define DPTXFSIZ10 0x128 // Device Periodic Transmit FIFO-10 Size ++#define DPTXFSIZ11 0x12C // Device Periodic Transmit FIFO-11 Size ++#define DPTXFSIZ12 0x130 // Device Periodic Transmit FIFO-12 Size ++#define DPTXFSIZ13 0x134 // Device Periodic Transmit FIFO-13 Size ++#define DPTXFSIZ14 0x138 // Device Periodic Transmit FIFO-14 Size ++#define DPTXFSIZ15 0x13C // Device Periodic Transmit FIFO-15 Size ++ ++//********************************************************************* ++// Host Mode Registers ++//********************************************************************* ++// Host Global Registers ++ ++// Channel specific registers ++#define HCCHAR_ADDR 0x500 ++#define HCCHAR(n) 0x500 + ((n)*0x20) ++#define HCSPLT(n) 0x504 + ((n)*0x20) ++#define HCINT(n) 0x508 + ((n)*0x20) ++#define HCINTMSK(n) 0x50C + ((n)*0x20) ++#define HCTSIZ(n) 0x510 + ((n)*0x20) ++#define HCDMA(n) 0x514 + ((n)*0x20) ++ ++#define HCFG 0x400 // Host Configuration ++#define HFIR 0x404 // Host Frame Interval ++#define HFNUM 0x408 // Host Frame Number/Frame Time Remaining ++#define HPTXSTS 0x410 // Host Periodic Transmit FIFO/Queue Status ++#define HAINT 0x414 // Host All Channels Interrupt ++#define HAINTMSK 0x418 // Host All Channels Interrupt Mask ++ ++// Host Port Control & Status Registers ++ ++#define HPRT 0x440 // Host Port Control & Status ++ ++// Device Logical Endpoints-Specific Registers ++ ++#define DIEPCTL 0x900 // Device IN Endpoint 0 Control ++#define DOEPCTL(n) 0xB00 + ((n)*0x20)) // Device OUT Endpoint 0 Control ++#define DIEPINT(n) 0x908 + ((n)*0x20)) // Device IN Endpoint 0 Interrupt ++#define DOEPINT(n) 0xB08 + ((n)*0x20)) // Device OUT Endpoint 0 Interrupt ++#define DIEPTSIZ(n) 0x910 + ((n)*0x20)) // Device IN Endpoint 0 Transfer Size ++#define DOEPTSIZ(n) 0xB10 + ((n)*0x20)) // Device OUT Endpoint 0 Transfer Size ++#define DIEPDMA(n) 0x914 + ((n)*0x20)) // Device IN Endpoint 0 DMA Address ++#define DOEPDMA(n) 0xB14 + ((n)*0x20)) // Device OUT Endpoint 0 DMA Address ++ ++#define EP_FIFO(n) 0x1000 + ((n)*0x1000)) ++ ++#define PCGCCTL 0x0E00 ++ ++// ++#define BASE_REGISTER_OFFSET 0x0 ++#define REGISTER_SET_SIZE 0x200 ++ ++// Power Reg Bits ++#define USB_RESET 0x8 ++#define MCU_RESUME 0x4 ++#define SUSPEND_MODE 0x2 ++#define SUSPEND_MODE_ENABLE_CTRL 0x1 ++ ++// EP0 CSR ++#define EP0_OUT_PACKET_RDY 0x1 ++#define EP0_IN_PACKET_RDY 0x2 ++#define EP0_SENT_STALL 0x4 ++#define DATA_END 0x8 ++#define SETUP_END 0x10 ++#define EP0_SEND_STALL 0x20 ++#define SERVICED_OUT_PKY_RDY 0x40 ++#define SERVICED_SETUP_END 0x80 ++ ++// IN_CSR1_REG Bit definitions ++#define IN_PACKET_READY 0x1 ++#define UNDER_RUN 0x4 // Iso Mode Only ++#define FLUSH_IN_FIFO 0x8 ++#define IN_SEND_STALL 0x10 ++#define IN_SENT_STALL 0x20 ++#define IN_CLR_DATA_TOGGLE 0x40 ++ ++// OUT_CSR1_REG Bit definitions ++#define OUT_PACKET_READY 0x1 ++#define FLUSH_OUT_FIFO 0x10 ++#define OUT_SEND_STALL 0x20 ++#define OUT_SENT_STALL 0x40 ++#define OUT_CLR_DATA_TOGGLE 0x80 ++ ++// IN_CSR2_REG Bit definitions ++#define IN_DMA_INT_DISABLE 0x10 ++#define SET_MODE_IN 0x20 ++ ++#define EPTYPE (0x3<<18) ++#define SET_TYPE_CONTROL (0x0<<18) ++#define SET_TYPE_ISO (0x1<<18) ++#define SET_TYPE_BULK (0x2<<18) ++#define SET_TYPE_INTERRUPT (0x3<<18) ++ ++#define AUTO_MODE 0x80 ++ ++// OUT_CSR2_REG Bit definitions ++#define AUTO_CLR 0x40 ++#define OUT_DMA_INT_DISABLE 0x20 ++ ++// Can be used for Interrupt and Interrupt Enable Reg - common bit def ++#define EP0_IN_INT (0x1<<0) ++#define EP1_IN_INT (0x1<<1) ++#define EP2_IN_INT (0x1<<2) ++#define EP3_IN_INT (0x1<<3) ++#define EP4_IN_INT (0x1<<4) ++#define EP5_IN_INT (0x1<<5) ++#define EP6_IN_INT (0x1<<6) ++#define EP7_IN_INT (0x1<<7) ++#define EP8_IN_INT (0x1<<8) ++#define EP9_IN_INT (0x1<<9) ++#define EP10_IN_INT (0x1<<10) ++#define EP11_IN_INT (0x1<<11) ++#define EP12_IN_INT (0x1<<12) ++#define EP13_IN_INT (0x1<<13) ++#define EP14_IN_INT (0x1<<14) ++#define EP15_IN_INT (0x1<<15) ++#define EP0_OUT_INT (0x1<<16) ++#define EP1_OUT_INT (0x1<<17) ++#define EP2_OUT_INT (0x1<<18) ++#define EP3_OUT_INT (0x1<<19) ++#define EP4_OUT_INT (0x1<<20) ++#define EP5_OUT_INT (0x1<<21) ++#define EP6_OUT_INT (0x1<<22) ++#define EP7_OUT_INT (0x1<<23) ++#define EP8_OUT_INT (0x1<<24) ++#define EP9_OUT_INT (0x1<<25) ++#define EP10_OUT_INT (0x1<<26) ++#define EP11_OUT_INT (0x1<<27) ++#define EP12_OUT_INT (0x1<<28) ++#define EP13_OUT_INT (0x1<<29) ++#define EP14_OUT_INT (0x1<<30) ++#define EP15_OUT_INT (0x1<<31) ++ ++// GOTGINT ++#define SesEndDet (0x1<<2) ++ ++// GRSTCTL ++#define TxFFlsh (0x1<<5) ++#define RxFFlsh (0x1<<4) ++#define INTknQFlsh (0x1<<3) ++#define FrmCntrRst (0x1<<2) ++#define HSftRst (0x1<<1) ++#define CSftRst (0x1<<0) ++ ++#define CLEAR_ALL_EP_INTRS 0xffffffff ++ ++#define EP_INTERRUPT_DISABLE_ALL 0x0 // Bits to write to EP_INT_EN_REG - Use CLEAR ++ ++// DMA control register bit definitions ++#define RUN_OB 0x80 ++#define STATE 0x70 ++#define DEMAND_MODE 0x8 ++#define OUT_DMA_RUN 0x4 ++#define IN_DMA_RUN 0x2 ++#define DMA_MODE_EN 0x1 ++ ++ ++#define REAL_PHYSICAL_ADDR_EP0_FIFO (0x520001c0) //Endpoint 0 FIFO ++#define REAL_PHYSICAL_ADDR_EP1_FIFO (0x520001c4) //Endpoint 1 FIFO ++#define REAL_PHYSICAL_ADDR_EP2_FIFO (0x520001c8) //Endpoint 2 FIFO ++#define REAL_PHYSICAL_ADDR_EP3_FIFO (0x520001cc) //Endpoint 3 FIFO ++#define REAL_PHYSICAL_ADDR_EP4_FIFO (0x520001d0) //Endpoint 4 FIFO ++ ++// GAHBCFG ++#define MODE_DMA (1<<5) ++#define MODE_SLAVE (0<<5) ++#define BURST_SINGLE (0<<1) ++#define BURST_INCR (1<<1) ++#define BURST_INCR4 (3<<1) ++#define BURST_INCR8 (5<<1) ++#define BURST_INCR16 (7<<1) ++#define GBL_INT_MASK (0<<0) ++#define GBL_INT_UNMASK (1<<0) ++ ++// For USB DMA ++//BOOL InitUsbdDriverGlobals(void); //:-) ++//void UsbdDeallocateVm(void); //:-) ++//BOOL UsbdAllocateVm(void); //:-) ++//void UsbdInitDma(int epnum, int bufIndex,int bufOffset); //:-) ++ ++ ++//by Kevin ++ ++////////////////////////////////////////////////////////////////////////// ++ ++/* ++inline u32 ReadReg( ++ u32 uiOffset ++ ) ++{ ++ volatile u32 *pbReg = ctrlr_base_reg_addr(uiOffset); ++ u32 uiValue = (u32) *pbReg; ++ return uiValue; ++} ++ ++inline void WriteReg( ++ u32 uiOffset, ++ u32 bValue ++ ) ++{ ++ volatile ULONG *pbReg = ctrlr_base_reg_addr(uiOffset); ++ *pbReg = (ULONG) bValue; ++} ++ ++inline void UpdateReg( ++ u32 uiOffset, ++ u32 bValue ++ ) ++{ ++ WriteReg(uiOffset, (ReadReg(uiOffset) | bValue)); ++}; ++ ++inline void ClearReg( ++ u32 uiOffeset, ++ u32 bValue ++ ) ++{ ++ WriteReg(uiOffeset, (ReadReg(uiOffeset) & ~bValue)); ++}; ++*/ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif //_S3C6400OTGDEVICE_H_ ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-hcdi-debug.h linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-hcdi-debug.h +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-hcdi-debug.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-hcdi-debug.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,94 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * @file s3c-otg-hcdi-debug.c ++ * @brief It provides debug functions for display message \n ++ * @version ++ * -# Jun 9,2008 v1.0 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Creating the initial version of this code \n ++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Optimizing for performance \n ++ * @see None ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#ifndef _S3C_OTG_HCDI_DEBUG_H_ ++#define _S3C_OTG_HCDI_DEBUG_H_ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++//#define OTG_DEBUG ++ ++#ifdef OTG_DEBUG ++#if 0 ++#include ++#endif ++ ++#define OTG_DBG_OTGHCDI_DRIVER true ++#define OTG_DBG_OTGHCDI_HCD true ++#define OTG_DBG_OTGHCDI_KAL false ++#define OTG_DBG_OTGHCDI_LIST false ++#define OTG_DBG_OTGHCDI_MEM false ++ ++#define OTG_DBG_TRANSFER false ++#define OTG_DBG_SCHEDULE false ++#define OTG_DBG_OCI true ++#define OTG_DBG_DONETRASF false ++#define OTG_DBG_ISR true ++#define OTG_DBG_ROOTHUB false ++ ++#if defined(__linux__) ++ ++#include //for printk ++ ++#define otg_err(is_active, msg...) \ ++ do{ if ((is_active) == true)\ ++ {\ ++ printk(KERN_ERR "otg_err: in %s()::%05d ", __func__ , __LINE__); \ ++ printk("=> " msg); \ ++ }\ ++ }while(0) ++ ++#define otg_dbg(is_active, msg...) \ ++ do{ if ((is_active) == true)\ ++ {\ ++ printk(KERN_DEBUG "otg_dbg: in %s()::%05d ", __func__, __LINE__); \ ++ printk("=> " msg); \ ++ }\ ++ }while(0) ++#else ++ ++#error Not supported OS ++ ++#endif ++ ++#else //OTG_DEBUG ++ ++# define otg_err(is_active, msg...) do{}while(0) ++# define otg_dbg(is_active, msg...) do{}while(0) ++ ++#endif ++ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* _S3C_OTG_HCDI_DEBUG_H_ */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.c linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.c +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,264 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * @file s3c-otg-hcdi-driver.c ++ * @brief It provides functions related with module for OTGHCD driver. \n ++ * @version ++ * -# Jun 9,2008 v1.0 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Creating the initial version of this code \n ++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Optimizing for performance \n ++ * -# Aug 18,2008 v1.3 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Modifying for successful rmmod & disconnecting \n ++ * @see None ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#include "s3c-otg-hcdi-driver.h" ++ ++/** ++ * static int s3c6410_otg_drv_probe (struct platform_device *pdev) ++ * ++ * @brief probe function of OTG hcd platform_driver ++ * ++ * @param [in] pdev : pointer of platform_device of otg hcd platform_driver ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If fail \n ++ * @remark ++ * it allocates resources of it and call other modules' init function. ++ * then call usb_create_hcd, usb_add_hcd, s3c6410_otghcd_start functions ++ */ ++ ++static struct clk *otg_clock = NULL; ++ ++static int s3c6410_otg_drv_probe (struct platform_device *pdev) ++{ ++ ++ int ret_val = 0; ++ u32 reg_val = 0; ++ ++ otg_dbg(OTG_DBG_OTGHCDI_DRIVER, "s3c_otg_drv_probe \n"); ++ ++ otg_clock = clk_get(&pdev->dev, "otg"); ++ if (otg_clock == NULL) { ++ printk(KERN_INFO "failed to find otg clock source\n"); ++ return -ENOENT; ++ } ++ clk_enable(otg_clock); ++ ++///init for host mode ++/** ++ Allocate memory for the base HCD & Initialize the base HCD. ++*/ ++ g_pUsbHcd = usb_create_hcd(&s3c6410_otg_hc_driver, &pdev->dev, pdev->dev.bus_id); ++ if (g_pUsbHcd == NULL) ++ { ++ ret_val = -ENOMEM; ++ otg_err(OTG_DBG_OTGHCDI_DRIVER, "failed to usb_create_hcd\n"); ++ goto err_out_clk; ++ } ++ ++ ++// mapping hcd resource & device resource ++ ++ g_pUsbHcd->rsrc_start = pdev->resource[0].start; ++ g_pUsbHcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1; ++ ++ if (!request_mem_region(g_pUsbHcd->rsrc_start, g_pUsbHcd->rsrc_len, gHcdName)) ++ { ++ otg_err(OTG_DBG_OTGHCDI_DRIVER, "failed to request_mem_region\n"); ++ reg_val = -EBUSY; ++ goto err_out_create_hcd; ++ } ++ ++ ++//Physical address => Virtual address ++ g_pUsbHcd->regs = S3C_VA_OTG; ++ g_pUsbHcd->self.otg_port = 1; ++ ++ g_pUDCBase = (u8 *)g_pUsbHcd->regs; ++ ++ /// call others' init() ++ reg_val = otg_hcd_init_modules(); ++ if( reg_val != USB_ERR_SUCCESS) ++ { ++ otg_err(OTG_DBG_OTGHCDI_DRIVER, "failed to otg_hcd_init_modules\n"); ++ reg_val = USB_ERR_FAIL; ++ goto err_out_create_hcd; ++ } ++ ++ /** ++ * Attempt to ensure this device is really a s3c6410 USB-OTG Controller. ++ * Read and verify the SNPSID register contents. The value should be ++ * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX". ++ */ ++ //reg_val = read_reg_32((unsigned int *)((u8 *)g_pUsbHcd->regs + 0x40)); ++ ++ reg_val = read_reg_32(0x40); ++ if ((reg_val & 0xFFFFF000) != 0x4F542000) ++ { ++ otg_err(OTG_DBG_OTGHCDI_DRIVER, "Bad value for SNPSID: 0x%x\n", reg_val); ++ ret_val = -EINVAL; ++ goto err_out_create_hcd_init; ++ } ++ ++ /* ++ * Finish generic HCD initialization and start the HCD. This function ++ * allocates the DMA buffer pool, registers the USB bus, requests the ++ * IRQ line, and calls s3c6410_otghcd_start method. ++ */ ++ ret_val = usb_add_hcd(g_pUsbHcd, pdev->resource[1].start, IRQF_DISABLED); ++ if (ret_val < 0) ++ { ++ goto err_out_create_hcd_init; ++ } ++ ++ otg_dbg(OTG_DBG_OTGHCDI_DRIVER,"OTG HCD Initialized HCD, bus=%s, usbbus=%d\n", ++ "EMSP OTG Controller", g_pUsbHcd->self.busnum); ++ return USB_ERR_SUCCESS; ++ ++err_out_create_hcd_init: ++ otg_hcd_deinit_modules(); ++ release_mem_region(g_pUsbHcd->rsrc_start, g_pUsbHcd->rsrc_len); ++ ++err_out_create_hcd: ++ usb_put_hcd(g_pUsbHcd); ++ ++err_out_clk: ++ ++ return ret_val; ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * static int s3c6410_otg_drv_remove (struct platform_device *dev) ++ * ++ * @brief remove function of OTG hcd platform_driver ++ * ++ * @param [in] pdev : pointer of platform_device of otg hcd platform_driver ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If fail \n ++ * @remark ++ * This function is called when the otg device unregistered with the ++ * s3c6410_otg_driver. This happens, for example, when the rmmod command is ++ * executed. The device may or may not be electrically present. If it is ++ * present, the driver stops device processing. Any resources used on behalf ++ * of this device are freed. ++ */ ++static int s3c6410_otg_drv_remove (struct platform_device *dev) ++{ ++ otg_dbg(OTG_DBG_OTGHCDI_DRIVER, "s3c6410_otg_drv_remove \n"); ++ ++ otg_hcd_deinit_modules(); ++ ++ usb_remove_hcd(g_pUsbHcd); ++ ++ release_mem_region(g_pUsbHcd->rsrc_start, g_pUsbHcd->rsrc_len); ++ ++ usb_put_hcd(g_pUsbHcd); ++ ++ if (otg_clock != NULL) { ++ clk_disable(otg_clock); ++ clk_put(otg_clock); ++ otg_clock = NULL; ++ } ++ ++ ++ return USB_ERR_SUCCESS; ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * @struct s3c6410_otg_driver ++ * ++ * @brief ++ * This structure defines the methods to be called by a bus driver ++ * during the lifecycle of a device on that bus. Both drivers and ++ * devices are registered with a bus driver. The bus driver matches ++ * devices to drivers based on information in the device and driver ++ * structures. ++ * ++ * The probe function is called when the bus driver matches a device ++ * to this driver. The remove function is called when a device is ++ * unregistered with the bus driver. ++ */ ++static struct platform_driver s3c6410_otg_driver = { ++ .probe = s3c6410_otg_drv_probe, ++ .remove = s3c6410_otg_drv_remove, ++ .shutdown = usb_hcd_platform_shutdown, ++ .driver = { ++ .name = "s3c_otghcd", ++ .owner = THIS_MODULE, ++ }, ++}; ++//------------------------------------------------------------------------------- ++ ++/** ++ * static int __init s3c6410_otg_module_init(void) ++ * ++ * @brief module_init function ++ * ++ * @return it returns result of platform_driver_register ++ * @remark ++ * This function is called when the s3c6410_otg_driver is installed with the ++ * insmod command. It registers the s3c6410_otg_driver structure with the ++ * appropriate bus driver. This will cause the s3c6410_otg_driver_probe function ++ * to be called. In addition, the bus driver will automatically expose ++ * attributes defined for the device and driver in the special sysfs file ++ * system. ++ */ ++static int __init s3c6410_otg_module_init(void) ++{ ++ int ret_val = 0; ++ ++ otg_dbg(OTG_DBG_OTGHCDI_DRIVER, "s3c_otg_module_init \n"); ++ ++ ret_val = platform_driver_register(&s3c6410_otg_driver); ++ if (ret_val < 0) ++ { ++ otg_err(OTG_DBG_OTGHCDI_DRIVER, "platform_driver_register \n"); ++ } ++ return ret_val; ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * static void __exit s3c6410_otg_module_exit(void) ++ * ++ * @brief module_exit function ++ * ++ * @remark ++ * This function is called when the driver is removed from the kernel ++ * with the rmmod command. The driver unregisters itself with its bus ++ * driver. ++ */ ++static void __exit s3c6410_otg_module_exit(void) ++{ ++ otg_dbg(OTG_DBG_OTGHCDI_DRIVER, "s3c_otg_module_exit \n"); ++ platform_driver_unregister(&s3c6410_otg_driver); ++} ++//------------------------------------------------------------------------------- ++ ++module_init(s3c6410_otg_module_init); ++module_exit(s3c6410_otg_module_exit); ++ ++MODULE_DESCRIPTION("OTG USB HOST controller driver"); ++MODULE_AUTHOR("SAMSUNG / System LSI / EMSP"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.h linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.h +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-hcdi-driver.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,74 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * @file s3c-otg-hcdi-driver.h ++ * @brief header of s3c-otg-hcdi-driver \n ++ * @version ++ * -# Jun 9,2008 v1.0 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Creating the initial version of this code \n ++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Optimizing for performance \n ++ * -# Aug 18,2008 v1.3 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Modifying for successful rmmod & disconnecting \n ++ * @see None ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#ifndef _S3C_OTG_HCDI_DRIVER_H_ ++#define _S3C_OTG_HCDI_DRIVER_H_ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++#include ++#include ++//#include //for clk_get, clk_enable etc. ++ ++#include ++#include ++#include ++#include //for SA_SHIRQ ++#include //address for smdk ++#include //dma_alloc_coherent ++#include //request_mem_request ... ++#include //for IRQ_OTG ++#include ++ ++//#include //for ioremap ++ ++#include "s3c-otg-common-common.h" ++#include "s3c-otg-hcdi-debug.h" ++#include "s3c-otg-hcdi-hcd.h" ++#include "s3c-otg-hcdi-kal.h" ++ ++//struct clk* g_pOTG_clock = NULL; ++struct usb_hcd* g_pUsbHcd = NULL; ++ ++volatile u8 * g_pUDCBase; ++ ++static const char gHcdName[] = "EMSP_OTG_HCD"; ++ ++extern int otg_hcd_init_modules(void); ++extern void otg_hcd_deinit_modules(void); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* _S3C_OTG_HCDI_DRIVER_H_ */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.c linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.c +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,655 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * @file s3c-otg-hcdi-hcd.c ++ * @brief implementation of structure hc_drive \n ++ * @version ++ * -# Jun 11,2008 v1.0 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Creating the initial version of this code \n ++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Optimizing for performance \n ++ * -# Aug 18,2008 v1.3 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Modifying for successful rmmod & disconnecting \n ++ * @see None ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#include "s3c-otg-hcdi-hcd.h" ++static DEFINE_SPINLOCK(otg_hcd_spin_lock); ++ ++/** ++ * otg_hcd_init_modules() ++ * ++ * @brief call other modules' init functions ++ * ++ * @return PASS : If success \n ++ * FAIL : If fail \n ++ */ ++int otg_hcd_init_modules(void) ++{ ++ unsigned long spin_lock_flag = 0; ++ ++ otg_dbg(OTG_DBG_OTGHCDI_DRIVER, "OTGHCD_InitModuless \n"); ++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ ++ init_transfer(); ++ init_scheduler(); ++ oci_init(); ++ ++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ ++ return USB_ERR_SUCCESS; ++}; ++ ++/** ++ * void otg_hcd_deinit_modules(void) ++ * ++ * @brief call other modules' de-init functions ++ * ++ * @return PASS : If success \n ++ * FAIL : If fail \n ++ */ ++void otg_hcd_deinit_modules(void) ++{ ++ unsigned long spin_lock_flag = 0; ++ ++ otg_dbg(OTG_DBG_OTGHCDI_DRIVER, "otg_hcd_deinit_modules \n"); ++ ++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ ++ deinit_transfer(); ++ ++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++} ++ ++/** ++ * irqreturn_t (*s3c6410_otghcd_irq) (struct usb_hcd *hcd) ++ * ++ * @brief interrupt handler of otg irq ++ * ++ * @param [in] hcd : pointer of usb_hcd ++ * ++ * @return IRQ_HANDLED \n ++ */ ++irqreturn_t s3c6410_otghcd_irq(struct usb_hcd *hcd) ++{ ++ ++ unsigned long spin_lock_flag = 0; ++ ++ otg_dbg(false, "s3c6410_otghcd_irq \n"); ++ ++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ otg_handle_interrupt(); ++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ ++ ++ return IRQ_HANDLED; ++} ++//------------------------------------------------------------------------------- ++ ++ ++/** ++ * int s3c6410_otghcd_start(struct usb_hcd *hcd) ++ * ++ * @brief initialize and start otg hcd ++ * ++ * @param [in] usb_hcd_p : pointer of usb_hcd ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ */ ++int s3c6410_otghcd_start(struct usb_hcd *usb_hcd_p) ++{ ++ struct usb_bus *usb_bus_p; ++ ++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "s3c6410_otghcd_start \n"); ++ ++ usb_bus_p = hcd_to_bus(usb_hcd_p); ++ ++ //* Initialize and connect root hub if one is not already attached */ ++ if (usb_bus_p->root_hub) { ++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "OTG HCD Has Root Hub\n"); ++ ++ //* Inform the HUB driver to resume. */ ++ otg_usbcore_resume_roothub(); ++ } else { ++ otg_err(OTG_DBG_OTGHCDI_HCD, "OTG HCD Does Not Have Root Hub\n"); ++ return USB_ERR_FAIL; ++ } ++ ++ usb_hcd_p->poll_rh = 1; ++ usb_hcd_p->uses_new_polling = 1; ++ ++ ///init bus state before enable irq ++ usb_hcd_p->state = HC_STATE_RUNNING; ++ ++ oci_start();//enable irq ++ ++ return USB_ERR_SUCCESS; ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * void s3c6410_otghcd_stop(struct usb_hcd *hcd) ++ * ++ * @brief deinitialize and stop otg hcd ++ * ++ * @param [in] hcd : pointer of usb_hcd ++ * ++ */ ++void s3c6410_otghcd_stop(struct usb_hcd *hcd) ++{ ++ unsigned long spin_lock_flag = 0; ++ ++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "s3c6410_otghcd_stop \n"); ++ ++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ otg_hcd_deinit_modules(); ++ oci_stop(); ++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * void s3c6410_otghcd_shutdown(struct usb_hcd *hcd) ++ * ++ * @brief shutdown otg hcd ++ * ++ * @param [in] usb_hcd_p : pointer of usb_hcd ++ * ++ */ ++void s3c6410_otghcd_shutdown(struct usb_hcd *usb_hcd_p) ++{ ++ ++ unsigned long spin_lock_flag = 0; ++ ++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "s3c6410_otghcd_shutdown \n"); ++ otg_hcd_deinit_modules(); ++ ++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ oci_stop(); ++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ ++ free_irq(IRQ_OTG, usb_hcd_p); ++ usb_hcd_p->state = HC_STATE_HALT; ++ otg_usbcore_hc_died(); ++} ++//------------------------------------------------------------------------------- ++ ++ ++/** ++ * int s3c6410_otghcd_get_frame_number(struct usb_hcd *hcd) ++ * ++ * @brief get currnet frame number ++ * ++ * @param [in] hcd : pointer of usb_hcd ++ * ++ * @return ret : frame number \n ++ */ ++int s3c6410_otghcd_get_frame_number(struct usb_hcd *hcd) ++{ ++ int ret = 0; ++ unsigned long spin_lock_flag = 0; ++ ++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "s3c6410_otghcd_get_frame_number \n"); ++ ++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ ret = oci_get_frame_num(); ++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ return ret; ++} ++//------------------------------------------------------------------------------- ++ ++ ++/** ++ * int s3c6410_otghcd_urb_enqueue() ++ * ++ * @brief enqueue a urb to otg hcd ++ * ++ * @param [in] hcd : pointer of usb_hcd ++ * [in] ep : pointer of usb_host_endpoint ++ * [in] urb : pointer of urb ++ * [in] mem_flags : type of gfp_t ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ */ ++int ++s3c6410_otghcd_urb_enqueue ++( ++ struct usb_hcd *hcd, ++ struct urb *urb, ++ gfp_t mem_flags ++) ++{ ++ ++ int ret_val = 0; ++ u32 trans_flag = 0; ++ u32 return_td_addr = 0; ++ u8 dev_speed, ed_type = 0, additional_multi_count; ++ u16 max_packet_size; ++ ++ u8 dev_addr = 0; ++ u8 ep_num = 0; ++ bool f_is_ep_in = true; ++ u8 interval = 0; ++ u32 sched_frame = 0; ++ u8 hub_addr = 0; ++ u8 hub_port = 0; ++ bool f_is_do_split = false; ++ ed_t *target_ed = NULL; ++ isoch_packet_desc_t *new_isoch_packet_desc = NULL; ++ ++ otg_dbg(false, "s3c6410_otghcd_urb_enqueue \n"); ++ ++ /// check ep has ed_t or not ++ if(!(urb->ep->hcpriv)) ++ { ++ ///for getting dev_speed ++ switch (urb->dev->speed) ++ { ++ case USB_SPEED_HIGH : ++ dev_speed = HIGH_SPEED_OTG; break; ++ ++ case USB_SPEED_FULL : ++ dev_speed = FULL_SPEED_OTG; break; ++ ++ case USB_SPEED_LOW : ++ dev_speed = LOW_SPEED_OTG; break; ++ ++ default: ++ otg_err(OTG_DBG_OTGHCDI_HCD, "unKnown Device Speed \n"); ++ return USB_ERR_FAIL; ++ } ++ ++ ///for getting ed_type ++ switch (usb_pipetype(urb->pipe)) ++ { ++ case PIPE_BULK : ++ ed_type = BULK_TRANSFER; break; ++ ++ case PIPE_INTERRUPT : ++ ed_type = INT_TRANSFER; break; ++ ++ case PIPE_CONTROL : ++ ed_type = CONTROL_TRANSFER; break; ++ ++ case PIPE_ISOCHRONOUS : ++ ed_type = ISOCH_TRANSFER; break; ++ default: ++ otg_err(OTG_DBG_OTGHCDI_HCD, "unKnown ep type \n"); ++ return USB_ERR_FAIL; ++ } ++ ++ max_packet_size = usb_maxpacket(urb->dev, urb->pipe, !(usb_pipein(urb->pipe))); ++ additional_multi_count = ((max_packet_size) >> 11) & 0x03; ++ dev_addr = usb_pipedevice(urb->pipe); ++ ep_num = usb_pipeendpoint(urb->pipe); ++ f_is_ep_in = usb_pipein(urb->pipe) ? true : false; ++ interval = (u8)(urb->interval); ++ sched_frame = (u8)(urb->start_frame); ++ ++ //check ++ if(urb->dev->tt == NULL) ++ { ++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "urb->dev->tt == NULL\n"); ++ hub_port = 0; //u8 hub_port ++ hub_addr = 0; //u8 hub_addr, ++ } ++ else ++ { ++ hub_port = (u8)(urb->dev->ttport); //u8 hub_port, ++ if (urb->dev->tt->hub) { ++ if ( ((dev_speed == FULL_SPEED_OTG) || (dev_speed == LOW_SPEED_OTG)) && ++ (urb->dev->tt) && (urb->dev->tt->hub->devnum != 1)) { ++ f_is_do_split = true; ++ } ++ ++ hub_addr = (u8)(urb->dev->tt->hub->devnum);//u8 hub_addr, ++ } ++ if (urb->dev->tt->multi) { ++ hub_addr = 0x80;//u8 hub_addr, ++ } ++ } ++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "hub_port=%d, hub_addr=%d\n", hub_port, hub_addr); ++ ++ ret_val = create_ed(&target_ed); ++ if(ret_val != USB_ERR_SUCCESS) ++ { ++ otg_err(OTG_DBG_OTGHCDI_HCD, "fail to create_ed() \n"); ++ return ret_val; ++ } ++ ++ ret_val = init_ed( target_ed, ++ dev_addr, ++ ep_num, ++ f_is_ep_in, ++ dev_speed, ++ ed_type, ++ max_packet_size, ++ additional_multi_count, ++ interval, ++ sched_frame, ++ hub_addr, ++ hub_port, ++ f_is_do_split, ++ (void *)urb->ep); ++ ++ if(ret_val != USB_ERR_SUCCESS) ++ { ++ otg_err(OTG_DBG_OTGHCDI_HCD, "fail to init_ed() :err = %d \n",(int)ret_val); ++ otg_mem_free(target_ed); ++ return USB_ERR_FAIL; ++ } ++ ++ urb->ep->hcpriv = (void *)(target_ed); ++ } // if(!(ep->hcpriv)) ++ else ++ { ++ dev_addr = usb_pipedevice(urb->pipe); ++ if(((ed_t *)(urb->ep->hcpriv))->ed_desc.device_addr != dev_addr) ++ { ++ ((ed_t *)urb->ep->hcpriv)->ed_desc.device_addr = dev_addr; ++ } ++ } ++ ++ target_ed = (ed_t *)urb->ep->hcpriv; ++ ++ if(urb->transfer_flags & URB_SHORT_NOT_OK) ++ trans_flag += USB_TRANS_FLAG_NOT_SHORT; ++ if (urb->transfer_flags & URB_ISO_ASAP) ++ trans_flag += USB_TRANS_FLAG_ISO_ASYNCH; ++ ++ if(ed_type == ISOCH_TRANSFER) ++ { ++ otg_err(OTG_DBG_OTGHCDI_HCD, "ISO not yet supported \n"); ++ return USB_ERR_FAIL; ++ } ++ ++ if (!HC_IS_RUNNING(hcd->state)) { ++ otg_err(OTG_DBG_OTGHCDI_HCD, "!HC_IS_RUNNING(hcd->state) \n"); ++ return -USB_ERR_NODEV; ++ } ++ ++ /* in case of unlink-during-submit */ ++ if (urb->status != -EINPROGRESS) { ++ urb->hcpriv = NULL; ++ usb_hcd_giveback_urb(hcd, urb, urb->status); ++ return USB_ERR_SUCCESS; ++ } ++ ++ ret_val = issue_transfer( target_ed, (void *)NULL, (void *)NULL, ++ trans_flag, ++ (usb_pipetype(urb->pipe) == PIPE_CONTROL)?true:false, ++ (u32)urb->setup_packet, (u32)urb->setup_dma, ++ (u32)urb->transfer_buffer, (u32)urb->transfer_dma, ++ (u32)urb->transfer_buffer_length, ++ (u32)urb->start_frame,(u32)urb->number_of_packets, ++ new_isoch_packet_desc, (void *)urb, &return_td_addr); ++ ++ if(ret_val != USB_ERR_SUCCESS) ++ { ++ otg_err(OTG_DBG_OTGHCDI_HCD, "fail to issue_transfer() \n"); ++ return USB_ERR_FAIL; ++ } ++ urb->hcpriv = (void *)return_td_addr; ++ ++ return USB_ERR_SUCCESS; ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * int s3c6410_otghcd_urb_dequeue(struct usb_hcd *_hcd, struct urb *_urb ) ++ * ++ * @brief dequeue a urb to otg ++ * ++ * @param [in] _hcd : pointer of usb_hcd ++ * [in] _urb : pointer of urb ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ */ ++int s3c6410_otghcd_urb_dequeue(struct usb_hcd *_hcd, struct urb *_urb, int status) ++{ ++ int ret_val = 0; ++ ++ unsigned long spin_lock_flag = 0; ++ td_t * cancel_td = (td_t *)_urb->hcpriv; ++ ++ if (cancel_td == NULL) ++ { ++ otg_err(OTG_DBG_OTGHCDI_HCD, "cancel_td == NULL\n"); ++ return USB_ERR_FAIL; ++ } ++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "s3c6410_otghcd_urb_dequeue, status = %d\n", status); ++ ++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ ++ ret_val = usb_hcd_check_unlink_urb(_hcd, _urb, status); ++ if (ret_val) { ++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "ret_val = %d\n", ret_val); ++ goto done; ++ } ++ ++ if (!HC_IS_RUNNING(_hcd->state)) { ++ otg_err(OTG_DBG_OTGHCDI_HCD, "!HC_IS_RUNNING(hcd->state) \n"); ++ usb_hcd_giveback_urb(_hcd, _urb, status); ++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ return USB_ERR_SUCCESS; ++ } ++ ++ ret_val = cancel_transfer(cancel_td->parent_ed_p, cancel_td); ++ if(ret_val != USB_ERR_DEQUEUED && ret_val != USB_ERR_NOELEMENT) ++ { ++ otg_err(OTG_DBG_OTGHCDI_HCD, "fail to cancel_transfer() \n"); ++ usb_hcd_giveback_urb(_hcd, _urb, status); ++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ return USB_ERR_FAIL; ++ } ++ ret_val = USB_ERR_SUCCESS; ++done: ++ usb_hcd_giveback_urb(_hcd, _urb, status); ++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ return ret_val; ++} ++//------------------------------------------------------------------------------- ++ ++ ++/** ++ * void s3c6410_otghcd_endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep) ++ * ++ * @brief disable a endpoint ++ * ++ * @param [in] hcd : pointer of usb_hcd ++ * [in] ep : pointer of usb_host_endpoint ++ */ ++void s3c6410_otghcd_endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep) ++{ ++ int ret_val = 0; ++ unsigned long spin_lock_flag = 0; ++ ++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "s3c6410_otghcd_endpoint_disable \n"); ++ ++ if(!((ed_t *)ep->hcpriv)) ++ return; ++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ ret_val = delete_ed((ed_t *)ep->hcpriv); ++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ ++ if(ret_val != USB_ERR_SUCCESS) ++ { ++ otg_err(OTG_DBG_OTGHCDI_HCD, "fail to delete_ed() \n"); ++ return ; ++ } ++ ++ ep->hcpriv = NULL; ++} ++//------------------------------------------------------------------------------- ++ ++ ++/** ++ * int s3c6410_otghcd_hub_status_data(struct usb_hcd *_hcd, char *_buf) ++ * ++ * @brief get status of root hub ++ * ++ * @param [in] _hcd : pointer of usb_hcd ++ * [inout] _buf : pointer of buffer for write a status data ++ * ++ * @return ret_val : return port status \n ++ */ ++int s3c6410_otghcd_hub_status_data(struct usb_hcd *_hcd, char *_buf) ++{ ++ int ret_val = 0; ++ unsigned long spin_lock_flag = 0; ++ ++ otg_dbg(false, "s3c6410_otghcd_hub_status_data \n"); ++ ++ /* if !USB_SUSPEND, root hub timers won't get shut down ... */ ++ if (!HC_IS_RUNNING(_hcd->state)) ++ return 0; ++ ++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ ret_val = get_otg_port_status(OTG_PORT_NUMBER, _buf); ++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ ++ return (int)ret_val; ++} ++//------------------------------------------------------------------------------- ++ ++ ++/** ++ * int s3c6410_otghcd_hub_control() ++ * ++ * @brief control root hub ++ * ++ * @param [in] hcd : pointer of usb_hcd ++ * [in] typeReq : type of control request ++ * [in] value : value ++ * [in] index : index ++ * [in] buf_p : pointer of urb ++ * [in] length : type of gfp_t ++ * ++ * @return ret_val : return root_hub_feature \n ++ */ ++int ++s3c6410_otghcd_hub_control ++( ++ struct usb_hcd *hcd, ++ u16 typeReq, ++ u16 value, ++ u16 index, ++ char* buf_p, ++ u16 length ++) ++{ ++ int ret_val = 0; ++ unsigned long spin_lock_flag = 0; ++ ++ otg_dbg(false, "s3c6410_otghcd_hub_control \n"); ++ ++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ ++ ret_val = root_hub_feature(OTG_PORT_NUMBER, typeReq, value, (void *)buf_p); ++ ++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ if(ret_val != USB_ERR_SUCCESS) ++ { ++ otg_err(OTG_DBG_OTGHCDI_HCD, "fail to root_hub_feature() \n"); ++ return ret_val; ++ } ++ return (int)ret_val; ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * int s3c6410_otghcd_bus_suspend(struct usb_hcd *hcd) ++ * ++ * @brief suspend otg hcd ++ * ++ * @param [in] hcd : pointer of usb_hcd ++ * ++ * @return USB_ERR_SUCCESS \n ++ */ ++int s3c6410_otghcd_bus_suspend(struct usb_hcd *hcd) ++{ ++ unsigned long spin_lock_flag = 0; ++ ++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "s3c6410_otghcd_bus_suspend \n"); ++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ bus_suspend(); ++ ++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ return USB_ERR_SUCCESS; ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * int s3c6410_otghcd_bus_resume(struct usb_hcd *hcd) ++ * ++ * @brief resume otg hcd ++ * ++ * @param [in] hcd : pointer of usb_hcd ++ * ++ * @return USB_ERR_SUCCESS \n ++ */ ++int s3c6410_otghcd_bus_resume(struct usb_hcd *hcd) ++{ ++ unsigned long spin_lock_flag = 0; ++ ++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "s3c6410_otghcd_bus_resume \n"); ++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ if(bus_resume() != USB_ERR_SUCCESS) ++ { ++ return USB_ERR_FAIL; ++ } ++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ return USB_ERR_SUCCESS; ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * int s3c6410_otghcd_start_port_reset(struct usb_hcd *hcd, unsigned port) ++ * ++ * @brief reset otg port ++ * ++ * @param [in] hcd : pointer of usb_hcd ++ * [in] port : number of port ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * ret_val : If call fail \n ++ */ ++int s3c6410_otghcd_start_port_reset(struct usb_hcd *hcd, unsigned port) ++{ ++ int ret_val = 0; ++ ++ unsigned long spin_lock_flag = 0; ++ ++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "s3c6410_otghcd_start_port_reset \n"); ++ spin_lock_irg_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ ++ ret_val = reset_and_enable_port(OTG_PORT_NUMBER); ++ ++ spin_unlock_irq_save_otg(&otg_hcd_spin_lock, spin_lock_flag); ++ if(ret_val != USB_ERR_SUCCESS) ++ { ++ otg_err(OTG_DBG_OTGHCDI_HCD, "fail to reset_and_enable_port() \n"); ++ return ret_val; ++ } ++ return USB_ERR_SUCCESS; ++} ++//------------------------------------------------------------------------------- ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.h linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.h +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-hcdi-hcd.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,144 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * @file s3c-otg-hcdi-hcd.h ++ * @brief header of s3c-otg-hcdi-hcd \n ++ * @version ++ * -# Jun 9,2008 v1.0 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Creating the initial version of this code \n ++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Optimizing for performance \n ++ * -# Aug 18,2008 v1.3 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Modifying for successful rmmod & disconnecting \n ++ * @see None ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#ifndef _S3C_OTG_HCDI_HCD_H_ ++#define _S3C_OTG_HCDI_HCD_H_ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++//for IRQ_NONE (0) IRQ_HANDLED (1) IRQ_RETVAL(x) ((x) != 0) ++#include ++ ++#include ++//#include <../drivers/usb/core/hcd.h> ++ ++#include "s3c-otg-hcdi-debug.h" ++#include "s3c-otg-hcdi-kal.h" ++ ++#include "s3c-otg-common-common.h" ++#include "s3c-otg-common-datastruct.h" ++#include "s3c-otg-common-const.h" ++ ++#include "s3c-otg-transfer-transfer.h" ++#include "s3c-otg-oci.h" ++#include "s3c-otg-roothub.h" ++ ++//placed in ISR ++extern void otg_handle_interrupt(void); ++ ++int otg_hcd_init_modules(void); ++void otg_hcd_deinit_modules(void); ++ ++ ++irqreturn_t s3c6410_otghcd_irq(struct usb_hcd *hcd); ++ ++int s3c6410_otghcd_start(struct usb_hcd *hcd); ++void s3c6410_otghcd_stop(struct usb_hcd *hcd); ++void s3c6410_otghcd_shutdown(struct usb_hcd *hcd); ++ ++int s3c6410_otghcd_get_frame_number(struct usb_hcd *hcd); ++ ++int s3c6410_otghcd_urb_enqueue( ++ struct usb_hcd *hcd, ++ struct urb *urb, ++ gfp_t mem_flags); ++ ++int s3c6410_otghcd_urb_dequeue( ++ struct usb_hcd *_hcd, ++ struct urb *_urb, ++ int status); ++ ++void s3c6410_otghcd_endpoint_disable( ++ struct usb_hcd *hcd, ++ struct usb_host_endpoint *ep); ++ ++int s3c6410_otghcd_hub_status_data( ++ struct usb_hcd *_hcd, ++ char *_buf); ++ ++int s3c6410_otghcd_hub_control( ++ struct usb_hcd *hcd, ++ u16 type_req, ++ u16 value, ++ u16 index, ++ char * buf, ++ u16 length); ++ ++int s3c6410_otghcd_bus_suspend(struct usb_hcd *hcd); ++int s3c6410_otghcd_bus_resume(struct usb_hcd *hcd); ++int s3c6410_otghcd_start_port_reset(struct usb_hcd *hcd, unsigned port); ++ ++/** ++ * @struct hc_driver s3c6410_otg_hc_driver ++ * ++ * @brief implementation of hc_driver for OTG HCD ++ * ++ * describe in detail ++ */ ++static const struct hc_driver s3c6410_otg_hc_driver = { ++ .description = "EMSP_OTGHCD", ++ .product_desc = "S3C OTGHCD", ++ ++ .irq = s3c6410_otghcd_irq, ++ .flags = HCD_MEMORY | HCD_USB2, ++ ++ /** basic lifecycle operations */ ++ //.reset = ++ .start = s3c6410_otghcd_start, ++ //.suspend = , ++ //.resume = , ++ .stop = s3c6410_otghcd_stop, ++ .shutdown = s3c6410_otghcd_shutdown, ++ ++ /** managing i/o requests and associated device resources */ ++ .urb_enqueue = s3c6410_otghcd_urb_enqueue, ++ .urb_dequeue = s3c6410_otghcd_urb_dequeue, ++ .endpoint_disable = s3c6410_otghcd_endpoint_disable, ++ ++ /** scheduling support */ ++ .get_frame_number = s3c6410_otghcd_get_frame_number, ++ ++ /** root hub support */ ++ .hub_status_data = s3c6410_otghcd_hub_status_data, ++ .hub_control = s3c6410_otghcd_hub_control, ++ //.hub_irq_enable = ++ .bus_suspend = s3c6410_otghcd_bus_suspend, ++ .bus_resume = s3c6410_otghcd_bus_resume, ++ .start_port_reset = s3c6410_otghcd_start_port_reset, ++}; ++ ++#ifdef __cplusplus ++} ++#endif ++#endif /* _S3C_OTG_HCDI_HCD_H_ */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-hcdi-kal.h linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-hcdi-kal.h +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-hcdi-kal.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-hcdi-kal.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,407 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * @file s3c-otg-hcdi-kal.h ++ * @brief header of s3c-otg-hcdi-kal \n ++ * @version ++ * -# Jun 9,2008 v1.0 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Creating the initial version of this code \n ++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Optimizing for performance \n ++ * -# Aug 18,2008 v1.3 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Modifying for successful rmmod & disconnecting \n ++ * @see None ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#ifndef _S3C_OTG_HCDI_KAL_H_ ++#define _S3C_OTG_HCDI_KAL_H_ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++#include "s3c-otg-hcdi-debug.h" ++#include "s3c-otg-common-common.h" ++#include "s3c-otg-common-datastruct.h" ++#include "s3c-otg-common-const.h" ++ ++#include //for readl, writel ++#include //for usb_device_driver, enum usb_device_speed ++#include ++#include <../drivers/usb/core/hcd.h> ++ ++extern volatile u8 * g_pUDCBase; ++extern struct usb_hcd* g_pUsbHcd; ++ ++ ++#if defined(__linux__) ++ ++#include ++#define SPINLOCK_t spinlock_t ++#define SPIN_LOCK_INIT SPIN_LOCK_UNLOCKED ++ ++#else ++ ++#error Not supported OS ++ ++#endif ++ ++#define spin_lock_otg(lock) spin_lock(lock) ++#define spin_lock_irg_otg(lock) spin_lock_irq(lock) ++#define spin_lock_irg_save_otg(lock, flags) spin_lock_irqsave(lock, flags) ++ ++#define spin_unlock_otg(lock) spin_unlock(lock) ++#define spin_unlock_irq_otg(lock) spin_unlock_irq(lock) ++#define spin_unlock_irq_save_otg(lock, flags) spin_unlock_irqrestore(lock, flags) ++ ++#define ctrlr_base_reg_addr(offset) \ ++ ((volatile unsigned int *)((g_pUDCBase) + (offset))) ++/** ++ * otg_kal_make_ep_null ++ * ++ * @brief make ep->hcpriv NULL ++ * ++ * @param [in] pdelete_ed : pointer of ed ++ * ++ * @return void \n ++ */ ++static inline void ++otg_kal_make_ep_null ++( ++ ed_t *pdelete_ed ++) ++{ ++ ((struct usb_host_endpoint *)(pdelete_ed->ed_private))->hcpriv = NULL; ++} ++//--------------------------------------------------------------------------------------- ++ ++/** ++ * otg_kal_is_ep_null ++ * ++ * @brief check ep->hcpriv is NULL or not ++ * ++ * @param [in] pdelete_ed : pointer of ed ++ * ++ * @return bool \n ++ */ ++static inline bool ++otg_kal_is_ep_null ++( ++ ed_t *pdelete_ed ++) ++{ ++ if (((struct usb_host_endpoint *)(pdelete_ed->ed_private))->hcpriv == NULL) ++ return true; ++ else ++ return false; ++} ++//--------------------------------------------------------------------------------------- ++ ++ ++/** ++ * int otg_usbcore_get_calc_bustime() ++ * ++ * @brief get bus time of usbcore ++ * ++ * @param [in] speed : usb speed ++ * [in] is_input : input or not ++ * [in] is_isoch : isochronous or not ++ * [in] byte_count : bytes ++ * ++ * @return bus time of usbcore \n ++ */ ++static inline int ++otg_usbcore_get_calc_bustime ++( ++ u8 speed, ++ bool is_input, ++ bool is_isoch, ++ unsigned int byte_count ++) ++{ ++ unsigned int convert_speed = 0; ++ ++ otg_dbg(OTG_DBG_OTGHCDI_KAL, "otg_usbcore_get_calc_bustime \n"); ++/* enum usb_device_speed { ++ USB_SPEED_UNKNOWN = 0, ++ USB_SPEED_LOW, USB_SPEED_FULL, ++ USB_SPEED_HIGH, ++ USB_SPEED_VARIABLE, };*/ ++ switch(speed) ++ { ++ case HIGH_SPEED_OTG : convert_speed = USB_SPEED_HIGH; break; ++ case FULL_SPEED_OTG : convert_speed = USB_SPEED_FULL; break; ++ case LOW_SPEED_OTG : convert_speed = USB_SPEED_LOW; break; ++ default: convert_speed = USB_SPEED_UNKNOWN; break; ++ } ++ return usb_calc_bus_time(convert_speed, is_input, (unsigned int)is_isoch, byte_count); ++} ++ ++//------------------------------------------------------------------------------- ++ ++/** ++ * void otg_usbcore_giveback(td_t td_p) ++ * ++ * @brief give-back a td as urb ++ * ++ * @param [in] td_p : pointer of td_t to give back ++ * ++ * @return void \n ++ */ ++static inline void ++otg_usbcore_giveback(td_t * td_p) ++{ ++ struct urb *urb_p = NULL; ++ ++// otg_dbg(OTG_DBG_OTGHCDI_KAL, "otg_usbcore_giveback \n"); ++ if (td_p->td_private == NULL) ++ { ++ otg_err(OTG_DBG_OTGHCDI_KAL, "td_p->td_private == NULL \n"); ++ return; ++ } ++ ++ urb_p = (struct urb *)td_p->td_private; ++ ++ urb_p->actual_length = (int)(td_p->transferred_szie); ++ urb_p->status = (int)(td_p->error_code); ++ urb_p->error_count = (int)(td_p->err_cnt); ++ urb_p->hcpriv = NULL; ++ ++ usb_hcd_giveback_urb(g_pUsbHcd, urb_p, urb_p->status); ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * void otg_usbcore_hc_died(void) ++ * ++ * @brief inform usbcore of hc die ++ * ++ * @return void \n ++ */ ++static inline void ++otg_usbcore_hc_died(void) ++{ ++ otg_dbg(OTG_DBG_OTGHCDI_KAL, "otg_usbcore_hc_died \n"); ++ usb_hc_died(g_pUsbHcd); ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * void otg_usbcore_poll_rh_status(void) ++ * ++ * @brief invoke usbcore's usb_hcd_poll_rh_status ++ * ++ * @param void ++ * ++ * @return void \n ++ */ ++static inline void ++otg_usbcore_poll_rh_status(void) ++{ ++ usb_hcd_poll_rh_status(g_pUsbHcd); ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * void otg_usbcore_resume_roothub(void) ++ * ++ * @brief invoke usbcore's usb_hcd_resume_root_hub ++ * ++ * @param void ++ * ++ * @return void \n ++ */ ++static inline void ++otg_usbcore_resume_roothub(void) ++{ ++ otg_dbg(OTG_DBG_OTGHCDI_KAL, "otg_usbcore_resume_roothub \n"); ++ usb_hcd_resume_root_hub(g_pUsbHcd); ++}; ++//------------------------------------------------------------------------------- ++ ++/** ++ * int otg_usbcore_inc_usb_bandwidth(u32 band_width) ++ * ++ * @brief increase bandwidth of usb bus ++ * ++ * @param [in] band_width : bandwidth to be increased ++ * ++ * @return USB_ERR_SUCCESS \n ++ */ ++static inline int ++otg_usbcore_inc_usb_bandwidth(u32 band_width) ++{ ++ otg_dbg(OTG_DBG_OTGHCDI_KAL, "otg_usbcore_inc_usb_bandwidth \n"); ++ hcd_to_bus(g_pUsbHcd)->bandwidth_allocated += band_width; ++ return USB_ERR_SUCCESS; ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * int otg_usbcore_des_usb_bandwidth(u32 uiBandwidth) ++ * ++ * @brief decrease bandwidth of usb bus ++ * ++ * @param [in] band_width : bandwidth to be decreased ++ * ++ * @return USB_ERR_SUCCESS \n ++ */ ++static inline int ++otg_usbcore_des_usb_bandwidth(u32 band_width) ++{ ++ otg_dbg(OTG_DBG_OTGHCDI_KAL, "otg_usbcore_des_usb_bandwidth \n"); ++ hcd_to_bus(g_pUsbHcd)->bandwidth_allocated -= band_width; ++ return USB_ERR_SUCCESS; ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * int otg_usbcore_inc_periodic_transfer_cnt(u8 transfer_type) ++ * ++ * @brief increase count of periodic transfer ++ * ++ * @param [in] transfer_type : type of transfer ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ */ ++static inline int ++otg_usbcore_inc_periodic_transfer_cnt(u8 transfer_type) ++{ ++ otg_dbg(OTG_DBG_OTGHCDI_KAL, "otg_usbcore_inc_periodic_transfer_cnt \n"); ++ ++ switch(transfer_type) ++ { ++ case INT_TRANSFER : ++ hcd_to_bus(g_pUsbHcd)->bandwidth_int_reqs++; ++ break; ++ case ISOCH_TRANSFER : ++ hcd_to_bus(g_pUsbHcd)->bandwidth_isoc_reqs++; ++ break; ++ default: ++ otg_err(OTG_DBG_OTGHCDI_KAL, "not proper TransferType for otg_usbcore_inc_periodic_transfer_cnt()\n"); ++ return USB_ERR_FAIL; ++ } ++ return USB_ERR_SUCCESS; ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * int otg_usbcore_des_periodic_transfer_cnt(u8 transfer_type) ++ * ++ * @brief decrease count of periodic transfer ++ * ++ * @param [in] transfer_type : type of transfer ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ */ ++static inline int ++otg_usbcore_des_periodic_transfer_cnt(u8 transfer_type) ++{ ++ otg_dbg(OTG_DBG_OTGHCDI_KAL, "otg_usbcore_des_periodic_transfer_cnt \n"); ++ ++ switch(transfer_type) ++ { ++ case INT_TRANSFER : ++ hcd_to_bus(g_pUsbHcd)->bandwidth_int_reqs--; ++ break; ++ case ISOCH_TRANSFER : ++ hcd_to_bus(g_pUsbHcd)->bandwidth_isoc_reqs--; ++ break; ++ default: ++ otg_err(OTG_DBG_OTGHCDI_KAL, "not proper TransferType for otg_usbcore_des_periodic_transfer_cnt()\n"); ++ return USB_ERR_FAIL; ++ } ++ return USB_ERR_SUCCESS; ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * u32 read_reg_32(u32 offset) ++ * ++ * @brief Reads the content of a register. ++ * ++ * @param [in] offset : offset of address of register to read. ++ * ++ * @return contents of the register. \n ++ * @remark call readl() ++ */ ++static inline u32 read_reg_32(u32 offset) ++{ ++ volatile unsigned int * reg_addr_p = ctrlr_base_reg_addr(offset); ++ return *reg_addr_p; ++ //return readl(reg_addr_p); ++}; ++//------------------------------------------------------------------------------- ++ ++/** ++ * void write_reg_32( u32 offset, const u32 value) ++ * ++ * @brief Writes a register with a 32 bit value. ++ * ++ * @param [in] offset : offset of address of register to write. ++ * @param [in] value : value to write ++ * ++ * @remark call writel() ++ */ ++static inline void write_reg_32( u32 offset, const u32 value) ++{ ++ volatile unsigned int * reg_addr_p = ctrlr_base_reg_addr(offset); ++ *reg_addr_p = value; ++ //writel( value, reg_addr_p ); ++}; ++//------------------------------------------------------------------------------- ++ ++/** ++ * void update_reg_32(u32 offset, u32 value) ++ * ++ * @brief logic or operation ++ * ++ * @param [in] offset : offset of address of register to write. ++ * @param [in] value : value to or ++ * ++ */ ++static inline void update_reg_32(u32 offset, u32 value) ++{ ++ write_reg_32(offset, (read_reg_32(offset) | value)); ++} ++//--------------------------------------------------------------------------------------- ++ ++/** ++ * void clear_reg_32(u32 offset, u32 value) ++ * ++ * @brief logic not operation ++ * ++ * @param [in] offset : offset of address of register to write. ++ * @param [in] value : value to not ++ * ++ */ ++static inline void clear_reg_32(u32 offset, u32 value) ++{ ++ write_reg_32(offset, (read_reg_32(offset) & ~value)); ++} ++//--------------------------------------------------------------------------------------- ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* _S3C_OTG_HCDI_KAL_H_ */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-hcdi-list.h linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-hcdi-list.h +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-hcdi-list.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-hcdi-list.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,225 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * @file s3c-otg-hcdi-list.h ++ * @brief list functions for otg \n ++ * @version ++ * -# Jun 9,2008 v1.0 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Creating the initial version of this code \n ++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Optimizing for performance \n ++ * @see None ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#ifndef _S3C_OTG_HCDI_LIST_H_ ++#define _S3C_OTG_HCDI_LIST_H_ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++#include "s3c-otg-common-common.h" ++#include "s3c-otg-hcdi-debug.h" ++ ++#if defined(__linux__) ++ ++#include ++ ++typedef struct list_head otg_list_head; ++ ++#else ++ ++#error Not supported OS ++ ++#endif ++ ++#define otg_list_get_node(ptr, type, member) container_of(ptr, type, member) ++ ++ ++#define otg_list_for_each_safe(pos, n, head) \ ++ for (pos = (head)->next, n = pos->next; pos != (head); \ ++ pos = n, n = pos->next) ++ ++ ++/** ++ * void otg_list_push_next(otg_list_head *new_node_p, otg_list_head *list_head_p) ++ * ++ * @brief push a list node into the next of head ++ * ++ * @param [in] new_node_p : node to be pushed ++ * @param [in] otg_list_head : target list head ++ * ++ * @return void \n ++ */ ++ ++static inline ++void otg_list_push_next(otg_list_head *new_node_p, otg_list_head *list_head_p) ++{ ++ otg_dbg(OTG_DBG_OTGHCDI_LIST, "otg_list_push_next \n"); ++ list_add(new_node_p, list_head_p); ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * void otg_list_push_prev(otg_list_head *new_node_p, otg_list_head *list_head_p) ++ * ++ * @brief push a list node into the previous of head ++ * ++ * @param [in] new_node_p : node to be pushed ++ * @param [in] otg_list_head : target list head ++ * ++ * @return void \n ++ */ ++static inline ++void otg_list_push_prev(otg_list_head *new_node_p, otg_list_head *list_head_p) ++{ ++ otg_dbg(OTG_DBG_OTGHCDI_LIST, "otg_list_push_prev \n"); ++ list_add_tail(new_node_p, list_head_p); ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * void otg_list_pop(otg_list_head *list_entity_p) ++ * ++ * @brief pop a list node ++ * ++ * @param [in] new_node_p : node to be poped ++ * @param [in] otg_list_head : target list head ++ * ++ * @return void \n ++ */ ++static inline ++void otg_list_pop(otg_list_head *list_entity_p) ++{ ++ otg_dbg(OTG_DBG_OTGHCDI_LIST, "otg_list_pop \n"); ++ list_del(list_entity_p); ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * void otg_list_move_next(otg_list_head *node_p, otg_list_head *list_head_p) ++ * ++ * @brief move a list to next of head ++ * ++ * @param [in] new_node_p : node to be moved ++ * @param [in] otg_list_head : target list head ++ * ++ * @return void \n ++ */ ++static inline ++void otg_list_move_next(otg_list_head *node_p, otg_list_head *list_head_p) ++{ ++ otg_dbg(OTG_DBG_OTGHCDI_LIST, "otg_list_move_next \n"); ++ list_move(node_p, list_head_p); ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * void otg_list_move_prev(otg_list_head *node_p, otg_list_head *list_head_p) ++ * ++ * @brief move a list to previous of head ++ * ++ * @param [in] new_node_p : node to be moved ++ * @param [in] otg_list_head : target list head ++ * ++ * @return void \n ++ */ ++static inline ++void otg_list_move_prev(otg_list_head *node_p, otg_list_head *list_head_p) ++{ ++ otg_dbg(OTG_DBG_OTGHCDI_LIST, "otg_list_move_prev \n"); ++ list_move_tail(node_p, list_head_p); ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * bool otg_list_empty(otg_list_head *list_head_p) ++ * ++ * @brief check a list empty or not ++ * ++ * @param [in] list_head_p : node to check ++ * ++ * @return true : empty list \n ++ * false : not empty list ++ */ ++static inline ++bool otg_list_empty(otg_list_head *list_head_p) ++{ ++ ++ otg_dbg(OTG_DBG_OTGHCDI_LIST, "otg_list_empty \n"); ++ if(list_empty(list_head_p)) ++ return true; ++ return false; ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * void otg_list_merge(otg_list_head *list_p, otg_list_head *head_p) ++ * ++ * @brief merge two list ++ * ++ * @param [in] list_p : a head ++ * @param [in] head_p : target list head ++ * ++ * @return void \n ++ */ ++static inline ++void otg_list_merge(otg_list_head *list_p, otg_list_head *head_p) ++{ ++ otg_dbg(OTG_DBG_OTGHCDI_LIST, "otg_list_merge \n"); ++ list_splice(list_p, head_p); ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * void otg_list_init(otg_list_head *list_p) ++ * ++ * @brief initialize a list ++ * ++ * @param [in] list_p : node to be initialized ++ * ++ * @return void \n ++ */ ++static inline ++void otg_list_init(otg_list_head *list_p) ++{ ++ otg_dbg(OTG_DBG_OTGHCDI_LIST, "otg_list_init \n"); ++ list_p->next = list_p; ++ list_p->prev = list_p; ++} ++//------------------------------------------------------------------------------- ++ ++/* ++void otg_list_push_next(otg_list_head *new_node_p, otg_list_head *list_head_p ); ++void otg_list_push_prev(otg_list_head *new_node_p, otg_list_head *list_head_p); ++void otg_list_pop(otg_list_head *list_entity_p); ++ ++void otg_list_move_next(otg_list_head *node_p, otg_list_head *list_head_p); ++void otg_list_move_prev(otg_list_head *node_p, otg_list_head *list_head_p); ++ ++bool otg_list_empty(otg_list_head *list_head_p); ++void otg_list_merge(otg_list_head *list_p, otg_list_head *head_p); ++void otg_list_init(otg_list_head *list_p); ++*/ ++ ++#ifdef __cplusplus ++} ++#endif ++#endif /* _S3C_OTG_HCDI_LIST_H_ */ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-hcdi-memory.h linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-hcdi-memory.h +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-hcdi-memory.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-hcdi-memory.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,180 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * @file s3c-otg-hcdi-memory.h ++ * @brief header of s3c-otg-hcdi-memory \n ++ * @version ++ * -# Jun 9,2008 v1.0 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Creating the initial version of this code \n ++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Optimizing for performance \n ++ * @see None ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#ifndef _S3C_OTG_HCDI_MEMORY_H_ ++#define _S3C_OTG_HCDI_MEMORY_H_ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++#include "s3c-otg-common-common.h" ++#include "s3c-otg-hcdi-debug.h" ++ ++/** ++ * @enum otg_mem_alloc_flag ++ * ++ * @brief enumeration for flag of memory allocation ++ */ ++typedef ++enum otg_mem_alloc_flag ++{ ++ USB_MEM_SYNC, USB_MEM_ASYNC, USB_MEM_DMA ++}otg_mem_alloc_flag_t; ++//--------------------------------------------------------------------------------------- ++ ++/* ++inline int otg_mem_alloc(void ** addr_pp, u16 byte_size, otg_mem_alloc_flag_t type); ++inline int otg_mem_copy(void * to_addr_p, void * from_addr_p, u16 byte_size); ++//inline int otg_mem_free(void * addr_p); ++inline int otg_mem_set(void * addr_p, char value, u16 byte_size); ++*/ ++ ++/** ++ * int otg_mem_alloc(void ** addr_pp, u16 byte_size, u8 ubType); ++ * ++ * @brief allocating momory specified ++ * ++ * @param [inout] addr_pp : address to be assigned ++ * [in] byte_size : size of memory ++ * [in] type : otg_mem_alloc_flag_t type ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ */ ++static inline int ++otg_mem_alloc ++( ++ void ** addr_pp, ++ u16 byte_size, ++ otg_mem_alloc_flag_t type ++) ++{ ++ gfp_t flags; ++ otg_dbg(OTG_DBG_OTGHCDI_MEM, "otg_mem_alloc \n"); ++ ++ switch(type) ++ { ++ case USB_MEM_SYNC: flags = GFP_KERNEL; break; ++ case USB_MEM_ASYNC: flags = GFP_ATOMIC; break; ++ case USB_MEM_DMA: flags = GFP_DMA; break; ++ default: ++ otg_err(OTG_DBG_OTGHCDI_MEM, "not proper otg_mem_alloc_flag_t in otg_mem_alloc \n"); ++ return USB_ERR_FAIL; ++ } ++ ++ *addr_pp = kmalloc((size_t)byte_size, flags); ++ if(*addr_pp == 0) ++ { ++ otg_err(OTG_DBG_OTGHCDI_MEM, "kmalloc failed\n"); ++ return USB_ERR_FAIL; ++ } ++ return USB_ERR_SUCCESS; ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * int otg_mem_copy(void * to_addr_p, void * from_addr_p, u16 byte_size); ++ * ++ * @brief memory copy ++ * ++ * @param [in] to_addr_p : target address ++ * [in] from_addr_p : source address ++ * [in] byte_size : size ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ */ ++static inline int ++otg_mem_copy ++( ++ void * to_addr_p, ++ void * from_addr_p, ++ u16 byte_size ++) ++{ ++ otg_dbg(OTG_DBG_OTGHCDI_MEM, "otg_mem_copy \n"); ++ ++ memcpy(to_addr_p, from_addr_p, (size_t)byte_size); ++ ++ return USB_ERR_SUCCESS; ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * int otg_mem_free(void * addr_p); ++ * ++ * @brief de-allocating memory ++ * ++ * @param [in] addr_p : target address to be de-allocated ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ */ ++static inline int ++otg_mem_free(void * addr_p) ++{ ++ //otg_dbg(OTG_DBG_OTGHCDI_MEM, "otg_mem_free \n"); ++ kfree(addr_p); ++ return USB_ERR_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------- ++ ++/** ++ * int otg_mem_set(void * addr_p, char value, u16 byte_size) ++ * ++ * @brief writing a value to memory ++ * ++ * @param [in] addr_p : target address ++ * [in] value : value to be written ++ * [in] byte_size : size ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ */ ++static inline int ++otg_mem_set ++( ++ void * addr_p, ++ char value, ++ u16 byte_size ++) ++{ ++ otg_dbg(OTG_DBG_OTGHCDI_MEM, "otg_mem_set \n"); ++ memset(addr_p, value, (size_t)byte_size); ++ return USB_ERR_SUCCESS; ++} ++//------------------------------------------------------------------------------- ++ ++ ++#ifdef __cplusplus ++} ++#endif ++#endif /* _S3C_OTG_HCDI_MEMORY_H_ */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-isr.c linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-isr.c +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-isr.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-isr.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,295 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : Isr.c ++ * [Description] : The file implement the external and internal functions of ISR ++ * [Author] : Jang Kyu Hyeok { kyuhyeok.jang@samsung.com } ++ * [Department] : System LSI Division/Embedded S/W Platform ++ * [Created Date]: 2009/02/10 ++ * [Revision History] ++ * (1) 2008/06/13 by Jang Kyu Hyeok { kyuhyeok.jang@samsung.com } ++ * - Created this file and implements functions of ISR ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#include "s3c-otg-isr.h" ++ ++/** ++ * void otg_handle_interrupt(void) ++ * ++ * @brief Main interrupt processing routine ++ * ++ * @param None ++ * ++ * @return None ++ * ++ * @remark ++ * ++ */ ++ ++extern port_flags_t port_flag; ++extern bool ch_halt; ++ ++__inline__ void otg_handle_interrupt(void) ++{ ++ gintsts_t clearIntr = {.d32 = 0}; ++ gintsts_t gintsts = {.d32 = 0}; ++ ++ gintsts.d32 = read_reg_32(GINTSTS) & read_reg_32(GINTMSK); ++ ++ if (gintsts.b.wkupintr) ++ { ++ otg_dbg(OTG_DBG_ISR, "Wakeup Interrupt\n"); ++ clearIntr.b.wkupintr = 1; ++ } ++ ++ if (gintsts.b.disconnect) ++ { ++ otg_dbg(OTG_DBG_ISR, "Disconnect Interrupt\n"); ++ port_flag.b.port_connect_status_change = 1; ++ port_flag.b.port_connect_status = 0; ++ clearIntr.b.disconnect = 1; ++ } ++ ++ if (gintsts.b.conidstschng) ++ { ++ otg_dbg(OTG_DBG_ISR, "Connect ID Status Change Interrupt\n"); ++ clearIntr.b.conidstschng = 1; ++ oci_init_mode(); ++ } ++ ++ if (gintsts.b.hcintr) ++ { ++ //Mask Channel Interrupt to prevent generating interrupt ++ //otg_dbg(OTG_DBG_ISR, "Channel Interrupt\n"); ++ if(!ch_halt) ++ { ++ do_transfer_checker(); ++ } ++ ++ } ++ ++ if (gintsts.b.portintr) ++ { ++ // Read Only ++ otg_dbg(OTG_DBG_ISR, "Port Interrupt\n"); ++ process_port_intr(); ++ } ++ ++ ++ if (gintsts.b.otgintr) ++ { ++ // Read Only ++ //otg_dbg(OTG_DBG_ISR, "OTG Interrupt\n"); ++ } ++ ++ if (gintsts.b.sofintr) ++ { ++ //otg_dbg(OTG_DBG_ISR, "SOF Interrupt\n"); ++ do_schedule(); ++ clearIntr.b.sofintr = 1; ++ } ++ ++ if (gintsts.b.modemismatch) ++ { ++ otg_dbg(OTG_DBG_ISR, "Mode Mismatch Interrupt\n"); ++ clearIntr.b.modemismatch = 1; ++ } ++ update_reg_32(GINTSTS, clearIntr.d32); ++ ++} ++ ++/** ++ * void mask_channel_interrupt(u32 ch_num, u32 mask_info) ++ * ++ * @brief Mask specific channel interrupt ++ * ++ * @param [IN] chnum : channel number for masking ++ * [IN] mask_info : mask information to write register ++ * ++ * @return None ++ * ++ * @remark ++ * ++ */ ++void mask_channel_interrupt(u32 ch_num, u32 mask_info) ++{ ++ clear_reg_32(HCINTMSK(ch_num),mask_info); ++} ++ ++/** ++ * void unmask_channel_interrupt(u32 ch_num, u32 mask_info) ++ * ++ * @brief Unmask specific channel interrupt ++ * ++ * @param [IN] chnum : channel number for unmasking ++ * [IN] mask_info : mask information to write register ++ * ++ * @return None ++ * ++ * @remark ++ * ++ */ ++void unmask_channel_interrupt(u32 ch_num, u32 mask_info) ++{ ++ update_reg_32(HCINTMSK(ch_num),mask_info); ++} ++ ++/** ++ * int get_ch_info(hc_info_t * hc_reg, u8 ch_num) ++ * ++ * @brief Get current channel information about specific channel ++ * ++ * @param [OUT] hc_reg : structure to write channel inforamtion value ++ * [IN] ch_num : channel number for unmasking ++ * ++ * @return None ++ * ++ * @remark ++ * ++ */ ++int get_ch_info(hc_info_t *hc_reg, u8 ch_num) ++{ ++ if(hc_reg !=NULL) ++ { ++ hc_reg->hc_int_msk.d32 = read_reg_32(HCINTMSK(ch_num)); ++ hc_reg->hc_int.d32 = read_reg_32(HCINT(ch_num)); ++ hc_reg->dma_addr = read_reg_32(HCDMA(ch_num)); ++ hc_reg->hc_char.d32 = read_reg_32(HCCHAR(ch_num)); ++ hc_reg->hc_size.d32 = read_reg_32(HCTSIZ(ch_num)); ++ ++ return USB_ERR_SUCCESS; ++ } ++ return USB_ERR_FAIL; ++} ++ ++/** ++ * void get_intr_ch(u32* haint, u32* haintmsk) ++ * ++ * @brief Get Channel Interrupt Information in HAINT, HAINTMSK register ++ * ++ * @param [OUT] haint : HAINT register value ++ * [OUT] haintmsk : HAINTMSK register value ++ * ++ * @return None ++ * ++ * @remark ++ * ++ */ ++void get_intr_ch(u32 *haint, u32 *haintmsk) ++{ ++ *haint = read_reg_32(HAINT); ++ *haintmsk = read_reg_32(HAINTMSK); ++} ++ ++ ++/** ++ * void clear_ch_intr(u8 ch_num, u32 clear_bit) ++ * ++ * @brief Get Channel Interrupt Information in HAINT, HAINTMSK register ++ * ++ * @param [IN] haint : HAINT register value ++ * [IN] haintmsk : HAINTMSK register value ++ * ++ * @return None ++ * ++ * @remark ++ * ++ */ ++void clear_ch_intr(u8 ch_num, u32 clear_bit) ++{ ++ update_reg_32(HCINT(ch_num),clear_bit); ++} ++ ++/** ++ * void enable_sof(void) ++ * ++ * @brief Generate SOF Interrupt. ++ * ++ * @param None ++ * ++ * @return None ++ * ++ * @remark ++ * ++ */ ++void enable_sof(void) ++{ ++ gintmsk_t gintmsk = {.d32 = 0}; ++ gintmsk.b.sofintr = 1; ++ update_reg_32(GINTMSK, gintmsk.d32); ++} ++ ++/** ++ * void disable_sof(void) ++ * ++ * @brief Stop to generage SOF interrupt ++ * ++ * @param None ++ * ++ * @return None ++ * ++ * @remark ++ * ++ */ ++ void disable_sof(void) ++{ ++ gintmsk_t gintmsk = {.d32 = 0}; ++ gintmsk.b.sofintr = 1; ++ clear_reg_32(GINTMSK, gintmsk.d32); ++} ++ ++/*Internal function of isr */ ++void process_port_intr(void) ++{ ++ hprt_t hprt;//by ss1, clear_hprt; ++ hprt.d32 = read_reg_32(HPRT); ++ ++ otg_dbg(OTG_DBG_ISR,"\nPort Interrupt() : HPRT = 0x%x\n",hprt.d32); ++ ++ if(hprt.b.prtconndet) ++ { ++ port_flag.b.port_connect_status_change = 1; ++ ++ if(hprt.b.prtconnsts) ++ port_flag.b.port_connect_status = 1; ++ } ++ ++ ++ if(hprt.b.prtenchng) ++ { ++ port_flag.b.port_enable_change = 1; ++ } ++ ++ if(hprt.b.prtovrcurrchng) ++ { ++ otg_dbg(OTG_DBG_ISR,"over current condition is changed\n"); ++ ++ if(hprt.b.prtovrcurract) ++ port_flag.b.port_over_current_change = 1; ++ else ++ port_flag.b.port_over_current_change = 0; ++ } ++ ++ hprt.b.prtena = 0; //prtena¸¦ writeclear½ÃÅ°¸é ¾ÈµÊ. ++ //hprt.b.prtpwr = 0; ++ hprt.b.prtrst = 0; ++ hprt.b.prtconnsts = 0; ++ write_reg_32(HPRT, hprt.d32); ++ ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-isr.h linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-isr.h +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-isr.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-isr.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,72 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] :s3c-otg-isr.h ++ * [Description] : The Header file defines the external and internal functions of ISR. ++ * [Author] : Jang Kyu Hyeok { kyuhyeok.jang@samsung.com } ++ * [Department] : System LSI Division/Embedded S/W Platform ++ * [Created Date]: 2008/06/18 ++ * [Revision History] ++ * (1) 2008/06/18 by Jang Kyu Hyeok { kyuhyeok.jang@samsung.com } ++ * - Created this file and defines functions of Scheduler ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#ifndef _ISR_H_ ++#define _ISR_H_ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++#include "s3c-otg-common-errorcode.h" ++#include "s3c-otg-common-const.h" ++#include "s3c-otg-common-datastruct.h" ++#include "s3c-otg-common-regdef.h" ++#include "s3c-otg-hcdi-kal.h" ++#include "s3c-otg-scheduler-scheduler.h" ++#include "s3c-otg-transferchecker-common.h" ++#include "s3c-otg-roothub.h" ++#include "s3c-otg-oci.h" ++ ++__inline__ void otg_handle_interrupt(void); ++ ++void process_port_intr(void); ++ ++void mask_channel_interrupt(u32 ch_num, u32 mask_info); ++ ++void unmask_channel_interrupt(u32 ch_num, u32 mask_info); ++ ++extern int get_ch_info(hc_info_t *hc_reg, u8 ch_num); ++ ++extern void get_intr_ch(u32 *haint, u32 *haintmsk); ++ ++extern void clear_ch_intr(u8 ch_num, u32 clear_bit); ++ ++extern void enable_sof(void); ++ ++extern void disable_sof(void); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif /* _ISR_H_ */ ++ ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-oci.c linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-oci.c +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-oci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-oci.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,798 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : OCI.c ++ * [Description] : The file implement the external and internal functions of OCI ++ * [Author] : Jang Kyu Hyeok { kyuhyeok.jang@samsung.com } ++ * [Department] : System LSI Division/Embedded S/W Platform ++ * [Created Date]: 2009/02/10 ++ * [Revision History] ++ * (1) 2008/06/12 by Jang Kyu Hyeok { kyuhyeok.jang@samsung.com } ++ * - Created this file and Implement functions of OCI ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#include "s3c-otg-oci.h" ++ ++static bool ch_enable[16]; ++bool ch_halt; ++ ++/** ++ * int oci_init(void) ++ * ++ * @brief Initialize oci module. ++ * ++ * @param None ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ * @remark ++ * ++ */ ++int oci_init(void) ++{ ++ otg_mem_set((void*)ch_enable, true, sizeof(bool)*16); ++ ch_halt = false; ++ ++ if(oci_sys_init() == USB_ERR_SUCCESS) ++ { ++ if(oci_core_reset() == USB_ERR_SUCCESS) ++ { ++ oci_set_global_interrupt(false); ++ return USB_ERR_SUCCESS; ++ } ++ else ++ { ++ //otg_dbg(OTG_DBG_OCI, "oci_core_reset() Fail\n"); ++ return USB_ERR_FAIL; ++ } ++ } ++ ++ return USB_ERR_FAIL; ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * int oci_core_init(void) ++ * ++ * @brief process core initialize as s3c6410 otg spec ++ * ++ * @param None ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ * @remark ++ * ++ */ ++int oci_core_init(void) ++{ ++ gahbcfg_t ahbcfg = {.d32 = 0}; ++ gusbcfg_t usbcfg = {.d32 = 0}; ++ ghwcfg2_t hwcfg2 = {.d32 = 0}; ++ gintmsk_t gintmsk = {.d32 = 0}; ++ ++ //otg_dbg(OTG_DBG_OCI, "oci_core_init \n"); ++ ++ /* PHY parameters */ ++ usbcfg.b.physel = 0; ++ usbcfg.b.phyif = 1; // 16 bit ++ usbcfg.b.ulpi_utmi_sel = 0; // UTMI ++ //usbcfg.b.ddrsel = 1; // DDR ++ usbcfg.b.usbtrdtim = 5; // 16 bit UTMI ++ usbcfg.b.toutcal = 7; ++ write_reg_32 (GUSBCFG, usbcfg.d32); ++ ++ // Reset after setting the PHY parameters ++ if(oci_core_reset() == USB_ERR_SUCCESS) ++ { ++ /* Program the GAHBCFG Register.*/ ++ hwcfg2.d32 = read_reg_32 (GHWCFG2); ++ ++ switch (hwcfg2.b.architecture) ++ { ++ case HWCFG2_ARCH_SLAVE_ONLY: ++ //otg_dbg(OTG_DBG_OCI, "Slave Only Mode\n"); ++ ahbcfg.b.nptxfemplvl = 0; ++ ahbcfg.b.ptxfemplvl = 0; ++ break; ++ ++ case HWCFG2_ARCH_EXT_DMA: ++ //otg_dbg(OTG_DBG_OCI, "External DMA Mode - TBD!\n"); ++ break; ++ ++ case HWCFG2_ARCH_INT_DMA: ++ //otg_dbg(OTG_DBG_OCI, "Internal DMA Setting \n"); ++ ahbcfg.b.dmaenable = true; ++ ahbcfg.b.hburstlen = INT_DMA_MODE_INCR; ++ break; ++ ++ default: ++ //otg_dbg(OTG_DBG_OCI, "ERR> hwcfg2\n "); ++ break; ++ } ++ write_reg_32 (GAHBCFG, ahbcfg.d32); ++ ++ /* Program the GUSBCFG register.*/ ++ switch (hwcfg2.b.op_mode) ++ { ++ case MODE_HNP_SRP_CAPABLE: ++ //otg_dbg(OTG_DBG_OCI, "GHWCFG2 OP Mode : MODE_HNP_SRP_CAPABLE \n"); ++ usbcfg.b.hnpcap = 1; ++ usbcfg.b.srpcap = 1; ++ break; ++ ++ case MODE_SRP_ONLY_CAPABLE: ++ //otg_dbg(OTG_DBG_OCI, "GHWCFG2 OP Mode : MODE_SRP_ONLY_CAPABLE \n"); ++ usbcfg.b.srpcap = 1; ++ break; ++ ++ case MODE_NO_HNP_SRP_CAPABLE: ++ //otg_dbg(OTG_DBG_OCI, "GHWCFG2 OP Mode : MODE_NO_HNP_SRP_CAPABLE \n"); ++ usbcfg.b.hnpcap = 0; ++ break; ++ ++ case MODE_SRP_CAPABLE_DEVICE: ++ //otg_dbg(OTG_DBG_OCI, "GHWCFG2 OP Mode : MODE_SRP_CAPABLE_DEVICE \n"); ++ usbcfg.b.srpcap = 1; ++ break; ++ ++ case MODE_NO_SRP_CAPABLE_DEVICE: ++ //otg_dbg(OTG_DBG_OCI, "GHWCFG2 OP Mode : MODE_NO_SRP_CAPABLE_DEVICE \n"); ++ usbcfg.b.srpcap = 0; ++ break; ++ ++ case MODE_SRP_CAPABLE_HOST: ++ //otg_dbg(OTG_DBG_OCI, "GHWCFG2 OP Mode : MODE_SRP_CAPABLE_HOST \n"); ++ usbcfg.b.srpcap = 1; ++ break; ++ ++ case MODE_NO_SRP_CAPABLE_HOST: ++ //otg_dbg(OTG_DBG_OCI, "GHWCFG2 OP Mode : MODE_NO_SRP_CAPABLE_HOST \n"); ++ usbcfg.b.srpcap = 0; ++ break; ++ default : ++ //otg_dbg(OTG_DBG_OCI, "ERR> hwcfg2\n "); ++ break; ++ } ++ write_reg_32 (GUSBCFG, usbcfg.d32); ++ ++ /* Program the GINTMSK register.*/ ++ gintmsk.b.modemismatch = 1; ++ gintmsk.b.sofintr = 1; ++ //gintmsk.b.otgintr = 1; ++ gintmsk.b.conidstschng = 1; ++ //gintmsk.b.wkupintr = 1; ++ gintmsk.b.disconnect = 1; ++ //gintmsk.b.usbsuspend = 1; ++ //gintmsk.b.sessreqintr = 1; ++ //gintmsk.b.portintr = 1; ++ //gintmsk.b.hcintr = 1; ++ write_reg_32(GINTMSK, gintmsk.d32); ++ ++ return USB_ERR_SUCCESS; ++ } ++ else ++ { ++ //otg_dbg(OTG_DBG_OCI, "Core Reset FAIL\n"); ++ return USB_ERR_FAIL; ++ } ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * int oci_host_init(void) ++ * ++ * @brief Process host initialize as s3c6410 spec ++ * ++ * @param None ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ * @remark ++ * ++ */ ++int oci_host_init(void) ++{ ++ gintmsk_t gintmsk = {.d32 = 0}; ++ hcfg_t hcfg = {.d32 = 0}; ++ hprt_t hprt; ++ hprt.d32 = read_reg_32(HPRT); ++ ++ //otg_dbg(OTG_DBG_OCI, "oci_host_init \n"); ++ ++ gintmsk.b.portintr = 1; ++ update_reg_32(GINTMSK,gintmsk.d32); ++ ++ hcfg.b.fslspclksel = HCFG_30_60_MHZ; ++ update_reg_32(HCFG, hcfg.d32); ++ ++ /* turn on vbus */ ++ if(!hprt.b.prtpwr) ++ { ++ hprt.b.prtpwr = 1; ++ write_reg_32(HPRT, hprt.d32); ++ } ++ ++ oci_config_flush_fifo(OTG_HOST_MODE); ++ ++ return USB_ERR_SUCCESS; ++ ++} ++//------------------------------------------------------------------------------- ++ ++ ++/** ++ * int oci_start(void) ++ * ++ * @brief start to operate oci module by calling oci_core_init function ++ * ++ * @param None ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ * @remark ++ * ++ */ ++int oci_start(void) ++{ ++ //otg_dbg(OTG_DBG_OCI, "oci_start \n"); ++ ++ if(oci_core_init() == USB_ERR_SUCCESS) ++ { ++ mdelay(50); ++ ++ if(oci_init_mode() == USB_ERR_SUCCESS) ++ { ++ oci_set_global_interrupt(true); ++ return USB_ERR_SUCCESS; ++ } ++ else ++ { ++ //otg_dbg(OTG_DBG_OCI, "oci_init_mode() Fail\n"); ++ return USB_ERR_FAIL; ++ } ++ } ++ else ++ { ++ //otg_dbg(OTG_DBG_OCI, "oci_core_init() Fail\n"); ++ return USB_ERR_FAIL; ++ } ++ ++ ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * int oci_stop(void) ++ * ++ * @brief stop to opearte otg core ++ * ++ * @param None ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ * @remark ++ * ++ */ ++int oci_stop(void) ++{ ++ //otg_dbg(OTG_DBG_OCI, "oci_stop \n"); ++ ++ oci_set_global_interrupt(false); ++ ++ root_hub_feature(0, ++ ClearPortFeature, ++ USB_PORT_FEAT_POWER, ++ NULL ++ ); ++ ++ return USB_ERR_SUCCESS; ++} ++//------------------------------------------------------------------------------- ++ ++ ++/** ++ * oci_start_transfer( stransfer_t *st_t) ++ * ++ * @brief start transfer by using transfer information to receive from scheduler ++ * ++ * @param [IN] *st_t - information about transfer to write register by calling oci_channel_init function ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ * @remark ++ * ++ */ ++ ++u8 oci_start_transfer( stransfer_t *st_t) ++{ ++ hcchar_t hcchar = {.d32 = 0}; ++ //otg_dbg(OTG_DBG_OCI, "oci_start_transfer \n"); ++ ++ if(st_t->alloc_chnum ==CH_NONE) ++ { ++ ++ if( oci_channel_alloc(&(st_t->alloc_chnum)) == USB_ERR_SUCCESS) ++ { ++ oci_channel_init(st_t->alloc_chnum, st_t); ++ ++ hcchar.b.chen = 1; ++ update_reg_32(HCCHAR(st_t->alloc_chnum), hcchar.d32); ++ return st_t->alloc_chnum; ++ } ++ else ++ { ++ otg_dbg(OTG_DBG_OCI, "oci_start_transfer Fail - Channel Allocation Error\n"); ++ return CH_NONE; ++ } ++ } ++ else ++ { ++ oci_channel_init(st_t->alloc_chnum, st_t); ++ ++ hcchar.b.chen = 1; ++ update_reg_32(HCCHAR(st_t->alloc_chnum), hcchar.d32); ++ ++ return st_t->alloc_chnum; ++ } ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * int oci_stop_transfer(u8 ch_num) ++ * ++ * @brief stop to transfer even if transfering ++ * ++ * @param None ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ * @remark ++ * ++ */ ++int oci_stop_transfer(u8 ch_num) ++{ ++ hcchar_t hcchar = {.d32 = 0}; ++ hcintmsk_t hcintmsk = {.d32 = 0}; ++ int count = 0, max_error_count = 10000; ++ ++ otg_dbg(OTG_DBG_OCI, "step1: oci_stop_transfer ch=%d, hcchar=0x%x\n", ++ ch_num, read_reg_32(HCCHAR(ch_num))); ++ ++ if(ch_num>16) ++ { ++ return USB_ERR_FAIL; ++ } ++ ++ ch_halt = true; ++ ++ hcintmsk.b.chhltd = 1; ++ update_reg_32(HCINTMSK(ch_num),hcintmsk.d32); ++ ++ hcchar.b.chdis = 1; ++ hcchar.b.chen = 1; ++ update_reg_32(HCCHAR(ch_num),hcchar.d32); ++ ++ //wait for Channel Disabled Interrupt ++ do { ++ hcchar.d32 = read_reg_32(HCCHAR(ch_num)); ++ ++ if(count > max_error_count) { ++ otg_dbg(OTG_DBG_OCI, "Warning!! oci_stop_transfer()" ++ "ChDis is not cleared! ch=%d, hcchar=0x%x\n", ++ ch_num, hcchar.d32); ++ return USB_ERR_FAIL; ++ } ++ count++; ++ ++ } while(hcchar.b.chdis); ++ ++ oci_channel_dealloc(ch_num); ++ ++ clear_reg_32(HAINTMSK,ch_num); ++ write_reg_32(HCINT(ch_num),INT_ALL); ++ clear_reg_32(HCINTMSK(ch_num), INT_ALL); ++ ++ ch_halt =false; ++ otg_dbg(OTG_DBG_OCI, "step2 : oci_stop_transfer ch=%d, hcchar=0x%x\n", ++ ch_num, read_reg_32(HCCHAR(ch_num))); ++ ++ return USB_ERR_SUCCESS; ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * int oci_channel_init( u8 ch_num, stransfer_t *st_t) ++ * ++ * @brief Process channel initialize to prepare starting transfer ++ * ++ * @param None ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ * @remark ++ * ++ */ ++int oci_channel_init( u8 ch_num, stransfer_t *st_t) ++{ ++ u32 intr_enable = 0; ++ gintmsk_t gintmsk = {.d32 = 0}; ++ hcchar_t hcchar = {.d32 = 0}; ++ hctsiz_t hctsiz = {.d32 = 0}; ++ ++ //otg_dbg(OTG_DBG_OCI, "oci_channel_init \n"); ++ ++ //Clear channel information ++ write_reg_32(HCTSIZ(ch_num), 0); ++ write_reg_32(HCCHAR(ch_num), 0); ++ write_reg_32(HCINTMSK(ch_num), 0); ++ write_reg_32(HCINT(ch_num), INT_ALL);//write clear ++ write_reg_32(HCDMA(ch_num), 0); ++ ++ //enable host channel interrupt in GINTSTS ++ gintmsk.b.hcintr =1; ++ update_reg_32(GINTMSK, gintmsk.d32); ++ // Enable the top level host channel interrupt in HAINT ++ intr_enable = (1 << ch_num); ++ update_reg_32(HAINTMSK, intr_enable); ++ // unmask the down level host channel interrupt in HCINT ++ write_reg_32(HCINTMSK(ch_num),st_t->hc_reg.hc_int_msk.d32); ++ ++ // Program the HCSIZn register with the endpoint characteristics for ++ hctsiz.b.xfersize = st_t->buf_size; ++ hctsiz.b.pktcnt = st_t->packet_cnt; ++ ++ // Program the HCCHARn register with the endpoint characteristics for ++ hcchar.b.mps = st_t->ed_desc_p->max_packet_size; ++ hcchar.b.epnum = st_t->ed_desc_p->endpoint_num; ++ hcchar.b.epdir = st_t->ed_desc_p->is_ep_in; ++ hcchar.b.lspddev = (st_t->ed_desc_p->dev_speed == LOW_SPEED_OTG); ++ hcchar.b.eptype = st_t->ed_desc_p->endpoint_type; ++ hcchar.b.multicnt = st_t->ed_desc_p->mc; ++ hcchar.b.devaddr = st_t->ed_desc_p->device_addr; ++ ++ if(st_t->ed_desc_p->endpoint_type == INT_TRANSFER || ++ st_t->ed_desc_p->endpoint_type == ISOCH_TRANSFER) ++ { ++ u32 uiFrameNum = 0; ++ uiFrameNum = oci_get_frame_num(); ++ ++ hcchar.b.oddfrm = uiFrameNum%2?1:0; ++ ++ //if transfer type is periodic transfer, must support sof interrupt ++ /* ++ gintmsk.b.sofintr = 1; ++ update_reg_32(GINTMSK, gintmsk.d32); ++ */ ++ } ++ ++ ++ if(st_t->ed_desc_p->endpoint_type == CONTROL_TRANSFER) ++ { ++ td_t *td_p; ++ td_p = (td_t *)st_t->parent_td; ++ ++ switch(td_p->standard_dev_req_info.conrol_transfer_stage) ++ { ++ case SETUP_STAGE: ++ hctsiz.b.pid = st_t->ed_status_p->control_data_tgl.setup_tgl; ++ hcchar.b.epdir = EP_OUT; ++ break; ++ case DATA_STAGE: ++ hctsiz.b.pid = st_t->ed_status_p->control_data_tgl.data_tgl; ++ hcchar.b.epdir = st_t->ed_desc_p->is_ep_in; ++ break; ++ case STATUS_STAGE: ++ hctsiz.b.pid = st_t->ed_status_p->control_data_tgl.status_tgl; ++ ++ if(td_p->standard_dev_req_info.is_data_stage) ++ { ++ hcchar.b.epdir = ~(st_t->ed_desc_p->is_ep_in); ++ } ++ else ++ { ++ hcchar.b.epdir = EP_IN; ++ } ++ break; ++ default:break; ++ } ++ } ++ else ++ { ++ hctsiz.b.pid = st_t->ed_status_p->data_tgl; ++ } ++ ++ hctsiz.b.dopng = st_t->ed_status_p->is_ping_enable; ++ write_reg_32(HCTSIZ(ch_num),hctsiz.d32); ++ st_t->ed_status_p->is_ping_enable = false; ++ ++ // Write DMA Address ++ write_reg_32(HCDMA(ch_num),st_t->start_phy_buf_addr); ++ ++ //Wrote HCCHAR Register ++ write_reg_32(HCCHAR(ch_num),hcchar.d32); ++ ++ return USB_ERR_SUCCESS; ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * u32 oci_get_frame_num(void) ++ * ++ * @brief Get current frame number by reading register. ++ * ++ * @param None ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ * @remark ++ * ++ */ ++u32 oci_get_frame_num(void) ++{ ++ hfnum_t hfnum; ++ hfnum.d32 = read_reg_32(HFNUM); ++ return hfnum.b.frnum; ++} ++//------------------------------------------------------------------------------- ++ ++/** ++ * u16 oci_get_frame_interval(void) ++ * ++ * @brief Get current frame interval by reading register. ++ * ++ * @param None ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ * @remark ++ * ++ */ ++u16 oci_get_frame_interval(void) ++{ ++ hfir_t hfir; ++ hfir.d32 = read_reg_32(HFIR); ++ return hfir.b.frint; ++} ++//------------------------------------------------------------------------------- ++ ++void oci_set_frame_interval(u16 interval) ++{ ++ hfir_t hfir = {.d32 = 0}; ++ hfir.b.frint = interval; ++ write_reg_32(HFIR, hfir.d32); ++ ++} ++ ++///OCI Internal Functions ++ ++int oci_channel_alloc(u8 *ch_num) ++{ ++ u8 ch; ++ ++ hcchar_t hcchar = {.d32 = 0}; ++ ++ for(ch = 0 ; ch<16 ; ch++) { ++ ++ if(ch_enable[ch] == true) { ++ hcchar.d32 = read_reg_32(HCCHAR(ch)); ++ ++ if(hcchar.b.chdis == 0) { ++ *ch_num = ch; ++ ch_enable[ch] = false; ++ return USB_ERR_SUCCESS; ++ } ++ } ++ ++ } ++ ++ return USB_ERR_FAIL; ++} ++ ++int oci_channel_dealloc(u8 ch_num) ++{ ++ if(ch_num < 16 && ch_enable[ch_num] == false) ++ { ++ ch_enable[ch_num] = true; ++ ++ write_reg_32(HCTSIZ(ch_num), 0); ++ write_reg_32(HCCHAR(ch_num), 0); ++ write_reg_32(HCINTMSK(ch_num), 0); ++ write_reg_32(HCINT(ch_num), INT_ALL); ++ write_reg_32(HCDMA(ch_num), 0); ++ return USB_ERR_SUCCESS; ++ } ++ return USB_ERR_FAIL; ++} ++ ++int oci_sys_init(void) ++{ ++ otg_phy_init(); ++ return USB_ERR_SUCCESS; ++} ++ ++void oci_set_global_interrupt(bool set) ++{ ++ gahbcfg_t ahbcfg; ++ ++ ahbcfg.d32 = 0; ++ ahbcfg.b.glblintrmsk = 1; ++ ++ if(set) ++ { ++ update_reg_32(GAHBCFG,ahbcfg.d32); ++ } ++ else ++ { ++ clear_reg_32(GAHBCFG,ahbcfg.d32); ++ } ++} ++ ++int oci_init_mode(void) ++{ ++ gintsts_t gintsts; ++ gintsts.d32 = read_reg_32(GINTSTS); ++ //otg_dbg(OTG_DBG_OCI,"GINSTS = 0x%x\n",(unsigned int)gintsts.d32); ++ //otg_dbg(OTG_DBG_OCI,"GINMSK = 0x%x\n",(unsigned int)read_reg_32(GINTMSK)); ++ ++ if(gintsts.b.curmode == OTG_HOST_MODE) ++ { ++ //otg_dbg(OTG_DBG_OCI,"HOST Mode\n"); ++ if(oci_host_init() == USB_ERR_SUCCESS) ++ { ++ return USB_ERR_SUCCESS; ++ } ++ else ++ { ++ //otg_dbg(OTG_DBG_OCI,"oci_host_init() Fail\n"); ++ return USB_ERR_FAIL; ++ } ++ } ++ ++ else // Device Mode ++ { ++ //otg_dbg(OTG_DBG_OCI,"DEVICE Mode\n"); ++ if(oci_dev_init() == USB_ERR_SUCCESS) ++ { ++ return USB_ERR_SUCCESS; ++ } ++ else ++ { ++ //otg_dbg(OTG_DBG_OCI,"oci_dev_init() Fail\n"); ++ return USB_ERR_FAIL; ++ } ++ } ++ ++ return USB_ERR_SUCCESS; ++} ++ ++void oci_config_flush_fifo(u32 mode) ++{ ++ ghwcfg2_t hwcfg2 = {.d32 = 0}; ++ //otg_dbg(OTG_DBG_OCI,"oci_config_flush_fifo\n"); ++ ++ hwcfg2.d32 = read_reg_32(GHWCFG2); ++ ++ // Configure data FIFO sizes ++ if (hwcfg2.b.dynamic_fifo) ++ { ++ // Rx FIFO ++ write_reg_32(GRXFSIZ, 0x0000010D); ++ ++ // Non-periodic Tx FIFO ++ write_reg_32(GNPTXFSIZ, 0x0080010D); ++ ++ if (mode == OTG_HOST_MODE) ++ { ++ // For Periodic transactions, ++ // program HPTXFSIZ ++ } ++ } ++ ++ // Flush the FIFOs ++ oci_flush_tx_fifo(0); ++ ++ oci_flush_rx_fifo(); ++} ++ ++void oci_flush_tx_fifo(u32 num) ++{ ++ grstctl_t greset = {.d32 = 0}; ++ u32 count = 0; ++ ++ //otg_dbg(OTG_DBG_OCI,"oci_flush_tx_fifo\n"); ++ ++ greset.b.txfflsh = 1; ++ greset.b.txfnum = num; ++ write_reg_32(GRSTCTL, greset.d32); ++ ++ // wait for flush to end ++ while (greset.b.txfflsh == 1) ++ { ++ greset.d32 = read_reg_32(GRSTCTL); ++ if (++count > MAX_COUNT) ++ { ++ break; ++ } ++ }; ++ ++ /* Wait for 3 PHY Clocks*/ ++ udelay(30); ++} ++ ++void oci_flush_rx_fifo(void) ++{ ++ grstctl_t greset = {.d32 = 0}; ++ u32 count = 0; ++ ++ //otg_dbg(OTG_DBG_OCI,"oci_flush_rx_fifo\n"); ++ ++ greset.b.rxfflsh = 1; ++ write_reg_32(GRSTCTL, greset.d32 ); ++ ++ do ++ { ++ greset.d32 = read_reg_32(GRSTCTL); ++ ++ if (++count > MAX_COUNT) ++ { ++ break; ++ } ++ ++ } while (greset.b.rxfflsh == 1); ++ ++ /* Wait for 3 PHY Clocks*/ ++ udelay(30); ++} ++ ++int oci_core_reset(void) ++{ ++ u32 count = 0; ++ grstctl_t greset = {.d32 = 0}; ++ ++ //otg_dbg(OTG_DBG_OCI,"oci_core_reset\n"); ++ ++ /* Wait for AHB master IDLE state. */ ++ do ++ { ++ greset.d32 = read_reg_32 (GRSTCTL); ++ mdelay (50); ++ ++ if(++count>100) ++ { ++ //otg_dbg(OTG_DBG_OCI,"AHB status is not IDLE\n"); ++ return USB_ERR_FAIL; ++ } ++ } while (greset.b.ahbidle != 1); ++ ++ /* Core Soft Reset */ ++ greset.b.csftrst = 1; ++ write_reg_32 (GRSTCTL, greset.d32); ++ ++ /* Wait for 3 PHY Clocks*/ ++ mdelay (50); ++ return USB_ERR_SUCCESS; ++} ++ ++int oci_dev_init(void) ++{ ++ //otg_dbg(OTG_DBG_OCI,"Current Not Support Device Mode! \n"); ++ //return USB_ERR_FAIL; ++ return USB_ERR_SUCCESS; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-oci.h linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-oci.h +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-oci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-oci.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,86 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] :s3c-otg-oci.h ++ * [Description] : The Header file defines the external and internal functions of OCI. ++ * [Author] : Jang Kyu Hyeok { kyuhyeok.jang@samsung.com } ++ * [Department] : System LSI Division/Embedded S/W Platform ++ * [Created Date]: 2008/06/18 ++ * [Revision History] ++ * (1) 2008/06/25 by Jang Kyu Hyeok { kyuhyeok.jang@samsung.com } ++ * - Added some functions and data structure of OCI ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#ifndef _OCI_H_ ++#define _OCI_H_ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++//#include "s3c-otg-common-const.h" ++#include "s3c-otg-common-errorcode.h" ++#include "s3c-otg-common-regdef.h" ++#include "s3c-otg-hcdi-kal.h" ++#include "s3c-otg-hcdi-memory.h" ++#include "s3c-otg-hcdi-debug.h" ++#include "s3c-otg-roothub.h" ++#include "s3c-otg-hcdi-hcd.h" ++ ++#include //virtual address for smdk ++ ++extern void otg_phy_init(void); ++#include ++ ++///OCI interace ++int oci_init(void); ++ ++int oci_start(void); ++int oci_stop(void); ++ ++u8 oci_start_transfer(stransfer_t *st_t); ++int oci_stop_transfer(u8 ch_num); ++ ++int oci_channel_init(u8 ch_num, stransfer_t *st_t); ++u32 oci_get_frame_num(void); ++u16 oci_get_frame_interval(void); ++void oci_set_frame_interval(u16 intervl); ++ ++///OCI Internal Functions ++int oci_sys_init(void); ++int oci_core_init(void); ++int oci_init_mode(void); ++int oci_host_init(void); ++int oci_dev_init(void); ++ ++int oci_channel_alloc(u8 *ch_num); ++int oci_channel_dealloc(u8 ch_num); ++ ++void oci_config_flush_fifo(u32 mode); ++void oci_flush_tx_fifo(u32 num); ++void oci_flush_rx_fifo(void); ++ ++int oci_core_reset(void); ++void oci_set_global_interrupt(bool set); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif /* _OCI_H_ */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-roothub.c linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-roothub.c +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-roothub.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-roothub.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,473 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : RootHub.c ++ * [Description] : The file implement the external and internal functions of RootHub ++ * [Author] : Jang Kyu Hyeok { kyuhyeok.jang@samsung.com } ++ * [Department] : System LSI Division/Embedded S/W Platform ++ * [Created Date]: 2009/02/10 ++ * [Revision History] ++ * (1) 2008/06/13 by Jang Kyu Hyeok { kyuhyeok.jang@samsung.com } ++ * - Created this file and implements functions of RootHub ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#include "s3c-otg-roothub.h" ++ ++port_flags_t port_flag; ++ ++/** ++ * int get_otg_port_status(const u8 port, char* status) ++ * ++ * @brief Get port change bitmap information ++ * ++ * @param [IN] port : port number ++ * [OUT] status : buffer to store bitmap information ++ * ++ * @returnUSB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ * ++ * @remark ++ * ++ */ ++__inline__ int get_otg_port_status(const u8 port, char *status) ++{ ++ //return root_hub_feature(port, GetPortStatus, NULL, status); ++ ++ status[port] = 0; ++ status[port] |= (port_flag.b.port_connect_status_change || ++ port_flag.b.port_reset_change || ++ port_flag.b.port_enable_change || ++ port_flag.b.port_suspend_change || ++ port_flag.b.port_over_current_change) << 1; ++ ++ if (status[port]) { ++ otg_dbg(OTG_DBG_ROOTHUB, " Root port status changed\n"); ++ otg_dbg(OTG_DBG_ROOTHUB, " port_connect_status_change: %d\n", ++ port_flag.b.port_connect_status_change); ++ otg_dbg(OTG_DBG_ROOTHUB, " port_reset_change: %d\n", ++ port_flag.b.port_reset_change); ++ otg_dbg(OTG_DBG_ROOTHUB, " port_enable_change: %d\n", ++ port_flag.b.port_enable_change); ++ otg_dbg(OTG_DBG_ROOTHUB, " port_suspend_change: %d\n", ++ port_flag.b.port_suspend_change); ++ otg_dbg(OTG_DBG_ROOTHUB, " port_over_current_change: %d\n", ++ port_flag.b.port_over_current_change); ++ } ++ ++ return (status[port] !=0); ++} ++ ++/** ++ * int reset_and_enable_port(const u8 port) ++ * ++ * @brief Reset port and make enable status the specific port ++ * ++ * @param [IN] port : port number ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ * ++ * @remark ++ * ++ */ ++int reset_and_enable_port(const u8 port) ++{ ++ hprt_t hprt; ++ u32 count = 0; ++ u32 max_error_count = 10000; ++ ++ hprt.d32 = read_reg_32(HPRT); ++ ++ if(hprt.b.prtconnsts==0) ++ { ++ otg_dbg(OTG_DBG_ROOTHUB,"No Attached Device, HPRT = 0x%x\n", hprt.d32); ++ ++ port_flag.b.port_connect_status_change = 1; ++ port_flag.b.port_connect_status = 0; ++ ++ return USB_ERR_FAIL; ++ } ++ ++ if(!hprt.b.prtena) ++ { ++ hprt.b.prtrst = 1; // drive reset ++ write_reg_32(HPRT, hprt.d32); ++ ++ mdelay(60); ++ hprt.b.prtrst = 0; ++ write_reg_32(HPRT, hprt.d32); ++ ++ do { ++ hprt.d32 = read_reg_32(HPRT); ++ ++ if(count > max_error_count) { ++ otg_dbg(OTG_DBG_ROOTHUB,"Port Reset Fail : HPRT : 0x%x\n", hprt.d32); ++ return USB_ERR_FAIL; ++ } ++ count++; ++ ++ } while(!hprt.b.prtena); ++ ++ } ++ return USB_ERR_SUCCESS; ++} ++ ++/** ++ * int root_hub_feature(const u8 port, ++ * const u16 type_req, ++ * const u16 feature, ++ * void* buf) ++ * ++ * @brief Get port change bitmap information ++ * ++ * @param [IN] port : port number ++ * [IN] type_req : request type of hub feature as usb 2.0 spec ++ * [IN] feature : hub feature as usb 2.0 spec ++ * [OUT] status : buffer to store results ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ * ++ * @remark ++ * ++ */ ++__inline__ int root_hub_feature(const u8 port, ++ const u16 type_req, ++ const u16 feature, ++ void *buf) ++{ ++ int retval = USB_ERR_SUCCESS; ++ usb_hub_descriptor_t *desc = NULL; ++ u32 port_status = 0; ++ hprt_t hprt = {.d32 = 0}; ++ ++ switch (type_req) ++ { ++ case ClearHubFeature: ++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearHubFeature\n"); ++ switch (feature) ++ { ++ case C_HUB_LOCAL_POWER: ++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearHubFeature -C_HUB_LOCAL_POWER \n"); ++ break; ++ case C_HUB_OVER_CURRENT: ++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearHubFeature -C_HUB_OVER_CURRENT \n"); ++ /* Nothing required here */ ++ break; ++ default: ++ retval = USB_ERR_FAIL; ++ } ++ break; ++ ++ case ClearPortFeature: ++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearPortFeature\n"); ++ switch (feature) ++ { ++ case USB_PORT_FEAT_ENABLE: ++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearPortFeature -USB_PORT_FEAT_ENABLE \n"); ++ hprt.b.prtena = 1; ++ update_reg_32(HPRT, hprt.d32); ++ break; ++ ++ case USB_PORT_FEAT_SUSPEND: ++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearPortFeature -USB_PORT_FEAT_SUSPEND \n"); ++ bus_resume(); ++ break; ++ ++ case USB_PORT_FEAT_POWER: ++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearPortFeature -USB_PORT_FEAT_POWER \n"); ++ hprt.b.prtpwr = 1; ++ clear_reg_32(HPRT, hprt.d32); ++ break; ++ ++ case USB_PORT_FEAT_INDICATOR: ++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearPortFeature -USB_PORT_FEAT_INDICATOR \n"); ++ /* Port inidicator not supported */ ++ break; ++ ++ case USB_PORT_FEAT_C_CONNECTION: ++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearPortFeature -USB_PORT_FEAT_C_CONNECTION \n"); ++ /* Clears drivers internal connect status change ++ * flag */ ++ port_flag.b.port_connect_status_change = 0; ++ break; ++ ++ case USB_PORT_FEAT_C_RESET: ++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearPortFeature -USB_PORT_FEAT_C_RESET \n"); ++ /* Clears the driver's internal Port Reset Change ++ * flag */ ++ port_flag.b.port_reset_change = 0; ++ break; ++ ++ case USB_PORT_FEAT_C_ENABLE: ++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearPortFeature -USB_PORT_FEAT_C_ENABLE \n"); ++ /* Clears the driver's internal Port ++ * Enable/Disable Change flag */ ++ port_flag.b.port_enable_change = 0; ++ break; ++ ++ case USB_PORT_FEAT_C_SUSPEND: ++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearPortFeature -USB_PORT_FEAT_C_SUSPEND \n"); ++ /* Clears the driver's internal Port Suspend ++ * Change flag, which is set when resume signaling on ++ * the host port is complete */ ++ port_flag.b.port_suspend_change = 0; ++ break; ++ ++ case USB_PORT_FEAT_C_OVER_CURRENT: ++ otg_dbg(OTG_DBG_ROOTHUB,"case ClearPortFeature -USB_PORT_FEAT_C_OVER_CURRENT \n"); ++ port_flag.b.port_over_current_change = 0; ++ break; ++ ++ default: ++ retval = USB_ERR_FAIL; ++ } ++ break; ++ ++ case GetHubDescriptor: ++ otg_dbg(OTG_DBG_ROOTHUB,"case GetHubDescriptor\n"); ++ desc = (usb_hub_descriptor_t *)buf; ++ desc->desc_length = 9; ++ desc->desc_type = 0x29; ++ desc->port_number = 1; ++ desc->hub_characteristics = 0x08; ++ desc->power_on_to_power_good = 1; ++ desc->hub_control_current = 0; ++ desc->bitmap[0] = 0; ++ desc->bitmap[1] = 0xff; ++ break; ++ ++ case GetHubStatus: ++ otg_dbg(OTG_DBG_ROOTHUB,"case GetHubStatus\n"); ++ otg_mem_set(buf, 0, 4); ++ break; ++ ++ case GetPortStatus: ++ //otg_dbg(OTG_DBG_ROOTHUB_KH,"case GetPortStatus\n"); ++ ++ ++ if (port_flag.b.port_connect_status_change) ++ port_status |= (1 << USB_PORT_FEAT_C_CONNECTION); ++ ++ if (port_flag.b.port_enable_change) ++ port_status |= (1 << USB_PORT_FEAT_C_ENABLE); ++ ++ if (port_flag.b.port_suspend_change) ++ port_status |= (1 << USB_PORT_FEAT_C_SUSPEND); ++ ++ if (port_flag.b.port_reset_change) ++ port_status|= (1 << USB_PORT_FEAT_C_RESET); ++ ++ if (port_flag.b.port_over_current_change) ++ port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT); ++ ++ ++ if (!port_flag.b.port_connect_status) ++ { ++ // ++ // The port is disconnected, which means the core is ++ // either in device mode or it soon will be. Just ++ // return 0's for the remainder of the port status ++ // since the port register can't be read if the core ++ // is in device mode. ++ ++ *((__le32*)buf) = cpu_to_le32(port_status); ++ break; ++ } ++ ++ ++ hprt.d32 = read_reg_32(HPRT); ++ ++ if (hprt.b.prtconnsts) ++ port_status|= (1 << USB_PORT_FEAT_CONNECTION); ++ ++ if (hprt.b.prtena) ++ port_status |= (1 << USB_PORT_FEAT_ENABLE); ++ ++ if (hprt.b.prtsusp) ++ port_status |= (1 << USB_PORT_FEAT_SUSPEND); ++ ++ if (hprt.b.prtovrcurract) ++ port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT); ++ ++ if (hprt.b.prtrst) ++ port_status |= (1 << USB_PORT_FEAT_RESET); ++ ++ if (hprt.b.prtpwr) ++ port_status |= (1 << USB_PORT_FEAT_POWER); ++ ++ if (hprt.b.prtspd == 0) ++ port_status |= (1 << USB_PORT_FEAT_HIGHSPEED); ++ ++ else if (hprt.b.prtspd == 2) ++ port_status |= (1 << USB_PORT_FEAT_LOWSPEED); ++ ++ if (hprt.b.prttstctl) ++ port_status |= (1 << USB_PORT_FEAT_TEST); ++ ++ *((__le32*)buf) = cpu_to_le32(port_status); ++ break; ++ ++ case SetHubFeature: ++ otg_dbg(OTG_DBG_ROOTHUB,"case SetHubFeature\n"); ++ /* No HUB features supported */ ++ break; ++ ++ case SetPortFeature: ++ otg_dbg(OTG_DBG_ROOTHUB,"case SetPortFeature\n"); ++ if (!port_flag.b.port_connect_status) { ++ /* ++ * The port is disconnected, which means the core is ++ * either in device mode or it soon will be. Just ++ * return without doing anything since the port ++ * register can't be written if the core is in device ++ * mode. ++ */ ++ break; ++ } ++ ++ switch (feature) ++ { ++ case USB_PORT_FEAT_SUSPEND: ++ otg_dbg(OTG_DBG_ROOTHUB,"case SetPortFeature -USB_PORT_FEAT_SUSPEND \n"); ++ bus_suspend(); ++ break; ++ ++ case USB_PORT_FEAT_POWER: ++ otg_dbg(OTG_DBG_ROOTHUB,"case SetPortFeature -USB_PORT_FEAT_POWER \n"); ++ hprt.d32 = read_reg_32(HPRT); ++ if(!hprt.b.prtpwr) ++ { ++ //hprt.d32 = 0; ++ hprt.b.prtpwr = 1; ++ write_reg_32(HPRT, hprt.d32); ++ } ++ break; ++ ++ case USB_PORT_FEAT_RESET: ++ otg_dbg(OTG_DBG_ROOTHUB,"case SetPortFeature -USB_PORT_FEAT_RESET \n"); ++ retval = reset_and_enable_port(port); ++ break; ++ ++ case USB_PORT_FEAT_INDICATOR: ++ otg_dbg(OTG_DBG_ROOTHUB,"case USB_PORT_FEAT_INDICATOR\n"); ++ break; ++ ++ default : ++ retval = USB_ERR_FAIL; ++ break; ++ } ++ break; ++ ++ default: ++ retval = USB_ERR_FAIL; ++ otg_dbg(OTG_DBG_ROOTHUB,"root_hub_feature() Function Error\n"); ++ break; ++ } ++ if(retval != USB_ERR_SUCCESS) ++ retval = USB_ERR_FAIL; ++ return retval; ++} ++ ++/** ++ * void bus_suspend(void) ++ * ++ * @brief Make suspend status when this platform support PM Mode ++ * ++ * @param None ++ * ++ * @return None ++ * ++ * @remark ++ * ++ */ ++void bus_suspend(void) ++{ ++ hprt_t hprt; ++ pcgcctl_t pcgcctl; ++ ++ hprt.d32 = 0; ++ pcgcctl.d32 = 0; ++ ++ hprt.b.prtsusp = 1; ++ update_reg_32(HPRT, hprt.d32); ++ ++ pcgcctl.b.pwrclmp = 1; ++ update_reg_32(PCGCCTL,pcgcctl.d32); ++ udelay(1); ++ ++ pcgcctl.b.rstpdwnmodule = 1; ++ update_reg_32(PCGCCTL,pcgcctl.d32); ++ udelay(1); ++ ++ pcgcctl.b.stoppclk = 1; ++ update_reg_32(PCGCCTL,pcgcctl.d32); ++ udelay(1); ++} ++ ++/** ++ * int bus_resume(void) ++ * ++ * @brief Make resume status when this platform support PM Mode ++ * ++ * @param None ++ * ++ * @return USB_ERR_SUCCESS : If success \n ++ * USB_ERR_FAIL : If call fail \n ++ * ++ * @remark ++ * ++ */ ++int bus_resume(void) ++{ ++ /* ++ hprt_t hprt; ++ pcgcctl_t pcgcctl; ++ hprt.d32 = 0; ++ pcgcctl.d32 = 0; ++ ++ pcgcctl.b.stoppclk = 1; ++ clear_reg_32(PCGCCTL,pcgcctl.d32); ++ udelay(1); ++ ++ pcgcctl.b.pwrclmp = 1; ++ clear_reg_32(PCGCCTL,pcgcctl.d32); ++ udelay(1); ++ ++ pcgcctl.b.rstpdwnmodule = 1; ++ clear_reg_32(PCGCCTL,pcgcctl.d32); ++ udelay(1); ++ ++ hprt.b.prtres = 1; ++ update_reg_32(HPRT, hprt.d32); ++ mdelay(20); ++ ++ clear_reg_32(HPRT, hprt.d32); ++ */ ++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "bus_resume()...... \n"); ++ if(oci_init() == USB_ERR_SUCCESS) ++ { ++ if(oci_start() == USB_ERR_SUCCESS) ++ { ++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "OTG Init Success...... \n"); ++ return USB_ERR_SUCCESS; ++ } ++ } ++ return USB_ERR_FAIL; ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-roothub.h linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-roothub.h +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-roothub.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-roothub.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,84 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] :s3c-otg-roothub.h ++ * [Description] : The Header file defines the external and internal functions of RootHub. ++ * [Author] : Jang Kyu Hyeok { kyuhyeok.jang@samsung.com } ++ * [Department] : System LSI Division/Embedded S/W Platform ++ * [Created Date]: 2008/06/13 ++ * [Revision History] ++ * (1) 2008/06/13 by Jang Kyu Hyeok { kyuhyeok.jang@samsung.com } ++ * - Created this file and defines functions of RootHub ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#ifndef _ROOTHUB_H_ ++#define _ROOTHUB_H_ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++#include "s3c-otg-common-errorcode.h" ++#include "s3c-otg-common-regdef.h" ++#include "s3c-otg-common-datastruct.h" ++#include "s3c-otg-hcdi-kal.h" ++#include "s3c-otg-hcdi-memory.h" ++#include "s3c-otg-oci.h" ++ ++typedef union _port_flags_t ++{ ++ /** raw register data */ ++ u32 d32; ++ /** register bits */ ++ struct ++ { ++ unsigned port_connect_status_change : 1; ++ unsigned port_connect_status : 1; ++ unsigned port_reset_change : 1; ++ unsigned port_enable_change : 1; ++ unsigned port_suspend_change : 1; ++ unsigned port_over_current_change : 1; ++ unsigned reserved : 27; ++ } b; ++}port_flags_t; ++ ++ ++ ++__inline__ int root_hub_feature(const u8 port, ++ const u16 typeReq, ++ const u16 feature, ++ void *buf ++ ); ++ ++__inline__ int get_otg_port_status(const u8 port, ++ char *status); ++ ++int reset_and_enable_port(const u8 port); ++ ++void bus_suspend(void); ++ ++int bus_resume(void); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif /* _ROOTHUB_H_ */ ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-scheduler-ischeduler.c linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-scheduler-ischeduler.c +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-scheduler-ischeduler.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-scheduler-ischeduler.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,395 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : Scheduler.c ++ * [Description] : The source file implements the internal functions of Scheduler. ++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com } ++ * [Department] : System LSI Division/System SW Lab ++ * [Created Date]: 2009/2/10 ++ * [Revision History] ++ * (1) 2008/06/03 by Yang Soon Yeal { syatom.yang@samsung.com } ++ * - Created this file and implements functions of Scheduler ++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Optimizing for performance \n ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#include "s3c-otg-scheduler-scheduler.h" ++ ++void init_scheduler(void) ++{ ++ //init_scheduling(); ++ init_transfer_ready_q(); ++} ++ ++/******************************************************************************/ ++/*! ++ * @name int reserve_used_resource_for_periodic(u32 usb_time) ++ * ++ * @brief this function reserves the necessary resource of USB Transfer for Periodic Transfer. ++ * So, this function firstly checks there ares some available USB Time ++ * and Channel resource for USB Transfer. ++ * if there exists necessary resources for Periodic Transfer, then reserves the resource. ++ * ++ * @param [IN] usb_time = indicates the USB Time for the USB Transfer. ++ * ++ * @return USB_ERR_SUCCESS - if success to insert pInsertED to S3CScheduler. ++ * USB_ERR_NO_BANDWIDTH - if fail to reserve the USB Bandwidth. ++ * USB_ERR_NO_CHANNEL - if fail to reserve the Channel. ++ */ ++/******************************************************************************/ ++ ++int reserve_used_resource_for_periodic(u32 usb_time, ++ u8 dev_speed, ++ u8 trans_type) ++{ ++ if(inc_perio_bus_time(usb_time,dev_speed)==USB_ERR_SUCCESS) ++ { ++ if(inc_perio_chnum()==USB_ERR_SUCCESS) ++ { ++ otg_usbcore_inc_usb_bandwidth(usb_time); ++ otg_usbcore_inc_periodic_transfer_cnt(trans_type); ++ return USB_ERR_SUCCESS; ++ } ++ else ++ { ++ dec_perio_bus_time(usb_time); ++ return USB_ERR_NO_CHANNEL; ++ } ++ } ++ else ++ { ++ return USB_ERR_NO_BANDWIDTH; ++ } ++ ++} ++ ++ ++/******************************************************************************/ ++/*! ++ * @name int free_usb_resource_for_periodic(ed_t * pFreeED) ++ * ++ * @brief this function frees the resources to be allocated to pFreeED at S3CScheduler. ++ * that is, this functions only releases the resources to be allocated by S3C6400Scheduler. ++ * ++ * @param [IN] pFreeED = indicates ed_t to have the information of the resource to be released. ++ * ++ * @return USB_ERR_SUCCESS - if success to free the USB Resource. ++ * USB_ERR_FAIL - if fail to free the USB Resrouce. ++ */ ++/******************************************************************************/ ++int free_usb_resource_for_periodic( u32 free_usb_time, ++ u8 free_chnum, ++ u8 trans_type) ++{ ++ if(dec_perio_bus_time(free_usb_time)==USB_ERR_SUCCESS) ++ { ++ if(dec_perio_chnum()==USB_ERR_SUCCESS) ++ { ++ if(free_chnum!=CH_NONE) ++ { ++ oci_channel_dealloc(free_chnum); ++ set_transferring_td_array(free_chnum, 0); ++ } ++ otg_usbcore_des_usb_bandwidth(free_usb_time); ++ otg_usbcore_des_periodic_transfer_cnt(trans_type); ++ return USB_ERR_SUCCESS; ++ } ++ } ++ return USB_ERR_FAIL; ++} ++ ++/******************************************************************************/ ++/*! ++ * @name int remove_ed_from_scheduler(ed_t * remove_ed) ++ * ++ * @brief this function just remove the remove_ed from TransferReadyQ. So if you want to ++ * stop the USB Tranfer of remove_ed or release the releated resources. ++ * you should call another functions of S3CScheduler. ++ * ++ * @param [IN] remove_ed = indicates ed_t to be removed from TransferReadyQ. ++ * ++ * @return USB_ERR_SUCCESS - if success to remove the remove_ed from TransferReadyQ. ++ * USB_ERR_FAIL - if fail to remove the remove_ed from TransferReadyQ. ++ */ ++ /******************************************************************************/ ++int remove_ed_from_scheduler(ed_t *remove_ed) ++{ ++ if(remove_ed->ed_status.is_in_transfer_ready_q) ++ { ++ remove_ed_from_ready_q(remove_ed); ++ remove_ed->ed_status.is_in_transfer_ready_q = false; ++ ++ return USB_ERR_SUCCESS; ++ } ++ else ++ { ++ return USB_ERR_FAIL; ++ } ++} ++ ++/******************************************************************************/ ++/*! ++ * @name int cancel_to_transfer_td(td_t * cancel_td) ++ * ++ * @brief this function stop to execute the USB Transfer of cancel_td and ++ * release the Channel Resources to be allocated the cancel_td ,if the Transfer Type of ++ * cancel_td is NonPeriodic Transfer. ++ * this function don't release any usb resources(Channel, USB Bandwidth) for Periodic Transfer. ++ * if you want to release some usb resources for a periodic Transfer, you should call ++ * the free_usb_resource_for_periodic() ++ * ++ * @param [IN] cancel_td = indicates the td_t to be canceled. ++ * ++ * @return USB_ERR_SUCCESS - if success to cancel the USB Transfer of cancel_td. ++ * USB_ERR_FAIL - if fail to cancel the USB Transfer of cancel_td. ++ */ ++ /******************************************************************************/ ++int cancel_to_transfer_td(td_t *cancel_td) ++{ ++ if(cancel_td->is_transfer_done) ++ { ++ return USB_ERR_FAIL; ++ } ++ ++ if(cancel_td->is_transferring) ++ { ++ int err; ++ ++ err = oci_stop_transfer(cancel_td->cur_stransfer.alloc_chnum); ++ ++ if(err == USB_ERR_SUCCESS) ++ { ++ set_transferring_td_array(cancel_td->cur_stransfer.alloc_chnum,0); ++ ++ cancel_td->cur_stransfer.alloc_chnum = CH_NONE; ++ cancel_td->is_transferring = false; ++ cancel_td->parent_ed_p->ed_status.is_in_transferring = false; ++ cancel_td->parent_ed_p->ed_status.in_transferring_td = 0; ++ cancel_td->parent_ed_p->is_need_to_insert_scheduler = true; ++ ++ if(cancel_td->cur_stransfer.ed_desc_p->endpoint_type == BULK_TRANSFER|| ++ cancel_td->cur_stransfer.ed_desc_p->endpoint_type == CONTROL_TRANSFER ) ++ { ++ dec_nonperio_chnum(); ++ } ++ return err; ++ } ++ else ++ { ++ return err; ++ } ++ } ++ else ++ { ++ return USB_ERR_FAIL; ++ } ++} ++ ++ ++ ++ ++/******************************************************************************/ ++/*! ++ * @name int retransmit(td_t *retrasmit_td) ++ * ++ * @brief this function retransmits the retrasmit_td immediately. ++ * So, the Channel of pRetransmitted is reused for retransmittion. ++ * ++ * @param [IN] retrasmit_td = indicates the pointer ot the td_t to be retransmitted. ++ * ++ * @return USB_ERR_SUCCESS - if success to retransmit the retrasmit_td. ++ * USB_ERR_FAIL - if fail to retransmit the retrasmit_td. ++ */ ++ /******************************************************************************/ ++int retransmit(td_t *retrasmit_td) ++{ ++ u32 td_addr=0; ++ ++ if(get_transferring_td_array(retrasmit_td->cur_stransfer.alloc_chnum,&td_addr)==USB_ERR_SUCCESS) ++ { ++ if(td_addr == (u32)retrasmit_td) ++ { ++ if(oci_start_transfer(&retrasmit_td->cur_stransfer)== retrasmit_td->cur_stransfer.alloc_chnum) ++ { ++ retrasmit_td->is_transferring = true; ++ retrasmit_td->parent_ed_p->ed_status.in_transferring_td = (u32)retrasmit_td; ++ retrasmit_td->parent_ed_p->ed_status.is_in_transfer_ready_q = false; ++ retrasmit_td->parent_ed_p->ed_status.is_in_transferring = true; ++ } ++ } ++ else ++ { ++ return USB_ERR_FAIL; ++ } ++ } ++ else ++ { ++ return USB_ERR_FAIL; ++ } ++ ++ return USB_ERR_SUCCESS; ++ ++} ++ ++/******************************************************************************/ ++/*! ++ * @name int reschedule(td_t *reschedule_td) ++ * ++ * @brief this function re-schedules the reschedule_td. ++ * So, the Channel of pRescheuleTD is released and reschedule_td is inserted to TransferReadyQ. ++ * ++ * @param [IN] reschedule_td = indicates the pointer ot the td_t to be rescheduled. ++ * ++ * @return USB_ERR_SUCCESS - if success to re-schedule the reschedule_td. ++ * USB_ERR_FAIL - if fail to re-schedule the reschedule_td. ++ */ ++ /******************************************************************************/ ++int reschedule(td_t *reschedule_td) ++{ ++ u32 td_addr; ++ ++ if(get_transferring_td_array(reschedule_td->cur_stransfer.alloc_chnum, &td_addr)==USB_ERR_SUCCESS) ++ { ++ if((u32)reschedule_td == td_addr) ++ { ++ set_transferring_td_array(reschedule_td->cur_stransfer.alloc_chnum, 0); ++ oci_channel_dealloc(reschedule_td->cur_stransfer.alloc_chnum); ++ ++ reschedule_td->cur_stransfer.alloc_chnum = CH_NONE; ++ reschedule_td->parent_ed_p->is_need_to_insert_scheduler = true; ++ reschedule_td->parent_ed_p->ed_status.in_transferring_td = 0; ++ ++ if(reschedule_td->parent_ed_p->ed_desc.endpoint_type == BULK_TRANSFER|| ++ reschedule_td->parent_ed_p->ed_desc.endpoint_type == CONTROL_TRANSFER ) ++ { ++ //Increase the available Channel ++ dec_nonperio_chnum(); ++ ++ } ++ ++ insert_ed_to_ready_q(reschedule_td->parent_ed_p, false); ++ reschedule_td->parent_ed_p->ed_status.is_in_transfer_ready_q =true; ++ ++ } ++ else ++ { ++ //this case is not support.... ++ } ++ } ++ return USB_ERR_SUCCESS; ++ ++} ++ ++/******************************************************************************/ ++/*! ++ * @name int deallocate(td_t *deallocate_td) ++ * ++ * @brief this function frees resources to be allocated deallocate_td by S3CScheduler. ++ * this function just free the resource by S3CScheduler. that is, Channel Resource. ++ * if there are another td_t at ed_t, deallocate() insert the ed_t to TransferReadyQ. ++ * ++ * @param [IN] deallocate_td = indicates the pointer ot the td_t to be deallocated. ++ * ++ * @return USB_ERR_SUCCESS - if success to dealloate the resources for the deallocate_td. ++ * USB_ERR_FAIL - if fail to dealloate the resources for the deallocate_td. ++ */ ++ /******************************************************************************/ ++int deallocate(td_t *deallocate_td) ++{ ++ u32 td_addr; ++ ++ if(get_transferring_td_array(deallocate_td->cur_stransfer.alloc_chnum , &td_addr)==USB_ERR_SUCCESS) ++ { ++ if((u32)deallocate_td == td_addr) ++ { ++ set_transferring_td_array(deallocate_td->cur_stransfer.alloc_chnum, 0); ++ oci_channel_dealloc(deallocate_td->cur_stransfer.alloc_chnum); ++ ++ deallocate_td->cur_stransfer.alloc_chnum = CH_NONE; ++ ++ if(deallocate_td->parent_ed_p->ed_desc.endpoint_type == BULK_TRANSFER|| ++ deallocate_td->parent_ed_p->ed_desc.endpoint_type == CONTROL_TRANSFER ) ++ { ++ //Increase the available Channel ++ dec_nonperio_chnum(); ++ } ++ ++ deallocate_td->parent_ed_p->is_need_to_insert_scheduler = true; ++ ++ if(deallocate_td->parent_ed_p->num_td) ++ { ++ //insert ed_t to TransferReadyQ. ++ insert_ed_to_ready_q(deallocate_td->parent_ed_p , false); ++ deallocate_td->parent_ed_p->ed_status.is_in_transfer_ready_q = true; ++ deallocate_td->parent_ed_p->is_need_to_insert_scheduler = false; ++ } ++ return USB_ERR_SUCCESS; ++ } ++ else ++ { ++ return USB_ERR_FAIL; ++ } ++ } ++ else ++ { ++ return USB_ERR_FAIL; ++ } ++ ++} ++ ++//TBD.... ++void do_schedule(void) ++{ ++ if(get_avail_chnum()) ++ { ++ do_periodic_schedule(); ++ do_nonperiodic_schedule(); ++ } ++} ++ ++/******************************************************************************/ ++/*! ++ * @name int get_td_info(u8 chnum, ++ * unsigned int *td_addr_p) ++ * ++ * @brief this function returns the pointer of td_t at TransferringTDArray[chnum] ++ * ++ * @param [IN] chnum = indicates the index of TransferringTDArray ++ * to include the address of td_t which we gets ++ * [OUT] td_addr_p= indicate pointer to store the address of td_t. ++ * ++ * @return USB_ERR_SUCCESS -if success to get the address of td_t. ++ * USB_ERR_FAIL -if fail to get the address of td_t. ++ */ ++ /******************************************************************************/ ++int get_td_info( u8 chnum, ++ unsigned int *td_addr_p) ++{ ++ u32 td_addr; ++ ++ if(get_transferring_td_array(chnum, &td_addr)==USB_ERR_SUCCESS) ++ { ++ *td_addr_p = td_addr; ++ return USB_ERR_SUCCESS; ++ } ++ ++ return USB_ERR_FAIL; ++} ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-scheduler-readyq.c linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-scheduler-readyq.c +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-scheduler-readyq.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-scheduler-readyq.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,253 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : TransferReadyQ.c ++ * [Description] : The source file implements the internal functions of TransferReadyQ. ++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com } ++ * [Department] : System LSI Division/System SW Lab ++ * [Created Date]: 2008/06/04 ++ * [Revision History] ++ * (1) 2008/06/04 by Yang Soon Yeal { syatom.yang@samsung.com } ++ * - Created this file and implements functions of TransferReadyQ. ++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Optimizing for performance \n ++ * ++ ****************************************************************************/ ++ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#include "s3c-otg-scheduler-scheduler.h" ++ ++static trans_ready_q_t periodic_trans_ready_q; ++static trans_ready_q_t nonperiodic_trans_ready_q; ++ ++/******************************************************************************/ ++/*! ++ * @name void init_transfer_ready_q(void) ++ * ++ * @brief this function initiates PeriodicTransferReadyQ and NonPeriodicTransferReadyQ. ++ * ++ * ++ * @param void ++ * ++ * @return void. ++ */ ++/******************************************************************************/ ++void init_transfer_ready_q(void) ++{ ++ ++ otg_dbg(OTG_DBG_SCHEDULE,"start init_transfer_ready_q\n"); ++ ++ otg_list_init(&periodic_trans_ready_q.trans_ready_q_list_head); ++ periodic_trans_ready_q.is_periodic_transfer = true; ++ periodic_trans_ready_q.trans_ready_entry_num = 0; ++ periodic_trans_ready_q.total_alloc_chnum = 0; ++ periodic_trans_ready_q.total_perio_bus_bandwidth = 0; ++ ++ otg_list_init(&nonperiodic_trans_ready_q.trans_ready_q_list_head); ++ nonperiodic_trans_ready_q.is_periodic_transfer = false; ++ nonperiodic_trans_ready_q.trans_ready_entry_num = 0; ++ nonperiodic_trans_ready_q.total_alloc_chnum = 0; ++ nonperiodic_trans_ready_q.total_perio_bus_bandwidth = 0; ++ ++ ++} ++ ++ ++/******************************************************************************/ ++/*! ++ * @name int insert_ed_to_ready_q(ed_t *insert_ed, ++ * bool f_isfirst) ++ * ++ * @brief this function inserts ed_t * to TransferReadyQ. ++ * ++ * ++ * @param [IN] insert_ed = indicates the ed_t to be inserted to TransferReadyQ. ++ * [IN] f_isfirst = indicates whether the insert_ed is inserted as first entry of TransferReadyQ. ++ * ++ * @return USB_ERR_SUCCESS -if successes to insert the insert_ed to TransferReadyQ. ++ * USB_ERR_FAILl -if fails to insert the insert_ed to TransferReadyQ. ++ */ ++/******************************************************************************/ ++int insert_ed_to_ready_q(ed_t *insert_ed, ++ bool f_isfirst) ++{ ++ ++ if(insert_ed->ed_desc.endpoint_type == BULK_TRANSFER|| ++ insert_ed->ed_desc.endpoint_type == CONTROL_TRANSFER) ++ { ++ if(f_isfirst) ++ { ++ otg_list_push_next(&insert_ed->trans_ready_q_list_entry,&nonperiodic_trans_ready_q.trans_ready_q_list_head); ++ } ++ else ++ { ++ otg_list_push_prev(&insert_ed->trans_ready_q_list_entry,&nonperiodic_trans_ready_q.trans_ready_q_list_head); ++ } ++ nonperiodic_trans_ready_q.trans_ready_entry_num++; ++ } ++ else ++ { ++ if(f_isfirst) ++ { ++ otg_list_push_next(&insert_ed->trans_ready_q_list_entry,&periodic_trans_ready_q.trans_ready_q_list_head); ++ } ++ else ++ { ++ otg_list_push_prev(&insert_ed->trans_ready_q_list_entry,&periodic_trans_ready_q.trans_ready_q_list_head); ++ } ++ periodic_trans_ready_q.trans_ready_entry_num++; ++ } ++ ++ return USB_ERR_SUCCESS; ++ ++} ++ ++ ++u32 get_periodic_ready_q_entity_num(void) ++{ ++ return periodic_trans_ready_q.trans_ready_entry_num; ++} ++/******************************************************************************/ ++/*! ++ * @name int remove_ed_from_ready_q(ed_t *remove_ed) ++ * ++ * @brief this function removes ed_t * from TransferReadyQ. ++ * ++ * ++ * @param [IN] remove_ed = indicate the ed_t to be removed from TransferReadyQ. ++ * ++ * @return USB_ERR_SUCCESS -if successes to remove the remove_ed from TransferReadyQ. ++ * USB_ERR_FAILl -if fails to remove the remove_ed from TransferReadyQ. ++ */ ++/******************************************************************************/ ++int remove_ed_from_ready_q(ed_t *remove_ed) ++{ ++// SPINLOCK_t SLForRemoveED_t = SPIN_LOCK_INIT; ++// u32 uiSLFlag=0; ++ ++ otg_list_pop(&remove_ed->trans_ready_q_list_entry); ++ ++ if(remove_ed->ed_desc.endpoint_type == BULK_TRANSFER|| ++ remove_ed->ed_desc.endpoint_type == CONTROL_TRANSFER) ++ { ++// spin_lock_irg_save_otg(&SLForRemoveED_t, uiSLFlag); ++// otg_list_pop(&remove_ed->trans_ready_q_list_entry); ++ nonperiodic_trans_ready_q.trans_ready_entry_num--; ++// spin_unlock_irq_save_otg(&SLForRemoveED_t, uiSLFlag); ++ } ++ else ++ { ++// spin_lock_irg_save_otg(&SLForRemoveED_t, uiSLFlag); ++// otg_list_pop(&remove_ed->trans_ready_q_list_entry); ++ periodic_trans_ready_q.trans_ready_entry_num--; ++// spin_unlock_irq_save_otg(&SLForRemoveED_t, uiSLFlag); ++ } ++ ++ return USB_ERR_SUCCESS; ++ ++} ++ ++//by ss1 unused func ++/* ++bool check_ed_on_ready_q(ed_t *check_ed_p) ++{ ++ ++ if(check_ed_p->ed_status.is_in_transfer_ready_q) ++ return true; ++ else ++ return false; ++}*/ ++ ++/******************************************************************************/ ++/*! ++ * @name int get_ed_from_ready_q(bool f_isperiodic, ++ * td_t **get_ed) ++ * ++ * @brief this function returns the first entity of TransferReadyQ. ++ * if there are some ed_t on TransferReadyQ, this function pops first ed_t from TransferReadyQ. ++ * So, the TransferReadyQ don's has the poped ed_t. ++ * ++ * ++ * @param [IN] f_isperiodic = indicate whether Periodic or not ++ * [OUT] get_ed = indicate the double pointer to store the address of first entity ++ * on TransferReadyQ. ++ * ++ * @return USB_ERR_SUCCESS -if successes to get frist ed_t from TransferReadyQ. ++ * USB_ERR_NO_ENTITY -if fails to get frist ed_t from TransferReadyQ ++ * because there is no entity on TransferReadyQ. ++ */ ++/******************************************************************************/ ++ ++int get_ed_from_ready_q(bool f_isperiodic, ++ ed_t **get_ed) ++{ ++ if(f_isperiodic) ++ { ++ otg_list_head *transreadyq_list_entity=NULL; ++ ++ if(periodic_trans_ready_q.trans_ready_entry_num==0) ++ { ++ return USB_ERR_NO_ENTITY; ++ } ++ ++ transreadyq_list_entity = periodic_trans_ready_q.trans_ready_q_list_head.next; ++ ++ //if(transreadyq_list_entity!= &periodic_trans_ready_q.trans_ready_q_list_head) ++ if(!otg_list_empty(&periodic_trans_ready_q.trans_ready_q_list_head)) ++ { ++ *get_ed = otg_list_get_node(transreadyq_list_entity,ed_t,trans_ready_q_list_entry); ++ otg_list_pop(transreadyq_list_entity); ++ periodic_trans_ready_q.trans_ready_entry_num--; ++ ++ return USB_ERR_SUCCESS; ++ } ++ else ++ { ++ return USB_ERR_NO_ENTITY; ++ } ++ } ++ else ++ { ++ otg_list_head *transreadyq_list_entity=NULL; ++ ++ if(nonperiodic_trans_ready_q.trans_ready_entry_num==0) ++ { ++ return USB_ERR_NO_ENTITY; ++ } ++ ++ transreadyq_list_entity = nonperiodic_trans_ready_q.trans_ready_q_list_head.next; ++ ++ //if(transreadyq_list_entity!= &nonperiodic_trans_ready_q.trans_ready_q_list_head) ++ if(!otg_list_empty(&nonperiodic_trans_ready_q.trans_ready_q_list_head)) ++ { ++ *get_ed = otg_list_get_node(transreadyq_list_entity,ed_t, trans_ready_q_list_entry); ++ ++ otg_list_pop(transreadyq_list_entity); ++ ++ nonperiodic_trans_ready_q.trans_ready_entry_num--; ++ ++ return USB_ERR_SUCCESS; ++ } ++ else ++ { ++ return USB_ERR_NO_ENTITY; ++ } ++ } ++} ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-scheduler-scheduler.c linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-scheduler-scheduler.c +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-scheduler-scheduler.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-scheduler-scheduler.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,449 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : Scheduler.c ++ * [Description] : The source file implements the internal functions of Scheduler. ++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com } ++ * [Department] : System LSI Division/System SW Lab ++ * [Created Date]: 2008/06/04 ++ * [Revision History] ++ * (1) 2008/06/03 by Yang Soon Yeal { syatom.yang@samsung.com } ++ * - Created this file and implements functions of Scheduler ++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Optimizing for performance \n ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#include "s3c-otg-scheduler-scheduler.h" ++ ++//Define constant variables ++ ++//the max periodic bus time is 80%*125us on High Speed Mode ++static const u32 perio_highbustime_threshold = 100; ++ ++//the max periodic bus time is 90%*1000us(1ms) on Full/Low Speed Mode . ++static const u32 perio_fullbustime_threshold = 900; ++ ++static const u8 perio_chnum_threshold = 14; ++//static const u8 total_chnum_threshold = 16; ++static u8 total_chnum_threshold = 16; ++ ++ //Define global variables ++ ++static u32 perio_used_bustime = 0; ++static u8 perio_used_chnum = 0; ++static u8 nonperio_used_chnum = 0; ++static u8 total_used_chnum = 0; ++static u32 transferring_td_array[16]={0}; ++ ++ ++int inc_perio_bus_time(u32 bus_time, u8 dev_speed) ++{ ++ switch(dev_speed) ++ { ++ case HIGH_SPEED_OTG: ++ if((bus_time+perio_used_bustime)<=perio_highbustime_threshold) ++ { ++ perio_used_bustime=+bus_time; ++ return USB_ERR_SUCCESS; ++ } ++ else ++ { ++ return USB_ERR_FAIL; ++ } ++ ++ case LOW_SPEED_OTG: ++ case FULL_SPEED_OTG: ++ if((bus_time+perio_used_bustime)<=perio_fullbustime_threshold) ++ { ++ perio_used_bustime=+bus_time; ++ return USB_ERR_SUCCESS; ++ } ++ else ++ { ++ return USB_ERR_FAIL; ++ } ++ case SUPER_SPEED_OTG: ++ break; ++ default: ++ break; ++ } ++ return USB_ERR_FAIL; ++} ++ ++int dec_perio_bus_time(u32 bus_time) ++{ ++ if(perio_used_bustime >= bus_time ) ++ { ++ perio_used_bustime =- bus_time; ++ return USB_ERR_SUCCESS; ++ } ++ else ++ { ++ return USB_ERR_FAIL; ++ } ++} ++ ++int inc_perio_chnum(void) ++{ ++ if(perio_used_chnum0) ++ { ++ if(total_used_chnum>0) ++ { ++ perio_used_chnum--; ++ total_used_chnum--; ++ return USB_ERR_SUCCESS; ++ } ++ } ++ return USB_ERR_FAIL; ++} ++ ++int inc_non_perio_chnum(void) ++{ ++ if(nonperio_used_chnum0) ++ { ++ if(total_used_chnum>0) ++ { ++ nonperio_used_chnum--; ++ total_used_chnum--; ++ return USB_ERR_SUCCESS; ++ } ++ } ++ return USB_ERR_FAIL; ++} ++ ++int get_transferring_td_array(u8 chnum, unsigned int *td_addr) ++{ ++ if(transferring_td_array[chnum]!=0) ++ { ++ *td_addr = transferring_td_array[chnum]; ++ return USB_ERR_SUCCESS; ++ } ++ ++ return USB_ERR_FAIL; ++} ++ ++int set_transferring_td_array(u8 chnum, u32 td_addr) ++{ ++ if(td_addr ==0) ++ { ++ transferring_td_array[chnum] = td_addr; ++ return USB_ERR_SUCCESS; ++ } ++ ++ if(transferring_td_array[chnum] == 0) ++ { ++ transferring_td_array[chnum] = td_addr; ++ return USB_ERR_SUCCESS; ++ } ++ else ++ { ++ return USB_ERR_FAIL; ++ } ++} ++ ++/******************************************************************************/ ++/*! ++ * @name int insert_ed_to_scheduler(ed_t *insert_ed) ++ * ++ * @brief this function transfers the insert_ed to S3C6400Scheduler, and ++ * after that, the insert_ed is inserted to TransferReadyQ and scheduled by Scheduler. ++ * ++ * ++ * @param [IN] insert_ed = indicates pointer of ed_t to be inserted to TransferReadyQ. ++ * ++ * @return USB_ERR_ALREADY_EXIST - if the insert_ed is already existed. ++ * USB_ERR_SUCCESS - if success to insert insert_ed to S3CScheduler. ++ */ ++/******************************************************************************/ ++int insert_ed_to_scheduler(ed_t *insert_ed) ++{ ++ if(!insert_ed->is_need_to_insert_scheduler) ++ { ++ return USB_ERR_ALREADY_EXIST; ++ } ++ ++ insert_ed_to_ready_q(insert_ed, false); ++ insert_ed->is_need_to_insert_scheduler = false; ++ insert_ed->ed_status.is_in_transfer_ready_q = true; ++ ++ do_periodic_schedule(); ++ do_nonperiodic_schedule(); ++ ++ return USB_ERR_SUCCESS; ++} ++ ++/******************************************************************************/ ++/*! ++ * @name int do_periodic_schedule(void) ++ * ++ * @brief this function schedules PeriodicTransferReadyQ. ++ * this function checks whether PeriodicTransferReadyQ has some ed_t. ++ * if there are some ed_t on PeriodicTransferReadyQ ++ * , this function request to start USB Trasnfer to S3C6400OCI. ++ * ++ * ++ * @param void ++ * ++ * @return void ++ */ ++/******************************************************************************/ ++void do_periodic_schedule(void) ++{ ++ ed_t *scheduling_ed= NULL; ++ int err_sched = USB_ERR_SUCCESS; ++ u32 sched_cnt = 0; ++ ++ otg_dbg(OTG_DBG_SCHEDULE,"*******Start to DoPeriodicSchedul*********\n"); ++ ++ sched_cnt = get_periodic_ready_q_entity_num(); ++ ++ while(sched_cnt) ++ { ++ ++ //in periodic transfser, the channel resource was already reserved. ++ //So, we don't need this routine... ++ ++start_sched_perio_transfer: ++ if(!sched_cnt) ++ goto end_sched_perio_transfer; ++ ++ err_sched = get_ed_from_ready_q(true, &scheduling_ed); ++ ++ if(err_sched==USB_ERR_SUCCESS) ++ { ++ otg_list_head *td_list_entry; ++ td_t *td; ++ u32 cur_frame_num = 0; ++ ++ otg_dbg(OTG_DBG_SCHEDULE,"the ed_t to be scheduled :%d",(int)scheduling_ed); ++ sched_cnt--; ++ td_list_entry = scheduling_ed->td_list_entry.next; ++ ++ if(td_list_entry == &scheduling_ed->td_list_entry) ++ { ++ //scheduling_ed has no td_t. so we schedules another ed_t on PeriodicTransferReadyQ. ++ goto start_sched_perio_transfer; ++ } ++ ++ if(scheduling_ed->ed_status.is_in_transferring) ++ { ++ //scheduling_ed is already Scheduled. so we schedules another ed_t on PeriodicTransferReadyQ. ++ goto start_sched_perio_transfer; ++ } ++ ++ cur_frame_num = oci_get_frame_num(); ++ ++ if(((cur_frame_num-scheduling_ed->ed_desc.sched_frame)&HFNUM_MAX_FRNUM)>(HFNUM_MAX_FRNUM>>1)) ++ { ++ insert_ed_to_ready_q(scheduling_ed, false); ++ goto start_sched_perio_transfer; ++ } ++ ++ td = otg_list_get_node(td_list_entry, td_t, td_list_entry); ++ ++ if((!td->is_transferring) && (!td->is_transfer_done)) ++ { ++ u8 alloc_ch; ++ otg_dbg(OTG_DBG_SCHEDULE,"the td_t to be scheduled :%d",(int)td); ++ alloc_ch = oci_start_transfer(&td->cur_stransfer); ++ if(alloc_chcur_stransfer.alloc_chnum = alloc_ch; ++ transferring_td_array[alloc_ch] = (u32)td; ++ ++ scheduling_ed->ed_status.is_in_transferring = true; ++ scheduling_ed->ed_status.is_in_transfer_ready_q = false; ++ scheduling_ed->ed_status.in_transferring_td = (u32)td; ++ ++ td->is_transferring = true; ++ } ++ else ++ { ++ //we should insert the ed_t to TransferReadyQ, because the USB Transfer of the ed_t is failed. ++ scheduling_ed->ed_status.is_in_transferring = false; ++ scheduling_ed->ed_status.is_in_transfer_ready_q = true; ++ scheduling_ed->ed_status.in_transferring_td = 0; ++ ++ insert_ed_to_ready_q(scheduling_ed,true); ++ ++ scheduling_ed->is_need_to_insert_scheduler = false; ++ goto end_sched_perio_transfer; ++ } ++ ++ } ++ else ++ { // the selected td_t was already transferring or completed to transfer. ++ //we should decide how to control this case. ++ goto end_sched_perio_transfer; ++ } ++ ++ ++ } ++ else ++ { ++ // there is no ED on PeriodicTransferQ. So we finish scheduling. ++ goto end_sched_perio_transfer; ++ } ++ } ++ ++end_sched_perio_transfer: ++ ++ return; ++} ++ ++ ++/******************************************************************************/ ++/*! ++ * @name int do_nonperiodic_schedule(void) ++ * ++ * @brief this function start to schedule thie NonPeriodicTransferReadyQ. ++ * this function checks whether NonPeriodicTransferReadyQ has some ed_t. ++ * if there are some ed_t on NonPeriodicTransferReadyQ ++ * , this function request to start USB Trasnfer to S3C6400OCI. ++ * ++ * ++ * @param void ++ * ++ * @return void ++ */ ++/******************************************************************************/ ++void do_nonperiodic_schedule(void) ++{ ++ if(total_used_chnumtd_list_entry.next; ++ ++ //if(td_list_entry == &scheduling_ed->td_list_entry) ++ if(otg_list_empty(&scheduling_ed->td_list_entry)) ++ { ++ //scheduling_ed has no td_t. so we schedules another ed_t on PeriodicTransferReadyQ. ++ goto start_sched_nonperio_transfer; ++ } ++ ++ if(scheduling_ed->ed_status.is_in_transferring) ++ { ++ //scheduling_ed is already Scheduled. so we schedules another ed_t on PeriodicTransferReadyQ. ++ goto start_sched_nonperio_transfer; ++ } ++ ++ td = otg_list_get_node(td_list_entry, td_t, td_list_entry); ++ ++ if((!td->is_transferring) && (!td->is_transfer_done)) ++ { ++ u8 alloc_ch; ++ ++ alloc_ch =oci_start_transfer(&td->cur_stransfer); ++ ++ if(alloc_chcur_stransfer.alloc_chnum = alloc_ch; ++ transferring_td_array[alloc_ch] = (u32)td; ++ ++ inc_non_perio_chnum(); ++ ++ scheduling_ed->ed_status.is_in_transferring = true; ++ scheduling_ed->ed_status.is_in_transfer_ready_q = false; ++ scheduling_ed->ed_status.in_transferring_td =(u32)td; ++ td->is_transferring = true; ++ } ++ else ++ { ++ //we should insert the ed_t to TransferReadyQ, because the USB Transfer of the ed_t is failed. ++ scheduling_ed->ed_status.is_in_transferring = false; ++ scheduling_ed->ed_status.in_transferring_td =0; ++ insert_ed_to_ready_q(scheduling_ed,true); ++ scheduling_ed->ed_status.is_in_transfer_ready_q = true; ++ ++ goto end_sched_nonperio_transfer; ++ } ++ } ++ else ++ { ++ goto end_sched_nonperio_transfer; ++ } ++ } ++ else ++ { //there is no ed_t on NonPeriodicTransferReadyQ. ++ //So, we finish do_nonperiodic_schedule(). ++ goto end_sched_nonperio_transfer; ++ } ++ } ++ } ++ ++end_sched_nonperio_transfer: ++ ++ return; ++} ++ ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-scheduler-scheduler.h linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-scheduler-scheduler.h +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-scheduler-scheduler.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-scheduler-scheduler.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,102 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : Scheduler.h ++ * [Description] : The Header file defines the external and internal functions of Scheduler. ++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com } ++ * [Department] : System LSI Division/System SW Lab ++ * [Created Date]: 2008/06/03 ++ * [Revision History] ++ * (1) 2008/06/03 by Yang Soon Yeal { syatom.yang@samsung.com } ++ * - Created this file and defines functions of Scheduler ++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Optimizing for performance \n ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#ifndef _SCHEDULER_H ++#define _SCHEDULER_H ++ ++/* ++// ---------------------------------------------------------------------------- ++// Include files : None. ++// ---------------------------------------------------------------------------- ++*/ ++//#include "s3c-otg-common-typedef.h" ++#include "s3c-otg-common-const.h" ++#include "s3c-otg-common-errorcode.h" ++#include "s3c-otg-common-datastruct.h" ++#include "s3c-otg-hcdi-memory.h" ++#include "s3c-otg-hcdi-kal.h" ++#include "s3c-otg-hcdi-debug.h" ++#include "s3c-otg-oci.h" ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++ ++//Defines external functions of IScheduler.c ++extern void init_scheduler(void); ++extern int reserve_used_resource_for_periodic(u32 usb_time,u8 dev_speed, u8 trans_type); ++extern int free_usb_resource_for_periodic(u32 free_usb_time, u8 free_chnum, u8 trans_type); ++extern int remove_ed_from_scheduler(ed_t *remove_ed); ++extern int cancel_to_transfer_td(td_t *cancel_td); ++extern int retransmit(td_t *retransmit_td); ++extern int reschedule(td_t *resched_td); ++extern int deallocate(td_t *dealloc_td); ++extern void do_schedule(void); ++ ++extern int get_td_info(u8 chnum,unsigned int *td_addr); ++ ++ ++// Defines functiions of TranferReadyQ. ++void init_transfer_ready_q(void); ++int insert_ed_to_ready_q(ed_t *insert_ed, bool f_isfirst); ++int remove_ed_from_ready_q(ed_t *remove_ed); ++int get_ed_from_ready_q(bool f_isperiodic, ed_t **get_ed); ++ ++//Define functions of Scheduler ++void do_periodic_schedule(void); ++void do_nonperiodic_schedule(void); ++int set_transferring_td_array(u8 chnum, u32 td_addr); ++int get_transferring_td_array(u8 chnum, unsigned int *td_addr); ++ ++ ++//Define fuctions to manage some static global variable. ++int inc_perio_bus_time(u32 uiBusTime, u8 dev_speed); ++int dec_perio_bus_time(u32 uiBusTime); ++ ++u8 get_avail_chnum(void); ++int inc_perio_chnum(void); ++int dec_perio_chnum(void); ++int inc_non_perio_chnum(void); ++int dec_nonperio_chnum(void); ++u32 get_periodic_ready_q_entity_num(void); ++ ++int insert_ed_to_scheduler(ed_t * insert_ed); ++ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++ ++#endif ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transfer-common.c linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transfer-common.c +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transfer-common.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transfer-common.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,841 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : Commons3c-otg-transfer-transfer.h ++ * [Description] : This source file implements the functions to be defined at CommonTransfer Module. ++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com } ++ * [Department] : System LSI Division/System SW Lab ++ * [Created Date]: 2008/06/03 ++ * [Revision History] ++ * (1) 2008/06/03 by Yang Soon Yeal { syatom.yang@samsung.com } ++ * - Created this file and implements some functions of CommonTransfer. ++ * (2) 2008/07/15 by SeungSoo Yang ( ss1.yang@samsung.com )n ++ * - Optimizing for performance \n ++ * (3) 2008/08/18 by SeungSoo Yang ( ss1.yang@samsung.com ) ++ * - Modifying for successful rmmod & disconnecting \n ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#include "s3c-otg-transfer-transfer.h" ++ ++// the header pointer to indicate the ED_list to manage the ed_t to be created and initiated. ++otg_list_head ed_list_head; ++u32 ref_periodic_transfer; ++ ++/******************************************************************************/ ++/*! ++ * @name void init_transfer(void) ++ * ++ * @brief this function initiates the S3CTranfer module. that is, this functions initiates ++ * the ED_list_head OTG List which manages the all ed_t to be existed. ++ * ++ * @param void ++ * ++ * @return void ++ */ ++/******************************************************************************/ ++ ++void init_transfer(void) ++{ ++ otg_dbg(OTG_DBG_TRANSFER,"start to init_transfer\n"); ++ otg_list_init(&ed_list_head); ++ ref_periodic_transfer = 0; ++ ++} ++ ++ ++/******************************************************************************/ ++/*! ++ * @name void DeInitTransfer(void) ++ * ++ * @brief this function Deinitiates the S3CTranfer module. this functions check which there are ++ * some ed_t on ED_list_head. if some ed_t exists, deinit_transfer() deletes the ed_t. ++ * ++ * ++ * @param void ++ * ++ * @return void ++ */ ++/******************************************************************************/ ++void deinit_transfer(void) ++{ ++ otg_list_head *ed_list_member; ++ ed_t *delete_ed_p; ++ ++ while(otg_list_empty(&ed_list_head) != true) ++ { ++ ed_list_member = ed_list_head.next; ++ ++ // otg_list_pop(ed_list_member); ++ ++ delete_ed_p= otg_list_get_node(ed_list_member,ed_t,ed_list_entry); ++ ++ delete_ed(delete_ed_p); ++ } ++} ++ ++ ++/******************************************************************************/ ++/*! ++ * @name int delete_ed(ed_t *delete_ed) ++ * ++ * @brief this function delete the delete_ed. ++ * if there is some available TD_ts on delete_ed, then this function also deletes these td_t ++ * ++ * ++ * @param [IN] delete_ed = indicates the address of ed_t to be deleted. ++ * ++ * @return USB_ERR_SUCCESS -if successes to delete the ed_t. ++ * USB_ERR_FAILl -if fails to delete the ed_t. ++ */ ++/******************************************************************************/ ++int delete_ed(ed_t *delete_ed) ++{ ++ otg_kal_make_ep_null(delete_ed); ++ ++ if(delete_ed->num_td) ++ { ++ cancel_all_td(delete_ed); ++/** ++ need to giveback of td's urb with considering life-cycle of ++ TD, ED, urb->hcpriv, td->private, ep->hcpriv, td->parentED ++ (commented by ss1.yang) ++*/ ++ } ++ ++ otg_list_pop(&delete_ed->ed_list_entry); ++ ++ if(delete_ed->ed_desc.endpoint_type == INT_TRANSFER || ++ delete_ed->ed_desc.endpoint_type == ISOCH_TRANSFER) ++ { ++ ref_periodic_transfer--; ++ } ++ ++ if(ref_periodic_transfer==0) ++ { ++ disable_sof(); ++ } ++ otg_mem_free(delete_ed); ++ ++ return USB_ERR_SUCCESS; ++} ++ ++ ++/******************************************************************************/ ++/*! ++ * @name int delete_td(td_t *delete_td) ++ * ++ * @brief this function frees memory resource for the delete_td. ++ * and if delete_td is transferring USB Transfer, then this function request to cancel ++ * the USB Transfer to S3CScheduler. ++ * ++ * ++ * @param [OUT] new_td_p = returns the address of the new td_t . ++ * ++ * @return USB_ERR_SUCCESS -if successes to create the new td_t. ++ * USB_ERR_FAILl -if fails to create to new td_t. ++ */ ++/******************************************************************************/ ++int delete_td(td_t *delete_td) ++{ ++ ++ if(delete_td->is_transferring) ++ { ++ //at this case, we should cancel the USB Transfer. ++ cancel_to_transfer_td(delete_td); ++ } ++ ++ otg_mem_free(delete_td); ++ return USB_ERR_SUCCESS; ++} ++ ++ ++int create_isoch_packet_desc( isoch_packet_desc_t **new_isoch_packet_desc, ++ u32 isoch_packet_num) ++{ ++ return otg_mem_alloc((void **)new_isoch_packet_desc, (u16)sizeof(isoch_packet_desc_t)*isoch_packet_num,USB_MEM_SYNC); ++} ++ ++int delete_isoch_packet_desc( isoch_packet_desc_t *del_isoch_packet_desc, ++ u32 isoch_packet_num) ++{ ++ return otg_mem_free(del_isoch_packet_desc); ++} ++ ++ ++/******************************************************************************/ ++/*! ++ * @name void init_isoch_packet_desc( isoch_packet_desc_t *init_isoch_packet_desc, ++ * u32 isoch_packet_start_addr, ++ * u32 isoch_packet_size, ++ * u32 index) ++ * ++ * @brief this function initiates the isoch_packet_desc_t[index]. ++ * ++ * ++ * @param [OUT] init_isoch_packet_desc = indicates the pointer of IsochPackDesc_t to be initiated. ++ * [IN] isoch_packet_start_addr = indicates the start address of the buffer to be used ++ * at USB Isochronous Transfer. ++ * [IN] isoch_packet_size = indicates the size of Isochronous packet. ++ * [IN] index = indicates the index to be mapped with this init_isoch_packet_desc. ++ * ++ * @return void ++ */ ++/******************************************************************************/ ++void init_isoch_packet_desc( isoch_packet_desc_t *init_isoch_packet_desc, ++ u32 isoch_packet_start_addr, ++ u32 isoch_packet_size, ++ u32 index) ++{ ++ ++ init_isoch_packet_desc[index].buf_size = isoch_packet_size; ++ init_isoch_packet_desc[index].isoch_packiet_start_addr = isoch_packet_start_addr; ++ init_isoch_packet_desc[index].isoch_status = 0; ++ init_isoch_packet_desc[index].transferred_szie = 0; ++ ++ ++} ++ ++/******************************************************************************/ ++/*! ++ * @name int create_ed(ed_t **new_ed) ++ * ++ * @brief this function creates a new ed_t and returns the ed_t to Caller ++ * ++ * ++ * @param [OUT] new_ed = returns the address of the new ed_t . ++ * ++ * @return USB_ERR_SUCCESS -if successes to create the new ed_t. ++ * USB_ERR_FAILl -if fails to create to new ed_t. ++ */ ++/******************************************************************************/ ++int create_ed(ed_t **new_ed) ++{ ++ int err_code = USB_ERR_SUCCESS; ++ ++ err_code = otg_mem_alloc((void **)new_ed,(u16)sizeof(ed_t), USB_MEM_SYNC); ++ otg_mem_set(*new_ed, 0, sizeof(ed_t)); ++ return err_code; ++} ++ ++ ++/******************************************************************************/ ++/*! ++ * @name int init_ed( ed_t *init_ed, ++ * u8 dev_addr, ++ * u8 ep_num, ++ * bool f_is_ep_in, ++ * u8 dev_speed, ++ * u8 ep_type, ++ * u32 max_packet_size, ++ * u8 multi_count, ++ * u8 interval, ++ * u32 sched_frame, ++ * u8 hub_addr, ++ * u8 hub_port, ++ * bool f_is_do_split) ++ * ++ * @brief this function initiates the init_ed by using the another parameters. ++ * ++ * ++ * @param [OUT] init_ed = returns the ed_t to be initiated. ++ * [IN] dev_addr = inidcates the address of USB Device. ++ * [IN] ep_num = inidcates the number of the specific endpoint on USB Device. ++ * [IN] f_is_ep_in = inidcates whether the endpoint is IN or not ++ * [IN] dev_speed = inidcates the speed of USB Device. ++ * [IN] max_packet_size = inidcates the maximum packet size of a specific endpoint on USB Device. ++ * [IN] multi_count = if the endpoint supports periodic transfer ++ * , this indicates the multiple packet to be transferred on a uframe ++ * [IN] interval= if the endpoint support periodic transfer, this indicates the polling rate. ++ * [IN] sched_frame= if the endpoint supports periodic transfer, this indicates the start frame number. ++ * [IN] hub_addr= indicate the address of hub which the USB device attachs to. ++ * [IN] hub_port= inidcates the port number of the hub which the USB device attachs to. ++ * [IN] f_is_do_split= inidcates whether this tranfer is split transaction or not. ++ * ++ * @return USB_ERR_SUCCESS -if successes to initiate the ed_t. ++ * USB_ERR_FAILl -if fails to initiate the ed_t. ++ * USB_ERR_NOSPACE -if fails to initiate the ed_t ++ * because there is no USB Resource for this init_ed. ++ */ ++/******************************************************************************/ ++int init_ed(ed_t *init_ed, ++ u8 dev_addr, ++ u8 ep_num, ++ bool f_is_ep_in, ++ u8 dev_speed, ++ u8 ep_type, ++ u16 max_packet_size, ++ u8 multi_count, ++ u8 interval, ++ u32 sched_frame, ++ u8 hub_addr, ++ u8 hub_port, ++ bool f_is_do_split, ++ void *ep) ++{ ++ init_ed->is_halted = false; ++ init_ed->is_need_to_insert_scheduler= true; ++ init_ed->ed_id = (u32)init_ed; ++ init_ed->num_td = 0; ++ init_ed->ed_private = ep; ++ ++ otg_list_init(&init_ed->td_list_entry); ++ ++ //start to initiate struct ed_desc.... ++ init_ed->ed_desc.is_do_split = f_is_do_split; ++ init_ed->ed_desc.is_ep_in = f_is_ep_in; ++ init_ed->ed_desc.dev_speed = dev_speed; ++ init_ed->ed_desc.hub_addr = hub_addr; ++ init_ed->ed_desc.hub_port = hub_port; ++ init_ed->ed_desc.mc = multi_count; ++ init_ed->ed_desc.device_addr = dev_addr; ++ init_ed->ed_desc.endpoint_num = ep_num; ++ init_ed->ed_desc.endpoint_type = ep_type; ++ init_ed->ed_desc.max_packet_size = max_packet_size; ++ init_ed->ed_desc.sched_frame = sched_frame; ++ ++ if(init_ed->ed_desc.endpoint_type == INT_TRANSFER) ++ { ++ if(init_ed->ed_desc.dev_speed == LOW_SPEED_OTG ||init_ed->ed_desc.dev_speed == FULL_SPEED_OTG) ++ { ++ init_ed->ed_desc.interval =interval; ++ } ++ else if(init_ed->ed_desc.dev_speed == HIGH_SPEED_OTG) ++ { ++ u8 count = 0; ++ u8 cal_interval = 1; ++ ++ for(count = 0;count<(init_ed->ed_desc.interval-1);count++) ++ { ++ cal_interval *=2; ++ } ++ ++ init_ed->ed_desc.interval =cal_interval; ++ } ++ else ++ { ++ otg_dbg(OTG_DBG_TRANSFER,"Super-Speed is not supported\n"); ++ } ++ init_ed->ed_desc.sched_frame = (SCHEDULE_SLOT+oci_get_frame_num())&HFNUM_MAX_FRNUM; ++ ref_periodic_transfer++; ++ } ++ if(init_ed->ed_desc.endpoint_type==ISOCH_TRANSFER) ++ { ++ u8 count = 0; ++ u8 cal_interval = 1; ++ ++ for(count = 0;count<(init_ed->ed_desc.interval-1);count++) ++ { ++ cal_interval *=2; ++ } ++ ++ init_ed->ed_desc.interval = cal_interval; ++ init_ed->ed_desc.sched_frame = (SCHEDULE_SLOT+oci_get_frame_num())&HFNUM_MAX_FRNUM; ++ ref_periodic_transfer++; ++ } ++ ++ //start to initiate struct ed_status.... ++ ++ //initiates PID ++ switch(ep_type) ++ { ++ case BULK_TRANSFER: ++ case INT_TRANSFER: ++ init_ed->ed_status.data_tgl = DATA0; ++ break; ++ ++ case CONTROL_TRANSFER: ++ init_ed->ed_status.control_data_tgl.setup_tgl = SETUP; ++ init_ed->ed_status.control_data_tgl.data_tgl = DATA1; ++ init_ed->ed_status.control_data_tgl.status_tgl = DATA1; ++ break; ++ ++ case ISOCH_TRANSFER: ++ if(f_is_ep_in) ++ { ++ switch(multi_count) ++ { ++ case MULTI_COUNT_ZERO : ++ init_ed->ed_status.data_tgl = DATA0; ++ break; ++ case MULTI_COUNT_ONE : ++ init_ed->ed_status.data_tgl = DATA1; ++ break; ++ case MULTI_COUNT_TWO : ++ init_ed->ed_status.data_tgl = DATA2; ++ break; ++ default:break; ++ } ++ } ++ else ++ { ++ switch(multi_count) ++ { ++ case MULTI_COUNT_ZERO : ++ init_ed->ed_status.data_tgl = DATA0; ++ break; ++ case MULTI_COUNT_ONE : ++ init_ed->ed_status.data_tgl = MDATA; ++ break; ++ case MULTI_COUNT_TWO : ++ init_ed->ed_status.data_tgl = MDATA; ++ break; ++ default:break; ++ } ++ } ++ break; ++ default: ++ break; ++ ++ } ++ ++ if(init_ed->ed_desc.endpoint_type == INT_TRANSFER || ++ init_ed->ed_desc.endpoint_type == ISOCH_TRANSFER) ++ { ++ u32 usb_time = 0, byte_count = 0; ++ ++ //calculates the bytes to be transferred at one (uframe)frame. ++ byte_count = (init_ed->ed_desc.mc+1)*init_ed->ed_desc.max_packet_size; ++ ++ usb_time = (u32)otg_usbcore_get_calc_bustime(init_ed->ed_desc.dev_speed, ++ init_ed->ed_desc.is_ep_in, ++ (init_ed->ed_desc.endpoint_type==ISOCH_TRANSFER?true:false), ++ byte_count); ++ usb_time /= 1000; //convert nanosec unit to usec unit ++ ++ if(reserve_used_resource_for_periodic(usb_time, init_ed->ed_desc.dev_speed, init_ed->ed_desc.endpoint_type)!=USB_ERR_SUCCESS) ++ { ++ return USB_ERR_NOSPACE; ++ } ++ ++ init_ed->ed_status.is_alloc_resource_for_ed =true; ++ init_ed->ed_desc.used_bus_time =usb_time; ++ init_ed->ed_desc.mc =multi_count+1; ++ } ++ ++ init_ed->ed_status.is_in_transfer_ready_q =false; ++ init_ed->ed_status.is_in_transferring =false; ++ init_ed->ed_status.is_ping_enable =false; ++ init_ed->ed_status.in_transferring_td =0; ++ ++ //push the ed_t to ED_list. ++ otg_list_push_prev(&init_ed->ed_list_entry,&ed_list_head); ++ ++ if(ref_periodic_transfer) ++ { ++ enable_sof(); ++ } ++ return USB_ERR_SUCCESS; ++} ++ ++ ++/******************************************************************************/ ++/*! ++ * @name int create_td(td_t **new_td) ++ * ++ * @brief this function creates a new td_t and returns the td_t to Caller ++ * ++ * ++ * @param [OUT] new_td = returns the address of the new td_t . ++ * ++ * @return USB_ERR_SUCCESS -if successes to create the new td_t. ++ * USB_ERR_FAILl -if fails to create to new td_t. ++ */ ++/******************************************************************************/ ++int create_td(td_t **new_td) ++{ ++ int err_code = USB_ERR_SUCCESS; ++ ++ err_code = otg_mem_alloc((void **)new_td,(u16)sizeof(td_t), USB_MEM_SYNC); ++ otg_mem_set(*new_td, 0, sizeof(td_t)); ++ return err_code; ++} ++ ++ ++/******************************************************************************/ ++/*! ++ * @name int init_td( td_t *init_td, ++ * ed_t *parent_ed, ++ * void *call_back_fun, ++ * void *call_back_param, ++ * u32 transfer_flag, ++ * bool f_is_standard_dev_req, ++ * u32 phy_setup, ++ * u32 vir_setup, ++ * u32 vir_buf_addr, ++ * u32 phy_buf_addr, ++ * u32 buf_size, ++ * u32 isoch_start_frame, ++ * isoch_packet_desc_t *isoch_packet_desc, ++ * u32 isoch_packet_num, ++ * void *td_priv) ++ * ++ * @brief this function initiates the init_td by using another parameter. ++ * ++ * ++ * @param [IN] init_td - indicate the td_t to be initiated. ++ * [IN] parent_ed - indicate the ed_t to manage this init_td ++ * [IN] call_back_func - indicate the call-back function of application. ++ * [IN] call_back_param - indicate the parameter of the call-back function. ++ * [IN] transfer_flag - indicate the transfer flag. ++ * [IN] f_is_standard_dev_req - indicates the issue transfer request is USB Standard Request ++ * [IN] phy_setup - the physical address of buffer to store the USB Standard Request. ++ * [IN] vir_setup - the virtual address of buffer to store the USB Standard Request. ++ * [IN] vir_buf_addr - the virtual address of buffer to store the data to be transferred or received. ++ * [IN] phy_buf_addr - the physical address of buffer to store the data to be transferred or received. ++ * [IN] buf_size - indicates the buffer size. ++ * [IN] isoch_start_frame - if this usb transfer is isochronous transfer ++ * , this indicates the start frame to start the usb transfer. ++ * [IN] isoch_packet_desc - if the usb transfer is isochronous transfer ++ * , this indicates the structure to describe the isochronous transfer. ++ * [IN] isoch_packet_num - if the usb transfer is isochronous transfer ++ * , this indicates the number of packet to consist of the usb transfer. ++ * [IN] td_priv - indicate the private data to be delivered from usb core of linux. ++ * td_priv stores the urb of linux. ++ * ++ * @return USB_ERR_SUCCESS -if successes to initiate the new td_t. ++ * USB_ERR_FAILl -if fails to create to new td_t. ++ */ ++/******************************************************************************/ ++int init_td( td_t *init_td, ++ ed_t *parent_ed, ++ void *call_back_fun, ++ void *call_back_param, ++ u32 transfer_flag, ++ bool f_is_standard_dev_req, ++ u32 phy_setup, ++ u32 vir_setup, ++ u32 vir_buf_addr, ++ u32 phy_buf_addr, ++ u32 buf_size, ++ u32 isoch_start_frame, ++ isoch_packet_desc_t *isoch_packet_desc, ++ u32 isoch_packet_num, ++ void *td_priv) ++{ ++ if(f_is_standard_dev_req) ++ { ++ if((phy_buf_addr>0) && (buf_size>0)) ++ { ++ init_td->standard_dev_req_info.is_data_stage = true; ++ } ++ else ++ { ++ init_td->standard_dev_req_info.is_data_stage = false; ++ } ++ init_td->standard_dev_req_info.conrol_transfer_stage = SETUP_STAGE; ++ init_td->standard_dev_req_info.phy_standard_dev_req_addr = phy_setup; ++ init_td->standard_dev_req_info.vir_standard_dev_req_addr = vir_setup; ++ } ++ ++ init_td->call_back_func_p = call_back_fun; ++ init_td->call_back_func_param_p = call_back_param; ++ init_td->error_code = USB_ERR_SUCCESS; ++ init_td->is_standard_dev_req = f_is_standard_dev_req; ++ init_td->is_transfer_done = false; ++ init_td->is_transferring = false; ++ init_td->td_private = td_priv; ++ init_td->err_cnt = 0; ++ init_td->parent_ed_p = parent_ed; ++ init_td->phy_buf_addr = phy_buf_addr; ++ init_td->vir_buf_addr = vir_buf_addr; ++ init_td->buf_size = buf_size; ++ init_td->isoch_packet_desc_p = isoch_packet_desc; ++ init_td->isoch_packet_num = isoch_packet_num; ++ init_td->isoch_packet_index = 0; ++ init_td->isoch_packet_position = 0; ++ init_td->sched_frame = isoch_start_frame; ++ init_td->used_total_bus_time = parent_ed->ed_desc.used_bus_time; ++ init_td->td_id = (u32)init_td; ++ init_td->transfer_flag = transfer_flag; ++ init_td->transferred_szie = 0; ++ ++ switch(parent_ed->ed_desc.endpoint_type) ++ { ++ case CONTROL_TRANSFER: ++ init_nonperio_stransfer(true, init_td); ++ break; ++ ++ case BULK_TRANSFER: ++ init_nonperio_stransfer(false, init_td); ++ break; ++ ++ case INT_TRANSFER: ++ init_perio_stransfer(false, init_td); ++ break; ++ ++ case ISOCH_TRANSFER: ++ init_perio_stransfer(true, init_td); ++ break; ++ ++ default: ++ return USB_ERR_FAIL; ++ } ++ ++ //insert the td_t to parent_ed->td_list_entry. ++ otg_list_push_prev(&init_td->td_list_entry,&parent_ed->td_list_entry); ++ parent_ed->num_td++; ++ ++ return USB_ERR_SUCCESS; ++} ++ ++/******************************************************************************/ ++/*! ++ * @name int issue_transfer(ed_t *parent_ed, ++ * void *call_back_func, ++ * void *call_back_param, ++ * u32 transfer_flag, ++ * bool f_is_standard_dev_req, ++ * u32 setup_vir_addr, ++ * u32 setup_phy_addr, ++ * u32 vir_buf_addr, ++ * u32 phy_buf_addr, ++ * u32 buf_size, ++ * u32 start_frame, ++ * u32 isoch_packet_num, ++ * isoch_packet_desc_t *isoch_packet_desc, ++ * void *td_priv, ++ * unsigned int *return_td_addr) ++ * ++ * @brief this function start USB Transfer ++ * ++ * ++ * @param [IN] parent_ed - indicate the ed_t to manage this issue transfer. ++ * [IN] call_back_func - indicate the call-back function of application. ++ * [IN] call_back_param - indicate the parameter of the call-back function. ++ * [IN] transfer_flag - indicate the transfer flag. ++ * [IN] f_is_standard_dev_req - indicates the issue transfer request is USB Standard Request ++ * [IN] setup_vir_addr - the virtual address of buffer to store the USB Standard Request. ++ * [IN] setup_phy_addr - the physical address of buffer to store the USB Standard Request. ++ * [IN] vir_buf_addr - the virtual address of buffer to store the data to be transferred or received. ++ * [IN] phy_buf_addr - the physical address of buffer to store the data to be transferred or received. ++ * [IN] buf_size - indicates the buffer size. ++ * [IN] start_frame - if this usb transfer is isochronous transfer ++ * , this indicates the start frame to start the usb transfer. ++ * [IN] isoch_packet_num - if the usb transfer is isochronous transfer ++ * , this indicates the number of packet to consist of the usb transfer. ++ * [IN] isoch_packet_desc - if the usb transfer is isochronous transfer ++ * , this indicates the structure to describe the isochronous transfer. ++ * [IN] td_priv - indicate the private data to be delivered from usb core of linux. ++ * td_priv stores the urb of linux. ++ * [OUT] return_td_addr - indicates the variable address to store the new td_t for this transfer ++ * ++ * @return USB_ERR_SUCCESS -if successes to initiate the new td_t. ++ * USB_ERR_FAILl -if fails to create to new td_t. ++ */ ++/******************************************************************************/ ++int issue_transfer(ed_t *parent_ed, ++ void *call_back_func, ++ void *call_back_param, ++ u32 transfer_flag, ++ bool f_is_standard_dev_req, ++ u32 setup_vir_addr, ++ u32 setup_phy_addr, ++ u32 vir_buf_addr, ++ u32 phy_buf_addr, ++ u32 buf_size, ++ u32 start_frame, ++ u32 isoch_packet_num, ++ isoch_packet_desc_t *isoch_packet_desc, ++ void *td_priv, ++ unsigned int *return_td_addr) ++{ ++ td_t *new_td_p = NULL; ++ ++ int err = USB_ERR_SUCCESS; ++ if(create_td(&new_td_p)==USB_ERR_SUCCESS) ++ { ++ err = init_td( new_td_p, ++ parent_ed, ++ call_back_func, ++ call_back_param, ++ transfer_flag, ++ f_is_standard_dev_req, ++ setup_phy_addr, ++ setup_vir_addr, ++ vir_buf_addr, ++ phy_buf_addr, ++ buf_size, ++ start_frame, ++ isoch_packet_desc, ++ isoch_packet_num, ++ td_priv); ++ ++ if(err !=USB_ERR_SUCCESS) ++ { ++ return USB_ERR_NOMEM; ++ } ++ ++ if(parent_ed->is_need_to_insert_scheduler) ++ { ++ insert_ed_to_scheduler(parent_ed); ++ } ++ ++ *return_td_addr = (u32)new_td_p; ++ ++ return USB_ERR_SUCCESS; ++ } ++ else ++ { ++ return USB_ERR_NOMEM; ++ } ++} ++ ++/******************************************************************************/ ++/*! ++ * @name int cancel_transfer( ed_t *parent_ed, ++ * td_t *cancel_td) ++ * ++ * @brief this function cancels to transfer USB Transfer of cancel_td. ++ * this function firstly check whether this cancel_td is transferring or not ++ * if the cancel_td is transferring, the this function requests to cancel the USB Transfer ++ * to S3CScheduler. if the parent_ed is for Periodic Transfer, and ++ * there is not any td_t at parent_ed, then this function requests to release ++ * some usb resources for the ed_t to S3CScheduler. finally this function deletes the cancel_td. ++ * ++ * @param [IN] pUpdateTD = indicates the pointer ot the td_t to have STransfer to be updated. ++ * ++ * @return USB_ERR_SUCCESS - if success to update the STranfer of pUpdateTD. ++ * USB_ERR_FAIL - if fail to update the STranfer of pUpdateTD. ++ */ ++ /******************************************************************************/ ++int cancel_transfer(ed_t *parent_ed, ++ td_t *cancel_td) ++{ ++ int err = USB_ERR_DEQUEUED; ++ otg_list_head *tmp_list_p, *tmp_list2_p; ++ bool cond_found = false; ++ ++ ++ if(parent_ed == NULL || cancel_td == NULL) ++ { ++ otg_dbg(OTG_DBG_TRANSFER, "parent_ed == NULL || cancel_td == NULL\n"); ++ cancel_td->error_code = USB_ERR_NOELEMENT; ++ // otg_usbcore_giveback(cancel_td); ++ return cancel_td->error_code; ++ } ++ ++ otg_list_for_each_safe(tmp_list_p, tmp_list2_p, &parent_ed->td_list_entry) { ++ if(&cancel_td->td_list_entry == tmp_list_p) ++ { ++ cond_found = true; ++ break; ++ } ++ } ++ ++ if (cond_found != true) ++ { ++ otg_dbg(OTG_DBG_TRANSFER, "cond_found != true \n"); ++ cancel_td->error_code = USB_ERR_NOELEMENT; ++ // otg_usbcore_giveback(cancel_td); ++ return cancel_td->error_code; ++ } ++ ++ ++ if(cancel_td->is_transferring) ++ { ++ if(!parent_ed->ed_status.is_in_transfer_ready_q) ++ { ++ err = cancel_to_transfer_td(cancel_td); ++ ++ parent_ed->ed_status.in_transferring_td = 0; ++ ++ if(err != USB_ERR_SUCCESS) ++ { ++ otg_dbg(OTG_DBG_TRANSFER, "cancel_to_transfer_td \n"); ++ cancel_td->error_code = err; ++ // otg_usbcore_giveback(cancel_td); ++ goto ErrorStatus; ++ } ++ ++ otg_list_pop(&cancel_td->td_list_entry); ++ parent_ed->num_td--; ++ } ++ } ++ else ++ { ++ otg_list_pop(&cancel_td->td_list_entry); ++ parent_ed->num_td--; ++ ++ if(parent_ed->num_td==0) ++ { ++ remove_ed_from_scheduler(parent_ed); ++ } ++ } ++ ++ if(parent_ed->num_td) ++ { ++ parent_ed->is_need_to_insert_scheduler = true; ++ insert_ed_to_scheduler(parent_ed); ++ } ++ else ++ { ++ if(parent_ed->ed_desc.endpoint_type == INT_TRANSFER || ++ parent_ed->ed_desc.endpoint_type == ISOCH_TRANSFER) ++ { ++ //Release channel and usb bus resource for this ed_t. ++ //but, not release memory for this ed_t. ++ free_usb_resource_for_periodic(parent_ed->ed_desc.used_bus_time, ++ cancel_td->cur_stransfer.alloc_chnum, ++ cancel_td->parent_ed_p->ed_desc.endpoint_type); ++ ++ parent_ed->ed_status.is_alloc_resource_for_ed =false; ++ } ++ } ++ // the caller of this functions should call otg_usbcore_giveback(cancel_td); ++ cancel_td->error_code = USB_ERR_DEQUEUED; ++ //otg_usbcore_giveback(cancel_td); ++ delete_td(cancel_td); ++ ++ErrorStatus: ++ ++ return err; ++ ++ ++} ++ ++ ++/******************************************************************************/ ++/*! ++ * @name int cancel_all_td(ed_t *parent_ed) ++ * ++ * @brief this function cancels all Transfer which parent_ed manages. ++ * ++ * @param [IN] parent_ed = indicates the pointer ot the ed_t to manage TD_ts to be canceled. ++ * ++ * @return USB_ERR_SUCCESS - if success to cancel all TD_ts of pParentsED. ++ * USB_ERR_FAIL - if fail to cancel all TD_ts of pParentsED. ++ */ ++ /******************************************************************************/ ++int cancel_all_td(ed_t *parent_ed) ++{ ++ otg_list_head *cancel_td_list_entry; ++ td_t *cancel_td; ++ ++ otg_dbg(OTG_DBG_OTGHCDI_HCD, "cancel_all_td \n"); ++ do ++ { ++ cancel_td_list_entry = parent_ed->td_list_entry.next; ++ ++ cancel_td = otg_list_get_node(cancel_td_list_entry,td_t, td_list_entry); ++ ++ cancel_transfer(parent_ed, cancel_td); ++ } while(parent_ed->num_td); ++ ++ return USB_ERR_SUCCESS; ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transfer-nonperiodic.c linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transfer-nonperiodic.c +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transfer-nonperiodic.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transfer-nonperiodic.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,147 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : NonPeriodicTransfer.c ++ * [Description] : This source file implements the functions to be defined at NonPeriodicTransfer Module. ++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com } ++ * [Department] : System LSI Division/System SW Lab ++ * [Created Date]: 2008/06/07 ++ * [Revision History] ++ * (1) 2008/06/07 by Yang Soon Yeal { syatom.yang@samsung.com } ++ * - Created this file and implements some functions of NonPeriodicTransfer. ++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Optimizing for performance \n ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++ ++#include "s3c-otg-transfer-transfer.h" ++ ++/******************************************************************************/ ++/*! ++ * @name int init_nonperio_stransfer( bool f_is_standard_dev_req, ++ * td_t *parent_td) ++ * ++ * @brief this function initiates the parent_td->cur_stransfer for NonPeriodic Transfer and ++ * inserts this init_td_p to init_td_p->parent_ed_p. ++ * ++ * @param [IN] f_is_standard_dev_req = indicates whether this transfer is Control or not. ++ * [IN] parent_td = indicates the address of td_t to be initiated. ++ * ++ * @return USB_ERR_SUCCESS - if success to update the STranfer of pUpdateTD. ++ * USB_ERR_FAIL - if fail to update the STranfer of pUpdateTD. ++ */ ++ /******************************************************************************/ ++int init_nonperio_stransfer(bool f_is_standard_dev_req, ++ td_t *parent_td) ++{ ++ ++ ++ parent_td->cur_stransfer.ed_desc_p = &parent_td->parent_ed_p->ed_desc; ++ parent_td->cur_stransfer.ed_status_p = &parent_td->parent_ed_p->ed_status; ++ parent_td->cur_stransfer.alloc_chnum = CH_NONE; ++ parent_td->cur_stransfer.parent_td = (u32)parent_td; ++ parent_td->cur_stransfer.stransfer_id = (u32)&parent_td->cur_stransfer; ++ ++ otg_mem_set(&(parent_td->cur_stransfer.hc_reg), 0, sizeof(hc_reg_t)); ++ ++ parent_td->cur_stransfer.hc_reg.hc_int_msk.b.chhltd = 1; ++ ++ if(f_is_standard_dev_req) ++ { ++ parent_td->cur_stransfer.buf_size = USB_20_STAND_DEV_REQUEST_SIZE; ++ parent_td->cur_stransfer.start_phy_buf_addr = parent_td->standard_dev_req_info.phy_standard_dev_req_addr; ++ parent_td->cur_stransfer.start_vir_buf_addr = parent_td->standard_dev_req_info.vir_standard_dev_req_addr; ++ } ++ else ++ { ++ parent_td->cur_stransfer.buf_size = (parent_td->buf_size>MAX_CH_TRANSFER_SIZE) ++ ?MAX_CH_TRANSFER_SIZE ++ :parent_td->buf_size; ++ ++ parent_td->cur_stransfer.start_phy_buf_addr = parent_td->phy_buf_addr; ++ parent_td->cur_stransfer.start_vir_buf_addr = parent_td->vir_buf_addr; ++ } ++ ++ parent_td->cur_stransfer.packet_cnt = calc_packet_cnt(parent_td->cur_stransfer.buf_size ++ , parent_td->parent_ed_p->ed_desc.max_packet_size); ++ ++ return USB_ERR_SUCCESS; ++} ++ ++ ++/******************************************************************************/ ++/*! ++ * @name void update_nonperio_stransfer(td_t *parent_td) ++ * ++ * @brief this function updates the parent_td->cur_stransfer to be used by S3COCI. ++ * ++ * @param [IN/OUT]parent_td = indicates the pointer of td_t to store the STranser to be updated. ++ * ++ * @return USB_ERR_SUCCESS -if success to update the parent_td->cur_stransfer. ++ * USB_ERR_FAIL -if fail to update the parent_td->cur_stransfer. ++ */ ++ /******************************************************************************/ ++void update_nonperio_stransfer(td_t *parent_td) ++{ ++ switch(parent_td->parent_ed_p->ed_desc.endpoint_type) ++ { ++ case BULK_TRANSFER: ++ parent_td->cur_stransfer.start_phy_buf_addr = parent_td->phy_buf_addr+parent_td->transferred_szie; ++ parent_td->cur_stransfer.start_vir_buf_addr = parent_td->vir_buf_addr+parent_td->transferred_szie; ++ parent_td->cur_stransfer.buf_size = ((parent_td->buf_size - parent_td->transferred_szie)>MAX_CH_TRANSFER_SIZE) ++ ?MAX_CH_TRANSFER_SIZE ++ :parent_td->buf_size - parent_td->transferred_szie; ++ break; ++ ++ case CONTROL_TRANSFER: ++ if(parent_td->standard_dev_req_info.conrol_transfer_stage == SETUP_STAGE) ++ { ++ // but, this case will not be occured...... ++ parent_td->cur_stransfer.start_phy_buf_addr = parent_td->standard_dev_req_info.phy_standard_dev_req_addr; ++ parent_td->cur_stransfer.start_vir_buf_addr = parent_td->standard_dev_req_info.vir_standard_dev_req_addr; ++ parent_td->cur_stransfer.buf_size = 8; ++ } ++ else if(parent_td->standard_dev_req_info.conrol_transfer_stage == DATA_STAGE) ++ { ++ parent_td->cur_stransfer.start_phy_buf_addr = parent_td->phy_buf_addr+parent_td->transferred_szie; ++ parent_td->cur_stransfer.start_vir_buf_addr = parent_td->vir_buf_addr+parent_td->transferred_szie; ++ parent_td->cur_stransfer.buf_size = ((parent_td->buf_size - parent_td->transferred_szie)>MAX_CH_TRANSFER_SIZE) ++ ?MAX_CH_TRANSFER_SIZE ++ :parent_td->buf_size - parent_td->transferred_szie; ++ } ++ else ++ { ++ parent_td->cur_stransfer.start_phy_buf_addr = 0; ++ parent_td->cur_stransfer.start_vir_buf_addr = 0; ++ parent_td->cur_stransfer.buf_size = 0; ++ } ++ break; ++ ++ ++ default: ++ break; ++ } ++ ++ parent_td->cur_stransfer.packet_cnt = calc_packet_cnt(parent_td->cur_stransfer.buf_size, parent_td->parent_ed_p->ed_desc.max_packet_size); ++ ++} ++ ++ ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transfer-periodic.c linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transfer-periodic.c +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transfer-periodic.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transfer-periodic.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,131 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : NonPeriodicTransfer.c ++ * [Description] : This source file implements the functions to be defined at NonPeriodicTransfer Module. ++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com } ++ * [Department] : System LSI Division/System SW Lab ++ * [Created Date]: 2008/06/09 ++ * [Revision History] ++ * (1) 2008/06/09 by Yang Soon Yeal { syatom.yang@samsung.com } ++ * - Created this file and implements some functions of PeriodicTransfer. ++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Optimizing for performance \n ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#include "s3c-otg-transfer-transfer.h" ++ ++ ++/******************************************************************************/ ++/*! ++ * @name int init_perio_stransfer( bool f_is_isoch_transfer, ++ * td_t *parent_td) ++ * ++ * @brief this function initiates the parent_td->cur_stransfer for Periodic Transfer and ++ * inserts this init_td_p to init_td_p->parent_ed_p. ++ * ++ * @param [IN] f_is_isoch_transfer = indicates whether this transfer is Isochronous or not. ++ * [IN] parent_td = indicates the address of td_t to be initiated. ++ * ++ * @return USB_ERR_SUCCESS -if success to update the STranfer of pUpdateTD. ++ * USB_ERR_FAIL -if fail to update the STranfer of pUpdateTD. ++ */ ++ /******************************************************************************/ ++int init_perio_stransfer( bool f_is_isoch_transfer, ++ td_t *parent_td) ++{ ++ parent_td->cur_stransfer.ed_desc_p = &parent_td->parent_ed_p->ed_desc; ++ parent_td->cur_stransfer.ed_status_p = &parent_td->parent_ed_p->ed_status; ++ parent_td->cur_stransfer.alloc_chnum = CH_NONE; ++ parent_td->cur_stransfer.parent_td = (u32)parent_td; ++ parent_td->cur_stransfer.stransfer_id = (u32)&parent_td->cur_stransfer; ++ ++ otg_mem_set(&parent_td->cur_stransfer.hc_reg, 0, sizeof(hc_reg_t)); ++ ++ parent_td->cur_stransfer.hc_reg.hc_int_msk.b.chhltd = 1; ++ ++ if(f_is_isoch_transfer) ++ { ++ // initiates the STransfer usinb the IsochPacketDesc[0]. ++ parent_td->cur_stransfer.buf_size =parent_td->isoch_packet_desc_p[0].buf_size; ++ parent_td->cur_stransfer.start_phy_buf_addr =parent_td->phy_buf_addr + parent_td->isoch_packet_desc_p[0].isoch_packiet_start_addr; ++ parent_td->cur_stransfer.start_vir_buf_addr =parent_td->vir_buf_addr + parent_td->isoch_packet_desc_p[0].isoch_packiet_start_addr; ++ } ++ else ++ { ++ parent_td->cur_stransfer.buf_size =(parent_td->buf_size>MAX_CH_TRANSFER_SIZE) ++ ?MAX_CH_TRANSFER_SIZE ++ :parent_td->buf_size; ++ ++ parent_td->cur_stransfer.start_phy_buf_addr =parent_td->phy_buf_addr; ++ parent_td->cur_stransfer.start_vir_buf_addr =parent_td->vir_buf_addr; ++ } ++ ++ parent_td->cur_stransfer.packet_cnt = calc_packet_cnt(parent_td->cur_stransfer.buf_size, parent_td->parent_ed_p->ed_desc.max_packet_size); ++ ++ return USB_ERR_SUCCESS; ++} ++ ++ ++/******************************************************************************/ ++/*! ++ * @name void update_perio_stransfer(td_t *parent_td) ++ * ++ * @brief this function updates the parent_td->cur_stransfer to be used by S3COCI. ++ * the STransfer of parent_td is for Periodic Transfer. ++ * ++ * @param [IN/OUT]parent_td = indicates the pointer of td_t to store the STranser to be updated. ++ * ++ * @return USB_ERR_SUCCESS -if success to update the parent_td->cur_stransfer. ++ * USB_ERR_FAIL -if fail to update the parent_td->cur_stransfer. ++ */ ++ /******************************************************************************/ ++void update_perio_stransfer(td_t *parent_td) ++{ ++ ++ switch(parent_td->parent_ed_p->ed_desc.endpoint_type) ++ { ++ case INT_TRANSFER: ++ parent_td->cur_stransfer.start_phy_buf_addr =parent_td->phy_buf_addr+parent_td->transferred_szie; ++ parent_td->cur_stransfer.start_vir_buf_addr =parent_td->vir_buf_addr+parent_td->transferred_szie; ++ parent_td->cur_stransfer.buf_size =(parent_td->buf_size>MAX_CH_TRANSFER_SIZE) ++ ?MAX_CH_TRANSFER_SIZE ++ :parent_td->buf_size; ++ break; ++ ++ case ISOCH_TRANSFER: ++ parent_td->cur_stransfer.start_phy_buf_addr = parent_td->phy_buf_addr ++ +parent_td->isoch_packet_desc_p[parent_td->isoch_packet_index].isoch_packiet_start_addr ++ +parent_td->isoch_packet_position; ++ ++ parent_td->cur_stransfer.start_vir_buf_addr = parent_td->vir_buf_addr ++ +parent_td->isoch_packet_desc_p[parent_td->isoch_packet_index].isoch_packiet_start_addr ++ +parent_td->isoch_packet_position; ++ ++ parent_td->cur_stransfer.buf_size = (parent_td->isoch_packet_desc_p[parent_td->isoch_packet_index].buf_size - parent_td->isoch_packet_position)>MAX_CH_TRANSFER_SIZE ++ ?MAX_CH_TRANSFER_SIZE ++ :parent_td->isoch_packet_desc_p[parent_td->isoch_packet_index].buf_size - parent_td->isoch_packet_position; ++ ++ break; ++ ++ default: ++ break; ++ } ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transfer-transfer.h linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transfer-transfer.h +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transfer-transfer.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transfer-transfer.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,147 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : s3c-otg-transfer-transfer.h ++ * [Description] : The Header file defines the external and internal functions of Transfer. ++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com } ++ * [Department] : System LSI Division/System SW Lab ++ * [Created Date]: 2008/06/03 ++ * [Revision History] ++ * (1) 2008/06/03 by Yang Soon Yeal { syatom.yang@samsung.com } ++ * - Created this file and defines functions of Transfer ++ * -# Jul 15,2008 v1.2 by SeungSoo Yang (ss1.yang@samsung.com) \n ++ * : Optimizing for performance \n ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#ifndef _TRANSFER_H ++#define _TRANSFER_H ++ ++/* ++// ---------------------------------------------------------------------------- ++// Include files : None. ++// ---------------------------------------------------------------------------- ++*/ ++//#include "s3c-otg-common-const.h" ++#include "s3c-otg-common-errorcode.h" ++#include "s3c-otg-common-datastruct.h" ++#include "s3c-otg-hcdi-memory.h" ++#include "s3c-otg-hcdi-kal.h" ++#include "s3c-otg-hcdi-debug.h" ++ ++#include "s3c-otg-scheduler-scheduler.h" ++#include "s3c-otg-isr.h" ++ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++// the header pointer to indicate the ED_list to manage the ed_t to be created and initiated. ++extern otg_list_head ed_list_head; ++extern u32 ref_periodic_transfer; ++ ++ ++void init_transfer(void); ++void deinit_transfer(void); ++ ++int issue_transfer(ed_t *parent_ed, ++ void *call_back_func, ++ void *call_back_param, ++ u32 transfer_flag, ++ bool f_is_standard_dev_req, ++ u32 setup_vir_addr, ++ u32 setup_phy_addr, ++ u32 vir_buf_addr, ++ u32 phy_buf_addr, ++ u32 buf_size, ++ u32 start_frame, ++ u32 isoch_packet_num, ++ isoch_packet_desc_t *isoch_packet_desc, ++ void *td_priv, ++ unsigned int *return_td_addr); ++ ++int cancel_transfer(ed_t *parent_ed, ++ td_t *cancel_td); ++ ++int cancel_all_td(ed_t *parent_ed); ++ ++int create_ed(ed_t ** new_ed); ++ ++int init_ed(ed_t * init_ed, ++ u8 dev_addr, ++ u8 ep_num, ++ bool f_is_ep_in, ++ u8 dev_speed, ++ u8 ep_type, ++ u16 max_packet_size, ++ u8 multi_count, ++ u8 interval, ++ u32 sched_frame, ++ u8 hub_addr, ++ u8 hub_port, ++ bool f_is_do_split, ++ void *ep); ++ ++int delete_ed(ed_t *delete_ed); ++ ++int delete_td(td_t * delete_td); ++ ++int create_isoch_packet_desc( isoch_packet_desc_t **new_isoch_packet_desc, ++ u32 isoch_packet_num); ++ ++int delete_isoch_packet_desc( isoch_packet_desc_t *del_isoch_packet_desc, ++ u32 isoch_packet_num); ++ ++ ++void init_isoch_packet_desc( isoch_packet_desc_t *init_isoch_packet_desc, ++ u32 offset, ++ u32 isoch_packet_size, ++ u32 index); ++ ++// NonPeriodicTransfer.c implements. ++ ++int init_nonperio_stransfer(bool f_is_standard_dev_req, ++ td_t *parent_td); ++ ++void update_nonperio_stransfer(td_t *parent_td); ++ ++//PeriodicTransfer.c implements ++ ++int init_perio_stransfer( bool f_is_isoch_transfer, ++ td_t *parent_td); ++ ++void update_perio_stransfer(td_t *parent_td); ++ ++static inline u32 calc_packet_cnt(u32 data_size, u16 max_packet_size) ++{ ++ if(data_size != 0) ++ { ++ return (data_size%max_packet_size==0)?data_size/max_packet_size:data_size/max_packet_size+1; ++ } ++ return 1; ++} ++ ++#ifdef __cplusplus ++} ++#endif ++ ++ ++#endif ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-bulk.c linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-bulk.c +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-bulk.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-bulk.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,673 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : BulkTransferChecker.c ++ * [Description] : The Source file implements the external and internal functions of BulkTransferChecker. ++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com } ++ * [Department] : System LSI Division/System SW Lab ++ * [Created Date]: 2008/06/13 ++ * [Revision History] ++ * (1) 2008/06/18 by Yang Soon Yeal { syatom.yang@samsung.com } ++ * - Created this file and implements functions of BulkTransferChecker ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#include "s3c-otg-transferchecker-bulk.h" ++#include "s3c-otg-isr.h" ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_bulk_transfer(td_t *result_td, ++ hc_info_t *hc_reg_data) ++ ++ * ++ * @brief this function processes the result of the Bulk Transfer. ++ * firstly, this function checks the result of the Bulk Transfer. ++ * and according to the result, calls the sub-functions to process the result. ++ * ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t whose channel is interruped. ++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return RE_TRANSMIT -if need to retransmit the result_td. ++ * RE_SCHEDULE -if need to reschedule the result_td. ++ * DE_ALLOCATE -if USB Transfer is completed. ++ * NO_ACTION -if we don't need any action, ++ */ ++/******************************************************************************/ ++u8 process_bulk_transfer(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ hcintn_t hc_intr_info; ++ u8 return_val=0; ++ ++ //we just deal with the interrupts to be unmasked. ++ hc_intr_info.d32 = hc_reg_data->hc_int.d32 & result_td->cur_stransfer.hc_reg.hc_int_msk.d32; ++ ++ if(result_td->parent_ed_p->ed_desc.is_ep_in) ++ { ++ if(hc_intr_info.b.chhltd) ++ { ++ return_val = process_chhltd_on_bulk(result_td, hc_reg_data); ++ } ++ ++ else if (hc_intr_info.b.ack) ++ { ++ return_val =process_ack_on_bulk(result_td, hc_reg_data); ++ } ++ ++ else if (hc_intr_info.b.nak) ++ { ++ return_val =process_nak_on_bulk(result_td, hc_reg_data); ++ } ++ ++ else if (hc_intr_info.b.datatglerr) ++ { ++ return_val = process_datatgl_on_bulk(result_td,hc_reg_data); ++ } ++ } ++ else ++ { ++ if(hc_intr_info.b.chhltd) ++ { ++ return_val = process_chhltd_on_bulk(result_td, hc_reg_data); ++ ++ } ++ ++ else if(hc_intr_info.b.ack) ++ { ++ return_val =process_ack_on_bulk( result_td, hc_reg_data); ++ } ++ } ++ ++ return return_val; ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_chhltd_on_bulk(td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function processes Channel Halt event according to Synopsys OTG Spec. ++ * firstly, this function checks the reason of the Channel Halt, and according to the reason, ++ * calls the sub-functions to process the result. ++ * ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return RE_TRANSMIT -if need to retransmit the result_td. ++ * RE_SCHEDULE -if need to reschedule the result_td. ++ * DE_ALLOCATE -if USB Transfer is completed. ++ */ ++/******************************************************************************/ ++u8 process_chhltd_on_bulk(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ if(result_td->parent_ed_p->ed_desc.is_ep_in) ++ { ++ if(hc_reg_data->hc_int.b.xfercompl) ++ { ++ return process_xfercompl_on_bulk( result_td, hc_reg_data); ++ } ++ else if(hc_reg_data->hc_int.b.stall) ++ { ++ return process_stall_on_bulk(result_td, hc_reg_data); ++ } ++ else if(hc_reg_data->hc_int.b.bblerr) ++ { ++ return process_bblerr_on_bulk(result_td, hc_reg_data); ++ } ++ else if(hc_reg_data->hc_int.b.xacterr) ++ { ++ return process_xacterr_on_bulk(result_td, hc_reg_data); ++ } ++ else ++ { ++ //Occure Error State..... ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL); ++ ++ //Mask ack Interrupt.. ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ result_td->err_cnt++; ++ if(result_td->err_cnt == 3) ++ { ++ result_td->error_code = USB_ERR_STATUS_XACTERR; ++ result_td->err_cnt = 0; ++ return DE_ALLOCATE; ++ } ++ ++ return RE_TRANSMIT; ++ } ++ } ++ else ++ { ++ if(hc_reg_data->hc_int.b.xfercompl) ++ { ++ return process_xfercompl_on_bulk(result_td, hc_reg_data); ++ } ++ else if(hc_reg_data->hc_int.b.stall) ++ { ++ return process_stall_on_bulk(result_td, hc_reg_data); ++ } ++ else if(hc_reg_data->hc_int.b.xacterr) ++ { ++ return process_xacterr_on_bulk(result_td, hc_reg_data); ++ } ++ ++ else if(hc_reg_data->hc_int.b.nak) ++ { ++ return process_nak_on_bulk(result_td, hc_reg_data); ++ } ++ else if(hc_reg_data->hc_int.b.nyet) ++ { ++ return process_nyet_on_bulk(result_td, hc_reg_data); ++ } ++ else ++ { ++ //occur error state... ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL); ++ ++ //Mask ack Interrupt.. ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ result_td->err_cnt++; ++ if(result_td->err_cnt == 3) ++ { ++ result_td->error_code = USB_ERR_STATUS_XACTERR; ++ result_td->err_cnt = 0; ++ return DE_ALLOCATE; ++ } ++ ++ return RE_TRANSMIT; ++ } ++ ++ ++ ++ } ++ return USB_ERR_SUCCESS; ++ ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_xfercompl_on_bulk( td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with the xfercompl event according to Synopsys OTG Spec. ++ * the procedure of this function is as following ++ * 1. clears all bits of the channel' HCINT by using clear_ch_intr() of S3CIsr. ++ * 2. masks some bit of HCINTMSK ++ * 3. updates the result_td fields ++ * err_cnt/u8/standard_dev_req_info. ++ * 4. updates the result_td->parent_ed_p->ed_status. ++ * BulkDataTgl. ++ * 5. calculates the tranferred size by calling calc_transferred_size() on DATA_STAGE. ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return USB_ERR_SUCCESS ++ */ ++/******************************************************************************/ ++u8 process_xfercompl_on_bulk(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ u8 ret_val=0; ++ ++ result_td->err_cnt = 0; ++ ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL); ++ ++ //Mask ack Interrupt.. ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ result_td->parent_ed_p->ed_status.is_ping_enable =false; ++ ++ result_td->transferred_szie += calc_transferred_size(true,result_td, hc_reg_data); ++ ++ if(result_td->transferred_szie==result_td->buf_size) ++ {//at IN Transfer, short transfer is accepted. ++ result_td->error_code = USB_ERR_STATUS_COMPLETE; ++ ret_val = DE_ALLOCATE; ++ } ++ else ++ { ++ if(result_td->parent_ed_p->ed_desc.is_ep_in&& hc_reg_data->hc_size.b.xfersize) ++ { ++ if(result_td->transfer_flag&USB_TRANS_FLAG_NOT_SHORT) ++ { ++ result_td->error_code =USB_ERR_STATUS_SHORTREAD; ++ } ++ else ++ { ++ result_td->error_code =USB_ERR_STATUS_COMPLETE; ++ } ++ ret_val = DE_ALLOCATE; ++ } ++ else ++ { ++ ret_val = RE_SCHEDULE; ++ } ++ } ++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td); ++ ++ if(hc_reg_data->hc_int.b.nyet) ++ { ++ //at OUT Transfer, we must re-transmit. ++ if(result_td->parent_ed_p->ed_desc.is_ep_in==false) ++ { ++ ++ if(result_td->parent_ed_p->ed_desc.dev_speed == HIGH_SPEED_OTG) ++ { ++ result_td->parent_ed_p->ed_status.is_ping_enable = true; ++ } ++ else ++ { ++ result_td->parent_ed_p->ed_status.is_ping_enable = false; ++ } ++ } ++ } ++ ++ return ret_val; ++ ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_ahb_on_bulk(td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with theAHB Errorl event according to Synopsys OTG Spec. ++ * this function stop the channel to be executed ++ * TBD.... ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return USB_ERR_SUCCESS ++ */ ++/******************************************************************************/ ++u8 process_ahb_on_bulk(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ result_td->err_cnt =0; ++ result_td->error_code =USB_ERR_STATUS_AHBERR; ++ ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_AHBErr); ++ ++ //Mask ack Interrupt.. ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ // we just calculate the size of the transferred data on Data Stage of Bulk Transfer. ++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data); ++ result_td->parent_ed_p->ed_status.is_ping_enable = false; ++ ++ return DE_ALLOCATE; ++ ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_stall_on_bulk(td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with theStall event according to Synopsys OTG Spec. ++ * when Stall is occured at Bulk Transfer, we should reset the PID as DATA0 ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return DE_ALLOCATE ++ */ ++/******************************************************************************/ ++u8 process_stall_on_bulk( td_t * result_td, ++ hc_info_t * hc_reg_data) ++{ ++ result_td->err_cnt =0; ++ result_td->error_code =USB_ERR_STATUS_STALL; ++ ++ //this channel is stalled, So we don't process another interrupts. ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL); ++ ++ //Mask ack Interrupt.. ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ result_td->parent_ed_p->ed_status.is_ping_enable = false; ++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data); ++ ++ update_datatgl(DATA0, result_td); ++ ++ ++ return DE_ALLOCATE; ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_nak_on_bulk(td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with the nak event according to Synopsys OTG Spec. ++ * nak is occured at OUT/IN Transaction of Data/Status Stage, and is not occured at Setup Stage. ++ * If nak is occured at IN Transaction, this function processes this interrupt as following. ++ * 1. resets the result_td->err_cnt. ++ * 2. masks ack/nak/DaaTglErr bit of HCINTMSK. ++ * 3. clears the nak bit of HCINT ++ * 4. be careful, nak of IN Transaction don't require re-transmit. ++ * If nak is occured at OUT Transaction, this function processes this interrupt as following. ++ * 1. all procedures of IN Transaction are executed. ++ * 2. calculates the size of the transferred data. ++ * 3. if the speed of USB Device is High-Speed, sets the ping protocol. ++ * 4. update the Toggle ++ * at OUT Transaction, this function check whether the speed of USB Device is High-Speed or not. ++ * if USB Device is High-Speed, then ++ * this function sets the ping protocol. ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return RE_SCHEDULE -if the direction of the Transfer is OUT ++ * NO_ACTION -if the direction of the Transfer is IN ++ */ ++/******************************************************************************/ ++u8 process_nak_on_bulk(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ result_td->err_cnt = 0; ++ ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ ++ //at OUT Transfer, we must re-transmit. ++ if(result_td->parent_ed_p->ed_desc.is_ep_in==false) ++ { ++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data); ++ ++ if(result_td->parent_ed_p->ed_desc.dev_speed == HIGH_SPEED_OTG) ++ { ++ result_td->parent_ed_p->ed_status.is_ping_enable = true; ++ } ++ else ++ { ++ result_td->parent_ed_p->ed_status.is_ping_enable = false; ++ } ++ ++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td); ++ ++ return RE_TRANSMIT; ++ } ++ return NO_ACTION; ++ ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_ack_on_bulk(td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with the ack event according to Synopsys OTG Spec. ++ * ack of IN/OUT Transaction don't need any retransmit. ++ * this function just resets result_td->err_cnt and masks ack/nak/DataTgl of HCINTMSK. ++ * finally, this function clears ack bit of HCINT and ed_status.is_ping_enable. ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return USB_ERR_SUCCESS ++ */ ++/******************************************************************************/ ++u8 process_ack_on_bulk(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ result_td->err_cnt = 0; ++ ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ ++ result_td->parent_ed_p->ed_status.is_ping_enable = false; ++ ++ return NO_ACTION; ++ ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_nyet_on_bulk(td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with the nyet event according to Synopsys OTG Spec. ++ * nyet is only occured at OUT Transaction. ++ * If nyet is occured at OUT Transaction, this function processes this interrupt as following. ++ * 1. resets the result_td->err_cnt. ++ * 2. masks ack/nak/datatglerr bit of HCINTMSK. ++ * 3. clears the nyet bit of HCINT ++ * 4. calculates the size of the transferred data. ++ * 5. if the speed of USB Device is High-Speed, sets the ping protocol. ++ * 6. update the Data Toggle. ++ * 7. return RE_SCHEDULE to retransmit. ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return RE_SCHEDULE ++ */ ++/******************************************************************************/ ++u8 process_nyet_on_bulk(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ if(result_td->parent_ed_p->ed_desc.is_ep_in) ++ { ++ // Error State.... ++ return NO_ACTION; ++ } ++ ++ result_td->err_cnt = 0; ++ ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NYET); ++ ++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data); ++ ++ if(result_td->parent_ed_p->ed_desc.dev_speed == HIGH_SPEED_OTG) ++ { ++ result_td->parent_ed_p->ed_status.is_ping_enable = true; ++ } ++ else ++ { ++ result_td->parent_ed_p->ed_status.is_ping_enable = false; ++ } ++ ++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td); ++ ++ return RE_TRANSMIT; ++ ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_xacterr_on_bulk( td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with the xacterr event according to Synopsys OTG Spec. ++ * xacterr is occured at OUT/IN Transaction and we should retransmit the USB Transfer ++ * if the Error Counter is less than the RETRANSMIT_THRESHOLD. ++ * the reasons of xacterr is Timeout/CRC error/false EOP. ++ * the procedure to process xacterr is as following. ++ * 1. increses the result_td->err_cnt ++ * 2. check whether the result_td->err_cnt is equal to 3. ++ * 2. unmasks ack/nak/datatglerr bit of HCINTMSK. ++ * 3. clears the xacterr bit of HCINT ++ * 4. calculates the size of the transferred data. ++ * 5. if the speed of USB Device is High-Speed, sets the ping protocol. ++ * 6. update the Data Toggle. ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return RE_TRANSMIT -if the error count is less than 3 ++ * DE_ALLOCATE -if the error count is equal to 3 ++ */ ++/******************************************************************************/ ++u8 process_xacterr_on_bulk( td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ u8 ret_val = 0; ++ ++ if(result_td->err_cntcur_stransfer.hc_reg.hc_int_msk.d32 |= (CH_STATUS_ACK+CH_STATUS_NAK+CH_STATUS_DataTglErr); ++ ret_val = RE_TRANSMIT; ++ result_td->err_cnt++ ; ++ } ++ else ++ { ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ret_val = DE_ALLOCATE; ++ result_td->err_cnt = 0 ; ++ result_td->error_code = USB_ERR_STATUS_XACTERR; ++ } ++ ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data); ++ ++ if(result_td->parent_ed_p->ed_desc.is_ep_in==false) ++ { ++ if(result_td->parent_ed_p->ed_desc.dev_speed == HIGH_SPEED_OTG) ++ { ++ result_td->parent_ed_p->ed_status.is_ping_enable = true; ++ } ++ else ++ { ++ result_td->parent_ed_p->ed_status.is_ping_enable = false; ++ } ++ } ++ ++ ++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td); ++ ++ return ret_val; ++ ++} ++ ++/******************************************************************************/ ++/*! ++ * @name void process_bblerr_on_bulk(td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with the Babble event according to Synopsys OTG Spec. ++ * babble error is occured when the buffer to receive data to be transmit is overflow. ++ * So, babble error can be just occured at IN Transaction. ++ * when Babble Error is occured, we should stop the USB Transfer, and return the fact ++ * to Application. ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return DE_ALLOCATE ++ */ ++/******************************************************************************/ ++u8 process_bblerr_on_bulk(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ ++ if(!result_td->parent_ed_p->ed_desc.is_ep_in) ++ { ++ return NO_ACTION; ++ } ++ ++ result_td->err_cnt =0; ++ result_td->error_code =USB_ERR_STATUS_BBLERR; ++ ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL); ++ ++ //Mask ack Interrupt.. ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ result_td->parent_ed_p->ed_status.is_ping_enable =false; ++ result_td->transferred_szie += calc_transferred_size(false, result_td, hc_reg_data); ++ ++ return DE_ALLOCATE; ++ ++ ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_datatgl_on_bulk( td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with the datatglerr event according to Synopsys OTG Spec. ++ * the datatglerr event is occured at IN Transfer, and the channel is not halted. ++ * this function just resets result_td->err_cnt and masks ack/nak/DataTgl of HCINTMSK. ++ * finally, this function clears datatglerr bit of HCINT. ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return NO_ACTION ++ */ ++/******************************************************************************/ ++u8 process_datatgl_on_bulk(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ result_td->err_cnt = 0; ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ return NO_ACTION; ++ ++} ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-bulk.h linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-bulk.h +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-bulk.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-bulk.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,88 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : BulkTransferChecker.h ++ * [Description] : The Header file defines the external and internal functions of BulkTransferChecker ++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com } ++ * [Department] : System LSI Division/System SW Lab ++ * [Created Date]: 2008/06/18 ++ * [Revision History] ++ * (1) 2008/06/18 by Yang Soon Yeal { syatom.yang@samsung.com } ++ * - Created this file and defines functions of BulkTransferChecker ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#ifndef _BULK_TRANSFER_CHECKER_H ++#define _BULK_TRANSFER_CHECKER_H ++ ++/* ++// ---------------------------------------------------------------------------- ++// Include files : None. ++// ---------------------------------------------------------------------------- ++*/ ++//#include "s3c-otg-common-typedef.h" ++#include "s3c-otg-common-const.h" ++#include "s3c-otg-common-errorcode.h" ++#include "s3c-otg-common-datastruct.h" ++ ++ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++u8 process_bulk_transfer(td_t *raw_td, ++ hc_info_t *hc_reg_data); ++ ++u8 process_xfercompl_on_bulk(td_t *raw_td, ++ hc_info_t *hc_reg_data); ++ ++u8 process_chhltd_on_bulk(td_t *raw_td, ++ hc_info_t *hc_reg_data); ++ ++u8 process_ahb_on_bulk(td_t *raw_td, ++ hc_info_t *hc_reg_data); ++ ++u8 process_stall_on_bulk(td_t *raw_td, ++ hc_info_t *hc_reg_data); ++ ++u8 process_nak_on_bulk(td_t *raw_td, ++ hc_info_t *hc_reg_data); ++ ++u8 process_ack_on_bulk(td_t *raw_td, ++ hc_info_t *hc_reg_data); ++ ++u8 process_nyet_on_bulk(td_t *raw_td, ++ hc_info_t *hc_reg_data); ++ ++u8 process_xacterr_on_bulk(td_t *raw_td, ++ hc_info_t *hc_reg_data); ++ ++u8 process_bblerr_on_bulk(td_t *raw_td, ++ hc_info_t *hc_reg_data); ++ ++u8 process_datatgl_on_bulk(td_t *raw_td, ++ hc_info_t *hc_reg_data); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++ ++#endif ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-checker.h linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-checker.h +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-checker.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-checker.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,66 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : DoneTransferChecker.h ++ * [Description] : The Header file defines the external and internal functions of S3CDoneTransferChecker. ++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com } ++ * [Department] : System LSI Division/System SW Lab ++ * [Created Date]: 2008/06/12 ++ * [Revision History] ++ * (1) 2008/06/12 by Yang Soon Yeal { syatom.yang@samsung.com } ++ * - Created this file and defines functions of S3CDoneTransferChecker ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#ifndef _DONE_TRANSFER_CHECKER_H ++#define _DONE_TRANSFER_CHECKER_H ++ ++/* ++// ---------------------------------------------------------------------------- ++// Include files : None. ++// ---------------------------------------------------------------------------- ++*/ ++ ++//#include "s3c-otg-common-typedef.h" ++#include "s3c-otg-common-const.h" ++#include "s3c-otg-common-errorcode.h" ++#include "s3c-otg-common-datastruct.h" ++ ++#include "s3c-otg-hcdi-debug.h" ++ ++ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++ ++#endif ++ ++ ++ ++ ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-common.c linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-common.c +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-common.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-common.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,259 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : CommonTransferChecker.c ++ * [Description] : The Source file implements the external and internal functions of CommonTransferChecker. ++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com } ++ * [Department] : System LSI Division/System SW Lab ++ * [Created Date]: 2009/01/12 ++ * [Revision History] ++ * (1) 2008/06/12 by Yang Soon Yeal { syatom.yang@samsung.com } ++ * - Created this file and implements functions of CommonTransferChecker ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#include "s3c-otg-transferchecker-common.h" ++ ++ ++/******************************************************************************/ ++/*! ++ * @name int init_done_transfer_checker(void) ++ * ++ * @brief this function initiates S3CDoneTransferChecker Module. ++ * ++ * ++ * @param void ++ * ++ * @return void ++ */ ++/******************************************************************************/ ++//ss1 ++/*void init_done_transfer_checker(void) ++{ ++ return USB_ERR_SUCCESS; ++}*/ ++ ++/******************************************************************************/ ++/*! ++ * @name void do_transfer_checker(void) ++ * ++ * @brief this function processes the result of USB Transfer. So, do_transfer_checker fistly ++ * check which channel occurs OTG Interrupt and gets the status information of the channel. ++ * do_transfer_checker requests the information of td_t to S3CScheduler. ++ * To process the interrupt of the channel, do_transfer_checker calls the sub-modules of ++ * S3CDoneTransferChecker, for example, ControlTransferChecker, BulkTransferChecker. ++ * according to the process result of the channel interrupt, do_transfer_checker decides ++ * the USB Transfer will be done or retransmitted. ++ * ++ * ++ * @param void ++ * ++ * @return void ++ */ ++/*******************************************************************************/ ++void do_transfer_checker (void) ++{ ++ u32 hc_intr = 0; ++ u32 hc_intr_msk = 0; ++ u8 do_try_cnt = 0; ++ ++ hc_info_t ch_info; ++ u32 td_addr = 0; ++ td_t *done_td = {0}; ++ u8 proc_result = 0; ++ ++ //by ss1 ++ otg_mem_set((void *)&ch_info, 0, sizeof(hc_info_t)); ++ ++ // Get value of HAINT... ++ get_intr_ch(&hc_intr,&hc_intr_msk); ++ ++start_do_transfer_checker: ++ ++ while(do_try_cntcur_stransfer.alloc_chnum) { ++ do_try_cnt++; ++ goto start_do_transfer_checker; ++ } ++ ++ } else { ++ do_try_cnt++; ++ goto start_do_transfer_checker; ++ } ++ //Gets the informationof channel to be interrupted. ++ get_ch_info(&ch_info,do_try_cnt); ++ ++ switch(done_td->parent_ed_p->ed_desc.endpoint_type) ++ { ++ case CONTROL_TRANSFER: ++ proc_result = process_control_transfer(done_td, &ch_info); ++ break; ++ case BULK_TRANSFER: ++ proc_result = process_bulk_transfer(done_td, &ch_info); ++ break; ++ case INT_TRANSFER: ++ proc_result = process_intr_transfer(done_td, &ch_info); ++ break; ++ case ISOCH_TRANSFER: ++ // proc_result = ProcessIsochTransfer(done_td, &ch_info); ++ break; ++ default:break; ++ } ++ ++ if((proc_result == RE_TRANSMIT) || (proc_result == RE_SCHEDULE)) ++ { ++ done_td->parent_ed_p->ed_status.is_in_transferring = false; ++ done_td->is_transfer_done = false; ++ done_td->is_transferring = false; ++ ++ if(done_td->parent_ed_p->ed_desc.endpoint_type == CONTROL_TRANSFER || ++ done_td->parent_ed_p->ed_desc.endpoint_type==BULK_TRANSFER) ++ { ++ update_nonperio_stransfer(done_td); ++ } ++ else ++ { ++ update_perio_stransfer(done_td); ++ } ++ ++ if(proc_result == RE_TRANSMIT) ++ { ++ retransmit(done_td); ++ } ++ else ++ { ++ reschedule(done_td); ++ } ++ } ++ ++ else if(proc_result==DE_ALLOCATE) ++ { ++ done_td->parent_ed_p->ed_status.is_in_transferring = false; ++ done_td->parent_ed_p->ed_status.in_transferring_td = 0; ++ done_td->is_transfer_done = true; ++ done_td->is_transferring = false; ++ ++ otg_usbcore_giveback( done_td); ++ release_trans_resource(done_td); ++ } ++ ++ else ++ { //NO_ACTION.... ++ done_td->parent_ed_p->ed_status.is_in_transferring = true; ++ done_td->parent_ed_p->ed_status.in_transferring_td = (u32)done_td; ++ done_td->is_transfer_done = false; ++ done_td->is_transferring = true; ++ } ++ do_try_cnt++; ++ } ++ // Complete to process the Channel Interrupt. ++ // So. we now start to scheduler of S3CScheduler. ++ do_schedule(); ++ ++} ++ ++ ++int release_trans_resource(td_t * done_td) ++{ ++ //remove the pDeallocateTD from parent_ed_p. ++ otg_list_pop(&done_td->td_list_entry); ++ done_td->parent_ed_p->num_td--; ++ ++ //Call deallocate to release the channel and bandwidth resource of S3CScheduler. ++ deallocate(done_td); ++ delete_td(done_td); ++ return USB_ERR_SUCCESS; ++} ++ ++u32 calc_transferred_size(bool f_is_complete, ++ td_t *td, ++ hc_info_t *hc_info) ++{ ++ if(f_is_complete) ++ { ++ if(td->parent_ed_p->ed_desc.is_ep_in) ++ { ++ return td->cur_stransfer.buf_size - hc_info->hc_size.b.xfersize; ++ } ++ else ++ { ++ return td->cur_stransfer.buf_size; ++ } ++ } ++ else ++ { ++ return (td->cur_stransfer.packet_cnt - hc_info->hc_size.b.pktcnt)*td->parent_ed_p->ed_desc.max_packet_size; ++ } ++ ++} ++ ++void update_frame_number(td_t *pResultTD) ++{ ++ u32 cur_frame_num=0; ++ ++ if(pResultTD->parent_ed_p->ed_desc.endpoint_type == CONTROL_TRANSFER || ++ pResultTD->parent_ed_p->ed_desc.endpoint_type == BULK_TRANSFER) ++ { ++ return; ++ } ++ ++ pResultTD->parent_ed_p->ed_desc.sched_frame+= pResultTD->parent_ed_p->ed_desc.interval; ++ pResultTD->parent_ed_p->ed_desc.sched_frame &= HFNUM_MAX_FRNUM; ++ ++ cur_frame_num = oci_get_frame_num(); ++ if(((cur_frame_num - pResultTD->parent_ed_p->ed_desc.sched_frame)&HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM>>1)) ++ { ++ pResultTD->parent_ed_p->ed_desc.sched_frame = cur_frame_num; ++ } ++} ++ ++void update_datatgl(u8 ubCurDataTgl, ++ td_t *td) ++{ ++ switch(td->parent_ed_p->ed_desc.endpoint_type) ++ { ++ case CONTROL_TRANSFER: ++ if(td->standard_dev_req_info.conrol_transfer_stage == DATA_STAGE) ++ { ++ td->parent_ed_p->ed_status.control_data_tgl.data_tgl = ubCurDataTgl; ++ } ++ break; ++ case BULK_TRANSFER: ++ case INT_TRANSFER: ++ td->parent_ed_p->ed_status.data_tgl =ubCurDataTgl; ++ break; ++ ++ case ISOCH_TRANSFER: ++ break; ++ default:break; ++ } ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-common.h linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-common.h +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-common.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-common.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,79 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : CommonTransferChecker.h ++ * [Description] : The Header file defines the external and internal functions of CommonTransferChecker. ++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com } ++ * [Department] : System LSI Division/System SW Lab ++ * [Created Date]: 2008/06/12 ++ * [Revision History] ++ * (1) 2008/06/12 by Yang Soon Yeal { syatom.yang@samsung.com } ++ * - Created this file and defines functions of CommonTransferChecker ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#ifndef _COMMON_TRANSFER_CHECKER_H ++#define _COMMON_TRANSFER_CHECKER_H ++ ++/* ++// ---------------------------------------------------------------------------- ++// Include files : None. ++// ---------------------------------------------------------------------------- ++*/ ++ ++#include "s3c-otg-common-common.h" ++//#include "s3c-otg-common-const.h" ++#include "s3c-otg-common-errorcode.h" ++#include "s3c-otg-common-datastruct.h" ++#include "s3c-otg-common-regdef.h" ++#include "s3c-otg-transfer-transfer.h" ++ ++#include "s3c-otg-hcdi-debug.h" ++#include "s3c-otg-hcdi-memory.h" ++#include "s3c-otg-scheduler-scheduler.h" ++#include "s3c-otg-isr.h" ++#include "s3c-otg-transferchecker-control.h" ++#include "s3c-otg-transferchecker-bulk.h" ++#include "s3c-otg-transferchecker-interrupt.h" ++//#include "s3c-otg-transferchecker-iso.h" ++ ++ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++//void init_done_transfer_checker (void); ++void do_transfer_checker (void); ++int release_trans_resource(td_t *done_td); ++u32 calc_transferred_size(bool f_is_complete, ++ td_t *td, ++ hc_info_t *hc_info); ++void update_frame_number(td_t *result_td); ++void update_datatgl(u8 cur_data_tgl, ++ td_t *td); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++ ++#endif ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-control.c linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-control.c +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-control.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-control.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,717 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : ControlTransferChecker.c ++ * [Description] : The Source file implements the external and internal functions of ControlTransferChecker. ++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com } ++ * [Department] : System LSI Division/System SW Lab ++ * [Created Date]: 2009/02/10 ++ * [Revision History] ++ * (1) 2008/06/13 by Yang Soon Yeal { syatom.yang@samsung.com } ++ * - Created this file and implements functions of ControlTransferChecker ++ * (2) 2008/06/18 by Yang Soon Yeal { syatom.yang@samsung.com } ++ * - Completed to implement ControlTransferChecker.c v1.0 ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#include "s3c-otg-transferchecker-control.h" ++#include "s3c-otg-isr.h" ++ ++ ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_control_transfer(td_t *result_td, ++ hc_info_t *hc_reg_data) ++ ++ * ++ * @brief this function processes the result of the Control Transfer. ++ * firstly, this function checks the result the Control Transfer. ++ * and according to the result, calls the sub-functions to process the result. ++ * ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] ubChNum -indicates the number of the channel to be interrupted. ++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return RE_TRANSMIT -if need to retransmit the result_td. ++ * RE_SCHEDULE -if need to reschedule the result_td. ++ * DE_ALLOCATE -if USB Transfer is completed. ++ */ ++/******************************************************************************/ ++u8 process_control_transfer(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ hcintn_t hcintr_info; ++ u8 ret_val=0; ++ ++ //we just deal with the interrupts to be unmasked. ++ hcintr_info.d32 = hc_reg_data->hc_int.d32&result_td->cur_stransfer.hc_reg.hc_int_msk.d32; ++ ++ if(result_td->parent_ed_p->ed_desc.is_ep_in) ++ { ++ if(hcintr_info.b.chhltd) ++ { ++ ret_val = process_chhltd_on_control(result_td, hc_reg_data); ++ } ++ ++ else if (hcintr_info.b.ack) ++ { ++ ret_val =process_ack_on_control(result_td, hc_reg_data); ++ } ++ ++ else if (hcintr_info.b.nak) ++ { ++ ret_val =process_nak_on_control(result_td, hc_reg_data); ++ } ++ ++ else if (hcintr_info.b.datatglerr) ++ { ++ ret_val = process_datatgl_on_control(result_td,hc_reg_data); ++ } ++ } ++ else ++ { ++ if(hcintr_info.b.chhltd) ++ { ++ ret_val = process_chhltd_on_control(result_td, hc_reg_data); ++ } ++ ++ else if(hcintr_info.b.ack) ++ { ++ ret_val =process_ack_on_control( result_td, hc_reg_data); ++ ++ } ++ } ++ ++ return ret_val; ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_chhltd_on_control( td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function processes Channel Halt event according to Synopsys OTG Spec. ++ * firstly, this function checks the reason of the Channel Halt, and according to the reason, ++ * calls the sub-functions to process the result. ++ * ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return RE_TRANSMIT -if need to retransmit the result_td. ++ * RE_SCHEDULE -if need to reschedule the result_td. ++ * DE_ALLOCATE -if USB Transfer is completed. ++ */ ++/******************************************************************************/ ++u8 process_chhltd_on_control( td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ if(hc_reg_data->hc_int.b.xfercompl) ++ { ++ return process_xfercompl_on_control( result_td, hc_reg_data); ++ } ++ else if(hc_reg_data->hc_int.b.stall) ++ { ++ return process_stall_on_control(result_td, hc_reg_data); ++ } ++ else if(hc_reg_data->hc_int.b.bblerr) ++ { ++ return process_bblerr_on_control(result_td, hc_reg_data); ++ } ++ else if(hc_reg_data->hc_int.b.xacterr) ++ { ++ return process_xacterr_on_control(result_td, hc_reg_data); ++ } ++ else if(hc_reg_data->hc_int.b.nak) ++ { ++ return process_nak_on_control(result_td, hc_reg_data); ++ } ++ else if(hc_reg_data->hc_int.b.nyet) ++ { ++ return process_nyet_on_control(result_td, hc_reg_data); ++ } ++ else ++ { ++ ++ //Occure Error State..... ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL); ++ ++ //Mask ack Interrupt.. ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ result_td->err_cnt++; ++ if(result_td->err_cnt == 3) ++ { ++ result_td->error_code = USB_ERR_STATUS_XACTERR; ++ result_td->err_cnt = 0; ++ return DE_ALLOCATE; ++ } ++ return RE_TRANSMIT; ++ } ++ return USB_ERR_SUCCESS; ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_xfercompl_on_control(td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with the xfercompl event according to Synopsys OTG Spec. ++ * the procedure of this function is as following ++ * 1. clears all bits of the channel' HCINT by using clear_ch_intr() of S3CIsr. ++ * 2. masks some bit of HCINTMSK ++ * 3. updates the result_td fields ++ * err_cnt/u8/standard_dev_req_info. ++ * 4. updates the result_td->parent_ed_p->ed_status. ++ * control_data_tgl. ++ * 5. calculates the tranferred size by calling calc_transferred_size() on DATA_STAGE. ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return USB_ERR_SUCCESS ++ */ ++/******************************************************************************/ ++u8 process_xfercompl_on_control(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ u8 ret_val = 0; ++ ++ result_td->err_cnt = 0; ++ ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum,CH_STATUS_ALL); ++ //Mask ack Interrupt.. ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ result_td->parent_ed_p->ed_status.is_ping_enable =false; ++ ++ switch(result_td->standard_dev_req_info.conrol_transfer_stage) ++ { ++ case SETUP_STAGE: ++ if(result_td->standard_dev_req_info.is_data_stage) ++ { ++ result_td->standard_dev_req_info.conrol_transfer_stage = DATA_STAGE; ++ } ++ else ++ { ++ result_td->standard_dev_req_info.conrol_transfer_stage = STATUS_STAGE; ++ } ++ ret_val = RE_TRANSMIT; ++ ++ break; ++ ++ case DATA_STAGE: ++ ++ result_td->transferred_szie += calc_transferred_size(true,result_td, hc_reg_data); ++ ++ if(result_td->transferred_szie==result_td->buf_size) ++ {//at IN Transfer, short transfer is accepted. ++ result_td->standard_dev_req_info.conrol_transfer_stage =STATUS_STAGE; ++ result_td->error_code = USB_ERR_STATUS_COMPLETE; ++ } ++ else ++ { ++ if(result_td->parent_ed_p->ed_desc.is_ep_in&& hc_reg_data->hc_size.b.xfersize) ++ { ++ if(result_td->transfer_flag&USB_TRANS_FLAG_NOT_SHORT) ++ { ++ result_td->error_code =USB_ERR_STATUS_SHORTREAD; ++ result_td->standard_dev_req_info.conrol_transfer_stage=STATUS_STAGE; ++ } ++ else ++ { ++ result_td->error_code =USB_ERR_STATUS_COMPLETE; ++ result_td->standard_dev_req_info.conrol_transfer_stage =STATUS_STAGE; ++ } ++ } ++ else ++ { // the Data Stage is not completed. So we need to continue Data Stage. ++ result_td->standard_dev_req_info.conrol_transfer_stage = DATA_STAGE; ++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td); ++ } ++ } ++ ++ if(hc_reg_data->hc_int.b.nyet) ++ { ++ //at OUT Transfer, we must re-transmit. ++ if(result_td->parent_ed_p->ed_desc.is_ep_in==false) ++ { ++ ++ if(result_td->parent_ed_p->ed_desc.dev_speed == HIGH_SPEED_OTG) ++ { ++ result_td->parent_ed_p->ed_status.is_ping_enable = true; ++ } ++ else ++ { ++ result_td->parent_ed_p->ed_status.is_ping_enable = false; ++ } ++ } ++ } ++ ret_val = RE_TRANSMIT; ++ break; ++ ++ case STATUS_STAGE: ++ result_td->standard_dev_req_info.conrol_transfer_stage = COMPLETE_STAGE; ++ ++ if(hc_reg_data->hc_int.b.nyet) ++ { ++ //at OUT Transfer, we must re-transmit. ++ if(result_td->parent_ed_p->ed_desc.is_ep_in==false) ++ { ++ ++ if(result_td->parent_ed_p->ed_desc.dev_speed == HIGH_SPEED_OTG) ++ { ++ result_td->parent_ed_p->ed_status.is_ping_enable = true; ++ } ++ else ++ { ++ result_td->parent_ed_p->ed_status.is_ping_enable = false; ++ } ++ } ++ } ++ ++ ret_val = DE_ALLOCATE; ++ break; ++ ++ default: ++ break; ++ } ++ ++ return ret_val; ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_ahb_on_control( td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with theAHB Errorl event according to Synopsys OTG Spec. ++ * this function stop the channel to be executed ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return DE_ALLOCATE ++ */ ++/******************************************************************************/ ++u8 process_ahb_on_control( td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ result_td->err_cnt =0; ++ result_td->error_code =USB_ERR_STATUS_AHBERR; ++ ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_AHBErr); ++ ++ //Mask ack Interrupt.. ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ // we just calculate the size of the transferred data on Data Stage of Control Transfer. ++ if(result_td->standard_dev_req_info.conrol_transfer_stage == DATA_STAGE) ++ { ++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data); ++ } ++ ++ return DE_ALLOCATE; ++ ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_stall_on_control( td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with theStall event according to Synopsys OTG Spec. ++ * but USB2.0 Spec don't permit the Stall on Setup Stage of Control Transfer. ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return DE_ALLOCATE ++ */ ++/******************************************************************************/ ++u8 process_stall_on_control( td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ result_td->err_cnt =0; ++ result_td->error_code =USB_ERR_STATUS_STALL; ++ ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL); ++ ++ //Mask ack Interrupt.. ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ result_td->parent_ed_p->ed_status.is_ping_enable = false; ++ ++ // we just calculate the size of the transferred data on Data Stage of Control Transfer. ++ if(result_td->standard_dev_req_info.conrol_transfer_stage == DATA_STAGE) ++ { ++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data); ++ } ++ ++ return DE_ALLOCATE; ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_nak_on_control( td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with the nak event according to Synopsys OTG Spec. ++ * nak is occured at OUT/IN Transaction of Data/Status Stage, and is not occured at Setup Stage. ++ * If nak is occured at IN Transaction, this function processes this interrupt as following. ++ * 1. resets the result_td->err_cnt. ++ * 2. masks ack/nak/DaaTglErr bit of HCINTMSK. ++ * 3. clears the nak bit of HCINT ++ * 4. be careful, nak of IN Transaction don't require re-transmit. ++ * If nak is occured at OUT Transaction, this function processes this interrupt as following. ++ * 1. all procedures of IN Transaction are executed. ++ * 2. calculates the size of the transferred data. ++ * 3. if the speed of USB Device is High-Speed, sets the ping protocol. ++ * 4. update the Toggle ++ * at OUT Transaction, this function check whether the speed of USB Device is High-Speed or not. ++ * if USB Device is High-Speed, then ++ * this function sets the ping protocol. ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return RE_SCHEDULE ++ */ ++/******************************************************************************/ ++u8 process_nak_on_control( td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ result_td->err_cnt = 0; ++ ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ ++ //at OUT Transfer, we must re-transmit. ++ if(result_td->parent_ed_p->ed_desc.is_ep_in==false) ++ { ++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data); ++ ++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td); ++ } ++ ++ if(result_td->parent_ed_p->ed_desc.dev_speed == HIGH_SPEED_OTG) ++ { ++ if(result_td->standard_dev_req_info.conrol_transfer_stage == DATA_STAGE) ++ { ++ if(result_td->parent_ed_p->ed_desc.is_ep_in==false) ++ { ++ result_td->parent_ed_p->ed_status.is_ping_enable = true; ++ } ++ } ++ else if(result_td->standard_dev_req_info.conrol_transfer_stage == STATUS_STAGE) ++ { ++ if(result_td->parent_ed_p->ed_desc.is_ep_in==true) ++ { ++ result_td->parent_ed_p->ed_status.is_ping_enable = true; ++ } ++ } ++ else ++ { ++ result_td->parent_ed_p->ed_status.is_ping_enable = false; ++ } ++ ++ } ++ ++ return RE_SCHEDULE; ++ ++ ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_ack_on_control( td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with the ack event according to Synopsys OTG Spec. ++ * ack of IN/OUT Transaction don't need any retransmit. ++ * this function just resets result_td->err_cnt and masks ack/nak/DataTgl of HCINTMSK. ++ * finally, this function clears ack bit of HCINT. ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return NO_ACTION ++ */ ++/******************************************************************************/ ++u8 process_ack_on_control(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ result_td->err_cnt = 0; ++ ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ ++ result_td->parent_ed_p->ed_status.is_ping_enable =false; ++ ++ return NO_ACTION; ++ ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_nyet_on_control(td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with the nyet event according to Synopsys OTG Spec. ++ * nyet is occured at OUT Transaction of Data/Status Stage, and is not occured at Setup Stage. ++ * If nyet is occured at OUT Transaction, this function processes this interrupt as following. ++ * 1. resets the result_td->err_cnt. ++ * 2. masks ack/nak/datatglerr bit of HCINTMSK. ++ * 3. clears the nyet bit of HCINT ++ * 4. calculates the size of the transferred data. ++ * 5. if the speed of USB Device is High-Speed, sets the ping protocol. ++ * 6. update the Data Toggle. ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return RE_SCHEDULE ++ */ ++/******************************************************************************/ ++u8 process_nyet_on_control(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ result_td->err_cnt = 0; ++ ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NYET); ++ ++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data); ++ ++ if(result_td->parent_ed_p->ed_desc.dev_speed == HIGH_SPEED_OTG) ++ { ++ if(result_td->standard_dev_req_info.conrol_transfer_stage == DATA_STAGE) ++ { ++ if(result_td->parent_ed_p->ed_desc.is_ep_in==false) ++ { ++ result_td->parent_ed_p->ed_status.is_ping_enable = true; ++ } ++ } ++ else if(result_td->standard_dev_req_info.conrol_transfer_stage == STATUS_STAGE) ++ { ++ if(result_td->parent_ed_p->ed_desc.is_ep_in==true) ++ { ++ result_td->parent_ed_p->ed_status.is_ping_enable = true; ++ } ++ } ++ else ++ { ++ result_td->parent_ed_p->ed_status.is_ping_enable = false; ++ } ++ ++ } ++ ++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td); ++ ++ return RE_SCHEDULE; ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_xacterr_on_control( td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with the xacterr event according to Synopsys OTG Spec. ++ * xacterr is occured at OUT/IN Transaction of Data/Status Stage, and is not occured at Setup Stage. ++ * if Timeout/CRC error/false EOP is occured, then xacterr is occured. ++ * the procedure to process xacterr is as following. ++ * 1. increses the result_td->err_cnt ++ * 2. check whether the result_td->err_cnt is equal to 3. ++ * 2. unmasks ack/nak/datatglerr bit of HCINTMSK. ++ * 3. clears the xacterr bit of HCINT ++ * 4. calculates the size of the transferred data. ++ * 5. if the speed of USB Device is High-Speed, sets the ping protocol. ++ * 6. update the Data Toggle. ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return RE_TRANSMIT -if the Error Counter is less than RETRANSMIT_THRESHOLD ++ * DE_ALLOCATE -if the Error Counter is equal to RETRANSMIT_THRESHOLD ++ */ ++/******************************************************************************/ ++u8 process_xacterr_on_control(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ u8 ret_val=0; ++ ++ if(result_td->err_cntcur_stransfer.hc_reg.hc_int_msk.d32 |= (CH_STATUS_ACK+CH_STATUS_NAK+CH_STATUS_DataTglErr); ++ ret_val = RE_TRANSMIT; ++ unmask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ unmask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ unmask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ result_td->err_cnt++ ; ++ } ++ else ++ { ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ret_val = DE_ALLOCATE; ++ result_td->err_cnt = 0 ; ++ result_td->error_code = USB_ERR_STATUS_XACTERR; ++ } ++ ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ if(result_td->standard_dev_req_info.conrol_transfer_stage == DATA_STAGE) ++ { ++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data); ++ ++ } ++ ++ if(result_td->parent_ed_p->ed_desc.dev_speed == HIGH_SPEED_OTG) ++ { ++ if(result_td->standard_dev_req_info.conrol_transfer_stage == DATA_STAGE) ++ { ++ if(result_td->parent_ed_p->ed_desc.is_ep_in==false) ++ { ++ result_td->parent_ed_p->ed_status.is_ping_enable = true; ++ } ++ } ++ else if(result_td->standard_dev_req_info.conrol_transfer_stage == STATUS_STAGE) ++ { ++ if(result_td->parent_ed_p->ed_desc.is_ep_in==true) ++ { ++ result_td->parent_ed_p->ed_status.is_ping_enable = true; ++ } ++ } ++ else ++ { ++ result_td->parent_ed_p->ed_status.is_ping_enable = false; ++ } ++ ++ ++ } ++ ++ ++ ++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td); ++ ++ return ret_val; ++ ++} ++ ++/******************************************************************************/ ++/*! ++ * @name void process_bblerr_on_control( td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with the Babble event according to Synopsys OTG Spec. ++ * babble error can be just occured at IN Transaction. So if the direction of transfer is ++ * OUT, this function return Error Code. ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return DE_ALLOCATE ++ * NO_ACTION -if the direction is OUT ++ */ ++/******************************************************************************/ ++u8 process_bblerr_on_control( td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ ++ if(!result_td->parent_ed_p->ed_desc.is_ep_in) ++ { ++ return NO_ACTION; ++ } ++ ++ result_td->err_cnt = 0; ++ result_td->error_code =USB_ERR_STATUS_BBLERR; ++ ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL); ++ ++ //Mask ack Interrupt.. ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ result_td->parent_ed_p->ed_status.is_ping_enable =false; ++ ++ // we just calculate the size of the transferred data on Data Stage of Control Transfer. ++ if(result_td->standard_dev_req_info.conrol_transfer_stage == DATA_STAGE) ++ { ++ result_td->transferred_szie += calc_transferred_size(false, result_td, hc_reg_data); ++ } ++ ++ return DE_ALLOCATE; ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_datatgl_on_control(td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with the datatglerr event according to Synopsys OTG Spec. ++ * the datatglerr event is occured at IN Transfer. ++ * this function just resets result_td->err_cnt and masks ack/nak/DataTgl of HCINTMSK. ++ * finally, this function clears datatglerr bit of HCINT. ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] hc_reg_data -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return NO_ACTION ++ */ ++/******************************************************************************/ ++u8 process_datatgl_on_control( td_t * result_td, ++ hc_info_t * hc_reg_data) ++{ ++ result_td->err_cnt = 0; ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ return NO_ACTION; ++ ++} ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-control.h linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-control.h +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-control.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-control.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,100 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : ControlTransferChecker.h ++ * [Description] : The Header file defines the external and internal functions of ControlTransferChecker ++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com } ++ * [Department] : System LSI Division/System SW Lab ++ * [Created Date]: 2009/01/12 ++ * [Revision History] ++ * (1) 2008/06/13 by Yang Soon Yeal { syatom.yang@samsung.com } ++ * - Created this file and defines functions of ControlTransferChecker ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#ifndef _CONTROL_TRANSFER_CHECKER_H ++#define _CONTROL_TRANSFER_CHECKER_H ++ ++/* ++// ---------------------------------------------------------------------------- ++// Include files : None. ++// ---------------------------------------------------------------------------- ++*/ ++ ++#include "s3c-otg-common-common.h" ++//#include "s3c-otg-common-typedef.h" ++#include "s3c-otg-common-const.h" ++#include "s3c-otg-common-errorcode.h" ++#include "s3c-otg-common-datastruct.h" ++#include "s3c-otg-common-regdef.h" ++ ++#include "s3c-otg-hcdi-debug.h" ++#include "s3c-otg-scheduler-scheduler.h" ++ ++#include "s3c-otg-transferchecker-checker.h" ++ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++u8 process_control_transfer( td_t *raw_td, ++ hc_info_t *hc_reg_data); ++ ++u8 process_xfercompl_on_control(td_t *raw_td, ++ hc_info_t *hc_reg_data); ++ ++u8 process_chhltd_on_control( td_t *raw_td, ++ hc_info_t *hc_reg_data); ++ ++u8 process_ahb_on_control( td_t *raw_td, ++ hc_info_t *hc_reg_data); ++ ++u8 process_stall_on_control( td_t *raw_td, ++ hc_info_t *hc_reg_data); ++ ++u8 process_nak_on_control (td_t *raw_td, ++ hc_info_t *hc_reg_data); ++ ++u8 process_ack_on_control (td_t *raw_td, ++ hc_info_t *hc_reg_data); ++ ++u8 process_nyet_on_control( td_t *raw_td, ++ hc_info_t *hc_reg_data); ++ ++u8 process_xacterr_on_control(td_t *raw_td, ++ hc_info_t *hc_reg_data); ++ ++u8 process_bblerr_on_control( td_t *raw_td, ++ hc_info_t *hc_reg_data); ++ ++u8 process_datatgl_on_control(td_t *raw_td, ++ hc_info_t *hc_reg_data); ++u8 process_indirection_on_control( td_t *result_td, ++ hc_info_t *hc_reg_data); ++ ++u8 process_outdirection_on_control(td_t *result_td, ++ hc_info_t *hc_reg_data); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++ ++#endif ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-interrupt.c linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-interrupt.c +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-interrupt.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-interrupt.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,582 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : IntTransferChecker.c ++ * [Description] : The Source file implements the external and internal functions of IntTransferChecker ++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com } ++ * [Department] : System LSI Division/System SW Lab ++ * [Created Date]: 2008/06/19 ++ * [Revision History] ++ * (1) 2008/06/18 by Yang Soon Yeal { syatom.yang@samsung.com } ++ * - Created this file and implements functions of IntTransferChecker ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++ ++#include "s3c-otg-transferchecker-interrupt.h" ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_intr_transfer(td_t *result_td, ++ * hc_info_t *HCRegData) ++ * ++ * ++ * @brief this function processes the result of the Interrupt Transfer. ++ * firstly, this function checks the result of the Interrupt Transfer. ++ * and according to the result, calls the sub-functions to process the result. ++ * ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t whose channel is interruped. ++ * [IN] HCRegData -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return RE_TRANSMIT -if need to retransmit the result_td. ++ * RE_SCHEDULE -if need to reschedule the result_td. ++ * DE_ALLOCATE -if USB Transfer is completed. ++ * NO_ACTION -if we don't need any action, ++ */ ++/******************************************************************************/ ++u8 process_intr_transfer(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ hcintn_t hc_intr_info; ++ u8 ret_val=0; ++ ++ //we just deal with the interrupts to be unmasked. ++ hc_intr_info.d32 = hc_reg_data->hc_int.d32&result_td->cur_stransfer.hc_reg.hc_int_msk.d32; ++ ++ if(result_td->parent_ed_p->ed_desc.is_ep_in) ++ { ++ if(hc_intr_info.b.chhltd) ++ { ++ ret_val = process_chhltd_on_intr(result_td, hc_reg_data); ++ } ++ ++ else if (hc_intr_info.b.ack) ++ { ++ ret_val =process_ack_on_intr(result_td, hc_reg_data); ++ } ++ } ++ else ++ { ++ if(hc_intr_info.b.chhltd) ++ { ++ ret_val = process_chhltd_on_intr(result_td, hc_reg_data); ++ ++ } ++ ++ else if(hc_intr_info.b.ack) ++ { ++ ret_val =process_ack_on_intr( result_td, hc_reg_data); ++ } ++ } ++ ++ return ret_val; ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_chhltd_on_intr(td_t *result_td, ++ * hc_info_t *HCRegData) ++ * ++ * ++ * @brief this function processes Channel Halt event according to Synopsys OTG Spec. ++ * firstly, this function checks the reason of the Channel Halt, and according to the reason, ++ * calls the sub-functions to process the result. ++ * ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] HCRegData -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return RE_TRANSMIT -if need to retransmit the result_td. ++ * RE_SCHEDULE -if need to reschedule the result_td. ++ * DE_ALLOCATE -if USB Transfer is completed. ++ */ ++/******************************************************************************/ ++u8 process_chhltd_on_intr(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ if(result_td->parent_ed_p->ed_desc.is_ep_in) ++ { ++ if(hc_reg_data->hc_int.b.xfercompl) ++ { ++ return process_xfercompl_on_intr( result_td, hc_reg_data); ++ } ++ else if(hc_reg_data->hc_int.b.stall) ++ { ++ return process_stall_on_intr(result_td, hc_reg_data); ++ } ++ else if(hc_reg_data->hc_int.b.bblerr) ++ { ++ return process_bblerr_on_intr(result_td, hc_reg_data); ++ } ++ else if (hc_reg_data->hc_int.b.nak) ++ { ++ return process_nak_on_intr(result_td, hc_reg_data); ++ } ++ else if(hc_reg_data->hc_int.b.datatglerr) ++ { ++ return process_datatgl_on_intr(result_td, hc_reg_data); ++ } ++ else if(hc_reg_data->hc_int.b.frmovrun) ++ { ++ return process_frmovrrun_on_intr(result_td,hc_reg_data); ++ } ++ else if(hc_reg_data->hc_int.b.xacterr) ++ { ++ return process_xacterr_on_intr(result_td, hc_reg_data); ++ } ++ else ++ { ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL); ++ ++ //Mask ack Interrupt.. ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ return RE_TRANSMIT; ++ } ++ } ++ else ++ { ++ if(hc_reg_data->hc_int.b.xfercompl) ++ { ++ return process_xfercompl_on_intr( result_td, hc_reg_data); ++ } ++ else if(hc_reg_data->hc_int.b.stall) ++ { ++ return process_stall_on_intr(result_td, hc_reg_data); ++ } ++ else if (hc_reg_data->hc_int.b.nak) ++ { ++ return process_nak_on_intr(result_td, hc_reg_data); ++ } ++ else if(hc_reg_data->hc_int.b.frmovrun) ++ { ++ return process_frmovrrun_on_intr(result_td,hc_reg_data); ++ } ++ else if(hc_reg_data->hc_int.b.xacterr) ++ { ++ return process_xacterr_on_intr(result_td, hc_reg_data); ++ } ++ else ++ { ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL); ++ ++ //Mask ack Interrupt.. ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ result_td->err_cnt++; ++ if(result_td->err_cnt == 3) ++ { ++ result_td->error_code = USB_ERR_STATUS_XACTERR; ++ result_td->err_cnt = 0; ++ return DE_ALLOCATE; ++ } ++ ++ return RE_TRANSMIT; ++ } ++ ++ } ++ ++ ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_xfercompl_on_intr( td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with the xfercompl event according to Synopsys OTG Spec. ++ * the procedure of this function is as following ++ * 1. clears all bits of the channel' HCINT by using clear_ch_intr() of S3CIsr. ++ * 2. masks ack/nak(?)/datatglerr(?) bit of HCINTMSK ++ * 3. Resets the err_cnt of result_td. ++ * 4. updates the result_td->parent_ed_p->ed_status. ++ * IntDataTgl. ++ * 5. calculates the tranferred size by calling calc_transferred_size() on DATA_STAGE. ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] HCRegData -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return DE_ALLOCATE -if USB Transfer is completed. ++ * RE_TRANSMIT -if need to retransmit the result_td. ++ */ ++/******************************************************************************/ ++u8 process_xfercompl_on_intr( td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ u8 ret_val=0; ++ ++ result_td->err_cnt =0; ++ ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL); ++ ++ //Mask ack Interrupt.. ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ result_td->transferred_szie += calc_transferred_size(true,result_td, hc_reg_data); ++ ++ if(result_td->transferred_szie==result_td->buf_size) ++ {//at IN Transfer, short transfer is accepted. ++ result_td->error_code = USB_ERR_STATUS_COMPLETE; ++ ret_val = DE_ALLOCATE; ++ } ++ else ++ { ++ // this routine will not be executed on Interrupt Transfer. ++ // So, we should decide to remove this routine or not. ++ if(result_td->parent_ed_p->ed_desc.is_ep_in&& hc_reg_data->hc_size.b.xfersize) ++ { ++ if(result_td->transfer_flag&USB_TRANS_FLAG_NOT_SHORT) ++ { ++ result_td->error_code = USB_ERR_STATUS_SHORTREAD; ++ } ++ else ++ { ++ result_td->error_code = USB_ERR_STATUS_COMPLETE; ++ } ++ ret_val = DE_ALLOCATE; ++ } ++ else ++ { // the Data Stage is not completed. So we need to continue Data Stage. ++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td); ++ ret_val = RE_TRANSMIT; ++ } ++ } ++ ++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td); ++ ++ return ret_val; ++ ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_ahb_on_intr(td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with theAHB Errorl event according to Synopsys OTG Spec. ++ * this function stop the channel to be executed ++ * ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] HCRegData -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return DE_ALLOCATE ++ */ ++/******************************************************************************/ ++u8 process_ahb_on_intr(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ result_td->err_cnt = 0; ++ result_td->error_code = USB_ERR_STATUS_AHBERR; ++ ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_AHBErr); ++ ++ //Mask ack Interrupt.. ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ // we just calculate the size of the transferred data on Data Stage of Int Transfer. ++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data); ++ result_td->parent_ed_p->ed_status.is_ping_enable =false; ++ ++ return DE_ALLOCATE; ++ ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_stall_on_intr(td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with the Stall event according to Synopsys OTG Spec. ++ * when Stall is occured at Int Transfer, we should reset the PID as DATA0 ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] HCRegData -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return DE_ALLOCATE ++ */ ++/******************************************************************************/ ++u8 process_stall_on_intr(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ result_td->err_cnt = 0; ++ result_td->error_code = USB_ERR_STATUS_STALL; ++ ++ //this channel is stalled, So we don't process another interrupts. ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL); ++ ++ //Mask ack Interrupt.. ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data); ++ ++ update_datatgl(DATA0, result_td); ++ ++ return DE_ALLOCATE; ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_nak_on_intr(td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with the nak event according to Synopsys OTG Spec. ++ * nak is occured at OUT/IN Transaction of Interrupt Transfer. ++ * we can't use ping protocol on Interrupt Transfer. and Syonopsys OTG IP occures ++ * chhltd interrupt on nak of IN/OUT Transaction. So we should retransmit the transfer ++ * on IN Transfer. ++ * If nak is occured at IN Transaction, this function processes this interrupt as following. ++ * 1. resets the result_td->err_cnt. ++ * 2. masks ack/nak/DaaTglErr bit of HCINTMSK. ++ * 3. clears the nak bit of HCINT ++ * 4. calculates frame number to retransmit this Interrupt Transfer. ++ * ++ * If nak is occured at OUT Transaction, this function processes this interrupt as following. ++ * 1. all procedures of IN Transaction are executed. ++ * 2. calculates the size of the transferred data. ++ * 3. if the speed of USB Device is High-Speed, sets the ping protocol. ++ * 4. update the Toggle ++ * at OUT Transaction, this function check whether the speed of USB Device is High-Speed or not. ++ * if USB Device is High-Speed, then ++ * this function sets the ping protocol. ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] HCRegData -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return RE_SCHEDULE -if the direction of the Transfer is OUT ++ * NO_ACTION -if the direction of the Transfer is IN ++ */ ++/******************************************************************************/ ++u8 process_nak_on_intr(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ result_td->err_cnt = 0; ++ ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ ++ ++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data); ++ ++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td); ++ ++ update_frame_number(result_td); ++ ++ return RE_SCHEDULE; ++// return RE_TRANSMIT; ++ ++ ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_ack_on_intr(td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with the ack event according to Synopsys OTG Spec. ++ * ack of IN/OUT Transaction don't need any retransmit. ++ * this function just resets result_td->err_cnt and masks ack/nak/DataTgl of HCINTMSK. ++ * finally, this function clears ack bit of HCINT and ed_status.is_ping_enable. ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] HCRegData -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return NO_ACTION ++ */ ++/******************************************************************************/ ++u8 process_ack_on_intr(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ result_td->err_cnt = 0; ++ ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ ++ return NO_ACTION; ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_xacterr_on_intr(td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * @brief this function deals with the xacterr event according to Synopsys OTG Spec. ++ * xacterr is occured at OUT/IN Transaction and we should retransmit the USB Transfer ++ * if the Error Counter is less than the RETRANSMIT_THRESHOLD. ++ * the reasons of xacterr is Timeout/CRC error/false EOP. ++ * the procedure to process xacterr is as following. ++ * 1. increses the result_td->err_cnt ++ * 2. check whether the result_td->err_cnt is equal to 3. ++ * 2. unmasks ack/nak/datatglerr bit of HCINTMSK. ++ * 3. clears the xacterr bit of HCINT ++ * 4. calculates the size of the transferred data. ++ * 5. update the Data Toggle. ++ * 6. update the frame number to start retransmitting the Interrupt Transfer. ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] HCRegData -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return RE_SCHEDULE -if the error count is less than 3 ++ * DE_ALLOCATE -if the error count is equal to 3 ++ */ ++/******************************************************************************/ ++u8 process_xacterr_on_intr(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ u8 ret_val = 0; ++ ++ if(result_td->err_cntcur_stransfer.hc_reg.hc_int_msk.d32 |=(CH_STATUS_ACK+CH_STATUS_NAK+CH_STATUS_DataTglErr); ++ ret_val = RE_SCHEDULE; ++ result_td->err_cnt++ ; ++ } ++ else ++ { ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ret_val = DE_ALLOCATE; ++ result_td->err_cnt = 0 ; ++ } ++ ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data); ++ ++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td); ++ ++ if(ret_val == RE_SCHEDULE) ++ { //Calculates the frame number ++ update_frame_number(result_td); ++ } ++ ++ return ret_val; ++} ++ ++/******************************************************************************/ ++/*! ++ * @name void process_bblerr_on_intr(td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * ++ * @brief this function deals with the Babble event according to Synopsys OTG Spec. ++ * babble error is occured when the USB device continues to send packets ++ * althrough EOP is occured. So Babble error is only occured at IN Transfer. ++ * when Babble Error is occured, we should stop the USB Transfer, and return the fact ++ * to Application. ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] HCRegData -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return DE_ALLOCATE ++ */ ++/******************************************************************************/ ++u8 process_bblerr_on_intr(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ ++ if(!result_td->parent_ed_p->ed_desc.is_ep_in) ++ { ++ return NO_ACTION; ++ } ++ ++ result_td->err_cnt = 0; ++ result_td->error_code =USB_ERR_STATUS_BBLERR; ++ ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ALL); ++ ++ //Mask ack Interrupt.. ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ result_td->transferred_szie += calc_transferred_size(false, result_td, hc_reg_data); ++ return DE_ALLOCATE; ++} ++ ++/******************************************************************************/ ++/*! ++ * @name u8 process_datatgl_on_intr( td_t *result_td, ++ * hc_info_t *hc_reg_data) ++ * ++ * @brief this function deals with the datatglerr event according to Synopsys OTG Spec. ++ * the datatglerr event is occured at IN Transfer, and the channel is not halted. ++ * this function just resets result_td->err_cnt and masks ack/nak/DataTgl of HCINTMSK. ++ * finally, this function clears datatglerr bit of HCINT. ++ * ++ * @param [IN] result_td -indicates the pointer of the td_t to be mapped with the uChNum. ++ * [IN] HCRegData -indicates the interrupt information of the Channel to be interrupted ++ * ++ * @return RE_SCHEDULE ++ */ ++/******************************************************************************/ ++u8 process_datatgl_on_intr(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ result_td->err_cnt = 0; ++ ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_ACK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ mask_channel_interrupt(result_td->cur_stransfer.alloc_chnum, CH_STATUS_DataTglErr); ++ ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ ++ result_td->transferred_szie += calc_transferred_size(false,result_td, hc_reg_data); ++ ++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td); ++ ++ update_frame_number(result_td); ++ ++ return RE_SCHEDULE; ++} ++ ++u8 process_frmovrrun_on_intr(td_t *result_td, ++ hc_info_t *hc_reg_data) ++{ ++ ++ clear_ch_intr(result_td->cur_stransfer.alloc_chnum, CH_STATUS_NAK); ++ ++ update_datatgl(hc_reg_data->hc_size.b.pid, result_td); ++ ++ update_frame_number(result_td); ++ ++ return RE_TRANSMIT; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-interrupt.h linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-interrupt.h +--- linux-2.6.28/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-interrupt.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/usb/host/s3c-otg/s3c-otg-transferchecker-interrupt.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,97 @@ ++/**************************************************************************** ++ * (C) Copyright 2008 Samsung Electronics Co., Ltd., All rights reserved ++ * ++ * [File Name] : IntTransferChecker.h ++ * [Description] : The Header file defines the external and internal functions of IntTransferChecker ++ * [Author] : Yang Soon Yeal { syatom.yang@samsung.com } ++ * [Department] : System LSI Division/System SW Lab ++ * [Created Date]: 2008/06/19 ++ * [Revision History] ++ * (1) 2008/06/18 by Yang Soon Yeal { syatom.yang@samsung.com } ++ * - Created this file and defines functions of IntTransferChecker ++ * ++ ****************************************************************************/ ++/**************************************************************************** ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ ****************************************************************************/ ++ ++#ifndef _INT_TRANSFER_CHECKER_H ++#define _INT_TRANSFER_CHECKER_H ++ ++/* ++// ---------------------------------------------------------------------------- ++// Include files : None. ++// ---------------------------------------------------------------------------- ++*/ ++ ++#include "s3c-otg-common-common.h" ++//#include "s3c-otg-common-typedef.h" ++#include "s3c-otg-common-const.h" ++#include "s3c-otg-common-errorcode.h" ++#include "s3c-otg-common-datastruct.h" ++#include "s3c-otg-common-regdef.h" ++ ++#include "s3c-otg-hcdi-debug.h" ++#include "s3c-otg-scheduler-scheduler.h" ++#include "s3c-otg-isr.h" ++#include "s3c-otg-transferchecker-checker.h" ++ ++ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++u8 process_intr_transfer(td_t *pRawTD, ++ hc_info_t *pHCRegData); ++ ++u8 process_xfercompl_on_intr(td_t *pRawTD, ++ hc_info_t *pHCRegData); ++ ++u8 process_chhltd_on_intr(td_t *pRawTD, ++ hc_info_t *pHCRegData); ++ ++u8 process_ahb_on_intr(td_t *pRawTD, ++ hc_info_t *pHCRegData); ++ ++u8 process_stall_on_intr(td_t *pRawTD, ++ hc_info_t *pHCRegData); ++ ++u8 process_nak_on_intr(td_t *pRawTD, ++ hc_info_t *pHCRegData); ++ ++u8 process_frmovrrun_on_intr(td_t *pRawTD, ++ hc_info_t *pHCRegData); ++ ++u8 process_ack_on_intr(td_t *pRawTD, ++ hc_info_t *pHCRegData); ++ ++u8 process_xacterr_on_intr(td_t *pRawTD, ++ hc_info_t *pHCRegData); ++ ++u8 process_bblerr_on_intr(td_t *pRawTD, ++ hc_info_t *pHCRegData); ++ ++u8 process_datatgl_on_intr(td_t *pRawTD, ++ hc_info_t *pHCRegData); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++ ++#endif ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/video/Kconfig linux-2.6.28.6/drivers/video/Kconfig +--- linux-2.6.28/drivers/video/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/video/Kconfig 2010-07-20 07:49:39.000000000 +0200 +@@ -237,6 +237,125 @@ + comment "Frame buffer hardware drivers" + depends on FB + ++config FB_S3C ++ tristate "S3C Framebuffer Support" ++ select FB_CFB_FILLRECT ++ select FB_CFB_COPYAREA ++ select FB_CFB_IMAGEBLIT ++ depends on FB && (ARCH_S3C64XX || ARCH_S5P64XX || ARCH_S5PC1XX) ++ ++ default n ++ ---help--- ++ TBA ++ ++choice ++depends on FB_S3C ++prompt "Select LCD Type" ++default FB_S3C_TFT480272 ++ ++config FB_S3C_TFT480272 ++ boolean "4.3 inch 480x272 TFT LCD" ++ ---help--- ++ 4.3 inch 480x272 TFT LCD ++ ++config FB_S3C_TFT800480 ++ boolean "7 inch 800x480 TFT LCD" ++ ---help--- ++ 7 inch 800x480 TFT LCD ++ ++config FB_S3C_T240320 ++ boolean "3.5 inch 240X320 Toppoly LCD" ++ help ++ 3.5 inch 240X320 Toppoly LCD ++ ++config FB_S3C_TFT640480 ++ boolean "8 inch 640X480 L80 LCD" ++ help ++ 8 inch 640X480 LCD ++ ++config FB_S3C_VGA1024768 ++ boolean "VGA 1024x768" ++ help ++ VGA 1024x768 ++ ++config FB_S3C_VGA800600 ++ boolean "VGA 800x600" ++ help ++ VGA 800x600 ++ ++config FB_S3C_VGA640480 ++ boolean "VGA 640x480" ++ help ++ VGA 640x480 ++ ++config FB_S3C_EZVGA800600 ++ boolean "EZVGA 800x600" ++ help ++ EZVGA 800x600 ++ ++endchoice ++ ++config FB_S3C_BPP ++ tristate "Advanced options for S3C Framebuffer" ++ depends on FB_S3C ++ default n ++ ---help--- ++ TBA ++ ++choice ++depends on FB_S3C_BPP ++prompt "Select BPP(Bits Per Pixel)" ++default FB_S3C_BPP_16 ++config FB_S3C_BPP_8 ++ bool "8 BPP" ++ ---help--- ++ TBA ++ ++config FB_S3C_BPP_16 ++ bool "16 BPP" ++ ---help--- ++ TBA ++ ++config FB_S3C_BPP_24 ++ bool "24 BPP(XRGB888)" ++ ---help--- ++ TBA ++ ++ ++config FB_S3C_BPP_28 ++ bool "28 BPP(ARGB4888)" ++ ---help--- ++ TBA ++ ++config FB_S3C_BPP_32 ++ bool "32 BPP(ARGB8888)" ++ ---help--- ++ TBA ++endchoice ++ ++config FB_S3C_NUM ++ int "Number of Framebuffers" ++ depends on FB_S3C_BPP && (ARCH_S3C64XX || ARCH_S5P64XX || ARCH_S5PC1XX) ++ default "1" ++ ---help--- ++ TBA ++ ++config FB_S3C_VIRTUAL_SCREEN ++ bool "Enable Virtual Screen" ++ depends on FB_S3C_BPP ++ ++ default n ++ ---help--- ++ TBA ++ ++config FB_S3C_DOUBLE_BUFFERING ++ bool "Enable Double Buffering" ++ depends on FB_S3C_BPP ++ ++ default n ++ ---help--- ++ TBA ++ + config FB_CIRRUS + tristate "Cirrus Logic support" + depends on FB && (ZORRO || PCI) +@@ -1941,6 +2060,12 @@ + Turn on debugging messages. Note that you can set/unset at run time + through sysfs + ++config BACKLIGHT_FRIENDLY_ARM ++ tristate "Backlight support for FriendlyARM board" ++ default y ++ help ++ backlight driver for FriendlyARM board ++ + config FB_SM501 + tristate "Silicon Motion SM501 framebuffer support" + depends on FB && MFD_SM501 +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/video/Makefile linux-2.6.28.6/drivers/video/Makefile +--- linux-2.6.28/drivers/video/Makefile 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/video/Makefile 2010-03-31 12:31:21.000000000 +0200 +@@ -110,6 +110,7 @@ + obj-$(CONFIG_FB_SH7760) += sh7760fb.o + obj-$(CONFIG_FB_IMX) += imxfb.o + obj-$(CONFIG_FB_S3C2410) += s3c2410fb.o ++obj-$(CONFIG_FB_S3C) += samsung/ + obj-$(CONFIG_FB_FSL_DIU) += fsl-diu-fb.o + obj-$(CONFIG_FB_COBALT) += cobalt_lcdfb.o + obj-$(CONFIG_FB_PNX4008_DUM) += pnx4008/ +@@ -138,3 +139,5 @@ + + #video output switch sysfs driver + obj-$(CONFIG_VIDEO_OUTPUT_CONTROL) += output.o ++ ++obj-$(CONFIG_BACKLIGHT_FRIENDLY_ARM) += mini6410_backlight.o +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/video/backlight/Kconfig linux-2.6.28.6/drivers/video/backlight/Kconfig +--- linux-2.6.28/drivers/video/backlight/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/video/backlight/Kconfig 2009-04-30 09:36:39.000000000 +0200 +@@ -178,7 +178,7 @@ + + config BACKLIGHT_PWM + tristate "Generic PWM based Backlight Driver" +- depends on BACKLIGHT_CLASS_DEVICE && HAVE_PWM ++ depends on BACKLIGHT_CLASS_DEVICE && (HAVE_PWM || TIMER_PWM) + help + If you have a LCD backlight adjustable by PWM, say Y to enable + this driver. +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/video/cfbimgblt.c linux-2.6.28.6/drivers/video/cfbimgblt.c +--- linux-2.6.28/drivers/video/cfbimgblt.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/video/cfbimgblt.c 2009-04-30 09:36:39.000000000 +0200 +@@ -80,7 +80,13 @@ + /* Draw the penguin */ + u32 __iomem *dst, *dst2; + u32 color = 0, val, shift; ++ ++#ifndef CONFIG_FB_S3C + int i, n, bpp = p->var.bits_per_pixel; ++#else ++ int i, n, bpp = p->fix.line_length / p->var.width * 8; ++#endif ++ + u32 null_bits = 32 - bpp; + u32 *palette = (u32 *) p->pseudo_palette; + const u8 *src = image->data; +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/video/logo/Kconfig linux-2.6.28.6/drivers/video/logo/Kconfig +--- linux-2.6.28/drivers/video/logo/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/video/logo/Kconfig 2009-04-30 09:36:39.000000000 +0200 +@@ -27,6 +27,11 @@ + bool "Standard 224-color Linux logo" + default y + ++config LOGO_LINUX_LANDSCAPED_CLUT224 ++ bool "Standard landscape 224-color Linux logo" ++ depends on LOGO ++ default y ++ + config LOGO_BLACKFIN_VGA16 + bool "16-colour Blackfin Processor Linux logo" + depends on BLACKFIN +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/video/logo/Makefile linux-2.6.28.6/drivers/video/logo/Makefile +--- linux-2.6.28/drivers/video/logo/Makefile 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/video/logo/Makefile 2009-04-30 09:36:39.000000000 +0200 +@@ -4,6 +4,7 @@ + obj-$(CONFIG_LOGO_LINUX_MONO) += logo_linux_mono.o + obj-$(CONFIG_LOGO_LINUX_VGA16) += logo_linux_vga16.o + obj-$(CONFIG_LOGO_LINUX_CLUT224) += logo_linux_clut224.o ++obj-$(CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224) += logo_linux_landscaped_clut224.o + obj-$(CONFIG_LOGO_BLACKFIN_CLUT224) += logo_blackfin_clut224.o + obj-$(CONFIG_LOGO_BLACKFIN_VGA16) += logo_blackfin_vga16.o + obj-$(CONFIG_LOGO_DEC_CLUT224) += logo_dec_clut224.o +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/video/logo/logo.c linux-2.6.28.6/drivers/video/logo/logo.c +--- linux-2.6.28/drivers/video/logo/logo.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/video/logo/logo.c 2009-04-30 09:36:39.000000000 +0200 +@@ -25,6 +25,7 @@ + extern const struct linux_logo logo_linux_vga16; + extern const struct linux_logo logo_linux_clut224; + extern const struct linux_logo logo_blackfin_vga16; ++extern const struct linux_logo logo_linux_landscaped_clut224; + extern const struct linux_logo logo_blackfin_clut224; + extern const struct linux_logo logo_dec_clut224; + extern const struct linux_logo logo_mac_clut224; +@@ -82,6 +83,9 @@ + /* Generic Linux logo */ + logo = &logo_linux_clut224; + #endif ++#ifdef CONFIG_LOGO_LINUX_LANDSCAPED_CLUT224 ++ logo = &logo_linux_landscaped_clut224; ++#endif + #ifdef CONFIG_LOGO_BLACKFIN_CLUT224 + /* Blackfin Linux logo */ + logo = &logo_blackfin_clut224; +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/video/mini6410_backlight.c linux-2.6.28.6/drivers/video/mini6410_backlight.c +--- linux-2.6.28/drivers/video/mini6410_backlight.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/video/mini6410_backlight.c 2010-03-31 12:58:00.000000000 +0200 +@@ -0,0 +1,129 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++#include ++ ++#undef DEBUG ++//#define DEBUG ++#ifdef DEBUG ++#define DPRINTK(x...) {printk(__FUNCTION__"(%d): ",__LINE__);printk(##x);} ++#else ++#define DPRINTK(x...) (void)(0) ++#endif ++ ++#define DEVICE_NAME "backlight" ++ ++ ++static unsigned int bl_state; ++ ++static inline void set_bl(int state) ++{ ++ bl_state = !!state; ++ //printk(DEVICE_NAME ": %s\n", state ? "ON" : "OFF"); ++ { ++ unsigned long tmp; ++ tmp = readl(S3C64XX_GPEDAT); ++ tmp = (tmp & ~0x1) | (!!state); ++ writel(tmp, S3C64XX_GPEDAT); ++ } ++} ++ ++static inline unsigned int get_bl(void) ++{ ++ return bl_state; ++} ++ ++static ssize_t dev_write(struct file *file, const char *buffer, size_t count, loff_t * ppos) ++{ ++ unsigned char ch; ++ int ret; ++ if (count == 0) { ++ return count; ++ } ++ ret = copy_from_user(&ch, buffer, sizeof ch) ? -EFAULT : 0; ++ if (ret) { ++ return ret; ++ } ++ ++ ch &= 0x01; ++ set_bl(ch); ++ ++ return count; ++} ++ ++static ssize_t dev_read(struct file *filp, char *buffer, size_t count, loff_t *ppos) ++{ ++ int ret; ++ unsigned char str[] = {'0', '1' }; ++ ++ if (count == 0) { ++ return 0; ++ } ++ ++ ret = copy_to_user(buffer, str + get_bl(), sizeof(unsigned char) ) ? -EFAULT : 0; ++ if (ret) { ++ return ret; ++ } ++ ++ return sizeof(unsigned char); ++} ++ ++static struct file_operations dev_fops = { ++ owner: THIS_MODULE, ++ read: dev_read, ++ write: dev_write, ++}; ++ ++static struct miscdevice misc = { ++ .minor = MISC_DYNAMIC_MINOR, ++ .name = DEVICE_NAME, ++ .fops = &dev_fops, ++}; ++ ++static int __init dev_init(void) ++{ ++ int ret; ++ ++ ret = misc_register(&misc); ++ ++ printk (DEVICE_NAME"\tinitialized\n"); ++ ++ { ++ unsigned long tmp; ++ tmp = readl(S3C64XX_GPECON); ++ tmp = (tmp & ~0xF) | 0x1; ++ writel(tmp, S3C64XX_GPECON); ++ } ++ set_bl(1); ++ return ret; ++} ++ ++ ++static void __exit dev_exit(void) ++{ ++ misc_deregister(&misc); ++} ++ ++module_init(dev_init); ++module_exit(dev_exit); ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("FriendlyARM Inc."); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/video/samsung/Makefile linux-2.6.28.6/drivers/video/samsung/Makefile +--- linux-2.6.28/drivers/video/samsung/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/video/samsung/Makefile 2010-07-20 07:47:51.000000000 +0200 +@@ -0,0 +1,17 @@ ++# ++# Makefile for the s3c framebuffer driver ++# ++ ++obj-$(CONFIG_FB_S3C) += s3cfb.o ++obj-$(CONFIG_FB_S3C) += s3cfb_spi.o ++obj-$(CONFIG_PLAT_S3C64XX) += s3cfb_fimd4x.o ++obj-$(CONFIG_PLAT_S5P64XX) += s3cfb_fimd5x.o ++obj-$(CONFIG_PLAT_S5PC1XX) += s3cfb_fimd5x.o ++obj-$(CONFIG_FB_S3C_TFT480272) += s3c_mini6410.o ++obj-$(CONFIG_FB_S3C_TFT800480) += s3c_mini6410.o ++obj-$(CONFIG_FB_S3C_T240320) += s3c_mini6410.o ++obj-$(CONFIG_FB_S3C_TFT640480) += s3c_mini6410.o ++obj-$(CONFIG_FB_S3C_VGA1024768) += s3c_mini6410.o ++obj-$(CONFIG_FB_S3C_VGA800600) += s3c_mini6410.o ++obj-$(CONFIG_FB_S3C_VGA640480) += s3c_mini6410.o ++obj-$(CONFIG_FB_S3C_EZVGA800600)+= s3c_mini6410.o +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/video/samsung/s3c_mini6410.c linux-2.6.28.6/drivers/video/samsung/s3c_mini6410.c +--- linux-2.6.28/drivers/video/samsung/s3c_mini6410.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/video/samsung/s3c_mini6410.c 2010-07-20 07:51:39.000000000 +0200 +@@ -0,0 +1,206 @@ ++/* ++ * drivers/video/s3c/s3cfb_mini6410.c ++ * ++ * based on s3cfb_lte480wv.c ++ * ++ * Copyright (C) 2008 Jinsung Yang ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive for ++ * more details. ++ * ++ * S3C Frame Buffer Driver ++ * based on skeletonfb.c, sa1100fb.h, s3c2410fb.c ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "s3cfb.h" ++#include ++ ++#if defined(CONFIG_FB_S3C_TFT480272) ++ ++#define S3CFB_VBP (1) /* back porch */ ++#define S3CFB_VFP (1) /* front porch */ ++#define S3CFB_VSW (1) /* vsync width */ ++#define S3CFB_HBP (0x02) /* back porch */ ++#define S3CFB_HFP (0x03) /* front porch */ ++#define S3CFB_HSW (0x28) /* hsync width */ ++ ++#define S3CFB_HRES 480 /* horizon pixel x resolition */ ++#define S3CFB_VRES 272 /* line cnt y resolution */ ++ ++#define S3CFB_CLKVAL 9 ++ ++#elif defined(CONFIG_FB_S3C_TFT800480) ++ ++#define S3CFB_VBP (0x02) /* back porch */ ++#define S3CFB_VFP (0x02) /* front porch */ ++#define S3CFB_VSW (0x04) /* vsync width */ ++#define S3CFB_HBP (0x02) /* back porch */ ++#define S3CFB_HFP (0x02) /* front porch */ ++#define S3CFB_HSW (0x29) /* hsync width */ ++ ++#define S3CFB_HRES 800 /* horizon pixel x resolition */ ++#define S3CFB_VRES 480 /* line cnt y resolution */ ++ ++#define S3CFB_CLKVAL 3 ++ ++#elif defined(CONFIG_FB_S3C_T240320) ++ ++#define S3CFB_VBP (0x01) /* back porch */ ++#define S3CFB_VFP (0x01) /* front porch */ ++#define S3CFB_VSW (0x04) /* vsync width */ ++#define S3CFB_HBP (0x01) /* back porch */ ++#define S3CFB_HFP (0x04) /* front porch */ ++#define S3CFB_HSW (0x1E) /* hsync width */ ++ ++#define S3CFB_HRES 240 /* horizon pixel x resolition */ ++#define S3CFB_VRES 320 /* line cnt y resolution */ ++ ++#define S3CFB_CLKVAL 11 ++ ++#elif defined(CONFIG_FB_S3C_TFT640480) ++ ++#define S3CFB_VBP (0x01) /* back porch */ ++#define S3CFB_VFP (0x01) /* front porch */ ++#define S3CFB_VSW (0x01) /* vsync width */ ++#define S3CFB_HBP (0x03) /* back porch */ ++#define S3CFB_HFP (0x03) /* front porch */ ++#define S3CFB_HSW (0x28) /* hsync width */ ++ ++#define S3CFB_HRES 640 /* horizon pixel x resolition */ ++#define S3CFB_VRES 480 /* line cnt y resolution */ ++ ++#define S3CFB_CLKVAL 3 ++ ++#elif defined(CONFIG_FB_S3C_VGA1024768) ++ ++#define S3CFB_VBP (0x02) /* back porch */ ++#define S3CFB_VFP (0x02) /* front porch */ ++#define S3CFB_VSW (0x10) /* vsync width */ ++#define S3CFB_HBP (0x02) /* back porch */ ++#define S3CFB_HFP (0x02) /* front porch */ ++#define S3CFB_HSW (0x2A) /* hsync width */ ++ ++#define S3CFB_HRES 1024 /* horizon pixel x resolition */ ++#define S3CFB_VRES 768 /* line cnt y resolution */ ++ ++#define S3CFB_CLKVAL 5 ++ ++#elif defined(CONFIG_FB_S3C_VGA800600) ++ ++#define S3CFB_VBP (0x02) /* back porch */ ++#define S3CFB_VFP (0x02) /* front porch */ ++#define S3CFB_VSW (0x10) /* vsync width */ ++#define S3CFB_HBP (0x02) /* back porch */ ++#define S3CFB_HFP (0x02) /* front porch */ ++#define S3CFB_HSW (0x2A) /* hsync width */ ++ ++#define S3CFB_HRES 800 /* horizon pixel x resolition */ ++#define S3CFB_VRES 600 /* line cnt y resolution */ ++ ++#define S3CFB_CLKVAL 5 ++ ++#elif defined(CONFIG_FB_S3C_VGA640480) ++ ++#define S3CFB_VBP (0x02) /* back porch */ ++#define S3CFB_VFP (0x02) /* front porch */ ++#define S3CFB_VSW (0x10) /* vsync width */ ++#define S3CFB_HBP (0x02) /* back porch */ ++#define S3CFB_HFP (0x02) /* front porch */ ++#define S3CFB_HSW (0x2A) /* hsync width */ ++ ++#define S3CFB_HRES 640 /* horizon pixel x resolition */ ++#define S3CFB_VRES 480 /* line cnt y resolution */ ++ ++#define S3CFB_CLKVAL 5 ++ ++#elif defined(CONFIG_FB_S3C_EZVGA800600) ++ ++#define S3CFB_VBP (0x02) /* back porch */ ++#define S3CFB_VFP (0x02) /* front porch */ ++#define S3CFB_VSW (0x10) /* vsync width */ ++#define S3CFB_HBP (0xA8) /* back porch */ ++#define S3CFB_HFP (0x11) /* front porch */ ++#define S3CFB_HSW (0x2A) /* hsync width */ ++ ++#define S3CFB_HRES 800 /* horizon pixel x resolition */ ++#define S3CFB_VRES 600 /* line cnt y resolution */ ++ ++#define S3CFB_CLKVAL 2 ++ ++#else ++#error mini2440 frame buffer driver not configed ++#endif ++ ++#define S3CFB_HRES_VIRTUAL S3CFB_HRES /* horizon pixel x resolition */ ++#define S3CFB_VRES_VIRTUAL S3CFB_VRES /* line cnt y resolution */ ++ ++#define S3CFB_HRES_OSD S3CFB_HRES /* horizon pixel x resolition */ ++#define S3CFB_VRES_OSD S3CFB_VRES /* line cnt y resolution */ ++ ++#define S3CFB_PIXEL_CLOCK S3CFB_CLKVAL ++ ++static void s3cfb_set_fimd_info(void) ++{ ++ s3cfb_fimd.vidcon1 = S3C_VIDCON1_IHSYNC_INVERT | S3C_VIDCON1_IVSYNC_INVERT | S3C_VIDCON1_IVDEN_NORMAL; ++ ++#if defined(CONFIG_FB_S3C_VGA1024768) ++ s3cfb_fimd.vidcon1 = 0; ++#endif ++ s3cfb_fimd.vidtcon0 = S3C_VIDTCON0_VBPD(S3CFB_VBP - 1) | S3C_VIDTCON0_VFPD(S3CFB_VFP - 1) | S3C_VIDTCON0_VSPW(S3CFB_VSW - 1); ++ s3cfb_fimd.vidtcon1 = S3C_VIDTCON1_HBPD(S3CFB_HBP - 1) | S3C_VIDTCON1_HFPD(S3CFB_HFP - 1) | S3C_VIDTCON1_HSPW(S3CFB_HSW - 1); ++ s3cfb_fimd.vidtcon2 = S3C_VIDTCON2_LINEVAL(S3CFB_VRES - 1) | S3C_VIDTCON2_HOZVAL(S3CFB_HRES - 1); ++ ++ s3cfb_fimd.vidosd0a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0); ++ s3cfb_fimd.vidosd0b = S3C_VIDOSDxB_OSD_RBX_F(S3CFB_HRES - 1) | S3C_VIDOSDxB_OSD_RBY_F(S3CFB_VRES - 1); ++ ++ s3cfb_fimd.vidosd1a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0); ++ s3cfb_fimd.vidosd1b = S3C_VIDOSDxB_OSD_RBX_F(S3CFB_HRES_OSD - 1) | S3C_VIDOSDxB_OSD_RBY_F(S3CFB_VRES_OSD - 1); ++ ++ s3cfb_fimd.width = S3CFB_HRES; ++ s3cfb_fimd.height = S3CFB_VRES; ++ s3cfb_fimd.xres = S3CFB_HRES; ++ s3cfb_fimd.yres = S3CFB_VRES; ++ ++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN) ++ s3cfb_fimd.xres_virtual = S3CFB_HRES_VIRTUAL; ++ s3cfb_fimd.yres_virtual = S3CFB_VRES_VIRTUAL; ++#else ++ s3cfb_fimd.xres_virtual = S3CFB_HRES; ++ s3cfb_fimd.yres_virtual = S3CFB_VRES; ++#endif ++ ++ s3cfb_fimd.osd_width = S3CFB_HRES_OSD; ++ s3cfb_fimd.osd_height = S3CFB_VRES_OSD; ++ s3cfb_fimd.osd_xres = S3CFB_HRES_OSD; ++ s3cfb_fimd.osd_yres = S3CFB_VRES_OSD; ++ ++ s3cfb_fimd.osd_xres_virtual = S3CFB_HRES_OSD; ++ s3cfb_fimd.osd_yres_virtual = S3CFB_VRES_OSD; ++ ++ s3cfb_fimd.pixclock = S3CFB_PIXEL_CLOCK; ++ ++ s3cfb_fimd.hsync_len = S3CFB_HSW; ++ s3cfb_fimd.vsync_len = S3CFB_VSW; ++ s3cfb_fimd.left_margin = S3CFB_HFP; ++ s3cfb_fimd.upper_margin = S3CFB_VFP; ++ s3cfb_fimd.right_margin = S3CFB_HBP; ++ s3cfb_fimd.lower_margin = S3CFB_VBP; ++} ++ ++void s3cfb_init_hw(void) ++{ ++ printk(KERN_INFO "LCD TYPE :: LTE480WV will be initialized\n"); ++ ++ s3cfb_set_fimd_info(); ++ s3cfb_set_gpio(); ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/video/samsung/s3cfb.c linux-2.6.28.6/drivers/video/samsung/s3cfb.c +--- linux-2.6.28/drivers/video/samsung/s3cfb.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/video/samsung/s3cfb.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,993 @@ ++/* ++ * drivers/video/s3c/s3cfb.c ++ * ++ * $Id: s3cfb.c,v 1.1 2008/11/17 11:12:08 jsgood Exp $ ++ * ++ * Copyright (C) 2008 Jinsung Yang ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive for ++ * more details. ++ * ++ * S3C Frame Buffer Driver ++ * based on skeletonfb.c, sa1100fb.h, s3c2410fb.c ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "s3cfb.h" ++ ++/* ++ * Globals ++ */ ++s3cfb_info_t s3cfb_info[S3CFB_NUM]; ++ ++static void s3cfb_set_lcd_power(int to) ++{ ++ s3cfb_fimd.lcd_power = to; ++ ++ if (s3cfb_fimd.set_lcd_power) ++ (s3cfb_fimd.set_lcd_power)(to); ++} ++ ++static void s3cfb_set_backlight_power(int to) ++{ ++ s3cfb_fimd.backlight_power = to; ++ ++ if (s3cfb_fimd.set_backlight_power) ++ (s3cfb_fimd.set_backlight_power)(to); ++} ++ ++static void s3cfb_set_backlight_level(int to) ++{ ++ s3cfb_fimd.backlight_level = to; ++ ++ if (s3cfb_fimd.set_brightness) ++ (s3cfb_fimd.set_brightness)(to); ++} ++ ++static int __init s3cfb_map_video_memory(s3cfb_info_t *fbi) ++{ ++ DPRINTK("map_video_memory(fbi=%p)\n", fbi); ++ ++ fbi->map_size_f1 = PAGE_ALIGN(fbi->fb.fix.smem_len); ++ fbi->map_cpu_f1 = dma_alloc_writecombine(fbi->dev, fbi->map_size_f1, &fbi->map_dma_f1, GFP_KERNEL); ++ fbi->map_size_f1 = fbi->fb.fix.smem_len; ++ ++ if (fbi->map_cpu_f1) { ++ /* prevent initial garbage on screen */ ++ printk("Window[%d] - FB1: map_video_memory: clear %p:%08x\n", ++ fbi->win_id, fbi->map_cpu_f1, fbi->map_size_f1); ++ memset(fbi->map_cpu_f1, 0xf0, fbi->map_size_f1); ++ ++ fbi->screen_dma_f1 = fbi->map_dma_f1; ++ fbi->fb.screen_base = fbi->map_cpu_f1; ++ fbi->fb.fix.smem_start = fbi->screen_dma_f1; ++ ++ printk(" FB1: map_video_memory: dma=%08x cpu=%p size=%08x\n", ++ fbi->map_dma_f1, fbi->map_cpu_f1, fbi->fb.fix.smem_len); ++ } ++ ++ if (!fbi->map_cpu_f1) ++ return -ENOMEM; ++ ++#if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING) ++ if (fbi->win_id < 2 && fbi->map_cpu_f1) { ++ fbi->map_size_f2 = (fbi->fb.fix.smem_len / 2); ++ fbi->map_cpu_f2 = fbi->map_cpu_f1 + fbi->map_size_f2; ++ fbi->map_dma_f2 = fbi->map_dma_f1 + fbi->map_size_f2; ++ ++ /* prevent initial garbage on screen */ ++ printk("Window[%d] - FB2: map_video_memory: clear %p:%08x\n", ++ fbi->win_id, fbi->map_cpu_f2, fbi->map_size_f2); ++ ++ fbi->screen_dma_f2 = fbi->map_dma_f2; ++ ++ printk(" FB2: map_video_memory: dma=%08x cpu=%p size=%08x\n", ++ fbi->map_dma_f2, fbi->map_cpu_f2, fbi->map_size_f2); ++ } ++#endif ++ ++ if (s3cfb_fimd.map_video_memory) ++ (s3cfb_fimd.map_video_memory)(fbi); ++ ++ return 0; ++} ++ ++static void s3cfb_unmap_video_memory(s3cfb_info_t *fbi) ++{ ++ dma_free_writecombine(fbi->dev, fbi->map_size_f1, fbi->map_cpu_f1, fbi->map_dma_f1); ++ ++#if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING) ++ dma_free_writecombine(fbi->dev, fbi->map_size_f2, fbi->map_cpu_f2, fbi->map_dma_f2); ++#endif ++ ++ if (s3cfb_fimd.unmap_video_memory) ++ (s3cfb_fimd.unmap_video_memory)(fbi); ++} ++ ++/* ++ * s3cfb_check_var(): ++ * Get the video params out of 'var'. If a value doesn't fit, round it up, ++ * if it's too big, return -EINVAL. ++ * ++ */ ++static int s3cfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) ++{ ++ s3cfb_info_t *fbi = (s3cfb_info_t *) info; ++ ++ DPRINTK("check_var(var=%p, info=%p)\n", var, info); ++ ++ switch (var->bits_per_pixel) { ++ case 8: ++ var->red = s3cfb_rgb_8.red; ++ var->green = s3cfb_rgb_8.green; ++ var->blue = s3cfb_rgb_8.blue; ++ var->transp = s3cfb_rgb_8.transp; ++ s3cfb_fimd.bytes_per_pixel = 1; ++ break; ++ ++ case 16: ++ var->red = s3cfb_rgb_16.red; ++ var->green = s3cfb_rgb_16.green; ++ var->blue = s3cfb_rgb_16.blue; ++ var->transp = s3cfb_rgb_16.transp; ++ s3cfb_fimd.bytes_per_pixel = 2; ++ break; ++ ++ case 24: ++ var->red = s3cfb_rgb_24.red; ++ var->green = s3cfb_rgb_24.green; ++ var->blue = s3cfb_rgb_24.blue; ++ var->transp = s3cfb_rgb_24.transp; ++ s3cfb_fimd.bytes_per_pixel = 4; ++ break; ++ ++ case 28: ++ var->red = s3cfb_rgb_28.red; ++ var->green = s3cfb_rgb_28.green; ++ var->blue = s3cfb_rgb_28.blue; ++ var->transp = s3cfb_rgb_28.transp; ++ s3cfb_fimd.bytes_per_pixel = 4; ++ break; ++ ++ case 32: ++ var->red = s3cfb_rgb_32.red; ++ var->green = s3cfb_rgb_32.green; ++ var->blue = s3cfb_rgb_32.blue; ++ var->transp = s3cfb_rgb_32.transp; ++ s3cfb_fimd.bytes_per_pixel = 4; ++ break; ++ } ++ ++ /* WIN0 cannot support alpha channel. */ ++ if( (fbi->win_id == 0) && (var->bits_per_pixel == 28) ){ ++ var->transp.length = 0; ++ } ++ ++ return 0; ++} ++ ++/* ++ * s3cfb_set_par - Optional function. Alters the hardware state. ++ * @info: frame buffer structure that represents a single frame buffer ++ * ++ */ ++static int s3cfb_set_par(struct fb_info *info) ++{ ++ struct fb_var_screeninfo *var = &info->var; ++ s3cfb_info_t *fbi = (s3cfb_info_t *) info; ++ ++ if (var->bits_per_pixel == 16 || var->bits_per_pixel == 24 || var->bits_per_pixel == 28) ++ fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR; ++ else ++ fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; ++ ++ fbi->fb.fix.line_length = var->width * s3cfb_fimd.bytes_per_pixel; ++ ++ /* activate this new configuration */ ++ s3cfb_activate_var(fbi, var); ++ ++ return 0; ++} ++ ++/** ++ * s3cfb_pan_display ++ * @var: frame buffer variable screen structure ++ * @info: frame buffer structure that represents a single frame buffer ++ * ++ * Pan (or wrap, depending on the `vmode' field) the display using the ++ * `xoffset' and `yoffset' fields of the `var' structure. ++ * If the values don't fit, return -EINVAL. ++ * ++ * Returns negative errno on error, or zero on success. ++ */ ++static int s3cfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) ++{ ++ s3cfb_info_t *fbi = (s3cfb_info_t *)info; ++ ++ DPRINTK("s3c_fb_pan_display(var=%p, info=%p)\n", var, info); ++ ++ if (var->xoffset != 0) ++ return -EINVAL; ++ ++ if (var->yoffset + info->var.yres > info->var.yres_virtual) ++ return -EINVAL; ++ ++ fbi->fb.var.xoffset = var->xoffset; ++ fbi->fb.var.yoffset = var->yoffset; ++ ++ s3cfb_set_fb_addr(fbi); ++ ++ return 0; ++} ++ ++/** ++ * s3cfb_blank ++ * @blank_mode: the blank mode we want. ++ * @info: frame buffer structure that represents a single frame buffer ++ * ++ * Blank the screen if blank_mode != 0, else unblank. Return 0 if ++ * blanking succeeded, != 0 if un-/blanking failed due to e.g. a ++ * video mode which doesn't support it. Implements VESA suspend ++ * and powerdown modes on hardware that supports disabling hsync/vsync: ++ * blank_mode == 2: suspend vsync ++ * blank_mode == 3: suspend hsync ++ * blank_mode == 4: powerdown ++ * ++ * Returns negative errno on error, or zero on success. ++ * ++ */ ++static int s3cfb_blank(int blank_mode, struct fb_info *info) ++{ ++ DPRINTK("blank(mode=%d, info=%p)\n", blank_mode, info); ++ ++ switch (blank_mode) { ++ case VESA_NO_BLANKING: /* lcd on, backlight on */ ++ s3cfb_set_lcd_power(1); ++ s3cfb_set_backlight_power(1); ++ break; ++ ++ case VESA_VSYNC_SUSPEND: /* lcd on, backlight off */ ++ case VESA_HSYNC_SUSPEND: ++ s3cfb_set_lcd_power(1); ++ s3cfb_set_backlight_power(0); ++ break; ++ ++ case VESA_POWERDOWN: /* lcd and backlight off */ ++ s3cfb_set_lcd_power(0); ++ s3cfb_set_backlight_power(0); ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN) ++int s3cfb_set_vs_info(s3cfb_vs_info_t vs_info) ++{ ++ /* check invalid value */ ++ if (vs_info.width != s3cfb_fimd.width || vs_info.height != s3cfb_fimd.height) ++ return 1; ++ ++ if (!(vs_info.bpp == 8 || vs_info.bpp == 16 || vs_info.bpp == 24 || vs_info.bpp == 28 || vs_info.bpp == 32)) ++ return 1; ++ ++ if (vs_info.offset < 0) ++ return 1; ++ ++ if (vs_info.v_width != s3cfb_fimd.xres_virtual || vs_info.v_height != s3cfb_fimd.yres_virtual) ++ return 1; ++ ++ /* save virtual screen information */ ++ s3cfb_fimd.vs_info = vs_info; ++ ++ if (s3cfb_fimd.vs_info.offset < 1) ++ s3cfb_fimd.vs_info.offset = 1; ++ ++ if (s3cfb_fimd.vs_info.offset > S3CFB_MAX_DISPLAY_OFFSET) ++ s3cfb_fimd.vs_info.offset = S3CFB_MAX_DISPLAY_OFFSET; ++ ++ s3cfb_fimd.vs_offset = s3cfb_fimd.vs_info.offset; ++ ++ return 0; ++} ++#endif ++ ++int s3cfb_onoff_win(s3cfb_info_t *fbi, int onoff) ++{ ++ int win_num = fbi->win_id; ++ ++ if (onoff) ++ writel(readl(S3C_WINCON0 + (0x04 * win_num)) | S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON0 + (0x04 * win_num)); ++ else ++ writel(readl(S3C_WINCON0 + (0x04 * win_num)) &~ (S3C_WINCONx_ENWIN_F_ENABLE), S3C_WINCON0 + (0x04 * win_num)); ++ ++ return 0; ++} ++ ++int s3cfb_onoff_color_key_alpha(s3cfb_info_t *fbi, int onoff) ++{ ++ int win_num = fbi->win_id - 1; ++ ++ if (onoff) ++ writel(readl(S3C_W1KEYCON0 + (0x08 * win_num)) | S3C_WxKEYCON0_KEYBLEN_ENABLE, S3C_W1KEYCON0 + (0x08 * win_num)); ++ else ++ writel(readl(S3C_W1KEYCON0 + (0x08 * win_num)) &~ (S3C_WxKEYCON0_KEYBLEN_ENABLE), S3C_W1KEYCON0 + (0x08 * win_num)); ++ ++ return 0; ++} ++ ++int s3cfb_onoff_color_key(s3cfb_info_t *fbi, int onoff) ++{ ++ int win_num = fbi->win_id - 1; ++ ++ if (onoff) ++ writel(readl(S3C_W1KEYCON0 + (0x08 * win_num)) | S3C_WxKEYCON0_KEYEN_F_ENABLE, S3C_W1KEYCON0 + (0x08 * win_num)); ++ else ++ writel(readl(S3C_W1KEYCON0 + (0x08 * win_num)) &~ (S3C_WxKEYCON0_KEYEN_F_ENABLE), S3C_W1KEYCON0 + (0x08 * win_num)); ++ ++ return 0; ++} ++ ++int s3cfb_set_color_key_registers(s3cfb_info_t *fbi, s3cfb_color_key_info_t colkey_info) ++{ ++ unsigned int compkey = 0; ++ int win_num = fbi->win_id; ++ ++ if (win_num == 0) { ++ printk("WIN0 do not support color key\n"); ++ return -1; ++ } ++ ++ win_num--; ++ ++ if (fbi->fb.var.bits_per_pixel == S3CFB_PIXEL_BPP_16) { ++ /* RGB 5-6-5 mode */ ++ compkey = (((colkey_info.compkey_red & 0x1f) << 19) | 0x70000); ++ compkey |= (((colkey_info.compkey_green & 0x3f) << 10) | 0x300); ++ compkey |= (((colkey_info.compkey_blue & 0x1f) << 3 )| 0x7); ++ } else if (fbi->fb.var.bits_per_pixel == S3CFB_PIXEL_BPP_24 || fbi->fb.var.bits_per_pixel == S3CFB_PIXEL_BPP_28) { ++ /* currently RGB 8-8-8 mode */ ++ compkey = ((colkey_info.compkey_red & 0xff) << 16); ++ compkey |= ((colkey_info.compkey_green & 0xff) << 8); ++ compkey |= ((colkey_info.compkey_blue & 0xff) << 0); ++ } else ++ printk("Invalid BPP has been given!\n"); ++ ++ if (colkey_info.direction == S3CFB_COLOR_KEY_DIR_BG) ++ writel(S3C_WxKEYCON0_COMPKEY(compkey) | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE, S3C_W1KEYCON0 + (0x08 * win_num)); ++ ++ else if (colkey_info.direction == S3CFB_COLOR_KEY_DIR_FG) ++ writel(S3C_WxKEYCON0_COMPKEY(compkey) | S3C_WxKEYCON0_DIRCON_MATCH_BG_IMAGE, S3C_W1KEYCON0 + (0x08 * win_num)); ++ ++ else ++ printk("Color key direction is not correct :: %d!\n", colkey_info.direction); ++ ++ return 0; ++} ++ ++int s3cfb_set_color_value(s3cfb_info_t *fbi, s3cfb_color_val_info_t colval_info) ++{ ++ unsigned int colval = 0; ++ ++ int win_num = fbi->win_id; ++ ++ if (win_num == 0) { ++ printk("WIN0 do not support color key value\n"); ++ return -1; ++ } ++ ++ win_num--; ++ ++ if (fbi->fb.var.bits_per_pixel == S3CFB_PIXEL_BPP_16) { ++ /* RGB 5-6-5 mode */ ++ colval = (((colval_info.colval_red & 0x1f) << 19) | 0x70000); ++ colval |= (((colval_info.colval_green & 0x3f) << 10) | 0x300); ++ colval |= (((colval_info.colval_blue & 0x1f) << 3 )| 0x7); ++ } else if (fbi->fb.var.bits_per_pixel == S3CFB_PIXEL_BPP_24 || fbi->fb.var.bits_per_pixel == S3CFB_PIXEL_BPP_28) { ++ /* currently RGB 8-8-8 mode */ ++ colval = ((colval_info.colval_red & 0xff) << 16); ++ colval |= ((colval_info.colval_green & 0xff) << 8); ++ colval |= ((colval_info.colval_blue & 0xff) << 0); ++ } else ++ printk("Invalid BPP has been given!\n"); ++ ++ writel(S3C_WxKEYCON1_COLVAL(colval), S3C_W1KEYCON1 + (0x08 * win_num)); ++ ++ return 0; ++} ++ ++static int s3cfb_set_bpp(s3cfb_info_t *fbi, int bpp) ++{ ++ struct fb_var_screeninfo *var= &fbi->fb.var; ++ int win_num = fbi->win_id; ++ unsigned int val; ++ ++ val = readl(S3C_WINCON0 + (0x04 * win_num)); ++ val &= ~(S3C_WINCONx_BPPMODE_F_MASK | S3C_WINCONx_BLD_PIX_MASK); ++ val |= S3C_WINCONx_ALPHA_SEL_1; ++ ++ switch (bpp) { ++ case 1: ++ case 2: ++ case 4: ++ case 8: ++ s3cfb_fimd.bytes_per_pixel = 1; ++ break; ++ ++ case 16: ++ writel(val | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE, S3C_WINCON0 + (0x04 * win_num)); ++ var->bits_per_pixel = bpp; ++ s3cfb_fimd.bytes_per_pixel = 2; ++ break; ++ ++ case 24: ++ writel(val | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE, S3C_WINCON0 + (0x04 * win_num)); ++ var->bits_per_pixel = bpp; ++ s3cfb_fimd.bytes_per_pixel = 4; ++ break; ++ ++ case 25: ++ writel(val | S3C_WINCONx_BPPMODE_F_25BPP_A888 | S3C_WINCONx_BLD_PIX_PLANE, S3C_WINCON0 + (0x04 * win_num)); ++ var->bits_per_pixel = bpp; ++ s3cfb_fimd.bytes_per_pixel = 4; ++ break; ++ ++ case 28: ++ writel(val | S3C_WINCONx_BPPMODE_F_28BPP_A888 | S3C_WINCONx_BLD_PIX_PIXEL, S3C_WINCON0 + (0x04 * win_num)); ++ var->bits_per_pixel = bpp; ++ s3cfb_fimd.bytes_per_pixel = 4; ++ break; ++ ++ case 32: ++ var->bits_per_pixel = bpp; ++ s3cfb_fimd.bytes_per_pixel = 4; ++ break; ++ } ++ ++ return 0; ++} ++ ++void s3cfb_stop_lcd(void) ++{ ++ unsigned long flags; ++ unsigned long tmp; ++ ++ local_irq_save(flags); ++ ++ tmp = readl(S3C_VIDCON0); ++ writel(tmp & ~(S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE), S3C_VIDCON0); ++ ++ local_irq_restore(flags); ++} ++ ++EXPORT_SYMBOL(s3cfb_stop_lcd); ++ ++void s3cfb_start_lcd(void) ++{ ++ unsigned long flags; ++ unsigned long tmp; ++ ++ local_irq_save(flags); ++ ++ tmp = readl(S3C_VIDCON0); ++ writel(tmp | S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE, S3C_VIDCON0); ++ ++ local_irq_restore(flags); ++} ++ ++EXPORT_SYMBOL(s3cfb_start_lcd); ++ ++void s3cfb_set_clock(unsigned int clkval) ++{ ++ unsigned int tmp; ++ ++ tmp = readl(S3C_VIDCON0); ++ ++ tmp &= ~(0x1 << 4); ++ tmp &= ~(0xff << 6); ++ ++ writel(tmp | (clkval << 6) | (1 << 4), S3C_VIDCON0); ++} ++ ++EXPORT_SYMBOL(s3cfb_set_clock); ++ ++int s3cfb_init_win(s3cfb_info_t *fbi, int bpp, int left_x, int top_y, int width, int height, int onoff) ++{ ++ s3cfb_onoff_win(fbi, OFF); ++ s3cfb_set_bpp(fbi, bpp); ++ s3cfb_set_win_position(fbi, left_x, top_y, width, height); ++ s3cfb_set_win_size(fbi, width, height); ++ s3cfb_set_fb_size(fbi); ++ s3cfb_onoff_win(fbi, onoff); ++ ++ return 0; ++} ++ ++int s3cfb_wait_for_vsync(void) ++{ ++ int cnt; ++ ++ cnt = s3cfb_fimd.vsync_info.count; ++ wait_event_interruptible_timeout(s3cfb_fimd.vsync_info.wait_queue, cnt != s3cfb_fimd.vsync_info.count, HZ / 10); ++ ++ return cnt; ++} ++ ++static void s3cfb_update_palette(s3cfb_info_t *fbi, unsigned int regno, unsigned int val) ++{ ++ unsigned long flags; ++ ++ local_irq_save(flags); ++ ++ fbi->palette_buffer[regno] = val; ++ ++ if (!fbi->palette_ready) { ++ fbi->palette_ready = 1; ++ s3cfb_fimd.palette_win = fbi->win_id; ++ } ++ ++ local_irq_restore(flags); ++} ++ ++static inline unsigned int s3cfb_chan_to_field(unsigned int chan, struct fb_bitfield bf) ++{ ++ chan &= 0xffff; ++ chan >>= 16 - bf.length; ++ ++ return chan << bf.offset; ++} ++ ++static int s3cfb_setcolreg(unsigned int regno, unsigned int red, unsigned int green, unsigned int blue, unsigned int transp, struct fb_info *info) ++{ ++ s3cfb_info_t *fbi = (s3cfb_info_t *)info; ++ unsigned int val = 0; ++ ++ switch (fbi->fb.fix.visual) { ++ case FB_VISUAL_TRUECOLOR: ++ if (regno < 16) { ++ /* Fake palette of 16 colors */ ++ unsigned int *pal = fbi->fb.pseudo_palette; ++ ++ val = s3cfb_chan_to_field(red, fbi->fb.var.red); ++ val |= s3cfb_chan_to_field(green, fbi->fb.var.green); ++ val |= s3cfb_chan_to_field(blue, fbi->fb.var.blue); ++ val |= s3cfb_chan_to_field(transp, fbi->fb.var.transp); ++ ++ pal[regno] = val; ++ } ++ ++ break; ++ ++ case FB_VISUAL_PSEUDOCOLOR: /* This means that the color format isn't 16, 24, 28 bpp. */ ++ /* S3C6410 has 256 palette entries */ ++ if (regno < 256) { ++ /* When var.bits_per_pixel is 8bp, then WIN0's palette is always set as 16 bit */ ++ val = ((red >> 0) & 0xf800); ++ val |= ((green >> 5) & 0x07e0); ++ val |= ((blue >> 11) & 0x001f); ++ ++ DPRINTK("index = %d, val = 0x%08x\n", regno, val); ++ s3cfb_update_palette(fbi, regno, val); ++ } ++ ++ break; ++ ++ default: ++ return 1; /* unknown type */ ++ } ++ ++ return 0; ++} ++ ++/* sysfs export of baclight control */ ++static int s3cfb_sysfs_show_lcd_power(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return snprintf(buf, PAGE_SIZE, "%d\n", s3cfb_fimd.lcd_power); ++} ++ ++static int s3cfb_sysfs_store_lcd_power(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) ++{ ++ if (len < 1) ++ return -EINVAL; ++ ++ if (strnicmp(buf, "on", 2) == 0 || strnicmp(buf, "1", 1) == 0) ++ s3cfb_set_lcd_power(1); ++ else if (strnicmp(buf, "off", 3) == 0 || strnicmp(buf, "0", 1) == 0) ++ s3cfb_set_lcd_power(0); ++ else ++ return -EINVAL; ++ ++ return len; ++} ++ ++static int s3cfb_sysfs_show_backlight_power(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return snprintf(buf, PAGE_SIZE, "%d\n", s3cfb_fimd.backlight_power); ++} ++ ++static int s3cfb_sysfs_store_backlight_power(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) ++{ ++ if (len < 1) ++ return -EINVAL; ++ ++ if (strnicmp(buf, "on", 2) == 0 || strnicmp(buf, "1", 1) == 0) ++ s3cfb_set_backlight_power(1); ++ else if (strnicmp(buf, "off", 3) == 0 || strnicmp(buf, "0", 1) == 0) ++ s3cfb_set_backlight_power(0); ++ else ++ return -EINVAL; ++ ++ return len; ++} ++ ++static int s3cfb_sysfs_show_backlight_level(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return snprintf(buf, PAGE_SIZE, "%d\n", s3cfb_fimd.backlight_level); ++} ++ ++static int s3cfb_sysfs_store_backlight_level(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) ++{ ++ unsigned long value = simple_strtoul(buf, NULL, 10); ++ ++ if (value < s3cfb_fimd.backlight_min || value > s3cfb_fimd.backlight_max) ++ return -ERANGE; ++ ++ s3cfb_set_backlight_level(value); ++ ++ return len; ++} ++ ++static DEVICE_ATTR(lcd_power, 0644, ++ s3cfb_sysfs_show_lcd_power, ++ s3cfb_sysfs_store_lcd_power); ++ ++static DEVICE_ATTR(backlight_power, 0644, ++ s3cfb_sysfs_show_backlight_power, ++ s3cfb_sysfs_store_backlight_power); ++ ++static DEVICE_ATTR(backlight_level, 0644, ++ s3cfb_sysfs_show_backlight_level, ++ s3cfb_sysfs_store_backlight_level); ++ ++struct fb_ops s3cfb_ops = { ++ .owner = THIS_MODULE, ++ .fb_check_var = s3cfb_check_var, ++ .fb_set_par = s3cfb_set_par, ++ .fb_blank = s3cfb_blank, ++ .fb_pan_display = s3cfb_pan_display, ++ .fb_setcolreg = s3cfb_setcolreg, ++ .fb_fillrect = cfb_fillrect, ++ .fb_copyarea = cfb_copyarea, ++ .fb_imageblit = cfb_imageblit, ++ .fb_cursor = soft_cursor, ++ .fb_ioctl = s3cfb_ioctl, ++}; ++ ++static void s3cfb_init_fbinfo(s3cfb_info_t *finfo, char *drv_name, int index) ++{ ++ int i = 0; ++ ++ if (index == 0) ++ s3cfb_init_hw(); ++ ++ strcpy(finfo->fb.fix.id, drv_name); ++ ++ finfo->win_id = index; ++ finfo->fb.fix.type = FB_TYPE_PACKED_PIXELS; ++ finfo->fb.fix.type_aux = 0; ++ finfo->fb.fix.xpanstep = 0; ++ finfo->fb.fix.ypanstep = 1; ++ finfo->fb.fix.ywrapstep = 0; ++ finfo->fb.fix.accel = FB_ACCEL_NONE; ++ ++ finfo->fb.fbops = &s3cfb_ops; ++ finfo->fb.flags = FBINFO_FLAG_DEFAULT; ++ ++ finfo->fb.pseudo_palette = &finfo->pseudo_pal; ++ ++ finfo->fb.var.nonstd = 0; ++ finfo->fb.var.activate = FB_ACTIVATE_NOW; ++ finfo->fb.var.accel_flags = 0; ++ finfo->fb.var.vmode = FB_VMODE_NONINTERLACED; ++ ++ finfo->fb.var.xoffset = s3cfb_fimd.xoffset; ++ finfo->fb.var.yoffset = s3cfb_fimd.yoffset; ++ ++ if (index == 0) { ++ finfo->fb.var.height = s3cfb_fimd.height; ++ finfo->fb.var.width = s3cfb_fimd.width; ++ ++ finfo->fb.var.xres = s3cfb_fimd.xres; ++ finfo->fb.var.yres = s3cfb_fimd.yres; ++ ++ finfo->fb.var.xres_virtual = s3cfb_fimd.xres_virtual; ++ finfo->fb.var.yres_virtual = s3cfb_fimd.yres_virtual; ++ } else { ++ finfo->fb.var.height = s3cfb_fimd.osd_height; ++ finfo->fb.var.width = s3cfb_fimd.osd_width; ++ ++ finfo->fb.var.xres = s3cfb_fimd.osd_xres; ++ finfo->fb.var.yres = s3cfb_fimd.osd_yres; ++ ++ finfo->fb.var.xres_virtual = s3cfb_fimd.osd_xres_virtual; ++ finfo->fb.var.yres_virtual = s3cfb_fimd.osd_yres_virtual; ++ } ++ ++ finfo->fb.var.bits_per_pixel = s3cfb_fimd.bpp; ++ finfo->fb.var.pixclock = s3cfb_fimd.pixclock; ++ finfo->fb.var.hsync_len = s3cfb_fimd.hsync_len; ++ finfo->fb.var.left_margin = s3cfb_fimd.left_margin; ++ finfo->fb.var.right_margin = s3cfb_fimd.right_margin; ++ finfo->fb.var.vsync_len = s3cfb_fimd.vsync_len; ++ finfo->fb.var.upper_margin = s3cfb_fimd.upper_margin; ++ finfo->fb.var.lower_margin = s3cfb_fimd.lower_margin; ++ finfo->fb.var.sync = s3cfb_fimd.sync; ++ finfo->fb.var.grayscale = s3cfb_fimd.cmap_grayscale; ++ ++ finfo->fb.fix.smem_len = finfo->fb.var.xres_virtual * finfo->fb.var.yres_virtual * s3cfb_fimd.bytes_per_pixel; ++ finfo->fb.fix.line_length = finfo->fb.var.width * s3cfb_fimd.bytes_per_pixel; ++ ++#if !defined(CONFIG_FB_S3C_VIRTUAL_SCREEN) ++ ++#if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING) ++ if (index < 2) ++ finfo->fb.fix.smem_len *= 2; ++#else ++ /* ++ * Some systems(ex. DirectFB) use FB0 memory as a video memory. ++ * You can modify the size of multiple. ++ */ ++ if (index == 0) ++ finfo->fb.fix.smem_len *= 5; ++#endif ++ ++#endif ++ ++ for (i = 0; i < 256; i++) ++ finfo->palette_buffer[i] = S3CFB_PALETTE_BUFF_CLEAR; ++} ++ ++/* ++ * Probe ++ */ ++static int __init s3cfb_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ struct fb_info *fbinfo; ++ s3cfb_info_t *info; ++ ++ char driver_name[] = "s3cfb"; ++ int index = 0, ret, size; ++ ++ fbinfo = framebuffer_alloc(sizeof(s3cfb_info_t), &pdev->dev); ++ ++ if (!fbinfo) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, fbinfo); ++ ++ info = fbinfo->par; ++ info->dev = &pdev->dev; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ++ if (res == NULL) { ++ dev_err(&pdev->dev, "failed to get memory registers\n"); ++ ret = -ENXIO; ++ goto dealloc_fb; ++ } ++ ++ size = (res->end - res->start) + 1; ++ info->mem = request_mem_region(res->start, size, pdev->name); ++ ++ if (info->mem == NULL) { ++ dev_err(&pdev->dev, "failed to get memory region\n"); ++ ret = -ENOENT; ++ goto dealloc_fb; ++ } ++ ++ info->io = ioremap(res->start, size); ++ ++ if (info->io == NULL) { ++ dev_err(&pdev->dev, "ioremap() of registers failed\n"); ++ ret = -ENXIO; ++ goto release_mem; ++ } ++ ++ s3cfb_pre_init(); ++ s3cfb_set_backlight_power(1); ++ s3cfb_set_lcd_power(1); ++ s3cfb_set_backlight_level(S3CFB_DEFAULT_BACKLIGHT_LEVEL); ++ ++ info->clk = clk_get(NULL, "lcd"); ++ ++ if (!info->clk || IS_ERR(info->clk)) { ++ printk(KERN_INFO "failed to get lcd clock source\n"); ++ ret = -ENOENT; ++ goto release_io; ++ } ++ ++ clk_enable(info->clk); ++ printk("S3C_LCD clock got enabled :: %ld.%03ld Mhz\n", PRINT_MHZ(clk_get_rate(info->clk))); ++ ++ s3cfb_fimd.vsync_info.count = 0; ++ init_waitqueue_head(&s3cfb_fimd.vsync_info.wait_queue); ++ ++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ ++ if (res == NULL) { ++ dev_err(&pdev->dev, "failed to get irq\n"); ++ ret = -ENXIO; ++ goto release_clock; ++ } ++ ++ ret = request_irq(res->start, s3cfb_irq, 0, "s3c-lcd", pdev); ++ ++ if (ret != 0) { ++ printk("Failed to install irq (%d)\n", ret); ++ goto release_clock; ++ } ++ ++ msleep(5); ++ ++ for (index = 0; index < S3CFB_NUM; index++) { ++ s3cfb_info[index].mem = info->mem; ++ s3cfb_info[index].io = info->io; ++ s3cfb_info[index].clk = info->clk; ++ ++ s3cfb_init_fbinfo(&s3cfb_info[index], driver_name, index); ++ ++ /* Initialize video memory */ ++ ret = s3cfb_map_video_memory(&s3cfb_info[index]); ++ ++ if (ret) { ++ printk("Failed to allocate video RAM: %d\n", ret); ++ ret = -ENOMEM; ++ goto release_irq; ++ } ++ ++ ret = s3cfb_init_registers(&s3cfb_info[index]); ++ ret = s3cfb_check_var(&s3cfb_info[index].fb.var, &s3cfb_info[index].fb); ++ ++ if (index < 2){ ++ if (fb_alloc_cmap(&s3cfb_info[index].fb.cmap, 256, 0) < 0) ++ goto dealloc_fb; ++ } else { ++ if (fb_alloc_cmap(&s3cfb_info[index].fb.cmap, 16, 0) < 0) ++ goto dealloc_fb; ++ } ++ ++ ret = register_framebuffer(&s3cfb_info[index].fb); ++ ++ if (ret < 0) { ++ printk(KERN_ERR "Failed to register framebuffer device: %d\n", ret); ++ goto free_video_memory; ++ } ++ ++ printk(KERN_INFO "fb%d: %s frame buffer device\n", s3cfb_info[index].fb.node, s3cfb_info[index].fb.fix.id); ++ } ++ ++ /* create device files */ ++ ret = device_create_file(&(pdev->dev), &dev_attr_backlight_power); ++ ++ if (ret < 0) ++ printk(KERN_WARNING "s3cfb: failed to add entries\n"); ++ ++ ret = device_create_file(&(pdev->dev), &dev_attr_backlight_level); ++ ++ if (ret < 0) ++ printk(KERN_WARNING "s3cfb: failed to add entries\n"); ++ ++ ret = device_create_file(&(pdev->dev), &dev_attr_lcd_power); ++ ++ if (ret < 0) ++ printk(KERN_WARNING "s3cfb: failed to add entries\n"); ++ ++ return 0; ++ ++free_video_memory: ++ s3cfb_unmap_video_memory(&s3cfb_info[index]); ++ ++release_irq: ++ free_irq(res->start, &info); ++ ++release_clock: ++ clk_disable(info->clk); ++ clk_put(info->clk); ++ ++release_io: ++ iounmap(info->io); ++ ++release_mem: ++ release_resource(info->mem); ++ kfree(info->mem); ++ ++dealloc_fb: ++ framebuffer_release(fbinfo); ++ return ret; ++} ++ ++/* ++ * Remove ++ */ ++static int s3cfb_remove(struct platform_device *pdev) ++{ ++ struct fb_info *fbinfo = platform_get_drvdata(pdev); ++ s3cfb_info_t *info = fbinfo->par; ++ int index = 0, irq; ++ ++ s3cfb_stop_lcd(); ++ msleep(1); ++ ++ if (info->clk) { ++ clk_disable(info->clk); ++ clk_put(info->clk); ++ info->clk = NULL; ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ release_resource(info->mem); ++ ++ for (index = 0; index < S3CFB_NUM; index++) { ++ s3cfb_unmap_video_memory((s3cfb_info_t *) &s3cfb_info[index]); ++ free_irq(irq, &s3cfb_info[index]); ++ unregister_framebuffer(&info[index].fb); ++ } ++ ++ return 0; ++} ++ ++static struct platform_driver s3cfb_driver = { ++ .probe = s3cfb_probe, ++ .remove = s3cfb_remove, ++ .suspend = s3cfb_suspend, ++ .resume = s3cfb_resume, ++ .driver = { ++ .name = "s3c-lcd", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++int __devinit s3cfb_init(void) ++{ ++ return platform_driver_register(&s3cfb_driver); ++} ++static void __exit s3cfb_cleanup(void) ++{ ++ platform_driver_unregister(&s3cfb_driver); ++} ++ ++module_init(s3cfb_init); ++module_exit(s3cfb_cleanup); ++ ++MODULE_AUTHOR("Jinsung Yang"); ++MODULE_DESCRIPTION("S3C Framebuffer Driver"); ++MODULE_LICENSE("GPL"); ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/video/samsung/s3cfb.h linux-2.6.28.6/drivers/video/samsung/s3cfb.h +--- linux-2.6.28/drivers/video/samsung/s3cfb.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/video/samsung/s3cfb.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,519 @@ ++/* ++ * drivers/video/s3c/s3cfb.h ++ * ++ * $Id: s3cfb.h,v 1.1 2008/11/17 11:12:08 jsgood Exp $ ++ * ++ * Copyright (C) 2008 Jinsung Yang ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive for ++ * more details. ++ * ++ * S3C Frame Buffer Driver ++ * based on skeletonfb.c, sa1100fb.h, s3c2410fb.c ++ */ ++ ++#ifndef _S3CFB_H_ ++#define _S3CFB_H_ ++ ++#include ++ ++#if defined(CONFIG_S3C6410_PWM) ++extern int s3c6410_timer_setup (int channel, int usec, unsigned long g_tcnt, unsigned long g_tcmp); ++#elif defined(CONFIG_S5PC1XX_PWM) ++extern int s5pc100_timer_setup (int channel, int usec, unsigned long g_tcnt, unsigned long g_tcmp); ++#endif ++ ++/* ++ * Debug macros ++ */ ++#define DEBUG 0 ++ ++#if DEBUG ++#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args) ++#else ++#define DPRINTK(fmt, args...) ++#endif ++ ++/* ++ * Definitions ++ */ ++#ifndef MHZ ++#define MHZ (1000 * 1000) ++#endif ++ ++#define ON 1 ++#define OFF 0 ++ ++#define S3CFB_PIXEL_BPP_8 8 ++#define S3CFB_PIXEL_BPP_16 16 /* RGB 5-6-5 format for SMDK EVAL BOARD */ ++#define S3CFB_PIXEL_BPP_24 24 /* XRGB 8-8-8 format for SMDK EVAL BOARD */ ++#define S3CFB_PIXEL_BPP_28 28 /* ARGB 4-8-8-8 format for SMDK EVAL BOARD */ ++ ++#define S3CFB_OUTPUT_RGB 0 ++#define S3CFB_OUTPUT_TV 1 ++#define S3CFB_OUTPUT_I80_LDI0 2 ++#define S3CFB_OUTPUT_I80_LDI1 3 ++ ++#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416) ++#define S3CFB_MAX_NUM 2 ++ ++#elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S5PC100) ++#define S3CFB_MAX_NUM 5 ++ ++#elif defined(CONFIG_CPU_S5P6440) ++#define S3CFB_MAX_NUM 3 ++ ++#else ++#define S3CFB_MAX_NUM 1 ++ ++#endif ++ ++#define S3CFB_PALETTE_BUFF_CLEAR (0x80000000) /* entry is clear/invalid */ ++#define S3CFB_COLOR_KEY_DIR_BG 0 ++#define S3CFB_COLOR_KEY_DIR_FG 1 ++#define S3CFB_DEFAULT_BACKLIGHT_LEVEL 2 ++#define S3CFB_MAX_DISPLAY_OFFSET 200 ++#define S3CFB_DEFAULT_DISPLAY_OFFSET 100 ++#define S3CFB_MAX_ALPHA_LEVEL 0xf ++#define S3CFB_MAX_BRIGHTNESS 90 ++#define S3CFB_DEFAULT_BRIGHTNESS 4 ++#define S3CFB_VS_SET 12 ++#define S3CFB_VS_MOVE_LEFT 15 ++#define S3CFB_VS_MOVE_RIGHT 16 ++#define S3CFB_VS_MOVE_UP 17 ++#define S3CFB_VS_MOVE_DOWN 18 ++#define S3CFB_ALPHA_MODE_PLANE 0 ++#define S3CFB_ALPHA_MODE_PIXEL 1 ++ ++/* ++ * macros ++ */ ++#define PRINT_MHZ(m) ((m) / MHZ), ((m / 1000) % 1000) ++#define FB_MIN_NUM(x, y) ((x) < (y) ? (x) : (y)) ++#define S3CFB_NUM FB_MIN_NUM(S3CFB_MAX_NUM, CONFIG_FB_S3C_NUM) ++ ++/* ++ * ioctls ++ */ ++#define S3CFB_GET_BRIGHTNESS _IOR ('F', 1, unsigned int) ++#define S3CFB_SET_BRIGHTNESS _IOW ('F', 2, unsigned int) ++#define FBIO_WAITFORVSYNC _IOW ('F', 32, unsigned int) ++ ++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN) ++#define S3CFB_VS_START _IO ('F', 103) ++#define S3CFB_VS_STOP _IO ('F', 104) ++#define S3CFB_VS_SET_INFO _IOW ('F', 105, s3cfb_vs_info_t) ++#define S3CFB_VS_MOVE _IOW ('F', 106, unsigned int) ++#endif ++ ++#define S3CFB_OSD_START _IO ('F', 201) ++#define S3CFB_OSD_STOP _IO ('F', 202) ++#define S3CFB_OSD_ALPHA_UP _IO ('F', 203) ++#define S3CFB_OSD_ALPHA_DOWN _IO ('F', 204) ++#define S3CFB_OSD_MOVE_LEFT _IO ('F', 205) ++#define S3CFB_OSD_MOVE_RIGHT _IO ('F', 206) ++#define S3CFB_OSD_MOVE_UP _IO ('F', 207) ++#define S3CFB_OSD_MOVE_DOWN _IO ('F', 208) ++#define S3CFB_OSD_SET_INFO _IOW ('F', 209, s3cfb_win_info_t) ++#define S3CFB_OSD_ALPHA0_SET _IOW ('F', 210, unsigned int) ++#define S3CFB_OSD_ALPHA1_SET _IOW ('F', 211, unsigned int) ++#define S3CFB_OSD_ALPHA_MODE _IOW ('F', 212, unsigned int) ++ ++#define S3CFB_COLOR_KEY_START _IO ('F', 300) ++#define S3CFB_COLOR_KEY_STOP _IO ('F', 301) ++#define S3CFB_COLOR_KEY_ALPHA_START _IO ('F', 302) ++#define S3CFB_COLOR_KEY_ALPHA_STOP _IO ('F', 303) ++#define S3CFB_COLOR_KEY_SET_INFO _IOW ('F', 304, s3cfb_color_key_info_t) ++#define S3CFB_COLOR_KEY_VALUE _IOW ('F', 305, s3cfb_color_val_info_t) ++ ++#if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING) ++#define S3CFB_GET_NUM _IOWR('F', 306, unsigned int) ++#endif ++ ++#define S3CFB_GET_INFO _IOR ('F', 307, s3cfb_dma_info_t) ++#define S3CFB_CHANGE_REQ _IOW ('F', 308, int) ++#define S3CFB_SET_VSYNC_INT _IOW ('F', 309, int) ++#define S3CFB_SET_NEXT_FB_INFO _IOW ('F', 320, s3cfb_next_info_t) ++#define S3CFB_GET_CURR_FB_INFO _IOR ('F', 321, s3cfb_next_info_t) ++ ++/* ++ * structures ++ */ ++typedef struct { ++ int bpp; ++ int left_x; ++ int top_y; ++ int width; ++ int height; ++} s3cfb_win_info_t; ++ ++typedef struct { ++ int width; ++ int height; ++ int bpp; ++ int offset; ++ int v_width; ++ int v_height; ++} s3cfb_vs_info_t; ++ ++typedef struct { ++ int direction; ++ unsigned int compkey_red; ++ unsigned int compkey_green; ++ unsigned int compkey_blue; ++} s3cfb_color_key_info_t; ++ ++typedef struct { ++ unsigned int colval_red; ++ unsigned int colval_green; ++ unsigned int colval_blue; ++} s3cfb_color_val_info_t; ++ ++typedef struct { ++ wait_queue_head_t wait_queue; ++ int count; ++} s3cfb_vsync_info_t; ++ ++typedef struct { ++ dma_addr_t map_dma_f1; ++ dma_addr_t map_dma_f2; ++} s3cfb_dma_info_t; ++ ++typedef struct { ++ unsigned int phy_start_addr; ++ unsigned int xres; /* visible resolution*/ ++ unsigned int yres; ++ unsigned int xres_virtual; /* virtual resolution*/ ++ unsigned int yres_virtual; ++ unsigned int xoffset; /* offset from virtual to visible */ ++ unsigned int yoffset; /* resolution */ ++ unsigned int lcd_offset_x; ++ unsigned int lcd_offset_y; ++} s3cfb_next_info_t; ++ ++typedef struct { ++ struct fb_bitfield red; ++ struct fb_bitfield green; ++ struct fb_bitfield blue; ++ struct fb_bitfield transp; ++} s3cfb_rgb_t; ++ ++const static s3cfb_rgb_t s3cfb_rgb_8 = { ++ .red = {.offset = 0, .length = 8,}, ++ .green = {.offset = 0, .length = 8,}, ++ .blue = {.offset = 0, .length = 8,}, ++ .transp = {.offset = 0, .length = 0,}, ++}; ++ ++const static s3cfb_rgb_t s3cfb_rgb_16 = { ++ .red = {.offset = 11, .length = 5,}, ++ .green = {.offset = 5, .length = 6,}, ++ .blue = {.offset = 0, .length = 5,}, ++ .transp = {.offset = 0, .length = 0,}, ++}; ++ ++const static s3cfb_rgb_t s3cfb_rgb_24 = { ++ .red = {.offset = 16, .length = 8,}, ++ .green = {.offset = 8, .length = 8,}, ++ .blue = {.offset = 0, .length = 8,}, ++ .transp = {.offset = 0, .length = 0,}, ++}; ++ ++const static s3cfb_rgb_t s3cfb_rgb_28 = { ++ .red = {.offset = 16, .length = 8,}, ++ .green = {.offset = 8, .length = 8,}, ++ .blue = {.offset = 0, .length = 8,}, ++ .transp = {.offset = 24, .length = 4,}, ++}; ++ ++const static s3cfb_rgb_t s3cfb_rgb_32 = { ++ .red = {.offset = 16, .length = 8,}, ++ .green = {.offset = 8, .length = 8,}, ++ .blue = {.offset = 0, .length = 8,}, ++ .transp = {.offset = 24, .length = 8,}, ++}; ++ ++typedef struct { ++ struct fb_info fb; ++ struct device *dev; ++ ++ struct clk *clk; ++ ++ struct resource *mem; ++ void __iomem *io; ++ ++ unsigned int win_id; ++ ++ unsigned int max_bpp; ++ unsigned int max_xres; ++ unsigned int max_yres; ++ ++ /* raw memory addresses */ ++ dma_addr_t map_dma_f1; /* physical */ ++ u_char * map_cpu_f1; /* virtual */ ++ unsigned int map_size_f1; ++ ++ /* addresses of pieces placed in raw buffer */ ++ u_char * screen_cpu_f1; /* virtual address of frame buffer */ ++ dma_addr_t screen_dma_f1; /* physical address of frame buffer */ ++ ++ /* raw memory addresses */ ++ dma_addr_t map_dma_f2; /* physical */ ++ u_char * map_cpu_f2; /* virtual */ ++ unsigned int map_size_f2; ++ ++ /* addresses of pieces placed in raw buffer */ ++ u_char * screen_cpu_f2; /* virtual address of frame buffer */ ++ dma_addr_t screen_dma_f2; /* physical address of frame buffer */ ++ ++ unsigned int palette_ready; ++ unsigned int fb_change_ready; ++ ++ /* keep these registers in case we need to re-write palette */ ++ unsigned int palette_buffer[256]; ++ unsigned int pseudo_pal[16]; ++ ++ unsigned int lcd_offset_x; ++ unsigned int lcd_offset_y; ++ unsigned int next_fb_info_change_req; ++ s3cfb_next_info_t next_fb_info; ++} s3cfb_info_t; ++ ++typedef struct { ++ ++ /* Screen size */ ++ int width; ++ int height; ++ ++ /* Screen info */ ++ int xres; ++ int yres; ++ ++ /* Virtual Screen info */ ++ int xres_virtual; ++ int yres_virtual; ++ int xoffset; ++ int yoffset; ++ ++ /* OSD Screen size */ ++ int osd_width; ++ int osd_height; ++ ++ /* OSD Screen info */ ++ int osd_xres; ++ int osd_yres; ++ ++ /* OSD Screen info */ ++ int osd_xres_virtual; ++ int osd_yres_virtual; ++ ++ int bpp; ++ int bytes_per_pixel; ++ unsigned long pixclock; ++ ++ int hsync_len; ++ int left_margin; ++ int right_margin; ++ int vsync_len; ++ int upper_margin; ++ int lower_margin; ++ int sync; ++ ++ int cmap_grayscale:1; ++ int cmap_inverse:1; ++ int cmap_static:1; ++ int unused:29; ++ ++ /* backlight info */ ++ int backlight_min; ++ int backlight_max; ++ int backlight_default; ++ ++ int vs_offset; ++ int brightness; ++ int palette_win; ++ int backlight_level; ++ int backlight_power; ++ int lcd_power; ++ ++ s3cfb_vsync_info_t vsync_info; ++ s3cfb_vs_info_t vs_info; ++ ++ /* lcd configuration registers */ ++ unsigned long lcdcon1; ++ unsigned long lcdcon2; ++ ++ unsigned long lcdcon3; ++ unsigned long lcdcon4; ++ unsigned long lcdcon5; ++ ++ /* GPIOs */ ++ unsigned long gpcup; ++ unsigned long gpcup_mask; ++ unsigned long gpccon; ++ unsigned long gpccon_mask; ++ unsigned long gpdup; ++ unsigned long gpdup_mask; ++ unsigned long gpdcon; ++ unsigned long gpdcon_mask; ++ ++ /* lpc3600 control register */ ++ unsigned long lpcsel; ++ unsigned long lcdtcon1; ++ unsigned long lcdtcon2; ++ unsigned long lcdtcon3; ++ unsigned long lcdosd1; ++ unsigned long lcdosd2; ++ unsigned long lcdosd3; ++ unsigned long lcdsaddrb1; ++ unsigned long lcdsaddrb2; ++ unsigned long lcdsaddrf1; ++ unsigned long lcdsaddrf2; ++ unsigned long lcdeaddrb1; ++ unsigned long lcdeaddrb2; ++ unsigned long lcdeaddrf1; ++ unsigned long lcdeaddrf2; ++ unsigned long lcdvscrb1; ++ unsigned long lcdvscrb2; ++ unsigned long lcdvscrf1; ++ unsigned long lcdvscrf2; ++ unsigned long lcdintcon; ++ unsigned long lcdkeycon; ++ unsigned long lcdkeyval; ++ unsigned long lcdbgcon; ++ unsigned long lcdfgcon; ++ unsigned long lcddithcon; ++ ++ unsigned long vidcon0; ++ unsigned long vidcon1; ++ unsigned long vidtcon0; ++ unsigned long vidtcon1; ++ unsigned long vidtcon2; ++ unsigned long vidtcon3; ++ unsigned long wincon0; ++ unsigned long wincon2; ++ unsigned long wincon1; ++ unsigned long wincon3; ++ unsigned long wincon4; ++ ++ unsigned long vidosd0a; ++ unsigned long vidosd0b; ++ unsigned long vidosd0c; ++ unsigned long vidosd1a; ++ unsigned long vidosd1b; ++ unsigned long vidosd1c; ++ unsigned long vidosd1d; ++ unsigned long vidosd2a; ++ unsigned long vidosd2b; ++ unsigned long vidosd2c; ++ unsigned long vidosd2d; ++ unsigned long vidosd3a; ++ unsigned long vidosd3b; ++ unsigned long vidosd3c; ++ unsigned long vidosd4a; ++ unsigned long vidosd4b; ++ unsigned long vidosd4c; ++ ++ unsigned long vidw00add0b0; ++ unsigned long vidw00add0b1; ++ unsigned long vidw01add0; ++ unsigned long vidw01add0b0; ++ unsigned long vidw01add0b1; ++ ++ unsigned long vidw00add1b0; ++ unsigned long vidw00add1b1; ++ unsigned long vidw01add1; ++ unsigned long vidw01add1b0; ++ unsigned long vidw01add1b1; ++ ++ unsigned long vidw00add2b0; ++ unsigned long vidw00add2b1; ++ ++ unsigned long vidw02add0; ++ unsigned long vidw03add0; ++ unsigned long vidw04add0; ++ ++ unsigned long vidw02add1; ++ unsigned long vidw03add1; ++ unsigned long vidw04add1; ++ unsigned long vidw00add2; ++ unsigned long vidw01add2; ++ unsigned long vidw02add2; ++ unsigned long vidw03add2; ++ unsigned long vidw04add2; ++ ++ unsigned long vidintcon; ++ unsigned long vidintcon0; ++ unsigned long vidintcon1; ++ unsigned long w1keycon0; ++ unsigned long w1keycon1; ++ unsigned long w2keycon0; ++ unsigned long w2keycon1; ++ unsigned long w3keycon0; ++ unsigned long w3keycon1; ++ unsigned long w4keycon0; ++ unsigned long w4keycon1; ++ ++ unsigned long win0map; ++ unsigned long win1map; ++ unsigned long win2map; ++ unsigned long win3map; ++ unsigned long win4map; ++ ++ unsigned long wpalcon; ++ unsigned long dithmode; ++ unsigned long intclr0; ++ unsigned long intclr1; ++ unsigned long intclr2; ++ ++ unsigned long win0pal; ++ unsigned long win1pal; ++ ++ /* utility functions */ ++ void (*set_backlight_power)(int); ++ void (*set_lcd_power)(int); ++ void (*set_brightness)(int); ++ int (*map_video_memory)(s3cfb_info_t *); ++ int (*unmap_video_memory)(s3cfb_info_t *); ++}s3cfb_fimd_info_t; ++ ++/* ++ * Externs ++ */ ++extern s3cfb_info_t s3cfb_info[]; ++extern s3cfb_fimd_info_t s3cfb_fimd; ++ ++extern int soft_cursor(struct fb_info *info, struct fb_cursor *cursor); ++extern int s3cfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg); ++extern void s3cfb_activate_var(s3cfb_info_t *fbi, struct fb_var_screeninfo *var); ++extern void s3cfb_set_fb_addr(s3cfb_info_t *fbi); ++extern void s3cfb_init_hw(void); ++extern irqreturn_t s3cfb_irq(int irqno, void *param); ++extern int s3cfb_init_registers(s3cfb_info_t *fbi); ++extern int s3cfb_set_win_position(s3cfb_info_t *fbi, int left_x, int top_y, int width, int height); ++extern int s3cfb_set_win_size(s3cfb_info_t *fbi, int width, int height); ++extern int s3cfb_set_fb_size(s3cfb_info_t *fbi); ++extern int s3cfb_set_vs_info(s3cfb_vs_info_t vs_info); ++extern int s3cfb_wait_for_vsync(void); ++extern int s3cfb_onoff_color_key(s3cfb_info_t *fbi, int onoff); ++extern int s3cfb_onoff_color_key_alpha(s3cfb_info_t *fbi, int onoff); ++extern int s3cfb_set_color_key_registers(s3cfb_info_t *fbi, s3cfb_color_key_info_t colkey_info); ++extern int s3cfb_set_color_value(s3cfb_info_t *fbi, s3cfb_color_val_info_t colval_info); ++extern int s3cfb_init_win(s3cfb_info_t *fbi, int bpp, int left_x, int top_y, int width, int height, int onoff); ++extern int s3cfb_onoff_win(s3cfb_info_t *fbi, int onoff); ++extern int s3cfb_set_gpio(void); ++extern void s3cfb_start_lcd(void); ++extern void s3cfb_stop_lcd(void); ++extern int s3cfb_suspend(struct platform_device *dev, pm_message_t state); ++extern int s3cfb_resume(struct platform_device *dev); ++extern int s3cfb_spi_gpio_request(int ch); ++extern void s3cfb_spi_lcd_den(int ch, int value); ++extern void s3cfb_spi_lcd_dseri(int ch, int value); ++extern void s3cfb_spi_lcd_dclk(int ch, int value); ++extern void s3cfb_spi_set_lcd_data(int ch); ++extern int s3cfb_spi_gpio_free(int ch); ++extern void s3cfb_pre_init(void); ++ ++#endif ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/video/samsung/s3cfb_fimd4x.c linux-2.6.28.6/drivers/video/samsung/s3cfb_fimd4x.c +--- linux-2.6.28/drivers/video/samsung/s3cfb_fimd4x.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/video/samsung/s3cfb_fimd4x.c 2010-05-16 09:03:40.000000000 +0200 +@@ -0,0 +1,1479 @@ ++/* ++ * drivers/video/samsung//s3cfb_fimd4x.c ++ * ++ * $Id: s3cfb_fimd4x.c,v 1.2 2008/11/17 23:44:28 jsgood Exp $ ++ * ++ * Copyright (C) 2008 Jinsung Yang ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive for ++ * more details. ++ * ++ * S3C Frame Buffer Driver ++ * based on skeletonfb.c, sa1100fb.h, s3c2410fb.c ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#if defined(CONFIG_PM) ++#include ++#endif ++ ++#include "s3cfb.h" ++ ++s3cfb_fimd_info_t s3cfb_fimd = { ++ .vidcon0 = S3C_VIDCON0_INTERLACE_F_PROGRESSIVE | S3C_VIDCON0_VIDOUT_RGB_IF | S3C_VIDCON0_L1_DATA16_SUB_16_MODE | \ ++ S3C_VIDCON0_L0_DATA16_MAIN_16_MODE | S3C_VIDCON0_PNRMODE_RGB_P | \ ++ S3C_VIDCON0_CLKVALUP_ALWAYS | S3C_VIDCON0_CLKDIR_DIVIDED | S3C_VIDCON0_CLKSEL_F_HCLK | \ ++ S3C_VIDCON0_ENVID_DISABLE | S3C_VIDCON0_ENVID_F_DISABLE, ++ ++ .dithmode = (S3C_DITHMODE_RDITHPOS_5BIT | S3C_DITHMODE_GDITHPOS_6BIT | S3C_DITHMODE_BDITHPOS_5BIT ) & S3C_DITHMODE_DITHERING_DISABLE, ++ ++#if defined (CONFIG_FB_S3C_BPP_8) ++ .wincon0 = S3C_WINCONx_BYTSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_8BPP_PAL, ++ .wincon1 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, ++ .bpp = S3CFB_PIXEL_BPP_8, ++ .bytes_per_pixel = 1, ++ .wpalcon = S3C_WPALCON_W0PAL_16BIT, ++ ++#elif defined (CONFIG_FB_S3C_BPP_16) ++ .wincon0 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BUFSEL_1 | S3C_WINCONx_BUFAUTOEN_DISABLE | \ ++ S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE | \ ++ S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_ENWIN_F_DISABLE, ++ ++ .wincon1 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BUFSEL_0 | S3C_WINCONx_BUFAUTOEN_DISABLE | \ ++ S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE | \ ++ S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_BPPMODE_F_16BPP_565 | \ ++ S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE, ++ ++ .wincon2 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | \ ++ S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BURSTLEN_16WORD | \ ++ S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE, ++ ++ .wincon3 = S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE | \ ++ S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BLD_PIX_PLANE | \ ++ S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE, ++ ++ .wincon4 = S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE | \ ++ S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BLD_PIX_PLANE | ++ S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE, ++ ++ .bpp = S3CFB_PIXEL_BPP_16, ++ .bytes_per_pixel = 2, ++ .wpalcon = S3C_WPALCON_W0PAL_16BIT, ++ ++#elif defined (CONFIG_FB_S3C_BPP_24) ++ .wincon0 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888, ++ .wincon1 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, ++ .wincon2 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, ++ .wincon3 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, ++ .wincon4 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, ++ .bpp = S3CFB_PIXEL_BPP_24, ++ .bytes_per_pixel = 4, ++ .wpalcon = S3C_WPALCON_W0PAL_24BIT, ++#elif defined (CONFIG_FB_S3C_BPP_28) ++ .wincon0 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888, ++ .wincon1 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_28BPP_A888 | S3C_WINCONx_BLD_PIX_PIXEL | S3C_WINCONx_ALPHA_SEL_1, ++ .wincon2 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_28BPP_A888 | S3C_WINCONx_BLD_PIX_PIXEL | S3C_WINCONx_ALPHA_SEL_1, ++ .wincon3 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_28BPP_A888 | S3C_WINCONx_BLD_PIX_PIXEL | S3C_WINCONx_ALPHA_SEL_1, ++ .wincon4 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_28BPP_A888 | S3C_WINCONx_BLD_PIX_PIXEL | S3C_WINCONx_ALPHA_SEL_1, ++ .bpp = S3CFB_PIXEL_BPP_28, ++ .bytes_per_pixel = 4, ++ .wpalcon = S3C_WPALCON_W0PAL_24BIT, ++#endif ++ ++ .vidosd1c = S3C_VIDOSDxC_ALPHA1_B(S3CFB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(S3CFB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_R(S3CFB_MAX_ALPHA_LEVEL), ++ .vidosd2c = S3C_VIDOSDxC_ALPHA1_B(S3CFB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(S3CFB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_R(S3CFB_MAX_ALPHA_LEVEL), ++ .vidosd3c = S3C_VIDOSDxC_ALPHA1_B(S3CFB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(S3CFB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_R(S3CFB_MAX_ALPHA_LEVEL), ++ .vidosd4c = S3C_VIDOSDxC_ALPHA1_B(S3CFB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(S3CFB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_R(S3CFB_MAX_ALPHA_LEVEL), ++ ++ .vidintcon0 = S3C_VIDINTCON0_FRAMESEL0_VSYNC | S3C_VIDINTCON0_FRAMESEL1_NONE | S3C_VIDINTCON0_INTFRMEN_DISABLE | \ ++ S3C_VIDINTCON0_FIFOSEL_WIN0 | S3C_VIDINTCON0_FIFOLEVEL_25 | S3C_VIDINTCON0_INTFIFOEN_DISABLE | S3C_VIDINTCON0_INTEN_ENABLE, ++ .vidintcon1 = 0, ++ ++ .xoffset = 0, ++ .yoffset = 0, ++ ++ .w1keycon0 = S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE | S3C_WxKEYCON0_COMPKEY(0x0), ++ .w1keycon1 = S3C_WxKEYCON1_COLVAL(0xffffff), ++ .w2keycon0 = S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE | S3C_WxKEYCON0_COMPKEY(0x0), ++ .w2keycon1 = S3C_WxKEYCON1_COLVAL(0xffffff), ++ .w3keycon0 = S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE | S3C_WxKEYCON0_COMPKEY(0x0), ++ .w3keycon1 = S3C_WxKEYCON1_COLVAL(0xffffff), ++ .w4keycon0 = S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE | S3C_WxKEYCON0_COMPKEY(0x0), ++ .w4keycon1 = S3C_WxKEYCON1_COLVAL(0xffffff), ++ ++ .sync = 0, ++ .cmap_static = 1, ++ ++ .vs_offset = S3CFB_DEFAULT_DISPLAY_OFFSET, ++ .brightness = S3CFB_DEFAULT_BRIGHTNESS, ++ .backlight_level = S3CFB_DEFAULT_BACKLIGHT_LEVEL, ++ .backlight_power = 1, ++ .lcd_power = 1, ++}; ++ ++#if defined(CONFIG_S3C6410_PWM) ++void s3cfb_set_brightness(int val) ++{ ++ int channel = 1; /* must use channel-1 */ ++ int usec = 0; /* don't care value */ ++ unsigned long tcnt = 1000; ++ unsigned long tcmp = 0; ++ ++ if (val < 0) ++ val = 0; ++ ++ if (val > S3CFB_MAX_BRIGHTNESS) ++ val = S3CFB_MAX_BRIGHTNESS; ++ ++ s3cfb_fimd.brightness = val; ++ tcmp = val * 5; ++ ++ s3c6410_timer_setup (channel, usec, tcnt, tcmp); ++} ++#endif ++ ++#if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING) ++ ++static void s3cfb_change_buff(int req_win, int req_fb) ++{ ++ switch (req_win) { ++ case 0: ++ if (req_fb == 0) ++ s3cfb_fimd.wincon0 &= ~S3C_WINCONx_BUFSEL_MASK; ++ else ++ s3cfb_fimd.wincon0 |= S3C_WINCONx_BUFSEL_1; ++ ++ writel(s3cfb_fimd.wincon0 | S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON0); ++ break; ++ ++ case 1: ++ if (req_fb == 0) ++ s3cfb_fimd.wincon1 &= ~S3C_WINCONx_BUFSEL_MASK; ++ else ++ s3cfb_fimd.wincon1 |= S3C_WINCONx_BUFSEL_1; ++ ++ writel(s3cfb_fimd.wincon1 | S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON1); ++ break; ++ ++ default: ++ break; ++ } ++} ++ ++#endif ++ ++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN) ++static int s3cfb_set_vs_registers(int vs_cmd) ++{ ++ int page_width, offset; ++ int shift_value; ++ ++ page_width = s3cfb_fimd.xres * s3cfb_fimd.bytes_per_pixel; ++ offset = (s3cfb_fimd.xres_virtual - s3cfb_fimd.xres) * s3cfb_fimd.bytes_per_pixel; ++ ++ switch (vs_cmd){ ++ case S3CFB_VS_SET: ++ /* size of buffer */ ++ s3cfb_fimd.vidw00add2 = S3C_VIDWxxADD2_OFFSIZE_F(offset) | S3C_VIDWxxADD2_PAGEWIDTH_F(page_width); ++ writel(s3cfb_fimd.vidw00add2, S3C_VIDW00ADD2); ++ break; ++ ++ case S3CFB_VS_MOVE_LEFT: ++ if (s3cfb_fimd.xoffset < s3cfb_fimd.vs_offset) ++ shift_value = s3cfb_fimd.xoffset; ++ else ++ shift_value = s3cfb_fimd.vs_offset; ++ ++ s3cfb_fimd.xoffset -= shift_value; ++ ++ /* For buffer start address */ ++ s3cfb_fimd.vidw00add0b0 = s3cfb_fimd.vidw00add0b0 - (s3cfb_fimd.bytes_per_pixel * shift_value); ++ s3cfb_fimd.vidw00add0b1 = s3cfb_fimd.vidw00add0b1 - (s3cfb_fimd.bytes_per_pixel * shift_value); ++ break; ++ ++ case S3CFB_VS_MOVE_RIGHT: ++ if ((s3cfb_fimd.vs_info.v_width - (s3cfb_fimd.xoffset + s3cfb_fimd.vs_info.width)) < (s3cfb_fimd.vs_offset)) ++ shift_value = s3cfb_fimd.vs_info.v_width - (s3cfb_fimd.xoffset + s3cfb_fimd.vs_info.width); ++ else ++ shift_value = s3cfb_fimd.vs_offset; ++ ++ s3cfb_fimd.xoffset += shift_value; ++ ++ /* For buffer start address */ ++ s3cfb_fimd.vidw00add0b0 = s3cfb_fimd.vidw00add0b0 + (s3cfb_fimd.bytes_per_pixel * shift_value); ++ s3cfb_fimd.vidw00add0b1 = s3cfb_fimd.vidw00add0b1 + (s3cfb_fimd.bytes_per_pixel * shift_value); ++ break; ++ ++ case S3CFB_VS_MOVE_UP: ++ if (s3cfb_fimd.yoffset < s3cfb_fimd.vs_offset) ++ shift_value = s3cfb_fimd.yoffset; ++ else ++ shift_value = s3cfb_fimd.vs_offset; ++ ++ s3cfb_fimd.yoffset -= shift_value; ++ ++ /* For buffer start address */ ++ s3cfb_fimd.vidw00add0b0 = s3cfb_fimd.vidw00add0b0 - (s3cfb_fimd.xres_virtual * s3cfb_fimd.bytes_per_pixel * shift_value); ++ s3cfb_fimd.vidw00add0b1 = s3cfb_fimd.vidw00add0b1 - (s3cfb_fimd.xres_virtual * s3cfb_fimd.bytes_per_pixel * shift_value); ++ break; ++ ++ case S3CFB_VS_MOVE_DOWN: ++ if ((s3cfb_fimd.vs_info.v_height - (s3cfb_fimd.yoffset + s3cfb_fimd.vs_info.height)) < (s3cfb_fimd.vs_offset)) ++ shift_value = s3cfb_fimd.vs_info.v_height - (s3cfb_fimd.yoffset + s3cfb_fimd.vs_info.height); ++ else ++ shift_value = s3cfb_fimd.vs_offset; ++ ++ s3cfb_fimd.yoffset += shift_value; ++ ++ /* For buffer start address */ ++ s3cfb_fimd.vidw00add0b0 = s3cfb_fimd.vidw00add0b0 + (s3cfb_fimd.xres_virtual * s3cfb_fimd.bytes_per_pixel * shift_value); ++ s3cfb_fimd.vidw00add0b1 = s3cfb_fimd.vidw00add0b1 + (s3cfb_fimd.xres_virtual * s3cfb_fimd.bytes_per_pixel * shift_value); ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ /* End address */ ++ s3cfb_fimd.vidw00add1b0 = S3C_VIDWxxADD1_VBASEL_F(s3cfb_fimd.vidw00add0b0 + (page_width + offset) * (s3cfb_fimd.yres)); ++ s3cfb_fimd.vidw00add1b1 = S3C_VIDWxxADD1_VBASEL_F(s3cfb_fimd.vidw00add0b1 + (page_width + offset) * (s3cfb_fimd.yres)); ++ ++ writel(s3cfb_fimd.vidw00add0b0, S3C_VIDW00ADD0B0); ++ writel(s3cfb_fimd.vidw00add0b1, S3C_VIDW00ADD0B1); ++ writel(s3cfb_fimd.vidw00add1b0, S3C_VIDW00ADD1B0); ++ writel(s3cfb_fimd.vidw00add1b1, S3C_VIDW00ADD1B1); ++ ++ return 0; ++} ++#endif ++ ++void s3cfb_write_palette(s3cfb_info_t *fbi) ++{ ++ unsigned int i; ++ unsigned long ent; ++ unsigned int win_num = fbi->win_id; ++ ++ fbi->palette_ready = 0; ++ ++ writel((s3cfb_fimd.wpalcon | S3C_WPALCON_PALUPDATEEN), S3C_WPALCON); ++ ++ for (i = 0; i < 256; i++) { ++ if ((ent = fbi->palette_buffer[i]) == S3CFB_PALETTE_BUFF_CLEAR) ++ continue; ++ ++ writel(ent, S3C_TFTPAL0(i) + 0x400 * win_num); ++ ++ /* it seems the only way to know exactly ++ * if the palette wrote ok, is to check ++ * to see if the value verifies ok ++ */ ++ if (readl(S3C_TFTPAL0(i) + 0x400 * win_num) == ent) { ++ fbi->palette_buffer[i] = S3CFB_PALETTE_BUFF_CLEAR; ++ } else { ++ fbi->palette_ready = 1; /* retry */ ++ printk("Retry writing into the palette\n"); ++ } ++ } ++ ++ writel(s3cfb_fimd.wpalcon, S3C_WPALCON); ++} ++ ++irqreturn_t s3cfb_irq(int irqno, void *param) ++{ ++ unsigned long buffer_size = 0; ++ unsigned int i; ++ unsigned int buffer_page_offset, buffer_page_width; ++ unsigned int fb_start_address, fb_end_address; ++ ++ if (s3cfb_info[s3cfb_fimd.palette_win].palette_ready) ++ s3cfb_write_palette(&s3cfb_info[s3cfb_fimd.palette_win]); ++ ++ for (i = 0; i < CONFIG_FB_S3C_NUM; i++) { ++ if (s3cfb_info[i].next_fb_info_change_req) { ++ /* fb variable setting */ ++ s3cfb_info[i].fb.fix.smem_start = s3cfb_info[i].next_fb_info.phy_start_addr; ++ ++ s3cfb_info[i].fb.fix.line_length = s3cfb_info[i].next_fb_info.xres_virtual * ++ s3cfb_fimd.bytes_per_pixel; ++ ++ s3cfb_info[i].fb.fix.smem_len = s3cfb_info[i].next_fb_info.xres_virtual * ++ s3cfb_info[i].next_fb_info.yres_virtual * ++ s3cfb_fimd.bytes_per_pixel; ++ ++ s3cfb_info[i].fb.var.xres = s3cfb_info[i].next_fb_info.xres; ++ s3cfb_info[i].fb.var.yres = s3cfb_info[i].next_fb_info.yres; ++ s3cfb_info[i].fb.var.xres_virtual = s3cfb_info[i].next_fb_info.xres_virtual; ++ s3cfb_info[i].fb.var.yres_virtual= s3cfb_info[i].next_fb_info.yres_virtual; ++ s3cfb_info[i].fb.var.xoffset = s3cfb_info[i].next_fb_info.xoffset; ++ s3cfb_info[i].fb.var.yoffset = s3cfb_info[i].next_fb_info.yoffset; ++ ++ s3cfb_info[i].lcd_offset_x= s3cfb_info[i].next_fb_info.lcd_offset_x; ++ s3cfb_info[i].lcd_offset_y= s3cfb_info[i].next_fb_info.lcd_offset_y; ++ ++ ++ /* fb start / end address setting */ ++ fb_start_address = s3cfb_info[i].next_fb_info.phy_start_addr + ++ s3cfb_info[i].fb.fix.line_length * s3cfb_info[i].next_fb_info.yoffset + ++ s3cfb_info[i].next_fb_info.xoffset * s3cfb_fimd.bytes_per_pixel; ++ ++ fb_end_address = fb_start_address + s3cfb_info[i].fb.fix.line_length * ++ s3cfb_info[i].next_fb_info.yres; ++ ++ writel(fb_start_address, S3C_VIDW00ADD0B0 + 0x8 * i); ++ writel(S3C_VIDWxxADD1_VBASEL_F(fb_end_address), S3C_VIDW00ADD1B0 + 0x8 * i); ++ ++ ++ /* fb virtual / visible size setting */ ++ buffer_page_width = s3cfb_info[i].next_fb_info.xres * s3cfb_fimd.bytes_per_pixel; ++ ++ buffer_page_offset = (s3cfb_info[i].next_fb_info.xres_virtual - ++ s3cfb_info[i].next_fb_info.xres) * s3cfb_fimd.bytes_per_pixel; ++ ++ buffer_size = S3C_VIDWxxADD2_OFFSIZE_F(buffer_page_offset) | ++ (S3C_VIDWxxADD2_PAGEWIDTH_F(buffer_page_width)); ++ ++ writel(buffer_size, S3C_VIDW00ADD2 + 0x04 * i); ++ ++ /* LCD position setting */ ++ writel(S3C_VIDOSDxA_OSD_LTX_F(s3cfb_info[i].next_fb_info.lcd_offset_x) | ++ S3C_VIDOSDxA_OSD_LTY_F(s3cfb_info[i].next_fb_info.lcd_offset_y), S3C_VIDOSD0A+(0x10 * i)); ++ ++ writel(S3C_VIDOSDxB_OSD_RBX_F(s3cfb_info[i].next_fb_info.lcd_offset_x - 1 + s3cfb_info[i].next_fb_info.xres) | ++ S3C_VIDOSDxB_OSD_RBY_F(s3cfb_info[i].next_fb_info.lcd_offset_y - 1 + s3cfb_info[i].next_fb_info.yres), ++ S3C_VIDOSD0B + (0x10 * i)); ++ ++ ++ /* fb size setting */ ++ if (i == 0) ++ writel(S3C_VIDOSD0C_OSDSIZE(s3cfb_info[i].next_fb_info.xres * s3cfb_info[i].next_fb_info.yres), S3C_VIDOSD0C); ++ else if (i == 1) ++ writel(S3C_VIDOSD0C_OSDSIZE(s3cfb_info[i].next_fb_info.xres * s3cfb_info[i].next_fb_info.yres), S3C_VIDOSD1D); ++ else if (i == 2) ++ writel(S3C_VIDOSD0C_OSDSIZE(s3cfb_info[i].next_fb_info.xres * s3cfb_info[i].next_fb_info.yres), S3C_VIDOSD2D); ++ ++ s3cfb_info[i].next_fb_info_change_req = 0; ++ } ++ } ++ ++ /* for clearing the interrupt source */ ++ writel(readl(S3C_VIDINTCON1), S3C_VIDINTCON1); ++ ++ s3cfb_fimd.vsync_info.count++; ++ wake_up_interruptible(&s3cfb_fimd.vsync_info.wait_queue); ++ ++ return IRQ_HANDLED; ++} ++ ++static void s3cfb_check_line_count(void) ++{ ++ int timeout = 30 * 5300; ++ unsigned int cfg; ++ int i; ++ ++ i = 0; ++ do { ++ if (!(readl(S3C_VIDCON1) & 0x7ff0000)) ++ break; ++ i++; ++ } while (i < timeout); ++ ++ if (i == timeout) { ++ printk(KERN_WARNING "line count mismatch\n"); ++ ++ cfg = readl(S3C_VIDCON0); ++ cfg |= (S3C_VIDCON0_ENVID_F_ENABLE | S3C_VIDCON0_ENVID_ENABLE); ++ writel(cfg, S3C_VIDCON0); ++ } ++} ++ ++static void s3cfb_enable_local0(int in_yuv) ++{ ++ unsigned int value; ++ ++ s3cfb_fimd.wincon0 = readl(S3C_WINCON0); ++ s3cfb_fimd.wincon0 &= ~S3C_WINCONx_ENWIN_F_ENABLE; ++ writel(s3cfb_fimd.wincon0, S3C_WINCON0); ++ ++ s3cfb_fimd.wincon0 &= ~(S3C_WINCONx_ENLOCAL_MASK | S3C_WINCONx_INRGB_MASK); ++ value = S3C_WINCONx_ENLOCAL | S3C_WINCONx_ENWIN_F_ENABLE; ++ ++ if (in_yuv) ++ value |= S3C_WINCONx_INRGB_YUV; ++ ++ writel(s3cfb_fimd.wincon0 | value, S3C_WINCON0); ++} ++ ++static void s3cfb_enable_local1(int in_yuv, int sel) ++{ ++ unsigned int value; ++ ++ s3cfb_fimd.wincon1 = readl(S3C_WINCON1); ++ s3cfb_fimd.wincon1 &= ~S3C_WINCONx_ENWIN_F_ENABLE; ++ writel(s3cfb_fimd.wincon1, S3C_WINCON1); ++ ++ s3cfb_fimd.wincon1 &= ~(S3C_WINCONx_ENLOCAL_MASK | S3C_WINCONx_INRGB_MASK); ++ s3cfb_fimd.wincon1 &= ~(S3C_WINCON1_LOCALSEL_MASK); ++ value = sel | S3C_WINCONx_ENLOCAL | S3C_WINCONx_ENWIN_F_ENABLE; ++ ++ if (in_yuv) ++ value |= S3C_WINCONx_INRGB_YUV; ++ ++ writel(s3cfb_fimd.wincon1 | value, S3C_WINCON1); ++} ++ ++static void s3cfb_enable_local2(int in_yuv, int sel) ++{ ++ unsigned int value; ++ ++ s3cfb_fimd.wincon2 = readl(S3C_WINCON2); ++ s3cfb_fimd.wincon2 &= ~S3C_WINCONx_ENWIN_F_ENABLE; ++ s3cfb_fimd.wincon2 &= ~S3C_WINCON2_LOCALSEL_MASK; ++ writel(s3cfb_fimd.wincon2, S3C_WINCON2); ++ ++ s3cfb_fimd.wincon2 &= ~(S3C_WINCONx_ENLOCAL_MASK | S3C_WINCONx_INRGB_MASK); ++ value = sel | S3C_WINCONx_ENLOCAL | S3C_WINCONx_ENWIN_F_ENABLE; ++ ++ if (in_yuv) ++ value |= S3C_WINCONx_INRGB_YUV; ++ ++ writel(s3cfb_fimd.wincon2 | value, S3C_WINCON2); ++} ++ ++static void s3cfb_enable_dma0(void) ++{ ++ u32 value; ++ ++ s3cfb_fimd.wincon0 &= ~(S3C_WINCONx_ENLOCAL_MASK | S3C_WINCONx_INRGB_MASK); ++ value = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_ENWIN_F_ENABLE; ++ ++ writel(s3cfb_fimd.wincon0 | value, S3C_WINCON0); ++} ++ ++static void s3cfb_enable_dma1(void) ++{ ++ u32 value; ++ ++ s3cfb_fimd.wincon1 &= ~(S3C_WINCONx_ENLOCAL_MASK | S3C_WINCONx_INRGB_MASK); ++ value = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_ENWIN_F_ENABLE; ++ ++ writel(s3cfb_fimd.wincon1 | value, S3C_WINCON1); ++} ++ ++static void s3cfb_enable_dma2(void) ++{ ++ u32 value; ++ ++ s3cfb_fimd.wincon2 &= ~(S3C_WINCONx_ENLOCAL_MASK | S3C_WINCONx_INRGB_MASK); ++ value = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_ENWIN_F_ENABLE; ++ ++ writel(s3cfb_fimd.wincon2 | value, S3C_WINCON2); ++} ++ ++void s3cfb_enable_local(int win, int in_yuv, int sel) ++{ ++ s3cfb_check_line_count(); ++ ++ switch (win) { ++ case 0: ++ s3cfb_enable_local0(in_yuv); ++ break; ++ ++ case 1: ++ s3cfb_enable_local1(in_yuv, sel); ++ break; ++ ++ case 2: ++ s3cfb_enable_local2(in_yuv, sel); ++ break; ++ ++ default: ++ break; ++ } ++} ++ ++void s3cfb_enable_dma(int win) ++{ ++ s3cfb_stop_lcd(); ++ ++ switch (win) { ++ case 0: ++ s3cfb_enable_dma0(); ++ break; ++ ++ case 1: ++ s3cfb_enable_dma1(); ++ break; ++ ++ case 2: ++ s3cfb_enable_dma2(); ++ break; ++ ++ default: ++ break; ++ } ++ ++ s3cfb_start_lcd(); ++} ++ ++EXPORT_SYMBOL(s3cfb_enable_local); ++EXPORT_SYMBOL(s3cfb_enable_dma); ++ ++int s3cfb_init_registers(s3cfb_info_t *fbi) ++{ ++ struct clk *lcd_clock; ++ struct fb_var_screeninfo *var = &fbi->fb.var; ++ unsigned long flags = 0, page_width = 0, offset = 0; ++ unsigned long video_phy_temp_f1 = fbi->screen_dma_f1; ++ unsigned long video_phy_temp_f2 = fbi->screen_dma_f2; ++ int win_num = fbi->win_id; ++ ++ /* Initialise LCD with values from hare */ ++ local_irq_save(flags); ++ ++ page_width = var->xres * s3cfb_fimd.bytes_per_pixel; ++ offset = (var->xres_virtual - var->xres) * s3cfb_fimd.bytes_per_pixel; ++ ++ if (win_num == 0) { ++ s3cfb_fimd.vidcon0 = s3cfb_fimd.vidcon0 & ~(S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE); ++ writel(s3cfb_fimd.vidcon0, S3C_VIDCON0); ++ ++ lcd_clock = clk_get(NULL, "lcd"); ++ s3cfb_fimd.vidcon0 |= S3C_VIDCON0_CLKVAL_F((int) (s3cfb_fimd.pixclock)); ++ ++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN) ++ offset = 0; ++ s3cfb_fimd.vidw00add0b0 = video_phy_temp_f1; ++ s3cfb_fimd.vidw00add0b1 = video_phy_temp_f2; ++ s3cfb_fimd.vidw00add1b0 = S3C_VIDWxxADD1_VBASEL_F((unsigned long) video_phy_temp_f1 + (page_width + offset) * (var->yres)); ++ s3cfb_fimd.vidw00add1b1 = S3C_VIDWxxADD1_VBASEL_F((unsigned long) video_phy_temp_f2 + (page_width + offset) * (var->yres)); ++#endif ++ } ++ ++ writel(video_phy_temp_f1, S3C_VIDW00ADD0B0 + (0x08 * win_num)); ++ writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) video_phy_temp_f1 + (page_width + offset) * (var->yres)), S3C_VIDW00ADD1B0 + (0x08 * win_num)); ++ writel(S3C_VIDWxxADD2_OFFSIZE_F(offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(page_width)), S3C_VIDW00ADD2 + (0x04 * win_num)); ++ ++ if (win_num < 2) { ++ writel(video_phy_temp_f2, S3C_VIDW00ADD0B1 + (0x08 * win_num)); ++ writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) video_phy_temp_f2 + (page_width + offset) * (var->yres)), S3C_VIDW00ADD1B1 + (0x08 * win_num)); ++ } ++ ++ switch (win_num) { ++ case 0: ++ writel(s3cfb_fimd.wincon0, S3C_WINCON0); ++ writel(s3cfb_fimd.vidcon0, S3C_VIDCON0); ++ writel(s3cfb_fimd.vidcon1, S3C_VIDCON1); ++ writel(s3cfb_fimd.vidtcon0, S3C_VIDTCON0); ++ writel(s3cfb_fimd.vidtcon1, S3C_VIDTCON1); ++ writel(s3cfb_fimd.vidtcon2, S3C_VIDTCON2); ++ writel(s3cfb_fimd.dithmode, S3C_DITHMODE); ++ writel(s3cfb_fimd.vidintcon0, S3C_VIDINTCON0); ++ writel(s3cfb_fimd.vidintcon1, S3C_VIDINTCON1); ++ writel(s3cfb_fimd.vidosd0a, S3C_VIDOSD0A); ++ writel(s3cfb_fimd.vidosd0b, S3C_VIDOSD0B); ++ writel(s3cfb_fimd.vidosd0c, S3C_VIDOSD0C); ++ writel(s3cfb_fimd.wpalcon, S3C_WPALCON); ++ ++ s3cfb_onoff_win(fbi, ON); ++ break; ++ ++ case 1: ++ writel(s3cfb_fimd.wincon1, S3C_WINCON1); ++ writel(s3cfb_fimd.vidosd1a, S3C_VIDOSD1A); ++ writel(s3cfb_fimd.vidosd1b, S3C_VIDOSD1B); ++ writel(s3cfb_fimd.vidosd1c, S3C_VIDOSD1C); ++ writel(s3cfb_fimd.vidosd1d, S3C_VIDOSD1D); ++ writel(s3cfb_fimd.wpalcon, S3C_WPALCON); ++ ++ s3cfb_onoff_win(fbi, OFF); ++ break; ++ ++ case 2: ++ writel(s3cfb_fimd.wincon2, S3C_WINCON2); ++ writel(s3cfb_fimd.vidosd2a, S3C_VIDOSD2A); ++ writel(s3cfb_fimd.vidosd2b, S3C_VIDOSD2B); ++ writel(s3cfb_fimd.vidosd2c, S3C_VIDOSD2C); ++ writel(s3cfb_fimd.vidosd2d, S3C_VIDOSD2D); ++ writel(s3cfb_fimd.wpalcon, S3C_WPALCON); ++ ++ s3cfb_onoff_win(fbi, OFF); ++ break; ++ ++ case 3: ++ writel(s3cfb_fimd.wincon3, S3C_WINCON3); ++ writel(s3cfb_fimd.vidosd3a, S3C_VIDOSD3A); ++ writel(s3cfb_fimd.vidosd3b, S3C_VIDOSD3B); ++ writel(s3cfb_fimd.vidosd3c, S3C_VIDOSD3C); ++ writel(s3cfb_fimd.wpalcon, S3C_WPALCON); ++ ++ s3cfb_onoff_win(fbi, OFF); ++ break; ++ ++ case 4: ++ writel(s3cfb_fimd.wincon4, S3C_WINCON4); ++ writel(s3cfb_fimd.vidosd4a, S3C_VIDOSD4A); ++ writel(s3cfb_fimd.vidosd4b, S3C_VIDOSD4B); ++ writel(s3cfb_fimd.vidosd4c, S3C_VIDOSD4C); ++ writel(s3cfb_fimd.wpalcon, S3C_WPALCON); ++ ++ s3cfb_onoff_win(fbi, OFF); ++ break; ++ } ++ ++ local_irq_restore(flags); ++ ++ return 0; ++ } ++ ++void s3cfb_activate_var(s3cfb_info_t *fbi, struct fb_var_screeninfo *var) ++{ ++ DPRINTK("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel); ++ ++ switch (var->bits_per_pixel) { ++ case 8: ++ s3cfb_fimd.wincon0 = S3C_WINCONx_BYTSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_8BPP_PAL; ++ s3cfb_fimd.wincon1 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.wincon2 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.wincon3 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.wincon4 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.bpp = S3CFB_PIXEL_BPP_8; ++ s3cfb_fimd.bytes_per_pixel = 1; ++ s3cfb_fimd.wpalcon = S3C_WPALCON_W0PAL_16BIT; ++ break; ++ ++ case 16: ++ s3cfb_fimd.wincon0 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565; ++ s3cfb_fimd.wincon1 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.wincon2 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.wincon3 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.wincon4 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.bpp = S3CFB_PIXEL_BPP_16; ++ s3cfb_fimd.bytes_per_pixel = 2; ++ break; ++ ++ case 24: ++ s3cfb_fimd.wincon0 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888; ++ s3cfb_fimd.wincon1 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.wincon2 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.wincon3 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.wincon4 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.bpp = S3CFB_PIXEL_BPP_24; ++ s3cfb_fimd.bytes_per_pixel = 4; ++ break; ++ ++ case 28: ++ s3cfb_fimd.wincon0 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888; ++ s3cfb_fimd.wincon1 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_28BPP_A888 | S3C_WINCONx_BLD_PIX_PIXEL | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.wincon2 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_28BPP_A888 | S3C_WINCONx_BLD_PIX_PIXEL | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.wincon3 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_28BPP_A888 | S3C_WINCONx_BLD_PIX_PIXEL | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.wincon4 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_28BPP_A888 | S3C_WINCONx_BLD_PIX_PIXEL | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.bpp = S3CFB_PIXEL_BPP_28; ++ s3cfb_fimd.bytes_per_pixel = 4; ++ if((fbi->win_id == 0) && (fbi->fb.var.bits_per_pixel == 28) ) ++ fbi->fb.var.bits_per_pixel = 24; ++ ++ break; ++ ++ case 32: ++ s3cfb_fimd.bytes_per_pixel = 4; ++ break; ++ } ++ ++ /* write new registers */ ++ ++/* FIXME: temporary fixing for pm by jsgood */ ++#if 1 ++ writel(s3cfb_fimd.wincon0, S3C_WINCON0); ++ writel(s3cfb_fimd.wincon1, S3C_WINCON1); ++ writel(s3cfb_fimd.wincon2, S3C_WINCON2); ++ writel(s3cfb_fimd.wincon3, S3C_WINCON3); ++ writel(s3cfb_fimd.wincon4, S3C_WINCON4); ++ writel(s3cfb_fimd.wpalcon, S3C_WPALCON); ++ writel(s3cfb_fimd.wincon0 | S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON0); ++ writel(s3cfb_fimd.vidcon0 | S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE, S3C_VIDCON0); ++#else ++ writel(readl(S3C_WINCON0) | S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON0); ++ writel(readl(S3C_VIDCON0) | S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE, S3C_VIDCON0); ++#endif ++} ++ ++/* JJNAHM comment. ++ * We had some problems related to frame buffer address. ++ * We used 2 frame buffers (FB0 and FB1) and GTK used FB1. ++ * When GTK launched, GTK set FB0's address to FB1's address. ++ * (GTK calls s3c_fb_pan_display() and then it calls this s3c_fb_set_lcdaddr()) ++ * Even though fbi->win_id is not 0, above original codes set ONLY FB0's address. ++ * So, I modified the codes like below. ++ * It works by fbi->win_id value. ++ * Below codes are not verified yet ++ * and there are nothing about Double buffering features ++ */ ++void s3cfb_set_fb_addr(s3cfb_info_t *fbi) ++{ ++ unsigned long video_phy_temp_f1 = fbi->screen_dma_f1; ++ unsigned long start_address, end_address; ++ unsigned int start; ++ ++ start = fbi->fb.fix.line_length * fbi->fb.var.yoffset; ++ ++ /* for buffer start address and end address */ ++ start_address = video_phy_temp_f1 + start; ++ end_address = start_address + (fbi->fb.fix.line_length * fbi->fb.var.yres); ++ ++ switch (fbi->win_id) ++ { ++ case 0: ++ s3cfb_fimd.vidw00add0b0 = start_address; ++ s3cfb_fimd.vidw00add1b0 = end_address; ++ __raw_writel(s3cfb_fimd.vidw00add0b0, S3C_VIDW00ADD0B0); ++ __raw_writel(s3cfb_fimd.vidw00add1b0, S3C_VIDW00ADD1B0); ++ break; ++ ++ case 1: ++ s3cfb_fimd.vidw01add0b0 = start_address; ++ s3cfb_fimd.vidw01add1b0 = end_address; ++ __raw_writel(s3cfb_fimd.vidw01add0b0, S3C_VIDW01ADD0B0); ++ __raw_writel(s3cfb_fimd.vidw01add1b0, S3C_VIDW01ADD1B0); ++ break; ++ ++ case 2: ++ s3cfb_fimd.vidw02add0 = start_address; ++ s3cfb_fimd.vidw02add1 = end_address; ++ __raw_writel(s3cfb_fimd.vidw02add0, S3C_VIDW02ADD0); ++ __raw_writel(s3cfb_fimd.vidw02add1, S3C_VIDW02ADD1); ++ break; ++ ++ case 3: ++ s3cfb_fimd.vidw03add0 = start_address; ++ s3cfb_fimd.vidw03add1 = end_address; ++ __raw_writel(s3cfb_fimd.vidw03add0, S3C_VIDW03ADD0); ++ __raw_writel(s3cfb_fimd.vidw03add1, S3C_VIDW03ADD1); ++ break; ++ ++ case 4: ++ s3cfb_fimd.vidw04add0 = start_address; ++ s3cfb_fimd.vidw04add1 = end_address; ++ __raw_writel(s3cfb_fimd.vidw04add0, S3C_VIDW04ADD0); ++ __raw_writel(s3cfb_fimd.vidw04add1, S3C_VIDW04ADD1); ++ break; ++ } ++} ++ ++static int s3cfb_set_alpha_level(s3cfb_info_t *fbi, unsigned int level, unsigned int alpha_index) ++{ ++ unsigned long alpha_val; ++ int win_num = fbi->win_id; ++ ++ if (win_num == 0) { ++ printk("WIN0 do not support alpha blending.\n"); ++ return -1; ++ } ++ ++ alpha_val = readl(S3C_VIDOSD0C+(0x10 * win_num)); ++ ++ if (alpha_index == 0) { ++ alpha_val &= ~(S3C_VIDOSDxC_ALPHA0_B(0xf) | S3C_VIDOSDxC_ALPHA0_G(0xf) | S3C_VIDOSDxC_ALPHA0_R(0xf)); ++ alpha_val |= S3C_VIDOSDxC_ALPHA0_B(level) | S3C_VIDOSDxC_ALPHA0_G(level) | S3C_VIDOSDxC_ALPHA0_R(level); ++ } else { ++ alpha_val &= ~(S3C_VIDOSDxC_ALPHA1_B(0xf) | S3C_VIDOSDxC_ALPHA1_G(0xf) | S3C_VIDOSDxC_ALPHA1_R(0xf)); ++ alpha_val |= S3C_VIDOSDxC_ALPHA1_B(level) | S3C_VIDOSDxC_ALPHA1_G(level) | S3C_VIDOSDxC_ALPHA1_R(level); ++ } ++ ++ writel(alpha_val, S3C_VIDOSD0C + (0x10 * win_num)); ++ ++ return 0; ++} ++ ++int s3cfb_set_alpha_mode(s3cfb_info_t *fbi, int mode) ++{ ++ unsigned long alpha_mode; ++ int win_num = fbi->win_id; ++ ++ if (win_num == 0) { ++ printk("WIN0 do not support alpha blending.\n"); ++ return -1; ++ } ++ ++ alpha_mode = readl(S3C_WINCON0 + (0x04 * win_num)); ++ alpha_mode &= ~(S3C_WINCONx_BLD_PIX_PIXEL | S3C_WINCONx_ALPHA_SEL_1); ++ ++ switch (mode) { ++ case S3CFB_ALPHA_MODE_PLANE: /* Plane Blending */ ++ writel(alpha_mode | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, S3C_WINCON0 + (0x04 * win_num)); ++ break; ++ ++ case S3CFB_ALPHA_MODE_PIXEL: /* Pixel Blending & chroma(color) key */ ++ writel(alpha_mode | S3C_WINCONx_BLD_PIX_PIXEL | S3C_WINCONx_ALPHA_SEL_0, S3C_WINCON0 + (0x04 * win_num)); ++ break; ++ } ++ ++ return 0; ++} ++ ++int s3cfb_set_win_position(s3cfb_info_t *fbi, int left_x, int top_y, int width, int height) ++{ ++ struct fb_var_screeninfo *var= &fbi->fb.var; ++ int win_num = fbi->win_id; ++ ++ writel(S3C_VIDOSDxA_OSD_LTX_F(left_x) | S3C_VIDOSDxA_OSD_LTY_F(top_y), S3C_VIDOSD0A + (0x10 * win_num)); ++ writel(S3C_VIDOSDxB_OSD_RBX_F(width - 1 + left_x) | S3C_VIDOSDxB_OSD_RBY_F(height - 1 + top_y), S3C_VIDOSD0B + (0x10 * win_num)); ++ ++ var->xoffset = left_x; ++ var->yoffset = top_y; ++ ++ return 0; ++} ++ ++int s3cfb_set_win_size(s3cfb_info_t *fbi, int width, int height) ++{ ++ struct fb_var_screeninfo *var= &fbi->fb.var; ++ int win_num = fbi->win_id; ++ ++ if (win_num == 1) ++ writel(S3C_VIDOSD0C_OSDSIZE(width * height), S3C_VIDOSD1D); ++ ++ else if (win_num == 2) ++ writel(S3C_VIDOSD0C_OSDSIZE(width * height), S3C_VIDOSD2D); ++ ++ var->xres = width; ++ var->yres = height; ++ var->xres_virtual = width; ++ var->yres_virtual = height; ++ ++ return 0; ++} ++ ++int s3cfb_set_fb_size(s3cfb_info_t *fbi) ++{ ++ struct fb_var_screeninfo *var= &fbi->fb.var; ++ int win_num = fbi->win_id; ++ unsigned long offset = 0; ++ unsigned long page_width = 0; ++ unsigned long fb_size = 0; ++ ++ page_width = var->xres * s3cfb_fimd.bytes_per_pixel; ++ offset = (var->xres_virtual - var->xres) * s3cfb_fimd.bytes_per_pixel; ++ ++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN) ++ if (win_num == 0) ++ offset=0; ++#endif ++ ++ writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) readl(S3C_VIDW00ADD0B0 + (0x08 * win_num)) + (page_width + offset) * (var->yres)), S3C_VIDW00ADD1B0 + (0x08 * win_num)); ++ ++ if (win_num == 1) ++ writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) readl(S3C_VIDW00ADD0B1 + (0x08 * win_num)) + (page_width + offset) * (var->yres)), S3C_VIDW00ADD1B1 + (0x08 * win_num)); ++ ++ /* size of frame buffer */ ++ fb_size = S3C_VIDWxxADD2_OFFSIZE_F(offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(page_width)); ++ ++ writel(fb_size, S3C_VIDW00ADD2 + (0x04 * win_num)); ++ ++ return 0; ++} ++ ++void s3cfb_set_output_path(int out) ++{ ++ unsigned int tmp; ++ ++ tmp = readl(S3C_VIDCON0); ++ ++ /* if output mode is LCD mode, Scan mode always should be progressive mode */ ++ if (out == S3CFB_OUTPUT_TV) ++ tmp &= ~S3C_VIDCON0_INTERLACE_F_MASK; ++ ++ tmp &= ~S3C_VIDCON0_VIDOUT_MASK; ++ tmp |= S3C_VIDCON0_VIDOUT(out); ++ ++ writel(tmp, S3C_VIDCON0); ++} ++ ++EXPORT_SYMBOL(s3cfb_set_output_path); ++ ++void s3cfb_enable_rgbport(int on) ++{ ++ if (on) ++ writel(S3C_VIDCON2_ORGYUV_CBCRY | S3C_VIDCON2_YUVORD_CRCB, S3C_VIDCON2); ++ else ++ writel(0, S3C_VIDCON2); ++} ++ ++EXPORT_SYMBOL(s3cfb_enable_rgbport); ++ ++int s3cfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) ++{ ++ s3cfb_info_t *fbi = container_of(info, s3cfb_info_t, fb); ++ s3cfb_win_info_t win_info; ++ s3cfb_color_key_info_t colkey_info; ++ s3cfb_color_val_info_t colval_info; ++ s3cfb_dma_info_t dma_info; ++ s3cfb_next_info_t next_fb_info; ++ struct fb_var_screeninfo *var= &fbi->fb.var; ++ unsigned int crt, alpha_level, alpha_mode; ++ ++#if defined(CONFIG_S3C6410_PWM) ++ int brightness; ++#endif ++ ++#if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING) ++ unsigned int f_num_val; ++#endif ++ ++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN) ++ s3cfb_vs_info_t vs_info; ++#endif ++ ++ switch(cmd){ ++ case S3CFB_GET_INFO: ++ dma_info.map_dma_f1 = fbi->map_dma_f1; ++ dma_info.map_dma_f2 = fbi->map_dma_f2; ++ ++ if(copy_to_user((void *) arg, (const void *) &dma_info, sizeof(s3cfb_dma_info_t))) ++ return -EFAULT; ++ break; ++ ++ case S3CFB_OSD_SET_INFO: ++ if (copy_from_user(&win_info, (s3cfb_win_info_t *) arg, sizeof(s3cfb_win_info_t))) ++ return -EFAULT; ++ ++ s3cfb_init_win(fbi, win_info.bpp, win_info.left_x, win_info.top_y, win_info.width, win_info.height, OFF); ++ break; ++ ++ case S3CFB_OSD_START: ++ s3cfb_onoff_win(fbi, ON); ++ break; ++ ++ case S3CFB_OSD_STOP: ++ s3cfb_onoff_win(fbi, OFF); ++ break; ++ ++ case S3CFB_OSD_ALPHA_UP: ++ alpha_level = readl(S3C_VIDOSD0C + (0x10 * fbi->win_id)) & 0xf; ++ ++ if (alpha_level < S3CFB_MAX_ALPHA_LEVEL) ++ alpha_level++; ++ ++ s3cfb_set_alpha_level(fbi, alpha_level, 1); ++ break; ++ ++ case S3CFB_OSD_ALPHA_DOWN: ++ alpha_level = readl(S3C_VIDOSD0C + (0x10 * fbi->win_id)) & 0xf; ++ ++ if (alpha_level > 0) ++ alpha_level--; ++ ++ s3cfb_set_alpha_level(fbi, alpha_level, 1); ++ break; ++ ++ case S3CFB_OSD_ALPHA0_SET: ++ alpha_level = (unsigned int) arg; ++ ++ if (alpha_level > S3CFB_MAX_ALPHA_LEVEL) ++ alpha_level = S3CFB_MAX_ALPHA_LEVEL; ++ ++ s3cfb_set_alpha_level(fbi, alpha_level, 0); ++ break; ++ ++ case S3CFB_OSD_ALPHA1_SET: ++ alpha_level = (unsigned int) arg; ++ ++ if (alpha_level > S3CFB_MAX_ALPHA_LEVEL) ++ alpha_level = S3CFB_MAX_ALPHA_LEVEL; ++ ++ s3cfb_set_alpha_level(fbi, alpha_level, 1); ++ break; ++ ++ case S3CFB_OSD_ALPHA_MODE: ++ alpha_mode = (unsigned int) arg; ++ s3cfb_set_alpha_mode(fbi, alpha_mode); ++ break; ++ ++ case S3CFB_OSD_MOVE_LEFT: ++ if (var->xoffset > 0) ++ var->xoffset--; ++ ++ s3cfb_set_win_position(fbi, var->xoffset, var->yoffset, var->xres, var->yres); ++ break; ++ ++ case S3CFB_OSD_MOVE_RIGHT: ++ if (var->xoffset < (s3cfb_fimd.width - var->xres)) ++ var->xoffset++; ++ ++ s3cfb_set_win_position(fbi, var->xoffset, var->yoffset, var->xres, var->yres); ++ break; ++ ++ case S3CFB_OSD_MOVE_UP: ++ if (var->yoffset > 0) ++ var->yoffset--; ++ ++ s3cfb_set_win_position(fbi, var->xoffset, var->yoffset, var->xres, var->yres); ++ break; ++ ++ case S3CFB_OSD_MOVE_DOWN: ++ if (var->yoffset < (s3cfb_fimd.height - var->yres)) ++ var->yoffset++; ++ ++ s3cfb_set_win_position(fbi, var->xoffset, var->yoffset, var->xres, var->yres); ++ break; ++ ++ case FBIO_WAITFORVSYNC: ++ if (get_user(crt, (unsigned int __user *)arg)) ++ return -EFAULT; ++ ++ return s3cfb_wait_for_vsync(); ++ ++ case S3CFB_COLOR_KEY_START: ++ s3cfb_onoff_color_key(fbi, ON); ++ break; ++ ++ case S3CFB_COLOR_KEY_STOP: ++ s3cfb_onoff_color_key(fbi, OFF); ++ break; ++ ++ case S3CFB_COLOR_KEY_ALPHA_START: ++ s3cfb_onoff_color_key_alpha(fbi, ON); ++ break; ++ ++ case S3CFB_COLOR_KEY_ALPHA_STOP: ++ s3cfb_onoff_color_key_alpha(fbi, OFF); ++ break; ++ ++ case S3CFB_COLOR_KEY_SET_INFO: ++ if (copy_from_user(&colkey_info, (s3cfb_color_key_info_t *) arg, sizeof(s3cfb_color_key_info_t))) ++ return -EFAULT; ++ ++ s3cfb_set_color_key_registers(fbi, colkey_info); ++ break; ++ ++ case S3CFB_COLOR_KEY_VALUE: ++ if (copy_from_user(&colval_info, (s3cfb_color_val_info_t *) arg, sizeof(s3cfb_color_val_info_t))) ++ return -EFAULT; ++ ++ s3cfb_set_color_value(fbi, colval_info); ++ break; ++ ++ case S3CFB_SET_VSYNC_INT: ++ s3cfb_fimd.vidintcon0 &= ~S3C_VIDINTCON0_FRAMESEL0_MASK; ++ s3cfb_fimd.vidintcon0 |= S3C_VIDINTCON0_FRAMESEL0_VSYNC; ++ ++ if (arg) ++ s3cfb_fimd.vidintcon0 |= S3C_VIDINTCON0_INTFRMEN_ENABLE; ++ else ++ s3cfb_fimd.vidintcon0 &= ~S3C_VIDINTCON0_INTFRMEN_ENABLE; ++ ++ writel(s3cfb_fimd.vidintcon0, S3C_VIDINTCON0); ++ break; ++ ++ case S3CFB_SET_NEXT_FB_INFO: ++ if (copy_from_user(&next_fb_info, (s3cfb_next_info_t *) arg, sizeof(s3cfb_next_info_t))) ++ return -EFAULT; ++ ++ /* check arguments */ ++ if ((next_fb_info.xres + next_fb_info.xoffset) > next_fb_info.xres_virtual || ++ (next_fb_info.yres + next_fb_info.yoffset) > next_fb_info.yres_virtual || ++ (next_fb_info.xres + next_fb_info.lcd_offset_x ) > s3cfb_fimd.width || ++ (next_fb_info.yres + next_fb_info.lcd_offset_y ) > s3cfb_fimd.height) { ++ printk("Error : S3CFB_SET_NEXT_FB_INFO\n"); ++ return -EINVAL; ++ } ++ ++ ++ fbi->next_fb_info = next_fb_info; ++ fbi->next_fb_info_change_req = 1; ++ break; ++ ++ case S3CFB_GET_CURR_FB_INFO: ++ next_fb_info.phy_start_addr = fbi->fb.fix.smem_start; ++ next_fb_info.xres = fbi->fb.var.xres; ++ next_fb_info.yres = fbi->fb.var.yres; ++ next_fb_info.xres_virtual = fbi->fb.var.xres_virtual; ++ next_fb_info.yres_virtual = fbi->fb.var.yres_virtual; ++ next_fb_info.xoffset = fbi->fb.var.xoffset; ++ next_fb_info.yoffset = fbi->fb.var.yoffset; ++ next_fb_info.lcd_offset_x = fbi->lcd_offset_x; ++ next_fb_info.lcd_offset_y = fbi->lcd_offset_y; ++ ++ if (copy_to_user((void *)arg, (s3cfb_next_info_t *) &next_fb_info, sizeof(s3cfb_next_info_t))) ++ return -EFAULT; ++ break; ++ ++ case S3CFB_GET_BRIGHTNESS: ++ if (copy_to_user((void *)arg, (const void *) &s3cfb_fimd.brightness, sizeof(int))) ++ return -EFAULT; ++ break; ++ ++#if defined(CONFIG_S3C6410_PWM) ++ case S3CFB_SET_BRIGHTNESS: ++ if (copy_from_user(&brightness, (int *) arg, sizeof(int))) ++ return -EFAULT; ++ ++ s3cfb_set_brightness(brightness); ++ break; ++#endif ++ ++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN) ++ case S3CFB_VS_START: ++ s3cfb_fimd.wincon0 &= ~(S3C_WINCONx_ENWIN_F_ENABLE); ++ writel(s3cfb_fimd.wincon0 | S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON0); ++ ++ fbi->fb.var.xoffset = s3cfb_fimd.xoffset; ++ fbi->fb.var.yoffset = s3cfb_fimd.yoffset; ++ break; ++ ++ case S3CFB_VS_STOP: ++ s3cfb_fimd.vidw00add0b0 = fbi->screen_dma_f1; ++ s3cfb_fimd.vidw00add0b1 = fbi->screen_dma_f2; ++ fbi->fb.var.xoffset = 0; ++ fbi->fb.var.yoffset = 0; ++ ++ writel(s3cfb_fimd.vidw00add0b0, S3C_VIDW00ADD0B0); ++ writel(s3cfb_fimd.vidw00add0b1, S3C_VIDW00ADD0B1); ++ ++ break; ++ ++ case S3CFB_VS_SET_INFO: ++ if (copy_from_user(&vs_info, (s3cfb_vs_info_t *) arg, sizeof(s3cfb_vs_info_t))) ++ return -EFAULT; ++ ++ if (s3cfb_set_vs_info(vs_info)) { ++ printk("Error S3CFB_VS_SET_INFO\n"); ++ return -EINVAL; ++ } ++ ++ s3cfb_set_vs_registers(S3CFB_VS_SET); ++ ++ fbi->fb.var.xoffset = s3cfb_fimd.xoffset; ++ fbi->fb.var.yoffset = s3cfb_fimd.yoffset; ++ break; ++ ++ case S3CFB_VS_MOVE: ++ s3cfb_set_vs_registers(arg); ++ ++ fbi->fb.var.xoffset = s3cfb_fimd.xoffset; ++ fbi->fb.var.yoffset = s3cfb_fimd.yoffset; ++ break; ++#endif ++ ++#if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING) ++ case S3CFB_GET_NUM: ++ if (copy_from_user((void *)&f_num_val, (const void *)arg, sizeof(u_int))) ++ return -EFAULT; ++ ++ if (copy_to_user((void *)arg, (const void *) &f_num_val, sizeof(u_int))) ++ return -EFAULT; ++ ++ break; ++ ++ case S3CFB_CHANGE_REQ: ++ s3cfb_change_buff(0, (int) arg); ++ break; ++#endif ++ ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++void s3cfb_pre_init(void) ++{ ++ /* initialize the fimd specific */ ++ s3cfb_fimd.vidintcon0 &= ~S3C_VIDINTCON0_FRAMESEL0_MASK; ++ s3cfb_fimd.vidintcon0 |= S3C_VIDINTCON0_FRAMESEL0_VSYNC; ++ s3cfb_fimd.vidintcon0 |= S3C_VIDINTCON0_INTFRMEN_ENABLE; ++ ++ writel(s3cfb_fimd.vidintcon0, S3C_VIDINTCON0); ++} ++ ++int s3cfb_set_gpio(void) ++{ ++ unsigned long val; ++ int i, err; ++ ++ /* Must be '0' for Normal-path instead of By-pass */ ++ writel(0x0, S3C_HOSTIFB_MIFPCON); ++ ++ /* enable clock to LCD */ ++ val = readl(S3C_HCLK_GATE); ++ val |= S3C_CLKCON_HCLK_LCD; ++ writel(val, S3C_HCLK_GATE); ++ ++ /* select TFT LCD type (RGB I/F) */ ++ val = readl(S3C64XX_SPC_BASE); ++ val &= ~0x3; ++ val |= (1 << 0); ++ writel(val, S3C64XX_SPC_BASE); ++ ++ /* VD */ ++ for (i = 0; i < 16; i++) ++ s3c_gpio_cfgpin(S3C64XX_GPI(i), S3C_GPIO_SFN(2)); ++ ++ for (i = 0; i < 12; i++) ++ s3c_gpio_cfgpin(S3C64XX_GPJ(i), S3C_GPIO_SFN(2)); ++ ++#if 0 ++#ifndef CONFIG_BACKLIGHT_PWM ++ /* backlight ON */ ++ //printk("oPEN LCD BACKLIGHT1.\n"); ++ if (gpio_is_valid(S3C64XX_GPF(14))) { //NOTE: orign GPF15 here ++ err = gpio_request(S3C64XX_GPF(14), "GPF"); ++ ++ if (err) { ++ printk(KERN_ERR "failed to request GPF for " ++ "lcd backlight control\n"); ++ return err; ++ } ++ ++ gpio_direction_output(S3C64XX_GPF(14), 1); ++ gpio_set_value(S3C64XX_GPF(14), 1); ++ } ++#endif ++#endif ++ //printk("oPEN LCD BACKLIGHT2.\n"); ++ if (gpio_is_valid(S3C64XX_GPE(0))) { ++ err = gpio_request(S3C64XX_GPE(0), "GPE"); ++ ++ if (err) { ++ printk(KERN_ERR "failed to request GPE for " ++ "lcd reset control\n"); ++ return err; ++ } ++ ++ gpio_direction_output(S3C64XX_GPE(0), 1); ++ } ++ gpio_set_value(S3C64XX_GPE(0), 1); ++ gpio_free(S3C64XX_GPE(0)); ++ ++ /* module reset */ ++ /*if (gpio_is_valid(S3C64XX_GPN(5))) { ++ err = gpio_request(S3C64XX_GPN(5), "GPN"); ++ ++ if (err) { ++ printk(KERN_ERR "failed to request GPN for " ++ "lcd reset control\n"); ++ return err; ++ } ++ ++ gpio_direction_output(S3C64XX_GPN(5), 1); ++ } ++ ++ mdelay(100); ++ ++ gpio_set_value(S3C64XX_GPN(5), 0); ++ mdelay(10); ++ ++ gpio_set_value(S3C64XX_GPN(5), 1); ++ mdelay(10); ++ */ ++#ifndef CONFIG_BACKLIGHT_PWM ++ gpio_free(S3C64XX_GPF(14)); ++#endif ++ ++ //gpio_free(S3C64XX_GPN(5)); ++ ++ return 0; ++} ++ ++#if defined(CONFIG_PM) ++ ++static struct sleep_save s3c_lcd_save[] = { ++ SAVE_ITEM(S3C_VIDCON0), ++ SAVE_ITEM(S3C_VIDCON1), ++ ++ SAVE_ITEM(S3C_VIDTCON0), ++ SAVE_ITEM(S3C_VIDTCON1), ++ SAVE_ITEM(S3C_VIDTCON2), ++ SAVE_ITEM(S3C_VIDTCON3), ++ ++ SAVE_ITEM(S3C_WINCON0), ++ SAVE_ITEM(S3C_WINCON1), ++ SAVE_ITEM(S3C_WINCON2), ++ SAVE_ITEM(S3C_WINCON3), ++ SAVE_ITEM(S3C_WINCON4), ++ ++ SAVE_ITEM(S3C_VIDOSD0A), ++ SAVE_ITEM(S3C_VIDOSD0B), ++ SAVE_ITEM(S3C_VIDOSD0C), ++ ++ SAVE_ITEM(S3C_VIDOSD1A), ++ SAVE_ITEM(S3C_VIDOSD1B), ++ SAVE_ITEM(S3C_VIDOSD1C), ++ SAVE_ITEM(S3C_VIDOSD1D), ++ ++ SAVE_ITEM(S3C_VIDOSD2A), ++ SAVE_ITEM(S3C_VIDOSD2B), ++ SAVE_ITEM(S3C_VIDOSD2C), ++ SAVE_ITEM(S3C_VIDOSD2D), ++ ++ SAVE_ITEM(S3C_VIDOSD3A), ++ SAVE_ITEM(S3C_VIDOSD3B), ++ SAVE_ITEM(S3C_VIDOSD3C), ++ ++ SAVE_ITEM(S3C_VIDOSD4A), ++ SAVE_ITEM(S3C_VIDOSD4B), ++ SAVE_ITEM(S3C_VIDOSD4C), ++ ++ SAVE_ITEM(S3C_VIDW00ADD0B0), ++ SAVE_ITEM(S3C_VIDW00ADD0B1), ++ SAVE_ITEM(S3C_VIDW01ADD0B0), ++ SAVE_ITEM(S3C_VIDW01ADD0B1), ++ SAVE_ITEM(S3C_VIDW02ADD0), ++ SAVE_ITEM(S3C_VIDW03ADD0), ++ SAVE_ITEM(S3C_VIDW04ADD0), ++ SAVE_ITEM(S3C_VIDW00ADD1B0), ++ SAVE_ITEM(S3C_VIDW00ADD1B1), ++ SAVE_ITEM(S3C_VIDW01ADD1B0), ++ SAVE_ITEM(S3C_VIDW01ADD1B1), ++ SAVE_ITEM(S3C_VIDW02ADD1), ++ SAVE_ITEM(S3C_VIDW03ADD1), ++ SAVE_ITEM(S3C_VIDW04ADD1), ++ SAVE_ITEM(S3C_VIDW00ADD2), ++ SAVE_ITEM(S3C_VIDW01ADD2), ++ SAVE_ITEM(S3C_VIDW02ADD2), ++ SAVE_ITEM(S3C_VIDW03ADD2), ++ SAVE_ITEM(S3C_VIDW04ADD2), ++ ++ SAVE_ITEM(S3C_VIDINTCON0), ++ SAVE_ITEM(S3C_VIDINTCON1), ++ SAVE_ITEM(S3C_W1KEYCON0), ++ SAVE_ITEM(S3C_W1KEYCON1), ++ SAVE_ITEM(S3C_W2KEYCON0), ++ SAVE_ITEM(S3C_W2KEYCON1), ++ ++ SAVE_ITEM(S3C_W3KEYCON0), ++ SAVE_ITEM(S3C_W3KEYCON1), ++ SAVE_ITEM(S3C_W4KEYCON0), ++ SAVE_ITEM(S3C_W4KEYCON1), ++ SAVE_ITEM(S3C_DITHMODE), ++ ++ SAVE_ITEM(S3C_WIN0MAP), ++ SAVE_ITEM(S3C_WIN1MAP), ++ SAVE_ITEM(S3C_WIN2MAP), ++ SAVE_ITEM(S3C_WIN3MAP), ++ SAVE_ITEM(S3C_WIN4MAP), ++ SAVE_ITEM(S3C_WPALCON), ++ ++ SAVE_ITEM(S3C_TRIGCON), ++ SAVE_ITEM(S3C_I80IFCONA0), ++ SAVE_ITEM(S3C_I80IFCONA1), ++ SAVE_ITEM(S3C_I80IFCONB0), ++ SAVE_ITEM(S3C_I80IFCONB1), ++ SAVE_ITEM(S3C_LDI_CMDCON0), ++ SAVE_ITEM(S3C_LDI_CMDCON1), ++ SAVE_ITEM(S3C_SIFCCON0), ++ SAVE_ITEM(S3C_SIFCCON1), ++ SAVE_ITEM(S3C_SIFCCON2), ++ ++ SAVE_ITEM(S3C_LDI_CMD0), ++ SAVE_ITEM(S3C_LDI_CMD1), ++ SAVE_ITEM(S3C_LDI_CMD2), ++ SAVE_ITEM(S3C_LDI_CMD3), ++ SAVE_ITEM(S3C_LDI_CMD4), ++ SAVE_ITEM(S3C_LDI_CMD5), ++ SAVE_ITEM(S3C_LDI_CMD6), ++ SAVE_ITEM(S3C_LDI_CMD7), ++ SAVE_ITEM(S3C_LDI_CMD8), ++ SAVE_ITEM(S3C_LDI_CMD9), ++ SAVE_ITEM(S3C_LDI_CMD10), ++ SAVE_ITEM(S3C_LDI_CMD11), ++ ++ SAVE_ITEM(S3C_W2PDATA01), ++ SAVE_ITEM(S3C_W2PDATA23), ++ SAVE_ITEM(S3C_W2PDATA45), ++ SAVE_ITEM(S3C_W2PDATA67), ++ SAVE_ITEM(S3C_W2PDATA89), ++ SAVE_ITEM(S3C_W2PDATAAB), ++ SAVE_ITEM(S3C_W2PDATACD), ++ SAVE_ITEM(S3C_W2PDATAEF), ++ SAVE_ITEM(S3C_W3PDATA01), ++ SAVE_ITEM(S3C_W3PDATA23), ++ SAVE_ITEM(S3C_W3PDATA45), ++ SAVE_ITEM(S3C_W3PDATA67), ++ SAVE_ITEM(S3C_W3PDATA89), ++ SAVE_ITEM(S3C_W3PDATAAB), ++ SAVE_ITEM(S3C_W3PDATACD), ++ SAVE_ITEM(S3C_W3PDATAEF), ++ SAVE_ITEM(S3C_W4PDATA01), ++ SAVE_ITEM(S3C_W4PDATA23), ++}; ++ ++/* ++ * Suspend ++ */ ++int s3cfb_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ struct fb_info *fbinfo = platform_get_drvdata(dev); ++ s3cfb_info_t *info = fbinfo->par; ++ ++ s3cfb_stop_lcd(); ++ s3c6410_pm_do_save(s3c_lcd_save, ARRAY_SIZE(s3c_lcd_save)); ++ ++ /* sleep before disabling the clock, we need to ensure ++ * the LCD DMA engine is not going to get back on the bus ++ * before the clock goes off again (bjd) */ ++ ++ msleep(1); ++ clk_disable(info->clk); ++ ++ return 0; ++} ++ ++/* ++ * Resume ++ */ ++int s3cfb_resume(struct platform_device *dev) ++{ ++ struct fb_info *fbinfo = platform_get_drvdata(dev); ++ s3cfb_info_t *info = fbinfo->par; ++ ++ clk_enable(info->clk); ++ s3c6410_pm_do_restore(s3c_lcd_save, ARRAY_SIZE(s3c_lcd_save)); ++ ++ s3cfb_set_gpio(); ++ s3cfb_start_lcd(); ++ ++ return 0; ++} ++ ++#else ++ ++int s3cfb_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ return 0; ++} ++ ++int s3cfb_resume(struct platform_device *dev) ++{ ++ return 0; ++} ++ ++#endif ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/video/samsung/s3cfb_fimd5x.c linux-2.6.28.6/drivers/video/samsung/s3cfb_fimd5x.c +--- linux-2.6.28/drivers/video/samsung/s3cfb_fimd5x.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/video/samsung/s3cfb_fimd5x.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,1521 @@ ++/* ++ * drivers/video/samsung/s3cfb_fimd5x.c ++ * ++ * $Id: s3cfb_fimd5x.c,v 1.2 2008/12/09 04:51:38 ihlee215 Exp $ ++ * ++ * Copyright (C) 2008 Jinsung Yang ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive for ++ * more details. ++ * ++ * S3C Frame Buffer Driver ++ * based on skeletonfb.c, sa1100fb.h, s3c2410fb.c ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#if defined(CONFIG_PM) ++#include ++#endif ++ ++#include "s3cfb.h" ++ ++s3cfb_fimd_info_t s3cfb_fimd = { ++ .vidcon0 = S3C_VIDCON0_INTERLACE_F_PROGRESSIVE | S3C_VIDCON0_VIDOUT_RGB_IF | S3C_VIDCON0_L1_DATA16_SUB_16_MODE | \ ++ S3C_VIDCON0_L0_DATA16_MAIN_16_MODE | S3C_VIDCON0_PNRMODE_RGB_P | \ ++ S3C_VIDCON0_CLKVALUP_ALWAYS | S3C_VIDCON0_CLKDIR_DIVIDED | S3C_VIDCON0_CLKSEL_F_HCLK | \ ++ S3C_VIDCON0_ENVID_DISABLE | S3C_VIDCON0_ENVID_F_DISABLE, ++ ++ .dithmode = (S3C_DITHMODE_RDITHPOS_5BIT | S3C_DITHMODE_GDITHPOS_6BIT | S3C_DITHMODE_BDITHPOS_5BIT ) & S3C_DITHMODE_DITHERING_DISABLE, ++ ++#if defined (CONFIG_FB_S3C_BPP_8) ++ .wincon0 = S3C_WINCONx_BYTSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_8BPP_PAL, ++ .wincon1 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, ++ .bpp = S3CFB_PIXEL_BPP_8, ++ .bytes_per_pixel = 1, ++ .wpalcon = S3C_WPALCON_W0PAL_16BIT, ++ ++#elif defined (CONFIG_FB_S3C_BPP_16) ++ .wincon0 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BUFSEL_1 | S3C_WINCONx_BUFAUTOEN_DISABLE | \ ++ S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE | \ ++ S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_ENWIN_F_DISABLE, ++ ++ .wincon1 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BUFSEL_0 | S3C_WINCONx_BUFAUTOEN_DISABLE | \ ++ S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE | \ ++ S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_BPPMODE_F_16BPP_565 | \ ++ S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE, ++ ++ .wincon2 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | \ ++ S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BURSTLEN_16WORD | \ ++ S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE, ++ ++ .wincon3 = S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE | \ ++ S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BLD_PIX_PLANE | \ ++ S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE, ++ ++ .wincon4 = S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE | \ ++ S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BLD_PIX_PLANE | ++ S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE, ++ ++ .bpp = S3CFB_PIXEL_BPP_16, ++ .bytes_per_pixel = 2, ++ .wpalcon = S3C_WPALCON_W0PAL_16BIT, ++ ++#elif defined (CONFIG_FB_S3C_BPP_24) ++ .wincon0 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888, ++ .wincon1 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, ++ .wincon2 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, ++ .wincon3 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, ++ .wincon4 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, ++ .bpp = S3CFB_PIXEL_BPP_24, ++ .bytes_per_pixel = 4, ++ .wpalcon = S3C_WPALCON_W0PAL_24BIT, ++#endif ++ ++ .vidosd1c = S3C_VIDOSDxC_ALPHA1_B(S3CFB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(S3CFB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_R(S3CFB_MAX_ALPHA_LEVEL), ++ .vidosd2c = S3C_VIDOSDxC_ALPHA1_B(S3CFB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(S3CFB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_R(S3CFB_MAX_ALPHA_LEVEL), ++ .vidosd3c = S3C_VIDOSDxC_ALPHA1_B(S3CFB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(S3CFB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_R(S3CFB_MAX_ALPHA_LEVEL), ++ .vidosd4c = S3C_VIDOSDxC_ALPHA1_B(S3CFB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(S3CFB_MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_R(S3CFB_MAX_ALPHA_LEVEL), ++ ++ .vidintcon0 = S3C_VIDINTCON0_FRAMESEL0_VSYNC | S3C_VIDINTCON0_FRAMESEL1_NONE | S3C_VIDINTCON0_INTFRMEN_DISABLE | \ ++ S3C_VIDINTCON0_FIFOSEL_WIN0 | S3C_VIDINTCON0_FIFOLEVEL_25 | S3C_VIDINTCON0_INTFIFOEN_DISABLE | S3C_VIDINTCON0_INTEN_ENABLE, ++ .vidintcon1 = 0, ++ ++ .xoffset = 0, ++ .yoffset = 0, ++ ++ .w1keycon0 = S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE | S3C_WxKEYCON0_COMPKEY(0x0), ++ .w1keycon1 = S3C_WxKEYCON1_COLVAL(0xffffff), ++ .w2keycon0 = S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE | S3C_WxKEYCON0_COMPKEY(0x0), ++ .w2keycon1 = S3C_WxKEYCON1_COLVAL(0xffffff), ++ .w3keycon0 = S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE | S3C_WxKEYCON0_COMPKEY(0x0), ++ .w3keycon1 = S3C_WxKEYCON1_COLVAL(0xffffff), ++ .w4keycon0 = S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE | S3C_WxKEYCON0_COMPKEY(0x0), ++ .w4keycon1 = S3C_WxKEYCON1_COLVAL(0xffffff), ++ ++ .sync = 0, ++ .cmap_static = 1, ++ ++ .vs_offset = S3CFB_DEFAULT_DISPLAY_OFFSET, ++ .brightness = S3CFB_DEFAULT_BRIGHTNESS, ++ .backlight_level = S3CFB_DEFAULT_BACKLIGHT_LEVEL, ++ .backlight_power = 1, ++ .lcd_power = 1, ++}; ++ ++#if defined(CONFIG_S3C6410_PWM) || defined(CONFIG_S5PC1XX_PWM) ++void s3cfb_set_brightness(int val) ++{ ++#if defined(CONFIG_S3C6410_PWM) ++ int channel = 1; /* must use channel-1 */ ++#elif defined(CONFIG_S5PC1XX_PWM) ++ int channel = 0; /* must use channel-0 */ ++#endif ++ ++ int usec = 0; /* don't care value */ ++ unsigned long tcnt = 1000; ++ unsigned long tcmp = 0; ++ ++ if (val < 0) ++ val = 0; ++ ++ if (val > S3CFB_MAX_BRIGHTNESS) ++ val = S3CFB_MAX_BRIGHTNESS; ++ ++ s3cfb_fimd.brightness = val; ++ tcmp = val * 50; ++ ++#if defined(CONFIG_S3C6410_PWM) ++ s3c6410_timer_setup(channel, usec, tcnt, tcmp); ++#elif defined(CONFIG_S5PC1XX_PWM) ++ s5pc100_timer_setup(channel, usec, tcnt, tcmp); ++#endif ++} ++#endif ++ ++#if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING) ++ ++static void s3cfb_change_buff(int req_win, int req_fb) ++{ ++ switch (req_win) { ++ case 0: ++ if (req_fb == 0) ++ s3cfb_fimd.wincon0 &= ~S3C_WINCONx_BUFSEL_MASK; ++ else ++ s3cfb_fimd.wincon0 |= S3C_WINCONx_BUFSEL_1; ++ ++ writel(s3cfb_fimd.wincon0 | S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON0); ++ break; ++ ++ case 1: ++ if (req_fb == 0) ++ s3cfb_fimd.wincon1 &= ~S3C_WINCONx_BUFSEL_MASK; ++ else ++ s3cfb_fimd.wincon1 |= S3C_WINCONx_BUFSEL_1; ++ ++ writel(s3cfb_fimd.wincon1 | S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON1); ++ break; ++ ++ default: ++ break; ++ } ++} ++ ++#endif ++ ++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN) ++static int s3cfb_set_vs_registers(int vs_cmd) ++{ ++ int page_width, offset; ++ int shift_value; ++ ++ page_width = s3cfb_fimd.xres * s3cfb_fimd.bytes_per_pixel; ++ offset = (s3cfb_fimd.xres_virtual - s3cfb_fimd.xres) * s3cfb_fimd.bytes_per_pixel; ++ ++ switch (vs_cmd){ ++ case S3CFB_VS_SET: ++ /* size of buffer */ ++ s3cfb_fimd.vidw00add2 = S3C_VIDWxxADD2_OFFSIZE_F(offset) | S3C_VIDWxxADD2_PAGEWIDTH_F(page_width); ++ writel(s3cfb_fimd.vidw00add2, S3C_VIDW00ADD2); ++ break; ++ ++ case S3CFB_VS_MOVE_LEFT: ++ if (s3cfb_fimd.xoffset < s3cfb_fimd.vs_offset) ++ shift_value = s3cfb_fimd.xoffset; ++ else ++ shift_value = s3cfb_fimd.vs_offset; ++ ++ s3cfb_fimd.xoffset -= shift_value; ++ ++ /* For buffer start address */ ++ s3cfb_fimd.vidw00add0b0 = s3cfb_fimd.vidw00add0b0 - (s3cfb_fimd.bytes_per_pixel * shift_value); ++ s3cfb_fimd.vidw00add0b1 = s3cfb_fimd.vidw00add0b1 - (s3cfb_fimd.bytes_per_pixel * shift_value); ++ break; ++ ++ case S3CFB_VS_MOVE_RIGHT: ++ if ((s3cfb_fimd.vs_info.v_width - (s3cfb_fimd.xoffset + s3cfb_fimd.vs_info.width)) < (s3cfb_fimd.vs_offset)) ++ shift_value = s3cfb_fimd.vs_info.v_width - (s3cfb_fimd.xoffset + s3cfb_fimd.vs_info.width); ++ else ++ shift_value = s3cfb_fimd.vs_offset; ++ ++ s3cfb_fimd.xoffset += shift_value; ++ ++ /* For buffer start address */ ++ s3cfb_fimd.vidw00add0b0 = s3cfb_fimd.vidw00add0b0 + (s3cfb_fimd.bytes_per_pixel * shift_value); ++ s3cfb_fimd.vidw00add0b1 = s3cfb_fimd.vidw00add0b1 + (s3cfb_fimd.bytes_per_pixel * shift_value); ++ break; ++ ++ case S3CFB_VS_MOVE_UP: ++ if (s3cfb_fimd.yoffset < s3cfb_fimd.vs_offset) ++ shift_value = s3cfb_fimd.yoffset; ++ else ++ shift_value = s3cfb_fimd.vs_offset; ++ ++ s3cfb_fimd.yoffset -= shift_value; ++ ++ /* For buffer start address */ ++ s3cfb_fimd.vidw00add0b0 = s3cfb_fimd.vidw00add0b0 - (s3cfb_fimd.xres_virtual * s3cfb_fimd.bytes_per_pixel * shift_value); ++ s3cfb_fimd.vidw00add0b1 = s3cfb_fimd.vidw00add0b1 - (s3cfb_fimd.xres_virtual * s3cfb_fimd.bytes_per_pixel * shift_value); ++ break; ++ ++ case S3CFB_VS_MOVE_DOWN: ++ if ((s3cfb_fimd.vs_info.v_height - (s3cfb_fimd.yoffset + s3cfb_fimd.vs_info.height)) < (s3cfb_fimd.vs_offset)) ++ shift_value = s3cfb_fimd.vs_info.v_height - (s3cfb_fimd.yoffset + s3cfb_fimd.vs_info.height); ++ else ++ shift_value = s3cfb_fimd.vs_offset; ++ ++ s3cfb_fimd.yoffset += shift_value; ++ ++ /* For buffer start address */ ++ s3cfb_fimd.vidw00add0b0 = s3cfb_fimd.vidw00add0b0 + (s3cfb_fimd.xres_virtual * s3cfb_fimd.bytes_per_pixel * shift_value); ++ s3cfb_fimd.vidw00add0b1 = s3cfb_fimd.vidw00add0b1 + (s3cfb_fimd.xres_virtual * s3cfb_fimd.bytes_per_pixel * shift_value); ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ /* End address */ ++ s3cfb_fimd.vidw00add1b0 = S3C_VIDWxxADD1_VBASEL_F(s3cfb_fimd.vidw00add0b0 + (page_width + offset) * (s3cfb_fimd.yres)); ++ s3cfb_fimd.vidw00add1b1 = S3C_VIDWxxADD1_VBASEL_F(s3cfb_fimd.vidw00add0b1 + (page_width + offset) * (s3cfb_fimd.yres)); ++ ++ writel(s3cfb_fimd.vidw00add0b0, S3C_VIDW00ADD0B0); ++ writel(s3cfb_fimd.vidw00add0b1, S3C_VIDW00ADD0B1); ++ writel(s3cfb_fimd.vidw00add1b0, S3C_VIDW00ADD1B0); ++ writel(s3cfb_fimd.vidw00add1b1, S3C_VIDW00ADD1B1); ++ ++ return 0; ++} ++#endif ++ ++void s3cfb_write_palette(s3cfb_info_t *fbi) ++{ ++ unsigned int i; ++ unsigned long ent; ++ unsigned int win_num = fbi->win_id; ++ ++ fbi->palette_ready = 0; ++ ++ writel((s3cfb_fimd.wpalcon | S3C_WPALCON_PALUPDATEEN), S3C_WPALCON); ++ ++ for (i = 0; i < 256; i++) { ++ if ((ent = fbi->palette_buffer[i]) == S3CFB_PALETTE_BUFF_CLEAR) ++ continue; ++ ++ writel(ent, S3C_TFTPAL0(i) + 0x400 * win_num); ++ ++ /* it seems the only way to know exactly ++ * if the palette wrote ok, is to check ++ * to see if the value verifies ok ++ */ ++ if (readl(S3C_TFTPAL0(i) + 0x400 * win_num) == ent) { ++ fbi->palette_buffer[i] = S3CFB_PALETTE_BUFF_CLEAR; ++ } else { ++ fbi->palette_ready = 1; /* retry */ ++ printk("Retry writing into the palette\n"); ++ } ++ } ++ ++ writel(s3cfb_fimd.wpalcon, S3C_WPALCON); ++} ++ ++irqreturn_t s3cfb_irq(int irqno, void *param) ++{ ++ unsigned long buffer_size = 0; ++ unsigned int i; ++ unsigned int buffer_page_offset, buffer_page_width; ++ unsigned int fb_start_address, fb_end_address; ++ ++ if (s3cfb_info[s3cfb_fimd.palette_win].palette_ready) ++ s3cfb_write_palette(&s3cfb_info[s3cfb_fimd.palette_win]); ++ ++ for (i = 0; i < CONFIG_FB_S3C_NUM; i++) { ++ if (s3cfb_info[i].next_fb_info_change_req) { ++ /* fb variable setting */ ++ s3cfb_info[i].fb.fix.smem_start = s3cfb_info[i].next_fb_info.phy_start_addr; ++ ++ s3cfb_info[i].fb.fix.line_length = s3cfb_info[i].next_fb_info.xres_virtual * ++ s3cfb_fimd.bytes_per_pixel; ++ ++ s3cfb_info[i].fb.fix.smem_len = s3cfb_info[i].next_fb_info.xres_virtual * ++ s3cfb_info[i].next_fb_info.yres_virtual * ++ s3cfb_fimd.bytes_per_pixel; ++ ++ s3cfb_info[i].fb.var.xres = s3cfb_info[i].next_fb_info.xres; ++ s3cfb_info[i].fb.var.yres = s3cfb_info[i].next_fb_info.yres; ++ s3cfb_info[i].fb.var.xres_virtual = s3cfb_info[i].next_fb_info.xres_virtual; ++ s3cfb_info[i].fb.var.yres_virtual= s3cfb_info[i].next_fb_info.yres_virtual; ++ s3cfb_info[i].fb.var.xoffset = s3cfb_info[i].next_fb_info.xoffset; ++ s3cfb_info[i].fb.var.yoffset = s3cfb_info[i].next_fb_info.yoffset; ++ ++ s3cfb_info[i].lcd_offset_x= s3cfb_info[i].next_fb_info.lcd_offset_x; ++ s3cfb_info[i].lcd_offset_y= s3cfb_info[i].next_fb_info.lcd_offset_y; ++ ++ ++ /* fb start / end address setting */ ++ fb_start_address = s3cfb_info[i].next_fb_info.phy_start_addr + ++ s3cfb_info[i].fb.fix.line_length * s3cfb_info[i].next_fb_info.yoffset + ++ s3cfb_info[i].next_fb_info.xoffset * s3cfb_fimd.bytes_per_pixel; ++ ++ fb_end_address = fb_start_address + s3cfb_info[i].fb.fix.line_length * ++ s3cfb_info[i].next_fb_info.yres; ++ ++ writel(fb_start_address, S3C_VIDW00ADD0B0 + 0x8 * i); ++ writel(S3C_VIDWxxADD1_VBASEL_F(fb_end_address), S3C_VIDW00ADD1B0 + 0x8 * i); ++ ++ ++ /* fb virtual / visible size setting */ ++ buffer_page_width = s3cfb_info[i].next_fb_info.xres * s3cfb_fimd.bytes_per_pixel; ++ ++ buffer_page_offset = (s3cfb_info[i].next_fb_info.xres_virtual - ++ s3cfb_info[i].next_fb_info.xres) * s3cfb_fimd.bytes_per_pixel; ++ ++ buffer_size = S3C_VIDWxxADD2_OFFSIZE_F(buffer_page_offset) | ++ (S3C_VIDWxxADD2_PAGEWIDTH_F(buffer_page_width)); ++ ++ writel(buffer_size, S3C_VIDW00ADD2 + 0x04 * i); ++ ++ /* LCD position setting */ ++ writel(S3C_VIDOSDxA_OSD_LTX_F(s3cfb_info[i].next_fb_info.lcd_offset_x) | ++ S3C_VIDOSDxA_OSD_LTY_F(s3cfb_info[i].next_fb_info.lcd_offset_y), S3C_VIDOSD0A+(0x10 * i)); ++ ++ writel(S3C_VIDOSDxB_OSD_RBX_F(s3cfb_info[i].next_fb_info.lcd_offset_x - 1 + s3cfb_info[i].next_fb_info.xres) | ++ S3C_VIDOSDxB_OSD_RBY_F(s3cfb_info[i].next_fb_info.lcd_offset_y - 1 + s3cfb_info[i].next_fb_info.yres), ++ S3C_VIDOSD0B + (0x10 * i)); ++ ++ ++ /* fb size setting */ ++ if (i == 0) ++ writel(S3C_VIDOSD0C_OSDSIZE(s3cfb_info[i].next_fb_info.xres * s3cfb_info[i].next_fb_info.yres), S3C_VIDOSD0C); ++ else if (i == 1) ++ writel(S3C_VIDOSD0C_OSDSIZE(s3cfb_info[i].next_fb_info.xres * s3cfb_info[i].next_fb_info.yres), S3C_VIDOSD1D); ++ else if (i == 2) ++ writel(S3C_VIDOSD0C_OSDSIZE(s3cfb_info[i].next_fb_info.xres * s3cfb_info[i].next_fb_info.yres), S3C_VIDOSD2D); ++ ++ s3cfb_info[i].next_fb_info_change_req = 0; ++ } ++ } ++ ++ /* for clearing the interrupt source */ ++ writel(readl(S3C_VIDINTCON1), S3C_VIDINTCON1); ++ ++ s3cfb_fimd.vsync_info.count++; ++ wake_up_interruptible(&s3cfb_fimd.vsync_info.wait_queue); ++ ++ return IRQ_HANDLED; ++} ++ ++static void s3cfb_check_line_count(void) ++{ ++ int timeout = 30 * 5300; ++ unsigned int cfg; ++ int i; ++ ++ i = 0; ++ do { ++ if (!(readl(S3C_VIDCON1) & 0x7ff0000)) ++ break; ++ i++; ++ } while (i < timeout); ++ ++ if (i == timeout) { ++ printk(KERN_WARNING "line count mismatch\n"); ++ ++ cfg = readl(S3C_VIDCON0); ++ cfg |= (S3C_VIDCON0_ENVID_F_ENABLE | S3C_VIDCON0_ENVID_ENABLE); ++ writel(cfg, S3C_VIDCON0); ++ } ++} ++ ++static void s3cfb_enable_local0(int in_yuv) ++{ ++ unsigned int value; ++ ++ s3cfb_fimd.wincon0 = readl(S3C_WINCON0); ++ s3cfb_fimd.wincon0 &= ~S3C_WINCONx_ENWIN_F_ENABLE; ++ writel(s3cfb_fimd.wincon0, S3C_WINCON0); ++ ++ s3cfb_fimd.wincon0 &= ~(S3C_WINCONx_ENLOCAL_MASK | S3C_WINCONx_INRGB_MASK | S3C_WINCONx_WSWP_ENABLE); ++ value = S3C_WINCONx_ENLOCAL | S3C_WINCONx_ENWIN_F_ENABLE; ++ ++ if (in_yuv) ++ value |= S3C_WINCONx_INRGB_YUV; ++ ++ writel(s3cfb_fimd.wincon0 | value, S3C_WINCON0); ++} ++ ++static void s3cfb_enable_local1(int in_yuv, int sel) ++{ ++ unsigned int value; ++ ++ s3cfb_fimd.wincon1 = readl(S3C_WINCON1); ++ s3cfb_fimd.wincon1 &= ~S3C_WINCONx_ENWIN_F_ENABLE; ++ writel(s3cfb_fimd.wincon1, S3C_WINCON1); ++ ++ s3cfb_fimd.wincon1 &= ~(S3C_WINCONx_ENLOCAL_MASK | S3C_WINCONx_INRGB_MASK); ++ s3cfb_fimd.wincon1 &= ~(S3C_WINCON1_LOCALSEL_MASK | S3C_WINCONx_WSWP_ENABLE); ++ value = sel | S3C_WINCONx_ENLOCAL | S3C_WINCONx_ENWIN_F_ENABLE; ++ ++ if (in_yuv) ++ value |= S3C_WINCONx_INRGB_YUV; ++ ++ writel(s3cfb_fimd.wincon1 | value, S3C_WINCON1); ++} ++ ++static void s3cfb_enable_local2(int in_yuv) ++{ ++ unsigned int value; ++ ++ s3cfb_fimd.wincon2 = readl(S3C_WINCON2); ++ s3cfb_fimd.wincon2 &= ~S3C_WINCONx_ENWIN_F_ENABLE; ++ writel(s3cfb_fimd.wincon2, S3C_WINCON2); ++ ++ s3cfb_fimd.wincon2 &= ~(S3C_WINCONx_ENLOCAL_MASK | S3C_WINCONx_INRGB_MASK | S3C_WINCONx_WSWP_ENABLE); ++ value = S3C_WINCONx_ENLOCAL | S3C_WINCONx_ENWIN_F_ENABLE; ++ ++ if (in_yuv) ++ value |= S3C_WINCONx_INRGB_YUV; ++ ++ writel(s3cfb_fimd.wincon2 | value, S3C_WINCON2); ++} ++ ++static void s3cfb_enable_dma0(void) ++{ ++ u32 value; ++ ++ s3cfb_fimd.wincon0 &= ~(S3C_WINCONx_ENLOCAL_MASK | S3C_WINCONx_INRGB_MASK); ++ value = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_WSWP_ENABLE | S3C_WINCONx_ENWIN_F_ENABLE; ++ ++ writel(s3cfb_fimd.wincon0 | value, S3C_WINCON0); ++} ++ ++static void s3cfb_enable_dma1(void) ++{ ++ u32 value; ++ ++ s3cfb_fimd.wincon1 &= ~(S3C_WINCONx_ENLOCAL_MASK | S3C_WINCONx_INRGB_MASK); ++ value = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_WSWP_ENABLE | S3C_WINCONx_ENWIN_F_ENABLE; ++ ++ writel(s3cfb_fimd.wincon1 | value, S3C_WINCON1); ++} ++ ++static void s3cfb_enable_dma2(void) ++{ ++ u32 value; ++ ++ s3cfb_fimd.wincon2 &= ~(S3C_WINCONx_ENLOCAL_MASK | S3C_WINCONx_INRGB_MASK); ++ value = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_WSWP_ENABLE | S3C_WINCONx_ENWIN_F_ENABLE; ++ ++ writel(s3cfb_fimd.wincon2 | value, S3C_WINCON2); ++} ++ ++void s3cfb_enable_local(int win, int in_yuv, int sel) ++{ ++ s3cfb_check_line_count(); ++ ++ switch (win) { ++ case 0: ++ s3cfb_enable_local0(in_yuv); ++ break; ++ ++ case 1: ++ s3cfb_enable_local1(in_yuv, sel); ++ break; ++ ++ case 2: ++ s3cfb_enable_local2(in_yuv); ++ break; ++ ++ default: ++ break; ++ } ++} ++ ++void s3cfb_enable_dma(int win) ++{ ++ s3cfb_stop_lcd(); ++ ++ switch (win) { ++ case 0: ++ s3cfb_enable_dma0(); ++ break; ++ ++ case 1: ++ s3cfb_enable_dma1(); ++ break; ++ ++ case 2: ++ s3cfb_enable_dma2(); ++ break; ++ ++ default: ++ break; ++ } ++ ++ s3cfb_start_lcd(); ++} ++ ++EXPORT_SYMBOL(s3cfb_enable_local); ++EXPORT_SYMBOL(s3cfb_enable_dma); ++ ++int s3cfb_init_registers(s3cfb_info_t *fbi) ++{ ++ struct clk *lcd_clock; ++ struct fb_var_screeninfo *var = &fbi->fb.var; ++ unsigned long flags = 0, page_width = 0, offset = 0; ++ unsigned long video_phy_temp_f1 = fbi->screen_dma_f1; ++ unsigned long video_phy_temp_f2 = fbi->screen_dma_f2; ++ int win_num = fbi->win_id; ++ ++ /* Initialise LCD with values from hare */ ++ local_irq_save(flags); ++ ++ page_width = var->xres * s3cfb_fimd.bytes_per_pixel; ++ offset = (var->xres_virtual - var->xres) * s3cfb_fimd.bytes_per_pixel; ++ ++ if (win_num == 0) { ++ s3cfb_fimd.vidcon0 = s3cfb_fimd.vidcon0 & ~(S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE); ++ writel(s3cfb_fimd.vidcon0, S3C_VIDCON0); ++ ++ lcd_clock = clk_get(NULL, "lcd"); ++ s3cfb_fimd.vidcon0 |= S3C_VIDCON0_CLKVAL_F((int) ((clk_get_rate(lcd_clock) / s3cfb_fimd.pixclock) - 1)); ++ ++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN) ++ offset = 0; ++ s3cfb_fimd.vidw00add0b0 = video_phy_temp_f1; ++ s3cfb_fimd.vidw00add0b1 = video_phy_temp_f2; ++ s3cfb_fimd.vidw00add1b0 = S3C_VIDWxxADD1_VBASEL_F((unsigned long) video_phy_temp_f1 + (page_width + offset) * (var->yres)); ++ s3cfb_fimd.vidw00add1b1 = S3C_VIDWxxADD1_VBASEL_F((unsigned long) video_phy_temp_f2 + (page_width + offset) * (var->yres)); ++#endif ++ } ++ ++ writel(video_phy_temp_f1, S3C_VIDW00ADD0B0 + (0x08 * win_num)); ++ writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) video_phy_temp_f1 + (page_width + offset) * (var->yres)), S3C_VIDW00ADD1B0 + (0x08 * win_num)); ++ writel(S3C_VIDWxxADD2_OFFSIZE_F(offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(page_width)), S3C_VIDW00ADD2 + (0x04 * win_num)); ++ ++ if (win_num < 2) { ++ writel(video_phy_temp_f2, S3C_VIDW00ADD0B1 + (0x08 * win_num)); ++ writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) video_phy_temp_f2 + (page_width + offset) * (var->yres)), S3C_VIDW00ADD1B1 + (0x08 * win_num)); ++ } ++ ++ #if defined(CONFIG_CPU_S5P6440) ++ #if defined(CONFIG_FB_S3C_BPP_24) ++ s3cfb_fimd.wincon0|= 0x8000; ++ s3cfb_fimd.wincon1|= 0x8000; ++ s3cfb_fimd.wincon2|= 0x8000; ++ s3cfb_fimd.wincon3|= 0x8000; ++ s3cfb_fimd.wincon4|= 0x8000; ++ #endif ++ s3cfb_fimd.vidcon0 = 0x153; ++ #endif ++ switch (win_num) { ++ case 0: ++ writel(s3cfb_fimd.wincon0, S3C_WINCON0); ++ writel(s3cfb_fimd.vidcon0, S3C_VIDCON0); ++ writel(s3cfb_fimd.vidcon1, S3C_VIDCON1); ++ writel(s3cfb_fimd.vidtcon0, S3C_VIDTCON0); ++ writel(s3cfb_fimd.vidtcon1, S3C_VIDTCON1); ++ writel(s3cfb_fimd.vidtcon2, S3C_VIDTCON2); ++ writel(s3cfb_fimd.dithmode, S3C_DITHMODE); ++ writel(s3cfb_fimd.vidintcon0, S3C_VIDINTCON0); ++ writel(s3cfb_fimd.vidintcon1, S3C_VIDINTCON1); ++ writel(s3cfb_fimd.vidosd0a, S3C_VIDOSD0A); ++ writel(s3cfb_fimd.vidosd0b, S3C_VIDOSD0B); ++ writel(s3cfb_fimd.vidosd0c, S3C_VIDOSD0C); ++ writel(s3cfb_fimd.wpalcon, S3C_WPALCON); ++ ++ s3cfb_onoff_win(fbi, ON); ++ break; ++ ++ case 1: ++ writel(s3cfb_fimd.wincon1, S3C_WINCON1); ++ writel(s3cfb_fimd.vidosd1a, S3C_VIDOSD1A); ++ writel(s3cfb_fimd.vidosd1b, S3C_VIDOSD1B); ++ writel(s3cfb_fimd.vidosd1c, S3C_VIDOSD1C); ++ writel(s3cfb_fimd.vidosd1d, S3C_VIDOSD1D); ++ writel(s3cfb_fimd.wpalcon, S3C_WPALCON); ++ ++ s3cfb_onoff_win(fbi, OFF); ++ break; ++ ++ case 2: ++ writel(s3cfb_fimd.wincon2, S3C_WINCON2); ++ writel(s3cfb_fimd.vidosd2a, S3C_VIDOSD2A); ++ writel(s3cfb_fimd.vidosd2b, S3C_VIDOSD2B); ++ writel(s3cfb_fimd.vidosd2c, S3C_VIDOSD2C); ++ writel(s3cfb_fimd.vidosd2d, S3C_VIDOSD2D); ++ writel(s3cfb_fimd.wpalcon, S3C_WPALCON); ++ ++ s3cfb_onoff_win(fbi, OFF); ++ break; ++ ++ case 3: ++ writel(s3cfb_fimd.wincon3, S3C_WINCON3); ++ writel(s3cfb_fimd.vidosd3a, S3C_VIDOSD3A); ++ writel(s3cfb_fimd.vidosd3b, S3C_VIDOSD3B); ++ writel(s3cfb_fimd.vidosd3c, S3C_VIDOSD3C); ++ writel(s3cfb_fimd.wpalcon, S3C_WPALCON); ++ ++ s3cfb_onoff_win(fbi, OFF); ++ break; ++ ++ case 4: ++ writel(s3cfb_fimd.wincon4, S3C_WINCON4); ++ writel(s3cfb_fimd.vidosd4a, S3C_VIDOSD4A); ++ writel(s3cfb_fimd.vidosd4b, S3C_VIDOSD4B); ++ writel(s3cfb_fimd.vidosd4c, S3C_VIDOSD4C); ++ writel(s3cfb_fimd.wpalcon, S3C_WPALCON); ++ ++ s3cfb_onoff_win(fbi, OFF); ++ break; ++ } ++ ++ local_irq_restore(flags); ++ ++ return 0; ++ } ++ ++void s3cfb_activate_var(s3cfb_info_t *fbi, struct fb_var_screeninfo *var) ++{ ++ DPRINTK("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel); ++ ++ switch (var->bits_per_pixel) { ++ case 8: ++ s3cfb_fimd.wincon0 = S3C_WINCONx_BYTSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_8BPP_PAL; ++ s3cfb_fimd.wincon1 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.wincon2 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.wincon3 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.wincon4 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.bpp = S3CFB_PIXEL_BPP_8; ++ s3cfb_fimd.bytes_per_pixel = 1; ++ s3cfb_fimd.wpalcon = S3C_WPALCON_W0PAL_16BIT; ++ break; ++ ++ case 16: ++ s3cfb_fimd.wincon0 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565; ++ s3cfb_fimd.wincon1 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.wincon2 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.wincon3 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.wincon4 = S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.bpp = S3CFB_PIXEL_BPP_16; ++ s3cfb_fimd.bytes_per_pixel = 2; ++ break; ++ ++ case 24: ++ s3cfb_fimd.wincon0 = S3C_WINCONx_WSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888; ++ s3cfb_fimd.wincon1 = S3C_WINCONx_WSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.wincon2 = S3C_WINCONx_WSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.wincon3 = S3C_WINCONx_WSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.wincon4 = S3C_WINCONx_WSWP_ENABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; ++ s3cfb_fimd.bpp = S3CFB_PIXEL_BPP_24; ++ s3cfb_fimd.bytes_per_pixel = 4; ++ break; ++ ++ case 32: ++ s3cfb_fimd.bytes_per_pixel = 4; ++ break; ++ } ++ ++ #if defined(CONFIG_CPU_S5P6440) ++ #if defined(CONFIG_FB_S3C_BPP_24) ++ s3cfb_fimd.wincon0|= 0x8000; ++ s3cfb_fimd.wincon1|= 0x8000; ++ s3cfb_fimd.wincon2|= 0x8000; ++ s3cfb_fimd.wincon3|= 0x8000; ++ s3cfb_fimd.wincon4|= 0x8000; ++ #endif ++ s3cfb_fimd.vidcon0 = 0x153; ++ #endif ++ ++ /* write new registers */ ++ writel(s3cfb_fimd.wincon0, S3C_WINCON0); ++ writel(s3cfb_fimd.wincon1, S3C_WINCON1); ++ writel(s3cfb_fimd.wincon2, S3C_WINCON2); ++ writel(s3cfb_fimd.wincon3, S3C_WINCON3); ++ writel(s3cfb_fimd.wincon4, S3C_WINCON4); ++ writel(s3cfb_fimd.wpalcon, S3C_WPALCON); ++ writel(s3cfb_fimd.wincon0 | S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON0); ++ writel(s3cfb_fimd.vidcon0 | S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE, S3C_VIDCON0); ++} ++ ++/* JJNAHM comment. ++ * We had some problems related to frame buffer address. ++ * We used 2 frame buffers (FB0 and FB1) and GTK used FB1. ++ * When GTK launched, GTK set FB0's address to FB1's address. ++ * (GTK calls s3c_fb_pan_display() and then it calls this s3c_fb_set_lcdaddr()) ++ * Even though fbi->win_id is not 0, above original codes set ONLY FB0's address. ++ * So, I modified the codes like below. ++ * It works by fbi->win_id value. ++ * Below codes are not verified yet ++ * and there are nothing about Double buffering features ++ */ ++void s3cfb_set_fb_addr(s3cfb_info_t *fbi) ++{ ++ unsigned long video_phy_temp_f1 = fbi->screen_dma_f1; ++ unsigned long start_address, end_address; ++ unsigned int start; ++ ++ start = fbi->fb.fix.line_length * fbi->fb.var.yoffset; ++ ++ /* for buffer start address and end address */ ++ start_address = video_phy_temp_f1 + start; ++ end_address = start_address + (fbi->fb.fix.line_length * fbi->fb.var.yres); ++ ++ switch (fbi->win_id) ++ { ++ case 0: ++ s3cfb_fimd.vidw00add0b0 = start_address; ++ s3cfb_fimd.vidw00add1b0 = end_address; ++ __raw_writel(s3cfb_fimd.vidw00add0b0, S3C_VIDW00ADD0B0); ++ __raw_writel(s3cfb_fimd.vidw00add1b0, S3C_VIDW00ADD1B0); ++ break; ++ ++ case 1: ++ s3cfb_fimd.vidw01add0b0 = start_address; ++ s3cfb_fimd.vidw01add1b0 = end_address; ++ __raw_writel(s3cfb_fimd.vidw01add0b0, S3C_VIDW01ADD0B0); ++ __raw_writel(s3cfb_fimd.vidw01add1b0, S3C_VIDW01ADD1B0); ++ break; ++ ++ case 2: ++ s3cfb_fimd.vidw02add0 = start_address; ++ s3cfb_fimd.vidw02add1 = end_address; ++ __raw_writel(s3cfb_fimd.vidw02add0, S3C_VIDW02ADD0); ++ __raw_writel(s3cfb_fimd.vidw02add1, S3C_VIDW02ADD1); ++ break; ++ ++ case 3: ++ s3cfb_fimd.vidw03add0 = start_address; ++ s3cfb_fimd.vidw03add1 = end_address; ++ __raw_writel(s3cfb_fimd.vidw03add0, S3C_VIDW03ADD0); ++ __raw_writel(s3cfb_fimd.vidw03add1, S3C_VIDW03ADD1); ++ break; ++ ++ case 4: ++ s3cfb_fimd.vidw04add0 = start_address; ++ s3cfb_fimd.vidw04add1 = end_address; ++ __raw_writel(s3cfb_fimd.vidw04add0, S3C_VIDW04ADD0); ++ __raw_writel(s3cfb_fimd.vidw04add1, S3C_VIDW04ADD1); ++ break; ++ } ++} ++ ++static int s3cfb_set_alpha_level(s3cfb_info_t *fbi, unsigned int level, unsigned int alpha_index) ++{ ++ unsigned long alpha_val; ++ int win_num = fbi->win_id; ++ ++ if (win_num == 0) { ++ printk("WIN0 do not support alpha blending.\n"); ++ return -1; ++ } ++ ++ alpha_val = readl(S3C_VIDOSD0C+(0x10 * win_num)); ++ ++ if (alpha_index == 0) { ++ alpha_val &= ~(S3C_VIDOSDxC_ALPHA0_B(0xf) | S3C_VIDOSDxC_ALPHA0_G(0xf) | S3C_VIDOSDxC_ALPHA0_R(0xf)); ++ alpha_val |= S3C_VIDOSDxC_ALPHA0_B(level) | S3C_VIDOSDxC_ALPHA0_G(level) | S3C_VIDOSDxC_ALPHA0_R(level); ++ } else { ++ alpha_val &= ~(S3C_VIDOSDxC_ALPHA1_B(0xf) | S3C_VIDOSDxC_ALPHA1_G(0xf) | S3C_VIDOSDxC_ALPHA1_R(0xf)); ++ alpha_val |= S3C_VIDOSDxC_ALPHA1_B(level) | S3C_VIDOSDxC_ALPHA1_G(level) | S3C_VIDOSDxC_ALPHA1_R(level); ++ } ++ ++ writel(alpha_val, S3C_VIDOSD0C + (0x10 * win_num)); ++ ++ return 0; ++} ++ ++int s3cfb_set_alpha_mode(s3cfb_info_t *fbi, int mode) ++{ ++ unsigned long alpha_mode; ++ int win_num = fbi->win_id; ++ ++ if (win_num == 0) { ++ printk("WIN0 do not support alpha blending.\n"); ++ return -1; ++ } ++ ++ alpha_mode = readl(S3C_WINCON0 + (0x04 * win_num)); ++ alpha_mode &= ~(S3C_WINCONx_BLD_PIX_PIXEL | S3C_WINCONx_ALPHA_SEL_1); ++ ++ switch (mode) { ++ case S3CFB_ALPHA_MODE_PLANE: /* Plane Blending */ ++ writel(alpha_mode | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, S3C_WINCON0 + (0x04 * win_num)); ++ break; ++ ++ case S3CFB_ALPHA_MODE_PIXEL: /* Pixel Blending & chroma(color) key */ ++ writel(alpha_mode | S3C_WINCONx_BLD_PIX_PIXEL | S3C_WINCONx_ALPHA_SEL_0, S3C_WINCON0 + (0x04 * win_num)); ++ break; ++ } ++ ++ return 0; ++} ++ ++int s3cfb_set_win_position(s3cfb_info_t *fbi, int left_x, int top_y, int width, int height) ++{ ++ struct fb_var_screeninfo *var= &fbi->fb.var; ++ int win_num = fbi->win_id; ++ ++ writel(S3C_VIDOSDxA_OSD_LTX_F(left_x) | S3C_VIDOSDxA_OSD_LTY_F(top_y), S3C_VIDOSD0A + (0x10 * win_num)); ++ writel(S3C_VIDOSDxB_OSD_RBX_F(width - 1 + left_x) | S3C_VIDOSDxB_OSD_RBY_F(height - 1 + top_y), S3C_VIDOSD0B + (0x10 * win_num)); ++ ++ var->xoffset = left_x; ++ var->yoffset = top_y; ++ ++ return 0; ++} ++ ++int s3cfb_set_win_size(s3cfb_info_t *fbi, int width, int height) ++{ ++ struct fb_var_screeninfo *var= &fbi->fb.var; ++ int win_num = fbi->win_id; ++ ++ if (win_num == 0) ++ writel(S3C_VIDOSD0C_OSDSIZE(width * height), S3C_VIDOSD0C); ++ ++ else if (win_num == 1) ++ writel(S3C_VIDOSD0C_OSDSIZE(width * height), S3C_VIDOSD1D); ++ ++ else if (win_num == 2) ++ writel(S3C_VIDOSD0C_OSDSIZE(width * height), S3C_VIDOSD2D); ++ ++ var->xres = width; ++ var->yres = height; ++ var->xres_virtual = width; ++ var->yres_virtual = height; ++ ++ return 0; ++} ++ ++int s3cfb_set_fb_size(s3cfb_info_t *fbi) ++{ ++ struct fb_var_screeninfo *var= &fbi->fb.var; ++ int win_num = fbi->win_id; ++ unsigned long offset = 0; ++ unsigned long page_width = 0; ++ unsigned long fb_size = 0; ++ ++ page_width = var->xres * s3cfb_fimd.bytes_per_pixel; ++ offset = (var->xres_virtual - var->xres) * s3cfb_fimd.bytes_per_pixel; ++ ++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN) ++ if (win_num == 0) ++ offset=0; ++#endif ++ ++ writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) readl(S3C_VIDW00ADD0B0 + (0x08 * win_num)) + (page_width + offset) * (var->yres)), S3C_VIDW00ADD1B0 + (0x08 * win_num)); ++ ++ if (win_num == 1) ++ writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) readl(S3C_VIDW00ADD0B1 + (0x08 * win_num)) + (page_width + offset) * (var->yres)), S3C_VIDW00ADD1B1 + (0x08 * win_num)); ++ ++ /* size of frame buffer */ ++ fb_size = S3C_VIDWxxADD2_OFFSIZE_F(offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(page_width)); ++ ++ writel(fb_size, S3C_VIDW00ADD2 + (0x04 * win_num)); ++ ++ return 0; ++} ++ ++void s3cfb_set_output_path(int out) ++{ ++ unsigned int tmp; ++ ++ tmp = readl(S3C_VIDCON0); ++ ++ /* if output mode is LCD mode, Scan mode always should be progressive mode */ ++ if (out == S3CFB_OUTPUT_TV) ++ tmp &= ~S3C_VIDCON0_INTERLACE_F_MASK; ++ ++ tmp &= ~S3C_VIDCON0_VIDOUT_MASK; ++ tmp |= S3C_VIDCON0_VIDOUT(out); ++ ++ writel(tmp, S3C_VIDCON0); ++} ++ ++EXPORT_SYMBOL(s3cfb_set_output_path); ++ ++void s3cfb_enable_rgbport(int on) ++{ ++ if (on) ++ writel(S3C_VIDCON2_ORGYUV_CBCRY | S3C_VIDCON2_YUVORD_CRCB, S3C_VIDCON2); ++ else ++ writel(0, S3C_VIDCON2); ++} ++ ++EXPORT_SYMBOL(s3cfb_enable_rgbport); ++ ++int s3cfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) ++{ ++ s3cfb_info_t *fbi = container_of(info, s3cfb_info_t, fb); ++ s3cfb_win_info_t win_info; ++ s3cfb_color_key_info_t colkey_info; ++ s3cfb_color_val_info_t colval_info; ++ s3cfb_dma_info_t dma_info; ++ s3cfb_next_info_t next_fb_info; ++ struct fb_var_screeninfo *var= &fbi->fb.var; ++ unsigned int crt, alpha_level, alpha_mode; ++ ++/* should be fixed for c100 */ ++#if defined(CONFIG_S3C6410_PWM) || defined(CONFIG_S5PC1XX_PWM) ++ int brightness; ++#endif ++ ++#if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING) ++ unsigned int f_num_val; ++#endif ++ ++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN) ++ s3cfb_vs_info_t vs_info; ++#endif ++ ++ switch(cmd){ ++ case S3CFB_GET_INFO: ++ dma_info.map_dma_f1 = fbi->map_dma_f1; ++ dma_info.map_dma_f2 = fbi->map_dma_f2; ++ ++ if(copy_to_user((void *) arg, (const void *) &dma_info, sizeof(s3cfb_dma_info_t))) ++ return -EFAULT; ++ break; ++ ++ case S3CFB_OSD_SET_INFO: ++ if (copy_from_user(&win_info, (s3cfb_win_info_t *) arg, sizeof(s3cfb_win_info_t))) ++ return -EFAULT; ++ ++ s3cfb_init_win(fbi, win_info.bpp, win_info.left_x, win_info.top_y, win_info.width, win_info.height, OFF); ++ break; ++ ++ case S3CFB_OSD_START: ++ s3cfb_onoff_win(fbi, ON); ++ break; ++ ++ case S3CFB_OSD_STOP: ++ s3cfb_onoff_win(fbi, OFF); ++ break; ++ ++ case S3CFB_OSD_ALPHA_UP: ++ alpha_level = readl(S3C_VIDOSD0C + (0x10 * fbi->win_id)) & 0xf; ++ ++ if (alpha_level < S3CFB_MAX_ALPHA_LEVEL) ++ alpha_level++; ++ ++ s3cfb_set_alpha_level(fbi, alpha_level, 1); ++ break; ++ ++ case S3CFB_OSD_ALPHA_DOWN: ++ alpha_level = readl(S3C_VIDOSD0C + (0x10 * fbi->win_id)) & 0xf; ++ ++ if (alpha_level > 0) ++ alpha_level--; ++ ++ s3cfb_set_alpha_level(fbi, alpha_level, 1); ++ break; ++ ++ case S3CFB_OSD_ALPHA0_SET: ++ alpha_level = (unsigned int) arg; ++ ++ if (alpha_level > S3CFB_MAX_ALPHA_LEVEL) ++ alpha_level = S3CFB_MAX_ALPHA_LEVEL; ++ ++ s3cfb_set_alpha_level(fbi, alpha_level, 0); ++ break; ++ ++ case S3CFB_OSD_ALPHA1_SET: ++ alpha_level = (unsigned int) arg; ++ ++ if (alpha_level > S3CFB_MAX_ALPHA_LEVEL) ++ alpha_level = S3CFB_MAX_ALPHA_LEVEL; ++ ++ s3cfb_set_alpha_level(fbi, alpha_level, 1); ++ break; ++ ++ case S3CFB_OSD_ALPHA_MODE: ++ alpha_mode = (unsigned int) arg; ++ s3cfb_set_alpha_mode(fbi, alpha_mode); ++ break; ++ ++ case S3CFB_OSD_MOVE_LEFT: ++ if (var->xoffset > 0) ++ var->xoffset--; ++ ++ s3cfb_set_win_position(fbi, var->xoffset, var->yoffset, var->xres, var->yres); ++ break; ++ ++ case S3CFB_OSD_MOVE_RIGHT: ++ if (var->xoffset < (s3cfb_fimd.width - var->xres)) ++ var->xoffset++; ++ ++ s3cfb_set_win_position(fbi, var->xoffset, var->yoffset, var->xres, var->yres); ++ break; ++ ++ case S3CFB_OSD_MOVE_UP: ++ if (var->yoffset > 0) ++ var->yoffset--; ++ ++ s3cfb_set_win_position(fbi, var->xoffset, var->yoffset, var->xres, var->yres); ++ break; ++ ++ case S3CFB_OSD_MOVE_DOWN: ++ if (var->yoffset < (s3cfb_fimd.height - var->yres)) ++ var->yoffset++; ++ ++ s3cfb_set_win_position(fbi, var->xoffset, var->yoffset, var->xres, var->yres); ++ break; ++ ++ case FBIO_WAITFORVSYNC: ++ if (get_user(crt, (unsigned int __user *)arg)) ++ return -EFAULT; ++ ++ return s3cfb_wait_for_vsync(); ++ ++ case S3CFB_COLOR_KEY_START: ++ s3cfb_onoff_color_key(fbi, ON); ++ break; ++ ++ case S3CFB_COLOR_KEY_STOP: ++ s3cfb_onoff_color_key(fbi, OFF); ++ break; ++ ++ case S3CFB_COLOR_KEY_ALPHA_START: ++ s3cfb_onoff_color_key_alpha(fbi, ON); ++ break; ++ ++ case S3CFB_COLOR_KEY_ALPHA_STOP: ++ s3cfb_onoff_color_key_alpha(fbi, OFF); ++ break; ++ ++ case S3CFB_COLOR_KEY_SET_INFO: ++ if (copy_from_user(&colkey_info, (s3cfb_color_val_info_t *) arg, sizeof(s3cfb_color_val_info_t))) ++ return -EFAULT; ++ ++ s3cfb_set_color_key_registers(fbi, colkey_info); ++ break; ++ ++ case S3CFB_COLOR_KEY_VALUE: ++ if (copy_from_user(&colval_info, (s3cfb_color_val_info_t *) arg, sizeof(s3cfb_color_val_info_t))) ++ return -EFAULT; ++ ++ s3cfb_set_color_value(fbi, colval_info); ++ break; ++ ++ case S3CFB_SET_VSYNC_INT: ++ s3cfb_fimd.vidintcon0 &= ~S3C_VIDINTCON0_FRAMESEL0_MASK; ++ s3cfb_fimd.vidintcon0 |= S3C_VIDINTCON0_FRAMESEL0_VSYNC; ++ ++ if (arg) ++ s3cfb_fimd.vidintcon0 |= S3C_VIDINTCON0_INTFRMEN_ENABLE; ++ else ++ s3cfb_fimd.vidintcon0 &= ~S3C_VIDINTCON0_INTFRMEN_ENABLE; ++ ++ writel(s3cfb_fimd.vidintcon0, S3C_VIDINTCON0); ++ break; ++ ++ case S3CFB_SET_NEXT_FB_INFO: ++ if (copy_from_user(&next_fb_info, (s3cfb_next_info_t *) arg, sizeof(s3cfb_next_info_t))) ++ return -EFAULT; ++ ++ /* check arguments */ ++ if ((next_fb_info.xres + next_fb_info.xoffset) > next_fb_info.xres_virtual || ++ (next_fb_info.yres + next_fb_info.yoffset) > next_fb_info.yres_virtual || ++ (next_fb_info.xres + next_fb_info.lcd_offset_x ) > s3cfb_fimd.width || ++ (next_fb_info.yres + next_fb_info.lcd_offset_y ) > s3cfb_fimd.height) ++ return -EINVAL; ++ ++ fbi->next_fb_info = next_fb_info; ++ fbi->next_fb_info_change_req = 1; ++ break; ++ ++ case S3CFB_GET_CURR_FB_INFO: ++ next_fb_info.phy_start_addr = fbi->fb.fix.smem_start; ++ next_fb_info.xres = fbi->fb.var.xres; ++ next_fb_info.yres = fbi->fb.var.yres; ++ next_fb_info.xres_virtual = fbi->fb.var.xres_virtual; ++ next_fb_info.yres_virtual = fbi->fb.var.yres_virtual; ++ next_fb_info.xoffset = fbi->fb.var.xoffset; ++ next_fb_info.yoffset = fbi->fb.var.yoffset; ++ next_fb_info.lcd_offset_x = fbi->lcd_offset_x; ++ next_fb_info.lcd_offset_y = fbi->lcd_offset_y; ++ ++ if (copy_to_user((void *)arg, (s3cfb_next_info_t *) &next_fb_info, sizeof(s3cfb_next_info_t))) ++ return -EFAULT; ++ break; ++ ++ case S3CFB_GET_BRIGHTNESS: ++ if (copy_to_user((void *)arg, (const void *) &s3cfb_fimd.brightness, sizeof(int))) ++ return -EFAULT; ++ break; ++ ++/* should be fixed for c100 */ ++#if defined(CONFIG_S3C6410_PWM) || defined(CONFIG_S5PC1XX_PWM) ++ case S3CFB_SET_BRIGHTNESS: ++ if (copy_from_user(&brightness, (int *) arg, sizeof(int))) ++ return -EFAULT; ++ ++ s3cfb_set_brightness(brightness); ++ break; ++#endif ++ ++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN) ++ case S3CFB_VS_START: ++ s3cfb_fimd.wincon0 &= ~(S3C_WINCONx_ENWIN_F_ENABLE); ++ writel(s3cfb_fimd.wincon0 | S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON0); ++ ++ fbi->fb.var.xoffset = s3cfb_fimd.xoffset; ++ fbi->fb.var.yoffset = s3cfb_fimd.yoffset; ++ break; ++ ++ case S3CFB_VS_STOP: ++ s3cfb_fimd.vidw00add0b0 = fbi->screen_dma_f1; ++ s3cfb_fimd.vidw00add0b1 = fbi->screen_dma_f2; ++ fbi->fb.var.xoffset = 0; ++ fbi->fb.var.yoffset = 0; ++ ++ writel(s3cfb_fimd.vidw00add0b0, S3C_VIDW00ADD0B0); ++ writel(s3cfb_fimd.vidw00add0b1, S3C_VIDW00ADD0B1); ++ ++ break; ++ ++ case S3CFB_VS_SET_INFO: ++ if (copy_from_user(&vs_info, (s3cfb_vs_info_t *) arg, sizeof(s3cfb_vs_info_t))) ++ return -EFAULT; ++ ++ if (s3cfb_set_vs_info(vs_info)) { ++ printk("Error S3CFB_VS_SET_INFO\n"); ++ return -EINVAL; ++ } ++ ++ s3cfb_set_vs_registers(S3CFB_VS_SET); ++ ++ fbi->fb.var.xoffset = s3cfb_fimd.xoffset; ++ fbi->fb.var.yoffset = s3cfb_fimd.yoffset; ++ break; ++ ++ case S3CFB_VS_MOVE: ++ s3cfb_set_vs_registers(arg); ++ ++ fbi->fb.var.xoffset = s3cfb_fimd.xoffset; ++ fbi->fb.var.yoffset = s3cfb_fimd.yoffset; ++ break; ++#endif ++ ++#if defined(CONFIG_FB_S3C_DOUBLE_BUFFERING) ++ case S3CFB_GET_NUM: ++ if (copy_from_user((void *)&f_num_val, (const void *)arg, sizeof(u_int))) ++ return -EFAULT; ++ ++ if (copy_to_user((void *)arg, (const void *) &f_num_val, sizeof(u_int))) ++ return -EFAULT; ++ ++ break; ++ ++ case S3CFB_CHANGE_REQ: ++ s3cfb_change_buff(0, (int) arg); ++ break; ++#endif ++ ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++void s3cfb_pre_init(void) ++{ ++ /* initialize the fimd specific */ ++ s3cfb_fimd.vidintcon0 &= ~S3C_VIDINTCON0_FRAMESEL0_MASK; ++ s3cfb_fimd.vidintcon0 |= S3C_VIDINTCON0_FRAMESEL0_VSYNC; ++ s3cfb_fimd.vidintcon0 |= S3C_VIDINTCON0_INTFRMEN_ENABLE; ++ ++ writel(s3cfb_fimd.vidintcon0, S3C_VIDINTCON0); ++} ++ ++#if defined(CONFIG_CPU_S5PC100) ++int s3cfb_set_gpio(void) ++{ ++ int i, err; ++ ++ /* LCD_HSYNC, LCD_VSYNC, LCD_VDEN, LCD_VCLK, VD[23:0] */ ++ for (i = 0; i < 8; i++) ++ s3c_gpio_cfgpin(S5PC1XX_GPF0(i), S3C_GPIO_SFN(2)); ++ ++ for (i = 0; i < 8; i++) ++ s3c_gpio_cfgpin(S5PC1XX_GPF1(i), S3C_GPIO_SFN(2)); ++ ++ for (i = 0; i < 8; i++) ++ s3c_gpio_cfgpin(S5PC1XX_GPF2(i), S3C_GPIO_SFN(2)); ++ ++ for (i = 0; i < 4; i++) ++ s3c_gpio_cfgpin(S5PC1XX_GPF3(i), S3C_GPIO_SFN(2)); ++ ++#ifndef CONFIG_BACKLIGHT_PWM ++ /* backlight ON */ ++ if (gpio_is_valid(S5PC1XX_GPD(0))) { ++ err = gpio_request(S5PC1XX_GPD(0), "GPD"); ++ ++ if (err) { ++ printk(KERN_ERR "failed to request GPD for " ++ "lcd backlight control\n"); ++ return err; ++ } ++ ++ gpio_direction_output(S5PC1XX_GPD(0), 1); ++ } ++#endif ++ ++ /* module reset */ ++ if (gpio_is_valid(S5PC1XX_GPH0(6))) { ++ err = gpio_request(S5PC1XX_GPH0(6), "GPH0"); ++ ++ if (err) { ++ printk(KERN_ERR "failed to request GPH0 for " ++ "lcd reset control\n"); ++ return err; ++ } ++ ++ gpio_direction_output(S5PC1XX_GPH0(6), 1); ++ } ++ ++ mdelay(100); ++ ++ gpio_set_value(S5PC1XX_GPH0(6), 0); ++ mdelay(10); ++ ++ gpio_set_value(S5PC1XX_GPH0(6), 1); ++ mdelay(10); ++ ++ gpio_free(S5PC1XX_GPH0(6)); ++#ifndef CONFIG_BACKLIGHT_PWM ++ gpio_free(S5PC1XX_GPD(0)); ++#endif ++ ++ return 0; ++} ++#elif defined(CONFIG_CPU_S5P6440) ++int s3cfb_set_gpio(void) ++{ ++ int i, err; ++ ++ int val; ++ val = readl(S5P64XX_SPC_BASE); ++ val &= ~0x3; ++ val |= (1 << 0); ++ writel(val, S5P64XX_SPC_BASE); ++ ++ /* LCD_HSYNC, LCD_VSYNC, LCD_VDEN, LCD_VCLK, VD[23:0] */ ++ for (i = 0; i < 16; i++) ++ s3c_gpio_cfgpin(S5P64XX_GPI(i), S3C_GPIO_SFN(2)); ++ ++ for (i = 0; i < 12; i++) ++ s3c_gpio_cfgpin(S5P64XX_GPJ(i), S3C_GPIO_SFN(2)); ++ ++#ifndef CONFIG_BACKLIGHT_PWM ++ /* backlight ON */ ++ if (gpio_is_valid(S5P64XX_GPF(15))) { ++ err = gpio_request(S5P64XX_GPF(15), "GPF"); ++ ++ if (err) { ++ printk(KERN_ERR "failed to request GPD for " ++ "lcd backlight control\n"); ++ return err; ++ } ++ ++ gpio_direction_output(S5P64XX_GPF(15), 1); ++ } ++#endif ++ /* module reset */ ++ if (gpio_is_valid(S5P64XX_GPN(5))) { ++ err = gpio_request(S5P64XX_GPN(5), "GPN"); ++ ++ if (err) { ++ printk(KERN_ERR "failed to request GPH0 for " ++ "lcd reset control\n"); ++ return err; ++ } ++ ++ gpio_direction_output(S5P64XX_GPN(5), 1); ++ } ++ ++ mdelay(100); ++ ++ gpio_set_value(S5P64XX_GPN(5), 0); ++ mdelay(10); ++ ++ gpio_set_value(S5P64XX_GPN(5), 1); ++ mdelay(10); ++ ++ gpio_free(S5P64XX_GPN(5)); ++ gpio_free(S5P64XX_GPF(15)); ++ ++ return 0; ++} ++#endif ++ ++#if defined(CONFIG_PM) ++ ++static struct sleep_save s3c_lcd_save[] = { ++ SAVE_ITEM(S3C_VIDCON0), ++ SAVE_ITEM(S3C_VIDCON1), ++ ++ SAVE_ITEM(S3C_VIDTCON0), ++ SAVE_ITEM(S3C_VIDTCON1), ++ SAVE_ITEM(S3C_VIDTCON2), ++ SAVE_ITEM(S3C_VIDTCON3), ++ ++ SAVE_ITEM(S3C_WINCON0), ++ SAVE_ITEM(S3C_WINCON1), ++ SAVE_ITEM(S3C_WINCON2), ++ SAVE_ITEM(S3C_WINCON3), ++ SAVE_ITEM(S3C_WINCON4), ++ ++ SAVE_ITEM(S3C_VIDOSD0A), ++ SAVE_ITEM(S3C_VIDOSD0B), ++ SAVE_ITEM(S3C_VIDOSD0C), ++ ++ SAVE_ITEM(S3C_VIDOSD1A), ++ SAVE_ITEM(S3C_VIDOSD1B), ++ SAVE_ITEM(S3C_VIDOSD1C), ++ SAVE_ITEM(S3C_VIDOSD1D), ++ ++ SAVE_ITEM(S3C_VIDOSD2A), ++ SAVE_ITEM(S3C_VIDOSD2B), ++ SAVE_ITEM(S3C_VIDOSD2C), ++ SAVE_ITEM(S3C_VIDOSD2D), ++ ++ SAVE_ITEM(S3C_VIDOSD3A), ++ SAVE_ITEM(S3C_VIDOSD3B), ++ SAVE_ITEM(S3C_VIDOSD3C), ++ ++ SAVE_ITEM(S3C_VIDOSD4A), ++ SAVE_ITEM(S3C_VIDOSD4B), ++ SAVE_ITEM(S3C_VIDOSD4C), ++ ++ SAVE_ITEM(S3C_VIDW00ADD0B0), ++ SAVE_ITEM(S3C_VIDW00ADD0B1), ++ SAVE_ITEM(S3C_VIDW01ADD0B0), ++ SAVE_ITEM(S3C_VIDW01ADD0B1), ++ SAVE_ITEM(S3C_VIDW02ADD0), ++ SAVE_ITEM(S3C_VIDW03ADD0), ++ SAVE_ITEM(S3C_VIDW04ADD0), ++ SAVE_ITEM(S3C_VIDW00ADD1B0), ++ SAVE_ITEM(S3C_VIDW00ADD1B1), ++ SAVE_ITEM(S3C_VIDW01ADD1B0), ++ SAVE_ITEM(S3C_VIDW01ADD1B1), ++ SAVE_ITEM(S3C_VIDW02ADD1), ++ SAVE_ITEM(S3C_VIDW03ADD1), ++ SAVE_ITEM(S3C_VIDW04ADD1), ++ SAVE_ITEM(S3C_VIDW00ADD2), ++ SAVE_ITEM(S3C_VIDW01ADD2), ++ SAVE_ITEM(S3C_VIDW02ADD2), ++ SAVE_ITEM(S3C_VIDW03ADD2), ++ SAVE_ITEM(S3C_VIDW04ADD2), ++ ++ SAVE_ITEM(S3C_VIDINTCON0), ++ SAVE_ITEM(S3C_VIDINTCON1), ++ SAVE_ITEM(S3C_W1KEYCON0), ++ SAVE_ITEM(S3C_W1KEYCON1), ++ SAVE_ITEM(S3C_W2KEYCON0), ++ SAVE_ITEM(S3C_W2KEYCON1), ++ ++ SAVE_ITEM(S3C_W3KEYCON0), ++ SAVE_ITEM(S3C_W3KEYCON1), ++ SAVE_ITEM(S3C_W4KEYCON0), ++ SAVE_ITEM(S3C_W4KEYCON1), ++ SAVE_ITEM(S3C_DITHMODE), ++ ++ SAVE_ITEM(S3C_WIN0MAP), ++ SAVE_ITEM(S3C_WIN1MAP), ++ SAVE_ITEM(S3C_WIN2MAP), ++ SAVE_ITEM(S3C_WIN3MAP), ++ SAVE_ITEM(S3C_WIN4MAP), ++ SAVE_ITEM(S3C_WPALCON), ++ ++ SAVE_ITEM(S3C_TRIGCON), ++ SAVE_ITEM(S3C_I80IFCONA0), ++ SAVE_ITEM(S3C_I80IFCONA1), ++ SAVE_ITEM(S3C_I80IFCONB0), ++ SAVE_ITEM(S3C_I80IFCONB1), ++ SAVE_ITEM(S3C_LDI_CMDCON0), ++ SAVE_ITEM(S3C_LDI_CMDCON1), ++ SAVE_ITEM(S3C_SIFCCON0), ++ SAVE_ITEM(S3C_SIFCCON1), ++ SAVE_ITEM(S3C_SIFCCON2), ++ ++ SAVE_ITEM(S3C_LDI_CMD0), ++ SAVE_ITEM(S3C_LDI_CMD1), ++ SAVE_ITEM(S3C_LDI_CMD2), ++ SAVE_ITEM(S3C_LDI_CMD3), ++ SAVE_ITEM(S3C_LDI_CMD4), ++ SAVE_ITEM(S3C_LDI_CMD5), ++ SAVE_ITEM(S3C_LDI_CMD6), ++ SAVE_ITEM(S3C_LDI_CMD7), ++ SAVE_ITEM(S3C_LDI_CMD8), ++ SAVE_ITEM(S3C_LDI_CMD9), ++ SAVE_ITEM(S3C_LDI_CMD10), ++ SAVE_ITEM(S3C_LDI_CMD11), ++ ++ SAVE_ITEM(S3C_W2PDATA01), ++ SAVE_ITEM(S3C_W2PDATA23), ++ SAVE_ITEM(S3C_W2PDATA45), ++ SAVE_ITEM(S3C_W2PDATA67), ++ SAVE_ITEM(S3C_W2PDATA89), ++ SAVE_ITEM(S3C_W2PDATAAB), ++ SAVE_ITEM(S3C_W2PDATACD), ++ SAVE_ITEM(S3C_W2PDATAEF), ++ SAVE_ITEM(S3C_W3PDATA01), ++ SAVE_ITEM(S3C_W3PDATA23), ++ SAVE_ITEM(S3C_W3PDATA45), ++ SAVE_ITEM(S3C_W3PDATA67), ++ SAVE_ITEM(S3C_W3PDATA89), ++ SAVE_ITEM(S3C_W3PDATAAB), ++ SAVE_ITEM(S3C_W3PDATACD), ++ SAVE_ITEM(S3C_W3PDATAEF), ++ SAVE_ITEM(S3C_W4PDATA01), ++ SAVE_ITEM(S3C_W4PDATA23), ++}; ++ ++/* ++ * Suspend ++ */ ++int s3cfb_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ struct fb_info *fbinfo = platform_get_drvdata(dev); ++ s3cfb_info_t *info = fbinfo->par; ++ ++ s3cfb_stop_lcd(); ++#if defined(CONFIG_CPU_S5P6440) ++ s5p6440_pm_do_save(s3c_lcd_save, ARRAY_SIZE(s3c_lcd_save)); ++#else ++ s5pc1xx_pm_do_save(s3c_lcd_save, ARRAY_SIZE(s3c_lcd_save)); ++#endif ++ ++ /* sleep before disabling the clock, we need to ensure ++ * the LCD DMA engine is not going to get back on the bus ++ * before the clock goes off again (bjd) */ ++ ++ msleep(1); ++ clk_disable(info->clk); ++ ++ return 0; ++} ++ ++/* ++ * Resume ++ */ ++int s3cfb_resume(struct platform_device *dev) ++{ ++ struct fb_info *fbinfo = platform_get_drvdata(dev); ++ s3cfb_info_t *info = fbinfo->par; ++ ++ clk_enable(info->clk); ++ msleep(1); ++#if defined(CONFIG_CPU_S5P6440) ++ s5p6440_pm_do_restore(s3c_lcd_save, ARRAY_SIZE(s3c_lcd_save)); ++#else ++ s5pc1xx_pm_do_restore(s3c_lcd_save, ARRAY_SIZE(s3c_lcd_save)); ++#endif ++ ++ s3cfb_init_hw(); ++ s3cfb_start_lcd(); ++ ++ return 0; ++} ++ ++#else ++ ++int s3cfb_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ return 0; ++} ++ ++int s3cfb_resume(struct platform_device *dev) ++{ ++ return 0; ++} ++ ++#endif ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/video/samsung/s3cfb_lte480wv.c linux-2.6.28.6/drivers/video/samsung/s3cfb_lte480wv.c +--- linux-2.6.28/drivers/video/samsung/s3cfb_lte480wv.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/video/samsung/s3cfb_lte480wv.c 2009-10-12 12:00:56.000000000 +0200 +@@ -0,0 +1,98 @@ ++/* ++ * drivers/video/s3c/s3cfb_lte480wv.c ++ * ++ * $Id: s3cfb_lte480wv.c,v 1.12 2008/06/05 02:13:24 jsgood Exp $ ++ * ++ * Copyright (C) 2008 Jinsung Yang ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive for ++ * more details. ++ * ++ * S3C Frame Buffer Driver ++ * based on skeletonfb.c, sa1100fb.h, s3c2410fb.c ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "s3cfb.h" ++ ++#define S3CFB_HFP 40 /* front porch */ ++#define S3CFB_HSW 48 /* hsync width */ ++#define S3CFB_HBP 40 /* back porch */ ++ ++#define S3CFB_VFP 13 /* front porch */ ++#define S3CFB_VSW 3 /* vsync width */ ++#define S3CFB_VBP 29 /* back porch */ ++ ++#define S3CFB_HRES 800 /* horizon pixel x resolition */ ++#define S3CFB_VRES 480 /* line cnt y resolution */ ++ ++#define S3CFB_HRES_VIRTUAL 800 /* horizon pixel x resolition */ ++#define S3CFB_VRES_VIRTUAL 960 /* line cnt y resolution */ ++ ++#define S3CFB_HRES_OSD 800 /* horizon pixel x resolition */ ++#define S3CFB_VRES_OSD 480 /* line cnt y resolution */ ++ ++#define S3CFB_VFRAME_FREQ 60 /* frame rate freq */ ++ ++#define S3CFB_PIXEL_CLOCK (S3CFB_VFRAME_FREQ * (S3CFB_HFP + S3CFB_HSW + S3CFB_HBP + S3CFB_HRES) * (S3CFB_VFP + S3CFB_VSW + S3CFB_VBP + S3CFB_VRES)) ++ ++static void s3cfb_set_fimd_info(void) ++{ ++ s3cfb_fimd.vidcon1 = S3C_VIDCON1_IHSYNC_INVERT | S3C_VIDCON1_IVSYNC_INVERT | S3C_VIDCON1_IVDEN_NORMAL; ++ s3cfb_fimd.vidtcon0 = S3C_VIDTCON0_VBPD(S3CFB_VBP - 1) | S3C_VIDTCON0_VFPD(S3CFB_VFP - 1) | S3C_VIDTCON0_VSPW(S3CFB_VSW - 1); ++ s3cfb_fimd.vidtcon1 = S3C_VIDTCON1_HBPD(S3CFB_HBP - 1) | S3C_VIDTCON1_HFPD(S3CFB_HFP - 1) | S3C_VIDTCON1_HSPW(S3CFB_HSW - 1); ++ s3cfb_fimd.vidtcon2 = S3C_VIDTCON2_LINEVAL(S3CFB_VRES - 1) | S3C_VIDTCON2_HOZVAL(S3CFB_HRES - 1); ++ ++ s3cfb_fimd.vidosd0a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0); ++ s3cfb_fimd.vidosd0b = S3C_VIDOSDxB_OSD_RBX_F(S3CFB_HRES - 1) | S3C_VIDOSDxB_OSD_RBY_F(S3CFB_VRES - 1); ++ ++ s3cfb_fimd.vidosd1a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0); ++ s3cfb_fimd.vidosd1b = S3C_VIDOSDxB_OSD_RBX_F(S3CFB_HRES_OSD - 1) | S3C_VIDOSDxB_OSD_RBY_F(S3CFB_VRES_OSD - 1); ++ ++ s3cfb_fimd.width = S3CFB_HRES; ++ s3cfb_fimd.height = S3CFB_VRES; ++ s3cfb_fimd.xres = S3CFB_HRES; ++ s3cfb_fimd.yres = S3CFB_VRES; ++ ++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN) ++ s3cfb_fimd.xres_virtual = S3CFB_HRES_VIRTUAL; ++ s3cfb_fimd.yres_virtual = S3CFB_VRES_VIRTUAL; ++#else ++ s3cfb_fimd.xres_virtual = S3CFB_HRES; ++ s3cfb_fimd.yres_virtual = S3CFB_VRES; ++#endif ++ ++ s3cfb_fimd.osd_width = S3CFB_HRES_OSD; ++ s3cfb_fimd.osd_height = S3CFB_VRES_OSD; ++ s3cfb_fimd.osd_xres = S3CFB_HRES_OSD; ++ s3cfb_fimd.osd_yres = S3CFB_VRES_OSD; ++ ++ s3cfb_fimd.osd_xres_virtual = S3CFB_HRES_OSD; ++ s3cfb_fimd.osd_yres_virtual = S3CFB_VRES_OSD; ++ ++ s3cfb_fimd.pixclock = S3CFB_PIXEL_CLOCK; ++ ++ s3cfb_fimd.hsync_len = S3CFB_HSW; ++ s3cfb_fimd.vsync_len = S3CFB_VSW; ++ s3cfb_fimd.left_margin = S3CFB_HFP; ++ s3cfb_fimd.upper_margin = S3CFB_VFP; ++ s3cfb_fimd.right_margin = S3CFB_HBP; ++ s3cfb_fimd.lower_margin = S3CFB_VBP; ++} ++ ++void s3cfb_init_hw(void) ++{ ++ printk(KERN_INFO "LCD TYPE :: LTE480WV will be initialized\n"); ++ ++ s3cfb_set_fimd_info(); ++ s3cfb_set_gpio(); ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/video/samsung/s3cfb_lts222qv.c linux-2.6.28.6/drivers/video/samsung/s3cfb_lts222qv.c +--- linux-2.6.28/drivers/video/samsung/s3cfb_lts222qv.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/video/samsung/s3cfb_lts222qv.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,365 @@ ++/* ++ * drivers/video/s3c/s3cfb_lte480wv.c ++ * ++ * $Id: s3cfb_lts222qv.c,v 1.2 2008/11/18 01:50:23 jsgood Exp $ ++ * ++ * Copyright (C) 2008 Jinsung Yang ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive for ++ * more details. ++ * ++ * S3C Frame Buffer Driver ++ * based on skeletonfb.c, sa1100fb.h, s3c2410fb.c ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "s3cfb.h" ++ ++#define S3CFB_SPI_CH 0 /* spi channel for module init */ ++ ++#if defined(CONFIG_CPU_S5P6440) ++#define S3CFB_HFP 6 /* front porch */ ++#define S3CFB_HSW 3 /* hsync width */ ++#define S3CFB_HBP 1 /* back porch */ ++ ++#define S3CFB_VFP 10 /* front porch */ ++#define S3CFB_VSW 3 /* vsync width */ ++#define S3CFB_VBP 9 /* back porch */ ++ ++#else ++#define S3CFB_HFP 7 /* front porch */ ++#define S3CFB_HSW 4 /* hsync width */ ++#define S3CFB_HBP 2 /* back porch */ ++ ++#define S3CFB_VFP 11 /* front porch */ ++#define S3CFB_VSW 4 /* vsync width */ ++#define S3CFB_VBP 10 /* back porch */ ++#endif ++ ++#define S3CFB_HRES 240 /* horizon pixel x resolition */ ++#define S3CFB_VRES 320 /* line cnt y resolution */ ++ ++#define S3CFB_HRES_VIRTUAL 240 /* horizon pixel x resolition */ ++#define S3CFB_VRES_VIRTUAL 640 /* line cnt y resolution */ ++ ++#define S3CFB_HRES_OSD 240 /* horizon pixel x resolition */ ++#define S3CFB_VRES_OSD 320 /* line cnt y resolution */ ++ ++#if defined(CONFIG_PLAT_S3C24XX) ++#define S3CFB_VFRAME_FREQ 75 /* frame rate freq */ ++#else ++#define S3CFB_VFRAME_FREQ 60 /* frame rate freq */ ++#endif ++ ++#define S3CFB_PIXEL_CLOCK (S3CFB_VFRAME_FREQ * (S3CFB_HFP + S3CFB_HSW + S3CFB_HBP + S3CFB_HRES) * (S3CFB_VFP + S3CFB_VSW + S3CFB_VBP + S3CFB_VRES)) ++ ++static void s3cfb_set_fimd_info(void) ++{ ++ s3cfb_fimd.vidcon1 = S3C_VIDCON1_IHSYNC_INVERT | S3C_VIDCON1_IVSYNC_INVERT | S3C_VIDCON1_IVDEN_NORMAL; ++ s3cfb_fimd.vidtcon0 = S3C_VIDTCON0_VBPD(S3CFB_VBP - 1) | S3C_VIDTCON0_VFPD(S3CFB_VFP - 1) | S3C_VIDTCON0_VSPW(S3CFB_VSW - 1); ++ s3cfb_fimd.vidtcon1 = S3C_VIDTCON1_HBPD(S3CFB_HBP - 1) | S3C_VIDTCON1_HFPD(S3CFB_HFP - 1) | S3C_VIDTCON1_HSPW(S3CFB_HSW - 1); ++ s3cfb_fimd.vidtcon2 = S3C_VIDTCON2_LINEVAL(S3CFB_VRES - 1) | S3C_VIDTCON2_HOZVAL(S3CFB_HRES - 1); ++ ++ s3cfb_fimd.vidosd0a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0); ++ s3cfb_fimd.vidosd0b = S3C_VIDOSDxB_OSD_RBX_F(S3CFB_HRES - 1) | S3C_VIDOSDxB_OSD_RBY_F(S3CFB_VRES - 1); ++ ++ s3cfb_fimd.vidosd1a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0); ++ s3cfb_fimd.vidosd1b = S3C_VIDOSDxB_OSD_RBX_F(S3CFB_HRES_OSD - 1) | S3C_VIDOSDxB_OSD_RBY_F(S3CFB_VRES_OSD - 1); ++ ++ s3cfb_fimd.width = S3CFB_HRES; ++ s3cfb_fimd.height = S3CFB_VRES; ++ s3cfb_fimd.xres = S3CFB_HRES; ++ s3cfb_fimd.yres = S3CFB_VRES; ++ ++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN) ++ s3cfb_fimd.xres_virtual = S3CFB_HRES_VIRTUAL; ++ s3cfb_fimd.yres_virtual = S3CFB_VRES_VIRTUAL; ++#else ++ s3cfb_fimd.xres_virtual = S3CFB_HRES; ++ s3cfb_fimd.yres_virtual = S3CFB_VRES; ++#endif ++ ++ s3cfb_fimd.osd_width = S3CFB_HRES_OSD; ++ s3cfb_fimd.osd_height = S3CFB_VRES_OSD; ++ s3cfb_fimd.osd_xres = S3CFB_HRES_OSD; ++ s3cfb_fimd.osd_yres = S3CFB_VRES_OSD; ++ ++ s3cfb_fimd.osd_xres_virtual = S3CFB_HRES_OSD; ++ s3cfb_fimd.osd_yres_virtual = S3CFB_VRES_OSD; ++ ++ s3cfb_fimd.pixclock = S3CFB_PIXEL_CLOCK; ++ ++ s3cfb_fimd.hsync_len = S3CFB_HSW; ++ s3cfb_fimd.vsync_len = S3CFB_VSW; ++ s3cfb_fimd.left_margin = S3CFB_HFP; ++ s3cfb_fimd.upper_margin = S3CFB_VFP; ++ s3cfb_fimd.right_margin = S3CFB_HBP; ++ s3cfb_fimd.lower_margin = S3CFB_VBP; ++} ++ ++static void s3cfb_spi_write_byte(int data) ++{ ++ unsigned int delay = 50; ++ int i; ++ ++ s3cfb_spi_lcd_den(S3CFB_SPI_CH, 1); ++ s3cfb_spi_lcd_dclk(S3CFB_SPI_CH, 1); ++ s3cfb_spi_lcd_dseri(S3CFB_SPI_CH, 1); ++ udelay(delay); ++ ++ s3cfb_spi_lcd_den(S3CFB_SPI_CH, 0); ++ udelay(delay); ++ ++ for (i = 7; i >= 0; i--) { ++ s3cfb_spi_lcd_dclk(S3CFB_SPI_CH, 0); ++ ++ if ((data >> i) & 0x1) ++ s3cfb_spi_lcd_dseri(S3CFB_SPI_CH, 1); ++ else ++ s3cfb_spi_lcd_dseri(S3CFB_SPI_CH, 0); ++ ++ udelay(delay); ++ ++ s3cfb_spi_lcd_dclk(S3CFB_SPI_CH, 1); ++ udelay(delay); ++ } ++ ++ s3cfb_spi_lcd_den(S3CFB_SPI_CH, 1); ++ udelay(delay); ++} ++ ++static void s3cfb_spi_write(int address, int data) ++{ ++ unsigned int mode = 0x8; ++ ++ writel(mode | 0x01, S3C_SIFCCON0); ++ writel(mode | 0x03, S3C_SIFCCON0); ++ ++ s3cfb_spi_write_byte(address); ++ ++ writel(mode | 0x01, S3C_SIFCCON0); ++ writel(mode | 0x00, S3C_SIFCCON0); ++ ++ udelay(100); ++ ++ writel(mode | 0x01, S3C_SIFCCON0); ++ writel(mode | 0x03, S3C_SIFCCON0); ++ ++ s3cfb_spi_write_byte(data); ++ ++ writel(mode | 0x01, S3C_SIFCCON0); ++ writel(mode | 0x00, S3C_SIFCCON0); ++} ++ ++static void s3cfb_init_ldi(void) ++{ ++ unsigned long long endtime; ++ ++ s3cfb_spi_write(0x22, 0x01); ++ s3cfb_spi_write(0x03, 0x01); ++ ++ s3cfb_spi_write(0x00, 0xa0); udelay(5); ++ s3cfb_spi_write(0x01, 0x10); udelay(5); ++ s3cfb_spi_write(0x02, 0x00); udelay(5); ++ s3cfb_spi_write(0x05, 0x00); udelay(5); ++ ++ s3cfb_spi_write(0x0d, 0x00); ++ endtime = get_jiffies_64() + 4; while(jiffies < endtime); ++ ++ s3cfb_spi_write(0x0e, 0x00); udelay(5); ++ s3cfb_spi_write(0x0f, 0x00); udelay(5); ++ s3cfb_spi_write(0x10, 0x00); udelay(5); ++ s3cfb_spi_write(0x11, 0x00); udelay(5); ++ s3cfb_spi_write(0x12, 0x00); udelay(5); ++ s3cfb_spi_write(0x13, 0x00); udelay(5); ++ s3cfb_spi_write(0x14, 0x00); udelay(5); ++ s3cfb_spi_write(0x15, 0x00); udelay(5); ++ s3cfb_spi_write(0x16, 0x00); udelay(5); ++ s3cfb_spi_write(0x17, 0x00); udelay(5); ++ s3cfb_spi_write(0x34, 0x01); udelay(5); ++ ++ s3cfb_spi_write(0x35, 0x00); ++ endtime = get_jiffies_64() + 4; while(jiffies < endtime); ++ ++ s3cfb_spi_write(0x8d, 0x01); udelay(5); ++ s3cfb_spi_write(0x8b, 0x28); udelay(5); ++ s3cfb_spi_write(0x4b, 0x00); udelay(5); ++ s3cfb_spi_write(0x4e, 0x00); udelay(5); ++ s3cfb_spi_write(0x4d, 0x00); udelay(5); ++ s3cfb_spi_write(0x4e, 0x00); udelay(5); ++ s3cfb_spi_write(0x4f, 0x00); udelay(5); ++ ++ s3cfb_spi_write(0x50, 0x00); ++ endtime = get_jiffies_64() + 5; while(jiffies < endtime); ++ ++ s3cfb_spi_write(0x86, 0x00); udelay(5); ++ s3cfb_spi_write(0x87, 0x26); udelay(5); ++ s3cfb_spi_write(0x88, 0x02); udelay(5); ++ s3cfb_spi_write(0x89, 0x05); udelay(5); ++ s3cfb_spi_write(0x33, 0x01); udelay(5); ++ ++ s3cfb_spi_write(0x37, 0x06); ++ endtime = get_jiffies_64() + 5; while(jiffies < endtime); ++ ++ s3cfb_spi_write(0x76, 0x00); ++ endtime = get_jiffies_64() + 4; while(jiffies < endtime); ++ ++ s3cfb_spi_write(0x42, 0x00); udelay(5); ++ s3cfb_spi_write(0x43, 0x00); udelay(5); ++ s3cfb_spi_write(0x44, 0x00); udelay(5); ++ s3cfb_spi_write(0x45, 0x00); udelay(5); ++ s3cfb_spi_write(0x46, 0xef); udelay(5); ++ s3cfb_spi_write(0x47, 0x00); udelay(5); ++ s3cfb_spi_write(0x48, 0x00); udelay(5); ++ ++ s3cfb_spi_write(0x49, 0x01); ++ endtime = get_jiffies_64() + 5; while(jiffies < endtime); ++ ++ s3cfb_spi_write(0x4a, 0x3f); udelay(5); ++ s3cfb_spi_write(0x3c, 0x00); udelay(5); ++ s3cfb_spi_write(0x3d, 0x00); udelay(5); ++ s3cfb_spi_write(0x3e, 0x01); udelay(5); ++ s3cfb_spi_write(0x3f, 0x3f); udelay(5); ++ s3cfb_spi_write(0x40, 0x01); udelay(5); ++ s3cfb_spi_write(0x41, 0x0a); udelay(5); ++ ++ s3cfb_spi_write(0x8f, 0x3f); ++ endtime = get_jiffies_64() + 4; while(jiffies < endtime); ++ ++ s3cfb_spi_write(0x90, 0x3f); udelay(5); ++ s3cfb_spi_write(0x91, 0x33); udelay(5); ++ s3cfb_spi_write(0x92, 0x77); udelay(5); ++ s3cfb_spi_write(0x93, 0x77); udelay(5); ++ s3cfb_spi_write(0x94, 0x17); udelay(5); ++ s3cfb_spi_write(0x95, 0x3f); udelay(5); ++ s3cfb_spi_write(0x96, 0x00); udelay(5); ++ s3cfb_spi_write(0x97, 0x33); udelay(5); ++ s3cfb_spi_write(0x98, 0x77); udelay(5); ++ s3cfb_spi_write(0x99, 0x77); udelay(5); ++ s3cfb_spi_write(0x9a, 0x17); udelay(5); ++ s3cfb_spi_write(0x9b, 0x07); udelay(5); ++ s3cfb_spi_write(0x9c, 0x07); udelay(5); ++ ++ s3cfb_spi_write(0x9d, 0x80); ++ endtime = get_jiffies_64() + 4; while(jiffies < endtime); ++ ++ s3cfb_spi_write(0x1d, 0x08); ++ endtime = get_jiffies_64() + 4; while(jiffies < endtime); ++ ++ s3cfb_spi_write(0x23, 0x00); ++ endtime = get_jiffies_64() + 5; while(jiffies < endtime); ++ ++ s3cfb_spi_write(0x24, 0x94); ++ endtime = get_jiffies_64() + 5; while(jiffies < endtime); ++ ++ s3cfb_spi_write(0x25, 0x6f); ++ endtime = get_jiffies_64() + 4; while(jiffies < endtime); ++ ++ s3cfb_spi_write(0x28, 0x1e); ++ s3cfb_spi_write(0x1a, 0x00); ++ s3cfb_spi_write(0x21, 0x10); ++ s3cfb_spi_write(0x18, 0x25); ++ ++ endtime = get_jiffies_64() + 4; while(jiffies < endtime); ++ ++ s3cfb_spi_write(0x19, 0x48); ++ s3cfb_spi_write(0x18, 0xe5); ++ ++ endtime = get_jiffies_64() + 4; while(jiffies < endtime); ++ ++ s3cfb_spi_write(0x18, 0xF7); ++ endtime = get_jiffies_64() + 4; while(jiffies < endtime); ++ ++ s3cfb_spi_write(0x1b, 0x07); ++ endtime = get_jiffies_64() + 4; while(jiffies < endtime); ++ ++ s3cfb_spi_write(0x1f, 0x68); ++ s3cfb_spi_write(0x20, 0x45); ++ s3cfb_spi_write(0x1e, 0xc1); ++ ++ endtime = get_jiffies_64() + 4; while(jiffies < endtime); ++ ++ s3cfb_spi_write(0x21, 0x00); ++ s3cfb_spi_write(0x3b, 0x01); ++ ++ endtime = get_jiffies_64() + 4; while(jiffies < endtime); ++ ++ s3cfb_spi_write(0x00, 0x20); ++ s3cfb_spi_write(0x02, 0x01); ++ ++ endtime = get_jiffies_64() + 4; while(jiffies < endtime); ++} ++ ++#if defined(CONFIG_CPU_S5P6440) ++static void InitStartPosOnLcd(void) ++{ ++ // start addr setting ++ s3cfb_spi_write(0x44, 0x00); // y addr 2 ++ s3cfb_spi_write(0x42, 0x00); // x addr ++ s3cfb_spi_write(0x43, 0x00); // y addr 1 ++} ++#endif ++ ++static void s3cfb_set_gpio_lts222qv(void) ++{ ++#if defined(CONFIG_CPU_S5P6440) ++ gpio_request(S5P64XX_GPN(1), "GPN"); ++ gpio_direction_output(S5P64XX_GPN(1), 1); ++ gpio_request(S5P64XX_GPN(2), "GPN"); ++ gpio_direction_output(S5P64XX_GPN(2), 1); ++ gpio_request(S5P64XX_GPN(3), "GPN"); ++ gpio_direction_output(S5P64XX_GPN(3), 1); ++ ++ s3c_gpio_setpull(S5P64XX_GPN(1), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S5P64XX_GPN(2), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S5P64XX_GPN(3), S3C_GPIO_PULL_NONE); ++#elif defined(CONFIG_PLAT_S3C64XX) ++ gpio_direction_output(S3C64XX_GPC(1), 1); ++ gpio_direction_output(S3C64XX_GPC(2), 1); ++ gpio_direction_output(S3C64XX_GPC(3), 1); ++ ++ s3c_gpio_setpull(S3C64XX_GPC(1), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S3C64XX_GPC(2), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S3C64XX_GPC(3), S3C_GPIO_PULL_NONE); ++#elif defined(CONFIG_CPU_S5PC100) ++ gpio_request(S5PC1XX_GPB(1), "GPB"); ++ gpio_direction_output(S5PC1XX_GPB(1), 1); ++ gpio_request(S5PC1XX_GPB(2), "GPB"); ++ gpio_direction_output(S5PC1XX_GPB(2), 1); ++ gpio_request(S5PC1XX_GPB(3), "GPB"); ++ gpio_direction_output(S5PC1XX_GPB(3), 1); ++ ++ s3c_gpio_setpull(S5PC1XX_GPB(1), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S5PC1XX_GPB(2), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S5PC1XX_GPB(3), S3C_GPIO_PULL_NONE); ++#endif ++} ++ ++void s3cfb_init_hw(void) ++{ ++ printk(KERN_INFO "LCD TYPE :: LTV222QV will be initialized\n"); ++ ++ s3cfb_set_fimd_info(); ++ s3cfb_set_gpio(); ++ ++ if (s3cfb_spi_gpio_request(S3CFB_SPI_CH)) ++ printk(KERN_ERR "failed to request GPIO for spi-lcd\n"); ++ else { ++ s3cfb_set_gpio_lts222qv(); ++ s3cfb_init_ldi(); ++ s3cfb_spi_gpio_free(S3CFB_SPI_CH); ++ } ++ #if defined(CONFIG_CPU_S5P6440) ++ InitStartPosOnLcd(); ++ #endif ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/video/samsung/s3cfb_ltv350qv.c linux-2.6.28.6/drivers/video/samsung/s3cfb_ltv350qv.c +--- linux-2.6.28/drivers/video/samsung/s3cfb_ltv350qv.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/video/samsung/s3cfb_ltv350qv.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,293 @@ ++/* ++ * drivers/video/s3c/s3cfb_lte480wv.c ++ * ++ * $Id: s3cfb_ltv350qv.c,v 1.1 2008/11/17 11:12:08 jsgood Exp $ ++ * ++ * Copyright (C) 2008 Jinsung Yang ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive for ++ * more details. ++ * ++ * S3C Frame Buffer Driver ++ * based on skeletonfb.c, sa1100fb.h, s3c2410fb.c ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "s3cfb.h" ++ ++#if defined(CONFIG_PLAT_S5PC1XX) ++#define S3CFB_SPI_CH 0 /* spi channel for module init */ ++#else ++#define S3CFB_SPI_CH 1 /* spi channel for module init */ ++#endif ++ ++#define S3CFB_HFP 3 /* front porch */ ++#define S3CFB_HSW 10 /* hsync width */ ++#define S3CFB_HBP 5 /* back porch */ ++ ++#define S3CFB_VFP 3 /* front porch */ ++#define S3CFB_VSW 4 /* vsync width */ ++#define S3CFB_VBP 5 /* back porch */ ++ ++#define S3CFB_HRES 320 /* horizon pixel x resolition */ ++#define S3CFB_VRES 240 /* line cnt y resolution */ ++ ++#define S3CFB_HRES_VIRTUAL 320 /* horizon pixel x resolition */ ++#define S3CFB_VRES_VIRTUAL 480 /* line cnt y resolution */ ++ ++#define S3CFB_HRES_OSD 320 /* horizon pixel x resolition */ ++#define S3CFB_VRES_OSD 240 /* line cnt y resolution */ ++ ++#if defined(CONFIG_PLAT_S3C24XX) ++#define S3CFB_VFRAME_FREQ 75 /* frame rate freq */ ++#else ++#define S3CFB_VFRAME_FREQ 60 /* frame rate freq */ ++#endif ++ ++#define S3CFB_PIXEL_CLOCK (S3CFB_VFRAME_FREQ * (S3CFB_HFP + S3CFB_HSW + S3CFB_HBP + S3CFB_HRES) * (S3CFB_VFP + S3CFB_VSW + S3CFB_VBP + S3CFB_VRES)) ++ ++static void s3cfb_set_fimd_info(void) ++{ ++ s3cfb_fimd.vidcon1 = S3C_VIDCON1_IHSYNC_INVERT | S3C_VIDCON1_IVSYNC_INVERT | S3C_VIDCON1_IVDEN_NORMAL; ++ s3cfb_fimd.vidtcon0 = S3C_VIDTCON0_VBPD(S3CFB_VBP - 1) | S3C_VIDTCON0_VFPD(S3CFB_VFP - 1) | S3C_VIDTCON0_VSPW(S3CFB_VSW - 1); ++ s3cfb_fimd.vidtcon1 = S3C_VIDTCON1_HBPD(S3CFB_HBP - 1) | S3C_VIDTCON1_HFPD(S3CFB_HFP - 1) | S3C_VIDTCON1_HSPW(S3CFB_HSW - 1); ++ s3cfb_fimd.vidtcon2 = S3C_VIDTCON2_LINEVAL(S3CFB_VRES - 1) | S3C_VIDTCON2_HOZVAL(S3CFB_HRES - 1); ++ ++ s3cfb_fimd.vidosd0a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0); ++ s3cfb_fimd.vidosd0b = S3C_VIDOSDxB_OSD_RBX_F(S3CFB_HRES - 1) | S3C_VIDOSDxB_OSD_RBY_F(S3CFB_VRES - 1); ++ ++ s3cfb_fimd.vidosd1a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0); ++ s3cfb_fimd.vidosd1b = S3C_VIDOSDxB_OSD_RBX_F(S3CFB_HRES_OSD - 1) | S3C_VIDOSDxB_OSD_RBY_F(S3CFB_VRES_OSD - 1); ++ ++ s3cfb_fimd.width = S3CFB_HRES; ++ s3cfb_fimd.height = S3CFB_VRES; ++ s3cfb_fimd.xres = S3CFB_HRES; ++ s3cfb_fimd.yres = S3CFB_VRES; ++ ++#if defined(CONFIG_FB_S3C_VIRTUAL_SCREEN) ++ s3cfb_fimd.xres_virtual = S3CFB_HRES_VIRTUAL; ++ s3cfb_fimd.yres_virtual = S3CFB_VRES_VIRTUAL; ++#else ++ s3cfb_fimd.xres_virtual = S3CFB_HRES; ++ s3cfb_fimd.yres_virtual = S3CFB_VRES; ++#endif ++ ++ s3cfb_fimd.osd_width = S3CFB_HRES_OSD; ++ s3cfb_fimd.osd_height = S3CFB_VRES_OSD; ++ s3cfb_fimd.osd_xres = S3CFB_HRES_OSD; ++ s3cfb_fimd.osd_yres = S3CFB_VRES_OSD; ++ ++ s3cfb_fimd.osd_xres_virtual = S3CFB_HRES_OSD; ++ s3cfb_fimd.osd_yres_virtual = S3CFB_VRES_OSD; ++ ++ s3cfb_fimd.pixclock = S3CFB_PIXEL_CLOCK; ++ ++ s3cfb_fimd.hsync_len = S3CFB_HSW; ++ s3cfb_fimd.vsync_len = S3CFB_VSW; ++ s3cfb_fimd.left_margin = S3CFB_HFP; ++ s3cfb_fimd.upper_margin = S3CFB_VFP; ++ s3cfb_fimd.right_margin = S3CFB_HBP; ++ s3cfb_fimd.lower_margin = S3CFB_VBP; ++} ++ ++void s3cfb_spi_write(int address, int data) ++{ ++ unsigned int delay = 50; ++ unsigned char dev_id = 0x1d; ++ int i; ++ ++ s3cfb_spi_lcd_den(S3CFB_SPI_CH, 1); ++ s3cfb_spi_lcd_dclk(S3CFB_SPI_CH, 1); ++ s3cfb_spi_lcd_dseri(S3CFB_SPI_CH, 1); ++ udelay(delay); ++ ++ s3cfb_spi_lcd_den(S3CFB_SPI_CH, 0); ++ udelay(delay); ++ ++ for (i = 5; i >= 0; i--) { ++ s3cfb_spi_lcd_dclk(S3CFB_SPI_CH, 0); ++ ++ if ((dev_id >> i) & 0x1) ++ s3cfb_spi_lcd_dseri(S3CFB_SPI_CH, 1); ++ else ++ s3cfb_spi_lcd_dseri(S3CFB_SPI_CH, 0); ++ ++ udelay(delay); ++ ++ s3cfb_spi_lcd_dclk(S3CFB_SPI_CH, 1); ++ udelay(delay); ++ } ++ ++ s3cfb_spi_lcd_dclk(S3CFB_SPI_CH, 0); ++ s3cfb_spi_lcd_dseri(S3CFB_SPI_CH, 0); ++ udelay(delay); ++ ++ s3cfb_spi_lcd_dclk(S3CFB_SPI_CH, 1); ++ udelay(delay); ++ ++ s3cfb_spi_lcd_dclk(S3CFB_SPI_CH, 0); ++ s3cfb_spi_lcd_dseri(S3CFB_SPI_CH, 0); ++ udelay(delay); ++ ++ s3cfb_spi_lcd_dclk(S3CFB_SPI_CH, 1); ++ udelay(delay); ++ ++ for (i = 15; i >= 0; i--) { ++ s3cfb_spi_lcd_dclk(S3CFB_SPI_CH, 0); ++ ++ if ((address >> i) & 0x1) ++ s3cfb_spi_lcd_dseri(S3CFB_SPI_CH, 1); ++ else ++ s3cfb_spi_lcd_dseri(S3CFB_SPI_CH, 0); ++ ++ udelay(delay); ++ ++ s3cfb_spi_lcd_dclk(S3CFB_SPI_CH, 1); ++ udelay(delay); ++ } ++ ++ s3cfb_spi_lcd_dseri(S3CFB_SPI_CH, 1); ++ udelay(delay); ++ ++ s3cfb_spi_lcd_den(S3CFB_SPI_CH, 1); ++ udelay(delay * 10); ++ ++ s3cfb_spi_lcd_den(S3CFB_SPI_CH, 0); ++ udelay(delay); ++ ++ for (i = 5; i >= 0; i--) { ++ s3cfb_spi_lcd_dclk(S3CFB_SPI_CH, 0); ++ ++ if ((dev_id >> i) & 0x1) ++ s3cfb_spi_lcd_dseri(S3CFB_SPI_CH, 1); ++ else ++ s3cfb_spi_lcd_dseri(S3CFB_SPI_CH, 0); ++ ++ udelay(delay); ++ ++ s3cfb_spi_lcd_dclk(S3CFB_SPI_CH, 1); ++ udelay(delay); ++ ++ } ++ ++ s3cfb_spi_lcd_dclk(S3CFB_SPI_CH, 0); ++ s3cfb_spi_lcd_dseri(S3CFB_SPI_CH, 1); ++ udelay(delay); ++ ++ s3cfb_spi_lcd_dclk(S3CFB_SPI_CH, 1); ++ udelay(delay); ++ ++ s3cfb_spi_lcd_dclk(S3CFB_SPI_CH, 0); ++ s3cfb_spi_lcd_dseri(S3CFB_SPI_CH, 0); ++ udelay(delay); ++ ++ s3cfb_spi_lcd_dclk(S3CFB_SPI_CH, 1); ++ udelay(delay); ++ ++ for (i = 15; i >= 0; i--) { ++ s3cfb_spi_lcd_dclk(S3CFB_SPI_CH, 0); ++ ++ if ((data >> i) & 0x1) ++ s3cfb_spi_lcd_dseri(S3CFB_SPI_CH, 1); ++ else ++ s3cfb_spi_lcd_dseri(S3CFB_SPI_CH, 0); ++ ++ udelay(delay); ++ ++ s3cfb_spi_lcd_dclk(S3CFB_SPI_CH, 1); ++ udelay(delay); ++ ++ } ++ ++ s3cfb_spi_lcd_den(S3CFB_SPI_CH, 1); ++ udelay(delay); ++} ++ ++static void s3cfb_init_ldi(void) ++{ ++ s3cfb_spi_set_lcd_data(S3CFB_SPI_CH); ++ mdelay(5); ++ ++ s3cfb_spi_lcd_den(S3CFB_SPI_CH, 1); ++ s3cfb_spi_lcd_dclk(S3CFB_SPI_CH, 1); ++ s3cfb_spi_lcd_dseri(S3CFB_SPI_CH, 1); ++ ++ s3cfb_spi_write(0x01, 0x001d); ++ s3cfb_spi_write(0x02, 0x0000); ++ s3cfb_spi_write(0x03, 0x0000); ++ s3cfb_spi_write(0x04, 0x0000); ++ s3cfb_spi_write(0x05, 0x50a3); ++ s3cfb_spi_write(0x06, 0x0000); ++ s3cfb_spi_write(0x07, 0x0000); ++ s3cfb_spi_write(0x08, 0x0000); ++ s3cfb_spi_write(0x09, 0x0000); ++ s3cfb_spi_write(0x0a, 0x0000); ++ s3cfb_spi_write(0x10, 0x0000); ++ s3cfb_spi_write(0x11, 0x0000); ++ s3cfb_spi_write(0x12, 0x0000); ++ s3cfb_spi_write(0x13, 0x0000); ++ s3cfb_spi_write(0x14, 0x0000); ++ s3cfb_spi_write(0x15, 0x0000); ++ s3cfb_spi_write(0x16, 0x0000); ++ s3cfb_spi_write(0x17, 0x0000); ++ s3cfb_spi_write(0x18, 0x0000); ++ s3cfb_spi_write(0x19, 0x0000); ++ ++ mdelay(10); ++ ++ s3cfb_spi_write(0x09, 0x4055); ++ s3cfb_spi_write(0x0a, 0x0000); ++ ++ mdelay(10); ++ ++ s3cfb_spi_write(0x0a, 0x2000); ++ ++ mdelay(50); ++ ++ s3cfb_spi_write(0x01, 0x409d); ++ s3cfb_spi_write(0x02, 0x0204); ++ s3cfb_spi_write(0x03, 0x2100); ++ s3cfb_spi_write(0x04, 0x1000); ++ s3cfb_spi_write(0x05, 0x5003); ++ s3cfb_spi_write(0x06, 0x0009); ++ s3cfb_spi_write(0x07, 0x000f); ++ s3cfb_spi_write(0x08, 0x0800); ++ s3cfb_spi_write(0x10, 0x0000); ++ s3cfb_spi_write(0x11, 0x0000); ++ s3cfb_spi_write(0x12, 0x000f); ++ s3cfb_spi_write(0x13, 0x1f00); ++ s3cfb_spi_write(0x14, 0x0000); ++ s3cfb_spi_write(0x15, 0x0000); ++ s3cfb_spi_write(0x16, 0x0000); ++ s3cfb_spi_write(0x17, 0x0000); ++ s3cfb_spi_write(0x18, 0x0000); ++ s3cfb_spi_write(0x19, 0x0000); ++ ++ mdelay(50); ++ ++ s3cfb_spi_write(0x09, 0x4a55); ++ s3cfb_spi_write(0x0a, 0x2000); ++} ++ ++void s3cfb_init_hw(void) ++{ ++ printk(KERN_INFO "LCD TYPE :: LTV350QV will be initialized\n"); ++ ++ s3cfb_set_fimd_info(); ++ s3cfb_set_gpio(); ++ ++ if (s3cfb_spi_gpio_request(S3CFB_SPI_CH)) ++ printk(KERN_ERR "failed to request GPIO for spi-lcd\n"); ++ else { ++ s3cfb_init_ldi(); ++ s3cfb_spi_gpio_free(S3CFB_SPI_CH); ++ } ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/video/samsung/s3cfb_spi.c linux-2.6.28.6/drivers/video/samsung/s3cfb_spi.c +--- linux-2.6.28/drivers/video/samsung/s3cfb_spi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/drivers/video/samsung/s3cfb_spi.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,277 @@ ++/* ++ * drivers/video/s3c/s3c24xxfb_spi.c ++ * ++ * $Id: s3cfb_spi.c,v 1.1 2008/11/17 11:12:08 jsgood Exp $ ++ * ++ * Copyright (C) 2008 Jinsung Yang ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive for ++ * more details. ++ * ++ * S3C Frame Buffer Driver ++ * based on skeletonfb.c, sa1100fb.h, s3c2410fb.c ++ */ ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#if 0 //defined(CONFIG_PLAT_S3C24XX) ++ ++#define S3CFB_SPI_CLK(x) (S3C2443_GPL10 + (ch * 0)) ++#define S3CFB_SPI_MOSI(x) (S3C2443_GPL11 + (ch * 0)) ++#define S3CFB_SPI_CS(x) (S3C2443_GPL14 + (ch * 0)) ++ ++static inline void s3cfb_spi_lcd_dclk(int ch, int value) ++{ ++ s3c2410_gpio_setpin(S3CFB_SPI_CLK(ch), value); ++} ++ ++static inline void s3cfb_spi_lcd_dseri(int ch, int value) ++{ ++ s3c2410_gpio_setpin(S3CFB_SPI_MOSI(ch), value); ++} ++ ++static inline void s3cfb_spi_lcd_den(int ch, int value) ++{ ++ s3c2410_gpio_setpin(S3CFB_SPI_CS(ch), value); ++} ++ ++static inline void s3cfb_spi_set_lcd_data(int ch) ++{ ++ s3c2410_gpio_cfgpin(S3CFB_SPI_CLK(ch), 1); ++ s3c2410_gpio_cfgpin(S3CFB_SPI_MOSI(ch), 1); ++ s3c2410_gpio_cfgpin(S3CFB_SPI_CS(ch), 1); ++ ++ s3c2410_gpio_pullup(S3CFB_SPI_CLK(ch), 2); ++ s3c2410_gpio_pullup(S3CFB_SPI_MOSI(ch), 2); ++ s3c2410_gpio_pullup(S3CFB_SPI_CS(ch), 2); ++} ++ ++#elif defined(CONFIG_PLAT_S3C64XX) || defined(CONFIG_PLAT_S5P64XX) ++ ++#if defined(CONFIG_PLAT_S5P64XX) ++#define S3CFB_SPI_CLK(x) (S5P64XX_GPN(2 + (x * 4))) ++#define S3CFB_SPI_MOSI(x) (S5P64XX_GPN(3 + (x * 4))) ++#define S3CFB_SPI_CS(x) (S5P64XX_GPN(1 + (x * 4))) ++ ++int s3cfb_spi_gpio_request(int ch) ++{ ++ int err = 0; ++ ++ if (gpio_is_valid(S3CFB_SPI_CLK(ch))) { ++ err = gpio_request(S3CFB_SPI_CLK(ch), "GPN"); ++ ++ if (err) ++ goto err_clk; ++ } else { ++ err = 1; ++ goto err_clk; ++ } ++ ++ if (gpio_is_valid(S3CFB_SPI_MOSI(ch))) { ++ err = gpio_request(S3CFB_SPI_MOSI(ch), "GPN"); ++ ++ if (err) ++ goto err_mosi; ++ } else { ++ err = 1; ++ goto err_mosi; ++ } ++ ++ if (gpio_is_valid(S3CFB_SPI_CS(ch))) { ++ err = gpio_request(S3CFB_SPI_CS(ch), "GPN"); ++ ++ if (err) ++ goto err_cs; ++ } else { ++ err = 1; ++ goto err_cs; ++ } ++ ++err_cs: ++ gpio_free(S3CFB_SPI_MOSI(ch)); ++ ++err_mosi: ++ gpio_free(S3CFB_SPI_CLK(ch)); ++ ++err_clk: ++ return err; ++ ++} ++ ++#elif defined(CONFIG_PLAT_S3C64XX) ++#define S3CFB_SPI_CLK(x) (S3C64XX_GPC(1 + (x * 4))) ++#define S3CFB_SPI_MOSI(x) (S3C64XX_GPC(2 + (x * 4))) ++#define S3CFB_SPI_CS(x) (S3C64XX_GPC(3 + (x * 4))) ++ ++int s3cfb_spi_gpio_request(int ch) ++{ ++ int err = 0; ++ ++ if (gpio_is_valid(S3CFB_SPI_CLK(ch))) { ++ err = gpio_request(S3CFB_SPI_CLK(ch), "GPC"); ++ ++ if (err) ++ goto err_clk; ++ } else { ++ err = 1; ++ goto err_clk; ++ } ++ ++ if (gpio_is_valid(S3CFB_SPI_MOSI(ch))) { ++ err = gpio_request(S3CFB_SPI_MOSI(ch), "GPC"); ++ ++ if (err) ++ goto err_mosi; ++ } else { ++ err = 1; ++ goto err_mosi; ++ } ++ ++ if (gpio_is_valid(S3CFB_SPI_CS(ch))) { ++ err = gpio_request(S3CFB_SPI_CS(ch), "GPC"); ++ ++ if (err) ++ goto err_cs; ++ } else { ++ err = 1; ++ goto err_cs; ++ } ++ ++err_cs: ++ gpio_free(S3CFB_SPI_MOSI(ch)); ++ ++err_mosi: ++ gpio_free(S3CFB_SPI_CLK(ch)); ++ ++err_clk: ++ return err; ++ ++} ++#endif ++ ++inline void s3cfb_spi_lcd_dclk(int ch, int value) ++{ ++ gpio_set_value(S3CFB_SPI_CLK(ch), value); ++} ++ ++inline void s3cfb_spi_lcd_dseri(int ch, int value) ++{ ++ gpio_set_value(S3CFB_SPI_MOSI(ch), value); ++} ++ ++inline void s3cfb_spi_lcd_den(int ch, int value) ++{ ++ gpio_set_value(S3CFB_SPI_CS(ch), value); ++} ++ ++inline void s3cfb_spi_set_lcd_data(int ch) ++{ ++ gpio_direction_output(S3CFB_SPI_CLK(ch), 1); ++ gpio_direction_output(S3CFB_SPI_MOSI(ch), 1); ++ gpio_direction_output(S3CFB_SPI_CS(ch), 1); ++ ++ s3c_gpio_setpull(S3CFB_SPI_CLK(ch), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S3CFB_SPI_MOSI(ch), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S3CFB_SPI_CS(ch), S3C_GPIO_PULL_NONE); ++} ++ ++void s3cfb_spi_gpio_free(int ch) ++{ ++ gpio_free(S3CFB_SPI_CLK(ch)); ++ gpio_free(S3CFB_SPI_MOSI(ch)); ++ gpio_free(S3CFB_SPI_CS(ch)); ++} ++ ++#elif defined(CONFIG_PLAT_S5PC1XX) ++ ++#define S5P_FB_SPI_CLK(x) (S5PC1XX_GPB(1 + (x * 4))) ++#define S5P_FB_SPI_MOSI(x) (S5PC1XX_GPB(2 + (x * 4))) ++#define S5P_FB_SPI_CS(x) (S5PC1XX_GPB(3 + (x * 4))) ++ ++int s3cfb_spi_gpio_request(int ch) ++{ ++ int err = 0; ++ ++ if (gpio_is_valid(S5P_FB_SPI_CLK(ch))) { ++ err = gpio_request(S5P_FB_SPI_CLK(ch), "GPB"); ++ ++ if (err) ++ goto err_clk; ++ } else { ++ err = 1; ++ goto err_clk; ++ } ++ ++ if (gpio_is_valid(S5P_FB_SPI_MOSI(ch))) { ++ err = gpio_request(S5P_FB_SPI_MOSI(ch), "GPB"); ++ ++ if (err) ++ goto err_mosi; ++ } else { ++ err = 1; ++ goto err_mosi; ++ } ++ ++ if (gpio_is_valid(S5P_FB_SPI_CS(ch))) { ++ err = gpio_request(S5P_FB_SPI_CS(ch), "GPB"); ++ ++ if (err) ++ goto err_cs; ++ } else { ++ err = 1; ++ goto err_cs; ++ } ++ ++err_cs: ++ gpio_free(S5P_FB_SPI_MOSI(ch)); ++ ++err_mosi: ++ gpio_free(S5P_FB_SPI_CLK(ch)); ++ ++err_clk: ++ return err; ++ ++} ++ ++inline void s3cfb_spi_lcd_dclk(int ch, int value) ++{ ++ gpio_set_value(S5P_FB_SPI_CLK(ch), value); ++} ++ ++inline void s3cfb_spi_lcd_dseri(int ch, int value) ++{ ++ gpio_set_value(S5P_FB_SPI_MOSI(ch), value); ++} ++ ++inline void s3cfb_spi_lcd_den(int ch, int value) ++{ ++ gpio_set_value(S5P_FB_SPI_CS(ch), value); ++} ++ ++inline void s3cfb_spi_set_lcd_data(int ch) ++{ ++ gpio_direction_output(S5P_FB_SPI_CLK(ch), 1); ++ gpio_direction_output(S5P_FB_SPI_MOSI(ch), 1); ++ gpio_direction_output(S5P_FB_SPI_CS(ch), 1); ++ ++ s3c_gpio_setpull(S5P_FB_SPI_CLK(ch), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S5P_FB_SPI_MOSI(ch), S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S5P_FB_SPI_CS(ch), S3C_GPIO_PULL_NONE); ++} ++ ++void s3cfb_spi_gpio_free(int ch) ++{ ++ gpio_free(S5P_FB_SPI_CLK(ch)); ++ gpio_free(S5P_FB_SPI_MOSI(ch)); ++ gpio_free(S5P_FB_SPI_CS(ch)); ++} ++ ++#endif ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/watchdog/Kconfig linux-2.6.28.6/drivers/watchdog/Kconfig +--- linux-2.6.28/drivers/watchdog/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/watchdog/Kconfig 2009-04-30 09:36:39.000000000 +0200 +@@ -132,10 +132,10 @@ + system when the timeout is reached. + + config S3C2410_WATCHDOG +- tristate "S3C2410 Watchdog" +- depends on ARCH_S3C2410 ++ tristate "Samsung SoC Watchdog" ++ depends on ARCH_S3C2410 || ARCH_S3C64XX || ARCH_S5PC1XX || ARCH_S5P64XX + help +- Watchdog timer block in the Samsung S3C2410 chips. This will ++ Watchdog timer block in the Samsung chips. This will + reboot the system when the timer expires with the watchdog + enabled. + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/drivers/watchdog/s3c2410_wdt.c linux-2.6.28.6/drivers/watchdog/s3c2410_wdt.c +--- linux-2.6.28/drivers/watchdog/s3c2410_wdt.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/drivers/watchdog/s3c2410_wdt.c 2009-10-20 07:50:57.000000000 +0200 +@@ -42,7 +42,7 @@ + #undef S3C_VA_WATCHDOG + #define S3C_VA_WATCHDOG (0) + +-#include ++#include + + #define PFX "s3c2410-wdt: " + +@@ -205,6 +205,8 @@ + + static int s3c2410wdt_open(struct inode *inode, struct file *file) + { ++ ++ printk("s3c2410wdt_open.\n"); + if (test_and_set_bit(0, &open_lock)) + return -EBUSY; + +@@ -242,6 +244,7 @@ + /* + * Refresh the timer. + */ ++ printk("s3c2410wdt_write.\n"); + if (len) { + if (!nowayout) { + size_t i; +@@ -279,6 +282,8 @@ + int __user *p = argp; + int new_margin; + ++ printk("s3c2410wdt_ioctl.\n"); ++ + switch (cmd) { + case WDIOC_GETSUPPORT: + return copy_to_user(argp, &s3c2410_wdt_ident, +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/Kconfig linux-2.6.28.6/fs/Kconfig +--- linux-2.6.28/fs/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/fs/Kconfig 2009-04-30 09:36:39.000000000 +0200 +@@ -907,6 +907,10 @@ + To compile the EFS file system support as a module, choose M here: the + module will be called efs. + ++ ++# Patched by YAFFS ++source "fs/yaffs2/Kconfig" ++ + source "fs/jffs2/Kconfig" + # UBIFS File system configuration + source "fs/ubifs/Kconfig" +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/Makefile linux-2.6.28.6/fs/Makefile +--- linux-2.6.28/fs/Makefile 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/fs/Makefile 2009-04-30 09:36:39.000000000 +0200 +@@ -122,3 +122,6 @@ + obj-$(CONFIG_DEBUG_FS) += debugfs/ + obj-$(CONFIG_OCFS2_FS) += ocfs2/ + obj-$(CONFIG_GFS2_FS) += gfs2/ ++ ++# Patched by YAFFS ++obj-$(CONFIG_YAFFS_FS) += yaffs2/ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/jffs2/scan.c linux-2.6.28.6/fs/jffs2/scan.c +--- linux-2.6.28/fs/jffs2/scan.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/fs/jffs2/scan.c 2009-04-30 09:36:39.000000000 +0200 +@@ -647,8 +647,8 @@ + inbuf_ofs = ofs - buf_ofs; + while (inbuf_ofs < scan_end) { + if (unlikely(*(uint32_t *)(&buf[inbuf_ofs]) != 0xffffffff)) { +- printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n", +- empty_start, ofs); ++ /* printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n", ++ empty_start, ofs); */ + if ((err = jffs2_scan_dirty_space(c, jeb, ofs-empty_start))) + return err; + goto scan_more; +@@ -835,8 +835,8 @@ + case JFFS2_NODETYPE_CLEANMARKER: + D1(printk(KERN_DEBUG "CLEANMARKER node found at 0x%08x\n", ofs)); + if (je32_to_cpu(node->totlen) != c->cleanmarker_size) { +- printk(KERN_NOTICE "CLEANMARKER node found at 0x%08x has totlen 0x%x != normal 0x%x\n", +- ofs, je32_to_cpu(node->totlen), c->cleanmarker_size); ++ /* printk(KERN_NOTICE "CLEANMARKER node found at 0x%08x has totlen 0x%x != normal 0x%x\n", ++ ofs, je32_to_cpu(node->totlen), c->cleanmarker_size); */ + if ((err = jffs2_scan_dirty_space(c, jeb, PAD(sizeof(struct jffs2_unknown_node))))) + return err; + ofs += PAD(sizeof(struct jffs2_unknown_node)); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/Kconfig linux-2.6.28.6/fs/yaffs2/Kconfig +--- linux-2.6.28/fs/yaffs2/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/Kconfig 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,156 @@ ++# ++# YAFFS file system configurations ++# ++ ++config YAFFS_FS ++ tristate "YAFFS2 file system support" ++ default n ++ depends on MTD_BLOCK ++ select YAFFS_YAFFS1 ++ select YAFFS_YAFFS2 ++ help ++ YAFFS2, or Yet Another Flash Filing System, is a filing system ++ optimised for NAND Flash chips. ++ ++ To compile the YAFFS2 file system support as a module, choose M ++ here: the module will be called yaffs2. ++ ++ If unsure, say N. ++ ++ Further information on YAFFS2 is available at ++ . ++ ++config YAFFS_YAFFS1 ++ bool "512 byte / page devices" ++ depends on YAFFS_FS ++ default y ++ help ++ Enable YAFFS1 support -- yaffs for 512 byte / page devices ++ ++ Not needed for 2K-page devices. ++ ++ If unsure, say Y. ++ ++config YAFFS_9BYTE_TAGS ++ bool "Use older-style on-NAND data format with pageStatus byte" ++ depends on YAFFS_YAFFS1 ++ default n ++ help ++ ++ Older-style on-NAND data format has a "pageStatus" byte to record ++ chunk/page state. This byte is zero when the page is discarded. ++ Choose this option if you have existing on-NAND data using this ++ format that you need to continue to support. New data written ++ also uses the older-style format. Note: Use of this option ++ generally requires that MTD's oob layout be adjusted to use the ++ older-style format. See notes on tags formats and MTD versions ++ in yaffs_mtdif1.c. ++ ++ If unsure, say N. ++ ++config YAFFS_DOES_ECC ++ bool "Lets Yaffs do its own ECC" ++ depends on YAFFS_FS && YAFFS_YAFFS1 && !YAFFS_9BYTE_TAGS ++ default n ++ help ++ This enables Yaffs to use its own ECC functions instead of using ++ the ones from the generic MTD-NAND driver. ++ ++ If unsure, say N. ++ ++config YAFFS_ECC_WRONG_ORDER ++ bool "Use the same ecc byte order as Steven Hill's nand_ecc.c" ++ depends on YAFFS_FS && YAFFS_DOES_ECC && !YAFFS_9BYTE_TAGS ++ default n ++ help ++ This makes yaffs_ecc.c use the same ecc byte order as Steven ++ Hill's nand_ecc.c. If not set, then you get the same ecc byte ++ order as SmartMedia. ++ ++ If unsure, say N. ++ ++config YAFFS_YAFFS2 ++ bool "2048 byte (or larger) / page devices" ++ depends on YAFFS_FS ++ default y ++ help ++ Enable YAFFS2 support -- yaffs for >= 2K bytes per page devices ++ ++ If unsure, say Y. ++ ++config YAFFS_AUTO_YAFFS2 ++ bool "Autoselect yaffs2 format" ++ depends on YAFFS_YAFFS2 ++ default y ++ help ++ Without this, you need to explicitely use yaffs2 as the file ++ system type. With this, you can say "yaffs" and yaffs or yaffs2 ++ will be used depending on the device page size (yaffs on ++ 512-byte page devices, yaffs2 on 2K page devices). ++ ++ If unsure, say Y. ++ ++config YAFFS_DISABLE_LAZY_LOAD ++ bool "Disable lazy loading" ++ depends on YAFFS_YAFFS2 ++ default n ++ help ++ "Lazy loading" defers loading file details until they are ++ required. This saves mount time, but makes the first look-up ++ a bit longer. ++ ++ Lazy loading will only happen if enabled by this option being 'n' ++ and if the appropriate tags are available, else yaffs2 will ++ automatically fall back to immediate loading and do the right ++ thing. ++ ++ Lazy laoding will be required by checkpointing. ++ ++ Setting this to 'y' will disable lazy loading. ++ ++ If unsure, say N. ++ ++ ++config YAFFS_DISABLE_WIDE_TNODES ++ bool "Turn off wide tnodes" ++ depends on YAFFS_FS ++ default n ++ help ++ Wide tnodes are only used for NAND arrays >=32MB for 512-byte ++ page devices and >=128MB for 2k page devices. They use slightly ++ more RAM but are faster since they eliminate chunk group ++ searching. ++ ++ Setting this to 'y' will force tnode width to 16 bits and save ++ memory but make large arrays slower. ++ ++ If unsure, say N. ++ ++config YAFFS_ALWAYS_CHECK_CHUNK_ERASED ++ bool "Force chunk erase check" ++ depends on YAFFS_FS ++ default n ++ help ++ Normally YAFFS only checks chunks before writing until an erased ++ chunk is found. This helps to detect any partially written ++ chunks that might have happened due to power loss. ++ ++ Enabling this forces on the test that chunks are erased in flash ++ before writing to them. This takes more time but is potentially ++ a bit more secure. ++ ++ Suggest setting Y during development and ironing out driver ++ issues etc. Suggest setting to N if you want faster writing. ++ ++ If unsure, say Y. ++ ++config YAFFS_SHORT_NAMES_IN_RAM ++ bool "Cache short names in RAM" ++ depends on YAFFS_FS ++ default y ++ help ++ If this config is set, then short names are stored with the ++ yaffs_Object. This costs an extra 16 bytes of RAM per object, ++ but makes look-ups faster. ++ ++ If unsure, say Y. +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/Makefile linux-2.6.28.6/fs/yaffs2/Makefile +--- linux-2.6.28/fs/yaffs2/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/Makefile 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,10 @@ ++# ++# Makefile for the linux YAFFS filesystem routines. ++# ++ ++obj-$(CONFIG_YAFFS_FS) += yaffs.o ++ ++yaffs-y := yaffs_ecc.o yaffs_fs.o yaffs_guts.o yaffs_checkptrw.o ++yaffs-y += yaffs_packedtags1.o yaffs_packedtags2.o yaffs_nand.o yaffs_qsort.o ++yaffs-y += yaffs_tagscompat.o yaffs_tagsvalidity.o ++yaffs-y += yaffs_mtdif.o yaffs_mtdif1.o yaffs_mtdif2.o +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/devextras.h linux-2.6.28.6/fs/yaffs2/devextras.h +--- linux-2.6.28/fs/yaffs2/devextras.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/devextras.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,199 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++/* ++ * This file is just holds extra declarations of macros that would normally ++ * be providesd in the Linux kernel. These macros have been written from ++ * scratch but are functionally equivalent to the Linux ones. ++ * ++ */ ++ ++#ifndef __EXTRAS_H__ ++#define __EXTRAS_H__ ++ ++ ++#if !(defined __KERNEL__) ++ ++/* Definition of types */ ++typedef unsigned char __u8; ++typedef unsigned short __u16; ++typedef unsigned __u32; ++ ++#endif ++ ++/* ++ * This is a simple doubly linked list implementation that matches the ++ * way the Linux kernel doubly linked list implementation works. ++ */ ++ ++struct ylist_head { ++ struct ylist_head *next; /* next in chain */ ++ struct ylist_head *prev; /* previous in chain */ ++}; ++ ++ ++/* Initialise a static list */ ++#define YLIST_HEAD(name) \ ++struct ylist_head name = { &(name),&(name)} ++ ++ ++ ++/* Initialise a list head to an empty list */ ++#define YINIT_LIST_HEAD(p) \ ++do { \ ++ (p)->next = (p);\ ++ (p)->prev = (p); \ ++} while(0) ++ ++ ++/* Add an element to a list */ ++static __inline__ void ylist_add(struct ylist_head *newEntry, ++ struct ylist_head *list) ++{ ++ struct ylist_head *listNext = list->next; ++ ++ list->next = newEntry; ++ newEntry->prev = list; ++ newEntry->next = listNext; ++ listNext->prev = newEntry; ++ ++} ++ ++static __inline__ void ylist_add_tail(struct ylist_head *newEntry, ++ struct ylist_head *list) ++{ ++ struct ylist_head *listPrev = list->prev; ++ ++ list->prev = newEntry; ++ newEntry->next = list; ++ newEntry->prev = listPrev; ++ listPrev->next = newEntry; ++ ++} ++ ++ ++/* Take an element out of its current list, with or without ++ * reinitialising the links.of the entry*/ ++static __inline__ void ylist_del(struct ylist_head *entry) ++{ ++ struct ylist_head *listNext = entry->next; ++ struct ylist_head *listPrev = entry->prev; ++ ++ listNext->prev = listPrev; ++ listPrev->next = listNext; ++ ++} ++ ++static __inline__ void ylist_del_init(struct ylist_head *entry) ++{ ++ ylist_del(entry); ++ entry->next = entry->prev = entry; ++} ++ ++ ++/* Test if the list is empty */ ++static __inline__ int ylist_empty(struct ylist_head *entry) ++{ ++ return (entry->next == entry); ++} ++ ++ ++/* ylist_entry takes a pointer to a list entry and offsets it to that ++ * we can find a pointer to the object it is embedded in. ++ */ ++ ++ ++#define ylist_entry(entry, type, member) \ ++ ((type *)((char *)(entry)-(unsigned long)(&((type *)NULL)->member))) ++ ++ ++/* ylist_for_each and list_for_each_safe iterate over lists. ++ * ylist_for_each_safe uses temporary storage to make the list delete safe ++ */ ++ ++#define ylist_for_each(itervar, list) \ ++ for (itervar = (list)->next; itervar != (list); itervar = itervar->next ) ++ ++#define ylist_for_each_safe(itervar,saveVar, list) \ ++ for (itervar = (list)->next, saveVar = (list)->next->next; itervar != (list); \ ++ itervar = saveVar, saveVar = saveVar->next) ++ ++ ++#if !(defined __KERNEL__) ++ ++ ++#ifndef WIN32 ++#include ++#endif ++ ++ ++#ifdef CONFIG_YAFFS_PROVIDE_DEFS ++/* File types */ ++ ++ ++#define DT_UNKNOWN 0 ++#define DT_FIFO 1 ++#define DT_CHR 2 ++#define DT_DIR 4 ++#define DT_BLK 6 ++#define DT_REG 8 ++#define DT_LNK 10 ++#define DT_SOCK 12 ++#define DT_WHT 14 ++ ++ ++#ifndef WIN32 ++#include ++#endif ++ ++/* ++ * Attribute flags. These should be or-ed together to figure out what ++ * has been changed! ++ */ ++#define ATTR_MODE 1 ++#define ATTR_UID 2 ++#define ATTR_GID 4 ++#define ATTR_SIZE 8 ++#define ATTR_ATIME 16 ++#define ATTR_MTIME 32 ++#define ATTR_CTIME 64 ++ ++struct iattr { ++ unsigned int ia_valid; ++ unsigned ia_mode; ++ unsigned ia_uid; ++ unsigned ia_gid; ++ unsigned ia_size; ++ unsigned ia_atime; ++ unsigned ia_mtime; ++ unsigned ia_ctime; ++ unsigned int ia_attr_flags; ++}; ++ ++#endif ++ ++ ++#define KERN_DEBUG ++ ++#else ++ ++#include ++#include ++#include ++ ++#endif ++ ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/moduleconfig.h linux-2.6.28.6/fs/yaffs2/moduleconfig.h +--- linux-2.6.28/fs/yaffs2/moduleconfig.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/moduleconfig.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,65 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Martin Fouts ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_CONFIG_H__ ++#define __YAFFS_CONFIG_H__ ++ ++#ifdef YAFFS_OUT_OF_TREE ++ ++/* DO NOT UNSET THESE THREE. YAFFS2 will not compile if you do. */ ++#define CONFIG_YAFFS_FS ++#define CONFIG_YAFFS_YAFFS1 ++#define CONFIG_YAFFS_YAFFS2 ++ ++/* These options are independent of each other. Select those that matter. */ ++ ++/* Default: Not selected */ ++/* Meaning: Yaffs does its own ECC, rather than using MTD ECC */ ++//#define CONFIG_YAFFS_DOES_ECC ++ ++/* Default: Not selected */ ++/* Meaning: ECC byte order is 'wrong'. Only meaningful if */ ++/* CONFIG_YAFFS_DOES_ECC is set */ ++//#define CONFIG_YAFFS_ECC_WRONG_ORDER ++ ++/* Default: Selected */ ++/* Meaning: Disables testing whether chunks are erased before writing to them*/ ++#define CONFIG_YAFFS_DISABLE_CHUNK_ERASED_CHECK ++ ++/* Default: Selected */ ++/* Meaning: Cache short names, taking more RAM, but faster look-ups */ ++#define CONFIG_YAFFS_SHORT_NAMES_IN_RAM ++ ++/* Default: 10 */ ++/* Meaning: set the count of blocks to reserve for checkpointing */ ++#define CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS 10 ++ ++/* ++Older-style on-NAND data format has a "pageStatus" byte to record ++chunk/page state. This byte is zeroed when the page is discarded. ++Choose this option if you have existing on-NAND data in this format ++that you need to continue to support. New data written also uses the ++older-style format. ++Note: Use of this option generally requires that MTD's oob layout be ++adjusted to use the older-style format. See notes on tags formats and ++MTD versions in yaffs_mtdif1.c. ++*/ ++/* Default: Not selected */ ++/* Meaning: Use older-style on-NAND data format with pageStatus byte */ ++//#define CONFIG_YAFFS_9BYTE_TAGS ++ ++#endif /* YAFFS_OUT_OF_TREE */ ++ ++#endif /* __YAFFS_CONFIG_H__ */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_checkptrw.c linux-2.6.28.6/fs/yaffs2/yaffs_checkptrw.c +--- linux-2.6.28/fs/yaffs2/yaffs_checkptrw.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_checkptrw.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,405 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++const char *yaffs_checkptrw_c_version = ++ "$Id: yaffs_checkptrw.c,v 1.17 2008/08/12 22:51:57 charles Exp $"; ++ ++ ++#include "yaffs_checkptrw.h" ++#include "yaffs_getblockinfo.h" ++ ++static int yaffs_CheckpointSpaceOk(yaffs_Device *dev) ++{ ++ ++ int blocksAvailable = dev->nErasedBlocks - dev->nReservedBlocks; ++ ++ T(YAFFS_TRACE_CHECKPOINT, ++ (TSTR("checkpt blocks available = %d" TENDSTR), ++ blocksAvailable)); ++ ++ ++ return (blocksAvailable <= 0) ? 0 : 1; ++} ++ ++ ++static int yaffs_CheckpointErase(yaffs_Device *dev) ++{ ++ ++ int i; ++ ++ ++ if(!dev->eraseBlockInNAND) ++ return 0; ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("checking blocks %d to %d"TENDSTR), ++ dev->internalStartBlock,dev->internalEndBlock)); ++ ++ for(i = dev->internalStartBlock; i <= dev->internalEndBlock; i++) { ++ yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev,i); ++ if(bi->blockState == YAFFS_BLOCK_STATE_CHECKPOINT){ ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("erasing checkpt block %d"TENDSTR),i)); ++ if(dev->eraseBlockInNAND(dev,i- dev->blockOffset /* realign */)){ ++ bi->blockState = YAFFS_BLOCK_STATE_EMPTY; ++ dev->nErasedBlocks++; ++ dev->nFreeChunks += dev->nChunksPerBlock; ++ } ++ else { ++ dev->markNANDBlockBad(dev,i); ++ bi->blockState = YAFFS_BLOCK_STATE_DEAD; ++ } ++ } ++ } ++ ++ dev->blocksInCheckpoint = 0; ++ ++ return 1; ++} ++ ++ ++static void yaffs_CheckpointFindNextErasedBlock(yaffs_Device *dev) ++{ ++ int i; ++ int blocksAvailable = dev->nErasedBlocks - dev->nReservedBlocks; ++ T(YAFFS_TRACE_CHECKPOINT, ++ (TSTR("allocating checkpt block: erased %d reserved %d avail %d next %d "TENDSTR), ++ dev->nErasedBlocks,dev->nReservedBlocks,blocksAvailable,dev->checkpointNextBlock)); ++ ++ if(dev->checkpointNextBlock >= 0 && ++ dev->checkpointNextBlock <= dev->internalEndBlock && ++ blocksAvailable > 0){ ++ ++ for(i = dev->checkpointNextBlock; i <= dev->internalEndBlock; i++){ ++ yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev,i); ++ if(bi->blockState == YAFFS_BLOCK_STATE_EMPTY){ ++ dev->checkpointNextBlock = i + 1; ++ dev->checkpointCurrentBlock = i; ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("allocating checkpt block %d"TENDSTR),i)); ++ return; ++ } ++ } ++ } ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("out of checkpt blocks"TENDSTR))); ++ ++ dev->checkpointNextBlock = -1; ++ dev->checkpointCurrentBlock = -1; ++} ++ ++static void yaffs_CheckpointFindNextCheckpointBlock(yaffs_Device *dev) ++{ ++ int i; ++ yaffs_ExtendedTags tags; ++ ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("find next checkpt block: start: blocks %d next %d" TENDSTR), ++ dev->blocksInCheckpoint, dev->checkpointNextBlock)); ++ ++ if(dev->blocksInCheckpoint < dev->checkpointMaxBlocks) ++ for(i = dev->checkpointNextBlock; i <= dev->internalEndBlock; i++){ ++ int chunk = i * dev->nChunksPerBlock; ++ int realignedChunk = chunk - dev->chunkOffset; ++ ++ dev->readChunkWithTagsFromNAND(dev,realignedChunk,NULL,&tags); ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("find next checkpt block: search: block %d oid %d seq %d eccr %d" TENDSTR), ++ i, tags.objectId,tags.sequenceNumber,tags.eccResult)); ++ ++ if(tags.sequenceNumber == YAFFS_SEQUENCE_CHECKPOINT_DATA){ ++ /* Right kind of block */ ++ dev->checkpointNextBlock = tags.objectId; ++ dev->checkpointCurrentBlock = i; ++ dev->checkpointBlockList[dev->blocksInCheckpoint] = i; ++ dev->blocksInCheckpoint++; ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("found checkpt block %d"TENDSTR),i)); ++ return; ++ } ++ } ++ ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("found no more checkpt blocks"TENDSTR))); ++ ++ dev->checkpointNextBlock = -1; ++ dev->checkpointCurrentBlock = -1; ++} ++ ++ ++int yaffs_CheckpointOpen(yaffs_Device *dev, int forWriting) ++{ ++ ++ /* Got the functions we need? */ ++ if (!dev->writeChunkWithTagsToNAND || ++ !dev->readChunkWithTagsFromNAND || ++ !dev->eraseBlockInNAND || ++ !dev->markNANDBlockBad) ++ return 0; ++ ++ if(forWriting && !yaffs_CheckpointSpaceOk(dev)) ++ return 0; ++ ++ if(!dev->checkpointBuffer) ++ dev->checkpointBuffer = YMALLOC_DMA(dev->totalBytesPerChunk); ++ if(!dev->checkpointBuffer) ++ return 0; ++ ++ ++ dev->checkpointPageSequence = 0; ++ ++ dev->checkpointOpenForWrite = forWriting; ++ ++ dev->checkpointByteCount = 0; ++ dev->checkpointSum = 0; ++ dev->checkpointXor = 0; ++ dev->checkpointCurrentBlock = -1; ++ dev->checkpointCurrentChunk = -1; ++ dev->checkpointNextBlock = dev->internalStartBlock; ++ ++ /* Erase all the blocks in the checkpoint area */ ++ if(forWriting){ ++ memset(dev->checkpointBuffer,0,dev->nDataBytesPerChunk); ++ dev->checkpointByteOffset = 0; ++ return yaffs_CheckpointErase(dev); ++ ++ ++ } else { ++ int i; ++ /* Set to a value that will kick off a read */ ++ dev->checkpointByteOffset = dev->nDataBytesPerChunk; ++ /* A checkpoint block list of 1 checkpoint block per 16 block is (hopefully) ++ * going to be way more than we need */ ++ dev->blocksInCheckpoint = 0; ++ dev->checkpointMaxBlocks = (dev->internalEndBlock - dev->internalStartBlock)/16 + 2; ++ dev->checkpointBlockList = YMALLOC(sizeof(int) * dev->checkpointMaxBlocks); ++ for(i = 0; i < dev->checkpointMaxBlocks; i++) ++ dev->checkpointBlockList[i] = -1; ++ } ++ ++ return 1; ++} ++ ++int yaffs_GetCheckpointSum(yaffs_Device *dev, __u32 *sum) ++{ ++ __u32 compositeSum; ++ compositeSum = (dev->checkpointSum << 8) | (dev->checkpointXor & 0xFF); ++ *sum = compositeSum; ++ return 1; ++} ++ ++static int yaffs_CheckpointFlushBuffer(yaffs_Device *dev) ++{ ++ ++ int chunk; ++ int realignedChunk; ++ ++ yaffs_ExtendedTags tags; ++ ++ if(dev->checkpointCurrentBlock < 0){ ++ yaffs_CheckpointFindNextErasedBlock(dev); ++ dev->checkpointCurrentChunk = 0; ++ } ++ ++ if(dev->checkpointCurrentBlock < 0) ++ return 0; ++ ++ tags.chunkDeleted = 0; ++ tags.objectId = dev->checkpointNextBlock; /* Hint to next place to look */ ++ tags.chunkId = dev->checkpointPageSequence + 1; ++ tags.sequenceNumber = YAFFS_SEQUENCE_CHECKPOINT_DATA; ++ tags.byteCount = dev->nDataBytesPerChunk; ++ if(dev->checkpointCurrentChunk == 0){ ++ /* First chunk we write for the block? Set block state to ++ checkpoint */ ++ yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev,dev->checkpointCurrentBlock); ++ bi->blockState = YAFFS_BLOCK_STATE_CHECKPOINT; ++ dev->blocksInCheckpoint++; ++ } ++ ++ chunk = dev->checkpointCurrentBlock * dev->nChunksPerBlock + dev->checkpointCurrentChunk; ++ ++ ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("checkpoint wite buffer nand %d(%d:%d) objid %d chId %d" TENDSTR), ++ chunk, dev->checkpointCurrentBlock, dev->checkpointCurrentChunk,tags.objectId,tags.chunkId)); ++ ++ realignedChunk = chunk - dev->chunkOffset; ++ ++ dev->writeChunkWithTagsToNAND(dev,realignedChunk,dev->checkpointBuffer,&tags); ++ dev->checkpointByteOffset = 0; ++ dev->checkpointPageSequence++; ++ dev->checkpointCurrentChunk++; ++ if(dev->checkpointCurrentChunk >= dev->nChunksPerBlock){ ++ dev->checkpointCurrentChunk = 0; ++ dev->checkpointCurrentBlock = -1; ++ } ++ memset(dev->checkpointBuffer,0,dev->nDataBytesPerChunk); ++ ++ return 1; ++} ++ ++ ++int yaffs_CheckpointWrite(yaffs_Device *dev,const void *data, int nBytes) ++{ ++ int i=0; ++ int ok = 1; ++ ++ ++ __u8 * dataBytes = (__u8 *)data; ++ ++ ++ ++ if(!dev->checkpointBuffer) ++ return 0; ++ ++ if(!dev->checkpointOpenForWrite) ++ return -1; ++ ++ while(i < nBytes && ok) { ++ ++ ++ ++ dev->checkpointBuffer[dev->checkpointByteOffset] = *dataBytes ; ++ dev->checkpointSum += *dataBytes; ++ dev->checkpointXor ^= *dataBytes; ++ ++ dev->checkpointByteOffset++; ++ i++; ++ dataBytes++; ++ dev->checkpointByteCount++; ++ ++ ++ if(dev->checkpointByteOffset < 0 || ++ dev->checkpointByteOffset >= dev->nDataBytesPerChunk) ++ ok = yaffs_CheckpointFlushBuffer(dev); ++ ++ } ++ ++ return i; ++} ++ ++int yaffs_CheckpointRead(yaffs_Device *dev, void *data, int nBytes) ++{ ++ int i=0; ++ int ok = 1; ++ yaffs_ExtendedTags tags; ++ ++ ++ int chunk; ++ int realignedChunk; ++ ++ __u8 *dataBytes = (__u8 *)data; ++ ++ if(!dev->checkpointBuffer) ++ return 0; ++ ++ if(dev->checkpointOpenForWrite) ++ return -1; ++ ++ while(i < nBytes && ok) { ++ ++ ++ if(dev->checkpointByteOffset < 0 || ++ dev->checkpointByteOffset >= dev->nDataBytesPerChunk) { ++ ++ if(dev->checkpointCurrentBlock < 0){ ++ yaffs_CheckpointFindNextCheckpointBlock(dev); ++ dev->checkpointCurrentChunk = 0; ++ } ++ ++ if(dev->checkpointCurrentBlock < 0) ++ ok = 0; ++ else { ++ ++ chunk = dev->checkpointCurrentBlock * dev->nChunksPerBlock + ++ dev->checkpointCurrentChunk; ++ ++ realignedChunk = chunk - dev->chunkOffset; ++ ++ /* read in the next chunk */ ++ /* printf("read checkpoint page %d\n",dev->checkpointPage); */ ++ dev->readChunkWithTagsFromNAND(dev, realignedChunk, ++ dev->checkpointBuffer, ++ &tags); ++ ++ if(tags.chunkId != (dev->checkpointPageSequence + 1) || ++ tags.eccResult > YAFFS_ECC_RESULT_FIXED || ++ tags.sequenceNumber != YAFFS_SEQUENCE_CHECKPOINT_DATA) ++ ok = 0; ++ ++ dev->checkpointByteOffset = 0; ++ dev->checkpointPageSequence++; ++ dev->checkpointCurrentChunk++; ++ ++ if(dev->checkpointCurrentChunk >= dev->nChunksPerBlock) ++ dev->checkpointCurrentBlock = -1; ++ } ++ } ++ ++ if(ok){ ++ *dataBytes = dev->checkpointBuffer[dev->checkpointByteOffset]; ++ dev->checkpointSum += *dataBytes; ++ dev->checkpointXor ^= *dataBytes; ++ dev->checkpointByteOffset++; ++ i++; ++ dataBytes++; ++ dev->checkpointByteCount++; ++ } ++ } ++ ++ return i; ++} ++ ++int yaffs_CheckpointClose(yaffs_Device *dev) ++{ ++ ++ if(dev->checkpointOpenForWrite){ ++ if(dev->checkpointByteOffset != 0) ++ yaffs_CheckpointFlushBuffer(dev); ++ } else { ++ int i; ++ for(i = 0; i < dev->blocksInCheckpoint && dev->checkpointBlockList[i] >= 0; i++){ ++ yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev,dev->checkpointBlockList[i]); ++ if(bi->blockState == YAFFS_BLOCK_STATE_EMPTY) ++ bi->blockState = YAFFS_BLOCK_STATE_CHECKPOINT; ++ else { ++ // Todo this looks odd... ++ } ++ } ++ YFREE(dev->checkpointBlockList); ++ dev->checkpointBlockList = NULL; ++ } ++ ++ dev->nFreeChunks -= dev->blocksInCheckpoint * dev->nChunksPerBlock; ++ dev->nErasedBlocks -= dev->blocksInCheckpoint; ++ ++ ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("checkpoint byte count %d" TENDSTR), ++ dev->checkpointByteCount)); ++ ++ if(dev->checkpointBuffer){ ++ /* free the buffer */ ++ YFREE(dev->checkpointBuffer); ++ dev->checkpointBuffer = NULL; ++ return 1; ++ } ++ else ++ return 0; ++ ++} ++ ++int yaffs_CheckpointInvalidateStream(yaffs_Device *dev) ++{ ++ /* Erase the first checksum block */ ++ ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("checkpoint invalidate"TENDSTR))); ++ ++ if(!yaffs_CheckpointSpaceOk(dev)) ++ return 0; ++ ++ return yaffs_CheckpointErase(dev); ++} ++ ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_checkptrw.h linux-2.6.28.6/fs/yaffs2/yaffs_checkptrw.h +--- linux-2.6.28/fs/yaffs2/yaffs_checkptrw.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_checkptrw.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,35 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_CHECKPTRW_H__ ++#define __YAFFS_CHECKPTRW_H__ ++ ++#include "yaffs_guts.h" ++ ++int yaffs_CheckpointOpen(yaffs_Device *dev, int forWriting); ++ ++int yaffs_CheckpointWrite(yaffs_Device *dev,const void *data, int nBytes); ++ ++int yaffs_CheckpointRead(yaffs_Device *dev,void *data, int nBytes); ++ ++int yaffs_GetCheckpointSum(yaffs_Device *dev, __u32 *sum); ++ ++int yaffs_CheckpointClose(yaffs_Device *dev); ++ ++int yaffs_CheckpointInvalidateStream(yaffs_Device *dev); ++ ++ ++#endif ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_ecc.c linux-2.6.28.6/fs/yaffs2/yaffs_ecc.c +--- linux-2.6.28/fs/yaffs2/yaffs_ecc.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_ecc.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,331 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++/* ++ * This code implements the ECC algorithm used in SmartMedia. ++ * ++ * The ECC comprises 22 bits of parity information and is stuffed into 3 bytes. ++ * The two unused bit are set to 1. ++ * The ECC can correct single bit errors in a 256-byte page of data. Thus, two such ECC ++ * blocks are used on a 512-byte NAND page. ++ * ++ */ ++ ++/* Table generated by gen-ecc.c ++ * Using a table means we do not have to calculate p1..p4 and p1'..p4' ++ * for each byte of data. These are instead provided in a table in bits7..2. ++ * Bit 0 of each entry indicates whether the entry has an odd or even parity, and therefore ++ * this bytes influence on the line parity. ++ */ ++ ++const char *yaffs_ecc_c_version = ++ "$Id: yaffs_ecc.c,v 1.10 2007/12/13 15:35:17 wookey Exp $"; ++ ++#include "yportenv.h" ++ ++#include "yaffs_ecc.h" ++ ++static const unsigned char column_parity_table[] = { ++ 0x00, 0x55, 0x59, 0x0c, 0x65, 0x30, 0x3c, 0x69, ++ 0x69, 0x3c, 0x30, 0x65, 0x0c, 0x59, 0x55, 0x00, ++ 0x95, 0xc0, 0xcc, 0x99, 0xf0, 0xa5, 0xa9, 0xfc, ++ 0xfc, 0xa9, 0xa5, 0xf0, 0x99, 0xcc, 0xc0, 0x95, ++ 0x99, 0xcc, 0xc0, 0x95, 0xfc, 0xa9, 0xa5, 0xf0, ++ 0xf0, 0xa5, 0xa9, 0xfc, 0x95, 0xc0, 0xcc, 0x99, ++ 0x0c, 0x59, 0x55, 0x00, 0x69, 0x3c, 0x30, 0x65, ++ 0x65, 0x30, 0x3c, 0x69, 0x00, 0x55, 0x59, 0x0c, ++ 0xa5, 0xf0, 0xfc, 0xa9, 0xc0, 0x95, 0x99, 0xcc, ++ 0xcc, 0x99, 0x95, 0xc0, 0xa9, 0xfc, 0xf0, 0xa5, ++ 0x30, 0x65, 0x69, 0x3c, 0x55, 0x00, 0x0c, 0x59, ++ 0x59, 0x0c, 0x00, 0x55, 0x3c, 0x69, 0x65, 0x30, ++ 0x3c, 0x69, 0x65, 0x30, 0x59, 0x0c, 0x00, 0x55, ++ 0x55, 0x00, 0x0c, 0x59, 0x30, 0x65, 0x69, 0x3c, ++ 0xa9, 0xfc, 0xf0, 0xa5, 0xcc, 0x99, 0x95, 0xc0, ++ 0xc0, 0x95, 0x99, 0xcc, 0xa5, 0xf0, 0xfc, 0xa9, ++ 0xa9, 0xfc, 0xf0, 0xa5, 0xcc, 0x99, 0x95, 0xc0, ++ 0xc0, 0x95, 0x99, 0xcc, 0xa5, 0xf0, 0xfc, 0xa9, ++ 0x3c, 0x69, 0x65, 0x30, 0x59, 0x0c, 0x00, 0x55, ++ 0x55, 0x00, 0x0c, 0x59, 0x30, 0x65, 0x69, 0x3c, ++ 0x30, 0x65, 0x69, 0x3c, 0x55, 0x00, 0x0c, 0x59, ++ 0x59, 0x0c, 0x00, 0x55, 0x3c, 0x69, 0x65, 0x30, ++ 0xa5, 0xf0, 0xfc, 0xa9, 0xc0, 0x95, 0x99, 0xcc, ++ 0xcc, 0x99, 0x95, 0xc0, 0xa9, 0xfc, 0xf0, 0xa5, ++ 0x0c, 0x59, 0x55, 0x00, 0x69, 0x3c, 0x30, 0x65, ++ 0x65, 0x30, 0x3c, 0x69, 0x00, 0x55, 0x59, 0x0c, ++ 0x99, 0xcc, 0xc0, 0x95, 0xfc, 0xa9, 0xa5, 0xf0, ++ 0xf0, 0xa5, 0xa9, 0xfc, 0x95, 0xc0, 0xcc, 0x99, ++ 0x95, 0xc0, 0xcc, 0x99, 0xf0, 0xa5, 0xa9, 0xfc, ++ 0xfc, 0xa9, 0xa5, 0xf0, 0x99, 0xcc, 0xc0, 0x95, ++ 0x00, 0x55, 0x59, 0x0c, 0x65, 0x30, 0x3c, 0x69, ++ 0x69, 0x3c, 0x30, 0x65, 0x0c, 0x59, 0x55, 0x00, ++}; ++ ++/* Count the bits in an unsigned char or a U32 */ ++ ++static int yaffs_CountBits(unsigned char x) ++{ ++ int r = 0; ++ while (x) { ++ if (x & 1) ++ r++; ++ x >>= 1; ++ } ++ return r; ++} ++ ++static int yaffs_CountBits32(unsigned x) ++{ ++ int r = 0; ++ while (x) { ++ if (x & 1) ++ r++; ++ x >>= 1; ++ } ++ return r; ++} ++ ++/* Calculate the ECC for a 256-byte block of data */ ++void yaffs_ECCCalculate(const unsigned char *data, unsigned char *ecc) ++{ ++ unsigned int i; ++ ++ unsigned char col_parity = 0; ++ unsigned char line_parity = 0; ++ unsigned char line_parity_prime = 0; ++ unsigned char t; ++ unsigned char b; ++ ++ for (i = 0; i < 256; i++) { ++ b = column_parity_table[*data++]; ++ col_parity ^= b; ++ ++ if (b & 0x01) // odd number of bits in the byte ++ { ++ line_parity ^= i; ++ line_parity_prime ^= ~i; ++ } ++ ++ } ++ ++ ecc[2] = (~col_parity) | 0x03; ++ ++ t = 0; ++ if (line_parity & 0x80) ++ t |= 0x80; ++ if (line_parity_prime & 0x80) ++ t |= 0x40; ++ if (line_parity & 0x40) ++ t |= 0x20; ++ if (line_parity_prime & 0x40) ++ t |= 0x10; ++ if (line_parity & 0x20) ++ t |= 0x08; ++ if (line_parity_prime & 0x20) ++ t |= 0x04; ++ if (line_parity & 0x10) ++ t |= 0x02; ++ if (line_parity_prime & 0x10) ++ t |= 0x01; ++ ecc[1] = ~t; ++ ++ t = 0; ++ if (line_parity & 0x08) ++ t |= 0x80; ++ if (line_parity_prime & 0x08) ++ t |= 0x40; ++ if (line_parity & 0x04) ++ t |= 0x20; ++ if (line_parity_prime & 0x04) ++ t |= 0x10; ++ if (line_parity & 0x02) ++ t |= 0x08; ++ if (line_parity_prime & 0x02) ++ t |= 0x04; ++ if (line_parity & 0x01) ++ t |= 0x02; ++ if (line_parity_prime & 0x01) ++ t |= 0x01; ++ ecc[0] = ~t; ++ ++#ifdef CONFIG_YAFFS_ECC_WRONG_ORDER ++ // Swap the bytes into the wrong order ++ t = ecc[0]; ++ ecc[0] = ecc[1]; ++ ecc[1] = t; ++#endif ++} ++ ++ ++/* Correct the ECC on a 256 byte block of data */ ++ ++int yaffs_ECCCorrect(unsigned char *data, unsigned char *read_ecc, ++ const unsigned char *test_ecc) ++{ ++ unsigned char d0, d1, d2; /* deltas */ ++ ++ d0 = read_ecc[0] ^ test_ecc[0]; ++ d1 = read_ecc[1] ^ test_ecc[1]; ++ d2 = read_ecc[2] ^ test_ecc[2]; ++ ++ if ((d0 | d1 | d2) == 0) ++ return 0; /* no error */ ++ ++ if (((d0 ^ (d0 >> 1)) & 0x55) == 0x55 && ++ ((d1 ^ (d1 >> 1)) & 0x55) == 0x55 && ++ ((d2 ^ (d2 >> 1)) & 0x54) == 0x54) { ++ /* Single bit (recoverable) error in data */ ++ ++ unsigned byte; ++ unsigned bit; ++ ++#ifdef CONFIG_YAFFS_ECC_WRONG_ORDER ++ // swap the bytes to correct for the wrong order ++ unsigned char t; ++ ++ t = d0; ++ d0 = d1; ++ d1 = t; ++#endif ++ ++ bit = byte = 0; ++ ++ if (d1 & 0x80) ++ byte |= 0x80; ++ if (d1 & 0x20) ++ byte |= 0x40; ++ if (d1 & 0x08) ++ byte |= 0x20; ++ if (d1 & 0x02) ++ byte |= 0x10; ++ if (d0 & 0x80) ++ byte |= 0x08; ++ if (d0 & 0x20) ++ byte |= 0x04; ++ if (d0 & 0x08) ++ byte |= 0x02; ++ if (d0 & 0x02) ++ byte |= 0x01; ++ ++ if (d2 & 0x80) ++ bit |= 0x04; ++ if (d2 & 0x20) ++ bit |= 0x02; ++ if (d2 & 0x08) ++ bit |= 0x01; ++ ++ data[byte] ^= (1 << bit); ++ ++ return 1; /* Corrected the error */ ++ } ++ ++ if ((yaffs_CountBits(d0) + ++ yaffs_CountBits(d1) + ++ yaffs_CountBits(d2)) == 1) { ++ /* Reccoverable error in ecc */ ++ ++ read_ecc[0] = test_ecc[0]; ++ read_ecc[1] = test_ecc[1]; ++ read_ecc[2] = test_ecc[2]; ++ ++ return 1; /* Corrected the error */ ++ } ++ ++ /* Unrecoverable error */ ++ ++ return -1; ++ ++} ++ ++ ++/* ++ * ECCxxxOther does ECC calcs on arbitrary n bytes of data ++ */ ++void yaffs_ECCCalculateOther(const unsigned char *data, unsigned nBytes, ++ yaffs_ECCOther * eccOther) ++{ ++ unsigned int i; ++ ++ unsigned char col_parity = 0; ++ unsigned line_parity = 0; ++ unsigned line_parity_prime = 0; ++ unsigned char b; ++ ++ for (i = 0; i < nBytes; i++) { ++ b = column_parity_table[*data++]; ++ col_parity ^= b; ++ ++ if (b & 0x01) { ++ /* odd number of bits in the byte */ ++ line_parity ^= i; ++ line_parity_prime ^= ~i; ++ } ++ ++ } ++ ++ eccOther->colParity = (col_parity >> 2) & 0x3f; ++ eccOther->lineParity = line_parity; ++ eccOther->lineParityPrime = line_parity_prime; ++} ++ ++int yaffs_ECCCorrectOther(unsigned char *data, unsigned nBytes, ++ yaffs_ECCOther * read_ecc, ++ const yaffs_ECCOther * test_ecc) ++{ ++ unsigned char cDelta; /* column parity delta */ ++ unsigned lDelta; /* line parity delta */ ++ unsigned lDeltaPrime; /* line parity delta */ ++ unsigned bit; ++ ++ cDelta = read_ecc->colParity ^ test_ecc->colParity; ++ lDelta = read_ecc->lineParity ^ test_ecc->lineParity; ++ lDeltaPrime = read_ecc->lineParityPrime ^ test_ecc->lineParityPrime; ++ ++ if ((cDelta | lDelta | lDeltaPrime) == 0) ++ return 0; /* no error */ ++ ++ if (lDelta == ~lDeltaPrime && ++ (((cDelta ^ (cDelta >> 1)) & 0x15) == 0x15)) ++ { ++ /* Single bit (recoverable) error in data */ ++ ++ bit = 0; ++ ++ if (cDelta & 0x20) ++ bit |= 0x04; ++ if (cDelta & 0x08) ++ bit |= 0x02; ++ if (cDelta & 0x02) ++ bit |= 0x01; ++ ++ if(lDelta >= nBytes) ++ return -1; ++ ++ data[lDelta] ^= (1 << bit); ++ ++ return 1; /* corrected */ ++ } ++ ++ if ((yaffs_CountBits32(lDelta) + yaffs_CountBits32(lDeltaPrime) + ++ yaffs_CountBits(cDelta)) == 1) { ++ /* Reccoverable error in ecc */ ++ ++ *read_ecc = *test_ecc; ++ return 1; /* corrected */ ++ } ++ ++ /* Unrecoverable error */ ++ ++ return -1; ++ ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_ecc.h linux-2.6.28.6/fs/yaffs2/yaffs_ecc.h +--- linux-2.6.28/fs/yaffs2/yaffs_ecc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_ecc.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,44 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++ /* ++ * This code implements the ECC algorithm used in SmartMedia. ++ * ++ * The ECC comprises 22 bits of parity information and is stuffed into 3 bytes. ++ * The two unused bit are set to 1. ++ * The ECC can correct single bit errors in a 256-byte page of data. Thus, two such ECC ++ * blocks are used on a 512-byte NAND page. ++ * ++ */ ++ ++#ifndef __YAFFS_ECC_H__ ++#define __YAFFS_ECC_H__ ++ ++typedef struct { ++ unsigned char colParity; ++ unsigned lineParity; ++ unsigned lineParityPrime; ++} yaffs_ECCOther; ++ ++void yaffs_ECCCalculate(const unsigned char *data, unsigned char *ecc); ++int yaffs_ECCCorrect(unsigned char *data, unsigned char *read_ecc, ++ const unsigned char *test_ecc); ++ ++void yaffs_ECCCalculateOther(const unsigned char *data, unsigned nBytes, ++ yaffs_ECCOther * ecc); ++int yaffs_ECCCorrectOther(unsigned char *data, unsigned nBytes, ++ yaffs_ECCOther * read_ecc, ++ const yaffs_ECCOther * test_ecc); ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_fs.c linux-2.6.28.6/fs/yaffs2/yaffs_fs.c +--- linux-2.6.28/fs/yaffs2/yaffs_fs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_fs.c 2010-04-22 05:44:13.000000000 +0200 +@@ -0,0 +1,2572 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * Acknowledgements: ++ * Luc van OostenRyck for numerous patches. ++ * Nick Bane for numerous patches. ++ * Nick Bane for 2.5/2.6 integration. ++ * Andras Toth for mknod rdev issue. ++ * Michael Fischer for finding the problem with inode inconsistency. ++ * Some code bodily lifted from JFFS ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++/* ++ * ++ * This is the file system front-end to YAFFS that hooks it up to ++ * the VFS. ++ * ++ * Special notes: ++ * >> 2.4: sb->u.generic_sbp points to the yaffs_Device associated with ++ * this superblock ++ * >> 2.6: sb->s_fs_info points to the yaffs_Device associated with this ++ * superblock ++ * >> inode->u.generic_ip points to the associated yaffs_Object. ++ */ ++ ++const char *yaffs_fs_c_version = ++ "$Id: yaffs_fs.c,v 1.72 2009/02/04 21:40:27 charles Exp $"; ++extern const char *yaffs_guts_c_version; ++ ++#include ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "asm/div64.h" ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++ ++#include /* Added NCB 15-8-2003 */ ++#include ++#define UnlockPage(p) unlock_page(p) ++#define Page_Uptodate(page) test_bit(PG_uptodate, &(page)->flags) ++ ++/* FIXME: use sb->s_id instead ? */ ++#define yaffs_devname(sb, buf) bdevname(sb->s_bdev, buf) ++ ++#else ++ ++#include ++#define BDEVNAME_SIZE 0 ++#define yaffs_devname(sb, buf) kdevname(sb->s_dev) ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) ++/* added NCB 26/5/2006 for 2.4.25-vrs2-tcl1 kernel */ ++#define __user ++#endif ++ ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++#define YPROC_ROOT &proc_root ++#else ++#define YPROC_ROOT NULL ++#endif ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17)) ++#define WRITE_SIZE_STR "writesize" ++#define WRITE_SIZE(mtd) (mtd)->writesize ++#else ++#define WRITE_SIZE_STR "oobblock" ++#define WRITE_SIZE(mtd) (mtd)->oobblock ++#endif ++ ++#if(LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)) ++#define YAFFS_USE_WRITE_BEGIN_END 1 ++#else ++#define YAFFS_USE_WRITE_BEGIN_END 0 ++#endif ++ ++ ++#include ++ ++#include "yportenv.h" ++#include "yaffs_guts.h" ++ ++#include ++#include "yaffs_mtdif.h" ++#include "yaffs_mtdif1.h" ++#include "yaffs_mtdif2.h" ++ ++unsigned int yaffs_traceMask = 0; //YAFFS_TRACE_BAD_BLOCKS; ++unsigned int yaffs_wr_attempts = YAFFS_WR_ATTEMPTS; ++unsigned int yaffs_auto_checkpoint = 1; ++ ++/* Module Parameters */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++module_param(yaffs_traceMask,uint,0644); ++module_param(yaffs_wr_attempts,uint,0644); ++module_param(yaffs_auto_checkpoint,uint,0644); ++#else ++MODULE_PARM(yaffs_traceMask,"i"); ++MODULE_PARM(yaffs_wr_attempts,"i"); ++MODULE_PARM(yaffs_auto_checkpoint,"i"); ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)) ++/* use iget and read_inode */ ++#define Y_IGET(sb,inum) iget((sb),(inum)) ++static void yaffs_read_inode(struct inode *inode); ++ ++#else ++/* Call local equivalent */ ++#define YAFFS_USE_OWN_IGET ++#define Y_IGET(sb,inum) yaffs_iget((sb),(inum)) ++ ++static struct inode * yaffs_iget(struct super_block *sb, unsigned long ino); ++#endif ++ ++/*#define T(x) printk x */ ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)) ++#define yaffs_InodeToObjectLV(iptr) (iptr)->i_private ++#else ++#define yaffs_InodeToObjectLV(iptr) (iptr)->u.generic_ip ++#endif ++ ++#define yaffs_InodeToObject(iptr) ((yaffs_Object *)(yaffs_InodeToObjectLV(iptr))) ++#define yaffs_DentryToObject(dptr) yaffs_InodeToObject((dptr)->d_inode) ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++#define yaffs_SuperToDevice(sb) ((yaffs_Device *)sb->s_fs_info) ++#else ++#define yaffs_SuperToDevice(sb) ((yaffs_Device *)sb->u.generic_sbp) ++#endif ++ ++static void yaffs_put_super(struct super_block *sb); ++ ++static ssize_t yaffs_file_write(struct file *f, const char *buf, size_t n, ++ loff_t * pos); ++static ssize_t yaffs_hold_space(struct file *f); ++static void yaffs_release_space(struct file *f); ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17)) ++static int yaffs_file_flush(struct file *file, fl_owner_t id); ++#else ++static int yaffs_file_flush(struct file *file); ++#endif ++ ++static int yaffs_sync_object(struct file *file, struct dentry *dentry, ++ int datasync); ++ ++static int yaffs_readdir(struct file *f, void *dirent, filldir_t filldir); ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode, ++ struct nameidata *n); ++static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry, ++ struct nameidata *n); ++#else ++static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode); ++static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry); ++#endif ++static int yaffs_link(struct dentry *old_dentry, struct inode *dir, ++ struct dentry *dentry); ++static int yaffs_unlink(struct inode *dir, struct dentry *dentry); ++static int yaffs_symlink(struct inode *dir, struct dentry *dentry, ++ const char *symname); ++static int yaffs_mkdir(struct inode *dir, struct dentry *dentry, int mode); ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode, ++ dev_t dev); ++#else ++static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode, ++ int dev); ++#endif ++static int yaffs_rename(struct inode *old_dir, struct dentry *old_dentry, ++ struct inode *new_dir, struct dentry *new_dentry); ++static int yaffs_setattr(struct dentry *dentry, struct iattr *attr); ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17)) ++static int yaffs_sync_fs(struct super_block *sb, int wait); ++static void yaffs_write_super(struct super_block *sb); ++#else ++static int yaffs_sync_fs(struct super_block *sb); ++static int yaffs_write_super(struct super_block *sb); ++#endif ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17)) ++static int yaffs_statfs(struct dentry *dentry, struct kstatfs *buf); ++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++static int yaffs_statfs(struct super_block *sb, struct kstatfs *buf); ++#else ++static int yaffs_statfs(struct super_block *sb, struct statfs *buf); ++#endif ++ ++#ifdef YAFFS_HAS_PUT_INODE ++static void yaffs_put_inode(struct inode *inode); ++#endif ++ ++static void yaffs_delete_inode(struct inode *); ++static void yaffs_clear_inode(struct inode *); ++ ++static int yaffs_readpage(struct file *file, struct page *page); ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++static int yaffs_writepage(struct page *page, struct writeback_control *wbc); ++#else ++static int yaffs_writepage(struct page *page); ++#endif ++ ++ ++#if (YAFFS_USE_WRITE_BEGIN_END != 0) ++static int yaffs_write_begin(struct file *filp, struct address_space *mapping, ++ loff_t pos, unsigned len, unsigned flags, ++ struct page **pagep, void **fsdata); ++static int yaffs_write_end(struct file *filp, struct address_space *mapping, ++ loff_t pos, unsigned len, unsigned copied, ++ struct page *pg, void *fsdadata); ++#else ++static int yaffs_prepare_write(struct file *f, struct page *pg, ++ unsigned offset, unsigned to); ++static int yaffs_commit_write(struct file *f, struct page *pg, unsigned offset, ++ unsigned to); ++ ++#endif ++ ++static int yaffs_readlink(struct dentry *dentry, char __user * buffer, ++ int buflen); ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13)) ++static void *yaffs_follow_link(struct dentry *dentry, struct nameidata *nd); ++#else ++static int yaffs_follow_link(struct dentry *dentry, struct nameidata *nd); ++#endif ++ ++static struct address_space_operations yaffs_file_address_operations = { ++ .readpage = yaffs_readpage, ++ .writepage = yaffs_writepage, ++#if (YAFFS_USE_WRITE_BEGIN_END > 0) ++ .write_begin = yaffs_write_begin, ++ .write_end = yaffs_write_end, ++#else ++ .prepare_write = yaffs_prepare_write, ++ .commit_write = yaffs_commit_write, ++#endif ++}; ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22)) ++static struct file_operations yaffs_file_operations = { ++ .read = do_sync_read, ++ .write = do_sync_write, ++ .aio_read = generic_file_aio_read, ++ .aio_write = generic_file_aio_write, ++ .mmap = generic_file_mmap, ++ .flush = yaffs_file_flush, ++ .fsync = yaffs_sync_object, ++ .splice_read = generic_file_splice_read, ++ .splice_write = generic_file_splice_write, ++ .llseek = generic_file_llseek, ++}; ++ ++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)) ++ ++static struct file_operations yaffs_file_operations = { ++ .read = do_sync_read, ++ .write = do_sync_write, ++ .aio_read = generic_file_aio_read, ++ .aio_write = generic_file_aio_write, ++ .mmap = generic_file_mmap, ++ .flush = yaffs_file_flush, ++ .fsync = yaffs_sync_object, ++ .sendfile = generic_file_sendfile, ++}; ++ ++#else ++ ++static struct file_operations yaffs_file_operations = { ++ .read = generic_file_read, ++ .write = generic_file_write, ++ .mmap = generic_file_mmap, ++ .flush = yaffs_file_flush, ++ .fsync = yaffs_sync_object, ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++ .sendfile = generic_file_sendfile, ++#endif ++}; ++#endif ++ ++static struct inode_operations yaffs_file_inode_operations = { ++ .setattr = yaffs_setattr, ++}; ++ ++static struct inode_operations yaffs_symlink_inode_operations = { ++ .readlink = yaffs_readlink, ++ .follow_link = yaffs_follow_link, ++ .setattr = yaffs_setattr, ++}; ++ ++static struct inode_operations yaffs_dir_inode_operations = { ++ .create = yaffs_create, ++ .lookup = yaffs_lookup, ++ .link = yaffs_link, ++ .unlink = yaffs_unlink, ++ .symlink = yaffs_symlink, ++ .mkdir = yaffs_mkdir, ++ .rmdir = yaffs_unlink, ++ .mknod = yaffs_mknod, ++ .rename = yaffs_rename, ++ .setattr = yaffs_setattr, ++}; ++ ++static struct file_operations yaffs_dir_operations = { ++ .read = generic_read_dir, ++ .readdir = yaffs_readdir, ++ .fsync = yaffs_sync_object, ++}; ++ ++static struct super_operations yaffs_super_ops = { ++ .statfs = yaffs_statfs, ++ ++#ifndef YAFFS_USE_OWN_IGET ++ .read_inode = yaffs_read_inode, ++#endif ++#ifdef YAFFS_HAS_PUT_INODE ++ .put_inode = yaffs_put_inode, ++#endif ++ .put_super = yaffs_put_super, ++ .delete_inode = yaffs_delete_inode, ++ .clear_inode = yaffs_clear_inode, ++ .sync_fs = yaffs_sync_fs, ++ .write_super = yaffs_write_super, ++}; ++ ++static void yaffs_GrossLock(yaffs_Device * dev) ++{ ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs locking\n")); ++ ++ down(&dev->grossLock); ++} ++ ++static void yaffs_GrossUnlock(yaffs_Device * dev) ++{ ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs unlocking\n")); ++ up(&dev->grossLock); ++ ++} ++ ++static int yaffs_readlink(struct dentry *dentry, char __user * buffer, ++ int buflen) ++{ ++ unsigned char *alias; ++ int ret; ++ ++ yaffs_Device *dev = yaffs_DentryToObject(dentry)->myDev; ++ ++ yaffs_GrossLock(dev); ++ ++ alias = yaffs_GetSymlinkAlias(yaffs_DentryToObject(dentry)); ++ ++ yaffs_GrossUnlock(dev); ++ ++ if (!alias) ++ return -ENOMEM; ++ ++ ret = vfs_readlink(dentry, buffer, buflen, alias); ++ kfree(alias); ++ return ret; ++} ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13)) ++static void *yaffs_follow_link(struct dentry *dentry, struct nameidata *nd) ++#else ++static int yaffs_follow_link(struct dentry *dentry, struct nameidata *nd) ++#endif ++{ ++ unsigned char *alias; ++ int ret; ++ yaffs_Device *dev = yaffs_DentryToObject(dentry)->myDev; ++ ++ yaffs_GrossLock(dev); ++ ++ alias = yaffs_GetSymlinkAlias(yaffs_DentryToObject(dentry)); ++ ++ yaffs_GrossUnlock(dev); ++ ++ if (!alias) ++ { ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ ret = vfs_follow_link(nd, alias); ++ kfree(alias); ++out: ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13)) ++ return ERR_PTR (ret); ++#else ++ return ret; ++#endif ++} ++ ++struct inode *yaffs_get_inode(struct super_block *sb, int mode, int dev, ++ yaffs_Object * obj); ++ ++/* ++ * Lookup is used to find objects in the fs ++ */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++ ++static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry, ++ struct nameidata *n) ++#else ++static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry) ++#endif ++{ ++ yaffs_Object *obj; ++ struct inode *inode = NULL; /* NCB 2.5/2.6 needs NULL here */ ++ ++ yaffs_Device *dev = yaffs_InodeToObject(dir)->myDev; ++ ++ yaffs_GrossLock(dev); ++ ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_lookup for %d:%s\n", ++ yaffs_InodeToObject(dir)->objectId, dentry->d_name.name)); ++ ++ obj = ++ yaffs_FindObjectByName(yaffs_InodeToObject(dir), ++ dentry->d_name.name); ++ ++ obj = yaffs_GetEquivalentObject(obj); /* in case it was a hardlink */ ++ ++ /* Can't hold gross lock when calling yaffs_get_inode() */ ++ yaffs_GrossUnlock(dev); ++ ++ if (obj) { ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_lookup found %d\n", obj->objectId)); ++ ++ inode = yaffs_get_inode(dir->i_sb, obj->yst_mode, 0, obj); ++ ++ if (inode) { ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_loookup dentry \n")); ++/* #if 0 asserted by NCB for 2.5/6 compatability - falls through to ++ * d_add even if NULL inode */ ++#if 0 ++ /*dget(dentry); // try to solve directory bug */ ++ d_add(dentry, inode); ++ ++ /* return dentry; */ ++ return NULL; ++#endif ++ } ++ ++ } else { ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_lookup not found\n")); ++ ++ } ++ ++/* added NCB for 2.5/6 compatability - forces add even if inode is ++ * NULL which creates dentry hash */ ++ d_add(dentry, inode); ++ ++ return NULL; ++ /* return (ERR_PTR(-EIO)); */ ++ ++} ++ ++ ++#ifdef YAFFS_HAS_PUT_INODE ++ ++/* For now put inode is just for debugging ++ * Put inode is called when the inode **structure** is put. ++ */ ++static void yaffs_put_inode(struct inode *inode) ++{ ++ T(YAFFS_TRACE_OS, ++ ("yaffs_put_inode: ino %d, count %d\n", (int)inode->i_ino, ++ atomic_read(&inode->i_count))); ++ ++} ++#endif ++ ++/* clear is called to tell the fs to release any per-inode data it holds */ ++static void yaffs_clear_inode(struct inode *inode) ++{ ++ yaffs_Object *obj; ++ yaffs_Device *dev; ++ ++ obj = yaffs_InodeToObject(inode); ++ ++ T(YAFFS_TRACE_OS, ++ ("yaffs_clear_inode: ino %d, count %d %s\n", (int)inode->i_ino, ++ atomic_read(&inode->i_count), ++ obj ? "object exists" : "null object")); ++ ++ if (obj) { ++ dev = obj->myDev; ++ yaffs_GrossLock(dev); ++ ++ /* Clear the association between the inode and ++ * the yaffs_Object. ++ */ ++ obj->myInode = NULL; ++ yaffs_InodeToObjectLV(inode) = NULL; ++ ++ /* If the object freeing was deferred, then the real ++ * free happens now. ++ * This should fix the inode inconsistency problem. ++ */ ++ ++ yaffs_HandleDeferedFree(obj); ++ ++ yaffs_GrossUnlock(dev); ++ } ++ ++} ++ ++/* delete is called when the link count is zero and the inode ++ * is put (ie. nobody wants to know about it anymore, time to ++ * delete the file). ++ * NB Must call clear_inode() ++ */ ++static void yaffs_delete_inode(struct inode *inode) ++{ ++ yaffs_Object *obj = yaffs_InodeToObject(inode); ++ yaffs_Device *dev; ++ ++ T(YAFFS_TRACE_OS, ++ ("yaffs_delete_inode: ino %d, count %d %s\n", (int)inode->i_ino, ++ atomic_read(&inode->i_count), ++ obj ? "object exists" : "null object")); ++ ++ if (obj) { ++ dev = obj->myDev; ++ yaffs_GrossLock(dev); ++ yaffs_DeleteFile(obj); ++ yaffs_GrossUnlock(dev); ++ } ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13)) ++ truncate_inode_pages (&inode->i_data, 0); ++#endif ++ clear_inode(inode); ++} ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17)) ++static int yaffs_file_flush(struct file *file, fl_owner_t id) ++#else ++static int yaffs_file_flush(struct file *file) ++#endif ++{ ++ yaffs_Object *obj = yaffs_DentryToObject(file->f_dentry); ++ ++ yaffs_Device *dev = obj->myDev; ++ ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_file_flush object %d (%s)\n", obj->objectId, ++ obj->dirty ? "dirty" : "clean")); ++ ++ yaffs_GrossLock(dev); ++ ++ yaffs_FlushFile(obj, 1); ++ ++ yaffs_GrossUnlock(dev); ++ ++ return 0; ++} ++ ++static int yaffs_readpage_nolock(struct file *f, struct page *pg) ++{ ++ /* Lifted from jffs2 */ ++ ++ yaffs_Object *obj; ++ unsigned char *pg_buf; ++ int ret; ++ ++ yaffs_Device *dev; ++ ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_readpage at %08x, size %08x\n", ++ (unsigned)(pg->index << PAGE_CACHE_SHIFT), ++ (unsigned)PAGE_CACHE_SIZE)); ++ ++ obj = yaffs_DentryToObject(f->f_dentry); ++ ++ dev = obj->myDev; ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++ BUG_ON(!PageLocked(pg)); ++#else ++ if (!PageLocked(pg)) ++ PAGE_BUG(pg); ++#endif ++ ++ pg_buf = kmap(pg); ++ /* FIXME: Can kmap fail? */ ++ ++ yaffs_GrossLock(dev); ++ ++ ret = ++ yaffs_ReadDataFromFile(obj, pg_buf, pg->index << PAGE_CACHE_SHIFT, ++ PAGE_CACHE_SIZE); ++ ++ yaffs_GrossUnlock(dev); ++ ++ if (ret >= 0) ++ ret = 0; ++ ++ if (ret) { ++ ClearPageUptodate(pg); ++ SetPageError(pg); ++ } else { ++ SetPageUptodate(pg); ++ ClearPageError(pg); ++ } ++ ++ flush_dcache_page(pg); ++ kunmap(pg); ++ ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_readpage done\n")); ++ return ret; ++} ++ ++static int yaffs_readpage_unlock(struct file *f, struct page *pg) ++{ ++ int ret = yaffs_readpage_nolock(f, pg); ++ UnlockPage(pg); ++ return ret; ++} ++ ++static int yaffs_readpage(struct file *f, struct page *pg) ++{ ++ return yaffs_readpage_unlock(f, pg); ++} ++ ++/* writepage inspired by/stolen from smbfs */ ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++static int yaffs_writepage(struct page *page, struct writeback_control *wbc) ++#else ++static int yaffs_writepage(struct page *page) ++#endif ++{ ++ struct address_space *mapping = page->mapping; ++ loff_t offset = (loff_t) page->index << PAGE_CACHE_SHIFT; ++ struct inode *inode; ++ unsigned long end_index; ++ char *buffer; ++ yaffs_Object *obj; ++ int nWritten = 0; ++ unsigned nBytes; ++ ++ if (!mapping) ++ BUG(); ++ inode = mapping->host; ++ if (!inode) ++ BUG(); ++ ++ if (offset > inode->i_size) { ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG ++ "yaffs_writepage at %08x, inode size = %08x!!!\n", ++ (unsigned)(page->index << PAGE_CACHE_SHIFT), ++ (unsigned)inode->i_size)); ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG " -> don't care!!\n")); ++ unlock_page(page); ++ return 0; ++ } ++ ++ end_index = inode->i_size >> PAGE_CACHE_SHIFT; ++ ++ /* easy case */ ++ if (page->index < end_index) { ++ nBytes = PAGE_CACHE_SIZE; ++ } else { ++ nBytes = inode->i_size & (PAGE_CACHE_SIZE - 1); ++ } ++ ++ get_page(page); ++ ++ buffer = kmap(page); ++ ++ obj = yaffs_InodeToObject(inode); ++ yaffs_GrossLock(obj->myDev); ++ ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_writepage at %08x, size %08x\n", ++ (unsigned)(page->index << PAGE_CACHE_SHIFT), nBytes)); ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "writepag0: obj = %05x, ino = %05x\n", ++ (int)obj->variant.fileVariant.fileSize, (int)inode->i_size)); ++ ++ nWritten = ++ yaffs_WriteDataToFile(obj, buffer, page->index << PAGE_CACHE_SHIFT, ++ nBytes, 0); ++ ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "writepag1: obj = %05x, ino = %05x\n", ++ (int)obj->variant.fileVariant.fileSize, (int)inode->i_size)); ++ ++ yaffs_GrossUnlock(obj->myDev); ++ ++ kunmap(page); ++ SetPageUptodate(page); ++ UnlockPage(page); ++ put_page(page); ++ ++ return (nWritten == nBytes) ? 0 : -ENOSPC; ++} ++ ++ ++#if (YAFFS_USE_WRITE_BEGIN_END > 0) ++static int yaffs_write_begin(struct file *filp, struct address_space *mapping, ++ loff_t pos, unsigned len, unsigned flags, ++ struct page **pagep, void **fsdata) ++ ++{ ++ struct page *pg = NULL; ++ pgoff_t index = pos >> PAGE_CACHE_SHIFT; ++ uint32_t offset = pos & (PAGE_CACHE_SIZE - 1); ++ uint32_t to = offset + len; ++ ++ int ret = 0; ++ int space_held = 0; ++ ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "start yaffs_write_begin\n")); ++ /* Get a page */ ++ pg = grab_cache_page(mapping,index); ++ *pagep = pg; ++ if(!pg){ ++ ret = -ENOMEM; ++ goto out; ++ } ++ /* Get fs space */ ++ space_held = yaffs_hold_space(filp); ++ ++ if(!space_held){ ++ ret = -ENOSPC; ++ goto out; ++ } ++ ++ /* Update page if required */ ++ ++ if (!Page_Uptodate(pg) && (offset || to < PAGE_CACHE_SIZE)) ++ ret = yaffs_readpage_nolock(filp, pg); ++ ++ if(ret) ++ goto out; ++ ++ /* Happy path return */ ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "end yaffs_write_begin - ok\n")); ++ ++ return 0; ++ ++out: ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "end yaffs_write_begin fail returning %d\n",ret)); ++ if(space_held){ ++ yaffs_release_space(filp); ++ } ++ if(pg) { ++ unlock_page(pg); ++ page_cache_release(pg); ++ } ++ return ret; ++} ++ ++#else ++ ++static int yaffs_prepare_write(struct file *f, struct page *pg, ++ unsigned offset, unsigned to) ++{ ++ ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_prepair_write\n")); ++ if (!Page_Uptodate(pg) && (offset || to < PAGE_CACHE_SIZE)) ++ return yaffs_readpage_nolock(f, pg); ++ return 0; ++ ++} ++#endif ++ ++#if (YAFFS_USE_WRITE_BEGIN_END > 0) ++static int yaffs_write_end(struct file *filp, struct address_space *mapping, ++ loff_t pos, unsigned len, unsigned copied, ++ struct page *pg, void *fsdadata) ++{ ++ int ret = 0; ++ void *addr, *kva; ++ uint32_t offset_into_page = pos & (PAGE_CACHE_SIZE -1); ++ ++ ++ ++ kva=kmap(pg); ++ addr = kva + offset_into_page; ++ ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_write_end addr %x pos %x nBytes %d\n", (unsigned) addr, ++ (int)pos, copied)); ++ ++ ret = yaffs_file_write(filp, addr, copied, &pos); ++ ++ if (ret != copied) { ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG ++ "yaffs_write_end not same size ret %d copied %d\n", ++ ret, copied )); ++ SetPageError(pg); ++ ClearPageUptodate(pg); ++ } else { ++ SetPageUptodate(pg); ++ } ++ ++ kunmap(pg); ++ ++ yaffs_release_space(filp); ++ unlock_page(pg); ++ page_cache_release(pg); ++ return ret; ++} ++#else ++ ++static int yaffs_commit_write(struct file *f, struct page *pg, unsigned offset, ++ unsigned to) ++{ ++ ++ void *addr, *kva; ++ ++ loff_t pos = (((loff_t) pg->index) << PAGE_CACHE_SHIFT) + offset; ++ int nBytes = to - offset; ++ int nWritten; ++ ++ unsigned spos = pos; ++ unsigned saddr; ++ ++ kva=kmap(pg); ++ addr = kva + offset; ++ ++ saddr = (unsigned) addr; ++ ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_commit_write addr %x pos %x nBytes %d\n", saddr, ++ spos, nBytes)); ++ ++ nWritten = yaffs_file_write(f, addr, nBytes, &pos); ++ ++ if (nWritten != nBytes) { ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG ++ "yaffs_commit_write not same size nWritten %d nBytes %d\n", ++ nWritten, nBytes)); ++ SetPageError(pg); ++ ClearPageUptodate(pg); ++ } else { ++ SetPageUptodate(pg); ++ } ++ ++ kunmap(pg); ++ ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_commit_write returning %d\n", ++ nWritten == nBytes ? 0 : nWritten)); ++ ++ return nWritten == nBytes ? 0 : nWritten; ++ ++} ++#endif ++ ++ ++static void yaffs_FillInodeFromObject(struct inode *inode, yaffs_Object * obj) ++{ ++ if (inode && obj) { ++ ++ ++ /* Check mode against the variant type and attempt to repair if broken. */ ++ __u32 mode = obj->yst_mode; ++ switch( obj->variantType ){ ++ case YAFFS_OBJECT_TYPE_FILE : ++ if( ! S_ISREG(mode) ){ ++ obj->yst_mode &= ~S_IFMT; ++ obj->yst_mode |= S_IFREG; ++ } ++ ++ break; ++ case YAFFS_OBJECT_TYPE_SYMLINK : ++ if( ! S_ISLNK(mode) ){ ++ obj->yst_mode &= ~S_IFMT; ++ obj->yst_mode |= S_IFLNK; ++ } ++ ++ break; ++ case YAFFS_OBJECT_TYPE_DIRECTORY : ++ if( ! S_ISDIR(mode) ){ ++ obj->yst_mode &= ~S_IFMT; ++ obj->yst_mode |= S_IFDIR; ++ } ++ ++ break; ++ case YAFFS_OBJECT_TYPE_UNKNOWN : ++ case YAFFS_OBJECT_TYPE_HARDLINK : ++ case YAFFS_OBJECT_TYPE_SPECIAL : ++ default: ++ /* TODO? */ ++ break; ++ } ++ ++ inode->i_flags |= S_NOATIME; ++ ++ inode->i_ino = obj->objectId; ++ inode->i_mode = obj->yst_mode; ++ inode->i_uid = obj->yst_uid; ++ inode->i_gid = obj->yst_gid; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)) ++ inode->i_blksize = inode->i_sb->s_blocksize; ++#endif ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++ ++ inode->i_rdev = old_decode_dev(obj->yst_rdev); ++ inode->i_atime.tv_sec = (time_t) (obj->yst_atime); ++ inode->i_atime.tv_nsec = 0; ++ inode->i_mtime.tv_sec = (time_t) obj->yst_mtime; ++ inode->i_mtime.tv_nsec = 0; ++ inode->i_ctime.tv_sec = (time_t) obj->yst_ctime; ++ inode->i_ctime.tv_nsec = 0; ++#else ++ inode->i_rdev = obj->yst_rdev; ++ inode->i_atime = obj->yst_atime; ++ inode->i_mtime = obj->yst_mtime; ++ inode->i_ctime = obj->yst_ctime; ++#endif ++ inode->i_size = yaffs_GetObjectFileLength(obj); ++ inode->i_blocks = (inode->i_size + 511) >> 9; ++ ++ inode->i_nlink = yaffs_GetObjectLinkCount(obj); ++ ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG ++ "yaffs_FillInode mode %x uid %d gid %d size %d count %d\n", ++ inode->i_mode, inode->i_uid, inode->i_gid, ++ (int)inode->i_size, atomic_read(&inode->i_count))); ++ ++ switch (obj->yst_mode & S_IFMT) { ++ default: /* fifo, device or socket */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++ init_special_inode(inode, obj->yst_mode, ++ old_decode_dev(obj->yst_rdev)); ++#else ++ init_special_inode(inode, obj->yst_mode, ++ (dev_t) (obj->yst_rdev)); ++#endif ++ break; ++ case S_IFREG: /* file */ ++ inode->i_op = &yaffs_file_inode_operations; ++ inode->i_fop = &yaffs_file_operations; ++ inode->i_mapping->a_ops = ++ &yaffs_file_address_operations; ++ break; ++ case S_IFDIR: /* directory */ ++ inode->i_op = &yaffs_dir_inode_operations; ++ inode->i_fop = &yaffs_dir_operations; ++ break; ++ case S_IFLNK: /* symlink */ ++ inode->i_op = &yaffs_symlink_inode_operations; ++ break; ++ } ++ ++ yaffs_InodeToObjectLV(inode) = obj; ++ ++ obj->myInode = inode; ++ ++ } else { ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_FileInode invalid parameters\n")); ++ } ++ ++} ++ ++struct inode *yaffs_get_inode(struct super_block *sb, int mode, int dev, ++ yaffs_Object * obj) ++{ ++ struct inode *inode; ++ ++ if (!sb) { ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_get_inode for NULL super_block!!\n")); ++ return NULL; ++ ++ } ++ ++ if (!obj) { ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_get_inode for NULL object!!\n")); ++ return NULL; ++ ++ } ++ ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_get_inode for object %d\n", obj->objectId)); ++ ++ inode = Y_IGET(sb, obj->objectId); ++ if(IS_ERR(inode)) ++ return NULL; ++ ++ /* NB Side effect: iget calls back to yaffs_read_inode(). */ ++ /* iget also increments the inode's i_count */ ++ /* NB You can't be holding grossLock or deadlock will happen! */ ++ ++ return inode; ++} ++ ++static ssize_t yaffs_file_write(struct file *f, const char *buf, size_t n, ++ loff_t * pos) ++{ ++ yaffs_Object *obj; ++ int nWritten, ipos; ++ struct inode *inode; ++ yaffs_Device *dev; ++ ++ obj = yaffs_DentryToObject(f->f_dentry); ++ ++ dev = obj->myDev; ++ ++ yaffs_GrossLock(dev); ++ ++ inode = f->f_dentry->d_inode; ++ ++ if (!S_ISBLK(inode->i_mode) && f->f_flags & O_APPEND) { ++ ipos = inode->i_size; ++ } else { ++ ipos = *pos; ++ } ++ ++ if (!obj) { ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_file_write: hey obj is null!\n")); ++ } else { ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG ++ "yaffs_file_write about to write writing %zu bytes" ++ "to object %d at %d\n", ++ n, obj->objectId, ipos)); ++ } ++ ++ nWritten = yaffs_WriteDataToFile(obj, buf, ipos, n, 0); ++ ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_file_write writing %zu bytes, %d written at %d\n", ++ n, nWritten, ipos)); ++ if (nWritten > 0) { ++ ipos += nWritten; ++ *pos = ipos; ++ if (ipos > inode->i_size) { ++ inode->i_size = ipos; ++ inode->i_blocks = (ipos + 511) >> 9; ++ ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG ++ "yaffs_file_write size updated to %d bytes, " ++ "%d blocks\n", ++ ipos, (int)(inode->i_blocks))); ++ } ++ ++ } ++ yaffs_GrossUnlock(dev); ++ return nWritten == 0 ? -ENOSPC : nWritten; ++} ++ ++/* Space holding and freeing is done to ensure we have space available for write_begin/end */ ++/* For now we just assume few parallel writes and check against a small number. */ ++/* Todo: need to do this with a counter to handle parallel reads better */ ++ ++static ssize_t yaffs_hold_space(struct file *f) ++{ ++ yaffs_Object *obj; ++ yaffs_Device *dev; ++ ++ int nFreeChunks; ++ ++ ++ obj = yaffs_DentryToObject(f->f_dentry); ++ ++ dev = obj->myDev; ++ ++ yaffs_GrossLock(dev); ++ ++ nFreeChunks = yaffs_GetNumberOfFreeChunks(dev); ++ ++ yaffs_GrossUnlock(dev); ++ ++ return (nFreeChunks > 20) ? 1 : 0; ++} ++ ++static void yaffs_release_space(struct file *f) ++{ ++ yaffs_Object *obj; ++ yaffs_Device *dev; ++ ++ ++ obj = yaffs_DentryToObject(f->f_dentry); ++ ++ dev = obj->myDev; ++ ++ yaffs_GrossLock(dev); ++ ++ ++ yaffs_GrossUnlock(dev); ++ ++} ++ ++static int yaffs_readdir(struct file *f, void *dirent, filldir_t filldir) ++{ ++ yaffs_Object *obj; ++ yaffs_Device *dev; ++ struct inode *inode = f->f_dentry->d_inode; ++ unsigned long offset, curoffs; ++ struct ylist_head *i; ++ yaffs_Object *l; ++ ++ char name[YAFFS_MAX_NAME_LENGTH + 1]; ++ ++ obj = yaffs_DentryToObject(f->f_dentry); ++ dev = obj->myDev; ++ ++ yaffs_GrossLock(dev); ++ ++ offset = f->f_pos; ++ ++ T(YAFFS_TRACE_OS, ("yaffs_readdir: starting at %d\n", (int)offset)); ++ ++ if (offset == 0) { ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_readdir: entry . ino %d \n", ++ (int)inode->i_ino)); ++ if (filldir(dirent, ".", 1, offset, inode->i_ino, DT_DIR) ++ < 0) { ++ goto out; ++ } ++ offset++; ++ f->f_pos++; ++ } ++ if (offset == 1) { ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_readdir: entry .. ino %d \n", ++ (int)f->f_dentry->d_parent->d_inode->i_ino)); ++ if (filldir ++ (dirent, "..", 2, offset, ++ f->f_dentry->d_parent->d_inode->i_ino, DT_DIR) < 0) { ++ goto out; ++ } ++ offset++; ++ f->f_pos++; ++ } ++ ++ curoffs = 1; ++ ++ /* If the directory has changed since the open or last call to ++ readdir, rewind to after the 2 canned entries. */ ++ ++ if (f->f_version != inode->i_version) { ++ offset = 2; ++ f->f_pos = offset; ++ f->f_version = inode->i_version; ++ } ++ ++ ylist_for_each(i, &obj->variant.directoryVariant.children) { ++ curoffs++; ++ if (curoffs >= offset) { ++ l = ylist_entry(i, yaffs_Object, siblings); ++ ++ yaffs_GetObjectName(l, name, ++ YAFFS_MAX_NAME_LENGTH + 1); ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_readdir: %s inode %d\n", name, ++ yaffs_GetObjectInode(l))); ++ ++ if (filldir(dirent, ++ name, ++ strlen(name), ++ offset, ++ yaffs_GetObjectInode(l), ++ yaffs_GetObjectType(l)) ++ < 0) { ++ goto up_and_out; ++ } ++ ++ offset++; ++ f->f_pos++; ++ } ++ } ++ ++ up_and_out: ++ out: ++ ++ yaffs_GrossUnlock(dev); ++ ++ return 0; ++} ++ ++/* ++ * File creation. Allocate an inode, and we're done.. ++ */ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode, ++ dev_t rdev) ++#else ++static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode, ++ int rdev) ++#endif ++{ ++ struct inode *inode; ++ ++ yaffs_Object *obj = NULL; ++ yaffs_Device *dev; ++ ++ yaffs_Object *parent = yaffs_InodeToObject(dir); ++ ++ int error = -ENOSPC; ++ uid_t uid = current->fsuid; ++ gid_t gid = (dir->i_mode & S_ISGID) ? dir->i_gid : current->fsgid; ++ ++ if((dir->i_mode & S_ISGID) && S_ISDIR(mode)) ++ mode |= S_ISGID; ++ ++ if (parent) { ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_mknod: parent object %d type %d\n", ++ parent->objectId, parent->variantType)); ++ } else { ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_mknod: could not get parent object\n")); ++ return -EPERM; ++ } ++ ++ T(YAFFS_TRACE_OS, ("yaffs_mknod: making oject for %s, " ++ "mode %x dev %x\n", ++ dentry->d_name.name, mode, rdev)); ++ ++ dev = parent->myDev; ++ ++ yaffs_GrossLock(dev); ++ ++ switch (mode & S_IFMT) { ++ default: ++ /* Special (socket, fifo, device...) */ ++ T(YAFFS_TRACE_OS, (KERN_DEBUG ++ "yaffs_mknod: making special\n")); ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++ obj = ++ yaffs_MknodSpecial(parent, dentry->d_name.name, mode, uid, ++ gid, old_encode_dev(rdev)); ++#else ++ obj = ++ yaffs_MknodSpecial(parent, dentry->d_name.name, mode, uid, ++ gid, rdev); ++#endif ++ break; ++ case S_IFREG: /* file */ ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_mknod: making file\n")); ++ obj = ++ yaffs_MknodFile(parent, dentry->d_name.name, mode, uid, ++ gid); ++ break; ++ case S_IFDIR: /* directory */ ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_mknod: making directory\n")); ++ obj = ++ yaffs_MknodDirectory(parent, dentry->d_name.name, mode, ++ uid, gid); ++ break; ++ case S_IFLNK: /* symlink */ ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_mknod: making file\n")); ++ obj = NULL; /* Do we ever get here? */ ++ break; ++ } ++ ++ /* Can not call yaffs_get_inode() with gross lock held */ ++ yaffs_GrossUnlock(dev); ++ ++ if (obj) { ++ inode = yaffs_get_inode(dir->i_sb, mode, rdev, obj); ++ d_instantiate(dentry, inode); ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_mknod created object %d count = %d\n", ++ obj->objectId, atomic_read(&inode->i_count))); ++ error = 0; ++ } else { ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_mknod failed making object\n")); ++ error = -ENOMEM; ++ } ++ ++ return error; ++} ++ ++static int yaffs_mkdir(struct inode *dir, struct dentry *dentry, int mode) ++{ ++ int retVal; ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_mkdir\n")); ++ retVal = yaffs_mknod(dir, dentry, mode | S_IFDIR, 0); ++#if 0 ++ /* attempt to fix dir bug - didn't work */ ++ if (!retVal) { ++ dget(dentry); ++ } ++#endif ++ return retVal; ++} ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode, ++ struct nameidata *n) ++#else ++static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode) ++#endif ++{ ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_create\n")); ++ return yaffs_mknod(dir, dentry, mode | S_IFREG, 0); ++} ++ ++static int yaffs_unlink(struct inode *dir, struct dentry *dentry) ++{ ++ int retVal; ++ ++ yaffs_Device *dev; ++ ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_unlink %d:%s\n", (int)(dir->i_ino), ++ dentry->d_name.name)); ++ ++ dev = yaffs_InodeToObject(dir)->myDev; ++ ++ yaffs_GrossLock(dev); ++ ++ retVal = yaffs_Unlink(yaffs_InodeToObject(dir), dentry->d_name.name); ++ ++ if (retVal == YAFFS_OK) { ++ dentry->d_inode->i_nlink--; ++ dir->i_version++; ++ yaffs_GrossUnlock(dev); ++ mark_inode_dirty(dentry->d_inode); ++ return 0; ++ } ++ yaffs_GrossUnlock(dev); ++ return -ENOTEMPTY; ++} ++ ++/* ++ * Create a link... ++ */ ++static int yaffs_link(struct dentry *old_dentry, struct inode *dir, ++ struct dentry *dentry) ++{ ++ struct inode *inode = old_dentry->d_inode; ++ yaffs_Object *obj = NULL; ++ yaffs_Object *link = NULL; ++ yaffs_Device *dev; ++ ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_link\n")); ++ ++ obj = yaffs_InodeToObject(inode); ++ dev = obj->myDev; ++ ++ yaffs_GrossLock(dev); ++ ++ if (!S_ISDIR(inode->i_mode)) /* Don't link directories */ ++ { ++ link = ++ yaffs_Link(yaffs_InodeToObject(dir), dentry->d_name.name, ++ obj); ++ } ++ ++ if (link) { ++ old_dentry->d_inode->i_nlink = yaffs_GetObjectLinkCount(obj); ++ d_instantiate(dentry, old_dentry->d_inode); ++ atomic_inc(&old_dentry->d_inode->i_count); ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_link link count %d i_count %d\n", ++ old_dentry->d_inode->i_nlink, ++ atomic_read(&old_dentry->d_inode->i_count))); ++ ++ } ++ ++ yaffs_GrossUnlock(dev); ++ ++ if (link) { ++ ++ return 0; ++ } ++ ++ return -EPERM; ++} ++ ++static int yaffs_symlink(struct inode *dir, struct dentry *dentry, ++ const char *symname) ++{ ++ yaffs_Object *obj; ++ yaffs_Device *dev; ++ uid_t uid = current->fsuid; ++ gid_t gid = (dir->i_mode & S_ISGID) ? dir->i_gid : current->fsgid; ++ ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_symlink\n")); ++ ++ dev = yaffs_InodeToObject(dir)->myDev; ++ yaffs_GrossLock(dev); ++ obj = yaffs_MknodSymLink(yaffs_InodeToObject(dir), dentry->d_name.name, ++ S_IFLNK | S_IRWXUGO, uid, gid, symname); ++ yaffs_GrossUnlock(dev); ++ ++ if (obj) { ++ ++ struct inode *inode; ++ ++ inode = yaffs_get_inode(dir->i_sb, obj->yst_mode, 0, obj); ++ d_instantiate(dentry, inode); ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "symlink created OK\n")); ++ return 0; ++ } else { ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "symlink not created\n")); ++ ++ } ++ ++ return -ENOMEM; ++} ++ ++static int yaffs_sync_object(struct file *file, struct dentry *dentry, ++ int datasync) ++{ ++ ++ yaffs_Object *obj; ++ yaffs_Device *dev; ++ ++ obj = yaffs_DentryToObject(dentry); ++ ++ dev = obj->myDev; ++ ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_sync_object\n")); ++ yaffs_GrossLock(dev); ++ yaffs_FlushFile(obj, 1); ++ yaffs_GrossUnlock(dev); ++ return 0; ++} ++ ++/* ++ * The VFS layer already does all the dentry stuff for rename. ++ * ++ * NB: POSIX says you can rename an object over an old object of the same name ++ */ ++static int yaffs_rename(struct inode *old_dir, struct dentry *old_dentry, ++ struct inode *new_dir, struct dentry *new_dentry) ++{ ++ yaffs_Device *dev; ++ int retVal = YAFFS_FAIL; ++ yaffs_Object *target; ++ ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_rename\n")); ++ dev = yaffs_InodeToObject(old_dir)->myDev; ++ ++ yaffs_GrossLock(dev); ++ ++ /* Check if the target is an existing directory that is not empty. */ ++ target = ++ yaffs_FindObjectByName(yaffs_InodeToObject(new_dir), ++ new_dentry->d_name.name); ++ ++ ++ ++ if (target && ++ target->variantType == YAFFS_OBJECT_TYPE_DIRECTORY && ++ !ylist_empty(&target->variant.directoryVariant.children)) { ++ ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "target is non-empty dir\n")); ++ ++ retVal = YAFFS_FAIL; ++ } else { ++ ++ /* Now does unlinking internally using shadowing mechanism */ ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "calling yaffs_RenameObject\n")); ++ ++ retVal = ++ yaffs_RenameObject(yaffs_InodeToObject(old_dir), ++ old_dentry->d_name.name, ++ yaffs_InodeToObject(new_dir), ++ new_dentry->d_name.name); ++ ++ } ++ yaffs_GrossUnlock(dev); ++ ++ if (retVal == YAFFS_OK) { ++ if(target) { ++ new_dentry->d_inode->i_nlink--; ++ mark_inode_dirty(new_dentry->d_inode); ++ } ++ ++ return 0; ++ } else { ++ return -ENOTEMPTY; ++ } ++ ++} ++ ++static int yaffs_setattr(struct dentry *dentry, struct iattr *attr) ++{ ++ struct inode *inode = dentry->d_inode; ++ int error; ++ yaffs_Device *dev; ++ ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_setattr of object %d\n", ++ yaffs_InodeToObject(inode)->objectId)); ++ ++ if ((error = inode_change_ok(inode, attr)) == 0) { ++ ++ dev = yaffs_InodeToObject(inode)->myDev; ++ yaffs_GrossLock(dev); ++ if (yaffs_SetAttributes(yaffs_InodeToObject(inode), attr) == ++ YAFFS_OK) { ++ error = 0; ++ } else { ++ error = -EPERM; ++ } ++ yaffs_GrossUnlock(dev); ++ if (!error) ++ error = inode_setattr(inode, attr); ++ } ++ return error; ++} ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17)) ++static int yaffs_statfs(struct dentry *dentry, struct kstatfs *buf) ++{ ++ yaffs_Device *dev = yaffs_DentryToObject(dentry)->myDev; ++ struct super_block *sb = dentry->d_sb; ++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++static int yaffs_statfs(struct super_block *sb, struct kstatfs *buf) ++{ ++ yaffs_Device *dev = yaffs_SuperToDevice(sb); ++#else ++static int yaffs_statfs(struct super_block *sb, struct statfs *buf) ++{ ++ yaffs_Device *dev = yaffs_SuperToDevice(sb); ++#endif ++ ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_statfs\n")); ++ ++ yaffs_GrossLock(dev); ++ ++ buf->f_type = YAFFS_MAGIC; ++ buf->f_bsize = sb->s_blocksize; ++ buf->f_namelen = 255; ++ ++ if(dev->nDataBytesPerChunk & (dev->nDataBytesPerChunk - 1)){ ++ /* Do this if chunk size is not a power of 2 */ ++ ++ uint64_t bytesInDev; ++ uint64_t bytesFree; ++ ++ bytesInDev = ((uint64_t)((dev->endBlock - dev->startBlock +1))) * ++ ((uint64_t)(dev->nChunksPerBlock * dev->nDataBytesPerChunk)); ++ ++ do_div(bytesInDev,sb->s_blocksize); /* bytesInDev becomes the number of blocks */ ++ buf->f_blocks = bytesInDev; ++ ++ bytesFree = ((uint64_t)(yaffs_GetNumberOfFreeChunks(dev))) * ++ ((uint64_t)(dev->nDataBytesPerChunk)); ++ ++ do_div(bytesFree,sb->s_blocksize); ++ ++ buf->f_bfree = bytesFree; ++ ++ } else if (sb->s_blocksize > dev->nDataBytesPerChunk) { ++ ++ buf->f_blocks = ++ (dev->endBlock - dev->startBlock + 1) * ++ dev->nChunksPerBlock / ++ (sb->s_blocksize / dev->nDataBytesPerChunk); ++ buf->f_bfree = ++ yaffs_GetNumberOfFreeChunks(dev) / ++ (sb->s_blocksize / dev->nDataBytesPerChunk); ++ } else { ++ buf->f_blocks = ++ (dev->endBlock - dev->startBlock + 1) * ++ dev->nChunksPerBlock * ++ (dev->nDataBytesPerChunk / sb->s_blocksize); ++ ++ buf->f_bfree = ++ yaffs_GetNumberOfFreeChunks(dev) * ++ (dev->nDataBytesPerChunk / sb->s_blocksize); ++ } ++ ++ ++ buf->f_files = 0; ++ buf->f_ffree = 0; ++ buf->f_bavail = buf->f_bfree; ++ ++ yaffs_GrossUnlock(dev); ++ return 0; ++} ++ ++ ++static int yaffs_do_sync_fs(struct super_block *sb) ++{ ++ ++ yaffs_Device *dev = yaffs_SuperToDevice(sb); ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_do_sync_fs\n")); ++ ++ if(sb->s_dirt) { ++ yaffs_GrossLock(dev); ++ ++ if(dev){ ++ yaffs_FlushEntireDeviceCache(dev); ++ yaffs_CheckpointSave(dev); ++ } ++ ++ yaffs_GrossUnlock(dev); ++ ++ sb->s_dirt = 0; ++ } ++ return 0; ++} ++ ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17)) ++static void yaffs_write_super(struct super_block *sb) ++#else ++static int yaffs_write_super(struct super_block *sb) ++#endif ++{ ++ ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_write_super\n")); ++ if (yaffs_auto_checkpoint >= 2) ++ yaffs_do_sync_fs(sb); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) ++ return 0; ++#endif ++} ++ ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17)) ++static int yaffs_sync_fs(struct super_block *sb, int wait) ++#else ++static int yaffs_sync_fs(struct super_block *sb) ++#endif ++{ ++ ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_sync_fs\n")); ++ ++ if (yaffs_auto_checkpoint >= 1) ++ yaffs_do_sync_fs(sb); ++ ++ return 0; ++ ++} ++ ++#ifdef YAFFS_USE_OWN_IGET ++ ++static struct inode * yaffs_iget(struct super_block *sb, unsigned long ino) ++{ ++ struct inode *inode; ++ yaffs_Object *obj; ++ yaffs_Device *dev = yaffs_SuperToDevice(sb); ++ ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_iget for %lu\n", ino)); ++ ++ inode = iget_locked(sb, ino); ++ if (!inode) ++ return ERR_PTR(-ENOMEM); ++ if (!(inode->i_state & I_NEW)) ++ return inode; ++ ++ /* NB This is called as a side effect of other functions, but ++ * we had to release the lock to prevent deadlocks, so ++ * need to lock again. ++ */ ++ ++ yaffs_GrossLock(dev); ++ ++ obj = yaffs_FindObjectByNumber(dev, inode->i_ino); ++ ++ yaffs_FillInodeFromObject(inode, obj); ++ ++ yaffs_GrossUnlock(dev); ++ ++ unlock_new_inode(inode); ++ return inode; ++} ++ ++#else ++ ++static void yaffs_read_inode(struct inode *inode) ++{ ++ /* NB This is called as a side effect of other functions, but ++ * we had to release the lock to prevent deadlocks, so ++ * need to lock again. ++ */ ++ ++ yaffs_Object *obj; ++ yaffs_Device *dev = yaffs_SuperToDevice(inode->i_sb); ++ ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_read_inode for %d\n", (int)inode->i_ino)); ++ ++ yaffs_GrossLock(dev); ++ ++ obj = yaffs_FindObjectByNumber(dev, inode->i_ino); ++ ++ yaffs_FillInodeFromObject(inode, obj); ++ ++ yaffs_GrossUnlock(dev); ++} ++ ++#endif ++ ++static YLIST_HEAD(yaffs_dev_list); ++ ++#if 0 // not used ++static int yaffs_remount_fs(struct super_block *sb, int *flags, char *data) ++{ ++ yaffs_Device *dev = yaffs_SuperToDevice(sb); ++ ++ if( *flags & MS_RDONLY ) { ++ struct mtd_info *mtd = yaffs_SuperToDevice(sb)->genericDevice; ++ ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_remount_fs: %s: RO\n", dev->name )); ++ ++ yaffs_GrossLock(dev); ++ ++ yaffs_FlushEntireDeviceCache(dev); ++ ++ yaffs_CheckpointSave(dev); ++ ++ if (mtd->sync) ++ mtd->sync(mtd); ++ ++ yaffs_GrossUnlock(dev); ++ } ++ else { ++ T(YAFFS_TRACE_OS, ++ (KERN_DEBUG "yaffs_remount_fs: %s: RW\n", dev->name )); ++ } ++ ++ return 0; ++} ++#endif ++ ++static void yaffs_put_super(struct super_block *sb) ++{ ++ yaffs_Device *dev = yaffs_SuperToDevice(sb); ++ ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_put_super\n")); ++ ++ yaffs_GrossLock(dev); ++ ++ yaffs_FlushEntireDeviceCache(dev); ++ ++ yaffs_CheckpointSave(dev); ++ ++ if (dev->putSuperFunc) { ++ dev->putSuperFunc(sb); ++ } ++ ++ yaffs_Deinitialise(dev); ++ ++ yaffs_GrossUnlock(dev); ++ ++ /* we assume this is protected by lock_kernel() in mount/umount */ ++ ylist_del(&dev->devList); ++ ++ if(dev->spareBuffer){ ++ YFREE(dev->spareBuffer); ++ dev->spareBuffer = NULL; ++ } ++ ++ kfree(dev); ++} ++ ++ ++static void yaffs_MTDPutSuper(struct super_block *sb) ++{ ++ ++ struct mtd_info *mtd = yaffs_SuperToDevice(sb)->genericDevice; ++ ++ if (mtd->sync) { ++ mtd->sync(mtd); ++ } ++ ++ put_mtd_device(mtd); ++} ++ ++ ++static void yaffs_MarkSuperBlockDirty(void *vsb) ++{ ++ struct super_block *sb = (struct super_block *)vsb; ++ ++ T(YAFFS_TRACE_OS, (KERN_DEBUG "yaffs_MarkSuperBlockDirty() sb = %p\n",sb)); ++ if(sb) ++ sb->s_dirt = 1; ++} ++ ++typedef struct { ++ int inband_tags; ++ int skip_checkpoint_read; ++ int skip_checkpoint_write; ++ int no_cache; ++} yaffs_options; ++ ++#define MAX_OPT_LEN 20 ++static int yaffs_parse_options(yaffs_options *options, const char *options_str) ++{ ++ char cur_opt[MAX_OPT_LEN+1]; ++ int p; ++ int error = 0; ++ ++ /* Parse through the options which is a comma seperated list */ ++ ++ while(options_str && *options_str && !error){ ++ memset(cur_opt,0,MAX_OPT_LEN+1); ++ p = 0; ++ ++ while(*options_str && *options_str != ','){ ++ if(p < MAX_OPT_LEN){ ++ cur_opt[p] = *options_str; ++ p++; ++ } ++ options_str++; ++ } ++ ++ if(!strcmp(cur_opt,"inband-tags")) ++ options->inband_tags = 1; ++ else if(!strcmp(cur_opt,"no-cache")) ++ options->no_cache = 1; ++ else if(!strcmp(cur_opt,"no-checkpoint-read")) ++ options->skip_checkpoint_read = 1; ++ else if(!strcmp(cur_opt,"no-checkpoint-write")) ++ options->skip_checkpoint_write = 1; ++ else if(!strcmp(cur_opt,"no-checkpoint")){ ++ options->skip_checkpoint_read = 1; ++ options->skip_checkpoint_write = 1; ++ } else { ++ printk(KERN_INFO "yaffs: Bad mount option \"%s\"\n",cur_opt); ++ error = 1; ++ } ++ ++ } ++ ++ return error; ++} ++ ++static struct super_block *yaffs_internal_read_super(int yaffsVersion, ++ struct super_block *sb, ++ void *data, int silent) ++{ ++ int nBlocks; ++ struct inode *inode = NULL; ++ struct dentry *root; ++ yaffs_Device *dev = 0; ++ char devname_buf[BDEVNAME_SIZE + 1]; ++ struct mtd_info *mtd; ++ int err; ++ char *data_str = (char *)data; ++ ++ yaffs_options options; ++ ++ sb->s_magic = YAFFS_MAGIC; ++ sb->s_op = &yaffs_super_ops; ++ sb->s_flags |= MS_NOATIME; ++ ++ if (!sb) ++ printk(KERN_INFO "yaffs: sb is NULL\n"); ++ else if (!sb->s_dev) ++ printk(KERN_INFO "yaffs: sb->s_dev is NULL\n"); ++ else if (!yaffs_devname(sb, devname_buf)) ++ printk(KERN_INFO "yaffs: devname is NULL\n"); ++ else ++ printk(KERN_INFO "yaffs: dev is %d name is \"%s\"\n", ++ sb->s_dev, ++ yaffs_devname(sb, devname_buf)); ++ ++ if(!data_str) ++ data_str = ""; ++ ++ printk(KERN_INFO "yaffs: passed flags \"%s\"\n",data_str); ++ ++ memset(&options,0,sizeof(options)); ++ ++ if(yaffs_parse_options(&options,data_str)){ ++ /* Option parsing failed */ ++ return NULL; ++ } ++ ++ ++ sb->s_blocksize = PAGE_CACHE_SIZE; ++ sb->s_blocksize_bits = PAGE_CACHE_SHIFT; ++ T(YAFFS_TRACE_OS, ("yaffs_read_super: Using yaffs%d\n", yaffsVersion)); ++ T(YAFFS_TRACE_OS, ++ ("yaffs_read_super: block size %d\n", (int)(sb->s_blocksize))); ++ ++#ifdef CONFIG_YAFFS_DISABLE_WRITE_VERIFY ++ T(YAFFS_TRACE_OS, ++ ("yaffs: Write verification disabled. All guarantees " ++ "null and void\n")); ++#endif ++ ++ T(YAFFS_TRACE_ALWAYS, ("yaffs: Attempting MTD mount on %u.%u, " ++ "\"%s\"\n", ++ MAJOR(sb->s_dev), MINOR(sb->s_dev), ++ yaffs_devname(sb, devname_buf))); ++ ++ /* Check it's an mtd device..... */ ++ if (MAJOR(sb->s_dev) != MTD_BLOCK_MAJOR) { ++ return NULL; /* This isn't an mtd device */ ++ } ++ /* Get the device */ ++ mtd = get_mtd_device(NULL, MINOR(sb->s_dev)); ++ if (!mtd) { ++ T(YAFFS_TRACE_ALWAYS, ++ ("yaffs: MTD device #%u doesn't appear to exist\n", ++ MINOR(sb->s_dev))); ++ return NULL; ++ } ++ /* Check it's NAND */ ++ if (mtd->type != MTD_NANDFLASH) { ++ T(YAFFS_TRACE_ALWAYS, ++ ("yaffs: MTD device is not NAND it's type %d\n", mtd->type)); ++ return NULL; ++ } ++ ++ T(YAFFS_TRACE_OS, (" erase %p\n", mtd->erase)); ++ T(YAFFS_TRACE_OS, (" read %p\n", mtd->read)); ++ T(YAFFS_TRACE_OS, (" write %p\n", mtd->write)); ++ T(YAFFS_TRACE_OS, (" readoob %p\n", mtd->read_oob)); ++ T(YAFFS_TRACE_OS, (" writeoob %p\n", mtd->write_oob)); ++ T(YAFFS_TRACE_OS, (" block_isbad %p\n", mtd->block_isbad)); ++ T(YAFFS_TRACE_OS, (" block_markbad %p\n", mtd->block_markbad)); ++ T(YAFFS_TRACE_OS, (" %s %d\n", WRITE_SIZE_STR, WRITE_SIZE(mtd))); ++ T(YAFFS_TRACE_OS, (" oobsize %d\n", mtd->oobsize)); ++ T(YAFFS_TRACE_OS, (" erasesize %d\n", mtd->erasesize)); ++ T(YAFFS_TRACE_OS, (" size %d\n", mtd->size)); ++ ++#ifdef CONFIG_YAFFS_AUTO_YAFFS2 ++ ++ if (yaffsVersion == 1 && ++ WRITE_SIZE(mtd) >= 2048) { ++ T(YAFFS_TRACE_ALWAYS,("yaffs: auto selecting yaffs2\n")); ++ yaffsVersion = 2; ++ } ++ ++ /* Added NCB 26/5/2006 for completeness */ ++ if (yaffsVersion == 2 && ++ !options.inband_tags && ++ WRITE_SIZE(mtd) == 512){ ++ T(YAFFS_TRACE_ALWAYS,("yaffs: auto selecting yaffs1\n")); ++ yaffsVersion = 1; ++ } ++ ++#endif ++ ++ if (yaffsVersion == 2) { ++ /* Check for version 2 style functions */ ++ if (!mtd->erase || ++ !mtd->block_isbad || ++ !mtd->block_markbad || ++ !mtd->read || ++ !mtd->write || ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17)) ++ !mtd->read_oob || !mtd->write_oob) { ++#else ++ !mtd->write_ecc || ++ !mtd->read_ecc || !mtd->read_oob || !mtd->write_oob) { ++#endif ++ T(YAFFS_TRACE_ALWAYS, ++ ("yaffs: MTD device does not support required " ++ "functions\n"));; ++ return NULL; ++ } ++ ++ if ((WRITE_SIZE(mtd) < YAFFS_MIN_YAFFS2_CHUNK_SIZE || ++ mtd->oobsize < YAFFS_MIN_YAFFS2_SPARE_SIZE) && ++ !options.inband_tags) { ++ T(YAFFS_TRACE_ALWAYS, ++ ("yaffs: MTD device does not have the " ++ "right page sizes\n")); ++ return NULL; ++ } ++ } else { ++ /* Check for V1 style functions */ ++ if (!mtd->erase || ++ !mtd->read || ++ !mtd->write || ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17)) ++ !mtd->read_oob || !mtd->write_oob) { ++#else ++ !mtd->write_ecc || ++ !mtd->read_ecc || !mtd->read_oob || !mtd->write_oob) { ++#endif ++ T(YAFFS_TRACE_ALWAYS, ++ ("yaffs: MTD device does not support required " ++ "functions\n"));; ++ return NULL; ++ } ++ ++ if (WRITE_SIZE(mtd) < YAFFS_BYTES_PER_CHUNK || ++ mtd->oobsize != YAFFS_BYTES_PER_SPARE) { ++ T(YAFFS_TRACE_ALWAYS, ++ ("yaffs: MTD device does not support have the " ++ "right page sizes\n")); ++ return NULL; ++ } ++ } ++ ++ /* OK, so if we got here, we have an MTD that's NAND and looks ++ * like it has the right capabilities ++ * Set the yaffs_Device up for mtd ++ */ ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++ sb->s_fs_info = dev = kmalloc(sizeof(yaffs_Device), GFP_KERNEL); ++#else ++ sb->u.generic_sbp = dev = kmalloc(sizeof(yaffs_Device), GFP_KERNEL); ++#endif ++ if (!dev) { ++ /* Deep shit could not allocate device structure */ ++ T(YAFFS_TRACE_ALWAYS, ++ ("yaffs_read_super: Failed trying to allocate " ++ "yaffs_Device. \n")); ++ return NULL; ++ } ++ ++ memset(dev, 0, sizeof(yaffs_Device)); ++ dev->genericDevice = mtd; ++ dev->name = mtd->name; ++ ++ /* Set up the memory size parameters.... */ ++ ++ nBlocks = mtd->size / (YAFFS_CHUNKS_PER_BLOCK * YAFFS_BYTES_PER_CHUNK); ++ dev->startBlock = 0; ++ dev->endBlock = nBlocks - 1; ++ dev->nChunksPerBlock = YAFFS_CHUNKS_PER_BLOCK; ++ dev->totalBytesPerChunk = YAFFS_BYTES_PER_CHUNK; ++ dev->nReservedBlocks = 5; ++ dev->nShortOpCaches = (options.no_cache) ? 0 : 10; ++ dev->inbandTags = options.inband_tags; ++ ++ /* ... and the functions. */ ++ if (yaffsVersion == 2) { ++ dev->writeChunkWithTagsToNAND = ++ nandmtd2_WriteChunkWithTagsToNAND; ++ dev->readChunkWithTagsFromNAND = ++ nandmtd2_ReadChunkWithTagsFromNAND; ++ dev->markNANDBlockBad = nandmtd2_MarkNANDBlockBad; ++ dev->queryNANDBlock = nandmtd2_QueryNANDBlock; ++ dev->spareBuffer = YMALLOC(mtd->oobsize); ++ dev->isYaffs2 = 1; ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17)) ++ dev->totalBytesPerChunk = mtd->writesize; ++ dev->nChunksPerBlock = mtd->erasesize / mtd->writesize; ++#else ++ dev->totalBytesPerChunk = mtd->oobblock; ++ dev->nChunksPerBlock = mtd->erasesize / mtd->oobblock; ++#endif ++ nBlocks = mtd->size / mtd->erasesize; ++ ++ dev->startBlock = 0; ++ dev->endBlock = nBlocks - 1; ++ } else { ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17)) ++ /* use the MTD interface in yaffs_mtdif1.c */ ++ dev->writeChunkWithTagsToNAND = ++ nandmtd1_WriteChunkWithTagsToNAND; ++ dev->readChunkWithTagsFromNAND = ++ nandmtd1_ReadChunkWithTagsFromNAND; ++ dev->markNANDBlockBad = nandmtd1_MarkNANDBlockBad; ++ dev->queryNANDBlock = nandmtd1_QueryNANDBlock; ++#else ++ dev->writeChunkToNAND = nandmtd_WriteChunkToNAND; ++ dev->readChunkFromNAND = nandmtd_ReadChunkFromNAND; ++#endif ++ dev->isYaffs2 = 0; ++ } ++ /* ... and common functions */ ++ dev->eraseBlockInNAND = nandmtd_EraseBlockInNAND; ++ dev->initialiseNAND = nandmtd_InitialiseNAND; ++ ++ dev->putSuperFunc = yaffs_MTDPutSuper; ++ ++ dev->superBlock = (void *)sb; ++ dev->markSuperBlockDirty = yaffs_MarkSuperBlockDirty; ++ ++ ++#ifndef CONFIG_YAFFS_DOES_ECC ++ dev->useNANDECC = 1; ++#endif ++ ++#ifdef CONFIG_YAFFS_DISABLE_WIDE_TNODES ++ dev->wideTnodesDisabled = 1; ++#endif ++ ++ dev->skipCheckpointRead = options.skip_checkpoint_read; ++ dev->skipCheckpointWrite = options.skip_checkpoint_write; ++ ++ /* we assume this is protected by lock_kernel() in mount/umount */ ++ ylist_add_tail(&dev->devList, &yaffs_dev_list); ++ ++ init_MUTEX(&dev->grossLock); ++ ++ yaffs_GrossLock(dev); ++ ++ err = yaffs_GutsInitialise(dev); ++ ++ T(YAFFS_TRACE_OS, ++ ("yaffs_read_super: guts initialised %s\n", ++ (err == YAFFS_OK) ? "OK" : "FAILED")); ++ ++ /* Release lock before yaffs_get_inode() */ ++ yaffs_GrossUnlock(dev); ++ ++ /* Create root inode */ ++ if (err == YAFFS_OK) ++ inode = yaffs_get_inode(sb, S_IFDIR | 0755, 0, ++ yaffs_Root(dev)); ++ ++ if (!inode) ++ return NULL; ++ ++ inode->i_op = &yaffs_dir_inode_operations; ++ inode->i_fop = &yaffs_dir_operations; ++ ++ T(YAFFS_TRACE_OS, ("yaffs_read_super: got root inode\n")); ++ ++ root = d_alloc_root(inode); ++ ++ T(YAFFS_TRACE_OS, ("yaffs_read_super: d_alloc_root done\n")); ++ ++ if (!root) { ++ iput(inode); ++ return NULL; ++ } ++ sb->s_root = root; ++ sb->s_dirt = !dev->isCheckpointed; ++ T(YAFFS_TRACE_ALWAYS, ++ ("yaffs_read_super: isCheckpointed %d\n", dev->isCheckpointed)); ++ ++ T(YAFFS_TRACE_OS, ("yaffs_read_super: done\n")); ++ return sb; ++} ++ ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++static int yaffs_internal_read_super_mtd(struct super_block *sb, void *data, ++ int silent) ++{ ++ return yaffs_internal_read_super(1, sb, data, silent) ? 0 : -EINVAL; ++} ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17)) ++static int yaffs_read_super(struct file_system_type *fs, ++ int flags, const char *dev_name, ++ void *data, struct vfsmount *mnt) ++{ ++ ++ return get_sb_bdev(fs, flags, dev_name, data, ++ yaffs_internal_read_super_mtd, mnt); ++} ++#else ++static struct super_block *yaffs_read_super(struct file_system_type *fs, ++ int flags, const char *dev_name, ++ void *data) ++{ ++ ++ return get_sb_bdev(fs, flags, dev_name, data, ++ yaffs_internal_read_super_mtd); ++} ++#endif ++ ++static struct file_system_type yaffs_fs_type = { ++ .owner = THIS_MODULE, ++ .name = "yaffs", ++ .get_sb = yaffs_read_super, ++ .kill_sb = kill_block_super, ++ .fs_flags = FS_REQUIRES_DEV, ++}; ++#else ++static struct super_block *yaffs_read_super(struct super_block *sb, void *data, ++ int silent) ++{ ++ return yaffs_internal_read_super(1, sb, data, silent); ++} ++ ++static DECLARE_FSTYPE(yaffs_fs_type, "yaffs", yaffs_read_super, ++ FS_REQUIRES_DEV); ++#endif ++ ++ ++#ifdef CONFIG_YAFFS_YAFFS2 ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++static int yaffs2_internal_read_super_mtd(struct super_block *sb, void *data, ++ int silent) ++{ ++ return yaffs_internal_read_super(2, sb, data, silent) ? 0 : -EINVAL; ++} ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17)) ++static int yaffs2_read_super(struct file_system_type *fs, ++ int flags, const char *dev_name, void *data, ++ struct vfsmount *mnt) ++{ ++ return get_sb_bdev(fs, flags, dev_name, data, ++ yaffs2_internal_read_super_mtd, mnt); ++} ++#else ++static struct super_block *yaffs2_read_super(struct file_system_type *fs, ++ int flags, const char *dev_name, ++ void *data) ++{ ++ ++ return get_sb_bdev(fs, flags, dev_name, data, ++ yaffs2_internal_read_super_mtd); ++} ++#endif ++ ++static struct file_system_type yaffs2_fs_type = { ++ .owner = THIS_MODULE, ++ .name = "yaffs2", ++ .get_sb = yaffs2_read_super, ++ .kill_sb = kill_block_super, ++ .fs_flags = FS_REQUIRES_DEV, ++}; ++#else ++static struct super_block *yaffs2_read_super(struct super_block *sb, ++ void *data, int silent) ++{ ++ return yaffs_internal_read_super(2, sb, data, silent); ++} ++ ++static DECLARE_FSTYPE(yaffs2_fs_type, "yaffs2", yaffs2_read_super, ++ FS_REQUIRES_DEV); ++#endif ++ ++#endif /* CONFIG_YAFFS_YAFFS2 */ ++ ++static struct proc_dir_entry *my_proc_entry; ++ ++static char *yaffs_dump_dev(char *buf, yaffs_Device * dev) ++{ ++ buf += sprintf(buf, "startBlock......... %d\n", dev->startBlock); ++ buf += sprintf(buf, "endBlock........... %d\n", dev->endBlock); ++ buf += sprintf(buf, "totalBytesPerChunk. %d\n", dev->totalBytesPerChunk); ++ buf += sprintf(buf, "nDataBytesPerChunk. %d\n", dev->nDataBytesPerChunk); ++ buf += sprintf(buf, "chunkGroupBits..... %d\n", dev->chunkGroupBits); ++ buf += sprintf(buf, "chunkGroupSize..... %d\n", dev->chunkGroupSize); ++ buf += sprintf(buf, "nErasedBlocks...... %d\n", dev->nErasedBlocks); ++ buf += sprintf(buf, "nReservedBlocks.... %d\n", dev->nReservedBlocks); ++ buf += sprintf(buf, "blocksInCheckpoint. %d\n", dev->blocksInCheckpoint); ++ buf += sprintf(buf, "nTnodesCreated..... %d\n", dev->nTnodesCreated); ++ buf += sprintf(buf, "nFreeTnodes........ %d\n", dev->nFreeTnodes); ++ buf += sprintf(buf, "nObjectsCreated.... %d\n", dev->nObjectsCreated); ++ buf += sprintf(buf, "nFreeObjects....... %d\n", dev->nFreeObjects); ++ buf += sprintf(buf, "nFreeChunks........ %d\n", dev->nFreeChunks); ++ buf += sprintf(buf, "nPageWrites........ %d\n", dev->nPageWrites); ++ buf += sprintf(buf, "nPageReads......... %d\n", dev->nPageReads); ++ buf += sprintf(buf, "nBlockErasures..... %d\n", dev->nBlockErasures); ++ buf += sprintf(buf, "nGCCopies.......... %d\n", dev->nGCCopies); ++ buf += sprintf(buf, "garbageCollections. %d\n", dev->garbageCollections); ++ buf += sprintf(buf, "passiveGCs......... %d\n", ++ dev->passiveGarbageCollections); ++ buf += sprintf(buf, "nRetriedWrites..... %d\n", dev->nRetriedWrites); ++ buf += sprintf(buf, "nShortOpCaches..... %d\n", dev->nShortOpCaches); ++ buf += sprintf(buf, "nRetireBlocks...... %d\n", dev->nRetiredBlocks); ++ buf += sprintf(buf, "eccFixed........... %d\n", dev->eccFixed); ++ buf += sprintf(buf, "eccUnfixed......... %d\n", dev->eccUnfixed); ++ buf += sprintf(buf, "tagsEccFixed....... %d\n", dev->tagsEccFixed); ++ buf += sprintf(buf, "tagsEccUnfixed..... %d\n", dev->tagsEccUnfixed); ++ buf += sprintf(buf, "cacheHits.......... %d\n", dev->cacheHits); ++ buf += sprintf(buf, "nDeletedFiles...... %d\n", dev->nDeletedFiles); ++ buf += sprintf(buf, "nUnlinkedFiles..... %d\n", dev->nUnlinkedFiles); ++ buf += ++ sprintf(buf, "nBackgroudDeletions %d\n", dev->nBackgroundDeletions); ++ buf += sprintf(buf, "useNANDECC......... %d\n", dev->useNANDECC); ++ buf += sprintf(buf, "isYaffs2........... %d\n", dev->isYaffs2); ++ buf += sprintf(buf, "inbandTags......... %d\n", dev->inbandTags); ++ ++ return buf; ++} ++ ++static int yaffs_proc_read(char *page, ++ char **start, ++ off_t offset, int count, int *eof, void *data) ++{ ++ struct ylist_head *item; ++ char *buf = page; ++ int step = offset; ++ int n = 0; ++ ++ /* Get proc_file_read() to step 'offset' by one on each sucessive call. ++ * We use 'offset' (*ppos) to indicate where we are in devList. ++ * This also assumes the user has posted a read buffer large ++ * enough to hold the complete output; but that's life in /proc. ++ */ ++ ++ *(int *)start = 1; ++ ++ /* Print header first */ ++ if (step == 0) { ++ buf += sprintf(buf, "YAFFS built:" __DATE__ " " __TIME__ ++ "\n%s\n%s\n", yaffs_fs_c_version, ++ yaffs_guts_c_version); ++ } ++ ++ /* hold lock_kernel while traversing yaffs_dev_list */ ++ lock_kernel(); ++ ++ /* Locate and print the Nth entry. Order N-squared but N is small. */ ++ ylist_for_each(item, &yaffs_dev_list) { ++ yaffs_Device *dev = ylist_entry(item, yaffs_Device, devList); ++ if (n < step) { ++ n++; ++ continue; ++ } ++ buf += sprintf(buf, "\nDevice %d \"%s\"\n", n, dev->name); ++ buf = yaffs_dump_dev(buf, dev); ++ break; ++ } ++ unlock_kernel(); ++ ++ return buf - page < count ? buf - page : count; ++} ++ ++/** ++ * Set the verbosity of the warnings and error messages. ++ * ++ * Note that the names can only be a..z or _ with the current code. ++ */ ++ ++static struct { ++ char *mask_name; ++ unsigned mask_bitfield; ++} mask_flags[] = { ++ {"allocate", YAFFS_TRACE_ALLOCATE}, ++ {"always", YAFFS_TRACE_ALWAYS}, ++ {"bad_blocks", YAFFS_TRACE_BAD_BLOCKS}, ++ {"buffers", YAFFS_TRACE_BUFFERS}, ++ {"bug", YAFFS_TRACE_BUG}, ++ {"checkpt", YAFFS_TRACE_CHECKPOINT}, ++ {"deletion", YAFFS_TRACE_DELETION}, ++ {"erase", YAFFS_TRACE_ERASE}, ++ {"error", YAFFS_TRACE_ERROR}, ++ {"gc_detail", YAFFS_TRACE_GC_DETAIL}, ++ {"gc", YAFFS_TRACE_GC}, ++ {"mtd", YAFFS_TRACE_MTD}, ++ {"nandaccess", YAFFS_TRACE_NANDACCESS}, ++ {"os", YAFFS_TRACE_OS}, ++ {"scan_debug", YAFFS_TRACE_SCAN_DEBUG}, ++ {"scan", YAFFS_TRACE_SCAN}, ++ {"tracing", YAFFS_TRACE_TRACING}, ++ ++ {"verify", YAFFS_TRACE_VERIFY}, ++ {"verify_nand", YAFFS_TRACE_VERIFY_NAND}, ++ {"verify_full", YAFFS_TRACE_VERIFY_FULL}, ++ {"verify_all", YAFFS_TRACE_VERIFY_ALL}, ++ ++ {"write", YAFFS_TRACE_WRITE}, ++ {"all", 0xffffffff}, ++ {"none", 0}, ++ {NULL, 0}, ++}; ++ ++#define MAX_MASK_NAME_LENGTH 40 ++static int yaffs_proc_write(struct file *file, const char *buf, ++ unsigned long count, void *data) ++{ ++ unsigned rg = 0, mask_bitfield; ++ char *end; ++ char *mask_name; ++ const char *x; ++ char substring[MAX_MASK_NAME_LENGTH+1]; ++ int i; ++ int done = 0; ++ int add, len = 0; ++ int pos = 0; ++ ++ rg = yaffs_traceMask; ++ ++ while (!done && (pos < count)) { ++ done = 1; ++ while ((pos < count) && isspace(buf[pos])) { ++ pos++; ++ } ++ ++ switch (buf[pos]) { ++ case '+': ++ case '-': ++ case '=': ++ add = buf[pos]; ++ pos++; ++ break; ++ ++ default: ++ add = ' '; ++ break; ++ } ++ mask_name = NULL; ++ ++ mask_bitfield = simple_strtoul(buf + pos, &end, 0); ++ if (end > buf + pos) { ++ mask_name = "numeral"; ++ len = end - (buf + pos); ++ pos += len; ++ done = 0; ++ } else { ++ for(x = buf + pos, i = 0; ++ (*x == '_' || (*x >='a' && *x <= 'z')) && ++ i write_proc = yaffs_proc_write; ++ my_proc_entry->read_proc = yaffs_proc_read; ++ my_proc_entry->data = NULL; ++ } else { ++ return -ENOMEM; ++ } ++ ++ /* Now add the file system entries */ ++ ++ fsinst = fs_to_install; ++ ++ while (fsinst->fst && !error) { ++ error = register_filesystem(fsinst->fst); ++ if (!error) { ++ fsinst->installed = 1; ++ } ++ fsinst++; ++ } ++ ++ /* Any errors? uninstall */ ++ if (error) { ++ fsinst = fs_to_install; ++ ++ while (fsinst->fst) { ++ if (fsinst->installed) { ++ unregister_filesystem(fsinst->fst); ++ fsinst->installed = 0; ++ } ++ fsinst++; ++ } ++ } ++ ++ return error; ++} ++ ++static void __exit exit_yaffs_fs(void) ++{ ++ ++ struct file_system_to_install *fsinst; ++ ++ T(YAFFS_TRACE_ALWAYS, ("yaffs " __DATE__ " " __TIME__ ++ " removing. \n")); ++ ++ remove_proc_entry("yaffs", YPROC_ROOT); ++ ++ fsinst = fs_to_install; ++ ++ while (fsinst->fst) { ++ if (fsinst->installed) { ++ unregister_filesystem(fsinst->fst); ++ fsinst->installed = 0; ++ } ++ fsinst++; ++ } ++ ++} ++ ++module_init(init_yaffs_fs) ++module_exit(exit_yaffs_fs) ++ ++MODULE_DESCRIPTION("YAFFS2 - a NAND specific flash file system"); ++MODULE_AUTHOR("Charles Manning, Aleph One Ltd., 2002-2006"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_getblockinfo.h linux-2.6.28.6/fs/yaffs2/yaffs_getblockinfo.h +--- linux-2.6.28/fs/yaffs2/yaffs_getblockinfo.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_getblockinfo.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,34 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_GETBLOCKINFO_H__ ++#define __YAFFS_GETBLOCKINFO_H__ ++ ++#include "yaffs_guts.h" ++ ++/* Function to manipulate block info */ ++static Y_INLINE yaffs_BlockInfo *yaffs_GetBlockInfo(yaffs_Device * dev, int blk) ++{ ++ if (blk < dev->internalStartBlock || blk > dev->internalEndBlock) { ++ T(YAFFS_TRACE_ERROR, ++ (TSTR ++ ("**>> yaffs: getBlockInfo block %d is not valid" TENDSTR), ++ blk)); ++ YBUG(); ++ } ++ return &dev->blockInfo[blk - dev->internalStartBlock]; ++} ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_guts.c linux-2.6.28.6/fs/yaffs2/yaffs_guts.c +--- linux-2.6.28/fs/yaffs2/yaffs_guts.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_guts.c 2010-04-22 05:42:51.000000000 +0200 +@@ -0,0 +1,7698 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++const char *yaffs_guts_c_version = ++ "$Id: yaffs_guts.c,v 1.78 2009/01/27 02:52:45 charles Exp $"; ++ ++#include "yportenv.h" ++ ++#include "yaffsinterface.h" ++#include "yaffs_guts.h" ++#include "yaffs_tagsvalidity.h" ++#include "yaffs_getblockinfo.h" ++ ++#include "yaffs_tagscompat.h" ++#ifndef CONFIG_YAFFS_USE_OWN_SORT ++#include "yaffs_qsort.h" ++#endif ++#include "yaffs_nand.h" ++ ++#include "yaffs_checkptrw.h" ++ ++#include "yaffs_nand.h" ++#include "yaffs_packedtags2.h" ++ ++ ++#define YAFFS_PASSIVE_GC_CHUNKS 2 ++ ++#include "yaffs_ecc.h" ++ ++ ++/* Robustification (if it ever comes about...) */ ++static void yaffs_RetireBlock(yaffs_Device * dev, int blockInNAND); ++static void yaffs_HandleWriteChunkError(yaffs_Device * dev, int chunkInNAND, int erasedOk); ++static void yaffs_HandleWriteChunkOk(yaffs_Device * dev, int chunkInNAND, ++ const __u8 * data, ++ const yaffs_ExtendedTags * tags); ++static void yaffs_HandleUpdateChunk(yaffs_Device * dev, int chunkInNAND, ++ const yaffs_ExtendedTags * tags); ++ ++/* Other local prototypes */ ++static int yaffs_UnlinkObject( yaffs_Object *obj); ++static int yaffs_ObjectHasCachedWriteData(yaffs_Object *obj); ++ ++static void yaffs_HardlinkFixup(yaffs_Device *dev, yaffs_Object *hardList); ++ ++static int yaffs_WriteNewChunkWithTagsToNAND(yaffs_Device * dev, ++ const __u8 * buffer, ++ yaffs_ExtendedTags * tags, ++ int useReserve); ++static int yaffs_PutChunkIntoFile(yaffs_Object * in, int chunkInInode, ++ int chunkInNAND, int inScan); ++ ++static yaffs_Object *yaffs_CreateNewObject(yaffs_Device * dev, int number, ++ yaffs_ObjectType type); ++static void yaffs_AddObjectToDirectory(yaffs_Object * directory, ++ yaffs_Object * obj); ++static int yaffs_UpdateObjectHeader(yaffs_Object * in, const YCHAR * name, ++ int force, int isShrink, int shadows); ++static void yaffs_RemoveObjectFromDirectory(yaffs_Object * obj); ++static int yaffs_CheckStructures(void); ++static int yaffs_DeleteWorker(yaffs_Object * in, yaffs_Tnode * tn, __u32 level, ++ int chunkOffset, int *limit); ++static int yaffs_DoGenericObjectDeletion(yaffs_Object * in); ++ ++static yaffs_BlockInfo *yaffs_GetBlockInfo(yaffs_Device * dev, int blockNo); ++ ++ ++static int yaffs_CheckChunkErased(struct yaffs_DeviceStruct *dev, ++ int chunkInNAND); ++ ++static int yaffs_UnlinkWorker(yaffs_Object * obj); ++static void yaffs_DestroyObject(yaffs_Object * obj); ++ ++static int yaffs_TagsMatch(const yaffs_ExtendedTags * tags, int objectId, ++ int chunkInObject); ++ ++loff_t yaffs_GetFileSize(yaffs_Object * obj); ++ ++static int yaffs_AllocateChunk(yaffs_Device * dev, int useReserve, yaffs_BlockInfo **blockUsedPtr); ++ ++static void yaffs_VerifyFreeChunks(yaffs_Device * dev); ++ ++static void yaffs_CheckObjectDetailsLoaded(yaffs_Object *in); ++ ++static void yaffs_VerifyDirectory(yaffs_Object *directory); ++#ifdef YAFFS_PARANOID ++static int yaffs_CheckFileSanity(yaffs_Object * in); ++#else ++#define yaffs_CheckFileSanity(in) ++#endif ++ ++static void yaffs_InvalidateWholeChunkCache(yaffs_Object * in); ++static void yaffs_InvalidateChunkCache(yaffs_Object * object, int chunkId); ++ ++static void yaffs_InvalidateCheckpoint(yaffs_Device *dev); ++ ++static int yaffs_FindChunkInFile(yaffs_Object * in, int chunkInInode, ++ yaffs_ExtendedTags * tags); ++ ++static __u32 yaffs_GetChunkGroupBase(yaffs_Device *dev, yaffs_Tnode *tn, unsigned pos); ++static yaffs_Tnode *yaffs_FindLevel0Tnode(yaffs_Device * dev, ++ yaffs_FileStructure * fStruct, ++ __u32 chunkId); ++ ++ ++/* Function to calculate chunk and offset */ ++ ++static void yaffs_AddrToChunk(yaffs_Device *dev, loff_t addr, int *chunkOut, __u32 *offsetOut) ++{ ++ int chunk; ++ __u32 offset; ++ ++ chunk = (__u32)(addr >> dev->chunkShift); ++ ++ if(dev->chunkDiv == 1) ++ { ++ /* easy power of 2 case */ ++ offset = (__u32)(addr & dev->chunkMask); ++ } ++ else ++ { ++ /* Non power-of-2 case */ ++ ++ loff_t chunkBase; ++ ++ chunk /= dev->chunkDiv; ++ ++ chunkBase = ((loff_t)chunk) * dev->nDataBytesPerChunk; ++ offset = (__u32)(addr - chunkBase); ++ } ++ ++ *chunkOut = chunk; ++ *offsetOut = offset; ++} ++ ++/* Function to return the number of shifts for a power of 2 greater than or equal ++ * to the given number ++ * Note we don't try to cater for all possible numbers and this does not have to ++ * be hellishly efficient. ++ */ ++ ++static __u32 ShiftsGE(__u32 x) ++{ ++ int extraBits; ++ int nShifts; ++ ++ nShifts = extraBits = 0; ++ ++ while(x>1){ ++ if(x & 1) extraBits++; ++ x>>=1; ++ nShifts++; ++ } ++ ++ if(extraBits) ++ nShifts++; ++ ++ return nShifts; ++} ++ ++/* Function to return the number of shifts to get a 1 in bit 0 ++ */ ++ ++static __u32 Shifts(__u32 x) ++{ ++ int nShifts; ++ ++ nShifts = 0; ++ ++ if(!x) return 0; ++ ++ while( !(x&1)){ ++ x>>=1; ++ nShifts++; ++ } ++ ++ return nShifts; ++} ++ ++ ++ ++/* ++ * Temporary buffer manipulations. ++ */ ++ ++static int yaffs_InitialiseTempBuffers(yaffs_Device *dev) ++{ ++ int i; ++ __u8 *buf = (__u8 *)1; ++ ++ memset(dev->tempBuffer,0,sizeof(dev->tempBuffer)); ++ ++ for (i = 0; buf && i < YAFFS_N_TEMP_BUFFERS; i++) { ++ dev->tempBuffer[i].line = 0; /* not in use */ ++ dev->tempBuffer[i].buffer = buf = ++ YMALLOC_DMA(dev->totalBytesPerChunk); ++ } ++ ++ return buf ? YAFFS_OK : YAFFS_FAIL; ++ ++} ++ ++__u8 *yaffs_GetTempBuffer(yaffs_Device * dev, int lineNo) ++{ ++ int i, j; ++ ++ dev->tempInUse++; ++ if(dev->tempInUse > dev->maxTemp) ++ dev->maxTemp = dev->tempInUse; ++ ++ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) { ++ if (dev->tempBuffer[i].line == 0) { ++ dev->tempBuffer[i].line = lineNo; ++ if ((i + 1) > dev->maxTemp) { ++ dev->maxTemp = i + 1; ++ for (j = 0; j <= i; j++) ++ dev->tempBuffer[j].maxLine = ++ dev->tempBuffer[j].line; ++ } ++ ++ return dev->tempBuffer[i].buffer; ++ } ++ } ++ ++ T(YAFFS_TRACE_BUFFERS, ++ (TSTR("Out of temp buffers at line %d, other held by lines:"), ++ lineNo)); ++ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) { ++ T(YAFFS_TRACE_BUFFERS, (TSTR(" %d "), dev->tempBuffer[i].line)); ++ } ++ T(YAFFS_TRACE_BUFFERS, (TSTR(" " TENDSTR))); ++ ++ /* ++ * If we got here then we have to allocate an unmanaged one ++ * This is not good. ++ */ ++ ++ dev->unmanagedTempAllocations++; ++ return YMALLOC(dev->nDataBytesPerChunk); ++ ++} ++ ++void yaffs_ReleaseTempBuffer(yaffs_Device * dev, __u8 * buffer, ++ int lineNo) ++{ ++ int i; ++ ++ dev->tempInUse--; ++ ++ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) { ++ if (dev->tempBuffer[i].buffer == buffer) { ++ dev->tempBuffer[i].line = 0; ++ return; ++ } ++ } ++ ++ if (buffer) { ++ /* assume it is an unmanaged one. */ ++ T(YAFFS_TRACE_BUFFERS, ++ (TSTR("Releasing unmanaged temp buffer in line %d" TENDSTR), ++ lineNo)); ++ YFREE(buffer); ++ dev->unmanagedTempDeallocations++; ++ } ++ ++} ++ ++/* ++ * Determine if we have a managed buffer. ++ */ ++int yaffs_IsManagedTempBuffer(yaffs_Device * dev, const __u8 * buffer) ++{ ++ int i; ++ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) { ++ if (dev->tempBuffer[i].buffer == buffer) ++ return 1; ++ ++ } ++ ++ for (i = 0; i < dev->nShortOpCaches; i++) { ++ if( dev->srCache[i].data == buffer ) ++ return 1; ++ ++ } ++ ++ if (buffer == dev->checkpointBuffer) ++ return 1; ++ ++ T(YAFFS_TRACE_ALWAYS, ++ (TSTR("yaffs: unmaged buffer detected.\n" TENDSTR))); ++ return 0; ++} ++ ++ ++ ++/* ++ * Chunk bitmap manipulations ++ */ ++ ++static Y_INLINE __u8 *yaffs_BlockBits(yaffs_Device * dev, int blk) ++{ ++ if (blk < dev->internalStartBlock || blk > dev->internalEndBlock) { ++ T(YAFFS_TRACE_ERROR, ++ (TSTR("**>> yaffs: BlockBits block %d is not valid" TENDSTR), ++ blk)); ++ YBUG(); ++ } ++ return dev->chunkBits + ++ (dev->chunkBitmapStride * (blk - dev->internalStartBlock)); ++} ++ ++static Y_INLINE void yaffs_VerifyChunkBitId(yaffs_Device *dev, int blk, int chunk) ++{ ++ if(blk < dev->internalStartBlock || blk > dev->internalEndBlock || ++ chunk < 0 || chunk >= dev->nChunksPerBlock) { ++ T(YAFFS_TRACE_ERROR, ++ (TSTR("**>> yaffs: Chunk Id (%d:%d) invalid"TENDSTR),blk,chunk)); ++ YBUG(); ++ } ++} ++ ++static Y_INLINE void yaffs_ClearChunkBits(yaffs_Device * dev, int blk) ++{ ++ __u8 *blkBits = yaffs_BlockBits(dev, blk); ++ ++ memset(blkBits, 0, dev->chunkBitmapStride); ++} ++ ++static Y_INLINE void yaffs_ClearChunkBit(yaffs_Device * dev, int blk, int chunk) ++{ ++ __u8 *blkBits = yaffs_BlockBits(dev, blk); ++ ++ yaffs_VerifyChunkBitId(dev,blk,chunk); ++ ++ blkBits[chunk / 8] &= ~(1 << (chunk & 7)); ++} ++ ++static Y_INLINE void yaffs_SetChunkBit(yaffs_Device * dev, int blk, int chunk) ++{ ++ __u8 *blkBits = yaffs_BlockBits(dev, blk); ++ ++ yaffs_VerifyChunkBitId(dev,blk,chunk); ++ ++ blkBits[chunk / 8] |= (1 << (chunk & 7)); ++} ++ ++static Y_INLINE int yaffs_CheckChunkBit(yaffs_Device * dev, int blk, int chunk) ++{ ++ __u8 *blkBits = yaffs_BlockBits(dev, blk); ++ yaffs_VerifyChunkBitId(dev,blk,chunk); ++ ++ return (blkBits[chunk / 8] & (1 << (chunk & 7))) ? 1 : 0; ++} ++ ++static Y_INLINE int yaffs_StillSomeChunkBits(yaffs_Device * dev, int blk) ++{ ++ __u8 *blkBits = yaffs_BlockBits(dev, blk); ++ int i; ++ for (i = 0; i < dev->chunkBitmapStride; i++) { ++ if (*blkBits) ++ return 1; ++ blkBits++; ++ } ++ return 0; ++} ++ ++static int yaffs_CountChunkBits(yaffs_Device * dev, int blk) ++{ ++ __u8 *blkBits = yaffs_BlockBits(dev, blk); ++ int i; ++ int n = 0; ++ for (i = 0; i < dev->chunkBitmapStride; i++) { ++ __u8 x = *blkBits; ++ while(x){ ++ if(x & 1) ++ n++; ++ x >>=1; ++ } ++ ++ blkBits++; ++ } ++ return n; ++} ++ ++/* ++ * Verification code ++ */ ++ ++static int yaffs_SkipVerification(yaffs_Device *dev) ++{ ++ return !(yaffs_traceMask & (YAFFS_TRACE_VERIFY | YAFFS_TRACE_VERIFY_FULL)); ++} ++ ++static int yaffs_SkipFullVerification(yaffs_Device *dev) ++{ ++ return !(yaffs_traceMask & (YAFFS_TRACE_VERIFY_FULL)); ++} ++ ++static int yaffs_SkipNANDVerification(yaffs_Device *dev) ++{ ++ return !(yaffs_traceMask & (YAFFS_TRACE_VERIFY_NAND)); ++} ++ ++static const char * blockStateName[] = { ++"Unknown", ++"Needs scanning", ++"Scanning", ++"Empty", ++"Allocating", ++"Full", ++"Dirty", ++"Checkpoint", ++"Collecting", ++"Dead" ++}; ++ ++static void yaffs_VerifyBlock(yaffs_Device *dev,yaffs_BlockInfo *bi,int n) ++{ ++ int actuallyUsed; ++ int inUse; ++ ++ if(yaffs_SkipVerification(dev)) ++ return; ++ ++ /* Report illegal runtime states */ ++ if(bi->blockState >= YAFFS_NUMBER_OF_BLOCK_STATES) ++ T(YAFFS_TRACE_VERIFY,(TSTR("Block %d has undefined state %d"TENDSTR),n,bi->blockState)); ++ ++ switch(bi->blockState){ ++ case YAFFS_BLOCK_STATE_UNKNOWN: ++ case YAFFS_BLOCK_STATE_SCANNING: ++ case YAFFS_BLOCK_STATE_NEEDS_SCANNING: ++ T(YAFFS_TRACE_VERIFY,(TSTR("Block %d has bad run-state %s"TENDSTR), ++ n,blockStateName[bi->blockState])); ++ } ++ ++ /* Check pages in use and soft deletions are legal */ ++ ++ actuallyUsed = bi->pagesInUse - bi->softDeletions; ++ ++ if(bi->pagesInUse < 0 || bi->pagesInUse > dev->nChunksPerBlock || ++ bi->softDeletions < 0 || bi->softDeletions > dev->nChunksPerBlock || ++ actuallyUsed < 0 || actuallyUsed > dev->nChunksPerBlock) ++ T(YAFFS_TRACE_VERIFY,(TSTR("Block %d has illegal values pagesInUsed %d softDeletions %d"TENDSTR), ++ n,bi->pagesInUse,bi->softDeletions)); ++ ++ ++ /* Check chunk bitmap legal */ ++ inUse = yaffs_CountChunkBits(dev,n); ++ if(inUse != bi->pagesInUse) ++ T(YAFFS_TRACE_VERIFY,(TSTR("Block %d has inconsistent values pagesInUse %d counted chunk bits %d"TENDSTR), ++ n,bi->pagesInUse,inUse)); ++ ++ /* Check that the sequence number is valid. ++ * Ten million is legal, but is very unlikely ++ */ ++ if(dev->isYaffs2 && ++ (bi->blockState == YAFFS_BLOCK_STATE_ALLOCATING || bi->blockState == YAFFS_BLOCK_STATE_FULL) && ++ (bi->sequenceNumber < YAFFS_LOWEST_SEQUENCE_NUMBER || bi->sequenceNumber > 10000000 )) ++ T(YAFFS_TRACE_VERIFY,(TSTR("Block %d has suspect sequence number of %d"TENDSTR), ++ n,bi->sequenceNumber)); ++ ++} ++ ++static void yaffs_VerifyCollectedBlock(yaffs_Device *dev,yaffs_BlockInfo *bi,int n) ++{ ++ yaffs_VerifyBlock(dev,bi,n); ++ ++ /* After collection the block should be in the erased state */ ++ /* This will need to change if we do partial gc */ ++ ++ if(bi->blockState != YAFFS_BLOCK_STATE_COLLECTING && ++ bi->blockState != YAFFS_BLOCK_STATE_EMPTY){ ++ T(YAFFS_TRACE_ERROR,(TSTR("Block %d is in state %d after gc, should be erased"TENDSTR), ++ n,bi->blockState)); ++ } ++} ++ ++static void yaffs_VerifyBlocks(yaffs_Device *dev) ++{ ++ int i; ++ int nBlocksPerState[YAFFS_NUMBER_OF_BLOCK_STATES]; ++ int nIllegalBlockStates = 0; ++ ++ ++ if(yaffs_SkipVerification(dev)) ++ return; ++ ++ memset(nBlocksPerState,0,sizeof(nBlocksPerState)); ++ ++ ++ for(i = dev->internalStartBlock; i <= dev->internalEndBlock; i++){ ++ yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev,i); ++ yaffs_VerifyBlock(dev,bi,i); ++ ++ if(bi->blockState < YAFFS_NUMBER_OF_BLOCK_STATES) ++ nBlocksPerState[bi->blockState]++; ++ else ++ nIllegalBlockStates++; ++ ++ } ++ ++ T(YAFFS_TRACE_VERIFY,(TSTR(""TENDSTR))); ++ T(YAFFS_TRACE_VERIFY,(TSTR("Block summary"TENDSTR))); ++ ++ T(YAFFS_TRACE_VERIFY,(TSTR("%d blocks have illegal states"TENDSTR),nIllegalBlockStates)); ++ if(nBlocksPerState[YAFFS_BLOCK_STATE_ALLOCATING] > 1) ++ T(YAFFS_TRACE_VERIFY,(TSTR("Too many allocating blocks"TENDSTR))); ++ ++ for(i = 0; i < YAFFS_NUMBER_OF_BLOCK_STATES; i++) ++ T(YAFFS_TRACE_VERIFY, ++ (TSTR("%s %d blocks"TENDSTR), ++ blockStateName[i],nBlocksPerState[i])); ++ ++ if(dev->blocksInCheckpoint != nBlocksPerState[YAFFS_BLOCK_STATE_CHECKPOINT]) ++ T(YAFFS_TRACE_VERIFY, ++ (TSTR("Checkpoint block count wrong dev %d count %d"TENDSTR), ++ dev->blocksInCheckpoint, nBlocksPerState[YAFFS_BLOCK_STATE_CHECKPOINT])); ++ ++ if(dev->nErasedBlocks != nBlocksPerState[YAFFS_BLOCK_STATE_EMPTY]) ++ T(YAFFS_TRACE_VERIFY, ++ (TSTR("Erased block count wrong dev %d count %d"TENDSTR), ++ dev->nErasedBlocks, nBlocksPerState[YAFFS_BLOCK_STATE_EMPTY])); ++ ++ if(nBlocksPerState[YAFFS_BLOCK_STATE_COLLECTING] > 1) ++ T(YAFFS_TRACE_VERIFY, ++ (TSTR("Too many collecting blocks %d (max is 1)"TENDSTR), ++ nBlocksPerState[YAFFS_BLOCK_STATE_COLLECTING])); ++ ++ T(YAFFS_TRACE_VERIFY,(TSTR(""TENDSTR))); ++ ++} ++ ++/* ++ * Verify the object header. oh must be valid, but obj and tags may be NULL in which ++ * case those tests will not be performed. ++ */ ++static void yaffs_VerifyObjectHeader(yaffs_Object *obj, yaffs_ObjectHeader *oh, yaffs_ExtendedTags *tags, int parentCheck) ++{ ++ if(obj && yaffs_SkipVerification(obj->myDev)) ++ return; ++ ++ if(!(tags && obj && oh)){ ++ T(YAFFS_TRACE_VERIFY, ++ (TSTR("Verifying object header tags %x obj %x oh %x"TENDSTR), ++ (__u32)tags,(__u32)obj,(__u32)oh)); ++ return; ++ } ++ ++ if(oh->type <= YAFFS_OBJECT_TYPE_UNKNOWN || ++ oh->type > YAFFS_OBJECT_TYPE_MAX) ++ T(YAFFS_TRACE_VERIFY, ++ (TSTR("Obj %d header type is illegal value 0x%x"TENDSTR), ++ tags->objectId, oh->type)); ++ ++ if(tags->objectId != obj->objectId) ++ T(YAFFS_TRACE_VERIFY, ++ (TSTR("Obj %d header mismatch objectId %d"TENDSTR), ++ tags->objectId, obj->objectId)); ++ ++ ++ /* ++ * Check that the object's parent ids match if parentCheck requested. ++ * ++ * Tests do not apply to the root object. ++ */ ++ ++ if(parentCheck && tags->objectId > 1 && !obj->parent) ++ T(YAFFS_TRACE_VERIFY, ++ (TSTR("Obj %d header mismatch parentId %d obj->parent is NULL"TENDSTR), ++ tags->objectId, oh->parentObjectId)); ++ ++ ++ if(parentCheck && obj->parent && ++ oh->parentObjectId != obj->parent->objectId && ++ (oh->parentObjectId != YAFFS_OBJECTID_UNLINKED || ++ obj->parent->objectId != YAFFS_OBJECTID_DELETED)) ++ T(YAFFS_TRACE_VERIFY, ++ (TSTR("Obj %d header mismatch parentId %d parentObjectId %d"TENDSTR), ++ tags->objectId, oh->parentObjectId, obj->parent->objectId)); ++ ++ ++ if(tags->objectId > 1 && oh->name[0] == 0) /* Null name */ ++ T(YAFFS_TRACE_VERIFY, ++ (TSTR("Obj %d header name is NULL"TENDSTR), ++ obj->objectId)); ++ ++ if(tags->objectId > 1 && ((__u8)(oh->name[0])) == 0xff) /* Trashed name */ ++ T(YAFFS_TRACE_VERIFY, ++ (TSTR("Obj %d header name is 0xFF"TENDSTR), ++ obj->objectId)); ++} ++ ++ ++ ++static int yaffs_VerifyTnodeWorker(yaffs_Object * obj, yaffs_Tnode * tn, ++ __u32 level, int chunkOffset) ++{ ++ int i; ++ yaffs_Device *dev = obj->myDev; ++ int ok = 1; ++ ++ if (tn) { ++ if (level > 0) { ++ ++ for (i = 0; i < YAFFS_NTNODES_INTERNAL && ok; i++){ ++ if (tn->internal[i]) { ++ ok = yaffs_VerifyTnodeWorker(obj, ++ tn->internal[i], ++ level - 1, ++ (chunkOffset<objectId; ++ ++ chunkOffset <<= YAFFS_TNODES_LEVEL0_BITS; ++ ++ for(i = 0; i < YAFFS_NTNODES_LEVEL0; i++){ ++ __u32 theChunk = yaffs_GetChunkGroupBase(dev,tn,i); ++ ++ if(theChunk > 0){ ++ /* T(~0,(TSTR("verifying (%d:%d) %d"TENDSTR),tags.objectId,tags.chunkId,theChunk)); */ ++ yaffs_ReadChunkWithTagsFromNAND(dev,theChunk,NULL, &tags); ++ if(tags.objectId != objectId || tags.chunkId != chunkOffset){ ++ T(~0,(TSTR("Object %d chunkId %d NAND mismatch chunk %d tags (%d:%d)"TENDSTR), ++ objectId, chunkOffset, theChunk, ++ tags.objectId, tags.chunkId)); ++ } ++ } ++ chunkOffset++; ++ } ++ } ++ } ++ ++ return ok; ++ ++} ++ ++ ++static void yaffs_VerifyFile(yaffs_Object *obj) ++{ ++ int requiredTallness; ++ int actualTallness; ++ __u32 lastChunk; ++ __u32 x; ++ __u32 i; ++ yaffs_Device *dev; ++ yaffs_ExtendedTags tags; ++ yaffs_Tnode *tn; ++ __u32 objectId; ++ ++ if(!obj) ++ return; ++ ++ if(yaffs_SkipVerification(obj->myDev)) ++ return; ++ ++ dev = obj->myDev; ++ objectId = obj->objectId; ++ ++ /* Check file size is consistent with tnode depth */ ++ lastChunk = obj->variant.fileVariant.fileSize / dev->nDataBytesPerChunk + 1; ++ x = lastChunk >> YAFFS_TNODES_LEVEL0_BITS; ++ requiredTallness = 0; ++ while (x> 0) { ++ x >>= YAFFS_TNODES_INTERNAL_BITS; ++ requiredTallness++; ++ } ++ ++ actualTallness = obj->variant.fileVariant.topLevel; ++ ++ if(requiredTallness > actualTallness ) ++ T(YAFFS_TRACE_VERIFY, ++ (TSTR("Obj %d had tnode tallness %d, needs to be %d"TENDSTR), ++ obj->objectId,actualTallness, requiredTallness)); ++ ++ ++ /* Check that the chunks in the tnode tree are all correct. ++ * We do this by scanning through the tnode tree and ++ * checking the tags for every chunk match. ++ */ ++ ++ if(yaffs_SkipNANDVerification(dev)) ++ return; ++ ++ for(i = 1; i <= lastChunk; i++){ ++ tn = yaffs_FindLevel0Tnode(dev, &obj->variant.fileVariant,i); ++ ++ if (tn) { ++ __u32 theChunk = yaffs_GetChunkGroupBase(dev,tn,i); ++ if(theChunk > 0){ ++ /* T(~0,(TSTR("verifying (%d:%d) %d"TENDSTR),objectId,i,theChunk)); */ ++ yaffs_ReadChunkWithTagsFromNAND(dev,theChunk,NULL, &tags); ++ if(tags.objectId != objectId || tags.chunkId != i){ ++ T(~0,(TSTR("Object %d chunkId %d NAND mismatch chunk %d tags (%d:%d)"TENDSTR), ++ objectId, i, theChunk, ++ tags.objectId, tags.chunkId)); ++ } ++ } ++ } ++ ++ } ++ ++} ++ ++ ++static void yaffs_VerifyHardLink(yaffs_Object *obj) ++{ ++ if(obj && yaffs_SkipVerification(obj->myDev)) ++ return; ++ ++ /* Verify sane equivalent object */ ++} ++ ++static void yaffs_VerifySymlink(yaffs_Object *obj) ++{ ++ if(obj && yaffs_SkipVerification(obj->myDev)) ++ return; ++ ++ /* Verify symlink string */ ++} ++ ++static void yaffs_VerifySpecial(yaffs_Object *obj) ++{ ++ if(obj && yaffs_SkipVerification(obj->myDev)) ++ return; ++} ++ ++static void yaffs_VerifyObject(yaffs_Object *obj) ++{ ++ yaffs_Device *dev; ++ ++ __u32 chunkMin; ++ __u32 chunkMax; ++ ++ __u32 chunkIdOk; ++ __u32 chunkInRange; ++ __u32 chunkShouldNotBeDeleted; ++ __u32 chunkValid; ++ ++ if(!obj) ++ return; ++ ++ if(obj->beingCreated) ++ return; ++ ++ dev = obj->myDev; ++ ++ if(yaffs_SkipVerification(dev)) ++ return; ++ ++ /* Check sane object header chunk */ ++ ++ chunkMin = dev->internalStartBlock * dev->nChunksPerBlock; ++ chunkMax = (dev->internalEndBlock+1) * dev->nChunksPerBlock - 1; ++ ++ chunkInRange = (((unsigned)(obj->hdrChunk)) >= chunkMin && ((unsigned)(obj->hdrChunk)) <= chunkMax); ++ chunkIdOk = chunkInRange || obj->hdrChunk == 0; ++ chunkValid = chunkInRange && ++ yaffs_CheckChunkBit(dev, ++ obj->hdrChunk / dev->nChunksPerBlock, ++ obj->hdrChunk % dev->nChunksPerBlock); ++ chunkShouldNotBeDeleted = chunkInRange && !chunkValid; ++ ++ if(!obj->fake && ++ (!chunkIdOk || chunkShouldNotBeDeleted)) { ++ T(YAFFS_TRACE_VERIFY, ++ (TSTR("Obj %d has chunkId %d %s %s"TENDSTR), ++ obj->objectId,obj->hdrChunk, ++ chunkIdOk ? "" : ",out of range", ++ chunkShouldNotBeDeleted ? ",marked as deleted" : "")); ++ } ++ ++ if(chunkValid &&!yaffs_SkipNANDVerification(dev)) { ++ yaffs_ExtendedTags tags; ++ yaffs_ObjectHeader *oh; ++ __u8 *buffer = yaffs_GetTempBuffer(dev,__LINE__); ++ ++ oh = (yaffs_ObjectHeader *)buffer; ++ ++ yaffs_ReadChunkWithTagsFromNAND(dev, obj->hdrChunk,buffer, &tags); ++ ++ yaffs_VerifyObjectHeader(obj,oh,&tags,1); ++ ++ yaffs_ReleaseTempBuffer(dev,buffer,__LINE__); ++ } ++ ++ /* Verify it has a parent */ ++ if(obj && !obj->fake && ++ (!obj->parent || obj->parent->myDev != dev)){ ++ T(YAFFS_TRACE_VERIFY, ++ (TSTR("Obj %d has parent pointer %p which does not look like an object"TENDSTR), ++ obj->objectId,obj->parent)); ++ } ++ ++ /* Verify parent is a directory */ ++ if(obj->parent && obj->parent->variantType != YAFFS_OBJECT_TYPE_DIRECTORY){ ++ T(YAFFS_TRACE_VERIFY, ++ (TSTR("Obj %d's parent is not a directory (type %d)"TENDSTR), ++ obj->objectId,obj->parent->variantType)); ++ } ++ ++ switch(obj->variantType){ ++ case YAFFS_OBJECT_TYPE_FILE: ++ yaffs_VerifyFile(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ yaffs_VerifySymlink(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_DIRECTORY: ++ yaffs_VerifyDirectory(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_HARDLINK: ++ yaffs_VerifyHardLink(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_SPECIAL: ++ yaffs_VerifySpecial(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_UNKNOWN: ++ default: ++ T(YAFFS_TRACE_VERIFY, ++ (TSTR("Obj %d has illegaltype %d"TENDSTR), ++ obj->objectId,obj->variantType)); ++ break; ++ } ++ ++ ++} ++ ++static void yaffs_VerifyObjects(yaffs_Device *dev) ++{ ++ yaffs_Object *obj; ++ int i; ++ struct ylist_head *lh; ++ ++ if(yaffs_SkipVerification(dev)) ++ return; ++ ++ /* Iterate through the objects in each hash entry */ ++ ++ for(i = 0; i < YAFFS_NOBJECT_BUCKETS; i++){ ++ ylist_for_each(lh, &dev->objectBucket[i].list) { ++ if (lh) { ++ obj = ylist_entry(lh, yaffs_Object, hashLink); ++ yaffs_VerifyObject(obj); ++ } ++ } ++ } ++ ++} ++ ++ ++/* ++ * Simple hash function. Needs to have a reasonable spread ++ */ ++ ++static Y_INLINE int yaffs_HashFunction(int n) ++{ ++ n = abs(n); ++ return (n % YAFFS_NOBJECT_BUCKETS); ++} ++ ++/* ++ * Access functions to useful fake objects. ++ * Note that root might have a presence in NAND if permissions are set. ++ */ ++ ++yaffs_Object *yaffs_Root(yaffs_Device * dev) ++{ ++ return dev->rootDir; ++} ++ ++yaffs_Object *yaffs_LostNFound(yaffs_Device * dev) ++{ ++ return dev->lostNFoundDir; ++} ++ ++ ++/* ++ * Erased NAND checking functions ++ */ ++ ++int yaffs_CheckFF(__u8 * buffer, int nBytes) ++{ ++ /* Horrible, slow implementation */ ++ while (nBytes--) { ++ if (*buffer != 0xFF) ++ return 0; ++ buffer++; ++ } ++ return 1; ++} ++ ++static int yaffs_CheckChunkErased(struct yaffs_DeviceStruct *dev, ++ int chunkInNAND) ++{ ++ ++ int retval = YAFFS_OK; ++ __u8 *data = yaffs_GetTempBuffer(dev, __LINE__); ++ yaffs_ExtendedTags tags; ++ int result; ++ ++ result = yaffs_ReadChunkWithTagsFromNAND(dev, chunkInNAND, data, &tags); ++ ++ if(tags.eccResult > YAFFS_ECC_RESULT_NO_ERROR) ++ retval = YAFFS_FAIL; ++ ++ ++ if (!yaffs_CheckFF(data, dev->nDataBytesPerChunk) || tags.chunkUsed) { ++ T(YAFFS_TRACE_NANDACCESS, ++ (TSTR("Chunk %d not erased" TENDSTR), chunkInNAND)); ++ retval = YAFFS_FAIL; ++ } ++ ++ yaffs_ReleaseTempBuffer(dev, data, __LINE__); ++ ++ return retval; ++ ++} ++ ++static int yaffs_WriteNewChunkWithTagsToNAND(struct yaffs_DeviceStruct *dev, ++ const __u8 * data, ++ yaffs_ExtendedTags * tags, ++ int useReserve) ++{ ++ int attempts = 0; ++ int writeOk = 0; ++ int chunk; ++ ++ yaffs_InvalidateCheckpoint(dev); ++ ++ do { ++ yaffs_BlockInfo *bi = 0; ++ int erasedOk = 0; ++ ++ chunk = yaffs_AllocateChunk(dev, useReserve, &bi); ++ if (chunk < 0) { ++ /* no space */ ++ break; ++ } ++ ++ /* First check this chunk is erased, if it needs ++ * checking. The checking policy (unless forced ++ * always on) is as follows: ++ * ++ * Check the first page we try to write in a block. ++ * If the check passes then we don't need to check any ++ * more. If the check fails, we check again... ++ * If the block has been erased, we don't need to check. ++ * ++ * However, if the block has been prioritised for gc, ++ * then we think there might be something odd about ++ * this block and stop using it. ++ * ++ * Rationale: We should only ever see chunks that have ++ * not been erased if there was a partially written ++ * chunk due to power loss. This checking policy should ++ * catch that case with very few checks and thus save a ++ * lot of checks that are most likely not needed. ++ */ ++ if (bi->gcPrioritise) { ++ yaffs_DeleteChunk(dev, chunk, 1, __LINE__); ++ /* try another chunk */ ++ continue; ++ } ++ ++ /* let's give it a try */ ++ attempts++; ++ ++#ifdef CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED ++ bi->skipErasedCheck = 0; ++#endif ++ if (!bi->skipErasedCheck) { ++ erasedOk = yaffs_CheckChunkErased(dev, chunk); ++ if (erasedOk != YAFFS_OK) { ++ T(YAFFS_TRACE_ERROR, ++ (TSTR ("**>> yaffs chunk %d was not erased" ++ TENDSTR), chunk)); ++ ++ /* try another chunk */ ++ continue; ++ } ++ bi->skipErasedCheck = 1; ++ } ++ ++ writeOk = yaffs_WriteChunkWithTagsToNAND(dev, chunk, ++ data, tags); ++ if (writeOk != YAFFS_OK) { ++ yaffs_HandleWriteChunkError(dev, chunk, erasedOk); ++ /* try another chunk */ ++ continue; ++ } ++ ++ /* Copy the data into the robustification buffer */ ++ yaffs_HandleWriteChunkOk(dev, chunk, data, tags); ++ ++ } while (writeOk != YAFFS_OK && ++ (yaffs_wr_attempts <= 0 || attempts <= yaffs_wr_attempts)); ++ ++ if(!writeOk) ++ chunk = -1; ++ ++ if (attempts > 1) { ++ T(YAFFS_TRACE_ERROR, ++ (TSTR("**>> yaffs write required %d attempts" TENDSTR), ++ attempts)); ++ ++ dev->nRetriedWrites += (attempts - 1); ++ } ++ ++ return chunk; ++} ++ ++/* ++ * Block retiring for handling a broken block. ++ */ ++ ++static void yaffs_RetireBlock(yaffs_Device * dev, int blockInNAND) ++{ ++ yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, blockInNAND); ++ ++ yaffs_InvalidateCheckpoint(dev); ++ ++ if (yaffs_MarkBlockBad(dev, blockInNAND) != YAFFS_OK) { ++ if (yaffs_EraseBlockInNAND(dev, blockInNAND) != YAFFS_OK) { ++ T(YAFFS_TRACE_ALWAYS, (TSTR( ++ "yaffs: Failed to mark bad and erase block %d" ++ TENDSTR), blockInNAND)); ++ } ++ else { ++ yaffs_ExtendedTags tags; ++ int chunkId = blockInNAND * dev->nChunksPerBlock; ++ ++ __u8 *buffer = yaffs_GetTempBuffer(dev, __LINE__); ++ ++ memset(buffer, 0xff, dev->nDataBytesPerChunk); ++ yaffs_InitialiseTags(&tags); ++ tags.sequenceNumber = YAFFS_SEQUENCE_BAD_BLOCK; ++ if (dev->writeChunkWithTagsToNAND(dev, chunkId - ++ dev->chunkOffset, buffer, &tags) != YAFFS_OK) ++ T(YAFFS_TRACE_ALWAYS, (TSTR("yaffs: Failed to " ++ TCONT("write bad block marker to block %d") ++ TENDSTR), blockInNAND)); ++ ++ yaffs_ReleaseTempBuffer(dev, buffer, __LINE__); ++ } ++ } ++ ++ bi->blockState = YAFFS_BLOCK_STATE_DEAD; ++ bi->gcPrioritise = 0; ++ bi->needsRetiring = 0; ++ ++ dev->nRetiredBlocks++; ++} ++ ++/* ++ * Functions for robustisizing TODO ++ * ++ */ ++ ++static void yaffs_HandleWriteChunkOk(yaffs_Device * dev, int chunkInNAND, ++ const __u8 * data, ++ const yaffs_ExtendedTags * tags) ++{ ++} ++ ++static void yaffs_HandleUpdateChunk(yaffs_Device * dev, int chunkInNAND, ++ const yaffs_ExtendedTags * tags) ++{ ++} ++ ++void yaffs_HandleChunkError(yaffs_Device *dev, yaffs_BlockInfo *bi) ++{ ++ if(!bi->gcPrioritise){ ++ bi->gcPrioritise = 1; ++ dev->hasPendingPrioritisedGCs = 1; ++ bi->chunkErrorStrikes ++; ++ ++ if(bi->chunkErrorStrikes > 3){ ++ bi->needsRetiring = 1; /* Too many stikes, so retire this */ ++ T(YAFFS_TRACE_ALWAYS, (TSTR("yaffs: Block struck out" TENDSTR))); ++ ++ } ++ ++ } ++} ++ ++static void yaffs_HandleWriteChunkError(yaffs_Device * dev, int chunkInNAND, int erasedOk) ++{ ++ ++ int blockInNAND = chunkInNAND / dev->nChunksPerBlock; ++ yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, blockInNAND); ++ ++ yaffs_HandleChunkError(dev,bi); ++ ++ ++ if(erasedOk ) { ++ /* Was an actual write failure, so mark the block for retirement */ ++ bi->needsRetiring = 1; ++ T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS, ++ (TSTR("**>> Block %d needs retiring" TENDSTR), blockInNAND)); ++ ++ ++ } ++ ++ /* Delete the chunk */ ++ yaffs_DeleteChunk(dev, chunkInNAND, 1, __LINE__); ++} ++ ++ ++/*---------------- Name handling functions ------------*/ ++ ++static __u16 yaffs_CalcNameSum(const YCHAR * name) ++{ ++ __u16 sum = 0; ++ __u16 i = 1; ++ ++ const YUCHAR *bname = (const YUCHAR *) name; ++ if (bname) { ++ while ((*bname) && (i < (YAFFS_MAX_NAME_LENGTH/2))) { ++ ++#ifdef CONFIG_YAFFS_CASE_INSENSITIVE ++ sum += yaffs_toupper(*bname) * i; ++#else ++ sum += (*bname) * i; ++#endif ++ i++; ++ bname++; ++ } ++ } ++ return sum; ++} ++ ++static void yaffs_SetObjectName(yaffs_Object * obj, const YCHAR * name) ++{ ++#ifdef CONFIG_YAFFS_SHORT_NAMES_IN_RAM ++ memset(obj->shortName,0,sizeof (YCHAR) * (YAFFS_SHORT_NAME_LENGTH+1)); ++ if (name && yaffs_strlen(name) <= YAFFS_SHORT_NAME_LENGTH) { ++ yaffs_strcpy(obj->shortName, name); ++ } else { ++ obj->shortName[0] = _Y('\0'); ++ } ++#endif ++ obj->sum = yaffs_CalcNameSum(name); ++} ++ ++/*-------------------- TNODES ------------------- ++ ++ * List of spare tnodes ++ * The list is hooked together using the first pointer ++ * in the tnode. ++ */ ++ ++/* yaffs_CreateTnodes creates a bunch more tnodes and ++ * adds them to the tnode free list. ++ * Don't use this function directly ++ */ ++ ++static int yaffs_CreateTnodes(yaffs_Device * dev, int nTnodes) ++{ ++ int i; ++ int tnodeSize; ++ yaffs_Tnode *newTnodes; ++ __u8 *mem; ++ yaffs_Tnode *curr; ++ yaffs_Tnode *next; ++ yaffs_TnodeList *tnl; ++ ++ if (nTnodes < 1) ++ return YAFFS_OK; ++ ++ /* Calculate the tnode size in bytes for variable width tnode support. ++ * Must be a multiple of 32-bits */ ++ tnodeSize = (dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8; ++ ++ if(tnodeSize < sizeof(yaffs_Tnode)) ++ tnodeSize = sizeof(yaffs_Tnode); ++ ++ ++ /* make these things */ ++ ++ newTnodes = YMALLOC(nTnodes * tnodeSize); ++ mem = (__u8 *)newTnodes; ++ ++ if (!newTnodes) { ++ T(YAFFS_TRACE_ERROR, ++ (TSTR("yaffs: Could not allocate Tnodes" TENDSTR))); ++ return YAFFS_FAIL; ++ } ++ ++ /* Hook them into the free list */ ++#if 0 ++ for (i = 0; i < nTnodes - 1; i++) { ++ newTnodes[i].internal[0] = &newTnodes[i + 1]; ++#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG ++ newTnodes[i].internal[YAFFS_NTNODES_INTERNAL] = (void *)1; ++#endif ++ } ++ ++ newTnodes[nTnodes - 1].internal[0] = dev->freeTnodes; ++#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG ++ newTnodes[nTnodes - 1].internal[YAFFS_NTNODES_INTERNAL] = (void *)1; ++#endif ++ dev->freeTnodes = newTnodes; ++#else ++ /* New hookup for wide tnodes */ ++ for(i = 0; i < nTnodes -1; i++) { ++ curr = (yaffs_Tnode *) &mem[i * tnodeSize]; ++ next = (yaffs_Tnode *) &mem[(i+1) * tnodeSize]; ++ curr->internal[0] = next; ++ } ++ ++ curr = (yaffs_Tnode *) &mem[(nTnodes - 1) * tnodeSize]; ++ curr->internal[0] = dev->freeTnodes; ++ dev->freeTnodes = (yaffs_Tnode *)mem; ++ ++#endif ++ ++ ++ dev->nFreeTnodes += nTnodes; ++ dev->nTnodesCreated += nTnodes; ++ ++ /* Now add this bunch of tnodes to a list for freeing up. ++ * NB If we can't add this to the management list it isn't fatal ++ * but it just means we can't free this bunch of tnodes later. ++ */ ++ ++ tnl = YMALLOC(sizeof(yaffs_TnodeList)); ++ if (!tnl) { ++ T(YAFFS_TRACE_ERROR, ++ (TSTR ++ ("yaffs: Could not add tnodes to management list" TENDSTR))); ++ return YAFFS_FAIL; ++ ++ } else { ++ tnl->tnodes = newTnodes; ++ tnl->next = dev->allocatedTnodeList; ++ dev->allocatedTnodeList = tnl; ++ } ++ ++ T(YAFFS_TRACE_ALLOCATE, (TSTR("yaffs: Tnodes added" TENDSTR))); ++ ++ return YAFFS_OK; ++} ++ ++/* GetTnode gets us a clean tnode. Tries to make allocate more if we run out */ ++ ++static yaffs_Tnode *yaffs_GetTnodeRaw(yaffs_Device * dev) ++{ ++ yaffs_Tnode *tn = NULL; ++ ++ /* If there are none left make more */ ++ if (!dev->freeTnodes) { ++ yaffs_CreateTnodes(dev, YAFFS_ALLOCATION_NTNODES); ++ } ++ ++ if (dev->freeTnodes) { ++ tn = dev->freeTnodes; ++#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG ++ if (tn->internal[YAFFS_NTNODES_INTERNAL] != (void *)1) { ++ /* Hoosterman, this thing looks like it isn't in the list */ ++ T(YAFFS_TRACE_ALWAYS, ++ (TSTR("yaffs: Tnode list bug 1" TENDSTR))); ++ } ++#endif ++ dev->freeTnodes = dev->freeTnodes->internal[0]; ++ dev->nFreeTnodes--; ++ } ++ ++ dev->nCheckpointBlocksRequired = 0; /* force recalculation*/ ++ ++ return tn; ++} ++ ++static yaffs_Tnode *yaffs_GetTnode(yaffs_Device * dev) ++{ ++ yaffs_Tnode *tn = yaffs_GetTnodeRaw(dev); ++ int tnodeSize = (dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8; ++ ++ if(tnodeSize < sizeof(yaffs_Tnode)) ++ tnodeSize = sizeof(yaffs_Tnode); ++ ++ if(tn) ++ memset(tn, 0, tnodeSize); ++ ++ return tn; ++} ++ ++/* FreeTnode frees up a tnode and puts it back on the free list */ ++static void yaffs_FreeTnode(yaffs_Device * dev, yaffs_Tnode * tn) ++{ ++ if (tn) { ++#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG ++ if (tn->internal[YAFFS_NTNODES_INTERNAL] != 0) { ++ /* Hoosterman, this thing looks like it is already in the list */ ++ T(YAFFS_TRACE_ALWAYS, ++ (TSTR("yaffs: Tnode list bug 2" TENDSTR))); ++ } ++ tn->internal[YAFFS_NTNODES_INTERNAL] = (void *)1; ++#endif ++ tn->internal[0] = dev->freeTnodes; ++ dev->freeTnodes = tn; ++ dev->nFreeTnodes++; ++ } ++ dev->nCheckpointBlocksRequired = 0; /* force recalculation*/ ++ ++} ++ ++static void yaffs_DeinitialiseTnodes(yaffs_Device * dev) ++{ ++ /* Free the list of allocated tnodes */ ++ yaffs_TnodeList *tmp; ++ ++ while (dev->allocatedTnodeList) { ++ tmp = dev->allocatedTnodeList->next; ++ ++ YFREE(dev->allocatedTnodeList->tnodes); ++ YFREE(dev->allocatedTnodeList); ++ dev->allocatedTnodeList = tmp; ++ ++ } ++ ++ dev->freeTnodes = NULL; ++ dev->nFreeTnodes = 0; ++} ++ ++static void yaffs_InitialiseTnodes(yaffs_Device * dev) ++{ ++ dev->allocatedTnodeList = NULL; ++ dev->freeTnodes = NULL; ++ dev->nFreeTnodes = 0; ++ dev->nTnodesCreated = 0; ++ ++} ++ ++ ++void yaffs_PutLevel0Tnode(yaffs_Device *dev, yaffs_Tnode *tn, unsigned pos, unsigned val) ++{ ++ __u32 *map = (__u32 *)tn; ++ __u32 bitInMap; ++ __u32 bitInWord; ++ __u32 wordInMap; ++ __u32 mask; ++ ++ pos &= YAFFS_TNODES_LEVEL0_MASK; ++ val >>= dev->chunkGroupBits; ++ ++ bitInMap = pos * dev->tnodeWidth; ++ wordInMap = bitInMap /32; ++ bitInWord = bitInMap & (32 -1); ++ ++ mask = dev->tnodeMask << bitInWord; ++ ++ map[wordInMap] &= ~mask; ++ map[wordInMap] |= (mask & (val << bitInWord)); ++ ++ if(dev->tnodeWidth > (32-bitInWord)) { ++ bitInWord = (32 - bitInWord); ++ wordInMap++;; ++ mask = dev->tnodeMask >> (/*dev->tnodeWidth -*/ bitInWord); ++ map[wordInMap] &= ~mask; ++ map[wordInMap] |= (mask & (val >> bitInWord)); ++ } ++} ++ ++static __u32 yaffs_GetChunkGroupBase(yaffs_Device *dev, yaffs_Tnode *tn, unsigned pos) ++{ ++ __u32 *map = (__u32 *)tn; ++ __u32 bitInMap; ++ __u32 bitInWord; ++ __u32 wordInMap; ++ __u32 val; ++ ++ pos &= YAFFS_TNODES_LEVEL0_MASK; ++ ++ bitInMap = pos * dev->tnodeWidth; ++ wordInMap = bitInMap /32; ++ bitInWord = bitInMap & (32 -1); ++ ++ val = map[wordInMap] >> bitInWord; ++ ++ if(dev->tnodeWidth > (32-bitInWord)) { ++ bitInWord = (32 - bitInWord); ++ wordInMap++;; ++ val |= (map[wordInMap] << bitInWord); ++ } ++ ++ val &= dev->tnodeMask; ++ val <<= dev->chunkGroupBits; ++ ++ return val; ++} ++ ++/* ------------------- End of individual tnode manipulation -----------------*/ ++ ++/* ---------Functions to manipulate the look-up tree (made up of tnodes) ------ ++ * The look up tree is represented by the top tnode and the number of topLevel ++ * in the tree. 0 means only the level 0 tnode is in the tree. ++ */ ++ ++/* FindLevel0Tnode finds the level 0 tnode, if one exists. */ ++static yaffs_Tnode *yaffs_FindLevel0Tnode(yaffs_Device * dev, ++ yaffs_FileStructure * fStruct, ++ __u32 chunkId) ++{ ++ ++ yaffs_Tnode *tn = fStruct->top; ++ __u32 i; ++ int requiredTallness; ++ int level = fStruct->topLevel; ++ ++ /* Check sane level and chunk Id */ ++ if (level < 0 || level > YAFFS_TNODES_MAX_LEVEL) { ++ return NULL; ++ } ++ ++ if (chunkId > YAFFS_MAX_CHUNK_ID) { ++ return NULL; ++ } ++ ++ /* First check we're tall enough (ie enough topLevel) */ ++ ++ i = chunkId >> YAFFS_TNODES_LEVEL0_BITS; ++ requiredTallness = 0; ++ while (i) { ++ i >>= YAFFS_TNODES_INTERNAL_BITS; ++ requiredTallness++; ++ } ++ ++ if (requiredTallness > fStruct->topLevel) { ++ /* Not tall enough, so we can't find it, return NULL. */ ++ return NULL; ++ } ++ ++ /* Traverse down to level 0 */ ++ while (level > 0 && tn) { ++ tn = tn-> ++ internal[(chunkId >> ++ ( YAFFS_TNODES_LEVEL0_BITS + ++ (level - 1) * ++ YAFFS_TNODES_INTERNAL_BITS) ++ ) & ++ YAFFS_TNODES_INTERNAL_MASK]; ++ level--; ++ ++ } ++ ++ return tn; ++} ++ ++/* AddOrFindLevel0Tnode finds the level 0 tnode if it exists, otherwise first expands the tree. ++ * This happens in two steps: ++ * 1. If the tree isn't tall enough, then make it taller. ++ * 2. Scan down the tree towards the level 0 tnode adding tnodes if required. ++ * ++ * Used when modifying the tree. ++ * ++ * If the tn argument is NULL, then a fresh tnode will be added otherwise the specified tn will ++ * be plugged into the ttree. ++ */ ++ ++static yaffs_Tnode *yaffs_AddOrFindLevel0Tnode(yaffs_Device * dev, ++ yaffs_FileStructure * fStruct, ++ __u32 chunkId, ++ yaffs_Tnode *passedTn) ++{ ++ ++ int requiredTallness; ++ int i; ++ int l; ++ yaffs_Tnode *tn; ++ ++ __u32 x; ++ ++ ++ /* Check sane level and page Id */ ++ if (fStruct->topLevel < 0 || fStruct->topLevel > YAFFS_TNODES_MAX_LEVEL) { ++ return NULL; ++ } ++ ++ if (chunkId > YAFFS_MAX_CHUNK_ID) { ++ return NULL; ++ } ++ ++ /* First check we're tall enough (ie enough topLevel) */ ++ ++ x = chunkId >> YAFFS_TNODES_LEVEL0_BITS; ++ requiredTallness = 0; ++ while (x) { ++ x >>= YAFFS_TNODES_INTERNAL_BITS; ++ requiredTallness++; ++ } ++ ++ ++ if (requiredTallness > fStruct->topLevel) { ++ /* Not tall enough,gotta make the tree taller */ ++ for (i = fStruct->topLevel; i < requiredTallness; i++) { ++ ++ tn = yaffs_GetTnode(dev); ++ ++ if (tn) { ++ tn->internal[0] = fStruct->top; ++ fStruct->top = tn; ++ } else { ++ T(YAFFS_TRACE_ERROR, ++ (TSTR("yaffs: no more tnodes" TENDSTR))); ++ } ++ } ++ ++ fStruct->topLevel = requiredTallness; ++ } ++ ++ /* Traverse down to level 0, adding anything we need */ ++ ++ l = fStruct->topLevel; ++ tn = fStruct->top; ++ ++ if(l > 0) { ++ while (l > 0 && tn) { ++ x = (chunkId >> ++ ( YAFFS_TNODES_LEVEL0_BITS + ++ (l - 1) * YAFFS_TNODES_INTERNAL_BITS)) & ++ YAFFS_TNODES_INTERNAL_MASK; ++ ++ ++ if((l>1) && !tn->internal[x]){ ++ /* Add missing non-level-zero tnode */ ++ tn->internal[x] = yaffs_GetTnode(dev); ++ ++ } else if(l == 1) { ++ /* Looking from level 1 at level 0 */ ++ if (passedTn) { ++ /* If we already have one, then release it.*/ ++ if(tn->internal[x]) ++ yaffs_FreeTnode(dev,tn->internal[x]); ++ tn->internal[x] = passedTn; ++ ++ } else if(!tn->internal[x]) { ++ /* Don't have one, none passed in */ ++ tn->internal[x] = yaffs_GetTnode(dev); ++ } ++ } ++ ++ tn = tn->internal[x]; ++ l--; ++ } ++ } else { ++ /* top is level 0 */ ++ if(passedTn) { ++ memcpy(tn,passedTn,(dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8); ++ yaffs_FreeTnode(dev,passedTn); ++ } ++ } ++ ++ return tn; ++} ++ ++static int yaffs_FindChunkInGroup(yaffs_Device * dev, int theChunk, ++ yaffs_ExtendedTags * tags, int objectId, ++ int chunkInInode) ++{ ++ int j; ++ ++ for (j = 0; theChunk && j < dev->chunkGroupSize; j++) { ++ if (yaffs_CheckChunkBit ++ (dev, theChunk / dev->nChunksPerBlock, ++ theChunk % dev->nChunksPerBlock)) { ++ yaffs_ReadChunkWithTagsFromNAND(dev, theChunk, NULL, ++ tags); ++ if (yaffs_TagsMatch(tags, objectId, chunkInInode)) { ++ /* found it; */ ++ return theChunk; ++ ++ } ++ } ++ theChunk++; ++ } ++ return -1; ++} ++ ++ ++/* DeleteWorker scans backwards through the tnode tree and deletes all the ++ * chunks and tnodes in the file ++ * Returns 1 if the tree was deleted. ++ * Returns 0 if it stopped early due to hitting the limit and the delete is incomplete. ++ */ ++ ++static int yaffs_DeleteWorker(yaffs_Object * in, yaffs_Tnode * tn, __u32 level, ++ int chunkOffset, int *limit) ++{ ++ int i; ++ int chunkInInode; ++ int theChunk; ++ yaffs_ExtendedTags tags; ++ int foundChunk; ++ yaffs_Device *dev = in->myDev; ++ ++ int allDone = 1; ++ ++ if (tn) { ++ if (level > 0) { ++ ++ for (i = YAFFS_NTNODES_INTERNAL - 1; allDone && i >= 0; ++ i--) { ++ if (tn->internal[i]) { ++ if (limit && (*limit) < 0) { ++ allDone = 0; ++ } else { ++ allDone = ++ yaffs_DeleteWorker(in, ++ tn-> ++ internal ++ [i], ++ level - ++ 1, ++ (chunkOffset ++ << ++ YAFFS_TNODES_INTERNAL_BITS) ++ + i, ++ limit); ++ } ++ if (allDone) { ++ yaffs_FreeTnode(dev, ++ tn-> ++ internal[i]); ++ tn->internal[i] = NULL; ++ } ++ } ++ ++ } ++ return (allDone) ? 1 : 0; ++ } else if (level == 0) { ++ int hitLimit = 0; ++ ++ for (i = YAFFS_NTNODES_LEVEL0 - 1; i >= 0 && !hitLimit; ++ i--) { ++ theChunk = yaffs_GetChunkGroupBase(dev,tn,i); ++ if (theChunk) { ++ ++ chunkInInode = ++ (chunkOffset << ++ YAFFS_TNODES_LEVEL0_BITS) + i; ++ ++ foundChunk = ++ yaffs_FindChunkInGroup(dev, ++ theChunk, ++ &tags, ++ in->objectId, ++ chunkInInode); ++ ++ if (foundChunk > 0) { ++ yaffs_DeleteChunk(dev, ++ foundChunk, 1, ++ __LINE__); ++ in->nDataChunks--; ++ if (limit) { ++ *limit = *limit - 1; ++ if (*limit <= 0) { ++ hitLimit = 1; ++ } ++ } ++ ++ } ++ ++ yaffs_PutLevel0Tnode(dev,tn,i,0); ++ } ++ ++ } ++ return (i < 0) ? 1 : 0; ++ ++ } ++ ++ } ++ ++ return 1; ++ ++} ++ ++static void yaffs_SoftDeleteChunk(yaffs_Device * dev, int chunk) ++{ ++ ++ yaffs_BlockInfo *theBlock; ++ ++ T(YAFFS_TRACE_DELETION, (TSTR("soft delete chunk %d" TENDSTR), chunk)); ++ ++ theBlock = yaffs_GetBlockInfo(dev, chunk / dev->nChunksPerBlock); ++ if (theBlock) { ++ theBlock->softDeletions++; ++ dev->nFreeChunks++; ++ } ++} ++ ++/* SoftDeleteWorker scans backwards through the tnode tree and soft deletes all the chunks in the file. ++ * All soft deleting does is increment the block's softdelete count and pulls the chunk out ++ * of the tnode. ++ * Thus, essentially this is the same as DeleteWorker except that the chunks are soft deleted. ++ */ ++ ++static int yaffs_SoftDeleteWorker(yaffs_Object * in, yaffs_Tnode * tn, ++ __u32 level, int chunkOffset) ++{ ++ int i; ++ int theChunk; ++ int allDone = 1; ++ yaffs_Device *dev = in->myDev; ++ ++ if (tn) { ++ if (level > 0) { ++ ++ for (i = YAFFS_NTNODES_INTERNAL - 1; allDone && i >= 0; ++ i--) { ++ if (tn->internal[i]) { ++ allDone = ++ yaffs_SoftDeleteWorker(in, ++ tn-> ++ internal[i], ++ level - 1, ++ (chunkOffset ++ << ++ YAFFS_TNODES_INTERNAL_BITS) ++ + i); ++ if (allDone) { ++ yaffs_FreeTnode(dev, ++ tn-> ++ internal[i]); ++ tn->internal[i] = NULL; ++ } else { ++ /* Hoosterman... how could this happen? */ ++ } ++ } ++ } ++ return (allDone) ? 1 : 0; ++ } else if (level == 0) { ++ ++ for (i = YAFFS_NTNODES_LEVEL0 - 1; i >= 0; i--) { ++ theChunk = yaffs_GetChunkGroupBase(dev,tn,i); ++ if (theChunk) { ++ /* Note this does not find the real chunk, only the chunk group. ++ * We make an assumption that a chunk group is not larger than ++ * a block. ++ */ ++ yaffs_SoftDeleteChunk(dev, theChunk); ++ yaffs_PutLevel0Tnode(dev,tn,i,0); ++ } ++ ++ } ++ return 1; ++ ++ } ++ ++ } ++ ++ return 1; ++ ++} ++ ++static void yaffs_SoftDeleteFile(yaffs_Object * obj) ++{ ++ if (obj->deleted && ++ obj->variantType == YAFFS_OBJECT_TYPE_FILE && !obj->softDeleted) { ++ if (obj->nDataChunks <= 0) { ++ /* Empty file with no duplicate object headers, just delete it immediately */ ++ yaffs_FreeTnode(obj->myDev, ++ obj->variant.fileVariant.top); ++ obj->variant.fileVariant.top = NULL; ++ T(YAFFS_TRACE_TRACING, ++ (TSTR("yaffs: Deleting empty file %d" TENDSTR), ++ obj->objectId)); ++ yaffs_DoGenericObjectDeletion(obj); ++ } else { ++ yaffs_SoftDeleteWorker(obj, ++ obj->variant.fileVariant.top, ++ obj->variant.fileVariant. ++ topLevel, 0); ++ obj->softDeleted = 1; ++ } ++ } ++} ++ ++/* Pruning removes any part of the file structure tree that is beyond the ++ * bounds of the file (ie that does not point to chunks). ++ * ++ * A file should only get pruned when its size is reduced. ++ * ++ * Before pruning, the chunks must be pulled from the tree and the ++ * level 0 tnode entries must be zeroed out. ++ * Could also use this for file deletion, but that's probably better handled ++ * by a special case. ++ */ ++ ++static yaffs_Tnode *yaffs_PruneWorker(yaffs_Device * dev, yaffs_Tnode * tn, ++ __u32 level, int del0) ++{ ++ int i; ++ int hasData; ++ ++ if (tn) { ++ hasData = 0; ++ ++ for (i = 0; i < YAFFS_NTNODES_INTERNAL; i++) { ++ if (tn->internal[i] && level > 0) { ++ tn->internal[i] = ++ yaffs_PruneWorker(dev, tn->internal[i], ++ level - 1, ++ (i == 0) ? del0 : 1); ++ } ++ ++ if (tn->internal[i]) { ++ hasData++; ++ } ++ } ++ ++ if (hasData == 0 && del0) { ++ /* Free and return NULL */ ++ ++ yaffs_FreeTnode(dev, tn); ++ tn = NULL; ++ } ++ ++ } ++ ++ return tn; ++ ++} ++ ++static int yaffs_PruneFileStructure(yaffs_Device * dev, ++ yaffs_FileStructure * fStruct) ++{ ++ int i; ++ int hasData; ++ int done = 0; ++ yaffs_Tnode *tn; ++ ++ if (fStruct->topLevel > 0) { ++ fStruct->top = ++ yaffs_PruneWorker(dev, fStruct->top, fStruct->topLevel, 0); ++ ++ /* Now we have a tree with all the non-zero branches NULL but the height ++ * is the same as it was. ++ * Let's see if we can trim internal tnodes to shorten the tree. ++ * We can do this if only the 0th element in the tnode is in use ++ * (ie all the non-zero are NULL) ++ */ ++ ++ while (fStruct->topLevel && !done) { ++ tn = fStruct->top; ++ ++ hasData = 0; ++ for (i = 1; i < YAFFS_NTNODES_INTERNAL; i++) { ++ if (tn->internal[i]) { ++ hasData++; ++ } ++ } ++ ++ if (!hasData) { ++ fStruct->top = tn->internal[0]; ++ fStruct->topLevel--; ++ yaffs_FreeTnode(dev, tn); ++ } else { ++ done = 1; ++ } ++ } ++ } ++ ++ return YAFFS_OK; ++} ++ ++/*-------------------- End of File Structure functions.-------------------*/ ++ ++/* yaffs_CreateFreeObjects creates a bunch more objects and ++ * adds them to the object free list. ++ */ ++static int yaffs_CreateFreeObjects(yaffs_Device * dev, int nObjects) ++{ ++ int i; ++ yaffs_Object *newObjects; ++ yaffs_ObjectList *list; ++ ++ if (nObjects < 1) ++ return YAFFS_OK; ++ ++ /* make these things */ ++ newObjects = YMALLOC(nObjects * sizeof(yaffs_Object)); ++ list = YMALLOC(sizeof(yaffs_ObjectList)); ++ ++ if (!newObjects || !list) { ++ if(newObjects) ++ YFREE(newObjects); ++ if(list) ++ YFREE(list); ++ T(YAFFS_TRACE_ALLOCATE, ++ (TSTR("yaffs: Could not allocate more objects" TENDSTR))); ++ return YAFFS_FAIL; ++ } ++ ++ /* Hook them into the free list */ ++ for (i = 0; i < nObjects - 1; i++) { ++ newObjects[i].siblings.next = ++ (struct ylist_head *)(&newObjects[i + 1]); ++ } ++ ++ newObjects[nObjects - 1].siblings.next = (void *)dev->freeObjects; ++ dev->freeObjects = newObjects; ++ dev->nFreeObjects += nObjects; ++ dev->nObjectsCreated += nObjects; ++ ++ /* Now add this bunch of Objects to a list for freeing up. */ ++ ++ list->objects = newObjects; ++ list->next = dev->allocatedObjectList; ++ dev->allocatedObjectList = list; ++ ++ return YAFFS_OK; ++} ++ ++ ++/* AllocateEmptyObject gets us a clean Object. Tries to make allocate more if we run out */ ++static yaffs_Object *yaffs_AllocateEmptyObject(yaffs_Device * dev) ++{ ++ yaffs_Object *tn = NULL; ++ ++#ifdef VALGRIND_TEST ++ tn = YMALLOC(sizeof(yaffs_Object)); ++#else ++ /* If there are none left make more */ ++ if (!dev->freeObjects) { ++ yaffs_CreateFreeObjects(dev, YAFFS_ALLOCATION_NOBJECTS); ++ } ++ ++ if (dev->freeObjects) { ++ tn = dev->freeObjects; ++ dev->freeObjects = ++ (yaffs_Object *) (dev->freeObjects->siblings.next); ++ dev->nFreeObjects--; ++ } ++#endif ++ if(tn){ ++ /* Now sweeten it up... */ ++ ++ memset(tn, 0, sizeof(yaffs_Object)); ++ tn->beingCreated = 1; ++ ++ tn->myDev = dev; ++ tn->hdrChunk = 0; ++ tn->variantType = YAFFS_OBJECT_TYPE_UNKNOWN; ++ YINIT_LIST_HEAD(&(tn->hardLinks)); ++ YINIT_LIST_HEAD(&(tn->hashLink)); ++ YINIT_LIST_HEAD(&tn->siblings); ++ ++ ++ /* Now make the directory sane */ ++ if(dev->rootDir){ ++ tn->parent = dev->rootDir; ++ ylist_add(&(tn->siblings),&dev->rootDir->variant.directoryVariant.children); ++ } ++ ++ /* Add it to the lost and found directory. ++ * NB Can't put root or lostNFound in lostNFound so ++ * check if lostNFound exists first ++ */ ++ if (dev->lostNFoundDir) { ++ yaffs_AddObjectToDirectory(dev->lostNFoundDir, tn); ++ } ++ ++ tn->beingCreated = 0; ++ } ++ ++ dev->nCheckpointBlocksRequired = 0; /* force recalculation*/ ++ ++ return tn; ++} ++ ++static yaffs_Object *yaffs_CreateFakeDirectory(yaffs_Device * dev, int number, ++ __u32 mode) ++{ ++ ++ yaffs_Object *obj = ++ yaffs_CreateNewObject(dev, number, YAFFS_OBJECT_TYPE_DIRECTORY); ++ if (obj) { ++ obj->fake = 1; /* it is fake so it might have no NAND presence... */ ++ obj->renameAllowed = 0; /* ... and we're not allowed to rename it... */ ++ obj->unlinkAllowed = 0; /* ... or unlink it */ ++ obj->deleted = 0; ++ obj->unlinked = 0; ++ obj->yst_mode = mode; ++ obj->myDev = dev; ++ obj->hdrChunk = 0; /* Not a valid chunk. */ ++ } ++ ++ return obj; ++ ++} ++ ++static void yaffs_UnhashObject(yaffs_Object * tn) ++{ ++ int bucket; ++ yaffs_Device *dev = tn->myDev; ++ ++ /* If it is still linked into the bucket list, free from the list */ ++ if (!ylist_empty(&tn->hashLink)) { ++ ylist_del_init(&tn->hashLink); ++ bucket = yaffs_HashFunction(tn->objectId); ++ dev->objectBucket[bucket].count--; ++ } ++ ++} ++ ++/* FreeObject frees up a Object and puts it back on the free list */ ++static void yaffs_FreeObject(yaffs_Object * tn) ++{ ++ ++ yaffs_Device *dev = tn->myDev; ++ ++ ++ if(tn->parent) ++ YBUG(); ++ if(!ylist_empty(&tn->siblings)) ++ YBUG(); ++ ++ ++#ifdef __KERNEL__ ++ if (tn->myInode) { ++ /* We're still hooked up to a cached inode. ++ * Don't delete now, but mark for later deletion ++ */ ++ tn->deferedFree = 1; ++ return; ++ } ++#endif ++ ++ yaffs_UnhashObject(tn); ++ ++#ifdef VALGRIND_TEST ++ YFREE(tn); ++#else ++ /* Link into the free list. */ ++ tn->siblings.next = (struct ylist_head *)(dev->freeObjects); ++ dev->freeObjects = tn; ++ dev->nFreeObjects++; ++#endif ++ dev->nCheckpointBlocksRequired = 0; /* force recalculation*/ ++ ++} ++ ++#ifdef __KERNEL__ ++ ++void yaffs_HandleDeferedFree(yaffs_Object * obj) ++{ ++ if (obj->deferedFree) { ++ yaffs_FreeObject(obj); ++ } ++} ++ ++#endif ++ ++static void yaffs_DeinitialiseObjects(yaffs_Device * dev) ++{ ++ /* Free the list of allocated Objects */ ++ ++ yaffs_ObjectList *tmp; ++ ++ while (dev->allocatedObjectList) { ++ tmp = dev->allocatedObjectList->next; ++ YFREE(dev->allocatedObjectList->objects); ++ YFREE(dev->allocatedObjectList); ++ ++ dev->allocatedObjectList = tmp; ++ } ++ ++ dev->freeObjects = NULL; ++ dev->nFreeObjects = 0; ++} ++ ++static void yaffs_InitialiseObjects(yaffs_Device * dev) ++{ ++ int i; ++ ++ dev->allocatedObjectList = NULL; ++ dev->freeObjects = NULL; ++ dev->nFreeObjects = 0; ++ ++ for (i = 0; i < YAFFS_NOBJECT_BUCKETS; i++) { ++ YINIT_LIST_HEAD(&dev->objectBucket[i].list); ++ dev->objectBucket[i].count = 0; ++ } ++ ++} ++ ++static int yaffs_FindNiceObjectBucket(yaffs_Device * dev) ++{ ++ static int x = 0; ++ int i; ++ int l = 999; ++ int lowest = 999999; ++ ++ /* First let's see if we can find one that's empty. */ ++ ++ for (i = 0; i < 10 && lowest > 0; i++) { ++ x++; ++ x %= YAFFS_NOBJECT_BUCKETS; ++ if (dev->objectBucket[x].count < lowest) { ++ lowest = dev->objectBucket[x].count; ++ l = x; ++ } ++ ++ } ++ ++ /* If we didn't find an empty list, then try ++ * looking a bit further for a short one ++ */ ++ ++ for (i = 0; i < 10 && lowest > 3; i++) { ++ x++; ++ x %= YAFFS_NOBJECT_BUCKETS; ++ if (dev->objectBucket[x].count < lowest) { ++ lowest = dev->objectBucket[x].count; ++ l = x; ++ } ++ ++ } ++ ++ return l; ++} ++ ++static int yaffs_CreateNewObjectNumber(yaffs_Device * dev) ++{ ++ int bucket = yaffs_FindNiceObjectBucket(dev); ++ ++ /* Now find an object value that has not already been taken ++ * by scanning the list. ++ */ ++ ++ int found = 0; ++ struct ylist_head *i; ++ ++ __u32 n = (__u32) bucket; ++ ++ /* yaffs_CheckObjectHashSanity(); */ ++ ++ while (!found) { ++ found = 1; ++ n += YAFFS_NOBJECT_BUCKETS; ++ if (1 || dev->objectBucket[bucket].count > 0) { ++ ylist_for_each(i, &dev->objectBucket[bucket].list) { ++ /* If there is already one in the list */ ++ if (i ++ && ylist_entry(i, yaffs_Object, ++ hashLink)->objectId == n) { ++ found = 0; ++ } ++ } ++ } ++ } ++ ++ ++ return n; ++} ++ ++static void yaffs_HashObject(yaffs_Object * in) ++{ ++ int bucket = yaffs_HashFunction(in->objectId); ++ yaffs_Device *dev = in->myDev; ++ ++ ylist_add(&in->hashLink, &dev->objectBucket[bucket].list); ++ dev->objectBucket[bucket].count++; ++ ++} ++ ++yaffs_Object *yaffs_FindObjectByNumber(yaffs_Device * dev, __u32 number) ++{ ++ int bucket = yaffs_HashFunction(number); ++ struct ylist_head *i; ++ yaffs_Object *in; ++ ++ ylist_for_each(i, &dev->objectBucket[bucket].list) { ++ /* Look if it is in the list */ ++ if (i) { ++ in = ylist_entry(i, yaffs_Object, hashLink); ++ if (in->objectId == number) { ++#ifdef __KERNEL__ ++ /* Don't tell the VFS about this one if it is defered free */ ++ if (in->deferedFree) ++ return NULL; ++#endif ++ ++ return in; ++ } ++ } ++ } ++ ++ return NULL; ++} ++ ++yaffs_Object *yaffs_CreateNewObject(yaffs_Device * dev, int number, ++ yaffs_ObjectType type) ++{ ++ ++ yaffs_Object *theObject; ++ yaffs_Tnode *tn = NULL; ++ ++ if (number < 0) { ++ number = yaffs_CreateNewObjectNumber(dev); ++ } ++ ++ theObject = yaffs_AllocateEmptyObject(dev); ++ if(!theObject) ++ return NULL; ++ ++ if(type == YAFFS_OBJECT_TYPE_FILE){ ++ tn = yaffs_GetTnode(dev); ++ if(!tn){ ++ yaffs_FreeObject(theObject); ++ return NULL; ++ } ++ } ++ ++ ++ ++ if (theObject) { ++ theObject->fake = 0; ++ theObject->renameAllowed = 1; ++ theObject->unlinkAllowed = 1; ++ theObject->objectId = number; ++ yaffs_HashObject(theObject); ++ theObject->variantType = type; ++#ifdef CONFIG_YAFFS_WINCE ++ yfsd_WinFileTimeNow(theObject->win_atime); ++ theObject->win_ctime[0] = theObject->win_mtime[0] = ++ theObject->win_atime[0]; ++ theObject->win_ctime[1] = theObject->win_mtime[1] = ++ theObject->win_atime[1]; ++ ++#else ++ ++ theObject->yst_atime = theObject->yst_mtime = ++ theObject->yst_ctime = Y_CURRENT_TIME; ++#endif ++ switch (type) { ++ case YAFFS_OBJECT_TYPE_FILE: ++ theObject->variant.fileVariant.fileSize = 0; ++ theObject->variant.fileVariant.scannedFileSize = 0; ++ theObject->variant.fileVariant.shrinkSize = 0xFFFFFFFF; /* max __u32 */ ++ theObject->variant.fileVariant.topLevel = 0; ++ theObject->variant.fileVariant.top = tn; ++ break; ++ case YAFFS_OBJECT_TYPE_DIRECTORY: ++ YINIT_LIST_HEAD(&theObject->variant.directoryVariant. ++ children); ++ break; ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ case YAFFS_OBJECT_TYPE_HARDLINK: ++ case YAFFS_OBJECT_TYPE_SPECIAL: ++ /* No action required */ ++ break; ++ case YAFFS_OBJECT_TYPE_UNKNOWN: ++ /* todo this should not happen */ ++ break; ++ } ++ } ++ ++ return theObject; ++} ++ ++static yaffs_Object *yaffs_FindOrCreateObjectByNumber(yaffs_Device * dev, ++ int number, ++ yaffs_ObjectType type) ++{ ++ yaffs_Object *theObject = NULL; ++ ++ if (number > 0) { ++ theObject = yaffs_FindObjectByNumber(dev, number); ++ } ++ ++ if (!theObject) { ++ theObject = yaffs_CreateNewObject(dev, number, type); ++ } ++ ++ return theObject; ++ ++} ++ ++ ++static YCHAR *yaffs_CloneString(const YCHAR * str) ++{ ++ YCHAR *newStr = NULL; ++ ++ if (str && *str) { ++ newStr = YMALLOC((yaffs_strlen(str) + 1) * sizeof(YCHAR)); ++ if(newStr) ++ yaffs_strcpy(newStr, str); ++ } ++ ++ return newStr; ++ ++} ++ ++/* ++ * Mknod (create) a new object. ++ * equivalentObject only has meaning for a hard link; ++ * aliasString only has meaning for a sumlink. ++ * rdev only has meaning for devices (a subset of special objects) ++ */ ++ ++static yaffs_Object *yaffs_MknodObject(yaffs_ObjectType type, ++ yaffs_Object * parent, ++ const YCHAR * name, ++ __u32 mode, ++ __u32 uid, ++ __u32 gid, ++ yaffs_Object * equivalentObject, ++ const YCHAR * aliasString, __u32 rdev) ++{ ++ yaffs_Object *in; ++ YCHAR *str = NULL; ++ ++ yaffs_Device *dev = parent->myDev; ++ ++ /* Check if the entry exists. If it does then fail the call since we don't want a dup.*/ ++ if (yaffs_FindObjectByName(parent, name)) { ++ return NULL; ++ } ++ ++ in = yaffs_CreateNewObject(dev, -1, type); ++ ++ if(!in) ++ return YAFFS_FAIL; ++ ++ if(type == YAFFS_OBJECT_TYPE_SYMLINK){ ++ str = yaffs_CloneString(aliasString); ++ if(!str){ ++ yaffs_FreeObject(in); ++ return NULL; ++ } ++ } ++ ++ ++ ++ if (in) { ++ in->hdrChunk = 0; ++ in->valid = 1; ++ in->variantType = type; ++ ++ in->yst_mode = mode; ++ ++#ifdef CONFIG_YAFFS_WINCE ++ yfsd_WinFileTimeNow(in->win_atime); ++ in->win_ctime[0] = in->win_mtime[0] = in->win_atime[0]; ++ in->win_ctime[1] = in->win_mtime[1] = in->win_atime[1]; ++ ++#else ++ in->yst_atime = in->yst_mtime = in->yst_ctime = Y_CURRENT_TIME; ++ ++ in->yst_rdev = rdev; ++ in->yst_uid = uid; ++ in->yst_gid = gid; ++#endif ++ in->nDataChunks = 0; ++ ++ yaffs_SetObjectName(in, name); ++ in->dirty = 1; ++ ++ yaffs_AddObjectToDirectory(parent, in); ++ ++ in->myDev = parent->myDev; ++ ++ switch (type) { ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ in->variant.symLinkVariant.alias = str; ++ break; ++ case YAFFS_OBJECT_TYPE_HARDLINK: ++ in->variant.hardLinkVariant.equivalentObject = ++ equivalentObject; ++ in->variant.hardLinkVariant.equivalentObjectId = ++ equivalentObject->objectId; ++ ylist_add(&in->hardLinks, &equivalentObject->hardLinks); ++ break; ++ case YAFFS_OBJECT_TYPE_FILE: ++ case YAFFS_OBJECT_TYPE_DIRECTORY: ++ case YAFFS_OBJECT_TYPE_SPECIAL: ++ case YAFFS_OBJECT_TYPE_UNKNOWN: ++ /* do nothing */ ++ break; ++ } ++ ++ if (yaffs_UpdateObjectHeader(in, name, 0, 0, 0) < 0) { ++ /* Could not create the object header, fail the creation */ ++ yaffs_DestroyObject(in); ++ in = NULL; ++ } ++ ++ } ++ ++ return in; ++} ++ ++yaffs_Object *yaffs_MknodFile(yaffs_Object * parent, const YCHAR * name, ++ __u32 mode, __u32 uid, __u32 gid) ++{ ++ return yaffs_MknodObject(YAFFS_OBJECT_TYPE_FILE, parent, name, mode, ++ uid, gid, NULL, NULL, 0); ++} ++ ++yaffs_Object *yaffs_MknodDirectory(yaffs_Object * parent, const YCHAR * name, ++ __u32 mode, __u32 uid, __u32 gid) ++{ ++ return yaffs_MknodObject(YAFFS_OBJECT_TYPE_DIRECTORY, parent, name, ++ mode, uid, gid, NULL, NULL, 0); ++} ++ ++yaffs_Object *yaffs_MknodSpecial(yaffs_Object * parent, const YCHAR * name, ++ __u32 mode, __u32 uid, __u32 gid, __u32 rdev) ++{ ++ return yaffs_MknodObject(YAFFS_OBJECT_TYPE_SPECIAL, parent, name, mode, ++ uid, gid, NULL, NULL, rdev); ++} ++ ++yaffs_Object *yaffs_MknodSymLink(yaffs_Object * parent, const YCHAR * name, ++ __u32 mode, __u32 uid, __u32 gid, ++ const YCHAR * alias) ++{ ++ return yaffs_MknodObject(YAFFS_OBJECT_TYPE_SYMLINK, parent, name, mode, ++ uid, gid, NULL, alias, 0); ++} ++ ++/* yaffs_Link returns the object id of the equivalent object.*/ ++yaffs_Object *yaffs_Link(yaffs_Object * parent, const YCHAR * name, ++ yaffs_Object * equivalentObject) ++{ ++ /* Get the real object in case we were fed a hard link as an equivalent object */ ++ equivalentObject = yaffs_GetEquivalentObject(equivalentObject); ++ ++ if (yaffs_MknodObject ++ (YAFFS_OBJECT_TYPE_HARDLINK, parent, name, 0, 0, 0, ++ equivalentObject, NULL, 0)) { ++ return equivalentObject; ++ } else { ++ return NULL; ++ } ++ ++} ++ ++static int yaffs_ChangeObjectName(yaffs_Object * obj, yaffs_Object * newDir, ++ const YCHAR * newName, int force, int shadows) ++{ ++ int unlinkOp; ++ int deleteOp; ++ ++ yaffs_Object *existingTarget; ++ ++ if (newDir == NULL) { ++ newDir = obj->parent; /* use the old directory */ ++ } ++ ++ if (newDir->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) { ++ T(YAFFS_TRACE_ALWAYS, ++ (TSTR ++ ("tragedy: yaffs_ChangeObjectName: newDir is not a directory" ++ TENDSTR))); ++ YBUG(); ++ } ++ ++ /* TODO: Do we need this different handling for YAFFS2 and YAFFS1?? */ ++ if (obj->myDev->isYaffs2) { ++ unlinkOp = (newDir == obj->myDev->unlinkedDir); ++ } else { ++ unlinkOp = (newDir == obj->myDev->unlinkedDir ++ && obj->variantType == YAFFS_OBJECT_TYPE_FILE); ++ } ++ ++ deleteOp = (newDir == obj->myDev->deletedDir); ++ ++ existingTarget = yaffs_FindObjectByName(newDir, newName); ++ ++ /* If the object is a file going into the unlinked directory, ++ * then it is OK to just stuff it in since duplicate names are allowed. ++ * else only proceed if the new name does not exist and if we're putting ++ * it into a directory. ++ */ ++ if ((unlinkOp || ++ deleteOp || ++ force || ++ (shadows > 0) || ++ !existingTarget) && ++ newDir->variantType == YAFFS_OBJECT_TYPE_DIRECTORY) { ++ yaffs_SetObjectName(obj, newName); ++ obj->dirty = 1; ++ ++ yaffs_AddObjectToDirectory(newDir, obj); ++ ++ if (unlinkOp) ++ obj->unlinked = 1; ++ ++ /* If it is a deletion then we mark it as a shrink for gc purposes. */ ++ if (yaffs_UpdateObjectHeader(obj, newName, 0, deleteOp, shadows)>= 0) ++ return YAFFS_OK; ++ } ++ ++ return YAFFS_FAIL; ++} ++ ++int yaffs_RenameObject(yaffs_Object * oldDir, const YCHAR * oldName, ++ yaffs_Object * newDir, const YCHAR * newName) ++{ ++ yaffs_Object *obj=NULL; ++ yaffs_Object *existingTarget=NULL; ++ int force = 0; ++ ++ ++ if(!oldDir || oldDir->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) ++ YBUG(); ++ if(!newDir || newDir->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) ++ YBUG(); ++ ++#ifdef CONFIG_YAFFS_CASE_INSENSITIVE ++ /* Special case for case insemsitive systems (eg. WinCE). ++ * While look-up is case insensitive, the name isn't. ++ * Therefore we might want to change x.txt to X.txt ++ */ ++ if (oldDir == newDir && yaffs_strcmp(oldName, newName) == 0) { ++ force = 1; ++ } ++#endif ++ ++ else if (yaffs_strlen(newName) > YAFFS_MAX_NAME_LENGTH) ++ /* ENAMETOOLONG */ ++ return YAFFS_FAIL; ++ ++ obj = yaffs_FindObjectByName(oldDir, oldName); ++ ++ if (obj && obj->renameAllowed) { ++ ++ /* Now do the handling for an existing target, if there is one */ ++ ++ existingTarget = yaffs_FindObjectByName(newDir, newName); ++ if (existingTarget && ++ existingTarget->variantType == YAFFS_OBJECT_TYPE_DIRECTORY && ++ !ylist_empty(&existingTarget->variant.directoryVariant.children)) { ++ /* There is a target that is a non-empty directory, so we fail */ ++ return YAFFS_FAIL; /* EEXIST or ENOTEMPTY */ ++ } else if (existingTarget && existingTarget != obj) { ++ /* Nuke the target first, using shadowing, ++ * but only if it isn't the same object ++ */ ++ yaffs_ChangeObjectName(obj, newDir, newName, force, ++ existingTarget->objectId); ++ yaffs_UnlinkObject(existingTarget); ++ } ++ ++ return yaffs_ChangeObjectName(obj, newDir, newName, 1, 0); ++ } ++ return YAFFS_FAIL; ++} ++ ++/*------------------------- Block Management and Page Allocation ----------------*/ ++ ++static int yaffs_InitialiseBlocks(yaffs_Device * dev) ++{ ++ int nBlocks = dev->internalEndBlock - dev->internalStartBlock + 1; ++ ++ dev->blockInfo = NULL; ++ dev->chunkBits = NULL; ++ ++ dev->allocationBlock = -1; /* force it to get a new one */ ++ ++ /* If the first allocation strategy fails, thry the alternate one */ ++ dev->blockInfo = YMALLOC(nBlocks * sizeof(yaffs_BlockInfo)); ++ if(!dev->blockInfo){ ++ dev->blockInfo = YMALLOC_ALT(nBlocks * sizeof(yaffs_BlockInfo)); ++ dev->blockInfoAlt = 1; ++ } ++ else ++ dev->blockInfoAlt = 0; ++ ++ if(dev->blockInfo){ ++ ++ /* Set up dynamic blockinfo stuff. */ ++ dev->chunkBitmapStride = (dev->nChunksPerBlock + 7) / 8; /* round up bytes */ ++ dev->chunkBits = YMALLOC(dev->chunkBitmapStride * nBlocks); ++ if(!dev->chunkBits){ ++ dev->chunkBits = YMALLOC_ALT(dev->chunkBitmapStride * nBlocks); ++ dev->chunkBitsAlt = 1; ++ } ++ else ++ dev->chunkBitsAlt = 0; ++ } ++ ++ if (dev->blockInfo && dev->chunkBits) { ++ memset(dev->blockInfo, 0, nBlocks * sizeof(yaffs_BlockInfo)); ++ memset(dev->chunkBits, 0, dev->chunkBitmapStride * nBlocks); ++ return YAFFS_OK; ++ } ++ ++ return YAFFS_FAIL; ++ ++} ++ ++static void yaffs_DeinitialiseBlocks(yaffs_Device * dev) ++{ ++ if(dev->blockInfoAlt && dev->blockInfo) ++ YFREE_ALT(dev->blockInfo); ++ else if(dev->blockInfo) ++ YFREE(dev->blockInfo); ++ ++ dev->blockInfoAlt = 0; ++ ++ dev->blockInfo = NULL; ++ ++ if(dev->chunkBitsAlt && dev->chunkBits) ++ YFREE_ALT(dev->chunkBits); ++ else if(dev->chunkBits) ++ YFREE(dev->chunkBits); ++ dev->chunkBitsAlt = 0; ++ dev->chunkBits = NULL; ++} ++ ++static int yaffs_BlockNotDisqualifiedFromGC(yaffs_Device * dev, ++ yaffs_BlockInfo * bi) ++{ ++ int i; ++ __u32 seq; ++ yaffs_BlockInfo *b; ++ ++ if (!dev->isYaffs2) ++ return 1; /* disqualification only applies to yaffs2. */ ++ ++ if (!bi->hasShrinkHeader) ++ return 1; /* can gc */ ++ ++ /* Find the oldest dirty sequence number if we don't know it and save it ++ * so we don't have to keep recomputing it. ++ */ ++ if (!dev->oldestDirtySequence) { ++ seq = dev->sequenceNumber; ++ ++ for (i = dev->internalStartBlock; i <= dev->internalEndBlock; ++ i++) { ++ b = yaffs_GetBlockInfo(dev, i); ++ if (b->blockState == YAFFS_BLOCK_STATE_FULL && ++ (b->pagesInUse - b->softDeletions) < ++ dev->nChunksPerBlock && b->sequenceNumber < seq) { ++ seq = b->sequenceNumber; ++ } ++ } ++ dev->oldestDirtySequence = seq; ++ } ++ ++ /* Can't do gc of this block if there are any blocks older than this one that have ++ * discarded pages. ++ */ ++ return (bi->sequenceNumber <= dev->oldestDirtySequence); ++ ++} ++ ++/* FindDiretiestBlock is used to select the dirtiest block (or close enough) ++ * for garbage collection. ++ */ ++ ++static int yaffs_FindBlockForGarbageCollection(yaffs_Device * dev, ++ int aggressive) ++{ ++ ++ int b = dev->currentDirtyChecker; ++ ++ int i; ++ int iterations; ++ int dirtiest = -1; ++ int pagesInUse = 0; ++ int prioritised=0; ++ yaffs_BlockInfo *bi; ++ int pendingPrioritisedExist = 0; ++ ++ /* First let's see if we need to grab a prioritised block */ ++ if(dev->hasPendingPrioritisedGCs){ ++ for(i = dev->internalStartBlock; i < dev->internalEndBlock && !prioritised; i++){ ++ ++ bi = yaffs_GetBlockInfo(dev, i); ++ //yaffs_VerifyBlock(dev,bi,i); ++ ++ if(bi->gcPrioritise) { ++ pendingPrioritisedExist = 1; ++ if(bi->blockState == YAFFS_BLOCK_STATE_FULL && ++ yaffs_BlockNotDisqualifiedFromGC(dev, bi)){ ++ pagesInUse = (bi->pagesInUse - bi->softDeletions); ++ dirtiest = i; ++ prioritised = 1; ++ aggressive = 1; /* Fool the non-aggressive skip logiv below */ ++ } ++ } ++ } ++ ++ if(!pendingPrioritisedExist) /* None found, so we can clear this */ ++ dev->hasPendingPrioritisedGCs = 0; ++ } ++ ++ /* If we're doing aggressive GC then we are happy to take a less-dirty block, and ++ * search harder. ++ * else (we're doing a leasurely gc), then we only bother to do this if the ++ * block has only a few pages in use. ++ */ ++ ++ dev->nonAggressiveSkip--; ++ ++ if (!aggressive && (dev->nonAggressiveSkip > 0)) { ++ return -1; ++ } ++ ++ if(!prioritised) ++ pagesInUse = ++ (aggressive) ? dev->nChunksPerBlock : YAFFS_PASSIVE_GC_CHUNKS + 1; ++ ++ if (aggressive) { ++ iterations = ++ dev->internalEndBlock - dev->internalStartBlock + 1; ++ } else { ++ iterations = ++ dev->internalEndBlock - dev->internalStartBlock + 1; ++ iterations = iterations / 16; ++ if (iterations > 200) { ++ iterations = 200; ++ } ++ } ++ ++ for (i = 0; i <= iterations && pagesInUse > 0 && !prioritised; i++) { ++ b++; ++ if (b < dev->internalStartBlock || b > dev->internalEndBlock) { ++ b = dev->internalStartBlock; ++ } ++ ++ if (b < dev->internalStartBlock || b > dev->internalEndBlock) { ++ T(YAFFS_TRACE_ERROR, ++ (TSTR("**>> Block %d is not valid" TENDSTR), b)); ++ YBUG(); ++ } ++ ++ bi = yaffs_GetBlockInfo(dev, b); ++ ++#if 0 ++ if (bi->blockState == YAFFS_BLOCK_STATE_CHECKPOINT) { ++ dirtiest = b; ++ pagesInUse = 0; ++ } ++ else ++#endif ++ ++ if (bi->blockState == YAFFS_BLOCK_STATE_FULL && ++ (bi->pagesInUse - bi->softDeletions) < pagesInUse && ++ yaffs_BlockNotDisqualifiedFromGC(dev, bi)) { ++ dirtiest = b; ++ pagesInUse = (bi->pagesInUse - bi->softDeletions); ++ } ++ } ++ ++ dev->currentDirtyChecker = b; ++ ++ if (dirtiest > 0) { ++ T(YAFFS_TRACE_GC, ++ (TSTR("GC Selected block %d with %d free, prioritised:%d" TENDSTR), dirtiest, ++ dev->nChunksPerBlock - pagesInUse,prioritised)); ++ } ++ ++ dev->oldestDirtySequence = 0; ++ ++ if (dirtiest > 0) { ++ dev->nonAggressiveSkip = 4; ++ } ++ ++ return dirtiest; ++} ++ ++static void yaffs_BlockBecameDirty(yaffs_Device * dev, int blockNo) ++{ ++ yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, blockNo); ++ ++ int erasedOk = 0; ++ ++ /* If the block is still healthy erase it and mark as clean. ++ * If the block has had a data failure, then retire it. ++ */ ++ ++ T(YAFFS_TRACE_GC | YAFFS_TRACE_ERASE, ++ (TSTR("yaffs_BlockBecameDirty block %d state %d %s"TENDSTR), ++ blockNo, bi->blockState, (bi->needsRetiring) ? "needs retiring" : "")); ++ ++ bi->blockState = YAFFS_BLOCK_STATE_DIRTY; ++ ++ if (!bi->needsRetiring) { ++ yaffs_InvalidateCheckpoint(dev); ++ erasedOk = yaffs_EraseBlockInNAND(dev, blockNo); ++ if (!erasedOk) { ++ dev->nErasureFailures++; ++ T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS, ++ (TSTR("**>> Erasure failed %d" TENDSTR), blockNo)); ++ } ++ } ++ ++ if (erasedOk && ++ ((yaffs_traceMask & YAFFS_TRACE_ERASE) || !yaffs_SkipVerification(dev))) { ++ int i; ++ for (i = 0; i < dev->nChunksPerBlock; i++) { ++ if (!yaffs_CheckChunkErased ++ (dev, blockNo * dev->nChunksPerBlock + i)) { ++ T(YAFFS_TRACE_ERROR, ++ (TSTR ++ (">>Block %d erasure supposedly OK, but chunk %d not erased" ++ TENDSTR), blockNo, i)); ++ } ++ } ++ } ++ ++ if (erasedOk) { ++ /* Clean it up... */ ++ bi->blockState = YAFFS_BLOCK_STATE_EMPTY; ++ dev->nErasedBlocks++; ++ bi->pagesInUse = 0; ++ bi->softDeletions = 0; ++ bi->hasShrinkHeader = 0; ++ bi->skipErasedCheck = 1; /* This is clean, so no need to check */ ++ bi->gcPrioritise = 0; ++ yaffs_ClearChunkBits(dev, blockNo); ++ ++ T(YAFFS_TRACE_ERASE, ++ (TSTR("Erased block %d" TENDSTR), blockNo)); ++ } else { ++ dev->nFreeChunks -= dev->nChunksPerBlock; /* We lost a block of free space */ ++ ++ yaffs_RetireBlock(dev, blockNo); ++ T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS, ++ (TSTR("**>> Block %d retired" TENDSTR), blockNo)); ++ } ++} ++ ++static int yaffs_FindBlockForAllocation(yaffs_Device * dev) ++{ ++ int i; ++ ++ yaffs_BlockInfo *bi; ++ ++ if (dev->nErasedBlocks < 1) { ++ /* Hoosterman we've got a problem. ++ * Can't get space to gc ++ */ ++ T(YAFFS_TRACE_ERROR, ++ (TSTR("yaffs tragedy: no more erased blocks" TENDSTR))); ++ ++ return -1; ++ } ++ ++ /* Find an empty block. */ ++ ++ for (i = dev->internalStartBlock; i <= dev->internalEndBlock; i++) { ++ dev->allocationBlockFinder++; ++ if (dev->allocationBlockFinder < dev->internalStartBlock ++ || dev->allocationBlockFinder > dev->internalEndBlock) { ++ dev->allocationBlockFinder = dev->internalStartBlock; ++ } ++ ++ bi = yaffs_GetBlockInfo(dev, dev->allocationBlockFinder); ++ ++ if (bi->blockState == YAFFS_BLOCK_STATE_EMPTY) { ++ bi->blockState = YAFFS_BLOCK_STATE_ALLOCATING; ++ dev->sequenceNumber++; ++ bi->sequenceNumber = dev->sequenceNumber; ++ dev->nErasedBlocks--; ++ T(YAFFS_TRACE_ALLOCATE, ++ (TSTR("Allocated block %d, seq %d, %d left" TENDSTR), ++ dev->allocationBlockFinder, dev->sequenceNumber, ++ dev->nErasedBlocks)); ++ return dev->allocationBlockFinder; ++ } ++ } ++ ++ T(YAFFS_TRACE_ALWAYS, ++ (TSTR ++ ("yaffs tragedy: no more erased blocks, but there should have been %d" ++ TENDSTR), dev->nErasedBlocks)); ++ ++ return -1; ++} ++ ++ ++ ++static int yaffs_CalcCheckpointBlocksRequired(yaffs_Device *dev) ++{ ++ if(!dev->nCheckpointBlocksRequired && ++ dev->isYaffs2){ ++ /* Not a valid value so recalculate */ ++ int nBytes = 0; ++ int nBlocks; ++ int devBlocks = (dev->endBlock - dev->startBlock + 1); ++ int tnodeSize; ++ ++ tnodeSize = (dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8; ++ ++ if(tnodeSize < sizeof(yaffs_Tnode)) ++ tnodeSize = sizeof(yaffs_Tnode); ++ ++ nBytes += sizeof(yaffs_CheckpointValidity); ++ nBytes += sizeof(yaffs_CheckpointDevice); ++ nBytes += devBlocks * sizeof(yaffs_BlockInfo); ++ nBytes += devBlocks * dev->chunkBitmapStride; ++ nBytes += (sizeof(yaffs_CheckpointObject) + sizeof(__u32)) * (dev->nObjectsCreated - dev->nFreeObjects); ++ nBytes += (tnodeSize + sizeof(__u32)) * (dev->nTnodesCreated - dev->nFreeTnodes); ++ nBytes += sizeof(yaffs_CheckpointValidity); ++ nBytes += sizeof(__u32); /* checksum*/ ++ ++ /* Round up and add 2 blocks to allow for some bad blocks, so add 3 */ ++ ++ nBlocks = (nBytes/(dev->nDataBytesPerChunk * dev->nChunksPerBlock)) + 3; ++ ++ dev->nCheckpointBlocksRequired = nBlocks; ++ } ++ ++ return dev->nCheckpointBlocksRequired; ++} ++ ++// Check if there's space to allocate... ++// Thinks.... do we need top make this ths same as yaffs_GetFreeChunks()? ++static int yaffs_CheckSpaceForAllocation(yaffs_Device * dev) ++{ ++ int reservedChunks; ++ int reservedBlocks = dev->nReservedBlocks; ++ int checkpointBlocks; ++ ++ if(dev->isYaffs2){ ++ checkpointBlocks = yaffs_CalcCheckpointBlocksRequired(dev) - ++ dev->blocksInCheckpoint; ++ if(checkpointBlocks < 0) ++ checkpointBlocks = 0; ++ } else { ++ checkpointBlocks =0; ++ } ++ ++ reservedChunks = ((reservedBlocks + checkpointBlocks) * dev->nChunksPerBlock); ++ ++ return (dev->nFreeChunks > reservedChunks); ++} ++ ++static int yaffs_AllocateChunk(yaffs_Device * dev, int useReserve, yaffs_BlockInfo **blockUsedPtr) ++{ ++ int retVal; ++ yaffs_BlockInfo *bi; ++ ++ if (dev->allocationBlock < 0) { ++ /* Get next block to allocate off */ ++ dev->allocationBlock = yaffs_FindBlockForAllocation(dev); ++ dev->allocationPage = 0; ++ } ++ ++ if (!useReserve && !yaffs_CheckSpaceForAllocation(dev)) { ++ /* Not enough space to allocate unless we're allowed to use the reserve. */ ++ return -1; ++ } ++ ++ if (dev->nErasedBlocks < dev->nReservedBlocks ++ && dev->allocationPage == 0) { ++ T(YAFFS_TRACE_ALLOCATE, (TSTR("Allocating reserve" TENDSTR))); ++ } ++ ++ /* Next page please.... */ ++ if (dev->allocationBlock >= 0) { ++ bi = yaffs_GetBlockInfo(dev, dev->allocationBlock); ++ ++ retVal = (dev->allocationBlock * dev->nChunksPerBlock) + ++ dev->allocationPage; ++ bi->pagesInUse++; ++ yaffs_SetChunkBit(dev, dev->allocationBlock, ++ dev->allocationPage); ++ ++ dev->allocationPage++; ++ ++ dev->nFreeChunks--; ++ ++ /* If the block is full set the state to full */ ++ if (dev->allocationPage >= dev->nChunksPerBlock) { ++ bi->blockState = YAFFS_BLOCK_STATE_FULL; ++ dev->allocationBlock = -1; ++ } ++ ++ if(blockUsedPtr) ++ *blockUsedPtr = bi; ++ ++ return retVal; ++ } ++ ++ T(YAFFS_TRACE_ERROR, ++ (TSTR("!!!!!!!!! Allocator out !!!!!!!!!!!!!!!!!" TENDSTR))); ++ ++ return -1; ++} ++ ++static int yaffs_GetErasedChunks(yaffs_Device * dev) ++{ ++ int n; ++ ++ n = dev->nErasedBlocks * dev->nChunksPerBlock; ++ ++ if (dev->allocationBlock > 0) { ++ n += (dev->nChunksPerBlock - dev->allocationPage); ++ } ++ ++ return n; ++ ++} ++ ++static int yaffs_GarbageCollectBlock(yaffs_Device * dev, int block, int wholeBlock) ++{ ++ int oldChunk; ++ int newChunk; ++ int markNAND; ++ int retVal = YAFFS_OK; ++ int cleanups = 0; ++ int i; ++ int isCheckpointBlock; ++ int matchingChunk; ++ int maxCopies; ++ ++ int chunksBefore = yaffs_GetErasedChunks(dev); ++ int chunksAfter; ++ ++ yaffs_ExtendedTags tags; ++ ++ yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, block); ++ ++ yaffs_Object *object; ++ ++ isCheckpointBlock = (bi->blockState == YAFFS_BLOCK_STATE_CHECKPOINT); ++ ++ bi->blockState = YAFFS_BLOCK_STATE_COLLECTING; ++ ++ T(YAFFS_TRACE_TRACING, ++ (TSTR("Collecting block %d, in use %d, shrink %d, wholeBlock %d" TENDSTR), ++ block, ++ bi->pagesInUse, ++ bi->hasShrinkHeader, ++ wholeBlock)); ++ ++ /*yaffs_VerifyFreeChunks(dev); */ ++ ++ bi->hasShrinkHeader = 0; /* clear the flag so that the block can erase */ ++ ++ /* Take off the number of soft deleted entries because ++ * they're going to get really deleted during GC. ++ */ ++ dev->nFreeChunks -= bi->softDeletions; ++ ++ dev->isDoingGC = 1; ++ ++ if (isCheckpointBlock || ++ !yaffs_StillSomeChunkBits(dev, block)) { ++ T(YAFFS_TRACE_TRACING, ++ (TSTR ++ ("Collecting block %d that has no chunks in use" TENDSTR), ++ block)); ++ yaffs_BlockBecameDirty(dev, block); ++ } else { ++ ++ __u8 *buffer = yaffs_GetTempBuffer(dev, __LINE__); ++ ++ yaffs_VerifyBlock(dev,bi,block); ++ ++ maxCopies = (wholeBlock) ? dev->nChunksPerBlock : 10; ++ oldChunk = block * dev->nChunksPerBlock + dev->gcChunk; ++ ++ for ( /* init already done */; ++ retVal == YAFFS_OK && ++ dev->gcChunk < dev->nChunksPerBlock && ++ (bi->blockState == YAFFS_BLOCK_STATE_COLLECTING)&& ++ maxCopies > 0; ++ dev->gcChunk++, oldChunk++) { ++ if (yaffs_CheckChunkBit(dev, block, dev->gcChunk)) { ++ ++ /* This page is in use and might need to be copied off */ ++ ++ maxCopies--; ++ ++ markNAND = 1; ++ ++ yaffs_InitialiseTags(&tags); ++ ++ yaffs_ReadChunkWithTagsFromNAND(dev, oldChunk, ++ buffer, &tags); ++ ++ object = ++ yaffs_FindObjectByNumber(dev, ++ tags.objectId); ++ ++ T(YAFFS_TRACE_GC_DETAIL, ++ (TSTR ++ ("Collecting chunk in block %d, %d %d %d " TENDSTR), ++ dev->gcChunk, tags.objectId, tags.chunkId, ++ tags.byteCount)); ++ ++ if(object && !yaffs_SkipVerification(dev)){ ++ if(tags.chunkId == 0) ++ matchingChunk = object->hdrChunk; ++ else if(object->softDeleted) ++ matchingChunk = oldChunk; /* Defeat the test */ ++ else ++ matchingChunk = yaffs_FindChunkInFile(object,tags.chunkId,NULL); ++ ++ if(oldChunk != matchingChunk) ++ T(YAFFS_TRACE_ERROR, ++ (TSTR("gc: page in gc mismatch: %d %d %d %d"TENDSTR), ++ oldChunk,matchingChunk,tags.objectId, tags.chunkId)); ++ ++ } ++ ++ if (!object) { ++ T(YAFFS_TRACE_ERROR, ++ (TSTR ++ ("page %d in gc has no object: %d %d %d " ++ TENDSTR), oldChunk, ++ tags.objectId, tags.chunkId, tags.byteCount)); ++ } ++ ++ if (object && ++ object->deleted && ++ object->softDeleted && ++ tags.chunkId != 0) { ++ /* Data chunk in a soft deleted file, throw it away ++ * It's a soft deleted data chunk, ++ * No need to copy this, just forget about it and ++ * fix up the object. ++ */ ++ ++ object->nDataChunks--; ++ ++ if (object->nDataChunks <= 0) { ++ /* remeber to clean up the object */ ++ dev->gcCleanupList[cleanups] = ++ tags.objectId; ++ cleanups++; ++ } ++ markNAND = 0; ++ } else if (0 ++ /* Todo object && object->deleted && object->nDataChunks == 0 */ ++ ) { ++ /* Deleted object header with no data chunks. ++ * Can be discarded and the file deleted. ++ */ ++ object->hdrChunk = 0; ++ yaffs_FreeTnode(object->myDev, ++ object->variant. ++ fileVariant.top); ++ object->variant.fileVariant.top = NULL; ++ yaffs_DoGenericObjectDeletion(object); ++ ++ } else if (object) { ++ /* It's either a data chunk in a live file or ++ * an ObjectHeader, so we're interested in it. ++ * NB Need to keep the ObjectHeaders of deleted files ++ * until the whole file has been deleted off ++ */ ++ tags.serialNumber++; ++ ++ dev->nGCCopies++; ++ ++ if (tags.chunkId == 0) { ++ /* It is an object Id, ++ * We need to nuke the shrinkheader flags first ++ * We no longer want the shrinkHeader flag since its work is done ++ * and if it is left in place it will mess up scanning. ++ */ ++ ++ yaffs_ObjectHeader *oh; ++ oh = (yaffs_ObjectHeader *)buffer; ++ oh->isShrink = 0; ++ tags.extraIsShrinkHeader = 0; ++ ++ yaffs_VerifyObjectHeader(object,oh,&tags,1); ++ } ++ ++ newChunk = ++ yaffs_WriteNewChunkWithTagsToNAND(dev, buffer, &tags, 1); ++ ++ if (newChunk < 0) { ++ retVal = YAFFS_FAIL; ++ } else { ++ ++ /* Ok, now fix up the Tnodes etc. */ ++ ++ if (tags.chunkId == 0) { ++ /* It's a header */ ++ object->hdrChunk = newChunk; ++ object->serial = tags.serialNumber; ++ } else { ++ /* It's a data chunk */ ++ yaffs_PutChunkIntoFile ++ (object, ++ tags.chunkId, ++ newChunk, 0); ++ } ++ } ++ } ++ ++ if(retVal == YAFFS_OK) ++ yaffs_DeleteChunk(dev, oldChunk, markNAND, __LINE__); ++ ++ } ++ } ++ ++ yaffs_ReleaseTempBuffer(dev, buffer, __LINE__); ++ ++ ++ /* Do any required cleanups */ ++ for (i = 0; i < cleanups; i++) { ++ /* Time to delete the file too */ ++ object = ++ yaffs_FindObjectByNumber(dev, ++ dev->gcCleanupList[i]); ++ if (object) { ++ yaffs_FreeTnode(dev, ++ object->variant.fileVariant. ++ top); ++ object->variant.fileVariant.top = NULL; ++ T(YAFFS_TRACE_GC, ++ (TSTR ++ ("yaffs: About to finally delete object %d" ++ TENDSTR), object->objectId)); ++ yaffs_DoGenericObjectDeletion(object); ++ object->myDev->nDeletedFiles--; ++ } ++ ++ } ++ ++ } ++ ++ yaffs_VerifyCollectedBlock(dev,bi,block); ++ ++ if (chunksBefore >= (chunksAfter = yaffs_GetErasedChunks(dev))) { ++ T(YAFFS_TRACE_GC, ++ (TSTR ++ ("gc did not increase free chunks before %d after %d" ++ TENDSTR), chunksBefore, chunksAfter)); ++ } ++ ++ /* If the gc completed then clear the current gcBlock so that we find another. */ ++ if(bi->blockState != YAFFS_BLOCK_STATE_COLLECTING){ ++ dev->gcBlock = -1; ++ dev->gcChunk = 0; ++ } ++ ++ dev->isDoingGC = 0; ++ ++ return retVal; ++} ++ ++/* New garbage collector ++ * If we're very low on erased blocks then we do aggressive garbage collection ++ * otherwise we do "leasurely" garbage collection. ++ * Aggressive gc looks further (whole array) and will accept less dirty blocks. ++ * Passive gc only inspects smaller areas and will only accept more dirty blocks. ++ * ++ * The idea is to help clear out space in a more spread-out manner. ++ * Dunno if it really does anything useful. ++ */ ++static int yaffs_CheckGarbageCollection(yaffs_Device * dev) ++{ ++ int block; ++ int aggressive; ++ int gcOk = YAFFS_OK; ++ int maxTries = 0; ++ ++ int checkpointBlockAdjust; ++ ++ if (dev->isDoingGC) { ++ /* Bail out so we don't get recursive gc */ ++ return YAFFS_OK; ++ } ++ ++ /* This loop should pass the first time. ++ * We'll only see looping here if the erase of the collected block fails. ++ */ ++ ++ do { ++ maxTries++; ++ ++ checkpointBlockAdjust = yaffs_CalcCheckpointBlocksRequired(dev) - dev->blocksInCheckpoint; ++ if(checkpointBlockAdjust < 0) ++ checkpointBlockAdjust = 0; ++ ++ if (dev->nErasedBlocks < (dev->nReservedBlocks + checkpointBlockAdjust + 2)) { ++ /* We need a block soon...*/ ++ aggressive = 1; ++ } else { ++ /* We're in no hurry */ ++ aggressive = 0; ++ } ++ ++ if(dev->gcBlock <= 0){ ++ dev->gcBlock = yaffs_FindBlockForGarbageCollection(dev, aggressive); ++ dev->gcChunk = 0; ++ } ++ ++ block = dev->gcBlock; ++ ++ if (block > 0) { ++ dev->garbageCollections++; ++ if (!aggressive) { ++ dev->passiveGarbageCollections++; ++ } ++ ++ T(YAFFS_TRACE_GC, ++ (TSTR ++ ("yaffs: GC erasedBlocks %d aggressive %d" TENDSTR), ++ dev->nErasedBlocks, aggressive)); ++ ++ gcOk = yaffs_GarbageCollectBlock(dev,block,aggressive); ++ } ++ ++ if (dev->nErasedBlocks < (dev->nReservedBlocks) && block > 0) { ++ T(YAFFS_TRACE_GC, ++ (TSTR ++ ("yaffs: GC !!!no reclaim!!! erasedBlocks %d after try %d block %d" ++ TENDSTR), dev->nErasedBlocks, maxTries, block)); ++ } ++ } while ((dev->nErasedBlocks < dev->nReservedBlocks) && ++ (block > 0) && ++ (maxTries < 2)); ++ ++ return aggressive ? gcOk : YAFFS_OK; ++} ++ ++/*------------------------- TAGS --------------------------------*/ ++ ++static int yaffs_TagsMatch(const yaffs_ExtendedTags * tags, int objectId, ++ int chunkInObject) ++{ ++ return (tags->chunkId == chunkInObject && ++ tags->objectId == objectId && !tags->chunkDeleted) ? 1 : 0; ++ ++} ++ ++ ++/*-------------------- Data file manipulation -----------------*/ ++ ++static int yaffs_FindChunkInFile(yaffs_Object * in, int chunkInInode, ++ yaffs_ExtendedTags * tags) ++{ ++ /*Get the Tnode, then get the level 0 offset chunk offset */ ++ yaffs_Tnode *tn; ++ int theChunk = -1; ++ yaffs_ExtendedTags localTags; ++ int retVal = -1; ++ ++ yaffs_Device *dev = in->myDev; ++ ++ if (!tags) { ++ /* Passed a NULL, so use our own tags space */ ++ tags = &localTags; ++ } ++ ++ tn = yaffs_FindLevel0Tnode(dev, &in->variant.fileVariant, chunkInInode); ++ ++ if (tn) { ++ theChunk = yaffs_GetChunkGroupBase(dev,tn,chunkInInode); ++ ++ retVal = ++ yaffs_FindChunkInGroup(dev, theChunk, tags, in->objectId, ++ chunkInInode); ++ } ++ return retVal; ++} ++ ++static int yaffs_FindAndDeleteChunkInFile(yaffs_Object * in, int chunkInInode, ++ yaffs_ExtendedTags * tags) ++{ ++ /* Get the Tnode, then get the level 0 offset chunk offset */ ++ yaffs_Tnode *tn; ++ int theChunk = -1; ++ yaffs_ExtendedTags localTags; ++ ++ yaffs_Device *dev = in->myDev; ++ int retVal = -1; ++ ++ if (!tags) { ++ /* Passed a NULL, so use our own tags space */ ++ tags = &localTags; ++ } ++ ++ tn = yaffs_FindLevel0Tnode(dev, &in->variant.fileVariant, chunkInInode); ++ ++ if (tn) { ++ ++ theChunk = yaffs_GetChunkGroupBase(dev,tn,chunkInInode); ++ ++ retVal = ++ yaffs_FindChunkInGroup(dev, theChunk, tags, in->objectId, ++ chunkInInode); ++ ++ /* Delete the entry in the filestructure (if found) */ ++ if (retVal != -1) { ++ yaffs_PutLevel0Tnode(dev,tn,chunkInInode,0); ++ } ++ } else { ++ /*T(("No level 0 found for %d\n", chunkInInode)); */ ++ } ++ ++ if (retVal == -1) { ++ /* T(("Could not find %d to delete\n",chunkInInode)); */ ++ } ++ return retVal; ++} ++ ++#ifdef YAFFS_PARANOID ++ ++static int yaffs_CheckFileSanity(yaffs_Object * in) ++{ ++ int chunk; ++ int nChunks; ++ int fSize; ++ int failed = 0; ++ int objId; ++ yaffs_Tnode *tn; ++ yaffs_Tags localTags; ++ yaffs_Tags *tags = &localTags; ++ int theChunk; ++ int chunkDeleted; ++ ++ if (in->variantType != YAFFS_OBJECT_TYPE_FILE) { ++ /* T(("Object not a file\n")); */ ++ return YAFFS_FAIL; ++ } ++ ++ objId = in->objectId; ++ fSize = in->variant.fileVariant.fileSize; ++ nChunks = ++ (fSize + in->myDev->nDataBytesPerChunk - 1) / in->myDev->nDataBytesPerChunk; ++ ++ for (chunk = 1; chunk <= nChunks; chunk++) { ++ tn = yaffs_FindLevel0Tnode(in->myDev, &in->variant.fileVariant, ++ chunk); ++ ++ if (tn) { ++ ++ theChunk = yaffs_GetChunkGroupBase(dev,tn,chunk); ++ ++ if (yaffs_CheckChunkBits ++ (dev, theChunk / dev->nChunksPerBlock, ++ theChunk % dev->nChunksPerBlock)) { ++ ++ yaffs_ReadChunkTagsFromNAND(in->myDev, theChunk, ++ tags, ++ &chunkDeleted); ++ if (yaffs_TagsMatch ++ (tags, in->objectId, chunk, chunkDeleted)) { ++ /* found it; */ ++ ++ } ++ } else { ++ ++ failed = 1; ++ } ++ ++ } else { ++ /* T(("No level 0 found for %d\n", chunk)); */ ++ } ++ } ++ ++ return failed ? YAFFS_FAIL : YAFFS_OK; ++} ++ ++#endif ++ ++static int yaffs_PutChunkIntoFile(yaffs_Object * in, int chunkInInode, ++ int chunkInNAND, int inScan) ++{ ++ /* NB inScan is zero unless scanning. ++ * For forward scanning, inScan is > 0; ++ * for backward scanning inScan is < 0 ++ */ ++ ++ yaffs_Tnode *tn; ++ yaffs_Device *dev = in->myDev; ++ int existingChunk; ++ yaffs_ExtendedTags existingTags; ++ yaffs_ExtendedTags newTags; ++ unsigned existingSerial, newSerial; ++ ++ if (in->variantType != YAFFS_OBJECT_TYPE_FILE) { ++ /* Just ignore an attempt at putting a chunk into a non-file during scanning ++ * If it is not during Scanning then something went wrong! ++ */ ++ if (!inScan) { ++ T(YAFFS_TRACE_ERROR, ++ (TSTR ++ ("yaffs tragedy:attempt to put data chunk into a non-file" ++ TENDSTR))); ++ YBUG(); ++ } ++ ++ yaffs_DeleteChunk(dev, chunkInNAND, 1, __LINE__); ++ return YAFFS_OK; ++ } ++ ++ tn = yaffs_AddOrFindLevel0Tnode(dev, ++ &in->variant.fileVariant, ++ chunkInInode, ++ NULL); ++ if (!tn) { ++ return YAFFS_FAIL; ++ } ++ ++ existingChunk = yaffs_GetChunkGroupBase(dev,tn,chunkInInode); ++ ++ if (inScan != 0) { ++ /* If we're scanning then we need to test for duplicates ++ * NB This does not need to be efficient since it should only ever ++ * happen when the power fails during a write, then only one ++ * chunk should ever be affected. ++ * ++ * Correction for YAFFS2: This could happen quite a lot and we need to think about efficiency! TODO ++ * Update: For backward scanning we don't need to re-read tags so this is quite cheap. ++ */ ++ ++ if (existingChunk > 0) { ++ /* NB Right now existing chunk will not be real chunkId if the device >= 32MB ++ * thus we have to do a FindChunkInFile to get the real chunk id. ++ * ++ * We have a duplicate now we need to decide which one to use: ++ * ++ * Backwards scanning YAFFS2: The old one is what we use, dump the new one. ++ * Forward scanning YAFFS2: The new one is what we use, dump the old one. ++ * YAFFS1: Get both sets of tags and compare serial numbers. ++ */ ++ ++ if (inScan > 0) { ++ /* Only do this for forward scanning */ ++ yaffs_ReadChunkWithTagsFromNAND(dev, ++ chunkInNAND, ++ NULL, &newTags); ++ ++ /* Do a proper find */ ++ existingChunk = ++ yaffs_FindChunkInFile(in, chunkInInode, ++ &existingTags); ++ } ++ ++ if (existingChunk <= 0) { ++ /*Hoosterman - how did this happen? */ ++ ++ T(YAFFS_TRACE_ERROR, ++ (TSTR ++ ("yaffs tragedy: existing chunk < 0 in scan" ++ TENDSTR))); ++ ++ } ++ ++ /* NB The deleted flags should be false, otherwise the chunks will ++ * not be loaded during a scan ++ */ ++ ++ if(inScan > 0) { ++ newSerial = newTags.serialNumber; ++ existingSerial = existingTags.serialNumber; ++ } ++ ++ if ((inScan > 0) && ++ (in->myDev->isYaffs2 || ++ existingChunk <= 0 || ++ ((existingSerial + 1) & 3) == newSerial)) { ++ /* Forward scanning. ++ * Use new ++ * Delete the old one and drop through to update the tnode ++ */ ++ yaffs_DeleteChunk(dev, existingChunk, 1, ++ __LINE__); ++ } else { ++ /* Backward scanning or we want to use the existing one ++ * Use existing. ++ * Delete the new one and return early so that the tnode isn't changed ++ */ ++ yaffs_DeleteChunk(dev, chunkInNAND, 1, ++ __LINE__); ++ return YAFFS_OK; ++ } ++ } ++ ++ } ++ ++ if (existingChunk == 0) { ++ in->nDataChunks++; ++ } ++ ++ yaffs_PutLevel0Tnode(dev,tn,chunkInInode,chunkInNAND); ++ ++ return YAFFS_OK; ++} ++ ++static int yaffs_ReadChunkDataFromObject(yaffs_Object * in, int chunkInInode, ++ __u8 * buffer) ++{ ++ int chunkInNAND = yaffs_FindChunkInFile(in, chunkInInode, NULL); ++ ++ if (chunkInNAND >= 0) { ++ return yaffs_ReadChunkWithTagsFromNAND(in->myDev, chunkInNAND, ++ buffer,NULL); ++ } else { ++ T(YAFFS_TRACE_NANDACCESS, ++ (TSTR("Chunk %d not found zero instead" TENDSTR), ++ chunkInNAND)); ++ /* get sane (zero) data if you read a hole */ ++ memset(buffer, 0, in->myDev->nDataBytesPerChunk); ++ return 0; ++ } ++ ++} ++ ++void yaffs_DeleteChunk(yaffs_Device * dev, int chunkId, int markNAND, int lyn) ++{ ++ int block; ++ int page; ++ yaffs_ExtendedTags tags; ++ yaffs_BlockInfo *bi; ++ ++ if (chunkId <= 0) ++ return; ++ ++ ++ dev->nDeletions++; ++ block = chunkId / dev->nChunksPerBlock; ++ page = chunkId % dev->nChunksPerBlock; ++ ++ ++ if(!yaffs_CheckChunkBit(dev,block,page)) ++ T(YAFFS_TRACE_VERIFY, ++ (TSTR("Deleting invalid chunk %d"TENDSTR), ++ chunkId)); ++ ++ bi = yaffs_GetBlockInfo(dev, block); ++ ++ T(YAFFS_TRACE_DELETION, ++ (TSTR("line %d delete of chunk %d" TENDSTR), lyn, chunkId)); ++ ++ if (markNAND && ++ bi->blockState != YAFFS_BLOCK_STATE_COLLECTING && !dev->isYaffs2) { ++ ++ yaffs_InitialiseTags(&tags); ++ ++ tags.chunkDeleted = 1; ++ ++ yaffs_WriteChunkWithTagsToNAND(dev, chunkId, NULL, &tags); ++ yaffs_HandleUpdateChunk(dev, chunkId, &tags); ++ } else { ++ dev->nUnmarkedDeletions++; ++ } ++ ++ /* Pull out of the management area. ++ * If the whole block became dirty, this will kick off an erasure. ++ */ ++ if (bi->blockState == YAFFS_BLOCK_STATE_ALLOCATING || ++ bi->blockState == YAFFS_BLOCK_STATE_FULL || ++ bi->blockState == YAFFS_BLOCK_STATE_NEEDS_SCANNING || ++ bi->blockState == YAFFS_BLOCK_STATE_COLLECTING) { ++ dev->nFreeChunks++; ++ ++ yaffs_ClearChunkBit(dev, block, page); ++ ++ bi->pagesInUse--; ++ ++ if (bi->pagesInUse == 0 && ++ !bi->hasShrinkHeader && ++ bi->blockState != YAFFS_BLOCK_STATE_ALLOCATING && ++ bi->blockState != YAFFS_BLOCK_STATE_NEEDS_SCANNING) { ++ yaffs_BlockBecameDirty(dev, block); ++ } ++ ++ } else { ++ /* T(("Bad news deleting chunk %d\n",chunkId)); */ ++ } ++ ++} ++ ++static int yaffs_WriteChunkDataToObject(yaffs_Object * in, int chunkInInode, ++ const __u8 * buffer, int nBytes, ++ int useReserve) ++{ ++ /* Find old chunk Need to do this to get serial number ++ * Write new one and patch into tree. ++ * Invalidate old tags. ++ */ ++ ++ int prevChunkId; ++ yaffs_ExtendedTags prevTags; ++ ++ int newChunkId; ++ yaffs_ExtendedTags newTags; ++ ++ yaffs_Device *dev = in->myDev; ++ ++ yaffs_CheckGarbageCollection(dev); ++ ++ /* Get the previous chunk at this location in the file if it exists */ ++ prevChunkId = yaffs_FindChunkInFile(in, chunkInInode, &prevTags); ++ ++ /* Set up new tags */ ++ yaffs_InitialiseTags(&newTags); ++ ++ newTags.chunkId = chunkInInode; ++ newTags.objectId = in->objectId; ++ newTags.serialNumber = ++ (prevChunkId >= 0) ? prevTags.serialNumber + 1 : 1; ++ newTags.byteCount = nBytes; ++ ++ if(nBytes < 1 || nBytes > dev->totalBytesPerChunk){ ++ T(YAFFS_TRACE_ERROR, ++ (TSTR("Writing %d bytes to chunk!!!!!!!!!" TENDSTR), nBytes)); ++ YBUG(); ++ } ++ ++ ++ ++ newChunkId = ++ yaffs_WriteNewChunkWithTagsToNAND(dev, buffer, &newTags, ++ useReserve); ++ ++ if (newChunkId >= 0) { ++ yaffs_PutChunkIntoFile(in, chunkInInode, newChunkId, 0); ++ ++ if (prevChunkId >= 0) { ++ yaffs_DeleteChunk(dev, prevChunkId, 1, __LINE__); ++ ++ } ++ ++ yaffs_CheckFileSanity(in); ++ } ++ return newChunkId; ++ ++} ++ ++/* UpdateObjectHeader updates the header on NAND for an object. ++ * If name is not NULL, then that new name is used. ++ */ ++int yaffs_UpdateObjectHeader(yaffs_Object * in, const YCHAR * name, int force, ++ int isShrink, int shadows) ++{ ++ ++ yaffs_BlockInfo *bi; ++ ++ yaffs_Device *dev = in->myDev; ++ ++ int prevChunkId; ++ int retVal = 0; ++ int result = 0; ++ ++ int newChunkId; ++ yaffs_ExtendedTags newTags; ++ yaffs_ExtendedTags oldTags; ++ ++ __u8 *buffer = NULL; ++ YCHAR oldName[YAFFS_MAX_NAME_LENGTH + 1]; ++ ++ yaffs_ObjectHeader *oh = NULL; ++ ++ yaffs_strcpy(oldName,_Y("silly old name")); ++ ++ ++ if (!in->fake || ++ in == dev->rootDir || /* The rootDir should also be saved */ ++ force) { ++ ++ yaffs_CheckGarbageCollection(dev); ++ yaffs_CheckObjectDetailsLoaded(in); ++ ++ buffer = yaffs_GetTempBuffer(in->myDev, __LINE__); ++ oh = (yaffs_ObjectHeader *) buffer; ++ ++ prevChunkId = in->hdrChunk; ++ ++ if (prevChunkId > 0) { ++ result = yaffs_ReadChunkWithTagsFromNAND(dev, prevChunkId, ++ buffer, &oldTags); ++ ++ yaffs_VerifyObjectHeader(in,oh,&oldTags,0); ++ ++ memcpy(oldName, oh->name, sizeof(oh->name)); ++ } ++ ++ memset(buffer, 0xFF, dev->nDataBytesPerChunk); ++ ++ oh->type = in->variantType; ++ oh->yst_mode = in->yst_mode; ++ oh->shadowsObject = oh->inbandShadowsObject = shadows; ++ ++#ifdef CONFIG_YAFFS_WINCE ++ oh->win_atime[0] = in->win_atime[0]; ++ oh->win_ctime[0] = in->win_ctime[0]; ++ oh->win_mtime[0] = in->win_mtime[0]; ++ oh->win_atime[1] = in->win_atime[1]; ++ oh->win_ctime[1] = in->win_ctime[1]; ++ oh->win_mtime[1] = in->win_mtime[1]; ++#else ++ oh->yst_uid = in->yst_uid; ++ oh->yst_gid = in->yst_gid; ++ oh->yst_atime = in->yst_atime; ++ oh->yst_mtime = in->yst_mtime; ++ oh->yst_ctime = in->yst_ctime; ++ oh->yst_rdev = in->yst_rdev; ++#endif ++ if (in->parent) { ++ oh->parentObjectId = in->parent->objectId; ++ } else { ++ oh->parentObjectId = 0; ++ } ++ ++ if (name && *name) { ++ memset(oh->name, 0, sizeof(oh->name)); ++ yaffs_strncpy(oh->name, name, YAFFS_MAX_NAME_LENGTH); ++ } else if (prevChunkId>=0) { ++ memcpy(oh->name, oldName, sizeof(oh->name)); ++ } else { ++ memset(oh->name, 0, sizeof(oh->name)); ++ } ++ ++ oh->isShrink = isShrink; ++ ++ switch (in->variantType) { ++ case YAFFS_OBJECT_TYPE_UNKNOWN: ++ /* Should not happen */ ++ break; ++ case YAFFS_OBJECT_TYPE_FILE: ++ oh->fileSize = ++ (oh->parentObjectId == YAFFS_OBJECTID_DELETED ++ || oh->parentObjectId == ++ YAFFS_OBJECTID_UNLINKED) ? 0 : in->variant. ++ fileVariant.fileSize; ++ break; ++ case YAFFS_OBJECT_TYPE_HARDLINK: ++ oh->equivalentObjectId = ++ in->variant.hardLinkVariant.equivalentObjectId; ++ break; ++ case YAFFS_OBJECT_TYPE_SPECIAL: ++ /* Do nothing */ ++ break; ++ case YAFFS_OBJECT_TYPE_DIRECTORY: ++ /* Do nothing */ ++ break; ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ yaffs_strncpy(oh->alias, ++ in->variant.symLinkVariant.alias, ++ YAFFS_MAX_ALIAS_LENGTH); ++ oh->alias[YAFFS_MAX_ALIAS_LENGTH] = 0; ++ break; ++ } ++ ++ /* Tags */ ++ yaffs_InitialiseTags(&newTags); ++ in->serial++; ++ newTags.chunkId = 0; ++ newTags.objectId = in->objectId; ++ newTags.serialNumber = in->serial; ++ ++ /* Add extra info for file header */ ++ ++ newTags.extraHeaderInfoAvailable = 1; ++ newTags.extraParentObjectId = oh->parentObjectId; ++ newTags.extraFileLength = oh->fileSize; ++ newTags.extraIsShrinkHeader = oh->isShrink; ++ newTags.extraEquivalentObjectId = oh->equivalentObjectId; ++ newTags.extraShadows = (oh->shadowsObject > 0) ? 1 : 0; ++ newTags.extraObjectType = in->variantType; ++ ++ yaffs_VerifyObjectHeader(in,oh,&newTags,1); ++ ++ /* Create new chunk in NAND */ ++ newChunkId = ++ yaffs_WriteNewChunkWithTagsToNAND(dev, buffer, &newTags, ++ (prevChunkId >= 0) ? 1 : 0); ++ ++ if (newChunkId >= 0) { ++ ++ in->hdrChunk = newChunkId; ++ ++ if (prevChunkId >= 0) { ++ yaffs_DeleteChunk(dev, prevChunkId, 1, ++ __LINE__); ++ } ++ ++ if(!yaffs_ObjectHasCachedWriteData(in)) ++ in->dirty = 0; ++ ++ /* If this was a shrink, then mark the block that the chunk lives on */ ++ if (isShrink) { ++ bi = yaffs_GetBlockInfo(in->myDev, ++ newChunkId /in->myDev-> nChunksPerBlock); ++ bi->hasShrinkHeader = 1; ++ } ++ ++ } ++ ++ retVal = newChunkId; ++ ++ } ++ ++ if (buffer) ++ yaffs_ReleaseTempBuffer(dev, buffer, __LINE__); ++ ++ return retVal; ++} ++ ++/*------------------------ Short Operations Cache ---------------------------------------- ++ * In many situations where there is no high level buffering (eg WinCE) a lot of ++ * reads might be short sequential reads, and a lot of writes may be short ++ * sequential writes. eg. scanning/writing a jpeg file. ++ * In these cases, a short read/write cache can provide a huge perfomance benefit ++ * with dumb-as-a-rock code. ++ * In Linux, the page cache provides read buffering aand the short op cache provides write ++ * buffering. ++ * ++ * There are a limited number (~10) of cache chunks per device so that we don't ++ * need a very intelligent search. ++ */ ++ ++static int yaffs_ObjectHasCachedWriteData(yaffs_Object *obj) ++{ ++ yaffs_Device *dev = obj->myDev; ++ int i; ++ yaffs_ChunkCache *cache; ++ int nCaches = obj->myDev->nShortOpCaches; ++ ++ for(i = 0; i < nCaches; i++){ ++ cache = &dev->srCache[i]; ++ if (cache->object == obj && ++ cache->dirty) ++ return 1; ++ } ++ ++ return 0; ++} ++ ++ ++static void yaffs_FlushFilesChunkCache(yaffs_Object * obj) ++{ ++ yaffs_Device *dev = obj->myDev; ++ int lowest = -99; /* Stop compiler whining. */ ++ int i; ++ yaffs_ChunkCache *cache; ++ int chunkWritten = 0; ++ int nCaches = obj->myDev->nShortOpCaches; ++ ++ if (nCaches > 0) { ++ do { ++ cache = NULL; ++ ++ /* Find the dirty cache for this object with the lowest chunk id. */ ++ for (i = 0; i < nCaches; i++) { ++ if (dev->srCache[i].object == obj && ++ dev->srCache[i].dirty) { ++ if (!cache ++ || dev->srCache[i].chunkId < ++ lowest) { ++ cache = &dev->srCache[i]; ++ lowest = cache->chunkId; ++ } ++ } ++ } ++ ++ if (cache && !cache->locked) { ++ /* Write it out and free it up */ ++ ++ chunkWritten = ++ yaffs_WriteChunkDataToObject(cache->object, ++ cache->chunkId, ++ cache->data, ++ cache->nBytes, ++ 1); ++ cache->dirty = 0; ++ cache->object = NULL; ++ } ++ ++ } while (cache && chunkWritten > 0); ++ ++ if (cache) { ++ /* Hoosterman, disk full while writing cache out. */ ++ T(YAFFS_TRACE_ERROR, ++ (TSTR("yaffs tragedy: no space during cache write" TENDSTR))); ++ ++ } ++ } ++ ++} ++ ++/*yaffs_FlushEntireDeviceCache(dev) ++ * ++ * ++ */ ++ ++void yaffs_FlushEntireDeviceCache(yaffs_Device *dev) ++{ ++ yaffs_Object *obj; ++ int nCaches = dev->nShortOpCaches; ++ int i; ++ ++ /* Find a dirty object in the cache and flush it... ++ * until there are no further dirty objects. ++ */ ++ do { ++ obj = NULL; ++ for( i = 0; i < nCaches && !obj; i++) { ++ if (dev->srCache[i].object && ++ dev->srCache[i].dirty) ++ obj = dev->srCache[i].object; ++ ++ } ++ if(obj) ++ yaffs_FlushFilesChunkCache(obj); ++ ++ } while(obj); ++ ++} ++ ++ ++/* Grab us a cache chunk for use. ++ * First look for an empty one. ++ * Then look for the least recently used non-dirty one. ++ * Then look for the least recently used dirty one...., flush and look again. ++ */ ++static yaffs_ChunkCache *yaffs_GrabChunkCacheWorker(yaffs_Device * dev) ++{ ++ int i; ++ ++ if (dev->nShortOpCaches > 0) { ++ for (i = 0; i < dev->nShortOpCaches; i++) { ++ if (!dev->srCache[i].object) ++ return &dev->srCache[i]; ++ } ++ } ++ ++ return NULL; ++} ++ ++static yaffs_ChunkCache *yaffs_GrabChunkCache(yaffs_Device * dev) ++{ ++ yaffs_ChunkCache *cache; ++ yaffs_Object *theObj; ++ int usage; ++ int i; ++ int pushout; ++ ++ if (dev->nShortOpCaches > 0) { ++ /* Try find a non-dirty one... */ ++ ++ cache = yaffs_GrabChunkCacheWorker(dev); ++ ++ if (!cache) { ++ /* They were all dirty, find the last recently used object and flush ++ * its cache, then find again. ++ * NB what's here is not very accurate, we actually flush the object ++ * the last recently used page. ++ */ ++ ++ /* With locking we can't assume we can use entry zero */ ++ ++ theObj = NULL; ++ usage = -1; ++ cache = NULL; ++ pushout = -1; ++ ++ for (i = 0; i < dev->nShortOpCaches; i++) { ++ if (dev->srCache[i].object && ++ !dev->srCache[i].locked && ++ (dev->srCache[i].lastUse < usage || !cache)) ++ { ++ usage = dev->srCache[i].lastUse; ++ theObj = dev->srCache[i].object; ++ cache = &dev->srCache[i]; ++ pushout = i; ++ } ++ } ++ ++ if (!cache || cache->dirty) { ++ /* Flush and try again */ ++ yaffs_FlushFilesChunkCache(theObj); ++ cache = yaffs_GrabChunkCacheWorker(dev); ++ } ++ ++ } ++ return cache; ++ } else ++ return NULL; ++ ++} ++ ++/* Find a cached chunk */ ++static yaffs_ChunkCache *yaffs_FindChunkCache(const yaffs_Object * obj, ++ int chunkId) ++{ ++ yaffs_Device *dev = obj->myDev; ++ int i; ++ if (dev->nShortOpCaches > 0) { ++ for (i = 0; i < dev->nShortOpCaches; i++) { ++ if (dev->srCache[i].object == obj && ++ dev->srCache[i].chunkId == chunkId) { ++ dev->cacheHits++; ++ ++ return &dev->srCache[i]; ++ } ++ } ++ } ++ return NULL; ++} ++ ++/* Mark the chunk for the least recently used algorithym */ ++static void yaffs_UseChunkCache(yaffs_Device * dev, yaffs_ChunkCache * cache, ++ int isAWrite) ++{ ++ ++ if (dev->nShortOpCaches > 0) { ++ if (dev->srLastUse < 0 || dev->srLastUse > 100000000) { ++ /* Reset the cache usages */ ++ int i; ++ for (i = 1; i < dev->nShortOpCaches; i++) { ++ dev->srCache[i].lastUse = 0; ++ } ++ dev->srLastUse = 0; ++ } ++ ++ dev->srLastUse++; ++ ++ cache->lastUse = dev->srLastUse; ++ ++ if (isAWrite) { ++ cache->dirty = 1; ++ } ++ } ++} ++ ++/* Invalidate a single cache page. ++ * Do this when a whole page gets written, ++ * ie the short cache for this page is no longer valid. ++ */ ++static void yaffs_InvalidateChunkCache(yaffs_Object * object, int chunkId) ++{ ++ if (object->myDev->nShortOpCaches > 0) { ++ yaffs_ChunkCache *cache = yaffs_FindChunkCache(object, chunkId); ++ ++ if (cache) { ++ cache->object = NULL; ++ } ++ } ++} ++ ++/* Invalidate all the cache pages associated with this object ++ * Do this whenever ther file is deleted or resized. ++ */ ++static void yaffs_InvalidateWholeChunkCache(yaffs_Object * in) ++{ ++ int i; ++ yaffs_Device *dev = in->myDev; ++ ++ if (dev->nShortOpCaches > 0) { ++ /* Invalidate it. */ ++ for (i = 0; i < dev->nShortOpCaches; i++) { ++ if (dev->srCache[i].object == in) { ++ dev->srCache[i].object = NULL; ++ } ++ } ++ } ++} ++ ++/*--------------------- Checkpointing --------------------*/ ++ ++ ++static int yaffs_WriteCheckpointValidityMarker(yaffs_Device *dev,int head) ++{ ++ yaffs_CheckpointValidity cp; ++ ++ memset(&cp,0,sizeof(cp)); ++ ++ cp.structType = sizeof(cp); ++ cp.magic = YAFFS_MAGIC; ++ cp.version = YAFFS_CHECKPOINT_VERSION; ++ cp.head = (head) ? 1 : 0; ++ ++ return (yaffs_CheckpointWrite(dev,&cp,sizeof(cp)) == sizeof(cp))? ++ 1 : 0; ++} ++ ++static int yaffs_ReadCheckpointValidityMarker(yaffs_Device *dev, int head) ++{ ++ yaffs_CheckpointValidity cp; ++ int ok; ++ ++ ok = (yaffs_CheckpointRead(dev,&cp,sizeof(cp)) == sizeof(cp)); ++ ++ if(ok) ++ ok = (cp.structType == sizeof(cp)) && ++ (cp.magic == YAFFS_MAGIC) && ++ (cp.version == YAFFS_CHECKPOINT_VERSION) && ++ (cp.head == ((head) ? 1 : 0)); ++ return ok ? 1 : 0; ++} ++ ++static void yaffs_DeviceToCheckpointDevice(yaffs_CheckpointDevice *cp, ++ yaffs_Device *dev) ++{ ++ cp->nErasedBlocks = dev->nErasedBlocks; ++ cp->allocationBlock = dev->allocationBlock; ++ cp->allocationPage = dev->allocationPage; ++ cp->nFreeChunks = dev->nFreeChunks; ++ ++ cp->nDeletedFiles = dev->nDeletedFiles; ++ cp->nUnlinkedFiles = dev->nUnlinkedFiles; ++ cp->nBackgroundDeletions = dev->nBackgroundDeletions; ++ cp->sequenceNumber = dev->sequenceNumber; ++ cp->oldestDirtySequence = dev->oldestDirtySequence; ++ ++} ++ ++static void yaffs_CheckpointDeviceToDevice(yaffs_Device *dev, ++ yaffs_CheckpointDevice *cp) ++{ ++ dev->nErasedBlocks = cp->nErasedBlocks; ++ dev->allocationBlock = cp->allocationBlock; ++ dev->allocationPage = cp->allocationPage; ++ dev->nFreeChunks = cp->nFreeChunks; ++ ++ dev->nDeletedFiles = cp->nDeletedFiles; ++ dev->nUnlinkedFiles = cp->nUnlinkedFiles; ++ dev->nBackgroundDeletions = cp->nBackgroundDeletions; ++ dev->sequenceNumber = cp->sequenceNumber; ++ dev->oldestDirtySequence = cp->oldestDirtySequence; ++} ++ ++ ++static int yaffs_WriteCheckpointDevice(yaffs_Device *dev) ++{ ++ yaffs_CheckpointDevice cp; ++ __u32 nBytes; ++ __u32 nBlocks = (dev->internalEndBlock - dev->internalStartBlock + 1); ++ ++ int ok; ++ ++ /* Write device runtime values*/ ++ yaffs_DeviceToCheckpointDevice(&cp,dev); ++ cp.structType = sizeof(cp); ++ ++ ok = (yaffs_CheckpointWrite(dev,&cp,sizeof(cp)) == sizeof(cp)); ++ ++ /* Write block info */ ++ if(ok) { ++ nBytes = nBlocks * sizeof(yaffs_BlockInfo); ++ ok = (yaffs_CheckpointWrite(dev,dev->blockInfo,nBytes) == nBytes); ++ } ++ ++ /* Write chunk bits */ ++ if(ok) { ++ nBytes = nBlocks * dev->chunkBitmapStride; ++ ok = (yaffs_CheckpointWrite(dev,dev->chunkBits,nBytes) == nBytes); ++ } ++ return ok ? 1 : 0; ++ ++} ++ ++static int yaffs_ReadCheckpointDevice(yaffs_Device *dev) ++{ ++ yaffs_CheckpointDevice cp; ++ __u32 nBytes; ++ __u32 nBlocks = (dev->internalEndBlock - dev->internalStartBlock + 1); ++ ++ int ok; ++ ++ ok = (yaffs_CheckpointRead(dev,&cp,sizeof(cp)) == sizeof(cp)); ++ if(!ok) ++ return 0; ++ ++ if(cp.structType != sizeof(cp)) ++ return 0; ++ ++ ++ yaffs_CheckpointDeviceToDevice(dev,&cp); ++ ++ nBytes = nBlocks * sizeof(yaffs_BlockInfo); ++ ++ ok = (yaffs_CheckpointRead(dev,dev->blockInfo,nBytes) == nBytes); ++ ++ if(!ok) ++ return 0; ++ nBytes = nBlocks * dev->chunkBitmapStride; ++ ++ ok = (yaffs_CheckpointRead(dev,dev->chunkBits,nBytes) == nBytes); ++ ++ return ok ? 1 : 0; ++} ++ ++static void yaffs_ObjectToCheckpointObject(yaffs_CheckpointObject *cp, ++ yaffs_Object *obj) ++{ ++ ++ cp->objectId = obj->objectId; ++ cp->parentId = (obj->parent) ? obj->parent->objectId : 0; ++ cp->hdrChunk = obj->hdrChunk; ++ cp->variantType = obj->variantType; ++ cp->deleted = obj->deleted; ++ cp->softDeleted = obj->softDeleted; ++ cp->unlinked = obj->unlinked; ++ cp->fake = obj->fake; ++ cp->renameAllowed = obj->renameAllowed; ++ cp->unlinkAllowed = obj->unlinkAllowed; ++ cp->serial = obj->serial; ++ cp->nDataChunks = obj->nDataChunks; ++ ++ if(obj->variantType == YAFFS_OBJECT_TYPE_FILE) ++ cp->fileSizeOrEquivalentObjectId = obj->variant.fileVariant.fileSize; ++ else if(obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK) ++ cp->fileSizeOrEquivalentObjectId = obj->variant.hardLinkVariant.equivalentObjectId; ++} ++ ++static int yaffs_CheckpointObjectToObject( yaffs_Object *obj,yaffs_CheckpointObject *cp) ++{ ++ ++ yaffs_Object *parent; ++ ++ if (obj->variantType != cp->variantType) { ++ T(YAFFS_TRACE_ERROR,(TSTR("Checkpoint read object %d type %d " ++ TCONT("chunk %d does not match existing object type %d") ++ TENDSTR), cp->objectId, cp->variantType, cp->hdrChunk, ++ obj->variantType)); ++ return 0; ++ } ++ ++ obj->objectId = cp->objectId; ++ ++ if(cp->parentId) ++ parent = yaffs_FindOrCreateObjectByNumber( ++ obj->myDev, ++ cp->parentId, ++ YAFFS_OBJECT_TYPE_DIRECTORY); ++ else ++ parent = NULL; ++ ++ if(parent) { ++ if (parent->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) { ++ T(YAFFS_TRACE_ALWAYS,(TSTR("Checkpoint read object %d parent %d type %d" ++ TCONT(" chunk %d Parent type, %d, not directory") ++ TENDSTR), ++ cp->objectId,cp->parentId,cp->variantType,cp->hdrChunk,parent->variantType)); ++ return 0; ++ } ++ yaffs_AddObjectToDirectory(parent, obj); ++ } ++ ++ obj->hdrChunk = cp->hdrChunk; ++ obj->variantType = cp->variantType; ++ obj->deleted = cp->deleted; ++ obj->softDeleted = cp->softDeleted; ++ obj->unlinked = cp->unlinked; ++ obj->fake = cp->fake; ++ obj->renameAllowed = cp->renameAllowed; ++ obj->unlinkAllowed = cp->unlinkAllowed; ++ obj->serial = cp->serial; ++ obj->nDataChunks = cp->nDataChunks; ++ ++ if(obj->variantType == YAFFS_OBJECT_TYPE_FILE) ++ obj->variant.fileVariant.fileSize = cp->fileSizeOrEquivalentObjectId; ++ else if(obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK) ++ obj->variant.hardLinkVariant.equivalentObjectId = cp->fileSizeOrEquivalentObjectId; ++ ++ if(obj->hdrChunk > 0) ++ obj->lazyLoaded = 1; ++ return 1; ++} ++ ++ ++ ++static int yaffs_CheckpointTnodeWorker(yaffs_Object * in, yaffs_Tnode * tn, ++ __u32 level, int chunkOffset) ++{ ++ int i; ++ yaffs_Device *dev = in->myDev; ++ int ok = 1; ++ int tnodeSize = (dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8; ++ ++ if(tnodeSize < sizeof(yaffs_Tnode)) ++ tnodeSize = sizeof(yaffs_Tnode); ++ ++ ++ if (tn) { ++ if (level > 0) { ++ ++ for (i = 0; i < YAFFS_NTNODES_INTERNAL && ok; i++){ ++ if (tn->internal[i]) { ++ ok = yaffs_CheckpointTnodeWorker(in, ++ tn->internal[i], ++ level - 1, ++ (chunkOffset<variantType == YAFFS_OBJECT_TYPE_FILE){ ++ ok = yaffs_CheckpointTnodeWorker(obj, ++ obj->variant.fileVariant.top, ++ obj->variant.fileVariant.topLevel, ++ 0); ++ if(ok) ++ ok = (yaffs_CheckpointWrite(obj->myDev,&endMarker,sizeof(endMarker)) == ++ sizeof(endMarker)); ++ } ++ ++ return ok ? 1 : 0; ++} ++ ++static int yaffs_ReadCheckpointTnodes(yaffs_Object *obj) ++{ ++ __u32 baseChunk; ++ int ok = 1; ++ yaffs_Device *dev = obj->myDev; ++ yaffs_FileStructure *fileStructPtr = &obj->variant.fileVariant; ++ yaffs_Tnode *tn; ++ int nread = 0; ++ int tnodeSize = (dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8; ++ ++ if(tnodeSize < sizeof(yaffs_Tnode)) ++ tnodeSize = sizeof(yaffs_Tnode); ++ ++ ok = (yaffs_CheckpointRead(dev,&baseChunk,sizeof(baseChunk)) == sizeof(baseChunk)); ++ ++ while(ok && (~baseChunk)){ ++ nread++; ++ /* Read level 0 tnode */ ++ ++ ++ tn = yaffs_GetTnodeRaw(dev); ++ if(tn) ++ ok = (yaffs_CheckpointRead(dev,tn,tnodeSize) == tnodeSize); ++ else ++ ok = 0; ++ ++ if(tn && ok){ ++ ok = yaffs_AddOrFindLevel0Tnode(dev, ++ fileStructPtr, ++ baseChunk, ++ tn) ? 1 : 0; ++ ++ } ++ ++ if(ok) ++ ok = (yaffs_CheckpointRead(dev,&baseChunk,sizeof(baseChunk)) == sizeof(baseChunk)); ++ ++ } ++ ++ T(YAFFS_TRACE_CHECKPOINT,( ++ TSTR("Checkpoint read tnodes %d records, last %d. ok %d" TENDSTR), ++ nread,baseChunk,ok)); ++ ++ return ok ? 1 : 0; ++} ++ ++ ++static int yaffs_WriteCheckpointObjects(yaffs_Device *dev) ++{ ++ yaffs_Object *obj; ++ yaffs_CheckpointObject cp; ++ int i; ++ int ok = 1; ++ struct ylist_head *lh; ++ ++ ++ /* Iterate through the objects in each hash entry, ++ * dumping them to the checkpointing stream. ++ */ ++ ++ for(i = 0; ok && i < YAFFS_NOBJECT_BUCKETS; i++){ ++ ylist_for_each(lh, &dev->objectBucket[i].list) { ++ if (lh) { ++ obj = ylist_entry(lh, yaffs_Object, hashLink); ++ if (!obj->deferedFree) { ++ yaffs_ObjectToCheckpointObject(&cp,obj); ++ cp.structType = sizeof(cp); ++ ++ T(YAFFS_TRACE_CHECKPOINT,( ++ TSTR("Checkpoint write object %d parent %d type %d chunk %d obj addr %x" TENDSTR), ++ cp.objectId,cp.parentId,cp.variantType,cp.hdrChunk,(unsigned) obj)); ++ ++ ok = (yaffs_CheckpointWrite(dev,&cp,sizeof(cp)) == sizeof(cp)); ++ ++ if(ok && obj->variantType == YAFFS_OBJECT_TYPE_FILE){ ++ ok = yaffs_WriteCheckpointTnodes(obj); ++ } ++ } ++ } ++ } ++ } ++ ++ /* Dump end of list */ ++ memset(&cp,0xFF,sizeof(yaffs_CheckpointObject)); ++ cp.structType = sizeof(cp); ++ ++ if(ok) ++ ok = (yaffs_CheckpointWrite(dev,&cp,sizeof(cp)) == sizeof(cp)); ++ ++ return ok ? 1 : 0; ++} ++ ++static int yaffs_ReadCheckpointObjects(yaffs_Device *dev) ++{ ++ yaffs_Object *obj; ++ yaffs_CheckpointObject cp; ++ int ok = 1; ++ int done = 0; ++ yaffs_Object *hardList = NULL; ++ ++ while(ok && !done) { ++ ok = (yaffs_CheckpointRead(dev,&cp,sizeof(cp)) == sizeof(cp)); ++ if(cp.structType != sizeof(cp)) { ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("struct size %d instead of %d ok %d"TENDSTR), ++ cp.structType,sizeof(cp),ok)); ++ ok = 0; ++ } ++ ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("Checkpoint read object %d parent %d type %d chunk %d " TENDSTR), ++ cp.objectId,cp.parentId,cp.variantType,cp.hdrChunk)); ++ ++ if(ok && cp.objectId == ~0) ++ done = 1; ++ else if(ok){ ++ obj = yaffs_FindOrCreateObjectByNumber(dev,cp.objectId, cp.variantType); ++ if(obj) { ++ ok = yaffs_CheckpointObjectToObject(obj,&cp); ++ if (!ok) ++ break; ++ if(obj->variantType == YAFFS_OBJECT_TYPE_FILE) { ++ ok = yaffs_ReadCheckpointTnodes(obj); ++ } else if(obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK) { ++ obj->hardLinks.next = ++ (struct ylist_head *) ++ hardList; ++ hardList = obj; ++ } ++ ++ } ++ else ++ ok = 0; ++ } ++ } ++ ++ if(ok) ++ yaffs_HardlinkFixup(dev,hardList); ++ ++ return ok ? 1 : 0; ++} ++ ++static int yaffs_WriteCheckpointSum(yaffs_Device *dev) ++{ ++ __u32 checkpointSum; ++ int ok; ++ ++ yaffs_GetCheckpointSum(dev,&checkpointSum); ++ ++ ok = (yaffs_CheckpointWrite(dev,&checkpointSum,sizeof(checkpointSum)) == sizeof(checkpointSum)); ++ ++ if(!ok) ++ return 0; ++ ++ return 1; ++} ++ ++static int yaffs_ReadCheckpointSum(yaffs_Device *dev) ++{ ++ __u32 checkpointSum0; ++ __u32 checkpointSum1; ++ int ok; ++ ++ yaffs_GetCheckpointSum(dev,&checkpointSum0); ++ ++ ok = (yaffs_CheckpointRead(dev,&checkpointSum1,sizeof(checkpointSum1)) == sizeof(checkpointSum1)); ++ ++ if(!ok) ++ return 0; ++ ++ if(checkpointSum0 != checkpointSum1) ++ return 0; ++ ++ return 1; ++} ++ ++ ++static int yaffs_WriteCheckpointData(yaffs_Device *dev) ++{ ++ ++ int ok = 1; ++ ++ if(dev->skipCheckpointWrite || !dev->isYaffs2){ ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("skipping checkpoint write" TENDSTR))); ++ ok = 0; ++ } ++ ++ if(ok) ++ ok = yaffs_CheckpointOpen(dev,1); ++ ++ if(ok){ ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("write checkpoint validity" TENDSTR))); ++ ok = yaffs_WriteCheckpointValidityMarker(dev,1); ++ } ++ if(ok){ ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("write checkpoint device" TENDSTR))); ++ ok = yaffs_WriteCheckpointDevice(dev); ++ } ++ if(ok){ ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("write checkpoint objects" TENDSTR))); ++ ok = yaffs_WriteCheckpointObjects(dev); ++ } ++ if(ok){ ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("write checkpoint validity" TENDSTR))); ++ ok = yaffs_WriteCheckpointValidityMarker(dev,0); ++ } ++ ++ if(ok){ ++ ok = yaffs_WriteCheckpointSum(dev); ++ } ++ ++ ++ if(!yaffs_CheckpointClose(dev)) ++ ok = 0; ++ ++ if(ok) ++ dev->isCheckpointed = 1; ++ else ++ dev->isCheckpointed = 0; ++ ++ return dev->isCheckpointed; ++} ++ ++static int yaffs_ReadCheckpointData(yaffs_Device *dev) ++{ ++ int ok = 1; ++ ++ if(dev->skipCheckpointRead || !dev->isYaffs2){ ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("skipping checkpoint read" TENDSTR))); ++ ok = 0; ++ } ++ ++ if(ok) ++ ok = yaffs_CheckpointOpen(dev,0); /* open for read */ ++ ++ if(ok){ ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("read checkpoint validity" TENDSTR))); ++ ok = yaffs_ReadCheckpointValidityMarker(dev,1); ++ } ++ if(ok){ ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("read checkpoint device" TENDSTR))); ++ ok = yaffs_ReadCheckpointDevice(dev); ++ } ++ if(ok){ ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("read checkpoint objects" TENDSTR))); ++ ok = yaffs_ReadCheckpointObjects(dev); ++ } ++ if(ok){ ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("read checkpoint validity" TENDSTR))); ++ ok = yaffs_ReadCheckpointValidityMarker(dev,0); ++ } ++ ++ if(ok){ ++ ok = yaffs_ReadCheckpointSum(dev); ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("read checkpoint checksum %d" TENDSTR),ok)); ++ } ++ ++ if(!yaffs_CheckpointClose(dev)) ++ ok = 0; ++ ++ if(ok) ++ dev->isCheckpointed = 1; ++ else ++ dev->isCheckpointed = 0; ++ ++ return ok ? 1 : 0; ++ ++} ++ ++static void yaffs_InvalidateCheckpoint(yaffs_Device *dev) ++{ ++ if(dev->isCheckpointed || ++ dev->blocksInCheckpoint > 0){ ++ dev->isCheckpointed = 0; ++ yaffs_CheckpointInvalidateStream(dev); ++ if(dev->superBlock && dev->markSuperBlockDirty) ++ dev->markSuperBlockDirty(dev->superBlock); ++ } ++} ++ ++ ++int yaffs_CheckpointSave(yaffs_Device *dev) ++{ ++ ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("save entry: isCheckpointed %d"TENDSTR),dev->isCheckpointed)); ++ ++ yaffs_VerifyObjects(dev); ++ yaffs_VerifyBlocks(dev); ++ yaffs_VerifyFreeChunks(dev); ++ ++ if(!dev->isCheckpointed) { ++ yaffs_InvalidateCheckpoint(dev); ++ yaffs_WriteCheckpointData(dev); ++ } ++ ++ T(YAFFS_TRACE_ALWAYS,(TSTR("save exit: isCheckpointed %d"TENDSTR),dev->isCheckpointed)); ++ ++ return dev->isCheckpointed; ++} ++ ++int yaffs_CheckpointRestore(yaffs_Device *dev) ++{ ++ int retval; ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("restore entry: isCheckpointed %d"TENDSTR),dev->isCheckpointed)); ++ ++ retval = yaffs_ReadCheckpointData(dev); ++ ++ if(dev->isCheckpointed){ ++ yaffs_VerifyObjects(dev); ++ yaffs_VerifyBlocks(dev); ++ yaffs_VerifyFreeChunks(dev); ++ } ++ ++ T(YAFFS_TRACE_CHECKPOINT,(TSTR("restore exit: isCheckpointed %d"TENDSTR),dev->isCheckpointed)); ++ ++ return retval; ++} ++ ++/*--------------------- File read/write ------------------------ ++ * Read and write have very similar structures. ++ * In general the read/write has three parts to it ++ * An incomplete chunk to start with (if the read/write is not chunk-aligned) ++ * Some complete chunks ++ * An incomplete chunk to end off with ++ * ++ * Curve-balls: the first chunk might also be the last chunk. ++ */ ++ ++int yaffs_ReadDataFromFile(yaffs_Object * in, __u8 * buffer, loff_t offset, ++ int nBytes) ++{ ++ ++ int chunk; ++ __u32 start; ++ int nToCopy; ++ int n = nBytes; ++ int nDone = 0; ++ yaffs_ChunkCache *cache; ++ ++ yaffs_Device *dev; ++ ++ dev = in->myDev; ++ ++ while (n > 0) { ++ //chunk = offset / dev->nDataBytesPerChunk + 1; ++ //start = offset % dev->nDataBytesPerChunk; ++ yaffs_AddrToChunk(dev,offset,&chunk,&start); ++ chunk++; ++ ++ /* OK now check for the curveball where the start and end are in ++ * the same chunk. ++ */ ++ if ((start + n) < dev->nDataBytesPerChunk) { ++ nToCopy = n; ++ } else { ++ nToCopy = dev->nDataBytesPerChunk - start; ++ } ++ ++ cache = yaffs_FindChunkCache(in, chunk); ++ ++ /* If the chunk is already in the cache or it is less than a whole chunk ++ * or we're using inband tags then use the cache (if there is caching) ++ * else bypass the cache. ++ */ ++ if (cache || nToCopy != dev->nDataBytesPerChunk || dev->inbandTags) { ++ if (dev->nShortOpCaches > 0) { ++ ++ /* If we can't find the data in the cache, then load it up. */ ++ ++ if (!cache) { ++ cache = yaffs_GrabChunkCache(in->myDev); ++ cache->object = in; ++ cache->chunkId = chunk; ++ cache->dirty = 0; ++ cache->locked = 0; ++ yaffs_ReadChunkDataFromObject(in, chunk, ++ cache-> ++ data); ++ cache->nBytes = 0; ++ } ++ ++ yaffs_UseChunkCache(dev, cache, 0); ++ ++ cache->locked = 1; ++ ++ ++ memcpy(buffer, &cache->data[start], nToCopy); ++ ++ cache->locked = 0; ++ } else { ++ /* Read into the local buffer then copy..*/ ++ ++ __u8 *localBuffer = ++ yaffs_GetTempBuffer(dev, __LINE__); ++ yaffs_ReadChunkDataFromObject(in, chunk, ++ localBuffer); ++ ++ memcpy(buffer, &localBuffer[start], nToCopy); ++ ++ ++ yaffs_ReleaseTempBuffer(dev, localBuffer, ++ __LINE__); ++ } ++ ++ } else { ++ ++ /* A full chunk. Read directly into the supplied buffer. */ ++ yaffs_ReadChunkDataFromObject(in, chunk, buffer); ++ ++ } ++ ++ n -= nToCopy; ++ offset += nToCopy; ++ buffer += nToCopy; ++ nDone += nToCopy; ++ ++ } ++ ++ return nDone; ++} ++ ++int yaffs_WriteDataToFile(yaffs_Object * in, const __u8 * buffer, loff_t offset, ++ int nBytes, int writeThrough) ++{ ++ ++ int chunk; ++ __u32 start; ++ int nToCopy; ++ int n = nBytes; ++ int nDone = 0; ++ int nToWriteBack; ++ int startOfWrite = offset; ++ int chunkWritten = 0; ++ __u32 nBytesRead; ++ __u32 chunkStart; ++ ++ yaffs_Device *dev; ++ ++ dev = in->myDev; ++ ++ while (n > 0 && chunkWritten >= 0) { ++ //chunk = offset / dev->nDataBytesPerChunk + 1; ++ //start = offset % dev->nDataBytesPerChunk; ++ yaffs_AddrToChunk(dev,offset,&chunk,&start); ++ ++ if(chunk * dev->nDataBytesPerChunk + start != offset || ++ start >= dev->nDataBytesPerChunk){ ++ T(YAFFS_TRACE_ERROR,( ++ TSTR("AddrToChunk of offset %d gives chunk %d start %d" ++ TENDSTR), ++ (int)offset, chunk,start)); ++ } ++ chunk++; ++ ++ /* OK now check for the curveball where the start and end are in ++ * the same chunk. ++ */ ++ ++ if ((start + n) < dev->nDataBytesPerChunk) { ++ nToCopy = n; ++ ++ /* Now folks, to calculate how many bytes to write back.... ++ * If we're overwriting and not writing to then end of file then ++ * we need to write back as much as was there before. ++ */ ++ ++ chunkStart = ((chunk - 1) * dev->nDataBytesPerChunk); ++ ++ if(chunkStart > in->variant.fileVariant.fileSize) ++ nBytesRead = 0; /* Past end of file */ ++ else ++ nBytesRead = in->variant.fileVariant.fileSize - chunkStart; ++ ++ if (nBytesRead > dev->nDataBytesPerChunk) { ++ nBytesRead = dev->nDataBytesPerChunk; ++ } ++ ++ nToWriteBack = ++ (nBytesRead > ++ (start + n)) ? nBytesRead : (start + n); ++ ++ if(nToWriteBack < 0 || nToWriteBack > dev->nDataBytesPerChunk) ++ YBUG(); ++ ++ } else { ++ nToCopy = dev->nDataBytesPerChunk - start; ++ nToWriteBack = dev->nDataBytesPerChunk; ++ } ++ ++ if (nToCopy != dev->nDataBytesPerChunk || dev->inbandTags) { ++ /* An incomplete start or end chunk (or maybe both start and end chunk), ++ * or we're using inband tags, so we want to use the cache buffers. ++ */ ++ if (dev->nShortOpCaches > 0) { ++ yaffs_ChunkCache *cache; ++ /* If we can't find the data in the cache, then load the cache */ ++ cache = yaffs_FindChunkCache(in, chunk); ++ ++ if (!cache ++ && yaffs_CheckSpaceForAllocation(in-> ++ myDev)) { ++ cache = yaffs_GrabChunkCache(in->myDev); ++ cache->object = in; ++ cache->chunkId = chunk; ++ cache->dirty = 0; ++ cache->locked = 0; ++ yaffs_ReadChunkDataFromObject(in, chunk, ++ cache-> ++ data); ++ } ++ else if(cache && ++ !cache->dirty && ++ !yaffs_CheckSpaceForAllocation(in->myDev)){ ++ /* Drop the cache if it was a read cache item and ++ * no space check has been made for it. ++ */ ++ cache = NULL; ++ } ++ ++ if (cache) { ++ yaffs_UseChunkCache(dev, cache, 1); ++ cache->locked = 1; ++ ++ ++ memcpy(&cache->data[start], buffer, ++ nToCopy); ++ ++ ++ cache->locked = 0; ++ cache->nBytes = nToWriteBack; ++ ++ if (writeThrough) { ++ chunkWritten = ++ yaffs_WriteChunkDataToObject ++ (cache->object, ++ cache->chunkId, ++ cache->data, cache->nBytes, ++ 1); ++ cache->dirty = 0; ++ } ++ ++ } else { ++ chunkWritten = -1; /* fail the write */ ++ } ++ } else { ++ /* An incomplete start or end chunk (or maybe both start and end chunk) ++ * Read into the local buffer then copy, then copy over and write back. ++ */ ++ ++ __u8 *localBuffer = ++ yaffs_GetTempBuffer(dev, __LINE__); ++ ++ yaffs_ReadChunkDataFromObject(in, chunk, ++ localBuffer); ++ ++ ++ ++ memcpy(&localBuffer[start], buffer, nToCopy); ++ ++ chunkWritten = ++ yaffs_WriteChunkDataToObject(in, chunk, ++ localBuffer, ++ nToWriteBack, ++ 0); ++ ++ yaffs_ReleaseTempBuffer(dev, localBuffer, ++ __LINE__); ++ ++ } ++ ++ } else { ++ /* A full chunk. Write directly from the supplied buffer. */ ++ ++ ++ ++ chunkWritten = ++ yaffs_WriteChunkDataToObject(in, chunk, buffer, ++ dev->nDataBytesPerChunk, ++ 0); ++ ++ /* Since we've overwritten the cached data, we better invalidate it. */ ++ yaffs_InvalidateChunkCache(in, chunk); ++ } ++ ++ if (chunkWritten >= 0) { ++ n -= nToCopy; ++ offset += nToCopy; ++ buffer += nToCopy; ++ nDone += nToCopy; ++ } ++ ++ } ++ ++ /* Update file object */ ++ ++ if ((startOfWrite + nDone) > in->variant.fileVariant.fileSize) { ++ in->variant.fileVariant.fileSize = (startOfWrite + nDone); ++ } ++ ++ in->dirty = 1; ++ ++ return nDone; ++} ++ ++ ++/* ---------------------- File resizing stuff ------------------ */ ++ ++static void yaffs_PruneResizedChunks(yaffs_Object * in, int newSize) ++{ ++ ++ yaffs_Device *dev = in->myDev; ++ int oldFileSize = in->variant.fileVariant.fileSize; ++ ++ int lastDel = 1 + (oldFileSize - 1) / dev->nDataBytesPerChunk; ++ ++ int startDel = 1 + (newSize + dev->nDataBytesPerChunk - 1) / ++ dev->nDataBytesPerChunk; ++ int i; ++ int chunkId; ++ ++ /* Delete backwards so that we don't end up with holes if ++ * power is lost part-way through the operation. ++ */ ++ for (i = lastDel; i >= startDel; i--) { ++ /* NB this could be optimised somewhat, ++ * eg. could retrieve the tags and write them without ++ * using yaffs_DeleteChunk ++ */ ++ ++ chunkId = yaffs_FindAndDeleteChunkInFile(in, i, NULL); ++ if (chunkId > 0) { ++ if (chunkId < ++ (dev->internalStartBlock * dev->nChunksPerBlock) ++ || chunkId >= ++ ((dev->internalEndBlock + ++ 1) * dev->nChunksPerBlock)) { ++ T(YAFFS_TRACE_ALWAYS, ++ (TSTR("Found daft chunkId %d for %d" TENDSTR), ++ chunkId, i)); ++ } else { ++ in->nDataChunks--; ++ yaffs_DeleteChunk(dev, chunkId, 1, __LINE__); ++ } ++ } ++ } ++ ++} ++ ++int yaffs_ResizeFile(yaffs_Object * in, loff_t newSize) ++{ ++ ++ int oldFileSize = in->variant.fileVariant.fileSize; ++ __u32 newSizeOfPartialChunk; ++ int newFullChunks; ++ ++ yaffs_Device *dev = in->myDev; ++ ++ yaffs_AddrToChunk(dev, newSize, &newFullChunks, &newSizeOfPartialChunk); ++ ++ yaffs_FlushFilesChunkCache(in); ++ yaffs_InvalidateWholeChunkCache(in); ++ ++ yaffs_CheckGarbageCollection(dev); ++ ++ if (in->variantType != YAFFS_OBJECT_TYPE_FILE) { ++ return YAFFS_FAIL; ++ } ++ ++ if (newSize == oldFileSize) { ++ return YAFFS_OK; ++ } ++ ++ if (newSize < oldFileSize) { ++ ++ yaffs_PruneResizedChunks(in, newSize); ++ ++ if (newSizeOfPartialChunk != 0) { ++ int lastChunk = 1 + newFullChunks; ++ ++ __u8 *localBuffer = yaffs_GetTempBuffer(dev, __LINE__); ++ ++ /* Got to read and rewrite the last chunk with its new size and zero pad */ ++ yaffs_ReadChunkDataFromObject(in, lastChunk, ++ localBuffer); ++ ++ memset(localBuffer + newSizeOfPartialChunk, 0, ++ dev->nDataBytesPerChunk - newSizeOfPartialChunk); ++ ++ yaffs_WriteChunkDataToObject(in, lastChunk, localBuffer, ++ newSizeOfPartialChunk, 1); ++ ++ yaffs_ReleaseTempBuffer(dev, localBuffer, __LINE__); ++ } ++ ++ in->variant.fileVariant.fileSize = newSize; ++ ++ yaffs_PruneFileStructure(dev, &in->variant.fileVariant); ++ } else { ++ /* newsSize > oldFileSize */ ++ in->variant.fileVariant.fileSize = newSize; ++ } ++ ++ ++ ++ /* Write a new object header. ++ * show we've shrunk the file, if need be ++ * Do this only if the file is not in the deleted directories. ++ */ ++ if (in->parent && ++ in->parent->objectId != YAFFS_OBJECTID_UNLINKED && ++ in->parent->objectId != YAFFS_OBJECTID_DELETED) { ++ yaffs_UpdateObjectHeader(in, NULL, 0, ++ (newSize < oldFileSize) ? 1 : 0, 0); ++ } ++ ++ return YAFFS_OK; ++} ++ ++loff_t yaffs_GetFileSize(yaffs_Object * obj) ++{ ++ obj = yaffs_GetEquivalentObject(obj); ++ ++ switch (obj->variantType) { ++ case YAFFS_OBJECT_TYPE_FILE: ++ return obj->variant.fileVariant.fileSize; ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ return yaffs_strlen(obj->variant.symLinkVariant.alias); ++ default: ++ return 0; ++ } ++} ++ ++ ++ ++int yaffs_FlushFile(yaffs_Object * in, int updateTime) ++{ ++ int retVal; ++ if (in->dirty) { ++ yaffs_FlushFilesChunkCache(in); ++ if (updateTime) { ++#ifdef CONFIG_YAFFS_WINCE ++ yfsd_WinFileTimeNow(in->win_mtime); ++#else ++ ++ in->yst_mtime = Y_CURRENT_TIME; ++ ++#endif ++ } ++ ++ retVal = ++ (yaffs_UpdateObjectHeader(in, NULL, 0, 0, 0) >= ++ 0) ? YAFFS_OK : YAFFS_FAIL; ++ } else { ++ retVal = YAFFS_OK; ++ } ++ ++ return retVal; ++ ++} ++ ++static int yaffs_DoGenericObjectDeletion(yaffs_Object * in) ++{ ++ ++ /* First off, invalidate the file's data in the cache, without flushing. */ ++ yaffs_InvalidateWholeChunkCache(in); ++ ++ if (in->myDev->isYaffs2 && (in->parent != in->myDev->deletedDir)) { ++ /* Move to the unlinked directory so we have a record that it was deleted. */ ++ yaffs_ChangeObjectName(in, in->myDev->deletedDir,_Y("deleted"), 0, 0); ++ ++ } ++ ++ yaffs_RemoveObjectFromDirectory(in); ++ yaffs_DeleteChunk(in->myDev, in->hdrChunk, 1, __LINE__); ++ in->hdrChunk = 0; ++ ++ yaffs_FreeObject(in); ++ return YAFFS_OK; ++ ++} ++ ++/* yaffs_DeleteFile deletes the whole file data ++ * and the inode associated with the file. ++ * It does not delete the links associated with the file. ++ */ ++static int yaffs_UnlinkFile(yaffs_Object * in) ++{ ++ ++ int retVal; ++ int immediateDeletion = 0; ++ ++#ifdef __KERNEL__ ++ if (!in->myInode) { ++ immediateDeletion = 1; ++ } ++#else ++ if (in->inUse <= 0) { ++ immediateDeletion = 1; ++ } ++#endif ++ ++ if (immediateDeletion) { ++ retVal = ++ yaffs_ChangeObjectName(in, in->myDev->deletedDir, ++ _Y("deleted"), 0, 0); ++ T(YAFFS_TRACE_TRACING, ++ (TSTR("yaffs: immediate deletion of file %d" TENDSTR), ++ in->objectId)); ++ in->deleted = 1; ++ in->myDev->nDeletedFiles++; ++ if (1 || in->myDev->isYaffs2) { ++ yaffs_ResizeFile(in, 0); ++ } ++ yaffs_SoftDeleteFile(in); ++ } else { ++ retVal = ++ yaffs_ChangeObjectName(in, in->myDev->unlinkedDir, ++ _Y("unlinked"), 0, 0); ++ } ++ ++ ++ return retVal; ++} ++ ++int yaffs_DeleteFile(yaffs_Object * in) ++{ ++ int retVal = YAFFS_OK; ++ int deleted = in->deleted; ++ ++ yaffs_ResizeFile(in,0); ++ ++ if (in->nDataChunks > 0) { ++ /* Use soft deletion if there is data in the file. ++ * That won't be the case if it has been resized to zero. ++ */ ++ if (!in->unlinked) { ++ retVal = yaffs_UnlinkFile(in); ++ } ++ if (retVal == YAFFS_OK && in->unlinked && !in->deleted) { ++ in->deleted = deleted = 1; ++ in->myDev->nDeletedFiles++; ++ yaffs_SoftDeleteFile(in); ++ } ++ return deleted ? YAFFS_OK : YAFFS_FAIL; ++ } else { ++ /* The file has no data chunks so we toss it immediately */ ++ yaffs_FreeTnode(in->myDev, in->variant.fileVariant.top); ++ in->variant.fileVariant.top = NULL; ++ yaffs_DoGenericObjectDeletion(in); ++ ++ return YAFFS_OK; ++ } ++} ++ ++static int yaffs_DeleteDirectory(yaffs_Object * in) ++{ ++ /* First check that the directory is empty. */ ++ if (ylist_empty(&in->variant.directoryVariant.children)) { ++ return yaffs_DoGenericObjectDeletion(in); ++ } ++ ++ return YAFFS_FAIL; ++ ++} ++ ++static int yaffs_DeleteSymLink(yaffs_Object * in) ++{ ++ YFREE(in->variant.symLinkVariant.alias); ++ ++ return yaffs_DoGenericObjectDeletion(in); ++} ++ ++static int yaffs_DeleteHardLink(yaffs_Object * in) ++{ ++ /* remove this hardlink from the list assocaited with the equivalent ++ * object ++ */ ++ ylist_del_init(&in->hardLinks); ++ return yaffs_DoGenericObjectDeletion(in); ++} ++ ++static void yaffs_DestroyObject(yaffs_Object * obj) ++{ ++ switch (obj->variantType) { ++ case YAFFS_OBJECT_TYPE_FILE: ++ yaffs_DeleteFile(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_DIRECTORY: ++ yaffs_DeleteDirectory(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ yaffs_DeleteSymLink(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_HARDLINK: ++ yaffs_DeleteHardLink(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_SPECIAL: ++ yaffs_DoGenericObjectDeletion(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_UNKNOWN: ++ break; /* should not happen. */ ++ } ++} ++ ++static int yaffs_UnlinkWorker(yaffs_Object * obj) ++{ ++ ++ if (obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK) { ++ return yaffs_DeleteHardLink(obj); ++ } else if (!ylist_empty(&obj->hardLinks)) { ++ /* Curve ball: We're unlinking an object that has a hardlink. ++ * ++ * This problem arises because we are not strictly following ++ * The Linux link/inode model. ++ * ++ * We can't really delete the object. ++ * Instead, we do the following: ++ * - Select a hardlink. ++ * - Unhook it from the hard links ++ * - Unhook it from its parent directory (so that the rename can work) ++ * - Rename the object to the hardlink's name. ++ * - Delete the hardlink ++ */ ++ ++ yaffs_Object *hl; ++ int retVal; ++ YCHAR name[YAFFS_MAX_NAME_LENGTH + 1]; ++ ++ hl = ylist_entry(obj->hardLinks.next, yaffs_Object, hardLinks); ++ ++ ylist_del_init(&hl->hardLinks); ++ ylist_del_init(&hl->siblings); ++ ++ yaffs_GetObjectName(hl, name, YAFFS_MAX_NAME_LENGTH + 1); ++ ++ retVal = yaffs_ChangeObjectName(obj, hl->parent, name, 0, 0); ++ ++ if (retVal == YAFFS_OK) { ++ retVal = yaffs_DoGenericObjectDeletion(hl); ++ } ++ return retVal; ++ ++ } else { ++ switch (obj->variantType) { ++ case YAFFS_OBJECT_TYPE_FILE: ++ return yaffs_UnlinkFile(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_DIRECTORY: ++ return yaffs_DeleteDirectory(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ return yaffs_DeleteSymLink(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_SPECIAL: ++ return yaffs_DoGenericObjectDeletion(obj); ++ break; ++ case YAFFS_OBJECT_TYPE_HARDLINK: ++ case YAFFS_OBJECT_TYPE_UNKNOWN: ++ default: ++ return YAFFS_FAIL; ++ } ++ } ++} ++ ++ ++static int yaffs_UnlinkObject( yaffs_Object *obj) ++{ ++ ++ if (obj && obj->unlinkAllowed) { ++ return yaffs_UnlinkWorker(obj); ++ } ++ ++ return YAFFS_FAIL; ++ ++} ++int yaffs_Unlink(yaffs_Object * dir, const YCHAR * name) ++{ ++ yaffs_Object *obj; ++ ++ obj = yaffs_FindObjectByName(dir, name); ++ return yaffs_UnlinkObject(obj); ++} ++ ++/*----------------------- Initialisation Scanning ---------------------- */ ++ ++static void yaffs_HandleShadowedObject(yaffs_Device * dev, int objId, ++ int backwardScanning) ++{ ++ yaffs_Object *obj; ++ ++ if (!backwardScanning) { ++ /* Handle YAFFS1 forward scanning case ++ * For YAFFS1 we always do the deletion ++ */ ++ ++ } else { ++ /* Handle YAFFS2 case (backward scanning) ++ * If the shadowed object exists then ignore. ++ */ ++ if (yaffs_FindObjectByNumber(dev, objId)) { ++ return; ++ } ++ } ++ ++ /* Let's create it (if it does not exist) assuming it is a file so that it can do shrinking etc. ++ * We put it in unlinked dir to be cleaned up after the scanning ++ */ ++ obj = ++ yaffs_FindOrCreateObjectByNumber(dev, objId, ++ YAFFS_OBJECT_TYPE_FILE); ++ if (!obj) ++ return; ++ yaffs_AddObjectToDirectory(dev->unlinkedDir, obj); ++ obj->variant.fileVariant.shrinkSize = 0; ++ obj->valid = 1; /* So that we don't read any other info for this file */ ++ ++} ++ ++typedef struct { ++ int seq; ++ int block; ++} yaffs_BlockIndex; ++ ++ ++static void yaffs_HardlinkFixup(yaffs_Device *dev, yaffs_Object *hardList) ++{ ++ yaffs_Object *hl; ++ yaffs_Object *in; ++ ++ while (hardList) { ++ hl = hardList; ++ hardList = (yaffs_Object *) (hardList->hardLinks.next); ++ ++ in = yaffs_FindObjectByNumber(dev, ++ hl->variant.hardLinkVariant. ++ equivalentObjectId); ++ ++ if (in) { ++ /* Add the hardlink pointers */ ++ hl->variant.hardLinkVariant.equivalentObject = in; ++ ylist_add(&hl->hardLinks, &in->hardLinks); ++ } else { ++ /* Todo Need to report/handle this better. ++ * Got a problem... hardlink to a non-existant object ++ */ ++ hl->variant.hardLinkVariant.equivalentObject = NULL; ++ YINIT_LIST_HEAD(&hl->hardLinks); ++ ++ } ++ ++ } ++ ++} ++ ++ ++ ++ ++ ++static int ybicmp(const void *a, const void *b){ ++ register int aseq = ((yaffs_BlockIndex *)a)->seq; ++ register int bseq = ((yaffs_BlockIndex *)b)->seq; ++ register int ablock = ((yaffs_BlockIndex *)a)->block; ++ register int bblock = ((yaffs_BlockIndex *)b)->block; ++ if( aseq == bseq ) ++ return ablock - bblock; ++ else ++ return aseq - bseq; ++ ++} ++ ++ ++struct yaffs_ShadowFixerStruct { ++ int objectId; ++ int shadowedId; ++ struct yaffs_ShadowFixerStruct *next; ++}; ++ ++ ++static void yaffs_StripDeletedObjects(yaffs_Device *dev) ++{ ++ /* ++ * Sort out state of unlinked and deleted objects after scanning. ++ */ ++ struct ylist_head *i; ++ struct ylist_head *n; ++ yaffs_Object *l; ++ ++ /* Soft delete all the unlinked files */ ++ ylist_for_each_safe(i, n, ++ &dev->unlinkedDir->variant.directoryVariant.children) { ++ if (i) { ++ l = ylist_entry(i, yaffs_Object, siblings); ++ yaffs_DestroyObject(l); ++ } ++ } ++ ++ ylist_for_each_safe(i, n, ++ &dev->deletedDir->variant.directoryVariant.children) { ++ if (i) { ++ l = ylist_entry(i, yaffs_Object, siblings); ++ yaffs_DestroyObject(l); ++ } ++ } ++ ++} ++ ++static int yaffs_Scan(yaffs_Device * dev) ++{ ++ yaffs_ExtendedTags tags; ++ int blk; ++ int blockIterator; ++ int startIterator; ++ int endIterator; ++ int result; ++ ++ int chunk; ++ int c; ++ int deleted; ++ yaffs_BlockState state; ++ yaffs_Object *hardList = NULL; ++ yaffs_BlockInfo *bi; ++ __u32 sequenceNumber; ++ yaffs_ObjectHeader *oh; ++ yaffs_Object *in; ++ yaffs_Object *parent; ++ ++ int alloc_failed = 0; ++ ++ struct yaffs_ShadowFixerStruct *shadowFixerList = NULL; ++ ++ ++ __u8 *chunkData; ++ ++ ++ ++ T(YAFFS_TRACE_SCAN, ++ (TSTR("yaffs_Scan starts intstartblk %d intendblk %d..." TENDSTR), ++ dev->internalStartBlock, dev->internalEndBlock)); ++ ++ chunkData = yaffs_GetTempBuffer(dev, __LINE__); ++ ++ dev->sequenceNumber = YAFFS_LOWEST_SEQUENCE_NUMBER; ++ ++ /* Scan all the blocks to determine their state */ ++ for (blk = dev->internalStartBlock; blk <= dev->internalEndBlock; blk++) { ++ bi = yaffs_GetBlockInfo(dev, blk); ++ yaffs_ClearChunkBits(dev, blk); ++ bi->pagesInUse = 0; ++ bi->softDeletions = 0; ++ ++ yaffs_QueryInitialBlockState(dev, blk, &state, &sequenceNumber); ++ ++ bi->blockState = state; ++ bi->sequenceNumber = sequenceNumber; ++ ++ if(bi->sequenceNumber == YAFFS_SEQUENCE_BAD_BLOCK) ++ bi->blockState = state = YAFFS_BLOCK_STATE_DEAD; ++ ++ T(YAFFS_TRACE_SCAN_DEBUG, ++ (TSTR("Block scanning block %d state %d seq %d" TENDSTR), blk, ++ state, sequenceNumber)); ++ ++ if (state == YAFFS_BLOCK_STATE_DEAD) { ++ T(YAFFS_TRACE_BAD_BLOCKS, ++ (TSTR("block %d is bad" TENDSTR), blk)); ++ } else if (state == YAFFS_BLOCK_STATE_EMPTY) { ++ T(YAFFS_TRACE_SCAN_DEBUG, ++ (TSTR("Block empty " TENDSTR))); ++ dev->nErasedBlocks++; ++ dev->nFreeChunks += dev->nChunksPerBlock; ++ } ++ } ++ ++ startIterator = dev->internalStartBlock; ++ endIterator = dev->internalEndBlock; ++ ++ /* For each block.... */ ++ for (blockIterator = startIterator; !alloc_failed && blockIterator <= endIterator; ++ blockIterator++) { ++ ++ YYIELD(); ++ ++ YYIELD(); ++ ++ blk = blockIterator; ++ ++ bi = yaffs_GetBlockInfo(dev, blk); ++ state = bi->blockState; ++ ++ deleted = 0; ++ ++ /* For each chunk in each block that needs scanning....*/ ++ for (c = 0; !alloc_failed && c < dev->nChunksPerBlock && ++ state == YAFFS_BLOCK_STATE_NEEDS_SCANNING; c++) { ++ /* Read the tags and decide what to do */ ++ chunk = blk * dev->nChunksPerBlock + c; ++ ++ result = yaffs_ReadChunkWithTagsFromNAND(dev, chunk, NULL, ++ &tags); ++ ++ /* Let's have a good look at this chunk... */ ++ ++ if (tags.eccResult == YAFFS_ECC_RESULT_UNFIXED || tags.chunkDeleted) { ++ /* YAFFS1 only... ++ * A deleted chunk ++ */ ++ deleted++; ++ dev->nFreeChunks++; ++ /*T((" %d %d deleted\n",blk,c)); */ ++ } else if (!tags.chunkUsed) { ++ /* An unassigned chunk in the block ++ * This means that either the block is empty or ++ * this is the one being allocated from ++ */ ++ ++ if (c == 0) { ++ /* We're looking at the first chunk in the block so the block is unused */ ++ state = YAFFS_BLOCK_STATE_EMPTY; ++ dev->nErasedBlocks++; ++ } else { ++ /* this is the block being allocated from */ ++ T(YAFFS_TRACE_SCAN, ++ (TSTR ++ (" Allocating from %d %d" TENDSTR), ++ blk, c)); ++ state = YAFFS_BLOCK_STATE_ALLOCATING; ++ dev->allocationBlock = blk; ++ dev->allocationPage = c; ++ dev->allocationBlockFinder = blk; ++ /* Set it to here to encourage the allocator to go forth from here. */ ++ ++ } ++ ++ dev->nFreeChunks += (dev->nChunksPerBlock - c); ++ } else if (tags.chunkId > 0) { ++ /* chunkId > 0 so it is a data chunk... */ ++ unsigned int endpos; ++ ++ yaffs_SetChunkBit(dev, blk, c); ++ bi->pagesInUse++; ++ ++ in = yaffs_FindOrCreateObjectByNumber(dev, ++ tags. ++ objectId, ++ YAFFS_OBJECT_TYPE_FILE); ++ /* PutChunkIntoFile checks for a clash (two data chunks with ++ * the same chunkId). ++ */ ++ ++ if(!in) ++ alloc_failed = 1; ++ ++ if(in){ ++ if(!yaffs_PutChunkIntoFile(in, tags.chunkId, chunk,1)) ++ alloc_failed = 1; ++ } ++ ++ endpos = ++ (tags.chunkId - 1) * dev->nDataBytesPerChunk + ++ tags.byteCount; ++ if (in && ++ in->variantType == YAFFS_OBJECT_TYPE_FILE ++ && in->variant.fileVariant.scannedFileSize < ++ endpos) { ++ in->variant.fileVariant. ++ scannedFileSize = endpos; ++ if (!dev->useHeaderFileSize) { ++ in->variant.fileVariant. ++ fileSize = ++ in->variant.fileVariant. ++ scannedFileSize; ++ } ++ ++ } ++ /* T((" %d %d data %d %d\n",blk,c,tags.objectId,tags.chunkId)); */ ++ } else { ++ /* chunkId == 0, so it is an ObjectHeader. ++ * Thus, we read in the object header and make the object ++ */ ++ yaffs_SetChunkBit(dev, blk, c); ++ bi->pagesInUse++; ++ ++ result = yaffs_ReadChunkWithTagsFromNAND(dev, chunk, ++ chunkData, ++ NULL); ++ ++ oh = (yaffs_ObjectHeader *) chunkData; ++ ++ in = yaffs_FindObjectByNumber(dev, ++ tags.objectId); ++ if (in && in->variantType != oh->type) { ++ /* This should not happen, but somehow ++ * Wev'e ended up with an objectId that has been reused but not yet ++ * deleted, and worse still it has changed type. Delete the old object. ++ */ ++ ++ yaffs_DestroyObject(in); ++ ++ in = 0; ++ } ++ ++ in = yaffs_FindOrCreateObjectByNumber(dev, ++ tags. ++ objectId, ++ oh->type); ++ ++ if(!in) ++ alloc_failed = 1; ++ ++ if (in && oh->shadowsObject > 0) { ++ ++ struct yaffs_ShadowFixerStruct *fixer; ++ fixer = YMALLOC(sizeof(struct yaffs_ShadowFixerStruct)); ++ if(fixer){ ++ fixer-> next = shadowFixerList; ++ shadowFixerList = fixer; ++ fixer->objectId = tags.objectId; ++ fixer->shadowedId = oh->shadowsObject; ++ } ++ ++ } ++ ++ if (in && in->valid) { ++ /* We have already filled this one. We have a duplicate and need to resolve it. */ ++ ++ unsigned existingSerial = in->serial; ++ unsigned newSerial = tags.serialNumber; ++ ++ if (((existingSerial + 1) & 3) == newSerial) { ++ /* Use new one - destroy the exisiting one */ ++ yaffs_DeleteChunk(dev, ++ in->hdrChunk, ++ 1, __LINE__); ++ in->valid = 0; ++ } else { ++ /* Use existing - destroy this one. */ ++ yaffs_DeleteChunk(dev, chunk, 1, ++ __LINE__); ++ } ++ } ++ ++ if (in && !in->valid && ++ (tags.objectId == YAFFS_OBJECTID_ROOT || ++ tags.objectId == YAFFS_OBJECTID_LOSTNFOUND)) { ++ /* We only load some info, don't fiddle with directory structure */ ++ in->valid = 1; ++ in->variantType = oh->type; ++ ++ in->yst_mode = oh->yst_mode; ++#ifdef CONFIG_YAFFS_WINCE ++ in->win_atime[0] = oh->win_atime[0]; ++ in->win_ctime[0] = oh->win_ctime[0]; ++ in->win_mtime[0] = oh->win_mtime[0]; ++ in->win_atime[1] = oh->win_atime[1]; ++ in->win_ctime[1] = oh->win_ctime[1]; ++ in->win_mtime[1] = oh->win_mtime[1]; ++#else ++ in->yst_uid = oh->yst_uid; ++ in->yst_gid = oh->yst_gid; ++ in->yst_atime = oh->yst_atime; ++ in->yst_mtime = oh->yst_mtime; ++ in->yst_ctime = oh->yst_ctime; ++ in->yst_rdev = oh->yst_rdev; ++#endif ++ in->hdrChunk = chunk; ++ in->serial = tags.serialNumber; ++ ++ } else if (in && !in->valid) { ++ /* we need to load this info */ ++ ++ in->valid = 1; ++ in->variantType = oh->type; ++ ++ in->yst_mode = oh->yst_mode; ++#ifdef CONFIG_YAFFS_WINCE ++ in->win_atime[0] = oh->win_atime[0]; ++ in->win_ctime[0] = oh->win_ctime[0]; ++ in->win_mtime[0] = oh->win_mtime[0]; ++ in->win_atime[1] = oh->win_atime[1]; ++ in->win_ctime[1] = oh->win_ctime[1]; ++ in->win_mtime[1] = oh->win_mtime[1]; ++#else ++ in->yst_uid = oh->yst_uid; ++ in->yst_gid = oh->yst_gid; ++ in->yst_atime = oh->yst_atime; ++ in->yst_mtime = oh->yst_mtime; ++ in->yst_ctime = oh->yst_ctime; ++ in->yst_rdev = oh->yst_rdev; ++#endif ++ in->hdrChunk = chunk; ++ in->serial = tags.serialNumber; ++ ++ yaffs_SetObjectName(in, oh->name); ++ in->dirty = 0; ++ ++ /* directory stuff... ++ * hook up to parent ++ */ ++ ++ parent = ++ yaffs_FindOrCreateObjectByNumber ++ (dev, oh->parentObjectId, ++ YAFFS_OBJECT_TYPE_DIRECTORY); ++ if(!parent) ++ alloc_failed = 1; ++ if (parent && parent->variantType == ++ YAFFS_OBJECT_TYPE_UNKNOWN) { ++ /* Set up as a directory */ ++ parent->variantType = ++ YAFFS_OBJECT_TYPE_DIRECTORY; ++ YINIT_LIST_HEAD(&parent->variant. ++ directoryVariant. ++ children); ++ } else if (!parent || parent->variantType != ++ YAFFS_OBJECT_TYPE_DIRECTORY) ++ { ++ /* Hoosterman, another problem.... ++ * We're trying to use a non-directory as a directory ++ */ ++ ++ T(YAFFS_TRACE_ERROR, ++ (TSTR ++ ("yaffs tragedy: attempting to use non-directory as a directory in scan. Put in lost+found." ++ TENDSTR))); ++ parent = dev->lostNFoundDir; ++ } ++ ++ yaffs_AddObjectToDirectory(parent, in); ++ ++ if (0 && (parent == dev->deletedDir || ++ parent == dev->unlinkedDir)) { ++ in->deleted = 1; /* If it is unlinked at start up then it wants deleting */ ++ dev->nDeletedFiles++; ++ } ++ /* Note re hardlinks. ++ * Since we might scan a hardlink before its equivalent object is scanned ++ * we put them all in a list. ++ * After scanning is complete, we should have all the objects, so we run through this ++ * list and fix up all the chains. ++ */ ++ ++ switch (in->variantType) { ++ case YAFFS_OBJECT_TYPE_UNKNOWN: ++ /* Todo got a problem */ ++ break; ++ case YAFFS_OBJECT_TYPE_FILE: ++ if (dev->useHeaderFileSize) ++ ++ in->variant.fileVariant. ++ fileSize = ++ oh->fileSize; ++ ++ break; ++ case YAFFS_OBJECT_TYPE_HARDLINK: ++ in->variant.hardLinkVariant. ++ equivalentObjectId = ++ oh->equivalentObjectId; ++ in->hardLinks.next = ++ (struct ylist_head *) ++ hardList; ++ hardList = in; ++ break; ++ case YAFFS_OBJECT_TYPE_DIRECTORY: ++ /* Do nothing */ ++ break; ++ case YAFFS_OBJECT_TYPE_SPECIAL: ++ /* Do nothing */ ++ break; ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ in->variant.symLinkVariant.alias = ++ yaffs_CloneString(oh->alias); ++ if(!in->variant.symLinkVariant.alias) ++ alloc_failed = 1; ++ break; ++ } ++ ++/* ++ if (parent == dev->deletedDir) { ++ yaffs_DestroyObject(in); ++ bi->hasShrinkHeader = 1; ++ } ++*/ ++ } ++ } ++ } ++ ++ if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING) { ++ /* If we got this far while scanning, then the block is fully allocated.*/ ++ state = YAFFS_BLOCK_STATE_FULL; ++ } ++ ++ bi->blockState = state; ++ ++ /* Now let's see if it was dirty */ ++ if (bi->pagesInUse == 0 && ++ !bi->hasShrinkHeader && ++ bi->blockState == YAFFS_BLOCK_STATE_FULL) { ++ yaffs_BlockBecameDirty(dev, blk); ++ } ++ ++ } ++ ++ ++ /* Ok, we've done all the scanning. ++ * Fix up the hard link chains. ++ * We should now have scanned all the objects, now it's time to add these ++ * hardlinks. ++ */ ++ ++ yaffs_HardlinkFixup(dev,hardList); ++ ++ /* Fix up any shadowed objects */ ++ { ++ struct yaffs_ShadowFixerStruct *fixer; ++ yaffs_Object *obj; ++ ++ while(shadowFixerList){ ++ fixer = shadowFixerList; ++ shadowFixerList = fixer->next; ++ /* Complete the rename transaction by deleting the shadowed object ++ * then setting the object header to unshadowed. ++ */ ++ obj = yaffs_FindObjectByNumber(dev,fixer->shadowedId); ++ if(obj) ++ yaffs_DestroyObject(obj); ++ ++ obj = yaffs_FindObjectByNumber(dev,fixer->objectId); ++ if(obj){ ++ yaffs_UpdateObjectHeader(obj,NULL,1,0,0); ++ } ++ ++ YFREE(fixer); ++ } ++ } ++ ++ yaffs_ReleaseTempBuffer(dev, chunkData, __LINE__); ++ ++ if(alloc_failed){ ++ return YAFFS_FAIL; ++ } ++ ++ T(YAFFS_TRACE_SCAN, (TSTR("yaffs_Scan ends" TENDSTR))); ++ ++ ++ return YAFFS_OK; ++} ++ ++static void yaffs_CheckObjectDetailsLoaded(yaffs_Object *in) ++{ ++ __u8 *chunkData; ++ yaffs_ObjectHeader *oh; ++ yaffs_Device *dev; ++ yaffs_ExtendedTags tags; ++ int result; ++ int alloc_failed = 0; ++ ++ if(!in) ++ return; ++ ++ dev = in->myDev; ++ ++#if 0 ++ T(YAFFS_TRACE_SCAN,(TSTR("details for object %d %s loaded" TENDSTR), ++ in->objectId, ++ in->lazyLoaded ? "not yet" : "already")); ++#endif ++ ++ if(in->lazyLoaded && in->hdrChunk > 0){ ++ in->lazyLoaded = 0; ++ chunkData = yaffs_GetTempBuffer(dev, __LINE__); ++ ++ result = yaffs_ReadChunkWithTagsFromNAND(dev,in->hdrChunk,chunkData,&tags); ++ oh = (yaffs_ObjectHeader *) chunkData; ++ ++ in->yst_mode = oh->yst_mode; ++#ifdef CONFIG_YAFFS_WINCE ++ in->win_atime[0] = oh->win_atime[0]; ++ in->win_ctime[0] = oh->win_ctime[0]; ++ in->win_mtime[0] = oh->win_mtime[0]; ++ in->win_atime[1] = oh->win_atime[1]; ++ in->win_ctime[1] = oh->win_ctime[1]; ++ in->win_mtime[1] = oh->win_mtime[1]; ++#else ++ in->yst_uid = oh->yst_uid; ++ in->yst_gid = oh->yst_gid; ++ in->yst_atime = oh->yst_atime; ++ in->yst_mtime = oh->yst_mtime; ++ in->yst_ctime = oh->yst_ctime; ++ in->yst_rdev = oh->yst_rdev; ++ ++#endif ++ yaffs_SetObjectName(in, oh->name); ++ ++ if(in->variantType == YAFFS_OBJECT_TYPE_SYMLINK){ ++ in->variant.symLinkVariant.alias = ++ yaffs_CloneString(oh->alias); ++ if(!in->variant.symLinkVariant.alias) ++ alloc_failed = 1; /* Not returned to caller */ ++ } ++ ++ yaffs_ReleaseTempBuffer(dev,chunkData, __LINE__); ++ } ++} ++ ++static int yaffs_ScanBackwards(yaffs_Device * dev) ++{ ++ yaffs_ExtendedTags tags; ++ int blk; ++ int blockIterator; ++ int startIterator; ++ int endIterator; ++ int nBlocksToScan = 0; ++ ++ int chunk; ++ int result; ++ int c; ++ int deleted; ++ yaffs_BlockState state; ++ yaffs_Object *hardList = NULL; ++ yaffs_BlockInfo *bi; ++ __u32 sequenceNumber; ++ yaffs_ObjectHeader *oh; ++ yaffs_Object *in; ++ yaffs_Object *parent; ++ int nBlocks = dev->internalEndBlock - dev->internalStartBlock + 1; ++ int itsUnlinked; ++ __u8 *chunkData; ++ ++ int fileSize; ++ int isShrink; ++ int foundChunksInBlock; ++ int equivalentObjectId; ++ int alloc_failed = 0; ++ ++ ++ yaffs_BlockIndex *blockIndex = NULL; ++ int altBlockIndex = 0; ++ ++ if (!dev->isYaffs2) { ++ T(YAFFS_TRACE_SCAN, ++ (TSTR("yaffs_ScanBackwards is only for YAFFS2!" TENDSTR))); ++ return YAFFS_FAIL; ++ } ++ ++ T(YAFFS_TRACE_SCAN, ++ (TSTR ++ ("yaffs_ScanBackwards starts intstartblk %d intendblk %d..." ++ TENDSTR), dev->internalStartBlock, dev->internalEndBlock)); ++ ++ ++ dev->sequenceNumber = YAFFS_LOWEST_SEQUENCE_NUMBER; ++ ++ blockIndex = YMALLOC(nBlocks * sizeof(yaffs_BlockIndex)); ++ ++ if(!blockIndex) { ++ blockIndex = YMALLOC_ALT(nBlocks * sizeof(yaffs_BlockIndex)); ++ altBlockIndex = 1; ++ } ++ ++ if(!blockIndex) { ++ T(YAFFS_TRACE_SCAN, ++ (TSTR("yaffs_Scan() could not allocate block index!" TENDSTR))); ++ return YAFFS_FAIL; ++ } ++ ++ dev->blocksInCheckpoint = 0; ++ ++ chunkData = yaffs_GetTempBuffer(dev, __LINE__); ++ ++ /* Scan all the blocks to determine their state */ ++ for (blk = dev->internalStartBlock; blk <= dev->internalEndBlock; blk++) { ++ bi = yaffs_GetBlockInfo(dev, blk); ++ yaffs_ClearChunkBits(dev, blk); ++ bi->pagesInUse = 0; ++ bi->softDeletions = 0; ++ ++ yaffs_QueryInitialBlockState(dev, blk, &state, &sequenceNumber); ++ ++ bi->blockState = state; ++ bi->sequenceNumber = sequenceNumber; ++ ++ if(bi->sequenceNumber == YAFFS_SEQUENCE_CHECKPOINT_DATA) ++ bi->blockState = state = YAFFS_BLOCK_STATE_CHECKPOINT; ++ if(bi->sequenceNumber == YAFFS_SEQUENCE_BAD_BLOCK) ++ bi->blockState = state = YAFFS_BLOCK_STATE_DEAD; ++ ++ T(YAFFS_TRACE_SCAN_DEBUG, ++ (TSTR("Block scanning block %d state %d seq %d" TENDSTR), blk, ++ state, sequenceNumber)); ++ ++ ++ if(state == YAFFS_BLOCK_STATE_CHECKPOINT){ ++ dev->blocksInCheckpoint++; ++ ++ } else if (state == YAFFS_BLOCK_STATE_DEAD) { ++ T(YAFFS_TRACE_BAD_BLOCKS, ++ (TSTR("block %d is bad" TENDSTR), blk)); ++ } else if (state == YAFFS_BLOCK_STATE_EMPTY) { ++ T(YAFFS_TRACE_SCAN_DEBUG, ++ (TSTR("Block empty " TENDSTR))); ++ dev->nErasedBlocks++; ++ dev->nFreeChunks += dev->nChunksPerBlock; ++ } else if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING) { ++ ++ /* Determine the highest sequence number */ ++ if (sequenceNumber >= YAFFS_LOWEST_SEQUENCE_NUMBER && ++ sequenceNumber < YAFFS_HIGHEST_SEQUENCE_NUMBER) { ++ ++ blockIndex[nBlocksToScan].seq = sequenceNumber; ++ blockIndex[nBlocksToScan].block = blk; ++ ++ nBlocksToScan++; ++ ++ if (sequenceNumber >= dev->sequenceNumber) { ++ dev->sequenceNumber = sequenceNumber; ++ } ++ } else { ++ /* TODO: Nasty sequence number! */ ++ T(YAFFS_TRACE_SCAN, ++ (TSTR ++ ("Block scanning block %d has bad sequence number %d" ++ TENDSTR), blk, sequenceNumber)); ++ ++ } ++ } ++ } ++ ++ T(YAFFS_TRACE_SCAN, ++ (TSTR("%d blocks to be sorted..." TENDSTR), nBlocksToScan)); ++ ++ ++ ++ YYIELD(); ++ ++ /* Sort the blocks */ ++#ifndef CONFIG_YAFFS_USE_OWN_SORT ++ { ++ /* Use qsort now. */ ++ yaffs_qsort(blockIndex, nBlocksToScan, sizeof(yaffs_BlockIndex), ybicmp); ++ } ++#else ++ { ++ /* Dungy old bubble sort... */ ++ ++ yaffs_BlockIndex temp; ++ int i; ++ int j; ++ ++ for (i = 0; i < nBlocksToScan; i++) ++ for (j = i + 1; j < nBlocksToScan; j++) ++ if (blockIndex[i].seq > blockIndex[j].seq) { ++ temp = blockIndex[j]; ++ blockIndex[j] = blockIndex[i]; ++ blockIndex[i] = temp; ++ } ++ } ++#endif ++ ++ YYIELD(); ++ ++ T(YAFFS_TRACE_SCAN, (TSTR("...done" TENDSTR))); ++ ++ /* Now scan the blocks looking at the data. */ ++ startIterator = 0; ++ endIterator = nBlocksToScan - 1; ++ T(YAFFS_TRACE_SCAN_DEBUG, ++ (TSTR("%d blocks to be scanned" TENDSTR), nBlocksToScan)); ++ ++ /* For each block.... backwards */ ++ for (blockIterator = endIterator; !alloc_failed && blockIterator >= startIterator; ++ blockIterator--) { ++ /* Cooperative multitasking! This loop can run for so ++ long that watchdog timers expire. */ ++ YYIELD(); ++ ++ /* get the block to scan in the correct order */ ++ blk = blockIndex[blockIterator].block; ++ ++ bi = yaffs_GetBlockInfo(dev, blk); ++ ++ ++ state = bi->blockState; ++ ++ deleted = 0; ++ ++ /* For each chunk in each block that needs scanning.... */ ++ foundChunksInBlock = 0; ++ for (c = dev->nChunksPerBlock - 1; ++ !alloc_failed && c >= 0 && ++ (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING || ++ state == YAFFS_BLOCK_STATE_ALLOCATING); c--) { ++ /* Scan backwards... ++ * Read the tags and decide what to do ++ */ ++ ++ chunk = blk * dev->nChunksPerBlock + c; ++ ++ result = yaffs_ReadChunkWithTagsFromNAND(dev, chunk, NULL, ++ &tags); ++ ++ /* Let's have a good look at this chunk... */ ++ ++ if (!tags.chunkUsed) { ++ /* An unassigned chunk in the block. ++ * If there are used chunks after this one, then ++ * it is a chunk that was skipped due to failing the erased ++ * check. Just skip it so that it can be deleted. ++ * But, more typically, We get here when this is an unallocated ++ * chunk and his means that either the block is empty or ++ * this is the one being allocated from ++ */ ++ ++ if(foundChunksInBlock) ++ { ++ /* This is a chunk that was skipped due to failing the erased check */ ++ ++ } else if (c == 0) { ++ /* We're looking at the first chunk in the block so the block is unused */ ++ state = YAFFS_BLOCK_STATE_EMPTY; ++ dev->nErasedBlocks++; ++ } else { ++ if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING || ++ state == YAFFS_BLOCK_STATE_ALLOCATING) { ++ if(dev->sequenceNumber == bi->sequenceNumber) { ++ /* this is the block being allocated from */ ++ ++ T(YAFFS_TRACE_SCAN, ++ (TSTR ++ (" Allocating from %d %d" ++ TENDSTR), blk, c)); ++ ++ state = YAFFS_BLOCK_STATE_ALLOCATING; ++ dev->allocationBlock = blk; ++ dev->allocationPage = c; ++ dev->allocationBlockFinder = blk; ++ } ++ else { ++ /* This is a partially written block that is not ++ * the current allocation block. This block must have ++ * had a write failure, so set up for retirement. ++ */ ++ ++ /* bi->needsRetiring = 1; ??? TODO */ ++ bi->gcPrioritise = 1; ++ ++ T(YAFFS_TRACE_ALWAYS, ++ (TSTR("Partially written block %d detected" TENDSTR), ++ blk)); ++ } ++ ++ } ++ ++ } ++ ++ dev->nFreeChunks++; ++ ++ } else if (tags.eccResult == YAFFS_ECC_RESULT_UNFIXED){ ++ T(YAFFS_TRACE_SCAN, ++ (TSTR(" Unfixed ECC in chunk(%d:%d), chunk ignored"TENDSTR), ++ blk, c)); ++ ++ dev->nFreeChunks++; ++ ++ }else if (tags.chunkId > 0) { ++ /* chunkId > 0 so it is a data chunk... */ ++ unsigned int endpos; ++ __u32 chunkBase = ++ (tags.chunkId - 1) * dev->nDataBytesPerChunk; ++ ++ foundChunksInBlock = 1; ++ ++ ++ yaffs_SetChunkBit(dev, blk, c); ++ bi->pagesInUse++; ++ ++ in = yaffs_FindOrCreateObjectByNumber(dev, ++ tags. ++ objectId, ++ YAFFS_OBJECT_TYPE_FILE); ++ if(!in){ ++ /* Out of memory */ ++ alloc_failed = 1; ++ } ++ ++ if (in && ++ in->variantType == YAFFS_OBJECT_TYPE_FILE ++ && chunkBase < ++ in->variant.fileVariant.shrinkSize) { ++ /* This has not been invalidated by a resize */ ++ if(!yaffs_PutChunkIntoFile(in, tags.chunkId, ++ chunk, -1)){ ++ alloc_failed = 1; ++ } ++ ++ /* File size is calculated by looking at the data chunks if we have not ++ * seen an object header yet. Stop this practice once we find an object header. ++ */ ++ endpos = ++ (tags.chunkId - ++ 1) * dev->nDataBytesPerChunk + ++ tags.byteCount; ++ ++ if (!in->valid && /* have not got an object header yet */ ++ in->variant.fileVariant. ++ scannedFileSize < endpos) { ++ in->variant.fileVariant. ++ scannedFileSize = endpos; ++ in->variant.fileVariant. ++ fileSize = ++ in->variant.fileVariant. ++ scannedFileSize; ++ } ++ ++ } else if(in) { ++ /* This chunk has been invalidated by a resize, so delete */ ++ yaffs_DeleteChunk(dev, chunk, 1, __LINE__); ++ ++ } ++ } else { ++ /* chunkId == 0, so it is an ObjectHeader. ++ * Thus, we read in the object header and make the object ++ */ ++ foundChunksInBlock = 1; ++ ++ yaffs_SetChunkBit(dev, blk, c); ++ bi->pagesInUse++; ++ ++ oh = NULL; ++ in = NULL; ++ ++ if (tags.extraHeaderInfoAvailable) { ++ in = yaffs_FindOrCreateObjectByNumber ++ (dev, tags.objectId, ++ tags.extraObjectType); ++ if (!in) ++ alloc_failed = 1; ++ } ++ ++ if (!in || ++#ifdef CONFIG_YAFFS_DISABLE_LAZY_LOAD ++ !in->valid || ++#endif ++ tags.extraShadows || ++ (!in->valid && ++ (tags.objectId == YAFFS_OBJECTID_ROOT || ++ tags.objectId == YAFFS_OBJECTID_LOSTNFOUND)) ++ ) { ++ ++ /* If we don't have valid info then we need to read the chunk ++ * TODO In future we can probably defer reading the chunk and ++ * living with invalid data until needed. ++ */ ++ ++ result = yaffs_ReadChunkWithTagsFromNAND(dev, ++ chunk, ++ chunkData, ++ NULL); ++ ++ oh = (yaffs_ObjectHeader *) chunkData; ++ ++ if(dev->inbandTags){ ++ /* Fix up the header if they got corrupted by inband tags */ ++ oh->shadowsObject = oh->inbandShadowsObject; ++ oh->isShrink = oh->inbandIsShrink; ++ } ++ ++ if (!in) { ++ in = yaffs_FindOrCreateObjectByNumber(dev, tags.objectId, oh->type); ++ if (!in) ++ alloc_failed = 1; ++ } ++ ++ } ++ ++ if (!in) { ++ /* TODO Hoosterman we have a problem! */ ++ T(YAFFS_TRACE_ERROR, ++ (TSTR ++ ("yaffs tragedy: Could not make object for object %d at chunk %d during scan" ++ TENDSTR), tags.objectId, chunk)); ++ continue; ++ } ++ ++ if (in->valid) { ++ /* We have already filled this one. ++ * We have a duplicate that will be discarded, but ++ * we first have to suck out resize info if it is a file. ++ */ ++ ++ if ((in->variantType == YAFFS_OBJECT_TYPE_FILE) && ++ ((oh && ++ oh-> type == YAFFS_OBJECT_TYPE_FILE)|| ++ (tags.extraHeaderInfoAvailable && ++ tags.extraObjectType == YAFFS_OBJECT_TYPE_FILE)) ++ ) { ++ __u32 thisSize = ++ (oh) ? oh->fileSize : tags. ++ extraFileLength; ++ __u32 parentObjectId = ++ (oh) ? oh-> ++ parentObjectId : tags. ++ extraParentObjectId; ++ ++ ++ isShrink = ++ (oh) ? oh->isShrink : tags. ++ extraIsShrinkHeader; ++ ++ /* If it is deleted (unlinked at start also means deleted) ++ * we treat the file size as being zeroed at this point. ++ */ ++ if (parentObjectId == ++ YAFFS_OBJECTID_DELETED ++ || parentObjectId == ++ YAFFS_OBJECTID_UNLINKED) { ++ thisSize = 0; ++ isShrink = 1; ++ } ++ ++ if (isShrink && ++ in->variant.fileVariant. ++ shrinkSize > thisSize) { ++ in->variant.fileVariant. ++ shrinkSize = ++ thisSize; ++ } ++ ++ if (isShrink) { ++ bi->hasShrinkHeader = 1; ++ } ++ ++ } ++ /* Use existing - destroy this one. */ ++ yaffs_DeleteChunk(dev, chunk, 1, __LINE__); ++ ++ } ++ ++ if (!in->valid && in->variantType != ++ (oh ? oh->type : tags.extraObjectType)) ++ T(YAFFS_TRACE_ERROR, ( ++ TSTR("yaffs tragedy: Bad object type, " ++ TCONT("%d != %d, for object %d at chunk ") ++ TCONT("%d during scan") ++ TENDSTR), oh ? ++ oh->type : tags.extraObjectType, ++ in->variantType, tags.objectId, ++ chunk)); ++ ++ if (!in->valid && ++ (tags.objectId == YAFFS_OBJECTID_ROOT || ++ tags.objectId == ++ YAFFS_OBJECTID_LOSTNFOUND)) { ++ /* We only load some info, don't fiddle with directory structure */ ++ in->valid = 1; ++ ++ if(oh) { ++ in->variantType = oh->type; ++ ++ in->yst_mode = oh->yst_mode; ++#ifdef CONFIG_YAFFS_WINCE ++ in->win_atime[0] = oh->win_atime[0]; ++ in->win_ctime[0] = oh->win_ctime[0]; ++ in->win_mtime[0] = oh->win_mtime[0]; ++ in->win_atime[1] = oh->win_atime[1]; ++ in->win_ctime[1] = oh->win_ctime[1]; ++ in->win_mtime[1] = oh->win_mtime[1]; ++#else ++ in->yst_uid = oh->yst_uid; ++ in->yst_gid = oh->yst_gid; ++ in->yst_atime = oh->yst_atime; ++ in->yst_mtime = oh->yst_mtime; ++ in->yst_ctime = oh->yst_ctime; ++ in->yst_rdev = oh->yst_rdev; ++ ++#endif ++ } else { ++ in->variantType = tags.extraObjectType; ++ in->lazyLoaded = 1; ++ } ++ ++ in->hdrChunk = chunk; ++ ++ } else if (!in->valid) { ++ /* we need to load this info */ ++ ++ in->valid = 1; ++ in->hdrChunk = chunk; ++ ++ if(oh) { ++ in->variantType = oh->type; ++ ++ in->yst_mode = oh->yst_mode; ++#ifdef CONFIG_YAFFS_WINCE ++ in->win_atime[0] = oh->win_atime[0]; ++ in->win_ctime[0] = oh->win_ctime[0]; ++ in->win_mtime[0] = oh->win_mtime[0]; ++ in->win_atime[1] = oh->win_atime[1]; ++ in->win_ctime[1] = oh->win_ctime[1]; ++ in->win_mtime[1] = oh->win_mtime[1]; ++#else ++ in->yst_uid = oh->yst_uid; ++ in->yst_gid = oh->yst_gid; ++ in->yst_atime = oh->yst_atime; ++ in->yst_mtime = oh->yst_mtime; ++ in->yst_ctime = oh->yst_ctime; ++ in->yst_rdev = oh->yst_rdev; ++#endif ++ ++ if (oh->shadowsObject > 0) ++ yaffs_HandleShadowedObject(dev, ++ oh-> ++ shadowsObject, ++ 1); ++ ++ ++ yaffs_SetObjectName(in, oh->name); ++ parent = ++ yaffs_FindOrCreateObjectByNumber ++ (dev, oh->parentObjectId, ++ YAFFS_OBJECT_TYPE_DIRECTORY); ++ ++ fileSize = oh->fileSize; ++ isShrink = oh->isShrink; ++ equivalentObjectId = oh->equivalentObjectId; ++ ++ } ++ else { ++ in->variantType = tags.extraObjectType; ++ parent = ++ yaffs_FindOrCreateObjectByNumber ++ (dev, tags.extraParentObjectId, ++ YAFFS_OBJECT_TYPE_DIRECTORY); ++ fileSize = tags.extraFileLength; ++ isShrink = tags.extraIsShrinkHeader; ++ equivalentObjectId = tags.extraEquivalentObjectId; ++ in->lazyLoaded = 1; ++ ++ } ++ in->dirty = 0; ++ ++ if (!parent) ++ alloc_failed = 1; ++ ++ /* directory stuff... ++ * hook up to parent ++ */ ++ ++ if (parent && parent->variantType == ++ YAFFS_OBJECT_TYPE_UNKNOWN) { ++ /* Set up as a directory */ ++ parent->variantType = ++ YAFFS_OBJECT_TYPE_DIRECTORY; ++ YINIT_LIST_HEAD(&parent->variant. ++ directoryVariant. ++ children); ++ } else if (!parent || parent->variantType != ++ YAFFS_OBJECT_TYPE_DIRECTORY) ++ { ++ /* Hoosterman, another problem.... ++ * We're trying to use a non-directory as a directory ++ */ ++ ++ T(YAFFS_TRACE_ERROR, ++ (TSTR ++ ("yaffs tragedy: attempting to use non-directory as a directory in scan. Put in lost+found." ++ TENDSTR))); ++ parent = dev->lostNFoundDir; ++ } ++ ++ yaffs_AddObjectToDirectory(parent, in); ++ ++ itsUnlinked = (parent == dev->deletedDir) || ++ (parent == dev->unlinkedDir); ++ ++ if (isShrink) { ++ /* Mark the block as having a shrinkHeader */ ++ bi->hasShrinkHeader = 1; ++ } ++ ++ /* Note re hardlinks. ++ * Since we might scan a hardlink before its equivalent object is scanned ++ * we put them all in a list. ++ * After scanning is complete, we should have all the objects, so we run ++ * through this list and fix up all the chains. ++ */ ++ ++ switch (in->variantType) { ++ case YAFFS_OBJECT_TYPE_UNKNOWN: ++ /* Todo got a problem */ ++ break; ++ case YAFFS_OBJECT_TYPE_FILE: ++ ++ if (in->variant.fileVariant. ++ scannedFileSize < fileSize) { ++ /* This covers the case where the file size is greater ++ * than where the data is ++ * This will happen if the file is resized to be larger ++ * than its current data extents. ++ */ ++ in->variant.fileVariant.fileSize = fileSize; ++ in->variant.fileVariant.scannedFileSize = ++ in->variant.fileVariant.fileSize; ++ } ++ ++ if (isShrink && ++ in->variant.fileVariant.shrinkSize > fileSize) { ++ in->variant.fileVariant.shrinkSize = fileSize; ++ } ++ ++ break; ++ case YAFFS_OBJECT_TYPE_HARDLINK: ++ if(!itsUnlinked) { ++ in->variant.hardLinkVariant.equivalentObjectId = ++ equivalentObjectId; ++ in->hardLinks.next = ++ (struct ylist_head *) hardList; ++ hardList = in; ++ } ++ break; ++ case YAFFS_OBJECT_TYPE_DIRECTORY: ++ /* Do nothing */ ++ break; ++ case YAFFS_OBJECT_TYPE_SPECIAL: ++ /* Do nothing */ ++ break; ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ if(oh){ ++ in->variant.symLinkVariant.alias = ++ yaffs_CloneString(oh-> ++ alias); ++ if(!in->variant.symLinkVariant.alias) ++ alloc_failed = 1; ++ } ++ break; ++ } ++ ++ } ++ ++ } ++ ++ } /* End of scanning for each chunk */ ++ ++ if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING) { ++ /* If we got this far while scanning, then the block is fully allocated. */ ++ state = YAFFS_BLOCK_STATE_FULL; ++ } ++ ++ bi->blockState = state; ++ ++ /* Now let's see if it was dirty */ ++ if (bi->pagesInUse == 0 && ++ !bi->hasShrinkHeader && ++ bi->blockState == YAFFS_BLOCK_STATE_FULL) { ++ yaffs_BlockBecameDirty(dev, blk); ++ } ++ ++ } ++ ++ if (altBlockIndex) ++ YFREE_ALT(blockIndex); ++ else ++ YFREE(blockIndex); ++ ++ /* Ok, we've done all the scanning. ++ * Fix up the hard link chains. ++ * We should now have scanned all the objects, now it's time to add these ++ * hardlinks. ++ */ ++ yaffs_HardlinkFixup(dev,hardList); ++ ++ ++ yaffs_ReleaseTempBuffer(dev, chunkData, __LINE__); ++ ++ if(alloc_failed){ ++ return YAFFS_FAIL; ++ } ++ ++ T(YAFFS_TRACE_SCAN, (TSTR("yaffs_ScanBackwards ends" TENDSTR))); ++ ++ return YAFFS_OK; ++} ++ ++/*------------------------------ Directory Functions ----------------------------- */ ++ ++static void yaffs_VerifyObjectInDirectory(yaffs_Object *obj) ++{ ++ struct ylist_head *lh; ++ yaffs_Object *listObj; ++ ++ int count = 0; ++ ++ if(!obj){ ++ T(YAFFS_TRACE_ALWAYS, (TSTR("No object to verify" TENDSTR))); ++ YBUG(); ++ } ++ ++ if(yaffs_SkipVerification(obj->myDev)) ++ return; ++ ++ if(!obj->parent){ ++ T(YAFFS_TRACE_ALWAYS, (TSTR("Object does not have parent" TENDSTR))); ++ YBUG(); ++ } ++ ++ if(obj->parent->variantType != YAFFS_OBJECT_TYPE_DIRECTORY){ ++ T(YAFFS_TRACE_ALWAYS, (TSTR("Parent is not directory" TENDSTR))); ++ YBUG(); ++ } ++ ++ /* Iterate through the objects in each hash entry */ ++ ++ ylist_for_each(lh, &obj->parent->variant.directoryVariant.children) { ++ if (lh) { ++ listObj = ylist_entry(lh, yaffs_Object, siblings); ++ yaffs_VerifyObject(listObj); ++ if(obj == listObj) ++ count ++; ++ } ++ } ++ ++ if(count != 1){ ++ T(YAFFS_TRACE_ALWAYS, (TSTR("Object in directory %d times" TENDSTR),count)); ++ YBUG(); ++ } ++ ++} ++ ++static void yaffs_VerifyDirectory(yaffs_Object *directory) ++{ ++ ++ struct ylist_head *lh; ++ yaffs_Object *listObj; ++ ++ if(!directory) ++ ;//YBUG(); ++ ++ if(yaffs_SkipFullVerification(directory->myDev)) ++ return; ++ ++ ++ if(directory->variantType != YAFFS_OBJECT_TYPE_DIRECTORY){ ++ T(YAFFS_TRACE_ALWAYS, (TSTR("Directory has wrong type: %d" TENDSTR),directory->variantType)); ++ YBUG(); ++ } ++ ++ /* Iterate through the objects in each hash entry */ ++ ++ ylist_for_each(lh, &directory->variant.directoryVariant.children) { ++ if (lh) { ++ listObj = ylist_entry(lh, yaffs_Object, siblings); ++ if(listObj->parent != directory){ ++ T(YAFFS_TRACE_ALWAYS, (TSTR("Object in directory list has wrong parent %p" TENDSTR),listObj->parent)); ++ YBUG(); ++ } ++ yaffs_VerifyObjectInDirectory(listObj); ++ } ++ } ++ ++} ++ ++ ++static void yaffs_RemoveObjectFromDirectory(yaffs_Object * obj) ++{ ++ yaffs_Device *dev = obj->myDev; ++ yaffs_Object *parent; ++ ++ yaffs_VerifyObjectInDirectory(obj); ++ parent = obj->parent; ++ ++ yaffs_VerifyDirectory(parent); ++ ++ if(dev && dev->removeObjectCallback) ++ dev->removeObjectCallback(obj); ++ ++ ++ ylist_del_init(&obj->siblings); ++ obj->parent = NULL; ++ ++ yaffs_VerifyDirectory(parent); ++ ++} ++ ++ ++static void yaffs_AddObjectToDirectory(yaffs_Object * directory, ++ yaffs_Object * obj) ++{ ++ ++ if (!directory) { ++ T(YAFFS_TRACE_ALWAYS, ++ (TSTR ++ ("tragedy: Trying to add an object to a null pointer directory" ++ TENDSTR))); ++ YBUG(); ++ } ++ if (directory->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) { ++ T(YAFFS_TRACE_ALWAYS, ++ (TSTR ++ ("tragedy: Trying to add an object to a non-directory" ++ TENDSTR))); ++ YBUG(); ++ } ++ ++ if (obj->siblings.prev == NULL) { ++ /* Not initialised */ ++ YBUG(); ++ ++ } else if (ylist_empty(&obj->siblings)) { ++ // YBUG(); ++ } ++ ++ ++ yaffs_VerifyDirectory(directory); ++ ++ yaffs_RemoveObjectFromDirectory(obj); ++ ++ ++ /* Now add it */ ++ ylist_add(&obj->siblings, &directory->variant.directoryVariant.children); ++ obj->parent = directory; ++ ++ if (directory == obj->myDev->unlinkedDir ++ || directory == obj->myDev->deletedDir) { ++ obj->unlinked = 1; ++ obj->myDev->nUnlinkedFiles++; ++ obj->renameAllowed = 0; ++ } ++ ++ yaffs_VerifyDirectory(directory); ++ yaffs_VerifyObjectInDirectory(obj); ++ ++ ++} ++ ++yaffs_Object *yaffs_FindObjectByName(yaffs_Object * directory, ++ const YCHAR * name) ++{ ++ int sum; ++ ++ struct ylist_head *i; ++ YCHAR buffer[YAFFS_MAX_NAME_LENGTH + 1]; ++ ++ yaffs_Object *l; ++ ++ if (!name) { ++ return NULL; ++ } ++ ++ if (!directory) { ++ T(YAFFS_TRACE_ALWAYS, ++ (TSTR ++ ("tragedy: yaffs_FindObjectByName: null pointer directory" ++ TENDSTR))); ++ YBUG(); ++ } ++ if (directory->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) { ++ T(YAFFS_TRACE_ALWAYS, ++ (TSTR ++ ("tragedy: yaffs_FindObjectByName: non-directory" TENDSTR))); ++ YBUG(); ++ } ++ ++ sum = yaffs_CalcNameSum(name); ++ ++ ylist_for_each(i, &directory->variant.directoryVariant.children) { ++ if (i) { ++ l = ylist_entry(i, yaffs_Object, siblings); ++ ++ if(l->parent != directory) ++ YBUG(); ++ ++ yaffs_CheckObjectDetailsLoaded(l); ++ ++ /* Special case for lost-n-found */ ++ if (l->objectId == YAFFS_OBJECTID_LOSTNFOUND) { ++ if (yaffs_strcmp(name, YAFFS_LOSTNFOUND_NAME) == 0) { ++ return l; ++ } ++ } else if (yaffs_SumCompare(l->sum, sum) || l->hdrChunk <= 0){ ++ /* LostnFound chunk called Objxxx ++ * Do a real check ++ */ ++ yaffs_GetObjectName(l, buffer, ++ YAFFS_MAX_NAME_LENGTH); ++ if (yaffs_strncmp(name, buffer,YAFFS_MAX_NAME_LENGTH) == 0) { ++ return l; ++ } ++ ++ } ++ } ++ } ++ ++ return NULL; ++} ++ ++ ++#if 0 ++int yaffs_ApplyToDirectoryChildren(yaffs_Object * theDir, ++ int (*fn) (yaffs_Object *)) ++{ ++ struct ylist_head *i; ++ yaffs_Object *l; ++ ++ if (!theDir) { ++ T(YAFFS_TRACE_ALWAYS, ++ (TSTR ++ ("tragedy: yaffs_FindObjectByName: null pointer directory" ++ TENDSTR))); ++ YBUG(); ++ } ++ if (theDir->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) { ++ T(YAFFS_TRACE_ALWAYS, ++ (TSTR ++ ("tragedy: yaffs_FindObjectByName: non-directory" TENDSTR))); ++ YBUG(); ++ } ++ ++ ylist_for_each(i, &theDir->variant.directoryVariant.children) { ++ if (i) { ++ l = ylist_entry(i, yaffs_Object, siblings); ++ if (l && !fn(l)) { ++ return YAFFS_FAIL; ++ } ++ } ++ } ++ ++ return YAFFS_OK; ++ ++} ++#endif ++ ++/* GetEquivalentObject dereferences any hard links to get to the ++ * actual object. ++ */ ++ ++yaffs_Object *yaffs_GetEquivalentObject(yaffs_Object * obj) ++{ ++ if (obj && obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK) { ++ /* We want the object id of the equivalent object, not this one */ ++ obj = obj->variant.hardLinkVariant.equivalentObject; ++ yaffs_CheckObjectDetailsLoaded(obj); ++ } ++ return obj; ++ ++} ++ ++int yaffs_GetObjectName(yaffs_Object * obj, YCHAR * name, int buffSize) ++{ ++ memset(name, 0, buffSize * sizeof(YCHAR)); ++ ++ yaffs_CheckObjectDetailsLoaded(obj); ++ ++ if (obj->objectId == YAFFS_OBJECTID_LOSTNFOUND) { ++ yaffs_strncpy(name, YAFFS_LOSTNFOUND_NAME, buffSize - 1); ++ } else if (obj->hdrChunk <= 0) { ++ YCHAR locName[20]; ++ YCHAR numString[20]; ++ YCHAR *x = &numString[19]; ++ unsigned v = obj->objectId; ++ numString[19] = 0; ++ while(v>0){ ++ x--; ++ *x = '0' + (v % 10); ++ v /= 10; ++ } ++ /* make up a name */ ++ yaffs_strcpy(locName, YAFFS_LOSTNFOUND_PREFIX); ++ yaffs_strcat(locName,x); ++ yaffs_strncpy(name, locName, buffSize - 1); ++ ++ } ++#ifdef CONFIG_YAFFS_SHORT_NAMES_IN_RAM ++ else if (obj->shortName[0]) { ++ yaffs_strcpy(name, obj->shortName); ++ } ++#endif ++ else { ++ int result; ++ __u8 *buffer = yaffs_GetTempBuffer(obj->myDev, __LINE__); ++ ++ yaffs_ObjectHeader *oh = (yaffs_ObjectHeader *) buffer; ++ ++ memset(buffer, 0, obj->myDev->nDataBytesPerChunk); ++ ++ if (obj->hdrChunk > 0) { ++ result = yaffs_ReadChunkWithTagsFromNAND(obj->myDev, ++ obj->hdrChunk, buffer, ++ NULL); ++ } ++ yaffs_strncpy(name, oh->name, buffSize - 1); ++ ++ yaffs_ReleaseTempBuffer(obj->myDev, buffer, __LINE__); ++ } ++ ++ return yaffs_strlen(name); ++} ++ ++int yaffs_GetObjectFileLength(yaffs_Object * obj) ++{ ++ ++ /* Dereference any hard linking */ ++ obj = yaffs_GetEquivalentObject(obj); ++ ++ if (obj->variantType == YAFFS_OBJECT_TYPE_FILE) { ++ return obj->variant.fileVariant.fileSize; ++ } ++ if (obj->variantType == YAFFS_OBJECT_TYPE_SYMLINK) { ++ return yaffs_strlen(obj->variant.symLinkVariant.alias); ++ } else { ++ /* Only a directory should drop through to here */ ++ return obj->myDev->nDataBytesPerChunk; ++ } ++} ++ ++int yaffs_GetObjectLinkCount(yaffs_Object * obj) ++{ ++ int count = 0; ++ struct ylist_head *i; ++ ++ if (!obj->unlinked) { ++ count++; /* the object itself */ ++ } ++ ylist_for_each(i, &obj->hardLinks) { ++ count++; /* add the hard links; */ ++ } ++ return count; ++ ++} ++ ++int yaffs_GetObjectInode(yaffs_Object * obj) ++{ ++ obj = yaffs_GetEquivalentObject(obj); ++ ++ return obj->objectId; ++} ++ ++unsigned yaffs_GetObjectType(yaffs_Object * obj) ++{ ++ obj = yaffs_GetEquivalentObject(obj); ++ ++ switch (obj->variantType) { ++ case YAFFS_OBJECT_TYPE_FILE: ++ return DT_REG; ++ break; ++ case YAFFS_OBJECT_TYPE_DIRECTORY: ++ return DT_DIR; ++ break; ++ case YAFFS_OBJECT_TYPE_SYMLINK: ++ return DT_LNK; ++ break; ++ case YAFFS_OBJECT_TYPE_HARDLINK: ++ return DT_REG; ++ break; ++ case YAFFS_OBJECT_TYPE_SPECIAL: ++ if (S_ISFIFO(obj->yst_mode)) ++ return DT_FIFO; ++ if (S_ISCHR(obj->yst_mode)) ++ return DT_CHR; ++ if (S_ISBLK(obj->yst_mode)) ++ return DT_BLK; ++ if (S_ISSOCK(obj->yst_mode)) ++ return DT_SOCK; ++ default: ++ return DT_REG; ++ break; ++ } ++} ++ ++YCHAR *yaffs_GetSymlinkAlias(yaffs_Object * obj) ++{ ++ obj = yaffs_GetEquivalentObject(obj); ++ if (obj->variantType == YAFFS_OBJECT_TYPE_SYMLINK) { ++ return yaffs_CloneString(obj->variant.symLinkVariant.alias); ++ } else { ++ return yaffs_CloneString(_Y("")); ++ } ++} ++ ++#ifndef CONFIG_YAFFS_WINCE ++ ++int yaffs_SetAttributes(yaffs_Object * obj, struct iattr *attr) ++{ ++ unsigned int valid = attr->ia_valid; ++ ++ if (valid & ATTR_MODE) ++ obj->yst_mode = attr->ia_mode; ++ if (valid & ATTR_UID) ++ obj->yst_uid = attr->ia_uid; ++ if (valid & ATTR_GID) ++ obj->yst_gid = attr->ia_gid; ++ ++ if (valid & ATTR_ATIME) ++ obj->yst_atime = Y_TIME_CONVERT(attr->ia_atime); ++ if (valid & ATTR_CTIME) ++ obj->yst_ctime = Y_TIME_CONVERT(attr->ia_ctime); ++ if (valid & ATTR_MTIME) ++ obj->yst_mtime = Y_TIME_CONVERT(attr->ia_mtime); ++ ++ if (valid & ATTR_SIZE) ++ yaffs_ResizeFile(obj, attr->ia_size); ++ ++ yaffs_UpdateObjectHeader(obj, NULL, 1, 0, 0); ++ ++ return YAFFS_OK; ++ ++} ++int yaffs_GetAttributes(yaffs_Object * obj, struct iattr *attr) ++{ ++ unsigned int valid = 0; ++ ++ attr->ia_mode = obj->yst_mode; ++ valid |= ATTR_MODE; ++ attr->ia_uid = obj->yst_uid; ++ valid |= ATTR_UID; ++ attr->ia_gid = obj->yst_gid; ++ valid |= ATTR_GID; ++ ++ Y_TIME_CONVERT(attr->ia_atime) = obj->yst_atime; ++ valid |= ATTR_ATIME; ++ Y_TIME_CONVERT(attr->ia_ctime) = obj->yst_ctime; ++ valid |= ATTR_CTIME; ++ Y_TIME_CONVERT(attr->ia_mtime) = obj->yst_mtime; ++ valid |= ATTR_MTIME; ++ ++ attr->ia_size = yaffs_GetFileSize(obj); ++ valid |= ATTR_SIZE; ++ ++ attr->ia_valid = valid; ++ ++ return YAFFS_OK; ++ ++} ++ ++#endif ++ ++#if 0 ++int yaffs_DumpObject(yaffs_Object * obj) ++{ ++ YCHAR name[257]; ++ ++ yaffs_GetObjectName(obj, name, 256); ++ ++ T(YAFFS_TRACE_ALWAYS, ++ (TSTR ++ ("Object %d, inode %d \"%s\"\n dirty %d valid %d serial %d sum %d" ++ " chunk %d type %d size %d\n" ++ TENDSTR), obj->objectId, yaffs_GetObjectInode(obj), name, ++ obj->dirty, obj->valid, obj->serial, obj->sum, obj->hdrChunk, ++ yaffs_GetObjectType(obj), yaffs_GetObjectFileLength(obj))); ++ ++ return YAFFS_OK; ++} ++#endif ++ ++/*---------------------------- Initialisation code -------------------------------------- */ ++ ++static int yaffs_CheckDevFunctions(const yaffs_Device * dev) ++{ ++ ++ /* Common functions, gotta have */ ++ if (!dev->eraseBlockInNAND || !dev->initialiseNAND) ++ return 0; ++ ++#ifdef CONFIG_YAFFS_YAFFS2 ++ ++ /* Can use the "with tags" style interface for yaffs1 or yaffs2 */ ++ if (dev->writeChunkWithTagsToNAND && ++ dev->readChunkWithTagsFromNAND && ++ !dev->writeChunkToNAND && ++ !dev->readChunkFromNAND && ++ dev->markNANDBlockBad && dev->queryNANDBlock) ++ return 1; ++#endif ++ ++ /* Can use the "spare" style interface for yaffs1 */ ++ if (!dev->isYaffs2 && ++ !dev->writeChunkWithTagsToNAND && ++ !dev->readChunkWithTagsFromNAND && ++ dev->writeChunkToNAND && ++ dev->readChunkFromNAND && ++ !dev->markNANDBlockBad && !dev->queryNANDBlock) ++ return 1; ++ ++ return 0; /* bad */ ++} ++ ++ ++static int yaffs_CreateInitialDirectories(yaffs_Device *dev) ++{ ++ /* Initialise the unlinked, deleted, root and lost and found directories */ ++ ++ dev->lostNFoundDir = dev->rootDir = NULL; ++ dev->unlinkedDir = dev->deletedDir = NULL; ++ ++ dev->unlinkedDir = ++ yaffs_CreateFakeDirectory(dev, YAFFS_OBJECTID_UNLINKED, S_IFDIR); ++ ++ dev->deletedDir = ++ yaffs_CreateFakeDirectory(dev, YAFFS_OBJECTID_DELETED, S_IFDIR); ++ ++ dev->rootDir = ++ yaffs_CreateFakeDirectory(dev, YAFFS_OBJECTID_ROOT, ++ YAFFS_ROOT_MODE | S_IFDIR); ++ dev->lostNFoundDir = ++ yaffs_CreateFakeDirectory(dev, YAFFS_OBJECTID_LOSTNFOUND, ++ YAFFS_LOSTNFOUND_MODE | S_IFDIR); ++ ++ if(dev->lostNFoundDir && dev->rootDir && dev->unlinkedDir && dev->deletedDir){ ++ yaffs_AddObjectToDirectory(dev->rootDir, dev->lostNFoundDir); ++ return YAFFS_OK; ++ } ++ ++ return YAFFS_FAIL; ++} ++ ++int yaffs_GutsInitialise(yaffs_Device * dev) ++{ ++ int init_failed = 0; ++ unsigned x; ++ int bits; ++ ++ T(YAFFS_TRACE_TRACING, (TSTR("yaffs: yaffs_GutsInitialise()" TENDSTR))); ++ ++ /* Check stuff that must be set */ ++ ++ if (!dev) { ++ T(YAFFS_TRACE_ALWAYS, (TSTR("yaffs: Need a device" TENDSTR))); ++ return YAFFS_FAIL; ++ } ++ ++ dev->internalStartBlock = dev->startBlock; ++ dev->internalEndBlock = dev->endBlock; ++ dev->blockOffset = 0; ++ dev->chunkOffset = 0; ++ dev->nFreeChunks = 0; ++ ++ dev->gcBlock = -1; ++ ++ if (dev->startBlock == 0) { ++ dev->internalStartBlock = dev->startBlock + 1; ++ dev->internalEndBlock = dev->endBlock + 1; ++ dev->blockOffset = 1; ++ dev->chunkOffset = dev->nChunksPerBlock; ++ } ++ ++ /* Check geometry parameters. */ ++ ++ if ((!dev->inbandTags && dev->isYaffs2 && dev->totalBytesPerChunk < 1024) || ++ (!dev->isYaffs2 && dev->totalBytesPerChunk < 512) || ++ (dev->inbandTags && !dev->isYaffs2 ) || ++ dev->nChunksPerBlock < 2 || ++ dev->nReservedBlocks < 2 || ++ dev->internalStartBlock <= 0 || ++ dev->internalEndBlock <= 0 || ++ dev->internalEndBlock <= (dev->internalStartBlock + dev->nReservedBlocks + 2) // otherwise it is too small ++ ) { ++ T(YAFFS_TRACE_ALWAYS, ++ (TSTR ++ ("yaffs: NAND geometry problems: chunk size %d, type is yaffs%s, inbandTags %d " ++ TENDSTR), dev->totalBytesPerChunk, dev->isYaffs2 ? "2" : "", dev->inbandTags)); ++ return YAFFS_FAIL; ++ } ++ ++ if (yaffs_InitialiseNAND(dev) != YAFFS_OK) { ++ T(YAFFS_TRACE_ALWAYS, ++ (TSTR("yaffs: InitialiseNAND failed" TENDSTR))); ++ return YAFFS_FAIL; ++ } ++ ++ /* Sort out space for inband tags, if required */ ++ if(dev->inbandTags) ++ dev->nDataBytesPerChunk = dev->totalBytesPerChunk - sizeof(yaffs_PackedTags2TagsPart); ++ else ++ dev->nDataBytesPerChunk = dev->totalBytesPerChunk; ++ ++ /* Got the right mix of functions? */ ++ if (!yaffs_CheckDevFunctions(dev)) { ++ /* Function missing */ ++ T(YAFFS_TRACE_ALWAYS, ++ (TSTR ++ ("yaffs: device function(s) missing or wrong\n" TENDSTR))); ++ ++ return YAFFS_FAIL; ++ } ++ ++ /* This is really a compilation check. */ ++ if (!yaffs_CheckStructures()) { ++ T(YAFFS_TRACE_ALWAYS, ++ (TSTR("yaffs_CheckStructures failed\n" TENDSTR))); ++ return YAFFS_FAIL; ++ } ++ ++ if (dev->isMounted) { ++ T(YAFFS_TRACE_ALWAYS, ++ (TSTR("yaffs: device already mounted\n" TENDSTR))); ++ return YAFFS_FAIL; ++ } ++ ++ /* Finished with most checks. One or two more checks happen later on too. */ ++ ++ dev->isMounted = 1; ++ ++ /* OK now calculate a few things for the device */ ++ ++ /* ++ * Calculate all the chunk size manipulation numbers: ++ */ ++ x = dev->nDataBytesPerChunk; ++ /* We always use dev->chunkShift and dev->chunkDiv */ ++ dev->chunkShift = Shifts(x); ++ x >>= dev->chunkShift; ++ dev->chunkDiv = x; ++ /* We only use chunk mask if chunkDiv is 1 */ ++ dev->chunkMask = (1<chunkShift) - 1; ++ ++ /* ++ * Calculate chunkGroupBits. ++ * We need to find the next power of 2 > than internalEndBlock ++ */ ++ ++ x = dev->nChunksPerBlock * (dev->internalEndBlock + 1); ++ ++ bits = ShiftsGE(x); ++ ++ /* Set up tnode width if wide tnodes are enabled. */ ++ if(!dev->wideTnodesDisabled){ ++ /* bits must be even so that we end up with 32-bit words */ ++ if(bits & 1) ++ bits++; ++ if(bits < 16) ++ dev->tnodeWidth = 16; ++ else ++ dev->tnodeWidth = bits; ++ } ++ else ++ dev->tnodeWidth = 16; ++ ++ dev->tnodeMask = (1<tnodeWidth)-1; ++ ++ /* Level0 Tnodes are 16 bits or wider (if wide tnodes are enabled), ++ * so if the bitwidth of the ++ * chunk range we're using is greater than 16 we need ++ * to figure out chunk shift and chunkGroupSize ++ */ ++ ++ if (bits <= dev->tnodeWidth) ++ dev->chunkGroupBits = 0; ++ else ++ dev->chunkGroupBits = bits - dev->tnodeWidth; ++ ++ ++ dev->chunkGroupSize = 1 << dev->chunkGroupBits; ++ ++ if (dev->nChunksPerBlock < dev->chunkGroupSize) { ++ /* We have a problem because the soft delete won't work if ++ * the chunk group size > chunks per block. ++ * This can be remedied by using larger "virtual blocks". ++ */ ++ T(YAFFS_TRACE_ALWAYS, ++ (TSTR("yaffs: chunk group too large\n" TENDSTR))); ++ ++ return YAFFS_FAIL; ++ } ++ ++ /* OK, we've finished verifying the device, lets continue with initialisation */ ++ ++ /* More device initialisation */ ++ dev->garbageCollections = 0; ++ dev->passiveGarbageCollections = 0; ++ dev->currentDirtyChecker = 0; ++ dev->bufferedBlock = -1; ++ dev->doingBufferedBlockRewrite = 0; ++ dev->nDeletedFiles = 0; ++ dev->nBackgroundDeletions = 0; ++ dev->nUnlinkedFiles = 0; ++ dev->eccFixed = 0; ++ dev->eccUnfixed = 0; ++ dev->tagsEccFixed = 0; ++ dev->tagsEccUnfixed = 0; ++ dev->nErasureFailures = 0; ++ dev->nErasedBlocks = 0; ++ dev->isDoingGC = 0; ++ dev->hasPendingPrioritisedGCs = 1; /* Assume the worst for now, will get fixed on first GC */ ++ ++ /* Initialise temporary buffers and caches. */ ++ if(!yaffs_InitialiseTempBuffers(dev)) ++ init_failed = 1; ++ ++ dev->srCache = NULL; ++ dev->gcCleanupList = NULL; ++ ++ ++ if (!init_failed && ++ dev->nShortOpCaches > 0) { ++ int i; ++ void *buf; ++ int srCacheBytes = dev->nShortOpCaches * sizeof(yaffs_ChunkCache); ++ ++ if (dev->nShortOpCaches > YAFFS_MAX_SHORT_OP_CACHES) { ++ dev->nShortOpCaches = YAFFS_MAX_SHORT_OP_CACHES; ++ } ++ ++ dev->srCache = YMALLOC(srCacheBytes); ++ ++ buf = (__u8 *) dev->srCache; ++ ++ if(dev->srCache) ++ memset(dev->srCache,0,srCacheBytes); ++ ++ for (i = 0; i < dev->nShortOpCaches && buf; i++) { ++ dev->srCache[i].object = NULL; ++ dev->srCache[i].lastUse = 0; ++ dev->srCache[i].dirty = 0; ++ dev->srCache[i].data = buf = YMALLOC_DMA(dev->totalBytesPerChunk); ++ } ++ if(!buf) ++ init_failed = 1; ++ ++ dev->srLastUse = 0; ++ } ++ ++ dev->cacheHits = 0; ++ ++ if(!init_failed){ ++ dev->gcCleanupList = YMALLOC(dev->nChunksPerBlock * sizeof(__u32)); ++ if(!dev->gcCleanupList) ++ init_failed = 1; ++ } ++ ++ if (dev->isYaffs2) { ++ dev->useHeaderFileSize = 1; ++ } ++ if(!init_failed && !yaffs_InitialiseBlocks(dev)) ++ init_failed = 1; ++ ++ yaffs_InitialiseTnodes(dev); ++ yaffs_InitialiseObjects(dev); ++ ++ if(!init_failed && !yaffs_CreateInitialDirectories(dev)) ++ init_failed = 1; ++ ++ ++ if(!init_failed){ ++ /* Now scan the flash. */ ++ if (dev->isYaffs2) { ++ if(yaffs_CheckpointRestore(dev)) { ++ yaffs_CheckObjectDetailsLoaded(dev->rootDir); ++ T(YAFFS_TRACE_ALWAYS, ++ (TSTR("yaffs: restored from checkpoint" TENDSTR))); ++ } else { ++ ++ /* Clean up the mess caused by an aborted checkpoint load ++ * and scan backwards. ++ */ ++ yaffs_DeinitialiseBlocks(dev); ++ yaffs_DeinitialiseTnodes(dev); ++ yaffs_DeinitialiseObjects(dev); ++ ++ ++ dev->nErasedBlocks = 0; ++ dev->nFreeChunks = 0; ++ dev->allocationBlock = -1; ++ dev->allocationPage = -1; ++ dev->nDeletedFiles = 0; ++ dev->nUnlinkedFiles = 0; ++ dev->nBackgroundDeletions = 0; ++ dev->oldestDirtySequence = 0; ++ ++ if(!init_failed && !yaffs_InitialiseBlocks(dev)) ++ init_failed = 1; ++ ++ yaffs_InitialiseTnodes(dev); ++ yaffs_InitialiseObjects(dev); ++ ++ if(!init_failed && !yaffs_CreateInitialDirectories(dev)) ++ init_failed = 1; ++ ++ if(!init_failed && !yaffs_ScanBackwards(dev)) ++ init_failed = 1; ++ } ++ }else ++ if(!yaffs_Scan(dev)) ++ init_failed = 1; ++ ++ yaffs_StripDeletedObjects(dev); ++ } ++ ++ if(init_failed){ ++ /* Clean up the mess */ ++ T(YAFFS_TRACE_TRACING, ++ (TSTR("yaffs: yaffs_GutsInitialise() aborted.\n" TENDSTR))); ++ ++ yaffs_Deinitialise(dev); ++ return YAFFS_FAIL; ++ } ++ ++ /* Zero out stats */ ++ dev->nPageReads = 0; ++ dev->nPageWrites = 0; ++ dev->nBlockErasures = 0; ++ dev->nGCCopies = 0; ++ dev->nRetriedWrites = 0; ++ ++ dev->nRetiredBlocks = 0; ++ ++ yaffs_VerifyFreeChunks(dev); ++ yaffs_VerifyBlocks(dev); ++ ++ ++ T(YAFFS_TRACE_TRACING, ++ (TSTR("yaffs: yaffs_GutsInitialise() done.\n" TENDSTR))); ++ return YAFFS_OK; ++ ++} ++ ++void yaffs_Deinitialise(yaffs_Device * dev) ++{ ++ if (dev->isMounted) { ++ int i; ++ ++ yaffs_DeinitialiseBlocks(dev); ++ yaffs_DeinitialiseTnodes(dev); ++ yaffs_DeinitialiseObjects(dev); ++ if (dev->nShortOpCaches > 0 && ++ dev->srCache) { ++ ++ for (i = 0; i < dev->nShortOpCaches; i++) { ++ if(dev->srCache[i].data) ++ YFREE(dev->srCache[i].data); ++ dev->srCache[i].data = NULL; ++ } ++ ++ YFREE(dev->srCache); ++ dev->srCache = NULL; ++ } ++ ++ YFREE(dev->gcCleanupList); ++ ++ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) { ++ YFREE(dev->tempBuffer[i].buffer); ++ } ++ ++ ++ dev->isMounted = 0; ++ ++ if(dev->deinitialiseNAND) ++ dev->deinitialiseNAND(dev); ++ } ++ ++} ++ ++static int yaffs_CountFreeChunks(yaffs_Device * dev) ++{ ++ int nFree; ++ int b; ++ ++ yaffs_BlockInfo *blk; ++ ++ for (nFree = 0, b = dev->internalStartBlock; b <= dev->internalEndBlock; ++ b++) { ++ blk = yaffs_GetBlockInfo(dev, b); ++ ++ switch (blk->blockState) { ++ case YAFFS_BLOCK_STATE_EMPTY: ++ case YAFFS_BLOCK_STATE_ALLOCATING: ++ case YAFFS_BLOCK_STATE_COLLECTING: ++ case YAFFS_BLOCK_STATE_FULL: ++ nFree += ++ (dev->nChunksPerBlock - blk->pagesInUse + ++ blk->softDeletions); ++ break; ++ default: ++ break; ++ } ++ ++ } ++ ++ return nFree; ++} ++ ++int yaffs_GetNumberOfFreeChunks(yaffs_Device * dev) ++{ ++ /* This is what we report to the outside world */ ++ ++ int nFree; ++ int nDirtyCacheChunks; ++ int blocksForCheckpoint; ++ ++#if 1 ++ nFree = dev->nFreeChunks; ++#else ++ nFree = yaffs_CountFreeChunks(dev); ++#endif ++ ++ nFree += dev->nDeletedFiles; ++ ++ /* Now count the number of dirty chunks in the cache and subtract those */ ++ ++ { ++ int i; ++ for (nDirtyCacheChunks = 0, i = 0; i < dev->nShortOpCaches; i++) { ++ if (dev->srCache[i].dirty) ++ nDirtyCacheChunks++; ++ } ++ } ++ ++ nFree -= nDirtyCacheChunks; ++ ++ nFree -= ((dev->nReservedBlocks + 1) * dev->nChunksPerBlock); ++ ++ /* Now we figure out how much to reserve for the checkpoint and report that... */ ++ blocksForCheckpoint = yaffs_CalcCheckpointBlocksRequired(dev) - dev->blocksInCheckpoint; ++ if(blocksForCheckpoint < 0) ++ blocksForCheckpoint = 0; ++ ++ nFree -= (blocksForCheckpoint * dev->nChunksPerBlock); ++ ++ if (nFree < 0) ++ nFree = 0; ++ ++ return nFree; ++ ++} ++ ++static int yaffs_freeVerificationFailures; ++ ++static void yaffs_VerifyFreeChunks(yaffs_Device * dev) ++{ ++ int counted; ++ int difference; ++ ++ if(yaffs_SkipVerification(dev)) ++ return; ++ ++ counted = yaffs_CountFreeChunks(dev); ++ ++ difference = dev->nFreeChunks - counted; ++ ++ if (difference) { ++ T(YAFFS_TRACE_ALWAYS, ++ (TSTR("Freechunks verification failure %d %d %d" TENDSTR), ++ dev->nFreeChunks, counted, difference)); ++ yaffs_freeVerificationFailures++; ++ } ++} ++ ++/*---------------------------------------- YAFFS test code ----------------------*/ ++ ++#define yaffs_CheckStruct(structure,syze, name) \ ++ do { \ ++ if(sizeof(structure) != syze) \ ++ { \ ++ T(YAFFS_TRACE_ALWAYS,(TSTR("%s should be %d but is %d\n" TENDSTR),\ ++ name,syze,sizeof(structure))); \ ++ return YAFFS_FAIL; \ ++ } \ ++ } while(0) ++ ++static int yaffs_CheckStructures(void) ++{ ++/* yaffs_CheckStruct(yaffs_Tags,8,"yaffs_Tags"); */ ++/* yaffs_CheckStruct(yaffs_TagsUnion,8,"yaffs_TagsUnion"); */ ++/* yaffs_CheckStruct(yaffs_Spare,16,"yaffs_Spare"); */ ++#ifndef CONFIG_YAFFS_TNODE_LIST_DEBUG ++ yaffs_CheckStruct(yaffs_Tnode, 2 * YAFFS_NTNODES_LEVEL0, "yaffs_Tnode"); ++#endif ++#ifndef CONFIG_YAFFS_WINCE ++ yaffs_CheckStruct(yaffs_ObjectHeader, 512, "yaffs_ObjectHeader"); ++#endif ++ return YAFFS_OK; ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_guts.h linux-2.6.28.6/fs/yaffs2/yaffs_guts.h +--- linux-2.6.28/fs/yaffs2/yaffs_guts.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_guts.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,908 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_GUTS_H__ ++#define __YAFFS_GUTS_H__ ++ ++#include "devextras.h" ++#include "yportenv.h" ++ ++#define YAFFS_OK 1 ++#define YAFFS_FAIL 0 ++ ++/* Give us a Y=0x59, ++ * Give us an A=0x41, ++ * Give us an FF=0xFF ++ * Give us an S=0x53 ++ * And what have we got... ++ */ ++#define YAFFS_MAGIC 0x5941FF53 ++ ++#define YAFFS_NTNODES_LEVEL0 16 ++#define YAFFS_TNODES_LEVEL0_BITS 4 ++#define YAFFS_TNODES_LEVEL0_MASK 0xf ++ ++#define YAFFS_NTNODES_INTERNAL (YAFFS_NTNODES_LEVEL0 / 2) ++#define YAFFS_TNODES_INTERNAL_BITS (YAFFS_TNODES_LEVEL0_BITS - 1) ++#define YAFFS_TNODES_INTERNAL_MASK 0x7 ++#define YAFFS_TNODES_MAX_LEVEL 6 ++ ++#ifndef CONFIG_YAFFS_NO_YAFFS1 ++#define YAFFS_BYTES_PER_SPARE 16 ++#define YAFFS_BYTES_PER_CHUNK 512 ++#define YAFFS_CHUNK_SIZE_SHIFT 9 ++#define YAFFS_CHUNKS_PER_BLOCK 32 ++#define YAFFS_BYTES_PER_BLOCK (YAFFS_CHUNKS_PER_BLOCK*YAFFS_BYTES_PER_CHUNK) ++#endif ++ ++#define YAFFS_MIN_YAFFS2_CHUNK_SIZE 1024 ++#define YAFFS_MIN_YAFFS2_SPARE_SIZE 32 ++ ++#define YAFFS_MAX_CHUNK_ID 0x000FFFFF ++ ++#define YAFFS_UNUSED_OBJECT_ID 0x0003FFFF ++ ++#define YAFFS_ALLOCATION_NOBJECTS 100 ++#define YAFFS_ALLOCATION_NTNODES 100 ++#define YAFFS_ALLOCATION_NLINKS 100 ++ ++#define YAFFS_NOBJECT_BUCKETS 256 ++ ++ ++#define YAFFS_OBJECT_SPACE 0x40000 ++ ++#define YAFFS_CHECKPOINT_VERSION 3 ++ ++#ifdef CONFIG_YAFFS_UNICODE ++#define YAFFS_MAX_NAME_LENGTH 127 ++#define YAFFS_MAX_ALIAS_LENGTH 79 ++#else ++#define YAFFS_MAX_NAME_LENGTH 255 ++#define YAFFS_MAX_ALIAS_LENGTH 159 ++#endif ++ ++#define YAFFS_SHORT_NAME_LENGTH 15 ++ ++/* Some special object ids for pseudo objects */ ++#define YAFFS_OBJECTID_ROOT 1 ++#define YAFFS_OBJECTID_LOSTNFOUND 2 ++#define YAFFS_OBJECTID_UNLINKED 3 ++#define YAFFS_OBJECTID_DELETED 4 ++ ++/* Sseudo object ids for checkpointing */ ++#define YAFFS_OBJECTID_SB_HEADER 0x10 ++#define YAFFS_OBJECTID_CHECKPOINT_DATA 0x20 ++#define YAFFS_SEQUENCE_CHECKPOINT_DATA 0x21 ++ ++/* */ ++ ++#define YAFFS_MAX_SHORT_OP_CACHES 20 ++ ++#define YAFFS_N_TEMP_BUFFERS 6 ++ ++/* We limit the number attempts at sucessfully saving a chunk of data. ++ * Small-page devices have 32 pages per block; large-page devices have 64. ++ * Default to something in the order of 5 to 10 blocks worth of chunks. ++ */ ++#define YAFFS_WR_ATTEMPTS (5*64) ++ ++/* Sequence numbers are used in YAFFS2 to determine block allocation order. ++ * The range is limited slightly to help distinguish bad numbers from good. ++ * This also allows us to perhaps in the future use special numbers for ++ * special purposes. ++ * EFFFFF00 allows the allocation of 8 blocks per second (~1Mbytes) for 15 years, ++ * and is a larger number than the lifetime of a 2GB device. ++ */ ++#define YAFFS_LOWEST_SEQUENCE_NUMBER 0x00001000 ++#define YAFFS_HIGHEST_SEQUENCE_NUMBER 0xEFFFFF00 ++ ++/* Special sequence number for bad block that failed to be marked bad */ ++#define YAFFS_SEQUENCE_BAD_BLOCK 0xFFFF0000 ++ ++/* ChunkCache is used for short read/write operations.*/ ++typedef struct { ++ struct yaffs_ObjectStruct *object; ++ int chunkId; ++ int lastUse; ++ int dirty; ++ int nBytes; /* Only valid if the cache is dirty */ ++ int locked; /* Can't push out or flush while locked. */ ++#ifdef CONFIG_YAFFS_YAFFS2 ++ __u8 *data; ++#else ++ __u8 data[YAFFS_BYTES_PER_CHUNK]; ++#endif ++} yaffs_ChunkCache; ++ ++ ++ ++/* Tags structures in RAM ++ * NB This uses bitfield. Bitfields should not straddle a u32 boundary otherwise ++ * the structure size will get blown out. ++ */ ++ ++#ifndef CONFIG_YAFFS_NO_YAFFS1 ++typedef struct { ++ unsigned chunkId:20; ++ unsigned serialNumber:2; ++ unsigned byteCountLSB:10; ++ unsigned objectId:18; ++ unsigned ecc:12; ++ unsigned byteCountMSB:2; ++ ++} yaffs_Tags; ++ ++typedef union { ++ yaffs_Tags asTags; ++ __u8 asBytes[8]; ++} yaffs_TagsUnion; ++ ++#endif ++ ++/* Stuff used for extended tags in YAFFS2 */ ++ ++typedef enum { ++ YAFFS_ECC_RESULT_UNKNOWN, ++ YAFFS_ECC_RESULT_NO_ERROR, ++ YAFFS_ECC_RESULT_FIXED, ++ YAFFS_ECC_RESULT_UNFIXED ++} yaffs_ECCResult; ++ ++typedef enum { ++ YAFFS_OBJECT_TYPE_UNKNOWN, ++ YAFFS_OBJECT_TYPE_FILE, ++ YAFFS_OBJECT_TYPE_SYMLINK, ++ YAFFS_OBJECT_TYPE_DIRECTORY, ++ YAFFS_OBJECT_TYPE_HARDLINK, ++ YAFFS_OBJECT_TYPE_SPECIAL ++} yaffs_ObjectType; ++ ++#define YAFFS_OBJECT_TYPE_MAX YAFFS_OBJECT_TYPE_SPECIAL ++ ++typedef struct { ++ ++ unsigned validMarker0; ++ unsigned chunkUsed; /* Status of the chunk: used or unused */ ++ unsigned objectId; /* If 0 then this is not part of an object (unused) */ ++ unsigned chunkId; /* If 0 then this is a header, else a data chunk */ ++ unsigned byteCount; /* Only valid for data chunks */ ++ ++ /* The following stuff only has meaning when we read */ ++ yaffs_ECCResult eccResult; ++ unsigned blockBad; ++ ++ /* YAFFS 1 stuff */ ++ unsigned chunkDeleted; /* The chunk is marked deleted */ ++ unsigned serialNumber; /* Yaffs1 2-bit serial number */ ++ ++ /* YAFFS2 stuff */ ++ unsigned sequenceNumber; /* The sequence number of this block */ ++ ++ /* Extra info if this is an object header (YAFFS2 only) */ ++ ++ unsigned extraHeaderInfoAvailable; /* There is extra info available if this is not zero */ ++ unsigned extraParentObjectId; /* The parent object */ ++ unsigned extraIsShrinkHeader; /* Is it a shrink header? */ ++ unsigned extraShadows; /* Does this shadow another object? */ ++ ++ yaffs_ObjectType extraObjectType; /* What object type? */ ++ ++ unsigned extraFileLength; /* Length if it is a file */ ++ unsigned extraEquivalentObjectId; /* Equivalent object Id if it is a hard link */ ++ ++ unsigned validMarker1; ++ ++} yaffs_ExtendedTags; ++ ++/* Spare structure for YAFFS1 */ ++typedef struct { ++ __u8 tagByte0; ++ __u8 tagByte1; ++ __u8 tagByte2; ++ __u8 tagByte3; ++ __u8 pageStatus; /* set to 0 to delete the chunk */ ++ __u8 blockStatus; ++ __u8 tagByte4; ++ __u8 tagByte5; ++ __u8 ecc1[3]; ++ __u8 tagByte6; ++ __u8 tagByte7; ++ __u8 ecc2[3]; ++} yaffs_Spare; ++ ++/*Special structure for passing through to mtd */ ++struct yaffs_NANDSpare { ++ yaffs_Spare spare; ++ int eccres1; ++ int eccres2; ++}; ++ ++/* Block data in RAM */ ++ ++typedef enum { ++ YAFFS_BLOCK_STATE_UNKNOWN = 0, ++ ++ YAFFS_BLOCK_STATE_SCANNING, ++ YAFFS_BLOCK_STATE_NEEDS_SCANNING, ++ /* The block might have something on it (ie it is allocating or full, perhaps empty) ++ * but it needs to be scanned to determine its true state. ++ * This state is only valid during yaffs_Scan. ++ * NB We tolerate empty because the pre-scanner might be incapable of deciding ++ * However, if this state is returned on a YAFFS2 device, then we expect a sequence number ++ */ ++ ++ YAFFS_BLOCK_STATE_EMPTY, ++ /* This block is empty */ ++ ++ YAFFS_BLOCK_STATE_ALLOCATING, ++ /* This block is partially allocated. ++ * At least one page holds valid data. ++ * This is the one currently being used for page ++ * allocation. Should never be more than one of these ++ */ ++ ++ YAFFS_BLOCK_STATE_FULL, ++ /* All the pages in this block have been allocated. ++ */ ++ ++ YAFFS_BLOCK_STATE_DIRTY, ++ /* All pages have been allocated and deleted. ++ * Erase me, reuse me. ++ */ ++ ++ YAFFS_BLOCK_STATE_CHECKPOINT, ++ /* This block is assigned to holding checkpoint data. ++ */ ++ ++ YAFFS_BLOCK_STATE_COLLECTING, ++ /* This block is being garbage collected */ ++ ++ YAFFS_BLOCK_STATE_DEAD ++ /* This block has failed and is not in use */ ++} yaffs_BlockState; ++ ++#define YAFFS_NUMBER_OF_BLOCK_STATES (YAFFS_BLOCK_STATE_DEAD + 1) ++ ++ ++typedef struct { ++ ++ int softDeletions:10; /* number of soft deleted pages */ ++ int pagesInUse:10; /* number of pages in use */ ++ unsigned blockState:4; /* One of the above block states. NB use unsigned because enum is sometimes an int */ ++ __u32 needsRetiring:1; /* Data has failed on this block, need to get valid data off */ ++ /* and retire the block. */ ++ __u32 skipErasedCheck: 1; /* If this is set we can skip the erased check on this block */ ++ __u32 gcPrioritise: 1; /* An ECC check or blank check has failed on this block. ++ It should be prioritised for GC */ ++ __u32 chunkErrorStrikes:3; /* How many times we've had ecc etc failures on this block and tried to reuse it */ ++ ++#ifdef CONFIG_YAFFS_YAFFS2 ++ __u32 hasShrinkHeader:1; /* This block has at least one shrink object header */ ++ __u32 sequenceNumber; /* block sequence number for yaffs2 */ ++#endif ++ ++} yaffs_BlockInfo; ++ ++/* -------------------------- Object structure -------------------------------*/ ++/* This is the object structure as stored on NAND */ ++ ++typedef struct { ++ yaffs_ObjectType type; ++ ++ /* Apply to everything */ ++ int parentObjectId; ++ __u16 sum__NoLongerUsed; /* checksum of name. No longer used */ ++ YCHAR name[YAFFS_MAX_NAME_LENGTH + 1]; ++ ++ /* The following apply to directories, files, symlinks - not hard links */ ++ __u32 yst_mode; /* protection */ ++ ++#ifdef CONFIG_YAFFS_WINCE ++ __u32 notForWinCE[5]; ++#else ++ __u32 yst_uid; ++ __u32 yst_gid; ++ __u32 yst_atime; ++ __u32 yst_mtime; ++ __u32 yst_ctime; ++#endif ++ ++ /* File size applies to files only */ ++ int fileSize; ++ ++ /* Equivalent object id applies to hard links only. */ ++ int equivalentObjectId; ++ ++ /* Alias is for symlinks only. */ ++ YCHAR alias[YAFFS_MAX_ALIAS_LENGTH + 1]; ++ ++ __u32 yst_rdev; /* device stuff for block and char devices (major/min) */ ++ ++#ifdef CONFIG_YAFFS_WINCE ++ __u32 win_ctime[2]; ++ __u32 win_atime[2]; ++ __u32 win_mtime[2]; ++#else ++ __u32 roomToGrow[6]; ++ ++#endif ++ __u32 inbandShadowsObject; ++ __u32 inbandIsShrink; ++ ++ __u32 reservedSpace[2]; ++ int shadowsObject; /* This object header shadows the specified object if > 0 */ ++ ++ /* isShrink applies to object headers written when we shrink the file (ie resize) */ ++ __u32 isShrink; ++ ++} yaffs_ObjectHeader; ++ ++/*--------------------------- Tnode -------------------------- */ ++ ++union yaffs_Tnode_union { ++#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG ++ union yaffs_Tnode_union *internal[YAFFS_NTNODES_INTERNAL + 1]; ++#else ++ union yaffs_Tnode_union *internal[YAFFS_NTNODES_INTERNAL]; ++#endif ++/* __u16 level0[YAFFS_NTNODES_LEVEL0]; */ ++ ++}; ++ ++typedef union yaffs_Tnode_union yaffs_Tnode; ++ ++struct yaffs_TnodeList_struct { ++ struct yaffs_TnodeList_struct *next; ++ yaffs_Tnode *tnodes; ++}; ++ ++typedef struct yaffs_TnodeList_struct yaffs_TnodeList; ++ ++/*------------------------ Object -----------------------------*/ ++/* An object can be one of: ++ * - a directory (no data, has children links ++ * - a regular file (data.... not prunes :->). ++ * - a symlink [symbolic link] (the alias). ++ * - a hard link ++ */ ++ ++typedef struct { ++ __u32 fileSize; ++ __u32 scannedFileSize; ++ __u32 shrinkSize; ++ int topLevel; ++ yaffs_Tnode *top; ++} yaffs_FileStructure; ++ ++typedef struct { ++ struct ylist_head children; /* list of child links */ ++} yaffs_DirectoryStructure; ++ ++typedef struct { ++ YCHAR *alias; ++} yaffs_SymLinkStructure; ++ ++typedef struct { ++ struct yaffs_ObjectStruct *equivalentObject; ++ __u32 equivalentObjectId; ++} yaffs_HardLinkStructure; ++ ++typedef union { ++ yaffs_FileStructure fileVariant; ++ yaffs_DirectoryStructure directoryVariant; ++ yaffs_SymLinkStructure symLinkVariant; ++ yaffs_HardLinkStructure hardLinkVariant; ++} yaffs_ObjectVariant; ++ ++struct yaffs_ObjectStruct { ++ __u8 deleted:1; /* This should only apply to unlinked files. */ ++ __u8 softDeleted:1; /* it has also been soft deleted */ ++ __u8 unlinked:1; /* An unlinked file. The file should be in the unlinked directory.*/ ++ __u8 fake:1; /* A fake object has no presence on NAND. */ ++ __u8 renameAllowed:1; /* Some objects are not allowed to be renamed. */ ++ __u8 unlinkAllowed:1; ++ __u8 dirty:1; /* the object needs to be written to flash */ ++ __u8 valid:1; /* When the file system is being loaded up, this ++ * object might be created before the data ++ * is available (ie. file data records appear before the header). ++ */ ++ __u8 lazyLoaded:1; /* This object has been lazy loaded and is missing some detail */ ++ ++ __u8 deferedFree:1; /* For Linux kernel. Object is removed from NAND, but is ++ * still in the inode cache. Free of object is defered. ++ * until the inode is released. ++ */ ++ __u8 beingCreated:1; /* This object is still being created so skip some checks. */ ++ ++ __u8 serial; /* serial number of chunk in NAND. Cached here */ ++ __u16 sum; /* sum of the name to speed searching */ ++ ++ struct yaffs_DeviceStruct *myDev; /* The device I'm on */ ++ ++ struct ylist_head hashLink; /* list of objects in this hash bucket */ ++ ++ struct ylist_head hardLinks; /* all the equivalent hard linked objects */ ++ ++ /* directory structure stuff */ ++ /* also used for linking up the free list */ ++ struct yaffs_ObjectStruct *parent; ++ struct ylist_head siblings; ++ ++ /* Where's my object header in NAND? */ ++ int hdrChunk; ++ ++ int nDataChunks; /* Number of data chunks attached to the file. */ ++ ++ __u32 objectId; /* the object id value */ ++ ++ __u32 yst_mode; ++ ++#ifdef CONFIG_YAFFS_SHORT_NAMES_IN_RAM ++ YCHAR shortName[YAFFS_SHORT_NAME_LENGTH + 1]; ++#endif ++ ++#ifndef __KERNEL__ ++ __u32 inUse; ++#endif ++ ++#ifdef CONFIG_YAFFS_WINCE ++ __u32 win_ctime[2]; ++ __u32 win_mtime[2]; ++ __u32 win_atime[2]; ++#else ++ __u32 yst_uid; ++ __u32 yst_gid; ++ __u32 yst_atime; ++ __u32 yst_mtime; ++ __u32 yst_ctime; ++#endif ++ ++ __u32 yst_rdev; ++ ++#ifdef __KERNEL__ ++ struct inode *myInode; ++ ++#endif ++ ++ yaffs_ObjectType variantType; ++ ++ yaffs_ObjectVariant variant; ++ ++}; ++ ++typedef struct yaffs_ObjectStruct yaffs_Object; ++ ++struct yaffs_ObjectList_struct { ++ yaffs_Object *objects; ++ struct yaffs_ObjectList_struct *next; ++}; ++ ++typedef struct yaffs_ObjectList_struct yaffs_ObjectList; ++ ++typedef struct { ++ struct ylist_head list; ++ int count; ++} yaffs_ObjectBucket; ++ ++ ++/* yaffs_CheckpointObject holds the definition of an object as dumped ++ * by checkpointing. ++ */ ++ ++typedef struct { ++ int structType; ++ __u32 objectId; ++ __u32 parentId; ++ int hdrChunk; ++ yaffs_ObjectType variantType:3; ++ __u8 deleted:1; ++ __u8 softDeleted:1; ++ __u8 unlinked:1; ++ __u8 fake:1; ++ __u8 renameAllowed:1; ++ __u8 unlinkAllowed:1; ++ __u8 serial; ++ ++ int nDataChunks; ++ __u32 fileSizeOrEquivalentObjectId; ++ ++}yaffs_CheckpointObject; ++ ++/*--------------------- Temporary buffers ---------------- ++ * ++ * These are chunk-sized working buffers. Each device has a few ++ */ ++ ++typedef struct { ++ __u8 *buffer; ++ int line; /* track from whence this buffer was allocated */ ++ int maxLine; ++} yaffs_TempBuffer; ++ ++/*----------------- Device ---------------------------------*/ ++ ++struct yaffs_DeviceStruct { ++ struct ylist_head devList; ++ const char *name; ++ ++ /* Entry parameters set up way early. Yaffs sets up the rest.*/ ++ int nDataBytesPerChunk; /* Should be a power of 2 >= 512 */ ++ int nChunksPerBlock; /* does not need to be a power of 2 */ ++ int spareBytesPerChunk;/* spare area size */ ++ int startBlock; /* Start block we're allowed to use */ ++ int endBlock; /* End block we're allowed to use */ ++ int nReservedBlocks; /* We want this tuneable so that we can reduce */ ++ /* reserved blocks on NOR and RAM. */ ++ ++ ++ /* Stuff used by the shared space checkpointing mechanism */ ++ /* If this value is zero, then this mechanism is disabled */ ++ ++// int nCheckpointReservedBlocks; /* Blocks to reserve for checkpoint data */ ++ ++ ++ ++ ++ int nShortOpCaches; /* If <= 0, then short op caching is disabled, else ++ * the number of short op caches (don't use too many) ++ */ ++ ++ int useHeaderFileSize; /* Flag to determine if we should use file sizes from the header */ ++ ++ int useNANDECC; /* Flag to decide whether or not to use NANDECC */ ++ ++ void *genericDevice; /* Pointer to device context ++ * On an mtd this holds the mtd pointer. ++ */ ++ void *superBlock; ++ ++ /* NAND access functions (Must be set before calling YAFFS)*/ ++ ++ int (*writeChunkToNAND) (struct yaffs_DeviceStruct * dev, ++ int chunkInNAND, const __u8 * data, ++ const yaffs_Spare * spare); ++ int (*readChunkFromNAND) (struct yaffs_DeviceStruct * dev, ++ int chunkInNAND, __u8 * data, ++ yaffs_Spare * spare); ++ int (*eraseBlockInNAND) (struct yaffs_DeviceStruct * dev, ++ int blockInNAND); ++ int (*initialiseNAND) (struct yaffs_DeviceStruct * dev); ++ int (*deinitialiseNAND) (struct yaffs_DeviceStruct * dev); ++ ++#ifdef CONFIG_YAFFS_YAFFS2 ++ int (*writeChunkWithTagsToNAND) (struct yaffs_DeviceStruct * dev, ++ int chunkInNAND, const __u8 * data, ++ const yaffs_ExtendedTags * tags); ++ int (*readChunkWithTagsFromNAND) (struct yaffs_DeviceStruct * dev, ++ int chunkInNAND, __u8 * data, ++ yaffs_ExtendedTags * tags); ++ int (*markNANDBlockBad) (struct yaffs_DeviceStruct * dev, int blockNo); ++ int (*queryNANDBlock) (struct yaffs_DeviceStruct * dev, int blockNo, ++ yaffs_BlockState * state, __u32 *sequenceNumber); ++#endif ++ ++ int isYaffs2; ++ ++ /* The removeObjectCallback function must be supplied by OS flavours that ++ * need it. The Linux kernel does not use this, but yaffs direct does use ++ * it to implement the faster readdir ++ */ ++ void (*removeObjectCallback)(struct yaffs_ObjectStruct *obj); ++ ++ /* Callback to mark the superblock dirsty */ ++ void (*markSuperBlockDirty)(void * superblock); ++ ++ int wideTnodesDisabled; /* Set to disable wide tnodes */ ++ ++ YCHAR *pathDividers; /* String of legal path dividers */ ++ ++ ++ /* End of stuff that must be set before initialisation. */ ++ ++ /* Checkpoint control. Can be set before or after initialisation */ ++ __u8 skipCheckpointRead; ++ __u8 skipCheckpointWrite; ++ ++ /* Runtime parameters. Set up by YAFFS. */ ++ ++ __u16 chunkGroupBits; /* 0 for devices <= 32MB. else log2(nchunks) - 16 */ ++ __u16 chunkGroupSize; /* == 2^^chunkGroupBits */ ++ ++ /* Stuff to support wide tnodes */ ++ __u32 tnodeWidth; ++ __u32 tnodeMask; ++ ++ /* Stuff for figuring out file offset to chunk conversions */ ++ __u32 chunkShift; /* Shift value */ ++ __u32 chunkDiv; /* Divisor after shifting: 1 for power-of-2 sizes */ ++ __u32 chunkMask; /* Mask to use for power-of-2 case */ ++ ++ /* Stuff to handle inband tags */ ++ int inbandTags; ++ __u32 totalBytesPerChunk; ++ ++#ifdef __KERNEL__ ++ ++ struct semaphore sem; /* Semaphore for waiting on erasure.*/ ++ struct semaphore grossLock; /* Gross locking semaphore */ ++ __u8 *spareBuffer; /* For mtdif2 use. Don't know the size of the buffer ++ * at compile time so we have to allocate it. ++ */ ++ void (*putSuperFunc) (struct super_block * sb); ++#endif ++ ++ int isMounted; ++ ++ int isCheckpointed; ++ ++ ++ /* Stuff to support block offsetting to support start block zero */ ++ int internalStartBlock; ++ int internalEndBlock; ++ int blockOffset; ++ int chunkOffset; ++ ++ ++ /* Runtime checkpointing stuff */ ++ int checkpointPageSequence; /* running sequence number of checkpoint pages */ ++ int checkpointByteCount; ++ int checkpointByteOffset; ++ __u8 *checkpointBuffer; ++ int checkpointOpenForWrite; ++ int blocksInCheckpoint; ++ int checkpointCurrentChunk; ++ int checkpointCurrentBlock; ++ int checkpointNextBlock; ++ int *checkpointBlockList; ++ int checkpointMaxBlocks; ++ __u32 checkpointSum; ++ __u32 checkpointXor; ++ ++ int nCheckpointBlocksRequired; /* Number of blocks needed to store current checkpoint set */ ++ ++ /* Block Info */ ++ yaffs_BlockInfo *blockInfo; ++ __u8 *chunkBits; /* bitmap of chunks in use */ ++ unsigned blockInfoAlt:1; /* was allocated using alternative strategy */ ++ unsigned chunkBitsAlt:1; /* was allocated using alternative strategy */ ++ int chunkBitmapStride; /* Number of bytes of chunkBits per block. ++ * Must be consistent with nChunksPerBlock. ++ */ ++ ++ int nErasedBlocks; ++ int allocationBlock; /* Current block being allocated off */ ++ __u32 allocationPage; ++ int allocationBlockFinder; /* Used to search for next allocation block */ ++ ++ /* Runtime state */ ++ int nTnodesCreated; ++ yaffs_Tnode *freeTnodes; ++ int nFreeTnodes; ++ yaffs_TnodeList *allocatedTnodeList; ++ ++ int isDoingGC; ++ int gcBlock; ++ int gcChunk; ++ ++ int nObjectsCreated; ++ yaffs_Object *freeObjects; ++ int nFreeObjects; ++ ++ int nHardLinks; ++ ++ yaffs_ObjectList *allocatedObjectList; ++ ++ yaffs_ObjectBucket objectBucket[YAFFS_NOBJECT_BUCKETS]; ++ ++ int nFreeChunks; ++ ++ int currentDirtyChecker; /* Used to find current dirtiest block */ ++ ++ __u32 *gcCleanupList; /* objects to delete at the end of a GC. */ ++ int nonAggressiveSkip; /* GC state/mode */ ++ ++ /* Statistcs */ ++ int nPageWrites; ++ int nPageReads; ++ int nBlockErasures; ++ int nErasureFailures; ++ int nGCCopies; ++ int garbageCollections; ++ int passiveGarbageCollections; ++ int nRetriedWrites; ++ int nRetiredBlocks; ++ int eccFixed; ++ int eccUnfixed; ++ int tagsEccFixed; ++ int tagsEccUnfixed; ++ int nDeletions; ++ int nUnmarkedDeletions; ++ ++ int hasPendingPrioritisedGCs; /* We think this device might have pending prioritised gcs */ ++ ++ /* Special directories */ ++ yaffs_Object *rootDir; ++ yaffs_Object *lostNFoundDir; ++ ++ /* Buffer areas for storing data to recover from write failures TODO ++ * __u8 bufferedData[YAFFS_CHUNKS_PER_BLOCK][YAFFS_BYTES_PER_CHUNK]; ++ * yaffs_Spare bufferedSpare[YAFFS_CHUNKS_PER_BLOCK]; ++ */ ++ ++ int bufferedBlock; /* Which block is buffered here? */ ++ int doingBufferedBlockRewrite; ++ ++ yaffs_ChunkCache *srCache; ++ int srLastUse; ++ ++ int cacheHits; ++ ++ /* Stuff for background deletion and unlinked files.*/ ++ yaffs_Object *unlinkedDir; /* Directory where unlinked and deleted files live. */ ++ yaffs_Object *deletedDir; /* Directory where deleted objects are sent to disappear. */ ++ yaffs_Object *unlinkedDeletion; /* Current file being background deleted.*/ ++ int nDeletedFiles; /* Count of files awaiting deletion;*/ ++ int nUnlinkedFiles; /* Count of unlinked files. */ ++ int nBackgroundDeletions; /* Count of background deletions. */ ++ ++ ++ /* Temporary buffer management */ ++ yaffs_TempBuffer tempBuffer[YAFFS_N_TEMP_BUFFERS]; ++ int maxTemp; ++ int tempInUse; ++ int unmanagedTempAllocations; ++ int unmanagedTempDeallocations; ++ ++ /* yaffs2 runtime stuff */ ++ unsigned sequenceNumber; /* Sequence number of currently allocating block */ ++ unsigned oldestDirtySequence; ++ ++}; ++ ++typedef struct yaffs_DeviceStruct yaffs_Device; ++ ++/* The static layout of block usage etc is stored in the super block header */ ++typedef struct { ++ int StructType; ++ int version; ++ int checkpointStartBlock; ++ int checkpointEndBlock; ++ int startBlock; ++ int endBlock; ++ int rfu[100]; ++} yaffs_SuperBlockHeader; ++ ++/* The CheckpointDevice structure holds the device information that changes at runtime and ++ * must be preserved over unmount/mount cycles. ++ */ ++typedef struct { ++ int structType; ++ int nErasedBlocks; ++ int allocationBlock; /* Current block being allocated off */ ++ __u32 allocationPage; ++ int nFreeChunks; ++ ++ int nDeletedFiles; /* Count of files awaiting deletion;*/ ++ int nUnlinkedFiles; /* Count of unlinked files. */ ++ int nBackgroundDeletions; /* Count of background deletions. */ ++ ++ /* yaffs2 runtime stuff */ ++ unsigned sequenceNumber; /* Sequence number of currently allocating block */ ++ unsigned oldestDirtySequence; ++ ++} yaffs_CheckpointDevice; ++ ++ ++typedef struct { ++ int structType; ++ __u32 magic; ++ __u32 version; ++ __u32 head; ++} yaffs_CheckpointValidity; ++ ++ ++/*----------------------- YAFFS Functions -----------------------*/ ++ ++int yaffs_GutsInitialise(yaffs_Device * dev); ++void yaffs_Deinitialise(yaffs_Device * dev); ++ ++int yaffs_GetNumberOfFreeChunks(yaffs_Device * dev); ++ ++int yaffs_RenameObject(yaffs_Object * oldDir, const YCHAR * oldName, ++ yaffs_Object * newDir, const YCHAR * newName); ++ ++int yaffs_Unlink(yaffs_Object * dir, const YCHAR * name); ++int yaffs_DeleteFile(yaffs_Object * obj); ++ ++int yaffs_GetObjectName(yaffs_Object * obj, YCHAR * name, int buffSize); ++int yaffs_GetObjectFileLength(yaffs_Object * obj); ++int yaffs_GetObjectInode(yaffs_Object * obj); ++unsigned yaffs_GetObjectType(yaffs_Object * obj); ++int yaffs_GetObjectLinkCount(yaffs_Object * obj); ++ ++int yaffs_SetAttributes(yaffs_Object * obj, struct iattr *attr); ++int yaffs_GetAttributes(yaffs_Object * obj, struct iattr *attr); ++ ++/* File operations */ ++int yaffs_ReadDataFromFile(yaffs_Object * obj, __u8 * buffer, loff_t offset, ++ int nBytes); ++int yaffs_WriteDataToFile(yaffs_Object * obj, const __u8 * buffer, loff_t offset, ++ int nBytes, int writeThrough); ++int yaffs_ResizeFile(yaffs_Object * obj, loff_t newSize); ++ ++yaffs_Object *yaffs_MknodFile(yaffs_Object * parent, const YCHAR * name, ++ __u32 mode, __u32 uid, __u32 gid); ++int yaffs_FlushFile(yaffs_Object * obj, int updateTime); ++ ++/* Flushing and checkpointing */ ++void yaffs_FlushEntireDeviceCache(yaffs_Device *dev); ++ ++int yaffs_CheckpointSave(yaffs_Device *dev); ++int yaffs_CheckpointRestore(yaffs_Device *dev); ++ ++/* Directory operations */ ++yaffs_Object *yaffs_MknodDirectory(yaffs_Object * parent, const YCHAR * name, ++ __u32 mode, __u32 uid, __u32 gid); ++yaffs_Object *yaffs_FindObjectByName(yaffs_Object * theDir, const YCHAR * name); ++int yaffs_ApplyToDirectoryChildren(yaffs_Object * theDir, ++ int (*fn) (yaffs_Object *)); ++ ++yaffs_Object *yaffs_FindObjectByNumber(yaffs_Device * dev, __u32 number); ++ ++/* Link operations */ ++yaffs_Object *yaffs_Link(yaffs_Object * parent, const YCHAR * name, ++ yaffs_Object * equivalentObject); ++ ++yaffs_Object *yaffs_GetEquivalentObject(yaffs_Object * obj); ++ ++/* Symlink operations */ ++yaffs_Object *yaffs_MknodSymLink(yaffs_Object * parent, const YCHAR * name, ++ __u32 mode, __u32 uid, __u32 gid, ++ const YCHAR * alias); ++YCHAR *yaffs_GetSymlinkAlias(yaffs_Object * obj); ++ ++/* Special inodes (fifos, sockets and devices) */ ++yaffs_Object *yaffs_MknodSpecial(yaffs_Object * parent, const YCHAR * name, ++ __u32 mode, __u32 uid, __u32 gid, __u32 rdev); ++ ++/* Special directories */ ++yaffs_Object *yaffs_Root(yaffs_Device * dev); ++yaffs_Object *yaffs_LostNFound(yaffs_Device * dev); ++ ++#ifdef CONFIG_YAFFS_WINCE ++/* CONFIG_YAFFS_WINCE special stuff */ ++void yfsd_WinFileTimeNow(__u32 target[2]); ++#endif ++ ++#ifdef __KERNEL__ ++ ++void yaffs_HandleDeferedFree(yaffs_Object * obj); ++#endif ++ ++/* Debug dump */ ++int yaffs_DumpObject(yaffs_Object * obj); ++ ++void yaffs_GutsTest(yaffs_Device * dev); ++ ++/* A few useful functions */ ++void yaffs_InitialiseTags(yaffs_ExtendedTags * tags); ++void yaffs_DeleteChunk(yaffs_Device * dev, int chunkId, int markNAND, int lyn); ++int yaffs_CheckFF(__u8 * buffer, int nBytes); ++void yaffs_HandleChunkError(yaffs_Device *dev, yaffs_BlockInfo *bi); ++ ++__u8 *yaffs_GetTempBuffer(yaffs_Device * dev, int lineNo); ++void yaffs_ReleaseTempBuffer(yaffs_Device * dev, __u8 * buffer, int lineNo); ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_mtdif.c linux-2.6.28.6/fs/yaffs2/yaffs_mtdif.c +--- linux-2.6.28/fs/yaffs2/yaffs_mtdif.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_mtdif.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,241 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++const char *yaffs_mtdif_c_version = ++ "$Id: yaffs_mtdif.c,v 1.21 2007/12/13 15:35:18 wookey Exp $"; ++ ++#include "yportenv.h" ++ ++ ++#include "yaffs_mtdif.h" ++ ++#include "linux/mtd/mtd.h" ++#include "linux/types.h" ++#include "linux/time.h" ++#include "linux/mtd/nand.h" ++ ++#if (MTD_VERSION_CODE < MTD_VERSION(2,6,18)) ++static struct nand_oobinfo yaffs_oobinfo = { ++ .useecc = 1, ++ .eccbytes = 6, ++ .eccpos = {8, 9, 10, 13, 14, 15} ++}; ++ ++static struct nand_oobinfo yaffs_noeccinfo = { ++ .useecc = 0, ++}; ++#endif ++ ++#if (MTD_VERSION_CODE > MTD_VERSION(2,6,17)) ++static inline void translate_spare2oob(const yaffs_Spare *spare, __u8 *oob) ++{ ++ oob[0] = spare->tagByte0; ++ oob[1] = spare->tagByte1; ++ oob[2] = spare->tagByte2; ++ oob[3] = spare->tagByte3; ++ oob[4] = spare->tagByte4; ++ oob[5] = spare->tagByte5 & 0x3f; ++ oob[5] |= spare->blockStatus == 'Y' ? 0: 0x80; ++ oob[5] |= spare->pageStatus == 0 ? 0: 0x40; ++ oob[6] = spare->tagByte6; ++ oob[7] = spare->tagByte7; ++} ++ ++static inline void translate_oob2spare(yaffs_Spare *spare, __u8 *oob) ++{ ++ struct yaffs_NANDSpare *nspare = (struct yaffs_NANDSpare *)spare; ++ spare->tagByte0 = oob[0]; ++ spare->tagByte1 = oob[1]; ++ spare->tagByte2 = oob[2]; ++ spare->tagByte3 = oob[3]; ++ spare->tagByte4 = oob[4]; ++ spare->tagByte5 = oob[5] == 0xff ? 0xff : oob[5] & 0x3f; ++ spare->blockStatus = oob[5] & 0x80 ? 0xff : 'Y'; ++ spare->pageStatus = oob[5] & 0x40 ? 0xff : 0; ++ spare->ecc1[0] = spare->ecc1[1] = spare->ecc1[2] = 0xff; ++ spare->tagByte6 = oob[6]; ++ spare->tagByte7 = oob[7]; ++ spare->ecc2[0] = spare->ecc2[1] = spare->ecc2[2] = 0xff; ++ ++ nspare->eccres1 = nspare->eccres2 = 0; /* FIXME */ ++} ++#endif ++ ++int nandmtd_WriteChunkToNAND(yaffs_Device * dev, int chunkInNAND, ++ const __u8 * data, const yaffs_Spare * spare) ++{ ++ struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice); ++#if (MTD_VERSION_CODE > MTD_VERSION(2,6,17)) ++ struct mtd_oob_ops ops; ++#endif ++ size_t dummy; ++ int retval = 0; ++ ++ loff_t addr = ((loff_t) chunkInNAND) * dev->nDataBytesPerChunk; ++#if (MTD_VERSION_CODE > MTD_VERSION(2,6,17)) ++ __u8 spareAsBytes[8]; /* OOB */ ++ ++ if (data && !spare) ++ retval = mtd->write(mtd, addr, dev->nDataBytesPerChunk, ++ &dummy, data); ++ else if (spare) { ++ if (dev->useNANDECC) { ++ translate_spare2oob(spare, spareAsBytes); ++ ops.mode = MTD_OOB_AUTO; ++ ops.ooblen = 8; /* temp hack */ ++ } else { ++ ops.mode = MTD_OOB_RAW; ++ ops.ooblen = YAFFS_BYTES_PER_SPARE; ++ } ++ ops.len = data ? dev->nDataBytesPerChunk : ops.ooblen; ++ ops.datbuf = (u8 *)data; ++ ops.ooboffs = 0; ++ ops.oobbuf = spareAsBytes; ++ retval = mtd->write_oob(mtd, addr, &ops); ++ } ++#else ++ __u8 *spareAsBytes = (__u8 *) spare; ++ ++ if (data && spare) { ++ if (dev->useNANDECC) ++ retval = ++ mtd->write_ecc(mtd, addr, dev->nDataBytesPerChunk, ++ &dummy, data, spareAsBytes, ++ &yaffs_oobinfo); ++ else ++ retval = ++ mtd->write_ecc(mtd, addr, dev->nDataBytesPerChunk, ++ &dummy, data, spareAsBytes, ++ &yaffs_noeccinfo); ++ } else { ++ if (data) ++ retval = ++ mtd->write(mtd, addr, dev->nDataBytesPerChunk, &dummy, ++ data); ++ if (spare) ++ retval = ++ mtd->write_oob(mtd, addr, YAFFS_BYTES_PER_SPARE, ++ &dummy, spareAsBytes); ++ } ++#endif ++ ++ if (retval == 0) ++ return YAFFS_OK; ++ else ++ return YAFFS_FAIL; ++} ++ ++int nandmtd_ReadChunkFromNAND(yaffs_Device * dev, int chunkInNAND, __u8 * data, ++ yaffs_Spare * spare) ++{ ++ struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice); ++#if (MTD_VERSION_CODE > MTD_VERSION(2,6,17)) ++ struct mtd_oob_ops ops; ++#endif ++ size_t dummy; ++ int retval = 0; ++ ++ loff_t addr = ((loff_t) chunkInNAND) * dev->nDataBytesPerChunk; ++#if (MTD_VERSION_CODE > MTD_VERSION(2,6,17)) ++ __u8 spareAsBytes[8]; /* OOB */ ++ ++ if (data && !spare) ++ retval = mtd->read(mtd, addr, dev->nDataBytesPerChunk, ++ &dummy, data); ++ else if (spare) { ++ if (dev->useNANDECC) { ++ ops.mode = MTD_OOB_AUTO; ++ ops.ooblen = 8; /* temp hack */ ++ } else { ++ ops.mode = MTD_OOB_RAW; ++ ops.ooblen = YAFFS_BYTES_PER_SPARE; ++ } ++ ops.len = data ? dev->nDataBytesPerChunk : ops.ooblen; ++ ops.datbuf = data; ++ ops.ooboffs = 0; ++ ops.oobbuf = spareAsBytes; ++ retval = mtd->read_oob(mtd, addr, &ops); ++ if (dev->useNANDECC) ++ translate_oob2spare(spare, spareAsBytes); ++ } ++#else ++ __u8 *spareAsBytes = (__u8 *) spare; ++ ++ if (data && spare) { ++ if (dev->useNANDECC) { ++ /* Careful, this call adds 2 ints */ ++ /* to the end of the spare data. Calling function */ ++ /* should allocate enough memory for spare, */ ++ /* i.e. [YAFFS_BYTES_PER_SPARE+2*sizeof(int)]. */ ++ retval = ++ mtd->read_ecc(mtd, addr, dev->nDataBytesPerChunk, ++ &dummy, data, spareAsBytes, ++ &yaffs_oobinfo); ++ } else { ++ retval = ++ mtd->read_ecc(mtd, addr, dev->nDataBytesPerChunk, ++ &dummy, data, spareAsBytes, ++ &yaffs_noeccinfo); ++ } ++ } else { ++ if (data) ++ retval = ++ mtd->read(mtd, addr, dev->nDataBytesPerChunk, &dummy, ++ data); ++ if (spare) ++ retval = ++ mtd->read_oob(mtd, addr, YAFFS_BYTES_PER_SPARE, ++ &dummy, spareAsBytes); ++ } ++#endif ++ ++ if (retval == 0) ++ return YAFFS_OK; ++ else ++ return YAFFS_FAIL; ++} ++ ++int nandmtd_EraseBlockInNAND(yaffs_Device * dev, int blockNumber) ++{ ++ struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice); ++ __u32 addr = ++ ((loff_t) blockNumber) * dev->nDataBytesPerChunk ++ * dev->nChunksPerBlock; ++ struct erase_info ei; ++ int retval = 0; ++ ++ ei.mtd = mtd; ++ ei.addr = addr; ++ ei.len = dev->nDataBytesPerChunk * dev->nChunksPerBlock; ++ ei.time = 1000; ++ ei.retries = 2; ++ ei.callback = NULL; ++ ei.priv = (u_long) dev; ++ ++ /* Todo finish off the ei if required */ ++ ++ sema_init(&dev->sem, 0); ++ ++ retval = mtd->erase(mtd, &ei); ++ ++ if (retval == 0) ++ return YAFFS_OK; ++ else ++ return YAFFS_FAIL; ++} ++ ++int nandmtd_InitialiseNAND(yaffs_Device * dev) ++{ ++ return YAFFS_OK; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_mtdif.h linux-2.6.28.6/fs/yaffs2/yaffs_mtdif.h +--- linux-2.6.28/fs/yaffs2/yaffs_mtdif.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_mtdif.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,32 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_MTDIF_H__ ++#define __YAFFS_MTDIF_H__ ++ ++#include "yaffs_guts.h" ++ ++#if (MTD_VERSION_CODE < MTD_VERSION(2,6,18)) ++extern struct nand_oobinfo yaffs_oobinfo; ++extern struct nand_oobinfo yaffs_noeccinfo; ++#endif ++ ++int nandmtd_WriteChunkToNAND(yaffs_Device * dev, int chunkInNAND, ++ const __u8 * data, const yaffs_Spare * spare); ++int nandmtd_ReadChunkFromNAND(yaffs_Device * dev, int chunkInNAND, __u8 * data, ++ yaffs_Spare * spare); ++int nandmtd_EraseBlockInNAND(yaffs_Device * dev, int blockNumber); ++int nandmtd_InitialiseNAND(yaffs_Device * dev); ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_mtdif1.c linux-2.6.28.6/fs/yaffs2/yaffs_mtdif1.c +--- linux-2.6.28/fs/yaffs2/yaffs_mtdif1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_mtdif1.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,369 @@ ++/* ++ * YAFFS: Yet another FFS. A NAND-flash specific file system. ++ * yaffs_mtdif1.c NAND mtd interface functions for small-page NAND. ++ * ++ * Copyright (C) 2002 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++/* ++ * This module provides the interface between yaffs_nand.c and the ++ * MTD API. This version is used when the MTD interface supports the ++ * 'mtd_oob_ops' style calls to read_oob and write_oob, circa 2.6.17, ++ * and we have small-page NAND device. ++ * ++ * These functions are invoked via function pointers in yaffs_nand.c. ++ * This replaces functionality provided by functions in yaffs_mtdif.c ++ * and the yaffs_TagsCompatability functions in yaffs_tagscompat.c that are ++ * called in yaffs_mtdif.c when the function pointers are NULL. ++ * We assume the MTD layer is performing ECC (useNANDECC is true). ++ */ ++ ++#include "yportenv.h" ++#include "yaffs_guts.h" ++#include "yaffs_packedtags1.h" ++#include "yaffs_tagscompat.h" // for yaffs_CalcTagsECC ++ ++#include "linux/kernel.h" ++#include "linux/version.h" ++#include "linux/types.h" ++#include "linux/mtd/mtd.h" ++ ++/* Don't compile this module if we don't have MTD's mtd_oob_ops interface */ ++#if (MTD_VERSION_CODE > MTD_VERSION(2,6,17)) ++ ++const char *yaffs_mtdif1_c_version = "$Id: yaffs_mtdif1.c,v 1.8 2008/07/23 03:35:12 charles Exp $"; ++ ++#ifndef CONFIG_YAFFS_9BYTE_TAGS ++# define YTAG1_SIZE 8 ++#else ++# define YTAG1_SIZE 9 ++#endif ++ ++#if 0 ++/* Use the following nand_ecclayout with MTD when using ++ * CONFIG_YAFFS_9BYTE_TAGS and the older on-NAND tags layout. ++ * If you have existing Yaffs images and the byte order differs from this, ++ * adjust 'oobfree' to match your existing Yaffs data. ++ * ++ * This nand_ecclayout scatters/gathers to/from the old-yaffs layout with the ++ * pageStatus byte (at NAND spare offset 4) scattered/gathered from/to ++ * the 9th byte. ++ * ++ * Old-style on-NAND format: T0,T1,T2,T3,P,B,T4,T5,E0,E1,E2,T6,T7,E3,E4,E5 ++ * We have/need PackedTags1 plus pageStatus: T0,T1,T2,T3,T4,T5,T6,T7,P ++ * where Tn are the tag bytes, En are MTD's ECC bytes, P is the pageStatus ++ * byte and B is the small-page bad-block indicator byte. ++ */ ++static struct nand_ecclayout nand_oob_16 = { ++ .eccbytes = 6, ++ .eccpos = { 8, 9, 10, 13, 14, 15 }, ++ .oobavail = 9, ++ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } ++}; ++#endif ++ ++/* Write a chunk (page) of data to NAND. ++ * ++ * Caller always provides ExtendedTags data which are converted to a more ++ * compact (packed) form for storage in NAND. A mini-ECC runs over the ++ * contents of the tags meta-data; used to valid the tags when read. ++ * ++ * - Pack ExtendedTags to PackedTags1 form ++ * - Compute mini-ECC for PackedTags1 ++ * - Write data and packed tags to NAND. ++ * ++ * Note: Due to the use of the PackedTags1 meta-data which does not include ++ * a full sequence number (as found in the larger PackedTags2 form) it is ++ * necessary for Yaffs to re-write a chunk/page (just once) to mark it as ++ * discarded and dirty. This is not ideal: newer NAND parts are supposed ++ * to be written just once. When Yaffs performs this operation, this ++ * function is called with a NULL data pointer -- calling MTD write_oob ++ * without data is valid usage (2.6.17). ++ * ++ * Any underlying MTD error results in YAFFS_FAIL. ++ * Returns YAFFS_OK or YAFFS_FAIL. ++ */ ++int nandmtd1_WriteChunkWithTagsToNAND(yaffs_Device *dev, ++ int chunkInNAND, const __u8 * data, const yaffs_ExtendedTags * etags) ++{ ++ struct mtd_info * mtd = dev->genericDevice; ++ int chunkBytes = dev->nDataBytesPerChunk; ++ loff_t addr = ((loff_t)chunkInNAND) * chunkBytes; ++ struct mtd_oob_ops ops; ++ yaffs_PackedTags1 pt1; ++ int retval; ++ ++ /* we assume that PackedTags1 and yaffs_Tags are compatible */ ++ compile_time_assertion(sizeof(yaffs_PackedTags1) == 12); ++ compile_time_assertion(sizeof(yaffs_Tags) == 8); ++ ++ dev->nPageWrites++; ++ ++ yaffs_PackTags1(&pt1, etags); ++ yaffs_CalcTagsECC((yaffs_Tags *)&pt1); ++ ++ /* When deleting a chunk, the upper layer provides only skeletal ++ * etags, one with chunkDeleted set. However, we need to update the ++ * tags, not erase them completely. So we use the NAND write property ++ * that only zeroed-bits stick and set tag bytes to all-ones and ++ * zero just the (not) deleted bit. ++ */ ++#ifndef CONFIG_YAFFS_9BYTE_TAGS ++ if (etags->chunkDeleted) { ++ memset(&pt1, 0xff, 8); ++ /* clear delete status bit to indicate deleted */ ++ pt1.deleted = 0; ++ } ++#else ++ ((__u8 *)&pt1)[8] = 0xff; ++ if (etags->chunkDeleted) { ++ memset(&pt1, 0xff, 8); ++ /* zero pageStatus byte to indicate deleted */ ++ ((__u8 *)&pt1)[8] = 0; ++ } ++#endif ++ ++ memset(&ops, 0, sizeof(ops)); ++ ops.mode = MTD_OOB_AUTO; ++ ops.len = (data) ? chunkBytes : 0; ++ ops.ooblen = YTAG1_SIZE; ++ ops.datbuf = (__u8 *)data; ++ ops.oobbuf = (__u8 *)&pt1; ++ ++ retval = mtd->write_oob(mtd, addr, &ops); ++ if (retval) { ++ yaffs_trace(YAFFS_TRACE_MTD, ++ "write_oob failed, chunk %d, mtd error %d\n", ++ chunkInNAND, retval); ++ } ++ return retval ? YAFFS_FAIL : YAFFS_OK; ++} ++ ++/* Return with empty ExtendedTags but add eccResult. ++ */ ++static int rettags(yaffs_ExtendedTags * etags, int eccResult, int retval) ++{ ++ if (etags) { ++ memset(etags, 0, sizeof(*etags)); ++ etags->eccResult = eccResult; ++ } ++ return retval; ++} ++ ++/* Read a chunk (page) from NAND. ++ * ++ * Caller expects ExtendedTags data to be usable even on error; that is, ++ * all members except eccResult and blockBad are zeroed. ++ * ++ * - Check ECC results for data (if applicable) ++ * - Check for blank/erased block (return empty ExtendedTags if blank) ++ * - Check the PackedTags1 mini-ECC (correct if necessary/possible) ++ * - Convert PackedTags1 to ExtendedTags ++ * - Update eccResult and blockBad members to refect state. ++ * ++ * Returns YAFFS_OK or YAFFS_FAIL. ++ */ ++int nandmtd1_ReadChunkWithTagsFromNAND(yaffs_Device *dev, ++ int chunkInNAND, __u8 * data, yaffs_ExtendedTags * etags) ++{ ++ struct mtd_info * mtd = dev->genericDevice; ++ int chunkBytes = dev->nDataBytesPerChunk; ++ loff_t addr = ((loff_t)chunkInNAND) * chunkBytes; ++ int eccres = YAFFS_ECC_RESULT_NO_ERROR; ++ struct mtd_oob_ops ops; ++ yaffs_PackedTags1 pt1; ++ int retval; ++ int deleted; ++ ++ dev->nPageReads++; ++ ++ memset(&ops, 0, sizeof(ops)); ++ ops.mode = MTD_OOB_AUTO; ++ ops.len = (data) ? chunkBytes : 0; ++ ops.ooblen = YTAG1_SIZE; ++ ops.datbuf = data; ++ ops.oobbuf = (__u8 *)&pt1; ++ ++#if (MTD_VERSION_CODE < MTD_VERSION(2,6,20)) ++ /* In MTD 2.6.18 to 2.6.19 nand_base.c:nand_do_read_oob() has a bug; ++ * help it out with ops.len = ops.ooblen when ops.datbuf == NULL. ++ */ ++ ops.len = (ops.datbuf) ? ops.len : ops.ooblen; ++#endif ++ /* Read page and oob using MTD. ++ * Check status and determine ECC result. ++ */ ++ retval = mtd->read_oob(mtd, addr, &ops); ++ if (retval) { ++ yaffs_trace(YAFFS_TRACE_MTD, ++ "read_oob failed, chunk %d, mtd error %d\n", ++ chunkInNAND, retval); ++ } ++ ++ switch (retval) { ++ case 0: ++ /* no error */ ++ break; ++ ++ case -EUCLEAN: ++ /* MTD's ECC fixed the data */ ++ eccres = YAFFS_ECC_RESULT_FIXED; ++ dev->eccFixed++; ++ break; ++ ++ case -EBADMSG: ++ /* MTD's ECC could not fix the data */ ++ dev->eccUnfixed++; ++ /* fall into... */ ++ default: ++ rettags(etags, YAFFS_ECC_RESULT_UNFIXED, 0); ++ etags->blockBad = (mtd->block_isbad)(mtd, addr); ++ return YAFFS_FAIL; ++ } ++ ++ /* Check for a blank/erased chunk. ++ */ ++ if (yaffs_CheckFF((__u8 *)&pt1, 8)) { ++ /* when blank, upper layers want eccResult to be <= NO_ERROR */ ++ return rettags(etags, YAFFS_ECC_RESULT_NO_ERROR, YAFFS_OK); ++ } ++ ++#ifndef CONFIG_YAFFS_9BYTE_TAGS ++ /* Read deleted status (bit) then return it to it's non-deleted ++ * state before performing tags mini-ECC check. pt1.deleted is ++ * inverted. ++ */ ++ deleted = !pt1.deleted; ++ pt1.deleted = 1; ++#else ++ deleted = (yaffs_CountBits(((__u8 *)&pt1)[8]) < 7); ++#endif ++ ++ /* Check the packed tags mini-ECC and correct if necessary/possible. ++ */ ++ retval = yaffs_CheckECCOnTags((yaffs_Tags *)&pt1); ++ switch (retval) { ++ case 0: ++ /* no tags error, use MTD result */ ++ break; ++ case 1: ++ /* recovered tags-ECC error */ ++ dev->tagsEccFixed++; ++ if (eccres == YAFFS_ECC_RESULT_NO_ERROR) ++ eccres = YAFFS_ECC_RESULT_FIXED; ++ break; ++ default: ++ /* unrecovered tags-ECC error */ ++ dev->tagsEccUnfixed++; ++ return rettags(etags, YAFFS_ECC_RESULT_UNFIXED, YAFFS_FAIL); ++ } ++ ++ /* Unpack the tags to extended form and set ECC result. ++ * [set shouldBeFF just to keep yaffs_UnpackTags1 happy] ++ */ ++ pt1.shouldBeFF = 0xFFFFFFFF; ++ yaffs_UnpackTags1(etags, &pt1); ++ etags->eccResult = eccres; ++ ++ /* Set deleted state */ ++ etags->chunkDeleted = deleted; ++ return YAFFS_OK; ++} ++ ++/* Mark a block bad. ++ * ++ * This is a persistant state. ++ * Use of this function should be rare. ++ * ++ * Returns YAFFS_OK or YAFFS_FAIL. ++ */ ++int nandmtd1_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo) ++{ ++ struct mtd_info * mtd = dev->genericDevice; ++ int blocksize = dev->nChunksPerBlock * dev->nDataBytesPerChunk; ++ int retval; ++ ++ yaffs_trace(YAFFS_TRACE_BAD_BLOCKS, "marking block %d bad\n", blockNo); ++ ++ retval = mtd->block_markbad(mtd, (loff_t)blocksize * blockNo); ++ return (retval) ? YAFFS_FAIL : YAFFS_OK; ++} ++ ++/* Check any MTD prerequists. ++ * ++ * Returns YAFFS_OK or YAFFS_FAIL. ++ */ ++static int nandmtd1_TestPrerequists(struct mtd_info * mtd) ++{ ++ /* 2.6.18 has mtd->ecclayout->oobavail */ ++ /* 2.6.21 has mtd->ecclayout->oobavail and mtd->oobavail */ ++ int oobavail = mtd->ecclayout->oobavail; ++ ++ if (oobavail < YTAG1_SIZE) { ++ yaffs_trace(YAFFS_TRACE_ERROR, ++ "mtd device has only %d bytes for tags, need %d\n", ++ oobavail, YTAG1_SIZE); ++ return YAFFS_FAIL; ++ } ++ return YAFFS_OK; ++} ++ ++/* Query for the current state of a specific block. ++ * ++ * Examine the tags of the first chunk of the block and return the state: ++ * - YAFFS_BLOCK_STATE_DEAD, the block is marked bad ++ * - YAFFS_BLOCK_STATE_NEEDS_SCANNING, the block is in use ++ * - YAFFS_BLOCK_STATE_EMPTY, the block is clean ++ * ++ * Always returns YAFFS_OK. ++ */ ++int nandmtd1_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo, ++ yaffs_BlockState * pState, __u32 *pSequenceNumber) ++{ ++ struct mtd_info * mtd = dev->genericDevice; ++ int chunkNo = blockNo * dev->nChunksPerBlock; ++ loff_t addr = (loff_t)chunkNo * dev->nDataBytesPerChunk; ++ yaffs_ExtendedTags etags; ++ int state = YAFFS_BLOCK_STATE_DEAD; ++ int seqnum = 0; ++ int retval; ++ ++ /* We don't yet have a good place to test for MTD config prerequists. ++ * Do it here as we are called during the initial scan. ++ */ ++ if (nandmtd1_TestPrerequists(mtd) != YAFFS_OK) { ++ return YAFFS_FAIL; ++ } ++ ++ retval = nandmtd1_ReadChunkWithTagsFromNAND(dev, chunkNo, NULL, &etags); ++ etags.blockBad = (mtd->block_isbad)(mtd, addr); ++ if (etags.blockBad) { ++ yaffs_trace(YAFFS_TRACE_BAD_BLOCKS, ++ "block %d is marked bad\n", blockNo); ++ state = YAFFS_BLOCK_STATE_DEAD; ++ } ++ else if (etags.eccResult != YAFFS_ECC_RESULT_NO_ERROR) { ++ /* bad tags, need to look more closely */ ++ state = YAFFS_BLOCK_STATE_NEEDS_SCANNING; ++ } ++ else if (etags.chunkUsed) { ++ state = YAFFS_BLOCK_STATE_NEEDS_SCANNING; ++ seqnum = etags.sequenceNumber; ++ } ++ else { ++ state = YAFFS_BLOCK_STATE_EMPTY; ++ } ++ ++ *pState = state; ++ *pSequenceNumber = seqnum; ++ ++ /* query always succeeds */ ++ return YAFFS_OK; ++} ++ ++#endif /*MTD_VERSION*/ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_mtdif1.h linux-2.6.28.6/fs/yaffs2/yaffs_mtdif1.h +--- linux-2.6.28/fs/yaffs2/yaffs_mtdif1.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_mtdif1.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,28 @@ ++/* ++ * YAFFS: Yet another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_MTDIF1_H__ ++#define __YAFFS_MTDIF1_H__ ++ ++int nandmtd1_WriteChunkWithTagsToNAND(yaffs_Device * dev, int chunkInNAND, ++ const __u8 * data, const yaffs_ExtendedTags * tags); ++ ++int nandmtd1_ReadChunkWithTagsFromNAND(yaffs_Device * dev, int chunkInNAND, ++ __u8 * data, yaffs_ExtendedTags * tags); ++ ++int nandmtd1_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo); ++ ++int nandmtd1_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo, ++ yaffs_BlockState * state, __u32 *sequenceNumber); ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_mtdif2.c linux-2.6.28.6/fs/yaffs2/yaffs_mtdif2.c +--- linux-2.6.28/fs/yaffs2/yaffs_mtdif2.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_mtdif2.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,248 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++/* mtd interface for YAFFS2 */ ++ ++const char *yaffs_mtdif2_c_version = ++ "$Id: yaffs_mtdif2.c,v 1.22 2008/11/02 22:47:13 charles Exp $"; ++ ++#include "yportenv.h" ++ ++ ++#include "yaffs_mtdif2.h" ++ ++#include "linux/mtd/mtd.h" ++#include "linux/types.h" ++#include "linux/time.h" ++ ++#include "yaffs_packedtags2.h" ++ ++/* NB For use with inband tags.... ++ * We assume that the data buffer is of size totalBytersPerChunk so that we can also ++ * use it to load the tags. ++ */ ++int nandmtd2_WriteChunkWithTagsToNAND(yaffs_Device * dev, int chunkInNAND, ++ const __u8 * data, ++ const yaffs_ExtendedTags * tags) ++{ ++ struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice); ++#if (MTD_VERSION_CODE > MTD_VERSION(2,6,17)) ++ struct mtd_oob_ops ops; ++#else ++ size_t dummy; ++#endif ++ int retval = 0; ++ ++ loff_t addr; ++ ++ yaffs_PackedTags2 pt; ++ ++ T(YAFFS_TRACE_MTD, ++ (TSTR ++ ("nandmtd2_WriteChunkWithTagsToNAND chunk %d data %p tags %p" ++ TENDSTR), chunkInNAND, data, tags)); ++ ++ ++ addr = ((loff_t) chunkInNAND) * dev->totalBytesPerChunk; ++ ++ /* For yaffs2 writing there must be both data and tags. ++ * If we're using inband tags, then the tags are stuffed into ++ * the end of the data buffer. ++ */ ++ if(!data || !tags) ++ BUG(); ++ else if(dev->inbandTags){ ++ yaffs_PackedTags2TagsPart *pt2tp; ++ pt2tp = (yaffs_PackedTags2TagsPart *)(data + dev->nDataBytesPerChunk); ++ yaffs_PackTags2TagsPart(pt2tp,tags); ++ } ++ else ++ yaffs_PackTags2(&pt, tags); ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17)) ++ ops.mode = MTD_OOB_AUTO; ++ ops.ooblen = (dev->inbandTags) ? 0 : sizeof(pt); ++ ops.len = dev->totalBytesPerChunk; ++ ops.ooboffs = 0; ++ ops.datbuf = (__u8 *)data; ++ ops.oobbuf = (dev->inbandTags) ? NULL : (void *)&pt; ++ retval = mtd->write_oob(mtd, addr, &ops); ++ ++#else ++ if (!dev->inbandTags) { ++ retval = ++ mtd->write_ecc(mtd, addr, dev->nDataBytesPerChunk, ++ &dummy, data, (__u8 *) & pt, NULL); ++ } else { ++ retval = ++ mtd->write(mtd, addr, dev->totalBytesPerChunk, &dummy, ++ data); ++ } ++#endif ++ ++ if (retval == 0) ++ return YAFFS_OK; ++ else ++ return YAFFS_FAIL; ++} ++ ++int nandmtd2_ReadChunkWithTagsFromNAND(yaffs_Device * dev, int chunkInNAND, ++ __u8 * data, yaffs_ExtendedTags * tags) ++{ ++ struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice); ++#if (MTD_VERSION_CODE > MTD_VERSION(2,6,17)) ++ struct mtd_oob_ops ops; ++#endif ++ size_t dummy; ++ int retval = 0; ++ int localData = 0; ++ ++ loff_t addr = ((loff_t) chunkInNAND) * dev->totalBytesPerChunk; ++ ++ yaffs_PackedTags2 pt; ++ ++ T(YAFFS_TRACE_MTD, ++ (TSTR ++ ("nandmtd2_ReadChunkWithTagsFromNAND chunk %d data %p tags %p" ++ TENDSTR), chunkInNAND, data, tags)); ++ ++ if(dev->inbandTags){ ++ ++ if(!data) { ++ localData = 1; ++ data = yaffs_GetTempBuffer(dev,__LINE__); ++ } ++ ++ ++ } ++ ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17)) ++ if (dev->inbandTags || (data && !tags)) ++ retval = mtd->read(mtd, addr, dev->totalBytesPerChunk, ++ &dummy, data); ++ else if (tags) { ++ ops.mode = MTD_OOB_AUTO; ++ ops.ooblen = sizeof(pt); ++ ops.len = data ? dev->nDataBytesPerChunk : sizeof(pt); ++ ops.ooboffs = 0; ++ ops.datbuf = data; ++ ops.oobbuf = dev->spareBuffer; ++ retval = mtd->read_oob(mtd, addr, &ops); ++ } ++#else ++ if (!dev->inbandTags && data && tags) { ++ ++ retval = mtd->read_ecc(mtd, addr, dev->nDataBytesPerChunk, ++ &dummy, data, dev->spareBuffer, ++ NULL); ++ } else { ++ if (data) ++ retval = ++ mtd->read(mtd, addr, dev->nDataBytesPerChunk, &dummy, ++ data); ++ if (!dev->inbandTags && tags) ++ retval = ++ mtd->read_oob(mtd, addr, mtd->oobsize, &dummy, ++ dev->spareBuffer); ++ } ++#endif ++ ++ ++ if(dev->inbandTags){ ++ if(tags){ ++ yaffs_PackedTags2TagsPart * pt2tp; ++ pt2tp = (yaffs_PackedTags2TagsPart *)&data[dev->nDataBytesPerChunk]; ++ yaffs_UnpackTags2TagsPart(tags,pt2tp); ++ } ++ } ++ else { ++ if (tags){ ++ memcpy(&pt, dev->spareBuffer, sizeof(pt)); ++ yaffs_UnpackTags2(tags, &pt); ++ } ++ } ++ ++ if(localData) ++ yaffs_ReleaseTempBuffer(dev,data,__LINE__); ++ ++ if(tags && retval == -EBADMSG && tags->eccResult == YAFFS_ECC_RESULT_NO_ERROR) ++ tags->eccResult = YAFFS_ECC_RESULT_UNFIXED; ++ if (retval == 0) ++ return YAFFS_OK; ++ else ++ return YAFFS_FAIL; ++} ++ ++int nandmtd2_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo) ++{ ++ struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice); ++ int retval; ++ T(YAFFS_TRACE_MTD, ++ (TSTR("nandmtd2_MarkNANDBlockBad %d" TENDSTR), blockNo)); ++ ++ retval = ++ mtd->block_markbad(mtd, ++ blockNo * dev->nChunksPerBlock * ++ dev->totalBytesPerChunk); ++ ++ if (retval == 0) ++ return YAFFS_OK; ++ else ++ return YAFFS_FAIL; ++ ++} ++ ++int nandmtd2_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo, ++ yaffs_BlockState * state, __u32 *sequenceNumber) ++{ ++ struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice); ++ int retval; ++ ++ T(YAFFS_TRACE_MTD, ++ (TSTR("nandmtd2_QueryNANDBlock %d" TENDSTR), blockNo)); ++ retval = ++ mtd->block_isbad(mtd, ++ blockNo * dev->nChunksPerBlock * ++ dev->totalBytesPerChunk); ++ ++ if (retval) { ++ T(YAFFS_TRACE_MTD, (TSTR("block is bad" TENDSTR))); ++ ++ *state = YAFFS_BLOCK_STATE_DEAD; ++ *sequenceNumber = 0; ++ } else { ++ yaffs_ExtendedTags t; ++ nandmtd2_ReadChunkWithTagsFromNAND(dev, ++ blockNo * ++ dev->nChunksPerBlock, NULL, ++ &t); ++ ++ if (t.chunkUsed) { ++ *sequenceNumber = t.sequenceNumber; ++ *state = YAFFS_BLOCK_STATE_NEEDS_SCANNING; ++ } else { ++ *sequenceNumber = 0; ++ *state = YAFFS_BLOCK_STATE_EMPTY; ++ } ++ } ++ T(YAFFS_TRACE_MTD, ++ (TSTR("block is bad seq %d state %d" TENDSTR), *sequenceNumber, ++ *state)); ++ ++ if (retval == 0) ++ return YAFFS_OK; ++ else ++ return YAFFS_FAIL; ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_mtdif2.h linux-2.6.28.6/fs/yaffs2/yaffs_mtdif2.h +--- linux-2.6.28/fs/yaffs2/yaffs_mtdif2.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_mtdif2.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,29 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_MTDIF2_H__ ++#define __YAFFS_MTDIF2_H__ ++ ++#include "yaffs_guts.h" ++int nandmtd2_WriteChunkWithTagsToNAND(yaffs_Device * dev, int chunkInNAND, ++ const __u8 * data, ++ const yaffs_ExtendedTags * tags); ++int nandmtd2_ReadChunkWithTagsFromNAND(yaffs_Device * dev, int chunkInNAND, ++ __u8 * data, yaffs_ExtendedTags * tags); ++int nandmtd2_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo); ++int nandmtd2_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo, ++ yaffs_BlockState * state, __u32 *sequenceNumber); ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_nand.c linux-2.6.28.6/fs/yaffs2/yaffs_nand.c +--- linux-2.6.28/fs/yaffs2/yaffs_nand.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_nand.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,135 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++const char *yaffs_nand_c_version = ++ "$Id: yaffs_nand.c,v 1.9 2008/05/05 07:58:58 charles Exp $"; ++ ++#include "yaffs_nand.h" ++#include "yaffs_tagscompat.h" ++#include "yaffs_tagsvalidity.h" ++ ++#include "yaffs_getblockinfo.h" ++ ++int yaffs_ReadChunkWithTagsFromNAND(yaffs_Device * dev, int chunkInNAND, ++ __u8 * buffer, ++ yaffs_ExtendedTags * tags) ++{ ++ int result; ++ yaffs_ExtendedTags localTags; ++ ++ int realignedChunkInNAND = chunkInNAND - dev->chunkOffset; ++ ++ /* If there are no tags provided, use local tags to get prioritised gc working */ ++ if(!tags) ++ tags = &localTags; ++ ++ if (dev->readChunkWithTagsFromNAND) ++ result = dev->readChunkWithTagsFromNAND(dev, realignedChunkInNAND, buffer, ++ tags); ++ else ++ result = yaffs_TagsCompatabilityReadChunkWithTagsFromNAND(dev, ++ realignedChunkInNAND, ++ buffer, ++ tags); ++ if(tags && ++ tags->eccResult > YAFFS_ECC_RESULT_NO_ERROR){ ++ ++ yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, chunkInNAND/dev->nChunksPerBlock); ++ yaffs_HandleChunkError(dev,bi); ++ } ++ ++ return result; ++} ++ ++int yaffs_WriteChunkWithTagsToNAND(yaffs_Device * dev, ++ int chunkInNAND, ++ const __u8 * buffer, ++ yaffs_ExtendedTags * tags) ++{ ++ chunkInNAND -= dev->chunkOffset; ++ ++ ++ if (tags) { ++ tags->sequenceNumber = dev->sequenceNumber; ++ tags->chunkUsed = 1; ++ if (!yaffs_ValidateTags(tags)) { ++ T(YAFFS_TRACE_ERROR, ++ (TSTR("Writing uninitialised tags" TENDSTR))); ++ YBUG(); ++ } ++ T(YAFFS_TRACE_WRITE, ++ (TSTR("Writing chunk %d tags %d %d" TENDSTR), chunkInNAND, ++ tags->objectId, tags->chunkId)); ++ } else { ++ T(YAFFS_TRACE_ERROR, (TSTR("Writing with no tags" TENDSTR))); ++ YBUG(); ++ } ++ ++ if (dev->writeChunkWithTagsToNAND) ++ return dev->writeChunkWithTagsToNAND(dev, chunkInNAND, buffer, ++ tags); ++ else ++ return yaffs_TagsCompatabilityWriteChunkWithTagsToNAND(dev, ++ chunkInNAND, ++ buffer, ++ tags); ++} ++ ++int yaffs_MarkBlockBad(yaffs_Device * dev, int blockNo) ++{ ++ blockNo -= dev->blockOffset; ++ ++; ++ if (dev->markNANDBlockBad) ++ return dev->markNANDBlockBad(dev, blockNo); ++ else ++ return yaffs_TagsCompatabilityMarkNANDBlockBad(dev, blockNo); ++} ++ ++int yaffs_QueryInitialBlockState(yaffs_Device * dev, ++ int blockNo, ++ yaffs_BlockState * state, ++ __u32 *sequenceNumber) ++{ ++ blockNo -= dev->blockOffset; ++ ++ if (dev->queryNANDBlock) ++ return dev->queryNANDBlock(dev, blockNo, state, sequenceNumber); ++ else ++ return yaffs_TagsCompatabilityQueryNANDBlock(dev, blockNo, ++ state, ++ sequenceNumber); ++} ++ ++ ++int yaffs_EraseBlockInNAND(struct yaffs_DeviceStruct *dev, ++ int blockInNAND) ++{ ++ int result; ++ ++ blockInNAND -= dev->blockOffset; ++ ++ ++ dev->nBlockErasures++; ++ result = dev->eraseBlockInNAND(dev, blockInNAND); ++ ++ return result; ++} ++ ++int yaffs_InitialiseNAND(struct yaffs_DeviceStruct *dev) ++{ ++ return dev->initialiseNAND(dev); ++} ++ ++ ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_nand.h linux-2.6.28.6/fs/yaffs2/yaffs_nand.h +--- linux-2.6.28/fs/yaffs2/yaffs_nand.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_nand.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,44 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_NAND_H__ ++#define __YAFFS_NAND_H__ ++#include "yaffs_guts.h" ++ ++ ++ ++int yaffs_ReadChunkWithTagsFromNAND(yaffs_Device * dev, int chunkInNAND, ++ __u8 * buffer, ++ yaffs_ExtendedTags * tags); ++ ++int yaffs_WriteChunkWithTagsToNAND(yaffs_Device * dev, ++ int chunkInNAND, ++ const __u8 * buffer, ++ yaffs_ExtendedTags * tags); ++ ++int yaffs_MarkBlockBad(yaffs_Device * dev, int blockNo); ++ ++int yaffs_QueryInitialBlockState(yaffs_Device * dev, ++ int blockNo, ++ yaffs_BlockState * state, ++ unsigned *sequenceNumber); ++ ++int yaffs_EraseBlockInNAND(struct yaffs_DeviceStruct *dev, ++ int blockInNAND); ++ ++int yaffs_InitialiseNAND(struct yaffs_DeviceStruct *dev); ++ ++#endif ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_nandemul2k.h linux-2.6.28.6/fs/yaffs2/yaffs_nandemul2k.h +--- linux-2.6.28/fs/yaffs2/yaffs_nandemul2k.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_nandemul2k.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,39 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++/* Interface to emulated NAND functions (2k page size) */ ++ ++#ifndef __YAFFS_NANDEMUL2K_H__ ++#define __YAFFS_NANDEMUL2K_H__ ++ ++#include "yaffs_guts.h" ++ ++int nandemul2k_WriteChunkWithTagsToNAND(struct yaffs_DeviceStruct *dev, ++ int chunkInNAND, const __u8 * data, ++ const yaffs_ExtendedTags * tags); ++int nandemul2k_ReadChunkWithTagsFromNAND(struct yaffs_DeviceStruct *dev, ++ int chunkInNAND, __u8 * data, ++ yaffs_ExtendedTags * tags); ++int nandemul2k_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo); ++int nandemul2k_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo, ++ yaffs_BlockState * state, __u32 *sequenceNumber); ++int nandemul2k_EraseBlockInNAND(struct yaffs_DeviceStruct *dev, ++ int blockInNAND); ++int nandemul2k_InitialiseNAND(struct yaffs_DeviceStruct *dev); ++int nandemul2k_GetBytesPerChunk(void); ++int nandemul2k_GetChunksPerBlock(void); ++int nandemul2k_GetNumberOfBlocks(void); ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_packedtags1.c linux-2.6.28.6/fs/yaffs2/yaffs_packedtags1.c +--- linux-2.6.28/fs/yaffs2/yaffs_packedtags1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_packedtags1.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,52 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include "yaffs_packedtags1.h" ++#include "yportenv.h" ++ ++void yaffs_PackTags1(yaffs_PackedTags1 * pt, const yaffs_ExtendedTags * t) ++{ ++ pt->chunkId = t->chunkId; ++ pt->serialNumber = t->serialNumber; ++ pt->byteCount = t->byteCount; ++ pt->objectId = t->objectId; ++ pt->ecc = 0; ++ pt->deleted = (t->chunkDeleted) ? 0 : 1; ++ pt->unusedStuff = 0; ++ pt->shouldBeFF = 0xFFFFFFFF; ++ ++} ++ ++void yaffs_UnpackTags1(yaffs_ExtendedTags * t, const yaffs_PackedTags1 * pt) ++{ ++ static const __u8 allFF[] = ++ { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, ++0xff }; ++ ++ if (memcmp(allFF, pt, sizeof(yaffs_PackedTags1))) { ++ t->blockBad = 0; ++ if (pt->shouldBeFF != 0xFFFFFFFF) { ++ t->blockBad = 1; ++ } ++ t->chunkUsed = 1; ++ t->objectId = pt->objectId; ++ t->chunkId = pt->chunkId; ++ t->byteCount = pt->byteCount; ++ t->eccResult = YAFFS_ECC_RESULT_NO_ERROR; ++ t->chunkDeleted = (pt->deleted) ? 0 : 1; ++ t->serialNumber = pt->serialNumber; ++ } else { ++ memset(t, 0, sizeof(yaffs_ExtendedTags)); ++ ++ } ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_packedtags1.h linux-2.6.28.6/fs/yaffs2/yaffs_packedtags1.h +--- linux-2.6.28/fs/yaffs2/yaffs_packedtags1.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_packedtags1.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,37 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++/* This is used to pack YAFFS1 tags, not YAFFS2 tags. */ ++ ++#ifndef __YAFFS_PACKEDTAGS1_H__ ++#define __YAFFS_PACKEDTAGS1_H__ ++ ++#include "yaffs_guts.h" ++ ++typedef struct { ++ unsigned chunkId:20; ++ unsigned serialNumber:2; ++ unsigned byteCount:10; ++ unsigned objectId:18; ++ unsigned ecc:12; ++ unsigned deleted:1; ++ unsigned unusedStuff:1; ++ unsigned shouldBeFF; ++ ++} yaffs_PackedTags1; ++ ++void yaffs_PackTags1(yaffs_PackedTags1 * pt, const yaffs_ExtendedTags * t); ++void yaffs_UnpackTags1(yaffs_ExtendedTags * t, const yaffs_PackedTags1 * pt); ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_packedtags2.c linux-2.6.28.6/fs/yaffs2/yaffs_packedtags2.c +--- linux-2.6.28/fs/yaffs2/yaffs_packedtags2.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_packedtags2.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,208 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include "yaffs_packedtags2.h" ++#include "yportenv.h" ++#include "yaffs_tagsvalidity.h" ++ ++/* This code packs a set of extended tags into a binary structure for ++ * NAND storage ++ */ ++ ++/* Some of the information is "extra" struff which can be packed in to ++ * speed scanning ++ * This is defined by having the EXTRA_HEADER_INFO_FLAG set. ++ */ ++ ++/* Extra flags applied to chunkId */ ++ ++#define EXTRA_HEADER_INFO_FLAG 0x80000000 ++#define EXTRA_SHRINK_FLAG 0x40000000 ++#define EXTRA_SHADOWS_FLAG 0x20000000 ++#define EXTRA_SPARE_FLAGS 0x10000000 ++ ++#define ALL_EXTRA_FLAGS 0xF0000000 ++ ++/* Also, the top 4 bits of the object Id are set to the object type. */ ++#define EXTRA_OBJECT_TYPE_SHIFT (28) ++#define EXTRA_OBJECT_TYPE_MASK ((0x0F) << EXTRA_OBJECT_TYPE_SHIFT) ++ ++ ++static void yaffs_DumpPackedTags2TagsPart(const yaffs_PackedTags2TagsPart * ptt) ++{ ++ T(YAFFS_TRACE_MTD, ++ (TSTR("packed tags obj %d chunk %d byte %d seq %d" TENDSTR), ++ ptt->objectId, ptt->chunkId, ptt->byteCount, ++ ptt->sequenceNumber)); ++} ++static void yaffs_DumpPackedTags2(const yaffs_PackedTags2 * pt) ++{ ++ yaffs_DumpPackedTags2TagsPart(&pt->t); ++} ++ ++static void yaffs_DumpTags2(const yaffs_ExtendedTags * t) ++{ ++ T(YAFFS_TRACE_MTD, ++ (TSTR ++ ("ext.tags eccres %d blkbad %d chused %d obj %d chunk%d byte %d del %d ser %d seq %d" ++ TENDSTR), t->eccResult, t->blockBad, t->chunkUsed, t->objectId, ++ t->chunkId, t->byteCount, t->chunkDeleted, t->serialNumber, ++ t->sequenceNumber)); ++ ++} ++ ++void yaffs_PackTags2TagsPart(yaffs_PackedTags2TagsPart * ptt, const yaffs_ExtendedTags * t) ++{ ++ ptt->chunkId = t->chunkId; ++ ptt->sequenceNumber = t->sequenceNumber; ++ ptt->byteCount = t->byteCount; ++ ptt->objectId = t->objectId; ++ ++ if (t->chunkId == 0 && t->extraHeaderInfoAvailable) { ++ /* Store the extra header info instead */ ++ /* We save the parent object in the chunkId */ ++ ptt->chunkId = EXTRA_HEADER_INFO_FLAG ++ | t->extraParentObjectId; ++ if (t->extraIsShrinkHeader) { ++ ptt->chunkId |= EXTRA_SHRINK_FLAG; ++ } ++ if (t->extraShadows) { ++ ptt->chunkId |= EXTRA_SHADOWS_FLAG; ++ } ++ ++ ptt->objectId &= ~EXTRA_OBJECT_TYPE_MASK; ++ ptt->objectId |= ++ (t->extraObjectType << EXTRA_OBJECT_TYPE_SHIFT); ++ ++ if (t->extraObjectType == YAFFS_OBJECT_TYPE_HARDLINK) { ++ ptt->byteCount = t->extraEquivalentObjectId; ++ } else if (t->extraObjectType == YAFFS_OBJECT_TYPE_FILE) { ++ ptt->byteCount = t->extraFileLength; ++ } else { ++ ptt->byteCount = 0; ++ } ++ } ++ ++ yaffs_DumpPackedTags2TagsPart(ptt); ++ yaffs_DumpTags2(t); ++} ++ ++ ++void yaffs_PackTags2(yaffs_PackedTags2 * pt, const yaffs_ExtendedTags * t) ++{ ++ yaffs_PackTags2TagsPart(&pt->t,t); ++ ++#ifndef YAFFS_IGNORE_TAGS_ECC ++ { ++ yaffs_ECCCalculateOther((unsigned char *)&pt->t, ++ sizeof(yaffs_PackedTags2TagsPart), ++ &pt->ecc); ++ } ++#endif ++} ++ ++ ++void yaffs_UnpackTags2TagsPart(yaffs_ExtendedTags * t, yaffs_PackedTags2TagsPart * ptt) ++{ ++ ++ memset(t, 0, sizeof(yaffs_ExtendedTags)); ++ ++ yaffs_InitialiseTags(t); ++ ++ if (ptt->sequenceNumber != 0xFFFFFFFF) { ++ t->blockBad = 0; ++ t->chunkUsed = 1; ++ t->objectId = ptt->objectId; ++ t->chunkId = ptt->chunkId; ++ t->byteCount = ptt->byteCount; ++ t->chunkDeleted = 0; ++ t->serialNumber = 0; ++ t->sequenceNumber = ptt->sequenceNumber; ++ ++ /* Do extra header info stuff */ ++ ++ if (ptt->chunkId & EXTRA_HEADER_INFO_FLAG) { ++ t->chunkId = 0; ++ t->byteCount = 0; ++ ++ t->extraHeaderInfoAvailable = 1; ++ t->extraParentObjectId = ++ ptt->chunkId & (~(ALL_EXTRA_FLAGS)); ++ t->extraIsShrinkHeader = ++ (ptt->chunkId & EXTRA_SHRINK_FLAG) ? 1 : 0; ++ t->extraShadows = ++ (ptt->chunkId & EXTRA_SHADOWS_FLAG) ? 1 : 0; ++ t->extraObjectType = ++ ptt->objectId >> EXTRA_OBJECT_TYPE_SHIFT; ++ t->objectId &= ~EXTRA_OBJECT_TYPE_MASK; ++ ++ if (t->extraObjectType == YAFFS_OBJECT_TYPE_HARDLINK) { ++ t->extraEquivalentObjectId = ptt->byteCount; ++ } else { ++ t->extraFileLength = ptt->byteCount; ++ } ++ } ++ } ++ ++ yaffs_DumpPackedTags2TagsPart(ptt); ++ yaffs_DumpTags2(t); ++ ++} ++ ++ ++void yaffs_UnpackTags2(yaffs_ExtendedTags * t, yaffs_PackedTags2 * pt) ++{ ++ ++ yaffs_ECCResult eccResult = YAFFS_ECC_RESULT_NO_ERROR; ++ ++ if (pt->t.sequenceNumber != 0xFFFFFFFF) { ++ /* Page is in use */ ++#ifndef YAFFS_IGNORE_TAGS_ECC ++ { ++ yaffs_ECCOther ecc; ++ int result; ++ yaffs_ECCCalculateOther((unsigned char *)&pt->t, ++ sizeof ++ (yaffs_PackedTags2TagsPart), ++ &ecc); ++ result = ++ yaffs_ECCCorrectOther((unsigned char *)&pt->t, ++ sizeof ++ (yaffs_PackedTags2TagsPart), ++ &pt->ecc, &ecc); ++ switch(result){ ++ case 0: ++ eccResult = YAFFS_ECC_RESULT_NO_ERROR; ++ break; ++ case 1: ++ eccResult = YAFFS_ECC_RESULT_FIXED; ++ break; ++ case -1: ++ eccResult = YAFFS_ECC_RESULT_UNFIXED; ++ break; ++ default: ++ eccResult = YAFFS_ECC_RESULT_UNKNOWN; ++ } ++ } ++#endif ++ } ++ ++ yaffs_UnpackTags2TagsPart(t,&pt->t); ++ ++ t->eccResult = eccResult; ++ ++ yaffs_DumpPackedTags2(pt); ++ yaffs_DumpTags2(t); ++ ++} ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_packedtags2.h linux-2.6.28.6/fs/yaffs2/yaffs_packedtags2.h +--- linux-2.6.28/fs/yaffs2/yaffs_packedtags2.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_packedtags2.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,43 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++/* This is used to pack YAFFS2 tags, not YAFFS1tags. */ ++ ++#ifndef __YAFFS_PACKEDTAGS2_H__ ++#define __YAFFS_PACKEDTAGS2_H__ ++ ++#include "yaffs_guts.h" ++#include "yaffs_ecc.h" ++ ++typedef struct { ++ unsigned sequenceNumber; ++ unsigned objectId; ++ unsigned chunkId; ++ unsigned byteCount; ++} yaffs_PackedTags2TagsPart; ++ ++typedef struct { ++ yaffs_PackedTags2TagsPart t; ++ yaffs_ECCOther ecc; ++} yaffs_PackedTags2; ++ ++/* Full packed tags with ECC, used for oob tags */ ++void yaffs_PackTags2(yaffs_PackedTags2 * pt, const yaffs_ExtendedTags * t); ++void yaffs_UnpackTags2(yaffs_ExtendedTags * t, yaffs_PackedTags2 * pt); ++ ++/* Only the tags part (no ECC for use with inband tags */ ++void yaffs_PackTags2TagsPart(yaffs_PackedTags2TagsPart * pt, const yaffs_ExtendedTags * t); ++void yaffs_UnpackTags2TagsPart(yaffs_ExtendedTags * t, yaffs_PackedTags2TagsPart * pt); ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_qsort.c linux-2.6.28.6/fs/yaffs2/yaffs_qsort.c +--- linux-2.6.28/fs/yaffs2/yaffs_qsort.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_qsort.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,160 @@ ++/* ++ * Copyright (c) 1992, 1993 ++ * The Regents of the University of California. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. Neither the name of the University nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ */ ++ ++#include "yportenv.h" ++//#include ++ ++/* ++ * Qsort routine from Bentley & McIlroy's "Engineering a Sort Function". ++ */ ++#define swapcode(TYPE, parmi, parmj, n) { \ ++ long i = (n) / sizeof (TYPE); \ ++ register TYPE *pi = (TYPE *) (parmi); \ ++ register TYPE *pj = (TYPE *) (parmj); \ ++ do { \ ++ register TYPE t = *pi; \ ++ *pi++ = *pj; \ ++ *pj++ = t; \ ++ } while (--i > 0); \ ++} ++ ++#define SWAPINIT(a, es) swaptype = ((char *)a - (char *)0) % sizeof(long) || \ ++ es % sizeof(long) ? 2 : es == sizeof(long)? 0 : 1; ++ ++static __inline void ++swapfunc(char *a, char *b, int n, int swaptype) ++{ ++ if (swaptype <= 1) ++ swapcode(long, a, b, n) ++ else ++ swapcode(char, a, b, n) ++} ++ ++#define swap(a, b) \ ++ if (swaptype == 0) { \ ++ long t = *(long *)(a); \ ++ *(long *)(a) = *(long *)(b); \ ++ *(long *)(b) = t; \ ++ } else \ ++ swapfunc(a, b, es, swaptype) ++ ++#define vecswap(a, b, n) if ((n) > 0) swapfunc(a, b, n, swaptype) ++ ++static __inline char * ++med3(char *a, char *b, char *c, int (*cmp)(const void *, const void *)) ++{ ++ return cmp(a, b) < 0 ? ++ (cmp(b, c) < 0 ? b : (cmp(a, c) < 0 ? c : a )) ++ :(cmp(b, c) > 0 ? b : (cmp(a, c) < 0 ? a : c )); ++} ++ ++#ifndef min ++#define min(a,b) (((a) < (b)) ? (a) : (b)) ++#endif ++ ++void ++yaffs_qsort(void *aa, size_t n, size_t es, ++ int (*cmp)(const void *, const void *)) ++{ ++ char *pa, *pb, *pc, *pd, *pl, *pm, *pn; ++ int d, r, swaptype, swap_cnt; ++ register char *a = aa; ++ ++loop: SWAPINIT(a, es); ++ swap_cnt = 0; ++ if (n < 7) { ++ for (pm = (char *)a + es; pm < (char *) a + n * es; pm += es) ++ for (pl = pm; pl > (char *) a && cmp(pl - es, pl) > 0; ++ pl -= es) ++ swap(pl, pl - es); ++ return; ++ } ++ pm = (char *)a + (n / 2) * es; ++ if (n > 7) { ++ pl = (char *)a; ++ pn = (char *)a + (n - 1) * es; ++ if (n > 40) { ++ d = (n / 8) * es; ++ pl = med3(pl, pl + d, pl + 2 * d, cmp); ++ pm = med3(pm - d, pm, pm + d, cmp); ++ pn = med3(pn - 2 * d, pn - d, pn, cmp); ++ } ++ pm = med3(pl, pm, pn, cmp); ++ } ++ swap(a, pm); ++ pa = pb = (char *)a + es; ++ ++ pc = pd = (char *)a + (n - 1) * es; ++ for (;;) { ++ while (pb <= pc && (r = cmp(pb, a)) <= 0) { ++ if (r == 0) { ++ swap_cnt = 1; ++ swap(pa, pb); ++ pa += es; ++ } ++ pb += es; ++ } ++ while (pb <= pc && (r = cmp(pc, a)) >= 0) { ++ if (r == 0) { ++ swap_cnt = 1; ++ swap(pc, pd); ++ pd -= es; ++ } ++ pc -= es; ++ } ++ if (pb > pc) ++ break; ++ swap(pb, pc); ++ swap_cnt = 1; ++ pb += es; ++ pc -= es; ++ } ++ if (swap_cnt == 0) { /* Switch to insertion sort */ ++ for (pm = (char *) a + es; pm < (char *) a + n * es; pm += es) ++ for (pl = pm; pl > (char *) a && cmp(pl - es, pl) > 0; ++ pl -= es) ++ swap(pl, pl - es); ++ return; ++ } ++ ++ pn = (char *)a + n * es; ++ r = min(pa - (char *)a, pb - pa); ++ vecswap(a, pb - r, r); ++ r = min((long)(pd - pc), (long)(pn - pd - es)); ++ vecswap(pb, pn - r, r); ++ if ((r = pb - pa) > es) ++ yaffs_qsort(a, r / es, es, cmp); ++ if ((r = pd - pc) > es) { ++ /* Iterate rather than recurse to save stack space */ ++ a = pn - r; ++ n = r / es; ++ goto loop; ++ } ++/* yaffs_qsort(pn - r, r / es, es, cmp);*/ ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_qsort.h linux-2.6.28.6/fs/yaffs2/yaffs_qsort.h +--- linux-2.6.28/fs/yaffs2/yaffs_qsort.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_qsort.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,23 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++ ++#ifndef __YAFFS_QSORT_H__ ++#define __YAFFS_QSORT_H__ ++ ++extern void yaffs_qsort (void *const base, size_t total_elems, size_t size, ++ int (*cmp)(const void *, const void *)); ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_tagscompat.c linux-2.6.28.6/fs/yaffs2/yaffs_tagscompat.c +--- linux-2.6.28/fs/yaffs2/yaffs_tagscompat.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_tagscompat.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,547 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include "yaffs_guts.h" ++#include "yaffs_tagscompat.h" ++#include "yaffs_ecc.h" ++#include "yaffs_getblockinfo.h" ++ ++static void yaffs_HandleReadDataError(yaffs_Device * dev, int chunkInNAND); ++#ifdef NOTYET ++static void yaffs_CheckWrittenBlock(yaffs_Device * dev, int chunkInNAND); ++static void yaffs_HandleWriteChunkOk(yaffs_Device * dev, int chunkInNAND, ++ const __u8 * data, ++ const yaffs_Spare * spare); ++static void yaffs_HandleUpdateChunk(yaffs_Device * dev, int chunkInNAND, ++ const yaffs_Spare * spare); ++static void yaffs_HandleWriteChunkError(yaffs_Device * dev, int chunkInNAND); ++#endif ++ ++static const char yaffs_countBitsTable[256] = { ++ 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, ++ 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, ++ 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, ++ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, ++ 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, ++ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, ++ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, ++ 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, ++ 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, ++ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, ++ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, ++ 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, ++ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, ++ 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, ++ 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, ++ 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8 ++}; ++ ++int yaffs_CountBits(__u8 x) ++{ ++ int retVal; ++ retVal = yaffs_countBitsTable[x]; ++ return retVal; ++} ++ ++/********** Tags ECC calculations *********/ ++ ++void yaffs_CalcECC(const __u8 * data, yaffs_Spare * spare) ++{ ++ yaffs_ECCCalculate(data, spare->ecc1); ++ yaffs_ECCCalculate(&data[256], spare->ecc2); ++} ++ ++void yaffs_CalcTagsECC(yaffs_Tags * tags) ++{ ++ /* Calculate an ecc */ ++ ++ unsigned char *b = ((yaffs_TagsUnion *) tags)->asBytes; ++ unsigned i, j; ++ unsigned ecc = 0; ++ unsigned bit = 0; ++ ++ tags->ecc = 0; ++ ++ for (i = 0; i < 8; i++) { ++ for (j = 1; j & 0xff; j <<= 1) { ++ bit++; ++ if (b[i] & j) { ++ ecc ^= bit; ++ } ++ } ++ } ++ ++ tags->ecc = ecc; ++ ++} ++ ++int yaffs_CheckECCOnTags(yaffs_Tags * tags) ++{ ++ unsigned ecc = tags->ecc; ++ ++ yaffs_CalcTagsECC(tags); ++ ++ ecc ^= tags->ecc; ++ ++ if (ecc && ecc <= 64) { ++ /* TODO: Handle the failure better. Retire? */ ++ unsigned char *b = ((yaffs_TagsUnion *) tags)->asBytes; ++ ++ ecc--; ++ ++ b[ecc / 8] ^= (1 << (ecc & 7)); ++ ++ /* Now recvalc the ecc */ ++ yaffs_CalcTagsECC(tags); ++ ++ return 1; /* recovered error */ ++ } else if (ecc) { ++ /* Wierd ecc failure value */ ++ /* TODO Need to do somethiong here */ ++ return -1; /* unrecovered error */ ++ } ++ ++ return 0; ++} ++ ++/********** Tags **********/ ++ ++static void yaffs_LoadTagsIntoSpare(yaffs_Spare * sparePtr, ++ yaffs_Tags * tagsPtr) ++{ ++ yaffs_TagsUnion *tu = (yaffs_TagsUnion *) tagsPtr; ++ ++ yaffs_CalcTagsECC(tagsPtr); ++ ++ sparePtr->tagByte0 = tu->asBytes[0]; ++ sparePtr->tagByte1 = tu->asBytes[1]; ++ sparePtr->tagByte2 = tu->asBytes[2]; ++ sparePtr->tagByte3 = tu->asBytes[3]; ++ sparePtr->tagByte4 = tu->asBytes[4]; ++ sparePtr->tagByte5 = tu->asBytes[5]; ++ sparePtr->tagByte6 = tu->asBytes[6]; ++ sparePtr->tagByte7 = tu->asBytes[7]; ++} ++ ++static void yaffs_GetTagsFromSpare(yaffs_Device * dev, yaffs_Spare * sparePtr, ++ yaffs_Tags * tagsPtr) ++{ ++ yaffs_TagsUnion *tu = (yaffs_TagsUnion *) tagsPtr; ++ int result; ++ ++ tu->asBytes[0] = sparePtr->tagByte0; ++ tu->asBytes[1] = sparePtr->tagByte1; ++ tu->asBytes[2] = sparePtr->tagByte2; ++ tu->asBytes[3] = sparePtr->tagByte3; ++ tu->asBytes[4] = sparePtr->tagByte4; ++ tu->asBytes[5] = sparePtr->tagByte5; ++ tu->asBytes[6] = sparePtr->tagByte6; ++ tu->asBytes[7] = sparePtr->tagByte7; ++ ++ result = yaffs_CheckECCOnTags(tagsPtr); ++ if (result > 0) { ++ dev->tagsEccFixed++; ++ } else if (result < 0) { ++ dev->tagsEccUnfixed++; ++ } ++} ++ ++static void yaffs_SpareInitialise(yaffs_Spare * spare) ++{ ++ memset(spare, 0xFF, sizeof(yaffs_Spare)); ++} ++ ++static int yaffs_WriteChunkToNAND(struct yaffs_DeviceStruct *dev, ++ int chunkInNAND, const __u8 * data, ++ yaffs_Spare * spare) ++{ ++ if (chunkInNAND < dev->startBlock * dev->nChunksPerBlock) { ++ T(YAFFS_TRACE_ERROR, ++ (TSTR("**>> yaffs chunk %d is not valid" TENDSTR), ++ chunkInNAND)); ++ return YAFFS_FAIL; ++ } ++ ++ dev->nPageWrites++; ++ return dev->writeChunkToNAND(dev, chunkInNAND, data, spare); ++} ++ ++static int yaffs_ReadChunkFromNAND(struct yaffs_DeviceStruct *dev, ++ int chunkInNAND, ++ __u8 * data, ++ yaffs_Spare * spare, ++ yaffs_ECCResult * eccResult, ++ int doErrorCorrection) ++{ ++ int retVal; ++ yaffs_Spare localSpare; ++ ++ dev->nPageReads++; ++ ++ if (!spare && data) { ++ /* If we don't have a real spare, then we use a local one. */ ++ /* Need this for the calculation of the ecc */ ++ spare = &localSpare; ++ } ++ ++ if (!dev->useNANDECC) { ++ retVal = dev->readChunkFromNAND(dev, chunkInNAND, data, spare); ++ if (data && doErrorCorrection) { ++ /* Do ECC correction */ ++ /* Todo handle any errors */ ++ int eccResult1, eccResult2; ++ __u8 calcEcc[3]; ++ ++ yaffs_ECCCalculate(data, calcEcc); ++ eccResult1 = ++ yaffs_ECCCorrect(data, spare->ecc1, calcEcc); ++ yaffs_ECCCalculate(&data[256], calcEcc); ++ eccResult2 = ++ yaffs_ECCCorrect(&data[256], spare->ecc2, calcEcc); ++ ++ if (eccResult1 > 0) { ++ T(YAFFS_TRACE_ERROR, ++ (TSTR ++ ("**>>yaffs ecc error fix performed on chunk %d:0" ++ TENDSTR), chunkInNAND)); ++ dev->eccFixed++; ++ } else if (eccResult1 < 0) { ++ T(YAFFS_TRACE_ERROR, ++ (TSTR ++ ("**>>yaffs ecc error unfixed on chunk %d:0" ++ TENDSTR), chunkInNAND)); ++ dev->eccUnfixed++; ++ } ++ ++ if (eccResult2 > 0) { ++ T(YAFFS_TRACE_ERROR, ++ (TSTR ++ ("**>>yaffs ecc error fix performed on chunk %d:1" ++ TENDSTR), chunkInNAND)); ++ dev->eccFixed++; ++ } else if (eccResult2 < 0) { ++ T(YAFFS_TRACE_ERROR, ++ (TSTR ++ ("**>>yaffs ecc error unfixed on chunk %d:1" ++ TENDSTR), chunkInNAND)); ++ dev->eccUnfixed++; ++ } ++ ++ if (eccResult1 || eccResult2) { ++ /* We had a data problem on this page */ ++ yaffs_HandleReadDataError(dev, chunkInNAND); ++ } ++ ++ if (eccResult1 < 0 || eccResult2 < 0) ++ *eccResult = YAFFS_ECC_RESULT_UNFIXED; ++ else if (eccResult1 > 0 || eccResult2 > 0) ++ *eccResult = YAFFS_ECC_RESULT_FIXED; ++ else ++ *eccResult = YAFFS_ECC_RESULT_NO_ERROR; ++ } ++ } else { ++ /* Must allocate enough memory for spare+2*sizeof(int) */ ++ /* for ecc results from device. */ ++ struct yaffs_NANDSpare nspare; ++ ++ memset(&nspare,0,sizeof(nspare)); ++ ++ retVal = ++ dev->readChunkFromNAND(dev, chunkInNAND, data, ++ (yaffs_Spare *) & nspare); ++ memcpy(spare, &nspare, sizeof(yaffs_Spare)); ++ if (data && doErrorCorrection) { ++ if (nspare.eccres1 > 0) { ++ T(YAFFS_TRACE_ERROR, ++ (TSTR ++ ("**>>mtd ecc error fix performed on chunk %d:0" ++ TENDSTR), chunkInNAND)); ++ } else if (nspare.eccres1 < 0) { ++ T(YAFFS_TRACE_ERROR, ++ (TSTR ++ ("**>>mtd ecc error unfixed on chunk %d:0" ++ TENDSTR), chunkInNAND)); ++ } ++ ++ if (nspare.eccres2 > 0) { ++ T(YAFFS_TRACE_ERROR, ++ (TSTR ++ ("**>>mtd ecc error fix performed on chunk %d:1" ++ TENDSTR), chunkInNAND)); ++ } else if (nspare.eccres2 < 0) { ++ T(YAFFS_TRACE_ERROR, ++ (TSTR ++ ("**>>mtd ecc error unfixed on chunk %d:1" ++ TENDSTR), chunkInNAND)); ++ } ++ ++ if (nspare.eccres1 || nspare.eccres2) { ++ /* We had a data problem on this page */ ++ yaffs_HandleReadDataError(dev, chunkInNAND); ++ } ++ ++ if (nspare.eccres1 < 0 || nspare.eccres2 < 0) ++ *eccResult = YAFFS_ECC_RESULT_UNFIXED; ++ else if (nspare.eccres1 > 0 || nspare.eccres2 > 0) ++ *eccResult = YAFFS_ECC_RESULT_FIXED; ++ else ++ *eccResult = YAFFS_ECC_RESULT_NO_ERROR; ++ ++ } ++ } ++ return retVal; ++} ++ ++#ifdef NOTYET ++static int yaffs_CheckChunkErased(struct yaffs_DeviceStruct *dev, ++ int chunkInNAND) ++{ ++ ++ static int init = 0; ++ static __u8 cmpbuf[YAFFS_BYTES_PER_CHUNK]; ++ static __u8 data[YAFFS_BYTES_PER_CHUNK]; ++ /* Might as well always allocate the larger size for */ ++ /* dev->useNANDECC == true; */ ++ static __u8 spare[sizeof(struct yaffs_NANDSpare)]; ++ ++ dev->readChunkFromNAND(dev, chunkInNAND, data, (yaffs_Spare *) spare); ++ ++ if (!init) { ++ memset(cmpbuf, 0xff, YAFFS_BYTES_PER_CHUNK); ++ init = 1; ++ } ++ ++ if (memcmp(cmpbuf, data, YAFFS_BYTES_PER_CHUNK)) ++ return YAFFS_FAIL; ++ if (memcmp(cmpbuf, spare, 16)) ++ return YAFFS_FAIL; ++ ++ return YAFFS_OK; ++ ++} ++#endif ++ ++/* ++ * Functions for robustisizing ++ */ ++ ++static void yaffs_HandleReadDataError(yaffs_Device * dev, int chunkInNAND) ++{ ++ int blockInNAND = chunkInNAND / dev->nChunksPerBlock; ++ ++ /* Mark the block for retirement */ ++ yaffs_GetBlockInfo(dev, blockInNAND + dev->blockOffset)->needsRetiring = 1; ++ T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS, ++ (TSTR("**>>Block %d marked for retirement" TENDSTR), blockInNAND)); ++ ++ /* TODO: ++ * Just do a garbage collection on the affected block ++ * then retire the block ++ * NB recursion ++ */ ++} ++ ++#ifdef NOTYET ++static void yaffs_CheckWrittenBlock(yaffs_Device * dev, int chunkInNAND) ++{ ++} ++ ++static void yaffs_HandleWriteChunkOk(yaffs_Device * dev, int chunkInNAND, ++ const __u8 * data, ++ const yaffs_Spare * spare) ++{ ++} ++ ++static void yaffs_HandleUpdateChunk(yaffs_Device * dev, int chunkInNAND, ++ const yaffs_Spare * spare) ++{ ++} ++ ++static void yaffs_HandleWriteChunkError(yaffs_Device * dev, int chunkInNAND) ++{ ++ int blockInNAND = chunkInNAND / dev->nChunksPerBlock; ++ ++ /* Mark the block for retirement */ ++ yaffs_GetBlockInfo(dev, blockInNAND)->needsRetiring = 1; ++ /* Delete the chunk */ ++ yaffs_DeleteChunk(dev, chunkInNAND, 1, __LINE__); ++} ++ ++static int yaffs_VerifyCompare(const __u8 * d0, const __u8 * d1, ++ const yaffs_Spare * s0, const yaffs_Spare * s1) ++{ ++ ++ if (memcmp(d0, d1, YAFFS_BYTES_PER_CHUNK) != 0 || ++ s0->tagByte0 != s1->tagByte0 || ++ s0->tagByte1 != s1->tagByte1 || ++ s0->tagByte2 != s1->tagByte2 || ++ s0->tagByte3 != s1->tagByte3 || ++ s0->tagByte4 != s1->tagByte4 || ++ s0->tagByte5 != s1->tagByte5 || ++ s0->tagByte6 != s1->tagByte6 || ++ s0->tagByte7 != s1->tagByte7 || ++ s0->ecc1[0] != s1->ecc1[0] || ++ s0->ecc1[1] != s1->ecc1[1] || ++ s0->ecc1[2] != s1->ecc1[2] || ++ s0->ecc2[0] != s1->ecc2[0] || ++ s0->ecc2[1] != s1->ecc2[1] || s0->ecc2[2] != s1->ecc2[2]) { ++ return 0; ++ } ++ ++ return 1; ++} ++#endif /* NOTYET */ ++ ++int yaffs_TagsCompatabilityWriteChunkWithTagsToNAND(yaffs_Device * dev, ++ int chunkInNAND, ++ const __u8 * data, ++ const yaffs_ExtendedTags * ++ eTags) ++{ ++ yaffs_Spare spare; ++ yaffs_Tags tags; ++ ++ yaffs_SpareInitialise(&spare); ++ ++ if (eTags->chunkDeleted) { ++ spare.pageStatus = 0; ++ } else { ++ tags.objectId = eTags->objectId; ++ tags.chunkId = eTags->chunkId; ++ ++ tags.byteCountLSB = eTags->byteCount & 0x3ff; ++ ++ if(dev->nDataBytesPerChunk >= 1024){ ++ tags.byteCountMSB = (eTags->byteCount >> 10) & 3; ++ } else { ++ tags.byteCountMSB = 3; ++ } ++ ++ ++ tags.serialNumber = eTags->serialNumber; ++ ++ if (!dev->useNANDECC && data) { ++ yaffs_CalcECC(data, &spare); ++ } ++ yaffs_LoadTagsIntoSpare(&spare, &tags); ++ ++ } ++ ++ return yaffs_WriteChunkToNAND(dev, chunkInNAND, data, &spare); ++} ++ ++int yaffs_TagsCompatabilityReadChunkWithTagsFromNAND(yaffs_Device * dev, ++ int chunkInNAND, ++ __u8 * data, ++ yaffs_ExtendedTags * eTags) ++{ ++ ++ yaffs_Spare spare; ++ yaffs_Tags tags; ++ yaffs_ECCResult eccResult = YAFFS_ECC_RESULT_UNKNOWN; ++ ++ static yaffs_Spare spareFF; ++ static int init = 0; ++ ++ if (!init) { ++ memset(&spareFF, 0xFF, sizeof(spareFF)); ++ init = 1; ++ } ++ ++ if (yaffs_ReadChunkFromNAND ++ (dev, chunkInNAND, data, &spare, &eccResult, 1)) { ++ /* eTags may be NULL */ ++ if (eTags) { ++ ++ int deleted = ++ (yaffs_CountBits(spare.pageStatus) < 7) ? 1 : 0; ++ ++ eTags->chunkDeleted = deleted; ++ eTags->eccResult = eccResult; ++ eTags->blockBad = 0; /* We're reading it */ ++ /* therefore it is not a bad block */ ++ eTags->chunkUsed = ++ (memcmp(&spareFF, &spare, sizeof(spareFF)) != ++ 0) ? 1 : 0; ++ ++ if (eTags->chunkUsed) { ++ yaffs_GetTagsFromSpare(dev, &spare, &tags); ++ ++ eTags->objectId = tags.objectId; ++ eTags->chunkId = tags.chunkId; ++ eTags->byteCount = tags.byteCountLSB; ++ ++ if(dev->nDataBytesPerChunk >= 1024) ++ eTags->byteCount |= (((unsigned) tags.byteCountMSB) << 10); ++ ++ eTags->serialNumber = tags.serialNumber; ++ } ++ } ++ ++ return YAFFS_OK; ++ } else { ++ return YAFFS_FAIL; ++ } ++} ++ ++int yaffs_TagsCompatabilityMarkNANDBlockBad(struct yaffs_DeviceStruct *dev, ++ int blockInNAND) ++{ ++ ++ yaffs_Spare spare; ++ ++ memset(&spare, 0xff, sizeof(yaffs_Spare)); ++ ++ spare.blockStatus = 'Y'; ++ ++ yaffs_WriteChunkToNAND(dev, blockInNAND * dev->nChunksPerBlock, NULL, ++ &spare); ++ yaffs_WriteChunkToNAND(dev, blockInNAND * dev->nChunksPerBlock + 1, ++ NULL, &spare); ++ ++ return YAFFS_OK; ++ ++} ++ ++int yaffs_TagsCompatabilityQueryNANDBlock(struct yaffs_DeviceStruct *dev, ++ int blockNo, ++ yaffs_BlockState *state, ++ __u32 *sequenceNumber) ++{ ++ ++ yaffs_Spare spare0, spare1; ++ static yaffs_Spare spareFF; ++ static int init; ++ yaffs_ECCResult dummy; ++ ++ if (!init) { ++ memset(&spareFF, 0xFF, sizeof(spareFF)); ++ init = 1; ++ } ++ ++ *sequenceNumber = 0; ++ ++ yaffs_ReadChunkFromNAND(dev, blockNo * dev->nChunksPerBlock, NULL, ++ &spare0, &dummy, 1); ++ yaffs_ReadChunkFromNAND(dev, blockNo * dev->nChunksPerBlock + 1, NULL, ++ &spare1, &dummy, 1); ++ ++ if (yaffs_CountBits(spare0.blockStatus & spare1.blockStatus) < 7) ++ *state = YAFFS_BLOCK_STATE_DEAD; ++ else if (memcmp(&spareFF, &spare0, sizeof(spareFF)) == 0) ++ *state = YAFFS_BLOCK_STATE_EMPTY; ++ else ++ *state = YAFFS_BLOCK_STATE_NEEDS_SCANNING; ++ ++ return YAFFS_OK; ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_tagscompat.h linux-2.6.28.6/fs/yaffs2/yaffs_tagscompat.h +--- linux-2.6.28/fs/yaffs2/yaffs_tagscompat.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_tagscompat.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,41 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFS_TAGSCOMPAT_H__ ++#define __YAFFS_TAGSCOMPAT_H__ ++ ++#include "yaffs_guts.h" ++int yaffs_TagsCompatabilityWriteChunkWithTagsToNAND(yaffs_Device * dev, ++ int chunkInNAND, ++ const __u8 * data, ++ const yaffs_ExtendedTags * ++ tags); ++int yaffs_TagsCompatabilityReadChunkWithTagsFromNAND(yaffs_Device * dev, ++ int chunkInNAND, ++ __u8 * data, ++ yaffs_ExtendedTags * ++ tags); ++int yaffs_TagsCompatabilityMarkNANDBlockBad(struct yaffs_DeviceStruct *dev, ++ int blockNo); ++int yaffs_TagsCompatabilityQueryNANDBlock(struct yaffs_DeviceStruct *dev, ++ int blockNo, ++ yaffs_BlockState *state, ++ __u32 *sequenceNumber); ++ ++void yaffs_CalcTagsECC(yaffs_Tags * tags); ++int yaffs_CheckECCOnTags(yaffs_Tags * tags); ++int yaffs_CountBits(__u8 byte); ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_tagsvalidity.c linux-2.6.28.6/fs/yaffs2/yaffs_tagsvalidity.c +--- linux-2.6.28/fs/yaffs2/yaffs_tagsvalidity.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_tagsvalidity.c 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,28 @@ ++/* ++ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include "yaffs_tagsvalidity.h" ++ ++void yaffs_InitialiseTags(yaffs_ExtendedTags * tags) ++{ ++ memset(tags, 0, sizeof(yaffs_ExtendedTags)); ++ tags->validMarker0 = 0xAAAAAAAA; ++ tags->validMarker1 = 0x55555555; ++} ++ ++int yaffs_ValidateTags(yaffs_ExtendedTags * tags) ++{ ++ return (tags->validMarker0 == 0xAAAAAAAA && ++ tags->validMarker1 == 0x55555555); ++ ++} +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffs_tagsvalidity.h linux-2.6.28.6/fs/yaffs2/yaffs_tagsvalidity.h +--- linux-2.6.28/fs/yaffs2/yaffs_tagsvalidity.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffs_tagsvalidity.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,24 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++ ++#ifndef __YAFFS_TAGS_VALIDITY_H__ ++#define __YAFFS_TAGS_VALIDITY_H__ ++ ++#include "yaffs_guts.h" ++ ++void yaffs_InitialiseTags(yaffs_ExtendedTags * tags); ++int yaffs_ValidateTags(yaffs_ExtendedTags * tags); ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yaffsinterface.h linux-2.6.28.6/fs/yaffs2/yaffsinterface.h +--- linux-2.6.28/fs/yaffs2/yaffsinterface.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yaffsinterface.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,21 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++#ifndef __YAFFSINTERFACE_H__ ++#define __YAFFSINTERFACE_H__ ++ ++int yaffs_Initialise(unsigned nBlocks); ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/fs/yaffs2/yportenv.h linux-2.6.28.6/fs/yaffs2/yportenv.h +--- linux-2.6.28/fs/yaffs2/yportenv.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/fs/yaffs2/yportenv.h 2009-04-30 09:36:39.000000000 +0200 +@@ -0,0 +1,203 @@ ++/* ++ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. ++ * ++ * Copyright (C) 2002-2007 Aleph One Ltd. ++ * for Toby Churchill Ltd and Brightstar Engineering ++ * ++ * Created by Charles Manning ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License version 2.1 as ++ * published by the Free Software Foundation. ++ * ++ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. ++ */ ++ ++ ++#ifndef __YPORTENV_H__ ++#define __YPORTENV_H__ ++ ++/* ++ * Define the MTD version in terms of Linux Kernel versions ++ * This allows yaffs to be used independantly of the kernel ++ * as well as with it. ++ */ ++ ++#define MTD_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) ++ ++#if defined CONFIG_YAFFS_WINCE ++ ++#include "ywinceenv.h" ++ ++#elif defined __KERNEL__ ++ ++#include "moduleconfig.h" ++ ++/* Linux kernel */ ++ ++#include ++#define MTD_VERSION_CODE LINUX_VERSION_CODE ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define YCHAR char ++#define YUCHAR unsigned char ++#define _Y(x) x ++#define yaffs_strcat(a,b) strcat(a,b) ++#define yaffs_strcpy(a,b) strcpy(a,b) ++#define yaffs_strncpy(a,b,c) strncpy(a,b,c) ++#define yaffs_strncmp(a,b,c) strncmp(a,b,c) ++#define yaffs_strlen(s) strlen(s) ++#define yaffs_sprintf sprintf ++#define yaffs_toupper(a) toupper(a) ++ ++#define Y_INLINE inline ++ ++#define YAFFS_LOSTNFOUND_NAME "lost+found" ++#define YAFFS_LOSTNFOUND_PREFIX "obj" ++ ++/* #define YPRINTF(x) printk x */ ++#define YMALLOC(x) kmalloc(x,GFP_NOFS) ++#define YFREE(x) kfree(x) ++#define YMALLOC_ALT(x) vmalloc(x) ++#define YFREE_ALT(x) vfree(x) ++#define YMALLOC_DMA(x) YMALLOC(x) ++ ++// KR - added for use in scan so processes aren't blocked indefinitely. ++#define YYIELD() schedule() ++ ++#define YAFFS_ROOT_MODE 0666 ++#define YAFFS_LOSTNFOUND_MODE 0666 ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)) ++#define Y_CURRENT_TIME CURRENT_TIME.tv_sec ++#define Y_TIME_CONVERT(x) (x).tv_sec ++#else ++#define Y_CURRENT_TIME CURRENT_TIME ++#define Y_TIME_CONVERT(x) (x) ++#endif ++ ++#define yaffs_SumCompare(x,y) ((x) == (y)) ++#define yaffs_strcmp(a,b) strcmp(a,b) ++ ++#define TENDSTR "\n" ++#define TSTR(x) KERN_WARNING x ++#define TCONT(x) x ++#define TOUT(p) printk p ++ ++#define yaffs_trace(mask, fmt, args...) \ ++ do { if ((mask) & (yaffs_traceMask|YAFFS_TRACE_ERROR)) \ ++ printk(KERN_WARNING "yaffs: " fmt, ## args); \ ++ } while (0) ++ ++#define compile_time_assertion(assertion) \ ++ ({ int x = __builtin_choose_expr(assertion, 0, (void)0); (void) x; }) ++ ++#elif defined CONFIG_YAFFS_DIRECT ++ ++#define MTD_VERSION_CODE MTD_VERSION(2,6,22) ++ ++/* Direct interface */ ++#include "ydirectenv.h" ++ ++#elif defined CONFIG_YAFFS_UTIL ++ ++/* Stuff for YAFFS utilities */ ++ ++#include "stdlib.h" ++#include "stdio.h" ++#include "string.h" ++ ++#include "devextras.h" ++ ++#define YMALLOC(x) malloc(x) ++#define YFREE(x) free(x) ++#define YMALLOC_ALT(x) malloc(x) ++#define YFREE_ALT(x) free(x) ++ ++#define YCHAR char ++#define YUCHAR unsigned char ++#define _Y(x) x ++#define yaffs_strcat(a,b) strcat(a,b) ++#define yaffs_strcpy(a,b) strcpy(a,b) ++#define yaffs_strncpy(a,b,c) strncpy(a,b,c) ++#define yaffs_strlen(s) strlen(s) ++#define yaffs_sprintf sprintf ++#define yaffs_toupper(a) toupper(a) ++ ++#define Y_INLINE inline ++ ++/* #define YINFO(s) YPRINTF(( __FILE__ " %d %s\n",__LINE__,s)) */ ++/* #define YALERT(s) YINFO(s) */ ++ ++#define TENDSTR "\n" ++#define TSTR(x) x ++#define TOUT(p) printf p ++ ++#define YAFFS_LOSTNFOUND_NAME "lost+found" ++#define YAFFS_LOSTNFOUND_PREFIX "obj" ++/* #define YPRINTF(x) printf x */ ++ ++#define YAFFS_ROOT_MODE 0666 ++#define YAFFS_LOSTNFOUND_MODE 0666 ++ ++#define yaffs_SumCompare(x,y) ((x) == (y)) ++#define yaffs_strcmp(a,b) strcmp(a,b) ++ ++#else ++/* Should have specified a configuration type */ ++#error Unknown configuration ++ ++#endif ++ ++/* see yaffs_fs.c */ ++extern unsigned int yaffs_traceMask; ++extern unsigned int yaffs_wr_attempts; ++ ++/* ++ * Tracing flags. ++ * The flags masked in YAFFS_TRACE_ALWAYS are always traced. ++ */ ++ ++#define YAFFS_TRACE_OS 0x00000002 ++#define YAFFS_TRACE_ALLOCATE 0x00000004 ++#define YAFFS_TRACE_SCAN 0x00000008 ++#define YAFFS_TRACE_BAD_BLOCKS 0x00000010 ++#define YAFFS_TRACE_ERASE 0x00000020 ++#define YAFFS_TRACE_GC 0x00000040 ++#define YAFFS_TRACE_WRITE 0x00000080 ++#define YAFFS_TRACE_TRACING 0x00000100 ++#define YAFFS_TRACE_DELETION 0x00000200 ++#define YAFFS_TRACE_BUFFERS 0x00000400 ++#define YAFFS_TRACE_NANDACCESS 0x00000800 ++#define YAFFS_TRACE_GC_DETAIL 0x00001000 ++#define YAFFS_TRACE_SCAN_DEBUG 0x00002000 ++#define YAFFS_TRACE_MTD 0x00004000 ++#define YAFFS_TRACE_CHECKPOINT 0x00008000 ++ ++#define YAFFS_TRACE_VERIFY 0x00010000 ++#define YAFFS_TRACE_VERIFY_NAND 0x00020000 ++#define YAFFS_TRACE_VERIFY_FULL 0x00040000 ++#define YAFFS_TRACE_VERIFY_ALL 0x000F0000 ++ ++ ++#define YAFFS_TRACE_ERROR 0x40000000 ++#define YAFFS_TRACE_BUG 0x80000000 ++#define YAFFS_TRACE_ALWAYS 0xF0000000 ++ ++ ++#define T(mask,p) do{ if((mask) & (yaffs_traceMask | YAFFS_TRACE_ALWAYS)) TOUT(p);} while(0) ++ ++#ifndef YBUG ++#define YBUG() do {T(YAFFS_TRACE_BUG,(TSTR("==>> yaffs bug: " __FILE__ " %d" TENDSTR),__LINE__));} while(0) ++#endif ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/include/linux/i2c-id.h linux-2.6.28.6/include/linux/i2c-id.h +--- linux-2.6.28/include/linux/i2c-id.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/include/linux/i2c-id.h 2009-10-21 21:23:33.000000000 +0200 +@@ -81,6 +81,9 @@ + #define I2C_DRIVERID_CS4270 94 /* Cirrus Logic 4270 audio codec */ + #define I2C_DRIVERID_M52790 95 /* Mitsubishi M52790SP/FP AV switch */ + #define I2C_DRIVERID_CS5345 96 /* cs5345 audio processor */ ++#define I2C_DRIVERID_S5K3BA 501 /* Samsung S5K3BA CMOS Image Sensor */ ++#define I2C_DRIVERID_S5K4BA 502 /* Samsung S5K4BA CMOS Image Sensor */ ++#define I2C_DRIVERID_OV965X 503 /* OVT OV965X CMOS Image Sensor */ + + #define I2C_DRIVERID_OV7670 1048 /* Omnivision 7670 camera */ + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/include/linux/mmc/host.h linux-2.6.28.6/include/linux/mmc/host.h +--- linux-2.6.28/include/linux/mmc/host.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/include/linux/mmc/host.h 2009-04-30 09:36:39.000000000 +0200 +@@ -41,6 +41,7 @@ + + #define MMC_BUS_WIDTH_1 0 + #define MMC_BUS_WIDTH_4 2 ++#define MMC_BUS_WIDTH_8 3 + + unsigned char timing; /* timing specification used */ + +@@ -116,6 +117,9 @@ + #define MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */ + #define MMC_CAP_SPI (1 << 4) /* Talks only SPI protocols */ + #define MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */ ++#define MMC_CAP_8_BIT_DATA (1 << 6) /* Can the host do 8 bit transfers */ ++#define MMC_CAP_ON_BOARD (1 << 7) /* Do not need to rescan after bootup */ ++#define MMC_CAP_BOOT_ONTHEFLY (1 << 8) /* Can detect device at boot time */ + + /* host specific block data */ + unsigned int max_seg_size; /* see blk_queue_max_segment_size */ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/include/linux/mmzone.h linux-2.6.28.6/include/linux/mmzone.h +--- linux-2.6.28/include/linux/mmzone.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/include/linux/mmzone.h 2009-04-30 09:36:39.000000000 +0200 +@@ -21,7 +21,7 @@ + + /* Free memory management - zoned buddy allocator. */ + #ifndef CONFIG_FORCE_MAX_ZONEORDER +-#define MAX_ORDER 11 ++#define MAX_ORDER 12 + #else + #define MAX_ORDER CONFIG_FORCE_MAX_ZONEORDER + #endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/include/linux/serial_core.h linux-2.6.28.6/include/linux/serial_core.h +--- linux-2.6.28/include/linux/serial_core.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/include/linux/serial_core.h 2009-04-30 09:36:39.000000000 +0200 +@@ -158,6 +159,8 @@ + /* SH-SCI */ + #define PORT_SCIFA 83 + ++#define PORT_S3C6400 255 ++ + #ifdef __KERNEL__ + + #include +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/include/linux/spi/spi.h linux-2.6.28.6/include/linux/spi/spi.h +--- linux-2.6.28/include/linux/spi/spi.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/include/linux/spi/spi.h 2009-04-30 09:36:40.000000000 +0200 +@@ -78,6 +78,10 @@ + #define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ + #define SPI_3WIRE 0x10 /* SI/SO signals shared */ + #define SPI_LOOP 0x20 /* loopback mode */ ++#define SPI_SLAVE 0x40 /* SLAVE mode if this bit is set */ ++ ++#define SPIDEV_MAX_BUFFSIZE 16384 ++ + u8 bits_per_word; + int irq; + void *controller_state; +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/include/linux/spi/spidev.h linux-2.6.28.6/include/linux/spi/spidev.h +--- linux-2.6.28/include/linux/spi/spidev.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/include/linux/spi/spidev.h 2009-04-30 09:36:40.000000000 +0200 +@@ -39,6 +39,9 @@ + #define SPI_LSB_FIRST 0x08 + #define SPI_3WIRE 0x10 + #define SPI_LOOP 0x20 ++#define SPI_SLAVE 0x40 /* SLAVE mode if this bit is set */ ++ ++#define SPIDEV_MAX_BUFFSIZE 16384 + + /*---------------------------------------------------------------------------*/ + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/include/media/v4l2-dev.h linux-2.6.28.6/include/media/v4l2-dev.h +--- linux-2.6.28/include/media/v4l2-dev.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/include/media/v4l2-dev.h 2009-04-30 09:36:40.000000000 +0200 +@@ -48,6 +48,11 @@ + int vfl_type; + int minor; + u16 num; ++ ++ /* added for TV */ ++ int type2; ++ int users; ++ + /* attribute to differentiate multiple indices on one physical device */ + int index; + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/include/sound/soc-dapm.h linux-2.6.28.6/include/sound/soc-dapm.h +--- linux-2.6.28/include/sound/soc-dapm.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/include/sound/soc-dapm.h 2009-04-30 09:36:40.000000000 +0200 +@@ -237,6 +237,11 @@ + /* dapm sys fs - used by the core */ + int snd_soc_dapm_sys_add(struct device *dev); + ++/* dapm audio endpoint control */ ++int snd_soc_dapm_set_endpoint(struct snd_soc_codec *codec, ++ char *pin, int status); ++int snd_soc_dapm_sync_endpoints(struct snd_soc_codec *codec); ++ + /* dapm audio pin control and status */ + int snd_soc_dapm_enable_pin(struct snd_soc_codec *codec, char *pin); + int snd_soc_dapm_disable_pin(struct snd_soc_codec *codec, char *pin); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/include/sound/soc.h linux-2.6.28.6/include/sound/soc.h +--- linux-2.6.28/include/sound/soc.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/include/sound/soc.h 2009-04-30 09:36:40.000000000 +0200 +@@ -430,6 +430,8 @@ + struct list_head dapm_paths; + enum snd_soc_bias_level bias_level; + enum snd_soc_bias_level suspend_bias_level; ++ unsigned int dapm_state; ++ unsigned int suspend_dapm_state; + struct delayed_work delayed_work; + + /* codec DAI's */ +Binary files linux-2.6.28/scripts/FriendlyARM.cpio and linux-2.6.28.6/scripts/FriendlyARM.cpio differ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/Kconfig linux-2.6.28.6/sound/soc/Kconfig +--- linux-2.6.28/sound/soc/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/Kconfig 2009-04-30 09:36:40.000000000 +0200 +@@ -28,6 +28,8 @@ + source "sound/soc/au1x/Kconfig" + source "sound/soc/pxa/Kconfig" + source "sound/soc/s3c24xx/Kconfig" ++source "sound/soc/s3c64xx/Kconfig" ++source "sound/soc/s5pc1xx/Kconfig" + source "sound/soc/sh/Kconfig" + source "sound/soc/fsl/Kconfig" + source "sound/soc/davinci/Kconfig" +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/Makefile linux-2.6.28.6/sound/soc/Makefile +--- linux-2.6.28/sound/soc/Makefile 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/Makefile 2009-04-30 09:36:40.000000000 +0200 +@@ -1,5 +1,5 @@ + snd-soc-core-objs := soc-core.o soc-dapm.o + + obj-$(CONFIG_SND_SOC) += snd-soc-core.o +-obj-$(CONFIG_SND_SOC) += codecs/ at32/ at91/ pxa/ s3c24xx/ sh/ fsl/ davinci/ ++obj-$(CONFIG_SND_SOC) += codecs/ at32/ at91/ pxa/ s3c24xx/ s3c64xx/ s5pc1xx/ sh/ fsl/ davinci/ + obj-$(CONFIG_SND_SOC) += omap/ au1x/ blackfin/ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/codecs/Kconfig linux-2.6.28.6/sound/soc/codecs/Kconfig +--- linux-2.6.28/sound/soc/codecs/Kconfig 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/codecs/Kconfig 2009-04-30 09:36:40.000000000 +0200 +@@ -20,6 +20,7 @@ + select SND_SOC_WM8903 + select SND_SOC_WM8971 + select SND_SOC_WM8990 ++ select SND_SOC_S5M8751 + help + Normally ASoC codec drivers are only built if a machine driver which + uses them is also built since they are only usable with a machine +@@ -110,3 +111,7 @@ + + config SND_SOC_WM9713 + tristate ++ ++config SND_SOC_S5M8751 ++ tristate ++ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/codecs/Makefile linux-2.6.28.6/sound/soc/codecs/Makefile +--- linux-2.6.28/sound/soc/codecs/Makefile 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/codecs/Makefile 2009-04-30 09:36:40.000000000 +0200 +@@ -19,6 +19,7 @@ + snd-soc-wm8990-objs := wm8990.o + snd-soc-wm9712-objs := wm9712.o + snd-soc-wm9713-objs := wm9713.o ++snd-soc-s5m8751-objs := s5m8751.o + + obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o + obj-$(CONFIG_SND_SOC_AD1980) += snd-soc-ad1980.o +@@ -41,3 +42,5 @@ + obj-$(CONFIG_SND_SOC_WM8990) += snd-soc-wm8990.o + obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o + obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o ++ ++obj-$(CONFIG_SND_SOC_S5M8751) += snd-soc-s5m8751.o +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/codecs/s5m8751.c linux-2.6.28.6/sound/soc/codecs/s5m8751.c +--- linux-2.6.28/sound/soc/codecs/s5m8751.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/codecs/s5m8751.c 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,666 @@ ++/* ++ * s5m8751.c -- S5M8751 Power-Audio IC ALSA Soc Audio driver ++ * ++ * Copyright 2009 Samsung Electronics. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "s5m8751.h" ++ ++#define S5M8751_VERSION "0.2" ++ ++/* S5M8751 is activated only in XXX SLAVE MODE XXX ++ * 8kHz ~ 96kHz sample rate. Auto/Manual ??? ++ * I2S, Lj, Rj, PCM short frame sync or PCM long frame sync formats. ++ * Slave addr:- 0xD1-Read, 0xD0-Write ++ * XXX This driver supports only SPEAKER-OUT mode, others are easy to implement XXX ++ * */ ++ ++static const u16 s5m8751_reg[S5M8751_NUMREGS]; ++ ++/* ++ * read s5m8751 register cache ++ */ ++static inline unsigned int s5m8751_read_reg_cache(struct snd_soc_codec *codec, ++ unsigned int reg) ++{ ++ u16 *cache = codec->reg_cache; ++ BUG_ON(reg < S5M8751_DA_PDB1); ++ BUG_ON(reg > S5M8751_LINE_CTRL); ++ return cache[reg]; ++} ++ ++/* Fills the data in cache and returns only operation status. ++ * 1 for success, -EIO for failure. ++ */ ++static int s5m8751_read(struct snd_soc_codec *codec, ++ unsigned int reg) ++{ ++ u8 data; ++ u16 *cache = codec->reg_cache; ++ ++ data = reg; ++ ++ if (codec->hw_write(codec->control_data, &data, 1) != 1){ ++ return -EIO; ++ } ++ ++ if (codec->hw_read(codec->control_data, &data, 1) != 1){ ++ return -EIO; ++ } ++ ++ cache[reg] = data; /* Update the cache */ ++ ++ return 1; ++} ++ ++/* ++ * write s5m8751 register cache ++ */ ++static inline void s5m8751_write_reg_cache(struct snd_soc_codec *codec, ++ unsigned int reg, unsigned int value) ++{ ++ u16 *cache = codec->reg_cache; ++ ++ if(reg == S5M8751_IN1_CTRL1) ++ value &= ~(1<<6); /* Reset is cleared automatically by the codec */ ++ ++ cache[reg] = value; ++} ++ ++/* ++ * write to the S5M8751 register space ++ */ ++/* Fills the data in cache and returns only operation status. ++ * 1 for success, 0 for failure. ++ */ ++static int s5m8751_write(struct snd_soc_codec *codec, unsigned int reg, ++ unsigned int value) ++{ ++ u8 data[2]; ++ ++ BUG_ON(reg < S5M8751_DA_PDB1); ++ BUG_ON(reg > S5M8751_LINE_CTRL); ++ ++ data[0] = reg & 0xff; ++ data[1] = value & 0xff; ++ ++ if (codec->hw_write(codec->control_data, data, 2) == 2){ ++ s5m8751_write_reg_cache(codec, reg, value); ++ return 0; ++ }else{ ++ return -EIO; ++ } ++} ++ ++static const struct snd_kcontrol_new s5m8751_snd_controls[] = { ++ SOC_DOUBLE_R("HeadPhone Volume", S5M8751_HP_VOL1, S5M8751_HP_VOL1, 0, 0x7f, 1), ++ SOC_DOUBLE_R("Line-In Gain", S5M8751_DA_LGAIN, S5M8751_DA_RGAIN, 0, 0x7f, 1), ++ SOC_DOUBLE_R("DAC Volume", S5M8751_DA_VOLL, S5M8751_DA_VOLR, 0, 0xff, 1), ++ SOC_SINGLE("Speaker Slope", S5M8751_SPK_SLOPE, 0, 0xf, 1), ++ SOC_SINGLE("DAC Mute", S5M8751_DA_DIG2, 7, 1, 0), ++ SOC_SINGLE("Mute Dither", S5M8751_DA_DIG2, 6, 1, 0), ++ SOC_SINGLE("Dither Level", S5M8751_DA_DIG2, 3, 7, 0), ++ SOC_SINGLE("Soft Limit", S5M8751_DA_LIM1, 7, 1, 0), ++ SOC_SINGLE("Limit Thrsh", S5M8751_DA_LIM1, 0, 0x7f, 1), ++ SOC_SINGLE("Attack", S5M8751_DA_LIM2, 4, 0xf, 0), ++ SOC_SINGLE("Release", S5M8751_DA_LIM2, 0, 0xf, 0), ++}; ++ ++/* Add non-DAPM controls */ ++static int s5m8751_add_controls(struct snd_soc_codec *codec) ++{ ++ int err, i; ++ ++ for (i = 0; i < ARRAY_SIZE(s5m8751_snd_controls); i++) { ++ err = snd_ctl_add(codec->card, ++ snd_soc_cnew(&s5m8751_snd_controls[i], ++ codec, NULL)); ++ if (err < 0) ++ return err; ++ } ++ return 0; ++} ++ ++static const struct snd_soc_dapm_widget s5m8751_dapm_widgets[] = { ++ SND_SOC_DAPM_DAC("RL-Mute", "Playback", S5M8751_AMP_MUTE, 0, 1), ++ SND_SOC_DAPM_DAC("LL-Mute", "Playback", S5M8751_AMP_MUTE, 1, 1), ++ SND_SOC_DAPM_DAC("RH-Mute", "Playback", S5M8751_AMP_MUTE, 2, 1), ++ SND_SOC_DAPM_DAC("LH-Mute", "Playback", S5M8751_AMP_MUTE, 3, 1), ++ SND_SOC_DAPM_DAC("SPK-Mute", "Playback", S5M8751_AMP_MUTE, 4, 1), ++ SND_SOC_DAPM_OUTPUT("RL"), ++ SND_SOC_DAPM_OUTPUT("LL"), ++ SND_SOC_DAPM_OUTPUT("RH"), ++ SND_SOC_DAPM_OUTPUT("LH"), ++ SND_SOC_DAPM_OUTPUT("SPK"), ++}; ++ ++static const struct snd_soc_dapm_route audio_map[] = { ++ { "RL", NULL, "RL-Mute" }, ++ { "LL", NULL, "LL-Mute" }, ++ { "RH", NULL, "RH-Mute" }, ++ { "LH", NULL, "LH-Mute" }, ++ { "SPK", NULL, "SPK-Mute" }, ++}; ++ ++static int s5m8751_add_widgets(struct snd_soc_codec *codec) ++{ ++ snd_soc_dapm_new_controls(codec, s5m8751_dapm_widgets, ++ ARRAY_SIZE(s5m8751_dapm_widgets)); ++ snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); ++ snd_soc_dapm_new_widgets(codec); ++ ++ return 0; ++} ++ ++/* ++ * Set PCM DAI bit size and sample rate. ++ */ ++static int s5m8751_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_device *socdev = rtd->socdev; ++ struct snd_soc_codec *codec = socdev->codec; ++ unsigned int in1_ctrl2, in1_ctrl1; ++ ++ in1_ctrl1 = s5m8751_read_reg_cache(codec, S5M8751_IN1_CTRL1); ++ in1_ctrl1 &= ~(0xf<<2); /* Sampling Rate field */ ++ ++ in1_ctrl2 = s5m8751_read_reg_cache(codec, S5M8751_IN1_CTRL2); ++ in1_ctrl2 &= ~(0x3<<0); /* I2S data length field */ ++ ++ /* bit size */ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S16_LE: ++ in1_ctrl2 |= (0x0<<0); break; ++ case SNDRV_PCM_FORMAT_S18_3LE: ++ in1_ctrl2 |= (0x1<<0); break; ++ case SNDRV_PCM_FORMAT_S20_3LE: ++ in1_ctrl2 |= (0x2<<0); break; ++ case SNDRV_PCM_FORMAT_S24_LE: ++ in1_ctrl2 |= (0x3<<0); break; ++ default: /* Doesn't it support SNDRV_PCM_FORMAT_S8 ?! */ ++ return -EINVAL; ++ } ++ ++ /* XXX What about bits in DA_DIG1 ? XXX */ ++ switch (params_rate(params)) { ++ case 8000: ++ in1_ctrl1 |= (0x0<<2); break; ++ case 11025: ++ in1_ctrl1 |= (0x1<<2); break; ++ case 16000: ++ in1_ctrl1 |= (0x2<<2); break; ++ case 22050: ++ in1_ctrl1 |= (0x3<<2); break; ++ case 32000: ++ in1_ctrl1 |= (0x4<<2); break; ++ case 44100: ++ in1_ctrl1 |= (0x5<<2); break; ++ case 48000: ++ in1_ctrl1 |= (0x6<<2); break; ++ case 64000: ++ in1_ctrl1 |= (0x7<<2); break; ++ case 88200: ++ in1_ctrl1 |= (0x8<<2); break; ++ case 96000: ++ in1_ctrl1 |= (0x9<<2); break; ++ default: ++ return -EINVAL; ++ } ++ ++// in1_ctrl1 &= ~(1<<7); /* Power down */ ++ s5m8751_write(codec, S5M8751_IN1_CTRL1, in1_ctrl1); ++ ++ s5m8751_write(codec, S5M8751_IN1_CTRL2, in1_ctrl2); ++ ++// in1_ctrl1 |= (1<<7); /* Power up */ ++// s5m8751_write(codec, S5M8751_IN1_CTRL1, in1_ctrl1); ++ ++ return 0; ++} ++ ++static int s5m8751_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) ++{ ++ struct snd_soc_codec *codec = codec_dai->codec; ++ unsigned int in1_ctrl2, in1_ctrl1; ++ ++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { ++ /* S5M8751 works only in SLAVE mode */ ++ case SND_SOC_DAIFMT_CBS_CFS: break; /* Nothing to do, already setup */ ++ default: ++ printk("Mst-Slv combo(%d) not supported!\n", fmt & SND_SOC_DAIFMT_MASTER_MASK); ++ return -EINVAL; ++ } ++ ++ in1_ctrl2 = s5m8751_read_reg_cache(codec, S5M8751_IN1_CTRL2); ++ in1_ctrl2 &= ~(0x3<<2); ++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { ++ case SND_SOC_DAIFMT_I2S: ++ in1_ctrl2 |= (0x0<<2); break; ++ case SND_SOC_DAIFMT_LEFT_J: ++ in1_ctrl2 |= (0x1<<2); break; ++ case SND_SOC_DAIFMT_RIGHT_J: ++ in1_ctrl2 |= (0x2<<2); break; ++ default: ++ printk("DAIFmt(%d) not supported!\n", fmt & SND_SOC_DAIFMT_FORMAT_MASK); ++ return -EINVAL; ++ } ++ ++ in1_ctrl2 &= ~(0x1<<4); /* LRCLK Polarity */ ++ in1_ctrl1 = s5m8751_read_reg_cache(codec, S5M8751_IN1_CTRL1); ++ in1_ctrl1 &= ~(0x1<<1); /* BCLK Polarity */ ++ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { ++ case SND_SOC_DAIFMT_NB_NF: ++ in1_ctrl1 |= (0x0<<1); ++ in1_ctrl2 |= (0x0<<4); ++ break; ++ ++ case SND_SOC_DAIFMT_IB_IF: ++ in1_ctrl1 |= (0x1<<1); ++ in1_ctrl2 |= (0x1<<4); ++ break; ++ ++ case SND_SOC_DAIFMT_IB_NF: ++ in1_ctrl1 |= (0x1<<1); ++ in1_ctrl2 |= (0x0<<4); ++ break; ++ ++ case SND_SOC_DAIFMT_NB_IF: ++ in1_ctrl1 |= (0x0<<1); ++ in1_ctrl2 |= (0x1<<4); ++ break; ++ ++ default: ++ printk("Inv-combo(%d) not supported!\n", fmt & SND_SOC_DAIFMT_FORMAT_MASK); ++ return -EINVAL; ++ } ++ ++ s5m8751_write(codec, S5M8751_IN1_CTRL1, in1_ctrl1); ++ s5m8751_write(codec, S5M8751_IN1_CTRL2, in1_ctrl2); ++ return 0; ++} ++ ++static int s5m8751_set_clkdiv(struct snd_soc_dai *codec_dai, ++ int div_id, int val) ++{ ++ struct snd_soc_codec *codec = codec_dai->codec; ++ unsigned int in1_ctrl1, in1_ctrl2; ++ ++ in1_ctrl2 = s5m8751_read_reg_cache(codec, S5M8751_IN1_CTRL2); ++ in1_ctrl2 &= ~(0x3<<5); /* XFS field */ ++ switch (div_id) { ++ case S5M8751_BCLK: ++ switch(val){ ++ case 32: in1_ctrl2 |= (0x0<<5); break; ++ case 48: in1_ctrl2 |= (0x1<<5); break; ++ case 64: in1_ctrl2 |= (0x2<<5); break; ++ default: return -EINVAL; ++ } ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ in1_ctrl1 = s5m8751_read_reg_cache(codec, S5M8751_IN1_CTRL1); ++ s5m8751_write(codec, S5M8751_IN1_CTRL1, in1_ctrl1); ++ ++ s5m8751_write(codec, S5M8751_IN1_CTRL2, in1_ctrl2); ++ ++ return 0; ++} ++ ++static int s5m8751_set_bias_level(struct snd_soc_codec *codec, ++ enum snd_soc_bias_level level) ++{ ++ u16 amp_en, amp_mute_off, in1_ctrl1; ++ ++ in1_ctrl1 = s5m8751_read_reg_cache(codec, S5M8751_IN1_CTRL1); ++ amp_en = s5m8751_read_reg_cache(codec, S5M8751_AMP_EN); ++ amp_mute_off = s5m8751_read_reg_cache(codec, S5M8751_AMP_MUTE); ++ ++ amp_en &= ~((0x7<<2)|(0x1<<6)); ++ amp_mute_off &= ~((0x3<<2)|(0x1<<4)); ++ ++ s5m8751_write(codec, S5M8751_AMP_MUTE, amp_mute_off); ++ mdelay(30); ++ s5m8751_write(codec, S5M8751_AMP_EN, amp_en); ++ ++ switch (level) { ++ case SND_SOC_BIAS_ON: ++ in1_ctrl1 &= ~(0x1<<7); ++ s5m8751_write(codec, S5M8751_IN1_CTRL1, in1_ctrl1); ++ in1_ctrl1 |= (0x1<<7); ++ s5m8751_write(codec, S5M8751_IN1_CTRL1, in1_ctrl1); ++#if defined(CONFIG_SOUND_S5M8751_OUTPUT_STREAM_HP_OUT) ++ amp_mute_off |= (0x3<<2); ++ amp_en |= (0x7<<2); ++#endif ++ ++#if defined(CONFIG_SOUND_S5M8751_OUTPUT_STREAM_SPK_OUT) ++ amp_mute_off |= (0x1<<4); ++ amp_en |= (0x1<<6); ++#endif ++ s5m8751_write(codec, S5M8751_AMP_EN, amp_en); ++ s5m8751_write(codec, S5M8751_AMP_MUTE, amp_mute_off); ++ break; ++ case SND_SOC_BIAS_PREPARE: ++ case SND_SOC_BIAS_STANDBY: ++ amp_en &= ~((0x7<<2)|(0x1<<6)); ++ amp_mute_off &= ~((0x3<<2)|(0x1<<4)); ++ s5m8751_write(codec, S5M8751_AMP_MUTE, amp_mute_off); ++ s5m8751_write(codec, S5M8751_AMP_EN, amp_en); ++ in1_ctrl1 &= ~(1<<7); ++ in1_ctrl1 &= ~(1<<7); ++ s5m8751_write(codec, S5M8751_IN1_CTRL1, in1_ctrl1); ++ break; ++ case SND_SOC_BIAS_OFF: ++ amp_en &= ~((0x7<<2)|(0x1<<6)); ++ amp_mute_off &= ~((0x3<<2)|(0x1<<4)); ++ s5m8751_write(codec, S5M8751_AMP_MUTE, amp_mute_off); ++ s5m8751_write(codec, S5M8751_AMP_EN, amp_en); ++ in1_ctrl1 &= ~(1<<7); ++ s5m8751_write(codec, S5M8751_IN1_CTRL1, in1_ctrl1); ++ break; ++ } ++ ++ codec->bias_level = level; ++ return 0; ++} ++ ++/* ++ * S5M8751 can work only in Slave mode. ++ * S5M8751 supports only Playback, not Capture! ++ * S5M8751 supports two i/f's: I2S and PCM. Only I2S is implemented in this driver. ++ */ ++#define S5M8751_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \ ++ SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE) ++struct snd_soc_dai s5m8751_dai = { ++ .name = "S5M8751-I2S", ++ .id = 0, ++ .playback = { ++ .stream_name = "Playback", ++ .channels_min = 1, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_96000, ++ .formats = S5M8751_FORMATS, ++ }, ++ .ops = { ++ .hw_params = s5m8751_hw_params, ++ }, ++ .dai_ops = { ++ .set_fmt = s5m8751_set_dai_fmt, ++ .set_clkdiv = s5m8751_set_clkdiv, ++ }, ++}; ++EXPORT_SYMBOL_GPL(s5m8751_dai); ++ ++/* ++ * initialise the S5M8751 driver ++ * register the mixer and dsp interfaces with the kernel ++ */ ++static int s5m8751_init(struct snd_soc_device *socdev) ++{ ++ int ret = 0, val; ++ u16 *cache; ++ struct snd_soc_codec *codec = socdev->codec; ++ ++ codec->name = "S5M8751"; ++ codec->owner = THIS_MODULE; ++ codec->read = s5m8751_read_reg_cache; ++ codec->write = s5m8751_write; ++ codec->set_bias_level = s5m8751_set_bias_level; ++ codec->dai = &s5m8751_dai; ++ codec->num_dai = 1; ++ codec->reg_cache_size = ARRAY_SIZE(s5m8751_reg); ++ codec->reg_cache = kmemdup(s5m8751_reg, sizeof(s5m8751_reg), GFP_KERNEL); ++ ++ if (codec->reg_cache == NULL) ++ return -ENOMEM; ++ ++ /* Fill the reg cache */ ++ cache = codec->reg_cache; ++ for(val=S5M8751_DA_PDB1; val<=S5M8751_LINE_CTRL; val++){ /* Don't use Power Mngmnt regs here */ ++ while(s5m8751_read(codec, val) == -EIO) ++ printk(KERN_WARNING "Read failed! "); ++ } ++ ++#if defined(CONFIG_SOUND_S5M8751_OUTPUT_STREAM_HP_OUT) ++ val = (0x3d<<0); /* PowerOn */ ++ s5m8751_write(codec, S5M8751_DA_PDB1, val); ++ ++ val = (0x21<<0); /* Enable */ ++ s5m8751_write(codec, S5M8751_DA_AMIX1, val); ++ ++ val = 0; /* XXX TODO Disable all for the time being TODO XXX */ ++ s5m8751_write(codec, S5M8751_DA_AMIX2, val); ++ ++ val = 0x30; ++ s5m8751_write(codec, S5M8751_DA_VOLL, val); ++ s5m8751_write(codec, S5M8751_DA_VOLR, val); ++ ++ val = 0x28; ++ s5m8751_write(codec, S5M8751_AMP_CTRL, val); ++#endif ++ ++#if defined(CONFIG_SOUND_S5M8751_OUTPUT_STREAM_SPK_OUT) ++ val = (0x3a<<0); /* PowerOn */ ++ s5m8751_write(codec, S5M8751_DA_PDB1, val); ++ ++ val = (0x12<<0); /* Enable */ ++ s5m8751_write(codec, S5M8751_DA_AMIX1, val); ++ ++ val = 0; /* XXX TODO Disable all for the time being TODO XXX */ ++ s5m8751_write(codec, S5M8751_DA_AMIX2, val); ++ ++ val = 0x18; ++ s5m8751_write(codec, S5M8751_DA_VOLL, val); ++ s5m8751_write(codec, S5M8751_DA_VOLR, val); ++ ++ val = 0x01; /* Gradual Slope */ ++ s5m8751_write(codec, S5M8751_SPK_SLOPE, val); ++ val = 0x05; ++ s5m8751_write(codec, S5M8751_SPK_DT, val); ++ val = 0x00; ++ s5m8751_write(codec, S5M8751_SPK_S2D, val); ++#endif ++ ++ /* TODO XXX What about DA_ANA, DA_DWA? TODO XXX */ ++ codec->bias_level = SND_SOC_BIAS_OFF; ++ ++ /* register pcms */ ++ ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); ++ if (ret < 0) { ++ printk(KERN_ERR "s5m8751: failed to create pcms\n"); ++ goto pcm_err; ++ } ++ ++ s5m8751_add_controls(codec); ++ s5m8751_add_widgets(codec); ++ ++ ret = snd_soc_register_card(socdev); ++ if (ret < 0) { ++ printk(KERN_ERR "s5m8751: failed to register card\n"); ++ goto card_err; ++ } ++ return ret; ++ ++card_err: ++ snd_soc_free_pcms(socdev); ++ snd_soc_dapm_free(socdev); ++pcm_err: ++ kfree(codec->reg_cache); ++ return ret; ++} ++ ++/* If the i2c layer weren't so broken, we could pass this kind of data ++ around */ ++static struct snd_soc_device *s5m8751_socdev; ++ ++#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) ++ ++static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END }; ++ ++/* Magic definition of all other variables and things */ ++I2C_CLIENT_INSMOD; ++ ++static struct i2c_driver s5m8751_i2c_driver; ++static struct i2c_client client_template; ++ ++static int s5m8751_codec_probe(struct i2c_adapter *adap, int addr, int kind) ++{ ++ struct snd_soc_device *socdev = s5m8751_socdev; ++ struct s5m8751_setup_data *setup = socdev->codec_data; ++ struct snd_soc_codec *codec = socdev->codec; ++ struct i2c_client *i2c; ++ int ret; ++ ++ if (addr != setup->i2c_address){ ++ return -ENODEV; ++ } ++ ++ client_template.adapter = adap; ++ client_template.addr = addr; ++ ++ i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL); ++ if (i2c == NULL) { ++ kfree(codec); ++ return -ENOMEM; ++ } ++ i2c_set_clientdata(i2c, codec); ++ codec->control_data = i2c; ++ ++ ret = i2c_attach_client(i2c); ++ if (ret < 0) { ++ dev_err(&i2c->dev, "failed to attach codec at addr %x\n", addr); ++ goto err; ++ } ++ ++ ret = s5m8751_init(socdev); ++ if (ret < 0) { ++ dev_err(&i2c->dev, "failed to initialise S5M8751\n"); ++ goto err; ++ } ++ ++ return ret; ++ ++err: ++ kfree(codec); ++ kfree(i2c); ++ return ret; ++} ++ ++static int s5m8751_i2c_detach(struct i2c_client *client) ++{ ++ struct snd_soc_codec *codec = i2c_get_clientdata(client); ++ i2c_detach_client(client); ++ kfree(codec->reg_cache); ++ kfree(client); ++ return 0; ++} ++ ++static int s5m8751_i2c_attach(struct i2c_adapter *adap) ++{ ++ return i2c_probe(adap, &addr_data, s5m8751_codec_probe); ++} ++ ++static struct i2c_driver s5m8751_i2c_driver = { ++ .driver = { ++ .name = "S5M8751 I2C Codec", ++ .owner = THIS_MODULE, ++ }, ++ .attach_adapter = s5m8751_i2c_attach, ++ .detach_client = s5m8751_i2c_detach, ++ .command = NULL, ++}; ++ ++static struct i2c_client client_template = { ++ .name = "S5M8751", ++ .driver = &s5m8751_i2c_driver, ++}; ++#endif ++ ++static int s5m8751_probe(struct platform_device *pdev) ++{ ++ struct snd_soc_device *socdev = platform_get_drvdata(pdev); ++ struct s5m8751_setup_data *setup; ++ struct snd_soc_codec *codec; ++ int ret = 0; ++ ++ pr_info("S5M8751 Audio Codec %s\n", S5M8751_VERSION); ++ ++ setup = socdev->codec_data; ++ codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); ++ if (codec == NULL) ++ return -ENOMEM; ++ ++ socdev->codec = codec; ++ mutex_init(&codec->mutex); ++ INIT_LIST_HEAD(&codec->dapm_widgets); ++ INIT_LIST_HEAD(&codec->dapm_paths); ++ s5m8751_socdev = socdev; ++ ++#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) ++ if (setup->i2c_address) { ++ normal_i2c[0] = setup->i2c_address; ++ codec->hw_write = (hw_write_t)i2c_master_send; ++ codec->hw_read = (hw_read_t)i2c_master_recv; ++ ret = i2c_add_driver(&s5m8751_i2c_driver); ++ if (ret != 0) ++ printk(KERN_ERR "can't add i2c driver"); ++ } ++#else ++ /* Add other interfaces here */ ++#endif ++ ++ return ret; ++} ++ ++/* power down chip */ ++static int s5m8751_remove(struct platform_device *pdev) ++{ ++ struct snd_soc_device *socdev = platform_get_drvdata(pdev); ++ struct snd_soc_codec *codec = socdev->codec; ++ ++ if (codec->control_data) ++ s5m8751_set_bias_level(codec, SND_SOC_BIAS_OFF); ++ snd_soc_free_pcms(socdev); ++ snd_soc_dapm_free(socdev); ++#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) ++ i2c_del_driver(&s5m8751_i2c_driver); ++#endif ++ kfree(codec); ++ ++ return 0; ++} ++ ++struct snd_soc_codec_device soc_codec_dev_s5m8751 = { ++ .probe = s5m8751_probe, ++ .remove = s5m8751_remove, ++}; ++EXPORT_SYMBOL_GPL(soc_codec_dev_s5m8751); ++ ++MODULE_DESCRIPTION("ASoC S5M8751 driver"); ++MODULE_AUTHOR("Jaswinder Singh "); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/codecs/s5m8751.h linux-2.6.28.6/sound/soc/codecs/s5m8751.h +--- linux-2.6.28/sound/soc/codecs/s5m8751.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/codecs/s5m8751.h 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,92 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#ifndef _S5M8751_H ++#define _S5M8751_H ++ ++/* S5M8751 register space */ ++#define S5M8751_IRQB_EVENT1 0x0 ++#define S5M8751_IRQB_EVENT2 0x1 ++#define S5M8751_IRQB_MASK1 0x2 ++#define S5M8751_IRQB_MASK2 0x3 ++#define S5M8751_ONOFF1 0x4 ++#define S5M8751_ONOFF2 0x5 ++#define S5M8751_ONOFF3 0x6 ++#define S5M8751_SLEEPCNTL1 0x7 ++#define S5M8751_SLEEPCNTL2 0x8 ++#define S5M8751_UVLO 0x9 ++#define S5M8751_LDO_AUDIO_VSET 0x0A ++#define S5M8751_LDO1_VSET 0x0B ++#define S5M8751_LDO2_VSET 0x0C ++#define S5M8751_LDO3_VSET 0x0D ++#define S5M8751_LDO4_VSET 0x0E ++#define S5M8751_LDO_MEMORY_VSET 0x0F ++#define S5M8751_BUCK1_V1_SET 0x10 ++#define S5M8751_BUCK1_V2_SET 0x11 ++#define S5M8751_BUCK2_V1_SET 0x12 ++#define S5M8751_BUCK2_V2_SET 0x13 ++#define S5M8751_WLED_CNTRL 0x14 ++#define S5M8751_CHG_IV_SET 0x15 ++#define S5M8751_CHG_CNTRL 0x16 ++#define S5M8751_DA_PDB1 0x17 ++#define S5M8751_DA_AMIX1 0x18 ++#define S5M8751_DA_AMIX2 0x19 ++#define S5M8751_DA_ANA 0x1A ++#define S5M8751_DA_DWA 0x1B ++#define S5M8751_DA_VOLL 0x1C ++#define S5M8751_DA_VOLR 0x1D ++#define S5M8751_DA_DIG1 0x1E ++#define S5M8751_DA_DIG2 0x1F ++#define S5M8751_DA_LIM1 0x20 ++#define S5M8751_DA_LIM2 0x21 ++#define S5M8751_DA_LOF 0x22 ++#define S5M8751_DA_ROF 0x23 ++#define S5M8751_DA_MUX 0x24 ++#define S5M8751_DA_LGAIN 0x25 ++#define S5M8751_DA_RGAIN 0x26 ++#define S5M8751_IN1_CTRL1 0x27 ++#define S5M8751_IN1_CTRL2 0x28 ++#define S5M8751_IN1_CTRL3 0x29 ++#define S5M8751_SLOT_L2 0x2A ++#define S5M8751_SLOT_L1 0x2B ++#define S5M8751_SLOT_R2 0x2C ++#define S5M8751_SLOT_R1 0x2D ++#define S5M8751_TSLOT 0x2E ++#define S5M8751_TEST 0x2F ++#define S5M8751_SPK_SLOPE 0x30 ++#define S5M8751_SPK_DT 0x31 ++#define S5M8751_SPK_S2D 0x32 ++#define S5M8751_SPK_CM 0x33 ++#define S5M8751_SPK_DUM 0x34 ++#define S5M8751_HP_VOL1 0x35 ++#define S5M8751_HP_VOL2 0x36 ++#define S5M8751_AMP_EN 0x37 ++#define S5M8751_AMP_MUTE 0x38 ++#define S5M8751_AMP_CTRL 0x39 ++#define S5M8751_AMP_VMID 0x3A ++#define S5M8751_LINE_CTRL 0x3B ++#define S5M8751_NUMREGS (S5M8751_LINE_CTRL + 1) ++ /* Careful, 7regs skipped */ ++#define S5M8751_CHIP_ID 0x43 ++#define S5M8751_STATUS 0x44 ++ ++#define S5M8751_SYSCLK 0 ++#define S5M8751_MCLK 1 ++#define S5M8751_BCLK 2 ++ ++#define MUTE_OFF 0 ++#define MUTE_ON 1 ++ ++struct s5m8751_setup_data { ++ unsigned short i2c_address; ++}; ++ ++extern struct snd_soc_dai s5m8751_dai; ++extern struct snd_soc_codec_device soc_codec_dev_s5m8751; ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/codecs/wm8580.c linux-2.6.28.6/sound/soc/codecs/wm8580.c +--- linux-2.6.28/sound/soc/codecs/wm8580.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/codecs/wm8580.c 2009-04-30 09:36:40.000000000 +0200 +@@ -262,6 +262,7 @@ + + static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1); + ++#if 0 + static int wm8580_out_vu(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) + { +@@ -288,6 +289,7 @@ + + return 0; + } ++#endif + + #define SOC_WM8580_OUT_DOUBLE_R_TLV(xname, reg_left, reg_right, shift, max, invert, tlv_array) \ + { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ +@@ -300,6 +302,7 @@ + ((max) << 12) | ((invert) << 20) | ((reg_right) << 24) } + + static const struct snd_kcontrol_new wm8580_snd_controls[] = { ++/* + SOC_WM8580_OUT_DOUBLE_R_TLV("DAC1 Playback Volume", + WM8580_DIGITAL_ATTENUATION_DACL1, + WM8580_DIGITAL_ATTENUATION_DACR1, +@@ -312,6 +315,20 @@ + WM8580_DIGITAL_ATTENUATION_DACL3, + WM8580_DIGITAL_ATTENUATION_DACR3, + 0, 0xff, 0, dac_tlv), ++*/ ++ ++SOC_DOUBLE_R_TLV("DAC1 Playback Volume", ++ WM8580_DIGITAL_ATTENUATION_DACL1, ++ WM8580_DIGITAL_ATTENUATION_DACR1, ++ 0, 0xff, 0, dac_tlv), ++SOC_DOUBLE_R_TLV("DAC2 Playback Volume", ++ WM8580_DIGITAL_ATTENUATION_DACL2, ++ WM8580_DIGITAL_ATTENUATION_DACR2, ++ 0, 0xff, 0, dac_tlv), ++SOC_DOUBLE_R_TLV("DAC3 Playback Volume", ++ WM8580_DIGITAL_ATTENUATION_DACL3, ++ WM8580_DIGITAL_ATTENUATION_DACR3, ++ 0, 0xff, 0, dac_tlv), + + SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0), + SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0), +@@ -796,19 +813,6 @@ + .rates = SNDRV_PCM_RATE_8000_192000, + .formats = WM8580_FORMATS, + }, +- .ops = { +- .hw_params = wm8580_paif_hw_params, +- }, +- .dai_ops = { +- .set_fmt = wm8580_set_paif_dai_fmt, +- .set_clkdiv = wm8580_set_dai_clkdiv, +- .set_pll = wm8580_set_dai_pll, +- .digital_mute = wm8580_digital_mute, +- }, +- }, +- { +- .name = "WM8580 PAIFTX", +- .id = 1, + .capture = { + .stream_name = "Capture", + .channels_min = 2, +@@ -823,6 +827,7 @@ + .set_fmt = wm8580_set_paif_dai_fmt, + .set_clkdiv = wm8580_set_dai_clkdiv, + .set_pll = wm8580_set_dai_pll, ++ .digital_mute = wm8580_digital_mute, + }, + }, + }; +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/codecs/wm8990.c linux-2.6.28.6/sound/soc/codecs/wm8990.c +--- linux-2.6.28/sound/soc/codecs/wm8990.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/codecs/wm8990.c 2009-04-30 09:36:40.000000000 +0200 +@@ -9,16 +9,21 @@ + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. ++ * ++ * Revision history ++ * 6th Mar 2008 Initial version. + */ + + #include + #include ++#include + #include + #include + #include + #include + #include + #include ++//#include + #include + #include + #include +@@ -30,7 +35,27 @@ + + #include "wm8990.h" + +-#define WM8990_VERSION "0.2" ++#define AUDIO_NAME "wm8990" ++#define WM8990_VERSION "0.1" ++ ++/* ++ * Debug ++ */ ++ ++#define WM8753_DEBUG 0 ++ ++#ifdef WM8753_DEBUG ++#define dbg(format, arg...) \ ++ printk(KERN_DEBUG AUDIO_NAME ": " format "\n" , ## arg) ++#else ++#define dbg(format, arg...) do {} while (0) ++#endif ++#define err(format, arg...) \ ++ printk(KERN_ERR AUDIO_NAME ": " format "\n" , ## arg) ++#define info(format, arg...) \ ++ printk(KERN_INFO AUDIO_NAME ": " format "\n" , ## arg) ++#define warn(format, arg...) \ ++ printk(KERN_WARNING AUDIO_NAME ": " format "\n" , ## arg) + + /* codec private data */ + struct wm8990_priv { +@@ -39,74 +64,11 @@ + }; + + /* +- * wm8990 register cache. Note that register 0 is not included in the +- * cache. ++ * wm8990 register cache ++ * We can't read the WM8990 register space when we ++ * are using 2 wire for device control, so we cache them instead. + */ +-static const u16 wm8990_reg[] = { +- 0x8990, /* R0 - Reset */ +- 0x0000, /* R1 - Power Management (1) */ +- 0x6000, /* R2 - Power Management (2) */ +- 0x0000, /* R3 - Power Management (3) */ +- 0x4050, /* R4 - Audio Interface (1) */ +- 0x4000, /* R5 - Audio Interface (2) */ +- 0x01C8, /* R6 - Clocking (1) */ +- 0x0000, /* R7 - Clocking (2) */ +- 0x0040, /* R8 - Audio Interface (3) */ +- 0x0040, /* R9 - Audio Interface (4) */ +- 0x0004, /* R10 - DAC CTRL */ +- 0x00C0, /* R11 - Left DAC Digital Volume */ +- 0x00C0, /* R12 - Right DAC Digital Volume */ +- 0x0000, /* R13 - Digital Side Tone */ +- 0x0100, /* R14 - ADC CTRL */ +- 0x00C0, /* R15 - Left ADC Digital Volume */ +- 0x00C0, /* R16 - Right ADC Digital Volume */ +- 0x0000, /* R17 */ +- 0x0000, /* R18 - GPIO CTRL 1 */ +- 0x1000, /* R19 - GPIO1 & GPIO2 */ +- 0x1010, /* R20 - GPIO3 & GPIO4 */ +- 0x1010, /* R21 - GPIO5 & GPIO6 */ +- 0x8000, /* R22 - GPIOCTRL 2 */ +- 0x0800, /* R23 - GPIO_POL */ +- 0x008B, /* R24 - Left Line Input 1&2 Volume */ +- 0x008B, /* R25 - Left Line Input 3&4 Volume */ +- 0x008B, /* R26 - Right Line Input 1&2 Volume */ +- 0x008B, /* R27 - Right Line Input 3&4 Volume */ +- 0x0000, /* R28 - Left Output Volume */ +- 0x0000, /* R29 - Right Output Volume */ +- 0x0066, /* R30 - Line Outputs Volume */ +- 0x0022, /* R31 - Out3/4 Volume */ +- 0x0079, /* R32 - Left OPGA Volume */ +- 0x0079, /* R33 - Right OPGA Volume */ +- 0x0003, /* R34 - Speaker Volume */ +- 0x0003, /* R35 - ClassD1 */ +- 0x0000, /* R36 */ +- 0x0100, /* R37 - ClassD3 */ +- 0x0079, /* R38 - ClassD4 */ +- 0x0000, /* R39 - Input Mixer1 */ +- 0x0000, /* R40 - Input Mixer2 */ +- 0x0000, /* R41 - Input Mixer3 */ +- 0x0000, /* R42 - Input Mixer4 */ +- 0x0000, /* R43 - Input Mixer5 */ +- 0x0000, /* R44 - Input Mixer6 */ +- 0x0000, /* R45 - Output Mixer1 */ +- 0x0000, /* R46 - Output Mixer2 */ +- 0x0000, /* R47 - Output Mixer3 */ +- 0x0000, /* R48 - Output Mixer4 */ +- 0x0000, /* R49 - Output Mixer5 */ +- 0x0000, /* R50 - Output Mixer6 */ +- 0x0180, /* R51 - Out3/4 Mixer */ +- 0x0000, /* R52 - Line Mixer1 */ +- 0x0000, /* R53 - Line Mixer2 */ +- 0x0000, /* R54 - Speaker Mixer */ +- 0x0000, /* R55 - Additional Control */ +- 0x0000, /* R56 - AntiPOP1 */ +- 0x0000, /* R57 - AntiPOP2 */ +- 0x0000, /* R58 - MICBIAS */ +- 0x0000, /* R59 */ +- 0x0008, /* R60 - PLL1 */ +- 0x0031, /* R61 - PLL2 */ +- 0x0026, /* R62 - PLL3 */ +-}; ++static const u16 wm8990_reg[] = WM8990_REGISTER_DEFAULTS; + + /* + * read wm8990 register cache +@@ -115,8 +77,9 @@ + unsigned int reg) + { + u16 *cache = codec->reg_cache; +- BUG_ON(reg > (ARRAY_SIZE(wm8990_reg)) - 1); +- return cache[reg]; ++ if (reg < 1 || reg > (ARRAY_SIZE(wm8990_reg) + 1)) ++ return -1; ++ return cache[reg - 1]; + } + + /* +@@ -126,13 +89,9 @@ + unsigned int reg, unsigned int value) + { + u16 *cache = codec->reg_cache; +- BUG_ON(reg > (ARRAY_SIZE(wm8990_reg)) - 1); +- +- /* Reset register is uncached */ +- if (reg == 0) ++ if (reg < 1 || reg > 0x3f) + return; +- +- cache[reg] = value; ++ cache[reg - 1] = value; + } + + /* +@@ -147,8 +106,7 @@ + data[1] = (value >> 8) & 0xFF; + data[2] = value & 0xFF; + +- wm8990_write_reg_cache(codec, reg, value); +- ++ wm8990_write_reg_cache (codec, reg, value); + if (codec->hw_write(codec->control_data, data, 3) == 2) + return 0; + else +@@ -157,21 +115,45 @@ + + #define wm8990_reset(c) wm8990_write(c, WM8990_RESET, 0) + +-static const DECLARE_TLV_DB_LINEAR(rec_mix_tlv, -1500, 600); ++static const unsigned int rec_mix_tlv[] = { ++ TLV_DB_RANGE_HEAD(1), ++ 0, 7, TLV_DB_LINEAR_ITEM(-1500, 600), ++}; + +-static const DECLARE_TLV_DB_LINEAR(in_pga_tlv, -1650, 3000); ++static const unsigned int in_pga_tlv[] = { ++ TLV_DB_RANGE_HEAD(1), ++ 0, 0x1F, TLV_DB_LINEAR_ITEM(-1650, 3000), ++}; + +-static const DECLARE_TLV_DB_LINEAR(out_mix_tlv, 0, -2100); ++static const unsigned int out_mix_tlv[] = { ++ TLV_DB_RANGE_HEAD(1), ++ 0, 7, TLV_DB_LINEAR_ITEM(0, -2100), ++}; + +-static const DECLARE_TLV_DB_LINEAR(out_pga_tlv, -7300, 600); ++static const unsigned int out_pga_tlv[] = { ++ TLV_DB_RANGE_HEAD(1), ++ 0, 127, TLV_DB_LINEAR_ITEM(-7300, 600), ++}; + +-static const DECLARE_TLV_DB_LINEAR(out_omix_tlv, -600, 0); ++static const unsigned int out_omix_tlv[] = { ++ TLV_DB_RANGE_HEAD(1), ++ 0, 7, TLV_DB_LINEAR_ITEM(-600, 0), ++}; + +-static const DECLARE_TLV_DB_LINEAR(out_dac_tlv, -7163, 0); ++static const unsigned int out_dac_tlv[] = { ++ TLV_DB_RANGE_HEAD(1), ++ 0, 255, TLV_DB_LINEAR_ITEM(-7163, 0), ++}; + +-static const DECLARE_TLV_DB_LINEAR(in_adc_tlv, -7163, 1763); ++static const unsigned int in_adc_tlv[] = { ++ TLV_DB_RANGE_HEAD(1), ++ 0, 255, TLV_DB_LINEAR_ITEM(-7163, 1763), ++}; + +-static const DECLARE_TLV_DB_LINEAR(out_sidetone_tlv, -3600, 0); ++static const unsigned int out_sidetone_tlv[] = { ++ TLV_DB_RANGE_HEAD(1), ++ 0, 31, TLV_DB_LINEAR_ITEM(-3600, 0), ++}; + + static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +@@ -190,11 +172,9 @@ + return wm8990_write(codec, reg, val | 0x0100); + } + +-#define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\ +- tlv_array) {\ +- .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ +- .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ +- SNDRV_CTL_ELEM_ACCESS_READWRITE,\ ++#define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert, tlv_array) \ ++{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ ++ .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, \ + .get = snd_soc_get_volsw, .put = wm899x_outpga_put_volsw_vu, \ +@@ -310,15 +290,11 @@ + WM8990_CDMODE_BIT, 1, 0), + + SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME, +- WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0), ++ WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0), + SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3, + WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0), + SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3, + WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0), +-SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4, +- WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv), +-SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4, +- WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0), + + SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume", + WM8990_LEFT_DAC_DIGITAL_VOLUME, +@@ -424,7 +400,7 @@ + + for (i = 0; i < ARRAY_SIZE(wm8990_snd_controls); i++) { + err = snd_ctl_add(codec->card, +- snd_soc_cnew(&wm8990_snd_controls[i], codec, ++ snd_soc_cnew(&wm8990_snd_controls[i],codec, + NULL)); + if (err < 0) + return err; +@@ -436,13 +412,13 @@ + * _DAPM_ Controls + */ + +-static int inmixer_event(struct snd_soc_dapm_widget *w, ++static int inmixer_event (struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) + { + u16 reg, fakepower; + +- reg = wm8990_read_reg_cache(w->codec, WM8990_POWER_MANAGEMENT_2); +- fakepower = wm8990_read_reg_cache(w->codec, WM8990_INTDRIVBITS); ++ reg=wm8990_read_reg_cache(w->codec, WM8990_POWER_MANAGEMENT_2); ++ fakepower=wm8990_read_reg_cache(w->codec, WM8990_INTDRIVBITS); + + if (fakepower & ((1 << WM8990_INMIXL_PWR_BIT) | + (1 << WM8990_AINLMUX_PWR_BIT))) { +@@ -462,16 +438,19 @@ + return 0; + } + +-static int outmixer_event(struct snd_soc_dapm_widget *w, +- struct snd_kcontrol *kcontrol, int event) ++static int outmixer_event (struct snd_soc_dapm_widget *w, ++ struct snd_kcontrol * kcontrol, int event) + { + u32 reg_shift = kcontrol->private_value & 0xfff; + int ret = 0; + u16 reg; + ++// printk("reg_shift %4.4x\n", reg_shift); ++ + switch (reg_shift) { + case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) : + reg = wm8990_read_reg_cache(w->codec, WM8990_OUTPUT_MIXER1); ++ printk("reg %4.4x\n", reg); + if (reg & WM8990_LDLO) { + printk(KERN_WARNING + "Cannot set as Output Mixer 1 LDLO Set\n"); +@@ -510,7 +489,7 @@ + /* INMIX dB values */ + static const unsigned int in_mix_tlv[] = { + TLV_DB_RANGE_HEAD(1), +- 0, 7, TLV_DB_LINEAR_ITEM(-1200, 600), ++ 0,7, TLV_DB_LINEAR_ITEM(-1200, 600), + }; + + /* Left In PGA Connections */ +@@ -541,10 +520,8 @@ + WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv), + SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT, + 7, 0, in_mix_tlv), +-SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT, +- 1, 0), +-SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT, +- 1, 0), ++SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT, 1, 0), ++SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT, 1, 0), + }; + + /* INMIXR */ +@@ -564,7 +541,7 @@ + {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"}; + + static const struct soc_enum wm8990_ainlmux_enum = +-SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT, ++SOC_ENUM_SINGLE( WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT, + ARRAY_SIZE(wm8990_ainlmux), wm8990_ainlmux); + + static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls = +@@ -577,7 +554,7 @@ + {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"}; + + static const struct soc_enum wm8990_ainrmux_enum = +-SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT, ++SOC_ENUM_SINGLE( WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT, + ARRAY_SIZE(wm8990_ainrmux), wm8990_ainrmux); + + static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls = +@@ -847,7 +824,8 @@ + SND_SOC_DAPM_OUTPUT("Internal DAC Sink"), + }; + +-static const struct snd_soc_dapm_route audio_map[] = { ++//static const struct snd_soc_dapm_route audio_map[][3] = { ++static const char *audio_map[][3] = { + /* Make DACs turn on when playing even if not mixed into any outputs */ + {"Internal DAC Sink", NULL, "Left DAC"}, + {"Internal DAC Sink", NULL, "Right DAC"}, +@@ -923,7 +901,7 @@ + {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"}, + {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"}, + {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"}, +- {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"}, ++ {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"}, + + /* LONMIX */ + {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"}, +@@ -970,15 +948,25 @@ + {"OUT4", NULL, "OUT4MIX"}, + {"ROP", NULL, "ROPMIX"}, + {"RON", NULL, "RONMIX"}, ++ ++ /* terminator */ ++ {NULL, NULL, NULL}, + }; + + static int wm8990_add_widgets(struct snd_soc_codec *codec) + { +- snd_soc_dapm_new_controls(codec, wm8990_dapm_widgets, +- ARRAY_SIZE(wm8990_dapm_widgets)); ++ int i; ++ ++// for (i = 0; i < ARRAY_SIZE(wm8990_dapm_widgets); i++) ++ snd_soc_dapm_new_controls(codec, wm8990_dapm_widgets, ARRAY_SIZE(wm8990_dapm_widgets)); + + /* set up the WM8990 audio map */ +- snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); ++ for (i = 0; audio_map[i][0] != NULL; i++) { ++ snd_soc_dapm_connect_input(codec, audio_map[i][0], ++ audio_map[i][1], audio_map[i][2]); ++ } ++ ++ //snd_soc_dapm_add_routes(codec, audio_map,ARRAY_SIZE(audio_map)); + + snd_soc_dapm_new_widgets(codec); + return 0; +@@ -1012,7 +1000,7 @@ + + if ((Ndiv < 6) || (Ndiv > 12)) + printk(KERN_WARNING +- "WM8990 N value outwith recommended range! N = %d\n", Ndiv); ++ "WM8990 N value outwith recommended range! N = %d\n",Ndiv); + + pll_div->n = Ndiv; + Nmod = target % source; +@@ -1183,6 +1172,7 @@ + /* bit size */ + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: ++ audio1 |= WM8990_AIF_WL_16BITS; + break; + case SNDRV_PCM_FORMAT_S20_3LE: + audio1 |= WM8990_AIF_WL_20BITS; +@@ -1196,15 +1186,14 @@ + } + + wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, audio1); ++ //wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, 0x4010); + return 0; + } + + static int wm8990_mute(struct snd_soc_dai *dai, int mute) + { + struct snd_soc_codec *codec = dai->codec; +- u16 val; +- +- val = wm8990_read_reg_cache(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE; ++ u16 val = wm8990_read_reg_cache(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE; + + if (mute) + wm8990_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE); +@@ -1320,10 +1309,10 @@ + + #define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \ +- SNDRV_PCM_RATE_48000) ++ SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) + + #define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ +- SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) ++ SNDRV_PCM_FMTBIT_S24_LE) + + /* + * The WM8990 supports 2 different and mutually exclusive DAI +@@ -1366,7 +1355,7 @@ + struct snd_soc_codec *codec = socdev->codec; + + /* we only need to suspend if we are a valid card */ +- if (!codec->card) ++ if(!codec->card) + return 0; + + wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF); +@@ -1394,7 +1383,7 @@ + codec->hw_write(codec->control_data, data, 2); + } + +- wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY); ++ wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF); + return 0; + } + +@@ -1415,7 +1404,7 @@ + codec->set_bias_level = wm8990_set_bias_level; + codec->dai = &wm8990_dai; + codec->num_dai = 2; +- codec->reg_cache_size = ARRAY_SIZE(wm8990_reg); ++ codec->reg_cache_size = sizeof(wm8990_reg); + codec->reg_cache = kmemdup(wm8990_reg, sizeof(wm8990_reg), GFP_KERNEL); + + if (codec->reg_cache == NULL) +@@ -1423,6 +1412,28 @@ + + wm8990_reset(codec); + ++#if (defined CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990) || (defined CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990_MODULE) ++ /* Enable the left and right output mixers by default so a ++ headphone output path will work */ ++ printk("Entered : %s, %d 8990 write..\n",__FUNCTION__,__LINE__); ++ wm8990_write(codec, WM8990_OUTPUT_MIXER1, WM8990_LDLO); ++ wm8990_write(codec, WM8990_OUTPUT_MIXER2, WM8990_RDRO); ++#endif ++ ++#if (defined CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990) || (defined CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990_MODULE) ++ /* Enable the left and right output mixers by default so a ++ headphone output path will work */ ++ wm8990_write(codec, WM8990_OUTPUT_MIXER1, WM8990_LDLO); ++ wm8990_write(codec, WM8990_OUTPUT_MIXER2, WM8990_RDRO); ++#endif ++ ++#if (defined CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990) || (defined CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990_MODULE) ++ /* Enable the left and right output mixers by default so a ++ headphone output path will work */ ++ wm8990_write(codec, WM8990_OUTPUT_MIXER1, WM8990_LDLO); ++ wm8990_write(codec, WM8990_OUTPUT_MIXER2, WM8990_RDRO); ++#endif ++ + /* register pcms */ + ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); + if (ret < 0) { +@@ -1434,19 +1445,61 @@ + codec->bias_level = SND_SOC_BIAS_OFF; + wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + +- reg = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_4); +- wm8990_write(codec, WM8990_AUDIO_INTERFACE_4, reg | WM8990_ALRCGPIO1); +- +- reg = wm8990_read_reg_cache(codec, WM8990_GPIO1_GPIO2) & +- ~WM8990_GPIO1_SEL_MASK; +- wm8990_write(codec, WM8990_GPIO1_GPIO2, reg | 1); ++ /* set up ADCLR clock internally */ ++ //reg = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_4); ++ //wm8990_write(codec, WM8990_AUDIO_INTERFACE_4, reg | WM8990_ALRCGPIO1); ++ ++ /* set GPIO1 as clk output */ ++ //reg = wm8990_read_reg_cache(codec, WM8990_GPIO1_GPIO2) & ++// ~WM8990_GPIO1_SEL_MASK; ++// wm8990_write(codec, WM8990_GPIO1_GPIO2, reg | 1); + ++// set Line-In and Mic-In Path. ++// + reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2); + wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg | WM8990_OPCLK_ENA); + + wm8990_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8)); + wm8990_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8)); + ++ reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2); ++ wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg | WM8990_AINR_ENA | WM8990_ADCR_ENA | WM8990_ADCL_ENA); ++ ++ reg = wm8990_read_reg_cache(codec, WM8990_INPUT_MIXER5); ++ wm8990_write(codec, WM8990_INPUT_MIXER5, (reg & ~WM8990_LI2BVOL_MASK) | (0x50 | (1<<8))); ++ ++ wm8990_write(codec, WM8990_LEFT_ADC_DIGITAL_VOLUME, 0xff | (1<<8)); ++ ++ reg = wm8990_read_reg_cache(codec, WM8990_INPUT_MIXER6); ++ wm8990_write(codec, WM8990_INPUT_MIXER6, (reg & ~WM8990_RI2BVOL_MASK) | (0x50 | (1<<8))); ++ ++ wm8990_write(codec, WM8990_RIGHT_ADC_DIGITAL_VOLUME, 0xff | (1<<8)); ++ ++ reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2); ++ wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg | WM8990_LIN12_ENA | WM8990_AINL_ENA); ++ ++ reg = wm8990_read_reg_cache(codec, WM8990_INPUT_MIXER2); ++ wm8990_write(codec, WM8990_INPUT_MIXER2, reg | WM8990_LMN1); ++ ++ reg = wm8990_read_reg_cache(codec, WM8990_LEFT_LINE_INPUT_1_2_VOLUME); ++ wm8990_write(codec, WM8990_LEFT_LINE_INPUT_1_2_VOLUME, (reg & ~WM8990_LIN12VOL_MASK) | (0x5f | (1<<8))); ++ ++ reg = wm8990_read_reg_cache(codec, WM8990_INPUT_MIXER4); ++ wm8990_write(codec, WM8990_INPUT_MIXER4, (reg & ~WM8990_RDBVOL_MASK) | (0x5f | (1<<8))); ++ ++ reg = wm8990_read_reg_cache(codec, WM8990_INPUT_MIXER3); ++ wm8990_write(codec, WM8990_INPUT_MIXER3, reg | WM8990_L12MNB); ++ ++ reg = wm8990_read_reg_cache(codec, WM8990_INPUT_MIXER3); ++ wm8990_write(codec, WM8990_INPUT_MIXER3, reg | WM8990_L12MNBST); ++ ++#if defined(CONFIG_SOUND_WM8990_INPUT_STREAM_MIC_IN) ++ /* For Mono MIC-In */ ++ reg = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_1); ++ wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, reg & (0<<14)); ++ ++#endif ++ + wm8990_add_controls(codec); + wm8990_add_widgets(codec); + ret = snd_soc_register_card(socdev); +@@ -1468,94 +1521,93 @@ + around */ + static struct snd_soc_device *wm8990_socdev; + +-#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) ++#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + + /* +- * WM891 2 wire address is determined by GPIO5 ++ * WM8912 wire address is determined by GPIO5 + * state during powerup. + * low = 0x34 + * high = 0x36 + */ ++static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END }; + +-static int wm8990_i2c_probe(struct i2c_client *i2c, +- const struct i2c_device_id *id) ++/* Magic definition of all other variables and things */ ++I2C_CLIENT_INSMOD; ++ ++static struct i2c_driver wm8990_i2c_driver; ++static struct i2c_client client_template; ++ ++static int wm8990_codec_probe(struct i2c_adapter *adap, int addr, int kind) + { + struct snd_soc_device *socdev = wm8990_socdev; ++ struct wm8990_setup_data *setup = socdev->codec_data; + struct snd_soc_codec *codec = socdev->codec; ++ struct i2c_client *i2c; + int ret; + ++ if (addr != setup->i2c_address) ++ return -ENODEV; ++ ++ client_template.adapter = adap; ++ client_template.addr = addr; ++ ++ i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL); ++ if (i2c == NULL){ ++ kfree(codec); ++ return -ENOMEM; ++ } + i2c_set_clientdata(i2c, codec); + codec->control_data = i2c; + ++ ret = i2c_attach_client(i2c); ++ if (ret < 0) { ++ err("failed to attach codec at addr %x\n", addr); ++ goto err; ++ } ++ + ret = wm8990_init(socdev); +- if (ret < 0) +- pr_err("failed to initialise WM8990\n"); ++ if (ret < 0) { ++ err("failed to initialise WM8990\n"); ++ goto err; ++ } ++ return ret; + ++err: ++ kfree(codec); ++ kfree(i2c); + return ret; + } + +-static int wm8990_i2c_remove(struct i2c_client *client) ++static int wm8990_i2c_detach(struct i2c_client *client) + { + struct snd_soc_codec *codec = i2c_get_clientdata(client); ++ i2c_detach_client(client); + kfree(codec->reg_cache); ++ kfree(client); + return 0; + } + +-static const struct i2c_device_id wm8990_i2c_id[] = { +- { "wm8990", 0 }, +- { } +-}; +-MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id); ++static int wm8990_i2c_attach(struct i2c_adapter *adap) ++{ ++ return i2c_probe(adap, &addr_data, wm8990_codec_probe); ++} + ++/* corgi i2c codec control layer */ + static struct i2c_driver wm8990_i2c_driver = { + .driver = { + .name = "WM8990 I2C Codec", + .owner = THIS_MODULE, + }, +- .probe = wm8990_i2c_probe, +- .remove = wm8990_i2c_remove, +- .id_table = wm8990_i2c_id, ++ .id = I2C_DRIVERID_WM8753, ++ .attach_adapter = wm8990_i2c_attach, ++ .detach_client = wm8990_i2c_detach, ++ .command = NULL, + }; + +-static int wm8990_add_i2c_device(struct platform_device *pdev, +- const struct wm8990_setup_data *setup) +-{ +- struct i2c_board_info info; +- struct i2c_adapter *adapter; +- struct i2c_client *client; +- int ret; +- +- ret = i2c_add_driver(&wm8990_i2c_driver); +- if (ret != 0) { +- dev_err(&pdev->dev, "can't add i2c driver\n"); +- return ret; +- } +- +- memset(&info, 0, sizeof(struct i2c_board_info)); +- info.addr = setup->i2c_address; +- strlcpy(info.type, "wm8990", I2C_NAME_SIZE); +- +- adapter = i2c_get_adapter(setup->i2c_bus); +- if (!adapter) { +- dev_err(&pdev->dev, "can't get i2c adapter %d\n", +- setup->i2c_bus); +- goto err_driver; +- } +- +- client = i2c_new_device(adapter, &info); +- i2c_put_adapter(adapter); +- if (!client) { +- dev_err(&pdev->dev, "can't add i2c device at 0x%x\n", +- (unsigned int)info.addr); +- goto err_driver; +- } +- +- return 0; +- +-err_driver: +- i2c_del_driver(&wm8990_i2c_driver); +- return -ENODEV; +-} ++static struct i2c_client client_template = { ++ .name = "WM8990", ++ .driver = &wm8990_i2c_driver, ++}; + #endif + + static int wm8990_probe(struct platform_device *pdev) +@@ -1564,9 +1616,9 @@ + struct wm8990_setup_data *setup; + struct snd_soc_codec *codec; + struct wm8990_priv *wm8990; +- int ret; ++ int ret = 0; + +- pr_info("WM8990 Audio Codec %s\n", WM8990_VERSION); ++ info("WM8990 Audio Codec %s", WM8990_VERSION); + + setup = socdev->codec_data; + codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); +@@ -1586,19 +1638,17 @@ + INIT_LIST_HEAD(&codec->dapm_paths); + wm8990_socdev = socdev; + +- ret = -ENODEV; +- +-#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) ++#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + if (setup->i2c_address) { ++ normal_i2c[0] = setup->i2c_address; + codec->hw_write = (hw_write_t)i2c_master_send; +- ret = wm8990_add_i2c_device(pdev, setup); ++ ret = i2c_add_driver(&wm8990_i2c_driver); ++ if (ret != 0) ++ printk(KERN_ERR "can't add i2c driver"); + } ++#else ++ /* Add other interfaces here */ + #endif +- +- if (ret != 0) { +- kfree(codec->private_data); +- kfree(codec); +- } + return ret; + } + +@@ -1612,8 +1662,7 @@ + wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF); + snd_soc_free_pcms(socdev); + snd_soc_dapm_free(socdev); +-#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) +- i2c_unregister_device(codec->control_data); ++#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) + i2c_del_driver(&wm8990_i2c_driver); + #endif + kfree(codec->private_data); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/codecs/wm8990.h linux-2.6.28.6/sound/soc/codecs/wm8990.h +--- linux-2.6.28/sound/soc/codecs/wm8990.h 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/codecs/wm8990.h 2009-04-30 09:36:40.000000000 +0200 +@@ -1,5 +1,5 @@ + /* +- * wm8990.h -- audio driver for WM8990 ++ * wm8753.h -- audio driver for WM8753 + * + * Copyright 2007 Wolfson Microelectronics PLC. + * Author: Graeme Gregory +@@ -54,7 +54,6 @@ + #define WM8990_SPEAKER_VOLUME 0x22 + #define WM8990_CLASSD1 0x23 + #define WM8990_CLASSD3 0x25 +-#define WM8990_CLASSD4 0x26 + #define WM8990_INPUT_MIXER1 0x27 + #define WM8990_INPUT_MIXER2 0x28 + #define WM8990_INPUT_MIXER3 0x29 +@@ -90,7 +89,7 @@ + /* + * R0 (0x00) - Reset + */ +-#define WM8990_SW_RESET_CHIP_ID_MASK 0xFFFF /* SW_RESET_CHIP_ID */ ++#define WM8990_SW_RESET_CHIP_ID_MASK 0xFFFF /* SW_RESET_CHIP_ID - [15:0] */ + + /* + * R1 (0x01) - Power Management (1) +@@ -190,7 +189,7 @@ + #define WM8990_DACR_SRC 0x4000 /* DACR_SRC */ + #define WM8990_AIFDAC_TDM 0x2000 /* AIFDAC_TDM */ + #define WM8990_AIFDAC_TDM_CHAN 0x1000 /* AIFDAC_TDM_CHAN */ +-#define WM8990_DAC_BOOST_MASK 0x0C00 /* DAC_BOOST */ ++#define WM8990_DAC_BOOST_MASK 0x0C00 /* DAC_BOOST - [11:10] */ + #define WM8990_DAC_COMP 0x0010 /* DAC_COMP */ + #define WM8990_DAC_COMPMODE 0x0008 /* DAC_COMPMODE */ + #define WM8990_ADC_COMP 0x0004 /* ADC_COMP */ +@@ -229,25 +228,25 @@ + #define WM8990_SYSCLK_SRC 0x4000 /* SYSCLK_SRC */ + #define WM8990_CLK_FORCE 0x2000 /* CLK_FORCE */ + #define WM8990_MCLK_DIV_MASK 0x1800 /* MCLK_DIV - [12:11] */ +-#define WM8990_MCLK_DIV_1 (0 << 11) +-#define WM8990_MCLK_DIV_2 (2 << 11) ++#define WM8990_MCLK_DIV_1 ( 0 << 11) ++#define WM8990_MCLK_DIV_2 ( 2 << 11) + #define WM8990_MCLK_INV 0x0400 /* MCLK_INV */ +-#define WM8990_ADC_CLKDIV_MASK 0x00E0 /* ADC_CLKDIV */ +-#define WM8990_ADC_CLKDIV_1 (0 << 5) +-#define WM8990_ADC_CLKDIV_1_5 (1 << 5) +-#define WM8990_ADC_CLKDIV_2 (2 << 5) +-#define WM8990_ADC_CLKDIV_3 (3 << 5) +-#define WM8990_ADC_CLKDIV_4 (4 << 5) +-#define WM8990_ADC_CLKDIV_5_5 (5 << 5) +-#define WM8990_ADC_CLKDIV_6 (6 << 5) ++#define WM8990_ADC_CLKDIV_MASK 0x00E0 /* ADC_CLKDIV - [7:5] */ ++#define WM8990_ADC_CLKDIV_1 ( 0 << 5) ++#define WM8990_ADC_CLKDIV_1_5 ( 1 << 5) ++#define WM8990_ADC_CLKDIV_2 ( 2 << 5) ++#define WM8990_ADC_CLKDIV_3 ( 3 << 5) ++#define WM8990_ADC_CLKDIV_4 ( 4 << 5) ++#define WM8990_ADC_CLKDIV_5_5 ( 5 << 5) ++#define WM8990_ADC_CLKDIV_6 ( 6 << 5) + #define WM8990_DAC_CLKDIV_MASK 0x001C /* DAC_CLKDIV - [4:2] */ +-#define WM8990_DAC_CLKDIV_1 (0 << 2) +-#define WM8990_DAC_CLKDIV_1_5 (1 << 2) +-#define WM8990_DAC_CLKDIV_2 (2 << 2) +-#define WM8990_DAC_CLKDIV_3 (3 << 2) +-#define WM8990_DAC_CLKDIV_4 (4 << 2) +-#define WM8990_DAC_CLKDIV_5_5 (5 << 2) +-#define WM8990_DAC_CLKDIV_6 (6 << 2) ++#define WM8990_DAC_CLKDIV_1 ( 0 << 2) ++#define WM8990_DAC_CLKDIV_1_5 ( 1 << 2) ++#define WM8990_DAC_CLKDIV_2 ( 2 << 2) ++#define WM8990_DAC_CLKDIV_3 ( 3 << 2) ++#define WM8990_DAC_CLKDIV_4 ( 4 << 2) ++#define WM8990_DAC_CLKDIV_5_5 ( 5 << 2) ++#define WM8990_DAC_CLKDIV_6 ( 6 << 2) + + /* + * R8 (0x08) - Audio Interface (3) +@@ -256,7 +255,7 @@ + #define WM8990_AIF_MSTR2 0x4000 /* AIF_MSTR2 */ + #define WM8990_AIF_SEL 0x2000 /* AIF_SEL */ + #define WM8990_ADCLRC_DIR 0x0800 /* ADCLRC_DIR */ +-#define WM8990_ADCLRC_RATE_MASK 0x07FF /* ADCLRC_RATE */ ++#define WM8990_ADCLRC_RATE_MASK 0x07FF /* ADCLRC_RATE - [10:0] */ + + /* + * R9 (0x09) - Audio Interface (4) +@@ -265,7 +264,7 @@ + #define WM8990_ALRCBGPIO6 0x4000 /* ALRCBGPIO6 */ + #define WM8990_AIF_TRIS 0x2000 /* AIF_TRIS */ + #define WM8990_DACLRC_DIR 0x0800 /* DACLRC_DIR */ +-#define WM8990_DACLRC_RATE_MASK 0x07FF /* DACLRC_RATE */ ++#define WM8990_DACLRC_RATE_MASK 0x07FF /* DACLRC_RATE - [10:0] */ + + /* + * R10 (0x0A) - DAC CTRL +@@ -295,9 +294,9 @@ + /* + * R13 (0x0D) - Digital Side Tone + */ +-#define WM8990_ADCL_DAC_SVOL_MASK 0x0F /* ADCL_DAC_SVOL */ ++#define WM8990_ADCL_DAC_SVOL_MASK 0x0F /* ADCL_DAC_SVOL - [12:9] */ + #define WM8990_ADCL_DAC_SVOL_SHIFT 9 +-#define WM8990_ADCR_DAC_SVOL_MASK 0x0F /* ADCR_DAC_SVOL */ ++#define WM8990_ADCR_DAC_SVOL_MASK 0x0F /* ADCR_DAC_SVOL - [8:5] */ + #define WM8990_ADCR_DAC_SVOL_SHIFT 5 + #define WM8990_ADC_TO_DACL_MASK 0x03 /* ADC_TO_DACL - [3:2] */ + #define WM8990_ADC_TO_DACL_SHIFT 2 +@@ -529,8 +528,8 @@ + /* + * R34 (0x22) - Speaker Volume + */ +-#define WM8990_SPKATTN_MASK 0x0003 /* SPKATTN - [1:0] */ +-#define WM8990_SPKATTN_SHIFT 0 ++#define WM8990_SPKVOL_MASK 0x0003 /* SPKVOL - [1:0] */ ++#define WM8990_SPKVOL_SHIFT 0 + + /* + * R35 (0x23) - ClassD1 +@@ -545,15 +544,6 @@ + #define WM8990_DCGAIN_SHIFT 3 + #define WM8990_ACGAIN_MASK 0x0007 /* ACGAIN - [2:0] */ + #define WM8990_ACGAIN_SHIFT 0 +- +-/* +- * R38 (0x26) - ClassD4 +- */ +-#define WM8990_SPKZC_MASK 0x0001 /* SPKZC */ +-#define WM8990_SPKZC_SHIFT 7 /* SPKZC */ +-#define WM8990_SPKVOL_MASK 0x007F /* SPKVOL - [6:0] */ +-#define WM8990_SPKVOL_SHIFT 0 /* SPKVOL - [6:0] */ +- + /* + * R39 (0x27) - Input Mixer1 + */ +@@ -820,14 +810,83 @@ + + /* + * R63 (0x3F) - Internal Driver Bits +- */ ++*/ + #define WM8990_INMIXL_PWR_BIT 0 + #define WM8990_AINLMUX_PWR_BIT 1 + #define WM8990_INMIXR_PWR_BIT 2 + #define WM8990_AINRMUX_PWR_BIT 3 + ++/* ++ * Default values. ++ */ ++#define WM8990_REGISTER_DEFAULTS \ ++{ \ ++ /*0x8990,*/ /* R0 - Reset */ \ ++ 0x0000, /* R1 - Power Management (1) */ \ ++ 0x6000, /* R2 - Power Management (2) */ \ ++ 0x0000, /* R3 - Power Management (3) */ \ ++ 0x4050, /* R4 - Audio Interface (1) */ \ ++ 0x4000, /* R5 - Audio Interface (2) */ \ ++ 0x01C8, /* R6 - Clocking (1) */ \ ++ 0x0000, /* R7 - Clocking (2) */ \ ++ 0x0040, /* R8 - Audio Interface (3) */ \ ++ 0x0040, /* R9 - Audio Interface (4) */ \ ++ 0x0004, /* R10 - DAC CTRL */ \ ++ 0x00C0, /* R11 - Left DAC Digital Volume */ \ ++ 0x00C0, /* R12 - Right DAC Digital Volume */ \ ++ 0x0000, /* R13 - Digital Side Tone */ \ ++ 0x0100, /* R14 - ADC CTRL */ \ ++ 0x00C0, /* R15 - Left ADC Digital Volume */ \ ++ 0x00C0, /* R16 - Right ADC Digital Volume */ \ ++ 0x0000, /* R17 */ \ ++ 0x0000, /* R18 - GPIO CTRL 1 */ \ ++ 0x1000, /* R19 - GPIO1 & GPIO2 */ \ ++ 0x1010, /* R20 - GPIO3 & GPIO4 */ \ ++ 0x1010, /* R21 - GPIO5 & GPIO6 */ \ ++ 0x8000, /* R22 - GPIOCTRL 2 */ \ ++ 0x0800, /* R23 - GPIO_POL */ \ ++ 0x008B, /* R24 - Left Line Input 1&2 Volume */ \ ++ 0x008B, /* R25 - Left Line Input 3&4 Volume */ \ ++ 0x008B, /* R26 - Right Line Input 1&2 Volume */ \ ++ 0x008B, /* R27 - Right Line Input 3&4 Volume */ \ ++ 0x0000, /* R28 - Left Output Volume */ \ ++ 0x0000, /* R29 - Right Output Volume */ \ ++ 0x0066, /* R30 - Line Outputs Volume */ \ ++ 0x0022, /* R31 - Out3/4 Volume */ \ ++ 0x0079, /* R32 - Left OPGA Volume */ \ ++ 0x0079, /* R33 - Right OPGA Volume */ \ ++ 0x0003, /* R34 - Speaker Volume */ \ ++ 0x0003, /* R35 - ClassD1 */ \ ++ 0x0000, /* R36 */ \ ++ 0x0100, /* R37 - ClassD3 */ \ ++ 0x0000, /* R38 */ \ ++ 0x0000, /* R39 - Input Mixer1 */ \ ++ 0x0000, /* R40 - Input Mixer2 */ \ ++ 0x0000, /* R41 - Input Mixer3 */ \ ++ 0x0000, /* R42 - Input Mixer4 */ \ ++ 0x0000, /* R43 - Input Mixer5 */ \ ++ 0x0000, /* R44 - Input Mixer6 */ \ ++ 0x0000, /* R45 - Output Mixer1 */ \ ++ 0x0000, /* R46 - Output Mixer2 */ \ ++ 0x0000, /* R47 - Output Mixer3 */ \ ++ 0x0000, /* R48 - Output Mixer4 */ \ ++ 0x0000, /* R49 - Output Mixer5 */ \ ++ 0x0000, /* R50 - Output Mixer6 */ \ ++ 0x0180, /* R51 - Out3/4 Mixer */ \ ++ 0x0000, /* R52 - Line Mixer1 */ \ ++ 0x0000, /* R53 - Line Mixer2 */ \ ++ 0x0000, /* R54 - Speaker Mixer */ \ ++ 0x0000, /* R55 - Additional Control */ \ ++ 0x0000, /* R56 - AntiPOP1 */ \ ++ 0x0000, /* R57 - AntiPOP2 */ \ ++ 0x0000, /* R58 - MICBIAS */ \ ++ 0x0000, /* R59 */ \ ++ 0x0008, /* R60 - PLL1 */ \ ++ 0x0031, /* R61 - PLL2 */ \ ++ 0x0026, /* R62 - PLL3 */ \ ++} ++ + struct wm8990_setup_data { +- unsigned i2c_bus; + unsigned short i2c_address; + }; + +@@ -836,6 +895,8 @@ + #define WM8990_ADCCLK_DIV 2 + #define WM8990_BCLK_DIV 3 + ++#define WM8990_MCLK 0 ++ + extern struct snd_soc_dai wm8990_dai; + extern struct snd_soc_codec_device soc_codec_dev_wm8990; + +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/codecs/wm9713.c linux-2.6.28.6/sound/soc/codecs/wm9713.c +--- linux-2.6.28/sound/soc/codecs/wm9713.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/codecs/wm9713.c 2010-04-21 06:38:39.000000000 +0200 +@@ -742,6 +743,7 @@ + /* disable PLL power and select ext source */ + reg = ac97_read(codec, AC97_HANDSET_RATE); + ac97_write(codec, AC97_HANDSET_RATE, reg | 0x0080); ++ //printk("-------1\n"); + reg = ac97_read(codec, AC97_EXTENDED_MID); + ac97_write(codec, AC97_EXTENDED_MID, reg | 0x0200); + wm9713->pll_out = 0; +@@ -784,6 +786,7 @@ + } + + /* turn PLL on and select as source */ ++//printk("-------2\n"); + reg = ac97_read(codec, AC97_EXTENDED_MID); + ac97_write(codec, AC97_EXTENDED_MID, reg & 0xfdff); + reg = ac97_read(codec, AC97_HANDSET_RATE); +@@ -962,6 +965,7 @@ + u16 status; + + /* Gracefully shut down the voice interface. */ ++ //printk("-------3\n"); + status = ac97_read(codec, AC97_EXTENDED_STATUS) | 0x1000; + ac97_write(codec, AC97_HANDSET_RATE, 0x0280); + schedule_timeout_interruptible(msecs_to_jiffies(1)); +@@ -1106,24 +1110,34 @@ + static int wm9713_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) + { ++#if !defined (CONFIG_CPU_S5PC100) + u16 reg; ++#endif + + switch (level) { + case SND_SOC_BIAS_ON: ++#if !defined (CONFIG_CPU_S5PC100) + /* enable thermal shutdown */ +- reg = ac97_read(codec, AC97_EXTENDED_MID) & 0x1bff; ++ //printk("-------4\n"); ++ /* reg = ac97_read(codec, AC97_EXTENDED_MID) & 0x1bff; + ac97_write(codec, AC97_EXTENDED_MID, reg); ++ */ ++#endif + break; + case SND_SOC_BIAS_PREPARE: + break; + case SND_SOC_BIAS_STANDBY: ++#if !defined (CONFIG_CPU_S5PC100) + /* enable master bias and vmid */ ++ //printk("-------5\n"); + reg = ac97_read(codec, AC97_EXTENDED_MID) & 0x3bff; + ac97_write(codec, AC97_EXTENDED_MID, reg); ++#endif + ac97_write(codec, AC97_POWERDOWN, 0x0000); + break; + case SND_SOC_BIAS_OFF: + /* disable everything including AC link */ ++//printk("-------6\n"); + ac97_write(codec, AC97_EXTENDED_MID, 0xffff); + ac97_write(codec, AC97_EXTENDED_MSTATUS, 0xffff); + ac97_write(codec, AC97_POWERDOWN, 0xffff); +@@ -1143,6 +1157,7 @@ + /* Disable everything except touchpanel - that will be handled + * by the touch driver and left disabled if touch is not in + * use. */ ++//printk("-------7\n"); + reg = ac97_read(codec, AC97_EXTENDED_MID); + ac97_write(codec, AC97_EXTENDED_MID, reg | 0x7fff); + ac97_write(codec, AC97_EXTENDED_MSTATUS, 0xffff); +@@ -1160,6 +1175,7 @@ + int i, ret; + u16 *cache = codec->reg_cache; + ++ wm9713_reset(codec, 0); + ret = wm9713_reset(codec, 1); + if (ret < 0) { + printk(KERN_ERR "could not reset AC97 codec\n"); +@@ -1249,6 +1265,8 @@ + /* unmute the adc - move to kcontrol */ + reg = ac97_read(codec, AC97_CD) & 0x7fff; + ac97_write(codec, AC97_CD, reg); ++ ac97_write(codec, AC97_MASTER, 0x8080); ++ //------------end of add----------------// + + wm9713_add_controls(codec); + wm9713_add_widgets(codec); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s3c24xx/s3c2443-ac97.c linux-2.6.28.6/sound/soc/s3c24xx/s3c2443-ac97.c +--- linux-2.6.28/sound/soc/s3c24xx/s3c2443-ac97.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s3c24xx/s3c2443-ac97.c 2009-04-30 09:36:40.000000000 +0200 +@@ -28,7 +28,7 @@ + #include + + #include +-#include ++#include + #include + #include + #include +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s3c64xx/Kconfig linux-2.6.28.6/sound/soc/s3c64xx/Kconfig +--- linux-2.6.28/sound/soc/s3c64xx/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s3c64xx/Kconfig 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,154 @@ ++menu "SoC Audio for the Samsung S3C" ++ depends on ARCH_S3C64XX || ARCH_S5P64XX ++ ++config SND_S3C64XX_SOC ++ tristate "SoC Audio for the Samsung S3C chips" ++ depends on ARCH_S3C64XX ++ select SND_PCM ++ help ++ Say Y or M if you want to add support for codecs attached to ++ the S3C AC97, I2S or SSP interface. You will also need ++ to select the audio interfaces to support below. ++ ++config SND_S5P64XX_SOC ++ tristate "SoC Audio for the Samsung S3C chips" ++ depends on ARCH_S5P64XX ++ select SND_PCM ++ help ++ Say Y or M if you want to add support for codecs attached to ++ the S3C AC97, I2S or SSP interface. You will also need ++ to select the audio interfaces to support below. ++ ++ ++config SND_S3C6410_SOC_I2S_V32 ++ tristate ++ ++config SND_S3C6410_SOC_I2S ++ tristate ++ ++config SND_S5P6440_SOC_I2S ++ tristate ++ ++config SND_SOC_I2S_V40 ++ tristate ++ ++config SND_S3C64XX_SOC_SMDK6410_WM9713 ++ tristate "SoC AC97 Audio support for SMDK6410 - WM9713" ++ depends on SND_S3C64XX_SOC && (MACH_SMDK6410) ++ select SND_S3C6410_SOC_AC97 ++ select SND_SOC_WM9713 ++ help ++ Say Y if you want to add support for SoC audio on smdk6410 ++ with the WM9713. ++ ++choice ++ prompt "SMDK Record Path Select" ++ depends on SND_S3C64XX_SOC_SMDK6400_WM9713 || SND_S3C64XX_SOC_SMDK6410_WM9713 ++ ++config SOUND_WM9713_INPUT_STREAM_LINE ++ bool "Input Stream is LINE-IN" ++ depends on SND_S3C64XX_SOC_SMDK6400_WM9713 || SND_S3C64XX_SOC_SMDK6410_WM9713 ++ help ++ Say Y here to make input stream as LINE-IN. ++ ++config SOUND_WM9713_INPUT_STREAM_MIC ++ bool "Input Stream is MIC" ++ depends on SND_S3C64XX_SOC_SMDK6400_WM9713 || SND_S3C64XX_SOC_SMDK6410_WM9713 ++ help ++ Say Y here to make input stream as MIC. ++endchoice ++ ++config SND_S3C6410_SOC_AC97 ++ tristate ++ select AC97_BUS ++ select SND_AC97_CODEC ++ select SND_SOC_AC97_BUS ++ ++config SND_S3C64XX_SOC_SMDK6410_WM8580 ++ tristate "SoC I2S Audio support for SMDK6410 - WM8580" ++ depends on SND_S3C64XX_SOC && (MACH_SMDK6410 || MACH_SMDK6430) ++ select SND_S3C6410_SOC_I2S ++ select SND_SOC_WM8580 ++ help ++ Say Y if you want to add support for SoC audio on smdk6410 ++ with the WM8580. ++ ++choice ++ prompt "SMDK Record Path Select" ++ depends on SND_S3C64XX_SOC_SMDK6410_WM8580 || SND_S3C24XX_SOC_SMDK2450_WM8580 ++ ++config SOUND_WM8580_INPUT_STREAM_LINE ++ bool "Input Stream is LINE-IN" ++ depends on SND_S3C64XX_SOC_SMDK6410_WM8580 || SND_S3C24XX_SOC_SMDK2450_WM8580 ++ help ++ Say Y here to make input stream as LINE-IN. ++ ++config SOUND_WM8580_INPUT_STREAM_MIC ++ bool "Input Stream is MIC" ++ depends on SND_S3C64XX_SOC_SMDK6410_WM8580 || SND_S3C24XX_SOC_SMDK2450_WM8580 ++ help ++ Say Y here to make input stream as MIC. ++endchoice ++ ++config SND_S5P64XX_SOC_SMDK6440_WM8580 ++ tristate "SoC I2S Audio support for SMDK6440 - WM8580" ++ depends on SND_S5P64XX_SOC && MACH_SMDK6440 ++ select SND_S5P6440_SOC_I2S ++ select SND_SOC_WM8580 ++ help ++ Say Y if you want to add support for SoC audio on smdk6440 ++ with the WM8580. ++ ++choice ++ prompt "SMDK Record Path Select" ++ depends on SND_S5P64XX_SOC_SMDK6440_WM8580 ++ ++config SOUND_SMDK6440_WM8580_INPUT_STREAM_LINE ++ bool "Input Stream is LINE-IN" ++ depends on SND_S5P64XX_SOC_SMDK6440_WM8580 ++ help ++ Say Y here to make input stream as LINE-IN. ++ ++config SOUND_SMDK6440_WM8580_INPUT_STREAM_MIC ++ bool "Input Stream is MIC" ++ depends on SND_S5P64XX_SOC_SMDK6440_WM8580 ++ help ++ Say Y here to make input stream as MIC. ++endchoice ++ ++config SND_S3C64XX_SOC_SMDK6410_WM8990 ++ tristate "SoC I2S Audio support for SMDK6410 - WM8990" ++ depends on SND_S3C64XX_SOC && (MACH_SMDK6410) ++ select SND_S3C6410_SOC_I2S_V32 ++ select SND_SOC_WM8990 ++ help ++ Say Y if you want to add support for SoC audio on smdk6410 ++ with the WM8990. ++ ++choice ++ prompt "SMDK Record Path Select" ++ depends on SND_S3C64XX_SOC_SMDK6410_WM8990 || SND_S3C64XX_SOC_SMDK6400_WM8990 ++ ++config SOUND_WM8990_INPUT_STREAM_LINE_IN ++ bool "Input Stream is LINE-IN" ++ depends on SND_S3C64XX_SOC_SMDK6410_WM8990 || SND_S3C64XX_SOC_SMDK6400_WM8990 ++ help ++ Say Y here to make input stream as LINE-IN. ++ ++config SOUND_WM8990_INPUT_STREAM_MIC_IN ++ bool "Input Stream is MIC" ++ depends on SND_S3C64XX_SOC_SMDK6410_WM8990 || SND_S3C64XX_SOC_SMDK6400_WM8990 ++ help ++ Say Y here to make input stream as MIC. ++endchoice ++ ++config SND_S3C64XX_SOC_SMDK6410_S5M8751 ++ tristate "SoC I2S Audio support for SMDK6410 - S5M8751" ++ depends on SND_S3C64XX_SOC && (MACH_SMDK6410) ++ select SND_S3C6410_SOC_I2S_V32 ++ select SND_SOC_S5M8751 ++ help ++ Say Y if you want to add support for SoC audio on smdk6410 ++ with the S5M8751. ++ ++endmenu +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s3c64xx/Makefile linux-2.6.28.6/sound/soc/s3c64xx/Makefile +--- linux-2.6.28/sound/soc/s3c64xx/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s3c64xx/Makefile 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,29 @@ ++# Samsung Platform Support ++snd-soc-s3c-objs := s3c-pcm.o ++snd-soc-s3c64xx-ac97-objs := s3c64xx-ac97.o ++snd-soc-s3c6410-i2s-objs := s3c6410-i2s.o ++snd-soc-s5p6440-i2s-objs := s5p6440-i2s.o ++ ++obj-$(CONFIG_SND_S3C64XX_SOC) += snd-soc-s3c.o ++obj-$(CONFIG_SND_S5P64XX_SOC) += snd-soc-s3c.o ++obj-$(CONFIG_SND_S3C6410_SOC_AC97) += snd-soc-s3c64xx-ac97.o ++obj-$(CONFIG_SND_S3C6410_SOC_I2S) += snd-soc-s3c6410-i2s.o ++obj-$(CONFIG_SND_S3C6410_SOC_I2S_V32) += snd-soc-s3c6410-i2s.o ++obj-$(CONFIG_SND_S5P6440_SOC_I2S) += snd-soc-s5p6440-i2s.o ++obj-$(CONFIG_SND_S5P6440_SOC_I2S_V32) += snd-soc-s5p6440-i2s.o ++ ++# Machine Support ++snd-soc-neo1973-wm8753-objs := neo1973_wm8753.o ++snd-soc-smdk64xx-wm9713-objs := smdk64xx_wm9713.o ++snd-soc-smdk6410-wm8580-objs := smdk6410_wm8580.o ++snd-soc-smdk6440-wm8580-objs := smdk6440_wm8580.o ++snd-soc-smdk6410-wm8990-objs := smdk6410_wm8990.o ++snd-soc-smdk6410-s5m8751-objs := smdk6410_s5m8751.o ++snd-soc-smdk6440-s5m8751-objs := smdk6440_s5m8751.o ++ ++obj-$(CONFIG_SND_S3C64XX_SOC_SMDK6410_WM9713) += snd-soc-smdk64xx-wm9713.o ++obj-$(CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8580) += snd-soc-smdk6410-wm8580.o ++obj-$(CONFIG_SND_S5P64XX_SOC_SMDK6440_WM8580) += snd-soc-smdk6440-wm8580.o ++obj-$(CONFIG_SND_S3C64XX_SOC_SMDK6410_WM8990) += snd-soc-smdk6410-wm8990.o ++obj-$(CONFIG_SND_S3C64XX_SOC_SMDK6410_S5M8751) += snd-soc-smdk6410-s5m8751.o ++obj-$(CONFIG_SND_S5P64XX_SOC_SMDK6440_S5M8751) += snd-soc-smdk6440-s5m8751.o +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s3c64xx/s3c-i2s.c linux-2.6.28.6/sound/soc/s3c64xx/s3c-i2s.c +--- linux-2.6.28/sound/soc/s3c64xx/s3c-i2s.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s3c64xx/s3c-i2s.c 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,619 @@ ++/* ++ * s3c-i2s.c -- ALSA Soc Audio Layer ++ * ++ * (c) 2006 Wolfson Microelectronics PLC. ++ * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com ++ * ++ * (c) 2004-2005 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * Ryu Euiyoul ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * ++ * Revision history ++ * 11th Dec 2006 Merged with Simtec driver ++ * 10th Nov 2006 Initial version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++//#include ++#include ++#include ++#include ++#include ++ ++#include "s3c-pcm.h" ++#include "s3c-i2s.h" ++ ++#ifdef CONFIG_SND_DEBUG ++#define s3cdbg(x...) printk(x) ++#else ++#define s3cdbg(x...) ++#endif ++ ++/* used to disable sysclk if external crystal is used */ ++static int extclk = 0; ++module_param(extclk, int, 0); ++MODULE_PARM_DESC(extclk, "set to 1 to disable s3c24XX i2s sysclk"); ++ ++static struct s3c2410_dma_client s3c24xx_dma_client_out = { ++ .name = "I2S PCM Stereo out" ++}; ++ ++static struct s3c2410_dma_client s3c24xx_dma_client_in = { ++ .name = "I2S PCM Stereo in" ++}; ++ ++static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_out = { ++ .client = &s3c24xx_dma_client_out, ++ .channel = DMACH_I2S_OUT, ++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410) ++ .dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFO, ++ .dma_size = 2, ++#else ++ .dma_addr = S3C6400_PA_IIS + S3C2410_IISFIFO, ++ .dma_size = 4, ++#endif ++}; ++ ++static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_in = { ++ .client = &s3c24xx_dma_client_in, ++ .channel = DMACH_I2S_IN, ++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410) ++ .dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFORX, ++ .dma_size = 2, ++#else ++ .dma_addr = S3C6400_PA_IIS + S3C2410_IISFIFORX, ++ .dma_size = 4, ++#endif ++}; ++ ++struct s3c24xx_i2s_info { ++ void __iomem *regs; ++ struct clk *iis_clk; ++ int master; ++}; ++static struct s3c24xx_i2s_info s3c24xx_i2s; ++ ++static void s3c24xx_snd_txctrl(int on) ++{ ++ u32 iisfcon; ++ u32 iiscon; ++ u32 iismod; ++ ++ s3cdbg("Entered %s : on = %d \n", __FUNCTION__, on); ++ ++ iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON); ++ iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD); ++ iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON); ++ ++ s3cdbg("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon); ++ ++ if (on) { ++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410) ++ iisfcon |= S3C2410_IISFCON_TXDMA | S3C2410_IISFCON_TXENABLE; ++ iiscon |= S3C2410_IISCON_TXDMAEN | S3C2410_IISCON_IISEN; ++ iiscon &= ~S3C2410_IISCON_TXIDLE; ++ iismod |= S3C2410_IISMOD_TXMODE; ++#else ++ iiscon |= S3C_IIS0CON_I2SACTIVE; ++#endif ++ writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); ++ writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); ++ writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); ++ } else { ++ /* note, we have to disable the FIFOs otherwise bad things ++ * seem to happen when the DMA stops. According to the ++ * Samsung supplied kernel, this should allow the DMA ++ * engine and FIFOs to reset. If this isn't allowed, the ++ * DMA engine will simply freeze randomly. ++ */ ++ ++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410) ++ iisfcon &= ~S3C2410_IISFCON_TXENABLE; ++ iisfcon &= ~S3C2410_IISFCON_TXDMA; ++ iiscon |= S3C2410_IISCON_TXIDLE; ++ iiscon &= ~S3C2410_IISCON_TXDMAEN; ++ iismod &= ~S3C2410_IISMOD_TXMODE; ++#else ++ iiscon &=~(S3C_IIS0CON_I2SACTIVE); ++ iismod &= ~S3C_IIS0MOD_TXMODE; ++#endif ++ ++ writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); ++ writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); ++ writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); ++ } ++ ++ s3cdbg("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon); ++} ++ ++static void s3c24xx_snd_rxctrl(int on) ++{ ++ u32 iisfcon; ++ u32 iiscon; ++ u32 iismod; ++ ++ s3cdbg("Entered %s: on = %d\n", __FUNCTION__, on); ++ ++ iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON); ++ iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON); ++ iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD); ++ ++ s3cdbg("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon); ++ ++ if (on) { ++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410) ++ iisfcon |= S3C2410_IISFCON_RXDMA | S3C2410_IISFCON_RXENABLE; ++ iiscon |= S3C2410_IISCON_RXDMAEN | S3C2410_IISCON_IISEN; ++ iiscon &= ~S3C2410_IISCON_RXIDLE; ++ iismod |= S3C2410_IISMOD_RXMODE; ++#else ++ iiscon |= S3C_IIS0CON_I2SACTIVE; ++#endif ++ writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); ++ writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); ++ writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); ++ } else { ++ /* note, we have to disable the FIFOs otherwise bad things ++ * seem to happen when the DMA stops. According to the ++ * Samsung supplied kernel, this should allow the DMA ++ * engine and FIFOs to reset. If this isn't allowed, the ++ * DMA engine will simply freeze randomly. ++ */ ++ ++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410) ++ iisfcon &= ~S3C2410_IISFCON_RXENABLE; ++ iisfcon &= ~S3C2410_IISFCON_RXDMA; ++ iiscon |= S3C2410_IISCON_RXIDLE; ++ iiscon &= ~S3C2410_IISCON_RXDMAEN; ++ iismod &= ~S3C2410_IISMOD_RXMODE; ++#else ++ iiscon &=~ S3C_IIS0CON_I2SACTIVE; ++ iismod &= ~S3C_IIS0MOD_RXMODE; ++#endif ++ writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); ++ writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); ++ writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); ++ ++ } ++ s3cdbg("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon); ++} ++ ++/* ++ * Wait for the LR signal to allow synchronisation to the L/R clock ++ * from the codec. May only be needed for slave mode. ++ */ ++static int s3c24xx_snd_lrsync(void) ++{ ++ u32 iiscon; ++ unsigned long timeout = jiffies + msecs_to_jiffies(5); ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ while (1) { ++ iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON); ++ if (iiscon & S3C2410_IISCON_LRINDEX) ++ break; ++ ++ if (timeout < jiffies) ++ return -ETIMEDOUT; ++ } ++ ++ return 0; ++} ++ ++/* ++ * Check whether CPU is the master or slave ++ */ ++static inline int s3c24xx_snd_is_clkmaster(void) ++{ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1; ++} ++ ++/* ++ * Set S3C24xx I2S DAI format ++ */ ++static int s3c_i2s_set_fmt(struct snd_soc_dai *cpu_dai, ++ unsigned int fmt) ++{ ++#if 0 ++ u32 iismod; ++ ++ s3cdbg("Entered %s: fmt = %d\n", __FUNCTION__, fmt); ++ ++ iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD); ++ ++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { ++ case SND_SOC_DAIFMT_CBM_CFM: ++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410) ++ iismod |= S3C2410_IISMOD_SLAVE; ++#else ++ iismod |= S3C2410_IISMOD_MASTER; ++#endif ++ break; ++ case SND_SOC_DAIFMT_CBS_CFS: ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { ++ case SND_SOC_DAIFMT_LEFT_J: ++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410) ++ iismod |= S3C2410_IISMOD_MSB; ++#else ++ iismod |= S3C_IIS0MOD_MSB; ++#endif ++ break; ++ case SND_SOC_DAIFMT_I2S: ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); ++#endif ++ return 0; ++ ++} ++ ++static int s3c_i2s_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ ++ unsigned long iiscon; ++ unsigned long iismod; ++ unsigned long iisfcon; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ /*Set I2C port to controll WM8753 codec*/ ++ gpio_pullup(S3C_GPB5, 0); ++ gpio_pullup(S3C_GPB6, 0); ++ gpio_set_pin(S3C_GPB5, S3C_GPB5_I2C_SCL); ++ gpio_set_pin(S3C_GPB6, S3C_GPB6_I2C_SDA); ++ ++ s3c24xx_i2s.master = 1; ++ ++ /* Configure the I2S pins in correct mode */ ++ gpio_set_pin(S3C_GPD2,S3C_GPD2_I2S_LRCLK0); ++ ++ if (s3c24xx_i2s.master && !extclk){ ++ s3cdbg("Setting Clock Output as we are Master\n"); ++ gpio_set_pin(S3C_GPD0,S3C_GPD0_I2S_CLK0); ++ ++ } ++ gpio_set_pin(S3C_GPD1,S3C_GPD1_I2S_CDCLK0); ++ gpio_set_pin(S3C_GPD3,S3C_GPD3_I2S_DI0); ++ gpio_set_pin(S3C_GPD4,S3C_GPD4_I2S_DO0); ++ ++ /* pull-up-enable, pull-down-disable*/ ++ gpio_pullup(S3C_GPD0, 0x2); ++ gpio_pullup(S3C_GPD1, 0x2); ++ gpio_pullup(S3C_GPD2, 0x2); ++ gpio_pullup(S3C_GPD3, 0x2); ++ gpio_pullup(S3C_GPD4, 0x2); ++ ++ s3cdbg("substream->stream : %d\n", substream->stream); ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_out; ++ } else { ++ rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_in; ++ } ++ ++ /* Working copies of registers */ ++ iiscon = readl(Ss3c24xx_i2s.regs + S3C_IIS0CON); ++ iismod = readl(S3C_IIS0MOD); ++ iisfcon = readl(S3C_IIS0FIC); ++ /* is port used by another stream */ ++ if (!(iiscon & S3C_IIS0CON_I2SACTIVE)) { ++ ++ // Clear BFS field [2:1] ++ iismod &= ~(0x3<<1); ++ iismod |= S3C_IIS0MOD_32FS | S3C_IIS0MOD_INTERNAL_CLK; ++ ++ if (!s3c24xx_i2s.master) ++ iismod |= S3C_IIS0MOD_IMS_SLAVE; ++ else ++ iismod |= S3C_IIS0MOD_IMS_EXTERNAL_MASTER; ++ } ++ ++ /* enable TX & RX all to support Full-duplex */ ++ iismod |= S3C_IIS0MOD_TXRXMODE; ++ iiscon |= S3C_IIS0CON_TXDMACTIVE; ++ iisfcon |= S3C_IIS_TX_FLUSH; ++ iiscon |= S3C_IIS0CON_RXDMACTIVE; ++ iisfcon |= S3C_IIS_RX_FLUSH; ++ ++ writel(iiscon, S3C_IIS0CON); ++ writel(iismod, S3C_IIS0MOD); ++ writel(iisfcon, S3C_IIS0FIC); ++ ++ // Tx, Rx fifo flush bit clear ++ iisfcon &= ~(S3C_IIS_TX_FLUSH | S3C_IIS_RX_FLUSH); ++ writel(iisfcon, S3C_IIS0FIC); ++ ++ s3cdbg("IISCON: %lx IISMOD: %lx", iiscon, iismod); ++ ++ return 0; ++ ++} ++ ++static int s3c_i2s_trigger(struct snd_pcm_substream *substream, int cmd) ++{ ++ int ret = 0; ++ ++ s3cdbg("Entered %s: cmd = %d\n", __FUNCTION__, cmd); ++ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ if (!s3c24xx_snd_is_clkmaster()) { ++ ret = s3c24xx_snd_lrsync(); ++ if (ret) ++ goto exit_err; ++ } ++ ++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) ++ s3c24xx_snd_rxctrl(1); ++ else ++ s3c24xx_snd_txctrl(1); ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) ++ s3c24xx_snd_rxctrl(0); ++ else ++ s3c24xx_snd_txctrl(0); ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++exit_err: ++ return ret; ++} ++ ++static void s3c64xx_i2s_shutdown(struct snd_pcm_substream *substream) ++{ ++ unsigned long iismod, iiscon; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ iismod=readl(S3C_IIS0MOD); ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ iismod &= ~S3C_IIS0MOD_TXMODE; ++ } else { ++ iismod &= ~S3C_IIS0MOD_RXMODE; ++ } ++ ++ writel(iismod,S3C_IIS0MOD); ++ ++ iiscon=readl(S3C_IIS0CON); ++ iiscon &= !S3C_IIS0CON_I2SACTIVE; ++ writel(iiscon,S3C_IIS0CON); ++ ++ /* Clock disable ++ * PCLK & SCLK gating disable ++ */ ++ __raw_writel(__raw_readl(S3C_PCLK_GATE)&~(S3C_CLKCON_PCLK_IIS0), S3C_PCLK_GATE); ++ __raw_writel(__raw_readl(S3C_SCLK_GATE)&~(S3C_CLKCON_SCLK_AUDIO0), S3C_SCLK_GATE); ++ ++ /* EPLL disable */ ++ __raw_writel(__raw_readl(S3C_EPLL_CON0)&~(1<<31) ,S3C_EPLL_CON0); ++ ++} ++ ++ ++/* ++ * Set S3C24xx Clock source ++ */ ++static int s3c_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, ++ int clk_id, unsigned int freq, int dir) ++{ ++ u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD); ++ ++ s3cdbg("Entered %s : clk_id = %d\n", __FUNCTION__, clk_id); ++ ++ iismod &= ~S3C2440_IISMOD_MPLL; ++ ++ switch (clk_id) { ++ case S3C24XX_CLKSRC_PCLK: ++ break; ++ case S3C24XX_CLKSRC_MPLL: ++ iismod |= S3C2440_IISMOD_MPLL; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); ++ return 0; ++} ++ ++/* ++ * Set S3C24xx Clock dividers ++ */ ++static int s3c_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai, ++ int div_id, int div) ++{ ++ u32 reg; ++ ++ s3cdbg("Entered %s : div_id = %d, div = %d\n", __FUNCTION__, div_id, div); ++ ++ switch (div_id) { ++ case S3C24XX_DIV_MCLK: ++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410) ++ reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK; ++ writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD); ++#endif ++ break; ++ case S3C24XX_DIV_BCLK: ++ reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS); ++ writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD); ++ break; ++ case S3C24XX_DIV_PRESCALER: ++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410) ++ writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR); ++ reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON); ++ writel(reg | S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON); ++#else ++ writel(div|(1<<15),S3C_IIS0PSR); ++#endif ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410) ++/* ++ * To avoid duplicating clock code, allow machine driver to ++ * get the clockrate from here. ++ */ ++u32 s3c24xx_i2s_get_clockrate(void) ++{ ++ return clk_get_rate(s3c24xx_i2s.iis_clk); ++} ++EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate); ++#endif ++ ++static int s3c_i2s_probe(struct platform_device *pdev) ++{ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ s3c24xx_i2s.regs = ioremap(S3C24XX_PA_IIS, 0x100); ++ if (s3c24xx_i2s.regs == NULL) ++ return -ENXIO; ++ ++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410) ++ s3c24xx_i2s.iis_clk=clk_get(&pdev->dev, "iis"); ++ if (s3c24xx_i2s.iis_clk == NULL) { ++ s3cdbg("failed to get iis_clock\n"); ++ return -ENODEV; ++ } ++ clk_enable(s3c24xx_i2s.iis_clk); ++ ++ /* Configure the I2S pins in correct mode */ ++ s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK); ++ s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK); ++ s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK); ++ s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI); ++ s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO); ++ ++ writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON); ++ ++ /* Configure the I2S pins in correct mode */ ++ gpio_set_pin(S3C_GPD2,S3C_GPD2_I2S_LRCLK0); ++ ++ gpio_set_pin(S3C_GPD0,S3C_GPD0_I2S_CLK0); ++ ++ gpio_set_pin(S3C_GPD1,S3C_GPD1_I2S_CDCLK0); ++ gpio_set_pin(S3C_GPD3,S3C_GPD3_I2S_DI0); ++ gpio_set_pin(S3C_GPD4,S3C_GPD4_I2S_DO0); ++ ++ /* pull-up-enable, pull-down-disable*/ ++ gpio_pullup(S3C_GPD0, 0x2); ++ gpio_pullup(S3C_GPD1, 0x2); ++ gpio_pullup(S3C_GPD2, 0x2); ++ gpio_pullup(S3C_GPD3, 0x2); ++ gpio_pullup(S3C_GPD4, 0x2); ++ ++ writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON); ++ s3c24xx_snd_txctrl(0); ++ s3c24xx_snd_rxctrl(0); ++#endif ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int s3c_i2s_suspend(struct platform_device *dev, ++ struct snd_soc_dai *dai) ++{ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ return 0; ++} ++ ++static int s3c_i2s_resume(struct platform_device *pdev, ++ struct snd_soc_dai *dai) ++{ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ return 0; ++} ++ ++#else ++#define s3c_i2s_suspend NULL ++#define s3c_i2s_resume NULL ++#endif ++ ++ ++#define S3C24XX_I2S_RATES \ ++ (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \ ++ SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ ++ SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) ++ ++struct snd_soc_dai s3c_i2s_dai = { ++ .name = "s3c-i2s", ++ .id = 0, ++ .type = SND_SOC_DAI_I2S, ++ .probe = s3c_i2s_probe, ++ .suspend = s3c_i2s_suspend, ++ .resume = s3c_i2s_resume, ++ .playback = { ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = S3C24XX_I2S_RATES, ++ .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,}, ++ .capture = { ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = S3C24XX_I2S_RATES, ++ .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,}, ++ .ops = { ++ .shutdown = s3c64xx_i2s_shutdown, ++ .trigger = s3c_i2s_trigger, ++ .hw_params = s3c_i2s_hw_params,}, ++ .dai_ops = { ++ .set_fmt = s3c_i2s_set_fmt, ++ .set_clkdiv = s3c_i2s_set_clkdiv, ++ .set_sysclk = s3c_i2s_set_sysclk, ++ }, ++}; ++EXPORT_SYMBOL_GPL(s3c_i2s_dai); ++ ++/* Module information */ ++MODULE_AUTHOR("Ben Dooks, "); ++MODULE_DESCRIPTION("s3c24xx I2S SoC Interface"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s3c64xx/s3c-i2s.h linux-2.6.28.6/sound/soc/s3c64xx/s3c-i2s.h +--- linux-2.6.28/sound/soc/s3c64xx/s3c-i2s.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s3c64xx/s3c-i2s.h 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,44 @@ ++/* ++ * s3c24xx-i2s.c -- ALSA Soc Audio Layer ++ * ++ * Copyright 2005 Wolfson Microelectronics PLC. ++ * Author: Graeme Gregory ++ * graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * Revision history ++ * 10th Nov 2006 Initial version. ++ */ ++ ++#ifndef S3C24XXI2S_H_ ++#define S3C24XXI2S_H_ ++ ++/* clock sources */ ++#define S3C24XX_CLKSRC_PCLK 0 ++#define S3C24XX_CLKSRC_MPLL 1 ++ ++/* Clock dividers */ ++#define S3C24XX_DIV_MCLK 0 ++#define S3C24XX_DIV_BCLK 1 ++#define S3C24XX_DIV_PRESCALER 2 ++ ++/* prescaler */ ++#if !defined(CONFIG_CPU_S3C6400) && !defined(CONFIG_CPU_S3C6410) ++#define S3C24XX_PRESCALE(a,b) \ ++ (((a - 1) << S3C2410_IISPSR_INTSHIFT) | ((b - 1) << S3C2410_IISPSR_EXTSHFIT)) ++#else ++#define S3C24XX_PRESCALE(a,b) \ ++ (((a - 1) << S3C_IISPSR_INTSHIFT) | ((b - 1) << S3C_IISPSR_INTSHIFT)) ++#endif ++ ++u32 s3c24xx_i2s_get_clockrate(void); ++ ++extern struct snd_soc_dai s3c_i2s_dai; ++extern struct snd_soc_dai s3c_i2s_v40_dai; ++extern struct snd_soc_dai s5p_i2s_v40_dai; ++ ++#endif /*S3C24XXI2S_H_*/ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s3c64xx/s3c-pcm.c linux-2.6.28.6/sound/soc/s3c64xx/s3c-pcm.c +--- linux-2.6.28/sound/soc/s3c64xx/s3c-pcm.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s3c64xx/s3c-pcm.c 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,546 @@ ++/* ++ * s3c-pcm.c -- ALSA Soc Audio Layer ++ * ++ * (c) 2006 Wolfson Microelectronics PLC. ++ * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com ++ * ++ * (c) 2004-2005 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * Ryu Euiyoul ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * Revision history ++ * 11th Dec 2006 Merged with Simtec driver ++ * 10th Nov 2006 Initial version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++//#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "s3c-pcm.h" ++ ++#if defined CONFIG_SND_S3C6400_SOC_AC97 ++#define MAIN_DMA_CH 1 ++#else /*S3C6400 I2S */ ++#define MAIN_DMA_CH 0 ++#endif ++ ++#ifdef CONFIG_SND_DEBUG ++#define s3cdbg(x...) printk(x) ++#else ++#define s3cdbg(x...) ++#endif ++ ++static const struct snd_pcm_hardware s3c24xx_pcm_hardware = { ++ .info = SNDRV_PCM_INFO_INTERLEAVED | ++ SNDRV_PCM_INFO_BLOCK_TRANSFER | ++ SNDRV_PCM_INFO_MMAP | ++ SNDRV_PCM_INFO_MMAP_VALID, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE | ++ SNDRV_PCM_FMTBIT_U16_LE | ++ SNDRV_PCM_FMTBIT_U8 | ++ SNDRV_PCM_FMTBIT_S24_LE | ++ SNDRV_PCM_FMTBIT_S8, ++ .channels_min = 2, ++ .channels_max = 2, ++ .buffer_bytes_max = 128*1024, ++ .period_bytes_min = PAGE_SIZE, ++ .period_bytes_max = PAGE_SIZE*2, ++ .periods_min = 2, ++ .periods_max = 128, ++ .fifo_size = 32, ++}; ++ ++struct s3c24xx_runtime_data { ++ spinlock_t lock; ++ int state; ++ unsigned int dma_loaded; ++ unsigned int dma_limit; ++ unsigned int dma_period; ++ dma_addr_t dma_start; ++ dma_addr_t dma_pos; ++ dma_addr_t dma_end; ++ struct s3c24xx_pcm_dma_params *params; ++}; ++ ++/* s3c24xx_pcm_enqueue ++ * ++ * place a dma buffer onto the queue for the dma system ++ * to handle. ++*/ ++static void s3c24xx_pcm_enqueue(struct snd_pcm_substream *substream) ++{ ++ struct s3c24xx_runtime_data *prtd = substream->runtime->private_data; ++ dma_addr_t pos = prtd->dma_pos; ++ int ret; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ while (prtd->dma_loaded < prtd->dma_limit) { ++ unsigned long len = prtd->dma_period; ++ ++ s3cdbg("dma_loaded: %d\n",prtd->dma_loaded); ++ ++ if ((pos + len) > prtd->dma_end) { ++ len = prtd->dma_end - pos; ++ s3cdbg(KERN_DEBUG "%s: corrected dma len %ld\n", ++ __FUNCTION__, len); ++ } ++ ++ ret = s3c2410_dma_enqueue(prtd->params->channel, ++ substream, pos, len); ++ ++ if (ret == 0) { ++ prtd->dma_loaded++; ++ pos += prtd->dma_period; ++ if (pos >= prtd->dma_end) ++ pos = prtd->dma_start; ++ } else ++ break; ++ } ++ ++ prtd->dma_pos = pos; ++} ++ ++static void s3c24xx_audio_buffdone(struct s3c2410_dma_chan *channel, ++ void *dev_id, int size, ++ enum s3c2410_dma_buffresult result) ++{ ++ struct snd_pcm_substream *substream = dev_id; ++ struct s3c24xx_runtime_data *prtd; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ if (result == S3C2410_RES_ABORT || result == S3C2410_RES_ERR){ ++ return; ++ } ++ else { ++ ++ if (!substream) ++ return; ++ ++ prtd = substream->runtime->private_data; ++ snd_pcm_period_elapsed(substream); ++ ++ spin_lock(&prtd->lock); ++ if (prtd->state & ST_RUNNING) { ++ prtd->dma_loaded--; ++ s3c24xx_pcm_enqueue(substream); ++ } ++ ++ prtd->dma_loaded--; ++ spin_unlock(&prtd->lock); ++ } ++#if 0 ++ struct snd_pcm_substream *substream = dev_id; ++ struct s3c24xx_runtime_data *prtd = substream->runtime->private_data; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ if (result == S3C2410_RES_ABORT || result == S3C2410_RES_ERR) ++ return; ++ ++ snd_pcm_period_elapsed(substream); ++ ++ spin_lock(&prtd->lock); ++ if (prtd->state & ST_RUNNING) { ++ prtd->dma_loaded--; ++ s3c24xx_pcm_enqueue(substream); ++ } ++ ++ spin_unlock(&prtd->lock); ++#endif ++} ++ ++static int s3c24xx_pcm_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct s3c24xx_runtime_data *prtd = runtime->private_data; ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct s3c24xx_pcm_dma_params *dma = rtd->dai->cpu_dai->dma_data; ++ unsigned long totbytes = params_buffer_bytes(params); ++ int ret=0; ++ ++ s3cdbg("Entered %s, params = %p \n", __FUNCTION__, prtd->params); ++ ++ /* return if this is a bufferless transfer e.g. ++ * codec <--> BT codec or GSM modem -- lg FIXME */ ++ if (!dma) ++ return 0; ++ ++ /* this may get called several times by oss emulation ++ * with different params */ ++ if (prtd->params == NULL) { ++ prtd->params = dma; ++ s3cdbg("params %p, client %p, channel %d\n", prtd->params, ++ prtd->params->client, prtd->params->channel); ++ ++ ++ /* prepare DMA */ ++ ret = s3c2410_dma_request(prtd->params->channel, ++ prtd->params->client, NULL); ++ ++ if (ret) { ++ printk(KERN_ERR "failed to get dma channel\n"); ++ return ret; ++ } ++ } else if (prtd->params != dma) { ++ s3c2410_dma_free(prtd->params->channel, prtd->params->client); ++ prtd->params = dma; ++ s3cdbg("params %p, client %p, channel %d\n", prtd->params, ++ prtd->params->client, prtd->params->channel); ++ ++ ++ /* prepare DMA */ ++ ret = s3c2410_dma_request(prtd->params->channel, ++ prtd->params->client, NULL); ++ ++ if (ret) { ++ printk(KERN_ERR "failed to get dma channel\n"); ++ return ret; ++ } ++ } ++ ++ /* channel needs configuring for mem=>device, increment memory addr, ++ * sync to pclk, half-word transfers to the IIS-FIFO. */ ++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410) && !defined(CONFIG_CPU_S5PC100) && !defined (CONFIG_CPU_S5P6440) ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ s3c2410_dma_devconfig(prtd->params->channel, ++ S3C2410_DMASRC_MEM, S3C2410_DISRCC_INC | ++ S3C2410_DISRCC_APB, prtd->params->dma_addr); ++ ++ s3c2410_dma_config(prtd->params->channel, ++ prtd->params->dma_size, ++ S3C2410_DCON_SYNC_PCLK | ++ S3C2410_DCON_HANDSHAKE); ++ } else { ++ s3c2410_dma_config(prtd->params->channel, ++ prtd->params->dma_size, ++ S3C2410_DCON_HANDSHAKE | ++ S3C2410_DCON_SYNC_PCLK); ++ ++ s3c2410_dma_devconfig(prtd->params->channel, ++ S3C2410_DMASRC_HW, 0x3, ++ prtd->params->dma_addr); ++ } ++ ++#else ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ s3c2410_dma_devconfig(prtd->params->channel, ++ S3C2410_DMASRC_MEM, 0, ++ prtd->params->dma_addr); ++ ++ s3c2410_dma_config(prtd->params->channel, ++ prtd->params->dma_size, 0); ++ } else { ++ s3c2410_dma_devconfig(prtd->params->channel, ++ S3C2410_DMASRC_HW, 0, ++ prtd->params->dma_addr); ++ ++ s3c2410_dma_config(prtd->params->channel, ++ prtd->params->dma_size, 0); ++ } ++#endif ++ ++ s3c2410_dma_set_buffdone_fn(prtd->params->channel, ++ s3c24xx_audio_buffdone); ++ ++ snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); ++ ++ runtime->dma_bytes = totbytes; ++ ++ spin_lock_irq(&prtd->lock); ++ prtd->dma_loaded = 0; ++ prtd->dma_limit = runtime->hw.periods_min; ++ prtd->dma_period = params_period_bytes(params); ++ prtd->dma_start = runtime->dma_addr; ++ prtd->dma_pos = prtd->dma_start; ++ prtd->dma_end = prtd->dma_start + totbytes; ++ spin_unlock_irq(&prtd->lock); ++ ++ s3cdbg("Entered %s, line %d \n", __FUNCTION__, __LINE__); ++ return 0; ++} ++ ++static int s3c24xx_pcm_hw_free(struct snd_pcm_substream *substream) ++{ ++ struct s3c24xx_runtime_data *prtd = substream->runtime->private_data; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ /* TODO - do we need to ensure DMA flushed */ ++ snd_pcm_set_runtime_buffer(substream, NULL); ++ ++ if (prtd->params) { ++ s3c2410_dma_free(prtd->params->channel, prtd->params->client); ++ prtd->params = NULL; ++ } ++ ++ return 0; ++} ++ ++static int s3c24xx_pcm_prepare(struct snd_pcm_substream *substream) ++{ ++ struct s3c24xx_runtime_data *prtd = substream->runtime->private_data; ++ int ret = 0; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410) ++ /* return if this is a bufferless transfer e.g. ++ * codec <--> BT codec or GSM modem -- lg FIXME */ ++ if (!prtd->params) ++ return 0; ++#endif ++ ++ /* flush the DMA channel */ ++ s3c2410_dma_ctrl(prtd->params->channel, S3C2410_DMAOP_FLUSH); ++ ++ prtd->dma_loaded = 0; ++ ++ prtd->dma_pos = prtd->dma_start; ++ ++ /* enqueue dma buffers */ ++ s3c24xx_pcm_enqueue(substream); ++ ++ return ret; ++} ++ ++static int s3c24xx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) ++{ ++ struct s3c24xx_runtime_data *prtd = substream->runtime->private_data; ++ int ret = 0; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ spin_lock(&prtd->lock); ++ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ prtd->state |= ST_RUNNING; ++ s3c2410_dma_ctrl(prtd->params->channel, S3C2410_DMAOP_START); ++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410) && !defined (CONFIG_CPU_S5P6440) ++ s3c2410_dma_ctrl(prtd->params->channel, S3C2410_DMAOP_STARTED); ++#endif ++ break; ++ ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ++ prtd->state &= ~ST_RUNNING; ++ s3c2410_dma_ctrl(prtd->params->channel, S3C2410_DMAOP_STOP); ++ break; ++ ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ spin_unlock(&prtd->lock); ++ ++ return ret; ++} ++ ++static snd_pcm_uframes_t ++ s3c24xx_pcm_pointer(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct s3c24xx_runtime_data *prtd = runtime->private_data; ++ unsigned long res; ++ dma_addr_t src, dst; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ spin_lock(&prtd->lock); ++ ++ s3c2410_dma_getposition(prtd->params->channel, &src, &dst); ++ ++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) ++ res = dst - prtd->dma_start; ++ else ++ res = src - prtd->dma_start; ++ ++ spin_unlock(&prtd->lock); ++ ++ s3cdbg("Pointer %x %x\n",src,dst); ++ ++ /* we seem to be getting the odd error from the pcm library due ++ * to out-of-bounds pointers. this is maybe due to the dma engine ++ * not having loaded the new values for the channel before being ++ * callled... (todo - fix ) ++ */ ++ ++ if (res >= snd_pcm_lib_buffer_bytes(substream)) { ++ if (res == snd_pcm_lib_buffer_bytes(substream)) ++ res = 0; ++ } ++ ++ return bytes_to_frames(substream->runtime, res); ++} ++ ++static int s3c24xx_pcm_open(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct s3c24xx_runtime_data *prtd; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ snd_soc_set_runtime_hwparams(substream, &s3c24xx_pcm_hardware); ++ ++ prtd = kzalloc(sizeof(struct s3c24xx_runtime_data), GFP_KERNEL); ++ if (prtd == NULL) ++ return -ENOMEM; ++ ++ spin_lock_init(&prtd->lock); ++ ++ runtime->private_data = prtd; ++ return 0; ++} ++ ++static int s3c24xx_pcm_close(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct s3c24xx_runtime_data *prtd = runtime->private_data; ++ ++ s3cdbg("Entered %s, prtd = %p\n", __FUNCTION__, prtd); ++ ++ if (prtd) ++ kfree(prtd); ++ else ++ printk("s3c24xx_pcm_close called with prtd == NULL\n"); ++ ++ return 0; ++} ++ ++static int s3c24xx_pcm_mmap(struct snd_pcm_substream *substream, ++ struct vm_area_struct *vma) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ return dma_mmap_writecombine(substream->pcm->card->dev, vma, ++ runtime->dma_area, ++ runtime->dma_addr, ++ runtime->dma_bytes); ++} ++ ++static struct snd_pcm_ops s3c24xx_pcm_ops = { ++ .open = s3c24xx_pcm_open, ++ .close = s3c24xx_pcm_close, ++ .ioctl = snd_pcm_lib_ioctl, ++ .hw_params = s3c24xx_pcm_hw_params, ++ .hw_free = s3c24xx_pcm_hw_free, ++ .prepare = s3c24xx_pcm_prepare, ++ .trigger = s3c24xx_pcm_trigger, ++ .pointer = s3c24xx_pcm_pointer, ++ .mmap = s3c24xx_pcm_mmap, ++}; ++ ++static int s3c24xx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream) ++{ ++ struct snd_pcm_substream *substream = pcm->streams[stream].substream; ++ struct snd_dma_buffer *buf = &substream->dma_buffer; ++ size_t size = s3c24xx_pcm_hardware.buffer_bytes_max; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ buf->dev.type = SNDRV_DMA_TYPE_DEV; ++ buf->dev.dev = pcm->card->dev; ++ buf->private_data = NULL; ++ buf->area = dma_alloc_writecombine(pcm->card->dev, size, ++ &buf->addr, GFP_KERNEL); ++ if (!buf->area) ++ return -ENOMEM; ++ buf->bytes = size; ++ return 0; ++} ++ ++static void s3c24xx_pcm_free_dma_buffers(struct snd_pcm *pcm) ++{ ++ struct snd_pcm_substream *substream; ++ struct snd_dma_buffer *buf; ++ int stream; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ for (stream = 0; stream < 2; stream++) { ++ substream = pcm->streams[stream].substream; ++ if (!substream) ++ continue; ++ ++ buf = &substream->dma_buffer; ++ if (!buf->area) ++ continue; ++ ++ dma_free_writecombine(pcm->card->dev, buf->bytes, ++ buf->area, buf->addr); ++ buf->area = NULL; ++ } ++} ++ ++static u64 s3c24xx_pcm_dmamask = DMA_32BIT_MASK; ++ ++static int s3c24xx_pcm_new(struct snd_card *card, ++ struct snd_soc_dai *dai, struct snd_pcm *pcm) ++{ ++ int ret = 0; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ if (!card->dev->dma_mask) ++ card->dev->dma_mask = &s3c24xx_pcm_dmamask; ++ if (!card->dev->coherent_dma_mask) ++ card->dev->coherent_dma_mask = 0xffffffff; ++ ++ if (dai->playback.channels_min) { ++ ret = s3c24xx_pcm_preallocate_dma_buffer(pcm, ++ SNDRV_PCM_STREAM_PLAYBACK); ++ if (ret) ++ goto out; ++ } ++ ++ if (dai->capture.channels_min) { ++ ret = s3c24xx_pcm_preallocate_dma_buffer(pcm, ++ SNDRV_PCM_STREAM_CAPTURE); ++ if (ret) ++ goto out; ++ } ++ out: ++ return ret; ++} ++ ++struct snd_soc_platform s3c24xx_soc_platform = { ++ .name = "s3c24xx-audio", ++ .pcm_ops = &s3c24xx_pcm_ops, ++ .pcm_new = s3c24xx_pcm_new, ++ .pcm_free = s3c24xx_pcm_free_dma_buffers, ++}; ++ ++EXPORT_SYMBOL_GPL(s3c24xx_soc_platform); ++ ++MODULE_AUTHOR("Ben Dooks, "); ++MODULE_DESCRIPTION("Samsung S3C24XX PCM DMA module"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s3c64xx/s3c-pcm.h linux-2.6.28.6/sound/soc/s3c64xx/s3c-pcm.h +--- linux-2.6.28/sound/soc/s3c64xx/s3c-pcm.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s3c64xx/s3c-pcm.h 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,40 @@ ++/* ++ * s3c24xx-pcm.h -- ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * ALSA PCM interface for the Samsung S3C24xx CPU ++ */ ++ ++#ifndef _S3C24XX_PCM_H ++#define _S3C24XX_PCM_H ++ ++#define ST_RUNNING (1<<0) ++#define ST_OPENED (1<<1) ++ ++struct s3c24xx_pcm_dma_params { ++ struct s3c2410_dma_client *client; /* stream identifier */ ++ int channel; /* Channel ID */ ++ dma_addr_t dma_addr; ++ int dma_size; /* Size of the DMA transfer */ ++}; ++ ++#define S3C24XX_DAI_I2S 0 ++ ++#if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410) ++#define S3CPCM_DCON 0 ++#define S3CPCM_HWCFG 0 ++#else ++//#include ++#define S3CPCM_DCON S3C2410_DCON_SYNC_PCLK|S3C2410_DCON_HANDSHAKE ++#define S3CPCM_HWCFG S3C2410_DISRCC_INC|S3C2410_DISRCC_APB ++#endif ++ ++/* platform data */ ++extern struct snd_soc_platform s3c24xx_soc_platform; ++extern struct snd_ac97_bus_ops s3c24xx_ac97_ops; ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s3c64xx/s3c6410-i2s.c linux-2.6.28.6/sound/soc/s3c64xx/s3c6410-i2s.c +--- linux-2.6.28/sound/soc/s3c64xx/s3c6410-i2s.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s3c64xx/s3c6410-i2s.c 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,699 @@ ++/* ++ * s3c6410-i2s.c -- ALSA Soc Audio Layer ++ * ++ * (c) 2009 Samsung Electronics - Jaswinder Singh Brar ++ * Derived from Ben Dooks' driver for s3c24xx ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "s3c-pcm.h" ++#include "s3c6410-i2s.h" ++ ++static struct s3c2410_dma_client s3c6410_dma_client_out = { ++ .name = "I2S PCM Stereo out" ++}; ++ ++static struct s3c2410_dma_client s3c6410_dma_client_in = { ++ .name = "I2S PCM Stereo in" ++}; ++ ++static struct s3c24xx_pcm_dma_params s3c6410_i2s_pcm_stereo_out = { ++ .client = &s3c6410_dma_client_out, ++#ifdef CONFIG_SND_S3C6410_SOC_I2S_V32 ++ .channel = DMACH_I2S_OUT, ++ .dma_addr = S3C64XX_PA_IIS + S3C64XX_IISTXD, ++#else ++ .channel = DMACH_I2S_V40_OUT, ++ .dma_addr = S3C64XX_PA_IIS_V40 + S3C64XX_IISTXD, ++#endif ++ .dma_size = 4, ++}; ++ ++static struct s3c24xx_pcm_dma_params s3c6410_i2s_pcm_stereo_in = { ++ .client = &s3c6410_dma_client_in, ++#ifdef CONFIG_SND_S3C6410_SOC_I2S_V32 ++ .channel = DMACH_I2S_IN, ++ .dma_addr = S3C64XX_PA_IIS + S3C64XX_IISRXD, ++#else ++ .channel = DMACH_I2S_V40_IN, ++ .dma_addr = S3C64XX_PA_IIS_V40 + S3C64XX_IISRXD, ++#endif ++ .dma_size = 4, ++}; ++ ++struct s3c6410_i2s_info { ++ void __iomem *regs; ++ struct clk *iis_clk; ++ struct clk *audio_bus; ++ u32 iiscon; ++ u32 iismod; ++ u32 iisfic; ++ u32 iispsr; ++ u32 slave; ++ u32 clk_rate; ++}; ++static struct s3c6410_i2s_info s3c6410_i2s; ++ ++static void s3c6410_snd_txctrl(int on) ++{ ++ u32 iiscon; ++ ++ iiscon = readl(s3c6410_i2s.regs + S3C64XX_IISCON); ++ ++ if(on){ ++ iiscon |= S3C64XX_IISCON_I2SACTIVE; ++ iiscon &= ~S3C64XX_IISCON_TXCHPAUSE; ++ iiscon &= ~S3C64XX_IISCON_TXDMAPAUSE; ++ iiscon |= S3C64XX_IISCON_TXDMACTIVE; ++ writel(iiscon, s3c6410_i2s.regs + S3C64XX_IISCON); ++ }else{ ++ iiscon &= ~S3C64XX_IISCON_I2SACTIVE; ++ iiscon |= S3C64XX_IISCON_TXCHPAUSE; ++ iiscon |= S3C64XX_IISCON_TXDMAPAUSE; ++ iiscon &= ~S3C64XX_IISCON_TXDMACTIVE; ++ writel(iiscon, s3c6410_i2s.regs + S3C64XX_IISCON); ++ } ++} ++ ++static void s3c6410_snd_rxctrl(int on) ++{ ++ u32 iiscon; ++ ++ iiscon = readl(s3c6410_i2s.regs + S3C64XX_IISCON); ++ ++ if(on){ ++ iiscon |= S3C64XX_IISCON_I2SACTIVE; ++ iiscon &= ~S3C64XX_IISCON_RXCHPAUSE; ++ iiscon &= ~S3C64XX_IISCON_RXDMAPAUSE; ++ iiscon |= S3C64XX_IISCON_RXDMACTIVE; ++ writel(iiscon, s3c6410_i2s.regs + S3C64XX_IISCON); ++ }else{ ++ iiscon &= ~S3C64XX_IISCON_I2SACTIVE; ++ iiscon |= S3C64XX_IISCON_RXCHPAUSE; ++ iiscon |= S3C64XX_IISCON_RXDMAPAUSE; ++ iiscon &= ~S3C64XX_IISCON_RXDMACTIVE; ++ writel(iiscon, s3c6410_i2s.regs + S3C64XX_IISCON); ++ } ++ ++} ++ ++/* ++ * Wait for the LR signal to allow synchronisation to the L/R clock ++ * from the codec. May only be needed for slave mode. ++ */ ++static int s3c6410_snd_lrsync(void) ++{ ++ u32 iiscon; ++ int timeout = 50; /* 5ms */ ++ ++ while (1) { ++ iiscon = readl(s3c6410_i2s.regs + S3C64XX_IISCON); ++ if (iiscon & S3C64XX_IISCON_LRI) ++ break; ++ ++ if (!timeout--) ++ return -ETIMEDOUT; ++ udelay(100); ++ } ++ ++ return 0; ++} ++ ++/* ++ * Set s3c64xx I2S DAI format ++ */ ++static int s3c6410_i2s_set_fmt(struct snd_soc_dai *cpu_dai, ++ unsigned int fmt) ++{ ++ u32 iismod; ++ ++ iismod = readl(s3c6410_i2s.regs + S3C64XX_IISMOD); ++ iismod &= ~S3C64XX_IISMOD_SDFMASK; ++ ++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { ++ case SND_SOC_DAIFMT_CBM_CFM: ++ s3c6410_i2s.slave = 1; ++ break; ++ case SND_SOC_DAIFMT_CBS_CFS: ++ s3c6410_i2s.slave = 0; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { ++ case SND_SOC_DAIFMT_I2S: ++ iismod &= ~S3C64XX_IISMOD_MSB; ++ break; ++ case SND_SOC_DAIFMT_LEFT_J: ++ iismod |= S3C64XX_IISMOD_MSB; ++ break; ++ case SND_SOC_DAIFMT_RIGHT_J: ++ iismod |= S3C64XX_IISMOD_LSB; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { ++ case SND_SOC_DAIFMT_NB_NF: ++ iismod &= ~S3C64XX_IISMOD_LRP; ++ break; ++ case SND_SOC_DAIFMT_NB_IF: ++ iismod |= S3C64XX_IISMOD_LRP; ++ break; ++ case SND_SOC_DAIFMT_IB_IF: ++ case SND_SOC_DAIFMT_IB_NF: ++ default: ++ printk("Inv-combo(%d) not supported!\n", fmt & SND_SOC_DAIFMT_FORMAT_MASK); ++ return -EINVAL; ++ } ++ ++ writel(iismod, s3c6410_i2s.regs + S3C64XX_IISMOD); ++ return 0; ++} ++ ++static int s3c6410_i2s_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ u32 iismod; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ rtd->dai->cpu_dai->dma_data = &s3c6410_i2s_pcm_stereo_out; ++ else ++ rtd->dai->cpu_dai->dma_data = &s3c6410_i2s_pcm_stereo_in; ++ ++ /* Working copies of register */ ++ iismod = readl(s3c6410_i2s.regs + S3C64XX_IISMOD); ++ iismod &= ~S3C64XX_IISMOD_BLCMASK; ++ ++ /* TODO */ ++ switch(params_channels(params)) { ++ case 1: ++ break; ++ case 2: ++ break; ++ case 4: ++ break; ++ case 6: ++ break; ++ default: ++ break; ++ } ++ ++ /* RFS & BFS are set by dai_link(machine specific) code via set_clkdiv */ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S8: ++ iismod |= S3C64XX_IISMOD_8BIT; ++ break; ++ case SNDRV_PCM_FORMAT_S16_LE: ++ iismod |= S3C64XX_IISMOD_16BIT; ++ break; ++ case SNDRV_PCM_FORMAT_S24_LE: ++ iismod |= S3C64XX_IISMOD_24BIT; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ writel(iismod, s3c6410_i2s.regs + S3C64XX_IISMOD); ++ ++ return 0; ++} ++ ++static int s3c6410_i2s_startup(struct snd_pcm_substream *substream) ++{ ++ u32 iiscon, iisfic; ++ ++ iiscon = readl(s3c6410_i2s.regs + S3C64XX_IISCON); ++ ++ /* FIFOs must be flushed before enabling PSR and other MOD bits, so we do it here. */ ++ if(!(iiscon & S3C64XX_IISCON_I2SACTIVE)){ ++ iisfic = readl(s3c6410_i2s.regs + S3C64XX_IISFIC); ++ iisfic |= S3C64XX_IISFIC_TFLUSH | S3C64XX_IISFIC_RFLUSH; ++ writel(iisfic, s3c6410_i2s.regs + S3C64XX_IISFIC); ++ } ++ ++ do{ ++ iiscon = readl(s3c6410_i2s.regs + S3C64XX_IISCON); ++ }while((iiscon & 0x780) != (S3C64XX_IISCON_FRXEMPT | S3C64XX_IISCON_FTX0EMPT)); ++ iisfic = readl(s3c6410_i2s.regs + S3C64XX_IISFIC); ++ iisfic &= ~(S3C64XX_IISFIC_TFLUSH | S3C64XX_IISFIC_RFLUSH); ++ writel(iisfic, s3c6410_i2s.regs + S3C64XX_IISFIC); ++ ++ return 0; ++} ++ ++static int s3c6410_i2s_prepare(struct snd_pcm_substream *substream) ++{ ++ u32 iismod; ++ ++ iismod = readl(s3c6410_i2s.regs + S3C64XX_IISMOD); ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){ ++ if((iismod & S3C64XX_IISMOD_TXRMASK) == S3C64XX_IISMOD_RX){ ++ iismod &= ~S3C64XX_IISMOD_TXRMASK; ++ iismod |= S3C64XX_IISMOD_TXRX; ++ } ++ }else{ ++ if((iismod & S3C64XX_IISMOD_TXRMASK) == S3C64XX_IISMOD_TX){ ++ iismod &= ~S3C64XX_IISMOD_TXRMASK; ++ iismod |= S3C64XX_IISMOD_TXRX; ++ } ++ } ++ ++ writel(iismod, s3c6410_i2s.regs + S3C64XX_IISMOD); ++ ++ return 0; ++} ++ ++static int s3c6410_i2s_trigger(struct snd_pcm_substream *substream, int cmd) ++{ ++ int ret = 0; ++ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ if (s3c6410_i2s.slave) { ++ ret = s3c6410_snd_lrsync(); ++ if (ret) ++ goto exit_err; ++ } ++ ++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) ++ s3c6410_snd_rxctrl(1); ++ else ++ s3c6410_snd_txctrl(1); ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) ++ s3c6410_snd_rxctrl(0); ++ else ++ s3c6410_snd_txctrl(0); ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++exit_err: ++ return ret; ++} ++ ++/* ++ * Set s3c64xx Clock source ++ * Since, we set frequencies using PreScaler and BFS, RFS, we select input clock source to the IIS here. ++ */ ++static int s3c6410_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, ++ int clk_id, unsigned int freq, int dir) ++{ ++ struct clk *clk; ++ u32 iismod = readl(s3c6410_i2s.regs + S3C64XX_IISMOD); ++ ++ switch (clk_id) { ++ case S3C6410_CLKSRC_PCLK: ++ if(s3c6410_i2s.slave) ++ return -EINVAL; ++ iismod &= ~S3C64XX_IISMOD_IMSMASK; ++ iismod |= clk_id; ++ s3c6410_i2s.clk_rate = clk_get_rate(s3c6410_i2s.iis_clk); ++ break; ++ ++#ifdef USE_CLKAUDIO ++ case S3C6410_CLKSRC_CLKAUDIO: ++ if(s3c6410_i2s.slave) ++ return -EINVAL; ++ iismod &= ~S3C64XX_IISMOD_IMSMASK; ++ iismod |= clk_id; ++/* ++8000 x 256 = 2048000 ++ 49152000 mod 2048000 = 0 ++ 32768000 mod 2048000 = 0 ++ 73728000 mod 2048000 = 0 ++ ++11025 x 256 = 2822400 ++ 67738000 mod 2822400 = 400 ++ ++16000 x 256 = 4096000 ++ 49152000 mod 4096000 = 0 ++ 32768000 mod 4096000 = 0 ++ 73728000 mod 4096000 = 0 ++ ++22050 x 256 = 5644800 ++ 67738000 mod 5644800 = 400 ++ ++32000 x 256 = 8192000 ++ 49152000 mod 8192000 = 0 ++ 32768000 mod 8192000 = 0 ++ 73728000 mod 8192000 = 0 ++ ++44100 x 256 = 11289600 ++ 67738000 mod 11289600 = 400 ++ ++48000 x 256 = 12288000 ++ 49152000 mod 12288000 = 0 ++ 73728000 mod 12288000 = 0 ++ ++64000 x 256 = 16384000 ++ 49152000 mod 16384000 = 0 ++ 32768000 mod 16384000 = 0 ++ ++88200 x 256 = 22579200 ++ 67738000 mod 22579200 = 400 ++ ++96000 x 256 = 24576000 ++ 49152000 mod 24576000 = 0 ++ 73728000 mod 24576000 = 0 ++ ++ From the table above, we find that 49152000 gives least(0) residue ++ for most sample rates, followed by 67738000. ++*/ ++ clk = clk_get(NULL, "fout_epll"); ++ if (IS_ERR(clk)) { ++ printk("failed to get FOUTepll\n"); ++ return -EBUSY; ++ } ++ clk_disable(clk); ++ switch (freq) { ++ case 8000: ++ case 16000: ++ case 32000: ++ case 48000: ++ case 64000: ++ case 96000: ++ clk_set_rate(clk, 49152000); ++ break; ++ case 11025: ++ case 22050: ++ case 44100: ++ case 88200: ++ default: ++ clk_set_rate(clk, 67738000); ++ break; ++ } ++ clk_enable(clk); ++ s3c6410_i2s.clk_rate = clk_get_rate(s3c6410_i2s.audio_bus); ++ //printk("Setting FOUTepll to %dHz", s3c6410_i2s.clk_rate); ++ clk_put(clk); ++ break; ++#endif ++ ++ case S3C6410_CLKSRC_SLVPCLK: ++ case S3C6410_CLKSRC_I2SEXT: ++ if(!s3c6410_i2s.slave) ++ return -EINVAL; ++ iismod &= ~S3C64XX_IISMOD_IMSMASK; ++ iismod |= clk_id; ++ break; ++ ++ /* Not sure about these two! */ ++ case S3C6410_CDCLKSRC_INT: ++ iismod &= ~S3C64XX_IISMOD_CDCLKCON; ++ break; ++ ++ case S3C6410_CDCLKSRC_EXT: ++ iismod |= S3C64XX_IISMOD_CDCLKCON; ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ writel(iismod, s3c6410_i2s.regs + S3C64XX_IISMOD); ++ return 0; ++} ++ ++/* ++ * Set s3c64xx Clock dividers ++ * NOTE: NOT all combinations of RFS, BFS and BCL are supported! XXX ++ * Machine specific(dai-link) code must consider that while setting MCLK and BCLK in this function. XXX ++ */ ++/* XXX BLC(bits-per-channel) --> BFS(bit clock shud be >= FS*(Bit-per-channel)*2) XXX */ ++/* XXX BFS --> RFS_VAL(must be a multiple of BFS) XXX */ ++/* XXX RFS_VAL & SRC_CLK --> Prescalar Value(SRC_CLK / RFS_VAL / fs - 1) XXX */ ++static int s3c6410_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai, ++ int div_id, int div) ++{ ++ u32 reg; ++ ++ switch (div_id) { ++ case S3C64XX_DIV_MCLK: ++ reg = readl(s3c6410_i2s.regs + S3C64XX_IISMOD) & ~S3C64XX_IISMOD_RFSMASK; ++ switch(div) { ++ case 256: div = S3C64XX_IISMOD_256FS; break; ++ case 512: div = S3C64XX_IISMOD_512FS; break; ++ case 384: div = S3C64XX_IISMOD_384FS; break; ++ case 768: div = S3C64XX_IISMOD_768FS; break; ++ default: return -EINVAL; ++ } ++ writel(reg | div, s3c6410_i2s.regs + S3C64XX_IISMOD); ++ break; ++ case S3C64XX_DIV_BCLK: ++ reg = readl(s3c6410_i2s.regs + S3C64XX_IISMOD) & ~S3C64XX_IISMOD_BFSMASK; ++ switch(div) { ++ case 16: div = S3C64XX_IISMOD_16FS; break; ++ case 24: div = S3C64XX_IISMOD_24FS; break; ++ case 32: div = S3C64XX_IISMOD_32FS; break; ++ case 48: div = S3C64XX_IISMOD_48FS; break; ++ default: return -EINVAL; ++ } ++ writel(reg | div, s3c6410_i2s.regs + S3C64XX_IISMOD); ++ break; ++ case S3C64XX_DIV_PRESCALER: ++ reg = readl(s3c6410_i2s.regs + S3C64XX_IISPSR) & ~S3C64XX_IISPSR_PSRAEN; ++ writel(reg, s3c6410_i2s.regs + S3C64XX_IISPSR); ++ reg = readl(s3c6410_i2s.regs + S3C64XX_IISPSR) & ~S3C64XX_IISPSR_PSVALA; ++ div &= 0x3f; ++ writel(reg | (div<<8) | S3C64XX_IISPSR_PSRAEN, s3c6410_i2s.regs + S3C64XX_IISPSR); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/* ++ * To avoid duplicating clock code, allow machine driver to ++ * get the clockrate from here. ++ */ ++u32 s3c6410_i2s_get_clockrate(void) ++{ ++ return s3c6410_i2s.clk_rate; ++} ++EXPORT_SYMBOL_GPL(s3c6410_i2s_get_clockrate); ++ ++static irqreturn_t s3c_iis_irq(int irqno, void *dev_id) ++{ ++ u32 iiscon; ++ ++ iiscon = readl(s3c6410_i2s.regs + S3C64XX_IISCON); ++ if(S3C64XX_IISCON_FTXURSTATUS & iiscon) { ++ iiscon &= ~S3C64XX_IISCON_FTXURINTEN; ++ iiscon |= S3C64XX_IISCON_FTXURSTATUS; ++ writel(iiscon, s3c6410_i2s.regs + S3C64XX_IISCON); ++ printk("underrun interrupt IISCON = 0x%08x\n", readl(s3c6410_i2s.regs + S3C64XX_IISCON)); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int s3c6410_i2s_probe(struct platform_device *pdev, ++ struct snd_soc_dai *dai) ++{ ++ int ret = 0; ++ struct clk *cm, *cf; ++ ++#ifdef CONFIG_SND_S3C6410_SOC_I2S_V32 ++ s3c6410_i2s.regs = ioremap(S3C64XX_PA_IIS, 0x100); ++#else ++ s3c6410_i2s.regs = ioremap(S3C64XX_PA_IIS_V40, 0x100); ++#endif ++ if (s3c6410_i2s.regs == NULL) ++ return -ENXIO; ++ ++#ifdef CONFIG_SND_S3C6410_SOC_I2S_V32 ++ ret = request_irq(IRQ_S3C6410_IIS, s3c_iis_irq, 0, "s3c-i2s-v32", pdev); ++#else ++ ret = request_irq(IRQ_S3C6410_IIS, s3c_iis_irq, 0, "s3c-i2s-v40", pdev); ++#endif ++ if (ret < 0) { ++ printk("fail to claim i2s irq , ret = %d\n", ret); ++ iounmap(s3c6410_i2s.regs); ++ return -ENODEV; ++ } ++ ++#ifdef CONFIG_SND_S3C6410_SOC_I2S_V32 ++ s3c6410_i2s.iis_clk = clk_get(&pdev->dev, "iis"); ++#else ++ s3c6410_i2s.iis_clk = clk_get(&pdev->dev, "iis_v40"); ++#endif ++ if (IS_ERR(s3c6410_i2s.iis_clk)) { ++ printk("failed to get iis_clock\n"); ++ goto lb5; ++ } ++ clk_enable(s3c6410_i2s.iis_clk); ++ s3c6410_i2s.clk_rate = clk_get_rate(s3c6410_i2s.iis_clk); ++ ++#ifdef USE_CLKAUDIO ++#ifdef CONFIG_SND_S3C6410_SOC_I2S_V32 ++ s3c6410_i2s.audio_bus = clk_get(NULL, "audio-bus0"); ++#else ++ s3c6410_i2s.audio_bus = clk_get(NULL, "audio-bus2"); ++#endif ++ if (IS_ERR(s3c6410_i2s.audio_bus)) { ++ printk("failed to get audio_bus\n"); ++ goto lb4; ++ } ++ ++ cm = clk_get(NULL, "mout_epll"); ++ if (IS_ERR(cm)) { ++ printk("failed to get MOUTepll\n"); ++ goto lb3; ++ } ++ if(clk_set_parent(s3c6410_i2s.audio_bus, cm)){ ++ printk("failed to set MOUTepll as parent of CLKAUDIO0\n"); ++ goto lb2; ++ } ++ ++ cf = clk_get(NULL, "fout_epll"); ++ if (IS_ERR(cf)) { ++ printk("failed to get FOUTepll\n"); ++ goto lb2; ++ } ++ clk_enable(cf); ++ if(clk_set_parent(cm, cf)){ ++ printk("failed to set FOUTepll as parent of MOUTepll\n"); ++ goto lb1; ++ } ++ s3c6410_i2s.clk_rate = clk_get_rate(s3c6410_i2s.audio_bus); ++ clk_put(cf); ++ clk_put(cm); ++#endif ++ ++ writel(S3C64XX_IISCON_I2SACTIVE, s3c6410_i2s.regs + S3C64XX_IISCON); ++ ++ s3c6410_snd_txctrl(0); ++ s3c6410_snd_rxctrl(0); ++ ++ return 0; ++ ++#ifdef USE_CLKAUDIO ++lb1: ++ clk_put(cf); ++lb2: ++ clk_put(cm); ++lb3: ++ clk_put(s3c6410_i2s.audio_bus); ++lb4: ++ clk_disable(s3c6410_i2s.iis_clk); ++ clk_put(s3c6410_i2s.iis_clk); ++#endif ++lb5: ++ free_irq(IRQ_S3C6410_IIS, pdev); ++ iounmap(s3c6410_i2s.regs); ++ ++ return -ENODEV; ++} ++ ++#ifdef CONFIG_PM ++static int s3c6410_i2s_suspend(struct platform_device *pdev, ++ struct snd_soc_dai *cpu_dai) ++{ ++ s3c6410_i2s.iiscon = readl(s3c6410_i2s.regs + S3C64XX_IISCON); ++ s3c6410_i2s.iismod = readl(s3c6410_i2s.regs + S3C64XX_IISMOD); ++ s3c6410_i2s.iisfic = readl(s3c6410_i2s.regs + S3C64XX_IISFIC); ++ s3c6410_i2s.iispsr = readl(s3c6410_i2s.regs + S3C64XX_IISPSR); ++ ++ clk_disable(s3c6410_i2s.iis_clk); ++ ++ return 0; ++} ++ ++static int s3c6410_i2s_resume(struct platform_device *pdev, ++ struct snd_soc_dai *cpu_dai) ++{ ++ clk_enable(s3c6410_i2s.iis_clk); ++ ++ writel(s3c6410_i2s.iiscon, s3c6410_i2s.regs + S3C64XX_IISCON); ++ writel(s3c6410_i2s.iismod, s3c6410_i2s.regs + S3C64XX_IISMOD); ++ writel(s3c6410_i2s.iisfic, s3c6410_i2s.regs + S3C64XX_IISFIC); ++ writel(s3c6410_i2s.iispsr, s3c6410_i2s.regs + S3C64XX_IISPSR); ++ ++ return 0; ++} ++#else ++#define s3c6410_i2s_suspend NULL ++#define s3c6410_i2s_resume NULL ++#endif ++ ++ ++#ifdef CONFIG_SND_S3C6410_SOC_I2S_V32 ++struct snd_soc_dai s3c6410_i2s_v32_dai = { ++#else ++struct snd_soc_dai s3c6410_i2s_v40_dai = { ++#endif ++ .name = "s3c6410-i2s", ++ .id = 0, ++ .type = SND_SOC_DAI_I2S, ++ .probe = s3c6410_i2s_probe, ++ .suspend = s3c6410_i2s_suspend, ++ .resume = s3c6410_i2s_resume, ++ .playback = { ++ .channels_min = 2, ++#ifdef CONFIG_SND_S3C6410_SOC_I2S_V32 ++ .channels_max = 2, ++#else ++ .channels_max = 6, ++#endif ++ .rates = SNDRV_PCM_RATE_8000_96000, ++ .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, ++ }, ++ .capture = { ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_96000, ++ .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, ++ }, ++ .ops = { ++ .hw_params = s3c6410_i2s_hw_params, ++ .prepare = s3c6410_i2s_prepare, ++ .startup = s3c6410_i2s_startup, ++ .trigger = s3c6410_i2s_trigger, ++ }, ++ .dai_ops = { ++ .set_fmt = s3c6410_i2s_set_fmt, ++ .set_clkdiv = s3c6410_i2s_set_clkdiv, ++ .set_sysclk = s3c6410_i2s_set_sysclk, ++ }, ++}; ++#ifdef CONFIG_SND_S3C6410_SOC_I2S_V32 ++EXPORT_SYMBOL_GPL(s3c6410_i2s_v32_dai); ++#else ++EXPORT_SYMBOL_GPL(s3c6410_i2s_v40_dai); ++#endif ++ ++/* Module information */ ++MODULE_AUTHOR("Jaswinder Singh "); ++MODULE_DESCRIPTION("s3c6410 I2S SoC Interface"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s3c64xx/s3c6410-i2s.h linux-2.6.28.6/sound/soc/s3c64xx/s3c6410-i2s.h +--- linux-2.6.28/sound/soc/s3c64xx/s3c6410-i2s.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s3c64xx/s3c6410-i2s.h 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,43 @@ ++/* ++ * s3c64xx-i2s.c -- ALSA Soc Audio Layer ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#ifndef S3C64XXI2S_H_ ++#define S3C64XXI2S_H_ ++ ++#include ++ ++#ifndef CONFIG_SND_S3C6410_SOC_I2S_V32 ++#define IIS_V40 1 ++#endif ++ ++/* clock sources */ ++#define S3C6410_CLKSRC_PCLK S3C64XX_IISMOD_MSTPCLK ++#define S3C6410_CLKSRC_CLKAUDIO S3C64XX_IISMOD_MSTCLKAUDIO ++#define S3C6410_CLKSRC_SLVPCLK S3C64XX_IISMOD_SLVPCLK ++#define S3C6410_CLKSRC_I2SEXT S3C64XX_IISMOD_SLVI2SCLK ++#define S3C6410_CDCLKSRC_INT (4<<10) ++#define S3C6410_CDCLKSRC_EXT (5<<10) ++ ++/* Clock dividers */ ++#define S3C64XX_DIV_MCLK 0 ++#define S3C64XX_DIV_BCLK 1 ++#define S3C64XX_DIV_PRESCALER 2 ++ ++#define USE_CLKAUDIO 1 ++ ++u32 s3c6410_i2s_get_clockrate(void); ++ ++#ifdef CONFIG_SND_S3C6410_SOC_I2S_V32 ++extern struct snd_soc_dai s3c6410_i2s_v32_dai; ++#else ++extern struct snd_soc_dai s3c6410_i2s_v40_dai; ++#endif ++ ++#endif /*S3C64XXI2S_H_*/ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s3c64xx/s3c64xx-ac97.c linux-2.6.28.6/sound/soc/s3c64xx/s3c64xx-ac97.c +--- linux-2.6.28/sound/soc/s3c64xx/s3c64xx-ac97.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s3c64xx/s3c64xx-ac97.c 2010-04-21 06:38:12.000000000 +0200 +@@ -0,0 +1,496 @@ ++/* ++ * s3c6400-ac97.c -- ALSA Soc Audio Layer ++ * ++ * Copyright (C) 2007, Ryu Euiyoul ++ * ++ * (c) 2007 Wolfson Microelectronics PLC. ++ * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com ++ * ++ * Copyright (C) 2007, Ryu Euiyoul ++ * All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * Revision history ++ * 21st Mar 2007 Initial Version ++ * 20th Sep 2007 Apply at s3c6400 ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++//#include ++ ++//#include "../s3c24xx/s3c-pcm.h" ++#include "s3c-pcm.h" ++#include "s3c64xx-ac97.h" ++ ++//#define CONFIG_SND_DEBUG 1 ++ ++#ifdef CONFIG_SND_DEBUG ++#define s3cdbg(x...) printk(x) ++#else ++#define s3cdbg(x...) ++#endif ++ ++extern struct clk *clk_get(struct device *dev, const char *id); ++extern int clk_enable(struct clk *clk); ++extern void clk_disable(struct clk *clk); ++ ++struct s3c24xx_ac97_info { ++ void __iomem *regs; ++ struct clk *ac97_clk; ++}; ++static struct s3c24xx_ac97_info s3c24xx_ac97; ++ ++static u32 codec_ready; ++static DEFINE_MUTEX(ac97_mutex); ++static DECLARE_WAIT_QUEUE_HEAD(gsr_wq); ++ ++static unsigned short s3c6400_ac97_read(struct snd_ac97 *ac97, ++ unsigned short reg) ++{ ++ u32 ac_glbctrl; ++ u32 ac_codec_cmd; ++ u32 stat, addr, data; ++ ++ s3cdbg("Entered %s: reg=0x%x\n", __FUNCTION__, reg); ++ ++ mutex_lock(&ac97_mutex); ++ ++ codec_ready = S3C_AC97_GLBSTAT_CODECREADY; ++ ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg); ++ writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD); ++ ++ udelay(1000); ++ ++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ ++ stat = readl(s3c24xx_ac97.regs + S3C_AC97_STAT); ++ addr = (stat >> 16) & 0x7f; ++ data = (stat & 0xffff); ++ ++ wait_event_timeout(gsr_wq,addr==reg,1); ++ if(addr!=reg){ ++ printk(KERN_ERR"AC97: read error (ac97_reg=%x addr=%x)\n", reg, addr); ++ printk(KERN_ERR"Check audio codec jumpper settings\n\n"); ++ goto out; ++ } ++ ++out: mutex_unlock(&ac97_mutex); ++ return (unsigned short)data; ++} ++ ++static void s3c6400_ac97_write(struct snd_ac97 *ac97, unsigned short reg, ++ unsigned short val) ++{ ++ u32 ac_glbctrl; ++ u32 ac_codec_cmd; ++ u32 stat, data; ++ ++ s3cdbg("Entered %s: reg=0x%x, val=0x%x\n", __FUNCTION__,reg,val); ++ ++ mutex_lock(&ac97_mutex); ++ ++ codec_ready = S3C_AC97_GLBSTAT_CODECREADY; ++ ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val); ++ writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD); ++ ++ udelay(50); ++ ++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ ++ ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ; ++ writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD); ++ ++ stat = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD); ++ data = (stat & 0xffff); ++ ++ wait_event_timeout(gsr_wq,data==val,1); ++ if(data!=val){ ++ printk("%s: write error (ac97_val=%x data=%x)\n", ++ __FUNCTION__, val, data); ++ } ++ ++ mutex_unlock(&ac97_mutex); ++} ++ ++static void s3c6400_ac97_warm_reset(struct snd_ac97 *ac97) ++{ ++ u32 ac_glbctrl; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ ac_glbctrl |= S3C_AC97_GLBCTRL_WARMRESET; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ msleep(1); ++ ++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_WARMRESET; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ msleep(1); ++ ++ ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ msleep(1); ++ ++ ac_glbctrl = S3C_AC97_GLBCTRL_TRANSFERDATAENABLE; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ msleep(1); ++ ++ ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA | ++ S3C_AC97_GLBCTRL_PCMINTM_DMA | S3C_AC97_GLBCTRL_MICINTM_DMA; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ ++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ ac_glbctrl |= S3C_AC97_GLBCTRL_ACLINKON; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ udelay(1000); ++} ++ ++static void s3c6400_ac97_cold_reset(struct snd_ac97 *ac97) ++{ ++ u32 ac_glbctrl; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ msleep(1); ++ ++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_COLDRESET; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ msleep(1); ++ ++ ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ msleep(1); ++ ++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_COLDRESET; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ msleep(1); ++} ++ ++static irqreturn_t s3c6400_ac97_irq(int irq, void *dev_id) ++{ ++ int status; ++ u32 ac_glbctrl, ac_glbstat; ++ ++ ac_glbstat = readl(s3c24xx_ac97.regs + S3C_AC97_GLBSTAT); ++ ++ s3cdbg("Entered %s: AC_GLBSTAT = 0x%x\n", __FUNCTION__, ac_glbstat); ++ ++ status = ac_glbstat & codec_ready; ++ ++ ++ if (status) { ++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ wake_up(&gsr_wq); ++ } ++ return IRQ_HANDLED; ++} ++ ++struct snd_ac97_bus_ops soc_ac97_ops = { ++ .read = s3c6400_ac97_read, ++ .write = s3c6400_ac97_write, ++ .warm_reset = s3c6400_ac97_warm_reset, ++ .reset = s3c6400_ac97_cold_reset, ++}; ++ ++static struct s3c2410_dma_client s3c6400_dma_client_out = { ++ .name = "AC97 PCM Stereo out" ++}; ++ ++static struct s3c24xx_pcm_dma_params s3c6400_ac97_pcm_stereo_out = { ++ .client = &s3c6400_dma_client_out, ++ .channel = DMACH_AC97_PCM_OUT, ++ .dma_addr = S3C6400_PA_AC97 + S3C_AC97_PCM_DATA, ++ .dma_size = 4, ++}; ++ ++#ifdef CONFIG_SOUND_WM9713_INPUT_STREAM_MIC ++static struct s3c2410_dma_client s3c6400_dma_client_micin = { ++ .name = "AC97 Mic Mono in" ++}; ++ ++static struct s3c24xx_pcm_dma_params s3c6400_ac97_mic_mono_in = { ++ .client = &s3c6400_dma_client_micin, ++ .channel = DMACH_AC97_MIC_IN, ++ .dma_addr = S3C6400_PA_AC97 + S3C_AC97_MIC_DATA, ++ .dma_size = 4, ++}; ++#else /* Input Stream is LINE-IN */ ++static struct s3c2410_dma_client s3c6400_dma_client_in = { ++ .name = "AC97 PCM Stereo Line in" ++}; ++ ++static struct s3c24xx_pcm_dma_params s3c6400_ac97_pcm_stereo_in = { ++ .client = &s3c6400_dma_client_in, ++ .channel = DMACH_AC97_PCM_IN, ++ .dma_addr = S3C6400_PA_AC97 + S3C_AC97_PCM_DATA, ++ .dma_size = 4, ++}; ++#endif ++ ++static int s3c6400_ac97_probe(struct platform_device *pdev) ++{ ++ int ret; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ s3c24xx_ac97.regs = ioremap(S3C6400_PA_AC97, 0x100); ++ if (s3c24xx_ac97.regs == NULL) ++ return -ENXIO; ++ ++ s3c24xx_ac97.ac97_clk = clk_get(&pdev->dev, "ac97"); ++ if (s3c24xx_ac97.ac97_clk == NULL) { ++ printk(KERN_ERR "s3c6400-ac97 failed to get ac97_clock\n"); ++ iounmap(s3c24xx_ac97.regs); ++ return -ENODEV; ++ } ++ clk_enable(s3c24xx_ac97.ac97_clk); ++ ++ s3c_gpio_cfgpin(S3C64XX_GPD(0),S3C64XX_GPD0_AC97_BITCLK); ++ s3c_gpio_cfgpin(S3C64XX_GPD(1),S3C64XX_GPD1_AC97_nRESET); ++ s3c_gpio_cfgpin(S3C64XX_GPD(2),S3C64XX_GPD2_AC97_SYNC); ++ s3c_gpio_cfgpin(S3C64XX_GPD(3),S3C64XX_GPD3_AC97_SDI); ++ s3c_gpio_cfgpin(S3C64XX_GPD(4),S3C64XX_GPD4_AC97_SDO); ++ ++ s3c_gpio_setpull(S3C64XX_GPD(0),S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S3C64XX_GPD(1),S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S3C64XX_GPD(2),S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S3C64XX_GPD(3),S3C_GPIO_PULL_NONE); ++ s3c_gpio_setpull(S3C64XX_GPD(4),S3C_GPIO_PULL_NONE); ++ ++ ret = request_irq(IRQ_AC97, s3c6400_ac97_irq, ++ IRQF_DISABLED, "AC97", NULL); ++ if (ret < 0) { ++ printk(KERN_ERR "s3c24xx-ac97: interrupt request failed.\n"); ++ clk_disable(s3c24xx_ac97.ac97_clk); ++ clk_put(s3c24xx_ac97.ac97_clk); ++ iounmap(s3c24xx_ac97.regs); ++ } ++ ++ return ret; ++} ++ ++static void s3c6400_ac97_remove(struct platform_device *pdev) ++{ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ free_irq(IRQ_AC97, NULL); ++ clk_disable(s3c24xx_ac97.ac97_clk); ++ clk_put(s3c24xx_ac97.ac97_clk); ++ iounmap(s3c24xx_ac97.regs); ++} ++ ++static int s3c6400_ac97_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ cpu_dai->dma_data = &s3c6400_ac97_pcm_stereo_out; ++ else ++#ifdef CONFIG_SOUND_WM9713_INPUT_STREAM_MIC ++ cpu_dai->dma_data = &s3c6400_ac97_mic_mono_in; ++#else /* Input Stream is LINE-IN */ ++ cpu_dai->dma_data = &s3c6400_ac97_pcm_stereo_in; ++#endif ++ ++ ++ return 0; ++} ++ ++static int s3c6400_ac97_hifi_prepare(struct snd_pcm_substream *substream) ++{ ++ /* ++ * To support full duplex ++ * Tested by cat /dev/dsp > /dev/dsp ++ */ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ s3c6400_ac97_write(0,0x26,0x0); ++ s3c6400_ac97_write(0, 0x0c, 0x0808); ++ s3c6400_ac97_write(0,0x3c, 0xf803); ++ s3c6400_ac97_write(0,0x3e,0xb990); ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ s3c6400_ac97_write(0,0x02, 0x0404); ++ s3c6400_ac97_write(0, 0x04, 0x0606); ++ s3c6400_ac97_write(0,0x1c, 0x12aa); ++ } ++ else ++ { ++ s3c6400_ac97_write(0, 0x12, 0x0f0f); ++#ifdef CONFIG_SOUND_WM9713_INPUT_STREAM_MIC ++ s3c6400_ac97_write(0,0x5c,0x2); ++ s3c6400_ac97_write(0,0x10,0x68); ++ s3c6400_ac97_write(0,0x14,0xfe00); ++#else /* Input Stream is LINE-IN */ ++ s3c6400_ac97_write(0, 0x14, 0xd612); ++#endif ++ } ++ ++ return 0; ++} ++ ++ ++static int s3c6400_ac97_trigger(struct snd_pcm_substream *substream, int cmd) ++{ ++ u32 ac_glbctrl; ++ ++ s3cdbg("Entered %s: cmd = %d\n", __FUNCTION__, cmd); ++ ++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ switch(cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ ++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) ++ ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA; ++ else ++ ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA; ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) ++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK; ++ else ++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK; ++ break; ++ } ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ ++ return 0; ++} ++ ++#if 0 ++static int s3c6400_ac97_hw_mic_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ return -ENODEV; ++ else ++ cpu_dai->dma_data = &s3c6400_ac97_mic_mono_in; ++ ++ return 0; ++} ++ ++static int s3c6400_ac97_mic_trigger(struct snd_pcm_substream *substream, ++ int cmd) ++{ ++ u32 ac_glbctrl; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ switch(cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA; ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK; ++ } ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ ++ return 0; ++} ++#endif ++ ++#define s3c6400_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ ++ SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \ ++ SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) ++ ++struct snd_soc_dai s3c6400_ac97_dai[] = { ++{ ++ .name = "s3c64xx-ac97", ++ .id = 0, ++ .type = SND_SOC_DAI_AC97, ++ .probe = s3c6400_ac97_probe, ++ .remove = s3c6400_ac97_remove, ++ .playback = { ++ .stream_name = "AC97 Playback", ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = s3c6400_AC97_RATES, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE,}, ++ .capture = { ++ .stream_name = "AC97 Capture", ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = s3c6400_AC97_RATES, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE,}, ++ .ops = { ++ .hw_params = s3c6400_ac97_hw_params, ++ .prepare = s3c6400_ac97_hifi_prepare, ++ .trigger = s3c6400_ac97_trigger}, ++}, ++#if 0 ++{ ++ .name = "s3c6400-ac97-mic", ++ .id = 1, ++ .type = SND_SOC_DAI_AC97, ++ .capture = { ++ .stream_name = "AC97 Mic Capture", ++ .channels_min = 1, ++ .channels_max = 1, ++ .rates = s3c6400_AC97_RATES, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE,}, ++ .ops = { ++ .hw_params = s3c6400_ac97_hw_mic_params, ++ .trigger = s3c6400_ac97_mic_trigger,}, ++}, ++#endif ++}; ++ ++EXPORT_SYMBOL_GPL(s3c6400_ac97_dai); ++EXPORT_SYMBOL_GPL(soc_ac97_ops); ++ ++MODULE_AUTHOR("Ryu Euiyoul"); ++MODULE_DESCRIPTION("AC97 driver for the Samsung s3c6400 chip"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s3c64xx/s3c64xx-ac97.h linux-2.6.28.6/sound/soc/s3c64xx/s3c64xx-ac97.h +--- linux-2.6.28/sound/soc/s3c64xx/s3c64xx-ac97.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s3c64xx/s3c64xx-ac97.h 2009-10-20 06:07:45.000000000 +0200 +@@ -0,0 +1,25 @@ ++/* ++ * s3c24xx-ac97.c -- ALSA Soc Audio Layer ++ * ++ * (c) 2007 Wolfson Microelectronics PLC. ++ * Author: Graeme Gregory ++ * graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * Revision history ++ * 10th Nov 2006 Initial version. ++ */ ++ ++#ifndef S3C6400AC97_H_ ++#define S3C6400AC97_H_ ++ ++#define AC_CMD_ADDR(x) (x << 16) ++#define AC_CMD_DATA(x) (x & 0xffff) ++ ++extern struct /*snd_soc_cpu_dai*/snd_soc_dai s3c6400_ac97_dai[]; ++ ++#endif /*S3C6400AC97_H_*/ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s3c64xx/s5p6440-i2s.c linux-2.6.28.6/sound/soc/s3c64xx/s5p6440-i2s.c +--- linux-2.6.28/sound/soc/s3c64xx/s5p6440-i2s.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s3c64xx/s5p6440-i2s.c 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,662 @@ ++/* ++ * s5p6440-i2s.c -- ALSA Soc Audio Layer ++ * ++ * (c) 2009 Samsung Electronics - Jaswinder Singh Brar ++ * Derived from Ben Dooks' driver for s3c24xx ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++//#include ++ ++#include "s3c-pcm.h" ++#include "s5p6440-i2s.h" ++ ++static struct s3c2410_dma_client s5p6440_dma_client_out = { ++ .name = "I2S PCM Stereo out" ++}; ++ ++static struct s3c2410_dma_client s5p6440_dma_client_in = { ++ .name = "I2S PCM Stereo in" ++}; ++ ++static struct s3c24xx_pcm_dma_params s5p6440_i2s_pcm_stereo_out = { ++ .client = &s5p6440_dma_client_out, ++ .channel = DMACH_I2S_V40_OUT, ++ .dma_addr = S5P64XX_PA_IIS_V40 + S5P64XX_IISTXD, ++ .dma_size = 4, ++}; ++ ++static struct s3c24xx_pcm_dma_params s5p6440_i2s_pcm_stereo_in = { ++ .client = &s5p6440_dma_client_in, ++ .channel = DMACH_I2S_V40_IN, ++ .dma_addr = S5P64XX_PA_IIS_V40 + S5P64XX_IISRXD, ++ .dma_size = 4, ++}; ++ ++struct s5p6440_i2s_info { ++ void __iomem *regs; ++ struct clk *iis_clk; ++ struct clk *audio_bus; ++ u32 iiscon; ++ u32 iismod; ++ u32 iisfic; ++ u32 iispsr; ++ u32 slave; ++ u32 clk_rate; ++}; ++static struct s5p6440_i2s_info s5p6440_i2s; ++ ++static void s5p6440_snd_txctrl(int on) ++{ ++ u32 iiscon; ++ ++ iiscon = readl(s5p6440_i2s.regs + S5P64XX_IISCON); ++ ++ if(on){ ++ iiscon |= S5P64XX_IISCON_I2SACTIVE; ++ iiscon &= ~S5P64XX_IISCON_TXCHPAUSE; ++ iiscon &= ~S5P64XX_IISCON_TXDMAPAUSE; ++ iiscon |= S5P64XX_IISCON_TXDMACTIVE; ++ writel(iiscon, s5p6440_i2s.regs + S5P64XX_IISCON); ++ }else{ ++ iiscon &= ~S5P64XX_IISCON_I2SACTIVE; ++ iiscon |= S5P64XX_IISCON_TXCHPAUSE; ++ iiscon |= S5P64XX_IISCON_TXDMAPAUSE; ++ iiscon &= ~S5P64XX_IISCON_TXDMACTIVE; ++ writel(iiscon, s5p6440_i2s.regs + S5P64XX_IISCON); ++ } ++} ++ ++static void s5p6440_snd_rxctrl(int on) ++{ ++ u32 iiscon; ++ ++ iiscon = readl(s5p6440_i2s.regs + S5P64XX_IISCON); ++ ++ if(on){ ++ iiscon |= S5P64XX_IISCON_I2SACTIVE; ++ iiscon &= ~S5P64XX_IISCON_RXCHPAUSE; ++ iiscon &= ~S5P64XX_IISCON_RXDMAPAUSE; ++ iiscon |= S5P64XX_IISCON_RXDMACTIVE; ++ writel(iiscon, s5p6440_i2s.regs + S5P64XX_IISCON); ++ }else{ ++ iiscon &= ~S5P64XX_IISCON_I2SACTIVE; ++ iiscon |= S5P64XX_IISCON_RXCHPAUSE; ++ iiscon |= S5P64XX_IISCON_RXDMAPAUSE; ++ iiscon &= ~S5P64XX_IISCON_RXDMACTIVE; ++ writel(iiscon, s5p6440_i2s.regs + S5P64XX_IISCON); ++ } ++ ++} ++ ++/* ++ * Wait for the LR signal to allow synchronisation to the L/R clock ++ * from the codec. May only be needed for slave mode. ++ */ ++static int s5p6440_snd_lrsync(void) ++{ ++ u32 iiscon; ++ int timeout = 50; /* 5ms */ ++ ++ while (1) { ++ iiscon = readl(s5p6440_i2s.regs + S5P64XX_IISCON); ++ if (iiscon & S5P64XX_IISCON_LRI) ++ break; ++ ++ if (!timeout--) ++ return -ETIMEDOUT; ++ udelay(100); ++ } ++ ++ return 0; ++} ++ ++/* ++ * Set s5p64xx I2S DAI format ++ */ ++static int s5p6440_i2s_set_fmt(struct snd_soc_dai *cpu_dai, ++ unsigned int fmt) ++{ ++ u32 iismod; ++ ++ iismod = readl(s5p6440_i2s.regs + S5P64XX_IISMOD); ++ iismod &= ~S5P64XX_IISMOD_SDFMASK; ++ ++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { ++ case SND_SOC_DAIFMT_CBM_CFM: ++ s5p6440_i2s.slave = 1; ++ break; ++ case SND_SOC_DAIFMT_CBS_CFS: ++ s5p6440_i2s.slave = 0; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { ++ case SND_SOC_DAIFMT_I2S: ++ iismod &= ~S5P64XX_IISMOD_MSB; ++ break; ++ case SND_SOC_DAIFMT_LEFT_J: ++ iismod |= S5P64XX_IISMOD_MSB; ++ break; ++ case SND_SOC_DAIFMT_RIGHT_J: ++ iismod |= S5P64XX_IISMOD_LSB; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { ++ case SND_SOC_DAIFMT_NB_NF: ++ iismod &= ~S5P64XX_IISMOD_LRP; ++ break; ++ case SND_SOC_DAIFMT_NB_IF: ++ iismod |= S5P64XX_IISMOD_LRP; ++ break; ++ case SND_SOC_DAIFMT_IB_IF: ++ case SND_SOC_DAIFMT_IB_NF: ++ default: ++ printk("Inv-combo(%d) not supported!\n", fmt & SND_SOC_DAIFMT_FORMAT_MASK); ++ return -EINVAL; ++ } ++ ++ writel(iismod, s5p6440_i2s.regs + S5P64XX_IISMOD); ++ return 0; ++} ++ ++static int s5p6440_i2s_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ u32 iismod; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ rtd->dai->cpu_dai->dma_data = &s5p6440_i2s_pcm_stereo_out; ++ else ++ rtd->dai->cpu_dai->dma_data = &s5p6440_i2s_pcm_stereo_in; ++ ++ /* Working copies of register */ ++ iismod = readl(s5p6440_i2s.regs + S5P64XX_IISMOD); ++ iismod &= ~S5P64XX_IISMOD_BLCMASK; ++ ++ /* TODO */ ++ switch(params_channels(params)) { ++ case 1: ++ break; ++ case 2: ++ break; ++ case 4: ++ break; ++ case 6: ++ break; ++ default: ++ break; ++ } ++ ++ /* RFS & BFS are set by dai_link(machine specific) code via set_clkdiv */ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S8: ++ iismod |= S5P64XX_IISMOD_8BIT; ++ break; ++ case SNDRV_PCM_FORMAT_S16_LE: ++ iismod |= S5P64XX_IISMOD_16BIT; ++ break; ++ case SNDRV_PCM_FORMAT_S24_LE: ++ iismod |= S5P64XX_IISMOD_24BIT; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ writel(iismod, s5p6440_i2s.regs + S5P64XX_IISMOD); ++ ++ return 0; ++} ++ ++static int s5p6440_i2s_startup(struct snd_pcm_substream *substream) ++{ ++ u32 iiscon, iisfic; ++ ++ iiscon = readl(s5p6440_i2s.regs + S5P64XX_IISCON); ++ ++ /* FIFOs must be flushed before enabling PSR and other MOD bits, so we do it here. */ ++ if(!(iiscon & S5P64XX_IISCON_I2SACTIVE)){ ++ iisfic = readl(s5p6440_i2s.regs + S5P64XX_IISFIC); ++ iisfic |= S5P64XX_IISFIC_TFLUSH | S5P64XX_IISFIC_RFLUSH; ++ writel(iisfic, s5p6440_i2s.regs + S5P64XX_IISFIC); ++ } ++ ++ do{ ++ iiscon = readl(s5p6440_i2s.regs + S5P64XX_IISCON); ++ }while((iiscon & 0x780) != (S5P64XX_IISCON_FRXEMPT | S5P64XX_IISCON_FTX0EMPT)); ++ iisfic = readl(s5p6440_i2s.regs + S5P64XX_IISFIC); ++ iisfic &= ~(S5P64XX_IISFIC_TFLUSH | S5P64XX_IISFIC_RFLUSH); ++ writel(iisfic, s5p6440_i2s.regs + S5P64XX_IISFIC); ++ ++ return 0; ++} ++ ++static int s5p6440_i2s_prepare(struct snd_pcm_substream *substream) ++{ ++ u32 iismod; ++ ++ iismod = readl(s5p6440_i2s.regs + S5P64XX_IISMOD); ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){ ++ if((iismod & S5P64XX_IISMOD_TXRMASK) == S5P64XX_IISMOD_RX){ ++ iismod &= ~S5P64XX_IISMOD_TXRMASK; ++ iismod |= S5P64XX_IISMOD_TXRX; ++ } ++ }else{ ++ if((iismod & S5P64XX_IISMOD_TXRMASK) == S5P64XX_IISMOD_TX){ ++ iismod &= ~S5P64XX_IISMOD_TXRMASK; ++ iismod |= S5P64XX_IISMOD_TXRX; ++ } ++ } ++ ++ writel(iismod, s5p6440_i2s.regs + S5P64XX_IISMOD); ++ ++ return 0; ++} ++ ++static int s5p6440_i2s_trigger(struct snd_pcm_substream *substream, int cmd) ++{ ++ int ret = 0; ++ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ if (s5p6440_i2s.slave) { ++ ret = s5p6440_snd_lrsync(); ++ if (ret) ++ goto exit_err; ++ } ++ ++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) ++ s5p6440_snd_rxctrl(1); ++ else ++ s5p6440_snd_txctrl(1); ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) ++ s5p6440_snd_rxctrl(0); ++ else ++ s5p6440_snd_txctrl(0); ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++exit_err: ++ return ret; ++} ++ ++/* ++ * Set s5p64xx Clock source ++ * Since, we set frequencies using PreScaler and BFS, RFS, we select input clock source to the IIS here. ++ */ ++static int s5p6440_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, ++ int clk_id, unsigned int freq, int dir) ++{ ++ struct clk *clk; ++ u32 iismod = readl(s5p6440_i2s.regs + S5P64XX_IISMOD); ++ ++ switch (clk_id) { ++ case S5P6440_CLKSRC_PCLK: ++ if(s5p6440_i2s.slave) ++ return -EINVAL; ++ iismod &= ~S5P64XX_IISMOD_IMSMASK; ++ iismod |= clk_id; ++ s5p6440_i2s.clk_rate = clk_get_rate(s5p6440_i2s.iis_clk); ++ break; ++ ++#ifdef USE_CLKAUDIO ++ case S5P6440_CLKSRC_CLKAUDIO: ++ if(s5p6440_i2s.slave) ++ return -EINVAL; ++ iismod &= ~S5P64XX_IISMOD_IMSMASK; ++ iismod |= clk_id; ++/* ++8000 x 256 = 2048000 ++ 49152000 mod 2048000 = 0 ++ 32768000 mod 2048000 = 0 ++ 73728000 mod 2048000 = 0 ++ ++11025 x 256 = 2822400 ++ 67738000 mod 2822400 = 400 ++ ++16000 x 256 = 4096000 ++ 49152000 mod 4096000 = 0 ++ 32768000 mod 4096000 = 0 ++ 73728000 mod 4096000 = 0 ++ ++22050 x 256 = 5644800 ++ 67738000 mod 5644800 = 400 ++ ++32000 x 256 = 8192000 ++ 49152000 mod 8192000 = 0 ++ 32768000 mod 8192000 = 0 ++ 73728000 mod 8192000 = 0 ++ ++44100 x 256 = 11289600 ++ 67738000 mod 11289600 = 400 ++ ++48000 x 256 = 12288000 ++ 49152000 mod 12288000 = 0 ++ 73728000 mod 12288000 = 0 ++ ++64000 x 256 = 16384000 ++ 49152000 mod 16384000 = 0 ++ 32768000 mod 16384000 = 0 ++ ++88200 x 256 = 22579200 ++ 67738000 mod 22579200 = 400 ++ ++96000 x 256 = 24576000 ++ 49152000 mod 24576000 = 0 ++ 73728000 mod 24576000 = 0 ++ ++ From the table above, we find that 49152000 gives least(0) residue ++ for most sample rates, followed by 67738000. ++*/ ++ clk = clk_get(NULL, "fout_epll"); ++ if (IS_ERR(clk)) { ++ printk("failed to get FOUTepll\n"); ++ return -EBUSY; ++ } ++ clk_disable(clk); ++ switch (freq) { ++ case 8000: ++ case 16000: ++ case 32000: ++ case 48000: ++ case 64000: ++ case 96000: ++ clk_set_rate(clk, 49152000); ++ break; ++ case 11025: ++ case 22050: ++ case 44100: ++ case 88200: ++ default: ++ clk_set_rate(clk, 67738000); ++ break; ++ } ++ clk_enable(clk); ++ clk_put(clk); ++ s5p6440_i2s.clk_rate = clk_get_rate(s5p6440_i2s.audio_bus); ++ //printk("Setting FOUTepll to %dHz", s5p6440_i2s.clk_rate); ++ break; ++#endif ++ ++ case S5P6440_CLKSRC_SLVPCLK: ++ case S5P6440_CLKSRC_I2SEXT: ++ if(!s5p6440_i2s.slave) ++ return -EINVAL; ++ iismod &= ~S5P64XX_IISMOD_IMSMASK; ++ iismod |= clk_id; ++ break; ++ ++ /* Not sure about these two! */ ++ case S5P6440_CDCLKSRC_INT: ++ iismod &= ~S5P64XX_IISMOD_CDCLKCON; ++ break; ++ ++ case S5P6440_CDCLKSRC_EXT: ++ iismod |= S5P64XX_IISMOD_CDCLKCON; ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ writel(iismod, s5p6440_i2s.regs + S5P64XX_IISMOD); ++ return 0; ++} ++ ++/* ++ * Set s5p64xx Clock dividers ++ * NOTE: NOT all combinations of RFS, BFS and BCL are supported! XXX ++ * Machine specific(dai-link) code must consider that while setting MCLK and BCLK in this function. XXX ++ */ ++/* XXX BLC(bits-per-channel) --> BFS(bit clock shud be >= FS*(Bit-per-channel)*2) XXX */ ++/* XXX BFS --> RFS_VAL(must be a multiple of BFS) XXX */ ++/* XXX RFS_VAL & SRC_CLK --> Prescalar Value(SRC_CLK / RFS_VAL / fs - 1) XXX */ ++static int s5p6440_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai, ++ int div_id, int div) ++{ ++ u32 reg; ++ ++ switch (div_id) { ++ case S5P64XX_DIV_MCLK: ++ reg = readl(s5p6440_i2s.regs + S5P64XX_IISMOD) & ~S5P64XX_IISMOD_RFSMASK; ++ switch(div) { ++ case 256: div = S5P64XX_IISMOD_256FS; break; ++ case 512: div = S5P64XX_IISMOD_512FS; break; ++ case 384: div = S5P64XX_IISMOD_384FS; break; ++ case 768: div = S5P64XX_IISMOD_768FS; break; ++ default: return -EINVAL; ++ } ++ writel(reg | div, s5p6440_i2s.regs + S5P64XX_IISMOD); ++ break; ++ case S5P64XX_DIV_BCLK: ++ reg = readl(s5p6440_i2s.regs + S5P64XX_IISMOD) & ~S5P64XX_IISMOD_BFSMASK; ++ switch(div) { ++ case 16: div = S5P64XX_IISMOD_16FS; break; ++ case 24: div = S5P64XX_IISMOD_24FS; break; ++ case 32: div = S5P64XX_IISMOD_32FS; break; ++ case 48: div = S5P64XX_IISMOD_48FS; break; ++ default: return -EINVAL; ++ } ++ writel(reg | div, s5p6440_i2s.regs + S5P64XX_IISMOD); ++ break; ++ case S5P64XX_DIV_PRESCALER: ++ reg = readl(s5p6440_i2s.regs + S5P64XX_IISPSR) & ~S5P64XX_IISPSR_PSRAEN; ++ writel(reg, s5p6440_i2s.regs + S5P64XX_IISPSR); ++ reg = readl(s5p6440_i2s.regs + S5P64XX_IISPSR) & ~S5P64XX_IISPSR_PSVALA; ++ div &= 0x3f; ++ writel(reg | (div<<8) | S5P64XX_IISPSR_PSRAEN, s5p6440_i2s.regs + S5P64XX_IISPSR); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/* ++ * To avoid duplicating clock code, allow machine driver to ++ * get the clockrate from here. ++ */ ++u32 s5p6440_i2s_get_clockrate(void) ++{ ++ return s5p6440_i2s.clk_rate; ++} ++EXPORT_SYMBOL_GPL(s5p6440_i2s_get_clockrate); ++ ++static irqreturn_t s5p_iis_irq(int irqno, void *dev_id) ++{ ++ u32 iiscon; ++ ++ iiscon = readl(s5p6440_i2s.regs + S5P64XX_IISCON); ++ if(S5P64XX_IISCON_FTXURSTATUS & iiscon) { ++ iiscon &= ~S5P64XX_IISCON_FTXURINTEN; ++ iiscon |= S5P64XX_IISCON_FTXURSTATUS; ++ writel(iiscon, s5p6440_i2s.regs + S5P64XX_IISCON); ++ printk("underrun interrupt IISCON = 0x%08x\n", readl(s5p6440_i2s.regs + S5P64XX_IISCON)); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int s5p6440_i2s_probe(struct platform_device *pdev, ++ struct snd_soc_dai *dai) ++{ ++ int ret = 0; ++ struct clk *cm, *cf; ++ ++ s5p6440_i2s.regs = ioremap(S5P64XX_PA_IIS_V40, 0x100); ++ if (s5p6440_i2s.regs == NULL) ++ return -ENXIO; ++ ++ ret = request_irq(IRQ_IISV40, s5p_iis_irq, 0, "s5p-i2s-v40", pdev); ++ if (ret < 0) { ++ printk("fail to claim i2s irq , ret = %d\n", ret); ++ iounmap(s5p6440_i2s.regs); ++ return -ENODEV; ++ } ++ ++ s5p6440_i2s.iis_clk = clk_get(&pdev->dev, "iis_v40"); ++ if (IS_ERR(s5p6440_i2s.iis_clk)) { ++ printk("failed to get iis_clock\n"); ++ goto lb5; ++ } ++ clk_enable(s5p6440_i2s.iis_clk); ++ s5p6440_i2s.clk_rate = clk_get_rate(s5p6440_i2s.iis_clk); ++ ++#ifdef USE_CLKAUDIO ++ s5p6440_i2s.audio_bus = clk_get(NULL, "audio-bus2"); ++ if (IS_ERR(s5p6440_i2s.audio_bus)) { ++ printk("failed to get audio_bus\n"); ++ goto lb4; ++ } ++ ++ cm = clk_get(NULL, "mout_epll"); ++ if (IS_ERR(cm)) { ++ printk("failed to get MOUTepll\n"); ++ goto lb3; ++ } ++ if(clk_set_parent(s5p6440_i2s.audio_bus, cm)){ ++ printk("failed to set MOUTepll as parent of CLKAUDIO0\n"); ++ goto lb2; ++ } ++ ++ cf = clk_get(NULL, "fout_epll"); ++ if (IS_ERR(cf)) { ++ printk("failed to get FOUTepll\n"); ++ goto lb2; ++ } ++ clk_enable(cf); ++ if(clk_set_parent(cm, cf)){ ++ printk("failed to set FOUTepll as parent of MOUTepll\n"); ++ goto lb1; ++ } ++ s5p6440_i2s.clk_rate = clk_get_rate(s5p6440_i2s.audio_bus); ++ clk_put(cf); ++ clk_put(cm); ++#endif ++ ++ writel(S5P64XX_IISCON_I2SACTIVE, s5p6440_i2s.regs + S5P64XX_IISCON); ++ ++ s5p6440_snd_txctrl(0); ++ s5p6440_snd_rxctrl(0); ++ ++ return 0; ++ ++#ifdef USE_CLKAUDIO ++lb1: ++ clk_put(cf); ++lb2: ++ clk_put(cm); ++lb3: ++ clk_put(s5p6440_i2s.audio_bus); ++lb4: ++ clk_disable(s5p6440_i2s.iis_clk); ++ clk_put(s5p6440_i2s.iis_clk); ++#endif ++lb5: ++ free_irq(IRQ_IISV40, pdev); ++ iounmap(s5p6440_i2s.regs); ++ ++ return -ENODEV; ++} ++ ++#ifdef CONFIG_PM ++static int s5p6440_i2s_suspend(struct platform_device *pdev, ++ struct snd_soc_dai *cpu_dai) ++{ ++ s5p6440_i2s.iiscon = readl(s5p6440_i2s.regs + S5P64XX_IISCON); ++ s5p6440_i2s.iismod = readl(s5p6440_i2s.regs + S5P64XX_IISMOD); ++ s5p6440_i2s.iisfic = readl(s5p6440_i2s.regs + S5P64XX_IISFIC); ++ s5p6440_i2s.iispsr = readl(s5p6440_i2s.regs + S5P64XX_IISPSR); ++ ++ clk_disable(s5p6440_i2s.iis_clk); ++ ++ return 0; ++} ++ ++static int s5p6440_i2s_resume(struct platform_device *pdev, ++ struct snd_soc_dai *cpu_dai) ++{ ++ clk_enable(s5p6440_i2s.iis_clk); ++ ++ writel(s5p6440_i2s.iiscon, s5p6440_i2s.regs + S5P64XX_IISCON); ++ writel(s5p6440_i2s.iismod, s5p6440_i2s.regs + S5P64XX_IISMOD); ++ writel(s5p6440_i2s.iisfic, s5p6440_i2s.regs + S5P64XX_IISFIC); ++ writel(s5p6440_i2s.iispsr, s5p6440_i2s.regs + S5P64XX_IISPSR); ++ ++ return 0; ++} ++#else ++#define s5p6440_i2s_suspend NULL ++#define s5p6440_i2s_resume NULL ++#endif ++ ++ ++struct snd_soc_dai s5p6440_i2s_v40_dai = { ++ .name = "s5p6440-i2s", ++ .id = 0, ++ .type = SND_SOC_DAI_I2S, ++ .probe = s5p6440_i2s_probe, ++ .suspend = s5p6440_i2s_suspend, ++ .resume = s5p6440_i2s_resume, ++ .playback = { ++ .channels_min = 2, ++ .channels_max = 6, ++ .rates = SNDRV_PCM_RATE_8000_96000, ++ .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, ++ }, ++ .capture = { ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_96000, ++ .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, ++ }, ++ .ops = { ++ .hw_params = s5p6440_i2s_hw_params, ++ .prepare = s5p6440_i2s_prepare, ++ .startup = s5p6440_i2s_startup, ++ .trigger = s5p6440_i2s_trigger, ++ }, ++ .dai_ops = { ++ .set_fmt = s5p6440_i2s_set_fmt, ++ .set_clkdiv = s5p6440_i2s_set_clkdiv, ++ .set_sysclk = s5p6440_i2s_set_sysclk, ++ }, ++}; ++EXPORT_SYMBOL_GPL(s5p6440_i2s_v40_dai); ++ ++/* Module information */ ++MODULE_AUTHOR("Jaswinder Singh "); ++MODULE_DESCRIPTION("s5p6440 I2S SoC Interface"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s3c64xx/s5p6440-i2s.h linux-2.6.28.6/sound/soc/s3c64xx/s5p6440-i2s.h +--- linux-2.6.28/sound/soc/s3c64xx/s5p6440-i2s.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s3c64xx/s5p6440-i2s.h 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,43 @@ ++/* ++ * s5p64xx-i2s.c -- ALSA Soc Audio Layer ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#ifndef S5P64XXI2S_H_ ++#define S5P64XXI2S_H_ ++ ++#include ++ ++#ifndef CONFIG_SND_S5P6440_SOC_I2S_V32 ++#define IIS_V40 1 ++#endif ++ ++/* clock sources */ ++#define S5P6440_CLKSRC_PCLK S5P64XX_IISMOD_MSTPCLK ++#define S5P6440_CLKSRC_CLKAUDIO S5P64XX_IISMOD_MSTCLKAUDIO ++#define S5P6440_CLKSRC_SLVPCLK S5P64XX_IISMOD_SLVPCLK ++#define S5P6440_CLKSRC_I2SEXT S5P64XX_IISMOD_SLVI2SCLK ++#define S5P6440_CDCLKSRC_INT (4<<10) ++#define S5P6440_CDCLKSRC_EXT (5<<10) ++ ++/* Clock dividers */ ++#define S5P64XX_DIV_MCLK 0 ++#define S5P64XX_DIV_BCLK 1 ++#define S5P64XX_DIV_PRESCALER 2 ++ ++#define USE_CLKAUDIO 1 ++ ++u32 s5p6440_i2s_get_clockrate(void); ++ ++#ifdef CONFIG_SND_S5P6440_SOC_I2S_V32 ++extern struct snd_soc_dai s5p6440_i2s_v32_dai; ++#else ++extern struct snd_soc_dai s5p6440_i2s_v40_dai; ++#endif ++ ++#endif /*S5P64XXI2S_H_*/ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s3c64xx/smdk6400_wm8753.c linux-2.6.28.6/sound/soc/s3c64xx/smdk6400_wm8753.c +--- linux-2.6.28/sound/soc/s3c64xx/smdk6400_wm8753.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s3c64xx/smdk6400_wm8753.c 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,436 @@ ++/* ++ * smdk6400_wm8753.c -- SoC audio for Neo1973 ++ * ++ * Copyright 2007 Wolfson Microelectronics PLC. ++ * Author: Graeme Gregory ++ * graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com ++ * ++ * Copyright (C) 2007, Ryu Euiyoul ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * Revision history ++ * 20th Jan 2007 Initial version. ++ * 05th Feb 2007 Rename all to Neo1973 ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../codecs/wm8753.h" ++#include "s3c-pcm.h" ++#include "s3c-i2s.h" ++ ++/* define the scenarios */ ++#define SMDK6400_AUDIO_OFF 0 ++#define SMDK6400_CAPTURE_MIC1 3 ++#define SMDK6400_STEREO_TO_HEADPHONES 2 ++#define SMDK6400_CAPTURE_LINE_IN 1 ++ ++#ifdef CONFIG_SND_DEBUG ++#define s3cdbg(x...) printk(x) ++#else ++#define s3cdbg(x...) ++#endif ++ ++static int smdk6400_hifi_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai; ++ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; ++ unsigned int pll_out = 0, bclk = 0; ++ int ret = 0; ++ unsigned int iispsr, iismod; ++ unsigned int prescaler = 4; ++ ++ s3cdbg("Entered %s, rate = %d\n", __FUNCTION__, params_rate(params)); ++ ++ /*PCLK & SCLK gating enable*/ ++ writel(readl(S3C_PCLK_GATE)|S3C_CLKCON_PCLK_IIS0, S3C_PCLK_GATE); ++ writel(readl(S3C_SCLK_GATE)|S3C_CLKCON_SCLK_AUDIO0, S3C_SCLK_GATE); ++ ++ iismod = readl(S3C_IIS0MOD); ++ iismod &=~(0x3<<3); ++ ++ /*Clear I2S prescaler value [13:8] and disable prescaler*/ ++ iispsr = readl(S3C_IIS0PSR); ++ iispsr &=~((0x3f<<8)|(1<<15)); ++ writel(iispsr, S3C_IIS0PSR); ++ ++ s3cdbg("%s: %d , params = %d \n", __FUNCTION__, __LINE__, params_rate(params)); ++ ++ switch (params_rate(params)) { ++ case 16000: ++ case 32000: ++ writel(0, S3C_EPLL_CON1); ++ writel((1<<31)|(128<<16)|(25<<8)|(0<<0) ,S3C_EPLL_CON0); ++ break; ++ //case 8000: ++ // prescaler = 0xe; ++ case 48000: ++ writel(0, S3C_EPLL_CON1); ++ writel((1<<31)|(192<<16)|(25<<8)|(0<<0) ,S3C_EPLL_CON0); ++ break; ++ case 11025: ++ prescaler = 9; ++ case 8000: ++ case 22050: ++ case 44100: ++ writel(0, S3C_EPLL_CON1); ++ writel((1<<31)|(254<<16)|(9<<8)|(2<<0) ,S3C_EPLL_CON0); ++ break; ++ default: ++ /* somtimes 32000 rate comes to 96000 ++ default values are same as 32000 */ ++ writel(0, S3C_EPLL_CON1); ++ writel((1<<31)|(128<<16)|(25<<8)|(0<<0) ,S3C_EPLL_CON0); ++ ++ /* for 96000 rate : error 0.3% ++ * prescaler = 1; ++ * writel((1<<31)|(154<<16)|(25<<8)|(0<<0) ,S3C_EPLL_CON0); ++ */ ++ break; ++ } ++ ++ s3cdbg("%s, IISCON: %x IISMOD: %x,IISFIC: %x,IISPSR: %x", ++ __FUNCTION__ , readl(S3C_IIS0CON), readl(S3C_IIS0MOD), ++ readl(S3C_IIS0FIC), readl(S3C_IIS0PSR)); ++ ++ while(!(__raw_readl(S3C_EPLL_CON0)&(1<<30))); ++ ++ /* MUXepll : FOUTepll */ ++ writel(readl(S3C_CLK_SRC)|S3C_CLKSRC_EPLL_CLKSEL, S3C_CLK_SRC); ++ /* AUDIO0 sel : FOUTepll */ ++ writel((readl(S3C_CLK_SRC)&~(0x7<<7))|(0<<7), S3C_CLK_SRC); ++ ++ /* CLK_DIV2 setting */ ++ writel(0x0,S3C_CLK_DIV2); ++ ++ switch (params_rate(params)) { ++// case 8000: ++// iismod |= S3C_IIS0MOD_768FS; ++// pll_out = 12288000; ++// break; ++ case 11025: ++ iismod |= S3C_IIS0MOD_768FS; ++ bclk = WM8753_BCLK_DIV_16; ++ pll_out = 16934400; ++ break; ++ case 16000: ++ iismod |= S3C_IIS0MOD_768FS; ++ bclk = WM8753_BCLK_DIV_2; ++ pll_out = 12288000; ++ break; ++ case 22050: ++ iismod |= S3C_IIS0MOD_768FS; ++ bclk = WM8753_BCLK_DIV_8; ++ pll_out = 16934400; ++ break; ++ case 32000: ++ iismod |= S3C_IIS0MOD_384FS; ++ bclk = WM8753_BCLK_DIV_2; ++ pll_out = 12288000; ++ break; ++ case 44100: ++ case 8000: ++ iismod |= S3C_IIS0MOD_384FS; ++ bclk = WM8753_BCLK_DIV_4; ++ pll_out = 16934400; ++ break; ++ case 48000: ++ iismod |= S3C_IIS0MOD_384FS; ++ bclk = WM8753_BCLK_DIV_4; ++ pll_out = 18432000; ++ break; ++ default: ++ /* somtimes 32000 rate comes to 96000 ++ default values are same as 32000 */ ++ iismod |= S3C_IIS0MOD_384FS; ++ bclk = WM8753_BCLK_DIV_2; ++ pll_out = 12288000; ++ break; ++ } ++ ++ writel(iismod , S3C_IIS0MOD); ++ ++ /* set codec DAI configuration */ ++ ret = codec_dai->dai_ops.set_fmt(codec_dai, ++ SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBS_CFS ); ++ if (ret < 0) ++ return ret; ++ ++ /* set cpu DAI configuration */ ++ ret = cpu_dai->dai_ops.set_fmt(cpu_dai, ++ SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBS_CFS ); ++ if (ret < 0) ++ return ret; ++ ++ /* set the codec system clock for DAC and ADC */ ++ ret = codec_dai->dai_ops.set_sysclk(codec_dai, WM8753_MCLK, pll_out, ++ SND_SOC_CLOCK_IN); ++ if (ret < 0) ++ return ret; ++ ++ /* set MCLK division for sample rate */ ++ ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_MCLK, ++ S3C2410_IISMOD_32FS ); ++ if (ret < 0) ++ return ret; ++ ++ /* set codec BCLK division for sample rate */ ++ ret = codec_dai->dai_ops.set_clkdiv(codec_dai, WM8753_BCLKDIV, bclk); ++ if (ret < 0) ++ return ret; ++ ++ /* set prescaler division for sample rate */ ++ ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER, ++ (prescaler << 0x8)); ++ if (ret < 0) ++ return ret; ++ ++ return 0; ++} ++ ++static int smdk6400_hifi_hw_free(struct snd_pcm_substream *substream) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai; ++ ++ /* disable the PLL */ ++ return codec_dai->dai_ops.set_pll(codec_dai, WM8753_PLL1, 0, 0); ++} ++ ++/* ++ * Neo1973 WM8753 HiFi DAI opserations. ++ */ ++static struct snd_soc_ops smdk6400_hifi_ops = { ++ .hw_params = smdk6400_hifi_hw_params, ++ .hw_free = smdk6400_hifi_hw_free, ++}; ++ ++static int smdk6400_scenario = 0; ++ ++static int smdk6400_get_scenario(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ ucontrol->value.integer.value[0] = smdk6400_scenario; ++ return 0; ++} ++ ++static int set_scenario_endpoints(struct snd_soc_codec *codec, int scenario) ++{ ++ switch(smdk6400_scenario) { ++ case SMDK6400_AUDIO_OFF: ++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 0); ++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 0); ++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 0); ++ break; ++ case SMDK6400_STEREO_TO_HEADPHONES: ++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1); ++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 0); ++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 0); ++ break; ++ case SMDK6400_CAPTURE_MIC1: ++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 0); ++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 1); ++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 0); ++ break; ++ case SMDK6400_CAPTURE_LINE_IN: ++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 0); ++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 0); ++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 1); ++ break; ++ default: ++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1); ++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 1); ++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 1); ++ break; ++ } ++ ++ snd_soc_dapm_sync_endpoints(codec); ++ ++ return 0; ++} ++ ++static int smdk6400_set_scenario(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); ++ ++ if (smdk6400_scenario == ucontrol->value.integer.value[0]) ++ return 0; ++ ++ smdk6400_scenario = ucontrol->value.integer.value[0]; ++ set_scenario_endpoints(codec, smdk6400_scenario); ++ return 1; ++} ++ ++static const struct snd_soc_dapm_widget wm8753_dapm_widgets[] = { ++ SND_SOC_DAPM_HP("Headphone Jack", NULL), ++ SND_SOC_DAPM_MIC("Mic1 Jack", NULL), ++ SND_SOC_DAPM_LINE("Line In Jack", NULL), ++}; ++ ++ ++/* example machine audio_mapnections */ ++static const char* audio_map[][3] = { ++ ++ {"Headphone Jack", NULL, "LOUT1"}, ++ {"Headphone Jack", NULL, "ROUT1"}, ++ ++ /* mic is connected to mic1 - with bias */ ++ /* mic is connected to mic1 - with bias */ ++ {"MIC1", NULL, "Mic1 Jack"}, ++ ++ {"LINE1", NULL, "Line In Jack"}, ++ {"LINE2", NULL, "Line In Jack"}, ++ ++ /* Connect the ALC pins */ ++ {"ACIN", NULL, "ACOP"}, ++ ++ {NULL, NULL, NULL}, ++}; ++ ++static const char *smdk_scenarios[] = { ++ "Off", ++ "Capture Line In", ++ "Headphones", ++ "Capture Mic1", ++}; ++ ++static const struct soc_enum smdk_scenario_enum[] = { ++ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(smdk_scenarios),smdk_scenarios), ++}; ++ ++static const struct snd_kcontrol_new wm8753_smdk6400_controls[] = { ++ SOC_ENUM_EXT("SMDK Mode", smdk_scenario_enum[0], ++ smdk6400_get_scenario, smdk6400_set_scenario), ++}; ++ ++/* ++ * This is an example machine initialisation for a wm8753 connected to a ++ * smdk6400. It is missing logic to detect hp/mic insertions and logic ++ * to re-route the audio in such an event. ++ */ ++static int smdk6400_wm8753_init(struct snd_soc_codec *codec) ++{ ++ int i, err; ++ ++ /* set endpoints to default mode */ ++ set_scenario_endpoints(codec, SMDK6400_AUDIO_OFF); ++ ++ /* Add smdk6400 specific widgets */ ++ for (i = 0; i < ARRAY_SIZE(wm8753_dapm_widgets); i++) ++ snd_soc_dapm_new_control(codec, &wm8753_dapm_widgets[i]); ++ ++ /* add smdk6400 specific controls */ ++ for (i = 0; i < ARRAY_SIZE(wm8753_smdk6400_controls); i++) { ++ err = snd_ctl_add(codec->card, ++ snd_soc_cnew(&wm8753_smdk6400_controls[i], ++ codec, NULL)); ++ if (err < 0) ++ return err; ++ } ++ ++ /* set up smdk6400 specific audio path audio_mapnects */ ++ for (i = 0; audio_map[i][0] != NULL; i++) { ++ snd_soc_dapm_connect_input(codec, audio_map[i][0], ++ audio_map[i][1], audio_map[i][2]); ++ } ++ ++ /* always connected */ ++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 1); ++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1); ++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 1); ++ ++ snd_soc_dapm_sync_endpoints(codec); ++ return 0; ++} ++ ++static struct snd_soc_dai_link smdk6400_dai[] = { ++{ /* Hifi Playback - for similatious use with voice below */ ++ .name = "WM8753", ++ .stream_name = "WM8753 HiFi", ++ .cpu_dai = &s3c_i2s_dai, ++ .codec_dai = &wm8753_dai[WM8753_DAI_HIFI], ++ .init = smdk6400_wm8753_init, ++ .ops = &smdk6400_hifi_ops, ++}, ++}; ++ ++static struct snd_soc_machine smdk6400 = { ++ .name = "smdk6400", ++ .dai_link = smdk6400_dai, ++ .num_links = ARRAY_SIZE(smdk6400_dai), ++}; ++ ++static struct wm8753_setup_data smdk6400_wm8753_setup = { ++ .i2c_address = 0x1a, ++}; ++ ++static struct snd_soc_device smdk6400_snd_devdata = { ++ .machine = &smdk6400, ++ .platform = &s3c24xx_soc_platform, ++ .codec_dev = &soc_codec_dev_wm8753, ++ .codec_data = &smdk6400_wm8753_setup, ++}; ++ ++static struct platform_device *smdk6400_snd_device; ++ ++static int __init smdk6400_init(void) ++{ ++ int ret; ++ ++ smdk6400_snd_device = platform_device_alloc("soc-audio", -1); ++ if (!smdk6400_snd_device) ++ return -ENOMEM; ++ ++ platform_set_drvdata(smdk6400_snd_device, &smdk6400_snd_devdata); ++ smdk6400_snd_devdata.dev = &smdk6400_snd_device->dev; ++ ret = platform_device_add(smdk6400_snd_device); ++ ++ if (ret) ++ platform_device_put(smdk6400_snd_device); ++ ++ return ret; ++} ++ ++static void __exit smdk6400_exit(void) ++{ ++ platform_device_unregister(smdk6400_snd_device); ++} ++ ++module_init(smdk6400_init); ++module_exit(smdk6400_exit); ++ ++/* Module information */ ++MODULE_AUTHOR("Ryu Euiyoul"); ++MODULE_DESCRIPTION("ALSA SoC WM8753 Neo1973"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s3c64xx/smdk6410_s5m8751.c linux-2.6.28.6/sound/soc/s3c64xx/smdk6410_s5m8751.c +--- linux-2.6.28/sound/soc/s3c64xx/smdk6410_s5m8751.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s3c64xx/smdk6410_s5m8751.c 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,273 @@ ++/* ++ * smdk6400_s5m8751.c ++ * ++ * Copyright (C) 2009, Samsung Elect. Ltd. - Jaswinder Singh ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "../codecs/s5m8751.h" ++#include "s3c-pcm.h" ++ ++#include "s3c6410-i2s.h" ++ ++#define SRC_CLK s3c6410_i2s_get_clockrate() ++ ++/* XXX BLC(bits-per-channel) --> BFS(bit clock shud be >= FS*(Bit-per-channel)*2) XXX */ ++/* XXX BFS --> RFS(must be a multiple of BFS) XXX */ ++/* XXX RFS & SRC_CLK --> Prescalar Value(SRC_CLK / RFS_VAL / fs - 1) XXX */ ++static int smdk6410_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; ++ struct snd_soc_dai *codec_dai = rtd->dai->codec_dai; ++ int bfs, rfs, psr, ret; ++ ++ /* Choose BFS and RFS values combination that is supported by ++ * both the S5M8751 codec as well as the S5P6410 AP ++ * ++ * S5M8751 codec supports only S16_LE, S18_3LE, S20_3LE & S24_LE. ++ * S5P6410 AP supports only S8, S16_LE & S24_LE. ++ * We implement all for completeness but only S16_LE & S24_LE bit-lengths ++ * are possible for this AP-Codec combination. ++ */ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S8: ++ bfs = 16; ++ rfs = 256; /* Can take any RFS value for AP */ ++ break; ++ case SNDRV_PCM_FORMAT_S16_LE: ++ bfs = 32; ++ rfs = 256; /* Can take any RFS value for AP */ ++ break; ++ case SNDRV_PCM_FORMAT_S18_3LE: ++ case SNDRV_PCM_FORMAT_S20_3LE: ++ case SNDRV_PCM_FORMAT_S24_LE: ++ bfs = 48; ++ rfs = 512; /* B'coz 48-BFS needs atleast 512-RFS acc to *S5P6440* UserManual */ ++ /* And S5P6440 uses the same I2S IP as S3C6410 */ ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ /* Select the AP Sysclk */ ++ ret = snd_soc_dai_set_sysclk(cpu_dai, S3C6410_CDCLKSRC_INT, params_rate(params), SND_SOC_CLOCK_OUT); ++ if (ret < 0) ++ return ret; ++ ++#ifdef USE_CLKAUDIO ++ ret = snd_soc_dai_set_sysclk(cpu_dai, S3C6410_CLKSRC_CLKAUDIO, params_rate(params), SND_SOC_CLOCK_OUT); ++#else ++ ret = snd_soc_dai_set_sysclk(cpu_dai, S3C6410_CLKSRC_PCLK, 0, SND_SOC_CLOCK_OUT); ++#endif ++ if (ret < 0) ++ return ret; ++ ++ /* Set the AP DAI configuration */ ++ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); ++ if (ret < 0) ++ return ret; ++ ++ /* Set the AP RFS */ ++ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C64XX_DIV_MCLK, rfs); ++ if (ret < 0) ++ return ret; ++ ++ /* Set the AP BFS */ ++ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C64XX_DIV_BCLK, bfs); ++ if (ret < 0) ++ return ret; ++ ++ switch (params_rate(params)) { ++ case 8000: ++ case 11025: ++ case 16000: ++ case 22050: ++ case 32000: ++ case 44100: ++ case 48000: ++ case 64000: ++ case 88200: ++ case 96000: ++ psr = SRC_CLK / rfs / params_rate(params); ++ ret = SRC_CLK / rfs - psr * params_rate(params); ++ if(ret >= params_rate(params)/2) // round off ++ psr += 1; ++ psr -= 1; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ //printk("SRC_CLK=%d PSR=%d RFS=%d BFS=%d\n", SRC_CLK, psr, rfs, bfs); ++ ++ /* Set the AP Prescalar */ ++ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C64XX_DIV_PRESCALER, psr); ++ if (ret < 0) ++ return ret; ++ ++ /* Set the Codec DAI configuration */ ++ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); ++ if (ret < 0) ++ return ret; ++ ++ /* Set the Codec BCLK(no option to set the MCLK) */ ++ ret = snd_soc_dai_set_clkdiv(codec_dai, S5M8751_BCLK, bfs); ++ if (ret < 0) ++ return ret; ++ ++ return 0; ++} ++ ++/* ++ * S5M8751 DAI operations. ++ */ ++static struct snd_soc_ops smdk6410_ops = { ++ .hw_params = smdk6410_hw_params, ++}; ++ ++static const struct snd_soc_dapm_widget s5m8751_dapm_widgets[] = { ++ SND_SOC_DAPM_LINE("I2S Front Jack", NULL), ++ SND_SOC_DAPM_LINE("I2S Center Jack", NULL), ++ SND_SOC_DAPM_LINE("I2S Rear Jack", NULL), ++ SND_SOC_DAPM_LINE("Line In Jack", NULL), ++}; ++ ++/* example machine audio_mapnections */ ++static const struct snd_soc_dapm_route audio_map[] = { ++ ++ { "I2S Front Jack", NULL, "VOUT1L" }, ++ { "I2S Front Jack", NULL, "VOUT1R" }, ++ ++ { "I2S Center Jack", NULL, "VOUT2L" }, ++ { "I2S Center Jack", NULL, "VOUT2R" }, ++ ++ { "I2S Rear Jack", NULL, "VOUT3L" }, ++ { "I2S Rear Jack", NULL, "VOUT3R" }, ++ ++ { "AINL", NULL, "Line In Jack" }, ++ { "AINR", NULL, "Line In Jack" }, ++ ++}; ++ ++static int smdk6410_s5m8751_init(struct snd_soc_codec *codec) ++{ ++ int i; ++ ++ /* Add smdk6410 specific widgets */ ++ snd_soc_dapm_new_controls(codec, s5m8751_dapm_widgets,ARRAY_SIZE(s5m8751_dapm_widgets)); ++ ++ /* set up smdk6410 specific audio paths */ ++ snd_soc_dapm_add_routes(codec, audio_map,ARRAY_SIZE(audio_map)); ++ ++ /* No jack detect - mark all jacks as enabled */ ++ for (i = 0; i < ARRAY_SIZE(s5m8751_dapm_widgets); i++) ++ snd_soc_dapm_set_endpoint(codec, ++ s5m8751_dapm_widgets[i].name, 1); ++ ++ snd_soc_dapm_sync_endpoints(codec); ++ ++ return 0; ++} ++ ++static struct snd_soc_dai_link smdk6410_dai[] = { ++{ ++ .name = "S5M8751", ++ .stream_name = "S5M8751 Playback", ++ .cpu_dai = &s3c6410_i2s_v32_dai, ++ .codec_dai = &s5m8751_dai, ++ .init = smdk6410_s5m8751_init, ++ .ops = &smdk6410_ops, ++}, ++}; ++ ++static struct snd_soc_machine smdk6410 = { ++ .name = "smdk6410", ++ .dai_link = smdk6410_dai, ++ .num_links = ARRAY_SIZE(smdk6410_dai), ++}; ++ ++static struct s5m8751_setup_data smdk6410_s5m8751_setup = { ++ .i2c_address = 0x68, ++}; ++ ++static struct snd_soc_device smdk6410_snd_devdata = { ++ .machine = &smdk6410, ++ .platform = &s3c24xx_soc_platform, ++ .codec_dev = &soc_codec_dev_s5m8751, ++ .codec_data = &smdk6410_s5m8751_setup, ++}; ++ ++static struct platform_device *smdk6410_snd_device; ++ ++static int __init smdk6410_audio_init(void) ++{ ++ int ret; ++ u32 val; ++ ++ /* Configure the GPD pins in I2S and Pull-Up mode */ ++ val = __raw_readl(S3C64XX_GPDPUD); ++ val &= ~((3<<0) | (3<<2) | (3<<4) | (3<<6) | (3<<8)); ++ val |= (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8); ++ __raw_writel(val, S3C64XX_GPDPUD); ++ ++ val = __raw_readl(S3C64XX_GPDCON); ++ val &= ~((0xf<<0) | (0xf<<4) | (0xf<<8) | (0xf<<12) | (0xf<<16)); ++ val |= (3<<0) | (3<<4) | (3<<8) | (3<<12) | (3<<16); ++ __raw_writel(val, S3C64XX_GPDCON); ++ ++ smdk6410_snd_device = platform_device_alloc("soc-audio", 0); ++ if (!smdk6410_snd_device) ++ return -ENOMEM; ++ ++ platform_set_drvdata(smdk6410_snd_device, &smdk6410_snd_devdata); ++ smdk6410_snd_devdata.dev = &smdk6410_snd_device->dev; ++ ret = platform_device_add(smdk6410_snd_device); ++ ++ if (ret) ++ platform_device_put(smdk6410_snd_device); ++ ++ return ret; ++} ++ ++static void __exit smdk6410_audio_exit(void) ++{ ++ platform_device_unregister(smdk6410_snd_device); ++} ++ ++module_init(smdk6410_audio_init); ++module_exit(smdk6410_audio_exit); ++ ++/* Module information */ ++MODULE_DESCRIPTION("ALSA SoC SMDK6410 S5M8751"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s3c64xx/smdk6410_wm8580.c linux-2.6.28.6/sound/soc/s3c64xx/smdk6410_wm8580.c +--- linux-2.6.28/sound/soc/s3c64xx/smdk6410_wm8580.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s3c64xx/smdk6410_wm8580.c 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,310 @@ ++/* ++ * smdk6400_wm8580.c ++ * ++ * Copyright (C) 2009, Samsung Elect. Ltd. - Jaswinder Singh ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++//#define USE_GPR ++ ++#include ++#ifdef USE_GPR ++#include ++#else ++#include ++#include ++#endif ++ ++#include "../codecs/wm8580.h" ++#include "s3c-pcm.h" ++ ++#include "s3c6410-i2s.h" ++ ++#define SRC_CLK s3c6410_i2s_get_clockrate() ++ ++/* XXX BLC(bits-per-channel) --> BFS(bit clock shud be >= FS*(Bit-per-channel)*2) XXX */ ++/* XXX BFS --> RFS(must be a multiple of BFS) XXX */ ++/* XXX RFS & SRC_CLK --> Prescalar Value(SRC_CLK / RFS_VAL / fs - 1) XXX */ ++static int smdk6410_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; ++ struct snd_soc_dai *codec_dai = rtd->dai->codec_dai; ++ int bfs, rfs, psr, ret; ++ ++ /* Choose BFS and RFS values combination that is supported by ++ * both the WM8580 codec as well as the S3C6410 AP ++ * ++ * WM8580 codec supports only S16_LE, S20_3LE, S24_LE & S32_LE. ++ * S3C6410 AP supports only S8, S16_LE & S24_LE. ++ * We implement all for completeness but only S16_LE & S24_LE bit-lengths ++ * are possible for this AP-Codec combination. ++ */ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S8: ++ bfs = 16; ++ rfs = 256; /* Can take any RFS value for AP */ ++ break; ++ case SNDRV_PCM_FORMAT_S16_LE: ++ bfs = 32; ++ rfs = 256; /* Can take any RFS value for AP */ ++ break; ++ case SNDRV_PCM_FORMAT_S20_3LE: ++ case SNDRV_PCM_FORMAT_S24_LE: ++ bfs = 48; ++ rfs = 512; /* B'coz 48-BFS needs atleast 512-RFS acc to *S5P6440* UserManual */ ++ /* And S5P6440 uses the same I2S IP as S3C6410 */ ++ break; ++ case SNDRV_PCM_FORMAT_S32_LE: /* Impossible, as the AP doesn't support 64fs or more BFS */ ++ default: ++ return -EINVAL; ++ } ++ ++ /* Select the AP Sysclk */ ++ ret = snd_soc_dai_set_sysclk(cpu_dai, S3C6410_CDCLKSRC_INT, params_rate(params), SND_SOC_CLOCK_OUT); ++ if (ret < 0) ++ return ret; ++ ++#ifdef USE_CLKAUDIO ++ ret = snd_soc_dai_set_sysclk(cpu_dai, S3C6410_CLKSRC_CLKAUDIO, params_rate(params), SND_SOC_CLOCK_OUT); ++#else ++ ret = snd_soc_dai_set_sysclk(cpu_dai, S3C6410_CLKSRC_PCLK, 0, SND_SOC_CLOCK_OUT); ++#endif ++ if (ret < 0) ++ return ret; ++ ++ /* Set the AP DAI configuration */ ++ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); ++ if (ret < 0) ++ return ret; ++ ++ /* Set the AP RFS */ ++ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C64XX_DIV_MCLK, rfs); ++ if (ret < 0) ++ return ret; ++ ++ /* Set the AP BFS */ ++ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C64XX_DIV_BCLK, bfs); ++ if (ret < 0) ++ return ret; ++ ++ switch (params_rate(params)) { ++ case 8000: ++ case 11025: ++ case 16000: ++ case 22050: ++ case 32000: ++ case 44100: ++ case 48000: ++ case 64000: ++ case 88200: ++ case 96000: ++ psr = SRC_CLK / rfs / params_rate(params); ++ ret = SRC_CLK / rfs - psr * params_rate(params); ++ if(ret >= params_rate(params)/2) // round off ++ psr += 1; ++ psr -= 1; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ //printk("SRC_CLK=%d PSR=%d RFS=%d BFS=%d\n", SRC_CLK, psr, rfs, bfs); ++ ++ /* Set the AP Prescalar */ ++ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C64XX_DIV_PRESCALER, psr); ++ if (ret < 0) ++ return ret; ++ ++ /* Set the Codec DAI configuration */ ++ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); ++ if (ret < 0) ++ return ret; ++ ++ /* Set the Codec BCLK(no option to set the MCLK) */ ++ /* See page 2 and 53 of Wm8580 Manual */ ++ ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_MCLK, WM8580_CLKSRC_MCLK); /* Use MCLK provided by CPU i/f */ ++ if (ret < 0) ++ return ret; ++ ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_DAC_CLKSEL, WM8580_CLKSRC_MCLK); /* Fig-26 Pg-43 */ ++ if (ret < 0) ++ return ret; ++ ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_CLKOUTSRC, WM8580_CLKSRC_NONE); /* Pg-58 */ ++ if (ret < 0) ++ return ret; ++ ++ return 0; ++} ++ ++/* ++ * WM8580 DAI operations. ++ */ ++static struct snd_soc_ops smdk6410_ops = { ++ .hw_params = smdk6410_hw_params, ++}; ++ ++static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = { ++ SND_SOC_DAPM_LINE("I2S Front Jack", NULL), ++ SND_SOC_DAPM_LINE("I2S Center Jack", NULL), ++ SND_SOC_DAPM_LINE("I2S Rear Jack", NULL), ++ SND_SOC_DAPM_LINE("Line In Jack", NULL), ++}; ++ ++/* example machine audio_mapnections */ ++static const struct snd_soc_dapm_route audio_map[] = { ++ ++ { "I2S Front Jack", NULL, "VOUT1L" }, ++ { "I2S Front Jack", NULL, "VOUT1R" }, ++ ++ { "I2S Center Jack", NULL, "VOUT2L" }, ++ { "I2S Center Jack", NULL, "VOUT2R" }, ++ ++ { "I2S Rear Jack", NULL, "VOUT3L" }, ++ { "I2S Rear Jack", NULL, "VOUT3R" }, ++ ++ { "AINL", NULL, "Line In Jack" }, ++ { "AINR", NULL, "Line In Jack" }, ++ ++}; ++ ++static int smdk6410_wm8580_init(struct snd_soc_codec *codec) ++{ ++ int i; ++ ++ /* Add smdk6410 specific widgets */ ++ snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets,ARRAY_SIZE(wm8580_dapm_widgets)); ++ ++ /* set up smdk6410 specific audio paths */ ++ snd_soc_dapm_add_routes(codec, audio_map,ARRAY_SIZE(audio_map)); ++ ++ /* No jack detect - mark all jacks as enabled */ ++ for (i = 0; i < ARRAY_SIZE(wm8580_dapm_widgets); i++) ++ snd_soc_dapm_set_endpoint(codec, ++ wm8580_dapm_widgets[i].name, 1); ++ ++ snd_soc_dapm_sync_endpoints(codec); ++ ++ return 0; ++} ++ ++static struct snd_soc_dai_link smdk6410_dai[] = { ++{ ++ .name = "WM8580", ++ .stream_name = "WM8580 HiFi Playback", ++ .cpu_dai = &s3c6410_i2s_v40_dai, ++ .codec_dai = &wm8580_dai[WM8580_DAI_PAIFRX], ++ .init = smdk6410_wm8580_init, ++ .ops = &smdk6410_ops, ++}, ++}; ++ ++static struct snd_soc_machine smdk6410 = { ++ .name = "smdk6410", ++ .dai_link = smdk6410_dai, ++ .num_links = ARRAY_SIZE(smdk6410_dai), ++}; ++ ++static struct wm8580_setup_data smdk6410_wm8580_setup = { ++ .i2c_address = 0x1b, ++}; ++ ++static struct snd_soc_device smdk6410_snd_devdata = { ++ .machine = &smdk6410, ++ .platform = &s3c24xx_soc_platform, ++ .codec_dev = &soc_codec_dev_wm8580, ++ .codec_data = &smdk6410_wm8580_setup, ++}; ++ ++static struct platform_device *smdk6410_snd_device; ++ ++static int __init smdk6410_audio_init(void) ++{ ++ int ret; ++ u32 val; ++ ++#ifdef USE_GPR ++ val = __raw_readl(S3C64XX_GPRPUD); ++ val &= ~((3<<8) | (3<<10) | (3<<14) | (3<<16) | (3<<18) | (3<<28) | (3<<30)); ++ val |= ((0<<8) | (0<<10) | (0<<14) | (0<<16) | (0<<18) | (0<<28) | (1<<30)); ++ __raw_writel(val, S3C64XX_GPRPUD); ++ ++ val = __raw_readl(S3C64XX_GPRCON0); ++ val &= ~((0xf<<16) | (0xf<<20) | (0xf<<28)); ++ val |= (5<<16) | (5<<20) | (5<<28); ++ __raw_writel(val, S3C64XX_GPRCON0); ++ ++ val = __raw_readl(S3C64XX_GPRCON1); ++ val &= ~((0xf<<0) | (0xf<<4) | (0xf<<24) | (0xf<<28)); ++ val |= (5<<0) | (5<<4) | (5<<24) | (5<<28); ++ __raw_writel(val, S3C64XX_GPRCON1); ++ ++#else ++ val = __raw_readl(S3C64XX_GPCPUD); ++ val &= ~((3<<8) | (3<<10) | (3<<14)); ++ val |= ((0<<8) | (0<<10) | (0<<14)); ++ __raw_writel(val, S3C64XX_GPCPUD); ++ ++ val = __raw_readl(S3C64XX_GPCCON); ++ val &= ~((0xf<<16) | (0xf<<20) | (0xf<<28)); ++ val |= (5<<16) | (5<<20) | (5<<28); ++ __raw_writel(val, S3C64XX_GPCCON); ++ ++ val = __raw_readl(S3C64XX_GPHPUD); ++ val &= ~((3<<12) | (3<<14) | (3<<16) | (3<<18)); ++ val |= ((0<<12) | (1<<14) | (0<<16) | (0<18)); ++ __raw_writel(val, S3C64XX_GPHPUD); ++ ++ val = __raw_readl(S3C64XX_GPHCON0); ++ val &= ~((0xf<<24) | (0xf<<28)); ++ val |= (5<<24) | (5<<28); ++ __raw_writel(val, S3C64XX_GPHCON0); ++ ++ val = __raw_readl(S3C64XX_GPHCON1); ++ val &= ~((0xf<<0) | (0xf<<4)); ++ val |= (5<<0) | (5<<4); ++ __raw_writel(val, S3C64XX_GPHCON1); ++#endif ++ ++ smdk6410_snd_device = platform_device_alloc("soc-audio", 0); ++ if (!smdk6410_snd_device) ++ return -ENOMEM; ++ ++ platform_set_drvdata(smdk6410_snd_device, &smdk6410_snd_devdata); ++ smdk6410_snd_devdata.dev = &smdk6410_snd_device->dev; ++ ret = platform_device_add(smdk6410_snd_device); ++ ++ if (ret) ++ platform_device_put(smdk6410_snd_device); ++ ++ return ret; ++} ++ ++static void __exit smdk6410_audio_exit(void) ++{ ++ platform_device_unregister(smdk6410_snd_device); ++} ++ ++module_init(smdk6410_audio_init); ++module_exit(smdk6410_audio_exit); ++ ++/* Module information */ ++MODULE_DESCRIPTION("ALSA SoC SMDK6410 WM8580"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s3c64xx/smdk6410_wm8990.c linux-2.6.28.6/sound/soc/s3c64xx/smdk6410_wm8990.c +--- linux-2.6.28/sound/soc/s3c64xx/smdk6410_wm8990.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s3c64xx/smdk6410_wm8990.c 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,432 @@ ++/* ++* smdk6410_wm8990.c -- SoC audio for SMDK6410 with WM8990 ++ * ++ * Copyright 2007, 2008 Wolfson Microelectronics PLC. ++ * Author: Liam Girdwood ++ * lg@opensource.wolfsonmicro.com or linux@wolfsonmicro.com ++ * ++ * Copyright (C) 2007, Ryu Euiyoul ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * Revision history ++ * 28th Feb 2008 Initial version. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++//#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "../codecs/wm8990.h" ++#include "s3c-pcm.h" ++#include "s3c-i2s.h" ++ ++/* define the scenarios */ ++#define SMDK6410_AUDIO_OFF 0 ++#define SMDK6410_CAPTURE_MIC1 3 ++#define SMDK6410_STEREO_TO_HEADPHONES 2 ++#define SMDK6410_CAPTURE_LINE_IN 1 ++ ++#ifdef CONFIG_SND_DEBUG ++#define s3cdbg(x...) printk(x) ++#else ++#define s3cdbg(x...) ++#endif ++ ++/* ++ * TODO: - We need to work out PLL values for 256FS for every rate. ++ */ ++static int smdk6410_hifi_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *codec_dai = rtd->dai->codec_dai; ++ struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; ++ unsigned int pll_out = 0;//, bclk = 0; ++ int ret = 0; ++ unsigned int iispsr, iismod; ++ unsigned int prescaler = 4; ++ ++ u32* regs; ++ regs = ioremap(S3C64XX_PA_IIS, 0x100); ++ ++ s3cdbg("Entered %s, rate = %d\n", __FUNCTION__, params_rate(params)); ++ ++ /*PCLK & SCLK gating enable*/ ++ writel(readl(S3C_PCLK_GATE)|S3C_CLKCON_PCLK_IIS0, S3C_PCLK_GATE); ++ writel(readl(S3C_SCLK_GATE)|S3C_CLKCON_SCLK_AUDIO0, S3C_SCLK_GATE); ++ ++ iismod = readl(regs + S3C64XX_IIS0MOD); ++ iismod &= ~S3C64XX_IIS0MOD_FS_MASK; ++ iismod &= ~S3C64XX_IIS0MOD_BFS_MASK; ++ ++ /*Clear I2S prescaler value [13:8] and disable prescaler*/ ++ iispsr = readl(regs + S3C64XX_IIS0PSR); ++ iispsr &=~((0x3f<<8)|(1<<15)); ++ writel(iispsr, regs + S3C64XX_IIS0PSR); ++ ++ s3cdbg("%s: %d , params = %d\n", __FUNCTION__, __LINE__, params_rate(params)); ++ ++ switch (params_rate(params)) { ++ case 8000: ++ case 16000: ++ case 32000: ++ case 64100: ++ writel(50332, S3C_EPLL_CON1); ++ writel((1<<31)|(32<<16)|(1<<8)|(3<<0) ,S3C_EPLL_CON0); ++ break; ++ case 11025: ++ case 22050: ++ case 44100: ++ case 88200: ++ writel(10398, S3C_EPLL_CON1); ++ writel((1<<31)|(45<<16)|(1<<8)|(3<<0) ,S3C_EPLL_CON0); ++ break; ++ case 48000: ++ case 96000: ++ writel(9961, S3C_EPLL_CON1); ++ writel((1<<31)|(49<<16)|(1<<8)|(3<<0) ,S3C_EPLL_CON0); ++ break; ++ default: ++ writel(0, S3C_EPLL_CON1); ++ writel((1<<31)|(128<<16)|(25<<8)|(0<<0) ,S3C_EPLL_CON0); ++ break; ++ } ++ ++ s3cdbg("%s, IISCON: %x IISMOD: %x,IISFIC: %x,IISPSR: %x\n", ++ __FUNCTION__ , readl(S3C_IIS0CON), readl(S3C_IIS0MOD), ++ readl(S3C_IIS0FIC), readl(S3C_IIS0PSR)); ++ ++ while(!(__raw_readl(S3C_EPLL_CON0)&(1<<30))); ++ ++ /* MUXepll : FOUTepll */ ++ writel(readl(S3C_CLK_SRC)|S3C_CLKSRC_EPLL_CLKSEL, S3C_CLK_SRC); ++ /* AUDIO0 sel : FOUTepll */ ++ writel((readl(S3C_CLK_SRC)&~(0x7<<7))|(0<<7), S3C_CLK_SRC); ++ ++ /* CLK_DIV2 setting */ ++ writel(0x0,S3C_CLK_DIV2); ++ ++ switch (params_rate(params)) { ++ case 8000: ++ pll_out = 2048000; ++ prescaler = 8; ++ break; ++ case 11025: ++ pll_out = 2822400; ++ prescaler = 8; ++ break; ++ case 16000: ++ pll_out = 4096000; ++ prescaler = 4; ++ break; ++ case 22050: ++ pll_out = 5644800; ++ prescaler = 4; ++ break; ++ case 32000: ++ pll_out = 8192000; ++ prescaler = 2; ++ break; ++ case 44100: ++ pll_out = 11289600; ++ //prescaler = 6; ++ prescaler = 2; ++ break; ++ case 48000: ++ pll_out = 12288000; ++ prescaler = 2; ++ break; ++ case 88200: ++ pll_out = 22579200; ++ prescaler = 1; ++ break; ++ case 96000: ++ pll_out = 24576000; ++ prescaler = 1; ++ break; ++ default: ++ /* somtimes 32000 rate comes to 96000 ++ default values are same as 32000 */ ++ iismod |= S3C64XX_IIS0MOD_384FS; ++ pll_out = 12288000; ++ break; ++ } ++ ++ /* set MCLK division for sample rate */ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S8: ++ case SNDRV_PCM_FORMAT_S16_LE: ++ iismod |= S3C64XX_IIS0MOD_256FS | S3C64XX_IIS0MOD_32FS; ++ prescaler *= 3; ++ break; ++ case SNDRV_PCM_FORMAT_S24_LE: ++ iismod |= S3C64XX_IIS0MOD_384FS | S3C64XX_IIS0MOD_48FS; ++ prescaler *= 2; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ prescaler = prescaler - 1; ++ writel(iismod , regs + S3C64XX_IIS0MOD); ++ ++ /* set codec DAI configuration */ ++ ret = codec_dai->dai_ops.set_fmt(codec_dai, ++ SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBS_CFS ); ++ if (ret < 0) ++ return ret; ++ ++ /* set cpu DAI configuration */ ++ ret = cpu_dai->dai_ops.set_fmt(cpu_dai, ++ SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBS_CFS ); ++ if (ret < 0) ++ return ret; ++ ++ /* set the codec system clock for DAC and ADC */ ++ ret = codec_dai->dai_ops.set_sysclk(codec_dai, WM8990_MCLK, pll_out, ++ SND_SOC_CLOCK_IN); ++ if (ret < 0) ++ return ret; ++ ++ /* set prescaler division for sample rate */ ++ ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER, ++ (prescaler << 0x8)); ++ if (ret < 0) ++ return ret; ++ ++ return 0; ++} ++ ++/* ++ * Neo1973 WM8990 HiFi DAI opserations. ++ */ ++static struct snd_soc_ops smdk6410_hifi_ops = { ++ .hw_params = smdk6410_hifi_hw_params, ++}; ++ ++static int smdk6410_scenario = 0; ++ ++static int smdk6410_get_scenario(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ ucontrol->value.integer.value[0] = smdk6410_scenario; ++ return 0; ++} ++ ++static int set_scenario_endpoints(struct snd_soc_codec *codec, int scenario) ++{ ++ smdk6410_scenario = scenario; ++ switch (smdk6410_scenario) { ++ case SMDK6410_AUDIO_OFF: ++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 0); ++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 0); ++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 0); ++ break; ++ case SMDK6410_STEREO_TO_HEADPHONES: ++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1); ++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 0); ++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 0); ++ break; ++ case SMDK6410_CAPTURE_MIC1: ++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 0); ++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 1); ++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 0); ++ break; ++ case SMDK6410_CAPTURE_LINE_IN: ++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 0); ++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 0); ++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 1); ++ break; ++ default: ++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1); ++ snd_soc_dapm_set_endpoint(codec, "Mic1 Jack", 1); ++ snd_soc_dapm_set_endpoint(codec, "Line In Jack", 1); ++ break; ++ } ++ ++ snd_soc_dapm_sync_endpoints(codec); ++ return 0; ++} ++ ++static int smdk6410_set_scenario(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); ++ ++ if (smdk6410_scenario == ucontrol->value.integer.value[0]) ++ return 0; ++ ++ set_scenario_endpoints(codec, ucontrol->value.integer.value[0]); ++ return 1; ++} ++ ++static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = { ++ SND_SOC_DAPM_HP("Headphone Jack", NULL), ++ SND_SOC_DAPM_MIC("Mic1 Jack", NULL), ++ SND_SOC_DAPM_LINE("Line In Jack", NULL), ++}; ++ ++/* example machine audio_mapnections */ ++static const struct snd_soc_dapm_route audio_map[] = { ++ ++ /* no irq jack detect */ ++ {"Headphone Jack", NULL, "LOUT"}, ++ {"Headphone Jack", NULL, "ROUT"}, ++ ++ /* mic is connected to LIN1 and LIN2 - with bias */ ++ {"LIN1", NULL, "Mic1 Jack"}, ++ //{"LIN2", NULL, "Mic1 Jack"}, ++ ++ {"LIN2", NULL, "Line In Jack"}, ++ {"RIN2", NULL, "Line In Jack"}, ++ ++}; ++ ++static const char *smdk_scenarios[] = { ++ "Off", ++ "Capture Line In", ++ "Headphones", ++ "Capture Mic1", ++}; ++ ++static const struct soc_enum smdk_scenario_enum[] = { ++ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(smdk_scenarios),smdk_scenarios), ++}; ++ ++static const struct snd_kcontrol_new wm8990_smdk6410_controls[] = { ++ SOC_ENUM_EXT("SMDK Mode", smdk_scenario_enum[0], ++ smdk6410_get_scenario, smdk6410_set_scenario), ++}; ++ ++/* ++ * This is an example machine initialisation for a wm8990 connected to a ++ * smdk6410. It is missing logic to detect hp/mic insertions and logic ++ * to re-route the audio in such an event. ++ */ ++static int smdk6410_wm8990_init(struct snd_soc_codec *codec) ++{ ++ int i, err; ++ ++ /* Add smdk6410 specific widgets */ ++ for (i = 0; i < ARRAY_SIZE(wm8990_dapm_widgets); i++) ++ snd_soc_dapm_new_control(codec, &wm8990_dapm_widgets[i]); ++ ++ /* add smdk6410 specific controls */ ++ for (i = 0; i < ARRAY_SIZE(wm8990_smdk6410_controls); i++) { ++ err = snd_ctl_add(codec->card, ++ snd_soc_cnew(&wm8990_smdk6410_controls[i], ++ codec, NULL)); ++ if (err < 0) ++ return err; ++ } ++ ++ /* set up smdk6410 specific audio paths */ ++ snd_soc_dapm_add_routes(codec, audio_map,ARRAY_SIZE(audio_map)); ++ ++ /* not connected */ ++ snd_soc_dapm_set_endpoint(codec, "RIN1", 0); ++ snd_soc_dapm_set_endpoint(codec, "LIN3", 0); ++ snd_soc_dapm_set_endpoint(codec, "LIN4", 0); ++ snd_soc_dapm_set_endpoint(codec, "RIN3", 0); ++ snd_soc_dapm_set_endpoint(codec, "RIN4", 0); ++ snd_soc_dapm_set_endpoint(codec, "OUT3", 0); ++ snd_soc_dapm_set_endpoint(codec, "OUT4", 0); ++ snd_soc_dapm_set_endpoint(codec, "SPKP", 0); ++ snd_soc_dapm_set_endpoint(codec, "SPKN", 0); ++ snd_soc_dapm_set_endpoint(codec, "ROP", 0); ++ snd_soc_dapm_set_endpoint(codec, "RON", 0); ++ snd_soc_dapm_set_endpoint(codec, "LOP", 0); ++ snd_soc_dapm_set_endpoint(codec, "LON", 0); ++ ++ /* set endpoints to default mode & sync with DAPM */ ++ set_scenario_endpoints(codec, SMDK6410_STEREO_TO_HEADPHONES); ++ ++ return 0; ++} ++ ++static struct snd_soc_dai_link smdk6410_dai[] = { ++{ /* Hifi Playback - for similatious use with voice below */ ++ .name = "WM8990", ++ .stream_name = "WM8990 HiFi", ++ .cpu_dai = &s3c_i2s_dai, ++ .codec_dai = &wm8990_dai, ++ .init = smdk6410_wm8990_init, ++ .ops = &smdk6410_hifi_ops, ++}, ++}; ++ ++static struct snd_soc_machine smdk6410 = { ++ .name = "smdk6410", ++ .dai_link = smdk6410_dai, ++ .num_links = ARRAY_SIZE(smdk6410_dai), ++}; ++ ++static struct wm8990_setup_data smdk6410_wm8990_setup = { ++ .i2c_address = 0x1b, ++}; ++ ++static struct snd_soc_device smdk6410_snd_devdata = { ++ .machine = &smdk6410, ++ .platform = &s3c24xx_soc_platform, ++ .codec_dev = &soc_codec_dev_wm8990, ++ .codec_data = &smdk6410_wm8990_setup, ++}; ++ ++static struct platform_device *smdk6410_snd_device; ++ ++static int __init smdk6410_init(void) ++{ ++ int ret; ++ ++ smdk6410_snd_device = platform_device_alloc("soc-audio", -1); ++ if (!smdk6410_snd_device) ++ return -ENOMEM; ++ ++ platform_set_drvdata(smdk6410_snd_device, &smdk6410_snd_devdata); ++ smdk6410_snd_devdata.dev = &smdk6410_snd_device->dev; ++ ret = platform_device_add(smdk6410_snd_device); ++ ++ if (ret) ++ platform_device_put(smdk6410_snd_device); ++ ++ return ret; ++} ++ ++static void __exit smdk6410_exit(void) ++{ ++ platform_device_unregister(smdk6410_snd_device); ++} ++ ++module_init(smdk6410_init); ++module_exit(smdk6410_exit); ++ ++/* Module information */ ++MODULE_AUTHOR("Liam Girdwood"); ++MODULE_DESCRIPTION("ALSA SoC WM8990 SMDK6410"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s3c64xx/smdk6440_s5m8751.c linux-2.6.28.6/sound/soc/s3c64xx/smdk6440_s5m8751.c +--- linux-2.6.28/sound/soc/s3c64xx/smdk6440_s5m8751.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s3c64xx/smdk6440_s5m8751.c 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,269 @@ ++/* ++ * smdk6440_s5m8751.c ++ * ++ * Copyright (C) 2009, Samsung Elect. Ltd. - Jaswinder Singh ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../codecs/s5m8751.h" ++#include "s3c-pcm.h" ++ ++#include "s5p6440-i2s.h" ++ ++#define SRC_CLK s5p6440_i2s_get_clockrate() ++ ++/* XXX BLC(bits-per-channel) --> BFS(bit clock shud be >= FS*(Bit-per-channel)*2) XXX */ ++/* XXX BFS --> RFS(must be a multiple of BFS) XXX */ ++/* XXX RFS & SRC_CLK --> Prescalar Value(SRC_CLK / RFS_VAL / fs - 1) XXX */ ++static int smdk6440_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; ++ struct snd_soc_dai *codec_dai = rtd->dai->codec_dai; ++ int bfs, rfs, psr, ret; ++ ++ /* Choose BFS and RFS values combination that is supported by ++ * both the S5M8751 codec as well as the S5P6440 AP ++ * ++ * S5M8751 codec supports only S16_LE, S18_3LE, S20_3LE & S24_LE. ++ * S5P6440 AP supports only S8, S16_LE & S24_LE. ++ * We implement all for completeness but only S16_LE & S24_LE bit-lengths ++ * are possible for this AP-Codec combination. ++ */ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S8: ++ bfs = 16; ++ rfs = 256; /* Can take any RFS value for AP */ ++ break; ++ case SNDRV_PCM_FORMAT_S16_LE: ++ bfs = 32; ++ rfs = 256; /* Can take any RFS value for AP */ ++ break; ++ case SNDRV_PCM_FORMAT_S18_3LE: ++ case SNDRV_PCM_FORMAT_S20_3LE: ++ case SNDRV_PCM_FORMAT_S24_LE: ++ bfs = 48; ++ rfs = 512; /* See Table 41-1,2 of S5P6440 UserManual */ ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ /* Select the AP Sysclk */ ++ ret = snd_soc_dai_set_sysclk(cpu_dai, S5P6440_CDCLKSRC_INT, params_rate(params), SND_SOC_CLOCK_OUT); ++ if (ret < 0) ++ return ret; ++ ++#ifdef USE_CLKAUDIO ++ ret = snd_soc_dai_set_sysclk(cpu_dai, S5P6440_CLKSRC_CLKAUDIO, params_rate(params), SND_SOC_CLOCK_OUT); ++#else ++ ret = snd_soc_dai_set_sysclk(cpu_dai, S5P6440_CLKSRC_PCLK, 0, SND_SOC_CLOCK_OUT); ++#endif ++ if (ret < 0) ++ return ret; ++ ++ /* Set the AP DAI configuration */ ++ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); ++ if (ret < 0) ++ return ret; ++ ++ /* Set the AP RFS */ ++ ret = snd_soc_dai_set_clkdiv(cpu_dai, S5P64XX_DIV_MCLK, rfs); ++ if (ret < 0) ++ return ret; ++ ++ /* Set the AP BFS */ ++ ret = snd_soc_dai_set_clkdiv(cpu_dai, S5P64XX_DIV_BCLK, bfs); ++ if (ret < 0) ++ return ret; ++ ++ switch (params_rate(params)) { ++ case 8000: ++ case 11025: ++ case 16000: ++ case 22050: ++ case 32000: ++ case 44100: ++ case 48000: ++ case 64000: ++ case 88200: ++ case 96000: ++ psr = SRC_CLK / rfs / params_rate(params); ++ ret = SRC_CLK / rfs - psr * params_rate(params); ++ if(ret >= params_rate(params)/2) // round off ++ psr += 1; ++ psr -= 1; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ //printk("SRC_CLK=%d PSR=%d RFS=%d BFS=%d\n", SRC_CLK, psr, rfs, bfs); ++ ++ /* Set the AP Prescalar */ ++ ret = snd_soc_dai_set_clkdiv(cpu_dai, S5P64XX_DIV_PRESCALER, psr); ++ if (ret < 0) ++ return ret; ++ ++ /* Set the Codec DAI configuration */ ++ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); ++ if (ret < 0) ++ return ret; ++ ++ /* Set the Codec BCLK(no option to set the MCLK) */ ++ ret = snd_soc_dai_set_clkdiv(codec_dai, S5M8751_BCLK, bfs); ++ if (ret < 0) ++ return ret; ++ ++ return 0; ++} ++ ++/* ++ * S5M8751 DAI operations. ++ */ ++static struct snd_soc_ops smdk6440_ops = { ++ .hw_params = smdk6440_hw_params, ++}; ++ ++static const struct snd_soc_dapm_widget s5m8751_dapm_widgets[] = { ++ SND_SOC_DAPM_LINE("I2S Front Jack", NULL), ++ SND_SOC_DAPM_LINE("I2S Center Jack", NULL), ++ SND_SOC_DAPM_LINE("I2S Rear Jack", NULL), ++ SND_SOC_DAPM_LINE("Line In Jack", NULL), ++}; ++ ++/* example machine audio_mapnections */ ++static const struct snd_soc_dapm_route audio_map[] = { ++ ++ { "I2S Front Jack", NULL, "VOUT1L" }, ++ { "I2S Front Jack", NULL, "VOUT1R" }, ++ ++ { "I2S Center Jack", NULL, "VOUT2L" }, ++ { "I2S Center Jack", NULL, "VOUT2R" }, ++ ++ { "I2S Rear Jack", NULL, "VOUT3L" }, ++ { "I2S Rear Jack", NULL, "VOUT3R" }, ++ ++ { "AINL", NULL, "Line In Jack" }, ++ { "AINR", NULL, "Line In Jack" }, ++ ++}; ++ ++static int smdk6440_s5m8751_init(struct snd_soc_codec *codec) ++{ ++ int i; ++ ++ /* Add smdk6440 specific widgets */ ++ snd_soc_dapm_new_controls(codec, s5m8751_dapm_widgets,ARRAY_SIZE(s5m8751_dapm_widgets)); ++ ++ /* set up smdk6440 specific audio paths */ ++ snd_soc_dapm_add_routes(codec, audio_map,ARRAY_SIZE(audio_map)); ++ ++ /* No jack detect - mark all jacks as enabled */ ++ for (i = 0; i < ARRAY_SIZE(s5m8751_dapm_widgets); i++) ++ snd_soc_dapm_set_endpoint(codec, ++ s5m8751_dapm_widgets[i].name, 1); ++ ++ snd_soc_dapm_sync_endpoints(codec); ++ ++ return 0; ++} ++ ++static struct snd_soc_dai_link smdk6440_dai[] = { ++{ ++ .name = "S5M8751", ++ .stream_name = "S5M8751 Playback", ++ .cpu_dai = &s5p6440_i2s_v40_dai, ++ .codec_dai = &s5m8751_dai, ++ .init = smdk6440_s5m8751_init, ++ .ops = &smdk6440_ops, ++}, ++}; ++ ++static struct snd_soc_machine smdk6440 = { ++ .name = "smdk6440", ++ .dai_link = smdk6440_dai, ++ .num_links = ARRAY_SIZE(smdk6440_dai), ++}; ++ ++static struct s5m8751_setup_data smdk6440_s5m8751_setup = { ++ .i2c_address = 0x68, ++}; ++ ++static struct snd_soc_device smdk6440_snd_devdata = { ++ .machine = &smdk6440, ++ .platform = &s3c24xx_soc_platform, ++ .codec_dev = &soc_codec_dev_s5m8751, ++ .codec_data = &smdk6440_s5m8751_setup, ++}; ++ ++static struct platform_device *smdk6440_snd_device; ++ ++static int __init vega_audio_init(void) ++{ ++ int ret; ++ u32 val; ++ /* configure the GPR pins is I2C mode */ ++ /* Configure the GPR pins in I2S mode */ ++ val = __raw_readl(S5P64XX_GPRPUD); ++ val &= ~((3<<8) | (3<<10) | (3<<14) | (3<<16) | (3<<18) | (3<<20) | (3<<28) | (3<<30)); ++ val |= ((0<<8) | (0<<10) | (0<<14) | (0<<16) | (0<<18) | (1<<19) | (1<<21) | (0<<28) | (1<<30)); ++ __raw_writel(val, S5P64XX_GPRPUD); ++ ++ val = __raw_readl(S5P64XX_GPRCON0); ++ val &= ~((0xf<<16) | (0xf<<20) | (0xf<<28)); ++ val |= (5<<16) | (5<<20) | (5<<28); ++ __raw_writel(val, S5P64XX_GPRCON0); ++ ++ val = __raw_readl(S5P64XX_GPRCON1); ++ val &= ~((0xf<<0) | (0xf<<4) | (0xf<<8) | (0xf<<12) | (0xf<<24) | (0xf<<28)); ++ val |= (5<<0) | (5<<4) | (3<<9) | (3<<13) | (5<<24) | (5<<28); ++ __raw_writel(val, S5P64XX_GPRCON1); ++ ++ smdk6440_snd_device = platform_device_alloc("soc-audio", 0); ++ if (!smdk6440_snd_device) ++ return -ENOMEM; ++ ++ platform_set_drvdata(smdk6440_snd_device, &smdk6440_snd_devdata); ++ smdk6440_snd_devdata.dev = &smdk6440_snd_device->dev; ++ ret = platform_device_add(smdk6440_snd_device); ++ ++ if (ret) ++ platform_device_put(smdk6440_snd_device); ++ ++ return ret; ++} ++ ++static void __exit vega_audio_exit(void) ++{ ++ platform_device_unregister(smdk6440_snd_device); ++} ++ ++module_init(vega_audio_init); ++module_exit(vega_audio_exit); ++ ++/* Module information */ ++MODULE_DESCRIPTION("ALSA SoC SMDK6440 S5M8751"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s3c64xx/smdk6440_wm8580.c linux-2.6.28.6/sound/soc/s3c64xx/smdk6440_wm8580.c +--- linux-2.6.28/sound/soc/s3c64xx/smdk6440_wm8580.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s3c64xx/smdk6440_wm8580.c 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,317 @@ ++/* ++ * smdk6440_wm8580.c ++ * ++ * Copyright (C) 2009, Samsung Elect. Ltd. - Jaswinder Singh ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++//#define USE_GPR ++ ++#ifdef USE_GPR ++#include ++#else ++#include ++#include ++#endif ++ ++#include ++#include ++ ++#include "../codecs/wm8580.h" ++#include "s3c-pcm.h" ++ ++#include "s5p6440-i2s.h" ++ ++#define SRC_CLK s5p6440_i2s_get_clockrate() ++ ++/* XXX BLC(bits-per-channel) --> BFS(bit clock shud be >= FS*(Bit-per-channel)*2) XXX */ ++/* XXX BFS --> RFS(must be a multiple of BFS) XXX */ ++/* XXX RFS & SRC_CLK --> Prescalar Value(SRC_CLK / RFS_VAL / fs - 1) XXX */ ++static int smdk6440_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; ++ struct snd_soc_dai *codec_dai = rtd->dai->codec_dai; ++ int bfs, rfs, psr, ret; ++ ++ /* Choose BFS and RFS values combination that is supported by ++ * both the WM8580 codec as well as the S5P6440 AP ++ * ++ * WM8580 codec supports only S16_LE, S20_3LE, S24_LE & S32_LE. ++ * S5P6440 AP supports only S8, S16_LE & S24_LE. ++ * We implement all for completeness but only S16_LE & S24_LE bit-lengths ++ * are possible for this AP-Codec combination. ++ */ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S8: ++ bfs = 16; ++ rfs = 256; /* Can take any RFS value for AP */ ++ break; ++ case SNDRV_PCM_FORMAT_S16_LE: ++ bfs = 32; ++ rfs = 256; /* Can take any RFS value for AP */ ++ break; ++ case SNDRV_PCM_FORMAT_S20_3LE: ++ case SNDRV_PCM_FORMAT_S24_LE: ++ bfs = 48; ++ rfs = 512; /* See Table 41-1,2 of S5P6440 UserManual */ ++ break; ++ case SNDRV_PCM_FORMAT_S32_LE: /* Impossible, as the AP doesn't support 64fs or more BFS */ ++ default: ++ return -EINVAL; ++ } ++ ++ /* Select the AP Sysclk */ ++ ret = snd_soc_dai_set_sysclk(cpu_dai, S5P6440_CDCLKSRC_INT, params_rate(params), SND_SOC_CLOCK_OUT); ++ if (ret < 0) ++ return ret; ++ ++#ifdef USE_CLKAUDIO ++ ret = snd_soc_dai_set_sysclk(cpu_dai, S5P6440_CLKSRC_CLKAUDIO, params_rate(params), SND_SOC_CLOCK_OUT); ++#else ++ ret = snd_soc_dai_set_sysclk(cpu_dai, S5P6440_CLKSRC_PCLK, 0, SND_SOC_CLOCK_OUT); ++#endif ++ if (ret < 0) ++ return ret; ++ ++ /* Set the AP DAI configuration */ ++ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); ++ if (ret < 0) ++ return ret; ++ ++ /* Set the AP RFS */ ++ ret = snd_soc_dai_set_clkdiv(cpu_dai, S5P64XX_DIV_MCLK, rfs); ++ if (ret < 0) ++ return ret; ++ ++ /* Set the AP BFS */ ++ ret = snd_soc_dai_set_clkdiv(cpu_dai, S5P64XX_DIV_BCLK, bfs); ++ if (ret < 0) ++ return ret; ++ ++ switch (params_rate(params)) { ++ case 8000: ++ case 11025: ++ case 16000: ++ case 22050: ++ case 32000: ++ case 44100: ++ case 48000: ++ case 64000: ++ case 88200: ++ case 96000: ++ psr = SRC_CLK / rfs / params_rate(params); ++ ret = SRC_CLK / rfs - psr * params_rate(params); ++ if(ret >= params_rate(params)/2) // round off ++ psr += 1; ++ psr -= 1; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ //printk("SRC_CLK=%d PSR=%d RFS=%d BFS=%d\n", SRC_CLK, psr, rfs, bfs); ++ ++ /* Set the AP Prescalar */ ++ ret = snd_soc_dai_set_clkdiv(cpu_dai, S5P64XX_DIV_PRESCALER, psr); ++ if (ret < 0) ++ return ret; ++ ++ /* Set the Codec DAI configuration */ ++ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); ++ if (ret < 0) ++ return ret; ++ ++ /* Set the Codec BCLK(no option to set the MCLK) */ ++ /* See page 2 and 53 of Wm8580 Manual */ ++ ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_MCLK, WM8580_CLKSRC_MCLK); /* Use MCLK provided by CPU i/f */ ++ if (ret < 0) ++ return ret; ++ ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_DAC_CLKSEL, WM8580_CLKSRC_MCLK); /* Fig-26 Pg-43 */ ++ if (ret < 0) ++ return ret; ++ ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_CLKOUTSRC, WM8580_CLKSRC_NONE); /* Pg-58 */ ++ if (ret < 0) ++ return ret; ++ ++ return 0; ++} ++ ++/* ++ * WM8580 DAI operations. ++ */ ++static struct snd_soc_ops smdk6440_ops = { ++ .hw_params = smdk6440_hw_params, ++}; ++ ++static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = { ++ SND_SOC_DAPM_LINE("I2S Front Jack", NULL), ++ SND_SOC_DAPM_LINE("I2S Center Jack", NULL), ++ SND_SOC_DAPM_LINE("I2S Rear Jack", NULL), ++ SND_SOC_DAPM_LINE("Line In Jack", NULL), ++}; ++ ++/* example machine audio_mapnections */ ++static const struct snd_soc_dapm_route audio_map[] = { ++ ++ { "I2S Front Jack", NULL, "VOUT1L" }, ++ { "I2S Front Jack", NULL, "VOUT1R" }, ++ ++ { "I2S Center Jack", NULL, "VOUT2L" }, ++ { "I2S Center Jack", NULL, "VOUT2R" }, ++ ++ { "I2S Rear Jack", NULL, "VOUT3L" }, ++ { "I2S Rear Jack", NULL, "VOUT3R" }, ++ ++ { "AINL", NULL, "Line In Jack" }, ++ { "AINR", NULL, "Line In Jack" }, ++ ++}; ++ ++static int smdk6440_wm8580_init(struct snd_soc_codec *codec) ++{ ++ int i; ++ ++ /* Add smdk6440 specific widgets */ ++ snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets,ARRAY_SIZE(wm8580_dapm_widgets)); ++ ++ /* set up smdk6440 specific audio paths */ ++ snd_soc_dapm_add_routes(codec, audio_map,ARRAY_SIZE(audio_map)); ++ ++ /* No jack detect - mark all jacks as enabled */ ++ for (i = 0; i < ARRAY_SIZE(wm8580_dapm_widgets); i++) ++ snd_soc_dapm_set_endpoint(codec, ++ wm8580_dapm_widgets[i].name, 1); ++ ++ snd_soc_dapm_sync_endpoints(codec); ++ ++ return 0; ++} ++ ++static struct snd_soc_dai_link smdk6440_dai[] = { ++{ ++ .name = "WM8580", ++ .stream_name = "WM8580 HiFi Playback", ++ .cpu_dai = &s5p6440_i2s_v40_dai, ++ .codec_dai = &wm8580_dai[WM8580_DAI_PAIFRX], ++ .init = smdk6440_wm8580_init, ++ .ops = &smdk6440_ops, ++}, ++}; ++ ++static struct snd_soc_machine smdk6440 = { ++ .name = "smdk6440", ++ .dai_link = smdk6440_dai, ++ .num_links = ARRAY_SIZE(smdk6440_dai), ++}; ++ ++static struct wm8580_setup_data smdk6440_wm8580_setup = { ++ .i2c_address = 0x1b, ++}; ++ ++static struct snd_soc_device smdk6440_snd_devdata = { ++ .machine = &smdk6440, ++ .platform = &s3c24xx_soc_platform, ++ .codec_dev = &soc_codec_dev_wm8580, ++ .codec_data = &smdk6440_wm8580_setup, ++}; ++ ++static struct platform_device *smdk6440_snd_device; ++ ++static int __init vega_audio_init(void) ++{ ++ int ret; ++ u32 val; ++ ++#ifdef USE_GPR ++ val = __raw_readl(S5P64XX_GPRPUD); ++ val &= ~((3<<8) | (3<<10) | (3<<14) | (3<<16) | (3<<18) | (3<<28) | (3<<30)); ++ val |= ((0<<8) | (0<<10) | (0<<14) | (0<<16) | (0<<18) | (0<<28) | (1<<30)); ++ __raw_writel(val, S5P64XX_GPRPUD); ++ ++ val = __raw_readl(S5P64XX_GPRCON0); ++ val &= ~((0xf<<16) | (0xf<<20) | (0xf<<28)); ++ val |= (5<<16) | (5<<20) | (5<<28); ++ __raw_writel(val, S5P64XX_GPRCON0); ++ ++ val = __raw_readl(S5P64XX_GPRCON1); ++ val &= ~((0xf<<0) | (0xf<<4) | (0xf<<24) | (0xf<<28)); ++ val |= (5<<0) | (5<<4) | (5<<24) | (5<<28); ++ __raw_writel(val, S5P64XX_GPRCON1); ++ ++#else ++ val = __raw_readl(S5P64XX_GPCPUD); ++ val &= ~((3<<8) | (3<<10) | (3<<14)); ++ val |= ((0<<8) | (0<<10) | (0<<14)); ++ __raw_writel(val, S5P64XX_GPCPUD); ++ ++ val = __raw_readl(S5P64XX_GPCCON); ++ val &= ~((0xf<<16) | (0xf<<20) | (0xf<<28)); ++ val |= (5<<16) | (5<<20) | (5<<28); ++ __raw_writel(val, S5P64XX_GPCCON); ++ ++ val = __raw_readl(S5P64XX_GPHPUD); ++ val &= ~((3<<12) | (3<<14) | (3<<16) | (3<<18)); ++ val |= ((0<<12) | (1<<14) | (0<<16) | (0<18)); ++ __raw_writel(val, S5P64XX_GPHPUD); ++ ++ val = __raw_readl(S5P64XX_GPHCON0); ++ val &= ~((0xf<<24) | (0xf<<28)); ++ val |= (5<<24) | (5<<28); ++ __raw_writel(val, S5P64XX_GPHCON0); ++ ++ val = __raw_readl(S5P64XX_GPHCON1); ++ val &= ~((0xf<<0) | (0xf<<4)); ++ val |= (5<<0) | (5<<4); ++ __raw_writel(val, S5P64XX_GPHCON1); ++ ++ val = __raw_readl(S3C_CLK_OUT); ++ val &= ~(0xff << 12); ++ val |= (0x1<<12) | (0<<16); ++ __raw_writel(val, S3C_CLK_OUT); ++#endif ++ ++ smdk6440_snd_device = platform_device_alloc("soc-audio", 0); ++ if (!smdk6440_snd_device) ++ return -ENOMEM; ++ ++ platform_set_drvdata(smdk6440_snd_device, &smdk6440_snd_devdata); ++ smdk6440_snd_devdata.dev = &smdk6440_snd_device->dev; ++ ret = platform_device_add(smdk6440_snd_device); ++ ++ if (ret) ++ platform_device_put(smdk6440_snd_device); ++ ++ return ret; ++} ++ ++static void __exit vega_audio_exit(void) ++{ ++ platform_device_unregister(smdk6440_snd_device); ++} ++ ++module_init(vega_audio_init); ++module_exit(vega_audio_exit); ++ ++/* Module information */ ++MODULE_DESCRIPTION("ALSA SoC SMDK6440 WM8580"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s3c64xx/smdk64xx_wm9713.c linux-2.6.28.6/sound/soc/s3c64xx/smdk64xx_wm9713.c +--- linux-2.6.28/sound/soc/s3c64xx/smdk64xx_wm9713.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s3c64xx/smdk64xx_wm9713.c 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,88 @@ ++/* ++ * smdk6400_wm9713.c -- SoC audio for smdk6400 ++ * ++ * Copyright (C) 2007, Ryu Euiyoul ++ * ++ * Copyright 2007 Wolfson Microelectronics PLC. ++ * Author: Graeme Gregory ++ * graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * Revision history ++ * 8th Mar 2007 Initial version. ++ * 20th Sep 2007 Apply at smdk6400 ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../codecs/wm9713.h" ++#include "s3c-pcm.h" ++#include "s3c64xx-ac97.h" ++ ++static struct snd_soc_machine smdk6400; ++ ++static struct snd_soc_dai_link smdk6400_dai[] = { ++{ ++ .name = "AC97", ++ .stream_name = "AC97 HiFi", ++ .cpu_dai = &s3c6400_ac97_dai[0], ++ .codec_dai = &wm9713_dai[WM9713_DAI_AC97_HIFI], ++}, ++}; ++ ++static struct snd_soc_machine smdk6400 = { ++ .name = "SMDK6400", ++ .dai_link = smdk6400_dai, ++ .num_links = ARRAY_SIZE(smdk6400_dai), ++}; ++ ++static struct snd_soc_device smdk6400_snd_ac97_devdata = { ++ .machine = &smdk6400, ++ .platform = &s3c24xx_soc_platform, ++ .codec_dev = &soc_codec_dev_wm9713, ++}; ++ ++static struct platform_device *smdk6400_snd_ac97_device; ++ ++static int __init smdk6400_init(void) ++{ ++ int ret; ++ ++ smdk6400_snd_ac97_device = platform_device_alloc("soc-audio", -1); ++ if (!smdk6400_snd_ac97_device) ++ return -ENOMEM; ++ ++ platform_set_drvdata(smdk6400_snd_ac97_device, ++ &smdk6400_snd_ac97_devdata); ++ smdk6400_snd_ac97_devdata.dev = &smdk6400_snd_ac97_device->dev; ++ ret = platform_device_add(smdk6400_snd_ac97_device); ++ ++ if (ret) ++ platform_device_put(smdk6400_snd_ac97_device); ++ ++ return ret; ++} ++ ++static void __exit smdk6400_exit(void) ++{ ++ platform_device_unregister(smdk6400_snd_ac97_device); ++} ++ ++module_init(smdk6400_init); ++module_exit(smdk6400_exit); ++ ++/* Module information */ ++MODULE_AUTHOR("Samsung: Ryu"); ++MODULE_DESCRIPTION("ALSA SoC WM9713 SMDK6400"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s5pc1xx/Kconfig linux-2.6.28.6/sound/soc/s5pc1xx/Kconfig +--- linux-2.6.28/sound/soc/s5pc1xx/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s5pc1xx/Kconfig 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,77 @@ ++menu "SoC Audio for the Samsung S3C" ++ depends on ARCH_S5PC1XX ++ ++config SND_S5PC1XX_SOC ++ tristate "SoC Audio for the Samsung S3C chips" ++ depends on ARCH_S5PC1XX ++ select SND_PCM ++ help ++ Say Y or M if you want to add support for codecs attached to ++ the S3C AC97, I2S or SSP interface. You will also need ++ to select the audio interfaces to support below. ++ ++config SND_S3C_SOC_I2S ++ tristate ++ ++config SND_SOC_I2S_V50 ++ tristate ++ ++config SND_SMDKC100_WM8580 ++ tristate "SoC I2S Audio support for SMDKC100 - WM8580" ++ depends on SND_S5PC1XX_SOC && MACH_SMDKC100 ++ select SND_SOC_I2S_V50 ++ select SND_SOC_WM8580 ++ help ++ Say Y if you want to add support for SoC audio on smdk6410 ++ with the WM8580. ++ ++choice ++ prompt "SMDK Record Path Select" ++ depends on SND_SMDKC100_WM8580 ++ ++config SOUND_S5PC100_WM8580_INPUT_STREAM_LINE ++ bool "Input Stream is LINE-IN" ++ depends on SND_SMDKC100_WM8580 ++ help ++ Say Y here to make input stream as LINE-IN. ++ ++config SOUND_S5PC100_WM8580_INPUT_STREAM_MIC ++ bool "Input Stream is MIC" ++ depends on SND_SMDKC100_WM8580 ++ help ++ Say Y here to make input stream as MIC. ++endchoice ++ ++config SND_SMDKC100_WM9713 ++ tristate "SoC AC97 Audio support for SMDKC100 - WM9713" ++ depends on SND_S5PC1XX_SOC && MACH_SMDKC100 ++ select SND_S5PC100_SOC_AC97 ++ select SND_SOC_WM9713 ++ help ++ Say Y if you want to add support for SoC audio on SMDKC100 ++ with the WM9713. ++ ++choice ++ prompt "SMDK Record Path Select" ++ depends on SND_SMDKC100_WM9713 ++ ++config SOUND_S5PC100_WM9713_INPUT_STREAM_LINE ++ bool "Input Stream is LINE-IN" ++ depends on SND_SMDKC100_WM9713 ++ help ++ Say Y here to make input stream as LINE-IN. ++ ++config SOUND_S5PC100_WM9713_INPUT_STREAM_MIC ++ bool "Input Stream is MIC" ++ depends on SND_SMDKC100_WM9713 ++ help ++ Say Y here to make input stream as MIC. ++endchoice ++ ++config SND_S5PC100_SOC_AC97 ++ tristate ++ select AC97_BUS ++ select SND_AC97_CODEC ++ select SND_SOC_AC97_BUS ++ ++endmenu +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s5pc1xx/Makefile linux-2.6.28.6/sound/soc/s5pc1xx/Makefile +--- linux-2.6.28/sound/soc/s5pc1xx/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s5pc1xx/Makefile 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,15 @@ ++# S5PC1XX Platform Support ++snd-soc-s5pc1xx-objs := s5pc1xx-pcm.o ++snd-soc-s5pc1xx-i2s-v50-objs := s5pc100-i2s-v50.o ++snd-soc-s5pc1xx-ac97-objs := s5pc1xx-ac97.o ++ ++obj-$(CONFIG_SND_S5PC1XX_SOC) += snd-soc-s5pc1xx.o ++obj-$(CONFIG_SND_SOC_I2S_V50) += snd-soc-s5pc1xx-i2s-v50.o ++obj-$(CONFIG_SND_S5PC100_SOC_AC97) += snd-soc-s5pc1xx-ac97.o ++ ++# S5PC1XX Machine Support ++snd-soc-smdkc1xx-wm8580-objs := smdkc100_wm8580.o ++snd-soc-smdkc1xx-wm9713-objs := smdkc100_wm9713.o ++ ++obj-$(CONFIG_SND_SMDKC100_WM8580) += snd-soc-smdkc1xx-wm8580.o ++obj-$(CONFIG_SND_SMDKC100_WM9713) += snd-soc-smdkc1xx-wm9713.o +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s5pc1xx/s5pc100-i2s-v50.c linux-2.6.28.6/sound/soc/s5pc1xx/s5pc100-i2s-v50.c +--- linux-2.6.28/sound/soc/s5pc1xx/s5pc100-i2s-v50.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s5pc1xx/s5pc100-i2s-v50.c 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,581 @@ ++/* ++ * s3c-i2s.c -- ALSA Soc Audio Layer ++ * ++ * (c) 2006 Wolfson Microelectronics PLC. ++ * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com ++ * ++ * (c) 2004-2005 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * Ryu Euiyoul ++ * ++ * Copyright (C) 2008, SungJun Bae ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * ++ * Revision history ++ * 11th Dec 2006 Merged with Simtec driver ++ * 10th Nov 2006 Initial version. ++ * 1st Dec 2008 Initial version from s3c64xx-i2s.c. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++#include "s5pc1xx-i2s.h" ++#include "s5pc1xx-pcm.h" ++ ++#ifdef CONFIG_SND_DEBUG ++#define s3cdbg(x...) printk(x) ++#else ++#define s3cdbg(x...) ++#endif ++ ++/* used to disable sysclk if external crystal is used */ ++static int extclk = 0; ++module_param(extclk, int, 0); ++MODULE_PARM_DESC(extclk, "set to 1 to disable s3c24XX i2s sysclk"); ++ ++static struct s3c2410_dma_client s5pc1xx_dma_client_out = { ++ .name = "I2S PCM Stereo out" ++}; ++ ++static struct s3c2410_dma_client s5pc1xx_dma_client_in = { ++ .name = "I2S PCM Stereo in" ++}; ++ ++static struct s3c24xx_pcm_dma_params s5pc1xx_i2s_pcm_stereo_out = { ++ .client = &s5pc1xx_dma_client_out, ++ .channel = DMACH_I2S_V50_OUT, ++ .dma_addr = S3C_PA_IIS + S3C64XX_IISFIFO, ++ .dma_size = 4, ++}; ++ ++static struct s3c24xx_pcm_dma_params s5pc1xx_i2s_pcm_stereo_in = { ++ .client = &s5pc1xx_dma_client_in, ++ .channel = DMACH_I2S_V50_IN, ++ .dma_addr = S3C_PA_IIS + S3C64XX_IISFIFORX, ++ .dma_size = 4, ++}; ++ ++struct s5pc1xx_i2s_info { ++ void __iomem *regs; ++ struct clk *iis_clk; ++ int master; ++}; ++static struct s5pc1xx_i2s_info s5pc1xx_i2s; ++ ++static void s5pc1xx_snd_txctrl(int on) ++{ ++ u32 iiscon; ++ u32 iismod; ++ ++ s3cdbg("Entered %s : on = %d \n", __FUNCTION__, on); ++ ++ iiscon = readl(s5pc1xx_i2s.regs + S3C64XX_IIS0CON); ++ iismod = readl(s5pc1xx_i2s.regs + S3C64XX_IIS0MOD); ++ ++ s3cdbg("r: IISCON: %x IISMOD: %x\n", iiscon, iismod); ++ ++ if (on) { ++ iiscon |= S3C64XX_IIS0CON_I2SACTIVE; ++ ++ writel(iismod, s5pc1xx_i2s.regs + S3C64XX_IIS0MOD); ++ writel(iiscon, s5pc1xx_i2s.regs + S3C64XX_IIS0CON); ++ ++ } else { ++ /* note, we have to disable the FIFOs otherwise bad things ++ * seem to happen when the DMA stops. According to the ++ * Samsung supplied kernel, this should allow the DMA ++ * engine and FIFOs to reset. If this isn't allowed, the ++ * DMA engine will simply freeze randomly. ++ */ ++ iiscon &= ~(S3C64XX_IIS0CON_I2SACTIVE); ++ iismod &= ~S3C64XX_IIS0MOD_TXMODE; ++ ++ writel(iiscon, s5pc1xx_i2s.regs + S3C64XX_IIS0CON); ++ writel(iismod, s5pc1xx_i2s.regs + S3C64XX_IIS0MOD); ++ } ++ ++ s3cdbg("w: IISCON: %x IISMOD: %x\n", iiscon, iismod); ++} ++ ++static void s5pc1xx_snd_rxctrl(int on) ++{ ++ u32 iisfcon; ++ u32 iiscon; ++ u32 iismod; ++ ++ s3cdbg("Entered %s: on = %d\n", __FUNCTION__, on); ++ ++ iisfcon = readl(s5pc1xx_i2s.regs + S3C64XX_IIS0FIC); ++ iiscon = readl(s5pc1xx_i2s.regs + S3C64XX_IIS0CON); ++ iismod = readl(s5pc1xx_i2s.regs + S3C64XX_IIS0MOD); ++ ++ s3cdbg("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon); ++ ++ if (on) { ++ iiscon |= S3C64XX_IIS0CON_I2SACTIVE; ++ ++ writel(iismod, s5pc1xx_i2s.regs + S3C64XX_IIS0MOD); ++ writel(iisfcon, s5pc1xx_i2s.regs + S3C64XX_IIS0FIC); ++ writel(iiscon, s5pc1xx_i2s.regs + S3C64XX_IIS0CON); ++ } else { ++ /* note, we have to disable the FIFOs otherwise bad things ++ * seem to happen when the DMA stops. According to the ++ * Samsung supplied kernel, this should allow the DMA ++ * engine and FIFOs to reset. If this isn't allowed, the ++ * DMA engine will simply freeze randomly. ++ */ ++ ++ iiscon &= ~S3C64XX_IIS0CON_I2SACTIVE; ++ iismod &= ~S3C64XX_IIS0MOD_RXMODE; ++ ++ writel(iisfcon, s5pc1xx_i2s.regs + S3C64XX_IIS0FIC); ++ writel(iiscon, s5pc1xx_i2s.regs + S3C64XX_IIS0CON); ++ writel(iismod, s5pc1xx_i2s.regs + S3C64XX_IIS0MOD); ++ ++ } ++ s3cdbg("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon); ++} ++ ++/* ++ * Wait for the LR signal to allow synchronisation to the L/R clock ++ * from the codec. May only be needed for slave mode. ++ */ ++static int s3c24xx_snd_lrsync(void) ++{ ++ u32 iiscon; ++ unsigned long timeout = jiffies + msecs_to_jiffies(5); ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ while (1) { ++ iiscon = readl(s5pc1xx_i2s.regs + S3C64XX_IIS0CON); ++ ++ if (iiscon & S3C64XX_IISCON_LRINDEX) ++ break; ++ ++ if (timeout < jiffies) ++ return -ETIMEDOUT; ++ ++ } ++ ++ return 0; ++} ++ ++/* ++ * Check whether CPU is the master or slave ++ */ ++static inline int s3c24xx_snd_is_clkmaster(void) ++{ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++// writel(readl(s5pc1xx_i2s.regs + S3C64XX_IIS0MOD)|~(S3C64XX_IISMOD_SLAVE),s5pc1xx_i2s.regs + S3C64XX_IIS0MOD); ++ ++// return (readl(s5pc1xx_i2s.regs + S3C64XX_IIS0MOD) & S3C64XX_IISMOD_SLAVE) ? 0:1; ++ return (readl(s5pc1xx_i2s.regs + S3C64XX_IIS0MOD) & S3C64XX_IIS0MOD_IMS_SLAVE) ? 0:1; ++} ++ ++/* ++ * Set S3C24xx I2S DAI format ++ */ ++static int s3c_i2s_v50_set_fmt(struct snd_soc_dai *cpu_dai, ++ unsigned int fmt) ++{ ++ u32 iismod; ++ ++ s3cdbg("Entered %s: fmt = %d\n", __FUNCTION__, fmt); ++ ++ iismod = readl(s5pc1xx_i2s.regs + S3C64XX_IIS0MOD); ++ ++ return 0; ++ ++} ++ ++static int s3c_i2s_v50_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ ++ unsigned long iiscon; ++ unsigned long iismod; ++ unsigned long iisfcon; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ s5pc1xx_i2s.master = 1; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ rtd->dai->cpu_dai->dma_data = &s5pc1xx_i2s_pcm_stereo_out; ++ } else { ++ rtd->dai->cpu_dai->dma_data = &s5pc1xx_i2s_pcm_stereo_in; ++ } ++ ++ /* Working copies of registers */ ++ iiscon = readl(s5pc1xx_i2s.regs + S3C64XX_IIS0CON); ++ iismod = readl(s5pc1xx_i2s.regs + S3C64XX_IIS0MOD); ++ iisfcon = readl(s5pc1xx_i2s.regs + S3C64XX_IIS0FIC); ++ ++ /* is port used by another stream */ ++ if (!(iiscon & S3C64XX_IIS0CON_I2SACTIVE)) { ++ ++ /* Clear BFS field [2:1] */ ++ iismod &= ~(0x3<<1); ++ iismod |= S3C64XX_IIS0MOD_32FS | S3C64XX_IIS0MOD_INTERNAL_CLK; ++ ++ if (!s5pc1xx_i2s.master) ++ iismod |= S3C64XX_IISMOD_SLAVE; ++ else ++ iismod |= S3C64XX_IIS0MOD_IMS_EXTERNAL_MASTER; ++ } ++ ++ iiscon |= S3C64XX_IISCON_FTXURINTEN; ++ iiscon |= S3C64XX_IIS0CON_TXDMACTIVE; ++ iiscon |= S3C64XX_IIS0CON_RXDMACTIVE; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ iismod |= S3C64XX_IIS0MOD_TXMODE; ++ iisfcon |= S3C64XX_IIS_TX_FLUSH; ++ } else { ++ iismod |= S3C64XX_IIS0MOD_RXMODE; ++ iisfcon |= S3C64XX_IIS_RX_FLUSH; ++ } ++ ++ /* Multi channel enable */ ++ iismod &= ~S3C64XX_IIS0MOD_DCE_MASK; ++ switch (params_channels(params)) { ++ case 6: ++ printk("s3c i2s: 5.1channel\n"); ++ iismod |= S3C64XX_IIS0MOD_DCE_SD2; ++ iismod |= S3C64XX_IIS0MOD_DCE_SD2; ++ break; ++ case 4: ++ printk("s3c i2s: 4 channel\n"); ++ iismod |= S3C64XX_IIS0MOD_DCE_SD2; ++ break; ++ case 2: ++ printk("s3c i2s: 2 channel\n"); ++ break; ++ default: ++ printk(KERN_ERR "s3c-i2s-v50: %d channels unsupported\n", ++ params_channels(params)); ++ return -EINVAL; ++ } ++ ++ /* Set the bit rate */ ++ iismod &= ~0x6000; ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S16_LE: ++ iismod &= ~S3C64XX_IIS0MOD_FS_MASK; ++ iismod |= S3C64XX_IIS0MOD_256FS | S3C64XX_IIS0MOD_32FS; ++ iismod &= ~(0x3<<13); ++ iismod |= S3C64XX_IIS0MOD_16BIT; ++ break; ++ case SNDRV_PCM_FORMAT_S8: ++ iismod |= S3C64XX_IIS0MOD_8BIT; ++ break; ++ case SNDRV_PCM_FORMAT_S24_LE: ++ iismod &= ~S3C64XX_IIS0MOD_FS_MASK; ++ iismod |= S3C64XX_IIS0MOD_384FS | S3C64XX_IIS0MOD_48FS; ++ iismod &= ~(0x3<<13); ++ iismod |= S3C64XX_IIS0MOD_24BIT; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ writel(iisfcon, s5pc1xx_i2s.regs + S3C64XX_IIS0FIC); ++ writel(iiscon, s5pc1xx_i2s.regs + S3C64XX_IIS0CON); ++ writel(iismod, s5pc1xx_i2s.regs + S3C64XX_IIS0MOD); ++ ++ // Tx, Rx fifo flush bit clear ++ iisfcon &= ~(S3C64XX_IIS_TX_FLUSH | S3C64XX_IIS_RX_FLUSH); ++ writel(iisfcon, s5pc1xx_i2s.regs + S3C64XX_IIS0FIC); ++ ++ s3cdbg("s3c iis mode: 0x%08x\n", readl(s5pc1xx_i2s.regs + S3C64XX_IIS0MOD)); ++ s3cdbg("s3c: params_channels %d\n", params_channels(params)); ++ s3cdbg("s3c: params_format %d\n", params_format(params)); ++ s3cdbg("s3c: params_subformat %d\n", params_subformat(params)); ++ s3cdbg("s3c: params_period_size %d\n", params_period_size(params)); ++ s3cdbg("s3c: params_period_bytes %d\n", params_period_bytes(params)); ++ s3cdbg("s3c: params_periods %d\n", params_periods(params)); ++ s3cdbg("s3c: params_buffer_size %d\n", params_buffer_size(params)); ++ s3cdbg("s3c: params_buffer_bytes %d\n", params_buffer_bytes(params)); ++// s3cdbg("s3c: params_tick_time %d\n", params_tick_time(params)); ++ s3cdbg("hw_params: IISCON: %lx IISMOD: %lx\n", iiscon, iismod); ++ ++ return 0; ++ ++} ++ ++static int s3c_i2s_v50_trigger(struct snd_pcm_substream *substream, int cmd) ++{ ++ int ret = 0; ++ ++ s3cdbg("Entered %s: cmd = %d\n", __FUNCTION__, cmd); ++ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ if (!s3c24xx_snd_is_clkmaster()) { ++ ret = s3c24xx_snd_lrsync(); ++ if (ret) ++ goto exit_err; ++ } ++ ++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) ++ s5pc1xx_snd_rxctrl(1); ++ else ++ s5pc1xx_snd_txctrl(1); ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) ++ s5pc1xx_snd_rxctrl(0); ++ else ++ s5pc1xx_snd_txctrl(0); ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++exit_err: ++ return ret; ++} ++ ++static void s5pc1xx_i2s_shutdown(struct snd_pcm_substream *substream) ++{ ++ unsigned long iismod, iiscon; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ iismod=readl(s5pc1xx_i2s.regs + S3C64XX_IIS0MOD); ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ iismod &= ~S3C64XX_IIS0MOD_TXMODE; ++ } else { ++ iismod &= ~S3C64XX_IIS0MOD_RXMODE; ++ } ++ ++ writel(iismod, s5pc1xx_i2s.regs + S3C64XX_IIS0MOD); ++ ++ iiscon=readl(s5pc1xx_i2s.regs + S3C64XX_IIS0CON); ++ iiscon &= !S3C64XX_IIS0CON_I2SACTIVE; ++ writel(iiscon, s5pc1xx_i2s.regs + S3C64XX_IIS0CON); ++ ++ /* Clock disable */ ++ /* EPLL disable */ ++ writel(readl(S5P_EPLL_CON)&~(0x1<<31),S5P_EPLL_CON); ++} ++ ++ ++/* ++ * Set S3C24xx Clock source ++ */ ++static int s3c_i2s_v50_set_sysclk(struct snd_soc_dai *cpu_dai, ++ int clk_id, unsigned int freq, int dir) ++{ ++ u32 iismod = readl(s5pc1xx_i2s.regs + S3C64XX_IIS0MOD); ++ ++ s3cdbg("Entered %s : clk_id = %d\n", __FUNCTION__, clk_id); ++ ++ iismod &= ~S3C64XX_IISMOD_MPLL; ++ ++ switch (clk_id) { ++ case S5PC1XX_CLKSRC_PCLK: ++ break; ++ case S5PC1XX_CLKSRC_MPLL: ++ iismod |= S3C64XX_IISMOD_MPLL; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ writel(iismod, s5pc1xx_i2s.regs + S3C64XX_IIS0MOD); ++ return 0; ++} ++ ++/* ++ * Set S3C24xx Clock dividers ++ */ ++static int s3c_i2s_v50_set_clkdiv(struct snd_soc_dai *cpu_dai, ++ int div_id, int div) ++{ ++ u32 reg; ++ ++ s3cdbg("Entered %s : div_id = %d, div = %x\n", __FUNCTION__, div_id, div); ++ ++ switch (div_id) { ++ case S5PC1XX_DIV_MCLK: ++ break; ++ case S5PC1XX_DIV_BCLK: ++ reg = readl(s5pc1xx_i2s.regs + S3C64XX_IIS0MOD) & ~(S3C64XX_IIS0MOD_FS_MASK); ++ writel(reg | div, s5pc1xx_i2s.regs + S3C64XX_IIS0MOD); ++ break; ++ case S5PC1XX_DIV_PRESCALER: ++ if (div) ++ div |= 1 << 15; ++ writel(div, s5pc1xx_i2s.regs + S3C64XX_IIS0PSR); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/* ++ * To avoid duplicating clock code, allow machine driver to ++ * get the clockrate from here. ++ */ ++u32 s3c_i2s_v50_get_clockrate(void) ++{ ++ return clk_get_rate(s5pc1xx_i2s.iis_clk); ++} ++EXPORT_SYMBOL_GPL(s3c_i2s_v50_get_clockrate); ++ ++static irqreturn_t s3c_iis_irq(int irqno, void *dev_id) ++{ ++ u32 iiscon; ++ ++ iiscon = readl(s5pc1xx_i2s.regs + S3C64XX_IIS0CON); ++ if((1<<17) & iiscon) { ++ iiscon &= ~(1<<16); ++ iiscon |= (1<<17); ++ writel(iiscon, s5pc1xx_i2s.regs + S3C64XX_IIS0CON); ++ printk("underrun interrupt IISCON = 0x%08x\n", readl(s5pc1xx_i2s.regs + S3C64XX_IIS0CON)); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int s3c_i2s_v50_probe(struct platform_device *pdev, ++ struct snd_soc_dai *dai) ++{ ++ int ret; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ s5pc1xx_i2s.regs = ioremap(S3C_PA_IIS, 0x100); ++ if (s5pc1xx_i2s.regs == NULL) ++ return -ENXIO; ++ ++ s5pc1xx_i2s.iis_clk=clk_get(&pdev->dev, "iis"); ++ if (s5pc1xx_i2s.iis_clk == NULL) { ++ printk("failed to get iis_clock\n"); ++ iounmap(s5pc1xx_i2s.regs); ++ return -ENODEV; ++ } ++ clk_enable(s5pc1xx_i2s.iis_clk); ++ ++ ret = request_irq(IRQ_I2S0, s3c_iis_irq, 0, ++ "s3c-i2s-v50", pdev); ++ if (ret < 0) { ++ printk("fail to claim i2s irq , ret = %d\n", ret); ++ return -ENODEV; ++ } ++ ++ s3cdbg("IIS Reset!\n"); ++// writel(readl(s5pc1xx_i2s.regs + S3C64XX_IIS0CON)&~(0x1<<31),(s5pc1xx_i2s.regs + S3C64XX_IIS0CON)); ++// msleep(100); ++ writel(readl(s5pc1xx_i2s.regs + S3C64XX_IIS0CON)|(0x1<<31),(s5pc1xx_i2s.regs + S3C64XX_IIS0CON)); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int s3c_i2s_v50_suspend(struct platform_device *dev, ++ struct snd_soc_dai *dai) ++{ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ return 0; ++} ++ ++static int s3c_i2s_v50_resume(struct platform_device *pdev, ++ struct snd_soc_dai *dai) ++{ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ return 0; ++} ++ ++#else ++#define s3c_i2s_v50_suspend NULL ++#define s3c_i2s_v50_resume NULL ++#endif ++ ++ ++#define S5PC1XX_I2S_RATES \ ++ (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \ ++ SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ ++ SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) ++ ++struct snd_soc_dai s3c_i2s_v50_dai = { ++ .name = "s3c-i2s-v50", ++ .id = 0, ++ .type = SND_SOC_DAI_I2S, ++ .probe = s3c_i2s_v50_probe, ++ .suspend = s3c_i2s_v50_suspend, ++ .resume = s3c_i2s_v50_resume, ++ .playback = { ++ .channels_min = 2, ++ .channels_max = 6, ++ .rates = S5PC1XX_I2S_RATES, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,}, ++ .capture = { ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = S5PC1XX_I2S_RATES, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,}, ++ .ops = { ++ .shutdown = s5pc1xx_i2s_shutdown, ++ .trigger = s3c_i2s_v50_trigger, ++ .hw_params = s3c_i2s_v50_hw_params,}, ++ .dai_ops = { ++ .set_fmt = s3c_i2s_v50_set_fmt, ++ .set_clkdiv = s3c_i2s_v50_set_clkdiv, ++ .set_sysclk = s3c_i2s_v50_set_sysclk, ++ }, ++}; ++EXPORT_SYMBOL_GPL(s3c_i2s_v50_dai); ++ ++/* Module information */ ++MODULE_AUTHOR("Ben Dooks, "); ++MODULE_DESCRIPTION("s3c24xx I2S SoC Interface"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s5pc1xx/s5pc1xx-ac97.c linux-2.6.28.6/sound/soc/s5pc1xx/s5pc1xx-ac97.c +--- linux-2.6.28/sound/soc/s5pc1xx/s5pc1xx-ac97.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s5pc1xx/s5pc1xx-ac97.c 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,426 @@ ++/* ++ * s5pc1xx-ac97.c -- ALSA Soc Audio Layer ++ * ++ * Copyright (C) 2007, Ryu Euiyoul ++ * Copyright (C) 2008 Samsung Electronics Co. Ltd. ++ * ++ * ++ * (c) 2007 Wolfson Microelectronics PLC. ++ * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com ++ * ++ * Copyright (C) 2007, Ryu Euiyoul ++ * All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * Revision history ++ * 21st Mar 2007 Initial Version ++ * 20th Sep 2007 Apply at s3c6400 ++ * 16th Mar 2009 Ported for s5pc100 ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "s5pc1xx-pcm.h" ++#include "s5pc1xx-ac97.h" ++ ++#ifdef CONFIG_SND_DEBUG ++#define s3cdbg(x...) printk(x) ++#else ++#define s3cdbg(x...) ++#endif ++ ++extern struct clk *clk_get(struct device *dev, const char *id); ++extern int clk_enable(struct clk *clk); ++extern void clk_disable(struct clk *clk); ++ ++struct s3c24xx_ac97_info { ++ void __iomem *regs; ++ struct clk *ac97_clk; ++}; ++static struct s3c24xx_ac97_info s3c24xx_ac97; ++ ++static unsigned int codec_ready; ++static DEFINE_MUTEX(ac97_mutex); ++static DECLARE_WAIT_QUEUE_HEAD(gsr_wq); ++ ++static unsigned short s3c6400_ac97_read(struct snd_ac97 *ac97, ++ unsigned short reg) ++{ ++ unsigned int ac_glbctrl; ++ unsigned int ac_codec_cmd; ++ unsigned int stat, addr, data; ++ ++ s3cdbg("Entered %s: reg=0x%x\n", __FUNCTION__, reg); ++ ++ mutex_lock(&ac97_mutex); ++ ++ codec_ready = S3C_AC97_GLBSTAT_CODECREADY; ++ ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg); ++ writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD); ++ ++ udelay(1000); ++ ++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ ++ stat = readl(s3c24xx_ac97.regs + S3C_AC97_STAT); ++ addr = (stat >> 16) & 0x7f; ++ data = (stat & 0xffff); ++ ++ wait_event_timeout(gsr_wq,addr==reg,1); ++ if(addr!=reg){ ++ printk(KERN_ERR"AC97: read error (ac97_reg=%x addr=%x)\n", reg, addr); ++ printk(KERN_ERR"Check audio codec jumpper settings\n\n"); ++ goto out; ++ } ++ ++out: mutex_unlock(&ac97_mutex); ++ return (unsigned short)data; ++} ++ ++static void s3c6400_ac97_write(struct snd_ac97 *ac97, unsigned short reg, ++ unsigned short val) ++{ ++ unsigned int ac_glbctrl; ++ unsigned int ac_codec_cmd; ++ unsigned int stat, data; ++ ++ s3cdbg("Entered %s: reg=0x%x, val=0x%x\n", __FUNCTION__,reg,val); ++ ++ mutex_lock(&ac97_mutex); ++ ++ codec_ready = S3C_AC97_GLBSTAT_CODECREADY; ++ ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val); ++ writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD); ++ ++ udelay(50); ++ ++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ ++ ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ; ++ writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD); ++ ++ stat = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD); ++ data = (stat & 0xffff); ++ ++ wait_event_timeout(gsr_wq,data==val,1); ++ if(data!=val){ ++ printk("%s: write error (ac97_val=%x data=%x)\n", ++ __FUNCTION__, val, data); ++ } ++ ++ mutex_unlock(&ac97_mutex); ++} ++ ++static void s3c6400_ac97_warm_reset(struct snd_ac97 *ac97) ++{ ++ unsigned int ac_glbctrl; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ ac_glbctrl |= S3C_AC97_GLBCTRL_WARMRESET; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ msleep(1); ++ ++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_WARMRESET; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ msleep(1); ++ ++ ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ msleep(1); ++ ++ ac_glbctrl = S3C_AC97_GLBCTRL_TRANSFERDATAENABLE; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ msleep(1); ++ ++ ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA | ++ S3C_AC97_GLBCTRL_PCMINTM_DMA | S3C_AC97_GLBCTRL_MICINTM_DMA; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ ++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ ac_glbctrl |= S3C_AC97_GLBCTRL_ACLINKON; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ udelay(1000); ++} ++ ++static void s3c6400_ac97_cold_reset(struct snd_ac97 *ac97) ++{ ++ unsigned int ac_glbctrl; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ msleep(1); ++ ++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_COLDRESET; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ msleep(1); ++ ++ ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ msleep(1); ++ ++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_COLDRESET; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ msleep(1); ++} ++ ++static irqreturn_t s3c6400_ac97_irq(int irq, void *dev_id) ++{ ++ int status; ++ unsigned int ac_glbctrl, ac_glbstat; ++ ++ ac_glbstat = readl(s3c24xx_ac97.regs + S3C_AC97_GLBSTAT); ++ ++ s3cdbg("Entered %s: AC_GLBSTAT = 0x%x\n", __FUNCTION__, ac_glbstat); ++ ++ status = ac_glbstat & codec_ready; ++ ++ ++ if (status) { ++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE; ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ wake_up(&gsr_wq); ++ } ++ return IRQ_HANDLED; ++} ++ ++struct snd_ac97_bus_ops soc_ac97_ops = { ++ .read = s3c6400_ac97_read, ++ .write = s3c6400_ac97_write, ++ .warm_reset = s3c6400_ac97_warm_reset, ++ .reset = s3c6400_ac97_cold_reset, ++}; ++ ++static struct s3c2410_dma_client s3c6400_dma_client_out = { ++ .name = "AC97 PCM Stereo out" ++}; ++ ++static struct s3c24xx_pcm_dma_params s3c6400_ac97_pcm_stereo_out = { ++ .client = &s3c6400_dma_client_out, ++ .channel = DMACH_AC97_PCM_OUT, ++ .dma_addr = S5PC1XX_PA_AC97 + S3C_AC97_PCM_DATA, ++ .dma_size = 4, ++}; ++ ++#ifdef CONFIG_SOUND_S5PC100_WM9713_INPUT_STREAM_MIC ++static struct s3c2410_dma_client s3c6400_dma_client_micin = { ++ .name = "AC97 Mic Mono in" ++}; ++ ++static struct s3c24xx_pcm_dma_params s3c6400_ac97_mic_mono_in = { ++ .client = &s3c6400_dma_client_micin, ++ .channel = DMACH_AC97_MIC_IN, ++ .dma_addr = S5PC1XX_PA_AC97 + S3C_AC97_MIC_DATA, ++ .dma_size = 4, ++}; ++#else /* Input Stream is Line-In */ ++static struct s3c2410_dma_client s3c6400_dma_client_in = { ++ .name = "AC97 PCM Stereo Line in" ++}; ++ ++static struct s3c24xx_pcm_dma_params s3c6400_ac97_pcm_stereo_in = { ++ .client = &s3c6400_dma_client_in, ++ .channel = DMACH_AC97_PCM_IN, ++ .dma_addr = S5PC1XX_PA_AC97 + S3C_AC97_PCM_DATA, ++ .dma_size = 4, ++}; ++#endif ++ ++static int s3c6400_ac97_probe(struct platform_device *pdev) ++{ ++ int ret; ++ unsigned int gpio; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ s3c24xx_ac97.regs = ioremap(S5PC1XX_PA_AC97, 0x100); ++ if (s3c24xx_ac97.regs == NULL) ++ return -ENXIO; ++ ++ s3c24xx_ac97.ac97_clk = clk_get(&pdev->dev, "ac97"); ++ if (s3c24xx_ac97.ac97_clk == NULL) { ++ printk(KERN_ERR "s3c6400-ac97 failed to get ac97_clock\n"); ++ iounmap(s3c24xx_ac97.regs); ++ return -ENODEV; ++ } ++ clk_enable(s3c24xx_ac97.ac97_clk); ++ ++ for (gpio = S5PC1XX_GPC(0); gpio <= S5PC1XX_GPC(4); gpio++) { ++ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4)); ++ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); ++ } ++ ++ ret = request_irq(IRQ_AC97, s3c6400_ac97_irq, ++ IRQF_DISABLED, "AC97", NULL); ++ if (ret < 0) { ++ printk(KERN_ERR "s3c24xx-ac97: interrupt request failed.\n"); ++ clk_disable(s3c24xx_ac97.ac97_clk); ++ clk_put(s3c24xx_ac97.ac97_clk); ++ iounmap(s3c24xx_ac97.regs); ++ } ++ ++ return ret; ++} ++ ++static void s3c6400_ac97_remove(struct platform_device *pdev) ++{ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ free_irq(IRQ_AC97, NULL); ++ clk_disable(s3c24xx_ac97.ac97_clk); ++ clk_put(s3c24xx_ac97.ac97_clk); ++ iounmap(s3c24xx_ac97.regs); ++} ++ ++static int s3c6400_ac97_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ cpu_dai->dma_data = &s3c6400_ac97_pcm_stereo_out; ++ else ++#ifdef CONFIG_SOUND_S5PC100_WM9713_INPUT_STREAM_MIC ++ cpu_dai->dma_data = &s3c6400_ac97_mic_mono_in; ++#else /* Input Stream is LINE-IN */ ++ cpu_dai->dma_data = &s3c6400_ac97_pcm_stereo_in; ++#endif ++ ++ ++ return 0; ++} ++ ++static int s3c6400_ac97_hifi_prepare(struct snd_pcm_substream *substream) ++{ ++ s3c6400_ac97_write(0, 0x26, 0x0); ++ s3c6400_ac97_write(0, 0x0c, 0x0808); ++ s3c6400_ac97_write(0, 0x3c, 0xf803); ++ s3c6400_ac97_write(0, 0x3e, 0xb990); ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ s3c6400_ac97_write(0, 0x02, 0x8080); ++ s3c6400_ac97_write(0, 0x04, 0x0606); ++ s3c6400_ac97_write(0, 0x1c, 0x00aa); ++ } ++ else ++ { ++ s3c6400_ac97_write(0, 0x12, 0x0f0f); ++#ifdef CONFIG_SOUND_S5PC100_WM9713_INPUT_STREAM_MIC ++ s3c6400_ac97_write(0, 0x5c, 0x2); ++ s3c6400_ac97_write(0, 0x10, 0x68); ++ s3c6400_ac97_write(0, 0x14, 0xfe00); ++#else /* Input Stream is LINE-IN */ ++ s3c6400_ac97_write(0, 0x14, 0xd612); ++#endif ++ } ++ ++ return 0; ++} ++ ++ ++static int s3c6400_ac97_trigger(struct snd_pcm_substream *substream, int cmd) ++{ ++ unsigned int ac_glbctrl; ++ ++ s3cdbg("Entered %s: cmd = %d\n", __FUNCTION__, cmd); ++ ++ ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ switch(cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) ++ ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA; ++ else ++ ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA; ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) ++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK; ++ else ++ ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK; ++ break; ++ } ++ writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL); ++ ++ return 0; ++} ++ ++#define s3c6400_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ ++ SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \ ++ SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) ++ ++struct snd_soc_dai s3c6400_ac97_dai[] = { ++{ ++ .name = "s3c64xx-ac97", ++ .id = 0, ++ .type = SND_SOC_DAI_AC97, ++ .probe = s3c6400_ac97_probe, ++ .remove = s3c6400_ac97_remove, ++ .playback = { ++ .stream_name = "AC97 Playback", ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = s3c6400_AC97_RATES, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE,}, ++ .capture = { ++ .stream_name = "AC97 Capture", ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = s3c6400_AC97_RATES, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE,}, ++ .ops = { ++ .hw_params = s3c6400_ac97_hw_params, ++ .prepare = s3c6400_ac97_hifi_prepare, ++ .trigger = s3c6400_ac97_trigger}, ++}, ++}; ++ ++EXPORT_SYMBOL_GPL(s3c6400_ac97_dai); ++EXPORT_SYMBOL_GPL(soc_ac97_ops); ++ ++MODULE_AUTHOR("Samsung"); ++MODULE_DESCRIPTION("AC97 driver for the Samsung S5PC100 chip"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s5pc1xx/s5pc1xx-ac97.h linux-2.6.28.6/sound/soc/s5pc1xx/s5pc1xx-ac97.h +--- linux-2.6.28/sound/soc/s5pc1xx/s5pc1xx-ac97.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s5pc1xx/s5pc1xx-ac97.h 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,25 @@ ++/* ++ * s3c24xx-ac97.c -- ALSA Soc Audio Layer ++ * ++ * (c) 2007 Wolfson Microelectronics PLC. ++ * Author: Graeme Gregory ++ * graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * Revision history ++ * 10th Nov 2006 Initial version. ++ */ ++ ++#ifndef S3C6400AC97_H_ ++#define S3C6400AC97_H_ ++ ++#define AC_CMD_ADDR(x) (x << 16) ++#define AC_CMD_DATA(x) (x & 0xffff) ++ ++extern struct snd_soc_dai s3c6400_ac97_dai[]; ++ ++#endif /*S3C6400AC97_H_*/ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s5pc1xx/s5pc1xx-i2s.h linux-2.6.28.6/sound/soc/s5pc1xx/s5pc1xx-i2s.h +--- linux-2.6.28/sound/soc/s5pc1xx/s5pc1xx-i2s.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s5pc1xx/s5pc1xx-i2s.h 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,37 @@ ++/* ++ * s3c24xx-i2s.c -- ALSA Soc Audio Layer ++ * ++ * Copyright 2005 Wolfson Microelectronics PLC. ++ * Author: Graeme Gregory ++ * graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * Revision history ++ * 10th Nov 2006 Initial version. ++ */ ++ ++#ifndef S5PC1XXI2S_H_ ++#define S5PC1XXI2S_H_ ++ ++/* clock sources */ ++#define S5PC1XX_CLKSRC_PCLK 0 ++#define S5PC1XX_CLKSRC_MPLL 1 ++ ++/* Clock dividers */ ++#define S5PC1XX_DIV_MCLK 0 ++#define S5PC1XX_DIV_BCLK 1 ++#define S5PC1XX_DIV_PRESCALER 2 ++ ++/* prescaler */ ++#define S5PC1XX_PRESCALE(a,b) \ ++ (((a - 1) << S3C_IISPSR_INTSHIFT) | ((b - 1) << S3C_IISPSR_INTSHIFT)) ++ ++u32 s5pc1xx_i2s_get_clockrate(void); ++ ++extern struct snd_soc_dai s3c_i2s_v50_dai; ++ ++#endif /*S5PC1XXI2S_H_*/ +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s5pc1xx/s5pc1xx-pcm.c linux-2.6.28.6/sound/soc/s5pc1xx/s5pc1xx-pcm.c +--- linux-2.6.28/sound/soc/s5pc1xx/s5pc1xx-pcm.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s5pc1xx/s5pc1xx-pcm.c 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,541 @@ ++/* ++ * s3c-pcm.c -- ALSA Soc Audio Layer ++ * ++ * (c) 2006 Wolfson Microelectronics PLC. ++ * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com ++ * ++ * (c) 2004-2005 Simtec Electronics ++ * http://armlinux.simtec.co.uk/ ++ * Ben Dooks ++ * Ryu Euiyoul ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * Revision history ++ * 11th Dec 2006 Merged with Simtec driver ++ * 10th Nov 2006 Initial version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++//#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "s5pc1xx-pcm.h" ++ ++#if defined CONFIG_SND_S3C6400_SOC_AC97 ++#define MAIN_DMA_CH 1 ++#else /*S3C6400 I2S */ ++#define MAIN_DMA_CH 0 ++#endif ++ ++#ifdef CONFIG_SND_DEBUG ++#define s3cdbg(x...) printk(x) ++#else ++#define s3cdbg(x...) ++#endif ++ ++static const struct snd_pcm_hardware s3c24xx_pcm_hardware = { ++ .info = SNDRV_PCM_INFO_INTERLEAVED | ++ SNDRV_PCM_INFO_BLOCK_TRANSFER | ++ SNDRV_PCM_INFO_MMAP | ++ SNDRV_PCM_INFO_MMAP_VALID, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE | ++ SNDRV_PCM_FMTBIT_U16_LE | ++ SNDRV_PCM_FMTBIT_U8 | ++ SNDRV_PCM_FMTBIT_S24_LE | ++ SNDRV_PCM_FMTBIT_S8, ++ .channels_min = 2, ++ .channels_max = 2, ++ .buffer_bytes_max = 128*1024, ++ .period_bytes_min = PAGE_SIZE, ++ .period_bytes_max = PAGE_SIZE*2, ++ .periods_min = 2, ++ .periods_max = 128, ++ .fifo_size = 32, ++}; ++ ++struct s3c24xx_runtime_data { ++ spinlock_t lock; ++ int state; ++ unsigned int dma_loaded; ++ unsigned int dma_limit; ++ unsigned int dma_period; ++ dma_addr_t dma_start; ++ dma_addr_t dma_pos; ++ dma_addr_t dma_end; ++ struct s3c24xx_pcm_dma_params *params; ++}; ++ ++/* s3c24xx_pcm_enqueue ++ * ++ * place a dma buffer onto the queue for the dma system ++ * to handle. ++*/ ++static void s3c24xx_pcm_enqueue(struct snd_pcm_substream *substream) ++{ ++ struct s3c24xx_runtime_data *prtd = substream->runtime->private_data; ++ dma_addr_t pos = prtd->dma_pos; ++ int ret; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ while (prtd->dma_loaded < prtd->dma_limit) { ++ unsigned long len = prtd->dma_period; ++ ++ s3cdbg("dma_loaded: %d\n",prtd->dma_loaded); ++ ++ if ((pos + len) > prtd->dma_end) { ++ len = prtd->dma_end - pos; ++ s3cdbg(KERN_DEBUG "%s: corrected dma len %ld\n", ++ __FUNCTION__, len); ++ } ++ ++ ret = s3c2410_dma_enqueue(prtd->params->channel, ++ substream, pos, len); ++ ++ if (ret == 0) { ++ prtd->dma_loaded++; ++ pos += prtd->dma_period; ++ if (pos >= prtd->dma_end) ++ pos = prtd->dma_start; ++ } else ++ break; ++ } ++ ++ prtd->dma_pos = pos; ++} ++ ++static void s3c24xx_audio_buffdone(struct s3c2410_dma_chan *channel, ++ void *dev_id, int size, ++ enum s3c2410_dma_buffresult result) ++{ ++ struct snd_pcm_substream *substream = dev_id; ++ struct s3c24xx_runtime_data *prtd; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ if (result == S3C2410_RES_ABORT || result == S3C2410_RES_ERR) ++ return; ++ else { ++ prtd = substream->runtime->private_data; ++ ++ if (substream) ++ snd_pcm_period_elapsed(substream); ++ else ++ return; ++ ++ spin_lock(&prtd->lock); ++ if (prtd->state & ST_RUNNING) { ++ prtd->dma_loaded--; ++ s3c24xx_pcm_enqueue(substream); ++ } ++ ++ spin_unlock(&prtd->lock); ++ } ++#if 0 ++ struct snd_pcm_substream *substream = dev_id; ++ struct s3c24xx_runtime_data *prtd = substream->runtime->private_data; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ if (result == S3C2410_RES_ABORT || result == S3C2410_RES_ERR) ++ return; ++ ++ snd_pcm_period_elapsed(substream); ++ ++ spin_lock(&prtd->lock); ++ if (prtd->state & ST_RUNNING) { ++ prtd->dma_loaded--; ++ s3c24xx_pcm_enqueue(substream); ++ } ++ ++ spin_unlock(&prtd->lock); ++#endif ++} ++ ++static int s3c24xx_pcm_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct s3c24xx_runtime_data *prtd = runtime->private_data; ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct s3c24xx_pcm_dma_params *dma = rtd->dai->cpu_dai->dma_data; ++ unsigned long totbytes = params_buffer_bytes(params); ++ int ret=0; ++ ++ s3cdbg("Entered %s, params = %p \n", __FUNCTION__, prtd->params); ++ ++ /* return if this is a bufferless transfer e.g. ++ * codec <--> BT codec or GSM modem -- lg FIXME */ ++ if (!dma) ++ return 0; ++ ++ /* this may get called several times by oss emulation ++ * with different params */ ++ if (prtd->params == NULL) { ++ prtd->params = dma; ++ s3cdbg("params %p, client %p, channel %d\n", prtd->params, ++ prtd->params->client, prtd->params->channel); ++ ++ ++ /* prepare DMA */ ++ ret = s3c2410_dma_request(prtd->params->channel, ++ prtd->params->client, NULL); ++ ++ if (ret) { ++ printk(KERN_ERR "failed to get dma channel\n"); ++ return ret; ++ } ++ } else if (prtd->params != dma) { ++ s3c2410_dma_free(prtd->params->channel, prtd->params->client); ++ prtd->params = dma; ++ s3cdbg("params %p, client %p, channel %d\n", prtd->params, ++ prtd->params->client, prtd->params->channel); ++ ++ ++ /* prepare DMA */ ++ ret = s3c2410_dma_request(prtd->params->channel, ++ prtd->params->client, NULL); ++ ++ if (ret) { ++ printk(KERN_ERR "failed to get dma channel\n"); ++ return ret; ++ } ++ } ++ ++ /* channel needs configuring for mem=>device, increment memory addr, ++ * sync to pclk, half-word transfers to the IIS-FIFO. */ ++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410) && !defined(CONFIG_CPU_S5PC100) ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ s3c2410_dma_devconfig(prtd->params->channel, ++ S3C2410_DMASRC_MEM, S3C2410_DISRCC_INC | ++ S3C2410_DISRCC_APB, prtd->params->dma_addr); ++ ++ s3c2410_dma_config(prtd->params->channel, ++ prtd->params->dma_size, ++ S3C2410_DCON_SYNC_PCLK | ++ S3C2410_DCON_HANDSHAKE); ++ } else { ++ s3c2410_dma_config(prtd->params->channel, ++ prtd->params->dma_size, ++ S3C2410_DCON_HANDSHAKE | ++ S3C2410_DCON_SYNC_PCLK); ++ ++ s3c2410_dma_devconfig(prtd->params->channel, ++ S3C2410_DMASRC_HW, 0x3, ++ prtd->params->dma_addr); ++ } ++ ++#else ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ s3c2410_dma_devconfig(prtd->params->channel, ++ S3C2410_DMASRC_MEM, 0, ++ prtd->params->dma_addr); ++ ++ s3c2410_dma_config(prtd->params->channel, ++ prtd->params->dma_size, 0); ++ } else { ++ s3c2410_dma_devconfig(prtd->params->channel, ++ S3C2410_DMASRC_HW, 0, ++ prtd->params->dma_addr); ++ ++ s3c2410_dma_config(prtd->params->channel, ++ prtd->params->dma_size, 0); ++ } ++#endif ++ ++ s3c2410_dma_set_buffdone_fn(prtd->params->channel, ++ s3c24xx_audio_buffdone); ++ ++ snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); ++ ++ runtime->dma_bytes = totbytes; ++ ++ spin_lock_irq(&prtd->lock); ++ prtd->dma_loaded = 0; ++ prtd->dma_limit = runtime->hw.periods_min; ++ prtd->dma_period = params_period_bytes(params); ++ prtd->dma_start = runtime->dma_addr; ++ prtd->dma_pos = prtd->dma_start; ++ prtd->dma_end = prtd->dma_start + totbytes; ++ spin_unlock_irq(&prtd->lock); ++ ++ s3cdbg("Entered %s, line %d \n", __FUNCTION__, __LINE__); ++ return 0; ++} ++ ++static int s3c24xx_pcm_hw_free(struct snd_pcm_substream *substream) ++{ ++ struct s3c24xx_runtime_data *prtd = substream->runtime->private_data; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ /* TODO - do we need to ensure DMA flushed */ ++ snd_pcm_set_runtime_buffer(substream, NULL); ++ ++ if (prtd->params) { ++ s3c2410_dma_free(prtd->params->channel, prtd->params->client); ++ prtd->params = NULL; ++ } ++ ++ return 0; ++} ++ ++static int s3c24xx_pcm_prepare(struct snd_pcm_substream *substream) ++{ ++ struct s3c24xx_runtime_data *prtd = substream->runtime->private_data; ++ int ret = 0; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++#if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410) ++ /* return if this is a bufferless transfer e.g. ++ * codec <--> BT codec or GSM modem -- lg FIXME */ ++ if (!prtd->params) ++ return 0; ++#endif ++ ++ /* flush the DMA channel */ ++ s3c2410_dma_ctrl(prtd->params->channel, S3C2410_DMAOP_FLUSH); ++ ++ prtd->dma_loaded = 0; ++ ++ prtd->dma_pos = prtd->dma_start; ++ ++ /* enqueue dma buffers */ ++ s3c24xx_pcm_enqueue(substream); ++ ++ return ret; ++} ++ ++static int s3c24xx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) ++{ ++ struct s3c24xx_runtime_data *prtd = substream->runtime->private_data; ++ int ret = 0; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ spin_lock(&prtd->lock); ++ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ prtd->state |= ST_RUNNING; ++ s3c2410_dma_ctrl(prtd->params->channel, S3C2410_DMAOP_START); ++ break; ++ ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ++ prtd->state &= ~ST_RUNNING; ++ s3c2410_dma_ctrl(prtd->params->channel, S3C2410_DMAOP_STOP); ++ break; ++ ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ spin_unlock(&prtd->lock); ++ ++ return ret; ++} ++ ++static snd_pcm_uframes_t ++ s3c24xx_pcm_pointer(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct s3c24xx_runtime_data *prtd = runtime->private_data; ++ unsigned long res; ++ dma_addr_t src, dst; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ spin_lock(&prtd->lock); ++ ++ s3c2410_dma_getposition(prtd->params->channel, &src, &dst); ++ ++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) ++ res = dst - prtd->dma_start; ++ else ++ res = src - prtd->dma_start; ++ ++ spin_unlock(&prtd->lock); ++ ++ s3cdbg("Pointer %x %x\n",src,dst); ++ ++ /* we seem to be getting the odd error from the pcm library due ++ * to out-of-bounds pointers. this is maybe due to the dma engine ++ * not having loaded the new values for the channel before being ++ * callled... (todo - fix ) ++ */ ++ ++ if (res >= snd_pcm_lib_buffer_bytes(substream)) { ++ if (res == snd_pcm_lib_buffer_bytes(substream)) ++ res = 0; ++ } ++ ++ return bytes_to_frames(substream->runtime, res); ++} ++ ++static int s3c24xx_pcm_open(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct s3c24xx_runtime_data *prtd; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ snd_soc_set_runtime_hwparams(substream, &s3c24xx_pcm_hardware); ++ ++ prtd = kzalloc(sizeof(struct s3c24xx_runtime_data), GFP_KERNEL); ++ if (prtd == NULL) ++ return -ENOMEM; ++ ++ spin_lock_init(&prtd->lock); ++ ++ runtime->private_data = prtd; ++ return 0; ++} ++ ++static int s3c24xx_pcm_close(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct s3c24xx_runtime_data *prtd = runtime->private_data; ++ ++ s3cdbg("Entered %s, prtd = %p\n", __FUNCTION__, prtd); ++ ++ if (prtd) ++ kfree(prtd); ++ else ++ printk("s3c24xx_pcm_close called with prtd == NULL\n"); ++ ++ return 0; ++} ++ ++static int s3c24xx_pcm_mmap(struct snd_pcm_substream *substream, ++ struct vm_area_struct *vma) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ return dma_mmap_writecombine(substream->pcm->card->dev, vma, ++ runtime->dma_area, ++ runtime->dma_addr, ++ runtime->dma_bytes); ++} ++ ++static struct snd_pcm_ops s3c24xx_pcm_ops = { ++ .open = s3c24xx_pcm_open, ++ .close = s3c24xx_pcm_close, ++ .ioctl = snd_pcm_lib_ioctl, ++ .hw_params = s3c24xx_pcm_hw_params, ++ .hw_free = s3c24xx_pcm_hw_free, ++ .prepare = s3c24xx_pcm_prepare, ++ .trigger = s3c24xx_pcm_trigger, ++ .pointer = s3c24xx_pcm_pointer, ++ .mmap = s3c24xx_pcm_mmap, ++}; ++ ++static int s3c24xx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream) ++{ ++ struct snd_pcm_substream *substream = pcm->streams[stream].substream; ++ struct snd_dma_buffer *buf = &substream->dma_buffer; ++ size_t size = s3c24xx_pcm_hardware.buffer_bytes_max; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ buf->dev.type = SNDRV_DMA_TYPE_DEV; ++ buf->dev.dev = pcm->card->dev; ++ buf->private_data = NULL; ++ buf->area = dma_alloc_writecombine(pcm->card->dev, size, ++ &buf->addr, GFP_KERNEL); ++ if (!buf->area) ++ return -ENOMEM; ++ buf->bytes = size; ++ return 0; ++} ++ ++static void s3c24xx_pcm_free_dma_buffers(struct snd_pcm *pcm) ++{ ++ struct snd_pcm_substream *substream; ++ struct snd_dma_buffer *buf; ++ int stream; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ for (stream = 0; stream < 2; stream++) { ++ substream = pcm->streams[stream].substream; ++ if (!substream) ++ continue; ++ ++ buf = &substream->dma_buffer; ++ if (!buf->area) ++ continue; ++ ++ dma_free_writecombine(pcm->card->dev, buf->bytes, ++ buf->area, buf->addr); ++ buf->area = NULL; ++ } ++} ++ ++static u64 s3c24xx_pcm_dmamask = DMA_32BIT_MASK; ++ ++static int s3c24xx_pcm_new(struct snd_card *card, ++ struct snd_soc_dai *dai, struct snd_pcm *pcm) ++{ ++ int ret = 0; ++ ++ s3cdbg("Entered %s\n", __FUNCTION__); ++ ++ if (!card->dev->dma_mask) ++ card->dev->dma_mask = &s3c24xx_pcm_dmamask; ++ if (!card->dev->coherent_dma_mask) ++ card->dev->coherent_dma_mask = 0xffffffff; ++ ++ if (dai->playback.channels_min) { ++ ret = s3c24xx_pcm_preallocate_dma_buffer(pcm, ++ SNDRV_PCM_STREAM_PLAYBACK); ++ if (ret) ++ goto out; ++ } ++ ++ if (dai->capture.channels_min) { ++ ret = s3c24xx_pcm_preallocate_dma_buffer(pcm, ++ SNDRV_PCM_STREAM_CAPTURE); ++ if (ret) ++ goto out; ++ } ++ out: ++ return ret; ++} ++ ++struct snd_soc_platform s3c24xx_soc_platform = { ++ .name = "s3c24xx-audio", ++ .pcm_ops = &s3c24xx_pcm_ops, ++ .pcm_new = s3c24xx_pcm_new, ++ .pcm_free = s3c24xx_pcm_free_dma_buffers, ++}; ++ ++EXPORT_SYMBOL_GPL(s3c24xx_soc_platform); ++ ++MODULE_AUTHOR("Ben Dooks, "); ++MODULE_DESCRIPTION("Samsung S3C24XX PCM DMA module"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s5pc1xx/s5pc1xx-pcm.h linux-2.6.28.6/sound/soc/s5pc1xx/s5pc1xx-pcm.h +--- linux-2.6.28/sound/soc/s5pc1xx/s5pc1xx-pcm.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s5pc1xx/s5pc1xx-pcm.h 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,40 @@ ++/* ++ * s3c24xx-pcm.h -- ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * ALSA PCM interface for the Samsung S3C24xx CPU ++ */ ++ ++#ifndef _S3C24XX_PCM_H ++#define _S3C24XX_PCM_H ++ ++#define ST_RUNNING (1<<0) ++#define ST_OPENED (1<<1) ++ ++struct s3c24xx_pcm_dma_params { ++ struct s3c2410_dma_client *client; /* stream identifier */ ++ int channel; /* Channel ID */ ++ dma_addr_t dma_addr; ++ int dma_size; /* Size of the DMA transfer */ ++}; ++ ++#define S3C24XX_DAI_I2S 0 ++ ++#if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410) ++#define S3CPCM_DCON 0 ++#define S3CPCM_HWCFG 0 ++#else ++//#include ++#define S3CPCM_DCON S3C2410_DCON_SYNC_PCLK|S3C2410_DCON_HANDSHAKE ++#define S3CPCM_HWCFG S3C2410_DISRCC_INC|S3C2410_DISRCC_APB ++#endif ++ ++/* platform data */ ++extern struct snd_soc_platform s3c24xx_soc_platform; ++extern struct snd_ac97_bus_ops s3c24xx_ac97_ops; ++ ++#endif +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s5pc1xx/smdkc100_wm8580.c linux-2.6.28.6/sound/soc/s5pc1xx/smdkc100_wm8580.c +--- linux-2.6.28/sound/soc/s5pc1xx/smdkc100_wm8580.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s5pc1xx/smdkc100_wm8580.c 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,339 @@ ++/* ++ * smdk6400_wm8580.c ++ * ++ * Copyright 2007, 2008 Wolfson Microelectronics PLC. ++ * ++ * Copyright (C) 2007, Ryu Euiyoul ++ * ++ * Copyright (C) 2008, SungJun Bae ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "s5pc1xx-i2s.h" ++#include "s5pc1xx-pcm.h" ++ ++#include "../codecs/wm8580.h" ++ ++#ifdef CONFIG_SND_DEBUG ++#define s3cdbg(x...) printk(x) ++#else ++#define s3cdbg(x...) ++#endif ++ ++extern void msleep(unsigned int msecs); ++ ++static int smdkc100_hifi_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ //struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai; ++ struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; ++ unsigned int pll_out = 0; /*bclk = 0; */ ++ int ret = 0; ++ unsigned int prescaler; ++ u32 *iiscon; ++ ++ s3cdbg("Entered %s, rate = %d\n", __FUNCTION__, params_rate(params)); ++ ++ iiscon = ioremap(S3C_PA_IIS, 0x100) + S3C64XX_IIS0CON; ++ ++ writel(readl(iiscon)&~(0x1<<31),iiscon); ++ msleep(100); ++ writel(readl(iiscon)|(0x1<<31),iiscon); ++ ++ //writel(readl(S5P_CLK_SRC0)|S5P_CLKSRC0_EPLL_MASK,S5P_CLK_SRC0); ++ s3cdbg("CLK_SRC0 : %x\n",readl(S5P_CLK_SRC0)); ++ ++ //writel(readl(S5P_CLK_SRC3)|(0x0<<12)|(0x0<<24)|(0x0<<4),S5P_CLK_SRC3); ++ //writel(readl(S5P_CLK_SRC3)|(0x2<<8),S5P_CLK_SRC3); ++ s3cdbg("MUX Audio 0: %x\n",readl(S5P_CLK_SRC3)); ++ ++ writel(readl(S5P_CLK_OUT)|(0x2<<12),S5P_CLK_OUT); ++ s3cdbg("CLK OUT : %x\n",readl(S5P_CLK_OUT)); ++ ++ writel(readl(S5P_CLKGATE_D20)|S5P_CLKGATE_D20_HCLKD2|S5P_CLKGATE_D20_I2SD2,S5P_CLKGATE_D20); ++ s3cdbg("HCLKD2 Gate : %x\n",readl(S5P_CLKGATE_D20)); ++ ++ writel(readl(S5P_SCLKGATE1)|S5P_CLKGATE_SCLK1_AUDIO0,S5P_SCLKGATE1); ++ s3cdbg("S5P_SCLKGATE1 : %x\n",readl(S5P_SCLKGATE1)); ++ ++ writel(readl(S5P_CLKGATE_D15)|(1<<0),S5P_CLKGATE_D15); ++ s3cdbg("GATE D1_5 : %x\n",readl(S5P_CLKGATE_D15)); ++ ++ writel(readl(S5P_EPLL_CON)|(0x1<<31),S5P_EPLL_CON); ++ s3cdbg("EPLL CON : %x\n",readl(S5P_EPLL_CON)); ++ ++// writel((readl(S5P_CLK_DIV4)&~(0x07<<12))|(0x0<<12),S5P_CLK_DIV4); ++ ////writel((readl(S5P_CLK_DIV4)&~(0x07<<8))|(0x1<<8),S5P_CLK_DIV4); ++ s3cdbg("DIV4: %x\n",readl(S5P_CLK_DIV4)); ++ ++ /*PCLK & SCLK gating enable*/ ++ ++// writel(readl(S3C_PCLK_GATE)|S3C6410_CLKCON_PCLK_IIS2, S3C_PCLK_GATE); ++// writel(readl(S3C_SCLK_GATE)|S3C_CLKCON_SCLK_AUDIO0, S3C_SCLK_GATE); ++ ++ /*Clear I2S prescaler value [13:8] and disable prescaler*/ ++ /* set prescaler division for sample rate */ ++ ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S5PC1XX_DIV_PRESCALER, 0); ++ ++ if (ret < 0) ++ return ret; ++// ++// ++ s3cdbg("%s: %d , params = %d\n", __FUNCTION__, __LINE__, params_rate(params)); ++ ++ switch (params_rate(params)) { ++ case 8000: ++ case 16000: ++ case 32000: ++ case 64100: ++ /* M=99, P=3, S=3 -- Fout=49.152*/ ++ writel((1<<31)|(99<<16)|(3<<8)|(3<<0) ,S5P_EPLL_CON); ++ break; ++ case 11025: ++ case 22050: ++ case 44100: ++ case 88200: ++ /* M=135, P=3, S=3 -- Fout=67.738 */ ++ writel((1<<31)|(135<<16)|(3<<8)|(3<<0) ,S5P_EPLL_CON); ++ break; ++ case 48000: ++ case 96000: ++ /* M=147, P=3, S=3 -- Fin=12, Fout=73.728; */ ++ writel((1<<31)|(147<<16)|(3<<8)|(3<<0) ,S5P_EPLL_CON); ++ break; ++ default: ++ writel((1<<31)|(128<<16)|(25<<8)|(0<<0) ,S5P_EPLL_CON); ++ break; ++ } ++ ++ switch (params_rate(params)) { ++ case 8000: ++ pll_out = 2048000; ++ prescaler = 8; ++ break; ++ case 11025: ++ pll_out = 2822400; ++ prescaler = 8; ++ break; ++ case 16000: ++ pll_out = 4096000; ++ prescaler = 4; ++ break; ++ case 22050: ++ pll_out = 5644800; ++ prescaler = 4; ++ break; ++ case 32000: ++ pll_out = 8192000; ++ prescaler = 2; ++ break; ++ case 44100: ++ pll_out = 11289600; ++ prescaler = 2; ++ break; ++ case 48000: ++ pll_out = 12288000; ++ prescaler = 2; ++ break; ++ case 88200: ++ pll_out = 22579200; ++ prescaler = 1; ++ break; ++ case 96000: ++ pll_out = 24576000; ++ prescaler = 1; ++ break; ++ default: ++ /* somtimes 32000 rate comes to 96000 ++ default values are same as 32000 */ ++ prescaler = 4; ++ pll_out = 12288000; ++ break; ++ } ++ ++ /* set MCLK division for sample rate */ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S8: ++ case SNDRV_PCM_FORMAT_S16_LE: ++ prescaler *= 3; ++ break; ++ case SNDRV_PCM_FORMAT_S24_3LE: ++ prescaler *= 2; ++ break; ++ case SNDRV_PCM_FORMAT_S24_LE: ++ prescaler *= 2; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ prescaler = prescaler - 1; ++ ++ /* set cpu DAI configuration */ ++ /* ++ ret = cpu_dai->dai_ops.set_fmt(cpu_dai, ++ SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBS_CFS); ++ if (ret < 0) ++ return ret; ++ */ ++ ++ ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S5PC1XX_DIV_BCLK, ++ S3C64XX_IIS0MOD_256FS); ++ if (ret < 0) ++ return ret; ++ ++ /* set prescaler division for sample rate */ ++ ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S5PC1XX_DIV_PRESCALER, ++ (prescaler << 0x8)); ++ if (ret < 0) ++ return ret; ++ ++ return 0; ++} ++ ++/* ++ * WM8580 HiFi DAI opserations. ++ */ ++static struct snd_soc_ops smdkc100_hifi_ops = { ++ .hw_params = smdkc100_hifi_hw_params, ++}; ++ ++static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = { ++ SND_SOC_DAPM_LINE("I2S Front Jack", NULL), ++ SND_SOC_DAPM_LINE("I2S Center Jack", NULL), ++ SND_SOC_DAPM_LINE("I2S Rear Jack", NULL), ++ SND_SOC_DAPM_LINE("Line In Jack", NULL), ++}; ++ ++/* example machine audio_mapnections */ ++static const struct snd_soc_dapm_route audio_map[] = { ++ ++ { "I2S Front Jack", NULL, "VOUT1L" }, ++ { "I2S Front Jack", NULL, "VOUT1R" }, ++ ++ { "I2S Center Jack", NULL, "VOUT2L" }, ++ { "I2S Center Jack", NULL, "VOUT2R" }, ++ ++ { "I2S Rear Jack", NULL, "VOUT3L" }, ++ { "I2S Rear Jack", NULL, "VOUT3R" }, ++ ++ { "AINL", NULL, "Line In Jack" }, ++ { "AINR", NULL, "Line In Jack" }, ++ ++}; ++ ++static int smdkc100_wm8580_init(struct snd_soc_codec *codec) ++{ ++ int i; ++ ++ /* Add smdkc100 specific widgets */ ++ snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets,ARRAY_SIZE(wm8580_dapm_widgets)); ++ ++ /* set up smdkc100 specific audio paths */ ++ snd_soc_dapm_add_routes(codec, audio_map,ARRAY_SIZE(audio_map)); ++ ++ /* No jack detect - mark all jacks as enabled */ ++ for (i = 0; i < ARRAY_SIZE(wm8580_dapm_widgets); i++) ++ snd_soc_dapm_set_endpoint(codec, ++ wm8580_dapm_widgets[i].name, 1); ++ ++ snd_soc_dapm_sync_endpoints(codec); ++ ++ return 0; ++} ++ ++static struct snd_soc_dai_link smdkc100_dai[] = { ++{ ++ .name = "WM8580", ++ .stream_name = "WM8580 HiFi Playback", ++ .cpu_dai = &s3c_i2s_v50_dai, ++ .codec_dai = &wm8580_dai[WM8580_DAI_PAIFRX], ++ .init = smdkc100_wm8580_init, ++ .ops = &smdkc100_hifi_ops, ++}, ++}; ++ ++static struct snd_soc_machine smdkc100 = { ++ .name = "smdkc100", ++ .dai_link = smdkc100_dai, ++ .num_links = ARRAY_SIZE(smdkc100_dai), ++}; ++ ++static struct wm8580_setup_data smdkc100_wm8580_setup = { ++ .i2c_address = 0x1b, ++}; ++ ++static struct snd_soc_device smdkc100_snd_devdata = { ++ .machine = &smdkc100, ++ .platform = &s3c24xx_soc_platform, ++ .codec_dev = &soc_codec_dev_wm8580, ++ .codec_data = &smdkc100_wm8580_setup, ++}; ++ ++static struct platform_device *smdkc100_snd_device; ++ ++static int __init smdkc100_init(void) ++{ ++ int ret; ++ ++ smdkc100_snd_device = platform_device_alloc("soc-audio", -1); ++ if (!smdkc100_snd_device) ++ return -ENOMEM; ++ ++ platform_set_drvdata(smdkc100_snd_device, &smdkc100_snd_devdata); ++ smdkc100_snd_devdata.dev = &smdkc100_snd_device->dev; ++ ret = platform_device_add(smdkc100_snd_device); ++ ++ if (ret) ++ platform_device_put(smdkc100_snd_device); ++ ++ return ret; ++} ++ ++static void __exit smdkc100_exit(void) ++{ ++ platform_device_unregister(smdkc100_snd_device); ++} ++ ++module_init(smdkc100_init); ++module_exit(smdkc100_exit); ++ ++/* Module information */ ++MODULE_AUTHOR("Mark Brown"); ++MODULE_DESCRIPTION("ALSA SoC SMDK6410 WM8580"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/s5pc1xx/smdkc100_wm9713.c linux-2.6.28.6/sound/soc/s5pc1xx/smdkc100_wm9713.c +--- linux-2.6.28/sound/soc/s5pc1xx/smdkc100_wm9713.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/s5pc1xx/smdkc100_wm9713.c 2009-04-30 09:36:40.000000000 +0200 +@@ -0,0 +1,87 @@ ++/* ++ * smdk6400_wm9713.c -- SoC audio for smdk6400 ++ * ++ * Copyright (C) 2007, Ryu Euiyoul ++ * ++ * Copyright 2007 Wolfson Microelectronics PLC. ++ * Author: Graeme Gregory ++ * graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * Revision history ++ * 8th Mar 2007 Initial version. ++ * 20th Sep 2007 Apply at smdk6400 ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../codecs/wm9713.h" ++#include "s5pc1xx-pcm.h" ++#include "s5pc1xx-ac97.h" ++ ++static struct snd_soc_machine smdk6400; ++ ++static struct snd_soc_dai_link smdk6400_dai[] = { ++{ ++ .name = "AC97", ++ .stream_name = "AC97 HiFi", ++ .cpu_dai = &s3c6400_ac97_dai[0], ++ .codec_dai = &wm9713_dai[WM9713_DAI_AC97_HIFI], ++}, ++}; ++ ++static struct snd_soc_machine smdk6400 = { ++ .name = "SMDKC100", ++ .dai_link = smdk6400_dai, ++ .num_links = ARRAY_SIZE(smdk6400_dai), ++}; ++ ++static struct snd_soc_device smdk6400_snd_ac97_devdata = { ++ .machine = &smdk6400, ++ .platform = &s3c24xx_soc_platform, ++ .codec_dev = &soc_codec_dev_wm9713, ++}; ++ ++static struct platform_device *smdk6400_snd_ac97_device; ++ ++static int __init smdk6400_init(void) ++{ ++ int ret; ++ ++ smdk6400_snd_ac97_device = platform_device_alloc("soc-audio", -1); ++ if (!smdk6400_snd_ac97_device) ++ return -ENOMEM; ++ ++ platform_set_drvdata(smdk6400_snd_ac97_device, ++ &smdk6400_snd_ac97_devdata); ++ smdk6400_snd_ac97_devdata.dev = &smdk6400_snd_ac97_device->dev; ++ ret = platform_device_add(smdk6400_snd_ac97_device); ++ ++ if (ret) ++ platform_device_put(smdk6400_snd_ac97_device); ++ ++ return ret; ++} ++ ++static void __exit smdk6400_exit(void) ++{ ++ platform_device_unregister(smdk6400_snd_ac97_device); ++} ++ ++module_init(smdk6400_init); ++module_exit(smdk6400_exit); ++ ++/* Module information */ ++MODULE_AUTHOR("Samsung"); ++MODULE_DESCRIPTION("ALSA SoC WM9713 SMDKC100"); ++MODULE_LICENSE("GPL"); +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/soc-core.c linux-2.6.28.6/sound/soc/soc-core.c +--- linux-2.6.28/sound/soc/soc-core.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/soc-core.c 2009-04-30 09:36:40.000000000 +0200 +@@ -430,6 +430,7 @@ + + /* we only want to start a DAPM playback stream if we are not waiting + * on an existing one stopping */ ++#if !defined(CONFIG_SND_SMDKC100_WM9713) + if (codec_dai->pop_wait) { + /* we are waiting for the delayed work to start */ + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) +@@ -474,6 +475,7 @@ + snd_soc_dai_digital_mute(codec_dai, 0); + } + } ++#endif + + out: + mutex_unlock(&pcm_mutex); +@@ -922,6 +924,7 @@ + if (codec_dai->capture.channels_min) + capture = 1; + ++printk("playback: %d, capture : %d\n",playback,capture); + ret = snd_pcm_new(codec->card, new_name, codec->pcm_devs++, playback, + capture, &pcm); + if (ret < 0) { +diff -NurbB --exclude linux-2.6.28.6/Documentation/dontdiff linux-2.6.28/sound/soc/soc-dapm.c linux-2.6.28.6/sound/soc/soc-dapm.c +--- linux-2.6.28/sound/soc/soc-dapm.c 2008-12-25 00:26:37.000000000 +0100 ++++ linux-2.6.28.6/sound/soc/soc-dapm.c 2009-04-30 09:36:40.000000000 +0200 +@@ -1021,12 +1021,14 @@ + * + * Returns 0 for success else error. + */ ++#if 1 + int snd_soc_dapm_connect_input(struct snd_soc_codec *codec, const char *sink, + const char *control, const char *source) + { + return snd_soc_dapm_add_route(codec, sink, control, source); + } + EXPORT_SYMBOL_GPL(snd_soc_dapm_connect_input); ++#endif + + /** + * snd_soc_dapm_add_routes - Add routes between DAPM widgets +@@ -1539,6 +1541,45 @@ + } + EXPORT_SYMBOL_GPL(snd_soc_dapm_free); + ++/* snd_soc_dapm_set_endpoint - set audio endpoint status ++ * @codec: audio codec ++ * @endpoint: audio signal endpoint (or start point) ++ * @status: point status ++ * ++ * Set audio endpoint status - connected or disconnected. ++ * ++ * Returns 0 for success else error. ++ */ ++int snd_soc_dapm_set_endpoint(struct snd_soc_codec *codec, ++ char *endpoint, int status) ++{ ++ struct snd_soc_dapm_widget *w; ++ ++ list_for_each_entry(w, &codec->dapm_widgets, list) { ++ if (!strcmp(w->name, endpoint)) { ++ w->connected = status; ++ } ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(snd_soc_dapm_set_endpoint); ++ ++/** ++ * snd_soc_dapm_sync_endpoints - scan and power dapm paths ++ * @codec: audio codec ++ * ++ * Walks all dapm audio paths and powers widgets according to their ++ * stream or path usage. ++ * ++ * Returns 0 for success. ++ */ ++int snd_soc_dapm_sync_endpoints(struct snd_soc_codec *codec) ++{ ++ return dapm_power_widgets(codec, SND_SOC_DAPM_STREAM_NOP); ++} ++EXPORT_SYMBOL_GPL(snd_soc_dapm_sync_endpoints); ++ + /* Module information */ + MODULE_AUTHOR("Liam Girdwood, lrg@slimlogic.co.uk"); + MODULE_DESCRIPTION("Dynamic Audio Power Management core for ALSA SoC"); diff --git a/recipes/linux/linux-2.6.28/mini6410/undefined.patch b/recipes/linux/linux-2.6.28/mini6410/undefined.patch new file mode 100644 index 0000000000..640dfe7e0c --- /dev/null +++ b/recipes/linux/linux-2.6.28/mini6410/undefined.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/plat-s3c/clock.c 2010-09-09 17:17:50.000000000 +0200 ++++ b/arch/arm/plat-s3c/clock.c 2010-09-08 22:55:34.000000000 +0200 +@@ -51,6 +51,8 @@ + #include + + static LIST_HEAD(clocks); ++extern int s3c_fclk_set_rate(struct clk *clk, unsigned long rate); ++extern unsigned long s3c_fclk_round_rate(struct clk *clk, unsigned long rate); + + /* We originally used an mutex here, but some contexts (see resume) + * are calling functions such as clk_set_parent() with IRQs disabled diff --git a/recipes/linux/linux_2.6.28.bb b/recipes/linux/linux_2.6.28.bb index 33037e662a..8f61268db0 100644 --- a/recipes/linux/linux_2.6.28.bb +++ b/recipes/linux/linux_2.6.28.bb @@ -15,6 +15,7 @@ DEFAULT_PREFERENCE_tx27 = "1" DEFAULT_PREFERENCE_nokia900 = "1" DEFAULT_PREFERENCE_mh355 = "2" DEFAULT_PREFERENCE_smartqv7 = "1" +DEFAULT_PREFERENCE_mini6410 = "1" SRC_URI = "${KERNELORG_MIRROR}/pub/linux/kernel/v2.6/linux-2.6.28.tar.bz2;name=kernel \ ${KERNELORG_MIRROR}/pub/linux/kernel/v2.6/patch-${PV}.10.bz2;apply=yes;name=stablepatch \ @@ -78,6 +79,12 @@ SRC_URI_append_tx27 = " \ file://linux-2.6.28-karo4.diff \ " +SRC_URI_mini6410 = "${KERNELORG_MIRROR}/pub/linux/kernel/v2.6/linux-2.6.28.tar.bz2;name=kernel \ + ${KERNELORG_MIRROR}/pub/linux/kernel/v2.6/patch-${PV}.6.bz2;apply=yes;name=stablepatch6 \ + file://mini6410.patch;apply=yes \ + file://undefined.patch;apply=yes \ + file://defconfig" + SRC_URI_nokia900 = "${KERNELORG_MIRROR}/pub/linux/kernel/v2.6/linux-2.6.28.tar.bz2;name=kernel \ http://repository.maemo.org/pool/maemo5.0/free/k/kernel/kernel_2.6.28-20094803.3+0m5.diff.gz;name=nokiapatch \ file://defconfig" @@ -100,6 +107,8 @@ SRC_URI[kernel.md5sum] = "d351e44709c9810b85e29b877f50968a" SRC_URI[kernel.sha256sum] = "ae0d97c55efe7fce01273c97f8152af0deff5541e3bbf5b9ad98689112b54380" SRC_URI[stablepatch.md5sum] = "64e6b226f1dc469755d82d0d8b677feb" SRC_URI[stablepatch.sha256sum] = "f4a2f97f59d272571a4977916392628642a8e4388f94417a723dc4bdb0e47dc2" +SRC_URI[stablepatch6.md5sum] = "f8aa9ca3eb395f0e781cd91de5d5d86b" +SRC_URI[stablepatch6.sha256sum] = "0da592467b8a1d3f839c4d2b6d8495d5b32f5661e96f0782c063c22e4c6393e4" SRC_URI[ronetixpatch.md5sum] = "22af1c0a7bdc5d0f4e83f17f91b0c524" SRC_URI[ronetixpatch.sha256sum] = "da47c6e2ab51180be3b50d3cd219dbebe877121e4068aa5846fc1cd018082931" SRC_URI[nokiapatch.md5sum] = "fdd13af46cbaf8594b9fc3d82070aecc" -- cgit v1.2.3