From c80e052a1532b7f8a10e1b19ceb4fb4086631d6f Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Wed, 14 Apr 2010 12:30:33 +0200 Subject: u-boot git: update beagleboard patches --- .../0001-Minimal-Display-driver-for-OMAP3.patch | 508 --------------------- ...-display-message-about-I2C-errors-being-e.patch | 26 ++ ...02-beagleboard-fix-TCT-expansionboard-IDs.patch | 27 ++ .../0003-Add-DSS-driver-for-OMAP3.patch | 353 ++++++++++++++ .../0004-Enable-DSS-driver-for-Beagle.patch | 158 +++++++ ...ardXM-don-t-set-mpurate-on-xM-in-bootargs.patch | 24 + ...e-ES1-cache-workaround-it-falsely-trigger.patch | 32 ++ recipes/u-boot/u-boot_git.bb | 9 +- 8 files changed, 627 insertions(+), 510 deletions(-) delete mode 100644 recipes/u-boot/u-boot-git/beagleboard/0001-Minimal-Display-driver-for-OMAP3.patch create mode 100644 recipes/u-boot/u-boot-git/beagleboard/0001-beagleboard-display-message-about-I2C-errors-being-e.patch create mode 100644 recipes/u-boot/u-boot-git/beagleboard/0002-beagleboard-fix-TCT-expansionboard-IDs.patch create mode 100644 recipes/u-boot/u-boot-git/beagleboard/0003-Add-DSS-driver-for-OMAP3.patch create mode 100644 recipes/u-boot/u-boot-git/beagleboard/0004-Enable-DSS-driver-for-Beagle.patch create mode 100644 recipes/u-boot/u-boot-git/beagleboard/0005-beagleboardXM-don-t-set-mpurate-on-xM-in-bootargs.patch create mode 100644 recipes/u-boot/u-boot-git/beagleboard/0006-OMAP3-remove-ES1-cache-workaround-it-falsely-trigger.patch (limited to 'recipes/u-boot') diff --git a/recipes/u-boot/u-boot-git/beagleboard/0001-Minimal-Display-driver-for-OMAP3.patch b/recipes/u-boot/u-boot-git/beagleboard/0001-Minimal-Display-driver-for-OMAP3.patch deleted file mode 100644 index f3a17b745c..0000000000 --- a/recipes/u-boot/u-boot-git/beagleboard/0001-Minimal-Display-driver-for-OMAP3.patch +++ /dev/null @@ -1,508 +0,0 @@ -From 6f539e0a265bbf009c35ca7474454aa2306fdd1a Mon Sep 17 00:00:00 2001 -From: Syed Mohammed Khasim -Date: Sun, 28 Mar 2010 22:03:30 +0200 -Subject: [PATCH] Minimal Display driver for OMAP3 - -Supports dynamic configuration of Panel and Video Encoder -Supports Background color on DVID -Supports Color bar on S-Video - -Signed-off-by: Syed Mohammed Khasim ---- - board/ti/beagle/beagle.c | 13 +++ - board/ti/beagle/beagle.h | 73 ++++++++++++++ - drivers/video/Makefile | 1 + - drivers/video/omap3_dss.c | 128 +++++++++++++++++++++++++ - include/asm-arm/arch-omap3/dss.h | 193 ++++++++++++++++++++++++++++++++++++++ - include/configs/omap3_beagle.h | 1 + - 6 files changed, 409 insertions(+), 0 deletions(-) - create mode 100644 drivers/video/omap3_dss.c - create mode 100644 include/asm-arm/arch-omap3/dss.h - -diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c -index 8c5b88c..b6ddc8e 100644 ---- a/board/ti/beagle/beagle.c -+++ b/board/ti/beagle/beagle.c -@@ -141,6 +141,17 @@ unsigned int get_expansion_id(void) - } - - /* -+ * Configure DSS to display background color on DVID -+ * Configure VENC to display color bar on S-Video -+ */ -+void display_init(void) -+{ -+ omap3_dss_venc_config(&venc_config_std_tv); -+ omap3_dss_panel_config(&dvid_cfg); -+ omap3_dss_set_background_col(DVI_BEAGLE_ORANGE_COL); -+} -+ -+/* - * Routine: misc_init_r - * Description: Configure board specific parts - */ -@@ -149,6 +160,7 @@ int misc_init_r(void) - struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; - struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE; - -+ display_init(); - beagle_identify(); - switch (get_expansion_id()) { - case TINCANTOOLS_ZIPPY: -@@ -185,6 +197,7 @@ int misc_init_r(void) - - twl4030_power_init(); - twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); -+ omap3_dss_enable(); - - switch (beagle_revision) { - case REVISION_AXBX: -diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h -index ec4f831..8ceea61 100644 ---- a/board/ti/beagle/beagle.h -+++ b/board/ti/beagle/beagle.h -@@ -23,6 +23,8 @@ - #ifndef _BEAGLE_H_ - #define _BEAGLE_H_ - -+#include -+ - const omap3_sysinfo sysinfo = { - DDR_STACKED, - "OMAP3 Beagle board", -@@ -433,4 +435,75 @@ const omap3_sysinfo sysinfo = { - MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\ - -+/* -+ * Display Configuration -+ */ -+ -+#define DVI_BEAGLE_ORANGE_COL 0x00FF8000 -+ -+/* -+ * Configure VENC in DSS for Beagle to generate Color Bar -+ * -+ * Kindly refer to OMAP TRM for definition of these values. -+ */ -+static const struct venc_config venc_config_std_tv = { -+ .status = 0x0000001B, -+ .f_control = 0x00000040, -+ .vidout_ctrl = 0x00000000, -+ .sync_ctrl = 0x00008000, -+ .llen = 0x00008359, -+ .flens = 0x0000020C, -+ .hfltr_ctrl = 0x00000000, -+ .cc_carr_wss_carr = 0x043F2631, -+ .c_phase = 0x00000024, -+ .gain_u = 0x00000130, -+ .gain_v = 0x00000198, -+ .gain_y = 0x000001C0, -+ .black_level = 0x0000006A, -+ .blank_level = 0x0000005C, -+ .x_color = 0x00000000, -+ .m_control = 0x00000001, -+ .bstamp_wss_data = 0x0000003F, -+ .s_carr = 0x21F07C1F, -+ .line21 = 0x00000000, -+ .ln_sel = 0x00000015, -+ .l21__wc_ctl = 0x00001400, -+ .htrigger_vtrigger = 0x00000000, -+ .savid__eavid = 0x069300F4, -+ .flen__fal = 0x0016020C, -+ .lal__phase_reset = 0x00060107, -+ .hs_int_start_stop_x = 0x008D034E, -+ .hs_ext_start_stop_x = 0x000F0359, -+ .vs_int_start_x = 0x01A00000, -+ .vs_int_stop_x__vs_int_start_y = 0x020501A0, -+ .vs_int_stop_y__vs_ext_start_x = 0x01AC0024, -+ .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC, -+ .vs_ext_stop_y = 0x00000006, -+ .avid_start_stop_x = 0x03480079, -+ .avid_start_stop_y = 0x02040024, -+ .fid_int_start_x__fid_int_start_y = 0x0001008A, -+ .fid_int_offset_y__fid_ext_start_x = 0x01AC0106, -+ .fid_ext_start_y__fid_ext_offset_y = 0x01060006, -+ .tvdetgp_int_start_stop_x = 0x00140001, -+ .tvdetgp_int_start_stop_y = 0x00010001, -+ .gen_ctrl = 0x00FF0000, -+ .output_control = 0x0000000D, -+ .dac_b__dac_c = 0x00000000, -+ .height_width = 0x00ef027f -+}; -+ -+/* -+ * Configure Timings for DVI D -+ */ -+static const struct panel_config dvid_cfg = { -+ .timing_h = 0x0ff03f31, /* Horizantal timing */ -+ .timing_v = 0x01400504, /* Vertical timing */ -+ .pol_freq = 0x00007028, /* Pol Freq */ -+ .divisor = 0x00010006, /* 72Mhz Pixel Clock */ -+ .lcd_size = 0x02ff03ff, /* 1024x768 */ -+ .panel_type = 0x01, /* TFT */ -+ .data_lines = 0x03, /* 24 Bit RGB */ -+ .load_mode = 0x02 /* Frame Mode */ -+}; -+ - #endif -diff --git a/drivers/video/Makefile b/drivers/video/Makefile -index a5e339a..44d7ae8 100644 ---- a/drivers/video/Makefile -+++ b/drivers/video/Makefile -@@ -38,6 +38,7 @@ COBJS-$(CONFIG_SED156X) += sed156x.o - COBJS-$(CONFIG_VIDEO_SM501) += sm501.o - COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o - COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o -+COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o - COBJS-y += videomodes.o - - COBJS := $(COBJS-y) -diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c -new file mode 100644 -index 0000000..2ead7b9 ---- /dev/null -+++ b/drivers/video/omap3_dss.c -@@ -0,0 +1,128 @@ -+/* -+ * (C) Copyright 2010 -+ * Texas Instruments, -+ * Syed Mohammed Khasim -+ * -+ * Referred to Linux DSS driver files for OMAP3 -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation's version 2 of -+ * the License. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+ -+#include -+#include -+#include -+ -+/* -+ * VENC configuration -+ */ -+void omap3_dss_venc_config(const struct venc_config *venc_cfg) -+{ -+ dss_write_reg(VENC_STATUS, venc_cfg->status); -+ dss_write_reg(VENC_F_CONTROL, venc_cfg->f_control); -+ dss_write_reg(VENC_VIDOUT_CTRL, venc_cfg->vidout_ctrl); -+ dss_write_reg(VENC_SYNC_CTRL, venc_cfg->sync_ctrl); -+ dss_write_reg(VENC_LLEN, venc_cfg->llen); -+ dss_write_reg(VENC_FLENS, venc_cfg->flens); -+ dss_write_reg(VENC_HFLTR_CTRL, venc_cfg->hfltr_ctrl); -+ dss_write_reg(VENC_CC_CARR_WSS_CARR, venc_cfg->cc_carr_wss_carr); -+ dss_write_reg(VENC_C_PHASE, venc_cfg->c_phase); -+ dss_write_reg(VENC_GAIN_U, venc_cfg->gain_u); -+ dss_write_reg(VENC_GAIN_V, venc_cfg->gain_v); -+ dss_write_reg(VENC_GAIN_Y, venc_cfg->gain_y); -+ dss_write_reg(VENC_BLACK_LEVEL, venc_cfg->black_level); -+ dss_write_reg(VENC_BLANK_LEVEL, venc_cfg->blank_level); -+ dss_write_reg(VENC_X_COLOR, venc_cfg->x_color); -+ dss_write_reg(VENC_M_CONTROL, venc_cfg->m_control); -+ dss_write_reg(VENC_BSTAMP_WSS_DATA, venc_cfg->bstamp_wss_data); -+ dss_write_reg(VENC_S_CARR, venc_cfg->s_carr); -+ dss_write_reg(VENC_LINE21, venc_cfg->line21); -+ dss_write_reg(VENC_LN_SEL, venc_cfg->ln_sel); -+ dss_write_reg(VENC_L21__WC_CTL, venc_cfg->l21__wc_ctl); -+ dss_write_reg(VENC_HTRIGGER_VTRIGGER, venc_cfg->htrigger_vtrigger); -+ dss_write_reg(VENC_SAVID__EAVID, venc_cfg->savid__eavid); -+ dss_write_reg(VENC_FLEN__FAL, venc_cfg->flen__fal); -+ dss_write_reg(VENC_LAL__PHASE_RESET, venc_cfg->lal__phase_reset); -+ dss_write_reg(VENC_HS_INT_START_STOP_X, -+ venc_cfg->hs_int_start_stop_x); -+ dss_write_reg(VENC_HS_EXT_START_STOP_X, -+ venc_cfg->hs_ext_start_stop_x); -+ dss_write_reg(VENC_VS_INT_START_X, venc_cfg->vs_int_start_x); -+ dss_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y, -+ venc_cfg->vs_int_stop_x__vs_int_start_y); -+ dss_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X, -+ venc_cfg->vs_int_stop_y__vs_ext_start_x); -+ dss_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y, -+ venc_cfg->vs_ext_stop_x__vs_ext_start_y); -+ dss_write_reg(VENC_VS_EXT_STOP_Y, venc_cfg->vs_ext_stop_y); -+ dss_write_reg(VENC_AVID_START_STOP_X, venc_cfg->avid_start_stop_x); -+ dss_write_reg(VENC_AVID_START_STOP_Y, venc_cfg->avid_start_stop_y); -+ dss_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y, -+ venc_cfg->fid_int_start_x__fid_int_start_y); -+ dss_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X, -+ venc_cfg->fid_int_offset_y__fid_ext_start_x); -+ dss_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y, -+ venc_cfg->fid_ext_start_y__fid_ext_offset_y); -+ dss_write_reg(VENC_TVDETGP_INT_START_STOP_X, -+ venc_cfg->tvdetgp_int_start_stop_x); -+ dss_write_reg(VENC_TVDETGP_INT_START_STOP_Y, -+ venc_cfg->tvdetgp_int_start_stop_y); -+ dss_write_reg(VENC_GEN_CTRL, venc_cfg->gen_ctrl); -+ dss_write_reg(VENC_OUTPUT_CONTROL, venc_cfg->output_control); -+ dss_write_reg(VENC_DAC_B__DAC_C, venc_cfg->dac_b__dac_c); -+ dss_write_reg(DISPC_SIZE_DIG, venc_cfg->height_width); -+ dss_write_reg(DSS_CONTROL, VENC_DSS_CONFIG); -+} -+ -+/* -+ * Configure Panel Specific parameters -+ */ -+void omap3_dss_panel_config(const struct panel_config *panel_cfg) -+{ -+ dss_write_reg(DISPC_TIMING_H, panel_cfg->timing_h); -+ dss_write_reg(DISPC_TIMING_V, panel_cfg->timing_v); -+ dss_write_reg(DISPC_POL_FREQ, panel_cfg->pol_freq); -+ dss_write_reg(DISPC_DIVISOR, panel_cfg->divisor); -+ dss_write_reg(DISPC_SIZE_LCD, panel_cfg->lcd_size); -+ dss_write_reg(DISPC_CONFIG, -+ (panel_cfg->load_mode << FRAME_MODE_OFFSET)); -+ dss_write_reg(DISPC_CONTROL, -+ ((panel_cfg->panel_type << TFTSTN_OFFSET) | -+ (panel_cfg->data_lines << DATALINES_OFFSET))); -+} -+ -+/* -+ * Enable LCD and DIGITAL OUT in DSS -+ */ -+void omap3_dss_enable(void) -+{ -+ u32 l = 0; -+ -+ l = dss_read_reg(DISPC_CONTROL); -+ l |= DISPC_ENABLE; -+ -+ dss_write_reg(DISPC_CONTROL, l); -+} -+ -+/* -+ * Set Background Color in DISPC -+ */ -+void omap3_dss_set_background_col(u32 color) -+{ -+ dss_write_reg(DISPC_DEFAULT_COLOR0, color); -+} -diff --git a/include/asm-arm/arch-omap3/dss.h b/include/asm-arm/arch-omap3/dss.h -new file mode 100644 -index 0000000..08c7d8d ---- /dev/null -+++ b/include/asm-arm/arch-omap3/dss.h -@@ -0,0 +1,193 @@ -+/* -+ * (C) Copyright 2010 -+ * Texas Instruments, -+ * Syed Mohammed Khasim -+ * -+ * Referred to Linux DSS driver files for OMAP3 -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation's version 2 of -+ * the License. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+ -+#ifndef DSS_H -+#define DSS_H -+ -+/* VENC Register address */ -+#define VENC_REV_ID 0x48050C00 -+#define VENC_STATUS 0x48050C04 -+#define VENC_F_CONTROL 0x48050C08 -+#define VENC_VIDOUT_CTRL 0x48050C10 -+#define VENC_SYNC_CTRL 0x48050C14 -+#define VENC_LLEN 0x48050C1C -+#define VENC_FLENS 0x48050C20 -+#define VENC_HFLTR_CTRL 0x48050C24 -+#define VENC_CC_CARR_WSS_CARR 0x48050C28 -+#define VENC_C_PHASE 0x48050C2C -+#define VENC_GAIN_U 0x48050C30 -+#define VENC_GAIN_V 0x48050C34 -+#define VENC_GAIN_Y 0x48050C38 -+#define VENC_BLACK_LEVEL 0x48050C3C -+#define VENC_BLANK_LEVEL 0x48050C40 -+#define VENC_X_COLOR 0x48050C44 -+#define VENC_M_CONTROL 0x48050C48 -+#define VENC_BSTAMP_WSS_DATA 0x48050C4C -+#define VENC_S_CARR 0x48050C50 -+#define VENC_LINE21 0x48050C54 -+#define VENC_LN_SEL 0x48050C58 -+#define VENC_L21__WC_CTL 0x48050C5C -+#define VENC_HTRIGGER_VTRIGGER 0x48050C60 -+#define VENC_SAVID__EAVID 0x48050C64 -+#define VENC_FLEN__FAL 0x48050C68 -+#define VENC_LAL__PHASE_RESET 0x48050C6C -+#define VENC_HS_INT_START_STOP_X 0x48050C70 -+#define VENC_HS_EXT_START_STOP_X 0x48050C74 -+#define VENC_VS_INT_START_X 0x48050C78 -+#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x48050C7C -+#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x48050C80 -+#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x48050C84 -+#define VENC_VS_EXT_STOP_Y 0x48050C88 -+#define VENC_AVID_START_STOP_X 0x48050C90 -+#define VENC_AVID_START_STOP_Y 0x48050C94 -+#define VENC_FID_INT_START_X__FID_INT_START_Y 0x48050CA0 -+#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0x48050CA4 -+#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0x48050CA8 -+#define VENC_TVDETGP_INT_START_STOP_X 0x48050CB0 -+#define VENC_TVDETGP_INT_START_STOP_Y 0x48050CB4 -+#define VENC_GEN_CTRL 0x48050CB8 -+#define VENC_OUTPUT_CONTROL 0x48050CC4 -+#define VENC_DAC_B__DAC_C 0x48050CC8 -+ -+/* DSS register addresses */ -+#define DSS_SYSCONFIG 0x48050010 -+#define DSS_CONTROL 0x48050040 -+ -+/* DISPC register addresses */ -+#define DISPC_SYSCONFIG 0x48050410 -+#define DISPC_SYSSTATUS 0x48050414 -+#define DISPC_CONTROL 0x48050440 -+#define DISPC_CONFIG 0x48050444 -+#define DISPC_DEFAULT_COLOR0 0x4805044c -+#define DISPC_DEFAULT_COLOR1 0x48050450 -+#define DISPC_TRANS_COLOR0 0x48050454 -+#define DISPC_TRANS_COLOR1 0x48050458 -+#define DISPC_TIMING_H 0x48050464 -+#define DISPC_TIMING_V 0x48050468 -+#define DISPC_POL_FREQ 0x4805046c -+#define DISPC_DIVISOR 0x48050470 -+#define DISPC_SIZE_DIG 0x48050478 -+#define DISPC_SIZE_LCD 0x4805047c -+ -+/* Few Register Offsets */ -+#define FRAME_MODE_OFFSET 1 -+#define TFTSTN_OFFSET 3 -+#define DATALINES_OFFSET 8 -+ -+/* Enabling Display controller */ -+#define LCD_ENABLE 1 -+#define DIG_ENABLE (1 << 1) -+#define GO_LCD (1 << 5) -+#define GO_DIG (1 << 6) -+#define GP_OUT0 (1 << 15) -+#define GP_OUT1 (1 << 16) -+ -+#define DISPC_ENABLE (LCD_ENABLE | \ -+ DIG_ENABLE | \ -+ GO_LCD | \ -+ GO_DIG | \ -+ GP_OUT0| \ -+ GP_OUT1) -+/* Configure VENC DSS Params */ -+#define VENC_CLK_ENABLE (1 << 3) -+#define DAC_DEMEN (1 << 4) -+#define DAC_POWERDN (1 << 5) -+#define VENC_OUT_SEL (1 << 6) -+ -+#define VENC_DSS_CONFIG (VENC_CLK_ENABLE | \ -+ DAC_DEMEN | \ -+ DAC_POWERDN | \ -+ VENC_OUT_SEL) -+ -+struct venc_config { -+ u32 status; -+ u32 f_control; -+ u32 vidout_ctrl; -+ u32 sync_ctrl; -+ u32 llen; -+ u32 flens; -+ u32 hfltr_ctrl; -+ u32 cc_carr_wss_carr; -+ u32 c_phase; -+ u32 gain_u; -+ u32 gain_v; -+ u32 gain_y; -+ u32 black_level; -+ u32 blank_level; -+ u32 x_color; -+ u32 m_control; -+ u32 bstamp_wss_data; -+ u32 s_carr; -+ u32 line21; -+ u32 ln_sel; -+ u32 l21__wc_ctl; -+ u32 htrigger_vtrigger; -+ u32 savid__eavid; -+ u32 flen__fal; -+ u32 lal__phase_reset; -+ u32 hs_int_start_stop_x; -+ u32 hs_ext_start_stop_x; -+ u32 vs_int_start_x; -+ u32 vs_int_stop_x__vs_int_start_y; -+ u32 vs_int_stop_y__vs_ext_start_x; -+ u32 vs_ext_stop_x__vs_ext_start_y; -+ u32 vs_ext_stop_y; -+ u32 avid_start_stop_x; -+ u32 avid_start_stop_y; -+ u32 fid_int_start_x__fid_int_start_y; -+ u32 fid_int_offset_y__fid_ext_start_x; -+ u32 fid_ext_start_y__fid_ext_offset_y; -+ u32 tvdetgp_int_start_stop_x; -+ u32 tvdetgp_int_start_stop_y; -+ u32 gen_ctrl; -+ u32 output_control; -+ u32 dac_b__dac_c; -+ u32 height_width; -+}; -+ -+struct panel_config { -+ u32 timing_h; -+ u32 timing_v; -+ u32 pol_freq; -+ u32 divisor; -+ u32 lcd_size; -+ u32 panel_type; -+ u32 data_lines; -+ u32 load_mode; -+}; -+ -+static inline void dss_write_reg(int reg, u32 val) -+{ -+ __raw_writel(val, reg); -+} -+ -+static inline u32 dss_read_reg(int reg) -+{ -+ u32 l = __raw_readl(reg); -+ return l; -+} -+ -+#endif /* DSS_H */ -diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h -index c156cea..a3092ef 100644 ---- a/include/configs/omap3_beagle.h -+++ b/include/configs/omap3_beagle.h -@@ -131,6 +131,7 @@ - #define CONFIG_CMD_I2C /* I2C serial bus support */ - #define CONFIG_CMD_MMC /* MMC support */ - #define CONFIG_CMD_NAND /* NAND support */ -+#define CONFIG_VIDEO_OMAP3 /* DSS Support */ - - #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ - #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ --- -1.6.6.1 - diff --git a/recipes/u-boot/u-boot-git/beagleboard/0001-beagleboard-display-message-about-I2C-errors-being-e.patch b/recipes/u-boot/u-boot-git/beagleboard/0001-beagleboard-display-message-about-I2C-errors-being-e.patch new file mode 100644 index 0000000000..18eeb3d6fc --- /dev/null +++ b/recipes/u-boot/u-boot-git/beagleboard/0001-beagleboard-display-message-about-I2C-errors-being-e.patch @@ -0,0 +1,26 @@ +From 59d34641c947f3b0a0c3757ced675245ae344012 Mon Sep 17 00:00:00 2001 +From: Koen Kooi +Date: Wed, 31 Mar 2010 14:24:25 +0200 +Subject: [PATCH 1/6] beagleboard: display message about I2C errors being expected when no expansion boards are present + +--- + board/ti/beagle/beagle.c | 3 +++ + 1 files changed, 3 insertions(+), 0 deletions(-) + +diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c +index 8c5b88c..c9c9a58 100644 +--- a/board/ti/beagle/beagle.c ++++ b/board/ti/beagle/beagle.c +@@ -150,6 +150,9 @@ int misc_init_r(void) + struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE; + + beagle_identify(); ++ ++ printf("\nProbing for expansion boards, if none are connected you'll see a harmless I2C error.\n"); ++ + switch (get_expansion_id()) { + case TINCANTOOLS_ZIPPY: + printf("Recognized Tincantools Zippy expansion board (rev %d %s)\n", +-- +1.6.6.1 + diff --git a/recipes/u-boot/u-boot-git/beagleboard/0002-beagleboard-fix-TCT-expansionboard-IDs.patch b/recipes/u-boot/u-boot-git/beagleboard/0002-beagleboard-fix-TCT-expansionboard-IDs.patch new file mode 100644 index 0000000000..0d75f3cffc --- /dev/null +++ b/recipes/u-boot/u-boot-git/beagleboard/0002-beagleboard-fix-TCT-expansionboard-IDs.patch @@ -0,0 +1,27 @@ +From 4397cc2f9b55471b4d90e7327bf65e1a610dcabb Mon Sep 17 00:00:00 2001 +From: Koen Kooi +Date: Sun, 11 Apr 2010 12:14:43 +0200 +Subject: [PATCH 2/6] beagleboard: fix TCT expansionboard IDs + +--- + board/ti/beagle/beagle.c | 4 ++-- + 1 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c +index c9c9a58..7cb6d1f 100644 +--- a/board/ti/beagle/beagle.c ++++ b/board/ti/beagle/beagle.c +@@ -58,8 +58,8 @@ static struct { + + #define TINCANTOOLS_ZIPPY 0x01000100 + #define TINCANTOOLS_ZIPPY2 0x02000100 +-#define TINCANTOOLS_TRAINER 0x03000100 +-#define TINCANTOOLS_SHOWDOG 0x04000100 ++#define TINCANTOOLS_TRAINER 0x04000100 ++#define TINCANTOOLS_SHOWDOG 0x03000100 + + #define BEAGLE_NO_EEPROM 0xffffffff + +-- +1.6.6.1 + diff --git a/recipes/u-boot/u-boot-git/beagleboard/0003-Add-DSS-driver-for-OMAP3.patch b/recipes/u-boot/u-boot-git/beagleboard/0003-Add-DSS-driver-for-OMAP3.patch new file mode 100644 index 0000000000..0a2a47f224 --- /dev/null +++ b/recipes/u-boot/u-boot-git/beagleboard/0003-Add-DSS-driver-for-OMAP3.patch @@ -0,0 +1,353 @@ +From fe23f2e29f4d6f4f20ed268d8060f897392a47f7 Mon Sep 17 00:00:00 2001 +From: Syed Mohammed Khasim +Date: Tue, 12 Jan 2010 23:57:28 +0530 +Subject: [PATCH 3/6] Add DSS driver for OMAP3 + +Supports dynamic panel configuration +Supports dynamic tv standard selection +Adds support for DSS register access through generic APIs + +Incorporated DSS register access using structures. + +Previous discussions are here +http://www.mail-archive.com/u-boot@lists.denx.de/msg27150.html + +Signed-off-by: Syed Mohammed Khasim +--- + drivers/video/Makefile | 1 + + drivers/video/omap3_dss.c | 130 ++++++++++++++++++++++++++++ + include/asm-arm/arch-omap3/dss.h | 173 ++++++++++++++++++++++++++++++++++++++ + 3 files changed, 304 insertions(+), 0 deletions(-) + create mode 100644 drivers/video/omap3_dss.c + create mode 100644 include/asm-arm/arch-omap3/dss.h + +diff --git a/drivers/video/Makefile b/drivers/video/Makefile +index a5e339a..44d7ae8 100644 +--- a/drivers/video/Makefile ++++ b/drivers/video/Makefile +@@ -38,6 +38,7 @@ COBJS-$(CONFIG_SED156X) += sed156x.o + COBJS-$(CONFIG_VIDEO_SM501) += sm501.o + COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o + COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o ++COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o + COBJS-y += videomodes.o + + COBJS := $(COBJS-y) +diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c +new file mode 100644 +index 0000000..69c705a +--- /dev/null ++++ b/drivers/video/omap3_dss.c +@@ -0,0 +1,130 @@ ++/* ++ * (C) Copyright 2010 ++ * Texas Instruments, ++ * Syed Mohammed Khasim ++ * ++ * Referred to Linux DSS driver files for OMAP3 ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation's version 2 of ++ * the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++ ++/* ++ * Configure VENC for a given Mode (NTSC / PAL) ++ */ ++void omap3_dss_venc_config(const struct venc_regs *venc_cfg, ++ u32 height, u32 width) ++{ ++ struct venc_regs *venc = (struct venc_regs *) OMAP3_VENC_BASE; ++ struct dss_regs *dss = (struct dss_regs *) OMAP3_DSS_BASE; ++ struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE; ++ ++ writel(venc_cfg->status, &venc->status); ++ writel(venc_cfg->f_control, &venc->f_control); ++ writel(venc_cfg->vidout_ctrl, &venc->vidout_ctrl); ++ writel(venc_cfg->sync_ctrl, &venc->sync_ctrl); ++ writel(venc_cfg->llen, &venc->llen); ++ writel(venc_cfg->flens, &venc->flens); ++ writel(venc_cfg->hfltr_ctrl, &venc->hfltr_ctrl); ++ writel(venc_cfg->cc_carr_wss_carr, &venc->cc_carr_wss_carr); ++ writel(venc_cfg->c_phase, &venc->c_phase); ++ writel(venc_cfg->gain_u, &venc->gain_u); ++ writel(venc_cfg->gain_v, &venc->gain_v); ++ writel(venc_cfg->gain_y, &venc->gain_y); ++ writel(venc_cfg->black_level, &venc->black_level); ++ writel(venc_cfg->blank_level, &venc->blank_level); ++ writel(venc_cfg->x_color, &venc->x_color); ++ writel(venc_cfg->m_control, &venc->m_control); ++ writel(venc_cfg->bstamp_wss_data, &venc->bstamp_wss_data); ++ writel(venc_cfg->s_carr, &venc->s_carr); ++ writel(venc_cfg->line21, &venc->line21); ++ writel(venc_cfg->ln_sel, &venc->ln_sel); ++ writel(venc_cfg->l21__wc_ctl, &venc->l21__wc_ctl); ++ writel(venc_cfg->htrigger_vtrigger, &venc->htrigger_vtrigger); ++ writel(venc_cfg->savid__eavid, &venc->savid__eavid); ++ writel(venc_cfg->flen__fal, &venc->flen__fal); ++ writel(venc_cfg->lal__phase_reset, &venc->lal__phase_reset); ++ writel(venc_cfg->hs_int_start_stop_x, ++ &venc->hs_int_start_stop_x); ++ writel(venc_cfg->hs_ext_start_stop_x, ++ &venc->hs_ext_start_stop_x); ++ writel(venc_cfg->vs_int_start_x, &venc->vs_int_start_x); ++ writel(venc_cfg->vs_int_stop_x__vs_int_start_y, ++ &venc->vs_int_stop_x__vs_int_start_y); ++ writel(venc_cfg->vs_int_stop_y__vs_ext_start_x, ++ &venc->vs_int_stop_y__vs_ext_start_x); ++ writel(venc_cfg->vs_ext_stop_x__vs_ext_start_y, ++ &venc->vs_ext_stop_x__vs_ext_start_y); ++ writel(venc_cfg->vs_ext_stop_y, &venc->vs_ext_stop_y); ++ writel(venc_cfg->avid_start_stop_x, &venc->avid_start_stop_x); ++ writel(venc_cfg->avid_start_stop_y, &venc->avid_start_stop_y); ++ writel(venc_cfg->fid_int_start_x__fid_int_start_y, ++ &venc->fid_int_start_x__fid_int_start_y); ++ writel(venc_cfg->fid_int_offset_y__fid_ext_start_x, ++ &venc->fid_int_offset_y__fid_ext_start_x); ++ writel(venc_cfg->fid_ext_start_y__fid_ext_offset_y, ++ &venc->fid_ext_start_y__fid_ext_offset_y); ++ writel(venc_cfg->tvdetgp_int_start_stop_x, ++ &venc->tvdetgp_int_start_stop_x); ++ writel(venc_cfg->tvdetgp_int_start_stop_y, ++ &venc->tvdetgp_int_start_stop_y); ++ writel(venc_cfg->gen_ctrl, &venc->gen_ctrl); ++ writel(venc_cfg->output_control, &venc->output_control); ++ writel(venc_cfg->dac_b__dac_c, &venc->dac_b__dac_c); ++ ++ /* Configure DSS for VENC Settings */ ++ writel(VENC_DSS_CONFIG, &dss->control); ++ ++ /* Configure height and width for Digital out */ ++ writel(((height << DIG_LPP_SHIFT) | width), &dispc->size_dig); ++} ++ ++/* ++ * Configure Panel Specific Parameters ++ */ ++void omap3_dss_panel_config(const struct panel_config *panel_cfg) ++{ ++ struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE; ++ ++ writel(panel_cfg->timing_h, &dispc->timing_h); ++ writel(panel_cfg->timing_v, &dispc->timing_v); ++ writel(panel_cfg->pol_freq, &dispc->pol_freq); ++ writel(panel_cfg->divisor, &dispc->divisor); ++ writel(panel_cfg->lcd_size, &dispc->size_lcd); ++ writel((panel_cfg->load_mode << FRAME_MODE_SHIFT), &dispc->config); ++ writel(((panel_cfg->panel_type << TFTSTN_SHIFT) | ++ (panel_cfg->data_lines << DATALINES_SHIFT)), &dispc->control); ++ writel(panel_cfg->panel_color, &dispc->default_color0); ++} ++ ++/* ++ * Enable LCD and DIGITAL OUT in DSS ++ */ ++void omap3_dss_enable(void) ++{ ++ struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE; ++ u32 l = 0; ++ ++ l = readl(&dispc->control); ++ l |= DISPC_ENABLE; ++ writel(l, &dispc->control); ++} +diff --git a/include/asm-arm/arch-omap3/dss.h b/include/asm-arm/arch-omap3/dss.h +new file mode 100644 +index 0000000..e5e3b0d +--- /dev/null ++++ b/include/asm-arm/arch-omap3/dss.h +@@ -0,0 +1,173 @@ ++/* ++ * (C) Copyright 2010 ++ * Texas Instruments, ++ * Syed Mohammed Khasim ++ * ++ * Referred to Linux DSS driver files for OMAP3 ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation's version 2 of ++ * the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef DSS_H ++#define DSS_H ++ ++/* ++ * DSS Base Registers ++ */ ++#define OMAP3_DSS_BASE 0x48050040 ++#define OMAP3_DISPC_BASE 0x48050440 ++#define OMAP3_VENC_BASE 0x48050C00 ++ ++/* DSS Registers */ ++struct dss_regs { ++ u32 control; /* 0x40 */ ++ u32 sdi_control; /* 0x44 */ ++ u32 pll_control; /* 0x48 */ ++}; ++ ++/* DISPC Registers */ ++struct dispc_regs { ++ u32 control; /* 0x40 */ ++ u32 config; /* 0x44 */ ++ u32 reserve_2; /* 0x48 */ ++ u32 default_color0; /* 0x4C */ ++ u32 default_color1; /* 0x50 */ ++ u32 trans_color0; /* 0x54 */ ++ u32 trans_color1; /* 0x58 */ ++ u32 line_status; /* 0x5C */ ++ u32 line_number; /* 0x60 */ ++ u32 timing_h; /* 0x64 */ ++ u32 timing_v; /* 0x68 */ ++ u32 pol_freq; /* 0x6C */ ++ u32 divisor; /* 0x70 */ ++ u32 global_alpha; /* 0x74 */ ++ u32 size_dig; /* 0x78 */ ++ u32 size_lcd; /* 0x7C */ ++}; ++ ++/* VENC Registers */ ++struct venc_regs { ++ u32 rev_id; /* 0x00 */ ++ u32 status; /* 0x04 */ ++ u32 f_control; /* 0x08 */ ++ u32 reserve_1; /* 0x0C */ ++ u32 vidout_ctrl; /* 0x10 */ ++ u32 sync_ctrl; /* 0x14 */ ++ u32 reserve_2; /* 0x18 */ ++ u32 llen; /* 0x1C */ ++ u32 flens; /* 0x20 */ ++ u32 hfltr_ctrl; /* 0x24 */ ++ u32 cc_carr_wss_carr; /* 0x28 */ ++ u32 c_phase; /* 0x2C */ ++ u32 gain_u; /* 0x30 */ ++ u32 gain_v; /* 0x34 */ ++ u32 gain_y; /* 0x38 */ ++ u32 black_level; /* 0x3C */ ++ u32 blank_level; /* 0x40 */ ++ u32 x_color; /* 0x44 */ ++ u32 m_control; /* 0x48 */ ++ u32 bstamp_wss_data; /* 0x4C */ ++ u32 s_carr; /* 0x50 */ ++ u32 line21; /* 0x54 */ ++ u32 ln_sel; /* 0x58 */ ++ u32 l21__wc_ctl; /* 0x5C */ ++ u32 htrigger_vtrigger; /* 0x60 */ ++ u32 savid__eavid; /* 0x64 */ ++ u32 flen__fal; /* 0x68 */ ++ u32 lal__phase_reset; /* 0x6C */ ++ u32 hs_int_start_stop_x; /* 0x70 */ ++ u32 hs_ext_start_stop_x; /* 0x74 */ ++ u32 vs_int_start_x; /* 0x78 */ ++ u32 vs_int_stop_x__vs_int_start_y; /* 0x7C */ ++ u32 vs_int_stop_y__vs_ext_start_x; /* 0x80 */ ++ u32 vs_ext_stop_x__vs_ext_start_y; /* 0x84 */ ++ u32 vs_ext_stop_y; /* 0x88 */ ++ u32 reserve_3; /* 0x8C */ ++ u32 avid_start_stop_x; /* 0x90 */ ++ u32 avid_start_stop_y; /* 0x94 */ ++ u32 reserve_4; /* 0x98 */ ++ u32 reserve_5; /* 0x9C */ ++ u32 fid_int_start_x__fid_int_start_y; /* 0xA0 */ ++ u32 fid_int_offset_y__fid_ext_start_x; /* 0xA4 */ ++ u32 fid_ext_start_y__fid_ext_offset_y; /* 0xA8 */ ++ u32 reserve_6; /* 0xAC */ ++ u32 tvdetgp_int_start_stop_x; /* 0xB0 */ ++ u32 tvdetgp_int_start_stop_y; /* 0xB4 */ ++ u32 gen_ctrl; /* 0xB8 */ ++ u32 reserve_7; /* 0xBC */ ++ u32 reserve_8; /* 0xC0 */ ++ u32 output_control; /* 0xC4 */ ++ u32 dac_b__dac_c; /* 0xC8 */ ++ u32 height_width; /* 0xCC */ ++}; ++ ++/* Few Register Offsets */ ++#define FRAME_MODE_SHIFT 1 ++#define TFTSTN_SHIFT 3 ++#define DATALINES_SHIFT 8 ++ ++/* Enabling Display controller */ ++#define LCD_ENABLE 1 ++#define DIG_ENABLE (1 << 1) ++#define GO_LCD (1 << 5) ++#define GO_DIG (1 << 6) ++#define GP_OUT0 (1 << 15) ++#define GP_OUT1 (1 << 16) ++ ++#define DISPC_ENABLE (LCD_ENABLE | \ ++ DIG_ENABLE | \ ++ GO_LCD | \ ++ GO_DIG | \ ++ GP_OUT0| \ ++ GP_OUT1) ++ ++/* Configure VENC DSS Params */ ++#define VENC_CLK_ENABLE (1 << 3) ++#define DAC_DEMEN (1 << 4) ++#define DAC_POWERDN (1 << 5) ++#define VENC_OUT_SEL (1 << 6) ++#define DIG_LPP_SHIFT 16 ++#define VENC_DSS_CONFIG (VENC_CLK_ENABLE | \ ++ DAC_DEMEN | \ ++ DAC_POWERDN | \ ++ VENC_OUT_SEL) ++/* ++ * Panel Configuration ++ */ ++struct panel_config { ++ u32 timing_h; ++ u32 timing_v; ++ u32 pol_freq; ++ u32 divisor; ++ u32 lcd_size; ++ u32 panel_type; ++ u32 data_lines; ++ u32 load_mode; ++ u32 panel_color; ++}; ++ ++/* ++ * Generic DSS Functions ++ */ ++void omap3_dss_venc_config(const struct venc_regs *venc_cfg, ++ u32 height, u32 width); ++void omap3_dss_panel_config(const struct panel_config *panel_cfg); ++void omap3_dss_enable(void); ++ ++#endif /* DSS_H */ +-- +1.6.6.1 + diff --git a/recipes/u-boot/u-boot-git/beagleboard/0004-Enable-DSS-driver-for-Beagle.patch b/recipes/u-boot/u-boot-git/beagleboard/0004-Enable-DSS-driver-for-Beagle.patch new file mode 100644 index 0000000000..a391dbd9d8 --- /dev/null +++ b/recipes/u-boot/u-boot-git/beagleboard/0004-Enable-DSS-driver-for-Beagle.patch @@ -0,0 +1,158 @@ +From 492fac657a2e53f4714e24471a01ed0462edb8fc Mon Sep 17 00:00:00 2001 +From: Syed Mohammed Khasim +Date: Sun, 11 Apr 2010 17:44:39 +0200 +Subject: [PATCH 4/6] Enable DSS driver for Beagle + +Configures DSS to display color bar on Svideo +Configures DSS to display background color on DVID + +Signed-off-by: Syed Mohammed Khasim +--- + board/ti/beagle/beagle.c | 12 ++++++ + board/ti/beagle/beagle.h | 75 ++++++++++++++++++++++++++++++++++++++++ + include/configs/omap3_beagle.h | 1 + + 3 files changed, 88 insertions(+), 0 deletions(-) + +diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c +index 7cb6d1f..eb57b5a 100644 +--- a/board/ti/beagle/beagle.c ++++ b/board/ti/beagle/beagle.c +@@ -141,6 +141,16 @@ unsigned int get_expansion_id(void) + } + + /* ++ * Configure DSS to display background color on DVID ++ * Configure VENC to display color bar on S-Video ++ */ ++void display_init(void) ++{ ++ omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH); ++ omap3_dss_panel_config(&dvid_cfg); ++} ++ ++/* + * Routine: misc_init_r + * Description: Configure board specific parts + */ +@@ -188,6 +198,7 @@ int misc_init_r(void) + + twl4030_power_init(); + twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); ++ display_init(); + + switch (beagle_revision) { + case REVISION_AXBX: +@@ -233,6 +244,7 @@ int misc_init_r(void) + GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout); + + dieid_num_r(); ++ omap3_dss_enable(); + + return 0; + } +diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h +index ec4f831..69f9398 100644 +--- a/board/ti/beagle/beagle.h ++++ b/board/ti/beagle/beagle.h +@@ -23,6 +23,8 @@ + #ifndef _BEAGLE_H_ + #define _BEAGLE_H_ + ++#include ++ + const omap3_sysinfo sysinfo = { + DDR_STACKED, + "OMAP3 Beagle board", +@@ -433,4 +435,77 @@ const omap3_sysinfo sysinfo = { + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\ + ++/* ++ * Display Configuration ++ */ ++ ++#define DVI_BEAGLE_ORANGE_COL 0x00FF8000 ++#define VENC_HEIGHT 0x00ef ++#define VENC_WIDTH 0x027f ++ ++/* ++ * Configure VENC in DSS for Beagle to generate Color Bar ++ * ++ * Kindly refer to OMAP TRM for definition of these values. ++ */ ++static const struct venc_regs venc_config_std_tv = { ++ .status = 0x0000001B, ++ .f_control = 0x00000040, ++ .vidout_ctrl = 0x00000000, ++ .sync_ctrl = 0x00008000, ++ .llen = 0x00008359, ++ .flens = 0x0000020C, ++ .hfltr_ctrl = 0x00000000, ++ .cc_carr_wss_carr = 0x043F2631, ++ .c_phase = 0x00000024, ++ .gain_u = 0x00000130, ++ .gain_v = 0x00000198, ++ .gain_y = 0x000001C0, ++ .black_level = 0x0000006A, ++ .blank_level = 0x0000005C, ++ .x_color = 0x00000000, ++ .m_control = 0x00000001, ++ .bstamp_wss_data = 0x0000003F, ++ .s_carr = 0x21F07C1F, ++ .line21 = 0x00000000, ++ .ln_sel = 0x00000015, ++ .l21__wc_ctl = 0x00001400, ++ .htrigger_vtrigger = 0x00000000, ++ .savid__eavid = 0x069300F4, ++ .flen__fal = 0x0016020C, ++ .lal__phase_reset = 0x00060107, ++ .hs_int_start_stop_x = 0x008D034E, ++ .hs_ext_start_stop_x = 0x000F0359, ++ .vs_int_start_x = 0x01A00000, ++ .vs_int_stop_x__vs_int_start_y = 0x020501A0, ++ .vs_int_stop_y__vs_ext_start_x = 0x01AC0024, ++ .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC, ++ .vs_ext_stop_y = 0x00000006, ++ .avid_start_stop_x = 0x03480079, ++ .avid_start_stop_y = 0x02040024, ++ .fid_int_start_x__fid_int_start_y = 0x0001008A, ++ .fid_int_offset_y__fid_ext_start_x = 0x01AC0106, ++ .fid_ext_start_y__fid_ext_offset_y = 0x01060006, ++ .tvdetgp_int_start_stop_x = 0x00140001, ++ .tvdetgp_int_start_stop_y = 0x00010001, ++ .gen_ctrl = 0x00FF0000, ++ .output_control = 0x0000000D, ++ .dac_b__dac_c = 0x00000000 ++}; ++ ++/* ++ * Configure Timings for DVI D ++ */ ++static const struct panel_config dvid_cfg = { ++ .timing_h = 0x0ff03f31, /* Horizantal timing */ ++ .timing_v = 0x01400504, /* Vertical timing */ ++ .pol_freq = 0x00007028, /* Pol Freq */ ++ .divisor = 0x00010006, /* 72Mhz Pixel Clock */ ++ .lcd_size = 0x02ff03ff, /* 1024x768 */ ++ .panel_type = 0x01, /* TFT */ ++ .data_lines = 0x03, /* 24 Bit RGB */ ++ .load_mode = 0x02, /* Frame Mode */ ++ .panel_color = DVI_BEAGLE_ORANGE_COL /* ORANGE */ ++}; ++ + #endif +diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h +index c156cea..7bcbe9b 100644 +--- a/include/configs/omap3_beagle.h ++++ b/include/configs/omap3_beagle.h +@@ -131,6 +131,7 @@ + #define CONFIG_CMD_I2C /* I2C serial bus support */ + #define CONFIG_CMD_MMC /* MMC support */ + #define CONFIG_CMD_NAND /* NAND support */ ++#define CONFIG_VIDEO_OMAP3 /* DSS Support */ + + #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ + #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +-- +1.6.6.1 + diff --git a/recipes/u-boot/u-boot-git/beagleboard/0005-beagleboardXM-don-t-set-mpurate-on-xM-in-bootargs.patch b/recipes/u-boot/u-boot-git/beagleboard/0005-beagleboardXM-don-t-set-mpurate-on-xM-in-bootargs.patch new file mode 100644 index 0000000000..020bbe15a1 --- /dev/null +++ b/recipes/u-boot/u-boot-git/beagleboard/0005-beagleboardXM-don-t-set-mpurate-on-xM-in-bootargs.patch @@ -0,0 +1,24 @@ +From 2a567cdc062d65e175f7bf0324d5d41d803fb2c5 Mon Sep 17 00:00:00 2001 +From: Koen Kooi +Date: Tue, 13 Apr 2010 22:04:07 +0200 +Subject: [PATCH 5/6] beagleboardXM: don't set mpurate on xM in bootargs + +--- + board/ti/beagle/beagle.c | 1 - + 1 files changed, 0 insertions(+), 1 deletions(-) + +diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c +index eb57b5a..974a72c 100644 +--- a/board/ti/beagle/beagle.c ++++ b/board/ti/beagle/beagle.c +@@ -226,7 +226,6 @@ int misc_init_r(void) + TWL4030_PM_RECEIVER_VAUX2_VSEL_18, + TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); +- setenv("mpurate", "720"); + break; + default: + printf("Beagle unknown 0x%02x\n", beagle_revision); +-- +1.6.6.1 + diff --git a/recipes/u-boot/u-boot-git/beagleboard/0006-OMAP3-remove-ES1-cache-workaround-it-falsely-trigger.patch b/recipes/u-boot/u-boot-git/beagleboard/0006-OMAP3-remove-ES1-cache-workaround-it-falsely-trigger.patch new file mode 100644 index 0000000000..b1c228f66d --- /dev/null +++ b/recipes/u-boot/u-boot-git/beagleboard/0006-OMAP3-remove-ES1-cache-workaround-it-falsely-trigger.patch @@ -0,0 +1,32 @@ +From afcb8e0076e2b1e8c78d7c8c34c29ec2447dc02a Mon Sep 17 00:00:00 2001 +From: Koen Kooi +Date: Wed, 14 Apr 2010 12:23:31 +0200 +Subject: [PATCH 6/6] OMAP3: remove ES1 cache workaround, it falsely triggers on xM37xx ES1 silicon + +--- + cpu/arm_cortexa8/omap3/cache.S | 2 -- + 1 files changed, 0 insertions(+), 2 deletions(-) + +diff --git a/cpu/arm_cortexa8/omap3/cache.S b/cpu/arm_cortexa8/omap3/cache.S +index 0f63815..a2d1b09 100644 +--- a/cpu/arm_cortexa8/omap3/cache.S ++++ b/cpu/arm_cortexa8/omap3/cache.S +@@ -134,7 +134,6 @@ l2_cache_enable: + @ ES2 onwards we can disable/enable L2 ourselves + bl get_cpu_rev + cmp r0, #CPU_3XX_ES20 +- blt l2_cache_disable_EARLIER_THAN_ES2 + mrc 15, 0, r3, cr1, cr0, 1 + orr r3, r3, #2 + mcr 15, 0, r3, cr1, cr0, 1 +@@ -165,7 +164,6 @@ l2_cache_disable: + @ ES2 onwards we can disable/enable L2 ourselves + bl get_cpu_rev + cmp r0, #CPU_3XX_ES20 +- blt l2_cache_disable_EARLIER_THAN_ES2 + mrc 15, 0, r3, cr1, cr0, 1 + bic r3, r3, #2 + mcr 15, 0, r3, cr1, cr0, 1 +-- +1.6.6.1 + diff --git a/recipes/u-boot/u-boot_git.bb b/recipes/u-boot/u-boot_git.bb index 50918fcbe8..a90be2975c 100644 --- a/recipes/u-boot/u-boot_git.bb +++ b/recipes/u-boot/u-boot_git.bb @@ -1,5 +1,5 @@ require u-boot.inc -PR ="r44" +PR ="r45" FILESPATHPKG =. "u-boot-git:" @@ -19,7 +19,12 @@ SRC_URI_append_afeb9260-180 = " file://AFEB9260-network-fix.patch;patch=1" SRC_URI_append_cm-t35 = "file://cm-t35/cm-t35.patch;patch=1" SRC_URI_beagleboard = "git://www.sakoman.com/git/u-boot.git;branch=omap3-v2010.3;protocol=git \ - file://0001-Minimal-Display-driver-for-OMAP3.patch;patch=1 \ + file://0001-beagleboard-display-message-about-I2C-errors-being-e.patch;patch=1 \ + file://0002-beagleboard-fix-TCT-expansionboard-IDs.patch;patch=1 \ + file://0003-Add-DSS-driver-for-OMAP3.patch;patch=1 \ + file://0004-Enable-DSS-driver-for-Beagle.patch;patch=1 \ + file://0005-beagleboardXM-don-t-set-mpurate-on-xM-in-bootargs.patch;patch=1 \ + file://0006-OMAP3-remove-ES1-cache-workaround-it-falsely-trigger.patch;patch=1 \ file://fw_env.config \ " SRCREV_beagleboard = "946351081bd14e8bf5816fc38b82e004a0e6b4fe" -- cgit v1.2.3