From 3f7b4e51b008bfaefc70eabe073c37eeef9ef355 Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Thu, 23 Apr 2009 13:57:35 +0200 Subject: linux-omap-pm git: update to latest git, refresh DSS2 patches --- .../0001-ASoC-Add-support-for-OMAP3-EVM.patch | 206 - ...-New-display-subsystem-driver-for-OMAP2-3.patch | 10355 ------------- .../0001-Implement-downsampling-with-debugs.patch | 138 - ...solution-check-that-prevents-scaling-when.patch | 26 - ...es-Steve-Kipisz-USB-EHCI-support.-He-star.patch | 146 - ...MAPFB-fb-driver-for-new-display-subsystem.patch | 3809 ----- .../0003-DSS-Add-generic-DVI-panel.patch | 146 - .../0004-DSS-support-for-Beagle-Board.patch | 1607 --- ...05-DSS-Sharp-LS037V7DW01-LCD-Panel-driver.patch | 156 - .../0006-DSS-Support-for-OMAP3-SDP-board.patch | 1877 --- .../0007-DSS-Support-for-OMAP3-EVM-board.patch | 255 - .../0008-DSS-Hacked-N810-support.patch | 1076 -- ...FB-allocate-fbmem-only-for-fb0-or-if-spes.patch | 121 - ...FB-remove-extra-omapfb_setup_overlay-call.patch | 29 - ...B-fix-GFX_SYNC-to-be-compatible-with-DSS1.patch | 27 - ...omments-to-FAKE_VSYNC-to-make-things-more.patch | 27 - .../0013-DSS-OMAPFB-remove-extra-spaces.patch | 25 - .../0014-DSS-fix-clk_get_usecount.patch | 67 - .../linux-omap-pm/add-cpufreq-for-omap3evm.diff | 28 - recipes/linux/linux-omap-pm/beagleboard/ehci.patch | 131 + .../linux/linux-omap-pm/cache-display-fix.patch | 238 - recipes/linux/linux-omap-pm/dss2.diff | 9 - ...t-gro-Fix-legacy-path-napi_complete-crash.patch | 39 + ...002-OMAPFB-move-omapfb.h-to-include-linux.patch | 1297 ++ ...003-DSS2-OMAP2-3-Display-Subsystem-driver.patch | 14450 +++++++++++++++++++ .../dss2/0004-DSS2-OMAP-framebuffer-driver.patch | 3403 +++++ .../dss2/0005-DSS2-Add-panel-drivers.patch | 396 + .../0006-DSS2-HACK-Add-DSS2-support-for-N800.patch | 1079 ++ ...Add-DSS2-support-for-SDP-Beagle-Overo-EVM.patch | 5691 ++++++++ ...unction-to-display-object-to-get-the-back.patch | 39 + .../dss2/0009-DSS2-Add-acx565akm-panel.patch | 778 + ...2-Small-VRFB-context-allocation-bug-fixed.patch | 28 + ...-Allocated-memory-for-Color-Look-up-table.patch | 37 + .../dss2/0012-DSS2-Fix-DMA-rotation.patch | 65 + .../0013-DSS2-Verify-that-overlay-paddr-0.patch | 41 + ...-Add-function-to-get-DSS-logic-clock-rate.patch | 51 + ...-DSS2-DSI-calculate-VP_CLK_RATIO-properly.patch | 68 + ...6-DSS2-DSI-improve-packet-len-calculation.patch | 58 + ...2-Disable-video-planes-on-sync-lost-error.patch | 103 + ...S2-check-for-ovl-paddr-only-when-enabling.patch | 40 + ...-fclk-limits-when-configuring-video-plane.patch | 183 + ...heck-scaling-limits-against-proper-values.patch | 79 + .../dss2/0021-DSS2-Add-venc-register-dump.patch | 96 + .../0022-DSS2-FB-remove-unused-var-warning.patch | 27 + ...the-default-FB-color-format-through-board.patch | 214 + .../dss2/0024-DSS2-Beagle-Use-gpio_set_value.patch | 48 + ...-Macro-for-calculating-base-address-of-th.patch | 28 + ...I-sidlemode-to-noidle-while-sending-frame.patch | 78 + ...2-VRFB-rotation-and-mirroring-implemented.patch | 324 + ...FB-Added-support-for-the-YUV-VRFB-rotatio.patch | 236 + ...FB-Set-line_length-correctly-for-YUV-with.patch | 61 + ..._get_trans_key-was-returning-wrong-key-ty.patch | 29 + ...2-do-bootmem-reserve-for-exclusive-access.patch | 33 + ...DSS2-Fix-DISPC_VID_FIR-value-for-omap34xx.patch | 35 + .../dss2/0033-DSS2-Prefer-3-tap-filter.patch | 82 + ...34-DSS2-VRAM-improve-omap_vram_add_region.patch | 135 + ...-the-function-pointer-for-getting-default.patch | 66 + ...-support-for-setting-and-querying-alpha-b.patch | 118 + ...2-Added-support-for-querying-color-keying.patch | 150 + ...B-Some-color-keying-pointerd-renamed-in-D.patch | 56 + ...ysfs-entry-to-for-the-alpha-blending-supp.patch | 59 + ...ded-proper-exclusion-for-destination-colo.patch | 97 + ...S2-Disable-vertical-offset-with-fieldmode.patch | 71 + ...DSS2-Don-t-enable-fieldmode-automatically.patch | 34 + ...3-DSS2-Swap-field-0-and-field-1-registers.patch | 170 + ...dd-sysfs-entry-for-seting-the-rotate-type.patch | 76 + .../0045-DSS2-Fixed-line-endings-from-to.patch | 48 + ...-DSI-decrease-sync-timeout-from-60s-to-2s.patch | 26 + ...eturn-value-for-rotate_type-sysfs-functio.patch | 44 + ...3-DMA-implement-trans-copy-and-const-fill.patch | 123 + ...9-DSS2-VRAM-clear-allocated-area-with-DMA.patch | 101 + .../0050-DSS2-OMAPFB-remove-fb-clearing-code.patch | 53 + .../0051-DSS2-VRAM-use-debugfs-not-procfs.patch | 170 + ...52-DSS2-VRAM-fix-section-mismatch-warning.patch | 34 + ...S2-disable-LCD-DIGIT-before-resetting-DSS.patch | 41 + recipes/linux/linux-omap-pm/dss2/merge-fixups.diff | 49 + recipes/linux/linux-omap-pm/dvb-fix-dma.diff | 60 - recipes/linux/linux-omap-pm/ehci.patch | 0 .../linux-omap-pm/fix-clkrate-programming.diff | 57 - recipes/linux/linux-omap-pm/fix-dpll-m4.diff | 37 - recipes/linux/linux-omap-pm/fix-irq33.diff | 111 - recipes/linux/linux-omap-pm/fixup-evm-cpufreq.diff | 44 - recipes/linux/linux-omap-pm/ioremap-fix.patch | 75 - recipes/linux/linux-omap-pm/mru-256MB.diff | 24 - .../mru-enable-overlay-optimalization.diff | 117 - .../linux-omap-pm/mru-fix-display-panning.diff | 49 - recipes/linux/linux-omap-pm/mru-fix-timings.diff | 26 - .../linux-omap-pm/mru-improve-pixclock-config.diff | 93 - .../mru-make-video-timings-selectable.diff | 312 - .../musb-support-high-bandwidth.patch.eml | 134 - recipes/linux/linux-omap-pm/no-harry-potter.diff | 11 - recipes/linux/linux-omap-pm/omap-2430-lcd.patch | 11 - .../linux/linux-omap-pm/oprofile-0.9.3.armv7.diff | 599 - recipes/linux/linux-omap-pm/overo-cpufreq.diff | 25 + recipes/linux/linux-omap-pm/overo/defconfig | 2250 +++ recipes/linux/linux-omap-pm/overo/ehci.patch | 113 + recipes/linux/linux-omap-pm/register-all-OPPs.diff | 12 - .../linux-omap-pm/strongly-ordered-memory.diff | 18 - ...edc-suppress-needless-timer-reprogramming.patch | 81 - .../linux/linux-omap-pm/timer-suppression.patch | 43 - recipes/linux/linux-omap-pm/touchscreen.patch | 22 - .../linux/linux-omap-pm/twl-asoc-fix-record.diff | 34 - recipes/linux/linux-omap-pm/usbttyfix.patch | 29 - recipes/linux/linux-omap-pm_git.bb | 94 +- 104 files changed, 33516 insertions(+), 22401 deletions(-) delete mode 100644 recipes/linux/linux-omap-pm/0001-ASoC-Add-support-for-OMAP3-EVM.patch delete mode 100644 recipes/linux/linux-omap-pm/0001-DSS-New-display-subsystem-driver-for-OMAP2-3.patch delete mode 100644 recipes/linux/linux-omap-pm/0001-Implement-downsampling-with-debugs.patch delete mode 100644 recipes/linux/linux-omap-pm/0001-Removed-resolution-check-that-prevents-scaling-when.patch delete mode 100644 recipes/linux/linux-omap-pm/0001-This-merges-Steve-Kipisz-USB-EHCI-support.-He-star.patch delete mode 100644 recipes/linux/linux-omap-pm/0002-DSS-OMAPFB-fb-driver-for-new-display-subsystem.patch delete mode 100644 recipes/linux/linux-omap-pm/0003-DSS-Add-generic-DVI-panel.patch delete mode 100644 recipes/linux/linux-omap-pm/0004-DSS-support-for-Beagle-Board.patch delete mode 100644 recipes/linux/linux-omap-pm/0005-DSS-Sharp-LS037V7DW01-LCD-Panel-driver.patch delete mode 100644 recipes/linux/linux-omap-pm/0006-DSS-Support-for-OMAP3-SDP-board.patch delete mode 100644 recipes/linux/linux-omap-pm/0007-DSS-Support-for-OMAP3-EVM-board.patch delete mode 100644 recipes/linux/linux-omap-pm/0008-DSS-Hacked-N810-support.patch delete mode 100644 recipes/linux/linux-omap-pm/0009-DSS-OMAPFB-allocate-fbmem-only-for-fb0-or-if-spes.patch delete mode 100644 recipes/linux/linux-omap-pm/0010-DSS-OMAPFB-remove-extra-omapfb_setup_overlay-call.patch delete mode 100644 recipes/linux/linux-omap-pm/0011-DSS-OMAPFB-fix-GFX_SYNC-to-be-compatible-with-DSS1.patch delete mode 100644 recipes/linux/linux-omap-pm/0012-DSS-Add-comments-to-FAKE_VSYNC-to-make-things-more.patch delete mode 100644 recipes/linux/linux-omap-pm/0013-DSS-OMAPFB-remove-extra-spaces.patch delete mode 100644 recipes/linux/linux-omap-pm/0014-DSS-fix-clk_get_usecount.patch delete mode 100644 recipes/linux/linux-omap-pm/add-cpufreq-for-omap3evm.diff create mode 100644 recipes/linux/linux-omap-pm/beagleboard/ehci.patch delete mode 100644 recipes/linux/linux-omap-pm/cache-display-fix.patch delete mode 100644 recipes/linux/linux-omap-pm/dss2.diff create mode 100644 recipes/linux/linux-omap-pm/dss2/0001-Revert-gro-Fix-legacy-path-napi_complete-crash.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0002-OMAPFB-move-omapfb.h-to-include-linux.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0003-DSS2-OMAP2-3-Display-Subsystem-driver.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0004-DSS2-OMAP-framebuffer-driver.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0005-DSS2-Add-panel-drivers.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0006-DSS2-HACK-Add-DSS2-support-for-N800.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0007-DSS2-Add-DSS2-support-for-SDP-Beagle-Overo-EVM.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0008-DSS2-Add-function-to-display-object-to-get-the-back.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0009-DSS2-Add-acx565akm-panel.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0010-DSS2-Small-VRFB-context-allocation-bug-fixed.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0011-DSS2-Allocated-memory-for-Color-Look-up-table.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0012-DSS2-Fix-DMA-rotation.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0013-DSS2-Verify-that-overlay-paddr-0.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0014-DSS2-Add-function-to-get-DSS-logic-clock-rate.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0015-DSS2-DSI-calculate-VP_CLK_RATIO-properly.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0016-DSS2-DSI-improve-packet-len-calculation.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0017-DSS2-Disable-video-planes-on-sync-lost-error.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0018-DSS2-check-for-ovl-paddr-only-when-enabling.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0019-DSS2-Check-fclk-limits-when-configuring-video-plane.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0020-DSS2-Check-scaling-limits-against-proper-values.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0021-DSS2-Add-venc-register-dump.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0022-DSS2-FB-remove-unused-var-warning.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0023-DSS2-pass-the-default-FB-color-format-through-board.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0024-DSS2-Beagle-Use-gpio_set_value.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0025-DSS2-VRFB-Macro-for-calculating-base-address-of-th.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0026-DSS2-DSI-sidlemode-to-noidle-while-sending-frame.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0027-DSS2-VRFB-rotation-and-mirroring-implemented.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0028-DSS2-OMAPFB-Added-support-for-the-YUV-VRFB-rotatio.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0029-DSS2-OMAPFB-Set-line_length-correctly-for-YUV-with.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0030-DSS2-dispc_get_trans_key-was-returning-wrong-key-ty.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0031-DSS2-do-bootmem-reserve-for-exclusive-access.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0032-DSS2-Fix-DISPC_VID_FIR-value-for-omap34xx.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0033-DSS2-Prefer-3-tap-filter.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0034-DSS2-VRAM-improve-omap_vram_add_region.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0035-DSS2-Added-the-function-pointer-for-getting-default.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0036-DSS2-Added-support-for-setting-and-querying-alpha-b.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0037-DSS2-Added-support-for-querying-color-keying.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0038-DSS2-OMAPFB-Some-color-keying-pointerd-renamed-in-D.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0039-DSS2-Add-sysfs-entry-to-for-the-alpha-blending-supp.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0040-DSS2-Provided-proper-exclusion-for-destination-colo.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0041-DSS2-Disable-vertical-offset-with-fieldmode.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0042-DSS2-Don-t-enable-fieldmode-automatically.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0043-DSS2-Swap-field-0-and-field-1-registers.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0044-DSS2-add-sysfs-entry-for-seting-the-rotate-type.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0045-DSS2-Fixed-line-endings-from-to.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0046-DSS2-DSI-decrease-sync-timeout-from-60s-to-2s.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0047-DSS2-fix-return-value-for-rotate_type-sysfs-functio.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0048-OMAP2-3-DMA-implement-trans-copy-and-const-fill.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0049-DSS2-VRAM-clear-allocated-area-with-DMA.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0050-DSS2-OMAPFB-remove-fb-clearing-code.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0051-DSS2-VRAM-use-debugfs-not-procfs.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0052-DSS2-VRAM-fix-section-mismatch-warning.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/0053-DSS2-disable-LCD-DIGIT-before-resetting-DSS.patch create mode 100644 recipes/linux/linux-omap-pm/dss2/merge-fixups.diff delete mode 100644 recipes/linux/linux-omap-pm/dvb-fix-dma.diff create mode 100644 recipes/linux/linux-omap-pm/ehci.patch delete mode 100644 recipes/linux/linux-omap-pm/fix-clkrate-programming.diff delete mode 100644 recipes/linux/linux-omap-pm/fix-dpll-m4.diff delete mode 100644 recipes/linux/linux-omap-pm/fix-irq33.diff delete mode 100644 recipes/linux/linux-omap-pm/fixup-evm-cpufreq.diff delete mode 100644 recipes/linux/linux-omap-pm/ioremap-fix.patch delete mode 100644 recipes/linux/linux-omap-pm/mru-256MB.diff delete mode 100644 recipes/linux/linux-omap-pm/mru-enable-overlay-optimalization.diff delete mode 100644 recipes/linux/linux-omap-pm/mru-fix-display-panning.diff delete mode 100644 recipes/linux/linux-omap-pm/mru-fix-timings.diff delete mode 100644 recipes/linux/linux-omap-pm/mru-improve-pixclock-config.diff delete mode 100644 recipes/linux/linux-omap-pm/mru-make-video-timings-selectable.diff delete mode 100644 recipes/linux/linux-omap-pm/musb-support-high-bandwidth.patch.eml delete mode 100644 recipes/linux/linux-omap-pm/no-harry-potter.diff delete mode 100644 recipes/linux/linux-omap-pm/omap-2430-lcd.patch delete mode 100644 recipes/linux/linux-omap-pm/oprofile-0.9.3.armv7.diff create mode 100644 recipes/linux/linux-omap-pm/overo-cpufreq.diff create mode 100644 recipes/linux/linux-omap-pm/overo/defconfig create mode 100644 recipes/linux/linux-omap-pm/overo/ehci.patch delete mode 100644 recipes/linux/linux-omap-pm/register-all-OPPs.diff delete mode 100644 recipes/linux/linux-omap-pm/strongly-ordered-memory.diff delete mode 100644 recipes/linux/linux-omap-pm/tick-schedc-suppress-needless-timer-reprogramming.patch delete mode 100644 recipes/linux/linux-omap-pm/timer-suppression.patch delete mode 100644 recipes/linux/linux-omap-pm/touchscreen.patch delete mode 100644 recipes/linux/linux-omap-pm/twl-asoc-fix-record.diff delete mode 100644 recipes/linux/linux-omap-pm/usbttyfix.patch (limited to 'recipes/linux') diff --git a/recipes/linux/linux-omap-pm/0001-ASoC-Add-support-for-OMAP3-EVM.patch b/recipes/linux/linux-omap-pm/0001-ASoC-Add-support-for-OMAP3-EVM.patch deleted file mode 100644 index a76e96e444..0000000000 --- a/recipes/linux/linux-omap-pm/0001-ASoC-Add-support-for-OMAP3-EVM.patch +++ /dev/null @@ -1,206 +0,0 @@ -From c1dad0b6b434300ae64c902d11611c54c513ea10 Mon Sep 17 00:00:00 2001 -From: Anuj Aggarwal -Date: Fri, 21 Nov 2008 17:41:03 +0530 -Subject: [PATCH] ASoC: Add support for OMAP3 EVM - -This patch adds ALSA SoC support for OMAP3 EVM using TWL4030 audio codec. - -Signed-off-by: Anuj Aggarwal ---- - sound/soc/omap/Kconfig | 8 +++ - sound/soc/omap/Makefile | 3 +- - sound/soc/omap/omap3evm.c | 147 +++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 157 insertions(+), 1 deletions(-) - create mode 100644 sound/soc/omap/omap3evm.c - -diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig -index 0daeee4..deb6ba9 100644 ---- a/sound/soc/omap/Kconfig -+++ b/sound/soc/omap/Kconfig -@@ -22,6 +22,14 @@ config SND_OMAP_SOC_OMAP3_BEAGLE - help - Say Y if you want to add support for SoC audio on the Beagleboard. - -+config SND_OMAP_SOC_OMAP3EVM -+ tristate "SoC Audio support for OMAP3EVM board" -+ depends on SND_OMAP_SOC && MACH_OMAP3EVM -+ select SND_OMAP_SOC_MCBSP -+ select SND_SOC_TWL4030 -+ help -+ Say Y if you want to add support for SoC audio on the omap3evm board. -+ - config SND_OMAP_SOC_OSK5912 - tristate "SoC Audio support for omap osk5912" - depends on SND_OMAP_SOC && MACH_OMAP_OSK -diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile -index 4bae404..ef31c25 100644 ---- a/sound/soc/omap/Makefile -+++ b/sound/soc/omap/Makefile -@@ -10,9 +10,10 @@ snd-soc-n810-objs := n810.o - snd-soc-omap3beagle-objs := omap3beagle.o - snd-soc-osk5912-objs := osk5912.o - snd-soc-overo-objs := overo.o -+snd-soc-omap3evm-objs := omap3evm.o - - obj-$(CONFIG_SND_OMAP_SOC_N810) += snd-soc-n810.o - obj-$(CONFIG_SND_OMAP_SOC_OMAP3_BEAGLE) += snd-soc-omap3beagle.o - obj-$(CONFIG_SND_OMAP_SOC_OSK5912) += snd-soc-osk5912.o - obj-$(CONFIG_SND_OMAP_SOC_OVERO) += snd-soc-overo.o -- -+obj-$(CONFIG_MACH_OMAP3EVM) += snd-soc-omap3evm.o -diff --git a/sound/soc/omap/omap3evm.c b/sound/soc/omap/omap3evm.c -new file mode 100644 -index 0000000..570af55 ---- /dev/null -+++ b/sound/soc/omap/omap3evm.c -@@ -0,0 +1,147 @@ -+/* -+ * omap3evm.c -- ALSA SoC support for OMAP3 EVM -+ * -+ * Author: Anuj Aggarwal -+ * -+ * Based on sound/soc/omap/beagle.c by Steve Sakoman -+ * -+ * Copyright (C) 2008 Texas Instruments, Incorporated -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation version 2. -+ * -+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, -+ * whether express or implied; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include "omap-mcbsp.h" -+#include "omap-pcm.h" -+#include "../codecs/twl4030.h" -+ -+static int omap3evm_hw_params(struct snd_pcm_substream *substream, -+ struct snd_pcm_hw_params *params) -+{ -+ struct snd_soc_pcm_runtime *rtd = substream->private_data; -+ struct snd_soc_dai *codec_dai = rtd->dai->codec_dai; -+ struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; -+ int ret; -+ -+ /* Set codec DAI configuration */ -+ ret = snd_soc_dai_set_fmt(codec_dai, -+ SND_SOC_DAIFMT_I2S | -+ SND_SOC_DAIFMT_NB_NF | -+ SND_SOC_DAIFMT_CBM_CFM); -+ if (ret < 0) { -+ printk(KERN_ERR "can't set codec DAI configuration\n"); -+ return ret; -+ } -+ -+ /* Set cpu DAI configuration */ -+ ret = snd_soc_dai_set_fmt(cpu_dai, -+ SND_SOC_DAIFMT_I2S | -+ SND_SOC_DAIFMT_NB_NF | -+ SND_SOC_DAIFMT_CBM_CFM); -+ if (ret < 0) { -+ printk(KERN_ERR "can't set cpu DAI configuration\n"); -+ return ret; -+ } -+ -+ /* Set the codec system clock for DAC and ADC */ -+ ret = snd_soc_dai_set_sysclk(codec_dai, 0, 26000000, -+ SND_SOC_CLOCK_IN); -+ if (ret < 0) { -+ printk(KERN_ERR "can't set codec system clock\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static struct snd_soc_ops omap3evm_ops = { -+ .hw_params = omap3evm_hw_params, -+}; -+ -+/* Digital audio interface glue - connects codec <--> CPU */ -+static struct snd_soc_dai_link omap3evm_dai = { -+ .name = "TWL4030", -+ .stream_name = "TWL4030", -+ .cpu_dai = &omap_mcbsp_dai[0], -+ .codec_dai = &twl4030_dai, -+ .ops = &omap3evm_ops, -+}; -+ -+/* Audio machine driver */ -+static struct snd_soc_machine snd_soc_machine_omap3evm = { -+ .name = "omap3evm", -+ .dai_link = &omap3evm_dai, -+ .num_links = 1, -+}; -+ -+/* Audio subsystem */ -+static struct snd_soc_device omap3evm_snd_devdata = { -+ .machine = &snd_soc_machine_omap3evm, -+ .platform = &omap_soc_platform, -+ .codec_dev = &soc_codec_dev_twl4030, -+}; -+ -+static struct platform_device *omap3evm_snd_device; -+ -+static int __init omap3evm_soc_init(void) -+{ -+ int ret; -+ -+ if (!machine_is_omap3evm()) { -+ pr_debug("Not OMAP3 EVM!\n"); -+ return -ENODEV; -+ } -+ pr_info("OMAP3 EVM SoC init\n"); -+ -+ omap3evm_snd_device = platform_device_alloc("soc-audio", -1); -+ if (!omap3evm_snd_device) { -+ printk(KERN_ERR "Platform device allocation failed\n"); -+ return -ENOMEM; -+ } -+ -+ platform_set_drvdata(omap3evm_snd_device, &omap3evm_snd_devdata); -+ omap3evm_snd_devdata.dev = &omap3evm_snd_device->dev; -+ *(unsigned int *)omap3evm_dai.cpu_dai->private_data = 1; /* McBSP2 */ -+ -+ ret = platform_device_add(omap3evm_snd_device); -+ if (ret) -+ goto err1; -+ -+ return 0; -+ -+err1: -+ printk(KERN_ERR "Unable to add platform device\n"); -+ platform_device_put(omap3evm_snd_device); -+ -+ return ret; -+} -+ -+static void __exit omap3evm_soc_exit(void) -+{ -+ platform_device_unregister(omap3evm_snd_device); -+} -+ -+module_init(omap3evm_soc_init); -+module_exit(omap3evm_soc_exit); -+ -+MODULE_AUTHOR("Anuj Aggarwal "); -+MODULE_DESCRIPTION("ALSA SoC OMAP3 EVM"); -+MODULE_LICENSE("GPL"); --- -1.5.6.5 - diff --git a/recipes/linux/linux-omap-pm/0001-DSS-New-display-subsystem-driver-for-OMAP2-3.patch b/recipes/linux/linux-omap-pm/0001-DSS-New-display-subsystem-driver-for-OMAP2-3.patch deleted file mode 100644 index 2c77fcc205..0000000000 --- a/recipes/linux/linux-omap-pm/0001-DSS-New-display-subsystem-driver-for-OMAP2-3.patch +++ /dev/null @@ -1,10355 +0,0 @@ -From 3128e95ff7e6a1bed47cc5c64a138cc3bbab492a Mon Sep 17 00:00:00 2001 -From: Tomi Valkeinen -Date: Wed, 7 Jan 2009 14:30:09 +0200 -Subject: [PATCH] DSS: New display subsystem driver for OMAP2/3 - -Signed-off-by: Tomi Valkeinen ---- - Documentation/arm/OMAP/DSS | 266 +++ - arch/arm/plat-omap/Kconfig | 2 + - arch/arm/plat-omap/Makefile | 2 + - arch/arm/plat-omap/dss/Kconfig | 69 + - arch/arm/plat-omap/dss/Makefile | 6 + - arch/arm/plat-omap/dss/dispc.c | 2113 +++++++++++++++++++ - arch/arm/plat-omap/dss/display.c | 787 +++++++ - arch/arm/plat-omap/dss/dpi.c | 344 ++++ - arch/arm/plat-omap/dss/dsi.c | 3187 +++++++++++++++++++++++++++++ - arch/arm/plat-omap/dss/dss.c | 774 +++++++ - arch/arm/plat-omap/dss/dss.h | 274 +++ - arch/arm/plat-omap/dss/rfbi.c | 1262 ++++++++++++ - arch/arm/plat-omap/dss/sdi.c | 174 ++ - arch/arm/plat-omap/dss/venc.c | 506 +++++ - arch/arm/plat-omap/include/mach/display.h | 462 +++++ - 15 files changed, 10228 insertions(+), 0 deletions(-) - create mode 100644 Documentation/arm/OMAP/DSS - create mode 100644 arch/arm/plat-omap/dss/Kconfig - create mode 100644 arch/arm/plat-omap/dss/Makefile - create mode 100644 arch/arm/plat-omap/dss/dispc.c - create mode 100644 arch/arm/plat-omap/dss/display.c - create mode 100644 arch/arm/plat-omap/dss/dpi.c - create mode 100644 arch/arm/plat-omap/dss/dsi.c - create mode 100644 arch/arm/plat-omap/dss/dss.c - create mode 100644 arch/arm/plat-omap/dss/dss.h - create mode 100644 arch/arm/plat-omap/dss/rfbi.c - create mode 100644 arch/arm/plat-omap/dss/sdi.c - create mode 100644 arch/arm/plat-omap/dss/venc.c - create mode 100644 arch/arm/plat-omap/include/mach/display.h - -diff --git a/Documentation/arm/OMAP/DSS b/Documentation/arm/OMAP/DSS -new file mode 100644 -index 0000000..a5e608c ---- /dev/null -+++ b/Documentation/arm/OMAP/DSS -@@ -0,0 +1,266 @@ -+OMAP2/3 Display Subsystem -+------------------------- -+ -+This is an almost total rewrite of the OMAP FB driver in drivers/video/omap -+(let's call it DSS1). The main differences between DSS1 and DSS2 are DSI, -+TV-out and multiple display support. -+ -+The DSS2 driver (omap-dss module) is in arch/arm/plat-omap/dss/, and the FB, -+panel and controller drivers are in drivers/video/omap2/. DSS1 and DSS2 live -+currently side by side, you can choose which one to use. -+ -+Features -+-------- -+ -+Working and tested features include: -+ -+- MIPI DPI (parallel) output -+- MIPI DSI output in command mode -+- MIPI DBI (RFBI) output (not tested for a while, might've gotten broken) -+- SDI output -+- TV output -+- All pieces can be compiled as a module or inside kernel -+- Use DISPC to update any of the outputs -+- Use CPU to update RFBI or DSI output -+- OMAP DISPC planes -+- RGB16, RGB24 packed, RGB24 unpacked -+- YUV2, UYVY -+- Scaling -+- Adjusting DSS FCK to find a good pixel clock -+- Use DSI DPLL to create DSS FCK -+ -+omap-dss driver -+------------ -+ -+The DSS driver does not itself have any support for Linux framebuffer, V4L or -+such like the current ones, but it has an internal kernel API that upper level -+drivers can use. -+ -+The DSS driver models OMAP's overlays, overlay managers and displays in a -+flexible way to enable non-common multi-display configuration. In addition to -+modelling the hardware overlays, omap-dss supports virtual overlays and overlay -+managers. These can be used when updating a display with CPU or system DMA. -+ -+Panel and controller drivers -+---------------------------- -+ -+The drivers implement panel or controller specific functionality and are not -+visible to users except through omapfb driver. They register themselves to the -+DSS driver. -+ -+omapfb driver -+------------- -+ -+The omapfb driver implements arbitrary number of standard linux framebuffers. -+These framebuffers can be routed flexibly to any overlays, thus allowing very -+dynamic display architecture. -+ -+The driver exports some omapfb specific ioctls, which are compatible with the -+ioctls in the old driver. -+ -+The rest of the non standard features are exported via sysfs. Whether the final -+implementation will use sysfs, or ioctls, is still open. -+ -+V4L2 drivers -+------------ -+ -+Currently there are no V4L2 display drivers planned, but it is possible to -+implement such either to omapfb driver, or as a separate one. From omap-dss -+point of view the V4L2 drivers should be similar to framebuffer driver. -+ -+Architecture -+-------------------- -+ -+Some clarification what the different components do: -+ -+ - Framebuffer is a memory area inside OMAP's SDRAM that contains the pixel -+ data for the image. Framebuffer has width and height and color depth. -+ - Overlay defines where the pixels are read from and where they go on the -+ screen. The overlay may be smaller than framebuffer, thus displaying only -+ part of the framebuffer. The position of the overlay may be changed if -+ the overlay is smaller than the display. -+ - Overlay manager combines the overlays in to one image and feeds them to -+ display. -+ - Display is the actual physical display device. -+ -+A framebuffer can be connected to multiple overlays to show the same pixel data -+on all of the overlays. Note that in this case the overlay input sizes must be -+the same, but, in case of video overlays, the output size can be different. Any -+framebuffer can be connected to any overlay. -+ -+An overlay can be connected to one overlay manager. Also DISPC overlays can be -+connected only to DISPC overlay managers, and virtual overlays can be only -+connected to virtual overlays. -+ -+An overlay manager can be connected to one display. There are certain -+restrictions which kinds of displays an overlay manager can be connected: -+ -+ - DISPC TV overlay manager can be only connected to TV display. -+ - Virtual overlay managers can only be connected to DBI or DSI displays. -+ - DISPC LCD overlay manager can be connected to all displays, except TV -+ display. -+ -+Sysfs -+----- -+The sysfs interface is a hack, but works for testing. I don't think sysfs -+interface is the best for this in the final version, but I don't quite know -+what would be the best interfaces for these things. -+ -+In /sys/devices/platform/omapfb we have four files: framebuffers, -+overlays, managers and displays. You can read them so see the current -+setup, and change them by writing to it in the form of -+" : :..." -+ -+"framebuffers" lists all framebuffers. Its format is: -+ -+ p: -+ v: -+ s: -+ t: -+ -+"overlays" lists all overlays. Its format is: -+ -+ t: -+ x: -+ y: -+ iw: -+ ih: -+ w: -+ h: -+ e: -+ -+"managers" lists all overlay managers. Its format is: -+ -+ t: -+ -+"displays" lists all displays. Its format is: -+ -+ e: -+ u: -+ t: -+ h: -+ v: -+ p: -+ m: -+ -+There is also a debug sysfs file at /sys/devices/platform/omap-dss/clk which -+shows how DSS has configured the clocks. -+ -+Examples -+-------- -+ -+In the example scripts "omapfb" is a symlink to /sys/devices/platform/omapfb/. -+ -+Default setup on OMAP3 SDP -+-------------------------- -+ -+Here's the default setup on OMAP3 SDP board. All planes go to LCD. DVI -+and TV-out are not in use. The columns from left to right are: -+framebuffers, overlays, overlay managers, displays. Framebuffers are -+handled by omapfb, and the rest by the DSS. -+ -+FB0 --- GFX -\ DVI -+FB1 --- VID1 --+- LCD ---- LCD -+FB2 --- VID2 -/ TV ----- TV -+ -+Switch from LCD to DVI -+---------------------- -+ -+dviline=`cat omapfb/displays |grep dvi` -+w=`echo $dviline | cut -d " " -f 5 | cut -d ":" -f 2 | cut -d "/" -f 1` -+h=`echo $dviline | cut -d " " -f 6 | cut -d ":" -f 2 | cut -d "/" -f 1` -+ -+echo "lcd e:0" > omapfb/displays -+echo "lcd t:none" > omapfb/managers -+fbset -fb /dev/fb0 -xres $w -yres $h -+# at this point you have to switch the dvi/lcd dip-switch from the omap board -+echo "lcd t:dvi" > omapfb/managers -+echo "dvi e:1" > omapfb/displays -+ -+After this the configuration looks like: -+ -+FB0 --- GFX -\ -- DVI -+FB1 --- VID1 --+- LCD -/ LCD -+FB2 --- VID2 -/ TV ----- TV -+ -+Clone GFX overlay to LCD and TV -+------------------------------- -+ -+tvline=`cat /sys/devices/platform/omapfb/displays |grep tv` -+w=`echo $tvline | cut -d " " -f 5 | cut -d ":" -f 2 | cut -d "/" -f 1` -+h=`echo $tvline | cut -d " " -f 6 | cut -d ":" -f 2 | cut -d "/" -f 1` -+ -+echo "1 t:none" > omapfb/framebuffers -+echo "0 t:gfx,vid1" > omapfb/framebuffers -+echo "gfx e:1" > omapfb/overlays -+echo "vid1 t:tv w:$w h:$h e:1" > omapfb/overlays -+echo "tv e:1" > omapfb/displays -+ -+After this the configuration looks like (only relevant parts shown): -+ -+FB0 +-- GFX ---- LCD ---- LCD -+ \- VID1 ---- TV ---- TV -+ -+Misc notes -+---------- -+ -+OMAP FB allocates the framebuffer memory using the OMAP VRAM allocator. If -+that fails, it will fall back to dma_alloc_writecombine(). -+ -+Using DSI DPLL to generate pixel clock it is possible produce the pixel clock -+of 86.5MHz (max possible), and with that you get 1280x1024@57 output from DVI. -+ -+Arguments -+--------- -+ -+vram -+ - Amount of total VRAM to preallocate. For example, "10M". -+ -+omapfb.video_mode -+ - Default video mode for default display. For example, -+ "800x400MR-24@60". See drivers/video/modedb.c -+ -+omapfb.vram -+ - VRAM allocated for each framebuffer. Normally omapfb allocates vram -+ depending on the display size. With this you can manually allocate -+ more. For example "4M,3M" allocates 4M for fb0, 3M for fb1. -+ -+omapfb.debug -+ - Enable debug printing. You have to have OMAPFB debug support enabled -+ in kernel config. -+ -+omap-dss.def_disp -+ - Name of default display, to which all overlays will be connected. -+ Common examples are "lcd" or "tv". -+ -+omap-dss.debug -+ - Enable debug printing. You have to have DSS debug support enabled in -+ kernel config. -+ -+TODO -+---- -+ -+DSS locking -+ -+Error checking -+- Lots of checks are missing or implemented just as BUG() -+ -+Rotate (external FB) -+Rotate (VRFB) -+Rotate (SMS) -+ -+System DMA update for DSI -+- Can be used for RGB16 and RGB24P modes. Probably not for RGB24U (how -+ to skip the empty byte?) -+ -+Power management -+- Context saving -+ -+Resolution change -+- The x/y res of the framebuffer are not display resolutions, but the size -+ of the overlay. -+- The display resolution affects all planes on the display. -+ -+OMAP1 support -+- Not sure if needed -+ -diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig -index 2465aea..cd7d9e2 100644 ---- a/arch/arm/plat-omap/Kconfig -+++ b/arch/arm/plat-omap/Kconfig -@@ -245,6 +245,8 @@ config OMAP_SERIAL_WAKE - to data on the serial RX line. This allows you to wake the - system from serial console. - -+source "arch/arm/plat-omap/dss/Kconfig" -+ - endmenu - - endif -diff --git a/arch/arm/plat-omap/dss/Kconfig b/arch/arm/plat-omap/dss/Kconfig -new file mode 100644 -index 0000000..6b342df ---- /dev/null -+++ b/arch/arm/plat-omap/dss/Kconfig -@@ -0,0 +1,69 @@ -+config OMAP2_DSS -+ tristate "OMAP2/3 Display Subsystem support (EXPERIMENTAL)" -+ depends on ARCH_OMAP2 || ARCH_OMAP3 -+ help -+ OMAP2/3 Display Subsystem support. -+ -+if OMAP2_DSS -+ -+config OMAP2_DSS_DEBUG_SUPPORT -+ bool "Debug support" -+ default y -+ help -+ This enables debug messages. You need to enable printing -+ with 'debug' module parameter. -+ -+config OMAP2_DSS_RFBI -+ bool "RFBI support" -+ default y -+ -+config OMAP2_DSS_VENC -+ bool "VENC support" -+ default y -+ -+if ARCH_OMAP3 -+ -+config OMAP2_DSS_SDI -+ bool "SDI support" -+ default y -+ -+config OMAP2_DSS_DSI -+ bool "DSI support" -+ default y -+ -+endif -+ -+config OMAP2_DSS_USE_DSI_PLL -+ bool "Use DSI PLL for PCLK (EXPERIMENTAL)" -+ default n -+ depends on OMAP2_DSS_DSI -+ help -+ Use DSI PLL to generate pixel clock. -+ Currently only for DPI output. -+ -+config OMAP2_DSS_FAKE_VSYNC -+ bool "Fake VSYNC irq from manual update displays" -+ default n -+ help -+ If this is selected, DSI will fake a DISPC VSYNC interrupt -+ when DSI has sent a frame. -+ -+config OMAP2_DSS_MIN_FCK_PER_PCK -+ int "Minimum FCK/PCK ratio (for scaling)" -+ range 0 32 -+ default 0 -+ help -+ This can be used to adjust the minimum FCK/PCK ratio. -+ -+ With this you can make sure that DISPC FCK is at least -+ n x PCK. Video plane scaling requires higher FCK than -+ normally. -+ -+ If this is set to 0, there's no extra constraint on the -+ DISPC FCK. However, the FCK will at minimum be -+ 2xPCK (if active matrix) or 3xPCK (if passive matrix). -+ -+ Max FCK is 173MHz, so this doesn't work if your PCK -+ is very high. -+ -+endif -diff --git a/arch/arm/plat-omap/dss/Makefile b/arch/arm/plat-omap/dss/Makefile -new file mode 100644 -index 0000000..e98c6c1 ---- /dev/null -+++ b/arch/arm/plat-omap/dss/Makefile -@@ -0,0 +1,6 @@ -+obj-$(CONFIG_OMAP2_DSS) += omap-dss.o -+omap-dss-y := dss.o display.o dispc.o dpi.o -+omap-dss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o -+omap-dss-$(CONFIG_OMAP2_DSS_VENC) += venc.o -+omap-dss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o -+omap-dss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o -diff --git a/arch/arm/plat-omap/dss/dispc.c b/arch/arm/plat-omap/dss/dispc.c -new file mode 100644 -index 0000000..20caa48 ---- /dev/null -+++ b/arch/arm/plat-omap/dss/dispc.c -@@ -0,0 +1,2113 @@ -+/* -+ * linux/arch/arm/plat-omap/dss/dispc.c -+ * -+ * Copyright (C) 2008 Nokia Corporation -+ * Author: Tomi Valkeinen -+ * -+ * Some code and ideas taken from drivers/video/omap/ driver -+ * by Imre Deak. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+#define DSS_SUBSYS_NAME "DISPC" -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include -+ -+#include "dss.h" -+ -+/* DISPC */ -+#define DISPC_BASE 0x48050400 -+ -+#define DISPC_SZ_REGS SZ_1K -+ -+struct dispc_reg { u16 idx; }; -+ -+#define DISPC_REG(idx) ((const struct dispc_reg) { idx }) -+ -+/* DISPC common */ -+#define DISPC_REVISION DISPC_REG(0x0000) -+#define DISPC_SYSCONFIG DISPC_REG(0x0010) -+#define DISPC_SYSSTATUS DISPC_REG(0x0014) -+#define DISPC_IRQSTATUS DISPC_REG(0x0018) -+#define DISPC_IRQENABLE DISPC_REG(0x001C) -+#define DISPC_CONTROL DISPC_REG(0x0040) -+#define DISPC_CONFIG DISPC_REG(0x0044) -+#define DISPC_CAPABLE DISPC_REG(0x0048) -+#define DISPC_DEFAULT_COLOR0 DISPC_REG(0x004C) -+#define DISPC_DEFAULT_COLOR1 DISPC_REG(0x0050) -+#define DISPC_TRANS_COLOR0 DISPC_REG(0x0054) -+#define DISPC_TRANS_COLOR1 DISPC_REG(0x0058) -+#define DISPC_LINE_STATUS DISPC_REG(0x005C) -+#define DISPC_LINE_NUMBER DISPC_REG(0x0060) -+#define DISPC_TIMING_H DISPC_REG(0x0064) -+#define DISPC_TIMING_V DISPC_REG(0x0068) -+#define DISPC_POL_FREQ DISPC_REG(0x006C) -+#define DISPC_DIVISOR DISPC_REG(0x0070) -+#define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074) -+#define DISPC_SIZE_DIG DISPC_REG(0x0078) -+#define DISPC_SIZE_LCD DISPC_REG(0x007C) -+ -+/* DISPC GFX plane */ -+#define DISPC_GFX_BA0 DISPC_REG(0x0080) -+#define DISPC_GFX_BA1 DISPC_REG(0x0084) -+#define DISPC_GFX_POSITION DISPC_REG(0x0088) -+#define DISPC_GFX_SIZE DISPC_REG(0x008C) -+#define DISPC_GFX_ATTRIBUTES DISPC_REG(0x00A0) -+#define DISPC_GFX_FIFO_THRESHOLD DISPC_REG(0x00A4) -+#define DISPC_GFX_FIFO_SIZE_STATUS DISPC_REG(0x00A8) -+#define DISPC_GFX_ROW_INC DISPC_REG(0x00AC) -+#define DISPC_GFX_PIXEL_INC DISPC_REG(0x00B0) -+#define DISPC_GFX_WINDOW_SKIP DISPC_REG(0x00B4) -+#define DISPC_GFX_TABLE_BA DISPC_REG(0x00B8) -+ -+#define DISPC_DATA_CYCLE1 DISPC_REG(0x01D4) -+#define DISPC_DATA_CYCLE2 DISPC_REG(0x01D8) -+#define DISPC_DATA_CYCLE3 DISPC_REG(0x01DC) -+ -+#define DISPC_CPR_COEF_R DISPC_REG(0x0220) -+#define DISPC_CPR_COEF_G DISPC_REG(0x0224) -+#define DISPC_CPR_COEF_B DISPC_REG(0x0228) -+ -+#define DISPC_GFX_PRELOAD DISPC_REG(0x022C) -+ -+/* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */ -+#define DISPC_VID_REG(n, idx) DISPC_REG(0x00BC + (n)*0x90 + idx) -+ -+#define DISPC_VID_BA0(n) DISPC_VID_REG(n, 0x0000) -+#define DISPC_VID_BA1(n) DISPC_VID_REG(n, 0x0004) -+#define DISPC_VID_POSITION(n) DISPC_VID_REG(n, 0x0008) -+#define DISPC_VID_SIZE(n) DISPC_VID_REG(n, 0x000C) -+#define DISPC_VID_ATTRIBUTES(n) DISPC_VID_REG(n, 0x0010) -+#define DISPC_VID_FIFO_THRESHOLD(n) DISPC_VID_REG(n, 0x0014) -+#define DISPC_VID_FIFO_SIZE_STATUS(n) DISPC_VID_REG(n, 0x0018) -+#define DISPC_VID_ROW_INC(n) DISPC_VID_REG(n, 0x001C) -+#define DISPC_VID_PIXEL_INC(n) DISPC_VID_REG(n, 0x0020) -+#define DISPC_VID_FIR(n) DISPC_VID_REG(n, 0x0024) -+#define DISPC_VID_PICTURE_SIZE(n) DISPC_VID_REG(n, 0x0028) -+#define DISPC_VID_ACCU0(n) DISPC_VID_REG(n, 0x002C) -+#define DISPC_VID_ACCU1(n) DISPC_VID_REG(n, 0x0030) -+ -+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ -+#define DISPC_VID_FIR_COEF_H(n, i) DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8) -+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ -+#define DISPC_VID_FIR_COEF_HV(n, i) DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8) -+/* coef index i = {0, 1, 2, 3, 4} */ -+#define DISPC_VID_CONV_COEF(n, i) DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4) -+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ -+#define DISPC_VID_FIR_COEF_V(n, i) DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4) -+ -+#define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04) -+ -+ -+#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \ -+ DISPC_IRQ_OCP_ERR | \ -+ DISPC_IRQ_VID1_FIFO_UNDERFLOW | \ -+ DISPC_IRQ_VID2_FIFO_UNDERFLOW | \ -+ DISPC_IRQ_SYNC_LOST | \ -+ DISPC_IRQ_SYNC_LOST_DIGIT) -+ -+#define DISPC_MAX_NR_ISRS 8 -+ -+static struct { -+ omap_dispc_isr_t isr; -+ void *arg; -+ u32 mask; -+} registered_isr[DISPC_MAX_NR_ISRS]; -+ -+#define REG_GET(idx, start, end) \ -+ FLD_GET(dispc_read_reg(idx), start, end) -+ -+#define REG_FLD_MOD(idx, val, start, end) \ -+ dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end)) -+ -+static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES, -+ DISPC_VID_ATTRIBUTES(0), -+ DISPC_VID_ATTRIBUTES(1) }; -+ -+static struct { -+ void __iomem *base; -+ -+ struct clk *dpll4_m4_ck; -+ -+ spinlock_t irq_lock; -+ -+ unsigned long cache_req_pck; -+ unsigned long cache_prate; -+ struct dispc_clock_info cache_cinfo; -+ -+ u32 ctx[DISPC_SZ_REGS / sizeof(u32)]; -+} dispc; -+ -+static inline void dispc_write_reg(const struct dispc_reg idx, u32 val) -+{ -+ __raw_writel(val, dispc.base + idx.idx); -+} -+ -+static inline u32 dispc_read_reg(const struct dispc_reg idx) -+{ -+ return __raw_readl(dispc.base + idx.idx); -+} -+ -+#define SR(reg) \ -+ dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg) -+#define RR(reg) \ -+ dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)]) -+ -+void dispc_save_context(void) -+{ -+ if (cpu_is_omap24xx()) -+ return; -+ -+ SR(SYSCONFIG); -+ SR(IRQENABLE); -+ SR(CONTROL); -+ SR(CONFIG); -+ SR(DEFAULT_COLOR0); -+ SR(DEFAULT_COLOR1); -+ SR(TRANS_COLOR0); -+ SR(TRANS_COLOR1); -+ SR(LINE_NUMBER); -+ SR(TIMING_H); -+ SR(TIMING_V); -+ SR(POL_FREQ); -+ SR(DIVISOR); -+ SR(GLOBAL_ALPHA); -+ SR(SIZE_DIG); -+ SR(SIZE_LCD); -+ -+ SR(GFX_BA0); -+ SR(GFX_BA1); -+ SR(GFX_POSITION); -+ SR(GFX_SIZE); -+ SR(GFX_ATTRIBUTES); -+ SR(GFX_FIFO_THRESHOLD); -+ SR(GFX_ROW_INC); -+ SR(GFX_PIXEL_INC); -+ SR(GFX_WINDOW_SKIP); -+ SR(GFX_TABLE_BA); -+ -+ SR(DATA_CYCLE1); -+ SR(DATA_CYCLE2); -+ SR(DATA_CYCLE3); -+ -+ SR(CPR_COEF_R); -+ SR(CPR_COEF_G); -+ SR(CPR_COEF_B); -+ -+ SR(GFX_PRELOAD); -+ -+ /* VID1 */ -+ SR(VID_BA0(0)); -+ SR(VID_BA1(0)); -+ SR(VID_POSITION(0)); -+ SR(VID_SIZE(0)); -+ SR(VID_ATTRIBUTES(0)); -+ SR(VID_FIFO_THRESHOLD(0)); -+ SR(VID_ROW_INC(0)); -+ SR(VID_PIXEL_INC(0)); -+ SR(VID_FIR(0)); -+ SR(VID_PICTURE_SIZE(0)); -+ SR(VID_ACCU0(0)); -+ SR(VID_ACCU1(0)); -+ -+ SR(VID_FIR_COEF_H(0, 0)); -+ SR(VID_FIR_COEF_H(0, 1)); -+ SR(VID_FIR_COEF_H(0, 2)); -+ SR(VID_FIR_COEF_H(0, 3)); -+ SR(VID_FIR_COEF_H(0, 4)); -+ SR(VID_FIR_COEF_H(0, 5)); -+ SR(VID_FIR_COEF_H(0, 6)); -+ SR(VID_FIR_COEF_H(0, 7)); -+ -+ SR(VID_FIR_COEF_HV(0, 0)); -+ SR(VID_FIR_COEF_HV(0, 1)); -+ SR(VID_FIR_COEF_HV(0, 2)); -+ SR(VID_FIR_COEF_HV(0, 3)); -+ SR(VID_FIR_COEF_HV(0, 4)); -+ SR(VID_FIR_COEF_HV(0, 5)); -+ SR(VID_FIR_COEF_HV(0, 6)); -+ SR(VID_FIR_COEF_HV(0, 7)); -+ -+ SR(VID_CONV_COEF(0, 0)); -+ SR(VID_CONV_COEF(0, 1)); -+ SR(VID_CONV_COEF(0, 2)); -+ SR(VID_CONV_COEF(0, 3)); -+ SR(VID_CONV_COEF(0, 4)); -+ -+ SR(VID_FIR_COEF_V(0, 0)); -+ SR(VID_FIR_COEF_V(0, 1)); -+ SR(VID_FIR_COEF_V(0, 2)); -+ SR(VID_FIR_COEF_V(0, 3)); -+ SR(VID_FIR_COEF_V(0, 4)); -+ SR(VID_FIR_COEF_V(0, 5)); -+ SR(VID_FIR_COEF_V(0, 6)); -+ SR(VID_FIR_COEF_V(0, 7)); -+ -+ SR(VID_PRELOAD(0)); -+ -+ /* VID2 */ -+ SR(VID_BA0(1)); -+ SR(VID_BA1(1)); -+ SR(VID_POSITION(1)); -+ SR(VID_SIZE(1)); -+ SR(VID_ATTRIBUTES(1)); -+ SR(VID_FIFO_THRESHOLD(1)); -+ SR(VID_ROW_INC(1)); -+ SR(VID_PIXEL_INC(1)); -+ SR(VID_FIR(1)); -+ SR(VID_PICTURE_SIZE(1)); -+ SR(VID_ACCU0(1)); -+ SR(VID_ACCU1(1)); -+ -+ SR(VID_FIR_COEF_H(1, 0)); -+ SR(VID_FIR_COEF_H(1, 1)); -+ SR(VID_FIR_COEF_H(1, 2)); -+ SR(VID_FIR_COEF_H(1, 3)); -+ SR(VID_FIR_COEF_H(1, 4)); -+ SR(VID_FIR_COEF_H(1, 5)); -+ SR(VID_FIR_COEF_H(1, 6)); -+ SR(VID_FIR_COEF_H(1, 7)); -+ -+ SR(VID_FIR_COEF_HV(1, 0)); -+ SR(VID_FIR_COEF_HV(1, 1)); -+ SR(VID_FIR_COEF_HV(1, 2)); -+ SR(VID_FIR_COEF_HV(1, 3)); -+ SR(VID_FIR_COEF_HV(1, 4)); -+ SR(VID_FIR_COEF_HV(1, 5)); -+ SR(VID_FIR_COEF_HV(1, 6)); -+ SR(VID_FIR_COEF_HV(1, 7)); -+ -+ SR(VID_CONV_COEF(1, 0)); -+ SR(VID_CONV_COEF(1, 1)); -+ SR(VID_CONV_COEF(1, 2)); -+ SR(VID_CONV_COEF(1, 3)); -+ SR(VID_CONV_COEF(1, 4)); -+ -+ SR(VID_FIR_COEF_V(1, 0)); -+ SR(VID_FIR_COEF_V(1, 1)); -+ SR(VID_FIR_COEF_V(1, 2)); -+ SR(VID_FIR_COEF_V(1, 3)); -+ SR(VID_FIR_COEF_V(1, 4)); -+ SR(VID_FIR_COEF_V(1, 5)); -+ SR(VID_FIR_COEF_V(1, 6)); -+ SR(VID_FIR_COEF_V(1, 7)); -+ -+ SR(VID_PRELOAD(1)); -+} -+ -+void dispc_restore_context(void) -+{ -+ RR(SYSCONFIG); -+ RR(IRQENABLE); -+ /*RR(CONTROL);*/ -+ RR(CONFIG); -+ RR(DEFAULT_COLOR0); -+ RR(DEFAULT_COLOR1); -+ RR(TRANS_COLOR0); -+ RR(TRANS_COLOR1); -+ RR(LINE_NUMBER); -+ RR(TIMING_H); -+ RR(TIMING_V); -+ RR(POL_FREQ); -+ RR(DIVISOR); -+ RR(GLOBAL_ALPHA); -+ RR(SIZE_DIG); -+ RR(SIZE_LCD); -+ -+ RR(GFX_BA0); -+ RR(GFX_BA1); -+ RR(GFX_POSITION); -+ RR(GFX_SIZE); -+ RR(GFX_ATTRIBUTES); -+ RR(GFX_FIFO_THRESHOLD); -+ RR(GFX_ROW_INC); -+ RR(GFX_PIXEL_INC); -+ RR(GFX_WINDOW_SKIP); -+ RR(GFX_TABLE_BA); -+ -+ RR(DATA_CYCLE1); -+ RR(DATA_CYCLE2); -+ RR(DATA_CYCLE3); -+ -+ RR(CPR_COEF_R); -+ RR(CPR_COEF_G); -+ RR(CPR_COEF_B); -+ -+ RR(GFX_PRELOAD); -+ -+ /* VID1 */ -+ RR(VID_BA0(0)); -+ RR(VID_BA1(0)); -+ RR(VID_POSITION(0)); -+ RR(VID_SIZE(0)); -+ RR(VID_ATTRIBUTES(0)); -+ RR(VID_FIFO_THRESHOLD(0)); -+ RR(VID_ROW_INC(0)); -+ RR(VID_PIXEL_INC(0)); -+ RR(VID_FIR(0)); -+ RR(VID_PICTURE_SIZE(0)); -+ RR(VID_ACCU0(0)); -+ RR(VID_ACCU1(0)); -+ -+ RR(VID_FIR_COEF_H(0, 0)); -+ RR(VID_FIR_COEF_H(0, 1)); -+ RR(VID_FIR_COEF_H(0, 2)); -+ RR(VID_FIR_COEF_H(0, 3)); -+ RR(VID_FIR_COEF_H(0, 4)); -+ RR(VID_FIR_COEF_H(0, 5)); -+ RR(VID_FIR_COEF_H(0, 6)); -+ RR(VID_FIR_COEF_H(0, 7)); -+ -+ RR(VID_FIR_COEF_HV(0, 0)); -+ RR(VID_FIR_COEF_HV(0, 1)); -+ RR(VID_FIR_COEF_HV(0, 2)); -+ RR(VID_FIR_COEF_HV(0, 3)); -+ RR(VID_FIR_COEF_HV(0, 4)); -+ RR(VID_FIR_COEF_HV(0, 5)); -+ RR(VID_FIR_COEF_HV(0, 6)); -+ RR(VID_FIR_COEF_HV(0, 7)); -+ -+ RR(VID_CONV_COEF(0, 0)); -+ RR(VID_CONV_COEF(0, 1)); -+ RR(VID_CONV_COEF(0, 2)); -+ RR(VID_CONV_COEF(0, 3)); -+ RR(VID_CONV_COEF(0, 4)); -+ -+ RR(VID_FIR_COEF_V(0, 0)); -+ RR(VID_FIR_COEF_V(0, 1)); -+ RR(VID_FIR_COEF_V(0, 2)); -+ RR(VID_FIR_COEF_V(0, 3)); -+ RR(VID_FIR_COEF_V(0, 4)); -+ RR(VID_FIR_COEF_V(0, 5)); -+ RR(VID_FIR_COEF_V(0, 6)); -+ RR(VID_FIR_COEF_V(0, 7)); -+ -+ RR(VID_PRELOAD(0)); -+ -+ /* VID2 */ -+ RR(VID_BA0(1)); -+ RR(VID_BA1(1)); -+ RR(VID_POSITION(1)); -+ RR(VID_SIZE(1)); -+ RR(VID_ATTRIBUTES(1)); -+ RR(VID_FIFO_THRESHOLD(1)); -+ RR(VID_ROW_INC(1)); -+ RR(VID_PIXEL_INC(1)); -+ RR(VID_FIR(1)); -+ RR(VID_PICTURE_SIZE(1)); -+ RR(VID_ACCU0(1)); -+ RR(VID_ACCU1(1)); -+ -+ RR(VID_FIR_COEF_H(1, 0)); -+ RR(VID_FIR_COEF_H(1, 1)); -+ RR(VID_FIR_COEF_H(1, 2)); -+ RR(VID_FIR_COEF_H(1, 3)); -+ RR(VID_FIR_COEF_H(1, 4)); -+ RR(VID_FIR_COEF_H(1, 5)); -+ RR(VID_FIR_COEF_H(1, 6)); -+ RR(VID_FIR_COEF_H(1, 7)); -+ -+ RR(VID_FIR_COEF_HV(1, 0)); -+ RR(VID_FIR_COEF_HV(1, 1)); -+ RR(VID_FIR_COEF_HV(1, 2)); -+ RR(VID_FIR_COEF_HV(1, 3)); -+ RR(VID_FIR_COEF_HV(1, 4)); -+ RR(VID_FIR_COEF_HV(1, 5)); -+ RR(VID_FIR_COEF_HV(1, 6)); -+ RR(VID_FIR_COEF_HV(1, 7)); -+ -+ RR(VID_CONV_COEF(1, 0)); -+ RR(VID_CONV_COEF(1, 1)); -+ RR(VID_CONV_COEF(1, 2)); -+ RR(VID_CONV_COEF(1, 3)); -+ RR(VID_CONV_COEF(1, 4)); -+ -+ RR(VID_FIR_COEF_V(1, 0)); -+ RR(VID_FIR_COEF_V(1, 1)); -+ RR(VID_FIR_COEF_V(1, 2)); -+ RR(VID_FIR_COEF_V(1, 3)); -+ RR(VID_FIR_COEF_V(1, 4)); -+ RR(VID_FIR_COEF_V(1, 5)); -+ RR(VID_FIR_COEF_V(1, 6)); -+ RR(VID_FIR_COEF_V(1, 7)); -+ -+ RR(VID_PRELOAD(1)); -+ -+ /* enable last, because LCD & DIGIT enable are here */ -+ RR(CONTROL); -+} -+ -+#undef SR -+#undef RR -+ -+static inline void enable_clocks(int enable) -+{ -+ if (enable) -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ else -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+} -+ -+void dispc_go(enum omap_channel channel) -+{ -+ int bit; -+ unsigned long tmo; -+ -+ enable_clocks(1); -+ -+ if (channel == OMAP_DSS_CHANNEL_LCD) -+ bit = 0; /* LCDENABLE */ -+ else -+ bit = 1; /* DIGITALENABLE */ -+ -+ /* if the channel is not enabled, we don't need GO */ -+ if (REG_GET(DISPC_CONTROL, bit, bit) == 0) -+ goto end; -+ -+ if (channel == OMAP_DSS_CHANNEL_LCD) -+ bit = 5; /* GOLCD */ -+ else -+ bit = 6; /* GODIGIT */ -+ -+ tmo = jiffies + msecs_to_jiffies(200); -+ while (REG_GET(DISPC_CONTROL, bit, bit) == 1) { -+ if (time_after(jiffies, tmo)) { -+ DSSERR("timeout waiting GO flag\n"); -+ goto end; -+ } -+ cpu_relax(); -+ } -+ -+ DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT"); -+ -+ REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit); -+end: -+ enable_clocks(0); -+} -+ -+static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value) -+{ -+ BUG_ON(plane == OMAP_DSS_GFX); -+ -+ dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value); -+} -+ -+static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value) -+{ -+ BUG_ON(plane == OMAP_DSS_GFX); -+ -+ dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value); -+} -+ -+ -+static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup, -+ int vscaleup) -+{ -+ /* Coefficients for horizontal up-sampling */ -+ const u32 coef_hup[8] = { -+ 0x00800000, -+ 0x0D7CF800, -+ 0x1E70F5FF, -+ 0x335FF5FE, -+ 0xF74949F7, -+ 0xF55F33FB, -+ 0xF5701EFE, -+ 0xF87C0DFF, -+ }; -+ -+ /* Coefficients for horizontal down-sampling */ -+ const u32 coef_hdown[8] = { -+ 0x24382400, -+ 0x28371FFE, -+ 0x2C361BFB, -+ 0x303516F9, -+ 0x11343311, -+ 0x1635300C, -+ 0x1B362C08, -+ 0x1F372804, -+ }; -+ -+ /* Coefficients for horizontal and vertical up-sampling */ -+ const u32 coef_hvup[8] = { -+ 0x00800000, -+ 0x037B02FF, -+ 0x0C6F05FE, -+ 0x205907FB, -+ 0x00404000, -+ 0x075920FE, -+ 0x056F0CFF, -+ 0x027B0300, -+ }; -+ -+ /* Coefficients for horizontal and vertical down-sampling */ -+ const u32 coef_hvdown[8] = { -+ 0x24382400, -+ 0x28391F04, -+ 0x2D381B08, -+ 0x3237170C, -+ 0x123737F7, -+ 0x173732F9, -+ 0x1B382DFB, -+ 0x1F3928FE, -+ }; -+ -+ const u32 *h_coef; -+ const u32 *hv_coef; -+ const u32 *hv_coef_mod; -+ int i; -+ -+ if (hscaleup) -+ h_coef = coef_hup; -+ else -+ h_coef = coef_hdown; -+ -+ if (vscaleup) { -+ hv_coef = coef_hvup; -+ -+ if (hscaleup) -+ hv_coef_mod = NULL; -+ else -+ hv_coef_mod = coef_hvdown; -+ } else { -+ hv_coef = coef_hvdown; -+ -+ if (hscaleup) -+ hv_coef_mod = coef_hvup; -+ else -+ hv_coef_mod = NULL; -+ } -+ -+ for (i = 0; i < 8; i++) { -+ u32 h, hv; -+ -+ h = h_coef[i]; -+ -+ hv = hv_coef[i]; -+ -+ if (hv_coef_mod) { -+ hv &= 0xffffff00; -+ hv |= (hv_coef_mod[i] & 0xff); -+ } -+ -+ _dispc_write_firh_reg(plane, i, h); -+ _dispc_write_firhv_reg(plane, i, hv); -+ } -+} -+ -+static void _dispc_setup_color_conv_coef(void) -+{ -+ const struct color_conv_coef { -+ int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb; -+ int full_range; -+ } ctbl_bt601_5 = { -+ 298, 409, 0, 298, -208, -100, 298, 0, 517, 0, -+ }; -+ -+ const struct color_conv_coef *ct; -+ -+#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0)) -+ -+ ct = &ctbl_bt601_5; -+ -+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry)); -+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy, ct->rcb)); -+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr)); -+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by)); -+ dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0, ct->bcb)); -+ -+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry)); -+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy, ct->rcb)); -+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr)); -+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by)); -+ dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0, ct->bcb)); -+ -+#undef CVAL -+ -+ REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11); -+ REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11); -+} -+ -+ -+static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr) -+{ -+ const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0, -+ DISPC_VID_BA0(0), -+ DISPC_VID_BA0(1) }; -+ -+ dispc_write_reg(ba0_reg[plane], paddr); -+} -+ -+static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr) -+{ -+ const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1, -+ DISPC_VID_BA1(0), -+ DISPC_VID_BA1(1) }; -+ -+ dispc_write_reg(ba1_reg[plane], paddr); -+} -+ -+static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y) -+{ -+ const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION, -+ DISPC_VID_POSITION(0), -+ DISPC_VID_POSITION(1) }; -+ -+ u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0); -+ dispc_write_reg(pos_reg[plane], val); -+} -+ -+static void _dispc_set_pic_size(enum omap_plane plane, int width, int height) -+{ -+ const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE, -+ DISPC_VID_PICTURE_SIZE(0), -+ DISPC_VID_PICTURE_SIZE(1) }; -+ u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); -+ dispc_write_reg(siz_reg[plane], val); -+} -+ -+static void _dispc_set_vid_size(enum omap_plane plane, int width, int height) -+{ -+ u32 val; -+ const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0), -+ DISPC_VID_SIZE(1) }; -+ -+ BUG_ON(plane == OMAP_DSS_GFX); -+ -+ val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); -+ dispc_write_reg(vsi_reg[plane-1], val); -+} -+ -+static void _dispc_set_row_inc(enum omap_plane plane, int inc) -+{ -+ const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC, -+ DISPC_VID_ROW_INC(0), -+ DISPC_VID_ROW_INC(1) }; -+ -+ dispc_write_reg(ri_reg[plane], inc); -+} -+ -+static void _dispc_set_color_mode(enum omap_plane plane, -+ enum omap_color_mode color_mode) -+{ -+ u32 m = 0; -+ -+ switch (color_mode) { -+ case OMAP_DSS_COLOR_CLUT1: -+ m = 0x0; break; -+ case OMAP_DSS_COLOR_CLUT2: -+ m = 0x1; break; -+ case OMAP_DSS_COLOR_CLUT4: -+ m = 0x2; break; -+ case OMAP_DSS_COLOR_CLUT8: -+ m = 0x3; break; -+ case OMAP_DSS_COLOR_RGB12U: -+ m = 0x4; break; -+ case OMAP_DSS_COLOR_ARGB16: -+ m = 0x5; break; -+ case OMAP_DSS_COLOR_RGB16: -+ m = 0x6; break; -+ case OMAP_DSS_COLOR_RGB24U: -+ m = 0x8; break; -+ case OMAP_DSS_COLOR_RGB24P: -+ m = 0x9; break; -+ case OMAP_DSS_COLOR_YUV2: -+ m = 0xa; break; -+ case OMAP_DSS_COLOR_UYVY: -+ m = 0xb; break; -+ case OMAP_DSS_COLOR_ARGB32: -+ m = 0xc; break; -+ case OMAP_DSS_COLOR_RGBA32: -+ m = 0xd; break; -+ case OMAP_DSS_COLOR_RGBX32: -+ m = 0xe; break; -+ default: -+ BUG(); break; -+ } -+ -+ REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1); -+} -+ -+static void _dispc_set_channel_out(enum omap_plane plane, -+ enum omap_channel channel) -+{ -+ int shift; -+ u32 val; -+ -+ switch (plane) { -+ case OMAP_DSS_GFX: -+ shift = 8; -+ break; -+ case OMAP_DSS_VIDEO1: -+ case OMAP_DSS_VIDEO2: -+ shift = 16; -+ break; -+ default: -+ BUG(); -+ return; -+ } -+ -+ val = dispc_read_reg(dispc_reg_att[plane]); -+ val = FLD_MOD(val, channel, shift, shift); -+ dispc_write_reg(dispc_reg_att[plane], val); -+} -+ -+void dispc_set_burst_size(enum omap_plane plane, -+ enum omap_burst_size burst_size) -+{ -+ int shift; -+ u32 val; -+ -+ enable_clocks(1); -+ -+ switch (plane) { -+ case OMAP_DSS_GFX: -+ shift = 6; -+ break; -+ case OMAP_DSS_VIDEO1: -+ case OMAP_DSS_VIDEO2: -+ shift = 14; -+ break; -+ default: -+ BUG(); -+ return; -+ } -+ -+ val = dispc_read_reg(dispc_reg_att[plane]); -+ val = FLD_MOD(val, burst_size, shift+1, shift); -+ dispc_write_reg(dispc_reg_att[plane], val); -+ -+ enable_clocks(0); -+} -+ -+static void _dispc_set_vid_color_conv(enum omap_plane plane, int enable) -+{ -+ u32 val; -+ -+ BUG_ON(plane == OMAP_DSS_GFX); -+ -+ val = dispc_read_reg(dispc_reg_att[plane]); -+ val = FLD_MOD(val, enable, 9, 9); -+ dispc_write_reg(dispc_reg_att[plane], val); -+} -+ -+void dispc_set_lcd_size(int width, int height) -+{ -+ u32 val; -+ BUG_ON((width > (1 << 11)) || (height > (1 << 11))); -+ val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); -+ enable_clocks(1); -+ dispc_write_reg(DISPC_SIZE_LCD, val); -+ enable_clocks(0); -+} -+ -+void dispc_set_digit_size(int width, int height) -+{ -+ u32 val; -+ BUG_ON((width > (1 << 11)) || (height > (1 << 11))); -+ val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); -+ enable_clocks(1); -+ dispc_write_reg(DISPC_SIZE_DIG, val); -+ enable_clocks(0); -+} -+ -+u32 dispc_get_plane_fifo_size(enum omap_plane plane) -+{ -+ const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS, -+ DISPC_VID_FIFO_SIZE_STATUS(0), -+ DISPC_VID_FIFO_SIZE_STATUS(1) }; -+ u32 size; -+ -+ enable_clocks(1); -+ -+ if (cpu_is_omap24xx()) -+ size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0); -+ else if (cpu_is_omap34xx()) -+ size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0); -+ else -+ BUG(); -+ -+ enable_clocks(0); -+ -+ return size; -+} -+ -+void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high) -+{ -+ const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD, -+ DISPC_VID_FIFO_THRESHOLD(0), -+ DISPC_VID_FIFO_THRESHOLD(1) }; -+ const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS, -+ DISPC_VID_FIFO_SIZE_STATUS(0), -+ DISPC_VID_FIFO_SIZE_STATUS(1) }; -+ u32 size; -+ -+ enable_clocks(1); -+ -+ if (cpu_is_omap24xx()) -+ size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0); -+ else if (cpu_is_omap34xx()) -+ size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0); -+ else -+ BUG(); -+ -+ BUG_ON(low > size || high > size); -+ -+ DSSDBG("fifo(%d) size %d, low/high old %u/%u, new %u/%u\n", -+ plane, size, -+ REG_GET(ftrs_reg[plane], 11, 0), -+ REG_GET(ftrs_reg[plane], 27, 16), -+ low, high); -+ -+ if (cpu_is_omap24xx()) -+ dispc_write_reg(ftrs_reg[plane], -+ FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0)); -+ else -+ dispc_write_reg(ftrs_reg[plane], -+ FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0)); -+ -+ enable_clocks(0); -+} -+ -+static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc) -+{ -+ u32 val; -+ const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0), -+ DISPC_VID_FIR(1) }; -+ -+ BUG_ON(plane == OMAP_DSS_GFX); -+ -+ val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0); -+ dispc_write_reg(fir_reg[plane-1], val); -+} -+ -+static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu) -+{ -+ u32 val; -+ const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0), -+ DISPC_VID_ACCU0(1) }; -+ -+ BUG_ON(plane == OMAP_DSS_GFX); -+ -+ val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0); -+ dispc_write_reg(ac0_reg[plane-1], val); -+} -+ -+static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu) -+{ -+ u32 val; -+ const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0), -+ DISPC_VID_ACCU1(1) }; -+ -+ BUG_ON(plane == OMAP_DSS_GFX); -+ -+ val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0); -+ dispc_write_reg(ac1_reg[plane-1], val); -+} -+ -+ -+static void _dispc_set_scaling(enum omap_plane plane, -+ int orig_width, int orig_height, -+ int out_width, int out_height, -+ int ilace) -+{ -+ int fir_hinc; -+ int fir_vinc; -+ int hscaleup, vscaleup; -+ int fieldmode = 0; -+ int accu0 = 0; -+ int accu1 = 0; -+ u32 l; -+ -+ BUG_ON(plane == OMAP_DSS_GFX); -+ -+ hscaleup = orig_width <= out_width; -+ vscaleup = orig_height <= out_height; -+ -+ _dispc_set_scale_coef(plane, hscaleup, vscaleup); -+ -+ if (!orig_width || orig_width == out_width) -+ fir_hinc = 0; -+ else -+ fir_hinc = 1024 * orig_width / out_width; -+ -+ if (!orig_height || orig_height == out_height) -+ fir_vinc = 0; -+ else -+ fir_vinc = 1024 * orig_height / out_height; -+ -+ _dispc_set_fir(plane, fir_hinc, fir_vinc); -+ -+ l = dispc_read_reg(dispc_reg_att[plane]); -+ l &= ~(0x0f << 5); -+ -+ l |= fir_hinc ? (1 << 5) : 0; -+ l |= fir_vinc ? (1 << 6) : 0; -+ -+ l |= hscaleup ? 0 : (1 << 7); -+ l |= vscaleup ? 0 : (1 << 8); -+ -+ dispc_write_reg(dispc_reg_att[plane], l); -+ -+ if (ilace) { -+ if (fieldmode) { -+ accu0 = fir_vinc / 2; -+ accu1 = 0; -+ } else { -+ accu0 = 0; -+ accu1 = fir_vinc / 2; -+ if (accu1 >= 1024/2) { -+ accu0 = 1024/2; -+ accu1 -= accu0; -+ } -+ } -+ } -+ -+ _dispc_set_vid_accu0(plane, 0, accu0); -+ _dispc_set_vid_accu1(plane, 0, accu1); -+} -+ -+static int _dispc_setup_plane(enum omap_plane plane, -+ enum omap_channel channel_out, -+ u32 paddr, int screen_width, -+ int pos_x, int pos_y, -+ int width, int height, -+ int out_width, int out_height, -+ enum omap_color_mode color_mode, -+ int ilace) -+{ -+ int fieldmode = 0; -+ int bpp; -+ int cconv; -+ int scaling = 0; -+ -+ if (plane == OMAP_DSS_GFX) { -+ if (width != out_width || height != out_height) -+ return -EINVAL; -+ } else { -+ /* video plane */ -+ if (width != out_width || height != out_height) -+ scaling = 1; -+ -+ if (out_width < width/2 || -+ out_width > width*8) -+ return -EINVAL; -+ -+ if (out_height < height/2 || -+ out_height > height*8) -+ return -EINVAL; -+ } -+ -+ -+ switch (color_mode) { -+ case OMAP_DSS_COLOR_RGB16: -+ bpp = 16; -+ cconv = 0; -+ break; -+ -+ case OMAP_DSS_COLOR_RGB24P: -+ bpp = 24; -+ cconv = 0; -+ break; -+ -+ case OMAP_DSS_COLOR_RGB24U: -+ bpp = 32; -+ cconv = 0; -+ break; -+ -+ case OMAP_DSS_COLOR_YUV2: -+ case OMAP_DSS_COLOR_UYVY: -+ BUG_ON(plane == OMAP_DSS_GFX); -+ bpp = 16; -+ cconv = 1; -+ break; -+ -+ default: -+ BUG(); -+ return 1; -+ } -+ -+ if (ilace) { -+ if (height == out_height || height > out_height) -+ fieldmode = 1; -+ } -+ -+ if (fieldmode) -+ height /= 2; -+ -+ if (ilace) -+ out_height /= 2; -+ -+ if (plane != OMAP_DSS_GFX) -+ _dispc_set_scaling(plane, width, height, -+ out_width, out_height, -+ ilace); -+ -+ /* attributes */ -+ _dispc_set_channel_out(plane, channel_out); -+ _dispc_set_color_mode(plane, color_mode); -+ if (plane != OMAP_DSS_GFX) -+ _dispc_set_vid_color_conv(plane, cconv); -+ -+ /* */ -+ -+ _dispc_set_plane_ba0(plane, paddr); -+ -+ if (fieldmode) -+ _dispc_set_plane_ba1(plane, paddr + screen_width * bpp/8); -+ else -+ _dispc_set_plane_ba1(plane, paddr); -+ -+ -+ _dispc_set_plane_pos(plane, pos_x, pos_y); -+ -+ _dispc_set_pic_size(plane, width, height); -+ -+ if (plane != OMAP_DSS_GFX) -+ _dispc_set_vid_size(plane, out_width, out_height); -+ -+ _dispc_set_row_inc(plane, -+ (screen_width - width) * bpp / 8 + -+ (fieldmode ? screen_width * bpp / 8 : 0) + -+ 1); -+ -+ return 0; -+} -+ -+static void _dispc_enable_plane(enum omap_plane plane, int enable) -+{ -+ REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0); -+} -+ -+ -+void dispc_enable_lcd_out(int enable) -+{ -+ enable_clocks(1); -+ REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0); -+ enable_clocks(0); -+} -+ -+void dispc_enable_digit_out(int enable) -+{ -+ enable_clocks(1); -+ REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1,