From 20face5dc2bfe22d6fb747c36ebfc70cad854fa4 Mon Sep 17 00:00:00 2001 From: Leon Woestenberg Date: Thu, 1 May 2008 12:53:25 +0000 Subject: u-boot-1.1.4: Added additional patches from Atmel AT32STK1000 BSP 2.0.0 CD, mostly LCD/splash support. u-boot-1.1.4/at32stk1000/ap7000-add-spi-device-and-lcdc-base-address.patch | 112 + u-boot-1.1.4/at32stk1000/at32ap-add-define-for-sdram-test.patch | 117 + u-boot-1.1.4/at32stk1000/at32ap-add-framebuffer-address.patch | 11 u-boot-1.1.4/at32stk1000/at32ap-add-spi-initcalls.patch | 16 u-boot-1.1.4/at32stk1000/at32ap-add-system-manager-header-file.patch | 252 ++ u-boot-1.1.4/at32stk1000/atstk1000-add-lcd-and-spi-to-config.patch | 124 + u-boot-1.1.4/at32stk1000/atstk1000-ltv350qv-display-support.patch | 163 + u-boot-1.1.4/at32stk1000/atstk1000-spi-support.patch | 98 u-boot-1.1.4/at32stk1000/avr32-boards-fix-flash-read.patch | 120 + u-boot-1.1.4/at32stk1000/cmd-bmp-add-gzip-compressed-bmp.patch | 90 u-boot-1.1.4/at32stk1000/fix-mmc-data-timeout.patch | 101 u-boot-1.1.4/at32stk1000/lcd-add-24-bpp-support-and-atmel-lcdc-support.patch | 670 ++++++ u-boot-1.1.4/at32stk1000/lcdc-driver-for-avr32.patch | 755 +++++++ u-boot-1.1.4/at32stk1000/libavr32-add-spi-and-lcd-board-support.patch | 61 u-boot-1.1.4/at32stk1000/spi-driver-for-avr32.patch | 1026 ++++++++++ u-boot_1.1.4.bb | 48 --- .../u-boot/u-boot-1.1.4/at32stk1000/.mtn2git_empty | 0 ...7000-add-spi-device-and-lcdc-base-address.patch | 112 +++ .../at32ap-add-define-for-sdram-test.patch | 117 +++ .../at32ap-add-framebuffer-address.patch | 11 + .../at32stk1000/at32ap-add-spi-initcalls.patch | 16 + .../at32ap-add-system-manager-header-file.patch | 252 +++++ .../atstk1000-add-lcd-and-spi-to-config.patch | 124 +++ .../atstk1000-ltv350qv-display-support.patch | 163 ++++ .../at32stk1000/atstk1000-spi-support.patch | 98 ++ .../at32stk1000/avr32-boards-fix-flash-read.patch | 120 +++ .../cmd-bmp-add-gzip-compressed-bmp.patch | 90 ++ .../at32stk1000/fix-mmc-data-timeout.patch | 101 ++ ...add-24-bpp-support-and-atmel-lcdc-support.patch | 670 +++++++++++++ .../at32stk1000/lcdc-driver-for-avr32.patch | 755 ++++++++++++++ .../libavr32-add-spi-and-lcd-board-support.patch | 61 ++ .../at32stk1000/spi-driver-for-avr32.patch | 1026 ++++++++++++++++++++ packages/u-boot/u-boot_1.1.4.bb | 48 +- 17 files changed, 3749 insertions(+), 15 deletions(-) create mode 100644 packages/u-boot/u-boot-1.1.4/at32stk1000/.mtn2git_empty create mode 100644 packages/u-boot/u-boot-1.1.4/at32stk1000/ap7000-add-spi-device-and-lcdc-base-address.patch create mode 100644 packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-define-for-sdram-test.patch create mode 100644 packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-framebuffer-address.patch create mode 100644 packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-spi-initcalls.patch create mode 100644 packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-system-manager-header-file.patch create mode 100644 packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-add-lcd-and-spi-to-config.patch create mode 100644 packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-ltv350qv-display-support.patch create mode 100644 packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-spi-support.patch create mode 100644 packages/u-boot/u-boot-1.1.4/at32stk1000/avr32-boards-fix-flash-read.patch create mode 100644 packages/u-boot/u-boot-1.1.4/at32stk1000/cmd-bmp-add-gzip-compressed-bmp.patch create mode 100644 packages/u-boot/u-boot-1.1.4/at32stk1000/fix-mmc-data-timeout.patch create mode 100644 packages/u-boot/u-boot-1.1.4/at32stk1000/lcd-add-24-bpp-support-and-atmel-lcdc-support.patch create mode 100644 packages/u-boot/u-boot-1.1.4/at32stk1000/lcdc-driver-for-avr32.patch create mode 100644 packages/u-boot/u-boot-1.1.4/at32stk1000/libavr32-add-spi-and-lcd-board-support.patch create mode 100644 packages/u-boot/u-boot-1.1.4/at32stk1000/spi-driver-for-avr32.patch (limited to 'packages') diff --git a/packages/u-boot/u-boot-1.1.4/at32stk1000/.mtn2git_empty b/packages/u-boot/u-boot-1.1.4/at32stk1000/.mtn2git_empty new file mode 100644 index 0000000000..e69de29bb2 diff --git a/packages/u-boot/u-boot-1.1.4/at32stk1000/ap7000-add-spi-device-and-lcdc-base-address.patch b/packages/u-boot/u-boot-1.1.4/at32stk1000/ap7000-add-spi-device-and-lcdc-base-address.patch new file mode 100644 index 0000000000..fa8c8f701f --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/at32stk1000/ap7000-add-spi-device-and-lcdc-base-address.patch @@ -0,0 +1,112 @@ +diff -uprN u-boot-orig/cpu/at32ap7xxx/ap7000/devices.c u-boot/cpu/at32ap7xxx/ap7000/devices.c +--- u-boot-orig/cpu/at32ap7xxx/ap7000/devices.c 2007-01-01 19:26:46.000000000 +0100 ++++ u-boot/cpu/at32ap7xxx/ap7000/devices.c 2006-12-22 14:51:26.000000000 +0100 +@@ -223,6 +223,46 @@ static const struct resource macb1_resou + }, + }; + #endif ++#if defined(CFG_SPI0) ++static const struct resource spi0_resource[] = { ++ { ++ .type = RESOURCE_CLOCK, ++ .u = { ++ .clock = { CLOCK_APBA, 0 }, ++ }, ++ }, { ++ .type = RESOURCE_GPIO, ++ .u = { ++ .gpio = { 6, DEVICE_PIOA, GPIO_FUNC_A, 0 }, ++ }, ++ }, { ++ .type = RESOURCE_GPIO, ++ .u = { ++ .gpio = { 1, DEVICE_PIOA, GPIO_FUNC_B, 20 }, ++ }, ++ }, ++}; ++#endif ++#if defined(CFG_SPI1) ++static const struct resource spi1_resource[] = { ++ { ++ .type = RESOURCE_CLOCK, ++ .u = { ++ .clock = { CLOCK_APBA, 1 }, ++ }, ++ }, { ++ .type = RESOURCE_GPIO, ++ .u = { ++ .gpio = { 6, DEVICE_PIOB, GPIO_FUNC_B, 0 }, ++ }, ++ }, { ++ .type = RESOURCE_GPIO, ++ .u = { ++ .gpio = { 1, DEVICE_PIOA, GPIO_FUNC_A, 27 }, ++ }, ++ }, ++}; ++#endif + #if defined(CFG_LCDC) + static const struct resource lcdc_resource[] = { + { +@@ -230,6 +270,16 @@ static const struct resource lcdc_resour + .u = { + .clock = { CLOCK_AHB, 7 }, + }, ++ }, { ++ .type = RESOURCE_GPIO, ++ .u = { ++ .gpio = { 13, DEVICE_PIOC, GPIO_FUNC_A, 19 }, ++ }, ++ }, { ++ .type = RESOURCE_GPIO, ++ .u = { ++ .gpio = { 18, DEVICE_PIOD, GPIO_FUNC_A, 0 }, ++ }, + }, + }; + #endif +@@ -390,6 +440,20 @@ const struct device chip_device[] = { + .resource = macb0_resource, + }, + #endif ++#if defined(CFG_SPI0) ++ [DEVICE_SPI0] = { ++ .regs = (void *)SPI0_BASE, ++ .nr_resources = ARRAY_SIZE(spi0_resource), ++ .resource = spi0_resource, ++ }, ++#endif ++#if defined(CFG_SPI1) ++ [DEVICE_SPI1] = { ++ .regs = (void *)SPI1_BASE, ++ .nr_resources = ARRAY_SIZE(spi1_resource), ++ .resource = spi1_resource, ++ }, ++#endif + #if defined(CFG_MACB1) + [DEVICE_MACB1] = { + .regs = (void *)MACB1_BASE, +@@ -399,6 +463,7 @@ const struct device chip_device[] = { + #endif + #if defined(CFG_LCDC) + [DEVICE_LCDC] = { ++ .regs = (void *)LCDC_BASE, + .nr_resources = ARRAY_SIZE(lcdc_resource), + .resource = lcdc_resource, + }, +diff -uprN u-boot-orig/include/asm-avr32/arch-ap7000/platform.h u-boot/include/asm-avr32/arch-ap7000/platform.h +--- u-boot-orig/include/asm-avr32/arch-ap7000/platform.h 2007-01-01 19:26:46.000000000 +0100 ++++ u-boot/include/asm-avr32/arch-ap7000/platform.h 2006-12-22 14:20:39.000000000 +0100 +@@ -66,6 +66,12 @@ enum device_id { + #if defined(CFG_MACB1) + DEVICE_MACB1, + #endif ++#if defined(CFG_SPI0) ++ DEVICE_SPI0, ++#endif ++#if defined(CFG_SPI1) ++ DEVICE_SPI1, ++#endif + #if defined(CFG_LCDC) + DEVICE_LCDC, + #endif diff --git a/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-define-for-sdram-test.patch b/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-define-for-sdram-test.patch new file mode 100644 index 0000000000..33c5eb9b7c --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-define-for-sdram-test.patch @@ -0,0 +1,117 @@ +Index: u-boot-1.1.4/cpu/at32ap7xxx/hsdramc.c +=================================================================== +--- u-boot-1.1.4.orig/cpu/at32ap7xxx/hsdramc.c 2007-01-11 15:28:40.000000000 +0100 ++++ u-boot-1.1.4/cpu/at32ap7xxx/hsdramc.c 2007-01-11 15:29:36.000000000 +0100 +@@ -133,6 +133,7 @@ + printf("SDRAM: %u MB at address 0x%08lx\n", + sdram_size >> 20, info->phys_addr); + ++#ifdef CONFIG_SDRAM_TEST + printf("Testing SDRAM..."); + for (i = 0; i < sdram_size / 4; i++) + sdram[i] = i; +@@ -148,6 +149,7 @@ + } + + puts("OK\n"); ++#endif + + return sdram_size; + } +Index: u-boot-1.1.4/include/configs/atngw.h +=================================================================== +--- u-boot-1.1.4.orig/include/configs/atngw.h 2007-01-11 15:28:40.000000000 +0100 ++++ u-boot-1.1.4/include/configs/atngw.h 2007-01-30 16:41:23.000000000 +0100 +@@ -31,6 +31,10 @@ + + #define CONFIG_NGW_EXT_FLASH 1 + ++/* Handy macros for making strings */ ++#define xstringify(x) #x ++#define stringify(x) xstringify(x) ++ + /* + * Timer clock frequency. We're using the CPU-internal COUNT register + * for this, so this is equivalent to the CPU core clock frequency +@@ -80,9 +84,9 @@ + + #define CONFIG_BAUDRATE 115200 + #define CONFIG_BOOTARGS \ +- "console=ttyS0 root=/dev/mmcblk0p1" ++ "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2" + #define CONFIG_BOOTCOMMAND \ +- "mmcinit; ext2load mmc 0:1 0x90400000 /uImage; bootm 0x90400000" ++ "fsload 0x90250000 /uImage; bootm 0x90250000" + + #define CONFIG_BOOTDELAY 2 + #define CONFIG_AUTOBOOT 1 +@@ -105,8 +109,8 @@ + * generated and assigned to the environment variables "ethaddr" and + * "eth1addr". + */ +-#define CONFIG_ETHADDR "6a:87:71:14:cd:cb" +-#define CONFIG_ETH1ADDR "ca:f8:15:e6:3e:e6" ++#define CONFIG_ETHADDR "42:b2:13:36:50:94" ++#define CONFIG_ETH1ADDR "4e:29:49:7e:5c:b9" + #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 + #define CONFIG_NET_MULTI 1 + +@@ -183,6 +187,7 @@ + + #define CFG_SDRAM_BASE 0x10000000 + #define CFG_SDRAM_16BIT 1 ++#define CONFIG_SDRAM_TEST 1 + + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_SIZE 65536 +@@ -202,7 +207,7 @@ + #define CFG_DMA_ALLOC_END (CFG_MALLOC_START) + #define CFG_DMA_ALLOC_START (CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN) + /* Allow 2MB for the kernel run-time image */ +-#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000) ++#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00250000) + #define CFG_BOOTPARAMS_LEN (16 * 1024) + + /* Other configuration settings that shouldn't have to change all that often */ +Index: u-boot-1.1.4/include/configs/atstk1002.h +=================================================================== +--- u-boot-1.1.4.orig/include/configs/atstk1002.h 2007-01-11 15:29:36.000000000 +0100 ++++ u-boot-1.1.4/include/configs/atstk1002.h 2007-01-30 16:41:25.000000000 +0100 +@@ -98,7 +98,7 @@ + #define CFG_CONSOLE_UART_DEV DEVICE_USART1 + + /* Define to force consol on serial */ +-/* #define CFG_CONSOLE_ALLWAYS_UART 1 */ ++#define CFG_CONSOLE_ALLWAYS_UART 1 + #ifdef CFG_CONSOLE_ALLWAYS_UART + #define CFG_CONSOLE_IS_IN_ENV 1 + #define CFG_CONSOLE_OVERWRITE_ROUTINE 1 +@@ -123,7 +123,7 @@ + #endif + + #define CONFIG_BOOTCOMMAND \ +- "mmcinit; ext2load mmc 0:1 /uImage; bootm" ++ "mmcinit; ext2load mmc 0:1 0x90250000 /uImage; bootm 0x90250000" + #define CONFIG_BOOTDELAY 2 + #define CONFIG_AUTOBOOT 1 + +@@ -145,8 +145,8 @@ + * generated and assigned to the environment variables "ethaddr" and + * "eth1addr". + */ +-#define CONFIG_ETHADDR "6a:87:71:14:cd:cb" +-#define CONFIG_ETH1ADDR "ca:f8:15:e6:3e:e6" ++#define CONFIG_ETHADDR "42:b2:13:36:50:94" ++#define CONFIG_ETH1ADDR "4e:29:49:7e:5c:b9" + #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 + #define CONFIG_NET_MULTI 1 + +@@ -233,6 +233,8 @@ + #define CFG_INTRAM_SIZE 0x8000 + + #define CFG_SDRAM_BASE 0x10000000 ++/* Will do SDRAM test if defined */ ++#define CONFIG_SDRAM_TEST 1 + + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_SIZE 65536 diff --git a/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-framebuffer-address.patch b/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-framebuffer-address.patch new file mode 100644 index 0000000000..cac9be5d55 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-framebuffer-address.patch @@ -0,0 +1,11 @@ +diff -uprN u-boot-orig/include/asm-avr32/global_data.h u-boot/include/asm-avr32/global_data.h +--- u-boot-orig/include/asm-avr32/global_data.h 2007-01-01 19:26:46.000000000 +0100 ++++ u-boot/include/asm-avr32/global_data.h 2006-12-19 11:08:14.000000000 +0100 +@@ -44,6 +44,7 @@ typedef struct global_data { + unsigned long env_addr; /* Address of env struct */ + unsigned long env_valid; /* Checksum of env valid? */ + unsigned long cpu_hz; /* TODO: remove */ ++ unsigned long fb_base; /* Address to framebuffer */ + void **jt; + } gd_t; + diff --git a/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-spi-initcalls.patch b/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-spi-initcalls.patch new file mode 100644 index 0000000000..397d6b00aa --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-spi-initcalls.patch @@ -0,0 +1,16 @@ +diff -uprN u-boot-orig/include/asm-avr32/initcalls.h u-boot/include/asm-avr32/initcalls.h +--- u-boot-orig/include/asm-avr32/initcalls.h 2007-01-01 19:26:46.000000000 +0100 ++++ u-boot/include/asm-avr32/initcalls.h 2007-01-05 13:29:16.000000000 +0100 +@@ -30,6 +30,12 @@ extern void board_init_memories(void); + extern void board_init_pio(void); + extern void board_init_info(void); + ++#if CONFIG_SPI ++extern void board_init_spi(void); ++#else ++static inline void board_init_spi(void) { } ++#endif ++ + #if (CONFIG_COMMANDS & CFG_CMD_NET) + extern void net_init(void); + #else diff --git a/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-system-manager-header-file.patch b/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-system-manager-header-file.patch new file mode 100644 index 0000000000..221333c4bc --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-system-manager-header-file.patch @@ -0,0 +1,252 @@ +diff -uprN u-boot-orig/include/asm-avr32/arch-ap7000/sm.h u-boot/include/asm-avr32/arch-ap7000/sm.h +--- u-boot-orig/include/asm-avr32/arch-ap7000/sm.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/include/asm-avr32/arch-ap7000/sm.h 2006-12-21 16:28:04.000000000 +0100 +@@ -0,0 +1,248 @@ ++/* ++ * Register definitions for SM ++ * ++ * System Manager ++ */ ++#ifndef __ASM_AVR32_SM_H__ ++#define __ASM_AVR32_SM_H__ ++ ++/* SM register offsets */ ++#define SM_PM_MCCTRL 0x0000 ++#define SM_PM_CKSEL 0x0004 ++#define SM_PM_CPU_MASK 0x0008 ++#define SM_PM_AHB_MASK 0x000c ++#define SM_PM_APBA_MASK 0x0010 ++#define SM_PM_APBB_MASK 0x0014 ++#define SM_PM_PLL0 0x0020 ++#define SM_PM_PLL1 0x0024 ++#define SM_PM_VCTRL 0x0030 ++#define SM_PM_VMREF 0x0034 ++#define SM_PM_VMV 0x0038 ++#define SM_PM_IER 0x0040 ++#define SM_PM_IDR 0x0044 ++#define SM_PM_IMR 0x0048 ++#define SM_PM_ISR 0x004c ++#define SM_PM_ICR 0x0050 ++#define SM_PM_GCCTRL 0x0060 ++#define SM_PM_GCCTRL0 0x0060 ++#define SM_PM_GCCTRL1 0x0064 ++#define SM_PM_GCCTRL2 0x0068 ++#define SM_PM_GCCTRL3 0x006c ++#define SM_PM_GCCTRL4 0x0070 ++#define SM_PM_GCCTRL5 0x0074 ++#define SM_PM_GCCTRL6 0x0078 ++#define SM_PM_GCCTRL7 0x007c ++#define SM_RTC_CTRL 0x0080 ++#define SM_RTC_VAL 0x0084 ++#define SM_RTC_TOP 0x0088 ++#define SM_RTC_IER 0x0090 ++#define SM_RTC_IDR 0x0094 ++#define SM_RTC_IMR 0x0098 ++#define SM_RTC_ISR 0x009c ++#define SM_RTC_ICR 0x00a0 ++#define SM_WDT_CTRL 0x00b0 ++#define SM_WDT_CLR 0x00b4 ++#define SM_WDT_EXT 0x00b8 ++#define SM_RC_RCAUSE 0x00c0 ++#define SM_EIM_IER 0x0100 ++#define SM_EIM_IDR 0x0104 ++#define SM_EIM_IMR 0x0108 ++#define SM_EIM_ISR 0x010c ++#define SM_EIM_ICR 0x0110 ++#define SM_EIM_MODE 0x0114 ++#define SM_EIM_EDGE 0x0118 ++#define SM_EIM_LEVEL 0x011c ++#define SM_EIM_TEST 0x0120 ++#define SM_EIM_NMIC 0x0124 ++ ++/* Bitfields in PM_MCCTRL */ ++ ++/* Bitfields in PM_CKSEL */ ++#define SM_CPUSEL_OFFSET 0 ++#define SM_CPUSEL_SIZE 3 ++#define SM_CPUDIV_OFFSET 7 ++#define SM_CPUDIV_SIZE 1 ++#define SM_AHBSEL_OFFSET 8 ++#define SM_AHBSEL_SIZE 3 ++#define SM_AHBDIV_OFFSET 15 ++#define SM_AHBDIV_SIZE 1 ++#define SM_APBASEL_OFFSET 16 ++#define SM_APBASEL_SIZE 3 ++#define SM_APBADIV_OFFSET 23 ++#define SM_APBADIV_SIZE 1 ++#define SM_APBBSEL_OFFSET 24 ++#define SM_APBBSEL_SIZE 3 ++#define SM_APBBDIV_OFFSET 31 ++#define SM_APBBDIV_SIZE 1 ++ ++/* Bitfields in PM_CPU_MASK */ ++ ++/* Bitfields in PM_AHB_MASK */ ++ ++/* Bitfields in PM_APBA_MASK */ ++ ++/* Bitfields in PM_APBB_MASK */ ++ ++/* Bitfields in PM_PLL0 */ ++#define SM_PLLEN_OFFSET 0 ++#define SM_PLLEN_SIZE 1 ++#define SM_PLLOSC_OFFSET 1 ++#define SM_PLLOSC_SIZE 1 ++#define SM_PLLOPT_OFFSET 2 ++#define SM_PLLOPT_SIZE 3 ++#define SM_PLLDIV_OFFSET 8 ++#define SM_PLLDIV_SIZE 8 ++#define SM_PLLMUL_OFFSET 16 ++#define SM_PLLMUL_SIZE 8 ++#define SM_PLLCOUNT_OFFSET 24 ++#define SM_PLLCOUNT_SIZE 6 ++#define SM_PLLTEST_OFFSET 31 ++#define SM_PLLTEST_SIZE 1 ++ ++/* Bitfields in PM_PLL1 */ ++ ++/* Bitfields in PM_VCTRL */ ++#define SM_VAUTO_OFFSET 0 ++#define SM_VAUTO_SIZE 1 ++#define SM_PM_VCTRL_VAL_OFFSET 8 ++#define SM_PM_VCTRL_VAL_SIZE 7 ++ ++/* Bitfields in PM_VMREF */ ++#define SM_REFSEL_OFFSET 0 ++#define SM_REFSEL_SIZE 4 ++ ++/* Bitfields in PM_VMV */ ++#define SM_PM_VMV_VAL_OFFSET 0 ++#define SM_PM_VMV_VAL_SIZE 8 ++ ++/* Bitfields in PM_IER */ ++ ++/* Bitfields in PM_IDR */ ++ ++/* Bitfields in PM_IMR */ ++ ++/* Bitfields in PM_ISR */ ++ ++/* Bitfields in PM_ICR */ ++#define SM_LOCK0_OFFSET 0 ++#define SM_LOCK0_SIZE 1 ++#define SM_LOCK1_OFFSET 1 ++#define SM_LOCK1_SIZE 1 ++#define SM_WAKE_OFFSET 2 ++#define SM_WAKE_SIZE 1 ++#define SM_VOK_OFFSET 3 ++#define SM_VOK_SIZE 1 ++#define SM_VMRDY_OFFSET 4 ++#define SM_VMRDY_SIZE 1 ++#define SM_CKRDY_OFFSET 5 ++#define SM_CKRDY_SIZE 1 ++ ++/* Bitfields in PM_GCCTRL */ ++#define SM_OSCSEL_OFFSET 0 ++#define SM_OSCSEL_SIZE 1 ++#define SM_PLLSEL_OFFSET 1 ++#define SM_PLLSEL_SIZE 1 ++#define SM_CEN_OFFSET 2 ++#define SM_CEN_SIZE 1 ++#define SM_CPC_OFFSET 3 ++#define SM_CPC_SIZE 1 ++#define SM_DIVEN_OFFSET 4 ++#define SM_DIVEN_SIZE 1 ++#define SM_DIV_OFFSET 8 ++#define SM_DIV_SIZE 8 ++ ++/* Bitfields in RTC_CTRL */ ++#define SM_PCLR_OFFSET 1 ++#define SM_PCLR_SIZE 1 ++#define SM_TOPEN_OFFSET 2 ++#define SM_TOPEN_SIZE 1 ++#define SM_CLKEN_OFFSET 3 ++#define SM_CLKEN_SIZE 1 ++#define SM_PSEL_OFFSET 8 ++#define SM_PSEL_SIZE 16 ++ ++/* Bitfields in RTC_VAL */ ++#define SM_RTC_VAL_VAL_OFFSET 0 ++#define SM_RTC_VAL_VAL_SIZE 31 ++ ++/* Bitfields in RTC_TOP */ ++#define SM_RTC_TOP_VAL_OFFSET 0 ++#define SM_RTC_TOP_VAL_SIZE 32 ++ ++/* Bitfields in RTC_IER */ ++ ++/* Bitfields in RTC_IDR */ ++ ++/* Bitfields in RTC_IMR */ ++ ++/* Bitfields in RTC_ISR */ ++ ++/* Bitfields in RTC_ICR */ ++#define SM_TOPI_OFFSET 0 ++#define SM_TOPI_SIZE 1 ++ ++/* Bitfields in WDT_CTRL */ ++#define SM_KEY_OFFSET 24 ++#define SM_KEY_SIZE 8 ++ ++/* Bitfields in WDT_CLR */ ++ ++/* Bitfields in WDT_EXT */ ++ ++/* Bitfields in RC_RCAUSE */ ++#define SM_POR_OFFSET 0 ++#define SM_POR_SIZE 1 ++#define SM_BOD_OFFSET 1 ++#define SM_BOD_SIZE 1 ++#define SM_EXT_OFFSET 2 ++#define SM_EXT_SIZE 1 ++#define SM_WDT_OFFSET 3 ++#define SM_WDT_SIZE 1 ++#define SM_NTAE_OFFSET 4 ++#define SM_NTAE_SIZE 1 ++#define SM_SERP_OFFSET 5 ++#define SM_SERP_SIZE 1 ++ ++/* Bitfields in EIM_IER */ ++ ++/* Bitfields in EIM_IDR */ ++ ++/* Bitfields in EIM_IMR */ ++ ++/* Bitfields in EIM_ISR */ ++ ++/* Bitfields in EIM_ICR */ ++ ++/* Bitfields in EIM_MODE */ ++ ++/* Bitfields in EIM_EDGE */ ++#define SM_INT0_OFFSET 0 ++#define SM_INT0_SIZE 1 ++#define SM_INT1_OFFSET 1 ++#define SM_INT1_SIZE 1 ++#define SM_INT2_OFFSET 2 ++#define SM_INT2_SIZE 1 ++#define SM_INT3_OFFSET 3 ++#define SM_INT3_SIZE 1 ++ ++/* Bitfields in EIM_LEVEL */ ++ ++/* Bitfields in EIM_TEST */ ++#define SM_TESTEN_OFFSET 31 ++#define SM_TESTEN_SIZE 1 ++ ++/* Bitfields in EIM_NMIC */ ++#define SM_EN_OFFSET 0 ++#define SM_EN_SIZE 1 ++ ++/* Bit manipulation macros */ ++#define SM_BIT(name) (1 << SM_##name##_OFFSET) ++#define SM_BF(name,value) (((value) & ((1 << SM_##name##_SIZE) - 1)) << SM_##name##_OFFSET) ++#define SM_BFEXT(name,value) (((value) >> SM_##name##_OFFSET) & ((1 << SM_##name##_SIZE) - 1)) ++#define SM_BFINS(name,value,old) (((old) & ~(((1 << SM_##name##_SIZE) - 1) << SM_##name##_OFFSET)) | SM_BF(name,value)) ++ ++/* Register access macros */ ++#define sm_readl(port,reg) readl((port)->regs + SM_##reg) ++#define sm_writel(port,reg,value) writel((value), (port)->regs + SM_##reg) ++ ++#endif /* __ASM_AVR32_SM_H__ */ diff --git a/packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-add-lcd-and-spi-to-config.patch b/packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-add-lcd-and-spi-to-config.patch new file mode 100644 index 0000000000..4deb284564 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-add-lcd-and-spi-to-config.patch @@ -0,0 +1,124 @@ +Index: u-boot-orig/include/configs/atstk1002.h +=================================================================== +--- u-boot-orig.orig/include/configs/atstk1002.h 2007-01-05 15:58:53.000000000 +0100 ++++ u-boot-orig/include/configs/atstk1002.h 2007-01-05 16:04:50.000000000 +0100 +@@ -32,6 +32,10 @@ + + #define CONFIG_ATSTK1000_EXT_FLASH 1 + ++/* Handy macros for making strings */ ++#define xstringify(x) #x ++#define stringify(x) xstringify(x) ++ + /* + * Timer clock frequency. We're using the CPU-internal COUNT register + * for this, so this is equivalent to the CPU core clock frequency +@@ -68,10 +72,39 @@ + #define CFG_USART1 1 + #define CFG_MMCI 1 + #define CFG_MACB0 1 +-#define CFG_MACB1 1 ++/* #define CFG_MACB1 1 */ ++ ++/* Enable SPI support */ ++#define CONFIG_SPI 1 ++#define CONFIG_ATMEL_SPI 1 ++#define CFG_SPI0 1 ++ ++/* Enable LCD support */ ++#define CFG_DMAC 1 ++#define CFG_LCDC 1 ++#define CONFIG_LCD 1 ++#define CONFIG_ATMEL_LCDC 1 ++#define CONFIG_DISPLAY_LTV350QV 1 ++ ++/* Setup LCD */ ++#define LCD_BPP LCD_COLOR24 ++/* CFG_SDRAM_BASE + 0x00500000 */ ++#define CFG_LCD_BASE 0x10500000 ++#define CFG_WHITE_ON_BLACK 1 ++#define CONFIG_VIDEO_BMP_GZIP 1 ++#define CFG_VIDEO_LOGO_MAX_SIZE 262144 /* > 320 * 240 * 3 */ ++/* #define CONFIG_SPLASH_SCREEN 1 */ + + #define CFG_CONSOLE_UART_DEV DEVICE_USART1 + ++/* Define to force consol on serial */ ++/* #define CFG_CONSOLE_ALLWAYS_UART 1 */ ++#ifdef CFG_CONSOLE_ALLWAYS_UART ++#define CFG_CONSOLE_IS_IN_ENV 1 ++#define CFG_CONSOLE_OVERWRITE_ROUTINE 1 ++#define CFG_CONSOLE_ENV_OVERWRITE 1 ++#endif ++ + /* User serviceable stuff */ + #define CONFIG_CMDLINE_TAG 1 + #define CONFIG_SETUP_MEMORY_TAGS 1 +@@ -80,11 +113,17 @@ + #define CONFIG_STACKSIZE (2048) + + #define CONFIG_BAUDRATE 115200 ++ ++#ifdef CFG_LCD_BASE + #define CONFIG_BOOTARGS \ +- "console=ttyUS0 root=/dev/mmcblk0p1 fbmem=600k" +-#define CONFIG_BOOTCOMMAND \ +- "mmcinit; ext2load mmc 0:1 0x90400000 /uImage; bootm 0x90400000" ++ "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k@" stringify(CFG_LCD_BASE) ++#else ++#define CONFIG_BOOTARGS \ ++ "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k" ++#endif + ++#define CONFIG_BOOTCOMMAND \ ++ "mmcinit; ext2load mmc 0:1 /uImage; bootm" + #define CONFIG_BOOTDELAY 2 + #define CONFIG_AUTOBOOT 1 + +@@ -144,7 +183,7 @@ + /* | CFG_CMD_DIAG */ \ + /* | CFG_CMD_HWFLOW */ \ + /* | CFG_CMD_SAVES */ \ +- /* | CFG_CMD_SPI */ \ ++ | CFG_CMD_SPI \ + /* | CFG_CMD_PING */ \ + | CFG_CMD_MMC \ + /* | CFG_CMD_FAT */ \ +@@ -152,6 +191,7 @@ + /* | CFG_CMD_ITEST */ \ + | CFG_CMD_EXT2 \ + | CFG_CMD_JFFS2 \ ++ | CFG_CMD_BMP \ + ) + + #include +@@ -201,7 +241,7 @@ + #define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) + + #ifdef CONFIG_ATSTK1000 +-# define CFG_MALLOC_LEN (256*1024) ++# define CFG_MALLOC_LEN (512*1024) + # define CFG_MALLOC_END \ + ({ \ + DECLARE_GLOBAL_DATA_PTR; \ +@@ -213,7 +253,7 @@ + # define CFG_DMA_ALLOC_END (CFG_MALLOC_START) + # define CFG_DMA_ALLOC_START (CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN) + /* Allow 2MB for the kernel run-time image */ +-# define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000) ++# define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00250000) + # define CFG_BOOTPARAMS_LEN (16 * 1024) + #else + # define CFG_MALLOC_LEN (8*1024) +Index: u-boot-orig/board/atstk1000/atstk1000.c +=================================================================== +--- u-boot-orig.orig/board/atstk1000/atstk1000.c 2007-01-05 16:02:33.000000000 +0100 ++++ u-boot-orig/board/atstk1000/atstk1000.c 2007-01-05 16:04:00.000000000 +0100 +@@ -52,3 +52,7 @@ + gd->bd->bi_phy_id[0] = 0x10; + gd->bd->bi_phy_id[1] = 0x11; + } ++ ++#ifdef CFG_CONSOLE_ALLWAYS_UART ++int overwrite_console(void) { return 1; } ++#endif diff --git a/packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-ltv350qv-display-support.patch b/packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-ltv350qv-display-support.patch new file mode 100644 index 0000000000..57c0fae127 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-ltv350qv-display-support.patch @@ -0,0 +1,163 @@ +diff -uprN u-boot-orig/board/atstk1000/ltv350qv.c u-boot/board/atstk1000/ltv350qv.c +--- u-boot-orig/board/atstk1000/ltv350qv.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/board/atstk1000/ltv350qv.c 2007-01-02 15:17:32.000000000 +0100 +@@ -0,0 +1,147 @@ ++/* ++ * Copyright (C) 2005-2006 Atmel Corporation ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++#include ++ ++#ifdef CONFIG_LCD ++#ifndef CONFIG_SPI ++#error No SPI controller for LCD setup, enable CFG_SPI ++#endif ++ ++#include ++ ++#ifdef CONFIG_ATMEL_SPI ++#include ++#endif ++ ++static int ltv350qv_write_reg(u8 reg, u16 val) ++{ ++ int ret; ++ u8 buffer[3]; ++ ++ buffer[0] = 0x74; ++ buffer[1] = 0x00; ++ buffer[2] = reg & 0x7f; ++ ++ ret = spi_write(&buffer[0], 1, &buffer[1], 2); ++ if (ret != 3) { ++ printf("spi_write returned %d\n", ret); ++ return -1; ++ } ++ ++ buffer[0] = 0x76; ++ buffer[1] = val >> 8; ++ buffer[2] = val; ++ ++ ret = spi_write(&buffer[0], 1, &buffer[1], 2); ++ if (ret != 3) { ++ printf("spi_write returned %d\n", ret); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++#define write_reg(reg, val) \ ++ do { \ ++ ret = ltv350qv_write_reg(reg, val); \ ++ if (ret) \ ++ goto out; \ ++ } while (0) ++ ++void ltv350qv_power_on(void) ++{ ++ int ret; ++ ++#ifdef CONFIG_ATMEL_SPI ++ spi_select_chip(1); ++#endif ++ ++ debug ("ltv350qv: do power on sequence\n"); ++ ++ /* write startup procedure */ ++ write_reg(9, 0x0000); ++ udelay(15000); ++ write_reg(9, 0x4000); ++ write_reg(10, 0x2000); ++ write_reg(9, 0x4055); ++ udelay(55000); ++ write_reg(1, 0x409d); ++ write_reg(2, 0x0204); ++ write_reg(3, 0x0100); ++ write_reg(4, 0x3000); ++ write_reg(5, 0x4003); ++ write_reg(6, 0x000a); ++ write_reg(7, 0x0021); ++ write_reg(8, 0x0c00); ++ write_reg(10, 0x0103); ++ write_reg(11, 0x0301); ++ write_reg(12, 0x1f0f); ++ write_reg(13, 0x1f0f); ++ write_reg(14, 0x0707); ++ write_reg(15, 0x0307); ++ write_reg(16, 0x0707); ++ write_reg(17, 0x0000); ++ write_reg(18, 0x0004); ++ write_reg(19, 0x0000); ++ ++ udelay(20000); ++ write_reg(9, 0x4a55); ++ write_reg(5, 0x5003); ++ ++ debug ("ltv350qv: power on sequence done\n"); ++out: ++ return; ++} ++ ++void ltv350qv_power_off(void) ++{ ++ int ret; ++ ++#ifdef CONFIG_ATMEL_SPI ++ spi_select_chip(1); ++#endif ++ ++ debug ("ltv350qv: do power off sequence\n"); ++ /* GON -> 0, POC -> 0 */ ++ write_reg(9, 0x4055); ++ /* DSC -> 0 */ ++ write_reg(5, 0x4003); ++ /* VCOMG -> 0 */ ++ write_reg(10, 0x2103); ++ ++ udelay(1000000); ++ ++ /* AP[2:0] -> 000 */ ++ write_reg(9, 0x4050); ++ ++ debug ("ltv350qv: power off sequence done\n"); ++out: ++ return; ++} ++ ++void ltv350qv_init(void) ++{ ++ debug ("ltv350qv: initializing LTV350QV panel\n"); ++ ltv350qv_power_on(); ++} ++ ++#endif +diff -uprN u-boot-orig/board/atstk1000/Makefile u-boot/board/atstk1000/Makefile +--- u-boot-orig/board/atstk1000/Makefile 2007-01-01 19:26:46.000000000 +0100 ++++ u-boot/board/atstk1000/Makefile 2007-01-01 16:23:12.000000000 +0100 +@@ -30,7 +30,7 @@ endif + + LIB := lib$(BOARD).a + +-SRC := $(BOARD).c $(DAUGHTERBOARD).c eth.c flash.c ++SRC := $(BOARD).c $(DAUGHTERBOARD).c eth.c flash.c ltv350qv.c + SRC += spi.c + OBJS := $(addsuffix .o,$(basename $(SRC))) + diff --git a/packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-spi-support.patch b/packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-spi-support.patch new file mode 100644 index 0000000000..b9cdba16ff --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-spi-support.patch @@ -0,0 +1,98 @@ +diff -uprN u-boot-orig/board/atstk1000/spi.c u-boot/board/atstk1000/spi.c +--- u-boot-orig/board/atstk1000/spi.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot/board/atstk1000/spi.c 2007-01-03 08:46:36.000000000 +0100 +@@ -0,0 +1,83 @@ ++/* ++ * Copyright (C) 2006 Atmel Corporation ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++#include ++ ++#include ++#include ++#include ++ ++extern void ltv350qv_init(void); ++ ++static struct spi_options_t cs0 = { ++ .reg = 0, ++ .baudrate = 200000, ++ .bits = 8, ++ .spck_delay = 0, ++ .trans_delay = 0, ++ .stay_act = 1, ++ .spi_mode = 3, ++}; ++static struct spi_options_t cs1 = { ++ .reg = 1, ++ .baudrate = 1500000, ++ .bits = 8, ++ .spck_delay = 0, ++ .trans_delay = 0, ++ .stay_act = 1, ++ .spi_mode = 3, ++}; ++ ++void spi_chipsel_dac(int cs) ++{ ++ if (cs) spi_select_chip(0); ++ else spi_unselect_chip(0); ++} ++ ++void spi_chipsel_lcd(int cs) ++{ ++ if (cs) spi_select_chip(1); ++ else spi_unselect_chip(1); ++} ++ ++spi_chipsel_type spi_chipsel[] = { ++ spi_chipsel_dac, ++ spi_chipsel_lcd, ++}; ++int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); ++ ++void board_init_spi(void) ++{ ++ int ret; ++ ++ spi_init(); ++ ++ ret = spi_setup_chip_reg(&cs0, 45000000); /* TODO: get APBA speed */ ++ if (ret) ++ return; ++ ret = spi_setup_chip_reg(&cs1, 45000000); /* TODO: get APBA speed */ ++ if (ret) ++ return; ++ ++ spi_enable(); ++ ++ ltv350qv_init(); ++} +diff -uprN u-boot-orig/board/atstk1000/Makefile u-boot/board/atstk1000/Makefile +--- u-boot-orig/board/atstk1000/Makefile 2007-01-01 19:26:46.000000000 +0100 ++++ u-boot/board/atstk1000/Makefile 2007-01-01 16:23:12.000000000 +0100 +@@ -31,6 +31,7 @@ endif + LIB := lib$(BOARD).a + + SRC := $(BOARD).c $(DAUGHTERBOARD).c eth.c flash.c ++SRC += spi.c + OBJS := $(addsuffix .o,$(basename $(SRC))) + + .PHONY: all diff --git a/packages/u-boot/u-boot-1.1.4/at32stk1000/avr32-boards-fix-flash-read.patch b/packages/u-boot/u-boot-1.1.4/at32stk1000/avr32-boards-fix-flash-read.patch new file mode 100644 index 0000000000..a1e9fe89e5 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/at32stk1000/avr32-boards-fix-flash-read.patch @@ -0,0 +1,120 @@ +Index: u-boot-orig/board/atmel/ngw/flash.c +=================================================================== +--- u-boot-orig.orig/board/atmel/ngw/flash.c 2007-01-03 11:31:44.000000000 +0100 ++++ u-boot-orig/board/atmel/ngw/flash.c 2007-01-03 11:33:13.000000000 +0100 +@@ -161,7 +161,7 @@ + { + unsigned long flags; + uint16_t *base, *p, *s, *end; +- uint16_t word, status; ++ uint16_t word, status,status1; + int ret = ERR_OK; + + if (addr < info->start[0] +@@ -196,20 +196,36 @@ + sync_write_buffer(); + + /* Wait for completion */ +- do { ++ status1 = readw(p); ++ do { + /* TODO: Timeout */ +- status = readw(p); +- } while ((status != word) && !(status & 0x28)); +- ++ status = status1; ++ status1=readw(p); ++ } while ( ((status ^ status1) & 0x40) && // toggle bit has toggled ++ !(status1 & 0x28) // status is "working" ++ ); ++ ++ // We'll need to check once again for toggle bit because the toggle bit ++ // may stop toggling as I/O5 changes to "1" (ref at49bv642.pdf p9) ++ status1=readw(p); ++ status=readw(p); ++ if ((status ^ status1) & 0x40) ++ { ++ printf("Flash write error at address 0x%p: 0x%02x != 0x%02x\n", ++ p, status,word); ++ ret = ERR_PROG_ERROR; ++ writew(0xf0, base); ++ readw(base); ++ break; ++ } ++ // we can now verify status==word if we want to. ++ ++ // is this Product ID Exit command really required?? ++ // --If configuration is 00 (the default) the device is allready in read mode, ++ // and the instruction is not required! + writew(0xf0, base); + readw(base); + +- if (status != word) { +- printf("Flash write error at address 0x%p: 0x%02x\n", +- p, status); +- ret = ERR_PROG_ERROR; +- break; +- } + } + + local_irq_restore(flags); +Index: u-boot-orig/board/atstk1000/flash.c +=================================================================== +--- u-boot-orig.orig/board/atstk1000/flash.c 2007-01-03 11:31:44.000000000 +0100 ++++ u-boot-orig/board/atstk1000/flash.c 2007-01-03 11:33:13.000000000 +0100 +@@ -160,7 +160,7 @@ + { + unsigned long flags; + uint16_t *base, *p, *s, *end; +- uint16_t word, status; ++ uint16_t word, status,status1; + int ret = ERR_OK; + + if (addr < info->start[0] +@@ -195,20 +195,36 @@ + sync_write_buffer(); + + /* Wait for completion */ +- do { ++ status1 = readw(p); ++ do { + /* TODO: Timeout */ +- status = readw(p); +- } while ((status != word) && !(status & 0x28)); +- ++ status = status1; ++ status1=readw(p); ++ } while ( ((status ^ status1) & 0x40) && // toggle bit has toggled ++ !(status1 & 0x28) // status is "working" ++ ); ++ ++ // We'll need to check once again for toggle bit because the toggle bit ++ // may stop toggling as I/O5 changes to "1" (ref at49bv642.pdf p9) ++ status1=readw(p); ++ status=readw(p); ++ if ((status ^ status1) & 0x40) ++ { ++ printf("Flash write error at address 0x%p: 0x%02x != 0x%02x\n", ++ p, status,word); ++ ret = ERR_PROG_ERROR; ++ writew(0xf0, base); ++ readw(base); ++ break; ++ } ++ // we can now verify status==word if we want to. ++ ++ // is this Product ID Exit command really required?? ++ // --If configuration is 00 (the default) the device is allready in read mode, ++ // and the instruction is not required! + writew(0xf0, base); + readw(base); + +- if (status != word) { +- printf("Flash write error at address 0x%p: 0x%02x\n", +- p, status); +- ret = ERR_PROG_ERROR; +- break; +- } + } + + local_irq_restore(flags); diff --git a/packages/u-boot/u-boot-1.1.4/at32stk1000/cmd-bmp-add-gzip-compressed-bmp.patch b/packages/u-boot/u-boot-1.1.4/at32stk1000/cmd-bmp-add-gzip-compressed-bmp.patch new file mode 100644 index 0000000000..47da73ef5e --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/at32stk1000/cmd-bmp-add-gzip-compressed-bmp.patch @@ -0,0 +1,90 @@ +Index: u-boot-orig/common/cmd_bmp.c +=================================================================== +--- u-boot-orig.orig/common/cmd_bmp.c 2007-01-05 14:50:55.000000000 +0100 ++++ u-boot-orig/common/cmd_bmp.c 2007-01-05 15:59:21.000000000 +0100 +@@ -176,13 +176,83 @@ + */ + static int bmp_display(ulong addr, int x, int y) + { ++ int ret; ++#ifdef CONFIG_VIDEO_BMP_GZIP ++ bmp_image_t *bmp = (bmp_image_t *)addr; ++ unsigned char *dst = NULL; ++ ulong len; ++ ++ if (!((bmp->header.signature[0]=='B') && ++ (bmp->header.signature[1]=='M'))) { ++ ++ /* ++ * Decompress bmp image ++ */ ++ len = CFG_VIDEO_LOGO_MAX_SIZE; ++ dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE); ++ if (dst == NULL) { ++ printf("Error: malloc in gunzip failed!\n"); ++ return(1); ++ } ++ if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)addr, &len) != 0) { ++ free(dst); ++ printf("There is no valid bmp file at the given address\n"); ++ return(1); ++ } ++ if (len == CFG_VIDEO_LOGO_MAX_SIZE) { ++ printf("Image could be truncated " ++ "(increase CFG_VIDEO_LOGO_MAX_SIZE)!\n"); ++ } ++ ++ /* ++ * Set addr to decompressed image ++ */ ++ bmp = (bmp_image_t *)dst; ++ ++ /* ++ * Check for bmp mark 'BM' ++ */ ++ if (!((bmp->header.signature[0] == 'B') && ++ (bmp->header.signature[1] == 'M'))) { ++ printf("There is no valid bmp file at the given address\n"); ++ free(dst); ++ return(1); ++ } ++ } ++ ++ if (dst) { ++ addr = (ulong)dst; ++ } ++#endif /* CONFIG_VIDEO_BMP_GZIP */ ++ + #if defined(CONFIG_LCD) + extern int lcd_display_bitmap (ulong, int, int); + +- return (lcd_display_bitmap (addr, x, y)); ++ ret = lcd_display_bitmap (addr, x, y); ++ if (ret) { ++#ifdef CONFIG_VIDEO_BMP_GZIP ++ free(dst); ++#endif ++ return ret; ++ } ++#ifdef CONFIG_VIDEO_BMP_GZIP ++ free(dst); ++#endif ++ return 0; ++ + #elif defined(CONFIG_VIDEO) + extern int video_display_bitmap (ulong, int, int); +- return (video_display_bitmap (addr, x, y)); ++ ret = video_display_bitmap (addr, x, y); ++ if (ret) { ++#ifdef CONFIG_VIDEO_BMP_GZIP ++ free(dst); ++#endif ++ return ret; ++ } ++#ifdef CONFIG_VIDEO_BMP_GZIP ++ free(dst); ++#endif ++ return 0; + #else + # error bmp_display() requires CONFIG_LCD or CONFIG_VIDEO + #endif diff --git a/packages/u-boot/u-boot-1.1.4/at32stk1000/fix-mmc-data-timeout.patch b/packages/u-boot/u-boot-1.1.4/at32stk1000/fix-mmc-data-timeout.patch new file mode 100644 index 0000000000..d78cbcaaaa --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/at32stk1000/fix-mmc-data-timeout.patch @@ -0,0 +1,101 @@ +--- + cpu/at32ap7xxx/mmc.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 58 insertions(+) + +Index: u-boot-1.1.4-avr32/cpu/at32ap7xxx/mmc.c +=================================================================== +--- u-boot-1.1.4-avr32.orig/cpu/at32ap7xxx/mmc.c 2007-01-30 14:53:33.000000000 +0100 ++++ u-boot-1.1.4-avr32/cpu/at32ap7xxx/mmc.c 2007-01-30 15:45:37.000000000 +0100 +@@ -67,6 +67,7 @@ struct mmci { + unsigned int rca; + block_dev_desc_t blkdev; + const struct device *dev; ++ int card_is_sd; + }; + + struct mmci mmci = { +@@ -391,6 +392,8 @@ static int sd_init_card(struct mmci *mmc + mmc->rca = resp[0] >> 16; + if (verbose) + printf("SD Card detected (RCA %u)\n", mmc->rca); ++ mmc->card_is_sd = 1; ++ + return 0; + } + +@@ -425,6 +428,57 @@ static int mmc_init_card(struct mmci *mm + return ret; + } + ++static void mci_set_data_timeout(struct mmci *mmc, struct mmc_csd *csd) ++{ ++ static const unsigned int dtomul_to_shift[] = { ++ 0, 4, 7, 8, 10, 12, 16, 20, ++ }; ++ static const unsigned int taac_exp[] = { ++ 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, ++ }; ++ static const unsigned int taac_mant[] = { ++ 0, 10, 12, 13, 15, 60, 25, 30, ++ 35, 40, 45, 50, 55, 60, 70, 80, ++ }; ++ unsigned int timeout_ns, timeout_clks; ++ unsigned int e, m; ++ unsigned int dtocyc, dtomul; ++ u32 dtor; ++ ++ e = csd->taac & 0x07; ++ m = (csd->taac >> 3) & 0x0f; ++ ++ timeout_ns = (taac_exp[e] * taac_mant[m] + 9) / 10; ++ timeout_clks = csd->nsac * 100; ++ ++ timeout_clks += (((timeout_ns + 9) / 10) ++ * ((CFG_MMC_CLK_PP + 99999) / 100000) + 9999) / 10000; ++ if (!mmc->card_is_sd) ++ timeout_clks *= 10; ++ else ++ timeout_clks *= 100; ++ ++ dtocyc = timeout_clks; ++ dtomul = 0; ++ while (dtocyc > 15 && dtomul < 8) { ++ dtomul++; ++ dtocyc = timeout_clks >> dtomul_to_shift[dtomul]; ++ } ++ ++ if (dtomul >= 8) { ++ dtomul = 7; ++ dtocyc = 15; ++ puts("Warning: Using maximum data timeout\n"); ++ } ++ ++ dtor = (MMCI_MKBF(MCI_DTOR_DTOMUL, dtomul) ++ | MMCI_MKBF(MCI_DTOR_DTOCYC, dtocyc)); ++ mmci_writel(&mmci, MCI_DTOR, dtor); ++ ++ printf("mmc: Using %u cycles data timeout (DTOR=0x%x)\n", ++ dtocyc << dtomul_to_shift[dtomul], dtor); ++} ++ + int mmc_init(int verbose) + { + struct mmc_cid cid; +@@ -443,6 +497,8 @@ int mmc_init(int verbose) + mmci_writel(&mmci, MCI_IDR, ~0UL); + mci_set_mode(CFG_MMC_CLK_OD, CFG_MMC_BLKLEN); + ++ mmci.card_is_sd = 0; ++ + ret = sd_init_card(&mmci, &cid, verbose); + if (ret) { + mmci.rca = MMC_DEFAULT_RCA; +@@ -458,6 +514,8 @@ int mmc_init(int verbose) + if (verbose) + mmc_dump_csd(&csd); + ++ mci_set_data_timeout(&mmci, &csd); ++ + /* Initialize the blockdev structure */ + sprintf(mmci.blkdev.vendor, + "Man %02x%04x Snr %08x", diff --git a/packages/u-boot/u-boot-1.1.4/at32stk1000/lcd-add-24-bpp-support-and-atmel-lcdc-support.patch b/packages/u-boot/u-boot-1.1.4/at32stk1000/lcd-add-24-bpp-support-and-atmel-lcdc-support.patch new file mode 100644 index 0000000000..126178b286 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/at32stk1000/lcd-add-24-bpp-support-and-atmel-lcdc-support.patch @@ -0,0 +1,670 @@ +Index: u-boot-1.1.4/common/lcd.c +=================================================================== +--- u-boot-1.1.4.orig/common/lcd.c 2007-01-11 15:25:03.000000000 +0100 ++++ u-boot-1.1.4/common/lcd.c 2007-01-11 15:28:54.000000000 +0100 +@@ -34,6 +34,7 @@ + #include + #include + #include ++#include + #include + #include + #if defined(CONFIG_POST) +@@ -81,6 +82,9 @@ + extern void lcd_enable (void); + static void *lcd_logo (void); + ++#ifdef CONFIG_VIDEO_BMP_GZIP ++extern int gunzip(void *, int, unsigned char *, unsigned long *); ++#endif + + #if LCD_BPP == LCD_COLOR8 + extern void lcd_setcolreg (ushort regno, +@@ -112,9 +116,12 @@ + #if 1 + /* Copy up rows ignoring the first one */ + memcpy (CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, CONSOLE_SCROLL_SIZE); +- + /* Clear the last one */ + memset (CONSOLE_ROW_LAST, COLOR_MASK(lcd_color_bg), CONSOLE_ROW_SIZE); ++#ifdef CONFIG_AVR32 ++ /* flush cache */ ++ dcache_clean_range(CONSOLE_ROW_FIRST, CONSOLE_SIZE); ++#endif + #else + /* + * Poor attempt to optimize speed by moving "long"s. +@@ -228,10 +235,23 @@ + static void lcd_drawchars (ushort x, ushort y, uchar *str, int count) + { + uchar *dest; +- ushort off, row; ++ ushort off, row, bpp, bytespp; ++#ifdef CONFIG_AVR32 ++ uchar *dest_start; ++#endif + +- dest = (uchar *)(lcd_base + y * lcd_line_length + x * (1 << LCD_BPP) / 8); +- off = x * (1 << LCD_BPP) % 8; ++#if (LCD_BPP > LCD_COLOR32) ++ bpp = LCD_BPP; ++#else ++ bpp = 1<fb_base); + +- lcd_line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; ++ if (panel_info.vl_bpix > LCD_COLOR32) ++ lcd_line_length = (panel_info.vl_col * panel_info.vl_bpix) / 8; ++ else ++ lcd_line_length = (panel_info.vl_col ++ * NBITS (panel_info.vl_bpix)) / 8; + + lcd_init (lcd_base); /* LCD initialization */ + +@@ -407,6 +445,11 @@ + console_col = 0; + console_row = 0; + ++#ifdef CONFIG_AVR32 ++ /* flush cache */ ++ dcache_clean_range(CONSOLE_ROW_FIRST, CONSOLE_SIZE); ++#endif ++ + return (0); + } + +@@ -453,10 +496,17 @@ + ulong lcd_setmem (ulong addr) + { + ulong size; +- int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; ++ int bpp; ++ int line_length; ++ if (panel_info.vl_bpix > LCD_COLOR32) ++ bpp = panel_info.vl_bpix; ++ else ++ bpp = NBITS (panel_info.vl_bpix); ++ ++ line_length = (panel_info.vl_col * bpp) / 8; + + debug ("LCD panel info: %d x %d, %d bit/pix\n", +- panel_info.vl_col, panel_info.vl_row, NBITS (panel_info.vl_bpix) ); ++ panel_info.vl_col, panel_info.vl_row, bpp); + + size = line_length * panel_info.vl_row; + +@@ -475,14 +525,22 @@ + + static void lcd_setfgcolor (int color) + { ++#if LCD_BPP <= LCD_COLOR8 + lcd_color_fg = color & 0x0F; ++#else ++ lcd_color_fg = color; ++#endif + } + + /*----------------------------------------------------------------------*/ + + static void lcd_setbgcolor (int color) + { ++#if LCD_BPP <= LCD_COLOR8 + lcd_color_bg = color & 0x0F; ++#else ++ lcd_color_bg = color; ++#endif + } + + /*----------------------------------------------------------------------*/ +@@ -509,7 +567,11 @@ + #ifdef CONFIG_LCD_LOGO + void bitmap_plot (int x, int y) + { ++#if !defined(CONFIG_ATMEL_LCDC) + ushort *cmap; ++#else ++ ulong *cmap; ++#endif + ushort i, j; + uchar *bmap; + uchar *fb; +@@ -519,6 +581,8 @@ + #elif defined(CONFIG_MPC823) + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile cpm8xx_t *cp = &(immr->im_cpm); ++#elif defined(CONFIG_ATMEL_LCDC) ++ struct lcdc_info *cinfo = panel_info.lcdc; + #endif + + debug ("Logo: width %d height %d colors %d cmap %d\n", +@@ -534,6 +598,8 @@ + cmap = (ushort *)fbi->palette; + #elif defined(CONFIG_MPC823) + cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]); ++#elif defined(CONFIG_ATMEL_LCDC) ++ cmap = (ulong *)(cinfo->palette) + BMP_LOGO_OFFSET; + #endif + + WATCHDOG_RESET(); +@@ -541,10 +607,19 @@ + /* Set color map */ + for (i=0; i<(sizeof(bmp_logo_palette)/(sizeof(ushort))); ++i) { + ushort colreg = bmp_logo_palette[i]; ++#if defined(CONFIG_ATMEL_LCDC) ++ /* convert to match palette registers */ ++ uchar red = (colreg >> 8) & 0x0f; ++ uchar green = (colreg >> 4) & 0x0f; ++ uchar blue = (colreg >> 0) & 0x0f; ++ colreg = (blue << 11); ++ colreg |= (green << 6); ++ colreg |= (red << 1); ++#endif + #ifdef CFG_INVERT_COLORS +- *cmap++ = 0xffff - colreg; ++ *(cmap++) = 0xffff - colreg; + #else +- *cmap++ = colreg; ++ *(cmap++) = colreg; + #endif + } + +@@ -579,14 +654,16 @@ + */ + int lcd_display_bitmap(ulong bmp_image, int x, int y) + { ++#if !defined(CONFIG_ATMEL_LCDC) + ushort *cmap; ++#endif + ushort i, j; + uchar *fb; + bmp_image_t *bmp=(bmp_image_t *)bmp_image; + uchar *bmap; + ushort padded_line; + unsigned long width, height; +- unsigned colors,bpix; ++ unsigned colors,bpix,bpp,bytespp; + unsigned long compression; + #if defined(CONFIG_PXA250) + struct pxafb_info *fbi = &panel_info.pxa; +@@ -597,82 +674,126 @@ + + if (!((bmp->header.signature[0]=='B') && + (bmp->header.signature[1]=='M'))) { +- printf ("Error: no valid bmp image at %lx\n", bmp_image); ++ printf ("[LCD] No valid BMP image at 0x%08lx\n", bmp_image); + return 1; +-} ++ } + + width = le32_to_cpu (bmp->header.width); + height = le32_to_cpu (bmp->header.height); ++ bpp = le16_to_cpu (bmp->header.bit_count); + colors = 1<header.bit_count); + compression = le32_to_cpu (bmp->header.compression); ++ bytespp = (panel_info.vl_bpix + 7) / 8; + +- bpix = NBITS(panel_info.vl_bpix); ++ if (panel_info.vl_bpix > LCD_COLOR32) ++ bpix = panel_info.vl_bpix; ++ else ++ bpix = NBITS(panel_info.vl_bpix); + +- if ((bpix != 1) && (bpix != 8)) { ++ if ((bpix != 1) && (bpix != 8) && (bpix != 24)) { + printf ("Error: %d bit/pixel mode not supported by U-Boot\n", + bpix); + return 1; + } + +- if (bpix != le16_to_cpu(bmp->header.bit_count)) { ++ if (bpix != bpp) { + printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n", +- bpix, +- le16_to_cpu(bmp->header.bit_count)); ++ bpix, bpp); + return 1; + } + +- debug ("Display-bmp: %d x %d with %d colors\n", +- (int)width, (int)height, (int)colors); ++ debug ("Display-bmp: %d x %d with %d colors (%d bpp)\n", ++ (int)width, (int)height, (int)colors, (int)bpp); + +- if (bpix==8) { ++ if (bpix == 8) { + #if defined(CONFIG_PXA250) + cmap = (ushort *)fbi->palette; + #elif defined(CONFIG_MPC823) + cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]); ++#elif defined(CONFIG_ATMEL_LCDC) ++ /* no need to have a palette link, we use lcd_setcolreg */ + #else + # error "Don't know location of color map" + #endif + + /* Set color map */ + for (i=0; icolor_table[i]; ++#endif ++#if !defined(CONFIG_ATMEL_LCDC) + ushort colreg = + ( ((cte.red) << 8) & 0xf800) | + ( ((cte.green) << 3) & 0x07e0) | + ( ((cte.blue) >> 3) & 0x001f) ; + #ifdef CFG_INVERT_COLORS +- *cmap = 0xffff - colreg; +-#else +- *cmap = colreg; ++ colreg = 0xffff - colreg; + #endif + #if defined(CONFIG_PXA250) +- cmap++; ++ cmap[i] = colreg; + #elif defined(CONFIG_MPC823) +- cmap--; ++ cmap[colors-i] = colreg; ++#endif ++#else /* CONFIG_ATMEL_LCDC */ ++#if LCD_BPP <= LCD_COLOR8 ++ lcd_setcolreg(i, cte.red, cte.green, cte.blue); ++#endif + #endif + } + } + +- padded_line = (width&0x3) ? ((width&~0x3)+4) : (width); +- if ((x + width)>panel_info.vl_col) ++ padded_line = (((width * bpp + 7) / 8) + 3) & ~0x3; ++ if ((x + width) > panel_info.vl_col) + width = panel_info.vl_col - x; +- if ((y + height)>panel_info.vl_row) ++ if ((y + height) > panel_info.vl_row) + height = panel_info.vl_row - y; + + bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset); +- fb = (uchar *) (lcd_base + +- (y + height - 1) * lcd_line_length + x); +- for (i = 0; i < height; ++i) { +- WATCHDOG_RESET(); +- for (j = 0; j < width ; j++) ++ fb = (uchar *) (lcd_base + (y + height - 1) * lcd_line_length + x); ++ ++ switch (bpp) { ++ case 24: ++ for (i = 0; i < height; ++i) { ++ WATCHDOG_RESET(); ++ for (j = 0; j < width; j++) { + #if defined(CONFIG_PXA250) +- *(fb++)=*(bmap++); ++#error 24 bpp support not added for PXA250 ++#elif defined(CONFIG_ATMEL_LCDC) ++ fb[0] = bmap[0]; ++ fb[1] = bmap[1]; ++ fb[2] = bmap[2]; ++ fb += 3; ++ bmap += 3; + #elif defined(CONFIG_MPC823) +- *(fb++)=255-*(bmap++); ++#error 24 bpp support not added for MPC823 + #endif +- bmap += (width - padded_line); +- fb -= (width + lcd_line_length); +- } ++ } ++ bmap += (width * bytespp - padded_line); ++ fb -= (width * bytespp + lcd_line_length); ++ } ++ break; ++ case 1: /* pass through */ ++ case 8: ++ for (i = 0; i < height; ++i) { ++ WATCHDOG_RESET(); ++ for (j = 0; j < width; j++) { ++#if defined(CONFIG_PXA250) ++ *(fb++)=*(bmap++); ++#elif defined(CONFIG_ATMEL_LCDC) ++ *(fb++)=*(bmap++); ++#elif defined(CONFIG_MPC823) ++ *(fb++)=255-*(bmap++); ++#endif ++ } ++ bmap += (width * bytespp - padded_line); ++ fb -= (width * bytespp + lcd_line_length); ++ } ++ break; ++ default: ++ break; ++ }; ++ ++ /* TODO: flush fb */ + + return (0); + } +@@ -694,12 +815,68 @@ + static int do_splash = 1; + + if (do_splash && (s = getenv("splashimage")) != NULL) { ++#ifdef CONFIG_VIDEO_BMP_GZIP ++ bmp_image_t *bmp; ++ unsigned char *dst = NULL; ++ ulong len; ++#endif + addr = simple_strtoul(s, NULL, 16); + do_splash = 0; + ++#ifdef CONFIG_VIDEO_BMP_GZIP ++ bmp = (bmp_image_t *)addr; ++ ++ if (!((bmp->header.signature[0]=='B') && ++ (bmp->header.signature[1]=='M'))) { ++ len = CFG_VIDEO_LOGO_MAX_SIZE; ++ dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE); ++ if (dst == NULL) { ++ printf("[LCD] Malloc for gunzip failed!\n"); ++ return ((void *)lcd_base); ++ } ++ if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, ++ (uchar *)addr, &len) != 0) { ++ free(dst); ++ printf("[LCD] No valid BMP image at 0x%08lx\n", ++ addr); ++ return ((void *)lcd_base); ++ } ++ if (len == CFG_VIDEO_LOGO_MAX_SIZE) { ++ printf("[LCD] Image could be truncated (increase " ++ "CFG_VIDEO_LOGO_MAX_SIZE)!\n"); ++ } ++ ++ /* ++ * Set addr to decompressed image ++ */ ++ bmp = (bmp_image_t *)dst; ++ ++ /* ++ * Check for bmp mark 'BM' ++ */ ++ if (!((bmp->header.signature[0] == 'B') && ++ (bmp->header.signature[1] == 'M'))) { ++ printf("[LCD] No valid BMP image at 0x%08lx\n", ++ addr); ++ free(dst); ++ return ((void *)lcd_base); ++ } ++ ++ addr = (ulong)dst; ++ } ++#endif + if (lcd_display_bitmap (addr, 0, 0) == 0) { ++#ifdef CONFIG_VIDEO_BMP_GZIP ++ if (dst) ++ free(dst); ++#endif + return ((void *)lcd_base); + } ++ ++#ifdef CONFIG_VIDEO_BMP_GZIP ++ if (dst) ++ free(dst); ++#endif + } + #endif /* CONFIG_SPLASH_SCREEN */ + +Index: u-boot-1.1.4/include/lcd.h +=================================================================== +--- u-boot-1.1.4.orig/include/lcd.h 2007-01-11 15:25:03.000000000 +0100 ++++ u-boot-1.1.4/include/lcd.h 2007-01-11 15:25:38.000000000 +0100 +@@ -148,7 +148,159 @@ + + extern vidinfo_t panel_info; + +-#endif /* CONFIG_MPC823 or CONFIG_PXA250 */ ++#elif defined CONFIG_ATMEL_LCDC ++struct lcdc_bitfield { ++ u32 offset; /* beginning of bitfield */ ++ u32 length; /* length of bitfield */ ++ u32 msb_right; /* != 0 : Most significant bit is right */ ++}; ++ ++struct lcdc_var_screeninfo { ++ u32 xres; /* visible resolution */ ++ u32 yres; ++ u32 xres_virtual; /* virtual resolution */ ++ u32 yres_virtual; ++ u32 xoffset; /* offset from virtual to visible */ ++ u32 yoffset; /* resolution */ ++ ++ u32 bits_per_pixel; /* guess what */ ++ u32 grayscale; /* != 0 Graylevels instead of colors */ ++ ++ struct lcdc_bitfield red; /* bitfield in fb mem if true color, */ ++ struct lcdc_bitfield green; /* else only length is significant */ ++ struct lcdc_bitfield blue; ++ struct lcdc_bitfield transp; /* transparency */ ++ ++ u32 nonstd; /* != 0 Non standard pixel format */ ++ ++ u32 activate; /* see FB_ACTIVATE_* */ ++ ++ u32 height; /* height of picture in mm */ ++ u32 width; /* width of picture in mm */ ++ ++ u32 accel_flags; /* (OBSOLETE) see fb_info.flags */ ++ ++ /* Timing: All values in pixclocks, except pixclock (of course) */ ++ u32 pixclock; /* pixel clock in ps (pico seconds) */ ++ u32 left_margin; /* time from sync to picture */ ++ u32 right_margin; /* time from picture to sync */ ++ u32 upper_margin; /* time from sync to picture */ ++ u32 lower_margin; ++ u32 hsync_len; /* length of horizontal sync */ ++ u32 vsync_len; /* length of vertical sync */ ++ u32 sync; /* see FB_SYNC_* */ ++ u32 vmode; /* see FB_VMODE_* */ ++ u32 rotate; /* angle we rotate counter clockwise */ ++ u32 reserved[5]; /* Reserved for future compatibility */ ++}; ++ ++/* ++ * Atmel LCDC DMA descriptor ++ */ ++struct lcdc_dma_descriptor { ++ u_long fdadr; /* Frame descriptor address register */ ++ u_long fsadr; /* Frame source address register */ ++ u_long fidr; /* Frame ID register */ ++ u_long ldcmd; /* Command register */ ++}; ++ ++/* ++ * Atmel LCDC info ++ */ ++struct lcdc_info { ++ u_long reg_lccr3; ++ u_long reg_lccr2; ++ u_long reg_lccr1; ++ u_long reg_lccr0; ++ u_long fdadr0; ++ u_long fdadr1; ++ ++ void *regs; ++ ++ u_long guard_time; ++ u_long xres; ++ u_long yres; ++ u_long xres_virtual; ++ u_long yres_virtual; ++ u_long bits_per_pixel; ++ u_long smem_start; ++ u_long line_length; ++ u_long visual; ++ ++ u_long pixclock; ++ u_long left_margin; ++ u_long right_margin; ++ u_long upper_margin; ++ u_long lower_margin; ++ u_long hsync_len; ++ u_long vsync_len; ++ u_long sync; ++ u_long yoffset; ++ u_long xoffset; ++ ++ struct lcdc_var_screeninfo var; ++ ++ /* DMA descriptors */ ++ struct lcdc_dma_descriptor *dmadesc_fblow; ++ struct lcdc_dma_descriptor *dmadesc_fbhigh; ++ struct lcdc_dma_descriptor *dmadesc_palette; ++ ++ u_long screen; /* physical address of frame buffer */ ++ u_long palette; /* physical address of palette memory */ ++ u_int palette_size; ++ ++ /* Device resource */ ++ const struct device *dev; ++}; ++ ++/* ++ * LCD controller stucture for AVR32 CPU ++ */ ++typedef struct vidinfo { ++ ushort vl_col; /* Number of columns (i.e. 640) */ ++ ushort vl_row; /* Number of rows (i.e. 480) */ ++ ushort vl_width; /* Width of display area in millimeters */ ++ ushort vl_height; /* Height of display area in millimeters */ ++ ++ /* LCD configuration register */ ++ u_char vl_clkp; /* Clock polarity */ ++ u_char vl_oep; /* Output Enable polarity */ ++ u_char vl_hsp; /* Horizontal Sync polarity */ ++ u_char vl_vsp; /* Vertical Sync polarity */ ++ u_char vl_dp; /* Data polarity */ ++ u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ ++ u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ ++ u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */ ++ u_char vl_clor; /* Color, 0 = mono, 1 = color */ ++ u_char vl_tft; /* 0 = passive, 1 = TFT */ ++ ++ /* Horizontal control register. Timing from data sheet */ ++ ushort vl_hpw; /* Horz sync pulse width */ ++ u_char vl_blw; /* Wait before of line */ ++ u_char vl_elw; /* Wait end of line */ ++ ++ /* Vertical control register. */ ++ u_char vl_vpw; /* Vertical sync pulse width */ ++ u_char vl_bfw; /* Wait before of frame */ ++ u_char vl_efw; /* Wait end of frame */ ++ ++ /* Atmel LCDC controller params */ ++ struct lcdc_info *lcdc; ++ u_long pixclock; ++ u_long left_margin; ++ u_long right_margin; ++ u_long upper_margin; ++ u_long lower_margin; ++ u_long hsync_len; ++ u_long vsync_len; ++ u_long sync; ++ u_long yoffset; ++ u_long xoffset; ++} vidinfo_t; ++ ++extern vidinfo_t panel_info; ++ ++#endif /* CONFIG_MPC823 or CONFIG_PXA250 or CONFIG_ATMEL_LCDC */ + + /* Video functions */ + +@@ -184,6 +336,16 @@ + #define LCD_COLOR4 2 + #define LCD_COLOR8 3 + #define LCD_COLOR16 4 ++#define LCD_COLOR32 5 ++#define LCD_COLOR15 15 ++#define LCD_COLOR24 24 ++ ++#define FB_VISUAL_MONO01 0 /* Monochr. 1=Black 0=White */ ++#define FB_VISUAL_MONO10 1 /* Monochr. 1=White 0=Black */ ++#define FB_VISUAL_TRUECOLOR 2 /* True color */ ++#define FB_VISUAL_PSEUDOCOLOR 3 /* Pseudo color (like atari) */ ++#define FB_VISUAL_DIRECTCOLOR 4 /* Direct color */ ++#define FB_VISUAL_STATIC_PSEUDOCOLOR 5 /* Pseudo color readonly */ + + /*----------------------------------------------------------------------*/ + #if defined(CONFIG_LCD_INFO_BELOW_LOGO) +@@ -235,7 +397,7 @@ + # define CONSOLE_COLOR_GREY 14 + # define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */ + +-#else ++#elif LCD_BPP == LCD_COLOR16 + + /* + * 16bpp color definitions +@@ -243,6 +405,14 @@ + # define CONSOLE_COLOR_BLACK 0x0000 + # define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */ + ++#else ++ ++/* ++ * 24bpp color definitions ++ */ ++# define CONSOLE_COLOR_BLACK 0x000000 ++# define CONSOLE_COLOR_WHITE 0xffffff /* Must remain last / highest */ ++ + #endif /* color definitions */ + + /************************************************************************/ +@@ -274,6 +444,8 @@ + (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7) + #elif LCD_BPP == LCD_COLOR8 + # define COLOR_MASK(c) (c) ++#elif LCD_BPP == LCD_COLOR24 ++# define COLOR_MASK(c) (c) + #else + # error Unsupported LCD BP