From 3c16468c15eee985e8b99040654f4d52466bd613 Mon Sep 17 00:00:00 2001 From: Steve Sakoman Date: Wed, 18 Jun 2008 15:04:42 +0000 Subject: u-boot beagleboard: update with latest patches and upstream changes --- packages/u-boot/u-boot-git/beagleboard/base.patch | 3496 +++++++++------------ packages/u-boot/u-boot_git.bb | 4 +- 2 files changed, 1571 insertions(+), 1929 deletions(-) (limited to 'packages') diff --git a/packages/u-boot/u-boot-git/beagleboard/base.patch b/packages/u-boot/u-boot-git/beagleboard/base.patch index a5f118275b..1d3a9e5154 100644 --- a/packages/u-boot/u-boot-git/beagleboard/base.patch +++ b/packages/u-boot/u-boot-git/beagleboard/base.patch @@ -1,5 +1,5 @@ diff --git a/Makefile b/Makefile -index cc988e1..16701c5 100644 +index 8bfc891..e9bf61a 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ ifeq ($(ARCH),ppc) @@ -20,7 +20,7 @@ index cc988e1..16701c5 100644 # The "tools" are needed early, so put this first # Don't include stuff already done in $(LIBS) -@@ -2562,6 +2562,12 @@ SMN42_config : unconfig +@@ -2565,6 +2565,12 @@ SMN42_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm720t SMN42 siemens lpc2292 ######################################################################### @@ -88,10 +88,10 @@ index 0000000..7065345 +######################################################################### diff --git a/board/omap3530beagle/clock.c b/board/omap3530beagle/clock.c new file mode 100644 -index 0000000..964525b +index 0000000..1f4b4f3 --- /dev/null +++ b/board/omap3530beagle/clock.c -@@ -0,0 +1,316 @@ +@@ -0,0 +1,314 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, @@ -121,14 +121,12 @@ index 0000000..964525b + */ + +#include -+#include +#include +#include +#include +#include +#include +#include -+#include +#include +#include + @@ -433,10 +431,10 @@ index 0000000..9639c43 + diff --git a/board/omap3530beagle/lowlevel_init.S b/board/omap3530beagle/lowlevel_init.S new file mode 100644 -index 0000000..7ec4d05 +index 0000000..1f9a0e9 --- /dev/null +++ b/board/omap3530beagle/lowlevel_init.S -@@ -0,0 +1,361 @@ +@@ -0,0 +1,360 @@ +/* + * Board specific setup info + * @@ -468,7 +466,6 @@ index 0000000..7ec4d05 + +#include +#include -+#include +#include +#include + @@ -800,10 +797,10 @@ index 0000000..7ec4d05 + diff --git a/board/omap3530beagle/mem.c b/board/omap3530beagle/mem.c new file mode 100644 -index 0000000..bee96c3 +index 0000000..fb803be --- /dev/null +++ b/board/omap3530beagle/mem.c -@@ -0,0 +1,251 @@ +@@ -0,0 +1,250 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, @@ -829,7 +826,6 @@ index 0000000..bee96c3 + */ + +#include -+#include +#include +#include +#include @@ -1057,10 +1053,10 @@ index 0000000..bee96c3 +} diff --git a/board/omap3530beagle/nand.c b/board/omap3530beagle/nand.c new file mode 100644 -index 0000000..4a8b6e4 +index 0000000..2f94684 --- /dev/null +++ b/board/omap3530beagle/nand.c -@@ -0,0 +1,409 @@ +@@ -0,0 +1,408 @@ +/* + * (C) Copyright 2004-2008 Texas Instruments, + * Rohit Choraria @@ -1086,7 +1082,6 @@ index 0000000..4a8b6e4 + +#include +#include -+#include +#include +#include + @@ -1472,10 +1467,10 @@ index 0000000..4a8b6e4 +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ diff --git a/board/omap3530beagle/omap3530beagle.c b/board/omap3530beagle/omap3530beagle.c new file mode 100644 -index 0000000..1daf42c +index 0000000..7d9a566 --- /dev/null +++ b/board/omap3530beagle/omap3530beagle.c -@@ -0,0 +1,781 @@ +@@ -0,0 +1,388 @@ +/* + * (C) Copyright 2004-2008 + * Texas Instruments, @@ -1508,12 +1503,10 @@ index 0000000..1daf42c + * MA 02111-1307 USA + */ +#include -+#include +#include +#include +#include +#include -+#include +#include +#include +#include @@ -1523,54 +1516,47 @@ index 0000000..1daf42c +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; +#endif + -+/* -+ * Dummy functions to handle errors for EABI incompatibility -+ */ -+void raise(void) -+{ -+} -+ -+void abort(void) -+{ -+} ++#define NOT_EARLY 0 + ++/* Permission values for registers -Full fledged permissions to all */ ++#define UNLOCK_1 0xFFFFFFFF ++#define UNLOCK_2 0x00000000 ++#define UNLOCK_3 0x0000FFFF + -+/******************************************************* ++/****************************************************************************** + * Routine: delay + * Description: spinning delay to use before udelay works -+ ******************************************************/ ++ *****************************************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + -+/***************************************** ++/****************************************************************************** + * Routine: board_init + * Description: Early hardware init. -+ *****************************************/ ++ *****************************************************************************/ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + -+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ -+ gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE; /* board id for Linux */ -+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); /* boot param addr */ ++ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ ++ /* board id for Linux */ ++ gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE; ++ /* boot param addr */ ++ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + -+/***************************************** ++/****************************************************************************** + * Routine: secure_unlock -+ * Description: Setup security registers for access -+ * (GP Device only) -+ *****************************************/ ++ * Description: Setup security registers for access ++ * (GP Device only) ++ *****************************************************************************/ +void secure_unlock_mem(void) +{ -+ /* Permission values for registers -Full fledged permissions to all */ -+#define UNLOCK_1 0xFFFFFFFF -+#define UNLOCK_2 0x00000000 -+#define UNLOCK_3 0x0000FFFF + /* Protection Module Register Target APE (PM_RT) */ + __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); @@ -1594,12 +1580,12 @@ index 0000000..1daf42c + __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ +} + -+/********************************************************** ++/****************************************************************************** + * Routine: secureworld_exit() + * Description: If chip is EMU and boot type is external + * configure secure registers and exit secure world -+ * general use. -+ ***********************************************************/ ++ * general use. ++ *****************************************************************************/ +void secureworld_exit() +{ + unsigned long i; @@ -1624,11 +1610,11 @@ index 0000000..1daf42c + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i)); +} + -+/********************************************************** ++/****************************************************************************** + * Routine: setup_auxcr() + * Description: Write to AuxCR desired value using SMI. -+ * general use. -+ ***********************************************************/ ++ * general use. ++ *****************************************************************************/ +void setup_auxcr() +{ + unsigned long i; @@ -1649,11 +1635,11 @@ index 0000000..1daf42c + __asm__ __volatile__("mov r12, %0":"=r"(j)); +} + -+/********************************************************** ++/****************************************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP/EMU(special) type, unlock the SRAM for -+ * general use. -+ ***********************************************************/ ++ * general use. ++ *****************************************************************************/ +void try_unlock_memory() +{ + int mode; @@ -1662,11 +1648,11 @@ index 0000000..1daf42c + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device - HS/E/T */ + mode = get_device_type(); -+ if (mode == GP_DEVICE) { ++ if (mode == GP_DEVICE) + secure_unlock_mem(); -+ } -+ /* If device is EMU and boot is XIP external booting -+ * Unlock firewalls and disable L2 and put chip ++ ++ /* If device is EMU and boot is XIP external booting ++ * Unlock firewalls and disable L2 and put chip + * out of secure world + */ + /* Assuming memories are unlocked by the demon who put us in SDRAM */ @@ -1679,23 +1665,21 @@ index 0000000..1daf42c + return; +} + -+/********************************************************** ++/****************************************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. -+ * - Called path is with SRAM stack. -+ **********************************************************/ ++ * - Called path is with SRAM stack. ++ *****************************************************************************/ +void s_init(void) +{ + int in_sdram = running_in_sdram(); + -+#ifdef CONFIG_3430VIRTIO -+ in_sdram = 0; /* allow setup from memory for Virtio */ -+#endif + watchdog_init(); + + try_unlock_memory(); + -+ /* Right now flushing at low MPU speed. Need to move after clock init */ ++ /* Right now flushing at low MPU speed. ++ Need to move after clock init */ + v7_flush_dcache_all(get_device_type()); +#ifndef CONFIG_ICACHE_OFF + icache_enable(); @@ -1723,12 +1707,14 @@ index 0000000..1daf42c + if (!in_sdram) + sdrc_init(); +} -+/******************************************************* ++ ++/****************************************************************************** + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) -+ ********************************************************/ ++ *****************************************************************************/ +int misc_init_r(void) +{ ++ + unsigned char byte; + +#ifdef CONFIG_DRIVER_OMAP34XX_I2C @@ -1757,10 +1743,11 @@ index 0000000..1daf42c + return (0); +} + -+/****************************************************** ++ ++/****************************************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog -+ ******************************************************/ ++ *****************************************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; @@ -1769,15 +1756,15 @@ index 0000000..1daf42c + } while (pending); +} + -+/**************************************** ++/****************************************************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs -+ *****************************************/ ++ *****************************************************************************/ +void watchdog_init(void) +{ -+ /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is ++ /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is + * either taken care of by ROM (HS/EMU) or not accessible (GP). -+ * We need to take care of WD2-MPU or take a PRCM reset. WD3 ++ * We need to take care of WD2-MPU or take a PRCM reset. WD3 + * should not be running and does not generate a PRCM reset. + */ + @@ -1790,68 +1777,28 @@ index 0000000..1daf42c + __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); +} + -+/******************************************************************* -+ * Routine:ether_init -+ * Description: take the Ethernet controller out of reset and wait -+ * for the EEPROM load to complete. -+ ******************************************************************/ -+void ether_init(void) -+{ -+#ifdef CONFIG_DRIVER_LAN91C96 -+ int cnt = 20; -+ -+ __raw_writew(0x0, LAN_RESET_REGISTER); -+ do { -+ __raw_writew(0x1, LAN_RESET_REGISTER); -+ udelay(100); -+ if (cnt == 0) -+ goto h4reset_err_out; -+ --cnt; -+ } while (__raw_readw(LAN_RESET_REGISTER) != 0x1); -+ -+ cnt = 20; -+ -+ do { -+ __raw_writew(0x0, LAN_RESET_REGISTER); -+ udelay(100); -+ if (cnt == 0) -+ goto h4reset_err_out; -+ --cnt; -+ } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000); -+ udelay(1000); -+ -+ *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; -+ udelay(1000); -+ -+ h4reset_err_out: -+ return; -+#endif -+} -+ -+/********************************************** ++/****************************************************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size -+ **********************************************/ ++ *****************************************************************************/ +int dram_init(void) +{ -+#define NOT_EARLY 0 + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0, size1 = 0; + u32 mtype, btype; + + btype = get_board_type(); + mtype = get_mem_type(); -+#ifndef CONFIG_3430ZEBU -+ /* fixme... dont know why this func is crashing in ZeBu */ ++ + display_board_info(btype); -+#endif -+ /* If a second bank of DDR is attached to CS1 this is ++ ++ /* If a second bank of DDR is attached to CS1 this is + * where it can be started. Early init code will init + * memory on CS0. + */ -+ if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) { ++ if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) + do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); -+ } ++ + size0 = get_sdr_cs_size(SDRC_CS0_OSET); + size1 = get_sdr_cs_size(SDRC_CS1_OSET); + @@ -1863,449 +1810,98 @@ index 0000000..1daf42c + return 0; +} + -+#define MUX_VAL(OFFSET,VALUE)\ -+ __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); ++/****************************************************************************** ++ * Routine: set_muxconf_regs ++ * Description: Setting up the configuration Mux registers specific to the ++ * hardware. Many pins need to be moved from protect to primary ++ * mode. ++ *****************************************************************************/ ++void set_muxconf_regs(void) ++{ ++ MUX_DEFAULT_ES2(); ++} + -+#define CP(x) (CONTROL_PADCONF_##x) ++#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) ++/****************************************************************************** ++ * Routine: nand+_init ++ * Description: Set up nand for nand and jffs2 commands ++ *****************************************************************************/ ++void nand_init(void) ++{ ++ extern flash_info_t flash_info[]; ++ ++ nand_probe(CFG_NAND_ADDR); ++ if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) ++ print_size(nand_dev_desc[0].totlen, "\n"); ++ ++#ifdef CFG_JFFS2_MEM_NAND ++ flash_info[CFG_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id; ++ /* only read kernel single meg partition */ ++ flash_info[CFG_JFFS2_FIRST_BANK].size = 1024 * 1024 * 2; ++ /* 1024 blocks in 16meg chip (use less for raw/copied partition) */ ++ flash_info[CFG_JFFS2_FIRST_BANK].sector_count = 1024; ++ /* ?, ram for now, open question, copy to RAM or adapt for NAND */ ++ flash_info[CFG_JFFS2_FIRST_BANK].start[0] = 0x80200000; ++#endif ++} ++#endif ++ ++/****************************************************************************** ++ * Dummy function to handle errors for EABI incompatibility ++ *****************************************************************************/ ++void raise(void) ++{ ++} ++ ++/****************************************************************************** ++ * Dummy function to handle errors for EABI incompatibility ++ *****************************************************************************/ ++void abort(void) ++{ ++} +diff --git a/board/omap3530beagle/sys_info.c b/board/omap3530beagle/sys_info.c +new file mode 100644 +index 0000000..a275557 +--- /dev/null ++++ b/board/omap3530beagle/sys_info.c +@@ -0,0 +1,309 @@ +/* -+ * IEN - Input Enable -+ * IDIS - Input Disable -+ * PTD - Pull type Down -+ * PTU - Pull type Up -+ * DIS - Pull type selection is inactive -+ * EN - Pull type selection is active -+ * M0 - Mode 0 -+ * The commented string gives the final mux configuration for that pin -+ */ -+#define MUX_DEFAULT_ES2()\ -+ /*SDRC*/\ -+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ -+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ -+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ -+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ -+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ -+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ -+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ -+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ -+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ -+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ -+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ -+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ -+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ -+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ -+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ -+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ -+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ -+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ -+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ -+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ -+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ -+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ -+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ -+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ -+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ -+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ -+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ -+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ -+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ -+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ -+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ -+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ -+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ -+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ -+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ -+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ -+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ -+ /*GPMC*/\ -+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ -+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ -+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ -+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ -+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ -+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ -+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ -+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ -+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ -+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ -+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ -+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ -+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ -+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ -+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ -+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ -+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ -+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ -+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ -+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ -+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ -+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ -+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ -+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ -+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ -+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ -+ MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ -+ MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ -+ MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ -+ MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ -+ /* For Beagle Rev 1 boards */\ -+ /*MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0))\ -+ MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0))\ -+ MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0))\ -+ MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0))\ -+ MUX_VAL(CP(GPMC_nBE1), (IDIS | PTD | DIS | M4))\ -+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4))\ -+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4))*/\ -+ /* For Beagle Rev 2 boards*/\ -+ MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0))\ -+ MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0))\ -+ MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1))\ -+ MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1))\ -+ MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0))\ -+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0))\ -+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0))\ -+ /* till here */\ -+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ -+ MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ -+ MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ -+ MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ -+ MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ -+ MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ -+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ -+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ -+ /*DSS*/\ -+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ -+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ -+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ -+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ -+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ -+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ -+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ -+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ -+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ -+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ -+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ -+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ -+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ -+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ -+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ -+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ -+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ -+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ -+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ -+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ -+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ -+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ -+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ -+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ -+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ -+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ -+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ -+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ -+ /*CAMERA*/\ -+ MUX_VAL(CP(CAM_HS ), (IEN | PTU | EN | M0)) /*CAM_HS */\ -+ MUX_VAL(CP(CAM_VS ), (IEN | PTU | EN | M0)) /*CAM_VS */\ -+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ -+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\ -+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98 - CAM_RESET*/\ -+ MUX_VAL(CP(CAM_D0 ), (IEN | PTD | DIS | M0)) /*CAM_D0 */\ -+ MUX_VAL(CP(CAM_D1 ), (IEN | PTD | DIS | M0)) /*CAM_D1 */\ -+ MUX_VAL(CP(CAM_D2 ), (IEN | PTD | DIS | M0)) /*CAM_D2 */\ -+ MUX_VAL(CP(CAM_D3 ), (IEN | PTD | DIS | M0)) /*CAM_D3 */\ -+ MUX_VAL(CP(CAM_D4 ), (IEN | PTD | DIS | M0)) /*CAM_D4 */\ -+ MUX_VAL(CP(CAM_D5 ), (IEN | PTD | DIS | M0)) /*CAM_D5 */\ -+ MUX_VAL(CP(CAM_D6 ), (IEN | PTD | DIS | M0)) /*CAM_D6 */\ -+ MUX_VAL(CP(CAM_D7 ), (IEN | PTD | DIS | M0)) /*CAM_D7 */\ -+ MUX_VAL(CP(CAM_D8 ), (IEN | PTD | DIS | M0)) /*CAM_D8 */\ -+ MUX_VAL(CP(CAM_D9 ), (IEN | PTD | DIS | M0)) /*CAM_D9 */\ -+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\ -+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\ -+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ -+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ -+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ -+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ -+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ -+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ -+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ -+ /*Audio Interface */\ -+ MUX_VAL(CP(McBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ -+ MUX_VAL(CP(McBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ -+ MUX_VAL(CP(McBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ -+ MUX_VAL(CP(McBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ -+ /*Expansion card */\ -+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ -+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ -+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ -+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ -+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ -+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ -+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ -+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ -+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ -+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ -+ /*Wireless LAN */\ -+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\ -+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\ -+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\ -+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\ -+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\ -+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\ -+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\ -+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\ -+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\ -+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ -+ /*Bluetooth*/\ -+ MUX_VAL(CP(McBSP3_DX), (IDIS | PTD | DIS | M4)) /*GPIO_140*/\ -+ MUX_VAL(CP(McBSP3_DR), (IDIS | PTD | DIS | M4)) /*GPIO_142*/\ -+ MUX_VAL(CP(McBSP3_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_141*/\ -+ MUX_VAL(CP(McBSP3_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_143*/\ -+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\ -+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ -+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\ -+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /*UART2_RX*/\ -+ /*Modem Interface */\ -+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ -+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/\ -+ MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/\ -+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ -+ MUX_VAL(CP(McBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX */\ -+ MUX_VAL(CP(McBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX */\ -+ MUX_VAL(CP(McBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX */\ -+ MUX_VAL(CP(McBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\ -+ MUX_VAL(CP(McBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\ -+ MUX_VAL(CP(McBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157 - BT_WAKEUP*/\ -+ MUX_VAL(CP(McBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\ -+ MUX_VAL(CP(McBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\ -+ MUX_VAL(CP(McBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS */\ -+ MUX_VAL(CP(McBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\ -+ MUX_VAL(CP(McBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162 */\ -+ /*Serial Interface*/\ -+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\ -+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ -+ MUX_VAL(CP(UART3_RX_IRRX ), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ -+ MUX_VAL(CP(UART3_TX_IRTX ), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ -+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ -+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ -+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ -+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ -+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0 */\ -+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1 */\ -+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2 */\ -+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3 */\ -+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4 */\ -+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5 */\ -+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6 */\ -+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7 */\ -+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ -+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ -+ MUX_VAL(CP(I2C2_SCL), (IDIS | PTU | DIS | M4)) /*GPIO_168*/\ -+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\ -+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ -+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ -+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ -+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ -+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\ -+ MUX_VAL(CP(McSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\ -+ MUX_VAL(CP(McSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\ -+ MUX_VAL(CP(McSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\ -+ MUX_VAL(CP(McSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ -+ MUX_VAL(CP(McSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\ -+ MUX_VAL(CP(McSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176 - NOR_DPD*/\ -+ MUX_VAL(CP(McSPI1_CS3), (IEN | PTD | EN | M0)) /*McSPI1_CS3*/\ -+ MUX_VAL(CP(McSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\ -+ MUX_VAL(CP(McSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\ -+ MUX_VAL(CP(McSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\ -+ MUX_VAL(CP(McSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\ -+ MUX_VAL(CP(McSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\ -+ /*Control and debug */\ -+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ -+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ -+ MUX_VAL(CP(SYS_nIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ -+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 - PEN_IRQ */\ -+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ -+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP */\ -+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 - LCD_ENVDD*/\ -+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 - LAN_INTR0*/\ -+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 - MMC2_WP*/\ -+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8 - LCD_ENBKL*/\ -+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE */\ -+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1 */\ -+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ -+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\ -+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB1_CLK*/\ -+ MUX_VAL(CP(ETK_D0_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA0*/\ -+ MUX_VAL(CP(ETK_D1_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA1*/\ -+ MUX_VAL(CP(ETK_D2_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA2*/\ -+ MUX_VAL(CP(ETK_D3_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA7*/\ -+ MUX_VAL(CP(ETK_D4_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA4*/\ -+ MUX_VAL(CP(ETK_D5_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA5*/\ -+ MUX_VAL(CP(ETK_D6_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA6*/\ -+ MUX_VAL(CP(ETK_D7_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA3*/\ -+ MUX_VAL(CP(ETK_D8_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DIR*/\ -+ MUX_VAL(CP(ETK_D9_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_NXT*/\ -+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | EN | M4)) /*GPIO_24*/\ -+ MUX_VAL(CP(ETK_D15), (IEN | PTU | EN | M4)) /*GPIO_29*/\ -+ MUX_VAL(CP(d2d_mcad1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ -+ MUX_VAL(CP(d2d_mcad2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ -+ MUX_VAL(CP(d2d_mcad3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ -+ MUX_VAL(CP(d2d_mcad4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ -+ MUX_VAL(CP(d2d_mcad5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ -+ MUX_VAL(CP(d2d_mcad6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ -+ MUX_VAL(CP(d2d_mcad7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ -+ MUX_VAL(CP(d2d_mcad8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ -+ MUX_VAL(CP(d2d_mcad9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ -+ MUX_VAL(CP(d2d_mcad10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ -+ MUX_VAL(CP(d2d_mcad11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ -+ MUX_VAL(CP(d2d_mcad12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ -+ MUX_VAL(CP(d2d_mcad13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ -+ MUX_VAL(CP(d2d_mcad14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ -+ MUX_VAL(CP(d2d_mcad15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ -+ MUX_VAL(CP(d2d_mcad16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ -+ MUX_VAL(CP(d2d_mcad17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ -+ MUX_VAL(CP(d2d_mcad18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ -+ MUX_VAL(CP(d2d_mcad19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ -+ MUX_VAL(CP(d2d_mcad20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ -+ MUX_VAL(CP(d2d_mcad21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ -+ MUX_VAL(CP(d2d_mcad22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ -+ MUX_VAL(CP(d2d_mcad23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ -+ MUX_VAL(CP(d2d_mcad24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ -+ MUX_VAL(CP(d2d_mcad25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ -+ MUX_VAL(CP(d2d_mcad26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ -+ MUX_VAL(CP(d2d_mcad27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ -+ MUX_VAL(CP(d2d_mcad28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ -+ MUX_VAL(CP(d2d_mcad29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ -+ MUX_VAL(CP(d2d_mcad30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ -+ MUX_VAL(CP(d2d_mcad31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ -+ MUX_VAL(CP(d2d_mcad32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ -+ MUX_VAL(CP(d2d_mcad33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ -+ MUX_VAL(CP(d2d_mcad34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ -+ MUX_VAL(CP(d2d_mcad35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ -+ MUX_VAL(CP(d2d_mcad36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ -+ MUX_VAL(CP(d2d_clk26mi), (IEN | PTD | DIS | M0)) /*d2d_clk26mi */\ -+ MUX_VAL(CP(d2d_nrespwron ), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ -+ MUX_VAL(CP(d2d_nreswarm), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ -+ MUX_VAL(CP(d2d_arm9nirq), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ -+ MUX_VAL(CP(d2d_uma2p6fiq ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ -+ MUX_VAL(CP(d2d_spint), (IEN | PTD | EN | M0)) /*d2d_spint*/\ -+ MUX_VAL(CP(d2d_frint), (IEN | PTD | EN | M0)) /*d2d_frint*/\ -+ MUX_VAL(CP(d2d_dmareq0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0 */\ -+ MUX_VAL(CP(d2d_dmareq1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1 */\ -+ MUX_VAL(CP(d2d_dmareq2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2 */\ -+ MUX_VAL(CP(d2d_dmareq3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3 */\ -+ MUX_VAL(CP(d2d_n3gtrst), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst */\ -+ MUX_VAL(CP(d2d_n3gtdi), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ -+ MUX_VAL(CP(d2d_n3gtdo), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ -+ MUX_VAL(CP(d2d_n3gtms), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ -+ MUX_VAL(CP(d2d_n3gtck), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ -+ MUX_VAL(CP(d2d_n3grtck), (IEN | PTD | DIS | M0)) /*d2d_n3grtck */\ -+ MUX_VAL(CP(d2d_mstdby), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ -+ MUX_VAL(CP(d2d_swakeup), (IEN | PTD | EN | M0)) /*d2d_swakeup */\ -+ MUX_VAL(CP(d2d_idlereq), (IEN | PTD | DIS | M0)) /*d2d_idlereq */\ -+ MUX_VAL(CP(d2d_idleack), (IEN | PTU | EN | M0)) /*d2d_idleack */\ -+ MUX_VAL(CP(d2d_mwrite), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ -+ MUX_VAL(CP(d2d_swrite), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ -+ MUX_VAL(CP(d2d_mread), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ -+ MUX_VAL(CP(d2d_sread), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ -+ MUX_VAL(CP(d2d_mbusflag), (IEN | PTD | DIS | M0)) /*d2d_mbusflag */\ -+ MUX_VAL(CP(d2d_sbusflag), (IEN | PTD | DIS | M0)) /*d2d_sbusflag */\ -+ MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\ -+ MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used */ -+ -+/********************************************************** -+ * Routine: set_muxconf_regs -+ * Description: Setting up the configuration Mux registers -+ * specific to the hardware. Many pins need -+ * to be moved from protect to primary mode. -+ *********************************************************/ -+void set_muxconf_regs(void) -+{ -+ MUX_DEFAULT_ES2(); -+} -+ -+/****************************************************************************** -+ * Routine: update_mux() -+ * Description:Update balls which are different between boards. All should be -+ * updated to match functionality. However, I'm only updating ones -+ * which I'll be using for now. When power comes into play they -+ * all need updating. -+ *****************************************************************************/ -+void update_mux(u32 btype, u32 mtype) -+{ -+ /* NOTHING as of now... */ -+} -+ -+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) -+/********************************************************** -+ * Routine: nand+_init -+ * Description: Set up nand for nand and jffs2 commands -+ *********************************************************/ -+void nand_init(void) -+{ -+ extern flash_info_t flash_info[]; -+ -+ nand_probe(CFG_NAND_ADDR); -+ if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { -+ print_size(nand_dev_desc[0].totlen, "\n"); -+ } -+#ifdef CFG_JFFS2_MEM_NAND -+ flash_info[CFG_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id; -+ /* only read kernel single meg partition */ -+ flash_info[CFG_JFFS2_FIRST_BANK].size = 1024 * 1024 * 2; -+ /* 1024 blocks in 16meg chip (use less for raw/copied partition) */ -+ flash_info[CFG_JFFS2_FIRST_BANK].sector_count = 1024; -+ /* ?, ram for now, open question, copy to RAM or adapt for NAND */ -+ flash_info[CFG_JFFS2_FIRST_BANK].start[0] = 0x80200000; -+#endif -+} -+#endif -diff --git a/board/omap3530beagle/sys_info.c b/board/omap3530beagle/sys_info.c -new file mode 100644 -index 0000000..017bfaa ---- /dev/null -+++ b/board/omap3530beagle/sys_info.c -@@ -0,0 +1,315 @@ -+/* -+ * (C) Copyright 2008 -+ * Texas Instruments, -+ * -+ * Derived from Beagle Board and 3430 SDP code by -+ * Richard Woodruff -+ * Syed Mohammed Khasim -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA ++ * (C) Copyright 2008 ++ * Texas Instruments, ++ * ++ * Derived from Beagle Board and 3430 SDP code by ++ * Richard Woodruff ++ * Syed Mohammed Khasim ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA + */ + +#include -+#include +#include +#include +#include /* get mem tables */ +#include -+#include +#include + +/************************************************************************** -+ * get_cpu_type() - Read the FPGA Debug registers and provide the DIP switch -+ * settings -+ * 1 is on -+ * 0 is off -+ * Will return Index of type of gpmc ++ * get_gpmc0_type() + ***************************************************************************/ +u32 get_gpmc0_type(void) +{ -+ // Default NAND ++ /* Default NAND */ + return (2); +} + @@ -2315,7 +1911,7 @@ index 0000000..017bfaa + ****************************************************/ +u32 get_cpu_type(void) +{ -+ // fixme, need to get register defines for OMAP3 ++ /* fixme, need to get register defines for OMAP3 */ + return (CPU_3430); +} + @@ -2580,10 +2176,10 @@ index 0000000..017bfaa +} diff --git a/board/omap3530beagle/syslib.c b/board/omap3530beagle/syslib.c new file mode 100644 -index 0000000..1eb5d95 +index 0000000..002c6e8 --- /dev/null +++ b/board/omap3530beagle/syslib.c -@@ -0,0 +1,74 @@ +@@ -0,0 +1,72 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, @@ -2608,13 +2204,11 @@ index 0000000..1eb5d95 + */ + +#include -+#include +#include +#include +#include +#include +#include -+#include + +/************************************************************ + * sdelay() - simple spin loop. Will be constant time as @@ -2727,6 +2321,19 @@ index 0000000..72f15f6 + .bss : { *(.bss) } + _end = .; +} +diff --git a/common/env_nand.c b/common/env_nand.c +index a48e98e..8b04a01 100644 +--- a/common/env_nand.c ++++ b/common/env_nand.c +@@ -231,6 +231,8 @@ int saveenv(void) + size_t total; + int ret = 0; + ++ nand_erase_options_t nand_erase_options; ++ + nand_erase_options.length = CFG_ENV_RANGE; + nand_erase_options.quiet = 0; + nand_erase_options.jffs2 = 0; diff --git a/cpu/omap3/Makefile b/cpu/omap3/Makefile new file mode 100644 index 0000000..097447a @@ -2818,10 +2425,10 @@ index 0000000..7551677 +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/omap3/cpu.c b/cpu/omap3/cpu.c new file mode 100644 -index 0000000..d32a8cb +index 0000000..59e6a58 --- /dev/null +++ b/cpu/omap3/cpu.c -@@ -0,0 +1,235 @@ +@@ -0,0 +1,221 @@ +/* + * (C) Copyright 2008 Texas Insturments + * @@ -2858,10 +2465,6 @@ index 0000000..d32a8cb +#include +#include +#include -+#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) -+#include -+#endif -+#include + +#ifdef CONFIG_USE_IRQ +DECLARE_GLOBAL_DATA_PTR; @@ -2876,7 +2479,8 @@ index 0000000..d32a8cb +{ + unsigned long value; + -+ __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0 @ read control reg\n":"=r"(value) ++ __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0\ ++ @ read control reg\n":"=r"(value) + ::"memory"); + return value; +} @@ -2884,10 +2488,9 @@ index 0000000..d32a8cb +/* write to co-processor 15, register #1 (control register) */ +static void write_p15_c1(unsigned long value) +{ -+ __asm__ -+ __volatile__ -+ ("mcr p15, 0, %0, c1, c0, 0 @ write it back\n"::"r"(value) -+ : "memory"); ++ __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0\ ++ @ write it back\n"::"r"(value) ++ : "memory"); + + read_p15_c1(); +} @@ -2927,6 +2530,8 @@ index 0000000..d32a8cb + +int cleanup_before_linux(void) +{ ++ unsigned int i; ++ + /* + * this function is called just before we call linux + * it prepares the processor for linux @@ -2935,49 +2540,37 @@ index 0000000..d32a8cb + */ + disable_interrupts(); + -+#ifdef CONFIG_LCD -+ { -+ extern void lcd_disable(void); -+ extern void lcd_panel_disable(void); -+ -+ lcd_disable(); /* proper disable of lcd & panel */ -+ lcd_panel_disable(); -+ } -+#endif -+ -+ { -+ unsigned int i; -+ -+ /* turn off I/D-cache */ -+ asm("mrc p15, 0, %0, c1, c0, 0":"=r"(i)); -+ i &= ~(C1_DC | C1_IC); -+ asm("mcr p15, 0, %0, c1, c0, 0": :"r"(i)); ++ /* turn off I/D-cache */ ++ asm("mrc p15, 0, %0, c1, c0, 0":"=r"(i)); ++ i &= ~(C1_DC | C1_IC); ++ asm("mcr p15, 0, %0, c1, c0, 0": :"r"(i)); + -+ /* invalidate I-cache */ -+ arm_cache_flush(); ++ /* invalidate I-cache */ ++ arm_cache_flush(); +#ifndef CONFIG_L2_OFF -+ /* turn off L2 cache */ -+ l2cache_disable(); -+ /* invalidate L2 cache also */ -+ v7_flush_dcache_all(get_device_type()); ++ /* turn off L2 cache */ ++ l2cache_disable(); ++ /* invalidate L2 cache also */ ++ v7_flush_dcache_all(get_device_type()); +#endif -+ i = 0; -+ /* mem barrier to sync up things */ -+ asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i)); ++ i = 0; ++ /* mem barrier to sync up things */ ++ asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i)); + +#ifndef CONFIG_L2_OFF + l2cache_enable(); +#endif -+ } + + return (0); +} + -+int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) ++int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + disable_interrupts(); + reset_cpu(0); -+ /*NOTREACHED*/ return (0); ++ ++ /* NOTREACHED */ ++ return (0); +} + +void icache_enable(void) @@ -3059,10 +2652,10 @@ index 0000000..d32a8cb +} diff --git a/cpu/omap3/interrupts.c b/cpu/omap3/interrupts.c new file mode 100644 -index 0000000..007193a +index 0000000..818b833 --- /dev/null +++ b/cpu/omap3/interrupts.c -@@ -0,0 +1,299 @@ +@@ -0,0 +1,304 @@ +/* + * (C) Copyright 2008 + * Texas Instruments @@ -3100,10 +2693,6 @@ index 0000000..007193a +#include +#include + -+#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) -+# include -+#endif -+ +#include + +#define TIMER_LOAD_VAL 0 @@ -3237,9 +2826,6 @@ index 0000000..007193a + bad_mode(); +} + -+#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR) -+/* Use the IntegratorCP function from board/integratorcp.c */ -+#else + +static ulong timestamp; +static ulong lastinc; @@ -3250,8 +2836,10 @@ index 0000000..007193a + int32_t val; + + /* Start the counter ticking up */ -+ *((int32_t *) (CFG_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow */ -+ val = (CFG_PVT << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer */ ++ /* reload value on overflow */ ++ *((int32_t *) (CFG_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; ++ /* mask to enable timer */ ++ val = (CFG_PVT << 2) | BIT5 | BIT1 | BIT0; + *((int32_t *) (CFG_TIMERBASE + TCLR)) = val; /* start timer */ + + reset_timer_masked(); /* init the timestamp and lastinc value */ @@ -3282,18 +2870,23 @@ index 0000000..007193a +{ + ulong tmo, tmp; + -+ if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ -+ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ -+ tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ ++ /* if "big" number, spread normalization to seconds */ ++ if (usec >= 1000) { ++ /* if "big" number, spread normalization to seconds */ ++ tmo = usec / 1000; ++ /* find number of "ticks" to wait to achieve target */ ++ tmo *= CFG_HZ; + tmo /= 1000; /* finish normalize. */ -+ } else { /* else small number, don't kill it prior to HZ multiply */ ++ } else {/* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000 * 1000); + } + + tmp = get_timer(0); /* get current timestamp */ -+ if ((tmo + tmp + 1) < tmp) /* if setting this forward will roll time stamp */ -+ reset_timer_masked(); /* reset "advancing" timestamp to 0, set lastinc value */ ++ /* if setting this forward will roll time stamp */ ++ if ((tmo + tmp + 1) < tmp) ++ /* reset "advancing" timestamp to 0, set lastinc value */ ++ reset_timer_masked(); + else + tmo += tmp; /* else, set advancing stamp wake up time */ + while (get_timer_masked() < tmo) /* loop till event */ @@ -3312,8 +2905,9 @@ index 0000000..007193a + ulong now = READ_TIMER; /* current tick value */ + + if (now >= lastinc) /* normal mode (non roll) */ -+ timestamp += (now - lastinc); /* move stamp fordward with absoulte diff ticks */ -+ else /* we have rollover of incrementer */ ++ /* move stamp fordward with absoulte diff ticks */ ++ timestamp += (now - lastinc); ++ else /* we have rollover of incrementer */ + timestamp += (0xFFFFFFFF - lastinc) + now; + lastinc = now; + return timestamp; @@ -3326,11 +2920,15 @@ index 0000000..007193a + ulong endtime; + signed long diff; + -+ if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ -+ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ -+ tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ ++ /* if "big" number, spread normalization to seconds */ ++ if (usec >= 1000) { ++ /* start to normalize for usec to ticks per sec */ ++ tmo = usec / 1000; ++ /* find number of "ticks" to wait to achieve target */ ++ tmo *= CFG_HZ; + tmo /= 1000; /* finish normalize. */ -+ } else { /* else small number, don't kill it prior to HZ multiply */ ++ } else { /* else small number, */ ++ /* don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000 * 1000); + } @@ -3361,13 +2959,13 @@ index 0000000..007193a + tbclk = CFG_HZ; + return tbclk; +} -+#endif /* !Integrator/CP */ ++ diff --git a/cpu/omap3/mmc.c b/cpu/omap3/mmc.c new file mode 100644 -index 0000000..ff6a50d +index 0000000..741360b --- /dev/null +++ b/cpu/omap3/mmc.c -@@ -0,0 +1,551 @@ +@@ -0,0 +1,559 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, @@ -3394,20 +2992,35 @@ index 0000000..ff6a50d + +#include +#include ++#include +#include +#include +#include -+#include "mmc_host_def.h" -+#include "mmc_protocol.h" + -+extern int fat_register_device(block_dev_desc_t * dev_desc, int part_no); ++const unsigned short mmc_transspeed_val[15][4] = { ++ {CLKD(10, 1), CLKD(10, 10), CLKD(10, 100), CLKD(10, 1000)}, ++ {CLKD(12, 1), CLKD(12, 10), CLKD(12, 100), CLKD(12, 1000)}, ++ {CLKD(13, 1), CLKD(13, 10), CLKD(13, 100), CLKD(13, 1000)}, ++ {CLKD(15, 1), CLKD(15, 10), CLKD(15, 100), CLKD(15, 1000)}, ++ {CLKD(20, 1), CLKD(20, 10), CLKD(20, 100), CLKD(20, 1000)}, ++ {CLKD(26, 1), CLKD(26, 10), CLKD(26, 100), CLKD(26, 1000)}, ++ {CLKD(30, 1), CLKD(30, 10), CLKD(30, 100), CLKD(30, 1000)}, ++ {CLKD(35, 1), CLKD(35, 10), CLKD(35, 100), CLKD(35, 1000)}, ++ {CLKD(40, 1), CLKD(40, 10), CLKD(40, 100), CLKD(40, 1000)}, ++ {CLKD(45, 1), CLKD(45, 10), CLKD(45, 100), CLKD(45, 1000)}, ++ {CLKD(52, 1), CLKD(52, 10), CLKD(52, 100), CLKD(52, 1000)}, ++ {CLKD(55, 1), CLKD(55, 10), CLKD(55, 100), CLKD(55, 1000)}, ++ {CLKD(60, 1), CLKD(60, 10), CLKD(60, 100), CLKD(60, 1000)}, ++ {CLKD(70, 1), CLKD(70, 10), CLKD(70, 100), CLKD(70, 1000)}, ++ {CLKD(80, 1), CLKD(80, 10), CLKD(80, 100), CLKD(80, 1000)} ++}; + +mmc_card_data cur_card_data; +static block_dev_desc_t mmc_blk_dev; + +block_dev_desc_t *mmc_get_dev(int dev) +{ -+ return ((block_dev_desc_t *) & mmc_blk_dev); ++ return ((block_dev_desc_t *) &mmc_blk_dev); +} + +void twl4030_mmc_config(void) @@ -3438,7 +3051,7 @@ index 0000000..ff6a50d +void mmc_init_stream(void) +{ + volatile unsigned int mmc_stat; -+ ++ + OMAP_HSMMC_CON |= INIT_INITSTREAM; + + OMAP_HSMMC_CMD = MMC_CMD0; @@ -3537,9 +3150,8 @@ index 0000000..ff6a50d + mmc_stat = OMAP_HSMMC_STAT; + } while (mmc_stat == 0); + -+ if ((mmc_stat & ERRI_MASK) != 0) { ++ if ((mmc_stat & ERRI_MASK) != 0) + return (unsigned char) mmc_stat; -+ } + + if (mmc_stat & CC_MASK) { + OMAP_HSMMC_STAT = CC_MASK; @@ -3593,7 +3205,7 @@ index 0000000..ff6a50d + return 1; +} + -+unsigned char mmc_detect_card(mmc_card_data * mmc_card_cur) ++unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur) +{ + unsigned char err; + unsigned int argument = 0; @@ -3636,9 +3248,9 @@ index 0000000..ff6a50d + + argument = ocr_value; + err = mmc_send_cmd(ret_cmd41, argument, resp); -+ if (err != 1) { ++ if (err != 1) + return err; -+ } ++ + ocr_recvd = ((mmc_resp_r3 *) resp)->ocr; + + while (!(ocr_recvd & (0x1 << 31)) && (retry_cnt > 0)) { @@ -3704,8 +3316,8 @@ index 0000000..ff6a50d + return 1; +} + -+unsigned char mmc_read_cardsize(mmc_card_data * mmc_dev_data, -+ mmc_csd_reg_t * cur_csd) ++unsigned char mmc_read_cardsize(mmc_card_data *mmc_dev_data, ++ mmc_csd_reg_t *cur_csd) +{ + mmc_extended_csd_reg_t ext_csd; + unsigned int size, count, blk_len, blk_no, card_size, argument; @@ -3759,7 +3371,7 @@ index 0000000..ff6a50d +} + +unsigned char omap_mmc_read_sect(unsigned int start_sec, unsigned int num_bytes, -+ mmc_card_data * mmc_c, ++ mmc_card_data *mmc_c, + unsigned long *output_buf) +{ + unsigned char err; @@ -3782,14 +3394,13 @@ index 0000000..ff6a50d + + while (num_sec_val) { + err = mmc_send_cmd(MMC_CMD17, argument, resp); -+ if (err != 1) { ++ if (err != 1) + return err; -+ } + + err = mmc_read_data((unsigned int *) output_buf); -+ if (err != 1) { ++ if (err != 1) + return err; -+ } ++ + output_buf += (MMCSD_SECTOR_SIZE / 4); + argument += sec_inc_val; + num_sec_val--; @@ -3797,7 +3408,7 @@ index 0000000..ff6a50d + return 1; +} + -+unsigned char configure_mmc(mmc_card_data * mmc_card_cur) ++unsigned char configure_mmc(mmc_card_data *mmc_card_cur) +{ + unsigned char ret_val; + unsigned int argument; @@ -3808,9 +3419,8 @@ index 0000000..ff6a50d + + ret_val = mmc_init_setup(); + -+ if (ret_val != 1) { ++ if (ret_val != 1) + return ret_val; -+ } + + do { + ret_val = mmc_detect_card(mmc_card_cur); @@ -3827,9 +3437,8 @@ index 0000000..ff6a50d + ((unsigned int *) &Card_CSD)[1] = resp[1]; + ((unsigned int *) &Card_CSD)[0] = resp[0]; + -+ if (mmc_card_cur->card_type == MMC_CARD) { ++ if (mmc_card_cur->card_type == MMC_CARD) + mmc_card_cur->version = Card_CSD.spec_vers; -+ } + + trans_speed = Card_CSD.tran_speed; + @@ -3902,45 +3511,49 @@ index 0000000..ff6a50d + return 0; +} + -+int mmc_read(ulong src, uchar * dst, int size) ++int mmc_read(ulong src, uchar *dst, int size) +{ -+ /* not implemented */ -+ return (0); ++ return 0; +} + -+int mmc_write(uchar * src, ulong dst, int size) ++int mmc_write(uchar *src, ulong dst, int size) +{ -+ /* not implementd */ -+ return (0); ++ return 0; +} + +int mmc2info(ulong addr) +{ -+ /*not implemented */ -+ return (0); ++ return 0; +} -diff --git a/cpu/omap3/mmc_host_def.h b/cpu/omap3/mmc_host_def.h +diff --git a/cpu/omap3/start.S b/cpu/omap3/start.S new file mode 100644 -index 0000000..3a84f16 +index 0000000..98706ad --- /dev/null -+++ b/cpu/omap3/mmc_host_def.h -@@ -0,0 +1,164 @@ ++++ b/cpu/omap3/start.S +@@ -0,0 +1,517 @@ +/* -+ * (C) Copyright 2008 -+ * Texas Instruments, -+ * Syed Mohammed Khasim ++ * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core ++ * ++ * Copyright (c) 2004 Texas Instruments ++ * ++ * Copyright (c) 2001 Marius Gröger ++ * Copyright (c) 2002 Alex Züpke ++ * Copyright (c) 2002 Gary Jennejohn ++ * Copyright (c) 2003 Richard Woodruff ++ * Copyright (c) 2003 Kshitij ++ * Copyright (c) 2006-2008 Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation's version 2 of -+ * the License. ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License @@ -3949,635 +3562,195 @@ index 0000000..3a84f16 + * MA 02111-1307 USA + */ + -+#ifndef MMC_HOST_DEFINITIONS_H -+#define MMC_HOST_DEFINITIONS_H ++#include ++#include + -+/* -+ * OMAP HSMMC register definitions -+ */ -+#define OMAP_HSMMC_SYSCONFIG (*(unsigned int *) 0x4809C010) -+#define OMAP_HSMMC_SYSSTATUS (*(unsigned int *) 0x4809C014) -+#define OMAP_HSMMC_CON (*(unsigned int *) 0x4809C02C) -+#define OMAP_HSMMC_BLK (*(unsigned int *) 0x4809C104) -+#define OMAP_HSMMC_ARG (*(unsigned int *) 0x4809C108) -+#define OMAP_HSMMC_CMD (*(unsigned int *) 0x4809C10C) -+#define OMAP_HSMMC_RSP10 (*(unsigned int *) 0x4809C110) -+#define OMAP_HSMMC_RSP32 (*(unsigned int *) 0x4809C114) -+#define OMAP_HSMMC_RSP54 (*(unsigned int *) 0x4809C118) -+#define OMAP_HSMMC_RSP76 (*(unsigned int *) 0x4809C11C) -+#define OMAP_HSMMC_DATA (*(unsigned int *) 0x4809C120) -+#define OMAP_HSMMC_PSTATE (*(unsigned int *) 0x4809C124) -+#define OMAP_HSMMC_HCTL (*(unsigned int *) 0x4809C128) -+#define OMAP_HSMMC_SYSCTL (*(unsigned int *) 0x4809C12C) -+#define OMAP_HSMMC_STAT (*(unsigned int *) 0x4809C130) -+#define OMAP_HSMMC_IE (*(unsigned int *) 0x4809C134) -+#define OMAP_HSMMC_CAPA (*(unsigned int *) 0x4809C140) ++.globl _start ++_start: b reset ++ ldr pc, _undefined_instruction ++ ldr pc, _software_interrupt ++ ldr pc, _prefetch_abort ++ ldr pc, _data_abort ++ ldr pc, _not_used ++ ldr pc, _irq ++ ldr pc, _fiq + -+/* T2 Register definitions */ -+#define CONTROL_DEV_CONF0 (*(unsigned int *) 0x48002274) -+#define CONTROL_PBIAS_LITE (*(unsigned int *) 0x48002520) ++_undefined_instruction: .word undefined_instruction ++_software_interrupt: .word software_interrupt ++_prefetch_abort: .word prefetch_abort ++_data_abort: .word data_abort ++_not_used: .word not_used ++_irq: .word irq ++_fiq: .word fiq ++_pad: .word 0x12345678 /* now 16*4=64 */ ++.global _end_vect ++_end_vect: + -+/* -+ * OMAP HS MMC Bit definitions ++ .balignl 16,0xdeadbeef ++/************************************************************************* ++ * ++ * Startup Code (reset vector) ++ * ++ * do important init only if we don't start from memory! ++ * setup Memory and board specific bits prior to relocation. ++ * relocate armboot to ram ++ * setup stack ++ * ++ *************************************************************************/ ++ ++_TEXT_BASE: ++ .word TEXT_BASE ++ ++.globl _armboot_start ++_armboot_start: ++ .word _start ++ ++/* ++ * These are defined in the board-specific linker script. + */ -+#define MMC_SOFTRESET (0x1 << 1) -+#define RESETDONE (0x1 << 0) -+#define NOOPENDRAIN (0x0 << 0) -+#define OPENDRAIN (0x1 << 0) -+#define OD (0x1 << 0) -+#define INIT_NOINIT (0x0 << 1) -+#define INIT_INITSTREAM (0x1 << 1) -+#define HR_NOHOSTRESP (0x0 << 2) -+#define STR_BLOCK (0x0 << 3) -+#define MODE_FUNC (0x0 << 4) -+#define DW8_1_4BITMODE (0x0 << 5) -+#define MIT_CTO (0x0 << 6) -+#define CDP_ACTIVEHIGH (0x0 << 7) -+#define WPP_ACTIVEHIGH (0x0 << 8) -+#define RESERVED_MASK (0x3 << 9) -+#define CTPL_MMC_SD (0x0 << 11) -+#define BLEN_512BYTESLEN (0x200 << 0) -+#define NBLK_STPCNT (0x0 << 16) -+#define DE_DISABLE (0x0 << 0) -+#define BCE_DISABLE (0x0 << 1) -+#define ACEN_DISABLE (0x0 << 2) -+#define DDIR_OFFSET (4) -+#define DDIR_MASK (0x1 << 4) -+#define DDIR_WRITE (0x0 << 4) -+#define DDIR_READ (0x1 << 4) -+#define MSBS_SGLEBLK (0x0 << 5) -+#define RSP_TYPE_OFFSET (16) -+#define RSP_TYPE_MASK (0x3 << 16) -+#define RSP_TYPE_NORSP (0x0 << 16) -+#define RSP_TYPE_LGHT136 (0x1 << 16) -+#define RSP_TYPE_LGHT48 (0x2 << 16) -+#define RSP_TYPE_LGHT48B (0x3 << 16) -+#define CCCE_NOCHECK (0x0 << 19) -+#define CCCE_CHECK (0x1 << 19) -+#define CICE_NOCHECK (0x0 << 20) -+#define CICE_CHECK (0x1 << 20) -+#define DP_OFFSET (21) -+#define DP_MASK (0x1 << 21) -+#define DP_NO_DATA (0x0 << 21) -+#define DP_DATA (0x1 << 21) -+#define CMD_TYPE_NORMAL (0x0 << 22) -+#define INDEX_OFFSET (24) -+#define INDEX_MASK (0x3f << 24) -+#define INDEX(i) (i << 24) -+#define DATI_MASK (0x1 << 1) -+#define DATI_CMDDIS (0x1 << 1) -+#define DTW_1_BITMODE (0x0 << 1) -+#define DTW_4_BITMODE (0x1 << 1) -+#define SDBP_PWROFF (0x0 << 8) -+#define SDBP_PWRON (0x1 << 8) -+#define SDVS_1V8 (0x5 << 9) -+#define SDVS_3V0 (0x6 << 9) -+#define ICE_MASK (0x1 << 0) -+#define ICE_STOP (0x0 << 0) -+#define ICS_MASK (0