From be3e650d031916b132b4cef9d19e7844cca3440b Mon Sep 17 00:00:00 2001 From: Michael Lauer Date: Fri, 28 Dec 2007 13:10:28 +0000 Subject: rename uboot directory for more consistency --- packages/u-boot/.mtn2git_empty | 0 packages/u-boot/files/.mtn2git_empty | 0 packages/u-boot/files/arm_flags.patch | 13 + .../boot-menu-gfx-fix-openmoko-bug-1140.patch | 29 + packages/u-boot/files/fix-arm920t-eabi.patch | 9 + packages/u-boot/files/makefile-no-dirafter.patch | 17 + .../files/u-boot-20061030-ext2load_hex.patch | 14 + .../uboot-20070311-tools_makefile_ln_sf.patch | 19 + packages/u-boot/files/uboot-eabi-fix-HACK.patch | 197 + packages/u-boot/u-boot-1.1.2/.mtn2git_empty | 0 packages/u-boot/u-boot-1.1.2/arm_flags.patch | 15 + packages/u-boot/u-boot-1.1.2/cmd-arm-linux.patch | 122 + packages/u-boot/u-boot-1.1.2/command-names.patch | 340 + packages/u-boot/u-boot-1.1.2/mnci-jffs2.patch | 16 + packages/u-boot/u-boot-1.1.2/mnci.patch | 1007 + .../u-boot/u-boot-1.1.2/u-boot-1.1.2-neon.patch | 19204 +++++++++++ packages/u-boot/u-boot-1.1.2/u-boot-emetec.patch | 2170 ++ packages/u-boot/u-boot-1.1.4/.mtn2git_empty | 0 .../u-boot/u-boot-1.1.4/u-boot-autoscript.patch | 12 + packages/u-boot/u-boot-1.1.4/u-boot-base.patch | 913 + .../u-boot-crc-warning-not-so-scary.patch | 11 + .../u-boot-1.1.4/u-boot-dht-walnut-df2.patch | 186 + .../u-boot-1.1.4/u-boot-flash-protect-fixup.patch | 11 + .../u-boot/u-boot-1.1.4/u-boot-fw_printenv.patch | 139 + packages/u-boot/u-boot-1.1.4/u-boot-install.patch | 102 + .../u-boot/u-boot-1.1.4/u-boot-jerase-cmd.patch | 107 + .../u-boot-1.1.4/u-boot-jffs2-new-nodetypes.patch | 25 + .../u-boot/u-boot-1.1.4/u-boot-loadb-safe.patch | 16 + .../u-boot/u-boot-1.1.4/u-boot-make381-fix.patch | 15 + packages/u-boot/u-boot-1.1.4/u-boot-mmc-init.patch | 24 + .../u-boot-1.1.4/u-boot-mmcclk-alternate.patch | 14 + .../u-boot/u-boot-1.1.4/u-boot-smc91x-multi.patch | 125 + packages/u-boot/u-boot-1.1.4/u-boot-zzz-osx.patch | 41 + packages/u-boot/u-boot-1.1.6/.mtn2git_empty | 0 packages/u-boot/u-boot-1.1.6/devkit-idp.patch | 28 + packages/u-boot/u-boot-1.1.6/sarge-uboot.patch | 3326 ++ .../u-boot-1.1.6-83xx-optimizations.patch | 89 + ...l-1-Add-support-for-the-MPC832XEMDS-board.patch | 1809 ++ ....6-fsl-1-Add-the-MPC832XEMDS-board-readme.patch | 131 + ...-fsl-1-Added-MPC8323E-RDB-board-support-2.patch | 1221 + ...-1.1.6-fsl-1-Fix-the-UEC-driver-bug-of-QE.patch | 62 + .../u-boot-1.1.6-fsl-1-UEC-remove-udelay.patch | 15 + .../u-boot-1.1.6-fsl-1-mpc83xx-20061206.patch | 32020 +++++++++++++++++++ ...-fsl-1-streamline-the-83xx-immr-head-file.patch | 3640 +++ packages/u-boot/u-boot-1.2.0/.mtn2git_empty | 0 packages/u-boot/u-boot-1.2.0/defconfig_lsppchd | 500 + packages/u-boot/u-boot-1.2.0/defconfig_lsppchg | 500 + packages/u-boot/u-boot-1.2.0/env-Makefile.patch | 19 + .../u-boot/u-boot-1.2.0/fic-gta01/.mtn2git_empty | 0 .../u-boot/u-boot-1.2.0/fic-gta01/fw_env.config | 6 + packages/u-boot/u-boot-1.2.0/fw_env.c.patch | 13 + packages/u-boot/u-boot-1.2.0/fw_env.config | 7 + .../kurobox_powerpc-20061105_target.gitdiff | 2286 ++ packages/u-boot/u-boot-1.2.0/qnap.diff | 1089 + packages/u-boot/u-boot-1.2.0/tools-Makefile.patch | 19 + .../u-boot-1.2.0/turbostation/.mtn2git_empty | 0 .../u-boot/u-boot-1.2.0/turbostation/fw_env.config | 7 + .../u-boot/u-boot-1.2.0/u-boot-kurobox-fdt.patch | 29 + packages/u-boot/u-boot-1.2.0/u-boot-kurobox.patch | 5595 ++++ packages/u-boot/u-boot-1.2.0/uboot-qnap.diff | 1100 + .../u-boot-mkimage-openmoko-native/.mtn2git_empty | 0 .../bbt-create-optional.patch | 52 + .../bbt-scan-second.patch | 69 + .../boot-from-ram-and-nand.patch | 98 + .../boot-from-ram-reloc.patch | 62 + .../u-boot-mkimage-openmoko-native/boot-menu.patch | 769 + .../u-boot-mkimage-openmoko-native/cmd-unzip.patch | 58 + .../console-ansi.patch | 127 + .../default-env.patch | 101 + .../u-boot-mkimage-openmoko-native/dontask.patch | 22 + .../dynenv-harden.patch | 139 + .../early-powerdown.patch | 40 + .../enable-splash-bmp.patch | 56 + .../env_nand_oob.patch | 198 + .../ext2load_hex.patch | 17 + .../lowlevel_foo.patch | 229 + .../mmcinit-power-up.patch | 73 + .../nand-badisbad.patch | 30 + .../nand-createbbt.patch | 126 + .../nand-dynamic_partitions.patch | 354 + .../u-boot-mkimage-openmoko-native/nand-otp.patch | 302 + .../nand-read_write_oob.patch | 23 + .../neo1973-chargefast.patch | 316 + .../preboot-override.patch | 137 + .../raise-limits.patch | 31 + .../u-boot/u-boot-mkimage-openmoko-native/series | 76 + .../splashimage-command.patch | 24 + .../uboot-20061030-neo1973.patch | 2248 ++ .../uboot-20061030-qt2410.patch | 1233 + .../uboot-arm920_s3c2410_irq_demux.patch | 56 + .../uboot-arm920t-gd_in_irq.patch | 28 + .../uboot-bbt-quiet.patch | 43 + .../uboot-cmd_s3c2410.patch | 175 + .../uboot-cramfs_but_no_jffs2.patch | 41 + .../u-boot-mkimage-openmoko-native/uboot-dfu.patch | 2081 ++ .../uboot-gta02.patch | 1560 + .../uboot-hxd8.patch | 1169 + .../uboot-license.patch | 712 + .../uboot-machtypes.patch | 4121 +++ .../uboot-mokoversion.patch | 10 + .../uboot-nand-markbad-reallybad.patch | 20 + .../uboot-neo1973-defaultenv.patch | 31 + .../uboot-neo1973-resume.patch | 113 + .../uboot-s3c2410-misccr-definitions.patch | 45 + .../uboot-s3c2410-mmc.patch | 818 + .../uboot-s3c2410-nand.patch | 525 + .../uboot-s3c2410-norelocate_irqvec_cpy.patch | 32 + .../uboot-s3c2410-warnings-fix.patch | 98 + .../uboot-s3c2410_fb.patch | 215 + .../uboot-s3c2410_udc.patch | 1263 + .../uboot-s3c2440.patch | 1301 + .../uboot-s3c2443.patch | 256 + .../uboot-smdk2440.patch | 1481 + .../uboot-smdk2443.patch | 1411 + .../uboot-strtoul.patch | 43 + .../uboot-usbtty-acm.patch | 1607 + .../unbusy-i2c.patch | 88 + .../usbdcore-multiple_configs.patch | 63 + .../wakeup-reason-nand-only.patch | 68 + .../u-boot/u-boot-mkimage-openmoko-native_oe.bb | 86 + .../u-boot/u-boot-omap2430sdp-1.1.4/.mtn2git_empty | 0 .../u-boot-makefile-3.81.patch | 11 + packages/u-boot/u-boot-omap2430sdp_1.1.4.bb | 13 + ...24d4a328e6edd906456da98d2c537155c4f7+svn2943.bb | 86 + packages/u-boot/u-boot-openmoko_svn.bb | 85 + packages/u-boot/u-boot-utils-native_1.2.0.bb | 27 + packages/u-boot/u-boot-utils_1.2.0.bb | 38 + packages/u-boot/u-boot.inc | 33 + packages/u-boot/u-boot_1.1.2.bb | 49 + packages/u-boot/u-boot_1.1.4.bb | 53 + packages/u-boot/u-boot_1.1.6.bb | 25 + packages/u-boot/u-boot_1.2.0.bb | 25 + packages/u-boot/u-boot_1.3.0.bb | 7 + packages/u-boot/u-boot_git.bb | 10 + 134 files changed, 105456 insertions(+) create mode 100644 packages/u-boot/.mtn2git_empty create mode 100644 packages/u-boot/files/.mtn2git_empty create mode 100644 packages/u-boot/files/arm_flags.patch create mode 100644 packages/u-boot/files/boot-menu-gfx-fix-openmoko-bug-1140.patch create mode 100644 packages/u-boot/files/fix-arm920t-eabi.patch create mode 100644 packages/u-boot/files/makefile-no-dirafter.patch create mode 100644 packages/u-boot/files/u-boot-20061030-ext2load_hex.patch create mode 100644 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create mode 100644 packages/u-boot/u-boot-1.1.6/sarge-uboot.patch create mode 100644 packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-83xx-optimizations.patch create mode 100644 packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Add-support-for-the-MPC832XEMDS-board.patch create mode 100644 packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Add-the-MPC832XEMDS-board-readme.patch create mode 100644 packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Added-MPC8323E-RDB-board-support-2.patch create mode 100644 packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Fix-the-UEC-driver-bug-of-QE.patch create mode 100644 packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-UEC-remove-udelay.patch create mode 100644 packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-mpc83xx-20061206.patch create mode 100644 packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-streamline-the-83xx-immr-head-file.patch create mode 100644 packages/u-boot/u-boot-1.2.0/.mtn2git_empty create mode 100644 packages/u-boot/u-boot-1.2.0/defconfig_lsppchd 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100644 packages/u-boot/u-boot_1.1.2.bb create mode 100644 packages/u-boot/u-boot_1.1.4.bb create mode 100644 packages/u-boot/u-boot_1.1.6.bb create mode 100644 packages/u-boot/u-boot_1.2.0.bb create mode 100644 packages/u-boot/u-boot_1.3.0.bb create mode 100644 packages/u-boot/u-boot_git.bb (limited to 'packages/u-boot') diff --git a/packages/u-boot/.mtn2git_empty b/packages/u-boot/.mtn2git_empty new file mode 100644 index 0000000000..e69de29bb2 diff --git a/packages/u-boot/files/.mtn2git_empty b/packages/u-boot/files/.mtn2git_empty new file mode 100644 index 0000000000..e69de29bb2 diff --git a/packages/u-boot/files/arm_flags.patch b/packages/u-boot/files/arm_flags.patch new file mode 100644 index 0000000000..84b8cada39 --- /dev/null +++ b/packages/u-boot/files/arm_flags.patch @@ -0,0 +1,13 @@ +Index: u-boot/cpu/pxa/config.mk +=================================================================== +--- u-boot.orig/cpu/pxa/config.mk 2005-01-09 16:28:17.000000000 -0500 ++++ u-boot/cpu/pxa/config.mk 2005-02-25 16:38:23.789788636 -0500 +@@ -23,7 +23,7 @@ + # + + PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ +- -mshort-load-bytes -msoft-float ++ -msoft-float + + #PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100 + PLATFORM_CPPFLAGS += -mapcs-32 -march=armv5 -mtune=xscale diff --git a/packages/u-boot/files/boot-menu-gfx-fix-openmoko-bug-1140.patch b/packages/u-boot/files/boot-menu-gfx-fix-openmoko-bug-1140.patch new file mode 100644 index 0000000000..c97880a01c --- /dev/null +++ b/packages/u-boot/files/boot-menu-gfx-fix-openmoko-bug-1140.patch @@ -0,0 +1,29 @@ +--- git.orig/drivers/video/cfb_console.c 2007-12-27 00:59:35.000000000 -0800 ++++ git/drivers/video/cfb_console.c 2007-12-27 08:23:42.000000000 -0800 +@@ -141,6 +141,14 @@ + #endif + + /*****************************************************************************/ ++/* Defines for the S3C2410 driver */ ++/*****************************************************************************/ ++#ifdef CONFIG_VIDEO_S3C2410 ++/* it actually is little-endian, but the host CPU, too ! */ ++//#define VIDEO_FB_LITTLE_ENDIAN ++#endif ++ ++/*****************************************************************************/ + /* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc */ + /*****************************************************************************/ + #include +@@ -309,6 +317,11 @@ + #define SHORTSWAP32(x) (x) + #endif + ++#ifdef CONFIG_VIDEO_S3C2410 ++#undef SHORTSWAP32 ++#define SHORTSWAP32(x) ((((x) & 0xffff) << 16) | (((x) >> 16) & 0xffff)) ++#endif ++ + #if defined(DEBUG) || defined(DEBUG_CFB_CONSOLE) + #define PRINTD(x) printf(x) + #else diff --git a/packages/u-boot/files/fix-arm920t-eabi.patch b/packages/u-boot/files/fix-arm920t-eabi.patch new file mode 100644 index 0000000000..9896388c8f --- /dev/null +++ b/packages/u-boot/files/fix-arm920t-eabi.patch @@ -0,0 +1,9 @@ +--- /tmp/config.mk 2007-02-14 17:23:15.000000000 +0100 ++++ git/cpu/arm920t/config.mk 2007-02-14 17:23:38.475251000 +0100 +@@ -30,5 +30,5 @@ + # Supply options according to compiler version + # + # ========================================================================= +-PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) ++PLATFORM_CPPFLAGS +=$(call cc-option) + PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/packages/u-boot/files/makefile-no-dirafter.patch b/packages/u-boot/files/makefile-no-dirafter.patch new file mode 100644 index 0000000000..2ed26c3127 --- /dev/null +++ b/packages/u-boot/files/makefile-no-dirafter.patch @@ -0,0 +1,17 @@ +Index: git/tools/Makefile +=================================================================== +--- git.orig/tools/Makefile 2007-10-03 16:51:38.000000000 +0100 ++++ git/tools/Makefile 2007-10-03 16:52:03.000000000 +0100 +@@ -114,9 +114,9 @@ + # + # Use native tools and options + # +-CPPFLAGS = -idirafter $(SRCTREE)/include \ +- -idirafter $(OBJTREE)/include2 \ +- -idirafter $(OBJTREE)/include \ ++CPPFLAGS = -I$(SRCTREE)/include \ ++ -I$(OBJTREE)/include2 \ ++ -I$(OBJTREE)/include \ + -DTEXT_BASE=$(TEXT_BASE) -DUSE_HOSTCC + CFLAGS = $(HOST_CFLAGS) $(CPPFLAGS) -O + AFLAGS = -D__ASSEMBLY__ $(CPPFLAGS) diff --git a/packages/u-boot/files/u-boot-20061030-ext2load_hex.patch b/packages/u-boot/files/u-boot-20061030-ext2load_hex.patch new file mode 100644 index 0000000000..3cecb7485d --- /dev/null +++ b/packages/u-boot/files/u-boot-20061030-ext2load_hex.patch @@ -0,0 +1,14 @@ +This patch adds the hex-printing of the file size read by 'ext2load' +Index: u-boot.git/common/cmd_ext2.c +=================================================================== +--- u-boot.git.orig/common/cmd_ext2.c 2007-01-02 18:26:17.000000000 +0100 ++++ u-boot.git/common/cmd_ext2.c 2007-01-02 18:26:27.000000000 +0100 +@@ -279,7 +279,7 @@ + /* Loading ok, update default load address */ + load_addr = addr; + +- printf ("\n%ld bytes read\n", filelen); ++ printf ("\n%ld (0x%lx) bytes read\n", filelen, filelen); + sprintf(buf, "%lX", filelen); + setenv("filesize", buf); + diff --git a/packages/u-boot/files/uboot-20070311-tools_makefile_ln_sf.patch b/packages/u-boot/files/uboot-20070311-tools_makefile_ln_sf.patch new file mode 100644 index 0000000000..e90cc0de71 --- /dev/null +++ b/packages/u-boot/files/uboot-20070311-tools_makefile_ln_sf.patch @@ -0,0 +1,19 @@ +--- a/tools/Makefile 2007-03-11 00:55:44.000000000 +0000 ++++ b/tools/Makefile 2007-03-11 00:55:52.000000000 +0000 +@@ -194,14 +194,14 @@ + + $(obj)environment.c: + @rm -f $(obj)environment.c +- ln -s $(src)../common/environment.c $(obj)environment.c ++ ln -sf $(src)../common/environment.c $(obj)environment.c + + $(obj)environment.o: $(obj)environment.c + $(CC) -g $(HOST_ENVIRO_CFLAGS) $(CPPFLAGS) -c -o $@ $< + + $(obj)crc32.c: + @rm -f $(obj)crc32.c +- ln -s $(src)../lib_generic/crc32.c $(obj)crc32.c ++ ln -sf $(src)../lib_generic/crc32.c $(obj)crc32.c + + $(LOGO_H): $(obj)bmp_logo $(LOGO_BMP) + $(obj)./bmp_logo $(LOGO_BMP) >$@ diff --git a/packages/u-boot/files/uboot-eabi-fix-HACK.patch b/packages/u-boot/files/uboot-eabi-fix-HACK.patch new file mode 100644 index 0000000000..65b212917d --- /dev/null +++ b/packages/u-boot/files/uboot-eabi-fix-HACK.patch @@ -0,0 +1,197 @@ +Index: git/lib_arm/div0.c +=================================================================== +--- git.orig/lib_arm/div0.c ++++ git/lib_arm/div0.c +@@ -22,9 +22,3 @@ + */ + + /* Replacement (=dummy) for GNU/Linux division-by zero handler */ +-void __div0 (void) +-{ +- extern void hang (void); +- +- hang(); +-} +Index: git/board/neo1973/common/bootmenu.c +=================================================================== +--- git.orig/board/neo1973/common/bootmenu.c ++++ git/board/neo1973/common/bootmenu.c +@@ -118,3 +118,14 @@ void neo1973_bootmenu(void) + bootmenu_add("Factory reset", factory_reset, NULL); + bootmenu(); + } ++ ++void raise() ++{ ++ serial_printf( "*** something's wrong... please reset ***\n" ); ++} ++ ++void abort() ++{ ++ serial_printf( "*** something's wrong... please reset ***\n" ); ++} ++ +Index: git/board/neo1973/gta01/u-boot.lds +=================================================================== +--- git.orig/board/neo1973/gta01/u-boot.lds ++++ git/board/neo1973/gta01/u-boot.lds +@@ -39,6 +39,10 @@ SECTIONS + + . = ALIGN(4); + .rodata : { *(.rodata) } ++ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } ++ __exidx_start = .; ++ .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } ++ __exidx_end = .; + + . = ALIGN(4); + .data : { *(.data) } +Index: git/board/neo1973/gta02/u-boot.lds +=================================================================== +--- git.orig/board/neo1973/gta02/u-boot.lds ++++ git/board/neo1973/gta02/u-boot.lds +@@ -39,6 +39,10 @@ SECTIONS + + . = ALIGN(4); + .rodata : { *(.rodata) } ++ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } ++ __exidx_start = .; ++ .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } ++ __exidx_end = .; + + . = ALIGN(4); + .data : { *(.data) } +Index: git/board/neo1973/common/lowlevel_foo.lds +=================================================================== +--- git.orig/board/neo1973/common/lowlevel_foo.lds ++++ git/board/neo1973/common/lowlevel_foo.lds +@@ -37,6 +37,10 @@ SECTIONS + + . = ALIGN(4); + .rodata : { *(.rodata) } ++ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } ++ __exidx_start = .; ++ .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } ++ __exidx_end = .; + + . = ALIGN(4); + .data : { *(.data) } +Index: git/board/hxd8/hxd8.c +=================================================================== +--- git.orig/board/hxd8/hxd8.c ++++ git/board/hxd8/hxd8.c +@@ -187,3 +187,6 @@ unsigned int dynpart_size[] = { + char *dynpart_names[] = { + "u-boot", "u-boot_env", "kernel", "splash", "rootfs", NULL }; + ++void raise() {} ++ ++void abort() {} +Index: git/board/hxd8/u-boot.lds +=================================================================== +--- git.orig/board/hxd8/u-boot.lds ++++ git/board/hxd8/u-boot.lds +@@ -39,6 +39,10 @@ SECTIONS + + . = ALIGN(4); + .rodata : { *(.rodata) } ++ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } ++ __exidx_start = .; ++ .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } ++ __exidx_end = .; + + . = ALIGN(4); + .data : { *(.data) } +Index: git/board/hxd8/lowlevel_foo.lds +=================================================================== +--- git.orig/board/hxd8/lowlevel_foo.lds ++++ git/board/hxd8/lowlevel_foo.lds +@@ -37,6 +37,10 @@ SECTIONS + + . = ALIGN(4); + .rodata : { *(.rodata) } ++ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } ++ __exidx_start = .; ++ .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } ++ __exidx_end = .; + + . = ALIGN(4); + .data : { *(.data) } +Index: git/board/qt2410/qt2410.c +=================================================================== +--- git.orig/board/qt2410/qt2410.c ++++ git/board/qt2410/qt2410.c +@@ -156,3 +156,7 @@ unsigned int dynpart_size[] = { + char *dynpart_names[] = { + "u-boot", "u-boot_env", "kernel", "splash", "rootfs", NULL }; + ++void raise() {} ++ ++void abort() {} ++ +Index: git/board/qt2410/u-boot.lds +=================================================================== +--- git.orig/board/qt2410/u-boot.lds ++++ git/board/qt2410/u-boot.lds +@@ -39,6 +39,10 @@ SECTIONS + + . = ALIGN(4); + .rodata : { *(.rodata) } ++ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } ++ __exidx_start = .; ++ .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } ++ __exidx_end = .; + + . = ALIGN(4); + .data : { *(.data) } +Index: git/Makefile +=================================================================== +--- git.orig/Makefile ++++ git/Makefile +@@ -225,7 +225,7 @@ LIBS := $(addprefix $(obj),$(LIBS)) + .PHONY : $(LIBS) + + # Add GCC lib +-PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc ++PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc -lgcc_eh + + # The "tools" are needed early, so put this first + # Don't include stuff already done in $(LIBS) +Index: git/board/smdk2440/smdk2440.c +=================================================================== +--- git.orig/board/smdk2440/smdk2440.c ++++ git/board/smdk2440/smdk2440.c +@@ -150,3 +150,6 @@ char *dynpart_names[] = { + "u-boot", "u-boot_env", "kernel", "splash", "rootfs", NULL }; + + ++void raise() {} ++void abort() {} ++ +Index: git/board/smdk2440/u-boot.lds +=================================================================== +--- git.orig/board/smdk2440/u-boot.lds ++++ git/board/smdk2440/u-boot.lds +@@ -39,6 +39,10 @@ SECTIONS + + . = ALIGN(4); + .rodata : { *(.rodata) } ++ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } ++ __exidx_start = .; ++ .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } ++ __exidx_end = .; + + . = ALIGN(4); + .data : { *(.data) } +Index: git/board/neo1973/gta02/gta02.c +=================================================================== +--- git.orig/board/neo1973/gta02/gta02.c ++++ git/board/neo1973/gta02/gta02.c +@@ -321,3 +321,7 @@ int neo1973_set_charge_mode(enum neo1973 + /* FIXME */ + return 0; + } ++ ++void raise() {} ++void abort() {} ++ diff --git a/packages/u-boot/u-boot-1.1.2/.mtn2git_empty b/packages/u-boot/u-boot-1.1.2/.mtn2git_empty new file mode 100644 index 0000000000..e69de29bb2 diff --git a/packages/u-boot/u-boot-1.1.2/arm_flags.patch b/packages/u-boot/u-boot-1.1.2/arm_flags.patch new file mode 100644 index 0000000000..48c7b78043 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.2/arm_flags.patch @@ -0,0 +1,15 @@ + +# +# Patch managed by http://www.holgerschurig.de/patcher.html +# + +--- u-boot-1.1.2/cpu/pxa/config.mk~armflags ++++ u-boot-1.1.2/cpu/pxa/config.mk +@@ -23,6 +23,6 @@ + # + + PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ +- -mshort-load-bytes -msoft-float ++ -msoft-float + + PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100 diff --git a/packages/u-boot/u-boot-1.1.2/cmd-arm-linux.patch b/packages/u-boot/u-boot-1.1.2/cmd-arm-linux.patch new file mode 100644 index 0000000000..e7ef37e061 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.2/cmd-arm-linux.patch @@ -0,0 +1,122 @@ + +# +# Patch managed by http://www.holgerschurig.de/patcher.html +# + +--- u-boot-1.1.2/include/cmd_confdefs.h~cmd-arm-linux ++++ u-boot-1.1.2/include/cmd_confdefs.h +@@ -92,6 +92,7 @@ + #define CFG_CMD_XIMG 0x0400000000000000ULL /* Load part of Multi Image */ + #define CFG_CMD_UNIVERSE 0x0800000000000000ULL /* Tundra Universe Support */ + #define CFG_CMD_EXT2 0x1000000000000000ULL /* EXT2 Support */ ++#define CFG_CMD_LINUX 0x2000000000000000ULL /* boot zImage directly */ + + #define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFFULL /* ALL commands */ + +--- u-boot-1.1.2/lib_arm/armlinux.c~cmd-arm-linux ++++ u-boot-1.1.2/lib_arm/armlinux.c +@@ -271,6 +271,104 @@ + } + + ++#if (CONFIG_COMMANDS & CFG_CMD_LINUX) ++void do_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ++{ ++ DECLARE_GLOBAL_DATA_PTR; ++ ++ ulong initrd_start = 0; ++ ulong initrd_end = 0; ++ ulong data; ++ void (*theKernel)(int zero, int arch, uint params); ++ bd_t *bd = gd->bd; ++ ++ ++#ifdef CONFIG_CMDLINE_TAG ++ char cmdline[128]; ++ char *s; ++#endif ++ ++#ifdef CONFIG_CMDLINE_TAG ++ if (argc > 1) { ++ ulong len; ++ int i; ++ ++ for (i=1, len=0 ; i 1) ++ cmdline[len++] = ' '; ++ strcpy (&cmdline[len], argv[i]); ++ len += strlen(argv[i]); ++ } ++ } else ++ if ((s = getenv("bootargs")) != NULL) { ++ strcpy(cmdline, s); ++ } else { ++ strcpy(cmdline, ""); ++ } ++#endif ++ ++ theKernel = (void (*)(int, int, uint))load_addr; ++ ++ SHOW_BOOT_PROGRESS (14); ++ ++#ifdef DEBUG ++ printf ("## Transferring control to Linux (at address %08lx) ...\n", ++ (ulong)theKernel); ++#endif ++ ++#if defined (CONFIG_SETUP_MEMORY_TAGS) || \ ++ defined (CONFIG_CMDLINE_TAG) || \ ++ defined (CONFIG_INITRD_TAG) || \ ++ defined (CONFIG_SERIAL_TAG) || \ ++ defined (CONFIG_REVISION_TAG) || \ ++ defined (CONFIG_LCD) || \ ++ defined (CONFIG_VFD) ++ setup_start_tag(bd); ++#ifdef CONFIG_SERIAL_TAG ++ setup_serial_tag(¶ms); ++#endif ++#ifdef CONFIG_REVISION_TAG ++ setup_revision_tag(¶ms); ++#endif ++#ifdef CONFIG_SETUP_MEMORY_TAGS ++ setup_memory_tags(bd); ++#endif ++#ifdef CONFIG_CMDLINE_TAG ++ setup_commandline_tag(bd, cmdline); ++#endif ++#ifdef CONFIG_INITRD_TAG ++ setup_initrd_tag(bd, initrd_start, initrd_end); ++#endif ++#if defined (CONFIG_VFD) || defined (CONFIG_LCD) ++ setup_videolfb_tag ((gd_t *) gd); ++#endif ++ setup_end_tag(bd); ++#endif ++ ++ /* we assume that the kernel is in place */ ++ printf("\nStarting kernel ...\n"); ++ ++#ifdef CONFIG_USB_DEVICE ++ { ++ extern void udc_disconnect (void); ++ udc_disconnect (); ++ } ++#endif ++ cleanup_before_linux(); ++ ++ //TODO: CONFIG_TAG_ADDR is now bd->bi_boot_params ? ++ theKernel(0, bd->bi_arch_number, bd->bi_boot_params); ++} ++ ++ ++U_BOOT_CMD( ++ linux, CFG_MAXARGS, 0, do_linux, ++ "linux - boot Linux zImage directly\n", ++ "[arg ...]\n - boot Linux zImage, passing arguments 'arg ...'\n" ++); ++#endif ++ ++ + #if defined (CONFIG_SETUP_MEMORY_TAGS) || \ + defined (CONFIG_CMDLINE_TAG) || \ + defined (CONFIG_INITRD_TAG) || \ diff --git a/packages/u-boot/u-boot-1.1.2/command-names.patch b/packages/u-boot/u-boot-1.1.2/command-names.patch new file mode 100644 index 0000000000..dd9a7fab44 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.2/command-names.patch @@ -0,0 +1,340 @@ + +# +# Patch managed by http://www.holgerschurig.de/patcher.html +# + +--- u-boot-1.1.2/common/cmd_mem.c~command-names ++++ u-boot-1.1.2/common/cmd_mem.c +@@ -1188,56 +1188,56 @@ + /**************************************************/ + #if (CONFIG_COMMANDS & CFG_CMD_MEMORY) + U_BOOT_CMD( +- md, 3, 1, do_mem_md, +- "md - memory display\n", ++ memdump, 3, 1, do_mem_md, ++ "memdump - memory display\n", + "[.b, .w, .l] address [# of objects]\n - memory display\n" + ); + + + U_BOOT_CMD( +- mm, 2, 1, do_mem_mm, +- "mm - memory modify (auto-incrementing)\n", ++ memmod, 2, 1, do_mem_mm, ++ "memmod - memory modify (auto-incrementing)\n", + "[.b, .w, .l] address\n" " - memory modify, auto increment address\n" + ); + + + U_BOOT_CMD( +- nm, 2, 1, do_mem_nm, +- "nm - memory modify (constant address)\n", ++ memchg, 2, 1, do_mem_nm, ++ "memchg - memory modify (constant address)\n", + "[.b, .w, .l] address\n - memory modify, read and keep address\n" + ); + + U_BOOT_CMD( +- mw, 4, 1, do_mem_mw, +- "mw - memory write (fill)\n", ++ memfill, 4, 1, do_mem_mw, ++ "memfill - fill write\n", + "[.b, .w, .l] address value [count]\n - write memory\n" + ); + + U_BOOT_CMD( +- cp, 4, 1, do_mem_cp, +- "cp - memory copy\n", ++ memcp, 4, 1, do_mem_cp, ++ "memcp - copy memory\n", + "[.b, .w, .l] source target count\n - copy memory\n" + ); + + U_BOOT_CMD( +- cmp, 4, 1, do_mem_cmp, +- "cmp - memory compare\n", ++ memcmp, 4, 1, do_mem_cmp, ++ "memcmp - compary memory\n", + "[.b, .w, .l] addr1 addr2 count\n - compare memory\n" + ); + + #ifndef CONFIG_CRC32_VERIFY + + U_BOOT_CMD( +- crc32, 4, 1, do_mem_crc, +- "crc32 - checksum calculation\n", ++ memcrc, 4, 1, do_mem_crc, ++ "memcrc - checksum memory\n", + "address count [addr]\n - compute CRC32 checksum [save at addr]\n" + ); + + #else /* CONFIG_CRC32_VERIFY */ + + U_BOOT_CMD( +- crc32, 5, 1, do_mem_crc, +- "crc32 - checksum calculation\n", ++ memcrc, 5, 1, do_mem_crc, ++ "memcrc - checksum memory\n", + "address count [addr]\n - compute CRC32 checksum [save at addr]\n" + "-v address count crc\n - verify crc of memory area\n" + ); +@@ -1245,31 +1245,31 @@ + #endif /* CONFIG_CRC32_VERIFY */ + + U_BOOT_CMD( +- base, 2, 1, do_mem_base, +- "base - print or set address offset\n", ++ membase, 2, 1, do_mem_base, ++ "membase - print/set memory offset\n", + "\n - print address offset for memory commands\n" +- "base off\n - set address offset for memory commands to 'off'\n" ++ "[offset]\n - set address offset for memory commands to 'offset'\n" + ); + + U_BOOT_CMD( +- loop, 3, 1, do_mem_loop, +- "loop - infinite loop on address range\n", ++ memloop, 3, 1, do_mem_loop, ++ "memloop - infinite loop on address range\n", + "[.b, .w, .l] address number_of_objects\n" + " - loop on a set of addresses\n" + ); + + #ifdef CONFIG_LOOPW + U_BOOT_CMD( +- loopw, 4, 1, do_mem_loopw, +- "loopw - infinite write loop on address range\n", ++ memloopw, 4, 1, do_mem_loopw, ++ "memloopw- infinite write loop on address range\n", + "[.b, .w, .l] address number_of_objects data_to_write\n" + " - loop on a set of addresses\n" + ); + #endif /* CONFIG_LOOPW */ + + U_BOOT_CMD( +- mtest, 4, 1, do_mem_mtest, +- "mtest - simple RAM test\n", ++ memtest, 4, 1, do_mem_mtest, ++ "memtest - simple RAM test\n", + "[start [end [pattern]]]\n" + " - simple RAM read/write test\n" + ); +--- u-boot-1.1.2/common/cmd_flash.c~command-names ++++ u-boot-1.1.2/common/cmd_flash.c +@@ -507,30 +507,30 @@ + ); + + U_BOOT_CMD( +- erase, 3, 1, do_flerase, +- "erase - erase FLASH memory\n", ++ flerase, 3, 1, do_flerase, ++ "flerase - erase FLASH memory\n", + "start end\n" + " - erase FLASH from addr 'start' to addr 'end'\n" +- "erase N:SF[-SL]\n - erase sectors SF-SL in FLASH bank # N\n" +- "erase bank N\n - erase FLASH bank # N\n" +- "erase all\n - erase all FLASH banks\n" ++ "flerase N:SF[-SL]\n - erase sectors SF-SL in FLASH bank # N\n" ++ "flerase bank N\n - erase FLASH bank # N\n" ++ "flerase all\n - erase all FLASH banks\n" + ); + + U_BOOT_CMD( +- protect, 4, 1, do_protect, +- "protect - enable or disable FLASH write protection\n", ++ flprot, 4, 1, do_protect, ++ "flprot - enable or disable FLASH write protection\n", + "on start end\n" + " - protect FLASH from addr 'start' to addr 'end'\n" +- "protect on N:SF[-SL]\n" ++ "flprot on N:SF[-SL]\n" + " - protect sectors SF-SL in FLASH bank # N\n" +- "protect on bank N\n - protect FLASH bank # N\n" +- "protect on all\n - protect all FLASH banks\n" +- "protect off start end\n" ++ "flprot on bank N\n - protect FLASH bank # N\n" ++ "flprot on all\n - protect all FLASH banks\n" ++ "flprot off start end\n" + " - make FLASH from addr 'start' to addr 'end' writable\n" +- "protect off N:SF[-SL]\n" ++ "flprot off N:SF[-SL]\n" + " - make sectors SF-SL writable in FLASH bank # N\n" +- "protect off bank N\n - make FLASH bank # N writable\n" +- "protect off all\n - make all FLASH banks writable\n" ++ "flprot off bank N\n - make FLASH bank # N writable\n" ++ "flprot off all\n - make all FLASH banks writable\n" + ); + + #endif /* CFG_CMD_FLASH */ +--- u-boot-1.1.2/common/cmd_bootm.c~command-names ++++ u-boot-1.1.2/common/cmd_bootm.c +@@ -446,8 +446,8 @@ + } + + U_BOOT_CMD( +- bootm, CFG_MAXARGS, 1, do_bootm, +- "bootm - boot application image from memory\n", ++ imgboot, CFG_MAXARGS, 1, do_bootm, ++ "imgboot - boot application image from memory\n", + "[addr [arg ...]]\n - boot application image stored in memory\n" + "\tpassing arguments 'arg ...'; when booting a Linux kernel,\n" + "\t'arg' can be the address of an initrd image\n" +@@ -1056,8 +1056,8 @@ + } + + U_BOOT_CMD( +- iminfo, CFG_MAXARGS, 1, do_iminfo, +- "iminfo - print header information for application image\n", ++ imginfo, CFG_MAXARGS, 1, do_iminfo, ++ "imginfo - print header information for application image\n", + "addr [addr ...]\n" + " - print header information for application image starting at\n" + " address 'addr' in memory; this includes verification of the\n" +@@ -1116,8 +1116,8 @@ + } + + U_BOOT_CMD( +- imls, 1, 1, do_imls, +- "imls - list all images found in flash\n", ++ imgls, 1, 1, do_imls, ++ "imgls - list all images found in flash\n", + "\n" + " - Prints information about all images found at sector\n" + " boundaries in flash.\n" +--- u-boot-1.1.2/common/cmd_jffs2.c~command-names ++++ u-boot-1.1.2/common/cmd_jffs2.c +@@ -259,8 +259,8 @@ + } + + U_BOOT_CMD( +- chpart, 2, 0, do_jffs2_chpart, +- "chpart\t- change active partition\n", ++ jffspart, 2, 0, do_jffs2_chpart, ++ "jffspart\t- change active partition\n", + " - change active partition\n" + ); + #endif /* CFG_JFFS_SINGLE_PART */ +@@ -268,22 +268,22 @@ + /***************************************************/ + + U_BOOT_CMD( +- fsload, 3, 0, do_jffs2_fsload, +- "fsload\t- load binary file from a filesystem image\n", ++ jffsload, 3, 0, do_jffs2_fsload, ++ "jffsload- load binary file from a filesystem image\n", + "[ off ] [ filename ]\n" + " - load binary file from flash bank\n" + " with offset 'off'\n" + ); + + U_BOOT_CMD( +- fsinfo, 1, 1, do_jffs2_fsinfo, +- "fsinfo\t- print information about filesystems\n", ++ jffsinfo, 1, 1, do_jffs2_fsinfo, ++ "jffsinfo- print information about filesystems\n", + " - print information about filesystems\n" + ); + + U_BOOT_CMD( +- ls, 2, 1, do_jffs2_ls, +- "ls\t- list files in a directory (default /)\n", ++ jffsls, 2, 1, do_jffs2_ls, ++ "jffsls\t- list files in a directory (default /)\n", + "[ directory ]\n" + " - list files in a directory.\n" + ); +--- u-boot-1.1.2/common/cmd_nvedit.c~command-names ++++ u-boot-1.1.2/common/cmd_nvedit.c +@@ -570,19 +570,19 @@ + /**************************************************/ + + U_BOOT_CMD( +- printenv, CFG_MAXARGS, 1, do_printenv, +- "printenv- print environment variables\n", ++ env, CFG_MAXARGS, 1, do_printenv, ++ "env - print environment variables\n", + "\n - print values of all environment variables\n" +- "printenv name ...\n" ++ "env name ...\n" + " - print value of environment variable 'name'\n" + ); + + U_BOOT_CMD( +- setenv, CFG_MAXARGS, 0, do_setenv, +- "setenv - set environment variables\n", ++ envset, CFG_MAXARGS, 0, do_setenv, ++ "envset - set environment variables\n", + "name value ...\n" + " - set environment variable 'name' to 'value ...'\n" +- "setenv name\n" ++ "envset name\n" + " - delete environment variable 'name'\n" + ); + +@@ -590,8 +590,8 @@ + ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == \ + (CFG_CMD_ENV|CFG_CMD_FLASH)) + U_BOOT_CMD( +- saveenv, 1, 0, do_saveenv, +- "saveenv - save environment variables to persistent storage\n", ++ envsave, 1, 0, do_saveenv, ++ "envsave - save environment variables to persistent storage\n", + NULL + ); + +@@ -600,16 +600,16 @@ + #if (CONFIG_COMMANDS & CFG_CMD_ASKENV) + + U_BOOT_CMD( +- askenv, CFG_MAXARGS, 1, do_askenv, +- "askenv - get environment variables from stdin\n", ++ envask, CFG_MAXARGS, 1, do_askenv, ++ "envask - get environment variables from stdin\n", + "name [message] [size]\n" + " - get environment variable 'name' from stdin (max 'size' chars)\n" +- "askenv name\n" ++ "envask name\n" + " - get environment variable 'name' from stdin\n" +- "askenv name size\n" ++ "envask name size\n" + " - get environment variable 'name' from stdin (max 'size' chars)\n" +- "askenv name [message] size\n" +- " - display 'message' string and get environment variable 'name'" ++ "envask name [message] size\n" ++ " - display 'message' string and get environment variable 'name' " + "from stdin (max 'size' chars)\n" + ); + #endif /* CFG_CMD_ASKENV */ +@@ -617,8 +617,8 @@ + #if (CONFIG_COMMANDS & CFG_CMD_RUN) + int do_run (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + U_BOOT_CMD( +- run, CFG_MAXARGS, 1, do_run, +- "run - run commands in an environment variable\n", ++ envrun, CFG_MAXARGS, 1, do_run, ++ "envrun - run commands in an environment variable\n", + "var [...]\n" + " - run the commands in the environment variable(s) 'var'\n" + ); +--- u-boot-1.1.2/common/cmd_cache.c~command-names ++++ u-boot-1.1.2/common/cmd_cache.c +@@ -96,15 +96,15 @@ + + + U_BOOT_CMD( +- icache, 2, 1, do_icache, +- "icache - enable or disable instruction cache\n", ++ cachei, 2, 1, do_icache, ++ "cachei - enable or disable instruction cache\n", + "[on, off]\n" + " - enable or disable instruction cache\n" + ); + + U_BOOT_CMD( +- dcache, 2, 1, do_dcache, +- "dcache - enable or disable data cache\n", ++ cached, 2, 1, do_dcache, ++ "cached - enable or disable data cache\n", + "[on, off]\n" + " - enable or disable data (writethrough) cache\n" + ); diff --git a/packages/u-boot/u-boot-1.1.2/mnci-jffs2.patch b/packages/u-boot/u-boot-1.1.2/mnci-jffs2.patch new file mode 100644 index 0000000000..8b2571ad99 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.2/mnci-jffs2.patch @@ -0,0 +1,16 @@ + +# +# Patch managed by http://www.holgerschurig.de/patcher.html +# + +--- u-boot-1.1.2/common/cmd_jffs2.c~mnci-jffs2 ++++ u-boot-1.1.2/common/cmd_jffs2.c +@@ -43,7 +43,7 @@ + extern int cramfs_ls (struct part_info *info, char *filename); + extern int cramfs_info (struct part_info *info); + +-static int part_num=0; ++static int part_num=3; + + #ifndef CFG_JFFS_CUSTOM_PART + diff --git a/packages/u-boot/u-boot-1.1.2/mnci.patch b/packages/u-boot/u-boot-1.1.2/mnci.patch new file mode 100644 index 0000000000..d69cf8eb72 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.2/mnci.patch @@ -0,0 +1,1007 @@ + +# +# Patch managed by http://www.holgerschurig.de/patcher.html +# + +--- u-boot-1.1.2/CREDITS~mnci ++++ u-boot-1.1.2/CREDITS +@@ -360,6 +360,9 @@ + E: r.schwebel@pengutronix.de + D: Support for csb226, logodl and innokom boards (PXA2xx) + ++N: Holger Schurig ++D: Support for MNCI-RX "Ramses" ++ + N: Yasushi Shoji + E: yashi@atmark-techno.com + D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board +--- u-boot-1.1.2/MAINTAINERS~mnci ++++ u-boot-1.1.2/MAINTAINERS +@@ -396,6 +396,10 @@ + csb226 xscale + innokom xscale + ++Holger Schurig ++ ++ mnci xscale ++ + Andrea Scian + + B2 ARM7TDMI (S3C44B0X) +--- u-boot-1.1.2/Makefile~mnci ++++ u-boot-1.1.2/Makefile +@@ -1388,6 +1388,9 @@ + wepep250_config : unconfig + @./mkconfig $(@:_config=) arm pxa wepep250 + ++mnci_config : unconfig ++ @./mkconfig $(@:_config=) arm pxa mnci ++ + xaeniax_config : unconfig + @./mkconfig $(@:_config=) arm pxa xaeniax + +--- /dev/null ++++ u-boot-1.1.2/board/mnci/Makefile +@@ -0,0 +1,49 @@ ++# ++# (C) Copyright 2000 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# (C) Copyright 2005 ++# M&N Solutions GmbH, Rosbach, Germany, Holger Schurig ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = lib$(BOARD).a ++ ++OBJS := mnci.o ++SOBJS := memsetup.o ++ ++$(LIB): $(OBJS) $(SOBJS) ++ $(AR) crv $@ $(OBJS) $(SOBJS) ++ ++clean: ++ rm -f $(SOBJS) $(OBJS ++ ++distclean: clean ++ rm -f $(LIB) core *.bak .depend ++ ++######################################################################### ++ ++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) ++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ ++ ++-include .depend ++ ++######################################################################### +--- /dev/null ++++ u-boot-1.1.2/board/mnci/config.mk +@@ -0,0 +1 @@ ++TEXT_BASE = 0xa1fe0000 +--- /dev/null ++++ u-boot-1.1.2/board/mnci/u-boot.lds +@@ -0,0 +1,55 @@ ++/* ++ * (C) Copyright 2000 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++OUTPUT_ARCH(arm) ++ENTRY(_start) ++SECTIONS ++{ ++ . = 0x00000000; ++ ++ . = ALIGN(4); ++ .text : ++ { ++ cpu/pxa/start.o (.text) ++ *(.text) ++ } ++ ++ . = ALIGN(4); ++ .rodata : { *(.rodata) } ++ ++ . = ALIGN(4); ++ .data : { *(.data) } ++ ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss : { *(.bss) } ++ _end = .; ++} +--- /dev/null ++++ u-boot-1.1.2/board/mnci/mnci.c +@@ -0,0 +1,174 @@ ++/* ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++ ++/** ++ * board_init: - setup some data structures ++ * ++ * @return: 0 in case of success ++ */ ++ ++int board_init (void) ++{ ++ DECLARE_GLOBAL_DATA_PTR; ++ ++ /* memory and cpu-speed are setup before relocation */ ++ /* so we do _nothing_ here */ ++ ++ gd->bd->bi_arch_number = MACH_TYPE_RAMSES; ++ gd->bd->bi_boot_params = 0xa0000100; ++#if 0 ++ gd->bd->bi_baudrate = 115200; ++#endif ++ ++#if 0 ++ CKEN |= CKEN2_AC97; ++ GCR = GCR_COLD_RST; ++#endif ++ ++ return 0; ++} ++ ++ ++int board_late_init(void) ++{ ++ setenv("stdout", "serial"); ++ setenv("stderr", "serial"); ++ return 0; ++} ++ ++ ++/** ++ * dram_init: - setup dynamic RAM ++ * ++ * @return: 0 in case of success ++ */ ++ ++int dram_init (void) ++{ ++ DECLARE_GLOBAL_DATA_PTR; ++ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; ++ ++ return 0; ++} ++ ++ ++ ++#ifdef CFG_JFFS_CUSTOM_PART ++ ++#include ++ ++#define FLASH_DEBUG 1 ++ ++/* Some debug macros */ ++#if (FLASH_DEBUG > 2 ) ++#define PRINTK3(args...) printf(args) ++#else ++#define PRINTK3(args...) ++#endif ++ ++#if FLASH_DEBUG > 1 ++#define PRINTK2(args...) printf(args) ++#else ++#define PRINTK2(args...) ++#endif ++ ++#ifdef FLASH_DEBUG ++#define PRINTK(args...) printf(args) ++#else ++#define PRINTK(args...) ++#endif ++ ++ ++#define FLASH_BANK_SIZE 0x02000000 /* 32 MB (during development) */ ++#define MAIN_SECT_SIZE 0x00040000 /* 256k per sector */ ++ ++#ifndef CFG_FLASH_CFI ++flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; ++#endif ++ ++static struct part_info part; ++static int current_part = -1; ++ ++struct part_info* jffs2_part_info(int part_num) { ++ void *jffs2_priv_saved = part.jffs2_priv; ++ ++ PRINTK2("jffs2_part_info: part_num=%i\n",part_num); ++ ++ if (current_part == part_num) ++ return ∂ ++ ++ /* u-boot partition */ ++ if(part_num==0){ ++ memset(&part, 0, sizeof(part)); ++ ++ part.offset=(char*)0x00000000; ++ part.size=0x00040000; ++ ++ /* Mark the struct as ready */ ++ current_part = part_num; ++ ++ PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset); ++ PRINTK("part.size = 0x%08x\n",(unsigned int)part.size); ++ } ++ ++ /* primary Kernel partition */ ++ if(part_num==1){ ++ memset(&part, 0, sizeof(part)); ++ ++ part.offset=(char*)0x00040000; ++ part.size=0x00040000*4; ++ ++ /* Mark the struct as ready */ ++ current_part = part_num; ++ ++ PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset); ++ PRINTK("part.size = 0x%08x\n",(unsigned int)part.size); ++ } ++ ++ /* data partition */ ++ if(part_num==3){ ++ memset(&part, 0, sizeof(part)); ++ ++ part.offset=(char*)0x00140000; ++ part.size=FLASH_BANK_SIZE-0x00140000; ++ ++ /* Mark the struct as ready */ ++ current_part = part_num; ++ ++ PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset); ++ PRINTK("part.size = 0x%08x\n",(unsigned int)part.size); ++ } ++ ++ if (current_part == part_num) { ++ part.usr_priv = ¤t_part; ++ part.jffs2_priv = jffs2_priv_saved; ++ return ∂ ++ } ++ ++ PRINTK("jffs2_part_info: end of partition table\n"); ++ return 0; ++} ++#endif +--- /dev/null ++++ u-boot-1.1.2/include/configs/mnci.h +@@ -0,0 +1,309 @@ ++/* ++ * (C) Copyright 2005 ++ * Holger Schurig, M&N Solutions GmbH, Rosbach, Germany ++ * ++ * Configuration for the Auerswald Innokom CPU board. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#include ++ ++/* ++ * If we are developing, we might want to start armboot from ram ++ * so we MUST NOT initialize critical regs like mem-timing ... ++ */ ++#define CONFIG_INIT_CRITICAL /* undef for developing */ ++ ++/* ++ * define the following to enable debug blinks. A debug blink function ++ * must be defined in memsetup.S ++ */ ++#undef DEBUG_BLINK_ENABLE ++#undef DEBUG_BLINKC_ENABLE ++ ++/* ++ * High Level Configuration Options ++ * (easy to change) ++ */ ++#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ ++ ++#undef CONFIG_LCD ++#ifdef CONFIG_LCD ++#define CONFIG_SHARP_LM8V31 ++#endif ++ ++#define CONFIG_MMC 1 ++#define BOARD_LATE_INIT 1 ++ ++#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ ++ ++/* ++ * Size of malloc() pool ++ */ ++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) ++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ ++ ++/* ++ * MNCI memory map information ++ */ ++ ++#define MNCI_CS5_ETH_OFFSET 0x03400000 ++ ++ ++/* ++ * Hardware drivers ++ */ ++#if 0 ++#define CONFIG_DRIVER_SMC91111 ++#define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + MNCI_CS5_ETH_OFFSET + 0x300) ++#define CONFIG_SMC_USE_32_BIT 1 ++//#define CONFIG_SMC_USE_IOFUNCS ++#endif ++ ++/* the following has to be set high -- suspect something is wrong with ++ * with the tftp timeout routines. FIXME!!! ++ */ ++#define CONFIG_NET_RETRY_COUNT 100 ++ ++/* ++ * select serial console configuration ++ */ ++#define CONFIG_FFUART 1 /* we use FFUART on MNCI */ ++ ++/* allow to overwrite serial and ethaddr */ ++//#define CONFIG_ENV_OVERWRITE ++ ++#define CONFIG_BAUDRATE 115200 ++ ++#define CONFIG_COMMANDS ( 0 \ ++ | CFG_CMD_ENV \ ++ | CFG_CMD_FLASH \ ++ | CFG_CMD_LINUX \ ++ | CFG_CMD_JFFS2 \ ++ | CFG_CMD_LOADB \ ++ | CFG_CMD_MEMORY \ ++ | CFG_CMD_MISC \ ++ | CFG_CMD_RUN \ ++ ) ++ ++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ ++#include ++ ++#define CONFIG_BOOTDELAY 0 ++#define CONFIG_BOOTCOMMAND "linux" ++#define CONFIG_BOOTARGS "console=ttyS0,115200 rootfstype=jffs2 root=/dev/mtdblock2" ++//#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfsroot ip=192.168.233.14:192.168.233.1:192.168.233.1:255.255.255.0:ramses2:eth0:off" ++#define CONFIG_CMDLINE_TAG 1 ++#define CONFIG_SETUP_MEMORY_TAGS 1 ++#define CFG_CONSOLE_INFO_QUIET 1 ++#define CFG_JFFS_SINGLE_PART 1 ++ ++/* ++ * Current memory map for MNCI supplied Linux images: ++ * ++ * Flash: ++ * 0x00000 - 0x003ffff: bootloader ++ * 0x040000 - 0x013ffff: kernel ++ * 0x140000 - 0x1ffffff: file system ++ * ++ * RAM: ++ * 0xa0008000 - kernel is loaded ++ * 0xa1fe0000 - Uboot runs (48MB into RAM) ++ * ++ */ ++ ++#define MY_CONFIG_EXTRA_ENV_SETTINGS \ ++ "prog_boot_mmc=" \ ++ "mw.b 0xa0000000 0xff 0x40000; " \ ++ "if mmcinit && " \ ++ "fatload mmc 0 0xa0000000 u-boot.bin; " \ ++ "then " \ ++ "protect off 0x0 0x3ffff; " \ ++ "erase 0x0 0x3ffff; " \ ++ "cp.b 0xa0000000 0x0 0x40000; " \ ++ "reset;" \ ++ "fi\0" \ ++ "prog_uImage_mmc=" \ ++ "mw.b 0xa0000000 0xff 0x1C0000; " \ ++ "if mmcinit && " \ ++ "fatload mmc 0 0xa0000000 uImage; " \ ++ "then " \ ++ "protect off 0x40000 0x13ffff; " \ ++ "erase 0x40000 0x13ffff; " \ ++ "cp.b 0xa0000000 0x40000 0x1C0000; " \ ++ "fi\0" \ ++ "prog_jffs_mmc=" \ ++ "mw.b 0xa0000000 0xff 0x1e00000; " \ ++ "if mmcinit && " \ ++ "fatload mmc 0 0xa0000000 root.jffs; " \ ++ "then " \ ++ "protect off 0x200000 0x13fffff; " \ ++ "erase 0x200000 0x13fffff; " \ ++ "cp.b 0xa0000000 0x200000 0x1e00000; " \ ++ "fi\0" \ ++ "boot_mmc=" \ ++ "if mmcinit && " \ ++ "fatload mmc 0 0xa1000000 uImage && " \ ++ "then " \ ++ "bootm 0xa1000000; " \ ++ "fi\0" \ ++ "prog_boot_net=" \ ++ "mw.b 0xa0000000 0xff 0x100000; " \ ++ "if bootp 0xa0000000 u-boot.bin; " \ ++ "then " \ ++ "protect off 0x0 0x3ffff; " \ ++ "erase 0x0 0x3ffff; " \ ++ "cp.b 0xa0000000 0x0 0x40000; " \ ++ "reset; " \ ++ "fi\0" \ ++ "prog_uImage_net=" \ ++ "mw.b 0xa0000000 0xff 0x1C0000; " \ ++ "if bootp 0xa0000000 uImage; " \ ++ "then " \ ++ "protect off 0x40000 0x13ffff; " \ ++ "erase 0x40000 0x13ffff; " \ ++ "cp.b 0xa0000000 0x40000 0x1C0000; " \ ++ "fi\0" \ ++ "boot_uImage_net=" \ ++ "mw.b 0xa0000000 0xff 0x1C0000; " \ ++ "if bootp 0xa0000000 uImage; " \ ++ "then " \ ++ "bootm 0xa0000000; " \ ++ "fi\0" \ ++ "prog_jffs_net=" \ ++ "mw.b 0xa0000000 0xff 0x1e00000; " \ ++ "if bootp 0xa0000000 root.jffs; " \ ++ "then " \ ++ "protect off 0x200000 0x13fffff; " \ ++ "erase 0x200000 0x13fffff; " \ ++ "cp.b 0xa0000000 0x200000 0x1e00000; " \ ++ "fi\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "bootargsnfs=console=ttyS0,115200 root=/dev/nfsroot ip=192.168.233.14:192.168.233.1:192.168.233.1:255.255.255.0:ramses2:eth0:off;\0" \ ++ "boot_nfs=" \ ++ "set bootargs $bootargsnfs; " \ ++ "linux\0" ++ ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ ++#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ ++#endif ++ ++/* ++ * Miscellaneous configurable options ++ */ ++//#define CFG_HUSH_PARSER 1 ++//#define CFG_PROMPT_HUSH_PS2 "> " ++ ++#define CFG_LONGHELP /* undef to save memory */ ++#define CFG_PROMPT "mnci> " /* Monitor Command Prompt */ ++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ ++#define CFG_MAXARGS 16 /* max number of command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ ++#define CFG_DEVICE_NULLDEV 1 ++ ++#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ ++#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ ++ ++#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ ++ ++#define CFG_LOAD_ADDR 0x40000 /* default load address */ ++ ++#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ ++#define CFG_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */ ++ ++//#define RTC 1 /* enable 32KHz osc */ ++ ++ /* valid baudrates */ ++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } ++ ++#define CFG_MMC_BASE 0xF0000000 ++ ++/* ++ * Stack sizes ++ * ++ * The stack sizes are set up in start.S using the settings below ++ */ ++#define CONFIG_STACKSIZE (256*1024) /* regular stack */ ++#ifdef CONFIG_USE_IRQ ++#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ ++#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ ++#endif ++ ++ ++/* ++ * Environment ++ */ ++#define CFG_MONITOR_BASE 0 ++#define CFG_MONITOR_LEN 0x40000 ++ ++#define CFG_ENV_IS_IN_FLASH 1 ++#define CFG_ENV_ADDR 0x20000 ++#define CFG_ENV_SIZE 0x4000 ++#define CFG_ENV_SECT_SIZE 0x40000 ++ ++/* ++ * Physical Memory Map ++ */ ++#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */ ++#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ ++#define PHYS_SDRAM_1_SIZE 0x08000000 /* 64 MB */ ++ ++#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ ++#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ ++#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ ++//#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ ++//#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ ++ ++#define CFG_DRAM_BASE PHYS_SDRAM_1 ++#define CFG_DRAM_SIZE PHYS_SDRAM_1_SIZE ++ ++#define CFG_FLASH_BASE PHYS_FLASH_1 ++ ++ ++/* ++ * JFFS2 Partitions ++ */ ++#define CFG_JFFS_CUSTOM_PART 1 /* see board/innokom/flash.c */ ++ ++ ++/* ++ * FLASH organization ++ */ ++#define CFG_FLASH_CFI ++#define CFG_FLASH_CFI_DRIVER 1 ++ ++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ ++#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ ++ ++#define CFG_FLASH_USE_BUFFER_WRITE 1 ++ ++/* timeout values are in ticks */ ++#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ ++#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ ++ ++ ++#endif /* __CONFIG_H */ +--- /dev/null ++++ u-boot-1.1.2/board/mnci/memsetup.S +@@ -0,0 +1,359 @@ ++/* ++ * Memory & peripheral setup of the XScale PXA250 ++ * ++ * Written October 2002 by H.Schurig for M&N Logistik-Lösungen Online GmbH ++ * http://www.mn-logistik.de/unsupported/pxa250/ ++ * ++ * Number in Parentheses like (3-29) refer to pages in the ++ * ++ * Intel PXA250 and PXA210 ++ * Application Processor ++ * Developer's Manual ++ * February 2002 ++ * ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++ ++ ++/********************************************************************** ++ * ++ * reginit ++ * ++ * PURPOSE: initialize stuff using a addr/data pair table ++ * PARAMS: r0 - address the the table ++ * REGISTERS: r0, r1, r2, r3 ++ * CALLS: Nothing ++ * RETURNS: Nothing ++ **********************************************************************/ ++reginit: ++1: ldmia r0!, {r1,r2} @ load reg/value from regtable ++ cmp r1, #0 @ at end? ++ strne r2, [r1] @ if not, store value into reg ++ ldrne r3, [r1] @ if not, read it back (see PXA errata) ++ bne 1b @ if not, branch back ++ mov pc, lr ++ ++ ++/********************************************************************** ++ * ++ * memsetup ++ * ++ * PURPOSE: ++ * PARAMS: ++ * REGISTERS: ++ * CALLS: ++ * RETURNS: Nothing ++ **********************************************************************/ ++ ++.globl memsetup ++memsetup: ++ mov r11, lr ++ ++ adr r0, SystemUnitTable ++ bl reginit ++ ++ @ Steps 2a..4d ++ adr r0,MemTable1 ++ bl reginit ++ ++ @ Step 4e wait 200 usec ++ ldr r0, oscr_addr ++ ldr r1, [r0] ++ add r1,r1,#0x300 @ Current OSCR+0x300 ++1: ++ ldr r2, [r0] ++ cmp r1, r2 ++ bgt 1b ++ ++ @ TODO: data cache must be off, see Developers Manual, Section 6.12, ++ @ page 6-77, point 6. ++ ++ @ Step 4f attempt read access to trigger a number of refresh cycles ++ ldr r2, =CFG_DRAM_BASE ++.rept 8 ++ str r2, [r2] ++.endr ++ ++ @ TODO: re-enable data cache ++ ++ @ Steps 4g..4h ++ adr r0,MemTable2 ++ bl reginit ++ @ Done with memory setup ++ ++ ++ @ Check if we return from Sleep Mode via RCSR (3-33) ++ ldr r0, rcsr_addr ++ ldr r1, [r0] ++ and r1,r1,#0xf @ mask RCSR_HWR|RCSR_WDR|RCSR_SMR|RCSR_GPR ++ str r1, [r0] @ clear Reset Controll State Register ++ teq r1, #4 @ RCSR_SMR (Sleep Mode) ++ beq WakeUp ++ ++ @ Issue Frequency Change Sequence ++freqchange: ++ mov r0, #3 ++ mcr p14, 0, r0, c6, c0, 0 ++ mov pc, r11 ++ ++WakeUp: ++ @ retrieve the scratchpad value and jump to that address ++ ldr r0, pspr_addr ++ ldr pc, [r0] ++ ++ ++@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ ++@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ ++@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ ++ ++ ++SystemUnitTable: ++ @ (4-22) Mask all interrupts ++ .long ICMR, 0x00000000 @ PM ++ @ (4-22) Interrupts are IRQs, not FIQs ++ .long ICLR, 0x00000000 ++ @ (4-23) Only enabled and unmasked interrupts bring the CPU out of idle mode ++ .long ICCR, 0x00000001 ++ @ (4-41) Clear OS Timer Match bits ++ .long OSSR, 0x0000000f @ NO PM ++ @ (3-34) Set clock register (we change CP14,6 at the end of this function) ++ .long CCCR, 0x00000161 @ NO PM, 121 is slow, 241 is medium, 161 is fast ++ @ (3-38) Enable 32 kHz Oszillator ++ .long OSCC, 0x00000002 ++ ++ @ (3-36) Enable needed clocks ++ .long CKEN, 0x00000043 @ PM: FFUART, PWM0, PWM1 ++ ++ .long 0x17c00004,8 @ CPLD: PER_PWR_EN ++ ++// Bit GPIO Level Function Direct Altern Function ++// -------------------------------------------------- ++// 00000001 0 1 nc Input 0 normal GPIO ++// 00000002 1 1 nPFI Input 0 normal GPIO ++// 00000004 2 1 BAT_DATA Input 0 normal GPIO ++// 00000008 3 1 IRQ_KEY Input 0 normal GPIO ++// 00000010 4 0 IRQ_ETH Input 0 normal GPIO ++// 00000020 5 1 nc Input 0 normal GPIO ++// 00000040 6 0 MMC_CLK Output 1 MMC_CLK ++// 00000080 7 1 IRQ_GSM Input 0 normal GPIO ++// 00000100 8 1 nPCC_S1_CD Input 0 normal GPIO ++// 00000200 9 1 nMMC_CD Input 0 normal GPIO ++// 00000400 10 1 IRQ_RTC Input 0 normal GPIO ++// 00000800 11 0 nc 3M6 Output 1 3.6 MHz ++// 00001000 12 1 nc Input 0 normal GPIO ++// 00002000 13 1 IRQ_DOCK Input 0 normal GPIO ++// 00004000 14 1 nc Input 0 normal GPIO ++// 00008000 15 1 nc nCS1 Output 2 nCS1 ++ ++// 00010000 16 1 PWM0 Output 2 PWM0 ++// 00020000 17 1 PWM1 Output 2 PWM1 ++// 00040000 18 1 RDY Input 1 RDY ++// 00080000 19 1 nPCC_S0_IRQ Input 0 normal GPIO ++// 00100000 20 1 nc Input 0 normal GPIO ++// 00200000 21 1 AC97_IRQ Input 0 normal GPIO ++// 00400000 22 1 nPCC_S1_IRQ Input 0 normal GPIO ++// 00800000 23 1 nc IRQ_GSM Input 0 normal GPIO ++// 01000000 24 0 UART_INTB Input 0 normal GPIO ++// 02000000 25 0 UART_INTC Input 0 normal GPIO ++// 04000000 26 1 UART_INTD Input 0 normal GPIO ++// 08000000 27 0 nc cpldfree Input 0 normal GPIO ++// 10000000 28 1 AUD_BITCLK Input 1 97_BITCLK ++// 20000000 29 0 AUD_SDIN0 Input 1 97_SDATAIN0 ++// 40000000 30 0 AUD_SDOUT Output 2 97_SDATAOUT ++// 80000000 31 0 AUD_SYNC Output 2 97_SYNC ++ ++ .long GPSR0, 0x00008000 @ set nCS1 ++ .long GPDR0, 0xd0038840 @ out MMC_CLK, 3M6, nCS1, PWM0, PWM1 ++ .long GAFR0_L,0x80401000 @ MMC_CLK:1, 3M6:1, nCS1:2 ++ .long GAFR0_U,0xA500001a @ PWM0:2, PWM1:2, RDY:1 ++ @ 97_BITCLK:1, 97_SDATAIN0:1, 97_SDATAOUT:2, 97_SYNC:2 ++ .long PGSR0, 0x00028000 @ sleep set: nCS1, PWM1 ++ .long GRER0, 0x00000000 @ rising edge detect: none ++ .long GFER0, 0x00000000 @ falling edge detect: none ++ ++ ++// 00000001 32 0 USB_INT Input 0 normal GPIO ++// 00000002 33 1 nCS5 Output 2 nCS5 ++// 00000004 34 1 FF_RXD Input 1 FF_RXD ++// 00000008 35 1 FF_CTS Input 1 FF_CTS ++// 00000010 36 1 FF_DCD Input 1 FF_DCD ++// 00000020 37 1 FF_DSR Input 1 FF_DSR ++// 00000040 38 1 FF_RI Input 1 FF_RI ++// 00000080 39 0 FF_TXD Output 2 FF_TXD ++// 00000100 40 0 FF_DTR Output 2 FF_DTR ++// 00000200 41 0 FF_RTS Output 2 FF_RTS ++// 00000400 42 1 BT_RXD Input 1 BT_RXD ++// 00000800 43 1 BT_TXD Output 2 BT_TXD ++// 00001000 44 0 BT_CTS Input 1 BT_CTS ++// 00002000 45 1 BT_RTS Output 2 BT_RTS ++// 00004000 46 1 IR_RXD Input 1 ICP_RXD ++// 00008000 47 0 IR_TXD Output 2 ICP_TXD ++// 00010000 48 1 nPOE Output 2 nPOE ++// 00020000 49 1 nPWE Output 2 nPWE ++// 00040000 50 1 nPIOR Output 2 nPIOR ++// 00080000 51 1 nPIOW Output 2 nPIOW ++// 00100000 52 1 nPCE1 Output 2 nPCE1 ++// 00200000 53 1 nPCE2 Output 2 nPCE2 ++// 00400000 54 0 nPKTSEL Output 2 nPKTSEL ++// 00800000 55 1 nPREG Output 2 nPREG ++// 01000000 56 1 nPWAIT Input 1 nPWAIT ++// 02000000 57 1 nIOIS16 Input 1 nIOI16 ++// 04000000 58 0 LDD0 Output 2 LDD0 ++// 08000000 59 1 LDD1 Output 2 LDD1 ++// 10000000 60 0 LDD2 Output 2 LDD2 ++// 20000000 61 1 LDD3 Output 2 LDD3 ++// 40000000 62 0 LDD4 Output 2 LDD4 ++// 80000000 63 0 LDD5 Output 2 LDD5 ++ ++ .long GPSR1, 0x00020302 @ set nCS5, FF_RTS, FF_DTR, nPWE ++ .long GPCR1, 0x00000080 @ clear FF_TXD ++ .long GPDR1, 0xfcffab82 @ out: nCS5, FF_TXD, FF_DTR, FF_RTS, BT_TXD, ++ @ BT_RTS, IR_TXD, nPOE...nPREG, LDD0..LDD5 ++ .long GAFR1_L,0x999a9558 @ ++ .long GAFR1_U,0xaaa5aaaa @ ++ .long PGSR1, 0x00020002 @ sleep set: nCS5, nPWE ++ .long GRER1, 0x00000000 @ ++ .long GFER1, 0x00000000 @ ++ ++ ++ ++// 00000001 64 0 LDD6 Output 2 LDD6 ++// 00000002 65 1 LDD7 Output 2 LDD7 ++// 00000004 66 1 LDD8 Output 2 LDD8 ++// 00000008 67 0 LDD9 Output 2 LDD9 ++// 00000010 68 1 LDD10 Output 2 LDD10 ++// 00000020 69 0 LDD11 Output 2 LDD11 ++// 00000040 70 0 LDD12 Output 2 LDD12 ++// 00000080 71 1 LDD13 Output 2 LDD13 ++// 00000100 72 0 LDD14 Output 2 LDD14 ++// 00000200 73 0 LDD15 Output 2 LDD15 ++// 00000400 74 1 FCLK Output 2 FCLK ++// 00000800 75 1 LCLK Output 2 LCLK ++// 00001000 76 1 PCLK Output 2 PCLK ++// 00002000 77 0 BIAS Output 2 ACBIAS ++// 00004000 78 1 nCS2 Output 2 nCS2 ++// 00008000 79 1 nCS3 Output 2 nCS3 ++// 00010000 80 1 nCS4 Output 2 nCS4 ++// 00020000 81 1 nc Input 0 normal GPIO ++// 00040000 82 1 nc Input 0 normal GPIO ++// 00080000 83 1 nc Input 0 normal GPIO ++// 00100000 84 1 nc Input 0 normal GPIO ++ ++ .long GPSR2, 0x0001c000 @ set nCS2..4 ++ .long GPDR2, 0x0001FFFF @ out: LDD6..nCS4 ++ .long GAFR2_L,0xaaaaaaaa @ ++ .long GAFR2_U,0x00000002 @ ++ .long PGSR2, 0x0001c000 @ sleep set: nCS2..4 ++ .long GRER2, 0x00000000 @ ++ .long GFER2, 0x00000000 @ ++ ++ @ (3-25) Power Wakeup Registers ++ .long PWER, 0x00000008 @ wake up on IRQ_KEY ++ .long PRER, 0x00000008 @ detect rising edge on IRQ_KEY ++ .long PFER, 0x00000000 @ dont detect falling edges ++ ++ @ (3-28) Power Manager Edge Detect Status Register ++ .long PEDR, 0x00000008 @ clear edge detect status for IRQ_KEY ++ ++ @ (3-29) Sleep State Register ++ .long PSSR, 0x00000030 @ clear PH and RDH ++ ++ .long PWM_CTRL0, 0 ++ .long PWM_CTRL0, 0 ++ .long PWM_PERVAL0, 512 ++ .long PWM_PERVAL1, 512 ++ .long PWM_PWDUTY0, 440 ++ .long PWM_PWDUTY1, 450 ++ ++ @ End ++ .long 0,0 ++ ++ ++ ++ ++MemTable1: ++ @ Info on this sequence is in the OS Developers Guide, Section 10.0 on page 13 ++ @ also see Developers Manual, Section 6.12 on page 6-76 ++ ++ @ write MSC0, MSC1, MSC2 (6-44) ++ .long MSC0, 0x7ff0fdc3 @ f4c0 ++ .long MSC1, 0x29842981 ++ .long MSC2, 0x29842984 ++ ++ @ no synchronous static stuff here ++ .long SXCNFG, 0x00000000 @ (6-31) ++ ++ @ write MECR (6-60), MCMEMx (6-57), MCATTx (6-58), MCIOx (6-58) ++ .long MECR, 0x00000003 ++ .long MCMEM0, 0x00020418 ++ .long MCMEM1, 0x00020418 ++ .long MCATT0, 0x0002449D ++ .long MCATT1, 0x0002449D ++ .long MCIO0, 0x00014290 ++ .long MCIO1, 0x00014290 ++ ++ @ write FLYCNFG (that register is now undocumented) ++ ++ @ OS Developers Manual: write MDREFR (6-15), K0RUN and K0PIN are ++ @ set for synchronous static memory. The desired value of ++ @ K0DB2 can be programmed. KxFREE can be deasserted. APD must ++ @ remain deasserted and SLFRSH must remain asserted. ++ @ Developers Manual: write K0RUN and E0PIN. Configure K0DB2. Retain ++ @ the current values of APD and SLFRSH. DRI must contain a ++ @ valid value. Deassert KxFREE. ++ .long MDREFR, 0x00400016 @ 2d KxFREE & APD deasserted, SLFRSH asserted ++ ++ @ Developers Manual: in systems containing Synchronous Static Memory, write ++ @ to SXCNFG, including the enable bits. ++ @.long SXCNFG, 0x00000000 @ no Synchronous Static Memory ++ ++ @ Assert K1RUN and K2RUN and configure K1DB2 and K2DB2 ++ .long MDREFR, 0x00450016 @ 4a ++ .long MDREFR, 0x00050016 @ 4b deassert SLFRFH ++ .long MDREFR, 0x00058016 @ 4c assert E1PIN ++ .long MDCNFG, 0x0A000AC8 @ 4d without DE0/DE1 (6-10) ++ .long 0,0 ++ ++oscr_addr: ++ .long OSCR ++rcsr_addr: ++ .long RCSR ++pspr_addr: ++ .long PSPR ++ ++ ++@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ ++ ++ ++MemTable2: ++ .long MDCNFG, 0x0A000ACB @ 4d with DE0/DE1 ++ .long MDMRS, 0x00000000 @ 4h ++ .long MDREFR, 0x00118016 @ 5 (optional) turn APD on ++ .long 0x17C0002C, 0x00000011 @ MNCI: enable FFUART driver ++ .long 0x17c00034, 0x00000000 @ MNCI: enable flash write ++ .long 0x17c00028, 0x00000000 @ MNCI: turn off CF-Card enable ++ .long 0x17c00014, 0x00000000 @ MNCI: turn off CF-Card power ++ .long 0x10000000, 0x0000d803 @ MNCI: disable all LEDs, SCANNER_WAKE & SCANNER_TRIG on ++@ .long 0x10000000, 0x0000d80b @ MNCI: disable all LEDs, SCANNER_WAKE, SCANNER_TRIG & UARTB on ++ .long 0,0 diff --git a/packages/u-boot/u-boot-1.1.2/u-boot-1.1.2-neon.patch b/packages/u-boot/u-boot-1.1.2/u-boot-1.1.2-neon.patch new file mode 100644 index 0000000000..ed959d43d8 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.2/u-boot-1.1.2-neon.patch @@ -0,0 +1,19204 @@ +diff -u -r --new-file u-boot-1.1.2/board/bd2003/bd2003.c u-boot-1.1.2-neon/board/bd2003/bd2003.c +--- u-boot-1.1.2/board/bd2003/bd2003.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/bd2003/bd2003.c 2007-08-11 21:07:19.000000000 +0200 +@@ -0,0 +1,94 @@ ++/* ++ * (C) Copyright 2002 ++ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net ++ * ++ * (C) Copyright 2002 ++ * Sysgo Real-Time Solutions, GmbH ++ * Marius Groeger ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ------------------------------------------------------------------------- */ ++/* ++ * LCD panel declarations ++ */ ++ ++vidinfo_t panel_info = { ++ vl_col: 1024, //this is corrected in SetPanelInfo ++ vl_row: 768, ++ vl_bpix: LCD_BPP, ++ vl_lcd_line_length: (320 * NBITS(LCD_BPP) ) >> 3 ++}; ++ ++void disable_lcd_panel( void ) ++{ ++} ++ ++ ++/* ------------------------------------------------------------------------- */ ++ ++ ++/* ++ * Miscelaneous platform dependent initialisations ++ */ ++ ++int board_init (void) ++{ ++ DECLARE_GLOBAL_DATA_PTR; ++ ++ /* memory and cpu-speed are setup before relocation */ ++ /* so we do _nothing_ here */ ++ ++ /* arch number of Neon Board */ ++ gd->bd->bi_arch_number = MACH_TYPE_BD2003 ; ++ ++ /* adress of boot parameters */ ++ gd->bd->bi_boot_params = 0xa0000100; ++ ++ return 0; ++} ++ ++int board_late_init(void) ++{ ++ setenv("stdout", "serial"); ++ setenv("stderr", "serial"); ++ return 0; ++} ++ ++ ++int dram_init (void) ++{ ++ DECLARE_GLOBAL_DATA_PTR; ++ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; ++ ++ return 0; ++} +diff -u -r --new-file u-boot-1.1.2/board/bd2003/config.mk u-boot-1.1.2-neon/board/bd2003/config.mk +--- u-boot-1.1.2/board/bd2003/config.mk 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/bd2003/config.mk 2007-08-11 21:07:19.000000000 +0200 +@@ -0,0 +1,4 @@ ++#TEXT_BASE = 0xa1700000 ++TEXT_BASE = 0xA1F00000 ++#TEXT_BASE = 0 ++PXALCD = 1 +diff -u -r --new-file u-boot-1.1.2/board/bd2003/.cvsignore u-boot-1.1.2-neon/board/bd2003/.cvsignore +--- u-boot-1.1.2/board/bd2003/.cvsignore 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/bd2003/.cvsignore 2007-08-11 21:07:19.000000000 +0200 +@@ -0,0 +1,2 @@ ++.depend ++ +diff -u -r --new-file u-boot-1.1.2/board/bd2003/flash.c u-boot-1.1.2-neon/board/bd2003/flash.c +--- u-boot-1.1.2/board/bd2003/flash.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/bd2003/flash.c 2007-08-11 21:07:19.000000000 +0200 +@@ -0,0 +1,477 @@ ++/* ++ * (C) Copyright 2001 ++ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net ++ * ++ * (C) Copyright 2001 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include "lcd.h" ++ ++flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ ++ ++/* Board support for 1 or 2 flash devices */ ++#define FLASH_PORT_WIDTH32 ++#undef FLASH_PORT_WIDTH16 ++ ++#ifdef FLASH_PORT_WIDTH16 ++#define FLASH_PORT_WIDTH ushort ++#define FLASH_PORT_WIDTHV vu_short ++#define SWAP(x) __swab16(x) ++#else ++#define FLASH_PORT_WIDTH ulong ++#define FLASH_PORT_WIDTHV vu_long ++#define SWAP(x) __swab32(x) ++#endif ++ ++#define FPW FLASH_PORT_WIDTH ++#define FPWV FLASH_PORT_WIDTHV ++ ++#define mb() __asm__ __volatile__ ("" : : : "memory") ++ ++/*----------------------------------------------------------------------- ++ * Functions ++ */ ++static ulong flash_get_size (FPW *addr, flash_info_t *info); ++static int write_data (flash_info_t *info, ulong dest, FPW data); ++static void flash_get_offsets (ulong base, flash_info_t *info); ++void inline spin_wheel_init(ulong addr, ulong cnt); ++void inline spin_wheel_done( int worked ); ++void inline spin_wheel (ulong numleft); ++ ++/*----------------------------------------------------------------------- ++ */ ++ulong bases[] = {PHYS_FLASH_1,PHYS_FLASH_2,1}; ++unsigned long flash_init (void) ++{ ++ int i=0; ++ int j=0; ++ ulong size = 0; ++ ulong base; ++ ++ while (i < CFG_MAX_FLASH_BANKS) { ++ base = bases[j++]; ++ flash_info[i].start[0] = 0; ++ if (base & 1) break; ++ if (flash_get_size ((FPW *) base, &flash_info[i])) { ++ flash_get_offsets (base, &flash_info[i]); ++ size += flash_info[i].size; ++ i++; ++ } ++ else { ++printf( "error reading flash size\n" ); ++ } ++ } ++ if (size>0) { ++ base = flash_info[0].start[0]; ++ // Protect monitor and environment sectors ++ flash_protect ( FLAG_PROTECT_SET, ++ base, ++ base + monitor_flash_len - 1, ++ &flash_info[0] ); ++ ++ flash_protect ( FLAG_PROTECT_SET, ++ base+CFG_ENV_OFFSET, ++ base+CFG_ENV_OFFSET + CFG_ENV_SIZE - 1, &flash_info[0] ); ++ } ++ ++ return size; ++} ++ ++/*----------------------------------------------------------------------- ++ */ ++static void flash_get_offsets (ulong base, flash_info_t *info) ++{ ++ int i; ++ ++ if (info->flash_id == FLASH_UNKNOWN) { ++ return; ++ } ++ ++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { ++ for (i = 0; i < info->sector_count; i++) { ++ info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); ++ info->protect[i] = 0; ++ } ++ } ++} ++ ++/*----------------------------------------------------------------------- ++ */ ++void flash_print_info (flash_info_t *info) ++{ ++ int i; ++ ++ if (info->flash_id == FLASH_UNKNOWN) { ++ printf ("missing or unknown FLASH type\n"); ++ return; ++ } ++ ++ switch (info->flash_id & FLASH_VENDMASK) { ++ case FLASH_MAN_INTEL: ++ printf ("INTEL "); ++ break; ++ default: ++ printf ("Unknown Vendor "); ++ break; ++ } ++ ++ switch (info->flash_id & FLASH_TYPEMASK) { ++ case FLASH_28F128J3A: ++ printf ("28F128J3A\n"); ++ break; ++ default: ++ printf ("Unknown Chip Type\n"); ++ break; ++ } ++ ++ printf (" Size: %ld MB in %d Sectors\n", ++ info->size >> 20, info->sector_count); ++ ++ printf (" Sector Start Addresses:"); ++ for (i = 0; i < info->sector_count; ++i) { ++ if ((i % 5) == 0) ++ printf ("\n "); ++ printf (" %08lX%s", ++ info->start[i], ++ info->protect[i] ? " (RO)" : " "); ++ } ++ printf ("\n"); ++ return; ++} ++ ++/* ++ * The following code cannot be run from FLASH! ++ */ ++static ulong flash_get_size (FPW *addr, flash_info_t *info) ++{ ++ volatile FPW value; ++ volatile unsigned long *mc = (unsigned long *)MEMORY_CONTROL_BASE; ++ unsigned long val = 1<<3; ++ ++ info->flash_id = FLASH_UNKNOWN; ++ info->sector_count = 0; ++ info->size = 0; ++ ++ if (((ulong)addr) > 0x14000000) return 0; ++ val = mc[(MSC0>>2) +(((ulong)addr)>>27)]; ++ if (((ulong)addr) & 0x04000000) val = val>>16; ++ if ( val & (1<<3)) return 0; //if 16 bit bus then return ++ ++ /* Write auto select command: read Manufacturer ID */ ++ addr[0x5555] = (FPW) 0x00AA00AA; ++ addr[0x2AAA] = (FPW) 0x00550055; ++ addr[0x5555] = (FPW) 0x00900090; ++ ++ mb (); ++ value = addr[0]; ++ ++ switch (value) { ++ ++ case (FPW) 0: ++ case (FPW) INTEL_MANUFACT & 0xFF0000 : ++ case (FPW) INTEL_MANUFACT & 0x0000FF : ++ case (FPW) INTEL_MANUFACT: ++ info->flash_id = FLASH_MAN_INTEL; ++ break; ++ ++ default: ++printf( "Invalid flash manufacturer %x\n", value ); ++ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ ++ return (0); /* no or unknown flash */ ++ } ++ ++ mb (); ++ value = addr[1]; /* device ID */ ++ ++ switch (value) { ++ ++ case (FPW) 0: ++ case (FPW) INTEL_ID_28F128J3A & 0xFF0000 : ++ case (FPW) INTEL_ID_28F128J3A & 0x0000FF : ++ case (FPW) INTEL_ID_28F128J3A: ++ info->flash_id += FLASH_28F128J3A; ++ info->sector_count = 128; ++ info->size = 0x02000000; ++ break; /* => 16 MB */ ++ ++ default: ++printf( "Unknown flash device %x\n", value ); ++ info->flash_id = FLASH_UNKNOWN; ++ break; ++ } ++ ++ if (info->sector_count > CFG_MAX_FLASH_SECT) { ++ printf ("** ERROR: sector count %d > max (%d) **\n", ++ info->sector_count, CFG_MAX_FLASH_SECT); ++ info->sector_count = CFG_MAX_FLASH_SECT; ++ } ++ ++ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ ++ ++ return (info->size); ++} ++ ++ ++/*----------------------------------------------------------------------- ++ */ ++ ++int flash_erase (flash_info_t *info, int s_first, int s_last) ++{ ++ int flag, prot, sect; ++ ulong type, start, last; ++ int rcode = 0; ++ ++ if ((s_first < 0) || (s_first > s_last)) { ++ if (info->flash_id == FLASH_UNKNOWN) { ++ printf ("- missing\n"); ++ } else { ++ printf ("- no sectors to erase\n"); ++ } ++ return 1; ++ } ++ ++ type = (info->flash_id & FLASH_VENDMASK); ++ if ((type != FLASH_MAN_INTEL)) { ++ printf ("Can't erase unknown flash type %08lx - aborted\n", ++ info->flash_id); ++ return 1; ++ } ++ ++ prot = 0; ++ for (sect = s_first; sect <= s_last; ++sect) { ++ if (info->protect[sect]) { ++ prot++; ++ } ++ } ++ ++ if (prot) { ++ printf ("- Warning: %d protected sectors will not be erased!\n", ++ prot); ++ } else { ++ printf ("\n"); ++ } ++ ++ start = get_timer (0); ++ last = start; ++ ++ /* Disable interrupts which might cause a timeout here */ ++ flag = disable_interrupts (); ++ ++ /* Start erase on unprotected sectors */ ++ for (sect = s_first; sect <= s_last; sect++) { ++ if (info->protect[sect] == 0) { /* not protected */ ++ char temp[80]; ++ FPWV *addr = (FPWV *) (info->start[sect]); ++ FPW status; ++ ++ sprintf (temp, "Erasing sector %2d ... \r", sect); ++ lcd_puts( temp ); ++ ++ /* arm simple, non interrupt dependent timer */ ++ reset_timer_masked (); ++ ++ *addr = (FPW) 0x00500050; /* clear status register */ ++ *addr = (FPW) 0x00200020; /* erase setup */ ++ *addr = (FPW) 0x00D000D0; /* erase confirm */ ++ ++ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { ++ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { ++ printf ("Timeout\n"); ++ *addr = (FPW) 0x00B000B0; /* suspend erase */ ++ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ ++ rcode = 1; ++ break; ++ } ++ } ++ ++ *addr = 0x00500050; /* clear status register cmd. */ ++ *addr = 0x00FF00FF; /* resest to read mode */ ++ } ++ } ++ lcd_puts( "\r\n" ); ++ return rcode; ++} ++ ++/*----------------------------------------------------------------------- ++ * Copy memory to flash, returns: ++ * 0 - OK ++ * 1 - write timeout ++ * 2 - Flash not erased ++ * 4 - Flash not identified ++ */ ++ ++int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) ++{ ++ ulong cp, wp; ++ FPW data; ++ int count, i, l, rc, port_width; ++ ++ rc = 0 ; ++ if (info->flash_id == FLASH_UNKNOWN) { ++ return 4; ++ } ++/* get lower word aligned address */ ++#ifdef FLASH_PORT_WIDTH16 ++ wp = (addr & ~1); ++ port_width = 2; ++#else ++ wp = (addr & ~3); ++ port_width = 4; ++#endif ++ ++ spin_wheel_init(addr,cnt); ++ ++ /* ++ * handle unaligned start bytes ++ */ ++ if ((l = addr - wp) != 0) { ++ data = 0; ++ for (i = 0, cp = wp; i < l; ++i, ++cp) { ++ data = (data << 8) | (*(uchar *) cp); ++ } ++ for (; i < port_width && cnt > 0; ++i) { ++ data = (data << 8) | *src++; ++ --cnt; ++ ++cp; ++ } ++ for (; cnt == 0 && i < port_width; ++i, ++cp) { ++ data = (data << 8) | (*(uchar *) cp); ++ } ++ ++ if ((rc = write_data (info, wp, SWAP (data))) != 0) { ++ goto out; ++ } ++ wp += port_width; ++ } ++ ++ /* ++ * handle word aligned part ++ */ ++ count = 0; ++ while (cnt >= port_width) { ++ data = 0; ++ for (i = 0; i < port_width; ++i) { ++ data = (data << 8) | *src++; ++ } ++ if ((rc = write_data (info, wp, SWAP (data))) != 0) { ++ goto out; ++ } ++ wp += port_width; ++ cnt -= port_width; ++ if (count++ > 0x800) { ++ spin_wheel (cnt); ++ count = 0; ++ } ++ } ++ ++ if (cnt) { ++ /* ++ * handle unaligned tail bytes ++ */ ++ data = 0; ++ for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { ++ data = (data << 8) | *src++; ++ --cnt; ++ } ++ for (; i < port_width; ++i, ++cp) { ++ data = (data << 8) | (*(uchar *) cp); ++ } ++ ++ rc = write_data (info, wp, SWAP (data)); ++ } ++ ++out: ++ spin_wheel_done(0 == rc); ++ return rc ; ++} ++ ++/*----------------------------------------------------------------------- ++ * Write a word or halfword to Flash, returns: ++ * 0 - OK ++ * 1 - write timeout ++ * 2 - Flash not erased ++ */ ++static int write_data (flash_info_t *info, ulong dest, FPW data) ++{ ++ FPWV *addr = (FPWV *) dest; ++ FPW old = *addr ; ++ ulong status; ++ int flag; ++ ++ /* Check if Flash is (sufficiently) erased */ ++ if ((old & data) != data) { ++ printf ("not erased at %08lx (%lx)\n", (ulong) addr, old); ++ return (2); ++ } ++ ++ if( old != data ) ++ { ++ /* Disable interrupts which might cause a timeout here */ ++ flag = disable_interrupts (); ++ ++ *addr = (FPW) 0x00400040; /* write setup */ ++ *addr = data; ++ ++ /* arm simple, non interrupt dependent timer */ ++ reset_timer_masked (); ++ ++ /* wait while polling the status register */ ++ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { ++ if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { ++ *addr = (FPW) 0x00FF00FF; /* restore read mode */ ++ return (1); ++ } ++ } ++ *addr = (FPW) 0x00FF00FF; /* restore read mode */ ++ } /* need to program? */ ++ ++ ++ return (0); ++} ++ ++void inline spin_wheel_init(ulong addr, ulong cnt) ++{ ++ char temp[80]; ++ sprintf( temp, ++ "\nprogramming flash\n" ++ "%08lx->%08lx\n" ++ " ", addr, cnt ); ++ lcd_puts( temp ); ++} ++ ++void inline spin_wheel_done( int worked ) ++{ ++ if( worked ) ++ spin_wheel(0); ++ lcd_puts( worked ? "\ncompleted.\n" : "\nfailed!\n" ); ++} ++ ++void inline spin_wheel( ulong numleft ) ++{ ++ char temp[40]; ++ sprintf( temp, "\r %08lx", numleft ); ++ lcd_puts( temp ); ++} +diff -u -r --new-file u-boot-1.1.2/board/bd2003/init.script u-boot-1.1.2-neon/board/bd2003/init.script +--- u-boot-1.1.2/board/bd2003/init.script 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/bd2003/init.script 2007-08-11 21:07:19.000000000 +0200 +@@ -0,0 +1,42 @@ ++if fatload mmc 0 a0000000 logo.bmp ; then ++ bmp info a0000000 ; ++ bmp display a0000000 ; ++else ++ lecho "No logo present" ; ++fi ++ ++if fatload mmc 0 a2000000 uimage ; then ++ lecho 'load Linux' ++ if fatload mmc 0 a2200000 mmcinitrd.u-boot ; then ++ echo 'using initrd' ; ++ lecho "Booting Linux" ++ set bootargs root=/dev/ram0 console=ttyS0,115200 debug=7 mtdparts=phys_mapped_flash:1024k(armboot),256k(params),-(rootfs1) ++ bootm a2000000 a2200000 ++ else ++ echo 'testing cramfs img' ; ++ if fatload mmc 0 a2200000 cramfs.img ; then ++ if cmp.b 00140000 a2200000 $filesize ; then ++ echo 'cramfs images match' ; ++ else ++ lecho 'filesystems differ...' ; ++ protect off all ; ++ erase 00140000 01ffffff ; ++ cp.b a2200000 00140000 $filesize ; ++ fi ++ ++ set bootargs console=ttyS0,115200 debug=7 mtdparts=phys_mapped_flash:1024k(armboot),256k(params),-(rootfs1) root=/dev/mtdblock3 rootfstype=cramfs ++ lecho "Booting Linux" ++ bootm a2000000 ++ fi ++ fi ++else ++ echo "No Linux kernel" ; ++fi ++ ++lecho 'No Linux, try CE' ++ ++if fatload mmc 0 A0030000 nk.nb0 ; then ++ g A0030000 ; ++else ++ echo "No WinCE image" ; ++fi +diff -u -r --new-file u-boot-1.1.2/board/bd2003/Makefile u-boot-1.1.2-neon/board/bd2003/Makefile +--- u-boot-1.1.2/board/bd2003/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/bd2003/Makefile 2007-08-11 21:07:19.000000000 +0200 +@@ -0,0 +1,48 @@ ++ ++# ++# (C) Copyright 2000 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = lib$(BOARD).a ++ ++OBJS := bd2003.o flash.o ++SOBJS := memsetup.o ++ ++$(LIB): $(OBJS) $(SOBJS) ++ $(AR) crv $@ $(OBJS) $(SOBJS) ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak .depend ++ ++######################################################################### ++ ++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) ++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ ++ ++-include .depend ++ ++######################################################################### +diff -u -r --new-file u-boot-1.1.2/board/bd2003/memsetup.S u-boot-1.1.2-neon/board/bd2003/memsetup.S +--- u-boot-1.1.2/board/bd2003/memsetup.S 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/bd2003/memsetup.S 2007-08-11 21:07:19.000000000 +0200 +@@ -0,0 +1,64 @@ ++/* ++ * Most of this taken from Redboot hal_platform_setup.h with cleanup ++ * ++ * NOTE: I haven't clean this up considerably, just enough to get it ++ * running. See hal_platform_setup.h for the source. See ++ * board/cradle/memsetup.S for another PXA250 setup that is ++ * much cleaner. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++ ++#define BAUDRATE 115200 ++#include ++#include ++#include ++#include ++ ++DRAM_SIZE: .long CFG_DRAM_SIZE ++ ++/* wait for coprocessor write complete */ ++ .macro CPWAIT reg ++ mrc p15,0,\reg,c2,c0,0 ++ mov \reg,\reg ++ sub pc,pc,#4 ++ .endm ++ ++ ++/* ++ * Memory setup ++ */ ++ ++.globl memsetup ++memsetup: ++ ++ mov r10, lr ++ ++ InitCS0_CS1 r0,sp ++ InitGPIO r0,sp ++ InitIC_Clocks r0,sp ++ InitUART r0,sp,UART_BASE,BAUDRATE ++ InitUART r0,sp,UART_BASE+0x600000,9600 ++ InitChangeCPUSpeed r0 ++ InitMemory r0,sp,r1 ++ ++ mov pc, lr +diff -u -r --new-file u-boot-1.1.2/board/bd2003/u-boot.lds u-boot-1.1.2-neon/board/bd2003/u-boot.lds +--- u-boot-1.1.2/board/bd2003/u-boot.lds 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/bd2003/u-boot.lds 2007-08-11 21:07:19.000000000 +0200 +@@ -0,0 +1,56 @@ ++/* ++ * (C) Copyright 2000 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++OUTPUT_ARCH(arm) ++ENTRY(_start) ++SECTIONS ++{ ++ . = 0x00000000; ++ ++ . = ALIGN(4); ++ .text : ++ { ++ cpu/pxa/start.o (.text) ++ cpu/pxa/ministart.o (.text) ++ *(.text) ++ } ++ ++ . = ALIGN(4); ++ .rodata : { *(.rodata) } ++ ++ . = ALIGN(4); ++ .data : { *(.data) } ++ ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss : { *(.bss) } ++ _end = .; ++} +diff -u -r --new-file u-boot-1.1.2/board/bd2003/u-bootmini.lds u-boot-1.1.2-neon/board/bd2003/u-bootmini.lds +--- u-boot-1.1.2/board/bd2003/u-bootmini.lds 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/bd2003/u-bootmini.lds 2007-08-11 21:07:19.000000000 +0200 +@@ -0,0 +1,56 @@ ++/* ++ * (C) Copyright 2000 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++OUTPUT_ARCH(arm) ++ENTRY(StartUp) ++SECTIONS ++{ ++ . = 0x00000000; ++ ++ . = ALIGN(4); ++ .text : ++ { ++ cpu/pxa/minidebug.o (.text) ++ cpu/pxa/ministart.o (.text) ++ *(.text) ++ } ++ ++ . = ALIGN(4); ++ .rodata : { *(.rodata) } ++ ++ . = ALIGN(4); ++ .data : { *(.data) } ++ ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss : { *(.bss) } ++ _end = .; ++} +diff -u -r --new-file u-boot-1.1.2/board/halogen/config.mk u-boot-1.1.2-neon/board/halogen/config.mk +--- u-boot-1.1.2/board/halogen/config.mk 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/halogen/config.mk 2007-08-11 21:07:19.000000000 +0200 +@@ -0,0 +1,4 @@ ++#TEXT_BASE = 0xa1700000 ++TEXT_BASE = 0xA1F00000 ++#TEXT_BASE = 0 ++PXALCD = 1 +diff -u -r --new-file u-boot-1.1.2/board/halogen/.cvsignore u-boot-1.1.2-neon/board/halogen/.cvsignore +--- u-boot-1.1.2/board/halogen/.cvsignore 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/halogen/.cvsignore 2007-08-11 21:07:19.000000000 +0200 +@@ -0,0 +1,2 @@ ++.depend ++ +diff -u -r --new-file u-boot-1.1.2/board/halogen/flash.c u-boot-1.1.2-neon/board/halogen/flash.c +--- u-boot-1.1.2/board/halogen/flash.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/halogen/flash.c 2007-08-11 21:07:19.000000000 +0200 +@@ -0,0 +1,482 @@ ++/* ++ * (C) Copyright 2001 ++ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net ++ * ++ * (C) Copyright 2001 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include "lcd.h" ++ ++flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ ++ ++/* Board support for 1 or 2 flash devices */ ++#define FLASH_PORT_WIDTH32 ++#undef FLASH_PORT_WIDTH16 ++ ++#ifdef FLASH_PORT_WIDTH16 ++#define FLASH_PORT_WIDTH ushort ++#define FLASH_PORT_WIDTHV vu_short ++#define SWAP(x) __swab16(x) ++#else ++#define FLASH_PORT_WIDTH ulong ++#define FLASH_PORT_WIDTHV vu_long ++#define SWAP(x) __swab32(x) ++#endif ++ ++#define FPW FLASH_PORT_WIDTH ++#define FPWV FLASH_PORT_WIDTHV ++ ++#define mb() __asm__ __volatile__ ("" : : : "memory") ++ ++/*----------------------------------------------------------------------- ++ * Functions ++ */ ++static ulong flash_get_size (FPW *addr, flash_info_t *info); ++static int write_data (flash_info_t *info, ulong dest, FPW data); ++static void flash_get_offsets (ulong base, flash_info_t *info); ++void inline spin_wheel_init(ulong addr, ulong cnt); ++void inline spin_wheel_done( int worked ); ++void inline spin_wheel (ulong numleft); ++ ++/*----------------------------------------------------------------------- ++ */ ++ulong bases[] = {PHYS_FLASH_1,PHYS_FLASH_2,1}; ++unsigned long flash_init (void) ++{ ++ int i=0; ++ int j=0; ++ ulong size = 0; ++ ulong base; ++ ++ while (i < CFG_MAX_FLASH_BANKS) { ++ base = bases[j++]; ++ flash_info[i].start[0] = 0; ++ if (base & 1) break; ++ if (flash_get_size ((FPW *) base, &flash_info[i])) { ++ flash_get_offsets (base, &flash_info[i]); ++ size += flash_info[i].size; ++ i++; ++ } ++ else { ++printf( "error reading flash size\n" ); ++ } ++ } ++ if (size>0) { ++ base = flash_info[0].start[0]; ++ // Protect monitor and environment sectors ++ flash_protect ( FLAG_PROTECT_SET, ++ base, ++ base + monitor_flash_len - 1, ++ &flash_info[0] ); ++ ++ flash_protect ( FLAG_PROTECT_SET, ++ base+CFG_ENV_OFFSET, ++ base+CFG_ENV_OFFSET + CFG_ENV_SIZE - 1, &flash_info[0] ); ++ } ++ ++ return size; ++} ++ ++/*----------------------------------------------------------------------- ++ */ ++static void flash_get_offsets (ulong base, flash_info_t *info) ++{ ++ int i; ++ ++ if (info->flash_id == FLASH_UNKNOWN) { ++ return; ++ } ++ ++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { ++ for (i = 0; i < info->sector_count; i++) { ++ info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); ++ info->protect[i] = 0; ++ } ++ } ++} ++ ++/*----------------------------------------------------------------------- ++ */ ++void flash_print_info (flash_info_t *info) ++{ ++ int i; ++ ++ if (info->flash_id == FLASH_UNKNOWN) { ++ printf ("missing or unknown FLASH type\n"); ++ return; ++ } ++ ++ switch (info->flash_id & FLASH_VENDMASK) { ++ case FLASH_MAN_INTEL: ++ printf ("INTEL "); ++ break; ++ default: ++ printf ("Unknown Vendor "); ++ break; ++ } ++ ++ switch (info->flash_id & FLASH_TYPEMASK) { ++ case FLASH_28F128J3A: ++ printf ("28F128J3A\n"); ++ break; ++ default: ++ printf ("Unknown Chip Type\n"); ++ break; ++ } ++ ++ printf (" Size: %ld MB in %d Sectors\n", ++ info->size >> 20, info->sector_count); ++ ++ printf (" Sector Start Addresses:"); ++ for (i = 0; i < info->sector_count; ++i) { ++ if ((i % 5) == 0) ++ printf ("\n "); ++ printf (" %08lX%s", ++ info->start[i], ++ info->protect[i] ? " (RO)" : " "); ++ } ++ printf ("\n"); ++ return; ++} ++ ++/* ++ * The following code cannot be run from FLASH! ++ */ ++static ulong flash_get_size (FPW *addr, flash_info_t *info) ++{ ++ volatile FPW value; ++ volatile unsigned long *mc = (unsigned long *)MEMORY_CONTROL_BASE; ++ unsigned long val = 1<<3; ++ ++ info->flash_id = FLASH_UNKNOWN; ++ info->sector_count = 0; ++ info->size = 0; ++ ++ if (((ulong)addr) > 0x14000000) return 0; ++ val = mc[(MSC0>>2) +(((ulong)addr)>>27)]; ++ if (((ulong)addr) & 0x04000000) val = val>>16; ++ if ( val & (1<<3)) return 0; //if 16 bit bus then return ++ ++ /* Write auto select command: read Manufacturer ID */ ++ addr[0x5555] = (FPW) 0x00AA00AA; ++ addr[0x2AAA] = (FPW) 0x00550055; ++ addr[0x5555] = (FPW) 0x00900090; ++ ++ mb (); ++ value = addr[0]; ++ ++ switch (value) { ++ ++ case (FPW) 0: ++ case (FPW) STM_MANUFACT: ++ case (FPW) INTEL_MANUFACT & 0xFF0000 : ++ case (FPW) INTEL_MANUFACT & 0x0000FF : ++ case (FPW) INTEL_MANUFACT: ++ info->flash_id = FLASH_MAN_INTEL; ++ break; ++ ++ default: ++printf( "Invalid flash manufacturer %x\n", value ); ++ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ ++ return (0); /* no or unknown flash */ ++ } ++ ++ mb (); ++ value = addr[1]; /* device ID */ ++ ++ switch (value) { ++ ++ case (FPW) 0: ++ case (FPW) INTEL_ID_28F128J3A & 0xFF0000 : ++ case (FPW) INTEL_ID_28F128J3A & 0x0000FF : ++ case (FPW) INTEL_ID_28F128J3A: ++ info->flash_id += FLASH_28F128J3A; ++ info->sector_count = 128; ++ info->size = 0x01000000; ++ break; /* => 16 MB x 1 */ ++ case (FPW) INTEL_ID_28F320J3A: ++ info->flash_id += FLASH_28F320J3A; ++ info->sector_count = 32 ; ++ info->size = 0x400000 ; ++ break; /* => 4 MB x 1 */ ++ default: ++printf( "Unknown flash device %x\n", value ); ++ info->flash_id = FLASH_UNKNOWN; ++ break; ++ } ++ ++ if (info->sector_count > CFG_MAX_FLASH_SECT) { ++ printf ("** ERROR: sector count %d > max (%d) **\n", ++ info->sector_count, CFG_MAX_FLASH_SECT); ++ info->sector_count = CFG_MAX_FLASH_SECT; ++ } ++ ++ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ ++ ++ return (info->size); ++} ++ ++ ++/*----------------------------------------------------------------------- ++ */ ++ ++int flash_erase (flash_info_t *info, int s_first, int s_last) ++{ ++ int flag, prot, sect; ++ ulong type, start, last; ++ int rcode = 0; ++ ++ if ((s_first < 0) || (s_first > s_last)) { ++ if (info->flash_id == FLASH_UNKNOWN) { ++ printf ("- missing\n"); ++ } else { ++ printf ("- no sectors to erase\n"); ++ } ++ return 1; ++ } ++ ++ type = (info->flash_id & FLASH_VENDMASK); ++ if ((type != FLASH_MAN_INTEL)) { ++ printf ("Can't erase unknown flash type %08lx - aborted\n", ++ info->flash_id); ++ return 1; ++ } ++ ++ prot = 0; ++ for (sect = s_first; sect <= s_last; ++sect) { ++ if (info->protect[sect]) { ++ prot++; ++ } ++ } ++ ++ if (prot) { ++ printf ("- Warning: %d protected sectors will not be erased!\n", ++ prot); ++ } else { ++ printf ("\n"); ++ } ++ ++ start = get_timer (0); ++ last = start; ++ ++ /* Disable interrupts which might cause a timeout here */ ++ flag = disable_interrupts (); ++ ++ /* Start erase on unprotected sectors */ ++ for (sect = s_first; sect <= s_last; sect++) { ++ if (info->protect[sect] == 0) { /* not protected */ ++ char temp[80]; ++ FPWV *addr = (FPWV *) (info->start[sect]); ++ FPW status; ++ ++ sprintf (temp, "Erasing sector %2d ... \r", sect); ++ lcd_puts( temp ); ++ ++ /* arm simple, non interrupt dependent timer */ ++ reset_timer_masked (); ++ ++ *addr = (FPW) 0x00500050; /* clear status register */ ++ *addr = (FPW) 0x00200020; /* erase setup */ ++ *addr = (FPW) 0x00D000D0; /* erase confirm */ ++ ++ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { ++ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { ++ printf ("Timeout\n"); ++ *addr = (FPW) 0x00B000B0; /* suspend erase */ ++ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ ++ rcode = 1; ++ break; ++ } ++ } ++ ++ *addr = 0x00500050; /* clear status register cmd. */ ++ *addr = 0x00FF00FF; /* resest to read mode */ ++ } ++ } ++ lcd_puts( "\r\n" ); ++ return rcode; ++} ++ ++/*----------------------------------------------------------------------- ++ * Copy memory to flash, returns: ++ * 0 - OK ++ * 1 - write timeout ++ * 2 - Flash not erased ++ * 4 - Flash not identified ++ */ ++ ++int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) ++{ ++ ulong cp, wp; ++ FPW data; ++ int count, i, l, rc, port_width; ++ ++ rc = 0 ; ++ if (info->flash_id == FLASH_UNKNOWN) { ++ return 4; ++ } ++/* get lower word aligned address */ ++#ifdef FLASH_PORT_WIDTH16 ++ wp = (addr & ~1); ++ port_width = 2; ++#else ++ wp = (addr & ~3); ++ port_width = 4; ++#endif ++ ++ spin_wheel_init(addr,cnt); ++ ++ /* ++ * handle unaligned start bytes ++ */ ++ if ((l = addr - wp) != 0) { ++ data = 0; ++ for (i = 0, cp = wp; i < l; ++i, ++cp) { ++ data = (data << 8) | (*(uchar *) cp); ++ } ++ for (; i < port_width && cnt > 0; ++i) { ++ data = (data << 8) | *src++; ++ --cnt; ++ ++cp; ++ } ++ for (; cnt == 0 && i < port_width; ++i, ++cp) { ++ data = (data << 8) | (*(uchar *) cp); ++ } ++ ++ if ((rc = write_data (info, wp, SWAP (data))) != 0) { ++ goto out; ++ } ++ wp += port_width; ++ } ++ ++ /* ++ * handle word aligned part ++ */ ++ count = 0; ++ while (cnt >= port_width) { ++ data = 0; ++ for (i = 0; i < port_width; ++i) { ++ data = (data << 8) | *src++; ++ } ++ if ((rc = write_data (info, wp, SWAP (data))) != 0) { ++ goto out; ++ } ++ wp += port_width; ++ cnt -= port_width; ++ if (count++ > 0x800) { ++ spin_wheel (cnt); ++ count = 0; ++ } ++ } ++ ++ if (cnt) { ++ /* ++ * handle unaligned tail bytes ++ */ ++ data = 0; ++ for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { ++ data = (data << 8) | *src++; ++ --cnt; ++ } ++ for (; i < port_width; ++i, ++cp) { ++ data = (data << 8) | (*(uchar *) cp); ++ } ++ ++ rc = write_data (info, wp, SWAP (data)); ++ } ++ ++out: ++ spin_wheel_done(0 == rc); ++ return rc ; ++} ++ ++/*----------------------------------------------------------------------- ++ * Write a word or halfword to Flash, returns: ++ * 0 - OK ++ * 1 - write timeout ++ * 2 - Flash not erased ++ */ ++static int write_data (flash_info_t *info, ulong dest, FPW data) ++{ ++ FPWV *addr = (FPWV *) dest; ++ FPW old = *addr ; ++ ulong status; ++ int flag; ++ ++ /* Check if Flash is (sufficiently) erased */ ++ if ((old & data) != data) { ++ printf ("not erased at %08lx (%lx)\n", (ulong) addr, old); ++ return (2); ++ } ++ ++ if( old != data ) ++ { ++ /* Disable interrupts which might cause a timeout here */ ++ flag = disable_interrupts (); ++ ++ *addr = (FPW) 0x00400040; /* write setup */ ++ *addr = data; ++ ++ /* arm simple, non interrupt dependent timer */ ++ reset_timer_masked (); ++ ++ /* wait while polling the status register */ ++ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { ++ if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { ++ *addr = (FPW) 0x00FF00FF; /* restore read mode */ ++ return (1); ++ } ++ } ++ *addr = (FPW) 0x00FF00FF; /* restore read mode */ ++ } /* need to program? */ ++ ++ ++ return (0); ++} ++ ++void inline spin_wheel_init(ulong addr, ulong cnt) ++{ ++ char temp[80]; ++ sprintf( temp, ++ "\nprogramming flash\n" ++ "%08lx->%08lx\n" ++ " ", addr, cnt ); ++ lcd_puts( temp ); ++} ++ ++void inline spin_wheel_done( int worked ) ++{ ++ if( worked ) ++ spin_wheel(0); ++ lcd_puts( worked ? "\ncompleted.\n" : "\nfailed!\n" ); ++} ++ ++void inline spin_wheel( ulong numleft ) ++{ ++ char temp[40]; ++ sprintf( temp, "\r %08lx", numleft ); ++ lcd_puts( temp ); ++} +diff -u -r --new-file u-boot-1.1.2/board/halogen/halogen.c u-boot-1.1.2-neon/board/halogen/halogen.c +--- u-boot-1.1.2/board/halogen/halogen.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/halogen/halogen.c 2007-08-11 21:07:19.000000000 +0200 +@@ -0,0 +1,94 @@ ++/* ++ * (C) Copyright 2002 ++ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net ++ * ++ * (C) Copyright 2002 ++ * Sysgo Real-Time Solutions, GmbH ++ * Marius Groeger ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ------------------------------------------------------------------------- */ ++/* ++ * LCD panel declarations ++ */ ++ ++vidinfo_t panel_info = { ++ vl_col: 1024, //this is corrected in SetPanelInfo ++ vl_row: 768, ++ vl_bpix: LCD_BPP, ++ vl_lcd_line_length: (320 * NBITS(LCD_BPP) ) >> 3 ++}; ++ ++void disable_lcd_panel( void ) ++{ ++} ++ ++ ++/* ------------------------------------------------------------------------- */ ++ ++ ++/* ++ * Miscelaneous platform dependent initialisations ++ */ ++ ++int board_init (void) ++{ ++ DECLARE_GLOBAL_DATA_PTR; ++ ++ /* memory and cpu-speed are setup before relocation */ ++ /* so we do _nothing_ here */ ++ ++ /* arch number of Neon Board */ ++ gd->bd->bi_arch_number = MACH_TYPE_HALOGEN ; ++ ++ /* adress of boot parameters */ ++ gd->bd->bi_boot_params = 0xa0000100; ++ ++ return 0; ++} ++ ++int board_late_init(void) ++{ ++ setenv("stdout", "serial"); ++ setenv("stderr", "serial"); ++ return 0; ++} ++ ++ ++int dram_init (void) ++{ ++ DECLARE_GLOBAL_DATA_PTR; ++ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; ++ ++ return 0; ++} +diff -u -r --new-file u-boot-1.1.2/board/halogen/init.script u-boot-1.1.2-neon/board/halogen/init.script +--- u-boot-1.1.2/board/halogen/init.script 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/halogen/init.script 2007-08-11 21:07:19.000000000 +0200 +@@ -0,0 +1,42 @@ ++if fatload mmc 0 a0008000 logo*.bmp ; then ++ bmp info a0008000 ; ++ bmp display a0008000 ; ++else ++ lecho "No logo present" ; ++fi ++ ++if fatload mmc 0 a2000000 uim* ; then ++ lecho 'load Linux' ++ if fatload mmc 0 a2200000 mmcinitrd* ; then ++ echo 'using initrd' ; ++ lecho "Booting Linux" ++ set bootargs root=/dev/ram0 console=ttyS0,115200 debug=7 mtdparts=phys_mapped_flash:1024k(armboot),256k(params),-(rootfs1) ++ bootm a2000000 a2200000 ++ else ++ echo 'testing cramfs img' ; ++ if fatload mmc 0 a2200000 cramfs* ; then ++ if cmp.b 00140000 a2200000 $filesize ; then ++ echo 'cramfs images match' ; ++ else ++ lecho 'filesystems differ...' ; ++ protect off all ; ++ erase 00140000 01ffffff ; ++ cp.b a2200000 00140000 $filesize ; ++ fi ++ ++ set bootargs console=ttyS0,115200 debug=7 mtdparts=phys_mapped_flash:1024k(armboot),256k(params),-(rootfs1) root=/dev/mtdblock3 rootfstype=cramfs ++ lecho "Booting Linux" ++ bootm a2000000 ++ fi ++ fi ++else ++ echo "No Linux kernel" ; ++fi ++ ++lecho 'No Linux, try CE' ++ ++if fatload mmc 0 A0030000 nk*.nb0 ; then ++ g A0030000 ; ++else ++ echo "No WinCE image" ; ++fi +diff -u -r --new-file u-boot-1.1.2/board/halogen/Makefile u-boot-1.1.2-neon/board/halogen/Makefile +--- u-boot-1.1.2/board/halogen/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/halogen/Makefile 2007-08-11 21:07:19.000000000 +0200 +@@ -0,0 +1,48 @@ ++ ++# ++# (C) Copyright 2000 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = lib$(BOARD).a ++ ++OBJS := halogen.o flash.o ++SOBJS := memsetup.o ++ ++$(LIB): $(OBJS) $(SOBJS) ++ $(AR) crv $@ $(OBJS) $(SOBJS) ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak .depend ++ ++######################################################################### ++ ++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) ++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ ++ ++-include .depend ++ ++######################################################################### +diff -u -r --new-file u-boot-1.1.2/board/halogen/memsetup.S u-boot-1.1.2-neon/board/halogen/memsetup.S +--- u-boot-1.1.2/board/halogen/memsetup.S 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/halogen/memsetup.S 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,64 @@ ++/* ++ * Most of this taken from Redboot hal_platform_setup.h with cleanup ++ * ++ * NOTE: I haven't clean this up considerably, just enough to get it ++ * running. See hal_platform_setup.h for the source. See ++ * board/cradle/memsetup.S for another PXA250 setup that is ++ * much cleaner. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++ ++#define BAUDRATE 115200 ++#include ++#include ++#include ++#include ++ ++DRAM_SIZE: .long CFG_DRAM_SIZE ++ ++/* wait for coprocessor write complete */ ++ .macro CPWAIT reg ++ mrc p15,0,\reg,c2,c0,0 ++ mov \reg,\reg ++ sub pc,pc,#4 ++ .endm ++ ++ ++/* ++ * Memory setup ++ */ ++ ++.globl memsetup ++memsetup: ++ ++ mov r10, lr ++ ++ InitCS0_CS1 r0,sp ++ InitGPIO r0,sp ++ InitIC_Clocks r0,sp ++ InitUART r0,sp,UART_BASE,BAUDRATE ++ InitUART r0,sp,UART_BASE+0x600000,9600 ++ InitChangeCPUSpeed r0 ++ InitMemory r0,sp,r1 ++ ++ mov pc, lr +diff -u -r --new-file u-boot-1.1.2/board/halogen/u-boot.lds u-boot-1.1.2-neon/board/halogen/u-boot.lds +--- u-boot-1.1.2/board/halogen/u-boot.lds 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/halogen/u-boot.lds 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,56 @@ ++/* ++ * (C) Copyright 2000 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++OUTPUT_ARCH(arm) ++ENTRY(_start) ++SECTIONS ++{ ++ . = 0x00000000; ++ ++ . = ALIGN(4); ++ .text : ++ { ++ cpu/pxa/start.o (.text) ++ cpu/pxa/ministart.o (.text) ++ *(.text) ++ } ++ ++ . = ALIGN(4); ++ .rodata : { *(.rodata) } ++ ++ . = ALIGN(4); ++ .data : { *(.data) } ++ ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss : { *(.bss) } ++ _end = .; ++} +diff -u -r --new-file u-boot-1.1.2/board/halogen/u-bootmini.lds u-boot-1.1.2-neon/board/halogen/u-bootmini.lds +--- u-boot-1.1.2/board/halogen/u-bootmini.lds 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/halogen/u-bootmini.lds 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,56 @@ ++/* ++ * (C) Copyright 2000 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++OUTPUT_ARCH(arm) ++ENTRY(StartUp) ++SECTIONS ++{ ++ . = 0x00000000; ++ ++ . = ALIGN(4); ++ .text : ++ { ++ cpu/pxa/minidebug.o (.text) ++ cpu/pxa/ministart.o (.text) ++ *(.text) ++ } ++ ++ . = ALIGN(4); ++ .rodata : { *(.rodata) } ++ ++ . = ALIGN(4); ++ .data : { *(.data) } ++ ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss : { *(.bss) } ++ _end = .; ++} +diff -u -r --new-file u-boot-1.1.2/board/neon/config.mk u-boot-1.1.2-neon/board/neon/config.mk +--- u-boot-1.1.2/board/neon/config.mk 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/neon/config.mk 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,4 @@ ++#TEXT_BASE = 0xa1700000 ++TEXT_BASE = 0xA1F00000 ++#TEXT_BASE = 0 ++#PXALCD = 1 +diff -u -r --new-file u-boot-1.1.2/board/neon/.cvsignore u-boot-1.1.2-neon/board/neon/.cvsignore +--- u-boot-1.1.2/board/neon/.cvsignore 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/neon/.cvsignore 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,2 @@ ++.depend ++ +diff -u -r --new-file u-boot-1.1.2/board/neon/flash.c u-boot-1.1.2-neon/board/neon/flash.c +--- u-boot-1.1.2/board/neon/flash.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/neon/flash.c 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,482 @@ ++/* ++ * (C) Copyright 2001 ++ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net ++ * ++ * (C) Copyright 2001 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include "lcd.h" ++ ++flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ ++ ++/* Board support for 1 or 2 flash devices */ ++#define FLASH_PORT_WIDTH32 ++#undef FLASH_PORT_WIDTH16 ++ ++#ifdef FLASH_PORT_WIDTH16 ++#define FLASH_PORT_WIDTH ushort ++#define FLASH_PORT_WIDTHV vu_short ++#define SWAP(x) __swab16(x) ++#else ++#define FLASH_PORT_WIDTH ulong ++#define FLASH_PORT_WIDTHV vu_long ++#define SWAP(x) __swab32(x) ++#endif ++ ++#define FPW FLASH_PORT_WIDTH ++#define FPWV FLASH_PORT_WIDTHV ++ ++#define mb() __asm__ __volatile__ ("" : : : "memory") ++ ++/*----------------------------------------------------------------------- ++ * Functions ++ */ ++static ulong flash_get_size (FPW *addr, flash_info_t *info); ++static int write_data (flash_info_t *info, ulong dest, FPW data); ++static void flash_get_offsets (ulong base, flash_info_t *info); ++void inline spin_wheel_init(ulong addr, ulong cnt); ++void inline spin_wheel_done( int worked ); ++void inline spin_wheel (ulong numleft); ++ ++/*----------------------------------------------------------------------- ++ */ ++ulong bases[] = {PHYS_FLASH_1,PHYS_FLASH_2,1}; ++unsigned long flash_init (void) ++{ ++ int i=0; ++ int j=0; ++ ulong size = 0; ++ ulong base; ++ ++ while (i < CFG_MAX_FLASH_BANKS) { ++ base = bases[j++]; ++ flash_info[i].start[0] = 0; ++ if (base & 1) break; ++ if (flash_get_size ((FPW *) base, &flash_info[i])) { ++ flash_get_offsets (base, &flash_info[i]); ++ size += flash_info[i].size; ++ i++; ++ } ++ else { ++printf( "error reading flash size\n" ); ++ } ++ } ++ if (size>0) { ++ base = flash_info[0].start[0]; ++ // Protect monitor and environment sectors ++ flash_protect ( FLAG_PROTECT_SET, ++ base, ++ base + monitor_flash_len - 1, ++ &flash_info[0] ); ++ ++ flash_protect ( FLAG_PROTECT_SET, ++ base+CFG_ENV_OFFSET, ++ base+CFG_ENV_OFFSET + CFG_ENV_SIZE - 1, &flash_info[0] ); ++ } ++ ++ return size; ++} ++ ++/*----------------------------------------------------------------------- ++ */ ++static void flash_get_offsets (ulong base, flash_info_t *info) ++{ ++ int i; ++ ++ if (info->flash_id == FLASH_UNKNOWN) { ++ return; ++ } ++ ++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { ++ for (i = 0; i < info->sector_count; i++) { ++ info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); ++ info->protect[i] = 0; ++ } ++ } ++} ++ ++/*----------------------------------------------------------------------- ++ */ ++void flash_print_info (flash_info_t *info) ++{ ++ int i; ++ ++ if (info->flash_id == FLASH_UNKNOWN) { ++ printf ("missing or unknown FLASH type\n"); ++ return; ++ } ++ ++ switch (info->flash_id & FLASH_VENDMASK) { ++ case FLASH_MAN_INTEL: ++ printf ("INTEL "); ++ break; ++ default: ++ printf ("Unknown Vendor "); ++ break; ++ } ++ ++ switch (info->flash_id & FLASH_TYPEMASK) { ++ case FLASH_28F128J3A: ++ printf ("28F128J3A\n"); ++ break; ++ default: ++ printf ("Unknown Chip Type\n"); ++ break; ++ } ++ ++ printf (" Size: %ld MB in %d Sectors\n", ++ info->size >> 20, info->sector_count); ++ ++ printf (" Sector Start Addresses:"); ++ for (i = 0; i < info->sector_count; ++i) { ++ if ((i % 5) == 0) ++ printf ("\n "); ++ printf (" %08lX%s", ++ info->start[i], ++ info->protect[i] ? " (RO)" : " "); ++ } ++ printf ("\n"); ++ return; ++} ++ ++/* ++ * The following code cannot be run from FLASH! ++ */ ++static ulong flash_get_size (FPW *addr, flash_info_t *info) ++{ ++ volatile FPW value; ++ volatile unsigned long *mc = (unsigned long *)MEMORY_CONTROL_BASE; ++ unsigned long val = 1<<3; ++ ++ info->flash_id = FLASH_UNKNOWN; ++ info->sector_count = 0; ++ info->size = 0; ++ ++ if (((ulong)addr) > 0x14000000) return 0; ++ val = mc[(MSC0>>2) +(((ulong)addr)>>27)]; ++ if (((ulong)addr) & 0x04000000) val = val>>16; ++ if ( val & (1<<3)) return 0; //if 16 bit bus then return ++ ++ /* Write auto select command: read Manufacturer ID */ ++ addr[0x5555] = (FPW) 0x00AA00AA; ++ addr[0x2AAA] = (FPW) 0x00550055; ++ addr[0x5555] = (FPW) 0x00900090; ++ ++ mb (); ++ value = addr[0]; ++ ++ switch (value) { ++ ++ case (FPW) 0: ++ case (FPW) STM_MANUFACT: ++ case (FPW) INTEL_MANUFACT & 0xFF0000 : ++ case (FPW) INTEL_MANUFACT & 0x0000FF : ++ case (FPW) INTEL_MANUFACT: ++ info->flash_id = FLASH_MAN_INTEL; ++ break; ++ ++ default: ++printf( "Invalid flash manufacturer %x\n", value ); ++ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ ++ return (0); /* no or unknown flash */ ++ } ++ ++ mb (); ++ value = addr[1]; /* device ID */ ++ ++ switch (value) { ++ ++ case (FPW) 0: ++ case (FPW) INTEL_ID_28F128J3A & 0xFF0000 : ++ case (FPW) INTEL_ID_28F128J3A & 0x0000FF : ++ case (FPW) INTEL_ID_28F128J3A: ++ info->flash_id += FLASH_28F128J3A; ++ info->sector_count = 128; ++ info->size = 0x02000000; ++ break; /* => 16 MB x 2 */ ++ case (FPW) INTEL_ID_28F320J3A: ++ info->flash_id += FLASH_28F320J3A; ++ info->sector_count = 32 ; ++ info->size = 0x800000 ; ++ break; /* => 4 MB x 2 */ ++ default: ++printf( "Unknown flash device %x\n", value ); ++ info->flash_id = FLASH_UNKNOWN; ++ break; ++ } ++ ++ if (info->sector_count > CFG_MAX_FLASH_SECT) { ++ printf ("** ERROR: sector count %d > max (%d) **\n", ++ info->sector_count, CFG_MAX_FLASH_SECT); ++ info->sector_count = CFG_MAX_FLASH_SECT; ++ } ++ ++ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ ++ ++ return (info->size); ++} ++ ++ ++/*----------------------------------------------------------------------- ++ */ ++ ++int flash_erase (flash_info_t *info, int s_first, int s_last) ++{ ++ int flag, prot, sect; ++ ulong type, start, last; ++ int rcode = 0; ++ ++ if ((s_first < 0) || (s_first > s_last)) { ++ if (info->flash_id == FLASH_UNKNOWN) { ++ printf ("- missing\n"); ++ } else { ++ printf ("- no sectors to erase\n"); ++ } ++ return 1; ++ } ++ ++ type = (info->flash_id & FLASH_VENDMASK); ++ if ((type != FLASH_MAN_INTEL)) { ++ printf ("Can't erase unknown flash type %08lx - aborted\n", ++ info->flash_id); ++ return 1; ++ } ++ ++ prot = 0; ++ for (sect = s_first; sect <= s_last; ++sect) { ++ if (info->protect[sect]) { ++ prot++; ++ } ++ } ++ ++ if (prot) { ++ printf ("- Warning: %d protected sectors will not be erased!\n", ++ prot); ++ } else { ++ printf ("\n"); ++ } ++ ++ start = get_timer (0); ++ last = start; ++ ++ /* Disable interrupts which might cause a timeout here */ ++ flag = disable_interrupts (); ++ ++ /* Start erase on unprotected sectors */ ++ for (sect = s_first; sect <= s_last; sect++) { ++ if (info->protect[sect] == 0) { /* not protected */ ++ char temp[80]; ++ FPWV *addr = (FPWV *) (info->start[sect]); ++ FPW status; ++ ++ sprintf (temp, "Erasing sector %2d ... \r", sect); ++ lcd_puts( temp ); ++ ++ /* arm simple, non interrupt dependent timer */ ++ reset_timer_masked (); ++ ++ *addr = (FPW) 0x00500050; /* clear status register */ ++ *addr = (FPW) 0x00200020; /* erase setup */ ++ *addr = (FPW) 0x00D000D0; /* erase confirm */ ++ ++ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { ++ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { ++ printf ("Timeout\n"); ++ *addr = (FPW) 0x00B000B0; /* suspend erase */ ++ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ ++ rcode = 1; ++ break; ++ } ++ } ++ ++ *addr = 0x00500050; /* clear status register cmd. */ ++ *addr = 0x00FF00FF; /* resest to read mode */ ++ } ++ } ++ lcd_puts( "\r\n" ); ++ return rcode; ++} ++ ++/*----------------------------------------------------------------------- ++ * Copy memory to flash, returns: ++ * 0 - OK ++ * 1 - write timeout ++ * 2 - Flash not erased ++ * 4 - Flash not identified ++ */ ++ ++int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) ++{ ++ ulong cp, wp; ++ FPW data; ++ int count, i, l, rc, port_width; ++ ++ rc = 0 ; ++ if (info->flash_id == FLASH_UNKNOWN) { ++ return 4; ++ } ++/* get lower word aligned address */ ++#ifdef FLASH_PORT_WIDTH16 ++ wp = (addr & ~1); ++ port_width = 2; ++#else ++ wp = (addr & ~3); ++ port_width = 4; ++#endif ++ ++ spin_wheel_init(addr,cnt); ++ ++ /* ++ * handle unaligned start bytes ++ */ ++ if ((l = addr - wp) != 0) { ++ data = 0; ++ for (i = 0, cp = wp; i < l; ++i, ++cp) { ++ data = (data << 8) | (*(uchar *) cp); ++ } ++ for (; i < port_width && cnt > 0; ++i) { ++ data = (data << 8) | *src++; ++ --cnt; ++ ++cp; ++ } ++ for (; cnt == 0 && i < port_width; ++i, ++cp) { ++ data = (data << 8) | (*(uchar *) cp); ++ } ++ ++ if ((rc = write_data (info, wp, SWAP (data))) != 0) { ++ goto out; ++ } ++ wp += port_width; ++ } ++ ++ /* ++ * handle word aligned part ++ */ ++ count = 0; ++ while (cnt >= port_width) { ++ data = 0; ++ for (i = 0; i < port_width; ++i) { ++ data = (data << 8) | *src++; ++ } ++ if ((rc = write_data (info, wp, SWAP (data))) != 0) { ++ goto out; ++ } ++ wp += port_width; ++ cnt -= port_width; ++ if (count++ > 0x800) { ++ spin_wheel (cnt); ++ count = 0; ++ } ++ } ++ ++ if (cnt) { ++ /* ++ * handle unaligned tail bytes ++ */ ++ data = 0; ++ for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { ++ data = (data << 8) | *src++; ++ --cnt; ++ } ++ for (; i < port_width; ++i, ++cp) { ++ data = (data << 8) | (*(uchar *) cp); ++ } ++ ++ rc = write_data (info, wp, SWAP (data)); ++ } ++ ++out: ++ spin_wheel_done(0 == rc); ++ return rc ; ++} ++ ++/*----------------------------------------------------------------------- ++ * Write a word or halfword to Flash, returns: ++ * 0 - OK ++ * 1 - write timeout ++ * 2 - Flash not erased ++ */ ++static int write_data (flash_info_t *info, ulong dest, FPW data) ++{ ++ FPWV *addr = (FPWV *) dest; ++ FPW old = *addr ; ++ ulong status; ++ int flag; ++ ++ /* Check if Flash is (sufficiently) erased */ ++ if ((old & data) != data) { ++ printf ("not erased at %08lx (%lx)\n", (ulong) addr, old); ++ return (2); ++ } ++ ++ if( old != data ) ++ { ++ /* Disable interrupts which might cause a timeout here */ ++ flag = disable_interrupts (); ++ ++ *addr = (FPW) 0x00400040; /* write setup */ ++ *addr = data; ++ ++ /* arm simple, non interrupt dependent timer */ ++ reset_timer_masked (); ++ ++ /* wait while polling the status register */ ++ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { ++ if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { ++ *addr = (FPW) 0x00FF00FF; /* restore read mode */ ++ return (1); ++ } ++ } ++ *addr = (FPW) 0x00FF00FF; /* restore read mode */ ++ } /* need to program? */ ++ ++ ++ return (0); ++} ++ ++void inline spin_wheel_init(ulong addr, ulong cnt) ++{ ++ char temp[80]; ++ sprintf( temp, ++ "\nprogramming flash\n" ++ "%08lx->%08lx\n" ++ " ", addr, cnt ); ++ lcd_puts( temp ); ++} ++ ++void inline spin_wheel_done( int worked ) ++{ ++ if( worked ) ++ spin_wheel(0); ++ lcd_puts( worked ? "\ncompleted.\n" : "\nfailed!\n" ); ++} ++ ++void inline spin_wheel( ulong numleft ) ++{ ++ char temp[40]; ++ sprintf( temp, "\r %08lx", numleft ); ++ lcd_puts( temp ); ++} +diff -u -r --new-file u-boot-1.1.2/board/neon/init.script u-boot-1.1.2-neon/board/neon/init.script +--- u-boot-1.1.2/board/neon/init.script 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/neon/init.script 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,42 @@ ++if fatload mmc 0 a0008000 logo*.bmp ; then ++ bmp info a0008000 ; ++ bmp display a0008000 ; ++else ++ lecho "No logo present" ; ++fi ++ ++if fatload mmc 0 a2000000 uim* ; then ++ lecho 'load Linux' ++ if fatload mmc 0 a2200000 mmcinitrd* ; then ++ echo 'using initrd' ; ++ lecho "Booting Linux" ++ set bootargs root=/dev/ram0 console=ttyS0,115200 debug=7 mtdparts=phys_mapped_flash:1024k(armboot),256k(params),-(rootfs1) ++ bootm a2000000 a2200000 ++ else ++ echo 'testing cramfs img' ; ++ if fatload mmc 0 a2200000 cramfs* ; then ++ if cmp.b 00140000 a2200000 $filesize ; then ++ echo 'cramfs images match' ; ++ else ++ lecho 'filesystems differ...' ; ++ protect off all ; ++ erase 00140000 01ffffff ; ++ cp.b a2200000 00140000 $filesize ; ++ fi ++ ++ set bootargs console=ttyS0,115200 debug=7 mtdparts=phys_mapped_flash:1024k(armboot),256k(params),-(rootfs1) root=/dev/mtdblock3 rootfstype=cramfs ++ lecho "Booting Linux" ++ bootm a2000000 ++ fi ++ fi ++else ++ echo "No Linux kernel" ; ++fi ++ ++lecho 'No Linux, try CE' ++ ++if fatload mmc 0 A0030000 nk*.nb0 ; then ++ g A0030000 ; ++else ++ echo "No WinCE image" ; ++fi +diff -u -r --new-file u-boot-1.1.2/board/neon/Makefile u-boot-1.1.2-neon/board/neon/Makefile +--- u-boot-1.1.2/board/neon/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/neon/Makefile 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,48 @@ ++ ++# ++# (C) Copyright 2000 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = lib$(BOARD).a ++ ++OBJS := neon.o flash.o rtc_M41T81S.o ++SOBJS := memsetup.o ++ ++$(LIB): $(OBJS) $(SOBJS) ++ $(AR) crv $@ $(OBJS) $(SOBJS) ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak .depend ++ ++######################################################################### ++ ++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) ++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ ++ ++-include .depend ++ ++######################################################################### +diff -u -r --new-file u-boot-1.1.2/board/neon/memsetup.S u-boot-1.1.2-neon/board/neon/memsetup.S +--- u-boot-1.1.2/board/neon/memsetup.S 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/neon/memsetup.S 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,64 @@ ++/* ++ * Most of this taken from Redboot hal_platform_setup.h with cleanup ++ * ++ * NOTE: I haven't clean this up considerably, just enough to get it ++ * running. See hal_platform_setup.h for the source. See ++ * board/cradle/memsetup.S for another PXA250 setup that is ++ * much cleaner. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++ ++#define BAUDRATE 115200 ++#include ++#include ++#include ++#include ++ ++DRAM_SIZE: .long CFG_DRAM_SIZE ++ ++/* wait for coprocessor write complete */ ++ .macro CPWAIT reg ++ mrc p15,0,\reg,c2,c0,0 ++ mov \reg,\reg ++ sub pc,pc,#4 ++ .endm ++ ++ ++/* ++ * Memory setup ++ */ ++ ++.globl memsetup ++memsetup: ++ ++ mov r10, lr ++ ++ InitCS0_CS1 r0,sp ++ InitGPIO r0,sp ++ InitIC_Clocks r0,sp ++ InitUART r0,sp,UART_BASE,BAUDRATE ++ InitUART r0,sp,UART_BASE+0x600000,9600 ++ InitChangeCPUSpeed r0 ++ InitMemory r0,sp,r1 ++ ++ mov pc, lr +diff -u -r --new-file u-boot-1.1.2/board/neon/neon.c u-boot-1.1.2-neon/board/neon/neon.c +--- u-boot-1.1.2/board/neon/neon.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/neon/neon.c 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,615 @@ ++/* ++ * (C) Copyright 2002 ++ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net ++ * ++ * (C) Copyright 2002 ++ * Sysgo Real-Time Solutions, GmbH ++ * Marius Groeger ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define FASTCLOCK1 0x291A0201 //faster pixel clock: P2S = 1, P2 = 9 (/6) ( panel source 1, divide by 6) ++ // V2S = 1, V2 = 10 (/12) ( crt source 1, divide by 12) ++ // M2S = 0, MR = 2 (/4) (sdram source 1, divide by 4) ++ // M1S = 0, MR = 1 (/2) ++ // miscTimReg[5:4] == 0 (336 MHz) ++ // / 6 == 56 MHz ++ // ++#define FASTCLOCK2 0x291A0201 ++#define FASTCLOCK3 0x00080800 ++ ++#define SLOWCLOCK1 0x0A1A0201 //slow pixel clock: P2S = 0, P2 = 10 (/12) ( panel source 0, divide by 12) ++ // V2S = 1, V2 = 10 (/12) ( crt source 1, divide by 12) ++ // M2S = 0, MR = 2 (/4) (sdram source 1, divide by 4) ++ // M1S = 0, MR = 1 (/2) ++ // miscTimReg[5:4] == 0 (288 MHz) ++ // / 12 == 24 MHz ++ // ++#define SLOWCLOCK2 0x0A1A0A09 ++#define SLOWCLOCK3 0x00090900 ++ ++unsigned long const fbStart = 0x0C000000 ; ++unsigned long const fbMax = 0x00800000 ; // ++ ++unsigned long const mmioStart = 0xFE00000 ; ++unsigned long const mmioLength = 0x00200000 ; ++unsigned long const lcdPaletteRegs = 0xFE80400 ; ++unsigned long const crtPaletteRegs = 0xFE80C00 ; ++unsigned long paletteRegs = 0xFE80400 ; ++ ++const unsigned int sm501_list1[]={ ++ 0x0FE00000, ++ 0x00100000,0x00001002,0x00000000,0x00000000,0x07F127C0,0x05146732,0x40715128,0x00000000, ++ 0x00000000,0x00180002,0x00000002,0x00000002,0x00000000,0x00000000,0x0000001F,0x291A0201, ++ 0x0000001F,0x291A0201,0x00000007,0x291A0201,0x00018000,0x00000000,0x00000000,0x00000000, ++ 0x050100A0,0x00000000,0x00080800}; ++ ++const unsigned int sm501_list2[]={ 0x0fe80000, ++/* 80000 dispctrl */ 0x0F013100, // 0f0d0105 ++/* 80004 pan */ 0x00000000, ++/* 80008 colorkey */ 0x00000000, ++/* 8000C fbaddr */ 0x00000000, ++/* 80010 offsetww */ 0x00000000, // ((LCD_XRES)<<16)+(LCD_XRES), ++/* 80014 fbwidth */ 0x00000000, // (LCD_XRES<<16), ++/* 80018 fbheight */ 0x00000000, // (LCD_YRES<<16), ++/* 8001C tllocate */ 0x00000000, ++/* 80020 brlocate */ 0x00000000, // ((LCD_YRES-1)<<16)+(LCD_XRES-1), ++/* 80024 htotal */ 0x00000000, // ((LCD_BEGIN_OF_LINE_WAIT_COUNT+ ++/* */ // LCD_XRES+ ++/* */ // LCD_END_OF_LINE_WAIT_COUNT+ ++/* */ // LCD_HORIZONTAL_SYNC_PULSE_WIDTH-1)<<16) ++/* */ // +(LCD_XRES-1), ++/* 80028 hsync */ 0x00000000, // (LCD_HORIZONTAL_SYNC_PULSE_WIDTH<<16) ++/* */ // +(LCD_XRES+LCD_BEGIN_OF_LINE_WAIT_COUNT-1), ++/* 8002C vtotal */ 0x00000000, // ((LCD_BEGIN_FRAME_WAIT_COUNT+ ++/* */ // LCD_YRES+ ++/* */ // LCD_END_OF_FRAME_WAIT_COUNT+ ++/* */ // LCD_VERTICAL_SYNC_PULSE_WIDTH-1)<<16) ++/* */ // +(LCD_YRES-1), ++/* 80030 vsync */ 0x00000000, // (LCD_VERTICAL_SYNC_PULSE_WIDTH<<16) ++/* */ // +(LCD_YRES+LCD_BEGIN_FRAME_WAIT_COUNT-1) ++}; ++ ++static unsigned const miscCtrl = 0x00000004 ; ++static unsigned const curClockReg = 0x0000003C ; ++static unsigned const pm0ClockReg = 0x00000044 ; ++static unsigned const pm1ClockReg = 0x0000004C ; ++static unsigned const miscTimReg = 0x00000068 ; ++ ++static unsigned const dispctrlReg = 0x00080000 ; ++static unsigned const offsetReg = 0x00080010 ; // ((xres)<<16)+(xres), ++static unsigned const fbWidthReg = 0x00080014 ; // (xres<<16), ++static unsigned const fbHeightReg = 0x00080018 ; // (yres<<16), ++static unsigned const brLocateReg = 0x00080020 ; // ((yres-1)<<16)+(xres-1), ++static unsigned const hTotalReg = 0x00080024 ; // (left_margin+xres+right_margin+hsync_len-1) << 16 ++ // + xres ++static unsigned const hSyncReg = 0x00080028 ; // (hsync_len<<16) + (xres+left_margin-1) ++static unsigned const vTotalReg = 0x0008002c ; // (top_margin+yres+lower_margin+vsync_len-1) << 16 ++ // + yres-1 ++static unsigned const vSyncReg = 0x00080030 ; // (vsync_len<<16) + yres+top_margin-1 ++ ++/* ++ * CRT regs ++ */ ++static unsigned const crtctrlReg = 0x00080200 ; ++static unsigned const crtFbAddrReg = 0x00080204 ; ++static unsigned const crtFbOffsReg = 0x00080208 ; ++static unsigned const crtFbHTotReg = 0x0008020C ; ++static unsigned const crtFbHSynReg = 0x00080210 ; ++static unsigned const crtFbVTotReg = 0x00080214 ; ++static unsigned const crtFbVSynReg = 0x00080218 ; ++ ++#define DISPCRTL_ENABLE 4 ++ ++#define CLOCK_ACTIVEHIGH 0 ++#define CLOCK_ACTIVELOW (1<<14) ++#define CLOCK_ACTIVEMASK (1<<14) ++ ++#define LCDTYPE_TFT 0 ++#define LCDTYPE_STN12 (3<<18) ++#define LCDTYPE_MASK (3<<18) ++ ++#define READREG( addr ) *( (unsigned long volatile *)((addr)+mmioStart) ) ++#define STUFFREG( addr, value ) *( (unsigned long volatile *)((addr)+mmioStart) ) = (value) ++ ++const unsigned int sm501_list3[]={0x0fe80040, ++ 0x00010000,0x0703E360,0x00200400,0x00A81330,0x0385009C,0x02200240,0x00000000,0x00000000, ++ 0x00EDEDED,0x089C4040,0x0031E3B0}; ++ ++const unsigned int sm501_list4[]={0x0fe80080, ++ 0x00010000,0x05121880,0x28800C00,0x00108030,0x02090040,0x00840050,0x00000000,0x00000000, ++ 0x0141A200,0x020A0802,0x0088D109,0x20820040,0x10800000,0x30029200,0x00080821,0x01010400, ++ 0x44000120,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, ++ 0x00000000,0x00000000,0x00000000,0x00000000}; ++ ++const unsigned int sm501_list5[]={0x0fe800f0, ++ 0x0070F800,0x00780140,0x00000000,0x0000FFFF,0x00010000}; ++ ++struct itemEntry { ++ const int cnt; ++ const unsigned int* p; ++}; ++ ++const struct itemEntry lists[] = { ++ {sizeof(sm501_list1)>>2,sm501_list1}, ++ {sizeof(sm501_list2)>>2,sm501_list2}, ++ {sizeof(sm501_list3)>>2,sm501_list3}, ++ {sizeof(sm501_list4)>>2,sm501_list4}, ++ {sizeof(sm501_list5)>>2,sm501_list5} ++}; ++ ++int lcd_color_fg; ++int lcd_color_bg; ++ ++void *lcd_base; /* Start of framebuffer memory */ ++void *lcd_console_address; /* Start of console buffer */ ++ ++short console_col; ++short console_row; ++ ++ ++ulong calc_fbsize (void) ++{ ++ if( cur_lcd_panel ) ++ { ++ int line_length = (cur_lcd_panel->xres * NBITS (LCD_BPP)) / 8; ++ return ( cur_lcd_panel->yres * line_length ) + PAGE_SIZE ; ++ } ++ else ++ return 0 ; ++} ++ ++void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) ++{ ++ unsigned long *const palette = (unsigned long *)paletteRegs ; ++ unsigned long const rgb = ((unsigned long)red ) << 16 ++ | ((unsigned long)green ) << 8 ++ | blue ; ++ palette[regno] = rgb ; ++} ++ ++void lcd_ctrl_init (void *lcdbase) ++{ ++ unsigned short *fbMem; ++ char *panelName ; ++ ++ unsigned long val=0; ++ const struct itemEntry* l = lists; ++ int count = sizeof(lists)/sizeof(struct itemEntry); ++ printf( "sm501 init start\n"); ++ ++ while (count) { ++ int cnt = l->cnt-1; ++ const unsigned long* p = (unsigned long*)l->p; ++ volatile unsigned int* reg = (unsigned int*)(*p++); ++// printf( "set regs: %p, cnt:%x, from %p, l:%p\n", reg, cnt, p,l ); ++// while (reg==0) { ++// } ++ ++ while (cnt) { ++ val = *p++; ++// printf( "set reg: %p = %x from %p\n", reg, val, p ); ++ *reg++ = val; ++ cnt--; ++ } ++ count--; ++ l++; ++ } ++// printf( "sm501 init middle\n"); ++ ++ panelName = getenv( "panel" ); ++// printf( "after getenv\n"); ++ if( panelName ) ++ { ++ struct lcd_panel_info_t const *panel ; ++ panel = find_lcd_panel( panelName ); ++ if( panel ) ++ { ++ printf( "panel %s found: %u x %u\n", panelName, panel->xres, panel->yres ); ++// printf( "before set_lcd_panel\n"); ++ set_lcd_panel( panel ); ++// printf( "after set_lcd_panel\n"); ++ } ++ else ++ printf( "panel %s not found\n", panelName ); ++ } ++ ++ fbMem = (unsigned short *)fbStart ; ++ lcd_base = fbMem ; ++ ++/* ++Settings for Hitachi 5.7 ++ PANEL_HORIZONTAL_TOTAL, 01c00160); ++ PANEL_HORIZONTAL_SYNC, 00400161); ++ PANEL_VERTICAL_TOTAL, 0x010800f0); ++ PANEL_VERTICAL_SYNC, 0x00020104); ++ ++In bdlogo.bmp - offset 436 is pixel data ++ STUFFREG( hTotalReg, 0x01800140 ); ++ STUFFREG( hSyncReg, 0x0008014f ); ++ STUFFREG( vTotalReg, 0x010700F0 ); ++ STUFFREG( vSyncReg, 0x00020100 ); ++*/ ++ printf( "lcd_ctrl_init exit\n"); ++} ++ ++void lcd_enable (void) ++{ ++} ++ ++#define BIT29 (1<<29) ++ ++static void setClockReg( unsigned reg, unsigned long value ) ++{ ++ unsigned oldValue = READREG( reg ); ++ if( (oldValue & BIT29) != (value&BIT29) ) ++ { ++ oldValue = (oldValue & (~BIT29)) ++ | (value & BIT29); ++ STUFFREG( reg, oldValue ); ++ udelay(16000); ++ } ++ ++ if( oldValue != value ) ++ STUFFREG( reg, value ); ++} ++ ++vidinfo_t panel_info = { ++ vl_col: 320, //this is corrected in SetPanelInfo ++ vl_row: 240, ++ vl_bpix: LCD_BPP, ++ vl_lcd_line_length: (320 * NBITS(LCD_BPP) ) >> 3 ++}; ++ ++static void SetPanelInfo(struct lcd_panel_info_t const *panel) ++{ ++ panel_info.vl_col = panel->xres; ++ panel_info.vl_row = panel->yres; ++ panel_info.vl_bpix = LCD_BPP; ++ panel_info.vl_lcd_line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) >> 3; ++ printf("panel: %ix%ix%i\n",panel_info.vl_col,panel_info.vl_row,(1<act_high ) ++ crtCtrl |= (3<<14); // horizontal and vertical phase ++ STUFFREG( crtFbAddrReg, 0 ); ++ STUFFREG( crtFbOffsReg, ((panel->xres)<<16)+(panel->xres) ); ++ STUFFREG( crtFbHTotReg, (( panel->left_margin ++ +panel->xres ++ +panel->right_margin ++ +panel->hsync_len - 1) << 16 ) ++ + panel->xres-1 ); ++ STUFFREG( crtFbHSynReg, (panel->hsync_len<<16)+ (panel->xres+panel->left_margin-1) ); ++ STUFFREG( crtFbVTotReg, (( panel->upper_margin ++ +panel->yres ++ +panel->lower_margin ++ +panel->vsync_len-1 ) << 16 ) ++ + panel->yres-1 ); ++ STUFFREG( crtFbVSynReg,(panel->vsync_len<<16) ++ + panel->yres+panel->upper_margin-1 ); ++ STUFFREG( crtctrlReg, crtCtrl ); // enable ++ ++ reg = READREG( miscCtrl ) & ~0x1000 ; ++ STUFFREG( miscCtrl, reg ); ++} ++ ++void set_lcd_panel( struct lcd_panel_info_t const *panel ) ++{ ++ unsigned long dispctrl = READREG( dispctrlReg ); ++ dispctrl &= ~(CLOCK_ACTIVEMASK|LCDTYPE_MASK); ++ if( !panel->act_high ) ++ dispctrl |= CLOCK_ACTIVELOW ; ++ else ++ dispctrl &= ~CLOCK_ACTIVEMASK ; ++ ++ if( !panel->active ) ++ dispctrl |= LCDTYPE_STN12 ; ++ else ++ dispctrl &= ~LCDTYPE_MASK ; ++ ++ if (panel->crt==0) dispctrl |= 4; ++ ++ STUFFREG( offsetReg, ((panel->xres)<<16)+(panel->xres) ); ++ STUFFREG( fbWidthReg, (panel->xres<<16) ); ++ STUFFREG( fbHeightReg, (panel->yres<<16) ); ++ STUFFREG( brLocateReg, ((panel->yres-1)<<16)+(panel->xres-1) ); ++ STUFFREG( hTotalReg, (( panel->left_margin ++ +panel->xres ++ +panel->right_margin ++ +panel->hsync_len - 1) << 16 ) ++ + panel->xres-1 ); ++ STUFFREG( hSyncReg, (panel->hsync_len<<16)+ (panel->xres+panel->left_margin-1) ); ++ STUFFREG( vTotalReg, (( panel->upper_margin ++ +panel->yres ++ +panel->lower_margin ++ +panel->vsync_len-1 ) << 16 ) ++ + panel->yres-1 ); ++ STUFFREG( vSyncReg, (panel->vsync_len<<16) ++ + panel->yres+panel->upper_margin-1 ); ++ ++ if( panel->pixclock < numClockRegs ) ++ { ++ unsigned long const *clk = clockRegs+(panel->pixclock*2); ++ setClockReg( curClockReg, *clk ); ++ setClockReg( pm0ClockReg, *clk++ ); ++ setClockReg( pm1ClockReg, *clk ); ++ } ++ else ++ { ++ int const isCRT = (0 != panel->crt); ++ int crt ; ++ ++ for( crt = 0 ; crt < 2 ; crt++ ) ++ { ++ unsigned long reg ; ++ unsigned long const *freq = frequencies[crt]; ++ unsigned const count = numFrequencies[crt]; ++ ++ unsigned long f, diffl, diffh ; ++ int i ; ++ unsigned long low, high ; ++ ++ // ++ // linear scan for closest frequency ++ // ++ for( i = 0 ; i < count ; i++, freq += ENTRIESPERFREQ ) ++ { ++ if( *freq > panel->pixclock ) ++ break; ++ } ++ ++ low = (i > 0) ++ ? freq[0-ENTRIESPERFREQ] ++ : 0 ; ++ diffl = panel->pixclock - low ; ++ ++ high = (i < count ) ++ ? *freq ++ : 0xFFFFFFFF ; ++ diffh = high - panel->pixclock ; ++ ++ if( diffh < diffl ) ++ { ++ f = high ; ++ } ++ else ++ { ++ f = low ; ++ freq-- ; ++ } ++ ++ printf( "pixclock == %lu, frequency %u/%u -> %lu\n", ++ panel->pixclock, low, high, f ); ++ ++ reg = READREG( curClockReg ) & ~(clockMasks[crt]); ++ ++ // Clock source ++ printf( "source %u, divisor %u\n", freq[1], freq[2] ); ++ reg |= freq[1]; ++ reg |= freq[2]; ++ ++ setClockReg( curClockReg, reg ); ++ setClockReg( pm0ClockReg, reg ); ++ setClockReg( pm1ClockReg, reg ); ++ ++ if( isCRT ) ++ { ++ paletteRegs = crtPaletteRegs ; ++ updateCRT( freq, panel ); ++ } ++ else ++ paletteRegs = lcdPaletteRegs ; ++ } ++ } ++ STUFFREG( dispctrlReg, dispctrl ); ++ cur_lcd_panel = panel ; ++ SetPanelInfo(panel); ++} ++ ++void disable_lcd_panel( void ) ++{ ++ unsigned long dispctrl = READREG( dispctrlReg ); ++ unsigned long crtctrl = READREG( crtctrlReg ); ++ ++ dispctrl &= ~(DISPCRTL_ENABLE); ++ STUFFREG( dispctrlReg, dispctrl ); ++ ++ crtctrl &= ~(DISPCRTL_ENABLE); ++ STUFFREG( crtctrlReg, crtctrl ); ++} ++ ++/* ------------------------------------------------------------------------- */ ++ ++ ++/* ++ * Miscelaneous platform dependent initialisations ++ */ ++ ++int board_init (void) ++{ ++ DECLARE_GLOBAL_DATA_PTR; ++ ++ /* memory and cpu-speed are setup before relocation */ ++ /* so we do _nothing_ here */ ++ ++ /* arch number of Neon Board */ ++ gd->bd->bi_arch_number = MACH_TYPE_BD2003 ; ++ ++ /* adress of boot parameters */ ++ gd->bd->bi_boot_params = 0xa0000100; ++ ++ /* address of frame buffer */ ++ gd->fb_base = fbStart ; ++ ++ return 0; ++} ++ ++int board_late_init(void) ++{ ++ setenv("stdout", "serial"); ++ setenv("stderr", "serial"); ++ return 0; ++} ++ ++ ++int dram_init (void) ++{ ++ DECLARE_GLOBAL_DATA_PTR; ++ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; ++ ++ return 0; ++} +diff -u -r --new-file u-boot-1.1.2/board/neon/rtc_M41T81S.c u-boot-1.1.2-neon/board/neon/rtc_M41T81S.c +--- u-boot-1.1.2/board/neon/rtc_M41T81S.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/neon/rtc_M41T81S.c 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,663 @@ ++/* ++ * M41T81S: ++ * ++ * This module defines a single 'rtc' command to read/write or ++ * test the ST Micro Real Time Clock attached to the SM-501 ++ * I2C pins. ++ * ++ * If called with no parameters, it will display the current time ++ * to the console device and set the 'time' environment variable. ++ * ++ * If called with a single parameter of "test", it will read the ++ * current time, wait a second and read the current time again. ++ * It will return success (zero) if the RTC time appears to tick ++ * by 1 second. ++ * ++ * If called with one or two parameters that appear to fit an ++ * ISO 8601 time format (i.e. YYYY-MM-DD HH:MM:SS.00 ), it will ++ * set the date and time. ++ * ++ * Copyright (c) Boundary Devices, 2006 ++ * ++ */ ++#include "sm501.h" ++#include ++#include ++#include ++#include ++#include ++ ++int WriteI2C(int bVal); ++int ReadI2C(int ack); ++int I2CStart(int bSlaveAddress); ++void I2CStop(void); ++void I2CInit(void); ++ ++////////////////////////////////////////////////////////// ++ ++#define SM501_GPIO_DATA 0x10000 ++#define SM501_GPIO_DIR 0x10008 ++ ++#define INPUT 0 ++#define OUTPUT 1 ++ ++#define I2C_CLK 46 ++#define I2C_DATA 47 ++#define GPBIT_MASK(bitnum) (1<<(bitnum&0x1f)) ++#define GPBIT_TEST(bitnum) ( (ReadReg(SM501_GPIO_DATA + ((bitnum>>5)<<2))) & (1<<(bitnum&0x1f)) ) ++#define GPBIT_TESTBIT(c,bitnum) ( c & (1<<(bitnum&0x1f)) ) ++#define GPBIT_SET(x,bitnum,value) ( (value) ? ((x) | (1<<(bitnum&0x1f))) : ((x) & ~(1<<(bitnum&0x1f))) ) ++ ++//0.400 Mhz protocol = 1/.4 uSec = 10/4 uSec = 2.5 uSec ++//4 should be safe ++#define I2CWait 4 ++#define LongBusWait 8 ++#define StartBusWait 12 ++ ++typedef struct { ++ unsigned short wYear; ++ unsigned short wMonth; ++ unsigned short wDayOfWeek; ++ unsigned short wDay; ++ unsigned short wHour; ++ unsigned short wMinute; ++ unsigned short wSecond; ++ unsigned short wMilliseconds; ++} SYSTEMTIME ; ++ ++typedef SYSTEMTIME *LPSYSTEMTIME ; ++ ++void I2CInit(void) ++{ ++ int i; ++ ++ for(i=0; i<9; i++) ++ { ++ I2CStop(); ++ } ++} ++ ++ ++#define ReadReg(reg) READ_SM501_REG(reg) ++#define WriteReg(reg,data) STUFF_SM501_REG((reg), (data)) ++ ++void SetVal_ClkData(int clk,int data) ++{ ++#if (I2C_DATA>>5)==(I2C_CLK>>5) ++ ulong c = ReadReg( SM501_GPIO_DATA + ((I2C_DATA>>5)<<2) ); ++ c = GPBIT_SET(c, I2C_DATA, data); ++ c = GPBIT_SET(c, I2C_CLK, clk); ++ WriteReg(SM501_GPIO_DATA + ((I2C_DATA>>5)<<2), c); ++#else ++ ulong c = ReadReg( SM501_GPIO_DATA + ((I2C_DATA>>5)<<2) ); ++ c = GPBIT_SET(c, I2C_DATA, data); ++ WriteReg(SM501_GPIO_DATA + ((I2C_DATA>>5)<<2), c); ++ ++ c = ReadReg( SM501_GPIO_DATA + ((I2C_CLK>>5)<<2) ); ++ c = GPBIT_SET(c, I2C_CLK, clk); ++ WriteReg(SM501_GPIO_DATA + ((I2C_CLK>>5)<<2), c); ++#endif ++} ++ ++void SetDir_ClkData(int clk,int data) ++{ ++ ulong c,c1; ++#if (I2C_DATA>>5)==(I2C_CLK>>5) ++ c = ReadReg( SM501_GPIO_DIR + ((I2C_CLK>>5)<<2) ); ++ if (clk==OUTPUT) { ++ //will be low, and can then change data ++ c1 = GPBIT_SET(c, I2C_CLK, OUTPUT); ++ if (c!=c1) WriteReg( SM501_GPIO_DIR + ((I2C_CLK>>5)<<2), c1); ++ c = GPBIT_SET(c1, I2C_DATA, data); ++ } else { ++ //clk might be low currently, so change data 1st ++ c1 = GPBIT_SET(c, I2C_DATA, data); ++ if (c!=c1) WriteReg( SM501_GPIO_DIR + ((I2C_DATA>>5)<<2), c1); ++ c = GPBIT_SET(c1, I2C_CLK, INPUT); ++ } ++ if (c!=c1) WriteReg( SM501_GPIO_DIR + ((I2C_CLK>>5)<<2), c); ++#else ++ if (clk==OUTPUT) { ++ //will be low, and can then change data ++ c = ReadReg( SM501_GPIO_DIR + ((I2C_CLK>>5)<<2) ); ++ c1 = GPBIT_SET(c, I2C_CLK, OUTPUT); ++ if (c!=c1) WriteReg( SM501_GPIO_DIR + ((I2C_CLK>>5)<<2), c1); ++ ++ c1 = ReadReg( SM501_GPIO_DIR + ((I2C_DATA>>5)<<2) ); ++ c = GPBIT_SET(c1, I2C_DATA, data); ++ if (c!=c1) WriteReg( SM501_GPIO_DIR + ((I2C_DATA>>5)<<2), c); ++ } else { ++ //clk might be low currently, so change data 1st ++ c = ReadReg( SM501_GPIO_DIR + ((I2C_DATA>>5)<<2) ); ++ c1 = GPBIT_SET(c, I2C_DATA, data); ++ if (c!=c1) WriteReg( SM501_GPIO_DIR + ((I2C_DATA>>5)<<2), c1); ++ ++ c1 = ReadReg( SM501_GPIO_DIR + ((I2C_CLK>>5)<<2) ); ++ c = GPBIT_SET(c1, I2C_CLK, INPUT); ++ if (c!=c1) c1WriteReg( SM501_GPIO_DIR + ((I2C_CLK>>5)<<2), c); ++ } ++#endif ++} ++void SetDir_Clk(int clk) ++{ ++ ulong c = ReadReg( SM501_GPIO_DIR + ((I2C_CLK>>5)<<2) ); ++ c = GPBIT_SET(c, I2C_CLK, clk); ++ WriteReg( SM501_GPIO_DIR + ((I2C_CLK>>5)<<2), c); ++} ++ ++void I2CStop() ++{ ++ SetDir_Clk(OUTPUT); //low clock ++ udelay(I2CWait); ++ SetDir_ClkData(OUTPUT,OUTPUT); //low clock, low data ++ udelay(I2CWait); ++ ++ //Drive Write SCL High ++ SetDir_Clk(INPUT); //high clock ++ udelay(I2CWait); ++ ++ // Drive Write SDA High ++ SetDir_ClkData(INPUT,INPUT); //transition on data from low to high while clock is high is a stop control signal ++ udelay(LongBusWait); ++ ++} ++ ++ ++//return 0 for success ++int WriteI2C(int bVal) ++{ ++ ++ int mask; ++ int i; ++ ++ // Enable Write SDA and SCL, and Drv SCL low ++ SetDir_Clk(OUTPUT); //clock low ++ udelay(I2CWait); //hold time ++ ++ for (mask=0x80; mask; mask>>=1) ++ { ++ SetDir_ClkData(OUTPUT, (bVal & mask) ? INPUT : OUTPUT); // Write data bits to SDA ++ udelay(LongBusWait); ++ ++ SetDir_Clk(INPUT); // Drv CLK High ++ udelay(I2CWait); ++ ++ SetDir_Clk(OUTPUT); // Drv CLK Low ++ udelay(I2CWait); //hold time after clock goes low ++ } ++ ++ ++ SetDir_ClkData(OUTPUT,INPUT); // Disable Write SDA ++ udelay(LongBusWait); //wait for acknowledge to be placed on SDA ++ SetDir_Clk(INPUT); // Drive Clock High ++ ++ // Read SDA, until SDA==0 ++ for (i=0; i<255; i++) { ++ udelay(LongBusWait); ++ if (!GPBIT_TEST(I2C_DATA)) { ++ SetDir_Clk(OUTPUT); // Drv Clk LOW ++ return 0; //success ++ } ++ } ++ ++ printf( "WriteI2C(%i) failed\n", bVal ); ++ return -1; ++} ++ ++int ReadI2C(int ack) ++{ ++ int mask; ++ int byRet = 0; ++ ++// SetVal_ClkData(0,0); ++ SetDir_Clk(OUTPUT); //clock low ++ udelay(I2CWait); //hold time ++ ++ SetDir_ClkData(OUTPUT,INPUT); //clock low, data input ++ for (mask=0x80; mask; mask>>=1) ++ { ++ // Disable Write SDA, Drive SCL to LOW ++ SetDir_Clk(OUTPUT); //clock low ++ udelay(LongBusWait); ++ ++ // Enable Write SCL, Drive SCL to HIGH ++ SetDir_Clk(INPUT); //clock high ++ udelay(I2CWait); ++ ++ // Read data bits from SDA ++ if (GPBIT_TEST(I2C_DATA)) byRet |= mask; //sample data bit ++ } ++ ++ SetDir_Clk(OUTPUT); //clock low ++ udelay(I2CWait); //let them stop driving data line ++ ++ if (ack) { ++ SetDir_ClkData(OUTPUT,OUTPUT); //clock low, data low for ack ++ } ++ udelay(I2CWait); ++ SetDir_Clk(INPUT); //clock high ++ udelay(I2CWait); //wait ack/noack phase ++ return byRet; ++ ++} ++ ++int I2CStart(int SlaveAddress) ++{ ++ int ret; ++ udelay(I2CWait); ++ // Enable Write SDA and Write SCL, and drive them high ++ SetDir_ClkData(INPUT,INPUT); ++ SetVal_ClkData(0,0); //they float high anyway ++ udelay(StartBusWait); ++ ++ // Drive Data ++ SetDir_ClkData(INPUT,OUTPUT); //drive data low, (high to low transition on data, while clock high is start signal) ++ udelay(StartBusWait); ++ ++ ret = WriteI2C(SlaveAddress); ++ if (ret) { ++ printf( "I2CStart failed write of device address\n" ); ++ } ++ return ret; ++} ++ ++#define M41T81S_SlaveAddrWrite 0xd0 ++#define M41T81S_SlaveAddrRead 0xd1 ++ ++#define M_HUNDREDTHS 0 //00-99 BCD ++#define M_SECONDS 1 //00-59 BCD, bit 7 ST (oscillator is stopped bit) ++#define M_MINUTES 2 //00-59 BCD ++#define M_HOURS 3 //high 2 bits are CENTURY, low 6 BCD 00-23 ++#define M_WEEKDAY 4 //01-07 ++#define M_DAY 5 //01-31 BCD ++#define M_MONTH 6 //01-12 BCD ++#define M_YEAR 7 //00-99 BCD ++#define M_CALIBRATION 8 ++#define M_WATCHDOG 9 ++#define M_ALARM_MOTH 0x0a //01-12 BCD, high 3 bits enable ++#define M_ALARM_DAY 0x0b //01-31 BCD. high 2 bits RPT4, RPT5 ++#define M_ALARM_HOUR 0x0c //00-23 BCD, high 2 bits RPT3, HT ++#define M_ALARM_MINUTES 0x0d //00-59 BCD, high bit RPT2 ++#define M_ALARM_SECONDS 0x0e //00-59 BCD, high bit RPT1 ++#define M_FLAGS 0x0f //bit 7(WDF), 6(AF), 4(BL), 2(OF) ++#define M_SQW 0x13 //bit 7(RS3), 6(RS2), 5(RS1), 4(RS0) ++ ++//M_FLAGS bit mask definitions ++#define MF_WDF 0x80 //Watchdog flag ++#define MF_AF 0x40 //Alarm flag ++#define MF_BL 0x10 //Battery low ++#define MF_OF 0x04 //Oscillator fail ++static int bcd(int val,int low, int high) ++{ ++ int tens = val>>4; ++ int ones = val & 0xf; ++ if ((tens > 9) || (ones > 9)) return -1; ++ val = (tens*10) + ones; ++ if ((val < low) || (val > high)) return -1; ++ return val; ++} ++static unsigned char toBcd(int val) ++{ ++ int tens = val/10; ++ int rem = val - (tens*10); ++ if (tens >= 10) tens = tens % 10; ++ return (tens<<4) | rem; ++} ++ ++static int GetTime(LPSYSTEMTIME lpst) ++{ ++ unsigned char b[M_YEAR+1]; ++ unsigned char * p = b; ++ unsigned char flags; ++ int i; ++ I2CInit(); //send a bunch of stops ++ ++ if (I2CStart(M41T81S_SlaveAddrWrite)) return -1; ++ if (WriteI2C(M_ALARM_HOUR)) return -1; ++ if (I2CStart(M41T81S_SlaveAddrRead)) return -1; ++ ++ b[0] = (unsigned char)ReadI2C(0); //read Halt bit ++ I2CStop(); ++ ++ if (b[0] & 0x40) { ++ //halted, restart it ++ if (I2CStart(M41T81S_SlaveAddrWrite)) return -1; ++ if (WriteI2C(M_ALARM_HOUR)) return -1; ++ if (WriteI2C(b[0] & ~0x40)) return -1; //clear Halt bit ++ I2CStop(); ++ } ++ ++ if (I2CStart(M41T81S_SlaveAddrWrite)) return -1; ++ if (WriteI2C(M_HUNDREDTHS)) return -1; ++ if (I2CStart(M41T81S_SlaveAddrRead)) return -1; ++ for (i=0; iwYear = ( (b[M_YEAR] > 0x99) || ((b[M_YEAR]&0xf) > 0x9) ) ? 0 : ++ (bcd(b[M_YEAR],0,99) + ( (b[M_HOURS]&0x40) ? 2100 : 2000)); ++ lpst->wMonth = bcd(b[M_MONTH],1,12); ++ lpst->wDayOfWeek = bcd(b[M_WEEKDAY],1,7); ++ lpst->wDay = bcd(b[M_DAY],1,31); ++ lpst->wHour = bcd(b[M_HOURS]&0x3f,0,23); ++ lpst->wMinute = bcd(b[M_MINUTES],0,59); ++ lpst->wSecond = bcd(b[M_SECONDS]&0x7f,0,59); ++ lpst->wMilliseconds = bcd(b[M_HUNDREDTHS],0,99)*10; ++ ++ if (b[M_SECONDS] & 0x80) { ++ //oscillator is stopped, restart it ++ if (I2CStart(M41T81S_SlaveAddrWrite)) return -1; ++ if (WriteI2C(M_SECONDS)) return -1; ++ if (WriteI2C(b[M_SECONDS] & ~0x80)) return -1; //clear stop bit ++ I2CStop(); ++ } ++ ++/* ++ printf( "M41T81S_GetTime: Year:%u, Month:%u, Day:%u, Hour:%u, Minute:%u, second:%u, milli:%u\n", ++ lpst->wYear, lpst->wMonth,lpst->wDay, lpst->wHour, lpst->wMinute, lpst->wSecond,lpst->wMilliseconds ); ++*/ ++ if (flags & MF_OF) { ++ if (I2CStart(M41T81S_SlaveAddrWrite)) return -1; ++ if (WriteI2C(M_FLAGS)) return -1; ++ if (WriteI2C(flags & ~MF_OF)) return -1; //clear oscillator failed bit ++ I2CStop(); ++ } ++ return 0; ++} ++ ++static int SetTime(LPSYSTEMTIME lpst) ++{ ++ unsigned char b[M_YEAR+1]; ++ unsigned char flags; ++ int i; ++ if (lpst->wYear < 2004) { ++ lpst->wYear = 2004; //don't allow it to be set in the far past. ++ lpst->wMonth = 1; ++ lpst->wDay = 1; ++ lpst->wDayOfWeek = 4; //Thursday Jan. 1, 2004 ++ } ++ ++/* printf( "M41T81S_SetTime: Year:%u, Month:%u, Day:%u, Hour:%u, Minute:%u, second:%u, milli:%u\n", ++ lpst->wYear, lpst->wMonth,lpst->wDay, lpst->wHour, lpst->wMinute, lpst->wSecond,lpst->wMilliseconds ); ++*/ ++ b[M_HUNDREDTHS] = 0; //toBcd(lpst->wMilliseconds/10); ++ b[M_SECONDS] = toBcd(lpst->wSecond); ++ b[M_MINUTES] = toBcd(lpst->wMinute); ++ b[M_HOURS] = toBcd(lpst->wHour) | ( ((lpst->wYear % 200) >= 100) ? 0xc0 : 0x80); ++ b[M_WEEKDAY] = (unsigned char)lpst->wDayOfWeek; ++ b[M_DAY] = toBcd(lpst->wDay); ++ b[M_MONTH] = toBcd(lpst->wMonth); ++ b[M_YEAR] = toBcd( lpst->wYear % 100); ++ ++ if (I2CStart(M41T81S_SlaveAddrWrite)) return -1; ++ if (WriteI2C(M_HUNDREDTHS)) return -1; ++ ++ for (i=M_HUNDREDTHS; i<=M_YEAR; i++) { ++ if (WriteI2C(b[i])) return -1; ++ } ++ I2CStop(); ++ ++ if (I2CStart(M41T81S_SlaveAddrWrite)) return -1; ++ if (WriteI2C(M_FLAGS)) return -1; ++ if (I2CStart(M41T81S_SlaveAddrRead)) return -1; ++ flags = (unsigned char)ReadI2C(0); //read flags ++ I2CStop(); ++ ++/* printf( "M41T81S_SetTime: Year:%u, Month:%u, Day:%u, Weekday:%u, Hour:%u, Minute:%u, second:%u flags:%u\n", ++ lpst->wYear, lpst->wMonth, lpst->wDay, lpst->wDayOfWeek, lpst->wHour, lpst->wMinute, lpst->wSecond, flags ); ++*/ ++ ++ if (flags & MF_OF) { ++ if (I2CStart(M41T81S_SlaveAddrWrite)) return -1; ++ if (WriteI2C(M_FLAGS)) return -1; ++ if (WriteI2C(flags & ~MF_OF)) return -1; //clear oscillator failed bit ++ I2CStop(); ++ } ++ return 0; ++} ++ ++int M41T81S_GetTime(LPSYSTEMTIME lpst) ++{ ++ int ret; ++ int reg = (READ_SM501_REG(SMIR_POWER_MODE_CONTROL) & 1) ? SMIR_PWRM1_GATE : SMIR_PWRM0_GATE; ++ int gate = READ_SM501_REG(reg); ++ if ((gate & 0x40)==0) STUFF_SM501_REG(reg, gate | 0x40); ++ STUFF_SM501_REG(SMIR_GPIO_32_63_CONTROL, ++ READ_SM501_REG(SMIR_GPIO_32_63_CONTROL) ++ & ~(GPBIT_MASK(I2C_CLK)|GPBIT_MASK(I2C_DATA))); // set as gpio controlled ++ udelay(LongBusWait); ++ ret = GetTime(lpst); ++ udelay(I2CWait); ++ SetDir_ClkData(INPUT,INPUT); //high clock, high data, just for safety, should be input already ++ if ((gate & 0x40)==0){ ++ STUFF_SM501_REG( reg, ++ READ_SM501_REG( reg ) ++ & ~0x40 ); //disable gpio if was originally ++ } ++ ++ return ret; ++} ++int M41T81S_SetTime(LPSYSTEMTIME lpst) ++{ ++ int ret; ++ int reg = (READ_SM501_REG(SMIR_POWER_MODE_CONTROL) & 1) ? SMIR_PWRM1_GATE : SMIR_PWRM0_GATE; ++ int gate = READ_SM501_REG(reg); ++ if ((gate & 0x40)==0) STUFF_SM501_REG(reg, gate | 0x40); ++ STUFF_SM501_REG(SMIR_GPIO_32_63_CONTROL, ++ READ_SM501_REG(SMIR_GPIO_32_63_CONTROL) ++ & ~(GPBIT_MASK(I2C_CLK)|GPBIT_MASK(I2C_DATA))); // set as gpio controlled ++ udelay(LongBusWait); ++ ret = SetTime(lpst); ++ udelay(I2CWait); ++ SetDir_ClkData(INPUT,INPUT); //high clock, high data, just for safety, should be input already ++ if ((gate & 0x40)==0){ ++ STUFF_SM501_REG( reg, ++ READ_SM501_REG( reg ) ++ & ~0x40 ); //disable gpio if was originally ++ } ++ ++ return ret; ++} ++ ++static int badTime( LPSYSTEMTIME lpst ) ++{ ++ return ( 1 > lpst->wMonth) ++ || ++ ( 12 < lpst->wMonth) ++ || ++ ( 1 > lpst->wDay) ++ || ++ ( 12 < lpst->wDay) ++ || ++ ( 24 <= lpst->wHour) ++ || ++ ( 60 <= lpst->wMinute) ++ || ++ ( 60 <= lpst->wSecond) ++ || ++ ( 1000 <= lpst->wMilliseconds ); ++} ++ ++static unsigned diffMs( LPSYSTEMTIME lpst1, ++ LPSYSTEMTIME lpst2 ) ++{ ++ return ( (long)lpst2->wMilliseconds-(long)lpst1->wMilliseconds ) ++ + ( (long)lpst2->wSecond-(long)lpst1->wSecond)*1000 ++ + ( (long)lpst2->wMinute-(long)lpst1->wMinute)*60000 ++ + ( (long)lpst2->wHour-(long)lpst1->wHour)*3600000 ; ++} ++ ++static void printTime( LPSYSTEMTIME t ) ++{ ++ printf( "%04u-%02u-%02u %02u:%02u:%02u.%02u", ++ t->wYear, t->wMonth, t->wDay, ++ t->wHour, t->wMinute, t->wSecond, t->wMilliseconds/10 ); ++} ++ ++// returns zero for success ++static int parseTime( LPSYSTEMTIME t, ++ char const *dateString, ++ char const *timeString ) ++{ ++ int rval = 1 ; ++ char *nextIn ; ++ unsigned long inVal = simple_strtoul( dateString, &nextIn, 10 ); ++ if( ( 0 == inVal ) || ( 2999 < inVal ) || ( '-' != *nextIn ) ) ++ goto bail ; ++ ++ nextIn++ ; ++ t->wYear = inVal ; ++ ++ inVal = simple_strtoul( nextIn, &nextIn, 10 ); ++ if( ( 0 == inVal ) || ( 12 < inVal ) || ( '-' != *nextIn ) ) ++ goto bail ; ++ ++ nextIn++ ; ++ t->wMonth = inVal ; ++ ++ inVal = simple_strtoul( nextIn, &nextIn, 10 ); ++ if( ( 0 == inVal ) || ( 31 < inVal ) || ( '\0' != *nextIn ) ) ++ goto bail ; ++ ++ nextIn++ ; ++ t->wDay = inVal ; ++ ++ t->wHour = 0 ; t->wMinute = 0 ; t->wSecond = 0 ; t->wMilliseconds = 0 ; ++ ++ if( 0 != timeString ) ++ { ++ inVal = simple_strtoul( timeString, &nextIn, 10 ); ++ if( ( 23 < inVal ) || ( ':' != *nextIn ) ) ++ goto bail ; ++ ++ nextIn++ ; ++ t->wHour = inVal ; ++ ++ inVal = simple_strtoul( nextIn, &nextIn, 10 ); ++ if( ( 59 < inVal ) || ( ':' != *nextIn ) ) ++ goto bail ; ++ ++ nextIn++ ; ++ t->wMinute = inVal ; ++ ++ inVal = simple_strtoul( nextIn, &nextIn, 10 ); ++ if( ( 59 < inVal ) || ( '.' != *nextIn ) ) ++ goto bail ; ++ ++ nextIn++ ; ++ t->wSecond = inVal ; ++ ++ inVal = simple_strtoul( nextIn, &nextIn, 10 ); ++ if( ( 99 < inVal ) || ( '\0' != *nextIn ) ) ++ goto bail ; ++ ++ nextIn++ ; ++ t->wMilliseconds = inVal*10 ; ++ rval = 0 ; ++ } ++ else ++ rval = 0 ; ++ ++bail: ++ return rval ; ++} ++ ++int do_rtc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ++{ ++ int rval = 1 ; ++ ++ if( 1 == argc ) ++ { ++ SYSTEMTIME t ; ++ int rval = M41T81S_GetTime( &t ); ++ if( 0 == rval ) ++ { ++ printTime(&t); ++ } ++ } ++ else if( ( 2 == argc ) && ( 0 == strcmp( "test", argv[1] ) ) ) ++ { ++ SYSTEMTIME t ; ++ int rval = M41T81S_GetTime( &t ); ++ if( 0 == rval ){ ++ if( badTime(&t) ){ ++ printf( "time not initialized...initializing\n" ); ++ t.wYear = 2006 ; ++ t.wMonth = 6 ; ++ t.wDay = 3 ; ++ memset( &t, 0, sizeof(t) ); ++ rval = M41T81S_SetTime(&t); ++ } ++ } ++ ++ if( 0 == rval ) ++ { ++ SYSTEMTIME t2 ; ++ udelay( 1000000 ); // wait a sec ++ rval = M41T81S_GetTime( &t2 ); ++ if( 0 == rval ) ++ { ++ unsigned diff = diffMs(&t,&t2); ++ ++ if( ( diff < 800 ) || ( diff > 1200 ) ) ++ { ++ rval = 1 ; // clock not moving or moving too fast (bad oscillator?) ++ if( 0 == diff ) ++ printf( "check RTC oscillator\n" ); ++#ifdef DEBUG ++ printf( "rtc test failed!\n" ++ "difftime: %u\n", diff ); ++ printf( "t1: " ); printTime( &t ); printf( "\n" ); ++ printf( "t2: " ); printTime( &t2 ); printf( "\n" ); ++#endif ++ } ++ } ++ } ++ } ++ else if( ( 2 == argc ) || ( 3 == argc ) ) ++ { ++ SYSTEMTIME t ; ++ if( 0 == parseTime( &t, argv[1], ( 3 == argc ) ? argv[2] : 0 ) ) ++ { ++ rval = M41T81S_SetTime(&t); ++ } ++ else ++ printf( "Invalid time format: use YYYY-MM-DD HH:MM:SS\n" ); ++ } ++ ++ return rval ; ++} ++ ++U_BOOT_CMD( ++ rtc, 127, 0, do_rtc, ++ "rtc - get/set/test RTC\n", ++ NULL ++); ++ ++ +diff -u -r --new-file u-boot-1.1.2/board/neon/sm501.h u-boot-1.1.2-neon/board/neon/sm501.h +--- u-boot-1.1.2/board/neon/sm501.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/neon/sm501.h 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,22 @@ ++#ifndef __SM501_H__ ++#define __SM501_H__ ++ ++/* ++ * sm501.h ++ * ++ * Defines constants and macros for the SM-501 Graphics Controller. ++ * ++ */ ++ ++extern unsigned long const mmioStart ; ++extern unsigned long const mmioLength ; ++ ++#define SMIR_GPIO_32_63_CONTROL 0x0000c ++#define SMIR_PWRM0_GATE 0x00040 ++#define SMIR_PWRM1_GATE 0x00048 ++#define SMIR_POWER_MODE_CONTROL 0x00054 ++ ++#define READ_SM501_REG( addr ) *( (unsigned long volatile *)((addr)+mmioStart) ) ++#define STUFF_SM501_REG( addr, value ) *( (unsigned long volatile *)((addr)+mmioStart) ) = (value) ++ ++#endif +diff -u -r --new-file u-boot-1.1.2/board/neon/u-boot.lds u-boot-1.1.2-neon/board/neon/u-boot.lds +--- u-boot-1.1.2/board/neon/u-boot.lds 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/neon/u-boot.lds 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,56 @@ ++/* ++ * (C) Copyright 2000 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++OUTPUT_ARCH(arm) ++ENTRY(_start) ++SECTIONS ++{ ++ . = 0x00000000; ++ ++ . = ALIGN(4); ++ .text : ++ { ++ cpu/pxa/start.o (.text) ++ cpu/pxa/ministart.o (.text) ++ *(.text) ++ } ++ ++ . = ALIGN(4); ++ .rodata : { *(.rodata) } ++ ++ . = ALIGN(4); ++ .data : { *(.data) } ++ ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss : { *(.bss) } ++ _end = .; ++} +diff -u -r --new-file u-boot-1.1.2/board/neon/u-bootmini.lds u-boot-1.1.2-neon/board/neon/u-bootmini.lds +--- u-boot-1.1.2/board/neon/u-bootmini.lds 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/board/neon/u-bootmini.lds 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,56 @@ ++/* ++ * (C) Copyright 2000 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++OUTPUT_ARCH(arm) ++ENTRY(StartUp) ++SECTIONS ++{ ++ . = 0x00000000; ++ ++ . = ALIGN(4); ++ .text : ++ { ++ cpu/pxa/minidebug.o (.text) ++ cpu/pxa/ministart.o (.text) ++ *(.text) ++ } ++ ++ . = ALIGN(4); ++ .rodata : { *(.rodata) } ++ ++ . = ALIGN(4); ++ .data : { *(.data) } ++ ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss : { *(.bss) } ++ _end = .; ++} +diff -u -r --new-file u-boot-1.1.2/common/cmd_boot.c u-boot-1.1.2-neon/common/cmd_boot.c +--- u-boot-1.1.2/common/cmd_boot.c 2003-10-09 01:26:14.000000000 +0200 ++++ u-boot-1.1.2-neon/common/cmd_boot.c 2007-08-11 21:07:20.000000000 +0200 +@@ -59,6 +59,7 @@ + */ + argv[0] = (char *)gd; + #endif ++ *((ulong*)0x40e00014) |= (1<<25); //make gpio89 an output(ac97_reset) + #if !defined(CONFIG_NIOS) + rc = ((ulong (*)(int, char *[]))addr) (--argc, &argv[1]); + #else +diff -u -r --new-file u-boot-1.1.2/common/cmd_bootm.c u-boot-1.1.2-neon/common/cmd_bootm.c +--- u-boot-1.1.2/common/cmd_bootm.c 2004-11-21 01:06:34.000000000 +0100 ++++ u-boot-1.1.2-neon/common/cmd_bootm.c 2007-08-11 21:07:20.000000000 +0200 +@@ -29,8 +29,6 @@ + #include + #include + #include +-#include +-#include + #include + #include + +@@ -73,10 +71,12 @@ + # define CHUNKSZ (64 * 1024) + #endif + ++#ifdef CONFIG_GZIP ++#include + int gunzip (void *, int, unsigned char *, unsigned long *); +- + static void *zalloc(void *, unsigned, unsigned); + static void zfree(void *, void *, unsigned); ++#endif + + #if (CONFIG_COMMANDS & CFG_CMD_IMI) + static int image_info (unsigned long addr); +@@ -327,12 +327,17 @@ + break; + case IH_COMP_GZIP: + printf (" Uncompressing %s ... ", name); ++#ifdef CONFIG_GZIP + if (gunzip ((void *)ntohl(hdr->ih_load), unc_len, + (uchar *)data, &len) != 0) { + puts ("GUNZIP ERROR - must RESET board to recover\n"); + SHOW_BOOT_PROGRESS (-6); + do_reset (cmdtp, flag, argc, argv); + } ++#else ++ printf( "GUNZIP not supported\n" ); ++#endif ++ + break; + #ifdef CONFIG_BZIP2 + case IH_COMP_BZIP2: +@@ -1221,6 +1226,8 @@ + printf ("%s %s %s (%s)", arch, os, type, comp); + } + ++#ifdef CONFIG_GZIP ++ + #define ZALLOC_ALIGNMENT 16 + + static void *zalloc(void *x, unsigned items, unsigned size) +@@ -1302,6 +1309,8 @@ + + return (0); + } ++#endif // CONFIG_GZIP ++ + + #ifdef CONFIG_BZIP2 + void bz_internal_error(int errcode) +diff -u -r --new-file u-boot-1.1.2/common/cmd_fat.c u-boot-1.1.2-neon/common/cmd_fat.c +--- u-boot-1.1.2/common/cmd_fat.c 2004-08-28 23:09:15.000000000 +0200 ++++ u-boot-1.1.2-neon/common/cmd_fat.c 2007-08-11 21:07:20.000000000 +0200 +@@ -30,6 +30,13 @@ + #include + #include + ++#define CONFIG_FATLOAD_TICKS ++#define CONFIG_FATLOAD_ADLER ++ ++#ifdef CONFIG_FATLOAD_ADLER ++#include ++#endif ++ + #if (CONFIG_COMMANDS & CFG_CMD_FAT) + + #undef DEBUG +@@ -83,6 +90,11 @@ + int dev=0; + int part=1; + char *ep; ++#ifdef CONFIG_FATLOAD_TICKS ++ ulong ticks1 ; ++ ulong ticks2 ; ++ ulong ticks3 ; ++#endif + + if (argc < 5) { + printf ("usage: fatload [bytes]\n"); +@@ -110,6 +122,10 @@ + count = simple_strtoul (argv[5], NULL, 16); + else + count = 0; ++#ifdef CONFIG_FATLOAD_TICKS ++ ticks1 = get_timer( 0 ); ++#endif ++ + size = file_fat_read (argv[4], (unsigned char *) offset, count); + + if(size==-1) { +@@ -117,7 +133,21 @@ + return 1; + } + +- printf ("\n%ld bytes read\n", size); ++ printf ("\n%ld bytes read", size); ++ ++#ifdef CONFIG_FATLOAD_TICKS ++ ticks2 = get_timer( 0 ); ++ printf( " in %lu ticks, (%lu ms)", (ticks2-ticks1), (ticks2-ticks1)/(CFG_HZ/1000) ); ++#endif ++ ++#ifdef CONFIG_FATLOAD_ADLER ++ printf( ", adler == 0x" ); ++ printf( "%08lx", adler32(0, (Bytef *)offset, size ) ); ++ ticks3 = get_timer( 0 ); ++ printf( " in %lu ticks, (%lu ms)", (ticks3-ticks2), (ticks3-ticks2)/(CFG_HZ/1000) ); ++#endif ++ ++ printf( "\n" ); + + sprintf(buf, "%lX", size); + setenv("filesize", buf); +diff -u -r --new-file u-boot-1.1.2/common/cmd_flash.c u-boot-1.1.2-neon/common/cmd_flash.c +--- u-boot-1.1.2/common/cmd_flash.c 2004-12-31 10:32:50.000000000 +0100 ++++ u-boot-1.1.2-neon/common/cmd_flash.c 2007-08-11 21:07:20.000000000 +0200 +@@ -507,7 +507,7 @@ + ); + + U_BOOT_CMD( +- erase, 3, 1, do_flerase, ++ erase, 3, 0, do_flerase, + "erase - erase FLASH memory\n", + "start end\n" + " - erase FLASH from addr 'start' to addr 'end'\n" +diff -u -r --new-file u-boot-1.1.2/common/cmd_lcdpanel.c u-boot-1.1.2-neon/common/cmd_lcdpanel.c +--- u-boot-1.1.2/common/cmd_lcdpanel.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/common/cmd_lcdpanel.c 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,265 @@ ++/* ++ * Module cmd_lcdpanel.cpp ++ * ++ * This module defines ... ++ * ++ * ++ * Change History : ++ * ++ * $Log: cmd_lcdpanel.c,v $ ++ * Revision 1.8 2005/09/19 13:15:59 ericn ++ * -allow zeros in most fields ++ * ++ * Revision 1.7 2005/08/22 16:30:32 ericn ++ * -update panel env var w/lcdp command ++ * ++ * Revision 1.6 2005/07/18 03:05:53 ericn ++ * -allow cmdline config of CRT ++ * ++ * Revision 1.5 2005/07/06 05:26:54 ericn ++ * -make lcdinfo command conditional on PXALCD ++ * ++ * Revision 1.4 2005/07/04 18:49:01 ericn ++ * -added lcdi command ++ * ++ * Revision 1.3 2005/06/02 04:01:30 ericn ++ * -allow zero value of pixclock (meaning slow one) ++ * ++ * Revision 1.2 2005/04/30 20:32:44 ericn ++ * -added disable cmd ++ * ++ * Revision 1.1 2005/04/09 17:49:15 ericn ++ * -Initial import ++ * ++ * ++ * Copyright Boundary Devices, Inc. 2005 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++ ++#include ++#include ++#if (CONFIG_COMMANDS & CFG_CMD_LCDPANEL) ++ ++#include ++#include ++ ++extern char console_buffer[]; /* console I/O buffer */ ++ ++static void print_panel_info( struct lcd_panel_info_t const *panel ) ++{ ++ printf( "------------------------------------\n" ++ "name : %s\n", panel->name ); ++ printf( "pixclock : %u\n", panel->pixclock ); ++ printf( "xres : %u\n", panel->xres ); ++ printf( "yres : %u\n", panel->yres ); ++ printf( "act_high : %u\n", panel->act_high ); ++ printf( "hsync_len : %u\n", panel->hsync_len ); ++ printf( "left_margin : %u\n", panel->left_margin ); ++ printf( "right_margin : %u\n", panel->right_margin ); ++ printf( "vsync_len : %u\n", panel->vsync_len ); ++ printf( "upper_margin : %u\n", panel->upper_margin ); ++ printf( "lower_margin : %u\n", panel->lower_margin ); ++ printf( "active : %u\n", panel->active ); ++ printf( "CRT ? %u\n", panel->crt ); ++} ++ ++static struct lcd_panel_info_t const *prompt_for_panel( void ) ++{ ++ struct lcd_panel_info_t *panel = (struct lcd_panel_info_t *)malloc(sizeof(struct lcd_panel_info_t)); ++ int bytesRead ; ++ ++ memset( panel, 0, sizeof(*panel)); ++ ++ bytesRead = readline( "name: " ); ++ if( 0 < bytesRead ) ++ { ++ panel->name = strdup( console_buffer ); ++ bytesRead = readline( "pixclock: " ); ++ if( 0 < bytesRead ) ++ { ++ char *endp; ++ ulong value = simple_strtoul( console_buffer, &endp, 0 ); ++ if( endp > console_buffer ) ++ { ++ panel->pixclock = value ; ++ bytesRead = readline( "xres: " ); ++ if( ( 0 < bytesRead ) ++ && ( 0 != ( value = simple_strtoul( console_buffer, &endp, 0 ) ) ) ++ && ( endp > console_buffer ) ) ++ { ++ panel->xres = value ; ++ bytesRead = readline( "yres: " ); ++ if( ( 0 < bytesRead ) ++ && ( 0 != ( value = simple_strtoul( console_buffer, &endp, 0 ) ) ) ++ && ( endp > console_buffer ) ) ++ { ++ panel->yres = value ; ++ bytesRead = readline( "act_high: " ); ++ if( ( 0 < bytesRead ) ++ && ( 1 >= ( value = simple_strtoul( console_buffer, &endp, 0 ) ) ) ++ && ( endp > console_buffer ) ) ++ { ++ panel->act_high = value ; ++ bytesRead = readline( "hsync_len: " ); ++ if( ( 0 < bytesRead ) ++ && ( 0 != ( value = simple_strtoul( console_buffer, &endp, 0 ) ) ) ++ && ( endp > console_buffer ) ) ++ { ++ panel->hsync_len = value ; ++ bytesRead = readline( "left_margin: " ); ++ value = simple_strtoul( console_buffer, &endp, 0 ); ++ if( ( 0 < bytesRead ) ++ && ( endp > console_buffer ) ) ++ { ++ panel->left_margin = value ; ++ bytesRead = readline( "right_margin: " ); ++ value = simple_strtoul( console_buffer, &endp, 0 ); ++ if( ( 0 < bytesRead ) ++ && ( endp > console_buffer ) ) ++ { ++ panel->right_margin = value ; ++ bytesRead = readline( "vsync_len: " ); ++ value = simple_strtoul( console_buffer, &endp, 0 ); ++ if( ( 0 < bytesRead ) ++ && ( endp > console_buffer ) ) ++ { ++ panel->vsync_len = value ; ++ bytesRead = readline( "upper_margin: " ); ++ value = simple_strtoul( console_buffer, &endp, 0 ); ++ if( ( 0 < bytesRead ) ++ && ( endp > console_buffer ) ) ++ { ++ panel->upper_margin = value ; ++ bytesRead = readline( "lower_margin: " ); ++ value = simple_strtoul( console_buffer, &endp, 0 ); ++ if( ( 0 < bytesRead ) ++ && ( endp > console_buffer ) ) ++ { ++ panel->lower_margin = value ; ++ bytesRead = readline( "active (0|1) : " ); ++ value = simple_strtoul( console_buffer, &endp, 0 ); ++ if( ( 0 < bytesRead ) && ( endp > console_buffer ) ) ++ { ++ panel->active = value ; ++ bytesRead = readline( "crt (0|1) : " ); ++ value = simple_strtoul( console_buffer, &endp, 0 ); ++ if( ( 0 < bytesRead ) ++ && ++ ( endp > console_buffer ) ) ++ { ++ panel->crt = value ; ++ print_panel_info( panel ); ++ return panel ; ++ } ++ } ++ } ++ } ++ } ++ } ++ } ++ } ++ } ++ } ++ } ++ } ++ } ++ } ++ ++ free( panel ); ++ ++ return 0 ; ++} ++ ++static int lcdpanel(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ++{ ++ if ( 1 == argc ) { ++ if( cur_lcd_panel ) ++ print_panel_info( cur_lcd_panel ); ++ else ++ printf( "no panel defined\n" ); ++ } ++ else { ++ struct lcd_panel_info_t const *panel = find_lcd_panel( argv[1] ); ++ if( panel ) { ++ printf( "found panel %s\n", panel->name ); ++ set_lcd_panel( panel ); ++ setenv( "panel", panel->name ); ++ } ++ else if( '+' == *argv[1] ) { ++ panel = prompt_for_panel(); ++ if( panel ) ++ { ++ print_panel_info( panel ); ++ set_lcd_panel( panel ); ++ } ++ } ++ else if( '?' == *argv[1] ) ++ { ++ int i ; ++ for( i = 0 ; i < num_lcd_panels ; i++ ) ++ print_panel_info( lcd_panels+i ); ++ } ++ else if( '-' == *argv[1] ) ++ { ++ disable_lcd_panel(); ++ printf( "panel disabled\n" ); ++ } ++ else ++ printf( "panel %s not found\n", argv[1] ); ++ } ++ ++ return 0; ++} ++ ++ ++U_BOOT_CMD( ++ lcdpanel, 2, 0, lcdpanel, ++ "lcdpanel [panelName|?|+|-]\n" ++ " init lcd panel with panel name\n" ++ " ? will display the supported panels\n" ++ " + will prompt for panel details\n" ++ " - will disable the panel\n", ++ NULL ++); ++ ++#ifdef PXALCD ++#include ++ ++static int lcdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ++{ ++ printf( "--> lcdinfo:\n" ++ "screen: %08lx\n" ++ "palette: %08lx/%u\n", ++ panel_info.pxa.screen, ++ panel_info.pxa.palette, ++ panel_info.pxa.palette_size ); ++ return 0 ; ++} ++ ++U_BOOT_CMD( ++ lcdinfo, 2, 0, lcdinfo, ++ "lcdinfo\n", ++ NULL ++); ++#endif ++ ++#endif /* CFG_CMD_LCDPANEL */ ++ ++ ++ ++ +diff -u -r --new-file u-boot-1.1.2/common/cmd_lcdpanel.h u-boot-1.1.2-neon/common/cmd_lcdpanel.h +--- u-boot-1.1.2/common/cmd_lcdpanel.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/common/cmd_lcdpanel.h 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,24 @@ ++#ifndef __CMD_LCDPANEL_H__ ++#define __CMD_LCDPANEL_H__ "$Id: cmd_lcdpanel.h,v 1.1 2005/04/09 17:49:16 ericn Exp $" ++ ++/* ++ * cmd_lcdpanel.h ++ * ++ * This header file declares ... ++ * ++ * ++ * Change History : ++ * ++ * $Log: cmd_lcdpanel.h,v $ ++ * Revision 1.1 2005/04/09 17:49:16 ericn ++ * -Initial import ++ * ++ * ++ * ++ * Copyright Boundary Devices, Inc. 2005 ++ */ ++ ++ ++ ++#endif ++ +diff -u -r --new-file u-boot-1.1.2/common/cmd_mmc.c u-boot-1.1.2-neon/common/cmd_mmc.c +--- u-boot-1.1.2/common/cmd_mmc.c 2003-07-01 23:07:07.000000000 +0200 ++++ u-boot-1.1.2-neon/common/cmd_mmc.c 2007-08-11 21:07:20.000000000 +0200 +@@ -43,4 +43,71 @@ + NULL + ); + ++int do_mmc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ++{ ++ if( 5 == argc ) ++ { ++ unsigned long args[4]; ++ unsigned i ; ++ for( i = 1 ; i < 5 ; i++ ) ++ { ++ char *endp ; ++ args[i-1] = simple_strtoul(argv[i], &endp, 16 ); ++ if( 0 != *endp ) ++ { ++ printf( "arg[%u] is not a valid hex number\n", i ); ++ break; ++ } ++ } ++ ++ if( 5 == i ) ++ { ++ uchar *resp = mmc_cmd( (ushort)args[0], ++ (ushort)args[1], ++ (ushort)args[2], ++ (ushort)args[3] ); ++ ushort numWords = 0 ; ++ switch( args[3] ) ++ { ++ case MMC_CMDAT_R1: ++ case MMC_CMDAT_R3: ++ numWords = 3; ++ break; ++ ++ case MMC_CMDAT_R2: ++ numWords = 8; ++ break; ++ ++ default: ++ printf( "Invalid response type %lu, options are [1,2,3]\n", args[3] ); ++ break; ++ } ++ ++ if( resp ) ++ { ++ for( i = 0 ; i < numWords*2 ; i++ ) ++ { ++ printf( "%02X ", resp[i] ); ++ } ++ printf( "\n" ); ++ } ++ else ++ printf( "no response\n" ); ++ } ++ } ++ else ++ printf ("Usage:\n%s\n", cmdtp->usage); ++ ++ return 0; ++} ++ ++extern uchar * ++mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat); ++ ++U_BOOT_CMD( ++ mmccmd, 5, 0, do_mmc_cmd, ++ "mmccmd - issue mmc command\n", ++ "mmccmd cmd# argh(hex) argl(hex) rsptype\n" ++); ++ + #endif /* CFG_CMD_MMC */ +diff -u -r --new-file u-boot-1.1.2/common/cmd_net.c u-boot-1.1.2-neon/common/cmd_net.c +--- u-boot-1.1.2/common/cmd_net.c 2004-06-09 14:42:26.000000000 +0200 ++++ u-boot-1.1.2-neon/common/cmd_net.c 2007-08-11 21:07:20.000000000 +0200 +@@ -46,6 +46,104 @@ + "[loadAddress] [bootfilename]\n" + ); + ++extern int get_rom_mac (char *v_rom_mac); ++extern int set_rom_mac (char const *v_rom_mac); ++ ++/* ++ * returns -1 if not valid hex ++ */ ++static int hexValue( char c ) ++{ ++ if( ( '0' <= c ) && ( '9' >= c ) ) ++ { ++ return c-'0' ; ++ } ++ else if( ( 'A' <= c ) && ( 'F' >= c ) ) ++ { ++ return c-'A'+10 ; ++ } ++ else if( ( 'a' <= c ) && ( 'f' >= c ) ) ++ { ++ return c-'a'+10 ; ++ } ++ else ++ return -1 ; ++} ++ ++// returns non-zero to indicate success ++static int parse_mac( char const *macString, // input ++ char *macaddr ) // output: not NULL-terminated ++{ ++ int i ; ++ for( i = 0 ; i < 6 ; i++ ) ++ { ++ char high, low, term ; ++ int highval, lowval ; ++ high = *macString++ ; ++ ++ if( ( 0 == high ) ++ || ++ ( 0 > ( highval = hexValue(high) ) ) ) ++ break ; ++ low = *macString++ ; ++ if( ( 0 == low ) ++ || ++ ( 0 > ( lowval = hexValue(low) ) ) ) ++ break ; ++ ++ term = *macString++ ; ++ if( 5 > i ) ++ { ++ if( ( '-' != term ) && ( ':' != term ) ) ++ break ; ++ } ++ else if( '\0' != term ) ++ break ; ++ ++ *macaddr++ = (highval<<4) | lowval ; ++ } ++ ++ return ( 6 == i ); ++} ++ ++int do_mac (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ++{ ++ if( 2 == argc ) ++ { ++ char mac[6]; ++ if( parse_mac( argv[1], mac ) ) ++ { ++ printf( "setting mac address to %02x:%02x:%02x:%02x:%02x:%02x\n", ++ mac[0],mac[1],mac[2],mac[3],mac[4],mac[5] ); ++ if( set_rom_mac( mac ) ) ++ printf( "done\n" ); ++ else ++ printf( "Error setting mac address\n" ); ++ } ++ else ++ printf( "Error parsing mac: use form NN:NN:NN:NN:NN:NN\n" ); ++ } ++ else ++ { ++ char mac[6]; ++ if( get_rom_mac( mac ) ) ++ printf( "mac address %02x:%02x:%02x:%02x:%02x:%02x\n", ++ mac[0],mac[1],mac[2],mac[3],mac[4],mac[5] ); ++ else if( 0xFF == mac[0] ) ++ printf( "MAC has not been programmed\n" ); ++ else ++ printf( "error reading mac\n" ); ++ } ++ return 0 ; ++} ++ ++U_BOOT_CMD( ++ mac, 3, 1, do_mac, ++ "mac\t- read/write mac address\n", ++ "- supply a parameter of the form NN:NN:NN:NN:NN:NN to set" ++); ++ ++ + int do_tftpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) + { + return netboot_common (TFTP, cmdtp, argc, argv); +diff -u -r --new-file u-boot-1.1.2/common/cmd_not.c u-boot-1.1.2-neon/common/cmd_not.c +--- u-boot-1.1.2/common/cmd_not.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/common/cmd_not.c 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,55 @@ ++/* ++ * (C) Copyright 2006 ++ * Eric Nelson, Boundary Devices ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++ ++#if (CONFIG_COMMANDS & CFG_CMD_NOT) ++ ++int do_not (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ++{ ++ int rval = 1 ; ++ if( 1 < argc ) ++ { ++ cmd_tbl_t *cmd = find_cmd(argv[1]); ++ if( cmd ) ++ { ++ rval = ( 0 == cmd->cmd(cmd, flag, argc-1, argv+1) ); ++ } ++ else ++ printf( "command %s not found\n", argv[1] ); ++ } ++ else ++ printf( "Usage not command [..params]\n" ); ++ ++ return rval ; ++} ++ ++U_BOOT_CMD( ++ not, 127, 0, do_not, ++ "not - negate a command\n", ++ NULL ++); ++ ++#endif /* CONFIG_COMMANDS & CFG_CMD_NOT */ +diff -u -r --new-file u-boot-1.1.2/common/cmd_nvedit.c u-boot-1.1.2-neon/common/cmd_nvedit.c +--- u-boot-1.1.2/common/cmd_nvedit.c 2004-09-30 00:55:14.000000000 +0200 ++++ u-boot-1.1.2-neon/common/cmd_nvedit.c 2007-08-11 21:07:20.000000000 +0200 +@@ -487,16 +487,21 @@ + { + int i, nxt; + ++// printf ("before WATCHDOG_RESET\n"); + WATCHDOG_RESET(); ++// printf ("after WATCHDOG_RESET\n"); + + for (i=0; env_get_char(i) != '\0'; i=nxt+1) { + int val; + ++// printf ("i= %i\n", i); + for (nxt=i; env_get_char(nxt) != '\0'; ++nxt) { + if (nxt >= CFG_ENV_SIZE) { + return (NULL); + } ++// putc(env_get_char(nxt)); + } ++// printf ("\n"); + if ((val=envmatch(name, i)) < 0) + continue; + return (env_get_addr(val)); +diff -u -r --new-file u-boot-1.1.2/common/command.c u-boot-1.1.2-neon/common/command.c +--- u-boot-1.1.2/common/command.c 2004-04-18 19:39:39.000000000 +0200 ++++ u-boot-1.1.2-neon/common/command.c 2007-08-11 21:07:20.000000000 +0200 +@@ -27,6 +27,9 @@ + + #include + #include ++#ifdef CONFIG_LCD ++#include "lcd.h" ++#endif + + int + do_version (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +@@ -74,6 +77,41 @@ + " - echo args to console; \\c suppresses newline\n" + ); + ++#ifdef CONFIG_LCD ++ ++int ++do_lecho (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ++{ ++ int i, putnl = 1; ++ ++ for (i = 1; i < argc; i++) { ++ char *p = argv[i], c; ++ ++ if (i > 1) ++ putc(' '); ++ while ((c = *p++) != '\0') { ++ if (c == '\\' && *p == 'c') { ++ putnl = 0; ++ p++; ++ } else { ++ lcd_putc(c); ++ } ++ } ++ } ++ ++ if (putnl) ++ lcd_putc('\n'); ++ return 0; ++} ++ ++U_BOOT_CMD( ++ lecho, CFG_MAXARGS, 1, do_lecho, ++ "lecho - echo args to lcd\n", ++ "[args..]\n" ++ " - echo args to lcd; \\c suppresses newline\n" ++); ++#endif ++ + #ifdef CFG_HUSH_PARSER + + int +diff -u -r --new-file u-boot-1.1.2/common/env_flash.c u-boot-1.1.2-neon/common/env_flash.c +--- u-boot-1.1.2/common/env_flash.c 2004-03-14 02:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/common/env_flash.c 2007-08-11 21:07:20.000000000 +0200 +@@ -83,6 +83,10 @@ + #define OBSOLETE_FLAG 0 + #endif /* CFG_ENV_ADDR_REDUND */ + ++#ifdef CFG_ENV_IS_IN_FLASH ++static env_t *flash_addr_new = (env_t *)CFG_ENV_ADDR ; ++#endif ++ + extern uchar default_environment[]; + extern int default_environment_size; + +diff -u -r --new-file u-boot-1.1.2/common/fnmatch.c u-boot-1.1.2-neon/common/fnmatch.c +--- u-boot-1.1.2/common/fnmatch.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/common/fnmatch.c 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,166 @@ ++/* ++ * (C) Copyright 2005 ++ * Boundary Devices ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++ ++/* Some file systems are case-insensitive. If FOLD_FN_CHAR is ++ #defined, it maps the character C onto its "canonical" form. In a ++ case-insensitive system, it would map all alphanumeric characters ++ to lower case. Under Windows NT, / and \ are both path component ++ separators, so FOLD_FN_CHAR would map them both to /. */ ++#define FOLD_FN_CHAR(c) (c) ++ ++ ++int fnmatch(const char *pattern, const char *string, int flags) ++{ ++ register const char *p = pattern, *n = string; ++ register char c; ++ ++ while ((c = *p++) != '\0') ++ { ++ switch (c) ++ { ++ case '?': ++ if (*n == '\0') ++ return FNM_NOMATCH; ++ else if ((flags & FNM_PATHNAME) && *n == '/') ++ return FNM_NOMATCH; ++ else if ((flags & FNM_PERIOD) && *n == '.' && ++ (n == string || ((flags & FNM_PATHNAME) && n[-1] == '/'))) ++ return FNM_NOMATCH; ++ break; ++ ++ case '\\': ++ if (!(flags & FNM_NOESCAPE)) ++ c = *p++; ++ if (FOLD_FN_CHAR (*n) != FOLD_FN_CHAR (c)) ++ return FNM_NOMATCH; ++ break; ++ ++ case '*': ++ if ((flags & FNM_PERIOD) && *n == '.' && ++ (n == string || ((flags & FNM_PATHNAME) && n[-1] == '/'))) ++ return FNM_NOMATCH; ++ ++ for (c = *p++; c == '?' || c == '*'; c = *p++, ++n) ++ if (((flags & FNM_PATHNAME) && *n == '/') || ++ (c == '?' && *n == '\0')) ++ return FNM_NOMATCH; ++ ++ if (c == '\0') ++ return 0; ++ ++ { ++ char c1 = (!(flags & FNM_NOESCAPE) && c == '\\') ? *p : c; ++ for (--p; *n != '\0'; ++n) ++ if ((c == '[' || FOLD_FN_CHAR (*n) == FOLD_FN_CHAR (c1)) && ++ fnmatch(p, n, flags & ~FNM_PERIOD) == 0) ++ return 0; ++ return FNM_NOMATCH; ++ } ++ ++ case '[': ++ { ++ /* Nonzero if the sense of the character class is inverted. */ ++ register int not; ++ ++ if (*n == '\0') ++ return FNM_NOMATCH; ++ ++ if ((flags & FNM_PERIOD) && *n == '.' && ++ (n == string || ((flags & FNM_PATHNAME) && n[-1] == '/'))) ++ return FNM_NOMATCH; ++ ++ not = (*p == '!' || *p == '^'); ++ if (not) ++ ++p; ++ ++ c = *p++; ++ for (;;) ++ { ++ register char cstart = c, cend = c; ++ ++ if (!(flags & FNM_NOESCAPE) && c == '\\') ++ cstart = cend = *p++; ++ ++ if (c == '\0') ++ /* [ (unterminated) loses. */ ++ return FNM_NOMATCH; ++ ++ c = *p++; ++ ++ if ((flags & FNM_PATHNAME) && c == '/') ++ /* [/] can never match. */ ++ return FNM_NOMATCH; ++ ++ if (c == '-' && *p != ']') ++ { ++ cend = *p++; ++ if (!(flags & FNM_NOESCAPE) && cend == '\\') ++ cend = *p++; ++ if (cend == '\0') ++ return FNM_NOMATCH; ++ c = *p++; ++ } ++ ++ if (*n >= cstart && *n <= cend) ++ goto matched; ++ ++ if (c == ']') ++ break; ++ } ++ if (!not) ++ return FNM_NOMATCH; ++ break; ++ ++ matched:; ++ /* Skip the rest of the [...] that already matched. */ ++ while (c != ']') ++ { ++ if (c == '\0') ++ /* [... (unterminated) loses. */ ++ return FNM_NOMATCH; ++ ++ c = *p++; ++ if (!(flags & FNM_NOESCAPE) && c == '\\') ++ /* 1003.2d11 is unclear if this is right. %%% */ ++ ++p; ++ } ++ if (not) ++ return FNM_NOMATCH; ++ } ++ break; ++ ++ default: ++ if (FOLD_FN_CHAR (c) != FOLD_FN_CHAR (*n)) ++ return FNM_NOMATCH; ++ } ++ ++ ++n; ++ } ++ ++ if (*n == '\0') ++ return 0; ++ ++ return FNM_NOMATCH; ++} ++ +diff -u -r --new-file u-boot-1.1.2/common/lcd.c u-boot-1.1.2-neon/common/lcd.c +--- u-boot-1.1.2/common/lcd.c 2004-12-10 12:40:50.000000000 +0100 ++++ u-boot-1.1.2-neon/common/lcd.c 2007-08-11 21:07:20.000000000 +0200 +@@ -41,7 +41,7 @@ + #endif + #include + +-#if defined(CONFIG_PXA250) ++#if defined(CONFIG_PXA250) || defined(CONFIG_PXA270) + #include + #endif + +@@ -94,8 +94,46 @@ + static int lcd_getfgcolor (void); + #endif /* NOT_USED_SO_FAR */ + +-/************************************************************************/ ++static int luminance( int red, int green, int blue ) ++{ ++ // ++ // I've seen a couple of different algorithms here: ++ // (max+min)/2 ++/* ++ ++ int max = MAX( red, MAX( green, blue ) ); ++ int min = MIN( red, MIN( green, blue ) ); ++ return (max+min)/2 ; ++*/ ++ ++ // A more mathematically-correct version ++// return (int)(c.R*0.3 + c.G*0.59+ c.B*0.11); ++ ++ // Just return 'green' ++ // return green; ++ ++ // and one that uses shifts and adds to come close to the above ++ // ++ // red = 5/16= 0.3125 == 1/4 + 1/16 ++ // green = 9/16= 0.5625 == 1/2 + 1/16 ++ // blue = 1/8 = 0.125 ++ // ++ if( 0 < red ) ++ red = (red>>2) + (red>>4); ++ else ++ red = 0 ; ++ if( 0 < green ) ++ green = (green>>1) + (green>>4) ; ++ else ++ green = 0 ; ++ if( 0 < blue ) ++ blue = blue >> 3 ; ++ else ++ blue = 0 ; ++ return red+green+blue ; ++} + ++/************************************************************************/ + /*----------------------------------------------------------------------*/ + + static void console_scrollup (void) +@@ -221,10 +259,10 @@ + uchar *dest; + ushort off, row; + +- dest = (uchar *)(lcd_base + y * lcd_line_length + x * (1 << LCD_BPP) / 8); ++ dest = (uchar *)(lcd_base + y * panel_info.vl_lcd_line_length + x * (1 << LCD_BPP) / 8); + off = x * (1 << LCD_BPP) % 8; + +- for (row=0; row < VIDEO_FONT_HEIGHT; ++row, dest += lcd_line_length) { ++ for (row=0; row < VIDEO_FONT_HEIGHT; ++row, dest += panel_info.vl_lcd_line_length) { + uchar *s = str; + uchar *d = dest; + int i; +@@ -337,8 +375,6 @@ + + lcd_base = (void *)(gd->fb_base); + +- lcd_line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; +- + lcd_init (lcd_base); /* LCD initialization */ + + /* Device initialization */ +@@ -389,7 +425,7 @@ + /* set framebuffer to background color */ + memset ((char *)lcd_base, + COLOR_MASK(lcd_getbgcolor()), +- lcd_line_length*panel_info.vl_row); ++ panel_info.vl_lcd_line_length*panel_info.vl_row); + #endif + /* Paint the logo and retrieve LCD base address */ + debug ("[LCD] Drawing the logo...\n"); +@@ -500,12 +536,13 @@ + #ifdef CONFIG_LCD_LOGO + void bitmap_plot (int x, int y) + { +- ushort *cmap; ++ PALETTEVAL_TYPE *cmap; + ushort i, j; + uchar *bmap; + uchar *fb; + ushort *fb16; +-#if defined(CONFIG_PXA250) ++ ++#if defined(PXALCD) + struct pxafb_info *fbi = &panel_info.pxa; + #elif defined(CONFIG_MPC823) + volatile immap_t *immr = (immap_t *) CFG_IMMR; +@@ -514,17 +551,18 @@ + + debug ("Logo: width %d height %d colors %d cmap %d\n", + BMP_LOGO_WIDTH, BMP_LOGO_HEIGHT, BMP_LOGO_COLORS, +- sizeof(bmp_logo_palette)/(sizeof(ushort))); ++ sizeof(bmp_logo_palette)/(sizeof(PALETTEVAL_TYPE))); + + bmap = &bmp_logo_bitmap[0]; +- fb = (char *)(lcd_base + y * lcd_line_length + x); ++ fb = (char *)(lcd_base + y * panel_info.vl_lcd_line_length + x); + + if (NBITS(panel_info.vl_bpix) < 12) { + /* Leave room for default color map */ +-#if defined(CONFIG_PXA250) +- cmap = (ushort *)fbi->palette; ++#if defined(PXALCD) ++ cmap = (PALETTEVAL_TYPE *)fbi->palette; + #elif defined(CONFIG_MPC823) + cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]); ++#elif defined(CONFIG_SM501) + #endif + + WATCHDOG_RESET(); +@@ -532,10 +570,13 @@ + /* Set color map */ + for (i=0; i<(sizeof(bmp_logo_palette)/(sizeof(ushort))); ++i) { + ushort colreg = bmp_logo_palette[i]; +-#ifdef CFG_INVERT_COLORS +- *cmap++ = 0xffff - colreg; ++#if defined(CONFIG_SM501) + #else ++ #ifdef CFG_INVERT_COLORS ++ *cmap++ = 0xffff - colreg; ++ #else + *cmap++ = colreg; ++ #endif + #endif + } + +@@ -548,7 +589,7 @@ + } + } + else { /* true color mode */ +- fb16 = (ushort *)(lcd_base + y * lcd_line_length + x); ++ fb16 = (ushort *)(lcd_base + y * panel_info.vl_lcd_line_length + x); + for (i=0; iheader.signature[1]=='M'))) { + printf ("Error: no valid bmp image at %lx\n", bmp_image); + return 1; +-} ++ } + + width = le32_to_cpu (bmp->header.width); + height = le32_to_cpu (bmp->header.height); +@@ -616,33 +666,64 @@ + (int)width, (int)height, (int)colors); + + if (bpix==8) { +-#if defined(CONFIG_PXA250) +- cmap = (ushort *)fbi->palette; ++#if defined(PXALCD) ++ cmap = (PALETTEVAL_TYPE *)fbi->palette; + #elif defined(CONFIG_MPC823) + cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]); ++#elif defined(CONFIG_SM501) ++ cmap = (uchar *)paletteRegs ; + #else + # error "Don't know location of color map" + #endif + + /* Set color map */ + for (i=0; icolor_table[i]; ++#if defined(CONFIG_SM501) ++ *cmap++ = cte.blue ; ++ *cmap++ = cte.green ; ++ *cmap++ = cte.red ; ++ *cmap++ = 0 ; ++#elif defined(CONFIG_PXA270) && defined(PXALCD) ++ *cmap = 0xFF000000 ; ++ *cmap |= cte.red << 16 ; ++ *cmap |= cte.green << 8 ; ++ *cmap |= cte.blue ; ++ *cmap++ ; ++#else + ushort colreg = + ( ((cte.red) << 8) & 0xf800) | + ( ((cte.green) << 4) & 0x07e0) | + ( (cte.blue) & 0x001f) ; +- +-#ifdef CFG_INVERT_COLORS ++ #ifdef CFG_INVERT_COLORS + *cmap = 0xffff - colreg; +-#else ++ #else + *cmap = colreg; +-#endif +-#if defined(CONFIG_PXA250) ++ #endif ++ #if defined(PXALCD) + cmap++; +-#elif defined(CONFIG_MPC823) ++ #elif defined(CONFIG_MPC823) + cmap--; ++ #endif + #endif ++ lum = luminance( cte.red, cte.green, cte.blue ); ++ if( lum > maxLum ) ++ { ++ maxLum = lum ; ++ bgCol = i ; ++ } ++ ++ if( lum < minLum ) ++ { ++ minLum = lum ; ++ fgCol = i ; ++ } + } ++ ++ printf( "bgcolor %u, fg %u\n", bgCol, fgCol ); ++ lcd_color_fg = fgCol ; ++ lcd_color_bg = bgCol ; + } + + padded_line = (width&0x3) ? ((width&~0x3)+4) : (width); +@@ -653,16 +734,16 @@ + + bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset); + fb = (uchar *) (lcd_base + +- (y + height - 1) * lcd_line_length + x); ++ (y + height - 1) * panel_info.vl_lcd_line_length + x); + for (i = 0; i < height; ++i) { + for (j = 0; j < width ; j++) +-#if defined(CONFIG_PXA250) ++#if defined(CONFIG_PXA250) || defined(CONFIG_PXA270) + *(fb++)=*(bmap++); + #elif defined(CONFIG_MPC823) + *(fb++)=255-*(bmap++); + #endif +- bmap += (width - padded_line); +- fb -= (width + lcd_line_length); ++ bmap += (padded_line-width); ++ fb -= (width + panel_info.vl_lcd_line_length); + } + + return (0); +@@ -735,7 +816,7 @@ + #endif /* LCD_INFO */ + + #if defined(CONFIG_LCD_LOGO) && !defined(LCD_INFO_BELOW_LOGO) +- return ((void *)((ulong)lcd_base + BMP_LOGO_HEIGHT * lcd_line_length)); ++ return ((void *)((ulong)lcd_base + BMP_LOGO_HEIGHT * panel_info.vl_lcd_line_length)); + #else + return ((void *)lcd_base); + #endif /* CONFIG_LCD_LOGO */ +diff -u -r --new-file u-boot-1.1.2/common/lcd_panels.c u-boot-1.1.2-neon/common/lcd_panels.c +--- u-boot-1.1.2/common/lcd_panels.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/common/lcd_panels.c 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,286 @@ ++/* ++ * Module lcd_panels.cpp ++ * ++ * This module defines the num_lcd_panels and lcd_panels ++ * constants as declared in lcd_panels.h ++ * ++ * Change History : ++ * ++ * $Log: lcd_panels.c,v $ ++ * Revision 1.9 2006/05/23 18:46:39 ericn ++ * -added hitachi_wxga panel ++ * ++ * Revision 1.8 2005/09/19 13:15:43 ericn ++ * -updated sharp_qvga timing ++ * ++ * Revision 1.7 2005/07/18 03:05:35 ericn ++ * -update crt1024x768 timings ++ * ++ * Revision 1.6 2005/07/07 03:42:22 tkisky ++ * -make my CRT 1024x768 display work ++ * ++ * Revision 1.5 2005/06/02 04:02:39 ericn ++ * -added qvga_portrait ++ * ++ * Revision 1.4 2005/05/15 18:59:00 tkisky ++ * -change polarity of hitachi_wvga ++ * ++ * Revision 1.3 2005/05/03 15:32:11 ericn ++ * -fast pixclock for hvga, remove redundant 1024x768 ++ * ++ * Revision 1.2 2005/04/30 20:33:22 ericn ++ * -added CRT support ++ * ++ * Revision 1.1 2005/04/09 17:49:17 ericn ++ * -Initial import ++ * ++ * ++ * Copyright Boundary Devices, Inc. 2005 ++ */ ++ ++ ++#include "lcd_panels.h" ++#include ++ ++/* ++Settings for Hitachi 5.7 ++ PANEL_HORIZONTAL_TOTAL, 01c00160); // should be 34+320+1+64-1= 418 = 0x1A2 (Hex) ++ + 0x13f+16 ++ PANEL_HORIZONTAL_SYNC, 00400161); hsync_len == 64 lmargin=0x161-0x13f=34 ++ PANEL_VERTICAL_TOTAL, 0x010800f0); ++ PANEL_VERTICAL_SYNC, 0x00020104); vsync=2, upper_margin=0x0104-0xf0-1= 19 ++ ++In bdlogo.bmp - offset 436 is pixel data ++ ++Sharp 5.7 active ++ ++ STUFFREG( hTotalReg, 0x01800140 ); // should be 16+320+1+8-1 == 0x158 ++ + 0x13f (width-1) ++ STUFFREG( hSyncReg, 0x0008014f ); hsync_len == 8 lmargin=0x14f-0x13f=16 ++ STUFFREG( vTotalReg, 0x010700F0 ); ++ STUFFREG( vSyncReg, 0x00020100 ); vsync=2, upper_margin=0x0100-0xf0+1= 17 ++ ++static unsigned const hTotalReg = 0x00080024 ; // 015F0140 ++static unsigned const hSyncReg = 0x00080028 ; // 0008014f ++static unsigned const vTotalReg = 0x0008002c ; // 010700F0 ++static unsigned const vSyncReg = 0x00080030 ; // 000200FE ++ ++const unsigned int sm501_list2[]={0x0fe80000, ++dispctrl 0x0F013104, // 0f0d0105 ++pan 0x00000000, ++colorkey 0x00000000, ++fbaddr 0x00000000, ++offsetww ((LCD_XRES)<<16)+(LCD_XRES), ++fbwidth (LCD_XRES<<16), ++fbheight (LCD_YRES<<16), ++tllocate 0x00000000, ++brlocate ((LCD_YRES-1)<<16)+(LCD_XRES-1), ++htotal ((LCD_BEGIN_OF_LINE_WAIT_COUNT+ ++ LCD_XRES+ ++ LCD_END_OF_LINE_WAIT_COUNT+ ++ LCD_HORIZONTAL_SYNC_PULSE_WIDTH-1)<<16) ++ +(LCD_XRES-1), ++hsync (LCD_HORIZONTAL_SYNC_PULSE_WIDTH<<16) ++ +(LCD_XRES+LCD_BEGIN_OF_LINE_WAIT_COUNT-1), ++vtotal ((LCD_BEGIN_FRAME_WAIT_COUNT+ ++ LCD_YRES+ ++ LCD_END_OF_FRAME_WAIT_COUNT+ ++ LCD_VERTICAL_SYNC_PULSE_WIDTH-1)<<16) ++ +(LCD_YRES-1), ++vsync (LCD_VERTICAL_SYNC_PULSE_WIDTH<<16) ++ +(LCD_YRES+LCD_BEGIN_FRAME_WAIT_COUNT-1)}; ++*/ ++ ++static struct lcd_panel_info_t const lcd_panels_[] = { ++ ++ /* char const *name */ { "hitachi_qvga" ++ /* unsigned long pixclock */ , 0 ++ /* unsigned short xres */ , 320 ++ /* unsigned short yres */ , 240 ++ /* unsigned char act_high */ , 1 ++ /* unsigned char hsync_len */ , 64 ++ /* unsigned char left_margin */ , 1 ++ /* unsigned char right_margin */ , 16 ++ /* unsigned char vsync_len */ , 20 ++ /* unsigned char upper_margin */ , 8 ++ /* unsigned char lower_margin */ , 3 ++ /* unsigned char active */ , 1 ++ /* unsigned char crt */ , 0 } ++ ++ /* char const *name */ , { "sharp_qvga" ++ /* unsigned long pixclock */ , 0 ++ /* unsigned short xres */ , 320 /* , 320 */ ++ /* unsigned short yres */ , 240 /* , 240 */ ++ /* unsigned char act_high */ , 1 /* , 1 */ ++ /* unsigned char hsync_len */ , 20 /* , 8 */ ++ /* unsigned char left_margin */ , 1 /* , 16 */ ++ /* unsigned char right_margin */ , 30 /* , 1 */ ++ /* unsigned char vsync_len */ , 4 /* , 20 */ ++ /* unsigned char upper_margin */ , 17 /* , 17 */ ++ /* unsigned char lower_margin */ , 3 /* , 3 */ ++ /* unsigned char active */ , 1 /* , 1 */ ++ /* unsigned char crt */ , 0 } ++ ++ /* char const *name */ , { "qvga_portrait" ++ /* unsigned long pixclock */ , 0 ++ /* unsigned short xres */ , 240 ++ /* unsigned short yres */ , 320 ++ /* unsigned char act_high */ , 1 ++ /* unsigned char hsync_len */ , 64 ++ /* unsigned char left_margin */ , 34 ++ /* unsigned char right_margin */ , 1 ++ /* unsigned char vsync_len */ , 20 ++ /* unsigned char upper_margin */ , 8 ++ /* unsigned char lower_margin */ , 3 ++ /* unsigned char active */ , 1 ++ /* unsigned char crt */ , 0 ++ /* unsigned rotation */ , 90 } ++ ++ /* char const *name */ , { "hitachi_hvga" ++ /* unsigned long pixclock */ , 1 ++ /* unsigned short xres */ , 640 ++ /* unsigned short yres */ , 240 ++ /* unsigned char act_high */ , 1 ++ /* unsigned char hsync_len */ , 64 ++ /* unsigned char left_margin */ , 34 ++ /* unsigned char right_margin */ , 1 ++ /* unsigned char vsync_len */ , 20 ++ /* unsigned char upper_margin */ , 8 ++ /* unsigned char lower_margin */ , 3 ++ /* unsigned char active */ , 1 ++ /* unsigned char crt */ , 0 } ++ ++ /* char const *name */ , { "sharp_vga" ++ /* unsigned long pixclock */ , 1 ++ /* unsigned short xres */ , 640 ++ /* unsigned short yres */ , 480 ++ /* unsigned char act_high */ , 1 ++ /* unsigned char hsync_len */ , 64 ++ /* unsigned char left_margin */ , 60 ++ /* unsigned char right_margin */ , 60 ++ /* unsigned char vsync_len */ , 20 ++ /* unsigned char upper_margin */ , 34 ++ /* unsigned char lower_margin */ , 3 ++ /* unsigned char active */ , 1 ++ /* unsigned char crt */ , 0 } ++ ++ /* char const *name */ , { "hitachi_wvga" ++ /* unsigned long pixclock */ , 1 ++ /* unsigned short xres */ , 800 ++ /* unsigned short yres */ , 480 ++ /* unsigned char act_high */ , 1 ++ /* unsigned char hsync_len */ , 64 ++ /* unsigned char left_margin */ , 1 ++ /* unsigned char right_margin */ , 39 ++ /* unsigned char vsync_len */ , 20 ++ /* unsigned char upper_margin */ , 8 ++ /* unsigned char lower_margin */ , 3 ++ /* unsigned char active */ , 1 ++ /* unsigned char crt */ , 0 } ++// Note that you can use the nifty tool at the ++// following location to generate these values: ++// http://www.tkk.fi/Misc/Electronics/faq/vga2rgb/calc.html ++, { ++ name: "crt1024x768", ++ pixclock: 65000000, ++ xres: 1024, ++ yres: 768, ++ act_high : 0, ++ hsync_len: 136, ++ left_margin: 24, ++ right_margin: 160, ++ vsync_len: 6, ++ upper_margin: 3, ++ lower_margin: 29, ++ active : 0, ++ crt : 1 ++} ++, { ++ name: "hitachi_wxga", ++ pixclock: 1, ++ xres: 1024, ++ yres: 768, ++ act_high : 1, ++ hsync_len: 64, ++ left_margin: 1, ++ right_margin: 39, ++ vsync_len: 20, ++ upper_margin: 8, ++ lower_margin: 3, ++ active : 1, ++ crt : 0 ++} ++}; ++ ++/* ++. e ++typedef enum _polarity_t ++{ ++ POSITIVE, ++ NEGATIVE, ++} ++polarity_t; ++ ++typedef struct _mode_table_t ++{ ++ // Horizontal timing. ++ int horizontal_total; ++ int horizontal_display_end; ++ int horizontal_sync_start; ++ int horizontal_sync_width; ++ polarity_t horizontal_sync_polarity; ++ ++ // Vertical timing. ++ int vertical_total; ++ int vertical_display_end; ++ int vertical_sync_start; ++ int vertical_sync_height; ++ polarity_t vertical_sync_polarity; ++ ++ // Refresh timing. ++ long pixel_clock; ++ long horizontal_frequency; ++ long vertical_frequency; ++} ++mode_table_t; ++ ++ // 1024 x 768 ++ htotal dend hsstrt hsw hpolar vtot vdend vdstrt vsh vpolar pixclk hfreq vfreq ++{ 1344, 1024, 1048, 136, NEGATIVE, 806, 768, 771, 6, NEGATIVE, 65000000, 48363, 60 }, ++{ 1328, 1024, 1048, 136, NEGATIVE, 806, 768, 771, 6, NEGATIVE, 75000000, 56476, 70 }, ++{ 1312, 1024, 1040, 96, POSITIVE, 800, 768, 769, 3, POSITIVE, 78750000, 60023, 75 }, ++{ 1376, 1024, 1072, 96, POSITIVE, 808, 768, 769, 3, POSITIVE, 94500000, 68677, 85 }, ++ ++0FE80200/00010000 + CRT regs ++0FE80204/00180000 + ++0FE80208/08000800 + ++0FE8020C/05D003FF + ++0FE80210/00C80424 + ++0FE80214/032502FF + ++0FE80218/00060302 + ++0FE8021C/00000000 + ++0FE80220/00000000 + ++0FE80224/00400200 + ++0FE80228/00000000 + ++0FE8022C/00000000 + ++0FE80230/00000800 + ++0FE80234/00000000 + ++0FE80238/08000000 + ++0FE8023C/00000400 + ++*/ ++ ++struct lcd_panel_info_t const * const lcd_panels = lcd_panels_ ; ++unsigned const num_lcd_panels = sizeof(lcd_panels_)/sizeof(lcd_panels_[0]); ++ ++struct lcd_panel_info_t const *find_lcd_panel( char const * name ) ++{ ++ unsigned i ; ++ for( i = 0 ; i < num_lcd_panels ; i++ ) ++ { ++ if( 0 == strcmp( lcd_panels_[i].name, name ) ) ++ return lcd_panels_+i ; ++ } ++ return 0 ; ++} ++ ++struct lcd_panel_info_t const *cur_lcd_panel = 0 ; +diff -u -r --new-file u-boot-1.1.2/common/Makefile u-boot-1.1.2-neon/common/Makefile +--- u-boot-1.1.2/common/Makefile 2004-12-16 18:35:57.000000000 +0100 ++++ u-boot-1.1.2-neon/common/Makefile 2007-08-11 21:07:20.000000000 +0200 +@@ -35,16 +35,16 @@ + cmd_eeprom.o cmd_elf.o cmd_ext2.o \ + cmd_fat.o cmd_fdc.o cmd_fdos.o cmd_flash.o cmd_fpga.o \ + cmd_i2c.o cmd_ide.o cmd_immap.o cmd_itest.o cmd_jffs2.o \ +- cmd_load.o cmd_log.o \ ++ cmd_lcdpanel.o cmd_load.o cmd_log.o \ + cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \ +- cmd_nand.o cmd_net.o cmd_nvedit.o \ ++ cmd_nand.o cmd_net.o cmd_not.o cmd_nvedit.o \ + cmd_pci.o cmd_pcmcia.o cmd_portio.o \ + cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o cmd_usb.o cmd_vfd.o \ + command.o console.o devices.o dlmalloc.o docecc.o \ + environment.o env_common.o \ + env_nand.o env_dataflash.o env_flash.o env_eeprom.o env_nvram.o env_nowhere.o exports.o \ +- flash.o fpga.o \ +- hush.o kgdb.o lcd.o lists.o lynxkdi.o \ ++ flash.o fnmatch.o fpga.o \ ++ hush.o kgdb.o lcd.o lcd_panels.o lists.o lynxkdi.o \ + memsize.o miiphybb.o miiphyutil.o \ + s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o \ + usb.o usb_kbd.o usb_storage.o \ +diff -u -r --new-file u-boot-1.1.2/config.mk u-boot-1.1.2-neon/config.mk +--- u-boot-1.1.2/config.mk 2004-10-10 00:21:30.000000000 +0200 ++++ u-boot-1.1.2-neon/config.mk 2007-08-11 21:07:20.000000000 +0200 +@@ -22,6 +22,7 @@ + # + + ######################################################################### ++sinclude select.mk # include DISPLAY_TYPE, HARDWARE_TYPE, SOFTWARE_TYPE, INCLUDE_MINIDEBUG + + # clean the slate ... + PLATFORM_RELFLAGS = +@@ -106,11 +107,15 @@ + OPTFLAGS= -Os #-fomit-frame-pointer + ifndef LDSCRIPT + #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug ++ifeq ($(INCLUDE_MINIDEBUG),y) ++LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-bootmini.lds ++else + LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds + endif ++endif + OBJCFLAGS += --gap-fill=0xff + +-gccincdir := $(shell $(CC) -print-file-name=include) ++gccincdir := "$(shell $(CC) -print-file-name=include)" + + CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \ + -D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE) \ +@@ -170,11 +175,19 @@ + + ######################################################################### + ++ifdef LISTINGS ++%.s: %.S ++ $(CPP) $(AFLAGS) -Wa,-alh=$(basename $<).lst -o $@ $(CURDIR)/$< ++%.o: %.S ++ $(CC) $(AFLAGS) -c -Wa,-alh=$(basename $<).lst -o $@ $(CURDIR)/$< ++%.o: %.c ++ $(CC) $(CFLAGS) -c -Wa,-alh=$(basename $<).lst -o $@ $< ++else + %.s: %.S + $(CPP) $(AFLAGS) -o $@ $(CURDIR)/$< + %.o: %.S + $(CC) $(AFLAGS) -c -o $@ $(CURDIR)/$< + %.o: %.c + $(CC) $(CFLAGS) -c -o $@ $< +- ++endif + ######################################################################### +diff -u -r --new-file u-boot-1.1.2/Configure u-boot-1.1.2-neon/Configure +--- u-boot-1.1.2/Configure 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/Configure 2007-08-11 21:07:19.000000000 +0200 +@@ -0,0 +1,170 @@ ++#!/bin/bash ++#======================================================================= ++DISPLAY_TYPE_CHOICES="DA640X240 DA320X240 DA800X480 DA640X480 DA240X320 DA800X600 DA1024X768 DP320X240 DP480X320 DL122X32" ++PLATFORM_TYPE_CHOICES="NEONB NEON HALOGEN BD2003 GAME_WITH_SMC GAME_CONTROLLER" ++# BOUNDARY_OLD_BOARD #lcd pin reordering for rgb problem, don't use VLIO(gp18 is turnstile) ++# OLD_GAME_CONTROLLER GAME_CONTROLLER_PLAITED_A1 ++REVISION_CHOICES="1 2" ++ ++SOFTWARE_TYPE_CHOICES="WINCE LINUX GAME" ++INCLUDE_MINIDEBUG_CHOICES="y n" ++CPU_CLOCK_CHOICES="100 200 300 400" ++CPU_CLOCK_PXA270_CHOICES="104 208 312 416 520 624" ++ ++CONFIG_H=include/configs/select.h ++CONFIG_MK=select.mk ++CONFIG_LOG=select.log ++ ++fail () ++{ ++ echo "" ++ echo "Configuration failed." ++ echo "" ++ exit 1 ++} ++ ++if [ -f $CONFIG_MK ] ; then ++. ./$CONFIG_LOG ++fi ++ ++ ++ ++#======================================================================= ++ ++ ++arg () { ++ VALUE="`echo X"$2" | sed -e 's/^X--[a-zA-Z_]*=//'`" ++ eval $1=\"$VALUE\" ++ eval $1_P='y' ++} ++ ++usage () { ++ echo "bad parameters" ++ exit 1 ++} ++ ++while [ $# -gt 0 ] ; do ++ case "$1" in ++ --DISPLAY_TYPE=*) arg DISPLAY_TYPE $1 ;; ++ --PLATFORM_TYPE=*) arg PLATFORM_TYPE $1 ;; ++ --SOFTWARE_TYPE=*) arg SOFTWARE_TYPE $1 ;; ++ --INCLUDE_MINIDEBUG=*) arg INCLUDE_MINIDEBUG $1 ;; ++ --CPU_CLOCK=*) arg CPU_CLOCK $1 ;; ++ *) usage ;; ++ esac ++ shift ++done ++ ++#======================================================================= ++ ++write_str () { ++ value=`eval echo '$'$1` ++ echo "$1=$value" >> $CONFIG_MK ++ echo "$1=\"$value\"" >> $CONFIG_LOG ++ if [ x$3 != x ] ; then ++ choices=`eval echo '$'$2` ++ str="" ++ for a in $choices ; do ++ if [ -n "$str" ] ; then str="$str && " ; fi ++ str="$str!defined($3$a)"; ++ done ++ echo "#if $str" >> $CONFIG_H ++ echo "#define $3$value" >> $CONFIG_H ++ echo "#endif" >> $CONFIG_H ++ else ++ echo "#ifndef $1" >> $CONFIG_H ++ echo "#define $1 $value" >> $CONFIG_H ++ echo "#endif" >> $CONFIG_H ++ fi ++} ++ ++prompt () { ++ eval $3=\"$2\" ++ /bin/echo -e "$1 [$2]: \c" ++ read tmp ++ if [ -n "$tmp" ] ; then eval $3=\"$tmp\" ; fi ++ if [ ! -t 1 ] ; then echo $3 ; fi ++} ++noprompt () { ++ eval $3=\"$2\" ++ /bin/echo -e "$1 [$2]: " ++ if [ ! -t 1 ] ; then echo $3 ; fi ++} ++ ++ ++ask_str () { ++ choices=`eval echo '$'$3` ++ default=`eval echo '$'$2` ++ ppp=`eval echo '$'$2_P` ++ ans="" ++ stop="0" ++ if [ x$ppp = x"y" ] ; then ++ noprompt "$1 ($choices)" "$default" answer ++ for a in $choices ; do ++ if [ x$a = x$answer ] ; then ans=$a; stop="1"; break; fi; ++ done ++ if [ $stop != "1" ] ; then default=""; fi; ++ fi ++ while [ $stop != "1" ] ; do ++ prompt "$1 ($choices)" "$default" answer ++ for a in $choices ; do ++ if [ x$a = x$answer ] ; then ans=$a; stop="1"; break; fi; ++ done ++ done ++ eval $2=\"$ans\" ++} ++#======================================================================= ++ ++echo "" ++echo " -------- U-Boot Boundary Devices Specific Configuration Script --------" ++echo "" ++echo "" ++ ++ask_str "Choose display type" DISPLAY_TYPE DISPLAY_TYPE_CHOICES ++ask_str "Choose hardware type" PLATFORM_TYPE PLATFORM_TYPE_CHOICES ++ if [ x$PLATFORM_TYPE = xHALOGEN ] ; then ++ask_str "Choose hardware revision" PLATFORM_REV REVISION_CHOICES ++ fi ++ask_str "Choose software type" SOFTWARE_TYPE SOFTWARE_TYPE_CHOICES ++ask_str "Include minidebug" INCLUDE_MINIDEBUG INCLUDE_MINIDEBUG_CHOICES ++ ++ if [ x$PLATFORM_TYPE = xHALOGEN ] ; then ++ask_str "CPU clock" CPU_CLOCK CPU_CLOCK_PXA270_CHOICES ++ else ++ask_str "CPU clock" CPU_CLOCK CPU_CLOCK_CHOICES ++ fi ++ ++rm -f $CONFIG_H $CONFIG_MK ++ ++cat << 'EOF' > $CONFIG_H ++/* ++ Automatically generated by 'make xxx_config' -- don't edit! ++*/ ++#include ++EOF ++ ++cat << 'EOF' > $CONFIG_MK ++# ++# Automatically generated by 'make xxx_config' -- don't edit! ++# ++EOF ++ ++cat << 'EOF' > $CONFIG_LOG ++#!/bin/bash ++EOF ++ ++chmod 777 $CONFIG_LOG ++ ++write_str DISPLAY_TYPE DISPLAY_TYPE_CHOICES ++write_str PLATFORM_TYPE PLATFORM_TYPE_CHOICES ++ if [ x$PLATFORM_TYPE = xHALOGEN ] ; then ++write_str PLATFORM_REV REVISION_CHOICES ++ fi ++write_str SOFTWARE_TYPE SOFTWARE_TYPE_CHOICES ++write_str INCLUDE_MINIDEBUG INCLUDE_MINIDEBUG_CHOICES ++ if [ x$PLATFORM_TYPE = xHALOGEN ] ; then ++write_str CPU_CLOCK CPU_CLOCK_PXA270_CHOICES ++ else ++write_str CPU_CLOCK CPU_CLOCK_CHOICES ++ fi ++echo "Configuration successful." +diff -u -r --new-file u-boot-1.1.2/cpu/mpc8xx/lcd.c u-boot-1.1.2-neon/cpu/mpc8xx/lcd.c +--- u-boot-1.1.2/cpu/mpc8xx/lcd.c 2004-10-10 01:26:00.000000000 +0200 ++++ u-boot-1.1.2-neon/cpu/mpc8xx/lcd.c 2007-08-11 21:07:20.000000000 +0200 +@@ -255,7 +255,6 @@ + /*----------------------------------------------------------------------*/ + + +-int lcd_line_length; + + int lcd_color_fg; + int lcd_color_bg; +diff -u -r --new-file u-boot-1.1.2/cpu/pxa/config.mk u-boot-1.1.2-neon/cpu/pxa/config.mk +--- u-boot-1.1.2/cpu/pxa/config.mk 2003-05-23 14:36:21.000000000 +0200 ++++ u-boot-1.1.2-neon/cpu/pxa/config.mk 2007-08-11 21:15:47.000000000 +0200 +@@ -21,8 +21,19 @@ + # Foundation, Inc., 59 Temple Place, Suite 330, Boston, + # MA 02111-1307 USA + # +- +-PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ +- -mshort-load-bytes -msoft-float +- +-PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100 +++sinclude ../../select.mk # include DISPLAY_TYPE, HARDWARE_TYPE, SOFTWARE_TYPE, INCLUDE_MINIDEBUG +++ +++PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 +++PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 +++GCC_MAJOR := $(shell $(CC) -v 2>&1 | grep version | cut -d' ' -f3 | cut -d'.' -f1) +++GCC_MINOR := $(shell $(CC) -v 2>&1 | grep version | cut -d' ' -f3 | cut -d'.' -f2) +++ +++ifneq ($(GCC_MAJOR),3) +++ PLATFORM_CPPFLAGS += -mtune=strongarm1100 +++ PLATFORM_RELFLAGS += -msoft-float +++else +++ PLATFORM_CPPFLAGS += -mtune=xscale +++ ifneq ($(GCC_MINOR),4) +++ PLATFORM_RELFLAGS += -msoft-float +++ endif +++endif +diff -u -r --new-file u-boot-1.1.2/cpu/pxa/cpu.c u-boot-1.1.2-neon/cpu/pxa/cpu.c +--- u-boot-1.1.2/cpu/pxa/cpu.c 2004-02-08 20:38:44.000000000 +0100 ++++ u-boot-1.1.2-neon/cpu/pxa/cpu.c 2007-08-11 21:07:20.000000000 +0200 +@@ -33,6 +33,7 @@ + #include + #include + #include ++#include + + int cpu_init (void) + { +@@ -59,8 +60,12 @@ + + unsigned long i; + ++ MMC_STRPCL = MMC_STRPCL_STOP_CLK; ++ + disable_interrupts (); + ++ dcache_disable(); ++ + /* turn off I-cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + i &= ~0x1000; +@@ -129,21 +134,6 @@ + return (i & 0x1000); + } + +-/* we will never enable dcache, because we have to setup MMU first */ +-void dcache_enable (void) +-{ +- return; +-} +- +-void dcache_disable (void) +-{ +- return; +-} +- +-int dcache_status (void) +-{ +- return 0; /* always off */ +-} + + void set_GPIO_mode(int gpio_mode) + { +diff -u -r --new-file u-boot-1.1.2/cpu/pxa/Makefile u-boot-1.1.2-neon/cpu/pxa/Makefile +--- u-boot-1.1.2/cpu/pxa/Makefile 2003-06-16 00:40:43.000000000 +0200 ++++ u-boot-1.1.2-neon/cpu/pxa/Makefile 2007-08-11 21:07:20.000000000 +0200 +@@ -23,10 +23,45 @@ + + include $(TOPDIR)/config.mk + ++CPU_TYPE=xscale ++ ++ifeq ($(SOFTWARE_TYPE),WINCE) ++STACKS_VALID = -DCONFIG_STACKS_VALID ++else ++ ++ifeq ($(SOFTWARE_TYPE),GAME) ++STACKS_VALID = -DCONFIG_STACKS_VALID ++else ++STACKS_VALID = ++endif ++endif ++ARM_ELF_GCC ?= arm-elf-gcc ++ + LIB = lib$(CPU).a + +-START = start.o +-OBJS = serial.o interrupts.o cpu.o i2c.o pxafb.o mmc.o ++ifeq ($(INCLUDE_MINIDEBUG),y) ++START = minidebug.o ministart.o ++else ++START = start.o ministart.o ++endif ++OBJS = serial.o interrupts.o cpu.o i2c.o mmc.o ++ ++ifdef PXALCD ++ OBJS += pxafb.o ++endif ++ ++ifeq ($(PLATFORM_TYPE),HALOGEN) ++ OBJS += usb_ohci.o ++else ++ifeq ($(PLATFORM_TYPE),NEON) ++ OBJS += usb_ohci.o ++else ++ifeq ($(PLATFORM_TYPE),NEONB) ++ OBJS += usb_ohci.o ++else ++endif ++endif ++endif + + all: .depend $(START) $(LIB) + +@@ -35,9 +70,13 @@ + + ######################################################################### + +-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) +- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ ++.depend: Makefile $(START) $(OBJS) ++ $(CC) -M $(CFLAGS) -DUBOOT=1 $(START:.o=.S) $(OBJS:.o=.c) > $@ + + sinclude .depend + ++minidebug.o : minidebug.S Makefile ++ $(ARM_ELF_GCC) -c $(D_GNUC) -DUBOOT=1 -DDISPLAY_TYPE=$(DISPLAY_TYPE) -DPLATFORM_TYPE=$(PLATFORM_TYPE) -DPLATFORM_REV=$(PLATFORM_REV) -DSOFTWARE_TYPE=$(SOFTWARE_TYPE) $(STACKS_VALID) -DCPU_CLOCK=$(CPU_CLOCK) \ ++ $(SOFT_FLOAT) -I$(TOPDIR)/include -mtune=$(CPU_TYPE) -mcpu=$(CPU_TYPE) -o $@ $< ++ + ######################################################################### +diff -u -r --new-file u-boot-1.1.2/cpu/pxa/minidebug.S u-boot-1.1.2-neon/cpu/pxa/minidebug.S +--- u-boot-1.1.2/cpu/pxa/minidebug.S 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/cpu/pxa/minidebug.S 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,3850 @@ ++ .nolist ++ .ifdef __ARMASM ++UBOOT EQU 0 ++CONFIG_UNSCRAMBLE_LCD EQU 0 ++LCD_REORDER_BLUE EQU 1 ++ .endif ++ ++#ifdef UBOOT ++#include ++#include ++#include ++#include ++#include ++#include ++#else ++#include "platformTypes.h" ++#include "pxaGpio.h" ++#include "pxaMacro3.h" ++#include "miniMac.inc" ++#include "burn.inc" ++ .ifdef __ARMASM ++ STARTUPTEXT ++ EXTERN HeadStart ++ .endif ++#endif ++ ++ .list ++ .global StartUp ++ ++ ++#define L1(a) ((CH_##a)) ++#define L2(a,b) ((CH_##a)+(CH_##b<<8)) ++#define L3(a,b,c) ((CH_##a)+(CH_##b<<8)+(CH_##c<<16)) ++#define L4(a,b,c,d) ((CH_##a)+(CH_##b<<8)+(CH_##c<<16)+(CH_##d<<24)) ++ ++#define C2(a,b) ((CH_##a<<8)+(CH_##b)) ++#define C3(a,b,c) ((CH_##a<<16)+(CH_##b<<8)+(CH_##c)) ++#define C4(a,b,c,d) ((CH_##a<<24)+(CH_##b<<16)+(CH_##c<<8)+(CH_##d)) ++ ++// ******************************************************************************************* ++// ******************************************************************************************* ++ ++ ++//.global _start ++//_start: ++StartUp: ++ b V_Reset //0 ++ b V_UndefinedInstr //4 ++ b V_SWI //8 ++ b V_PrefetchAbort //0x0c ++ b V_DataAbort //0x10 ++ b V_Unused //0x14, not used ++ b V_IRQ //0x18 ++// b V_FIQ //0x1c ++ ++//In Linux, all modes switch almost immediately to the SVC mode ++//and it is the only one with a valid stack ++//FIQ & SWI stacks are always assumed valid ++V_FIQ: ++ V_VectorEntrance V_rWork,V_rBranch,SIG_FIQ ++ ++join_fiq: ++ CheckBranch V_rWork,V_rBranch ++ V_VectorExitCC V_rWork,V_rBranch,eq,eqia ++ CheckLdr V_rWork,V_rBranch ++ V_VectorExitCC1 V_rWork,V_rBranch,cc,ccia ++join_fiq2: ++ sub sp,sp,#(DEBUG_SPACE-DBG_R0) //the extra 12 bytes already on stack are needed for indirect return for SDS bug ++ stmia sp,{r0,r1} ++ sub r1,V_rBranch,#8 //restore to SIG_xxx value ++ add r0,sp,#(DEBUG_SPACE-DBG_R0) ++ ldr V_rWork,[r0],#4 ++ ldr V_rBranch,[r0],#8 ++ str r0,[sp,#DBG_HSP-DBG_R0] ++ sub r0,sp,#DBG_R0 ++join_fiq3: ++ mov r1,r1,LSR #2 ++ and r1,r1,#0xf ++ b SaveRest2 ++V_Reset: ++//this is either a normal processor reset, or a debug exception in halt mode ++ mrs sp,cpsr ++ and sp,sp,#0x1f ++ cmp sp,#0x15 ++ bne 2f ++//this is a debug exception in halt mode ++ CP14_DCSR mrc,sp ++ and sp,sp,#0x1c ++ cmp sp,#0 //reset ++ cmpne sp,#5<<2 //vector trap (reset vector) ++ bne 10f //initialization already done ++ ++ BigMov sp,PWR_MANAGER_BASE ++ ldr sp,[sp,#RCSR] ++ tst sp,#2 ++ tsteq pc,#0xff000000 ++ bne 2f //br if watchdog reset or if not nCS0 address ++ ++//signal debugger that he can download into main instruction cache now ++ CP14_TX mcr,sp ++1: ++ CP14_TXRXCTRL mrc,r15 //r15 means update condition codes ++ bpl 1b ++ CP14_RX mrc,sp //just read and discard ++2: ++ CP14_DCSR mrc,sp ++ orr sp,sp,#1<<31 //set global debug enable bit ++ CP14_DCSR mcr,sp ++ ++// InitGPIO r0,sp ++// InitIC_Clocks r0,sp ++// InitUART r0,sp,UART_BASE,BAUDRATE ++// TransMacro L1(U) ++ b MainInitializationCode //this can be in the main instruction cache not locked ++ //because it is only executed upon reset ++ ++10: ++ cmp sp,#1<<2 //Instruction breakpoint ++ mov sp,r0 //save r0 ++ BigMov r0,DEBUG_BASE ++ str sp,[r0,#DBG_R0] ++ str r1,[r0,#DBG_R1] ++ str r2,[r0,#DBG_R2] ++SSDebug: ++ bne 11f ++//this is a breakpoint ++ ldr r1,[r0,#DBG_TRACE] ++ tst r1,#1 ++ beq 11f ++ cmn r1,#1 ++ moveq r1,#0 ++ CP15_IBCR1 mrc,sp ++ sub r2,lr,#3 ++ cmp sp,r2 ++ CP15_IBCR1 mcreq,r1 //remove breakpoint if single-stepping ++ beq 11f ++ CP15_IBCR0 mrc,sp ++ cmp sp,r2 ++ CP15_IBCR0 mcreq,r1 ++11: ++ mrs r2,spsr ++ sub lr,lr,#4 ++ ++ str r3,[r0,#DBG_R3] ++ ldrb r3,[r0,#DBG_Mode] ++SaveDebug: ++ CP14_DCSR mrc,sp ++// str sp,[r0,#DBG_Temp] //the mcr CP14_DCSR instruction below will trash sp in SDS (special debug state) ++ and r1,sp,#0x1c ++ orr sp,sp,#0x1c ++ CP14_DCSR mcr,sp ++ mov r1,r1,LSR #2 ++ add r1,r1,#SIG_DBG ++ b SaveR4andUp ++ ++V_UndefinedInstr: ++ VectorEntrance rWork,rBranch,SIG_UNDEFINED_INSTRUCTION ++ JOIN b ++V_IRQ: ++ VectorEntrance rWork,rBranch,SIG_IRQ ++ ++ .if STACKS_VALID ++ JOIN b ++ .else ++join_irq: ++ CheckBranch I_rWork,I_rBranch ++ I_VectorExitCC I_rWork,I_rBranch,eq,eqia ++ ++ CheckLdr I_rWork,I_rBranch ++ I_VectorExitCC1 I_rWork,I_rBranch,cc,ccia ++join_irq2: ++ strd r0,[I_rWork,#DBG_R0-DBG_MAGIC] ++ sub r0,I_rWork,#DBG_MAGIC ++ sub r1,I_rBranch,#8 //restore to SIG_xxx value ++ ldr I_rWork,[r0,#DBG_TEMP] ++ add sp,r0,#DBG_INDIRECT_R0+8 //sp is trashed, if stacks assumed invalid ++ str sp,[r0,#DBG_HSP] ++ b join_fiq3 ++ .endif ++ ++//sp is valid for this!!!!!, what a treat ++V_SWI: ++ V_VectorEntrance V_rWork,V_rBranch,SIG_SWI ++ b join_fiq ++ ++//monitor mode also has instruction breakpoint, bkpt instruction ++V_PrefetchAbort: ++ VectorEntrance rWork,rBranch,SIG_PREFETCH_ABORT ++ CP15_FSR mrc,rWork ++ tst rWork,#1<<9 ++ bne DEBUG_EVENT //br if a debug event, in monitor mode ++ ++//the 1st instruction after exiting special debug state can cause an abort or possibly the wrong instruction to execute. ++//the Immu is not turned on until the 2nd instruction. ++ tst rWork,#1<<10 ++ JOIN beq ++ and rWork,rWork,#0xf ++ cmp rWork,#0x6 ++ JOIN bne //br if not an external abort ++ ++ CP15_CONTROL mrc,rWork //get the control register ++ tst rWork,#1 //test MMU ++ ++ BigMov rWork,DEBUG_BASE+DBG_ABORT_PC ++ swpne rWork,lr,[rWork] //save lr as a flag so not infinite errors, if mmu on ++ cmpne rWork,lr ++ ++ .if STACKS_VALID ++ ldrne rBranch,[sp,#4] ++ ldrne rWork,[sp],#12 ++ subnes pc,lr,#4 //retry access ++ .else ++ BigMov rWork,DEBUG_BASE+DBG_MAGIC ++ ldrne rWork,[rWork,#DBG_TEMP-DBG_MAGIC] ++ subnes pc,lr,#4 //retry access ++ .endif ++ ++ add rBranch,rBranch,#8 ++ JOIN2 b ++ ++//stacks aren't kept valid ++//monitor mode also has data breakpoint, external debug break, trace-buffer full break ++V_DataAbort: ++ VectorEntrance rWork,rBranch,SIG_DATA_ABORT ++ CP15_FSR mrc,rWork ++ tst rWork,#1<<9 ++ JOIN beq ++ sub lr,lr,#4 //+8 of offending instruction for most data aborts instead of +4 ++DEBUG_EVENT: ++ BigMov rWork,DEBUG_BASE+DBG_MAGIC ++ strd r0,[rWork,#DBG_R0-DBG_MAGIC] ++ sub r0,rWork,#DBG_MAGIC ++ ++ .if STACKS_VALID ++ ldr rWork,[sp],#4 ++ ldr rBranch,[sp],#8 ++ .else ++ ldr rWork,[r0,#DBG_TEMP] ++ add sp,r0,#DBG_INDIRECT_R0+8 //sp is trashed, if stacks assumed invalid ++ .endif ++ str sp,[r0,#DBG_HSP] ++ CP14_DCSR mrc,sp ++ and sp,sp,#0x1c ++ cmp sp,#1<<2 //Instruction breakpoint ++ str r2,[r0,#DBG_R2] ++ b SSDebug ++ ++V_Unused: ++ mov sp,r0 //save r0 ++ BigMov r0,DEBUG_BASE ++ str sp,[r0,#DBG_R0] ++ str r1,[r0,#DBG_R1] ++ mov r1,#SIG_UNUSED ++// b SaveRest2 ++ ++//r0 - debug storage ++//r1 - reason for getting here ++SaveRest2: ++ str r2,[r0,#DBG_R2] ++ sub lr,lr,#4 ++ mrs r2,spsr ++ str r3,[r0,#DBG_R3] ++ ldrb r3,[r0,#DBG_Mode] ++//r2 - spsr ++//r3 - DBG_MODE - don't assume that ram is working upon reset ++SaveR4andUp: ++ str r4,[r0,#DBG_R4] ++ str lr,[r0,#DBG_PC] //return PC ++ str r2,[r0,#DBG_CPSR] //return CPSR ++ mrs r4,cpsr ++ str r4,[r0,#DBG_HCPSR] //mode to return to before exception return ++ ++ tst r2,#0xf ++ orreq r2,r2,#0xdf //if user mode, switch to system mode to access user registers, set I, F ++ orrne r2,r2,#0xc0 //set I, F ++ msr cpsr_c,r2 ++ ++ add r2,r0,#DBG_R5 ++ stmia r2,{r5,r6,r7,r8,r9,sl,fp,ip,sp,lr} ++// ********************************** ++// ********************************** ++ ++ mov rDBG,r0 ++ mov r6,r1 //reason ++ mov r5,r3 //DBG_MODE ++ strb r2,[rDBG,#DBG_LastSignal] ++ CP15_CONTROL mrc,r1 //get the control register ++ tst r1,#1 ++ BigMov rUart,UART_BASE //this is right if MMU is off ++ blne GetUartAddress //if MMU is on ++ b gdb_lastSignal1 ++ ++//r1 - CP15_CONTROL(r1) ++GetUartAddress: ++ tst r1,#1<<13 //assume 1:1 mapping for TTBR if relocation vector is off ++// see if identity mapping is enabled ++ CP15_TTBR mrc,r1 ++// using Big will generate no instructions if Wince, throwing off my reloc vector ++// BigAdd2Ne r1,(SDRAM_BASE_C_VIRTUAL-0xA0000000) ++ addne r1,r1,#(SDRAM_BASE_C_VIRTUAL-0xA0000000) //convert this physical address to a virtual address if relocation vector ON ++ ++ ldr r2,[r1,rUart,lsr #18] ++ sub r2,r2,rUart ++ cmp r2,#1<<20 ++ movcc pc,lr //identity mapping on ++ ++ mov r3,rUart ++ BigMov rUart,UART_VIRT_BASE ++1: ldr r2,[r1,rUart,lsr #18] ++ tst r2,#3 ++ beq 2f ++ sub r2,r2,r3 ++ cmp r2,#1<<20 ++ movcc pc,lr //br if found virtual address ++ adds rUart,rUart,#1<<20 ++ moveq rUart,#0xE0000000 ++ b 1b ++2: ++ BigOrr2 r3,0xc02 ++ str r3,[r1,rUart,lsr #18] //steal this unused entry ++// b cache_clean_invalidate_all ++ ++cache_clean_invalidate_all: ++//flush data cache, if data cache is enabled ++ CP15_CONTROL mrc,r0 //get the control register ++ tst r0,#4 ++ moveq pc,lr //return if disabled ++ ++// Set baseaddress as the 1st virtual address of a 32k range used only ++// to flush the data cache. baseaddress should be aligned on a 32 byte(cache-line) boundary. ++// If the virtual range beginning with baseaddress is used for any purpos other than flushing ++// the data cache, then cachelinecount must be doubled from 1024 to 2048 ++ mov r1,#cachelinecount ++ ldr r0,[rDBG,#DBG_PC] //I hope my return address is mapped ++ BigBic2 r0,0xffff ++1: ++ CP15_CF_ALLOC_LINE mcr,r0 //allocate a cache line for r0 ++ add r0,r0,#cachelinesize ++ subs r1,r1,#1 ++ bne 1b ++ ++// teq r2, #0 // if running only from cache, an invalidate could be fatal if not done from minicache ++ // and then, a return to caller would not be allowed, so invalidate is postponed ++// CP15_CF_INVAL_I mcrne,r0 ++ CP15_CF_DRAIN mcr,r0 ++ CP15_CF_INVAL_D mcr,r0 ++// The instruction cache is guaranteed to be invalidated at this point. The ++// next instruction sees the result of the invalidate command. ++ mov pc,lr ++ ++ ++//r0 - value to printm r9 - chksum ++PrintHexEndian: ++#if LITTLE_ENDIAN ++ mov r2,#8 ++1: mov r4,r0 ++ mov r3,lr ++2: tst r2,#1 ++ moveq r0,r4,LSR #4 ++ andne r0,r4,#0xf ++ andeq r0,r0,#0xf ++ movne r4,r4,ROR #8 ++ cmp r0,#0xA ++ addcs r0,r0,#L1(a)-0x0a ++ addcc r0,r0,#L1(0) ++ add r9,r9,r0 ++ bl Transmit ++ subs r2,r2,#1 ++ bne 2b ++ mov pc,r3 ++ ++PrintHexByteEndian: ++ mov r2,#2 ++ b 1b ++#else ++ mov r2,#8 ++ mov r4,r0 ++1: mov r3,lr ++2: mov r4,r4,ROR #28 ++ and r0,r4,#0xf ++ cmp r0,#0xA ++ addcs r0,r0,#L1(a)-0x0a ++ addcc r0,r0,#L1(0) ++ add r9,r9,r0 ++ bl Transmit ++ subs r2,r2,#1 ++ bne 2b ++ mov pc,r3 ++PrintHexByteEndian: ++ mov r4,r0,LSL #24 ++ mov r2,#2 ++ b 1b ++#endif ++ ++PrintHexByte: ++ mov r4,r0,LSL #24 ++ mov r2,#2 ++ b PrintHex1 ++ ++TransmitCRLF: ++ BigMov r0,L2(CR,LF) ++ b Transmit ++ ++ ++ .if STACKS_VALID ++ .else ++// ******************************************************* ++ RelocationVector 0 ++// ******************************************************* ++ .endif ++ ++ ++//IN: r0 - value to print ++//OUT: r0-r4 trashed ++PrintHex: ++ mov r2,#8 ++ mov r4,r0 ++PrintHex1: ++ mov r3,lr ++1: mov r4,r4,ROR #28 ++ and r0,r4,#0xf ++ cmp r0,#0xA ++ addcs r0,r0,#L1(A)-0x0a ++ addcc r0,r0,#L1(0) ++ bl Transmit ++ subs r2,r2,#1 ++ bne 1b ++ mov pc,r3 ++ ++ ++TransmitSPACE: ++ mov r0,#L1(SPACE) ++// b Transmit ++ ++//IN: r0 - character to transmit ++//OUT: r0 - last character transmitted, r1 - trashed ++Transmit1: ++Transmit: ++1: ldr r1,[rUart,#UART_LSR] ++ ands r1,r1,#0x20 ++ beq 1b ++ mov r1,r0 ++ and r1,r1,#0xff ++ str r1,[rUart,#UART_THR] ++ movs r1,r0,LSR #8 ++ movne r0,r1 ++ bne 1b ++ mov pc,lr //return ++ ++TransmitChkSum: ++ add r9,r9,r0 ++ b Transmit ++ ++ .if STACKS_VALID ++// ******************************************************* ++ RelocationVector 2 ++// ******************************************************* ++ .endif ++ ++//OUT: ++//z-0 good data in r0 ++//z-1 timeout, r0 is 0 ++//r1 - loop cnt time remaining ++Receive: ++ mov r1,#RECEIVE_LOOP_COUNT ++Receive1: ++1: ldr r0,[rUart,#UART_LSR] ++ ands r0,r0,#0x1 ++ ldrne r0,[rUart,#UART_RBR] ++ movne pc,lr //return ++ ++ subs r1,r1,#1 ++ bne 1b ++ mov pc,lr //return ++ ++ ++ ++ ++//IN: r2 - symbol # ++//OUT: r1:r0 - value, ++GetRegVal: ++ cmp r2,#SYM_FP0 ++ bcs GetSpecialReg ++#if DBG_R0 ++ add r1,rDBG,#DBG_R0 ++ ldr r0,[r1,r2,LSL #2] ++#else ++ ldr r0,[rDBG,r2,LSL #2] ++#endif ++ mov r1,#0 ++ mov pc,lr ++ ++// ******************************************************************** ++// ******************************************************************** ++// ******************************************************************** ++ ++ ++gdb_lastSignal: ++ ldrb r6,[rDBG,#DBG_LastSignal] ++ ldrb r5,[rDBG,#DBG_Mode] ++gdb_lastSignal1: ++ ldr r0,[rUart,#UART_LCR] ++ strb r0,[rDBG,#DBG_FFUART_LCR] ++ bic r0,r0,#0x80 //make sure DLAB is clear ++ str r0,[rUart,#UART_LCR] ++ ++ ++1: mov r9,#0 //chksum ++ mov r0,#L1(DOLLAR) ++ bl Transmit ++// mov r0,#L1(T) ++ mov r0,#L1(S) ++ bl TransmitChkSum ++ mov r0,r6 ++ bl PrintHexByteEndian ++// mov r0,#L1(F) ++// bl TransmitChkSum ++// mov r0,#L1(COLON) ++// bl TransmitChkSum ++// mov r2,#SYM_PC ++// bl GetRegVal ++// bl PrintHexEndian ++ ++ mov r0,#L1(POUND) ++ bl Transmit ++ and r0,r9,#0xff ++ bl PrintHexByteEndian ++ mov r3,#0 ++ mov r1,#RECEIVE_LOOP_COUNT ++10: ++ bl Receive1 //z-0 good data in r0, z-1 timeout, r0 is 0 ++ moveq rNum1,#0 ++ beq 12f //br if timeout ++ cmpne r6,#SIG_RESET //disable cr abort on power up ++// beq 10b //uncomment to stop from stopping ++ ++ cmp r0,#L1(PLUS) ++ beq WaitForDollarSign ++ cmp r0,#L1(DOLLAR) ++ beq ReadGDB ++ ++ cmp r0,#L1(MINUS) ++ beq 1b ++ tst r5,#1 ++ cmpeq r0,#GDB_EXIT_CHAR ++ bne 10b //br if in GDB mode or NOT ++ mov rNum1,#1 ++ ++//r6 -SIG_xxx ++12: ++ bl TransmitCRLF ++ cmp r6,#SIG_DBG ++ BigMov r0,L4(D,B,G,MINUS) ++ blcs Transmit1 ++ ++ mov r2,#0 ++ mov r3,#0 ++ mov r4,#0 ++ cmp r6,#SIG_RESET ++ cmpne r6,#SIG_DBG_RESET ++ BigMovEq r0,L4(R,e,s,e) ++ BigMovEq r2,L1(t) ++ cmp r6,#SIG_UNDEFINED_INSTRUCTION ++ BigMovEq r0,L4(U,n,d,e) ++ BigMovEq r2,L1(f) ++// BigMovEq r3,L1(d) ++ cmp r6,#SIG_SWI ++ BigMovEq r0,L3(S,w,i) ++ cmp r6,#SIG_PREFETCH_ABORT ++ BigMovEq r0,L4(P,r,e,f) ++ BigMovEq r2,L4(e,t,c,h) ++ cmp r6,#SIG_DATA_ABORT ++ BigMovEq r0,L4(D,a,t,a) ++ cmpne r6,#SIG_PREFETCH_ABORT ++ BigMovEq r3,L4(SPACE,A,b,o) ++ BigMovEq r4,L2(r,t) ++ cmp r6,#SIG_UNUSED ++ BigMovEq r0,L4(U,n,u,s) ++ BigMovEq r2,L2(e,d) ++ cmp r6,#SIG_IRQ ++ BigMovEq r0,L3(I,r,q) ++ cmp r6,#SIG_FIQ ++ BigMovEq r0,L3(F,i,q) ++ cmp r6,#SIG_DBG_INSTRUCTION_BKPT ++ BigMovEq r0,L4(I,n,s,t) ++ BigMovEq r2,L4(SPACE,B,r,k) ++ cmp r6,#SIG_DBG_DATA_BKPT ++ BigMovEq r0,L4(D,a,t,a) ++ BigMovEq r2,L4(SPACE,B,r,k) ++ cmp r6,#SIG_DBG_BKPT_SOFTWARE ++ BigMovEq r0,L4(B,k,p,t) ++ cmp r6,#SIG_DBG_EXTERNAL ++ BigMovEq r0,L4(E,x,t,e) ++ BigMovEq r2,L4(r,n,a,l) ++ cmp r6,#SIG_DBG_VECTOR_TRAP ++ BigMovEq r0,L4(V,e,c,t) ++ BigMovEq r2,L4(o,r,SPACE,T) ++ BigMovEq r3,L3(r,a,p) ++ cmp r6,#SIG_DBG_TRACE_BUFFER_FULL ++ BigMovEq r0,L4(T,r,a,c) ++ BigMovEq r2,L4(e,SPACE,F,u) ++ BigMovEq r3,L2(l,l) ++ cmp r6,#SIG_DBG_RESERVED ++ BigMovEq r0,L4(R,e,s,e) ++ BigMovEq r2,L4(r,v,e,d) ++ ++ bl Transmit1 ++ movs r0,r2 ++ blne Transmit1 ++ movs r0,r3 ++ blne Transmit1 ++ movs r0,r4 ++ blne Transmit1 ++ ++ bl TransmitSPACE ++ mov r2,#SYM_PC ++ bl GetRegVal ++ bl PrintHex ++// bl TransmitSPACE ++ bl TransmitCRLF ++ ++ rsbs r0,pc,#0x800 ++ BigMov r0,FLASH_READ_CMD ++ ++#if (PLATFORM_TYPE==NEONB) ++ BigMov r1,VIRTUAL_CS1 //remember, although instruction fetches are physical, data are still virtual ++#else ++ BigMov r1,VIRTUAL_CS0 //remember, although instruction fetches are physical, data are still virtual ++#endif ++ cmphs rUart,#0x41000000 ++ strhs r0,[r1] //if (pc is in minicache) & (rUart is in virtual memory) then ++ //make sure flash is in read mode, we are almost off the minicache ++ ++#if (PLATFORM_TYPE==NEONB) ++ adr lr,AfterPCPrint ++ add r1,r1,lr //virtual address of AfterPCPrint if in Linux for data fetch ++ cmp lr,#0x800 ++ BigOrr2Eq lr,FLASH_BASE_ADDRESS //if in low part of CS0 flash, try CS1 flash ++ BigMov r0,0xe3a00055 //instruction mov r0,#55 ++ cmp rUart,#0x41000000 ++ movlo r1,lr //use physical address of AfterPCPrint for data fetch ++ ldr r2,[r1] ++ cmp r2,r0 ++ moveq pc,lr //br if CS1 valid ++ b AfterPCPrint_error ++#else ++ b AfterPCPrint1 ++#endif ++ ++// ****************************************************************************************** ++//A MAIN goal is for all the code above this point to fit into the 2k mini instruction cache ++//So that if difficult errors occur and the flash isn't functioning properly, we can ++//at least get the PC printed out before a crash. ++// ****************************************************************************************** ++ ++ ++//IN: r2 - symbol #, z-1 if SYM_FP0 ++//OUT: r1:r0 - value, ++GetSpecialReg: ++ bne 2f ++//MRA{} ,,acc0 ++ mra r0,r1,acc0 ++ mov pc,lr ++ ++ .if STACKS_VALID ++ .else ++//Must keep this aligned at 0x800 if Bal ++ mac_AfterPCPrint 1 ++ .endif ++ ++2: cmp r2,#SYM_FSR ++ CP15_FSR mrceq,r0 ++ cmp r2,#SYM_FAR ++ CP15_FAR mrceq,r0 ++ cmp r2,#SYM_DCSR ++ CP14_DCSR mrceq,r0 ++ cmp r2,#SYM_TTBR ++ CP15_TTBR mrceq,r0 ++ cmp r2,#SYM_CTRL ++ CP15_CONTROL mrceq,r0 ++ mov r1,#0 ++ mov pc,lr ++ ++//out: c-1 means hex char, r0 - character read, r1 - 0:15 if r0 is a hex character ++ReadHex: ++1: ldr r0,[rUart,#UART_LSR] ++ ands r0,r0,#0x1 ++ ldrne r0,[rUart,#UART_RBR] ++ beq 1b //br on timeout ++ rsbs r1,r0,#L1(9) //reverse subtract ++ subcss r1,r0,#L1(0) ++ movcs pc,lr ++ ++ rsbs r1,r0,#L1(f) //reverse subtract ++ subcss r1,r0,#L1(a) ++ addcs r1,r1,#10 ++ ++ movcs pc,lr ++ ++ rsbs r1,r0,#L1(F) //reverse subtract ++ subcss r1,r0,#L1(A) ++ addcs r1,r1,#10 ++ mov pc,lr ++ ++ .if STACKS_VALID ++//Must keep this aligned at 0x800 if Bal ++ mac_AfterPCPrint 0 ++ .endif ++ ++ ++//r2:r1:r0 value to print, r9 - chksum ++PrintHexEndian12: ++ .if 1 ++ orr r3,r0,r1 ++ orrs r3,r3,r2 ++ bne 1f ++ mov r3,lr ++ mov r0,#L1(0) ++ bl TransmitChkSum ++ mov r0,#L1(ASTERISK) ++ bl TransmitChkSum ++ mov r0,#29+24-1 ++ mov lr,r3 ++ b TransmitChkSum ++ .endif ++1: ++#if LITTLE_ENDIAN ++ mov r7,lr ++ mov r5,r1 ++ mov r6,r2 ++ bl PrintHexEndian //r0 ++ mov r0,r5 ++ bl PrintHexEndian //r1 ++ mov r0,r6 ++ mov lr,r7 ++ b PrintHexEndian //r2 ++ ++#else ++ mov r7,lr ++ mov r5,r0 ++ mov r6,r1 ++ mov r0,r2 ++ bl PrintHexEndian //r2 ++ mov r0,r6 ++ bl PrintHexEndian //r1 ++ mov r0,r5 ++ mov lr,r7 ++ b PrintHexEndian //r0 ++#endif ++ ++ ++MainInitializationCode: ++ cmp pc,#MEM_START ++ biclo sp,pc,#FLASH_BASE_ADDRESS ++ rsblos sp,sp,#0x4000 ++ movlo r1,#0 ++ blo InitializeCont2 //br if not ram and not from reset vector ++ ++//pc - 0-0x4000, 0x04000000-0x04004000, 0xa000000-0xffffffff ++ InitCS0_CS1 r0,sp ++ InitGPIO r0,sp ++ ++#if (PLATFORM_TYPE==NEONB) ++ adr lr,AfterPCPrint ++ cmp lr,#0x800 ++ bne InitializeCont1 ++ BigOrr2 lr,FLASH_BASE_ADDRESS //if in low part of CS0 flash, try CS1 flash ++ BigMov r0,0xe3a00055 //instruction mov r0,#55 ++ ldr r2,[lr] ++ cmp r2,r0 ++ addeq pc,lr,#InitializeCont-AfterPCPrint //br if CS1 valid ++#endif ++ b InitializeCont1 ++ ++//OUT: r0,r2 value, r7 trashed ++ReadHexEndian: ++ mov r3,lr ++ ReadHexE r2,r7 ++ mov r0,r2 ++ mov pc,r3 ++ ++ ++//OUT: r2:r1:r0 value ++ReadHexEndian12: ++ mov r3,lr ++ ++#if LITTLE_ENDIAN ++ ReadHexE r4,r7 ++ ReadHexE r5,r7 ++ ReadHexE r2,r7 ++ mov r0,r4 ++ mov r1,r5 ++#else ++ ReadHexE r2,r7 ++ ReadHexE r5,r7 ++ ReadHexE r4,r7 ++ mov r0,r4 ++ mov r1,r5 ++#endif ++ mov pc,r3 ++ ++ ++ ++ReadGDB: ++ mov r8,#0 ++ mov r9,#0 ++ mov rGdbNum3,#0 ++ mov rGdbChkSum,#0 ++1: bl Receive ++ beq 1b //br on timeout ++ cmp r0,#L1(G) ++ beq gdb_G ++// cmp r0,#L1(q) ++// beq gdb_q ++ mov rGdbCmd,r0 //r5 - command being requested ++ add rGdbChkSum,rGdbChkSum,r0 //update checksum ++ bl GetNumber ++ mov r6,r2 ++ mov r7,r0 ++ cmp r0,#L1(POUND) ++ beq 2f ++ cmp rGdbCmd,#L1(P) ++ beq gdb_P ++// cmp r0,#L1(COMMA) ++// cmpne r0,#L1(SEMICOLON) ++// cmpne r0,#L1(COLON) ++// cmpne r0,#L1(EQUAL) ++ bl GetNumber ++ mov r8,r2 ++ mov r9,r0 ++ cmp r0,#L1(POUND) ++ beq 2f ++ cmp rGdbCmd,#L1(M) ++ beq gdb_M ++ cmp rGdbCmd,#L1(X) ++ beq gdb_X ++ ++ bl GetNumber ++ mov rGdbNum3,r2 ++ cmp r0,#L1(POUND) ++ bne WaitForPound ++ ++//# found, check chksum ++2: bl ReadChksum ++ and rGdbChkSum,rGdbChkSum,#0xff ++ cmp rGdbChkSum,r2 ++ bne CheckSumError ++ mov r0,#L1(PLUS) ++ bl Transmit ++ ++ cmp rGdbCmd,#L1(g) ++ beq gdb_g ++ cmp rGdbCmd,#L1(p) ++ beq gdb_p ++ cmp rGdbCmd,#L1(m) ++ beq gdb_m ++ cmp rGdbCmd,#L1(c) ++ beq gdb_c ++ cmp rGdbCmd,#L1(C) ++ beq gdb_C ++ cmp rGdbCmd,#L1(s) ++ beq gdb_s ++ cmp rGdbCmd,#L1(S) ++ beq gdb_S ++ cmp rGdbCmd,#L1(z) ++ beq gdb_z ++ cmp rGdbCmd,#L1(Z) ++ beq gdb_Z ++ cmp rGdbCmd,#L1(t) ++ beq gdb_t ++ cmp rGdbCmd,#L1(QUESTION_MARK) ++ beq gdb_lastSignal ++ cmp rGdbCmd,#L1(D) ++ beq gdb_D ++//this is an unimplemented command ++UnImplemented: ++ BigMov r0,L4(DOLLAR,POUND,0,0) ++ bl Transmit1 ++ b WaitForDollarSign ++ ++ ++SendError01: ++ mov r9,#0 //chksum ++ mov r0,#L1(DOLLAR) ++ bl Transmit ++ mov r0,#L1(E) ++ bl TransmitChkSum ++ mov r0,#L1(0) ++ bl TransmitChkSum ++ mov r0,#L1(1) ++ bl TransmitChkSum ++ sub r5,pc,#.+8-SendError01 ++ b FinishPacket ++ ++ ++SendOK: ++ mov r9,#0 //chksum ++ mov r0,#L1(DOLLAR) ++ bl Transmit ++ mov r0,#L1(O) ++ bl TransmitChkSum ++ mov r0,#L1(K) ++ bl TransmitChkSum ++ sub r5,pc,#.+8-SendOK ++ b FinishPacket ++ ++CheckSumError: ++ mov r0,#L1(MINUS) ++ bl Transmit ++WaitForDollarSign: ++11: bl GetNumber //$ will branch to ReadGDB ++ b 11b ++WaitForPound: ++11: bl GetNumber ++ cmp r0,#L1(POUND) ++ bne 11b ++ bl ReadChksum ++ and rGdbChkSum,rGdbChkSum,#0xff ++ cmp rGdbChkSum,r2 ++ bne CheckSumError ++ mov r0,#L1(PLUS) ++ bl Transmit ++ b UnImplemented ++ ++ ++ ++FinishPacket: ++ mov r0,#L1(POUND) ++ bl Transmit ++ and r0,r9,#0xff ++ bl PrintHexByte ++10: mov r2,#5 ++11: bl ReadHex ++ cmp r0,#L1(DOLLAR) ++ beq ReadGDB ++ cmp r0,#L1(PLUS) ++ beq WaitForDollarSign ++ cmp r0,#L1(MINUS) ++ ++ ++ moveq pc,r5 //retransmit packet ++ cmp r0,#GDB_EXIT_CHAR ++ bne 10b ++ subs r2,r2,#1 ++ beq Prompt ++ b 11b ++ ++ .if 0 ++gdb_q: ++ mov r2,#0 ++ mov r3,#0 ++1: bl ReadHex ++ cmp r0,#L1(DOLLAR) ++ beq ReadGDB ++ cmp r0,#GDB_EXIT_CHAR ++ beq Prompt ++ cmp r0,#L1(POUND) ++ beq 2f ++ add rGdbChkSum,rGdbChkSum,r0 //update checksum ++ mov r1,r2,LSR #24 ++ orr r3,r1,r3,LSL #8 ++ orr r2,r0,r2,LSL #8 ++ b 1b ++2: ++ bl ReadChksum ++ and rGdbChkSum,rGdbChkSum,#0xff ++ cmp rGdbChkSum,r2 ++ bne CheckSumError ++ mov r0,#L1(PLUS) ++ bl Transmit ++ b UnImplemented ++ .endif ++ ++ ++//Detach command - gdb is exiting ++gdb_D: ++//clear break/watch points ++ b Prompt ++ ++//r6 - addr, r8 - PP, rGdbNum3 - mm ++gdb_t: ++ b UnImplemented ++ ++ ++//read general registers ++gdb_g: ++ mov r9,#0 //chksum ++ mov r0,#L1(DOLLAR) ++ bl Transmit ++ mov r8,#0 ++1: mov r2,r8 ++ bl GetRegVal ++ bl PrintHexEndian ++ add r8,r8,#1 ++ cmp r8,#SYM_PC+1 ++ bne 1b ++ ++ mov r2,#SYM_FP0 ++ bl GetRegVal ++ mov r8,#0 ++2: mov r2,#0 ++ bl PrintHexEndian12 //fp0-7 ++ mov r0,#0 ++ mov r1,#0 ++ add r8,r8,#1 ++ cmp r8,#8 ++ bne 2b ++ ++ bl PrintHexEndian //fps ++ ++ mov r2,#SYM_CPSR ++ bl GetRegVal ++ bl PrintHexEndian //cpsr ++ ++ sub r5,pc,#.+8-gdb_g ++ b FinishPacket ++ ++ ++//Read general register ++//r6 - reg # ++gdb_p: ++ mov r9,#0 //chksum ++ mov r0,#L1(DOLLAR) ++ bl Transmit ++ mov r2,r6 ++ cmp r6,#SYM_PC+1 ++ bcs 2f ++ ++1: bl GetRegVal ++3: bl PrintHexEndian ++4: sub r5,pc,#.+8-gdb_p ++ b FinishPacket ++2: cmp r6,#25 ++ mov r2,#SYM_CPSR ++ beq 1b ++ cmp r6,#24 //fps ++ mov r0,#0 ++ beq 3b ++ cmp r6,#16 //fp0 ++ mov r0,#0 ++ mov r1,#0 ++ mov r2,#SYM_FP0 ++ mov rGdbNum3,r6 ++ bleq GetRegVal ++ mov r2,#0 ++ bl PrintHexEndian12 //fp0-7 ++ mov r6,rGdbNum3 ++ b 4b ++ ++//read memory ++//r6 - addr, r8 - length ++gdb_m: ++ mov r9,#0 //chksum ++ mov r0,#L1(DOLLAR) ++ bl Transmit ++ mov r5,r6 ++ movs r7,r8 ++ beq 4f ++1: ++ tst r5,#3 ++ bne 3f ++ cmp r7,#4 ++ bcc 3f ++ ldr r0,[r5],#4 ++ bl PrintHexEndian ++ subs r7,r7,#4 ++ bne 1b ++ b 4f ++ ++3: ldrb r0,[r5],#1 ++ bl PrintHexByteEndian ++ subs r7,r7,#1 ++ bne 1b ++4: sub r5,pc,#.+8-gdb_m ++ b FinishPacket ++ ++ ++//continue ++//r6 - address, 0- current PC ++gdb_c: ++ mov r8,r6 ++//r8 - address, 0- current PC ++gdb_C: ++ movs rNum1,r8 ++ movne rValidCnt,#F_NUM1_MASK ++ moveq rValidCnt,#0 ++ tst rNum1,#3 ++ bne SendError01 ++ mov r4,#1 ++ b Go_Cmd1 ++ ++//step ++//r6 - address, 0- current PC ++gdb_s: ++ mov r8,r6 ++//r8 - address, 0- current PC ++gdb_S: ++ movs rNum1,r8 ++ movne rValidCnt,#F_NUM1_MASK ++ moveq rValidCnt,#0 ++ tst rNum1,#3 ++ bne SendError01 ++ mov r4,#1 ++ b Trace_Cmd1 ++ ++ ++ ++//watchpoints/breakpoints - remove ++//r6 - type, r8 - address ++gdb_z: ++ cmp r6,#0 //software breakpoint ++ cmpne r6,#1 //hardware breakpoint ++ bne UnImplemented ++// mov rNum1,r8 //same reg ++ bl BC_Do ++ b SendOK ++ ++ ++ ++//watchpoints/breakpoints - insert ++gdb_Z: ++ cmp r6,#0 //software breakpoint ++ cmpne r6,#1 //hardware breakpoint ++ bne UnImplemented ++// mov rNum1,r8 //same reg ++ bl BS_Do // z-0 if r0==rNum1, breakpoint was already set ++ cmpne r0,rNum1 ++ beq SendOK ++ b SendError01 ++ ++ ++//gdb routines below have not done checksum yet ++//write general registers ++gdb_G: ++ mov r8,#0 ++1: bl ReadHexEndian ++ mov r2,r8 ++ mov r1,#0 ++ bl StoreRegVal //r2 - symbol #, r1:r0 - value ++ add r8,r8,#1 ++ cmp r8,#SYM_PC+1 ++ bne 1b ++ ++ bl ReadHexEndian12 ++ mov r2,#SYM_FP0 ++ bl StoreRegVal //r2 - symbol #, r1:r0 - value ++ ++ mov r8,#1 ++2: bl ReadHexEndian12 ++ add r8,r8,#1 ++ cmp r8,#8 ++ bne 2b ++ ++ bl ReadHexEndian //fps ++ bl ReadHexEndian //cpsr ++ ++ mov r2,#SYM_CPSR ++ bl StoreRegVal //r2 - symbol #, r1:r0 - value ++FinishWritePacket: ++ bl FinishWriteP ++ b SendOK ++FinishWriteP: ++ mov r4,lr ++ bl ReadHex ++ cmp r0,#L1(POUND) ++ bne CheckSumError ++ bl ReadChksum ++ and rGdbChkSum,rGdbChkSum,#0xff ++ cmp rGdbChkSum,r2 ++ bne CheckSumError ++ mov r0,#L1(PLUS) ++ bl Transmit ++ mov pc,r4 ++ ++ ++ ++ ++//write general register ++//r6 - reg# ++gdb_P: ++ mov r8,r6 ++ cmp r6,#SYM_PC+1 ++ bcs 2f ++1: ++ bl ReadHexEndian ++4: mov r6,r0 ++ mov r7,r1 ++ bl FinishWriteP ++ mov r0,r6 ++ mov r1,r7 ++ mov r2,r8 ++ bl StoreRegVal //r2 - symbol #, r1:r0 - value ++ b SendOK ++ ++3: bl ReadHexEndian ++ b FinishWritePacket ++ ++2: cmp r6,#25 ++ mov r8,#SYM_CPSR ++ beq 1b ++ cmp r6,#24 //fps ++ beq 3b ++ bl ReadHexEndian12 ++ cmp r6,#16 //fp0 ++ bne FinishWritePacket ++ mov r8,#SYM_FP0 ++ b 4b ++ ++ ++//write memory ++//r6 - addr, r8 - length ++gdb_M: ++ movs r8,r8 ++ beq FinishWritePacket ++ ++1: tst r6,#3 ++ beq 3f ++2: bl ReadHexByteEndian ++ strb r2,[r6],#1 ++ subs r8,r8,#1 ++ bne 1b ++ b FinishWritePacket ++3: cmp r8,#4 ++ bcc 2b ++ bl ReadHexEndian ++ str r2,[r6],#4 ++ subs r8,r8,#4 ++ bne 3b ++ b FinishWritePacket ++ ++ ++//write memory binary with 0x7d, "$","#", escaped with 0x7d ++//r6 - addr, r8 - length ++gdb_X: ++ movs r8,r8 ++ beq FinishWritePacket ++ ++1: tst r6,#3 ++ beq 3f ++2: bl ReadByteEndian ++ strb r0,[r6],#1 ++ subs r8,r8,#1 ++ bne 1b ++ b FinishWritePacket ++3: cmp r8,#4 ++ bcc 2b ++ bl ReadEndian ++ str r0,[r6],#4 ++ subs r8,r8,#4 ++ bne 3b ++ b FinishWritePacket ++ ++ ++ ++ReadEndian: ++ mov r4,lr ++ mov r5,#4 ++1: bl ReadByteEndian ++ ++#if LITTLE_ENDIAN ++ mov r0,r0,LSL #24 ++ orr r2,r0,r2,LSR #8 ++#else ++ orr r2,r0,r2,LSL #8 ++#endif ++ ++ subs r5,r5,#1 ++ bne 1b ++ mov r0,r2 ++ mov pc,r4 ++ ++ ++ReadByteEndian: ++ mov r3,lr ++ bl ReadHex ++ add rGdbChkSum,rGdbChkSum,r0 //update checksum ++ cmp r0,#0x7d ++ beq 1f ++ cmp r0,#L1(DOLLAR) ++ cmpne r0,#L1(POUND) ++ beq CheckSumError ++ mov pc,r3 ++1: ++ bl ReadHex ++ add rGdbChkSum,rGdbChkSum,r0 //update checksum ++ mov pc,r3 ++ ++ ++ReadHexByteEndian: ++ mov r3,lr ++ bl ReadHex ++ bcc CheckSumError ++ add rGdbChkSum,rGdbChkSum,r0 //update checksum ++ mov r2,r1 ++ bl ReadHex ++ bcc CheckSumError ++ add rGdbChkSum,rGdbChkSum,r0 //update checksum ++ add r2,r1,r2,LSL #4 ++ mov pc,r3 ++ ++//OUT: r2 - checksum ++ReadChksum: ++ mov r3,lr ++ bl ReadHex ++ movcs r2,r1 ++ blcs ReadHex ++ addcs r2,r1,r2,LSL #4 ++ mvncc r2,#0 ++ mov pc,r3 ++ ++//out: r0 exit character, r2 - number, rGdbChkSum - updated ++GetNumber: ++ mov r2,#0 ++ mov r3,lr ++1: bl ReadHex ++ bcc 3f ++ add rGdbChkSum,rGdbChkSum,r0 //update checksum ++2: tst r2,#0xf0000000 ++ movne pc,r3 //return on number overflow ++ add r2,r1,r2,LSL #4 ++ b 1b ++3: cmp r0,#L1(DOLLAR) ++ beq ReadGDB ++ cmp r0,#GDB_EXIT_CHAR ++ beq Prompt ++ cmp r0,#L1(POUND) ++ addne rGdbChkSum,rGdbChkSum,r0 //update checksum ++ mov pc,r3 ++ ++// ***************************************************************** ++#if (PLATFORM_TYPE==NEONB) ++AfterPCPrint_error: ++ bl TransmitCRLF ++ BigMov r0,L4(F,l,a,s) ++ bl Transmit1 ++ BigMov r0,L4(h,SPACE,i,s) ++ bl Transmit1 ++ BigMov r0,L4(SPACE,i,n,v) ++ bl Transmit1 ++ BigMov r0,L4(a,l,i,d) ++ bl Transmit1 ++ bl TransmitCRLF ++#endif ++AfterPCPrint1: ++ mov rPrevNum1,#MEM_START ++ movs rNum1,rNum1 ++ tsteq r6,#7 //make sure it's a SIG_RESET, or SIG_DBG_RESET, and timeout ++ bne 1f ++ BigBic r0,pc,FLASH_BASE_ADDRESS ++ cmp r0,#0x4000 ++ blo Gl_Cmd //auto start program if running in flash ++1: ++ b R_Cmd ++// b Prompt2 ++ ++ ++Invalid: ++ bl TransmitCRLF ++ BigMov r0,L4(i,n,v,a) ++ bl Transmit1 ++ BigMov r0,L3(l,i,d) ++ bl Transmit1 ++ b Prompt ++Prompt1: ++ mov rPrevNum1,#MEM_START ++Prompt: ++1: bl TransmitCRLF ++Prompt2: ++ mov r0,#L1(PERIOD) ++ bl Transmit ++ bl TransmitSPACE ++ mov rFieldStart,#1 ++ bl ReadCommand ++ ++ mov r2,r0 //save exit character ++ cmp r0,#0x0d ++ blne Transmit ++ bl TransmitCRLF ++ ++ cmp rCommand,#0 ++ bne 2f ++ cmp r2,#0x0d ++ beq 1b ++ cmp r2,#L1(PLUS) ++ addeq rPrevNum1,rPrevNum1,#4 ++ beq Examine_Cmd ++ cmp r2,#L1(MINUS) ++ subeq rPrevNum1,rPrevNum1,#4 ++ beq Examine_Cmd ++ b 1b ++ ++2: tst rSymbol,#F_NUM1_MASK ++ mov r0,rNum1 ++ blne GetSymbolNumber ++ bne Invalid ++ mov rNum1,r0 ++ ++ tst rSymbol,#F_NUM2_MASK ++ mov r0,rNum2 ++ blne GetSymbolNumber ++ bne Invalid ++ mov rNum2,r0 ++ ++ cmp rCommand,#L1(E) ++ beq Examine_Cmd ++ cmp rCommand,#L1(D) ++ beq Deposit_Cmd ++ cmp rCommand,#L1(G) ++ beq Go_Cmd ++ cmp rCommand,#L1(R) ++ beq R_Cmd ++ cmp rCommand,#L1(T) ++ beq Trace_Cmd ++ BigMov r0,C2(D,L) ++ cmp rCommand,r0 ++ beq Download_Cmd ++ cmp rCommand,#L1(QUESTION_MARK) ++ beq Help_Cmd ++ ++ mov r0,r0,LSL #8 ++ orr r0,r0,#L1(W) ++ cmp rCommand,r0 ++ beq Download_Wireless_Cmd ++ ++ BigMov r0,C4(S,S,I,D) ++ cmp rCommand,r0 ++ beq SSID_Cmd ++ ++ BigMov r0,C3(M,A,C) ++ cmp rCommand,r0 ++ beq MAC_Cmd ++ ++ BigMov r0,C4(B,U,R,N) ++ cmp rCommand,r0 ++ beq Burn_Cmd ++ ++ BigMov r0,C2(B,B) ++ cmp rCommand,r0 ++ beq Burn2_Cmd ++ ++ BigMov r0,C4(B,A,L,L) //Burn all of flash, erase end. ++ cmp rCommand,r0 ++ beq BurnAll_Cmd ++ ++ cmp rCommand,#L1(V) ++ beq Verify_Cmd ++ ++ BigMov r0,C2(V,V) ++ cmp rCommand,r0 ++ beq Verify2_Cmd ++ ++ BigMov r0,C2(G,L) ++ cmp rCommand,r0 ++ beq Gl_Cmd //go linux!! ++ ++ BigEor2 r0,C2(G,L)^C2(G,G) ++ cmp rCommand,r0 ++ beq GG_Cmd //go without cache invalidate ++ ++ BigMov r0,C2(T,T) ++ cmp rCommand,r0 ++ beq TT_Cmd //Trace without cache invalidate ++ ++ BigMov r0,C2(B,S) ++ cmp rCommand,r0 ++ beq BS_Cmd ++ ++ BigEor2 r0,C2(B,S)^C2(B,E) ++ cmp rCommand,r0 ++ beq BE_Cmd ++ ++ BigEor2 r0,C2(B,E)^C2(B,C) ++ cmp rCommand,r0 ++ beq BC_Cmd ++ ++ BigEor2 r0,C2(B,C)^C2(W,C) ++ cmp rCommand,r0 ++ beq WC_Cmd ++ ++ BigEor2 r0,C2(W,C)^C2(W,W) ++ cmp rCommand,r0 ++ beq WW_Cmd ++ ++ BigEor2 r0,C2(W,W)^C2(W,R) ++ cmp rCommand,r0 ++ beq WR_Cmd ++ ++ mov r0,r0,LSL #8 ++ orr r0,r0,#L1(W) ++ cmp rCommand,r0 ++ beq WRW_Cmd ++ ++ BigMov r0,C3(M,M,U) ++ cmp rCommand,r0 ++ beq MMU_Cmd ++// mov r0,rCommand ++// bl PrintHex ++ b Invalid ++ ++//IN: rFieldStart - starting field (this is a blank counting field) ++//OUT: ++ReadCommand: ++ mov r3,lr ++ mov rSymbol,#0 ++ mov rField,rFieldStart ++ mov rValidCnt,#0 //low nibble: # of blanks before command ++ //next: # of chars in command ++ //next: # of blanks ++ //next: # of hex digits in num1 ++ //next: # of blanks ++ //next: # of hex digits in num2 ++ mov rCommand,#0 //command ++ mov rNum1,#0 //1st number ++ mov rNum2,#0 //2nd number ++ ++1: bl Receive ++ beq 1b //br on timeout ++ cmp r0,#L1(DOLLAR) ++ beq ReadGDB ++ cmp r0,#L1(PLUS) ++ cmpne r0,#L1(MINUS) ++ cmpne r0,#L1(AT_SIGN) ++ cmpeq rValidCnt,#0 ++ cmpne r0,#0x0d ++ moveq pc,r3 //return on -,+, 1st on line or ++ ++ cmp r0,#L1(SPACE) ++ bne 2f ++ bl Transmit ++ tst rValidCnt,#0x80000000 ++ eorne rValidCnt,rValidCnt,#0x80000000 //clear bit 31 to mark as blank field ++ movne rField,rField,LSL #F_INC ++//now we are in a counting blanks field ++ rsb r2,rField,rField,LSL #F_INC //get a field mask ++ and r1,rValidCnt,r2 ++ cmp r1,r2 ++ beq Invalid //br if field is full ++ add rValidCnt,rValidCnt,rField ++ b 1b ++2: ++ cmp r0,#0x08 //Backspace ++ cmpne r0,#0x7f //del or Backspace ++ bne 4f ++ cmp rValidCnt,#0 ++ beq 1b //br if nothing to remove ++ BigMov r0,L3(BACKSPACE,SPACE,BACKSPACE) ++ bl Transmit1 ++ sub rValidCnt,rValidCnt,rField ++ mov r0,#4 ++ tst rSymbol,rField ++ movne r0,#8 ++ cmp rField,#F_COMMAND ++ moveq rCommand,rCommand,LSR #8 ++ cmp rField,#F_NUM1 ++ moveq rNum1,rNum1,LSR r0 ++ cmp rField,#F_NUM2 ++ moveq rNum2,rNum2,LSR r0 ++ ++3: rsb r0,rField,rField,LSL #F_INC //get a field mask ++ tst rValidCnt,r0 ++ bne 1b //br if still more in this field ++ bic rSymbol,rSymbol,rField ++ cmp rField,rFieldStart ++ beq 1b ++//move back to lower field ++ mov rField,rField,LSR #F_INC ++ eors rValidCnt,rValidCnt,#0x80000000 ++ b 3b ++ ++4: bl Transmit ++ tst rValidCnt,#0x80000000 ++ orreq rValidCnt,rValidCnt,#0x80000000 //set bit 31 to mark as data field ++ moveq rField,rField,LSL #F_INC ++ cmp rField,#F_UNDEF ++ beq Invalid ++//now we are in a data field ++ rsbs r1,rField,#F_COMMAND ++ rsbges r1,r0,#L1(9) //reverse subtract ++ subges r1,r0,#L1(0) ++ movge rField,rField,LSL #F_INC+F_INC //advance to number field if in range "0"-"9" ++ ++ rsb r2,rField,rField,LSL #F_INC //get a field mask ++ and r1,rValidCnt,r2 ++ cmp r1,r2 ++ beq Invalid //field is full ++ add rValidCnt,rValidCnt,rField ++ ++ rsbs r1,r0,#L1(z) //reverse subtract ++ subges r1,r0,#L1(a) ++ andge r0,r0,#0xdf //convert to uppercase if was "a"-"z" ++ cmp rField,#F_COMMAND ++ bne 6f ++ tst rCommand,#0xff000000 ++ bne Invalid ++ add rCommand,r0,rCommand,LSL #8 ++ b 1b ++ ++6: tst rSymbol,rField ++ bne 15f ++ rsbs r1,r0,#L1(9) //reverse subtract ++ subges r1,r0,#L1(0) ++ bge 5f ++ rsbs r1,r0,#L1(F) //reverse subtract ++ subges r1,r0,#L1(A) ++ add r1,r1,#10 ++ bge 5f ++ orr rSymbol,rSymbol,rField ++//now if number started with "A"-"F", convert back to ascii ++ ++ cmp rField,#F_NUM1 ++ mov r1,rValidCnt,LSR #F_NUM1_BIT //# of nibbles +1 in rNum ++ movne r1,rValidCnt,LSR #F_NUM2_BIT ++ and r1,r1,#((1< instruction -eq ++ andeq r3,r2,#0xf ++#if DBG_R0 ++ addeq r0,rDBG,#DBG_R0 ++ ldreq r0,[r0,r3,LSL #2] ++#else ++ ldreq r0,[rDBG,r3,LSL #2] ++#endif ++ ++ biceq r0,r0,#1 ++ mov pc,r4 ++ ++ ++51: tst r2,#1<<4 ++ bne 52f ++ add r0,r0,#4 //pc+8 ++ bl RegShiftImmed ++ b 50f ++52: ++ tst r2,#1<<7 ++ movne pc,r4 //return if LDR|STR|MUL|MLA... ++//this is a shift by a register value ++ add r0,r0,#4 //pc+8 ++ bl RegShiftReg ++ b 50f ++ ++//nnnn 001n immediate ++11: ++ movne pc,r4 ++ and r3,r2,#0x01800000 ++ cmp r3, #0x01000000 ++ moveq pc,r4 //return if TST|TEQ|CMP|CMN|MRS|MSR|SMLA..... ++ and r6,r1,#0xff ++ mov r3,r1,LSR #7 ++ BIC r3,r3,#1 ++ mov r1,r6,ROR r3 ++ add r0,r0,#4 //pc+8 ++//r1 has 2nd operand ++50: ++ mov r3,r2,LSR #16 ++ and r3,r3,#0xf ++ cmp r3,#0xf ++ moveq r6,r0 //pc+8 ++#if DBG_R0 ++ addne r6,rDBG,#DBG_R0 ++ ldrne r6,[r6,r3,LSL #2] // - r6 ++#else ++ ldrne r6,[rDBG,r3,LSL #2] // - r6 ++#endif ++ ++//r6 has 1st operand ++ mov r3,r2,LSR #21 ++ and r3,r3,#0xf ++ msr CPSR_f,r7 ++ add pc,pc,r3,LSL #3 ++ nop ++ and r0,r6,r1 //0-AND ++ mov pc,r4 ++ eor r0,r6,r1 //1-EOR ++ mov pc,r4 ++ sub r0,r6,r1 //2-SUB ++ mov pc,r4 ++ rsb r0,r6,r1 //3-RSB ++ mov pc,r4 ++ add r0,r6,r1 //4-ADD ++ mov pc,r4 ++ adc r0,r6,r1 //5-ADC ++ mov pc,r4 ++ sbc r0,r6,r1 //6-SBC ++ mov pc,r4 ++ rsc r0,r6,r1 //7-RSC ++ mov pc,r4 ++ sub r0,r0,#4 //8-TST, cannot get here ++ mov pc,r4 ++ sub r0,r0,#4 //9-TEQ, cannot get here ++ mov pc,r4 ++ sub r0,r0,#4 //A-CMP, cannot get here ++ mov pc,r4 ++ sub r0,r0,#4 //B-CMN, cannot get here ++ mov pc,r4 ++ orr r0,r6,r1 //C-ORR ++ mov pc,r4 ++ mov r0,r1 //D-MOV ++ mov pc,r4 ++ bic r0,r6,r1 //E-BIC ++ mov pc,r4 ++ mvn r0,r1 //F-MVN ++ mov pc,r4 ++ ++//LDR ++12: ++13: ++ tsteq r2,#1<<22 //B bit 22 1 : Byte, 0: Word ++ movne pc,r4 ++ tst r2,#1<<20 //L bit 20 1 : LDR, 0:STR ++ moveq pc,r4 ++ ++ add r0,r0,#4 //pc+8 ++ tst r2,#1<<24 //P bit ++ moveq r1,#0 ++ beq 34f ++ tst r2,#1<<25 ++ beq 34f //branch if immediate12bits value is in r1 ++ bl RegShiftImmed ++34: ++ mov r3,r2,LSR #16 ++ and r3,r3,#0xf ++ cmp r3,#0xf ++ moveq r6,r0 //pc+8 ++#if DBG_R0 ++ addne r6,rDBG,#DBG_R0 ++ ldrne r6,[r6,r3,LSL #2] // - r6 ++#else ++ ldrne r6,[rDBG,r3,LSL #2] // - r6 ++#endif ++ ++ tst r2,#1<<23 //U bit Up/Down, Add/Sub ++ addne r6,r6,r1 ++ subeq r6,r6,r1 ++ ldr r0,[r6] ++ mov pc,r4 ++ ++ ++//LDM ++14: ++ and r3,r2,#(1<<15)+(1<<20) ++ cmp r3, #(1<<15)+(1<<20) ++ movne pc,r4 ++ ++//LDM to PC -eq ++ add r0,r0,#4 //pc+8 ++ mov r3,r2,LSR #16 ++ and r3,r3,#0xf ++ cmp r3,#0xf ++ moveq r1,r0 //pc+8, should never execute ++#if DBG_R0 ++ addne r1,rDBG,#DBG_R0 ++ ldrne r1,[r1,r3,LSL #2] // - r1 ++#else ++ ldrne r1,[rDBG,r3,LSL #2] // - r1 ++#endif ++ ++//r1 is already correct address for downward from base (U==0), included(P==0) ++ tst r2,#1<<23 //U bit ++ beq 4f ++ mov r6,r2,LSL #16 ++3: movs r6,r6,LSL #1 ++ addcs r1,r1,#4 ++ bne 3b ++ eor r2,r2,#1<<24 ++4: tst r2,#1<<24 //P bit ++ subne r1,r1,#4 ++ ldr r0,[r1] ++ mov pc,r4 ++ ++//B{L} instruction ++15: ++ mov r3,r2,LSL #8 ++ add r0,r0,#4 ++ add r0,r0,r3,ASR #6 ++ mov pc,r4 ++ ++//IN: r0 - pc+4, r2 instruction, r1 low 12 bits of instruction ++//OUT: r1 - shifted value, r2 - unchanged, r0 - pc+8 ++RegShiftImmed: ++ mov r1,r1,LSR #7 //Shift_imm - r1 ++ and r3,r2,#0xf ++ cmp r3,#0xf ++ moveq r6,r0 //pc+8 ++#if DBG_R0 ++ addne r6,rDBG,#DBG_R0 ++ ldrne r6,[r6,r3,LSL #2] // - r6 ++#else ++ ldrne r6,[rDBG,r3,LSL #2] // - r6 ++#endif ++ ++ tst r2,#1<<6 ++ bne 32f ++ tst r2,#1<<5 ++ bne 31f ++ mov r1,r6,LSL r1 // shf Shift_imm - r1 ++ mov pc,lr ++ ++31: cmp r1,#0 ++ movne r1,r6,LSR r1 ++ mov pc,lr ++ ++32: tst r2,#1<<5 ++ bne 33f ++ cmp r1,#0 ++ moveq r1,#32 ++ mov r1,r6,ASR r1 ++ mov pc,lr ++ ++33: cmp r1,#0 ++ movne r1,r6,ROR r1 ++ movne pc,lr ++ ++ msr CPSR_f,r7 ++ mov r1,r6, RRX ++ mov pc,lr ++ ++ ++//IN: r2 instruction, r1 low 12 bits of instruction ++//OUT: r1 - shifted value, r2 - unchanged, r0 - pc+8 ++RegShiftReg: ++ mov r3,r1,LSR #8 ++ cmp r3,#0xf ++ moveq r1,r0 //pc+8 ++#if DBG_R0 ++ addne r1,rDBG,#DBG_R0 ++ ldrne r1,[r1,r3,LSL #2] // - r1 ++#else ++ ldrne r1,[rDBG,r3,LSL #2] // - r1 ++#endif ++ ++ and r3,r2,#0xf ++ cmp r3,#0xf ++ moveq r6,r0 //pc+8 ++#if DBG_R0 ++ addne r6,rDBG,#DBG_R0 ++ ldrne r6,[r6,r3,LSL #2] // - r6 ++#else ++ ldrne r6,[rDBG,r3,LSL #2] // - r6 ++#endif ++ tst r2,#1<<6 ++ bne 32f ++ tst r2,#1<<5 ++ moveq r1,r6,LSL r1 // shf - r1 ++ movne r1,r6,LSR r1 ++ mov pc,lr ++ ++32: tst r2,#1<<5 ++ moveq r1,r6,ASR r1 ++ movne r1,r6,ROR r1 ++ mov pc,lr ++ ++ ++ ++//IN: r0 - register name ++//OUT: r0 - location ++GetSymbolNumber: ++ BigMov r1,C2(R,0) ++ sub r2,r0,r1 ++ cmp r2,#10 ++ bcc 1f ++ ++ BigMov r1,C3(R,1,0) ++ sub r2,r0,r1 ++ cmp r2,#6 ++ bcc 2f ++ ++ BigMov r1,C3(F,P,0) ++ cmp r1,r0 ++ moveq r2,#SYM_FP0 ++ beq 1f ++ ++ BigMov r1,C2(S,L) ++ cmp r1,r0 ++ moveq r2,#SYM_SL ++ beq 1f ++ ++ BigMov r1,C2(F,P) ++ cmp r1,r0 ++ moveq r2,#SYM_FP ++ beq 1f ++ ++ BigEor2 r1,C2(F,P)^C2(I,P) ++ cmp r1,r0 ++ moveq r2,#SYM_IP ++ beq 1f ++ ++ BigEor2 r1,C2(I,P)^C2(S,P) ++ cmp r1,r0 ++ moveq r2,#SYM_SP ++ beq 1f ++ ++ BigMov r1,C2(L,R) ++ cmp r1,r0 ++ moveq r2,#SYM_LR ++ beq 1f ++ ++ BigMov r1,C2(P,C) ++ cmp r1,r0 ++ moveq r2,#SYM_PC ++ beq 1f ++ ++ BigMov r1,C4(C,P,S,R) ++ cmp r1,r0 ++ moveq r2,#SYM_CPSR ++ beq 1f ++ ++ BigMov r1,C3(F,S,R) ++ cmp r1,r0 ++ moveq r2,#SYM_FSR ++ beq 1f ++ ++ BigMov r1,C3(F,A,R) ++ cmp r1,r0 ++ moveq r2,#SYM_FAR ++ beq 1f ++ ++ BigMov r1,C4(D,C,S,R) ++ cmp r1,r0 ++ moveq r2,#SYM_DCSR ++ beq 1f ++ ++ BigMov r1,C4(T,T,B,R) ++ cmp r1,r0 ++ moveq r2,#SYM_TTBR ++ beq 1f ++ ++ BigMov r1,C4(C,T,R,L) ++ cmp r1,r0 ++ moveq r2,#SYM_CTRL ++ beq 1f ++ ++// BigMov r1,C3(F,P,S) ++// cmp r1,r0 ++// moveq r2,#SYM_FPS-SYM_F0 ++ movne pc,lr ++ ++ ++//3: add r2,r2,#SYM_F0-SYM_SL ++2: add r2,r2,#SYM_SL ++1: BigMov r0,DEBUG_SYM ++ add r0,r0,r2 ++ subs r2,r2,r2 ++ mov pc,lr ++ ++ ++ ++//IN: r0 - symbol address or number to print ++PrintHexOrSymbol: ++ BigAdd r1,r0,-DEBUG_SYM ++ cmp r1,#SYM_LAST+1 ++ bcs PrintHex ++ mov r0,#0 ++ ++//IN: r1 register #, r0 {31:16}- 2 characters to print after ++PrintRegName: ++ cmp r1,#SYM_SL ++ bcs 1f ++ add r0,r0,r1,LSL #8 ++ add r0,r0,#L2(NULL,0) ++// cmp r1,#10 ++// subge r0,r0,#10<<8 ++// movge r0,r0,LSL #8 ++// addge r0,r0,#L2(NULL,1) ++ add r0,r0,#L1(R) ++20: b Transmit1 ++1: BigOrr2Eq r0,L2(S,L) ++ cmp r1,#SYM_FP ++ BigOrr2Eq r0,L2(F,P) ++ cmp r1,#SYM_IP ++ BigOrr2Eq r0,L2(I,P) ++ cmp r1,#SYM_SP ++ BigOrr2Eq r0,L2(S,P) ++ cmp r1,#SYM_LR ++ BigOrr2Eq r0,L2(L,R) ++ cmp r1,#SYM_PC ++ BigOrr2Eq r0,L2(P,C) ++ ble 20b ++ cmp r1,#SYM_FP0 ++ ++ mov r0,r0,LSL #8 ++ BigOrr2Eq r0,L3(F,P,0) ++ cmp r1,#SYM_FSR ++ BigOrr2Eq r0,L3(F,S,R) ++ cmp r1,#SYM_FAR ++ BigOrr2Eq r0,L3(F,A,R) ++ ++ cmp r1,#SYM_CPSR ++ BigMovEq r0,L4(C,P,S,R) ++ cmp r1,#SYM_DCSR ++ BigMovEq r0,L4(D,C,S,R) ++ cmp r1,#SYM_TTBR ++ BigMovEq r0,L4(T,T,B,R) ++ cmp r1,#SYM_CTRL ++ BigMovEq r0,L4(C,T,R,L) ++ b Transmit1 ++ ++ ++//r2 - symbol # ++PrintRegVal: ++ mov r6,lr ++ bl GetRegVal ++ cmp r2,#SYM_FP0 ++ bne 1f ++ mov r5,r0 ++ mov r0,r1 ++ bl PrintHexByte //40 bits ++ mov r0,r5 ++1: mov lr,r6 ++ b PrintHex ++ ++ ++ ++ ++ ++//r2 - symbol #, r1:r0 - value ++StoreRegVal: ++ cmp r2,#SYM_FP0 ++ bcs 1f ++#if DBG_R0 ++ add r1,rDBG,#DBG_R0 ++ str r0,[r1,r2,LSL #2] ++#else ++ str r0,[rDBG,r2,LSL #2] ++#endif ++ mov pc,lr ++1: ++ bne 2f ++//MAR{} acc0,, ++ mar acc0,r0,r1 ++ mov pc,lr ++2: cmp r2,#SYM_FSR ++ CP15_FSR mcreq,r0 ++ cmp r2,#SYM_FAR ++ CP15_FAR mcreq,r0 ++ cmp r2,#SYM_DCSR ++ CP14_DCSR mcreq,r0 ++ cmp r2,#SYM_TTBR ++ CP15_TTBR mcreq,r0 ++ cmp r2,#SYM_CTRL ++ CP15_CONTROL mcreq,r0 ++ mov pc,lr ++ ++R_Cmd: ++ mov r7,#0 ++1: mov r1,r7 ++ BigMov r0,L4(NULL,NULL,COLON,SPACE) ++ bl PrintRegName ++ bl TransmitSPACE ++ mov r2,r7 ++ bl PrintRegVal ++ bl TransmitSPACE ++ bl TransmitSPACE ++ add r7,r7,#1 ++ tst r7,#3 ++ bleq TransmitCRLF ++ cmp r7,#SYM_LAST_RCMD+1 ++ bne 1b ++ b Prompt ++BS_Cmd: ++ tst rValidCnt,#F_NUM1_MASK ++ beq BE_Cmd ++ tst rSymbol,#F_NUM1_MASK ++ mov r0,rNum1 ++ blne GetSymValue ++ mov rNum1,r0 ++ bl BS_Do ++ beq Prompt ++ b BE_Cmd ++ ++//out: z-1 breakpoint just set ++// z-0 if r0==rNum1, breakpoint was already set ++BS_Do: ++ CP15_IBCR0 mrc,r0 ++ CP15_IBCR1 mrc,r1 ++ orr rNum1,rNum1,#1 ++ cmp r0,rNum1 ++ cmpne r1,rNum1 ++ beq 2f ++ tst r0,#1 ++ CP15_IBCR0 mcreq,rNum1 ++ moveq pc,lr ++ tst r1,#1 ++ CP15_IBCR1 mcreq,rNum1 ++ mov pc,lr ++ ++2: mov r0,rNum1 ++ movs r1,#1 ++ mov pc,lr ++ ++BC_Cmd: ++ tst rValidCnt,#F_NUM1_MASK ++ beq BE_Cmd ++ tst rSymbol,#F_NUM1_MASK ++ mov r0,rNum1 ++ blne GetSymValue ++ mov rNum1,r0 ++ bl BC_Do ++ beq Prompt ++ b BE_Cmd ++ ++//out: z-1 breakpoint just cleared ++BC_Do: ++ CP15_IBCR0 mrc,r0 ++ CP15_IBCR1 mrc,r1 ++ orr rNum1,rNum1,#1 ++ mov r2,#0 ++ cmp r0,rNum1 ++ CP15_IBCR0 mcreq,r2 ++ cmp r1,rNum1 ++ CP15_IBCR1 mcreq,r2 ++ cmpne r0,rNum1 ++ mov pc,lr ++ ++BE_Cmd: ++ BigMov r0,L4(B,K,P,T) ++ bl Transmit1 ++ bl TransmitSPACE ++ BigMov r0,L4(S,t,a,t) ++ bl Transmit1 ++ BigMov r0,L4(u,s,COLON,SPACE) ++ bl Transmit1 ++ CP15_IBCR0 mrc,r0 ++ tst r0,#1 ++ bic r0,r0,#1 ++ blne PrintHex ++ bl TransmitSPACE ++ ++ CP15_IBCR1 mrc,r0 ++ tst r0,#1 ++ bic r0,r0,#1 ++ blne PrintHex ++ b Prompt ++ ++WatchStatus: ++ BigMov r0,L4(W,A,T,C) ++ bl Transmit1 ++ BigMov r0,L2(H,SPACE) ++ bl Transmit1 ++ BigMov r0,L4(S,t,a,t) ++ bl Transmit1 ++ BigMov r0,L4(u,s,COLON,SPACE) ++ bl Transmit1 ++ CP15_DBCON mrc,r5 ++ tst r5,#0x0f ++ beq 10f ++ tst r5,#0x03 ++ bne 1f ++ tst r5,#0x100 ++ bne 10f //br if dbr1 is mask (nothing being watched) ++ b 4f ++1: ++ CP15_DBR0 mrc,r0 ++ bl PrintHex ++ bl 20f ++ tst r5,#0x100 ++ beq 3f ++ BigMov r0,L2(M,COLON) ++ bl Transmit1 ++ CP15_DBR1 mrc,r0 //read mask ++ bl PrintHex ++ b 10f ++3: ++ tst r5,#3<<2 ++ beq 10f ++4: ++ CP15_DBR1 mrc,r0 ++ bl PrintHex ++ mov r5,r5,LSR #2 ++ bl 20f ++10: b Prompt ++ ++ ++20: ++ BigMov r0,L4(SPACE,R,W,SPACE) ++ tst r5,#1 ++ beq 21f ++ tst r5,#2 ++ BigEor2Eq r0,L4(SPACE,R,W,SPACE)^L4(SPACE,SPACE,W,SPACE) //store only ++ BigEor2Ne r0,L4(SPACE,R,W,SPACE)^L4(SPACE,R,SPACE,SPACE) //load only ++21: ++ b Transmit1 ++ ++WC_Cmd: ++ mov r0,#0 ++ CP15_DBCON mcr,r0 ++ b Prompt ++WRW_Cmd: ++ mov r4,#2 ++ b WW_JOIN ++WR_Cmd: ++ mov r4,#3 ++ b WW_JOIN ++WW_Cmd: ++ mov r4,#1 ++WW_JOIN: ++ tst rValidCnt,#F_NUM1_MASK ++ beq WatchStatus ++ tst rSymbol,#F_NUM1_MASK ++ mov r0,rNum1 ++ blne GetSymValue ++ mov rNum1,r0 ++ ++ tst rValidCnt,#F_NUM2_MASK ++ beq 3f ++ tst rSymbol,#F_NUM2_MASK ++ mov r0,rNum2 ++ blne GetSymValue ++ mov rNum2,r0 ++ orr r4,r4,#0x100 //mask ++1: ++ mov r0,#0 ++ CP15_DBCON mcr,r0 ++ CP15_DBR0 mcr,rNum1 ++ CP15_DBR1 mcr,rNum2 ++2: ++ CP15_DBCON mcr,r4 ++ b Prompt ++3: ++ CP15_DBCON mrc,r5 ++ mov rNum2,#0 ++ tst r5,#0x100 ++ bne 1b //br if mask was used previously ++ tst r5,#0x0f ++ beq 1b ++ mov r0,#0 ++ CP15_DBCON mcr,r0 ++ tst r5,#3 ++ orreq r4,r5,r4 ++ bicne r5,r5,#3<<2 ++ orrne r4,r5,r4,LSL #2 ++ CP15_DBR0 mcreq,rNum1 ++ CP15_DBR1 mcrne,rNum1 ++ b 2b ++ ++ ++//IN: rNum2 address ++//OUT: r1:r0 val ++GetSymValue: ++ BigAdd r2,rNum2,-DEBUG_SYM ++ cmp r2,#SYM_LAST+1 ++ bcc GetRegVal ++ mov r0,rNum2 ++ mov r1,#0 ++ mov pc,lr ++//IN: rPrevNum1 address or symbol ++//OUT: r1:r0 val ++GetValue: ++ BigAdd r2,rPrevNum1,-DEBUG_SYM ++ cmp r2,#SYM_LAST+1 ++ bcc GetRegVal ++ ldr r0,[rPrevNum1] ++ mov r1,#0 ++ mov pc,lr ++ ++ ++//IN: rNum1 address ++PrintLocationOrRegVal: ++ BigAdd r2,rNum1,-DEBUG_SYM ++ cmp r2,#SYM_LAST+1 ++ bcc PrintRegVal ++ tst r5,#3 ++ tsteq rNum1,#3 ++ bne 1f ++ ldr r0,[rNum1] ++ b PrintHex ++1: ldrb r0,[rNum1] ++ b PrintHexByte ++ ++//IN: rPrevNum1 address, r1:r0 - value ++StoreLocationOrReg: ++ BigAdd r2,rPrevNum1,-DEBUG_SYM ++ cmp r2,#SYM_LAST+1 ++ bcc StoreRegVal ++ tst r5,#3 ++ tsteq rPrevNum1,#3 ++ bne 1f ++ str r0,[rPrevNum1] ++ mov pc,lr ++1: strb r0,[rPrevNum1] ++ mov pc,lr ++ ++GetChangeAmount: ++ BigAdd r0,rPrevNum1,-DEBUG_SYM ++ cmp r0,#SYM_LAST+1 ++ movcs r0,#4 ++ movcc r0,#1 ++ tst r5,#3 ++// tsteq rPrevNum1,#3 ++ movne r0,#1 ++ mov pc,lr ++ ++Examine_Cmd: ++ tst rValidCnt,#F_NUM1_MASK ++ moveq rNum1,rPrevNum1 ++ movne rPrevNum1,rNum1 ++ mov r5,rNum1 ++ tst rValidCnt,#F_NUM2_MASK ++ bne 12f ++1: mov r0,rNum1 ++ bl PrintHexOrSymbol ++ mov r0,#L1(FSLASH) ++ bl Transmit ++ ++ bl PrintLocationOrRegVal ++ ++ bl TransmitSPACE ++ mov rFieldStart,#1<<(F_INC+F_INC+F_INC+F_INC) //blank before num2 field ++ str r5,[rDBG,#DBG_TEMP] ++ bl ReadCommand ++ ldr r5,[rDBG,#DBG_TEMP] ++ mov r3,r0 //save exit character ++ mov r0,rNum2 ++ mov r1,#0 ++ tst rSymbol,#F_NUM2_MASK ++ beq 20f ++ blne GetSymbolNumber ++ bne Invalid ++ mov rNum2,r0 ++ bl GetSymValue ++ ++20: ++ cmp r3,#L1(PLUS) ++ cmpne r3,#L1(MINUS) ++ cmpne r3,#L1(AT_SIGN) ++ beq 2f ++ tst rValidCnt,#F_NUM2_MASK ++ beq Prompt ++ bl StoreLocationOrReg ++ mov r3,#L1(PLUS) ++ b 3f ++ ++2: mov r0,r3 ++ bl Transmit ++3: bl TransmitCRLF ++ bl GetChangeAmount ++ cmp r3,#L1(AT_SIGN) ++ beq 5f ++ cmp r3,#L1(PLUS) ++ addeq rPrevNum1,rPrevNum1,r0 ++ subne rPrevNum1,rPrevNum1,r0 ++4: mov rNum1,rPrevNum1 ++ b 1b ++ ++5: bl GetValue ++ mov rPrevNum1,r0 ++ mov r5,r0 ++ b 4b ++ ++11: sub r0,rNum1,r5 ++ cmp r0,#0x1000 ++ bhs Prompt //no more than 128 lines per examine command ++ bl TransmitCRLF ++12: mov r0,rNum1 ++ bl PrintHexOrSymbol ++ mov r0,#L1(FSLASH) ++ bl Transmit ++13: ++ bl GetChangeAmount ++ bcc 14f ++ add r0,rNum1,#3 ++ cmp r0,rNum2 ++ bhi 16f ++ tst r5,#3 ++ tsteq rNum1,#3 ++ bne 16f ++14: bl PrintLocationOrRegVal ++ bl GetChangeAmount ++15: add rNum1,rNum1,r0 ++ cmp rNum1,rNum2 ++ bhi Prompt ++ tst rNum1,#0x1f ++ beq 11b ++ bl TransmitSPACE ++ tst rNum1,#0x0f ++ bleq TransmitSPACE ++ b 13b ++16: ++ ldrb r0,[rNum1] ++ bl PrintHexByte ++ mov r0,#1 ++ b 15b ++ ++Deposit_Cmd: ++ tst rValidCnt,#F_NUM1_MASK ++ beq Invalid ++ tst rValidCnt,#F_NUM2_MASK ++ beq Invalid ++ mov r0,rNum2 ++ mov r1,#0 ++ tst rSymbol,#F_NUM2_MASK ++ blne GetSymValue ++ mov rPrevNum1,rNum1 ++ bl StoreLocationOrReg ++ b Prompt ++ ++ ++Download_Cmd: ++ tst rValidCnt,#F_NUM1_MASK ++ beq Invalid ++ tst rNum1,#3 ++ bne Invalid ++ cmp rNum1,#MEM_START ++ bcc Invalid //br if rNum1 is below ram start, ++ //NOTE: arm sets the carry to the opposite of most processors on subtract, compare ++ ++ mov rDest,rNum1 ++ mov rDestHead,rNum1 ++ mov rPrevNum1,rNum1 ++ mov rPrevCRC,#0 ++ mov rRunningCRC,#0 ++ mov rNak,#L1(C) //current NAK character ++ mov rBlockNum,#1 //block # to receive ++ ++#if DDEBUG ++ b 47f ++91: ++ cmp rBlockNum,#1 ++ beq 47f ++ mov r2,#L1(1) ++ b 45f ++92: ++ mov r2,#L1(2) ++ b 45f ++93: ++ mov r2,#L1(3) ++ b 45f ++94: ++ mov r2,#L1(4) ++ b 45f ++95: ++ mov r2,#L1(5) ++45: ++ BigMov r0,L3(CAN,CAN,CAN) //abort ++ bl Transmit1 ++46: bl Receive ++ bne 46b //branch until timeout ++ mov r0,r2 ++ bl Transmit ++ b Invalid ++#else ++91: ++92: ++93: ++94: ++95: ++#endif ++ ++47: ++ ++ mov r0,rNak ++15: ++ bl Transmit ++2: bl Receive ++ beq 91b //branch on timeout ++ ++ mov rPacketLength,#128-1 ++ cmp r0,#SOH ++ addne rPacketLength,rPacketLength,#1024-1-(128-1) ++ cmpne r0,#STX ++ beq 3f ++ cmp r0,#CAN ++ bne 16f ++ bl Receive ++ cmp r0,#CAN ++ bne 10f ++ b Invalid ++16: cmp r0,#EOT ++ bne 10f ++ mov r0,#ACK ++ bl Transmit ++ ++#if DDEBUG ++ mov rDestHead,rDest ++ mov r0,rDest ++ bl PrintHex ++ bl TransmitSPACE ++ mov r0,rBlockNum ++ bl PrintHex ++ ++ bl TransmitSPACE ++ mov r0,rRunningCRC ++ bl PrintHex ++ mov rDest,rDestHead ++#endif ++ ++// now verify that ram is STILL valid by recomputing the CRC ++ mov rCRC,#0 ++ mov r1,rPrevNum1 ++ b 83f ++82: ++ ldrb r0,[r1],#1 ++// ++ eor r0,rCRC,r0,LSL #24 ++ eor r0,r0,r0,LSR #4 //c is in high byte of r0 ++ and r0,r0,#0xff000000 ++ ++ mov rCRC,rCRC,LSL #8 ++ eor rCRC,rCRC,r0,LSL #4 ++ orr rCRC,rCRC,r0,LSR #8 ++ ++ eor rCRC,rCRC,r0,LSR #3 ++// ++83: cmp r1,rDest ++ bne 82b ++#if DDEBUG ++ bl TransmitSPACE ++ mov r0,rCRC ++ bl PrintHex ++#endif ++ ++ cmp rCRC,rRunningCRC ++ bne 84f ++ BigMov r0,L3(O,K,SPACE) ++ bl Transmit1 ++ mov r0,rPrevNum1 ++ mov rDestHead,rDest ++ bl PrintHex ++ mov r0,#L1(MINUS) ++ bl Transmit ++ mov r0,rDestHead ++ bl PrintHex ++ b Prompt ++84: ++ BigMov r0,L4(E,R,R,O) ++ bl Transmit1 ++ mov r0,#L1(R) ++ bl Transmit ++ b Prompt ++ ++3: bl Receive ++ beq 92b ++ mov r2,r0 ++ bl Receive ++ beq 93b ++ eor r0,r0,#0xff ++ cmp r0,r2 //check 1's complement blk # ++ bne 10f ++ cmp r2,rBlockNum //check blk # ++ bne 20f ++80: ++ mov rDestHead,rDest //rDestHead - start of buffer, rDest end of buffer ++ mov rPrevCRC,rRunningCRC ++ mov rCRC,#0 //crc ++ ++//alternative CRC calculation routines ++ .if 0 ++ BigMov r2,CRC_POLY ++4: bl Receive ++ beq 8f //branch on timeout ++ eor rCRC,rCRC,r0,LSL #24 ++ mov r1,#8 ++5: ++ movs rCRC,rCRC,LSL #1 ++ eorcs rCRC,rCRC,r2 ++ subs r1,r1,#1 ++ bne 5b ++ strb r0,[rDest],#1 ++ subs rPacketLength,rPacketLength,#1 ++ bge 4b ++ mov rCRC,rCRC,LSR #16 //CRC was only in the high half ++ ++ .endif ++ ++ ++ ++ .if 1 ++4: bl Receive ++ beq 8f //branch on timeout ++// ++//calculate CRC ++//unsigned int crc = 0; ++//unsigned int c = 0; ++//for (i=3; i> 4); ++// c &= 0xff000000; ++// crc = (((crc<<8) ^ (c << 4)) | (c>>8)) ^ (c >> 3); ++//} ++//crc >>= 16; ++// ++ eor r1,rCRC,r0,LSL #24 ++ eor r1,r1,r1,LSR #4 ++ and r1,r1,#0xff000000 ++ ++ mov rCRC,rCRC,LSL #8 ++ eor rCRC,rCRC,r1,LSL #4 ++ orr rCRC,rCRC,r1,LSR #8 ++ eor rCRC,rCRC,r1,LSR #3 ++ ++//also save a running total CRC to use to verify RAM after download is complete ++// ++ eor r1,rRunningCRC,r0,LSL #24 ++ eor r1,r1,r1,LSR #4 //c is in high byte of r1 ++ and r1,r1,#0xff000000 ++ ++ mov rRunningCRC,rRunningCRC,LSL #8 ++ eor rRunningCRC,rRunningCRC,r1,LSL #4 ++ orr rRunningCRC,rRunningCRC,r1,LSR #8 ++ ++ eor rRunningCRC,rRunningCRC,r1,LSR #3 ++// ++#if LITTLE_ENDIAN ++ mov r0,r0,LSL #24 ++ orr r2,r0,r2,LSR #8 //this assumes a little endian memory system ++#else ++ orr r2,r0,r2,LSL #8 //this assumes a big endian memory system ++#endif ++ ++ tst rPacketLength,#3 ++ streq r2,[rDest],#4 ++ subs rPacketLength,rPacketLength,#1 ++ bge 4b ++ mov rCRC,rCRC,LSR #16 //CRC was only in the high half ++ .endif ++ ++ ++ ++ ++ bl Receive ++ beq 8f //branch on timeout ++ mov r2,r0 ++ bl Receive ++ beq 8f //branch on timeout ++ add r2,r0,r2,LSL #8 ++ cmp rCRC,r2 ++ bne 9f //branch on crc mismatch ++//packet is good ++ add rBlockNum,rBlockNum,#1 ++ and rBlockNum,rBlockNum,#0xff ++ mov rNak,#NAK ++ mov r0,#ACK ++ b 15b ++20: ++ sub r1,rBlockNum,#1 ++ and r1,r1,#0xff ++ cmp r1,r2 ++ bne 21f //br if not trying to transmit the packet I just ACKed ++ mov rDest,rDestHead //reset pointer to previous packet ++ mov rRunningCRC,rPrevCRC ++ mov rBlockNum,r1 //correct blk # ++ b 80b ++ ++21: BigMov r0,L3(CAN,CAN,CAN) //abort code ++ bl Transmit1 ++48: bl Receive ++ bne 48b //branch until timeout ++ ++#if DDEBUG ++ mov r0,r2 ++ bl PrintHex ++ bl TransmitSPACE ++ mov r0,rBlockNum ++ bl PrintHex ++#endif ++ ++ b Invalid //give up ++ ++ ++8: mov rDest,rDestHead //reset register ++ mov rRunningCRC,rPrevCRC ++ b 94b //send NAK ++9: ++#if DDEBUG //debug code ++ BigMov r0,L3(CAN,CAN,CAN) //abort code ++ bl Transmit1 ++44: bl Receive ++ bne 44b //branch until timeout ++ mov r0,r2 ++ bl PrintHex ++ bl TransmitSPACE ++ mov r0,rCRC ++ bl PrintHex ++ b Invalid ++#endif ++ ++ mov rDest,rDestHead ++ mov rRunningCRC,rPrevCRC ++ ++ ++10: bl Receive ++ bne 10b //branch until timeout ++ b 95b //send NAK and wait for packet ++ ++ ++ ++// ******************************************************************************************* ++// ******************************************************************************************* ++// ******************************************************************************************* ++// ******************************************************************************************* ++//Code above this point must fit in 2k mini cache or be burned on flash ++// ++//Code below this point need not be in the 2k mini-instruction cache, ++//it can be temporarily placed in the main instruction cache unlocked ++// ******************************************************************************************* ++ ++InitializeCont1: ++//pc - 0-0x4000, 0x04000000-0x04004000, 0xa000000-0xffffffff ++ InitIC_Clocks r0,sp ++ InitUART r0,sp,FFUART_BASE,BAUDRATE ++ InitUART r0,sp,BTUART_BASE,BAUDRATE ++ InitUART r0,sp,STUART_BASE,9600 ++ InitChangeCPUSpeed r0 ++ InitMemory r0,sp,r1 ++ BigMov r1,MACH_TYPE_SCANPASS ++ SaveRegisters r0,sp ++// ******************************************************* ++ InitMMU r0 ++ InitPWR r0,r1,sp //out: r1 RCSR ++InitializeCont2: ++ cmp pc,#MEM_START ++ bhs 89f //if in ram, must be mdebug ++ bic sp,pc,#FLASH_BASE_ADDRESS ++ cmp sp,#0x4000 ++ mov r2,#FUNC_REQ_GL ++ bhs 87f //br if not part of reset vector ++ tst r1,#RCSR_SLEEP_RESET ++ beq 89f //; Not sleep. ++ mov r2,#FUNC_REQ_WAKEUP ++87: adr r7,88f ++ adr lr,89f ++ mov r10,r1 //RCSR ++ b TryRoutine1 ++88: ldmia sp,{rPrevNum1,rUart,rDBG} ++89: ++ mov r2,lr ++ bl CalcMemEnd ++ mov r3,r0 ++ mov lr,r2 ++// ******************************************************* ++//0xnnnn0000 - 16k remapping of flash address 0 for relocated vector table ++//0xnnnn4000 - 16k 16k 1st level descriptors table ++//0xnnnn8000 - 16k 2 x 1k 2nd level descriptor tables ++//0xnnnnc000 - 16k 12k skipped, 4k debug data ++//end of ram ++ BigSub sp,r3,0x8000 ++ sub r2,sp,#0x4000 ++ mov r1,r2 ++ BigMov r0,0x0402 //section descriptor, ap-01, privileged r/w ++ //map virt to phys 1-to-1, non-cache, non-bufferable ++1: str r0,[r2],#4 ++ add r0,r0,#1<<20 ++ cmp r2,sp ++ bne 1b ++ ++ ++ add sp,r1,r3,LSR #(20-2) ++ add r1,r1,#((MEM_START>>20)&0xfff)<<2 //microsoft assembler bug propagates the sign bit ++ BigMov r0,(MEM_START&0xfff00000)+0x040A //cacheable (write through) ++2: str r0,[r1],#4 ++ cmp r1,sp ++ addne r0,r0,#1<<20 ++ bne 2b ++//r0 is physical address of last meg of memory ++ orr r1,r2,#1 //2nd level descriptor address (1k boundary), coarse page table ++ ++ .ifdef __ARMASM ++ GBLA TABLE_CNT ++ .endif ++ .if ((DEBUG_START&0xfff00000) - (0xffff0000&0xfff00000)) ++ .set TABLE_CNT,2 ++ str r1,[r2,#((DEBUG_START>>18)&0x3ffc)-0x4000] //r2 is the end of the 16k table ++ add r1,r1,#0x400 ++ ++ .else ++ .set TABLE_CNT,1 ++ .endif ++ ++ str r1,[r2,#-4] //map (0xfff00000) to 2nd level page table ++ //last meg of memory (contains relocated reset vector) ++ add sp,r2,#((256*TABLE_CNT)-16)<<2 //256 - 4byte entries each mapping 4k ++ ++//clear out 1 or 2 level 2 page tables ++ mov r1,#0 ++3: str r1,[r2],#4 ++ cmp r2,sp ++ bne 3b ++ ++ ++ BigMov r1,0x559 //map to flash in 1 - 64k page ++ add sp,sp,#16<<2 ++4: str r1,[r2],#4 ++ cmp r2,sp ++ bne 4b ++ ++ bic r0,r0,#0x000ff ++ orr r0,r0,#0x0000e //cacheable writeback 4k page ++// orr r0,r0,#0x0000a //cacheable writethru 4k page ++ orr r0,r0,#0x00aa0 //privileged r/w, user read ++ orr r0,r0,#0xff000 //last 4k of ram ++ ++ str r0,[r2,#((DEBUG_START>>10)&0x3fc)-(TABLE_CNT*0x400)] //debug variables, r2 is end of 1k tables ++ ++ BigMov r0,0xffffffff ++ CP15_DACR mcr,r0 ++ ++ BigSub r0,r3,0xc000 //MEM_END-0xc000 ++ CP15_TTBR mcr,r0 ++//enable MMU ++ CP15_TLB_UNLOCK_I mcr,r0 ++ CP15_TLB_UNLOCK_D mcr,r0 ++ CP15_TLB_INVAL_BOTH mcr,r0 ++ ++ CP15_CONTROL mrc,r1 //get the control register ++ orr r1,r1,#0x1 //set bit 0 - enable MMU ++ CPWAIT r0 ++ CP15_CONTROL mcr,r1 //set the control register ++ CPWAIT r0 ++ ++//enable the instruction cache ++ CP15_CF_UNLOCK_I mcr,r0 ++// CP15_CF_INVAL_I mcr,r0 //I might be running from cache only, don't invalidate ++ ++ orr r1,r1,#0x1000 //set bit 12 -- the I bit ++ CP15_CONTROL mcr,r1 //set the control register ++ CPWAIT r0 ++ ++//enable the data cache ++ CP15_CF_UNLOCK_D mcr,r0 ++ CP15_CF_INVAL_D mcr,r0 //this will also drain write buffer ++ CP15_CF_DRAIN mcr,r0 //make sure it is drained just to be very safe ++ ++ orr r1,r1,#0x4 //set bit 4 -- the D bit ++ CP15_CONTROL mcr,r1 //set the control register ++ CPWAIT r0 ++ ++ .if 0 ++//if not in halt mode, lock 64k of flash remap in instruction TLB(contains override relocated vector table) ++//halt mode uses the mini cache and physical addresses only for this ++ CP14_DCSR mrc,r0 ++ BigMov r1,0xffff0000 ++ tst r0,#0x40000000 ++//I am currently executing from flash, marked as uncacheable ++ CP15_TLB_LOCK_IENTRY mcreq,r1 //lock 64k if not in halt mode ++ CPWAIT r0 ++ .endif ++ ++//now lock debug data into data cache ++ BigMov r1,DEBUG_START ++ mov r2,#DEBUG_SPACE>>5 //3 or 4 cache lines to lock ++ CP15_TLB_LOCK_DENTRY mcr,r1 ++ mov sp,#1 ++ CP15_CF_LOCK_D_CSR mcr,sp //data cache is into lock mode ++ CPWAIT r0 ++5: pld [r1] ++ add r1,r1,#32 //lock and load ++ CP15_CF_DRAIN mcr,r0 ++ subs r2,r2,#1 ++ bne 5b ++ ++ mov sp,#0 ++ CP15_CF_LOCK_D_CSR mcr,sp //data cache is out of lock mode ++ CPWAIT r0 ++ ++ BigMov r0,0x3fff ++ CP15_CP_ACCESS mcr,r0 //enable access to all coprocessors ++//now disable MMU, Data Cache ++ .if 1 ++ CP15_CONTROL mrc,r1 //get the control register ++ bic r1,r1,#0x5 ++ CP15_CONTROL mcr,r1 //set the control register ++ CPWAIT r0 ++ .endif ++#if (DO_GPTEST==0) ++// TransMacro L1(U) ++ ++#if (PLATFORM_TYPE==BD2003) || (PLATFORM_TYPE==BOUNDARY_OLD_BOARD) || (PLATFORM_TYPE==OLD_GAME_CONTROLLER) || (PLATFORM_TYPE==HALOGEN) ++ sub r0,r3,#0x100000 //last meg-8k for video ram ++ sub r1,r3,#0x2000 //8K from end, last 4k is debug variables ++ str r1,[r1,#FDESC_FDADR] //next frame descriptor address, loop to self ++ str r0,[r1,#FDESC_FSADR] //start of frame ++ str r0,[r1,#FDESC_FIDR] //id of frame, anything I want ++ BigMov r2,SCREEN_WIDTH*SCREEN_HEIGHT*BYTES_PER_PIXEL ++ str r2,[r1,#FDESC_DCMD] //length of dma transfer ++ ++#if (BYTES_PER_PIXEL==2) ++ BigMov sp,(BLUE_VAL<<0)+(GREEN_VAL<<5)+(RED_VAL<<11) //rgb value ++ orr sp,sp,sp,LSL #16 ++79: str sp,[r0],#4 ++ subs r2,r2,#4 ++ bne 79b ++#else ++ BigMov r1,(BLUE_VAL<<0)+(GREEN_VAL<<6)+(RED_VAL<<12) //rgb value ++ orr r1,r1,r1,LSL #24 ++ ++ mov sp,r1,LSR #8 ++ orr sp,sp,sp,LSL #24 ++ ++ mov lr,sp,LSR #8 ++ orr lr,lr,lr,LSL #24 ++79: stmia r0!,{r1,sp,lr} ++ subs r2,r2,#12 ++ bne 79b ++ sub r1,r3,#0x2000 //8K from end, last 4k is debug variables ++#endif ++ ++ InitLCD r0,sp,r1 //r1 has descriptor address ++#endif ++ ++ ++// **************************** ++ mrs r1, CPSR ++ bic r2, r1,#PSR_MODE_MASK ++ orr r0, r2,#PSR_NOINTS_MASK+PSR_MODE_SVC //change to supervisor stack ++ msr CPSR_c, r0 ++ BigMov r0,SS_START+SS_SUPERVISOR ++ mov sp, r0 ++ ++ orr r2, r2, #PSR_NOINTS_MASK+PSR_MODE_IRQ //irq stack ++ msr CPSR_c, r2 ++ BigAdd sp, r0, SS_IRQ ++ ++ sub r2, r2, #PSR_MODE_IRQ-PSR_MODE_FIQ //fiq stack ++ msr CPSR_c, r2 ++ BigAdd sp, r0, SS_IRQ+SS_FIQ ++ ++ add r2, r2, #PSR_MODE_SYSTEM-PSR_MODE_FIQ //system(user mode) ++ msr CPSR_c, r2 ++ BigAdd sp, r0, SS_IRQ+SS_FIQ+SS_SYSTEM ++ ++ sub r2, r2, #PSR_MODE_SYSTEM-PSR_MODE_UNDEF //undefined stack ++ msr CPSR_c, r2 ++ BigAdd sp, r0, SS_IRQ+SS_FIQ+SS_SYSTEM+SS_UNDEFINED ++ ++ sub r2, r2, #PSR_MODE_UNDEF-PSR_MODE_ABORT //Abort stack ++ msr CPSR_c, r2 ++ BigAdd sp, r0, SS_IRQ+SS_FIQ+SS_SYSTEM+SS_UNDEFINED+SS_ABORT ++// ++ msr CPSR_c, r1 ++ sub r2, r2, #PSR_MODE_ABORT-PSR_MODE_SVC //supervisor stack ++ ++// **************************** ++ CP14_DCSR mrc,sp ++ tst sp,#1<<5 //test sticky abort bit ++ mov sp,r0 ++ BigMovEq r0,DEBUG_BASE+DBG_MAGIC ++ BigAddNe r0,r3,(-0x1000+((DEBUG_BASE+DBG_MAGIC)&0xfff)) //don't use virtual address if memory isn't working right ++ sub r0,r0,#DBG_MAGIC ++ ++ and r1,r1,#PSR_MODE_MASK ++ mov r3,#0 ++ cmp r1,#PSR_MODE_DEBUG ++ BigMov lr,0xa0008000 //default start pc ++ beq SaveDebug //br if a debug exception in halt mode ++ mov r1,#SIG_RESET ++ b SaveR4andUp ++#else ++//#define GPBIT 2 ++//#define GPL GPLR1 ++#define GPBIT 9 ++#define GPL GPLR0 ++#define GPMASK (1< ++ * Copyright (C) 1999 Magnus Damm ++ * Copyright (C) 2000 Wolfgang Denk ++ * Copyright (C) 2001 Alex Zuepke ++ * Copyright (C) 2002 Kyle Harris ++ * Copyright (C) 2003 Robert Schwebel ++ * Copyright (C) 2003 Kai-Uwe Bloem ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++ ++#define Mode_SVC 0x13 ++#define NoIntsMask 0xc0 ++.globl _bss_start ++.globl _bss_end ++ ++//defined globals ++.globl HeadStart ++.globl _armboot_start ++ ++//r3 - display type ++HeadStart: ++ mov r8,r0 //there is a check for this instruction before jumping here ++ ++// ******************************************************************** ++// Set processor into Supervisior mode (SVC) and disable IRQ & FIQ ++// ++ mrs r0, CPSR ++ bic r0, r0,#0x1f ++ orr r0, r0,#(Mode_SVC | NoIntsMask) ++ msr cpsr_c, r0 ++//exit SDS, if currently active ++ msr SPSR, r0 ++ adr lr,1f ++ movs pc,lr ++1: ++ b relocate ++// ******************************************************************** ++_armboot_start: ++_TEXT_BASE: .word TEXT_BASE ++ ++_start_armboot: .word start_armboot ++/* ++ * These are defined in the board-specific linker script. ++ */ ++_bss_start: .word __bss_start ++_bss_end: .word _end ++ ++#ifdef CONFIG_USE_IRQ ++/* IRQ stack memory (calculated at run-time) */ ++.globl IRQ_STACK_START ++IRQ_STACK_START: ++ .word 0x0badc0de ++ ++/* IRQ stack memory (calculated at run-time) */ ++.globl FIQ_STACK_START ++FIQ_STACK_START: ++ .word 0x0badc0de ++#endif ++ ++relocate: /* relocate U-Boot to RAM */ ++ adr r0, HeadStart /* r0 <- current position of code */ ++ bic r0,r0,#0xff ++ bic r0,r0,#0xff00 //64k aligned ++ ldr r1, _TEXT_BASE ++ cmp r0, r1 /* don't reloc during debug */ ++ beq stack_setup ++ ++ ldr r2, _bss_start ++ ++copy_loop: ++ ldmia r0!, {r3-r10} /* copy from source address [r0] */ ++ stmia r1!, {r3-r10} /* copy to target address [r1] */ ++ cmp r1, r2 /* until dest end addreee [r2] */ ++ ble copy_loop ++ ++ /* Set up the stack */ ++stack_setup: ++ ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ ++ BigSub2 r0,(CFG_MALLOC_LEN+CFG_GBL_DATA_SIZE+CFG_MMU_SPACE_RESERVED) //malloc area,bdinfo ++#ifdef CONFIG_USE_IRQ ++ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) ++#endif ++ sub sp, r0, #12 /* leave 3 words for abort-stack */ ++ ++clear_bss: ++ ldr r0, _bss_start /* find start of bss segment */ ++ ldr r1, _bss_end /* stop here */ ++ mov r2, #0x00000000 /* clear */ ++ ++clbss_l:str r2, [r0] /* clear loop... */ ++ add r0, r0, #4 ++ cmp r0, r1 ++ bne clbss_l ++ bl dcache_enable ++ ++ ldr pc, _start_armboot ++ ++ ++FlushCache: ++ CP15_CONTROL mrc,r0 ++ tst r0, #4 //is data cache enabled ++ beq 2f ++// b 2f ++ mov r1, #2048 ++ add r0,pc,#0x20000 //make sure I don't alloc a line in this subroutine ++ BigBic2 r0, 0xffff ++1: CP15_CF_ALLOC_LINE mcr,r0 ++ add r0, r0, #0x20 ++ subs r1, r1, #1 ++ bne 1b ++ ++ CP15_CF_DRAIN mcr,r0 ++ CPWAIT r0 ++2: CP15_CF_INVAL_BOTH mcr,r0 ++ CPWAIT r0 ++ mov pc, lr ++ ++ ++ ++//void dcache_disable (void) ++.globl dcache_disable ++dcache_disable: ++ mov r3,lr ++ bl FlushCache ++ CP15_CONTROL mrc,r1 ++ ++ BigBic2 r1, 0x2805 //disable high vector, branch target buffer, disable data cache, MMU ++ .balignl 32,0xe1a00000 //cacheline boundary (32 bytes) ++ //Needed so that if new flash is burnt ++ //and flash != ram copy, ++ //mov pc, r3 will be in cache and execute correctly ++ //(r3 is 0) return to the reset vector ++ CP15_CONTROL mcr,r1 ++ CPWAIT r0 ++ mov pc, r3 ++ ++ ++//int dcache_status (void) ++.globl dcache_status ++dcache_status: ++ CP15_CONTROL mrc,r0 //get the control register ++ and r0,r0,#1 ++ mov pc,lr ++ ++#define MEM_START1 0xa0000000 ++#define MEM_END1 0xa4000000 ++//void dcache_enable (void) ++.globl dcache_enable ++dcache_enable: ++ stmdb sp!,{r5,r6,lr} ++ bl FlushCache ++#if !defined(CFG_MMU_SPACE_RESERVED) || (CFG_MMU_SPACE_RESERVED<(1<<14)) ++ mov r0,#1<<15 //16k plus alignment of 16k ++ bl malloc ++ add r6,r0,#(1<<14) //16k alignment ++ BigBic2 r6,(1<<14)-1 ++#else ++ ldr r6, _TEXT_BASE /* upper 128 KiB: relocated uboot */ ++ BigSub2 r6,(CFG_MMU_SPACE_RESERVED) //malloc area,bdinfo ++#endif ++ mov r2,r6 ++ add r5,r6,#(1<<14) //16k 1st level page table ++ BigMov r0,0x0402 //section descriptor, ap-01, privileged r/w ++ //map virt to phys 1-to-1, non-cache, non-bufferable ++1: str r0,[r2],#4 ++ add r0,r0,#1<<20 ++ cmp r2,r5 ++ bne 1b ++ ++ ++ mov r3,#MEM_END1 ++ add r5,r6,r3,LSR #(20-2) ++ add r1,r6,#(MEM_START1>>20)<<2 ++ BigMov r0,(MEM_START1&0xfff00000)+0x040A //cacheable (write through) ++2: str r0,[r1],#4 ++ cmp r1,r5 ++ addne r0,r0,#1<<20 ++ bne 2b ++ ++ BigMov r0,0xffffffff ++ CP15_DACR mcr,r0 ++ ++ CP15_TTBR mcr,r6 ++//enable MMU ++ CP15_TLB_UNLOCK_I mcr,r0 ++ CP15_TLB_UNLOCK_D mcr,r0 ++ CP15_TLB_INVAL_BOTH mcr,r0 ++ ++ CP15_CONTROL mrc,r1 //get the control register ++ BigOrr2 r1,0x201 // enable MMU, r bit ++ BigBic2 r1,0x100 // disable S bit, ap -0 means read only by all ++ CPWAIT r0 ++ CP15_CONTROL mcr,r1 //set the control register ++ CPWAIT r0 ++ ++//enable the instruction cache ++ CP15_CF_UNLOCK_I mcr,r0 ++// CP15_CF_INVAL_I mcr,r0 //I might be running from cache only, don't invalidate ++ ++ orr r1,r1,#0x1000 //set bit 12 -- the I bit ++ CP15_CONTROL mcr,r1 //set the control register ++ CPWAIT r0 ++ ++//enable the data cache ++// CP15_CF_UNLOCK_D mcr,r0 ++ CP15_CF_INVAL_D mcr,r0 //this will also drain write buffer ++ CP15_CF_DRAIN mcr,r0 //make sure it is drained just to be very safe ++ ++ orr r1,r1,#0x4 //set bit 4 -- the D bit ++ CP15_CONTROL mcr,r1 //set the control register ++ CPWAIT r0 ++ ++ BigMov r0,0x3fff ++ CP15_CP_ACCESS mcr,r0 //enable access to all coprocessors ++ ldmia sp!,{r5,r6,pc} ++ ++ ++ ++/****************************************************************************/ ++/* */ ++/* Reset function: the PXA250 doesn't have a reset function, so we have to */ ++/* perform a watchdog timeout for a soft reset. */ ++/* */ ++/****************************************************************************/ ++.globl reset_cpu ++ /* FIXME: this code is PXA250 specific. How is this handled on */ ++ /* other XScale processors? */ ++ ++reset_cpu: ++ BigMov r0,0x40a00000 //OSTIMER_BASE ++ /* We set OWE:WME (watchdog enable) and wait until timeout happens */ ++ ++ ldr r1, [r0, #OWER] ++ orr r1, r1, #0x0001 /* bit0: WME */ ++ str r1, [r0, #OWER] ++ ++ /* OS timer does only wrap every 1165 seconds, so we have to set */ ++ /* the match register as well. */ ++ ++ ldr r1, [r0, #OSCR] /* read OS timer */ ++ add r1, r1, #0x800 /* let OSMR3 match after */ ++ add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */ ++ str r1, [r0, #OSMR3] ++ ++reset_endless: ++ b reset_endless +diff -u -r --new-file u-boot-1.1.2/cpu/pxa/mmc.c u-boot-1.1.2-neon/cpu/pxa/mmc.c +--- u-boot-1.1.2/cpu/pxa/mmc.c 2003-10-16 01:53:52.000000000 +0200 ++++ u-boot-1.1.2-neon/cpu/pxa/mmc.c 2007-08-11 21:07:20.000000000 +0200 +@@ -27,6 +27,7 @@ + #include + #include + #include ++#include + + #ifdef CONFIG_MMC + +@@ -47,9 +48,19 @@ + static uchar mmc_buf[MMC_BLOCK_SIZE]; + static mmc_csd_t mmc_csd; + static int mmc_ready = 0; ++static int isSD = 0 ; ++static int startBlock = 0 ; ++static ushort RCA = MMC_DEFAULT_RCA ; ++static struct partition part ; + ++static void stop_clock( void ) ++{ ++ MMC_STRPCL = MMC_STRPCL_STOP_CLK; ++ MMC_I_MASK = ~MMC_I_MASK_CLK_IS_OFF; ++ while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF)); ++} + +-static uchar * ++uchar * + /****************************************************/ + mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat) + /****************************************************/ +@@ -59,9 +70,8 @@ + int words, i; + + debug("mmc_cmd %x %x %x %x\n", cmd, argh, argl, cmdat); +- MMC_STRPCL = MMC_STRPCL_STOP_CLK; +- MMC_I_MASK = ~MMC_I_MASK_CLK_IS_OFF; +- while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF)); ++ stop_clock(); ++ + MMC_CMD = cmd; + MMC_ARGH = argh; + MMC_ARGL = argl; +@@ -71,9 +81,10 @@ + while (!(MMC_I_REG & MMC_I_REG_END_CMD_RES)); + + status = MMC_STAT; +- debug("MMC status %x\n", status); ++ debug("MMC status %lx\n", status); + if (status & MMC_STAT_TIME_OUT_RESPONSE) + { ++ printf( "mmc_cmd timeout: cmd: 0x%x, args: 0x%04x%04x, status 0x%lx\n", cmd, argh, argl, status ); + return 0; + } + +@@ -85,7 +96,7 @@ + break; + + case MMC_CMDAT_R2: +- words = 8; ++ words = 9; + break; + + default: +@@ -109,6 +120,22 @@ + return resp; + } + ++static void mmc_setblklen( ulong blklen ) ++{ ++ static ulong prevLen = -1UL ; ++ if( blklen != prevLen ) ++ { ++ ushort argh, argl ; ++ ++ argh = blklen >> 16; ++ argl = blklen & 0xffff; ++ ++ /* set block len */ ++ mmc_cmd( MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1); ++ prevLen = blklen ; ++ } ++} ++ + int + /****************************************************/ + mmc_block_read(uchar *dst, ulong src, ulong len) +@@ -117,20 +144,18 @@ + uchar *resp; + ushort argh, argl; + ulong status; ++ unsigned char volatile *rxFIFO = (unsigned char *)&(MMC_RXFIFO); + + if (len == 0) + { + return 0; + } + +- debug("mmc_block_rd dst %lx src %lx len %d\n", (ulong)dst, src, len); ++ debug("mmc_block_rd dst %lx src %lx len %ld\n", (ulong)dst, src, len); + +- argh = len >> 16; +- argl = len & 0xffff; +- +- /* set block len */ +- resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1); ++ mmc_setblklen( len ); + ++ src += (startBlock*MMC_BLOCK_SIZE); + /* send read command */ + argh = src >> 16; + argl = src & 0xffff; +@@ -147,15 +172,14 @@ + { + if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) + { +- *dst++ = MMC_RXFIFO; +- len--; +- } +- status = MMC_STAT; +- if (status & MMC_STAT_ERRORS) +- { +- printf("MMC_STAT error %lx\n", status); +- return -1; ++ int i, bytes = min(32,len); ++ len -= bytes; ++ ++ for (i=0; i> 16, ++ src & 0xFFFF, ++ MMC_CMDAT_R1|MMC_CMDAT_READ|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN ); ++ ++ // read the data ++ for( blknr = 0 ; blknr < blkcnt ; blknr++ ) ++ { ++ unsigned len = MMC_BLOCK_SIZE ; ++ ++ while (len) ++ { ++ int i ; ++ MMC_I_MASK = ~MMC_I_MASK_RXFIFO_RD_REQ; ++ while( (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) == 0 ) ++ { ++ } ++ ++ for (i = 0; i < 32 ; i++ ) ++ { ++ *dstb++ = *rxFIFO ; ++ } ++ len -= 32 ; ++ } ++ } // for each block ++ ++ MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE; ++ while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)); ++ status = MMC_STAT; ++ if (status & MMC_STAT_ERRORS) ++ { ++ printf("MMC_STAT error %lx\n", status); ++ return -1; ++ } ++// printf( "completed mread... now stop\n" ); ++ ++ mmc_cmd( MMC_CMD_STOP, 0, 0, MMC_CMDAT_R1); ++ ++ } // multi-block read ++ } // or why bother? + return blkcnt; + } + ++static void dumpResponse( uchar *resp, unsigned bytes ) ++{ ++ debug( "rsp: " ); ++ if( resp ) ++ { ++ while( bytes-- ) ++ debug( "%02X ", *resp++ ); ++ debug( "\n" ); ++ } ++ else ++ debug( "NULL\n" ); ++} ++ ++int SDCard_test( void ) ++{ ++ unsigned short response ; ++ unsigned long ignore ; ++ unsigned char *resp ; ++ ++ mmc_cmd(0, 0, 0, 0); ++ ++ resp = mmc_cmd(SD_APP_CMD55, 0, 0, MMC_CMDAT_R1); ++ if( !resp ) ++ { ++ printf( "SDInitErr1\n" ); ++ return -ENODEV ; ++ } ++ ++ resp = mmc_cmd(SD_APP_CMD41, 0x0020, 0, MMC_CMDAT_INIT|MMC_CMDAT_R1); ++ if( !resp ) ++ { ++ printf( "SDInitErr2\n" ); ++ return -ENODEV ; ++ } ++ ++ memcpy( &response, resp, sizeof( response ) ); ++ ++ while (response != 0x3f80)//continue doing ACMD1 until busy bit in response is set ++ { ++ //CMD55 APP_CMD ++ MMC_STRPCL = 0x00000001;//stop clock ++ while ((MMC_STAT & 0x00000100) == 0x00000100); //wait for clock to stop ++ MMC_CMD = 0x00000037;//CMD55 index APP_CMD ++ MMC_ARGH = 0x00000000;//relative card address 0x0 ++ MMC_ARGL = 0x00000000;//stuff bits ++ MMC_CMDAT = 0x00000001;//expect response 1 ++ MMC_STRPCL = 0x00000002;//start clock ++ while ((MMC_STAT & 0x00002000) == 0x00000000);//wait for end_cmd_res ++ //read response FIFO ++ response = MMC_RES & 0x0000ffff ; ++ ignore = MMC_RES ; ++ ignore = MMC_RES ; ++ ++ //ACMD41 ++ MMC_STRPCL = 0x00000001;//stop clock ++ while ((MMC_STAT & 0x00000100) == 0x00000100); //wait for clock to stop ++ MMC_CMD = 0x00000029;//ACMD41 index SD_APP_SEND_OP_COND ++ MMC_ARGH = 0x00000020;//set voltage limit of system in command argument ++ MMC_ARGL = 0x00000000; ++ MMC_CMDAT = 0x00000003;//expect response 3 ++ MMC_STRPCL = 0x00000002;//start clock ++ while ((MMC_STAT & 0x00002000) == 0x00000000);//wait for end_cmd_res ++ ++ //read response FIFO ++ response = MMC_RES & 0x0000ffff ; ++ ignore = MMC_RES ; ++ ignore = MMC_RES ; ++ } ++ ++ return 0 ; ++} ++ ++#ifdef DEBUG ++static void print_mmc_csd( struct mmc_csd *csd ) ++{ ++ printf( "ecc: %u\n", csd->ecc ); ++ printf( "file_format: %u\n", csd->file_format ); ++ printf( "tmp_write_protect: %u\n", csd->tmp_write_protect ); ++ printf( "perm_write_protect: %u\n", csd->perm_write_protect ); ++ printf( "copy: %u\n", csd->copy ); ++ printf( "file_format_grp: %u\n", csd->file_format_grp ); ++ printf( "content_prot_app: %u\n", csd->content_prot_app ); ++ printf( "rsvd3: %u\n", csd->rsvd3 ); ++ printf( "write_bl_partial: %u\n", csd->write_bl_partial ); ++ printf( "write_bl_len: %u\n", csd->write_bl_len ); ++ printf( "r2w_factor: %u\n", csd->r2w_factor ); ++ printf( "default_ecc: %u\n", csd->default_ecc ); ++ printf( "wp_grp_enable: %u\n", csd->wp_grp_enable ); ++ printf( "wp_grp_size: %u\n", csd->wp_grp_size ); ++ printf( "erase_grp_mult: %u\n", csd->erase_grp_mult ); ++ printf( "erase_grp_size: %u\n", csd->erase_grp_size ); ++ printf( "c_size_mult1: %u\n", csd->c_size_mult1 ); ++ printf( "vdd_w_curr_max: %u\n", csd->vdd_w_curr_max ); ++ printf( "vdd_w_curr_min: %u\n", csd->vdd_w_curr_min ); ++ printf( "vdd_r_curr_max: %u\n", csd->vdd_r_curr_max ); ++ printf( "vdd_r_curr_min: %u\n", csd->vdd_r_curr_min ); ++ printf( "c_size: %u\n", csd->c_size ); ++ printf( "rsvd2: %u\n", csd->rsvd2 ); ++ printf( "dsr_imp: %u\n", csd->dsr_imp ); ++ printf( "read_blk_misalign: %u\n", csd->read_blk_misalign ); ++ printf( "write_blk_misalign: %u\n", csd->write_blk_misalign ); ++ printf( "read_bl_partial: %u\n", csd->read_bl_partial ); ++ printf( "read_bl_len: %u\n", csd->read_bl_len ); ++ printf( "ccc: %u\n", csd->ccc ); ++ printf( "tran_speed %u\n", csd->tran_speed ); ++ printf( "nsac; %u\n", csd->nsac ); ++ printf( "taac; %u\n", csd->taac ); ++ printf( "rsvd1: %u\n", csd->rsvd1 ); ++ printf( "spec_vers: %u\n", csd->spec_vers ); ++ printf( "csd_structure: %u\n", csd->csd_structure ); ++} ++#endif ++ ++#define DOS_PART_MAGIC_OFFSET 0x1fe ++#define DOS_FS_TYPE_OFFSET 0x36 ++#define MSDOS_LABEL_MAGIC1 0x55 ++#define MSDOS_LABEL_MAGIC2 0xAA ++ ++struct bpb { // see http://staff.washington.edu/dittrich/misc/fatgen103.pdf ++ unsigned char jump[3]; ++ char oemName[8]; ++ unsigned short bytesPerSector ; ++ unsigned char sectorsPerCluster ; ++ unsigned short reservedSectorCount ; ++ unsigned char numFats ; ++ unsigned short rootEntCount ; ++ unsigned short totalSec16 ; ++ unsigned char media ; // 0xF8 ++ unsigned short fatSz16 ; ++ unsigned short secPerTrack ; ++ unsigned short numHeads ; ++ unsigned long hiddenSectors ; ++ unsigned long totalSectors32 ; ++ unsigned char driveNum ; ++ unsigned char reserved1 ; // 0x00 ++ unsigned char bootSig ; // 0x29 ++ unsigned long volumeId ; ++ char volumeLabel[11]; ++ char fileSysType[8]; ++} __attribute__((packed)); ++ ++#define isprint(__c) (((__c)>=0x20)&&((__c)<=0x7f)) ++ ++static int find_mbr( int max_blocks ) ++{ ++ int i ; ++ ulong addr = 0 ; ++ ++printf( "---- searching %d blocks for MBR\n", max_blocks ); ++ ++ for( i = 0 ; i < 10 ; i++, addr += MMC_BLOCK_SIZE ) ++ { ++ uchar data[MMC_BLOCK_SIZE]; ++ if( 0 == mmc_block_read(data, addr, sizeof(data) )) ++ { ++ memcpy( &part, data+0x1be, sizeof(part)); ++ if( ( data[DOS_PART_MAGIC_OFFSET] == MSDOS_LABEL_MAGIC1 ) ++ && ++ ( data[DOS_PART_MAGIC_OFFSET + 1] == MSDOS_LABEL_MAGIC2 ) ) ++ { ++ if( ( ('\x00' == part.boot_ind ) ++ || ++ ('\x80' == part.boot_ind ) ) ++ && ++ ( 10 > part.head ) ++ && ++ ( part.end_head >= part.head ) ) ++ { ++ printf( "partition info found at block %u\n", i ); ++ printf( "boot:%02x head:%02x sec:%02x cyl:%02x sys:%02x endh:%02x ends:%02x endc:%02x start:%08x, count:%08x\n", ++ part.boot_ind, part.head, part.sector, part.cyl, ++ part.sys_ind, part.end_head, part.end_sector, part.end_cyl, ++ part.start_sect, part.nr_sects ); ++ printf( "MBR found at block %d\n", i ); ++ return part.start_sect ; ++ } ++ else { ++ struct bpb const *bootParams = (struct bpb *)data ; ++ unsigned j ; ++ for( j = 0 ; j < sizeof(data); j++ ) ++ { ++ if( 0 == ( j & 0x0f ) ) ++ printf( "%04x ", j ); ++ printf( "%02x ", data[j] ); ++ if( 7 == ( j & 7 ) ) ++ printf( " " ); ++ if( 0x0f == ( j & 0x0f ) ) ++ { ++ unsigned b ; ++ for( b = j-15 ; b <= j ; b++ ) ++ { ++ uchar c = data[b]; ++ if( isprint(c) ) ++ printf( "%c", c ); ++ else ++ printf( "." ); ++ if( 7 == ( b & 7 ) ) ++ printf( " " ); ++ } ++ printf( "\n" ); ++ } ++ } ++ printf( "Invalid MBR\n" ); ++ printf( "---> Boot Parameter block\n" ); ++ printf( "jump %02x %02x %02x\n", bootParams->jump[0],bootParams->jump[1],bootParams->jump[2]); ++ printf( "bytesPerSector: %04x\n", bootParams->bytesPerSector ); ++ printf( "sectorsPerCluster: %02x\n", bootParams->sectorsPerCluster ); ++ printf( "reservedSectors %04x\n", bootParams->reservedSectorCount ); ++ printf( "numFats: %02x\n", bootParams->numFats ); ++ printf( "rootEntCount: %04x\n", bootParams->rootEntCount ); ++ printf( "totalSec16: %04x\n", bootParams->totalSec16 ); ++ printf( "media: %02x\n", bootParams->media ); ++ printf( "fatsz16: %04x", bootParams->fatSz16 ); ++ printf( "secPerTrack: %04x\n", bootParams->secPerTrack ); ++ printf( "numHeads = %04x\n", bootParams->numHeads ); ++ printf( "hidden = %08lx\n", bootParams->hiddenSectors ); ++ printf( "totalSec32 = %08lx\n", bootParams->totalSectors32 ); ++ printf( "drive #%u\n", bootParams->driveNum ); ++ printf( "reserved1: %02x\n", bootParams->reserved1 ); ++ printf( "bootSig: %02x\n", bootParams->bootSig ); ++ printf( "volume: %08lx\n", bootParams->volumeId ); ++ part.boot_ind = 0 ; ++ part.head = 0 ; ++ part.sector = 2 ; ++ part.cyl = 0 ; ++ part.sys_ind = 6 ; ++ part.end_head = bootParams->numHeads ; ++ part.end_sector = 0xe0 ; ++ part.end_cyl = 0xc9 ; ++ part.start_sect = 0 ; ++ part.nr_sects = bootParams->totalSectors32 ; ++ printf( "partition info found at block %u\n", i ); ++ printf( "boot:%02x head:%02x sec:%02x cyl:%02x sys:%02x endh:%02x ends:%02x endc:%02x start:%08x, count:%08x\n", ++ part.boot_ind, part.head, part.sector, part.cyl, ++ part.sys_ind, part.end_head, part.end_sector, part.end_cyl, ++ part.start_sect, part.nr_sects ); ++ printf( "MBR found at block %d\n", i ); ++ return 0 ; ++ } ++ } ++ } ++ else ++ { ++ printf( "!!! Error reading mmc block %u\n", i ); ++ break; ++ } ++ } ++ ++ printf( "MBR not found!\n" ); ++ return -1 ; ++} ++ + int + /****************************************************/ + mmc_init(int verbose) +@@ -406,7 +741,8 @@ + { + int retries, rc = -ENODEV; + uchar *resp; +- ++ mmc_cid_t *cid ; ++ mmc_csd_t *csd ; + #ifdef CONFIG_LUBBOCK + set_GPIO_mode( GPIO6_MMCCLK_MD ); + set_GPIO_mode( GPIO8_MMCCS0_MD ); +@@ -419,23 +755,63 @@ + MMC_RESTO = MMC_RES_TO_MAX; + MMC_SPI = MMC_SPI_DISABLE; + ++ if( 0 == SDCard_test() ) ++ { ++ printf( "SD card detected!\n" ); ++ isSD = 1 ; ++ } ++ else ++ { ++ isSD = 0 ; ++ + /* reset */ +- retries = 10; +- resp = mmc_cmd(0, 0, 0, 0); ++ mmc_cmd(0, 0, 0, 0); + resp = mmc_cmd(1, 0x00ff, 0xc000, MMC_CMDAT_INIT|MMC_CMDAT_BUSY|MMC_CMDAT_R3); +- while (retries-- && resp && !(resp[4] & 0x80)) ++ if( 0 == resp ) ++ { ++ printf( "MMC CMD1 error\n" ); ++ return -1 ; ++ } ++ ++ printf( "init: " ); dumpResponse( resp, 6 ); ++ retries = 0 ; ++ do + { +- debug("resp %x %x\n", resp[0], resp[1]); +- udelay(50); ++ udelay(100); + resp = mmc_cmd(1, 0x00ff, 0xff00, MMC_CMDAT_BUSY|MMC_CMDAT_R3); ++ debug( "cmd1: " ); dumpResponse( resp, 6 ); ++ retries++ ; ++ } while( resp && ( 0 == ( resp[4] & 0x80 ) ) ); ++ ++ if( 0 == resp ) ++ { ++ printf( "MMC CMD1 error2\n" ); ++ return -1 ; ++ } ++ ++ do { ++ udelay(100); ++ resp = mmc_cmd(1, 0x00ff, 0xff00, MMC_CMDAT_BUSY|MMC_CMDAT_R3); ++ debug( "cmd1: " ); dumpResponse( resp, 6 ); ++ retries++ ; ++ } while( resp && ( 0 != ( resp[4] & 0x80 ) ) ); ++ ++ printf( "after busy: %s, %d retries\n", ++ resp ? "have INIT response" ++ : "no INIT response", ++ retries ); + } + + /* try to get card id */ + resp = mmc_cmd(2, 0, 0, MMC_CMDAT_R2); +- if (resp) ++ if( !resp ) + { ++ printf( "Bad CMDAT_R2 response\n" ); ++ return -1 ; ++ } ++ + /* TODO configure mmc driver depending on card attributes */ +- mmc_cid_t *cid = (mmc_cid_t *)resp; ++ cid = (mmc_cid_t *)resp; + if (verbose) + { + printf("MMC found. Card desciption is:\n"); +@@ -449,6 +825,12 @@ + printf("Month = %d\n",cid->month); + printf("Year = %d\n",1997 + cid->year); + } ++ sprintf(mmc_dev.product,"%s",cid->name); ++ sprintf(mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x", ++ cid->id[0], cid->id[1], cid->id[2], ++ cid->sn[0], cid->sn[1], cid->sn[2]); ++ sprintf(mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev); ++ + /* fill in device description */ + mmc_dev.if_type = IF_TYPE_MMC; + mmc_dev.dev = 0; +@@ -457,30 +839,118 @@ + /* FIXME fill in the correct size (is set to 32MByte) */ + mmc_dev.blksz = 512; + mmc_dev.lba = 0x10000; +- sprintf(mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x", +- cid->id[0], cid->id[1], cid->id[2], +- cid->sn[0], cid->sn[1], cid->sn[2]); +- sprintf(mmc_dev.product,"%s",cid->name); +- sprintf(mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev); + mmc_dev.removable = 0; + mmc_dev.block_read = mmc_bread; + + /* MMC exists, get CSD too */ + resp = mmc_cmd(MMC_CMD_SET_RCA, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1); +- resp = mmc_cmd(MMC_CMD_SEND_CSD, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R2); +- if (resp) ++ ++ if( resp ) + { +- mmc_csd_t *csd = (mmc_csd_t *)resp; +- memcpy(&mmc_csd, csd, sizeof(csd)); +- rc = 0; +- mmc_ready = 1; +- /* FIXME add verbose printout for csd */ ++ if( isSD ) ++ RCA = ((ushort)resp[4] << 8 ) | resp[3]; ++ else ++ RCA = MMC_DEFAULT_RCA ; + } ++ else ++ { ++ printf( "no SET_RCA response\n" ); ++ return -1 ; + } + ++#if 0 ++/* ++ * According to a Toshiba doc, the following is supposed to give ++ * the size of the 'protected' area (so we can ignore it). ++ ++ * Unfortunately, I can't get the numbers to add up, so we walk ++ * til we find an MBR instead. ++ */ ++ if( isSD ) ++ { ++ printf( "sending CMD55\n" ); ++ resp = mmc_cmd(SD_APP_CMD55, RCA, 0, MMC_CMDAT_R1); ++ if( !resp ) ++ { ++ printf( "Error 0x%04x sending APP CMD\n", MMC_STAT ); ++ return -1 ; ++ } ++ else ++ { ++ printf( "have CMD55 response\n" ); ++ memset( resp, 0, 20 ); ++ } ++ ++ resp = mmc_cmd(SD_STATUS, RCA, 0, MMC_CMDAT_R1 ); ++ if( resp ) ++ { ++ sd_status_t *status ; ++ int i ; ++ printf( "SDSTATUS returned\n" ); ++ for( i = 0 ; i < 16 ; i++ ) ++ printf( "%02x ", resp[i] ); ++ printf( "\n" ); ++ status = (sd_status_t *)resp ; ++ printf( "bus_width: %u\n", status->bus_width ); ++ printf( "secured_mode: %u\n", status->secured_mode ); ++ printf( "unused0: %x\n", status->unused0 ); ++ printf( "card_type: %x\n", status->card_type ); ++ printf( "prot_size: %lx\n", status->prot_size ); ++ } ++ else ++ { ++ printf( "Error reading SD_STATUS\n" ); ++ return -1 ; ++ } ++ } ++#endif ++ ++ MMC_STRPCL = MMC_STRPCL_STOP_CLK; ++ MMC_I_MASK = ~MMC_I_MASK_CLK_IS_OFF; ++ while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF)); ++ + MMC_CLKRT = 0; /* 20 MHz */ +- resp = mmc_cmd(7, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1); ++ resp = mmc_cmd(7, RCA, 0, MMC_CMDAT_R1); ++ if( !resp ) ++ { ++ printf( "Error selecting RCA %x\n", RCA ); ++ return -1 ; ++ } ++ ++ resp = mmc_cmd(7, 0, 0, MMC_CMDAT_R1); ++ if( !resp ) ++ { ++ // this is normal ++ } ++ ++ resp = mmc_cmd(MMC_CMD_SEND_CSD, RCA, 0, MMC_CMDAT_R2); ++ if (!resp) ++ { ++ printf( "Error reading CSD\n" ); ++ return -1 ; ++ } ++ ++ csd = (mmc_csd_t *)resp; ++ memcpy(&mmc_csd, csd, sizeof(*csd)); ++ rc = 0; ++ ++#ifdef DEBUG ++ dumpResponse( resp, sizeof( *csd ) ); ++ print_mmc_csd( csd ); ++#endif ++ ++ resp = mmc_cmd(7, RCA, 0, MMC_CMDAT_R1); ++ if( !resp ) ++ { ++ printf( "Error selecting RCA %x\n", RCA ); ++ return -1 ; ++ } ++ ++ mmc_ready = 1; ++ startBlock = find_mbr(mmc_csd.c_size); + ++ printf( "registering device: startBlock == %d, isSD ? %s\n", ++ startBlock, isSD ? "yes" : "no" ); + fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */ + + return rc; +@@ -503,4 +973,41 @@ + return 0; + } + ++#if (CONFIG_COMMANDS & CFG_CMD_MMC) ++ ++int do_mmc_detect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ++{ ++ unsigned long gplr1 = GPLR1 ; ++ int rval = ( 0 != (gplr1 & 0x10) ); ++#ifdef DEBUG ++ printf ("Checking for MMC card: %lx, %d\n", gplr1, rval ); ++#endif ++ return rval ; ++} ++ ++U_BOOT_CMD( ++ mmcdet, 1, 0, do_mmc_detect, ++ "mmcdet - detect mmc card\n", ++ NULL ++); ++ ++int do_mmc_wp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ++{ ++ unsigned long gplr1 = GPLR1 ; ++ int rval = ( 0 == (gplr1 & 0x40) ); ++#ifdef DEBUG ++ printf ("Checking MMC write protect: %lx, %d\n", gplr1, rval ); ++#endif ++ return rval ; ++} ++ ++U_BOOT_CMD( ++ mmcwp, 1, 0, do_mmc_wp, ++ "mmcwp - detect mmc write protect\n", ++ NULL ++); ++ ++#endif ++ + #endif ++ +diff -u -r --new-file u-boot-1.1.2/cpu/pxa/pxafb.c u-boot-1.1.2-neon/cpu/pxa/pxafb.c +--- u-boot-1.1.2/cpu/pxa/pxafb.c 2004-10-10 01:26:00.000000000 +0200 ++++ u-boot-1.1.2-neon/cpu/pxa/pxafb.c 2007-08-11 21:07:20.000000000 +0200 +@@ -36,6 +36,10 @@ + #include + #include + ++#ifdef CFG_CMD_LCDPANEL ++#include ++#endif ++ + /* #define DEBUG */ + + #ifdef CONFIG_LCD +@@ -147,6 +151,38 @@ + #endif /* CONFIG_HITACHI_SX14 */ + + /*----------------------------------------------------------------------*/ ++#ifdef CONFIG_SHARP_QVGA ++/* Sharp 1/4 VGA LCD */ ++#define LCD_BPP LCD_COLOR8 ++ ++/* you have to set lccr0 and lccr3 (including pcd) */ ++#define REG_LCCR0 0x003008F8 ++#define REG_LCCR3 (0x0040FF0C|(LCD_BPP<<24)) ++ ++vidinfo_t panel_info = { ++ vl_col: 320, ++ vl_row: 240, ++ vl_width: 167, ++ vl_height: 109, ++ vl_clkp: CFG_HIGH, ++ vl_oep: CFG_HIGH, ++ vl_hsp: CFG_HIGH, ++ vl_vsp: CFG_HIGH, ++ vl_dp: CFG_HIGH, ++ vl_bpix: LCD_BPP, ++ vl_lbw: 1, ++ vl_splt: 0, ++ vl_clor: 1, ++ vl_tft: 1, ++ vl_hpw: 64, ++ vl_blw: 34, ++ vl_elw: 1, ++ vl_vpw: 20, ++ vl_bfw: 8, ++ vl_efw: 3, ++}; ++#endif /* CONFIG_SHARP_QVGA */ ++ + + #if LCD_BPP == LCD_COLOR8 + void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue); +@@ -163,7 +199,6 @@ + void lcd_ctrl_init (void *lcdbase); + void lcd_enable (void); + +-int lcd_line_length; + int lcd_color_fg; + int lcd_color_bg; + +@@ -185,10 +220,28 @@ + + void lcd_ctrl_init (void *lcdbase) + { ++#ifdef CFG_CMD_LCDPANEL ++ char const *panelName = getenv( "panel" ); ++ if( panelName ) ++ { ++ struct lcd_panel_info_t const *panel ; ++ panel = find_lcd_panel( panelName ); ++ if( panel ) ++ { ++ printf( "panel %s found: %u x %u\n", panelName, panel->xres, panel->yres ); ++ panel_info.pxa.screen = (u_long)lcdbase; ++ set_lcd_panel( panel ); ++ } ++ else ++ printf( "panel %s not found\n", panelName ); ++ } ++#else + pxafb_init_mem(lcdbase, &panel_info); + pxafb_init(&panel_info); + pxafb_setup_gpio(&panel_info); + pxafb_enable_controller(&panel_info); ++#endif ++ + } + + /*----------------------------------------------------------------------*/ +@@ -204,6 +257,7 @@ + void + lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) + { ++#if defined( CONFIG_PXA250 ) + struct pxafb_info *fbi = &panel_info.pxa; + unsigned short *palette = (unsigned short *)fbi->palette; + u_int val; +@@ -219,7 +273,22 @@ + palette[regno] = val; + #endif + } ++#elif defined( CONFIG_PXA270 ) ++ struct pxafb_info *fbi = &panel_info.pxa; ++ u32 *palette = (u32 *)fbi->palette; ++ u32 val; ++ ++ if (regno < fbi->palette_size) { ++ val = 0xFF000000 ; // transparency ++ val |= (red << 16); ++ val |= (green << 8); ++ val |= blue ; + ++ palette[regno] = val; ++ } ++#else ++#error no processor defined ++#endif + debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n", + regno, &palette[regno], + red, green, blue, +@@ -284,7 +353,7 @@ + fbi->screen = (u_long)lcdbase; + + fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16; +- palette_mem_size = fbi->palette_size * sizeof(u16); ++ palette_mem_size = fbi->palette_size * sizeof(PALETTEVAL_TYPE); + + debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size); + /* locate palette and descs at end of page following fb */ +@@ -376,11 +445,16 @@ + static int pxafb_init (vidinfo_t *vid) + { + struct pxafb_info *fbi = &vid->pxa; ++ unsigned long const REG_LCCR3 = 0x0040FF0C|(LCD_BPP<<24); + + debug("Configuring PXA LCD\n"); + +- fbi->reg_lccr0 = REG_LCCR0; +- fbi->reg_lccr3 = REG_LCCR3; ++#if defined( CONFIG_PXA270 ) ++ LCCR4 = 0x00010000 ; ++#endif ++ ++ fbi->reg_lccr0 = 0x003008F8; ++ fbi->reg_lccr3 = REG_LCCR3 ; + + debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n", + vid->vl_col, vid->vl_hpw, +@@ -429,7 +503,7 @@ + + fbi->dmadesc_palette->fsadr = fbi->palette; + fbi->dmadesc_palette->fidr = 0; +- fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL; ++ fbi->dmadesc_palette->ldcmd = (fbi->palette_size * sizeof(PALETTEVAL_TYPE)) | LDCMD_PAL; + + if( NBITS(vid->vl_bpix) < 12) + { +@@ -465,6 +539,39 @@ + return 0; + } + ++ ++#ifdef CFG_CMD_LCDPANEL ++ ++void set_lcd_panel( struct lcd_panel_info_t const *panel ) ++{ ++ panel_info.vl_col = panel->xres ; ++ panel_info.vl_row = panel->yres ; ++ panel_info.vl_clkp = panel->act_high ; ++ panel_info.vl_oep = panel->act_high ; ++ panel_info.vl_hsp = panel->act_high ; ++ panel_info.vl_vsp = panel->act_high ; ++ panel_info.vl_dp = panel->act_high ; ++ panel_info.vl_bpix = LCD_BPP ; ++ panel_info.vl_lcd_line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) >> 3; ++ panel_info.vl_lbw = 1 ; ++ panel_info.vl_splt = 0 ; ++ panel_info.vl_clor = 1 ; ++ panel_info.vl_tft = panel->active ; ++ panel_info.vl_hpw = panel->hsync_len ; ++ panel_info.vl_blw = panel->left_margin ; ++ panel_info.vl_elw = panel->right_margin ; ++ panel_info.vl_vpw = panel->vsync_len ; ++ panel_info.vl_bfw = panel->upper_margin ; ++ panel_info.vl_efw = panel->lower_margin ; ++ ++ pxafb_init_mem( (void *)panel_info.pxa.screen, &panel_info); ++ pxafb_init(&panel_info); ++ pxafb_setup_gpio(&panel_info); ++ pxafb_enable_controller(&panel_info); ++} ++ ++#endif // dynamic LCD panel support ++ + /************************************************************************/ + /************************************************************************/ + +diff -u -r --new-file u-boot-1.1.2/cpu/pxa/sm501_usb.h u-boot-1.1.2-neon/cpu/pxa/sm501_usb.h +--- u-boot-1.1.2/cpu/pxa/sm501_usb.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/cpu/pxa/sm501_usb.h 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,66 @@ ++#ifndef SM501_USB_INCLUDED ++#define SM501_USB_INCLUDED ++ ++ #if defined(CONFIG_SM501) ++ #define USB_GATE_MODE0 __REG(0xFE00040) ++ #define USB_GATE_MODE1 __REG(0xFE00048) ++ #define ENABLE_USBH (1<<11) ++ ++ /* ++ * USB Host Controller ++ */ ++ #define USBH_BASE 0xFE40000 ++ #define UHCREV __REG(0xFE40000) ++ #define UHCHCON __REG(0xFE40004) ++ #define UHCCOMS __REG(0xFE40008) ++ #define UHCINTS __REG(0xFE4000C) ++ #define UHCINTE __REG(0xFE40010) ++ #define UHCINTD __REG(0xFE40014) ++ #define UHCHCCA __REG(0xFE40018) ++ #define UHCPCED __REG(0xFE4001C) ++ #define UHCCHED __REG(0xFE40020) ++ #define UHCCCED __REG(0xFE40024) ++ #define UHCBHED __REG(0xFE40028) ++ #define UHCBCED __REG(0xFE4002C) ++ #define UHCDHEAD __REG(0xFE40030) ++ #define UHCFMI __REG(0xFE40034) ++ #define UHCFMR __REG(0xFE40038) ++ #define UHCFMN __REG(0xFE4003C) ++ #define UHCPERS __REG(0xFE40040) ++ #define UHCLST __REG(0xFE40044) ++ #define UHCRHDA __REG(0xFE40048) ++ #define UHCRHDB __REG(0xFE4004C) ++ #define UHCRHS __REG(0xFE40050) ++ #define UHCRHPS1 __REG(0xFE40054) ++ #define UHCRHPS2 __REG(0xFE40058) ++ #define UHCRHPS3 __REG(0xFE4005C) ++ #define UHCSTAT __REG(0xFE40060) ++ #define UHCHR __REG(0xFE40064) ++ #define UHCHIE __REG(0xFE40068) ++ #define UHCHIT __REG(0xFE4006C) ++ ++ #define UHCHR_FSBIR (1<<0) ++ #define UHCHR_FHR (1<<1) ++ #define UHCHR_CGR (1<<2) ++ #define UHCHR_SSDC (1<<3) ++ #define UHCHR_UIT (1<<4) ++ #define UHCHR_SSE (1<<5) ++ #define UHCHR_PSPL (1<<6) ++ #define UHCHR_PCPL (1<<7) ++ #define UHCHR_SSEP0 (1<<9) ++ #define UHCHR_SSEP1 (1<<10) ++ #define UHCHR_SSEP2 (1<<11) ++ ++ #define UHCHIE_UPRIE (1<<13) ++ #define UHCHIE_UPS2IE (1<<12) ++ #define UHCHIE_UPS1IE (1<<11) ++ #define UHCHIE_TAIE (1<<10) ++ #define UHCHIE_HBAIE (1<<8) ++ #define UHCHIE_RWIE (1<<7) ++ ++ #define UHCCOMS_HCR 1 ++ #define UHCRHS_LPS 1 ++ #define UHCHR_SSE (1<<5) ++ ++ #endif ++#endif +diff -u -r --new-file u-boot-1.1.2/cpu/pxa/start.S u-boot-1.1.2-neon/cpu/pxa/start.S +--- u-boot-1.1.2/cpu/pxa/start.S 2004-06-09 02:11:02.000000000 +0200 ++++ u-boot-1.1.2-neon/cpu/pxa/start.S 2007-08-11 21:07:20.000000000 +0200 +@@ -61,23 +61,10 @@ + * - jump to second stage + */ + +-_TEXT_BASE: +- .word TEXT_BASE + +-.globl _armboot_start +-_armboot_start: +- .word _start ++_textBase: ++ .word TEXT_BASE + +-/* +- * These are defined in the board-specific linker script. +- */ +-.globl _bss_start +-_bss_start: +- .word __bss_start +- +-.globl _bss_end +-_bss_end: +- .word _end + + #ifdef CONFIG_USE_IRQ + /* IRQ stack memory (calculated at run-time) */ +@@ -111,47 +98,9 @@ + #ifdef CONFIG_INIT_CRITICAL + bl cpu_init_crit /* we do sys-critical inits */ + #endif ++ b HeadStart + +-relocate: /* relocate U-Boot to RAM */ +- adr r0, _start /* r0 <- current position of code */ +- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ +- cmp r0, r1 /* don't reloc during debug */ +- beq stack_setup +- +- ldr r2, _armboot_start +- ldr r3, _bss_start +- sub r2, r3, r2 /* r2 <- size of armboot */ +- add r2, r0, r2 /* r2 <- source end address */ +- +-copy_loop: +- ldmia r0!, {r3-r10} /* copy from source address [r0] */ +- stmia r1!, {r3-r10} /* copy to target address [r1] */ +- cmp r0, r2 /* until source end addreee [r2] */ +- ble copy_loop +- +- /* Set up the stack */ +-stack_setup: +- ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ +- sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ +- sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ +-#ifdef CONFIG_USE_IRQ +- sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) +-#endif +- sub sp, r0, #12 /* leave 3 words for abort-stack */ +- +-clear_bss: +- ldr r0, _bss_start /* find start of bss segment */ +- ldr r1, _bss_end /* stop here */ +- mov r2, #0x00000000 /* clear */ + +-clbss_l:str r2, [r0] /* clear loop... */ +- add r0, r0, #4 +- cmp r0, r1 +- bne clbss_l +- +- ldr pc, _start_armboot +- +-_start_armboot: .word start_armboot + + + /****************************************************************************/ +@@ -167,16 +116,7 @@ + IC_BASE: .word 0x40d00000 + #define ICMR 0x04 + +-/* Reset-Controller */ +-RST_BASE: .word 0x40f00030 +-#define RCSR 0x00 +- +-/* Operating System Timer */ +-OSTIMER_BASE: .word 0x40a00000 +-#define OSMR3 0x0C +-#define OSCR 0x10 +-#define OWER 0x18 +-#define OIER 0x1C ++ + + /* Clock Manager Registers */ + #ifdef CFG_CPUSPEED +@@ -288,7 +228,7 @@ + stmia sp, {r0 - r12} /* Calling r0-r12 */ + add r8, sp, #S_PC + +- ldr r2, _armboot_start ++ ldr r2, _textBase + sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ +@@ -325,7 +265,7 @@ + .endm + + .macro get_bad_stack +- ldr r13, _armboot_start @ setup our mode stack ++ ldr r13, _textBase @ setup our mode stack + sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) + sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + +@@ -416,36 +356,3 @@ + + #endif + +-/****************************************************************************/ +-/* */ +-/* Reset function: the PXA250 doesn't have a reset function, so we have to */ +-/* perform a watchdog timeout for a soft reset. */ +-/* */ +-/****************************************************************************/ +- +- .align 5 +-.globl reset_cpu +- +- /* FIXME: this code is PXA250 specific. How is this handled on */ +- /* other XScale processors? */ +- +-reset_cpu: +- +- /* We set OWE:WME (watchdog enable) and wait until timeout happens */ +- +- ldr r0, OSTIMER_BASE +- ldr r1, [r0, #OWER] +- orr r1, r1, #0x0001 /* bit0: WME */ +- str r1, [r0, #OWER] +- +- /* OS timer does only wrap every 1165 seconds, so we have to set */ +- /* the match register as well. */ +- +- ldr r1, [r0, #OSCR] /* read OS timer */ +- add r1, r1, #0x800 /* let OSMR3 match after */ +- add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */ +- str r1, [r0, #OSMR3] +- +-reset_endless: +- +- b reset_endless +diff -u -r --new-file u-boot-1.1.2/cpu/pxa/usb_ohci.c u-boot-1.1.2-neon/cpu/pxa/usb_ohci.c +--- u-boot-1.1.2/cpu/pxa/usb_ohci.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/cpu/pxa/usb_ohci.c 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,1679 @@ ++/* ++ * URB OHCI HCD (Host Controller Driver) for USB on the S3C2400. ++ * ++ * (C) Copyright 2003 ++ * Gary Jennejohn, DENX Software Engineering ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ * Note: Part of this code has been derived from linux ++ * ++ */ ++/* ++ * IMPORTANT NOTES ++ * 1 - you MUST define LITTLEENDIAN in the configuration file for the ++ * board or this driver will NOT work! ++ * 2 - this driver is intended for use with USB Mass Storage Devices ++ * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! ++ */ ++ ++#include ++/* #include no PCI on the S3C24X0 */ ++ ++#ifdef CONFIG_USB_OHCI ++ ++#include ++ ++#include ++#include ++#include "usb_ohci.h" ++ ++#if defined( CONFIG_SM501 ) ++#include "sm501_usb.h" ++#endif ++ ++// #define OHCI_USE_NPS /* force NoPowerSwitching mode */ ++// #define OHCI_VERBOSE_DEBUG /* not always helpful */ ++ ++ ++/* For initializing controller (mask in an HCFS mode too) */ ++#define OHCI_CONTROL_INIT \ ++ (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE ++ ++#define readl(a) (*((vu_long *)(a))) ++#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a)) ++ ++#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) ++ ++//#define DEBUG ++#ifdef DEBUG ++#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) ++#else ++#define dbg(format, arg...) do {} while(0) ++#endif /* DEBUG */ ++#define err(format, arg...) printf("ERROR: " format "\n", ## arg) ++#define SHOW_INFO ++#ifdef SHOW_INFO ++#define info(format, arg...) printf("INFO: " format "\n", ## arg) ++#else ++#define info(format, arg...) do {} while(0) ++#endif ++ ++#define m16_swap(x) swap_16(x) ++#define m32_swap(x) swap_32(x) ++ ++/* global ohci_t */ ++static ohci_t gohci; ++/* this must be aligned to a 256 byte boundary */ ++struct ohci_hcca ghcca[1]; ++/* a pointer to the aligned storage */ ++struct ohci_hcca *phcca; ++/* this allocates EDs for all possible endpoints */ ++struct ohci_device ohci_dev; ++/* urb_priv */ ++urb_priv_t urb_priv; ++/* RHSC flag */ ++int got_rhsc; ++/* device which was disconnected */ ++struct usb_device *devgone; ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* AMD-756 (D2 rev) reports corrupt register contents in some cases. ++ * The erratum (#4) description is incorrect. AMD's workaround waits ++ * till some bits (mostly reserved) are clear; ok for all revs. ++ */ ++#define OHCI_QUIRK_AMD756 0xabcd ++#define read_roothub(hc, register, mask) ({ \ ++ u32 temp = readl (&hc->regs->roothub.register); \ ++ if (hc->flags & OHCI_QUIRK_AMD756) \ ++ while (temp & mask) \ ++ temp = readl (&hc->regs->roothub.register); \ ++ temp; }) ++ ++static u32 roothub_a (struct ohci *hc) ++ { return read_roothub (hc, a, 0xfc0fe000); } ++static inline u32 roothub_b (struct ohci *hc) ++ { return readl (&hc->regs->roothub.b); } ++static inline u32 roothub_status (struct ohci *hc) ++ { return readl (&hc->regs->roothub.status); } ++static u32 roothub_portstatus (struct ohci *hc, int i) ++ { return read_roothub (hc, portstatus [i], 0xffe0fce0); } ++ ++ ++/* forward declaration */ ++static int hc_interrupt (void); ++static void ++td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer, ++ int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval); ++ ++/*-------------------------------------------------------------------------* ++ * URB support functions ++ *-------------------------------------------------------------------------*/ ++ ++/* free HCD-private data associated with this URB */ ++ ++static void urb_free_priv (urb_priv_t * urb) ++{ ++ int i; ++ int last; ++ struct td * td; ++ ++ last = urb->length - 1; ++ if (last >= 0) { ++ for (i = 0; i <= last; i++) { ++ td = urb->td[i]; ++ if (td) { ++ td->usb_dev = NULL; ++ urb->td[i] = NULL; ++ } ++ } ++ } ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++#ifdef DEBUG ++static int sohci_get_current_frame_number (struct usb_device * dev); ++ ++/* debug| print the main components of an URB ++ * small: 0) header + data packets 1) just header */ ++ ++static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer, ++ int transfer_len, struct devrequest * setup, char * str, int small) ++{ ++ urb_priv_t * purb = &urb_priv; ++ ++ dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", ++ str, ++ sohci_get_current_frame_number (dev), ++ usb_pipedevice (pipe), ++ usb_pipeendpoint (pipe), ++ usb_pipeout (pipe)? 'O': 'I', ++ usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): ++ (usb_pipecontrol (pipe)? "CTRL": "BULK"), ++ purb->actual_length, ++ transfer_len, dev->status); ++#ifdef OHCI_VERBOSE_DEBUG ++ if (!small) { ++ int i, len; ++ ++ if (usb_pipecontrol (pipe)) { ++ printf (__FILE__ ": cmd(8):"); ++ for (i = 0; i < 8 ; i++) ++ printf (" %02x", ((__u8 *) setup) [i]); ++ printf ("\n"); ++ } ++ if (transfer_len > 0 && buffer) { ++ printf (__FILE__ ": data(%d/%d):", ++ purb->actual_length, ++ transfer_len); ++ len = usb_pipeout (pipe)? ++ transfer_len: purb->actual_length; ++ for (i = 0; i < 16 && i < len; i++) ++ printf (" %02x", ((__u8 *) buffer) [i]); ++ printf ("%s\n", i < len? "...": ""); ++ } ++ } ++#endif ++} ++ ++/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ ++void ep_print_int_eds (ohci_t *ohci, char * str) { ++ int i, j; ++ __u32 * ed_p; ++ for (i= 0; i < 32; i++) { ++ j = 5; ++ ed_p = &(ohci->hcca->int_table [i]); ++ if (*ed_p == 0) ++ continue; ++ printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i); ++ while (*ed_p != 0 && j--) { ++ ed_t *ed = (ed_t *)m32_swap(ed_p); ++ printf (" ed: %4x;", ed->hwINFO); ++ ed_p = &ed->hwNextED; ++ } ++ printf ("\n"); ++ } ++} ++ ++static void ohci_dump_intr_mask (char *label, __u32 mask) ++{ ++ dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s", ++ label, ++ mask, ++ (mask & OHCI_INTR_MIE) ? " MIE" : "", ++ (mask & OHCI_INTR_OC) ? " OC" : "", ++ (mask & OHCI_INTR_RHSC) ? " RHSC" : "", ++ (mask & OHCI_INTR_FNO) ? " FNO" : "", ++ (mask & OHCI_INTR_UE) ? " UE" : "", ++ (mask & OHCI_INTR_RD) ? " RD" : "", ++ (mask & OHCI_INTR_SF) ? " SF" : "", ++ (mask & OHCI_INTR_WDH) ? " WDH" : "", ++ (mask & OHCI_INTR_SO) ? " SO" : "" ++ ); ++} ++ ++static void maybe_print_eds (char *label, __u32 value) ++{ ++ ed_t *edp = (ed_t *)value; ++ ++ if (value) { ++ dbg ("%s %08x", label, value); ++ dbg ("%08x", edp->hwINFO); ++ dbg ("%08x", edp->hwTailP); ++ dbg ("%08x", edp->hwHeadP); ++ dbg ("%08x", edp->hwNextED); ++ } ++} ++ ++static char * hcfs2string (int state) ++{ ++ switch (state) { ++ case OHCI_USB_RESET: return "reset"; ++ case OHCI_USB_RESUME: return "resume"; ++ case OHCI_USB_OPER: return "operational"; ++ case OHCI_USB_SUSPEND: return "suspend"; ++ } ++ return "?"; ++} ++ ++/* dump control and status registers */ ++static void ohci_dump_status (ohci_t *controller) ++{ ++ struct ohci_regs *regs = controller->regs; ++ __u32 temp; ++ ++ temp = readl (®s->revision) & 0xff; ++ if (temp != 0x10) ++ dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f)); ++ ++ temp = readl (®s->control); ++ dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, ++ (temp & OHCI_CTRL_RWE) ? " RWE" : "", ++ (temp & OHCI_CTRL_RWC) ? " RWC" : "", ++ (temp & OHCI_CTRL_IR) ? " IR" : "", ++ hcfs2string (temp & OHCI_CTRL_HCFS), ++ (temp & OHCI_CTRL_BLE) ? " BLE" : "", ++ (temp & OHCI_CTRL_CLE) ? " CLE" : "", ++ (temp & OHCI_CTRL_IE) ? " IE" : "", ++ (temp & OHCI_CTRL_PLE) ? " PLE" : "", ++ temp & OHCI_CTRL_CBSR ++ ); ++ ++ temp = readl (®s->cmdstatus); ++ dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, ++ (temp & OHCI_SOC) >> 16, ++ (temp & OHCI_OCR) ? " OCR" : "", ++ (temp & OHCI_BLF) ? " BLF" : "", ++ (temp & OHCI_CLF) ? " CLF" : "", ++ (temp & OHCI_HCR) ? " HCR" : "" ++ ); ++ ++ ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus)); ++ ohci_dump_intr_mask ("intrenable", readl (®s->intrenable)); ++ ++ maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent)); ++ ++ maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead)); ++ maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent)); ++ ++ maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead)); ++ maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent)); ++ ++ maybe_print_eds ("donehead", readl (®s->donehead)); ++} ++ ++static void ohci_dump_roothub (ohci_t *controller, int verbose) ++{ ++ __u32 temp, ndp, i; ++ ++ temp = roothub_a (controller); ++ ndp = (temp & RH_A_NDP); ++ ++ if (verbose) { ++ dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, ++ ((temp & RH_A_POTPGT) >> 24) & 0xff, ++ (temp & RH_A_NOCP) ? " NOCP" : "", ++ (temp & RH_A_OCPM) ? " OCPM" : "", ++ (temp & RH_A_DT) ? " DT" : "", ++ (temp & RH_A_NPS) ? " NPS" : "", ++ (temp & RH_A_PSM) ? " PSM" : "", ++ ndp ++ ); ++ temp = roothub_b (controller); ++ dbg ("roothub.b: %08x PPCM=%04x DR=%04x", ++ temp, ++ (temp & RH_B_PPCM) >> 16, ++ (temp & RH_B_DR) ++ ); ++ temp = roothub_status (controller); ++ dbg ("roothub.status: %08x%s%s%s%s%s%s", ++ temp, ++ (temp & RH_HS_CRWE) ? " CRWE" : "", ++ (temp & RH_HS_OCIC) ? " OCIC" : "", ++ (temp & RH_HS_LPSC) ? " LPSC" : "", ++ (temp & RH_HS_DRWE) ? " DRWE" : "", ++ (temp & RH_HS_OCI) ? " OCI" : "", ++ (temp & RH_HS_LPS) ? " LPS" : "" ++ ); ++ } ++ ++ for (i = 0; i < ndp; i++) { ++ temp = roothub_portstatus (controller, i); ++ dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", ++ i, ++ temp, ++ (temp & RH_PS_PRSC) ? " PRSC" : "", ++ (temp & RH_PS_OCIC) ? " OCIC" : "", ++ (temp & RH_PS_PSSC) ? " PSSC" : "", ++ (temp & RH_PS_PESC) ? " PESC" : "", ++ (temp & RH_PS_CSC) ? " CSC" : "", ++ ++ (temp & RH_PS_LSDA) ? " LSDA" : "", ++ (temp & RH_PS_PPS) ? " PPS" : "", ++ (temp & RH_PS_PRS) ? " PRS" : "", ++ (temp & RH_PS_POCI) ? " POCI" : "", ++ (temp & RH_PS_PSS) ? " PSS" : "", ++ ++ (temp & RH_PS_PES) ? " PES" : "", ++ (temp & RH_PS_CCS) ? " CCS" : "" ++ ); ++ } ++} ++ ++static void ohci_dump (ohci_t *controller, int verbose) ++{ ++ dbg ("OHCI controller usb-%s state", controller->slot_name); ++ ++ /* dumps some of the state we know about */ ++ ohci_dump_status (controller); ++ if (verbose) ++ ep_print_int_eds (controller, "hcca"); ++ dbg ("hcca frame #%04x", controller->hcca->frame_no); ++ ohci_dump_roothub (controller, 1); ++} ++ ++ ++#endif /* DEBUG */ ++ ++/*-------------------------------------------------------------------------* ++ * Interface functions (URB) ++ *-------------------------------------------------------------------------*/ ++ ++/* get a transfer request */ ++ ++int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, ++ int transfer_len, struct devrequest *setup, int interval) ++{ ++ ohci_t *ohci; ++ ed_t * ed; ++ urb_priv_t *purb_priv; ++ int i, size = 0; ++ ++ ohci = &gohci; ++ ++ /* when controller's hung, permit only roothub cleanup attempts ++ * such as powering down ports */ ++ if (ohci->disabled) { ++ err("sohci_submit_job: EPIPE"); ++ return -1; ++ } ++ ++ /* every endpoint has a ed, locate and fill it */ ++ if (!(ed = ep_add_ed (dev, pipe))) { ++ err("sohci_submit_job: ENOMEM"); ++ return -1; ++ } ++ ++ /* for the private part of the URB we need the number of TDs (size) */ ++ switch (usb_pipetype (pipe)) { ++ case PIPE_BULK: /* one TD for every 4096 Byte */ ++ size = (transfer_len - 1) / 4096 + 1; ++ break; ++ case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ ++ size = (transfer_len == 0)? 2: ++ (transfer_len - 1) / 4096 + 3; ++ break; ++ } ++ ++ if (size >= (N_URB_TD - 1)) { ++ err("need %d TDs, only have %d", size, N_URB_TD); ++ return -1; ++ } ++ purb_priv = &urb_priv; ++ purb_priv->pipe = pipe; ++ ++ /* fill the private part of the URB */ ++ purb_priv->length = size; ++ purb_priv->ed = ed; ++ purb_priv->actual_length = 0; ++ ++ /* allocate the TDs */ ++ /* note that td[0] was allocated in ep_add_ed */ ++ for (i = 0; i < size; i++) { ++ purb_priv->td[i] = td_alloc (dev); ++ if (!purb_priv->td[i]) { ++ purb_priv->length = i; ++ urb_free_priv (purb_priv); ++ err("sohci_submit_job: ENOMEM"); ++ return -1; ++ } ++ } ++ ++ if (ed->state == ED_NEW || (ed->state & ED_DEL)) { ++ urb_free_priv (purb_priv); ++ err("sohci_submit_job: EINVAL"); ++ return -1; ++ } ++ ++ /* link the ed into a chain if is not already */ ++ if (ed->state != ED_OPER) ++ ep_link (ohci, ed); ++ ++ /* fill the TDs and link it to the ed */ ++ td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); ++ ++ return 0; ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++#ifdef DEBUG ++/* tell us the current USB frame number */ ++ ++static int sohci_get_current_frame_number (struct usb_device *usb_dev) ++{ ++ ohci_t *ohci = &gohci; ++ ++ return m16_swap (ohci->hcca->frame_no); ++} ++#endif ++ ++/*-------------------------------------------------------------------------* ++ * ED handling functions ++ *-------------------------------------------------------------------------*/ ++ ++/* link an ed into one of the HC chains */ ++ ++static int ep_link (ohci_t *ohci, ed_t *edi) ++{ ++ volatile ed_t *ed = edi; ++ ++ ed->state = ED_OPER; ++ ++ switch (ed->type) { ++ case PIPE_CONTROL: ++ ed->hwNextED = 0; ++ if (ohci->ed_controltail == NULL) { ++ writel (ed, &ohci->regs->ed_controlhead); ++ } else { ++ ohci->ed_controltail->hwNextED = m32_swap (ed); ++ } ++ ed->ed_prev = ohci->ed_controltail; ++ if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && ++ !ohci->ed_rm_list[1] && !ohci->sleeping) { ++ ohci->hc_control |= OHCI_CTRL_CLE; ++ writel (ohci->hc_control, &ohci->regs->control); ++ } ++ ohci->ed_controltail = edi; ++ break; ++ ++ case PIPE_BULK: ++ ed->hwNextED = 0; ++ if (ohci->ed_bulktail == NULL) { ++ writel (ed, &ohci->regs->ed_bulkhead); ++ } else { ++ ohci->ed_bulktail->hwNextED = m32_swap (ed); ++ } ++ ed->ed_prev = ohci->ed_bulktail; ++ if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && ++ !ohci->ed_rm_list[1] && !ohci->sleeping) { ++ ohci->hc_control |= OHCI_CTRL_BLE; ++ writel (ohci->hc_control, &ohci->regs->control); ++ } ++ ohci->ed_bulktail = edi; ++ break; ++ } ++ return 0; ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* unlink an ed from one of the HC chains. ++ * just the link to the ed is unlinked. ++ * the link from the ed still points to another operational ed or 0 ++ * so the HC can eventually finish the processing of the unlinked ed */ ++ ++static int ep_unlink (ohci_t *ohci, ed_t *ed) ++{ ++ ed->hwINFO |= m32_swap (OHCI_ED_SKIP); ++ ++ switch (ed->type) { ++ case PIPE_CONTROL: ++ if (ed->ed_prev == NULL) { ++ if (!ed->hwNextED) { ++ ohci->hc_control &= ~OHCI_CTRL_CLE; ++ writel (ohci->hc_control, &ohci->regs->control); ++ } ++ writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); ++ } else { ++ ed->ed_prev->hwNextED = ed->hwNextED; ++ } ++ if (ohci->ed_controltail == ed) { ++ ohci->ed_controltail = ed->ed_prev; ++ } else { ++ ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; ++ } ++ break; ++ ++ case PIPE_BULK: ++ if (ed->ed_prev == NULL) { ++ if (!ed->hwNextED) { ++ ohci->hc_control &= ~OHCI_CTRL_BLE; ++ writel (ohci->hc_control, &ohci->regs->control); ++ } ++ writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); ++ } else { ++ ed->ed_prev->hwNextED = ed->hwNextED; ++ } ++ if (ohci->ed_bulktail == ed) { ++ ohci->ed_bulktail = ed->ed_prev; ++ } else { ++ ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; ++ } ++ break; ++ } ++ ed->state = ED_UNLINK; ++ return 0; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* add/reinit an endpoint; this should be done once at the usb_set_configuration command, ++ * but the USB stack is a little bit stateless so we do it at every transaction ++ * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK ++ * in all other cases the state is left unchanged ++ * the ed info fields are setted anyway even though most of them should not change */ ++ ++static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) ++{ ++ td_t *td; ++ ed_t *ed_ret; ++ volatile ed_t *ed; ++ ++ ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) | ++ (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]; ++ ++ if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { ++ err("ep_add_ed: pending delete"); ++ /* pending delete request */ ++ return NULL; ++ } ++ ++ if (ed->state == ED_NEW) { ++ ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */ ++ /* dummy td; end of td list for ed */ ++ td = td_alloc (usb_dev); ++ ed->hwTailP = m32_swap (td); ++ ed->hwHeadP = ed->hwTailP; ++ ed->state = ED_UNLINK; ++ ed->type = usb_pipetype (pipe); ++ ohci_dev.ed_cnt++; ++ } ++ ++ ed->hwINFO = m32_swap (usb_pipedevice (pipe) ++ | usb_pipeendpoint (pipe) << 7 ++ | (usb_pipeisoc (pipe)? 0x8000: 0) ++ | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) ++ | usb_pipeslow (pipe) << 13 ++ | usb_maxpacket (usb_dev, pipe) << 16); ++ ++ return ed_ret; ++} ++ ++/*-------------------------------------------------------------------------* ++ * TD handling functions ++ *-------------------------------------------------------------------------*/ ++ ++/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ ++ ++static void td_fill (ohci_t *ohci, unsigned int info, ++ void *data, int len, ++ struct usb_device *dev, int index, urb_priv_t *urb_priv) ++{ ++ volatile td_t *td, *td_pt; ++#ifdef OHCI_FILL_TRACE ++ int i; ++#endif ++ ++ if (index > urb_priv->length) { ++ err("index > length"); ++ return; ++ } ++ /* use this td as the next dummy */ ++ td_pt = urb_priv->td [index]; ++ td_pt->hwNextTD = 0; ++ ++ /* fill the old dummy TD */ ++ td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf); ++ ++ td->ed = urb_priv->ed; ++ td->next_dl_td = NULL; ++ td->index = index; ++ td->data = (__u32)data; ++#ifdef OHCI_FILL_TRACE ++ if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) { ++ for (i = 0; i < len; i++) ++ printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]); ++ printf("\n"); ++ } ++#endif ++ if (!len) ++ data = 0; ++ ++ td->hwINFO = m32_swap (info); ++ td->hwCBP = m32_swap (data); ++ if (data) ++ td->hwBE = m32_swap (data + len - 1); ++ else ++ td->hwBE = 0; ++ td->hwNextTD = m32_swap (td_pt); ++ td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000); ++ ++ /* append to queue */ ++ td->ed->hwTailP = td->hwNextTD; ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* prepare all TDs of a transfer */ ++ ++static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer, ++ int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) ++{ ++ ohci_t *ohci = &gohci; ++ int data_len = transfer_len; ++ void *data; ++ int cnt = 0; ++ __u32 info = 0; ++ unsigned int toggle = 0; ++ ++ /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */ ++ if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { ++ toggle = TD_T_TOGGLE; ++ } else { ++ toggle = TD_T_DATA0; ++ usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); ++ } ++ urb->td_cnt = 0; ++ if (data_len) ++ data = buffer; ++ else ++ data = 0; ++ ++ switch (usb_pipetype (pipe)) { ++ case PIPE_BULK: ++ info = usb_pipeout (pipe)? ++ TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; ++ while(data_len > 4096) { ++ td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb); ++ data += 4096; data_len -= 4096; cnt++; ++ } ++ info = usb_pipeout (pipe)? ++ TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; ++ td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); ++ cnt++; ++ ++ if (!ohci->sleeping) ++ writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ ++ break; ++ ++ case PIPE_CONTROL: ++ info = TD_CC | TD_DP_SETUP | TD_T_DATA0; ++ td_fill (ohci, info, setup, 8, dev, cnt++, urb); ++ if (data_len > 0) { ++ info = usb_pipeout (pipe)? ++ TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; ++ /* NOTE: mishandles transfers >8K, some >4K */ ++ td_fill (ohci, info, data, data_len, dev, cnt++, urb); ++ } ++ info = usb_pipeout (pipe)? ++ TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; ++ td_fill (ohci, info, data, 0, dev, cnt++, urb); ++ if (!ohci->sleeping) ++ writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ ++ break; ++ } ++ if (urb->length != cnt) ++ dbg("TD LENGTH %d != CNT %d", urb->length, cnt); ++} ++ ++/*-------------------------------------------------------------------------* ++ * Done List handling functions ++ *-------------------------------------------------------------------------*/ ++ ++ ++/* calculate the transfer length and update the urb */ ++ ++static void dl_transfer_length(td_t * td) ++{ ++ __u32 tdINFO, tdBE, tdCBP; ++ urb_priv_t *lurb_priv = &urb_priv; ++ ++ tdINFO = m32_swap (td->hwINFO); ++ tdBE = m32_swap (td->hwBE); ++ tdCBP = m32_swap (td->hwCBP); ++ ++ ++ if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL && ++ ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { ++ if (tdBE != 0) { ++ if (td->hwCBP == 0) ++ lurb_priv->actual_length += tdBE - td->data + 1; ++ else ++ lurb_priv->actual_length += tdCBP - td->data; ++ } ++ } ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* replies to the request have to be on a FIFO basis so ++ * we reverse the reversed done-list */ ++ ++static td_t * dl_reverse_done_list (ohci_t *ohci) ++{ ++ __u32 td_list_hc; ++ td_t *td_rev = NULL; ++ td_t *td_list = NULL; ++ urb_priv_t *lurb_priv = NULL; ++ ++ td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0; ++ ohci->hcca->done_head = 0; ++ ++ while (td_list_hc) { ++ td_list = (td_t *)td_list_hc; ++ ++ if (TD_CC_GET (m32_swap (td_list->hwINFO))) { ++ lurb_priv = &urb_priv; ++ dbg(" USB-error/status: %x : %p", ++ TD_CC_GET (m32_swap (td_list->hwINFO)), td_list); ++ if (td_list->ed->hwHeadP & m32_swap (0x1)) { ++ if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) { ++ td_list->ed->hwHeadP = ++ (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) | ++ (td_list->ed->hwHeadP & m32_swap (0x2)); ++ lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1; ++ } else ++ td_list->ed->hwHeadP &= m32_swap (0xfffffff2); ++ } ++ } ++ ++ td_list->next_dl_td = td_rev; ++ td_rev = td_list; ++ td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0; ++ } ++ return td_list; ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* td done list */ ++static int dl_done_list (ohci_t *ohci, td_t *td_list) ++{ ++ td_t *td_list_next = NULL; ++ ed_t *ed; ++ int cc = 0; ++ int stat = 0; ++ /* urb_t *urb; */ ++ urb_priv_t *lurb_priv; ++ __u32 tdINFO, edHeadP, edTailP; ++ ++ while (td_list) { ++ td_list_next = td_list->next_dl_td; ++ ++ lurb_priv = &urb_priv; ++ tdINFO = m32_swap (td_list->hwINFO); ++ ++ ed = td_list->ed; ++ ++ dl_transfer_length(td_list); ++ ++ /* error code of transfer */ ++ cc = TD_CC_GET (tdINFO); ++ if (cc != 0) { ++ dbg("ConditionCode %#x", cc); ++ stat = cc_to_error[cc]; ++ } ++ ++ if (ed->state != ED_NEW) { ++ edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0; ++ edTailP = m32_swap (ed->hwTailP); ++ ++ /* unlink eds if they are not busy */ ++ if ((edHeadP == edTailP) && (ed->state == ED_OPER)) ++ ep_unlink (ohci, ed); ++ } ++ ++ td_list = td_list_next; ++ } ++ return stat; ++} ++ ++/*-------------------------------------------------------------------------* ++ * Virtual Root Hub ++ *-------------------------------------------------------------------------*/ ++ ++/* Device descriptor */ ++static __u8 root_hub_dev_des[] = ++{ ++ 0x12, /* __u8 bLength; */ ++ 0x01, /* __u8 bDescriptorType; Device */ ++ 0x10, /* __u16 bcdUSB; v1.1 */ ++ 0x01, ++ 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ ++ 0x00, /* __u8 bDeviceSubClass; */ ++ 0x00, /* __u8 bDeviceProtocol; */ ++ 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ ++ 0x00, /* __u16 idVendor; */ ++ 0x00, ++ 0x00, /* __u16 idProduct; */ ++ 0x00, ++ 0x00, /* __u16 bcdDevice; */ ++ 0x00, ++ 0x00, /* __u8 iManufacturer; */ ++ 0x01, /* __u8 iProduct; */ ++ 0x00, /* __u8 iSerialNumber; */ ++ 0x01 /* __u8 bNumConfigurations; */ ++}; ++ ++ ++/* Configuration descriptor */ ++static __u8 root_hub_config_des[] = ++{ ++ 0x09, /* __u8 bLength; */ ++ 0x02, /* __u8 bDescriptorType; Configuration */ ++ 0x19, /* __u16 wTotalLength; */ ++ 0x00, ++ 0x01, /* __u8 bNumInterfaces; */ ++ 0x01, /* __u8 bConfigurationValue; */ ++ 0x00, /* __u8 iConfiguration; */ ++ 0x40, /* __u8 bmAttributes; ++ Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ ++ 0x00, /* __u8 MaxPower; */ ++ ++ /* interface */ ++ 0x09, /* __u8 if_bLength; */ ++ 0x04, /* __u8 if_bDescriptorType; Interface */ ++ 0x00, /* __u8 if_bInterfaceNumber; */ ++ 0x00, /* __u8 if_bAlternateSetting; */ ++ 0x01, /* __u8 if_bNumEndpoints; */ ++ 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ ++ 0x00, /* __u8 if_bInterfaceSubClass; */ ++ 0x00, /* __u8 if_bInterfaceProtocol; */ ++ 0x00, /* __u8 if_iInterface; */ ++ ++ /* endpoint */ ++ 0x07, /* __u8 ep_bLength; */ ++ 0x05, /* __u8 ep_bDescriptorType; Endpoint */ ++ 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ ++ 0x03, /* __u8 ep_bmAttributes; Interrupt */ ++ 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ ++ 0x00, ++ 0xff /* __u8 ep_bInterval; 255 ms */ ++}; ++ ++static unsigned char root_hub_str_index0[] = ++{ ++ 0x04, /* __u8 bLength; */ ++ 0x03, /* __u8 bDescriptorType; String-descriptor */ ++ 0x09, /* __u8 lang ID */ ++ 0x04, /* __u8 lang ID */ ++}; ++ ++static unsigned char root_hub_str_index1[] = ++{ ++ 28, /* __u8 bLength; */ ++ 0x03, /* __u8 bDescriptorType; String-descriptor */ ++ 'O', /* __u8 Unicode */ ++ 0, /* __u8 Unicode */ ++ 'H', /* __u8 Unicode */ ++ 0, /* __u8 Unicode */ ++ 'C', /* __u8 Unicode */ ++ 0, /* __u8 Unicode */ ++ 'I', /* __u8 Unicode */ ++ 0, /* __u8 Unicode */ ++ ' ', /* __u8 Unicode */ ++ 0, /* __u8 Unicode */ ++ 'R', /* __u8 Unicode */ ++ 0, /* __u8 Unicode */ ++ 'o', /* __u8 Unicode */ ++ 0, /* __u8 Unicode */ ++ 'o', /* __u8 Unicode */ ++ 0, /* __u8 Unicode */ ++ 't', /* __u8 Unicode */ ++ 0, /* __u8 Unicode */ ++ ' ', /* __u8 Unicode */ ++ 0, /* __u8 Unicode */ ++ 'H', /* __u8 Unicode */ ++ 0, /* __u8 Unicode */ ++ 'u', /* __u8 Unicode */ ++ 0, /* __u8 Unicode */ ++ 'b', /* __u8 Unicode */ ++ 0, /* __u8 Unicode */ ++}; ++ ++/* Hub class-specific descriptor is constructed dynamically */ ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++#define OK(x) len = (x); break ++#ifdef DEBUG ++#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} ++#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} ++#else ++#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) ++#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) ++#endif ++#define RD_RH_STAT roothub_status(&gohci) ++#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) ++ ++/* request to virtual root hub */ ++ ++int rh_check_port_status(ohci_t *controller) ++{ ++ __u32 temp, ndp, i; ++ int res; ++ ++ res = -1; ++ temp = roothub_a (controller); ++ ndp = (temp & RH_A_NDP); ++ for (i = 0; i < ndp; i++) { ++ temp = roothub_portstatus (controller, i); ++ /* check for a device disconnect */ ++ if (((temp & (RH_PS_PESC | RH_PS_CSC)) == ++ (RH_PS_PESC | RH_PS_CSC)) && ++ ((temp & RH_PS_CCS) == 0)) { ++ res = i; ++ break; ++ } ++ } ++ return res; ++} ++ ++static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, ++ void *buffer, int transfer_len, struct devrequest *cmd) ++{ ++ void * data = buffer; ++ int leni = transfer_len; ++ int len = 0; ++ int stat = 0; ++ __u32 datab[4]; ++ __u8 *data_buf = (__u8 *)datab; ++ __u16 bmRType_bReq; ++ __u16 wValue; ++ __u16 wIndex; ++ __u16 wLength; ++ ++#ifdef DEBUG ++urb_priv.actual_length = 0; ++pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); ++#else ++ wait_ms(1); ++#endif ++ if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { ++ info("Root-Hub submit IRQ: NOT implemented"); ++ return 0; ++ } ++ ++ bmRType_bReq = cmd->requesttype | (cmd->request << 8); ++ wValue = m16_swap (cmd->value); ++ wIndex = m16_swap (cmd->index); ++ wLength = m16_swap (cmd->length); ++ ++ info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", ++ dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); ++ ++ switch (bmRType_bReq) { ++ /* Request Destination: ++ without flags: Device, ++ RH_INTERFACE: interface, ++ RH_ENDPOINT: endpoint, ++ RH_CLASS means HUB here, ++ RH_OTHER | RH_CLASS almost ever means HUB_PORT here ++ */ ++ ++ case RH_GET_STATUS: ++ *(__u16 *) data_buf = m16_swap (1); OK (2); ++ case RH_GET_STATUS | RH_INTERFACE: ++ *(__u16 *) data_buf = m16_swap (0); OK (2); ++ case RH_GET_STATUS | RH_ENDPOINT: ++ *(__u16 *) data_buf = m16_swap (0); OK (2); ++ case RH_GET_STATUS | RH_CLASS: ++ *(__u32 *) data_buf = m32_swap ( ++ RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); ++ OK (4); ++ case RH_GET_STATUS | RH_OTHER | RH_CLASS: ++ *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4); ++ ++ case RH_CLEAR_FEATURE | RH_ENDPOINT: ++ switch (wValue) { ++ case (RH_ENDPOINT_STALL): OK (0); ++ } ++ break; ++ ++ case RH_CLEAR_FEATURE | RH_CLASS: ++ switch (wValue) { ++ case RH_C_HUB_LOCAL_POWER: ++ OK(0); ++ case (RH_C_HUB_OVER_CURRENT): ++ WR_RH_STAT(RH_HS_OCIC); OK (0); ++ } ++ break; ++ ++ case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: ++ switch (wValue) { ++ case (RH_PORT_ENABLE): ++ WR_RH_PORTSTAT (RH_PS_CCS ); OK (0); ++ case (RH_PORT_SUSPEND): ++ WR_RH_PORTSTAT (RH_PS_POCI); OK (0); ++ case (RH_PORT_POWER): ++ WR_RH_PORTSTAT (RH_PS_LSDA); OK (0); ++ case (RH_C_PORT_CONNECTION): ++ WR_RH_PORTSTAT (RH_PS_CSC ); OK (0); ++ case (RH_C_PORT_ENABLE): ++ WR_RH_PORTSTAT (RH_PS_PESC); OK (0); ++ case (RH_C_PORT_SUSPEND): ++ WR_RH_PORTSTAT (RH_PS_PSSC); OK (0); ++ case (RH_C_PORT_OVER_CURRENT): ++ WR_RH_PORTSTAT (RH_PS_OCIC); OK (0); ++ case (RH_C_PORT_RESET): ++ WR_RH_PORTSTAT (RH_PS_PRSC); OK (0); ++ } ++ break; ++ ++ case RH_SET_FEATURE | RH_OTHER | RH_CLASS: ++ switch (wValue) { ++ case (RH_PORT_SUSPEND): ++ WR_RH_PORTSTAT (RH_PS_PSS ); OK (0); ++ case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ ++ if (RD_RH_PORTSTAT & RH_PS_CCS) ++ WR_RH_PORTSTAT (RH_PS_PRS); ++ OK (0); ++ case (RH_PORT_POWER): ++ WR_RH_PORTSTAT (RH_PS_PPS ); OK (0); ++ case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ ++ if (RD_RH_PORTSTAT & RH_PS_CCS) ++ WR_RH_PORTSTAT (RH_PS_PES ); ++ OK (0); ++ } ++ break; ++ ++ case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0); ++ ++ case RH_GET_DESCRIPTOR: ++ switch ((wValue & 0xff00) >> 8) { ++ case (0x01): /* device descriptor */ ++ len = min_t(unsigned int, ++ leni, ++ min_t(unsigned int, ++ sizeof (root_hub_dev_des), ++ wLength)); ++ data_buf = root_hub_dev_des; OK(len); ++ case (0x02): /* configuration descriptor */ ++ len = min_t(unsigned int, ++ leni, ++ min_t(unsigned int, ++ sizeof (root_hub_config_des), ++ wLength)); ++ data_buf = root_hub_config_des; OK(len); ++ case (0x03): /* string descriptors */ ++ if(wValue==0x0300) { ++ len = min_t(unsigned int, ++ leni, ++ min_t(unsigned int, ++ sizeof (root_hub_str_index0), ++ wLength)); ++ data_buf = root_hub_str_index0; ++ OK(len); ++ } ++ if(wValue==0x0301) { ++ len = min_t(unsigned int, ++ leni, ++ min_t(unsigned int, ++ sizeof (root_hub_str_index1), ++ wLength)); ++ data_buf = root_hub_str_index1; ++ OK(len); ++ } ++ default: ++ stat = USB_ST_STALLED; ++ } ++ break; ++ ++ case RH_GET_DESCRIPTOR | RH_CLASS: ++ { ++ __u32 temp = roothub_a (&gohci); ++ ++ data_buf [0] = 9; /* min length; */ ++ data_buf [1] = 0x29; ++ data_buf [2] = temp & RH_A_NDP; ++ data_buf [3] = 0; ++ if (temp & RH_A_PSM) /* per-port power switching? */ ++ data_buf [3] |= 0x1; ++ if (temp & RH_A_NOCP) /* no overcurrent reporting? */ ++ data_buf [3] |= 0x10; ++ else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ ++ data_buf [3] |= 0x8; ++ ++ /* corresponds to data_buf[4-7] */ ++ datab [1] = 0; ++ data_buf [5] = (temp & RH_A_POTPGT) >> 24; ++ temp = roothub_b (&gohci); ++ data_buf [7] = temp & RH_B_DR; ++ if (data_buf [2] < 7) { ++ data_buf [8] = 0xff; ++ } else { ++ data_buf [0] += 2; ++ data_buf [8] = (temp & RH_B_DR) >> 8; ++ data_buf [10] = data_buf [9] = 0xff; ++ } ++ ++ len = min_t(unsigned int, leni, ++ min_t(unsigned int, data_buf [0], wLength)); ++ OK (len); ++ } ++ ++ case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); ++ ++ case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); ++ ++ default: ++ dbg ("unsupported root hub command"); ++ stat = USB_ST_STALLED; ++ } ++ ++#ifdef DEBUG ++ ohci_dump_roothub (&gohci, 1); ++#else ++ wait_ms(1); ++#endif ++ ++ len = min_t(int, len, leni); ++ if (data != data_buf) ++ memcpy (data, data_buf, len); ++ dev->act_len = len; ++ dev->status = stat; ++ ++#ifdef DEBUG ++ if (transfer_len) ++ urb_priv.actual_length = transfer_len; ++ pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); ++#else ++ wait_ms(1); ++#endif ++ ++ return stat; ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* common code for handling submit messages - used for all but root hub */ ++/* accesses. */ ++int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, ++ int transfer_len, struct devrequest *setup, int interval) ++{ ++ int stat = 0; ++ int maxsize = usb_maxpacket(dev, pipe); ++ int timeout; ++ ++ /* device pulled? Shortcut the action. */ ++ if (devgone == dev) { ++ dev->status = USB_ST_CRC_ERR; ++ return 0; ++ } ++ ++#ifdef DEBUG ++ urb_priv.actual_length = 0; ++ pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); ++#else ++ wait_ms(1); ++#endif ++ if (!maxsize) { ++ err("submit_common_message: pipesize for pipe %lx is zero", ++ pipe); ++ return -1; ++ } ++ ++ if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) { ++ err("sohci_submit_job failed"); ++ return -1; ++ } ++ ++ wait_ms(10); ++ /* ohci_dump_status(&gohci); */ ++ ++ /* allow more time for a BULK device to react - some are slow */ ++#define BULK_TO 5000 /* timeout in milliseconds */ ++ if (usb_pipetype (pipe) == PIPE_BULK) ++ timeout = BULK_TO; ++ else ++ timeout = 100; ++ ++ /* wait for it to complete */ ++ for (;;) { ++ /* check whether the controller is done */ ++ stat = hc_interrupt(); ++ if (stat < 0) { ++ stat = USB_ST_CRC_ERR; ++ break; ++ } ++ if (stat >= 0 && stat != 0xff) { ++ /* 0xff is returned for an SF-interrupt */ ++ break; ++ } ++ if (--timeout) { ++ wait_ms(1); ++ } else { ++ err("CTL:TIMEOUT "); ++ stat = USB_ST_CRC_ERR; ++ break; ++ } ++ } ++ /* we got an Root Hub Status Change interrupt */ ++ if (got_rhsc) { ++#ifdef DEBUG ++ ohci_dump_roothub (&gohci, 1); ++#endif ++ got_rhsc = 0; ++ /* abuse timeout */ ++ timeout = rh_check_port_status(&gohci); ++ if (timeout >= 0) { ++#if 0 /* this does nothing useful, but leave it here in case that changes */ ++ /* the called routine adds 1 to the passed value */ ++ usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); ++#endif ++ /* ++ * XXX ++ * This is potentially dangerous because it assumes ++ * that only one device is ever plugged in! ++ */ ++ devgone = dev; ++ } ++ } ++ ++ dev->status = stat; ++ dev->act_len = transfer_len; ++ ++#ifdef DEBUG ++ pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); ++#else ++ wait_ms(1); ++#endif ++ ++ /* free TDs in urb_priv */ ++ urb_free_priv (&urb_priv); ++ return 0; ++} ++ ++/* submit routines called from usb.c */ ++int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, ++ int transfer_len) ++{ ++ info("submit_bulk_msg"); ++ return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); ++} ++ ++int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, ++ int transfer_len, struct devrequest *setup) ++{ ++ int maxsize = usb_maxpacket(dev, pipe); ++ ++ info("submit_control_msg"); ++#ifdef DEBUG ++ urb_priv.actual_length = 0; ++ pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); ++#else ++ wait_ms(1); ++#endif ++ if (!maxsize) { ++ err("submit_control_message: pipesize for pipe %lx is zero", ++ pipe); ++ return -1; ++ } ++ if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { ++ gohci.rh.dev = dev; ++ /* root hub - redirect */ ++ return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, ++ setup); ++ } ++ ++ return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); ++} ++ ++int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, ++ int transfer_len, int interval) ++{ ++ info("submit_int_msg"); ++ return -1; ++} ++ ++/*-------------------------------------------------------------------------* ++ * HC functions ++ *-------------------------------------------------------------------------*/ ++ ++/* reset the HC and BUS */ ++ ++static int hc_reset (ohci_t *ohci) ++{ ++ int timeout = 30; ++ int smm_timeout = 50; /* 0,5 sec */ ++ ++ if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ ++ writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ ++ info("USB HC TakeOver from SMM"); ++ while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { ++ wait_ms (10); ++ if (--smm_timeout == 0) { ++ err("USB HC TakeOver failed!"); ++ return -1; ++ } ++ } ++ } ++ ++ /* Disable HC interrupts */ ++ writel (OHCI_INTR_MIE, &ohci->regs->intrdisable); ++ ++ dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;", ++ ohci->slot_name, ++ readl (&ohci->regs->control)); ++ ++ /* Reset USB (needed by some controllers) */ ++ writel (0, &ohci->regs->control); ++ ++ /* HC Reset requires max 10 us delay */ ++ writel (OHCI_HCR, &ohci->regs->cmdstatus); ++ while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { ++ if (--timeout == 0) { ++ err("USB HC reset timed out!"); ++ return -1; ++ } ++ udelay (1); ++ } ++ return 0; ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* Start an OHCI controller, set the BUS operational ++ * enable interrupts ++ * connect the virtual root hub */ ++ ++static int hc_start (ohci_t * ohci) ++{ ++ __u32 mask; ++ unsigned int fminterval; ++ ++ ohci->disabled = 1; ++ ++ /* Tell the controller where the control and bulk lists are ++ * The lists are empty now. */ ++ ++ writel (0, &ohci->regs->ed_controlhead); ++ writel (0, &ohci->regs->ed_bulkhead); ++ ++ writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ ++ ++ fminterval = 0x2edf; ++ writel ((fminterval * 9) / 10, &ohci->regs->periodicstart); ++ fminterval |= ((((fminterval - 210) * 6) / 7) << 16); ++ writel (fminterval, &ohci->regs->fminterval); ++ writel (0x628, &ohci->regs->lsthresh); ++ ++ /* start controller operations */ ++ ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; ++ ohci->disabled = 0; ++ writel (ohci->hc_control, &ohci->regs->control); ++ ++ /* disable all interrupts */ ++ mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | ++ OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | ++ OHCI_INTR_OC | OHCI_INTR_MIE); ++ writel (mask, &ohci->regs->intrdisable); ++ /* clear all interrupts */ ++ mask &= ~OHCI_INTR_MIE; ++ writel (mask, &ohci->regs->intrstatus); ++ /* Choose the interrupts we care about now - but w/o MIE */ ++ mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; ++ writel (mask, &ohci->regs->intrenable); ++ ++#ifdef OHCI_USE_NPS ++ /* required for AMD-756 and some Mac platforms */ ++ writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM, ++ &ohci->regs->roothub.a); ++ writel (RH_HS_LPSC, &ohci->regs->roothub.status); ++#endif /* OHCI_USE_NPS */ ++ ++#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);}) ++ /* POTPGT delay is bits 24-31, in 2 ms units. */ ++ mdelay ((roothub_a (ohci) >> 23) & 0x1fe); ++ ++ /* connect the virtual root hub */ ++ ohci->rh.devnum = 0; ++ ++printf( "---> Done with hc_start\n" ); ++ ++ return 0; ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* an interrupt happens */ ++ ++static int ++hc_interrupt (void) ++{ ++ ohci_t *ohci = &gohci; ++ struct ohci_regs *regs = ohci->regs; ++ int ints; ++ int stat = -1; ++ ++ if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) { ++ ints = OHCI_INTR_WDH; ++ } else { ++ ints = readl (®s->intrstatus); ++ } ++ ++dbg("Interrupt: %x frame: %x", ints, ohci->hcca->frame_no); ++ ++ if (ints & OHCI_INTR_RHSC) { ++dbg("rhsc\n" ); ++ got_rhsc = 1; ++ } ++ ++ if (ints & OHCI_INTR_UE) { ++ ohci->disabled++; ++ err ("OHCI Unrecoverable Error, controller usb-%s disabled", ++ ohci->slot_name); ++ /* e.g. due to PCI Master/Target Abort */ ++ ++#ifdef DEBUG ++ ohci_dump (ohci, 1); ++#else ++ wait_ms(1); ++#endif ++ /* FIXME: be optimistic, hope that bug won't repeat often. */ ++ /* Make some non-interrupt context restart the controller. */ ++ /* Count and limit the retries though; either hardware or */ ++ /* software errors can go forever... */ ++ hc_reset (ohci); ++ return -1; ++ } ++ ++ if (ints & OHCI_INTR_WDH) { ++ wait_ms(1); ++ writel (OHCI_INTR_WDH, ®s->intrdisable); ++ stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); ++ writel (OHCI_INTR_WDH, ®s->intrenable); ++dbg("wdh: %x\n", stat ); ++ goto out ; ++ } ++ ++ if (ints & OHCI_INTR_SO) { ++ dbg("USB Schedule overrun\n"); ++ writel (OHCI_INTR_SO, ®s->intrenable); ++ stat = -1; ++ } ++ ++ /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ ++ if (ints & OHCI_INTR_SF) { ++ unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1; ++ wait_ms(1); ++ writel (OHCI_INTR_SF, ®s->intrdisable); ++ if (ohci->ed_rm_list[frame] != NULL) ++ writel (OHCI_INTR_SF, ®s->intrenable); ++ if( -1 == stat ) ++ stat = 0xff; ++dbg("sf\n" ); ++ } ++ if( 0 == ints ) ++ stat = 0 ; ++out: ++ writel (ints, ®s->intrstatus); ++ return stat; ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* De-allocate all resources.. */ ++ ++static void hc_release_ohci (ohci_t *ohci) ++{ ++ dbg ("USB HC release ohci usb-%s", ohci->slot_name); ++ ++ if (!ohci->disabled) ++ hc_reset (ohci); ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* ++ * low level initalisation routine, called from usb.c ++ */ ++static char ohci_inited = 0; ++ ++int usb_lowlevel_init(void) ++{ ++#ifdef FIXME ++ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ /* ++ * Set the 48 MHz UPLL clocking. Values are taken from ++ * "PLL value selection guide", 6-23, s3c2400_UM.pdf. ++ */ ++ clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2); ++ gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */ ++ /* ++ * Enable USB host clock. ++ */ ++ clk_power->CLKCON |= (1 << 4); ++#endif ++#ifdef CONFIG_PXA27X ++ /* ++ * Section 20.6.1 of PXA Developer's reference manual ++ */ ++ GPCR3 |= 0x80 ; // GP103 low ++ ++ UHCHR |= UHCHR_SSEP2|UHCHR_SSEP1 ; // Port 2 and 3 not supported ++ UHCHR &= ~(UHCHR_SSE|UHCHR_SSEP0); ++ ++// UHCRHS &= ~UHCRHS_LPS ; ++// UHCCOMS &= ~UHCCOMS_HCR ; // reset ++ CKEN |= CKEN10_USBHOST ; ++ udelay(10); ++ UHCHR &= ~(UHCHR_FHR|UHCHR_SSE); ++#elif defined( CONFIG_SM501 ) ++ USB_GATE_MODE0 |= ENABLE_USBH ; ++ USB_GATE_MODE1 |= ENABLE_USBH ; ++#endif ++ ++ memset (&gohci, 0, sizeof (ohci_t)); ++ memset (&urb_priv, 0, sizeof (urb_priv_t)); ++ ++ /* align the storage */ ++ if ((__u32)&ghcca[0] & 0xff) { ++ err("HCCA not aligned!!"); ++ return -1; ++ } ++ phcca = &ghcca[0]; ++ info("aligned ghcca %p", phcca); ++ memset(&ohci_dev, 0, sizeof(struct ohci_device)); ++ if ((__u32)&ohci_dev.ed[0] & 0x7) { ++ err("EDs not aligned!!"); ++ return -1; ++ } ++ memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); ++ if ((__u32)gtd & 0x7) { ++ err("TDs not aligned!!"); ++ return -1; ++ } ++ ptd = gtd; ++ gohci.hcca = phcca; ++ memset (phcca, 0, sizeof (struct ohci_hcca)); ++ ++ gohci.disabled = 1; ++ gohci.sleeping = 0; ++ gohci.irq = -1; ++ gohci.regs = (struct ohci_regs *)USBH_BASE ; ++ gohci.flags = 0; ++ gohci.slot_name = "s3c2400"; ++ ++ if (hc_reset (&gohci) < 0) { ++ err( "----> Error from hc_reset\n" ); ++ hc_release_ohci (&gohci); ++ /* Initialization failed */ ++#ifdef FIXME ++ clk_power->CLKCON &= ~(1 << 4); ++#endif ++#ifdef CONFIG_PXA27X ++ CKEN &= ~CKEN10_USBHOST ; ++#elif defined( CONFIG_SM501 ) ++#endif ++ return -1; ++ } ++ ++ /* FIXME this is a second HC reset; why?? */ ++ writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control); ++ wait_ms (10); ++ ++ if (hc_start (&gohci) < 0) { ++ err ("can't start usb-%s", gohci.slot_name); ++ hc_release_ohci (&gohci); ++ /* Initialization failed */ ++#ifdef FIXME ++ clk_power->CLKCON &= ~(1 << 4); ++#endif ++#ifdef CONFIG_PXA27X ++ CKEN &= ~CKEN10_USBHOST ; ++#elif defined( CONFIG_SM501 ) ++#endif ++ return -1; ++ } ++ ++#ifdef DEBUG ++ ohci_dump (&gohci, 1); ++#else ++ wait_ms(1); ++#endif ++printf( "----> end of low_level_init()\n" ); ++ ohci_inited = 1; ++ return 0; ++} ++ ++int usb_lowlevel_stop(void) ++{ ++ /* this gets called really early - before the controller has */ ++ /* even been initialized! */ ++ if (!ohci_inited) ++ return 0; ++ /* TODO release any interrupts, etc. */ ++ /* call hc_release_ohci() here ? */ ++ hc_reset (&gohci); ++ ++#ifdef CONFIG_PXA27X ++ /* ++ * Section 20.7.4.4 of PXA Developer's reference manual ++ */ ++ UHCCOMS |= UHCCOMS_HCR ; // reset ++ udelay(10); ++ UHCRHS |= UHCRHS_LPS ; ++ UHCHR |= UHCHR_SSE ; ++ CKEN &= ~CKEN10_USBHOST ; ++#elif defined( CONFIG_SM501 ) ++#endif ++ ++ return 0; ++} ++ ++#endif /* CONFIG_USB_OHCI */ +diff -u -r --new-file u-boot-1.1.2/cpu/pxa/usb_ohci.h u-boot-1.1.2-neon/cpu/pxa/usb_ohci.h +--- u-boot-1.1.2/cpu/pxa/usb_ohci.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/cpu/pxa/usb_ohci.h 2007-08-11 21:07:20.000000000 +0200 +@@ -0,0 +1,419 @@ ++/* ++ * URB OHCI HCD (Host Controller Driver) for USB. ++ * ++ * (C) Copyright 1999 Roman Weissgaerber ++ * (C) Copyright 2000-2001 David Brownell ++ * ++ * usb-ohci.h ++ */ ++ ++ ++static int cc_to_error[16] = { ++ ++/* mapping of the OHCI CC status to error codes */ ++ /* No Error */ 0, ++ /* CRC Error */ USB_ST_CRC_ERR, ++ /* Bit Stuff */ USB_ST_BIT_ERR, ++ /* Data Togg */ USB_ST_CRC_ERR, ++ /* Stall */ USB_ST_STALLED, ++ /* DevNotResp */ -1, ++ /* PIDCheck */ USB_ST_BIT_ERR, ++ /* UnExpPID */ USB_ST_BIT_ERR, ++ /* DataOver */ USB_ST_BUF_ERR, ++ /* DataUnder */ USB_ST_BUF_ERR, ++ /* reservd */ -1, ++ /* reservd */ -1, ++ /* BufferOver */ USB_ST_BUF_ERR, ++ /* BuffUnder */ USB_ST_BUF_ERR, ++ /* Not Access */ -1, ++ /* Not Access */ -1 ++}; ++ ++/* ED States */ ++ ++#define ED_NEW 0x00 ++#define ED_UNLINK 0x01 ++#define ED_OPER 0x02 ++#define ED_DEL 0x04 ++#define ED_URB_DEL 0x08 ++ ++/* usb_ohci_ed */ ++struct ed { ++ __u32 hwINFO; ++ __u32 hwTailP; ++ __u32 hwHeadP; ++ __u32 hwNextED; ++ ++ struct ed *ed_prev; ++ __u8 int_period; ++ __u8 int_branch; ++ __u8 int_load; ++ __u8 int_interval; ++ __u8 state; ++ __u8 type; ++ __u16 last_iso; ++ struct ed *ed_rm_list; ++ ++ struct usb_device *usb_dev; ++ __u32 unused[3]; ++} __attribute((aligned(16))); ++typedef struct ed ed_t; ++ ++ ++/* TD info field */ ++#define TD_CC 0xf0000000 ++#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) ++#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) ++#define TD_EC 0x0C000000 ++#define TD_T 0x03000000 ++#define TD_T_DATA0 0x02000000 ++#define TD_T_DATA1 0x03000000 ++#define TD_T_TOGGLE 0x00000000 ++#define TD_R 0x00040000 ++#define TD_DI 0x00E00000 ++#define TD_DI_SET(X) (((X) & 0x07)<< 21) ++#define TD_DP 0x00180000 ++#define TD_DP_SETUP 0x00000000 ++#define TD_DP_IN 0x00100000 ++#define TD_DP_OUT 0x00080000 ++ ++#define TD_ISO 0x00010000 ++#define TD_DEL 0x00020000 ++ ++/* CC Codes */ ++#define TD_CC_NOERROR 0x00 ++#define TD_CC_CRC 0x01 ++#define TD_CC_BITSTUFFING 0x02 ++#define TD_CC_DATATOGGLEM 0x03 ++#define TD_CC_STALL 0x04 ++#define TD_DEVNOTRESP 0x05 ++#define TD_PIDCHECKFAIL 0x06 ++#define TD_UNEXPECTEDPID 0x07 ++#define TD_DATAOVERRUN 0x08 ++#define TD_DATAUNDERRUN 0x09 ++#define TD_BUFFEROVERRUN 0x0C ++#define TD_BUFFERUNDERRUN 0x0D ++#define TD_NOTACCESSED 0x0F ++ ++ ++#define MAXPSW 1 ++ ++struct td { ++ __u32 hwINFO; ++ __u32 hwCBP; /* Current Buffer Pointer */ ++ __u32 hwNextTD; /* Next TD Pointer */ ++ __u32 hwBE; /* Memory Buffer End Pointer */ ++ ++ __u16 hwPSW[MAXPSW]; ++ __u8 unused; ++ __u8 index; ++ struct ed *ed; ++ struct td *next_dl_td; ++ struct usb_device *usb_dev; ++ int transfer_len; ++ __u32 data; ++ ++ __u32 unused2[2]; ++} __attribute((aligned(32))); ++typedef struct td td_t; ++ ++#define OHCI_ED_SKIP (1 << 14) ++ ++/* ++ * The HCCA (Host Controller Communications Area) is a 256 byte ++ * structure defined in the OHCI spec. that the host controller is ++ * told the base address of. It must be 256-byte aligned. ++ */ ++ ++#define NUM_INTS 32 /* part of the OHCI standard */ ++struct ohci_hcca { ++ __u32 int_table[NUM_INTS]; /* Interrupt ED table */ ++ __u16 frame_no; /* current frame number */ ++ __u16 pad1; /* set to 0 on each frame_no change */ ++ __u32 done_head; /* info returned for an interrupt */ ++ u8 reserved_for_hc[116]; ++} __attribute((aligned(256))); ++ ++ ++/* ++ * Maximum number of root hub ports. ++ */ ++#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ ++ ++/* ++ * This is the structure of the OHCI controller's memory mapped I/O ++ * region. This is Memory Mapped I/O. You must use the readl() and ++ * writel() macros defined in asm/io.h to access these!! ++ */ ++struct ohci_regs { ++ /* control and status registers */ ++ __u32 revision; ++ __u32 control; ++ __u32 cmdstatus; ++ __u32 intrstatus; ++ __u32 intrenable; ++ __u32 intrdisable; ++ /* memory pointers */ ++ __u32 hcca; ++ __u32 ed_periodcurrent; ++ __u32 ed_controlhead; ++ __u32 ed_controlcurrent; ++ __u32 ed_bulkhead; ++ __u32 ed_bulkcurrent; ++ __u32 donehead; ++ /* frame counters */ ++ __u32 fminterval; ++ __u32 fmremaining; ++ __u32 fmnumber; ++ __u32 periodicstart; ++ __u32 lsthresh; ++ /* Root hub ports */ ++ struct ohci_roothub_regs { ++ __u32 a; ++ __u32 b; ++ __u32 status; ++ __u32 portstatus[MAX_ROOT_PORTS]; ++ } roothub; ++} __attribute((aligned(32))); ++ ++ ++/* OHCI CONTROL AND STATUS REGISTER MASKS */ ++ ++/* ++ * HcControl (control) register masks ++ */ ++#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ ++#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ ++#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ ++#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ ++#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ ++#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ ++#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ ++#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ ++#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ ++ ++/* pre-shifted values for HCFS */ ++# define OHCI_USB_RESET (0 << 6) ++# define OHCI_USB_RESUME (1 << 6) ++# define OHCI_USB_OPER (2 << 6) ++# define OHCI_USB_SUSPEND (3 << 6) ++ ++/* ++ * HcCommandStatus (cmdstatus) register masks ++ */ ++#define OHCI_HCR (1 << 0) /* host controller reset */ ++#define OHCI_CLF (1 << 1) /* control list filled */ ++#define OHCI_BLF (1 << 2) /* bulk list filled */ ++#define OHCI_OCR (1 << 3) /* ownership change request */ ++#define OHCI_SOC (3 << 16) /* scheduling overrun count */ ++ ++/* ++ * masks used with interrupt registers: ++ * HcInterruptStatus (intrstatus) ++ * HcInterruptEnable (intrenable) ++ * HcInterruptDisable (intrdisable) ++ */ ++#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ ++#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ ++#define OHCI_INTR_SF (1 << 2) /* start frame */ ++#define OHCI_INTR_RD (1 << 3) /* resume detect */ ++#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ ++#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ ++#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ ++#define OHCI_INTR_OC (1 << 30) /* ownership change */ ++#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ ++ ++ ++/* Virtual Root HUB */ ++struct virt_root_hub { ++ int devnum; /* Address of Root Hub endpoint */ ++ void *dev; /* was urb */ ++ void *int_addr; ++ int send; ++ int interval; ++}; ++ ++/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ ++ ++/* destination of request */ ++#define RH_INTERFACE 0x01 ++#define RH_ENDPOINT 0x02 ++#define RH_OTHER 0x03 ++ ++#define RH_CLASS 0x20 ++#define RH_VENDOR 0x40 ++ ++/* Requests: bRequest << 8 | bmRequestType */ ++#define RH_GET_STATUS 0x0080 ++#define RH_CLEAR_FEATURE 0x0100 ++#define RH_SET_FEATURE 0x0300 ++#define RH_SET_ADDRESS 0x0500 ++#define RH_GET_DESCRIPTOR 0x0680 ++#define RH_SET_DESCRIPTOR 0x0700 ++#define RH_GET_CONFIGURATION 0x0880 ++#define RH_SET_CONFIGURATION 0x0900 ++#define RH_GET_STATE 0x0280 ++#define RH_GET_INTERFACE 0x0A80 ++#define RH_SET_INTERFACE 0x0B00 ++#define RH_SYNC_FRAME 0x0C80 ++/* Our Vendor Specific Request */ ++#define RH_SET_EP 0x2000 ++ ++ ++/* Hub port features */ ++#define RH_PORT_CONNECTION 0x00 ++#define RH_PORT_ENABLE 0x01 ++#define RH_PORT_SUSPEND 0x02 ++#define RH_PORT_OVER_CURRENT 0x03 ++#define RH_PORT_RESET 0x04 ++#define RH_PORT_POWER 0x08 ++#define RH_PORT_LOW_SPEED 0x09 ++ ++#define RH_C_PORT_CONNECTION 0x10 ++#define RH_C_PORT_ENABLE 0x11 ++#define RH_C_PORT_SUSPEND 0x12 ++#define RH_C_PORT_OVER_CURRENT 0x13 ++#define RH_C_PORT_RESET 0x14 ++ ++/* Hub features */ ++#define RH_C_HUB_LOCAL_POWER 0x00 ++#define RH_C_HUB_OVER_CURRENT 0x01 ++ ++#define RH_DEVICE_REMOTE_WAKEUP 0x00 ++#define RH_ENDPOINT_STALL 0x01 ++ ++#define RH_ACK 0x01 ++#define RH_REQ_ERR -1 ++#define RH_NACK 0x00 ++ ++ ++/* OHCI ROOT HUB REGISTER MASKS */ ++ ++/* roothub.portstatus [i] bits */ ++#define RH_PS_CCS 0x00000001 /* current connect status */ ++#define RH_PS_PES 0x00000002 /* port enable status*/ ++#define RH_PS_PSS 0x00000004 /* port suspend status */ ++#define RH_PS_POCI 0x00000008 /* port over current indicator */ ++#define RH_PS_PRS 0x00000010 /* port reset status */ ++#define RH_PS_PPS 0x00000100 /* port power status */ ++#define RH_PS_LSDA 0x00000200 /* low speed device attached */ ++#define RH_PS_CSC 0x00010000 /* connect status change */ ++#define RH_PS_PESC 0x00020000 /* port enable status change */ ++#define RH_PS_PSSC 0x00040000 /* port suspend status change */ ++#define RH_PS_OCIC 0x00080000 /* over current indicator change */ ++#define RH_PS_PRSC 0x00100000 /* port reset status change */ ++ ++/* roothub.status bits */ ++#define RH_HS_LPS 0x00000001 /* local power status */ ++#define RH_HS_OCI 0x00000002 /* over current indicator */ ++#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ ++#define RH_HS_LPSC 0x00010000 /* local power status change */ ++#define RH_HS_OCIC 0x00020000 /* over current indicator change */ ++#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ ++ ++/* roothub.b masks */ ++#define RH_B_DR 0x0000ffff /* device removable flags */ ++#define RH_B_PPCM 0xffff0000 /* port power control mask */ ++ ++/* roothub.a masks */ ++#define RH_A_NDP (0xff << 0) /* number of downstream ports */ ++#define RH_A_PSM (1 << 8) /* power switching mode */ ++#define RH_A_NPS (1 << 9) /* no power switching */ ++#define RH_A_DT (1 << 10) /* device type (mbz) */ ++#define RH_A_OCPM (1 << 11) /* over current protection mode */ ++#define RH_A_NOCP (1 << 12) /* no over current protection */ ++#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ ++ ++/* urb */ ++#define N_URB_TD 48 ++typedef struct ++{ ++ ed_t *ed; ++ __u16 length; /* number of tds associated with this request */ ++ __u16 td_cnt; /* number of tds already serviced */ ++ int state; ++ unsigned long pipe; ++ int actual_length; ++ td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ ++} urb_priv_t; ++#define URB_DEL 1 ++ ++/* ++ * This is the full ohci controller description ++ * ++ * Note how the "proper" USB information is just ++ * a subset of what the full implementation needs. (Linus) ++ */ ++ ++ ++typedef struct ohci { ++ struct ohci_hcca *hcca; /* hcca */ ++ /*dma_addr_t hcca_dma;*/ ++ ++ int irq; ++ int disabled; /* e.g. got a UE, we're hung */ ++ int sleeping; ++ unsigned long flags; /* for HC bugs */ ++ ++ struct ohci_regs *regs; /* OHCI controller's memory */ ++ ++ ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ ++ ed_t *ed_bulktail; /* last endpoint of bulk list */ ++ ed_t *ed_controltail; /* last endpoint of control list */ ++ int intrstatus; ++ __u32 hc_control; /* copy of the hc control reg */ ++ struct usb_device *dev[32]; ++ struct virt_root_hub rh; ++ ++ const char *slot_name; ++} ohci_t; ++ ++#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ ++ ++struct ohci_device { ++ ed_t ed[NUM_EDS]; ++ int ed_cnt; ++}; ++ ++/* hcd */ ++/* endpoint */ ++static int ep_link(ohci_t * ohci, ed_t * ed); ++static int ep_unlink(ohci_t * ohci, ed_t * ed); ++static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* we need more TDs than EDs */ ++#define NUM_TD 64 ++ ++/* +1 so we can align the storage */ ++td_t gtd[NUM_TD+1]; ++/* pointers to aligned storage */ ++td_t *ptd; ++ ++/* TDs ... */ ++static inline struct td * ++td_alloc (struct usb_device *usb_dev) ++{ ++ int i; ++ struct td *td; ++ ++ td = NULL; ++ for (i = 0; i < NUM_TD; i++) ++ { ++ if (ptd[i].usb_dev == NULL) ++ { ++ td = &ptd[i]; ++ td->usb_dev = usb_dev; ++ break; ++ } ++ } ++ ++ return td; ++} ++ ++static inline void ++ed_free (struct ed *ed) ++{ ++ ed->usb_dev = NULL; ++} +diff -u -r --new-file u-boot-1.1.2/.cvsignore u-boot-1.1.2-neon/.cvsignore +--- u-boot-1.1.2/.cvsignore 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/.cvsignore 2007-08-11 21:07:19.000000000 +0200 +@@ -0,0 +1,13 @@ ++*.map ++*.scr ++*.gz ++select.h ++*.log ++select.mk ++u-boot ++u-boot.bin ++u-boot.map ++u-boot.map.sorted ++u-boot.srec ++u-boot-binaries.zip ++ +diff -u -r --new-file u-boot-1.1.2/drivers/lan91c96.h u-boot-1.1.2-neon/drivers/lan91c96.h +--- u-boot-1.1.2/drivers/lan91c96.h 2004-06-07 00:11:41.000000000 +0200 ++++ u-boot-1.1.2-neon/drivers/lan91c96.h 2007-08-11 21:07:21.000000000 +0200 +@@ -76,7 +76,7 @@ + + #define SMC_IO_EXTENT 16 + +-#ifdef CONFIG_PXA250 ++#if defined( CONFIG_PXA250 ) || defined( CONFIG_PXA270 ) + + #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+( r * 4 )))) + #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+( r * 4 )))) +@@ -139,7 +139,7 @@ + }; \ + }) + +-#else /* if not CONFIG_PXA250 */ ++#else /* if not CONFIG_PXA250 or CONFIG_PXA270 */ + + /* + * We have only 16 Bit PCMCIA access on Socket 0 +diff -u -r --new-file u-boot-1.1.2/drivers/smc91111.c u-boot-1.1.2-neon/drivers/smc91111.c +--- u-boot-1.1.2/drivers/smc91111.c 2004-11-22 23:20:09.000000000 +0100 ++++ u-boot-1.1.2-neon/drivers/smc91111.c 2007-08-11 21:07:21.000000000 +0200 +@@ -1583,6 +1583,101 @@ + return (0); + } + ++#define SMC_GET_INT_MASK() (SMC_inw( SMC91111_INT_REG ) >> 8) ++#define SMC_SET_INT_MASK(x) SMC_outw( (x) << 8, SMC91111_INT_REG ) ++#define SMC_CURRENT_BANK() SMC_inw( BANK_SELECT ) ++#define SMC_GET_CTL() SMC_inw( CTL_REG ) ++#define SMC_SET_CTL(x) SMC_outw( x, CTL_REG ) ++#define SMC_GET_MII() SMC_inw( MII_REG ) ++#define SMC_SET_MII(x) SMC_outw( x, MII_REG ) ++#define SMC_GET_PTR() SMC_inw( PTR_REG ) ++#define SMC_SET_PTR(x) SMC_outw( x, PTR_REG ) ++ ++static int writeEEprom(int i,unsigned short val,unsigned short ctl) ++{ ++ SMC_SELECT_BANK( 2 ); ++ SMC_SET_PTR( i ); ++ SMC_SELECT_BANK( 1 ); ++ SMC_outw( val, GP_REG ); ++ udelay(1); ++ SMC_SET_CTL( ctl | CTL_EEPROM_SELECT | CTL_STORE ); ++ int j=0; ++ do { ++ udelay(10); ++ j++; ++ if (j>=100000) return -1; ++ } while (SMC_GET_CTL() & CTL_STORE); ++ return 0; ++} ++ ++#define SMC_SET_MAC_ADDR(addr) \ ++ do { \ ++ SMC_outw( addr[0]|(addr[1] << 8), ADDR0_REG ); \ ++ SMC_outw( addr[2]|(addr[3] << 8), ADDR1_REG ); \ ++ SMC_outw( addr[4]|(addr[5] << 8), ADDR2_REG ); \ ++ } while (0) ++ ++int set_rom_mac (char const *mac) ++{ ++ unsigned short saved_bank = SMC_CURRENT_BANK(); ++ SMC_SELECT_BANK( 2 ); ++ ++ unsigned short saved_mask = SMC_GET_INT_MASK(); ++ SMC_SET_INT_MASK( 0 ); ++ ++ unsigned short saved_ptr = SMC_GET_PTR(); ++ ++ SMC_SELECT_BANK( 1 ); ++ ++ unsigned short saved_ctl = SMC_GET_CTL(); ++ ++ SMC_SET_MAC_ADDR(mac); ++ ++ SMC_SELECT_BANK( 3 ); ++ unsigned short mii_reg = SMC_GET_MII(); ++ ++ SMC_SET_MII(mii_reg & ~(0x0f)); ++ ++ SMC_SELECT_BANK( 1 ); ++ ++ SMC_SET_CTL( saved_ctl | CTL_EEPROM_SELECT ); ++ unsigned short cfg = CONFIG_DEFAULT ++ | CONFIG_NO_WAIT ++ | CONFIG_EPH_POWER_EN; ++ unsigned short bar = (unsigned short)( SMC_BASE_ADDRESS ); ++//a4, a10,a11,a12 must be all zeros ++ bar = (bar & 0xe000) | ((bar & 0x3e0)<<3) | (0x27); ++ int i=0; ++ while (i < 0x20) { ++ if (writeEEprom(i,cfg,saved_ctl)) break; ++ if (writeEEprom(i+1,bar,saved_ctl)) break; ++ if (writeEEprom(i+2,0,saved_ctl)) break; ++ if (writeEEprom(i+3,0,saved_ctl)) break; ++ i+=4; ++ } ++ ++ int j = 0; ++ if (i==0x20) { ++ while (j < 6) { ++ if (writeEEprom(i,mac[j]|(mac[j+1]<<8),saved_ctl)) break; ++ i++; j+=2; ++ } ++ } ++ ++ SMC_SET_CTL( saved_ctl ); ++ ++ SMC_SELECT_BANK( 2 ); ++ SMC_SET_PTR( saved_ptr ); ++ SMC_SET_INT_MASK( saved_mask ); ++ SMC_SELECT_BANK( saved_bank ); ++ ++ return 6 == j ; ++} ++ ++static char const invalidMac[6] = { ++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ++}; ++ + int get_rom_mac (char *v_rom_mac) + { + #ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */ +@@ -1601,6 +1696,9 @@ + valid_mac |= v_rom_mac[i]; + } + ++ if( valid_mac ) ++ valid_mac = ( 0 != memcmp( invalidMac, v_rom_mac, sizeof(invalidMac) ) ); ++ + return (valid_mac ? 1 : 0); + #endif + } +diff -u -r --new-file u-boot-1.1.2/drivers/smc91111.h u-boot-1.1.2-neon/drivers/smc91111.h +--- u-boot-1.1.2/drivers/smc91111.h 2004-11-02 14:00:56.000000000 +0100 ++++ u-boot-1.1.2-neon/drivers/smc91111.h 2007-08-11 21:07:21.000000000 +0200 +@@ -74,7 +74,7 @@ + + #define SMC_IO_EXTENT 16 + +-#ifdef CONFIG_PXA250 ++#if defined( CONFIG_PXA250 ) || defined( CONFIG_PXA270 ) + + #ifdef CONFIG_XSENGINE + #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1)))) +@@ -176,7 +176,7 @@ + }; \ + }) + +-#else /* if not CONFIG_PXA250 */ ++#else /* if not CONFIG_PXA250 or CONFIG_PXA270 */ + + #ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */ + /* +diff -u -r --new-file u-boot-1.1.2/examples/Makefile u-boot-1.1.2-neon/examples/Makefile +--- u-boot-1.1.2/examples/Makefile 2004-10-10 23:27:33.000000000 +0200 ++++ u-boot-1.1.2-neon/examples/Makefile 2007-08-11 21:07:21.000000000 +0200 +@@ -100,12 +100,12 @@ + LIBCOBJS= stubs.o + LIBOBJS = $(LIBAOBJS) $(LIBCOBJS) + +-gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) +-clibdir := $(shell dirname `$(CC) $(CFLAGS) -print-file-name=libc.a`) ++gcclibdir := $(shell dirname "`$(CC) -print-libgcc-file-name`") ++clibdir := $(shell dirname "`$(CC) $(CFLAGS) -print-file-name=libc.a`") + + CPPFLAGS += -I.. + +-all: .depend $(LIB) $(SREC) $(BIN) ++all: .depend $(LIB) + + ######################################################################### + $(LIB): .depend $(LIBOBJS) +diff -u -r --new-file u-boot-1.1.2/fs/fat/fat.c u-boot-1.1.2-neon/fs/fat/fat.c +--- u-boot-1.1.2/fs/fat/fat.c 2004-12-16 18:57:26.000000000 +0100 ++++ u-boot-1.1.2-neon/fs/fat/fat.c 2007-08-11 21:07:21.000000000 +0200 +@@ -52,6 +52,8 @@ + #define DOS_PART_TBL_OFFSET 0x1be + #define DOS_PART_MAGIC_OFFSET 0x1fe + #define DOS_FS_TYPE_OFFSET 0x36 ++#define DOS_FS_TYPE_OFFSET_FAT_16 0x36 // Code relating to this constant was changed/added by Dubner 2005-05-20 ++#define DOS_FS_TYPE_OFFSET_FAT_32 0x52 // Code relating to this constant was changed/added by Dubner 2005-05-20 + + int disk_read (__u32 startblock, __u32 getsize, __u8 * bufptr) + { +@@ -83,7 +85,8 @@ + /* no signature found */ + return -1; + } +- if(!strncmp(&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) { ++ if(!strncmp(&buffer[DOS_FS_TYPE_OFFSET_FAT_16],"FAT",3) ++ || !strncmp (&buffer[DOS_FS_TYPE_OFFSET_FAT_32], "FAT", 3)) { + /* ok, we assume we are on a PBR only */ + cur_part = 1; + part_offset=0; +@@ -342,7 +345,7 @@ + newclust = get_fatent(mydata, endclust); + if((newclust -1)!=endclust) + goto getit; +- if (newclust <= 0x0001 || newclust >= 0xfff0) { ++ if (newclust <= 0x0001 ) { // || newclust >= 0xfff0) { + FAT_DPRINT("curclust: 0x%x\n", newclust); + FAT_DPRINT("Invalid FAT entry\n"); + return gotsize; +@@ -890,7 +893,7 @@ + dentptr++; + continue; + } +- if (strcmp (fnamecopy, s_name) && strcmp (fnamecopy, l_name)) { ++ if (fnmatch(fnamecopy, s_name,0) && fnmatch(fnamecopy, l_name,0)) { + FAT_DPRINT ("RootMismatch: |%s|%s|\n", s_name, l_name); + dentptr++; + continue; +diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/BigMacro.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/BigMacro.h +--- u-boot-1.1.2/include/asm-arm/arch-pxa/BigMacro.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/BigMacro.h 2007-08-11 21:07:21.000000000 +0200 +@@ -0,0 +1,325 @@ ++// ++// linux/include/asm-arm/BigMacro.h ++// ++// Author: Troy Kisky ++// Created: Jun 30, 2002 ++// Copyright: Boundary Devices ++// ++// This program is free software; you can redistribute it and/or modify ++// it under the terms of the GNU General Public License version 2 as ++// published by the Free Software Foundation. ++// ++ .nolist ++ ++//find set bit pair >= curbit ++//out: __nBit ++ .ifdef __ARMASM ++ GBLA __nBit ++ GBLA __nMask ++ GBLA __nVal ++; DCD __nV1 ++ ++.macro NextSetBitUp val,curBit ++ LCLA __nV1 ++ .set __nBit,(\curBit) ++ .set __nV1,(\val) ++ WHILE ( (__nBit < 30) :LAND: ( (__nV1 :AND: (0x03:SHL:__nBit))=0) ) ++ .set __nBit,(__nBit)+2 ++ WEND ++.endm ++ ++//find set bit pair <= curbit ++//out: __nBit ++.macro NextSetBitDown val,curBit ++ LCLA __nV1 ++ .set __nBit,(\curBit) ++ .set __nV1,(\val) ++ WHILE ( (__nBit <> 0) :LAND: ( (__nV1:AND:(0xc0:SHL:__nBit))=0) ) ++ .set __nBit,(__nBit)-2 ++ WEND ++.endm ++ .else ++ ++.macro NextSetBitUp val,curBit ++ .set __nBit,(\curBit) ++ .set __nV1,(\val) ++ .if ((__nV1) & (0x03<<(__nBit))) ++ .else ++ .if ((__nBit)-30) ++ NextSetBitUp __nV1,((__nBit)+2) ++ .endif ++ .endif ++ .set __nV1,0 ++.endm ++ ++//find set bit pair <= curbit ++//out: __nBit ++.macro NextSetBitDown val,curBit ++ .set __nBit,(\curBit) ++ .set __nV1,(\val) ++ .if ((__nV1)&(0xc0<<(__nBit))) ++ .else ++ .if (__nBit) ++ NextSetBitDown __nV1,((__nBit)-2) ++ .endif ++ .endif ++ .set __nV1,0 ++.endm ++ .endif ++ ++//OUT: __nMask ++.macro NextSetMask val ++ NextSetBitDown \val,24 ++ .if (__nBit>=20) ++ NextSetBitUp \val,__nBit ++ .set __nMask,(0xff<<((__nBit)-16)) ++ .set __nMask,(((__nMask)>>16)+(((__nMask)<<16)&0xffff0000)) ++ .else ++ .set __nMask,(0xff<<(__nBit)) ++ .endif ++ ++.endm ++ ++.macro Big2CC inst,dest,val ++ .set __nVal,(\val) ++ .if (__nVal)<>0 ++ NextSetMask __nVal ++ \inst \dest,\dest,#(__nVal)&(__nMask) ++ Big2CC \inst,\dest,(__nVal)&~(__nMask) ++ .endif ++.endm ++ ++.macro BigAnd2CC cc,dest,val ++ .set __nVal,(\val) ++ .if (~__nVal)<>0 ++ NextSetMask __nVal ++ .if (((__nVal)&~(__nMask))=0) ++ and\cc \dest,\dest,#(__nVal)&(__nMask) ++ .else ++ Big2CC bic\cc,\dest,~__nVal ++ .endif ++ .endif ++.endm ++ ++/////////////////////////////////////////////////////// ++.macro BigMovCC cc,dest, val ++ .set __nVal,(\val) ++ NextSetMask ~__nVal ++ .if (((~(__nVal))&~(__nMask)) > 0x255) ++ NextSetMask __nVal ++ mov\cc \dest,#(__nVal)&(__nMask) ++ .if (((__nVal)&0xffff) ^ (((__nVal)>>16)&0xffff))<>0 ++ Big2CC orr\cc,\dest,(__nVal)&~(__nMask) ++ .else ++ .set __nVal,(__nVal)&~(__nMask) ++ .if (__nVal)<>0 ++ NextSetMask __nVal ++ orr\cc \dest,\dest,#(__nVal)&(__nMask) ++ .set __nVal,(__nVal)&~(__nMask) ++ .if (__nVal)<>0 ++ orr\cc \dest,\dest,\dest,LSR #16 ++ .endif ++ .endif ++ .endif ++ .else ++ mvn\cc \dest,#(~(__nVal))&(__nMask) //complement of complement is original ++ Big2CC bic\cc,\dest,(~(__nVal))&~(__nMask) ++ .endif ++.endm ++ ++ ++.macro BigAddCC cc,dest,src,val ++ .set __nVal,(\val) ++ .if (__nVal)<>0 ++ NextSetMask -__nVal ++ .if (((-(__nVal))&~(__nMask)) > 0x255) ++ NextSetMask __nVal ++ add\cc \dest,\src,#(__nVal)&(__nMask) ++ Big2CC add\cc,\dest,(__nVal)&~(__nMask) ++ .else ++ sub\cc \dest,\src,#(-(__nVal))&(__nMask) ++ Big2CC sub\cc,\dest,(-(__nVal))&~(__nMask) ++ .endif ++ .else ++ mov\cc \dest,\src ++ .endif ++.endm ++ ++.macro BigSubCC cc,dest,src,val ++ .set __nVal,(\val) ++ BigAddCC \cc,\dest,\src,-__nVal ++.endm ++ ++.macro BigCC inst,cc,dest,src,val ++ .set __nVal,(\val) ++ .if (__nVal)<>0 ++ NextSetMask __nVal ++ \inst\cc \dest,\src,#(__nVal)&(__nMask) ++ Big2CC \inst\cc,\dest,(__nVal)&~(__nMask) ++ .else ++ mov\cc \dest,\src ++ .endif ++.endm ++ ++ ++.macro BigAndCC cc,dest,src,val ++ .set __nVal,(\val) ++ .if (~__nVal)<>0 ++ NextSetMask __nVal ++ .if (((__nVal)&~(__nMask))=0) ++ and\cc \dest,\src,#(__nVal)&(__nMask) ++ .else ++ BigCC bic,\cc,\dest,\src,~__nVal ++ .endif ++ .else ++ mov\cc \dest,\src ++ .endif ++.endm ++ ++///////////////////////////////////// ++//dest, value ++.macro BigAdd2 dest,val ++ Big2CC add,\dest,\val ++.endm ++.macro BigAdd2Eq dest,val ++ Big2CC addeq,\dest,\val ++.endm ++.macro BigAdd2Ne dest,val ++ Big2CC addne,\dest,\val ++.endm ++ ++.macro BigSub2 dest,val ++ Big2CC sub,\dest,\val ++.endm ++.macro BigSub2Eq dest,val ++ Big2CC subeq,\dest,\val ++.endm ++.macro BigSub2Ne dest,val ++ Big2CC subne,\dest,\val ++.endm ++ ++.macro BigOrr2 dest,val ++ Big2CC orr,\dest,\val ++.endm ++.macro BigOrr2Eq dest,val ++ Big2CC orreq,\dest,\val ++.endm ++.macro BigOrr2Ne dest,val ++ Big2CC orrne,\dest,\val ++.endm ++ ++.macro BigEor2 dest,val ++ Big2CC eor,\dest,\val ++.endm ++.macro BigEor2Eq dest,val ++ Big2CC eoreq,\dest,\val ++.endm ++.macro BigEor2Ne dest,val ++ Big2CC eorne,\dest,\val ++.endm ++.macro BigEor2Cs dest,val ++ Big2CC eorcs,\dest,\val ++.endm ++.macro BigEor2Cc dest,val ++ Big2CC eorcc,\dest,\val ++.endm ++ ++.macro BigBic2 dest,val ++ Big2CC bic,\dest,\val ++.endm ++.macro BigBic2Eq dest,val ++ Big2CC biceq,\dest,\val ++.endm ++.macro BigBic2Ne dest,val ++ Big2CC bicne,\dest,\val ++.endm ++ ++.macro BigAnd2 dest,val ++ BigAnd2CC al,\dest,\val ++.endm ++.macro BigAnd2Eq dest,val ++ BigAnd2CC eq,\dest,\val ++.endm ++.macro BigAnd2Ne dest,val ++ BigAnd2CC ne,\dest,\val ++.endm ++///////////////////////////////////// ++ ++.macro BigMov dest,val ++ BigMovCC al,\dest,\val ++.endm ++.macro BigMovEq dest,val ++ BigMovCC eq,\dest,\val ++.endm ++.macro BigMovNe dest,val ++ BigMovCC ne,\dest,\val ++.endm ++// dest,src,value ++.macro BigAdd dest,src,val ++ BigAddCC al,\dest,\src,\val ++.endm ++.macro BigAddEq dest,src,val ++ BigAddCC eq,\dest,\src,\val ++.endm ++.macro BigAddNe dest,src,val ++ BigAddCC ne,\dest,\src,\val ++.endm ++ ++.macro BigSub dest,src,val ++ BigSubCC al,\dest,\src,\val ++.endm ++.macro BigSubEq dest,src,val ++ BigSubCC eq,\dest,\src,\val ++.endm ++.macro BigSubNe dest,src,val ++ BigSubCC ne,\dest,\src,\val ++.endm ++ ++.macro BigOrr dest,src,val ++ BigCC orr,al,\dest,\src,\val ++.endm ++.macro BigOrrEq dest,src,val ++ BigCC orr,eq,\dest,\src,\val ++.endm ++.macro BigOrrNe dest,src,val ++ BigCC orr,ne,\dest,\src,\val ++.endm ++ ++.macro BigEor dest,src,val ++ BigCC eor,al,\dest,\src,\val ++.endm ++.macro BigEorEq dest,src,val ++ BigCC eor,eq,\dest,\src,\val ++.endm ++.macro BigEorNe dest,src,val ++ BigCC eor,ne,\dest,\src,\val ++.endm ++.macro BigEorCs dest,src,val ++ BigCC eor,cs,\dest,\src,\val ++.endm ++.macro BigEorCc dest,src,val ++ BigCC eor,cc,\dest,\src,\val ++.endm ++ ++.macro BigBic dest,src,val ++ BigCC bic,al,\dest,\src,\val ++.endm ++.macro BigBicEq dest,src,val ++ BigCC bic,eq,\dest,\src,\val ++.endm ++.macro BigBicNe dest,src,val ++ BigCC bic,ne,\dest,\src,\val ++.endm ++ ++.macro BigAnd dest,src,val ++ BigAndCC al,\dest,\src,\val ++.endm ++.macro BigAndEq dest,src,val ++ BigAndCC eq,\dest,\src,\val ++.endm ++.macro BigAndNe dest,src,val ++ BigAndCC ne,\dest,\src,\val ++.endm ++ ++// ******************************************************************************************* ++ .list +diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/burn.inc u-boot-1.1.2-neon/include/asm-arm/arch-pxa/burn.inc +--- u-boot-1.1.2/include/asm-arm/arch-pxa/burn.inc 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/burn.inc 2007-08-11 21:07:21.000000000 +0200 +@@ -0,0 +1,367 @@ ++#define FLASH_GPIO_STATUS 0 //1 means use gp to tell when flash is ready ++ ++#if (PLATFORM_TYPE==NEONB) ++#define FLASH_BASE_ADDRESS 0x04000000 ++#else ++#define FLASH_BASE_ADDRESS 0x0 ++#endif ++ ++ ++#define FLASH_ID_CMD ((0x0090<<16) + 0x0090) //read Identifier Codes ++#define FLASH_STATUS_CMD ((0x0070<<16) + 0x0070) ++#define FLASH_STATUS_CLEAR_CMD ((0x0050<<16) + 0x0050) ++#define FLASH_READ_CMD ((0x00FF<<16) + 0x00FF) //Read Array/Reset ++#define FLASH_ERASE_CMD ((0x0020<<16) + 0x0020) //Block Erase ++#define FLASH_CONFIRM_CMD ((0x00D0<<16) + 0x00D0) //Block Erase and Program Resume ++//#define FLASH_WRITE_CMD ((0x0040<<16) + 0x0040) //Program word ++#define FLASH_WRITE_TO_BUFFER_CMD ((0x00E8<<16) + 0x00E8) //Program word ++ ++#define FLASH_SUCCESS_RSP ((0x0080<<16) + 0x0080) ++ ++#define stmicro_manCode ((0x0020<<16) + 0x0020) ++#define intel_manCode ((0x0089<<16) + 0x0089) ++#define SECT_SIZE (1<<18) //256k ++ ++#define f320j3a_devCode ((0x0016<<16) + 0x0016) ++#define f320j3a_NUM_SECTORS 32 //for 8M flash ++#define f320j3a_SIZE (f320j3a_NUM_SECTORS*SECT_SIZE) ++ ++#define f640j3a_devCode ((0x0017<<16) + 0x0017) ++#define f640j3a_NUM_SECTORS 64 //for 16M flash (8 meg on 16bit boards) ++#define f640j3a_SIZE (f640j3a_NUM_SECTORS*SECT_SIZE) ++ ++#define f128j3a_devCode ((0x0018<<16) + 0x0018) ++#define f128j3a_NUM_SECTORS 128 //for 32M flash ++#define f128j3a_SIZE (f128j3a_NUM_SECTORS*SECT_SIZE) ++// ***************************** ++#define MANCODE 0 ++#define DEVCODE 4 ++ ++ ++ ++#define rRet r6 ++#define rRamSectorEnd r7 ++#define rRamSector rNum1 ++#define rRamEnd rNum2 ++#define rFlashBase sl //r10 ++#define rFlashSector fp //r11 ++ ++#define CMD_BURN 0 ++#define CMD_VERIFY 1 ++#define CMD_BURNALL 2 ++ ++.macro delayCnt rTemp,cnt ++ mov \rTemp,#\cnt ++90: subs \rTemp,\rTemp,#1 ++ bne 90b ++.endm ++// ********************************* ++//default delay is for write recovery before read, allow 400 MHZ cpu ++.macro delay ++ delayCnt r4,((40/10)*COUNT_MULT) ++.endm ++ ++ ++ ++.macro FLASH_GPIO_WAIT_FOR_IDLE ++ .if FLASH_GPIO_STATUS ++ bl FlashGpioWaitForIdle ++ .endif ++.endm ++ ++.macro DEFINE_FLASH_GPIO_WAIT_FOR_IDLE ++ .if FLASH_GPIO_STATUS ++FlashGpioWaitForIdle: ++//500 ns delay for STS going low ++ delayCnt r4,((500/10)*COUNT_MULT) //500ns /10ns (for 100MHZ cpu cycle time) * 4 (100MHZ cpu) ++ mov r5,#0x300000 ++ BigMov r4,GPIO_BASE ++91: ldr r2,[r4,#GPLR0] ++ and r2,r2,#3 ++ cmp r2,#3 ++ subnes r5,r5,#1 ++ bne 91b ++ mov pc,lr //return ++ .endif ++.endm ++ ++//out: z-1 timeout ++.macro waitForReady istr,ildr,mask,inc ++ BigMov r2,FLASH_STATUS_CMD&\mask ++ \istr r2,[r1,#-\inc] ++ ++ FLASH_GPIO_WAIT_FOR_IDLE ++ BigMov r3,FLASH_SUCCESS_RSP&\mask ++ ++ mov r5,#0x300000*COUNT_MULT ++ .if FLASH_GPIO_STATUS ++ b 92f ++ .endif ++ ++71: ++ delayCnt r4,((500/10)*COUNT_MULT) ++92: \ildr r4,[r1,#-\inc] //!!! read status ++ and r4,r4,r3 ++ cmp r4,r3 ++ subnes r5,r5,#1 ++ bne 71b ++ ++ BigMov r2,FLASH_READ_CMD&\mask ++ \istr r2,[r1,#-\inc] ++ delay ++ teq r5,#0 ++.endm ++ ++ ++ ++//out: z-1 timeout ++.macro WaitForEraseDone istr,ildr,mask ++ FLASH_GPIO_WAIT_FOR_IDLE ++ BigMov r3,FLASH_SUCCESS_RSP&\mask ++ mov r5,#0x10000 ++92: ++ delayCnt r4,0x3000 ++ \ildr r4,[rFlashSector] ++ and r4,r4,r3 ++ cmp r4,r3 ++ subnes r5,r5,#1 ++ bne 92b ++ ++ BigMov r2,FLASH_READ_CMD&\mask ++ \istr r2,[rFlashSector,#0] ++ delay ++ teq r5,#0 ++.endm ++// *********************************** ++ ++//r5 - command - CMD_BURN or CMD_BURNALL ++//rRet(r6) succesful burn return address ++//rRamSectorEnd(r7) - but not an input, just how it is used ++//rRamSector(r8) - start ++//rRamEnd(r9) - end ++//rFlashBase(sl,r10) - flash base ++//rFlashSector(fp,r11) - starting flash sector ++//rDBG(sp,r13) ++//lr - return address on failure ++ ++.macro BurnRtn istr,ildr,mask,shift,sizeShift,inc,plait ++ str r5,[rDBG,#DBG_TEMP] ++ BigMov r0,FLASH_STATUS_CLEAR_CMD&\mask ++ \istr r0,[rFlashBase,#0] ++ delay ++ BigMov r0,FLASH_ID_CMD&\mask ++ \istr r0,[rFlashBase,#0] ++ delay ++ BigMov r4,intel_manCode&\mask ++ BigMov r1,stmicro_manCode&\mask ++ BigMov r5,f320j3a_devCode&\mask ++ \ildr r2,[rFlashBase,#MANCODE>>\shift] ++ \ildr r3,[rFlashBase,#DEVCODE>>\shift] ++ ++ BigMov r0,FLASH_READ_CMD&\mask ++ \istr r0,[rFlashBase,#0] ++ delayCnt r0,((40/10)*COUNT_MULT) ++ ++ mov r0,#f320j3a_SIZE>>\sizeShift ++ cmp r3,r5 ++ ++ BigMovNe r5,f128j3a_devCode&\mask ++ movne r0,#f128j3a_SIZE>>\sizeShift ++ cmpne r3,r5 ++ ++ BigMovNe r5,f640j3a_devCode&\mask ++ movne r0,#f640j3a_SIZE>>\sizeShift ++ cmpne r3,r5 ++ ++ cmpeq r2,r4 ++ cmpne r2,r1 ++ movne r0,#MANCODE>>2 ++ movne r1,#DEVCODE>>2 ++ movne pc,lr //return if unrecognized chip ++ ++ sub r1,rRamEnd,rRamSector ++ sub r2,rFlashSector,rFlashBase ++ add r1,r1,r2 ++ cmp r1,r0 ++ movhi pc,lr //return if trying to write too much ++ ++ ldrb r5,[rDBG,#DBG_TEMP] ++ cmp r5,#CMD_BURNALL ++ streq r0,[rDBG,#DBG_TEMP] //r0 is size of flash ++ ++ FLASH_GPIO_WAIT_FOR_IDLE ++1: ++ bl PrintSector ++ ++//Now see if block needs erased ++ add rRamSectorEnd,rRamSector,#SECT_SIZE>>\shift ++ cmp rRamSectorEnd,rRamEnd ++ movhi rRamSectorEnd,rRamEnd ++ b 3f ++2: ++ ldr r2,[r0],#4 //read ram ++ ldr r3,[r1],#4 //read flash ++ and r4,r3,r2 ++ cmp r4,r2 ++ bne 10f ++3: cmp r0,rRamSectorEnd ++ blo 2b ++ ++ ++ ldr r2,[rDBG,#DBG_TEMP] ++ movs r2,r2 ++ beq 20f ++ add r0,rFlashSector,#SECT_SIZE>>\shift ++ b 62f ++61: ++ ldr r2,[r1],#4 //read flash ++ adds r2,r2,#1 ++ bne 10f ++62: cmp r1,r0 ++ blo 61b ++ b 19f //erase not needed ++ ++//erase ++10: ++ BigMov r3,FLASH_READ_CMD&\mask ++ \istr r3,[rFlashBase,#0] ++ delay ++ ldr r3,[r1,#-4] //read flash ++ and r4,r3,r2 ++ cmp r4,r2 ++ beq 3b //br if (we signal) glitch caused a spurious status register read ++ ++ BigMov r0,FLASH_ERASE_CMD&\mask ++ \istr r0,[rFlashSector] ++ BigMov r0,FLASH_CONFIRM_CMD&\mask ++ \istr r0,[rFlashSector] ++ bl PrintErasing ++ ++ WaitForEraseDone \istr,\ildr,\mask ++ beq Timeout //br if erase timed out ++ ++ .if (\plait) ++ BigMov r0,FLASH_ERASE_CMD&\mask ++ \istr r0,[rFlashSector,#2] ++ BigMov r0,FLASH_CONFIRM_CMD&\mask ++ \istr r0,[rFlashSector,#2] ++ bl PrintErasing ++ ++ WaitForEraseDone \istr,\ildr,\mask ++ beq Timeout //br if erase timed out ++ .endif ++ ++19: cmp rRamSector,rRamSectorEnd ++ bhs 42f ++ ++//programming ++20: ++ bl PrintProgramming ++21: ++ ldr r2,[r0],#4 //read ram ++ ldr r3,[r1],#4 //read flash ++ cmp r2,r3 ++ bne 22f ++28: ++ cmp r0,rRamSectorEnd ++ blo 21b ++ b 30f //goto verify ++ ++22: ++ sub r1,r1,#4 ++ sub r0,r0,#4 ++ and r2,r1,#0x3f>>\shift //align to a 64 byte boundary (32 per device) ++ sub r1,r1,r2 ++ sub r0,r0,r2 ++ ++ BigMov r2,FLASH_WRITE_TO_BUFFER_CMD&\mask ++ \istr r2,[r1] //!!! write_to_buffer ++ ++ sub r3,rRamSectorEnd,r0 ++ mov r3,r3,LSR #2-\shift ++ sub r3,r3,#1 ++ cmp r3,#0x0f ++ movhi r3,#0x0f ++ orr r2,r3,r3,LSL #16 ++ \istr r2,[r1] //!!! word cnt -1 ++25: \ildr r2,[r0],#\inc ++ \istr r2,[r1],#\inc //!!! words ++ subs r3,r3,#1 ++ bpl 25b ++ BigMov r2,FLASH_CONFIRM_CMD&\mask ++ \istr r2,[r1,#-\inc] //!!! confirm ++ ++ waitForReady \istr,\ildr,\mask,\inc ++ ++ .if (\plait) ++ beq 88f ++ sub r1,r1,#\inc ++ sub r0,r0,#\inc ++ and r2,r1,#0x3f>>\shift //align to a 64 byte boundary (32 per device) ++ sub r1,r1,r2 ++ sub r0,r0,r2 ++ ++ BigMov r2,FLASH_WRITE_TO_BUFFER_CMD&\mask ++ \istr r2,[r1,#2]! //!!! write_to_buffer ++ sub r3,rRamSectorEnd,r0 ++ add r0,r0,#2 ++ mov r3,r3,LSR #2-\shift ++ sub r3,r3,#1 ++ cmp r3,#0x0f ++ movhi r3,#0x0f ++ orr r2,r3,r3,LSL #16 ++ \istr r2,[r1] //!!! word cnt -1 ++85: \ildr r2,[r0],#\inc ++ \istr r2,[r1],#\inc //!!! words ++ subs r3,r3,#1 ++ bpl 85b ++ BigMov r2,FLASH_CONFIRM_CMD&\mask ++ \istr r2,[r1,#-\inc] //!!! confirm ++ ++ waitForReady \istr,\ildr,\mask,\inc ++ sub r0,r0,#2 ++ sub r1,r1,#2 ++ ++ bne 28b ++88: ++ ++ .else ++ bne 28b ++ .endif ++ sub rRamSector,r0,#0x40>>\shift //whoops, timeout ++ sub rFlashSector,r1,#0x40>>\shift ++ b Timeout ++ ++ ++ ++//verify ++30: ++ bl PrintVerifying ++31: ++ ldr r2,[r0],#4 //read ram ++ ldr r3,[r1],#4 //read flash ++ cmp r2,r3 ++ bne 33f ++32: cmp r0,rRamSectorEnd ++ blo 31b ++42: ++ add rRamSector,rRamSector,#SECT_SIZE>>\shift ++ add rFlashSector,rFlashSector,#SECT_SIZE>>\shift ++ cmp rRamSector,rRamEnd ++ blo 1b //goto next sector ++ ++ ldr r2,[rDBG,#DBG_TEMP] ++ add r2,r2,rFlashBase ++ cmp rFlashSector,r2 ++ blo 1b ++ ++ b PrintSuccess ++33: ++ BigMov r3,FLASH_READ_CMD&\mask ++ \istr r3,[rFlashBase,#0] ++ delay ++ ldr r3,[r1,#-4] //read flash ++ cmp r2,r3 ++ beq 32b //br if (we signal) glitch caused a spurious status register read ++ b ReturnError ++.endm +diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/miniMac.inc u-boot-1.1.2-neon/include/asm-arm/arch-pxa/miniMac.inc +--- u-boot-1.1.2/include/asm-arm/arch-pxa/miniMac.inc 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/miniMac.inc 2007-08-11 21:07:21.000000000 +0200 +@@ -0,0 +1,476 @@ ++#include "platformTypes.h" ++#define SUB_LR_FALL_THRU_FOR_FIQ 1 //0 for branch ++#define LITTLE_ENDIAN 1 //describes memory system ++#define DDEBUG 0 ++#define DO_GPTEST 0 ++ ++#define MACH_TYPE_SCANPASS 332 ++ ++#define ATAG_CORE 0x54410001 ++#define ATAG_MEM 0x54410002 ++#define TAGGED_LIST 0xa0000100 ++ .ifdef __ARMASM ++ GBLA STACKS_VALID ++ GBLA CONFIG_STACKS_VALID ++ .set CONFIG_STACKS_VALID,1 ++ .endif ++ ++#if (SOFTWARE_TYPE==WINCE) ++ .set STACKS_VALID,1 ++ .ifdef __ARMASM ++ .else ++#ifndef CONFIG_STACKS_VALID ++#define CONFIG_STACKS_VALID 1 ++#endif ++ .endif ++ ++#define SDRAM_BASE_C_VIRTUAL 0xA0000000 //0x80000000 is cached mapped, 0xa0000000 is uncacheable ++#define UART_VIRT_BASE 0xAA100000 ++#define VMA_DEBUG (0xfff00000) ++#define VIRTUAL_CS0 0xa8000000 ++#define VIRTUAL_CS1 0xa8000000 ++ ++#else ++#ifdef CONFIG_STACKS_VALID ++ .set STACKS_VALID,1 ++#else ++ .set STACKS_VALID,0 ++#endif ++#define SDRAM_BASE_C_VIRTUAL 0xC0000000 ++#define UART_VIRT_BASE 0xf8100000 ++//#define VMA_DEBUG 0xff000000 ++//!!!!!for some reason the above base causes bizarre problems ++#define VMA_DEBUG (0xfff00000) ++#define VIRTUAL_CS0 0xff000000 ++#define VIRTUAL_CS1 0xff100000 ++#endif ++ ++#define V_rWork r2 ++#define V_rBranch r3 ++#define I_rWork r2 ++#define I_rBranch sp //r13 ++ ++#ifdef CONFIG_STACKS_VALID ++#define rWork V_rWork ++#define rBranch V_rBranch ++ ++#else ++#define rWork I_rWork ++#define rBranch I_rBranch ++#endif ++ ++ ++#if 0 ++#define RED_VAL 0x15 ++#define GREEN_VAL 0x2a ++#define BLUE_VAL 0x0a ++#else ++#define RED_VAL 0x0 ++#define GREEN_VAL 0x0 ++#define BLUE_VAL 0x0 ++#endif ++ ++//#define BAUDRATE 9600 ++//#define BAUDRATE 38400 ++//#define BAUDRATE 57600 ++//#define BAUDRATE 57600 ++#define BAUDRATE 115200 ++//#define BAUDRATE 230400 ++ ++#if (CPU_CLOCK==100) ++#define COUNT_MULT 1 ++#else ++#if (CPU_CLOCK==200) ++#define COUNT_MULT 2 ++#else ++#if (CPU_CLOCK==300) ++#define COUNT_MULT 3 ++#else ++#define COUNT_MULT 4 ++#endif ++#endif ++#endif ++ ++#if 1 //(SOFTWARE_TYPE==WINCE) ++#define RECEIVE_LOOP_COUNT 0x10000*COUNT_MULT ++#else ++#if (PLATFORM_TYPE==GAME_CONTROLLER_PLAITED_A1)||(PLATFORM_TYPE==GAME_CONTROLLER)||(PLATFORM_TYPE==GAME_WITH_SMC) ++#define RECEIVE_LOOP_COUNT 0x100000*COUNT_MULT ++#else ++#define RECEIVE_LOOP_COUNT 0x300000*3*COUNT_MULT ++#endif ++#endif ++ ++// ********************************************************** ++#define DBG_MAGIC 95 //this allows BigMov sp,DEBUG_BASE+DBG_MAGIC to generate just 1 instruction ++//#define DBG_START -95 ++#define DBG_START 0 ++#define DBG_R0 ((0<<2)+DBG_START) ++#define DBG_R1 ((1<<2)+DBG_START) ++#define DBG_R2 ((2<<2)+DBG_START) ++#define DBG_R3 ((3<<2)+DBG_START) ++#define DBG_R4 ((4<<2)+DBG_START) ++#define DBG_R5 ((5<<2)+DBG_START) ++#define DBG_R6 ((6<<2)+DBG_START) ++#define DBG_R7 ((7<<2)+DBG_START) ++#define DBG_R8 ((8<<2)+DBG_START) ++#define DBG_R9 ((9<<2)+DBG_START) ++#define DBG_SL ((10<<2)+DBG_START) ++#define DBG_FP ((11<<2)+DBG_START) ++#define DBG_IP ((12<<2)+DBG_START) ++#define DBG_SP ((13<<2)+DBG_START) ++#define DBG_LR ((14<<2)+DBG_START) ++#define DBG_PC ((15<<2)+DBG_START) ++#define DBG_CPSR ((16<<2)+DBG_START) //this and above have corresponding symbol #s ++ ++#define DBG_HCPSR ((17<<2)+DBG_START) //interrupt handler original CPSR ++#define DBG_TRACE ((18<<2)+DBG_START) ++#define DBG_LastSignal ((19<<2)+DBG_START) //only 1 byte ++#define DBG_Mode (((19<<2)+1)+DBG_START) //only 1 byte, bit 0 -1 means gdb mode for control breaks ++#define DBG_FFUART_LCR (((19<<2)+2)+DBG_START) //only 1 byte ++#define DBG_HSP ((20<<2)+DBG_START) //handler stack pointer on entry, for aborts ++#define DBG_TEMP ((21<<2)+DBG_START) ++//22 free ++#define DBG_ABORT_PC ((23<<2)+DBG_START) ++#define DBG_INDIRECT_R0 ((24<<2)+DBG_START) //it needs it's own space in case a debug interrupt ++#define DBG_INDIRECT_LR ((25<<2)+DBG_START) //happens in the return code, but memory is mapped if used ++#define DEBUG_SPACE (((23<<2)|0x1f)+1) //a multiple of 32 bytes ++ ++// ********************************************************* ++ ++#define DEBUG_START (VMA_DEBUG+0x3000-DEBUG_SPACE) //this saves on memory, but the else is easier to debug ++#define VMA_DEBUG_OFFSET (0xffff0000-VMA_DEBUG) ++#define DEBUG_BASE (DEBUG_START-DBG_START) ++#define DEBUG_SYM DEBUG_START ++ ++ ++#define SYM_R0 0 ++#define SYM_R1 1 ++#define SYM_R2 2 ++#define SYM_R3 3 ++#define SYM_R4 4 ++#define SYM_R5 5 ++#define SYM_R6 6 ++#define SYM_R7 7 ++#define SYM_R8 8 ++#define SYM_R9 9 ++#define SYM_SL 10 ++#define SYM_FP 11 ++#define SYM_IP 12 ++#define SYM_SP 13 ++#define SYM_LR 14 ++#define SYM_PC 15 ++#define SYM_CPSR 16 ++ ++//#define SYM_SPSR 17 //nice to have, but do it later ++//#define SYM_FPS 17 ++#define SYM_FP0 17 //40 bits, 5 ++#define SYM_FSR 18 ++#define SYM_FAR 19 ++#define SYM_DCSR 20 ++#define SYM_TTBR 21 ++#define SYM_CTRL 22 ++ ++#define SYM_LAST 22 ++ ++#define SYM_LAST_RCMD (SYM_FP0) //last symbol printed by R cmd ++ ++ ++ ++#define SIG_RESET 0 ++#define SIG_UNDEFINED_INSTRUCTION 1 ++#define SIG_SWI 2 ++#define SIG_PREFETCH_ABORT 3 ++#define SIG_DATA_ABORT 4 ++#define SIG_UNUSED 5 ++#define SIG_IRQ 6 ++#define SIG_FIQ 7 ++#define SIG_DBG 8 ++#define SIG_DBG_RESET 8+0 ++#define SIG_DBG_INSTRUCTION_BKPT 8+1 ++#define SIG_DBG_DATA_BKPT 8+2 ++#define SIG_DBG_BKPT_SOFTWARE 8+3 ++#define SIG_DBG_EXTERNAL 8+4 ++#define SIG_DBG_VECTOR_TRAP 8+5 ++#define SIG_DBG_TRACE_BUFFER_FULL 8+6 ++#define SIG_DBG_RESERVED 8+7 ++ ++#define GDB_EXIT_CHAR 0x0d ++// ****************************************************************** ++#define rFieldStart r4 ++#define rField r5 ++#define rValidCnt r6 ++#define rCommand r7 ++#define rNum1 r8 ++#define rNum2 r9 ++#define rSymbol sl //r10 ++#define rPrevNum1 fp //r11 ++#define rUart ip //r12 ++#define rDBG sp ++ ++//in Go routine, temporary ++#define rBCR0 sl //r10 ++#define rBCR1 fp //r11 ++ ++//in GDB routines ++#define rGdbCmd r5 ++#define rGdbNum1 r6 ++#define rGdbTermChar1 r7 ++#define rGdbNum2 r8 ++#define rGdbTermChar2 r9 ++#define rGdbNum3 sl //r10 ++#define rGdbChkSum fp //r11 ++ ++//in Download routine ++#define rDest r3 ++#define rPacketLength r4 ++#define rDestHead r5 ++#define rBlockNum r6 ++#define rNak r7 ++#define rCRC r8 ++#define rRunningCRC r9 ++#define rPrevCRC sl //r10 ++ ++#define rSP r8 //register which contains L4(' ',' ',' ',' '), all spaces ++// ******** ++ ++#define CR 0x0d ++#define LF 0x0a ++ ++// ****************************** ++#define F_INC 4 ++ ++#define F_NUM1_BIT (F_INC*3) ++#define F_NUM2_BIT (F_INC*5) ++ ++#define F_COMMAND 1<<(F_INC) ++#define F_NUM1 1<<(F_NUM1_BIT) ++#define F_NUM2 1<<(F_NUM2_BIT) ++#define F_UNDEF 1<<(F_INC*7) ++ ++#define F_COMMAND_MASK ((1<0 ++ b 93f ++ .set cnt,cnt-1 ++ WEND ++ .else ++ .rept (\branch) ++ b 93f ++ .endr ++ .endif ++ ++AfterPCPrint: ++ mov r0,#0x55 ++ b AfterPCPrint1 ++InitializeCont: ++ b MainInitializationCode ++93: ++.endm ++ ++ ++.macro RelocationVector branch //vector table at 0xffff0000, br to vector table at VMA_DEBUG ++ //warning, do not use relocated vectors unless memory management is enabled and VMA_DEBUG is mapped ++ .ifdef __ARMASM ++ LCLA cnt ++ .set cnt,$branch ++ WHILE cnt>0 ++ b 71f ++ .set cnt,cnt-1 ++ WEND ++ .else ++ .rept (\branch) ++ b 71f ++ .endr ++ .endif ++ ++ mov pc,#0x00 //0 - reset always goes to 0 because it will be in physical memory mode for instructions ++ b .-VMA_DEBUG_OFFSET //4 - UndefinedInstr ++ b .-VMA_DEBUG_OFFSET //8 - SWI ++ b .-VMA_DEBUG_OFFSET //0x0c - PrefetchAbort ++ b .-VMA_DEBUG_OFFSET //0x10 - DataAbort ++ b .-VMA_DEBUG_OFFSET //0x14 - Unused ++ b .-VMA_DEBUG_OFFSET //0x18 - IRQ ++ .if SUB_LR_FALL_THRU_FOR_FIQ ++ sub lr,lr,#4 //0x1c - FIQ ++ .else ++ b .-VMA_DEBUG_OFFSET //0x1c - FIQ ++ .endif ++ ++//these instructions are always at this address ++//to minimize the effect of a mismatch of minicache and flash ++ReturnWithIndirection: ++ mov r0,r0 //!!!! make sure this instruction is in the 1st 4k of flash so that BigOrr2Ne is guaranteed to work ++ ldr pc,[sp],#4 ++ ++//c-0 invalidate caches, c-1 skip cache invalidate ++//z-1 return direct, z-0 return indirect ++InvalidateAndReturn: ++ adrne lr,ReturnWithIndirection ++ ldreq lr,[r0,#DBG_PC-DBG_R2] ++ BigOrr2Ne lr,VMA_DEBUG //this range is sure to give an external abort for errata on exiting SDS ++ ++//Invalidate the data/instruction cache and branch target buffer ++ ++ CP15_CF_INVAL_BOTH mcrcc,r1 ++ CPWAIT r1 ++ ++ ldr sp,[r0,#DBG_HSP-DBG_R2] ++ ldr r1,[r0,#DBG_R1-DBG_R2] ++ str r0,[r0,#DBG_ABORT_PC-DBG_R2] //reset error flag so abort can be retried ++ ldr r0,[r0,#DBG_R0-DBG_R2] ++ movs pc,lr ++71: ++.endm ++ ++.macro CheckBranch rTemp,rAddr ++ movs \rTemp,pc //don't redirect if running from flash ++ submi \rAddr, \rAddr, #0x00010000 ++ ldrmi \rTemp, [\rAddr], #8 ++ eormi \rTemp, \rTemp, #0xea000000 ++ tstmi \rTemp, #0xff000000 ++ moveq \rTemp, \rTemp, LSL #8 ++ addeq \rAddr, \rAddr, \rTemp, ASR #6 ++.endm ++.macro CheckLdr rTemp,rAddr //check for instruction LDR pc,[pc,#nnn] ++ eor \rTemp, \rTemp, #0x0f900000 ++ eor \rTemp, \rTemp, #0x000ff000 ++ cmp \rTemp, #0x1000 ++ ldrcc \rAddr,[\rAddr,\rTemp] ++.endm ++ ++//this is case where stacks are assumed valid ++.macro V_VectorEntrance Work,Branch,code ++ stmdb sp!,{\Work,\Branch,lr} ++ mov \Branch,#\code<<2 ++.endm ++.macro V_VectorExitCC Work,Branch,cc,ccia ++ str\cc \Branch,[sp,#8] ++ ldm\ccia sp!,{\Work,\Branch,pc} ++.endm ++.macro V_VectorExitCC1 Work,Branch,cc,ccia ++ str\cc \Branch,[sp,#8] ++ ldm\ccia sp!,{\Work,\Branch,pc} ++.endm ++ ++//this is case where stacks are assumed invalid ++.macro I_VectorEntrance Work,Branch,code ++ BigMov \Branch,DEBUG_BASE+DBG_MAGIC ++ str \Work,[\Branch,#DBG_TEMP-DBG_MAGIC] ++ mov \Branch, #\code<<2 ++.endm ++.macro I_VectorExitCC Work,Branch,cc,ccia ++ BigMovCC \cc,\Work,DEBUG_BASE+DBG_MAGIC ++ ldr\cc \Work,[\Work,#DBG_TEMP-DBG_MAGIC] ++ bx\cc \Branch ++.endm ++.macro I_VectorExitCC1 Work,Branch,cc,ccia ++ BigMov \Work,DEBUG_BASE+DBG_MAGIC ++ ldr\cc \Work,[\Work,#DBG_TEMP-DBG_MAGIC] ++ bx\cc \Branch ++.endm ++.macro VectorEntrance Work,Branch,code ++ .if STACKS_VALID ++ V_VectorEntrance \Work,\Branch,\code ++ .else ++ I_VectorEntrance \Work,\Branch,\code ++ .endif ++.endm ++.macro JOIN brcc ++ .if STACKS_VALID ++ \brcc join_fiq ++ .else ++ \brcc join_irq ++ .endif ++.endm ++.macro JOIN2 brcc ++ .if STACKS_VALID ++ \brcc join_fiq2 ++ .else ++ \brcc join_irq2 ++ .endif ++.endm ++// ***************************************************** ++ ++.macro SaveRegisters rBase,rTemp ++ CalcMemSize \rBase,\rTemp,MEMORY_CONTROL_BASE //out: \rTemp - mem size ++ BigAdd \rBase,\rTemp,MEM_START-0x1000+((DEBUG_BASE+DBG_MAGIC)&0xfff) //last 4k of memory ++ mov \rTemp,#0 ++//great, now memory should be working, let's save registers, only r0(rBase),sp(rTemp) have been lost ++//don't trust LDM,STM instructions in debug mode.... ++//or LDR w/Rd=PC, LDR w/RRX addressing mode, SWP, LDC, STC ++// ******************************************************* ++// ******************************************************* ++ str \rTemp,[\rBase,#DBG_START-32 -DBG_MAGIC] ++ str \rTemp,[\rBase,#DBG_R0 -DBG_MAGIC] ++ str r1, [\rBase,#DBG_R1 -DBG_MAGIC] ++ str r2, [\rBase,#DBG_R2 -DBG_MAGIC] ++ str r3, [\rBase,#DBG_R3 -DBG_MAGIC] ++ str \rTemp,[\rBase,#DBG_TRACE -DBG_MAGIC] ++ str \rTemp,[\rBase,#DBG_LastSignal-DBG_MAGIC] ++.endm ++.macro ReadHexE dest,rCnt1 ++ ++#if LITTLE_ENDIAN ++ mov \rCnt1,#4 ++ mov \dest,#0 ++1: bl ReadHex ++ bcc CheckSumError ++ add rGdbChkSum,rGdbChkSum,r0 //update checksum ++ mov r1,r1,LSL #28 ++ add \dest,r1,\dest,LSR #8 ++ ++ bl ReadHex ++ bcc CheckSumError ++ add rGdbChkSum,rGdbChkSum,r0 //update checksum ++ add \dest,\dest,r1,LSL #24 ++#else ++ mov \rCnt1,#8 ++ mov \dest,#0 ++1: bl ReadHex ++ bcc CheckSumError ++ add rGdbChkSum,rGdbChkSum,r0 //update checksum ++ add \dest,r1,\dest,LSL #4 ++#endif ++ subs \rCnt1,\rCnt1,#1 ++ bne 1b ++.endm ++ ++ ++ +diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/mmc.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/mmc.h +--- u-boot-1.1.2/include/asm-arm/arch-pxa/mmc.h 2003-06-27 23:32:42.000000000 +0200 ++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/mmc.h 2007-08-11 21:07:21.000000000 +0200 +@@ -4,7 +4,7 @@ + * Author: Vladimir Shebordaev, Igor Oblakov + * Copyright: MontaVista Software Inc. + * +- * $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $ ++ * $Id: mmc.h,v 1.3 2005/04/16 17:05:19 ericn Exp $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as +@@ -113,12 +113,17 @@ + #define MMC_CMD_SET_RCA 3 + #define MMC_CMD_SEND_CSD 9 + #define MMC_CMD_SEND_CID 10 ++#define MMC_CMD_STOP 12 + #define MMC_CMD_SEND_STATUS 13 + #define MMC_CMD_SET_BLOCKLEN 16 + #define MMC_CMD_READ_BLOCK 17 + #define MMC_CMD_RD_BLK_MULTI 18 + #define MMC_CMD_WRITE_BLOCK 24 + ++#define SD_APP_CMD55 55 /* 0x37 */ ++#define SD_APP_CMD41 41 /* 0x29 */ ++#define SD_STATUS 13 /* 0x0D */ ++ + #define MMC_MAX_BLOCK_SIZE 512 + + #define MMC_R1_IDLE_STATE 0x01 +@@ -197,4 +202,15 @@ + } mmc_csd_t; + + ++typedef struct sd_status { ++ ulong prot_size ; ++ ushort card_type ; ++ ushort bus_width:2, ++ secured_mode:1, ++ unused0: 13 ; ++} sd_status_t ; ++ ++extern uchar * ++mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat); ++ + #endif /* __MMC_PXA_P_H__ */ +diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/platformTypes.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/platformTypes.h +--- u-boot-1.1.2/include/asm-arm/arch-pxa/platformTypes.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/platformTypes.h 2007-08-11 21:07:21.000000000 +0200 +@@ -0,0 +1,19 @@ ++#ifndef __PLATFORMTYPES_H__ ++#define __PLATFORMTYPES_H__ 1 ++#define NEON 1 ++#define NEONB 2 ++#define BD2003 3 ++#define GAME_WITH_SMC 4 ++#define GAME_CONTROLLER 5 ++#define GAME_CONTROLLER_PLAITED_A1 6 ++#define BOUNDARY_OLD_BOARD 7 //lcd pin reordering for rgb problem, don't use VLIO(gp18 is turnstile) ++#define OLD_GAME_CONTROLLER 8 ++#define HALOGEN 9 ++ ++#if (PLATFORM_TYPE==NEONB) ++#define PHYS_FLASH_BASE 0x04000000 ++#else ++#define PHYS_FLASH_BASE 0x0 ++#endif ++ ++#endif +diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/pxa250Base.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxa250Base.h +--- u-boot-1.1.2/include/asm-arm/arch-pxa/pxa250Base.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxa250Base.h 2007-08-11 21:07:21.000000000 +0200 +@@ -0,0 +1,60 @@ ++#ifndef __PXA250BASE_H__ ++#define __PXA250BASE_H__ 1 ++ ++#ifdef __ARMASM ++#define USE_PHYSICAL 1 ++#else ++#ifndef _MSC_VER ++#define USE_PHYSICAL 1 ++#endif ++#endif ++ ++ ++#ifndef USE_PHYSICAL ++#if EBOOT_PHYS ++#define USE_PHYSICAL 1 ++#endif ++#endif ++ ++#if USE_PHYSICAL ++#define PCMCIA_CARD0_IO 0x20000000 ++#define PCMCIA_CARD0_ATTR 0x28000000 ++#define PCMCIA_CARD0_MEM 0x2c000000 ++ ++#define PCMCIA_CARD1_IO 0x30000000 ++#define PCMCIA_CARD1_ATTR 0x38000000 ++#define PCMCIA_CARD1_MEM 0x3c000000 ++ ++#define FFUART_BASE 0x40100000 ++#define BTUART_BASE 0x40200000 ++#define STUART_BASE 0x40700000 ++#define UART_BASE FFUART_BASE ++//#define UART_BASE BTUART_BASE ++ ++#define OS_TIMER_BASE 0x40a00000 ++#define IC_BASE 0x40D00000 ++#define GPIO_BASE 0x40E00000 ++#define PWR_MANAGER_BASE 0x40F00000 ++#define CLK_MANAGER_BASE 0x41300000 ++#define LCD_CONTROL_BASE 0x44000000 ++#define MEMORY_CONTROL_BASE 0x48000000 ++ ++#define MEM_START 0xa0000000 ++ ++ ++#else ++#include "xsc1.h" ++ ++#define PCMCIA_CARD0_IO PCMCIA_S0_IO_U_VIRTUAL ++#define PCMCIA_CARD0_ATTR PCMCIA_S0_ATTR_U_VIRTUAL ++#define PCMCIA_CARD0_MEM PCMCIA_S0_CMN_U_VIRTUAL ++ ++#define PCMCIA_CARD1_IO PCMCIA_S1_IO_U_VIRTUAL ++#define PCMCIA_CARD1_ATTR PCMCIA_S1_ATTR_U_VIRTUAL ++#define PCMCIA_CARD1_MEM PCMCIA_S0_CMN_U_VIRTUAL ++ ++#define MEMORY_CONTROL_BASE MEMC_BASE_U_VIRTUAL ++#define GPIO_BASE GPIO_BASE_U_VIRTUAL ++#endif ++ ++#endif +diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/pxaGpio25x.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaGpio25x.h +--- u-boot-1.1.2/include/asm-arm/arch-pxa/pxaGpio25x.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaGpio25x.h 2007-08-11 21:07:21.000000000 +0200 +@@ -0,0 +1,218 @@ ++//gpios for PLATFORM_TYPE== NEON,NEONB,BD2003, or BOUNDARY_OLD_BOARD ++ ++#define LCD_CS_STATE HIGH ++ ++//CP - Clock and Power Management Unit ++//MMC - Multimedia Card Controller ++//MC - Memory Controller ++//SIU - System Integration Unit ++//SSP - Synchronous Serial Port ++//AC - Audio Controller (AC97) ++//FF - Full Function UART ++//BT - Blue Tooth UART ++//ST - standard UART Port ++//LCD - LCD Controller ++ SPEC_GP 0,IN,HIGH,0 // flash ready low 16, or magStripe T1 Clk(SMC) ++ SPEC_GP 1,IN,HIGH,0 //CP_RST, flash ready high 16, or magStripe T2 Clk(SMC) ++ ++#if (PLATFORM_TYPE==NEONB) ++ SPEC_GP 2,IN,HIGH,0 //USB client connection status ++ SPEC_GP 3,IN,HIGH,0 //float means USB Slave not ready to accept data ++ //out 1 means ready (D+ signal) ++ SPEC_GP 4,OUT,LOW,0 //low means don't provide 12 volts to I2C bus ++#else ++#if (PLATFORM_TYPE==NEON) ++ SPEC_GP 2,IN,HIGH,0 //USB client connection status ++ SPEC_GP 3,IN,HIGH,0 //float means USB Slave not ready to accept data ++ SPEC_GP 4,IN,HIGH,0 //UCB1400 irq on NEON board ++#else ++ SPEC_GP 2,OUT,LOW,0 //output to transistor (unused), OUT_DRY_CONTACT2 ++ SPEC_GP 3,OUT,HIGH,0 ++ SPEC_GP 4,IN,HIGH,0 //interrupt for USB irq 1 ++#endif ++#endif ++ ++ SPEC_GP 5,IN,HIGH,0 //interrupt for USB irq 2, or SM501 ++ SPEC_GP 6,OUT,HIGH,1 //MMC_CLK ++ SPEC_GP 7,OUT,LOW,0 //CP_48MHZ !!! red led, NEON:J13,pin3 ++ SPEC_GP 8,OUT,HIGH,1 //MMC_CCS0 ++ SPEC_GP 9,OUT,LOW,0 //MMC_CCS1, !!! doorlock, or OUT_DRY_CONTACT1 ++ SPEC_GP 10,IN,HIGH,0 //SIU_RTCCLK, Neon/Neonb data 1 for SDIO interrupt ++ ++#if (PLATFORM_TYPE==NEON) ++ SPEC_GP 11,OUT,HIGH,0 //CP_3600KHZ, NEON:J12,pin1 ++#else ++ SPEC_GP 11,IN,HIGH,0 //CP_3600KHZ, suspend USB slave ++#endif ++ SPEC_GP 12,IN,HIGH,0 //CP_32KHZ, suspend USB host ++ ++#if (PLATFORM_TYPE==NEON) || (PLATFORM_TYPE==NEONB) ++ SPEC_GP 13,OUT,HIGH,2 //MC_MBGNT ++ SPEC_GP 14,IN,HIGH,1 //MC_MBREQ ++#else ++ SPEC_GP 13,OUT,HIGH,0 //USB wakeup slave ++ SPEC_GP 14,IN,HIGH,0 //UCB1400 IRQ ++#endif ++ ++ ++#if (PLATFORM_TYPE==NEONB) ++ SPEC_GP 15,OUT,HIGH,2 //MC_nCS1, eeprom ++#else ++#if (PLATFORM_TYPE==NEON) ++ SPEC_GP 15,OUT,LOW,0 //MC_nCS1, NEON:J13, pin 1 ++#else ++ SPEC_GP 15,OUT,LOW,0 //MC_nCS1, !!! amber led ++#endif ++#endif ++ ++ ++#if (PLATFORM_TYPE==NEON) || (PLATFORM_TYPE==NEONB) ++ SPEC_GP 16,OUT,HIGH,0 //LCD backlight brightness control ++ SPEC_GP 17,OUT,HIGH,0 //LCD backlight ON/OFF ++#else ++ SPEC_GP 16,IN,HIGH,0 //SIU_PWM0, !!! feedback2, left in ++ SPEC_GP 17,IN,HIGH,0 //SIU_PWM1, !!! feedback1, right in ++#endif ++ ++#if (PLATFORM_TYPE==BOUNDARY_OLD_BOARD) ++ SPEC_GP 18,OUT,HIGH,0 //MC_RDY, !!! turnstile ++#else ++ SPEC_GP 18,IN,HIGH,1 //MC_RDY, VIO_READY ++#endif ++ ++#if (PLATFORM_TYPE==NEON) || (PLATFORM_TYPE==NEONB) ++ SPEC_GP 19,OUT,HIGH,0 //MC_DREQ1, nc ++#else ++ SPEC_GP 19,IN,HIGH,1 //MC_DREQ1, DMA request for USB DC ++#endif ++ ++#if (PLATFORM_TYPE==NEON) || (PLATFORM_TYPE==NEONB) ++ SPEC_GP 20,OUT,HIGH,1 //MC_DREQ0, nc ++#else ++ SPEC_GP 20,IN,HIGH,1 //MC_DREQ0, DMA request for USB HC ++#endif ++ ++ SPEC_GP 21,IN,HIGH,0 // pcmcia card detect ++ SPEC_GP 22,IN,HIGH,0 // pcmcia intr (active low) ++ ++#if (PLATFORM_TYPE==NEON) || (PLATFORM_TYPE==NEONB) ++ SPEC_GP 23,IN,LOW,0 //UCB1400 irq for NEONB, nc for NEW NEON ++#else ++ SPEC_GP 23,OUT,HIGH,0 //SSP_SCLK, nc ++#endif ++ ++#if (PLATFORM_TYPE==NEON) || (PLATFORM_TYPE==NEONB) ++ SPEC_GP 24,IN,LOW,0 //SSP_SFRM, SMSC interrupt (active high) ++#else ++ SPEC_GP 24,OUT,HIGH,0 //SSP_SFRM, nc ++#endif ++ ++ SPEC_GP 25,OUT,HIGH,0 //SSP_TXD, nc ++ SPEC_GP 26,OUT,HIGH,0 //SSP_RXD, nc ++ SPEC_GP 27,OUT,LOW,0 //SSP_EXTCLK, DC1 (SMC) ++ ++ SPEC_GP 28,IN,HIGH,1 //AC_BITCLK, ac97 bitclk ++ SPEC_GP 29,IN,HIGH,1 //AC_SDATAIN0, ac97 datain0 ++ SPEC_GP 30,OUT,HIGH,2 //AC_SDATAOUT, ac97 data out ++ SPEC_GP 31,OUT,HIGH,2 //AC_SYNC, ac97 sync ++//////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++ SPEC_GP 32,OUT,HIGH,0 //AC_SDATAIN1, wet contact ++ SPEC_GP 33,OUT,LOW,0 //MC_nCS5, green led (left), NEON:J13,pin 2 ++ SPEC_GP 34,IN,HIGH,1 //FF_RXD ++ SPEC_GP 35,IN,HIGH,1 //FF_CTS ++ SPEC_GP 36,IN,HIGH,0 //FF_DCD, MMC Card Detect ++ SPEC_GP 37,IN,HIGH,1 //FF_DSR ++ SPEC_GP 38,IN,HIGH,0 //FF_RI, MMC Write Protect, MMC/SDIO IRQ ++ SPEC_GP 39,OUT,HIGH,2 //FF_TXD ++ SPEC_GP 40,OUT,HIGH,2 //FF_DTR ++ SPEC_GP 41,OUT,HIGH,2 //FF_RTS ++ SPEC_GP 42,IN,HIGH,1 //BT_RXD ++ SPEC_GP 43,OUT,HIGH,2 //BT_TXD ++#if (PLATFORM_TYPE==NEON) ++ SPEC_GP 44,IN,HIGH,0 //BT_CTS, NEON:J12,pin 2 ++#else ++ SPEC_GP 44,OUT,HIGH,0 //BT_CTS, USB wakeup host ++#endif ++ SPEC_GP 45,OUT,LOW,0 //BT_RTS, HIGH 2 ++#if (PLATFORM_TYPE==NEON) ++ SPEC_GP 46,IN,HIGH,0 //ST_RXD, NEON:J12,pin 3 ++#else ++ SPEC_GP 46,IN,HIGH,2 //ST_RXD ++#endif ++ SPEC_GP 47,OUT,HIGH,1 //ST_TXD ++ SPEC_GP 48,OUT,HIGH,2 //MC_nPOE, pcmcia ++ SPEC_GP 49,OUT,HIGH,2 //MC_nPWE, pcmcia ++ SPEC_GP 50,OUT,HIGH,2 //MC_nPIOR, pcmcia ++ SPEC_GP 51,OUT,HIGH,2 //MC_nPIOW, pcmcia ++ SPEC_GP 52,OUT,HIGH,2 //MC_nPCE1, pcmcia ++ SPEC_GP 53,OUT,HIGH,2 //MC_nPCE2, pcmcia ++ SPEC_GP 54,OUT,HIGH,2 //MC_nPSKTSEL, nc ++ SPEC_GP 55,OUT,HIGH,2 //MC_nPREG, pcmcia attribe vs Io space ++ SPEC_GP 56,IN,HIGH,1 //MC_nPWAIT pcmcia busy ++ SPEC_GP 57,IN,HIGH,1 //MC_nIOIS16, pcmcia 16 bit wide ++ SPEC_GP 58,OUT,HIGH,ALT_LCD //LCD_LDD0, also GP_PIX_D0 ++ SPEC_GP 59,OUT,HIGH,ALT_LCD //LCD_LDD1, also GP_PIX_D1 ++ SPEC_GP 60,OUT,HIGH,ALT_LCD //LCD_LDD2, also GP_PIX_D2 ++ SPEC_GP 61,OUT,HIGH,ALT_LCD //LCD_LDD3, also GP_PIX_D3 ++ SPEC_GP 62,OUT,HIGH,ALT_LCD //LCD_LDD4, also GP_PIX_D4 ++ SPEC_GP 63,OUT,HIGH,ALT_LCD //LCD_LDD5, also GP_PIX_D5 ++ ++ ++//////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++ SPEC_GP 64,OUT,HIGH,ALT_LCD //LCD_LDD6, also GP_PIX_D6 ++ SPEC_GP 65,OUT,HIGH,ALT_LCD //LCD_LDD7, also GP_PIX_D7 ++ SPEC_GP 66,OUT,HIGH,ALT_LCD //LCD_LDD8, also GP_PIX_RESET ++ SPEC_GP 67,OUT,HIGH,ALT_LCD //LCD_LDD9 ++ SPEC_GP 68,OUT,HIGH,ALT_LCD //LCD_LDD10 ++ SPEC_GP 69,OUT,HIGH,ALT_LCD //LCD_LDD11 ++ SPEC_GP 70,OUT,HIGH,ALT_LCD //LCD_LDD12 ++ ++ SPEC_GP 71,OUT,HIGH,ALT_LCD //LCD_LDD13 ++ ++ SPEC_GP 72,OUT,HIGH,ALT_LCD //LCD_LDD14 ++ SPEC_GP 73,OUT,HIGH,ALT_LCD //LCD_LDD15 ++ SPEC_GP 74,OUT,HIGH,ALT_LCD //LCD_FCLK, also GP_PIX_READ ++ SPEC_GP 75,OUT,LCD_CS_STATE,ALT_LCD //LCD_LCLK, also GP_PIX_CS1 ++ SPEC_GP 76,OUT,LCD_CS_STATE,ALT_LCD //LCD_PCLK, also GP_PIX_CS0 ++ SPEC_GP 77,OUT,HIGH,ALT_LCD //LCD_ACBIAS, also GP_PIX_A0 ++ SPEC_GP 78,OUT,HIGH,2 //nCS2, DMA acknowledge channel 1 for USB, SMC91c111 Chip Select nDATACS ++ SPEC_GP 79,OUT,HIGH,2 //nCS3, DMA acknowledge channel 2 for USB, SM501 Chip Select ++ SPEC_GP 80,OUT,HIGH,2 //nCS4, USB chip select, SMC91c111 Chip Select ++ SPEC_GP 81,IN,LOW,0 //GND (pin F16), pxa255 has 9 extra gpios ++ SPEC_GP 82,IN,LOW,0 //GND (pin E16) ++ SPEC_GP 83,IN,LOW,0 //GND (pin E15) ++ SPEC_GP 84,IN,LOW,0 //GND (pin D16) ++ SPEC_GP 85,IN,LOW,0 //GND (pin F15) ++//to maintain compatibility with code written for the pxa250 ++//the meaning of gp86-gp89's direction bit is reversed, and alternate function is forced to the SDRAM/AC97 unit's control ++ SPEC_GP 86,IN,HIGH,0 //SDCS2 (pin G3) set as OUTPUT!!! ++ SPEC_GP 87,IN,HIGH,0 //SDCS3 (pin F2) set as OUTPUT!!! ++ SPEC_GP 88,IN,HIGH,0 //old RDnWR(pin D3) set as OUTPUT!!! ++ SPEC_GP 89,IN,LOW,0 //old ac97_reset(pin D10), set as OUTPUT!!! ++ SPEC_GP 90,IN,LOW,0 //undefined ++ SPEC_GP 91,IN,LOW,0 //undefined ++ SPEC_GP 92,IN,LOW,0 //undefined ++ SPEC_GP 93,IN,LOW,0 //undefined ++ SPEC_GP 94,IN,LOW,0 //undefined ++ SPEC_GP 95,IN,LOW,0 //undefined ++ ++// **************************************************************************** ++ CREATE_MASK_DIR DRVAL0, SPEC_, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 ++ CREATE_MASK_LEVEL SRVAL0, SPEC_, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 ++ CREATE_MASK_ALT AFVAL0, SPEC_, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 ++ CREATE_MASK_ALT AFVAL16,SPEC_,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 ++ ++ CREATE_MASK_DIR DRVAL32,SPEC_,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63 ++ CREATE_MASK_LEVEL SRVAL32,SPEC_,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63 ++ CREATE_MASK_ALT AFVAL32,SPEC_,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47 ++ CREATE_MASK_ALT AFVAL48,SPEC_,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63 ++ ++ CREATE_MASK_DIR DRVAL64,SPEC_,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95 ++ CREATE_MASK_LEVEL SRVAL64,SPEC_,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95 ++ CREATE_MASK_ALT AFVAL64,SPEC_,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79 ++ CREATE_MASK_ALT AFVAL80,SPEC_,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95 ++ +diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/pxaGpio27x.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaGpio27x.h +--- u-boot-1.1.2/include/asm-arm/arch-pxa/pxaGpio27x.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaGpio27x.h 2007-08-11 21:07:21.000000000 +0200 +@@ -0,0 +1,221 @@ ++//gpios for HALOGEN ++ ++//CP - Clock and Power Management Unit ++//MMC - Multimedia Card Controller ++//MC - Memory Controller ++//SIU - System Integration Unit ++//SSP - Synchronous Serial Port ++//AC - Audio Controller (AC97) ++//FF - Full Function UART ++//BT - Blue Tooth UART ++//ST - standard UART Port ++//LCD - LCD Controller ++ ++ SPEC_GP 0,IN,HIGH,0 // ++ SPEC_GP 1,IN,HIGH,0 //nRESET_GPIO, usb client connect interrupt ++ ++ SPEC_GP 2,IN,HIGH,0 //SYS_EN ++ ++ SPEC_GP 3,IN,HIGH,0 //PWR_SCL, Rev 1 usb client enable, float means USB Slave not ready to accept data ++ //out 1 means ready ++ ++ SPEC_GP 4,IN,HIGH,0 //PWR_SDA ++ ++ SPEC_GP 5,IN,HIGH,0 //PWR_CAP 0 ++ SPEC_GP 6,IN,HIGH,0 //PWR_CAP 1 ++ SPEC_GP 7,IN,HIGH,0 //PWR_CAP 2 ++ SPEC_GP 8,IN,HIGH,0 //PWR_CAP 3 ++ SPEC_GP 9,OUT,HIGH,0 //NC ++#if (PLATFORM_REV==1) ++ SPEC_GP 10,OUT,HIGH,0 //NC, rev 1 doesn't have MMC write protect, or card detect ++#else ++ SPEC_GP 10,IN,HIGH,0 //MMC card detect ++#endif ++ ++ SPEC_GP 11,OUT,HIGH,0 //NC ++ SPEC_GP 12,OUT,HIGH,0 //NC ++ SPEC_GP 13,OUT,HIGH,0 //NC ++ ++ SPEC_GP 14,OUT,HIGH,0 //NC ++ SPEC_GP 15,OUT,HIGH,2 //nCS1, NC ++ ++ ++ SPEC_GP 16,OUT,LOW,0 //PWM0 backlight intensity, 0 brightest ++ SPEC_GP 17,OUT,HIGH,0 //NC ++ ++ SPEC_GP 18,IN,HIGH,1 //MC_RDY, VIO_READY ++ ++ SPEC_GP 19,OUT,HIGH,0 //NC ++ ++ SPEC_GP 20,OUT,HIGH,1 //MC_DREQ0, NC ++ ++ SPEC_GP 21,OUT,HIGH,0 //NC ++ SPEC_GP 22,OUT,HIGH,0 //NC ++ ++#if (PLATFORM_REV==1) ++ SPEC_GP 23,OUT,HIGH,0 //NC ++#else ++ SPEC_GP 23,IN,HIGH,0 //rev 2 UCB1400 int ++#endif ++ ++ SPEC_GP 24,IN,LOW,0 //LAN91c111 Interrupt pin (SMSC) ++ ++ SPEC_GP 25,OUT,HIGH,0 //SSP_TXD, nc ++ SPEC_GP 26,OUT,HIGH,0 //SSP_RXD, nc ++ SPEC_GP 27,OUT,HIGH,0 //NC ++ ++ SPEC_GP 28,IN,HIGH,1 //AC_BITCLK, ac97 bitclk ++ SPEC_GP 29,IN,HIGH,1 //AC_SDATAIN0, ac97 datain0 ++ SPEC_GP 30,OUT,HIGH,2 //AC_SDATAOUT, ac97 data out ++ SPEC_GP 31,OUT,HIGH,2 //AC_SYNC, ac97 sync ++//////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++ SPEC_GP 32,OUT,HIGH,2 //MMCLK ++ SPEC_GP 33,OUT,HIGH,0 //MC_nCS5, NC ++ SPEC_GP 34,IN,HIGH,1 //(in alt 1:FF_RXD) (out alt 1:USB_P2_2) 2 input, Session Valid ++ SPEC_GP 35,IN,HIGH,0 //(in alt 1:FF_CTS) (in alt 2:USB_P2_1) 1 input, SRP Detect ++#if (PLATFORM_REV==1) ++ SPEC_GP 36,OUT,HIGH,0 //(in alt 1:FF_DCD) ++#else ++ SPEC_GP 36,IN,HIGH,0 //(in alt 1:FF_DCD) (out alt 1:USB_P2_4) 4 output Vbus Enable ++#endif ++ SPEC_GP 37,OUT,HIGH,0 //(in alt 1:FF_DSR) (out alt 1:USB_P2_8) 8 output Vbus Pulsing Enable for SRP ++ ++ SPEC_GP 38,IN,HIGH,0 //(in alt 1:FF_RI) (in alt 3:USB_P2_3) //MMC Write Protect (rev 1 is NC),// 3 input, Vbus valid 4.4 Volts ++ SPEC_GP 39,OUT,HIGH,2 //(out alt 2:FF_TXD) (out alt 1:USB_P2_6) ++ ++#if (PLATFORM_REV==1) ++ SPEC_GP 40,OUT,HIGH,2 //(out alt 2:FF_DTR) ++#else ++ SPEC_GP 40,IN,HIGH,0 //(out alt 2:FF_DTR) (in alt 3:USB_P2_5) 5 input, Vbus valid 4.0 Volts ++#endif ++ ++ SPEC_GP 41,OUT,HIGH,2 //(out alt 2:FF_RTS) (in alt 2:USB_P2_7) 7 input OTG ID ++ SPEC_GP 42,IN,HIGH,1 //BT_RXD ++ SPEC_GP 43,OUT,HIGH,2 //BT_TXD ++ SPEC_GP 44,OUT,HIGH,0 //BT_CTS, NC ++ SPEC_GP 45,OUT,LOW,0 //BT_RTS, NC ++ SPEC_GP 46,IN,HIGH,2 //ST_RXD ++ SPEC_GP 47,OUT,HIGH,1 //ST_TXD ++ SPEC_GP 48,OUT,HIGH,2 //MC_nPOE,NC ++ SPEC_GP 49,OUT,HIGH,2 //MC_nPWE ++ SPEC_GP 50,OUT,HIGH,2 //MC_nPIOR, NC ++ SPEC_GP 51,OUT,HIGH,2 //MC_nPIOW, NC ++ SPEC_GP 52,OUT,HIGH,2 //MC_nPCE1, NC ++ SPEC_GP 53,OUT,HIGH,2 //MC_nPCE2, NC ++ SPEC_GP 54,OUT,HIGH,2 //MC_nPSKTSEL, nc ++ SPEC_GP 55,OUT,HIGH,2 //MC_nPREG, NC ++ SPEC_GP 56,IN,HIGH,1 //MC_nPWAIT NC ++ SPEC_GP 57,IN,HIGH,1 //MC_nIOIS16, NC ++ SPEC_GP 58,OUT,HIGH,ALT_LCD //LCD_LDD0 ++ SPEC_GP 59,OUT,HIGH,ALT_LCD //LCD_LDD1 ++ SPEC_GP 60,OUT,HIGH,ALT_LCD //LCD_LDD2 ++ SPEC_GP 61,OUT,HIGH,ALT_LCD //LCD_LDD3 ++ SPEC_GP 62,OUT,HIGH,ALT_LCD //LCD_LDD4 ++ SPEC_GP 63,OUT,HIGH,ALT_LCD //LCD_LDD5 ++ ++ ++//////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++ SPEC_GP 64,OUT,HIGH,ALT_LCD //LCD_LDD6 ++ SPEC_GP 65,OUT,HIGH,ALT_LCD //LCD_LDD7 ++ SPEC_GP 66,OUT,HIGH,ALT_LCD //LCD_LDD8 ++ SPEC_GP 67,OUT,HIGH,ALT_LCD //LCD_LDD9 ++ SPEC_GP 68,OUT,HIGH,ALT_LCD //LCD_LDD10 ++ SPEC_GP 69,OUT,HIGH,ALT_LCD //LCD_LDD11 ++ SPEC_GP 70,OUT,HIGH,ALT_LCD //LCD_LDD12 ++ ++ SPEC_GP 71,OUT,HIGH,ALT_LCD //LCD_LDD13 ++ ++ SPEC_GP 72,OUT,HIGH,ALT_LCD //LCD_LDD14 ++ SPEC_GP 73,OUT,HIGH,ALT_LCD //LCD_LDD15 ++ SPEC_GP 74,OUT,HIGH,ALT_LCD //LCD_FCLK, NC ++ SPEC_GP 75,OUT,HIGH,ALT_LCD //LCD_LCLK ++ SPEC_GP 76,OUT,HIGH,ALT_LCD //LCD_PCLK ++ SPEC_GP 77,OUT,HIGH,ALT_LCD //LCD_ACBIAS ++ SPEC_GP 78,OUT,HIGH,2 //nCS2, SMC91c111 Chip Select nDATACS ++ SPEC_GP 79,OUT,HIGH,2 //nCS3, NC ++ SPEC_GP 80,OUT,HIGH,2 //nCS4, SMC91c111 Chip Select ++ SPEC_GP 81,OUT,HIGH,0 //NC ++ SPEC_GP 82,OUT,HIGH,0 //NC ++ SPEC_GP 83,OUT,HIGH,0 //NC ++ SPEC_GP 84,OUT,HIGH,0 //NC ++ SPEC_GP 85,OUT,HIGH,0 //NC ++ SPEC_GP 86,OUT,HIGH,ALT_LCD //LDD16 ++ SPEC_GP 87,OUT,HIGH,ALT_LCD //LDD17 ++#if (PLATFORM_REV==1) ++ SPEC_GP 88,OUT,HIGH,0 //NC ++ SPEC_GP 89,OUT,HIGH,0 //NC ++#else ++ SPEC_GP 88,IN,HIGH,1 //port 1 usb power over current ++ SPEC_GP 89,OUT,HIGH,0 //port 1 usb power enable (driver needs to enable usb power (LOW,2) ++#endif ++ ++ SPEC_GP 90,OUT,HIGH,0 //NC ++ SPEC_GP 91,OUT,HIGH,0 //NC ++ SPEC_GP 92,OUT,HIGH,1 //MMDAT ++ SPEC_GP 93,OUT,HIGH,0 //NC ++ SPEC_GP 94,OUT,HIGH,0 //NC ++ SPEC_GP 95,OUT,HIGH,0 //NC ++ SPEC_GP 96,OUT,HIGH,0 //NC ++ SPEC_GP 97,OUT,HIGH,0 //NC ++ SPEC_GP 98,OUT,HIGH,0 //NC ++ SPEC_GP 99,OUT,HIGH,0 //NC ++ SPEC_GP 100,OUT,HIGH,0 //NC ++ SPEC_GP 101,OUT,HIGH,0 //NC ++ SPEC_GP 102,OUT,HIGH,0 //NC ++ SPEC_GP 103,OUT,HIGH,0 //port 1,USB Power Enable for REV 1 board (driver needs to enable usb power (LOW,0) ++ SPEC_GP 104,OUT,HIGH,0 //NC ++ ++#if (PLATFORM_REV==1) ++ SPEC_GP 105,IN,HIGH,0 //USB Overcurrent ++#else ++ SPEC_GP 105,OUT,HIGH,0 //NC ++#endif ++ ++ SPEC_GP 106,OUT,HIGH,0 //NC ++ SPEC_GP 107,OUT,HIGH,0 //NC ++ SPEC_GP 108,OUT,HIGH,0 //NC ++ SPEC_GP 109,OUT,HIGH,1 //MMDAT 1 ++ SPEC_GP 110,OUT,HIGH,1 //MMDAT 2 ++ SPEC_GP 111,OUT,HIGH,1 //MMDAT 3 ++ SPEC_GP 112,OUT,HIGH,1 //MMCMD ++ SPEC_GP 113,OUT,HIGH,2 //AC97 Reset, NC ++ SPEC_GP 114,OUT,HIGH,0 //NC ++ SPEC_GP 115,OUT,HIGH,0 //NC ++ SPEC_GP 116,OUT,HIGH,0 //NC ++ SPEC_GP 117,OUT,HIGH,1 //SCL (I2C) ++ SPEC_GP 118,OUT,HIGH,1 //SDA (I2C) ++ SPEC_GP 119,OUT,HIGH,0 //NC ++ SPEC_GP 120,OUT,HIGH,0 //NC ++ SPEC_GP 121,IN,LOW,0 //undefined ++ SPEC_GP 122,IN,LOW,0 //undefined ++ SPEC_GP 123,IN,LOW,0 //undefined ++ SPEC_GP 124,IN,LOW,0 //undefined ++ SPEC_GP 125,IN,LOW,0 //undefined ++ SPEC_GP 126,IN,LOW,0 //undefined ++ SPEC_GP 127,IN,LOW,0 //undefined ++ ++// **************************************************************************** ++ CREATE_MASK_DIR DRVAL0, SPEC_, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 ++ CREATE_MASK_LEVEL SRVAL0, SPEC_, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 ++ CREATE_MASK_ALT AFVAL0, SPEC_, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 ++ CREATE_MASK_ALT AFVAL16,SPEC_,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 ++ ++ CREATE_MASK_DIR DRVAL32,SPEC_,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63 ++ CREATE_MASK_LEVEL SRVAL32,SPEC_,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63 ++ CREATE_MASK_ALT AFVAL32,SPEC_,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47 ++ CREATE_MASK_ALT AFVAL48,SPEC_,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63 ++ ++ CREATE_MASK_DIR DRVAL64,SPEC_,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95 ++ CREATE_MASK_LEVEL SRVAL64,SPEC_,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95 ++ CREATE_MASK_ALT AFVAL64,SPEC_,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79 ++ CREATE_MASK_ALT AFVAL80,SPEC_,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95 ++ ++ CREATE_MASK_DIR DRVAL96,SPEC_,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127 ++ CREATE_MASK_LEVEL SRVAL96,SPEC_,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127 ++ CREATE_MASK_ALT AFVAL96,SPEC_, 96, 97, 98, 99,100,101,102,103,104,105,106,107,108,109,110,111 ++ CREATE_MASK_ALT AFVAL112,SPEC_,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127 ++ +diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/pxaGpio.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaGpio.h +--- u-boot-1.1.2/include/asm-arm/arch-pxa/pxaGpio.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaGpio.h 2007-08-11 21:07:21.000000000 +0200 +@@ -0,0 +1,142 @@ ++#include "platformTypes.h" ++ ++#define IN 0 ++#define OUT 1 ++ ++#define LOW 0 ++#define HIGH 1 ++ ++ .ifdef __ARMASM ++.macro SPEC_GP gp_,dir,level,alt ++SPEC_\gp_ EQU \dir+(\level<<8)+(\alt<<16) ++.endm ++ .else ++.macro SPEC_GP gp_,dir,level,alt ++ .set SPEC_\gp_,\dir+(\level<<8)+(\alt<<16) ++.endm ++ .endif ++// ***************************************************************************************** ++.macro CREATE_MASK_DIR name,prefix,p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31 ++ .ifdef __ARMASM ++ LCLA mask ++ .endif ++ .set mask,((\prefix\p0&1)<<(\p0&0x1f)) ++ .set mask,mask | ((\prefix\p1&1)<<(\p1&0x1f)) ++ .set mask,mask | ((\prefix\p2&1)<<(\p2&0x1f)) ++ .set mask,mask | ((\prefix\p3&1)<<(\p3&0x1f)) ++ .set mask,mask | ((\prefix\p4&1)<<(\p4&0x1f)) ++ .set mask,mask | ((\prefix\p5&1)<<(\p5&0x1f)) ++ .set mask,mask | ((\prefix\p6&1)<<(\p6&0x1f)) ++ .set mask,mask | ((\prefix\p7&1)<<(\p7&0x1f)) ++ .set mask,mask | ((\prefix\p8&1)<<(\p8&0x1f)) ++ .set mask,mask | ((\prefix\p9&1)<<(\p9&0x1f)) ++ .set mask,mask | ((\prefix\p10&1)<<(\p10&0x1f)) ++ .set mask,mask | ((\prefix\p11&1)<<(\p11&0x1f)) ++ .set mask,mask | ((\prefix\p12&1)<<(\p12&0x1f)) ++ .set mask,mask | ((\prefix\p13&1)<<(\p13&0x1f)) ++ .set mask,mask | ((\prefix\p14&1)<<(\p14&0x1f)) ++ .set mask,mask | ((\prefix\p15&1)<<(\p15&0x1f)) ++ .set mask,mask | ((\prefix\p16&1)<<(\p16&0x1f)) ++ .set mask,mask | ((\prefix\p17&1)<<(\p17&0x1f)) ++ .set mask,mask | ((\prefix\p18&1)<<(\p18&0x1f)) ++ .set mask,mask | ((\prefix\p19&1)<<(\p19&0x1f)) ++ .set mask,mask | ((\prefix\p20&1)<<(\p20&0x1f)) ++ .set mask,mask | ((\prefix\p21&1)<<(\p21&0x1f)) ++ .set mask,mask | ((\prefix\p22&1)<<(\p22&0x1f)) ++ .set mask,mask | ((\prefix\p23&1)<<(\p23&0x1f)) ++ .set mask,mask | ((\prefix\p24&1)<<(\p24&0x1f)) ++ .set mask,mask | ((\prefix\p25&1)<<(\p25&0x1f)) ++ .set mask,mask | ((\prefix\p26&1)<<(\p26&0x1f)) ++ .set mask,mask | ((\prefix\p27&1)<<(\p27&0x1f)) ++ .set mask,mask | ((\prefix\p28&1)<<(\p28&0x1f)) ++ .set mask,mask | ((\prefix\p29&1)<<(\p29&0x1f)) ++ .set mask,mask | ((\prefix\p30&1)<<(\p30&0x1f)) ++ .set mask,mask | ((\prefix\p31&1)<<(\p31&0x1f)) ++ .ifdef __ARMASM ++\name EQU mask ++ .else ++ .set \name,mask ++ .endif ++.endm ++ ++.macro CREATE_MASK_LEVEL name,prefix,p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31 ++ .ifdef __ARMASM ++ LCLA mask ++ .endif ++ .set mask,(((\prefix\p0>>8)&1)<<(\p0&0x1f)) ++ .set mask,mask | (((\prefix\p1>>8)&1)<<(\p1&0x1f)) ++ .set mask,mask | (((\prefix\p2>>8)&1)<<(\p2&0x1f)) ++ .set mask,mask | (((\prefix\p3>>8)&1)<<(\p3&0x1f)) ++ .set mask,mask | (((\prefix\p4>>8)&1)<<(\p4&0x1f)) ++ .set mask,mask | (((\prefix\p5>>8)&1)<<(\p5&0x1f)) ++ .set mask,mask | (((\prefix\p6>>8)&1)<<(\p6&0x1f)) ++ .set mask,mask | (((\prefix\p7>>8)&1)<<(\p7&0x1f)) ++ .set mask,mask | (((\prefix\p8>>8)&1)<<(\p8&0x1f)) ++ .set mask,mask | (((\prefix\p9>>8)&1)<<(\p9&0x1f)) ++ .set mask,mask | (((\prefix\p10>>8)&1)<<(\p10&0x1f)) ++ .set mask,mask | (((\prefix\p11>>8)&1)<<(\p11&0x1f)) ++ .set mask,mask | (((\prefix\p12>>8)&1)<<(\p12&0x1f)) ++ .set mask,mask | (((\prefix\p13>>8)&1)<<(\p13&0x1f)) ++ .set mask,mask | (((\prefix\p14>>8)&1)<<(\p14&0x1f)) ++ .set mask,mask | (((\prefix\p15>>8)&1)<<(\p15&0x1f)) ++ .set mask,mask | (((\prefix\p16>>8)&1)<<(\p16&0x1f)) ++ .set mask,mask | (((\prefix\p17>>8)&1)<<(\p17&0x1f)) ++ .set mask,mask | (((\prefix\p18>>8)&1)<<(\p18&0x1f)) ++ .set mask,mask | (((\prefix\p19>>8)&1)<<(\p19&0x1f)) ++ .set mask,mask | (((\prefix\p20>>8)&1)<<(\p20&0x1f)) ++ .set mask,mask | (((\prefix\p21>>8)&1)<<(\p21&0x1f)) ++ .set mask,mask | (((\prefix\p22>>8)&1)<<(\p22&0x1f)) ++ .set mask,mask | (((\prefix\p23>>8)&1)<<(\p23&0x1f)) ++ .set mask,mask | (((\prefix\p24>>8)&1)<<(\p24&0x1f)) ++ .set mask,mask | (((\prefix\p25>>8)&1)<<(\p25&0x1f)) ++ .set mask,mask | (((\prefix\p26>>8)&1)<<(\p26&0x1f)) ++ .set mask,mask | (((\prefix\p27>>8)&1)<<(\p27&0x1f)) ++ .set mask,mask | (((\prefix\p28>>8)&1)<<(\p28&0x1f)) ++ .set mask,mask | (((\prefix\p29>>8)&1)<<(\p29&0x1f)) ++ .set mask,mask | (((\prefix\p30>>8)&1)<<(\p30&0x1f)) ++ .set mask,mask | (((\prefix\p31>>8)&1)<<(\p31&0x1f)) ++ .ifdef __ARMASM ++\name EQU mask ++ .else ++ .set \name,mask ++ .endif ++.endm ++ ++.macro CREATE_MASK_ALT name,prefix,p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15 ++ .ifdef __ARMASM ++ LCLA mask ++ .endif ++ .set mask,(((\prefix\p0>>16)&3)<<((\p0&0x0f)<<1)) ++ .set mask,mask | (((\prefix\p1>>16)&3)<<((\p1&0x0f)<<1)) ++ .set mask,mask | (((\prefix\p2>>16)&3)<<((\p2&0x0f)<<1)) ++ .set mask,mask | (((\prefix\p3>>16)&3)<<((\p3&0x0f)<<1)) ++ .set mask,mask | (((\prefix\p4>>16)&3)<<((\p4&0x0f)<<1)) ++ .set mask,mask | (((\prefix\p5>>16)&3)<<((\p5&0x0f)<<1)) ++ .set mask,mask | (((\prefix\p6>>16)&3)<<((\p6&0x0f)<<1)) ++ .set mask,mask | (((\prefix\p7>>16)&3)<<((\p7&0x0f)<<1)) ++ .set mask,mask | (((\prefix\p8>>16)&3)<<((\p8&0x0f)<<1)) ++ .set mask,mask | (((\prefix\p9>>16)&3)<<((\p9&0x0f)<<1)) ++ .set mask,mask | (((\prefix\p10>>16)&3)<<((\p10&0x0f)<<1)) ++ .set mask,mask | (((\prefix\p11>>16)&3)<<((\p11&0x0f)<<1)) ++ .set mask,mask | (((\prefix\p12>>16)&3)<<((\p12&0x0f)<<1)) ++ .set mask,mask | (((\prefix\p13>>16)&3)<<((\p13&0x0f)<<1)) ++ .set mask,mask | (((\prefix\p14>>16)&3)<<((\p14&0x0f)<<1)) ++ .set mask,mask | (((\prefix\p15>>16)&3)<<((\p15&0x0f)<<1)) ++ .ifdef __ARMASM ++\name EQU mask ++ .else ++ .set \name,mask ++ .endif ++.endm ++ ++#if (PLATFORM_TYPE==NEON)||(PLATFORM_TYPE==NEONB)||(PLATFORM_TYPE==BD2003)||(PLATFORM_TYPE==BOUNDARY_OLD_BOARD) ++#define ALT_LCD 2 ++#include "pxaGpio25x.h" ++#else ++#if (PLATFORM_TYPE==HALOGEN) ++#define ALT_LCD 2 ++#include "pxaGpio27x.h" ++#else ++#include "pxaGpioGame.h" ++#endif ++#endif +diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/pxaHardware.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaHardware.h +--- u-boot-1.1.2/include/asm-arm/arch-pxa/pxaHardware.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaHardware.h 2007-08-11 21:07:21.000000000 +0200 +@@ -0,0 +1,288 @@ ++//#define GPIO_BASE 0x40E00000 ++#define GPLR0 0x00 //level ++#define GPLR1 0x04 ++#define GPLR2 0x08 ++#define GPLR3 0x100 //level ++ ++#define GPDR0 0x0c //direction ++#define GPDR1 0x10 ++#define GPDR2 0x14 ++#define GPDR3 0x10c //direction ++ ++#define GPSR0 0x18 //set ++#define GPSR1 0x1C ++#define GPSR2 0x20 ++#define GPSR3 0x118 //set ++ ++#define GPCR0 0x24 //clear ++#define GPCR1 0x28 ++#define GPCR2 0x2c ++#define GPCR3 0x124 //clear ++ ++#define GRER0 0x30 //enable rising edge detect ++#define GRER1 0x34 ++#define GRER2 0x38 ++#define GRER3 0x130 //enable rising edge detect ++ ++#define GFER0 0x3C //enable falling edge detect ++#define GFER1 0x40 ++#define GFER2 0x44 ++#define GFER3 0x13C //enable falling edge detect ++ ++#define GEDR0 0x48 //edge detect status ++#define GEDR1 0x4C ++#define GEDR2 0x50 ++#define GEDR3 0x148 //edge detect status ++ ++#define GAFR0_L 0x54 //alternate function ++#define GAFR0_U 0x58 ++#define GAFR1_L 0x5C ++#define GAFR1_U 0x60 ++#define GAFR2_L 0x64 ++#define GAFR2_U 0x68 ++#define GAFR3_L 0x6c ++#define GAFR3_U 0x70 ++ ++ ++#define UART_RBR 0 //read, DLAB-0 :RECEIVE_BUFFER ++#define UART_THR 0 //write, DLAB-0 :TRANSMIT_BUFFER ++#define UART_DLL 0 //r/w, DLAB-1 :DIVISOR_LOW ++#define UART_IER 4 //r/w, DLAB-0 :INTERRUPT_ENABLE ++#define UART_DLH 4 //r/w, DLAB-1 :DIVISOR_HIGH ++ ++#define UART_IIR 8 //read :INTERRUPT_INDENTIFICATION ++#define UART_FCR 8 //write :FIFO_CONTROL ++#define UART_LCR 0x0c //r/w :LINE_CONTROL ++#define UART_MCR 0x10 //r/w :MODEM_CONTROL ++#define UART_LSR 0x14 //read :LINE_STATUS ++#define UART_MSR 0x18 //read :MODEM_STATUS ++#define UART_SPR 0x1c //r/w :SCRATCH_PAD ++#define UART_ISR 0x20 //r/w :INFRARED ++ ++//#define IC_BASE 0x40D00000 ++#define ICIP 0x00 //IRQ pending status ++#define ICMR 0x04 //interrupt controller mask ++#define ICLR 0x08 //level, 0 - irq, 1 -fiq ++#define ICFP 0x0C //FIQ pending status ++#define ICPR 0x10 //all interrupts pending, no mask ++#define ICCR 0x14 //0 - ignore ICMR in idle mode, 1 - only unmasked interrupts will awaken processor ++ ++ ++#define __SKIP 8 ++#define ICL1_GPIO0 (8 - __SKIP) ++#define ICL1_GPIO1 (9 - __SKIP) ++#define ICL1_GPIO2_80 (10 - __SKIP) ++#define ICL1_USB (11 - __SKIP) ++#define ICL1_PMU (12 - __SKIP) ++#define ICL1_I2S (13 - __SKIP) ++#define ICL1_AC97 (14 - __SKIP) ++#define ICL1_LCD (17 - __SKIP) ++#define ICL1_I2C (18 - __SKIP) ++#define ICL1_ICP (19 - __SKIP) ++#define ICL1_STUART (20 - __SKIP) ++#define ICL1_BTUART (21 - __SKIP) ++#define ICL1_FFUART (22 - __SKIP) ++#define ICL1_MMC (23 - __SKIP) ++#define ICL1_SSP (24 - __SKIP) ++#define ICL1_DMA (25 - __SKIP) ++#define ICL1_OS_TIMER0 (26 - __SKIP) ++#define ICL1_OS_TIMER1 (27 - __SKIP) ++#define ICL1_OS_TIMER2 (28 - __SKIP) ++#define ICL1_OS_TIMER3 (29 - __SKIP) ++#define ICL1_RTC_TICK (30 - __SKIP) ++#define ICL1_RTC_ALARM_MATCH (31 - __SKIP) ++ ++//#define OS_TIMER_BASE 0x40a00000 ++#define OSMR0 0x00 ++#define OSMR1 0x04 ++#define OSMR2 0x08 ++#define OSMR3 0x0c ++#define OSCR 0x10 //OS timer Count register, increments at 3.6864 Mhz ++#define OSSR 0x14 //OS timer Status Register ++#define OWER 0x18 //OS timer Watchdog Match enable register ++#define OIER 0x1c ++ ++//3686400 ticks/seconds = 3.6864 ticks/usec = 1 tick/.271267361111 usec ++#define TICK_PER_USEC_WHOLE 3 ++#define TICK_PER_USEC_FRAC 0xAFB7E910 ++////////////////////////////////////////////////////////////////////////////////////////// ++ ++//#define PWR_MANAGER_BASE 0x40F00000 ++#define PMCR 0 ++#define PSSR 4 ++#define PSPR 8 ++#define PWER 0x0c ++#define PRER 0x10 ++#define PFER 0x14 ++#define PEDR 0x18 ++#define PCFR 0x1c ++#define PGSR0 0x20 ++#define PGSR1 0x24 ++#define PGSR2 0x28 ++#define RCSR 0x30 ++ ++#define PSSR_MASK 0x37 ++#define RCSR_MASK 0x0f ++#define RCSR_SLEEP_RESET 4 ++ ++//#define CLK_MANAGER_BASE 0x41300000 ++#define CCCR 0 ++#define CKEN 4 ++#define OSCC 8 ++ ++//#define MEMORY_CONTROL_BASE 0x48000000 ++#define MDCNFG 0 ++#define MDREFR 4 ++#define MSC0 8 ++#define MSC1 0x0c ++#define MSC2 0x10 ++#define MECR 0x14 ++#define SXCNFG 0x1c ++#define SXMRS 0x24 ++#define MCMEM0 0x28 ++#define MCMEM1 0x2c ++#define MCATT0 0x30 ++#define MCATT1 0x34 ++#define MCIO0 0x38 ++#define MCIO1 0x3c ++#define MDMRS 0x40 ++#define BOOT_DEF 0x44 ++ ++ ++//#define LCD_CONTROL_BASE 0x44000000 ++#define LCD_CR0 0 //master enable last ++#define LCD_CR1 4 ++#define LCD_CR2 8 ++#define LCD_CR3 0x0c ++#define LCD_FBR0 0x20 //Frame branch register ++#define LCD_FBR1 0x24 //Frame branch register ++#define LCD_SR 0x38 ++#define LCD_INT_ID 0x3c ++#define LCD_TMEDS 0x40 //TMED RGB seed ++#define LCD_TMEDC 0x44 //TMED control ++#define LCD_FDADR0 0x200 //frame descriptor address register ++#define LCD_FDADR1 0x210 //frame descriptor address register ++ ++#define LCD_FSADR0 0x204 //frame source address register ++#define LCD_FSADR1 0x214 //frame source address register ++ ++#define LCD_FIDR0 0x208 //frame ID register ++#define LCD_FIDR1 0x218 //frame ID register ++ ++#define LCD_DCMD0 0x20c //dma command ++#define LCD_DCMD1 0x21c //dma command ++ ++#define CRO_LDDALT 26 //LDDALT ;0 selects RGB 555, 1 selects RGB 565 ++#define CRO_OUC 25 //OUC ;0 underlays, 1 overlays ++#define CR0_CMDIM 24 //CMDIM ;command interrupt mask, 0 - enabled, 1 disabled ++#define CR0_RDSTM 23 //RDSTM ;read status interrupt mask, 0 - enabled, 1 disabled ++#define CR0_LCDT 22 //LCDT ;LCD Panel Type, 1 - internal frame buffer ++#define CR0_IM_OUTPUT_FIFO_UNDERRUN 21 //OUM IM stands for Interrupt Mask ++#define CR0_IM_BRANCH 20 //BSM0 ++#define CR0_PALETTE_DMA_REQUEST_DELAY 12 //PDD 8 bit field, 0-255 ++#define CR0_IM_LCD_QUICK_DISABLE 11 //QDM ++#define CR0_DISABLE 10 //DIS ++#define CR0_DOUBLE_PIXEL_DATA 9 //DPD ++#define CR0_ACTIVE_SELECT 7 //PAS ++#define CR0_IM_END_OF_FRAME 6 //EOFM0 ++#define CR0_IM_INPUT_FIFO_UNDERRUN 5 //IUM ++#define CR0_IM_START_OF_FRAME 4 //SOFM0 ++#define CR0_IM_DISABLE_DONE 3 //LDM ++#define CR0_DUAL_PANEL_SELECT 2 //SDS ++#define CR0_MONOCHROME_SELECT 1 //CMS ++#define CR0_ENABLE 0 //ENB ++ ++ ++ ++ ++#define CR1_BEGINNING_OF_LINE_WAIT 24 //8 bit field +1 ++#define CR1_END_OF_LINE_WAIT 16 //8 bit field +1 ++#define CR1_HORIZONTAL_SYNC_PULSE_WIDTH 10 //6 bit field +1 ++#define CR1_PIXELS_PER_LINE 0 //10 bit field +1 ++ ++ ++ ++#define CR2_BEGINNING_OF_FRAME_WAIT 24 //8 bit field ++#define CR2_END_OF_FRAME_WAIT 16 //8 bit field ++#define CR2_VERTICAL_SYNC_PULSE_WIDTH 10 //6 bit field +1 ++#define CR2_LINES_PER_PANEL 0 //10 bit field +1 ++ ++ ++#define CR3_PDFOR 30 ++#define CR3_DOUBLE_PCLK 27 ++#define CR3_BITS_PER_PIXEL 24 //3 bit field ++//0 - 1 bit ++//1 - 2 bits ++//2 - 4 bits ++//3 - 8 bits ++//4 - 16 bits, ++//5-7 reserved ++#define CR3_BIAS_POLARITY 23 ++#define CR3_PCLK_POLARITY 22 ++#define CR3_LCLK_POLARITY 21 ++#define CR3_FCLK_POLARITY 20 ++#define CR3_API 16 //4 bits field, ac bias transitions per interrupt, 0 disable ++#define CR3_ACBIAS_TOGGLE 8 //8 bit field +1 ++#define CR3_PCLK_DIVISOR 0 //8 bit field +1 ++ ++ ++ ++#define FBR_BRANCH_INT 1 ++#define FBR_BRANCH 0 ++ ++ ++#define SR_MISSED_INT 10 ++#define SR_BRANCH_INT 9 ++#define SR_END_OF_FRAME_INT 8 ++#define SR_QUICK_DISABLE_INT 7 ++#define SR_OUTPUT_FIFO_UNDERRUN 6 ++#define SR_INPUT_FIFO_UNDERRUN0 5 ++#define SR_INPUT_FIFO_UNDERRUN1 4 ++#define SR_ACBIAS_COUNT_INT 3 ++#define SR_BUS_ERROR 2 ++#define SR_START_OF_FRAME 1 ++#define SR_DISABLE_DONE 0 ++ ++#define TMEDS_BLUE 16 //8 bit field ++#define TMEDS_GREEN 8 //8 bit field ++#define TMEDS_RED 0 //8 bit field ++ ++ ++#define TMEDC_MATRIX2_SELECT 14 ++#define TMEDC_RESERVED 12 //2 bit field ++#define TMEDC_HORIZONTAL_BEAT_SUPPRESSION 8 //4 bit field ++#define TMEDC_VERTICAL_BEAT_SUPPRESSION 4 //4 bit field ++#define TMEDC_FRAME_NUMBER_ADJUST_EN 3 ++#define TMEDC_COLOR_OFFSET_ADJUST_EN 2 ++#define TMEDC_FRAME_NUMBER_ADJUST_MATRIX2 1 ++#define TMEDC_COLOR_OFFSET_ADJUST_MATRIX2 0 ++ ++ ++#define DCMD_PALETTE 26 ++#define DCMD_START_OF_FRAME_INTERRUPT 22 ++#define DCMD_END_OF_FRAME_INTERRUPT 21 ++#define DCMD_LENGTH 0 //21 bit field ++ ++ ++#define FDESC_FDADR 0 ++#define FDESC_FSADR 4 ++#define FDESC_FIDR 8 ++#define FDESC_DCMD 0x0c ++ ++#define PSR_MODE_MASK 0x1f ++#define PSR_MODE_USER 0x10 ++#define PSR_MODE_FIQ 0x11 ++#define PSR_MODE_IRQ 0x12 ++#define PSR_MODE_SVC 0x13 ++#define PSR_MODE_DEBUG 0x15 ++#define PSR_MODE_ABORT 0x17 ++#define PSR_MODE_UNDEF 0x1b ++#define PSR_MODE_SYSTEM 0x1f ++#define PSR_NOINTS_MASK 0xc0 ++ ++#define FUNC_REQ_GL 0 ++#define FUNC_REQ_DLW 1 ++#define FUNC_REQ_GAME 2 //not specifically referenced ++#define FUNC_REQ_MAC 3 ++#define FUNC_REQ_WAKEUP 4 ++#define FUNC_REQ_PIC 5 +diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/pxaLcd2.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaLcd2.h +--- u-boot-1.1.2/include/asm-arm/arch-pxa/pxaLcd2.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaLcd2.h 2007-08-11 21:07:21.000000000 +0200 +@@ -0,0 +1,78 @@ ++#include "pxaLcd.h" ++#define DA320X240 0 ++#define DA640X240 1 ++#define DA800X480 2 ++#define DA640X480 3 ++#define DA240X320 4 ++#define DA800X600 5 ++#define DA1024X768 6 ++#define DP480X320 7 ++#define DP320X240 8 ++#define DL122X32 9 ++#define UNKNOWN 0xcc ++ ++#ifdef __ARMASM ++ GBLS DEF_P ++#endif ++ ++#if DISPLAY_TYPE==DA320X240 //5.7 inch display ++#define DEF_P DA320X240_P ++#define DEF_DISPLAY_INDEX 0 ++#else ++#if DISPLAY_TYPE==DA640X240 //6.2 inch display ++#define DEF_P DA640X240_P ++#define DEF_DISPLAY_INDEX 1 ++#else ++#if DISPLAY_TYPE==DA800X480 //7 or 9 inch display ++#define DEF_P DA800X480_P ++#define DEF_DISPLAY_INDEX 2 ++#else ++#if DISPLAY_TYPE==DA640X480 //10.4 inch display ++#define DEF_P DA640X480_P ++#define DEF_DISPLAY_INDEX 3 ++#else ++#if DISPLAY_TYPE==DA240X320 //3.5 inch display ++#define DEF_P DA240X320_P ++#define DEF_DISPLAY_INDEX 4 ++#else ++#if DISPLAY_TYPE==DA800X600 ++#define DEF_P DA800X600_P ++#define DEF_DISPLAY_INDEX 5 ++#else ++#if DISPLAY_TYPE==DA1024X768 ++#define DEF_P DA1024X768_P ++#define DEF_DISPLAY_INDEX 6 ++#else ++#if DISPLAY_TYPE==DP480X320 //5.7 inch display ++#define DEF_P DP480X320_P ++#define DEF_DISPLAY_INDEX 7 ++#else ++#if DISPLAY_TYPE==DP320X240 //5.7 inch display ++#define DEF_P DP320X240_P ++#define DEF_DISPLAY_INDEX 8 ++#else ++#if DISPLAY_TYPE==DL122X32 ++#define DEF_P DL122X32_P ++#define DEF_DISPLAY_INDEX 9 ++#else ++#if DISPLAY_TYPE==UNKNOWN ++#define DEF_P DA320X240_P ++#define DEF_DISPLAY_INDEX 0xcc ++ ++#else ++#define DEF_P DA320X240_P ++#define DEF_DISPLAY_INDEX 0 ++#warning "No display selected, defaulting to DA320X240" ++ ++#endif //0xcc ++#endif //9 ++#endif //8 ++#endif //7 ++#endif //6 ++#endif //5 ++#endif //4 ++#endif //3 ++#endif //2 ++#endif //1 ++#endif //0 ++ +diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/pxaLcd.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaLcd.h +--- u-boot-1.1.2/include/asm-arm/arch-pxa/pxaLcd.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaLcd.h 2007-08-11 21:07:21.000000000 +0200 +@@ -0,0 +1,79 @@ ++#include "platformTypes.h" ++#define WINCE 1 ++#define LINUX 2 ++#define GAME 3 ++ ++#define PXAFB_BPP 16 ++ ++#define LCD_PANEL 0 ++#define CRT 1 ++ ++//pixel clock frequency = LCLK / (2*(PCD+1)) ++#if (PLATFORM_TYPE==HALOGEN) ++#define __BPP 18 ++#define BPP_FORMAT 6 ++#define PDFOR 3 ++#define BYTES_PER_PIXEL 3 ++#else ++#define __BPP 16 ++#define BPP_FORMAT 4 ++#define PDFOR 0 ++#define BYTES_PER_PIXEL 2 ++#endif ++ ++// **************************************************************************** ++// This is where different display settings reside ++// xres,xsyncWidth,xbegin,xend, yres,ysyncWidth,ybegin,yend, enable,unscramble,rotate,active,bpp,clkdiv,type ++//#define DA320X240_P 320, 64, 34, 1, 240, 20, 8, 3, 1,0,0,1,PXAFB_BPP,4,LCD_PANEL //0 ++#define DA320X240_P 320, 64, 34, 11, 240, 5, 8, 3, 1,0,0,1,PXAFB_BPP,4,LCD_PANEL //0 ++ ++#define DA640X240_P 640, 64, 34, 1, 240, 20, 8, 3, 1,1,0,1,PXAFB_BPP,2,LCD_PANEL //1 ++#define DA800X480_P 800, 64, 34, 1, 480, 20, 8, 3, 1,1,0,1,PXAFB_BPP,2,LCD_PANEL //2 ++#define DA640X480_P 640, 64, 34,105, 480, 20, 8,14, 1,1,0,1,PXAFB_BPP,2,LCD_PANEL //3 ++#define DA240X320_P 240, 64, 34, 1, 320, 20, 8, 3, 1,0,1,1,PXAFB_BPP,5,LCD_PANEL //4 ++#define DA800X600_P 800,0x9b,0x31,0x69, 600,0x04,0x01,0x17, 1,1,0,1,PXAFB_BPP,2,CRT //5 ++//#define DA1024X768_P 1024,0xc8,0x55,0xb4, 768,0x06,0x0b,0x1d, 1,1,0,1,PXAFB_BPP,2,CRT //6 ++//#define DA1024X768_P 1024,0xe4,0x3c,0x70, 768,0x0c,0x0b,0x20, 1,1,0,1,PXAFB_BPP,2,CRT //6 ++#define DA1024X768_P 1024,0xe4,0x3c,0x70, 768,0x0c,0x0b,0x20, 1,1,0,1,PXAFB_BPP,2,LCD_PANEL //6 ++#define DP480X320_P 480, 64, 34, 1, 320,20,8,3, 1,0,0,0,PXAFB_BPP,3,LCD_PANEL //7 ++#define DP320X240_P 320, 64, 34, 1, 240,20,8,3, 1,0,0,0,PXAFB_BPP,4,LCD_PANEL //8 ++#define DL122X32_P 320, 64, 34, 1, 240,20,8,3, 0,0,0,0,PXAFB_BPP,4,0 //9 ++ ++// ******************************************************************************** ++#if (PLATFORM_TYPE==BOUNDARY_OLD_BOARD) ++#define MOTHERBOARD_SCRAMBLED ++#endif ++ ++//#define CONFIG_UNSCRAMBLE_LCD ++#ifdef CONFIG_UNSCRAMBLE_LCD ++#if 1 //FL_ACTIVE(DEF_P) //passive cannot swap pin order ++#ifdef MOTHERBOARD_SCRAMBLED ++ ++#ifndef DAUGHTERBOARD_UNSCRAMBLE ++#define LCD_REORDER_BLUE 15,14, 8, 7, 6 ++#define LCD_REORDER_GREEN 13,12,11, 5, 4, 3 ++#define LCD_REORDER_RED 10, 9, 2, 1, 0 ++#endif ++ ++#else ++//motherboard is NOT scrambled ++#ifdef DAUGHTERBOARD_UNSCRAMBLE ++#define LCD_REORDER_BLUE 15,14,13,10, 9 ++#define LCD_REORDER_GREEN 8, 4, 3, 2, 12, 11 ++#define LCD_REORDER_RED 7, 6, 5, 1, 0 ++#endif ++#endif //#ifdef MOTHERBOARD_SCRAMBLED ++#endif //#if FL_ACTIVE(DEF_P) ++#endif //#ifdef CONFIG_UNSCRAMBLE_LCD ++ ++#ifndef LCD_REORDER_BLUE ++#if (BYTES_PER_PIXEL==2) ++#define LCD_REORDER_BLUE 0,1,2,3,4 ++#define LCD_REORDER_GREEN 5,6,7,8,9,10 ++#define LCD_REORDER_RED 11,12,13,14,15 ++#else ++#define LCD_REORDER_BLUE 0,1,2,3,4,5 ++#define LCD_REORDER_GREEN 6,7,8,9,10,11 ++#define LCD_REORDER_RED 12,13,14,15,16,17 ++#endif ++#endif +diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/pxaMacro2.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaMacro2.h +--- u-boot-1.1.2/include/asm-arm/arch-pxa/pxaMacro2.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaMacro2.h 2007-08-11 21:07:21.000000000 +0200 +@@ -0,0 +1,540 @@ ++#include "pxaMacro.h" ++// ************************************************************************************************ ++// ************************************************************************************************ ++ ++//In: c-0 try 64meg, c-1 try 32meg ++// or if 16 bit mode ++// c-0 try 32meg, c-1 try 16meg ++//Out: z-0 if 16 bit mode ++.macro InitRam rBase,rTemp ++ BigMov \rBase,MEMORY_CONTROL_BASE ++ ldr \rTemp,[\rBase,#BOOT_DEF] ++ tst \rTemp,#1 //bit 0 - 1 means 16 bit mode ++ BigMov \rTemp,M64_MDCNFG_VAL ++ BigEor2Cs \rTemp,(M64_MDCNFG_VAL)^(M32_MDCNFG_VAL) ++#if (!(PLATFORM_TYPE==NEONB)) && (!(PLATFORM_TYPE==HALOGEN)) ++ BigOrr2Ne \rTemp,(1<<2) //select 16 bit width ++#endif ++ str \rTemp,[\rBase,#MDCNFG] ++ ++ mov \rTemp,#0 ++ nop //pxa270 may need this for some reason, depending upon instruction alignment ++ str \rTemp,[\rBase,#MDMRS] ++ ++ ++ BigMov \rTemp,M64_MDREFR_VAL ++ BigEor2Cs \rTemp,(M64_MDREFR_VAL)^(M32_MDREFR_VAL) ++ str \rTemp,[\rBase,#MDREFR] ++.endm ++ ++ ++//In: z-1 - c-0 try 64meg, c-1 try 32meg ++// z-0 - c-0 try 32meg, c-1 try 16meg ++//out: rTemp - memory size ++.macro CheckRam rBase,rTemp,rTemp2 ++ // Issue read requests to disabled bank to start refresh ++ BigMov \rBase,MEM_START+0x0C000000 ++ ldr \rTemp, [\rBase] ++ mov \rTemp,#M32_MEM_SIZE ++ movcc \rTemp,#M64_MEM_SIZE ++#if (!(PLATFORM_TYPE==NEONB)) && (!(PLATFORM_TYPE==HALOGEN)) ++ movne \rTemp,\rTemp,LSR #1 ++#endif ++ BigMov \rBase,MEM_START ++#if 1 ++ mov \rTemp2,#0x24<<2 //0x24 seems to work, but keep it safe ++81: sub \rTemp2,\rTemp2,#1 ++ str \rTemp2,[\rBase] ++ movs \rTemp2,\rTemp2 //don't affect carry flag ++ bne 81b ++#endif ++ str \rTemp,[\rBase] ++ str \rBase,[\rBase,\rTemp,LSR #1] ++ ldr \rTemp2,[\rBase] ++ movcs \rTemp2,\rTemp //if 2nd time through, force match ++ cmp \rTemp2,\rTemp ++#if 1 ++ strne \rTemp2,[\rBase,#4] ++// teq \rTemp2,\rTemp2 ++#endif ++.endm ++ ++#define tEHEL 0 //R14 ++#define tAPA 3 //r15 25ns/10ns rounded up ++ ++#define RDFSelect 13 //R2 : tAVQV : 110ns/10ns = 11; 11-1=10=RDF ++//#define RDFSelect 10 //R2 : tAVQV : 110ns/10ns = 11; 11-1=10=RDF ++ //0-11 map to 0-11 ++ //12 -> 13, 13 ->15, 14->18, 15->23 ++ ++//#if (PLATFORM_TYPE==GAME_CONTROLLER_PLAITED_A1) ++#if (PLATFORM_TYPE==GAME_CONTROLLER_PLAITED_A1)||(PLATFORM_TYPE==GAME_CONTROLLER)||(PLATFORM_TYPE==GAME_WITH_SMC) ++#define BurstSelect 0 //if plaited bug, burst mode will no longer work. ++#else ++#define BurstSelect 2 //0->nonburst,1->SRAM,2->burst of4, 3->burst of 8, 4->variable latency i/o ++#endif ++ ++ ++#if (PLATFORM_TYPE==NEONB) ++//access time 70ns, 25ns after CS data becomes valid ++// RRR RDN RDF RBW RTX ++// gap between Address to ++// 1-fast chip selects data valid ++// 0-slow recovery 2nd burst access 1st access delay 16-bit bus non-burst(0), sram(1), 4cycle(2), 8cycle(3), VLIO(4) ++#define CS0_MSC (1<<15)+ (1<<12)+ (7<<8)+ ((7-1)<<4)+ 0 ++#define CS1_MSC (1<<15)+(((tEHEL+1)>>1)<<12)+((tAPA-1)<<8)+ (RDFSelect<<4)+ (BurstSelect) //fast device ++#else ++#define CS0_MSC (1<<15)+(((tEHEL+1)>>1)<<12)+((tAPA-1)<<8)+ (RDFSelect<<4)+ (BurstSelect) //fast device ++#define CS1_MSC (1<<15)+ (3<<12)+ (2<<8)+ ((3-1)<<4)+ (1<<3) + 4 //SMC chip ++//#define CS1_MSC (1<<15)+ (6<<12)+ ((11-1)<<8)+ ((4-1)<<4)+ (1<<3) + 4 //SMC chip ++#endif ++ ++.macro InitCS0_CS1 rBase,rTemp ++ BigMov \rBase,MEMORY_CONTROL_BASE ++ ldr \rTemp,[\rBase,#BOOT_DEF] ++ tst \rTemp,#1 //bit 0 - 1 means 16 bit mode ++ BigMov \rTemp,(CS0_MSC)|((CS1_MSC)<<16) ++/////// BigMov \rTemp,0x7ff07ff0 ++ orrne \rTemp,\rTemp,#1<<3 //16 bit bus ++ str \rTemp,[\rBase,#MSC0] ++.endm ++ ++ ++.macro InitMemory rBase,rTemp,rTemp2 ++ cmp pc,#MEM_START ++ bcs 92f //exit if running from ram ++#if 0 //1 to force smaller memory ++ subs \rTemp,\rTemp,\rTemp //set carry flag ++#endif ++ ++1: ++ InitRam \rBase, \rTemp //out: \rBase - MEMORY_CONTROL_BASE ++ ++#if (PLATFORM_TYPE==BOUNDARY_OLD_BOARD) ++#define CHIP_MODE 0 //don't use VIO_READY ++#else ++#define CHIP_MODE 4 //gp18 is VIO_READY ++#endif ++ ++// RRR RDN RDF RBW RTX ++// gap between Address to ++// 1-fast chip selects data valid ++// 0-slow recovery 2nd burst access 1st access delay 16-bit bus non-burst(0), sram(1), 4cycle(2), 8cycle(3), VLIO(4) ++#if 1 ++#define CS2_MSC (1<<15)+ (4<<12)+ ((6-2)<<8)+ ((4-1)<<4)+ (1<<3) + CHIP_MODE //for USB dma ++//#define CS2_MSC (1<<15)+ (7<<12)+ ((16-1)<<8)+ ((16-1)<<4)+ (1<<3) + CHIP_MODE //for USB dma ++ ++// vlio min 2 vlio min 3 ++#if (PLATFORM_TYPE==NEON) || (PLATFORM_TYPE==NEONB) ++#define CS3_MSC (1<<15)+ (1<<12)+ (2<<8)+ ((4-1)<<4)+ (0<<3) + 4 //SM501 ++#define CS4_MSC (1<<15)+ (3<<12)+ (2<<8)+ ((4-1)<<4)+ (0<<3) + 4 //SMC chip ++#else ++#if (PLATFORM_TYPE==HALOGEN) ++#define CS3_MSC (1<<15)+ (1<<12)+ (2<<8)+ ((4-1)<<4)+ (0<<3) + 4 //NC ++#define CS4_MSC (1<<15)+ (3<<12)+ (2<<8)+ ((5-1)<<4)+ (0<<3) + 4 //SMC chip ++#else ++#define CS3_MSC (1<<15)+ (4<<12)+ ((6-2)<<8)+ ((4-1)<<4)+ (1<<3) + CHIP_MODE //for USB dma ++//#define CS3_MSC (1<<15)+ (7<<12)+ ((16-1)<<8)+ ((16-1)<<4)+ (1<<3) + CHIP_MODE //for USB dma ++#define CS4_MSC (1<<15)+ (6<<12)+ ((11-1)<<8)+ ((4-1)<<4)+ (1<<3) + CHIP_MODE //for USB IO ++#endif ++#endif ++ ++#define CS5_MSC (0<<15)+ (7<<12)+ ((8-1)<<8)+ ((8-1)<<4)+ (1<<3) + (0) //for USB IO delay after CMD write ++#else ++#define CS2_MSC (1<<15)+ (7<<12)+ ((16-1)<<8)+ ((16-1)<<4)+ (1<<3) + CHIP_MODE //for USB dma ++#define CS3_MSC (1<<15)+ (7<<12)+ ((16-1)<<8)+ ((16-1)<<4)+ (1<<3) + CHIP_MODE //for USB dma ++#define CS4_MSC (1<<15)+ (7<<12)+ ((16-1)<<8)+ ((16-1)<<4)+ (1<<3) + CHIP_MODE //for USB IO ++#define CS5_MSC (0<<15)+ (7<<12)+ ((16-1)<<8)+ ((16-1)<<4)+ (1<<3) + (0) //for USB IO delay after CMD write ++#endif ++ BigMov \rTemp,(CS2_MSC)|((CS3_MSC)<<16) ++ str \rTemp,[\rBase,#MSC1] ++ BigMov \rTemp,(CS4_MSC)|((CS5_MSC)<<16) ++ str \rTemp,[\rBase,#MSC2] ++ ++ ++ ++#define PCMCIA_MEM_SETUP_ADDRESS 5 //0-127 ++#define PCMCIA_MEM_COMMAND_CODE 3 //0-31 ++#define PCMCIA_MEM_HOLD_ADDRESS 2 //0-63 ++ BigMov \rTemp,(PCMCIA_MEM_HOLD_ADDRESS<<14)+(PCMCIA_MEM_COMMAND_CODE<<7)+(PCMCIA_MEM_SETUP_ADDRESS<<0) ++ str \rTemp,[\rBase,#MCMEM0] ++ str \rTemp,[\rBase,#MCMEM1] ++#define PCMCIA_ATT_SETUP_ADDRESS 5 //0-127 ++#define PCMCIA_ATT_COMMAND_CODE 3 //0-31 ++#define PCMCIA_ATT_HOLD_ADDRESS 2 //0-63 ++ BigMov \rTemp,(PCMCIA_ATT_HOLD_ADDRESS<<14)+(PCMCIA_ATT_COMMAND_CODE<<7)+(PCMCIA_ATT_SETUP_ADDRESS<<0) ++ str \rTemp,[\rBase,#MCATT0] ++ str \rTemp,[\rBase,#MCATT1] ++#define PCMCIA_IO_SETUP_ADDRESS 5 //0-127 ++#define PCMCIA_IO_COMMAND_CODE 3 //0-31 ++#define PCMCIA_IO_HOLD_ADDRESS 2 //0-63 ++ BigMov \rTemp,(PCMCIA_IO_HOLD_ADDRESS<<14)+(PCMCIA_IO_COMMAND_CODE<<7)+(PCMCIA_IO_SETUP_ADDRESS<<0) ++ str \rTemp,[\rBase,#MCIO0] ++ str \rTemp,[\rBase,#MCIO1] ++ mov \rTemp,#2 ++ str \rTemp,[\rBase,#MECR] ++ ++ CheckRam \rBase, \rTemp, \rTemp2 ++ cmpne \rTemp,#0x0 //set carry flag, keep z-0 (memory size!=0) ++ bne 1b ++92: ++.endm ++ ++// ******************************************************************************************* ++// ******************************************************************************************* ++// ******************************************************************************************* ++// ******************************************************************************************* ++#define CKEN_PWM0 0 ++#define CKEN_PWM1 1 ++#define CKEN_AC97 2 ++#define CKEN_SSP 3 ++#define CKEN_HWUART 4 ++#define CKEN_STUART 5 ++#define CKEN_FFUART 6 ++#define CKEN_BTUART 7 ++#define CKEN_I2S 8 ++#define CKEN_USB 11 ++#define CKEN_MMC 12 ++#define CKEN_FICP 13 ++#define CKEN_I2C 14 ++#define CKEN_LCD 16 ++ ++#if (PLATFORM_TYPE==NEON) || (PLATFORM_TYPE==BD2003) || (PLATFORM_TYPE==BOUNDARY_OLD_BOARD) || (PLATFORM_TYPE==OLD_GAME_CONTROLLER) || (PLATFORM_TYPE==HALOGEN) ++#define __ENABLED_BTUART_MASK (1< 2 clks ++ // tRAS_clk= 4.47899 -> 5 clks ++ // tRC_clk= 6.46966 -> 7 clks ++ //2 : *32 = 8.47711 ns, 117.96 MHz ++ // tRP_clk = tRCD_clk= 2.35929 -> 3 clks ++ // tRAS_clk=5.30841 -> 6 ++ // tRC_clk =7.66771 -> 8 clks ++ //3 : *36 = 7.5352 ns, 132.71 MHz ++ // tRP_clk = tRCD_clk= 2.65421 -> 3 clks ++ // tRAS_clk=5.97197 -> 6 ++ // tRC_clk = 8.62618 -> 9 clks ++ //4 : *40 = 6.78168ns, 147.46 MHz ++ // tRP_clk = tRCD_clk= 2.94912 -> 3 clks ++ // tRAS_clk=6.63522 -> 7 ++ // tRC_clk = 9.58465 -> 10 clks ++ //5 : *45 = 6.02816ns, 165.89 MHz ++ // tRP_clk = tRCD_clk= 3.31776 -> 4 clks ++ // tRAS_clk=7.46496 -> 8 ++ // tRC_clk = 10.7827 -> 11 clks ++//MSelect ++//1 : *1 ++//2 : *2 ++ ++//NSelect ++//2 : *1; ++//3 : *1.5; ++//4 : *2; ++//6 : *3 ++ ++#if (CPU_CLOCK==100) ++#define MSelect 1 //1 : *1 100MHz ++#define NSelect 4 //4 : *2; turbo 200 MHZ ++#define FCS_MASK 2 // turbo off ++#else ++#if (CPU_CLOCK==200) ++#define MSelect 2 //2 : *2 200 MHz ++#define NSelect 3 //3 : *1.5; turbo 300 MHZ ++#define FCS_MASK 2 // turbo off ++#else ++#if (CPU_CLOCK==300) ++#define MSelect 2 //2 : *2 200 MHz ++#define NSelect 3 //3 : *1.5; turbo 300 MHZ ++#define FCS_MASK 3 // turbo on ++#else ++#if (CPU_CLOCK==400) ++ ++#if 0 //only pxa255 runs with 200Mhz internal bus, pxa250 doesn't ++#define MSelect 2 //2 : *2 200 MHz ++#define NSelect 4 //4 : *2; turbo 400 MHZ ++#define FCS_MASK 3 // turbo on ++#else ++#define MSelect 3 //2 : *4 400 MHz ++#define NSelect 2 //4 : *1; turbo 400 MHZ ++#define FCS_MASK 2 // turbo off ++#endif ++ ++#else ++//////#WARNING CPU_CLOCK selection not made ++#endif ++#endif ++#endif ++#endif ++ ++ BigMov \rTemp,(NSelect<<7)+(MSelect<<5)+(LSelect) ++ str \rTemp,[\rBase,#CCCR] ++ ++ BigMov \rTemp,(1<>8) ++ str \rTemp,[\rBase,#UART_DLH] ++ ++ mov \rTemp,#3 //8-bit characters ++ str \rTemp,[\rBase,#UART_LCR] ++ ++ mov \rTemp,#0xc1 //enable fifo, 32 byte level ++ str \rTemp,[\rBase,#UART_FCR] ++ ++ mov \rTemp,#0x40 //UUE- UART unit enable ++ str \rTemp,[\rBase,#UART_IER] ++.endm ++.macro InitGPIO rBase,rTemp ++ BigMov \rBase,GPIO_BASE ++ ++ BigMov \rTemp,~SRVAL0 ++ str \rTemp,[\rBase,#GPCR0] ++ mvn \rTemp,\rTemp ++ str \rTemp,[\rBase,#GPSR0] ++ ++ BigMov \rTemp,~SRVAL32 ++ str \rTemp,[\rBase,#GPCR1] ++ mvn \rTemp,\rTemp ++ str \rTemp,[\rBase,#GPSR1] ++ ++ BigMov \rTemp,~SRVAL64 ++ str \rTemp,[\rBase,#GPCR2] ++ mvn \rTemp,\rTemp ++ str \rTemp,[\rBase,#GPSR2] ++#if (PLATFORM_TYPE==HALOGEN) ++ BigMov \rTemp,~SRVAL96 ++ str \rTemp,[\rBase,#GPCR3] ++ mvn \rTemp,\rTemp ++ str \rTemp,[\rBase,#GPSR3] ++#endif ++//////// ++ BigMov \rTemp,DRVAL0 ++ str \rTemp,[\rBase,#GPDR0] ++ ++ BigMov \rTemp,DRVAL32 ++ str \rTemp,[\rBase,#GPDR1] ++ ++ BigMov \rTemp,DRVAL64 ++ str \rTemp,[\rBase,#GPDR2] ++#if (PLATFORM_TYPE==HALOGEN) ++ BigMov \rTemp,DRVAL96 ++ str \rTemp,[\rBase,#GPDR3] ++#endif ++//////// ++ BigMov \rTemp,AFVAL0 ++ str \rTemp,[\rBase,#GAFR0_L] ++ BigMov \rTemp,AFVAL16 ++ str \rTemp,[\rBase,#GAFR0_U] ++ ++ BigMov \rTemp,AFVAL32 ++ str \rTemp,[\rBase,#GAFR1_L] ++ BigMov \rTemp,AFVAL48 ++ str \rTemp,[\rBase,#GAFR1_U] ++ ++ BigMov \rTemp,AFVAL64 ++ str \rTemp,[\rBase,#GAFR2_L] ++ BigMov \rTemp,AFVAL80 ++ str \rTemp,[\rBase,#GAFR2_U] ++#if (PLATFORM_TYPE==HALOGEN) ++ BigMov \rTemp,AFVAL96 ++ str \rTemp,[\rBase,#GAFR3_L] ++ BigMov \rTemp,AFVAL112 ++ str \rTemp,[\rBase,#GAFR3_U] ++#endif ++ BigMov \rBase,PWR_MANAGER_BASE ++ mov \rTemp,#0x30 ++ str \rTemp,[\rBase,#PSSR] ++.endm ++ ++ ++ ++.macro TransMacro val ++ BigMov r12,UART_BASE ++91: ++ BigMov r0,\val ++ bl Transmit ++ b 91b ++.endm ++// ******************************************************************************************* ++.macro InitMMU rBase,rTemp ++// mov r0,#PSR_NOINTS_MASK+PSR_MODE_SVC ++// msr cpsr_c,r0 ++// ******************************************************************** ++// Disable the MMU and gang regardless of why we are here. ++ BigMov \rBase,0x2001 //; enable access to all coprocessors ++ CP15_CP_ACCESS mcr,\rBase ++ CPWAIT \rBase ++ ++ mov \rBase,#0x00000078 //; get a zero to turn things off (must write bits[6:3] as 1's) ++ CP15_CONTROL mcr,\rBase //; Turn Off MMU, I&D Caches, WB. ++ CPWAIT \rBase ++ ++ mov \rBase,#0x00000000 //; get a zero to turn things off ++ cmp pc,#MEM_START ++ CP15_TLB_INVAL_BOTH mcr,\rBase //; flush (invalidate) I/D tlb's ++ CP15_CF_INVAL_BTB mcr,\rBase //invalidate Branch target buffer ++ CP15_CF_INVAL_D mcr,\rBase ++ CP15_CF_INVAL_I mcrcs,\rBase //I might be running from cache only, invalidate if in ram ++ CP15_CF_DRAIN mcr,\rBase //; Drain the write buffer ++ nop ++ nop ++ nop ++ mvn r0, #0 //; grant manager access to all domains ++ CP15_DACR mcr,\rBase ++.endm ++ ++//out rTemp1 reset reason ++.macro InitPWR rBase,rTemp1,rTemp2 ++ BigMov \rBase,PWR_MANAGER_BASE ++// ******************************************************************** ++ ldr \rTemp1,[\rBase,#RCSR] // Read & Init Reset Cause bits in RCSR. ++ and \rTemp1,\rTemp1,#RCSR_MASK // extract the reset cause bits ++ str \rTemp1,[\rBase,#RCSR] // clear the reset cause bits (they're sticky) ++// ******************************************************************** ++// Read and store PSSR, too - it will be reset later, after GPIOs are initialized. ++// Unclear when we'll need this information, but don't throw a good status away. ++// ldr \rTemp2, [\rBase,#PSSR] ++// extract the reset cause bits ++// and \rTemp2,\rTemp2,#PSSR_MASK //; r12 now holds the conditioned PSSR ++// orr \rTemp1,\rTemp1,\rTemp2,lsl #16 //; R10 now has RCSR in lower half and PSSR in upper. ++// ******************************************************************** ++// Reasons for being here: ++// 1) Hard Reset ++// 2) Wake from Sleep ++// 3) GPIO Reset ++// 4) Watchdog Reset ++// 5) Eboot Handoff ++// If Sleep_Reset: reinit all but RTC, PWRMAN, CLKS (except cp14)... so reinit: OST, INTC, GPIO ++// If GPIO_Reset: reinit all but MEMC.Config, RTC, CLKS (except cp14)... so reinit: treat like sleep ++// If Watchdog_Reset: reinit all but RTC.RTTR, CLK.OSCC... so reinit: treat like a hard reset, minus OSCC and RTTR init. ++// If Hard_Reset: reinit all ++.endm ++ ++// ******************************************************************************************* ++// ******************************************************************************************* ++ .list +diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/pxaMacro3.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaMacro3.h +--- u-boot-1.1.2/include/asm-arm/arch-pxa/pxaMacro3.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaMacro3.h 2007-08-11 21:07:21.000000000 +0200 +@@ -0,0 +1,74 @@ ++#include "pxaLcd2.h" ++#include "pxaMacro2.h" ++.macro DEFINE_SCREEN_WIDTH xres,xsyncWidth,xbegin,xend, yres,ysyncWidth,ybegin,yend, enable,unscramble,rotate,active,bpp,clkdiv,type ++ .ifdef __ARMASM ++ GBLA SCREEN_WIDTH ++ .endif ++ .set SCREEN_WIDTH,\xres ++.endm ++ ++.macro DEFINE_SCREEN_HEIGHT xres,xsyncWidth,xbegin,xend, yres,ysyncWidth,ybegin,yend, enable,unscramble,rotate,active,bpp,clkdiv,type ++ .ifdef __ARMASM ++ GBLA SCREEN_HEIGHT ++ .endif ++ .set SCREEN_HEIGHT,\yres ++.endm ++ ++ DEFINE_SCREEN_WIDTH DEF_P ++ DEFINE_SCREEN_HEIGHT DEF_P ++ ++.macro CR0_INIT_VAL reg,xres,xsyncWidth,xbegin,xend, yres,ysyncWidth,ybegin,yend, enable,unscramble,rotate,active,bpp,clkdiv,type ++ BigMov \reg,(\enable<>M64_numRowAddrBits)>>5) //(# of cycles/ms * # of ms for entire refresh period)/ # of rows/refresh period /32 ++#define M64_MDCNFG_VAL 1+((numColumnAddrBits-8)<<3)+((M64_numRowAddrBits-11)<<5)+((numBankAddrBits-1)<<7)+(ClkSelect<<8)+(1<<11)+(M64_SA1111_mask) //DLATCH0, latch return data with return clock ++#define M64_MDREFR_VAL (1<<16)+(1<<15)+(M64_DRI_cnt&0xfff) //don't set bit 20: APD (buggy), bit 16: K1RUN, 15:E1PIN ++//#define M64_MDREFR_VAL (1<<20)+(1<<16)+(1<<15)+(M64_DRI_cnt&0xfff) //20: APD, bit 16: K1RUN, 15:E1PIN ++// 13 9 2 2 (4bytes per address)=2**26=64 MB ++#define M64_MEM_SIZE (1<<(M64_numRowAddrBits+numColumnAddrBits+numBankAddrBits+2)) ++#define M64_MEM_END ((MEM_START)+M64_MEM_SIZE) ++ ++//32 meg option ++#define M32_numRowAddrBits 12 //for MT48LC8M16A2 - 75 B ++#define M32_SA1111_mask 0 ++#define M32_DRI_cnt (((99530*64)>>M32_numRowAddrBits)>>5) //(# of cycles/ms * # of ms for entire refresh period)/ # of rows/refresh period /32 ++#define M32_MDCNFG_VAL 1+((numColumnAddrBits-8)<<3)+((M32_numRowAddrBits-11)<<5)+((numBankAddrBits-1)<<7)+(ClkSelect<<8)+(1<<11)+(M32_SA1111_mask) //DLATCH0, latch return data with return clock ++#define M32_MDREFR_VAL (1<<16)+(1<<15)+(M32_DRI_cnt&0xfff) //don't set bit 20: APD (buggy), bit 16: K1RUN, 15:E1PIN ++// 12 9 2 2 (4bytes per address)=2**25=32 MB ++#define M32_MEM_SIZE (1<<(M32_numRowAddrBits+numColumnAddrBits+numBankAddrBits+2)) ++#define M32_MEM_END ((MEM_START)+M32_MEM_SIZE) ++// ******************************************************************************************* ++//out: rTemp - memory size ++.macro CalcMemSize rBase,rTemp,mem_control_base ++ BigMov \rBase,\mem_control_base ++ ldr \rTemp,[\rBase,#MDCNFG] ++ movs \rTemp,\rTemp,LSR #2+1 //bit 2 - 1 means 16 bit mode, 0 means 32 bit mode, mov to carry flag ++ tst \rTemp,#1<<(5-3) //is number of row address bits 12 or 13 ? ++ moveq \rTemp,#M64_MEM_SIZE ++ movne \rTemp,#M32_MEM_SIZE ++ movcs \rTemp,\rTemp,LSR #1 //half as much if 16 bit mode ++.endm ++ ++ ++#define CH_NULL 0x00 ++#define CH_BACKSPACE 0x08 ++#define CH_LF 0x0a ++#define CH_CR 0x0d ++#define CH_CAN 0x18 ++#define CH_SPACE 0x20 //" " ++#define CH_EXCLAMATION 0x21 //! ++#define CH_DQUOTE 0x22 //" ++#define CH_POUND 0x23 //# ++#define CH_DOLLAR 0x24 //$ ++#define CH_PERCENT 0x25 //% ++#define CH_AMPERSAND 0x26 //& ++#define CH_SQUOTE 0x27 //' ++#define CH_OPEN_PAREN 0x28 //( ++#define CH_CLOSE_PAREN 0x29 //) ++#define CH_ASTERISK 0x2a //* ++#define CH_PLUS 0x2b //+ ++#define CH_COMMA 0x2c //, ++#define CH_HYPHEN 0x2d //- ++#define CH_MINUS 0x2d //- ++#define CH_PERIOD 0x2e //. ++#define CH_FSLASH 0x2f // / ++#define CH_0 0x30 ++#define CH_1 0x31 ++#define CH_2 0x32 ++#define CH_3 0x33 ++#define CH_4 0x34 ++#define CH_5 0x35 ++#define CH_6 0x36 ++#define CH_7 0x37 ++#define CH_8 0x38 ++#define CH_9 0x39 ++#define CH_COLON 0x3a //: ++#define CH_SEMICOLON 0x3b //; ++#define CH_LESS_THAN 0x3c //< ++#define CH_EQUAL 0x3d //= ++#define CH_GREATER_THAN 0x3e //> ++#define CH_QUESTION_MARK 0x3f //? ++#define CH_AT_SIGN 0x40 //@ ++ ++#define CH_A 0x41 ++#define CH_B 0x42 ++#define CH_C 0x43 ++#define CH_D 0x44 ++#define CH_E 0x45 ++#define CH_F 0x46 ++#define CH_G 0x47 ++#define CH_H 0x48 ++#define CH_I 0x49 ++#define CH_J 0x4a ++#define CH_K 0x4b ++#define CH_L 0x4c ++#define CH_M 0x4d ++#define CH_N 0x4e ++#define CH_O 0x4f ++#define CH_P 0x50 ++#define CH_Q 0x51 ++#define CH_R 0x52 ++#define CH_S 0x53 ++#define CH_T 0x54 ++#define CH_U 0x55 ++#define CH_V 0x56 ++#define CH_W 0x57 ++#define CH_X 0x58 ++#define CH_Y 0x59 ++#define CH_Z 0x5a ++#define CH_OPEN_SQUARE 0x5b //[ ++#define CH_BSLASH 0x5c //\.. ++#define CH_CLOSE_SQUARE 0x5d //] ++#define CH_CARET 0x5e //^ ++#define CH__ 0x5f //_ ++#define CH_OPEN_SQUOTE 0x60 //` ++ ++#define CH_a 0x61 ++#define CH_b 0x62 ++#define CH_c 0x63 ++#define CH_d 0x64 ++#define CH_e 0x65 ++#define CH_f 0x66 ++#define CH_g 0x67 ++#define CH_h 0x68 ++#define CH_i 0x69 ++#define CH_j 0x6a ++#define CH_k 0x6b ++#define CH_l 0x6c ++#define CH_m 0x6d ++#define CH_n 0x6e ++#define CH_o 0x6f ++#define CH_p 0x70 ++#define CH_q 0x71 ++#define CH_r 0x72 ++#define CH_s 0x73 ++#define CH_t 0x74 ++#define CH_u 0x75 ++#define CH_v 0x76 ++#define CH_w 0x77 ++#define CH_x 0x78 ++#define CH_y 0x79 ++#define CH_z 0x7a ++#define CH_OPEN_CURLY 0x7b //{ ++#define CH_VERTICAL_BAR 0x7c //| ++#define CH_CLOSE_CURLY 0x7d //} ++#define CH_TILDE 0x7e //~ ++#define CH_DELETE 0x7f ++ ++ ++.macro STARTUPTEXT ++ GBLS AreaName ++ AREA |.astart|,ALIGN=2,CODE ++AreaName SETS "|.astart|" ++.endm ++ ++.macro DUP count,val ++ LCLA cnt ++cnt SETA $count ++ WHILE ( cnt<>0) ++ DCD $val ++cnt SETA cnt-1 ++ WEND ++.endm +diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/pxa-regs.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxa-regs.h +--- u-boot-1.1.2/include/asm-arm/arch-pxa/pxa-regs.h 2003-06-27 23:32:42.000000000 +0200 ++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxa-regs.h 2007-08-11 21:07:21.000000000 +0200 +@@ -107,6 +107,17 @@ + #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ + #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ + #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ ++ ++#if defined(CONFIG_PXA27X) ++#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ ++#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ ++#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ ++#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ ++#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ ++#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ ++#define DCSR_ENRINTR (1 << 9) /* The end of Receive */ ++#endif ++ + #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ + #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ + #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */ +@@ -156,6 +167,10 @@ + #define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */ + #define DRCMR39 __REG(0x4000019C) /* Reserved */ + ++#define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */ ++#define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */ ++#define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */ ++ + #define DRCMRRXSADR DRCMR2 + #define DRCMRTXSADR DRCMR3 + #define DRCMRRXBTRBR DRCMR4 +@@ -424,6 +439,12 @@ + #define ISR __REG(0x40301698) /* I2C Status Register - ISR */ + #define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */ + ++#define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */ ++#define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */ ++#define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */ ++#define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */ ++#define PWRISAR __REG(0x40f001A0) /* Power I2C Slave Address Register-ISAR */ ++ + /* ----- Control register bits ---------------------------------------- */ + + #define ICR_START 0x1 /* start bit */ +@@ -460,11 +481,9 @@ + /* + * Serial Audio Controller + */ +- +- + /* FIXME the audio defines collide w/ the SA1111 defines. I don't like these +- * short defines because there is too much chance of namespace collision */ +- ++ * short defines because there is too much chance of namespace collision ++ */ + /*#define SACR0 __REG(0x40400000) / Global Control Register */ + /*#define SACR1 __REG(0x40400004) / Serial Audio I 2 S/MSB-Justified Control Register */ + /*#define SASR0 __REG(0x4040000C) / Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ +@@ -711,10 +730,68 @@ + #define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */ + + ++#if defined(CONFIG_PXA27X) + /* +- * Fast Infrared Communication Port ++ * USB Host Controller + */ ++#define USBH_BASE 0x4C000000 ++#define UHCREV __REG(0x4C000000) ++#define UHCHCON __REG(0x4C000004) ++#define UHCCOMS __REG(0x4C000008) ++#define UHCINTS __REG(0x4C00000C) ++#define UHCINTE __REG(0x4C000010) ++#define UHCINTD __REG(0x4C000014) ++#define UHCHCCA __REG(0x4C000018) ++#define UHCPCED __REG(0x4C00001C) ++#define UHCCHED __REG(0x4C000020) ++#define UHCCCED __REG(0x4C000024) ++#define UHCBHED __REG(0x4C000028) ++#define UHCBCED __REG(0x4C00002C) ++#define UHCDHEAD __REG(0x4C000030) ++#define UHCFMI __REG(0x4C000034) ++#define UHCFMR __REG(0x4C000038) ++#define UHCFMN __REG(0x4C00003C) ++#define UHCPERS __REG(0x4C000040) ++#define UHCLST __REG(0x4C000044) ++#define UHCRHDA __REG(0x4C000048) ++#define UHCRHDB __REG(0x4C00004C) ++#define UHCRHS __REG(0x4C000050) ++#define UHCRHPS1 __REG(0x4C000054) ++#define UHCRHPS2 __REG(0x4C000058) ++#define UHCRHPS3 __REG(0x4C00005C) ++#define UHCSTAT __REG(0x4C000060) ++#define UHCHR __REG(0x4C000064) ++#define UHCHIE __REG(0x4C000068) ++#define UHCHIT __REG(0x4C00006C) ++ ++#define UHCHR_FSBIR (1<<0) ++#define UHCHR_FHR (1<<1) ++#define UHCHR_CGR (1<<2) ++#define UHCHR_SSDC (1<<3) ++#define UHCHR_UIT (1<<4) ++#define UHCHR_SSE (1<<5) ++#define UHCHR_PSPL (1<<6) ++#define UHCHR_PCPL (1<<7) ++#define UHCHR_SSEP0 (1<<9) ++#define UHCHR_SSEP1 (1<<10) ++#define UHCHR_SSEP2 (1<<11) ++ ++#define UHCHIE_UPRIE (1<<13) ++#define UHCHIE_UPS2IE (1<<12) ++#define UHCHIE_UPS1IE (1<<11) ++#define UHCHIE_TAIE (1<<10) ++#define UHCHIE_HBAIE (1<<8) ++#define UHCHIE_RWIE (1<<7) ++ ++#define UHCCOMS_HCR 1 ++#define UHCRHS_LPS 1 ++#define UHCHR_SSE (1<<5) ++ ++#endif + ++/* ++ * Fast Infrared Communication Port ++ */ + #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ + #define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */ + #define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */ +@@ -731,7 +808,21 @@ + #define RTAR __REG(0x40900004) /* RTC Alarm Register */ + #define RTSR __REG(0x40900008) /* RTC Status Register */ + #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ +- ++#define RDAR1 __REG(0x40900018) /* Wristwatch Day Alarm Reg 1 */ ++#define RDAR2 __REG(0x40900020) /* Wristwatch Day Alarm Reg 2 */ ++#define RYAR1 __REG(0x4090001C) /* Wristwatch Year Alarm Reg 1 */ ++#define RYAR2 __REG(0x40900024) /* Wristwatch Year Alarm Reg 2 */ ++#define SWAR1 __REG(0x4090002C) /* Stopwatch Alarm Register 1 */ ++#define SWAR2 __REG(0x40900030) /* Stopwatch Alarm Register 2 */ ++#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */ ++#define RDCR __REG(0x40900010) /* RTC Day Count Register. */ ++#define RYCR __REG(0x40900014) /* RTC Year Count Register. */ ++#define SWCR __REG(0x40900028) /* Stopwatch Count Register */ ++#define RTCPICR __REG(0x40900034) /* Periodic Interrupt Counter Register */ ++ ++#define RTSR_PICE (1 << 15) /* Peridoc interrupt count enable */ ++#define RTSR_PIALE (1 << 14) /* Peridoc interrupt Alarm enable */ ++#define RTSR_PIAL (1 << 13) /* Peridoc interrupt Alarm status */ + #define RTSR_HZE (1 << 3) /* HZ interrupt enable */ + #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ + #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ +@@ -831,6 +922,37 @@ + /* More handy macros. The argument is a literal GPIO number. */ + + #define GPIO_bit(x) (1 << ((x) & 0x1f)) ++ ++#ifdef CONFIG_PXA27X ++ ++/* Interrupt Controller */ ++ ++#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ ++#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ ++#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ ++#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ ++#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ ++ ++#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) ++#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) ++#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) ++#define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) ++#define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) ++#define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) ++#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) ++#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) ++ ++#define GPLR(x) ((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3) ++#define GPDR(x) ((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3) ++#define GPSR(x) ((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3) ++#define GPCR(x) ((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3) ++#define GRER(x) ((((x) & 0x7f) < 96) ? _GRER(x) : GRER3) ++#define GFER(x) ((((x) & 0x7f) < 96) ? _GFER(x) : GFER3) ++#define GEDR(x) ((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3) ++#define GAFR(x) ((((x) & 0x7f) < 96) ? _GAFR(x) : \ ++ ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U)) ++#else ++ + #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) + #define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) + #define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) +@@ -840,6 +962,8 @@ + #define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) + #define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) + ++#endif ++ + /* GPIO alternate function assignments */ + + #define GPIO1_RST 1 /* reset */ +@@ -1038,6 +1162,8 @@ + #define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT) + #define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT) + ++#define GPIO117_SCL (117 | GPIO_ALT_FN_1_OUT) ++#define GPIO118_SDA (118 | GPIO_ALT_FN_1_OUT) + + /* + * Power Manager +@@ -1054,8 +1180,62 @@ + #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */ + #define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */ + #define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ ++#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */ + #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ + ++#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */ ++#define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */ ++#define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */ ++#define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */ ++#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */ ++#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */ ++#define PCMD(x) __REG(0x40F00080 + x*4) ++#define PCMD0 __REG(0x40F00080 + 0 * 4) ++#define PCMD1 __REG(0x40F00080 + 1 * 4) ++#define PCMD2 __REG(0x40F00080 + 2 * 4) ++#define PCMD3 __REG(0x40F00080 + 3 * 4) ++#define PCMD4 __REG(0x40F00080 + 4 * 4) ++#define PCMD5 __REG(0x40F00080 + 5 * 4) ++#define PCMD6 __REG(0x40F00080 + 6 * 4) ++#define PCMD7 __REG(0x40F00080 + 7 * 4) ++#define PCMD8 __REG(0x40F00080 + 8 * 4) ++#define PCMD9 __REG(0x40F00080 + 9 * 4) ++#define PCMD10 __REG(0x40F00080 + 10 * 4) ++#define PCMD11 __REG(0x40F00080 + 11 * 4) ++#define PCMD12 __REG(0x40F00080 + 12 * 4) ++#define PCMD13 __REG(0x40F00080 + 13 * 4) ++#define PCMD14 __REG(0x40F00080 + 14 * 4) ++#define PCMD15 __REG(0x40F00080 + 15 * 4) ++#define PCMD16 __REG(0x40F00080 + 16 * 4) ++#define PCMD17 __REG(0x40F00080 + 17 * 4) ++#define PCMD18 __REG(0x40F00080 + 18 * 4) ++#define PCMD19 __REG(0x40F00080 + 19 * 4) ++#define PCMD20 __REG(0x40F00080 + 20 * 4) ++#define PCMD21 __REG(0x40F00080 + 21 * 4) ++#define PCMD22 __REG(0x40F00080 + 22 * 4) ++#define PCMD23 __REG(0x40F00080 + 23 * 4) ++#define PCMD24 __REG(0x40F00080 + 24 * 4) ++#define PCMD25 __REG(0x40F00080 + 25 * 4) ++#define PCMD26 __REG(0x40F00080 + 26 * 4) ++#define PCMD27 __REG(0x40F00080 + 27 * 4) ++#define PCMD28 __REG(0x40F00080 + 28 * 4) ++#define PCMD29 __REG(0x40F00080 + 29 * 4) ++#define PCMD30 __REG(0x40F00080 + 30 * 4) ++#define PCMD31 __REG(0x40F00080 + 31 * 4) ++ ++#define PCMD_MBC (1<<12) ++#define PCMD_DCE (1<<11) ++#define PCMD_LC (1<<10) ++/* FIXME: PCMD_SQC need be checked. */ ++#define PCMD_SQC (3<<8) /* currently only bit 8 is changerable, */ ++ /* bit 9 should be 0 all day. */ ++#define PVCR_VCSA (0x1<<14) ++#define PVCR_CommandDelay (0xf80) ++/* define MACRO for Power Manager General Configuration Register (PCFR) */ ++#define PCFR_FVC (0x1 << 10) ++#define PCFR_PI2C_EN (0x1 << 6) ++ ++#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ + #define PSSR_RDH (1 << 5) /* Read Disable Hold */ + #define PSSR_PH (1 << 4) /* Peripheral Control Hold */ + #define PSSR_VFS (1 << 2) /* VDD Fault Status */ +@@ -1117,14 +1297,29 @@ + #define OSCC __REG(0x41300008) /* Oscillator Configuration Register */ + + #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ ++#if !defined(CONFIG_PXA27X) + #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ ++#endif + #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ + ++#define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */ ++#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ ++#define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */ ++#define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */ ++#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ ++#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ ++#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ ++#define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */ + #define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */ ++#define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */ + #define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */ + #define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */ + #define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */ + #define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */ ++#if defined(CONFIG_PXA27X) ++#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */ ++#define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */ ++#endif + #define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */ + #define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */ + #define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */ +@@ -1137,6 +1332,7 @@ + #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ + #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ + ++#if !defined(CONFIG_PXA27X) + #define CCCR_L09 (0x1F) + #define CCCR_L27 (0x1) + #define CCCR_L32 (0x2) +@@ -1153,6 +1349,7 @@ + #define CCCR_N20 (0x4 << 7) + #define CCCR_N25 (0x5 << 7) + #define CCCR_N30 (0x6 << 7) ++#endif + + /* + * LCD +@@ -1164,7 +1361,8 @@ + #define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */ + #define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */ + #define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */ +-#define LCSR __REG(0x44000038) /* LCD Controller Status Register */ ++#define LCSR0 __REG(0x44000038) /* LCD Controller Status Register */ ++#define LCSR1 __REG(0x44000034) /* LCD Controller Status Register */ + #define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */ + #define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */ + #define TMEDCR __REG(0x44000044) /* TMED Control Register */ +@@ -1194,6 +1392,11 @@ + #define LCCR0_PDD_S 12 + #define LCCR0_BM (1 << 20) /* Branch mask */ + #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ ++#if defined(CONFIG_PXA27X) ++#define LCCR0_LCDT (1 << 22) /* LCD Panel Type */ ++#define LCCR0_RDSTM (1 << 23) /* Read Status Interrupt Mask */ ++#define LCCR0_CMDIM (1 << 24) /* Command Interrupt Mask */ ++#endif + + #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ + #define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \ +@@ -1257,6 +1460,11 @@ + #endif + #define LCCR3_DPC (1 << 27) /* double pixel clock mode */ + ++#define LCCR3_PDFOR_0 (0 << 30) ++#define LCCR3_PDFOR_1 (1 << 30) ++#define LCCR3_PDFOR_2 (2 << 30) ++#define LCCR3_PDFOR_3 (3 << 30) ++ + + #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ + #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \ +@@ -1265,7 +1473,7 @@ + + #define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */ + #define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \ +- (((Bpp) << FShft (LCCR3_BPP))) ++ ((((Bpp&0x7) << FShft (LCCR3_BPP)))|(((Bpp&0x8)<<26))) + + #define LCCR3_ACB Fld (8, 8) /* AC Bias */ + #define LCCR3_Acb(Acb) /* BAC Bias */ \ +@@ -1280,33 +1488,50 @@ + #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ + /* active Low */ + +-#define LCSR_LDD (1 << 0) /* LCD Disable Done */ +-#define LCSR_SOF (1 << 1) /* Start of frame */ +-#define LCSR_BER (1 << 2) /* Bus error */ +-#define LCSR_ABC (1 << 3) /* AC Bias count */ +-#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */ +-#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */ +-#define LCSR_OU (1 << 6) /* output FIFO underrun */ +-#define LCSR_QD (1 << 7) /* quick disable */ +-#define LCSR_EOF (1 << 8) /* end of frame */ +-#define LCSR_BS (1 << 9) /* branch status */ +-#define LCSR_SINT (1 << 10) /* subsequent interrupt */ +- +-#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ +- +-#define LCSR_LDD (1 << 0) /* LCD Disable Done */ +-#define LCSR_SOF (1 << 1) /* Start of frame */ +-#define LCSR_BER (1 << 2) /* Bus error */ +-#define LCSR_ABC (1 << 3) /* AC Bias count */ +-#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */ +-#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */ +-#define LCSR_OU (1 << 6) /* output FIFO underrun */ +-#define LCSR_QD (1 << 7) /* quick disable */ +-#define LCSR_EOF (1 << 8) /* end of frame */ +-#define LCSR_BS (1 << 9) /* branch status */ +-#define LCSR_SINT (1 << 10) /* subsequent interrupt */ ++#define LCSR0_LDD (1 << 0) /* LCD Disable Done */ ++#define LCSR0_SOF (1 << 1) /* Start of frame */ ++#define LCSR0_BER (1 << 2) /* Bus error */ ++#define LCSR0_ABC (1 << 3) /* AC Bias count */ ++#define LCSR0_IUL (1 << 4) /* input FIFO underrun Lower panel */ ++#define LCSR0_IUU (1 << 5) /* input FIFO underrun Upper panel */ ++#define LCSR0_OU (1 << 6) /* output FIFO underrun */ ++#define LCSR0_QD (1 << 7) /* quick disable */ ++#define LCSR0_EOF0 (1 << 8) /* end of frame */ ++#define LCSR0_BS (1 << 9) /* branch status */ ++#define LCSR0_SINT (1 << 10) /* subsequent interrupt */ ++ ++#define LCSR1_SOF1 (1 << 0) ++#define LCSR1_SOF2 (1 << 1) ++#define LCSR1_SOF3 (1 << 2) ++#define LCSR1_SOF4 (1 << 3) ++#define LCSR1_SOF5 (1 << 4) ++#define LCSR1_SOF6 (1 << 5) ++ ++#define LCSR1_EOF1 (1 << 8) ++#define LCSR1_EOF2 (1 << 9) ++#define LCSR1_EOF3 (1 << 10) ++#define LCSR1_EOF4 (1 << 11) ++#define LCSR1_EOF5 (1 << 12) ++#define LCSR1_EOF6 (1 << 13) ++ ++#define LCSR1_BS1 (1 << 16) ++#define LCSR1_BS2 (1 << 17) ++#define LCSR1_BS3 (1 << 18) ++#define LCSR1_BS4 (1 << 19) ++#define LCSR1_BS5 (1 << 20) ++#define LCSR1_BS6 (1 << 21) ++ ++#define LCSR1_IU2 (1 << 25) ++#define LCSR1_IU3 (1 << 26) ++#define LCSR1_IU4 (1 << 27) ++#define LCSR1_IU5 (1 << 28) ++#define LCSR1_IU6 (1 << 29) + + #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ ++#if defined(CONFIG_PXA27X) ++#define LDCMD_SOFINT (1 << 22) ++#define LDCMD_EOFINT (1 << 21) ++#endif + + /* + * Memory controller +@@ -1369,5 +1594,191 @@ + #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ + #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ + ++#if defined(CONFIG_PXA27X) + +-#endif ++#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ ++ ++#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ ++#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ ++#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */ ++#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */ ++#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */ ++#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */ ++#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ ++#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ ++#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ ++ ++/* Interrupt Controller */ ++ ++#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ ++#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ ++#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ ++#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ ++#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ ++ ++/* General Purpose I/O */ ++ ++#define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */ ++#define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */ ++#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */ ++#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */ ++#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */ ++#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO <127:96> */ ++#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */ ++#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */ ++#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */ ++ ++/* Core Clock */ ++ ++#define CCSR __REG(0x4130000C) /* Core Clock Status Register */ ++ ++#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ ++#define CKEN22_MEMC (1 << 22) /* Memory Controler */ ++#define CKEN21_MSHC (1 << 21) /* Memery Stick Host Controller */ ++#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ ++#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ ++#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ ++#define CKEN17_MSL (1 << 17) /* MSL Interface Unit Clock Enable */ ++#define CKEN15_PWR_I2C (1 << 15) /* PWR_I2C Unit Clock Enable */ ++#define CKEN9_OST (1 << 9) /* OS Timer Unit Clock Enable */ ++#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */ ++ ++/* Memory controller */ ++ ++#define MDREFR_K0DB4 (1 << 29) /* SDCLK[0] divide by 4 */ ++ ++/* LCD registers */ ++#define LCCR4 __REG(0x44000010) /* LCD Controller Control Register 4 */ ++#define LCCR5 __REG(0x44000014) /* LCD Controller Control Register 5 */ ++#define FBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */ ++#define FBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */ ++#define FBR2 __REG(0x44000028) /* DMA Channel 2 Frame Branch Register */ ++#define FBR3 __REG(0x4400002C) /* DMA Channel 3 Frame Branch Register */ ++#define FBR4 __REG(0x44000030) /* DMA Channel 4 Frame Branch Register */ ++#define FDADR2 __REG(0x44000220) /* DMA Channel 2 Frame Descriptor Address Register */ ++#define FSADR2 __REG(0x44000224) /* DMA Channel 2 Frame Source Address Register */ ++#define FIDR2 __REG(0x44000228) /* DMA Channel 2 Frame ID Register */ ++#define LDCMD2 __REG(0x4400022C) /* DMA Channel 2 Command Register */ ++#define FDADR3 __REG(0x44000230) /* DMA Channel 3 Frame Descriptor Address Register */ ++#define FSADR3 __REG(0x44000234) /* DMA Channel 3 Frame Source Address Register */ ++#define FIDR3 __REG(0x44000238) /* DMA Channel 3 Frame ID Register */ ++#define LDCMD3 __REG(0x4400023C) /* DMA Channel 3 Command Register */ ++#define FDADR4 __REG(0x44000240) /* DMA Channel 4 Frame Descriptor Address Register */ ++#define FSADR4 __REG(0x44000244) /* DMA Channel 4 Frame Source Address Register */ ++#define FIDR4 __REG(0x44000248) /* DMA Channel 4 Frame ID Register */ ++#define LDCMD4 __REG(0x4400024C) /* DMA Channel 4 Command Register */ ++#define FDADR5 __REG(0x44000250) /* DMA Channel 5 Frame Descriptor Address Register */ ++#define FSADR5 __REG(0x44000254) /* DMA Channel 5 Frame Source Address Register */ ++#define FIDR5 __REG(0x44000258) /* DMA Channel 5 Frame ID Register */ ++#define LDCMD5 __REG(0x4400025C) /* DMA Channel 5 Command Register */ ++ ++#define OVL1C1 __REG(0x44000050) /* Overlay 1 Control Register 1 */ ++#define OVL1C2 __REG(0x44000060) /* Overlay 1 Control Register 2 */ ++#define OVL2C1 __REG(0x44000070) /* Overlay 2 Control Register 1 */ ++#define OVL2C2 __REG(0x44000080) /* Overlay 2 Control Register 2 */ ++#define CCR __REG(0x44000090) /* Cursor Control Register */ ++ ++#define FBR5 __REG(0x44000110) /* DMA Channel 5 Frame Branch Register */ ++#define FBR6 __REG(0x44000114) /* DMA Channel 6 Frame Branch Register */ ++ ++#define LCCR0_LDDALT (1<<26) /* LDD Alternate mapping bit when base pixel is RGBT16 */ ++#define LCCR0_OUC (1<<25) /* Overlay Underlay Control Bit */ ++ ++#define LCCR5_SOFM1 (1<<0) /* Start Of Frame Mask for Overlay 1 (channel 1) */ ++#define LCCR5_SOFM2 (1<<1) /* Start Of Frame Mask for Overlay 2 (channel 2) */ ++#define LCCR5_SOFM3 (1<<2) /* Start Of Frame Mask for Overlay 2 (channel 3) */ ++#define LCCR5_SOFM4 (1<<3) /* Start Of Frame Mask for Overlay 2 (channel 4) */ ++#define LCCR5_SOFM5 (1<<4) /* Start Of Frame Mask for cursor (channel 5) */ ++#define LCCR5_SOFM6 (1<<5) /* Start Of Frame Mask for command data (channel 6) */ ++ ++#define LCCR5_EOFM1 (1<<8) /* End Of Frame Mask for Overlay 1 (channel 1) */ ++#define LCCR5_EOFM2 (1<<9) /* End Of Frame Mask for Overlay 2 (channel 2) */ ++#define LCCR5_EOFM3 (1<<10) /* End Of Frame Mask for Overlay 2 (channel 3) */ ++#define LCCR5_EOFM4 (1<<11) /* End Of Frame Mask for Overlay 2 (channel 4) */ ++#define LCCR5_EOFM5 (1<<12) /* End Of Frame Mask for cursor (channel 5) */ ++#define LCCR5_EOFM6 (1<<13) /* End Of Frame Mask for command data (channel 6) */ ++ ++#define LCCR5_BSM1 (1<<16) /* Branch mask for Overlay 1 (channel 1) */ ++#define LCCR5_BSM2 (1<<17) /* Branch mask for Overlay 2 (channel 2) */ ++#define LCCR5_BSM3 (1<<18) /* Branch mask for Overlay 2 (channel 3) */ ++#define LCCR5_BSM4 (1<<19) /* Branch mask for Overlay 2 (channel 4) */ ++#define LCCR5_BSM5 (1<<20) /* Branch mask for cursor (channel 5) */ ++#define LCCR5_BSM6 (1<<21) /* Branch mask for data command (channel 6) */ ++ ++#define LCCR5_IUM1 (1<<24) /* Input FIFO Underrun Mask for Overlay 1 */ ++#define LCCR5_IUM2 (1<<25) /* Input FIFO Underrun Mask for Overlay 2 */ ++#define LCCR5_IUM3 (1<<26) /* Input FIFO Underrun Mask for Overlay 2 */ ++#define LCCR5_IUM4 (1<<27) /* Input FIFO Underrun Mask for Overlay 2 */ ++#define LCCR5_IUM5 (1<<28) /* Input FIFO Underrun Mask for cursor */ ++#define LCCR5_IUM6 (1<<29) /* Input FIFO Underrun Mask for data command */ ++ ++#define OVL1C1_O1EN (1<<31) /* Enable bit for Overlay 1 */ ++#define OVL2C1_O2EN (1<<31) /* Enable bit for Overlay 2 */ ++#define CCR_CEN (1<<31) /* Enable bit for Cursor */ ++ ++/* Keypad controller */ ++ ++#define KPC __REG(0x41500000) /* Keypad Interface Control register */ ++#define KPDK __REG(0x41500008) /* Keypad Interface Direct Key register */ ++#define KPREC __REG(0x41500010) /* Keypad Intefcace Rotary Encoder register */ ++#define KPMK __REG(0x41500018) /* Keypad Intefcace Matrix Key register */ ++#define KPAS __REG(0x41500020) /* Keypad Interface Automatic Scan register */ ++#define KPASMKP0 __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */ ++#define KPASMKP1 __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */ ++#define KPASMKP2 __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */ ++#define KPASMKP3 __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */ ++#define KPKDI __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */ ++ ++#define KPC_AS (0x1 << 30) /* Automatic Scan bit */ ++#define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */ ++#define KPC_MI (0x1 << 22) /* Matrix interrupt bit */ ++#define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */ ++#define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */ ++#define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */ ++#define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */ ++#define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */ ++#define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */ ++#define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */ ++#define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */ ++#define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */ ++#define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */ ++#define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */ ++#define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Key Debounce select */ ++#define KPC_DI (0x1 << 5) /* Direct key interrupt bit */ ++#define KPC_DEE0 (0x1 << 2) /* Rotary Encoder 0 Enable */ ++#define KPC_DE (0x1 << 1) /* Direct Keypad Enable */ ++#define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */ ++ ++#define KPDK_DKP (0x1 << 31) ++#define KPDK_DK7 (0x1 << 7) ++#define KPDK_DK6 (0x1 << 6) ++#define KPDK_DK5 (0x1 << 5) ++#define KPDK_DK4 (0x1 << 4) ++#define KPDK_DK3 (0x1 << 3) ++#define KPDK_DK2 (0x1 << 2) ++#define KPDK_DK1 (0x1 << 1) ++#define KPDK_DK0 (0x1 << 0) ++ ++#define KPREC_OF1 (0x1 << 31) ++#define kPREC_UF1 (0x1 << 30) ++#define KPREC_OF0 (0x1 << 15) ++#define KPREC_UF0 (0x1 << 14) ++ ++#define KPMK_MKP (0x1 << 31) ++#define KPAS_SO (0x1 << 31) ++#define KPASMKPx_SO (0x1 << 31) ++ ++#define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */ ++#define PSLR __REG(0x40F00034) ++#define PSTR __REG(0x40F00038) /* Power Manager Standby Configuration Reg */ ++#define PSNR __REG(0x40F0003C) /* Power Manager Sense Configuration Reg */ ++#define PVCR __REG(0x40F00040) /* Power Manager Voltage Change Control Reg */ ++#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-Up Enable Reg */ ++#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Status Reg */ ++#define OSMR4 __REG(0x40A00080) /* */ ++#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ ++#define OMCR4 __REG(0x40A000C0) /* */ ++ ++#endif /* CONFIG_PXA27X */ ++ ++#endif /* _PXA_REGS_H_ */ +diff -u -r --new-file u-boot-1.1.2/include/asm-arm/mach-types.h u-boot-1.1.2-neon/include/asm-arm/mach-types.h +--- u-boot-1.1.2/include/asm-arm/mach-types.h 2004-10-10 20:41:14.000000000 +0200 ++++ u-boot-1.1.2-neon/include/asm-arm/mach-types.h 2007-08-11 21:07:21.000000000 +0200 +@@ -624,6 +624,9 @@ + #define MACH_TYPE_RMS100 611 + #define MACH_TYPE_KB9200 612 + #define MACH_TYPE_SX1 613 ++#define MACH_TYPE_NEON 332 ++#define MACH_TYPE_BD2003 332 ++#define MACH_TYPE_HALOGEN 332 + + #ifdef CONFIG_ARCH_EBSA110 + # ifdef machine_arch_type +@@ -7945,6 +7948,42 @@ + # define machine_is_sx1() (0) + #endif + ++#ifdef CONFIG_ARCH_NEON ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_NEON ++# endif ++# define machine_is_neon() (machine_arch_type == MACH_TYPE_NEON) ++#else ++# define machine_is_neon() (0) ++#endif ++ ++#ifdef CONFIG_ARCH_BD2003 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_BD2003 ++# endif ++# define machine_is_bd2003() (machine_arch_type == MACH_TYPE_BD2003) ++#else ++# define machine_is_bd2003() (0) ++#endif ++ ++#ifdef CONFIG_ARCH_HALOGEN ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_HALOGEN ++# endif ++# define machine_is_halogen() (machine_arch_type == MACH_TYPE_HALOGEN) ++#else ++# define machine_is_halogen() (0) ++#endif ++ + /* + * These have not yet been registered + */ +diff -u -r --new-file u-boot-1.1.2/include/asm-arm/processor.h u-boot-1.1.2-neon/include/asm-arm/processor.h +--- u-boot-1.1.2/include/asm-arm/processor.h 2003-06-26 00:26:36.000000000 +0200 ++++ u-boot-1.1.2-neon/include/asm-arm/processor.h 2007-08-11 21:07:21.000000000 +0200 +@@ -48,11 +48,22 @@ + #include + #include + ++#ifdef arm ++#warning arm defined by preprocessor ++#define armX arm ++#undef arm ++#endif ++ + union debug_insn { + u32 arm; + u16 thumb; + }; + ++#ifdef armX ++#define arm ++#undef armX ++#endif ++ + struct debug_entry { + u32 address; + union debug_insn insn; +diff -u -r --new-file u-boot-1.1.2/include/cmd_confdefs.h u-boot-1.1.2-neon/include/cmd_confdefs.h +--- u-boot-1.1.2/include/cmd_confdefs.h 2004-12-16 18:59:53.000000000 +0100 ++++ u-boot-1.1.2-neon/include/cmd_confdefs.h 2007-08-11 21:07:21.000000000 +0200 +@@ -92,6 +92,8 @@ + #define CFG_CMD_XIMG 0x0400000000000000ULL /* Load part of Multi Image */ + #define CFG_CMD_UNIVERSE 0x0800000000000000ULL /* Tundra Universe Support */ + #define CFG_CMD_EXT2 0x1000000000000000ULL /* EXT2 Support */ ++#define CFG_CMD_LCDPANEL 0x2000000000000000ULL /* Dynamic LCD Panel Support */ ++#define CFG_CMD_NOT 0x4000000000000000ULL /* Negate a command */ + + #define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFFULL /* ALL commands */ + +diff -u -r --new-file u-boot-1.1.2/include/configs/bd2003.h u-boot-1.1.2-neon/include/configs/bd2003.h +--- u-boot-1.1.2/include/configs/bd2003.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/include/configs/bd2003.h 2007-08-11 21:07:21.000000000 +0200 +@@ -0,0 +1,315 @@ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++/* ++ * bd2003.h ++ * ++ * This header file declares the configuration constants for the Boundary ++ * Devices BD2003 board. ++ * ++ * Change History : ++ * ++ * $Log: bd2003.h,v $ ++ * Revision 1.7 2005/07/18 01:51:59 tkisky ++ * -define display types ++ * ++ * Revision 1.6 2005/07/17 22:52:10 ericn ++ * -fix comment ++ * ++ * Revision 1.5 2005/07/17 22:36:37 ericn ++ * -merge w/boundaryLib ++ * ++ * Revision 1.4 2005/07/02 18:45:55 ericn ++ * -bring up-to-date ++ * ++ * Revision 1.3 2005/04/20 09:05:36 tkisky ++ * -include select.h ++ * ++ * Revision 1.2 2005/04/15 10:40:52 tkisky ++ * -remove LCD_XRES,LCD_YRES ++ * ++ * Revision 1.1 2005/04/09 17:49:24 ericn ++ * -Initial import ++ * ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ * Copyright Boundary Devices, Inc. 2005 ++ */ ++ ++/* ++ * If we are developing, we might want to start armboot from ram ++ * so we MUST NOT initialize critical regs like mem-timing ... ++ */ ++#include "select.h" ++ ++#define CONFIG_INIT_CRITICAL /* undef for developing */ ++#define CONFIG_SETUP_MEMORY_TAGS 1 ++#define CONFIG_INITRD_TAG 1 ++ ++/* ++ * High Level Configuration Options ++ * (easy to change) ++ */ ++#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ ++#define PXALCD 1 /* Using the PXA display controller */ ++#define CONFIG_LCD 1 ++ ++#define CONFIG_MMC 1 ++#define BOARD_LATE_INIT 1 ++ ++#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ ++ ++/* ++ * Size of malloc() pool ++ */ ++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) ++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ ++#define CFG_MMU_SPACE_RESERVED (1<<14) ++ ++/* ++ * Hardware drivers ++ */ ++#define CONFIG_DRIVER_SMC91111 ++#define CONFIG_SMC91111_BASE 0x10000300 ++#define CONFIG_SMC_USE_32_BIT ++ ++/* ++ * select serial console configuration ++ */ ++#define CONFIG_FFUART 1 /* we use FFUART on BD2003 */ ++ ++/* allow to overwrite serial and ethaddr */ ++//#define CONFIG_ENV_OVERWRITE ++ ++#define CONFIG_BAUDRATE 115200 ++ ++#define SKIP_COMMANDS ( CFG_CMD_MISC \ ++ | CFG_CMD_BDI \ ++ | CFG_CMD_BOOTD \ ++ | CFG_CMD_LOADS \ ++ | CFG_CMD_LOADB \ ++ | CFG_CMD_ITEST \ ++ | CFG_CMD_FPGA \ ++ | CFG_CMD_ECHO \ ++ | CFG_CMD_DIAG \ ++ | CFG_CMD_DATE \ ++ | CFG_CMD_BOOTP \ ++ | CFG_CMD_NFS \ ++ ) ++// | CFG_CMD_FLASH ++// | CFG_CMD_DHCP ++// | CFG_CMD_NET ++// | CFG_CMD_MEMORY ++// | CFG_CMD_ENV ++ ++#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL \ ++ | CFG_CMD_MMC \ ++ | CFG_CMD_FAT \ ++ | CFG_CMD_LCDPANEL \ ++ | CFG_CMD_FLASH \ ++ | CFG_CMD_DHCP \ ++ | CFG_CMD_ENV \ ++ | CFG_CMD_BMP) & ~(SKIP_COMMANDS) ) ++ ++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ ++#include ++#define CONFIG_BOOTDELAY 3 ++#define CONFIG_BOOTCOMMAND "mmcinit; " \ ++ "fatload mmc 0 a0000000 init.scr ; autoscr a0000000 ; " ++#define CONFIG_BOOTARGS "console=ttyS0,115200 DEBUG=1 ENV=/etc/bashrc init=/linuxrc rw mtdparts=phys:1024k(armboot),256k(params),-(rootfs1) root=/dev/mtdblock3 rootfstype=cramfs" ++#define CONFIG_CMDLINE_TAG ++ ++#define CONFIG_GZIP ++ ++/* ++ * Choose one of the following: ++ * ++ * hitachi_qvga ++ * sharp_qvga ++ * hitachi_hvga ++ * sharp_vga ++ * hitachi_wvga - 7 or 9 inch ++ */ ++#ifndef DA320X240 ++#define DA320X240 0 ++#define DA640X240 1 ++#define DA800X480 2 ++#define DA640X480 3 ++#define DA240X320 4 ++#define DA800X600 5 ++#define DA1024X768 6 ++#define DP480X320 7 ++#define DP320X240 8 ++#define DL122X32 9 ++#endif ++ ++#if DISPLAY_TYPE == DA640X240 ++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_hvga" "\0" ++#elif DISPLAY_TYPE == DA240X320 ++#define CONFIG_EXTRA_ENV_SETTINGS "panel=qvga_portrait" "\0" ++#elif DISPLAY_TYPE == DA320X240 ++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_qvga" "\0" ++#elif DISPLAY_TYPE == DA8000X480 ++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_wvga" "\0" ++#elif DISPLAY_TYPE == DA640X480 ++#define CONFIG_EXTRA_ENV_SETTINGS "panel=sharp_vga" "\0" ++#elif DISPLAY_TYPE == DA800X480 ++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_wvga" "\0" ++#elif DISPLAY_TYPE == DA1024X768 ++#define CONFIG_EXTRA_ENV_SETTINGS "panel=crt1024x768" "\0" ++#else ++#error No display selected ++#endif ++ ++#define LCD_BPP LCD_COLOR8 ++ ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ ++#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ ++#endif ++ ++/* ++ * Miscellaneous configurable options ++ */ ++#define CFG_HUSH_PARSER 1 ++#define CFG_PROMPT_HUSH_PS2 "> " ++ ++#define CFG_LONGHELP /* undef to save memory */ ++#ifdef CFG_HUSH_PARSER ++#define CFG_PROMPT "$ " /* Monitor Command Prompt */ ++#else ++#define CFG_PROMPT "=> " /* Monitor Command Prompt */ ++#endif ++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ ++#define CFG_MAXARGS 16 /* max number of command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ ++#define CFG_DEVICE_NULLDEV 1 ++ ++#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ ++#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ ++ ++#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ ++ ++#define CFG_LOAD_ADDR 0xa0030000 /* default load address */ ++ ++#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ ++#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ ++ ++ /* valid baudrates */ ++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } ++#define CFG_MMC_BASE 0xF0000000 ++ ++/* ++ * Stack sizes ++ * ++ * The stack sizes are set up in start.S using the settings below ++ */ ++#define CONFIG_STACKSIZE (128*1024) /* regular stack */ ++#ifdef CONFIG_USE_IRQ ++#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ ++#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ ++#endif ++ ++/* ++ * Physical Memory Map ++ */ ++#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ ++#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ ++#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ ++ ++#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ ++#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ ++#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ ++#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ ++#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ ++ ++#define CFG_DRAM_BASE 0xa0000000 ++#define CFG_DRAM_SIZE 0x04000000 ++ ++ ++/* ++ * Memory settings ++ */ ++#define CFG_MSC0_VAL 0x23F223F2 ++#define CFG_MSC1_VAL 0x3FF1A441 ++#define CFG_MSC2_VAL 0x7FF97FF1 ++#define CFG_MDCNFG_VAL 0x00001AC9 ++#define CFG_MDREFR_VAL 0x00018018 ++#define CFG_MDMRS_VAL 0x00000000 ++ ++/* ++ * FLASH and environment organization ++ */ ++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ ++#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ ++ ++/* timeout values are in ticks */ ++#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ ++#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ ++ ++/* ++ * Environment is saved in flash at offset 1MB ++ */ ++#define CFG_ENV_IS_IN_FLASH 1 ++#define CFG_FLASH_BASE 0 ++#define CFG_ENV_ADDR ((CFG_FLASH_BASE)+0x100000) /* Addr of Environment Sector */ ++#define CFG_ENV_OFFSET ((CFG_ENV_ADDR)-(CFG_FLASH_BASE)) ++#define CFG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */ ++ ++/* ++ * GPIO settings ++ */ ++#define CFG_GPSR0_VAL 0x00008000 ++#define CFG_GPSR1_VAL 0x00FC0382 ++#define CFG_GPSR2_VAL 0x0001FFFF ++#define CFG_GPCR0_VAL 0x00000000 ++#define CFG_GPCR1_VAL 0x00000000 ++#define CFG_GPCR2_VAL 0x00000000 ++#define CFG_GPDR0_VAL 0x0060A800 ++#define CFG_GPDR1_VAL 0x00FF0382 ++#define CFG_GPDR2_VAL 0x0001C000 ++#define CFG_GAFR0_L_VAL 0x98400000 ++#define CFG_GAFR0_U_VAL 0x00002950 ++#define CFG_GAFR1_L_VAL 0x000A9558 ++#define CFG_GAFR1_U_VAL 0x0005AAAA ++#define CFG_GAFR2_L_VAL 0xA0000000 ++#define CFG_GAFR2_U_VAL 0x00000002 ++ ++#define CFG_PSSR_VAL 0x20 ++ ++/* ++ * PCMCIA and CF Interfaces ++ */ ++#define CFG_MECR_VAL 0x00000000 ++#define CFG_MCMEM0_VAL 0x00010504 ++#define CFG_MCMEM1_VAL 0x00010504 ++#define CFG_MCATT0_VAL 0x00010504 ++#define CFG_MCATT1_VAL 0x00010504 ++#define CFG_MCIO0_VAL 0x00004715 ++#define CFG_MCIO1_VAL 0x00004715 ++ ++#ifndef __ASSEMBLY__ ++ ++extern unsigned long const fbStart ; ++extern unsigned long paletteRegs ; ++ ++#endif /* _ASMLANGUAGE */ ++ ++#endif ++ +diff -u -r --new-file u-boot-1.1.2/include/configs/.cvsignore u-boot-1.1.2-neon/include/configs/.cvsignore +--- u-boot-1.1.2/include/configs/.cvsignore 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/include/configs/.cvsignore 2007-08-11 21:07:21.000000000 +0200 +@@ -0,0 +1 @@ ++select.h +diff -u -r --new-file u-boot-1.1.2/include/configs/halogen.h u-boot-1.1.2-neon/include/configs/halogen.h +--- u-boot-1.1.2/include/configs/halogen.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/include/configs/halogen.h 2007-08-11 21:07:21.000000000 +0200 +@@ -0,0 +1,325 @@ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++/* ++ * halogen.h ++ * ++ * This header file declares the configuration constants for the Boundary ++ * Devices Halogen (PXA-270) boards. ++ * ++ * Change History : ++ * ++ * $Log: halogen.h,v $ ++ * Revision 1.6 2005/07/18 01:51:59 tkisky ++ * -define display types ++ * ++ * Revision 1.5 2005/07/17 22:52:10 ericn ++ * -fix comment ++ * ++ * Revision 1.4 2005/07/17 22:36:37 ericn ++ * -merge w/boundaryLib ++ * ++ * Revision 1.3 2005/07/16 16:26:00 ericn ++ * -fix name, memsize ++ * ++ * Revision 1.2 2005/07/10 14:32:45 ericn ++ * -include USB ++ * ++ * Revision 1.1 2005/07/04 16:40:32 ericn ++ * -Initial import ++ * ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ * Copyright Boundary Devices, Inc. 2005 ++ */ ++ ++/* ++ * If we are developing, we might want to start armboot from ram ++ * so we MUST NOT initialize critical regs like mem-timing ... ++ */ ++#include "select.h" ++ ++#define CONFIG_INIT_CRITICAL /* undef for developing */ ++#define CONFIG_SETUP_MEMORY_TAGS 1 ++#define CONFIG_INITRD_TAG 1 ++ ++/* ++ * High Level Configuration Options ++ * (easy to change) ++ */ ++#define CONFIG_PXA270 1 /* This is a PXA270 CPU */ ++#define CONFIG_PXA27X 1 /* Which is a PXA27X */ ++ ++#define PXALCD 1 /* Using the PXA display controller */ ++#define CONFIG_LCD 1 ++ ++#define CONFIG_MMC 1 ++#define BOARD_LATE_INIT 1 ++ ++#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ ++ ++/* ++ * Size of malloc() pool ++ */ ++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) ++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ ++#define CFG_MMU_SPACE_RESERVED (1<<14) ++ ++/* ++ * Hardware drivers ++ */ ++#define CONFIG_DRIVER_SMC91111 ++#define CONFIG_SMC91111_BASE 0x10000300 ++#define CONFIG_SMC_USE_32_BIT ++ ++/************************************************************ ++ * USB support ++ ************************************************************/ ++#define LITTLEENDIAN 1 /* Needed by usb_ohci.c */ ++#define CFG_DEVICE_DEREGISTER 1 /* Needed by usb_kbd */ ++#define CONFIG_DOS_PARTITION 1 ++#define CONFIG_USB_OHCI 1 ++#define CONFIG_USB_KEYBOARD 1 ++#define CONFIG_USB_STORAGE 1 ++ ++/* ++ * select serial console configuration ++ */ ++#define CONFIG_FFUART 1 /* we use FFUART on HALOGEN */ ++ ++/* allow to overwrite serial and ethaddr */ ++//#define CONFIG_ENV_OVERWRITE ++ ++#define CONFIG_BAUDRATE 115200 ++ ++#define SKIP_COMMANDS ( CFG_CMD_MISC \ ++ | CFG_CMD_BDI \ ++ | CFG_CMD_BOOTD \ ++ | CFG_CMD_LOADS \ ++ | CFG_CMD_LOADB \ ++ | CFG_CMD_ITEST \ ++ | CFG_CMD_FPGA \ ++ | CFG_CMD_ECHO \ ++ | CFG_CMD_DIAG \ ++ | CFG_CMD_DATE \ ++ | CFG_CMD_BOOTP \ ++ | CFG_CMD_NFS \ ++ ) ++// | CFG_CMD_FLASH ++// | CFG_CMD_DHCP ++// | CFG_CMD_NET ++// | CFG_CMD_MEMORY ++// | CFG_CMD_ENV ++ ++#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL \ ++ | CFG_CMD_MMC \ ++ | CFG_CMD_FAT \ ++ | CFG_CMD_LCDPANEL \ ++ | CFG_CMD_FLASH \ ++ | CFG_CMD_DHCP \ ++ | CFG_CMD_ENV \ ++ | CFG_CMD_USB \ ++ | CFG_CMD_BMP) & ~(SKIP_COMMANDS) ) ++ ++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ ++#include ++#define CONFIG_BOOTDELAY 3 ++#define CONFIG_BOOTCOMMAND "mmcinit; " \ ++ "fatload mmc 0 a0000000 init.scr ; autoscr a0000000 ; " ++#define CONFIG_BOOTARGS "console=ttyS0,115200 DEBUG=1 ENV=/etc/bashrc init=/linuxrc rw mtdparts=phys:1024k(armboot),256k(params),-(rootfs1) root=/dev/mtdblock3 rootfstype=cramfs" ++#define CONFIG_CMDLINE_TAG ++ ++#define CONFIG_GZIP ++ ++/* ++ * Choose one of the following: ++ * ++ * hitachi_qvga ++ * sharp_qvga ++ * hitachi_hvga ++ * sharp_vga ++ * hitachi_wvga - 7 or 9 inch ++ */ ++#ifndef DA320X240 ++#define DA320X240 0 ++#define DA640X240 1 ++#define DA800X480 2 ++#define DA640X480 3 ++#define DA240X320 4 ++#define DA800X600 5 ++#define DA1024X768 6 ++#define DP480X320 7 ++#define DP320X240 8 ++#define DL122X32 9 ++#endif ++ ++#if DISPLAY_TYPE == DA640X240 ++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_hvga" "\0" ++#elif DISPLAY_TYPE == DA240X320 ++#define CONFIG_EXTRA_ENV_SETTINGS "panel=qvga_portrait" "\0" ++#elif DISPLAY_TYPE == DA320X240 ++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_qvga" "\0" ++#elif DISPLAY_TYPE == DA8000X480 ++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_wvga" "\0" ++#elif DISPLAY_TYPE == DA640X480 ++#define CONFIG_EXTRA_ENV_SETTINGS "panel=sharp_vga" "\0" ++#elif DISPLAY_TYPE == DA800X480 ++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_wvga" "\0" ++#elif DISPLAY_TYPE == DA1024X768 ++#define CONFIG_EXTRA_ENV_SETTINGS "panel=crt1024x768" "\0" ++#else ++#error No display selected ++#endif ++ ++#define LCD_BPP LCD_COLOR8 ++ ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ ++#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ ++#endif ++ ++/* ++ * Miscellaneous configurable options ++ */ ++#define CFG_HUSH_PARSER 1 ++#define CFG_PROMPT_HUSH_PS2 "> " ++ ++#define CFG_LONGHELP /* undef to save memory */ ++#ifdef CFG_HUSH_PARSER ++#define CFG_PROMPT "$ " /* Monitor Command Prompt */ ++#else ++#define CFG_PROMPT "=> " /* Monitor Command Prompt */ ++#endif ++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ ++#define CFG_MAXARGS 16 /* max number of command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ ++#define CFG_DEVICE_NULLDEV 1 ++ ++#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ ++#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ ++ ++#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ ++ ++#define CFG_LOAD_ADDR 0xa0030000 /* default load address */ ++ ++#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ ++#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ ++ ++ /* valid baudrates */ ++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } ++#define CFG_MMC_BASE 0xF0000000 ++ ++/* ++ * Stack sizes ++ * ++ * The stack sizes are set up in start.S using the settings below ++ */ ++#define CONFIG_STACKSIZE (128*1024) /* regular stack */ ++#ifdef CONFIG_USE_IRQ ++#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ ++#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ ++#endif ++ ++/* ++ * Physical Memory Map ++ */ ++#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ ++#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ ++#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ ++ ++#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ ++#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ ++#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ ++#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ ++#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ ++ ++#define CFG_DRAM_BASE 0xa0000000 ++#define CFG_DRAM_SIZE 0x04000000 ++ ++ ++/* ++ * Memory settings ++ */ ++#define CFG_MSC0_VAL 0x23F223F2 ++#define CFG_MSC1_VAL 0x3FF1A441 ++#define CFG_MSC2_VAL 0x7FF97FF1 ++#define CFG_MDCNFG_VAL 0x00001AC9 ++#define CFG_MDREFR_VAL 0x00018018 ++#define CFG_MDMRS_VAL 0x00000000 ++ ++/* ++ * FLASH and environment organization ++ */ ++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ ++#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ ++ ++/* timeout values are in ticks */ ++#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ ++#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ ++ ++/* ++ * Environment is saved in flash at offset 1MB ++ */ ++#define CFG_ENV_IS_IN_FLASH 1 ++#define CFG_FLASH_BASE 0 ++#define CFG_ENV_ADDR ((CFG_FLASH_BASE)+0x100000) /* Addr of Environment Sector */ ++#define CFG_ENV_OFFSET ((CFG_ENV_ADDR)-(CFG_FLASH_BASE)) ++#define CFG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */ ++ ++/* ++ * GPIO settings ++ */ ++#define CFG_GPSR0_VAL 0x00008000 ++#define CFG_GPSR1_VAL 0x00FC0382 ++#define CFG_GPSR2_VAL 0x0001FFFF ++#define CFG_GPCR0_VAL 0x00000000 ++#define CFG_GPCR1_VAL 0x00000000 ++#define CFG_GPCR2_VAL 0x00000000 ++#define CFG_GPDR0_VAL 0x0060A800 ++#define CFG_GPDR1_VAL 0x00FF0382 ++#define CFG_GPDR2_VAL 0x0001C000 ++#define CFG_GAFR0_L_VAL 0x98400000 ++#define CFG_GAFR0_U_VAL 0x00002950 ++#define CFG_GAFR1_L_VAL 0x000A9558 ++#define CFG_GAFR1_U_VAL 0x0005AAAA ++#define CFG_GAFR2_L_VAL 0xA0000000 ++#define CFG_GAFR2_U_VAL 0x00000002 ++ ++#define CFG_PSSR_VAL 0x20 ++ ++/* ++ * PCMCIA and CF Interfaces ++ */ ++#define CFG_MECR_VAL 0x00000000 ++#define CFG_MCMEM0_VAL 0x00010504 ++#define CFG_MCMEM1_VAL 0x00010504 ++#define CFG_MCATT0_VAL 0x00010504 ++#define CFG_MCATT1_VAL 0x00010504 ++#define CFG_MCIO0_VAL 0x00004715 ++#define CFG_MCIO1_VAL 0x00004715 ++ ++#ifndef __ASSEMBLY__ ++ ++extern unsigned long const fbStart ; ++extern unsigned long paletteRegs ; ++ ++#endif /* _ASMLANGUAGE */ ++ ++#endif ++ +diff -u -r --new-file u-boot-1.1.2/include/configs/neon.h u-boot-1.1.2-neon/include/configs/neon.h +--- u-boot-1.1.2/include/configs/neon.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/include/configs/neon.h 2007-08-11 21:07:21.000000000 +0200 +@@ -0,0 +1,395 @@ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++/* ++ * neon.h ++ * ++ * This header file declares the configuration constants for the Boundary ++ * Devices Neon board. ++ * ++ * Change History : ++ * ++ * $Log: neon.h,v $ ++ * Revision 1.27 2006/05/30 15:52:17 ericn ++ * -clear screen after SD wait loop ++ * ++ * Revision 1.26 2006/05/27 22:11:50 ericn ++ * -include 'not', 'sleep' commands, wait for SD, for prompt ++ * ++ * Revision 1.25 2005/10/22 02:09:31 ericn ++ * -add CONFIG_SUPPORT_VFAT ++ * ++ * Revision 1.24 2005/07/23 19:35:42 ericn ++ * -fix name ++ * ++ * Revision 1.23 2005/07/23 17:13:25 ericn ++ * -add USB support ++ * ++ * Revision 1.22 2005/07/18 01:48:15 tkisky ++ * -define display types ++ * ++ * Revision 1.21 2005/07/17 22:52:10 ericn ++ * -fix comment ++ * ++ * Revision 1.20 2005/07/17 22:36:37 ericn ++ * -merge w/boundaryLib ++ * ++ * Revision 1.19 2005/07/02 18:46:16 ericn ++ * -Neon always has CONFIG_SM501 ++ * ++ * Revision 1.18 2005/07/02 14:57:11 ericn ++ * -include INITRD tag ++ * ++ * Revision 1.17 2005/06/02 04:55:06 ericn ++ * -auto-choose qvga_portrait for DA240X320 ++ * ++ * Revision 1.16 2005/06/02 04:10:30 ericn ++ * -save environment in flash ++ * ++ * Revision 1.15 2005/05/08 22:07:31 ericn ++ * -added 1024x768, 800x480 options ++ * ++ * Revision 1.14 2005/05/05 04:11:53 ericn ++ * -add flash commands, sharp_vga display selector ++ * ++ * Revision 1.13 2005/05/05 03:22:20 ericn ++ * -change default load addr to WinCE's ++ * ++ * Revision 1.12 2005/05/04 04:22:23 ericn ++ * -updated to allow DHCP ++ * ++ * Revision 1.11 2005/05/03 15:28:56 ericn ++ * -include DHCP support ++ * ++ * Revision 1.10 2005/05/02 15:14:26 ericn ++ * -add SMC driver, remove hard-coded MAC ++ * ++ * Revision 1.9 2005/05/01 15:21:41 ericn ++ * -change crtPalette -> paletteRegs ++ * ++ * Revision 1.8 2005/04/28 03:41:23 ericn ++ * -pass RAM qty to Linux ++ * ++ * Revision 1.7 2005/04/28 03:35:32 ericn ++ * -default to cramfs ++ * ++ * Revision 1.6 2005/04/22 01:57:39 ericn ++ * -fix default boot args ++ * ++ * Revision 1.5 2005/04/20 09:05:36 tkisky ++ * -include select.h ++ * ++ * Revision 1.4 2005/04/18 13:49:10 ericn ++ * -default wvga, use init.scr ++ * ++ * Revision 1.3 2005/04/18 03:58:48 ericn ++ * -added autoscr, hush parser support ++ * ++ * Revision 1.2 2005/04/15 10:41:35 tkisky ++ * -remove LCD_XRES,LCD_YRES, remove extra mmcinit ++ * ++ * Revision 1.1 2005/04/09 17:49:25 ericn ++ * -Initial import ++ * ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ * Copyright Boundary Devices, Inc. 2005 ++ */ ++ ++/* ++ * If we are developing, we might want to start armboot from ram ++ * so we MUST NOT initialize critical regs like mem-timing ... ++ */ ++#include "select.h" ++ ++#define CONFIG_INIT_CRITICAL /* undef for developing */ ++#define CONFIG_SETUP_MEMORY_TAGS 1 ++#define CONFIG_INITRD_TAG 1 ++ ++/* ++ * High Level Configuration Options ++ * (easy to change) ++ */ ++#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ ++#define CONFIG_NEON 1 /* on a Neon Board */ ++#define CONFIG_SM501 1 ++#define CONFIG_LCD 1 ++ ++#define CONFIG_MMC 1 ++#define BOARD_LATE_INIT 1 ++ ++#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ ++ ++/* ++ * Size of malloc() pool ++ */ ++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) ++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ ++#define CFG_MMU_SPACE_RESERVED (1<<14) ++ ++/* ++ * Hardware drivers ++ */ ++#define CONFIG_DRIVER_SMC91111 ++#define CONFIG_SMC91111_BASE 0x10000300 ++#define CONFIG_SMC_USE_32_BIT ++ ++/************************************************************ ++ * USB support ++ ************************************************************/ ++#define LITTLEENDIAN 1 /* Needed by usb_ohci.c */ ++#define CFG_DEVICE_DEREGISTER 1 /* Needed by usb_kbd */ ++#define CONFIG_DOS_PARTITION 1 ++#define CONFIG_USB_OHCI 1 ++#define CONFIG_USB_KEYBOARD 1 ++#define CONFIG_USB_STORAGE 1 ++ ++/* ++ * select serial console configuration ++ */ ++#define CONFIG_FFUART 1 /* we use FFUART on NEON */ ++ ++/* allow to overwrite serial and ethaddr */ ++//#define CONFIG_ENV_OVERWRITE ++ ++#define CONFIG_BAUDRATE 115200 ++ ++#define SKIP_COMMANDS ( CFG_CMD_BDI \ ++ | CFG_CMD_BOOTD \ ++ | CFG_CMD_LOADS \ ++ | CFG_CMD_LOADB \ ++ | CFG_CMD_ITEST \ ++ | CFG_CMD_FPGA \ ++ | CFG_CMD_ECHO \ ++ | CFG_CMD_DIAG \ ++ | CFG_CMD_DATE \ ++ | CFG_CMD_BOOTP \ ++ | CFG_CMD_NFS \ ++ ) ++// | CFG_CMD_FLASH ++// | CFG_CMD_DHCP ++// | CFG_CMD_NET ++// | CFG_CMD_MEMORY ++// | CFG_CMD_ENV ++ ++#define CONFIG_SUPPORT_VFAT ++#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL \ ++ | CFG_CMD_MMC \ ++ | CFG_CMD_FAT \ ++ | CFG_CMD_LCDPANEL \ ++ | CFG_CMD_FLASH \ ++ | CFG_CMD_DHCP \ ++ | CFG_CMD_ENV \ ++ | CFG_CMD_USB \ ++ | CFG_CMD_NOT \ ++ | CFG_CMD_MISC \ ++ | CFG_CMD_BMP) & ~(SKIP_COMMANDS) ) ++ ++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ ++#include ++#define CONFIG_BOOTDELAY 3 ++#define CONFIG_BOOTCOMMAND "while not mmcdet ; do cls ; lecho \"insert SD card\" ; sleep 1 ; done ; cls" \ ++ "if mmcwp ; then lecho \"write protected\" ; else lecho \"not write protected\" ; fi ; " \ ++ "mmcinit; " \ ++ "if fatload mmc 0 a0000000 init.scr ; then autoscr a0000000 ; fi" ++#define CONFIG_BOOTARGS "console=ttyS0,115200 DEBUG=1 ENV=/etc/bashrc init=/linuxrc rw mtdparts=phys:1024k(armboot),256k(params),-(rootfs1) root=/dev/mtdblock3 rootfstype=cramfs" ++#define CONFIG_CMDLINE_TAG ++ ++#define CONFIG_GZIP ++ ++#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ ++#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" ++#define CONFIG_AUTOBOOT_DELAY_STR "\x1b\x1b\x1b" ++ ++/* ++ * Choose one of the following: ++ * ++ * hitachi_qvga ++ * sharp_qvga ++ * hitachi_hvga ++ * sharp_vga ++ * hitachi_wvga - 7 or 9 inch ++ */ ++#ifndef DA320X240 ++#define DA320X240 0 ++#define DA640X240 1 ++#define DA800X480 2 ++#define DA640X480 3 ++#define DA240X320 4 ++#define DA800X600 5 ++#define DA1024X768 6 ++#define DP480X320 7 ++#define DP320X240 8 ++#define DL122X32 9 ++#endif ++ ++#if DISPLAY_TYPE == DA640X240 ++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_hvga" "\0" ++#elif DISPLAY_TYPE == DA240X320 ++#define CONFIG_EXTRA_ENV_SETTINGS "panel=qvga_portrait" "\0" ++#elif DISPLAY_TYPE == DA320X240 ++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_qvga" "\0" ++#elif DISPLAY_TYPE == DA8000X480 ++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_wvga" "\0" ++#elif DISPLAY_TYPE == DA640X480 ++#define CONFIG_EXTRA_ENV_SETTINGS "panel=sharp_vga" "\0" ++#elif DISPLAY_TYPE == DA800X480 ++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_wvga" "\0" ++#elif DISPLAY_TYPE == DA1024X768 ++#define CONFIG_EXTRA_ENV_SETTINGS "panel=crt1024x768" "\0" ++#else ++#error No display selected ++#endif ++ ++#define LCD_BPP LCD_COLOR8 ++ ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ ++#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ ++#endif ++ ++/* ++ * Miscellaneous configurable options ++ */ ++#define CFG_HUSH_PARSER 1 ++#define CFG_PROMPT_HUSH_PS2 "> " ++ ++#define CFG_LONGHELP /* undef to save memory */ ++#ifdef CFG_HUSH_PARSER ++#define CFG_PROMPT "$ " /* Monitor Command Prompt */ ++#else ++#define CFG_PROMPT "=> " /* Monitor Command Prompt */ ++#endif ++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ ++#define CFG_MAXARGS 16 /* max number of command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ ++#define CFG_DEVICE_NULLDEV 1 ++ ++#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ ++#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ ++ ++#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ ++ ++#define CFG_LOAD_ADDR 0xa0030000 /* default load address */ ++ ++#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ ++#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ ++ ++ /* valid baudrates */ ++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } ++#define CFG_MMC_BASE 0xF0000000 ++ ++/* ++ * Stack sizes ++ * ++ * The stack sizes are set up in start.S using the settings below ++ */ ++#define CONFIG_STACKSIZE (128*1024) /* regular stack */ ++#ifdef CONFIG_USE_IRQ ++#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ ++#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ ++#endif ++ ++/* ++ * Physical Memory Map ++ */ ++#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ ++#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ ++#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ ++ ++#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ ++#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ ++#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ ++#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ ++#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ ++ ++#define CFG_DRAM_BASE 0xa0000000 ++#define CFG_DRAM_SIZE 0x04000000 ++ ++ ++/* ++ * Memory settings ++ */ ++#define CFG_MSC0_VAL 0x23F223F2 ++#define CFG_MSC1_VAL 0x3FF1A441 ++#define CFG_MSC2_VAL 0x7FF97FF1 ++#define CFG_MDCNFG_VAL 0x00001AC9 ++#define CFG_MDREFR_VAL 0x00018018 ++#define CFG_MDMRS_VAL 0x00000000 ++ ++/* ++ * FLASH and environment organization ++ */ ++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ ++#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ ++ ++/* timeout values are in ticks */ ++#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ ++#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ ++ ++/* ++ * Environment is saved in flash at offset 1MB ++ */ ++#define CFG_ENV_IS_IN_FLASH 1 ++#define CFG_FLASH_BASE 0 ++#define CFG_ENV_ADDR ((CFG_FLASH_BASE)+0x100000) /* Addr of Environment Sector */ ++#define CFG_ENV_OFFSET ((CFG_ENV_ADDR)-(CFG_FLASH_BASE)) ++#define CFG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */ ++ ++/* ++ * GPIO settings ++ */ ++#define CFG_GPSR0_VAL 0x00008000 ++#define CFG_GPSR1_VAL 0x00FC0382 ++#define CFG_GPSR2_VAL 0x0001FFFF ++#define CFG_GPCR0_VAL 0x00000000 ++#define CFG_GPCR1_VAL 0x00000000 ++#define CFG_GPCR2_VAL 0x00000000 ++#define CFG_GPDR0_VAL 0x0060A800 ++#define CFG_GPDR1_VAL 0x00FF0382 ++#define CFG_GPDR2_VAL 0x0001C000 ++#define CFG_GAFR0_L_VAL 0x98400000 ++#define CFG_GAFR0_U_VAL 0x00002950 ++#define CFG_GAFR1_L_VAL 0x000A9558 ++#define CFG_GAFR1_U_VAL 0x0005AAAA ++#define CFG_GAFR2_L_VAL 0xA0000000 ++#define CFG_GAFR2_U_VAL 0x00000002 ++ ++#define CFG_PSSR_VAL 0x20 ++ ++/* ++ * PCMCIA and CF Interfaces ++ */ ++#define CFG_MECR_VAL 0x00000000 ++#define CFG_MCMEM0_VAL 0x00010504 ++#define CFG_MCMEM1_VAL 0x00010504 ++#define CFG_MCATT0_VAL 0x00010504 ++#define CFG_MCATT1_VAL 0x00010504 ++#define CFG_MCIO0_VAL 0x00004715 ++#define CFG_MCIO1_VAL 0x00004715 ++ ++#ifndef __ASSEMBLY__ ++ ++extern unsigned long const fbStart ; ++extern unsigned long paletteRegs ; ++ ++#endif /* _ASMLANGUAGE */ ++ ++#endif ++ +diff -u -r --new-file u-boot-1.1.2/include/fat.h u-boot-1.1.2-neon/include/fat.h +--- u-boot-1.1.2/include/fat.h 2004-04-23 22:32:07.000000000 +0200 ++++ u-boot-1.1.2-neon/include/fat.h 2007-08-11 21:07:21.000000000 +0200 +@@ -177,13 +177,13 @@ + + /* Private filesystem parameters */ + typedef struct { ++ __u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */ + int fatsize; /* Size of FAT in bits */ + __u16 fatlength; /* Length of FAT in sectors */ + __u16 fat_sect; /* Starting sector of the FAT */ + __u16 rootdir_sect; /* Start sector of root directory */ + __u16 clust_size; /* Size of clusters in sectors */ + short data_begin; /* The sector of the first cluster, can be negative */ +- __u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */ + int fatbufnum; /* Used by get_fatent, init to -1 */ + } fsdata; + +diff -u -r --new-file u-boot-1.1.2/include/lcd.h u-boot-1.1.2-neon/include/lcd.h +--- u-boot-1.1.2/include/lcd.h 2004-10-10 01:26:01.000000000 +0200 ++++ u-boot-1.1.2-neon/include/lcd.h 2007-08-11 21:07:21.000000000 +0200 +@@ -31,7 +31,6 @@ + + extern char lcd_is_enabled; + +-extern int lcd_line_length; + extern int lcd_color_fg; + extern int lcd_color_bg; + +@@ -53,6 +52,7 @@ + ushort vl_row; /* Number of rows (i.e. 480) */ + ushort vl_width; /* Width of display area in millimeters */ + ushort vl_height; /* Height of display area in millimeters */ ++ int vl_lcd_line_length; + + /* LCD configuration register */ + u_char vl_clkp; /* Clock polarity */ +@@ -77,7 +77,7 @@ + + extern vidinfo_t panel_info; + +-#elif defined CONFIG_PXA250 ++#elif defined( PXALCD ) + /* + * PXA LCD DMA descriptor + */ +@@ -119,6 +119,7 @@ + ushort vl_row; /* Number of rows (i.e. 480) */ + ushort vl_width; /* Width of display area in millimeters */ + ushort vl_height; /* Height of display area in millimeters */ ++ int vl_lcd_line_length; + + /* LCD configuration register */ + u_char vl_clkp; /* Clock polarity */ +@@ -148,7 +149,29 @@ + + extern vidinfo_t panel_info; + +-#endif /* CONFIG_MPC823 or CONFIG_PXA250 */ ++#if defined( CONFIG_PXA250 ) ++ #define PALETTEVAL_TYPE u16 ++#elif defined( CONFIG_PXA270 ) ++ #define PALETTEVAL_TYPE u32 ++#else ++#error no processor defined ++#endif ++ ++#elif defined( CONFIG_SM501 ) ++ ++/* ++ * LCD controller stucture for PXA CPU ++ */ ++typedef struct vidinfo { ++ ushort vl_col; /* Number of columns (i.e. 640) */ ++ ushort vl_row; /* Number of rows (i.e. 480) */ ++ int vl_lcd_line_length; ++ u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ ++} vidinfo_t; ++ ++extern vidinfo_t panel_info; ++ ++#endif /* CONFIG_MPC823 */ + + /* Video functions */ + +@@ -272,7 +295,7 @@ + #endif + + #define CONSOLE_COLS (panel_info.vl_col / VIDEO_FONT_WIDTH) +-#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * lcd_line_length) ++#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * panel_info.vl_lcd_line_length) + #define CONSOLE_ROW_FIRST (lcd_console_address) + #define CONSOLE_ROW_SECOND (lcd_console_address + CONSOLE_ROW_SIZE) + #define CONSOLE_ROW_LAST (lcd_console_address + CONSOLE_SIZE \ +diff -u -r --new-file u-boot-1.1.2/include/lcd_panels.h u-boot-1.1.2-neon/include/lcd_panels.h +--- u-boot-1.1.2/include/lcd_panels.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/include/lcd_panels.h 2007-08-11 21:07:21.000000000 +0200 +@@ -0,0 +1,83 @@ ++#ifndef __LCD_PANELS_H__ ++#define __LCD_PANELS_H__ "$Id: lcd_panels.h,v 1.3 2005/06/02 04:03:37 ericn Exp $" ++ ++/* ++ * lcd_panels.h ++ * ++ * This header file declares the lcd_panel_info_t ++ * data type and the num_lcd_panels and lcd_panels ++ * constants for use in initializing a variety of displays. ++ * ++ * Note that this is based on the pxafb_mach_info structure ++ * in linux-2.4.19/drivers/video/pxafb.h (Nico's patches), ++ * but differs in a couple of respects: ++ * ++ * Doesn't support the color-mapping stuff ++ * Includes an 'active' flag ++ * ++ * Doesn't include the lccr0 and lccr3 fields, since most of ++ * the fields in those registers are display controller options, ++ * not panel options, and the others (so far) can have reasonable ++ * defaults. When (if) we need to support a non-standard display, ++ * we can fill in the blanks with defaults in the previously ++ * supported displays and compute lccr0 and lccr3. ++ * ++ * Change History : ++ * ++ * $Log: lcd_panels.h,v $ ++ * Revision 1.3 2005/06/02 04:03:37 ericn ++ * -added rotation field ++ * ++ * Revision 1.2 2005/04/30 20:33:36 ericn ++ * -added CRT support ++ * ++ * Revision 1.1 2005/04/09 17:49:18 ericn ++ * -Initial import ++ * ++ * ++ * Copyright Boundary Devices, Inc. 2005 ++ */ ++ ++struct lcd_panel_info_t { ++ char const *name ; ++ unsigned long pixclock; ++ ++ unsigned short xres; ++ unsigned short yres; ++ ++ unsigned act_high ; // clock is active high ++ unsigned hsync_len; ++ unsigned left_margin; ++ unsigned right_margin; ++ unsigned vsync_len; ++ unsigned upper_margin; ++ unsigned lower_margin; ++ unsigned active ; // active matrix (TFT) LCD ++ unsigned crt ; // 1 == CRT, not LCD ++ unsigned rotation ; ++}; ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++extern unsigned const num_lcd_panels ; ++extern struct lcd_panel_info_t const * const lcd_panels ; ++ ++extern struct lcd_panel_info_t const *find_lcd_panel( char const * name ); ++ ++ ++// ++// Each platform needs to define this routine, and ++// set cur_lcd_panel within ++// ++void set_lcd_panel( struct lcd_panel_info_t const *panel ); ++extern struct lcd_panel_info_t const *cur_lcd_panel ; ++void disable_lcd_panel( void ); ++ ++#ifdef __CPLUSPLUS ++}; ++#endif ++ ++#endif ++ +diff -u -r --new-file u-boot-1.1.2/include/part.h u-boot-1.1.2-neon/include/part.h +--- u-boot-1.1.2/include/part.h 2004-04-18 19:39:40.000000000 +0200 ++++ u-boot-1.1.2-neon/include/part.h 2007-08-11 21:07:21.000000000 +0200 +@@ -24,6 +24,48 @@ + #define _PART_H + #include + ++enum { ++/* These three have identical behaviour; use the second one if DOS fdisk gets ++ confused about extended/logical partitions starting past cylinder 1023. */ ++ DOS_EXTENDED_PARTITION = 5, ++ LINUX_EXTENDED_PARTITION = 0x85, ++ WIN98_EXTENDED_PARTITION = 0x0f, ++ ++ LINUX_SWAP_PARTITION = 0x82, ++ LINUX_RAID_PARTITION = 0xfd, /* autodetect RAID partition */ ++ ++ SOLARIS_X86_PARTITION = LINUX_SWAP_PARTITION, ++ ++ DM6_PARTITION = 0x54, /* has DDO: use xlated geom & offset */ ++ EZD_PARTITION = 0x55, /* EZ-DRIVE */ ++ DM6_AUX1PARTITION = 0x51, /* no DDO: use xlated geom */ ++ DM6_AUX3PARTITION = 0x53, /* no DDO: use xlated geom */ ++ ++ FREEBSD_PARTITION = 0xa5, /* FreeBSD Partition ID */ ++ OPENBSD_PARTITION = 0xa6, /* OpenBSD Partition ID */ ++ NETBSD_PARTITION = 0xa9, /* NetBSD Partition ID */ ++ BSDI_PARTITION = 0xb7, /* BSDI Partition ID */ ++/* Ours is not to wonder why.. */ ++ BSD_PARTITION = FREEBSD_PARTITION, ++ MINIX_PARTITION = 0x81, /* Minix Partition ID */ ++ PLAN9_PARTITION = 0x39, /* Plan 9 Partition ID */ ++ UNIXWARE_PARTITION = 0x63, /* Partition ID, same as */ ++ /* GNU_HURD and SCO Unix */ ++}; ++ ++struct partition { ++ unsigned char boot_ind; /* 0x80 - active */ ++ unsigned char head; /* starting head */ ++ unsigned char sector; /* starting sector */ ++ unsigned char cyl; /* starting cylinder */ ++ unsigned char sys_ind; /* What partition type */ ++ unsigned char end_head; /* end head */ ++ unsigned char end_sector; /* end sector */ ++ unsigned char end_cyl; /* end cylinder */ ++ unsigned int start_sect; /* starting sector counting from 0 */ ++ unsigned int nr_sects; /* nr of sectors in partition */ ++} __attribute__((packed)); ++ + typedef struct block_dev_desc { + int if_type; /* type of the interface */ + int dev; /* device number */ +@@ -118,4 +160,15 @@ + int test_part_amiga (block_dev_desc_t *dev_desc); + #endif + ++/* Value returned by `fnmatch' if STRING does not match PATTERN. */ ++#define FNM_NOMATCH 1 ++ ++/* Bits set in the FLAGS argument to `fnmatch'. */ ++#define FNM_PATHNAME (1 << 0) /* No wildcard can ever match `/'. */ ++#define FNM_NOESCAPE (1 << 1) /* Backslashes don't quote special chars. */ ++#define FNM_PERIOD (1 << 2) /* Leading `.' is matched only explicitly. */ ++#define FNM_NOSYS (-1) ++ ++int fnmatch(const char *pattern, const char *string, int flags); ++ + #endif /* _PART_H */ +diff -u -r --new-file u-boot-1.1.2/lib_arm/armlinux.c u-boot-1.1.2-neon/lib_arm/armlinux.c +--- u-boot-1.1.2/lib_arm/armlinux.c 2004-10-10 01:26:01.000000000 +0200 ++++ u-boot-1.1.2-neon/lib_arm/armlinux.c 2007-08-11 21:07:21.000000000 +0200 +@@ -29,6 +29,7 @@ + #ifdef CONFIG_HAS_DATAFLASH + #include + #endif ++#include "lcd_panels.h" + + /*cmd_boot.c*/ + extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +@@ -88,6 +89,16 @@ + + #ifdef CONFIG_CMDLINE_TAG + char *commandline = getenv ("bootargs"); ++ if( ( 0 != cur_lcd_panel ) && ( 0 != cur_lcd_panel->rotation ) ) ++ { ++ char temp[80]; ++ int addedLen = sprintf( temp, " fbrotation=%u", cur_lcd_panel->rotation ); ++ unsigned cmdLen = strlen( commandline ); ++ char *bigger = (char *)malloc( cmdLen + addedLen + 1 ); ++ strcpy( bigger, commandline ); ++ strcpy( bigger+cmdLen, temp ); ++ commandline = bigger ; ++ } + #endif + + theKernel = (void (*)(int, int, uint))ntohl(hdr->ih_ep); +@@ -365,6 +376,7 @@ + * We only use it to pass the address and size, the other entries + * in the tag_videolfb are not of interest. + */ ++#ifdef VESA_DISPLAY + params->hdr.tag = ATAG_VIDEOLFB; + params->hdr.size = tag_size (tag_videolfb); + +@@ -374,6 +386,7 @@ + params->u.videolfb.lfb_size = calc_fbsize(); + + params = tag_next (params); ++#endif + } + #endif /* CONFIG_VFD || CONFIG_LCD */ + +diff -u -r --new-file u-boot-1.1.2/lib_arm/board.c u-boot-1.1.2-neon/lib_arm/board.c +--- u-boot-1.1.2/lib_arm/board.c 2004-08-02 00:48:22.000000000 +0200 ++++ u-boot-1.1.2-neon/lib_arm/board.c 2007-08-11 21:07:21.000000000 +0200 +@@ -216,7 +216,10 @@ + #endif + + /* Pointer is writable since we allocated a register for it */ +- gd = (gd_t*)(_armboot_start - CFG_MALLOC_LEN - sizeof(gd_t)); ++#ifndef CFG_MMU_SPACE_RESERVED ++#define CFG_MMU_SPACE_RESERVED 0 ++#endif ++ gd = (gd_t*)(_armboot_start - CFG_MMU_SPACE_RESERVED - CFG_MALLOC_LEN - sizeof(gd_t)); + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("": : :"memory"); + +@@ -263,7 +266,7 @@ + #endif /* CONFIG_LCD */ + + /* armboot_start is defined in the board-specific linker script */ +- mem_malloc_init (_armboot_start - CFG_MALLOC_LEN); ++ mem_malloc_init (_armboot_start - CFG_MMU_SPACE_RESERVED - CFG_MALLOC_LEN); + + #if (CONFIG_COMMANDS & CFG_CMD_NAND) + puts ("NAND:"); +diff -u -r --new-file u-boot-1.1.2/make_all u-boot-1.1.2-neon/make_all +--- u-boot-1.1.2/make_all 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/make_all 2007-08-11 21:07:21.000000000 +0200 +@@ -0,0 +1,31 @@ ++#!/bin/sh ++halogen1_clock="416" ++halogen2_clock="416" ++bd2003_clock="400" ++neon_clock="400" ++neonb_clock="400" ++ ++SOFTWARE="LINUX" ++ ++targets="halogen1 halogen2 bd2003 neon neonb" ++for suff in $targets ; do ++ make distclean ; ++ REV="" ++ PLATFORM="$suff" ++ if [ $suff = "halogen1" ] ; then REV="1\n"; PLATFORM="halogen" ++ else ++ if [ $suff = "halogen2" ] ; then REV="2\n"; PLATFORM="halogen" ++ fi ++ fi ++ eval clock=\$$suff"_clock" ++ echo -e "DA640X240\n$REV$SOFTWARE\ny\n$clock\n" | make $PLATFORM"_config" ; ++ make u-boot.bin ; ++ mv u-boot.bin u-boot-$suff ++done ++ ++ ++for suff in $targets ; do ++ mv u-boot-$suff u-boot-$suff.bin ++done ++ ++zip u-boot-binaries.zip u-boot-*.bin +diff -u -r --new-file u-boot-1.1.2/Makefile u-boot-1.1.2-neon/Makefile +--- u-boot-1.1.2/Makefile 2004-12-19 10:58:11.000000000 +0100 ++++ u-boot-1.1.2-neon/Makefile 2007-08-11 21:17:14.000000000 +0200 +@@ -57,7 +57,7 @@ + CROSS_COMPILE = ppc_8xx- + endif + ifeq ($(ARCH),arm) +-CROSS_COMPILE = arm-linux- ++CROSS_COMPILE = arm-elf- + endif + ifeq ($(ARCH),i386) + ifeq ($(HOSTARCH),i386) +@@ -89,6 +89,9 @@ + ######################################################################### + # U-Boot objects....order is important (i.e. start must be first) + ++ifeq ($(CPU),pxa) ++OBJS = ++else + OBJS = cpu/$(CPU)/start.o + ifeq ($(CPU),i386) + OBJS += cpu/$(CPU)/start16.o +@@ -100,6 +103,7 @@ + ifeq ($(CPU),mpc85xx) + OBJS += cpu/$(CPU)/resetvec.o + endif ++endif + + LIBS = lib_generic/libgeneric.a + LIBS += board/$(BOARDDIR)/lib$(BOARD).a +@@ -121,7 +125,8 @@ + .PHONY : $(LIBS) + + # Add GCC lib +-PLATFORM_LIBS += --no-warn-mismatch -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc ++LIBGCC_DIRNAME := $(shell dirname "`$(CC) $(CFLAGS) -print-libgcc-file-name`") ++PLATFORM_LIBS += --no-warn-mismatch -L "$(LIBGCC_DIRNAME)" -lgcc + + + # The "tools" are needed early, so put this first +@@ -129,13 +134,14 @@ + SUBDIRS = tools \ + examples \ + post \ +- post/cpu ++ post/cpu \ ++ cpu/$(CPU) + .PHONY : $(SUBDIRS) + + ######################################################################### + ######################################################################### + +-ALL = u-boot.srec u-boot.bin System.map ++ALL = u-boot.srec u-boot.bin System.map init.scr upgrade.scr + + all: $(ALL) + +@@ -192,6 +198,12 @@ + grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ + sort > System.map + ++init.scr: board/$(BOARDDIR)/init.script ++ tools/mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "autoscript" -d $< $@ ++ ++upgrade.scr: upgrade.script ++ tools/mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "U-Boot upgrade script" -d $< $@ ++ + ######################################################################### + else + all install u-boot u-boot.srec depend dep: +@@ -203,6 +215,7 @@ + + unconfig: + @rm -f include/config.h include/config.mk board/*/config.tmp ++ @rm -f select.mk include/configs/select.h + + #======================================================================== + # PowerPC +@@ -1388,6 +1401,22 @@ + wepep250_config : unconfig + @./mkconfig $(@:_config=) arm pxa wepep250 + ++bd-neon_config : unconfig ++ @./mkconfig $(@:_config=) arm pxa neon ++ ./Configure --PLATFORM_TYPE=NEON ++ ++neonb_config : unconfig ++ @./mkconfig neon arm pxa neon ++ ./Configure --PLATFORM_TYPE=NEONB --SOFTWARE_TYPE=WINCE --DISPLAY_TYPE=DA640X240 ++ ++bd2003_config : unconfig ++ @./mkconfig $(@:_config=) arm pxa bd2003 ++ ./Configure --PLATFORM_TYPE=BD2003 ++ ++halogen_config : unconfig ++ @./mkconfig $(@:_config=) arm pxa halogen ++ ./Configure --PLATFORM_TYPE=HALOGEN ++ + xaeniax_config : unconfig + @./mkconfig $(@:_config=) arm pxa xaeniax + +@@ -1558,10 +1587,16 @@ + ######################################################################### + ######################################################################### + ++ifeq ($(HOSTOS),cygwin) ++FIND = /bin/find ++else ++FIND = find ++endif ++ + clean: +- find . -type f \ ++ $(FIND) . -type f \ + \( -name 'core' -o -name '*.bak' -o -name '*~' \ +- -o -name '*.o' -o -name '*.a' \) -print \ ++ -o -name '*.o' -o -name '*.a' -o -name '*.lst' \) -print \ + | xargs rm -f + rm -f examples/hello_world examples/timer \ + examples/eepro100_eeprom examples/sched \ +@@ -1575,7 +1610,7 @@ + rm -f board/trab/trab_fkt + + clobber: clean +- find . -type f \( -name .depend \ ++ $(FIND) . -type f \( -name .depend \ + -o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \ + -print0 \ + | xargs -0 rm -f +@@ -1585,6 +1620,8 @@ + rm -f tools/crc32.c tools/environment.c tools/env/crc32.c + rm -f tools/inca-swap-bytes cpu/mpc824x/bedbug_603e.c + rm -f include/asm/proc include/asm/arch include/asm ++ cd tools && rm -f *.exe ++ rm -f include/configs/select.h select.mk select.log + + mrproper \ + distclean: clobber unconfig +diff -u -r --new-file u-boot-1.1.2/patches/arm_flags.patch u-boot-1.1.2-neon/patches/arm_flags.patch +--- u-boot-1.1.2/patches/arm_flags.patch 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/patches/arm_flags.patch 2007-08-11 21:01:36.000000000 +0200 +@@ -0,0 +1,15 @@ ++ ++# ++# Patch managed by http://www.holgerschurig.de/patcher.html ++# ++ ++--- u-boot-1.1.2/cpu/pxa/config.mk~armflags +++++ u-boot-1.1.2/cpu/pxa/config.mk ++@@ -23,6 +23,6 @@ ++ # ++ ++ PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ ++- -mshort-load-bytes -msoft-float +++ -msoft-float ++ ++ PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100 +diff -u -r --new-file u-boot-1.1.2/patches/series u-boot-1.1.2-neon/patches/series +--- u-boot-1.1.2/patches/series 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/patches/series 2007-08-11 21:01:36.000000000 +0200 +@@ -0,0 +1,2 @@ ++arm_flags.patch -p1 ++u-boot-2006-06-03.patch.gz -p1 +Binary files u-boot-1.1.2/patches/u-boot-2006-06-03.patch.gz and u-boot-1.1.2-neon/patches/u-boot-2006-06-03.patch.gz differ +diff -u -r --new-file u-boot-1.1.2/.pc/applied-patches u-boot-1.1.2-neon/.pc/applied-patches +--- u-boot-1.1.2/.pc/applied-patches 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/.pc/applied-patches 2007-08-11 21:01:36.000000000 +0200 +@@ -0,0 +1 @@ ++arm_flags.patch +diff -u -r --new-file u-boot-1.1.2/.pc/arm_flags.patch/cpu/pxa/config.mk u-boot-1.1.2-neon/.pc/arm_flags.patch/cpu/pxa/config.mk +--- u-boot-1.1.2/.pc/arm_flags.patch/cpu/pxa/config.mk 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/.pc/arm_flags.patch/cpu/pxa/config.mk 2003-05-23 14:36:21.000000000 +0200 +@@ -0,0 +1,28 @@ ++# ++# (C) Copyright 2002 ++# Sysgo Real-Time Solutions, GmbH ++# Marius Groeger ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ ++ -mshort-load-bytes -msoft-float ++ ++PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100 +diff -u -r --new-file u-boot-1.1.2/.pc/.version u-boot-1.1.2-neon/.pc/.version +--- u-boot-1.1.2/.pc/.version 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/.pc/.version 2007-08-11 21:01:36.000000000 +0200 +@@ -0,0 +1 @@ ++2 +diff -u -r --new-file u-boot-1.1.2/README u-boot-1.1.2-neon/README +--- u-boot-1.1.2/README 2004-12-16 22:44:03.000000000 +0100 ++++ u-boot-1.1.2-neon/README 2007-08-11 21:07:19.000000000 +0200 +@@ -608,6 +608,7 @@ + CFG_CMD_ITEST Integer/string test of 2 values + CFG_CMD_JFFS2 * JFFS2 Support + CFG_CMD_KGDB * kgdb ++ CFG_CMD_LCDPANEL * Dynamic LCD Panel support + CFG_CMD_LOADB loadb + CFG_CMD_LOADS loads + CFG_CMD_MEMORY md, mm, nm, mw, cp, cmp, crc, base, +@@ -812,6 +813,9 @@ + for differential drivers: 0x00001000 + for single ended drivers: 0x00005000 + ++- Dynamic LCD Panel support ++ Allows the choice of an LCD panel through the environment. ++ Also allows prompting for panel characteristics. + + - MMC Support: + The MMC controller on the Intel PXA is supported. To +diff -u -r --new-file u-boot-1.1.2/tools/mkimage.c u-boot-1.1.2-neon/tools/mkimage.c +--- u-boot-1.1.2/tools/mkimage.c 2004-11-21 01:06:36.000000000 +0100 ++++ u-boot-1.1.2-neon/tools/mkimage.c 2007-08-11 21:07:22.000000000 +0200 +@@ -618,10 +618,10 @@ + printf ("Image Name: %.*s\n", IH_NMLEN, hdr->ih_name); + printf ("Created: %s", ctime(×tamp)); + printf ("Image Type: "); print_type(hdr); +- printf ("Data Size: %d Bytes = %.2f kB = %.2f MB\n", ++ printf ("Data Size: %ld Bytes = %.2f kB = %.2f MB\n", + size, (double)size / 1.024e3, (double)size / 1.048576e6 ); +- printf ("Load Address: 0x%08X\n", ntohl(hdr->ih_load)); +- printf ("Entry Point: 0x%08X\n", ntohl(hdr->ih_ep)); ++ printf ("Load Address: 0x%08lX\n", ntohl(hdr->ih_load)); ++ printf ("Entry Point: 0x%08lX\n", ntohl(hdr->ih_ep)); + + if (hdr->ih_type == IH_TYPE_MULTI || hdr->ih_type == IH_TYPE_SCRIPT) { + int i, ptrs; +@@ -640,7 +640,7 @@ + for (i=0; len_ptr[i]; ++i) { + size = ntohl(len_ptr[i]); + +- printf (" Image %d: %8d Bytes = %4d kB = %d MB\n", ++ printf (" Image %d: %8ld Bytes = %4ld kB = %ld MB\n", + i, size, size>>10, size>>20); + if (hdr->ih_type == IH_TYPE_SCRIPT && i > 0) { + /* +@@ -648,7 +648,7 @@ + * if planning to do something with + * multiple files + */ +- printf (" Offset = %08X\n", pos); ++ printf (" Offset = %08lX\n", pos); + } + /* copy_file() will pad the first files to even word align */ + size += 3; +diff -u -r --new-file u-boot-1.1.2/upgrade.script u-boot-1.1.2-neon/upgrade.script +--- u-boot-1.1.2/upgrade.script 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.1.2-neon/upgrade.script 2007-08-11 21:07:22.000000000 +0200 +@@ -0,0 +1,32 @@ ++lecho "---------> upgrade to newest U-Boot" ++echo "---------> upgrade to newest U-Boot" ++if fatload mmc 0 a0008000 u-boot-*.bin ; then ++ if cmp.b 0 a0008000 $filesize ; then ++ fatload mmc 0 a0008000 *.bmp ++ bmp display a0008000 ++ lecho 'Already upgraded. Latest U-Boot is installed' ; ++ echo 'Already upgraded. Latest U-Boot is installed' ; ++ if mmcwp ; then ++ lecho "write protected" ; ++ else ++ lecho "not write protected" ; ++ fi ++ else ++ lecho 'Old U-Boot found. Upgrading' ; ++ echo 'Old U-Boot found. Upgrading' ; ++ protect off all ; ++ lecho 'Erasing' ; ++ echo 'Erasing' ; ++ erase 0 3FFFF ; ++ lecho 'Programming' ; ++ echo 'Programming' ; ++ cp.b a0008000 0 $filesize ; ++ lecho 'Done programming. Cycle power' ; ++ echo 'Done programming. Cycle power' ; ++ fi ++else ++ lecho 'Error loading new U-Boot from SD card' ++ echo 'Error loading new U-Boot from SD card' ++ lecho 'Should have u-boot-neon-something.bin' ++ echo 'Should have u-boot-neon-something.bin' ++fi +\ No newline at end of file diff --git a/packages/u-boot/u-boot-1.1.2/u-boot-emetec.patch b/packages/u-boot/u-boot-1.1.2/u-boot-emetec.patch new file mode 100644 index 0000000000..ab3f106e71 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.2/u-boot-emetec.patch @@ -0,0 +1,2170 @@ +diff -uNr u-boot-1.1.2/.pc/.version u-boot-emetec-1.1.2/.pc/.version +--- u-boot-1.1.2/.pc/.version 2007-04-20 00:01:06.000000000 +0300 ++++ u-boot-emetec-1.1.2/.pc/.version 1970-01-01 02:00:00.000000000 +0200 +@@ -1 +0,0 @@ +-2 +diff -uNr u-boot-1.1.2/.pc/applied-patches u-boot-emetec-1.1.2/.pc/applied-patches +--- u-boot-1.1.2/.pc/applied-patches 2007-04-20 00:01:06.000000000 +0300 ++++ u-boot-emetec-1.1.2/.pc/applied-patches 1970-01-01 02:00:00.000000000 +0200 +@@ -1 +0,0 @@ +-arm_flags.patch +diff -uNr u-boot-1.1.2/.pc/arm_flags.patch/cpu/pxa/config.mk u-boot-emetec-1.1.2/.pc/arm_flags.patch/cpu/pxa/config.mk +--- u-boot-1.1.2/.pc/arm_flags.patch/cpu/pxa/config.mk 2003-05-23 15:36:21.000000000 +0300 ++++ u-boot-emetec-1.1.2/.pc/arm_flags.patch/cpu/pxa/config.mk 1970-01-01 02:00:00.000000000 +0200 +@@ -1,28 +0,0 @@ +-# +-# (C) Copyright 2002 +-# Sysgo Real-Time Solutions, GmbH +-# Marius Groeger +-# +-# See file CREDITS for list of people who contributed to this +-# project. +-# +-# This program is free software; you can redistribute it and/or +-# modify it under the terms of the GNU General Public License as +-# published by the Free Software Foundation; either version 2 of +-# the License, or (at your option) any later version. +-# +-# This program is distributed in the hope that it will be useful, +-# but WITHOUT ANY WARRANTY; without even the implied warranty of +-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-# GNU General Public License for more details. +-# +-# You should have received a copy of the GNU General Public License +-# along with this program; if not, write to the Free Software +-# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +-# MA 02111-1307 USA +-# +- +-PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ +- -mshort-load-bytes -msoft-float +- +-PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100 +diff -uNr u-boot-1.1.2/MAKEALL u-boot-emetec-1.1.2/MAKEALL +--- u-boot-1.1.2/MAKEALL 2004-12-31 11:32:48.000000000 +0200 ++++ u-boot-emetec-1.1.2/MAKEALL 2005-03-11 22:23:47.000000000 +0200 +@@ -69,7 +69,7 @@ + ml300 OCOTEA OCRTC ORSG \ + PCI405 PIP405 PLU405 PMC405 \ + PPChameleonEVB VOH405 W7OLMC W7OLMG \ +- WALNUT405 WUH405 XPEDITE1K \ ++ WALNUT405 WUH405 XPEDITE1K EMETEC405 \ + " + + ######################################################################### +diff -uNr u-boot-1.1.2/Makefile u-boot-emetec-1.1.2/Makefile +--- u-boot-1.1.2/Makefile 2004-12-19 11:58:11.000000000 +0200 ++++ u-boot-emetec-1.1.2/Makefile 2005-03-14 22:43:56.000000000 +0200 +@@ -54,7 +54,7 @@ + CROSS_COMPILE = + else + ifeq ($(ARCH),ppc) +-CROSS_COMPILE = ppc_8xx- ++CROSS_COMPILE = ppc_4xx- + endif + ifeq ($(ARCH),arm) + CROSS_COMPILE = arm-linux- +@@ -127,7 +127,6 @@ + # The "tools" are needed early, so put this first + # Don't include stuff already done in $(LIBS) + SUBDIRS = tools \ +- examples \ + post \ + post/cpu + .PHONY : $(SUBDIRS) +@@ -838,6 +837,9 @@ + + VOM405_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx vom405 esd ++ ++EMETEC405_config: unconfig ++ @./mkconfig $(@:_config=) ppc ppc4xx emetec405 + + W7OLMC_config \ + W7OLMG_config: unconfig +diff -uNr u-boot-1.1.2/board/emetec405/Makefile u-boot-emetec-1.1.2/board/emetec405/Makefile +--- u-boot-1.1.2/board/emetec405/Makefile 1970-01-01 02:00:00.000000000 +0200 ++++ u-boot-emetec-1.1.2/board/emetec405/Makefile 2005-04-26 22:34:53.000000000 +0300 +@@ -0,0 +1,46 @@ ++# ++# (C) Copyright 2000 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = lib$(BOARD).a ++ ++OBJS = $(BOARD).o flash.o ++ ++$(LIB): $(OBJS) $(SOBJS) ++ $(AR) crv $@ $(OBJS) ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak .depend ++ ++######################################################################### ++ ++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) ++ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ ++ ++sinclude .depend ++ ++######################################################################### +diff -uNr u-boot-1.1.2/board/emetec405/config.mk u-boot-emetec-1.1.2/board/emetec405/config.mk +--- u-boot-1.1.2/board/emetec405/config.mk 1970-01-01 02:00:00.000000000 +0200 ++++ u-boot-emetec-1.1.2/board/emetec405/config.mk 2005-03-11 22:26:43.000000000 +0200 +@@ -0,0 +1,28 @@ ++# ++# (C) Copyright 2000 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++# ++# emetec EMETEC405 boards ++# ++ ++TEXT_BASE = 0xFFFC0000 +diff -uNr u-boot-1.1.2/board/emetec405/emetec405.c u-boot-emetec-1.1.2/board/emetec405/emetec405.c +--- u-boot-1.1.2/board/emetec405/emetec405.c 1970-01-01 02:00:00.000000000 +0200 ++++ u-boot-emetec-1.1.2/board/emetec405/emetec405.c 2005-04-26 23:02:01.000000000 +0300 +@@ -0,0 +1,106 @@ ++/* ++ * (C) Copyright 2001-2003 ++ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++ ++ ++int board_early_init_f (void) ++{ ++ /*-------------------------------------------------------------------------+ ++ | Interrupt controller setup for the Walnut board. ++ | Note: IRQ 0-15 405GP internally generated; active high; level sensitive ++ | IRQ 16 405GP internally generated; active low; level sensitive ++ | IRQ 17-24 RESERVED ++ | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive ++ | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive ++ | IRQ 27 (EXT IRQ 2) Not Used ++ | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive ++ | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive ++ | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive ++ | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive ++ | Note for Walnut board: ++ | An interrupt taken for the FPGA (IRQ 25) indicates that either ++ | the Mouse, Keyboard, IRDA, or External Expansion caused the ++ | interrupt. The FPGA must be read to determine which device ++ | caused the interrupt. The default setting of the FPGA clears ++ | ++ +-------------------------------------------------------------------------*/ ++ ++ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ ++ mtdcr (uicer, 0x00000000); /* disable all ints */ ++ mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ ++ mtdcr (uicpr, 0xFFFFFFE0); /* set int polarities */ ++ mtdcr (uictr, 0x10000000); /* set int trigger levels */ ++ mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ ++ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ ++ ++ return 0; ++} ++ ++ ++int misc_init_f (void) ++{ ++ return 0; /* dummy implementation */ ++} ++ ++ ++int misc_init_r (void) ++{ ++ return 0; /* dummy implementation */ ++} ++ ++ ++/* ++ * Check Board Identity: ++ */ ++int checkboard (void) ++{ ++ unsigned char str[64]; ++ ++ puts ("Board: MAGICBOX\n"); ++ ++ return 0; ++} ++ ++ ++long int initdram (int board_type) ++{ ++ unsigned long val; ++ ++ mtdcr(memcfga, mem_mb0cf); ++ val = mfdcr(memcfgd); ++ ++ return (4*1024*1024 << ((val & 0x000e0000) >> 17)); ++} ++ ++ ++int testdram (void) ++{ ++ printf ("test: 32 MB - ok\n"); ++ ++ return (0); ++} ++ +diff -uNr u-boot-1.1.2/board/emetec405/flash.c u-boot-emetec-1.1.2/board/emetec405/flash.c +--- u-boot-1.1.2/board/emetec405/flash.c 1970-01-01 02:00:00.000000000 +0200 ++++ u-boot-emetec-1.1.2/board/emetec405/flash.c 2005-05-25 10:14:13.000000000 +0300 +@@ -0,0 +1,544 @@ ++/* ++ * (C) Copyright 2000 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++#include ++#include ++#include ++ ++flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ ++ ++/*----------------------------------------------------------------------- ++ * Functions ++ */ ++static ulong flash_get_size (vu_long * addr, flash_info_t * info); ++static void flash_get_offsets (ulong base, flash_info_t * info); ++ ++/*----------------------------------------------------------------------- ++ */ ++unsigned long flash_init (void) ++{ ++ unsigned long size_b0; ++ int i; ++ uint pbcr; ++ unsigned long base_b0; ++ int size_val = 0; ++ ++ /* Init: no FLASHes known */ ++ for (i=0; isize; ++ i = info->sector_count; ++ ++ switch (info->flash_id & FLASH_TYPEMASK) ++ { ++ case FLASH_STMW320DT : ++ /* 1 x 16k boot sector */ ++ base -= 16 << 10; ++ --i; ++ info->start[i] = base; ++ /* 2 x 8k boot sectors */ ++ for (n=0; n<2; ++n) { ++ base -= 8 << 10; ++ --i; ++ info->start[i] = base; ++ } ++ /* 1 x 32k boot sector */ ++ base -= 32 << 10; ++ --i; ++ info->start[i] = base; ++ break; ++ ++ case FLASH_STMW640DT : ++ /* 8 x 8k boot sectors */ ++ for (n=0; n<8; ++n) { ++ base -= 8 << 10; ++ --i; ++ info->start[i] = base; ++ } ++ break; ++ }; ++ /* 64k regular sectors */ ++ while (i > 0) { ++ base -= 64 << 10; ++ --i; ++ info->start[i] = base; ++ } ++} ++ ++/*----------------------------------------------------------------------- ++ */ ++static ulong flash_get_size (vu_long *addr, flash_info_t *info) ++{ ++ short i; ++ short n; ++ CFG_FLASH_WORD_SIZE value; ++ ulong base = (ulong)addr; ++ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr; ++ ++ /* Write auto select command: read Manufacturer ID */ ++ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; ++ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; ++ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090; ++ ++ value = addr2[CFG_FLASH_READ0]; ++ ++ switch (value) { ++ case (CFG_FLASH_WORD_SIZE)SST_MANUFACT: ++ info->flash_id = FLASH_MAN_SST; ++ break; ++ case (CFG_FLASH_WORD_SIZE)STM_MANUFACT: ++ info->flash_id = FLASH_MAN_STM; ++ break; ++ default: ++ info->flash_id = FLASH_UNKNOWN; ++ info->sector_count = 0; ++ info->size = 0; ++ return (0); ++ } ++ ++ value = addr2[CFG_FLASH_READ1]; /* device ID */ ++ ++ switch (value) { ++ case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT: ++ info->flash_id += FLASH_STMW320DT; ++ info->sector_count = 67; ++ info->size = 0x00400000; ++ ++ /* set up sector start address table for FLASH_STMW320DT */ ++ /* set sector offsets for top boot block type */ ++ base += info->size; ++ i = info->sector_count; ++ /* 1 x 16k boot sector */ ++ base -= 16 << 10; ++ --i; ++ info->start[i] = base; ++ /* 2 x 8k boot sectors */ ++ for (n=0; n<2; ++n) { ++ base -= 8 << 10; ++ --i; ++ info->start[i] = base; ++ }; ++ /* 1 x 32k boot sector */ ++ base -= 32 << 10; ++ --i; ++ info->start[i] = base; ++ ++ /* 64k regular sectors */ ++ while (i > 0) ++ { ++ base -= 64 << 10; ++ --i; ++ info->start[i] = base; ++ }; ++ break; /* => 4 MB */ ++ ++ case (CFG_FLASH_WORD_SIZE)STM_ID_29W640DT: ++ info->flash_id += FLASH_STMW640DT; ++ info->sector_count = 135; ++ info->size = 0x00800000; ++ ++ /* set up sector start address table for FLASH_STMW640DT */ ++ /* set sector offsets for top boot block type */ ++ base += info->size; ++ i = info->sector_count; ++ /* 8 x 8k boot sectors */ ++ for (n=0; n<8; ++n) { ++ base -= 8 << 10; ++ --i; ++ info->start[i] = base; ++ }; ++ ++ /* 64k regular sectors */ ++ while (i > 0) ++ { ++ base -= 64 << 10; ++ --i; ++ info->start[i] = base; ++ }; ++ ++ break; /* => 8 MB */ ++ default: ++ info->flash_id = FLASH_UNKNOWN; ++ return (0); /* => no or unknown flash */ ++ } ++ ++ /* check for protected sectors */ ++ for (i = 0; i < info->sector_count; i++) { ++ /* read sector protection at sector address, (A7 .. A0) = 0x02 */ ++ /* D0 = 1 if protected */ ++ addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); ++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ++ info->protect[i] = 0; ++ else ++ info->protect[i] = addr2[CFG_FLASH_READ2] & 1; ++ } ++ ++ /* ++ * Prevent writes to uninitialized FLASH. ++ */ ++ if (info->flash_id != FLASH_UNKNOWN) { ++ addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0]; ++ *addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ ++ } ++ ++ return (info->size); ++} ++ ++/*----------------------------------------------------------------------- ++ */ ++void flash_print_info (flash_info_t *info) ++{ ++ int i; ++ int k; ++ int size; ++ int erased; ++ volatile unsigned long *flash; ++ ++ switch (info->flash_id & FLASH_TYPEMASK) ++ { ++ case FLASH_STMW320DT : ++ printf ("ST M29W320DT (32 M, top sector)\n"); ++ break; ++ case FLASH_STMW640DT : ++ printf ("ST M29W640DT (64 M, top sector)\n"); ++ break; ++ default : ++ printf ("Missing or unknown FLASH type\n"); ++ return; ++ }; ++ printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); ++ ++ printf (" Sector Start Addresses:"); ++ for (i=0; isector_count; ++i) { ++ /* ++ * Check if whole sector is erased ++ */ ++ if (i != (info->sector_count-1)) ++ size = info->start[i+1] - info->start[i]; ++ else ++ size = info->start[0] + info->size - info->start[i]; ++ erased = 1; ++ flash = (volatile unsigned long *)info->start[i]; ++ size = size >> 2; /* divide by 4 for longword access */ ++ for (k=0; kstart[i], ++ erased ? " E" : " ", ++ info->protect[i] ? "RO " : " " ++ ); ++ } ++ printf ("\n"); ++ return; ++} ++ ++/*----------------------------------------------------------------------- ++ */ ++ ++int flash_erase (flash_info_t *info, int s_first, int s_last) ++{ ++ volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]); ++ volatile CFG_FLASH_WORD_SIZE *addr2; ++ int flag, prot, sect, l_sect; ++ ulong start, now, last; ++ int i; ++ ++ if ((s_first < 0) || (s_first > s_last)) { ++ if (info->flash_id == FLASH_UNKNOWN) { ++ printf ("- missing\n"); ++ } else { ++ printf ("- no sectors to erase\n"); ++ } ++ return 1; ++ } ++ ++ if (info->flash_id == FLASH_UNKNOWN) { ++ printf ("Can't erase unknown flash type - aborted\n"); ++ return 1; ++ } ++ ++ prot = 0; ++ for (sect=s_first; sect<=s_last; ++sect) { ++ if (info->protect[sect]) { ++ prot++; ++ } ++ } ++ ++ if (prot) { ++ printf ("- Warning: %d protected sectors will not be erased!\n", ++ prot); ++ } else { ++ printf ("\n"); ++ } ++ ++ l_sect = -1; ++ ++ /* Disable interrupts which might cause a timeout here */ ++ flag = disable_interrupts(); ++ ++ /* Start erase on unprotected sectors */ ++ for (sect = s_first; sect<=s_last; sect++) { ++ if (info->protect[sect] == 0) { /* not protected */ ++ addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]); ++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { ++ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; ++ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; ++ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; ++ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; ++ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; ++ addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050; /* block erase */ ++ for (i=0; i<50; i++) ++ udelay(1000); /* wait 1 ms */ ++ } else { ++ if (sect == s_first) { ++ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; ++ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; ++ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; ++ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; ++ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; ++ } ++ addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */ ++ } ++ l_sect = sect; ++ } ++ } ++ ++ /* re-enable interrupts if necessary */ ++ if (flag) ++ enable_interrupts(); ++ ++ /* wait at least 80us - let's wait 1 ms */ ++ udelay (1000); ++ ++ /* ++ * We wait for the last triggered sector ++ */ ++ if (l_sect < 0) ++ goto DONE; ++ ++ start = get_timer (0); ++ last = start; ++ addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]); ++ while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) { ++ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { ++ printf ("Timeout\n"); ++ return 1; ++ } ++ /* show that we're waiting */ ++ if ((now - last) > 1000) { /* every second */ ++ putc ('.'); ++ last = now; ++ } ++ } ++ ++DONE: ++ /* reset to read mode */ ++ addr = (CFG_FLASH_WORD_SIZE *)info->start[0]; ++ addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ ++ ++ printf (" done\n"); ++ return 0; ++} ++ ++/*----------------------------------------------------------------------- ++ * Copy memory to flash, returns: ++ * 0 - OK ++ * 1 - write timeout ++ * 2 - Flash not erased ++ */ ++ ++int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) ++{ ++ ulong cp, wp, data; ++ int i, l, rc; ++ ++ wp = (addr & ~3); /* get lower word aligned address */ ++ ++ /* ++ * handle unaligned start bytes ++ */ ++ if ((l = addr - wp) != 0) { ++ data = 0; ++ for (i=0, cp=wp; i0; ++i) { ++ data = (data << 8) | *src++; ++ --cnt; ++ ++cp; ++ } ++ for (; cnt==0 && i<4; ++i, ++cp) { ++ data = (data << 8) | (*(uchar *)cp); ++ } ++ ++ if ((rc = write_word(info, wp, data)) != 0) { ++ return (rc); ++ } ++ wp += 4; ++ } ++ ++ /* ++ * handle word aligned part ++ */ ++ while (cnt >= 4) { ++ data = 0; ++ for (i=0; i<4; ++i) { ++ data = (data << 8) | *src++; ++ } ++ if ((rc = write_word(info, wp, data)) != 0) { ++ return (rc); ++ } ++ wp += 4; ++ cnt -= 4; ++ } ++ ++ if (cnt == 0) { ++ return (0); ++ } ++ ++ /* ++ * handle unaligned tail bytes ++ */ ++ data = 0; ++ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { ++ data = (data << 8) | *src++; ++ --cnt; ++ } ++ for (; i<4; ++i, ++cp) { ++ data = (data << 8) | (*(uchar *)cp); ++ } ++ ++ return (write_word(info, wp, data)); ++} ++ ++/*----------------------------------------------------------------------- ++ * Write a word to Flash, returns: ++ * 0 - OK ++ * 1 - write timeout ++ * 2 - Flash not erased ++ */ ++static int write_word (flash_info_t *info, ulong dest, ulong data) ++{ ++ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]); ++ volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest; ++ volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data; ++ ulong start; ++ int flag; ++ int i; ++ ++ /* Check if Flash is (sufficiently) erased */ ++ if ((*((volatile ulong *)dest) & data) != data) { ++ return (2); ++ } ++ /* Disable interrupts which might cause a timeout here */ ++ flag = disable_interrupts(); ++ ++ for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++) ++ { ++ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; ++ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; ++ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0; ++ ++ dest2[i] = data2[i]; ++ ++ /* re-enable interrupts if necessary */ ++ if (flag) ++ enable_interrupts(); ++ ++ /* data polling for D7 */ ++ start = get_timer (0); ++ while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) != ++ (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) { ++ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { ++ return (1); ++ } ++ } ++ } ++ ++ return (0); ++} +diff -uNr u-boot-1.1.2/board/emetec405/pllmr.c u-boot-emetec-1.1.2/board/emetec405/pllmr.c +--- u-boot-1.1.2/board/emetec405/pllmr.c 1970-01-01 02:00:00.000000000 +0200 ++++ u-boot-emetec-1.1.2/board/emetec405/pllmr.c 2005-03-14 22:32:04.000000000 +0200 +@@ -0,0 +1,19 @@ ++#define PLL_CPUDIV_1 0x00000000 ++#define PLL_PLBDIV_2 0x00010000 ++#define PLL_OPBDIV_2 0x00001000 ++#define PLL_EXTBUSDIV_3 0x00000100 ++#define PLL_MALDIV_1 0x00000000 ++#define PLL_PCIDIV_4 0x00000003 ++ ++#define PLL_FBKDIV_8 0x00800000 ++#define PLL_FWDDIVA_4 0x00040000 ++#define PLL_FWDDIVB_4 0x00004000 ++#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ ++#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ ++ ++#define PLLMR0_200_100_50_25 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ ++ PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ ++ PLL_MALDIV_1 | PLL_PCIDIV_4) ++#define PLLMR1_200_100_50_25 (PLL_FBKDIV_8 | \ ++ PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ ++ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +diff -uNr u-boot-1.1.2/board/emetec405/u-boot.lds u-boot-emetec-1.1.2/board/emetec405/u-boot.lds +--- u-boot-1.1.2/board/emetec405/u-boot.lds 1970-01-01 02:00:00.000000000 +0200 ++++ u-boot-emetec-1.1.2/board/emetec405/u-boot.lds 2003-09-12 11:41:39.000000000 +0300 +@@ -0,0 +1,147 @@ ++/* ++ * (C) Copyright 2000 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_ARCH(powerpc) ++SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); ++/* Do we need any of these for elf? ++ __DYNAMIC = 0; */ ++SECTIONS ++{ ++ .resetvec 0xFFFFFFFC : ++ { ++ *(.resetvec) ++ } = 0xffff ++ ++ /* Read-only sections, merged into text segment: */ ++ . = + SIZEOF_HEADERS; ++ .interp : { *(.interp) } ++ .hash : { *(.hash) } ++ .dynsym : { *(.dynsym) } ++ .dynstr : { *(.dynstr) } ++ .rel.text : { *(.rel.text) } ++ .rela.text : { *(.rela.text) } ++ .rel.data : { *(.rel.data) } ++ .rela.data : { *(.rela.data) } ++ .rel.rodata : { *(.rel.rodata) } ++ .rela.rodata : { *(.rela.rodata) } ++ .rel.got : { *(.rel.got) } ++ .rela.got : { *(.rela.got) } ++ .rel.ctors : { *(.rel.ctors) } ++ .rela.ctors : { *(.rela.ctors) } ++ .rel.dtors : { *(.rel.dtors) } ++ .rela.dtors : { *(.rela.dtors) } ++ .rel.bss : { *(.rel.bss) } ++ .rela.bss : { *(.rela.bss) } ++ .rel.plt : { *(.rel.plt) } ++ .rela.plt : { *(.rela.plt) } ++ .init : { *(.init) } ++ .plt : { *(.plt) } ++ .text : ++ { ++ /* WARNING - the following is hand-optimized to fit within */ ++ /* the sector layout of our flash chips! XXX FIXME XXX */ ++ ++ cpu/ppc4xx/start.o (.text) ++ cpu/ppc4xx/traps.o (.text) ++ cpu/ppc4xx/interrupts.o (.text) ++ cpu/ppc4xx/serial.o (.text) ++ cpu/ppc4xx/cpu_init.o (.text) ++ cpu/ppc4xx/speed.o (.text) ++ cpu/ppc4xx/405gp_enet.o (.text) ++ common/dlmalloc.o (.text) ++ lib_generic/crc32.o (.text) ++ lib_ppc/extable.o (.text) ++ lib_generic/zlib.o (.text) ++ ++/* . = env_offset;*/ ++/* common/environment.o(.text)*/ ++ ++ *(.text) ++ *(.fixup) ++ *(.got1) ++ } ++ _etext = .; ++ PROVIDE (etext = .); ++ .rodata : ++ { ++ *(.rodata) ++ *(.rodata1) ++ *(.rodata.str1.4) ++ } ++ .fini : { *(.fini) } =0 ++ .ctors : { *(.ctors) } ++ .dtors : { *(.dtors) } ++ ++ /* Read-write section, merged into data segment: */ ++ . = (. + 0x00FF) & 0xFFFFFF00; ++ _erotext = .; ++ PROVIDE (erotext = .); ++ .reloc : ++ { ++ *(.got) ++ _GOT2_TABLE_ = .; ++ *(.got2) ++ _FIXUP_TABLE_ = .; ++ *(.fixup) ++ } ++ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; ++ __fixup_entries = (. - _FIXUP_TABLE_)>>2; ++ ++ .data : ++ { ++ *(.data) ++ *(.data1) ++ *(.sdata) ++ *(.sdata2) ++ *(.dynamic) ++ CONSTRUCTORS ++ } ++ _edata = .; ++ PROVIDE (edata = .); ++ ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ __start___ex_table = .; ++ __ex_table : { *(__ex_table) } ++ __stop___ex_table = .; ++ ++ . = ALIGN(256); ++ __init_begin = .; ++ .text.init : { *(.text.init) } ++ .data.init : { *(.data.init) } ++ . = ALIGN(256); ++ __init_end = .; ++ ++ __bss_start = .; ++ .bss : ++ { ++ *(.sbss) *(.scommon) ++ *(.dynbss) ++ *(.bss) ++ *(COMMON) ++ } ++ _end = . ; ++ PROVIDE (end = .); ++} +diff -uNr u-boot-1.1.2/copy.sh u-boot-emetec-1.1.2/copy.sh +--- u-boot-1.1.2/copy.sh 1970-01-01 02:00:00.000000000 +0200 ++++ u-boot-emetec-1.1.2/copy.sh 2005-03-17 23:26:42.000000000 +0200 +@@ -0,0 +1,2 @@ ++cp u-boot.bin /home/admin/uboot/uboot_v6.bin ++cp u-boot.srec /home/admin/uboot/uboot_v6.srec +diff -uNr u-boot-1.1.2/cpu/ppc4xx/405gp_enet.c u-boot-emetec-1.1.2/cpu/ppc4xx/405gp_enet.c +--- u-boot-1.1.2/cpu/ppc4xx/405gp_enet.c 2004-07-02 17:36:35.000000000 +0300 ++++ u-boot-emetec-1.1.2/cpu/ppc4xx/405gp_enet.c 2005-05-06 18:07:02.000000000 +0300 +@@ -133,7 +133,7 @@ + /*-----------------------------------------------------------------------------+ + * Prototypes and externals. + *-----------------------------------------------------------------------------*/ +-static void enet_rcv (struct eth_device *dev, unsigned long malisr); ++static void enet_rcv (struct eth_device *dev, unsigned long malisr); + + int enetInt (struct eth_device *dev); + static void mal_err (struct eth_device *dev, unsigned long isr, +@@ -190,11 +190,15 @@ + unsigned short reg_short; + + EMAC_405_HW_PST hw_p = dev->priv; ++ ++ puts ("Test 1\n"); + /* before doing anything, figure out if we have a MAC address */ + /* if not, bail */ + if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) + return -1; + ++ puts ("Test 2\n"); ++ + msr = mfmsr (); + mtmsr (msr & ~(MSR_EE)); /* disable interrupts */ + +@@ -1023,6 +1027,8 @@ + #else + emac0_dev = dev; + #endif ++ // print device name ++ printf("%s\n", dev->name); + + } /* end for each supported device */ + +diff -uNr u-boot-1.1.2/cpu/pxa/config.mk u-boot-emetec-1.1.2/cpu/pxa/config.mk +--- u-boot-1.1.2/cpu/pxa/config.mk 2007-04-20 00:01:06.000000000 +0300 ++++ u-boot-emetec-1.1.2/cpu/pxa/config.mk 2003-05-23 15:36:21.000000000 +0300 +@@ -23,6 +23,6 @@ + # + + PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ +- -msoft-float ++ -mshort-load-bytes -msoft-float + + PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100 +diff -uNr u-boot-1.1.2/include/configs/EMETEC405.h u-boot-emetec-1.1.2/include/configs/EMETEC405.h +--- u-boot-1.1.2/include/configs/EMETEC405.h 1970-01-01 02:00:00.000000000 +0200 ++++ u-boot-emetec-1.1.2/include/configs/EMETEC405.h 2005-05-25 10:08:39.000000000 +0300 +@@ -0,0 +1,349 @@ ++/* ++ * (C) Copyright 2001-2003 ++ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* ++ * board/config.h - configuration options, board specific ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define FLASH_8MB 1 ++/* ++ * High Level Configuration Options ++ * (easy to change) ++ */ ++ ++#define CONFIG_405EP 1 /* This is a PPC405 CPU */ ++#define CONFIG_4xx 1 /* ...member of PPC4xx family */ ++#define CONFIG_EMETEC405 1 /* ...on a EMETEC405 board */ ++ ++#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ ++#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ ++ ++#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ ++ ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ ++ ++#undef CONFIG_BOOTARGS ++#undef CONFIG_BOOTCOMMAND ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "ramargs=setenv bootargs console=ttyS0,115200 " \ ++ "root=/dev/ram rw\0" \ ++ "flash_mem=run ramargs;" \ ++ "bootm $(kernel_addr) $(ramdisk_addr)\0" \ ++ "kernel_addr=ffC00000\0" \ ++ "ramdisk_addr=ffCE0000\0" \ ++ "" ++#define CONFIG_BOOTCOMMAND "run flash_mem" ++ ++#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ ++ ++#define CONFIG_MII 1 /* MII PHY management */ ++#define CONFIG_PHY_ADDR 0 /* PHY address */ ++ ++#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ ++ CFG_CMD_NET | \ ++ CFG_CMD_DHCP | \ ++ CFG_CMD_IRQ | \ ++ CFG_CMD_ELF | \ ++ CFG_CMD_I2C | \ ++ CFG_CMD_PING | \ ++ CFG_CMD_EEPROM ) ++ ++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ ++#include ++ ++#undef CONFIG_WATCHDOG /* watchdog disabled */ ++ ++#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ ++ ++/* ++ * Miscellaneous configurable options ++ */ ++#define CFG_LONGHELP /* undef to save memory */ ++#define CFG_PROMPT "=> " /* Monitor Command Prompt */ ++ ++#undef CFG_HUSH_PARSER /* use "hush" command parser */ ++#ifdef CFG_HUSH_PARSER ++#define CFG_PROMPT_HUSH_PS2 "> " ++#endif ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ ++#else ++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ ++#endif ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ ++#define CFG_MAXARGS 16 /* max number of command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ ++ ++#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ ++ ++#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ ++ ++#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ ++#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ ++ ++#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ ++#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ ++#define CFG_BASE_BAUD 691200 ++ ++/* The following table includes the supported baudrates */ ++#define CFG_BAUDRATE_TABLE \ ++ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ ++ 57600, 115200, 230400, 460800, 921600 } ++ ++#define CFG_LOAD_ADDR 0x100000 /* default load address */ ++#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ ++ ++#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ ++ ++#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ ++ ++#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ ++ ++#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ ++ ++/* Ethernet stuff */ ++#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */ ++#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE ++ ++#define CONFIG_IPADDR 192.168.0.50 ++#define CONFIG_NETMASK 255.255.255.0 ++#define CONFIG_SERVERIP 192.168.0.1 ++ ++/*----------------------------------------------------------------------- ++ * PCI stuff ++ *----------------------------------------------------------------------- ++ */ ++#define PCI_HOST_ADAPTER 0 // configure as pci adapter ++#define PCI_HOST_FORCE 1 // configure as pci host ++#define PCI_HOST_AUTO 2 // detected via arbiter enable ++ ++#define CONFIG_PCI // include pci support ++#define CONFIG_PCI_HOST PCI_HOST_FORCE // select pci host function ++#define CONFIG_PCI_PNP // do pci plug-and-play ++ ++ ++#define CFG_PCI_SUBSYS_VENDORID 0x0000 // PCI Vendor ID: IBM ++#define CFG_PCI_SUBSYS_DEVICEID 0x0000 // PCI Device ID: 405GP ++#define CFG_PCI_PTM1LA 0x00000000 // point to sdram ++#define CFG_PCI_PTM1MS 0x80000001 // 2GB, enable hard-wired to 1 ++#define CFG_PCI_PTM1PCI 0x00000000 // Host: use this pci address ++#define CFG_PCI_PTM2LA 0x00000000 // disabled ++#define CFG_PCI_PTM2MS 0x00000000 // disabled ++#define CFG_PCI_PTM2PCI 0x00000000 // Host: use this pci address ++ ++/*----------------------------------------------------------------------- ++ * Start addresses for the final memory configuration ++ * (Set up by the startup code) ++ * Please note that CFG_SDRAM_BASE _must_ start at 0 ++ */ ++ ++/* ++ * Flash configuration (8,16 or 32 MB) ++ * TEXT base always at 0xFFF00000 ++ * ENV_ADDR always at 0xFFF40000 ++ * FLASH_BASE at 0xFE000000 for 32 MB ++ * 0xFF000000 for 16 MB ++ * 0xFF800000 for 8 MB ++ * 0xFFC00000 for 4 MB ++ */ ++ ++#define CFG_SDRAM_BASE 0x00000000 ++#define CFG_FLASH_BASE 0xFFFC0000 ++#define CFG_MONITOR_BASE CFG_FLASH_BASE ++#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ ++#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ ++ ++/* ++ * For booting Linux, the board info and command line data ++ * have to be in the first 8 MB of memory, since this is ++ * the maximum mapped by the Linux kernel during initialization. ++ */ ++#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ ++/*----------------------------------------------------------------------- ++ * FLASH organization ++ */ ++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ ++#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ ++ ++#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ ++#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ ++ ++#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ ++#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ ++#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ ++/* ++ * The following defines are added for buggy IOP480 byte interface. ++ * All other boards should use the standard values (CPCI405 etc.) ++ */ ++#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ ++#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ ++#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ ++ ++#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ ++ ++/* ++#define CFG_ENV_IS_IN_FLASH 1 ++//Address and size of Primary Environment Sector ++#define CFG_ENV_ADDR 0xFFFFA000 ++#define CFG_ENV_SIZE 0x2000 ++*/ ++ ++/*----------------------------------------------------------------------- ++ * Environment Variable setup ++ */ ++#define CFG_ENV_IS_IN_EEPROM 1 // use EEPROM for environment vars ++#define CFG_ENV_OFFSET 0x100 // environment starts at the beginning of the EEPROM ++#define CFG_ENV_SIZE 0x700 // 2048 bytes may be used for env vars ++ ++/*----------------------------------------------------------------------- ++ * I2C EEPROM (CAT24WC16) for environment ++ */ ++#define CONFIG_HARD_I2C // I2c with hardware support ++#define CFG_I2C_SPEED 400000 // I2C speed and slave address ++#define CFG_I2C_SLAVE 0x7F ++ ++#define CFG_I2C_EEPROM_ADDR 0x50 // EEPROM CAT28WC08 ++#define CFG_I2C_EEPROM_ADDR_LEN 1 // Bytes of address ++ ++#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 ++#define CFG_EEPROM_PAGE_WRITE_BITS 4 // The Catalyst CAT24WC08 has ++ // 16 byte page write mode using ++ // last 4 bits of the address ++#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 // and takes up to 10 msec ++#define CFG_EEPROM_PAGE_WRITE_ENABLE ++ ++/*----------------------------------------------------------------------- ++ * Cache Configuration ++ */ ++#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ ++ /* have only 8kB, 16kB is save here */ ++#define CFG_CACHELINE_SIZE 32 /* ... */ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ ++#endif ++ ++/* ++ * Init Memory Controller: ++ * ++ * BR0/1 and OR0/1 (FLASH) ++ */ ++ ++#if FLASH_8MB == 1 ++#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ ++#else ++#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ ++#endif ++ ++/*----------------------------------------------------------------------- ++ * External Bus Controller (EBC) Setup ++ */ ++ ++/* Memory Bank 0 (Flash Bank 0) initialization */ ++#if FLASH_8MB == 1 ++#define CFG_EBC_PB0AP 0x92015480 ++#define CFG_EBC_PB0CR 0xFFC5B000 /* BAS=0xFFC,BS=8MB,BU=R/W,BW=16bit */ ++#else ++#define CFG_EBC_PB0AP 0x92015480 ++#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ ++#endif ++ ++/*----------------------------------------------------------------------- ++ * Definitions for initial stack pointer and data area (in data cache) ++ */ ++/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ ++#define CFG_TEMP_STACK_OCM 1 ++ ++/* On Chip Memory location */ ++#define CFG_OCM_DATA_ADDR 0xF8000000 ++#define CFG_OCM_DATA_SIZE 0x1000 ++#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ ++#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ ++ ++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ ++#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) ++#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET ++ ++/*----------------------------------------------------------------------- ++ * Definitions for GPIO setup (PPC405EP specific) ++ * ++ * GPIO0[0] - External Bus Controller BLAST output ++ * GPIO0[1-9] - Instruction trace outputs -> GPIO ++ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs ++ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO ++ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs ++ * GPIO0[24-27] - UART0 control signal inputs/outputs ++ * GPIO0[28-29] - UART1 data signal input/output ++ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs ++ */ ++#define CFG_GPIO0_OSRH 0x40000550 ++#define CFG_GPIO0_OSRL 0x00000110 ++#define CFG_GPIO0_ISR1H 0x00000000 ++#define CFG_GPIO0_ISR1L 0x15555445 ++#define CFG_GPIO0_TSRH 0x00000000 ++#define CFG_GPIO0_TSRL 0x00000000 ++#define CFG_GPIO0_TCR 0xF7FE0014 ++ ++/* ++ * Internal Definitions ++ * ++ * Boot Flags ++ */ ++#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ ++#define BOOTFLAG_WARM 0x02 /* Software reboot */ ++ ++#define PLL_CPUDIV_1 0x00000000 ++#define PLL_PLBDIV_2 0x00010000 ++#define PLL_OPBDIV_2 0x00001000 ++ ++#define PLL_EXTBUSDIV_4 0x00000200 ++ ++#define PLL_MALDIV_1 0x00000000 ++#define PLL_PCIDIV_2 0x00000001 ++#define PLL_PCIDIV_4 0x00000003 ++ ++#define PLL_FBKDIV_8 0x00800000 ++ ++#define PLL_FWDDIVA_4 0x00040000 ++#define PLL_FWDDIVB_4 0x00004000 ++#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ ++#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ ++ ++#define PLLMR0_200_100_50_25 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ ++ PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ ++ PLL_MALDIV_1 | PLL_PCIDIV_4) ++#define PLLMR1_200_100_50_25 (PLL_FBKDIV_8 | \ ++ PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ ++ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) ++/* ++ * Default speed selection (cpu_plb_opb_ebc) in mhz. ++ * This value will be set if iic boot eprom is disabled. ++ */ ++#define PLLMR0_DEFAULT PLLMR0_200_100_50_25 ++#define PLLMR1_DEFAULT PLLMR1_200_100_50_25 ++ ++#endif /* __CONFIG_H */ +diff -uNr u-boot-1.1.2/include/configs/EMETEC405.h.old u-boot-emetec-1.1.2/include/configs/EMETEC405.h.old +--- u-boot-1.1.2/include/configs/EMETEC405.h.old 1970-01-01 02:00:00.000000000 +0200 ++++ u-boot-emetec-1.1.2/include/configs/EMETEC405.h.old 2005-03-17 23:00:33.000000000 +0200 +@@ -0,0 +1,349 @@ ++/* ++ * (C) Copyright 2001-2003 ++ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* ++ * board/config.h - configuration options, board specific ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++/* ++ * High Level Configuration Options ++ * (easy to change) ++ */ ++ ++#define CONFIG_405EP 1 /* This is a PPC405 CPU */ ++#define CONFIG_4xx 1 /* ...member of PPC4xx family */ ++#define CONFIG_EMETEC405 1 /* ...on a EMETEC405 board */ ++ ++#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ ++#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ ++ ++#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ ++ ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ ++ ++#undef CONFIG_BOOTARGS ++#undef CONFIG_BOOTCOMMAND ++ ++#define CONFIG_PREBOOT /* enable preboot variable */ ++ ++#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ ++ ++#define CONFIG_MII 1 /* MII PHY management */ ++#define CONFIG_PHY_ADDR 0 /* PHY address */ ++#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ ++ ++/* ++#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ // 66 MHz OPB clock ++*/ ++ ++#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ ++ CFG_CMD_DHCP | \ ++ CFG_CMD_IRQ | \ ++ CFG_CMD_ELF | \ ++ CFG_CMD_I2C | \ ++ CFG_CMD_MII | \ ++ CFG_CMD_PING | \ ++ CFG_CMD_EEPROM ) ++ ++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ ++#include ++ ++#undef CONFIG_WATCHDOG /* watchdog disabled */ ++ ++#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ ++ ++/* ++ * Miscellaneous configurable options ++ */ ++#define CFG_LONGHELP /* undef to save memory */ ++#define CFG_PROMPT "=> " /* Monitor Command Prompt */ ++ ++#undef CFG_HUSH_PARSER /* use "hush" command parser */ ++#ifdef CFG_HUSH_PARSER ++#define CFG_PROMPT_HUSH_PS2 "> " ++#endif ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ ++#else ++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ ++#endif ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ ++#define CFG_MAXARGS 16 /* max number of command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ ++ ++#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ ++ ++#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ ++ ++#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ ++#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ ++ ++#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ ++#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ ++#define CFG_BASE_BAUD 691200 ++#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ ++ ++/* The following table includes the supported baudrates */ ++#define CFG_BAUDRATE_TABLE \ ++ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ ++ 57600, 115200, 230400, 460800, 921600 } ++ ++#define CFG_LOAD_ADDR 0x100000 /* default load address */ ++#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ ++ ++#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ ++ ++#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ ++ ++#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ ++ ++#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ ++ ++/* Ethernet stuff */ ++#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */ ++#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE ++#define CONFIG_HAS_ETH1 ++#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD ++ ++#define CONFIG_IPADDR 192.168.0.50 ++#define CONFIG_IP1ADDR 192.168.0.51 ++#define CONFIG_NETMASK 255.255.255.0 ++#define CONFIG_SERVERIP 192.168.0.1 ++ ++/*----------------------------------------------------------------------- ++ * PCI stuff ++ *----------------------------------------------------------------------- ++ */ ++#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ ++#define PCI_HOST_FORCE 1 /* configure as pci host */ ++#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ ++ ++#undef CONFIG_PCI /* include pci support */ ++#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ ++#undef CONFIG_PCI_PNP /* do pci plug-and-play */ ++ /* resource configuration */ ++ ++#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ ++ ++#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ ++#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ ++#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ ++#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ ++#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ ++#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ ++#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ ++#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ ++#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ ++ ++/*----------------------------------------------------------------------- ++ * Start addresses for the final memory configuration ++ * (Set up by the startup code) ++ * Please note that CFG_SDRAM_BASE _must_ start at 0 ++ */ ++#define CFG_SDRAM_BASE 0x00000000 ++#define CFG_FLASH_BASE 0xFFFC0000 ++#define CFG_MONITOR_BASE CFG_FLASH_BASE ++#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ ++#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ ++ ++/* ++ * For booting Linux, the board info and command line data ++ * have to be in the first 8 MB of memory, since this is ++ * the maximum mapped by the Linux kernel during initialization. ++ */ ++#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ ++/*----------------------------------------------------------------------- ++ * FLASH organization ++ */ ++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ ++#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ ++ ++#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ ++#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ ++ ++#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ ++#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ ++#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ ++/* ++ * The following defines are added for buggy IOP480 byte interface. ++ * All other boards should use the standard values (CPCI405 etc.) ++ */ ++#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ ++#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ ++#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ ++ ++#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ ++ ++#if 0 /* test-only */ ++#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ ++#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ ++#endif ++ ++/*----------------------------------------------------------------------- ++ * Environment Variable setup ++ */ ++#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ ++#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ ++#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ ++ /* total size of a CAT24WC16 is 2048 bytes */ ++ ++#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ ++#define CFG_NVRAM_SIZE 242 /* NVRAM size */ ++ ++/*----------------------------------------------------------------------- ++ * I2C EEPROM (CAT24WC16) for environment ++ */ ++#define CONFIG_HARD_I2C /* I2c with hardware support */ ++#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ ++#define CFG_I2C_SLAVE 0x7F ++ ++#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ ++#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ ++/* mask of address bits that overflow into the "EEPROM chip address" */ ++#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 ++#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ ++ /* 16 byte page write mode using*/ ++ /* last 4 bits of the address */ ++#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ ++#define CFG_EEPROM_PAGE_WRITE_ENABLE ++ ++/*----------------------------------------------------------------------- ++ * Cache Configuration ++ */ ++#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ ++ /* have only 8kB, 16kB is save here */ ++#define CFG_CACHELINE_SIZE 32 /* ... */ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ ++#endif ++ ++/* ++ * Init Memory Controller: ++ * ++ * BR0/1 and OR0/1 (FLASH) ++ */ ++ ++#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ ++ ++/*----------------------------------------------------------------------- ++ * External Bus Controller (EBC) Setup ++ */ ++ ++/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ ++#define CFG_EBC_PB0AP 0x92015480 ++#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ ++ ++#define DUART0_BA 0xF0000000 /* DUART Base Address */ ++#define DUART1_BA 0xF0000008 /* DUART Base Address */ ++#define DUART2_BA 0xF0000010 /* DUART Base Address */ ++#define DUART3_BA 0xF0000018 /* DUART Base Address */ ++ ++/*----------------------------------------------------------------------- ++ * FPGA stuff ++ */ ++#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ ++#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/ ++ ++/* FPGA program pin configuration */ ++#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ ++#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ ++#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ ++#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ ++#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ ++ ++/*----------------------------------------------------------------------- ++ * Definitions for initial stack pointer and data area (in data cache) ++ */ ++/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ ++#define CFG_TEMP_STACK_OCM 1 ++ ++/* On Chip Memory location */ ++#define CFG_OCM_DATA_ADDR 0xF8000000 ++#define CFG_OCM_DATA_SIZE 0x1000 ++#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ ++#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ ++ ++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ ++#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) ++#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET ++ ++/*----------------------------------------------------------------------- ++ * Definitions for GPIO setup (PPC405EP specific) ++ * ++ * GPIO0[0] - External Bus Controller BLAST output ++ * GPIO0[1-9] - Instruction trace outputs -> GPIO ++ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs ++ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO ++ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs ++ * GPIO0[24-27] - UART0 control signal inputs/outputs ++ * GPIO0[28-29] - UART1 data signal input/output ++ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs ++ */ ++#define CFG_GPIO0_OSRH 0x40000550 ++#define CFG_GPIO0_OSRL 0x00000110 ++#define CFG_GPIO0_ISR1H 0x00000000 ++#define CFG_GPIO0_ISR1L 0x15555445 ++#define CFG_GPIO0_TSRH 0x00000000 ++#define CFG_GPIO0_TSRL 0x00000000 ++#define CFG_GPIO0_TCR 0xF7FE0014 ++ ++/* ++ * Internal Definitions ++ * ++ * Boot Flags ++ */ ++#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ ++#define BOOTFLAG_WARM 0x02 /* Software reboot */ ++ ++#define PLL_CPUDIV_1 0x00000000 ++#define PLL_PLBDIV_2 0x00010000 ++#define PLL_OPBDIV_2 0x00001000 ++#define PLL_EXTBUSDIV_3 0x00000100 ++#define PLL_MALDIV_1 0x00000000 ++#define PLL_PCIDIV_4 0x00000003 ++ ++#define PLL_FBKDIV_8 0x00800000 ++#define PLL_FWDDIVA_4 0x00040000 ++#define PLL_FWDDIVB_4 0x00004000 ++#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ ++#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ ++ ++#define PLLMR0_200_100_50_25 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ ++ PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ ++ PLL_MALDIV_1 | PLL_PCIDIV_4) ++#define PLLMR1_200_100_50_25 (PLL_FBKDIV_8 | \ ++ PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ ++ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) ++/* ++ * Default speed selection (cpu_plb_opb_ebc) in mhz. ++ * This value will be set if iic boot eprom is disabled. ++ */ ++#define PLLMR0_DEFAULT PLLMR0_200_100_50_25 ++#define PLLMR1_DEFAULT PLLMR1_200_100_50_25 ++ ++#endif /* __CONFIG_H */ +diff -uNr u-boot-1.1.2/include/configs/HUB405.h u-boot-emetec-1.1.2/include/configs/HUB405.h +--- u-boot-1.1.2/include/configs/HUB405.h 2004-12-31 11:32:53.000000000 +0200 ++++ u-boot-emetec-1.1.2/include/configs/HUB405.h 2005-03-11 22:19:12.000000000 +0200 +@@ -35,7 +35,7 @@ + + #define CONFIG_405EP 1 /* This is a PPC405 CPU */ + #define CONFIG_4xx 1 /* ...member of PPC4xx family */ +-#define CONFIG_HUB405 1 /* ...on a HUB405 board */ ++#define CONFIG_EMETEC405 1 /* ...on a EMETEC405 board */ + + #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ + #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ +diff -uNr u-boot-1.1.2/include/flash.h u-boot-emetec-1.1.2/include/flash.h +--- u-boot-1.1.2/include/flash.h 2004-12-16 20:01:48.000000000 +0200 ++++ u-boot-emetec-1.1.2/include/flash.h 2005-05-25 10:04:56.000000000 +0300 +@@ -229,7 +229,11 @@ + + #define STM_ID_x800AB 0x005B005B /* M29W800AB ID (8M = 512K x 16 ) */ + #define STM_ID_29W320DT 0x22CA22CA /* M29W320DT ID (32 M, top boot sector) */ +-#define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect) */ ++#define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect)*/ ++ ++#define STM_ID_29W640DT 0x22DE22DE /* M29W640DT ID (64 M, top boot sector) */ ++#define STM_ID_29W640DB 0x22DF22DF /* M29W640DB ID (64 M, bottom boot sect)*/ ++ + #define STM_ID_29W040B 0x00E300E3 /* M29W040B ID (4M = 512K x 8) */ + + #define INTEL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */ +@@ -328,6 +332,8 @@ + #define FLASH_STM800AB 0x0051 /* STM M29WF800AB ( 8M = 512K x 16 ) */ + #define FLASH_STMW320DT 0x0052 /* STM M29W320DT (32 M, top boot sector) */ + #define FLASH_STMW320DB 0x0053 /* STM M29W320DB (32 M, bottom boot sect)*/ ++#define FLASH_STMW640DT 0x0054 /* STM M29W640DT (64 M, top boot sector) */ ++#define FLASH_STMW640DB 0x0055 /* STM M29W640DB (64 M, bottom boot sect)*/ + #define FLASH_STM320DB 0x00CB /* STM M29W320DB (4M = 64K x 64, bottom)*/ + #define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */ + #define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom)*/ +diff -uNr u-boot-1.1.2/include/net.h u-boot-emetec-1.1.2/include/net.h +--- u-boot-1.1.2/include/net.h 2004-10-10 00:56:21.000000000 +0300 ++++ u-boot-emetec-1.1.2/include/net.h 2005-04-27 23:16:40.000000000 +0300 +@@ -331,9 +331,9 @@ + #define NETLOOP_SUCCESS 3 + #define NETLOOP_FAIL 4 + +-#ifdef CONFIG_NET_MULTI ++/* #ifdef CONFIG_NET_MULTI */ + extern int NetRestartWrap; /* Tried all network devices */ +-#endif ++/* #endif */ + + typedef enum { BOOTP, RARP, ARP, TFTP, DHCP, PING, DNS, NFS, CDP, NETCONS } proto_t; + +diff -uNr u-boot-1.1.2/lib_ppc/board.c u-boot-emetec-1.1.2/lib_ppc/board.c +--- u-boot-1.1.2/lib_ppc/board.c 2004-12-31 11:32:54.000000000 +0200 ++++ u-boot-emetec-1.1.2/lib_ppc/board.c 2005-04-27 23:03:33.000000000 +0300 +@@ -970,7 +970,8 @@ + nand_init(); /* go init the NAND */ + #endif + +-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) ++ ++#if (CONFIG_COMMANDS & CFG_CMD_NET) /* && defined(CONFIG_NET_MULTI) */ + WATCHDOG_RESET (); + puts ("Net: "); + eth_initialize (bd); +diff -uNr u-boot-1.1.2/loadftp.sh u-boot-emetec-1.1.2/loadftp.sh +--- u-boot-1.1.2/loadftp.sh 1970-01-01 02:00:00.000000000 +0200 ++++ u-boot-emetec-1.1.2/loadftp.sh 2005-04-25 21:30:54.000000000 +0300 +@@ -0,0 +1 @@ ++cp u-boot.bin /home/ftp/uboot.bin +diff -uNr u-boot-1.1.2/loadwww.sh u-boot-emetec-1.1.2/loadwww.sh +--- u-boot-1.1.2/loadwww.sh 1970-01-01 02:00:00.000000000 +0200 ++++ u-boot-emetec-1.1.2/loadwww.sh 2005-03-12 13:06:19.000000000 +0200 +@@ -0,0 +1,2 @@ ++#!/bin/bash ++rsync -vzr --rsh='ssh -l admin -p 5522' /home/admin/uboot/ admin@mhaber.net:/home/admin/uboot +diff -uNr u-boot-1.1.2/net/eth.c u-boot-emetec-1.1.2/net/eth.c +--- u-boot-1.1.2/net/eth.c 2004-12-16 19:49:38.000000000 +0200 ++++ u-boot-emetec-1.1.2/net/eth.c 2005-05-06 18:04:08.000000000 +0300 +@@ -25,7 +25,7 @@ + #include + #include + +-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) ++#if (CONFIG_COMMANDS & CFG_CMD_NET) /* && defined(CONFIG_NET_MULTI) */ + + #ifdef CFG_GT_6426x + extern int gt6426x_eth_initialize(bd_t *bis); +@@ -126,10 +126,13 @@ + #ifdef CONFIG_DB64460 + mv6446x_eth_initialize(bis); + #endif ++ + #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ + ( defined(CONFIG_440) && !defined(CONFIG_NET_MULTI) ) + ppc_4xx_eth_initialize(bis); ++ eth_number=1; + #endif ++ + #if defined(CONFIG_440) && defined(CONFIG_NET_MULTI) + ppc_440x_eth_initialize(bis); + #endif +@@ -197,6 +200,7 @@ + rtl8169_initialize(bis); + #endif + ++#if defined(CONFIG_NET_MULTI) + if (!eth_devices) { + puts ("No ethernet found.\n"); + } else { +@@ -248,7 +252,6 @@ + dev = dev->next; + } while(dev != eth_devices); + +-#ifdef CONFIG_NET_MULTI + /* update current ethernet name */ + if (eth_current) { + char *act = getenv("ethact"); +@@ -256,14 +259,14 @@ + setenv("ethact", eth_current->name); + } else + setenv("ethact", NULL); +-#endif +- + putc ('\n'); + } ++#endif + + return eth_number; + } + ++#ifdef CONFIG_NET_MULTI + void eth_set_enetaddr(int num, char *addr) { + struct eth_device *dev; + unsigned char enetaddr[6]; +@@ -362,21 +365,20 @@ + + eth_current = eth_current->next; + +-#ifdef CONFIG_NET_MULTI ++//#ifdef CONFIG_NET_MULTI + /* update current ethernet name */ + { + char *act = getenv("ethact"); + if (act == NULL || strcmp(act, eth_current->name) != 0) + setenv("ethact", eth_current->name); + } +-#endif ++//#endif + + if (first_failed == eth_current) { + NetRestartWrap = 1; + } + } + +-#ifdef CONFIG_NET_MULTI + void eth_set_current(void) + { + char *act; +@@ -397,10 +399,11 @@ + + setenv("ethact", eth_current->name); + } +-#endif + + char *eth_get_name (void) + { + return (eth_current ? eth_current->name : "unknown"); + } + #endif ++ ++#endif +diff -uNr u-boot-1.1.2/net/net.c u-boot-emetec-1.1.2/net/net.c +--- u-boot-1.1.2/net/net.c 2004-10-12 01:51:14.000000000 +0300 ++++ u-boot-emetec-1.1.2/net/net.c 2005-04-27 23:34:20.000000000 +0300 +@@ -126,11 +126,11 @@ + { 0x01, 0x00, 0x0c, 0xcc, 0xcc, 0xcc }; + #endif + int NetState; /* Network loop state */ +-#ifdef CONFIG_NET_MULTI ++/* #ifdef CONFIG_NET_MULTI */ + int NetRestartWrap = 0; /* Tried all network devices */ + static int NetRestarted = 0; /* Network loop restarted */ + static int NetDevExists = 0; /* At least one device configured */ +-#endif ++/* #endif */ + + /* XXX in both little & big endian machines 0xFFFF == ntohs(-1) */ + ushort NetOurVLAN = 0xFFFF; /* default is without VLAN */ +diff -uNr u-boot-1.1.2/patches/arm_flags.patch u-boot-emetec-1.1.2/patches/arm_flags.patch +--- u-boot-1.1.2/patches/arm_flags.patch 2007-04-20 00:01:06.000000000 +0300 ++++ u-boot-emetec-1.1.2/patches/arm_flags.patch 1970-01-01 02:00:00.000000000 +0200 +@@ -1,15 +0,0 @@ +- +-# +-# Patch managed by http://www.holgerschurig.de/patcher.html +-# +- +---- u-boot-1.1.2/cpu/pxa/config.mk~armflags +-+++ u-boot-1.1.2/cpu/pxa/config.mk +-@@ -23,6 +23,6 @@ +- # +- +- PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ +-- -mshort-load-bytes -msoft-float +-+ -msoft-float +- +- PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100 +diff -uNr u-boot-1.1.2/patches/series u-boot-emetec-1.1.2/patches/series +--- u-boot-1.1.2/patches/series 2007-04-20 00:01:06.000000000 +0300 ++++ u-boot-emetec-1.1.2/patches/series 1970-01-01 02:00:00.000000000 +0200 +@@ -1 +0,0 @@ +-arm_flags.patch -p1 +diff -uNr u-boot-1.1.2/lib_ppc/board.c new-uboot-1.1.2/lib_ppc/board.c +--- u-boot-1.1.2/lib_ppc/board.c 2005-04-27 23:03:33.000000000 +0300 ++++ new-uboot-1.1.2/lib_ppc/board.c 2007-04-20 00:55:16.000000000 +0300 +@@ -347,6 +347,7 @@ + + bd_t *bd; + ulong len, addr, addr_sp; ++ ulong *s; + gd_t *id; + init_fnc_t **init_fnc_ptr; + #ifdef CONFIG_PRAM +@@ -466,8 +467,10 @@ + */ + addr_sp -= 16; + addr_sp &= ~0xF; +- *((ulong *) addr_sp)-- = 0; +- *((ulong *) addr_sp)-- = 0; ++ s = (ulong *)addr_sp; ++ *s-- = 0; ++ *s-- = 0; ++ addr_sp = (ulong)s; + debug ("Stack Pointer at: %08lx\n", addr_sp); + + /* +diff -uNr u-boot-1.1.2/net/net.c new-uboot-1.1.2/net/net.c +--- u-boot-1.1.2/net/net.c 2005-04-27 23:34:20.000000000 +0300 ++++ new-uboot-1.1.2/net/net.c 2007-04-20 01:00:26.000000000 +0300 +@@ -1491,14 +1491,17 @@ + unsigned + NetCksum(uchar * ptr, int len) + { +- ulong xsum; + +- xsum = 0; +- while (len-- > 0) +- xsum += *((ushort *)ptr)++; +- xsum = (xsum & 0xffff) + (xsum >> 16); +- xsum = (xsum & 0xffff) + (xsum >> 16); +- return (xsum & 0xffff); ++ ulong xsum; ++ ushort *p = (ushort *)ptr; ++ ++ xsum = 0; ++ while (len-- > 0) ++ xsum += *p++; ++ xsum = (xsum & 0xffff) + (xsum >> 16); ++ xsum = (xsum & 0xffff) + (xsum >> 16); ++ return (xsum & 0xffff); ++ + } + + int +diff -uNr u-boot-1.1.2/net/tftp.c new-uboot-1.1.2/net/tftp.c +--- u-boot-1.1.2/net/tftp.c 2004-04-16 00:48:55.000000000 +0300 ++++ new-uboot-1.1.2/net/tftp.c 2005-12-16 18:39:27.000000000 +0200 +@@ -58,7 +58,7 @@ + static char *tftp_filename; + + #ifdef CFG_DIRECT_FLASH_TFTP +-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; ++extern flash_info_t flash_info[]; + #endif + + static __inline__ void +@@ -78,7 +78,7 @@ + } + + if (rc) { /* Flash is destination for this packet */ +- rc = flash_write ((uchar *)src, (ulong)(load_addr+offset), len); ++ rc = flash_write ((char *)src, (ulong)(load_addr+offset), len); + if (rc) { + flash_perror (rc); + NetState = NETLOOP_FAIL; +@@ -106,6 +106,7 @@ + volatile uchar * pkt; + volatile uchar * xp; + int len = 0; ++ volatile ushort *s; + + /* + * We will always be sending some sort of packet, so +@@ -117,7 +118,9 @@ + + case STATE_RRQ: + xp = pkt; +- *((ushort *)pkt)++ = htons(TFTP_RRQ); ++ s = (ushort *)pkt; ++ *s++ = htons(TFTP_RRQ); ++ pkt = (uchar *)s; + strcpy ((char *)pkt, tftp_filename); + pkt += strlen(tftp_filename) + 1; + strcpy ((char *)pkt, "octet"); +@@ -135,15 +138,19 @@ + case STATE_DATA: + case STATE_OACK: + xp = pkt; +- *((ushort *)pkt)++ = htons(TFTP_ACK); +- *((ushort *)pkt)++ = htons(TftpBlock); ++ s = (ushort *)pkt; ++ *s++ = htons(TFTP_ACK); ++ *s++ = htons(TftpBlock); ++ pkt = (uchar *)s; + len = pkt - xp; + break; + + case STATE_TOO_LARGE: + xp = pkt; +- *((ushort *)pkt)++ = htons(TFTP_ERROR); +- *((ushort *)pkt)++ = htons(3); ++ s = (ushort *)pkt; ++ *s++ = htons(TFTP_ERROR); ++ *s++ = htons(3); ++ pkt = (uchar *)s; + strcpy ((char *)pkt, "File too large"); + pkt += 14 /*strlen("File too large")*/ + 1; + len = pkt - xp; +@@ -151,8 +158,10 @@ + + case STATE_BAD_MAGIC: + xp = pkt; +- *((ushort *)pkt)++ = htons(TFTP_ERROR); +- *((ushort *)pkt)++ = htons(2); ++ s = (ushort *)pkt; ++ *s++ = htons(TFTP_ERROR); ++ *s++ = htons(2); ++ pkt = (uchar *)s; + strcpy ((char *)pkt, "File has bad magic"); + pkt += 18 /*strlen("File has bad magic")*/ + 1; + len = pkt - xp; +@@ -167,6 +176,7 @@ + TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len) + { + ushort proto; ++ ushort *s; + + if (dest != TftpOurPort) { + return; +@@ -180,7 +190,9 @@ + } + len -= 2; + /* warning: don't use increment (++) in ntohs() macros!! */ +- proto = *((ushort *)pkt)++; ++ s = (ushort *)pkt; ++ proto = *s++; ++ pkt = (uchar *)s; + switch (ntohs(proto)) { + + case TFTP_RRQ: +@@ -301,14 +313,16 @@ + void + TftpStart (void) + { +- if (BootFile[0] == '\0') { +- IPaddr_t OurIP = ntohl(NetOurIP); ++#ifdef CONFIG_TFTP_PORT ++ char *ep; /* Environment pointer */ ++#endif + ++ if (BootFile[0] == '\0') { + sprintf(default_filename, "%02lX%02lX%02lX%02lX.img", +- OurIP & 0xFF, +- (OurIP >> 8) & 0xFF, +- (OurIP >> 16) & 0xFF, +- (OurIP >> 24) & 0xFF ); ++ NetOurIP & 0xFF, ++ (NetOurIP >> 8) & 0xFF, ++ (NetOurIP >> 16) & 0xFF, ++ (NetOurIP >> 24) & 0xFF ); + tftp_filename = default_filename; + + printf ("*** Warning: no boot file name; using '%s'\n", +@@ -354,7 +368,16 @@ + TftpServerPort = WELL_KNOWN_PORT; + TftpTimeoutCount = 0; + TftpState = STATE_RRQ; ++ /* Use a pseudo-random port unless a specific port is set */ + TftpOurPort = 1024 + (get_timer(0) % 3072); ++#ifdef CONFIG_TFTP_PORT ++ if ((ep = getenv("tftpdstp")) != NULL) { ++ TftpServerPort = simple_strtol(ep, NULL, 10); ++ } ++ if ((ep = getenv("tftpsrcp")) != NULL) { ++ TftpOurPort= simple_strtol(ep, NULL, 10); ++ } ++#endif + TftpBlock = 0; + + /* zero out server ether in case the server ip has changed */ +diff -uNr u-boot-1.1.2/board/emetec405/flash.c new-uboot-1.1.2/board/emetec405/flash.c +--- u-boot-1.1.2/board/emetec405/flash.c 2007-04-20 00:40:26.000000000 +0300 ++++ new-uboot-1.1.2/board/emetec405/flash.c 2007-04-20 00:41:11.000000000 +0300 +@@ -31,6 +31,7 @@ + */ + static ulong flash_get_size (vu_long * addr, flash_info_t * info); + static void flash_get_offsets (ulong base, flash_info_t * info); ++static int write_word (flash_info_t *info, ulong dest, ulong data); + + /*----------------------------------------------------------------------- + */ diff --git a/packages/u-boot/u-boot-1.1.4/.mtn2git_empty b/packages/u-boot/u-boot-1.1.4/.mtn2git_empty new file mode 100644 index 0000000000..e69de29bb2 diff --git a/packages/u-boot/u-boot-1.1.4/u-boot-autoscript.patch b/packages/u-boot/u-boot-1.1.4/u-boot-autoscript.patch new file mode 100644 index 0000000000..1864b4494e --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/u-boot-autoscript.patch @@ -0,0 +1,12 @@ +--- u-boot-1.1.2/common/cmd_autoscript.c ++++ u-boot-1.1.2/common/cmd_autoscript.c +@@ -110,8 +110,8 @@ + return 1; + } + +- while (*len_ptr++); ++ do { len_ptr++; } while (!(*len_ptr)); + + /* make sure cmd is null terminated */ + memmove (cmd, (char *)len_ptr, len); + *(cmd + len) = 0; diff --git a/packages/u-boot/u-boot-1.1.4/u-boot-base.patch b/packages/u-boot/u-boot-1.1.4/u-boot-base.patch new file mode 100644 index 0000000000..d866c1c26e --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/u-boot-base.patch @@ -0,0 +1,913 @@ +--- a/MAKEALL ++++ a/MAKEALL +@@ -146,8 +146,8 @@ + + LIST_pxa=" \ + adsvix cerf250 cradle csb226 \ +- innokom lubbock pxa255_idp wepep250 \ +- xaeniax xm250 xsengine \ ++ gumstix innokom lubbock pxa255_idp \ ++ wepep250 xaeniax xm250 xsengine \ + " + + LIST_ixp="ixdp425" +--- a/Makefile ++++ a/Makefile +@@ -121,7 +121,6 @@ + # The "tools" are needed early, so put this first + # Don't include stuff already done in $(LIBS) + SUBDIRS = tools \ +- examples \ + post \ + post/cpu + .PHONY : $(SUBDIRS) +@@ -1078,6 +1077,9 @@ + csb226_config : unconfig + @./mkconfig $(@:_config=) arm pxa csb226 + ++gumstix_config : unconfig ++ @./mkconfig $(@:_config=) arm pxa gumstix ++ + innokom_config : unconfig + @./mkconfig $(@:_config=) arm pxa innokom + +--- a/board/gumstix/Makefile ++++ a/board/gumstix/Makefile +@@ -0,0 +1,47 @@ ++# ++# (C) Copyright 2004 ++# Craig Hughes, Gumstix Inc, ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = lib$(BOARD).a ++ ++OBJS := gumstix.o ++SOBJS := memsetup.o ++ ++$(LIB): $(OBJS) $(SOBJS) ++ $(AR) crv $@ $^ ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak .depend ++ ++######################################################################### ++ ++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) ++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ ++ ++-include .depend ++ ++######################################################################### +--- a/board/gumstix/config.mk ++++ a/board/gumstix/config.mk +@@ -0,0 +1,13 @@ ++# ++# This is config used for compilation of Gumstix sources ++# ++# You might change location of U-Boot in memory by setting right TEXT_BASE. ++# This allows for example having one copy located at the end of ram and stored ++# in flash device and later on while developing use other location to test ++# the code in RAM device only. ++# ++ ++TEXT_BASE = 0xA3F00000 ++ifeq ($(GUMSTIX_400MHZ),y) ++ PLATFORM_CPPFLAGS += -DCONFIG_GUMSTIX_CPUSPEED_400 ++endif +--- a/board/gumstix/early_refresh.S ++++ a/board/gumstix/early_refresh.S +@@ -0,0 +1,50 @@ ++#define COTULLA_CP15_B1_VAL 0x69052903 ++ /* Workaround for early termination of SDRAM autorefresh on exit from ++ processor's sleep state in B1 stepping of XPA250/210. (sighting 27004) ++ Need first forced refresh within 8 usec. ++ ++ - Code snippet received from validation team, slightly modified ++ ++ Notes: - MMU assumed to be inactive at this time, so use physical addresses ++ - Eboot didn't boot on A1 stepping without the leading exclusion, ++ so the core code must be restricted to B1 only. ++ */ ++ ++ mrc p15, 0, r9, c0, c0, 0 @ Grab CPU ID ++ ldr r3, =COTULLA_CP15_B1_VAL @ Load the B1 CPU ID value ++ cmp r9, r3 ++ bne EARLY_REFRESH_DONE ++ ++ @ Eboot loads BIN image into RAM, ++ @ turns off the MMU and then jumps here. ++ @ If we're already executing from RAM, don't mess with it ++ ++ mov r0, #0x400000 @ Just at the end of boot device addressing space ++ cmp r0, pc @ Are we executing from boot flash space? ++ bls EARLY_REFRESH_DONE @ if outside that space, skip this. ++ ++ ++ /* ++ Need to set MDREFR:DRI field to 0 for this to work. Side effect is ++ picking the MEMCLK:SDCLK ratio. The specified value (0x038FF000) ++ sets that ratio as 2:1. ++ This corresponds to the defaults after reset, including sleep reset. ++ 0x038ff000 == MDREFR_K2FREE | MDREFR_K1FREE | MDREFR_K0FREE | ++ MDREFR_K2DB2 | MDREFR_K2RUN | ++ MDREFR_K1DB2 | MDREFR_K1RUN | MDREFR_E1PIN | ++ MDREFR_K0DB2 | MDREFR_K0RUN | MDREFR_E0PIN ++ */ ++ ++ ldr r0, =0X48000004 @ Memory controller base physical addr+ REFR Offset. ++ mov r1, #0x03800000 ++ orr r1, r1, #0x000FF000 ++ str r1, [r0] ++ ++ mov r0, #CFG_DRAM_BASE ++ ldr r1, [r0] @ CAUSES the 1st row refresh to all partitions ++ mov r2, #0x2000 @ 8k loo ++1: ++ ldr r1, [r0] @ CAUSES a row refresh to all partitions ++ subs r2, r2, #0x1 ++ bpl 1b @ while >= 0 ++EARLY_REFRESH_DONE: +--- a/board/gumstix/gumstix.c ++++ a/board/gumstix/gumstix.c +@@ -0,0 +1,134 @@ ++/* ++ * Copyright (C) 2004 Gumstix, Inc. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ * Written by Craig Hughes ++ * ++ */ ++ ++#include ++#include ++ ++int board_init( void ){ ++ DECLARE_GLOBAL_DATA_PTR; ++ ++ gd->bd->bi_arch_number = 373; ++ gd->bd->bi_boot_params = 0xa0000100; ++ ++ PSSR = 0x20; ++ ++ GPDR1 = CFG_GPDR1_VAL; ++ GAFR1_L = CFG_GAFR1_L_VAL; ++ ++ return 0; ++} ++ ++int dram_init( void ){ ++ DECLARE_GLOBAL_DATA_PTR; ++ ++#if ( CONFIG_NR_DRAM_BANKS > 0 ) ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; ++#endif ++#if ( CONFIG_NR_DRAM_BANKS > 1 ) ++ gd->bd->bi_dram[1].start = PHYS_SDRAM_2; ++ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; ++#endif ++#if ( CONFIG_NR_DRAM_BANKS > 2 ) ++ gd->bd->bi_dram[2].start = PHYS_SDRAM_3; ++ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; ++#endif ++#if ( CONFIG_NR_DRAM_BANKS > 3 ) ++ gd->bd->bi_dram[3].start = PHYS_SDRAM_4; ++ gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; ++#endif ++ ++ return 0; ++} ++ ++extern flash_info_t flash_info[]; /* info for FLASH chips */ ++ ++static u8 system_serial[8]; ++ ++void get_board_serial(struct tag_serialnr *serialnr) ++{ ++ serialnr->high = (system_serial[0]<<24) + (system_serial[1]<<16) + (system_serial[2]<<8) + system_serial[3]; ++ serialnr->low = (system_serial[4]<<24) + (system_serial[5]<<16) + (system_serial[6]<<8) + system_serial[7]; ++} ++ ++/* ++ * This hash function converts a structured 64-bit number to an unstructured, more bit-random 64-bit number. ++ * The purpose is to provide more randomness for each bit of the system serial number, since we're going to ++ * be using some of its bits (by extraction) as the varying part of an ethernet MAC. So more random bits = ++ * less chance of collision ++ * ++ * The has algorithm is basically going to work by looping through each bit in the incoming number. If that bit ++ * is set, then we'll XOR our result with a bitmask; if not, then we leave the result and continue the loop. ++ * Each time through the loop, we rotate the bitmask by one bit position, so that each bit of the incoming number ++ * will affect half of the bits of the result, but which bits it modifies are unique to that incoming bit position ++ */ ++void gumstix_serial_hash(u8 *buf) ++{ ++ unsigned int bit_number,byte; ++ // Starting bitmask is 0b0101001100001111000000001111111100000000000000001111111111111111 ++ u8 xor_mask[] = { 0x53, 0x0F, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0xFF }; ++ ++ u8 result[8]; ++ ++ // Loop through all 64 bits ++ for(bit_number=0; bit_number<64; bit_number++) ++ { ++ // If the given bit is set in the incoming buffer ++ if(buf[bit_number/8] & (1 << (bit_number % 8))) ++ { ++ // XOR the masked bits of the result ++ for(byte=0;byte<8;byte++) result[byte] ^= xor_mask[byte]; ++ } ++ ++ // Now rotate the bitmask ++ for(byte=0;byte<8;byte++) ++ { ++ // Shift the byte up by one bit ++ xor_mask[byte] = xor_mask[byte]<<1; ++ // Take the most significant bit of the previous byte and tack that on the bottom ++ // Special case for byte==0 when we take the MSB of the top byte instead ++ xor_mask[byte] |= xor_mask[(byte == 0 ? 7 : byte-1)]>>7; ++ } ++ } ++ ++ // Copy result out ++ for(byte=0;byte<8;byte++) buf[byte]=result[byte]; ++} ++ ++int misc_init_r(void) ++{ ++ unsigned char serial[17]; ++ ++ flash_read_user_serial(flash_info, (void *)system_serial, 0, 8); ++ if(0xff == (system_serial[0] & system_serial[1] & system_serial[2] & system_serial[3] & ++ system_serial[4] & system_serial[5] & system_serial[6] & system_serial[7])) ++ { ++ // User serial number is all ones, so use the factory serial number ++ flash_read_factory_serial(flash_info, (void *)system_serial, 0, 8); ++ gumstix_serial_hash(system_serial); ++ } ++ ++ sprintf(serial,"%02lX%02lX%02lX%02lX%02lX%02lX%02lX%02lX",system_serial[0],system_serial[1],system_serial[2],system_serial[3], ++ system_serial[4],system_serial[5],system_serial[6],system_serial[7]); ++ ++ setenv("serial#",serial); ++} +--- a/board/gumstix/memsetup.S ++++ a/board/gumstix/memsetup.S +@@ -0,0 +1,229 @@ ++#include ++#include ++#include ++ ++ ++.macro CPWAIT ++ mrc p15,0,r0,c2,c0,0 ++ mov r0,r0 ++ sub pc,pc,#4 ++.endm ++ ++ ++.globl lowlevel_init ++lowlevel_init: ++ ++ ++ cmp pc, #0xa0000000 /** test if we're in SDRAM **/ ++ bhi end_of_memsetup /** if we are, then jump **/ ++ ++ /* First, setup GPIOs */ ++ ++ ldr r0, =GPSR0 ++ ldr r1, =CFG_GPSR0_VAL ++ str r1, [r0] ++ ++ ldr r0, =GPSR1 ++ ldr r1, =CFG_GPSR1_VAL ++ str r1, [r0] ++ ++ ldr r0, =GPSR2 ++ ldr r1, =CFG_GPSR2_VAL ++ str r1, [r0] ++ ++ ldr r0, =GPCR0 ++ ldr r1, =CFG_GPCR0_VAL ++ str r1, [r0] ++ ++ ldr r0, =GPCR1 ++ ldr r1, =CFG_GPCR1_VAL ++ str r1, [r0] ++ ++ ldr r0, =GPCR2 ++ ldr r1, =CFG_GPCR2_VAL ++ str r1, [r0] ++ ++ ldr r0, =GPDR0 ++ ldr r1, =CFG_GPDR0_VAL ++ str r1, [r0] ++ ++ ldr r0, =GPDR1 ++ ldr r1, =CFG_GPDR1_VAL ++ str r1, [r0] ++ ++ ldr r0, =GPDR2 ++ ldr r1, =CFG_GPDR2_VAL ++ str r1, [r0] ++ ++ ldr r0, =GAFR0_L ++ ldr r1, =CFG_GAFR0_L_VAL ++ str r1, [r0] ++ ++ ldr r0, =GAFR0_U ++ ldr r1, =CFG_GAFR0_U_VAL ++ str r1, [r0] ++ ++ ldr r0, =GAFR1_L ++ ldr r1, =CFG_GAFR1_L_VAL ++ str r1, [r0] ++ ++ ldr r0, =GAFR1_U ++ ldr r1, =CFG_GAFR1_U_VAL ++ str r1, [r0] ++ ++ ldr r0, =GAFR2_L ++ ldr r1, =CFG_GAFR2_L_VAL ++ str r1, [r0] ++ ++ ldr r0, =GAFR2_U ++ ldr r1, =CFG_GAFR2_U_VAL ++ str r1, [r0] ++ ++ ldr r0, =PSSR ++ ldr r1, =CFG_PSSR_VAL ++ str r1, [r0] ++ ++ ++ /* The procedure below uses sample code generated by the Intel PXA250 Memory ++ * Configuration Tool [http://appzone.intel.com/pcg/pxa250/memory/] which has ++ * then been modified manually while following the documentation in ++ * "Intel PXA255 Process Developer's Manual" [order #278693-002] ++ * Chapter 6.11 - Hardware, Watchdog, or Sleep Reset Operation */ ++ ++ /* Step 1: After hardware reset, complete a power-on wait of 200us to allow clocks to stabilize */ ++ ++ ldr r3, =OSCR /* reset the OS Timer Count to zero */ ++ mov r2, #0 ++ str r2, [r3] ++ ldr r4, =0x300 /* really 0x2E1 is about 200usec, so 0x300 should be plenty */ ++10: ++ ldr r2, [r3] ++ cmp r4, r2 ++ bgt 10b ++ ++ /* Step 1a: Write MSC0, MSC1, MSC2 */ ++ ldr r3, =MSC0 /* Configures /CS0 and /CS1 */ ++ ldr r2, =0x128C26AB /* Generated value */ ++ str r2, [r3] ++ ldr r2, [r3] /* the MSC register should be read after it is written with */ ++ /* a new value before an access to the memory is attempted. */ ++ /* (see MSC section of manual) */ ++ ldr r3, =MSC1 /* /CS2 and /CS3 */ ++ ldr r2, =0x0000128C /* Generated value */ ++ str r2, [r3] ++ ldr r2, [r3] ++ ++ /* Step 1b: Write MECR, MCMEM0, MCMEM1, MCATT0, MCATT1, MCIO0, MCIO1 (Skip on gumstix) */ ++ /* Step 1c: Write MDREFR:K0RUN and MDREFR:E0PIN. Configure MDREFR:K0DB2. Retain ++ * the current values of MDREFR:APD and MDREFR:SLFRSH. MDREFR:DRI must ++ * contain a valid value. Deassert MDREFR:KxFREE. (Skip on gumstix) */ ++ ++ ldr r3, =MDREFR ++ ldr r2, [r3] /* read MDREFR value */ ++ ++ ldr r1, =0xfff ++ bic r2, r2, r1 /* Clear DRI -- INTEL TOOL LEAVES THIS STEP OUT!! */ ++ orr r2, r2, #0x018 /* configure a valid SDRAM Refresh Interval (DRI) */ ++ str r2, [r3] ++ ++ /* Step 2: Configure Synchronous Static memory (Skip on gumstix) */ ++ ++ /* Step 4: In systems that contain SDRAM, transition the SDRAM controller through the following state sequence: ++ * a. self-refresh ++ * b. power-down ++ * c. PWRDNX ++ * d. NOP */ ++ ++ orr r2, r2, #0x00010000 /* assert K1RUN for SDCLK1 */ ++ bic r2, r2, #0x000A4000 /* clear K0DB2, K1DB2 and K2DB2 */ ++ str r2, [r3] /* change from "self-refresh and clock-stop" to "self-refresh" state */ ++ ++ bic r2, r2, #0x00400000 /* clear SLFRSH bit field */ ++ str r2, [r3] /* change from "self-refresh" to "Power-down" state */ ++ ++ orr r2, r2, #0x00008000 /* set the E1PIN bit field */ ++ str r2, [r3] /* change from "Power-down" to "PWRDNX" state */ ++ ++ nop /* no action is required to change from "PWRDNX" to "NOP" state */ ++ ++ /* Step 4f: Write MDCNFG (with enable bits deasserted), MDCNFG:DE3:2,1:0 set to 0. */ ++ ++ ldr r3, =MDCNFG /* Load the SDRAM Configuration register. Must not be enabled yet. */ ++ ldr r2, =0x000019C8 /* Value from Intel tool */ ++ str r2, [r3] /* Write to MDCNFG register */ ++ ++ /* Step 5: For systems that contain SDRAM, wait a specified NOP power-up waiting period required by ++ * the SDRAMs to ensure the SDRAMs receive a stable clock with a NOP condition */ ++ ++ ldr r3, =OSCR /* reset the OS Timer Count to zero */ ++ mov r2, #0 ++ str r2, [r3] ++ ldr r4, =0x300 /* really 0x2E1 is about 200usec, so 0x300 should be plenty */ ++20: ++ ldr r2, [r3] ++ cmp r4, r2 ++ bgt 20b ++ ++ /* Step 6: Ensure the data cache is disabled -- should not be needed out of reset, but best to be safe*/ ++ ++ mov r0, #0x78 /* turn everything off */ ++ mcr p15, 0, r0, c1, c0, 0 /* caches off, MMU off, etc. */ ++ ++ CPWAIT /* wait for co-processor */ ++ ++ /* Step 7: On a hardware reset in systems that contain SDRAM, trigger the specified number (typically ++ eight) of refresh cycles by attempting non-burst read or write accesses to any disabled ++ SDRAM bank. Each such access causes a simultaneous CBR refresh cycles for all four banks, ++ which causes a pass through the CBR state and back to NOP. On the first pass, the PALL state ++ occurs before the CBR state. */ ++ ++ ldr r3, =PHYS_SDRAM_1 ++ mov r2, #9 /* now must do 9 (!) refresh or CBR commands before the first access */ ++CBR_refresh1: ++ str r2, [r3] ++ subs r2, r2, #1 ++ bne CBR_refresh1 ++ ++ /* Step 8: Can re-enable DCACHE if it was disabled above (Skip on gumstix) */ ++ ++ /* Step 9: Enable SDRAM partitions */ ++ ++ ldr r3, =MDCNFG /* sdram config -- sdram enable */ ++ ldr r2, [r3] ++ orr r2, r2, #0x00000001 /* enable partition 0 only */ ++ str r2, [r3] /* write to MDCNFG */ ++ ++ /* Step 10: In systems containing SDRAM, write the MDMRS register to trigger an MRS command to all ++ * enabled banks of SDRAM. For each SDRAM partition pair that has one or both partitions ++ * enabled, this forces a pass through the MRS state and back to NOP. The CAS latency must be ++ * the only variable option and is derived from the value programmed in the ++ * MDCNFG:MDTC0,2 fields. The burst type is programmed to sequential and the length is set ++ * to four. */ ++ ++ ldr r3, =MDMRS /* write the MDMRS */ ++ ldr r2, =0x00020022 /* the writable bits will be written as a 0 */ ++ str r2, [r3] ++ ++ /* Step 11: (optional) Enable auto-power-down */ ++ ++ ldr r3, =MDREFR /* enable auto-power-down */ ++ ldr r2, [r3] ++ orr r2, r2, #0x00100000 /* set the APD bit */ ++ str r2, [r3] /* write to MDREFR */ ++ ++ /* enable the 32Khz oscillator for RTC and PowerManager */ ++ ++ ldr r1, =OSCC ++ mov r2, #OSCC_OON ++ str r2, [r1] ++ ++ /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ ++ /* has settled. */ ++/*60: ++ ldr r2, [r1] ++ ands r2, r2, #1 ++ beq 60b */ ++ ++end_of_memsetup: ++ mov pc, lr ++ +--- a/board/gumstix/u-boot.lds ++++ a/board/gumstix/u-boot.lds +@@ -0,0 +1,55 @@ ++/* ++ * (C) Copyright 2004 ++ * Craig Hughes, Gumstix Inc, ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++OUTPUT_ARCH(arm) ++ENTRY(_start) ++SECTIONS ++{ ++ . = 0x00000000; ++ ++ . = ALIGN(4); ++ .text : ++ { ++ cpu/pxa/start.o (.text) ++ board/gumstix/memsetup.o (.text) ++ *(.text) ++ } ++ . = ALIGN(4); ++ .rodata : { *(.rodata) } ++ ++ . = ALIGN(4); ++ .data : { *(.data) } ++ ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss : { *(.bss) } ++ _end = .; ++} +--- a/cpu/pxa/start.S ++++ a/cpu/pxa/start.S +@@ -91,6 +91,7 @@ + .word 0x0badc0de + #endif + ++.space 0x800 /* JTAG install interrupt vectors over low memory in instruction cache */ + + /****************************************************************************/ + /* */ +@@ -104,6 +105,37 @@ + orr r0,r0,#0x13 + msr cpsr,r0 + ++/* This special code just unprotects all of flash, then erases it */ ++// mov r0, #0x1f /* Loop over all blocks 0x1f-0x00*/ ++//flash_wipe_main_loop: ++// mov r1, r0, LSL #0x11 /* Convert bank number to start address */ ++// mov r2, #0x60 /* Clear lock bit setup */ ++// strh r2, [r1] ++// nop ++// mov r2, #0xd0 /* Clear lock bits confirm */ ++// strh r2, [r1] ++// nop ++//flash_clear_wait_loop: ++// ldrh r2, [r1] ++// tst r2, #0x80 /* Check SR.7 */ ++// bne flash_clear_wait_loop ++// ++// mov r2, #0x20 /* Block erase command */ ++// strh r2, [r1] ++// nop ++// mov r2, #0xd0 /* Block erase confirm */ ++// strh r2, [r1] ++// nop ++//flash_erase_wait_loop: ++// ldrh r2, [r1] ++// tst r2, #0x80 ++// bne flash_clear_wait_loop ++// ++// teq r0, #0 ++// subne r0, r0, #1 ++// bne flash_wipe_main_loop ++/* End of flash-nuking code */ ++ + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! +@@ -113,7 +145,7 @@ + #endif + + relocate: /* relocate U-Boot to RAM */ +- adr r0, _start /* r0 <- current position of code */ ++ adrl r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* don't reloc during debug */ + beq stack_setup +--- a/include/configs/gumstix.h ++++ a/include/configs/gumstix.h +@@ -0,0 +1,259 @@ ++/* ++ * Copyright (C) 2004 Gumstix, Inc. ++** ++** Gumstix u-boot 1.1.1 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ * Written by Craig Hughes 2004 ++ * ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_PXA250 /* this is an PXA250 CPU */ ++#define CONFIG_GUMSTIX /* config for gumstix board */ ++#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ ++#ifndef __LITTLE_ENDIAN ++#define __LITTLE_ENDIAN 1234 /* For some reason this is not defined */ ++#endif ++ ++/* ++ * Select serial console configuration FFUART is default on G dev board ++ */ ++ ++#define CONFIG_FFUART ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_SILENT_CONSOLE ++ ++/* ++ * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if ++ * neccessary in include/cmd_confdefs.h file. (Un)comment for getting ++ * functionality or size of u-boot code. ++ */ ++ ++#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \ ++ & ~CFG_CMD_CDP \ ++ & ~CFG_CMD_IDE \ ++ & ~CFG_CMD_IMLS \ ++ & ~CFG_CMD_IRQ \ ++ & ~CFG_CMD_PCMCIA \ ++ & ~CFG_CMD_SETGETDCR \ ++ | CFG_CMD_AUTOSCRIPT \ ++ | CFG_CMD_BDI \ ++ | CFG_CMD_BOOTD \ ++ | CFG_CMD_CACHE \ ++ | CFG_CMD_CONSOLE \ ++ | CFG_CMD_DHCP \ ++ | CFG_CMD_DIAG \ ++ | CFG_CMD_ECHO \ ++ | CFG_CMD_ELF \ ++ | CFG_CMD_ENV \ ++ | CFG_CMD_FAT \ ++ | CFG_CMD_FLASH \ ++ | CFG_CMD_IMI \ ++ | CFG_CMD_ITEST \ ++ | CFG_CMD_JFFS2 \ ++ | CFG_CMD_LOADB \ ++ | CFG_CMD_LOADS \ ++ | CFG_CMD_MEMORY \ ++ | CFG_CMD_MISC \ ++ | CFG_CMD_MMC \ ++ | CFG_CMD_NET \ ++ | CFG_CMD_NFS \ ++ | CFG_CMD_PING \ ++ | CFG_CMD_REGINFO \ ++ | CFG_CMD_RUN \ ++ | CFG_CMD_SAVES \ ++ | CFG_CMD_SDRAM \ ++ ) ++ ++ ++#define CONFIG_NETCONSOLE ++#define CONFIG_NET_MULTI ++ ++#define CFG_DEVICE_NULLDEV ++ ++#include ++ ++/* ++ * Boot options. Setting delay to -1 stops autostart count down. ++ * NOTE: Sending parameters to kernel depends on kernel version and ++ * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept ++ * parameters at all! Do not get confused by them so. ++*/ ++ ++#define CONFIG_IDENT_STRING "\n\n*** Welcome to Gumstix ***" ++#define CONFIG_MISC_INIT_R /* misc_init_r function in gumstix sets board serial number */ ++ ++#define CONFIG_BOOTFILE boot/uImage ++#define CONFIG_BOOTARGS "console=ttyS0,115200n8 root=1f01 rootfstype=jffs2 reboot=cold,hard" ++#define CONFIG_BOOTCOMMAND "icache on;setenv stderr nulldev; setenv stdout nulldev; if mmcinit && fatload mmc 0 a2000000 gumstix-factory.script; then setenv stdout serial; setenv stderr serial; echo Found gumstix-factory script...; autoscr; else setenv stdout serial;setenv stderr serial;fsload && bootm; fi" ++#define CONFIG_BOOTDELAY 2 /* in seconds */ ++#define CONFIG_EXTRA_ENV_SETTINGS "verify=no" ++#define CFG_HUSH_PARSER ++#define CFG_AUTO_COMPLETE ++#define CFG_PROMPT_HUSH_PS2 "> " ++ ++/* ++ * General options for u-boot. Modify to save memory foot print ++ */ ++ ++#define CFG_LONGHELP /* undef saves memory */ ++#define CFG_PROMPT "GUM> " /* prompt string */ ++#define CFG_CBSIZE 512 /* console I/O buffer */ ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */ ++#define CFG_MAXARGS 16 /* max command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */ ++ ++#define CONFIG_CRC32_VERIFY ++#define CONFIG_LOOPW ++#define CONFIG_MX_CYCLIC ++ ++/* ++ * * SMSC91C111 Network Card ++ * */ ++#define CONFIG_DRIVER_SMC91111 1 ++#define CONFIG_SMC91111_BASE 0x04000300 /* chip select 1 */ ++#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */ ++#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ ++#undef CONFIG_SHOW_ACTIVITY ++#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ ++#define CONFIG_ETHPRIME "SMC91C1111-0" ++#define CONFIG_ETHADDR 00:0A:95:A5:47:3A ++ ++ ++#define CFG_MEMTEST_START 0xa1000000 /* memtest test area */ ++#define CFG_MEMTEST_END 0xa2000000 ++ ++ ++#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */ ++#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ ++#ifdef CONFIG_GUMSTIX_CPUSPEED_400 ++#define CFG_CPUSPEED 0x161 /* 0x161 == 400MHz, 0x141 ==200MHz */ ++#else ++#define CFG_CPUSPEED 0x141 ++#endif ++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } ++ ++#define CFG_CONSOLE_INFO_QUIET ++ ++/* ++ * Definitions related to passing arguments to kernel. ++ */ ++#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ ++#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ ++#define CONFIG_INITRD_TAG /* send initrd params */ ++#define CONFIG_SERIAL_TAG /* send serialnr from flash */ ++#undef CONFIG_VFD /* do not send framebuffer setup */ ++ ++/* ++ * SDRAM Memory Map ++ */ ++#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ ++#define PHYS_SDRAM_1 0xa0000000 /* SDRAM bank #1 */ ++#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB ( 2 chip ) */ ++ ++#define CFG_DRAM_BASE PHYS_SDRAM_1 ++#define CFG_DRAM_SIZE PHYS_SDRAM_1_SIZE ++ ++/* ++ * Configuration for FLASH memory ++ */ ++#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ ++#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors */ ++ ++#define CFG_FLASH_BASE PHYS_FLASH_1 ++#define CFG_FLASH_CFI /* flash is CFI conformant */ ++#define CFG_FLASH_CFI_DRIVER /* use common cfi driver */ ++#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ ++#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ ++#define CFG_MAX_FLASH_SECT 256 /* max # of sectors on one chip */ ++#define CFG_FLASH_PROTECTION /* use hardware flash protection */ ++ ++#define CFG_ENV_IS_IN_FLASH ++#define CFG_ENV_SIZE 0x1000 /* 4kB */ ++#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE ++#define CFG_ENV_ADDR ((CFG_FLASH_BASE + CFG_ENV_SECT_SIZE*2) - CFG_ENV_SIZE) ++ ++/* ++ * Malloc pool need to host env + 128 Kb reserve for other allocations. ++ */ ++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) ) ++#define CONFIG_STACKSIZE (120<<10) /* stack size */ ++#define CFG_GBL_DATA_SIZE 512 /* num bytes initial data */ ++ ++/* ++ * This is setting for JFFS2 support in u-boot. ++ * Right now there is no gain for user, but later on booting kernel might be ++ * possible. Consider using XIP kernel running from flash to save RAM ++ * footprint. ++ * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support. ++ */ ++ ++#define CFG_JFFS2_FIRST_BANK 0 ++#define CFG_JFFS2_FIRST_SECTOR 2 ++#define CFG_JFFS2_NUM_BANKS 1 ++ ++#define CONFIG_MMC 1 ++#define CFG_MMC_BASE 0xF0000000 ++#define CONFIG_DOS_PARTITION ++ ++/* ++ * Environment setup. Definitions of monitor location and size with ++ * definition of environment setup ends up in 2 possibilities. ++ * 1. Embedded environment - in u-boot code is space for environment ++ * 2. Environment is read from predefined sector of flash ++ * Right now we support 2. possiblity, but expecting no env placed ++ * on mentioned address right now. This also needs to provide whole ++ * sector for it - for us 256Kb is really waste of memory. U-boot uses ++ * default env. and until kernel parameters could be sent to kernel ++ * env. has no sense to us. ++ */ ++ ++#define CFG_MONITOR_BASE CFG_FLASH_BASE ++#define CFG_MONITOR_LEN (PHYS_FLASH_SECT_SIZE*2 - CFG_ENV_SIZE) ++ ++#define CFG_GPSR0_VAL 0xFFFFFFFF ++#define CFG_GPSR1_VAL 0xFFEFFFFF ++#define CFG_GPSR2_VAL 0xFFFEFFFF ++ ++#define CFG_GPCR0_VAL 0x08022080 ++#define CFG_GPCR1_VAL 0x00100000 ++#define CFG_GPCR2_VAL 0x00010000 ++ ++#define CFG_GPDR0_VAL 0xC182B9F8 ++#define CFG_GPDR1_VAL 0x0012AA80 ++#define CFG_GPDR2_VAL 0x0001FFFF ++ ++#define CFG_GAFR0_L_VAL 0x81011000 ++#define CFG_GAFR0_U_VAL 0xA5254010 ++#define CFG_GAFR1_L_VAL 0x69908010 ++#define CFG_GAFR1_U_VAL 0xAAA5A8AA ++#define CFG_GAFR2_L_VAL 0xAAAAAAAA ++#define CFG_GAFR2_U_VAL 0x00000000 ++ ++#define CFG_PSSR_VAL 0x20 ++ ++/* ++ * Well this has to be defined, but on the other hand it is used differently ++ * one may expect. For instance loadb command do not cares :-) ++ * So advice is - do not rely on this... ++ */ ++ ++#define CFG_LOAD_ADDR 0xA2000000 ++#endif /* __CONFIG_H */ +--- a/lib_arm/board.c ++++ a/lib_arm/board.c +@@ -200,10 +200,10 @@ + NULL, + }; + ++DECLARE_GLOBAL_DATA_PTR; ++ + void start_armboot (void) + { +- DECLARE_GLOBAL_DATA_PTR; +- + ulong size; + init_fnc_t **init_fnc_ptr; + char *s; diff --git a/packages/u-boot/u-boot-1.1.4/u-boot-crc-warning-not-so-scary.patch b/packages/u-boot/u-boot-1.1.4/u-boot-crc-warning-not-so-scary.patch new file mode 100644 index 0000000000..b5736894c6 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/u-boot-crc-warning-not-so-scary.patch @@ -0,0 +1,11 @@ +--- u-boot-1.1.2/common/env_common.c 2005-06-15 12:38:53.632219409 -0700 ++++ u-boot-1.1.2/common/env_common.c 2005-06-15 12:39:41.469052324 -0700 +@@ -237,7 +237,7 @@ + #if defined(CONFIG_GTH) || defined(CFG_ENV_IS_NOWHERE) /* Environment not changable */ + puts ("Using default environment\n\n"); + #else ++ puts ("Using default environment\n\n"); +- puts ("*** Warning - bad CRC, using default environment\n\n"); + SHOW_BOOT_PROGRESS (-1); + #endif + diff --git a/packages/u-boot/u-boot-1.1.4/u-boot-dht-walnut-df2.patch b/packages/u-boot/u-boot-1.1.4/u-boot-dht-walnut-df2.patch new file mode 100644 index 0000000000..d919ea504e --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/u-boot-dht-walnut-df2.patch @@ -0,0 +1,186 @@ +diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c +index f1a96a6..86bcc65 100644 +--- a/board/amcc/walnut/walnut.c ++++ b/board/amcc/walnut/walnut.c +@@ -73,7 +73,11 @@ int checkboard(void) + if (pvr == PVR_405GPR_RB) { + puts("Board: Sycamore - AMCC PPC405GPr Evaluation Board"); + } else { ++#ifdef CONFIG_DHT_WALNUT ++ puts("Board: DHT Walnut"); ++#else + puts("Board: Walnut - AMCC PPC405GP Evaluation Board"); ++#endif + } + + if (s != NULL) { +diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c +index ebd5f39..1c4c4b1 100644 +--- a/cpu/ppc4xx/spd_sdram.c ++++ b/cpu/ppc4xx/spd_sdram.c +@@ -398,19 +398,24 @@ long int spd_sdram(int(read_spd)(uint ad + + tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1; + sdram0_b0cr = (bank_size * 0) | tmp; +-#ifndef CONFIG_405EP /* not on PPC405EP */ ++#if defined(CONFIG_405EP) ++ /* PPC405EP chip only supports two SDRAM banks */ ++ if (bank_cnt > 1) ++ sdram0_b1cr = (bank_size * 1) | tmp; ++ if (bank_cnt > 2) ++ total_size = 2 * bank_size; ++#elif defined(CONFIG_DHT_WALNUT) ++ if (bank_cnt > 1) { ++ sdram0_b2cr = (bank_size * 1) | tmp; ++ total_size = 2 * bank_size; ++ } ++#else + if (bank_cnt > 1) + sdram0_b2cr = (bank_size * 1) | tmp; + if (bank_cnt > 2) + sdram0_b1cr = (bank_size * 2) | tmp; + if (bank_cnt > 3) + sdram0_b3cr = (bank_size * 3) | tmp; +-#else +- /* PPC405EP chip only supports two SDRAM banks */ +- if (bank_cnt > 1) +- sdram0_b1cr = (bank_size * 1) | tmp; +- if (bank_cnt > 2) +- total_size = 2 * bank_size; + #endif + + /* +diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c +index 3302457..7f6d33a 100644 +--- a/drivers/pci_auto.c ++++ b/drivers/pci_auto.c +@@ -296,10 +296,12 @@ int pciauto_config_device(struct pci_con + + case PCI_CLASS_STORAGE_IDE: + pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface); ++#ifndef CONFIG_DHT_WALNUT + if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) { + DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n"); + return sub_bus; + } ++#endif + + pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io); + break; +diff --git a/include/configs/walnut.h b/include/configs/walnut.h +index 1171ee5..df9e8ac 100644 +--- a/include/configs/walnut.h ++++ b/include/configs/walnut.h +@@ -37,6 +37,7 @@ + #define CONFIG_4xx 1 /* ...member of PPC4xx family */ + #define CONFIG_WALNUT 1 /* ...on a WALNUT board */ + /* ...and on a SYCAMORE board */ ++#define CONFIG_DHT_WALNUT 1 /* Just like a walnut, but .... */ + + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +@@ -88,10 +89,36 @@ + #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + + #define CONFIG_MII 1 /* MII PHY management */ ++#ifdef CONFIG_DHT_WALNUT ++#define CONFIG_ETHADDR de:ad:be:ef:00:00 ++#define CONFIG_ENV_OVERWRITE 1 ++#define CONFIG_PHY_ADDR 9 /* PHY address */ ++#else + #define CONFIG_PHY_ADDR 1 /* PHY address */ ++#endif + + #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */ + ++#ifdef CONFIG_DHT_WALNUT ++#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ ++ CFG_CMD_ASKENV | \ ++ CFG_CMD_DATE | \ ++ CFG_CMD_DHCP | \ ++ CFG_CMD_DIAG | \ ++ CFG_CMD_ELF | \ ++ CFG_CMD_I2C | \ ++ CFG_CMD_IRQ | \ ++ CFG_CMD_MII | \ ++ CFG_CMD_NET | \ ++ CFG_CMD_NFS | \ ++ CFG_CMD_PCI | \ ++ CFG_CMD_PING | \ ++ CFG_CMD_REGINFO | \ ++ CFG_CMD_SDRAM | \ ++ CFG_CMD_IDE | \ ++ CFG_CMD_BEDBUG | \ ++ CFG_CMD_SNTP ) ++#else + #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ +@@ -108,6 +135,7 @@ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP ) ++#endif + + /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ + #include +@@ -151,7 +179,7 @@ + #define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +-#define CFG_LOAD_ADDR 0x100000 /* default load address */ ++#define CFG_LOAD_ADDR 0x200000 /* default load address */ + #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + + #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +@@ -198,6 +226,50 @@ + #define CFG_PCI_PTM2MS 0x00000000 /* disabled */ + #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + ++#ifdef CONFIG_DHT_WALNUT ++/*********************************************************************** ++ * External peripheral base address ++ ***********************************************************************/ ++#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000 ++ ++/************************************************************ ++ * IDE/ATA stuff ++ ************************************************************/ ++#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */ ++#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 per IDE bus */ ++ ++#define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */ ++#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offset */ ++#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ ++#define CFG_ATA_REG_OFFSET 0 /* reg offset */ ++#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ ++ ++#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ ++#undef CONFIG_IDE_LED /* no led for ide supported */ ++#undef CONFIG_IDE_RESET /* no reset for ide supported */ ++ ++#define CONFIG_LBA48 1 ++#define CONFIG_MAC_PARTITION 1 ++#define CONFIG_DOS_PARTITION 1 ++#define CONFIG_ISO_PARTITION 1 ++ ++#define CONFIG_SUPPORT_VFAT ++ ++/************************************************************ ++ * ATAPI support (experimental) ++ ************************************************************/ ++#define CONFIG_ATAPI /* enable ATAPI Support */ ++ ++/************************************************************ ++ * SCSI support (experimental) only SYM53C8xx supported ++ ************************************************************/ ++#define CONFIG_SCSI_SYM53C8XX ++#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */ ++#define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */ ++#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */ ++#define CFG_SCSI_SPIN_UP_TIME 2 ++#endif ++ + /*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) diff --git a/packages/u-boot/u-boot-1.1.4/u-boot-flash-protect-fixup.patch b/packages/u-boot/u-boot-1.1.4/u-boot-flash-protect-fixup.patch new file mode 100644 index 0000000000..1bbbbcb32d --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/u-boot-flash-protect-fixup.patch @@ -0,0 +1,11 @@ +--- a/drivers/cfi_flash.c ++++ a/drivers/cfi_flash.c +@@ -345,7 +345,7 @@ + #endif + + /* Environment protection ON by default */ +-#ifdef CFG_ENV_IS_IN_FLASH ++#if defined(CFG_ENV_IS_IN_FLASH) && (CFG_MONITOR_BASE + CFG_MONITOR_LEN < CFG_ENV_ADDR) + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, diff --git a/packages/u-boot/u-boot-1.1.4/u-boot-fw_printenv.patch b/packages/u-boot/u-boot-1.1.4/u-boot-fw_printenv.patch new file mode 100644 index 0000000000..5e33452d11 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/u-boot-fw_printenv.patch @@ -0,0 +1,139 @@ +--- u-boot/tools/env/fw_env.c 2006-03-17 17:21:00.000000000 -0800 ++++ u-boot/tools/env/fw_env.c 2006-03-17 17:53:41.000000000 -0800 +@@ -31,8 +31,9 @@ + #include + #include + #include +-#include ++#include + #include "fw_env.h" ++#include "config.h" + + typedef unsigned char uchar; + +@@ -54,8 +55,6 @@ + #define ENVSIZE(i) envdevices[(i)].env_size + #define DEVESIZE(i) envdevices[(i)].erase_size + +-#define CFG_ENV_SIZE ENVSIZE(curdev) +- + #define ENV_SIZE getenvsize() + + typedef struct environment_s { +@@ -418,8 +417,8 @@ + fdr = fd; + } + printf ("Unlocking flash...\n"); +- erase.length = DEVESIZE (otherdev); +- erase.start = DEVOFFSET (otherdev); ++ erase.length = DEVESIZE (otherdev)*2; ++ erase.start = 0; + ioctl (fdr, MEMUNLOCK, &erase); + + if (HaveRedundEnv) { +@@ -439,7 +438,7 @@ + strerror (errno)); + return (-1); + } +- if (lseek (fdr, DEVOFFSET (otherdev) + CFG_ENV_SIZE, SEEK_SET) ++ if (lseek (fdr, DEVESIZE(otherdev), SEEK_SET) + == -1) { + fprintf (stderr, "seek error on %s: %s\n", + DEVNAME (otherdev), +@@ -458,7 +457,7 @@ + printf ("Erasing old environment...\n"); + + erase.length = DEVESIZE (otherdev); +- erase.start = DEVOFFSET (otherdev); ++ erase.start = DEVESIZE (otherdev); + if (ioctl (fdr, MEMERASE, &erase) != 0) { + fprintf (stderr, "MTD erase error on %s: %s\n", + DEVNAME (otherdev), +@@ -469,6 +468,22 @@ + printf ("Done\n"); + + printf ("Writing environment to %s...\n", DEVNAME (otherdev)); ++ if (resid) { ++ if (lseek(fdr, DEVESIZE(otherdev), SEEK_SET) ++ == -1) { ++ fprintf(stderr, "seek error on %s: %s\n", ++ DEVNAME(otherdev), ++ strerror(errno)); ++ return -1; ++ } ++ if (write (fdr, data, resid) != resid) { ++ fprintf (stderr, ++ "write error on %s: %s\n", ++ DEVNAME (curdev), strerror (errno)); ++ return (-1); ++ } ++ free (data); ++ } + if (lseek (fdr, DEVOFFSET (otherdev), SEEK_SET) == -1) { + fprintf (stderr, + "seek error on %s: %s\n", +@@ -487,15 +502,6 @@ + DEVNAME (otherdev), strerror (errno)); + return (-1); + } +- if (resid) { +- if (write (fdr, data, resid) != resid) { +- fprintf (stderr, +- "write error on %s: %s\n", +- DEVNAME (curdev), strerror (errno)); +- return (-1); +- } +- free (data); +- } + if (HaveRedundEnv) { + /* change flag on current active env partition */ + if (lseek (fd, DEVOFFSET (curdev) + sizeof (ulong), SEEK_SET) +@@ -514,8 +520,8 @@ + } + printf ("Done\n"); + printf ("Locking ...\n"); +- erase.length = DEVESIZE (otherdev); +- erase.start = DEVOFFSET (otherdev); ++ erase.length = DEVESIZE (otherdev)*2; ++ erase.start = 0; + ioctl (fdr, MEMLOCK, &erase); + if (HaveRedundEnv) { + erase.length = DEVESIZE (curdev); +--- u-boot/tools/env/fw_env.h 2006-03-17 17:16:37.000000000 -0800 ++++ u-boot/tools/env/fw_env.h 2006-03-17 17:53:41.000000000 -0800 +@@ -27,25 +27,17 @@ + * See included "fw_env.config" sample file (TRAB board) + * for notes on configuration. + */ +-#define CONFIG_FILE "/etc/fw_env.config" ++//#define CONFIG_FILE "/etc/fw_env.config" + +-#define HAVE_REDUND /* For systems with 2 env sectors */ +-#define DEVICE1_NAME "/dev/mtd1" +-#define DEVICE2_NAME "/dev/mtd2" +-#define DEVICE1_OFFSET 0x0000 +-#define ENV1_SIZE 0x4000 +-#define DEVICE1_ESIZE 0x4000 +-#define DEVICE2_OFFSET 0x0000 +-#define ENV2_SIZE 0x4000 +-#define DEVICE2_ESIZE 0x4000 +- +-#define CONFIG_BAUDRATE 115200 +-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +-#define CONFIG_BOOTCOMMAND \ +- "bootp; " \ +- "setenv bootargs root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ +- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ +- "bootm" ++//#define HAVE_REDUND /* For systems with 2 env sectors */ ++#define DEVICE1_NAME "/dev/mtd0" ++//#define DEVICE2_NAME "/dev/mtd2" ++#define DEVICE1_OFFSET CFG_ENV_ADDR ++#define ENV1_SIZE CFG_ENV_SIZE ++#define DEVICE1_ESIZE CFG_ENV_SECT_SIZE ++//#define DEVICE2_OFFSET 0x0000 ++//#define ENV2_SIZE 0x4000 ++//#define DEVICE2_ESIZE 0x4000 + + extern void fw_printenv(int argc, char *argv[]); + extern unsigned char *fw_getenv (unsigned char *name); diff --git a/packages/u-boot/u-boot-1.1.4/u-boot-install.patch b/packages/u-boot/u-boot-1.1.4/u-boot-install.patch new file mode 100644 index 0000000000..50c149c0a1 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/u-boot-install.patch @@ -0,0 +1,102 @@ +--- u-boot-1.1.2/common/Makefile 2004-12-16 09:35:57.000000000 -0800 ++++ u-boot-install/common/Makefile 2005-04-12 07:00:25.000000000 -0700 +@@ -34,7 +34,7 @@ + cmd_date.o cmd_dcr.o cmd_diag.o cmd_doc.o cmd_dtt.o \ + cmd_eeprom.o cmd_elf.o cmd_ext2.o \ + cmd_fat.o cmd_fdc.o cmd_fdos.o cmd_flash.o cmd_fpga.o \ +- cmd_i2c.o cmd_ide.o cmd_immap.o cmd_itest.o cmd_jffs2.o \ ++ cmd_i2c.o cmd_ide.o cmd_immap.o cmd_install.o cmd_itest.o cmd_jffs2.o \ + cmd_load.o cmd_log.o \ + cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \ + cmd_nand.o cmd_net.o cmd_nvedit.o \ +--- u-boot-1.1.2/common/cmd_install.c 1969-12-31 16:00:00.000000000 -0800 ++++ u-boot-install/common/cmd_install.c 2005-04-12 07:43:10.000000000 -0700 +@@ -0,0 +1,70 @@ ++/* ++ * (C) Copyright 2005 ++ * Craig Hughes, Gumstix Inc. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* ++ * Install command to copy compiled-in binary to flash ++ * ++ */ ++ ++#include ++#include ++#if (CONFIG_COMMANDS & CFG_CMD_INSTALL) ++ ++#ifdef CONFIG_GUMSTIX_CPUSPEED_400 ++#include ++#else ++#include ++#endif ++ ++int do_install ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ++{ ++ int rc; ++ size_t sect_top; ++ ++ if (argc != 1) { ++ printf ("Usage:\n%s\n", cmdtp->usage); ++ return 1; ++ } ++ ++ for(sect_top=0; sect_topstart[i], 12); ++ } ++} ++ + int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) + { + flash_info_t *info; + ulong bank, addr_first, addr_last; + int n, sect_first, sect_last; + #if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) + struct mtd_device *dev; + struct part_info *part; + u8 dev_type, dev_num, pnum; + #endif + int rcode = 0; ++ int jffs2erase = 0; + + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + ++ // Special JFFS2 erase which will write a JFFS2 "clean" header after the erase ++ if('j' == argv[0][0]) ++ { ++ jffs2erase = 1; ++ } ++ + if (strcmp(argv[1], "all") == 0) { + for (bank=1; bank<=CFG_MAX_FLASH_BANKS; ++bank) { + printf ("Erase Flash Bank # %ld ", bank); + info = &flash_info[bank-1]; + rcode = flash_erase (info, 0, info->sector_count-1); ++ if(jffs2erase) jffs2_write_header(info, 0, info->sector_count-1); + } + return rcode; + } +@@ -235,6 +257,7 @@ + printf ("Erase Flash Sectors %d-%d in Bank # %d ", + sect_first, sect_last, (info-flash_info)+1); + rcode = flash_erase(info, sect_first, sect_last); ++ if(jffs2erase) jffs2_write_header(info, sect_first, sect_last); + return rcode; + } + +@@ -253,6 +276,7 @@ + printf ("Erase Flash Bank # %ld ", bank); + info = &flash_info[bank-1]; + rcode = flash_erase (info, 0, info->sector_count-1); ++ if(jffs2erase) jffs2_write_header(info, 0, info->sector_count-1); + return rcode; + } + +@@ -264,6 +288,12 @@ + return 1; + } + ++ if (jffs2erase) ++ { ++ printf ("Usage:\n%s\n", cmdtp->usage); ++ return 1; ++ } ++ + rcode = flash_sect_erase(addr_first, addr_last); + return rcode; + } +@@ -517,6 +547,16 @@ + ); + + U_BOOT_CMD( ++ jerase, 3, 1, do_flerase, ++ "jerase - erase FLASH memory for JFFS2\n", ++ "jerase N:SF[-SL]\n - erase sectors SF-SL in FLASH bank # N\n" ++ "jerase bank N\n - erase FLASH bank # N\n" ++ "jerase all\n - erase all FLASH banks\n" ++ " in each case, after erasing a flash sector, that sector\n" ++ " has a JFFS2 'clean' marker written to it\n" ++); ++ ++U_BOOT_CMD( + protect, 4, 1, do_protect, + "protect - enable or disable FLASH write protection\n", + "on start end\n" diff --git a/packages/u-boot/u-boot-1.1.4/u-boot-jffs2-new-nodetypes.patch b/packages/u-boot/u-boot-1.1.4/u-boot-jffs2-new-nodetypes.patch new file mode 100644 index 0000000000..cce41aca18 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/u-boot-jffs2-new-nodetypes.patch @@ -0,0 +1,25 @@ +--- u-boot-1.1.4/fs/jffs2/jffs2_1pass.c-orig 2006-03-17 07:46:53.000000000 -0800 ++++ u-boot-1.1.4/fs/jffs2/jffs2_1pass.c 2006-03-17 07:59:37.000000000 -0800 +@@ -1194,6 +1194,10 @@ + printf("OOPS Padding has bad size " + "%d < %d\n", node->totlen, + sizeof(struct jffs2_unknown_node)); ++ } else if (node->nodetype == JFFS2_NODETYPE_ERASEBLOCK_HEADER) { ++ // Could check offset here to ensure we're at start of erase block ++ } else if (node->nodetype == JFFS2_NODETYPE_SUMMARY) { ++ // Ignore summary blocks for now + } else { + printf("Unknown node type: %x len %d " + "offset 0x%x\n", node->nodetype, +--- u-boot-1.1.4/include/jffs2/jffs2.h-orig 2006-03-17 08:20:01.000000000 -0800 ++++ u-boot-1.1.4/include/jffs2/jffs2.h 2006-03-17 08:20:20.000000000 -0800 +@@ -90,6 +90,9 @@ + #define JFFS2_NODETYPE_CLEANMARKER (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3) + #define JFFS2_NODETYPE_PADDING (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 4) + ++#define JFFS2_NODETYPE_ERASEBLOCK_HEADER (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 5) ++#define JFFS2_NODETYPE_SUMMARY (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 6) ++ + /* Maybe later... */ + /*#define JFFS2_NODETYPE_CHECKPOINT (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3) */ + /*#define JFFS2_NODETYPE_OPTIONS (JFFS2_FEATURE_RWCOMPAT_COPY | JFFS2_NODE_ACCURATE | 4) */ diff --git a/packages/u-boot/u-boot-1.1.4/u-boot-loadb-safe.patch b/packages/u-boot/u-boot-1.1.4/u-boot-loadb-safe.patch new file mode 100644 index 0000000000..d4b8ef3935 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/u-boot-loadb-safe.patch @@ -0,0 +1,16 @@ +diff -bBdurNP u-boot-1.1.1/common/cmd_load.c u-boot/common/cmd_load.c +--- u-boot-1.1.1/common/cmd_load.c 2004-03-11 16:14:10.000000000 -0800 ++++ u-boot/common/cmd_load.c 2004-09-30 00:19:43.656640004 -0700 +@@ -454,6 +454,12 @@ + if (argc >= 2) { + offset = simple_strtoul(argv[1], NULL, 16); + } ++ ++ if(offset < CFG_DRAM_BASE || offset > (CFG_DRAM_BASE+CFG_DRAM_SIZE)) { ++ printf("Cannot load to 0x%08lX -- address not in RAM\n",offset); ++ return 1; ++ } ++ + if (argc == 3) { + load_baudrate = (int)simple_strtoul(argv[2], NULL, 10); + diff --git a/packages/u-boot/u-boot-1.1.4/u-boot-make381-fix.patch b/packages/u-boot/u-boot-1.1.4/u-boot-make381-fix.patch new file mode 100644 index 0000000000..89555ac027 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/u-boot-make381-fix.patch @@ -0,0 +1,15 @@ +--- /examples/orig-Makefile 2005-12-16 18:39:27.000000000 +0200 ++++ /examples/Makefile 2006-12-02 14:58:59.000000000 +0200 +@@ -123,10 +123,10 @@ + $(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \ + -o $@ -e $(<:.o=) $< $(LIB) \ + -L$(gcclibdir) -lgcc +-%.srec: % ++%.srec: %.o + $(OBJCOPY) -O srec $< $@ 2>/dev/null + +-%.bin: % ++%.bin: %.o + $(OBJCOPY) -O binary $< $@ 2>/dev/null + + ######################################################################### diff --git a/packages/u-boot/u-boot-1.1.4/u-boot-mmc-init.patch b/packages/u-boot/u-boot-1.1.4/u-boot-mmc-init.patch new file mode 100644 index 0000000000..a18d4d3609 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/u-boot-mmc-init.patch @@ -0,0 +1,24 @@ +--- a/cpu/pxa/mmc.c ++++ a/cpu/pxa/mmc.c +@@ -401,16 +401,17 @@ + + /* reset */ + retries = 10; +- resp = mmc_cmd(0, 0, 0, 0); +- resp = mmc_cmd(1, 0x00ff, 0xc000, MMC_CMDAT_INIT|MMC_CMDAT_BUSY|MMC_CMDAT_R3); ++ resp = mmc_cmd(0, 0, 0, MMC_CMDAT_INIT|MMC_CMDAT_BUSY|MMC_CMDAT_R1); ++ udelay(200000); ++ resp = mmc_cmd(1, 0x00ff, 0x8000, MMC_CMDAT_BUSY|MMC_CMDAT_R3); + while (retries-- && resp && !(resp[4] & 0x80)) { + debug("resp %x %x\n", resp[0], resp[1]); + #ifdef CONFIG_PXA27X + udelay(10000); + #else +- udelay(50); ++ udelay(200000); + #endif +- resp = mmc_cmd(1, 0x00ff, 0xff00, MMC_CMDAT_BUSY|MMC_CMDAT_R3); ++ resp = mmc_cmd(1, 0x00ff, 0x8000, MMC_CMDAT_BUSY|MMC_CMDAT_R3); + } + + /* try to get card id */ diff --git a/packages/u-boot/u-boot-1.1.4/u-boot-mmcclk-alternate.patch b/packages/u-boot/u-boot-1.1.4/u-boot-mmcclk-alternate.patch new file mode 100644 index 0000000000..5eb8324630 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/u-boot-mmcclk-alternate.patch @@ -0,0 +1,14 @@ +--- a/cpu/pxa/mmc.c 2005-05-31 14:58:43.090949787 -0700 ++++ a/cpu/pxa/mmc.c 2005-04-14 16:02:22.000000000 -0700 +@@ -546,9 +546,10 @@ + int retries, rc = -ENODEV; + uchar *resp; + +-#ifdef CONFIG_LUBBOCK ++#if defined(CONFIG_LUBBOCK) || defined(CONFIG_GUMSTIX) + set_GPIO_mode( GPIO6_MMCCLK_MD ); + set_GPIO_mode( GPIO8_MMCCS0_MD ); ++ set_GPIO_mode( GPIO53_MMCCLK_MD ); + #endif + CKEN |= CKEN12_MMC; /* enable MMC unit clock */ + #if defined(CONFIG_ADSVIX) diff --git a/packages/u-boot/u-boot-1.1.4/u-boot-smc91x-multi.patch b/packages/u-boot/u-boot-1.1.4/u-boot-smc91x-multi.patch new file mode 100644 index 0000000000..3f285e34dc --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/u-boot-smc91x-multi.patch @@ -0,0 +1,125 @@ +diff -u a/drivers/smc91111.c a/drivers/smc91111.c +--- a/drivers/smc91111.c 2005-03-31 15:43:10.000000000 -0800 ++++ a/drivers/smc91111.c 2005-04-13 13:48:41.000000000 -0700 +@@ -155,10 +155,14 @@ + . + .------------------------------------------------------------------ */ + ++#ifndef CONFIG_NET_MULTI + extern int eth_init(bd_t *bd); + extern void eth_halt(void); + extern int eth_rx(void); + extern int eth_send(volatile void *packet, int length); ++#else ++extern int smc_initialize(bd_t *); ++#endif + + + /* +@@ -797,6 +801,56 @@ + } + + ++#ifdef CONFIG_NET_MULTI ++static int smc_multi_init(struct eth_device *, bd_t *); ++static void smc_multi_halt(struct eth_device *); ++static int smc_multi_send(struct eth_device *,volatile void *,int); ++static int smc_multi_recv(struct eth_device *); ++ ++extern int smc_initialize(bd_t *bd) ++{ ++ struct eth_device *dev; ++ ++ dev = (struct eth_device *)malloc(sizeof(struct eth_device)); ++ sprintf(dev->name, "SMC91C1111-%d",0); ++ dev->priv = NULL; ++ dev->iobase = SMC_BASE_ADDRESS; ++ dev->init = smc_multi_init; ++ dev->halt = smc_multi_halt; ++ dev->send = smc_multi_send; ++ dev->recv = smc_multi_recv; ++ eth_register(dev); ++ ++ return 1; // number of cards detected ++} ++ ++static int smc_multi_init(struct eth_device *dev, bd_t *bis) ++{ ++ if(dev->priv == NULL) ++ { ++ smc_open(bis); ++ dev->priv = (void *)1; ++ } ++ return 1; ++} ++ ++static void smc_multi_halt(struct eth_device *dev) ++{ ++ // Not sure when we should actually close... ++ //smc_close(); ++} ++ ++static int smc_multi_send(struct eth_device *dev, volatile void *packet, int length) ++{ ++ return smc_send_packet(packet, length); ++} ++ ++static int smc_multi_recv(struct eth_device *dev) ++{ ++ return smc_rcv(); ++} ++#endif ++ + /* + * Open and Initialize the board + * +@@ -1505,6 +1559,7 @@ + } + #endif + ++#ifndef CONFIG_NET_MULTI + int eth_init(bd_t *bd) { + return (smc_open(bd)); + } +@@ -1520,6 +1575,7 @@ + int eth_send(volatile void *packet, int length) { + return smc_send_packet(packet, length); + } ++#endif //CONFIG_NET_MULTI + + int smc_get_ethaddr (bd_t * bd) + { +--- a/lib_arm/board.c 2005-03-30 16:39:47.000000000 -0800 ++++ a/lib_arm/board.c 2005-03-30 14:26:08.000000000 -0800 +@@ -278,6 +278,11 @@ + /* initialize environment */ + env_relocate (); + ++#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) ++ /* must do after the environment variables are set up */ ++ eth_initialize (NULL); ++#endif ++ + #ifdef CONFIG_VFD + /* must do this after the framebuffer is allocated */ + drv_vfd_init(); +--- a/net/eth.c 2004-12-16 09:49:38.000000000 -0800 ++++ a/net/eth.c 2005-03-30 17:06:49.000000000 -0800 +@@ -53,6 +53,7 @@ + extern int scc_initialize(bd_t*); + extern int skge_initialize(bd_t*); + extern int tsec_initialize(bd_t*, int, char *); ++extern int smc_initialize(bd_t*); + + static struct eth_device *eth_devices, *eth_current; + +@@ -196,6 +197,9 @@ + #if defined(CONFIG_RTL8169) + rtl8169_initialize(bis); + #endif ++#if defined(CONFIG_DRIVER_SMC91111) ++ smc_initialize(bis); ++#endif + + if (!eth_devices) { + puts ("No ethernet found.\n"); diff --git a/packages/u-boot/u-boot-1.1.4/u-boot-zzz-osx.patch b/packages/u-boot/u-boot-1.1.4/u-boot-zzz-osx.patch new file mode 100644 index 0000000000..f9d52c7dfe --- /dev/null +++ b/packages/u-boot/u-boot-1.1.4/u-boot-zzz-osx.patch @@ -0,0 +1,41 @@ +--- u-boot-1.1.1/tools/Makefile Mon Sep 27 03:34:12 2004 ++++ u-boot-1.1.1/tools/Makefile Mon Sep 27 03:34:52 2004 +@@ -70,26 +70,26 @@ + # multiple symbol definitions are treated as errors, hence the + # -multiply_defined suppress option to turn off this error. + # +-ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) +-HOST_CFLAGS = -traditional-cpp -Wall +-HOST_LDFLAGS =-multiply_defined suppress +-HOST_ENVIRO_CFLAGS = -traditional-cpp ++#ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) ++#HOST_CFLAGS = -traditional-cpp -Wall ++#HOST_LDFLAGS =-multiply_defined suppress ++#HOST_ENVIRO_CFLAGS = -traditional-cpp + +-else +-ifeq ($(HOSTOS)-$(HOSTARCH),netbsd-ppc) +-HOST_CFLAGS = -Wall -pedantic +-HOST_LDFLAGS = +-HOST_ENVIRO_CFLAGS = ++#else ++#ifeq ($(HOSTOS)-$(HOSTARCH),netbsd-ppc) ++#HOST_CFLAGS = -Wall -pedantic ++#HOST_LDFLAGS = ++#HOST_ENVIRO_CFLAGS = + + # + # Everyone else + # +-else ++#else + HOST_CFLAGS = -Wall -pedantic + HOST_LDFLAGS = + HOST_ENVIRO_CFLAGS = +-endif +-endif ++#endif ++#endif + + # + # Cygwin needs .exe files :-( diff --git a/packages/u-boot/u-boot-1.1.6/.mtn2git_empty b/packages/u-boot/u-boot-1.1.6/.mtn2git_empty new file mode 100644 index 0000000000..e69de29bb2 diff --git a/packages/u-boot/u-boot-1.1.6/devkit-idp.patch b/packages/u-boot/u-boot-1.1.6/devkit-idp.patch new file mode 100644 index 0000000000..1460c3d1f0 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.6/devkit-idp.patch @@ -0,0 +1,28 @@ +Index: u-boot-1.1.6/board/pxa255_idp/memsetup.S +=================================================================== +--- u-boot-1.1.6.orig/board/pxa255_idp/memsetup.S ++++ u-boot-1.1.6/board/pxa255_idp/memsetup.S +@@ -41,8 +41,8 @@ DRAM_SIZE: .long CFG_DRAM_SIZE + /* + * Memory setup + */ +-.globl memsetup +-memsetup: ++.globl lowlevel_init ++lowlevel_init: + + mov r10, lr + +Index: u-boot-1.1.6/include/configs/pxa255_idp.h +=================================================================== +--- u-boot-1.1.6.orig/include/configs/pxa255_idp.h ++++ u-boot-1.1.6/include/configs/pxa255_idp.h +@@ -41,7 +41,7 @@ + * If we are developing, we might want to start armboot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +-#define CONFIG_INIT_CRITICAL /* undef for developing */ ++#undef CONFIG_INIT_CRITICAL /* undef for developing */ + + /* + * define the following to enable debug blinks. A debug blink function diff --git a/packages/u-boot/u-boot-1.1.6/sarge-uboot.patch b/packages/u-boot/u-boot-1.1.6/sarge-uboot.patch new file mode 100644 index 0000000000..0c0d56f4d1 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.6/sarge-uboot.patch @@ -0,0 +1,3326 @@ +diff -Nurp ../u-boot-1.1.6/arm_config.mk ./arm_config.mk +--- ../u-boot-1.1.6/arm_config.mk 2006-11-02 15:15:01.000000000 +0100 ++++ ./arm_config.mk 2007-04-23 18:07:47.000000000 +0200 +@@ -21,4 +21,6 @@ + # MA 02111-1307 USA + # + ++#PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 -msoft-float ++PLATFORM_CPPFLAGS += -march=armv4t -mtune=arm920t + PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__ +diff -Nurp ../u-boot-1.1.6/board/sarge/config.mk ./board/sarge/config.mk +--- ../u-boot-1.1.6/board/sarge/config.mk 1970-01-01 01:00:00.000000000 +0100 ++++ ./board/sarge/config.mk 2007-03-21 00:31:33.000000000 +0100 +@@ -0,0 +1 @@ ++TEXT_BASE = 0x21F00000 +diff -Nurp ../u-boot-1.1.6/board/sarge/flash.c ./board/sarge/flash.c +--- ../u-boot-1.1.6/board/sarge/flash.c 1970-01-01 01:00:00.000000000 +0100 ++++ ./board/sarge/flash.c 2007-03-09 01:25:41.000000000 +0100 +@@ -0,0 +1,504 @@ ++/* ++ * (C) Copyright 2002 ++ * Lineo, Inc. ++ * Bernhard Kuhn ++ * ++ * (C) Copyright 2002 ++ * Sysgo Real-Time Solutions, GmbH ++ * Alex Zuepke ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++ ++ulong myflush(void); ++ ++ ++/* Flash Organization Structure */ ++typedef struct OrgDef ++{ ++ unsigned int sector_number; ++ unsigned int sector_size; ++} OrgDef; ++ ++ ++/* Flash Organizations */ ++OrgDef OrgAT49BV16x4[] = ++{ ++ { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ ++ { 2, 32*1024 }, /* 2 * 32 kBytes sectors */ ++ { 30, 64*1024 }, /* 30 * 64 kBytes sectors */ ++}; ++ ++OrgDef OrgAT49BV16x4A[] = ++{ ++ { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ ++ { 31, 64*1024 }, /* 31 * 64 kBytes sectors */ ++}; ++ ++OrgDef OrgAT49BV6416[] = ++{ ++ { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ ++ { 127, 64*1024 }, /* 127 * 64 kBytes sectors */ ++}; ++ ++flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; ++ ++/* AT49BV1614A Codes */ ++#define FLASH_CODE1 0xAA ++#define FLASH_CODE2 0x55 ++#define ID_IN_CODE 0x90 ++#define ID_OUT_CODE 0xF0 ++ ++ ++#define CMD_READ_ARRAY 0x00F0 ++#define CMD_UNLOCK1 0x00AA ++#define CMD_UNLOCK2 0x0055 ++#define CMD_ERASE_SETUP 0x0080 ++#define CMD_ERASE_CONFIRM 0x0030 ++#define CMD_PROGRAM 0x00A0 ++#define CMD_UNLOCK_BYPASS 0x0020 ++#define CMD_SECTOR_UNLOCK 0x0070 ++ ++#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00005555<<1))) ++#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00002AAA<<1))) ++ ++#define BIT_ERASE_DONE 0x0080 ++#define BIT_RDY_MASK 0x0080 ++#define BIT_PROGRAM_ERROR 0x0020 ++#define BIT_TIMEOUT 0x80000000 /* our flag */ ++ ++#define READY 1 ++#define ERR 2 ++#define TMO 4 ++ ++/*----------------------------------------------------------------------- ++ */ ++void flash_identification (flash_info_t * info) ++{ ++ volatile u16 manuf_code, device_code, add_device_code; ++ ++ MEM_FLASH_ADDR1 = FLASH_CODE1; ++ MEM_FLASH_ADDR2 = FLASH_CODE2; ++ MEM_FLASH_ADDR1 = ID_IN_CODE; ++ ++ manuf_code = *(volatile u16 *) CFG_FLASH_BASE; ++ device_code = *(volatile u16 *) (CFG_FLASH_BASE + 2); ++ add_device_code = *(volatile u16 *) (CFG_FLASH_BASE + (3 << 1)); ++ ++ MEM_FLASH_ADDR1 = FLASH_CODE1; ++ MEM_FLASH_ADDR2 = FLASH_CODE2; ++ MEM_FLASH_ADDR1 = ID_OUT_CODE; ++ ++ /* Vendor type */ ++ info->flash_id = ATM_MANUFACT & FLASH_VENDMASK; ++ printf ("Atmel: "); ++ ++ if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV1614 & FLASH_TYPEMASK)) { ++ ++ if ((add_device_code & FLASH_TYPEMASK) == ++ (ATM_ID_BV1614A & FLASH_TYPEMASK)) { ++ info->flash_id |= ATM_ID_BV1614A & FLASH_TYPEMASK; ++ printf ("AT49BV1614A (16Mbit)\n"); ++ } else { /* AT49BV1614 Flash */ ++ info->flash_id |= ATM_ID_BV1614 & FLASH_TYPEMASK; ++ printf ("AT49BV1614 (16Mbit)\n"); ++ } ++ ++ } else if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV6416 & FLASH_TYPEMASK)) { ++ info->flash_id |= ATM_ID_BV6416 & FLASH_TYPEMASK; ++ printf ("AT49BV6416 (64Mbit)\n"); ++ } ++} ++ ++ushort flash_number_sector(OrgDef *pOrgDef, unsigned int nb_blocks) ++{ ++ int i, nb_sectors = 0; ++ ++ for (i=0; istart[sector]); ++ ++ MEM_FLASH_ADDR1 = CMD_UNLOCK1; ++ *addr = CMD_SECTOR_UNLOCK; ++} ++ ++ ++ulong flash_init (void) ++{ ++ int i, j, k; ++ unsigned int flash_nb_blocks, sector; ++ unsigned int start_address; ++ OrgDef *pOrgDef; ++ ++ ulong size = 0; ++ ++ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { ++ ulong flashbase = 0; ++ ++ flash_identification (&flash_info[i]); ++ ++ if ((flash_info[i].flash_id & FLASH_TYPEMASK) == ++ (ATM_ID_BV1614 & FLASH_TYPEMASK)) { ++ ++ pOrgDef = OrgAT49BV16x4; ++ flash_nb_blocks = sizeof (OrgAT49BV16x4) / sizeof (OrgDef); ++ } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) == ++ (ATM_ID_BV1614A & FLASH_TYPEMASK)){ /* AT49BV1614A Flash */ ++ ++ pOrgDef = OrgAT49BV16x4A; ++ flash_nb_blocks = sizeof (OrgAT49BV16x4A) / sizeof (OrgDef); ++ } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) == ++ (ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */ ++ ++ pOrgDef = OrgAT49BV6416; ++ flash_nb_blocks = sizeof (OrgAT49BV6416) / sizeof (OrgDef); ++ } else { ++ flash_nb_blocks = 0; ++ pOrgDef = OrgAT49BV16x4; ++ } ++ ++ flash_info[i].sector_count = flash_number_sector(pOrgDef, flash_nb_blocks); ++ memset (flash_info[i].protect, 0, flash_info[i].sector_count); ++ ++ if (i == 0) ++ flashbase = PHYS_FLASH_1; ++ else ++ panic ("configured too many flash banks!\n"); ++ ++ sector = 0; ++ start_address = flashbase; ++ flash_info[i].size = 0; ++ ++ for (j = 0; j < flash_nb_blocks; j++) { ++ for (k = 0; k < pOrgDef[j].sector_number; k++) { ++ flash_info[i].start[sector++] = start_address; ++ start_address += pOrgDef[j].sector_size; ++ flash_info[i].size += pOrgDef[j].sector_size; ++ } ++ } ++ ++ size += flash_info[i].size; ++ ++ if ((flash_info[i].flash_id & FLASH_TYPEMASK) == ++ (ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */ ++ ++ /* Unlock all sectors at reset */ ++ for (j=0; jflash_id & FLASH_VENDMASK) { ++ case (ATM_MANUFACT & FLASH_VENDMASK): ++ printf ("Atmel: "); ++ break; ++ default: ++ printf ("Unknown Vendor "); ++ break; ++ } ++ ++ switch (info->flash_id & FLASH_TYPEMASK) { ++ case (ATM_ID_BV1614 & FLASH_TYPEMASK): ++ printf ("AT49BV1614 (16Mbit)\n"); ++ break; ++ case (ATM_ID_BV1614A & FLASH_TYPEMASK): ++ printf ("AT49BV1614A (16Mbit)\n"); ++ break; ++ case (ATM_ID_BV6416 & FLASH_TYPEMASK): ++ printf ("AT49BV6416 (64Mbit)\n"); ++ break; ++ default: ++ printf ("Unknown Chip Type\n"); ++ return; ++ } ++ ++ printf (" Size: %ld MB in %d Sectors\n", ++ info->size >> 20, info->sector_count); ++ ++ printf (" Sector Start Addresses:"); ++ for (i = 0; i < info->sector_count; i++) { ++ if ((i % 5) == 0) { ++ printf ("\n "); ++ } ++ printf (" %08lX%s", info->start[i], ++ info->protect[i] ? " (RO)" : " "); ++ } ++ printf ("\n"); ++} ++ ++/*----------------------------------------------------------------------- ++ */ ++ ++int flash_erase (flash_info_t * info, int s_first, int s_last) ++{ ++ ulong result; ++ int iflag, cflag, prot, sect; ++ int rc = ERR_OK; ++ int chip1; ++ ++ /* first look for protection bits */ ++ ++ if (info->flash_id == FLASH_UNKNOWN) ++ return ERR_UNKNOWN_FLASH_TYPE; ++ ++ if ((s_first < 0) || (s_first > s_last)) { ++ return ERR_INVAL; ++ } ++ ++ if ((info->flash_id & FLASH_VENDMASK) != ++ (ATM_MANUFACT & FLASH_VENDMASK)) { ++ return ERR_UNKNOWN_FLASH_VENDOR; ++ } ++ ++ prot = 0; ++ for (sect = s_first; sect <= s_last; ++sect) { ++ if (info->protect[sect]) { ++ prot++; ++ } ++ } ++ if (prot) ++ return ERR_PROTECTED; ++ ++ /* ++ * Disable interrupts which might cause a timeout ++ * here. Remember that our exception vectors are ++ * at address 0 in the flash, and we don't want a ++ * (ticker) exception to happen while the flash ++ * chip is in programming mode. ++ */ ++ cflag = icache_status (); ++ icache_disable (); ++ iflag = disable_interrupts (); ++ ++ /* Start erase on unprotected sectors */ ++ for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { ++ printf ("Erasing sector %2d ... ", sect); ++ ++ /* arm simple, non interrupt dependent timer */ ++ reset_timer_masked (); ++ ++ if (info->protect[sect] == 0) { /* not protected */ ++ volatile u16 *addr = (volatile u16 *) (info->start[sect]); ++ ++ MEM_FLASH_ADDR1 = CMD_UNLOCK1; ++ MEM_FLASH_ADDR2 = CMD_UNLOCK2; ++ MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; ++ ++ MEM_FLASH_ADDR1 = CMD_UNLOCK1; ++ MEM_FLASH_ADDR2 = CMD_UNLOCK2; ++ *addr = CMD_ERASE_CONFIRM; ++ ++ /* wait until flash is ready */ ++ chip1 = 0; ++ ++ do { ++ result = *addr; ++ ++ /* check timeout */ ++ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { ++ MEM_FLASH_ADDR1 = CMD_READ_ARRAY; ++ chip1 = TMO; ++ break; ++ } ++ ++ if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) ++ chip1 = READY; ++ ++ } while (!chip1); ++ ++ MEM_FLASH_ADDR1 = CMD_READ_ARRAY; ++ ++ if (chip1 == ERR) { ++ rc = ERR_PROG_ERROR; ++ goto outahere; ++ } ++ if (chip1 == TMO) { ++ rc = ERR_TIMOUT; ++ goto outahere; ++ } ++ ++ printf ("ok.\n"); ++ } else { /* it was protected */ ++ printf ("protected!\n"); ++ } ++ } ++ ++ if (ctrlc ()) ++ printf ("User Interrupt!\n"); ++ ++outahere: ++ /* allow flash to settle - wait 10 ms */ ++ udelay_masked (10000); ++ ++ if (iflag) ++ enable_interrupts (); ++ ++ if (cflag) ++ icache_enable (); ++ ++ return rc; ++} ++ ++/*----------------------------------------------------------------------- ++ * Copy memory to flash ++ */ ++ ++volatile static int write_word (flash_info_t * info, ulong dest, ++ ulong data) ++{ ++ volatile u16 *addr = (volatile u16 *) dest; ++ ulong result; ++ int rc = ERR_OK; ++ int cflag, iflag; ++ int chip1; ++ ++ /* ++ * Check if Flash is (sufficiently) erased ++ */ ++ result = *addr; ++ if ((result & data) != data) ++ return ERR_NOT_ERASED; ++ ++ ++ /* ++ * Disable interrupts which might cause a timeout ++ * here. Remember that our exception vectors are ++ * at address 0 in the flash, and we don't want a ++ * (ticker) exception to happen while the flash ++ * chip is in programming mode. ++ */ ++ cflag = icache_status (); ++ icache_disable (); ++ iflag = disable_interrupts (); ++ ++ MEM_FLASH_ADDR1 = CMD_UNLOCK1; ++ MEM_FLASH_ADDR2 = CMD_UNLOCK2; ++ MEM_FLASH_ADDR1 = CMD_PROGRAM; ++ *addr = data; ++ ++ /* arm simple, non interrupt dependent timer */ ++ reset_timer_masked (); ++ ++ /* wait until flash is ready */ ++ chip1 = 0; ++ do { ++ result = *addr; ++ ++ /* check timeout */ ++ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { ++ chip1 = ERR | TMO; ++ break; ++ } ++ if (!chip1 && ((result & 0x80) == (data & 0x80))) ++ chip1 = READY; ++ ++ } while (!chip1); ++ ++ *addr = CMD_READ_ARRAY; ++ ++ if (chip1 == ERR || *addr != data) ++ rc = ERR_PROG_ERROR; ++ ++ if (iflag) ++ enable_interrupts (); ++ ++ if (cflag) ++ icache_enable (); ++ ++ return rc; ++} ++ ++/*----------------------------------------------------------------------- ++ * Copy memory to flash. ++ */ ++ ++int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) ++{ ++ ulong wp, data; ++ int rc; ++ ++ if (addr & 1) { ++ printf ("unaligned destination not supported\n"); ++ return ERR_ALIGN; ++ }; ++ ++ if ((int) src & 1) { ++ printf ("unaligned source not supported\n"); ++ return ERR_ALIGN; ++ }; ++ ++ wp = addr; ++ ++ while (cnt >= 2) { ++ data = *((volatile u16 *) src); ++ if ((rc = write_word (info, wp, data)) != 0) { ++ return (rc); ++ } ++ src += 2; ++ wp += 2; ++ cnt -= 2; ++ } ++ ++ if (cnt == 1) { ++ data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) << ++ 8); ++ if ((rc = write_word (info, wp, data)) != 0) { ++ return (rc); ++ } ++ src += 1; ++ wp += 1; ++ cnt -= 1; ++ }; ++ ++ return ERR_OK; ++} +diff -Nurp ../u-boot-1.1.6/board/sarge/Makefile ./board/sarge/Makefile +--- ../u-boot-1.1.6/board/sarge/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ ./board/sarge/Makefile 2007-03-14 01:05:48.000000000 +0100 +@@ -0,0 +1,46 @@ ++# ++# (C) Copyright 2007 ++# Grzegorz Rajtar, mcgregor@blackmesaeast.com.pl. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = lib$(BOARD).a ++ ++OBJS := sarge_board.o at45.o flash.o ++ ++$(LIB): $(OBJS) $(SOBJS) ++ $(AR) crv $@ $(OBJS) $(SOBJS) ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak .depend ++ ++######################################################################### ++ ++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) ++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ ++ ++-include .depend ++ ++######################################################################### +diff -Nurp ../u-boot-1.1.6/board/sarge/sarge_board.c ./board/sarge/sarge_board.c +--- ../u-boot-1.1.6/board/sarge/sarge_board.c 1970-01-01 01:00:00.000000000 +0100 ++++ ./board/sarge/sarge_board.c 2007-05-11 23:45:25.000000000 +0200 +@@ -0,0 +1,363 @@ ++/* ++ * (C) Copyright 2007 ++ * Grzegorz Rajtar ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++/* ------------------------------------------------------------------------- */ ++/* ++ * Miscelaneous platform dependent initialisations ++ */ ++ ++void lowlevel_init(void) ++{ ++} ++/* ------------------------------------------------------------------------- */ ++ ++void cs_init(int enable) ++{ ++ unsigned long flag = ++ AT91C_PIO_PA0 | AT91C_PIO_PA1 | AT91C_PIO_PA2 | ++ AT91C_PIO_PA4 | AT91C_PIO_PA5 | AT91C_PIO_PA6; ++ //MISO, MOSI, SPCK, NPCS1, NPCS2, NPCS3; ++ if (enable) ++ { ++ ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_PDR = flag; ++ ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_ASR = flag; ++ } ++ else ++ ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_PER = flag; ++} ++ ++void mac_init(int enable) ++{ ++ unsigned long flag = ++ // ETXCK, ETXEN, ETX0, ETX1, EXRS, ++ // ERX0, ERX1, ERXER, EMDC, EMDIO ++ AT91C_PIO_PA7 | AT91C_PIO_PA8 | AT91C_PIO_PA9 | AT91C_PIO_PA10 | ++ AT91C_PIO_PA11 | AT91C_PIO_PA12 | AT91C_PIO_PA13 | AT91C_PIO_PA14 | ++ AT91C_PIO_PA13 | AT91C_PIO_PA16; ++ if (enable) ++ { ++ ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_PDR = flag; ++ ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_ASR = flag; ++ } ++ else ++ ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_PER = flag; ++ ++ //ERXCK, ECOL, ERXDV, ERX3, ERX2, ETXER, ETX3, ETX2 ++ flag = AT91C_PIO_PB19 | AT91C_PIO_PB18 | AT91C_PIO_PB17 | AT91C_PIO_PB16 | ++ AT91C_PIO_PB15 | AT91C_PIO_PB14 | AT91C_PIO_PB13 | AT91C_PIO_PB12; ++ ++ if (enable) ++ { ++ ((AT91PS_PIO) AT91C_BASE_PIOB)->PIO_PDR = flag; ++ ((AT91PS_PIO) AT91C_BASE_PIOB)->PIO_BSR = flag; ++ } ++ else ++ ((AT91PS_PIO) AT91C_BASE_PIOB)->PIO_PER = flag; ++ // EMDINT - ++ flag = AT91C_PIO_PB1; ++ if (enable) ++ { ++ ((AT91PS_PIO) AT91C_BASE_PIOB)->PIO_PER = flag; ++ ((AT91PS_PIO) AT91C_BASE_PIOB)->PIO_IER = flag; ++ } ++ else ++ { ++ ((AT91PS_PIO) AT91C_BASE_PIOB)->PIO_PDR = flag; ++ ((AT91PS_PIO) AT91C_BASE_PIOB)->PIO_IDR = flag; ++ } ++} ++ ++void peripheral_init(int enable) ++{ ++ unsigned long flag = ++ // A - TXD0, RXD0, SCK0, RXD2, TXD2, I2C_SCL. I2C_SDA ++ AT91C_PIO_PA17 | AT91C_PIO_PA18 | AT91C_PIO_PA19 | ++ AT91C_PIO_PA20 | AT91C_PIO_PA21 | AT91C_PIO_PA22 | ++ AT91C_PIO_PA23 | AT91C_PA25_TWD | AT91C_PA26_TWCK; ++ ++ if (enable) ++ { ++ ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_PDR = flag; ++ ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_ASR = flag; ++ } ++ else ++ ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_PER = flag; ++ ++ //B - PCK1 ++ flag = AT91C_PIO_PA24; ++ ++ if (enable) ++ { ++ ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_PDR = flag; ++ ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_BSR = flag; ++ } ++ else ++ ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_PER = flag; ++ ++ ++ // PA20, PA21 - I/O ++ flag = AT91C_PIO_PA20 | AT91C_PIO_PA21; ++ if (enable) ++ ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_PER = flag; ++ else ++ ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_PDR = flag; ++ ++ // A - PCK0, RXD1, TXD1,RF1,RK1, RD1, TD1, TK1, TF1 ++ flag = AT91C_PIO_PB27 | AT91C_PIO_PB21 | AT91C_PIO_PB20 | ++ AT91C_PIO_PB11 | AT91C_PIO_PB10 | AT91C_PIO_PB9 | ++ AT91C_PIO_PB8 | AT91C_PIO_PB7 | AT91C_PIO_PB6; ++ if (enable) ++ { ++ ((AT91PS_PIO) AT91C_BASE_PIOB)->PIO_PDR = flag; ++ ((AT91PS_PIO) AT91C_BASE_PIOB)->PIO_ASR = flag; ++ } ++ else ++ ((AT91PS_PIO) AT91C_BASE_PIOB)->PIO_PER = flag; ++ // I/O PB26 - PB22 ++ flag = AT91C_PIO_PB22 | AT91C_PIO_PB23 | AT91C_PIO_PB24 | ++ AT91C_PIO_PB25 | AT91C_PIO_PB26; ++ if (enable) ++ ((AT91PS_PIO) AT91C_BASE_PIOB)->PIO_PER = flag; ++ else ++ ((AT91PS_PIO) AT91C_BASE_PIOB)->PIO_PDR = flag; ++} ++ ++void mmc_init(int enable) ++{ ++ // MCCK, MCCDA, MCDA0 ++ unsigned long flag = ++ AT91C_PIO_PA27 | AT91C_PIO_PA28 | AT91C_PIO_PA29; ++ if (enable) ++ { ++ ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_PDR = flag; ++ ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_ASR = flag; ++ } ++ else ++ ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_PER = flag; ++ // MCDA3, MCDA2, MCDA1 ++ flag = AT91C_PIO_PB5 | AT91C_PIO_PB4 | AT91C_PIO_PB3; ++ if (enable) ++ { ++ ((AT91PS_PIO) AT91C_BASE_PIOB)->PIO_PDR = flag; ++ ((AT91PS_PIO) AT91C_BASE_PIOB)->PIO_BSR = flag; ++ } ++ else ++ ((AT91PS_PIO) AT91C_BASE_PIOB)->PIO_PER = flag; ++ //MCWP, MCCD ++ flag = AT91C_PIO_PB2 | AT91C_PIO_PB0; ++ ++ if (enable) ++ { ++ ((AT91PS_PIO) AT91C_BASE_PIOB)->PIO_PER = flag; ++ ((AT91PS_PIO) AT91C_BASE_PIOB)->PIO_IER = AT91C_PIO_PB0; ++ } ++ else ++ { ++ ((AT91PS_PIO) AT91C_BASE_PIOB)->PIO_PDR = flag; ++ ((AT91PS_PIO) AT91C_BASE_PIOB)->PIO_IDR = AT91C_PIO_PB0; ++ } ++} ++ ++void irq_init(int enable) ++{ ++ // IRQ, FIQ ++ unsigned long flag = ++ AT91C_PIO_PB29 | AT91C_PIO_PB28; ++ if (enable) ++ { ++ ((AT91PS_PIO) AT91C_BASE_PIOB)->PIO_PDR = flag; ++ ((AT91PS_PIO) AT91C_BASE_PIOB)->PIO_ASR = flag; ++ } ++ else ++ ((AT91PS_PIO) AT91C_BASE_PIOB)->PIO_PER = flag; ++} ++ ++int board_init (void) ++{ ++ DECLARE_GLOBAL_DATA_PTR; ++ long flag; ++ ++ /* Enable Ctrlc */ ++ console_init_f (); ++ ++ /* sarge board specific */ ++ /* ++ cs_init(1); ++ mac_init(1); ++ peripheral_init(1); ++ mmc_init(1); ++ irq_init(1); ++ */ ++ ++ /* PIOB and PIOA clock enabling */ ++ ++ *AT91C_PMC_PCER = 1 << AT91C_ID_PIOA; ++ *AT91C_PMC_PCER = 1 << AT91C_ID_PIOB; ++ ++ ++ //miiphy_init(); ++ /* memory and cpu-speed are setup before relocation */ ++ /* so we do _nothing_ here */ ++ ++ /* Correct IRDA resistor problem */ ++ /* Set PA23_TXD in Output */ ++ ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_OER = AT91C_PA23_TXD2; ++ ++ /* arch number of AT91RM9200-Board */ ++ gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200; ++ ++ /* adress of boot parameters */ ++ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; ++ ++ return 0; ++} ++ ++int dram_init (void) ++{ ++ DECLARE_GLOBAL_DATA_PTR; ++ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM; ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; ++ return 0; ++} ++ ++ ++int sarge_before_linux(void) ++{ ++ DECLARE_GLOBAL_DATA_PTR; ++ AT91PS_EMAC mac = AT91C_BASE_EMAC; ++ char* isolate_str = getenv("phy_isolate"); ++ if (strlen(isolate_str) && strcmp(isolate_str, "yes") == 0) ++ { ++ printf("\nisolating PHY\n"); ++ eth_init(gd->bd); ++ ste100p_DisableInterrupts(mac); ++ ste100p_Isolate(mac); ++ } ++} ++ ++#ifdef CONFIG_DRIVER_ETHER ++#if (CONFIG_COMMANDS & CFG_CMD_NET) ++ ++/* ++ * Name: ++ * at91rm9200_GetPhyInterface ++ * Description: ++ * Initialise the interface functions to the PHY ++ * Arguments: ++ * None ++ * Return value: ++ * None ++ */ ++void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) ++{ ++#ifdef DM9161_ETH ++ p_phyops->Init = dm9161_InitPhy; ++ p_phyops->IsPhyConnected = dm9161_IsPhyConnected; ++ p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed; ++ p_phyops->AutoNegotiate = dm9161_AutoNegotiate; ++#endif ++ ++#ifdef RTL8201BL_ETH ++ p_phyops->Init = rtl8201bl_InitPhy; ++ p_phyops->IsPhyConnected = rtl8201bl_IsPhyConnected; ++ p_phyops->GetLinkSpeed = rtl8201bl_GetLinkSpeed; ++ p_phyops->AutoNegotiate = rtl8201bl_AutoNegotiate; ++ ++#endif ++#ifdef STE100P_ETH ++ p_phyops->Init = ste100p_InitPhy; ++ p_phyops->IsPhyConnected = ste100p_IsPhyConnected; ++ p_phyops->GetLinkSpeed = ste100p_GetLinkSpeed; ++ p_phyops->AutoNegotiate = ste100p_AutoNegotiate; ++ p_phyops->Isolate = ste100p_Isolate; ++ ++#endif ++ ++} ++ ++#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ ++#endif /* CONFIG_DRIVER_ETHER */ ++ ++/* ++ * Disk On Chip (NAND) Millenium initialization. ++ * The NAND lives in the CS2* space ++ */ ++#if (CONFIG_COMMANDS & CFG_CMD_NAND) ++extern ulong nand_probe (ulong physadr); ++ ++#define AT91_SMARTMEDIA_BASE 0x40000000 /* physical address to access memory on NCS3 */ ++void nand_init (void) ++{ ++ /* Setup Smart Media, fitst enable the address range of CS3 */ ++ *AT91C_EBI_CSA |= AT91C_EBI_CS3A_SMC_SmartMedia; ++ /* set the bus interface characteristics based on ++ tDS Data Set up Time 30 - ns ++ tDH Data Hold Time 20 - ns ++ tALS ALE Set up Time 20 - ns ++ 16ns at 60 MHz ~= 3 */ ++/*memory mapping structures */ ++#define SM_ID_RWH (5 << 28) ++#define SM_RWH (1 << 28) ++#define SM_RWS (0 << 24) ++#define SM_TDF (1 << 8) ++#define SM_NWS (3) ++ AT91C_BASE_SMC2->SMC2_CSR[3] = (SM_RWH | SM_RWS | ++ AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_DBW_8 | ++ SM_TDF | AT91C_SMC2_WSEN | SM_NWS); ++ ++ /* enable the SMOE line PC0=SMCE, A21=CLE, A22=ALE */ ++ *AT91C_PIOC_ASR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE | ++ AT91C_PC3_BFBAA_SMWE; ++ *AT91C_PIOC_PDR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE | ++ AT91C_PC3_BFBAA_SMWE; ++ ++ /* Configure PC2 as input (signal READY of the SmartMedia) */ ++ *AT91C_PIOC_PER = AT91C_PC2_BFAVD; /* enable direct output enable */ ++ *AT91C_PIOC_ODR = AT91C_PC2_BFAVD; /* disable output */ ++ ++ /* Configure PB1 as input (signal Card Detect of the SmartMedia) */ ++ *AT91C_PIOB_PER = AT91C_PIO_PB1; /* enable direct output enable */ ++ *AT91C_PIOB_ODR = AT91C_PIO_PB1; /* disable output */ ++ ++ /* PIOB and PIOC clock enabling */ ++ *AT91C_PMC_PCER = 1 << AT91C_ID_PIOB; ++ *AT91C_PMC_PCER = 1 << AT91C_ID_PIOC; ++ ++ if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1) ++ printf (" No SmartMedia card inserted\n"); ++#ifdef DEBUG ++ printf (" SmartMedia card inserted\n"); ++ ++ printf ("Probing at 0x%.8x\n", AT91_SMARTMEDIA_BASE); ++#endif ++ printf ("%4lu MB\n", nand_probe(AT91_SMARTMEDIA_BASE) >> 20); ++} ++#endif +diff -Nurp ../u-boot-1.1.6/board/sarge/u-boot.lds ./board/sarge/u-boot.lds +--- ../u-boot-1.1.6/board/sarge/u-boot.lds 1970-01-01 01:00:00.000000000 +0100 ++++ ./board/sarge/u-boot.lds 2007-03-09 01:25:41.000000000 +0100 +@@ -0,0 +1,57 @@ ++/* ++ * (C) Copyright 2002 ++ * Gary Jennejohn, DENX Software Engineering, ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ ++OUTPUT_ARCH(arm) ++ENTRY(_start) ++SECTIONS ++{ ++ . = 0x00000000; ++ ++ . = ALIGN(4); ++ .text : ++ { ++ cpu/arm920t/start.o (.text) ++ *(.text) ++ } ++ ++ . = ALIGN(4); ++ .rodata : { *(.rodata) } ++ ++ . = ALIGN(4); ++ .data : { *(.data) } ++ ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ . = .; ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss : { *(.bss) } ++ _end = .; ++} +diff -Nurp ../u-boot-1.1.6/common/cmd_bootm.c ./common/cmd_bootm.c +--- ../u-boot-1.1.6/common/cmd_bootm.c 2006-11-02 15:15:01.000000000 +0100 ++++ ./common/cmd_bootm.c 2007-03-27 02:55:11.000000000 +0200 +@@ -79,7 +79,10 @@ DECLARE_GLOBAL_DATA_PTR; + # define CHUNKSZ (64 * 1024) + #endif + +-int gunzip (void *, int, unsigned char *, unsigned long *); ++ ++//int gunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp); ++int gunzip(unsigned char *inbuf, unsigned long *insize, unsigned char *outbuf, unsigned long *outsize); ++ + + static void *zalloc(void *, unsigned, unsigned); + static void zfree(void *, void *, unsigned); +@@ -94,6 +97,12 @@ extern flash_info_t flash_info[]; /* inf + static int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + #endif + ++ ++#ifdef CONFIG_HAS_DATAFLASH ++extern int AT91F_DataflashInit(void); ++#endif ++ ++ + static void print_type (image_header_t *hdr); + + #ifdef __I386__ +@@ -176,8 +185,9 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag + + /* Copy header so we can blank CRC field for re-calculation */ + #ifdef CONFIG_HAS_DATAFLASH ++ AT91F_DataflashInit(); + if (addr_dataflash(addr)){ +- read_dataflash(addr, sizeof(image_header_t), (char *)&header); ++ read_dataflash(addr, sizeof(image_header_t), (char *)&header); + } else + #endif + memmove (&header, (char *)addr, sizeof(image_header_t)); +@@ -194,7 +204,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag + } else + #endif /* __I386__ */ + { +- puts ("Bad Magic Number\n"); ++ printf ("Bad Magic Number, got 0x%x, should be: 0x%x\n", hdr->ih_magic, IH_MAGIC); + SHOW_BOOT_PROGRESS (-1); + return 1; + } +@@ -216,9 +226,14 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag + + #ifdef CONFIG_HAS_DATAFLASH + if (addr_dataflash(addr)){ +- len = ntohl(hdr->ih_size) + sizeof(image_header_t); +- read_dataflash(addr, len, (char *)CFG_LOAD_ADDR); +- addr = CFG_LOAD_ADDR; ++ len = ntohl(hdr->ih_size) + sizeof(image_header_t); ++ char* env_loadaddr = getenv("loadaddr"); ++ unsigned long load_addr = CFG_LOAD_ADDR; ++ if (env_loadaddr) ++ load_addr = simple_strtoul(env_loadaddr, NULL, 16); ++ read_dataflash(addr, len, (char *)load_addr); ++ addr = load_addr; ++ + } + #endif + +@@ -227,6 +242,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag + print_image_hdr ((image_header_t *)addr); + + data = addr + sizeof(image_header_t); ++ + len = ntohl(hdr->ih_size); + + if (verify) { +@@ -343,12 +359,24 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag + break; + case IH_COMP_GZIP: + printf (" Uncompressing %s ... ", name); +- if (gunzip ((void *)ntohl(hdr->ih_load), unc_len, +- (uchar *)data, &len) != 0) { +- puts ("GUNZIP ERROR - must RESET board to recover\n"); ++ int res; ++ if ((res = gunzip ((uchar *)data, &len, (void *)ntohl(hdr->ih_load), &unc_len ++ )) != 0) { ++ printf ("GUNZIP ERROR (code %d)- must RESET board to recover\n", res); + SHOW_BOOT_PROGRESS (-6); ++ + do_reset (cmdtp, flag, argc, argv); + } ++ //addr = ntohl(hdr->ih_load); ++ //old gunzip switched parameters list ++ ++/* if ((res = gunzip ((void *)ntohl(hdr->ih_load), unc_len, ++ (uchar *)data, &len)) != 0) { ++ printf ("GUNZIP ERROR (code %d)- must RESET board to recover\n", res); ++ SHOW_BOOT_PROGRESS (-6); ++ do_reset (cmdtp, flag, argc, argv); ++ } */ ++ + break; + #ifdef CONFIG_BZIP2 + case IH_COMP_BZIP2: +@@ -413,7 +441,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag + default: /* handled by (original) Linux case */ + case IH_OS_LINUX: + #ifdef CONFIG_SILENT_CONSOLE +- fixup_silent_linux(); ++// fixup_silent_linux(); + #endif + do_bootm_linux (cmdtp, flag, argc, argv, + addr, len_ptr, verify); +@@ -1429,12 +1457,13 @@ static void zfree(void *x, void *addr, u + + #define DEFLATED 8 + ++/* + int gunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp) + { + z_stream s; + int r, i, flags; + +- /* skip header */ ++ // skip header + i = 10; + flags = src[3]; + if (src[2] != DEFLATED || (flags & RESERVED) != 0) { +@@ -1462,9 +1491,10 @@ int gunzip(void *dst, int dstlen, unsign + s.outcb = (cb_func)WATCHDOG_RESET; + #else + s.outcb = Z_NULL; +-#endif /* CONFIG_HW_WATCHDOG */ +- ++#endif // CONFIG_HW_WATCHDOG // ++ + r = inflateInit2(&s, -MAX_WBITS); ++ // gunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp) + if (r != Z_OK) { + printf ("Error: inflateInit2() returned %d\n", r); + return (-1); +@@ -1480,9 +1510,8 @@ int gunzip(void *dst, int dstlen, unsign + } + *lenp = s.next_out - (unsigned char *) dst; + inflateEnd(&s); +- + return (0); +-} ++}*/ + + #ifdef CONFIG_BZIP2 + void bz_internal_error(int errcode) +diff -Nurp ../u-boot-1.1.6/cpu/arm920t/at91rm9200/Makefile ./cpu/arm920t/at91rm9200/Makefile +--- ../u-boot-1.1.6/cpu/arm920t/at91rm9200/Makefile 2006-11-02 15:15:01.000000000 +0100 ++++ ./cpu/arm920t/at91rm9200/Makefile 2007-05-13 20:19:07.000000000 +0200 +@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk + LIB = $(obj)lib$(SOC).a + + COBJS = bcm5221.o dm9161.o ether.o i2c.o interrupts.o \ +- lxt972.o serial.o usb_ohci.o ++ lxt972.o serial.o usb_ohci.o ste100p.o + SOBJS = lowlevel_init.o + + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +diff -Nurp ../u-boot-1.1.6/cpu/arm920t/at91rm9200/ste100p.c ./cpu/arm920t/at91rm9200/ste100p.c +--- ../u-boot-1.1.6/cpu/arm920t/at91rm9200/ste100p.c 1970-01-01 01:00:00.000000000 +0100 ++++ ./cpu/arm920t/at91rm9200/ste100p.c 2007-05-10 02:02:34.000000000 +0200 +@@ -0,0 +1,517 @@ ++/* ++ * (C) Copyright 2007 ++ * Author : Grzegorz Rajtar (McGregor) (mcgregor@blackmesaeast.com.pl) ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++ ++#ifdef CONFIG_DRIVER_ETHER ++ ++#if (CONFIG_COMMANDS & CFG_CMD_NET) ++ ++void PhyReset(AT91PS_EMAC p_mac) ++{ ++ static long init_wait = 0; ++ unsigned short IntValue; ++ unsigned Status; ++ ++#ifdef DEBUG_ETHER ++ printf("ste100p PhyReset \n"); ++#endif ++ at91rm9200_EmacEnableMDIO (p_mac); ++ ++ ++ // first software reset the STE100P ++ at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &IntValue); ++ udelay(1000); ++ IntValue |= STE100P_XCR_RESET; ++ ++ at91rm9200_EmacWritePhy (p_mac, STE100P_XCR_REG, &IntValue); ++ udelay(10000); ++ ++ while (1) ++ { ++ at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &IntValue); ++ if ((IntValue & STE100P_XCR_RESET) != STE100P_XCR_RESET) ++ break; ++ udelay(1000); ++ } ++ ++ ++ IntValue = STE100P_ANA_FC | STE100P_ANA_TXF | STE100P_ANA_TXH | ++ STE100P_ANA_10F | STE100P_ANA_10H; ++ ++ ++ at91rm9200_EmacWritePhy (p_mac, STE100P_ANA_REG, &IntValue); ++ ++ //default configuration ++#ifdef CONFIG_STE100P_OVERRIDE_HARDWARE ++ IntValue = STE100P_100CTR_ENDCR | STE100P_100CTR_ENRZI | STE100P_100CTR_EN4B5B; ++ IntValue &= ~(STE100P_100CTR_DISRER); ++ IntValue &= ~(STE100P_100CTR_ISOTX); ++ IntValue &= ~(STE100P_100CTR_DISMLT); ++ IntValue &= ~(STE100P_100CTR_DISCRM); ++ ++ at91rm9200_EmacWritePhy (p_mac, STE100P_100CTR_REG, &IntValue); ++ ++#endif //CONFIG_STE100P_OVERRIDE_HARDWARE ++ ++ /* Disable PHY Interrupts */ ++ ++ at91rm9200_EmacReadPhy (p_mac, STE100P_XIE_REG, &IntValue); ++ udelay(10000); ++ /* disable all interrypts from SE100P */ ++ ++ IntValue &= ~(STE100P_XIE_ANCE | STE100P_XIE_RFE | STE100P_XIE_LDE | ++ STE100P_XIE_ANAE | STE100P_XIE_PDFE | STE100P_XIE_ANPE | STE100P_XIE_REFE); ++ ++ at91rm9200_EmacWritePhy (p_mac, STE100P_XIE_REG, &IntValue); ++ udelay(10000); ++ ++ at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &IntValue); ++ ++ IntValue |= STE100P_XCR_AN | STE100P_XCR_RSTRT_AN; ++ at91rm9200_EmacWritePhy (p_mac, STE100P_XCR_REG, &IntValue); ++ ++ at91rm9200_EmacDisableMDIO (p_mac); ++} ++ ++/* ++ * Name: ++ * ste100p_Isolate ++ * Description: ++ * Isolates PHY ++ * Arguments: ++ * p_mac - pointer to AT91S_EMAC struct ++ * Return value: ++ * TRUE - if id isolated successfuly ++ * FALSE- if error ++ */ ++ ++unsigned int ste100p_Isolate (AT91PS_EMAC p_mac) ++{ ++ unsigned int result = FALSE; ++ unsigned short IntValue; ++ ++ at91rm9200_EmacEnableMDIO (p_mac); ++ udelay(10000); ++ at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &IntValue); ++ ++ IntValue |= STE100P_XCR_ISOLATE ;//| STE100P_XCR_PWRDN; ++ //IntValue &= ~STE100P_XCR_RESET; ++ //IntValue &= ~STE100P_XCR_AN; ++ ++ result = at91rm9200_EmacWritePhy (p_mac, STE100P_XCR_REG, &IntValue); ++ udelay(10000); ++ //Isolate is latch so we need to read once more the register ++ at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &IntValue); ++ at91rm9200_EmacDisableMDIO (p_mac); ++ ++#ifdef DEBUG_ETHER ++ printf("ste100p_Isolate [%d]\n", result); ++#endif ++ return result; ++} ++ ++ ++/* ++ * Name: ++ * ste100p_IsPhyConnected ++ * Description: ++ * Reads the 2 PHY ID registers ++ * Arguments: ++ * p_mac - pointer to AT91S_EMAC struct ++ * Return value: ++ * TRUE - if id read successfully ++ * FALSE- if error ++ */ ++unsigned int ste100p_IsPhyConnected (AT91PS_EMAC p_mac) ++{ ++ unsigned short Id1, Id2; ++ unsigned int result = FALSE; ++ ++ at91rm9200_EmacEnableMDIO (p_mac); ++ udelay(10000); ++ do ++ { ++ Id1 = Id2 = 0; ++ udelay(10000); ++ at91rm9200_EmacReadPhy (p_mac, STE100P_PID1_REG, &Id1); ++ ++ udelay(10000); ++ at91rm9200_EmacReadPhy (p_mac, STE100P_PID2_REG, &Id2); ++ ++ Id2 = (Id2 & STE100P_PID2_PHYID_MASK) >> 6; ++ ++ if ((Id1 == STE100P_PID1_PHYID_VAL) && (Id2 == STE100P_PID2_PHYID_VAL)) ++ result = TRUE; ++ } while (!result); ++ ++ at91rm9200_EmacDisableMDIO (p_mac); ++#ifdef DEBUG_ETHER ++ printf ("ste100p id1[0x%02x] id2[0x%02x]\r\n", Id1, Id2); ++#endif ++ return result; ++} ++ ++/* ++ * Name: ++ * ste100p_GetLinkSpeed ++ * Description: ++ * Link parallel detection status of MAC is checked and set in the ++ * MAC configuration registers ++ * Arguments: ++ * p_mac - pointer to MAC ++ * Return value: ++ * TRUE - if link status set succesfully ++ * FALSE - if link status not set ++ */ ++UCHAR ste100p_GetLinkSpeed (AT91PS_EMAC p_mac) ++{ ++ unsigned short stat; ++ int result = 0; ++ ++ result = at91rm9200_EmacReadPhy (p_mac, STE100P_XSR_REG, &stat); ++ ++ if (!result) ++ return FALSE; ++ ++ if (!(stat & STE100P_XSR_LINK)) /* link status up? */ ++ { //last link failure is latched so reread STE100P_XSR_REG for new value ++ result = at91rm9200_EmacReadPhy (p_mac, STE100P_XSR_REG, &stat); ++ if (!result || !(stat & STE100P_XSR_LINK)) ++ return FALSE; ++ } ++ ++ if (stat & STE100P_XSR_100TX_FULL) { ++ /*set Emac for 100BaseTX and Full Duplex */ ++ p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; ++ return TRUE; ++ } ++ ++ if (stat & STE100P_XSR_100TX) { ++ /*set Emac for 100BaseTX and Half Duplex */ ++ p_mac->EMAC_CFG = (p_mac->EMAC_CFG & ++ ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) ++ | AT91C_EMAC_SPD; ++ return TRUE; ++ } ++ ++ if (stat & STE100P_XSR_10T_FULL) { ++ /*set MII for 10BaseT and Full Duplex */ ++ p_mac->EMAC_CFG = (p_mac->EMAC_CFG & ++ ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) ++ | AT91C_EMAC_FD; ++ return TRUE; ++ } ++ ++ if (stat & STE100P_XSR_10T) { ++ /*set MII for 10BaseT and Half Duplex */ ++ p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD); ++ return TRUE; ++ } ++ ++ return FALSE; ++} ++ ++ ++/* ++ * Name: ++ * ste100p_Deisolate ++ * Description: ++ * deisolates PHY ++ * Arguments: ++ * p_mac - pointer to struct AT91S_EMAC ++ */ ++ ++void ste100p_Deisolate (AT91PS_EMAC p_mac) ++{ ++ unsigned short IntValue; ++ ++ IntValue = STE100P_XCR_SPEED | STE100P_XCR_AN | ++ STE100P_XCR_COLLEN; ++ ++ at91rm9200_EmacWritePhy (p_mac, STE100P_XCR_REG, &IntValue); ++ ++ udelay(10000); ++ IntValue = STE100P_100CTR_EN4B5B | STE100P_100CTR_ENRZI | ++ STE100P_100CTR_ENDCR; ++ ++ at91rm9200_EmacWritePhy (p_mac, STE100P_100CTR_REG, &IntValue); ++ udelay(10000); ++ ++ ++ if ((IntValue & STE100P_XCR_ISOLATE) == STE100P_XCR_ISOLATE) ++ { ++ IntValue &= ~STE100P_XCR_ISOLATE; ++ at91rm9200_EmacWritePhy (p_mac, STE100P_XCR_REG, &IntValue); ++ udelay(10000); ++ //isolate is latch so read once more the register ++ at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &IntValue); ++ udelay(10000); ++ } ++} ++ ++/* ++ * Name: ++ * ste100p_WaitForLink ++ * Description: ++ * waits for link with timeout ++ * Arguments: ++ * p_mac - pointer to struct AT91S_EMAC ++ * timeout - timeout in miliseconds ++ */ ++ ++UCHAR ste100p_WaitForLink (AT91PS_EMAC p_mac, unsigned long timeout) ++{ ++ unsigned long loop ; ++ unsigned short IntValue; ++ ++ loop = 0; ++ do ++ { ++ at91rm9200_EmacReadPhy (p_mac, STE100P_XSR_REG, &IntValue); ++ if (IntValue & STE100P_XSR_LINK) ++ return TRUE; ++ ++ udelay(1000); ++ loop++; ++ if (loop > timeout) ++ break; ++ ++ } while (1); ++ ++ return FALSE; ++} ++ ++/* ++ * Name: ++ * ste100p_InitPhy ++ * Description: ++ * MAC starts checking its link by using parallel detection and ++ * Autonegotiation and the same is set in the MAC configuration registers ++ * Arguments: ++ * p_mac - pointer to struct AT91S_EMAC ++ * Return value: ++ * TRUE - if link status set succesfully ++ * FALSE - if link status not set ++ */ ++UCHAR ste100p_InitPhy (AT91PS_EMAC p_mac) ++{ ++ UCHAR ret = FALSE; ++ unsigned short IntValue; ++ int aneg_status; ++ unsigned long loop; ++ ++ PhyReset(p_mac); ++ ++ at91rm9200_EmacEnableMDIO (p_mac); ++ ++ ste100p_Deisolate(p_mac); ++ ++ at91rm9200_EmacDisableMDIO (p_mac); ++ ++ ++ ++#if 1 ++ at91rm9200_EmacEnableMDIO (p_mac); ++ ++ ste100p_WaitForLink(p_mac, 10000 /* timeout in ms */); ++ ++ ret = ste100p_GetLinkSpeed (p_mac); ++ ++ if (!ret) ++ { ++ ste100p_AutoNegotiate(p_mac, aneg_status); ++#ifdef DEBUG_ETHER ++ if (aneg_status) ++ { ++ printf("link speed autonegotiated\n"); ++ ret = ste100p_GetLinkSpeed (p_mac); ++ } ++ else ++ printf("auto-neogtiation failed\n"); ++#endif //DEBUG_ETHER ++ } ++ ++ /* Disable PHY Interrupts */ ++ ++ at91rm9200_EmacReadPhy (p_mac, STE100P_XIE_REG, &IntValue); ++ udelay(1000); ++ /* disable all interrypts from SE100P */ ++ ++ IntValue &= ~(STE100P_XIE_ANCE | STE100P_XIE_RFE | STE100P_XIE_LDE | ++ STE100P_XIE_ANAE | STE100P_XIE_PDFE | STE100P_XIE_ANPE | STE100P_XIE_REFE); ++ ++ at91rm9200_EmacWritePhy (p_mac, STE100P_XIE_REG, &IntValue); ++ udelay(10000); ++ ++ ++ ++ at91rm9200_EmacDisableMDIO (p_mac); ++ udelay(1000); ++#endif ++ ++#ifdef DEBUG_ETHER ++ printf("ste100p InitPhy ["); ++ if (ret) ++ printf("OK]\n"); ++ else ++ printf("FAILED]\n"); ++#endif //DEBUG_ETHER ++ return (ret); ++} ++ ++ ++/* ++ * Name: ++ * ste100p_AutoNegotiate ++ * Description: ++ * MAC Autonegotiates with the partner status of same is set in the ++ * MAC configuration registers ++ * Arguments: ++ * dev - pointer to struct net_device ++ * Return value: ++ * TRUE - if link status set successfully ++ * FALSE - if link status not set ++ */ ++UCHAR ste100p_AutoNegotiate (AT91PS_EMAC p_mac, int *status) ++{ ++ unsigned short value; ++ unsigned short PhyAnar; ++ unsigned short PhyAnalpar; ++#ifdef DEBUG_ETHER ++ printf("ste100p AutoNegotiate\n"); ++#endif //DEBUG_ETHER ++#if 1 ++ /* Set ste100p control register */ ++ if (!at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &value)) ++ return FALSE; ++ ++ value &= ~STE100P_XCR_AN; /* remove autonegotiation enable */ ++ value |= STE100P_XCR_ISOLATE; /* Electrically isolate PHY */ ++ if (!at91rm9200_EmacWritePhy (p_mac, STE100P_XCR_REG, &value)) ++ return FALSE; ++ ++ if (!at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &value)) ++ return FALSE; ++ ++ ++ /* Set the Auto_negotiation Advertisement Register */ ++ /* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */ ++ PhyAnar = STE100P_ANA_NXTPG | STE100P_ANA_TXF | STE100P_ANA_TXH | ++ STE100P_ANA_10F | STE100P_ANA_10H | STE100P_ANA_SF; ++ if (!at91rm9200_EmacWritePhy (p_mac, STE100P_ANA_REG, &PhyAnar)) ++ return FALSE; ++ ++ /* Read the Control Register */ ++ if (!at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &value)) ++ return FALSE; ++ ++ value |= STE100P_XCR_SPEED | STE100P_XCR_AN | STE100P_XCR_FULL_DUP; ++ if (!at91rm9200_EmacWritePhy (p_mac, STE100P_XCR_REG, &value)) ++ return FALSE; ++ ++ /* Restart Auto_negotiation */ ++ value |= STE100P_XCR_AN; ++ value &= ~STE100P_XCR_ISOLATE; ++ value |= STE100P_XCR_RSTRT_AN; ++ ++ if (!at91rm9200_EmacWritePhy (p_mac, STE100P_XCR_REG, &value)) ++ return FALSE; ++ udelay(10000); ++ if (!at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &value)) ++ return FALSE; ++ ++ /*check AutoNegotiate complete */ ++ udelay (10000); ++ at91rm9200_EmacReadPhy (p_mac, STE100P_XSR_REG, &value); ++ if (!(value & STE100P_XSR_AN_COMPLETE)) ++ return FALSE; ++ ++ /* Get the AutoNeg Link partner base page */ ++ if (!at91rm9200_EmacReadPhy (p_mac, STE100P_ANLP_REG, &PhyAnalpar)) ++ return FALSE; ++ ++ if ((PhyAnar & STE100P_ANA_TXF) && (PhyAnalpar & STE100P_ANLP_LPTXF)) { ++ /*set MII for 100BaseTX and Full Duplex */ ++ p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; ++ return TRUE; ++ } ++ ++ if ((PhyAnar & STE100P_ANA_10F) && (PhyAnalpar & STE100P_ANLP_LPTXH)) { ++ /*set MII for 10BaseT and Full Duplex */ ++ p_mac->EMAC_CFG = (p_mac->EMAC_CFG & ++ ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) ++ | AT91C_EMAC_FD; ++ return TRUE; ++ } ++#endif ++ return FALSE; ++} ++ ++/* ++ * Name: ++ * ste100p_DisableInterrupts ++ * Description: ++ * disables interrupts ++ * Arguments: ++ * p_mac - pointer to AT91S_EMAC struct ++ */ ++void ste100p_DisableInterrupts (AT91PS_EMAC p_mac) ++{ ++ ++ unsigned short IntValue; ++ unsigned int rep; ++ ++ rep = 0; ++ ++ at91rm9200_EmacEnableMDIO (p_mac); ++ ++ /* Disable PHY Interrupts */ ++ ++ at91rm9200_EmacReadPhy (p_mac, STE100P_XIE_REG, &IntValue); ++ udelay(10000); ++ /* disable all interrypts from SE100P */ ++ ++ IntValue &= ~(STE100P_XIE_ANCE | STE100P_XIE_RFE | STE100P_XIE_LDE | ++ STE100P_XIE_ANAE | STE100P_XIE_PDFE | STE100P_XIE_ANPE | STE100P_XIE_REFE); ++ ++ at91rm9200_EmacWritePhy (p_mac, STE100P_XIE_REG, &IntValue); ++ udelay(10000); ++ ++ IntValue = 1; ++ ++ do ++ { ++ at91rm9200_EmacReadPhy (p_mac, STE100P_XCSIIS_REG, &IntValue); ++ rep++; ++ } while (IntValue != 0 && rep < 100); ++ ++ at91rm9200_EmacDisableMDIO (p_mac); ++} ++ ++ ++#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ ++ ++#endif /* CONFIG_DRIVER_ETHER */ +diff -Nurp ../u-boot-1.1.6/drivers/dataflash.c ./drivers/dataflash.c +--- ../u-boot-1.1.6/drivers/dataflash.c 2006-11-02 15:15:01.000000000 +0100 ++++ ./drivers/dataflash.c 2007-03-19 23:43:20.000000000 +0100 +@@ -46,8 +46,8 @@ extern int AT91F_DataFlashRead (AT91PS_D + unsigned long size, char *buffer); + extern int AT91F_DataFlashWrite( AT91PS_DataFlash pDataFlash, + unsigned char *src, +- int dest, +- int size ); ++ unsigned long dest, ++ unsigned long size ); + + int AT91F_DataflashInit (void) + { +@@ -68,6 +68,8 @@ int AT91F_DataflashInit (void) + dataflash_info[i].Device.pages_size = 528; + dataflash_info[i].Device.page_offset = 10; + dataflash_info[i].Device.byte_mask = 0x300; ++ dataflash_info[i].Device.total_size = ++ dataflash_info[i].Device.pages_size * dataflash_info[i].Device.pages_number; + dataflash_info[i].Device.cs = cs[i][1]; + dataflash_info[i].Desc.DataFlash_state = IDLE; + dataflash_info[i].logical_address = cs[i][0]; +@@ -79,6 +81,8 @@ int AT91F_DataflashInit (void) + dataflash_info[i].Device.pages_size = 528; + dataflash_info[i].Device.page_offset = 10; + dataflash_info[i].Device.byte_mask = 0x300; ++ dataflash_info[i].Device.total_size = ++ dataflash_info[i].Device.pages_size * dataflash_info[i].Device.pages_number; + dataflash_info[i].Device.cs = cs[i][1]; + dataflash_info[i].Desc.DataFlash_state = IDLE; + dataflash_info[i].logical_address = cs[i][0]; +@@ -90,6 +94,8 @@ int AT91F_DataflashInit (void) + dataflash_info[i].Device.pages_size = 1056; + dataflash_info[i].Device.page_offset = 11; + dataflash_info[i].Device.byte_mask = 0x700; ++ dataflash_info[i].Device.total_size = ++ dataflash_info[i].Device.pages_size * dataflash_info[i].Device.pages_number; + dataflash_info[i].Device.cs = cs[i][1]; + dataflash_info[i].Desc.DataFlash_state = IDLE; + dataflash_info[i].logical_address = cs[i][0]; +@@ -100,6 +106,8 @@ int AT91F_DataflashInit (void) + dataflash_info[i].Device.pages_size = 1056; + dataflash_info[i].Device.page_offset = 11; + dataflash_info[i].Device.byte_mask = 0x700; ++ dataflash_info[i].Device.total_size = ++ dataflash_info[i].Device.pages_size * dataflash_info[i].Device.pages_number; + dataflash_info[i].Device.cs = cs[i][1]; + dataflash_info[i].Desc.DataFlash_state = IDLE; + dataflash_info[i].logical_address = cs[i][0]; +@@ -220,11 +228,13 @@ int addr_dataflash (unsigned long addr) + int size_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr, unsigned long size) + { + /* is outside the dataflash */ +- if (((int)addr & 0x0FFFFFFF) > (pdataFlash->pDevice->pages_size * +- pdataFlash->pDevice->pages_number)) return 0; ++ ++ if (((unsigned long)addr & 0x0FFFFFFF) > pdataFlash->pDevice->total_size) ++ return 0; + /* is too large for the dataflash */ +- if (size > ((pdataFlash->pDevice->pages_size * +- pdataFlash->pDevice->pages_number) - ((int)addr & 0x0FFFFFFF))) return 0; ++ ++ if (size > ( pdataFlash->pDevice->total_size - ((unsigned long)addr & 0x0FFFFFFF))) ++ return 0; + + return 1; + } +diff -Nurp ../u-boot-1.1.6/include/asm-arm/arch-at91rm9200/AT91RM9200.h ./include/asm-arm/arch-at91rm9200/AT91RM9200.h +--- ../u-boot-1.1.6/include/asm-arm/arch-at91rm9200/AT91RM9200.h 2006-11-02 15:15:01.000000000 +0100 ++++ ./include/asm-arm/arch-at91rm9200/AT91RM9200.h 2007-03-11 16:21:22.000000000 +0100 +@@ -625,14 +625,40 @@ typedef struct _AT91S_PDC + #define AT91C_PA26_TWCK ((unsigned int) 1 << 26) + #define AT91C_PA31_DTXD ((unsigned int) AT91C_PIO_PA31) /* DBGU Debug Transmit Data */ + #define AT91C_PIO_PA17 ((unsigned int) 1 << 17) /* Pin Controlled by PA17 */ ++#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) /* Pin Controlled by PA19 */ ++#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) /* Pin Controlled by PA22 */ ++#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) /* Pin Controlled by PA23 */ ++#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) /* Pin Controlled by PA24 */ ++#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) /* Pin Controlled by PA26 */ ++#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) /* Pin Controlled by PA27 */ ++#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) /* Pin Controlled by PA28 */ ++#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) /* Pin Controlled by PA29 */ ++ + #define AT91C_PA17_TXD0 AT91C_PIO_PA17 /* USART0 Transmit Data */ + #define AT91C_PIO_PA18 ((unsigned int) 1 << 18) /* Pin Controlled by PA18 */ + #define AT91C_PA18_RXD0 AT91C_PIO_PA18 /* USART0 Receive Data */ + #define AT91C_PIO_PB20 ((unsigned int) 1 << 20) /* Pin Controlled by PB20 */ + #define AT91C_PB20_RXD1 AT91C_PIO_PB20 /* USART1 Receive Data */ ++ ++#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) /* Pin Controlled by PB29 */ ++#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) /* Pin Controlled by PB28 */ ++ + #define AT91C_PIO_PB21 ((unsigned int) 1 << 21) /* Pin Controlled by PB21 */ + #define AT91C_PB21_TXD1 AT91C_PIO_PB21 /* USART1 Transmit Data */ + ++ ++#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) /* Pin Controlled by PB0 */ ++#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) /* Pin Controlled by PB2 */ ++#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) /* Pin Controlled by PB8 */ ++#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) /* Pin Controlled by PB9 */ ++#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) /* Pin Controlled by PB10 */ ++#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) /* Pin Controlled by PB11 */ ++ ++#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) /* Pin Controlled by PB22 */ ++#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) /* Pin Controlled by PB23 */ ++#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) /* Pin Controlled by PB24 */ ++#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) /* Pin Controlled by PB26 */ ++ + #define AT91C_ID_SYS ((unsigned int) 1) /* System Peripheral */ + #define AT91C_ID_PIOA ((unsigned int) 2) /* PIO port A */ + #define AT91C_ID_PIOB ((unsigned int) 3) /* PIO port B */ +@@ -671,6 +697,8 @@ typedef struct _AT91S_PDC + #define AT91C_PIO_PA6 ((unsigned int) 1 << 6) /* Pin Controlled by PA6 */ + #define AT91C_PA6_NPCS3 ((unsigned int) AT91C_PIO_PA6) /* SPI Peripheral Chip Select 3 */ + ++#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) /* Pin Controlled by PA20 */ ++#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) /* Pin Controlled by PA21 */ + #define AT91C_PIO_PA16 ((unsigned int) 1 << 16) /* Pin Controlled by PA16 */ + #define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) /* Ethernet MAC Management Data Input/Output */ + #define AT91C_PIO_PA15 ((unsigned int) 1 << 15) /* Pin Controlled by PA15 */ +@@ -697,6 +725,7 @@ typedef struct _AT91S_PDC + #define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */ + #define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */ + #define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */ ++#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) /* Pin Controlled by PB27 */ + #define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */ + #define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */ + #define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */ +diff -Nurp ../u-boot-1.1.6/include/asm-arm/arch-at91rm9200/mmc.h ./include/asm-arm/arch-at91rm9200/mmc.h +--- ../u-boot-1.1.6/include/asm-arm/arch-at91rm9200/mmc.h 1970-01-01 01:00:00.000000000 +0100 ++++ ./include/asm-arm/arch-at91rm9200/mmc.h 2006-10-13 20:55:04.000000000 +0200 +@@ -0,0 +1,117 @@ ++/* ++ * linux/include/linux/mmc/mmc.h ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#ifndef MMC_H ++#define MMC_H ++ ++#include ++#include ++#include ++ ++struct request; ++struct mmc_data; ++struct mmc_request; ++ ++struct mmc_command { ++ u32 opcode; ++ u32 arg; ++ u32 resp[4]; ++ unsigned int flags; /* expected response type */ ++#define MMC_RSP_PRESENT (1 << 0) ++#define MMC_RSP_136 (1 << 1) /* 136 bit response */ ++#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ ++#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ ++#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ ++#define MMC_CMD_MASK (3 << 5) /* command type */ ++#define MMC_CMD_AC (0 << 5) ++#define MMC_CMD_ADTC (1 << 5) ++#define MMC_CMD_BC (2 << 5) ++#define MMC_CMD_BCR (3 << 5) ++ ++/* ++ * These are the response types, and correspond to valid bit ++ * patterns of the above flags. One additional valid pattern ++ * is all zeros, which means we don't expect a response. ++ */ ++#define MMC_RSP_NONE (0) ++#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) ++#define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY) ++#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) ++#define MMC_RSP_R3 (MMC_RSP_PRESENT) ++#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC) ++ ++#define mmc_resp_type(cmd) ((cmd)->flags & (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC|MMC_RSP_BUSY|MMC_RSP_OPCODE)) ++ ++/* ++ * These are the command types. ++ */ ++#define mmc_cmd_type(cmd) ((cmd)->flags & MMC_CMD_MASK) ++ ++ unsigned int retries; /* max number of retries */ ++ unsigned int error; /* command error */ ++ ++#define MMC_ERR_NONE 0 ++#define MMC_ERR_TIMEOUT 1 ++#define MMC_ERR_BADCRC 2 ++#define MMC_ERR_FIFO 3 ++#define MMC_ERR_FAILED 4 ++#define MMC_ERR_INVALID 5 ++ ++ struct mmc_data *data; /* data segment associated with cmd */ ++ struct mmc_request *mrq; /* associated request */ ++}; ++ ++struct mmc_data { ++ unsigned int timeout_ns; /* data timeout (in ns, max 80ms) */ ++ unsigned int timeout_clks; /* data timeout (in clocks) */ ++ unsigned int blksz_bits; /* data block size */ ++ unsigned int blksz; /* data block size */ ++ unsigned int blocks; /* number of blocks */ ++ unsigned int error; /* data error */ ++ unsigned int flags; ++ ++#define MMC_DATA_WRITE (1 << 8) ++#define MMC_DATA_READ (1 << 9) ++#define MMC_DATA_STREAM (1 << 10) ++#define MMC_DATA_MULTI (1 << 11) ++ ++ unsigned int bytes_xfered; ++ ++ struct mmc_command *stop; /* stop command */ ++ struct mmc_request *mrq; /* associated request */ ++ ++ unsigned int sg_len; /* size of scatter list */ ++ struct scatterlist *sg; /* I/O scatter list */ ++}; ++ ++struct mmc_request { ++ struct mmc_command *cmd; ++ struct mmc_data *data; ++ struct mmc_command *stop; ++ ++ void *done_data; /* completion data */ ++ void (*done)(struct mmc_request *);/* completion function */ ++}; ++ ++struct mmc_host; ++struct mmc_card; ++ ++extern int mmc_wait_for_req(struct mmc_host *, struct mmc_request *); ++extern int mmc_wait_for_cmd(struct mmc_host *, struct mmc_command *, int); ++extern int mmc_wait_for_app_cmd(struct mmc_host *, unsigned int, ++ struct mmc_command *, int); ++ ++extern int __mmc_claim_host(struct mmc_host *host, struct mmc_card *card); ++ ++static inline void mmc_claim_host(struct mmc_host *host) ++{ ++ __mmc_claim_host(host, (struct mmc_card *)-1); ++} ++ ++extern void mmc_release_host(struct mmc_host *host); ++ ++#endif +diff -Nurp ../u-boot-1.1.6/include/at91rm9200_net.h ./include/at91rm9200_net.h +--- ../u-boot-1.1.6/include/at91rm9200_net.h 2006-11-02 15:15:01.000000000 +0100 ++++ ./include/at91rm9200_net.h 2007-05-04 22:14:56.000000000 +0200 +@@ -38,6 +38,7 @@ typedef struct _AT91S_PhyOps + unsigned int (*IsPhyConnected)(AT91S_EMAC *pmac); + unsigned char (*GetLinkSpeed)(AT91S_EMAC *pmac); + unsigned char (*AutoNegotiate)(AT91S_EMAC *pmac, int *); ++ unsigned int (*Isolate)(AT91S_EMAC *pmac); + + } AT91S_PhyOps,*AT91PS_PhyOps; + +diff -Nurp ../u-boot-1.1.6/include/configs/sarge.h ./include/configs/sarge.h +--- ../u-boot-1.1.6/include/configs/sarge.h 1970-01-01 01:00:00.000000000 +0100 ++++ ./include/configs/sarge.h 2007-05-10 00:02:56.000000000 +0200 +@@ -0,0 +1,281 @@ ++/* ++ * Grzegorz Rajtar ++ * ++ * Configuation settings for the Sarge (AT91RM9200DK like) board. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++ ++//#define DEBUG ++ ++#define CFG_SARGE_STACK_SIZE (32 * 1024) ++ ++/* ARM asynchronous clock */ ++#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ ++#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ ++/* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */ ++#define CFG_AT91C_BRGR_DIVISOR 33 ++ ++#define AT91_SLOW_CLOCK 32768 /* slow clock */ ++ ++#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ ++#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ ++#define CONFIG_AT91RM9200_SARGE 1 ++ ++#define CONFIG_USE_IRQ 1 /* we don't need IRQ/FIQ stuff */ ++//#undef CONFIG_USE_IRQ ++#define USE_920T_MMU 1 ++//#undef USE_920T_MMU ++#define MMU_DEBUG 1 ++ ++#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ ++#define CONFIG_SETUP_MEMORY_TAGS 1 ++#define CONFIG_INITRD_TAG 1 ++ ++#define CONFIG_SKIP_LOWLEVEL_INIT 1 ++#define CONFIG_SKIP_RELOCATE_UBOOT 1 ++#define CFG_USE_MAIN_OSCILLATOR 1 ++ ++ ++#ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#define CFG_USE_MAIN_OSCILLATOR 1 ++/* flash */ ++#define MC_PUIA_VAL 0x00000000 ++#define MC_PUP_VAL 0x00000000 ++#define MC_PUER_VAL 0x00000000 ++#define MC_ASR_VAL 0x00000000 ++#define MC_AASR_VAL 0x00000000 ++#define EBI_CFGR_VAL 0x00000000 ++#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ ++ ++/* clocks */ ++#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ ++#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ ++#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ ++ ++/* sdram */ ++#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ ++#define PIOC_BSR_VAL 0x00000000 ++#define PIOC_PDR_VAL 0xFFFF0000 ++#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ ++//#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */ ++#define SDRC_CR_VAL 0x2188A155 /* set up the SDRAM */ ++#define SDRAM 0x20000000 /* address of the SDRAM */ ++#define SDRAM1 0x20000080 /* address of the SDRAM */ ++#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ ++#define SDRC_MR_VAL 0x00000002 /* Precharge All */ ++#define SDRC_MR_VAL1 0x00000004 /* refresh */ ++#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ ++#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ ++#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ ++#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ ++/* ++ * Size of malloc() pool ++ */ ++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128 << 10)) ++//#define CFG_MALLOC_LEN ((4 << 20)) ++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ ++ ++#define CONFIG_BAUDRATE 115200 ++//#define CFG_CONSOLE_INFO_QUIET 0 ++#undef CFG_CONSOLE_INFO_QUIET ++ ++/* ++ * Hardware drivers ++ */ ++ ++/* define one of these to choose the DBGU, USART0 or USART1 as console */ ++#define CONFIG_DBGU ++#undef CONFIG_USART0 ++#undef CONFIG_USART1 ++ ++#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ ++ ++#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ ++ ++#define CONFIG_BOOTDELAY 3 ++/* #define CONFIG_ENV_OVERWRITE 1 */ ++ ++#define CONFIG_MII 1 ++#define CONFIG_HARD_I2C ++#define CFG_I2C_SPEED 100000 ++#define CFG_I2C_SLAVE 0xFE ++//#define CONFIG_TERSE_MII 1 ++#define CONFIG_DOS_PARTITION 1 ++#define CONFIG_USB_OHCI 1 ++#define CONFIG_COMMANDS \ ++ ((CONFIG_CMD_DFL | CFG_CMD_MII | CFG_CMD_NET | \ ++ CFG_CMD_MISC | \ ++ CFG_CMD_SDRAM | \ ++ CFG_CMD_PING | \ ++ CFG_CMD_DHCP | \ ++ CFG_CMD_BOOTP | \ ++ CFG_CMD_BOOTD | \ ++ CFG_CMD_I2C | \ ++ CFG_CMD_EEPROM | \ ++ CFG_CMD_USB | \ ++ CFG_CMD_BDI) & \ ++ ~(CFG_CMD_IMI | \ ++ CFG_CMD_AUTOSCRIPT | \ ++ CFG_CMD_LOADS )) ++ ++#define CFG_I2C_EEPROM_ADDR_LEN 1 ++ ++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ ++#include ++ ++//#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ ++//#define SECTORSIZE 512 ++ ++//#define ADDR_COLUMN 1 ++//#define ADDR_PAGE 2 ++//#define ADDR_COLUMN_PAGE 3 ++ ++//#define NAND_ChipID_UNKNOWN 0x00 ++//#define NAND_MAX_FLOORS 1 ++//#define NAND_MAX_CHIPS 1 ++ ++//#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ ++//#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ ++ ++//#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0) ++//#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0) ++ ++//#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2)) ++ ++//#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0) ++//#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0) ++//#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) ++//#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) ++/* the following are NOP's in our implementation */ ++//#define NAND_CTL_CLRALE(nandptr) ++//#define NAND_CTL_SETALE(nandptr) ++//#define NAND_CTL_CLRCLE(nandptr) ++//#define NAND_CTL_SETCLE(nandptr) ++ ++ ++#define CONFIG_NR_DRAM_BANKS 1 ++#define PHYS_SDRAM 0x20000000 ++#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */ ++ ++#define CFG_MEMTEST_START PHYS_SDRAM ++#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 ++ ++#define CONFIG_DRIVER_ETHER 1 ++#define CONFIG_NET_RETRY_COUNT 20 ++#define STE100P_ETH 1 ++//#define CONFIG_STE100P_OVERRIDE_HARDWARE 1 ++ ++#define CONFIG_HAS_DATAFLASH 1 ++#define CFG_SPI_WRITE_TOUT (10 * CFG_HZ) ++#define CFG_MAX_DATAFLASH_BANKS 2 ++#define CFG_MAX_DATAFLASH_PAGES 16384 ++#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ ++#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ ++ ++#define PHYS_FLASH_1 0x10000000 ++#define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */ ++#define CFG_FLASH_BASE PHYS_FLASH_1 ++#define CFG_MAX_FLASH_BANKS 1 ++#define CFG_MAX_FLASH_SECT 256 ++#define CFG_FLASH_ERASE_TOUT (10 * CFG_HZ) /* Timeout for Flash Erase */ ++#define CFG_FLASH_WRITE_TOUT (10 * CFG_HZ) /* Timeout for Flash Write */ ++ ++ ++#define CFG_ENV_IS_IN_DATAFLASH ++ ++#ifdef CFG_ENV_IS_IN_DATAFLASH ++#define CFG_ENV_OFFSET 0x200000 ++#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) ++#define CFG_ENV_SIZE 0x2000 /* 0x2000 */ ++#else ++#define CFG_ENV_IS_IN_FLASH 1 ++#ifdef CONFIG_SKIP_LOWLEVEL_INIT ++#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */ ++#define CFG_ENV_SIZE 0x10000 /* sectors are 64K here */ ++#else ++#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */ ++#define CFG_ENV_SIZE 0x2000 /* 0x8000 */ ++#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ ++#endif /* CFG_ENV_IS_IN_DATAFLASH */ ++ ++#define CFG_LOAD_ADDR 0x21000000 ++ ++#ifdef CONFIG_SKIP_LOWLEVEL_INIT ++#define CFG_BOOT_SIZE 0x00 /* 0 KBytes */ ++#define CFG_U_BOOT_BASE PHYS_FLASH_1 ++#define CFG_U_BOOT_SIZE 0x60000 /* 384 KBytes */ ++#else ++#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */ ++#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000) ++#define CFG_U_BOOT_SIZE 0x10000 /* 128 KBytes */ ++#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ ++ ++#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } ++ ++#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */ ++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ ++#define CFG_MAXARGS 16 /* max number of command args */ ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ ++ ++#ifndef __ASSEMBLY__ ++/*----------------------------------------------------------------------- ++ * Board specific extension for bd_info ++ * ++ * This structure is embedded in the global bd_info (bd_t) structure ++ * and can be used by the board specific code (eg board/...) ++ */ ++ ++struct bd_info_ext { ++ /* helper variable for board environment handling ++ * ++ * env_crc_valid == 0 => uninitialised ++ * env_crc_valid > 0 => environment crc in flash is valid ++ * env_crc_valid < 0 => environment crc in flash is invalid ++ */ ++ int env_crc_valid; ++}; ++#endif ++ ++#define CFG_HZ 1000 ++#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ ++#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ ++ ++ /* AT91C_TC_TIMER_DIV1_CLOCK */ ++#ifdef CONFIG_USE_IRQ ++//#error CONFIG_USE_IRQ not supported ++ #define CONFIG_STACKSIZE_IRQ (4*1024) ++ #define CONFIG_STACKSIZE_FIQ (4*1024) ++#endif ++ ++#define CONFIG_BOOTARGS "mem=32M rootfstype=ext2 root=/dev/mmcblk0p1 console=ttyS0,115200n8 rootdelay=5 init=/sbin/init" ++#define CONFIG_ETHADDR 00:01:20:38:00:5b ++#define CONFIG_NETMASK 255.255.255.0 ++#define CONFIG_IPADDR 192.168.0.212 ++#define CONFIG_SERVERIP 192.168.0.200 ++#define CONFIG_BOOTCOMMAND " bootm 0xC0040000" ++#define CONFIG_BOOTFILE "sarge_at91.img" ++#define CONFIG_ROOTPATH "/tftp/at91/rootfs" ++#define CONFIG_LOADADDR 0x21000000 ++#define CONFIG_NFSARGS "mem=32M console=ttyS0,115200n8 root=/dev/nfs nfsroot=192.168.0.200:/tftp/at91/rootfs,timeo=200,retrans=500 ip=:::::eth0:on" ++#endif +diff -Nurp ../u-boot-1.1.6/include/dataflash.h ./include/dataflash.h +--- ../u-boot-1.1.6/include/dataflash.h 2006-11-02 15:15:01.000000000 +0100 ++++ ./include/dataflash.h 2007-03-19 23:29:49.000000000 +0100 +@@ -79,6 +79,7 @@ typedef struct _AT91S_Dataflash { + int page_offset; /* page offset in command */ + int byte_mask; /* byte mask in command */ + int cs; ++ unsigned long total_size; + dataflash_protect_t area_list[NB_DATAFLASH_AREA]; /* area protection status */ + } AT91S_DataflashFeatures, *AT91PS_DataflashFeatures; + +@@ -107,7 +108,7 @@ typedef struct _AT91S_DATAFLASH_INFO { + #define AT45DB642 0x3c + #define AT45DB128 0x10 + +-#define AT91C_DATAFLASH_TIMEOUT 10000 /* For AT91F_DataFlashWaitReady */ ++#define AT91C_DATAFLASH_TIMEOUT 800000 /* For AT91F_DataFlashWaitReady */ + + /* DataFlash return value */ + #define DATAFLASH_BUSY 0x00 +diff -Nurp ../u-boot-1.1.6/include/_exports.h ./include/_exports.h +--- ../u-boot-1.1.6/include/_exports.h 2006-11-02 15:15:01.000000000 +0100 ++++ ./include/_exports.h 2007-03-15 23:41:08.000000000 +0100 +@@ -18,4 +18,4 @@ EXPORT_FUNC(simple_strtoul) + #if (CONFIG_COMMANDS & CFG_CMD_I2C) + EXPORT_FUNC(i2c_write) + EXPORT_FUNC(i2c_read) +-#endif /* CFG_CMD_I2C */ ++#endif /* CFG_CMD_I2C */ +\ Brak znaku nowej linii na koÅ„cu pliku +diff -Nurp ../u-boot-1.1.6/include/gunzip.h ./include/gunzip.h +--- ../u-boot-1.1.6/include/gunzip.h 1970-01-01 01:00:00.000000000 +0100 ++++ ./include/gunzip.h 2007-03-21 23:23:36.000000000 +0100 +@@ -0,0 +1,73 @@ ++#ifndef _GUNZIP_H ++#define _GUNZIP_H ++ ++/* unzip code taken from bios-lt project */ ++/* http://sourceforge.net/projects/bios-lt */ ++/* maintainer Liu Tao */ ++ ++#define ERR_BADMAGIC 1 ++#define ERR_BADMETHOD 2 ++#define ERR_ENCRYPTED 3 ++#define ERR_MULTIPART 4 ++#define ERR_INVALIDFLAGS 5 ++#define ERR_BADFORMAT1 6 ++#define ERR_BADFORMAT2 7 ++#define ERR_MEM 8 ++#define ERR_BADFORMAT 9 ++#define ERR_CRC 10 ++#define ERR_LENGTH 11 ++ ++#define PACK_MAGIC "\037\036" /* Magic header for packed files */ ++#define GZIP_MAGIC "\037\213" /* Magic header for gzip files, 1F 8B */ ++#define OLD_GZIP_MAGIC "\037\236" /* Magic header for gzip 0.5 = freeze 1.x */ ++#define LZH_MAGIC "\037\240" /* Magic header for SCO LZH Compress files*/ ++#define PKZIP_MAGIC "\120\113\003\004" /* Magic header for pkzip files */ ++ ++/* gzip flag byte */ ++#define ASCII_FLAG 0x01 /* bit 0 set: file probably ascii text */ ++#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */ ++#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */ ++#define ORIG_NAME 0x08 /* bit 3 set: original file name present */ ++#define COMMENT 0x10 /* bit 4 set: file comment present */ ++#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */ ++#define RESERVED 0xC0 /* bit 6,7: reserved */ ++ ++/* If B_MAX needs to be larger than 16, then h and x[] should be ulong. */ ++#define B_MAX 16 /* maximum bit length of any code (16 for explode) */ ++#define N_MAX 288 /* maximum number of codes in any set */ ++ ++ ++#define NULL 0 ++ ++#define __TYPES_DEFINED ++#ifndef TYPES_DEFINED ++typedef unsigned char uchar; ++typedef unsigned short ushort; ++typedef unsigned long ulong; ++typedef ushort huft_code; ++typedef uchar huft_bits; ++#endif ++ ++#define get_uchar(guz) (uchar)(guz->inptr < guz->insize ? guz->inbuf[guz->inptr++] : 0) ++#define get_ushort(guz) ((ushort)get_uchar(guz) | (ushort)get_uchar(guz) << 8) ++#define get_ulong(guz) ((ulong)get_uchar(guz)|(ulong)get_uchar(guz)<<8|(ulong)get_uchar(guz)<<16|(ulong)get_uchar(guz) << 24) ++#define output_char(guz, ch) (guz)->outbuf[(guz)->outptr++] = ch ++ ++typedef struct { ++ uchar *inbuf; ++ ulong insize; ++ ulong inptr; ++ ++ uchar *outbuf; ++ ulong outsize; ++ ulong outptr; ++ ++ ulong bitbuf; ++ ulong bufbits; ++ ++} gunzip_t; ++ ++int gunzip(unsigned char *inbuf, unsigned long *insize, ++ unsigned char *outbuf, unsigned long *outsize); ++ ++#endif /* _GUNZIP_H */ +diff -Nurp ../u-boot-1.1.6/include/ste100p.h ./include/ste100p.h +--- ../u-boot-1.1.6/include/ste100p.h 1970-01-01 01:00:00.000000000 +0100 ++++ ./include/ste100p.h 2007-05-05 01:38:11.000000000 +0200 +@@ -0,0 +1,163 @@ ++#ifndef _ste100p_h_ ++#define _ste100p_h_ ++ ++ ++// UTILS ++#define Bit(n) (1<<(n)) ++ ++ ++// STE100P register offsets. ++ ++#define STE100P_XCR_REG 0x00 ++#define STE100P_XSR_REG 0x01 ++#define STE100P_PID1_REG 0x02 ++#define STE100P_PID2_REG 0x03 ++#define STE100P_ANA_REG 0x04 ++#define STE100P_ANLP_REG 0x05 ++#define STE100P_ANE_REG 0x06 ++#define STE100P_XCSIIS_REG 0x11 ++#define STE100P_XIE_REG 0x12 ++#define STE100P_100CTR_REG 0x13 ++#define STE100P_XMC_REG 0x14 ++ ++ ++// STE100P XCR - Control register bit defines. ++#define STE100P_XCR_RESET 0x8000 //(RW) ++#define STE100P_XCR_LOOPBACK 0x4000 //(RW) ++#define STE100P_XCR_SPEED 0x2000 // 1=100Meg, 0=10Meg (RW) ++#define STE100P_XCR_AN 0x1000 // 1=Enable auto negotiation, 0=disable it (RW) ++#define STE100P_XCR_PWRDN 0x0800 // 1=Enable power down (RW) ++#define STE100P_XCR_ISOLATE 0x0400 // 1=Isolate PHY from MII (RW) ++#define STE100P_XCR_RSTRT_AN 0x0200 // 1=Restart Auto Negotioation process (RW) ++#define STE100P_XCR_FULL_DUP 0x0100 // 1=Enable full duplex mode, 0=half dup (RW) ++#define STE100P_XCR_COLLEN 0x0080 // 1=Collision test control (RW) ++ ++// STE100P XSR - Control status bit defines. ++ ++#define STE100P_XSR_100T4 Bit(15) // (RO) ++#define STE100P_XSR_100TX_FULL Bit(14) // (RO) ++#define STE100P_XSR_100TX Bit(13) // (RO) ++#define STE100P_XSR_10T_FULL Bit(12) // (RO) ++#define STE100P_XSR_10T Bit(11) // (RO) ++#define STE100P_XSR_MFPS Bit(6) //MF preamble suppression (RO) ++#define STE100P_XSR_AN_COMPLETE Bit(5) ++#define STE100P_XSR_RF Bit(4) //RF result of remote fault detection (RO/LH) ++#define STE100P_XSR_AN Bit(3) //AN - auto-negotation ability, always 1 for STE100P (RO) ++#define STE100P_XSR_LINK Bit(2) // Link status (RO/LL) ++#define STE100P_XSR_JABBER Bit(1) // Jabber condition is detected (10Base-T only) (RO/LH) ++#define STE100P_XSR_EXT Bit(0) // Extended register support, always 1 for STE100P (RO) ++ ++ ++// STE100P PHY identification bit defines. ++ ++#define STE100P_PID1_PHYID_VAL 0x1C04 // (RO) ++ ++#define STE100P_PID2_PHYID_MASK 0xFC00 // (RO) ++#define STE100P_PID2_PHYID_VAL 0x0 ++#define STE100P_PID2_MODEL_MASK 0x01F0 // (RO) ++#define STE100P_PID2_MODEL_VAL 0x1 ++#define STE100P_PID2_REV_MASK 0x000F // (RO) ++#define STE100P_PID2_REV_VAL 0x1 ++ ++// STE100P auto-negatiation bit defines. ++ ++#define STE100P_ANA_NXTPG Bit(15) //Next Page avability, always 0 for STE100P. (RO) ++#define STE100P_ANA_RF Bit(13) // Remote fault function. (RW) ++#define STE100P_ANA_FC Bit(10) // Flow Control function Ability, 1 - supports PAUSE operation of flow control for full-duplex link. (RW) ++#define STE100P_ANA_T4 Bit(9) // 100Base-T4 ability, always 0 for STE100P. (RO) ++#define STE100P_ANA_TXF Bit(8) // 100Base-TX full duplex ability, 1 with 100Base-TX full duplex ability. (RW) ++#define STE100P_ANA_TXH Bit(7) // 100Base-TX half duplex ability, 1 with 100Base-TX half duplex ability. (RW) ++ ++#define STE100P_ANA_10F Bit(6) // 10Base-T full duplex ability, 1 with 10Base-T full duplex ability. (RW) ++#define STE100P_ANA_10H Bit(5) // 10Base-T half duplex ability, 1 with 10Base-T half duplex ability. (RW) ++#define STE100P_ANA_SF 0x0000 // select field, default val 0, (RO) ++#define STE100P_ANA_SF_MASK 0x000F // STE100P_ANA_SF mask ++ ++// STE100P auto-negatiation link partner ability bit defines. ++ ++#define STE100P_ANLP_LPNP Bit(15) // Link partner next page, 1 ON. (RO) ++#define STE100P_ANLP_LPACK Bit(14) // Received link parnter ACK, 1 received. (RO) ++#define STE100P_ANLP_LPRF Bit(13) // Link partner's remote fault status, 1 - remote fault detected. (RO) ++#define STE100P_ANLP_LPFC Bit(10) // Link partner's flow control ability, 1 - link partner with PAUSE function full duplex link ability. (RO) ++#define STE100P_ANLP_LPT4 Bit(9) // Link partner's 100Base-T4 ability, 1 - link parnter with 100Base-T4 ability. (RO) ++#define STE100P_ANLP_LPTXF Bit(8) // Link partner's 100Base-TX full duplex ability, 1 - link parnter with 100Base-TX full duplex ability. (RO) ++#define STE100P_ANLP_LPTXH Bit(7) // Link partner's 100Base-TX half duplex ability, 1 - link parnter with 100Base-TX half duplex ability. (RO) ++#define STE100P_ANLP_LP10F Bit(6) // Link partner's 10Base-T full duplex ability, 1 - link parnter with 10Base-T full duplex ability. (RO) ++#define STE100P_ANLP_LP10H Bit(5) // Link partner's 10Base-T half duplex ability, 1 - link parnter with 10Base-T half duplex ability. (RO) ++#define STE100P_ANLP_LPFS 0x001F // Link partner selct field, default 0x0001 = IEEE 802.3 (RO) ++ ++// STE100P auto-negatiation expansion bit defines. ++ ++#define STE100P_ANE_PDF Bit(4) // Parallel detection fault, 1 - fault detecrted (RO/LH). ++#define STE100P_ANE_LPNP Bit(3) // Link partner's next page ability, 1 - link partner with next page ability (RO). ++#define STE100P_ANE_NP Bit(2) // STE100P next page ability, always 0 (RO). ++#define STE100P_ANE_PR Bit(1) // Page received, 1 - a new page has been received (RO/LH). ++#define STE100P_ANE_LPAN Bit(0) // Link partner auto-negotiation ability, 1 - LP has auto-negotiation ability (RO) ++ ++// STE100P configuration information and interrupt status bit defines ++ ++#define STE100P_XCIIS_SPEED Bit(9) // Configured information of SPEED, 0 - 10Mbit/s, 1 - 100Mbit/s. (RO) ++#define STE100P_XCIIS_DUPLEX Bit(8) // Configured information of DUPLEX, 0 - half-duplex, 1 - full-duplex. (RO) ++#define STE100P_XCIIS_PAUSE Bit(7) // Configured information of PAUSE, 0 - pause function disabled, 1 - pause function enabled. (RO) ++#define STE100P_XCIIS_ANC Bit(6) // Interrupt source of auto-negotiation completed, 0 - auto-negotiation is not completed yet. (RO/LH) ++#define STE100P_XCIIS_RFD Bit(5) // Interrupt source of remote fault detected, 0 -fault not detected, 1 - fault detected. (RO/LH) ++#define STE100P_XCIIS_LS Bit(4) // Interrupt source link fail, 0 - link test status is up, 1 - link is down. (RO/LH). ++#define STE100P_XCIIS_ANAR Bit(3) // Interrupt source of auto-negotiation ACK received, 0 - auto-negotiation not received. (RO/LH) ++#define STE100P_XCIIS_PDF Bit(2) // Interrupt source of parallel detection fault, 0 - fault not detected. (RO/LH) ++#define STE100P_XCIIS_ANPR Bit(1) // Interrupt source of auto-negotiation page received, 1 - auto-negotiation page os received (RO/LH) ++#define STE100P_XCIIS_REF Bit(0) // Interrupt source of receive full error, 0 - the receive error number is less than 64, 1 - 64 error packets ++ // are received (RO/LH) ++ ++// STE100P interrupt enable register bit defines ++ ++#define STE100P_XIE_ANCE Bit(6) // Auto-negtiation completed interrupt enable: 0/1 - disable/enable auto-negotiation completed interrupt. (RW) ++#define STE100P_XIE_RFE Bit(5) // Remote fault detected interrupt enable: 0/1 - disable/enable remote fault detection interrupt. (RW) ++#define STE100P_XIE_LDE Bit(4) // Link down interrupt enable: 0/1 - disable/enable link down detection interrupt. (RW) ++#define STE100P_XIE_ANAE Bit(3) // Auto-negotiation acknowledge interrupt enable: 0/1 - disable/enable link partner acknowledge interrupt. (RW) ++#define STE100P_XIE_PDFE Bit(2) // Parallel detection fault interrupt enable: 0/1 - disable/enable fault parallel detection interrupt. (RW) ++#define STE100P_XIE_ANPE Bit(1) // Auto-negotiation page received interrupt enable: 0/1 - disable/enable auto-negotiation page received interrupt. (RW) ++#define STE100P_XIE_REFE Bit(0) // RX_ERR page full interrupt enable: 0 - disable rx_err full interrupt, 1 - enable more than 64 time rx_err interrupt (RW) ++ ++// STE100P 100Base-TX control register bit defines ++ ++#define STE100P_100CTR_DISRER Bit(13) // Disable the RX_ERR counter, 0 - receive error counter RX_ERR is enabled, 1 - ... disabled. (RW) ++#define STE100P_100CTR_ANC Bit(12) // Auto-negotiation completed, 0 - auto-negotiation process has not completed yet, 1 - auto-negotiation process has completed. (RO) ++#define STE100P_100CTR_ENRLB Bit(9) // Enable remote loop-back function: 1 - enable, 0 - disable (RW) ++#define STE100P_100CTR_ENDCR Bit(8) // Enable DC restoration: 0 - disable, 1 - enable (RW) ++#define STE100P_100CTR_ENRZI Bit(7) // Enable the conversions between NRZ and NRZI (RW) ++#define STE100P_100CTR_EN4B5B Bit(6) // Enable 4B/5B encoder and decoder, 0 - the 4B/5B encoder and decoder are bypassed, 1 - .. enabled. (RW) ++#define STE100P_100CTR_ISOTX Bit(5) // Transmit isolation: 1 - isolate from MII, 0 - for normal operation. (RW) ++#define STE100P_100CTR_CMODE_MASK 0x001C // Reporting of current operation mode of transceiver: (RO) ++ // 000 - in auto-negotiation ++ // 001 - 10Base-T half duplex ++ // 010 - 100Base-TX half duplex ++ // 011 - reserved ++ // 100 - reserved ++ // 101 - 10Base-T full duplex ++ // 110 - 100Base-TX full duplex ++ // 111 - isolation, auto-negotiation disable ++#define STE100P_100CTR_DISMLT Bit(1) // Disable MLT3, 0 - encoder/decoder enabled, 1 - ... disabled, (RW) ++#define STE100P_100CTR_DISCRM Bit(0) // Disable Scramble, 0 - scrambler/descambler enabled, 1 - scrambler/descambler disabled, (RW) ++ ++ ++// STE100P mode control register bit defines ++ ++#define STE100P_XMC_LD Bit(11) // Long distance mode of 10Base-T: 0 - notmal squelch level, 1 - reduces squelch for extended cable lenght. (RW) ++#define STE100P_XMC_PAD_MASK 0x00F8 // PHY addres 4:0 - 0x0000 after reset causes to isolate the PHY from MII (PR0 - 10 bit is set) (RW). ++#define STE100P_XMC_MFPSE Bit(1) // MF preamble supression enable, 1 - accept management frames with pre-amble supressed. (RW) ++ ++ ++/* (R0) - register is rea-only. ++ * (RW) - register is rea-write. ++ * (LH) - latching high and cleared by reading. ++ * (LL) - latching low and cleared by reading. ++ */ ++ ++unsigned int ste100p_IsPhyConnected (AT91PS_EMAC p_mac); ++unsigned int ste100p_Isolate (AT91PS_EMAC p_mac); ++void ste100p_DisableInterrupts (AT91PS_EMAC p_mac); ++UCHAR ste100p_GetLinkSpeed (AT91PS_EMAC p_mac); ++UCHAR ste100p_InitPhy (AT91PS_EMAC p_mac); ++UCHAR ste100p_AutoNegotiate (AT91PS_EMAC p_mac, int *status); ++ ++#endif // _ste100p_h_ +diff -Nurp ../u-boot-1.1.6/lib_arm/armlinux.c ./lib_arm/armlinux.c +--- ../u-boot-1.1.6/lib_arm/armlinux.c 2006-11-02 15:15:01.000000000 +0100 ++++ ./lib_arm/armlinux.c 2007-05-05 01:28:02.000000000 +0200 +@@ -62,6 +62,10 @@ static void setup_end_tag (bd_t *bd); + static void setup_videolfb_tag (gd_t *gd); + # endif + ++#ifdef CONFIG_AT91RM9200_SARGE ++int sarge_before_linux(void); ++#endif ++ + + static struct tag *params; + #endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ +@@ -89,9 +93,7 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, i + #ifdef CONFIG_CMDLINE_TAG + char *commandline = getenv ("bootargs"); + #endif +- + theKernel = (void (*)(int, int, uint))ntohl(hdr->ih_ep); +- + /* + * Check if there is an initrd image + */ +@@ -224,7 +226,7 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, i + + debug ("## Transferring control to Linux (at address %08lx) ...\n", + (ulong) theKernel); +- ++ + #if defined (CONFIG_SETUP_MEMORY_TAGS) || \ + defined (CONFIG_CMDLINE_TAG) || \ + defined (CONFIG_INITRD_TAG) || \ +@@ -255,6 +257,10 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, i + setup_end_tag (bd); + #endif + ++#ifdef CONFIG_AT91RM9200_SARGE ++ sarge_before_linux(); ++#endif ++ + /* we assume that the kernel is in place */ + printf ("\nStarting kernel ...\n\n"); + +@@ -267,6 +273,8 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, i + + cleanup_before_linux (); + ++ ++ printf("kernel address is 0x%x\n", theKernel); + theKernel (0, bd->bi_arch_number, bd->bi_boot_params); + } + +@@ -348,7 +356,7 @@ static void setup_initrd_tag (bd_t *bd, + + params->u.initrd.start = initrd_start; + params->u.initrd.size = initrd_end - initrd_start; +- ++ + params = tag_next (params); + } + #endif /* CONFIG_INITRD_TAG */ +diff -Nurp ../u-boot-1.1.6/lib_arm/board.c ./lib_arm/board.c +--- ../u-boot-1.1.6/lib_arm/board.c 2006-11-02 15:15:01.000000000 +0100 ++++ ./lib_arm/board.c 2007-05-04 23:21:40.000000000 +0200 +@@ -94,6 +94,8 @@ void mem_malloc_init (ulong dest_addr) + mem_malloc_end = dest_addr + CFG_MALLOC_LEN; + mem_malloc_brk = mem_malloc_start; + ++ //printf("mem_malloc_start = %x, mem_malloc_end = %x\n", ++ // mem_malloc_start, mem_malloc_end); + memset ((void *) mem_malloc_start, 0, + mem_malloc_end - mem_malloc_start); + } +@@ -254,11 +256,14 @@ void start_armboot (void) + memset (gd->bd, 0, sizeof (bd_t)); + + monitor_flash_len = _bss_start - _armboot_start; +- ++ int num = 0; + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { + if ((*init_fnc_ptr)() != 0) { ++ printf("hanf at %d\n", num); + hang (); + } ++ else ++ num++; + } + + #ifndef CFG_NO_FLASH +@@ -391,8 +396,10 @@ void start_armboot (void) + #if defined(CONFIG_NET_MULTI) + puts ("Net: "); + #endif +- eth_initialize(gd->bd); ++ puts("eth_initialize\n"); ++ eth_initialize(gd->bd); + #endif ++ + /* main_loop() can return to retry autoboot, if so just run it again. */ + for (;;) { + main_loop (); +diff -Nurp ../u-boot-1.1.6/lib_generic/gunzip.c ./lib_generic/gunzip.c +--- ../u-boot-1.1.6/lib_generic/gunzip.c 1970-01-01 01:00:00.000000000 +0100 ++++ ./lib_generic/gunzip.c 2007-03-22 00:44:21.000000000 +0100 +@@ -0,0 +1,613 @@ ++#include "gunzip.h" ++ ++/* unzip code taken from bios-lt project */ ++/* http://sourceforge.net/projects/bios-lt */ ++/* maintainer Liu Tao */ ++ ++static const ulong crc_32_tab[256] = { ++ 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, ++ 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, ++ 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, ++ 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, ++ 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, ++ 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, ++ 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, ++ 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, ++ 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, ++ 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, ++ 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, ++ 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, ++ 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, ++ 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, ++ 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, ++ 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, ++ 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, ++ 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, ++ 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, ++ 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, ++ 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, ++ 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, ++ 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, ++ 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, ++ 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, ++ 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, ++ 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, ++ 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, ++ 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, ++ 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, ++ 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, ++ 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d ++}; ++ ++static const huft_code mask_bits[] = { ++ 0x0000, ++ 0x0001, 0x0003, 0x0007, 0x000f, 0x001f, 0x003f, 0x007f, 0x00ff, ++ 0x01ff, 0x03ff, 0x07ff, 0x0fff, 0x1fff, 0x3fff, 0x7fff, 0xffff ++}; ++ ++/* Tables for deflate from PKZIP's appnote.txt. */ ++static const unsigned border[] = { /* Order of the bit length code lengths */ ++ 16, 17, 18, 0, 8, 7, 9, 6, 10, 5, 11, 4, 12, 3, 13, 2, 14, 1, 15}; ++ ++static const ushort cplext[] = { /* Extra bits for literal codes 257..285 */ ++ 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, ++ 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 0, 99, 99 ++}; /* 99==invalid */ ++ ++static const ushort cplens[] = { /* Copy lengths for literal codes 257..285 */ ++ 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, 17, 19, 23, 27, 31, ++ 35, 43, 51, 59, 67, 83, 99, 115, 131, 163, 195, 227, 258, 0, 0 ++}; /* note: see note #13 above about the 258 in this list. */ ++ ++static const ushort cpdext[] = { /* Extra bits for distance codes */ ++ 0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, ++ 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13 ++}; ++ ++static const ushort cpdist[] = { /* Copy offsets for distance codes 0..29 */ ++ 1, 2, 3, 4, 5, 7, 9, 13, 17, 25, 33, 49, 65, 97, 129, 193, ++ 257, 385, 513, 769, 1025, 1537, 2049, 3073, 4097, 6145, ++ 8193, 12289, 16385, 24577 ++}; ++ ++static huft_code bit_reverse(huft_code code, huft_bits bits) ++{ ++ huft_code ret = 0; ++ int i; ++ ++ for (i = 0; i < bits; i++) { ++ if (code & (1 << i)) ++ ret |= (1 << (bits - i - 1)); ++ } ++ ++ return ret; ++} ++ ++static huft_code huft_get_code( ++ huft_bits *b, /* code lengths in bits (all assumed <= B_MAX) */ ++ int n, /* number of codes (assumed <= N_MAX) */ ++ int k /* index */ ++ ) ++{ ++ huft_code code = 0; ++ huft_bits bits = b[k]; ++ int i; ++ ++ if (bits == 0) ++ return 0; ++ ++ for (i = 0; i < n; i++) { ++ if (b[i] < bits && b[i] > 0) ++ code += 1 << (b[k] - b[i]); ++ else if ((i < k) && (b[i] == bits)) ++ code += 1; ++ } ++ ++ return bit_reverse(code, bits); ++} ++ ++static int huft_build_table( ++ huft_bits *b, /* code lengths in bits (all assumed <= B_MAX) */ ++ int n, /* number of codes (assumed <= N_MAX) */ ++ huft_code *t /* result: starting table */ ++ ) ++{ ++ int i; ++ ++ for (i = 0; i < n; i++) { ++ t[i] = huft_get_code(b, n, i); ++ } ++ ++ return 0; ++} ++ ++static int huft_get_value( ++ huft_bits *b, /* code lengths in bits (all assumed <= B_MAX) */ ++ huft_code *t, /* huft table */ ++ int n, /* number of codes (assumed <= N_MAX) */ ++ huft_code code, ++ huft_bits *bits ++ ) ++{ ++ int i; ++ ++ for (i = 0; i < n; i++) { ++ if (b[i] == 0) ++ continue; ++ ++ if ((code & ~(0xffff << b[i])) == t[i]) ++ break; ++ } ++ ++ if (i == n) ++ return -1; ++ ++ *bits = b[i]; ++ return i; ++} ++ ++static huft_code peek_bits(gunzip_t *guz, huft_bits n) ++{ ++ huft_code r; ++ ++ while (guz->bufbits < (n)) ++ { ++ guz->bitbuf |= ((ulong)get_uchar(guz)) << guz->bufbits; ++ guz->bufbits += 8; ++ } ++ r = guz->bitbuf & mask_bits[n]; ++ ++ return r; ++} ++ ++static void skip_bits(gunzip_t *guz, huft_bits n) ++{ ++ guz->bitbuf >>= (n); ++ guz->bufbits -= (n); ++} ++ ++static huft_code get_bits(gunzip_t *guz, huft_bits n) ++{ ++ huft_code r; ++ ++ while (guz->bufbits < (n)) ++ { ++ guz->bitbuf |= ((ulong)get_uchar(guz)) << guz->bufbits; ++ guz->bufbits += 8; ++ } ++ r = guz->bitbuf & mask_bits[n]; ++ ++ guz->bitbuf >>= (n); ++ guz->bufbits -= (n); ++ ++ return r; ++} ++ ++static int inflate_codes(gunzip_t *guz, ++ huft_bits *ll, ++ huft_code *tl, /* literal/length decoder tables */ ++ huft_bits *ld, ++ huft_code *td, /* distance decoder tables */ ++ int nl, /* number of bits decoded by tl[] */ ++ int nd /* number of bits decoded by td[] */ ++ ) ++{ ++ register int i, j; ++ register huft_code code; ++ register huft_bits bits; ++ register int value, n; ++ register uchar *outbuf; ++ register ulong outptr; ++ register huft_code codex; ++ huft_bits bits_tmp; ++ huft_code ftl[256], ftlex[512], ftd[256]; ++ int ftnex = 0; ++ int len, dist; ++ ++ outbuf = guz->outbuf; ++ outptr = guz->outptr; ++ ++ for (i = 0; i < 256; i++) { ++ ftl[i] = 0xffff; ++ ftd[i] = 0xffff; ++ } ++ ++ for (i = 0; i < 512; i++) ++ ftlex[i] = 0xffff; ++ ++ for (i = 0; i < nl; i++) { ++ ++ bits = ll[i]; ++ if (bits > 0 && bits <= 8) { ++ code = (ushort)i | (bits << 9); ++ for (j = 0; j < (1 << (8 - bits)); j++) { ++ ftl[tl[i] | (j << bits)] = code; ++ } ++ ++ } else if (bits > 8 && bits < 12 && ftnex < 64) { ++ code = tl[i] & 0xff; ++ if (ftl[code] == 0xffff) { ++ n = (ftnex++) << 3; ++ ftl[code] = 0x8000 | n; ++ } else ++ n = ftl[code] & 0x7fff; ++ ++ code = (ushort)i | (bits << 9); ++ n += tl[i] >> 8; ++ for (j = 0; j < (1 << (11 - bits)); j++) { ++ ftlex[n | (j << (bits - 8))] = code; ++ } ++ } ++ } ++ ++ for (i = 0; i < nd; i++) { ++ bits = ld[i]; ++ code = (ushort)i + (bits << 9); ++ if (bits > 0 && bits <= 8) { ++ for (j = 0; j < (1 << (8 - bits)); j++) { ++ ftd[td[i] | (j << bits)] = code; ++ } ++ } ++ } ++ ++ while (1) { ++ ++ code = peek_bits(guz, 8); ++ ++ if (!(ftl[code] & 0x8000)) { ++ value = ftl[code] & 0x01ff; ++ bits = ftl[code] >> 9; ++ ++ } else if (ftl[code] != 0xffff) { ++ n = ftl[code] & 0x7fff; ++ code = peek_bits(guz, 11); ++ codex = code >> 8; ++ if (ftlex[n + codex] != 0xffff) { ++ value = ftlex[n + codex] & 0x01ff; ++ bits = ftlex[n + codex] >> 9; ++ } else { ++ code = peek_bits(guz, 16); ++ value = huft_get_value(ll, tl, nl, code, &bits_tmp); ++ bits = bits_tmp; ++ if (value == -1) ++ return 1; /* error in compressed data */ ++ } ++ ++ } else { ++ code = peek_bits(guz, 16); ++ value = huft_get_value(ll, tl, nl, code, &bits_tmp); ++ bits = bits_tmp; ++ if (value == -1) ++ return 1; /* error in compressed data */ ++ } ++ skip_bits(guz, bits); ++ ++ if (value < 256) { ++ outbuf[outptr++] = (uchar)value; ++ } else if (value > 256) { ++ code = get_bits(guz, cplext[value - 257]); ++ len = cplens[value - 257] + code; ++ ++ code = peek_bits(guz, 8); ++ if (ftd[code] != 0xffff) { ++ value = ftd[code] & 0x01ff; ++ bits = ftd[code] >> 9; ++ } else { ++ code = peek_bits(guz, 16); ++ value = huft_get_value(ld, td, nd, code, &bits_tmp); ++ bits = bits_tmp; ++ if (value == -1) ++ return 1; /* error in compressed data */ ++ } ++ skip_bits(guz, bits); ++ dist = cpdist[value] + get_bits(guz, cpdext[value]); ++ ++ for (i = 0; i < len; i++) ++ outbuf[outptr++] = outbuf[outptr - dist]; ++ } else { ++ break; ++ } ++ } ++ ++ guz->outbuf = outbuf; ++ guz->outptr = outptr; ++ ++ return 0; ++} ++ ++static int inflate_stored(gunzip_t *guz) ++{ ++ ulong n; /* number of bytes in block */ ++ ++ /* go to byte boundary */ ++ n = guz->bufbits & 7; ++ get_bits(guz, n); ++ ++ /* get the length and its complement */ ++ n = get_bits(guz, 16); ++ if (n != (~get_bits(guz, 16) & 0xffff)) ++ return 1; /* error in compressed data */ ++ ++ /* read and output the compressed data */ ++ while (n--) ++ output_char(guz, (uchar)get_bits(guz, 8)); ++ ++ return 0; ++} ++ ++static int inflate_fixed(gunzip_t *guz) ++{ ++ huft_bits ll[288], ld[32]; ++ huft_code tl[288], td[32]; ++ int i; ++ ++ /* set up literal table */ ++ for (i = 0; i < 144; i++) ++ ll[i] = 8; ++ for (; i < 256; i++) ++ ll[i] = 9; ++ for (; i < 280; i++) ++ ll[i] = 7; ++ for (; i < 288; i++) /* make a complete, but wrong code set */ ++ ll[i] = 8; ++ huft_build_table(ll, 288, tl); ++ ++ for (i = 0; i < 30; i++) ++ ld[i] = 5; ++ huft_build_table(ld, 30, td); ++ ++ return inflate_codes(guz, ll, tl, ld, td, 288, 30); ++ ++} ++ ++static int build_bits_table(gunzip_t *guz, ++ huft_bits *lb, ++ huft_code *tb, ++ int nb, ++ huft_bits *ll, ++ int nl ++ ) ++{ ++ huft_bits bits; ++ huft_code code; ++ int value, i, n; ++ ++ i = 0; ++ while (i < nl) { ++ code = peek_bits(guz, 16); ++ value = huft_get_value(lb, tb, 19, code, &bits); ++ if (value == -1) ++ return 1; /* error in compressed data */ ++ skip_bits(guz, bits); ++ if (value < 16) { ++ ll[i++] = value; ++ } else if (value == 16) { ++ code = get_bits(guz, 2); ++ for (n = 0; n < code + 3; n++) { ++ ll[i++] = ll[i - 1]; ++ } ++ } else if (value == 17) { ++ code = get_bits(guz, 3); ++ for (n = 0; n < code + 3; n++) ++ ll[i++] = 0; ++ } else if (value == 18) { ++ code = get_bits(guz, 7); ++ for (n = 0; n < code + 11; n++) ++ ll[i++] = 0; ++ } ++ } ++ ++ return 0; ++} ++ ++static int inflate_dynamic(gunzip_t *guz) ++{ ++ huft_bits lb[19], ll[288], ld[32]; ++ huft_code tb[19], tl[288], td[32]; ++ int nb; /* number of bit length codes */ ++ int nl; /* number of literal/length codes */ ++ int nd; /* number of distance codes */ ++ int i; ++ ++ /* read in table lengths */ ++ nl = 257 + get_bits(guz, 5); /* number of literal/length codes */ ++ nd = 1 + get_bits(guz, 5); /* number of distance codes */ ++ nb = 4 + get_bits(guz, 4); /* number of bit length codes */ ++ if (nl > 286 || nd > 30) ++ return 1; /* bad lengths */ ++ ++ /* read in bit-length-code lengths */ ++ for (i = 0; i < nb; i++) ++ lb[border[i]] = get_bits(guz, 3); ++ for (; i < 19; i++) ++ lb[border[i]] = 0; ++ huft_build_table(lb, 19, tb); ++ ++ build_bits_table(guz, lb, tb, 19, ll, nl); ++ huft_build_table(ll, nl, tl); ++ ++ build_bits_table(guz, lb, tb, 19, ld, nd); ++ huft_build_table(ld, nd, td); ++ ++ return inflate_codes(guz, ll, tl, ld, td, nl, nd); ++} ++ ++static int inflate_block(gunzip_t *guz, ulong *e) ++{ ++ ulong t; /* block type */ ++ ++ /* read in last block bit */ ++ *e = get_bits(guz, 1); ++ ++ /* read in block type */ ++ t = get_bits(guz, 2); ++ ++ /* inflate that block type */ ++ if (t == 0) ++ return inflate_stored(guz); ++ if (t == 1) ++ return inflate_fixed(guz); ++ if (t == 2) ++ return inflate_dynamic(guz); ++ ++ /* bad block type */ ++ return 2; ++} ++ ++static int inflate(gunzip_t *guz) ++{ ++ ulong e; /* last block flag */ ++ int r; /* result code */ ++ /* unsigned h; maximum struct huft's malloc'ed */ ++ ++ /* decompress until the last block */ ++ do { ++ if ((r = inflate_block(guz, &e)) != 0) { ++ return r; ++ } ++ } while (!e); ++ ++ /* Undo too much lookahead. The next read will be byte aligned so we ++ * can discard unused bits in the last meaningful byte. ++ */ ++ while (guz->bufbits >= 8) { ++ guz->bufbits -= 8; ++ guz->inptr--; ++ } ++ ++ /* return success */ ++ return 0; ++} ++ ++static void init_gunzip_struct(gunzip_t *guz, ++ uchar *inbuf, ulong insize, uchar *outbuf, ulong outsize) ++{ ++ guz->inbuf = inbuf; ++ guz->insize = insize; ++ guz->inptr = 0; ++ ++ guz->outbuf = outbuf; ++ guz->outsize = outsize; ++ guz->outptr = 0; ++ ++ guz->bitbuf = 0; ++ guz->bufbits = 0; ++} ++ ++ulong get_crc(uchar *buf, int len) ++{ ++ ulong crc; ++ uchar ch; ++ int i; ++ ++ crc = 0xffffffffL; ++ for (i = 0; i < len; i++) { ++ ch = buf[i]; ++ crc = crc_32_tab[((int)crc ^ ch) & 0xff] ^ (crc >> 8); ++ } ++ crc = (crc ^ 0xffffffffL); ++ ++ return crc; ++} ++ ++int gunzip(uchar *inbuf, ulong *insize, uchar *outbuf, ulong *outsize) ++{ ++ gunzip_t guz_struct; ++ gunzip_t *guz; ++ uchar magic[2]; /* magic header */ ++ uchar method; ++ uchar flags; ++ ulong orig_crc = 0; /* original crc */ ++ ulong orig_len = 0; /* original uncompressed length */ ++ int res; ++ ++ guz = &guz_struct; ++ init_gunzip_struct(guz, inbuf, *insize, outbuf, *outsize); ++ ++ ++ magic[0] = get_uchar(guz); ++ magic[1] = get_uchar(guz); ++ method = get_uchar(guz); ++ ++ if (magic[0] != 0x1f || magic[1] != 0x8b) ++ return ERR_BADMAGIC; ++ ++ /* We only support method #8, DEFLATED */ ++ if (method != 8) ++ return ERR_BADMETHOD; ++ ++ flags = get_uchar(guz); ++ if (flags & ENCRYPTED) ++ return ERR_ENCRYPTED; ++ ++ if (flags & CONTINUATION) ++ return ERR_MULTIPART; ++ ++ if (flags & RESERVED) ++ return ERR_INVALIDFLAGS; ++ ++ get_ulong(guz); /* Get timestamp */ ++ ++ get_uchar(guz); /* Ignore extra flags for the moment */ ++ get_uchar(guz); /* Ignore OS type for the moment */ ++ ++ if (flags & EXTRA_FIELD) { ++ ushort len; ++ ++ len = get_ushort(guz); ++ while (len--) ++ get_uchar(guz); ++ } ++ ++ /* Get original file name if it was truncated */ ++ if (flags & ORIG_NAME) { ++ /* Discard the old name */ ++ while (get_uchar(guz) != 0); ++ } ++ ++ /* Discard file comment if any */ ++ if (flags & COMMENT) { ++ while (get_uchar(guz) != 0); ++ } ++ ++ /* Decompress */ ++ if ((res = inflate(guz)) != 0) { ++ switch (res) { ++ case 1: ++ /* invalid compressed format (err=1) */ ++ res = ERR_BADFORMAT1; ++ break; ++ case 2: ++ /* invalid compressed format (err=2) */ ++ res = ERR_BADFORMAT2; ++ break; ++ case 3: ++ /* out of memory */ ++ res = ERR_MEM; ++ break; ++ default: ++ /* invalid compressed format (other) */ ++ res = ERR_BADFORMAT; ++ } ++ ++ return res; ++ } ++ /* Get the crc and original length */ ++ /* crc32 (see algorithm.doc) ++ * uncompressed input size modulo 2^32 ++ */ ++ orig_crc = get_ulong(guz); ++ orig_len = get_ulong(guz); ++ ++ /* Validate decompression */ ++// if (orig_crc != get_crc(guz->outbuf, guz->outptr)) ++// return ERR_CRC; ++ ++ if (orig_len != guz->outptr) ++ return ERR_LENGTH; ++ ++ *insize = guz->inptr; ++ *outsize = guz->outptr; ++ ++ return 0; ++} +diff -Nurp ../u-boot-1.1.6/lib_generic/Makefile ./lib_generic/Makefile +--- ../u-boot-1.1.6/lib_generic/Makefile 2006-11-02 15:15:01.000000000 +0100 ++++ ./lib_generic/Makefile 2007-03-25 17:49:13.000000000 +0200 +@@ -28,7 +28,8 @@ LIB = $(obj)libgeneric.a + COBJS = bzlib.o bzlib_crctable.o bzlib_decompress.o \ + bzlib_randtable.o bzlib_huffman.o \ + crc32.o ctype.o display_options.o ldiv.o \ +- string.o vsprintf.o zlib.o ++ string.o vsprintf.o gunzip.o ++# zlib.o gunzip.o + + SRCS := $(COBJS:.o=.c) + OBJS := $(addprefix $(obj),$(COBJS)) +Pliki ../u-boot-1.1.6/loader-sarge i ./loader-sarge różniÄ… siÄ™ +diff -Nurp ../u-boot-1.1.6/Makefile ./Makefile +--- ../u-boot-1.1.6/Makefile 2006-11-02 15:15:01.000000000 +0100 ++++ ./Makefile 2007-03-29 20:07:54.000000000 +0200 +@@ -1882,6 +1882,9 @@ smdk2410_config : unconfig + SX1_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm925t sx1 + ++sarge_config : unconfig ++ @$(MKCONFIG) $(@:_config=) arm arm920t sarge NULL at91rm9200 ++ + # TRAB default configuration: 8 MB Flash, 32 MB RAM + trab_config \ + trab_bigram_config \ +diff -Nurp ../u-boot-1.1.6/net/bootp.c ./net/bootp.c +--- ../u-boot-1.1.6/net/bootp.c 2006-11-02 15:15:01.000000000 +0100 ++++ ./net/bootp.c 2007-05-09 23:46:31.000000000 +0200 +@@ -35,7 +35,7 @@ + + #define TIMEOUT 5 /* Seconds before trying BOOTP again */ + #ifndef CONFIG_NET_RETRY_COUNT +-# define TIMEOUT_COUNT 5 /* # of timeouts before giving up */ ++# define TIMEOUT_COUNT 10 /* # of timeouts before giving up */ + #else + # define TIMEOUT_COUNT (CONFIG_NET_RETRY_COUNT) + #endif +diff -Nurp ../u-boot-1.1.6/net/eth.c ./net/eth.c +--- ../u-boot-1.1.6/net/eth.c 2006-11-02 15:15:01.000000000 +0100 ++++ ./net/eth.c 2007-05-09 23:47:19.000000000 +0200 +@@ -397,10 +397,10 @@ int eth_send(volatile void *packet, int + } + + int eth_rx(void) +-{ ++{ + if (!eth_current) + return -1; +- ++ + return eth_current->recv(eth_current); + } + +diff -Nurp ../u-boot-1.1.6/net/Makefile ./net/Makefile +--- ../u-boot-1.1.6/net/Makefile 2006-11-02 15:15:01.000000000 +0100 ++++ ./net/Makefile 2007-05-09 23:52:55.000000000 +0200 +@@ -23,7 +23,7 @@ + + include $(TOPDIR)/config.mk + +-# CFLAGS += -DET_DEBUG -DDEBUG ++#CFLAGS += -DET_DEBUG -DDEBUG -DDEBUG_BOOTP_EXT + + LIB = $(obj)libnet.a + +diff -Nurp ../u-boot-1.1.6/net/net.c ./net/net.c +--- ../u-boot-1.1.6/net/net.c 2006-11-02 15:15:01.000000000 +0100 ++++ ./net/net.c 2007-05-09 23:47:40.000000000 +0200 +@@ -78,6 +78,7 @@ + #include + #include + #include ++#include + #include "bootp.h" + #include "tftp.h" + #include "rarp.h" +@@ -1745,7 +1746,23 @@ void print_IPaddr (IPaddr_t x) + + IPaddr_t getenv_IPaddr (char *var) + { +- return (string_to_ip(getenv(var))); ++ /* new code changed by Yu Lu , ++ to solve the problem of ++ mess up the ip addr from environment variables */ ++ char tmp_str[64]; ++ // printf("DebugLY1: \n\r"); ++ //puts(getenv(var)); ++ ++ strcpy(tmp_str, getenv(var) ); ++ if(isxdigit(*tmp_str)) ++ return (string_to_ip( tmp_str )); ++ else ++ return (string_to_ip( tmp_str+1 )); ++ //return (string_to_ip(getenv(var)+1)); ++ /* old code is the below */ ++ // return (string_to_ip(getenv(var))); ++ ++ //return (string_to_ip(getenv(var))); + } + + ushort getenv_VLAN(char *var) diff --git a/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-83xx-optimizations.patch b/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-83xx-optimizations.patch new file mode 100644 index 0000000000..fe85228771 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-83xx-optimizations.patch @@ -0,0 +1,89 @@ +diff --exclude CVS -uNr u-boot-1.1.6/cpu/mpc83xx/cpu_init.c u-boot-1.1.6.modified/cpu/mpc83xx/cpu_init.c +--- u-boot-1.1.6/cpu/mpc83xx/cpu_init.c 2007-04-10 17:43:16.000000000 -0400 ++++ u-boot-1.1.6.modified/cpu/mpc83xx/cpu_init.c 2007-04-10 17:31:51.000000000 -0400 +@@ -66,10 +66,30 @@ + memset ((void *) gd, 0, sizeof (gd_t)); + + /* system performance tweaking */ ++ /* System Priority Configuration Register (SPCR) */ ++#ifdef CFG_SPCR_PCIHPE ++ /* PCI highest priority enable */ ++ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_PCIHPE) | (CFG_SPCR_PCIHPE << SPCR_PCIHPE_SHIFT); ++#endif + +-#ifdef CFG_ACR_PIPE_DEP +- /* Arbiter pipeline depth */ +- im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (3 << ACR_PIPE_DEP_SHIFT); ++#ifdef CFG_SPCR_PCIPR ++ /* PCI bridge CSB request priority */ ++ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_PCIPR) | (CFG_SPCR_PCIPR << SPCR_PCIPR_SHIFT); ++#endif ++ ++#ifdef CFG_SPCR_OPT ++ /* Optimize transactions between CSB and other devices */ ++ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) | (CFG_SPCR_OPT << SPCR_OPT_SHIFT); ++#endif ++ ++#ifdef CFG_SPCR_TBEN ++ /* e300 time base unit enable */ ++ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TBEN) | (CFG_SPCR_TBEN << SPCR_TBEN_SHIFT); ++#endif ++ ++#ifdef CFG_SPCR_COREPR ++ /* e300 core CSB request priority */ ++ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_COREPR) | (CFG_SPCR_COREPR << SPCR_COREPR_SHIFT); + #endif + + #ifdef CFG_SPCR_TSEC1EP +@@ -82,6 +102,7 @@ + im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (3 << SPCR_TSEC2EP_SHIFT); + #endif + ++ /* System Clock Control Register (SCCR) */ + #ifdef CFG_SCCR_TSEC1CM + /* TSEC1 clock mode */ + im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (1 << SCCR_TSEC1CM_SHIFT); +@@ -91,6 +112,12 @@ + im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (1 << SCCR_TSEC2CM_SHIFT); + #endif + ++ /* Arbiter Control Register (ACR) */ ++#ifdef CFG_ACR_PIPE_DEP ++ /* Arbiter pipeline depth */ ++ im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (3 << ACR_PIPE_DEP_SHIFT); ++#endif ++ + #ifdef CFG_ACR_RPTCNT + /* Arbiter repeat count */ + im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (3 << ACR_RPTCNT_SHIFT)); +diff --exclude CVS -uNr u-boot-1.1.6/include/configs/MPC8323ERDB.h u-boot-1.1.6.modified/include/configs/MPC8323ERDB.h +--- u-boot-1.1.6/include/configs/MPC8323ERDB.h 2007-04-10 17:43:16.000000000 -0400 ++++ u-boot-1.1.6.modified/include/configs/MPC8323ERDB.h 2007-04-10 17:32:03.000000000 -0400 +@@ -63,6 +63,16 @@ + HRCWH_BIG_ENDIAN |\ + HRCWH_LALE_NORMAL) + ++/* System performance */ ++#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ ++#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ ++#define CFG_SPCR_PCIHPE 0 /* (0-1) PCI highest priority enable */ ++#define CFG_SPCR_PCIPR 0 /* (0-3) PCI bridge CSB request priority */ ++#define CFG_SPCR_OPT 1 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */ ++#define CFG_SPCR_TBEN 1 /* (0-1) e300 time base unit enable */ ++#define CFG_SPCR_COREPR 0 /* (0-3) e300 core CSB request priority */ ++ ++ + /* + * System IO Config + */ +diff --exclude CVS -uNr u-boot-1.1.6/include/mpc83xx.h u-boot-1.1.6.modified/include/mpc83xx.h +--- u-boot-1.1.6/include/mpc83xx.h 2007-04-10 17:43:16.000000000 -0400 ++++ u-boot-1.1.6.modified/include/mpc83xx.h 2007-04-10 17:32:15.000000000 -0400 +@@ -91,6 +91,7 @@ + #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ + #define SPCR_PCIPR_SHIFT (31-7) + #define SPCR_OPT 0x00800000 /* Optimize */ ++#define SPCR_OPT_SHIFT (31-8) + #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ + #define SPCR_TBEN_SHIFT (31-9) + #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ diff --git a/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Add-support-for-the-MPC832XEMDS-board.patch b/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Add-support-for-the-MPC832XEMDS-board.patch new file mode 100644 index 0000000000..5018cd3434 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Add-support-for-the-MPC832XEMDS-board.patch @@ -0,0 +1,1809 @@ +fe298a1bbd7b9526ca1139da8977e1a076c4e176 +diff --git a/Makefile b/Makefile +index d2534ab..d172411 100644 +--- a/Makefile ++++ b/Makefile +@@ -1621,6 +1621,30 @@ MPC8360EMDS_SLAVE_config: unconfig + MPC8349ITX_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349itx + ++MPC832XEMDS_config \ ++MPC832XEMDS_HOST_33_config \ ++MPC832XEMDS_HOST_66_config \ ++MPC832XEMDS_SLAVE_config: unconfig ++ @echo "" >include/config.h ; \ ++ if [ "$(findstring _HOST_,$@)" ] ; then \ ++ echo -n "... PCI HOST " ; \ ++ echo "#define CONFIG_PCI" >>include/config.h ; \ ++ fi ; \ ++ if [ "$(findstring _SLAVE_,$@)" ] ; then \ ++ echo "...PCI SLAVE 66M" ; \ ++ echo "#define CONFIG_PCI" >>include/config.h ; \ ++ echo "#define CONFIG_PCISLAVE" >>include/config.h ; \ ++ fi ; \ ++ if [ "$(findstring _33_,$@)" ] ; then \ ++ echo -n "...33M ..." ; \ ++ echo "#define PCI_33M" >>include/config.h ; \ ++ fi ; \ ++ if [ "$(findstring _66_,$@)" ] ; then \ ++ echo -n "...66M..." ; \ ++ echo "#define PCI_66M" >>include/config.h ; \ ++ fi ; ++ @$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds ++ + ######################################################################### + ## MPC85xx Systems + ######################################################################### +diff --git a/board/mpc832xemds/Makefile b/board/mpc832xemds/Makefile +new file mode 100644 +index 0000000..5ec7a87 +--- /dev/null ++++ b/board/mpc832xemds/Makefile +@@ -0,0 +1,50 @@ ++# ++# (C) Copyright 2006 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).a ++ ++COBJS := $(BOARD).o pci.o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) ++ $(AR) $(ARFLAGS) $@ $(OBJS) ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak .depend ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +diff --git a/board/mpc832xemds/config.mk b/board/mpc832xemds/config.mk +new file mode 100644 +index 0000000..6c3eca7 +--- /dev/null ++++ b/board/mpc832xemds/config.mk +@@ -0,0 +1,28 @@ ++# ++# (C) Copyright 2006 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++# ++# MPC832XEMDS ++# ++ ++TEXT_BASE = 0xFE000000 +diff --git a/board/mpc832xemds/mpc832xemds.c b/board/mpc832xemds/mpc832xemds.c +new file mode 100644 +index 0000000..772da67 +--- /dev/null ++++ b/board/mpc832xemds/mpc832xemds.c +@@ -0,0 +1,176 @@ ++/* ++ * Copyright (C) 2006 Freescale Semiconductor, Inc. ++ * ++ * Dave Liu ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if defined(CONFIG_PCI) ++#include ++#endif ++#if defined(CONFIG_SPD_EEPROM) ++#include ++#else ++#include ++#endif ++#if defined(CONFIG_OF_FLAT_TREE) ++#include ++#endif ++ ++const qe_iop_conf_t qe_iop_conf_tab[] = { ++ /* ETH3 */ ++ {1, 0, 1, 0, 1}, /* TxD0 */ ++ {1, 1, 1, 0, 1}, /* TxD1 */ ++ {1, 2, 1, 0, 1}, /* TxD2 */ ++ {1, 3, 1, 0, 1}, /* TxD3 */ ++ {1, 9, 1, 0, 1}, /* TxER */ ++ {1, 12, 1, 0, 1}, /* TxEN */ ++ {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ ++ ++ {1, 4, 2, 0, 1}, /* RxD0 */ ++ {1, 5, 2, 0, 1}, /* RxD1 */ ++ {1, 6, 2, 0, 1}, /* RxD2 */ ++ {1, 7, 2, 0, 1}, /* RxD3 */ ++ {1, 8, 2, 0, 1}, /* RxER */ ++ {1, 10, 2, 0, 1}, /* RxDV */ ++ {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ ++ {1, 11, 2, 0, 1}, /* COL */ ++ {1, 13, 2, 0, 1}, /* CRS */ ++ ++ /* ETH4 */ ++ {1, 18, 1, 0, 1}, /* TxD0 */ ++ {1, 19, 1, 0, 1}, /* TxD1 */ ++ {1, 20, 1, 0, 1}, /* TxD2 */ ++ {1, 21, 1, 0, 1}, /* TxD3 */ ++ {1, 27, 1, 0, 1}, /* TxER */ ++ {1, 30, 1, 0, 1}, /* TxEN */ ++ {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */ ++ ++ {1, 22, 2, 0, 1}, /* RxD0 */ ++ {1, 23, 2, 0, 1}, /* RxD1 */ ++ {1, 24, 2, 0, 1}, /* RxD2 */ ++ {1, 25, 2, 0, 1}, /* RxD3 */ ++ {1, 26, 1, 0, 1}, /* RxER */ ++ {1, 28, 2, 0, 1}, /* Rx_DV */ ++ {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */ ++ {1, 29, 2, 0, 1}, /* COL */ ++ {1, 31, 2, 0, 1}, /* CRS */ ++ ++ {3, 4, 3, 0, 2}, /* MDIO */ ++ {3, 5, 1, 0, 2}, /* MDC */ ++ ++ {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ ++}; ++ ++int board_early_init_f(void) ++{ ++ volatile u8 *bcsr = (volatile u8 *)CFG_BCSR; ++ ++ /* Enable flash write */ ++ bcsr[9] &= ~0x08; ++ ++ return 0; ++} ++ ++int fixed_sdram(void); ++ ++long int initdram(int board_type) ++{ ++ volatile immap_t *im = (immap_t *) CFG_IMMR; ++ u32 msize = 0; ++ ++ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) ++ return -1; ++ ++ /* DDR SDRAM - Main SODIMM */ ++ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; ++ ++ msize = fixed_sdram(); ++ ++ puts("\n DDR RAM: "); ++ ++ /* return total bus SDRAM size(bytes) -- DDR */ ++ return (msize * 1024 * 1024); ++} ++ ++/************************************************************************* ++ * fixed sdram init -- doesn't use serial presence detect. ++ ************************************************************************/ ++int fixed_sdram(void) ++{ ++ volatile immap_t *im = (immap_t *) CFG_IMMR; ++ u32 msize = 0; ++ u32 ddr_size; ++ u32 ddr_size_log2; ++ ++ msize = CFG_DDR_SIZE; ++ for (ddr_size = msize << 20, ddr_size_log2 = 0; ++ (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { ++ if (ddr_size & 1) { ++ return -1; ++ } ++ } ++ im->sysconf.ddrlaw[0].ar = ++ LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); ++#if (CFG_DDR_SIZE != 128) ++#warning Currenly any ddr size other than 128 is not supported ++#endif ++ im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; ++ im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; ++ im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; ++ im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; ++ im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; ++ im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; ++ im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; ++ im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; ++ im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; ++ im->ddr.sdram_mode = CFG_DDR_MODE; ++ im->ddr.sdram_mode2 = CFG_DDR_MODE2; ++ im->ddr.sdram_interval = CFG_DDR_INTERVAL; ++ __asm__ __volatile__ ("sync"); ++ udelay(200); ++ ++ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; ++ __asm__ __volatile__ ("sync"); ++ return msize; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: Freescale MPC832XEMDS\n"); ++ return 0; ++} ++ ++#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) ++void ++ft_board_setup(void *blob, bd_t *bd) ++{ ++ u32 *p; ++ int len; ++ ++#ifdef CONFIG_PCI ++ ft_pci_setup(blob, bd); ++#endif ++ ft_cpu_setup(blob, bd); ++ ++ p = ft_get_prop(blob, "/memory/reg", &len); ++ if (p != NULL) { ++ *p++ = cpu_to_be32(bd->bi_memstart); ++ *p = cpu_to_be32(bd->bi_memsize); ++ } ++} ++#endif +diff --git a/board/mpc832xemds/pci.c b/board/mpc832xemds/pci.c +new file mode 100644 +index 0000000..09f3ac3 +--- /dev/null ++++ b/board/mpc832xemds/pci.c +@@ -0,0 +1,313 @@ ++/* ++ * Copyright (C) 2006 Freescale Semiconductor, Inc. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++/* ++ * PCI Configuration space access support for MPC83xx PCI Bridge ++ */ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#if defined(CONFIG_PCI) ++#define PCI_FUNCTION_CONFIG 0x44 ++#define PCI_FUNCTION_CFG_LOCK 0x20 ++ ++/* ++ * Initialize PCI Devices, report devices found ++ */ ++#ifndef CONFIG_PCI_PNP ++static struct pci_config_table pci_mpc83xxemds_config_table[] = { ++ { ++ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, ++ pci_cfgfunc_config_device, ++ {PCI_ENET0_IOADDR, ++ PCI_ENET0_MEMADDR, ++ PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} ++ }, ++ {} ++} ++#endif ++static struct pci_controller hose[] = { ++ { ++#ifndef CONFIG_PCI_PNP ++ config_table:pci_mpc83xxemds_config_table, ++#endif ++ }, ++}; ++ ++/********************************************************************** ++ * pci_init_board() ++ *********************************************************************/ ++void pci_init_board(void) ++#ifdef CONFIG_PCISLAVE ++{ ++ u16 reg16; ++ volatile immap_t *immr; ++ volatile law83xx_t *pci_law; ++ volatile pot83xx_t *pci_pot; ++ volatile pcictrl83xx_t *pci_ctrl; ++ volatile pciconf83xx_t *pci_conf; ++ ++ immr = (immap_t *) CFG_IMMR; ++ pci_law = immr->sysconf.pcilaw; ++ pci_pot = immr->ios.pot; ++ pci_ctrl = immr->pci_ctrl; ++ pci_conf = immr->pci_conf; ++ /* ++ * Configure PCI Inbound Translation Windows ++ */ ++ pci_ctrl[0].pitar0 = 0x0; ++ pci_ctrl[0].pibar0 = 0x0; ++ pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP | ++ PIWAR_WTT_SNOOP | PIWAR_IWS_4K; ++ ++ pci_ctrl[0].pitar1 = 0x0; ++ pci_ctrl[0].pibar1 = 0x0; ++ pci_ctrl[0].piebar1 = 0x0; ++ pci_ctrl[0].piwar1 &= ~PIWAR_EN; ++ ++ pci_ctrl[0].pitar2 = 0x0; ++ pci_ctrl[0].pibar2 = 0x0; ++ pci_ctrl[0].piebar2 = 0x0; ++ pci_ctrl[0].piwar2 &= ~PIWAR_EN; ++ ++ hose[0].first_busno = 0; ++ hose[0].last_busno = 0xff; ++ pci_setup_indirect(&hose[0], ++ (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); ++ reg16 = 0xff; ++ ++ pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), ++ PCI_COMMAND, ®16); ++ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY; ++ pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), ++ PCI_COMMAND, reg16); ++ ++ /* ++ * Clear non-reserved bits in status register. ++ */ ++ pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), ++ PCI_STATUS, 0xffff); ++ pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0), ++ PCI_LATENCY_TIMER, 0x80); ++ ++ /* ++ * Unlock configuration lock in PCI function configuration register. ++ */ ++ pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), ++ PCI_FUNCTION_CONFIG, ®16); ++ reg16 &= ~(PCI_FUNCTION_CFG_LOCK); ++ pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), ++ PCI_FUNCTION_CONFIG, reg16); ++ ++ printf("Enabled PCI 32bit Agent Mode\n"); ++} ++#else ++{ ++ volatile immap_t *immr; ++ volatile clk83xx_t *clk; ++ volatile law83xx_t *pci_law; ++ volatile pot83xx_t *pci_pot; ++ volatile pcictrl83xx_t *pci_ctrl; ++ volatile pciconf83xx_t *pci_conf; ++ ++ u8 val8, orig_i2c_bus; ++ u16 reg16; ++ u32 val32; ++ u32 dev; ++ ++ immr = (immap_t *) CFG_IMMR; ++ clk = (clk83xx_t *) & immr->clk; ++ pci_law = immr->sysconf.pcilaw; ++ pci_pot = immr->ios.pot; ++ pci_ctrl = immr->pci_ctrl; ++ pci_conf = immr->pci_conf; ++ /* ++ * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode ++ */ ++ val32 = clk->occr; ++ udelay(2000); ++#if defined(PCI_66M) ++ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; ++ printf("PCI clock is 66MHz\n"); ++#elif defined(PCI_33M) ++ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | ++ OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; ++ printf("PCI clock is 33MHz\n"); ++#else ++ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; ++ printf("PCI clock is 66MHz\n"); ++#endif ++ udelay(2000); ++ ++ /* ++ * Configure PCI Local Access Windows ++ */ ++ pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; ++ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; ++ ++ pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; ++ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; ++ ++ /* ++ * Configure PCI Outbound Translation Windows ++ */ ++ ++ /* PCI mem space - prefetch */ ++ pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; ++ pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; ++ pci_pot[0].pocmr = ++ POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK); ++ ++ /* PCI mmio - non-prefetch mem space */ ++ pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; ++ pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; ++ pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); ++ ++ /* PCI IO space */ ++ pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK; ++ pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; ++ pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); ++ ++ /* ++ * Configure PCI Inbound Translation Windows ++ */ ++ pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; ++ pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; ++ pci_ctrl[0].piebar1 = 0x0; ++ pci_ctrl[0].piwar1 = ++ PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | ++ PIWAR_IWS_2G; ++ ++ /* ++ * Assign PIB PMC slot to desired PCI bus ++ */ ++ ++ /* Switch temporarily to I2C bus #2 */ ++ orig_i2c_bus = i2c_get_bus_num(); ++ i2c_set_bus_num(1); ++ ++ val8 = 0; ++ i2c_write(0x23, 0x6, 1, &val8, 1); ++ i2c_write(0x23, 0x7, 1, &val8, 1); ++ val8 = 0xff; ++ i2c_write(0x23, 0x2, 1, &val8, 1); ++ i2c_write(0x23, 0x3, 1, &val8, 1); ++ ++ val8 = 0; ++ i2c_write(0x26, 0x6, 1, &val8, 1); ++ val8 = 0x34; ++ i2c_write(0x26, 0x7, 1, &val8, 1); ++ ++ val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */ ++ i2c_write(0x26, 0x2, 1, &val8, 1); ++ val8 = 0xff; ++ i2c_write(0x26, 0x3, 1, &val8, 1); ++ ++ val8 = 0; ++ i2c_write(0x27, 0x6, 1, &val8, 1); ++ i2c_write(0x27, 0x7, 1, &val8, 1); ++ val8 = 0xff; ++ i2c_write(0x27, 0x2, 1, &val8, 1); ++ val8 = 0xef; ++ i2c_write(0x27, 0x3, 1, &val8, 1); ++ asm("eieio"); ++ ++ /* Reset to original I2C bus */ ++ i2c_set_bus_num(orig_i2c_bus); ++ ++ /* ++ * Release PCI RST Output signal ++ */ ++ udelay(2000); ++ pci_ctrl[0].gcr = 1; ++ udelay(2000); ++ ++ hose[0].first_busno = 0; ++ hose[0].last_busno = 0xff; ++ ++ /* PCI memory prefetch space */ ++ pci_set_region(hose[0].regions + 0, ++ CFG_PCI_MEM_BASE, ++ CFG_PCI_MEM_PHYS, ++ CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); ++ ++ /* PCI memory space */ ++ pci_set_region(hose[0].regions + 1, ++ CFG_PCI_MMIO_BASE, ++ CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM); ++ ++ /* PCI IO space */ ++ pci_set_region(hose[0].regions + 2, ++ CFG_PCI_IO_BASE, ++ CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); ++ ++ /* System memory space */ ++ pci_set_region(hose[0].regions + 3, ++ CFG_PCI_SLV_MEM_LOCAL, ++ CFG_PCI_SLV_MEM_BUS, ++ CFG_PCI_SLV_MEM_SIZE, ++ PCI_REGION_MEM | PCI_REGION_MEMORY); ++ ++ hose[0].region_count = 4; ++ ++ pci_setup_indirect(&hose[0], ++ (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); ++ ++ pci_register_hose(hose); ++ ++ /* ++ * Write command register ++ */ ++ reg16 = 0xff; ++ dev = PCI_BDF(0, 0, 0); ++ pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16); ++ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; ++ pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16); ++ ++ /* ++ * Clear non-reserved bits in status register. ++ */ ++ pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff); ++ pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); ++ pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); ++ ++ printf("PCI 32bit bus on PMC2 & PMC3\n"); ++ ++ /* ++ * Hose scan. ++ */ ++ hose->last_busno = pci_hose_scan(hose); ++} ++#endif /* CONFIG_PCISLAVE */ ++ ++#ifdef CONFIG_OF_FLAT_TREE ++void ++ft_pci_setup(void *blob, bd_t *bd) ++{ ++ u32 *p; ++ int len; ++ ++ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); ++ if (p != NULL) { ++ p[0] = hose[0].first_busno; ++ p[1] = hose[0].last_busno; ++ } ++} ++#endif /* CONFIG_OF_FLAT_TREE */ ++#endif /* CONFIG_PCI */ +diff --git a/board/mpc832xemds/u-boot.lds b/board/mpc832xemds/u-boot.lds +new file mode 100644 +index 0000000..937c87a +--- /dev/null ++++ b/board/mpc832xemds/u-boot.lds +@@ -0,0 +1,123 @@ ++/* ++ * (C) Copyright 2006 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_ARCH(powerpc) ++SECTIONS ++{ ++ /* Read-only sections, merged into text segment: */ ++ . = + SIZEOF_HEADERS; ++ .interp : { *(.interp) } ++ .hash : { *(.hash) } ++ .dynsym : { *(.dynsym) } ++ .dynstr : { *(.dynstr) } ++ .rel.text : { *(.rel.text) } ++ .rela.text : { *(.rela.text) } ++ .rel.data : { *(.rel.data) } ++ .rela.data : { *(.rela.data) } ++ .rel.rodata : { *(.rel.rodata) } ++ .rela.rodata : { *(.rela.rodata) } ++ .rel.got : { *(.rel.got) } ++ .rela.got : { *(.rela.got) } ++ .rel.ctors : { *(.rel.ctors) } ++ .rela.ctors : { *(.rela.ctors) } ++ .rel.dtors : { *(.rel.dtors) } ++ .rela.dtors : { *(.rela.dtors) } ++ .rel.bss : { *(.rel.bss) } ++ .rela.bss : { *(.rela.bss) } ++ .rel.plt : { *(.rel.plt) } ++ .rela.plt : { *(.rela.plt) } ++ .init : { *(.init) } ++ .plt : { *(.plt) } ++ .text : ++ { ++ cpu/mpc83xx/start.o (.text) ++ *(.text) ++ *(.fixup) ++ *(.got1) ++ . = ALIGN(16); ++ *(.rodata) ++ *(.rodata1) ++ *(.rodata.str1.4) ++ *(.eh_frame) ++ } ++ .fini : { *(.fini) } =0 ++ .ctors : { *(.ctors) } ++ .dtors : { *(.dtors) } ++ ++ /* Read-write section, merged into data segment: */ ++ . = (. + 0x0FFF) & 0xFFFFF000; ++ _erotext = .; ++ PROVIDE (erotext = .); ++ .reloc : ++ { ++ *(.got) ++ _GOT2_TABLE_ = .; ++ *(.got2) ++ _FIXUP_TABLE_ = .; ++ *(.fixup) ++ } ++ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; ++ __fixup_entries = (. - _FIXUP_TABLE_) >> 2; ++ ++ .data : ++ { ++ *(.data) ++ *(.data1) ++ *(.sdata) ++ *(.sdata2) ++ *(.dynamic) ++ CONSTRUCTORS ++ } ++ _edata = .; ++ PROVIDE (edata = .); ++ ++ . = .; ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ ++ . = .; ++ __start___ex_table = .; ++ __ex_table : { *(__ex_table) } ++ __stop___ex_table = .; ++ ++ . = ALIGN(4096); ++ __init_begin = .; ++ .text.init : { *(.text.init) } ++ .data.init : { *(.data.init) } ++ . = ALIGN(4096); ++ __init_end = .; ++ ++ __bss_start = .; ++ .bss : ++ { ++ *(.sbss) *(.scommon) ++ *(.dynbss) ++ *(.bss) ++ *(COMMON) ++ } ++ _end = . ; ++ PROVIDE (end = .); ++} ++ENTRY(_start) +diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c +index 1b51078..bc61219 100644 +--- a/cpu/mpc83xx/cpu.c ++++ b/cpu/mpc83xx/cpu.c +@@ -92,6 +92,22 @@ int checkcpu(void) + case SPR_8360_REV12: + puts("MPC8360, "); + break; ++ case SPR_8323E_REV10: ++ case SPR_8323E_REV11: ++ puts("MPC8323E, "); ++ break; ++ case SPR_8323_REV10: ++ case SPR_8323_REV11: ++ puts("MPC8323, "); ++ break; ++ case SPR_8321E_REV10: ++ case SPR_8321E_REV11: ++ puts("MPC8321E, "); ++ break; ++ case SPR_8321_REV10: ++ case SPR_8321_REV11: ++ puts("MPC8321, "); ++ break; + default: + puts("Rev: Unknown\n"); + return -1; /* Not sure what this is */ +diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c +index 7574fab..eb256e5 100644 +--- a/cpu/mpc83xx/cpu_init.c ++++ b/cpu/mpc83xx/cpu_init.c +@@ -119,6 +119,11 @@ void cpu_init_f (volatile immap_t * im) + #ifdef CFG_SICRL + im->sysconf.sicrl = CFG_SICRL; + #endif ++ /* DDR control driver register */ ++#ifdef CFG_DDRCDR ++ im->sysconf.ddrcdr = CFG_DDRCDR; ++#endif ++ + #ifdef CONFIG_QE + /* Config QE ioports */ + config_qe_ioports(); +diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c +index 40ba6b0..9fd1bf1 100644 +--- a/cpu/mpc83xx/speed.c ++++ b/cpu/mpc83xx/speed.c +@@ -107,15 +107,19 @@ int get_clocks(void) + #endif + u32 core_clk; + u32 i2c1_clk; ++#if !defined(CONFIG_MPC832X) + u32 i2c2_clk; ++#endif + u32 enc_clk; + u32 lbiu_clk; + u32 lclk_clk; + u32 ddr_clk; +-#if defined (CONFIG_MPC8360) ++#if defined(CONFIG_MPC8360) ++ u32 ddr_sec_clk; ++#endif ++#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) + u32 qepmf; + u32 qepdf; +- u32 ddr_sec_clk; + u32 qe_clk; + u32 brg_clk; + #endif +@@ -227,10 +231,12 @@ int get_clocks(void) + return -9; + } + #endif +-#if defined (CONFIG_MPC8360) ++#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) + i2c1_clk = csb_clk; + #endif ++#if !defined(CONFIG_MPC832X) + i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ ++#endif + + switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { + case 0: +@@ -249,12 +255,9 @@ int get_clocks(void) + /* unkown SCCR_ENCCM value */ + return -6; + } +-#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360) ++ + lbiu_clk = csb_clk * + (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); +-#else +-#error Unknown MPC83xx chip +-#endif + lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT; + switch (lcrr) { + case 2: +@@ -266,17 +269,14 @@ int get_clocks(void) + /* unknown lcrr */ + return -10; + } +-#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360) ++ + ddr_clk = csb_clk * + (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT)); + corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT; +-#if defined (CONFIG_MPC8360) ++#if defined(CONFIG_MPC8360) + ddr_sec_clk = csb_clk * (1 + + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); + #endif +-#else +-#error Unknown MPC83xx chip +-#endif + + corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5); + if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) { +@@ -306,7 +306,7 @@ int get_clocks(void) + return -12; + } + +-#if defined (CONFIG_MPC8360) ++#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) + qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT; + qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT; + qe_clk = (pci_sync_in * qepmf) / (1 + qepdf); +@@ -322,13 +322,17 @@ int get_clocks(void) + #endif + gd->core_clk = core_clk; + gd->i2c1_clk = i2c1_clk; ++#if !defined(CONFIG_MPC832X) + gd->i2c2_clk = i2c2_clk; ++#endif + gd->enc_clk = enc_clk; + gd->lbiu_clk = lbiu_clk; + gd->lclk_clk = lclk_clk; + gd->ddr_clk = ddr_clk; +-#if defined (CONFIG_MPC8360) ++#if defined(CONFIG_MPC8360) + gd->ddr_sec_clk = ddr_sec_clk; ++#endif ++#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) + gd->qe_clk = qe_clk; + gd->brg_clk = brg_clk; + #endif +@@ -352,18 +356,21 @@ int print_clock_conf(void) + printf("Clock configuration:\n"); + printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000); + printf(" Core: %4d MHz\n", gd->core_clk / 1000000); +-#if defined (CONFIG_MPC8360) ++#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) + printf(" QE: %4d MHz\n", gd->qe_clk / 1000000); ++ printf(" BRG: %4d MHz\n", gd->brg_clk / 1000000); + #endif + printf(" Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000); + printf(" Local Bus: %4d MHz\n", gd->lclk_clk / 1000000); + printf(" DDR: %4d MHz\n", gd->ddr_clk / 1000000); +-#if defined (CONFIG_MPC8360) ++#if defined(CONFIG_MPC8360) + printf(" DDR Secondary: %4d MHz\n", gd->ddr_sec_clk / 1000000); + #endif + printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000); + printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000); ++#if !defined(CONFIG_MPC832X) + printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000); ++#endif + #if defined(CONFIG_MPC8349) + printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000); + printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000); +diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h +index f7f8ed0..0bcd0a9 100644 +--- a/drivers/qe/qe.h ++++ b/drivers/qe/qe.h +@@ -30,7 +30,7 @@ + #define UCC_MAX_NUM 8 + + #define QE_DATAONLY_BASE (uint)(128) +-#define QE_DATAONLY_SIZE ((uint)(0xc000) - QE_DATAONLY_BASE) ++#define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE) + + /* QE threads SNUM + */ +diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c +index c44a5be..aea455b 100644 +--- a/drivers/qe/uec.c ++++ b/drivers/qe/uec.c +@@ -432,7 +432,12 @@ static int init_phy(struct eth_device *dev) + } + memset(mii_info, 0, sizeof(*mii_info)); + +- mii_info->speed = SPEED_1000; ++ if (uec->uec_info->uf_info.eth_type == GIGA_ETH) { ++ mii_info->speed = SPEED_1000; ++ } else { ++ mii_info->speed = SPEED_100; ++ } ++ + mii_info->duplex = DUPLEX_FULL; + mii_info->pause = 0; + mii_info->link = 1; +@@ -508,7 +513,8 @@ static void adjust_link(struct eth_device *dev) + } + + if (mii_info->speed != uec->oldspeed) { +- switch (mii_info->speed) { ++ if (uec->uec_info->uf_info.eth_type == GIGA_ETH) { ++ switch (mii_info->speed) { + case 1000: + break; + case 100: +@@ -531,6 +537,7 @@ static void adjust_link(struct eth_device *dev) + printf("%s: Ack,Speed(%d)is illegal\n", + dev->name, mii_info->speed); + break; ++ } + } + + printf("%s: Speed %dBT\n", dev->name, mii_info->speed); +diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h +index 79dcae4..ff9512f 100644 +--- a/include/asm-ppc/e300.h ++++ b/include/asm-ppc/e300.h +@@ -15,6 +15,11 @@ + #define PVR_8360_REV10 (PVR_83xx | 0x0020) + #define PVR_8360_REV11 (PVR_83xx | 0x0020) + ++#if defined(CONFIG_MPC832X) ++#undef PVR_83xx ++#define PVR_83xx 0x80840000 ++#endif ++ + /* + * Hardware Implementation-Dependent Register 0 (HID0) + */ +diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h +index 67b035c..77a079f 100644 +--- a/include/asm-ppc/immap_83xx.h ++++ b/include/asm-ppc/immap_83xx.h +@@ -60,7 +60,10 @@ typedef struct sysconf83xx { + u32 spcr; /* System Priority Configuration Register */ + u32 sicrl; /* System I/O Configuration Register Low */ + u32 sicrh; /* System I/O Configuration Register High */ +- u8 res6[0xE4]; ++ u8 res6[0x0C]; ++ u32 ddrcdr; /* DDR Control Driver Register */ ++ u32 ddrdsr; /* DDR Debug Status Register */ ++ u8 res7[0xD0]; + } sysconf83xx_t; + + /* +@@ -274,25 +277,35 @@ typedef struct ddr83xx { + ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */ + u8 res0[0x60]; + u32 cs_config[4]; /* Chip Select x Configuration */ +- u8 res1[0x78]; ++ u8 res1[0x70]; ++ u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ ++ u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ + u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ + u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ + u32 sdram_cfg; /* SDRAM Control Configuration */ +- u8 res2[4]; ++ u32 sdram_cfg2; /* SDRAM Control Configuration 2 */ + u32 sdram_mode; /* SDRAM Mode Configuration */ +- u8 res3[8]; ++ u32 sdram_mode2; /* SDRAM Mode Configuration 2 */ ++ u32 sdram_md_cntl; /* SDRAM Mode Control */ + u32 sdram_interval; /* SDRAM Interval Configuration */ +- u8 res9[8]; +- u32 sdram_clk_cntl; +- u8 res4[0xCCC]; ++ u32 ddr_data_init; /* SDRAM Data Initialization */ ++ u8 res2[4]; ++ u32 sdram_clk_cntl; /* SDRAM Clock Control */ ++ u8 res3[0x14]; ++ u32 ddr_init_addr; /* DDR training initialization address */ ++ u32 ddr_init_ext_addr; /* DDR training initialization extended address */ ++ u8 res4[0xAA8]; ++ u32 ddr_ip_rev1; /* DDR IP block revision 1 */ ++ u32 ddr_ip_rev2; /* DDR IP block revision 2 */ ++ u8 res5[0x200]; + u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */ + u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */ + u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */ +- u8 res5[0x14]; ++ u8 res6[0x14]; + u32 capture_data_hi; /* Memory Data Path Read Capture High */ + u32 capture_data_lo; /* Memory Data Path Read Capture Low */ + u32 capture_ecc; /* Memory Data Path Read Capture ECC */ +- u8 res6[0x14]; ++ u8 res7[0x14]; + u32 err_detect; /* Memory Error Detect */ + u32 err_disable; /* Memory Error Disable */ + u32 err_int_en; /* Memory Error Interrupt Enable */ +@@ -300,9 +313,9 @@ typedef struct ddr83xx { + u32 capture_address; /* Memory Error Address Capture */ + u32 capture_ext_address;/* Memory Error Extended Address Capture */ + u32 err_sbe; /* Memory Single-Bit ECC Error Management */ +- u8 res7[0xA4]; ++ u8 res8[0xA4]; + u32 debug_reg; +- u8 res8[0xFC]; ++ u8 res9[0xFC]; + } ddr83xx_t; + + /* +@@ -607,6 +620,43 @@ typedef struct immap { + u8 res10[0xC0000]; + u8 qe[0x100000]; /* QE block */ + } immap_t; ++ ++#elif defined(CONFIG_MPC832X) ++typedef struct immap { ++ sysconf83xx_t sysconf; /* System configuration */ ++ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ ++ rtclk83xx_t rtc; /* Real Time Clock Module Registers */ ++ rtclk83xx_t pit; /* Periodic Interval Timer */ ++ gtm83xx_t gtm[2]; /* Global Timers Module */ ++ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ ++ arbiter83xx_t arbiter; /* System Arbiter Registers */ ++ reset83xx_t reset; /* Reset Module */ ++ clk83xx_t clk; /* System Clock Module */ ++ pmc83xx_t pmc; /* Power Management Control Module */ ++ qepi83xx_t qepi; /* QE Ports Interrupts Registers */ ++ u8 res0[0x300]; ++ u8 dll_ddr[0x100]; ++ u8 dll_lbc[0x100]; ++ u8 res1[0x200]; ++ qepio83xx_t qepio; /* QE Parallel I/O ports */ ++ u8 res2[0x800]; ++ ddr83xx_t ddr; /* DDR Memory Controller Memory */ ++ fsl_i2c_t i2c[2]; /* I2C Controllers */ ++ u8 res3[0x1300]; ++ duart83xx_t duart[2]; /* DUART */ ++ u8 res4[0x900]; ++ lbus83xx_t lbus; /* Local Bus Controller Registers */ ++ u8 res5[0x2000]; ++ dma83xx_t dma; /* DMA */ ++ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ ++ u8 res6[128]; ++ ios83xx_t ios; /* Sequencer (IOS) */ ++ pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ ++ u8 res7[0x27A00]; ++ security83xx_t security; ++ u8 res8[0xC0000]; ++ u8 qe[0x100000]; /* QE block */ ++} immap_t; + #endif + + #endif /* __IMMAP_83xx__ */ +diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h +index f385032..950b949 100644 +--- a/include/asm-ppc/immap_qe.h ++++ b/include/asm-ppc/immap_qe.h +@@ -547,4 +547,10 @@ typedef struct qe_immap { + + extern qe_map_t *qe_immr; + ++#if defined(CONFIG_MPC8360) ++#define QE_MURAM_SIZE 0xc000UL ++#elif defined(CONFIG_MPC832X) ++#define QE_MURAM_SIZE 0x4000UL ++#endif ++ + #endif /* __IMMAP_QE_H__ */ +diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h +new file mode 100644 +index 0000000..b8bf00f +--- /dev/null ++++ b/include/configs/MPC832XEMDS.h +@@ -0,0 +1,629 @@ ++/* ++ * Copyright (C) 2006 Freescale Semiconductor, Inc. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#undef DEBUG ++ ++/* ++ * High Level Configuration Options ++ */ ++#define CONFIG_E300 1 /* E300 family */ ++#define CONFIG_QE 1 /* Has QE */ ++#define CONFIG_MPC83XX 1 /* MPC83xx family */ ++#define CONFIG_MPC832X 1 /* MPC832x CPU specific */ ++#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ ++ ++/* ++ * System Clock Setup ++ */ ++#ifdef CONFIG_PCISLAVE ++#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ ++#else ++#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ ++#endif ++ ++#ifndef CONFIG_SYS_CLK_FREQ ++#define CONFIG_SYS_CLK_FREQ 66000000 ++#endif ++ ++/* ++ * Hardware Reset Configuration Word ++ */ ++#define CFG_HRCW_LOW (\ ++ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ ++ HRCWL_DDR_TO_SCB_CLK_2X1 |\ ++ HRCWL_VCO_1X2 |\ ++ HRCWL_CSB_TO_CLKIN_2X1 |\ ++ HRCWL_CORE_TO_CSB_2X1 |\ ++ HRCWL_CE_PLL_VCO_DIV_2 |\ ++ HRCWL_CE_PLL_DIV_1X1 |\ ++ HRCWL_CE_TO_PLL_1X3) ++ ++#ifdef CONFIG_PCISLAVE ++#define CFG_HRCW_HIGH (\ ++ HRCWH_PCI_AGENT |\ ++ HRCWH_PCI1_ARBITER_DISABLE |\ ++ HRCWH_CORE_ENABLE |\ ++ HRCWH_FROM_0XFFF00100 |\ ++ HRCWH_BOOTSEQ_DISABLE |\ ++ HRCWH_SW_WATCHDOG_DISABLE |\ ++ HRCWH_ROM_LOC_LOCAL_16BIT |\ ++ HRCWH_BIG_ENDIAN |\ ++ HRCWH_LALE_NORMAL) ++#else ++#define CFG_HRCW_HIGH (\ ++ HRCWH_PCI_HOST |\ ++ HRCWH_PCI1_ARBITER_ENABLE |\ ++ HRCWH_CORE_ENABLE |\ ++ HRCWH_FROM_0X00000100 |\ ++ HRCWH_BOOTSEQ_DISABLE |\ ++ HRCWH_SW_WATCHDOG_DISABLE |\ ++ HRCWH_ROM_LOC_LOCAL_16BIT |\ ++ HRCWH_BIG_ENDIAN |\ ++ HRCWH_LALE_NORMAL) ++#endif ++ ++/* ++ * System IO Config ++ */ ++#define CFG_SICRL 0x00000000 ++ ++#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ ++ ++/* ++ * IMMR new address ++ */ ++#define CFG_IMMR 0xE0000000 ++ ++/* ++ * DDR Setup ++ */ ++#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ ++#define CFG_SDRAM_BASE CFG_DDR_BASE ++#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE ++#define CFG_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ ++ ++#undef CONFIG_SPD_EEPROM ++#if defined(CONFIG_SPD_EEPROM) ++/* Determine DDR configuration from I2C interface ++ */ ++#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ ++#else ++/* Manually set up DDR parameters ++ */ ++#define CFG_DDR_SIZE 128 /* MB */ ++#define CFG_DDR_CS0_CONFIG 0x80840102 ++#define CFG_DDR_TIMING_0 0x00220802 ++#define CFG_DDR_TIMING_1 0x3935d322 ++#define CFG_DDR_TIMING_2 0x0f9048ca ++#define CFG_DDR_TIMING_3 0x00000000 ++#define CFG_DDR_CLK_CNTL 0x02000000 ++#define CFG_DDR_MODE 0x44400232 ++#define CFG_DDR_MODE2 0x8000c000 ++#define CFG_DDR_INTERVAL 0x03200064 ++#define CFG_DDR_CS0_BNDS 0x00000007 ++#define CFG_DDR_SDRAM_CFG 0x43080000 ++#define CFG_DDR_SDRAM_CFG2 0x00401000 ++#endif ++ ++/* ++ * Memory test ++ */ ++#undef CFG_DRAM_TEST /* memory test, takes time */ ++#define CFG_MEMTEST_START 0x00000000 /* memtest region */ ++#define CFG_MEMTEST_END 0x00100000 ++ ++/* ++ * The reserved memory ++ */ ++#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ ++ ++#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) ++#define CFG_RAMBOOT ++#else ++#undef CFG_RAMBOOT ++#endif ++ ++#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ ++#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ ++ ++/* ++ * Initial RAM Base Address Setup ++ */ ++#define CFG_INIT_RAM_LOCK 1 ++#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ ++#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ ++#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ ++#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) ++ ++/* ++ * Local Bus Configuration & Clock Setup ++ */ ++#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) ++#define CFG_LBC_LBCR 0x00000000 ++ ++/* ++ * FLASH on the Local Bus ++ */ ++#define CFG_FLASH_CFI /* use the Common Flash Interface */ ++#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ ++#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ ++#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */ ++ ++#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ ++#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ ++ ++#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ ++ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ ++ BR_V) /* valid */ ++#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ ++ ++#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ ++#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ ++ ++#undef CFG_FLASH_CHECKSUM ++ ++/* ++ * BCSR on the Local Bus ++ */ ++#define CFG_BCSR 0xF8000000 ++#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ ++#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ ++ ++#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */ ++#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ ++ ++/* ++ * SDRAM on the Local Bus ++ */ ++#undef CFG_LB_SDRAM /* The board has not SRDAM on local bus */ ++ ++#ifdef CFG_LB_SDRAM ++#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ ++#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ ++ ++#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE ++#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ ++ ++/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ ++/* ++ * Base Register 2 and Option Register 2 configure SDRAM. ++ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. ++ * ++ * For BR2, need: ++ * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 ++ * port size = 32-bits = BR2[19:20] = 11 ++ * no parity checking = BR2[21:22] = 00 ++ * SDRAM for MSEL = BR2[24:26] = 011 ++ * Valid = BR[31] = 1 ++ * ++ * 0 4 8 12 16 20 24 28 ++ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 ++ * ++ * CFG_LBC_SDRAM_BASE should be masked and OR'ed into ++ * the top 17 bits of BR2. ++ */ ++ ++#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ ++ ++/* ++ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. ++ * ++ * For OR2, need: ++ * 64MB mask for AM, OR2[0:7] = 1111 1100 ++ * XAM, OR2[17:18] = 11 ++ * 9 columns OR2[19-21] = 010 ++ * 13 rows OR2[23-25] = 100 ++ * EAD set for extra time OR[31] = 1 ++ * ++ * 0 4 8 12 16 20 24 28 ++ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 ++ */ ++ ++#define CFG_OR2_PRELIM 0xfc006901 ++ ++#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ ++#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ ++ ++/* ++ * LSDMR masks ++ */ ++#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) ++ ++#define CFG_LBC_LSDMR_COMMON 0x0063b723 ++ ++/* ++ * SDRAM Controller configuration sequence. ++ */ ++#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ ++ | CFG_LBC_LSDMR_OP_PCHALL) ++#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ ++ | CFG_LBC_LSDMR_OP_ARFRSH) ++#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ ++ | CFG_LBC_LSDMR_OP_ARFRSH) ++#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ ++ | CFG_LBC_LSDMR_OP_MRW) ++#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ ++ | CFG_LBC_LSDMR_OP_NORMAL) ++ ++#endif ++ ++/* ++ * Windows to access PIB via local bus ++ */ ++#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ ++#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ ++ ++/* ++ * CS2 on Local Bus, to PIB ++ */ ++#define CFG_BR2_PRELIM 0xf8008801 /* CS2 base address at 0xf8008000 */ ++#define CFG_OR2_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ ++ ++/* ++ * CS3 on Local Bus, to PIB ++ */ ++#define CFG_BR3_PRELIM 0xf8010801 /* CS3 base address at 0xf8010000 */ ++#define CFG_OR3_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ ++ ++/* ++ * Serial Port ++ */ ++#define CONFIG_CONS_INDEX 1 ++#undef CONFIG_SERIAL_SOFTWARE_FIFO ++#define CFG_NS16550 ++#define CFG_NS16550_SERIAL ++#define CFG_NS16550_REG_SIZE 1 ++#define CFG_NS16550_CLK get_bus_freq(0) ++ ++#define CFG_BAUDRATE_TABLE \ ++ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} ++ ++#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) ++#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) ++ ++/* Use the HUSH parser */ ++#define CFG_HUSH_PARSER ++#ifdef CFG_HUSH_PARSER ++#define CFG_PROMPT_HUSH_PS2 "> " ++#endif ++ ++/* pass open firmware flat tree */ ++#define CONFIG_OF_FLAT_TREE 1 ++#define CONFIG_OF_BOARD_SETUP 1 ++ ++/* maximum size of the flat tree (8K) */ ++#define OF_FLAT_TREE_MAX_SIZE 8192 ++ ++#define OF_CPU "PowerPC,8323@0" ++#define OF_SOC "soc8323@e0000000" ++#define OF_TBCLK (bd->bi_busfreq / 4) ++#define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500" ++ ++/* I2C */ ++#define CONFIG_HARD_I2C /* I2C with hardware support */ ++#undef CONFIG_SOFT_I2C /* I2C bit-banged */ ++#define CONFIG_FSL_I2C ++#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ ++#define CFG_I2C_SLAVE 0x7F ++#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ ++#define CFG_I2C_OFFSET 0x3000 ++ ++/* ++ * Config on-board RTC ++ */ ++#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ ++#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ ++ ++/* ++ * General PCI ++ * Addresses are mapped 1-1. ++ */ ++#define CFG_PCI_MEM_BASE 0x80000000 ++#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE ++#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ ++#define CFG_PCI_MMIO_BASE 0x90000000 ++#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE ++#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ ++#define CFG_PCI_IO_BASE 0xE0300000 ++#define CFG_PCI_IO_PHYS 0xE0300000 ++#define CFG_PCI_IO_SIZE 0x100000 /* 1M */ ++ ++#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE ++#define CFG_PCI_SLV_MEM_BUS 0x00000000 ++#define CFG_PCI_SLV_MEM_SIZE 0x80000000 ++ ++ ++#ifdef CONFIG_PCI ++ ++#define CONFIG_NET_MULTI ++#define CONFIG_PCI_PNP /* do pci plug-and-play */ ++ ++#undef CONFIG_EEPRO100 ++#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ ++#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ ++ ++#endif /* CONFIG_PCI */ ++ ++ ++#ifndef CONFIG_NET_MULTI ++#define CONFIG_NET_MULTI 1 ++#endif ++ ++/* ++ * QE UEC ethernet configuration ++ */ ++#define CONFIG_UEC_ETH ++#define CONFIG_ETHPRIME "Freescale GETH" ++ ++#define CONFIG_UEC_ETH1 /* ETH3 */ ++ ++#ifdef CONFIG_UEC_ETH1 ++#define CFG_UEC1_UCC_NUM 2 /* UCC3 */ ++#define CFG_UEC1_RX_CLK QE_CLK9 ++#define CFG_UEC1_TX_CLK QE_CLK10 ++#define CFG_UEC1_ETH_TYPE FAST_ETH ++#define CFG_UEC1_PHY_ADDR 3 ++#define CFG_UEC1_INTERFACE_MODE ENET_100_MII ++#endif ++ ++#define CONFIG_UEC_ETH2 /* ETH4 */ ++ ++#ifdef CONFIG_UEC_ETH2 ++#define CFG_UEC2_UCC_NUM 3 /* UCC4 */ ++#define CFG_UEC2_RX_CLK QE_CLK7 ++#define CFG_UEC2_TX_CLK QE_CLK8 ++#define CFG_UEC2_ETH_TYPE FAST_ETH ++#define CFG_UEC2_PHY_ADDR 4 ++#define CFG_UEC2_INTERFACE_MODE ENET_100_MII ++#endif ++ ++/* ++ * Environment ++ */ ++#ifndef CFG_RAMBOOT ++ #define CFG_ENV_IS_IN_FLASH 1 ++ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) ++ #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ ++ #define CFG_ENV_SIZE 0x2000 ++#else ++ #define CFG_NO_FLASH 1 /* Flash is not usable now */ ++ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ ++ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) ++ #define CFG_ENV_SIZE 0x2000 ++#endif ++ ++#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ ++#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ ++ ++#if defined(CFG_RAMBOOT) ++#if defined(CONFIG_PCI) ++#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ ++ | CFG_CMD_PING \ ++ | CFG_CMD_ASKENV \ ++ | CFG_CMD_PCI \ ++ | CFG_CMD_I2C) \ ++ & \ ++ ~(CFG_CMD_ENV \ ++ | CFG_CMD_LOADS)) ++#else ++#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ ++ | CFG_CMD_PING \ ++ | CFG_CMD_ASKENV \ ++ | CFG_CMD_I2C) \ ++ & \ ++ ~(CFG_CMD_ENV \ ++ | CFG_CMD_LOADS)) ++#endif ++#else ++#if defined(CONFIG_PCI) ++#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ ++ | CFG_CMD_PCI \ ++ | CFG_CMD_PING \ ++ | CFG_CMD_ASKENV \ ++ | CFG_CMD_I2C) ++#else ++#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ ++ | CFG_CMD_PING \ ++ | CFG_CMD_ASKENV \ ++ | CFG_CMD_I2C ) ++#endif ++#endif ++ ++#include ++ ++#undef CONFIG_WATCHDOG /* watchdog disabled */ ++ ++/* ++ * Miscellaneous configurable options ++ */ ++#define CFG_LONGHELP /* undef to save memory */ ++#define CFG_LOAD_ADDR 0x2000000 /* default load address */ ++#define CFG_PROMPT "=> " /* Monitor Command Prompt */ ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ ++#else ++ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ ++#endif ++ ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ ++#define CFG_MAXARGS 16 /* max number of command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ ++#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ ++ ++/* ++ * For booting Linux, the board info and command line data ++ * have to be in the first 8 MB of memory, since this is ++ * the maximum mapped by the Linux kernel during initialization. ++ */ ++#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ ++ ++/* ++ * Core HID Setup ++ */ ++#define CFG_HID0_INIT 0x000000000 ++#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK ++#define CFG_HID2 HID2_HBE ++ ++/* ++ * Cache Config ++ */ ++#define CFG_DCACHE_SIZE 16384 ++#define CFG_CACHELINE_SIZE 32 ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ ++#endif ++ ++/* ++ * MMU Setup ++ */ ++ ++/* DDR: cache cacheable */ ++#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) ++#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) ++#define CFG_DBAT0L CFG_IBAT0L ++#define CFG_DBAT0U CFG_IBAT0U ++ ++/* IMMRBAR & PCI IO: cache-inhibit and guarded */ ++#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ ++ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) ++#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) ++#define CFG_DBAT1L CFG_IBAT1L ++#define CFG_DBAT1U CFG_IBAT1U ++ ++/* BCSR: cache-inhibit and guarded */ ++#define CFG_IBAT2L (CFG_BCSR | BATL_PP_10 | \ ++ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) ++#define CFG_IBAT2U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) ++#define CFG_DBAT2L CFG_IBAT2L ++#define CFG_DBAT2U CFG_IBAT2U ++ ++/* FLASH: icache cacheable, but dcache-inhibit and guarded */ ++#define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) ++#define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) ++#define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \ ++ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) ++#define CFG_DBAT3U CFG_IBAT3U ++ ++#define CFG_IBAT4L (0) ++#define CFG_IBAT4U (0) ++#define CFG_DBAT4L CFG_IBAT4L ++#define CFG_DBAT4U CFG_IBAT4U ++ ++/* Stack in dcache: cacheable, no memory coherence */ ++#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) ++#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) ++#define CFG_DBAT5L CFG_IBAT5L ++#define CFG_DBAT5U CFG_IBAT5U ++ ++#ifdef CONFIG_PCI ++/* PCI MEM space: cacheable */ ++#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) ++#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) ++#define CFG_DBAT6L CFG_IBAT6L ++#define CFG_DBAT6U CFG_IBAT6U ++/* PCI MMIO space: cache-inhibit and guarded */ ++#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ ++ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) ++#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) ++#define CFG_DBAT7L CFG_IBAT7L ++#define CFG_DBAT7U CFG_IBAT7U ++#else ++#define CFG_IBAT6L (0) ++#define CFG_IBAT6U (0) ++#define CFG_IBAT7L (0) ++#define CFG_IBAT7U (0) ++#define CFG_DBAT6L CFG_IBAT6L ++#define CFG_DBAT6U CFG_IBAT6U ++#define CFG_DBAT7L CFG_IBAT7L ++#define CFG_DBAT7U CFG_IBAT7U ++#endif ++ ++/* ++ * Internal Definitions ++ * ++ * Boot Flags ++ */ ++#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ ++#define BOOTFLAG_WARM 0x02 /* Software reboot */ ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ ++#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ ++#endif ++ ++/* ++ * Environment Configuration ++ */ ++ ++#define CONFIG_ENV_OVERWRITE ++ ++#if defined(CONFIG_UEC_ETH) ++#define CONFIG_ETHADDR 00:04:9f:ef:03:01 ++#define CONFIG_HAS_ETH1 ++#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02 ++#endif ++ ++#define CONFIG_BAUDRATE 115200 ++ ++#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ ++ ++#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ ++#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "netdev=eth0\0" \ ++ "consoledev=ttyS0\0" \ ++ "ramdiskaddr=1000000\0" \ ++ "ramdiskfile=ramfs.83xx\0" \ ++ "fdtaddr=400000\0" \ ++ "fdtfile=mpc832xemds.dtb\0" \ ++ "" ++ ++#define CONFIG_NFSBOOTCOMMAND \ ++ "setenv bootargs root=/dev/nfs rw " \ ++ "nfsroot=$serverip:$rootpath " \ ++ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ ++ "console=$consoledev,$baudrate $othbootargs;" \ ++ "tftp $loadaddr $bootfile;" \ ++ "tftp $fdtaddr $fdtfile;" \ ++ "bootm $loadaddr - $fdtaddr" ++ ++#define CONFIG_RAMBOOTCOMMAND \ ++ "setenv bootargs root=/dev/ram rw " \ ++ "console=$consoledev,$baudrate $othbootargs;" \ ++ "tftp $ramdiskaddr $ramdiskfile;" \ ++ "tftp $loadaddr $bootfile;" \ ++ "tftp $fdtaddr $fdtfile;" \ ++ "bootm $loadaddr $ramdiskaddr $fdtaddr" ++ ++ ++#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND ++ ++#endif /* __CONFIG_H */ +diff --git a/include/mpc83xx.h b/include/mpc83xx.h +index 504b6a9..52e4369 100644 +--- a/include/mpc83xx.h ++++ b/include/mpc83xx.h +@@ -75,6 +75,15 @@ + #define SPR_8360E_REV12 0x80480012 + #define SPR_8360_REV12 0x80490012 + ++#define SPR_8323E_REV10 0x80620010 ++#define SPR_8323_REV10 0x80630010 ++#define SPR_8321E_REV10 0x80660010 ++#define SPR_8321_REV10 0x80670010 ++#define SPR_8323E_REV11 0x80620011 ++#define SPR_8323_REV11 0x80630011 ++#define SPR_8321E_REV11 0x80660011 ++#define SPR_8321_REV11 0x80670011 ++ + /* SPCR - System Priority Configuration Register + */ + #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ +@@ -167,6 +176,14 @@ + #define SICRH_UC1EOBI 0x00000004 + #define SICRH_UC2E1OBI 0x00000002 + #define SICRH_UC2E2OBI 0x00000001 ++ ++#elif defined(CONFIG_MPC832X) ++/* SICRL bits - MPC832X specific */ ++#define SICRL_LDP_LCS_A 0x80000000 ++#define SICRL_IRQ_CKS 0x20000000 ++#define SICRL_PCI_MSRC 0x10000000 ++#define SICRL_URT_CTPR 0x06000000 ++#define SICRL_IRQ_CTPR 0x00C00000 + #endif + + /* SWCRR - System Watchdog Control Register +@@ -270,7 +287,7 @@ + #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 + #define HRCWL_CORE_TO_CSB_3X1 0x00060000 + +-#if defined(CONFIG_MPC8360) ++#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) + #define HRCWL_CEVCOD 0x000000C0 + #define HRCWL_CEVCOD_SHIFT 6 + #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 +@@ -718,7 +735,7 @@ + #define BR_MS_UPMA 0x00000080 /* UPMA */ + #define BR_MS_UPMB 0x000000A0 /* UPMB */ + #define BR_MS_UPMC 0x000000C0 /* UPMC */ +-#if defined(CONFIG_MPC8360) ++#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) + #define BR_ATOM 0x0000000C + #define BR_ATOM_SHIFT 2 + #endif diff --git a/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Add-the-MPC832XEMDS-board-readme.patch b/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Add-the-MPC832XEMDS-board-readme.patch new file mode 100644 index 0000000000..b5e2a87b16 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Add-the-MPC832XEMDS-board-readme.patch @@ -0,0 +1,131 @@ +657bdd350516722e4d73329caf37aae694f7eaaa +diff --git a/doc/README.mpc832xemds b/doc/README.mpc832xemds +new file mode 100644 +index 0000000..00c3af1 +--- /dev/null ++++ b/doc/README.mpc832xemds +@@ -0,0 +1,124 @@ ++Freescale MPC832XEMDS Board ++----------------------------------------- ++1. Board Switches and Jumpers ++1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board ++ For some reason, the HW designers describe the switch settings ++ in terms of 0 and 1, and then map that to physical switches where ++ the label "On" refers to logic 0 and "Off" is logic 1. ++ ++ Switch bits are numbered 1 through, like, 4 6 8 or 10, but the ++ bits may contribute to signals that are numbered based at 0, ++ and some of those signals may be high-bit-number-0 too. Heed ++ well the names and labels and do not get confused. ++ ++ "Off" == 1 ++ "On" == 0 ++ ++ SW3 is switch 18 as silk-screened onto the board. ++ SW4[8] is the bit labled 8 on Switch 4. ++ SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5. ++ SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6. ++ SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On" ++ and bits labeled 8 is set as "Off". ++ ++1.1 For the MPC832XEMDS PROTO Board ++ ++ First, make sure the board default setting is consistent with the ++ document shipped with your board. Then apply the following setting: ++ SW3[1-8]= 0000_1000 (core PLL setting, core enable) ++ SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting) ++ SW5[1-8]= 0010_0110 (Boot from high end) ++ SW6[1-8]= 0011_0100 (Flash boot on 16 bit local bus) ++ SW7[1-8]= 1000_0011 (QE PLL setting) ++ ++ ENET3/4 MII mode settings: ++ J1 1-2 (ETH3_TXER) ++ J2 2-3 (MII mode) ++ J3 2-3 (MII mode) ++ J4 2-3 (ADSL clockOscillator) ++ J5 1-2 (ETH4_TXER) ++ J6 2-3 (ClockOscillator) ++ JP1 removed (don't force PORESET) ++ JP2 mounted (ETH4/2 MII) ++ JP3 mounted (ETH3 MII) ++ JP4 mounted (HRCW from BCSR) ++ ++ ENET3/4 RMII mode settings: ++ J1 1-2 (ETH3_TXER) ++ J2 1-2 (RMII mode) ++ J3 1-2 (RMII mode) ++ J4 2-3 (ADSL clockOscillator) ++ J5 1-2 (ETH4_TXER) ++ J6 2-3 (ClockOscillator) ++ JP1 removed (don't force PORESET) ++ JP2 removed (ETH4/2 RMII) ++ JP3 removed (ETH3 RMII) ++ JP4 removed (HRCW from FLASH) ++ ++ on board Oscillator: 66M ++ ++ ++2. Memory Map ++ ++2.1 The memory map should look pretty much like this: ++ ++ 0x0000_0000 0x7fff_ffff DDR 2G ++ 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M ++ 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M ++ 0xc000_0000 0xdfff_ffff Empty 512M ++ 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M ++ 0xe020_0000 0xe02f_ffff Empty 1M ++ 0xe030_0000 0xe03f_ffff PCI IO 1M ++ 0xe040_0000 0xefff_ffff Empty 252M ++ 0xf400_0000 0xf7ff_ffff Empty 64M ++ 0xf800_0000 0xf800_7fff BCSR on CS1 32K ++ 0xf800_8000 0xf800_ffff PIB CS2 32K ++ 0xf801_0000 0xf801_7fff PIB CS3 32K ++ 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M ++ ++ ++3. Definitions ++ ++3.1 Explanation of NEW definitions in: ++ ++ include/configs/MPC832XEMDS.h ++ ++ CONFIG_MPC83XX MPC83XX family for MPC8349, MPC8360 and MPC832X ++ CONFIG_MPC832X MPC832X specific ++ CONFIG_MPC832XEMDS MPC832XEMDS board specific ++ ++4. Compilation ++ ++ Assuming you're using BASH shell: ++ ++ export CROSS_COMPILE=your-cross-compile-prefix ++ cd u-boot ++ make distclean ++ make MPC832XEMDS_config ++ make ++ ++ MPC832X support PCI 33MHz and PCI 66MHz, to make u-boot support PCI: ++ ++ 1)Make sure the DIP SW support PCI mode ++ as described in Section 1.1. ++ ++ 2)To Make U-Boot image support PCI 33MHz, use ++ Make MPC832XEMDS_HOST_33_config ++ ++ 3)To Make U-Boot image support PCI 66MHz, use ++ Make MPC832XEMDS_HOST_66_config ++ ++5. Downloading and Flashing Images ++ ++5.0 Download over network: ++ ++ tftp 20000 u-boot.bin ++ ++5.1 Reflash U-boot Image using U-boot ++ ++ If your current u-boot sets $filesize automatically: ++ ++ protect off fe000000 +$filesize ++ erase fe000000 +$filesize ++ cp.b 20000 fe000000 $filesize ++ diff --git a/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Added-MPC8323E-RDB-board-support-2.patch b/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Added-MPC8323E-RDB-board-support-2.patch new file mode 100644 index 0000000000..23a9717e74 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Added-MPC8323E-RDB-board-support-2.patch @@ -0,0 +1,1221 @@ +7a328e85f4ff0b6c074a7fdb302e6e6f6f36e7f2 +diff --git a/Makefile b/Makefile +index d172411..73014fd 100644 +--- a/Makefile ++++ b/Makefile +@@ -1645,6 +1645,12 @@ MPC832XEMDS_SLAVE_config: unconfig + fi ; + @$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds + ++MPC8323ERDB_config: unconfig ++ @echo "" >include/config.h ; \ ++ echo -n "... PCI HOST " ; \ ++ echo "#define CONFIG_PCI" >>include/config.h ; ++ @$(MKCONFIG) -a MPC8323ERDB ppc mpc83xx mpc8323erdb ++ + ######################################################################### + ## MPC85xx Systems + ######################################################################### +diff --git a/board/mpc8323erdb/Makefile b/board/mpc8323erdb/Makefile +new file mode 100644 +index 0000000..5ec7a87 +--- /dev/null ++++ b/board/mpc8323erdb/Makefile +@@ -0,0 +1,50 @@ ++# ++# (C) Copyright 2006 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).a ++ ++COBJS := $(BOARD).o pci.o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) ++ $(AR) $(ARFLAGS) $@ $(OBJS) ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak .depend ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +diff --git a/board/mpc8323erdb/config.mk b/board/mpc8323erdb/config.mk +new file mode 100644 +index 0000000..fe0d37d +--- /dev/null ++++ b/board/mpc8323erdb/config.mk +@@ -0,0 +1,28 @@ ++# ++# (C) Copyright 2006 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++# ++# MPC8323ERDB ++# ++ ++TEXT_BASE = 0xFE000000 +diff --git a/board/mpc8323erdb/mpc8323erdb.c b/board/mpc8323erdb/mpc8323erdb.c +new file mode 100644 +index 0000000..239adbb +--- /dev/null ++++ b/board/mpc8323erdb/mpc8323erdb.c +@@ -0,0 +1,169 @@ ++/* ++ * Copyright (C) 2006 Freescale Semiconductor, Inc. ++ * ++ * Michael Barkowski ++ * Based on mpc832xmds file by Dave Liu ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if defined(CONFIG_PCI) ++#include ++#endif ++#if defined(CONFIG_SPD_EEPROM) ++#include ++#else ++#include ++#endif ++#if defined(CONFIG_OF_FLAT_TREE) ++#include ++#endif ++ ++const qe_iop_conf_t qe_iop_conf_tab[] = { ++ /* UCC3 */ ++ {1, 0, 1, 0, 1}, /* TxD0 */ ++ {1, 1, 1, 0, 1}, /* TxD1 */ ++ {1, 2, 1, 0, 1}, /* TxD2 */ ++ {1, 3, 1, 0, 1}, /* TxD3 */ ++ {1, 9, 1, 0, 1}, /* TxER */ ++ {1, 12, 1, 0, 1}, /* TxEN */ ++ {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ ++ ++ {1, 4, 2, 0, 1}, /* RxD0 */ ++ {1, 5, 2, 0, 1}, /* RxD1 */ ++ {1, 6, 2, 0, 1}, /* RxD2 */ ++ {1, 7, 2, 0, 1}, /* RxD3 */ ++ {1, 8, 2, 0, 1}, /* RxER */ ++ {1, 10, 2, 0, 1}, /* RxDV */ ++ {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ ++ {1, 11, 2, 0, 1}, /* COL */ ++ {1, 13, 2, 0, 1}, /* CRS */ ++ ++ /* UCC2 */ ++ {0, 18, 1, 0, 1}, /* TxD0 */ ++ {0, 19, 1, 0, 1}, /* TxD1 */ ++ {0, 20, 1, 0, 1}, /* TxD2 */ ++ {0, 21, 1, 0, 1}, /* TxD3 */ ++ {0, 27, 1, 0, 1}, /* TxER */ ++ {0, 30, 1, 0, 1}, /* TxEN */ ++ {3, 23, 2, 0, 1}, /* TxCLK->CLK3 */ ++ ++ {0, 22, 2, 0, 1}, /* RxD0 */ ++ {0, 23, 2, 0, 1}, /* RxD1 */ ++ {0, 24, 2, 0, 1}, /* RxD2 */ ++ {0, 25, 2, 0, 1}, /* RxD3 */ ++ {0, 26, 1, 0, 1}, /* RxER */ ++ {0, 28, 2, 0, 1}, /* Rx_DV */ ++ {3, 21, 2, 0, 1}, /* RxCLK->CLK16 */ ++ {0, 29, 2, 0, 1}, /* COL */ ++ {0, 31, 2, 0, 1}, /* CRS */ ++ ++ {3, 4, 3, 0, 2}, /* MDIO */ ++ {3, 5, 1, 0, 2}, /* MDC */ ++ ++ {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ ++}; ++ ++int board_early_init_f(void) ++{ ++ return 0; ++} ++ ++int fixed_sdram(void); ++ ++long int initdram(int board_type) ++{ ++ volatile immap_t *im = (immap_t *) CFG_IMMR; ++ u32 msize = 0; ++ ++ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) ++ return -1; ++ ++ /* DDR SDRAM - Main SODIMM */ ++ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; ++ ++ msize = fixed_sdram(); ++ ++ puts("\n DDR RAM: "); ++ ++ /* return total bus SDRAM size(bytes) -- DDR */ ++ return (msize * 1024 * 1024); ++} ++ ++/************************************************************************* ++ * fixed sdram init -- doesn't use serial presence detect. ++ ************************************************************************/ ++int fixed_sdram(void) ++{ ++ volatile immap_t *im = (immap_t *) CFG_IMMR; ++ u32 msize = 0; ++ u32 ddr_size; ++ u32 ddr_size_log2; ++ ++ msize = CFG_DDR_SIZE; ++ for (ddr_size = msize << 20, ddr_size_log2 = 0; ++ (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { ++ if (ddr_size & 1) { ++ return -1; ++ } ++ } ++ im->sysconf.ddrlaw[0].ar = ++ LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); ++ im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; ++ im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; ++ im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; ++ im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; ++ im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; ++ im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; ++ im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; ++ im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; ++ im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; ++ im->ddr.sdram_mode = CFG_DDR_MODE; ++ im->ddr.sdram_mode2 = CFG_DDR_MODE2; ++ im->ddr.sdram_interval = CFG_DDR_INTERVAL; ++ __asm__ __volatile__ ("sync"); ++ udelay(200); ++ ++ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; ++ __asm__ __volatile__ ("sync"); ++ return msize; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: Freescale MPC8323ERDB\n"); ++ return 0; ++} ++ ++#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) ++void ++ft_board_setup(void *blob, bd_t *bd) ++{ ++ u32 *p; ++ int len; ++ ++#ifdef CONFIG_PCI ++ ft_pci_setup(blob, bd); ++#endif ++ ft_cpu_setup(blob, bd); ++ ++ p = ft_get_prop(blob, "/memory/reg", &len); ++ if (p != NULL) { ++ *p++ = cpu_to_be32(bd->bi_memstart); ++ *p = cpu_to_be32(bd->bi_memsize); ++ } ++} ++#endif +diff --git a/board/mpc8323erdb/pci.c b/board/mpc8323erdb/pci.c +new file mode 100644 +index 0000000..2e942d2 +--- /dev/null ++++ b/board/mpc8323erdb/pci.c +@@ -0,0 +1,208 @@ ++/* ++ * Copyright (C) 2006 Freescale Semiconductor, Inc. ++ * ++ * Michael Barkowski ++ * Based on mpc832xemds/pci.c by Dave Liu. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++/* ++ * PCI Configuration space access support for MPC83xx PCI Bridge ++ */ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#if defined(CONFIG_PCI) ++#define PCI_FUNCTION_CONFIG 0x44 ++#define PCI_FUNCTION_CFG_LOCK 0x20 ++ ++/* ++ * Initialize PCI Devices, report devices found ++ */ ++#ifndef CONFIG_PCI_PNP ++static struct pci_config_table pci_mpc8323erdb_config_table[] = { ++ { ++ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, ++ pci_cfgfunc_config_device, ++ {PCI_ENET0_IOADDR, ++ PCI_ENET0_MEMADDR, ++ PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} ++ }, ++ {} ++} ++#endif ++static struct pci_controller hose[] = { ++ { ++#ifndef CONFIG_PCI_PNP ++ config_table:pci_mpc8323erdb_config_table, ++#endif ++ }, ++}; ++ ++/********************************************************************** ++ * pci_init_board() ++ *********************************************************************/ ++void pci_init_board(void) ++{ ++ volatile immap_t *immr; ++ volatile clk83xx_t *clk; ++ volatile law83xx_t *pci_law; ++ volatile pot83xx_t *pci_pot; ++ volatile pcictrl83xx_t *pci_ctrl; ++ volatile pciconf83xx_t *pci_conf; ++ ++ u8 val8; ++ u16 reg16; ++ u32 val32; ++ u32 dev; ++ ++ immr = (immap_t *) CFG_IMMR; ++ clk = (clk83xx_t *) & immr->clk; ++ pci_law = immr->sysconf.pcilaw; ++ pci_pot = immr->ios.pot; ++ pci_ctrl = immr->pci_ctrl; ++ pci_conf = immr->pci_conf; ++ /* ++ * Enable PCI output signals ++ */ ++ val32 = clk->occr; ++ udelay(2000); ++ /* if pin /CFG_CLKIN_DIV=1, PCI clock = clkin = 66MHz; ++ if pin /CFG_CLKIN_DIV=0, PCI clock = clkin/2 = 33MHz; */ ++ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; ++ if (clk->spmr & SPMR_CKID) ++ printf("PCI clock is 33MHz\n"); ++ else ++ printf("PCI clock is 66MHz\n"); ++ udelay(2000); ++ ++ /* ++ * Configure PCI Local Access Windows ++ */ ++ pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; ++ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; ++ ++ pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; ++ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; ++ ++ /* ++ * Configure PCI Outbound Translation Windows ++ */ ++ ++ /* PCI mem space - prefetch */ ++ pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; ++ pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; ++ pci_pot[0].pocmr = ++ POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK); ++ ++ /* PCI mmio - non-prefetch mem space */ ++ pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; ++ pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; ++ pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); ++ ++ /* PCI IO space */ ++ pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK; ++ pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; ++ pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); ++ ++ /* ++ * Configure PCI Inbound Translation Windows ++ */ ++ pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; ++ pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; ++ pci_ctrl[0].piebar1 = 0x0; ++ pci_ctrl[0].piwar1 = ++ PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | ++ PIWAR_IWS_2G; ++ ++ /* ++ * Release PCI RST Output signal ++ */ ++ udelay(2000); ++ pci_ctrl[0].gcr = 1; ++ udelay(2000); ++ ++ hose[0].first_busno = 0; ++ hose[0].last_busno = 0xff; ++ ++ /* PCI memory prefetch space */ ++ pci_set_region(hose[0].regions + 0, ++ CFG_PCI_MEM_BASE, ++ CFG_PCI_MEM_PHYS, ++ CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); ++ ++ /* PCI memory space */ ++ pci_set_region(hose[0].regions + 1, ++ CFG_PCI_MMIO_BASE, ++ CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM); ++ ++ /* PCI IO space */ ++ pci_set_region(hose[0].regions + 2, ++ CFG_PCI_IO_BASE, ++ CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); ++ ++ /* System memory space */ ++ pci_set_region(hose[0].regions + 3, ++ CFG_PCI_SLV_MEM_LOCAL, ++ CFG_PCI_SLV_MEM_BUS, ++ CFG_PCI_SLV_MEM_SIZE, ++ PCI_REGION_MEM | PCI_REGION_MEMORY); ++ ++ hose[0].region_count = 4; ++ ++ pci_setup_indirect(&hose[0], ++ (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); ++ ++ pci_register_hose(hose); ++ ++ /* ++ * Write command register ++ */ ++ reg16 = 0xff; ++ dev = PCI_BDF(0, 0, 0); ++ pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16); ++ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; ++ pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16); ++ ++ /* ++ * Clear non-reserved bits in status register. ++ */ ++ pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff); ++ pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); ++ pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); ++ ++ /* ++ * Hose scan. ++ */ ++ hose->last_busno = pci_hose_scan(hose); ++} ++ ++#ifdef CONFIG_OF_FLAT_TREE ++void ++ft_pci_setup(void *blob, bd_t *bd) ++{ ++ u32 *p; ++ int len; ++ ++ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); ++ if (p != NULL) { ++ p[0] = hose[0].first_busno; ++ p[1] = hose[0].last_busno; ++ } ++} ++#endif /* CONFIG_OF_FLAT_TREE */ ++#endif /* CONFIG_PCI */ +diff --git a/board/mpc8323erdb/u-boot.lds b/board/mpc8323erdb/u-boot.lds +new file mode 100644 +index 0000000..937c87a +--- /dev/null ++++ b/board/mpc8323erdb/u-boot.lds +@@ -0,0 +1,123 @@ ++/* ++ * (C) Copyright 2006 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_ARCH(powerpc) ++SECTIONS ++{ ++ /* Read-only sections, merged into text segment: */ ++ . = + SIZEOF_HEADERS; ++ .interp : { *(.interp) } ++ .hash : { *(.hash) } ++ .dynsym : { *(.dynsym) } ++ .dynstr : { *(.dynstr) } ++ .rel.text : { *(.rel.text) } ++ .rela.text : { *(.rela.text) } ++ .rel.data : { *(.rel.data) } ++ .rela.data : { *(.rela.data) } ++ .rel.rodata : { *(.rel.rodata) } ++ .rela.rodata : { *(.rela.rodata) } ++ .rel.got : { *(.rel.got) } ++ .rela.got : { *(.rela.got) } ++ .rel.ctors : { *(.rel.ctors) } ++ .rela.ctors : { *(.rela.ctors) } ++ .rel.dtors : { *(.rel.dtors) } ++ .rela.dtors : { *(.rela.dtors) } ++ .rel.bss : { *(.rel.bss) } ++ .rela.bss : { *(.rela.bss) } ++ .rel.plt : { *(.rel.plt) } ++ .rela.plt : { *(.rela.plt) } ++ .init : { *(.init) } ++ .plt : { *(.plt) } ++ .text : ++ { ++ cpu/mpc83xx/start.o (.text) ++ *(.text) ++ *(.fixup) ++ *(.got1) ++ . = ALIGN(16); ++ *(.rodata) ++ *(.rodata1) ++ *(.rodata.str1.4) ++ *(.eh_frame) ++ } ++ .fini : { *(.fini) } =0 ++ .ctors : { *(.ctors) } ++ .dtors : { *(.dtors) } ++ ++ /* Read-write section, merged into data segment: */ ++ . = (. + 0x0FFF) & 0xFFFFF000; ++ _erotext = .; ++ PROVIDE (erotext = .); ++ .reloc : ++ { ++ *(.got) ++ _GOT2_TABLE_ = .; ++ *(.got2) ++ _FIXUP_TABLE_ = .; ++ *(.fixup) ++ } ++ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; ++ __fixup_entries = (. - _FIXUP_TABLE_) >> 2; ++ ++ .data : ++ { ++ *(.data) ++ *(.data1) ++ *(.sdata) ++ *(.sdata2) ++ *(.dynamic) ++ CONSTRUCTORS ++ } ++ _edata = .; ++ PROVIDE (edata = .); ++ ++ . = .; ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ ++ . = .; ++ __start___ex_table = .; ++ __ex_table : { *(__ex_table) } ++ __stop___ex_table = .; ++ ++ . = ALIGN(4096); ++ __init_begin = .; ++ .text.init : { *(.text.init) } ++ .data.init : { *(.data.init) } ++ . = ALIGN(4096); ++ __init_end = .; ++ ++ __bss_start = .; ++ .bss : ++ { ++ *(.sbss) *(.scommon) ++ *(.dynbss) ++ *(.bss) ++ *(COMMON) ++ } ++ _end = . ; ++ PROVIDE (end = .); ++} ++ENTRY(_start) +diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h +new file mode 100644 +index 0000000..ebbc7b0 +--- /dev/null ++++ b/include/configs/MPC8323ERDB.h +@@ -0,0 +1,589 @@ ++/* ++ * Copyright (C) 2006 Freescale Semiconductor, Inc. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#undef DEBUG ++ ++/* ++ * High Level Configuration Options ++ */ ++#define CONFIG_E300 1 /* E300 family */ ++#define CONFIG_QE 1 /* Has QE */ ++#define CONFIG_MPC83XX 1 /* MPC83xx family */ ++#define CONFIG_MPC832X 1 /* MPC832x CPU specific */ ++ ++/* ++ * System Clock Setup ++ */ ++#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ ++ ++#ifndef CONFIG_SYS_CLK_FREQ ++#define CONFIG_SYS_CLK_FREQ 66666667 ++#endif ++ ++/* ++ * Hardware Reset Configuration Word ++ */ ++#define CFG_HRCW_LOW (\ ++ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ ++ HRCWL_DDR_TO_SCB_CLK_2X1 |\ ++ HRCWL_VCO_1X2 |\ ++ HRCWL_CSB_TO_CLKIN_2X1 |\ ++ HRCWL_CORE_TO_CSB_2_5X1 |\ ++ HRCWL_CE_PLL_VCO_DIV_2 |\ ++ HRCWL_CE_PLL_DIV_1X1 |\ ++ HRCWL_CE_TO_PLL_1X3) ++ ++#define CFG_HRCW_HIGH (\ ++ HRCWH_PCI_HOST |\ ++ HRCWH_PCI1_ARBITER_ENABLE |\ ++ HRCWH_CORE_ENABLE |\ ++ HRCWH_FROM_0X00000100 |\ ++ HRCWH_BOOTSEQ_DISABLE |\ ++ HRCWH_SW_WATCHDOG_DISABLE |\ ++ HRCWH_ROM_LOC_LOCAL_16BIT |\ ++ HRCWH_BIG_ENDIAN |\ ++ HRCWH_LALE_NORMAL) ++ ++/* ++ * System IO Config ++ */ ++#define CFG_SICRL 0x00000000 ++ ++#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ ++ ++/* ++ * IMMR new address ++ */ ++#define CFG_IMMR 0xE0000000 ++ ++/* ++ * DDR Setup ++ */ ++#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ ++#define CFG_SDRAM_BASE CFG_DDR_BASE ++#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE ++#define CFG_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ ++ ++#undef CONFIG_SPD_EEPROM ++#if defined(CONFIG_SPD_EEPROM) ++/* Determine DDR configuration from I2C interface ++ */ ++#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ ++#else ++/* Manually set up DDR parameters ++ */ ++#define CFG_DDR_SIZE 64 /* MB */ ++#define CFG_DDR_CS0_CONFIG 0x80840101 ++#define CFG_DDR_TIMING_0 0x00220802 ++#define CFG_DDR_TIMING_1 0x3935d322 ++#define CFG_DDR_TIMING_2 0x0f9048ca ++#define CFG_DDR_TIMING_3 0x00000000 ++#define CFG_DDR_CLK_CNTL 0x02000000 ++#define CFG_DDR_MODE 0x44400232 ++#define CFG_DDR_MODE2 0x8000c000 ++#define CFG_DDR_INTERVAL 0x03200064 ++#define CFG_DDR_CS0_BNDS 0x00000003 ++#define CFG_DDR_SDRAM_CFG 0x43080000 ++#define CFG_DDR_SDRAM_CFG2 0x00401000 ++#endif ++ ++/* ++ * Memory test ++ */ ++#undef CFG_DRAM_TEST /* memory test, takes time */ ++#define CFG_MEMTEST_START 0x00030000 /* memtest region */ ++#define CFG_MEMTEST_END 0x03f00000 ++ ++/* ++ * The reserved memory ++ */ ++#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ ++ ++#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) ++#define CFG_RAMBOOT ++#else ++#undef CFG_RAMBOOT ++#endif ++ ++#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ ++#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ ++ ++/* ++ * Initial RAM Base Address Setup ++ */ ++#define CFG_INIT_RAM_LOCK 1 ++#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ ++#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ ++#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ ++#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) ++ ++/* ++ * Local Bus Configuration & Clock Setup ++ */ ++#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) ++#define CFG_LBC_LBCR 0x00000000 ++ ++/* ++ * FLASH on the Local Bus ++ */ ++#define CFG_FLASH_CFI /* use the Common Flash Interface */ ++#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ ++#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ ++#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */ ++ ++#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ ++#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ ++ ++#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ ++ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ ++ BR_V) /* valid */ ++#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ ++ ++#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ ++#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ ++ ++#undef CFG_FLASH_CHECKSUM ++ ++/* ++ * SDRAM on the Local Bus ++ */ ++#undef CFG_LB_SDRAM /* The board has not SRDAM on local bus */ ++ ++#ifdef CFG_LB_SDRAM ++#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ ++#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ ++ ++#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE ++#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ ++ ++/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ ++/* ++ * Base Register 2 and Option Register 2 configure SDRAM. ++ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. ++ * ++ * For BR2, need: ++ * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 ++ * port size = 32-bits = BR2[19:20] = 11 ++ * no parity checking = BR2[21:22] = 00 ++ * SDRAM for MSEL = BR2[24:26] = 011 ++ * Valid = BR[31] = 1 ++ * ++ * 0 4 8 12 16 20 24 28 ++ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 ++ * ++ * CFG_LBC_SDRAM_BASE should be masked and OR'ed into ++ * the top 17 bits of BR2. ++ */ ++ ++#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ ++ ++/* ++ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. ++ * ++ * For OR2, need: ++ * 64MB mask for AM, OR2[0:7] = 1111 1100 ++ * XAM, OR2[17:18] = 11 ++ * 9 columns OR2[19-21] = 010 ++ * 13 rows OR2[23-25] = 100 ++ * EAD set for extra time OR[31] = 1 ++ * ++ * 0 4 8 12 16 20 24 28 ++ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 ++ */ ++ ++#define CFG_OR2_PRELIM 0xfc006901 ++ ++#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ ++#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ ++ ++/* ++ * LSDMR masks ++ */ ++#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) ++ ++#define CFG_LBC_LSDMR_COMMON 0x0063b723 ++ ++/* ++ * SDRAM Controller configuration sequence. ++ */ ++#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ ++ | CFG_LBC_LSDMR_OP_PCHALL) ++#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ ++ | CFG_LBC_LSDMR_OP_ARFRSH) ++#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ ++ | CFG_LBC_LSDMR_OP_ARFRSH) ++#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ ++ | CFG_LBC_LSDMR_OP_MRW) ++#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ ++ | CFG_LBC_LSDMR_OP_NORMAL) ++ ++#endif ++ ++/* ++ * Windows to access PIB via local bus ++ */ ++#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ ++#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ ++ ++/* ++ * Serial Port ++ */ ++#define CONFIG_CONS_INDEX 1 ++#undef CONFIG_SERIAL_SOFTWARE_FIFO ++#define CFG_NS16550 ++#define CFG_NS16550_SERIAL ++#define CFG_NS16550_REG_SIZE 1 ++#define CFG_NS16550_CLK get_bus_freq(0) ++ ++#define CFG_BAUDRATE_TABLE \ ++ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} ++ ++#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) ++#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) ++ ++/* Use the HUSH parser */ ++#define CFG_HUSH_PARSER ++#ifdef CFG_HUSH_PARSER ++#define CFG_PROMPT_HUSH_PS2 "> " ++#endif ++ ++/* pass open firmware flat tree */ ++#define CONFIG_OF_FLAT_TREE 1 ++#define CONFIG_OF_BOARD_SETUP 1 ++ ++/* maximum size of the flat tree (8K) */ ++#define OF_FLAT_TREE_MAX_SIZE 8192 ++ ++#define OF_CPU "PowerPC,8323@0" ++#define OF_SOC "soc8323@e0000000" ++#define OF_TBCLK (bd->bi_busfreq / 4) ++#define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500" ++ ++/* I2C */ ++#define CONFIG_HARD_I2C /* I2C with hardware support */ ++#undef CONFIG_SOFT_I2C /* I2C bit-banged */ ++#define CONFIG_FSL_I2C ++#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ ++#define CFG_I2C_SLAVE 0x7F ++#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ ++#define CFG_I2C_OFFSET 0x3000 ++ ++/* ++ * Config on-board RTC ++ */ ++#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ ++#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ ++ ++/* ++ * General PCI ++ * Addresses are mapped 1-1. ++ */ ++#define CFG_PCI_MEM_BASE 0x80000000 ++#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE ++#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ ++#define CFG_PCI_MMIO_BASE 0x90000000 ++#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE ++#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ ++#define CFG_PCI_IO_BASE 0xd0000000 ++#define CFG_PCI_IO_PHYS CFG_PCI_IO_BASE ++#define CFG_PCI_IO_SIZE 0x04000000 /* 64M */ ++ ++#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE ++#define CFG_PCI_SLV_MEM_BUS 0x00000000 ++#define CFG_PCI_SLV_MEM_SIZE 0x80000000 ++ ++ ++#ifdef CONFIG_PCI ++ ++#define CONFIG_NET_MULTI ++#define CONFIG_PCI_PNP /* do pci plug-and-play */ ++ ++#undef CONFIG_EEPRO100 ++#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ ++#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ ++ ++#endif /* CONFIG_PCI */ ++ ++ ++#ifndef CONFIG_NET_MULTI ++#define CONFIG_NET_MULTI 1 ++#endif ++ ++/* ++ * QE UEC ethernet configuration ++ */ ++#define CONFIG_UEC_ETH ++#define CONFIG_ETHPRIME "Freescale GETH" ++ ++#define CONFIG_UEC_ETH1 /* ETH3 */ ++ ++#ifdef CONFIG_UEC_ETH1 ++#define CFG_UEC1_UCC_NUM 2 /* UCC3 */ ++#define CFG_UEC1_RX_CLK QE_CLK9 ++#define CFG_UEC1_TX_CLK QE_CLK10 ++#define CFG_UEC1_ETH_TYPE FAST_ETH ++#define CFG_UEC1_PHY_ADDR 4 ++#define CFG_UEC1_INTERFACE_MODE ENET_100_MII ++#endif ++ ++#define CONFIG_UEC_ETH2 /* ETH4 */ ++ ++#ifdef CONFIG_UEC_ETH2 ++#define CFG_UEC2_UCC_NUM 1 /* UCC2 */ ++#define CFG_UEC2_RX_CLK QE_CLK16 ++#define CFG_UEC2_TX_CLK QE_CLK3 ++#define CFG_UEC2_ETH_TYPE FAST_ETH ++#define CFG_UEC2_PHY_ADDR 0 ++#define CFG_UEC2_INTERFACE_MODE ENET_100_MII ++#endif ++ ++/* ++ * Environment ++ */ ++#ifndef CFG_RAMBOOT ++ #define CFG_ENV_IS_IN_FLASH 1 ++ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) ++ #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ ++ #define CFG_ENV_SIZE 0x2000 ++#else ++ #define CFG_NO_FLASH 1 /* Flash is not usable now */ ++ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ ++ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) ++ #define CFG_ENV_SIZE 0x2000 ++#endif ++ ++#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ ++#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ ++ ++#if defined(CFG_RAMBOOT) ++#if defined(CONFIG_PCI) ++#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ ++ | CFG_CMD_PING \ ++ | CFG_CMD_ASKENV \ ++ | CFG_CMD_PCI \ ++ | CFG_CMD_I2C) \ ++ & \ ++ ~(CFG_CMD_ENV \ ++ | CFG_CMD_LOADS)) ++#else ++#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ ++ | CFG_CMD_PING \ ++ | CFG_CMD_ASKENV \ ++ | CFG_CMD_I2C) \ ++ & \ ++ ~(CFG_CMD_ENV \ ++ | CFG_CMD_LOADS)) ++#endif ++#else ++#if defined(CONFIG_PCI) ++#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ ++ | CFG_CMD_PCI \ ++ | CFG_CMD_PING \ ++ | CFG_CMD_ASKENV \ ++ | CFG_CMD_I2C) ++#else ++#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ ++ | CFG_CMD_PING \ ++ | CFG_CMD_ASKENV \ ++ | CFG_CMD_I2C ) ++#endif ++#endif ++ ++#include ++ ++#undef CONFIG_WATCHDOG /* watchdog disabled */ ++ ++/* ++ * Miscellaneous configurable options ++ */ ++#define CFG_LONGHELP /* undef to save memory */ ++#define CFG_LOAD_ADDR 0x2000000 /* default load address */ ++#define CFG_PROMPT "=> " /* Monitor Command Prompt */ ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ ++#else ++ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ ++#endif ++ ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ ++#define CFG_MAXARGS 16 /* max number of command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ ++#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ ++ ++/* ++ * For booting Linux, the board info and command line data ++ * have to be in the first 8 MB of memory, since this is ++ * the maximum mapped by the Linux kernel during initialization. ++ */ ++#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ ++ ++/* ++ * Core HID Setup ++ */ ++#define CFG_HID0_INIT 0x000000000 ++#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK ++#define CFG_HID2 HID2_HBE ++ ++/* ++ * Cache Config ++ */ ++#define CFG_DCACHE_SIZE 16384 ++#define CFG_CACHELINE_SIZE 32 ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ ++#endif ++ ++/* ++ * MMU Setup ++ */ ++ ++/* DDR: cache cacheable */ ++#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) ++#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) ++#define CFG_DBAT0L CFG_IBAT0L ++#define CFG_DBAT0U CFG_IBAT0U ++ ++/* IMMRBAR & PCI IO: cache-inhibit and guarded */ ++#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ ++ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) ++#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) ++#define CFG_DBAT1L CFG_IBAT1L ++#define CFG_DBAT1U CFG_IBAT1U ++ ++/* FLASH: icache cacheable, but dcache-inhibit and guarded */ ++#define CFG_IBAT2L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) ++#define CFG_IBAT2U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) ++#define CFG_DBAT2L (CFG_FLASH_BASE | BATL_PP_10 | \ ++ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) ++#define CFG_DBAT2U CFG_IBAT2U ++ ++#define CFG_IBAT3L (0) ++#define CFG_IBAT3U (0) ++#define CFG_DBAT3L CFG_IBAT3L ++#define CFG_DBAT3U CFG_IBAT3U ++ ++/* Stack in dcache: cacheable, no memory coherence */ ++#define CFG_IBAT4L (CFG_INIT_RAM_ADDR | BATL_PP_10) ++#define CFG_IBAT4U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) ++#define CFG_DBAT4L CFG_IBAT4L ++#define CFG_DBAT4U CFG_IBAT4U ++ ++#ifdef CONFIG_PCI ++/* PCI MEM space: cacheable */ ++#define CFG_IBAT5L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) ++#define CFG_IBAT5U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) ++#define CFG_DBAT5L CFG_IBAT5L ++#define CFG_DBAT5U CFG_IBAT5U ++/* PCI MMIO space: cache-inhibit and guarded */ ++#define CFG_IBAT6L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ ++ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) ++#define CFG_IBAT6U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) ++#define CFG_DBAT6L CFG_IBAT6L ++#define CFG_DBAT6U CFG_IBAT6U ++#else ++#define CFG_IBAT5L (0) ++#define CFG_IBAT5U (0) ++#define CFG_IBAT6L (0) ++#define CFG_IBAT6U (0) ++#define CFG_DBAT5L CFG_IBAT5L ++#define CFG_DBAT5U CFG_IBAT5U ++#define CFG_DBAT6L CFG_IBAT6L ++#define CFG_DBAT6U CFG_IBAT6U ++#endif ++ ++/* Nothing in BAT7 */ ++#define CFG_IBAT7L (0) ++#define CFG_IBAT7U (0) ++#define CFG_DBAT7L CFG_IBAT7L ++#define CFG_DBAT7U CFG_IBAT7U ++ ++/* ++ * Internal Definitions ++ * ++ * Boot Flags ++ */ ++#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ ++#define BOOTFLAG_WARM 0x02 /* Software reboot */ ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ ++#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ ++#endif ++ ++/* ++ * Environment Configuration ++ */ ++ ++#define CONFIG_ENV_OVERWRITE ++ ++#if defined(CONFIG_UEC_ETH) ++#define CONFIG_ETHADDR 00:04:9f:ef:03:01 ++#define CONFIG_HAS_ETH1 ++#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02 ++#endif ++ ++#define CONFIG_BAUDRATE 115200 ++ ++#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ ++ ++#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ ++#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "netdev=eth0\0" \ ++ "consoledev=ttyS0\0" \ ++ "bootfile=uImage\0" \ ++ "ramdiskaddr=1000000\0" \ ++ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ ++ "fdtaddr=400000\0" \ ++ "fdtfile=mpc832x_rdb.dtb\0" \ ++ "" ++ ++#define CONFIG_NFSBOOTCOMMAND \ ++ "setenv bootargs root=/dev/nfs rw " \ ++ "nfsroot=$serverip:$rootpath " \ ++ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ ++ "console=$consoledev,$baudrate $othbootargs;" \ ++ "tftp $loadaddr $bootfile;" \ ++ "tftp $fdtaddr $fdtfile;" \ ++ "bootm $loadaddr - $fdtaddr" ++ ++#define CONFIG_RAMBOOTCOMMAND \ ++ "setenv bootargs root=/dev/ram rw " \ ++ "console=$consoledev,$baudrate $othbootargs;" \ ++ "tftp $ramdiskaddr $ramdiskfile;" \ ++ "tftp $loadaddr $bootfile;" \ ++ "tftp $fdtaddr $fdtfile;" \ ++ "bootm $loadaddr $ramdiskaddr $fdtaddr" ++ ++ ++#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND ++ ++#endif /* __CONFIG_H */ diff --git a/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Fix-the-UEC-driver-bug-of-QE.patch b/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Fix-the-UEC-driver-bug-of-QE.patch new file mode 100644 index 0000000000..ad2ff243e8 --- /dev/null +++ b/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Fix-the-UEC-driver-bug-of-QE.patch @@ -0,0 +1,62 @@ +21fb83dfa2dcba7982eeb54f4ca7bc1056582c1e +diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c +index f640c81..c44a5be 100644 +--- a/drivers/qe/uec.c ++++ b/drivers/qe/uec.c +@@ -1122,7 +1122,7 @@ static int uec_send(struct eth_device* dev, volatile void *buf, int len) + uec_private_t *uec; + ucc_fast_private_t *uccf; + volatile qe_bd_t *bd; +- volatile u16 status; ++ u16 status; + int i; + int result = 0; + +@@ -1131,7 +1131,7 @@ static int uec_send(struct eth_device* dev, volatile void *buf, int len) + bd = uec->txBd; + + /* Find an empty TxBD */ +- for (i = 0; BD_STATUS(bd) & TxBD_READY; i++) { ++ for (i = 0; bd->status & TxBD_READY; i++) { + if (i > 0x100000) { + printf("%s: tx buffer not ready\n", dev->name); + return result; +@@ -1150,13 +1150,11 @@ static int uec_send(struct eth_device* dev, volatile void *buf, int len) + ucc_fast_transmit_on_demand(uccf); + + /* Wait for buffer to be transmitted */ +- status = BD_STATUS(bd); +- for (i = 0; status & TxBD_READY; i++) { ++ for (i = 0; bd->status & TxBD_READY; i++) { + if (i > 0x100000) { + printf("%s: tx error\n", dev->name); + return result; + } +- status = BD_STATUS(bd); + } + + /* Ok, the buffer be transimitted */ +@@ -1171,12 +1169,12 @@ static int uec_recv(struct eth_device* dev) + { + uec_private_t *uec = dev->priv; + volatile qe_bd_t *bd; +- volatile u16 status; ++ u16 status; + u16 len; + u8 *data; + + bd = uec->rxBd; +- status = BD_STATUS(bd); ++ status = bd->status; + + while (!(status & RxBD_EMPTY)) { + if (!(status & RxBD_ERROR)) { +@@ -1190,7 +1188,7 @@ static int uec_recv(struct eth_device* dev) + BD_LENGTH_SET(bd, 0); + BD_STATUS_SET(bd, status | RxBD_EMPTY); + BD_ADVANCE(bd, status, uec->p_rx_bd_ring); +- status = BD_STATUS(bd); ++ status = bd->status; + } + uec->rxBd = bd; + diff --git a/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-UEC-remove-udelay.patch b/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-UEC-remove-udelay.patch new file mode 100644 index 0000000000..9e2829bd3e --- /dev/null +++ b/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-UEC-remove-udelay.patch @@ -0,0 +1,15 @@ +123b7d94ab4fa50a62aa9c0c0202d4e2c99a14c8 +diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c +index aea455b..a327a34 100644 +--- a/drivers/qe/uec.c ++++ b/drivers/qe/uec.c +@@ -567,9 +567,6 @@ static void phy_change(struct eth_device *dev) + + uec_regs = uec->uec_regs; + +- /* Delay 5s to give the PHY a chance to change the register state */ +- udelay(5000000); +- + /* Update the link, speed, duplex */ + result = uec->mii_info->phyinfo->read_status(uec->mii_info); + diff --git a/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-mpc83xx-20061206.patch b/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-mpc83xx-20061206.patch new file mode 100644 index 0000000000..5f3e1f7aaa --- /dev/null +++ b/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-mpc83xx-20061206.patch @@ -0,0 +1,32020 @@ +This patch, when applied against the external pristine +tarball u-boot-1.1.6.tar.bz2, makes the u-boot code match the git tree +with sha1 dd520bf314c7add4183c5191692180f576f96b60, +in the repository http://opensource.freescale.com/pub/scm/u-boot-83xx.git. +This git tag is identified for this code baseline: u-boot-1.1.6-fsl-1 + +The patch includes support changes for mpc8349itx, mpc8349emds, and mpc8360emds +as well as many other changes as of November 30, 2006. + +diff -Naupr u-boot-1.1.6/board/amcc/yellowstone/yellowstone.c u-boot-1.1.6-fsl-1/board/amcc/yellowstone/yellowstone.c +--- u-boot-1.1.6/board/amcc/yellowstone/yellowstone.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/amcc/yellowstone/yellowstone.c 2006-11-30 12:34:13.000000000 -0600 +@@ -552,3 +552,9 @@ void hw_watchdog_reset(void) + + } + #endif ++ ++void board_reset(void) ++{ ++ /* give reset to BCSR */ ++ *(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09; ++} +diff -Naupr u-boot-1.1.6/board/amcc/yosemite/yosemite.c u-boot-1.1.6-fsl-1/board/amcc/yosemite/yosemite.c +--- u-boot-1.1.6/board/amcc/yosemite/yosemite.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/amcc/yosemite/yosemite.c 2006-11-30 12:34:13.000000000 -0600 +@@ -548,3 +548,9 @@ void hw_watchdog_reset(void) + + } + #endif ++ ++void board_reset(void) ++{ ++ /* give reset to BCSR */ ++ *(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09; ++} +diff -Naupr u-boot-1.1.6/board/bc3450/bc3450.c u-boot-1.1.6-fsl-1/board/bc3450/bc3450.c +--- u-boot-1.1.6/board/bc3450/bc3450.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/bc3450/bc3450.c 2006-11-10 11:24:28.000000000 -0600 +@@ -295,7 +295,6 @@ void pci_init_board(void) + #endif + + #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) +-#define GPIO_PSC1_4 0x01000000UL + + void init_ide_reset (void) + { +@@ -311,9 +310,9 @@ void ide_set_reset (int idereset) + debug ("ide_reset(%d)\n", idereset); + + if (idereset) { +- *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; + } else { +- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; + } + } + #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ +diff -Naupr u-boot-1.1.6/board/BuS/EB+MCF-EV123/cfm_flash.c u-boot-1.1.6-fsl-1/board/BuS/EB+MCF-EV123/cfm_flash.c +--- u-boot-1.1.6/board/BuS/EB+MCF-EV123/cfm_flash.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/BuS/EB+MCF-EV123/cfm_flash.c 2006-12-06 10:33:49.000000000 -0600 +@@ -60,7 +60,7 @@ void cfm_flash_init (flash_info_t * info + MCFCFM_MCR = 0; + MCFCFM_CLKD = CFM_CLK; + debug ("CFM Clock divider: %ld (%d Hz @ %ld Hz)\n",CFM_CLK,\ +- CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\ ++ CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\ + CFG_CLK); + MCFCFM_SACC = 0; + MCFCFM_DACC = 0; +diff -Naupr u-boot-1.1.6/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c u-boot-1.1.6-fsl-1/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c +--- u-boot-1.1.6/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c 2006-12-06 10:33:49.000000000 -0600 +@@ -50,13 +50,13 @@ long int initdram (int board_type) + + MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE0) + | MCFSDRAMC_DACR_CASL(1) +- | MCFSDRAMC_DACR_CBM(3) ++ | MCFSDRAMC_DACR_CBM(3) + | MCFSDRAMC_DACR_PS_16); + + MCFSDRAMC_DMR0 = MCFSDRAMC_DMR_BAM_16M + | MCFSDRAMC_DMR_V; + +- MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; ++ MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; + + *(unsigned short *)(CFG_SDRAM_BASE0) = 0xA5A5; + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; +@@ -70,10 +70,10 @@ long int initdram (int board_type) + #ifdef CFG_SDRAM_BASE1 + MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE1) + | MCFSDRAMC_DACR_CASL(1) +- | MCFSDRAMC_DACR_CBM(3) ++ | MCFSDRAMC_DACR_CBM(3) + | MCFSDRAMC_DACR_PS_16; + +- MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M ++ MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M + | MCFSDRAMC_DMR_V; + + MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP; +@@ -82,7 +82,7 @@ long int initdram (int board_type) + MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE; + for (i=0; i < 2000; i++) + asm(" nop"); +- MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS; ++ MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS; + *(unsigned int *)(CFG_SDRAM_BASE1 + 0x220) = 0xA5A5; + size += CFG_SDRAM_SIZE1 * 1024 * 1024; + #endif +diff -Naupr u-boot-1.1.6/board/BuS/EB+MCF-EV123/flash.c u-boot-1.1.6-fsl-1/board/BuS/EB+MCF-EV123/flash.c +--- u-boot-1.1.6/board/BuS/EB+MCF-EV123/flash.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/BuS/EB+MCF-EV123/flash.c 2006-12-06 10:33:49.000000000 -0600 +@@ -256,7 +256,7 @@ int flash_erase (flash_info_t * info, in + enable_interrupts (); + + if (cflag) +- icache_enable (); ++ icache_enable (); + + return rc; + } +diff -Naupr u-boot-1.1.6/board/BuS/EB+MCF-EV123/u-boot.lds u-boot-1.1.6-fsl-1/board/BuS/EB+MCF-EV123/u-boot.lds +--- u-boot-1.1.6/board/BuS/EB+MCF-EV123/u-boot.lds 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/BuS/EB+MCF-EV123/u-boot.lds 2006-12-06 10:33:49.000000000 -0600 +@@ -34,11 +34,11 @@ SECTIONS + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } +- .rela.text : { *(.rela.text) } ++ .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } +- .rela.data : { *(.rela.data) } +- .rel.rodata : { *(.rel.rodata) } +- .rela.rodata : { *(.rela.rodata) } ++ .rela.data : { *(.rela.data) } ++ .rel.rodata : { *(.rel.rodata) } ++ .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } +diff -Naupr u-boot-1.1.6/board/BuS/EB+MCF-EV123/VCxK.c u-boot-1.1.6-fsl-1/board/BuS/EB+MCF-EV123/VCxK.c +--- u-boot-1.1.6/board/BuS/EB+MCF-EV123/VCxK.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/BuS/EB+MCF-EV123/VCxK.c 2006-12-06 10:33:49.000000000 -0600 +@@ -66,7 +66,7 @@ int init_vcxk(void) + return 1; + } + +-void vcxk_loadimage(ulong source) ++void vcxk_loadimage(ulong source) + { + int cnt; + vcxk_acknowledge_wait(); +diff -Naupr u-boot-1.1.6/board/BuS/EB+MCF-EV123/VCxK.h u-boot-1.1.6-fsl-1/board/BuS/EB+MCF-EV123/VCxK.h +--- u-boot-1.1.6/board/BuS/EB+MCF-EV123/VCxK.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/BuS/EB+MCF-EV123/VCxK.h 2006-12-06 10:33:49.000000000 -0600 +@@ -25,24 +25,24 @@ + #define __VCXK_H_ + + extern int init_vcxk(void); +-void vcxk_loadimage(ulong source); ++void vcxk_loadimage(ulong source); + + #define VIDEO_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT +-#define VIDEO_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR ++#define VIDEO_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR + #define VIDEO_ACKNOWLEDGE_PIN 0x0001 + +-#define VIDEO_ENABLE_PORT MCFGPTB_GPTPORT +-#define VIDEO_ENABLE_DDR MCFGPTB_GPTDDR ++#define VIDEO_ENABLE_PORT MCFGPTB_GPTPORT ++#define VIDEO_ENABLE_DDR MCFGPTB_GPTDDR + #define VIDEO_ENABLE_PIN 0x0002 + +-#define VIDEO_REQUEST_PORT MCFGPTB_GPTPORT +-#define VIDEO_REQUEST_DDR MCFGPTB_GPTDDR ++#define VIDEO_REQUEST_PORT MCFGPTB_GPTPORT ++#define VIDEO_REQUEST_DDR MCFGPTB_GPTDDR + #define VIDEO_REQUEST_PIN 0x0004 + + #define VIDEO_Invert_CFG MCFGPIO_PEPAR + #define VIDEO_Invert_IO MCFGPIO_PEPAR_PEPA2 +-#define VIDEO_INVERT_PORT MCFGPIO_PORTE +-#define VIDEO_INVERT_DDR MCFGPIO_DDRE ++#define VIDEO_INVERT_PORT MCFGPIO_PORTE ++#define VIDEO_INVERT_DDR MCFGPIO_DDRE + #define VIDEO_INVERT_PIN MCFGPIO_PORT2 + + #endif +diff -Naupr u-boot-1.1.6/board/emk/top5200/top5200.c u-boot-1.1.6-fsl-1/board/emk/top5200/top5200.c +--- u-boot-1.1.6/board/emk/top5200/top5200.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/emk/top5200/top5200.c 2006-12-06 10:33:49.000000000 -0600 +@@ -186,13 +186,11 @@ void pci_init_board(void) + *****************************************************************************/ + #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +-#define GPIO_PSC1_4 0x01000000UL +- + void init_ide_reset (void) + { + debug ("init_ide_reset\n"); + +- /* Configure PSC1_4 as GPIO output for ATA reset */ ++ /* Configure PSC1_4 as GPIO output for ATA reset */ + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; + } +@@ -202,9 +200,9 @@ void ide_set_reset (int idereset) + debug ("ide_reset(%d)\n", idereset); + + if (idereset) { +- *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; + } else { +- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; + } + } + #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ +diff -Naupr u-boot-1.1.6/board/esd/cpci5200/cpci5200.c u-boot-1.1.6-fsl-1/board/esd/cpci5200/cpci5200.c +--- u-boot-1.1.6/board/esd/cpci5200/cpci5200.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/esd/cpci5200/cpci5200.c 2006-12-06 10:33:49.000000000 -0600 +@@ -191,16 +191,13 @@ static struct pci_controller hose; + + extern void pci_mpc5xxx_init(struct pci_controller *); + +-void pci_init_board(void +- ) { ++void pci_init_board(void) { + pci_mpc5xxx_init(&hose); + } + #endif + + #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +-#define GPIO_PSC1_4 0x01000000UL +- + void init_ide_reset(void) + { + debug("init_ide_reset\n"); +@@ -215,9 +212,9 @@ void ide_set_reset(int idereset) + debug("ide_reset(%d)\n", idereset); + + if (idereset) { +- *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; + } else { +- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; + } + } + #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ +@@ -242,7 +239,7 @@ void init_ata_reset(void) + debug("init_ata_reset\n"); + + /* Configure GPIO_WU6 as GPIO output for ATA reset */ +- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6; + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6; + __asm__ volatile ("sync"); +diff -Naupr u-boot-1.1.6/board/esd/pf5200/pf5200.c u-boot-1.1.6-fsl-1/board/esd/pf5200/pf5200.c +--- u-boot-1.1.6/board/esd/pf5200/pf5200.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/esd/pf5200/pf5200.c 2006-12-06 10:33:49.000000000 -0600 +@@ -191,16 +191,13 @@ static struct pci_controller hose; + + extern void pci_mpc5xxx_init(struct pci_controller *); + +-void pci_init_board(void +- ) { ++void pci_init_board(void) { + pci_mpc5xxx_init(&hose); + } + #endif + + #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +-#define GPIO_PSC1_4 0x01000000UL +- + void init_ide_reset(void) + { + debug("init_ide_reset\n"); +@@ -215,9 +212,9 @@ void ide_set_reset(int idereset) + debug("ide_reset(%d)\n", idereset); + + if (idereset) { +- *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; + } else { +- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; + } + } + #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ +@@ -242,7 +239,7 @@ void init_power_switch(void) + debug("init_power_switch\n"); + + /* Configure GPIO_WU6 as GPIO output for ATA reset */ +- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6; + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6; + __asm__ volatile ("sync"); +@@ -272,10 +269,10 @@ void power_set_reset(int power) + debug("ide_set_reset(%d)\n", power); + + if (power) { +- *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_WU6; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_WU6; + *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9; + } else { +- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6; + if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == + 0) { + *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= +diff -Naupr u-boot-1.1.6/board/icecube/icecube.c u-boot-1.1.6-fsl-1/board/icecube/icecube.c +--- u-boot-1.1.6/board/icecube/icecube.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/icecube/icecube.c 2006-12-06 10:33:49.000000000 -0600 +@@ -29,6 +29,10 @@ + #include + #include + ++#if defined(CONFIG_OF_FLAT_TREE) ++#include ++#endif ++ + #if defined(CONFIG_LITE5200B) + #include "mt46v32m16.h" + #else +@@ -308,17 +312,15 @@ void pci_init_board(void) + + #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +-#define GPIO_PSC1_4 0x01000000UL +- + void init_ide_reset (void) + { + debug ("init_ide_reset\n"); + +- /* Configure PSC1_4 as GPIO output for ATA reset */ ++ /* Configure PSC1_4 as GPIO output for ATA reset */ + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; + /* Deassert reset */ +- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; + } + + void ide_set_reset (int idereset) +@@ -326,11 +328,19 @@ void ide_set_reset (int idereset) + debug ("ide_reset(%d)\n", idereset); + + if (idereset) { +- *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; + /* Make a delay. MPC5200 spec says 25 usec min */ + udelay(500000); + } else { +- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; + } + } + #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ ++ ++#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) ++void ++ft_board_setup(void *blob, bd_t *bd) ++{ ++ ft_cpu_setup(blob, bd); ++} ++#endif +diff -Naupr u-boot-1.1.6/board/inka4x0/inka4x0.c u-boot-1.1.6-fsl-1/board/inka4x0/inka4x0.c +--- u-boot-1.1.6/board/inka4x0/inka4x0.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/inka4x0/inka4x0.c 2006-11-10 11:24:28.000000000 -0600 +@@ -173,9 +173,6 @@ void flash_preinit(void) + *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ + } + +-#define GPIO_WKUP_7 0x80000000UL +-#define GPIO_PSC3_9 0x04000000UL +- + int misc_init_f (void) + { + uchar tmp[10]; +@@ -218,13 +215,13 @@ int misc_init_f (void) + *(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000; + + /* Set LR mirror bit because it is low-active */ +- *(vu_long *)MPC5XXX_WU_GPIO_DATA |= GPIO_WKUP_7; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WKUP_7; + /* + * Reset Coral-P graphics controller + */ + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9; +- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC3_9; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC3_9; + return 0; + } + +@@ -241,8 +238,6 @@ void pci_init_board(void) + + #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +-#define GPIO_PSC1_4 0x01000000UL +- + void init_ide_reset (void) + { + debug ("init_ide_reset\n"); +@@ -251,7 +246,7 @@ void init_ide_reset (void) + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; + /* Deassert reset */ +- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; + } + + void ide_set_reset (int idereset) +@@ -259,11 +254,11 @@ void ide_set_reset (int idereset) + debug ("ide_reset(%d)\n", idereset); + + if (idereset) { +- *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; + /* Make a delay. MPC5200 spec says 25 usec min */ + udelay(500000); + } else { +- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; + } + } + #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ +diff -Naupr u-boot-1.1.6/board/LEOX/elpt860/u-boot.lds u-boot-1.1.6-fsl-1/board/LEOX/elpt860/u-boot.lds +--- u-boot-1.1.6/board/LEOX/elpt860/u-boot.lds 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/LEOX/elpt860/u-boot.lds 2006-12-06 10:33:49.000000000 -0600 +@@ -43,11 +43,11 @@ SECTIONS + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } +- .rela.text : { *(.rela.text) } ++ .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } +- .rela.data : { *(.rela.data) } +- .rel.rodata : { *(.rel.rodata) } +- .rela.rodata : { *(.rela.rodata) } ++ .rela.data : { *(.rela.data) } ++ .rel.rodata : { *(.rel.rodata) } ++ .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } +diff -Naupr u-boot-1.1.6/board/LEOX/elpt860/u-boot.lds.debug u-boot-1.1.6-fsl-1/board/LEOX/elpt860/u-boot.lds.debug +--- u-boot-1.1.6/board/LEOX/elpt860/u-boot.lds.debug 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/LEOX/elpt860/u-boot.lds.debug 2006-12-06 10:33:49.000000000 -0600 +@@ -43,11 +43,11 @@ SECTIONS + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } +- .rela.text : { *(.rela.text) } ++ .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } +- .rela.data : { *(.rela.data) } +- .rel.rodata : { *(.rel.rodata) } +- .rela.rodata : { *(.rela.rodata) } ++ .rela.data : { *(.rela.data) } ++ .rel.rodata : { *(.rel.rodata) } ++ .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } +diff -Naupr u-boot-1.1.6/board/MAI/AmigaOneG3SE/articiaS_pci.c u-boot-1.1.6-fsl-1/board/MAI/AmigaOneG3SE/articiaS_pci.c +--- u-boot-1.1.6/board/MAI/AmigaOneG3SE/articiaS_pci.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/MAI/AmigaOneG3SE/articiaS_pci.c 2006-12-06 10:33:49.000000000 -0600 +@@ -368,11 +368,11 @@ void articiaS_pci_init (void) + if (articiaS_init_vga() == -1) + { + /* If the VGA didn't init and we have stdout set to VGA, reset to serial */ +-/* s = getenv("stdout"); */ +-/* if (s && strcmp(s, "vga") == 0) */ +-/* { */ +-/* setenv("stdout", "serial"); */ +-/* } */ ++/* s = getenv("stdout"); */ ++/* if (s && strcmp(s, "vga") == 0) */ ++/* { */ ++/* setenv("stdout", "serial"); */ ++/* } */ + } + } + pci_write_config_byte(PCI_BDF(0,1,0), PCI_INTERRUPT_LINE, 0xFF); +diff -Naupr u-boot-1.1.6/board/MAI/AmigaOneG3SE/enet.c u-boot-1.1.6-fsl-1/board/MAI/AmigaOneG3SE/enet.c +--- u-boot-1.1.6/board/MAI/AmigaOneG3SE/enet.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/MAI/AmigaOneG3SE/enet.c 2006-12-06 10:33:49.000000000 -0600 +@@ -41,57 +41,57 @@ + + /* 3Com Commands, top 5 bits are command and bottom 11 bits are parameters */ + +-#define TotalReset (0<<11) +-#define SelectWindow (1<<11) +-#define StartCoax (2<<11) +-#define RxDisable (3<<11) +-#define RxEnable (4<<11) +-#define RxReset (5<<11) +-#define UpStall (6<<11) +-#define UpUnstall (6<<11)+1 +-#define DownStall (6<<11)+2 +-#define DownUnstall (6<<11)+3 +-#define RxDiscard (8<<11) +-#define TxEnable (9<<11) +-#define TxDisable (10<<11) +-#define TxReset (11<<11) +-#define FakeIntr (12<<11) +-#define AckIntr (13<<11) +-#define SetIntrEnb (14<<11) +-#define SetStatusEnb (15<<11) +-#define SetRxFilter (16<<11) +-#define SetRxThreshold (17<<11) +-#define SetTxThreshold (18<<11) +-#define SetTxStart (19<<11) +-#define StartDMAUp (20<<11) +-#define StartDMADown (20<<11)+1 ++#define TotalReset (0<<11) ++#define SelectWindow (1<<11) ++#define StartCoax (2<<11) ++#define RxDisable (3<<11) ++#define RxEnable (4<<11) ++#define RxReset (5<<11) ++#define UpStall (6<<11) ++#define UpUnstall (6<<11)+1 ++#define DownStall (6<<11)+2 ++#define DownUnstall (6<<11)+3 ++#define RxDiscard (8<<11) ++#define TxEnable (9<<11) ++#define TxDisable (10<<11) ++#define TxReset (11<<11) ++#define FakeIntr (12<<11) ++#define AckIntr (13<<11) ++#define SetIntrEnb (14<<11) ++#define SetStatusEnb (15<<11) ++#define SetRxFilter (16<<11) ++#define SetRxThreshold (17<<11) ++#define SetTxThreshold (18<<11) ++#define SetTxStart (19<<11) ++#define StartDMAUp (20<<11) ++#define StartDMADown (20<<11)+1 + #define StatsEnable (21<<11) + #define StatsDisable (22<<11) +-#define StopCoax (23<<11) +-#define SetFilterBit (25<<11) ++#define StopCoax (23<<11) ++#define SetFilterBit (25<<11) + + /* The SetRxFilter command accepts the following classes */ + +-#define RxStation 1 ++#define RxStation 1 + #define RxMulticast 2 + #define RxBroadcast 4 +-#define RxProm 8 ++#define RxProm 8 + + /* 3Com status word defnitions */ + +-#define IntLatch 0x0001 +-#define HostError 0x0002 +-#define TxComplete 0x0004 +-#define TxAvailable 0x0008 +-#define RxComplete 0x0010 +-#define RxEarly 0x0020 +-#define IntReq 0x0040 +-#define StatsFull 0x0080 +-#define DMADone (1<<8) +-#define DownComplete (1<<9) +-#define UpComplete (1<<10) +-#define DMAInProgress (1<<11) /* DMA controller is still busy.*/ +-#define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/ ++#define IntLatch 0x0001 ++#define HostError 0x0002 ++#define TxComplete 0x0004 ++#define TxAvailable 0x0008 ++#define RxComplete 0x0010 ++#define RxEarly 0x0020 ++#define IntReq 0x0040 ++#define StatsFull 0x0080 ++#define DMADone (1<<8) ++#define DownComplete (1<<9) ++#define UpComplete (1<<10) ++#define DMAInProgress (1<<11) /* DMA controller is still busy.*/ ++#define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/ + + /* Polling Registers */ + +@@ -100,17 +100,17 @@ + + /* Register window 0 offets */ + +-#define Wn0EepromCmd 10 /* Window 0: EEPROM command register. */ +-#define Wn0EepromData 12 /* Window 0: EEPROM results register. */ ++#define Wn0EepromCmd 10 /* Window 0: EEPROM command register. */ ++#define Wn0EepromData 12 /* Window 0: EEPROM results register. */ + #define IntrStatus 0x0E /* Valid in all windows. */ + + /* Register window 0 EEPROM bits */ + +-#define EEPROM_Read 0x80 +-#define EEPROM_WRITE 0x40 +-#define EEPROM_ERASE 0xC0 +-#define EEPROM_EWENB 0x30 /* Enable erasing/writing for 10 msec. */ +-#define EEPROM_EWDIS 0x00 /* Disable EWENB before 10 msec timeout. */ ++#define EEPROM_Read 0x80 ++#define EEPROM_WRITE 0x40 ++#define EEPROM_ERASE 0xC0 ++#define EEPROM_EWENB 0x30 /* Enable erasing/writing for 10 msec. */ ++#define EEPROM_EWDIS 0x00 /* Disable EWENB before 10 msec timeout. */ + + /* EEPROM locations. */ + +@@ -129,13 +129,13 @@ + + /* Register window 1 offsets, the window used in normal operation */ + +-#define TX_FIFO 0x10 +-#define RX_FIFO 0x10 +-#define RxErrors 0x14 +-#define RxStatus 0x18 ++#define TX_FIFO 0x10 ++#define RX_FIFOa 0x10 ++#define RxErrors 0x14 ++#define RxStatus 0x18 + #define Timer 0x1A +-#define TxStatus 0x1B +-#define TxFree 0x1C /* Remaining free bytes in Tx buffer. */ ++#define TxStatus 0x1B ++#define TxFree 0x1C /* Remaining free bytes in Tx buffer. */ + + /* Register Window 2 */ + +@@ -147,47 +147,47 @@ + #define Wn3_MAC_Ctrl 6 + #define Wn3_Options 8 + +-#define BFEXT(value, offset, bitcount) \ ++#define BFEXT(value, offset, bitcount) \ + ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1)) + + #define BFINS(lhs, rhs, offset, bitcount) \ +- (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \ ++ (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \ + (((rhs) & ((1 << (bitcount)) - 1)) << (offset))) + + #define RAM_SIZE(v) BFEXT(v, 0, 3) +-#define RAM_WIDTH(v) BFEXT(v, 3, 1) +-#define RAM_SPEED(v) BFEXT(v, 4, 2) ++#define RAM_WIDTH(v) BFEXT(v, 3, 1) ++#define RAM_SPEED(v) BFEXT(v, 4, 2) + #define ROM_SIZE(v) BFEXT(v, 6, 2) +-#define RAM_SPLIT(v) BFEXT(v, 16, 2) ++#define RAM_SPLIT(v) BFEXT(v, 16, 2) + #define XCVR(v) BFEXT(v, 20, 4) +-#define AUTOSELECT(v) BFEXT(v, 24, 1) ++#define AUTOSELECT(v) BFEXT(v, 24, 1) + + /* Register Window 4: Xcvr/media bits */ + +-#define Wn4_FIFODiag 4 +-#define Wn4_NetDiag 6 ++#define Wn4_FIFODiag 4 ++#define Wn4_NetDiag 6 + #define Wn4_PhysicalMgmt 8 +-#define Wn4_Media 10 ++#define Wn4_Media 10 + +-#define Media_SQE 0x0008 /* Enable SQE error counting for AUI. */ +-#define Media_10TP 0x00C0 /* Enable link beat and jabber for 10baseT. */ +-#define Media_Lnk 0x0080 /* Enable just link beat for 100TX/100FX. */ +-#define Media_LnkBeat 0x0800 ++#define Media_SQE 0x0008 /* Enable SQE error counting for AUI. */ ++#define Media_10TP 0x00C0 /* Enable link beat and jabber for 10baseT. */ ++#define Media_Lnk 0x0080 /* Enable just link beat for 100TX/100FX. */ ++#define Media_LnkBeat 0x0800 + + /* Register Window 7: Bus Master control */ + +-#define Wn7_MasterAddr 0 +-#define Wn7_MasterLen 6 +-#define Wn7_MasterStatus 12 ++#define Wn7_MasterAddr 0 ++#define Wn7_MasterLen 6 ++#define Wn7_MasterStatus 12 + + /* Boomerang bus master control registers. */ + +-#define PktStatus 0x20 ++#define PktStatus 0x20 + #define DownListPtr 0x24 +-#define FragAddr 0x28 +-#define FragLen 0x2c ++#define FragAddr 0x28 ++#define FragLen 0x2c + #define TxFreeThreshold 0x2f +-#define UpPktStatus 0x30 ++#define UpPktStatus 0x30 + #define UpListPtr 0x38 + + /* The Rx and Tx descriptor lists. */ +diff -Naupr u-boot-1.1.6/board/MAI/AmigaOneG3SE/Makefile u-boot-1.1.6-fsl-1/board/MAI/AmigaOneG3SE/Makefile +--- u-boot-1.1.6/board/MAI/AmigaOneG3SE/Makefile 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/MAI/AmigaOneG3SE/Makefile 2006-12-06 10:33:49.000000000 -0600 +@@ -30,7 +30,7 @@ endif + LIB = $(obj)lib$(BOARD).a + + COBJS = $(BOARD).o articiaS.o flash.o serial.o smbus.o articiaS_pci.o \ +- via686.o i8259.o ../bios_emulator/x86interface.o \ ++ via686.o i8259.o ../bios_emulator/x86interface.o \ + ../bios_emulator/bios.o ../bios_emulator/glue.o \ + interrupts.o ps2kbd.o video.o usb_uhci.o enet.o \ + ../menu/cmd_menu.o cmd_boota.o nvram.o +diff -Naupr u-boot-1.1.6/board/mcc200/mcc200.c u-boot-1.1.6-fsl-1/board/mcc200/mcc200.c +--- u-boot-1.1.6/board/mcc200/mcc200.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/mcc200/mcc200.c 2006-11-30 12:34:13.000000000 -0600 +@@ -27,6 +27,7 @@ + #include + #include + #include ++#include + + /* Two MT48LC8M32B2 for 32 MB */ + /* #include "mt48lc8m32b2-6-7.h" */ +@@ -98,6 +99,7 @@ long int initdram (int board_type) + { + ulong dramsize = 0; + ulong dramsize2 = 0; ++ uint svr, pvr; + #ifndef CFG_RAMBOOT + ulong test1, test2; + +@@ -192,6 +194,22 @@ long int initdram (int board_type) + + #endif /* CFG_RAMBOOT */ + ++ /* ++ * On MPC5200B we need to set the special configuration delay in the ++ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM ++ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: ++ * ++ * "The SDelay should be written to a value of 0x00000004. It is ++ * required to account for changes caused by normal wafer processing ++ * parameters." ++ */ ++ svr = get_svr(); ++ pvr = get_pvr(); ++ if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { ++ *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; ++ __asm__ volatile ("sync"); ++ } ++ + return dramsize + dramsize2; + } + +diff -Naupr u-boot-1.1.6/board/mpc8349emds/Makefile u-boot-1.1.6-fsl-1/board/mpc8349emds/Makefile +--- u-boot-1.1.6/board/mpc8349emds/Makefile 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/mpc8349emds/Makefile 2006-11-10 11:24:28.000000000 -0600 +@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk + + LIB = $(obj)lib$(BOARD).a + +-COBJS := $(BOARD).o ++COBJS := $(BOARD).o pci.o + + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) + OBJS := $(addprefix $(obj),$(COBJS)) +diff -Naupr u-boot-1.1.6/board/mpc8349emds/mpc8349emds.c u-boot-1.1.6-fsl-1/board/mpc8349emds/mpc8349emds.c +--- u-boot-1.1.6/board/mpc8349emds/mpc8349emds.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/mpc8349emds/mpc8349emds.c 2006-11-10 11:24:28.000000000 -0600 +@@ -33,6 +33,10 @@ + #if defined(CONFIG_SPD_EEPROM) + #include + #endif ++#if defined(CONFIG_OF_FLAT_TREE) ++#include ++#endif ++ + int fixed_sdram(void); + void sdram_init(void); + +@@ -59,7 +63,7 @@ int board_early_init_f (void) + + long int initdram (int board_type) + { +- volatile immap_t *im = (immap_t *)CFG_IMMRBAR; ++ volatile immap_t *im = (immap_t *)CFG_IMMR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) +@@ -96,7 +100,7 @@ long int initdram (int board_type) + ************************************************************************/ + int fixed_sdram(void) + { +- volatile immap_t *im = (immap_t *)CFG_IMMRBAR; ++ volatile immap_t *im = (immap_t *)CFG_IMMR; + u32 msize = 0; + u32 ddr_size; + u32 ddr_size_log2; +@@ -167,8 +171,8 @@ int checkboard (void) + + void sdram_init(void) + { +- volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; +- volatile lbus8349_t *lbc= &immap->lbus; ++ volatile immap_t *immap = (immap_t *)CFG_IMMR; ++ volatile lbus83xx_t *lbc= &immap->lbus; + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + + puts("\n SDRAM on Local Bus: "); +@@ -245,8 +249,8 @@ void sdram_init(void) + */ + void ecc_print_status(void) + { +- volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; +- volatile ddr8349_t *ddr = &immap->ddr; ++ volatile immap_t *immap = (immap_t *)CFG_IMMR; ++ volatile ddr83xx_t *ddr = &immap->ddr; + + printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); + +@@ -320,8 +324,8 @@ void ecc_print_status(void) + + int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) + { +- volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; +- volatile ddr8349_t *ddr = &immap->ddr; ++ volatile immap_t *immap = (immap_t *)CFG_IMMR; ++ volatile ddr83xx_t *ddr = &immap->ddr; + volatile u32 val; + u64 *addr, count, val64; + register u64 *i; +@@ -564,3 +568,23 @@ U_BOOT_CMD( + " - re-inits memory" + ); + #endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */ ++ ++#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) ++void ++ft_board_setup(void *blob, bd_t *bd) ++{ ++ u32 *p; ++ int len; ++ ++#ifdef CONFIG_PCI ++ ft_pci_setup(blob, bd); ++#endif ++ ft_cpu_setup(blob, bd); ++ ++ p = ft_get_prop(blob, "/memory/reg", &len); ++ if (p != NULL) { ++ *p++ = cpu_to_be32(bd->bi_memstart); ++ *p = cpu_to_be32(bd->bi_memsize); ++ } ++} ++#endif +diff -Naupr u-boot-1.1.6/board/mpc8349emds/pci.c u-boot-1.1.6-fsl-1/board/mpc8349emds/pci.c +--- u-boot-1.1.6/board/mpc8349emds/pci.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/mpc8349emds/pci.c 2006-12-06 10:33:49.000000000 -0600 +@@ -68,12 +68,13 @@ static struct pci_controller pci_hose[] + void + pib_init(void) + { +- u8 val8; ++ u8 val8, orig_i2c_bus; + /* + * Assign PIB PMC slot to desired PCI bus + */ +- mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET); +- i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); ++ /* Switch temporarily to I2C bus #2 */ ++ orig_i2c_bus = i2c_get_bus_num(); ++ i2c_set_bus_num(1); + + val8 = 0; + i2c_write(0x23, 0x6, 1, &val8, 1); +@@ -118,6 +119,8 @@ pib_init(void) + printf("PCI1: 32-bit on PMC1, PMC2\n"); + printf("PCI2: 32-bit on PMC3\n"); + #endif ++ /* Reset to original I2C bus */ ++ i2c_set_bus_num(orig_i2c_bus); + } + + /************************************************************************** +@@ -130,18 +133,18 @@ void + pci_init_board(void) + { + volatile immap_t * immr; +- volatile clk8349_t * clk; +- volatile law8349_t * pci_law; +- volatile pot8349_t * pci_pot; +- volatile pcictrl8349_t * pci_ctrl; +- volatile pciconf8349_t * pci_conf; ++ volatile clk83xx_t * clk; ++ volatile law83xx_t * pci_law; ++ volatile pot83xx_t * pci_pot; ++ volatile pcictrl83xx_t * pci_ctrl; ++ volatile pciconf83xx_t * pci_conf; + u16 reg16; + u32 reg32; + u32 dev; + struct pci_controller * hose; + +- immr = (immap_t *)CFG_IMMRBAR; +- clk = (clk8349_t *)&immr->clk; ++ immr = (immap_t *)CFG_IMMR; ++ clk = (clk83xx_t *)&immr->clk; + pci_law = immr->sysconf.pcilaw; + pci_pot = immr->ios.pot; + pci_ctrl = immr->pci_ctrl; +@@ -254,8 +257,8 @@ pci_init_board(void) + hose->region_count = 4; + + pci_setup_indirect(hose, +- (CFG_IMMRBAR+0x8300), +- (CFG_IMMRBAR+0x8304)); ++ (CFG_IMMR+0x8300), ++ (CFG_IMMR+0x8304)); + + pci_register_hose(hose); + +@@ -350,8 +353,8 @@ pci_init_board(void) + hose->region_count = 4; + + pci_setup_indirect(hose, +- (CFG_IMMRBAR+0x8380), +- (CFG_IMMRBAR+0x8384)); ++ (CFG_IMMR+0x8380), ++ (CFG_IMMR+0x8384)); + + pci_register_hose(hose); + +@@ -379,4 +382,26 @@ pci_init_board(void) + + } + ++#ifdef CONFIG_OF_FLAT_TREE ++void ++ft_pci_setup(void *blob, bd_t *bd) ++{ ++ u32 *p; ++ int len; ++ ++ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); ++ if (p != NULL) { ++ p[0] = pci_hose[0].first_busno; ++ p[1] = pci_hose[0].last_busno; ++ } ++ ++#ifdef CONFIG_MPC83XX_PCI2 ++ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); ++ if (p != NULL) { ++ p[0] = pci_hose[1].first_busno; ++ p[1] = pci_hose[1].last_busno; ++ } ++#endif ++} ++#endif /* CONFIG_OF_FLAT_TREE */ + #endif /* CONFIG_PCI */ +diff -Naupr u-boot-1.1.6/board/mpc8349itx/config.mk u-boot-1.1.6-fsl-1/board/mpc8349itx/config.mk +--- u-boot-1.1.6/board/mpc8349itx/config.mk 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/mpc8349itx/config.mk 2006-11-10 11:24:28.000000000 -0600 +@@ -0,0 +1,33 @@ ++# ++# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++# ++# MPC8349ITX ++# ++ ++TEXT_BASE = 0xFEF00000 ++ ++ifneq ($(OBJTREE),$(SRCTREE)) ++# We are building u-boot in a separate directory, use generated ++# .lds script from OBJTREE directory. ++LDSCRIPT := $(OBJTREE)/board/$(BOARDDIR)/u-boot.lds ++endif +diff -Naupr u-boot-1.1.6/board/mpc8349itx/Makefile u-boot-1.1.6-fsl-1/board/mpc8349itx/Makefile +--- u-boot-1.1.6/board/mpc8349itx/Makefile 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/mpc8349itx/Makefile 2006-11-10 11:24:28.000000000 -0600 +@@ -0,0 +1,48 @@ ++# ++# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).a ++ ++COBJS := $(BOARD).o pci.o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) ++ $(AR) crv $@ $(OBJS) ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak .depend ++ ++######################################################################### ++ ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +diff -Naupr u-boot-1.1.6/board/mpc8349itx/mpc8349itx.c u-boot-1.1.6-fsl-1/board/mpc8349itx/mpc8349itx.c +--- u-boot-1.1.6/board/mpc8349itx/mpc8349itx.c 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/mpc8349itx/mpc8349itx.c 2006-11-30 12:34:13.000000000 -0600 +@@ -0,0 +1,477 @@ ++/* ++ * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_PCI ++#include ++#include ++#endif ++ ++#ifdef CONFIG_SPD_EEPROM ++#include ++#else ++#include ++#endif ++#if defined(CONFIG_OF_FLAT_TREE) ++#include ++#endif ++ ++#ifndef CONFIG_SPD_EEPROM ++/************************************************************************* ++ * fixed sdram init -- doesn't use serial presence detect. ++ ************************************************************************/ ++int fixed_sdram(void) ++{ ++ volatile immap_t *im = (immap_t *) CFG_IMMR; ++ u32 ddr_size; /* The size of RAM, in bytes */ ++ u32 ddr_size_log2 = 0; ++ ++ for (ddr_size = CFG_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) { ++ if (ddr_size & 1) { ++ return -1; ++ } ++ ddr_size_log2++; ++ } ++ ++ im->sysconf.ddrlaw[0].ar = ++ LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); ++ im->sysconf.ddrlaw[0].bar = (CFG_DDR_SDRAM_BASE >> 12) & 0xfffff; ++ ++ /* Only one CS0 for DDR */ ++ im->ddr.csbnds[0].csbnds = 0x0000000f; ++ im->ddr.cs_config[0] = CFG_DDR_CONFIG; ++ ++ debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds); ++ debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]); ++ ++ debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar); ++ debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar); ++ ++ im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; ++ im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ ++ im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR; ++ im->ddr.sdram_mode = ++ (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT); ++ im->ddr.sdram_interval = ++ (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 << ++ SDRAM_INTERVAL_BSTOPRE_SHIFT); ++ im->ddr.sdram_clk_cntl = ++ DDR_SDRAM_CLK_CNTL_SS_EN | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05; ++ ++ udelay(200); ++ ++ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; ++ ++ debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1); ++ debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2); ++ debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode); ++ debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval); ++ debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg); ++ ++ return CFG_DDR_SIZE; ++} ++#endif ++ ++#ifdef CONFIG_PCI ++/* ++ * Initialize PCI Devices, report devices found ++ */ ++#ifndef CONFIG_PCI_PNP ++static struct pci_config_table pci_mpc83xxmitx_config_table[] = { ++ { ++ PCI_ANY_ID, ++ PCI_ANY_ID, ++ PCI_ANY_ID, ++ PCI_ANY_ID, ++ 0x0f, ++ PCI_ANY_ID, ++ pci_cfgfunc_config_device, ++ { ++ PCI_ENET0_IOADDR, ++ PCI_ENET0_MEMADDR, ++ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} ++ }, ++ {} ++} ++#endif ++ ++volatile static struct pci_controller hose[] = { ++ { ++#ifndef CONFIG_PCI_PNP ++ config_table:pci_mpc83xxmitx_config_table, ++#endif ++ }, ++ { ++#ifndef CONFIG_PCI_PNP ++ config_table:pci_mpc83xxmitx_config_table, ++#endif ++ } ++}; ++#endif /* CONFIG_PCI */ ++ ++/* If MPC8349E-mITX is soldered with SDRAM, then initialize it. */ ++ ++void sdram_init(void) ++{ ++ volatile immap_t *immap = (immap_t *) CFG_IMMR; ++ volatile lbus83xx_t *lbc = &immap->lbus; ++ ++#if defined(CFG_BR2_PRELIM) \ ++ && defined(CFG_OR2_PRELIM) \ ++ && defined(CFG_LBLAWBAR2_PRELIM) \ ++ && defined(CFG_LBLAWAR2_PRELIM) \ ++ && !defined(CONFIG_COMPACT_FLASH) ++ ++ uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; ++ ++ puts("\n SDRAM on Local Bus: "); ++ print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); ++ ++ /* ++ * Setup SDRAM Base and Option Registers, already done in cpu_init.c ++ */ ++ ++ /*setup mtrpt, lsrt and lbcr for LB bus */ ++ lbc->lbcr = CFG_LBC_LBCR; ++ lbc->mrtpr = CFG_LBC_MRTPR; ++ lbc->lsrt = CFG_LBC_LSRT; ++ asm("sync"); ++ ++ /* ++ * Configure the SDRAM controller Machine Mode register. ++ */ ++ lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ ++ ++ lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733; precharge all the banks */ ++ asm("sync"); ++ *sdram_addr = 0xff; ++ udelay(100); ++ ++ lbc->lsdmr = CFG_LBC_LSDMR_2; /*0x48636733; auto refresh */ ++ asm("sync"); ++ *sdram_addr = 0xff; /*1 time*/ ++ udelay(100); ++ *sdram_addr = 0xff; /*2 times*/ ++ udelay(100); ++ *sdram_addr = 0xff; /*3 times*/ ++ udelay(100); ++ *sdram_addr = 0xff; /*4 times*/ ++ udelay(100); ++ *sdram_addr = 0xff; /*5 times*/ ++ udelay(100); ++ *sdram_addr = 0xff; /*6 times*/ ++ udelay(100); ++ *sdram_addr = 0xff; /*7 times*/ ++ udelay(100); ++ *sdram_addr = 0xff; /*8 times*/ ++ udelay(100); ++ ++ lbc->lsdmr = CFG_LBC_LSDMR_4; /*0x58636733;mode register write operation */ ++ asm("sync"); ++ *sdram_addr = 0xff; ++ udelay(100); ++ ++ lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation */ ++ asm("sync"); ++ *sdram_addr = 0xff; ++ udelay(100); ++ ++#else ++ puts("SDRAM on Local Bus is NOT available!\n"); ++ ++#ifdef CFG_BR2_PRELIM ++ lbc->bank[2].br = CFG_BR2_PRELIM; ++ lbc->bank[2].or = CFG_OR2_PRELIM; ++#endif ++ ++#ifdef CFG_BR3_PRELIM ++ lbc->bank[3].br = CFG_BR3_PRELIM; ++ lbc->bank[3].or = CFG_OR3_PRELIM; ++#endif ++#endif ++} ++ ++long int initdram(int board_type) ++{ ++ volatile immap_t *im = (immap_t *) CFG_IMMR; ++ u32 msize = 0; ++#ifdef CONFIG_DDR_ECC ++ volatile ddr83xx_t *ddr = &im->ddr; ++#endif ++ ++ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) ++ return -1; ++ ++ /* DDR SDRAM - Main SODIMM */ ++ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; ++#ifdef CONFIG_SPD_EEPROM ++ msize = spd_sdram(); ++#else ++ msize = fixed_sdram(); ++#endif ++ ++#ifdef CONFIG_DDR_ECC ++ if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ++ /* Unlike every other board, on the 83xx spd_sdram() returns ++ megabytes instead of just bytes. That's why we need to ++ multiple by 1MB when calling ddr_enable_ecc(). */ ++ ddr_enable_ecc(msize * 1048576); ++#endif ++ ++ /* ++ * Initialize SDRAM if it is on local bus. ++ */ ++ sdram_init(); ++ puts(" DDR RAM: "); ++ /* return total bus SDRAM size(bytes) -- DDR */ ++ return msize * 1024 * 1024; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: Freescale MPC8349E-mITX\n"); ++ ++ return 0; ++} ++ ++/* ++ * Implement a work-around for a hardware problem with compact ++ * flash. ++ * ++ * Program the UPM if compact flash is enabled. ++ */ ++int misc_init_f(void) ++{ ++ volatile u32 *vsc7385_cpuctrl; ++ ++ /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up ++ default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That ++ means it is 0 when the IRQ is not active. This makes the wire-AND ++ logic always assert IRQ7 to CPU even if there is no request from the ++ switch. Since the compact flash and the switch share the same IRQ, ++ the Linux kernel will think that the compact flash is requesting irq ++ and get stuck when it tries to clear the IRQ. Thus we need to set ++ the L2_IRQ0 and L2_IRQ1 to active low. ++ ++ The following code sets the L1_IRQ and L2_IRQ polarity to active low. ++ Without this code, compact flash will not work in Linux because ++ unlike U-Boot, Linux uses the IRQ, so this code is necessary if we ++ don't enable compact flash for U-Boot. ++ */ ++ ++ vsc7385_cpuctrl = (volatile u32 *)(CFG_VSC7385_BASE + 0x1c0c0); ++ *vsc7385_cpuctrl |= 0x0c; ++ ++#ifdef CONFIG_COMPACT_FLASH ++ /* UPM Table Configuration Code */ ++ static uint UPMATable[] = { ++ 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00, ++ 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01, ++ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, ++ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, ++ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00, ++ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, ++ 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00, ++ 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00, ++ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, ++ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, ++ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, ++ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, ++ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, ++ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, ++ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, ++ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 ++ }; ++ volatile immap_t *immap = (immap_t *) CFG_IMMR; ++ volatile lbus83xx_t *lbus = &immap->lbus; ++ ++ lbus->bank[3].br = CFG_BR3_PRELIM; ++ lbus->bank[3].or = CFG_OR3_PRELIM; ++ ++ /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000, ++ GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000 ++ */ ++ lbus->mamr = 0x08404440; ++ ++ upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); ++ ++ puts("UPMA: Configured for compact flash\n"); ++#endif ++ ++ return 0; ++} ++ ++/* ++ * Make sure the EEPROM has the HRCW correctly programmed. ++ * Make sure the RTC is correctly programmed. ++ * ++ * The MPC8349E-mITX can be configured to load the HRCW from ++ * EEPROM instead of flash. This is controlled via jumpers ++ * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all ++ * jumpered), but if they're set to 001 or 010, then the HRCW is ++ * read from the "I2C EEPROM". ++ * ++ * This function makes sure that the I2C EEPROM is programmed ++ * correctly. ++ */ ++int misc_init_r(void) ++{ ++ int rc = 0; ++ ++#ifdef CONFIG_HARD_I2C ++ ++ unsigned int orig_bus = i2c_get_bus_num();; ++ u8 i2c_data; ++ ++#ifdef CFG_I2C_RTC_ADDR ++ u8 ds1339_data[17]; ++#endif ++ ++#ifdef CFG_I2C_EEPROM_ADDR ++ static u8 eeprom_data[] = /* HRCW data */ ++ { ++ 0xaa, 0x55, 0xaa, ++ 0x7c, 0x02, 0x40, 0x05, 0x04, 0x00, 0x00, ++ 0x7c, 0x02, 0x41, 0xb4, 0x60, 0xa0, 0x00, ++ }; ++ ++ u8 data[sizeof(eeprom_data)]; ++#endif ++ ++ printf("Board revision: "); ++ i2c_set_bus_num(1); ++ if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) ++ printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); ++ else if (i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) ++ printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); ++ else { ++ printf("Unknown\n"); ++ rc = 1; ++ } ++ ++#ifdef CFG_I2C_EEPROM_ADDR ++ i2c_set_bus_num(0); ++ ++ if (i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) { ++ if (memcmp(data, eeprom_data, sizeof(data)) != 0) { ++ if (i2c_write ++ (CFG_I2C_EEPROM_ADDR, 0, 2, eeprom_data, ++ sizeof(eeprom_data)) != 0) { ++ puts("Failure writing the HRCW to EEPROM via I2C.\n"); ++ rc = 1; ++ } ++ } ++ } else { ++ puts("Failure reading the HRCW from EEPROM via I2C.\n"); ++ rc = 1; ++ } ++#endif ++ ++#ifdef CFG_I2C_RTC_ADDR ++ i2c_set_bus_num(1); ++ ++ if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data)) ++ == 0) { ++ ++ /* Work-around for MPC8349E-mITX bug #13601. ++ If the RTC does not contain valid register values, the DS1339 ++ Linux driver will not work. ++ */ ++ ++ /* Make sure status register bits 6-2 are zero */ ++ ds1339_data[0x0f] &= ~0x7c; ++ ++ /* Check for a valid day register value */ ++ ds1339_data[0x03] &= ~0xf8; ++ if (ds1339_data[0x03] == 0) { ++ ds1339_data[0x03] = 1; ++ } ++ ++ /* Check for a valid date register value */ ++ ds1339_data[0x04] &= ~0xc0; ++ if ((ds1339_data[0x04] == 0) || ++ ((ds1339_data[0x04] & 0x0f) > 9) || ++ (ds1339_data[0x04] >= 0x32)) { ++ ds1339_data[0x04] = 1; ++ } ++ ++ /* Check for a valid month register value */ ++ ds1339_data[0x05] &= ~0x60; ++ ++ if ((ds1339_data[0x05] == 0) || ++ ((ds1339_data[0x05] & 0x0f) > 9) || ++ ((ds1339_data[0x05] >= 0x13) ++ && (ds1339_data[0x05] <= 0x19))) { ++ ds1339_data[0x05] = 1; ++ } ++ ++ /* Enable Oscillator and rate select */ ++ ds1339_data[0x0e] = 0x1c; ++ ++ /* Work-around for MPC8349E-mITX bug #13330. ++ Ensure that the RTC control register contains the value 0x1c. ++ This affects SATA performance. ++ */ ++ ++ if (i2c_write ++ (CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, ++ sizeof(ds1339_data))) { ++ puts("Failure writing to the RTC via I2C.\n"); ++ rc = 1; ++ } ++ } else { ++ puts("Failure reading from the RTC via I2C.\n"); ++ rc = 1; ++ } ++#endif ++ ++ i2c_set_bus_num(orig_bus); ++#endif ++ ++ return rc; ++} ++ ++#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) ++void ++ft_board_setup(void *blob, bd_t *bd) ++{ ++ u32 *p; ++ int len; ++ ++#ifdef CONFIG_PCI ++ ft_pci_setup(blob, bd); ++#endif ++ ft_cpu_setup(blob, bd); ++ ++ p = ft_get_prop(blob, "/memory/reg", &len); ++ if (p != NULL) { ++ *p++ = cpu_to_be32(bd->bi_memstart); ++ *p = cpu_to_be32(bd->bi_memsize); ++ } ++} ++#endif +diff -Naupr u-boot-1.1.6/board/mpc8349itx/pci.c u-boot-1.1.6-fsl-1/board/mpc8349itx/pci.c +--- u-boot-1.1.6/board/mpc8349itx/pci.c 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/mpc8349itx/pci.c 2006-11-10 11:24:28.000000000 -0600 +@@ -0,0 +1,357 @@ ++/* ++ * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++ ++#ifdef CONFIG_PCI ++ ++#include ++#include ++#include ++#include ++#include ++#if defined(CONFIG_OF_FLAT_TREE) ++#include ++#endif ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++/* System RAM mapped to PCI space */ ++#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE ++#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE ++ ++#ifndef CONFIG_PCI_PNP ++static struct pci_config_table pci_mpc8349itx_config_table[] = { ++ { ++ PCI_ANY_ID, ++ PCI_ANY_ID, ++ PCI_ANY_ID, ++ PCI_ANY_ID, ++ PCI_IDSEL_NUMBER, ++ PCI_ANY_ID, ++ pci_cfgfunc_config_device, ++ { ++ PCI_ENET0_IOADDR, ++ PCI_ENET0_MEMADDR, ++ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} ++ }, ++ {} ++}; ++#endif ++ ++static struct pci_controller pci_hose[] = { ++ { ++#ifndef CONFIG_PCI_PNP ++ config_table:pci_mpc8349itx_config_table, ++#endif ++ }, ++ { ++#ifndef CONFIG_PCI_PNP ++ config_table:pci_mpc8349itx_config_table, ++#endif ++ } ++}; ++ ++/************************************************************************** ++ * pci_init_board() ++ * ++ * NOTICE: PCI2 is not currently supported ++ * ++ */ ++void pci_init_board(void) ++{ ++ volatile immap_t *immr; ++ volatile clk83xx_t *clk; ++ volatile law83xx_t *pci_law; ++ volatile pot83xx_t *pci_pot; ++ volatile pcictrl83xx_t *pci_ctrl; ++ volatile pciconf83xx_t *pci_conf; ++ u8 reg8; ++ u16 reg16; ++ u32 reg32; ++ u32 dev; ++ struct pci_controller *hose; ++ ++ immr = (immap_t *) CFG_IMMR; ++ clk = (clk83xx_t *) & immr->clk; ++ pci_law = immr->sysconf.pcilaw; ++ pci_pot = immr->ios.pot; ++ pci_ctrl = immr->pci_ctrl; ++ pci_conf = immr->pci_conf; ++ ++ hose = &pci_hose[0]; ++ ++ /* ++ * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode ++ */ ++ ++ reg32 = clk->occr; ++ udelay(2000); ++ ++#ifdef CONFIG_HARD_I2C ++ i2c_set_bus_num(1); ++ /* Read the PCI_M66EN jumper setting */ ++ if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) || ++ (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) { ++ if (reg8 & I2C_8574_PCI66) ++ clk->occr = 0xff000000; /* 66 MHz PCI */ ++ else ++ clk->occr = 0xff600001; /* 33 MHz PCI */ ++ } else { ++ clk->occr = 0xff600001; /* 33 MHz PCI */ ++ } ++#else ++ clk->occr = 0xff000000; /* 66 MHz PCI */ ++#endif ++ ++ udelay(2000); ++ ++ /* ++ * Release PCI RST Output signal ++ */ ++ pci_ctrl[0].gcr = 0; ++ udelay(2000); ++ pci_ctrl[0].gcr = 1; ++ ++#ifdef CONFIG_MPC83XX_PCI2 ++ pci_ctrl[1].gcr = 0; ++ udelay(2000); ++ pci_ctrl[1].gcr = 1; ++#endif ++ ++ /* We need to wait at least a 1sec based on PCI specs */ ++ { ++ int i; ++ ++ for (i = 0; i < 1000; i++) ++ udelay(1000); ++ } ++ ++ /* ++ * Configure PCI Local Access Windows ++ */ ++ pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; ++ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; ++ ++ pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; ++ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M; ++ ++ /* ++ * Configure PCI Outbound Translation Windows ++ */ ++ ++ /* PCI1 mem space - prefetch */ ++ pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; ++ pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; ++ pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | POCMR_CM_256M; ++ ++ /* PCI1 IO space */ ++ pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; ++ pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; ++ pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M; ++ ++ /* PCI1 mmio - non-prefetch mem space */ ++ pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; ++ pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; ++ pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M; ++ ++ /* ++ * Configure PCI Inbound Translation Windows ++ */ ++ ++ /* we need RAM mapped to PCI space for the devices to ++ * access main memory */ ++ pci_ctrl[0].pitar1 = 0x0; ++ pci_ctrl[0].pibar1 = 0x0; ++ pci_ctrl[0].piebar1 = 0x0; ++ pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | ++ PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); ++ ++ hose->first_busno = 0; ++ hose->last_busno = 0xff; ++ ++ /* PCI memory prefetch space */ ++ pci_set_region(hose->regions + 0, ++ CFG_PCI1_MEM_BASE, ++ CFG_PCI1_MEM_PHYS, ++ CFG_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); ++ ++ /* PCI memory space */ ++ pci_set_region(hose->regions + 1, ++ CFG_PCI1_MMIO_BASE, ++ CFG_PCI1_MMIO_PHYS, CFG_PCI1_MMIO_SIZE, PCI_REGION_MEM); ++ ++ /* PCI IO space */ ++ pci_set_region(hose->regions + 2, ++ CFG_PCI1_IO_BASE, ++ CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO); ++ ++ /* System memory space */ ++ pci_set_region(hose->regions + 3, ++ CONFIG_PCI_SYS_MEM_BUS, ++ CONFIG_PCI_SYS_MEM_PHYS, ++ gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); ++ ++ hose->region_count = 4; ++ ++ pci_setup_indirect(hose, ++ (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); ++ ++ pci_register_hose(hose); ++ ++ /* ++ * Write to Command register ++ */ ++ reg16 = 0xff; ++ dev = PCI_BDF(hose->first_busno, 0, 0); ++ pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); ++ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; ++ pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); ++ ++ /* ++ * Clear non-reserved bits in status register. ++ */ ++ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); ++ pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); ++ pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); ++ ++#ifdef CONFIG_PCI_SCAN_SHOW ++ printf("PCI: Bus Dev VenId DevId Class Int\n"); ++#endif ++ /* ++ * Hose scan. ++ */ ++ hose->last_busno = pci_hose_scan(hose); ++ ++#ifdef CONFIG_MPC83XX_PCI2 ++ hose = &pci_hose[1]; ++ ++ /* ++ * Configure PCI Outbound Translation Windows ++ */ ++ ++ /* PCI2 mem space - prefetch */ ++ pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; ++ pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; ++ pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | POCMR_CM_256M; ++ ++ /* PCI2 IO space */ ++ pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; ++ pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; ++ pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | POCMR_CM_16M; ++ ++ /* PCI2 mmio - non-prefetch mem space */ ++ pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; ++ pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; ++ pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_CM_256M; ++ ++ /* ++ * Configure PCI Inbound Translation Windows ++ */ ++ ++ /* we need RAM mapped to PCI space for the devices to ++ * access main memory */ ++ pci_ctrl[1].pitar1 = 0x0; ++ pci_ctrl[1].pibar1 = 0x0; ++ pci_ctrl[1].piebar1 = 0x0; ++ pci_ctrl[1].piwar1 = ++ PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | ++ (__ilog2(gd->ram_size) - 1); ++ ++ hose->first_busno = pci_hose[0].last_busno + 1; ++ hose->last_busno = 0xff; ++ ++ /* PCI memory prefetch space */ ++ pci_set_region(hose->regions + 0, ++ CFG_PCI2_MEM_BASE, ++ CFG_PCI2_MEM_PHYS, ++ CFG_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); ++ ++ /* PCI memory space */ ++ pci_set_region(hose->regions + 1, ++ CFG_PCI2_MMIO_BASE, ++ CFG_PCI2_MMIO_PHYS, CFG_PCI2_MMIO_SIZE, PCI_REGION_MEM); ++ ++ /* PCI IO space */ ++ pci_set_region(hose->regions + 2, ++ CFG_PCI2_IO_BASE, ++ CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO); ++ ++ /* System memory space */ ++ pci_set_region(hose->regions + 3, ++ CONFIG_PCI_SYS_MEM_BUS, ++ CONFIG_PCI_SYS_MEM_PHYS, ++ gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); ++ ++ hose->region_count = 4; ++ ++ pci_setup_indirect(hose, ++ (CFG_IMMR + 0x8380), (CFG_IMMR + 0x8384)); ++ ++ pci_register_hose(hose); ++ ++ /* ++ * Write to Command register ++ */ ++ reg16 = 0xff; ++ dev = PCI_BDF(hose->first_busno, 0, 0); ++ pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); ++ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; ++ pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); ++ ++ /* ++ * Clear non-reserved bits in status register. ++ */ ++ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); ++ pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); ++ pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); ++ ++ /* ++ * Hose scan. ++ */ ++ hose->last_busno = pci_hose_scan(hose); ++#endif ++} ++ ++#endif /* CONFIG_PCI */ ++#ifdef CONFIG_OF_FLAT_TREE ++void ++ft_pci_setup(void *blob, bd_t *bd) ++{ ++ u32 *p; ++ int len; ++ ++ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); ++ if (p != NULL) { ++ p[0] = pci_hose[0].first_busno; ++ p[1] = pci_hose[0].last_busno; ++ } ++ ++#ifdef CONFIG_MPC83XX_PCI2 ++ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); ++ if (p != NULL) { ++ p[0] = pci_hose[1].first_busno; ++ p[1] = pci_hose[1].last_busno; ++ } ++#endif ++} ++#endif /* CONFIG_OF_FLAT_TREE */ +diff -Naupr u-boot-1.1.6/board/mpc8349itx/u-boot.lds u-boot-1.1.6-fsl-1/board/mpc8349itx/u-boot.lds +--- u-boot-1.1.6/board/mpc8349itx/u-boot.lds 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/mpc8349itx/u-boot.lds 2006-11-10 11:24:28.000000000 -0600 +@@ -0,0 +1,120 @@ ++/* ++ * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_ARCH(powerpc) ++SECTIONS ++{ ++ /* Read-only sections, merged into text segment: */ ++ . = + SIZEOF_HEADERS; ++ .interp : { *(.interp) } ++ .hash : { *(.hash) } ++ .dynsym : { *(.dynsym) } ++ .dynstr : { *(.dynstr) } ++ .rel.text : { *(.rel.text) } ++ .rela.text : { *(.rela.text) } ++ .rel.data : { *(.rel.data) } ++ .rela.data : { *(.rela.data) } ++ .rel.rodata : { *(.rel.rodata) } ++ .rela.rodata : { *(.rela.rodata) } ++ .rel.got : { *(.rel.got) } ++ .rela.got : { *(.rela.got) } ++ .rel.ctors : { *(.rel.ctors) } ++ .rela.ctors : { *(.rela.ctors) } ++ .rel.dtors : { *(.rel.dtors) } ++ .rela.dtors : { *(.rela.dtors) } ++ .rel.bss : { *(.rel.bss) } ++ .rela.bss : { *(.rela.bss) } ++ .rel.plt : { *(.rel.plt) } ++ .rela.plt : { *(.rela.plt) } ++ .init : { *(.init) } ++ .plt : { *(.plt) } ++ .text : ++ { ++ cpu/mpc83xx/start.o (.text) ++ *(.text) ++ *(.fixup) ++ *(.got1) ++ . = ALIGN(16); ++ *(.rodata) ++ *(.rodata1) ++ *(.rodata.str1.4) ++ } ++ .fini : { *(.fini) } =0 ++ .ctors : { *(.ctors) } ++ .dtors : { *(.dtors) } ++ ++ /* Read-write section, merged into data segment: */ ++ . = (. + 0x0FFF) & 0xFFFFF000; ++ _erotext = .; ++ PROVIDE (erotext = .); ++ .reloc : ++ { ++ *(.got) ++ _GOT2_TABLE_ = .; ++ *(.got2) ++ _FIXUP_TABLE_ = .; ++ *(.fixup) ++ } ++ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; ++ __fixup_entries = (. - _FIXUP_TABLE_) >> 2; ++ ++ .data : ++ { ++ *(.data) ++ *(.data1) ++ *(.sdata) ++ *(.sdata2) ++ *(.dynamic) ++ CONSTRUCTORS ++ } ++ _edata = .; ++ PROVIDE (edata = .); ++ ++ . = .; ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = .; ++ __start___ex_table = .; ++ __ex_table : { *(__ex_table) } ++ __stop___ex_table = .; ++ ++ . = ALIGN(4096); ++ __init_begin = .; ++ .text.init : { *(.text.init) } ++ .data.init : { *(.data.init) } ++ . = ALIGN(4096); ++ __init_end = .; ++ ++ __bss_start = .; ++ .bss : ++ { ++ *(.sbss) *(.scommon) ++ *(.dynbss) ++ *(.bss) ++ *(COMMON) ++ } ++ _end = . ; ++ PROVIDE (end = .); ++} ++ENTRY(_start) +diff -Naupr u-boot-1.1.6/board/mpc8360emds/config.mk u-boot-1.1.6-fsl-1/board/mpc8360emds/config.mk +--- u-boot-1.1.6/board/mpc8360emds/config.mk 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/mpc8360emds/config.mk 2006-11-10 11:24:28.000000000 -0600 +@@ -0,0 +1,28 @@ ++# ++# (C) Copyright 2006 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++# ++# MPC8360EMDS ++# ++ ++TEXT_BASE = 0xFE000000 +diff -Naupr u-boot-1.1.6/board/mpc8360emds/Makefile u-boot-1.1.6-fsl-1/board/mpc8360emds/Makefile +--- u-boot-1.1.6/board/mpc8360emds/Makefile 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/mpc8360emds/Makefile 2006-11-10 11:24:28.000000000 -0600 +@@ -0,0 +1,50 @@ ++# ++# (C) Copyright 2006 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).a ++ ++COBJS := $(BOARD).o pci.o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) ++ $(AR) $(ARFLAGS) $@ $(OBJS) ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak .depend ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +diff -Naupr u-boot-1.1.6/board/mpc8360emds/mpc8360emds.c u-boot-1.1.6-fsl-1/board/mpc8360emds/mpc8360emds.c +--- u-boot-1.1.6/board/mpc8360emds/mpc8360emds.c 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/mpc8360emds/mpc8360emds.c 2006-11-10 11:24:28.000000000 -0600 +@@ -0,0 +1,657 @@ ++/* ++ * Copyright (C) 2006 Freescale Semiconductor, Inc. ++ * ++ * Dave Liu ++ * based on board/mpc8349emds/mpc8349emds.c ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if defined(CONFIG_PCI) ++#include ++#endif ++#if defined(CONFIG_SPD_EEPROM) ++#include ++#else ++#include ++#endif ++#if defined(CONFIG_OF_FLAT_TREE) ++#include ++#endif ++ ++const qe_iop_conf_t qe_iop_conf_tab[] = { ++ /* GETH1 */ ++ {0, 3, 1, 0, 1}, /* TxD0 */ ++ {0, 4, 1, 0, 1}, /* TxD1 */ ++ {0, 5, 1, 0, 1}, /* TxD2 */ ++ {0, 6, 1, 0, 1}, /* TxD3 */ ++ {1, 6, 1, 0, 3}, /* TxD4 */ ++ {1, 7, 1, 0, 1}, /* TxD5 */ ++ {1, 9, 1, 0, 2}, /* TxD6 */ ++ {1, 10, 1, 0, 2}, /* TxD7 */ ++ {0, 9, 2, 0, 1}, /* RxD0 */ ++ {0, 10, 2, 0, 1}, /* RxD1 */ ++ {0, 11, 2, 0, 1}, /* RxD2 */ ++ {0, 12, 2, 0, 1}, /* RxD3 */ ++ {0, 13, 2, 0, 1}, /* RxD4 */ ++ {1, 1, 2, 0, 2}, /* RxD5 */ ++ {1, 0, 2, 0, 2}, /* RxD6 */ ++ {1, 4, 2, 0, 2}, /* RxD7 */ ++ {0, 7, 1, 0, 1}, /* TX_EN */ ++ {0, 8, 1, 0, 1}, /* TX_ER */ ++ {0, 15, 2, 0, 1}, /* RX_DV */ ++ {0, 16, 2, 0, 1}, /* RX_ER */ ++ {0, 0, 2, 0, 1}, /* RX_CLK */ ++ {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */ ++ {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */ ++ /* GETH2 */ ++ {0, 17, 1, 0, 1}, /* TxD0 */ ++ {0, 18, 1, 0, 1}, /* TxD1 */ ++ {0, 19, 1, 0, 1}, /* TxD2 */ ++ {0, 20, 1, 0, 1}, /* TxD3 */ ++ {1, 2, 1, 0, 1}, /* TxD4 */ ++ {1, 3, 1, 0, 2}, /* TxD5 */ ++ {1, 5, 1, 0, 3}, /* TxD6 */ ++ {1, 8, 1, 0, 3}, /* TxD7 */ ++ {0, 23, 2, 0, 1}, /* RxD0 */ ++ {0, 24, 2, 0, 1}, /* RxD1 */ ++ {0, 25, 2, 0, 1}, /* RxD2 */ ++ {0, 26, 2, 0, 1}, /* RxD3 */ ++ {0, 27, 2, 0, 1}, /* RxD4 */ ++ {1, 12, 2, 0, 2}, /* RxD5 */ ++ {1, 13, 2, 0, 3}, /* RxD6 */ ++ {1, 11, 2, 0, 2}, /* RxD7 */ ++ {0, 21, 1, 0, 1}, /* TX_EN */ ++ {0, 22, 1, 0, 1}, /* TX_ER */ ++ {0, 29, 2, 0, 1}, /* RX_DV */ ++ {0, 30, 2, 0, 1}, /* RX_ER */ ++ {0, 31, 2, 0, 1}, /* RX_CLK */ ++ {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */ ++ {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */ ++ ++ {0, 1, 3, 0, 2}, /* MDIO */ ++ {0, 2, 1, 0, 1}, /* MDC */ ++ ++ {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ ++}; ++ ++int board_early_init_f(void) ++{ ++ volatile u8 *bcsr = (volatile u8 *)CFG_BCSR; ++ ++ /* Enable flash write */ ++ bcsr[0xa] &= ~0x04; ++ ++ return 0; ++} ++ ++#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) ++extern void ddr_enable_ecc(unsigned int dram_size); ++#endif ++int fixed_sdram(void); ++void sdram_init(void); ++ ++long int initdram(int board_type) ++{ ++ volatile immap_t *im = (immap_t *) CFG_IMMR; ++ u32 msize = 0; ++ ++ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) ++ return -1; ++ ++ /* DDR SDRAM - Main SODIMM */ ++ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; ++#if defined(CONFIG_SPD_EEPROM) ++ msize = spd_sdram(); ++#else ++ msize = fixed_sdram(); ++#endif ++ ++#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) ++ /* ++ * Initialize DDR ECC byte ++ */ ++ ddr_enable_ecc(msize * 1024 * 1024); ++#endif ++ /* ++ * Initialize SDRAM if it is on local bus. ++ */ ++ sdram_init(); ++ puts(" DDR RAM: "); ++ /* return total bus SDRAM size(bytes) -- DDR */ ++ return (msize * 1024 * 1024); ++} ++ ++#if !defined(CONFIG_SPD_EEPROM) ++/************************************************************************* ++ * fixed sdram init -- doesn't use serial presence detect. ++ ************************************************************************/ ++int fixed_sdram(void) ++{ ++ volatile immap_t *im = (immap_t *) CFG_IMMR; ++ u32 msize = 0; ++ u32 ddr_size; ++ u32 ddr_size_log2; ++ ++ msize = CFG_DDR_SIZE; ++ for (ddr_size = msize << 20, ddr_size_log2 = 0; ++ (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { ++ if (ddr_size & 1) { ++ return -1; ++ } ++ } ++ im->sysconf.ddrlaw[0].ar = ++ LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); ++#if (CFG_DDR_SIZE != 256) ++#warning Currenly any ddr size other than 256 is not supported ++#endif ++ im->ddr.csbnds[0].csbnds = 0x00000007; ++ im->ddr.csbnds[1].csbnds = 0x0008000f; ++ ++ im->ddr.cs_config[0] = CFG_DDR_CONFIG; ++ im->ddr.cs_config[1] = CFG_DDR_CONFIG; ++ ++ im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; ++ im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; ++ im->ddr.sdram_cfg = CFG_DDR_CONTROL; ++ ++ im->ddr.sdram_mode = CFG_DDR_MODE; ++ im->ddr.sdram_interval = CFG_DDR_INTERVAL; ++ udelay(200); ++ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; ++ ++ return msize; ++} ++#endif /*!CFG_SPD_EEPROM */ ++ ++int checkboard(void) ++{ ++ puts("Board: Freescale MPC8360EMDS\n"); ++ return 0; ++} ++ ++/* ++ * if MPC8360EMDS is soldered with SDRAM ++ */ ++#if defined(CFG_BR2_PRELIM) \ ++ && defined(CFG_OR2_PRELIM) \ ++ && defined(CFG_LBLAWBAR2_PRELIM) \ ++ && defined(CFG_LBLAWAR2_PRELIM) ++/* ++ * Initialize SDRAM memory on the Local Bus. ++ */ ++ ++void sdram_init(void) ++{ ++ volatile immap_t *immap = (immap_t *) CFG_IMMR; ++ volatile lbus83xx_t *lbc = &immap->lbus; ++ uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; ++ ++ puts("\n SDRAM on Local Bus: "); ++ print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); ++ /* ++ * Setup SDRAM Base and Option Registers, already done in cpu_init.c ++ */ ++ /*setup mtrpt, lsrt and lbcr for LB bus */ ++ lbc->lbcr = CFG_LBC_LBCR; ++ lbc->mrtpr = CFG_LBC_MRTPR; ++ lbc->lsrt = CFG_LBC_LSRT; ++ asm("sync"); ++ ++ /* ++ * Configure the SDRAM controller Machine Mode Register. ++ */ ++ lbc->lsdmr = CFG_LBC_LSDMR_5; /* Normal Operation */ ++ lbc->lsdmr = CFG_LBC_LSDMR_1; /* Precharge All Banks */ ++ asm("sync"); ++ *sdram_addr = 0xff; ++ udelay(100); ++ ++ /* ++ * We need do 8 times auto refresh operation. ++ */ ++ lbc->lsdmr = CFG_LBC_LSDMR_2; ++ asm("sync"); ++ *sdram_addr = 0xff; /* 1 times */ ++ udelay(100); ++ *sdram_addr = 0xff; /* 2 times */ ++ udelay(100); ++ *sdram_addr = 0xff; /* 3 times */ ++ udelay(100); ++ *sdram_addr = 0xff; /* 4 times */ ++ udelay(100); ++ *sdram_addr = 0xff; /* 5 times */ ++ udelay(100); ++ *sdram_addr = 0xff; /* 6 times */ ++ udelay(100); ++ *sdram_addr = 0xff; /* 7 times */ ++ udelay(100); ++ *sdram_addr = 0xff; /* 8 times */ ++ udelay(100); ++ ++ /* Mode register write operation */ ++ lbc->lsdmr = CFG_LBC_LSDMR_4; ++ asm("sync"); ++ *(sdram_addr + 0xcc) = 0xff; ++ udelay(100); ++ ++ /* Normal operation */ ++ lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000; ++ asm("sync"); ++ *sdram_addr = 0xff; ++ udelay(100); ++} ++#else ++void sdram_init(void) ++{ ++ puts("SDRAM on Local Bus is NOT available!\n"); ++} ++#endif ++ ++#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) ++/* ++ * ECC user commands ++ */ ++void ecc_print_status(void) ++{ ++ volatile immap_t *immap = (immap_t *) CFG_IMMR; ++ volatile ddr83xx_t *ddr = &immap->ddr; ++ ++ printf("\nECC mode: %s\n\n", ++ (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); ++ ++ /* Interrupts */ ++ printf("Memory Error Interrupt Enable:\n"); ++ printf(" Multiple-Bit Error Interrupt Enable: %d\n", ++ (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0); ++ printf(" Single-Bit Error Interrupt Enable: %d\n", ++ (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0); ++ printf(" Memory Select Error Interrupt Enable: %d\n\n", ++ (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0); ++ ++ /* Error disable */ ++ printf("Memory Error Disable:\n"); ++ printf(" Multiple-Bit Error Disable: %d\n", ++ (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0); ++ printf(" Sinle-Bit Error Disable: %d\n", ++ (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0); ++ printf(" Memory Select Error Disable: %d\n\n", ++ (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0); ++ ++ /* Error injection */ ++ printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n", ++ ddr->data_err_inject_hi, ddr->data_err_inject_lo); ++ ++ printf("Memory Data Path Error Injection Mask ECC:\n"); ++ printf(" ECC Mirror Byte: %d\n", ++ (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0); ++ printf(" ECC Injection Enable: %d\n", ++ (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0); ++ printf(" ECC Error Injection Mask: 0x%02x\n\n", ++ ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM); ++ ++ /* SBE counter/threshold */ ++ printf("Memory Single-Bit Error Management (0..255):\n"); ++ printf(" Single-Bit Error Threshold: %d\n", ++ (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT); ++ printf(" Single-Bit Error Counter: %d\n\n", ++ (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT); ++ ++ /* Error detect */ ++ printf("Memory Error Detect:\n"); ++ printf(" Multiple Memory Errors: %d\n", ++ (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0); ++ printf(" Multiple-Bit Error: %d\n", ++ (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0); ++ printf(" Single-Bit Error: %d\n", ++ (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0); ++ printf(" Memory Select Error: %d\n\n", ++ (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0); ++ ++ /* Capture data */ ++ printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address); ++ printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n", ++ ddr->capture_data_hi, ddr->capture_data_lo); ++ printf("Memory Data Path Read Capture ECC: 0x%02x\n\n", ++ ddr->capture_ecc & CAPTURE_ECC_ECE); ++ ++ printf("Memory Error Attributes Capture:\n"); ++ printf(" Data Beat Number: %d\n", ++ (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ++ ECC_CAPT_ATTR_BNUM_SHIFT); ++ printf(" Transaction Size: %d\n", ++ (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ++ ECC_CAPT_ATTR_TSIZ_SHIFT); ++ printf(" Transaction Source: %d\n", ++ (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ++ ECC_CAPT_ATTR_TSRC_SHIFT); ++ printf(" Transaction Type: %d\n", ++ (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ++ ECC_CAPT_ATTR_TTYP_SHIFT); ++ printf(" Error Information Valid: %d\n\n", ++ ddr->capture_attributes & ECC_CAPT_ATTR_VLD); ++} ++ ++int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) ++{ ++ volatile immap_t *immap = (immap_t *) CFG_IMMR; ++ volatile ddr83xx_t *ddr = &immap->ddr; ++ volatile u32 val; ++ u64 *addr; ++ u32 count; ++ register u64 *i; ++ u32 ret[2]; ++ u32 pattern[2]; ++ u32 writeback[2]; ++ ++ /* The pattern is written into memory to generate error */ ++ pattern[0] = 0xfedcba98UL; ++ pattern[1] = 0x76543210UL; ++ ++ /* After injecting error, re-initialize the memory with the value */ ++ writeback[0] = 0x01234567UL; ++ writeback[1] = 0x89abcdefUL; ++ ++ if (argc > 4) { ++ printf("Usage:\n%s\n", cmdtp->usage); ++ return 1; ++ } ++ ++ if (argc == 2) { ++ if (strcmp(argv[1], "status") == 0) { ++ ecc_print_status(); ++ return 0; ++ } else if (strcmp(argv[1], "captureclear") == 0) { ++ ddr->capture_address = 0; ++ ddr->capture_data_hi = 0; ++ ddr->capture_data_lo = 0; ++ ddr->capture_ecc = 0; ++ ddr->capture_attributes = 0; ++ return 0; ++ } ++ } ++ if (argc == 3) { ++ if (strcmp(argv[1], "sbecnt") == 0) { ++ val = simple_strtoul(argv[2], NULL, 10); ++ if (val > 255) { ++ printf("Incorrect Counter value, " ++ "should be 0..255\n"); ++ return 1; ++ } ++ ++ val = (val << ECC_ERROR_MAN_SBEC_SHIFT); ++ val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET); ++ ++ ddr->err_sbe = val; ++ return 0; ++ } else if (strcmp(argv[1], "sbethr") == 0) { ++ val = simple_strtoul(argv[2], NULL, 10); ++ if (val > 255) { ++ printf("Incorrect Counter value, " ++ "should be 0..255\n"); ++ return 1; ++ } ++ ++ val = (val << ECC_ERROR_MAN_SBET_SHIFT); ++ val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC); ++ ++ ddr->err_sbe = val; ++ return 0; ++ } else if (strcmp(argv[1], "errdisable") == 0) { ++ val = ddr->err_disable; ++ ++ if (strcmp(argv[2], "+sbe") == 0) { ++ val |= ECC_ERROR_DISABLE_SBED; ++ } else if (strcmp(argv[2], "+mbe") == 0) { ++ val |= ECC_ERROR_DISABLE_MBED; ++ } else if (strcmp(argv[2], "+mse") == 0) { ++ val |= ECC_ERROR_DISABLE_MSED; ++ } else if (strcmp(argv[2], "+all") == 0) { ++ val |= (ECC_ERROR_DISABLE_SBED | ++ ECC_ERROR_DISABLE_MBED | ++ ECC_ERROR_DISABLE_MSED); ++ } else if (strcmp(argv[2], "-sbe") == 0) { ++ val &= ~ECC_ERROR_DISABLE_SBED; ++ } else if (strcmp(argv[2], "-mbe") == 0) { ++ val &= ~ECC_ERROR_DISABLE_MBED; ++ } else if (strcmp(argv[2], "-mse") == 0) { ++ val &= ~ECC_ERROR_DISABLE_MSED; ++ } else if (strcmp(argv[2], "-all") == 0) { ++ val &= ~(ECC_ERROR_DISABLE_SBED | ++ ECC_ERROR_DISABLE_MBED | ++ ECC_ERROR_DISABLE_MSED); ++ } else { ++ printf("Incorrect err_disable field\n"); ++ return 1; ++ } ++ ++ ddr->err_disable = val; ++ __asm__ __volatile__("sync"); ++ __asm__ __volatile__("isync"); ++ return 0; ++ } else if (strcmp(argv[1], "errdetectclr") == 0) { ++ val = ddr->err_detect; ++ ++ if (strcmp(argv[2], "mme") == 0) { ++ val |= ECC_ERROR_DETECT_MME; ++ } else if (strcmp(argv[2], "sbe") == 0) { ++ val |= ECC_ERROR_DETECT_SBE; ++ } else if (strcmp(argv[2], "mbe") == 0) { ++ val |= ECC_ERROR_DETECT_MBE; ++ } else if (strcmp(argv[2], "mse") == 0) { ++ val |= ECC_ERROR_DETECT_MSE; ++ } else if (strcmp(argv[2], "all") == 0) { ++ val |= (ECC_ERROR_DETECT_MME | ++ ECC_ERROR_DETECT_MBE | ++ ECC_ERROR_DETECT_SBE | ++ ECC_ERROR_DETECT_MSE); ++ } else { ++ printf("Incorrect err_detect field\n"); ++ return 1; ++ } ++ ++ ddr->err_detect = val; ++ return 0; ++ } else if (strcmp(argv[1], "injectdatahi") == 0) { ++ val = simple_strtoul(argv[2], NULL, 16); ++ ++ ddr->data_err_inject_hi = val; ++ return 0; ++ } else if (strcmp(argv[1], "injectdatalo") == 0) { ++ val = simple_strtoul(argv[2], NULL, 16); ++ ++ ddr->data_err_inject_lo = val; ++ return 0; ++ } else if (strcmp(argv[1], "injectecc") == 0) { ++ val = simple_strtoul(argv[2], NULL, 16); ++ if (val > 0xff) { ++ printf("Incorrect ECC inject mask, " ++ "should be 0x00..0xff\n"); ++ return 1; ++ } ++ val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM); ++ ++ ddr->ecc_err_inject = val; ++ return 0; ++ } else if (strcmp(argv[1], "inject") == 0) { ++ val = ddr->ecc_err_inject; ++ ++ if (strcmp(argv[2], "en") == 0) ++ val |= ECC_ERR_INJECT_EIEN; ++ else if (strcmp(argv[2], "dis") == 0) ++ val &= ~ECC_ERR_INJECT_EIEN; ++ else ++ printf("Incorrect command\n"); ++ ++ ddr->ecc_err_inject = val; ++ __asm__ __volatile__("sync"); ++ __asm__ __volatile__("isync"); ++ return 0; ++ } else if (strcmp(argv[1], "mirror") == 0) { ++ val = ddr->ecc_err_inject; ++ ++ if (strcmp(argv[2], "en") == 0) ++ val |= ECC_ERR_INJECT_EMB; ++ else if (strcmp(argv[2], "dis") == 0) ++ val &= ~ECC_ERR_INJECT_EMB; ++ else ++ printf("Incorrect command\n"); ++ ++ ddr->ecc_err_inject = val; ++ return 0; ++ } ++ } ++ if (argc == 4) { ++ if (strcmp(argv[1], "testdw") == 0) { ++ addr = (u64 *) simple_strtoul(argv[2], NULL, 16); ++ count = simple_strtoul(argv[3], NULL, 16); ++ ++ if ((u32) addr % 8) { ++ printf("Address not alligned on " ++ "double word boundary\n"); ++ return 1; ++ } ++ disable_interrupts(); ++ ++ for (i = addr; i < addr + count; i++) { ++ ++ /* enable injects */ ++ ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; ++ __asm__ __volatile__("sync"); ++ __asm__ __volatile__("isync"); ++ ++ /* write memory location injecting errors */ ++ ppcDWstore((u32 *) i, pattern); ++ __asm__ __volatile__("sync"); ++ ++ /* disable injects */ ++ ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; ++ __asm__ __volatile__("sync"); ++ __asm__ __volatile__("isync"); ++ ++ /* read data, this generates ECC error */ ++ ppcDWload((u32 *) i, ret); ++ __asm__ __volatile__("sync"); ++ ++ /* re-initialize memory, double word write the location again, ++ * generates new ECC code this time */ ++ ppcDWstore((u32 *) i, writeback); ++ __asm__ __volatile__("sync"); ++ } ++ enable_interrupts(); ++ return 0; ++ } ++ if (strcmp(argv[1], "testword") == 0) { ++ addr = (u64 *) simple_strtoul(argv[2], NULL, 16); ++ count = simple_strtoul(argv[3], NULL, 16); ++ ++ if ((u32) addr % 8) { ++ printf("Address not alligned on " ++ "double word boundary\n"); ++ return 1; ++ } ++ disable_interrupts(); ++ ++ for (i = addr; i < addr + count; i++) { ++ ++ /* enable injects */ ++ ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; ++ __asm__ __volatile__("sync"); ++ __asm__ __volatile__("isync"); ++ ++ /* write memory location injecting errors */ ++ *(u32 *) i = 0xfedcba98UL; ++ __asm__ __volatile__("sync"); ++ ++ /* sub double word write, ++ * bus will read-modify-write, ++ * generates ECC error */ ++ *((u32 *) i + 1) = 0x76543210UL; ++ __asm__ __volatile__("sync"); ++ ++ /* disable injects */ ++ ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; ++ __asm__ __volatile__("sync"); ++ __asm__ __volatile__("isync"); ++ ++ /* re-initialize memory, ++ * double word write the location again, ++ * generates new ECC code this time */ ++ ppcDWstore((u32 *) i, writeback); ++ __asm__ __volatile__("sync"); ++ } ++ enable_interrupts(); ++ return 0; ++ } ++ } ++ printf("Usage:\n%s\n", cmdtp->usage); ++ return 1; ++} ++ ++U_BOOT_CMD(ecc, 4, 0, do_ecc, ++ "ecc - support for DDR ECC features\n", ++ "status - print out status info\n" ++ "ecc captureclear - clear capture regs data\n" ++ "ecc sbecnt - set Single-Bit Error counter\n" ++ "ecc sbethr - set Single-Bit Threshold\n" ++ "ecc errdisable - clear/set disable Memory Error Disable, flag:\n" ++ " [-|+]sbe - Single-Bit Error\n" ++ " [-|+]mbe - Multiple-Bit Error\n" ++ " [-|+]mse - Memory Select Error\n" ++ " [-|+]all - all errors\n" ++ "ecc errdetectclr - clear Memory Error Detect, flag:\n" ++ " mme - Multiple Memory Errors\n" ++ " sbe - Single-Bit Error\n" ++ " mbe - Multiple-Bit Error\n" ++ " mse - Memory Select Error\n" ++ " all - all errors\n" ++ "ecc injectdatahi - set Memory Data Path Error Injection Mask High\n" ++ "ecc injectdatalo - set Memory Data Path Error Injection Mask Low\n" ++ "ecc injectecc - set ECC Error Injection Mask\n" ++ "ecc inject - enable/disable error injection\n" ++ "ecc mirror - enable/disable mirror byte\n" ++ "ecc testdw - test mem region with double word access:\n" ++ " - enables injects\n" ++ " - writes pattern injecting errors with double word access\n" ++ " - disables injects\n" ++ " - reads pattern back with double word access, generates error\n" ++ " - re-inits memory\n" ++ "ecc testword - test mem region with word access:\n" ++ " - enables injects\n" ++ " - writes pattern injecting errors with word access\n" ++ " - writes pattern with word access, generates error\n" ++ " - disables injects\n" " - re-inits memory"); ++#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */ ++ ++#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) ++void ++ft_board_setup(void *blob, bd_t *bd) ++{ ++ u32 *p; ++ int len; ++ ++#ifdef CONFIG_PCI ++ ft_pci_setup(blob, bd); ++#endif ++ ft_cpu_setup(blob, bd); ++ ++ p = ft_get_prop(blob, "/memory/reg", &len); ++ if (p != NULL) { ++ *p++ = cpu_to_be32(bd->bi_memstart); ++ *p = cpu_to_be32(bd->bi_memsize); ++ } ++} ++#endif +diff -Naupr u-boot-1.1.6/board/mpc8360emds/pci.c u-boot-1.1.6-fsl-1/board/mpc8360emds/pci.c +--- u-boot-1.1.6/board/mpc8360emds/pci.c 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/mpc8360emds/pci.c 2006-11-10 11:24:28.000000000 -0600 +@@ -0,0 +1,313 @@ ++/* ++ * Copyright (C) 2006 Freescale Semiconductor, Inc. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++/* ++ * PCI Configuration space access support for MPC83xx PCI Bridge ++ */ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#if defined(CONFIG_PCI) ++#define PCI_FUNCTION_CONFIG 0x44 ++#define PCI_FUNCTION_CFG_LOCK 0x20 ++ ++/* ++ * Initialize PCI Devices, report devices found ++ */ ++#ifndef CONFIG_PCI_PNP ++static struct pci_config_table pci_mpc83xxemds_config_table[] = { ++ { ++ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, ++ pci_cfgfunc_config_device, ++ {PCI_ENET0_IOADDR, ++ PCI_ENET0_MEMADDR, ++ PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} ++ }, ++ {} ++} ++#endif ++static struct pci_controller hose[] = { ++ { ++#ifndef CONFIG_PCI_PNP ++ config_table:pci_mpc83xxemds_config_table, ++#endif ++ }, ++}; ++ ++/********************************************************************** ++ * pci_init_board() ++ *********************************************************************/ ++void pci_init_board(void) ++#ifdef CONFIG_PCISLAVE ++{ ++ u16 reg16; ++ volatile immap_t *immr; ++ volatile law83xx_t *pci_law; ++ volatile pot83xx_t *pci_pot; ++ volatile pcictrl83xx_t *pci_ctrl; ++ volatile pciconf83xx_t *pci_conf; ++ ++ immr = (immap_t *) CFG_IMMR; ++ pci_law = immr->sysconf.pcilaw; ++ pci_pot = immr->ios.pot; ++ pci_ctrl = immr->pci_ctrl; ++ pci_conf = immr->pci_conf; ++ /* ++ * Configure PCI Inbound Translation Windows ++ */ ++ pci_ctrl[0].pitar0 = 0x0; ++ pci_ctrl[0].pibar0 = 0x0; ++ pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP | ++ PIWAR_WTT_SNOOP | PIWAR_IWS_4K; ++ ++ pci_ctrl[0].pitar1 = 0x0; ++ pci_ctrl[0].pibar1 = 0x0; ++ pci_ctrl[0].piebar1 = 0x0; ++ pci_ctrl[0].piwar1 &= ~PIWAR_EN; ++ ++ pci_ctrl[0].pitar2 = 0x0; ++ pci_ctrl[0].pibar2 = 0x0; ++ pci_ctrl[0].piebar2 = 0x0; ++ pci_ctrl[0].piwar2 &= ~PIWAR_EN; ++ ++ hose[0].first_busno = 0; ++ hose[0].last_busno = 0xff; ++ pci_setup_indirect(&hose[0], ++ (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); ++ reg16 = 0xff; ++ ++ pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), ++ PCI_COMMAND, ®16); ++ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY; ++ pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), ++ PCI_COMMAND, reg16); ++ ++ /* ++ * Clear non-reserved bits in status register. ++ */ ++ pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), ++ PCI_STATUS, 0xffff); ++ pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0), ++ PCI_LATENCY_TIMER, 0x80); ++ ++ /* ++ * Unlock configuration lock in PCI function configuration register. ++ */ ++ pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), ++ PCI_FUNCTION_CONFIG, ®16); ++ reg16 &= ~(PCI_FUNCTION_CFG_LOCK); ++ pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), ++ PCI_FUNCTION_CONFIG, reg16); ++ ++ printf("Enabled PCI 32bit Agent Mode\n"); ++} ++#else ++{ ++ volatile immap_t *immr; ++ volatile clk83xx_t *clk; ++ volatile law83xx_t *pci_law; ++ volatile pot83xx_t *pci_pot; ++ volatile pcictrl83xx_t *pci_ctrl; ++ volatile pciconf83xx_t *pci_conf; ++ ++ u8 val8, orig_i2c_bus; ++ u16 reg16; ++ u32 val32; ++ u32 dev; ++ ++ immr = (immap_t *) CFG_IMMR; ++ clk = (clk83xx_t *) & immr->clk; ++ pci_law = immr->sysconf.pcilaw; ++ pci_pot = immr->ios.pot; ++ pci_ctrl = immr->pci_ctrl; ++ pci_conf = immr->pci_conf; ++ /* ++ * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode ++ */ ++ val32 = clk->occr; ++ udelay(2000); ++#if defined(PCI_66M) ++ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; ++ printf("PCI clock is 66MHz\n"); ++#elif defined(PCI_33M) ++ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | ++ OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; ++ printf("PCI clock is 33MHz\n"); ++#else ++ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; ++ printf("PCI clock is 66MHz\n"); ++#endif ++ udelay(2000); ++ ++ /* ++ * Configure PCI Local Access Windows ++ */ ++ pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; ++ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; ++ ++ pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; ++ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; ++ ++ /* ++ * Configure PCI Outbound Translation Windows ++ */ ++ ++ /* PCI mem space - prefetch */ ++ pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; ++ pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; ++ pci_pot[0].pocmr = ++ POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK); ++ ++ /* PCI mmio - non-prefetch mem space */ ++ pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; ++ pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; ++ pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); ++ ++ /* PCI IO space */ ++ pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK; ++ pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; ++ pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); ++ ++ /* ++ * Configure PCI Inbound Translation Windows ++ */ ++ pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; ++ pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; ++ pci_ctrl[0].piebar1 = 0x0; ++ pci_ctrl[0].piwar1 = ++ PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | ++ PIWAR_IWS_2G; ++ ++ /* ++ * Assign PIB PMC slot to desired PCI bus ++ */ ++ ++ /* Switch temporarily to I2C bus #2 */ ++ orig_i2c_bus = i2c_get_bus_num(); ++ i2c_set_bus_num(1); ++ ++ val8 = 0; ++ i2c_write(0x23, 0x6, 1, &val8, 1); ++ i2c_write(0x23, 0x7, 1, &val8, 1); ++ val8 = 0xff; ++ i2c_write(0x23, 0x2, 1, &val8, 1); ++ i2c_write(0x23, 0x3, 1, &val8, 1); ++ ++ val8 = 0; ++ i2c_write(0x26, 0x6, 1, &val8, 1); ++ val8 = 0x34; ++ i2c_write(0x26, 0x7, 1, &val8, 1); ++ ++ val8 = 0xf3; /*PMC1, PMC2, PMC3 slot to PCI bus */ ++ i2c_write(0x26, 0x2, 1, &val8, 1); ++ val8 = 0xff; ++ i2c_write(0x26, 0x3, 1, &val8, 1); ++ ++ val8 = 0; ++ i2c_write(0x27, 0x6, 1, &val8, 1); ++ i2c_write(0x27, 0x7, 1, &val8, 1); ++ val8 = 0xff; ++ i2c_write(0x27, 0x2, 1, &val8, 1); ++ val8 = 0xef; ++ i2c_write(0x27, 0x3, 1, &val8, 1); ++ asm("eieio"); ++ ++ /* Reset to original I2C bus */ ++ i2c_set_bus_num(orig_i2c_bus); ++ ++ /* ++ * Release PCI RST Output signal ++ */ ++ udelay(2000); ++ pci_ctrl[0].gcr = 1; ++ udelay(2000); ++ ++ hose[0].first_busno = 0; ++ hose[0].last_busno = 0xff; ++ ++ /* PCI memory prefetch space */ ++ pci_set_region(hose[0].regions + 0, ++ CFG_PCI_MEM_BASE, ++ CFG_PCI_MEM_PHYS, ++ CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); ++ ++ /* PCI memory space */ ++ pci_set_region(hose[0].regions + 1, ++ CFG_PCI_MMIO_BASE, ++ CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM); ++ ++ /* PCI IO space */ ++ pci_set_region(hose[0].regions + 2, ++ CFG_PCI_IO_BASE, ++ CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); ++ ++ /* System memory space */ ++ pci_set_region(hose[0].regions + 3, ++ CFG_PCI_SLV_MEM_LOCAL, ++ CFG_PCI_SLV_MEM_BUS, ++ CFG_PCI_SLV_MEM_SIZE, ++ PCI_REGION_MEM | PCI_REGION_MEMORY); ++ ++ hose[0].region_count = 4; ++ ++ pci_setup_indirect(&hose[0], ++ (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); ++ ++ pci_register_hose(hose); ++ ++ /* ++ * Write command register ++ */ ++ reg16 = 0xff; ++ dev = PCI_BDF(0, 0, 0); ++ pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16); ++ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; ++ pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16); ++ ++ /* ++ * Clear non-reserved bits in status register. ++ */ ++ pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff); ++ pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); ++ pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); ++ ++ printf("PCI 32bit bus on PMC1 & PMC2 & PMC3\n"); ++ ++ /* ++ * Hose scan. ++ */ ++ hose->last_busno = pci_hose_scan(hose); ++} ++#endif /* CONFIG_PCISLAVE */ ++ ++#ifdef CONFIG_OF_FLAT_TREE ++void ++ft_pci_setup(void *blob, bd_t *bd) ++{ ++ u32 *p; ++ int len; ++ ++ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); ++ if (p != NULL) { ++ p[0] = hose[0].first_busno; ++ p[1] = hose[0].last_busno; ++ } ++} ++#endif /* CONFIG_OF_FLAT_TREE */ ++#endif /* CONFIG_PCI */ +diff -Naupr u-boot-1.1.6/board/mpc8360emds/u-boot.lds u-boot-1.1.6-fsl-1/board/mpc8360emds/u-boot.lds +--- u-boot-1.1.6/board/mpc8360emds/u-boot.lds 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/mpc8360emds/u-boot.lds 2006-11-10 11:24:28.000000000 -0600 +@@ -0,0 +1,123 @@ ++/* ++ * (C) Copyright 2006 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_ARCH(powerpc) ++SECTIONS ++{ ++ /* Read-only sections, merged into text segment: */ ++ . = + SIZEOF_HEADERS; ++ .interp : { *(.interp) } ++ .hash : { *(.hash) } ++ .dynsym : { *(.dynsym) } ++ .dynstr : { *(.dynstr) } ++ .rel.text : { *(.rel.text) } ++ .rela.text : { *(.rela.text) } ++ .rel.data : { *(.rel.data) } ++ .rela.data : { *(.rela.data) } ++ .rel.rodata : { *(.rel.rodata) } ++ .rela.rodata : { *(.rela.rodata) } ++ .rel.got : { *(.rel.got) } ++ .rela.got : { *(.rela.got) } ++ .rel.ctors : { *(.rel.ctors) } ++ .rela.ctors : { *(.rela.ctors) } ++ .rel.dtors : { *(.rel.dtors) } ++ .rela.dtors : { *(.rela.dtors) } ++ .rel.bss : { *(.rel.bss) } ++ .rela.bss : { *(.rela.bss) } ++ .rel.plt : { *(.rel.plt) } ++ .rela.plt : { *(.rela.plt) } ++ .init : { *(.init) } ++ .plt : { *(.plt) } ++ .text : ++ { ++ cpu/mpc83xx/start.o (.text) ++ *(.text) ++ *(.fixup) ++ *(.got1) ++ . = ALIGN(16); ++ *(.rodata) ++ *(.rodata1) ++ *(.rodata.str1.4) ++ *(.eh_frame) ++ } ++ .fini : { *(.fini) } =0 ++ .ctors : { *(.ctors) } ++ .dtors : { *(.dtors) } ++ ++ /* Read-write section, merged into data segment: */ ++ . = (. + 0x0FFF) & 0xFFFFF000; ++ _erotext = .; ++ PROVIDE (erotext = .); ++ .reloc : ++ { ++ *(.got) ++ _GOT2_TABLE_ = .; ++ *(.got2) ++ _FIXUP_TABLE_ = .; ++ *(.fixup) ++ } ++ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; ++ __fixup_entries = (. - _FIXUP_TABLE_) >> 2; ++ ++ .data : ++ { ++ *(.data) ++ *(.data1) ++ *(.sdata) ++ *(.sdata2) ++ *(.dynamic) ++ CONSTRUCTORS ++ } ++ _edata = .; ++ PROVIDE (edata = .); ++ ++ . = .; ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ ++ . = .; ++ __start___ex_table = .; ++ __ex_table : { *(__ex_table) } ++ __stop___ex_table = .; ++ ++ . = ALIGN(4096); ++ __init_begin = .; ++ .text.init : { *(.text.init) } ++ .data.init : { *(.data.init) } ++ . = ALIGN(4096); ++ __init_end = .; ++ ++ __bss_start = .; ++ .bss : ++ { ++ *(.sbss) *(.scommon) ++ *(.dynbss) ++ *(.bss) ++ *(COMMON) ++ } ++ _end = . ; ++ PROVIDE (end = .); ++} ++ENTRY(_start) +diff -Naupr u-boot-1.1.6/board/prodrive/alpr/alpr.c u-boot-1.1.6-fsl-1/board/prodrive/alpr/alpr.c +--- u-boot-1.1.6/board/prodrive/alpr/alpr.c 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/alpr/alpr.c 2006-11-30 12:34:13.000000000 -0600 +@@ -0,0 +1,328 @@ ++/* ++ * (C) Copyright 2006 ++ * Stefan Roese, DENX Software Engineering, sr@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++ ++#include ++#include ++#include ++#include ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++extern int alpr_fpga_init(void); ++ ++int board_early_init_f (void) ++{ ++ /*------------------------------------------------------------------------- ++ * Initialize EBC CONFIG ++ *-------------------------------------------------------------------------*/ ++ mtebc(xbcfg, EBC_CFG_LE_UNLOCK | ++ EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK | ++ EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | ++ EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | ++ EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); ++ ++ /*-------------------------------------------------------------------- ++ * Setup the interrupt controller polarities, triggers, etc. ++ *-------------------------------------------------------------------*/ ++ mtdcr (uic0sr, 0xffffffff); /* clear all */ ++ mtdcr (uic0er, 0x00000000); /* disable all */ ++ mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ ++ mtdcr (uic0pr, 0xfffffe03); /* per manual */ ++ mtdcr (uic0tr, 0x01c00000); /* per manual */ ++ mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ ++ mtdcr (uic0sr, 0xffffffff); /* clear all */ ++ ++ mtdcr (uic1sr, 0xffffffff); /* clear all */ ++ mtdcr (uic1er, 0x00000000); /* disable all */ ++ mtdcr (uic1cr, 0x00000000); /* all non-critical */ ++ mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */ ++ mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */ ++ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ ++ mtdcr (uic1sr, 0xffffffff); /* clear all */ ++ ++ mtdcr (uic2sr, 0xffffffff); /* clear all */ ++ mtdcr (uic2er, 0x00000000); /* disable all */ ++ mtdcr (uic2cr, 0x00000000); /* all non-critical */ ++ mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */ ++ mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */ ++ mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ ++ mtdcr (uic2sr, 0xffffffff); /* clear all */ ++ ++ mtdcr (uicb0sr, 0xfc000000); /* clear all */ ++ mtdcr (uicb0er, 0x00000000); /* disable all */ ++ mtdcr (uicb0cr, 0x00000000); /* all non-critical */ ++ mtdcr (uicb0pr, 0xfc000000); /* */ ++ mtdcr (uicb0tr, 0x00000000); /* */ ++ mtdcr (uicb0vr, 0x00000001); /* */ ++ ++ /* Setup GPIO/IRQ multiplexing */ ++ mtsdr(sdr_pfc0, 0x01a03e00); ++ ++ return 0; ++} ++ ++int last_stage_init(void) ++{ ++ unsigned short reg; ++ ++ /* ++ * Configure LED's of both Marvell 88E1111 PHY's ++ * ++ * This has to be done after the 4xx ethernet driver is loaded, ++ * so "last_stage_init()" is the right place. ++ */ ++ miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, ®); ++ reg |= 0x0001; ++ miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg); ++ miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, ®); ++ reg |= 0x0001; ++ miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg); ++ ++ return 0; ++} ++ ++static int board_rev(void) ++{ ++ int rev; ++ u32 pfc0; ++ ++ /* Setup GPIO14 & 15 as GPIO */ ++ mfsdr(sdr_pfc0, pfc0); ++ pfc0 |= CFG_GPIO_REV0 | CFG_GPIO_REV1; ++ mtsdr(sdr_pfc0, pfc0); ++ ++ /* Setup as input */ ++ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0)); ++ out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0)); ++ ++ rev = (in32(GPIO0_IR) >> 16) & 0x3; ++ ++ /* Setup GPIO14 & 15 as non GPIO again */ ++ mfsdr(sdr_pfc0, pfc0); ++ pfc0 &= ~(CFG_GPIO_REV0 | CFG_GPIO_REV1); ++ mtsdr(sdr_pfc0, pfc0); ++ ++ return rev; ++} ++ ++int checkboard (void) ++{ ++ char *s = getenv ("serial#"); ++ ++ printf ("Board: ALPR"); ++ if (s != NULL) { ++ puts (", serial# "); ++ puts (s); ++ } ++ printf(" (Rev. %d)\n", board_rev()); ++ ++ return (0); ++} ++ ++#if defined(CFG_DRAM_TEST) ++int testdram (void) ++{ ++ uint *pstart = (uint *) 0x00000000; ++ uint *pend = (uint *) 0x08000000; ++ uint *p; ++ ++ for (p = pstart; p < pend; p++) ++ *p = 0xaaaaaaaa; ++ ++ for (p = pstart; p < pend; p++) { ++ if (*p != 0xaaaaaaaa) { ++ printf ("SDRAM test fails at: %08x\n", (uint) p); ++ return 1; ++ } ++ } ++ ++ for (p = pstart; p < pend; p++) ++ *p = 0x55555555; ++ ++ for (p = pstart; p < pend; p++) { ++ if (*p != 0x55555555) { ++ printf ("SDRAM test fails at: %08x\n", (uint) p); ++ return 1; ++ } ++ } ++ return 0; ++} ++#endif ++ ++/************************************************************************* ++ * pci_pre_init ++ * ++ * This routine is called just prior to registering the hose and gives ++ * the board the opportunity to check things. Returning a value of zero ++ * indicates that things are bad & PCI initialization should be aborted. ++ * ++ * Different boards may wish to customize the pci controller structure ++ * (add regions, override default access routines, etc) or perform ++ * certain pre-initialization actions. ++ * ++ ************************************************************************/ ++#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) ++int pci_pre_init(struct pci_controller * hose ) ++{ ++ unsigned long strap; ++ ++ /*--------------------------------------------------------------------------+ ++ * The ocotea board is always configured as the host & requires the ++ * PCI arbiter to be enabled. ++ *--------------------------------------------------------------------------*/ ++ mfsdr(sdr_sdstp1, strap); ++ if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ ++ printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); ++ return 0; ++ } ++ ++ /* FPGA Init */ ++ alpr_fpga_init (); ++ ++ return 1; ++} ++#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ ++ ++/************************************************************************* ++ * pci_target_init ++ * ++ * The bootstrap configuration provides default settings for the pci ++ * inbound map (PIM). But the bootstrap config choices are limited and ++ * may not be sufficient for a given board. ++ * ++ ************************************************************************/ ++#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) ++void pci_target_init(struct pci_controller * hose ) ++{ ++ /*--------------------------------------------------------------------------+ ++ * Disable everything ++ *--------------------------------------------------------------------------*/ ++ out32r( PCIX0_PIM0SA, 0 ); /* disable */ ++ out32r( PCIX0_PIM1SA, 0 ); /* disable */ ++ out32r( PCIX0_PIM2SA, 0 ); /* disable */ ++ out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ ++ ++ /*--------------------------------------------------------------------------+ ++ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping ++ * options to not support sizes such as 128/256 MB. ++ *--------------------------------------------------------------------------*/ ++ out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); ++ out32r( PCIX0_PIM0LAH, 0 ); ++ out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); ++ ++ out32r( PCIX0_BAR0, 0 ); ++ ++ /*--------------------------------------------------------------------------+ ++ * Program the board's subsystem id/vendor id ++ *--------------------------------------------------------------------------*/ ++ out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); ++ out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); ++ ++ out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); ++} ++#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ ++ ++/************************************************************************* ++ * is_pci_host ++ * ++ * This routine is called to determine if a pci scan should be ++ * performed. With various hardware environments (especially cPCI and ++ * PPMC) it's insufficient to depend on the state of the arbiter enable ++ * bit in the strap register, or generic host/adapter assumptions. ++ * ++ * Rather than hard-code a bad assumption in the general 440 code, the ++ * 440 pci code requires the board to decide at runtime. ++ * ++ * Return 0 for adapter mode, non-zero for host (monarch) mode. ++ * ++ * ++ ************************************************************************/ ++#if defined(CONFIG_PCI) ++ ++static void wait_for_pci_ready(void) ++{ ++ /* ++ * Configure EREADY as input ++ */ ++ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_GPIO_EREADY); ++ udelay(1000); ++ ++ for (;;) { ++ if (in32(GPIO0_IR) & CFG_GPIO_EREADY) ++ return; ++ } ++ ++} ++ ++int is_pci_host(struct pci_controller *hose) ++{ ++ wait_for_pci_ready(); ++ return 1; /* return 1 for host controller */ ++} ++#endif /* defined(CONFIG_PCI) */ ++ ++/************************************************************************* ++ * pci_master_init ++ * ++ ************************************************************************/ ++#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) ++void pci_master_init(struct pci_controller *hose) ++{ ++ /*--------------------------------------------------------------------------+ ++ | PowerPC440 PCI Master configuration. ++ | Map PLB/processor addresses to PCI memory space. ++ | PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF ++ | Use byte reversed out routines to handle endianess. ++ | Make this region non-prefetchable. ++ +--------------------------------------------------------------------------*/ ++ out32r( PCIX0_POM0SA, 0 ); /* disable */ ++ out32r( PCIX0_POM1SA, 0 ); /* disable */ ++ out32r( PCIX0_POM2SA, 0 ); /* disable */ ++ ++ out32r(PCIX0_POM0LAL, CFG_PCI_MEMBASE); /* PMM0 Local Address */ ++ out32r(PCIX0_POM0LAH, 0x00000003); /* PMM0 Local Address */ ++ out32r(PCIX0_POM0PCIAL, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ ++ out32r(PCIX0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */ ++ out32r(PCIX0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ ++ ++ out32r(PCIX0_POM1LAL, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ ++ out32r(PCIX0_POM1LAH, 0x00000003); /* PMM0 Local Address */ ++ out32r(PCIX0_POM1PCIAL, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ ++ out32r(PCIX0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */ ++ out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ ++} ++#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ ++ ++#ifdef CONFIG_POST ++/* ++ * Returns 1 if keys pressed to start the power-on long-running tests ++ * Called from board_init_f(). ++ */ ++int post_hotkeys_pressed(void) ++{ ++ ++ return (ctrlc()); ++} ++#endif +diff -Naupr u-boot-1.1.6/board/prodrive/alpr/config.mk u-boot-1.1.6-fsl-1/board/prodrive/alpr/config.mk +--- u-boot-1.1.6/board/prodrive/alpr/config.mk 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/alpr/config.mk 2006-11-30 12:34:13.000000000 -0600 +@@ -0,0 +1,44 @@ ++# ++# (C) Copyright 2004 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++# ++# AMCC 440GX Reference Platform (Ocotea) board ++# ++ ++#TEXT_BASE = 0xFFFE0000 ++ ++ifeq ($(ramsym),1) ++TEXT_BASE = 0x07FD0000 ++else ++TEXT_BASE = 0xFFFC0000 ++endif ++ ++PLATFORM_CPPFLAGS += -DCONFIG_440=1 ++ ++ifeq ($(debug),1) ++PLATFORM_CPPFLAGS += -DDEBUG ++endif ++ ++ifeq ($(dbcr),1) ++PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 ++endif +diff -Naupr u-boot-1.1.6/board/prodrive/alpr/fpga.c u-boot-1.1.6-fsl-1/board/prodrive/alpr/fpga.c +--- u-boot-1.1.6/board/prodrive/alpr/fpga.c 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/alpr/fpga.c 2006-11-30 12:34:13.000000000 -0600 +@@ -0,0 +1,257 @@ ++/* ++ * (C) Copyright 2006 ++ * Heiko Schocher, DENX Software Engineering, hs@denx.de ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++ ++/* ++ * Altera FPGA configuration support for the ALPR computer from prodrive ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "fpga.h" ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#if defined(CONFIG_FPGA) ++ ++#ifdef FPGA_DEBUG ++#define PRINTF(fmt,args...) printf (fmt ,##args) ++#else ++#define PRINTF(fmt,args...) ++#endif ++ ++static unsigned long regval; ++ ++#define SET_GPIO_REG_0(reg, bit) { \ ++ regval = in32(reg); \ ++ regval &= ~(0x80000000 >> bit); \ ++ out32(reg, regval); \ ++ } ++ ++#define SET_GPIO_REG_1(reg, bit) { \ ++ regval = in32(reg); \ ++ regval |= (0x80000000 >> bit); \ ++ out32(reg, regval); \ ++ } ++ ++#define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit) ++#define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit) ++ ++#define FPGA_PRG (0x80000000 >> CFG_GPIO_PROG_EN) ++#define FPGA_CONFIG (0x80000000 >> CFG_GPIO_CONFIG) ++#define FPGA_DATA (0x80000000 >> CFG_GPIO_DATA) ++#define FPGA_CLK (0x80000000 >> CFG_GPIO_CLK) ++#define OLD_VAL (FPGA_PRG | FPGA_CONFIG) ++ ++#define SET_FPGA(data) out32(GPIO0_OR, data) ++ ++#define FPGA_WRITE_1 { \ ++ SET_FPGA(OLD_VAL | 0 | FPGA_DATA); /* set data to 1 */ \ ++ SET_FPGA(OLD_VAL | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ ++ ++#define FPGA_WRITE_0 { \ ++ SET_FPGA(OLD_VAL | 0 | 0 ); /* set data to 0 */ \ ++ SET_FPGA(OLD_VAL | FPGA_CLK | 0 );} /* set data to 1 */ ++ ++/* Plattforminitializations */ ++/* Here we have to set the FPGA Chain */ ++/* PROGRAM_PROG_EN = HIGH */ ++/* PROGRAM_SEL_DPR = LOW */ ++int fpga_pre_fn (int cookie) ++{ ++ unsigned long reg; ++ ++ reg = in32(GPIO0_IR); ++ /* Enable the FPGA Chain */ ++ SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_PROG_EN); ++ SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_PROG_EN); ++ SET_GPIO_1(CFG_GPIO_PROG_EN); ++ SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_SEL_DPR); ++ SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_SEL_DPR); ++ SET_GPIO_0((CFG_GPIO_SEL_DPR)); ++ ++ /* initialize the GPIO Pins */ ++ /* output */ ++ SET_GPIO_0(CFG_GPIO_CLK); ++ SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CLK); ++ SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CLK); ++ ++ /* output */ ++ SET_GPIO_0(CFG_GPIO_DATA); ++ SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_DATA); ++ SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_DATA); ++ ++ /* First we set STATUS to 0 then as an input */ ++ SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_STATUS); ++ SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_STATUS); ++ SET_GPIO_0(CFG_GPIO_STATUS); ++ SET_GPIO_REG_0(GPIO0_TCR, CFG_GPIO_STATUS); ++ SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_STATUS); ++ ++ /* output */ ++ SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CONFIG); ++ SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CONFIG); ++ SET_GPIO_0(CFG_GPIO_CONFIG); ++ ++ /* input */ ++ SET_GPIO_0(CFG_GPIO_CON_DON); ++ SET_GPIO_REG_0(GPIO0_TCR, CFG_GPIO_CON_DON); ++ SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CON_DON); ++ ++ /* CONFIG = 0 STATUS = 0 -> FPGA in reset state */ ++ SET_GPIO_0(CFG_GPIO_CONFIG); ++ return FPGA_SUCCESS; ++} ++ ++/* Set the state of CONFIG Pin */ ++int fpga_config_fn (int assert_config, int flush, int cookie) ++{ ++ if (assert_config) { ++ SET_GPIO_1(CFG_GPIO_CONFIG); ++ } else { ++ SET_GPIO_0(CFG_GPIO_CONFIG); ++ } ++ return FPGA_SUCCESS; ++} ++ ++/* Returns the state of STATUS Pin */ ++int fpga_status_fn (int cookie) ++{ ++ unsigned long reg; ++ ++ reg = in32(GPIO0_IR); ++ if (reg &= (0x80000000 >> CFG_GPIO_STATUS)) { ++ PRINTF("STATUS = HIGH\n"); ++ return FPGA_FAIL; ++ } ++ PRINTF("STATUS = LOW\n"); ++ return FPGA_SUCCESS; ++} ++ ++/* Returns the state of CONF_DONE Pin */ ++int fpga_done_fn (int cookie) ++{ ++ unsigned long reg; ++ reg = in32(GPIO0_IR); ++ if (reg &= (0x80000000 >> CFG_GPIO_CON_DON)) { ++ PRINTF("CONF_DON = HIGH\n"); ++ return FPGA_FAIL; ++ } ++ PRINTF("CONF_DON = LOW\n"); ++ return FPGA_SUCCESS; ++} ++ ++/* writes the complete buffer to the FPGA ++ writing the complete buffer in one function is much faster, ++ then calling it for every bit */ ++int fpga_write_fn (void *buf, size_t len, int flush, int cookie) ++{ ++ size_t bytecount = 0; ++ unsigned char *data = (unsigned char *) buf; ++ unsigned char val=0; ++ int i; ++ int len_40 = len / 40; ++ ++ while (bytecount < len) { ++ val = data[bytecount++]; ++ i = 8; ++ do { ++ if (val & 0x01) { ++ FPGA_WRITE_1; ++ } else { ++ FPGA_WRITE_0; ++ } ++ val >>= 1; ++ i --; ++ } while (i > 0); ++ ++#ifdef CFG_FPGA_PROG_FEEDBACK ++ if (bytecount % len_40 == 0) { ++ putc ('.'); /* let them know we are alive */ ++#ifdef CFG_FPGA_CHECK_CTRLC ++ if (ctrlc ()) ++ return FPGA_FAIL; ++#endif ++ } ++#endif ++ } ++ return FPGA_SUCCESS; ++} ++ ++/* called, when programming is aborted */ ++int fpga_abort_fn (int cookie) ++{ ++ SET_GPIO_1((CFG_GPIO_SEL_DPR)); ++ return FPGA_SUCCESS; ++} ++ ++/* called, when programming was succesful */ ++int fpga_post_fn (int cookie) ++{ ++ return fpga_abort_fn (cookie); ++} ++ ++/* Note that these are pointers to code that is in Flash. They will be ++ * relocated at runtime. ++ */ ++Altera_CYC2_Passive_Serial_fns fpga_fns = { ++ fpga_pre_fn, ++ fpga_config_fn, ++ fpga_status_fn, ++ fpga_done_fn, ++ fpga_write_fn, ++ fpga_abort_fn, ++ fpga_post_fn ++}; ++ ++Altera_desc fpga[CONFIG_FPGA_COUNT] = { ++ {Altera_CYC2, ++ passive_serial, ++ Altera_EP2C35_SIZE, ++ (void *) &fpga_fns, ++ NULL, ++ 0} ++}; ++ ++/* ++ * Initialize the fpga. Return 1 on success, 0 on failure. ++ */ ++int alpr_fpga_init (void) ++{ ++ int i; ++ ++ PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off); ++ fpga_init (gd->reloc_off); ++ ++ for (i = 0; i < CONFIG_FPGA_COUNT; i++) { ++ PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i); ++ fpga_add (fpga_altera, &fpga[i]); ++ } ++ return 1; ++} ++ ++#endif +diff -Naupr u-boot-1.1.6/board/prodrive/alpr/init.S u-boot-1.1.6-fsl-1/board/prodrive/alpr/init.S +--- u-boot-1.1.6/board/prodrive/alpr/init.S 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/alpr/init.S 2006-11-30 12:34:13.000000000 -0600 +@@ -0,0 +1,103 @@ ++/* ++ * (C) Copyright 2006 ++ * Stefan Roese, DENX Software Engineering, sr@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++ ++/* General */ ++#define TLB_VALID 0x00000200 ++ ++/* Supported page sizes */ ++#define SZ_1K 0x00000000 ++#define SZ_4K 0x00000010 ++#define SZ_16K 0x00000020 ++#define SZ_64K 0x00000030 ++#define SZ_256K 0x00000040 ++#define SZ_1M 0x00000050 ++#define SZ_16M 0x00000070 ++#define SZ_256M 0x00000090 ++ ++/* Storage attributes */ ++#define SA_W 0x00000800 /* Write-through */ ++#define SA_I 0x00000400 /* Caching inhibited */ ++#define SA_M 0x00000200 /* Memory coherence */ ++#define SA_G 0x00000100 /* Guarded */ ++#define SA_E 0x00000080 /* Endian */ ++ ++/* Access control */ ++#define AC_X 0x00000024 /* Execute */ ++#define AC_W 0x00000012 /* Write */ ++#define AC_R 0x00000009 /* Read */ ++ ++/* Some handy macros */ ++ ++#define EPN(e) ((e) & 0xfffffc00) ++#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) ++#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) ++#define TLB2(a) ( (a)&0x00000fbf ) ++ ++#define tlbtab_start\ ++ mflr r1 ;\ ++ bl 0f ; ++ ++#define tlbtab_end\ ++ .long 0, 0, 0 ; \ ++0: mflr r0 ; \ ++ mtlr r1 ; \ ++ blr ; ++ ++#define tlbentry(epn,sz,rpn,erpn,attr)\ ++ .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) ++ ++ ++/************************************************************************** ++ * TLB TABLE ++ * ++ * This table is used by the cpu boot code to setup the initial tlb ++ * entries. Rather than make broad assumptions in the cpu source tree, ++ * this table lets each board set things up however they like. ++ * ++ * Pointer to the table is returned in r1 ++ * ++ *************************************************************************/ ++ ++ .section .bootpg,"ax" ++ .globl tlbtab ++ ++tlbtab: ++ tlbtab_start ++ tlbentry( 0xff000000, SZ_16M, 0xff000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) ++ tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I ) ++ tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) ++ tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) ++ tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) ++ tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) ++ ++ /* PCI */ ++ tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I ) ++ tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I ) ++ tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I ) ++ ++ /* NAND */ ++ tlbentry( CFG_NAND_BASE, SZ_4K, CFG_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) ++ tlbtab_end +diff -Naupr u-boot-1.1.6/board/prodrive/alpr/Makefile u-boot-1.1.6-fsl-1/board/prodrive/alpr/Makefile +--- u-boot-1.1.6/board/prodrive/alpr/Makefile 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/alpr/Makefile 2006-11-30 12:34:13.000000000 -0600 +@@ -0,0 +1,51 @@ ++# ++# (C) Copyright 2006 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).a ++ ++COBJS = $(BOARD).o fpga.o nand.o ++SOBJS = init.o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(OBJS) $(SOBJS) ++ $(AR) $(ARFLAGS) $@ $(OBJS) ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak .depend *~ ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +diff -Naupr u-boot-1.1.6/board/prodrive/alpr/nand.c u-boot-1.1.6-fsl-1/board/prodrive/alpr/nand.c +--- u-boot-1.1.6/board/prodrive/alpr/nand.c 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/alpr/nand.c 2006-11-30 12:34:13.000000000 -0600 +@@ -0,0 +1,173 @@ ++/* ++ * (C) Copyright 2006 ++ * Heiko Schocher, DENX Software Engineering, hs@denx.de ++ * ++ * (C) Copyright 2006 ++ * Stefan Roese, DENX Software Engineering, sr@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++ ++#if (CONFIG_COMMANDS & CFG_CMD_NAND) ++ ++#include ++#include ++ ++struct alpr_ndfc_regs { ++ u8 cmd[4]; ++ u8 addr_wait; ++ u8 term; ++ u8 dummy; ++ u8 dummy2; ++ u8 data; ++}; ++ ++static u8 hwctl; ++static struct alpr_ndfc_regs *alpr_ndfc = NULL; ++ ++#define readb(addr) (u8)(*(volatile u8 *)(addr)) ++#define writeb(d,addr) *(volatile u8 *)(addr) = ((u8)(d)) ++ ++/* ++ * The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to ++ * the NAND devices. The NDFC has command, address and data registers that ++ * when accessed will set up the NAND flash pins appropriately. We'll use the ++ * hwcontrol function to save the configuration in a global variable. ++ * We can then use this information in the read and write functions to ++ * determine which NDFC register to access. ++ * ++ * There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte). ++ */ ++static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd) ++{ ++ switch (cmd) { ++ case NAND_CTL_SETCLE: ++ hwctl |= 0x1; ++ break; ++ case NAND_CTL_CLRCLE: ++ hwctl &= ~0x1; ++ break; ++ case NAND_CTL_SETALE: ++ hwctl |= 0x2; ++ break; ++ case NAND_CTL_CLRALE: ++ hwctl &= ~0x2; ++ break; ++ case NAND_CTL_SETNCE: ++ break; ++ case NAND_CTL_CLRNCE: ++ writeb(0x00, &(alpr_ndfc->term)); ++ break; ++ } ++} ++ ++static void alpr_nand_write_byte(struct mtd_info *mtd, u_char byte) ++{ ++ struct nand_chip *nand = mtd->priv; ++ ++ if (hwctl & 0x1) ++ /* ++ * IO_ADDR_W used as CMD[i] reg to support multiple NAND ++ * chips. ++ */ ++ writeb(byte, nand->IO_ADDR_W); ++ else if (hwctl & 0x2) { ++ writeb(byte, &(alpr_ndfc->addr_wait)); ++ } else ++ writeb(byte, &(alpr_ndfc->data)); ++} ++ ++static u_char alpr_nand_read_byte(struct mtd_info *mtd) ++{ ++ return readb(&(alpr_ndfc->data)); ++} ++ ++static void alpr_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) ++{ ++ struct nand_chip *nand = mtd->priv; ++ int i; ++ ++ for (i = 0; i < len; i++) { ++ if (hwctl & 0x1) ++ /* ++ * IO_ADDR_W used as CMD[i] reg to support multiple NAND ++ * chips. ++ */ ++ writeb(buf[i], nand->IO_ADDR_W); ++ else if (hwctl & 0x2) ++ writeb(buf[i], &(alpr_ndfc->addr_wait)); ++ else ++ writeb(buf[i], &(alpr_ndfc->data)); ++ } ++} ++ ++static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) ++{ ++ int i; ++ ++ for (i = 0; i < len; i++) { ++ buf[i] = readb(&(alpr_ndfc->data)); ++ } ++} ++ ++static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) ++{ ++ int i; ++ ++ for (i = 0; i < len; i++) ++ if (buf[i] != readb(&(alpr_ndfc->data))) ++ return i; ++ ++ return 0; ++} ++ ++static int alpr_nand_dev_ready(struct mtd_info *mtd) ++{ ++ volatile u_char val; ++ ++ /* ++ * Blocking read to wait for NAND to be ready ++ */ ++ val = readb(&(alpr_ndfc->addr_wait)); ++ ++ /* ++ * Return always true ++ */ ++ return 1; ++} ++ ++void board_nand_init(struct nand_chip *nand) ++{ ++ alpr_ndfc = (struct alpr_ndfc_regs *)CFG_NAND_BASE; ++ ++ nand->eccmode = NAND_ECC_SOFT; ++ ++ /* Reference hardware control function */ ++ nand->hwcontrol = alpr_nand_hwcontrol; ++ /* Set command delay time */ ++ nand->write_byte = alpr_nand_write_byte; ++ nand->read_byte = alpr_nand_read_byte; ++ nand->write_buf = alpr_nand_write_buf; ++ nand->read_buf = alpr_nand_read_buf; ++ nand->verify_buf = alpr_nand_verify_buf; ++ nand->dev_ready = alpr_nand_dev_ready; ++} ++#endif +diff -Naupr u-boot-1.1.6/board/prodrive/alpr/u-boot.lds u-boot-1.1.6-fsl-1/board/prodrive/alpr/u-boot.lds +--- u-boot-1.1.6/board/prodrive/alpr/u-boot.lds 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/alpr/u-boot.lds 2006-11-30 12:34:13.000000000 -0600 +@@ -0,0 +1,157 @@ ++/* ++ * (C) Copyright 2004 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_ARCH(powerpc) ++SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); ++/* Do we need any of these for elf? ++ __DYNAMIC = 0; */ ++SECTIONS ++{ ++ .resetvec 0xFFFFFFFC : ++ { ++ *(.resetvec) ++ } = 0xffff ++ ++ .bootpg 0xFFFFF000 : ++ { ++ cpu/ppc4xx/start.o (.bootpg) ++ } = 0xffff ++ ++ /* Read-only sections, merged into text segment: */ ++ . = + SIZEOF_HEADERS; ++ .interp : { *(.interp) } ++ .hash : { *(.hash) } ++ .dynsym : { *(.dynsym) } ++ .dynstr : { *(.dynstr) } ++ .rel.text : { *(.rel.text) } ++ .rela.text : { *(.rela.text) } ++ .rel.data : { *(.rel.data) } ++ .rela.data : { *(.rela.data) } ++ .rel.rodata : { *(.rel.rodata) } ++ .rela.rodata : { *(.rela.rodata) } ++ .rel.got : { *(.rel.got) } ++ .rela.got : { *(.rela.got) } ++ .rel.ctors : { *(.rel.ctors) } ++ .rela.ctors : { *(.rela.ctors) } ++ .rel.dtors : { *(.rel.dtors) } ++ .rela.dtors : { *(.rela.dtors) } ++ .rel.bss : { *(.rel.bss) } ++ .rela.bss : { *(.rela.bss) } ++ .rel.plt : { *(.rel.plt) } ++ .rela.plt : { *(.rela.plt) } ++ .init : { *(.init) } ++ .plt : { *(.plt) } ++ .text : ++ { ++ /* WARNING - the following is hand-optimized to fit within */ ++ /* the sector layout of our flash chips! XXX FIXME XXX */ ++ ++ cpu/ppc4xx/start.o (.text) ++ board/prodrive/alpr/init.o (.text) ++ cpu/ppc4xx/kgdb.o (.text) ++ cpu/ppc4xx/traps.o (.text) ++ cpu/ppc4xx/interrupts.o (.text) ++ cpu/ppc4xx/serial.o (.text) ++ cpu/ppc4xx/cpu_init.o (.text) ++ cpu/ppc4xx/speed.o (.text) ++ common/dlmalloc.o (.text) ++ lib_generic/crc32.o (.text) ++ lib_ppc/extable.o (.text) ++ lib_generic/zlib.o (.text) ++ ++/* . = env_offset;*/ ++/* common/environment.o(.text)*/ ++ ++ *(.text) ++ *(.fixup) ++ *(.got1) ++ } ++ _etext = .; ++ PROVIDE (etext = .); ++ .rodata : ++ { ++ *(.rodata) ++ *(.rodata1) ++ *(.rodata.str1.4) ++ *(.eh_frame) ++ } ++ .fini : { *(.fini) } =0 ++ .ctors : { *(.ctors) } ++ .dtors : { *(.dtors) } ++ ++ /* Read-write section, merged into data segment: */ ++ . = (. + 0x00FF) & 0xFFFFFF00; ++ _erotext = .; ++ PROVIDE (erotext = .); ++ .reloc : ++ { ++ *(.got) ++ _GOT2_TABLE_ = .; ++ *(.got2) ++ _FIXUP_TABLE_ = .; ++ *(.fixup) ++ } ++ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; ++ __fixup_entries = (. - _FIXUP_TABLE_)>>2; ++ ++ .data : ++ { ++ *(.data) ++ *(.data1) ++ *(.sdata) ++ *(.sdata2) ++ *(.dynamic) ++ CONSTRUCTORS ++ } ++ _edata = .; ++ PROVIDE (edata = .); ++ ++ . = .; ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ ++ . = .; ++ __start___ex_table = .; ++ __ex_table : { *(__ex_table) } ++ __stop___ex_table = .; ++ ++ . = ALIGN(256); ++ __init_begin = .; ++ .text.init : { *(.text.init) } ++ .data.init : { *(.data.init) } ++ . = ALIGN(256); ++ __init_end = .; ++ ++ __bss_start = .; ++ .bss : ++ { ++ *(.sbss) *(.scommon) ++ *(.dynbss) ++ *(.bss) ++ *(COMMON) ++ } ++ _end = . ; ++ PROVIDE (end = .); ++} +diff -Naupr u-boot-1.1.6/board/prodrive/common/flash.c u-boot-1.1.6-fsl-1/board/prodrive/common/flash.c +--- u-boot-1.1.6/board/prodrive/common/flash.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/common/flash.c 2006-11-30 12:34:13.000000000 -0600 +@@ -48,6 +48,7 @@ void flash_print_info(flash_info_t *info + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; ++ case FLASH_MAN_STM: printf ("ST "); break; + case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break; + default: printf ("Unknown Vendor "); break; + } +@@ -156,6 +157,9 @@ static ulong flash_get_size(vu_long *add + case (CFG_FLASH_WORD_SIZE)SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; ++ case (CFG_FLASH_WORD_SIZE)STM_MANUFACT: ++ info->flash_id = FLASH_MAN_STM; ++ break; + case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT: + info->flash_id = FLASH_MAN_EXCEL; + break; +diff -Naupr u-boot-1.1.6/board/prodrive/p3mx/64460.h u-boot-1.1.6-fsl-1/board/prodrive/p3mx/64460.h +--- u-boot-1.1.6/board/prodrive/p3mx/64460.h 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/p3mx/64460.h 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,52 @@ ++/* ++ * (C) Copyright 2003 ++ * Ingo Assmus ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* ++ * main board support/init for the Galileo Eval board DB64460. ++ */ ++ ++#ifndef __64460_H__ ++#define __64460_H__ ++ ++/* CPU Configuration bits */ ++#define CPU_CONF_ADDR_MISS_EN (1 << 8) ++#define CPU_CONF_SINGLE_CPU (1 << 11) ++#define CPU_CONF_ENDIANESS (1 << 12) ++#define CPU_CONF_PIPELINE (1 << 13) ++#define CPU_CONF_STOP_RETRY (1 << 17) ++#define CPU_CONF_MULTI_DECODE (1 << 18) ++#define CPU_CONF_DP_VALID (1 << 19) ++#define CPU_CONF_PERR_PROP (1 << 22) ++#define CPU_CONF_AACK_DELAY_2 (1 << 25) ++#define CPU_CONF_AP_VALID (1 << 26) ++#define CPU_CONF_REMAP_WR_DIS (1 << 27) ++ ++/* CPU Master Control bits */ ++#define CPU_MAST_CTL_ARB_EN (1 << 8) ++#define CPU_MAST_CTL_MASK_BR_1 (1 << 9) ++#define CPU_MAST_CTL_M_WR_TRIG (1 << 10) ++#define CPU_MAST_CTL_M_RD_TRIG (1 << 11) ++#define CPU_MAST_CTL_CLEAN_BLK (1 << 12) ++#define CPU_MAST_CTL_FLUSH_BLK (1 << 13) ++ ++#endif /* __64460_H__ */ +diff -Naupr u-boot-1.1.6/board/prodrive/p3mx/config.mk u-boot-1.1.6-fsl-1/board/prodrive/p3mx/config.mk +--- u-boot-1.1.6/board/prodrive/p3mx/config.mk 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/p3mx/config.mk 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,28 @@ ++# ++# (C) Copyright 2002-2006 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++# ++# p3mx boards (P3M750 & P3M7448) ++# ++ ++TEXT_BASE = 0xfff00000 +diff -Naupr u-boot-1.1.6/board/prodrive/p3mx/eth.h u-boot-1.1.6-fsl-1/board/prodrive/p3mx/eth.h +--- u-boot-1.1.6/board/prodrive/p3mx/eth.h 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/p3mx/eth.h 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,43 @@ ++/* ++ * (C) Copyright 2001 ++ * Josh Huber , Mission Critical Linux, Inc. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* ++ * eth.h - header file for the polled mode GT ethernet driver ++ */ ++ ++#ifndef __EVB64360_ETH_H__ ++#define __EVB64360_ETH_H__ ++ ++#include ++#include ++#include ++#include ++ ++ ++int db64360_eth0_poll(void); ++int db64360_eth0_transmit(unsigned int s, volatile char *p); ++void db64360_eth0_disable(void); ++bool network_start(bd_t *bis); ++ ++ ++#endif /* __EVB64360_ETH_H__ */ +diff -Naupr u-boot-1.1.6/board/prodrive/p3mx/Makefile u-boot-1.1.6-fsl-1/board/prodrive/p3mx/Makefile +--- u-boot-1.1.6/board/prodrive/p3mx/Makefile 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/p3mx/Makefile 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,55 @@ ++# ++# (C) Copyright 2002-2006 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ifneq ($(OBJTREE),$(SRCTREE)) ++$(shell mkdir -p $(obj)../../Marvell/common) ++endif ++ ++LIB = $(obj)lib$(BOARD).a ++ ++SOBJS = misc.o ++COBJS = $(BOARD).o mpsc.o mv_eth.o pci.o sdram_init.o serial.o \ ++ ../../Marvell/common/i2c.o ../../Marvell/common/memory.o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak .depend *~ ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +diff -Naupr u-boot-1.1.6/board/prodrive/p3mx/misc.S u-boot-1.1.6-fsl-1/board/prodrive/p3mx/misc.S +--- u-boot-1.1.6/board/prodrive/p3mx/misc.S 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/p3mx/misc.S 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,245 @@ ++#include ++#include <74xx_7xx.h> ++#include "version.h" ++ ++#include ++#include ++ ++#include ++#include ++ ++#include "../../Marvell/include/mv_gen_reg.h" ++ ++#ifdef CONFIG_ECC ++ /* Galileo specific asm code for initializing ECC */ ++ .globl board_relocate_rom ++board_relocate_rom: ++ mflr r7 ++ /* update the location of the GT registers */ ++ lis r11, CFG_GT_REGS@h ++ /* if we're using ECC, we must use the DMA engine to copy ourselves */ ++ bl start_idma_transfer_0 ++ bl wait_for_idma_0 ++ bl stop_idma_engine_0 ++ ++ mtlr r7 ++ blr ++ ++ .globl board_init_ecc ++board_init_ecc: ++ mflr r7 ++ /* NOTE: r10 still contains the location we've been relocated to ++ * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */ ++ ++ /* now that we're running from ram, init the rest of main memory ++ * for ECC use */ ++ lis r8, CFG_MONITOR_LEN@h ++ ori r8, r8, CFG_MONITOR_LEN@l ++ ++ divw r3, r10, r8 ++ ++ /* set up the counter, and init the starting address */ ++ mtctr r3 ++ li r12, 0 ++ ++ /* bytes per transfer */ ++ mr r5, r8 ++about_to_init_ecc: ++1: mr r3, r12 ++ mr r4, r12 ++ bl start_idma_transfer_0 ++ bl wait_for_idma_0 ++ bl stop_idma_engine_0 ++ add r12, r12, r8 ++ bdnz 1b ++ ++ mtlr r7 ++ blr ++ ++ /* r3: dest addr ++ * r4: source addr ++ * r5: byte count ++ * r11: gt regbase ++ * trashes: r6, r5 ++ */ ++start_idma_transfer_0: ++ /* set the byte count, including the OWN bit */ ++ mr r6, r11 ++ ori r6, r6, CHANNEL0_DMA_BYTE_COUNT ++ stwbrx r5, 0, (r6) ++ ++ /* set the source address */ ++ mr r6, r11 ++ ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS ++ stwbrx r4, 0, (r6) ++ ++ /* set the dest address */ ++ mr r6, r11 ++ ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS ++ stwbrx r3, 0, (r6) ++ ++ /* set the next record pointer */ ++ li r5, 0 ++ mr r6, r11 ++ ori r6, r6, CHANNEL0NEXT_RECORD_POINTER ++ stwbrx r5, 0, (r6) ++ ++ /* set the low control register */ ++ /* bit 9 is NON chained mode, bit 31 is new style descriptors. ++ bit 12 is channel enable */ ++ ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11) ++ /* 15 shifted by 16 (oris) == bit 31 */ ++ oris r5, r5, (1 << 15) ++ mr r6, r11 ++ ori r6, r6, CHANNEL0CONTROL ++ stwbrx r5, 0, (r6) ++ ++ blr ++ ++ /* this waits for the bytecount to return to zero, indicating ++ * that the trasfer is complete */ ++wait_for_idma_0: ++ mr r5, r11 ++ lis r6, 0xff ++ ori r6, r6, 0xffff ++ ori r5, r5, CHANNEL0_DMA_BYTE_COUNT ++1: lwbrx r4, 0, (r5) ++ and. r4, r4, r6 ++ bne 1b ++ ++ blr ++ ++ /* this turns off channel 0 of the idma engine */ ++stop_idma_engine_0: ++ /* shut off the DMA engine */ ++ li r5, 0 ++ mr r6, r11 ++ ori r6, r6, CHANNEL0CONTROL ++ stwbrx r5, 0, (r6) ++ ++ blr ++#endif ++ ++#ifdef CFG_BOARD_ASM_INIT ++ /* NOTE: trashes r3-r7 */ ++ .globl board_asm_init ++board_asm_init: ++ /* just move the GT registers to where they belong */ ++ lis r3, CFG_DFL_GT_REGS@h ++ ori r3, r3, CFG_DFL_GT_REGS@l ++ lis r4, CFG_GT_REGS@h ++ ori r4, r4, CFG_GT_REGS@l ++ li r5, INTERNAL_SPACE_DECODE ++ ++ /* test to see if we've already moved */ ++ lwbrx r6, r5, r4 ++ andi. r6, r6, 0xffff ++ /* check loading of R7 is: 0x0F80 should: 0xf800: DONE */ ++/* rlwinm r7, r4, 8, 16, 31 ++ rlwinm r7, r4, 12, 16, 31 */ /* original */ ++ rlwinm r7, r4, 16, 16, 31 ++ /* -----------------------------------------------------*/ ++ cmp cr0, r7, r6 ++ beqlr ++ ++ /* nope, have to move the registers */ ++ lwbrx r6, r5, r3 ++ andis. r6, r6, 0xffff ++ or r6, r6, r7 ++ stwbrx r6, r5, r3 ++ ++ /* now, poll for the change */ ++1: lwbrx r7, r5, r4 ++ cmp cr0, r7, r6 ++ bne 1b ++ ++ lis r3, CFG_INT_SRAM_BASE@h ++ ori r3, r3, CFG_INT_SRAM_BASE@l ++ rlwinm r3, r3, 16, 16, 31 ++ lis r4, CFG_GT_REGS@h ++ ori r4, r4, CFG_GT_REGS@l ++ li r5, INTEGRATED_SRAM_BASE_ADDR ++ stwbrx r3, r5, r4 ++ ++2: lwbrx r6, r5, r4 ++ cmp cr0, r3, r6 ++ bne 2b ++ ++ /* done! */ ++ blr ++#endif ++ ++/* For use of the debug LEDs */ ++ .global led_on0_relocated ++led_on0_relocated: ++ xor r21, r21, r21 ++ xor r18, r18, r18 ++ lis r18, 0xFC80 ++ ori r18, r18, 0x8000 ++/* stw r21, 0x0(r18) */ ++ sync ++ blr ++ ++ .global led_off0_relocated ++led_off0_relocated: ++ xor r21, r21, r21 ++ xor r18, r18, r18 ++ lis r18, 0xFC81 ++ ori r18, r18, 0x4000 ++/* stw r21, 0x0(r18) */ ++ sync ++ blr ++ ++ .global led_on0 ++led_on0: ++ xor r18, r18, r18 ++ lis r18, 0x1c80 ++ ori r18, r18, 0x8000 ++/* stw r18, 0x0(r18) */ ++ sync ++ blr ++ ++ .global led_off0 ++led_off0: ++ xor r18, r18, r18 ++ lis r18, 0x1c81 ++ ori r18, r18, 0x4000 ++/* stw r18, 0x0(r18) */ ++ sync ++ blr ++ ++ .global led_on1 ++led_on1: ++ xor r18, r18, r18 ++ lis r18, 0x1c80 ++ ori r18, r18, 0xc000 ++/* stw r18, 0x0(r18) */ ++ sync ++ blr ++ ++ .global led_off1 ++led_off1: ++ xor r18, r18, r18 ++ lis r18, 0x1c81 ++ ori r18, r18, 0x8000 ++/* stw r18, 0x0(r18) */ ++ sync ++ blr ++ ++ .global led_on2 ++led_on2: ++ xor r18, r18, r18 ++ lis r18, 0x1c81 ++ ori r18, r18, 0x0000 ++/* stw r18, 0x0(r18) */ ++ sync ++ blr ++ ++ .global led_off2 ++led_off2: ++ xor r18, r18, r18 ++ lis r18, 0x1c81 ++ ori r18, r18, 0xc000 ++/* stw r18, 0x0(r18) */ ++ sync ++ blr +diff -Naupr u-boot-1.1.6/board/prodrive/p3mx/mpsc.c u-boot-1.1.6-fsl-1/board/prodrive/p3mx/mpsc.c +--- u-boot-1.1.6/board/prodrive/p3mx/mpsc.c 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/p3mx/mpsc.c 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,1013 @@ ++/* ++ * (C) Copyright 2001 ++ * John Clemens , Mission Critical Linux, Inc. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/************************************************************************* ++ * changes for Marvell DB64460 eval board 2003 by Ingo Assmus ++ * ++ ************************************************************************/ ++ ++/* ++ * mpsc.c - driver for console over the MPSC. ++ */ ++ ++ ++#include ++#include ++#include ++ ++#include ++#include "mpsc.h" ++ ++#include "mv_regs.h" ++ ++#include "../../Marvell/include/memory.h" ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++/* Define this if you wish to use the MPSC as a register based UART. ++ * This will force the serial port to not use the SDMA engine at all. ++ */ ++#undef CONFIG_MPSC_DEBUG_PORT ++ ++ ++int (*mpsc_putchar) (char ch) = mpsc_putchar_early; ++char (*mpsc_getchar) (void) = mpsc_getchar_debug; ++int (*mpsc_test_char) (void) = mpsc_test_char_debug; ++ ++ ++static volatile unsigned int *rx_desc_base = NULL; ++static unsigned int rx_desc_index = 0; ++static volatile unsigned int *tx_desc_base = NULL; ++static unsigned int tx_desc_index = 0; ++ ++/* local function declarations */ ++static int galmpsc_connect (int channel, int connect); ++static int galmpsc_route_rx_clock (int channel, int brg); ++static int galmpsc_route_tx_clock (int channel, int brg); ++static int galmpsc_write_config_regs (int mpsc, int mode); ++static int galmpsc_config_channel_regs (int mpsc); ++static int galmpsc_set_char_length (int mpsc, int value); ++static int galmpsc_set_stop_bit_length (int mpsc, int value); ++static int galmpsc_set_parity (int mpsc, int value); ++static int galmpsc_enter_hunt (int mpsc); ++static int galmpsc_set_brkcnt (int mpsc, int value); ++static int galmpsc_set_tcschar (int mpsc, int value); ++static int galmpsc_set_snoop (int mpsc, int value); ++static int galmpsc_shutdown (int mpsc); ++ ++static int galsdma_set_RFT (int channel); ++static int galsdma_set_SFM (int channel); ++static int galsdma_set_rxle (int channel); ++static int galsdma_set_txle (int channel); ++static int galsdma_set_burstsize (int channel, unsigned int value); ++static int galsdma_set_RC (int channel, unsigned int value); ++ ++static int galbrg_set_CDV (int channel, int value); ++static int galbrg_enable (int channel); ++static int galbrg_disable (int channel); ++static int galbrg_set_clksrc (int channel, int value); ++static int galbrg_set_CUV (int channel, int value); ++ ++static void galsdma_enable_rx (void); ++static int galsdma_set_mem_space (unsigned int memSpace, ++ unsigned int memSpaceTarget, ++ unsigned int memSpaceAttr, ++ unsigned int baseAddress, ++ unsigned int size); ++ ++ ++#define SOFTWARE_CACHE_MANAGEMENT ++ ++#ifdef SOFTWARE_CACHE_MANAGEMENT ++#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));} ++#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));} ++#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));} ++#else ++#define FLUSH_DCACHE(a,b) ++#define FLUSH_AND_INVALIDATE_DCACHE(a,b) ++#define INVALIDATE_DCACHE(a,b) ++#endif ++ ++#ifdef CONFIG_MPSC_DEBUG_PORT ++static void mpsc_debug_init (void) ++{ ++ ++ volatile unsigned int temp; ++ ++ /* Clear the CFR (CHR4) */ ++ /* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */ ++ temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP)); ++ temp &= 0xffffff00; ++ temp |= BIT29; ++ GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP), ++ temp); ++ ++ /* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */ ++ temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP)); ++ temp |= (BIT12 | BIT15); ++ GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP), ++ temp); ++ ++ /* Set int mask */ ++ temp = GTREGREAD (GALMPSC_0_INT_MASK); ++ temp |= BIT6; ++ GT_REG_WRITE (GALMPSC_0_INT_MASK, temp); ++} ++#endif ++ ++char mpsc_getchar_debug (void) ++{ ++ volatile int temp; ++ volatile unsigned int cause; ++ ++ cause = GTREGREAD (GALMPSC_0_INT_CAUSE); ++ while ((cause & BIT6) == 0) { ++ cause = GTREGREAD (GALMPSC_0_INT_CAUSE); ++ } ++ ++ temp = GTREGREAD (GALMPSC_CHANNELREG_10 + ++ (CHANNEL * GALMPSC_REG_GAP)); ++ /* By writing 1's to the set bits, the register is cleared */ ++ GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP), ++ temp); ++ GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6); ++ return (temp >> 16) & 0xff; ++} ++ ++/* special function for running out of flash. doesn't modify any ++ * global variables [josh] */ ++int mpsc_putchar_early (char ch) ++{ ++ int mpsc = CHANNEL; ++ int temp = ++ GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); ++ galmpsc_set_tcschar (mpsc, ch); ++ GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), ++ temp | 0x200); ++ ++#define MAGIC_FACTOR (10*1000000) ++ ++ udelay (MAGIC_FACTOR / gd->baudrate); ++ return 0; ++} ++ ++/* This is used after relocation, see serial.c and mpsc_init2 */ ++static int mpsc_putchar_sdma (char ch) ++{ ++ volatile unsigned int *p; ++ unsigned int temp; ++ ++ ++ /* align the descriptor */ ++ p = tx_desc_base; ++ memset ((void *) p, 0, 8 * sizeof (unsigned int)); ++ ++ /* fill one 64 bit buffer */ ++ /* word swap, pad with 0 */ ++ p[4] = 0; /* x */ ++ p[5] = (unsigned int) ch; /* x */ ++ ++ /* CHANGED completely according to GT64260A dox - NTL */ ++ p[0] = 0x00010001; /* 0 */ ++ p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* 4 */ ++ p[2] = 0; /* 8 */ ++ p[3] = (unsigned int) &p[4]; /* c */ ++ ++#if 0 ++ p[9] = DESC_FIRST | DESC_LAST; ++ p[10] = (unsigned int) &p[0]; ++ p[11] = (unsigned int) &p[12]; ++#endif ++ ++ FLUSH_DCACHE (&p[0], &p[8]); ++ ++ GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), ++ (unsigned int) &p[0]); ++ GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF), ++ (unsigned int) &p[0]); ++ ++ temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); ++ temp |= (TX_DEMAND | TX_STOP); ++ GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); ++ ++ INVALIDATE_DCACHE (&p[1], &p[2]); ++ ++ while (p[1] & DESC_OWNER_BIT) { ++ udelay (100); ++ INVALIDATE_DCACHE (&p[1], &p[2]); ++ } ++ return 0; ++} ++ ++char mpsc_getchar_sdma (void) ++{ ++ static unsigned int done = 0; ++ volatile char ch; ++ unsigned int len = 0, idx = 0, temp; ++ ++ volatile unsigned int *p; ++ ++ ++ do { ++ p = &rx_desc_base[rx_desc_index * 8]; ++ ++ INVALIDATE_DCACHE (&p[0], &p[1]); ++ /* Wait for character */ ++ while (p[1] & DESC_OWNER_BIT) { ++ udelay (100); ++ INVALIDATE_DCACHE (&p[0], &p[1]); ++ } ++ ++ /* Handle error case */ ++ if (p[1] & (1 << 15)) { ++ printf ("oops, error: %08x\n", p[1]); ++ ++ temp = GTREGREAD (GALMPSC_CHANNELREG_2 + ++ (CHANNEL * GALMPSC_REG_GAP)); ++ temp |= (1 << 23); ++ GT_REG_WRITE (GALMPSC_CHANNELREG_2 + ++ (CHANNEL * GALMPSC_REG_GAP), temp); ++ ++ /* Can't poll on abort bit, so we just wait. */ ++ udelay (100); ++ ++ galsdma_enable_rx (); ++ } ++ ++ /* Number of bytes left in this descriptor */ ++ len = p[0] & 0xffff; ++ ++ if (len) { ++ /* Where to look */ ++ idx = 5; ++ if (done > 3) ++ idx = 4; ++ if (done > 7) ++ idx = 7; ++ if (done > 11) ++ idx = 6; ++ ++ INVALIDATE_DCACHE (&p[idx], &p[idx + 1]); ++ ch = p[idx] & 0xff; ++ done++; ++ } ++ ++ if (done < len) { ++ /* this descriptor has more bytes still ++ * shift down the char we just read, and leave the ++ * buffer in place for the next time around ++ */ ++ p[idx] = p[idx] >> 8; ++ FLUSH_DCACHE (&p[idx], &p[idx + 1]); ++ } ++ ++ if (done == len) { ++ /* nothing left in this descriptor. ++ * go to next one ++ */ ++ p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; ++ p[0] = 0x00100000; ++ FLUSH_DCACHE (&p[0], &p[1]); ++ /* Next descriptor */ ++ rx_desc_index = (rx_desc_index + 1) % RX_DESC; ++ done = 0; ++ } ++ } while (len == 0); /* galileo bug.. len might be zero */ ++ ++ return ch; ++} ++ ++ ++int mpsc_test_char_debug (void) ++{ ++ if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0) ++ return 0; ++ else { ++ return 1; ++ } ++} ++ ++ ++int mpsc_test_char_sdma (void) ++{ ++ volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8]; ++ ++ INVALIDATE_DCACHE (&p[1], &p[2]); ++ ++ if (p[1] & DESC_OWNER_BIT) ++ return 0; ++ else ++ return 1; ++} ++ ++int mpsc_init (int baud) ++{ ++ /* BRG CONFIG */ ++ galbrg_set_baudrate (CHANNEL, baud); ++ galbrg_set_clksrc (CHANNEL, 8); /* set source=Tclk */ ++ galbrg_set_CUV (CHANNEL, 0); /* set up CountUpValue */ ++ galbrg_enable (CHANNEL); /* Enable BRG */ ++ ++ /* Set up clock routing */ ++ galmpsc_connect (CHANNEL, GALMPSC_CONNECT); /* connect it */ ++ ++ galmpsc_route_rx_clock (CHANNEL, CHANNEL); /* chosse BRG0 for Rx */ ++ galmpsc_route_tx_clock (CHANNEL, CHANNEL); /* chose BRG0 for Tx */ ++ ++ /* reset MPSC state */ ++ galmpsc_shutdown (CHANNEL); ++ ++ /* SDMA CONFIG */ ++ galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8); /* in 64 bit words (8 bytes) */ ++ galsdma_set_txle (CHANNEL); ++ galsdma_set_rxle (CHANNEL); ++ galsdma_set_RC (CHANNEL, 0xf); ++ galsdma_set_SFM (CHANNEL); ++ galsdma_set_RFT (CHANNEL); ++ ++ /* MPSC CONFIG */ ++ galmpsc_write_config_regs (CHANNEL, GALMPSC_UART); ++ galmpsc_config_channel_regs (CHANNEL); ++ galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */ ++ galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE); /* N */ ++ galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */ ++ ++#ifdef CONFIG_MPSC_DEBUG_PORT ++ mpsc_debug_init (); ++#endif ++ ++ /* COMM_MPSC CONFIG */ ++#ifdef SOFTWARE_CACHE_MANAGEMENT ++ galmpsc_set_snoop (CHANNEL, 0); /* disable snoop */ ++#else ++ galmpsc_set_snoop (CHANNEL, 1); /* enable snoop */ ++#endif ++ ++ return 0; ++} ++ ++ ++void mpsc_sdma_init (void) ++{ ++ /* Setup SDMA channel0 SDMA_CONFIG_REG*/ ++ GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff); ++ ++ /* Enable MPSC-Window0 for DRAM Bank 0 */ ++ if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT, ++ MV64460_SDMA_DRAM_CS_0_TARGET, ++ 0, ++ memoryGetBankBaseAddress(0), ++ memoryGetBankSize(0)) != true) ++ printf ("%s: SDMA_Window0 memory setup failed !!! \n", ++ __FUNCTION__); ++ ++ ++ /* Enable MPSC-Window1 for DRAM Bank 1 */ ++ if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_1_BIT, ++ MV64460_SDMA_DRAM_CS_1_TARGET, ++ 0, ++ memoryGetBankBaseAddress(1), ++ memoryGetBankSize(1)) != true) ++ printf ("%s: SDMA_Window1 memory setup failed !!! \n", ++ __FUNCTION__); ++ ++ ++ /* Disable MPSC-Window2 */ ++ if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_2_BIT, ++ MV64460_SDMA_DRAM_CS_2_TARGET, ++ 0, ++ memoryGetBankBaseAddress(2), ++ memoryGetBankSize(2)) != true) ++ printf ("%s: SDMA_Window2 memory setup failed !!! \n", ++ __FUNCTION__); ++ ++ ++ /* Disable MPSC-Window3 */ ++ if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_3_BIT, ++ MV64460_SDMA_DRAM_CS_3_TARGET, ++ 0, ++ memoryGetBankBaseAddress(3), ++ memoryGetBankSize(3)) != true) ++ printf ("%s: SDMA_Window3 memory setup failed !!! \n", ++ __FUNCTION__); ++ ++ /* Setup MPSC0 access mode Window0 full access */ ++ GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG, ++ (MV64460_SDMA_WIN_ACCESS_FULL << ++ (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); ++ ++ /* Setup MPSC1 access mode Window1 full access */ ++ GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG, ++ (MV64460_SDMA_WIN_ACCESS_FULL << ++ (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); ++ ++ /* Setup MPSC internal address space base address */ ++ GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS); ++ ++ /* no high address remap*/ ++ GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); ++ GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00); ++ ++ /* clear interrupt cause register for MPSC (fault register)*/ ++ GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00); ++} ++ ++ ++void mpsc_init2 (void) ++{ ++ int i; ++ ++#ifndef CONFIG_MPSC_DEBUG_PORT ++ mpsc_putchar = mpsc_putchar_sdma; ++ mpsc_getchar = mpsc_getchar_sdma; ++ mpsc_test_char = mpsc_test_char_sdma; ++#endif ++ /* RX descriptors */ ++ rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) * ++ sizeof (unsigned int)); ++ ++ /* align descriptors */ ++ rx_desc_base = (unsigned int *) ++ (((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0); ++ ++ rx_desc_index = 0; ++ ++ memset ((void *) rx_desc_base, 0, ++ (RX_DESC * 8) * sizeof (unsigned int)); ++ ++ for (i = 0; i < RX_DESC; i++) { ++ rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4]; /* Buffer */ ++ rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8]; /* Next descriptor */ ++ rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; /* Command & control */ ++ rx_desc_base[i * 8] = 0x00100000; ++ } ++ rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0]; ++ ++ FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]); ++ GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF), ++ (unsigned int) &rx_desc_base[0]); ++ ++ /* TX descriptors */ ++ tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) * ++ sizeof (unsigned int)); ++ ++ /* align descriptors */ ++ tx_desc_base = (unsigned int *) ++ (((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0); ++ ++ tx_desc_index = -1; ++ ++ memset ((void *) tx_desc_base, 0, ++ (TX_DESC * 8) * sizeof (unsigned int)); ++ ++ for (i = 0; i < TX_DESC; i++) { ++ tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323; ++ tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323; ++ tx_desc_base[i * 8 + 3] = ++ (unsigned int) &tx_desc_base[i * 8 + 4]; ++ tx_desc_base[i * 8 + 2] = ++ (unsigned int) &tx_desc_base[(i + 1) * 8]; ++ tx_desc_base[i * 8 + 1] = ++ DESC_OWNER_BIT | DESC_FIRST | DESC_LAST; ++ ++ /* set sbytecnt and shadow byte cnt to 1 */ ++ tx_desc_base[i * 8] = 0x00010001; ++ } ++ tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0]; ++ ++ FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]); ++ ++ udelay (100); ++ ++ galsdma_enable_rx (); ++ ++ return; ++} ++ ++int galbrg_set_baudrate (int channel, int rate) ++{ ++ int clock; ++ ++ galbrg_disable (channel); /*ok */ ++ ++#ifdef ZUMA_NTL ++ /* from tclk */ ++ clock = (CFG_TCLK / (16 * rate)) - 1; ++#else ++ clock = (CFG_TCLK / (16 * rate)) - 1; ++#endif ++ ++ galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ ++ ++ galbrg_enable (channel); ++ ++ gd->baudrate = rate; ++ ++ return 0; ++} ++ ++/* ------------------------------------------------------------------ */ ++ ++/* Below are all the private functions that no one else needs */ ++ ++static int galbrg_set_CDV (int channel, int value) ++{ ++ unsigned int temp; ++ ++ temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); ++ temp &= 0xFFFF0000; ++ temp |= (value & 0x0000FFFF); ++ GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); ++ ++ return 0; ++} ++ ++static int galbrg_enable (int channel) ++{ ++ unsigned int temp; ++ ++ temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); ++ temp |= 0x00010000; ++ GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); ++ ++ return 0; ++} ++ ++static int galbrg_disable (int channel) ++{ ++ unsigned int temp; ++ ++ temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); ++ temp &= 0xFFFEFFFF; ++ GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); ++ ++ return 0; ++} ++ ++static int galbrg_set_clksrc (int channel, int value) ++{ ++ unsigned int temp; ++ ++ temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); ++ temp &= 0xFFC3FFFF; /* Bit 18 - 21 (MV 64260 18-22) */ ++ temp |= (value << 18); ++ GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); ++ return 0; ++} ++ ++static int galbrg_set_CUV (int channel, int value) ++{ ++ /* set CountUpValue */ ++ GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value); ++ ++ return 0; ++} ++ ++#if 0 ++static int galbrg_reset (int channel) ++{ ++ unsigned int temp; ++ ++ temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP)); ++ temp |= 0x20000; ++ GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp); ++ ++ return 0; ++} ++#endif ++ ++static int galsdma_set_RFT (int channel) ++{ ++ unsigned int temp; ++ ++ temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); ++ temp |= 0x00000001; ++ GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), ++ temp); ++ ++ return 0; ++} ++ ++static int galsdma_set_SFM (int channel) ++{ ++ unsigned int temp; ++ ++ temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); ++ temp |= 0x00000002; ++ GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), ++ temp); ++ ++ return 0; ++} ++ ++static int galsdma_set_rxle (int channel) ++{ ++ unsigned int temp; ++ ++ temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); ++ temp |= 0x00000040; ++ GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), ++ temp); ++ ++ return 0; ++} ++ ++static int galsdma_set_txle (int channel) ++{ ++ unsigned int temp; ++ ++ temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); ++ temp |= 0x00000080; ++ GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), ++ temp); ++ ++ return 0; ++} ++ ++static int galsdma_set_RC (int channel, unsigned int value) ++{ ++ unsigned int temp; ++ ++ temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); ++ temp &= ~0x0000003c; ++ temp |= (value << 2); ++ GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF), ++ temp); ++ ++ return 0; ++} ++ ++static int galsdma_set_burstsize (int channel, unsigned int value) ++{ ++ unsigned int temp; ++ ++ temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF)); ++ temp &= 0xFFFFCFFF; ++ switch (value) { ++ case 8: ++ GT_REG_WRITE (GALSDMA_0_CONF_REG + ++ (channel * GALSDMA_REG_DIFF), ++ (temp | (0x3 << 12))); ++ break; ++ ++ case 4: ++ GT_REG_WRITE (GALSDMA_0_CONF_REG + ++ (channel * GALSDMA_REG_DIFF), ++ (temp | (0x2 << 12))); ++ break; ++ ++ case 2: ++ GT_REG_WRITE (GALSDMA_0_CONF_REG + ++ (channel * GALSDMA_REG_DIFF), ++ (temp | (0x1 << 12))); ++ break; ++ ++ case 1: ++ GT_REG_WRITE (GALSDMA_0_CONF_REG + ++ (channel * GALSDMA_REG_DIFF), ++ (temp | (0x0 << 12))); ++ break; ++ ++ default: ++ return -1; ++ break; ++ } ++ ++ return 0; ++} ++ ++static int galmpsc_connect (int channel, int connect) ++{ ++ unsigned int temp; ++ ++ temp = GTREGREAD (GALMPSC_ROUTING_REGISTER); ++ ++ if ((channel == 0) && connect) ++ temp &= ~0x00000007; ++ else if ((channel == 1) && connect) ++ temp &= ~(0x00000007 << 6); ++ else if ((channel == 0) && !connect) ++ temp |= 0x00000007; ++ else ++ temp |= (0x00000007 << 6); ++ ++ /* Just in case... */ ++ temp &= 0x3fffffff; ++ ++ GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp); ++ ++ return 0; ++} ++ ++static int galmpsc_route_rx_clock (int channel, int brg) ++{ ++ unsigned int temp; ++ ++ temp = GTREGREAD (GALMPSC_RxC_ROUTE); ++ ++ if (channel == 0) { ++ temp &= ~0x0000000F; ++ temp |= brg; ++ } else { ++ temp &= ~0x00000F00; ++ temp |= (brg << 8); ++ } ++ ++ GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp); ++ ++ return 0; ++} ++ ++static int galmpsc_route_tx_clock (int channel, int brg) ++{ ++ unsigned int temp; ++ ++ temp = GTREGREAD (GALMPSC_TxC_ROUTE); ++ ++ if (channel == 0) { ++ temp &= ~0x0000000F; ++ temp |= brg; ++ } else { ++ temp &= ~0x00000F00; ++ temp |= (brg << 8); ++ } ++ ++ GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp); ++ ++ return 0; ++} ++ ++static int galmpsc_write_config_regs (int mpsc, int mode) ++{ ++ if (mode == GALMPSC_UART) { ++ /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */ ++ GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP), ++ 0x000004c4); ++ ++ /* Main config reg High (32x Rx/Tx clock mode, width=8bits */ ++ GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP), ++ 0x024003f8); ++ /* 22 2222 1111 */ ++ /* 54 3210 9876 */ ++ /* 0000 0010 0000 0000 */ ++ /* 1 */ ++ /* 098 7654 3210 */ ++ /* 0000 0011 1111 1000 */ ++ } else ++ return -1; ++ ++ return 0; ++} ++ ++static int galmpsc_config_channel_regs (int mpsc) ++{ ++ GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0); ++ GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0); ++ GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1); ++ GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0); ++ GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0); ++ GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0); ++ GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0); ++ GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0); ++ GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0); ++ GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0); ++ ++ galmpsc_set_brkcnt (mpsc, 0x3); ++ galmpsc_set_tcschar (mpsc, 0xab); ++ ++ return 0; ++} ++ ++static int galmpsc_set_brkcnt (int mpsc, int value) ++{ ++ unsigned int temp; ++ ++ temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); ++ temp &= 0x0000FFFF; ++ temp |= (value << 16); ++ GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); ++ ++ return 0; ++} ++ ++static int galmpsc_set_tcschar (int mpsc, int value) ++{ ++ unsigned int temp; ++ ++ temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP)); ++ temp &= 0xFFFF0000; ++ temp |= value; ++ GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp); ++ ++ return 0; ++} ++ ++static int galmpsc_set_char_length (int mpsc, int value) ++{ ++ unsigned int temp; ++ ++ temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); ++ temp &= 0xFFFFCFFF; ++ temp |= (value << 12); ++ GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); ++ ++ return 0; ++} ++ ++static int galmpsc_set_stop_bit_length (int mpsc, int value) ++{ ++ unsigned int temp; ++ ++ temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP)); ++ temp &= 0xFFFFBFFF; ++ temp |= (value << 14); ++ GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp); ++ ++ return 0; ++} ++ ++static int galmpsc_set_parity (int mpsc, int value) ++{ ++ unsigned int temp; ++ ++ temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); ++ if (value != -1) { ++ temp &= 0xFFF3FFF3; ++ temp |= ((value << 18) | (value << 2)); ++ temp |= ((value << 17) | (value << 1)); ++ } else { ++ temp &= 0xFFF1FFF1; ++ } ++ ++ GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); ++ ++ return 0; ++} ++ ++static int galmpsc_enter_hunt (int mpsc) ++{ ++ int temp; ++ ++ temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); ++ temp |= 0x80000000; ++ GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); ++ ++ while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) & ++ MPSC_ENTER_HUNT) { ++ udelay (1); ++ } ++ return 0; ++} ++ ++ ++static int galmpsc_shutdown (int mpsc) ++{ ++ unsigned int temp; ++ ++ /* cause RX abort (clears RX) */ ++ temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)); ++ temp |= MPSC_RX_ABORT | MPSC_TX_ABORT; ++ temp &= ~MPSC_ENTER_HUNT; ++ GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp); ++ ++ GT_REG_WRITE (GALSDMA_0_COM_REG, 0); ++ GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT); ++ ++ /* shut down the MPSC */ ++ GT_REG_WRITE (GALMPSC_MCONF_LOW, 0); ++ GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0); ++ GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0); ++ ++ udelay (100); ++ ++ /* shut down the sdma engines. */ ++ /* reset config to default */ ++ GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc); ++ ++ udelay (100); ++ ++ /* clear the SDMA current and first TX and RX pointers */ ++ GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0); ++ GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0); ++ GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0); ++ ++ udelay (100); ++ ++ return 0; ++} ++ ++static void galsdma_enable_rx (void) ++{ ++ int temp; ++ ++ /* Enable RX processing */ ++ temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF)); ++ temp |= RX_ENABLE; ++ GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp); ++ ++ galmpsc_enter_hunt (CHANNEL); ++} ++ ++static int galmpsc_set_snoop (int mpsc, int value) ++{ ++ int reg = ++ mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : ++ MPSC_0_ADDRESS_CONTROL_LOW; ++ int temp = GTREGREAD (reg); ++ ++ if (value) ++ temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30); ++ else ++ temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30)); ++ GT_REG_WRITE (reg, temp); ++ return 0; ++} ++ ++/******************************************************************************* ++* galsdma_set_mem_space - Set MV64460 IDMA memory decoding map. ++* ++* DESCRIPTION: ++* the MV64460 SDMA has its own address decoding map that is de-coupled ++* from the CPU interface address decoding windows. The SDMA channels ++* share four address windows. Each region can be individually configured ++* by this function by associating it to a target interface and setting ++* base and size values. ++* ++* NOTE!!! ++* The size must be in 64Kbyte granularity. ++* The base address must be aligned to the size. ++* The size must be a series of 1s followed by a series of zeros ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* True for success, false otherwise. ++* ++*******************************************************************************/ ++ ++static int galsdma_set_mem_space (unsigned int memSpace, ++ unsigned int memSpaceTarget, ++ unsigned int memSpaceAttr, ++ unsigned int baseAddress, unsigned int size) ++{ ++ unsigned int temp; ++ ++ if (size == 0) { ++ GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG, ++ 1 << memSpace); ++ return true; ++ } ++ ++ /* The base address must be aligned to the size. */ ++ if (baseAddress % size != 0) { ++ return false; ++ } ++ if (size < 0x10000) { ++ return false; ++ } ++ ++ /* Align size and base to 64K */ ++ baseAddress &= 0xffff0000; ++ size &= 0xffff0000; ++ temp = size >> 16; ++ ++ /* Checking that the size is a sequence of '1' followed by a ++ sequence of '0' starting from LSB to MSB. */ ++ while ((temp > 0) && (temp & 0x1)) { ++ temp = temp >> 1; ++ } ++ ++ if (temp != 0) { ++ GT_REG_WRITE (MV64460_CUNIT_BASE_ADDR_REG0 + memSpace * 8, ++ (baseAddress | memSpaceTarget | memSpaceAttr)); ++ GT_REG_WRITE ((MV64460_CUNIT_SIZE0 + memSpace * 8), ++ (size - 1) & 0xffff0000); ++ GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG, ++ 1 << memSpace); ++ } else { ++ /* An invalid size was specified */ ++ return false; ++ } ++ return true; ++} +diff -Naupr u-boot-1.1.6/board/prodrive/p3mx/mpsc.h u-boot-1.1.6-fsl-1/board/prodrive/p3mx/mpsc.h +--- u-boot-1.1.6/board/prodrive/p3mx/mpsc.h 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/p3mx/mpsc.h 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,156 @@ ++/* ++ * (C) Copyright 2001 ++ * John Clemens , Mission Critical Linux, Inc. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/************************************************************************* ++ * changes for Marvell DB64360 eval board 2003 by Ingo Assmus ++ * ++ ************************************************************************/ ++ ++ ++/* ++ * mpsc.h - header file for MPSC in uart mode (console driver) ++ */ ++ ++#ifndef __MPSC_H__ ++#define __MPSC_H__ ++ ++/* include actual Galileo defines */ ++#include "../../Marvell/include/mv_gen_reg.h" ++ ++/* driver related defines */ ++ ++int mpsc_init(int baud); ++void mpsc_sdma_init(void); ++void mpsc_init2(void); ++int galbrg_set_baudrate(int channel, int rate); ++ ++int mpsc_putchar_early(char ch); ++char mpsc_getchar_debug(void); ++int mpsc_test_char_debug(void); ++ ++int mpsc_test_char_sdma(void); ++ ++extern int (*mpsc_putchar)(char ch); ++extern char (*mpsc_getchar)(void); ++extern int (*mpsc_test_char)(void); ++ ++#define CHANNEL CONFIG_MPSC_PORT ++ ++#define TX_DESC 5 ++#define RX_DESC 20 ++ ++#define DESC_FIRST 0x00010000 ++#define DESC_LAST 0x00020000 ++#define DESC_OWNER_BIT 0x80000000 ++ ++#define TX_DEMAND 0x00800000 ++#define TX_STOP 0x00010000 ++#define RX_ENABLE 0x00000080 ++ ++#define SDMA_RX_ABORT (1 << 15) ++#define SDMA_TX_ABORT (1 << 31) ++#define MPSC_TX_ABORT (1 << 7) ++#define MPSC_RX_ABORT (1 << 23) ++#define MPSC_ENTER_HUNT (1 << 31) ++ ++/* MPSC defines */ ++ ++#define GALMPSC_CONNECT 0x1 ++#define GALMPSC_DISCONNECT 0x0 ++ ++#define GALMPSC_UART 0x1 ++ ++#define GALMPSC_STOP_BITS_1 0x0 ++#define GALMPSC_STOP_BITS_2 0x1 ++#define GALMPSC_CHAR_LENGTH_8 0x3 ++#define GALMPSC_CHAR_LENGTH_7 0x2 ++ ++#define GALMPSC_PARITY_ODD 0x0 ++#define GALMPSC_PARITY_EVEN 0x2 ++#define GALMPSC_PARITY_MARK 0x3 ++#define GALMPSC_PARITY_SPACE 0x1 ++#define GALMPSC_PARITY_NONE -1 ++ ++#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */ ++#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */ ++#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */ ++#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */ ++#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */ ++#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */ ++#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */ ++ ++#define GALMPSC_REG_GAP 0x1000 ++ ++#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */ ++#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */ ++#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */ ++#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */ ++#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */ ++#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */ ++#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */ ++#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */ ++#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */ ++#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */ ++#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */ ++#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */ ++ ++#define GALSDMA_COMMAND_FIRST (1 << 16) ++#define GALSDMA_COMMAND_LAST (1 << 17) ++#define GALSDMA_COMMAND_ENABLEINT (1 << 23) ++#define GALSDMA_COMMAND_AUTO (1 << 30) ++#define GALSDMA_COMMAND_OWNER (1 << 31) ++ ++#define GALSDMA_RX 0 ++#define GALSDMA_TX 1 ++ ++/* CHANNEL2 should be CHANNEL1, according to documentation, ++ * but to work with the current GTREGS file... ++ */ ++#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */ ++#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */ ++#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */ ++#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */ ++#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */ ++#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */ ++#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */ ++#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */ ++#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */ ++#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */ ++#define GALSDMA_REG_DIFF 0x2000 ++ ++/* WRONG in gt64260R.h */ ++#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */ ++#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */ ++#define GALMPSC_0_INT_CAUSE 0xb804 ++#define GALMPSC_0_INT_MASK 0xb884 ++ ++#define GALSDMA_MODE_UART 0 ++#define GALSDMA_MODE_BISYNC 1 ++#define GALSDMA_MODE_HDLC 2 ++#define GALSDMA_MODE_TRANSPARENT 3 ++ ++#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */ ++#define GALBRG_REG_GAP 0x0008 ++#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */ ++ ++#endif /* __MPSC_H__ */ +diff -Naupr u-boot-1.1.6/board/prodrive/p3mx/mv_eth.c u-boot-1.1.6-fsl-1/board/prodrive/p3mx/mv_eth.c +--- u-boot-1.1.6/board/prodrive/p3mx/mv_eth.c 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/p3mx/mv_eth.c 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,3344 @@ ++/* ++ * (C) Copyright 2003 ++ * Ingo Assmus ++ * ++ * based on - Driver for MV64460X ethernet ports ++ * Copyright (C) 2002 rabeeh@galileo.co.il ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ 3 the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* ++ * mv_eth.c - header file for the polled mode GT ethernet driver ++ */ ++#include ++#include ++#include ++#include ++ ++#include "mv_eth.h" ++ ++/* enable Debug outputs */ ++ ++#undef DEBUG_MV_ETH ++ ++#ifdef DEBUG_MV_ETH ++#define DEBUG ++#define DP(x) x ++#else ++#define DP(x) ++#endif ++ ++/* PHY DFCDL Registers */ ++#define ETH_PHY_DFCDL_CONFIG0_REG 0x2100 ++#define ETH_PHY_DFCDL_CONFIG1_REG 0x2104 ++#define ETH_PHY_DFCDL_ADDR_REG 0x2110 ++#define ETH_PHY_DFCDL_DATA0_REG 0x2114 ++ ++#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */ ++#define PHY_UPDATE_TIMEOUT 10000 ++ ++#undef MV64460_CHECKSUM_OFFLOAD ++/************************************************************************* ++* The first part is the high level driver of the gigE ethernet ports. * ++*************************************************************************/ ++ ++/* Definition for configuring driver */ ++/* #define UPDATE_STATS_BY_SOFTWARE */ ++#undef MV64460_RX_QUEUE_FILL_ON_TASK ++ ++/* Constants */ ++#define MAGIC_ETH_RUNNING 8031971 ++#define MV64460_INTERNAL_SRAM_SIZE _256K ++#define EXTRA_BYTES 32 ++#define WRAP ETH_HLEN + 2 + 4 + 16 ++#define BUFFER_MTU dev->mtu + WRAP ++#define INT_CAUSE_UNMASK_ALL 0x0007ffff ++#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff ++#ifdef MV64460_RX_FILL_ON_TASK ++#define INT_CAUSE_MASK_ALL 0x00000000 ++#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL ++#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT ++#endif ++ ++/* Read/Write to/from MV64460 internal registers */ ++#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset)) ++#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data) ++#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits))) ++#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits))) ++ ++#define my_cpu_to_le32(x) my_le32_to_cpu((x)) ++ ++/* Static function declarations */ ++static int mv64460_eth_real_open (struct eth_device *eth); ++static int mv64460_eth_real_stop (struct eth_device *eth); ++static struct net_device_stats *mv64460_eth_get_stats (struct eth_device ++ *dev); ++static void eth_port_init_mac_tables (ETH_PORT eth_port_num); ++static void mv64460_eth_update_stat (struct eth_device *dev); ++bool db64460_eth_start (struct eth_device *eth); ++unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, ++ unsigned int mib_offset); ++int mv64460_eth_receive (struct eth_device *dev); ++ ++int mv64460_eth_xmit (struct eth_device *, volatile void *packet, int length); ++ ++int mv_miiphy_read(char *devname, unsigned char phy_addr, ++ unsigned char phy_reg, unsigned short *value); ++int mv_miiphy_write(char *devname, unsigned char phy_addr, ++ unsigned char phy_reg, unsigned short value); ++ ++int phy_setup_aneg (char *devname, unsigned char addr); ++ ++#ifndef UPDATE_STATS_BY_SOFTWARE ++static void mv64460_eth_print_stat (struct eth_device *dev); ++#endif ++/* Processes a received packet */ ++extern void NetReceive (volatile uchar *, int); ++ ++extern unsigned int INTERNAL_REG_BASE_ADDR; ++ ++unsigned long my_le32_to_cpu (unsigned long x) ++{ ++ return (((x & 0x000000ffU) << 24) | ++ ((x & 0x0000ff00U) << 8) | ++ ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24)); ++} ++ ++/************************************************* ++ *Helper functions - used inside the driver only * ++ *************************************************/ ++#ifdef DEBUG_MV_ETH ++void print_globals (struct eth_device *dev) ++{ ++ printf ("Ethernet PRINT_Globals-Debug function\n"); ++ printf ("Base Address for ETH_PORT_INFO: %08x\n", ++ (unsigned int) dev->priv); ++ printf ("Base Address for mv64460_eth_priv: %08x\n", ++ (unsigned int) &(((ETH_PORT_INFO *) dev->priv)-> ++ port_private)); ++ ++ printf ("GT Internal Base Address: %08x\n", ++ INTERNAL_REG_BASE_ADDR); ++ printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", ++ (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64460_TX_QUEUE_SIZE); ++ printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", ++ (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64460_RX_QUEUE_SIZE); ++ printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n", ++ (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> ++ p_rx_buffer_base[0], ++ (MV64460_RX_QUEUE_SIZE * MV64460_RX_BUFFER_SIZE) + 32); ++ printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n", ++ (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> ++ p_tx_buffer_base[0], ++ (MV64460_TX_QUEUE_SIZE * MV64460_TX_BUFFER_SIZE) + 32); ++} ++#endif ++ ++/********************************************************************** ++ * mv64460_eth_print_phy_status ++ * ++ * Prints gigabit ethenret phy status ++ * ++ * Input : pointer to ethernet interface network device structure ++ * Output : N/A ++ **********************************************************************/ ++void mv64460_eth_print_phy_status (struct eth_device *dev) ++{ ++ struct mv64460_eth_priv *port_private; ++ unsigned int port_num; ++ ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv; ++ unsigned int port_status, phy_reg_data; ++ ++ port_private = ++ (struct mv64460_eth_priv *) ethernet_private->port_private; ++ port_num = port_private->port_num; ++ ++ /* Check Link status on phy */ ++ eth_port_read_smi_reg (port_num, 1, &phy_reg_data); ++ if (!(phy_reg_data & 0x20)) { ++ printf ("Ethernet port changed link status to DOWN\n"); ++ } else { ++ port_status = ++ MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num)); ++ printf ("Ethernet status port %d: Link up", port_num); ++ printf (", %s", ++ (port_status & BIT2) ? "Full Duplex" : "Half Duplex"); ++ if (port_status & BIT4) ++ printf (", Speed 1 Gbps"); ++ else ++ printf (", %s", ++ (port_status & BIT5) ? "Speed 100 Mbps" : ++ "Speed 10 Mbps"); ++ printf ("\n"); ++ } ++} ++ ++/********************************************************************** ++ * u-boot entry functions for mv64460_eth ++ * ++ **********************************************************************/ ++int db64460_eth_probe (struct eth_device *dev) ++{ ++ return ((int) db64460_eth_start (dev)); ++} ++ ++int db64460_eth_poll (struct eth_device *dev) ++{ ++ return mv64460_eth_receive (dev); ++} ++ ++int db64460_eth_transmit (struct eth_device *dev, volatile void *packet, ++ int length) ++{ ++ mv64460_eth_xmit (dev, packet, length); ++ return 0; ++} ++ ++void db64460_eth_disable (struct eth_device *dev) ++{ ++ mv64460_eth_stop (dev); ++} ++ ++#define DFCDL(write,read) ((write << 6) | read) ++unsigned int ethDfcdls[] = { ++ DFCDL(0,0), DFCDL(1,1), DFCDL(2,2), DFCDL(3,3), ++ DFCDL(4,4), DFCDL(5,5), DFCDL(6,6), DFCDL(7,7), ++ DFCDL(8,8), DFCDL(9,9), DFCDL(10,10), DFCDL(11,11), ++ DFCDL(12,12), DFCDL(13,13), DFCDL(14,14), DFCDL(15,15), ++ DFCDL(16,16), DFCDL(17,17), DFCDL(18,18), DFCDL(19,19), ++ DFCDL(20,20), DFCDL(21,21), DFCDL(22,22), DFCDL(23,23), ++ DFCDL(24,24), DFCDL(25,25), DFCDL(26,26), DFCDL(27,27), ++ DFCDL(28,28), DFCDL(29,29), DFCDL(30,30), DFCDL(31,31), ++ DFCDL(32,32), DFCDL(33,33), DFCDL(34,34), DFCDL(35,35), ++ DFCDL(36,36), DFCDL(37,37), DFCDL(38,38), DFCDL(39,39), ++ DFCDL(40,40), DFCDL(41,41), DFCDL(42,42), DFCDL(43,43), ++ DFCDL(44,44), DFCDL(45,45), DFCDL(46,46), DFCDL(47,47), ++ DFCDL(48,48), DFCDL(49,49), DFCDL(50,50), DFCDL(51,51), ++ DFCDL(52,52), DFCDL(53,53), DFCDL(54,54), DFCDL(55,55), ++ DFCDL(56,56), DFCDL(57,57), DFCDL(58,58), DFCDL(59,59), ++ DFCDL(60,60), DFCDL(61,61), DFCDL(62,62), DFCDL(63,63), ++}; ++ ++void mv_eth_phy_init (void) ++{ ++ int i; ++ ++ MV_REG_WRITE (ETH_PHY_DFCDL_ADDR_REG, 0); ++ ++ for (i = 0; i < 64; i++) { ++ MV_REG_WRITE (ETH_PHY_DFCDL_DATA0_REG, ethDfcdls[i]); ++ } ++ ++ MV_REG_WRITE (ETH_PHY_DFCDL_CONFIG0_REG, 0x300000); ++} ++ ++void mv6446x_eth_initialize (bd_t * bis) ++{ ++ struct eth_device *dev; ++ ETH_PORT_INFO *ethernet_private; ++ struct mv64460_eth_priv *port_private; ++ int devnum, x, temp; ++ char *s, *e, buf[64]; ++ ++ /* P3M750 only ++ * Set RGMII clock drives strength ++ */ ++ temp = MV_REG_READ(0x20A0); ++ temp |= 0x04000080; ++ MV_REG_WRITE(0x20A0, temp); ++ ++ mv_eth_phy_init(); ++ ++ for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) { ++ dev = calloc (sizeof (*dev), 1); ++ if (!dev) { ++ printf ("%s: mv_enet%d allocation failure, %s\n", ++ __FUNCTION__, devnum, "eth_device structure"); ++ return; ++ } ++ ++ /* must be less than NAMESIZE (16) */ ++ sprintf (dev->name, "mv_enet%d", devnum); ++ ++#ifdef DEBUG ++ printf ("Initializing %s\n", dev->name); ++#endif ++ ++ /* Extract the MAC address from the environment */ ++ switch (devnum) { ++ case 0: ++ s = "ethaddr"; ++ break; ++ case 1: ++ s = "eth1addr"; ++ break; ++ case 2: ++ s = "eth2addr"; ++ break; ++ default: /* this should never happen */ ++ printf ("%s: Invalid device number %d\n", ++ __FUNCTION__, devnum); ++ return; ++ } ++ ++ temp = getenv_r (s, buf, sizeof (buf)); ++ s = (temp > 0) ? buf : NULL; ++ ++#ifdef DEBUG ++ printf ("Setting MAC %d to %s\n", devnum, s); ++#endif ++ for (x = 0; x < 6; ++x) { ++ dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; ++ if (s) ++ s = (*e) ? e + 1 : e; ++ } ++ /* ronen - set the MAC addr in the HW */ ++ eth_port_uc_addr_set (devnum, dev->enetaddr, 0); ++ ++ dev->init = (void *) db64460_eth_probe; ++ dev->halt = (void *) ethernet_phy_reset; ++ dev->send = (void *) db64460_eth_transmit; ++ dev->recv = (void *) db64460_eth_poll; ++ ++ ethernet_private = calloc (sizeof (*ethernet_private), 1); ++ dev->priv = (void *)ethernet_private; ++ if (!ethernet_private) { ++ printf ("%s: %s allocation failure, %s\n", ++ __FUNCTION__, dev->name, ++ "Private Device Structure"); ++ free (dev); ++ return; ++ } ++ /* start with an zeroed ETH_PORT_INFO */ ++ memset (ethernet_private, 0, sizeof (ETH_PORT_INFO)); ++ memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); ++ ++ /* set pointer to memory for stats data structure etc... */ ++ port_private = calloc (sizeof (*ethernet_private), 1); ++ ethernet_private->port_private = (void *)port_private; ++ if (!port_private) { ++ printf ("%s: %s allocation failure, %s\n", ++ __FUNCTION__, dev->name, ++ "Port Private Device Structure"); ++ ++ free (ethernet_private); ++ free (dev); ++ return; ++ } ++ ++ port_private->stats = ++ calloc (sizeof (struct net_device_stats), 1); ++ if (!port_private->stats) { ++ printf ("%s: %s allocation failure, %s\n", ++ __FUNCTION__, dev->name, ++ "Net stat Structure"); ++ ++ free (port_private); ++ free (ethernet_private); ++ free (dev); ++ return; ++ } ++ memset (ethernet_private->port_private, 0, ++ sizeof (struct mv64460_eth_priv)); ++ switch (devnum) { ++ case 0: ++ ethernet_private->port_num = ETH_0; ++ break; ++ case 1: ++ ethernet_private->port_num = ETH_1; ++ break; ++ case 2: ++ ethernet_private->port_num = ETH_2; ++ break; ++ default: ++ printf ("Invalid device number %d\n", devnum); ++ break; ++ }; ++ ++ port_private->port_num = devnum; ++ /* ++ * Read MIB counter on the GT in order to reset them, ++ * then zero all the stats fields in memory ++ */ ++ mv64460_eth_update_stat (dev); ++ memset (port_private->stats, 0, ++ sizeof (struct net_device_stats)); ++ /* Extract the MAC address from the environment */ ++ switch (devnum) { ++ case 0: ++ s = "ethaddr"; ++ break; ++ case 1: ++ s = "eth1addr"; ++ break; ++ case 2: ++ s = "eth2addr"; ++ break; ++ default: /* this should never happen */ ++ printf ("%s: Invalid device number %d\n", ++ __FUNCTION__, devnum); ++ return; ++ } ++ ++ temp = getenv_r (s, buf, sizeof (buf)); ++ s = (temp > 0) ? buf : NULL; ++ ++#ifdef DEBUG ++ printf ("Setting MAC %d to %s\n", devnum, s); ++#endif ++ for (x = 0; x < 6; ++x) { ++ dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; ++ if (s) ++ s = (*e) ? e + 1 : e; ++ } ++ ++ DP (printf ("Allocating descriptor and buffer rings\n")); ++ ++ ethernet_private->p_rx_desc_area_base[0] = ++ (ETH_RX_DESC *) memalign (16, ++ RX_DESC_ALIGNED_SIZE * ++ MV64460_RX_QUEUE_SIZE + 1); ++ ethernet_private->p_tx_desc_area_base[0] = ++ (ETH_TX_DESC *) memalign (16, ++ TX_DESC_ALIGNED_SIZE * ++ MV64460_TX_QUEUE_SIZE + 1); ++ ++ ethernet_private->p_rx_buffer_base[0] = ++ (char *) memalign (16, ++ MV64460_RX_QUEUE_SIZE * ++ MV64460_TX_BUFFER_SIZE + 1); ++ ethernet_private->p_tx_buffer_base[0] = ++ (char *) memalign (16, ++ MV64460_RX_QUEUE_SIZE * ++ MV64460_TX_BUFFER_SIZE + 1); ++ ++#ifdef DEBUG_MV_ETH ++ /* DEBUG OUTPUT prints adresses of globals */ ++ print_globals (dev); ++#endif ++ eth_register (dev); ++ ++ miiphy_register(dev->name, mv_miiphy_read, mv_miiphy_write); ++ } ++ DP (printf ("%s: exit\n", __FUNCTION__)); ++ ++} ++ ++/********************************************************************** ++ * mv64460_eth_open ++ * ++ * This function is called when openning the network device. The function ++ * should initialize all the hardware, initialize cyclic Rx/Tx ++ * descriptors chain and buffers and allocate an IRQ to the network ++ * device. ++ * ++ * Input : a pointer to the network device structure ++ * / / ronen - changed the output to match net/eth.c needs ++ * Output : nonzero of success , zero if fails. ++ * under construction ++ **********************************************************************/ ++ ++int mv64460_eth_open (struct eth_device *dev) ++{ ++ return (mv64460_eth_real_open (dev)); ++} ++ ++/* Helper function for mv64460_eth_open */ ++static int mv64460_eth_real_open (struct eth_device *dev) ++{ ++ ++ unsigned int queue; ++ ETH_PORT_INFO *ethernet_private; ++ struct mv64460_eth_priv *port_private; ++ unsigned int port_num; ++ u32 port_status; ++ ushort reg_short; ++ int speed; ++ int duplex; ++ int i; ++ int reg; ++ ++ ethernet_private = (ETH_PORT_INFO *) dev->priv; ++ /* ronen - when we update the MAC env params we only update dev->enetaddr ++ see ./net/eth.c eth_set_enetaddr() */ ++ memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); ++ ++ port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; ++ port_num = port_private->port_num; ++ ++ /* Stop RX Queues */ ++ MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), 0x0000ff00); ++ ++ /* Clear the ethernet port interrupts */ ++ MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0); ++ MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); ++ ++ /* Unmask RX buffer and TX end interrupt */ ++ MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), ++ INT_CAUSE_UNMASK_ALL); ++ ++ /* Unmask phy and link status changes interrupts */ ++ MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), ++ INT_CAUSE_UNMASK_ALL_EXT); ++ ++ /* Set phy address of the port */ ++ ethernet_private->port_phy_addr = 0x1 + (port_num << 1); ++ reg = ethernet_private->port_phy_addr; ++ ++ /* Activate the DMA channels etc */ ++ eth_port_init (ethernet_private); ++ ++ /* "Allocate" setup TX rings */ ++ ++ for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) { ++ unsigned int size; ++ ++ port_private->tx_ring_size[queue] = MV64460_TX_QUEUE_SIZE; ++ size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */ ++ ethernet_private->tx_desc_area_size[queue] = size; ++ ++ /* first clear desc area completely */ ++ memset ((void *) ethernet_private->p_tx_desc_area_base[queue], ++ 0, ethernet_private->tx_desc_area_size[queue]); ++ ++ /* initialize tx desc ring with low level driver */ ++ if (ether_init_tx_desc_ring ++ (ethernet_private, ETH_Q0, ++ port_private->tx_ring_size[queue], ++ MV64460_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , ++ (unsigned int) ethernet_private-> ++ p_tx_desc_area_base[queue], ++ (unsigned int) ethernet_private-> ++ p_tx_buffer_base[queue]) == false) ++ printf ("### Error initializing TX Ring\n"); ++ } ++ ++ /* "Allocate" setup RX rings */ ++ for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) { ++ unsigned int size; ++ ++ /* Meantime RX Ring are fixed - but must be configurable by user */ ++ port_private->rx_ring_size[queue] = MV64460_RX_QUEUE_SIZE; ++ size = (port_private->rx_ring_size[queue] * ++ RX_DESC_ALIGNED_SIZE); ++ ethernet_private->rx_desc_area_size[queue] = size; ++ ++ /* first clear desc area completely */ ++ memset ((void *) ethernet_private->p_rx_desc_area_base[queue], ++ 0, ethernet_private->rx_desc_area_size[queue]); ++ if ((ether_init_rx_desc_ring ++ (ethernet_private, ETH_Q0, ++ port_private->rx_ring_size[queue], ++ MV64460_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , ++ (unsigned int) ethernet_private-> ++ p_rx_desc_area_base[queue], ++ (unsigned int) ethernet_private-> ++ p_rx_buffer_base[queue])) == false) ++ printf ("### Error initializing RX Ring\n"); ++ } ++ ++ eth_port_start (ethernet_private); ++ ++ /* Set maximum receive buffer to 9700 bytes */ ++ MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num), ++ (0x5 << 17) | ++ (MV_REG_READ ++ (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num)) ++ & 0xfff1ffff)); ++ ++ /* ++ * Set ethernet MTU for leaky bucket mechanism to 0 - this will ++ * disable the leaky bucket mechanism . ++ */ ++ ++ MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); ++ port_status = MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num)); ++ ++#if defined(CONFIG_PHY_RESET) ++ /* ++ * Reset the phy, only if its the first time through ++ * otherwise, just check the speeds & feeds ++ */ ++ if (port_private->first_init == 0) { ++ port_private->first_init = 1; ++ ethernet_phy_reset (port_num); ++ ++ /* Start/Restart autonegotiation */ ++ phy_setup_aneg (dev->name, reg); ++ udelay (1000); ++ } ++#endif /* defined(CONFIG_PHY_RESET) */ ++ ++ miiphy_read (dev->name, reg, PHY_BMSR, ®_short); ++ ++ /* ++ * Wait if PHY is capable of autonegotiation and autonegotiation is not complete ++ */ ++ if ((reg_short & PHY_BMSR_AUTN_ABLE) ++ && !(reg_short & PHY_BMSR_AUTN_COMP)) { ++ puts ("Waiting for PHY auto negotiation to complete"); ++ i = 0; ++ while (!(reg_short & PHY_BMSR_AUTN_COMP)) { ++ /* ++ * Timeout reached ? ++ */ ++ if (i > PHY_AUTONEGOTIATE_TIMEOUT) { ++ puts (" TIMEOUT !\n"); ++ break; ++ } ++ ++ if ((i++ % 1000) == 0) { ++ putc ('.'); ++ } ++ udelay (1000); /* 1 ms */ ++ miiphy_read (dev->name, reg, PHY_BMSR, ®_short); ++ ++ } ++ puts (" done\n"); ++ udelay (500000); /* another 500 ms (results in faster booting) */ ++ } ++ ++ speed = miiphy_speed (dev->name, reg); ++ duplex = miiphy_duplex (dev->name, reg); ++ ++ printf ("ENET Speed is %d Mbps - %s duplex connection\n", ++ (int) speed, (duplex == HALF) ? "HALF" : "FULL"); ++ ++ port_private->eth_running = MAGIC_ETH_RUNNING; ++ return 1; ++} ++ ++static int mv64460_eth_free_tx_rings (struct eth_device *dev) ++{ ++ unsigned int queue; ++ ETH_PORT_INFO *ethernet_private; ++ struct mv64460_eth_priv *port_private; ++ unsigned int port_num; ++ volatile ETH_TX_DESC *p_tx_curr_desc; ++ ++ ethernet_private = (ETH_PORT_INFO *) dev->priv; ++ port_private = ++ (struct mv64460_eth_priv *) ethernet_private->port_private; ++ port_num = port_private->port_num; ++ ++ /* Stop Tx Queues */ ++ MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num), ++ 0x0000ff00); ++ ++ /* Free TX rings */ ++ DP (printf ("Clearing previously allocated TX queues... ")); ++ for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) { ++ /* Free on TX rings */ ++ for (p_tx_curr_desc = ++ ethernet_private->p_tx_desc_area_base[queue]; ++ ((unsigned int) p_tx_curr_desc <= (unsigned int) ++ ethernet_private->p_tx_desc_area_base[queue] + ++ ethernet_private->tx_desc_area_size[queue]); ++ p_tx_curr_desc = ++ (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc + ++ TX_DESC_ALIGNED_SIZE)) { ++ /* this is inside for loop */ ++ if (p_tx_curr_desc->return_info != 0) { ++ p_tx_curr_desc->return_info = 0; ++ DP (printf ("freed\n")); ++ } ++ } ++ DP (printf ("Done\n")); ++ } ++ return 0; ++} ++ ++static int mv64460_eth_free_rx_rings (struct eth_device *dev) ++{ ++ unsigned int queue; ++ ETH_PORT_INFO *ethernet_private; ++ struct mv64460_eth_priv *port_private; ++ unsigned int port_num; ++ volatile ETH_RX_DESC *p_rx_curr_desc; ++ ++ ethernet_private = (ETH_PORT_INFO *) dev->priv; ++ port_private = ++ (struct mv64460_eth_priv *) ethernet_private->port_private; ++ port_num = port_private->port_num; ++ ++ /* Stop RX Queues */ ++ MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), ++ 0x0000ff00); ++ ++ /* Free RX rings */ ++ DP (printf ("Clearing previously allocated RX queues... ")); ++ for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) { ++ /* Free preallocated skb's on RX rings */ ++ for (p_rx_curr_desc = ++ ethernet_private->p_rx_desc_area_base[queue]; ++ (((unsigned int) p_rx_curr_desc < ++ ((unsigned int) ethernet_private-> ++ p_rx_desc_area_base[queue] + ++ ethernet_private->rx_desc_area_size[queue]))); ++ p_rx_curr_desc = ++ (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc + ++ RX_DESC_ALIGNED_SIZE)) { ++ if (p_rx_curr_desc->return_info != 0) { ++ p_rx_curr_desc->return_info = 0; ++ DP (printf ("freed\n")); ++ } ++ } ++ DP (printf ("Done\n")); ++ } ++ return 0; ++} ++ ++/********************************************************************** ++ * mv64460_eth_stop ++ * ++ * This function is used when closing the network device. ++ * It updates the hardware, ++ * release all memory that holds buffers and descriptors and release the IRQ. ++ * Input : a pointer to the device structure ++ * Output : zero if success , nonzero if fails ++ *********************************************************************/ ++ ++int mv64460_eth_stop (struct eth_device *dev) ++{ ++ ETH_PORT_INFO *ethernet_private; ++ struct mv64460_eth_priv *port_private; ++ unsigned int port_num; ++ ++ ethernet_private = (ETH_PORT_INFO *) dev->priv; ++ port_private = ++ (struct mv64460_eth_priv *) ethernet_private->port_private; ++ port_num = port_private->port_num; ++ ++ /* Disable all gigE address decoder */ ++ MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f); ++ DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); ++ mv64460_eth_real_stop (dev); ++ ++ return 0; ++}; ++ ++/* Helper function for mv64460_eth_stop */ ++ ++static int mv64460_eth_real_stop (struct eth_device *dev) ++{ ++ ETH_PORT_INFO *ethernet_private; ++ struct mv64460_eth_priv *port_private; ++ unsigned int port_num; ++ ++ ethernet_private = (ETH_PORT_INFO *) dev->priv; ++ port_private = ++ (struct mv64460_eth_priv *) ethernet_private->port_private; ++ port_num = port_private->port_num; ++ ++ mv64460_eth_free_tx_rings (dev); ++ mv64460_eth_free_rx_rings (dev); ++ ++ eth_port_reset (ethernet_private->port_num); ++ /* Disable ethernet port interrupts */ ++ MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0); ++ MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); ++ /* Mask RX buffer and TX end interrupt */ ++ MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), 0); ++ /* Mask phy and link status changes interrupts */ ++ MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0); ++ MV_RESET_REG_BITS (MV64460_CPU_INTERRUPT0_MASK_HIGH, ++ BIT0 << port_num); ++ /* Print Network statistics */ ++#ifndef UPDATE_STATS_BY_SOFTWARE ++ /* ++ * Print statistics (only if ethernet is running), ++ * then zero all the stats fields in memory ++ */ ++ if (port_private->eth_running == MAGIC_ETH_RUNNING) { ++ port_private->eth_running = 0; ++ mv64460_eth_print_stat (dev); ++ } ++ memset (port_private->stats, 0, sizeof (struct net_device_stats)); ++#endif ++ DP (printf ("\nEthernet stopped ... \n")); ++ return 0; ++} ++ ++/********************************************************************** ++ * mv64460_eth_start_xmit ++ * ++ * This function is queues a packet in the Tx descriptor for ++ * required port. ++ * ++ * Input : skb - a pointer to socket buffer ++ * dev - a pointer to the required port ++ * ++ * Output : zero upon success ++ **********************************************************************/ ++ ++int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr, ++ int dataSize) ++{ ++ ETH_PORT_INFO *ethernet_private; ++ struct mv64460_eth_priv *port_private; ++ unsigned int port_num; ++ PKT_INFO pkt_info; ++ ETH_FUNC_RET_STATUS status; ++ struct net_device_stats *stats; ++ ETH_FUNC_RET_STATUS release_result; ++ ++ ethernet_private = (ETH_PORT_INFO *) dev->priv; ++ port_private = ++ (struct mv64460_eth_priv *) ethernet_private->port_private; ++ port_num = port_private->port_num; ++ ++ stats = port_private->stats; ++ ++ /* Update packet info data structure */ ++ pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */ ++ pkt_info.byte_cnt = dataSize; ++ pkt_info.buf_ptr = (unsigned int) dataPtr; ++ pkt_info.return_info = 0; ++ ++ status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info); ++ if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) { ++ printf ("Error on transmitting packet .."); ++ if (status == ETH_QUEUE_FULL) ++ printf ("ETH Queue is full. \n"); ++ if (status == ETH_QUEUE_LAST_RESOURCE) ++ printf ("ETH Queue: using last available resource. \n"); ++ return 1; ++ } ++ ++ /* Update statistics and start of transmittion time */ ++ stats->tx_bytes += dataSize; ++ stats->tx_packets++; ++ ++ /* Check if packet(s) is(are) transmitted correctly (release everything) */ ++ do { ++ release_result = ++ eth_tx_return_desc (ethernet_private, ETH_Q0, ++ &pkt_info); ++ switch (release_result) { ++ case ETH_OK: ++ DP (printf ("descriptor released\n")); ++ if (pkt_info.cmd_sts & BIT0) { ++ printf ("Error in TX\n"); ++ stats->tx_errors++; ++ } ++ break; ++ case ETH_RETRY: ++ DP (printf ("transmission still in process\n")); ++ break; ++ ++ case ETH_ERROR: ++ printf ("routine can not access Tx desc ring\n"); ++ break; ++ ++ case ETH_END_OF_JOB: ++ DP (printf ("the routine has nothing to release\n")); ++ break; ++ default: /* should not happen */ ++ break; ++ } ++ } while (release_result == ETH_OK); ++ ++ return 0; /* success */ ++} ++ ++/********************************************************************** ++ * mv64460_eth_receive ++ * ++ * This function is forward packets that are received from the port's ++ * queues toward kernel core or FastRoute them to another interface. ++ * ++ * Input : dev - a pointer to the required interface ++ * max - maximum number to receive (0 means unlimted) ++ * ++ * Output : number of served packets ++ **********************************************************************/ ++ ++int mv64460_eth_receive (struct eth_device *dev) ++{ ++ ETH_PORT_INFO *ethernet_private; ++ struct mv64460_eth_priv *port_private; ++ unsigned int port_num; ++ PKT_INFO pkt_info; ++ struct net_device_stats *stats; ++ ++ ethernet_private = (ETH_PORT_INFO *) dev->priv; ++ port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; ++ port_num = port_private->port_num; ++ stats = port_private->stats; ++ ++ while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == ETH_OK)) { ++#ifdef DEBUG_MV_ETH ++ if (pkt_info.byte_cnt != 0) { ++ printf ("%s: Received %d byte Packet @ 0x%x\n", ++ __FUNCTION__, pkt_info.byte_cnt, ++ pkt_info.buf_ptr); ++ if(pkt_info.buf_ptr != 0){ ++ for(i=0; i < pkt_info.byte_cnt; i++){ ++ if((i % 4) == 0){ ++ printf("\n0x"); ++ } ++ printf("%02x", ((char*)pkt_info.buf_ptr)[i]); ++ } ++ printf("\n"); ++ } ++ } ++#endif ++ /* Update statistics. Note byte count includes 4 byte CRC count */ ++ stats->rx_packets++; ++ stats->rx_bytes += pkt_info.byte_cnt; ++ ++ /* ++ * In case received a packet without first / last bits on OR the error ++ * summary bit is on, the packets needs to be dropeed. ++ */ ++ if (((pkt_info. ++ cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != ++ (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) ++ || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { ++ stats->rx_dropped++; ++ ++ printf ("Received packet spread on multiple descriptors\n"); ++ ++ /* Is this caused by an error ? */ ++ if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) { ++ stats->rx_errors++; ++ } ++ ++ /* free these descriptors again without forwarding them to the higher layers */ ++ pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ ++ pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ ++ ++ if (eth_rx_return_buff ++ (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { ++ printf ("Error while returning the RX Desc to Ring\n"); ++ } else { ++ DP (printf ("RX Desc returned to Ring\n")); ++ } ++ /* /free these descriptors again */ ++ } else { ++ ++/* !!! call higher layer processing */ ++#ifdef DEBUG_MV_ETH ++ printf ("\nNow send it to upper layer protocols (NetReceive) ...\n"); ++#endif ++ /* let the upper layer handle the packet */ ++ NetReceive ((uchar *) pkt_info.buf_ptr, ++ (int) pkt_info.byte_cnt); ++ ++/* **************************************************************** */ ++/* free descriptor */ ++ pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ ++ pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ ++ DP (printf ("RX: pkt_info.buf_ptr = %x\n", pkt_info.buf_ptr)); ++ if (eth_rx_return_buff ++ (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { ++ printf ("Error while returning the RX Desc to Ring\n"); ++ } else { ++ DP (printf ("RX: Desc returned to Ring\n")); ++ } ++ ++/* **************************************************************** */ ++ ++ } ++ } ++ mv64460_eth_get_stats (dev); /* update statistics */ ++ return 1; ++} ++ ++/********************************************************************** ++ * mv64460_eth_get_stats ++ * ++ * Returns a pointer to the interface statistics. ++ * ++ * Input : dev - a pointer to the required interface ++ * ++ * Output : a pointer to the interface's statistics ++ **********************************************************************/ ++ ++static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev) ++{ ++ ETH_PORT_INFO *ethernet_private; ++ struct mv64460_eth_priv *port_private; ++ unsigned int port_num; ++ ++ ethernet_private = (ETH_PORT_INFO *) dev->priv; ++ port_private = ++ (struct mv64460_eth_priv *) ethernet_private->port_private; ++ port_num = port_private->port_num; ++ ++ mv64460_eth_update_stat (dev); ++ ++ return port_private->stats; ++} ++ ++/********************************************************************** ++ * mv64460_eth_update_stat ++ * ++ * Update the statistics structure in the private data structure ++ * ++ * Input : pointer to ethernet interface network device structure ++ * Output : N/A ++ **********************************************************************/ ++ ++static void mv64460_eth_update_stat (struct eth_device *dev) ++{ ++ ETH_PORT_INFO *ethernet_private; ++ struct mv64460_eth_priv *port_private; ++ struct net_device_stats *stats; ++ unsigned int port_num; ++ volatile unsigned int dummy; ++ ++ ethernet_private = (ETH_PORT_INFO *) dev->priv; ++ port_private = ++ (struct mv64460_eth_priv *) ethernet_private->port_private; ++ port_num = port_private->port_num; ++ stats = port_private->stats; ++ ++ /* These are false updates */ ++ stats->rx_packets += (unsigned long) ++ eth_read_mib_counter (ethernet_private->port_num, ++ ETH_MIB_GOOD_FRAMES_RECEIVED); ++ stats->tx_packets += (unsigned long) ++ eth_read_mib_counter (ethernet_private->port_num, ++ ETH_MIB_GOOD_FRAMES_SENT); ++ stats->rx_bytes += (unsigned long) ++ eth_read_mib_counter (ethernet_private->port_num, ++ ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); ++ /* ++ * Ideally this should be as follows - ++ * ++ * stats->rx_bytes += stats->rx_bytes + ++ * ((unsigned long) ethReadMibCounter (ethernet_private->port_num , ++ * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32); ++ * ++ * But the unsigned long in PowerPC and MIPS are 32bit. So the next read ++ * is just a dummy read for proper work of the GigE port ++ */ ++ dummy = eth_read_mib_counter (ethernet_private->port_num, ++ ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); ++ stats->tx_bytes += (unsigned long) ++ eth_read_mib_counter (ethernet_private->port_num, ++ ETH_MIB_GOOD_OCTETS_SENT_LOW); ++ dummy = eth_read_mib_counter (ethernet_private->port_num, ++ ETH_MIB_GOOD_OCTETS_SENT_HIGH); ++ stats->rx_errors += (unsigned long) ++ eth_read_mib_counter (ethernet_private->port_num, ++ ETH_MIB_MAC_RECEIVE_ERROR); ++ ++ /* Rx dropped is for received packet with CRC error */ ++ stats->rx_dropped += ++ (unsigned long) eth_read_mib_counter (ethernet_private-> ++ port_num, ++ ETH_MIB_BAD_CRC_EVENT); ++ stats->multicast += (unsigned long) ++ eth_read_mib_counter (ethernet_private->port_num, ++ ETH_MIB_MULTICAST_FRAMES_RECEIVED); ++ stats->collisions += ++ (unsigned long) eth_read_mib_counter (ethernet_private-> ++ port_num, ++ ETH_MIB_COLLISION) + ++ (unsigned long) eth_read_mib_counter (ethernet_private-> ++ port_num, ++ ETH_MIB_LATE_COLLISION); ++ /* detailed rx errors */ ++ stats->rx_length_errors += ++ (unsigned long) eth_read_mib_counter (ethernet_private-> ++ port_num, ++ ETH_MIB_UNDERSIZE_RECEIVED) ++ + ++ (unsigned long) eth_read_mib_counter (ethernet_private-> ++ port_num, ++ ETH_MIB_OVERSIZE_RECEIVED); ++ /* detailed tx errors */ ++} ++ ++#ifndef UPDATE_STATS_BY_SOFTWARE ++/********************************************************************** ++ * mv64460_eth_print_stat ++ * ++ * Update the statistics structure in the private data structure ++ * ++ * Input : pointer to ethernet interface network device structure ++ * Output : N/A ++ **********************************************************************/ ++ ++static void mv64460_eth_print_stat (struct eth_device *dev) ++{ ++ ETH_PORT_INFO *ethernet_private; ++ struct mv64460_eth_priv *port_private; ++ struct net_device_stats *stats; ++ unsigned int port_num; ++ ++ ethernet_private = (ETH_PORT_INFO *) dev->priv; ++ port_private = ++ (struct mv64460_eth_priv *) ethernet_private->port_private; ++ port_num = port_private->port_num; ++ stats = port_private->stats; ++ ++ /* These are false updates */ ++ printf ("\n### Network statistics: ###\n"); ++ printf ("--------------------------\n"); ++ printf (" Packets received: %ld\n", stats->rx_packets); ++ printf (" Packets send: %ld\n", stats->tx_packets); ++ printf (" Received bytes: %ld\n", stats->rx_bytes); ++ printf (" Send bytes: %ld\n", stats->tx_bytes); ++ if (stats->rx_errors != 0) ++ printf (" Rx Errors: %ld\n", ++ stats->rx_errors); ++ if (stats->rx_dropped != 0) ++ printf (" Rx dropped (CRC Errors): %ld\n", ++ stats->rx_dropped); ++ if (stats->multicast != 0) ++ printf (" Rx mulicast frames: %ld\n", ++ stats->multicast); ++ if (stats->collisions != 0) ++ printf (" No. of collisions: %ld\n", ++ stats->collisions); ++ if (stats->rx_length_errors != 0) ++ printf (" Rx length errors: %ld\n", ++ stats->rx_length_errors); ++} ++#endif ++ ++/************************************************************************** ++ *network_start - Network Kick Off Routine UBoot ++ *Inputs : ++ *Outputs : ++ **************************************************************************/ ++ ++bool db64460_eth_start (struct eth_device *dev) ++{ ++ return (mv64460_eth_open (dev)); /* calls real open */ ++} ++ ++/************************************************************************* ++************************************************************************** ++************************************************************************** ++* The second part is the low level driver of the gigE ethernet ports. * ++************************************************************************** ++************************************************************************** ++*************************************************************************/ ++/* ++ * based on Linux code ++ * arch/ppc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports ++ * Copyright (C) 2002 rabeeh@galileo.co.il ++ ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ * ++ */ ++ ++/******************************************************************************** ++ * Marvell's Gigabit Ethernet controller low level driver ++ * ++ * DESCRIPTION: ++ * This file introduce low level API to Marvell's Gigabit Ethernet ++ * controller. This Gigabit Ethernet Controller driver API controls ++ * 1) Operations (i.e. port init, start, reset etc'). ++ * 2) Data flow (i.e. port send, receive etc'). ++ * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO ++ * struct. ++ * This struct includes user configuration information as well as ++ * driver internal data needed for its operations. ++ * ++ * Supported Features: ++ * - This low level driver is OS independent. Allocating memory for ++ * the descriptor rings and buffers are not within the scope of ++ * this driver. ++ * - The user is free from Rx/Tx queue managing. ++ * - This low level driver introduce functionality API that enable ++ * the to operate Marvell's Gigabit Ethernet Controller in a ++ * convenient way. ++ * - Simple Gigabit Ethernet port operation API. ++ * - Simple Gigabit Ethernet port data flow API. ++ * - Data flow and operation API support per queue functionality. ++ * - Support cached descriptors for better performance. ++ * - Enable access to all four DRAM banks and internal SRAM memory ++ * spaces. ++ * - PHY access and control API. ++ * - Port control register configuration API. ++ * - Full control over Unicast and Multicast MAC configurations. ++ * ++ * Operation flow: ++ * ++ * Initialization phase ++ * This phase complete the initialization of the ETH_PORT_INFO ++ * struct. ++ * User information regarding port configuration has to be set ++ * prior to calling the port initialization routine. For example, ++ * the user has to assign the port_phy_addr field which is board ++ * depended parameter. ++ * In this phase any port Tx/Rx activity is halted, MIB counters ++ * are cleared, PHY address is set according to user parameter and ++ * access to DRAM and internal SRAM memory spaces. ++ * ++ * Driver ring initialization ++ * Allocating memory for the descriptor rings and buffers is not ++ * within the scope of this driver. Thus, the user is required to ++ * allocate memory for the descriptors ring and buffers. Those ++ * memory parameters are used by the Rx and Tx ring initialization ++ * routines in order to curve the descriptor linked list in a form ++ * of a ring. ++ * Note: Pay special attention to alignment issues when using ++ * cached descriptors/buffers. In this phase the driver store ++ * information in the ETH_PORT_INFO struct regarding each queue ++ * ring. ++ * ++ * Driver start ++ * This phase prepares the Ethernet port for Rx and Tx activity. ++ * It uses the information stored in the ETH_PORT_INFO struct to ++ * initialize the various port registers. ++ * ++ * Data flow: ++ * All packet references to/from the driver are done using PKT_INFO ++ * struct. ++ * This struct is a unified struct used with Rx and Tx operations. ++ * This way the user is not required to be familiar with neither ++ * Tx nor Rx descriptors structures. ++ * The driver's descriptors rings are management by indexes. ++ * Those indexes controls the ring resources and used to indicate ++ * a SW resource error: ++ * 'current' ++ * This index points to the current available resource for use. For ++ * example in Rx process this index will point to the descriptor ++ * that will be passed to the user upon calling the receive routine. ++ * In Tx process, this index will point to the descriptor ++ * that will be assigned with the user packet info and transmitted. ++ * 'used' ++ * This index points to the descriptor that need to restore its ++ * resources. For example in Rx process, using the Rx buffer return ++ * API will attach the buffer returned in packet info to the ++ * descriptor pointed by 'used'. In Tx process, using the Tx ++ * descriptor return will merely return the user packet info with ++ * the command status of the transmitted buffer pointed by the ++ * 'used' index. Nevertheless, it is essential to use this routine ++ * to update the 'used' index. ++ * 'first' ++ * This index supports Tx Scatter-Gather. It points to the first ++ * descriptor of a packet assembled of multiple buffers. For example ++ * when in middle of Such packet we have a Tx resource error the ++ * 'curr' index get the value of 'first' to indicate that the ring ++ * returned to its state before trying to transmit this packet. ++ * ++ * Receive operation: ++ * The eth_port_receive API set the packet information struct, ++ * passed by the caller, with received information from the ++ * 'current' SDMA descriptor. ++ * It is the user responsibility to return this resource back ++ * to the Rx descriptor ring to enable the reuse of this source. ++ * Return Rx resource is done using the eth_rx_return_buff API. ++ * ++ * Transmit operation: ++ * The eth_port_send API supports Scatter-Gather which enables to ++ * send a packet spanned over multiple buffers. This means that ++ * for each packet info structure given by the user and put into ++ * the Tx descriptors ring, will be transmitted only if the 'LAST' ++ * bit will be set in the packet info command status field. This ++ * API also consider restriction regarding buffer alignments and ++ * sizes. ++ * The user must return a Tx resource after ensuring the buffer ++ * has been transmitted to enable the Tx ring indexes to update. ++ * ++ * BOARD LAYOUT ++ * This device is on-board. No jumper diagram is necessary. ++ * ++ * EXTERNAL INTERFACE ++ * ++ * Prior to calling the initialization routine eth_port_init() the user ++ * must set the following fields under ETH_PORT_INFO struct: ++ * port_num User Ethernet port number. ++ * port_phy_addr User PHY address of Ethernet port. ++ * port_mac_addr[6] User defined port MAC address. ++ * port_config User port configuration value. ++ * port_config_extend User port config extend value. ++ * port_sdma_config User port SDMA config value. ++ * port_serial_control User port serial control value. ++ * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr. ++ * *port_private User scratch pad for user specific data structures. ++ * ++ * This driver introduce a set of default values: ++ * PORT_CONFIG_VALUE Default port configuration value ++ * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value ++ * PORT_SDMA_CONFIG_VALUE Default sdma control value ++ * PORT_SERIAL_CONTROL_VALUE Default port serial control value ++ * ++ * This driver data flow is done using the PKT_INFO struct which is ++ * a unified struct for Rx and Tx operations: ++ * byte_cnt Tx/Rx descriptor buffer byte count. ++ * l4i_chk CPU provided TCP Checksum. For Tx operation only. ++ * cmd_sts Tx/Rx descriptor command status. ++ * buf_ptr Tx/Rx descriptor buffer pointer. ++ * return_info Tx/Rx user resource return information. ++ * ++ * ++ * EXTERNAL SUPPORT REQUIREMENTS ++ * ++ * This driver requires the following external support: ++ * ++ * D_CACHE_FLUSH_LINE (address, address offset) ++ * ++ * This macro applies assembly code to flush and invalidate cache ++ * line. ++ * address - address base. ++ * address offset - address offset ++ * ++ * ++ * CPU_PIPE_FLUSH ++ * ++ * This macro applies assembly code to flush the CPU pipeline. ++ * ++ *******************************************************************************/ ++/* includes */ ++ ++/* defines */ ++/* SDMA command macros */ ++#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \ ++ MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue)) ++ ++#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \ ++ MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\ ++ (1 << (8 + tx_queue))) ++ ++#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \ ++MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue)) ++ ++#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \ ++MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue))) ++ ++#define CURR_RFD_GET(p_curr_desc, queue) \ ++ ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue]) ++ ++#define CURR_RFD_SET(p_curr_desc, queue) \ ++ (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc)) ++ ++#define USED_RFD_GET(p_used_desc, queue) \ ++ ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue]) ++ ++#define USED_RFD_SET(p_used_desc, queue)\ ++(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc)) ++ ++ ++#define CURR_TFD_GET(p_curr_desc, queue) \ ++ ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue]) ++ ++#define CURR_TFD_SET(p_curr_desc, queue) \ ++ (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc)) ++ ++#define USED_TFD_GET(p_used_desc, queue) \ ++ ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue]) ++ ++#define USED_TFD_SET(p_used_desc, queue) \ ++ (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc)) ++ ++#define FIRST_TFD_GET(p_first_desc, queue) \ ++ ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue]) ++ ++#define FIRST_TFD_SET(p_first_desc, queue) \ ++ (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc)) ++ ++ ++/* Macros that save access to desc in order to find next desc pointer */ ++#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) ++ ++#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) ++ ++#define LINK_UP_TIMEOUT 100000 ++#define PHY_BUSY_TIMEOUT 10000000 ++ ++/* locals */ ++ ++/* PHY routines */ ++static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr); ++static int ethernet_phy_get (ETH_PORT eth_port_num); ++ ++/* Ethernet Port routines */ ++static void eth_set_access_control (ETH_PORT eth_port_num, ++ ETH_WIN_PARAM * param); ++static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble, ++ ETH_QUEUE queue, int option); ++#if 0 /* FIXME */ ++static bool eth_port_smc_addr (ETH_PORT eth_port_num, ++ unsigned char mc_byte, ++ ETH_QUEUE queue, int option); ++static bool eth_port_omc_addr (ETH_PORT eth_port_num, ++ unsigned char crc8, ++ ETH_QUEUE queue, int option); ++#endif ++ ++static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, ++ int byte_count); ++ ++void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl); ++ ++ ++typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK; ++u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank) ++{ ++ u32 result = 0; ++ u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE); ++ ++ if (enable & (1 << bank)) ++ return 0; ++ if (bank == BANK0) ++ result = MV_REG_READ (MV64460_CS_0_BASE_ADDR); ++ if (bank == BANK1) ++ result = MV_REG_READ (MV64460_CS_1_BASE_ADDR); ++ if (bank == BANK2) ++ result = MV_REG_READ (MV64460_CS_2_BASE_ADDR); ++ if (bank == BANK3) ++ result = MV_REG_READ (MV64460_CS_3_BASE_ADDR); ++ result &= 0x0000ffff; ++ result = result << 16; ++ return result; ++} ++ ++u32 mv_get_dram_bank_size (MEMORY_BANK bank) ++{ ++ u32 result = 0; ++ u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE); ++ ++ if (enable & (1 << bank)) ++ return 0; ++ if (bank == BANK0) ++ result = MV_REG_READ (MV64460_CS_0_SIZE); ++ if (bank == BANK1) ++ result = MV_REG_READ (MV64460_CS_1_SIZE); ++ if (bank == BANK2) ++ result = MV_REG_READ (MV64460_CS_2_SIZE); ++ if (bank == BANK3) ++ result = MV_REG_READ (MV64460_CS_3_SIZE); ++ result += 1; ++ result &= 0x0000ffff; ++ result = result << 16; ++ return result; ++} ++ ++u32 mv_get_internal_sram_base (void) ++{ ++ u32 result; ++ ++ result = MV_REG_READ (MV64460_INTEGRATED_SRAM_BASE_ADDR); ++ result &= 0x0000ffff; ++ result = result << 16; ++ return result; ++} ++ ++/******************************************************************************* ++* eth_port_init - Initialize the Ethernet port driver ++* ++* DESCRIPTION: ++* This function prepares the ethernet port to start its activity: ++* 1) Completes the ethernet port driver struct initialization toward port ++* start routine. ++* 2) Resets the device to a quiescent state in case of warm reboot. ++* 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. ++* 4) Clean MAC tables. The reset status of those tables is unknown. ++* 5) Set PHY address. ++* Note: Call this routine prior to eth_port_start routine and after setting ++* user values in the user fields of Ethernet port control struct (i.e. ++* port_phy_addr). ++* ++* INPUT: ++* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct ++* ++* OUTPUT: ++* See description. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl) ++{ ++ int queue; ++ ETH_WIN_PARAM win_param; ++ ++ p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE; ++ p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE; ++ p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE; ++ p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE; ++ ++ p_eth_port_ctrl->port_rx_queue_command = 0; ++ p_eth_port_ctrl->port_tx_queue_command = 0; ++ ++ /* Zero out SW structs */ ++ for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { ++ CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); ++ USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); ++ p_eth_port_ctrl->rx_resource_err[queue] = false; ++ } ++ ++ for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { ++ CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); ++ USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); ++ FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); ++ p_eth_port_ctrl->tx_resource_err[queue] = false; ++ } ++ ++ eth_port_reset (p_eth_port_ctrl->port_num); ++ ++ /* Set access parameters for DRAM bank 0 */ ++ win_param.win = ETH_WIN0; /* Use Ethernet window 0 */ ++ win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ ++ win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */ ++#ifndef CONFIG_NOT_COHERENT_CACHE ++ win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; ++#endif ++ win_param.high_addr = 0; ++ /* Get bank base */ ++ win_param.base_addr = mv_get_dram_bank_base_addr (BANK0); ++ win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */ ++ if (win_param.size == 0) ++ win_param.enable = 0; ++ else ++ win_param.enable = 1; /* Enable the access */ ++ win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ ++ ++ /* Set the access control for address window (EPAPR) READ & WRITE */ ++ eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); ++ ++ /* Set access parameters for DRAM bank 1 */ ++ win_param.win = ETH_WIN1; /* Use Ethernet window 1 */ ++ win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ ++ win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */ ++#ifndef CONFIG_NOT_COHERENT_CACHE ++ win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; ++#endif ++ win_param.high_addr = 0; ++ /* Get bank base */ ++ win_param.base_addr = mv_get_dram_bank_base_addr (BANK1); ++ win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */ ++ if (win_param.size == 0) ++ win_param.enable = 0; ++ else ++ win_param.enable = 1; /* Enable the access */ ++ win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ ++ ++ /* Set the access control for address window (EPAPR) READ & WRITE */ ++ eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); ++ ++ /* Set access parameters for DRAM bank 2 */ ++ win_param.win = ETH_WIN2; /* Use Ethernet window 2 */ ++ win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ ++ win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */ ++#ifndef CONFIG_NOT_COHERENT_CACHE ++ win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; ++#endif ++ win_param.high_addr = 0; ++ /* Get bank base */ ++ win_param.base_addr = mv_get_dram_bank_base_addr (BANK2); ++ win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */ ++ if (win_param.size == 0) ++ win_param.enable = 0; ++ else ++ win_param.enable = 1; /* Enable the access */ ++ win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ ++ ++ /* Set the access control for address window (EPAPR) READ & WRITE */ ++ eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); ++ ++ /* Set access parameters for DRAM bank 3 */ ++ win_param.win = ETH_WIN3; /* Use Ethernet window 3 */ ++ win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ ++ win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */ ++#ifndef CONFIG_NOT_COHERENT_CACHE ++ win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; ++#endif ++ win_param.high_addr = 0; ++ /* Get bank base */ ++ win_param.base_addr = mv_get_dram_bank_base_addr (BANK3); ++ win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */ ++ if (win_param.size == 0) ++ win_param.enable = 0; ++ else ++ win_param.enable = 1; /* Enable the access */ ++ win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ ++ ++ /* Set the access control for address window (EPAPR) READ & WRITE */ ++ eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); ++ ++ /* Set access parameters for Internal SRAM */ ++ win_param.win = ETH_WIN4; /* Use Ethernet window 0 */ ++ win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */ ++ win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0; ++ win_param.high_addr = 0; ++ win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */ ++ win_param.size = MV64460_INTERNAL_SRAM_SIZE; /* Get bank size */ ++ win_param.enable = 1; /* Enable the access */ ++ win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ ++ ++ /* Set the access control for address window (EPAPR) READ & WRITE */ ++ eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); ++ ++ eth_port_init_mac_tables (p_eth_port_ctrl->port_num); ++ ++ ethernet_phy_set (p_eth_port_ctrl->port_num, ++ p_eth_port_ctrl->port_phy_addr); ++ ++ return; ++ ++} ++ ++/******************************************************************************* ++* eth_port_start - Start the Ethernet port activity. ++* ++* DESCRIPTION: ++* This routine prepares the Ethernet port for Rx and Tx activity: ++* 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that ++* has been initialized a descriptor's ring (using ether_init_tx_desc_ring ++* for Tx and ether_init_rx_desc_ring for Rx) ++* 2. Initialize and enable the Ethernet configuration port by writing to ++* the port's configuration and command registers. ++* 3. Initialize and enable the SDMA by writing to the SDMA's ++* configuration and command registers. ++* After completing these steps, the ethernet port SDMA can starts to ++* perform Rx and Tx activities. ++* ++* Note: Each Rx and Tx queue descriptor's list must be initialized prior ++* to calling this function (use ether_init_tx_desc_ring for Tx queues and ++* ether_init_rx_desc_ring for Rx queues). ++* ++* INPUT: ++* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct ++* ++* OUTPUT: ++* Ethernet port is ready to receive and transmit. ++* ++* RETURN: ++* false if the port PHY is not up. ++* true otherwise. ++* ++*******************************************************************************/ ++static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl) ++{ ++ int queue; ++ volatile ETH_TX_DESC *p_tx_curr_desc; ++ volatile ETH_RX_DESC *p_rx_curr_desc; ++ unsigned int phy_reg_data; ++ ETH_PORT eth_port_num = p_eth_port_ctrl->port_num; ++ ++ /* Assignment of Tx CTRP of given queue */ ++ for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { ++ CURR_TFD_GET (p_tx_curr_desc, queue); ++ MV_REG_WRITE ((MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0 ++ (eth_port_num) ++ + (4 * queue)), ++ ((unsigned int) p_tx_curr_desc)); ++ ++ } ++ ++ /* Assignment of Rx CRDP of given queue */ ++ for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { ++ CURR_RFD_GET (p_rx_curr_desc, queue); ++ MV_REG_WRITE ((MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0 ++ (eth_port_num) ++ + (4 * queue)), ++ ((unsigned int) p_rx_curr_desc)); ++ ++ if (p_rx_curr_desc != NULL) ++ /* Add the assigned Ethernet address to the port's address table */ ++ eth_port_uc_addr_set (p_eth_port_ctrl->port_num, ++ p_eth_port_ctrl->port_mac_addr, ++ queue); ++ } ++ ++ /* Assign port configuration and command. */ ++ MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num), ++ p_eth_port_ctrl->port_config); ++ ++ MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), ++ p_eth_port_ctrl->port_config_extend); ++ ++ MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), ++ p_eth_port_ctrl->port_serial_control); ++ ++ MV_SET_REG_BITS (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), ++ ETH_SERIAL_PORT_ENABLE); ++ ++ /* Assign port SDMA configuration */ ++ MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num), ++ p_eth_port_ctrl->port_sdma_config); ++ ++ MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT ++ (eth_port_num), 0x3fffffff); ++ MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG ++ (eth_port_num), 0x03fffcff); ++ /* Turn off the port/queue bandwidth limitation */ ++ MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0); ++ ++ /* Enable port Rx. */ ++ MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num), ++ p_eth_port_ctrl->port_rx_queue_command); ++ ++ /* Check if link is up */ ++ eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); ++ ++ if (!(phy_reg_data & 0x20)) ++ return false; ++ ++ return true; ++} ++ ++/******************************************************************************* ++* eth_port_uc_addr_set - This function Set the port Unicast address. ++* ++* DESCRIPTION: ++* This function Set the port Ethernet MAC address. ++* ++* INPUT: ++* ETH_PORT eth_port_num Port number. ++* char * p_addr Address to be set ++* ETH_QUEUE queue Rx queue number for this MAC address. ++* ++* OUTPUT: ++* Set MAC address low and high registers. also calls eth_port_uc_addr() ++* To set the unicast table with the proper information. ++* ++* RETURN: ++* N/A. ++* ++*******************************************************************************/ ++static void eth_port_uc_addr_set (ETH_PORT eth_port_num, ++ unsigned char *p_addr, ETH_QUEUE queue) ++{ ++ unsigned int mac_h; ++ unsigned int mac_l; ++ ++ mac_l = (p_addr[4] << 8) | (p_addr[5]); ++ mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | ++ (p_addr[2] << 8) | (p_addr[3] << 0); ++ ++ MV_REG_WRITE (MV64460_ETH_MAC_ADDR_LOW (eth_port_num), mac_l); ++ MV_REG_WRITE (MV64460_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h); ++ ++ /* Accept frames of this address */ ++ eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR); ++ ++ return; ++} ++ ++/******************************************************************************* ++* eth_port_uc_addr - This function Set the port unicast address table ++* ++* DESCRIPTION: ++* This function locates the proper entry in the Unicast table for the ++* specified MAC nibble and sets its properties according to function ++* parameters. ++* ++* INPUT: ++* ETH_PORT eth_port_num Port number. ++* unsigned char uc_nibble Unicast MAC Address last nibble. ++* ETH_QUEUE queue Rx queue number for this MAC address. ++* int option 0 = Add, 1 = remove address. ++* ++* OUTPUT: ++* This function add/removes MAC addresses from the port unicast address ++* table. ++* ++* RETURN: ++* true is output succeeded. ++* false if option parameter is invalid. ++* ++*******************************************************************************/ ++static bool eth_port_uc_addr (ETH_PORT eth_port_num, ++ unsigned char uc_nibble, ++ ETH_QUEUE queue, int option) ++{ ++ unsigned int unicast_reg; ++ unsigned int tbl_offset; ++ unsigned int reg_offset; ++ ++ /* Locate the Unicast table entry */ ++ uc_nibble = (0xf & uc_nibble); ++ tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */ ++ reg_offset = uc_nibble % 4; /* Entry offset within the above register */ ++ ++ switch (option) { ++ case REJECT_MAC_ADDR: ++ /* Clear accepts frame bit at specified unicast DA table entry */ ++ unicast_reg = ++ MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE ++ (eth_port_num) ++ + tbl_offset)); ++ ++ unicast_reg &= (0x0E << (8 * reg_offset)); ++ ++ MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE ++ (eth_port_num) ++ + tbl_offset), unicast_reg); ++ break; ++ ++ case ACCEPT_MAC_ADDR: ++ /* Set accepts frame bit at unicast DA filter table entry */ ++ unicast_reg = ++ MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE ++ (eth_port_num) ++ + tbl_offset)); ++ ++ unicast_reg |= ((0x01 | queue) << (8 * reg_offset)); ++ ++ MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE ++ (eth_port_num) ++ + tbl_offset), unicast_reg); ++ ++ break; ++ ++ default: ++ return false; ++ } ++ return true; ++} ++ ++#if 0 /* FIXME */ ++/******************************************************************************* ++* eth_port_mc_addr - Multicast address settings. ++* ++* DESCRIPTION: ++* This API controls the MV device MAC multicast support. ++* The MV device supports multicast using two tables: ++* 1) Special Multicast Table for MAC addresses of the form ++* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). ++* The MAC DA[7:0] bits are used as a pointer to the Special Multicast ++* Table entries in the DA-Filter table. ++* In this case, the function calls eth_port_smc_addr() routine to set the ++* Special Multicast Table. ++* 2) Other Multicast Table for multicast of another type. A CRC-8bit ++* is used as an index to the Other Multicast Table entries in the ++* DA-Filter table. ++* In this case, the function calculates the CRC-8bit value and calls ++* eth_port_omc_addr() routine to set the Other Multicast Table. ++* INPUT: ++* ETH_PORT eth_port_num Port number. ++* unsigned char *p_addr Unicast MAC Address. ++* ETH_QUEUE queue Rx queue number for this MAC address. ++* int option 0 = Add, 1 = remove address. ++* ++* OUTPUT: ++* See description. ++* ++* RETURN: ++* true is output succeeded. ++* false if add_address_table_entry( ) failed. ++* ++*******************************************************************************/ ++static void eth_port_mc_addr (ETH_PORT eth_port_num, ++ unsigned char *p_addr, ++ ETH_QUEUE queue, int option) ++{ ++ unsigned int mac_h; ++ unsigned int mac_l; ++ unsigned char crc_result = 0; ++ int mac_array[48]; ++ int crc[8]; ++ int i; ++ ++ if ((p_addr[0] == 0x01) && ++ (p_addr[1] == 0x00) && ++ (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) { ++ ++ eth_port_smc_addr (eth_port_num, p_addr[5], queue, option); ++ } else { ++ /* Calculate CRC-8 out of the given address */ ++ mac_h = (p_addr[0] << 8) | (p_addr[1]); ++ mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | ++ (p_addr[4] << 8) | (p_addr[5] << 0); ++ ++ for (i = 0; i < 32; i++) ++ mac_array[i] = (mac_l >> i) & 0x1; ++ for (i = 32; i < 48; i++) ++ mac_array[i] = (mac_h >> (i - 32)) & 0x1; ++ ++ crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ ++ mac_array[39] ^ mac_array[35] ^ mac_array[34] ^ ++ mac_array[31] ^ mac_array[30] ^ mac_array[28] ^ ++ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ ++ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ ++ mac_array[12] ^ mac_array[8] ^ mac_array[7] ^ ++ mac_array[6] ^ mac_array[0]; ++ ++ crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ ++ mac_array[43] ^ mac_array[41] ^ mac_array[39] ^ ++ mac_array[36] ^ mac_array[34] ^ mac_array[32] ^ ++ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ ++ mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ ++ mac_array[21] ^ mac_array[20] ^ mac_array[18] ^ ++ mac_array[17] ^ mac_array[16] ^ mac_array[15] ^ ++ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ ++ mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ ++ mac_array[0]; ++ ++ crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ ++ mac_array[43] ^ mac_array[42] ^ mac_array[39] ^ ++ mac_array[37] ^ mac_array[34] ^ mac_array[33] ^ ++ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ ++ mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ ++ mac_array[15] ^ mac_array[13] ^ mac_array[12] ^ ++ mac_array[10] ^ mac_array[8] ^ mac_array[6] ^ ++ mac_array[2] ^ mac_array[1] ^ mac_array[0]; ++ ++ crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ ++ mac_array[43] ^ mac_array[40] ^ mac_array[38] ^ ++ mac_array[35] ^ mac_array[34] ^ mac_array[30] ^ ++ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ ++ mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ ++ mac_array[14] ^ mac_array[13] ^ mac_array[11] ^ ++ mac_array[9] ^ mac_array[7] ^ mac_array[3] ^ ++ mac_array[2] ^ mac_array[1]; ++ ++ crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ ++ mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ ++ mac_array[35] ^ mac_array[31] ^ mac_array[30] ^ ++ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ ++ mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ ++ mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ ++ mac_array[8] ^ mac_array[4] ^ mac_array[3] ^ ++ mac_array[2]; ++ ++ crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ ++ mac_array[42] ^ mac_array[40] ^ mac_array[37] ^ ++ mac_array[36] ^ mac_array[32] ^ mac_array[31] ^ ++ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ ++ mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ ++ mac_array[15] ^ mac_array[13] ^ mac_array[11] ^ ++ mac_array[9] ^ mac_array[5] ^ mac_array[4] ^ ++ mac_array[3]; ++ ++ crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ ++ mac_array[41] ^ mac_array[38] ^ mac_array[37] ^ ++ mac_array[33] ^ mac_array[32] ^ mac_array[29] ^ ++ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ ++ mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ ++ mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ ++ mac_array[6] ^ mac_array[5] ^ mac_array[4]; ++ ++ crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ ++ mac_array[39] ^ mac_array[38] ^ mac_array[34] ^ ++ mac_array[33] ^ mac_array[30] ^ mac_array[29] ^ ++ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ ++ mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ ++ mac_array[13] ^ mac_array[11] ^ mac_array[7] ^ ++ mac_array[6] ^ mac_array[5]; ++ ++ for (i = 0; i < 8; i++) ++ crc_result = crc_result | (crc[i] << i); ++ ++ eth_port_omc_addr (eth_port_num, crc_result, queue, option); ++ } ++ return; ++} ++ ++/******************************************************************************* ++* eth_port_smc_addr - Special Multicast address settings. ++* ++* DESCRIPTION: ++* This routine controls the MV device special MAC multicast support. ++* The Special Multicast Table for MAC addresses supports MAC of the form ++* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). ++* The MAC DA[7:0] bits are used as a pointer to the Special Multicast ++* Table entries in the DA-Filter table. ++* This function set the Special Multicast Table appropriate entry ++* according to the argument given. ++* ++* INPUT: ++* ETH_PORT eth_port_num Port number. ++* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). ++* ETH_QUEUE queue Rx queue number for this MAC address. ++* int option 0 = Add, 1 = remove address. ++* ++* OUTPUT: ++* See description. ++* ++* RETURN: ++* true is output succeeded. ++* false if option parameter is invalid. ++* ++*******************************************************************************/ ++static bool eth_port_smc_addr (ETH_PORT eth_port_num, ++ unsigned char mc_byte, ++ ETH_QUEUE queue, int option) ++{ ++ unsigned int smc_table_reg; ++ unsigned int tbl_offset; ++ unsigned int reg_offset; ++ ++ /* Locate the SMC table entry */ ++ tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */ ++ reg_offset = mc_byte % 4; /* Entry offset within the above register */ ++ queue &= 0x7; ++ ++ switch (option) { ++ case REJECT_MAC_ADDR: ++ /* Clear accepts frame bit at specified Special DA table entry */ ++ smc_table_reg = ++ MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); ++ smc_table_reg &= (0x0E << (8 * reg_offset)); ++ ++ MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); ++ break; ++ ++ case ACCEPT_MAC_ADDR: ++ /* Set accepts frame bit at specified Special DA table entry */ ++ smc_table_reg = ++ MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); ++ smc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); ++ ++ MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); ++ break; ++ ++ default: ++ return false; ++ } ++ return true; ++} ++ ++/******************************************************************************* ++* eth_port_omc_addr - Multicast address settings. ++* ++* DESCRIPTION: ++* This routine controls the MV device Other MAC multicast support. ++* The Other Multicast Table is used for multicast of another type. ++* A CRC-8bit is used as an index to the Other Multicast Table entries ++* in the DA-Filter table. ++* The function gets the CRC-8bit value from the calling routine and ++* set the Other Multicast Table appropriate entry according to the ++* CRC-8 argument given. ++* ++* INPUT: ++* ETH_PORT eth_port_num Port number. ++* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). ++* ETH_QUEUE queue Rx queue number for this MAC address. ++* int option 0 = Add, 1 = remove address. ++* ++* OUTPUT: ++* See description. ++* ++* RETURN: ++* true is output succeeded. ++* false if option parameter is invalid. ++* ++*******************************************************************************/ ++static bool eth_port_omc_addr (ETH_PORT eth_port_num, ++ unsigned char crc8, ++ ETH_QUEUE queue, int option) ++{ ++ unsigned int omc_table_reg; ++ unsigned int tbl_offset; ++ unsigned int reg_offset; ++ ++ /* Locate the OMC table entry */ ++ tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ ++ reg_offset = crc8 % 4; /* Entry offset within the above register */ ++ queue &= 0x7; ++ ++ switch (option) { ++ case REJECT_MAC_ADDR: ++ /* Clear accepts frame bit at specified Other DA table entry */ ++ omc_table_reg = ++ MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); ++ omc_table_reg &= (0x0E << (8 * reg_offset)); ++ ++ MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); ++ break; ++ ++ case ACCEPT_MAC_ADDR: ++ /* Set accepts frame bit at specified Other DA table entry */ ++ omc_table_reg = ++ MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); ++ omc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); ++ ++ MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); ++ break; ++ ++ default: ++ return false; ++ } ++ return true; ++} ++#endif ++ ++/******************************************************************************* ++* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables ++* ++* DESCRIPTION: ++* Go through all the DA filter tables (Unicast, Special Multicast & Other ++* Multicast) and set each entry to 0. ++* ++* INPUT: ++* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. ++* ++* OUTPUT: ++* Multicast and Unicast packets are rejected. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static void eth_port_init_mac_tables (ETH_PORT eth_port_num) ++{ ++ int table_index; ++ ++ /* Clear DA filter unicast table (Ex_dFUT) */ ++ for (table_index = 0; table_index <= 0xC; table_index += 4) ++ MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE ++ (eth_port_num) + table_index), 0); ++ ++ for (table_index = 0; table_index <= 0xFC; table_index += 4) { ++ /* Clear DA filter special multicast table (Ex_dFSMT) */ ++ MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); ++ /* Clear DA filter other multicast table (Ex_dFOMT) */ ++ MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); ++ } ++} ++ ++/******************************************************************************* ++* eth_clear_mib_counters - Clear all MIB counters ++* ++* DESCRIPTION: ++* This function clears all MIB counters of a specific ethernet port. ++* A read from the MIB counter will reset the counter. ++* ++* INPUT: ++* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. ++* ++* OUTPUT: ++* After reading all MIB counters, the counters resets. ++* ++* RETURN: ++* MIB counter value. ++* ++*******************************************************************************/ ++static void eth_clear_mib_counters (ETH_PORT eth_port_num) ++{ ++ int i; ++ unsigned int dummy; ++ ++ /* Perform dummy reads from MIB counters */ ++ for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; ++ i += 4) ++ dummy = MV_REG_READ ((MV64460_ETH_MIB_COUNTERS_BASE ++ (eth_port_num) + i)); ++ ++ return; ++} ++ ++/******************************************************************************* ++* eth_read_mib_counter - Read a MIB counter ++* ++* DESCRIPTION: ++* This function reads a MIB counter of a specific ethernet port. ++* NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the ++* following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH ++* register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and ++* ETH_MIB_GOOD_OCTETS_SENT_HIGH ++* ++* INPUT: ++* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. ++* unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros). ++* ++* OUTPUT: ++* After reading the MIB counter, the counter resets. ++* ++* RETURN: ++* MIB counter value. ++* ++*******************************************************************************/ ++unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, ++ unsigned int mib_offset) ++{ ++ return (MV_REG_READ (MV64460_ETH_MIB_COUNTERS_BASE (eth_port_num) ++ + mib_offset)); ++} ++ ++/******************************************************************************* ++* ethernet_phy_set - Set the ethernet port PHY address. ++* ++* DESCRIPTION: ++* This routine set the ethernet port PHY address according to given ++* parameter. ++* ++* INPUT: ++* ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. ++* ++* OUTPUT: ++* Set PHY Address Register with given PHY address parameter. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr) ++{ ++ unsigned int reg_data; ++ ++ reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG); ++ ++ reg_data &= ~(0x1F << (5 * eth_port_num)); ++ reg_data |= (phy_addr << (5 * eth_port_num)); ++ ++ MV_REG_WRITE (MV64460_ETH_PHY_ADDR_REG, reg_data); ++ ++ return; ++} ++ ++/******************************************************************************* ++ * ethernet_phy_get - Get the ethernet port PHY address. ++ * ++ * DESCRIPTION: ++ * This routine returns the given ethernet port PHY address. ++ * ++ * INPUT: ++ * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. ++ * ++ * OUTPUT: ++ * None. ++ * ++ * RETURN: ++ * PHY address. ++ * ++ *******************************************************************************/ ++static int ethernet_phy_get (ETH_PORT eth_port_num) ++{ ++ unsigned int reg_data; ++ ++ reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG); ++ ++ return ((reg_data >> (5 * eth_port_num)) & 0x1f); ++} ++ ++/***********************************************************/ ++/* (Re)start autonegotiation */ ++/***********************************************************/ ++int phy_setup_aneg (char *devname, unsigned char addr) ++{ ++ unsigned short ctl, adv; ++ ++ /* Setup standard advertise */ ++ miiphy_read (devname, addr, PHY_ANAR, &adv); ++ adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 | ++ PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD | ++ PHY_ANLPAR_10); ++ miiphy_write (devname, addr, PHY_ANAR, adv); ++ ++ miiphy_read (devname, addr, PHY_1000BTCR, &adv); ++ adv |= (0x0300); ++ miiphy_write (devname, addr, PHY_1000BTCR, adv); ++ ++ /* Start/Restart aneg */ ++ miiphy_read (devname, addr, PHY_BMCR, &ctl); ++ ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); ++ miiphy_write (devname, addr, PHY_BMCR, ctl); ++ ++ return 0; ++} ++ ++/******************************************************************************* ++ * ethernet_phy_reset - Reset Ethernet port PHY. ++ * ++ * DESCRIPTION: ++ * This routine utilize the SMI interface to reset the ethernet port PHY. ++ * The routine waits until the link is up again or link up is timeout. ++ * ++ * INPUT: ++ * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. ++ * ++ * OUTPUT: ++ * The ethernet port PHY renew its link. ++ * ++ * RETURN: ++ * None. ++ * ++ *******************************************************************************/ ++static bool ethernet_phy_reset (ETH_PORT eth_port_num) ++{ ++ unsigned int time_out = 50; ++ unsigned int phy_reg_data; ++ ++ eth_port_read_smi_reg (eth_port_num, 20, &phy_reg_data); ++ phy_reg_data |= 0x0083; /* Set bit 7 to 1 for different RGMII timing */ ++ eth_port_write_smi_reg (eth_port_num, 20, phy_reg_data); ++ ++ /* Reset the PHY */ ++ eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data); ++ phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ ++ eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data); ++ ++ /* Poll on the PHY LINK */ ++ do { ++ eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); ++ ++ if (time_out-- == 0) ++ return false; ++ } ++ while (!(phy_reg_data & 0x20)); ++ ++ return true; ++} ++ ++/******************************************************************************* ++ * eth_port_reset - Reset Ethernet port ++ * ++ * DESCRIPTION: ++ * This routine resets the chip by aborting any SDMA engine activity and ++ * clearing the MIB counters. The Receiver and the Transmit unit are in ++ * idle state after this command is performed and the port is disabled. ++ * ++ * INPUT: ++ * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. ++ * ++ * OUTPUT: ++ * Channel activity is halted. ++ * ++ * RETURN: ++ * None. ++ * ++ *******************************************************************************/ ++static void eth_port_reset (ETH_PORT eth_port_num) ++{ ++ unsigned int reg_data; ++ ++ /* Stop Tx port activity. Check port Tx activity. */ ++ reg_data = ++ MV_REG_READ (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG ++ (eth_port_num)); ++ ++ if (reg_data & 0xFF) { ++ /* Issue stop command for active channels only */ ++ MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG ++ (eth_port_num), (reg_data << 8)); ++ ++ /* Wait for all Tx activity to terminate. */ ++ do { ++ /* Check port cause register that all Tx queues are stopped */ ++ reg_data = ++ MV_REG_READ ++ (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG ++ (eth_port_num)); ++ } ++ while (reg_data & 0xFF); ++ } ++ ++ /* Stop Rx port activity. Check port Rx activity. */ ++ reg_data = ++ MV_REG_READ (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG ++ (eth_port_num)); ++ ++ if (reg_data & 0xFF) { ++ /* Issue stop command for active channels only */ ++ MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG ++ (eth_port_num), (reg_data << 8)); ++ ++ /* Wait for all Rx activity to terminate. */ ++ do { ++ /* Check port cause register that all Rx queues are stopped */ ++ reg_data = ++ MV_REG_READ ++ (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG ++ (eth_port_num)); ++ } ++ while (reg_data & 0xFF); ++ } ++ ++ /* Clear all MIB counters */ ++ eth_clear_mib_counters (eth_port_num); ++ ++ /* Reset the Enable bit in the Configuration Register */ ++ reg_data = ++ MV_REG_READ (MV64460_ETH_PORT_SERIAL_CONTROL_REG ++ (eth_port_num)); ++ reg_data &= ~ETH_SERIAL_PORT_ENABLE; ++ MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), ++ reg_data); ++ ++ return; ++} ++ ++#if 0 /* Not needed here */ ++/******************************************************************************* ++ * ethernet_set_config_reg - Set specified bits in configuration register. ++ * ++ * DESCRIPTION: ++ * This function sets specified bits in the given ethernet ++ * configuration register. ++ * ++ * INPUT: ++ * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. ++ * unsigned int value 32 bit value. ++ * ++ * OUTPUT: ++ * The set bits in the value parameter are set in the configuration ++ * register. ++ * ++ * RETURN: ++ * None. ++ * ++ *******************************************************************************/ ++static void ethernet_set_config_reg (ETH_PORT eth_port_num, ++ unsigned int value) ++{ ++ unsigned int eth_config_reg; ++ ++ eth_config_reg = ++ MV_REG_READ (MV64460_ETH_PORT_CONFIG_REG (eth_port_num)); ++ eth_config_reg |= value; ++ MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num), ++ eth_config_reg); ++ ++ return; ++} ++#endif ++ ++#if 0 /* FIXME */ ++/******************************************************************************* ++ * ethernet_reset_config_reg - Reset specified bits in configuration register. ++ * ++ * DESCRIPTION: ++ * This function resets specified bits in the given Ethernet ++ * configuration register. ++ * ++ * INPUT: ++ * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. ++ * unsigned int value 32 bit value. ++ * ++ * OUTPUT: ++ * The set bits in the value parameter are reset in the configuration ++ * register. ++ * ++ * RETURN: ++ * None. ++ * ++ *******************************************************************************/ ++static void ethernet_reset_config_reg (ETH_PORT eth_port_num, ++ unsigned int value) ++{ ++ unsigned int eth_config_reg; ++ ++ eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG ++ (eth_port_num)); ++ eth_config_reg &= ~value; ++ MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), ++ eth_config_reg); ++ ++ return; ++} ++#endif ++ ++#if 0 /* Not needed here */ ++/******************************************************************************* ++ * ethernet_get_config_reg - Get the port configuration register ++ * ++ * DESCRIPTION: ++ * This function returns the configuration register value of the given ++ * ethernet port. ++ * ++ * INPUT: ++ * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. ++ * ++ * OUTPUT: ++ * None. ++ * ++ * RETURN: ++ * Port configuration register value. ++ * ++ *******************************************************************************/ ++static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num) ++{ ++ unsigned int eth_config_reg; ++ ++ eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG ++ (eth_port_num)); ++ return eth_config_reg; ++} ++ ++#endif ++ ++/******************************************************************************* ++ * eth_port_read_smi_reg - Read PHY registers ++ * ++ * DESCRIPTION: ++ * This routine utilize the SMI interface to interact with the PHY in ++ * order to perform PHY register read. ++ * ++ * INPUT: ++ * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. ++ * unsigned int phy_reg PHY register address offset. ++ * unsigned int *value Register value buffer. ++ * ++ * OUTPUT: ++ * Write the value of a specified PHY register into given buffer. ++ * ++ * RETURN: ++ * false if the PHY is busy or read data is not in valid state. ++ * true otherwise. ++ * ++ *******************************************************************************/ ++static bool eth_port_read_smi_reg (ETH_PORT eth_port_num, ++ unsigned int phy_reg, unsigned int *value) ++{ ++ unsigned int reg_value; ++ unsigned int time_out = PHY_BUSY_TIMEOUT; ++ int phy_addr; ++ ++ phy_addr = ethernet_phy_get (eth_port_num); ++ ++ /* first check that it is not busy */ ++ do { ++ reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); ++ if (time_out-- == 0) { ++ return false; ++ } ++ } ++ while (reg_value & ETH_SMI_BUSY); ++ ++ /* not busy */ ++ ++ MV_REG_WRITE (MV64460_ETH_SMI_REG, ++ (phy_addr << 16) | (phy_reg << 21) | ++ ETH_SMI_OPCODE_READ); ++ ++ time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */ ++ ++ do { ++ reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); ++ if (time_out-- == 0) { ++ return false; ++ } ++ } ++ while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */ ++ ++ /* Wait for the data to update in the SMI register */ ++#define PHY_UPDATE_TIMEOUT 10000 ++ for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++); ++ ++ reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); ++ ++ *value = reg_value & 0xffff; ++ ++ return true; ++} ++ ++int mv_miiphy_read(char *devname, unsigned char phy_addr, ++ unsigned char phy_reg, unsigned short *value) ++{ ++ unsigned int reg_value; ++ unsigned int time_out = PHY_BUSY_TIMEOUT; ++ ++ /* first check that it is not busy */ ++ do { ++ reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); ++ if (time_out-- == 0) { ++ return false; ++ } ++ } ++ while (reg_value & ETH_SMI_BUSY); ++ ++ /* not busy */ ++ MV_REG_WRITE (MV64460_ETH_SMI_REG, ++ (phy_addr << 16) | (phy_reg << 21) | ++ ETH_SMI_OPCODE_READ); ++ ++ time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */ ++ ++ do { ++ reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); ++ if (time_out-- == 0) { ++ return false; ++ } ++ } ++ while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */ ++ ++ /* Wait for the data to update in the SMI register */ ++ for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++); ++ ++ reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); ++ ++ *value = reg_value & 0xffff; ++ ++ return 0; ++} ++ ++/******************************************************************************* ++ * eth_port_write_smi_reg - Write to PHY registers ++ * ++ * DESCRIPTION: ++ * This routine utilize the SMI interface to interact with the PHY in ++ * order to perform writes to PHY registers. ++ * ++ * INPUT: ++ * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. ++ * unsigned int phy_reg PHY register address offset. ++ * unsigned int value Register value. ++ * ++ * OUTPUT: ++ * Write the given value to the specified PHY register. ++ * ++ * RETURN: ++ * false if the PHY is busy. ++ * true otherwise. ++ * ++ *******************************************************************************/ ++static bool eth_port_write_smi_reg (ETH_PORT eth_port_num, ++ unsigned int phy_reg, unsigned int value) ++{ ++ unsigned int reg_value; ++ unsigned int time_out = PHY_BUSY_TIMEOUT; ++ int phy_addr; ++ ++ phy_addr = ethernet_phy_get (eth_port_num); ++ ++ /* first check that it is not busy */ ++ do { ++ reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); ++ if (time_out-- == 0) { ++ return false; ++ } ++ } ++ while (reg_value & ETH_SMI_BUSY); ++ ++ /* not busy */ ++ MV_REG_WRITE (MV64460_ETH_SMI_REG, ++ (phy_addr << 16) | (phy_reg << 21) | ++ ETH_SMI_OPCODE_WRITE | (value & 0xffff)); ++ return true; ++} ++ ++int mv_miiphy_write(char *devname, unsigned char phy_addr, ++ unsigned char phy_reg, unsigned short value) ++{ ++ unsigned int reg_value; ++ unsigned int time_out = PHY_BUSY_TIMEOUT; ++ ++ /* first check that it is not busy */ ++ do { ++ reg_value = MV_REG_READ (MV64460_ETH_SMI_REG); ++ if (time_out-- == 0) { ++ return false; ++ } ++ } ++ while (reg_value & ETH_SMI_BUSY); ++ ++ /* not busy */ ++ MV_REG_WRITE (MV64460_ETH_SMI_REG, ++ (phy_addr << 16) | (phy_reg << 21) | ++ ETH_SMI_OPCODE_WRITE | (value & 0xffff)); ++ return 0; ++} ++ ++/******************************************************************************* ++ * eth_set_access_control - Config address decode parameters for Ethernet unit ++ * ++ * DESCRIPTION: ++ * This function configures the address decode parameters for the Gigabit ++ * Ethernet Controller according the given parameters struct. ++ * ++ * INPUT: ++ * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. ++ * ETH_WIN_PARAM *param Address decode parameter struct. ++ * ++ * OUTPUT: ++ * An access window is opened using the given access parameters. ++ * ++ * RETURN: ++ * None. ++ * ++ *******************************************************************************/ ++static void eth_set_access_control (ETH_PORT eth_port_num, ++ ETH_WIN_PARAM * param) ++{ ++ unsigned int access_prot_reg; ++ ++ /* Set access control register */ ++ access_prot_reg = MV_REG_READ (MV64460_ETH_ACCESS_PROTECTION_REG ++ (eth_port_num)); ++ access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */ ++ access_prot_reg |= (param->access_ctrl << (param->win * 2)); ++ MV_REG_WRITE (MV64460_ETH_ACCESS_PROTECTION_REG (eth_port_num), ++ access_prot_reg); ++ ++ /* Set window Size reg (SR) */ ++ MV_REG_WRITE ((MV64460_ETH_SIZE_REG_0 + ++ (ETH_SIZE_REG_GAP * param->win)), ++ (((param->size / 0x10000) - 1) << 16)); ++ ++ /* Set window Base address reg (BA) */ ++ MV_REG_WRITE ((MV64460_ETH_BAR_0 + (ETH_BAR_GAP * param->win)), ++ (param->target | param->attributes | param->base_addr)); ++ /* High address remap reg (HARR) */ ++ if (param->win < 4) ++ MV_REG_WRITE ((MV64460_ETH_HIGH_ADDR_REMAP_REG_0 + ++ (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)), ++ param->high_addr); ++ ++ /* Base address enable reg (BARER) */ ++ if (param->enable == 1) ++ MV_RESET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG, ++ (1 << param->win)); ++ else ++ MV_SET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG, ++ (1 << param->win)); ++} ++ ++/******************************************************************************* ++ * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. ++ * ++ * DESCRIPTION: ++ * This function prepares a Rx chained list of descriptors and packet ++ * buffers in a form of a ring. The routine must be called after port ++ * initialization routine and before port start routine. ++ * The Ethernet SDMA engine uses CPU bus addresses to access the various ++ * devices in the system (i.e. DRAM). This function uses the ethernet ++ * struct 'virtual to physical' routine (set by the user) to set the ring ++ * with physical addresses. ++ * ++ * INPUT: ++ * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. ++ * ETH_QUEUE rx_queue Number of Rx queue. ++ * int rx_desc_num Number of Rx descriptors ++ * int rx_buff_size Size of Rx buffer ++ * unsigned int rx_desc_base_addr Rx descriptors memory area base addr. ++ * unsigned int rx_buff_base_addr Rx buffer memory area base addr. ++ * ++ * OUTPUT: ++ * The routine updates the Ethernet port control struct with information ++ * regarding the Rx descriptors and buffers. ++ * ++ * RETURN: ++ * false if the given descriptors memory area is not aligned according to ++ * Ethernet SDMA specifications. ++ * true otherwise. ++ * ++ *******************************************************************************/ ++static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, ++ ETH_QUEUE rx_queue, ++ int rx_desc_num, ++ int rx_buff_size, ++ unsigned int rx_desc_base_addr, ++ unsigned int rx_buff_base_addr) ++{ ++ ETH_RX_DESC *p_rx_desc; ++ ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */ ++ unsigned int buffer_addr; ++ int ix; /* a counter */ ++ ++ p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr; ++ p_rx_prev_desc = p_rx_desc; ++ buffer_addr = rx_buff_base_addr; ++ ++ /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ ++ if (rx_buff_base_addr & 0xF) ++ return false; ++ ++ /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */ ++ if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE)) ++ return false; ++ ++ /* Rx buffers must be 64-bit aligned. */ ++ if ((rx_buff_base_addr + rx_buff_size) & 0x7) ++ return false; ++ ++ /* initialize the Rx descriptors ring */ ++ for (ix = 0; ix < rx_desc_num; ix++) { ++ p_rx_desc->buf_size = rx_buff_size; ++ p_rx_desc->byte_cnt = 0x0000; ++ p_rx_desc->cmd_sts = ++ ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; ++ p_rx_desc->next_desc_ptr = ++ ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE; ++ p_rx_desc->buf_ptr = buffer_addr; ++ p_rx_desc->return_info = 0x00000000; ++ D_CACHE_FLUSH_LINE (p_rx_desc, 0); ++ buffer_addr += rx_buff_size; ++ p_rx_prev_desc = p_rx_desc; ++ p_rx_desc = (ETH_RX_DESC *) ++ ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE); ++ } ++ ++ /* Closing Rx descriptors ring */ ++ p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr); ++ D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0); ++ ++ /* Save Rx desc pointer to driver struct. */ ++ CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); ++ USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); ++ ++ p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] = ++ (ETH_RX_DESC *) rx_desc_base_addr; ++ p_eth_port_ctrl->rx_desc_area_size[rx_queue] = ++ rx_desc_num * RX_DESC_ALIGNED_SIZE; ++ ++ p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue); ++ ++ return true; ++} ++ ++/******************************************************************************* ++ * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. ++ * ++ * DESCRIPTION: ++ * This function prepares a Tx chained list of descriptors and packet ++ * buffers in a form of a ring. The routine must be called after port ++ * initialization routine and before port start routine. ++ * The Ethernet SDMA engine uses CPU bus addresses to access the various ++ * devices in the system (i.e. DRAM). This function uses the ethernet ++ * struct 'virtual to physical' routine (set by the user) to set the ring ++ * with physical addresses. ++ * ++ * INPUT: ++ * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. ++ * ETH_QUEUE tx_queue Number of Tx queue. ++ * int tx_desc_num Number of Tx descriptors ++ * int tx_buff_size Size of Tx buffer ++ * unsigned int tx_desc_base_addr Tx descriptors memory area base addr. ++ * unsigned int tx_buff_base_addr Tx buffer memory area base addr. ++ * ++ * OUTPUT: ++ * The routine updates the Ethernet port control struct with information ++ * regarding the Tx descriptors and buffers. ++ * ++ * RETURN: ++ * false if the given descriptors memory area is not aligned according to ++ * Ethernet SDMA specifications. ++ * true otherwise. ++ * ++ *******************************************************************************/ ++static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, ++ ETH_QUEUE tx_queue, ++ int tx_desc_num, ++ int tx_buff_size, ++ unsigned int tx_desc_base_addr, ++ unsigned int tx_buff_base_addr) ++{ ++ ++ ETH_TX_DESC *p_tx_desc; ++ ETH_TX_DESC *p_tx_prev_desc; ++ unsigned int buffer_addr; ++ int ix; /* a counter */ ++ ++ /* save the first desc pointer to link with the last descriptor */ ++ p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr; ++ p_tx_prev_desc = p_tx_desc; ++ buffer_addr = tx_buff_base_addr; ++ ++ /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ ++ if (tx_buff_base_addr & 0xF) ++ return false; ++ ++ /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */ ++ if ((tx_buff_size > TX_BUFFER_MAX_SIZE) ++ || (tx_buff_size < TX_BUFFER_MIN_SIZE)) ++ return false; ++ ++ /* Initialize the Tx descriptors ring */ ++ for (ix = 0; ix < tx_desc_num; ix++) { ++ p_tx_desc->byte_cnt = 0x0000; ++ p_tx_desc->l4i_chk = 0x0000; ++ p_tx_desc->cmd_sts = 0x00000000; ++ p_tx_desc->next_desc_ptr = ++ ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE; ++ ++ p_tx_desc->buf_ptr = buffer_addr; ++ p_tx_desc->return_info = 0x00000000; ++ D_CACHE_FLUSH_LINE (p_tx_desc, 0); ++ buffer_addr += tx_buff_size; ++ p_tx_prev_desc = p_tx_desc; ++ p_tx_desc = (ETH_TX_DESC *) ++ ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE); ++ ++ } ++ /* Closing Tx descriptors ring */ ++ p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr; ++ D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0); ++ /* Set Tx desc pointer in driver struct. */ ++ CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); ++ USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); ++ ++ /* Init Tx ring base and size parameters */ ++ p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] = ++ (ETH_TX_DESC *) tx_desc_base_addr; ++ p_eth_port_ctrl->tx_desc_area_size[tx_queue] = ++ (tx_desc_num * TX_DESC_ALIGNED_SIZE); ++ ++ /* Add the queue to the list of Tx queues of this port */ ++ p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue); ++ ++ return true; ++} ++ ++/******************************************************************************* ++ * eth_port_send - Send an Ethernet packet ++ * ++ * DESCRIPTION: ++ * This routine send a given packet described by p_pktinfo parameter. It ++ * supports transmitting of a packet spaned over multiple buffers. The ++ * routine updates 'curr' and 'first' indexes according to the packet ++ * segment passed to the routine. In case the packet segment is first, ++ * the 'first' index is update. In any case, the 'curr' index is updated. ++ * If the routine get into Tx resource error it assigns 'curr' index as ++ * 'first'. This way the function can abort Tx process of multiple ++ * descriptors per packet. ++ * ++ * INPUT: ++ * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. ++ * ETH_QUEUE tx_queue Number of Tx queue. ++ * PKT_INFO *p_pkt_info User packet buffer. ++ * ++ * OUTPUT: ++ * Tx ring 'curr' and 'first' indexes are updated. ++ * ++ * RETURN: ++ * ETH_QUEUE_FULL in case of Tx resource error. ++ * ETH_ERROR in case the routine can not access Tx desc ring. ++ * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource. ++ * ETH_OK otherwise. ++ * ++ *******************************************************************************/ ++static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl, ++ ETH_QUEUE tx_queue, ++ PKT_INFO * p_pkt_info) ++{ ++ volatile ETH_TX_DESC *p_tx_desc_first; ++ volatile ETH_TX_DESC *p_tx_desc_curr; ++ volatile ETH_TX_DESC *p_tx_next_desc_curr; ++ volatile ETH_TX_DESC *p_tx_desc_used; ++ unsigned int command_status; ++ ++ /* Do not process Tx ring in case of Tx ring resource error */ ++ if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) ++ return ETH_QUEUE_FULL; ++ ++ /* Get the Tx Desc ring indexes */ ++ CURR_TFD_GET (p_tx_desc_curr, tx_queue); ++ USED_TFD_GET (p_tx_desc_used, tx_queue); ++ ++ if (p_tx_desc_curr == NULL) ++ return ETH_ERROR; ++ ++ /* The following parameters are used to save readings from memory */ ++ p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue); ++ command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC; ++ ++ if (command_status & (ETH_TX_FIRST_DESC)) { ++ /* Update first desc */ ++ FIRST_TFD_SET (p_tx_desc_curr, tx_queue); ++ p_tx_desc_first = p_tx_desc_curr; ++ } else { ++ FIRST_TFD_GET (p_tx_desc_first, tx_queue); ++ command_status |= ETH_BUFFER_OWNED_BY_DMA; ++ } ++ ++ /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */ ++ /* boundary. We use the memory allocated for Tx descriptor. This memory */ ++ /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */ ++ if (p_pkt_info->byte_cnt <= 8) { ++ printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */ ++ return ETH_ERROR; ++ ++ p_tx_desc_curr->buf_ptr = ++ (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC; ++ eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr, ++ p_pkt_info->byte_cnt); ++ } else ++ p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr; ++ ++ p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt; ++ p_tx_desc_curr->return_info = p_pkt_info->return_info; ++ ++ if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) { ++ /* Set last desc with DMA ownership and interrupt enable. */ ++ p_tx_desc_curr->cmd_sts = command_status | ++ ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT; ++ ++ if (p_tx_desc_curr != p_tx_desc_first) ++ p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA; ++ ++ /* Flush CPU pipe */ ++ ++ D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); ++ D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0); ++ CPU_PIPE_FLUSH; ++ ++ /* Apply send command */ ++ ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num); ++ ++ /* Finish Tx packet. Update first desc in case of Tx resource error */ ++ p_tx_desc_first = p_tx_next_desc_curr; ++ FIRST_TFD_SET (p_tx_desc_first, tx_queue); ++ ++ } else { ++ p_tx_desc_curr->cmd_sts = command_status; ++ D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); ++ } ++ ++ /* Check for ring index overlap in the Tx desc ring */ ++ if (p_tx_next_desc_curr == p_tx_desc_used) { ++ /* Update the current descriptor */ ++ CURR_TFD_SET (p_tx_desc_first, tx_queue); ++ ++ p_eth_port_ctrl->tx_resource_err[tx_queue] = true; ++ return ETH_QUEUE_LAST_RESOURCE; ++ } else { ++ /* Update the current descriptor */ ++ CURR_TFD_SET (p_tx_next_desc_curr, tx_queue); ++ return ETH_OK; ++ } ++} ++ ++/******************************************************************************* ++ * eth_tx_return_desc - Free all used Tx descriptors ++ * ++ * DESCRIPTION: ++ * This routine returns the transmitted packet information to the caller. ++ * It uses the 'first' index to support Tx desc return in case a transmit ++ * of a packet spanned over multiple buffer still in process. ++ * In case the Tx queue was in "resource error" condition, where there are ++ * no available Tx resources, the function resets the resource error flag. ++ * ++ * INPUT: ++ * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. ++ * ETH_QUEUE tx_queue Number of Tx queue. ++ * PKT_INFO *p_pkt_info User packet buffer. ++ * ++ * OUTPUT: ++ * Tx ring 'first' and 'used' indexes are updated. ++ * ++ * RETURN: ++ * ETH_ERROR in case the routine can not access Tx desc ring. ++ * ETH_RETRY in case there is transmission in process. ++ * ETH_END_OF_JOB if the routine has nothing to release. ++ * ETH_OK otherwise. ++ * ++ *******************************************************************************/ ++static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * ++ p_eth_port_ctrl, ++ ETH_QUEUE tx_queue, ++ PKT_INFO * p_pkt_info) ++{ ++ volatile ETH_TX_DESC *p_tx_desc_used = NULL; ++ volatile ETH_TX_DESC *p_tx_desc_first = NULL; ++ unsigned int command_status; ++ ++ /* Get the Tx Desc ring indexes */ ++ USED_TFD_GET (p_tx_desc_used, tx_queue); ++ FIRST_TFD_GET (p_tx_desc_first, tx_queue); ++ ++ /* Sanity check */ ++ if (p_tx_desc_used == NULL) ++ return ETH_ERROR; ++ ++ command_status = p_tx_desc_used->cmd_sts; ++ ++ /* Still transmitting... */ ++ if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { ++ D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); ++ return ETH_RETRY; ++ } ++ ++ /* Stop release. About to overlap the current available Tx descriptor */ ++ if ((p_tx_desc_used == p_tx_desc_first) && ++ (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) { ++ D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); ++ return ETH_END_OF_JOB; ++ } ++ ++ /* Pass the packet information to the caller */ ++ p_pkt_info->cmd_sts = command_status; ++ p_pkt_info->return_info = p_tx_desc_used->return_info; ++ p_tx_desc_used->return_info = 0; ++ ++ /* Update the next descriptor to release. */ ++ USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue); ++ ++ /* Any Tx return cancels the Tx resource error status */ ++ if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) ++ p_eth_port_ctrl->tx_resource_err[tx_queue] = false; ++ ++ D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); ++ ++ return ETH_OK; ++ ++} ++ ++/******************************************************************************* ++ * eth_port_receive - Get received information from Rx ring. ++ * ++ * DESCRIPTION: ++ * This routine returns the received data to the caller. There is no ++ * data copying during routine operation. All information is returned ++ * using pointer to packet information struct passed from the caller. ++ * If the routine exhausts Rx ring resources then the resource error flag ++ * is set. ++ * ++ * INPUT: ++ * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. ++ * ETH_QUEUE rx_queue Number of Rx queue. ++ * PKT_INFO *p_pkt_info User packet buffer. ++ * ++ * OUTPUT: ++ * Rx ring current and used indexes are updated. ++ * ++ * RETURN: ++ * ETH_ERROR in case the routine can not access Rx desc ring. ++ * ETH_QUEUE_FULL if Rx ring resources are exhausted. ++ * ETH_END_OF_JOB if there is no received data. ++ * ETH_OK otherwise. ++ * ++ *******************************************************************************/ ++static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, ++ ETH_QUEUE rx_queue, ++ PKT_INFO * p_pkt_info) ++{ ++ volatile ETH_RX_DESC *p_rx_curr_desc; ++ volatile ETH_RX_DESC *p_rx_next_curr_desc; ++ volatile ETH_RX_DESC *p_rx_used_desc; ++ unsigned int command_status; ++ ++ /* Do not process Rx ring in case of Rx ring resource error */ ++ if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) { ++ printf ("\nRx Queue is full ...\n"); ++ return ETH_QUEUE_FULL; ++ } ++ ++ /* Get the Rx Desc ring 'curr and 'used' indexes */ ++ CURR_RFD_GET (p_rx_curr_desc, rx_queue); ++ USED_RFD_GET (p_rx_used_desc, rx_queue); ++ ++ /* Sanity check */ ++ if (p_rx_curr_desc == NULL) ++ return ETH_ERROR; ++ ++ /* The following parameters are used to save readings from memory */ ++ p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue); ++ command_status = p_rx_curr_desc->cmd_sts; ++ ++ /* Nothing to receive... */ ++ if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { ++/* DP(printf("Rx: command_status: %08x\n", command_status)); */ ++ D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); ++/* DP(printf("\nETH_END_OF_JOB ...\n"));*/ ++ return ETH_END_OF_JOB; ++ } ++ ++ p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET; ++ p_pkt_info->cmd_sts = command_status; ++ p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET; ++ p_pkt_info->return_info = p_rx_curr_desc->return_info; ++ p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */ ++ ++ /* Clean the return info field to indicate that the packet has been */ ++ /* moved to the upper layers */ ++ p_rx_curr_desc->return_info = 0; ++ ++ /* Update 'curr' in data structure */ ++ CURR_RFD_SET (p_rx_next_curr_desc, rx_queue); ++ ++ /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */ ++ if (p_rx_next_curr_desc == p_rx_used_desc) ++ p_eth_port_ctrl->rx_resource_err[rx_queue] = true; ++ ++ D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); ++ CPU_PIPE_FLUSH; ++ ++ return ETH_OK; ++} ++ ++/******************************************************************************* ++ * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. ++ * ++ * DESCRIPTION: ++ * This routine returns a Rx buffer back to the Rx ring. It retrieves the ++ * next 'used' descriptor and attached the returned buffer to it. ++ * In case the Rx ring was in "resource error" condition, where there are ++ * no available Rx resources, the function resets the resource error flag. ++ * ++ * INPUT: ++ * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. ++ * ETH_QUEUE rx_queue Number of Rx queue. ++ * PKT_INFO *p_pkt_info Information on the returned buffer. ++ * ++ * OUTPUT: ++ * New available Rx resource in Rx descriptor ring. ++ * ++ * RETURN: ++ * ETH_ERROR in case the routine can not access Rx desc ring. ++ * ETH_OK otherwise. ++ * ++ *******************************************************************************/ ++static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO * ++ p_eth_port_ctrl, ++ ETH_QUEUE rx_queue, ++ PKT_INFO * p_pkt_info) ++{ ++ volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */ ++ ++ /* Get 'used' Rx descriptor */ ++ USED_RFD_GET (p_used_rx_desc, rx_queue); ++ ++ /* Sanity check */ ++ if (p_used_rx_desc == NULL) ++ return ETH_ERROR; ++ ++ p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; ++ p_used_rx_desc->return_info = p_pkt_info->return_info; ++ p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt; ++ p_used_rx_desc->buf_size = MV64460_RX_BUFFER_SIZE; /* Reset Buffer size */ ++ ++ /* Flush the write pipe */ ++ CPU_PIPE_FLUSH; ++ ++ /* Return the descriptor to DMA ownership */ ++ p_used_rx_desc->cmd_sts = ++ ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; ++ ++ /* Flush descriptor and CPU pipe */ ++ D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0); ++ CPU_PIPE_FLUSH; ++ ++ /* Move the used descriptor pointer to the next descriptor */ ++ USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue); ++ ++ /* Any Rx return cancels the Rx resource error status */ ++ if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) ++ p_eth_port_ctrl->rx_resource_err[rx_queue] = false; ++ ++ return ETH_OK; ++} ++ ++/******************************************************************************* ++ * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path ++ * ++ * DESCRIPTION: ++ * This routine sets the RX coalescing interrupt mechanism parameter. ++ * This parameter is a timeout counter, that counts in 64 t_clk ++ * chunks ; that when timeout event occurs a maskable interrupt ++ * occurs. ++ * The parameter is calculated using the tClk of the MV-643xx chip ++ * , and the required delay of the interrupt in usec. ++ * ++ * INPUT: ++ * ETH_PORT eth_port_num Ethernet port number ++ * unsigned int t_clk t_clk of the MV-643xx chip in HZ units ++ * unsigned int delay Delay in usec ++ * ++ * OUTPUT: ++ * Interrupt coalescing mechanism value is set in MV-643xx chip. ++ * ++ * RETURN: ++ * The interrupt coalescing value set in the gigE port. ++ * ++ *******************************************************************************/ ++#if 0 /* FIXME */ ++static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num, ++ unsigned int t_clk, ++ unsigned int delay) ++{ ++ unsigned int coal; ++ ++ coal = ((t_clk / 1000000) * delay) / 64; ++ /* Set RX Coalescing mechanism */ ++ MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num), ++ ((coal & 0x3fff) << 8) | ++ (MV_REG_READ ++ (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num)) ++ & 0xffc000ff)); ++ return coal; ++} ++ ++#endif ++/******************************************************************************* ++ * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path ++ * ++ * DESCRIPTION: ++ * This routine sets the TX coalescing interrupt mechanism parameter. ++ * This parameter is a timeout counter, that counts in 64 t_clk ++ * chunks ; that when timeout event occurs a maskable interrupt ++ * occurs. ++ * The parameter is calculated using the t_cLK frequency of the ++ * MV-643xx chip and the required delay in the interrupt in uSec ++ * ++ * INPUT: ++ * ETH_PORT eth_port_num Ethernet port number ++ * unsigned int t_clk t_clk of the MV-643xx chip in HZ units ++ * unsigned int delay Delay in uSeconds ++ * ++ * OUTPUT: ++ * Interrupt coalescing mechanism value is set in MV-643xx chip. ++ * ++ * RETURN: ++ * The interrupt coalescing value set in the gigE port. ++ * ++ *******************************************************************************/ ++#if 0 /* FIXME */ ++static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num, ++ unsigned int t_clk, ++ unsigned int delay) ++{ ++ unsigned int coal; ++ ++ coal = ((t_clk / 1000000) * delay) / 64; ++ /* Set TX Coalescing mechanism */ ++ MV_REG_WRITE (MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num), ++ coal << 4); ++ return coal; ++} ++#endif ++ ++/******************************************************************************* ++ * eth_b_copy - Copy bytes from source to destination ++ * ++ * DESCRIPTION: ++ * This function supports the eight bytes limitation on Tx buffer size. ++ * The routine will zero eight bytes starting from the destination address ++ * followed by copying bytes from the source address to the destination. ++ * ++ * INPUT: ++ * unsigned int src_addr 32 bit source address. ++ * unsigned int dst_addr 32 bit destination address. ++ * int byte_count Number of bytes to copy. ++ * ++ * OUTPUT: ++ * See description. ++ * ++ * RETURN: ++ * None. ++ * ++ *******************************************************************************/ ++static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, ++ int byte_count) ++{ ++ /* Zero the dst_addr area */ ++ *(unsigned int *) dst_addr = 0x0; ++ ++ while (byte_count != 0) { ++ *(char *) dst_addr = *(char *) src_addr; ++ dst_addr++; ++ src_addr++; ++ byte_count--; ++ } ++} +diff -Naupr u-boot-1.1.6/board/prodrive/p3mx/mv_eth.h u-boot-1.1.6-fsl-1/board/prodrive/p3mx/mv_eth.h +--- u-boot-1.1.6/board/prodrive/p3mx/mv_eth.h 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/p3mx/mv_eth.h 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,840 @@ ++/* ++ * (C) Copyright 2003 ++ * Ingo Assmus ++ * ++ * based on - Driver for MV64460X ethernet ports ++ * Copyright (C) 2002 rabeeh@galileo.co.il ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* ++ * mv_eth.h - header file for the polled mode GT ethernet driver ++ */ ++ ++#ifndef __DB64460_ETH_H__ ++#define __DB64460_ETH_H__ ++ ++#include ++#include ++#include ++#include ++#include ++#include "mv_regs.h" ++#include "ppc_error_no.h" ++#include "../../Marvell/include/core.h" ++ ++/************************************************************************* ++************************************************************************** ++************************************************************************** ++* The first part is the high level driver of the gigE ethernet ports. * ++************************************************************************** ++************************************************************************** ++*************************************************************************/ ++#ifndef TRUE ++#define TRUE 1 ++#endif ++#ifndef FALSE ++#define FALSE 0 ++#endif ++ ++/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */ ++#ifndef MAX_SKB_FRAGS ++#define MAX_SKB_FRAGS 0 ++#endif ++ ++/* Port attributes */ ++/*#define MAX_RX_QUEUE_NUM 8*/ ++/*#define MAX_TX_QUEUE_NUM 8*/ ++#define MAX_RX_QUEUE_NUM 1 ++#define MAX_TX_QUEUE_NUM 1 ++ ++ ++/* Use one TX queue and one RX queue */ ++#define MV64460_TX_QUEUE_NUM 1 ++#define MV64460_RX_QUEUE_NUM 1 ++ ++/* ++ * Number of RX / TX descriptors on RX / TX rings. ++ * Note that allocating RX descriptors is done by allocating the RX ++ * ring AND a preallocated RX buffers (skb's) for each descriptor. ++ * The TX descriptors only allocates the TX descriptors ring, ++ * with no pre allocated TX buffers (skb's are allocated by higher layers. ++ */ ++ ++/* Default TX ring size is 10 descriptors */ ++#ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE ++#define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE ++#else ++#define MV64460_TX_QUEUE_SIZE 4 ++#endif ++ ++/* Default RX ring size is 4 descriptors */ ++#ifdef CONFIG_MV64460_ETH_RXQUEUE_SIZE ++#define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE ++#else ++#define MV64460_RX_QUEUE_SIZE 4 ++#endif ++ ++#ifdef CONFIG_RX_BUFFER_SIZE ++#define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE ++#else ++#define MV64460_RX_BUFFER_SIZE 1600 ++#endif ++ ++#ifdef CONFIG_TX_BUFFER_SIZE ++#define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE ++#else ++#define MV64460_TX_BUFFER_SIZE 1600 ++#endif ++ ++/* ++ * Network device statistics. Akin to the 2.0 ether stats but ++ * with byte counters. ++ */ ++ ++struct net_device_stats ++{ ++ unsigned long rx_packets; /* total packets received */ ++ unsigned long tx_packets; /* total packets transmitted */ ++ unsigned long rx_bytes; /* total bytes received */ ++ unsigned long tx_bytes; /* total bytes transmitted */ ++ unsigned long rx_errors; /* bad packets received */ ++ unsigned long tx_errors; /* packet transmit problems */ ++ unsigned long rx_dropped; /* no space in linux buffers */ ++ unsigned long tx_dropped; /* no space available in linux */ ++ unsigned long multicast; /* multicast packets received */ ++ unsigned long collisions; ++ ++ /* detailed rx_errors: */ ++ unsigned long rx_length_errors; ++ unsigned long rx_over_errors; /* receiver ring buff overflow */ ++ unsigned long rx_crc_errors; /* recved pkt with crc error */ ++ unsigned long rx_frame_errors; /* recv'd frame alignment error */ ++ unsigned long rx_fifo_errors; /* recv'r fifo overrun */ ++ unsigned long rx_missed_errors; /* receiver missed packet */ ++ ++ /* detailed tx_errors */ ++ unsigned long tx_aborted_errors; ++ unsigned long tx_carrier_errors; ++ unsigned long tx_fifo_errors; ++ unsigned long tx_heartbeat_errors; ++ unsigned long tx_window_errors; ++ ++ /* for cslip etc */ ++ unsigned long rx_compressed; ++ unsigned long tx_compressed; ++}; ++ ++ ++/* Private data structure used for ethernet device */ ++struct mv64460_eth_priv { ++ unsigned int port_num; ++ struct net_device_stats *stats; ++ ++ /* to buffer area aligned */ ++ char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */ ++ char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */ ++ ++ /* Size of Tx Ring per queue */ ++ unsigned int tx_ring_size [MAX_TX_QUEUE_NUM]; ++ ++ /* Size of Rx Ring per queue */ ++ unsigned int rx_ring_size [MAX_RX_QUEUE_NUM]; ++ ++ /* Magic Number for Ethernet running */ ++ unsigned int eth_running; ++ ++ int first_init; ++}; ++ ++int mv64460_eth_init (struct eth_device *dev); ++int mv64460_eth_stop (struct eth_device *dev); ++int mv64460_eth_start_xmit (struct eth_device*, volatile void* packet, int length); ++/* return db64460_eth0_poll(); */ ++ ++int mv64460_eth_open (struct eth_device *dev); ++ ++ ++/************************************************************************* ++************************************************************************** ++************************************************************************** ++* The second part is the low level driver of the gigE ethernet ports. * ++************************************************************************** ++************************************************************************** ++*************************************************************************/ ++ ++ ++/******************************************************************************** ++ * Header File for : MV-643xx network interface header ++ * ++ * DESCRIPTION: ++ * This header file contains macros typedefs and function declaration for ++ * the Marvell Gig Bit Ethernet Controller. ++ * ++ * DEPENDENCIES: ++ * None. ++ * ++ *******************************************************************************/ ++ ++ ++#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY ++#ifdef CONFIG_MV64460_SRAM_CACHEABLE ++/* In case SRAM is cacheable but not cache coherent */ ++#define D_CACHE_FLUSH_LINE(addr, offset) \ ++{ \ ++ __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ ++} ++#else ++/* In case SRAM is cache coherent or non-cacheable */ ++#define D_CACHE_FLUSH_LINE(addr, offset) ; ++#endif ++#else ++#ifdef CONFIG_NOT_COHERENT_CACHE ++/* In case of descriptors on DDR but not cache coherent */ ++#define D_CACHE_FLUSH_LINE(addr, offset) \ ++{ \ ++ __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ ++} ++#else ++/* In case of descriptors on DDR and cache coherent */ ++#define D_CACHE_FLUSH_LINE(addr, offset) ; ++#endif /* CONFIG_NOT_COHERENT_CACHE */ ++#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */ ++ ++ ++#define CPU_PIPE_FLUSH \ ++{ \ ++ __asm__ __volatile__ ("eieio"); \ ++} ++ ++ ++/* defines */ ++ ++/* Default port configuration value */ ++#define PORT_CONFIG_VALUE \ ++ ETH_UNICAST_NORMAL_MODE | \ ++ ETH_DEFAULT_RX_QUEUE_0 | \ ++ ETH_DEFAULT_RX_ARP_QUEUE_0 | \ ++ ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ ++ ETH_RECEIVE_BC_IF_IP | \ ++ ETH_RECEIVE_BC_IF_ARP | \ ++ ETH_CAPTURE_TCP_FRAMES_DIS | \ ++ ETH_CAPTURE_UDP_FRAMES_DIS | \ ++ ETH_DEFAULT_RX_TCP_QUEUE_0 | \ ++ ETH_DEFAULT_RX_UDP_QUEUE_0 | \ ++ ETH_DEFAULT_RX_BPDU_QUEUE_0 ++ ++/* Default port extend configuration value */ ++#define PORT_CONFIG_EXTEND_VALUE \ ++ ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ ++ ETH_PARTITION_DISABLE ++ ++ ++/* Default sdma control value */ ++#ifdef CONFIG_NOT_COHERENT_CACHE ++#define PORT_SDMA_CONFIG_VALUE \ ++ ETH_RX_BURST_SIZE_16_64BIT | \ ++ GT_ETH_IPG_INT_RX(0) | \ ++ ETH_TX_BURST_SIZE_16_64BIT; ++#else ++#define PORT_SDMA_CONFIG_VALUE \ ++ ETH_RX_BURST_SIZE_4_64BIT | \ ++ GT_ETH_IPG_INT_RX(0) | \ ++ ETH_TX_BURST_SIZE_4_64BIT; ++#endif ++ ++#define GT_ETH_IPG_INT_RX(value) \ ++ ((value & 0x3fff) << 8) ++ ++/* Default port serial control value */ ++#define PORT_SERIAL_CONTROL_VALUE \ ++ ETH_FORCE_LINK_PASS | \ ++ ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ ++ ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ ++ ETH_ADV_SYMMETRIC_FLOW_CTRL | \ ++ ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ ++ ETH_FORCE_BP_MODE_NO_JAM | \ ++ BIT9 | \ ++ ETH_DO_NOT_FORCE_LINK_FAIL | \ ++ ETH_RETRANSMIT_16_ETTEMPTS | \ ++ ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ ++ ETH_DTE_ADV_0 | \ ++ ETH_DISABLE_AUTO_NEG_BYPASS | \ ++ ETH_AUTO_NEG_NO_CHANGE | \ ++ ETH_MAX_RX_PACKET_1552BYTE | \ ++ ETH_CLR_EXT_LOOPBACK | \ ++ ETH_SET_FULL_DUPLEX_MODE | \ ++ ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX; ++ ++#define RX_BUFFER_MAX_SIZE 0xFFFF ++#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */ ++ ++#define RX_BUFFER_MIN_SIZE 0x8 ++#define TX_BUFFER_MIN_SIZE 0x8 ++ ++/* Tx WRR confoguration macros */ ++#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ ++#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */ ++#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */ ++ ++/* MAC accepet/reject macros */ ++#define ACCEPT_MAC_ADDR 0 ++#define REJECT_MAC_ADDR 1 ++ ++/* Size of a Tx/Rx descriptor used in chain list data structure */ ++#define RX_DESC_ALIGNED_SIZE 0x20 ++#define TX_DESC_ALIGNED_SIZE 0x20 ++ ++/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ ++#define TX_BUF_OFFSET_IN_DESC 0x18 ++/* Buffer offset from buffer pointer */ ++#define RX_BUF_OFFSET 0x2 ++ ++/* Gap define */ ++#define ETH_BAR_GAP 0x8 ++#define ETH_SIZE_REG_GAP 0x8 ++#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4 ++#define ETH_PORT_ACCESS_CTRL_GAP 0x4 ++ ++/* Gigabit Ethernet Unit Global Registers */ ++ ++/* MIB Counters register definitions */ ++#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 ++#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 ++#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 ++#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc ++#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 ++#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 ++#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 ++#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c ++#define ETH_MIB_FRAMES_64_OCTETS 0x20 ++#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 ++#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 ++#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c ++#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 ++#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 ++#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 ++#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c ++#define ETH_MIB_GOOD_FRAMES_SENT 0x40 ++#define ETH_MIB_EXCESSIVE_COLLISION 0x44 ++#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 ++#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c ++#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 ++#define ETH_MIB_FC_SENT 0x54 ++#define ETH_MIB_GOOD_FC_RECEIVED 0x58 ++#define ETH_MIB_BAD_FC_RECEIVED 0x5c ++#define ETH_MIB_UNDERSIZE_RECEIVED 0x60 ++#define ETH_MIB_FRAGMENTS_RECEIVED 0x64 ++#define ETH_MIB_OVERSIZE_RECEIVED 0x68 ++#define ETH_MIB_JABBER_RECEIVED 0x6c ++#define ETH_MIB_MAC_RECEIVE_ERROR 0x70 ++#define ETH_MIB_BAD_CRC_EVENT 0x74 ++#define ETH_MIB_COLLISION 0x78 ++#define ETH_MIB_LATE_COLLISION 0x7c ++ ++/* Port serial status reg (PSR) */ ++#define ETH_INTERFACE_GMII_MII 0 ++#define ETH_INTERFACE_PCM BIT0 ++#define ETH_LINK_IS_DOWN 0 ++#define ETH_LINK_IS_UP BIT1 ++#define ETH_PORT_AT_HALF_DUPLEX 0 ++#define ETH_PORT_AT_FULL_DUPLEX BIT2 ++#define ETH_RX_FLOW_CTRL_DISABLED 0 ++#define ETH_RX_FLOW_CTRL_ENBALED BIT3 ++#define ETH_GMII_SPEED_100_10 0 ++#define ETH_GMII_SPEED_1000 BIT4 ++#define ETH_MII_SPEED_10 0 ++#define ETH_MII_SPEED_100 BIT5 ++#define ETH_NO_TX 0 ++#define ETH_TX_IN_PROGRESS BIT7 ++#define ETH_BYPASS_NO_ACTIVE 0 ++#define ETH_BYPASS_ACTIVE BIT8 ++#define ETH_PORT_NOT_AT_PARTITION_STATE 0 ++#define ETH_PORT_AT_PARTITION_STATE BIT9 ++#define ETH_PORT_TX_FIFO_NOT_EMPTY 0 ++#define ETH_PORT_TX_FIFO_EMPTY BIT10 ++ ++ ++/* These macros describes the Port configuration reg (Px_cR) bits */ ++#define ETH_UNICAST_NORMAL_MODE 0 ++#define ETH_UNICAST_PROMISCUOUS_MODE BIT0 ++#define ETH_DEFAULT_RX_QUEUE_0 0 ++#define ETH_DEFAULT_RX_QUEUE_1 BIT1 ++#define ETH_DEFAULT_RX_QUEUE_2 BIT2 ++#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1) ++#define ETH_DEFAULT_RX_QUEUE_4 BIT3 ++#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1) ++#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2) ++#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1) ++#define ETH_DEFAULT_RX_ARP_QUEUE_0 0 ++#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4 ++#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5 ++#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4) ++#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6 ++#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4) ++#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5) ++#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4) ++#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0 ++#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7 ++#define ETH_RECEIVE_BC_IF_IP 0 ++#define ETH_REJECT_BC_IF_IP BIT8 ++#define ETH_RECEIVE_BC_IF_ARP 0 ++#define ETH_REJECT_BC_IF_ARP BIT9 ++#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12 ++#define ETH_CAPTURE_TCP_FRAMES_DIS 0 ++#define ETH_CAPTURE_TCP_FRAMES_EN BIT14 ++#define ETH_CAPTURE_UDP_FRAMES_DIS 0 ++#define ETH_CAPTURE_UDP_FRAMES_EN BIT15 ++#define ETH_DEFAULT_RX_TCP_QUEUE_0 0 ++#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16 ++#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17 ++#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16) ++#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18 ++#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16) ++#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17) ++#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16) ++#define ETH_DEFAULT_RX_UDP_QUEUE_0 0 ++#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19 ++#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20 ++#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19) ++#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21 ++#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19) ++#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20) ++#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19) ++#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0 ++#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22 ++#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23 ++#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22) ++#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24 ++#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22) ++#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23) ++#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22) ++ ++ ++/* These macros describes the Port configuration extend reg (Px_cXR) bits*/ ++#define ETH_CLASSIFY_EN BIT0 ++#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0 ++#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1 ++#define ETH_PARTITION_DISABLE 0 ++#define ETH_PARTITION_ENABLE BIT2 ++ ++ ++/* Tx/Rx queue command reg (RQCR/TQCR)*/ ++#define ETH_QUEUE_0_ENABLE BIT0 ++#define ETH_QUEUE_1_ENABLE BIT1 ++#define ETH_QUEUE_2_ENABLE BIT2 ++#define ETH_QUEUE_3_ENABLE BIT3 ++#define ETH_QUEUE_4_ENABLE BIT4 ++#define ETH_QUEUE_5_ENABLE BIT5 ++#define ETH_QUEUE_6_ENABLE BIT6 ++#define ETH_QUEUE_7_ENABLE BIT7 ++#define ETH_QUEUE_0_DISABLE BIT8 ++#define ETH_QUEUE_1_DISABLE BIT9 ++#define ETH_QUEUE_2_DISABLE BIT10 ++#define ETH_QUEUE_3_DISABLE BIT11 ++#define ETH_QUEUE_4_DISABLE BIT12 ++#define ETH_QUEUE_5_DISABLE BIT13 ++#define ETH_QUEUE_6_DISABLE BIT14 ++#define ETH_QUEUE_7_DISABLE BIT15 ++ ++/* These macros describes the Port Sdma configuration reg (SDCR) bits */ ++#define ETH_RIFB BIT0 ++#define ETH_RX_BURST_SIZE_1_64BIT 0 ++#define ETH_RX_BURST_SIZE_2_64BIT BIT1 ++#define ETH_RX_BURST_SIZE_4_64BIT BIT2 ++#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1) ++#define ETH_RX_BURST_SIZE_16_64BIT BIT3 ++#define ETH_BLM_RX_NO_SWAP BIT4 ++#define ETH_BLM_RX_BYTE_SWAP 0 ++#define ETH_BLM_TX_NO_SWAP BIT5 ++#define ETH_BLM_TX_BYTE_SWAP 0 ++#define ETH_DESCRIPTORS_BYTE_SWAP BIT6 ++#define ETH_DESCRIPTORS_NO_SWAP 0 ++#define ETH_TX_BURST_SIZE_1_64BIT 0 ++#define ETH_TX_BURST_SIZE_2_64BIT BIT22 ++#define ETH_TX_BURST_SIZE_4_64BIT BIT23 ++#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22) ++#define ETH_TX_BURST_SIZE_16_64BIT BIT24 ++ ++/* These macros describes the Port serial control reg (PSCR) bits */ ++#define ETH_SERIAL_PORT_DISABLE 0 ++#define ETH_SERIAL_PORT_ENABLE BIT0 ++#define ETH_FORCE_LINK_PASS BIT1 ++#define ETH_DO_NOT_FORCE_LINK_PASS 0 ++#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0 ++#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2 ++#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0 ++#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3 ++#define ETH_ADV_NO_FLOW_CTRL 0 ++#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4 ++#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 ++#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5 ++#define ETH_FORCE_BP_MODE_NO_JAM 0 ++#define ETH_FORCE_BP_MODE_JAM_TX BIT7 ++#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8 ++#define ETH_FORCE_LINK_FAIL 0 ++#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10 ++#define ETH_RETRANSMIT_16_ETTEMPTS 0 ++#define ETH_RETRANSMIT_FOREVER BIT11 ++#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13 ++#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0 ++#define ETH_DTE_ADV_0 0 ++#define ETH_DTE_ADV_1 BIT14 ++#define ETH_DISABLE_AUTO_NEG_BYPASS 0 ++#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15 ++#define ETH_AUTO_NEG_NO_CHANGE 0 ++#define ETH_RESTART_AUTO_NEG BIT16 ++#define ETH_MAX_RX_PACKET_1518BYTE 0 ++#define ETH_MAX_RX_PACKET_1522BYTE BIT17 ++#define ETH_MAX_RX_PACKET_1552BYTE BIT18 ++#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17) ++#define ETH_MAX_RX_PACKET_9192BYTE BIT19 ++#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17) ++#define ETH_SET_EXT_LOOPBACK BIT20 ++#define ETH_CLR_EXT_LOOPBACK 0 ++#define ETH_SET_FULL_DUPLEX_MODE BIT21 ++#define ETH_SET_HALF_DUPLEX_MODE 0 ++#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22 ++#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 ++#define ETH_SET_GMII_SPEED_TO_10_100 0 ++#define ETH_SET_GMII_SPEED_TO_1000 BIT23 ++#define ETH_SET_MII_SPEED_TO_10 0 ++#define ETH_SET_MII_SPEED_TO_100 BIT24 ++ ++ ++/* SMI reg */ ++#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */ ++#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */ ++#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */ ++#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */ ++ ++/* SDMA command status fields macros */ ++ ++/* Tx & Rx descriptors status */ ++#define ETH_ERROR_SUMMARY (BIT0) ++ ++/* Tx & Rx descriptors command */ ++#define ETH_BUFFER_OWNED_BY_DMA (BIT31) ++ ++/* Tx descriptors status */ ++#define ETH_LC_ERROR (0 ) ++#define ETH_UR_ERROR (BIT1 ) ++#define ETH_RL_ERROR (BIT2 ) ++#define ETH_LLC_SNAP_FORMAT (BIT9 ) ++ ++/* Rx descriptors status */ ++#define ETH_CRC_ERROR (0 ) ++#define ETH_OVERRUN_ERROR (BIT1 ) ++#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 ) ++#define ETH_RESOURCE_ERROR ((BIT2 | BIT1)) ++#define ETH_VLAN_TAGGED (BIT19) ++#define ETH_BPDU_FRAME (BIT20) ++#define ETH_TCP_FRAME_OVER_IP_V_4 (0 ) ++#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21) ++#define ETH_OTHER_FRAME_TYPE (BIT22) ++#define ETH_LAYER_2_IS_ETH_V_2 (BIT23) ++#define ETH_FRAME_TYPE_IP_V_4 (BIT24) ++#define ETH_FRAME_HEADER_OK (BIT25) ++#define ETH_RX_LAST_DESC (BIT26) ++#define ETH_RX_FIRST_DESC (BIT27) ++#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28) ++#define ETH_RX_ENABLE_INTERRUPT (BIT29) ++#define ETH_LAYER_4_CHECKSUM_OK (BIT30) ++ ++/* Rx descriptors byte count */ ++#define ETH_FRAME_FRAGMENTED (BIT2) ++ ++/* Tx descriptors command */ ++#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10) ++#define ETH_FRAME_SET_TO_VLAN (BIT15) ++#define ETH_TCP_FRAME (0 ) ++#define ETH_UDP_FRAME (BIT16) ++#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17) ++#define ETH_GEN_IP_V_4_CHECKSUM (BIT18) ++#define ETH_ZERO_PADDING (BIT19) ++#define ETH_TX_LAST_DESC (BIT20) ++#define ETH_TX_FIRST_DESC (BIT21) ++#define ETH_GEN_CRC (BIT22) ++#define ETH_TX_ENABLE_INTERRUPT (BIT23) ++#define ETH_AUTO_MODE (BIT30) ++ ++/* Address decode parameters */ ++/* Ethernet Base Address Register bits */ ++#define EBAR_TARGET_DRAM 0x00000000 ++#define EBAR_TARGET_DEVICE 0x00000001 ++#define EBAR_TARGET_CBS 0x00000002 ++#define EBAR_TARGET_PCI0 0x00000003 ++#define EBAR_TARGET_PCI1 0x00000004 ++#define EBAR_TARGET_CUNIT 0x00000005 ++#define EBAR_TARGET_AUNIT 0x00000006 ++#define EBAR_TARGET_GUNIT 0x00000007 ++ ++/* Window attributes */ ++#define EBAR_ATTR_DRAM_CS0 0x00000E00 ++#define EBAR_ATTR_DRAM_CS1 0x00000D00 ++#define EBAR_ATTR_DRAM_CS2 0x00000B00 ++#define EBAR_ATTR_DRAM_CS3 0x00000700 ++ ++/* DRAM Target interface */ ++#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000 ++#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000 ++#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000 ++ ++/* Device Bus Target interface */ ++#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00 ++#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00 ++#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00 ++#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700 ++#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00 ++ ++/* PCI Target interface */ ++#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000 ++#define EBAR_ATTR_PCI_NO_SWAP 0x00000100 ++#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200 ++#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300 ++#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000 ++#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400 ++#define EBAR_ATTR_PCI_IO_SPACE 0x00000000 ++#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800 ++#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000 ++#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000 ++ ++/* CPU 60x bus or internal SRAM interface */ ++#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000 ++#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100 ++#define EBAR_ATTR_CBS_SRAM 0x00000000 ++#define EBAR_ATTR_CBS_CPU_BUS 0x00000800 ++ ++/* Window access control */ ++#define EWIN_ACCESS_NOT_ALLOWED 0 ++#define EWIN_ACCESS_READ_ONLY BIT0 ++#define EWIN_ACCESS_FULL (BIT1 | BIT0) ++#define EWIN0_ACCESS_MASK 0x0003 ++#define EWIN1_ACCESS_MASK 0x000C ++#define EWIN2_ACCESS_MASK 0x0030 ++#define EWIN3_ACCESS_MASK 0x00C0 ++ ++/* typedefs */ ++ ++typedef enum _eth_port ++{ ++ ETH_0 = 0, ++ ETH_1 = 1, ++ ETH_2 = 2 ++}ETH_PORT; ++ ++typedef enum _eth_func_ret_status ++{ ++ ETH_OK, /* Returned as expected. */ ++ ETH_ERROR, /* Fundamental error. */ ++ ETH_RETRY, /* Could not process request. Try later. */ ++ ETH_END_OF_JOB, /* Ring has nothing to process. */ ++ ETH_QUEUE_FULL, /* Ring resource error. */ ++ ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ ++}ETH_FUNC_RET_STATUS; ++ ++typedef enum _eth_queue ++{ ++ ETH_Q0 = 0, ++ ETH_Q1 = 1, ++ ETH_Q2 = 2, ++ ETH_Q3 = 3, ++ ETH_Q4 = 4, ++ ETH_Q5 = 5, ++ ETH_Q6 = 6, ++ ETH_Q7 = 7 ++} ETH_QUEUE; ++ ++typedef enum _addr_win ++{ ++ ETH_WIN0, ++ ETH_WIN1, ++ ETH_WIN2, ++ ETH_WIN3, ++ ETH_WIN4, ++ ETH_WIN5 ++} ETH_ADDR_WIN; ++ ++typedef enum _eth_target ++{ ++ ETH_TARGET_DRAM , ++ ETH_TARGET_DEVICE, ++ ETH_TARGET_CBS , ++ ETH_TARGET_PCI0 , ++ ETH_TARGET_PCI1 ++}ETH_TARGET; ++ ++typedef struct _eth_rx_desc ++{ ++ unsigned short byte_cnt ; /* Descriptor buffer byte count */ ++ unsigned short buf_size ; /* Buffer size */ ++ unsigned int cmd_sts ; /* Descriptor command status */ ++ unsigned int next_desc_ptr; /* Next descriptor pointer */ ++ unsigned int buf_ptr ; /* Descriptor buffer pointer */ ++ unsigned int return_info ; /* User resource return information */ ++} ETH_RX_DESC; ++ ++ ++typedef struct _eth_tx_desc ++{ ++ unsigned short byte_cnt ; /* Descriptor buffer byte count */ ++ unsigned short l4i_chk ; /* CPU provided TCP Checksum */ ++ unsigned int cmd_sts ; /* Descriptor command status */ ++ unsigned int next_desc_ptr; /* Next descriptor pointer */ ++ unsigned int buf_ptr ; /* Descriptor buffer pointer */ ++ unsigned int return_info ; /* User resource return information */ ++} ETH_TX_DESC; ++ ++/* Unified struct for Rx and Tx operations. The user is not required to */ ++/* be familier with neither Tx nor Rx descriptors. */ ++typedef struct _pkt_info ++{ ++ unsigned short byte_cnt ; /* Descriptor buffer byte count */ ++ unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */ ++ unsigned int cmd_sts ; /* Descriptor command status */ ++ unsigned int buf_ptr ; /* Descriptor buffer pointer */ ++ unsigned int return_info ; /* User resource return information */ ++} PKT_INFO; ++ ++ ++typedef struct _eth_win_param ++{ ++ ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */ ++ ETH_TARGET target; /* System targets. See ETH_TARGET enum */ ++ unsigned short attributes; /* BAR attributes. See above macros. */ ++ unsigned int base_addr; /* Window base address in unsigned int form */ ++ unsigned int high_addr; /* Window high address in unsigned int form */ ++ unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */ ++ bool enable; /* Enable/disable access to the window. */ ++ unsigned short access_ctrl; /* Access ctrl register. see above macros */ ++} ETH_WIN_PARAM; ++ ++ ++/* Ethernet port specific infomation */ ++ ++typedef struct _eth_port_ctrl ++{ ++ ETH_PORT port_num; /* User Ethernet port number */ ++ int port_phy_addr; /* User phy address of Ethrnet port */ ++ unsigned char port_mac_addr[6]; /* User defined port MAC address. */ ++ unsigned int port_config; /* User port configuration value */ ++ unsigned int port_config_extend; /* User port config extend value */ ++ unsigned int port_sdma_config; /* User port SDMA config value */ ++ unsigned int port_serial_control; /* User port serial control value */ ++ unsigned int port_tx_queue_command; /* Port active Tx queues summary */ ++ unsigned int port_rx_queue_command; /* Port active Rx queues summary */ ++ ++ /* User function to cast virtual address to CPU bus address */ ++ unsigned int (*port_virt_to_phys)(unsigned int addr); ++ /* User scratch pad for user specific data structures */ ++ void *port_private; ++ ++ bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */ ++ bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */ ++ ++ /* Tx/Rx rings managment indexes fields. For driver use */ ++ ++ /* Next available Rx resource */ ++ volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM]; ++ /* Returning Rx resource */ ++ volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM]; ++ ++ /* Next available Tx resource */ ++ volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM]; ++ /* Returning Tx resource */ ++ volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM]; ++ /* An extra Tx index to support transmit of multiple buffers per packet */ ++ volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM]; ++ ++ /* Tx/Rx rings size and base variables fields. For driver use */ ++ ++ volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM]; ++ unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM]; ++ char *p_rx_buffer_base[MAX_RX_QUEUE_NUM]; ++ ++ volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM]; ++ unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM]; ++ char *p_tx_buffer_base[MAX_TX_QUEUE_NUM]; ++ ++} ETH_PORT_INFO; ++ ++ ++/* ethernet.h API list */ ++ ++/* Port operation control routines */ ++static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl); ++static void eth_port_reset(ETH_PORT eth_port_num); ++static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl); ++ ++ ++/* Port MAC address routines */ ++static void eth_port_uc_addr_set (ETH_PORT eth_port_num, ++ unsigned char *p_addr, ++ ETH_QUEUE queue); ++#if 0 /* FIXME */ ++static void eth_port_mc_addr (ETH_PORT eth_port_num, ++ unsigned char *p_addr, ++ ETH_QUEUE queue, ++ int option); ++#endif ++ ++/* PHY and MIB routines */ ++static bool ethernet_phy_reset(ETH_PORT eth_port_num); ++ ++static bool eth_port_write_smi_reg(ETH_PORT eth_port_num, ++ unsigned int phy_reg, ++ unsigned int value); ++ ++static bool eth_port_read_smi_reg(ETH_PORT eth_port_num, ++ unsigned int phy_reg, ++ unsigned int* value); ++ ++static void eth_clear_mib_counters(ETH_PORT eth_port_num); ++ ++/* Port data flow control routines */ ++static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl, ++ ETH_QUEUE tx_queue, ++ PKT_INFO *p_pkt_info); ++static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl, ++ ETH_QUEUE tx_queue, ++ PKT_INFO *p_pkt_info); ++static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl, ++ ETH_QUEUE rx_queue, ++ PKT_INFO *p_pkt_info); ++static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl, ++ ETH_QUEUE rx_queue, ++ PKT_INFO *p_pkt_info); ++ ++ ++static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, ++ ETH_QUEUE tx_queue, ++ int tx_desc_num, ++ int tx_buff_size, ++ unsigned int tx_desc_base_addr, ++ unsigned int tx_buff_base_addr); ++ ++static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl, ++ ETH_QUEUE rx_queue, ++ int rx_desc_num, ++ int rx_buff_size, ++ unsigned int rx_desc_base_addr, ++ unsigned int rx_buff_base_addr); ++ ++#endif /* MV64460_ETH_ */ +diff -Naupr u-boot-1.1.6/board/prodrive/p3mx/mv_regs.h u-boot-1.1.6-fsl-1/board/prodrive/p3mx/mv_regs.h +--- u-boot-1.1.6/board/prodrive/p3mx/mv_regs.h 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/p3mx/mv_regs.h 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,1125 @@ ++/* ++ * (C) Copyright 2003 ++ * Ingo Assmus ++ * ++ * based on - Driver for MV64460X ethernet ports ++ * Copyright (C) 2002 rabeeh@galileo.co.il ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/******************************************************************************** ++* gt64460r.h - GT-64460 Internal registers definition file. ++* ++* DESCRIPTION: ++* None. ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++#ifndef __INCmv_regsh ++#define __INCmv_regsh ++ ++#define MV64460 ++ ++/* Supported by the Atlantis */ ++#define MV64460_INCLUDE_PCI_1 ++#define MV64460_INCLUDE_PCI_0_ARBITER ++#define MV64460_INCLUDE_PCI_1_ARBITER ++#define MV64460_INCLUDE_SNOOP_SUPPORT ++#define MV64460_INCLUDE_P2P ++#define MV64460_INCLUDE_ETH_PORT_2 ++#define MV64460_INCLUDE_CPU_MAPPING ++#define MV64460_INCLUDE_MPSC ++ ++/* Not supported features */ ++#undef INCLUDE_CNTMR_4_7 ++#undef INCLUDE_DMA_4_7 ++ ++/****************************************/ ++/* Processor Address Space */ ++/****************************************/ ++ ++/* DDR SDRAM BAR and size registers */ ++ ++#define MV64460_CS_0_BASE_ADDR 0x008 ++#define MV64460_CS_0_SIZE 0x010 ++#define MV64460_CS_1_BASE_ADDR 0x208 ++#define MV64460_CS_1_SIZE 0x210 ++#define MV64460_CS_2_BASE_ADDR 0x018 ++#define MV64460_CS_2_SIZE 0x020 ++#define MV64460_CS_3_BASE_ADDR 0x218 ++#define MV64460_CS_3_SIZE 0x220 ++ ++/* Devices BAR and size registers */ ++ ++#define MV64460_DEV_CS0_BASE_ADDR 0x028 ++#define MV64460_DEV_CS0_SIZE 0x030 ++#define MV64460_DEV_CS1_BASE_ADDR 0x228 ++#define MV64460_DEV_CS1_SIZE 0x230 ++#define MV64460_DEV_CS2_BASE_ADDR 0x248 ++#define MV64460_DEV_CS2_SIZE 0x250 ++#define MV64460_DEV_CS3_BASE_ADDR 0x038 ++#define MV64460_DEV_CS3_SIZE 0x040 ++#define MV64460_BOOTCS_BASE_ADDR 0x238 ++#define MV64460_BOOTCS_SIZE 0x240 ++ ++/* PCI 0 BAR and size registers */ ++ ++#define MV64460_PCI_0_IO_BASE_ADDR 0x048 ++#define MV64460_PCI_0_IO_SIZE 0x050 ++#define MV64460_PCI_0_MEMORY0_BASE_ADDR 0x058 ++#define MV64460_PCI_0_MEMORY0_SIZE 0x060 ++#define MV64460_PCI_0_MEMORY1_BASE_ADDR 0x080 ++#define MV64460_PCI_0_MEMORY1_SIZE 0x088 ++#define MV64460_PCI_0_MEMORY2_BASE_ADDR 0x258 ++#define MV64460_PCI_0_MEMORY2_SIZE 0x260 ++#define MV64460_PCI_0_MEMORY3_BASE_ADDR 0x280 ++#define MV64460_PCI_0_MEMORY3_SIZE 0x288 ++ ++/* PCI 1 BAR and size registers */ ++#define MV64460_PCI_1_IO_BASE_ADDR 0x090 ++#define MV64460_PCI_1_IO_SIZE 0x098 ++#define MV64460_PCI_1_MEMORY0_BASE_ADDR 0x0a0 ++#define MV64460_PCI_1_MEMORY0_SIZE 0x0a8 ++#define MV64460_PCI_1_MEMORY1_BASE_ADDR 0x0b0 ++#define MV64460_PCI_1_MEMORY1_SIZE 0x0b8 ++#define MV64460_PCI_1_MEMORY2_BASE_ADDR 0x2a0 ++#define MV64460_PCI_1_MEMORY2_SIZE 0x2a8 ++#define MV64460_PCI_1_MEMORY3_BASE_ADDR 0x2b0 ++#define MV64460_PCI_1_MEMORY3_SIZE 0x2b8 ++ ++/* SRAM base address */ ++#define MV64460_INTEGRATED_SRAM_BASE_ADDR 0x268 ++ ++/* internal registers space base address */ ++#define MV64460_INTERNAL_SPACE_BASE_ADDR 0x068 ++ ++/* Enables the CS , DEV_CS , PCI 0 and PCI 1 ++ windows above */ ++#define MV64460_BASE_ADDR_ENABLE 0x278 ++ ++/****************************************/ ++/* PCI remap registers */ ++/****************************************/ ++ /* PCI 0 */ ++#define MV64460_PCI_0_IO_ADDR_REMAP 0x0f0 ++#define MV64460_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8 ++#define MV64460_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320 ++#define MV64460_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100 ++#define MV64460_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328 ++#define MV64460_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8 ++#define MV64460_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330 ++#define MV64460_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300 ++#define MV64460_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338 ++ /* PCI 1 */ ++#define MV64460_PCI_1_IO_ADDR_REMAP 0x108 ++#define MV64460_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110 ++#define MV64460_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340 ++#define MV64460_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118 ++#define MV64460_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348 ++#define MV64460_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310 ++#define MV64460_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350 ++#define MV64460_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318 ++#define MV64460_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358 ++ ++#define MV64460_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 ++#define MV64460_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 ++#define MV64460_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 ++#define MV64460_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 ++#define MV64460_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 ++#define MV64460_CPU_GE_HEADERS_RETARGET_BASE 0x3d8 ++#define MV64460_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0 ++#define MV64460_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8 ++ ++/****************************************/ ++/* CPU Control Registers */ ++/****************************************/ ++ ++#define MV64460_CPU_CONFIG 0x000 ++#define MV64460_CPU_MODE 0x120 ++#define MV64460_CPU_MASTER_CONTROL 0x160 ++#define MV64460_CPU_CROSS_BAR_CONTROL_LOW 0x150 ++#define MV64460_CPU_CROSS_BAR_CONTROL_HIGH 0x158 ++#define MV64460_CPU_CROSS_BAR_TIMEOUT 0x168 ++ ++/****************************************/ ++/* SMP RegisterS */ ++/****************************************/ ++ ++#define MV64460_SMP_WHO_AM_I 0x200 ++#define MV64460_SMP_CPU0_DOORBELL 0x214 ++#define MV64460_SMP_CPU0_DOORBELL_CLEAR 0x21C ++#define MV64460_SMP_CPU1_DOORBELL 0x224 ++#define MV64460_SMP_CPU1_DOORBELL_CLEAR 0x22C ++#define MV64460_SMP_CPU0_DOORBELL_MASK 0x234 ++#define MV64460_SMP_CPU1_DOORBELL_MASK 0x23C ++#define MV64460_SMP_SEMAPHOR0 0x244 ++#define MV64460_SMP_SEMAPHOR1 0x24c ++#define MV64460_SMP_SEMAPHOR2 0x254 ++#define MV64460_SMP_SEMAPHOR3 0x25c ++#define MV64460_SMP_SEMAPHOR4 0x264 ++#define MV64460_SMP_SEMAPHOR5 0x26c ++#define MV64460_SMP_SEMAPHOR6 0x274 ++#define MV64460_SMP_SEMAPHOR7 0x27c ++ ++/****************************************/ ++/* CPU Sync Barrier Register */ ++/****************************************/ ++ ++#define MV64460_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 ++#define MV64460_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 ++#define MV64460_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 ++#define MV64460_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 ++ ++/****************************************/ ++/* CPU Access Protect */ ++/****************************************/ ++ ++#define MV64460_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180 ++#define MV64460_CPU_PROTECT_WINDOW_0_SIZE 0x188 ++#define MV64460_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190 ++#define MV64460_CPU_PROTECT_WINDOW_1_SIZE 0x198 ++#define MV64460_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0 ++#define MV64460_CPU_PROTECT_WINDOW_2_SIZE 0x1a8 ++#define MV64460_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0 ++#define MV64460_CPU_PROTECT_WINDOW_3_SIZE 0x1b8 ++ ++ ++/****************************************/ ++/* CPU Error Report */ ++/****************************************/ ++ ++#define MV64460_CPU_ERROR_ADDR_LOW 0x070 ++#define MV64460_CPU_ERROR_ADDR_HIGH 0x078 ++#define MV64460_CPU_ERROR_DATA_LOW 0x128 ++#define MV64460_CPU_ERROR_DATA_HIGH 0x130 ++#define MV64460_CPU_ERROR_PARITY 0x138 ++#define MV64460_CPU_ERROR_CAUSE 0x140 ++#define MV64460_CPU_ERROR_MASK 0x148 ++ ++/****************************************/ ++/* CPU Interface Debug Registers */ ++/****************************************/ ++ ++#define MV64460_PUNIT_SLAVE_DEBUG_LOW 0x360 ++#define MV64460_PUNIT_SLAVE_DEBUG_HIGH 0x368 ++#define MV64460_PUNIT_MASTER_DEBUG_LOW 0x370 ++#define MV64460_PUNIT_MASTER_DEBUG_HIGH 0x378 ++#define MV64460_PUNIT_MMASK 0x3e4 ++ ++/****************************************/ ++/* Integrated SRAM Registers */ ++/****************************************/ ++ ++#define MV64460_SRAM_CONFIG 0x380 ++#define MV64460_SRAM_TEST_MODE 0X3F4 ++#define MV64460_SRAM_ERROR_CAUSE 0x388 ++#define MV64460_SRAM_ERROR_ADDR 0x390 ++#define MV64460_SRAM_ERROR_ADDR_HIGH 0X3F8 ++#define MV64460_SRAM_ERROR_DATA_LOW 0x398 ++#define MV64460_SRAM_ERROR_DATA_HIGH 0x3a0 ++#define MV64460_SRAM_ERROR_DATA_PARITY 0x3a8 ++ ++/****************************************/ ++/* SDRAM Configuration */ ++/****************************************/ ++ ++#define MV64460_SDRAM_CONFIG 0x1400 ++#define MV64460_D_UNIT_CONTROL_LOW 0x1404 ++#define MV64460_D_UNIT_CONTROL_HIGH 0x1424 ++#define MV64460_D_UNIT_MMASK 0x14B0 ++#define MV64460_SDRAM_TIMING_CONTROL_LOW 0x1408 ++#define MV64460_SDRAM_TIMING_CONTROL_HIGH 0x140c ++#define MV64460_SDRAM_ADDR_CONTROL 0x1410 ++#define MV64460_SDRAM_OPEN_PAGES_CONTROL 0x1414 ++#define MV64460_SDRAM_OPERATION 0x1418 ++#define MV64460_SDRAM_MODE 0x141c ++#define MV64460_EXTENDED_DRAM_MODE 0x1420 ++#define MV64460_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 ++#define MV64460_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 ++#define MV64460_SDRAM_CROSS_BAR_TIMEOUT 0x1438 ++#define MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 ++#define MV64460_SDRAM_DATA_PADS_CALIBRATION 0x14c4 ++ ++/****************************************/ ++/* SDRAM Error Report */ ++/****************************************/ ++ ++#define MV64460_SDRAM_ERROR_DATA_LOW 0x1444 ++#define MV64460_SDRAM_ERROR_DATA_HIGH 0x1440 ++#define MV64460_SDRAM_ERROR_ADDR 0x1450 ++#define MV64460_SDRAM_RECEIVED_ECC 0x1448 ++#define MV64460_SDRAM_CALCULATED_ECC 0x144c ++#define MV64460_SDRAM_ECC_CONTROL 0x1454 ++#define MV64460_SDRAM_ECC_ERROR_COUNTER 0x1458 ++ ++/******************************************/ ++/* Controlled Delay Line (CDL) Registers */ ++/******************************************/ ++ ++#define MV64460_DFCDL_CONFIG0 0x1480 ++#define MV64460_DFCDL_CONFIG1 0x1484 ++#define MV64460_DLL_WRITE 0x1488 ++#define MV64460_DLL_READ 0x148c ++#define MV64460_SRAM_ADDR 0x1490 ++#define MV64460_SRAM_DATA0 0x1494 ++#define MV64460_SRAM_DATA1 0x1498 ++#define MV64460_SRAM_DATA2 0x149c ++#define MV64460_DFCL_PROBE 0x14a0 ++ ++/******************************************/ ++/* Debug Registers */ ++/******************************************/ ++ ++#define MV64460_DUNIT_DEBUG_LOW 0x1460 ++#define MV64460_DUNIT_DEBUG_HIGH 0x1464 ++#define MV64460_DUNIT_MMASK 0X1b40 ++ ++/****************************************/ ++/* Device Parameters */ ++/****************************************/ ++ ++#define MV64460_DEVICE_BANK0_PARAMETERS 0x45c ++#define MV64460_DEVICE_BANK1_PARAMETERS 0x460 ++#define MV64460_DEVICE_BANK2_PARAMETERS 0x464 ++#define MV64460_DEVICE_BANK3_PARAMETERS 0x468 ++#define MV64460_DEVICE_BOOT_BANK_PARAMETERS 0x46c ++#define MV64460_DEVICE_INTERFACE_CONTROL 0x4c0 ++#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8 ++#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc ++#define MV64460_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4 ++ ++/****************************************/ ++/* Device interrupt registers */ ++/****************************************/ ++ ++#define MV64460_DEVICE_INTERRUPT_CAUSE 0x4d0 ++#define MV64460_DEVICE_INTERRUPT_MASK 0x4d4 ++#define MV64460_DEVICE_ERROR_ADDR 0x4d8 ++#define MV64460_DEVICE_ERROR_DATA 0x4dc ++#define MV64460_DEVICE_ERROR_PARITY 0x4e0 ++ ++/****************************************/ ++/* Device debug registers */ ++/****************************************/ ++ ++#define MV64460_DEVICE_DEBUG_LOW 0x4e4 ++#define MV64460_DEVICE_DEBUG_HIGH 0x4e8 ++#define MV64460_RUNIT_MMASK 0x4f0 ++ ++/****************************************/ ++/* PCI Slave Address Decoding registers */ ++/****************************************/ ++ ++#define MV64460_PCI_0_CS_0_BANK_SIZE 0xc08 ++#define MV64460_PCI_1_CS_0_BANK_SIZE 0xc88 ++#define MV64460_PCI_0_CS_1_BANK_SIZE 0xd08 ++#define MV64460_PCI_1_CS_1_BANK_SIZE 0xd88 ++#define MV64460_PCI_0_CS_2_BANK_SIZE 0xc0c ++#define MV64460_PCI_1_CS_2_BANK_SIZE 0xc8c ++#define MV64460_PCI_0_CS_3_BANK_SIZE 0xd0c ++#define MV64460_PCI_1_CS_3_BANK_SIZE 0xd8c ++#define MV64460_PCI_0_DEVCS_0_BANK_SIZE 0xc10 ++#define MV64460_PCI_1_DEVCS_0_BANK_SIZE 0xc90 ++#define MV64460_PCI_0_DEVCS_1_BANK_SIZE 0xd10 ++#define MV64460_PCI_1_DEVCS_1_BANK_SIZE 0xd90 ++#define MV64460_PCI_0_DEVCS_2_BANK_SIZE 0xd18 ++#define MV64460_PCI_1_DEVCS_2_BANK_SIZE 0xd98 ++#define MV64460_PCI_0_DEVCS_3_BANK_SIZE 0xc14 ++#define MV64460_PCI_1_DEVCS_3_BANK_SIZE 0xc94 ++#define MV64460_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14 ++#define MV64460_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94 ++#define MV64460_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c ++#define MV64460_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c ++#define MV64460_PCI_0_P2P_MEM1_BAR_SIZE 0xd20 ++#define MV64460_PCI_1_P2P_MEM1_BAR_SIZE 0xda0 ++#define MV64460_PCI_0_P2P_I_O_BAR_SIZE 0xd24 ++#define MV64460_PCI_1_P2P_I_O_BAR_SIZE 0xda4 ++#define MV64460_PCI_0_CPU_BAR_SIZE 0xd28 ++#define MV64460_PCI_1_CPU_BAR_SIZE 0xda8 ++#define MV64460_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00 ++#define MV64460_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80 ++#define MV64460_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c ++#define MV64460_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c ++#define MV64460_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c ++#define MV64460_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc ++#define MV64460_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48 ++#define MV64460_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8 ++#define MV64460_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48 ++#define MV64460_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8 ++#define MV64460_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c ++#define MV64460_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc ++#define MV64460_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c ++#define MV64460_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc ++#define MV64460_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04 ++#define MV64460_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84 ++#define MV64460_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08 ++#define MV64460_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88 ++#define MV64460_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C ++#define MV64460_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C ++#define MV64460_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10 ++#define MV64460_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90 ++#define MV64460_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50 ++#define MV64460_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0 ++#define MV64460_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50 ++#define MV64460_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0 ++#define MV64460_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58 ++#define MV64460_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8 ++#define MV64460_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54 ++#define MV64460_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4 ++#define MV64460_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54 ++#define MV64460_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4 ++#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c ++#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc ++#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60 ++#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0 ++#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64 ++#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4 ++#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68 ++#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8 ++#define MV64460_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c ++#define MV64460_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec ++#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70 ++#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0 ++#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 ++#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 ++#define MV64460_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00 ++#define MV64460_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 ++#define MV64460_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38 ++#define MV64460_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8 ++#define MV64460_PCI_0_ADDR_DECODE_CONTROL 0xd3c ++#define MV64460_PCI_1_ADDR_DECODE_CONTROL 0xdbc ++#define MV64460_PCI_0_HEADERS_RETARGET_CONTROL 0xF40 ++#define MV64460_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 ++#define MV64460_PCI_0_HEADERS_RETARGET_BASE 0xF44 ++#define MV64460_PCI_1_HEADERS_RETARGET_BASE 0xFc4 ++#define MV64460_PCI_0_HEADERS_RETARGET_HIGH 0xF48 ++#define MV64460_PCI_1_HEADERS_RETARGET_HIGH 0xFc8 ++ ++/***********************************/ ++/* PCI Control Register Map */ ++/***********************************/ ++ ++#define MV64460_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 ++#define MV64460_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 ++#define MV64460_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C ++#define MV64460_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C ++#define MV64460_PCI_0_COMMAND 0xc00 ++#define MV64460_PCI_1_COMMAND 0xc80 ++#define MV64460_PCI_0_MODE 0xd00 ++#define MV64460_PCI_1_MODE 0xd80 ++#define MV64460_PCI_0_RETRY 0xc04 ++#define MV64460_PCI_1_RETRY 0xc84 ++#define MV64460_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 ++#define MV64460_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 ++#define MV64460_PCI_0_MSI_TRIGGER_TIMER 0xc38 ++#define MV64460_PCI_1_MSI_TRIGGER_TIMER 0xcb8 ++#define MV64460_PCI_0_ARBITER_CONTROL 0x1d00 ++#define MV64460_PCI_1_ARBITER_CONTROL 0x1d80 ++#define MV64460_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 ++#define MV64460_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 ++#define MV64460_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c ++#define MV64460_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c ++#define MV64460_PCI_0_CROSS_BAR_TIMEOUT 0x1d04 ++#define MV64460_PCI_1_CROSS_BAR_TIMEOUT 0x1d84 ++#define MV64460_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 ++#define MV64460_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 ++#define MV64460_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 ++#define MV64460_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 ++#define MV64460_PCI_0_P2P_CONFIG 0x1d14 ++#define MV64460_PCI_1_P2P_CONFIG 0x1d94 ++ ++#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 ++#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 ++#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 ++#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 ++#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 ++#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 ++#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 ++#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 ++#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 ++#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 ++#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 ++#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 ++#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 ++#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 ++#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 ++#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 ++#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 ++#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 ++ ++#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 ++#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 ++#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 ++#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 ++#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 ++#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 ++#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 ++#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 ++#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 ++#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 ++#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 ++#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 ++#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 ++#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 ++#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 ++#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 ++#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 ++#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 ++ ++/****************************************/ ++/* PCI Configuration Access Registers */ ++/****************************************/ ++ ++#define MV64460_PCI_0_CONFIG_ADDR 0xcf8 ++#define MV64460_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc ++#define MV64460_PCI_1_CONFIG_ADDR 0xc78 ++#define MV64460_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c ++#define MV64460_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 ++#define MV64460_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 ++ ++/****************************************/ ++/* PCI Error Report Registers */ ++/****************************************/ ++ ++#define MV64460_PCI_0_SERR_MASK 0xc28 ++#define MV64460_PCI_1_SERR_MASK 0xca8 ++#define MV64460_PCI_0_ERROR_ADDR_LOW 0x1d40 ++#define MV64460_PCI_1_ERROR_ADDR_LOW 0x1dc0 ++#define MV64460_PCI_0_ERROR_ADDR_HIGH 0x1d44 ++#define MV64460_PCI_1_ERROR_ADDR_HIGH 0x1dc4 ++#define MV64460_PCI_0_ERROR_ATTRIBUTE 0x1d48 ++#define MV64460_PCI_1_ERROR_ATTRIBUTE 0x1dc8 ++#define MV64460_PCI_0_ERROR_COMMAND 0x1d50 ++#define MV64460_PCI_1_ERROR_COMMAND 0x1dd0 ++#define MV64460_PCI_0_ERROR_CAUSE 0x1d58 ++#define MV64460_PCI_1_ERROR_CAUSE 0x1dd8 ++#define MV64460_PCI_0_ERROR_MASK 0x1d5c ++#define MV64460_PCI_1_ERROR_MASK 0x1ddc ++ ++/****************************************/ ++/* PCI Debug Registers */ ++/****************************************/ ++ ++#define MV64460_PCI_0_MMASK 0X1D24 ++#define MV64460_PCI_1_MMASK 0X1DA4 ++ ++/*********************************************/ ++/* PCI Configuration, Function 0, Registers */ ++/*********************************************/ ++ ++#define MV64460_PCI_DEVICE_AND_VENDOR_ID 0x000 ++#define MV64460_PCI_STATUS_AND_COMMAND 0x004 ++#define MV64460_PCI_CLASS_CODE_AND_REVISION_ID 0x008 ++#define MV64460_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C ++ ++#define MV64460_PCI_SCS_0_BASE_ADDR_LOW 0x010 ++#define MV64460_PCI_SCS_0_BASE_ADDR_HIGH 0x014 ++#define MV64460_PCI_SCS_1_BASE_ADDR_LOW 0x018 ++#define MV64460_PCI_SCS_1_BASE_ADDR_HIGH 0x01C ++#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 ++#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 ++#define MV64460_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c ++#define MV64460_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 ++#define MV64460_PCI_CAPABILTY_LIST_POINTER 0x034 ++#define MV64460_PCI_INTERRUPT_PIN_AND_LINE 0x03C ++ /* capability list */ ++#define MV64460_PCI_POWER_MANAGEMENT_CAPABILITY 0x040 ++#define MV64460_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 ++#define MV64460_PCI_VPD_ADDR 0x048 ++#define MV64460_PCI_VPD_DATA 0x04c ++#define MV64460_PCI_MSI_MESSAGE_CONTROL 0x050 ++#define MV64460_PCI_MSI_MESSAGE_ADDR 0x054 ++#define MV64460_PCI_MSI_MESSAGE_UPPER_ADDR 0x058 ++#define MV64460_PCI_MSI_MESSAGE_DATA 0x05c ++#define MV64460_PCI_X_COMMAND 0x060 ++#define MV64460_PCI_X_STATUS 0x064 ++#define MV64460_PCI_COMPACT_PCI_HOT_SWAP 0x068 ++ ++/***********************************************/ ++/* PCI Configuration, Function 1, Registers */ ++/***********************************************/ ++ ++#define MV64460_PCI_SCS_2_BASE_ADDR_LOW 0x110 ++#define MV64460_PCI_SCS_2_BASE_ADDR_HIGH 0x114 ++#define MV64460_PCI_SCS_3_BASE_ADDR_LOW 0x118 ++#define MV64460_PCI_SCS_3_BASE_ADDR_HIGH 0x11c ++#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 ++#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 ++ ++/***********************************************/ ++/* PCI Configuration, Function 2, Registers */ ++/***********************************************/ ++ ++#define MV64460_PCI_DEVCS_0_BASE_ADDR_LOW 0x210 ++#define MV64460_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 ++#define MV64460_PCI_DEVCS_1_BASE_ADDR_LOW 0x218 ++#define MV64460_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c ++#define MV64460_PCI_DEVCS_2_BASE_ADDR_LOW 0x220 ++#define MV64460_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 ++ ++/***********************************************/ ++/* PCI Configuration, Function 3, Registers */ ++/***********************************************/ ++ ++#define MV64460_PCI_DEVCS_3_BASE_ADDR_LOW 0x310 ++#define MV64460_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 ++#define MV64460_PCI_BOOT_CS_BASE_ADDR_LOW 0x318 ++#define MV64460_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c ++#define MV64460_PCI_CPU_BASE_ADDR_LOW 0x220 ++#define MV64460_PCI_CPU_BASE_ADDR_HIGH 0x224 ++ ++/***********************************************/ ++/* PCI Configuration, Function 4, Registers */ ++/***********************************************/ ++ ++#define MV64460_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 ++#define MV64460_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 ++#define MV64460_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 ++#define MV64460_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c ++#define MV64460_PCI_P2P_I_O_BASE_ADDR 0x420 ++#define MV64460_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 ++ ++/****************************************/ ++/* Messaging Unit Registers (I20) */ ++/****************************************/ ++ ++#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 ++#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 ++#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 ++#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C ++#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 ++#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 ++#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 ++#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C ++#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 ++#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 ++#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 ++#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 ++#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 ++#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 ++#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 ++#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 ++#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 ++#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C ++#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 ++#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 ++#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 ++#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC ++ ++#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 ++#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 ++#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 ++#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C ++#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 ++#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 ++#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 ++#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC ++#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 ++#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 ++#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 ++#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 ++#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 ++#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 ++#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 ++#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 ++#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 ++#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC ++#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 ++#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 ++#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 ++#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C ++ ++#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 ++#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 ++#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 ++#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C ++#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 ++#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 ++#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 ++#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C ++#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 ++#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 ++#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 ++#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 ++#define MV64460_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 ++#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 ++#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 ++#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 ++#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 ++#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C ++#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 ++#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 ++#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 ++#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC ++#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 ++#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 ++#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 ++#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C ++#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 ++#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 ++#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 ++#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC ++#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 ++#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 ++#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 ++#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 ++#define MV64460_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 ++#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 ++#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 ++#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 ++#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 ++#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC ++#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 ++#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 ++#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 ++#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C ++ ++/****************************************/ ++/* Ethernet Unit Registers */ ++/****************************************/ ++ ++#define MV64460_ETH_PHY_ADDR_REG 0x2000 ++#define MV64460_ETH_SMI_REG 0x2004 ++#define MV64460_ETH_UNIT_DEFAULT_ADDR_REG 0x2008 ++#define MV64460_ETH_UNIT_DEFAULTID_REG 0x200c ++#define MV64460_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 ++#define MV64460_ETH_UNIT_INTERRUPT_MASK_REG 0x2084 ++#define MV64460_ETH_UNIT_INTERNAL_USE_REG 0x24fc ++#define MV64460_ETH_UNIT_ERROR_ADDR_REG 0x2094 ++#define MV64460_ETH_BAR_0 0x2200 ++#define MV64460_ETH_BAR_1 0x2208 ++#define MV64460_ETH_BAR_2 0x2210 ++#define MV64460_ETH_BAR_3 0x2218 ++#define MV64460_ETH_BAR_4 0x2220 ++#define MV64460_ETH_BAR_5 0x2228 ++#define MV64460_ETH_SIZE_REG_0 0x2204 ++#define MV64460_ETH_SIZE_REG_1 0x220c ++#define MV64460_ETH_SIZE_REG_2 0x2214 ++#define MV64460_ETH_SIZE_REG_3 0x221c ++#define MV64460_ETH_SIZE_REG_4 0x2224 ++#define MV64460_ETH_SIZE_REG_5 0x222c ++#define MV64460_ETH_HEADERS_RETARGET_BASE_REG 0x2230 ++#define MV64460_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 ++#define MV64460_ETH_HIGH_ADDR_REMAP_REG_0 0x2280 ++#define MV64460_ETH_HIGH_ADDR_REMAP_REG_1 0x2284 ++#define MV64460_ETH_HIGH_ADDR_REMAP_REG_2 0x2288 ++#define MV64460_ETH_HIGH_ADDR_REMAP_REG_3 0x228c ++#define MV64460_ETH_BASE_ADDR_ENABLE_REG 0x2290 ++#define MV64460_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) ++#define MV64460_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) ++#define MV64460_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) ++#define MV64460_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) ++#define MV64460_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) ++#define MV64460_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) ++#define MV64460_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) ++#define MV64460_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) ++#define MV64460_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) ++#define MV64460_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) ++#define MV64460_ETH_DSCP_0(port) (0x2420 + (port<<10)) ++#define MV64460_ETH_DSCP_1(port) (0x2424 + (port<<10)) ++#define MV64460_ETH_DSCP_2(port) (0x2428 + (port<<10)) ++#define MV64460_ETH_DSCP_3(port) (0x242c + (port<<10)) ++#define MV64460_ETH_DSCP_4(port) (0x2430 + (port<<10)) ++#define MV64460_ETH_DSCP_5(port) (0x2434 + (port<<10)) ++#define MV64460_ETH_DSCP_6(port) (0x2438 + (port<<10)) ++#define MV64460_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) ++#define MV64460_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) ++#define MV64460_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) ++#define MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) ++#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) ++#define MV64460_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) ++#define MV64460_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) ++#define MV64460_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) ++#define MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) ++#define MV64460_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) ++#define MV64460_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) ++#define MV64460_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) ++#define MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) ++#define MV64460_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) ++#define MV64460_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10) ++#define MV64460_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) ++#define MV64460_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) ++#define MV64460_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) ++#define MV64460_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) ++#define MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) ++#define MV64460_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) ++#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) ++#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) ++#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) ++#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) ++#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) ++#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) ++#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) ++#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) ++#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) ++#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) ++#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) ++#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) ++#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) ++#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) ++#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) ++#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) ++#define MV64460_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) ++#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) ++#define MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) ++#define MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) ++#define MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) ++ ++/*******************************************/ ++/* CUNIT Registers */ ++/*******************************************/ ++ ++ /* Address Decoding Register Map */ ++ ++#define MV64460_CUNIT_BASE_ADDR_REG0 0xf200 ++#define MV64460_CUNIT_BASE_ADDR_REG1 0xf208 ++#define MV64460_CUNIT_BASE_ADDR_REG2 0xf210 ++#define MV64460_CUNIT_BASE_ADDR_REG3 0xf218 ++#define MV64460_CUNIT_SIZE0 0xf204 ++#define MV64460_CUNIT_SIZE1 0xf20c ++#define MV64460_CUNIT_SIZE2 0xf214 ++#define MV64460_CUNIT_SIZE3 0xf21c ++#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 ++#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 ++#define MV64460_CUNIT_BASE_ADDR_ENABLE_REG 0xf250 ++#define MV64460_MPSC0_ACCESS_PROTECTION_REG 0xf254 ++#define MV64460_MPSC1_ACCESS_PROTECTION_REG 0xf258 ++#define MV64460_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C ++ ++ /* Error Report Registers */ ++ ++#define MV64460_CUNIT_INTERRUPT_CAUSE_REG 0xf310 ++#define MV64460_CUNIT_INTERRUPT_MASK_REG 0xf314 ++#define MV64460_CUNIT_ERROR_ADDR 0xf318 ++ ++ /* Cunit Control Registers */ ++ ++#define MV64460_CUNIT_ARBITER_CONTROL_REG 0xf300 ++#define MV64460_CUNIT_CONFIG_REG 0xb40c ++#define MV64460_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 ++ ++ /* Cunit Debug Registers */ ++ ++#define MV64460_CUNIT_DEBUG_LOW 0xf340 ++#define MV64460_CUNIT_DEBUG_HIGH 0xf344 ++#define MV64460_CUNIT_MMASK 0xf380 ++ ++ /* Cunit Base Address Enable Window Bits*/ ++#define MV64460_CUNIT_BASE_ADDR_WIN_0_BIT 0x0 ++#define MV64460_CUNIT_BASE_ADDR_WIN_1_BIT 0x1 ++#define MV64460_CUNIT_BASE_ADDR_WIN_2_BIT 0x2 ++#define MV64460_CUNIT_BASE_ADDR_WIN_3_BIT 0x3 ++ ++ /* MPSCs Clocks Routing Registers */ ++ ++#define MV64460_MPSC_ROUTING_REG 0xb400 ++#define MV64460_MPSC_RX_CLOCK_ROUTING_REG 0xb404 ++#define MV64460_MPSC_TX_CLOCK_ROUTING_REG 0xb408 ++ ++ /* MPSCs Interrupts Registers */ ++ ++#define MV64460_MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) ++#define MV64460_MPSC_MASK_REG(port) (0xb884 + (port<<3)) ++ ++#define MV64460_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) ++#define MV64460_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) ++#define MV64460_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) ++#define MV64460_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) ++#define MV64460_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) ++#define MV64460_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) ++#define MV64460_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) ++#define MV64460_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) ++#define MV64460_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) ++#define MV64460_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) ++#define MV64460_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) ++#define MV64460_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) ++#define MV64460_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) ++ ++ /* MPSC0 Registers */ ++ ++ ++/***************************************/ ++/* SDMA Registers */ ++/***************************************/ ++ ++#define MV64460_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) ++#define MV64460_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) ++#define MV64460_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) ++#define MV64460_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) ++#define MV64460_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) ++ ++#define MV64460_SDMA_CAUSE_REG 0xb800 ++#define MV64460_SDMA_MASK_REG 0xb880 ++ ++ ++/****************************************/ ++/* SDMA Address Space Targets */ ++/****************************************/ ++ ++#define MV64460_SDMA_DRAM_CS_0_TARGET 0x0e00 ++#define MV64460_SDMA_DRAM_CS_1_TARGET 0x0d00 ++#define MV64460_SDMA_DRAM_CS_2_TARGET 0x0b00 ++#define MV64460_SDMA_DRAM_CS_3_TARGET 0x0700 ++ ++#define MV64460_SDMA_DEV_CS_0_TARGET 0x1e01 ++#define MV64460_SDMA_DEV_CS_1_TARGET 0x1d01 ++#define MV64460_SDMA_DEV_CS_2_TARGET 0x1b01 ++#define MV64460_SDMA_DEV_CS_3_TARGET 0x1701 ++ ++#define MV64460_SDMA_BOOT_CS_TARGET 0x0f00 ++ ++#define MV64460_SDMA_SRAM_TARGET 0x0003 ++#define MV64460_SDMA_60X_BUS_TARGET 0x4003 ++ ++#define MV64460_PCI_0_TARGET 0x0003 ++#define MV64460_PCI_1_TARGET 0x0004 ++ ++ ++/* Devices BAR and size registers */ ++ ++#define MV64460_DEV_CS0_BASE_ADDR 0x028 ++#define MV64460_DEV_CS0_SIZE 0x030 ++#define MV64460_DEV_CS1_BASE_ADDR 0x228 ++#define MV64460_DEV_CS1_SIZE 0x230 ++#define MV64460_DEV_CS2_BASE_ADDR 0x248 ++#define MV64460_DEV_CS2_SIZE 0x250 ++#define MV64460_DEV_CS3_BASE_ADDR 0x038 ++#define MV64460_DEV_CS3_SIZE 0x040 ++#define MV64460_BOOTCS_BASE_ADDR 0x238 ++#define MV64460_BOOTCS_SIZE 0x240 ++ ++/* SDMA Window access protection */ ++#define MV64460_SDMA_WIN_ACCESS_NOT_ALLOWED 0 ++#define MV64460_SDMA_WIN_ACCESS_READ_ONLY 1 ++#define MV64460_SDMA_WIN_ACCESS_FULL 2 ++ ++/* BRG Interrupts */ ++ ++#define MV64460_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) ++#define MV64460_BRG_BAUDE_TUNING_REG(brg) (0xb204 + (brg<<3)) ++#define MV64460_BRG_CAUSE_REG 0xb834 ++#define MV64460_BRG_MASK_REG 0xb8b4 ++ ++/****************************************/ ++/* DMA Channel Control */ ++/****************************************/ ++ ++#define MV64460_DMA_CHANNEL0_CONTROL 0x840 ++#define MV64460_DMA_CHANNEL0_CONTROL_HIGH 0x880 ++#define MV64460_DMA_CHANNEL1_CONTROL 0x844 ++#define MV64460_DMA_CHANNEL1_CONTROL_HIGH 0x884 ++#define MV64460_DMA_CHANNEL2_CONTROL 0x848 ++#define MV64460_DMA_CHANNEL2_CONTROL_HIGH 0x888 ++#define MV64460_DMA_CHANNEL3_CONTROL 0x84C ++#define MV64460_DMA_CHANNEL3_CONTROL_HIGH 0x88C ++ ++ ++/****************************************/ ++/* IDMA Registers */ ++/****************************************/ ++ ++#define MV64460_DMA_CHANNEL0_BYTE_COUNT 0x800 ++#define MV64460_DMA_CHANNEL1_BYTE_COUNT 0x804 ++#define MV64460_DMA_CHANNEL2_BYTE_COUNT 0x808 ++#define MV64460_DMA_CHANNEL3_BYTE_COUNT 0x80C ++#define MV64460_DMA_CHANNEL0_SOURCE_ADDR 0x810 ++#define MV64460_DMA_CHANNEL1_SOURCE_ADDR 0x814 ++#define MV64460_DMA_CHANNEL2_SOURCE_ADDR 0x818 ++#define MV64460_DMA_CHANNEL3_SOURCE_ADDR 0x81c ++#define MV64460_DMA_CHANNEL0_DESTINATION_ADDR 0x820 ++#define MV64460_DMA_CHANNEL1_DESTINATION_ADDR 0x824 ++#define MV64460_DMA_CHANNEL2_DESTINATION_ADDR 0x828 ++#define MV64460_DMA_CHANNEL3_DESTINATION_ADDR 0x82C ++#define MV64460_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830 ++#define MV64460_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834 ++#define MV64460_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838 ++#define MV64460_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C ++#define MV64460_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870 ++#define MV64460_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874 ++#define MV64460_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878 ++#define MV64460_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C ++ ++ /* IDMA Address Decoding Base Address Registers */ ++ ++#define MV64460_DMA_BASE_ADDR_REG0 0xa00 ++#define MV64460_DMA_BASE_ADDR_REG1 0xa08 ++#define MV64460_DMA_BASE_ADDR_REG2 0xa10 ++#define MV64460_DMA_BASE_ADDR_REG3 0xa18 ++#define MV64460_DMA_BASE_ADDR_REG4 0xa20 ++#define MV64460_DMA_BASE_ADDR_REG5 0xa28 ++#define MV64460_DMA_BASE_ADDR_REG6 0xa30 ++#define MV64460_DMA_BASE_ADDR_REG7 0xa38 ++ ++ /* IDMA Address Decoding Size Address Register */ ++ ++#define MV64460_DMA_SIZE_REG0 0xa04 ++#define MV64460_DMA_SIZE_REG1 0xa0c ++#define MV64460_DMA_SIZE_REG2 0xa14 ++#define MV64460_DMA_SIZE_REG3 0xa1c ++#define MV64460_DMA_SIZE_REG4 0xa24 ++#define MV64460_DMA_SIZE_REG5 0xa2c ++#define MV64460_DMA_SIZE_REG6 0xa34 ++#define MV64460_DMA_SIZE_REG7 0xa3C ++ ++ /* IDMA Address Decoding High Address Remap and Access ++ Protection Registers */ ++ ++#define MV64460_DMA_HIGH_ADDR_REMAP_REG0 0xa60 ++#define MV64460_DMA_HIGH_ADDR_REMAP_REG1 0xa64 ++#define MV64460_DMA_HIGH_ADDR_REMAP_REG2 0xa68 ++#define MV64460_DMA_HIGH_ADDR_REMAP_REG3 0xa6C ++#define MV64460_DMA_BASE_ADDR_ENABLE_REG 0xa80 ++#define MV64460_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 ++#define MV64460_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 ++#define MV64460_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 ++#define MV64460_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c ++#define MV64460_DMA_ARBITER_CONTROL 0x860 ++#define MV64460_DMA_CROSS_BAR_TIMEOUT 0x8d0 ++ ++ /* IDMA Headers Retarget Registers */ ++ ++#define MV64460_DMA_HEADERS_RETARGET_CONTROL 0xa84 ++#define MV64460_DMA_HEADERS_RETARGET_BASE 0xa88 ++ ++ /* IDMA Interrupt Register */ ++ ++#define MV64460_DMA_INTERRUPT_CAUSE_REG 0x8c0 ++#define MV64460_DMA_INTERRUPT_CAUSE_MASK 0x8c4 ++#define MV64460_DMA_ERROR_ADDR 0x8c8 ++#define MV64460_DMA_ERROR_SELECT 0x8cc ++ ++ /* IDMA Debug Register ( for internal use ) */ ++ ++#define MV64460_DMA_DEBUG_LOW 0x8e0 ++#define MV64460_DMA_DEBUG_HIGH 0x8e4 ++#define MV64460_DMA_SPARE 0xA8C ++ ++/****************************************/ ++/* Timer_Counter */ ++/****************************************/ ++ ++#define MV64460_TIMER_COUNTER0 0x850 ++#define MV64460_TIMER_COUNTER1 0x854 ++#define MV64460_TIMER_COUNTER2 0x858 ++#define MV64460_TIMER_COUNTER3 0x85C ++#define MV64460_TIMER_COUNTER_0_3_CONTROL 0x864 ++#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 ++#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c ++ ++/****************************************/ ++/* Watchdog registers */ ++/****************************************/ ++ ++#define MV64460_WATCHDOG_CONFIG_REG 0xb410 ++#define MV64460_WATCHDOG_VALUE_REG 0xb414 ++ ++/****************************************/ ++/* I2C Registers */ ++/****************************************/ ++ ++#define MV64460_I2C_SLAVE_ADDR 0xc000 ++#define MV64460_I2C_EXTENDED_SLAVE_ADDR 0xc010 ++#define MV64460_I2C_DATA 0xc004 ++#define MV64460_I2C_CONTROL 0xc008 ++#define MV64460_I2C_STATUS_BAUDE_RATE 0xc00C ++#define MV64460_I2C_SOFT_RESET 0xc01c ++ ++/****************************************/ ++/* GPP Interface Registers */ ++/****************************************/ ++ ++#define MV64460_GPP_IO_CONTROL 0xf100 ++#define MV64460_GPP_LEVEL_CONTROL 0xf110 ++#define MV64460_GPP_VALUE 0xf104 ++#define MV64460_GPP_INTERRUPT_CAUSE 0xf108 ++#define MV64460_GPP_INTERRUPT_MASK0 0xf10c ++#define MV64460_GPP_INTERRUPT_MASK1 0xf114 ++#define MV64460_GPP_VALUE_SET 0xf118 ++#define MV64460_GPP_VALUE_CLEAR 0xf11c ++ ++/****************************************/ ++/* Interrupt Controller Registers */ ++/****************************************/ ++ ++/****************************************/ ++/* Interrupts */ ++/****************************************/ ++ ++#define MV64460_MAIN_INTERRUPT_CAUSE_LOW 0x004 ++#define MV64460_MAIN_INTERRUPT_CAUSE_HIGH 0x00c ++#define MV64460_CPU_INTERRUPT0_MASK_LOW 0x014 ++#define MV64460_CPU_INTERRUPT0_MASK_HIGH 0x01c ++#define MV64460_CPU_INTERRUPT0_SELECT_CAUSE 0x024 ++#define MV64460_CPU_INTERRUPT1_MASK_LOW 0x034 ++#define MV64460_CPU_INTERRUPT1_MASK_HIGH 0x03c ++#define MV64460_CPU_INTERRUPT1_SELECT_CAUSE 0x044 ++#define MV64460_INTERRUPT0_MASK_0_LOW 0x054 ++#define MV64460_INTERRUPT0_MASK_0_HIGH 0x05c ++#define MV64460_INTERRUPT0_SELECT_CAUSE 0x064 ++#define MV64460_INTERRUPT1_MASK_0_LOW 0x074 ++#define MV64460_INTERRUPT1_MASK_0_HIGH 0x07c ++#define MV64460_INTERRUPT1_SELECT_CAUSE 0x084 ++ ++/****************************************/ ++/* MPP Interface Registers */ ++/****************************************/ ++ ++#define MV64460_MPP_CONTROL0 0xf000 ++#define MV64460_MPP_CONTROL1 0xf004 ++#define MV64460_MPP_CONTROL2 0xf008 ++#define MV64460_MPP_CONTROL3 0xf00c ++ ++/****************************************/ ++/* Serial Initialization registers */ ++/****************************************/ ++ ++#define MV64460_SERIAL_INIT_LAST_DATA 0xf324 ++#define MV64460_SERIAL_INIT_CONTROL 0xf328 ++#define MV64460_SERIAL_INIT_STATUS 0xf32c ++ ++ ++#endif /* __INCgt64460rh */ +diff -Naupr u-boot-1.1.6/board/prodrive/p3mx/p3mx.c u-boot-1.1.6-fsl-1/board/prodrive/p3mx/p3mx.c +--- u-boot-1.1.6/board/prodrive/p3mx/p3mx.c 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/p3mx/p3mx.c 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,809 @@ ++/* ++ * (C) Copyright 2006 ++ * Stefan Roese, DENX Software Engineering, sr@denx.de. ++ * ++ * Based on original work by ++ * Roel Loeffen, (C) Copyright 2006 Prodrive B.V. ++ * Josh Huber, (C) Copyright 2001 Mission Critical Linux, Inc. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com ++ * modifications for the cpci750 by reinhard.arlt@esd-electronics.com ++ * modifications for the P3M750 by roel.loeffen@prodrive.nl ++ */ ++ ++/* ++ * p3m750.c - main board support/init for the Prodrive p3m750/p3m7448. ++ */ ++ ++#include ++#include <74xx_7xx.h> ++#include "../../Marvell/include/memory.h" ++#include "../../Marvell/include/pci.h" ++#include "../../Marvell/include/mv_gen_reg.h" ++#include ++#include ++ ++#include "eth.h" ++#include "mpsc.h" ++#include "64460.h" ++#include "mv_regs.h" ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#undef DEBUG ++/*#define DEBUG */ ++ ++#ifdef CONFIG_PCI ++#define MAP_PCI ++#endif /* of CONFIG_PCI */ ++ ++#ifdef DEBUG ++#define DP(x) x ++#else ++#define DP(x) ++#endif ++ ++extern void flush_data_cache (void); ++extern void invalidate_l1_instruction_cache (void); ++extern flash_info_t flash_info[]; ++ ++/* ------------------------------------------------------------------------- */ ++ ++/* this is the current GT register space location */ ++/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */ ++ ++/* Unfortunately, we cant change it while we are in flash, so we initialize it ++ * to the "final" value. This means that any debug_led calls before ++ * board_early_init_f wont work right (like in cpu_init_f). ++ * See also my_remap_gt_regs below. (NTL) ++ */ ++ ++void board_prebootm_init (void); ++unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; ++int display_mem_map (void); ++ ++/* ------------------------------------------------------------------------- */ ++ ++/* ++ * This is a version of the GT register space remapping function that ++ * doesn't touch globals (meaning, it's ok to run from flash.) ++ * ++ * Unfortunately, this has the side effect that a writable ++ * INTERNAL_REG_BASE_ADDR is impossible. Oh well. ++ */ ++ ++void my_remap_gt_regs (u32 cur_loc, u32 new_loc) ++{ ++ u32 temp; ++ ++ /* check and see if it's already moved */ ++ temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); ++ if ((temp & 0xffff) == new_loc >> 16) ++ return; ++ ++ temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & ++ 0xffff0000) | (new_loc >> 16); ++ ++ out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); ++ ++ while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp); ++} ++ ++#ifdef CONFIG_PCI ++ ++static void gt_pci_config (void) ++{ ++ unsigned int stat; ++ unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, */ ++ /* FuncNum 10:8, RegNum 7:2 */ ++ ++ /* ++ * In PCIX mode devices provide their own bus and device numbers. ++ * We query the Discovery II's ++ * config registers by writing ones to the bus and device. ++ * We then update the Virtual register with the correct value for the ++ * bus and device. ++ */ ++ if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /* if PCI-X */ ++ GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); ++ ++ GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat); ++ ++ GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); ++ GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, ++ (stat & 0xffff0000) | CFG_PCI_IDSEL); ++ ++ } ++ if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /* if PCI-X */ ++ GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); ++ GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat); ++ ++ GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); ++ GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, ++ (stat & 0xffff0000) | CFG_PCI_IDSEL); ++ } ++ ++ /* Enable master */ ++ PCI_MASTER_ENABLE (0, SELF); ++ PCI_MASTER_ENABLE (1, SELF); ++ ++ /* Enable PCI0/1 Mem0 and IO 0 disable all others */ ++ GT_REG_READ (BASE_ADDR_ENABLE, &stat); ++ stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | ++ (1 << 18); ++ stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15)); ++ GT_REG_WRITE (BASE_ADDR_ENABLE, stat); ++ ++ /* ronen: ++ * add write to pci remap registers for 64460. ++ * in 64360 when writing to pci base go and overide remap automaticaly, ++ * in 64460 it doesn't ++ */ ++ GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_SPACE >> 16); ++ GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_SPACE_PCI >> 16); ++ GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16); ++ ++ GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16); ++ GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16); ++ GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16); ++ ++ GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_SPACE >> 16); ++ GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_SPACE_PCI >> 16); ++ GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16); ++ ++ GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16); ++ GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16); ++ GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16); ++ ++ /* PCI interface settings */ ++ /* Timeout set to retry forever */ ++ GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0); ++ GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0); ++ ++ /* ronen - enable only CS0 and Internal reg!! */ ++ GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); ++ GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); ++ ++ /* ronen: ++ * update the pci internal registers base address. ++ */ ++#ifdef MAP_PCI ++ for (stat = 0; stat <= PCI_HOST1; stat++) ++ pciWriteConfigReg (stat, ++ PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, ++ SELF, CFG_GT_REGS); ++#endif ++ ++} ++#endif ++ ++/* Setup CPU interface paramaters */ ++static void gt_cpu_config (void) ++{ ++ cpu_t cpu = get_cpu_type (); ++ ulong tmp; ++ ++ /* cpu configuration register */ ++ tmp = GTREGREAD (CPU_CONFIGURATION); ++ /* set the SINGLE_CPU bit see MV64460 */ ++#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ ++ tmp |= CPU_CONF_SINGLE_CPU; ++#endif ++ tmp &= ~CPU_CONF_AACK_DELAY_2; ++ tmp |= CPU_CONF_DP_VALID; ++ tmp |= CPU_CONF_AP_VALID; ++ tmp |= CPU_CONF_PIPELINE; ++ GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */ ++ ++ /* CPU master control register */ ++ tmp = GTREGREAD (CPU_MASTER_CONTROL); ++ tmp |= CPU_MAST_CTL_ARB_EN; ++ ++ if ((cpu == CPU_7400) || ++ (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) { ++ ++ tmp |= CPU_MAST_CTL_CLEAN_BLK; ++ tmp |= CPU_MAST_CTL_FLUSH_BLK; ++ ++ } else { ++ /* cleanblock must be cleared for CPUs ++ * that do not support this command (603e, 750) ++ * see Res#1 */ ++ tmp &= ~CPU_MAST_CTL_CLEAN_BLK; ++ tmp &= ~CPU_MAST_CTL_FLUSH_BLK; ++ } ++ GT_REG_WRITE (CPU_MASTER_CONTROL, tmp); ++} ++ ++/* ++ * board_early_init_f. ++ * ++ * set up gal. device mappings, etc. ++ */ ++int board_early_init_f (void) ++{ ++ /* set up the GT the way the kernel wants it ++ * the call to move the GT register space will obviously ++ * fail if it has already been done, but we're going to assume ++ * that if it's not at the power-on location, it's where we put ++ * it last time. (huber) ++ */ ++ ++ my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS); ++ ++#ifdef CONFIG_PCI ++ gt_pci_config (); ++#endif ++ /* mask all external interrupt sources */ ++ GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0); ++ GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0); ++ /* new in >MV6436x */ ++ GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0); ++ GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0); ++ /* --------------------- */ ++ GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); ++ GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); ++ GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0); ++ GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0); ++ ++ /* Device and Boot bus settings ++ */ ++ memoryMapDeviceSpace(DEVICE0, 0, 0); ++ GT_REG_WRITE(DEVICE_BANK0PARAMETERS, 0); ++ memoryMapDeviceSpace(DEVICE1, 0, 0); ++ GT_REG_WRITE(DEVICE_BANK1PARAMETERS, 0); ++ memoryMapDeviceSpace(DEVICE2, 0, 0); ++ GT_REG_WRITE(DEVICE_BANK2PARAMETERS, 0); ++ memoryMapDeviceSpace(DEVICE3, 0, 0); ++ GT_REG_WRITE(DEVICE_BANK3PARAMETERS, 0); ++ ++ GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_BOOT_PAR); ++ ++ gt_cpu_config(); ++ ++ /* MPP setup */ ++ GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0); ++ GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1); ++ GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2); ++ GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3); ++ ++ GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL); ++ ++ return 0; ++} ++ ++/* various things to do after relocation */ ++ ++int misc_init_r () ++{ ++ u8 val; ++ ++ icache_enable (); ++#ifdef CFG_L2 ++ l2cache_enable (); ++#endif ++#ifdef CONFIG_MPSC ++ mpsc_sdma_init (); ++ mpsc_init2 (); ++#endif ++ ++ /* ++ * Enable trickle changing in RTC upon powerup ++ * No diode, 250 ohm series resistor ++ */ ++ val = 0xa5; ++ i2c_write(CFG_I2C_RTC_ADDR, 8, 1, &val, 1); ++ ++ return 0; ++} ++ ++int board_early_init_r(void) ++{ ++ /* now relocate the debug serial driver */ ++ mpsc_putchar += gd->reloc_off; ++ mpsc_getchar += gd->reloc_off; ++ mpsc_test_char += gd->reloc_off; ++ ++ return 0; ++} ++ ++void after_reloc (ulong dest_addr, gd_t * gd) ++{ ++ memoryMapDeviceSpace (BOOT_DEVICE, CFG_BOOT_SPACE, CFG_BOOT_SIZE); ++ ++/* display_mem_map(); */ ++ ++ /* now, jump to the main U-Boot board init code */ ++ board_init_r (gd, dest_addr); ++ /* NOTREACHED */ ++} ++ ++/* ++ * Check Board Identity: ++ * right now, assume borad type. (there is just one...after all) ++ */ ++ ++int checkboard (void) ++{ ++ char *s = getenv("serial#"); ++ ++ printf("Board: %s", CFG_BOARD_NAME); ++ ++ if (s != NULL) { ++ puts(", serial# "); ++ puts(s); ++ } ++ putc('\n'); ++ ++ return (0); ++} ++ ++/* utility functions */ ++void debug_led (int led, int mode) ++{ ++} ++ ++int display_mem_map (void) ++{ ++ int i, j; ++ unsigned int base, size, width; ++ ++ /* SDRAM */ ++ printf ("SD (DDR) RAM\n"); ++ for (i = 0; i <= BANK3; i++) { ++ base = memoryGetBankBaseAddress (i); ++ size = memoryGetBankSize (i); ++ if (size != 0) ++ printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n", ++ i, base, size >> 20); ++ } ++#ifdef CONFIG_PCI ++ /* CPU's PCI windows */ ++ for (i = 0; i <= PCI_HOST1; i++) { ++ printf ("\nCPU's PCI %d windows\n", i); ++ base = pciGetSpaceBase (i, PCI_IO); ++ size = pciGetSpaceSize (i, PCI_IO); ++ printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base, ++ size >> 20); ++ /* ronen currently only first PCI MEM is used 3 */ ++ for (j = 0; j <= PCI_REGION0; j++) { ++ base = pciGetSpaceBase (i, j); ++ size = pciGetSpaceSize (i, j); ++ printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", ++ j, base, size >> 20); ++ } ++ } ++#endif /* of CONFIG_PCI */ ++ ++ /* Bootrom */ ++ base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */ ++ size = memoryGetDeviceSize (BOOT_DEVICE); ++ width = memoryGetDeviceWidth (BOOT_DEVICE) * 8; ++ printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\t- FLASH\n", ++ base, size >> 20, width); ++ ++ return (0); ++} ++ ++/* DRAM check routines copied from gw8260 */ ++ ++#if defined (CFG_DRAM_TEST) ++ ++/*********************************************************************/ ++/* NAME: move64() - moves a double word (64-bit) */ ++/* */ ++/* DESCRIPTION: */ ++/* this function performs a double word move from the data at */ ++/* the source pointer to the location at the destination pointer. */ ++/* */ ++/* INPUTS: */ ++/* unsigned long long *src - pointer to data to move */ ++/* */ ++/* OUTPUTS: */ ++/* unsigned long long *dest - pointer to locate to move data */ ++/* */ ++/* RETURNS: */ ++/* None */ ++/* */ ++/* RESTRICTIONS/LIMITATIONS: */ ++/* May cloober fr0. */ ++/* */ ++/*********************************************************************/ ++static void move64 (unsigned long long *src, unsigned long long *dest) ++{ ++ asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ ++ "stfd 0, 0(4)" /* *dest = fpr0 */ ++ : : : "fr0"); /* Clobbers fr0 */ ++ return; ++} ++ ++ ++#if defined (CFG_DRAM_TEST_DATA) ++ ++unsigned long long pattern[] = { ++ 0xaaaaaaaaaaaaaaaaULL, ++ 0xccccccccccccccccULL, ++ 0xf0f0f0f0f0f0f0f0ULL, ++ 0xff00ff00ff00ff00ULL, ++ 0xffff0000ffff0000ULL, ++ 0xffffffff00000000ULL, ++ 0x00000000ffffffffULL, ++ 0x0000ffff0000ffffULL, ++ 0x00ff00ff00ff00ffULL, ++ 0x0f0f0f0f0f0f0f0fULL, ++ 0x3333333333333333ULL, ++ 0x5555555555555555ULL ++}; ++ ++/*********************************************************************/ ++/* NAME: mem_test_data() - test data lines for shorts and opens */ ++/* */ ++/* DESCRIPTION: */ ++/* Tests data lines for shorts and opens by forcing adjacent data */ ++/* to opposite states. Because the data lines could be routed in */ ++/* an arbitrary manner the must ensure test patterns ensure that */ ++/* every case is tested. By using the following series of binary */ ++/* patterns every combination of adjacent bits is test regardless */ ++/* of routing. */ ++/* */ ++/* ...101010101010101010101010 */ ++/* ...110011001100110011001100 */ ++/* ...111100001111000011110000 */ ++/* ...111111110000000011111111 */ ++/* */ ++/* Carrying this out, gives us six hex patterns as follows: */ ++/* */ ++/* 0xaaaaaaaaaaaaaaaa */ ++/* 0xcccccccccccccccc */ ++/* 0xf0f0f0f0f0f0f0f0 */ ++/* 0xff00ff00ff00ff00 */ ++/* 0xffff0000ffff0000 */ ++/* 0xffffffff00000000 */ ++/* */ ++/* The number test patterns will always be given by: */ ++/* */ ++/* log(base 2)(number data bits) = log2 (64) = 6 */ ++/* */ ++/* To test for short and opens to other signals on our boards. we */ ++/* simply */ ++/* test with the 1's complemnt of the paterns as well. */ ++/* */ ++/* OUTPUTS: */ ++/* Displays failing test pattern */ ++/* */ ++/* RETURNS: */ ++/* 0 - Passed test */ ++/* 1 - Failed test */ ++/* */ ++/* RESTRICTIONS/LIMITATIONS: */ ++/* Assumes only one one SDRAM bank */ ++/* */ ++/*********************************************************************/ ++int mem_test_data (void) ++{ ++ unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START; ++ unsigned long long temp64 = 0; ++ int num_patterns = sizeof (pattern) / sizeof (pattern[0]); ++ int i; ++ unsigned int hi, lo; ++ ++ for (i = 0; i < num_patterns; i++) { ++ move64 (&(pattern[i]), pmem); ++ move64 (pmem, &temp64); ++ ++ /* hi = (temp64>>32) & 0xffffffff; */ ++ /* lo = temp64 & 0xffffffff; */ ++ /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ ++ ++ hi = (pattern[i] >> 32) & 0xffffffff; ++ lo = pattern[i] & 0xffffffff; ++ /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */ ++ ++ if (temp64 != pattern[i]) { ++ printf ("\n Data Test Failed, pattern 0x%08x%08x", ++ hi, lo); ++ return 1; ++ } ++ } ++ ++ return 0; ++} ++#endif /* CFG_DRAM_TEST_DATA */ ++ ++#if defined (CFG_DRAM_TEST_ADDRESS) ++/*********************************************************************/ ++/* NAME: mem_test_address() - test address lines */ ++/* */ ++/* DESCRIPTION: */ ++/* This function performs a test to verify that each word im */ ++/* memory is uniquly addressable. The test sequence is as follows: */ ++/* */ ++/* 1) write the address of each word to each word. */ ++/* 2) verify that each location equals its address */ ++/* */ ++/* OUTPUTS: */ ++/* Displays failing test pattern and address */ ++/* */ ++/* RETURNS: */ ++/* 0 - Passed test */ ++/* 1 - Failed test */ ++/* */ ++/* RESTRICTIONS/LIMITATIONS: */ ++/* */ ++/* */ ++/*********************************************************************/ ++int mem_test_address (void) ++{ ++ volatile unsigned int *pmem = ++ (volatile unsigned int *) CFG_MEMTEST_START; ++ const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4; ++ unsigned int i; ++ ++ /* write address to each location */ ++ for (i = 0; i < size; i++) ++ pmem[i] = i; ++ ++ /* verify each loaction */ ++ for (i = 0; i < size; i++) { ++ if (pmem[i] != i) { ++ printf ("\n Address Test Failed at 0x%x", i); ++ return 1; ++ } ++ } ++ return 0; ++} ++#endif /* CFG_DRAM_TEST_ADDRESS */ ++ ++#if defined (CFG_DRAM_TEST_WALK) ++/*********************************************************************/ ++/* NAME: mem_march() - memory march */ ++/* */ ++/* DESCRIPTION: */ ++/* Marches up through memory. At each location verifies rmask if */ ++/* read = 1. At each location write wmask if write = 1. Displays */ ++/* failing address and pattern. */ ++/* */ ++/* INPUTS: */ ++/* volatile unsigned long long * base - start address of test */ ++/* unsigned int size - number of dwords(64-bit) to test */ ++/* unsigned long long rmask - read verify mask */ ++/* unsigned long long wmask - wrtie verify mask */ ++/* short read - verifies rmask if read = 1 */ ++/* short write - writes wmask if write = 1 */ ++/* */ ++/* OUTPUTS: */ ++/* Displays failing test pattern and address */ ++/* */ ++/* RETURNS: */ ++/* 0 - Passed test */ ++/* 1 - Failed test */ ++/* */ ++/* RESTRICTIONS/LIMITATIONS: */ ++/* */ ++/* */ ++/*********************************************************************/ ++int mem_march (volatile unsigned long long *base, ++ unsigned int size, ++ unsigned long long rmask, ++ unsigned long long wmask, short read, short write) ++{ ++ unsigned int i; ++ unsigned long long temp = 0; ++ unsigned int hitemp, lotemp, himask, lomask; ++ ++ for (i = 0; i < size; i++) { ++ if (read != 0) { ++ /* temp = base[i]; */ ++ move64 ((unsigned long long *) &(base[i]), &temp); ++ if (rmask != temp) { ++ hitemp = (temp >> 32) & 0xffffffff; ++ lotemp = temp & 0xffffffff; ++ himask = (rmask >> 32) & 0xffffffff; ++ lomask = rmask & 0xffffffff; ++ ++ printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp); ++ return 1; ++ } ++ } ++ if (write != 0) { ++ /* base[i] = wmask; */ ++ move64 (&wmask, (unsigned long long *) &(base[i])); ++ } ++ } ++ return 0; ++} ++#endif /* CFG_DRAM_TEST_WALK */ ++ ++/*********************************************************************/ ++/* NAME: mem_test_walk() - a simple walking ones test */ ++/* */ ++/* DESCRIPTION: */ ++/* Performs a walking ones through entire physical memory. The */ ++/* test uses as series of memory marches, mem_march(), to verify */ ++/* and write the test patterns to memory. The test sequence is as */ ++/* follows: */ ++/* 1) march writing 0000...0001 */ ++/* 2) march verifying 0000...0001 , writing 0000...0010 */ ++/* 3) repeat step 2 shifting masks left 1 bit each time unitl */ ++/* the write mask equals 1000...0000 */ ++/* 4) march verifying 1000...0000 */ ++/* The test fails if any of the memory marches return a failure. */ ++/* */ ++/* OUTPUTS: */ ++/* Displays which pass on the memory test is executing */ ++/* */ ++/* RETURNS: */ ++/* 0 - Passed test */ ++/* 1 - Failed test */ ++/* */ ++/* RESTRICTIONS/LIMITATIONS: */ ++/* */ ++/* */ ++/*********************************************************************/ ++int mem_test_walk (void) ++{ ++ unsigned long long mask; ++ volatile unsigned long long *pmem = ++ (volatile unsigned long long *) CFG_MEMTEST_START; ++ const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8; ++ ++ unsigned int i; ++ ++ mask = 0x01; ++ ++ printf ("Initial Pass"); ++ mem_march (pmem, size, 0x0, 0x1, 0, 1); ++ ++ printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); ++ printf (" "); ++ printf (" "); ++ printf ("\b\b\b\b\b\b\b\b\b\b\b\b"); ++ ++ for (i = 0; i < 63; i++) { ++ printf ("Pass %2d", i + 2); ++ if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) { ++ /*printf("mask: 0x%x, pass: %d, ", mask, i); */ ++ return 1; ++ } ++ mask = mask << 1; ++ printf ("\b\b\b\b\b\b\b"); ++ } ++ ++ printf ("Last Pass"); ++ if (mem_march (pmem, size, 0, mask, 0, 1) != 0) { ++ /* printf("mask: 0x%x", mask); */ ++ return 1; ++ } ++ printf ("\b\b\b\b\b\b\b\b\b"); ++ printf (" "); ++ printf ("\b\b\b\b\b\b\b\b\b"); ++ ++ return 0; ++} ++ ++/*********************************************************************/ ++/* NAME: testdram() - calls any enabled memory tests */ ++/* */ ++/* DESCRIPTION: */ ++/* Runs memory tests if the environment test variables are set to */ ++/* 'y'. */ ++/* */ ++/* INPUTS: */ ++/* testdramdata - If set to 'y', data test is run. */ ++/* testdramaddress - If set to 'y', address test is run. */ ++/* testdramwalk - If set to 'y', walking ones test is run */ ++/* */ ++/* OUTPUTS: */ ++/* None */ ++/* */ ++/* RETURNS: */ ++/* 0 - Passed test */ ++/* 1 - Failed test */ ++/* */ ++/* RESTRICTIONS/LIMITATIONS: */ ++/* */ ++/* */ ++/*********************************************************************/ ++int testdram (void) ++{ ++ char *s; ++ int rundata = 0; ++ int runaddress = 0; ++ int runwalk = 0; ++ ++#ifdef CFG_DRAM_TEST_DATA ++ s = getenv ("testdramdata"); ++ rundata = (s && (*s == 'y')) ? 1 : 0; ++#endif ++#ifdef CFG_DRAM_TEST_ADDRESS ++ s = getenv ("testdramaddress"); ++ runaddress = (s && (*s == 'y')) ? 1 : 0; ++#endif ++#ifdef CFG_DRAM_TEST_WALK ++ s = getenv ("testdramwalk"); ++ runwalk = (s && (*s == 'y')) ? 1 : 0; ++#endif ++ ++ if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) ++ printf ("Testing RAM from 0x%08x to 0x%08x ... " ++ "(don't panic... that will take a moment !!!!)\n", ++ CFG_MEMTEST_START, CFG_MEMTEST_END); ++#ifdef CFG_DRAM_TEST_DATA ++ if (rundata == 1) { ++ printf ("Test DATA ... "); ++ if (mem_test_data () == 1) { ++ printf ("failed \n"); ++ return 1; ++ } else ++ printf ("ok \n"); ++ } ++#endif ++#ifdef CFG_DRAM_TEST_ADDRESS ++ if (runaddress == 1) { ++ printf ("Test ADDRESS ... "); ++ if (mem_test_address () == 1) { ++ printf ("failed \n"); ++ return 1; ++ } else ++ printf ("ok \n"); ++ } ++#endif ++#ifdef CFG_DRAM_TEST_WALK ++ if (runwalk == 1) { ++ printf ("Test WALKING ONEs ... "); ++ if (mem_test_walk () == 1) { ++ printf ("failed \n"); ++ return 1; ++ } else ++ printf ("ok \n"); ++ } ++#endif ++ if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) ++ printf ("passed\n"); ++ return 0; ++ ++} ++#endif /* CFG_DRAM_TEST */ ++ ++/* ronen - the below functions are used by the bootm function */ ++/* - we map the base register to fbe00000 (same mapping as in the LSP) */ ++/* - we turn off the RX gig dmas - to prevent the dma from overunning */ ++/* the kernel data areas. */ ++/* - we diable and invalidate the icache and dcache. */ ++void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc) ++{ ++ u32 temp; ++ ++ temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE)); ++ if ((temp & 0xffff) == new_loc >> 16) ++ return; ++ ++ temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) & ++ 0xffff0000) | (new_loc >> 16); ++ ++ out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp); ++ ++ while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE | ++ new_loc | ++ (INTERNAL_SPACE_DECODE))))) ++ != temp); ++ ++} +diff -Naupr u-boot-1.1.6/board/prodrive/p3mx/pci.c u-boot-1.1.6-fsl-1/board/prodrive/p3mx/pci.c +--- u-boot-1.1.6/board/prodrive/p3mx/pci.c 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/p3mx/pci.c 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,1025 @@ ++/* ++ * (C) Copyright 2000 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++/* PCI.c - PCI functions */ ++ ++ ++#include ++#ifdef CONFIG_PCI ++#include ++ ++#ifdef CONFIG_PCI_PNP ++void pciauto_config_init(struct pci_controller *hose); ++int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar); ++#endif ++ ++#include "../../Marvell/include/pci.h" ++ ++#undef DEBUG ++#undef IDE_SET_NATIVE_MODE ++static unsigned int local_buses[] = { 0, 0 }; ++ ++static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { ++ {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 }, ++ {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 }, ++}; ++ ++#ifdef CONFIG_USE_CPCIDVI ++typedef struct { ++ unsigned int base; ++ unsigned int init; ++} GT_CPCIDVI_ROM_T; ++ ++static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0}; ++#endif ++ ++#ifdef DEBUG ++static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE }; ++static void gt_pci_bus_mode_display (PCI_HOST host) ++{ ++ unsigned int mode; ++ ++ ++ mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4; ++ switch (mode) { ++ case 0: ++ printf ("PCI %d bus mode: Conventional PCI\n", host); ++ break; ++ case 1: ++ printf ("PCI %d bus mode: 66 Mhz PCIX\n", host); ++ break; ++ case 2: ++ printf ("PCI %d bus mode: 100 Mhz PCIX\n", host); ++ break; ++ case 3: ++ printf ("PCI %d bus mode: 133 Mhz PCIX\n", host); ++ break; ++ default: ++ printf ("Unknown BUS %d\n", mode); ++ } ++} ++#endif ++ ++static const unsigned int pci_p2p_configuration_reg[] = { ++ PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION ++}; ++ ++static const unsigned int pci_configuration_address[] = { ++ PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS ++}; ++ ++static const unsigned int pci_configuration_data[] = { ++ PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, ++ PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER ++}; ++ ++static const unsigned int pci_error_cause_reg[] = { ++ PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE ++}; ++ ++static const unsigned int pci_arbiter_control[] = { ++ PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL ++}; ++ ++static const unsigned int pci_address_space_en[] = { ++ PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE ++}; ++ ++static const unsigned int pci_snoop_control_base_0_low[] = { ++ PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW ++}; ++static const unsigned int pci_snoop_control_top_0[] = { ++ PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0 ++}; ++ ++static const unsigned int pci_access_control_base_0_low[] = { ++ PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW ++}; ++static const unsigned int pci_access_control_top_0[] = { ++ PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0 ++}; ++ ++static const unsigned int pci_scs_bank_size[2][4] = { ++ {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE, ++ PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE}, ++ {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE, ++ PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE} ++}; ++ ++static const unsigned int pci_p2p_configuration[] = { ++ PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION ++}; ++ ++ ++/******************************************************************** ++* pciWriteConfigReg - Write to a PCI configuration register ++* - Make sure the GT is configured as a master before writing ++* to another device on the PCI. ++* - The function takes care of Big/Little endian conversion. ++* ++* ++* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec ++* (or any other PCI device spec) ++* pciDevNum: The device number needs to be addressed. ++* ++* Configuration Address 0xCF8: ++* ++* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number ++* |congif|Reserved| Bus |Device|Function|Register|00| ++* |Enable| |Number|Number| Number | Number | | <=field Name ++* ++*********************************************************************/ ++void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, ++ unsigned int pciDevNum, unsigned int data) ++{ ++ volatile unsigned int DataForAddrReg; ++ unsigned int functionNum; ++ unsigned int busNum = 0; ++ unsigned int addr; ++ ++ if (pciDevNum > 32) /* illegal device Number */ ++ return; ++ if (pciDevNum == SELF) { /* configure our configuration space. */ ++ pciDevNum = ++ (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & ++ 0x1f; ++ busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & ++ 0xff0000; ++ } ++ functionNum = regOffset & 0x00000700; ++ pciDevNum = pciDevNum << 11; ++ regOffset = regOffset & 0xfc; ++ DataForAddrReg = ++ (regOffset | pciDevNum | functionNum | busNum) | BIT31; ++ GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); ++ GT_REG_READ (pci_configuration_address[host], &addr); ++ if (addr != DataForAddrReg) ++ return; ++ GT_REG_WRITE (pci_configuration_data[host], data); ++} ++ ++/******************************************************************** ++* pciReadConfigReg - Read from a PCI0 configuration register ++* - Make sure the GT is configured as a master before reading ++* from another device on the PCI. ++* - The function takes care of Big/Little endian conversion. ++* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI ++* spec) ++* pciDevNum: The device number needs to be addressed. ++* RETURNS: data , if the data == 0xffffffff check the master abort bit in the ++* cause register to make sure the data is valid ++* ++* Configuration Address 0xCF8: ++* ++* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number ++* |congif|Reserved| Bus |Device|Function|Register|00| ++* |Enable| |Number|Number| Number | Number | | <=field Name ++* ++*********************************************************************/ ++unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, ++ unsigned int pciDevNum) ++{ ++ volatile unsigned int DataForAddrReg; ++ unsigned int data; ++ unsigned int functionNum; ++ unsigned int busNum = 0; ++ ++ if (pciDevNum > 32) /* illegal device Number */ ++ return 0xffffffff; ++ if (pciDevNum == SELF) { /* configure our configuration space. */ ++ pciDevNum = ++ (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) & ++ 0x1f; ++ busNum = GTREGREAD (pci_p2p_configuration_reg[host]) & ++ 0xff0000; ++ } ++ functionNum = regOffset & 0x00000700; ++ pciDevNum = pciDevNum << 11; ++ regOffset = regOffset & 0xfc; ++ DataForAddrReg = ++ (regOffset | pciDevNum | functionNum | busNum) | BIT31; ++ GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg); ++ GT_REG_READ (pci_configuration_address[host], &data); ++ if (data != DataForAddrReg) ++ return 0xffffffff; ++ GT_REG_READ (pci_configuration_data[host], &data); ++ return data; ++} ++ ++/******************************************************************** ++* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where ++* the agent is placed on another Bus. For more ++* information read P2P in the PCI spec. ++* ++* Inputs: unsigned int regOffset - The register offset as it apears in the ++* GT spec (or any other PCI device spec). ++* unsigned int pciDevNum - The device number needs to be addressed. ++* unsigned int busNum - On which bus does the Target agent connect ++* to. ++* unsigned int data - data to be written. ++* ++* Configuration Address 0xCF8: ++* ++* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number ++* |congif|Reserved| Bus |Device|Function|Register|01| ++* |Enable| |Number|Number| Number | Number | | <=field Name ++* ++* The configuration Address is configure as type-I (bits[1:0] = '01') due to ++* PCI spec referring to P2P. ++* ++*********************************************************************/ ++void pciOverBridgeWriteConfigReg (PCI_HOST host, ++ unsigned int regOffset, ++ unsigned int pciDevNum, ++ unsigned int busNum, unsigned int data) ++{ ++ unsigned int DataForReg; ++ unsigned int functionNum; ++ ++ functionNum = regOffset & 0x00000700; ++ pciDevNum = pciDevNum << 11; ++ regOffset = regOffset & 0xff; ++ busNum = busNum << 16; ++ if (pciDevNum == SELF) { /* This board */ ++ DataForReg = (regOffset | pciDevNum | functionNum) | BIT0; ++ } else { ++ DataForReg = (regOffset | pciDevNum | functionNum | busNum) | ++ BIT31 | BIT0; ++ } ++ GT_REG_WRITE (pci_configuration_address[host], DataForReg); ++ GT_REG_WRITE (pci_configuration_data[host], data); ++} ++ ++ ++/******************************************************************** ++* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where ++* the agent target locate on another PCI bus. ++* - Make sure the GT is configured as a master ++* before reading from another device on the PCI. ++* - The function takes care of Big/Little endian ++* conversion. ++* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI ++* spec). (configuration register offset.) ++* pciDevNum: The device number needs to be addressed. ++* busNum: the Bus number where the agent is place. ++* RETURNS: data , if the data == 0xffffffff check the master abort bit in the ++* cause register to make sure the data is valid ++* ++* Configuration Address 0xCF8: ++* ++* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number ++* |congif|Reserved| Bus |Device|Function|Register|01| ++* |Enable| |Number|Number| Number | Number | | <=field Name ++* ++*********************************************************************/ ++unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, ++ unsigned int regOffset, ++ unsigned int pciDevNum, ++ unsigned int busNum) ++{ ++ unsigned int DataForReg; ++ unsigned int data; ++ unsigned int functionNum; ++ ++ functionNum = regOffset & 0x00000700; ++ pciDevNum = pciDevNum << 11; ++ regOffset = regOffset & 0xff; ++ busNum = busNum << 16; ++ if (pciDevNum == SELF) { /* This board */ ++ DataForReg = (regOffset | pciDevNum | functionNum) | BIT31; ++ } else { /* agent on another bus */ ++ ++ DataForReg = (regOffset | pciDevNum | functionNum | busNum) | ++ BIT0 | BIT31; ++ } ++ GT_REG_WRITE (pci_configuration_address[host], DataForReg); ++ GT_REG_READ (pci_configuration_data[host], &data); ++ return data; ++} ++ ++ ++/******************************************************************** ++* pciGetRegOffset - Gets the register offset for this region config. ++* ++* INPUT: Bus, Region - The bus and region we ask for its base address. ++* OUTPUT: N/A ++* RETURNS: PCI register base address ++*********************************************************************/ ++static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region) ++{ ++ switch (host) { ++ case PCI_HOST0: ++ switch (region) { ++ case PCI_IO: ++ return PCI_0I_O_LOW_DECODE_ADDRESS; ++ case PCI_REGION0: ++ return PCI_0MEMORY0_LOW_DECODE_ADDRESS; ++ case PCI_REGION1: ++ return PCI_0MEMORY1_LOW_DECODE_ADDRESS; ++ case PCI_REGION2: ++ return PCI_0MEMORY2_LOW_DECODE_ADDRESS; ++ case PCI_REGION3: ++ return PCI_0MEMORY3_LOW_DECODE_ADDRESS; ++ } ++ case PCI_HOST1: ++ switch (region) { ++ case PCI_IO: ++ return PCI_1I_O_LOW_DECODE_ADDRESS; ++ case PCI_REGION0: ++ return PCI_1MEMORY0_LOW_DECODE_ADDRESS; ++ case PCI_REGION1: ++ return PCI_1MEMORY1_LOW_DECODE_ADDRESS; ++ case PCI_REGION2: ++ return PCI_1MEMORY2_LOW_DECODE_ADDRESS; ++ case PCI_REGION3: ++ return PCI_1MEMORY3_LOW_DECODE_ADDRESS; ++ } ++ } ++ return PCI_0MEMORY0_LOW_DECODE_ADDRESS; ++} ++ ++static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) ++{ ++ switch (host) { ++ case PCI_HOST0: ++ switch (region) { ++ case PCI_IO: ++ return PCI_0I_O_ADDRESS_REMAP; ++ case PCI_REGION0: ++ return PCI_0MEMORY0_ADDRESS_REMAP; ++ case PCI_REGION1: ++ return PCI_0MEMORY1_ADDRESS_REMAP; ++ case PCI_REGION2: ++ return PCI_0MEMORY2_ADDRESS_REMAP; ++ case PCI_REGION3: ++ return PCI_0MEMORY3_ADDRESS_REMAP; ++ } ++ case PCI_HOST1: ++ switch (region) { ++ case PCI_IO: ++ return PCI_1I_O_ADDRESS_REMAP; ++ case PCI_REGION0: ++ return PCI_1MEMORY0_ADDRESS_REMAP; ++ case PCI_REGION1: ++ return PCI_1MEMORY1_ADDRESS_REMAP; ++ case PCI_REGION2: ++ return PCI_1MEMORY2_ADDRESS_REMAP; ++ case PCI_REGION3: ++ return PCI_1MEMORY3_ADDRESS_REMAP; ++ } ++ } ++ return PCI_0MEMORY0_ADDRESS_REMAP; ++} ++ ++/******************************************************************** ++* pciGetBaseAddress - Gets the base address of a PCI. ++* - If the PCI size is 0 then this base address has no meaning!!! ++* ++* ++* INPUT: Bus, Region - The bus and region we ask for its base address. ++* OUTPUT: N/A ++* RETURNS: PCI base address. ++*********************************************************************/ ++unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region) ++{ ++ unsigned int regBase; ++ unsigned int regEnd; ++ unsigned int regOffset = pciGetRegOffset (host, region); ++ ++ GT_REG_READ (regOffset, ®Base); ++ GT_REG_READ (regOffset + 8, ®End); ++ ++ if (regEnd <= regBase) ++ return 0xffffffff; /* ERROR !!! */ ++ ++ regBase = regBase << 16; ++ return regBase; ++} ++ ++bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase, ++ unsigned int bankBase, unsigned int bankLength) ++{ ++ unsigned int low = 0xfff; ++ unsigned int high = 0x0; ++ unsigned int regOffset = pciGetRegOffset (host, region); ++ unsigned int remapOffset = pciGetRemapOffset (host, region); ++ ++ if (bankLength != 0) { ++ low = (bankBase >> 16) & 0xffff; ++ high = ((bankBase + bankLength) >> 16) - 1; ++ } ++ ++ GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */ ++ GT_REG_WRITE (regOffset + 8, high); ++ ++ if (bankLength != 0) { /* must do AFTER writing maps */ ++ GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only. ++ dont support upper 32 ++ in this driver */ ++ } ++ return true; ++} ++ ++unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region) ++{ ++ unsigned int low; ++ unsigned int regOffset = pciGetRegOffset (host, region); ++ ++ GT_REG_READ (regOffset, &low); ++ return (low & 0xffff) << 16; ++} ++ ++unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region) ++{ ++ unsigned int low, high; ++ unsigned int regOffset = pciGetRegOffset (host, region); ++ ++ GT_REG_READ (regOffset, &low); ++ GT_REG_READ (regOffset + 8, &high); ++ return ((high & 0xffff) + 1) << 16; ++} ++ ++ ++/* ronen - 7/Dec/03*/ ++/******************************************************************** ++* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS. ++* Inputs: one of the PCI BAR ++*********************************************************************/ ++void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) ++{ ++ RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); ++} ++ ++void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR) ++{ ++ SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR); ++} ++ ++/******************************************************************** ++* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave. ++* ++* Inputs: base and size of PCI SCS ++*********************************************************************/ ++void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, ++ unsigned int pciDramBase, unsigned int pciDramSize) ++{ ++ /*ronen different function for 3rd bank. */ ++ unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8; ++ ++ pciDramBase = pciDramBase & 0xfffff000; ++ pciDramBase = pciDramBase | (pciReadConfigReg (host, ++ PCI_SCS_0_BASE_ADDRESS ++ + offset, ++ SELF) & 0x00000fff); ++ pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF, ++ pciDramBase); ++ if (pciDramSize == 0) ++ pciDramSize++; ++ GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1); ++ gtPciEnableInternalBAR (host, bank); ++} ++ ++/******************************************************************** ++* pciSetRegionFeatures - This function modifys one of the 8 regions with ++* feature bits given as an input. ++* - Be advised to check the spec before modifying them. ++* Inputs: PCI_PROTECT_REGION region - one of the eight regions. ++* unsigned int features - See file: pci.h there are defintion for those ++* region features. ++* unsigned int baseAddress - The region base Address. ++* unsigned int topAddress - The region top Address. ++* Returns: false if one of the parameters is erroneous true otherwise. ++*********************************************************************/ ++bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, ++ unsigned int features, unsigned int baseAddress, ++ unsigned int regionLength) ++{ ++ unsigned int accessLow; ++ unsigned int accessHigh; ++ unsigned int accessTop = baseAddress + regionLength; ++ ++ if (regionLength == 0) { /* close the region. */ ++ pciDisableAccessRegion (host, region); ++ return true; ++ } ++ /* base Address is store is bits [11:0] */ ++ accessLow = (baseAddress & 0xfff00000) >> 20; ++ /* All the features are update according to the defines in pci.h (to be on ++ the safe side we disable bits: [11:0] */ ++ accessLow = accessLow | (features & 0xfffff000); ++ /* write to the Low Access Region register */ ++ GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, ++ accessLow); ++ ++ accessHigh = (accessTop & 0xfff00000) >> 20; ++ ++ /* write to the High Access Region register */ ++ GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, ++ accessHigh - 1); ++ return true; ++} ++ ++/******************************************************************** ++* pciDisableAccessRegion - Disable The given Region by writing MAX size ++* to its low Address and MIN size to its high Address. ++* ++* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. ++* Returns: N/A. ++*********************************************************************/ ++void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region) ++{ ++ /* writing back the registers default values. */ ++ GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region, ++ 0x01001fff); ++ GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0); ++} ++ ++/******************************************************************** ++* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism. ++* ++* Inputs: N/A ++* Returns: true. ++*********************************************************************/ ++bool pciArbiterEnable (PCI_HOST host) ++{ ++ unsigned int regData; ++ ++ GT_REG_READ (pci_arbiter_control[host], ®Data); ++ GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31); ++ return true; ++} ++ ++/******************************************************************** ++* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism. ++* ++* Inputs: N/A ++* Returns: true ++*********************************************************************/ ++bool pciArbiterDisable (PCI_HOST host) ++{ ++ unsigned int regData; ++ ++ GT_REG_READ (pci_arbiter_control[host], ®Data); ++ GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff); ++ return true; ++} ++ ++/******************************************************************** ++* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) ++* ++* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. ++* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. ++* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. ++* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. ++* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. ++* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. ++* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. ++* Returns: true ++*********************************************************************/ ++bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, ++ PCI_AGENT_PRIO externalAgent0, ++ PCI_AGENT_PRIO externalAgent1, ++ PCI_AGENT_PRIO externalAgent2, ++ PCI_AGENT_PRIO externalAgent3, ++ PCI_AGENT_PRIO externalAgent4, ++ PCI_AGENT_PRIO externalAgent5) ++{ ++ unsigned int regData; ++ unsigned int writeData; ++ ++ GT_REG_READ (pci_arbiter_control[host], ®Data); ++ writeData = (internalAgent << 7) + (externalAgent0 << 8) + ++ (externalAgent1 << 9) + (externalAgent2 << 10) + ++ (externalAgent3 << 11) + (externalAgent4 << 12) + ++ (externalAgent5 << 13); ++ regData = (regData & 0xffffc07f) | writeData; ++ GT_REG_WRITE (pci_arbiter_control[host], regData & regData); ++ return true; ++} ++ ++/******************************************************************** ++* pciParkingDisable - Park on last option disable, with this function you can ++* disable the park on last mechanism for each agent. ++* disabling this option for all agents results parking ++* on the internal master. ++* ++* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. ++* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. ++* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. ++* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. ++* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. ++* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. ++* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. ++* Returns: true ++*********************************************************************/ ++bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, ++ PCI_AGENT_PARK externalAgent0, ++ PCI_AGENT_PARK externalAgent1, ++ PCI_AGENT_PARK externalAgent2, ++ PCI_AGENT_PARK externalAgent3, ++ PCI_AGENT_PARK externalAgent4, ++ PCI_AGENT_PARK externalAgent5) ++{ ++ unsigned int regData; ++ unsigned int writeData; ++ ++ GT_REG_READ (pci_arbiter_control[host], ®Data); ++ writeData = (internalAgent << 14) + (externalAgent0 << 15) + ++ (externalAgent1 << 16) + (externalAgent2 << 17) + ++ (externalAgent3 << 18) + (externalAgent4 << 19) + ++ (externalAgent5 << 20); ++ regData = (regData & ~(0x7f << 14)) | writeData; ++ GT_REG_WRITE (pci_arbiter_control[host], regData); ++ return true; ++} ++ ++/******************************************************************** ++* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to ++* respond to grant assertion within a window specified in ++* the input value: 'brokenValue'. ++* ++* Inputs: unsigned char brokenValue - A value which limits the Master to hold the ++* grant without asserting frame. ++* Returns: Error for illegal broken value otherwise true. ++*********************************************************************/ ++bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) ++{ ++ unsigned int data; ++ unsigned int regData; ++ ++ if (brokenValue > 0xf) ++ return false; /* brokenValue must be 4 bit */ ++ data = brokenValue << 3; ++ GT_REG_READ (pci_arbiter_control[host], ®Data); ++ regData = (regData & 0xffffff87) | data; ++ GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1); ++ return true; ++} ++ ++/******************************************************************** ++* pciDisableBrokenAgentDetection - This function disable the Broken agent ++* Detection mechanism. ++* NOTE: This operation may cause a dead lock on the ++* pci0 arbitration. ++* ++* Inputs: N/A ++* Returns: true. ++*********************************************************************/ ++bool pciDisableBrokenAgentDetection (PCI_HOST host) ++{ ++ unsigned int regData; ++ ++ GT_REG_READ (pci_arbiter_control[host], ®Data); ++ regData = regData & 0xfffffffd; ++ GT_REG_WRITE (pci_arbiter_control[host], regData); ++ return true; ++} ++ ++/******************************************************************** ++* pciP2PConfig - This function set the PCI_n P2P configurate. ++* For more information on the P2P read PCI spec. ++* ++* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower ++* Boundry. ++* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper ++* Boundry. ++* unsigned int busNum - The CPI bus number to which the PCI interface ++* is connected. ++* unsigned int devNum - The PCI interface's device number. ++* ++* Returns: true. ++*********************************************************************/ ++bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow, ++ unsigned int SecondBusHigh, ++ unsigned int busNum, unsigned int devNum) ++{ ++ unsigned int regData; ++ ++ regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) | ++ ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24); ++ GT_REG_WRITE (pci_p2p_configuration[host], regData); ++ return true; ++} ++ ++/******************************************************************** ++* pciSetRegionSnoopMode - This function modifys one of the 4 regions which ++* supports Cache Coherency in the PCI_n interface. ++* Inputs: region - One of the four regions. ++* snoopType - There is four optional Types: ++* 1. No Snoop. ++* 2. Snoop to WT region. ++* 3. Snoop to WB region. ++* 4. Snoop & Invalidate to WB region. ++* baseAddress - Base Address of this region. ++* regionLength - Region length. ++* Returns: false if one of the parameters is wrong otherwise return true. ++*********************************************************************/ ++bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, ++ PCI_SNOOP_TYPE snoopType, ++ unsigned int baseAddress, ++ unsigned int regionLength) ++{ ++ unsigned int snoopXbaseAddress; ++ unsigned int snoopXtopAddress; ++ unsigned int data; ++ unsigned int snoopHigh = baseAddress + regionLength; ++ ++ if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB)) ++ return false; ++ snoopXbaseAddress = ++ pci_snoop_control_base_0_low[host] + 0x10 * region; ++ snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region; ++ if (regionLength == 0) { /* closing the region */ ++ GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff); ++ GT_REG_WRITE (snoopXtopAddress, 0); ++ return true; ++ } ++ baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ ++ data = (baseAddress >> 20) | snoopType << 12; ++ GT_REG_WRITE (snoopXbaseAddress, data); ++ snoopHigh = (snoopHigh & 0xfff00000) >> 20; ++ GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1); ++ return true; ++} ++ ++static int gt_read_config_dword (struct pci_controller *hose, ++ pci_dev_t dev, int offset, u32 * value) ++{ ++ int bus = PCI_BUS (dev); ++ ++ if ((bus == local_buses[0]) || (bus == local_buses[1])) { ++ *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset, ++ PCI_DEV (dev)); ++ } else { ++ *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose-> ++ cfg_addr, offset, ++ PCI_DEV (dev), bus); ++ } ++ ++ return 0; ++} ++ ++static int gt_write_config_dword (struct pci_controller *hose, ++ pci_dev_t dev, int offset, u32 value) ++{ ++ int bus = PCI_BUS (dev); ++ ++ if ((bus == local_buses[0]) || (bus == local_buses[1])) { ++ pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset, ++ PCI_DEV (dev), value); ++ } else { ++ pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr, ++ offset, PCI_DEV (dev), bus, ++ value); ++ } ++ return 0; ++} ++ ++ ++static void gt_setup_ide (struct pci_controller *hose, ++ pci_dev_t dev, struct pci_config_table *entry) ++{ ++ static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 }; ++ u32 bar_response, bar_value; ++ int bar; ++ ++ for (bar = 0; bar < 6; bar++) { ++ /*ronen different function for 3rd bank. */ ++ unsigned int offset = ++ (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8; ++ ++ pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset, ++ 0x0); ++ pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset, ++ &bar_response); ++ ++ pciauto_region_allocate (bar_response & ++ PCI_BASE_ADDRESS_SPACE_IO ? hose-> ++ pci_io : hose->pci_mem, ide_bar[bar], ++ &bar_value); ++ ++ pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4, ++ bar_value); ++ } ++} ++ ++#ifdef CONFIG_USE_CPCIDVI ++static void gt_setup_cpcidvi (struct pci_controller *hose, ++ pci_dev_t dev, struct pci_config_table *entry) ++{ ++ u32 bar_value, pci_response; ++ ++ pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response); ++ pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff); ++ pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response); ++ pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value); ++ pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00)); ++ pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0); ++ pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value); ++ pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01); ++ gt_cpcidvi_rom.base = bar_value & 0xffffff00; ++ gt_cpcidvi_rom.init = 1; ++} ++ ++unsigned char gt_cpcidvi_in8(unsigned int offset) ++{ ++ unsigned char data; ++ ++ if (gt_cpcidvi_rom.init == 0) { ++ return(0); ++ } ++ data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base); ++ return(data); ++} ++ ++void gt_cpcidvi_out8(unsigned int offset, unsigned char data) ++{ ++ unsigned int off; ++ ++ if (gt_cpcidvi_rom.init == 0) { ++ return; ++ } ++ off = data; ++ off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base; ++ in8(off); ++ return; ++} ++#endif ++ ++/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ ++/* and is curently not called *. */ ++#if 0 ++static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) ++{ ++ unsigned char pin, irq; ++ ++ pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin); ++ ++ if (pin == 1) { /* only allow INT A */ ++ irq = pci_irq_swizzle[(PCI_HOST) hose-> ++ cfg_addr][PCI_DEV (dev)]; ++ if (irq) ++ pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq); ++ } ++} ++#endif ++ ++struct pci_config_table gt_config_table[] = { ++#ifdef CONFIG_USE_CPCIDVI ++ {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA, ++ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi}, ++#endif ++ {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, ++ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide}, ++ {} ++}; ++ ++struct pci_controller pci0_hose = { ++/* fixup_irq: gt_fixup_irq, */ ++ config_table:gt_config_table, ++}; ++ ++struct pci_controller pci1_hose = { ++/* fixup_irq: gt_fixup_irq, */ ++ config_table:gt_config_table, ++}; ++ ++void pci_init_board (void) ++{ ++ unsigned int command; ++#ifdef CONFIG_PCI_PNP ++ unsigned int bar; ++#endif ++#ifdef DEBUG ++ gt_pci_bus_mode_display (PCI_HOST0); ++#endif ++#ifdef CONFIG_USE_CPCIDVI ++ gt_cpcidvi_rom.init = 0; ++ gt_cpcidvi_rom.base = 0; ++#endif ++ ++ pci0_hose.config_table = gt_config_table; ++ pci1_hose.config_table = gt_config_table; ++ ++#ifdef CONFIG_USE_CPCIDVI ++ gt_config_table[0].config_device = gt_setup_cpcidvi; ++#endif ++ gt_config_table[1].config_device = gt_setup_ide; ++ ++ pci0_hose.first_busno = 0; ++ pci0_hose.last_busno = 0xff; ++ local_buses[0] = pci0_hose.first_busno; ++ ++ /* PCI memory space */ ++ pci_set_region (pci0_hose.regions + 0, ++ CFG_PCI0_0_MEM_SPACE, ++ CFG_PCI0_0_MEM_SPACE, ++ CFG_PCI0_MEM_SIZE, PCI_REGION_MEM); ++ ++ /* PCI I/O space */ ++ pci_set_region (pci0_hose.regions + 1, ++ CFG_PCI0_IO_SPACE_PCI, ++ CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO); ++ ++ pci_set_ops (&pci0_hose, ++ pci_hose_read_config_byte_via_dword, ++ pci_hose_read_config_word_via_dword, ++ gt_read_config_dword, ++ pci_hose_write_config_byte_via_dword, ++ pci_hose_write_config_word_via_dword, ++ gt_write_config_dword); ++ pci0_hose.region_count = 2; ++ ++ pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0; ++ ++ pci_register_hose (&pci0_hose); ++ pciArbiterDisable(PCI_HOST0); /* on PMC modules no arbiter is used */ ++ pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); ++ command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); ++ command |= PCI_COMMAND_MASTER; ++ pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); ++ command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); ++ command |= PCI_COMMAND_MEMORY; ++ pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); ++ ++#ifdef CONFIG_PCI_PNP ++ pciauto_config_init(&pci0_hose); ++ pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar); ++#endif ++#ifdef CONFIG_PCI_SCAN_SHOW ++ printf("PCI: Bus Dev VenId DevId Class Int\n"); ++#endif ++ pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose, pci0_hose.first_busno); ++ ++#ifdef DEBUG ++ gt_pci_bus_mode_display (PCI_HOST1); ++#endif ++ pci1_hose.first_busno = pci0_hose.last_busno + 1; ++ pci1_hose.last_busno = 0xff; ++ pci1_hose.current_busno = pci1_hose.first_busno; ++ local_buses[1] = pci1_hose.first_busno; ++ ++ /* PCI memory space */ ++ pci_set_region (pci1_hose.regions + 0, ++ CFG_PCI1_0_MEM_SPACE, ++ CFG_PCI1_0_MEM_SPACE, ++ CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); ++ ++ /* PCI I/O space */ ++ pci_set_region (pci1_hose.regions + 1, ++ CFG_PCI1_IO_SPACE_PCI, ++ CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO); ++ ++ pci_set_ops (&pci1_hose, ++ pci_hose_read_config_byte_via_dword, ++ pci_hose_read_config_word_via_dword, ++ gt_read_config_dword, ++ pci_hose_write_config_byte_via_dword, ++ pci_hose_write_config_word_via_dword, ++ gt_write_config_dword); ++ ++ pci1_hose.region_count = 2; ++ ++ pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1; ++ ++ pci_register_hose (&pci1_hose); ++ ++ pciArbiterEnable (PCI_HOST1); ++ pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1); ++ ++ command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); ++ command |= PCI_COMMAND_MASTER; ++ pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); ++ ++#ifdef CONFIG_PCI_PNP ++ pciauto_config_init(&pci1_hose); ++ pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar); ++#endif ++ pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno); ++ ++ command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF); ++ command |= PCI_COMMAND_MEMORY; ++ pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command); ++ ++} ++#endif /* of CONFIG_PCI */ +diff -Naupr u-boot-1.1.6/board/prodrive/p3mx/ppc_error_no.h u-boot-1.1.6-fsl-1/board/prodrive/p3mx/ppc_error_no.h +--- u-boot-1.1.6/board/prodrive/p3mx/ppc_error_no.h 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/p3mx/ppc_error_no.h 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,164 @@ ++/* ++ * (C) Copyright 2003 ++ * Ingo Assmus ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* ++ * BK Id: SCCS/s.errno.h 1.9 06/05/01 21:45:21 paulus ++ */ ++#ifndef _MV_PPC_ERRNO_H ++#define _MV_PPC_ERRNO_H ++ ++#define EPERM 1 /* Operation not permitted */ ++#define ENOENT 2 /* No such file or directory */ ++#define ESRCH 3 /* No such process */ ++#define EINTR 4 /* Interrupted system call */ ++#define EIO 5 /* I/O error */ ++#define ENXIO 6 /* No such device or address */ ++#define E2BIG 7 /* Arg list too long */ ++#define ENOEXEC 8 /* Exec format error */ ++#define EBADF 9 /* Bad file number */ ++#define ECHILD 10 /* No child processes */ ++#define EAGAIN 11 /* Try again */ ++#define ENOMEM 12 /* Out of memory */ ++#define EACCES 13 /* Permission denied */ ++#define EFAULT 14 /* Bad address */ ++#define ENOTBLK 15 /* Block device required */ ++#define EBUSY 16 /* Device or resource busy */ ++#define EEXIST 17 /* File exists */ ++#define EXDEV 18 /* Cross-device link */ ++#define ENODEV 19 /* No such device */ ++#define ENOTDIR 20 /* Not a directory */ ++#define EISDIR 21 /* Is a directory */ ++#define EINVAL 22 /* Invalid argument */ ++#define ENFILE 23 /* File table overflow */ ++#define EMFILE 24 /* Too many open files */ ++#define ENOTTY 25 /* Not a typewriter */ ++#define ETXTBSY 26 /* Text file busy */ ++#define EFBIG 27 /* File too large */ ++#define ENOSPC 28 /* No space left on device */ ++#define ESPIPE 29 /* Illegal seek */ ++#define EROFS 30 /* Read-only file system */ ++#define EMLINK 31 /* Too many links */ ++#define EPIPE 32 /* Broken pipe */ ++#define EDOM 33 /* Math argument out of domain of func */ ++#define ERANGE 34 /* Math result not representable */ ++#define EDEADLK 35 /* Resource deadlock would occur */ ++#define ENAMETOOLONG 36 /* File name too long */ ++#define ENOLCK 37 /* No record locks available */ ++#define ENOSYS 38 /* Function not implemented */ ++#define ENOTEMPTY 39 /* Directory not empty */ ++#define ELOOP 40 /* Too many symbolic links encountered */ ++#define EWOULDBLOCK EAGAIN /* Operation would block */ ++#define ENOMSG 42 /* No message of desired type */ ++#define EIDRM 43 /* Identifier removed */ ++#define ECHRNG 44 /* Channel number out of range */ ++#define EL2NSYNC 45 /* Level 2 not synchronized */ ++#define EL3HLT 46 /* Level 3 halted */ ++#define EL3RST 47 /* Level 3 reset */ ++#define ELNRNG 48 /* Link number out of range */ ++#define EUNATCH 49 /* Protocol driver not attached */ ++#define ENOCSI 50 /* No CSI structure available */ ++#define EL2HLT 51 /* Level 2 halted */ ++#define EBADE 52 /* Invalid exchange */ ++#define EBADR 53 /* Invalid request descriptor */ ++#define EXFULL 54 /* Exchange full */ ++#define ENOANO 55 /* No anode */ ++#define EBADRQC 56 /* Invalid request code */ ++#define EBADSLT 57 /* Invalid slot */ ++#define EDEADLOCK 58 /* File locking deadlock error */ ++#define EBFONT 59 /* Bad font file format */ ++#define ENOSTR 60 /* Device not a stream */ ++#define ENODATA 61 /* No data available */ ++#define ETIME 62 /* Timer expired */ ++#define ENOSR 63 /* Out of streams resources */ ++#define ENONET 64 /* Machine is not on the network */ ++#define ENOPKG 65 /* Package not installed */ ++#define EREMOTE 66 /* Object is remote */ ++#define ENOLINK 67 /* Link has been severed */ ++#define EADV 68 /* Advertise error */ ++#define ESRMNT 69 /* Srmount error */ ++#define ECOMM 70 /* Communication error on send */ ++#define EPROTO 71 /* Protocol error */ ++#define EMULTIHOP 72 /* Multihop attempted */ ++#define EDOTDOT 73 /* RFS specific error */ ++#define EBADMSG 74 /* Not a data message */ ++#define EOVERFLOW 75 /* Value too large for defined data type */ ++#define ENOTUNIQ 76 /* Name not unique on network */ ++#define EBADFD 77 /* File descriptor in bad state */ ++#define EREMCHG 78 /* Remote address changed */ ++#define ELIBACC 79 /* Can not access a needed shared library */ ++#define ELIBBAD 80 /* Accessing a corrupted shared library */ ++#define ELIBSCN 81 /* .lib section in a.out corrupted */ ++#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ ++#define ELIBEXEC 83 /* Cannot exec a shared library directly */ ++#define EILSEQ 84 /* Illegal byte sequence */ ++#define ERESTART 85 /* Interrupted system call should be restarted */ ++#define ESTRPIPE 86 /* Streams pipe error */ ++#define EUSERS 87 /* Too many users */ ++#define ENOTSOCK 88 /* Socket operation on non-socket */ ++#define EDESTADDRREQ 89 /* Destination address required */ ++#define EMSGSIZE 90 /* Message too long */ ++#define EPROTOTYPE 91 /* Protocol wrong type for socket */ ++#define ENOPROTOOPT 92 /* Protocol not available */ ++#define EPROTONOSUPPORT 93 /* Protocol not supported */ ++#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ ++#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ ++#define EPFNOSUPPORT 96 /* Protocol family not supported */ ++#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ ++#define EADDRINUSE 98 /* Address already in use */ ++#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ ++#define ENETDOWN 100 /* Network is down */ ++#define ENETUNREACH 101 /* Network is unreachable */ ++#define ENETRESET 102 /* Network dropped connection because of reset */ ++#define ECONNABORTED 103 /* Software caused connection abort */ ++#define ECONNRESET 104 /* Connection reset by peer */ ++#define ENOBUFS 105 /* No buffer space available */ ++#define EISCONN 106 /* Transport endpoint is already connected */ ++#define ENOTCONN 107 /* Transport endpoint is not connected */ ++#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ ++#define ETOOMANYREFS 109 /* Too many references: cannot splice */ ++#define ETIMEDOUT 110 /* Connection timed out */ ++#define ECONNREFUSED 111 /* Connection refused */ ++#define EHOSTDOWN 112 /* Host is down */ ++#define EHOSTUNREACH 113 /* No route to host */ ++#define EALREADY 114 /* Operation already in progress */ ++#define EINPROGRESS 115 /* Operation now in progress */ ++#define ESTALE 116 /* Stale NFS file handle */ ++#define EUCLEAN 117 /* Structure needs cleaning */ ++#define ENOTNAM 118 /* Not a XENIX named type file */ ++#define ENAVAIL 119 /* No XENIX semaphores available */ ++#define EISNAM 120 /* Is a named type file */ ++#define EREMOTEIO 121 /* Remote I/O error */ ++#define EDQUOT 122 /* Quota exceeded */ ++ ++#define ENOMEDIUM 123 /* No medium found */ ++#define EMEDIUMTYPE 124 /* Wrong medium type */ ++ ++/* Should never be seen by user programs */ ++#define ERESTARTSYS 512 ++#define ERESTARTNOINTR 513 ++#define ERESTARTNOHAND 514 /* restart if no handler.. */ ++#define ENOIOCTLCMD 515 /* No ioctl command */ ++ ++#define _LAST_ERRNO 515 ++ ++#endif +diff -Naupr u-boot-1.1.6/board/prodrive/p3mx/sdram_init.c u-boot-1.1.6-fsl-1/board/prodrive/p3mx/sdram_init.c +--- u-boot-1.1.6/board/prodrive/p3mx/sdram_init.c 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/p3mx/sdram_init.c 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,434 @@ ++/* ++ * (C) Copyright 2001 ++ * Josh Huber , Mission Critical Linux, Inc. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/************************************************************************* ++ * adaption for the Marvell DB64460 Board ++ * Ingo Assmus (ingo.assmus@keymile.com) ++ *************************************************************************/ ++ ++/* sdram_init.c - automatic memory sizing */ ++ ++#include ++#include <74xx_7xx.h> ++#include "../../Marvell/include/memory.h" ++#include "../../Marvell/include/pci.h" ++#include "../../Marvell/include/mv_gen_reg.h" ++#include ++ ++#include "eth.h" ++#include "mpsc.h" ++#include "../../Marvell/common/i2c.h" ++#include "64460.h" ++#include "mv_regs.h" ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#undef DEBUG ++#define MAP_PCI ++ ++#ifdef DEBUG ++#define DP(x) x ++#else ++#define DP(x) ++#endif ++ ++int set_dfcdlInit (void); /* setup delay line of Mv64460 */ ++int mvDmaIsChannelActive (int); ++int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong); ++int mvDmaTransfer (int, ulong, ulong, ulong, ulong); ++ ++#define D_CACHE_FLUSH_LINE(addr, offset) \ ++ { \ ++ __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \ ++ } ++ ++int memory_map_bank (unsigned int bankNo, ++ unsigned int bankBase, unsigned int bankLength) ++{ ++#ifdef MAP_PCI ++ PCI_HOST host; ++#endif ++ ++#ifdef DEBUG ++ if (bankLength > 0) { ++ printf ("mapping bank %d at %08x - %08x\n", ++ bankNo, bankBase, bankBase + bankLength - 1); ++ } else { ++ printf ("unmapping bank %d\n", bankNo); ++ } ++#endif ++ ++ memoryMapBank (bankNo, bankBase, bankLength); ++ ++#ifdef MAP_PCI ++ for (host = PCI_HOST0; host <= PCI_HOST1; host++) { ++ const int features = ++ PREFETCH_ENABLE | ++ DELAYED_READ_ENABLE | ++ AGGRESSIVE_PREFETCH | ++ READ_LINE_AGGRESSIVE_PREFETCH | ++ READ_MULTI_AGGRESSIVE_PREFETCH | ++ MAX_BURST_4 | PCI_NO_SWAP; ++ ++ pciMapMemoryBank (host, bankNo, bankBase, bankLength); ++ ++ pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase, ++ bankLength); ++ ++ pciSetRegionFeatures (host, bankNo, features, bankBase, ++ bankLength); ++ } ++#endif ++ ++ return 0; ++} ++ ++/* ++ * Check memory range for valid RAM. A simple memory test determines ++ * the actually available RAM size between addresses `base' and ++ * `base + maxsize'. Some (not all) hardware errors are detected: ++ * - short between address lines ++ * - short between data lines ++ */ ++long int dram_size (long int *base, long int maxsize) ++{ ++ volatile long int *addr, *b = base; ++ long int cnt, val, save1, save2; ++ ++#define STARTVAL (1<<20) /* start test at 1M */ ++ for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long); ++ cnt <<= 1) { ++ addr = base + cnt; /* pointer arith! */ ++ ++ save1 = *addr; /* save contents of addr */ ++ save2 = *b; /* save contents of base */ ++ ++ *addr = cnt; /* write cnt to addr */ ++ *b = 0; /* put null at base */ ++ ++ /* check at base address */ ++ if ((*b) != 0) { ++ *addr = save1; /* restore *addr */ ++ *b = save2; /* restore *b */ ++ return (0); ++ } ++ val = *addr; /* read *addr */ ++ val = *addr; /* read *addr */ ++ ++ *addr = save1; ++ *b = save2; ++ ++ if (val != cnt) { ++ DP (printf ++ ("Found %08x at Address %08x (failure)\n", ++ (unsigned int) val, (unsigned int) addr)); ++ /* fix boundary condition.. STARTVAL means zero */ ++ if (cnt == STARTVAL / sizeof (long)) ++ cnt = 0; ++ return (cnt * sizeof (long)); ++ } ++ } ++ ++ return maxsize; ++} ++ ++#define SDRAM_NORMAL 0x0 ++#define SDRAM_PRECHARGE_ALL 0x1 ++#define SDRAM_REFRESH_ALL 0x2 ++#define SDRAM_MODE_REG_SETUP 0x3 ++#define SDRAM_XTEN_MODE_REG_SETUP 0x4 ++#define SDRAM_NOP 0x5 ++#define SDRAM_SELF_REFRESH 0x7 ++ ++long int initdram (int board_type) ++{ ++ int tmp; ++ int start; ++ ulong size; ++ ulong memSpaceAttr; ++ ulong dest; ++ ++ /* first disable all banks */ ++ memory_map_bank(0, 0, 0); ++ memory_map_bank(1, 0, 0); ++ memory_map_bank(2, 0, 0); ++ memory_map_bank(3, 0, 0); ++ ++ /* calibrate delay lines */ ++ set_dfcdlInit(); ++ ++ GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_NOP); /* 0x1418 */ ++ do { ++ tmp = GTREGREAD(MV64460_SDRAM_OPERATION); ++ } while(tmp != 0x0); ++ ++ /* SDRAM controller configuration */ ++#ifdef CONFIG_MV64460_ECC ++ GT_REG_WRITE(MV64460_SDRAM_CONFIG, 0x58201400); /* 0x1400 */ ++#else ++ GT_REG_WRITE(MV64460_SDRAM_CONFIG, 0x58200400); /* 0x1400 */ ++#endif ++ GT_REG_WRITE(MV64460_D_UNIT_CONTROL_LOW, 0xC3000540); /* 0x1404 */ ++ GT_REG_WRITE(MV64460_D_UNIT_CONTROL_HIGH, 0x0300F777); /* 0x1424 */ ++ GT_REG_WRITE(MV64460_SDRAM_TIMING_CONTROL_LOW, 0x01712220); /* 0x1408 */ ++ GT_REG_WRITE(MV64460_SDRAM_TIMING_CONTROL_HIGH, 0x0000005D); /* 0x140C */ ++ GT_REG_WRITE(MV64460_SDRAM_ADDR_CONTROL, 0x00000012); /* 0x1410 */ ++ GT_REG_WRITE(MV64460_SDRAM_OPEN_PAGES_CONTROL, 0x00000001); /* 0x1414 */ ++ ++ /* SDRAM drive strength */ ++ GT_REG_WRITE(MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x80000000); /* 0x14C0 */ ++ GT_REG_WRITE(MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x80000008); /* 0x14C0 */ ++ GT_REG_WRITE(MV64460_SDRAM_DATA_PADS_CALIBRATION, 0x80000000); /* 0x14C4 */ ++ GT_REG_WRITE(MV64460_SDRAM_DATA_PADS_CALIBRATION, 0x80000008); /* 0x14C4 */ ++ ++ /* setup SDRAM device registers */ ++ ++ /* precharge all */ ++ GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_PRECHARGE_ALL); /* 0x1418 */ ++ do { ++ tmp = GTREGREAD(MV64460_SDRAM_OPERATION); ++ } while(tmp != 0x0); ++ ++ /* enable DLL */ ++ GT_REG_WRITE(MV64460_EXTENDED_DRAM_MODE, 0x00000000); /* 0x1420 */ ++ GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_XTEN_MODE_REG_SETUP); /* 0x1418 */ ++ do { ++ tmp = GTREGREAD(MV64460_SDRAM_OPERATION); ++ } while(tmp != 0x0); ++ ++ /* reset DLL */ ++ GT_REG_WRITE(MV64460_SDRAM_MODE, 0x00000132); /* 0x141C */ ++ GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_MODE_REG_SETUP); /* 0x1418 */ ++ do { ++ tmp = GTREGREAD(MV64460_SDRAM_OPERATION); ++ } while(tmp != 0x0); ++ ++ /* precharge all */ ++ GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_PRECHARGE_ALL); /* 0x1418 */ ++ do { ++ tmp = GTREGREAD(MV64460_SDRAM_OPERATION); ++ } while(tmp != 0x0); ++ ++ /* wait for 2 auto refresh commands */ ++ udelay(20); ++ ++ /* un-reset DLL */ ++ GT_REG_WRITE(MV64460_SDRAM_MODE, 0x00000032); /* 0x141C */ ++ GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_MODE_REG_SETUP); /* 0x1418 */ ++ do { ++ tmp = GTREGREAD(MV64460_SDRAM_OPERATION); ++ } while(tmp != 0x0); ++ ++ /* wait 200 cycles */ ++ udelay(2); /* FIXME make this dynamic for the system clock */ ++ ++ /* SDRAM init done */ ++ memory_map_bank(0, CFG_SDRAM_BASE, (256 << 20)); ++#ifdef CFG_SDRAM1_BASE ++ memory_map_bank(1, CFG_SDRAM1_BASE, (256 << 20)); ++#endif ++ ++ /* DUNIT_MMASK: enable SnoopHitEn bit to avoid errata CPU-#4 ++ */ ++ tmp = GTREGREAD(MV64460_D_UNIT_MMASK); /* 0x14B0 */ ++ GT_REG_WRITE(MV64460_D_UNIT_MMASK, tmp | 0x2); ++ ++ start = (0 << 20); ++#ifdef CONFIG_P3M750 ++ size = (512 << 20); ++#elif defined (CONFIG_P3M7448) ++ size = (128 << 20); ++#endif ++ ++#ifdef CONFIG_MV64460_ECC ++ memSpaceAttr = ((~(BIT0 << 0)) & 0xf) << 8; ++ mvDmaSetMemorySpace (0, 0, memSpaceAttr, start, size); ++ for (dest = start; dest < start + size; dest += _8M) { ++ mvDmaTransfer (0, start, dest, _8M, ++ BIT8 /*DMA_DTL_128BYTES */ | ++ BIT3 /*DMA_HOLD_SOURCE_ADDR */ | ++ BIT11 /*DMA_BLOCK_TRANSFER_MODE */ ); ++ while (mvDmaIsChannelActive (0)); ++ } ++#endif ++ ++ return (size); ++} ++ ++void board_add_ram_info(int use_default) ++{ ++ u32 val; ++ ++ puts(" (CL="); ++ switch ((GTREGREAD(MV64460_SDRAM_MODE) >> 4) & 0x7) { ++ case 0x2: ++ puts("2"); ++ break; ++ case 0x3: ++ puts("3"); ++ break; ++ case 0x5: ++ puts("1.5"); ++ break; ++ case 0x6: ++ puts("2.5"); ++ break; ++ } ++ ++ val = GTREGREAD(MV64460_SDRAM_CONFIG); ++ ++ puts(", ECC "); ++ if (val & 0x00001000) ++ puts("enabled)"); ++ else ++ puts("not enabled)"); ++} ++ ++/* ++ * mvDmaIsChannelActive - Check if IDMA channel is active ++ * ++ * channel = IDMA channel number from 0 to 7 ++ */ ++int mvDmaIsChannelActive (int channel) ++{ ++ ulong data; ++ ++ data = GTREGREAD (MV64460_DMA_CHANNEL0_CONTROL + 4 * channel); ++ if (data & BIT14) /* activity status */ ++ return 1; ++ ++ return 0; ++} ++ ++/* ++ * mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding ++ * map. ++ * ++ * memSpace = IDMA memory window number from 0 to 7 ++ * trg_if = Target interface: ++ * 0x0 DRAM ++ * 0x1 Device Bus ++ * 0x2 Integrated SDRAM (or CPU bus 60x only) ++ * 0x3 PCI0 ++ * 0x4 PCI1 ++ * attr = IDMA attributes (see MV datasheet) ++ * base_addr = Sets up memory window for transfers ++ * ++ */ ++int mvDmaSetMemorySpace (ulong memSpace, ++ ulong trg_if, ++ ulong attr, ulong base_addr, ulong size) ++{ ++ ulong temp; ++ ++ /* The base address must be aligned to the size. */ ++ if (base_addr % size != 0) ++ return 0; ++ ++ if (size >= 0x10000) { /* 64K */ ++ size &= 0xffff0000; ++ base_addr = (base_addr & 0xffff0000); ++ /* Set the new attributes */ ++ GT_REG_WRITE (MV64460_DMA_BASE_ADDR_REG0 + memSpace * 8, ++ (base_addr | trg_if | attr)); ++ GT_REG_WRITE ((MV64460_DMA_SIZE_REG0 + memSpace * 8), ++ (size - 1) & 0xffff0000); ++ temp = GTREGREAD (MV64460_DMA_BASE_ADDR_ENABLE_REG); ++ GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG, ++ (temp & ~(BIT0 << memSpace))); ++ return 1; ++ } ++ ++ return 0; ++} ++ ++/* ++ * mvDmaTransfer - Transfer data from src_addr to dst_addr on one of the 4 ++ * DMA channels. ++ * ++ * channel = IDMA channel number from 0 to 3 ++ * destAddr = Destination address ++ * sourceAddr = Source address ++ * size = Size in bytes ++ * command = See MV datasheet ++ * ++ */ ++int mvDmaTransfer (int channel, ulong sourceAddr, ++ ulong destAddr, ulong size, ulong command) ++{ ++ ulong engOffReg = 0; /* Engine Offset Register */ ++ ++ if (size > 0xffff) ++ command = command | BIT31; /* DMA_16M_DESCRIPTOR_MODE */ ++ command = command | ((command >> 6) & 0x7); ++ engOffReg = channel * 4; ++ GT_REG_WRITE (MV64460_DMA_CHANNEL0_BYTE_COUNT + engOffReg, size); ++ GT_REG_WRITE (MV64460_DMA_CHANNEL0_SOURCE_ADDR + engOffReg, sourceAddr); ++ GT_REG_WRITE (MV64460_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg, destAddr); ++ command = command | ++ BIT12 | /* DMA_CHANNEL_ENABLE */ ++ BIT9; /* DMA_NON_CHAIN_MODE */ ++ /* Activate DMA channel By writting to mvDmaControlRegister */ ++ GT_REG_WRITE (MV64460_DMA_CHANNEL0_CONTROL + engOffReg, command); ++ return 1; ++} ++ ++/**************************************************************************************** ++ * SDRAM INIT * ++ * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb * ++ * This procedure fits only the Atlantis * ++ * * ++ ***************************************************************************************/ ++ ++/**************************************************************************************** ++ * DFCDL initialize MV643xx Design Considerations * ++ * * ++ ***************************************************************************************/ ++int set_dfcdlInit (void) ++{ ++ int i; ++ ++ /* Values from MV64460 User Manual */ ++ unsigned int dfcdl_tbl[] = { 0x00000000, 0x00000001, 0x00000042, 0x00000083, ++ 0x000000c4, 0x00000105, 0x00000146, 0x00000187, ++ 0x000001c8, 0x00000209, 0x0000024a, 0x0000028b, ++ 0x000002cc, 0x0000030d, 0x0000034e, 0x0000038f, ++ 0x000003d0, 0x00000411, 0x00000452, 0x00000493, ++ 0x000004d4, 0x00000515, 0x00000556, 0x00000597, ++ 0x000005d8, 0x00000619, 0x0000065a, 0x0000069b, ++ 0x000006dc, 0x0000071d, 0x0000075e, 0x0000079f, ++ 0x000007e0, 0x00000821, 0x00000862, 0x000008a3, ++ 0x000008e4, 0x00000925, 0x00000966, 0x000009a7, ++ 0x000009e8, 0x00000a29, 0x00000a6a, 0x00000aab, ++ 0x00000aec, 0x00000b2d, 0x00000b6e, 0x00000baf, ++ 0x00000bf0, 0x00000c31, 0x00000c72, 0x00000cb3, ++ 0x00000cf4, 0x00000d35, 0x00000d76, 0x00000db7, ++ 0x00000df8, 0x00000e39, 0x00000e7a, 0x00000ebb, ++ 0x00000efc, 0x00000f3d, 0x00000f7e, 0x00000fbf }; ++ ++ for (i = 0; i < 64; i++) ++ GT_REG_WRITE (SRAM_DATA0, dfcdl_tbl[i]); ++ GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */ ++ ++ return (0); ++} +diff -Naupr u-boot-1.1.6/board/prodrive/p3mx/serial.c u-boot-1.1.6-fsl-1/board/prodrive/p3mx/serial.c +--- u-boot-1.1.6/board/prodrive/p3mx/serial.c 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/p3mx/serial.c 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,107 @@ ++/* ++ * (C) Copyright 2001 ++ * Josh Huber , Mission Critical Linux, Inc. ++ * ++ * modified for marvell db64360 eval board by ++ * Ingo Assmus ++ * ++ * modified for cpci750 board by ++ * Reinhard Arlt ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* ++ * serial.c - serial support for esd cpci750 board ++ */ ++ ++/* supports the MPSC */ ++ ++#include ++#include ++#include "../../Marvell/include/memory.h" ++#include "serial.h" ++ ++#include "mpsc.h" ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++int serial_init (void) ++{ ++ mpsc_init (gd->baudrate); ++ ++ return (0); ++} ++ ++void serial_putc (const char c) ++{ ++ if (c == '\n') ++ mpsc_putchar ('\r'); ++ ++ mpsc_putchar (c); ++} ++ ++int serial_getc (void) ++{ ++ return mpsc_getchar (); ++} ++ ++int serial_tstc (void) ++{ ++ return mpsc_test_char (); ++} ++ ++void serial_setbrg (void) ++{ ++ galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate); ++} ++ ++ ++void serial_puts (const char *s) ++{ ++ while (*s) { ++ serial_putc (*s++); ++ } ++} ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++void kgdb_serial_init (void) ++{ ++} ++ ++void putDebugChar (int c) ++{ ++ serial_putc (c); ++} ++ ++void putDebugStr (const char *str) ++{ ++ serial_puts (str); ++} ++ ++int getDebugChar (void) ++{ ++ return serial_getc (); ++} ++ ++void kgdb_interruptible (int yes) ++{ ++ return; ++} ++#endif /* CFG_CMD_KGDB */ +diff -Naupr u-boot-1.1.6/board/prodrive/p3mx/serial.h u-boot-1.1.6-fsl-1/board/prodrive/p3mx/serial.h +--- u-boot-1.1.6/board/prodrive/p3mx/serial.h 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/p3mx/serial.h 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,89 @@ ++/* ++ * (C) Copyright 2001 ++ * Josh Huber , Mission Critical Linux, Inc. ++ * ++ * modified for marvell db64360 eval board by ++ * Ingo Assmus ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* serial.h - mostly useful for DUART serial_init in serial.c */ ++ ++#ifndef __SERIAL_H__ ++#define __SERIAL_H__ ++ ++#if 0 ++ ++#define B230400 1 ++#define B115200 2 ++#define B57600 4 ++#define B38400 82 ++#define B19200 163 ++#define B9600 24 ++#define B4800 651 ++#define B2400 1302 ++#define B1200 2604 ++#define B600 5208 ++#define B300 10417 ++#define B150 20833 ++#define B110 28409 ++#define BDEFAULT B115200 ++ ++ /* this stuff is important to initialize ++ the DUART channels */ ++ ++#define Scale 0x01L /* distance between port addresses */ ++#define COM1 0x000003f8 /* Keyboard */ ++#define COM2 0x000002f8 /* Host */ ++ ++ ++/* Port Definitions relative to base COM port addresses */ ++#define DataIn (0x00*Scale) /* data input port */ ++#define DataOut (0x00*Scale) /* data output port */ ++#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */ ++#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */ ++#define Ier (0x01*Scale) /* interrupt enable register */ ++#define Iir (0x02*Scale) /* interrupt identification register */ ++#define Lcr (0x03*Scale) /* line control register */ ++#define Mcr (0x04*Scale) /* modem control register */ ++#define Lsr (0x05*Scale) /* line status register */ ++#define Msr (0x06*Scale) /* modem status register */ ++ ++/* Bit Definitions for above ports */ ++#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */ ++#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */ ++ ++#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */ ++#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */ ++#define McrDflt (McrRts|McrDtr) ++ ++#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/ ++ /* b6: transmitter empty */ ++#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */ ++ ++#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */ ++#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */ ++#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */ ++ ++#define IerRda 0xf /* b0: Enable received data available interrupt */ ++ ++#endif ++ ++#endif /* __SERIAL_H__ */ +diff -Naupr u-boot-1.1.6/board/prodrive/p3mx/u-boot.lds u-boot-1.1.6-fsl-1/board/prodrive/p3mx/u-boot.lds +--- u-boot-1.1.6/board/prodrive/p3mx/u-boot.lds 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/prodrive/p3mx/u-boot.lds 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,138 @@ ++/* ++ * (C) Copyright 2001 ++ * Josh Huber , Mission Critical Linux, Inc. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* ++ * u-boot.lds - linker script for U-Boot on the Galileo Eval Board. ++ */ ++ ++OUTPUT_ARCH(powerpc) ++SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); ++/* Do we need any of these for elf? ++ __DYNAMIC = 0; */ ++SECTIONS ++{ ++ /* Read-only sections, merged into text segment: */ ++ . = + SIZEOF_HEADERS; ++ .interp : { *(.interp) } ++ .hash : { *(.hash) } ++ .dynsym : { *(.dynsym) } ++ .dynstr : { *(.dynstr) } ++ .rel.text : { *(.rel.text) } ++ .rela.text : { *(.rela.text) } ++ .rel.data : { *(.rel.data) } ++ .rela.data : { *(.rela.data) } ++ .rel.rodata : { *(.rel.rodata) } ++ .rela.rodata : { *(.rela.rodata) } ++ .rel.got : { *(.rel.got) } ++ .rela.got : { *(.rela.got) } ++ .rel.ctors : { *(.rel.ctors) } ++ .rela.ctors : { *(.rela.ctors) } ++ .rel.dtors : { *(.rel.dtors) } ++ .rela.dtors : { *(.rela.dtors) } ++ .rel.bss : { *(.rel.bss) } ++ .rela.bss : { *(.rela.bss) } ++ .rel.plt : { *(.rel.plt) } ++ .rela.plt : { *(.rela.plt) } ++ .init : { *(.init) } ++ .plt : { *(.plt) } ++ .text : ++ { ++ cpu/74xx_7xx/start.o (.text) ++ ++/* store the environment in a seperate sector in the boot flash */ ++/* . = env_offset; */ ++/* common/environment.o(.text) */ ++ ++ *(.text) ++ *(.fixup) ++ *(.got1) ++ } ++ _etext = .; ++ PROVIDE (etext = .); ++ .rodata : ++ { ++ *(.rodata) ++ *(.rodata1) ++ *(.rodata.str1.4) ++ *(.eh_frame) ++ } ++ .fini : { *(.fini) } =0 ++ .ctors : { *(.ctors) } ++ .dtors : { *(.dtors) } ++ ++ /* Read-write section, merged into data segment: */ ++ . = (. + 0x00FF) & 0xFFFFFF00; ++ _erotext = .; ++ PROVIDE (erotext = .); ++ .reloc : ++ { ++ *(.got) ++ _GOT2_TABLE_ = .; ++ *(.got2) ++ _FIXUP_TABLE_ = .; ++ *(.fixup) ++ } ++ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; ++ __fixup_entries = (. - _FIXUP_TABLE_)>>2; ++ ++ .data : ++ { ++ *(.data) ++ *(.data1) ++ *(.sdata) ++ *(.sdata2) ++ *(.dynamic) ++ CONSTRUCTORS ++ } ++ _edata = .; ++ PROVIDE (edata = .); ++ ++ . = .; ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ ++ . = .; ++ __start___ex_table = .; ++ __ex_table : { *(__ex_table) } ++ __stop___ex_table = .; ++ ++ . = ALIGN(256); ++ __init_begin = .; ++ .text.init : { *(.text.init) } ++ .data.init : { *(.data.init) } ++ . = ALIGN(256); ++ __init_end = .; ++ ++ __bss_start = .; ++ .bss : ++ { ++ *(.sbss) *(.scommon) ++ *(.dynbss) ++ *(.bss) ++ *(COMMON) ++ } ++ _end = . ; ++ PROVIDE (end = .); ++} +diff -Naupr u-boot-1.1.6/board/tqm5200/cam5200_flash.c u-boot-1.1.6-fsl-1/board/tqm5200/cam5200_flash.c +--- u-boot-1.1.6/board/tqm5200/cam5200_flash.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/tqm5200/cam5200_flash.c 2006-11-30 12:34:13.000000000 -0600 +@@ -759,7 +759,7 @@ unsigned long flash_init(void) + + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", +- i, size_b[i], size_b[i] << 20); ++ i+1, size_b[i], size_b[i] << 20); + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + } +diff -Naupr u-boot-1.1.6/board/tqm5200/tqm5200.c u-boot-1.1.6-fsl-1/board/tqm5200/tqm5200.c +--- u-boot-1.1.6/board/tqm5200/tqm5200.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/tqm5200/tqm5200.c 2006-11-30 12:34:13.000000000 -0600 +@@ -289,7 +289,7 @@ int checkboard (void) + #elif defined(CONFIG_TB5200) + # define CARRIER_NAME "TB5200" + #elif defined(CONFIG_CAM5200) +-# define CARRIER_NAME "Cam5200" ++# define CARRIER_NAME "CAM5200" + #elif defined(CONFIG_FO300) + # define CARRIER_NAME "FO300" + #else +@@ -341,9 +341,7 @@ void pci_init_board(void) + #define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL + #define SM501_GPIO_DATA_HIGH 0x00010004UL + #define SM501_GPIO_51 0x00080000UL +-#else +-#define GPIO_PSC1_4 0x01000000UL +-#endif ++#endif /* CONFIG MINIFAP */ + + void init_ide_reset (void) + { +@@ -381,9 +379,9 @@ void ide_set_reset (int idereset) + } + #else + if (idereset) { +- *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; + } else { +- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; + } + #endif + } +diff -Naupr u-boot-1.1.6/board/tqm834x/pci.c u-boot-1.1.6-fsl-1/board/tqm834x/pci.c +--- u-boot-1.1.6/board/tqm834x/pci.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/tqm834x/pci.c 2006-11-10 11:24:29.000000000 -0600 +@@ -69,17 +69,17 @@ void + pci_init_board(void) + { + volatile immap_t * immr; +- volatile clk8349_t * clk; +- volatile law8349_t * pci_law; +- volatile pot8349_t * pci_pot; +- volatile pcictrl8349_t * pci_ctrl; +- volatile pciconf8349_t * pci_conf; ++ volatile clk83xx_t * clk; ++ volatile law83xx_t * pci_law; ++ volatile pot83xx_t * pci_pot; ++ volatile pcictrl83xx_t * pci_ctrl; ++ volatile pciconf83xx_t * pci_conf; + u16 reg16; + u32 reg32; + struct pci_controller * hose; + +- immr = (immap_t *)CFG_IMMRBAR; +- clk = (clk8349_t *)&immr->clk; ++ immr = (immap_t *)CFG_IMMR; ++ clk = (clk83xx_t *)&immr->clk; + pci_law = immr->sysconf.pcilaw; + pci_pot = immr->ios.pot; + pci_ctrl = immr->pci_ctrl; +@@ -186,8 +186,8 @@ pci_init_board(void) + hose->region_count = 3; + + pci_setup_indirect(hose, +- (CFG_IMMRBAR+0x8300), +- (CFG_IMMRBAR+0x8304)); ++ (CFG_IMMR+0x8300), ++ (CFG_IMMR+0x8304)); + + pci_register_hose(hose); + +diff -Naupr u-boot-1.1.6/board/tqm834x/tqm834x.c u-boot-1.1.6-fsl-1/board/tqm834x/tqm834x.c +--- u-boot-1.1.6/board/tqm834x/tqm834x.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/tqm834x/tqm834x.c 2006-11-10 11:24:29.000000000 -0600 +@@ -69,7 +69,7 @@ static void set_cs_config(short cs, long + static void set_ddr_config(void); + + /* Local variable */ +-static volatile immap_t *im = (immap_t *)CFG_IMMRBAR; ++static volatile immap_t *im = (immap_t *)CFG_IMMR; + + /************************************************************************** + * Board initialzation after relocation to RAM. Used to detect the number +@@ -147,7 +147,7 @@ int checkboard (void) + volatile immap_t * immr; + u32 w, f; + +- immr = (immap_t *)CFG_IMMRBAR; ++ immr = (immap_t *)CFG_IMMR; + if (!(immr->reset.rcwh & RCWH_PCIHOST)) { + printf("PCI: NOT in host mode..?!\n"); + return 0; +diff -Naupr u-boot-1.1.6/board/v38b/ethaddr.c u-boot-1.1.6-fsl-1/board/v38b/ethaddr.c +--- u-boot-1.1.6/board/v38b/ethaddr.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/board/v38b/ethaddr.c 2006-11-10 11:24:29.000000000 -0600 +@@ -1,5 +1,4 @@ + /* +- * + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * +@@ -25,48 +24,13 @@ + #include + #include + +-#define GPIO_ENABLE (MPC5XXX_WU_GPIO) +- +-/* Open Drain Emulation Register */ +-#define GPIO_ODR (MPC5XXX_WU_GPIO + 0x04) +- +-/* Data Direction Register */ +-#define GPIO_DDR (MPC5XXX_WU_GPIO + 0x08) +- +-/* Data Value Out Register */ +-#define GPIO_DVOR (MPC5XXX_WU_GPIO + 0x0C) +- +-/* Interrupt Enable Register */ +-#define GPIO_IER (MPC5XXX_WU_GPIO + 0x10) +- +-/* Individual Interrupt Enable Register */ +-#define GPIO_IIER (MPC5XXX_WU_GPIO + 0x14) +- +-/* Interrupt Type Register */ +-#define GPIO_ITR (MPC5XXX_WU_GPIO + 0x18) +- +-/* Master Enable Register */ +-#define GPIO_MER (MPC5XXX_WU_GPIO + 0x1C) +- +-/* Data Input Value Register */ +-#define GPIO_DIVR (MPC5XXX_WU_GPIO + 0x20) +- +-/* Status Register */ +-#define GPIO_SR (MPC5XXX_WU_GPIO + 0x24) +- +-#define PSC6_0 0x10000000 +-#define WKUP_7 0x80000000 +- +-/* For NS4 A/B board define WKUP_7, for V38B board PSC_6 */ +-#define GPIO_PIN PSC6_0 ++/* For the V38B board the pin is GPIO_PSC_6 */ ++#define GPIO_PIN GPIO_PSC6_0 + + #define NO_ERROR 0 + #define ERR_NO_NUMBER 1 + #define ERR_BAD_NUMBER 2 + +-typedef volatile unsigned long GPIO_REG; +-typedef GPIO_REG *GPIO_REG_PTR; +- + static int is_high(void); + static int check_device(void); + static void io_out(int value); +@@ -79,33 +43,34 @@ static void write_byte(unsigned char com + void read_2501_memory(unsigned char *psernum, unsigned char *perr); + void board_get_enetaddr(uchar *enetaddr); + ++ + static int is_high() + { +- return (* ((vu_long *) GPIO_DIVR) & GPIO_PIN); ++ return (*((vu_long *) MPC5XXX_WU_GPIO_DATA_I) & GPIO_PIN); + } + + static void io_out(int value) + { + if (value) +- *((vu_long *) GPIO_DVOR) |= GPIO_PIN; ++ *((vu_long *) MPC5XXX_WU_GPIO_DATA_O) |= GPIO_PIN; + else +- *((vu_long *) GPIO_DVOR) &= ~GPIO_PIN; ++ *((vu_long *) MPC5XXX_WU_GPIO_DATA_O) &= ~GPIO_PIN; + } + + static void io_input() + { +- *((vu_long *) GPIO_DDR) &= ~GPIO_PIN; ++ *((vu_long *) MPC5XXX_WU_GPIO_DIR) &= ~GPIO_PIN; + udelay(3); /* allow input to settle */ + } + + static void io_output() + { +- *((vu_long *) GPIO_DDR) |= GPIO_PIN; ++ *((vu_long *) MPC5XXX_WU_GPIO_DIR) |= GPIO_PIN; + } + + static void init_gpio() + { +- *((vu_long *) GPIO_ENABLE) |= GPIO_PIN; /* Enable appropriate pin */ ++ *((vu_long *) MPC5XXX_WU_GPIO_ENABLE) |= GPIO_PIN; /* Enable appropriate pin */ + } + + void read_2501_memory(unsigned char *psernum, unsigned char *perr) +@@ -117,8 +82,8 @@ void read_2501_memory(unsigned char *pse + *perr = 0; + crcval = 0; + +- for (i=0; i + #include + ++ + #ifndef CFG_RAMBOOT + static void sdram_start(int hi_addr) + { + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ +- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; ++ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ +- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; ++ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + #if SDRAM_DDR + /* set mode register: extended mode */ +- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; ++ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ +- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; ++ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); + #endif /* SDRAM_DDR */ + + /* precharge all banks */ +- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; ++ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ +- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; ++ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ +- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; ++ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ +- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; ++ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); + } + #endif /* !CFG_RAMBOOT */ +@@ -80,18 +81,18 @@ long int initdram(int board_type) + ulong test1, test2; + + /* setup SDRAM chip selects */ +- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ +- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ ++ *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ ++ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ +- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; +- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; ++ *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; ++ *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + + #if SDRAM_DDR + /* set tap delay */ +- *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; ++ *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); + #endif /* SDRAM_DDR */ + +@@ -112,20 +113,20 @@ long int initdram(int board_type) + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) +- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; ++ *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; + else +- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ ++ *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + + /* let SDRAM CS1 start right after CS0 */ +- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ ++ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ + + /* find RAM size using SDRAM CS1 only */ + if (!dramsize) + sdram_start(0); +- test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); ++ test2 = test1 = get_ram_size((long *) (CFG_SDRAM_BASE + dramsize), 0x80000000); + if (!dramsize) { + sdram_start(1); +- test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); ++ test2 = get_ram_size((long *) (CFG_SDRAM_BASE + dramsize), 0x80000000); + } + if (test1 > test2) { + sdram_start(0); +@@ -139,22 +140,22 @@ long int initdram(int board_type) + + /* set SDRAM CS1 size according to the amount of RAM found */ + if (dramsize2 > 0) +- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize ++ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); + else +- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ ++ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + + #else /* CFG_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ +- dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; ++ dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) + dramsize = (1 << (dramsize - 0x13)) << 20; + else + dramsize = 0; + + /* retrieve size of memory connected to SDRAM CS1 */ +- dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; ++ dramsize2 = *(vu_long *) MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + else +@@ -176,7 +177,7 @@ long int initdram(int board_type) + if ((SVR_MJREV(svr) >= 2) && + (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { + +- *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; ++ *(vu_long *) MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + } + +@@ -194,27 +195,42 @@ int checkboard (void) + int board_early_init_r(void) + { + /* +- * Now, when we are in RAM, enable flash write access for detection process. +- * Note that CS_BOOT cannot be cleared when executing in flash. ++ * Now, when we are in RAM, enable flash write access for the ++ * detection process. Note that CS_BOOT cannot be cleared when ++ * executing in flash. ++ */ ++ *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ ++ ++#ifdef CONFIG_HW_WATCHDOG ++ /* ++ * Enable and configure the direction (output) of PSC3_9 - watchdog ++ * reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's ++ * Manual. ++ */ ++ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9; ++ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9; ++#endif /* CONFIG_HW_WATCHDOG */ ++ ++ /* ++ * Enable GPIO_WKUP_7 to "read the status of the actual power ++ * situation". Default direction is input, so no need to set it ++ * explicitly. + */ +- *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ ++ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WKUP_7; + return 0; + } + + + #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) +- +-#define GPIO_PSC1_4 0x01000000UL +- + void init_ide_reset(void) + { + debug("init_ide_reset\n"); + + /* Configure PSC1_4 as GPIO output for ATA reset */ + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; +- *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; ++ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; + /* Deassert reset */ +- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; + } + + +@@ -223,30 +239,22 @@ void ide_set_reset(int idereset) + debug("ide_reset(%d)\n", idereset); + + if (idereset) { +- *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; + /* Make a delay. MPC5200 spec says 25 usec min */ + udelay(500000); + } else +- *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; + } + #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ + + +-void led_d4_on(void) +-{ +- /* TIMER7 as GPIO output low */ +- *(vu_long *) (MPC5XXX_GPT + 0x70) |= 0x24; +-} +- +- +-void led_d4_off(void) +-{ +- /* TIMER7 as GPIO output high */ +- *(vu_long *) (MPC5XXX_GPT + 0x70) |= 0x34; +-} +- +- ++#ifdef CONFIG_HW_WATCHDOG + void hw_watchdog_reset(void) + { +-/* TODO fill this in */ ++ /* ++ * MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog ++ * we need a positive or negative transition on WDI i.e., our PSC3_9. ++ */ ++ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9; + } ++#endif /* CONFIG_HW_WATCHDOG */ +diff -Naupr u-boot-1.1.6/CHANGELOG u-boot-1.1.6-fsl-1/CHANGELOG +--- u-boot-1.1.6/CHANGELOG 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/CHANGELOG 2006-12-06 10:33:48.000000000 -0600 +@@ -1,3 +1,737 @@ ++commit 8d9a8610b8256331132227e9e6585c6bd5742787 ++Author: Wolfgang Denk ++Date: Thu Nov 30 01:54:07 2006 +0100 ++ ++ Code cleanup. Update CHANGELOG. ++ ++commit 726e90aacf0b1ecb0e7055be574622fbe3e450ba ++Author: Grant Likely ++Date: Wed Nov 29 16:23:42 2006 +0100 ++ ++ [PATCH] [MPC52xx] Use IPB bus frequency for SOC peripherals ++ ++ The soc node of the mpc52xx needs to be loaded with the IPB bus frequency, ++ not the XLB frequency. ++ ++ This patch depends on the previous patches for MPC52xx device tree support ++ ++ Signed-off-by: Grant Likely ++ Signed-off-by: Sylvain Munaut ++ ++commit 1eac2a71417b6675b11aace72102a2e7fde8f5c6 ++Author: Stefan Roese ++Date: Wed Nov 29 15:42:37 2006 +0100 ++ ++ [PATCH] Add support for Prodrive P3M750 & P3M7448 (P3Mx) boards ++ ++ This patch adds support for the Prodrive P3M750 (PPC750 & MV64460) ++ and the P3M7448 (MPC7448 & MV64460) PMC modules. Both modules are ++ quite similar and share the same board directory "prodrive/p3mx" ++ and the same config file "p3mx.h". ++ ++ Signed-off-by: Stefan Roese ++ ++commit 1bdd46832aeb569f5e04b1f20f64318525b6525a ++Author: Stefan Roese ++Date: Wed Nov 29 12:53:15 2006 +0100 ++ ++ [PATCH] common/cmd_elf.c: Enable loadaddr as parameter in bootvx command ++ ++ In the bootvx command the load address was only read from the env ++ variable "loadaddr" and not optionally passed as paramter as described ++ in the help. This is fixed with this patch. The behaviour is now the ++ same as in the bootelf command. ++ ++ Signed-off-by: Stefan Roese ++ ++commit 4e26f1074c3ac1bd8fd094f0dc4a1c4a0b15a592 ++Author: Stefan Roese ++Date: Wed Nov 29 12:03:57 2006 +0100 ++ ++ [PATCH] include/ppc440.h minor error affecting interrupts ++ ++ Fixed include/ppc440.c for UIC address Bug ++ ++ Corrects bug affecting the addresses for the universal interrupt ++ controller UIC2 and UIC3 on the PPC440 Epx, GRx, and SPE chips. ++ ++ Signed-off-by: Jeff Mann ++ Signed-off-by: Stefan Roese ++ ++commit 1939d969443ccf316cab2bf32ab1027d4db5ba1a ++Author: Joakim Tjernlund ++Date: Tue Nov 28 16:17:27 2006 -0600 ++ ++ Make fsl-i2c not conflict with SOFT I2C ++ ++ Signed-off-by: Timur Tabi ++ ++commit 14198bf768fdc958e3c1afd2404e5262208e98d7 ++Author: Joakim Tjernlund ++Date: Tue Nov 28 16:17:18 2006 -0600 ++ ++ Fix I2C master address initialization. ++ ++ Signed-off-by: Timur Tabi ++ ++commit cf3d045e51ca8dcc6cf759827140861d6ac25c04 ++Author: Kim Phillips ++Date: Tue Nov 28 23:31:19 2006 -0600 ++ ++ Assign maintainers for mpc8349emds and mpc8360emds ++ ++ Dave for mpc8360emds, and me for mpc8349emds. ++ ++commit 1aa934c81b77f2080d3ca4b226eab67b17a33961 ++Author: Kim Phillips ++Date: Tue Nov 28 23:28:33 2006 -0600 ++ ++ Eliminate gcc 4 'used uninitialized' warnings in drivers/qe/uccf.c ++ ++ give initial values for reg_num, shift, p_cmxucr in ucc_set_clk_src ++ since they are passed by reference to ucc_get_cmxucr_reg and assigned. ++ ++commit e857a5bdb3954b896c0920cb9d8d2b1b9c107ce5 ++Author: Timur Tabi ++Date: Tue Nov 28 12:09:35 2006 -0600 ++ ++ mpc83xx: Miscellaneous code style fixes ++ ++ Implement various code style fixes and similar changes. ++ ++ Signed-off-by: Timur Tabi ++ ++commit e59581c56ab5d6e0207ddac3b2c1d55cb36ec706 ++Author: Stefan Roese ++Date: Tue Nov 28 17:55:49 2006 +0100 ++ ++ [PATCH] Enable the IceCube/lite5200 variants to pass a device tree to Linux. ++ ++ This patch adds the code and configuration necessary to boot with an ++ arch/powerpc Linux kernel. ++ ++ Signed-off-by: Grant Likely ++ Acked-by: Jon Loeliger ++ ++commit e732faec95a83cb468b4850ae807c8301dde8f6a ++Author: Stefan Roese ++Date: Tue Nov 28 16:09:24 2006 +0100 ++ ++ [PATCH] PPC4xx: 440SP Rev. C detection added ++ ++ Signed-off-by: Stefan Roese ++ ++commit e7f3e9ff01fbd7fa72eb42a9675fbed6bc4736b0 ++Author: Stefan Roese ++Date: Tue Nov 28 11:04:45 2006 +0100 ++ ++ [PATCH] nand: Fix patch merge problem ++ ++ Signed-off-by: Stefan Roese ++ ++commit 4f4b602ec7524a032bdf3c6d28c7f525a4a67eaa ++Author: Wolfgang Denk ++Date: Mon Nov 27 22:53:53 2006 +0100 ++ ++ Update CHANGELOG ++ ++commit f6e495f54cdb8fe340b9c03deab40ad746d52fae ++Author: Stefan Roese ++Date: Mon Nov 27 17:43:25 2006 +0100 ++ ++ [PATCH] 4xx_enet.c: Correct the setting of zmiifer register ++ ++ Patch below corrects the setting of the zmiifer register, it was ++ overwritting the register rather than ORing the settings. ++ ++ Signed-off-by: Neil Wilson ++ Signed-off-by: Stefan Roese ++ ++commit d1a72545296800b7e219f93104ad5836f0003d66 ++Author: Stefan Roese ++Date: Mon Nov 27 17:34:10 2006 +0100 ++ ++ [PATCH] Select NAND embedded environment from board configuration ++ ++ The current NAND Bootloader setup forces the environment ++ variables to be in line with the bootloader. This change ++ enables the configuration to be made in the board include ++ file instead so that it can be individually enabled. ++ ++ Signed-off-by: Nick Spence ++ Signed-off-by: Stefan Roese ++ ++commit 15784862857c3c2214498defcfed84ff137fb81e ++Author: Stefan Roese ++Date: Mon Nov 27 17:22:19 2006 +0100 ++ ++ [PATCH] nand_wait() timeout fixes ++ ++ Two fixes for the nand_wait() function in ++ drivers/nand/nand_base.c: ++ ++ 1. Use correct timeouts. The original timeouts in Linux ++ source are 400ms and 20ms not 40s and 20s ++ ++ 2. Return correct error value in case of timeout. 0 is ++ interpreted as OK. ++ ++ Signed-off-by: Rui Sousa ++ Signed-off-by: Stefan Roese ++ ++commit da5553b095bf04f4f109ad7e565dae3aba47b230 ++Author: Stefan Roese ++Date: Mon Nov 27 17:04:06 2006 +0100 ++ ++ [PATCH] Allow CONFIG_OF_FLAT_TREE to boot a non-arch/powerpc kernel ++ ++ This patch allows an arch/ppc kernel to be booted by just passing 1 or 2 ++ arguments to bootm. It removes the getenv("disable_of") test that used ++ to be used for this purpose. ++ ++ Signed-off-by: Grant Likely ++ Acked-by: Jon Loeliger ++ ++commit a9398e018593782c5fa7d0741955fc1256b34c1e ++Author: Wolfgang Denk ++Date: Mon Nov 27 15:32:42 2006 +0100 ++ ++ Minor code cleanup. Update CHANGELOG. ++ ++commit 1729b92cde575476684bffe819d0b7791b57bff2 ++Author: Stefan Roese ++Date: Mon Nov 27 14:52:04 2006 +0100 ++ ++ [PATCH] 4xx: Fix problem with board specific reset code (now for real) ++ ++ Signed-off-by: Stefan Roese ++ ++commit cc5ee8a92a0e3ca6f727af71b8fd206460c7afd7 ++Author: Stefan Roese ++Date: Mon Nov 27 14:49:51 2006 +0100 ++ ++ [PATCH] alpr: remove unused board specific flash driver ++ ++ Signed-off-by: Stefan Roese ++ ++commit 1f94d162e2b5f0edc28d9fb11482502c44d218e1 ++Author: Stefan Roese ++Date: Mon Nov 27 14:48:41 2006 +0100 ++ ++ [PATCH] 4xx: Fix problem with board specific reset code ++ ++ Signed-off-by: Stefan Roese ++ ++commit ec0c2ec725aec9524a177a77ce75559e644a931a ++Author: Stefan Roese ++Date: Mon Nov 27 14:46:06 2006 +0100 ++ ++ [PATCH] Remove testing 4xx enet PHY setup ++ ++ Signed-off-by: Stefan Roese ++ ++commit 1c2ce2262069510f31c7d3fd7efd3d58b8c0c148 ++Author: Stefan Roese ++Date: Mon Nov 27 14:12:17 2006 +0100 ++ ++ [PATCH] Update Prodrive ALPR board support (440GX) ++ ++ Signed-off-by: Stefan Roese ++ ++commit 78d620ebb5871d252270dedfad60c6568993b780 ++Author: Wolfgang Denk ++Date: Thu Nov 23 22:58:58 2006 +0100 ++ ++ Updates for TQM5200 modules: ++ - fix off-by-one error in board/tqm5200/cam5200_flash.c error message ++ - simplify "udate" definitions ++ ++commit 2053283304eeddf250d109e6791eb6fa4cad14f7 ++Author: Stefan Roese ++Date: Wed Nov 22 13:20:50 2006 +0100 ++ ++ [PATCH] PPC4xx start.S: Fix for processor errata ++ ++ Fixed cpu/ppc4xx/start.S for 440EPx Errata: further corrects PPC440EPx ++ errata 1.12: 440_33 by moving patch up in code. ++ ++ Signed-off-by: Jeff Mann ++ Signed-off-by: Stefan Roese ++ ++commit 4ef6251403f637841000e0fef9e832aa01339822 ++Author: Stefan Roese ++Date: Mon Nov 20 20:39:52 2006 +0100 ++ ++ [PATCH] Update AMCC Sequoia config file to support 64MByte NOR FLASH ++ ++ Signed-off-by: Stefan Roese ++ ++commit e4bbd8da164b976d38616bd9c69c5e86e193cdf0 ++Author: Wolfgang Denk ++Date: Mon Nov 20 10:28:30 2006 +0100 ++ ++ Update CHANGELOG ++ ++commit 260421a21e934a68d31fb6125b0fbd2631a8ca20 ++Author: Stefan Roese ++Date: Mon Nov 13 13:55:24 2006 +0100 ++ ++ [PATCH] CFI driver AMD Command Set Top boot geometry reversal, etc. [Updated] ++ ++ * Adds support for AMD command set Top Boot flash geometry reversal ++ * Adds support for reading JEDEC Manufacturer ID and Device ID ++ * Adds support for displaying command set, manufacturer id and ++ device ids (flinfo) ++ * Makes flinfo output to be consistent when CFG_FLASH_EMPTY_INFO defined ++ * Removes outdated change history (refer to git log instead) ++ ++ Signed-off-by: Tolunay Orkun ++ Signed-off-by: Stefan Roese ++ ++commit b21b511d4c50408f4853f46f06b601272196223f ++Author: Wolfgang Denk ++Date: Sun Nov 12 21:13:23 2006 +0100 ++ ++ Update CHANGELOG ++ ++commit ce3f1a40c507afbab06c5eb58ccdc6713eda3245 ++Author: Bartlomiej Sieka ++Date: Sat Nov 11 22:48:22 2006 +0100 ++ ++ Disable the watchdog in the default config for the V38B board. ++ ++commit 44a47e6db2694841211f1c8fdbafd36992e9cd1a ++Author: Bartlomiej Sieka ++Date: Sat Nov 11 22:43:00 2006 +0100 ++ ++ Change the GPIO pin multiplexing configuration for V38B. The USB GPIO pin ++ group is enabled for USB earlier (in cpu_init_f() instead of ++ usb_lowlevel_init()). ++ ++commit 91650b3e4de688038d4f71279c44858e3e2c6870 ++Author: Wolfgang Denk ++Date: Mon Nov 6 17:06:36 2006 +0100 ++ ++ Sequential accesses to non-existent memory must be synchronized, ++ at least on G2 cores. ++ ++ This fixes get_ram_size() problems on MPC5200 Rev. B boards. ++ ++commit be5e61815d5a1fac290ce9c0ef09cb6a8e4288fa ++Author: Timur Tabi ++Date: Fri Nov 3 19:15:00 2006 -0600 ++ ++ mpc83xx: Update 83xx to use fsl_i2c.c ++ ++ Update the 83xx tree to use I2C support in drivers/fsl_i2c.c. Delete ++ cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files. ++ Added multiple I2C bus support to fsl_i2c.c. ++ ++ Signed-off-by: Timur Tabi ++ ++commit d239d74b1c937984bc519083a8e7de373a390f06 ++Author: Timur Tabi ++Date: Fri Nov 3 12:00:28 2006 -0600 ++ ++ mpc83xx: Replace CFG_IMMRBAR with CFG_IMMR ++ ++ Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx ++ tree matches the other 8xxx trees. ++ ++ Signed-off-by: Timur Tabi ++ ++commit f7fb2e703ec9688541416962724adff70a7322cb ++Author: Kim Phillips ++Date: Thu Nov 2 19:47:11 2006 -0600 ++ ++ mpc83xx: Lindent and clean up cpu/mpc83xx/speed.c ++ ++commit 90f30a710a3c619b5405860a686c4ddfc495d4b6 ++Author: Dave Liu ++Date: Thu Nov 2 18:05:50 2006 -0600 ++ ++ mpc83xx: Fix the incorrect dcbz operation ++ ++ The 834x rev1.x silicon has one CPU5 errata. ++ ++ The issue is when the data cache locked with ++ HID0[DLOCK], the dcbz instruction looks like no-op inst. ++ ++ The right behavior of the data cache is when the data cache ++ Locked with HID0[DLOCK], the dcbz instruction allocates ++ new tags in cache. ++ ++ The 834x rev3.0 and later and 8360 have not this bug inside. ++ ++ So, when 834x rev3.0/8360 are working with ECC, the dcbz ++ instruction will corrupt the stack in cache, the processor will ++ checkstop reset. ++ ++ However, the 834x rev1.x can work with ECC with these code, ++ because the sillicon has this cache bug. The dcbz will not ++ corrupt the stack in cache. ++ Really, it is the fault code running on fault sillicon. ++ ++ This patch fix the incorrect dcbz operation. Instead of ++ CPU FP writing to initialise the ECC. ++ ++ CHANGELOG: ++ * Fix the incorrect dcbz operation instead of CPU FP ++ writing to initialise the ECC memory. Otherwise, it ++ will corrupt the stack in cache, The processor will checkstop ++ reset. ++ ++ Signed-off-by: Dave Liu ++ ++commit bf0b542d6773a5a1cbce77691f009b06d9aeb57d ++Author: Kim Phillips ++Date: Wed Nov 1 00:10:40 2006 -0600 ++ ++ mpc83xx: add OF_FLAT_TREE bits to 83xx boards ++ ++ add ft_pci_setup, OF_CPU, OF_SOC, OF_TBCLK, and ++ STDOUT_PATH configuration bits to mpc8349emds, ++ mpc8349itx, and mpc8360emds board code. ++ ++ redo environment to use bootm with the fdtaddr ++ for booting ARCH=powerpc kernels by default, ++ and provide default fdtaddr values. ++ ++commit 48041365b3420589ad464ebc7752e0053538b729 ++Author: Kim Phillips ++Date: Wed Nov 1 00:07:25 2006 -0600 ++ ++ mpc83xx: change ft code to modify local-mac-address property ++ ++ Update 83xx OF code to update local-mac-address properties ++ for ethernet instead of the obsolete 'address' property. ++ ++commit 9ca880a250870a7d55754291b5591d2b5fe89b54 ++Author: Timur Tabi ++Date: Tue Oct 31 21:23:16 2006 -0600 ++ ++ mpc83xx: Fix dual I2C support for the MPC8349ITX, MPC8349EMDS, TQM834x, and MPC8360EMDS ++ ++ This patch also adds an improved I2C set_speed(), which handles all clock ++ frequencies. ++ ++ Signed-off-by: Timur Tabi ++ ++commit ac4b5622ce050b5ee1e154b98df630d778661632 ++Author: Dave Liu ++Date: Tue Oct 31 19:54:59 2006 -0600 ++ ++ mpc83xx: add the README.mpc8360emds ++ ++ add doc/README.mpc8360emds to accompany the new board support ++ ++commit 7737d5c658c606f999dfbe3e86b0fed49e5c50ef ++Author: Dave Liu ++Date: Fri Nov 3 12:11:15 2006 -0600 ++ ++ mpc83xx: add QE ethernet support ++ ++ this patch adds support for the QUICC Engine based UCC gigabit ethernet device. ++ ++commit 5f8204394e39bbe8cd9f08b8f8d145b6c01f7c73 ++Author: Dave Liu ++Date: Fri Nov 3 19:33:44 2006 -0600 ++ ++ mpc83xx: Add MPC8360EMDS basic board support ++ ++ Add support for the Freescale MPC8360EMDS board. ++ Includes DDR, DUART, Local Bus, PCI. ++ ++commit 23892e49352de74f7fac36ff90bb1be143d195e3 ++Author: Dave Liu ++Date: Tue Oct 31 19:30:40 2006 -0600 ++ ++ mpc83xx: add the QUICC Engine (QE) immap file ++ ++ common QE immap file. Also required for 8360. ++ ++commit b701652a4992bdcc62fb1a6038a85beef9e55da4 ++Author: Dave Liu ++Date: Tue Oct 31 19:25:38 2006 -0600 ++ ++ mpc83xx: Add 8360 specifics to 83xx immap ++ ++ Mainly add QE device dependencies, with appropriate 8360 protection. ++ Lindent also run. ++ ++commit 988833324a7fda482c8ac3ca23eb539f8232e404 ++Author: Timur Tabi ++Date: Tue Oct 31 19:14:41 2006 -0600 ++ ++ mpc83xx: Fix PCI, USB, bootargs for MPC8349E-mITX ++ ++ PREREQUISITE PATCHES: ++ ++ * This patch can only be applied after the following patches have been applied: ++ ++ 1) DNX#2006092142000015 "Add support for the MPC8349E-mITX 1/2" ++ 2) DNX#2006092142000024 "Add support for the MPC8349E-mITX 2/2" ++ ++ CHANGELOG: ++ ++ * For the 8349E-mITX, fix some size values in pci_init_board(), enable ++ the clock for the 2nd USB board (Linux kernel will hang otherwise), ++ and fix the CONFIG_BOOTARGS macro. ++ ++ Signed-off-by: Timur Tabi ++ ++commit 2ad6b513b31070bd0c003792ed1c3e7f5d740357 ++Author: Timur Tabi ++Date: Tue Oct 31 18:44:42 2006 -0600 ++ ++ mpc83xx: Add support for the MPC8349E-mITX ++ ++ PREREQUISITE PATCHES: ++ ++ * This patch can only be applied after the following patches have been applied: ++ ++ 1) DNX#2006090742000024 "Add support for multiple I2C buses" ++ 2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x" ++ 3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c" ++ 4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems" ++ 5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems" ++ ++ CHANGELOG: ++ ++ * Add support for the Freescale MPC8349E-mITX reference design platform. ++ The second TSEC (Vitesse 7385 switch) is not supported at this time. ++ ++ Signed-off-by: Timur Tabi ++ ++commit 183da6d9b446cc12123455844ad1187e2375626f ++Author: Ben Warren ++Date: Tue Sep 12 10:15:53 2006 -0400 ++ ++ Additional MPC8349 support for multibus i2c ++ ++ Hello, ++ ++ Here is a patch for a file that was accidentally left out of a previous ++ attempt. ++ ++ It accompanies the patch with ticket DNX#2006090742000024 ++ ++ CHANGELOG: ++ Change PCI initialization to use new multi-bus I2C API. ++ ++ regards, ++ Ben ++ ++commit b24f119d672b709d153ff2ac091d4aa63ec6877d ++Author: Ben Warren ++Date: Thu Sep 7 16:51:04 2006 -0400 ++ ++ Multi-bus I2C implementation of MPC834x ++ ++ Hello, ++ ++ Attached is a patch implementing multiple I2C buses on the MPC834x CPU ++ family and the MPC8349EMDS board in particular. ++ This patch requires Patch 1 (Add support for multiple I2C buses). ++ Testing was performed on a 533MHz board. ++ ++ /*** Note: This patch replaces ticket DNX#2006083042000027 ***/ ++ ++ Signed-off-by: Ben Warren ++ ++ CHANGELOG: ++ Implemented driver-level code to support two I2C buses on the ++ MPC834x CPU family and the MPC8349EMDS board. Available I2C bus speeds ++ are 50kHz, 100kHz and 400kHz on each bus. ++ ++ regards, ++ Ben ++ ++commit bb99ad6d8257bf828f150d40f507b30d80a4a7ae ++Author: Ben Warren ++Date: Thu Sep 7 16:50:54 2006 -0400 ++ ++ Add support for multiple I2C buses ++ ++ Hello, ++ ++ Attached is a patch providing support for multiple I2C buses at the ++ command level. The second part of the patch includes an implementation ++ for the MPC834x CPU and MPC8349EMDS board. ++ ++ /*** Note: This patch replaces ticket DNX#2006083042000018 ***/ ++ ++ Signed-off-by: Ben Warren ++ ++ Overview: ++ ++ 1. Include new 'i2c' command (based on USB implementation) using ++ CONFIG_I2C_CMD_TREE. ++ ++ 2. Allow multiple buses by defining CONFIG_I2C_MULTI_BUS. Note that ++ the commands to change bus number and speed are only available under the ++ new 'i2c' command mentioned in the first bullet. ++ ++ 3. The option CFG_I2C_NOPROBES has been expanded to work in multi-bus ++ systems. When CONFIG_I2C_MULTI_BUS is used, this option takes the form ++ of an array of bus-device pairs. Otherwise, it is an array of uchar. ++ ++ CHANGELOG: ++ Added new 'i2c' master command for all I2C interaction. This is ++ conditionally compiled with CONFIG_I2C_CMD_TREE. New commands added for ++ setting I2C bus speed as well as changing the active bus if the board ++ has more than one (conditionally compiled with ++ CONFIG_I2C_MULTI_BUS). Updated NOPROBE logic to handle multiple buses. ++ Updated README. ++ ++ regards, ++ Ben ++ ++commit bed85caf872714ebf53013967a695c9d63acfc68 ++Author: Timur Tabi ++Date: Tue Oct 31 18:13:36 2006 -0600 ++ ++ mpc83xx: Add support for Errata DDR6 on MPC 834x systems ++ ++ CHANGELOG: ++ ++ * Errata DDR6, which affects all current MPC 834x processors, lists changes ++ required to maintain compatibility with various types of DDR memory. This ++ patch implements those changes. ++ ++ Signed-off-by: Timur Tabi ++ ++commit afd6e470f639883002c7c59d562690a5cb0f4865 ++Author: Timur Tabi ++Date: Wed Oct 25 18:45:23 2006 -0500 ++ ++ mpc83xx: fix TQM build by defining a CFG_FLASH_SIZE for it ++ ++commit 31068b7c4abeefcb2c8fd4fbeccc8ec6c6d0475a ++Author: Timur Tabi ++Date: Tue Aug 22 17:07:00 2006 -0500 ++ ++ mpc83xx: Add support for variable flash memory sizes on 83xx systems ++ ++ CHANGELOG: ++ ++ * On 83xx systems, use the CFG_FLASH_SIZE macro to program the LBC local access ++ window registers, instead of using a hard-coded value of 8MB. ++ ++ Signed-off-by: Timur Tabi ++ ++commit 2fc34ae66e73fa7841d1a006dc1b5dcbc1f78965 ++Author: Tanya Jiang ++Date: Thu Aug 3 18:38:13 2006 +0800 ++ ++ mpc83xx: Unified TQM834x variable names with 83xx and consolidated macros ++ ++ Unified TQM834x variable names with 83xx and consolidated macro ++ in preparation for the 8360 and other upcoming 83xx devices. ++ ++ Signed-off-by: Tanya Jiang ++ ++commit f6eda7f80ccc13d658020268c507d7173cf2e8aa ++Author: Dave Liu ++Date: Wed Oct 25 14:41:21 2006 -0500 ++ ++ mpc83xx: Changed to unified mpx83xx names and added common 83xx changes ++ ++ Incorporated the common unified variable names and the changes in preparation ++ for releasing mpc8360 patches. ++ ++ Signed-off-by: Dave Liu ++ ++commit 3894c46c27c64891f93ac04edde86a9fa9758d92 ++Author: Tanya Jiang ++Date: Thu Aug 3 18:36:02 2006 +0800 ++ ++ mpc83xx: Fix missing build for mpc8349emds pci.c ++ ++ Make pci build for mpc8349emds ++ ++ Signed-off-by: Tanya Jiang ++ ++commit 09a81ff740b29deea1e2ab08a3c2ac136c2e6219 ++Author: Tanya Jiang ++Date: Thu Aug 3 18:39:49 2006 +0800 ++ ++ mpc83xx: Removed unused file resetvec.S for mpc83xx cpu ++ ++ Removed unused file resetvec.S for mpc83xx cpu ++ ++ Signed-off-by: Tanya Jiang ++ ++commit 04f899fc465c3e44f2b55ecc70618f5696fc0ddf ++Author: Nick Spence ++Date: Sat Sep 30 00:32:59 2006 -0700 ++ ++ NAND Flash verify across block boundaries ++ ++ This patch addresses a problem when CONFIG_MTD_NAND_VERIFY_WRITE is ++ defined ++ and the write crosses a block boundary. The pointer to the verification ++ buffer (bufstart) is not being updated to reflect the starting of the ++ new ++ block so the verification of the second block fails. ++ ++ CHANGELOG: ++ ++ * Fix NAND FLASH page verification across block boundaries ++ ++commit f484dc791a3932537213c43c654cc1295c64b84c ++Author: Nick Spence ++Date: Thu Sep 7 07:39:46 2006 -0700 ++ ++ Added RGMII support to the TSECs and Marvell 881111 Phy ++ ++ Added a phy initialization to adjust the RGMII RX and TX timing ++ Always set the R100 bit in 100 BaseT mode regardless of the TSEC mode ++ ++ Signed-off-by: Nick Spence ++ ++commit c59200443072353044aa4bf737a5a60f9a9af231 ++Author: Wolfgang Denk ++Date: Thu Nov 2 15:15:01 2006 +0100 ++ ++ Release U-Boot 1.1.6 ++ ++commit 25721b5cec2be4bce79cfade17ec8f6aa1e67526 ++Author: Bartlomiej Sieka ++Date: Wed Nov 1 02:04:38 2006 +0100 ++ ++ Finish up support for MarelV38B board ++ - add watchdog support ++ - enable GPIO_WKUP_7 pin for input ++ - code cleanup ++ ++commit ffa150bc90c943ca265170bd1be3f293674dd5c7 ++Author: Bartlomiej Sieka ++Date: Wed Nov 1 01:45:46 2006 +0100 ++ ++ - Fix issues related to the use of ELDK 4 when compiling for MarelV38B: ++ * remove warnings when compiling ethaddr.c ++ * adjust linker script (fixes a crash resulting from incorrect ++ definition of __u_boot_cmd_start) ++ - Some MarelV38B code cleanup. ++ ++commit dae80f3caf9754a6dd3ddf3cf903d0c46cbd4385 ++Author: Bartlomiej Sieka ++Date: Wed Nov 1 01:38:16 2006 +0100 ++ ++ - Add MPC5XXX register definition MPC5XXX_WU_GPIO_DATA_I and change the ++ MPC5XXX_WU_GPIO_DATA macro to MPC5XXX_WU_GPIO_DATA_O (per MPC5200 User's ++ Manual). Replace the uses of MPC5XXX_WU_GPIO_DATA with ++ MPC5XXX_WU_GPIO_DATA_O for affected boards. ++ ++ - Add defintions for some MPC5XXX GPIO pins. ++ ++commit 82d9c9ec29a1bec1b03ba616425ebaed231072c8 ++Author: Bartlomiej Sieka ++Date: Wed Nov 1 01:34:29 2006 +0100 ++ ++ Changed MarelV38B board make target to lowercase. Config file cleanup. ++ + commit 1954be6e9c9421b45d0a9d05b10356acc7563150 + Author: Wolfgang Denk + Date: Sun Oct 29 01:03:51 2006 +0200 +@@ -451,6 +1185,34 @@ Date: Tue Oct 10 17:02:22 2006 -0500 + + Fix whitespace and 80-col issues. + ++commit 5c912cb1c31266c66ca59b36f9b6f87296421d75 ++Author: Stefan Roese ++Date: Sat Oct 7 11:36:51 2006 +0200 ++ ++ CFG_NAND_QUIET_TEST added to not warn upon missing NAND device ++ Patch by Stefan Roese, 07 Oct 2006 ++ ++commit 5bc528fa4da751d472397b308137238a6465afd2 ++Author: Stefan Roese ++Date: Sat Oct 7 11:35:25 2006 +0200 ++ ++ Update ALPR code (NAND support working now) ++ Patch by Stefan Roese, 07 Oct 2006 ++ ++commit 77d5034847d328753b80c46b83f960a14a26f40e ++Author: Stefan Roese ++Date: Sat Oct 7 11:33:03 2006 +0200 ++ ++ Remove compile warnings in fpga code ++ Patch by Stefan Roese, 07 Oct 2006 ++ ++commit f3443867e90d2979a7dd1c65b0d537777e1f9850 ++Author: Stefan Roese ++Date: Sat Oct 7 11:30:52 2006 +0200 ++ ++ Add CONFIG_BOARD_RESET to configure board specific reset function ++ Patch by Stefan Roese, 07 Oct 2006 ++ + commit f55df18187e7a45cb73fec4370d12135e6691ae1 + Author: John Traill + Date: Fri Sep 29 08:23:12 2006 +0100 +@@ -683,6 +1445,21 @@ Date: Wed Aug 16 10:54:09 2006 -0500 + + Signed-off-by: Matthew McClintock + ++commit 899620c2d66d4eef3b2a0034d062e71d45d886c9 ++Author: Stefan Roese ++Date: Tue Aug 15 14:22:35 2006 +0200 ++ ++ Add initial support for the ALPR board from Prodrive ++ NAND needs some additional testing ++ Patch by Heiko Schocher, 15 Aug 2006 ++ ++commit f0ff4692ff3372dec55074a8eb444943ab095abb ++Author: Stefan Roese ++Date: Tue Aug 15 14:15:51 2006 +0200 ++ ++ Add FPGA Altera Cyclone 2 support ++ Patch by Heiko Schocher, 15 Aug 2006 ++ + commit fecf1c7e4de1b2779edc18742b91c22bdc32b68b + Author: Jon Loeliger + Date: Mon Aug 14 15:33:38 2006 -0500 +diff -Naupr u-boot-1.1.6/common/altera.c u-boot-1.1.6-fsl-1/common/altera.c +--- u-boot-1.1.6/common/altera.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/common/altera.c 2006-11-30 12:34:13.000000000 -0600 +@@ -50,15 +50,20 @@ int altera_load( Altera_desc *desc, void + { + int ret_val = FPGA_FAIL; /* assume a failure */ + +- if (!altera_validate (desc, __FUNCTION__)) { ++ if (!altera_validate (desc, (char *)__FUNCTION__)) { + printf ("%s: Invalid device descriptor\n", __FUNCTION__); + } else { + switch (desc->family) { + case Altera_ACEX1K: ++ case Altera_CYC2: + #if (CONFIG_FPGA & CFG_ACEX1K) + PRINTF ("%s: Launching the ACEX1K Loader...\n", + __FUNCTION__); + ret_val = ACEX1K_load (desc, buf, bsize); ++#elif (CONFIG_FPGA & CFG_CYCLON2) ++ PRINTF ("%s: Launching the CYCLON II Loader...\n", ++ __FUNCTION__); ++ ret_val = CYC2_load (desc, buf, bsize); + #else + printf ("%s: No support for ACEX1K devices.\n", + __FUNCTION__); +@@ -78,7 +83,7 @@ int altera_dump( Altera_desc *desc, void + { + int ret_val = FPGA_FAIL; /* assume a failure */ + +- if (!altera_validate (desc, __FUNCTION__)) { ++ if (!altera_validate (desc, (char *)__FUNCTION__)) { + printf ("%s: Invalid device descriptor\n", __FUNCTION__); + } else { + switch (desc->family) { +@@ -106,13 +111,16 @@ int altera_info( Altera_desc *desc ) + { + int ret_val = FPGA_FAIL; + +- if (altera_validate (desc, __FUNCTION__)) { ++ if (altera_validate (desc, (char *)__FUNCTION__)) { + printf ("Family: \t"); + switch (desc->family) { + case Altera_ACEX1K: + printf ("ACEX1K\n"); + break; + /* Add new family types here */ ++ case Altera_CYC2: ++ printf ("CYCLON II\n"); ++ break; + default: + printf ("Unknown family type, %d\n", desc->family); + } +@@ -147,8 +155,11 @@ int altera_info( Altera_desc *desc ) + printf ("Device Function Table @ 0x%p\n", desc->iface_fns); + switch (desc->family) { + case Altera_ACEX1K: ++ case Altera_CYC2: + #if (CONFIG_FPGA & CFG_ACEX1K) + ACEX1K_info (desc); ++#elif (CONFIG_FPGA & CFG_CYCLON2) ++ CYC2_info (desc); + #else + /* just in case */ + printf ("%s: No support for ACEX1K devices.\n", +@@ -176,7 +187,7 @@ int altera_reloc( Altera_desc *desc, ulo + { + int ret_val = FPGA_FAIL; /* assume a failure */ + +- if (!altera_validate (desc, __FUNCTION__)) { ++ if (!altera_validate (desc, (char *)__FUNCTION__)) { + printf ("%s: Invalid device descriptor\n", __FUNCTION__); + } else { + switch (desc->family) { +@@ -188,6 +199,14 @@ int altera_reloc( Altera_desc *desc, ulo + __FUNCTION__); + #endif + break; ++ case Altera_CYC2: ++#if (CONFIG_FPGA & CFG_CYCLON2) ++ ret_val = CYC2_reloc (desc, reloc_offset); ++#else ++ printf ("%s: No support for CYCLON II devices.\n", ++ __FUNCTION__); ++#endif ++ break; + /* Add new family types here */ + default: + printf ("%s: Unsupported family type, %d\n", +diff -Naupr u-boot-1.1.6/common/cmd_bootm.c u-boot-1.1.6-fsl-1/common/cmd_bootm.c +--- u-boot-1.1.6/common/cmd_bootm.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/common/cmd_bootm.c 2006-11-30 12:34:13.000000000 -0600 +@@ -833,10 +833,6 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int fl + printf ("ERROR: flat device tree size does not agree with image\n"); + return; + } +- +- } else if (getenv("disable_of") == NULL) { +- printf ("ERROR: bootm needs flat device tree as third argument\n"); +- return; + } + #endif + if (!data) { +@@ -913,23 +909,11 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int fl + + SHOW_BOOT_PROGRESS (15); + +-#ifndef CONFIG_OF_FLAT_TREE +- + #if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) + unlock_ram_in_cache(); + #endif + +- /* +- * Linux Kernel Parameters: +- * r3: ptr to board info data +- * r4: initrd_start or 0 if no initrd +- * r5: initrd_end - unused if r4 is 0 +- * r6: Start of command line string +- * r7: End of command line string +- */ +- (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end); +- +-#else /* CONFIG_OF_FLAT_TREE */ ++#ifdef CONFIG_OF_FLAT_TREE + /* move of_flat_tree if needed */ + if (of_data) { + ulong of_start, of_len; +@@ -948,30 +932,36 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int fl + of_start, of_start + of_len - 1); + memmove ((void *)of_start, (void *)of_data, of_len); + } ++#endif + +- ft_setup(of_flat_tree, kbd, initrd_start, initrd_end); +- /* ft_dump_blob(of_flat_tree); */ +- +-#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) +- unlock_ram_in_cache(); ++ /* ++ * Linux Kernel Parameters (passing board info data): ++ * r3: ptr to board info data ++ * r4: initrd_start or 0 if no initrd ++ * r5: initrd_end - unused if r4 is 0 ++ * r6: Start of command line string ++ * r7: End of command line string ++ */ ++#ifdef CONFIG_OF_FLAT_TREE ++ if (!of_flat_tree) /* no device tree; boot old style */ + #endif ++ (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end); ++ /* does not return */ ++ ++#ifdef CONFIG_OF_FLAT_TREE + /* +- * Linux Kernel Parameters: ++ * Linux Kernel Parameters (passing device tree): + * r3: ptr to OF flat tree, followed by the board info data + * r4: physical pointer to the kernel itself + * r5: NULL + * r6: NULL + * r7: NULL + */ +- if (getenv("disable_of") != NULL) +- (*kernel) ((bd_t *)of_flat_tree, initrd_start, initrd_end, +- cmd_start, cmd_end); +- else { +- ft_setup(of_flat_tree, kbd, initrd_start, initrd_end); +- /* ft_dump_blob(of_flat_tree); */ +- (*kernel) ((bd_t *)of_flat_tree, (ulong)kernel, 0, 0, 0); +- } +-#endif /* CONFIG_OF_FLAT_TREE */ ++ ft_setup(of_flat_tree, kbd, initrd_start, initrd_end); ++ /* ft_dump_blob(of_flat_tree); */ ++ ++ (*kernel) ((bd_t *)of_flat_tree, (ulong)kernel, 0, 0, 0); ++#endif + } + #endif /* CONFIG_PPC */ + +diff -Naupr u-boot-1.1.6/common/cmd_elf.c u-boot-1.1.6-fsl-1/common/cmd_elf.c +--- u-boot-1.1.6/common/cmd_elf.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/common/cmd_elf.c 2006-12-06 10:33:49.000000000 -0600 +@@ -79,7 +79,7 @@ int do_bootelf (cmd_tbl_t *cmdtp, int fl + * be either an ELF image or a raw binary. Will attempt to setup the + * bootline and other parameters correctly. + * ====================================================================== */ +-int do_bootvx ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ++int do_bootvx (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) + { + unsigned long addr; /* Address of image */ + unsigned long bootaddr; /* Address to put the bootline */ +@@ -96,12 +96,10 @@ int do_bootvx ( cmd_tbl_t *cmdtp, int fl + * If we don't know where the image is then we're done. + */ + +- if ((tmp = getenv ("loadaddr")) != NULL) { +- addr = simple_strtoul (tmp, NULL, 16); +- } else { +- puts ("No load address provided\n"); +- return 1; +- } ++ if (argc < 2) ++ addr = load_addr; ++ else ++ addr = simple_strtoul (argv[1], NULL, 16); + + #if (CONFIG_COMMANDS & CFG_CMD_NET) + /* Check to see if we need to tftp the image ourselves before starting */ +diff -Naupr u-boot-1.1.6/common/cmd_fpga.c u-boot-1.1.6-fsl-1/common/cmd_fpga.c +--- u-boot-1.1.6/common/cmd_fpga.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/common/cmd_fpga.c 2006-11-30 12:34:13.000000000 -0600 +@@ -55,6 +55,7 @@ static int fpga_get_op (char *opstr); + #define FPGA_LOAD 1 + #define FPGA_LOADB 2 + #define FPGA_DUMP 3 ++#define FPGA_LOADMK 4 + + /* Convert bitstream data and load into the fpga */ + int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) +@@ -251,6 +252,23 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag + rc = fpga_loadbitstream(dev, fpga_data, data_size); + break; + ++ case FPGA_LOADMK: ++ { ++ image_header_t header; ++ image_header_t *hdr = &header; ++ ulong data; ++ ++ memmove (&header, (char *)fpga_data, sizeof(image_header_t)); ++ if (ntohl(hdr->ih_magic) != IH_MAGIC) { ++ puts ("Bad Magic Number\n"); ++ return 1; ++ } ++ data = ((ulong)fpga_data + sizeof(image_header_t)); ++ data_size = ntohl(hdr->ih_size); ++ rc = fpga_load (dev, (void *)data, data_size); ++ } ++ break; ++ + case FPGA_DUMP: + rc = fpga_dump (dev, fpga_data, data_size); + break; +@@ -282,6 +300,8 @@ static int fpga_get_op (char *opstr) + op = FPGA_LOADB; + } else if (!strcmp ("load", opstr)) { + op = FPGA_LOAD; ++ } else if (!strcmp ("loadmk", opstr)) { ++ op = FPGA_LOADMK; + } else if (!strcmp ("dump", opstr)) { + op = FPGA_DUMP; + } +@@ -299,5 +319,6 @@ U_BOOT_CMD (fpga, 6, 1, do_fpga, + "\tinfo\tlist known device information\n" + "\tload\tLoad device from memory buffer\n" + "\tloadb\tLoad device from bitstream buffer (Xilinx devices only)\n" ++ "\tloadmk\tLoad device generated with mkimage\n" + "\tdump\tLoad device to memory buffer\n"); + #endif /* CONFIG_FPGA && CONFIG_COMMANDS & CFG_CMD_FPGA */ +diff -Naupr u-boot-1.1.6/common/cmd_i2c.c u-boot-1.1.6-fsl-1/common/cmd_i2c.c +--- u-boot-1.1.6/common/cmd_i2c.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/common/cmd_i2c.c 2006-11-30 12:34:13.000000000 -0600 +@@ -101,8 +101,31 @@ static uchar i2c_mm_last_chip; + static uint i2c_mm_last_addr; + static uint i2c_mm_last_alen; + ++/* If only one I2C bus is present, the list of devices to ignore when ++ * the probe command is issued is represented by a 1D array of addresses. ++ * When multiple buses are present, the list is an array of bus-address ++ * pairs. The following macros take care of this */ ++ + #if defined(CFG_I2C_NOPROBES) ++#if defined(CONFIG_I2C_MULTI_BUS) ++static struct ++{ ++ uchar bus; ++ uchar addr; ++} i2c_no_probes[] = CFG_I2C_NOPROBES; ++#define GET_BUS_NUM i2c_get_bus_num() ++#define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b)) ++#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a)) ++#define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr ++#else /* single bus */ + static uchar i2c_no_probes[] = CFG_I2C_NOPROBES; ++#define GET_BUS_NUM 0 ++#define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */ ++#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a)) ++#define NO_PROBE_ADDR(i) i2c_no_probes[(i)] ++#endif /* CONFIG_MULTI_BUS */ ++ ++#define NUM_ELEMENTS_NOPROBE (sizeof(i2c_no_probes)/sizeof(i2c_no_probes[0])) + #endif + + static int +@@ -151,7 +174,7 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int fl + */ + addr = simple_strtoul(argv[2], NULL, 16); + alen = 1; +- for(j = 0; j < 8; j++) { ++ for (j = 0; j < 8; j++) { + if (argv[2][j] == '.') { + alen = argv[2][j+1] - '0'; + if (alen > 4) { +@@ -159,9 +182,8 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int fl + return 1; + } + break; +- } else if (argv[2][j] == '\0') { ++ } else if (argv[2][j] == '\0') + break; +- } + } + + /* +@@ -185,9 +207,9 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int fl + + linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes; + +- if(i2c_read(chip, addr, alen, linebuf, linebytes) != 0) { ++ if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0) + puts ("Error reading the chip.\n"); +- } else { ++ else { + printf("%04x:", addr); + cp = linebuf; + for (j=0; j 4) { ++ if (alen > 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + break; +- } else if (argv[2][j] == '\0') { ++ } else if (argv[2][j] == '\0') + break; +- } + } + + /* +@@ -277,16 +298,14 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int fl + /* + * Optional count + */ +- if(argc == 5) { ++ if (argc == 5) + count = simple_strtoul(argv[4], NULL, 16); +- } else { ++ else + count = 1; +- } + + while (count-- > 0) { +- if(i2c_write(chip, addr++, alen, &byte, 1) != 0) { ++ if (i2c_write(chip, addr++, alen, &byte, 1) != 0) + puts ("Error writing the chip.\n"); +- } + /* + * Wait for the write to complete. The write can take + * up to 10mSec (we allow a little more time). +@@ -303,9 +322,9 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int fl + #endif + + #if 0 +- for(timeout = 0; timeout < 10; timeout++) { ++ for (timeout = 0; timeout < 10; timeout++) { + udelay(2000); +- if(i2c_probe(chip) == 0) ++ if (i2c_probe(chip) == 0) + break; + } + #endif +@@ -346,17 +365,16 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int fl + */ + addr = simple_strtoul(argv[2], NULL, 16); + alen = 1; +- for(j = 0; j < 8; j++) { ++ for (j = 0; j < 8; j++) { + if (argv[2][j] == '.') { + alen = argv[2][j+1] - '0'; +- if(alen > 4) { ++ if (alen > 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + break; +- } else if (argv[2][j] == '\0') { ++ } else if (argv[2][j] == '\0') + break; +- } + } + + /* +@@ -371,19 +389,16 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int fl + */ + crc = 0; + err = 0; +- while(count-- > 0) { +- if(i2c_read(chip, addr, alen, &byte, 1) != 0) { ++ while (count-- > 0) { ++ if (i2c_read(chip, addr, alen, &byte, 1) != 0) + err++; +- } + crc = crc32 (crc, &byte, 1); + addr++; + } +- if(err > 0) +- { ++ if (err > 0) + puts ("Error reading the chip,\n"); +- } else { ++ else + printf ("%08lx\n", crc); +- } + + return 0; + } +@@ -441,17 +456,16 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrfl + */ + addr = simple_strtoul(argv[2], NULL, 16); + alen = 1; +- for(j = 0; j < 8; j++) { ++ for (j = 0; j < 8; j++) { + if (argv[2][j] == '.') { + alen = argv[2][j+1] - '0'; +- if(alen > 4) { ++ if (alen > 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + break; +- } else if (argv[2][j] == '\0') { ++ } else if (argv[2][j] == '\0') + break; +- } + } + } + +@@ -461,17 +475,16 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrfl + */ + do { + printf("%08lx:", addr); +- if(i2c_read(chip, addr, alen, (uchar *)&data, size) != 0) { ++ if (i2c_read(chip, addr, alen, (uchar *)&data, size) != 0) + puts ("\nError reading the chip,\n"); +- } else { ++ else { + data = cpu_to_be32(data); +- if(size == 1) { ++ if (size == 1) + printf(" %02lx", (data >> 24) & 0x000000FF); +- } else if(size == 2) { ++ else if (size == 2) + printf(" %04lx", (data >> 16) & 0x0000FFFF); +- } else { ++ else + printf(" %08lx", data); +- } + } + + nbytes = readline (" ? "); +@@ -488,19 +501,17 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrfl + #endif + } + #ifdef CONFIG_BOOT_RETRY_TIME +- else if (nbytes == -2) { ++ else if (nbytes == -2) + break; /* timed out, exit the command */ +- } + #endif + else { + char *endp; + + data = simple_strtoul(console_buffer, &endp, 16); +- if(size == 1) { ++ if (size == 1) + data = data << 24; +- } else if(size == 2) { ++ else if (size == 2) + data = data << 16; +- } + data = be32_to_cpu(data); + nbytes = endp - console_buffer; + if (nbytes) { +@@ -510,9 +521,8 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrfl + */ + reset_cmd_timeout(); + #endif +- if(i2c_write(chip, addr, alen, (uchar *)&data, size) != 0) { ++ if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0) + puts ("Error writing the chip.\n"); +- } + #ifdef CFG_EEPROM_PAGE_WRITE_DELAY_MS + udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); + #endif +@@ -538,14 +548,15 @@ int do_i2c_probe (cmd_tbl_t *cmdtp, int + int j; + #if defined(CFG_I2C_NOPROBES) + int k, skip; +-#endif ++ uchar bus = GET_BUS_NUM; ++#endif /* NOPROBES */ + + puts ("Valid chip addresses:"); +- for(j = 0; j < 128; j++) { ++ for (j = 0; j < 128; j++) { + #if defined(CFG_I2C_NOPROBES) + skip = 0; +- for (k = 0; k < sizeof(i2c_no_probes); k++){ +- if (j == i2c_no_probes[k]){ ++ for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) { ++ if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) { + skip = 1; + break; + } +@@ -553,16 +564,17 @@ int do_i2c_probe (cmd_tbl_t *cmdtp, int + if (skip) + continue; + #endif +- if(i2c_probe(j) == 0) { ++ if (i2c_probe(j) == 0) + printf(" %02X", j); +- } + } + putc ('\n'); + + #if defined(CFG_I2C_NOPROBES) + puts ("Excluded chip addresses:"); +- for( k = 0; k < sizeof(i2c_no_probes); k++ ) +- printf(" %02X", i2c_no_probes[k] ); ++ for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) { ++ if (COMPARE_BUS(bus,k)) ++ printf(" %02X", NO_PROBE_ADDR(k)); ++ } + putc ('\n'); + #endif + +@@ -601,7 +613,7 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int fl + */ + addr = simple_strtoul(argv[2], NULL, 16); + alen = 1; +- for(j = 0; j < 8; j++) { ++ for (j = 0; j < 8; j++) { + if (argv[2][j] == '.') { + alen = argv[2][j+1] - '0'; + if (alen > 4) { +@@ -609,9 +621,8 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int fl + return 1; + } + break; +- } else if (argv[2][j] == '\0') { ++ } else if (argv[2][j] == '\0') + break; +- } + } + + /* +@@ -619,24 +630,21 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int fl + */ + length = 1; + length = simple_strtoul(argv[3], NULL, 16); +- if(length > sizeof(bytes)) { ++ if (length > sizeof(bytes)) + length = sizeof(bytes); +- } + + /* + * The delay time (uSec) is optional. + */ + delay = 1000; +- if (argc > 3) { ++ if (argc > 3) + delay = simple_strtoul(argv[4], NULL, 10); +- } + /* + * Run the loop... + */ +- while(1) { +- if(i2c_read(chip, addr, alen, bytes, length) != 0) { ++ while (1) { ++ if (i2c_read(chip, addr, alen, bytes, length) != 0) + puts ("Error reading the chip.\n"); +- } + udelay(delay); + } + +@@ -671,7 +679,7 @@ int do_sdram ( cmd_tbl_t *cmdtp, int fl + */ + chip = simple_strtoul(argv[1], NULL, 16); + +- if(i2c_read(chip, 0, 1, data, sizeof(data)) != 0) { ++ if (i2c_read(chip, 0, 1, data, sizeof(data)) != 0) { + puts ("No SDRAM Serial Presence Detect found.\n"); + return 1; + } +@@ -680,7 +688,7 @@ int do_sdram ( cmd_tbl_t *cmdtp, int fl + for (j = 0; j < 63; j++) { + cksum += data[j]; + } +- if(cksum != data[63]) { ++ if (cksum != data[63]) { + printf ("WARNING: Configuration data checksum failure:\n" + " is 0x%02x, calculated 0x%02x\n", + data[63], cksum); +@@ -696,17 +704,15 @@ int do_sdram ( cmd_tbl_t *cmdtp, int fl + default: puts ("unknown\n"); break; + } + puts ("Row address bits "); +- if((data[3] & 0x00F0) == 0) { ++ if ((data[3] & 0x00F0) == 0) + printf("%d\n", data[3] & 0x0F); +- } else { ++ else + printf("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F); +- } + puts ("Column address bits "); +- if((data[4] & 0x00F0) == 0) { ++ if ((data[4] & 0x00F0) == 0) + printf("%d\n", data[4] & 0x0F); +- } else { ++ else + printf("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F); +- } + printf("Module rows %d\n", data[5]); + printf("Module data width %d bits\n", (data[7] << 8) | data[6]); + puts ("Interface signal levels "); +@@ -729,11 +735,10 @@ int do_sdram ( cmd_tbl_t *cmdtp, int fl + case 2: puts ("ECC\n"); break; + default: puts ("unknown\n"); break; + } +- if((data[12] & 0x80) == 0) { ++ if ((data[12] & 0x80) == 0) + puts ("No self refresh, rate "); +- } else { ++ else + puts ("Self refresh, rate "); +- } + switch(data[12] & 0x7F) { + case 0: puts ("15.625uS\n"); break; + case 1: puts ("3.9uS\n"); break; +@@ -744,17 +749,16 @@ int do_sdram ( cmd_tbl_t *cmdtp, int fl + default: puts ("unknown\n"); break; + } + printf("SDRAM width (primary) %d\n", data[13] & 0x7F); +- if((data[13] & 0x80) != 0) { ++ if ((data[13] & 0x80) != 0) { + printf(" (second bank) %d\n", + 2 * (data[13] & 0x7F)); + } +- if(data[14] != 0) { ++ if (data[14] != 0) { + printf("EDC width %d\n", + data[14] & 0x7F); +- if((data[14] & 0x80) != 0) { ++ if ((data[14] & 0x80) != 0) + printf(" (second bank) %d\n", + 2 * (data[14] & 0x7F)); +- } + } + printf("Min clock delay, back-to-back random column addresses %d\n", + data[15]); +@@ -852,18 +856,18 @@ int do_sdram ( cmd_tbl_t *cmdtp, int fl + (data[35] & 0x80) ? '-' : '+', + (data[35] >> 4) & 0x07, data[35] & 0x0F); + puts ("Manufacturer's JEDEC ID "); +- for(j = 64; j <= 71; j++) ++ for (j = 64; j <= 71; j++) + printf("%02X ", data[j]); + putc ('\n'); + printf("Manufacturing Location %02X\n", data[72]); + puts ("Manufacturer's Part Number "); +- for(j = 73; j <= 90; j++) ++ for (j = 73; j <= 90; j++) + printf("%02X ", data[j]); + putc ('\n'); + printf("Revision Code %02X %02X\n", data[91], data[92]); + printf("Manufacturing Date %02X %02X\n", data[93], data[94]); + puts ("Assembly Serial Number "); +- for(j = 95; j <= 98; j++) ++ for (j = 95; j <= 98; j++) + printf("%02X ", data[j]); + putc ('\n'); + printf("Speed rating PC%d\n", +@@ -873,6 +877,74 @@ int do_sdram ( cmd_tbl_t *cmdtp, int fl + } + #endif /* CFG_CMD_SDRAM */ + ++#if defined(CONFIG_I2C_CMD_TREE) ++#if defined(CONFIG_I2C_MULTI_BUS) ++int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) ++{ ++ int bus_idx, ret=0; ++ ++ if (argc == 1) ++ /* querying current setting */ ++ printf("Current bus is %d\n", i2c_get_bus_num()); ++ else { ++ bus_idx = simple_strtoul(argv[1], NULL, 10); ++ printf("Setting bus to %d\n", bus_idx); ++ ret = i2c_set_bus_num(bus_idx); ++ if (ret) ++ printf("Failure changing bus number (%d)\n", ret); ++ } ++ return ret; ++} ++#endif /* CONFIG_I2C_MULTI_BUS */ ++ ++int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) ++{ ++ int speed, ret=0; ++ ++ if (argc == 1) ++ /* querying current speed */ ++ printf("Current bus speed=%d\n", i2c_get_bus_speed()); ++ else { ++ speed = simple_strtoul(argv[1], NULL, 10); ++ printf("Setting bus speed to %d Hz\n", speed); ++ ret = i2c_set_bus_speed(speed); ++ if (ret) ++ printf("Failure changing bus speed (%d)\n", ret); ++ } ++ return ret; ++} ++ ++int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) ++{ ++#if defined(CONFIG_I2C_MULTI_BUS) ++ if (!strncmp(argv[1], "de", 2)) ++ return do_i2c_bus_num(cmdtp, flag, --argc, ++argv); ++#endif /* CONFIG_I2C_MULTI_BUS */ ++ if (!strncmp(argv[1], "sp", 2)) ++ return do_i2c_bus_speed(cmdtp, flag, --argc, ++argv); ++ if (!strncmp(argv[1], "md", 2)) ++ return do_i2c_md(cmdtp, flag, --argc, ++argv); ++ if (!strncmp(argv[1], "mm", 2)) ++ return do_i2c_mm(cmdtp, flag, --argc, ++argv); ++ if (!strncmp(argv[1], "mw", 2)) ++ return do_i2c_mw(cmdtp, flag, --argc, ++argv); ++ if (!strncmp(argv[1], "nm", 2)) ++ return do_i2c_nm(cmdtp, flag, --argc, ++argv); ++ if (!strncmp(argv[1], "cr", 2)) ++ return do_i2c_crc(cmdtp, flag, --argc, ++argv); ++ if (!strncmp(argv[1], "pr", 2)) ++ return do_i2c_probe(cmdtp, flag, --argc, ++argv); ++ if (!strncmp(argv[1], "lo", 2)) ++ return do_i2c_loop(cmdtp, flag, --argc, ++argv); ++#if (CONFIG_COMMANDS & CFG_CMD_SDRAM) ++ if (!strncmp(argv[1], "sd", 2)) ++ return do_sdram(cmdtp, flag, --argc, ++argv); ++#endif /* CFG_CMD_SDRAM */ ++ else ++ printf ("Usage:\n%s\n", cmdtp->usage); ++ return 0; ++} ++#endif /* CONFIG_I2C_CMD_TREE */ + + /***************************************************/ + +@@ -930,4 +1002,26 @@ U_BOOT_CMD( + " (valid chip values 50..57)\n" + ); + #endif ++ ++#if defined(CONFIG_I2C_CMD_TREE) ++U_BOOT_CMD( ++ i2c, 6, 1, do_i2c, ++ "i2c - I2C sub-system\n", ++#if defined(CONFIG_I2C_MULTI_BUS) ++ "dev [dev] - show or set current I2C bus\n" ++#endif /* CONFIG_I2C_MULTI_BUS */ ++ "i2c speed [speed] - show or set I2C bus speed\n" ++ "i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n" ++ "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n" ++ "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n" ++ "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n" ++ "i2c crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n" ++ "i2c probe - show devices on the I2C bus\n" ++ "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n" ++#if (CONFIG_COMMANDS & CFG_CMD_SDRAM) ++ "i2c sdram chip - print SDRAM configuration information\n" ++#endif /* CFG_CMD_SDRAM */ ++); ++#endif /* CONFIG_I2C_CMD_TREE */ ++ + #endif /* CFG_CMD_I2C */ +diff -Naupr u-boot-1.1.6/common/cmd_nand.c u-boot-1.1.6-fsl-1/common/cmd_nand.c +--- u-boot-1.1.6/common/cmd_nand.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/common/cmd_nand.c 2006-12-06 10:33:49.000000000 -0600 +@@ -684,178 +684,182 @@ extern int nand_write_oob(struct nand_ch + size_t len, size_t *retlen, const u_char *buf); + + +-int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ++int do_nand (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) + { +- int rcode = 0; ++ int rcode = 0; + +- switch (argc) { +- case 0: +- case 1: +- printf ("Usage:\n%s\n", cmdtp->usage); +- return 1; +- case 2: +- if (strcmp(argv[1],"info") == 0) { +- int i; +- +- putc ('\n'); +- +- for (i=0; iusage); ++ return 1; ++ case 2: ++ if (strcmp (argv[1], "info") == 0) { ++ int i; + +- } else if (strcmp(argv[1],"device") == 0) { +- if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) { +- puts ("\nno devices available\n"); +- return 1; +- } +- printf ("\nDevice %d: ", curr_device); +- nand_print(&nand_dev_desc[curr_device]); +- return 0; +- +- } else if (strcmp(argv[1],"bad") == 0) { +- if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) { +- puts ("\nno devices available\n"); +- return 1; +- } +- printf ("\nDevice %d bad blocks:\n", curr_device); +- nand_print_bad(&nand_dev_desc[curr_device]); +- return 0; ++ putc ('\n'); + +- } +- printf ("Usage:\n%s\n", cmdtp->usage); +- return 1; +- case 3: +- if (strcmp(argv[1],"device") == 0) { +- int dev = (int)simple_strtoul(argv[2], NULL, 10); +- +- printf ("\nDevice %d: ", dev); +- if (dev >= CFG_MAX_NAND_DEVICE) { +- puts ("unknown device\n"); +- return 1; +- } +- nand_print(&nand_dev_desc[dev]); +- /*nand_print (dev);*/ ++ for (i = 0; i < CFG_MAX_NAND_DEVICE; ++i) { ++ if (nand_dev_desc[i].ChipID == ++ NAND_ChipID_UNKNOWN) ++ continue; /* list only known devices */ ++ printf ("Device %d: ", i); ++ nand_print (&nand_dev_desc[i]); ++ } ++ return 0; ++ ++ } else if (strcmp (argv[1], "device") == 0) { ++ if ((curr_device < 0) ++ || (curr_device >= CFG_MAX_NAND_DEVICE)) { ++ puts ("\nno devices available\n"); ++ return 1; ++ } ++ printf ("\nDevice %d: ", curr_device); ++ nand_print (&nand_dev_desc[curr_device]); ++ return 0; ++ ++ } else if (strcmp (argv[1], "bad") == 0) { ++ if ((curr_device < 0) ++ || (curr_device >= CFG_MAX_NAND_DEVICE)) { ++ puts ("\nno devices available\n"); ++ return 1; ++ } ++ printf ("\nDevice %d bad blocks:\n", curr_device); ++ nand_print_bad (&nand_dev_desc[curr_device]); ++ return 0; + +- if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) { +- return 1; + } ++ printf ("Usage:\n%s\n", cmdtp->usage); ++ return 1; ++ case 3: ++ if (strcmp (argv[1], "device") == 0) { ++ int dev = (int) simple_strtoul (argv[2], NULL, 10); + +- curr_device = dev; ++ printf ("\nDevice %d: ", dev); ++ if (dev >= CFG_MAX_NAND_DEVICE) { ++ puts ("unknown device\n"); ++ return 1; ++ } ++ nand_print (&nand_dev_desc[dev]); ++ /*nand_print (dev); */ + +- puts ("... is now current device\n"); ++ if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) { ++ return 1; ++ } + +- return 0; +- } +- else if (strcmp(argv[1],"erase") == 0 && strcmp(argv[2], "clean") == 0) { +- struct nand_chip* nand = &nand_dev_desc[curr_device]; +- ulong off = 0; +- ulong size = nand->totlen; +- int ret; ++ curr_device = dev; + +- printf ("\nNAND erase: device %d offset %ld, size %ld ... ", +- curr_device, off, size); ++ puts ("... is now current device\n"); + +- ret = nand_legacy_erase (nand, off, size, 1); ++ return 0; ++ } else if (strcmp (argv[1], "erase") == 0 ++ && strcmp (argv[2], "clean") == 0) { ++ struct nand_chip *nand = &nand_dev_desc[curr_device]; ++ ulong off = 0; ++ ulong size = nand->totlen; ++ int ret; + +- printf("%s\n", ret ? "ERROR" : "OK"); ++ printf ("\nNAND erase: device %d offset %ld, size %ld ... ", curr_device, off, size); + +- return ret; +- } ++ ret = nand_legacy_erase (nand, off, size, 1); + +- printf ("Usage:\n%s\n", cmdtp->usage); +- return 1; +- default: +- /* at least 4 args */ +- +- if (strncmp(argv[1], "read", 4) == 0 || +- strncmp(argv[1], "write", 5) == 0) { +- ulong addr = simple_strtoul(argv[2], NULL, 16); +- ulong off = simple_strtoul(argv[3], NULL, 16); +- ulong size = simple_strtoul(argv[4], NULL, 16); +- int cmd = (strncmp(argv[1], "read", 4) == 0) ? +- NANDRW_READ : NANDRW_WRITE; +- int ret, total; +- char* cmdtail = strchr(argv[1], '.'); ++ printf ("%s\n", ret ? "ERROR" : "OK"); + +- if (cmdtail && !strncmp(cmdtail, ".oob", 2)) { +- /* read out-of-band data */ +- if (cmd & NANDRW_READ) { +- ret = nand_read_oob(nand_dev_desc + curr_device, +- off, size, (size_t *)&total, +- (u_char*)addr); +- } +- else { +- ret = nand_write_oob(nand_dev_desc + curr_device, +- off, size, (size_t *)&total, +- (u_char*)addr); +- } + return ret; + } +- else if (cmdtail && !strncmp(cmdtail, ".jffs2", 2)) +- cmd |= NANDRW_JFFS2; /* skip bad blocks */ +- else if (cmdtail && !strncmp(cmdtail, ".jffs2s", 2)) { +- cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ +- if (cmd & NANDRW_READ) +- cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ +- } ++ ++ printf ("Usage:\n%s\n", cmdtp->usage); ++ return 1; ++ default: ++ /* at least 4 args */ ++ ++ if (strncmp (argv[1], "read", 4) == 0 || ++ strncmp (argv[1], "write", 5) == 0) { ++ ulong addr = simple_strtoul (argv[2], NULL, 16); ++ ulong off = simple_strtoul (argv[3], NULL, 16); ++ ulong size = simple_strtoul (argv[4], NULL, 16); ++ int cmd = (strncmp (argv[1], "read", 4) == 0) ? ++ NANDRW_READ : NANDRW_WRITE; ++ int ret, total; ++ char *cmdtail = strchr (argv[1], '.'); ++ ++ if (cmdtail && !strncmp (cmdtail, ".oob", 2)) { ++ /* read out-of-band data */ ++ if (cmd & NANDRW_READ) { ++ ret = nand_read_oob (nand_dev_desc + curr_device, ++ off, size, (size_t *) & total, ++ (u_char *) addr); ++ } else { ++ ret = nand_write_oob (nand_dev_desc + curr_device, ++ off, size, (size_t *) & total, ++ (u_char *) addr); ++ } ++ return ret; ++ } else if (cmdtail && !strncmp (cmdtail, ".jffs2", 2)) ++ cmd |= NANDRW_JFFS2; /* skip bad blocks */ ++ else if (cmdtail && !strncmp (cmdtail, ".jffs2s", 2)) { ++ cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ ++ if (cmd & NANDRW_READ) ++ cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ ++ } + #ifdef SXNI855T +- /* need ".e" same as ".j" for compatibility with older units */ +- else if (cmdtail && !strcmp(cmdtail, ".e")) +- cmd |= NANDRW_JFFS2; /* skip bad blocks */ ++ /* need ".e" same as ".j" for compatibility with older units */ ++ else if (cmdtail && !strcmp (cmdtail, ".e")) ++ cmd |= NANDRW_JFFS2; /* skip bad blocks */ + #endif + #ifdef CFG_NAND_SKIP_BAD_DOT_I +- /* need ".i" same as ".jffs2s" for compatibility with older units (esd) */ +- /* ".i" for image -> read skips bad block (no 0xff) */ +- else if (cmdtail && !strcmp(cmdtail, ".i")) { +- cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ +- if (cmd & NANDRW_READ) +- cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ +- } ++ /* need ".i" same as ".jffs2s" for compatibility with older units (esd) */ ++ /* ".i" for image -> read skips bad block (no 0xff) */ ++ else if (cmdtail && !strcmp (cmdtail, ".i")) { ++ cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ ++ if (cmd & NANDRW_READ) ++ cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ ++ } + #endif /* CFG_NAND_SKIP_BAD_DOT_I */ +- else if (cmdtail) { +- printf ("Usage:\n%s\n", cmdtp->usage); +- return 1; +- } ++ else if (cmdtail) { ++ printf ("Usage:\n%s\n", cmdtp->usage); ++ return 1; ++ } + +- printf ("\nNAND %s: device %d offset %ld, size %ld ...\n", +- (cmd & NANDRW_READ) ? "read" : "write", +- curr_device, off, size); +- +- ret = nand_legacy_rw(nand_dev_desc + curr_device, cmd, off, size, +- (size_t *)&total, (u_char*)addr); +- +- printf (" %d bytes %s: %s\n", total, +- (cmd & NANDRW_READ) ? "read" : "written", +- ret ? "ERROR" : "OK"); +- +- return ret; +- } else if (strcmp(argv[1],"erase") == 0 && +- (argc == 4 || strcmp("clean", argv[2]) == 0)) { +- int clean = argc == 5; +- ulong off = simple_strtoul(argv[2 + clean], NULL, 16); +- ulong size = simple_strtoul(argv[3 + clean], NULL, 16); +- int ret; +- +- printf ("\nNAND erase: device %d offset %ld, size %ld ...\n", +- curr_device, off, size); ++ printf ("\nNAND %s: device %d offset %ld, size %ld ...\n", ++ (cmd & NANDRW_READ) ? "read" : "write", ++ curr_device, off, size); ++ ++ ret = nand_legacy_rw (nand_dev_desc + curr_device, ++ cmd, off, size, ++ (size_t *) & total, ++ (u_char *) addr); ++ ++ printf (" %d bytes %s: %s\n", total, ++ (cmd & NANDRW_READ) ? "read" : "written", ++ ret ? "ERROR" : "OK"); + +- ret = nand_legacy_erase (nand_dev_desc + curr_device, +- off, size, clean); ++ return ret; ++ } else if (strcmp (argv[1], "erase") == 0 && ++ (argc == 4 || strcmp ("clean", argv[2]) == 0)) { ++ int clean = argc == 5; ++ ulong off = ++ simple_strtoul (argv[2 + clean], NULL, 16); ++ ulong size = ++ simple_strtoul (argv[3 + clean], NULL, 16); ++ int ret; + +- printf("%s\n", ret ? "ERROR" : "OK"); ++ printf ("\nNAND erase: device %d offset %ld, size %ld ...\n", ++ curr_device, off, size); + +- return ret; +- } else { +- printf ("Usage:\n%s\n", cmdtp->usage); +- rcode = 1; +- } ++ ret = nand_legacy_erase (nand_dev_desc + curr_device, ++ off, size, clean); + +- return rcode; +- } ++ printf ("%s\n", ret ? "ERROR" : "OK"); ++ ++ return ret; ++ } else { ++ printf ("Usage:\n%s\n", cmdtp->usage); ++ rcode = 1; ++ } ++ ++ return rcode; ++ } + } + + U_BOOT_CMD( +diff -Naupr u-boot-1.1.6/common/cyclon2.c u-boot-1.1.6-fsl-1/common/cyclon2.c +--- u-boot-1.1.6/common/cyclon2.c 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/common/cyclon2.c 2006-11-30 12:34:13.000000000 -0600 +@@ -0,0 +1,305 @@ ++/* ++ * (C) Copyright 2006 ++ * Heiko Schocher, hs@denx.de ++ * Based on ACE1XK.c ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++ ++#include /* core U-Boot definitions */ ++#include ++#include /* ACEX device family */ ++ ++#if (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2)) ++ ++/* Define FPGA_DEBUG to get debug printf's */ ++#ifdef FPGA_DEBUG ++#define PRINTF(fmt,args...) printf (fmt ,##args) ++#else ++#define PRINTF(fmt,args...) ++#endif ++ ++/* Note: The assumption is that we cannot possibly run fast enough to ++ * overrun the device (the Slave Parallel mode can free run at 50MHz). ++ * If there is a need to operate slower, define CONFIG_FPGA_DELAY in ++ * the board config file to slow things down. ++ */ ++#ifndef CONFIG_FPGA_DELAY ++#define CONFIG_FPGA_DELAY() ++#endif ++ ++#ifndef CFG_FPGA_WAIT ++#define CFG_FPGA_WAIT CFG_HZ/10 /* 100 ms */ ++#endif ++ ++static int CYC2_ps_load( Altera_desc *desc, void *buf, size_t bsize ); ++static int CYC2_ps_dump( Altera_desc *desc, void *buf, size_t bsize ); ++/* static int CYC2_ps_info( Altera_desc *desc ); */ ++static int CYC2_ps_reloc( Altera_desc *desc, ulong reloc_offset ); ++ ++/* ------------------------------------------------------------------------- */ ++/* CYCLON2 Generic Implementation */ ++int CYC2_load (Altera_desc * desc, void *buf, size_t bsize) ++{ ++ int ret_val = FPGA_FAIL; ++ ++ switch (desc->iface) { ++ case passive_serial: ++ PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__); ++ ret_val = CYC2_ps_load (desc, buf, bsize); ++ break; ++ ++ /* Add new interface types here */ ++ ++ default: ++ printf ("%s: Unsupported interface type, %d\n", ++ __FUNCTION__, desc->iface); ++ } ++ ++ return ret_val; ++} ++ ++int CYC2_dump (Altera_desc * desc, void *buf, size_t bsize) ++{ ++ int ret_val = FPGA_FAIL; ++ ++ switch (desc->iface) { ++ case passive_serial: ++ PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__); ++ ret_val = CYC2_ps_dump (desc, buf, bsize); ++ break; ++ ++ /* Add new interface types here */ ++ ++ default: ++ printf ("%s: Unsupported interface type, %d\n", ++ __FUNCTION__, desc->iface); ++ } ++ ++ return ret_val; ++} ++ ++int CYC2_info( Altera_desc *desc ) ++{ ++ return FPGA_SUCCESS; ++} ++ ++int CYC2_reloc (Altera_desc * desc, ulong reloc_offset) ++{ ++ int ret_val = FPGA_FAIL; /* assume a failure */ ++ ++ if (desc->family != Altera_CYC2) { ++ printf ("%s: Unsupported family type, %d\n", ++ __FUNCTION__, desc->family); ++ return FPGA_FAIL; ++ } else ++ switch (desc->iface) { ++ case passive_serial: ++ ret_val = CYC2_ps_reloc (desc, reloc_offset); ++ break; ++ ++ /* Add new interface types here */ ++ ++ default: ++ printf ("%s: Unsupported interface type, %d\n", ++ __FUNCTION__, desc->iface); ++ } ++ ++ return ret_val; ++} ++ ++/* ------------------------------------------------------------------------- */ ++/* CYCLON2 Passive Serial Generic Implementation */ ++static int CYC2_ps_load (Altera_desc * desc, void *buf, size_t bsize) ++{ ++ int ret_val = FPGA_FAIL; /* assume the worst */ ++ Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns; ++ int ret = 0; ++ ++ PRINTF ("%s: start with interface functions @ 0x%p\n", ++ __FUNCTION__, fn); ++ ++ if (fn) { ++ int cookie = desc->cookie; /* make a local copy */ ++ unsigned long ts; /* timestamp */ ++ ++ PRINTF ("%s: Function Table:\n" ++ "ptr:\t0x%p\n" ++ "struct: 0x%p\n" ++ "config:\t0x%p\n" ++ "status:\t0x%p\n" ++ "write:\t0x%p\n" ++ "done:\t0x%p\n\n", ++ __FUNCTION__, &fn, fn, fn->config, fn->status, ++ fn->write, fn->done); ++#ifdef CFG_FPGA_PROG_FEEDBACK ++ printf ("Loading FPGA Device %d...", cookie); ++#endif ++ ++ /* ++ * Run the pre configuration function if there is one. ++ */ ++ if (*fn->pre) { ++ (*fn->pre) (cookie); ++ } ++ ++ /* Establish the initial state */ ++ (*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */ ++ ++ udelay(2); /* T_cfg > 2us */ ++ ++ /* Wait for nSTATUS to be asserted */ ++ ts = get_timer (0); /* get current time */ ++ do { ++ CONFIG_FPGA_DELAY (); ++ if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */ ++ puts ("** Timeout waiting for STATUS to go high.\n"); ++ (*fn->abort) (cookie); ++ return FPGA_FAIL; ++ } ++ } while (!(*fn->status) (cookie)); ++ ++ /* Get ready for the burn */ ++ CONFIG_FPGA_DELAY (); ++ ++ ret = (*fn->write) (buf, bsize, TRUE, cookie); ++ if (ret) { ++ puts ("** Write failed.\n"); ++ (*fn->abort) (cookie); ++ return FPGA_FAIL; ++ } ++#ifdef CFG_FPGA_PROG_FEEDBACK ++ puts(" OK? ..."); ++#endif ++ ++ CONFIG_FPGA_DELAY (); ++ ++#ifdef CFG_FPGA_PROG_FEEDBACK ++ putc (' '); /* terminate the dotted line */ ++#endif ++ ++ /* ++ * Checking FPGA's CONF_DONE signal - correctly booted ? ++ */ ++ ++ if ( ! (*fn->done) (cookie) ) { ++ puts ("** Booting failed! CONF_DONE is still deasserted.\n"); ++ (*fn->abort) (cookie); ++ return (FPGA_FAIL); ++ } ++#ifdef CFG_FPGA_PROG_FEEDBACK ++ puts(" OK\n"); ++#endif ++ ++ ret_val = FPGA_SUCCESS; ++ ++#ifdef CFG_FPGA_PROG_FEEDBACK ++ if (ret_val == FPGA_SUCCESS) { ++ puts ("Done.\n"); ++ } ++ else { ++ puts ("Fail.\n"); ++ } ++#endif ++ (*fn->post) (cookie); ++ ++ } else { ++ printf ("%s: NULL Interface function table!\n", __FUNCTION__); ++ } ++ ++ return ret_val; ++} ++ ++static int CYC2_ps_dump (Altera_desc * desc, void *buf, size_t bsize) ++{ ++ /* Readback is only available through the Slave Parallel and */ ++ /* boundary-scan interfaces. */ ++ printf ("%s: Passive Serial Dumping is unavailable\n", ++ __FUNCTION__); ++ return FPGA_FAIL; ++} ++ ++static int CYC2_ps_reloc (Altera_desc * desc, ulong reloc_offset) ++{ ++ int ret_val = FPGA_FAIL; /* assume the worst */ ++ Altera_CYC2_Passive_Serial_fns *fn_r, *fn = ++ (Altera_CYC2_Passive_Serial_fns *) (desc->iface_fns); ++ ++ if (fn) { ++ ulong addr; ++ ++ /* Get the relocated table address */ ++ addr = (ulong) fn + reloc_offset; ++ fn_r = (Altera_CYC2_Passive_Serial_fns *) addr; ++ ++ if (!fn_r->relocated) { ++ ++ if (memcmp (fn_r, fn, ++ sizeof (Altera_CYC2_Passive_Serial_fns)) ++ == 0) { ++ /* good copy of the table, fix the descriptor pointer */ ++ desc->iface_fns = fn_r; ++ } else { ++ PRINTF ("%s: Invalid function table at 0x%p\n", ++ __FUNCTION__, fn_r); ++ return FPGA_FAIL; ++ } ++ ++ PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, ++ desc); ++ ++ addr = (ulong) (fn->pre) + reloc_offset; ++ fn_r->pre = (Altera_pre_fn) addr; ++ ++ addr = (ulong) (fn->config) + reloc_offset; ++ fn_r->config = (Altera_config_fn) addr; ++ ++ addr = (ulong) (fn->status) + reloc_offset; ++ fn_r->status = (Altera_status_fn) addr; ++ ++ addr = (ulong) (fn->done) + reloc_offset; ++ fn_r->done = (Altera_done_fn) addr; ++ ++ addr = (ulong) (fn->write) + reloc_offset; ++ fn_r->write = (Altera_write_fn) addr; ++ ++ addr = (ulong) (fn->abort) + reloc_offset; ++ fn_r->abort = (Altera_abort_fn) addr; ++ ++ addr = (ulong) (fn->post) + reloc_offset; ++ fn_r->post = (Altera_post_fn) addr; ++ ++ fn_r->relocated = TRUE; ++ ++ } else { ++ /* this table has already been moved */ ++ /* XXX - should check to see if the descriptor is correct */ ++ desc->iface_fns = fn_r; ++ } ++ ++ ret_val = FPGA_SUCCESS; ++ } else { ++ printf ("%s: NULL Interface function table!\n", __FUNCTION__); ++ } ++ ++ return ret_val; ++} ++ ++#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2)) */ +diff -Naupr u-boot-1.1.6/common/fpga.c u-boot-1.1.6-fsl-1/common/fpga.c +--- u-boot-1.1.6/common/fpga.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/common/fpga.c 2006-11-30 12:34:13.000000000 -0600 +@@ -139,7 +139,7 @@ static int fpga_dev_info( int devnum ) + printf( "Xilinx Device\nDescriptor @ 0x%p\n", desc ); + ret_val = xilinx_info( desc->devdesc ); + #else +- fpga_no_sup( __FUNCTION__, "Xilinx devices" ); ++ fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); + #endif + break; + case fpga_altera: +@@ -178,7 +178,7 @@ int fpga_reloc( fpga_type devtype, void + #if CONFIG_FPGA & CFG_FPGA_XILINX + ret_val = xilinx_reloc( desc, reloc_off ); + #else +- fpga_no_sup( __FUNCTION__, "Xilinx devices" ); ++ fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); + #endif + break; + case fpga_altera: +@@ -271,7 +271,7 @@ int fpga_load( int devnum, void *buf, si + #if CONFIG_FPGA & CFG_FPGA_XILINX + ret_val = xilinx_load( desc->devdesc, buf, bsize ); + #else +- fpga_no_sup( __FUNCTION__, "Xilinx devices" ); ++ fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); + #endif + break; + case fpga_altera: +@@ -304,7 +304,7 @@ int fpga_dump( int devnum, void *buf, si + #if CONFIG_FPGA & CFG_FPGA_XILINX + ret_val = xilinx_dump( desc->devdesc, buf, bsize ); + #else +- fpga_no_sup( __FUNCTION__, "Xilinx devices" ); ++ fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); + #endif + break; + case fpga_altera: +diff -Naupr u-boot-1.1.6/common/Makefile u-boot-1.1.6-fsl-1/common/Makefile +--- u-boot-1.1.6/common/Makefile 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/common/Makefile 2006-11-30 12:34:13.000000000 -0600 +@@ -41,7 +41,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug. + cmd_pci.o cmd_pcmcia.o cmd_portio.o \ + cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o \ + cmd_usb.o cmd_vfd.o \ +- command.o console.o devices.o dlmalloc.o docecc.o \ ++ command.o console.o cyclon2.o devices.o dlmalloc.o docecc.o \ + environment.o env_common.o \ + env_nand.o env_dataflash.o env_flash.o env_eeprom.o \ + env_nvram.o env_nowhere.o \ +diff -Naupr u-boot-1.1.6/common/memsize.c u-boot-1.1.6-fsl-1/common/memsize.c +--- u-boot-1.1.6/common/memsize.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/common/memsize.c 2006-11-30 12:34:13.000000000 -0600 +@@ -21,6 +21,16 @@ + * MA 02111-1307 USA + */ + ++#include ++#ifdef __PPC__ ++/* ++ * At least on G2 PowerPC cores, sequential accesses to non-existent ++ * memory must be synchronized. ++ */ ++# include /* for sync() */ ++#else ++# define sync() /* nothing */ ++#endif + + /* + * Check memory range for valid RAM. A simple memory test determines +@@ -38,20 +48,27 @@ long get_ram_size(volatile long *base, l + + for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) { + addr = base + cnt; /* pointer arith! */ ++ sync (); + save[i++] = *addr; ++ sync (); + *addr = ~cnt; + } + + addr = base; ++ sync (); + save[i] = *addr; ++ sync (); + *addr = 0; + ++ sync (); + if ((val = *addr) != 0) { + /* Restore the original data before leaving the function. + */ ++ sync (); + *addr = save[i]; + for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) { + addr = base + cnt; ++ sync (); + *addr = save[--i]; + } + return (0); +diff -Naupr u-boot-1.1.6/cpu/74xx_7xx/cpu.c u-boot-1.1.6-fsl-1/cpu/74xx_7xx/cpu.c +--- u-boot-1.1.6/cpu/74xx_7xx/cpu.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/cpu/74xx_7xx/cpu.c 2006-12-06 10:33:49.000000000 -0600 +@@ -101,6 +101,10 @@ get_cpu_type(void) + type = CPU_7457; + break; + ++ case 0x8004: ++ type = CPU_7448; ++ break; ++ + default: + break; + } +@@ -152,6 +156,10 @@ int checkcpu (void) + str = "MPC7410"; + break; + ++ case CPU_7448: ++ str = "MPC7448"; ++ break; ++ + case CPU_7450: + str = "MPC7450"; + break; +@@ -221,7 +229,7 @@ soft_restart(unsigned long addr) + void + do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) + { +- ulong addr; ++ ulong addr; + /* flush and disable I/D cache */ + __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); + __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); +diff -Naupr u-boot-1.1.6/cpu/74xx_7xx/cpu_init.c u-boot-1.1.6-fsl-1/cpu/74xx_7xx/cpu_init.c +--- u-boot-1.1.6/cpu/74xx_7xx/cpu_init.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/cpu/74xx_7xx/cpu_init.c 2006-12-06 10:33:49.000000000 -0600 +@@ -43,6 +43,7 @@ cpu_init_f (void) + case CPU_7450: + case CPU_7455: + case CPU_7457: ++ case CPU_7448: + /* enable the timebase bit in HID0 */ + set_hid0(get_hid0() | 0x4000000); + break; +diff -Naupr u-boot-1.1.6/cpu/74xx_7xx/speed.c u-boot-1.1.6-fsl-1/cpu/74xx_7xx/speed.c +--- u-boot-1.1.6/cpu/74xx_7xx/speed.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/cpu/74xx_7xx/speed.c 2006-12-06 10:33:49.000000000 -0600 +@@ -91,6 +91,7 @@ int get_clocks (void) + + /* calculate the clock frequency based upon the CPU type */ + switch (get_cpu_type()) { ++ case CPU_7448: + case CPU_7455: + case CPU_7457: + /* +diff -Naupr u-boot-1.1.6/cpu/74xx_7xx/start.S u-boot-1.1.6-fsl-1/cpu/74xx_7xx/start.S +--- u-boot-1.1.6/cpu/74xx_7xx/start.S 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/cpu/74xx_7xx/start.S 2006-12-06 10:33:49.000000000 -0600 +@@ -44,7 +44,8 @@ + + #if !defined(CONFIG_DB64360) && \ + !defined(CONFIG_DB64460) && \ +- !defined(CONFIG_CPCI750) ++ !defined(CONFIG_CPCI750) && \ ++ !defined(CONFIG_P3Mx) + #include + #endif + +@@ -270,7 +271,7 @@ in_flash: + * gt-regs BAT can be reused after board_init_f calls + * board_early_init_f (EVB only). + */ +-#if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) ++#if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) && !defined(CONFIG_P3Mx) + /* enable address translation */ + bl enable_addr_trans + sync +@@ -757,7 +758,8 @@ in_ram: + defined(CONFIG_DB64360) || \ + defined(CONFIG_DB64460) || \ + defined(CONFIG_CPCI750) || \ +- defined(CONFIG_PPMC7XX) ++ defined(CONFIG_PPMC7XX) || \ ++ defined(CONFIG_P3Mx) + mr r4, r9 /* Use RAM copy of the global data */ + #endif + bl after_reloc +diff -Naupr u-boot-1.1.6/cpu/mpc5xxx/cpu.c u-boot-1.1.6-fsl-1/cpu/mpc5xxx/cpu.c +--- u-boot-1.1.6/cpu/mpc5xxx/cpu.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/cpu/mpc5xxx/cpu.c 2006-12-06 10:33:49.000000000 -0600 +@@ -31,6 +31,10 @@ + #include + #include + ++#if defined(CONFIG_OF_FLAT_TREE) ++#include ++#endif ++ + DECLARE_GLOBAL_DATA_PTR; + + int checkcpu (void) +@@ -102,3 +106,26 @@ unsigned long get_tbclk (void) + } + + /* ------------------------------------------------------------------------- */ ++ ++#ifdef CONFIG_OF_FLAT_TREE ++void ++ft_cpu_setup(void *blob, bd_t *bd) ++{ ++ u32 *p; ++ int len; ++ ++ /* Core XLB bus frequency */ ++ p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len); ++ if (p != NULL) ++ *p = cpu_to_be32(bd->bi_busfreq); ++ ++ /* SOC peripherals use the IPB bus frequency */ ++ p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len); ++ if (p != NULL) ++ *p = cpu_to_be32(bd->bi_ipbfreq); ++ ++ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/mac-address", &len); ++ if (p != NULL) ++ memcpy(p, bd->bi_enetaddr, 6); ++} ++#endif +diff -Naupr u-boot-1.1.6/cpu/mpc83xx/cpu.c u-boot-1.1.6-fsl-1/cpu/mpc83xx/cpu.c +--- u-boot-1.1.6/cpu/mpc83xx/cpu.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/cpu/mpc83xx/cpu.c 2006-11-30 12:34:13.000000000 -0600 +@@ -1,5 +1,5 @@ + /* +- * Copyright 2004 Freescale Semiconductor, Inc. ++ * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. +@@ -18,11 +18,6 @@ + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA +- * +- * Change log: +- * +- * 20050101: Eran Liberty (liberty@freescale.com) +- * Initial file creating (porting from 85XX & 8260) + */ + + /* +@@ -43,35 +38,140 @@ DECLARE_GLOBAL_DATA_PTR; + + int checkcpu(void) + { ++ volatile immap_t *immr; + ulong clock = gd->cpu_clk; + u32 pvr = get_pvr(); ++ u32 spridr; + char buf[32]; + ++ immr = (immap_t *)CFG_IMMR; ++ + if ((pvr & 0xFFFF0000) != PVR_83xx) { + puts("Not MPC83xx Family!!!\n"); + return -1; + } + +- puts("CPU: MPC83xx, "); +- switch(pvr) { +- case PVR_8349_REV10: ++ spridr = immr->sysconf.spridr; ++ puts("CPU: "); ++ switch(spridr) { ++ case SPR_8349E_REV10: ++ case SPR_8349E_REV11: ++ puts("MPC8349E, "); ++ break; ++ case SPR_8349_REV10: ++ case SPR_8349_REV11: ++ puts("MPC8349, "); ++ break; ++ case SPR_8347E_REV10_TBGA: ++ case SPR_8347E_REV11_TBGA: ++ case SPR_8347E_REV10_PBGA: ++ case SPR_8347E_REV11_PBGA: ++ puts("MPC8347E, "); ++ break; ++ case SPR_8347_REV10_TBGA: ++ case SPR_8347_REV11_TBGA: ++ case SPR_8347_REV10_PBGA: ++ case SPR_8347_REV11_PBGA: ++ puts("MPC8347, "); ++ break; ++ case SPR_8343E_REV10: ++ case SPR_8343E_REV11: ++ puts("MPC8343E, "); + break; +- case PVR_8349_REV11: ++ case SPR_8343_REV10: ++ case SPR_8343_REV11: ++ puts("MPC8343, "); ++ break; ++ case SPR_8360E_REV10: ++ case SPR_8360E_REV11: ++ case SPR_8360E_REV12: ++ puts("MPC8360E, "); ++ break; ++ case SPR_8360_REV10: ++ case SPR_8360_REV11: ++ case SPR_8360_REV12: ++ puts("MPC8360, "); + break; + default: + puts("Rev: Unknown\n"); + return -1; /* Not sure what this is */ + } +- printf("Rev: %d.%d at %s MHz\n", (pvr & 0xf0) >> 4, +- (pvr & 0x0f), strmhz(buf, clock)); + ++#if defined(CONFIG_MPC8349) ++ printf("Rev: %02x at %s MHz\n", (spridr & 0x0000FFFF)>>4 |(spridr & 0x0000000F), strmhz(buf, clock)); ++#else ++ printf("Rev: %02x at %s MHz\n", spridr & 0x0000FFFF, strmhz(buf, clock)); ++#endif + return 0; + } + + ++/* ++ * Program a UPM with the code supplied in the table. ++ * ++ * The 'dummy' variable is used to increment the MAD. 'dummy' is ++ * supposed to be a pointer to the memory of the device being ++ * programmed by the UPM. The data in the MDR is written into ++ * memory and the MAD is incremented every time there's a read ++ * from 'dummy'. Unfortunately, the current prototype for this ++ * function doesn't allow for passing the address of this ++ * device, and changing the prototype will break a number lots ++ * of other code, so we need to use a round-about way of finding ++ * the value for 'dummy'. ++ * ++ * The value can be extracted from the base address bits of the ++ * Base Register (BR) associated with the specific UPM. To find ++ * that BR, we need to scan all 8 BRs until we find the one that ++ * has its MSEL bits matching the UPM we want. Once we know the ++ * right BR, we can extract the base address bits from it. ++ * ++ * The MxMR and the BR and OR of the chosen bank should all be ++ * configured before calling this function. ++ * ++ * Parameters: ++ * upm: 0=UPMA, 1=UPMB, 2=UPMC ++ * table: Pointer to an array of values to program ++ * size: Number of elements in the array. Must be 64 or less. ++ */ + void upmconfig (uint upm, uint *table, uint size) + { +- hang(); /* FIXME: upconfig() needed? */ ++#if defined(CONFIG_MPC834X) ++ volatile immap_t *immap = (immap_t *) CFG_IMMR; ++ volatile lbus83xx_t *lbus = &immap->lbus; ++ volatile uchar *dummy = NULL; ++ const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */ ++ volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */ ++ uint i; ++ ++ /* Scan all the banks to determine the base address of the device */ ++ for (i = 0; i < 8; i++) { ++ if ((lbus->bank[i].br & BR_MSEL) == msel) { ++ dummy = (uchar *) (lbus->bank[i].br & BR_BA); ++ break; ++ } ++ } ++ ++ if (!dummy) { ++ printf("Error: %s() could not find matching BR\n", __FUNCTION__); ++ hang(); ++ } ++ ++ /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */ ++ *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000; ++ ++ for (i = 0; i < size; i++) { ++ lbus->mdr = table[i]; ++ __asm__ __volatile__ ("sync"); ++ *dummy; /* Write the value to memory and increment MAD */ ++ __asm__ __volatile__ ("sync"); ++ } ++ ++ /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */ ++ *mxmr &= 0xCFFFFFC0; ++#else ++ printf("Error: %s() not defined for this configuration.\n", __FUNCTION__); ++ hang(); ++#endif + } + + +@@ -83,7 +183,7 @@ do_reset (cmd_tbl_t * cmdtp, int flag, i + ulong addr; + #endif + +- volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; ++ volatile immap_t *immap = (immap_t *) CFG_IMMR; + + #ifdef MPC83xx_RESET + /* Interrupts and MMU off */ +@@ -150,9 +250,21 @@ unsigned long get_tbclk(void) + #if defined(CONFIG_WATCHDOG) + void watchdog_reset (void) + { +- hang(); /* FIXME: implement watchdog_reset()? */ ++#ifdef CONFIG_MPC834X ++ int re_enable = disable_interrupts(); ++ ++ /* Reset the 83xx watchdog */ ++ volatile immap_t *immr = (immap_t *) CFG_IMMR; ++ immr->wdt.swsrr = 0x556c; ++ immr->wdt.swsrr = 0xaa39; ++ ++ if (re_enable) ++ enable_interrupts (); ++#else ++ hang(); ++#endif + } +-#endif /* CONFIG_WATCHDOG */ ++#endif + + #if defined(CONFIG_OF_FLAT_TREE) + void +@@ -180,12 +292,12 @@ ft_cpu_setup(void *blob, bd_t *bd) + *p = cpu_to_be32(clock); + + #ifdef CONFIG_MPC83XX_TSEC1 +- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/address", &len); ++ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len); + memcpy(p, bd->bi_enetaddr, 6); + #endif + + #ifdef CONFIG_MPC83XX_TSEC2 +- p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/address", &len); ++ p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len); + memcpy(p, bd->bi_enet1addr, 6); + #endif + } +@@ -194,8 +306,8 @@ ft_cpu_setup(void *blob, bd_t *bd) + #if defined(CONFIG_DDR_ECC) + void dma_init(void) + { +- volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; +- volatile dma8349_t *dma = &immap->dma; ++ volatile immap_t *immap = (immap_t *)CFG_IMMR; ++ volatile dma83xx_t *dma = &immap->dma; + volatile u32 status = swab32(dma->dmasr0); + volatile u32 dmamr0 = swab32(dma->dmamr0); + +@@ -225,8 +337,8 @@ void dma_init(void) + + uint dma_check(void) + { +- volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; +- volatile dma8349_t *dma = &immap->dma; ++ volatile immap_t *immap = (immap_t *)CFG_IMMR; ++ volatile dma83xx_t *dma = &immap->dma; + volatile u32 status = swab32(dma->dmasr0); + volatile u32 byte_count = swab32(dma->dmabcr0); + +@@ -244,8 +356,8 @@ uint dma_check(void) + + int dma_xfer(void *dest, u32 count, void *src) + { +- volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; +- volatile dma8349_t *dma = &immap->dma; ++ volatile immap_t *immap = (immap_t *)CFG_IMMR; ++ volatile dma83xx_t *dma = &immap->dma; + volatile u32 dmamr0; + + /* initialize DMASARn, DMADAR and DMAABCRn */ +diff -Naupr u-boot-1.1.6/cpu/mpc83xx/cpu_init.c u-boot-1.1.6-fsl-1/cpu/mpc83xx/cpu_init.c +--- u-boot-1.1.6/cpu/mpc83xx/cpu_init.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/cpu/mpc83xx/cpu_init.c 2006-11-30 12:34:13.000000000 -0600 +@@ -1,5 +1,5 @@ + /* +- * Copyright 2004 Freescale Semiconductor, Inc. ++ * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. +@@ -18,11 +18,6 @@ + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA +- * +- * Change log: +- * +- * 20050101: Eran Liberty (liberty@freescale.com) +- * Initial file creating (porting from 85XX & 8260) + */ + + #include +@@ -31,6 +26,30 @@ + + DECLARE_GLOBAL_DATA_PTR; + ++#ifdef CONFIG_QE ++extern qe_iop_conf_t qe_iop_conf_tab[]; ++extern void qe_config_iopin(u8 port, u8 pin, int dir, ++ int open_drain, int assign); ++extern void qe_init(uint qe_base); ++extern void qe_reset(void); ++ ++static void config_qe_ioports(void) ++{ ++ u8 port, pin; ++ int dir, open_drain, assign; ++ int i; ++ ++ for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { ++ port = qe_iop_conf_tab[i].port; ++ pin = qe_iop_conf_tab[i].pin; ++ dir = qe_iop_conf_tab[i].dir; ++ open_drain = qe_iop_conf_tab[i].open_drain; ++ assign = qe_iop_conf_tab[i].assign; ++ qe_config_iopin(port, pin, dir, open_drain, assign); ++ } ++} ++#endif ++ + /* + * Breathe some life into the CPU... + * +@@ -46,6 +65,37 @@ void cpu_init_f (volatile immap_t * im) + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + ++ /* system performance tweaking */ ++ ++#ifdef CFG_ACR_PIPE_DEP ++ /* Arbiter pipeline depth */ ++ im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (3 << ACR_PIPE_DEP_SHIFT); ++#endif ++ ++#ifdef CFG_SPCR_TSEC1EP ++ /* TSEC1 Emergency priority */ ++ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (3 << SPCR_TSEC1EP_SHIFT); ++#endif ++ ++#ifdef CFG_SPCR_TSEC2EP ++ /* TSEC2 Emergency priority */ ++ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (3 << SPCR_TSEC2EP_SHIFT); ++#endif ++ ++#ifdef CFG_SCCR_TSEC1CM ++ /* TSEC1 clock mode */ ++ im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (1 << SCCR_TSEC1CM_SHIFT); ++#endif ++#ifdef CFG_SCCR_TSEC2CM ++ /* TSEC2 & I2C1 clock mode */ ++ im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (1 << SCCR_TSEC2CM_SHIFT); ++#endif ++ ++#ifdef CFG_ACR_RPTCNT ++ /* Arbiter repeat count */ ++ im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (3 << ACR_RPTCNT_SHIFT)); ++#endif ++ + /* RSR - Reset Status Register - clear all status (4.6.1.3) */ + gd->reset_status = im->reset.rsr; + im->reset.rsr = ~(RSR_RES); +@@ -69,6 +119,10 @@ void cpu_init_f (volatile immap_t * im) + #ifdef CFG_SICRL + im->sysconf.sicrl = CFG_SICRL; + #endif ++#ifdef CONFIG_QE ++ /* Config QE ioports */ ++ config_qe_ioports(); ++#endif + + /* + * Memory Controller: +@@ -157,12 +211,12 @@ void cpu_init_f (volatile immap_t * im) + #endif + } + +- +-/* +- * Initialize higher level parts of CPU like time base and timers. +- */ +- + int cpu_init_r (void) + { ++#ifdef CONFIG_QE ++ uint qe_base = CFG_IMMR + 0x00100000; /* QE immr base */ ++ qe_init(qe_base); ++ qe_reset(); ++#endif + return 0; + } +diff -Naupr u-boot-1.1.6/cpu/mpc83xx/i2c.c u-boot-1.1.6-fsl-1/cpu/mpc83xx/i2c.c +--- u-boot-1.1.6/cpu/mpc83xx/i2c.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/cpu/mpc83xx/i2c.c 1969-12-31 18:00:00.000000000 -0600 +@@ -1,253 +0,0 @@ +-/* +- * (C) Copyright 2003,Motorola Inc. +- * Xianghua Xiao +- * Adapted for Motorola 85xx chip. +- * +- * (C) Copyright 2003 +- * Gleb Natapov +- * Some bits are taken from linux driver writen by adrian@humboldt.co.uk +- * +- * Hardware I2C driver for MPC107 PCI bridge. +- * +- * See file CREDITS for list of people who contributed to this +- * project. +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, +- * MA 02111-1307 USA +- * +- * Change log: +- * +- * 20050101: Eran Liberty (liberty@freescale.com) +- * Initial file creating (porting from 85XX & 8260) +- */ +- +-#include +-#include +-#include +- +-#ifdef CONFIG_HARD_I2C +-#include +-#include +- +-#if defined(CONFIG_MPC8349EMDS) || defined(CONFIG_TQM834X) +-i2c_t * mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET); +-#endif +- +-void +-i2c_init(int speed, int slaveadd) +-{ +- /* stop I2C controller */ +- writeb(0x00 , &I2C->cr); +- +- /* set clock */ +- writeb(0x3f, &I2C->fdr); +- +- /* set default filter */ +- writeb(0x10,&I2C->dfsrr); +- +- /* write slave address */ +- writeb(slaveadd, &I2C->adr); +- +- /* clear status register */ +- writeb(0x00, &I2C->sr); +- +- /* start I2C controller */ +- writeb(I2C_CR_MEN, &I2C->cr); +-} +- +-static __inline__ int +-i2c_wait4bus (void) +-{ +- ulong timeval = get_timer (0); +- while (readb(&I2C->sr) & I2C_SR_MBB) { +- if (get_timer (timeval) > I2C_TIMEOUT) { +- return -1; +- } +- } +- return 0; +-} +- +-static __inline__ int +-i2c_wait (int write) +-{ +- u32 csr; +- ulong timeval = get_timer(0); +- do { +- csr = readb(&I2C->sr); +- +- if (!(csr & I2C_SR_MIF)) +- continue; +- +- writeb(0x0, &I2C->sr); +- +- if (csr & I2C_SR_MAL) { +- debug("i2c_wait: MAL\n"); +- return -1; +- } +- +- if (!(csr & I2C_SR_MCF)) { +- debug("i2c_wait: unfinished\n"); +- return -1; +- } +- +- if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) { +- debug("i2c_wait: No RXACK\n"); +- return -1; +- } +- +- return 0; +- } while (get_timer (timeval) < I2C_TIMEOUT); +- +- debug("i2c_wait: timed out\n"); +- return -1; +-} +- +-static __inline__ int +-i2c_write_addr (u8 dev, u8 dir, int rsta) +-{ +- writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX | +- (rsta?I2C_CR_RSTA:0), +- &I2C->cr); +- +- writeb((dev << 1) | dir, &I2C->dr); +- +- if (i2c_wait (I2C_WRITE) < 0) +- return 0; +- return 1; +-} +- +-static __inline__ int +-__i2c_write (u8 *data, int length) +-{ +- int i; +- +- writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, +- &I2C->cr); +- +- for (i=0; i < length; i++) { +- writeb(data[i], &I2C->dr); +- +- if (i2c_wait (I2C_WRITE) < 0) +- break; +- } +- return i; +-} +- +-static __inline__ int +-__i2c_read (u8 *data, int length) +-{ +- int i; +- +- writeb(I2C_CR_MEN | I2C_CR_MSTA | +- ((length == 1) ? I2C_CR_TXAK : 0), +- &I2C->cr); +- +- /* dummy read */ +- readb(&I2C->dr); +- +- for (i=0; i < length; i++) { +- if (i2c_wait (I2C_READ) < 0) +- break; +- +- /* Generate ack on last next to last byte */ +- if (i == length - 2) +- writeb(I2C_CR_MEN | I2C_CR_MSTA | +- I2C_CR_TXAK, +- &I2C->cr); +- +- /* Generate stop on last byte */ +- if (i == length - 1) +- writeb(I2C_CR_MEN | I2C_CR_TXAK, &I2C->cr); +- +- data[i] = readb(&I2C->dr); +- } +- return i; +-} +- +-int +-i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) +-{ +- int i = 0; +- u8 *a = (u8*)&addr; +- +- if (i2c_wait4bus () < 0) +- goto exit; +- +- if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) +- goto exit; +- +- if (__i2c_write (&a[4 - alen], alen) != alen) +- goto exit; +- +- if (i2c_write_addr (dev, I2C_READ, 1) == 0) +- goto exit; +- +- i = __i2c_read (data, length); +- +- exit: +- writeb(I2C_CR_MEN, &I2C->cr); +- return !(i == length); +-} +- +-int +-i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) +-{ +- int i = 0; +- u8 *a = (u8*)&addr; +- +- if (i2c_wait4bus () < 0) +- goto exit; +- +- if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) +- goto exit; +- +- if (__i2c_write (&a[4 - alen], alen) != alen) +- goto exit; +- +- i = __i2c_write (data, length); +- +- exit: +- writeb(I2C_CR_MEN, &I2C->cr); +- return !(i == length); +-} +- +-int i2c_probe (uchar chip) +-{ +- int tmp; +- +- /* +- * Try to read the first location of the chip. The underlying +- * driver doesn't appear to support sending just the chip address +- * and looking for an back. +- */ +- udelay(10000); +- return i2c_read (chip, 0, 1, (uchar *)&tmp, 1); +-} +- +-uchar i2c_reg_read (uchar i2c_addr, uchar reg) +-{ +- uchar buf[1]; +- +- i2c_read (i2c_addr, reg, 1, buf, 1); +- +- return (buf[0]); +-} +- +-void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) +-{ +- i2c_write (i2c_addr, reg, 1, &val, 1); +-} +- +-#endif /* CONFIG_HARD_I2C */ +diff -Naupr u-boot-1.1.6/cpu/mpc83xx/interrupts.c u-boot-1.1.6-fsl-1/cpu/mpc83xx/interrupts.c +--- u-boot-1.1.6/cpu/mpc83xx/interrupts.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/cpu/mpc83xx/interrupts.c 2006-11-30 12:34:13.000000000 -0600 +@@ -21,13 +21,6 @@ + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA +- * +- * Change log: +- * +- * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00 +- * +- * 20050101: Eran Liberty (liberty@freescale.com) +- * Initial file creating (porting from 85XX & 8260) + */ + + #include +@@ -45,7 +38,7 @@ struct irq_action { + + int interrupt_init_cpu (unsigned *decrementer_count) + { +- volatile immap_t *immr = (immap_t *) CFG_IMMRBAR; ++ volatile immap_t *immr = (immap_t *) CFG_IMMR; + + *decrementer_count = (gd->bus_clk / 4) / CFG_HZ; + +diff -Naupr u-boot-1.1.6/cpu/mpc83xx/Makefile u-boot-1.1.6-fsl-1/cpu/mpc83xx/Makefile +--- u-boot-1.1.6/cpu/mpc83xx/Makefile 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/cpu/mpc83xx/Makefile 2006-11-10 11:24:29.000000000 -0600 +@@ -27,9 +27,9 @@ include $(TOPDIR)/config.mk + + LIB = $(obj)lib$(CPU).a + +-START = start.o resetvec.o ++START = start.o + COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ +- i2c.o spd_sdram.o ++ spd_sdram.o qe_io.o + + SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) + OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +diff -Naupr u-boot-1.1.6/cpu/mpc83xx/qe_io.c u-boot-1.1.6-fsl-1/cpu/mpc83xx/qe_io.c +--- u-boot-1.1.6/cpu/mpc83xx/qe_io.c 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/cpu/mpc83xx/qe_io.c 2006-11-10 11:24:29.000000000 -0600 +@@ -0,0 +1,85 @@ ++/* ++ * Copyright (C) 2006 Freescale Semiconductor, Inc. ++ * ++ * Dave Liu ++ * based on source code of Shlomi Gridish ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include "common.h" ++#include "asm/errno.h" ++#include "asm/io.h" ++#include "asm/immap_83xx.h" ++ ++#if defined(CONFIG_QE) ++#define NUM_OF_PINS 32 ++void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) ++{ ++ u32 pin_2bit_mask; ++ u32 pin_2bit_dir; ++ u32 pin_2bit_assign; ++ u32 pin_1bit_mask; ++ u32 tmp_val; ++ volatile immap_t *im = (volatile immap_t *)CFG_IMMR; ++ volatile gpio83xx_t *par_io =(volatile gpio83xx_t *)&im->gpio; ++ ++ /* Caculate pin location and 2bit mask and dir */ ++ pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); ++ pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); ++ ++ /* Setup the direction */ ++ tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \ ++ in_be32(&par_io->ioport[port].dir2) : ++ in_be32(&par_io->ioport[port].dir1); ++ ++ if (pin > (NUM_OF_PINS/2) -1) { ++ out_be32(&par_io->ioport[port].dir2, ~pin_2bit_mask & tmp_val); ++ out_be32(&par_io->ioport[port].dir2, pin_2bit_dir | tmp_val); ++ } else { ++ out_be32(&par_io->ioport[port].dir1, ~pin_2bit_mask & tmp_val); ++ out_be32(&par_io->ioport[port].dir1, pin_2bit_dir | tmp_val); ++ } ++ ++ /* Calculate pin location for 1bit mask */ ++ pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); ++ ++ /* Setup the open drain */ ++ tmp_val = in_be32(&par_io->ioport[port].podr); ++ if (open_drain) { ++ out_be32(&par_io->ioport[port].podr, pin_1bit_mask | tmp_val); ++ } else { ++ out_be32(&par_io->ioport[port].podr, ~pin_1bit_mask & tmp_val); ++ } ++ ++ /* Setup the assignment */ ++ tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? ++ in_be32(&par_io->ioport[port].ppar2): ++ in_be32(&par_io->ioport[port].ppar1); ++ pin_2bit_assign = (u32)(assign ++ << (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2)); ++ ++ /* Clear and set 2 bits mask */ ++ if (pin > (NUM_OF_PINS/2) - 1) { ++ out_be32(&par_io->ioport[port].ppar2, ~pin_2bit_mask & tmp_val); ++ out_be32(&par_io->ioport[port].ppar2, pin_2bit_assign | tmp_val); ++ } else { ++ out_be32(&par_io->ioport[port].ppar1, ~pin_2bit_mask & tmp_val); ++ out_be32(&par_io->ioport[port].ppar1, pin_2bit_assign | tmp_val); ++ } ++} ++ ++#endif /* CONFIG_QE */ +diff -Naupr u-boot-1.1.6/cpu/mpc83xx/resetvec.S u-boot-1.1.6-fsl-1/cpu/mpc83xx/resetvec.S +--- u-boot-1.1.6/cpu/mpc83xx/resetvec.S 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/cpu/mpc83xx/resetvec.S 1969-12-31 18:00:00.000000000 -0600 +@@ -1,6 +0,0 @@ +- .section .resetvec,"ax" +-#ifndef FIXME +-#if 0 +- b _start_e500 +-#endif +-#endif +diff -Naupr u-boot-1.1.6/cpu/mpc83xx/spd_sdram.c u-boot-1.1.6-fsl-1/cpu/mpc83xx/spd_sdram.c +--- u-boot-1.1.6/cpu/mpc83xx/spd_sdram.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/cpu/mpc83xx/spd_sdram.c 2006-12-06 10:33:49.000000000 -0600 +@@ -1,8 +1,10 @@ + /* ++ * (C) Copyright 2006 Freescale Semiconductor, Inc. ++ * + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * +- * Copyright 2004 Freescale Semiconductor. ++ * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * (C) Copyright 2003 Motorola Inc. + * Xianghua Xiao (X.Xiao@motorola.com) + * +@@ -23,11 +25,6 @@ + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA +- * +- * Change log: +- * +- * 20050101: Eran Liberty (liberty@freescale.com) +- * Initial file creating (porting from 85XX & 8260) + */ + + #include +@@ -39,7 +36,9 @@ + + #ifdef CONFIG_SPD_EEPROM + +-#if defined(CONFIG_DDR_ECC) ++DECLARE_GLOBAL_DATA_PTR; ++ ++#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) + extern void dma_init(void); + extern uint dma_check(void); + extern int dma_xfer(void *dest, uint count, void *src); +@@ -52,16 +51,16 @@ extern int dma_xfer(void *dest, uint cou + /* + * Convert picoseconds into clock cycles (rounding up if needed). + */ +- + int + picos_to_clk(int picos) + { ++ unsigned int ddr_bus_clk; + int clks; + +- clks = picos / (2000000000 / (get_bus_freq(0) / 1000)); +- if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) { +- clks++; +- } ++ ddr_bus_clk = gd->ddr_clk >> 1; ++ clks = picos / ((1000000000 / ddr_bus_clk) * 1000); ++ if (picos % ((1000000000 / ddr_bus_clk) * 1000) != 0) ++ clks++; + + return clks; + } +@@ -103,33 +102,72 @@ static void spd_debug(spd_eeprom_t *spd) + + long int spd_sdram() + { +- volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; +- volatile ddr8349_t *ddr = &immap->ddr; +- volatile law8349_t *ecm = &immap->sysconf.ddrlaw[0]; ++ volatile immap_t *immap = (immap_t *)CFG_IMMR; ++ volatile ddr83xx_t *ddr = &immap->ddr; ++ volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0]; + spd_eeprom_t spd; +- unsigned tmp, tmp1; + unsigned int memsize; + unsigned int law_size; +- unsigned char caslat; +- unsigned int trfc, trfc_clk, trfc_low; ++ unsigned char caslat, caslat_ctrl; ++ unsigned char burstlen; ++ unsigned int max_bus_clk; ++ unsigned int max_data_rate, effective_data_rate; ++ unsigned int ddrc_clk; ++ unsigned int refresh_clk; ++ unsigned sdram_cfg; ++ unsigned int ddrc_ecc_enable; + ++ /* Read SPD parameters with I2C */ + CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd)); + #ifdef SPD_DEBUG + spd_debug(&spd); + #endif ++ /* Check the memory type */ ++ if (spd.mem_type != SPD_MEMTYPE_DDR) { ++ printf("DDR: Module mem type is %02X\n", spd.mem_type); ++ return 0; ++ } ++ ++ /* Check the number of physical bank */ + if (spd.nrows > 2) { +- puts("DDR:Only two chip selects are supported on ADS.\n"); ++ printf("DDR: The number of physical bank is %02X\n", spd.nrows); + return 0; + } + +- if (spd.nrow_addr < 12 +- || spd.nrow_addr > 14 +- || spd.ncol_addr < 8 +- || spd.ncol_addr > 11) { +- puts("DDR:Row or Col number unsupported.\n"); ++ /* Check if the number of row of the module is in the range of DDRC */ ++ if (spd.nrow_addr < 12 || spd.nrow_addr > 14) { ++ printf("DDR: Row number is out of range of DDRC, row=%02X\n", ++ spd.nrow_addr); + return 0; + } + ++ /* Check if the number of col of the module is in the range of DDRC */ ++ if (spd.ncol_addr < 8 || spd.ncol_addr > 11) { ++ printf("DDR: Col number is out of range of DDRC, col=%02X\n", ++ spd.ncol_addr); ++ return 0; ++ } ++ /* Setup DDR chip select register */ ++#ifdef CFG_83XX_DDR_USES_CS0 ++ ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1; ++ ddr->cs_config[0] = ( 1 << 31 ++ | (spd.nrow_addr - 12) << 8 ++ | (spd.ncol_addr - 8) ); ++ debug("\n"); ++ debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds); ++ debug("cs0_config = 0x%08x\n",ddr->cs_config[0]); ++ ++ if (spd.nrows == 2) { ++ ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8) ++ | ((banksize(spd.row_dens) >> 23) - 1) ); ++ ddr->cs_config[1] = ( 1<<31 ++ | (spd.nrow_addr-12) << 8 ++ | (spd.ncol_addr-8) ); ++ debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds); ++ debug("cs1_config = 0x%08x\n",ddr->cs_config[1]); ++ } ++ ++#else + ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1; + ddr->cs_config[2] = ( 1 << 31 + | (spd.nrow_addr - 12) << 8 +@@ -147,6 +185,7 @@ long int spd_sdram() + debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds); + debug("cs3_config = 0x%08x\n",ddr->cs_config[3]); + } ++#endif + + if (spd.mem_type != 0x07) { + puts("No DDR module found!\n"); +@@ -172,56 +211,136 @@ long int spd_sdram() + debug("DDR:ar=0x%08x\n", ecm->ar); + + /* +- * find the largest CAS +- */ +- if(spd.cas_lat & 0x40) { +- caslat = 7; +- } else if (spd.cas_lat & 0x20) { +- caslat = 6; +- } else if (spd.cas_lat & 0x10) { +- caslat = 5; +- } else if (spd.cas_lat & 0x08) { +- caslat = 4; +- } else if (spd.cas_lat & 0x04) { +- caslat = 3; +- } else if (spd.cas_lat & 0x02) { +- caslat = 2; +- } else if (spd.cas_lat & 0x01) { +- caslat = 1; +- } else { +- puts("DDR:no valid CAS Latency information.\n"); ++ * Find the largest CAS by locating the highest 1 bit ++ * in the spd.cas_lat field. Translate it to a DDR ++ * controller field value: ++ * ++ * CAS Lat DDR I Ctrl ++ * Clocks SPD Bit Value ++ * -------+--------+--------- ++ * 1.0 0 001 ++ * 1.5 1 010 ++ * 2.0 2 011 ++ * 2.5 3 100 ++ * 3.0 4 101 ++ * 3.5 5 110 ++ * 4.0 6 111 ++ */ ++ caslat = __ilog2(spd.cas_lat); ++ ++ if (caslat > 6 ) { ++ printf("DDR: Invalid SPD CAS Latency, caslat=%02X\n", ++ spd.cas_lat); + return 0; + } +- +- tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10 +- + (spd.clk_cycle & 0x0f)); +- debug("DDR:Module maximum data rate is: %dMhz\n", tmp); +- +- tmp1 = get_bus_freq(0) / 1000000; +- if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) { +- /* 90~230 range, treated as DDR 200 */ +- if (spd.clk_cycle3 == 0xa0) +- caslat -= 2; +- else if(spd.clk_cycle2 == 0xa0) +- caslat--; +- } else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) { +- /* 230-280 range, treated as DDR 266 */ +- if (spd.clk_cycle3 == 0x75) +- caslat -= 2; +- else if (spd.clk_cycle2 == 0x75) +- caslat--; +- } else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) { +- /* 280~350 range, treated as DDR 333 */ +- if (spd.clk_cycle3 == 0x60) +- caslat -= 2; +- else if (spd.clk_cycle2 == 0x60) +- caslat--; +- } else if (tmp1 < 90 || tmp1 >= 350) { +- /* DDR rate out-of-range */ +- puts("DDR:platform frequency is not fit for DDR rate\n"); +- return 0; ++ max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10 ++ + (spd.clk_cycle & 0x0f)); ++ max_data_rate = max_bus_clk * 2; ++ ++ debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate); ++ ++ ddrc_clk = gd->ddr_clk / 1000000; ++ ++ if (max_data_rate >= 390) { /* it is DDR 400 */ ++ if (ddrc_clk <= 410 && ddrc_clk > 350) { ++ /* DDR controller clk at 350~410 */ ++ effective_data_rate = 400; /* 5ns */ ++ caslat = caslat; ++ } else if (ddrc_clk <= 350 && ddrc_clk > 280) { ++ /* DDR controller clk at 280~350 */ ++ effective_data_rate = 333; /* 6ns */ ++ if (spd.clk_cycle2 == 0x60) ++ caslat = caslat - 1; ++ else ++ caslat = caslat; ++ } else if (ddrc_clk <= 280 && ddrc_clk > 230) { ++ /* DDR controller clk at 230~280 */ ++ effective_data_rate = 266; /* 7.5ns */ ++ if (spd.clk_cycle3 == 0x75) ++ caslat = caslat - 2; ++ else if (spd.clk_cycle2 == 0x60) ++ caslat = caslat - 1; ++ else ++ caslat = caslat; ++ } else if (ddrc_clk <= 230 && ddrc_clk > 90) { ++ /* DDR controller clk at 90~230 */ ++ effective_data_rate = 200; /* 10ns */ ++ if (spd.clk_cycle3 == 0x75) ++ caslat = caslat - 2; ++ else if (spd.clk_cycle2 == 0x60) ++ caslat = caslat - 1; ++ else ++ caslat = caslat; ++ } ++ } else if (max_data_rate >= 323) { /* it is DDR 333 */ ++ if (ddrc_clk <= 350 && ddrc_clk > 280) { ++ /* DDR controller clk at 280~350 */ ++ effective_data_rate = 333; /* 6ns */ ++ caslat = caslat; ++ } else if (ddrc_clk <= 280 && ddrc_clk > 230) { ++ /* DDR controller clk at 230~280 */ ++ effective_data_rate = 266; /* 7.5ns */ ++ if (spd.clk_cycle2 == 0x75) ++ caslat = caslat - 1; ++ else ++ caslat = caslat; ++ } else if (ddrc_clk <= 230 && ddrc_clk > 90) { ++ /* DDR controller clk at 90~230 */ ++ effective_data_rate = 200; /* 10ns */ ++ if (spd.clk_cycle3 == 0xa0) ++ caslat = caslat - 2; ++ else if (spd.clk_cycle2 == 0x75) ++ caslat = caslat - 1; ++ else ++ caslat = caslat; ++ } ++ } else if (max_data_rate >= 256) { /* it is DDR 266 */ ++ if (ddrc_clk <= 350 && ddrc_clk > 280) { ++ /* DDR controller clk at 280~350 */ ++ printf("DDR: DDR controller freq is more than " ++ "max data rate of the module\n"); ++ return 0; ++ } else if (ddrc_clk <= 280 && ddrc_clk > 230) { ++ /* DDR controller clk at 230~280 */ ++ effective_data_rate = 266; /* 7.5ns */ ++ caslat = caslat; ++ } else if (ddrc_clk <= 230 && ddrc_clk > 90) { ++ /* DDR controller clk at 90~230 */ ++ effective_data_rate = 200; /* 10ns */ ++ if (spd.clk_cycle2 == 0xa0) ++ caslat = caslat - 1; ++ } ++ } else if (max_data_rate >= 190) { /* it is DDR 200 */ ++ if (ddrc_clk <= 350 && ddrc_clk > 230) { ++ /* DDR controller clk at 230~350 */ ++ printf("DDR: DDR controller freq is more than " ++ "max data rate of the module\n"); ++ return 0; ++ } else if (ddrc_clk <= 230 && ddrc_clk > 90) { ++ /* DDR controller clk at 90~230 */ ++ effective_data_rate = 200; /* 10ns */ ++ caslat = caslat; ++ } + } + ++ debug("DDR:Effective data rate is: %dMhz\n", effective_data_rate); ++ debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat); ++ ++ /* ++ * Errata DDR6 work around: input enable 2 cycles earlier. ++ * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2. ++ */ ++ if (caslat == 2) ++ ddr->debug_reg = 0x201c0000; /* CL=2 */ ++ else if (caslat == 3) ++ ddr->debug_reg = 0x202c0000; /* CL=2.5 */ ++ else if (caslat == 4) ++ ddr->debug_reg = 0x202c0000; /* CL=3.0 */ ++ ++ __asm__ __volatile__ ("sync"); ++ ++ debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg); ++ + /* + * note: caslat must also be programmed into ddr->sdram_mode + * register. +@@ -229,16 +348,14 @@ long int spd_sdram() + * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD, + * use conservative value here. + */ +- trfc = spd.trfc * 1000; /* up to ps */ +- trfc_clk = picos_to_clk(trfc); +- trfc_low = (trfc_clk - 8) & 0xf; ++ caslat_ctrl = (caslat + 1) & 0x07; /* see as above */ + + ddr->timing_cfg_1 = + (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | + ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | + ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) | +- ((caslat & 0x07) << 16 ) | +- (trfc_low << 12 ) | ++ ((caslat_ctrl & 0x07) << 16 ) | ++ (((picos_to_clk(spd.trfc * 1000) - 8) & 0x0f) << 12 ) | + ( 0x300 ) | + ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1); + +@@ -246,144 +363,143 @@ long int spd_sdram() + + debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1); + debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2); ++ /* Setup init value, but not enable */ ++ ddr->sdram_cfg = 0x42000000; + +- /* +- * Only DDR I is supported +- * DDR I and II have different mode-register-set definition +- */ +- switch(caslat) { +- case 2: +- tmp = 0x50; /* 1.5 */ +- break; +- case 3: +- tmp = 0x20; /* 2.0 */ +- break; +- case 4: +- tmp = 0x60; /* 2.5 */ +- break; +- case 5: +- tmp = 0x30; /* 3.0 */ +- break; +- default: +- puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n"); +- return 0; ++ /* Check DIMM data bus width */ ++ if (spd.dataw_lsb == 0x20) { ++ burstlen = 0x03; /* 32 bit data bus, burst len is 8 */ ++ printf("\n DDR DIMM: data bus width is 32 bit"); ++ } else { ++ burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */ ++ printf("\n DDR DIMM: data bus width is 64 bit"); ++ } ++ ++ /* Is this an ECC DDR chip? */ ++ if (spd.config == 0x02) ++ printf(" with ECC\n"); ++ else ++ printf(" without ECC\n"); ++ ++ /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus, ++ Burst type is sequential ++ */ ++ switch (caslat) { ++ case 1: ++ ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */ ++ break; ++ case 2: ++ ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */ ++ break; ++ case 3: ++ ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */ ++ break; ++ case 4: ++ ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */ ++ break; ++ default: ++ printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n"); ++ return 0; + } +-#if defined (CONFIG_DDR_32BIT) +- /* set burst length to 8 for 32-bit data path */ +- tmp |= 0x03; +-#else +- /* set burst length to 4 - default for 64-bit data path */ +- tmp |= 0x02; +-#endif +- ddr->sdram_mode = tmp; + debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode); + +- switch(spd.refresh) { +- case 0x00: +- case 0x80: +- tmp = picos_to_clk(15625000); +- break; +- case 0x01: +- case 0x81: +- tmp = picos_to_clk(3900000); +- break; +- case 0x02: +- case 0x82: +- tmp = picos_to_clk(7800000); +- break; +- case 0x03: +- case 0x83: +- tmp = picos_to_clk(31300000); +- break; +- case 0x04: +- case 0x84: +- tmp = picos_to_clk(62500000); +- break; +- case 0x05: +- case 0x85: +- tmp = picos_to_clk(125000000); +- break; +- default: +- tmp = 0x512; +- break; ++ switch (spd.refresh) { ++ case 0x00: ++ case 0x80: ++ refresh_clk = picos_to_clk(15625000); ++ break; ++ case 0x01: ++ case 0x81: ++ refresh_clk = picos_to_clk(3900000); ++ break; ++ case 0x02: ++ case 0x82: ++ refresh_clk = picos_to_clk(7800000); ++ break; ++ case 0x03: ++ case 0x83: ++ refresh_clk = picos_to_clk(31300000); ++ break; ++ case 0x04: ++ case 0x84: ++ refresh_clk = picos_to_clk(62500000); ++ break; ++ case 0x05: ++ case 0x85: ++ refresh_clk = picos_to_clk(125000000); ++ break; ++ default: ++ refresh_clk = 0x512; ++ break; + } + + /* + * Set BSTOPRE to 0x100 for page mode + * If auto-charge is used, set BSTOPRE = 0 + */ +- ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100; ++ ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100; + debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval); + +- /* +- * Is this an ECC DDR chip? ++ /* SS_EN = 0, source synchronous disable ++ * CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd + */ +-#if defined(CONFIG_DDR_ECC) +- if (spd.config == 0x02) { +- /* disable error detection */ +- ddr->err_disable = ~ECC_ERROR_ENABLE; ++ ddr->sdram_clk_cntl = 0x00000000; ++ debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl); + +- /* set single bit error threshold to maximum value, +- * reset counter to zero */ +- ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) | +- (0 << ECC_ERROR_MAN_SBEC_SHIFT); +- } +- debug("DDR:err_disable=0x%08x\n", ddr->err_disable); +- debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe); +-#endif + asm("sync;isync"); + +- udelay(500); ++ udelay(600); + + /* +- * SS_EN=1, +- * CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM +- * clock cycle after address/command +- */ +- /*ddr->sdram_clk_cntl = 0x82000000;*/ +- ddr->sdram_clk_cntl = (DDR_SDRAM_CLK_CNTL_SS_EN|DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05); +- +- /* +- * Figure out the settings for the sdram_cfg register. Build up +- * the entire register in 'tmp' before writing since the write into ++ * Figure out the settings for the sdram_cfg register. Build up ++ * the value in 'sdram_cfg' before writing since the write into + * the register will actually enable the memory controller, and all + * settings must be done before enabling. + * + * sdram_cfg[0] = 1 (ddr sdram logic enable) + * sdram_cfg[1] = 1 (self-refresh-enable) + * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM) ++ * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode) ++ * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts) + */ +- tmp = 0xc2000000; ++ sdram_cfg = 0xC2000000; + +-#if defined (CONFIG_DDR_32BIT) +- /* in 32-Bit mode burst len is 8 beats */ +- tmp |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); +-#endif +- /* +- * sdram_cfg[3] = RD_EN - registered DIMM enable +- * A value of 0x26 indicates micron registered DIMMS (micron.com) +- */ +- if (spd.mod_attr == 0x26) { +- tmp |= 0x10000000; +- } ++ /* sdram_cfg[3] = RD_EN - registered DIMM enable */ ++ if (spd.mod_attr & 0x02) ++ sdram_cfg |= 0x10000000; ++ ++ /* The DIMM is 32bit width */ ++ if (spd.dataw_lsb == 0x20) ++ sdram_cfg |= 0x000C0000; ++ ++ ddrc_ecc_enable = 0; + + #if defined(CONFIG_DDR_ECC) +- /* +- * If the user wanted ECC (enabled via sdram_cfg[2]) +- */ ++ /* Enable ECC with sdram_cfg[2] */ + if (spd.config == 0x02) { +- tmp |= SDRAM_CFG_ECC_EN; ++ sdram_cfg |= 0x20000000; ++ ddrc_ecc_enable = 1; ++ /* disable error detection */ ++ ddr->err_disable = ~ECC_ERROR_ENABLE; ++ /* set single bit error threshold to maximum value, ++ * reset counter to zero */ ++ ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) | ++ (0 << ECC_ERROR_MAN_SBEC_SHIFT); + } ++ ++ debug("DDR:err_disable=0x%08x\n", ddr->err_disable); ++ debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe); + #endif ++ printf(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF"); + + #if defined(CONFIG_DDR_2T_TIMING) + /* + * Enable 2T timing by setting sdram_cfg[16]. + */ +- tmp |= SDRAM_CFG_2T_EN; ++ sdram_cfg |= SDRAM_CFG_2T_EN; + #endif +- +- ddr->sdram_cfg = tmp; ++ /* Enable controller, and GO! */ ++ ddr->sdram_cfg = sdram_cfg; + asm("sync;isync"); + udelay(500); + +@@ -392,8 +508,7 @@ long int spd_sdram() + } + #endif /* CONFIG_SPD_EEPROM */ + +- +-#if defined(CONFIG_DDR_ECC) ++#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) + /* + * Use timebase counter, get_timer() is not availabe + * at this point of initialization yet. +@@ -429,74 +544,48 @@ static __inline__ unsigned long get_tbms + /* #define CONFIG_DDR_ECC_INIT_VIA_DMA */ + void ddr_enable_ecc(unsigned int dram_size) + { +- uint *p; +- volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; +- volatile ddr8349_t *ddr = &immap->ddr; ++ volatile immap_t *immap = (immap_t *)CFG_IMMR; ++ volatile ddr83xx_t *ddr= &immap->ddr; + unsigned long t_start, t_end; ++ register u64 *p; ++ register uint size; ++ unsigned int pattern[2]; + #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA) + uint i; + #endif +- +- debug("Initialize a Cachline in DRAM\n"); + icache_enable(); +- +-#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA) +- /* Initialise DMA for direct Transfers */ +- dma_init(); +-#endif +- + t_start = get_tbms(); ++ pattern[0] = 0xdeadbeef; ++ pattern[1] = 0xdeadbeef; + + #if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA) +- debug("DDR init: Cache flush method\n"); +- for (p = 0; p < (uint *)(dram_size); p++) { +- if (((unsigned int)p & 0x1f) == 0) { +- ppcDcbz((unsigned long) p); +- } +- +- /* write pattern to cache and flush */ +- *p = (unsigned int)0xdeadbeef; +- +- if (((unsigned int)p & 0x1c) == 0x1c) { +- ppcDcbf((unsigned long) p); +- } ++ debug("ddr init: CPU FP write method\n"); ++ size = dram_size; ++ for (p = 0; p < (u64*)(size); p++) { ++ ppcDWstore((u32*)p, pattern); + } ++ __asm__ __volatile__ ("sync"); + #else +- printf("DDR init: DMA method\n"); +- for (p = 0; p < (uint *)(8 * 1024); p++) { +- /* zero one data cache line */ +- if (((unsigned int)p & 0x1f) == 0) { +- ppcDcbz((unsigned long)p); +- } +- +- /* write pattern to it and flush */ +- *p = (unsigned int)0xdeadbeef; +- +- if (((unsigned int)p & 0x1c) == 0x1c) { +- ppcDcbf((unsigned long)p); +- } ++ debug("ddr init: DMA method\n"); ++ size = 0x2000; ++ for (p = 0; p < (u64*)(size); p++) { ++ ppcDWstore((u32*)p, pattern); + } ++ __asm__ __volatile__ ("sync"); + +- /* 8K */ +- dma_xfer((uint *)0x2000, 0x2000, (uint *)0); +- /* 16K */ +- dma_xfer((uint *)0x4000, 0x4000, (uint *)0); +- /* 32K */ +- dma_xfer((uint *)0x8000, 0x8000, (uint *)0); +- /* 64K */ +- dma_xfer((uint *)0x10000, 0x10000, (uint *)0); +- /* 128k */ +- dma_xfer((uint *)0x20000, 0x20000, (uint *)0); +- /* 256k */ +- dma_xfer((uint *)0x40000, 0x40000, (uint *)0); +- /* 512k */ +- dma_xfer((uint *)0x80000, 0x80000, (uint *)0); +- /* 1M */ +- dma_xfer((uint *)0x100000, 0x100000, (uint *)0); +- /* 2M */ +- dma_xfer((uint *)0x200000, 0x200000, (uint *)0); +- /* 4M */ +- dma_xfer((uint *)0x400000, 0x400000, (uint *)0); ++ /* Initialise DMA for direct transfer */ ++ dma_init(); ++ /* Start DMA to transfer */ ++ dma_xfer((uint *)0x2000, 0x2000, (uint *)0); /* 8K */ ++ dma_xfer((uint *)0x4000, 0x4000, (uint *)0); /* 16K */ ++ dma_xfer((uint *)0x8000, 0x8000, (uint *)0); /* 32K */ ++ dma_xfer((uint *)0x10000, 0x10000, (uint *)0); /* 64K */ ++ dma_xfer((uint *)0x20000, 0x20000, (uint *)0); /* 128K */ ++ dma_xfer((uint *)0x40000, 0x40000, (uint *)0); /* 256K */ ++ dma_xfer((uint *)0x80000, 0x80000, (uint *)0); /* 512K */ ++ dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */ ++ dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */ ++ dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */ + + for (i = 1; i < dram_size / 0x800000; i++) { + dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0); +diff -Naupr u-boot-1.1.6/cpu/mpc83xx/speed.c u-boot-1.1.6-fsl-1/cpu/mpc83xx/speed.c +--- u-boot-1.1.6/cpu/mpc83xx/speed.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/cpu/mpc83xx/speed.c 2006-11-30 12:34:13.000000000 -0600 +@@ -2,7 +2,7 @@ + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * +- * Copyright 2004 Freescale Semiconductor, Inc. ++ * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. +@@ -21,11 +21,6 @@ + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA +- * +- * Change log: +- * +- * 20050101: Eran Liberty (liberty@freescale.com) +- * Initial file creating (porting from 85XX & 8260) + */ + + #include +@@ -53,38 +48,38 @@ typedef enum { + + typedef struct { + mult_t core_csb_ratio; +- mult_t vco_divider; ++ mult_t vco_divider; + } corecnf_t; + + corecnf_t corecnf_tab[] = { +- { _byp, _byp}, /* 0x00 */ +- { _byp, _byp}, /* 0x01 */ +- { _byp, _byp}, /* 0x02 */ +- { _byp, _byp}, /* 0x03 */ +- { _byp, _byp}, /* 0x04 */ +- { _byp, _byp}, /* 0x05 */ +- { _byp, _byp}, /* 0x06 */ +- { _byp, _byp}, /* 0x07 */ +- { _1x, _x2}, /* 0x08 */ +- { _1x, _x4}, /* 0x09 */ +- { _1x, _x8}, /* 0x0A */ +- { _1x, _x8}, /* 0x0B */ +- {_1_5x, _x2}, /* 0x0C */ +- {_1_5x, _x4}, /* 0x0D */ +- {_1_5x, _x8}, /* 0x0E */ +- {_1_5x, _x8}, /* 0x0F */ +- { _2x, _x2}, /* 0x10 */ +- { _2x, _x4}, /* 0x11 */ +- { _2x, _x8}, /* 0x12 */ +- { _2x, _x8}, /* 0x13 */ +- {_2_5x, _x2}, /* 0x14 */ +- {_2_5x, _x4}, /* 0x15 */ +- {_2_5x, _x8}, /* 0x16 */ +- {_2_5x, _x8}, /* 0x17 */ +- { _3x, _x2}, /* 0x18 */ +- { _3x, _x4}, /* 0x19 */ +- { _3x, _x8}, /* 0x1A */ +- { _3x, _x8}, /* 0x1B */ ++ {_byp, _byp}, /* 0x00 */ ++ {_byp, _byp}, /* 0x01 */ ++ {_byp, _byp}, /* 0x02 */ ++ {_byp, _byp}, /* 0x03 */ ++ {_byp, _byp}, /* 0x04 */ ++ {_byp, _byp}, /* 0x05 */ ++ {_byp, _byp}, /* 0x06 */ ++ {_byp, _byp}, /* 0x07 */ ++ {_1x, _x2}, /* 0x08 */ ++ {_1x, _x4}, /* 0x09 */ ++ {_1x, _x8}, /* 0x0A */ ++ {_1x, _x8}, /* 0x0B */ ++ {_1_5x, _x2}, /* 0x0C */ ++ {_1_5x, _x4}, /* 0x0D */ ++ {_1_5x, _x8}, /* 0x0E */ ++ {_1_5x, _x8}, /* 0x0F */ ++ {_2x, _x2}, /* 0x10 */ ++ {_2x, _x4}, /* 0x11 */ ++ {_2x, _x8}, /* 0x12 */ ++ {_2x, _x8}, /* 0x13 */ ++ {_2_5x, _x2}, /* 0x14 */ ++ {_2_5x, _x4}, /* 0x15 */ ++ {_2_5x, _x8}, /* 0x16 */ ++ {_2_5x, _x8}, /* 0x17 */ ++ {_3x, _x2}, /* 0x18 */ ++ {_3x, _x4}, /* 0x19 */ ++ {_3x, _x8}, /* 0x1A */ ++ {_3x, _x8}, /* 0x1B */ + }; + + /* ----------------------------------------------------------------- */ +@@ -92,91 +87,64 @@ corecnf_t corecnf_tab[] = { + /* + * + */ +-int get_clocks (void) ++int get_clocks(void) + { +- volatile immap_t *im = (immap_t *)CFG_IMMRBAR; ++ volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 pci_sync_in; +- u8 spmf; +- u8 clkin_div; ++ u8 spmf; ++ u8 clkin_div; + u32 sccr; + u32 corecnf_tab_index; +- u8 corepll; ++ u8 corepll; + u32 lcrr; + + u32 csb_clk; ++#if defined(CONFIG_MPC8349) + u32 tsec1_clk; + u32 tsec2_clk; +- u32 core_clk; + u32 usbmph_clk; + u32 usbdr_clk; +- u32 i2c_clk; ++#endif ++ u32 core_clk; ++ u32 i2c1_clk; ++ u32 i2c2_clk; + u32 enc_clk; + u32 lbiu_clk; + u32 lclk_clk; + u32 ddr_clk; ++#if defined (CONFIG_MPC8360) ++ u32 qepmf; ++ u32 qepdf; ++ u32 ddr_sec_clk; ++ u32 qe_clk; ++ u32 brg_clk; ++#endif + +- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) ++ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + +-#ifndef CFG_HRCW_HIGH +-# error "CFG_HRCW_HIGH must be defined in board config file" +-#endif /* CFG_HCWD_HIGH */ +- +-#if (CFG_HRCW_HIGH & HRCWH_PCI_HOST) +- +-# ifndef CONFIG_83XX_CLKIN +-# error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in board config file" +-# endif /* CONFIG_83XX_CLKIN */ +-# ifdef CONFIG_83XX_PCICLK +-# warning "In PCI Host Mode, CONFIG_83XX_PCICLK in board config file is igonred" +-# endif /* CONFIG_83XX_PCICLK */ +- +- /* PCI Host Mode */ +- if (!(im->reset.rcwh & RCWH_PCIHOST)) { +- /* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH +- * the im->reset.rcwhr PCI Host Mode is disabled +- * FIXME: findout if there is a way to issue some warning */ +- return -2; +- } +- if (im->clk.spmr & SPMR_CKID) { +- /* PCI Clock is half CONFIG_83XX_CLKIN */ +- pci_sync_in = CONFIG_83XX_CLKIN / 2; +- } +- else { +- pci_sync_in = CONFIG_83XX_CLKIN; +- } +- +-#else /* (CFG_HRCW_HIGH & HRCWH_PCI_HOST) */ ++ clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT); + +-# ifdef CONFIG_83XX_CLKIN +-# warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in board config file is igonred" +-# endif /* CONFIG_83XX_CLKIN */ +-# ifndef CONFIG_83XX_PCICLK +-# error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in board config file" +-# endif /* CONFIG_83XX_PCICLK */ +- +- /* PCI Agent Mode */ +- if (im->reset.rcwh & RCWH_PCIHOST) { +- /* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH +- * the im->reset.rcwhr PCI Host Mode is enabled */ +- return -3; ++ if (im->reset.rcwh & HRCWH_PCI_HOST) { ++#if defined(CONFIG_83XX_CLKIN) ++ pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div); ++#else ++ pci_sync_in = 0xDEADBEEF; ++#endif ++ } else { ++#if defined(CONFIG_83XX_PCICLK) ++ pci_sync_in = CONFIG_83XX_PCICLK; ++#else ++ pci_sync_in = 0xDEADBEEF; ++#endif + } +- pci_sync_in = CONFIG_83XX_PCICLK; + +-#endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */ +- +- /* we have up to date pci_sync_in */ + spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT); +- clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT); +- +- if ((im->reset.rcwl & RCWL_LBIUCM) || (im->reset.rcwl & RCWL_DDRCM)) { +- csb_clk = (pci_sync_in * spmf * (1 + clkin_div)) / 2; +- } +- else { +- csb_clk = pci_sync_in * spmf * (1 + clkin_div); +- } ++ csb_clk = pci_sync_in * (1 + clkin_div) * spmf; + + sccr = im->clk.sccr; ++ ++#if defined(CONFIG_MPC8349) + switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { + case 0: + tsec1_clk = 0; +@@ -212,25 +180,8 @@ int get_clocks (void) + /* unkown SCCR_TSEC2CM value */ + return -5; + } +- i2c_clk = tsec2_clk; + +- switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { +- case 0: +- enc_clk = 0; +- break; +- case 1: +- enc_clk = csb_clk; +- break; +- case 2: +- enc_clk = csb_clk / 2; +- break; +- case 3: +- enc_clk = csb_clk / 3; +- break; +- default: +- /* unkown SCCR_ENCCM value */ +- return -6; +- } ++ i2c1_clk = tsec2_clk; + + switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) { + case 0: +@@ -268,14 +219,42 @@ int get_clocks (void) + return -8; + } + +- if (usbmph_clk != 0 +- && usbdr_clk != 0 +- && usbmph_clk != usbdr_clk ) { +- /* if USB MPH clock is not disabled and USB DR clock is not disabled than USB MPH & USB DR must have the same rate */ ++ if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) { ++ /* if USB MPH clock is not disabled and ++ * USB DR clock is not disabled then ++ * USB MPH & USB DR must have the same rate ++ */ + return -9; + } ++#endif ++#if defined (CONFIG_MPC8360) ++ i2c1_clk = csb_clk; ++#endif ++ i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ + +- lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT)); ++ switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { ++ case 0: ++ enc_clk = 0; ++ break; ++ case 1: ++ enc_clk = csb_clk; ++ break; ++ case 2: ++ enc_clk = csb_clk / 2; ++ break; ++ case 3: ++ enc_clk = csb_clk / 3; ++ break; ++ default: ++ /* unkown SCCR_ENCCM value */ ++ return -6; ++ } ++#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360) ++ lbiu_clk = csb_clk * ++ (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT)); ++#else ++#error Unknown MPC83xx chip ++#endif + lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT; + switch (lcrr) { + case 2: +@@ -287,12 +266,20 @@ int get_clocks (void) + /* unknown lcrr */ + return -10; + } +- +- ddr_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT)); +- ++#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360) ++ ddr_clk = csb_clk * ++ (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT)); + corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT; ++#if defined (CONFIG_MPC8360) ++ ddr_sec_clk = csb_clk * (1 + ++ ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT)); ++#endif ++#else ++#error Unknown MPC83xx chip ++#endif ++ + corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5); +- if (corecnf_tab_index > (sizeof(corecnf_tab)/sizeof(corecnf_t)) ) { ++ if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) { + /* corecnf_tab_index is too high, possibly worng value */ + return -11; + } +@@ -309,7 +296,7 @@ int get_clocks (void) + core_clk = 2 * csb_clk; + break; + case _2_5x: +- core_clk = ( 5 * csb_clk) / 2; ++ core_clk = (5 * csb_clk) / 2; + break; + case _3x: + core_clk = 3 * csb_clk; +@@ -319,46 +306,69 @@ int get_clocks (void) + return -12; + } + +- gd->csb_clk = csb_clk ; +- gd->tsec1_clk = tsec1_clk ; +- gd->tsec2_clk = tsec2_clk ; +- gd->core_clk = core_clk ; ++#if defined (CONFIG_MPC8360) ++ qepmf = (im->reset.rcwl & RCWL_CEPMF) >> RCWL_CEPMF_SHIFT; ++ qepdf = (im->reset.rcwl & RCWL_CEPDF) >> RCWL_CEPDF_SHIFT; ++ qe_clk = (pci_sync_in * qepmf) / (1 + qepdf); ++ brg_clk = qe_clk / 2; ++#endif ++ ++ gd->csb_clk = csb_clk; ++#if defined(CONFIG_MPC8349) ++ gd->tsec1_clk = tsec1_clk; ++ gd->tsec2_clk = tsec2_clk; + gd->usbmph_clk = usbmph_clk; +- gd->usbdr_clk = usbdr_clk ; +- gd->i2c_clk = i2c_clk ; +- gd->enc_clk = enc_clk ; +- gd->lbiu_clk = lbiu_clk ; +- gd->lclk_clk = lclk_clk ; +- gd->ddr_clk = ddr_clk ; +- gd->pci_clk = pci_sync_in; +- ++ gd->usbdr_clk = usbdr_clk; ++#endif ++ gd->core_clk = core_clk; ++ gd->i2c1_clk = i2c1_clk; ++ gd->i2c2_clk = i2c2_clk; ++ gd->enc_clk = enc_clk; ++ gd->lbiu_clk = lbiu_clk; ++ gd->lclk_clk = lclk_clk; ++ gd->ddr_clk = ddr_clk; ++#if defined (CONFIG_MPC8360) ++ gd->ddr_sec_clk = ddr_sec_clk; ++ gd->qe_clk = qe_clk; ++ gd->brg_clk = brg_clk; ++#endif + gd->cpu_clk = gd->core_clk; +- gd->bus_clk = gd->lbiu_clk; ++ gd->bus_clk = gd->csb_clk; + return 0; ++ + } + + /******************************************** + * get_bus_freq + * return system bus freq in Hz + *********************************************/ +-ulong get_bus_freq (ulong dummy) ++ulong get_bus_freq(ulong dummy) + { + return gd->csb_clk; + } + +-int print_clock_conf (void) ++int print_clock_conf(void) + { + printf("Clock configuration:\n"); +- printf(" Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000); +- printf(" Core: %4d MHz\n",gd->core_clk/1000000); +- debug(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000); +- printf(" Local Bus: %4d MHz\n",gd->lclk_clk/1000000); +- debug(" DDR: %4d MHz\n",gd->ddr_clk/1000000); +- debug(" I2C: %4d MHz\n",gd->i2c_clk/1000000); +- debug(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000); +- debug(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000); +- debug(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000); +- debug(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000); +- ++ printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000); ++ printf(" Core: %4d MHz\n", gd->core_clk / 1000000); ++#if defined (CONFIG_MPC8360) ++ printf(" QE: %4d MHz\n", gd->qe_clk / 1000000); ++#endif ++ printf(" Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000); ++ printf(" Local Bus: %4d MHz\n", gd->lclk_clk / 1000000); ++ printf(" DDR: %4d MHz\n", gd->ddr_clk / 1000000); ++#if defined (CONFIG_MPC8360) ++ printf(" DDR Secondary: %4d MHz\n", gd->ddr_sec_clk / 1000000); ++#endif ++ printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000); ++ printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000); ++ printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000); ++#if defined(CONFIG_MPC8349) ++ printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000); ++ printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000); ++ printf(" USB MPH: %4d MHz\n", gd->usbmph_clk / 1000000); ++ printf(" USB DR: %4d MHz\n", gd->usbdr_clk / 1000000); ++#endif + return 0; + } +diff -Naupr u-boot-1.1.6/cpu/mpc83xx/start.S u-boot-1.1.6-fsl-1/cpu/mpc83xx/start.S +--- u-boot-1.1.6/cpu/mpc83xx/start.S 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/cpu/mpc83xx/start.S 2006-11-10 11:24:29.000000000 -0600 +@@ -2,7 +2,7 @@ + * Copyright (C) 1998 Dan Malek + * Copyright (C) 1999 Magnus Damm + * Copyright (C) 2000, 2001,2002 Wolfgang Denk +- * Copyright 2004 Freescale Semiconductor, Inc. ++ * Copyright Freescale Semiconductor, Inc. 2004, 2006. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. +@@ -104,9 +104,9 @@ version_string: + #ifndef CONFIG_DEFAULT_IMMR + #error CONFIG_DEFAULT_IMMR must be defined + #endif /* CFG_DEFAULT_IMMR */ +-#ifndef CFG_IMMRBAR +-#define CFG_IMMRBAR CONFIG_DEFAULT_IMMR +-#endif /* CFG_IMMRBAR */ ++#ifndef CFG_IMMR ++#define CFG_IMMR CONFIG_DEFAULT_IMMR ++#endif /* CFG_IMMR */ + + /* + * After configuration, a system reset exception is executed using the +@@ -152,8 +152,8 @@ boot_cold: /* time t 3 */ + nop + boot_warm: /* time t 5 */ + mfmsr r5 /* save msr contents */ +- lis r3, CFG_IMMRBAR@h +- ori r3, r3, CFG_IMMRBAR@l ++ lis r3, CFG_IMMR@h ++ ori r3, r3, CFG_IMMR@l + stw r3, IMMRBAR(r4) + + /* Initialise the E300 processor core */ +@@ -226,7 +226,7 @@ in_flash: + GET_GOT /* initialize GOT access */ + + /* r3: IMMR */ +- lis r3, CFG_IMMRBAR@h ++ lis r3, CFG_IMMR@h + /* run low-level CPU init code (in Flash)*/ + bl cpu_init_f + +@@ -446,7 +446,7 @@ init_e300_core: /* time t 10 */ + mtspr SRR1, r3 /* Make SRR1 match MSR */ + + +- lis r3, CFG_IMMRBAR@h ++ lis r3, CFG_IMMR@h + #if defined(CONFIG_WATCHDOG) + /* Initialise the Wathcdog values and reset it (if req) */ + /*------------------------------------------------------*/ +@@ -870,6 +870,18 @@ ppcDcbz: + dcbz r0,r3 + blr + ++ .globl ppcDWstore ++ppcDWstore: ++ lfd 1, 0(r4) ++ stfd 1, 0(r3) ++ blr ++ ++ .globl ppcDWload ++ppcDWload: ++ lfd 1, 0(r3) ++ stfd 1, 0(r4) ++ blr ++ + /*-------------------------------------------------------------------*/ + + /* +@@ -1189,7 +1201,7 @@ map_flash_by_law1: + /* When booting from ROM (Flash or EPROM), clear the */ + /* Address Mask in OR0 so ROM appears everywhere */ + /*----------------------------------------------------*/ +- lis r3, (CFG_IMMRBAR)@h /* r3 <= CFG_IMMRBAR */ ++ lis r3, (CFG_IMMR)@h /* r3 <= CFG_IMMR */ + lwz r4, OR0@l(r3) + li r5, 0x7fff /* r5 <= 0x00007FFFF */ + and r4, r4, r5 +@@ -1214,8 +1226,15 @@ map_flash_by_law1: + lis r4, (CFG_FLASH_BASE)@h + ori r4, r4, (CFG_FLASH_BASE)@l + stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_FLASH_BASE */ +- lis r4, (0x80000016)@h +- ori r4, r4, (0x80000016)@l ++ ++ /* Store 0x80000012 + log2(CFG_FLASH_SIZE) into LBLAWAR1 */ ++ lis r4, (0x80000012)@h ++ ori r4, r4, (0x80000012)@l ++ li r5, CFG_FLASH_SIZE ++1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ ++ addi r4, r4, 1 ++ bne 1b ++ + stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ + blr + +@@ -1234,17 +1253,23 @@ remap_flash_by_law0: + stw r5, BR0(r3) /* r5 <= (CFG_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ + + lwz r4, OR0(r3) +- lis r5, 0xFF80 /* 8M */ ++ lis r5, ~((CFG_FLASH_SIZE << 4) - 1) + or r4, r4, r5 +- stw r4, OR0(r3) /* OR0 <= OR0 | 0xFF800000 */ ++ stw r4, OR0(r3) + + lis r4, (CFG_FLASH_BASE)@h + ori r4, r4, (CFG_FLASH_BASE)@l + stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_FLASH_BASE */ + +- lis r4, (0x80000016)@h +- ori r4, r4, (0x80000016)@l +- stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= 8MB Flash Size */ ++ /* Store 0x80000012 + log2(CFG_FLASH_SIZE) into LBLAWAR0 */ ++ lis r4, (0x80000012)@h ++ ori r4, r4, (0x80000012)@l ++ li r5, CFG_FLASH_SIZE ++1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ ++ addi r4, r4, 1 ++ bne 1b ++ stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */ ++ + + xor r4, r4, r4 + stw r4, LBLAWBAR1(r3) +diff -Naupr u-boot-1.1.6/cpu/mpc83xx/traps.c u-boot-1.1.6-fsl-1/cpu/mpc83xx/traps.c +--- u-boot-1.1.6/cpu/mpc83xx/traps.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/cpu/mpc83xx/traps.c 2006-11-30 12:34:13.000000000 -0600 +@@ -1,5 +1,8 @@ + /* +- * linux/arch/ppc/kernel/traps.c ++ * (C) Copyright 2000 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as +@@ -15,19 +18,6 @@ + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA +- * +- * Change log: +- * +- * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) +- * +- * Modified by Cort Dougan (cort@cs.nmt.edu) +- * and Paul Mackerras (paulus@cs.anu.edu.au) +- * +- * (C) Copyright 2000 +- * Wolfgang Denk, DENX Software Engineering, wd@denx.de. +- * +- * 20050101: Eran Liberty (liberty@freescale.com) +- * Initial file creating (porting from 85XX & 8260) + */ + + /* +diff -Naupr u-boot-1.1.6/cpu/ppc4xx/405gp_pci.c u-boot-1.1.6-fsl-1/cpu/ppc4xx/405gp_pci.c +--- u-boot-1.1.6/cpu/ppc4xx/405gp_pci.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/cpu/ppc4xx/405gp_pci.c 2006-11-30 12:34:13.000000000 -0600 +@@ -475,7 +475,11 @@ void pci_440_init (struct pci_controller + pci_set_region(hose->regions + reg_num++, + CFG_PCI_TARGBASE, + CFG_PCI_MEMBASE, ++#ifdef CFG_PCI_MEMSIZE ++ CFG_PCI_MEMSIZE, ++#else + 0x10000000, ++#endif + PCI_REGION_MEM ); + + #if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \ +diff -Naupr u-boot-1.1.6/cpu/ppc4xx/4xx_enet.c u-boot-1.1.6-fsl-1/cpu/ppc4xx/4xx_enet.c +--- u-boot-1.1.6/cpu/ppc4xx/4xx_enet.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/cpu/ppc4xx/4xx_enet.c 2006-11-30 12:34:13.000000000 -0600 +@@ -264,10 +264,10 @@ int ppc_4xx_eth_setup_bridge(int devnum, + bis->bi_phymode[3] = BI_PHYMODE_ZMII; + break; + case 2: +- zmiifer = ZMII_FER_SMII << ZMII_FER_V(0); +- zmiifer = ZMII_FER_SMII << ZMII_FER_V(1); +- zmiifer = ZMII_FER_SMII << ZMII_FER_V(2); +- zmiifer = ZMII_FER_SMII << ZMII_FER_V(3); ++ zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); ++ zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); ++ zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2); ++ zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3); + bis->bi_phymode[0] = BI_PHYMODE_ZMII; + bis->bi_phymode[1] = BI_PHYMODE_ZMII; + bis->bi_phymode[2] = BI_PHYMODE_ZMII; +@@ -470,8 +470,7 @@ static int ppc_4xx_eth_init (struct eth_ + #else + if ((devnum == 0) || (devnum == 1)) { + out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); +- } +- else { /* ((devnum == 2) || (devnum == 3)) */ ++ } else { /* ((devnum == 2) || (devnum == 3)) */ + out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum)); + out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) | + (RGMII_FER_RGMII << RGMII_FER_V (3)))); +@@ -561,22 +560,7 @@ static int ppc_4xx_eth_init (struct eth_ + * otherwise, just check the speeds & feeds + */ + if (hw_p->first_init == 0) { +-#if defined(CONFIG_88E1111_CLK_DELAY) +- /* +- * On some boards (e.g. ALPR) the Marvell 88E1111 PHY needs +- * the "RGMII transmit timing control" and "RGMII receive +- * timing control" bits set, so that Gbit communication works +- * without problems. +- * Also set the "Transmitter disable" to 1 to enable the +- * transmitter. +- * After setting these bits a soft-reset must occur for this +- * change to become active. +- */ +- miiphy_read (dev->name, reg, 0x14, ®_short); +- reg_short |= (1 << 7) | (1 << 1) | (1 << 0); +- miiphy_write (dev->name, reg, 0x14, reg_short); +-#endif +-#if defined(CONFIG_M88E1111_PHY) /* test-only: merge with CONFIG_88E1111_CLK_DELAY !!! */ ++#if defined(CONFIG_M88E1111_PHY) + miiphy_write (dev->name, reg, 0x14, 0x0ce3); + miiphy_write (dev->name, reg, 0x18, 0x4101); + miiphy_write (dev->name, reg, 0x09, 0x0e00); +@@ -808,7 +792,7 @@ static int ppc_4xx_eth_init (struct eth_ + hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR; + hw_p->rx_ready[i] = -1; + #if 0 +- printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr); ++ printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) hw_p->rx[i].data_ptr); + #endif + } + +diff -Naupr u-boot-1.1.6/cpu/ppc4xx/cpu.c u-boot-1.1.6-fsl-1/cpu/ppc4xx/cpu.c +--- u-boot-1.1.6/cpu/ppc4xx/cpu.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/cpu/ppc4xx/cpu.c 2006-12-06 10:33:49.000000000 -0600 +@@ -41,6 +41,10 @@ + DECLARE_GLOBAL_DATA_PTR; + #endif + ++#if defined(CONFIG_BOARD_RESET) ++void board_reset(void); ++#endif ++ + #if defined(CONFIG_440) + #define FREQ_EBC (sys_info.freqEPB) + #else +@@ -336,6 +340,10 @@ int checkcpu (void) + puts("SP Rev. B"); + break; + ++ case PVR_440SP_RC: ++ puts("SP Rev. C"); ++ break; ++ + case PVR_440SPe_RA: + puts("SPe Rev. A"); + break; +@@ -422,23 +430,19 @@ int ppc440spe_revB() { + + int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) + { +-#if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE) +- /*give reset to BCSR*/ +- *(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09; +- ++#if defined(CONFIG_BOARD_RESET) ++ board_reset(); ++#else ++#if defined(CFG_4xx_RESET_TYPE) ++ mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28); + #else +- + /* + * Initiate system reset in debug control register DBCR + */ +- __asm__ __volatile__("lis 3, 0x3000" ::: "r3"); +-#if defined(CONFIG_440) +- __asm__ __volatile__("mtspr 0x134, 3"); +-#else +- __asm__ __volatile__("mtspr 0x3f2, 3"); +-#endif ++ mtspr(dbcr0, 0x30000000); ++#endif /* defined(CFG_4xx_RESET_TYPE) */ ++#endif /* defined(CONFIG_BOARD_RESET) */ + +-#endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/ + return 1; + } + +diff -Naupr u-boot-1.1.6/cpu/ppc4xx/cpu_init.c u-boot-1.1.6-fsl-1/cpu/ppc4xx/cpu_init.c +--- u-boot-1.1.6/cpu/ppc4xx/cpu_init.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/cpu/ppc4xx/cpu_init.c 2006-11-30 12:34:13.000000000 -0600 +@@ -321,6 +321,10 @@ cpu_init_f (void) + #else + val |= 0xf0000000; /* generate system reset after 2.684 seconds */ + #endif ++#if defined(CFG_4xx_RESET_TYPE) ++ val &= ~0x30000000; /* clear WRC bits */ ++ val |= CFG_4xx_RESET_TYPE << 28; /* set board specific WRC type */ ++#endif + mtspr(tcr, val); + + val = mfspr(tsr); +diff -Naupr u-boot-1.1.6/cpu/ppc4xx/sdram.c u-boot-1.1.6-fsl-1/cpu/ppc4xx/sdram.c +--- u-boot-1.1.6/cpu/ppc4xx/sdram.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/cpu/ppc4xx/sdram.c 2006-11-30 12:34:13.000000000 -0600 +@@ -351,6 +351,14 @@ long int initdram(int board_type) + int i; + int tr1_bank1; + ++#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) ++ /* ++ * Soft-reset SDRAM controller. ++ */ ++ mtsdr(sdr_srst, SDR0_SRST_DMC); ++ mtsdr(sdr_srst, 0x00000000); ++#endif ++ + for (i=0; i ++ c ++ ] ++ ++ ++ Or via tftp: ++ ++ tftp 10000 u-boot.bin ++ ++5.1 Reflash U-boot Image using U-boot ++ ++ tftp 20000 u-boot.bin ++ protect off fef00000 fef3ffff ++ erase fef00000 fef3ffff ++ ++ cp.b 20000 fef00000 xxxx ++ ++ or ++ ++ cp.b 20000 fef00000 3ffff ++ ++ ++You have to supply the correct byte count with 'xxxx' from the TFTP result log. ++Maybe 3ffff will work too, that corresponds to the erased sectors. ++ ++ ++6. Notes ++ 1) The console baudrate for MPC8360EMDS is 115200bps. +diff -Naupr u-boot-1.1.6/drivers/cfi_flash.c u-boot-1.1.6-fsl-1/drivers/cfi_flash.c +--- u-boot-1.1.6/drivers/cfi_flash.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/drivers/cfi_flash.c 2006-11-30 12:34:13.000000000 -0600 +@@ -4,11 +4,12 @@ + * + * Copyright (C) 2003 Arabella Software Ltd. + * Yuli Barcohen +- * Modified to work with AMD flashes + * + * Copyright (C) 2004 + * Ed Okerson +- * Modified to work with little-endian systems. ++ * ++ * Copyright (C) 2006 ++ * Tolunay Orkun + * + * See file CREDITS for list of people who contributed to this + * project. +@@ -28,17 +29,6 @@ + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * +- * History +- * 01/20/2004 - combined variants of original driver. +- * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay) +- * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud) +- * 01/27/2004 - Little endian support Ed Okerson +- * +- * Tested Architectures +- * Port Width Chip Width # of banks Flash Chip Board +- * 32 16 1 28F128J3 seranoa/eagle +- * 64 16 1 28F128J3 seranoa/falcon +- * + */ + + /* The DEBUG define must be before common to enable debugging */ +@@ -54,21 +44,16 @@ + * This file implements a Common Flash Interface (CFI) driver for U-Boot. + * The width of the port and the width of the chips are determined at initialization. + * These widths are used to calculate the address for access CFI data structures. +- * It has been tested on an Intel Strataflash implementation and AMD 29F016D. + * + * References + * JEDEC Standard JESD68 - Common Flash Interface (CFI) + * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes + * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets + * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet ++ * AMD CFI Specification, Release 2.0 December 1, 2001 ++ * AMD/Spansion Application Note: Migration from Single-byte to Three-byte ++ * Device IDs, Publication Number 25538 Revision A, November 8, 2001 + * +- * TODO +- * +- * Use Primary Extended Query table (PRI) and Alternate Algorithm Query +- * Table (ALT) to determine if protection is available +- * +- * Add support for other command sets Use the PRI and ALT to determine command set +- * Verify erase and program timeouts. + */ + + #ifndef CFG_FLASH_BANKS_LIST +@@ -114,6 +99,10 @@ + #define AMD_ADDR_START ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555) + #define AMD_ADDR_ACK ((info->portwidth == FLASH_CFI_8BIT) ? 0x555 : 0x2AA) + ++#define FLASH_OFFSET_MANUFACTURER_ID 0x00 ++#define FLASH_OFFSET_DEVICE_ID 0x01 ++#define FLASH_OFFSET_DEVICE_ID2 0x0E ++#define FLASH_OFFSET_DEVICE_ID3 0x0F + #define FLASH_OFFSET_CFI 0x55 + #define FLASH_OFFSET_CFI_RESP 0x10 + #define FLASH_OFFSET_PRIMARY_VENDOR 0x13 +@@ -135,25 +124,20 @@ + #define FLASH_OFFSET_USER_PROTECTION 0x85 + #define FLASH_OFFSET_INTEL_PROTECTION 0x81 + +- +-#define FLASH_MAN_CFI 0x01000000 +- +-#define CFI_CMDSET_NONE 0 +-#define CFI_CMDSET_INTEL_EXTENDED 1 +-#define CFI_CMDSET_AMD_STANDARD 2 +-#define CFI_CMDSET_INTEL_STANDARD 3 +-#define CFI_CMDSET_AMD_EXTENDED 4 +-#define CFI_CMDSET_MITSU_STANDARD 256 +-#define CFI_CMDSET_MITSU_EXTENDED 257 +-#define CFI_CMDSET_SST 258 +- ++#define CFI_CMDSET_NONE 0 ++#define CFI_CMDSET_INTEL_EXTENDED 1 ++#define CFI_CMDSET_AMD_STANDARD 2 ++#define CFI_CMDSET_INTEL_STANDARD 3 ++#define CFI_CMDSET_AMD_EXTENDED 4 ++#define CFI_CMDSET_MITSU_STANDARD 256 ++#define CFI_CMDSET_MITSU_EXTENDED 257 ++#define CFI_CMDSET_SST 258 + + #ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ + # undef FLASH_CMD_RESET +-# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */ ++# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */ + #endif + +- + typedef union { + unsigned char c; + unsigned short w; +@@ -168,7 +152,7 @@ typedef union { + volatile unsigned long long *llp; + } cfiptr_t; + +-#define NUM_ERASE_REGIONS 4 ++#define NUM_ERASE_REGIONS 4 /* max. number of erase regions */ + + /* use CFG_MAX_FLASH_BANKS_DETECT if defined */ + #ifdef CFG_MAX_FLASH_BANKS_DETECT +@@ -200,6 +184,7 @@ static void flash_unlock_seq (flash_info + static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); + static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); + static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); ++static void flash_read_jedec_ids (flash_info_t * info); + static int flash_detect_cfi (flash_info_t * info); + static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword); + static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, +@@ -307,7 +292,7 @@ ushort flash_read_ushort (flash_info_t * + } + + /*----------------------------------------------------------------------- +- * read a long word by picking the least significant byte of each maiximum ++ * read a long word by picking the least significant byte of each maximum + * port size word. Swap for ppc format. + */ + ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset) +@@ -529,14 +514,42 @@ void flash_print_info (flash_info_t * in + (info->portwidth << 3), (info->chipwidth << 3)); + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); +- printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", ++ printf (" "); ++ switch (info->vendor) { ++ case CFI_CMDSET_INTEL_STANDARD: ++ printf ("Intel Standard"); ++ break; ++ case CFI_CMDSET_INTEL_EXTENDED: ++ printf ("Intel Extended"); ++ break; ++ case CFI_CMDSET_AMD_STANDARD: ++ printf ("AMD Standard"); ++ break; ++ case CFI_CMDSET_AMD_EXTENDED: ++ printf ("AMD Extended"); ++ break; ++ default: ++ printf ("Unknown (%d)", info->vendor); ++ break; ++ } ++ printf (" command set, Manufacturer ID: 0x%02X, Device ID: 0x%02X", ++ info->manufacturer_id, info->device_id); ++ if (info->device_id == 0x7E) { ++ printf("%04X", info->device_id2); ++ } ++ printf ("\n Erase timeout: %ld ms, write timeout: %ld ms\n", + info->erase_blk_tout, +- info->write_tout, ++ info->write_tout); ++ if (info->buffer_size > 1) { ++ printf (" Buffer write timeout: %ld ms, buffer size: %d bytes\n", + info->buffer_write_tout, + info->buffer_size); ++ } + +- puts (" Sector Start Addresses:"); ++ puts ("\n Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { ++ if ((i % 5) == 0) ++ printf ("\n"); + #ifdef CFG_FLASH_EMPTY_INFO + int k; + int size; +@@ -560,18 +573,15 @@ void flash_print_info (flash_info_t * in + } + } + +- if ((i % 5) == 0) +- printf ("\n"); + /* print empty and read-only info */ +- printf (" %08lX%s%s", ++ printf (" %08lX %c %s ", + info->start[i], +- erased ? " E" : " ", +- info->protect[i] ? "RO " : " "); ++ erased ? 'E' : ' ', ++ info->protect[i] ? "RO" : " "); + #else /* ! CFG_FLASH_EMPTY_INFO */ +- if ((i % 5) == 0) +- printf ("\n "); +- printf (" %08lX%s", +- info->start[i], info->protect[i] ? " (RO)" : " "); ++ printf (" %08lX %s ", ++ info->start[i], ++ info->protect[i] ? "RO" : " "); + #endif + } + putc ('\n'); +@@ -1071,6 +1081,55 @@ static int flash_toggle (flash_info_t * + } + + /*----------------------------------------------------------------------- ++ * read jedec ids from device and set corresponding fields in info struct ++ * ++ * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct ++ * ++*/ ++static void flash_read_jedec_ids (flash_info_t * info) ++{ ++ info->manufacturer_id = 0; ++ info->device_id = 0; ++ info->device_id2 = 0; ++ ++ switch (info->vendor) { ++ case CFI_CMDSET_INTEL_STANDARD: ++ case CFI_CMDSET_INTEL_EXTENDED: ++ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); ++ flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); ++ udelay(1000); /* some flash are slow to respond */ ++ info->manufacturer_id = flash_read_uchar (info, ++ FLASH_OFFSET_MANUFACTURER_ID); ++ info->device_id = flash_read_uchar (info, ++ FLASH_OFFSET_DEVICE_ID); ++ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); ++ break; ++ case CFI_CMDSET_AMD_STANDARD: ++ case CFI_CMDSET_AMD_EXTENDED: ++ flash_write_cmd(info, 0, 0, AMD_CMD_RESET); ++ flash_unlock_seq(info, 0); ++ flash_write_cmd(info, 0, AMD_ADDR_START, FLASH_CMD_READ_ID); ++ udelay(1000); /* some flash are slow to respond */ ++ info->manufacturer_id = flash_read_uchar (info, ++ FLASH_OFFSET_MANUFACTURER_ID); ++ info->device_id = flash_read_uchar (info, ++ FLASH_OFFSET_DEVICE_ID); ++ if (info->device_id == 0x7E) { ++ /* AMD 3-byte (expanded) device ids */ ++ info->device_id2 = flash_read_uchar (info, ++ FLASH_OFFSET_DEVICE_ID2); ++ info->device_id2 <<= 8; ++ info->device_id2 |= flash_read_uchar (info, ++ FLASH_OFFSET_DEVICE_ID3); ++ } ++ flash_write_cmd(info, 0, 0, AMD_CMD_RESET); ++ break; ++ default: ++ break; ++ } ++} ++ ++/*----------------------------------------------------------------------- + * detect if flash is compatible with the Common Flash Interface (CFI) + * http://www.jedec.org/download/search/jesd68.pdf + * +@@ -1120,15 +1179,31 @@ ulong flash_get_size (ulong base, int ba + uchar num_erase_regions; + int erase_region_size; + int erase_region_count; ++ int geometry_reversed = 0; ++ ++ info->ext_addr = 0; ++ info->cfi_version = 0; + #ifdef CFG_FLASH_PROTECTION +- int ext_addr; + info->legacy_unlock = 0; + #endif + + info->start[0] = base; + + if (flash_detect_cfi (info)) { +- info->vendor = flash_read_ushort (info, 0, FLASH_OFFSET_PRIMARY_VENDOR); ++ info->vendor = flash_read_ushort (info, 0, ++ FLASH_OFFSET_PRIMARY_VENDOR); ++ flash_read_jedec_ids (info); ++ flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); ++ num_erase_regions = flash_read_uchar (info, ++ FLASH_OFFSET_NUM_ERASE_REGIONS); ++ info->ext_addr = flash_read_ushort (info, 0, ++ FLASH_OFFSET_EXT_QUERY_T_P_ADDR); ++ if (info->ext_addr) { ++ info->cfi_version = (ushort) flash_read_uchar (info, ++ info->ext_addr + 3) << 8; ++ info->cfi_version |= (ushort) flash_read_uchar (info, ++ info->ext_addr + 4); ++ } + #ifdef DEBUG + flash_printqry (info, 0); + #endif +@@ -1139,26 +1214,46 @@ ulong flash_get_size (ulong base, int ba + info->cmd_reset = FLASH_CMD_RESET; + #ifdef CFG_FLASH_PROTECTION + /* read legacy lock/unlock bit from intel flash */ +- ext_addr = flash_read_ushort (info, 0, +- FLASH_OFFSET_EXT_QUERY_T_P_ADDR); +- info->legacy_unlock = +- flash_read_uchar (info, ext_addr + 5) & 0x08; ++ if (info->ext_addr) { ++ info->legacy_unlock = flash_read_uchar (info, ++ info->ext_addr + 5) & 0x08; ++ } + #endif + break; + case CFI_CMDSET_AMD_STANDARD: + case CFI_CMDSET_AMD_EXTENDED: + info->cmd_reset = AMD_CMD_RESET; ++ /* check if flash geometry needs reversal */ ++ if (num_erase_regions <= 1) ++ break; ++ /* reverse geometry if top boot part */ ++ if (info->cfi_version < 0x3131) { ++ /* CFI < 1.1, try to guess from device id */ ++ if ((info->device_id & 0x80) != 0) { ++ geometry_reversed = 1; ++ } ++ break; ++ } ++ /* CFI >= 1.1, deduct from top/bottom flag */ ++ /* note: ext_addr is valid since cfi_version > 0 */ ++ if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { ++ geometry_reversed = 1; ++ } + break; + } + + debug ("manufacturer is %d\n", info->vendor); ++ debug ("manufacturer id is 0x%x\n", info->manufacturer_id); ++ debug ("device id is 0x%x\n", info->device_id); ++ debug ("device id2 is 0x%x\n", info->device_id2); ++ debug ("cfi version is 0x%04x\n", info->cfi_version); ++ + size_ratio = info->portwidth / info->chipwidth; + /* if the chip is x8/x16 reduce the ratio by half */ + if ((info->interface == FLASH_CFI_X8X16) + && (info->chipwidth == FLASH_CFI_BY8)) { + size_ratio >>= 1; + } +- num_erase_regions = flash_read_uchar (info, FLASH_OFFSET_NUM_ERASE_REGIONS); + debug ("size_ratio %d port %d bits chip %d bits\n", + size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, + info->chipwidth << CFI_FLASH_SHIFT_WIDTH); +@@ -1171,7 +1266,12 @@ ulong flash_get_size (ulong base, int ba + num_erase_regions, NUM_ERASE_REGIONS); + break; + } +- tmp = flash_read_long (info, 0, ++ if (geometry_reversed) ++ tmp = flash_read_long (info, 0, ++ FLASH_OFFSET_ERASE_REGIONS + ++ (num_erase_regions - 1 - i) * 4); ++ else ++ tmp = flash_read_long (info, 0, + FLASH_OFFSET_ERASE_REGIONS + + i * 4); + erase_region_size = +diff -Naupr u-boot-1.1.6/drivers/fsl_i2c.c u-boot-1.1.6-fsl-1/drivers/fsl_i2c.c +--- u-boot-1.1.6/drivers/fsl_i2c.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/drivers/fsl_i2c.c 2006-11-30 12:34:13.000000000 -0600 +@@ -28,29 +28,52 @@ + #include /* HW definitions */ + + #define I2C_TIMEOUT (CFG_HZ / 4) +-#define I2C ((struct fsl_i2c *)(CFG_IMMR + CFG_I2C_OFFSET)) + ++#define I2C_READ_BIT 1 ++#define I2C_WRITE_BIT 0 ++ ++/* Initialize the bus pointer to whatever one the SPD EEPROM is on. ++ * Default is bus 0. This is necessary because the DDR initialization ++ * runs from ROM, and we can't switch buses because we can't modify ++ * the global variables. ++ */ ++#ifdef CFG_SPD_BUS_NUM ++static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM; ++#else ++static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0; ++#endif ++ ++static volatile struct fsl_i2c *i2c_dev[2] = { ++ (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET), ++#ifdef CFG_I2C2_OFFSET ++ (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET) ++#endif ++}; + + void + i2c_init(int speed, int slaveadd) + { +- /* stop I2C controller */ +- writeb(0x0, &I2C->cr); +- +- /* set clock */ +- writeb(0x3f, &I2C->fdr); +- +- /* set default filter */ +- writeb(0x10, &I2C->dfsrr); ++ volatile struct fsl_i2c *dev; + +- /* write slave address */ +- writeb(slaveadd, &I2C->adr); ++ dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET); + +- /* clear status register */ +- writeb(0x0, &I2C->sr); +- +- /* start I2C controller */ +- writeb(I2C_CR_MEN, &I2C->cr); ++ writeb(0, &dev->cr); /* stop I2C controller */ ++ writeb(0x3F, &dev->fdr); /* set bus speed */ ++ writeb(0x3F, &dev->dfsrr); /* set default filter */ ++ writeb(slaveadd << 1, &dev->adr); /* write slave address */ ++ writeb(0x0, &dev->sr); /* clear status register */ ++ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ ++ ++#ifdef CFG_I2C2_OFFSET ++ dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET); ++ ++ writeb(0, &dev->cr); /* stop I2C controller */ ++ writeb(0x3F, &dev->fdr); /* set bus speed */ ++ writeb(0x3F, &dev->dfsrr); /* set default filter */ ++ writeb(slaveadd, &dev->adr); /* write slave address */ ++ writeb(0x0, &dev->sr); /* clear status register */ ++ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ ++#endif /* CFG_I2C2_OFFSET */ + } + + static __inline__ int +@@ -58,7 +81,7 @@ i2c_wait4bus(void) + { + ulong timeval = get_timer(0); + +- while (readb(&I2C->sr) & I2C_SR_MBB) { ++ while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) { + if (get_timer(timeval) > I2C_TIMEOUT) { + return -1; + } +@@ -74,11 +97,11 @@ i2c_wait(int write) + ulong timeval = get_timer(0); + + do { +- csr = readb(&I2C->sr); ++ csr = readb(&i2c_dev[i2c_bus_num]->sr); + if (!(csr & I2C_SR_MIF)) + continue; + +- writeb(0x0, &I2C->sr); ++ writeb(0x0, &i2c_dev[i2c_bus_num]->sr); + + if (csr & I2C_SR_MAL) { + debug("i2c_wait: MAL\n"); +@@ -90,7 +113,7 @@ i2c_wait(int write) + return -1; + } + +- if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) { ++ if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) { + debug("i2c_wait: No RXACK\n"); + return -1; + } +@@ -107,11 +130,11 @@ i2c_write_addr (u8 dev, u8 dir, int rsta + { + writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX + | (rsta ? I2C_CR_RSTA : 0), +- &I2C->cr); ++ &i2c_dev[i2c_bus_num]->cr); + +- writeb((dev << 1) | dir, &I2C->dr); ++ writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr); + +- if (i2c_wait(I2C_WRITE) < 0) ++ if (i2c_wait(I2C_WRITE_BIT) < 0) + return 0; + + return 1; +@@ -123,12 +146,12 @@ __i2c_write(u8 *data, int length) + int i; + + writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, +- &I2C->cr); ++ &i2c_dev[i2c_bus_num]->cr); + + for (i = 0; i < length; i++) { +- writeb(data[i], &I2C->dr); ++ writeb(data[i], &i2c_dev[i2c_bus_num]->dr); + +- if (i2c_wait(I2C_WRITE) < 0) ++ if (i2c_wait(I2C_WRITE_BIT) < 0) + break; + } + +@@ -141,25 +164,25 @@ __i2c_read(u8 *data, int length) + int i; + + writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0), +- &I2C->cr); ++ &i2c_dev[i2c_bus_num]->cr); + + /* dummy read */ +- readb(&I2C->dr); ++ readb(&i2c_dev[i2c_bus_num]->dr); + + for (i = 0; i < length; i++) { +- if (i2c_wait(I2C_READ) < 0) ++ if (i2c_wait(I2C_READ_BIT) < 0) + break; + + /* Generate ack on last next to last byte */ + if (i == length - 2) + writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK, +- &I2C->cr); ++ &i2c_dev[i2c_bus_num]->cr); + + /* Generate stop on last byte */ + if (i == length - 1) +- writeb(I2C_CR_MEN | I2C_CR_TXAK, &I2C->cr); ++ writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr); + +- data[i] = readb(&I2C->dr); ++ data[i] = readb(&i2c_dev[i2c_bus_num]->dr); + } + + return i; +@@ -172,13 +195,13 @@ i2c_read(u8 dev, uint addr, int alen, u8 + u8 *a = (u8*)&addr; + + if (i2c_wait4bus() >= 0 +- && i2c_write_addr(dev, I2C_WRITE, 0) != 0 ++ && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 + && __i2c_write(&a[4 - alen], alen) == alen +- && i2c_write_addr(dev, I2C_READ, 1) != 0) { ++ && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) { + i = __i2c_read(data, length); + } + +- writeb(I2C_CR_MEN, &I2C->cr); ++ writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); + + if (i == length) + return 0; +@@ -193,12 +216,12 @@ i2c_write(u8 dev, uint addr, int alen, u + u8 *a = (u8*)&addr; + + if (i2c_wait4bus() >= 0 +- && i2c_write_addr(dev, I2C_WRITE, 0) != 0 ++ && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 + && __i2c_write(&a[4 - alen], alen) == alen) { + i = __i2c_write(data, length); + } + +- writeb(I2C_CR_MEN, &I2C->cr); ++ writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); + + if (i == length) + return 0; +@@ -237,5 +260,34 @@ i2c_reg_write(uchar i2c_addr, uchar reg, + i2c_write(i2c_addr, reg, 1, &val, 1); + } + ++int i2c_set_bus_num(unsigned int bus) ++{ ++#ifdef CFG_I2C2_OFFSET ++ if (bus > 1) { ++#else ++ if (bus > 0) { ++#endif ++ return -1; ++ } ++ ++ i2c_bus_num = bus; ++ ++ return 0; ++} ++ ++int i2c_set_bus_speed(unsigned int speed) ++{ ++ return -1; ++} ++ ++unsigned int i2c_get_bus_num(void) ++{ ++ return i2c_bus_num; ++} ++ ++unsigned int i2c_get_bus_speed(void) ++{ ++ return 0; ++} + #endif /* CONFIG_HARD_I2C */ + #endif /* CONFIG_FSL_I2C */ +diff -Naupr u-boot-1.1.6/drivers/nand/nand_base.c u-boot-1.1.6-fsl-1/drivers/nand/nand_base.c +--- u-boot-1.1.6/drivers/nand/nand_base.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/drivers/nand/nand_base.c 2006-12-06 10:33:49.000000000 -0600 +@@ -838,9 +838,9 @@ static int nand_wait(struct mtd_info *mt + unsigned long timeo; + + if (state == FL_ERASING) +- timeo = CFG_HZ * 400; ++ timeo = (CFG_HZ * 400) / 1000; + else +- timeo = CFG_HZ * 20; ++ timeo = (CFG_HZ * 20) / 1000; + + if ((state == FL_ERASING) && (this->options & NAND_IS_AND)) + this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); +@@ -852,8 +852,8 @@ static int nand_wait(struct mtd_info *mt + while (1) { + if (get_timer(0) > timeo) { + printf("Timeout!"); +- return 0; +- } ++ return 0x01; ++ } + + if (this->dev_ready) { + if (this->dev_ready(mtd)) +@@ -1713,6 +1713,7 @@ static int nand_write_ecc (struct mtd_in + goto out; + } + *retlen = written; ++ bufstart = (u_char*) &buf[written]; + + ofs = autoplace ? mtd->oobavail : mtd->oobsize; + if (eccbuf) +@@ -2407,7 +2408,9 @@ int nand_scan (struct mtd_info *mtd, int + } + + if (!nand_flash_ids[i].name) { ++#ifndef CFG_NAND_QUIET_TEST + printk (KERN_WARNING "No NAND device found!!!\n"); ++#endif + this->select_chip(mtd, -1); + return 1; + } +diff -Naupr u-boot-1.1.6/drivers/qe/Makefile u-boot-1.1.6-fsl-1/drivers/qe/Makefile +--- u-boot-1.1.6/drivers/qe/Makefile 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/drivers/qe/Makefile 2006-11-10 11:24:29.000000000 -0600 +@@ -0,0 +1,43 @@ ++# ++# Copyright (C) 2006 Freescale Semiconductor, Inc. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB := $(obj)qe.a ++ ++COBJS := qe.o uccf.o uec.o uec_phy.o ++ ++SRCS := $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++ ++all: $(LIB) ++ ++$(LIB): $(obj).depend $(OBJS) ++ $(AR) $(ARFLAGS) $@ $(OBJS) ++ ++######################################################################### ++ ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +diff -Naupr u-boot-1.1.6/drivers/qe/qe.c u-boot-1.1.6-fsl-1/drivers/qe/qe.c +--- u-boot-1.1.6/drivers/qe/qe.c 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/drivers/qe/qe.c 2006-11-10 11:24:29.000000000 -0600 +@@ -0,0 +1,254 @@ ++/* ++ * Copyright (C) 2006 Freescale Semiconductor, Inc. ++ * ++ * Dave Liu ++ * based on source code of Shlomi Gridish ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include "common.h" ++#include "asm/errno.h" ++#include "asm/io.h" ++#include "asm/immap_qe.h" ++#include "qe.h" ++ ++#if defined(CONFIG_QE) ++qe_map_t *qe_immr = NULL; ++static qe_snum_t snums[QE_NUM_OF_SNUM]; ++ ++void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data) ++{ ++ u32 cecr; ++ ++ if (cmd == QE_RESET) { ++ out_be32(&qe_immr->cp.cecr,(u32) (cmd | QE_CR_FLG)); ++ } else { ++ out_be32(&qe_immr->cp.cecdr, cmd_data); ++ out_be32(&qe_immr->cp.cecr, (sbc | QE_CR_FLG | ++ ((u32) mcn<cp.cecr); ++ } while (cecr & QE_CR_FLG); ++ ++ return; ++} ++ ++uint qe_muram_alloc(uint size, uint align) ++{ ++ DECLARE_GLOBAL_DATA_PTR; ++ ++ uint retloc; ++ uint align_mask, off; ++ uint savebase; ++ ++ align_mask = align - 1; ++ savebase = gd->mp_alloc_base; ++ ++ if ((off = (gd->mp_alloc_base & align_mask)) != 0) ++ gd->mp_alloc_base += (align - off); ++ ++ if ((off = size & align_mask) != 0) ++ size += (align - off); ++ ++ if ((gd->mp_alloc_base + size) >= gd->mp_alloc_top) { ++ gd->mp_alloc_base = savebase; ++ printf("%s: ran out of ram.\n", __FUNCTION__); ++ } ++ ++ retloc = gd->mp_alloc_base; ++ gd->mp_alloc_base += size; ++ ++ memset((void *)&qe_immr->muram[retloc], 0, size); ++ ++ __asm__ __volatile__("sync"); ++ ++ return retloc; ++} ++ ++void *qe_muram_addr(uint offset) ++{ ++ return (void *)&qe_immr->muram[offset]; ++} ++ ++static void qe_sdma_init(void) ++{ ++ volatile sdma_t *p; ++ uint sdma_buffer_base; ++ ++ p = (volatile sdma_t *)&qe_immr->sdma; ++ ++ /* All of DMA transaction in bus 1 */ ++ out_be32(&p->sdaqr, 0); ++ out_be32(&p->sdaqmr, 0); ++ ++ /* Allocate 2KB temporary buffer for sdma */ ++ sdma_buffer_base = qe_muram_alloc(2048, 64); ++ out_be32(&p->sdwbcr, sdma_buffer_base & QE_SDEBCR_BA_MASK); ++ ++ /* Clear sdma status */ ++ out_be32(&p->sdsr, 0x03000000); ++ ++ /* Enable global mode on bus 1, and 2KB buffer size */ ++ out_be32(&p->sdmr, QE_SDMR_GLB_1_MSK | (0x3 << QE_SDMR_CEN_SHIFT)); ++} ++ ++static u8 thread_snum[QE_NUM_OF_SNUM] = { ++ 0x04, 0x05, 0x0c, 0x0d, ++ 0x14, 0x15, 0x1c, 0x1d, ++ 0x24, 0x25, 0x2c, 0x2d, ++ 0x34, 0x35, 0x88, 0x89, ++ 0x98, 0x99, 0xa8, 0xa9, ++ 0xb8, 0xb9, 0xc8, 0xc9, ++ 0xd8, 0xd9, 0xe8, 0xe9 ++}; ++ ++static void qe_snums_init(void) ++{ ++ int i; ++ ++ for (i = 0; i < QE_NUM_OF_SNUM; i++) { ++ snums[i].state = QE_SNUM_STATE_FREE; ++ snums[i].num = thread_snum[i]; ++ } ++} ++ ++int qe_get_snum(void) ++{ ++ int snum = -EBUSY; ++ int i; ++ ++ for (i = 0; i < QE_NUM_OF_SNUM; i++) { ++ if (snums[i].state == QE_SNUM_STATE_FREE) { ++ snums[i].state = QE_SNUM_STATE_USED; ++ snum = snums[i].num; ++ break; ++ } ++ } ++ ++ return snum; ++} ++ ++void qe_put_snum(u8 snum) ++{ ++ int i; ++ ++ for (i = 0; i < QE_NUM_OF_SNUM; i++) { ++ if (snums[i].num == snum) { ++ snums[i].state = QE_SNUM_STATE_FREE; ++ break; ++ } ++ } ++} ++ ++void qe_init(uint qe_base) ++{ ++ DECLARE_GLOBAL_DATA_PTR; ++ ++ /* Init the QE IMMR base */ ++ qe_immr = (qe_map_t *)qe_base; ++ ++ gd->mp_alloc_base = QE_DATAONLY_BASE; ++ gd->mp_alloc_top = gd->mp_alloc_base + QE_DATAONLY_SIZE; ++ ++ qe_sdma_init(); ++ qe_snums_init(); ++} ++ ++void qe_reset(void) ++{ ++ qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID, ++ (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0); ++} ++ ++void qe_assign_page(uint snum, uint para_ram_base) ++{ ++ u32 cecr; ++ ++ out_be32(&qe_immr->cp.cecdr, para_ram_base); ++ out_be32(&qe_immr->cp.cecr, ((u32) snum<cp.cecr); ++ } while (cecr & QE_CR_FLG ); ++ ++ return; ++} ++ ++/* ++ * brg: 0~15 as BRG1~BRG16 ++ rate: baud rate ++ * BRG input clock comes from the BRGCLK (internal clock generated from ++ the QE clock, it is one-half of the QE clock), If need the clock source ++ from CLKn pin, we have te change the function. ++ */ ++ ++#define BRG_CLK (gd->brg_clk) ++ ++int qe_set_brg(uint brg, uint rate) ++{ ++ DECLARE_GLOBAL_DATA_PTR; ++ volatile uint *bp; ++ u32 divisor; ++ int div16 = 0; ++ ++ if (brg >= QE_NUM_OF_BRGS) ++ return -EINVAL; ++ bp = (uint *)&qe_immr->brg.brgc1; ++ bp += brg; ++ ++ divisor = (BRG_CLK / rate); ++ if (divisor > QE_BRGC_DIVISOR_MAX + 1) { ++ div16 = 1; ++ divisor /= 16; ++ } ++ ++ *bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE; ++ __asm__ __volatile__("sync"); ++ ++ if (div16) { ++ *bp |= QE_BRGC_DIV16; ++ __asm__ __volatile__("sync"); ++ } ++ ++ return 0; ++} ++ ++/* Set ethernet MII clock master ++*/ ++int qe_set_mii_clk_src(int ucc_num) ++{ ++ u32 cmxgcr; ++ ++ /* check if the UCC number is in range. */ ++ if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) { ++ printf("%s: ucc num not in ranges\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ cmxgcr = in_be32(&qe_immr->qmx.cmxgcr); ++ cmxgcr &= ~QE_CMXGCR_MII_ENET_MNG_MASK; ++ cmxgcr |= (ucc_num <qmx.cmxgcr, cmxgcr); ++ ++ return 0; ++} ++ ++#endif /* CONFIG_QE */ +diff -Naupr u-boot-1.1.6/drivers/qe/qe.h u-boot-1.1.6-fsl-1/drivers/qe/qe.h +--- u-boot-1.1.6/drivers/qe/qe.h 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/drivers/qe/qe.h 2006-11-10 11:24:29.000000000 -0600 +@@ -0,0 +1,237 @@ ++/* ++ * Copyright (C) 2006 Freescale Semiconductor, Inc. ++ * ++ * Dave Liu ++ * based on source code of Shlomi Gridish ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __QE_H__ ++#define __QE_H__ ++ ++#include "common.h" ++ ++#define QE_NUM_OF_SNUM 28 ++#define QE_NUM_OF_BRGS 16 ++#define UCC_MAX_NUM 8 ++ ++#define QE_DATAONLY_BASE (uint)(128) ++#define QE_DATAONLY_SIZE ((uint)(0xc000) - QE_DATAONLY_BASE) ++ ++/* QE threads SNUM ++*/ ++typedef enum qe_snum_state { ++ QE_SNUM_STATE_USED, /* used */ ++ QE_SNUM_STATE_FREE /* free */ ++} qe_snum_state_e; ++ ++typedef struct qe_snum { ++ u8 num; /* snum */ ++ qe_snum_state_e state; /* state */ ++} qe_snum_t; ++ ++/* QE RISC allocation ++*/ ++typedef enum qe_risc_allocation { ++ QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */ ++ QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */ ++ QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* RISC 1 or RISC 2 */ ++} qe_risc_allocation_e; ++ ++/* QE CECR commands for UCC fast. ++*/ ++#define QE_CR_FLG 0x00010000 ++#define QE_RESET 0x80000000 ++#define QE_INIT_TX_RX 0x00000000 ++#define QE_INIT_RX 0x00000001 ++#define QE_INIT_TX 0x00000002 ++#define QE_ENTER_HUNT_MODE 0x00000003 ++#define QE_STOP_TX 0x00000004 ++#define QE_GRACEFUL_STOP_TX 0x00000005 ++#define QE_RESTART_TX 0x00000006 ++#define QE_SWITCH_COMMAND 0x00000007 ++#define QE_SET_GROUP_ADDRESS 0x00000008 ++#define QE_INSERT_CELL 0x00000009 ++#define QE_ATM_TRANSMIT 0x0000000a ++#define QE_CELL_POOL_GET 0x0000000b ++#define QE_CELL_POOL_PUT 0x0000000c ++#define QE_IMA_HOST_CMD 0x0000000d ++#define QE_ATM_MULTI_THREAD_INIT 0x00000011 ++#define QE_ASSIGN_PAGE 0x00000012 ++#define QE_START_FLOW_CONTROL 0x00000014 ++#define QE_STOP_FLOW_CONTROL 0x00000015 ++#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016 ++#define QE_GRACEFUL_STOP_RX 0x0000001a ++#define QE_RESTART_RX 0x0000001b ++ ++/* QE CECR Sub Block Code - sub block code of QE command. ++*/ ++#define QE_CR_SUBBLOCK_INVALID 0x00000000 ++#define QE_CR_SUBBLOCK_USB 0x03200000 ++#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000 ++#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000 ++#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000 ++#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000 ++#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000 ++#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000 ++#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000 ++#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000 ++#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000 ++#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000 ++#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000 ++#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000 ++#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000 ++#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000 ++#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000 ++#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000 ++#define QE_CR_SUBBLOCK_MCC1 0x03800000 ++#define QE_CR_SUBBLOCK_MCC2 0x03a00000 ++#define QE_CR_SUBBLOCK_MCC3 0x03000000 ++#define QE_CR_SUBBLOCK_IDMA1 0x02800000 ++#define QE_CR_SUBBLOCK_IDMA2 0x02a00000 ++#define QE_CR_SUBBLOCK_IDMA3 0x02c00000 ++#define QE_CR_SUBBLOCK_IDMA4 0x02e00000 ++#define QE_CR_SUBBLOCK_HPAC 0x01e00000 ++#define QE_CR_SUBBLOCK_SPI1 0x01400000 ++#define QE_CR_SUBBLOCK_SPI2 0x01600000 ++#define QE_CR_SUBBLOCK_RAND 0x01c00000 ++#define QE_CR_SUBBLOCK_TIMER 0x01e00000 ++#define QE_CR_SUBBLOCK_GENERAL 0x03c00000 ++ ++/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command. ++*/ ++#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */ ++#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00 ++#define QE_CR_PROTOCOL_ATM_POS 0x0A ++#define QE_CR_PROTOCOL_ETHERNET 0x0C ++#define QE_CR_PROTOCOL_L2_SWITCH 0x0D ++#define QE_CR_PROTOCOL_SHIFT 6 ++ ++/* QE ASSIGN PAGE command ++*/ ++#define QE_CR_ASSIGN_PAGE_SNUM_SHIFT 17 ++ ++/* Communication Direction. ++*/ ++typedef enum comm_dir { ++ COMM_DIR_NONE = 0, ++ COMM_DIR_RX = 1, ++ COMM_DIR_TX = 2, ++ COMM_DIR_RX_AND_TX = 3 ++} comm_dir_e; ++ ++/* Clocks and BRG's ++*/ ++typedef enum qe_clock { ++ QE_CLK_NONE = 0, ++ QE_BRG1, /* Baud Rate Generator 1 */ ++ QE_BRG2, /* Baud Rate Generator 2 */ ++ QE_BRG3, /* Baud Rate Generator 3 */ ++ QE_BRG4, /* Baud Rate Generator 4 */ ++ QE_BRG5, /* Baud Rate Generator 5 */ ++ QE_BRG6, /* Baud Rate Generator 6 */ ++ QE_BRG7, /* Baud Rate Generator 7 */ ++ QE_BRG8, /* Baud Rate Generator 8 */ ++ QE_BRG9, /* Baud Rate Generator 9 */ ++ QE_BRG10, /* Baud Rate Generator 10 */ ++ QE_BRG11, /* Baud Rate Generator 11 */ ++ QE_BRG12, /* Baud Rate Generator 12 */ ++ QE_BRG13, /* Baud Rate Generator 13 */ ++ QE_BRG14, /* Baud Rate Generator 14 */ ++ QE_BRG15, /* Baud Rate Generator 15 */ ++ QE_BRG16, /* Baud Rate Generator 16 */ ++ QE_CLK1, /* Clock 1 */ ++ QE_CLK2, /* Clock 2 */ ++ QE_CLK3, /* Clock 3 */ ++ QE_CLK4, /* Clock 4 */ ++ QE_CLK5, /* Clock 5 */ ++ QE_CLK6, /* Clock 6 */ ++ QE_CLK7, /* Clock 7 */ ++ QE_CLK8, /* Clock 8 */ ++ QE_CLK9, /* Clock 9 */ ++ QE_CLK10, /* Clock 10 */ ++ QE_CLK11, /* Clock 11 */ ++ QE_CLK12, /* Clock 12 */ ++ QE_CLK13, /* Clock 13 */ ++ QE_CLK14, /* Clock 14 */ ++ QE_CLK15, /* Clock 15 */ ++ QE_CLK16, /* Clock 16 */ ++ QE_CLK17, /* Clock 17 */ ++ QE_CLK18, /* Clock 18 */ ++ QE_CLK19, /* Clock 19 */ ++ QE_CLK20, /* Clock 20 */ ++ QE_CLK21, /* Clock 21 */ ++ QE_CLK22, /* Clock 22 */ ++ QE_CLK23, /* Clock 23 */ ++ QE_CLK24, /* Clock 24 */ ++ QE_CLK_DUMMY ++} qe_clock_e; ++ ++/* QE CMXGCR register ++*/ ++#define QE_CMXGCR_MII_ENET_MNG_MASK 0x00007000 ++#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 ++ ++/* QE CMXUCR registers ++ */ ++#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F ++ ++/* QE BRG configuration register ++*/ ++#define QE_BRGC_ENABLE 0x00010000 ++#define QE_BRGC_DIVISOR_SHIFT 1 ++#define QE_BRGC_DIVISOR_MAX 0xFFF ++#define QE_BRGC_DIV16 1 ++ ++/* QE SDMA registers ++*/ ++#define QE_SDSR_BER1 0x02000000 ++#define QE_SDSR_BER2 0x01000000 ++ ++#define QE_SDMR_GLB_1_MSK 0x80000000 ++#define QE_SDMR_ADR_SEL 0x20000000 ++#define QE_SDMR_BER1_MSK 0x02000000 ++#define QE_SDMR_BER2_MSK 0x01000000 ++#define QE_SDMR_EB1_MSK 0x00800000 ++#define QE_SDMR_ER1_MSK 0x00080000 ++#define QE_SDMR_ER2_MSK 0x00040000 ++#define QE_SDMR_CEN_MASK 0x0000E000 ++#define QE_SDMR_SBER_1 0x00000200 ++#define QE_SDMR_SBER_2 0x00000200 ++#define QE_SDMR_EB1_PR_MASK 0x000000C0 ++#define QE_SDMR_ER1_PR 0x00000008 ++ ++#define QE_SDMR_CEN_SHIFT 13 ++#define QE_SDMR_EB1_PR_SHIFT 6 ++ ++#define QE_SDTM_MSNUM_SHIFT 24 ++ ++#define QE_SDEBCR_BA_MASK 0x01FFFFFF ++ ++void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign); ++void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data); ++uint qe_muram_alloc(uint size, uint align); ++void *qe_muram_addr(uint offset); ++int qe_get_snum(void); ++void qe_put_snum(u8 snum); ++void qe_init(uint qe_base); ++void qe_reset(void); ++void qe_assign_page(uint snum, uint para_ram_base); ++int qe_set_brg(uint brg, uint rate); ++int qe_set_mii_clk_src(int ucc_num); ++ ++#endif /* __QE_H__ */ +diff -Naupr u-boot-1.1.6/drivers/qe/uccf.c u-boot-1.1.6-fsl-1/drivers/qe/uccf.c +--- u-boot-1.1.6/drivers/qe/uccf.c 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/drivers/qe/uccf.c 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,404 @@ ++/* ++ * Copyright (C) 2006 Freescale Semiconductor, Inc. ++ * ++ * Dave Liu ++ * based on source code of Shlomi Gridish ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include "common.h" ++#include "malloc.h" ++#include "asm/errno.h" ++#include "asm/io.h" ++#include "asm/immap_qe.h" ++#include "qe.h" ++#include "uccf.h" ++ ++#if defined(CONFIG_QE) ++void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf) ++{ ++ out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD); ++} ++ ++u32 ucc_fast_get_qe_cr_subblock(int ucc_num) ++{ ++ switch (ucc_num) { ++ case 0: return QE_CR_SUBBLOCK_UCCFAST1; ++ case 1: return QE_CR_SUBBLOCK_UCCFAST2; ++ case 2: return QE_CR_SUBBLOCK_UCCFAST3; ++ case 3: return QE_CR_SUBBLOCK_UCCFAST4; ++ case 4: return QE_CR_SUBBLOCK_UCCFAST5; ++ case 5: return QE_CR_SUBBLOCK_UCCFAST6; ++ case 6: return QE_CR_SUBBLOCK_UCCFAST7; ++ case 7: return QE_CR_SUBBLOCK_UCCFAST8; ++ default: return QE_CR_SUBBLOCK_INVALID; ++ } ++} ++ ++static void ucc_get_cmxucr_reg(int ucc_num, volatile u32 **p_cmxucr, ++ u8 *reg_num, u8 *shift) ++{ ++ switch (ucc_num) { ++ case 0: /* UCC1 */ ++ *p_cmxucr = &(qe_immr->qmx.cmxucr1); ++ *reg_num = 1; ++ *shift = 16; ++ break; ++ case 2: /* UCC3 */ ++ *p_cmxucr = &(qe_immr->qmx.cmxucr1); ++ *reg_num = 1; ++ *shift = 0; ++ break; ++ case 4: /* UCC5 */ ++ *p_cmxucr = &(qe_immr->qmx.cmxucr2); ++ *reg_num = 2; ++ *shift = 16; ++ break; ++ case 6: /* UCC7 */ ++ *p_cmxucr = &(qe_immr->qmx.cmxucr2); ++ *reg_num = 2; ++ *shift = 0; ++ break; ++ case 1: /* UCC2 */ ++ *p_cmxucr = &(qe_immr->qmx.cmxucr3); ++ *reg_num = 3; ++ *shift = 16; ++ break; ++ case 3: /* UCC4 */ ++ *p_cmxucr = &(qe_immr->qmx.cmxucr3); ++ *reg_num = 3; ++ *shift = 0; ++ break; ++ case 5: /* UCC6 */ ++ *p_cmxucr = &(qe_immr->qmx.cmxucr4); ++ *reg_num = 4; ++ *shift = 16; ++ break; ++ case 7: /* UCC8 */ ++ *p_cmxucr = &(qe_immr->qmx.cmxucr4); ++ *reg_num = 4; ++ *shift = 0; ++ break; ++ default: ++ break; ++ } ++} ++ ++static int ucc_set_clk_src(int ucc_num, qe_clock_e clock, comm_dir_e mode) ++{ ++ volatile u32 *p_cmxucr = NULL; ++ u8 reg_num = 0; ++ u8 shift = 0; ++ u32 clockBits; ++ u32 clockMask; ++ int source = -1; ++ ++ /* check if the UCC number is in range. */ ++ if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) ++ return -EINVAL; ++ ++ if (! ((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX))) { ++ printf("%s: bad comm mode type passed\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ ucc_get_cmxucr_reg(ucc_num, &p_cmxucr, ®_num, &shift); ++ ++ switch (reg_num) { ++ case 1: ++ switch (clock) { ++ case QE_BRG1: source = 1; break; ++ case QE_BRG2: source = 2; break; ++ case QE_BRG7: source = 3; break; ++ case QE_BRG8: source = 4; break; ++ case QE_CLK9: source = 5; break; ++ case QE_CLK10: source = 6; break; ++ case QE_CLK11: source = 7; break; ++ case QE_CLK12: source = 8; break; ++ case QE_CLK15: source = 9; break; ++ case QE_CLK16: source = 10; break; ++ default: source = -1; break; ++ } ++ break; ++ case 2: ++ switch (clock) { ++ case QE_BRG5: source = 1; break; ++ case QE_BRG6: source = 2; break; ++ case QE_BRG7: source = 3; break; ++ case QE_BRG8: source = 4; break; ++ case QE_CLK13: source = 5; break; ++ case QE_CLK14: source = 6; break; ++ case QE_CLK19: source = 7; break; ++ case QE_CLK20: source = 8; break; ++ case QE_CLK15: source = 9; break; ++ case QE_CLK16: source = 10; break; ++ default: source = -1; break; ++ } ++ break; ++ case 3: ++ switch (clock) { ++ case QE_BRG9: source = 1; break; ++ case QE_BRG10: source = 2; break; ++ case QE_BRG15: source = 3; break; ++ case QE_BRG16: source = 4; break; ++ case QE_CLK3: source = 5; break; ++ case QE_CLK4: source = 6; break; ++ case QE_CLK17: source = 7; break; ++ case QE_CLK18: source = 8; break; ++ case QE_CLK7: source = 9; break; ++ case QE_CLK8: source = 10; break; ++ case QE_CLK16: source = 11; break; ++ default: source = -1; break; ++ } ++ break; ++ case 4: ++ switch (clock) { ++ case QE_BRG13: source = 1; break; ++ case QE_BRG14: source = 2; break; ++ case QE_BRG15: source = 3; break; ++ case QE_BRG16: source = 4; break; ++ case QE_CLK5: source = 5; break; ++ case QE_CLK6: source = 6; break; ++ case QE_CLK21: source = 7; break; ++ case QE_CLK22: source = 8; break; ++ case QE_CLK7: source = 9; break; ++ case QE_CLK8: source = 10; break; ++ case QE_CLK16: source = 11; break; ++ default: source = -1; break; ++ } ++ break; ++ default: ++ source = -1; ++ break; ++ } ++ ++ if (source == -1) { ++ printf("%s: Bad combination of clock and UCC\n", __FUNCTION__); ++ return -ENOENT; ++ } ++ ++ clockBits = (u32) source; ++ clockMask = QE_CMXUCR_TX_CLK_SRC_MASK; ++ if (mode == COMM_DIR_RX) { ++ clockBits <<= 4; /* Rx field is 4 bits to left of Tx field */ ++ clockMask <<= 4; /* Rx field is 4 bits to left of Tx field */ ++ } ++ clockBits <<= shift; ++ clockMask <<= shift; ++ ++ out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clockMask) | clockBits); ++ ++ return 0; ++} ++ ++static uint ucc_get_reg_baseaddr(int ucc_num) ++{ ++ uint base = 0; ++ ++ /* check if the UCC number is in range */ ++ if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) { ++ printf("%s: the UCC num not in ranges\n", __FUNCTION__); ++ return 0; ++ } ++ ++ switch (ucc_num) { ++ case 0: base = 0x00002000; break; ++ case 1: base = 0x00003000; break; ++ case 2: base = 0x00002200; break; ++ case 3: base = 0x00003200; break; ++ case 4: base = 0x00002400; break; ++ case 5: base = 0x00003400; break; ++ case 6: base = 0x00002600; break; ++ case 7: base = 0x00003600; break; ++ default: break; ++ } ++ ++ base = (uint)qe_immr + base; ++ return base; ++} ++ ++void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode) ++{ ++ ucc_fast_t *uf_regs; ++ u32 gumr; ++ ++ uf_regs = uccf->uf_regs; ++ ++ /* Enable reception and/or transmission on this UCC. */ ++ gumr = in_be32(&uf_regs->gumr); ++ if (mode & COMM_DIR_TX) { ++ gumr |= UCC_FAST_GUMR_ENT; ++ uccf->enabled_tx = 1; ++ } ++ if (mode & COMM_DIR_RX) { ++ gumr |= UCC_FAST_GUMR_ENR; ++ uccf->enabled_rx = 1; ++ } ++ out_be32(&uf_regs->gumr, gumr); ++} ++ ++void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode) ++{ ++ ucc_fast_t *uf_regs; ++ u32 gumr; ++ ++ uf_regs = uccf->uf_regs; ++ ++ /* Disable reception and/or transmission on this UCC. */ ++ gumr = in_be32(&uf_regs->gumr); ++ if (mode & COMM_DIR_TX) { ++ gumr &= ~UCC_FAST_GUMR_ENT; ++ uccf->enabled_tx = 0; ++ } ++ if (mode & COMM_DIR_RX) { ++ gumr &= ~UCC_FAST_GUMR_ENR; ++ uccf->enabled_rx = 0; ++ } ++ out_be32(&uf_regs->gumr, gumr); ++} ++ ++int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret) ++{ ++ ucc_fast_private_t *uccf; ++ ucc_fast_t *uf_regs; ++ ++ if (!uf_info) ++ return -EINVAL; ++ ++ if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) { ++ printf("%s: Illagal UCC number!\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ uccf = (ucc_fast_private_t *)malloc(sizeof(ucc_fast_private_t)); ++ if (!uccf) { ++ printf("%s: No memory for UCC fast data structure!\n", ++ __FUNCTION__); ++ return -ENOMEM; ++ } ++ memset(uccf, 0, sizeof(ucc_fast_private_t)); ++ ++ /* Save fast UCC structure */ ++ uccf->uf_info = uf_info; ++ uccf->uf_regs = (ucc_fast_t *)ucc_get_reg_baseaddr(uf_info->ucc_num); ++ ++ if (uccf->uf_regs == NULL) { ++ printf("%s: No memory map for UCC fast controller!\n", ++ __FUNCTION__); ++ return -ENOMEM; ++ } ++ ++ uccf->enabled_tx = 0; ++ uccf->enabled_rx = 0; ++ ++ uf_regs = uccf->uf_regs; ++ uccf->p_ucce = (u32 *) &(uf_regs->ucce); ++ uccf->p_uccm = (u32 *) &(uf_regs->uccm); ++ ++ /* Init GUEMR register, UCC both Rx and Tx is Fast protocol */ ++ out_8(&uf_regs->guemr, UCC_GUEMR_SET_RESERVED3 | UCC_GUEMR_MODE_FAST_RX ++ | UCC_GUEMR_MODE_FAST_TX); ++ ++ /* Set GUMR, disable UCC both Rx and Tx, Ethernet protocol */ ++ out_be32(&uf_regs->gumr, UCC_FAST_GUMR_ETH); ++ ++ /* Set the Giga ethernet VFIFO stuff */ ++ if (uf_info->eth_type == GIGA_ETH) { ++ /* Allocate memory for Tx Virtual Fifo */ ++ uccf->ucc_fast_tx_virtual_fifo_base_offset = ++ qe_muram_alloc(UCC_GETH_UTFS_GIGA_INIT, ++ UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); ++ ++ /* Allocate memory for Rx Virtual Fifo */ ++ uccf->ucc_fast_rx_virtual_fifo_base_offset = ++ qe_muram_alloc(UCC_GETH_URFS_GIGA_INIT + ++ UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD, ++ UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); ++ ++ /* utfb, urfb are offsets from MURAM base */ ++ out_be32(&uf_regs->utfb, ++ uccf->ucc_fast_tx_virtual_fifo_base_offset); ++ out_be32(&uf_regs->urfb, ++ uccf->ucc_fast_rx_virtual_fifo_base_offset); ++ ++ /* Set Virtual Fifo registers */ ++ out_be16(&uf_regs->urfs, UCC_GETH_URFS_GIGA_INIT); ++ out_be16(&uf_regs->urfet, UCC_GETH_URFET_GIGA_INIT); ++ out_be16(&uf_regs->urfset, UCC_GETH_URFSET_GIGA_INIT); ++ out_be16(&uf_regs->utfs, UCC_GETH_UTFS_GIGA_INIT); ++ out_be16(&uf_regs->utfet, UCC_GETH_UTFET_GIGA_INIT); ++ out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_GIGA_INIT); ++ } ++ ++ /* Set the Fast ethernet VFIFO stuff */ ++ if (uf_info->eth_type == FAST_ETH) { ++ /* Allocate memory for Tx Virtual Fifo */ ++ uccf->ucc_fast_tx_virtual_fifo_base_offset = ++ qe_muram_alloc(UCC_GETH_UTFS_INIT, ++ UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); ++ ++ /* Allocate memory for Rx Virtual Fifo */ ++ uccf->ucc_fast_rx_virtual_fifo_base_offset = ++ qe_muram_alloc(UCC_GETH_URFS_INIT + ++ UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD, ++ UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); ++ ++ /* utfb, urfb are offsets from MURAM base */ ++ out_be32(&uf_regs->utfb, ++ uccf->ucc_fast_tx_virtual_fifo_base_offset); ++ out_be32(&uf_regs->urfb, ++ uccf->ucc_fast_rx_virtual_fifo_base_offset); ++ ++ /* Set Virtual Fifo registers */ ++ out_be16(&uf_regs->urfs, UCC_GETH_URFS_INIT); ++ out_be16(&uf_regs->urfet, UCC_GETH_URFET_INIT); ++ out_be16(&uf_regs->urfset, UCC_GETH_URFSET_INIT); ++ out_be16(&uf_regs->utfs, UCC_GETH_UTFS_INIT); ++ out_be16(&uf_regs->utfet, UCC_GETH_UTFET_INIT); ++ out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_INIT); ++ } ++ ++ /* Rx clock routing */ ++ if (uf_info->rx_clock != QE_CLK_NONE) { ++ if (ucc_set_clk_src(uf_info->ucc_num, ++ uf_info->rx_clock, COMM_DIR_RX)) { ++ printf("%s: Illegal value for parameter 'RxClock'.\n", ++ __FUNCTION__); ++ return -EINVAL; ++ } ++ } ++ ++ /* Tx clock routing */ ++ if (uf_info->tx_clock != QE_CLK_NONE) { ++ if (ucc_set_clk_src(uf_info->ucc_num, ++ uf_info->tx_clock, COMM_DIR_TX)) { ++ printf("%s: Illegal value for parameter 'TxClock'.\n", ++ __FUNCTION__); ++ return -EINVAL; ++ } ++ } ++ ++ /* Clear interrupt mask register to disable all of interrupts */ ++ out_be32(&uf_regs->uccm, 0x0); ++ ++ /* Writing '1' to clear all of envents */ ++ out_be32(&uf_regs->ucce, 0xffffffff); ++ ++ *uccf_ret = uccf; ++ return 0; ++} ++#endif /* CONFIG_QE */ +diff -Naupr u-boot-1.1.6/drivers/qe/uccf.h u-boot-1.1.6-fsl-1/drivers/qe/uccf.h +--- u-boot-1.1.6/drivers/qe/uccf.h 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/drivers/qe/uccf.h 2006-11-10 11:24:29.000000000 -0600 +@@ -0,0 +1,130 @@ ++/* ++ * Copyright (C) 2006 Freescale Semiconductor, Inc. ++ * ++ * Dave Liu ++ * based on source code of Shlomi Gridish ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __UCCF_H__ ++#define __UCCF_H__ ++ ++#include "common.h" ++#include "qe.h" ++ ++/* Fast or Giga ethernet ++*/ ++typedef enum enet_type { ++ FAST_ETH, ++ GIGA_ETH, ++} enet_type_e; ++ ++/* General UCC Extended Mode Register ++*/ ++#define UCC_GUEMR_MODE_MASK_RX 0x02 ++#define UCC_GUEMR_MODE_MASK_TX 0x01 ++#define UCC_GUEMR_MODE_FAST_RX 0x02 ++#define UCC_GUEMR_MODE_FAST_TX 0x01 ++#define UCC_GUEMR_MODE_SLOW_RX 0x00 ++#define UCC_GUEMR_MODE_SLOW_TX 0x00 ++#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 must be set 1 */ ++ ++/* General UCC FAST Mode Register ++*/ ++#define UCC_FAST_GUMR_TCI 0x20000000 ++#define UCC_FAST_GUMR_TRX 0x10000000 ++#define UCC_FAST_GUMR_TTX 0x08000000 ++#define UCC_FAST_GUMR_CDP 0x04000000 ++#define UCC_FAST_GUMR_CTSP 0x02000000 ++#define UCC_FAST_GUMR_CDS 0x01000000 ++#define UCC_FAST_GUMR_CTSS 0x00800000 ++#define UCC_FAST_GUMR_TXSY 0x00020000 ++#define UCC_FAST_GUMR_RSYN 0x00010000 ++#define UCC_FAST_GUMR_RTSM 0x00002000 ++#define UCC_FAST_GUMR_REVD 0x00000400 ++#define UCC_FAST_GUMR_ENR 0x00000020 ++#define UCC_FAST_GUMR_ENT 0x00000010 ++ ++/* GUMR [MODE] bit maps ++*/ ++#define UCC_FAST_GUMR_HDLC 0x00000000 ++#define UCC_FAST_GUMR_QMC 0x00000002 ++#define UCC_FAST_GUMR_UART 0x00000004 ++#define UCC_FAST_GUMR_BISYNC 0x00000008 ++#define UCC_FAST_GUMR_ATM 0x0000000a ++#define UCC_FAST_GUMR_ETH 0x0000000c ++ ++/* Transmit On Demand (UTORD) ++*/ ++#define UCC_SLOW_TOD 0x8000 ++#define UCC_FAST_TOD 0x8000 ++ ++/* Fast Ethernet (10/100 Mbps) ++*/ ++#define UCC_GETH_URFS_INIT 512 /* Rx virtual FIFO size */ ++#define UCC_GETH_URFET_INIT 256 /* 1/2 urfs */ ++#define UCC_GETH_URFSET_INIT 384 /* 3/4 urfs */ ++#define UCC_GETH_UTFS_INIT 512 /* Tx virtual FIFO size */ ++#define UCC_GETH_UTFET_INIT 256 /* 1/2 utfs */ ++#define UCC_GETH_UTFTT_INIT 128 ++ ++/* Gigabit Ethernet (1000 Mbps) ++*/ ++#define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/ /* Rx virtual FIFO size */ ++#define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/ /* 1/2 urfs */ ++#define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/ /* 3/4 urfs */ ++#define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/ /* Tx virtual FIFO size */ ++#define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/ /* 1/2 utfs */ ++#define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/ /* */ ++ ++/* UCC fast alignment ++*/ ++#define UCC_FAST_RX_ALIGN 4 ++#define UCC_FAST_MRBLR_ALIGNMENT 4 ++#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8 ++ ++/* Sizes ++*/ ++#define UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD 8 ++ ++/* UCC fast structure. ++*/ ++typedef struct ucc_fast_info { ++ int ucc_num; ++ qe_clock_e rx_clock; ++ qe_clock_e tx_clock; ++ enet_type_e eth_type; ++} ucc_fast_info_t; ++ ++typedef struct ucc_fast_private { ++ ucc_fast_info_t *uf_info; ++ ucc_fast_t *uf_regs; /* a pointer to memory map of UCC regs */ ++ u32 *p_ucce; /* a pointer to the event register */ ++ u32 *p_uccm; /* a pointer to the mask register */ ++ int enabled_tx; /* whether UCC is enabled for Tx (ENT) */ ++ int enabled_rx; /* whether UCC is enabled for Rx (ENR) */ ++ u32 ucc_fast_tx_virtual_fifo_base_offset; ++ u32 ucc_fast_rx_virtual_fifo_base_offset; ++} ucc_fast_private_t; ++ ++void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf); ++u32 ucc_fast_get_qe_cr_subblock(int ucc_num); ++void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode); ++void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode); ++int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret); ++ ++#endif /* __UCCF_H__ */ +diff -Naupr u-boot-1.1.6/drivers/qe/uec.c u-boot-1.1.6-fsl-1/drivers/qe/uec.c +--- u-boot-1.1.6/drivers/qe/uec.c 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/drivers/qe/uec.c 2006-11-10 11:24:29.000000000 -0600 +@@ -0,0 +1,1266 @@ ++/* ++ * Copyright (C) 2006 Freescale Semiconductor, Inc. ++ * ++ * Dave Liu ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include "common.h" ++#include "net.h" ++#include "malloc.h" ++#include "asm/errno.h" ++#include "asm/io.h" ++#include "asm/immap_qe.h" ++#include "qe.h" ++#include "uccf.h" ++#include "uec.h" ++#include "uec_phy.h" ++ ++#if defined(CONFIG_QE) ++ ++#ifdef CONFIG_UEC_ETH1 ++static uec_info_t eth1_uec_info = { ++ .uf_info = { ++ .ucc_num = CFG_UEC1_UCC_NUM, ++ .rx_clock = CFG_UEC1_RX_CLK, ++ .tx_clock = CFG_UEC1_TX_CLK, ++ .eth_type = CFG_UEC1_ETH_TYPE, ++ }, ++ .num_threads_tx = UEC_NUM_OF_THREADS_4, ++ .num_threads_rx = UEC_NUM_OF_THREADS_4, ++ .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, ++ .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, ++ .tx_bd_ring_len = 16, ++ .rx_bd_ring_len = 16, ++ .phy_address = CFG_UEC1_PHY_ADDR, ++ .enet_interface = CFG_UEC1_INTERFACE_MODE, ++}; ++#endif ++#ifdef CONFIG_UEC_ETH2 ++static uec_info_t eth2_uec_info = { ++ .uf_info = { ++ .ucc_num = CFG_UEC2_UCC_NUM, ++ .rx_clock = CFG_UEC2_RX_CLK, ++ .tx_clock = CFG_UEC2_TX_CLK, ++ .eth_type = CFG_UEC2_ETH_TYPE, ++ }, ++ .num_threads_tx = UEC_NUM_OF_THREADS_4, ++ .num_threads_rx = UEC_NUM_OF_THREADS_4, ++ .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, ++ .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, ++ .tx_bd_ring_len = 16, ++ .rx_bd_ring_len = 16, ++ .phy_address = CFG_UEC2_PHY_ADDR, ++ .enet_interface = CFG_UEC2_INTERFACE_MODE, ++}; ++#endif ++ ++static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode) ++{ ++ uec_t *uec_regs; ++ u32 maccfg1; ++ ++ if (!uec) { ++ printf("%s: uec not initial\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ uec_regs = uec->uec_regs; ++ ++ maccfg1 = in_be32(&uec_regs->maccfg1); ++ ++ if (mode & COMM_DIR_TX) { ++ maccfg1 |= MACCFG1_ENABLE_TX; ++ out_be32(&uec_regs->maccfg1, maccfg1); ++ uec->mac_tx_enabled = 1; ++ } ++ ++ if (mode & COMM_DIR_RX) { ++ maccfg1 |= MACCFG1_ENABLE_RX; ++ out_be32(&uec_regs->maccfg1, maccfg1); ++ uec->mac_rx_enabled = 1; ++ } ++ ++ return 0; ++} ++ ++static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode) ++{ ++ uec_t *uec_regs; ++ u32 maccfg1; ++ ++ if (!uec) { ++ printf("%s: uec not initial\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ uec_regs = uec->uec_regs; ++ ++ maccfg1 = in_be32(&uec_regs->maccfg1); ++ ++ if (mode & COMM_DIR_TX) { ++ maccfg1 &= ~MACCFG1_ENABLE_TX; ++ out_be32(&uec_regs->maccfg1, maccfg1); ++ uec->mac_tx_enabled = 0; ++ } ++ ++ if (mode & COMM_DIR_RX) { ++ maccfg1 &= ~MACCFG1_ENABLE_RX; ++ out_be32(&uec_regs->maccfg1, maccfg1); ++ uec->mac_rx_enabled = 0; ++ } ++ ++ return 0; ++} ++ ++static int uec_graceful_stop_tx(uec_private_t *uec) ++{ ++ ucc_fast_t *uf_regs; ++ u32 cecr_subblock; ++ u32 ucce; ++ ++ if (!uec || !uec->uccf) { ++ printf("%s: No handle passed.\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ uf_regs = uec->uccf->uf_regs; ++ ++ /* Clear the grace stop event */ ++ out_be32(&uf_regs->ucce, UCCE_GRA); ++ ++ /* Issue host command */ ++ cecr_subblock = ++ ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); ++ qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock, ++ (u8)QE_CR_PROTOCOL_ETHERNET, 0); ++ ++ /* Wait for command to complete */ ++ do { ++ ucce = in_be32(&uf_regs->ucce); ++ } while (! (ucce & UCCE_GRA)); ++ ++ uec->grace_stopped_tx = 1; ++ ++ return 0; ++} ++ ++static int uec_graceful_stop_rx(uec_private_t *uec) ++{ ++ u32 cecr_subblock; ++ u8 ack; ++ ++ if (!uec) { ++ printf("%s: No handle passed.\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ if (!uec->p_rx_glbl_pram) { ++ printf("%s: No init rx global parameter\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ /* Clear acknowledge bit */ ++ ack = uec->p_rx_glbl_pram->rxgstpack; ++ ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX; ++ uec->p_rx_glbl_pram->rxgstpack = ack; ++ ++ /* Keep issuing cmd and checking ack bit until it is asserted */ ++ do { ++ /* Issue host command */ ++ cecr_subblock = ++ ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); ++ qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock, ++ (u8)QE_CR_PROTOCOL_ETHERNET, 0); ++ ack = uec->p_rx_glbl_pram->rxgstpack; ++ } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX )); ++ ++ uec->grace_stopped_rx = 1; ++ ++ return 0; ++} ++ ++static int uec_restart_tx(uec_private_t *uec) ++{ ++ u32 cecr_subblock; ++ ++ if (!uec || !uec->uec_info) { ++ printf("%s: No handle passed.\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ cecr_subblock = ++ ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); ++ qe_issue_cmd(QE_RESTART_TX, cecr_subblock, ++ (u8)QE_CR_PROTOCOL_ETHERNET, 0); ++ ++ uec->grace_stopped_tx = 0; ++ ++ return 0; ++} ++ ++static int uec_restart_rx(uec_private_t *uec) ++{ ++ u32 cecr_subblock; ++ ++ if (!uec || !uec->uec_info) { ++ printf("%s: No handle passed.\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ cecr_subblock = ++ ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); ++ qe_issue_cmd(QE_RESTART_RX, cecr_subblock, ++ (u8)QE_CR_PROTOCOL_ETHERNET, 0); ++ ++ uec->grace_stopped_rx = 0; ++ ++ return 0; ++} ++ ++static int uec_open(uec_private_t *uec, comm_dir_e mode) ++{ ++ ucc_fast_private_t *uccf; ++ ++ if (!uec || !uec->uccf) { ++ printf("%s: No handle passed.\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ uccf = uec->uccf; ++ ++ /* check if the UCC number is in range. */ ++ if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) { ++ printf("%s: ucc_num out of range.\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ /* Enable MAC */ ++ uec_mac_enable(uec, mode); ++ ++ /* Enable UCC fast */ ++ ucc_fast_enable(uccf, mode); ++ ++ /* RISC microcode start */ ++ if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) { ++ uec_restart_tx(uec); ++ } ++ if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) { ++ uec_restart_rx(uec); ++ } ++ ++ return 0; ++} ++ ++static int uec_stop(uec_private_t *uec, comm_dir_e mode) ++{ ++ ucc_fast_private_t *uccf; ++ ++ if (!uec || !uec->uccf) { ++ printf("%s: No handle passed.\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ uccf = uec->uccf; ++ ++ /* check if the UCC number is in range. */ ++ if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) { ++ printf("%s: ucc_num out of range.\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ /* Stop any transmissions */ ++ if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) { ++ uec_graceful_stop_tx(uec); ++ } ++ /* Stop any receptions */ ++ if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) { ++ uec_graceful_stop_rx(uec); ++ } ++ ++ /* Disable the UCC fast */ ++ ucc_fast_disable(uec->uccf, mode); ++ ++ /* Disable the MAC */ ++ uec_mac_disable(uec, mode); ++ ++ return 0; ++} ++ ++static int uec_set_mac_duplex(uec_private_t *uec, int duplex) ++{ ++ uec_t *uec_regs; ++ u32 maccfg2; ++ ++ if (!uec) { ++ printf("%s: uec not initial\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ uec_regs = uec->uec_regs; ++ ++ if (duplex == DUPLEX_HALF) { ++ maccfg2 = in_be32(&uec_regs->maccfg2); ++ maccfg2 &= ~MACCFG2_FDX; ++ out_be32(&uec_regs->maccfg2, maccfg2); ++ } ++ ++ if (duplex == DUPLEX_FULL) { ++ maccfg2 = in_be32(&uec_regs->maccfg2); ++ maccfg2 |= MACCFG2_FDX; ++ out_be32(&uec_regs->maccfg2, maccfg2); ++ } ++ ++ return 0; ++} ++ ++static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode) ++{ ++ enet_interface_e enet_if_mode; ++ uec_info_t *uec_info; ++ uec_t *uec_regs; ++ u32 upsmr; ++ u32 maccfg2; ++ ++ if (!uec) { ++ printf("%s: uec not initial\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ uec_info = uec->uec_info; ++ uec_regs = uec->uec_regs; ++ enet_if_mode = if_mode; ++ ++ maccfg2 = in_be32(&uec_regs->maccfg2); ++ maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK; ++ ++ upsmr = in_be32(&uec->uccf->uf_regs->upsmr); ++ upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM); ++ ++ switch (enet_if_mode) { ++ case ENET_100_MII: ++ case ENET_10_MII: ++ maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; ++ break; ++ case ENET_1000_GMII: ++ maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; ++ break; ++ case ENET_1000_TBI: ++ maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; ++ upsmr |= UPSMR_TBIM; ++ break; ++ case ENET_1000_RTBI: ++ maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; ++ upsmr |= (UPSMR_RPM | UPSMR_TBIM); ++ break; ++ case ENET_1000_RGMII: ++ maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; ++ upsmr |= UPSMR_RPM; ++ break; ++ case ENET_100_RGMII: ++ maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; ++ upsmr |= UPSMR_RPM; ++ break; ++ case ENET_10_RGMII: ++ maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; ++ upsmr |= (UPSMR_RPM | UPSMR_R10M); ++ break; ++ case ENET_100_RMII: ++ maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; ++ upsmr |= UPSMR_RMM; ++ break; ++ case ENET_10_RMII: ++ maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; ++ upsmr |= (UPSMR_R10M | UPSMR_RMM); ++ break; ++ default: ++ return -EINVAL; ++ break; ++ } ++ out_be32(&uec_regs->maccfg2, maccfg2); ++ out_be32(&uec->uccf->uf_regs->upsmr, upsmr); ++ ++ return 0; ++} ++ ++static int init_mii_management_configuration(uec_t *uec_regs) ++{ ++ uint timeout = 0x1000; ++ u32 miimcfg = 0; ++ ++ miimcfg = in_be32(&uec_regs->miimcfg); ++ miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE; ++ out_be32(&uec_regs->miimcfg, miimcfg); ++ ++ /* Wait until the bus is free */ ++ while ((in_be32(&uec_regs->miimcfg) & MIIMIND_BUSY) && timeout--); ++ if (timeout <= 0) { ++ printf("%s: The MII Bus is stuck!", __FUNCTION__); ++ return -ETIMEDOUT; ++ } ++ ++ return 0; ++} ++ ++static int init_phy(struct eth_device *dev) ++{ ++ uec_private_t *uec; ++ uec_t *uec_regs; ++ struct uec_mii_info *mii_info; ++ struct phy_info *curphy; ++ int err; ++ ++ uec = (uec_private_t *)dev->priv; ++ uec_regs = uec->uec_regs; ++ ++ uec->oldlink = 0; ++ uec->oldspeed = 0; ++ uec->oldduplex = -1; ++ ++ mii_info = malloc(sizeof(*mii_info)); ++ if (!mii_info) { ++ printf("%s: Could not allocate mii_info", dev->name); ++ return -ENOMEM; ++ } ++ memset(mii_info, 0, sizeof(*mii_info)); ++ ++ mii_info->speed = SPEED_1000; ++ mii_info->duplex = DUPLEX_FULL; ++ mii_info->pause = 0; ++ mii_info->link = 1; ++ ++ mii_info->advertising = (ADVERTISED_10baseT_Half | ++ ADVERTISED_10baseT_Full | ++ ADVERTISED_100baseT_Half | ++ ADVERTISED_100baseT_Full | ++ ADVERTISED_1000baseT_Full); ++ mii_info->autoneg = 1; ++ mii_info->mii_id = uec->uec_info->phy_address; ++ mii_info->dev = dev; ++ ++ mii_info->mdio_read = &read_phy_reg; ++ mii_info->mdio_write = &write_phy_reg; ++ ++ uec->mii_info = mii_info; ++ ++ if (init_mii_management_configuration(uec_regs)) { ++ printf("%s: The MII Bus is stuck!", dev->name); ++ err = -1; ++ goto bus_fail; ++ } ++ ++ /* get info for this PHY */ ++ curphy = get_phy_info(uec->mii_info); ++ if (!curphy) { ++ printf("%s: No PHY found", dev->name); ++ err = -1; ++ goto no_phy; ++ } ++ ++ mii_info->phyinfo = curphy; ++ ++ /* Run the commands which initialize the PHY */ ++ if (curphy->init) { ++ err = curphy->init(uec->mii_info); ++ if (err) ++ goto phy_init_fail; ++ } ++ ++ return 0; ++ ++phy_init_fail: ++no_phy: ++bus_fail: ++ free(mii_info); ++ return err; ++} ++ ++static void adjust_link(struct eth_device *dev) ++{ ++ uec_private_t *uec = (uec_private_t *)dev->priv; ++ uec_t *uec_regs; ++ struct uec_mii_info *mii_info = uec->mii_info; ++ ++ extern void change_phy_interface_mode(struct eth_device *dev, ++ enet_interface_e mode); ++ uec_regs = uec->uec_regs; ++ ++ if (mii_info->link) { ++ /* Now we make sure that we can be in full duplex mode. ++ * If not, we operate in half-duplex mode. */ ++ if (mii_info->duplex != uec->oldduplex) { ++ if (!(mii_info->duplex)) { ++ uec_set_mac_duplex(uec, DUPLEX_HALF); ++ printf("%s: Half Duplex\n", dev->name); ++ } else { ++ uec_set_mac_duplex(uec, DUPLEX_FULL); ++ printf("%s: Full Duplex\n", dev->name); ++ } ++ uec->oldduplex = mii_info->duplex; ++ } ++ ++ if (mii_info->speed != uec->oldspeed) { ++ switch (mii_info->speed) { ++ case 1000: ++ break; ++ case 100: ++ printf ("switching to rgmii 100\n"); ++ /* change phy to rgmii 100 */ ++ change_phy_interface_mode(dev, ++ ENET_100_RGMII); ++ /* change the MAC interface mode */ ++ uec_set_mac_if_mode(uec,ENET_100_RGMII); ++ break; ++ case 10: ++ printf ("switching to rgmii 10\n"); ++ /* change phy to rgmii 10 */ ++ change_phy_interface_mode(dev, ++ ENET_10_RGMII); ++ /* change the MAC interface mode */ ++ uec_set_mac_if_mode(uec,ENET_10_RGMII); ++ break; ++ default: ++ printf("%s: Ack,Speed(%d)is illegal\n", ++ dev->name, mii_info->speed); ++ break; ++ } ++ ++ printf("%s: Speed %dBT\n", dev->name, mii_info->speed); ++ uec->oldspeed = mii_info->speed; ++ } ++ ++ if (!uec->oldlink) { ++ printf("%s: Link is up\n", dev->name); ++ uec->oldlink = 1; ++ } ++ ++ } else { /* if (mii_info->link) */ ++ if (uec->oldlink) { ++ printf("%s: Link is down\n", dev->name); ++ uec->oldlink = 0; ++ uec->oldspeed = 0; ++ uec->oldduplex = -1; ++ } ++ } ++} ++ ++static void phy_change(struct eth_device *dev) ++{ ++ uec_private_t *uec = (uec_private_t *)dev->priv; ++ uec_t *uec_regs; ++ int result = 0; ++ ++ uec_regs = uec->uec_regs; ++ ++ /* Delay 5s to give the PHY a chance to change the register state */ ++ udelay(5000000); ++ ++ /* Update the link, speed, duplex */ ++ result = uec->mii_info->phyinfo->read_status(uec->mii_info); ++ ++ /* Adjust the interface according to speed */ ++ if ((0 == result) || (uec->mii_info->link == 0)) { ++ adjust_link(dev); ++ } ++} ++ ++static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr) ++{ ++ uec_t *uec_regs; ++ u32 mac_addr1; ++ u32 mac_addr2; ++ ++ if (!uec) { ++ printf("%s: uec not initial\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ uec_regs = uec->uec_regs; ++ ++ /* if a station address of 0x12345678ABCD, perform a write to ++ MACSTNADDR1 of 0xCDAB7856, ++ MACSTNADDR2 of 0x34120000 */ ++ ++ mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \ ++ (mac_addr[3] << 8) | (mac_addr[2]); ++ out_be32(&uec_regs->macstnaddr1, mac_addr1); ++ ++ mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000; ++ out_be32(&uec_regs->macstnaddr2, mac_addr2); ++ ++ return 0; ++} ++ ++static int uec_convert_threads_num(uec_num_of_threads_e threads_num, ++ int *threads_num_ret) ++{ ++ int num_threads_numerica; ++ ++ switch (threads_num) { ++ case UEC_NUM_OF_THREADS_1: ++ num_threads_numerica = 1; ++ break; ++ case UEC_NUM_OF_THREADS_2: ++ num_threads_numerica = 2; ++ break; ++ case UEC_NUM_OF_THREADS_4: ++ num_threads_numerica = 4; ++ break; ++ case UEC_NUM_OF_THREADS_6: ++ num_threads_numerica = 6; ++ break; ++ case UEC_NUM_OF_THREADS_8: ++ num_threads_numerica = 8; ++ break; ++ default: ++ printf("%s: Bad number of threads value.", ++ __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ *threads_num_ret = num_threads_numerica; ++ ++ return 0; ++} ++ ++static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx) ++{ ++ uec_info_t *uec_info; ++ u32 end_bd; ++ u8 bmrx = 0; ++ int i; ++ ++ uec_info = uec->uec_info; ++ ++ /* Alloc global Tx parameter RAM page */ ++ uec->tx_glbl_pram_offset = qe_muram_alloc( ++ sizeof(uec_tx_global_pram_t), ++ UEC_TX_GLOBAL_PRAM_ALIGNMENT); ++ uec->p_tx_glbl_pram = (uec_tx_global_pram_t *) ++ qe_muram_addr(uec->tx_glbl_pram_offset); ++ ++ /* Zero the global Tx prameter RAM */ ++ memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t)); ++ ++ /* Init global Tx parameter RAM */ ++ ++ /* TEMODER, RMON statistics disable, one Tx queue */ ++ out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE); ++ ++ /* SQPTR */ ++ uec->send_q_mem_reg_offset = qe_muram_alloc( ++ sizeof(uec_send_queue_qd_t), ++ UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT); ++ uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *) ++ qe_muram_addr(uec->send_q_mem_reg_offset); ++ out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset); ++ ++ /* Setup the table with TxBDs ring */ ++ end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1) ++ * SIZEOFBD; ++ out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base, ++ (u32)(uec->p_tx_bd_ring)); ++ out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address, ++ end_bd); ++ ++ /* Scheduler Base Pointer, we have only one Tx queue, no need it */ ++ out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0); ++ ++ /* TxRMON Base Pointer, TxRMON disable, we don't need it */ ++ out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0); ++ ++ /* TSTATE, global snooping, big endian, the CSB bus selected */ ++ bmrx = BMR_INIT_VALUE; ++ out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT)); ++ ++ /* IPH_Offset */ ++ for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) { ++ out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0); ++ } ++ ++ /* VTAG table */ ++ for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) { ++ out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0); ++ } ++ ++ /* TQPTR */ ++ uec->thread_dat_tx_offset = qe_muram_alloc( ++ num_threads_tx * sizeof(uec_thread_data_tx_t) + ++ 32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT); ++ ++ uec->p_thread_data_tx = (uec_thread_data_tx_t *) ++ qe_muram_addr(uec->thread_dat_tx_offset); ++ out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset); ++} ++ ++static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx) ++{ ++ u8 bmrx = 0; ++ int i; ++ uec_82xx_address_filtering_pram_t *p_af_pram; ++ ++ /* Allocate global Rx parameter RAM page */ ++ uec->rx_glbl_pram_offset = qe_muram_alloc( ++ sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT); ++ uec->p_rx_glbl_pram = (uec_rx_global_pram_t *) ++ qe_muram_addr(uec->rx_glbl_pram_offset); ++ ++ /* Zero Global Rx parameter RAM */ ++ memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t)); ++ ++ /* Init global Rx parameter RAM */ ++ /* REMODER, Extended feature mode disable, VLAN disable, ++ LossLess flow control disable, Receive firmware statisic disable, ++ Extended address parsing mode disable, One Rx queues, ++ Dynamic maximum/minimum frame length disable, IP checksum check ++ disable, IP address alignment disable ++ */ ++ out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE); ++ ++ /* RQPTR */ ++ uec->thread_dat_rx_offset = qe_muram_alloc( ++ num_threads_rx * sizeof(uec_thread_data_rx_t), ++ UEC_THREAD_DATA_ALIGNMENT); ++ uec->p_thread_data_rx = (uec_thread_data_rx_t *) ++ qe_muram_addr(uec->thread_dat_rx_offset); ++ out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset); ++ ++ /* Type_or_Len */ ++ out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072); ++ ++ /* RxRMON base pointer, we don't need it */ ++ out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0); ++ ++ /* IntCoalescingPTR, we don't need it, no interrupt */ ++ out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0); ++ ++ /* RSTATE, global snooping, big endian, the CSB bus selected */ ++ bmrx = BMR_INIT_VALUE; ++ out_8(&uec->p_rx_glbl_pram->rstate, bmrx); ++ ++ /* MRBLR */ ++ out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN); ++ ++ /* RBDQPTR */ ++ uec->rx_bd_qs_tbl_offset = qe_muram_alloc( ++ sizeof(uec_rx_bd_queues_entry_t) + \ ++ sizeof(uec_rx_prefetched_bds_t), ++ UEC_RX_BD_QUEUES_ALIGNMENT); ++ uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *) ++ qe_muram_addr(uec->rx_bd_qs_tbl_offset); ++ ++ /* Zero it */ ++ memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \ ++ sizeof(uec_rx_prefetched_bds_t)); ++ out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset); ++ out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr, ++ (u32)uec->p_rx_bd_ring); ++ ++ /* MFLR */ ++ out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN); ++ /* MINFLR */ ++ out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN); ++ /* MAXD1 */ ++ out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN); ++ /* MAXD2 */ ++ out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN); ++ /* ECAM_PTR */ ++ out_be32(&uec->p_rx_glbl_pram->ecamptr, 0); ++ /* L2QT */ ++ out_be32(&uec->p_rx_glbl_pram->l2qt, 0); ++ /* L3QT */ ++ for (i = 0; i < 8; i++) { ++ out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0); ++ } ++ ++ /* VLAN_TYPE */ ++ out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100); ++ /* TCI */ ++ out_be16(&uec->p_rx_glbl_pram->vlantci, 0); ++ ++ /* Clear PQ2 style address filtering hash table */ ++ p_af_pram = (uec_82xx_address_filtering_pram_t *) \ ++ uec->p_rx_glbl_pram->addressfiltering; ++ ++ p_af_pram->iaddr_h = 0; ++ p_af_pram->iaddr_l = 0; ++ p_af_pram->gaddr_h = 0; ++ p_af_pram->gaddr_l = 0; ++} ++ ++static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec, ++ int thread_tx, int thread_rx) ++{ ++ uec_init_cmd_pram_t *p_init_enet_param; ++ u32 init_enet_param_offset; ++ uec_info_t *uec_info; ++ int i; ++ int snum; ++ u32 init_enet_offset; ++ u32 entry_val; ++ u32 command; ++ u32 cecr_subblock; ++ ++ uec_info = uec->uec_info; ++ ++ /* Allocate init enet command parameter */ ++ uec->init_enet_param_offset = qe_muram_alloc( ++ sizeof(uec_init_cmd_pram_t), 4); ++ init_enet_param_offset = uec->init_enet_param_offset; ++ uec->p_init_enet_param = (uec_init_cmd_pram_t *) ++ qe_muram_addr(uec->init_enet_param_offset); ++ ++ /* Zero init enet command struct */ ++ memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t)); ++ ++ /* Init the command struct */ ++ p_init_enet_param = uec->p_init_enet_param; ++ p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0; ++ p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1; ++ p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2; ++ p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3; ++ p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4; ++ p_init_enet_param->largestexternallookupkeysize = 0; ++ ++ p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx) ++ << ENET_INIT_PARAM_RGF_SHIFT; ++ p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx) ++ << ENET_INIT_PARAM_TGF_SHIFT; ++ ++ /* Init Rx global parameter pointer */ ++ p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset | ++ (u32)uec_info->riscRx; ++ ++ /* Init Rx threads */ ++ for (i = 0; i < (thread_rx + 1); i++) { ++ if ((snum = qe_get_snum()) < 0) { ++ printf("%s can not get snum\n", __FUNCTION__); ++ return -ENOMEM; ++ } ++ ++ if (i==0) { ++ init_enet_offset = 0; ++ } else { ++ init_enet_offset = qe_muram_alloc( ++ sizeof(uec_thread_rx_pram_t), ++ UEC_THREAD_RX_PRAM_ALIGNMENT); ++ } ++ ++ entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) | ++ init_enet_offset | (u32)uec_info->riscRx; ++ p_init_enet_param->rxthread[i] = entry_val; ++ } ++ ++ /* Init Tx global parameter pointer */ ++ p_init_enet_param->txglobal = uec->tx_glbl_pram_offset | ++ (u32)uec_info->riscTx; ++ ++ /* Init Tx threads */ ++ for (i = 0; i < thread_tx; i++) { ++ if ((snum = qe_get_snum()) < 0) { ++ printf("%s can not get snum\n", __FUNCTION__); ++ return -ENOMEM; ++ } ++ ++ init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t), ++ UEC_THREAD_TX_PRAM_ALIGNMENT); ++ ++ entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) | ++ init_enet_offset | (u32)uec_info->riscTx; ++ p_init_enet_param->txthread[i] = entry_val; ++ } ++ ++ __asm__ __volatile__("sync"); ++ ++ /* Issue QE command */ ++ command = QE_INIT_TX_RX; ++ cecr_subblock = ucc_fast_get_qe_cr_subblock( ++ uec->uec_info->uf_info.ucc_num); ++ qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET, ++ init_enet_param_offset); ++ ++ return 0; ++} ++ ++static int uec_startup(uec_private_t *uec) ++{ ++ uec_info_t *uec_info; ++ ucc_fast_info_t *uf_info; ++ ucc_fast_private_t *uccf; ++ ucc_fast_t *uf_regs; ++ uec_t *uec_regs; ++ int num_threads_tx; ++ int num_threads_rx; ++ u32 utbipar; ++ enet_interface_e enet_interface; ++ u32 length; ++ u32 align; ++ qe_bd_t *bd; ++ u8 *buf; ++ int i; ++ ++ if (!uec || !uec->uec_info) { ++ printf("%s: uec or uec_info not initial\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ uec_info = uec->uec_info; ++ uf_info = &(uec_info->uf_info); ++ ++ /* Check if Rx BD ring len is illegal */ ++ if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \ ++ (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) { ++ printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n", ++ __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ /* Check if Tx BD ring len is illegal */ ++ if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) { ++ printf("%s: Tx BD ring length must not be smaller than 2.\n", ++ __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ /* Check if MRBLR is illegal */ ++ if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN % UEC_MRBLR_ALIGNMENT)) { ++ printf("%s: max rx buffer length must be mutliple of 128.\n", ++ __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ /* Both Rx and Tx are stopped */ ++ uec->grace_stopped_rx = 1; ++ uec->grace_stopped_tx = 1; ++ ++ /* Init UCC fast */ ++ if (ucc_fast_init(uf_info, &uccf)) { ++ printf("%s: failed to init ucc fast\n", __FUNCTION__); ++ return -ENOMEM; ++ } ++ ++ /* Save uccf */ ++ uec->uccf = uccf; ++ ++ /* Convert the Tx threads number */ ++ if (uec_convert_threads_num(uec_info->num_threads_tx, ++ &num_threads_tx)) { ++ return -EINVAL; ++ } ++ ++ /* Convert the Rx threads number */ ++ if (uec_convert_threads_num(uec_info->num_threads_rx, ++ &num_threads_rx)) { ++ return -EINVAL; ++ } ++ ++ uf_regs = uccf->uf_regs; ++ ++ /* UEC register is following UCC fast registers */ ++ uec_regs = (uec_t *)(&uf_regs->ucc_eth); ++ ++ /* Save the UEC register pointer to UEC private struct */ ++ uec->uec_regs = uec_regs; ++ ++ /* Init UPSMR, enable hardware statistics (UCC) */ ++ out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE); ++ ++ /* Init MACCFG1, flow control disable, disable Tx and Rx */ ++ out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE); ++ ++ /* Init MACCFG2, length check, MAC PAD and CRC enable */ ++ out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE); ++ ++ /* Setup MAC interface mode */ ++ uec_set_mac_if_mode(uec, uec_info->enet_interface); ++ ++ /* Setup MII master clock source */ ++ qe_set_mii_clk_src(uec_info->uf_info.ucc_num); ++ ++ /* Setup UTBIPAR */ ++ utbipar = in_be32(&uec_regs->utbipar); ++ utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK; ++ enet_interface = uec->uec_info->enet_interface; ++ if (enet_interface == ENET_1000_TBI || ++ enet_interface == ENET_1000_RTBI) { ++ utbipar |= (uec_info->phy_address + uec_info->uf_info.ucc_num) ++ << UTBIPAR_PHY_ADDRESS_SHIFT; ++ } else { ++ utbipar |= (0x10 + uec_info->uf_info.ucc_num) ++ << UTBIPAR_PHY_ADDRESS_SHIFT; ++ } ++ ++ out_be32(&uec_regs->utbipar, utbipar); ++ ++ /* Allocate Tx BDs */ ++ length = ((uec_info->tx_bd_ring_len * SIZEOFBD) / ++ UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) * ++ UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; ++ if ((uec_info->tx_bd_ring_len * SIZEOFBD) % ++ UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) { ++ length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; ++ } ++ ++ align = UEC_TX_BD_RING_ALIGNMENT; ++ uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align)); ++ if (uec->tx_bd_ring_offset != 0) { ++ uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align) ++ & ~(align - 1)); ++ } ++ ++ /* Zero all of Tx BDs */ ++ memset((void *)(uec->tx_bd_ring_offset), 0, length + align); ++ ++ /* Allocate Rx BDs */ ++ length = uec_info->rx_bd_ring_len * SIZEOFBD; ++ align = UEC_RX_BD_RING_ALIGNMENT; ++ uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align))); ++ if (uec->rx_bd_ring_offset != 0) { ++ uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align) ++ & ~(align - 1)); ++ } ++ ++ /* Zero all of Rx BDs */ ++ memset((void *)(uec->rx_bd_ring_offset), 0, length + align); ++ ++ /* Allocate Rx buffer */ ++ length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN; ++ align = UEC_RX_DATA_BUF_ALIGNMENT; ++ uec->rx_buf_offset = (u32)malloc(length + align); ++ if (uec->rx_buf_offset != 0) { ++ uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align) ++ & ~(align - 1)); ++ } ++ ++ /* Zero all of the Rx buffer */ ++ memset((void *)(uec->rx_buf_offset), 0, length + align); ++ ++ /* Init TxBD ring */ ++ bd = (qe_bd_t *)uec->p_tx_bd_ring; ++ uec->txBd = bd; ++ ++ for (i = 0; i < uec_info->tx_bd_ring_len; i++) { ++ BD_DATA_CLEAR(bd); ++ BD_STATUS_SET(bd, 0); ++ BD_LENGTH_SET(bd, 0); ++ bd ++; ++ } ++ BD_STATUS_SET((--bd), TxBD_WRAP); ++ ++ /* Init RxBD ring */ ++ bd = (qe_bd_t *)uec->p_rx_bd_ring; ++ uec->rxBd = bd; ++ buf = uec->p_rx_buf; ++ for (i = 0; i < uec_info->rx_bd_ring_len; i++) { ++ BD_DATA_SET(bd, buf); ++ BD_LENGTH_SET(bd, 0); ++ BD_STATUS_SET(bd, RxBD_EMPTY); ++ buf += MAX_RXBUF_LEN; ++ bd ++; ++ } ++ BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY); ++ ++ /* Init global Tx parameter RAM */ ++ uec_init_tx_parameter(uec, num_threads_tx); ++ ++ /* Init global Rx parameter RAM */ ++ uec_init_rx_parameter(uec, num_threads_rx); ++ ++ /* Init ethernet Tx and Rx parameter command */ ++ if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx, ++ num_threads_rx)) { ++ printf("%s issue init enet cmd failed\n", __FUNCTION__); ++ return -ENOMEM; ++ } ++ ++ return 0; ++} ++ ++static int uec_init(struct eth_device* dev, bd_t *bd) ++{ ++ uec_private_t *uec; ++ int err; ++ ++ uec = (uec_private_t *)dev->priv; ++ ++ if (uec->the_first_run == 0) { ++ /* Set up the MAC address */ ++ if (dev->enetaddr[0] & 0x01) { ++ printf("%s: MacAddress is multcast address\n", ++ __FUNCTION__); ++ return -EINVAL; ++ } ++ uec_set_mac_address(uec, dev->enetaddr); ++ uec->the_first_run = 1; ++ } ++ ++ err = uec_open(uec, COMM_DIR_RX_AND_TX); ++ if (err) { ++ printf("%s: cannot enable UEC device\n", dev->name); ++ return err; ++ } ++ ++ return 0; ++} ++ ++static void uec_halt(struct eth_device* dev) ++{ ++ uec_private_t *uec = (uec_private_t *)dev->priv; ++ uec_stop(uec, COMM_DIR_RX_AND_TX); ++} ++ ++static int uec_send(struct eth_device* dev, volatile void *buf, int len) ++{ ++ uec_private_t *uec; ++ ucc_fast_private_t *uccf; ++ volatile qe_bd_t *bd; ++ volatile u16 status; ++ int i; ++ int result = 0; ++ ++ uec = (uec_private_t *)dev->priv; ++ uccf = uec->uccf; ++ bd = uec->txBd; ++ ++ /* Find an empty TxBD */ ++ for (i = 0; BD_STATUS(bd) & TxBD_READY; i++) { ++ if (i > 0x100000) { ++ printf("%s: tx buffer not ready\n", dev->name); ++ return result; ++ } ++ } ++ ++ /* Init TxBD */ ++ BD_DATA_SET(bd, buf); ++ BD_LENGTH_SET(bd, len); ++ status = BD_STATUS(bd); ++ status &= BD_WRAP; ++ status |= (TxBD_READY | TxBD_LAST); ++ BD_STATUS_SET(bd, status); ++ ++ /* Tell UCC to transmit the buffer */ ++ ucc_fast_transmit_on_demand(uccf); ++ ++ /* Wait for buffer to be transmitted */ ++ status = BD_STATUS(bd); ++ for (i = 0; status & TxBD_READY; i++) { ++ if (i > 0x100000) { ++ printf("%s: tx error\n", dev->name); ++ return result; ++ } ++ status = BD_STATUS(bd); ++ } ++ ++ /* Ok, the buffer be transimitted */ ++ BD_ADVANCE(bd, status, uec->p_tx_bd_ring); ++ uec->txBd = bd; ++ result = 1; ++ ++ return result; ++} ++ ++static int uec_recv(struct eth_device* dev) ++{ ++ uec_private_t *uec = dev->priv; ++ volatile qe_bd_t *bd; ++ volatile u16 status; ++ u16 len; ++ u8 *data; ++ ++ bd = uec->rxBd; ++ status = BD_STATUS(bd); ++ ++ while (!(status & RxBD_EMPTY)) { ++ if (!(status & RxBD_ERROR)) { ++ data = BD_DATA(bd); ++ len = BD_LENGTH(bd); ++ NetReceive(data, len); ++ } else { ++ printf("%s: Rx error\n", dev->name); ++ } ++ status &= BD_CLEAN; ++ BD_LENGTH_SET(bd, 0); ++ BD_STATUS_SET(bd, status | RxBD_EMPTY); ++ BD_ADVANCE(bd, status, uec->p_rx_bd_ring); ++ status = BD_STATUS(bd); ++ } ++ uec->rxBd = bd; ++ ++ return 1; ++} ++ ++int uec_initialize(int index) ++{ ++ struct eth_device *dev; ++ int i; ++ uec_private_t *uec; ++ uec_info_t *uec_info; ++ int err; ++ ++ dev = (struct eth_device *)malloc(sizeof(struct eth_device)); ++ if (!dev) ++ return 0; ++ memset(dev, 0, sizeof(struct eth_device)); ++ ++ /* Allocate the UEC private struct */ ++ uec = (uec_private_t *)malloc(sizeof(uec_private_t)); ++ if (!uec) { ++ return -ENOMEM; ++ } ++ memset(uec, 0, sizeof(uec_private_t)); ++ ++ /* Init UEC private struct, they come from board.h */ ++ if (index == 0) { ++#ifdef CONFIG_UEC_ETH1 ++ uec_info = ð1_uec_info; ++#endif ++ } else if (index == 1) { ++#ifdef CONFIG_UEC_ETH2 ++ uec_info = ð2_uec_info; ++#endif ++ } else { ++ printf("%s: index is illegal.\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ uec->uec_info = uec_info; ++ ++ sprintf(dev->name, "FSL UEC%d", index); ++ dev->iobase = 0; ++ dev->priv = (void *)uec; ++ dev->init = uec_init; ++ dev->halt = uec_halt; ++ dev->send = uec_send; ++ dev->recv = uec_recv; ++ ++ /* Clear the ethnet address */ ++ for (i = 0; i < 6; i++) ++ dev->enetaddr[i] = 0; ++ ++ eth_register(dev); ++ ++ err = uec_startup(uec); ++ if (err) { ++ printf("%s: Cannot configure net device, aborting.",dev->name); ++ return err; ++ } ++ ++ err = init_phy(dev); ++ if (err) { ++ printf("%s: Cannot initialize PHY, aborting.\n", dev->name); ++ return err; ++ } ++ ++ phy_change(dev); ++ ++ return 1; ++} ++#endif /* CONFIG_QE */ +diff -Naupr u-boot-1.1.6/drivers/qe/uec.h u-boot-1.1.6-fsl-1/drivers/qe/uec.h +--- u-boot-1.1.6/drivers/qe/uec.h 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/drivers/qe/uec.h 2006-11-10 11:24:29.000000000 -0600 +@@ -0,0 +1,716 @@ ++/* ++ * Copyright (C) 2006 Freescale Semiconductor, Inc. ++ * ++ * Dave Liu ++ * based on source code of Shlomi Gridish ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __UEC_H__ ++#define __UEC_H__ ++ ++#define MAX_TX_THREADS 8 ++#define MAX_RX_THREADS 8 ++#define MAX_TX_QUEUES 8 ++#define MAX_RX_QUEUES 8 ++#define MAX_PREFETCHED_BDS 4 ++#define MAX_IPH_OFFSET_ENTRY 8 ++#define MAX_ENET_INIT_PARAM_ENTRIES_RX 9 ++#define MAX_ENET_INIT_PARAM_ENTRIES_TX 8 ++ ++/* UEC UPSMR (Protocol Specific Mode Register) ++ */ ++#define UPSMR_ECM 0x04000000 /* Enable CAM Miss */ ++#define UPSMR_HSE 0x02000000 /* Hardware Statistics Enable */ ++#define UPSMR_PRO 0x00400000 /* Promiscuous */ ++#define UPSMR_CAP 0x00200000 /* CAM polarity */ ++#define UPSMR_RSH 0x00100000 /* Receive Short Frames */ ++#define UPSMR_RPM 0x00080000 /* Reduced Pin Mode interfaces */ ++#define UPSMR_R10M 0x00040000 /* RGMII/RMII 10 Mode */ ++#define UPSMR_RLPB 0x00020000 /* RMII Loopback Mode */ ++#define UPSMR_TBIM 0x00010000 /* Ten-bit Interface Mode */ ++#define UPSMR_RMM 0x00001000 /* RMII/RGMII Mode */ ++#define UPSMR_CAM 0x00000400 /* CAM Address Matching */ ++#define UPSMR_BRO 0x00000200 /* Broadcast Address */ ++#define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */ ++ ++#define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1) ++ ++/* UEC MACCFG1 (MAC Configuration 1 Register) ++ */ ++#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */ ++#define MACCFG1_FLOW_TX 0x00000010 /* Flow Control Tx */ ++#define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Enable Rx Sync */ ++#define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */ ++#define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Enable Tx Sync */ ++#define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */ ++ ++#define MACCFG1_INIT_VALUE (0) ++ ++/* UEC MACCFG2 (MAC Configuration 2 Register) ++ */ ++#define MACCFG2_PREL 0x00007000 ++#define MACCFG2_PREL_SHIFT (31 - 19) ++#define MACCFG2_PREL_MASK 0x0000f000 ++#define MACCFG2_SRP 0x00000080 ++#define MACCFG2_STP 0x00000040 ++#define MACCFG2_RESERVED_1 0x00000020 /* must be set */ ++#define MACCFG2_LC 0x00000010 /* Length Check */ ++#define MACCFG2_MPE 0x00000008 ++#define MACCFG2_FDX 0x00000001 /* Full Duplex */ ++#define MACCFG2_FDX_MASK 0x00000001 ++#define MACCFG2_PAD_CRC 0x00000004 ++#define MACCFG2_CRC_EN 0x00000002 ++#define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000 ++#define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002 ++#define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004 ++#define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100 ++#define MACCFG2_INTERFACE_MODE_BYTE 0x00000200 ++#define MACCFG2_INTERFACE_MODE_MASK 0x00000300 ++ ++#define MACCFG2_INIT_VALUE (MACCFG2_PREL | MACCFG2_RESERVED_1 | \ ++ MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX) ++ ++/* UEC Event Register ++*/ ++#define UCCE_MPD 0x80000000 ++#define UCCE_SCAR 0x40000000 ++#define UCCE_GRA 0x20000000 ++#define UCCE_CBPR 0x10000000 ++#define UCCE_BSY 0x08000000 ++#define UCCE_RXC 0x04000000 ++#define UCCE_TXC 0x02000000 ++#define UCCE_TXE 0x01000000 ++#define UCCE_TXB7 0x00800000 ++#define UCCE_TXB6 0x00400000 ++#define UCCE_TXB5 0x00200000 ++#define UCCE_TXB4 0x00100000 ++#define UCCE_TXB3 0x00080000 ++#define UCCE_TXB2 0x00040000 ++#define UCCE_TXB1 0x00020000 ++#define UCCE_TXB0 0x00010000 ++#define UCCE_RXB7 0x00008000 ++#define UCCE_RXB6 0x00004000 ++#define UCCE_RXB5 0x00002000 ++#define UCCE_RXB4 0x00001000 ++#define UCCE_RXB3 0x00000800 ++#define UCCE_RXB2 0x00000400 ++#define UCCE_RXB1 0x00000200 ++#define UCCE_RXB0 0x00000100 ++#define UCCE_RXF7 0x00000080 ++#define UCCE_RXF6 0x00000040 ++#define UCCE_RXF5 0x00000020 ++#define UCCE_RXF4 0x00000010 ++#define UCCE_RXF3 0x00000008 ++#define UCCE_RXF2 0x00000004 ++#define UCCE_RXF1 0x00000002 ++#define UCCE_RXF0 0x00000001 ++ ++#define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \ ++ UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0) ++#define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \ ++ UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0) ++#define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \ ++ UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0) ++#define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY | \ ++ UCCE_RXC | UCCE_TXC | UCCE_TXE) ++ ++/* UEC TEMODR Register ++*/ ++#define TEMODER_SCHEDULER_ENABLE 0x2000 ++#define TEMODER_IP_CHECKSUM_GENERATE 0x0400 ++#define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200 ++#define TEMODER_RMON_STATISTICS 0x0100 ++#define TEMODER_NUM_OF_QUEUES_SHIFT (15-15) ++ ++#define TEMODER_INIT_VALUE 0xc000 ++ ++/* UEC REMODR Register ++*/ ++#define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000 ++#define REMODER_RX_EXTENDED_FEATURES 0x80000000 ++#define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 ) ++#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) ++#define REMODER_RX_QOS_MODE_SHIFT (31-15) ++#define REMODER_RMON_STATISTICS 0x00001000 ++#define REMODER_RX_EXTENDED_FILTERING 0x00000800 ++#define REMODER_NUM_OF_QUEUES_SHIFT (31-23) ++#define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008 ++#define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004 ++#define REMODER_IP_CHECKSUM_CHECK 0x00000002 ++#define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001 ++ ++#define REMODER_INIT_VALUE 0 ++ ++/* BMRx - Bus Mode Register */ ++#define BMR_GLB 0x20 ++#define BMR_BO_BE 0x10 ++#define BMR_DTB_SECONDARY_BUS 0x02 ++#define BMR_BDB_SECONDARY_BUS 0x01 ++ ++#define BMR_SHIFT 24 ++#define BMR_INIT_VALUE (BMR_GLB | BMR_BO_BE) ++ ++/* UEC UCCS (Ethernet Status Register) ++ */ ++#define UCCS_BPR 0x02 ++#define UCCS_PAU 0x02 ++#define UCCS_MPD 0x01 ++ ++/* UEC MIIMCFG (MII Management Configuration Register) ++ */ ++#define MIIMCFG_RESET_MANAGEMENT 0x80000000 ++#define MIIMCFG_NO_PREAMBLE 0x00000010 ++#define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31) ++#define MIIMCFG_CLOCK_DIVIDE_MASK 0x0000000f ++#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001 ++#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002 ++#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003 ++#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004 ++#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005 ++#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006 ++#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007 ++ ++#define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE \ ++ MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 ++ ++/* UEC MIIMCOM (MII Management Command Register) ++ */ ++#define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */ ++#define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */ ++ ++/* UEC MIIMADD (MII Management Address Register) ++ */ ++#define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23) ++#define MIIMADD_PHY_REGISTER_SHIFT (31 - 31) ++ ++/* UEC MIIMCON (MII Management Control Register) ++ */ ++#define MIIMCON_PHY_CONTROL_SHIFT (31 - 31) ++#define MIIMCON_PHY_STATUS_SHIFT (31 - 31) ++ ++/* UEC MIIMIND (MII Management Indicator Register) ++ */ ++#define MIIMIND_NOT_VALID 0x00000004 ++#define MIIMIND_SCAN 0x00000002 ++#define MIIMIND_BUSY 0x00000001 ++ ++/* UEC UTBIPAR (Ten Bit Interface Physical Address Register) ++ */ ++#define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31) ++#define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f ++ ++/* UEC UESCR (Ethernet Statistics Control Register) ++ */ ++#define UESCR_AUTOZ 0x8000 ++#define UESCR_CLRCNT 0x4000 ++#define UESCR_MAXCOV_SHIFT (15 - 7) ++#define UESCR_SCOV_SHIFT (15 - 15) ++ ++/****** Tx data struct collection ******/ ++/* Tx thread data, each Tx thread has one this struct. ++*/ ++typedef struct uec_thread_data_tx { ++ u8 res0[136]; ++} __attribute__ ((packed)) uec_thread_data_tx_t; ++ ++/* Tx thread parameter, each Tx thread has one this struct. ++*/ ++typedef struct uec_thread_tx_pram { ++ u8 res0[64]; ++} __attribute__ ((packed)) uec_thread_tx_pram_t; ++ ++/* Send queue queue-descriptor, each Tx queue has one this QD ++*/ ++typedef struct uec_send_queue_qd { ++ u32 bd_ring_base; /* pointer to BD ring base address */ ++ u8 res0[0x8]; ++ u32 last_bd_completed_address; /* last entry in BD ring */ ++ u8 res1[0x30]; ++} __attribute__ ((packed)) uec_send_queue_qd_t; ++ ++/* Send queue memory region */ ++typedef struct uec_send_queue_mem_region { ++ uec_send_queue_qd_t sqqd[MAX_TX_QUEUES]; ++} __attribute__ ((packed)) uec_send_queue_mem_region_t; ++ ++/* Scheduler struct ++*/ ++typedef struct uec_scheduler { ++ u16 cpucount0; /* CPU packet counter */ ++ u16 cpucount1; /* CPU packet counter */ ++ u16 cecount0; /* QE packet counter */ ++ u16 cecount1; /* QE packet counter */ ++ u16 cpucount2; /* CPU packet counter */ ++ u16 cpucount3; /* CPU packet counter */ ++ u16 cecount2; /* QE packet counter */ ++ u16 cecount3; /* QE packet counter */ ++ u16 cpucount4; /* CPU packet counter */ ++ u16 cpucount5; /* CPU packet counter */ ++ u16 cecount4; /* QE packet counter */ ++ u16 cecount5; /* QE packet counter */ ++ u16 cpucount6; /* CPU packet counter */ ++ u16 cpucount7; /* CPU packet counter */ ++ u16 cecount6; /* QE packet counter */ ++ u16 cecount7; /* QE packet counter */ ++ u32 weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */ ++ u32 rtsrshadow; /* temporary variable handled by QE */ ++ u32 time; /* temporary variable handled by QE */ ++ u32 ttl; /* temporary variable handled by QE */ ++ u32 mblinterval; /* max burst length interval */ ++ u16 nortsrbytetime; /* normalized value of byte time in tsr units */ ++ u8 fracsiz; ++ u8 res0[1]; ++ u8 strictpriorityq; /* Strict Priority Mask register */ ++ u8 txasap; /* Transmit ASAP register */ ++ u8 extrabw; /* Extra BandWidth register */ ++ u8 oldwfqmask; /* temporary variable handled by QE */ ++ u8 weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */ ++ u32 minw; /* temporary variable handled by QE */ ++ u8 res1[0x70-0x64]; ++} __attribute__ ((packed)) uec_scheduler_t; ++ ++/* Tx firmware counters ++*/ ++typedef struct uec_tx_firmware_statistics_pram { ++ u32 sicoltx; /* single collision */ ++ u32 mulcoltx; /* multiple collision */ ++ u32 latecoltxfr; /* late collision */ ++ u32 frabortduecol; /* frames aborted due to tx collision */ ++ u32 frlostinmactxer; /* frames lost due to internal MAC error tx */ ++ u32 carriersenseertx; /* carrier sense error */ ++ u32 frtxok; /* frames transmitted OK */ ++ u32 txfrexcessivedefer; ++ u32 txpkts256; /* total packets(including bad) 256~511 B */ ++ u32 txpkts512; /* total packets(including bad) 512~1023B */ ++ u32 txpkts1024; /* total packets(including bad) 1024~1518B */ ++ u32 txpktsjumbo; /* total packets(including bad) >1024 */ ++} __attribute__ ((packed)) uec_tx_firmware_statistics_pram_t; ++ ++/* Tx global parameter table ++*/ ++typedef struct uec_tx_global_pram { ++ u16 temoder; ++ u8 res0[0x38-0x02]; ++ u32 sqptr; ++ u32 schedulerbasepointer; ++ u32 txrmonbaseptr; ++ u32 tstate; ++ u8 iphoffset[MAX_IPH_OFFSET_ENTRY]; ++ u32 vtagtable[0x8]; ++ u32 tqptr; ++ u8 res2[0x80-0x74]; ++} __attribute__ ((packed)) uec_tx_global_pram_t; ++ ++ ++/****** Rx data struct collection ******/ ++/* Rx thread data, each Rx thread has one this struct. ++*/ ++typedef struct uec_thread_data_rx { ++ u8 res0[40]; ++} __attribute__ ((packed)) uec_thread_data_rx_t; ++ ++/* Rx thread parameter, each Rx thread has one this struct. ++*/ ++typedef struct uec_thread_rx_pram { ++ u8 res0[128]; ++} __attribute__ ((packed)) uec_thread_rx_pram_t; ++ ++/* Rx firmware counters ++*/ ++typedef struct uec_rx_firmware_statistics_pram { ++ u32 frrxfcser; /* frames with crc error */ ++ u32 fraligner; /* frames with alignment error */ ++ u32 inrangelenrxer; /* in range length error */ ++ u32 outrangelenrxer; /* out of range length error */ ++ u32 frtoolong; /* frame too long */ ++ u32 runt; /* runt */ ++ u32 verylongevent; /* very long event */ ++ u32 symbolerror; /* symbol error */ ++ u32 dropbsy; /* drop because of BD not ready */ ++ u8 res0[0x8]; ++ u32 mismatchdrop; /* drop because of MAC filtering */ ++ u32 underpkts; /* total frames less than 64 octets */ ++ u32 pkts256; /* total frames(including bad)256~511 B */ ++ u32 pkts512; /* total frames(including bad)512~1023 B */ ++ u32 pkts1024; /* total frames(including bad)1024~1518 B */ ++ u32 pktsjumbo; /* total frames(including bad) >1024 B */ ++ u32 frlossinmacer; ++ u32 pausefr; /* pause frames */ ++ u8 res1[0x4]; ++ u32 removevlan; ++ u32 replacevlan; ++ u32 insertvlan; ++} __attribute__ ((packed)) uec_rx_firmware_statistics_pram_t; ++ ++/* Rx interrupt coalescing entry, each Rx queue has one this entry. ++*/ ++typedef struct uec_rx_interrupt_coalescing_entry { ++ u32 maxvalue; ++ u32 counter; ++} __attribute__ ((packed)) uec_rx_interrupt_coalescing_entry_t; ++ ++typedef struct uec_rx_interrupt_coalescing_table { ++ uec_rx_interrupt_coalescing_entry_t entry[MAX_RX_QUEUES]; ++} __attribute__ ((packed)) uec_rx_interrupt_coalescing_table_t; ++ ++/* RxBD queue entry, each Rx queue has one this entry. ++*/ ++typedef struct uec_rx_bd_queues_entry { ++ u32 bdbaseptr; /* BD base pointer */ ++ u32 bdptr; /* BD pointer */ ++ u32 externalbdbaseptr; /* external BD base pointer */ ++ u32 externalbdptr; /* external BD pointer */ ++} __attribute__ ((packed)) uec_rx_bd_queues_entry_t; ++ ++/* Rx global paramter table ++*/ ++typedef struct uec_rx_global_pram { ++ u32 remoder; /* ethernet mode reg. */ ++ u32 rqptr; /* base pointer to the Rx Queues */ ++ u32 res0[0x1]; ++ u8 res1[0x20-0xC]; ++ u16 typeorlen; ++ u8 res2[0x1]; ++ u8 rxgstpack; /* ack on GRACEFUL STOP RX command */ ++ u32 rxrmonbaseptr; /* Rx RMON statistics base */ ++ u8 res3[0x30-0x28]; ++ u32 intcoalescingptr; /* Interrupt coalescing table pointer */ ++ u8 res4[0x36-0x34]; ++ u8 rstate; ++ u8 res5[0x46-0x37]; ++ u16 mrblr; /* max receive buffer length reg. */ ++ u32 rbdqptr; /* RxBD parameter table description */ ++ u16 mflr; /* max frame length reg. */ ++ u16 minflr; /* min frame length reg. */ ++ u16 maxd1; /* max dma1 length reg. */ ++ u16 maxd2; /* max dma2 length reg. */ ++ u32 ecamptr; /* external CAM address */ ++ u32 l2qt; /* VLAN priority mapping table. */ ++ u32 l3qt[0x8]; /* IP priority mapping table. */ ++ u16 vlantype; /* vlan type */ ++ u16 vlantci; /* default vlan tci */ ++ u8 addressfiltering[64];/* address filtering data structure */ ++ u32 exfGlobalParam; /* extended filtering global parameters */ ++ u8 res6[0x100-0xC4]; /* Initialize to zero */ ++} __attribute__ ((packed)) uec_rx_global_pram_t; ++ ++#define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01 ++ ++ ++/****** UEC common ******/ ++/* UCC statistics - hardware counters ++*/ ++typedef struct uec_hardware_statistics { ++ u32 tx64; ++ u32 tx127; ++ u32 tx255; ++ u32 rx64; ++ u32 rx127; ++ u32 rx255; ++ u32 txok; ++ u16 txcf; ++ u32 tmca; ++ u32 tbca; ++ u32 rxfok; ++ u32 rxbok; ++ u32 rbyt; ++ u32 rmca; ++ u32 rbca; ++} __attribute__ ((packed)) uec_hardware_statistics_t; ++ ++/* InitEnet command parameter ++*/ ++typedef struct uec_init_cmd_pram { ++ u8 resinit0; ++ u8 resinit1; ++ u8 resinit2; ++ u8 resinit3; ++ u16 resinit4; ++ u8 res1[0x1]; ++ u8 largestexternallookupkeysize; ++ u32 rgftgfrxglobal; ++ u32 rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */ ++ u8 res2[0x38 - 0x30]; ++ u32 txglobal; /* tx global */ ++ u32 txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */ ++ u8 res3[0x1]; ++} __attribute__ ((packed)) uec_init_cmd_pram_t; ++ ++#define ENET_INIT_PARAM_RGF_SHIFT (32 - 4) ++#define ENET_INIT_PARAM_TGF_SHIFT (32 - 8) ++ ++#define ENET_INIT_PARAM_RISC_MASK 0x0000003f ++#define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0 ++#define ENET_INIT_PARAM_SNUM_MASK 0xff000000 ++#define ENET_INIT_PARAM_SNUM_SHIFT 24 ++ ++#define ENET_INIT_PARAM_MAGIC_RES_INIT0 0x06 ++#define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x30 ++#define ENET_INIT_PARAM_MAGIC_RES_INIT2 0xff ++#define ENET_INIT_PARAM_MAGIC_RES_INIT3 0x00 ++#define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x0400 ++ ++/* structure representing 82xx Address Filtering Enet Address in PRAM ++*/ ++typedef struct uec_82xx_enet_address { ++ u8 res1[0x2]; ++ u16 h; /* address (MSB) */ ++ u16 m; /* address */ ++ u16 l; /* address (LSB) */ ++} __attribute__ ((packed)) uec_82xx_enet_address_t; ++ ++/* structure representing 82xx Address Filtering PRAM ++*/ ++typedef struct uec_82xx_address_filtering_pram { ++ u32 iaddr_h; /* individual address filter, high */ ++ u32 iaddr_l; /* individual address filter, low */ ++ u32 gaddr_h; /* group address filter, high */ ++ u32 gaddr_l; /* group address filter, low */ ++ uec_82xx_enet_address_t taddr; ++ uec_82xx_enet_address_t paddr[4]; ++ u8 res0[0x40-0x38]; ++} __attribute__ ((packed)) uec_82xx_address_filtering_pram_t; ++ ++/* Buffer Descriptor ++*/ ++typedef struct buffer_descriptor { ++ u16 status; ++ u16 len; ++ u32 data; ++} __attribute__ ((packed)) qe_bd_t, *p_bd_t; ++ ++#define SIZEOFBD sizeof(qe_bd_t) ++ ++/* Common BD flags ++*/ ++#define BD_WRAP 0x2000 ++#define BD_INT 0x1000 ++#define BD_LAST 0x0800 ++#define BD_CLEAN 0x3000 ++ ++/* TxBD status flags ++*/ ++#define TxBD_READY 0x8000 ++#define TxBD_PADCRC 0x4000 ++#define TxBD_WRAP BD_WRAP ++#define TxBD_INT BD_INT ++#define TxBD_LAST BD_LAST ++#define TxBD_TXCRC 0x0400 ++#define TxBD_DEF 0x0200 ++#define TxBD_PP 0x0100 ++#define TxBD_LC 0x0080 ++#define TxBD_RL 0x0040 ++#define TxBD_RC 0x003C ++#define TxBD_UNDERRUN 0x0002 ++#define TxBD_TRUNC 0x0001 ++ ++#define TxBD_ERROR (TxBD_UNDERRUN | TxBD_TRUNC) ++ ++/* RxBD status flags ++*/ ++#define RxBD_EMPTY 0x8000 ++#define RxBD_OWNER 0x4000 ++#define RxBD_WRAP BD_WRAP ++#define RxBD_INT BD_INT ++#define RxBD_LAST BD_LAST ++#define RxBD_FIRST 0x0400 ++#define RxBD_CMR 0x0200 ++#define RxBD_MISS 0x0100 ++#define RxBD_BCAST 0x0080 ++#define RxBD_MCAST 0x0040 ++#define RxBD_LG 0x0020 ++#define RxBD_NO 0x0010 ++#define RxBD_SHORT 0x0008 ++#define RxBD_CRCERR 0x0004 ++#define RxBD_OVERRUN 0x0002 ++#define RxBD_IPCH 0x0001 ++ ++#define RxBD_ERROR (RxBD_LG | RxBD_NO | RxBD_SHORT | \ ++ RxBD_CRCERR | RxBD_OVERRUN) ++ ++/* BD access macros ++*/ ++#define BD_STATUS(_bd) (((p_bd_t)(_bd))->status) ++#define BD_STATUS_SET(_bd, _val) (((p_bd_t)(_bd))->status = _val) ++#define BD_LENGTH(_bd) (((p_bd_t)(_bd))->len) ++#define BD_LENGTH_SET(_bd, _val) (((p_bd_t)(_bd))->len = _val) ++#define BD_DATA_CLEAR(_bd) (((p_bd_t)(_bd))->data = 0) ++#define BD_IS_DATA(_bd) (((p_bd_t)(_bd))->data) ++#define BD_DATA(_bd) ((u8 *)(((p_bd_t)(_bd))->data)) ++#define BD_DATA_SET(_bd, _data) (((p_bd_t)(_bd))->data = (u32)(_data)) ++#define BD_ADVANCE(_bd,_status,_base) \ ++ (((_status) & BD_WRAP) ? (_bd) = ((p_bd_t)(_base)) : ++(_bd)) ++ ++/* Rx Prefetched BDs ++*/ ++typedef struct uec_rx_prefetched_bds { ++ qe_bd_t bd[MAX_PREFETCHED_BDS]; /* prefetched bd */ ++} __attribute__ ((packed)) uec_rx_prefetched_bds_t; ++ ++/* Alignments ++ */ ++#define UEC_RX_GLOBAL_PRAM_ALIGNMENT 64 ++#define UEC_TX_GLOBAL_PRAM_ALIGNMENT 64 ++#define UEC_THREAD_RX_PRAM_ALIGNMENT 128 ++#define UEC_THREAD_TX_PRAM_ALIGNMENT 64 ++#define UEC_THREAD_DATA_ALIGNMENT 256 ++#define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32 ++#define UEC_SCHEDULER_ALIGNMENT 4 ++#define UEC_TX_STATISTICS_ALIGNMENT 4 ++#define UEC_RX_STATISTICS_ALIGNMENT 4 ++#define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT 4 ++#define UEC_RX_BD_QUEUES_ALIGNMENT 8 ++#define UEC_RX_PREFETCHED_BDS_ALIGNMENT 128 ++#define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4 ++#define UEC_RX_BD_RING_ALIGNMENT 32 ++#define UEC_TX_BD_RING_ALIGNMENT 32 ++#define UEC_MRBLR_ALIGNMENT 128 ++#define UEC_RX_BD_RING_SIZE_ALIGNMENT 4 ++#define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32 ++#define UEC_RX_DATA_BUF_ALIGNMENT 64 ++ ++#define UEC_VLAN_PRIORITY_MAX 8 ++#define UEC_IP_PRIORITY_MAX 64 ++#define UEC_TX_VTAG_TABLE_ENTRY_MAX 8 ++#define UEC_RX_BD_RING_SIZE_MIN 8 ++#define UEC_TX_BD_RING_SIZE_MIN 2 ++ ++/* Ethernet speed ++*/ ++typedef enum enet_speed { ++ ENET_SPEED_10BT, /* 10 Base T */ ++ ENET_SPEED_100BT, /* 100 Base T */ ++ ENET_SPEED_1000BT /* 1000 Base T */ ++} enet_speed_e; ++ ++/* Ethernet Address Type. ++*/ ++typedef enum enet_addr_type { ++ ENET_ADDR_TYPE_INDIVIDUAL, ++ ENET_ADDR_TYPE_GROUP, ++ ENET_ADDR_TYPE_BROADCAST ++} enet_addr_type_e; ++ ++/* TBI / MII Set Register ++*/ ++typedef enum enet_tbi_mii_reg { ++ ENET_TBI_MII_CR = 0x00, ++ ENET_TBI_MII_SR = 0x01, ++ ENET_TBI_MII_ANA = 0x04, ++ ENET_TBI_MII_ANLPBPA = 0x05, ++ ENET_TBI_MII_ANEX = 0x06, ++ ENET_TBI_MII_ANNPT = 0x07, ++ ENET_TBI_MII_ANLPANP = 0x08, ++ ENET_TBI_MII_EXST = 0x0F, ++ ENET_TBI_MII_JD = 0x10, ++ ENET_TBI_MII_TBICON = 0x11 ++} enet_tbi_mii_reg_e; ++ ++/* UEC number of threads ++*/ ++typedef enum uec_num_of_threads { ++ UEC_NUM_OF_THREADS_1 = 0x1, /* 1 */ ++ UEC_NUM_OF_THREADS_2 = 0x2, /* 2 */ ++ UEC_NUM_OF_THREADS_4 = 0x0, /* 4 */ ++ UEC_NUM_OF_THREADS_6 = 0x3, /* 6 */ ++ UEC_NUM_OF_THREADS_8 = 0x4 /* 8 */ ++} uec_num_of_threads_e; ++ ++/* UEC ethernet interface type ++*/ ++typedef enum enet_interface { ++ ENET_10_MII, ++ ENET_10_RMII, ++ ENET_10_RGMII, ++ ENET_100_MII, ++ ENET_100_RMII, ++ ENET_100_RGMII, ++ ENET_1000_GMII, ++ ENET_1000_RGMII, ++ ENET_1000_TBI, ++ ENET_1000_RTBI ++} enet_interface_e; ++ ++/* UEC initialization info struct ++*/ ++typedef struct uec_info { ++ ucc_fast_info_t uf_info; ++ uec_num_of_threads_e num_threads_tx; ++ uec_num_of_threads_e num_threads_rx; ++ qe_risc_allocation_e riscTx; ++ qe_risc_allocation_e riscRx; ++ u16 rx_bd_ring_len; ++ u16 tx_bd_ring_len; ++ u8 phy_address; ++ enet_interface_e enet_interface; ++} uec_info_t; ++ ++/* UEC driver initialized info ++*/ ++#define MAX_RXBUF_LEN 1536 ++#define MAX_FRAME_LEN 1518 ++#define MIN_FRAME_LEN 64 ++#define MAX_DMA1_LEN 1520 ++#define MAX_DMA2_LEN 1520 ++ ++/* UEC driver private struct ++*/ ++typedef struct uec_private { ++ uec_info_t *uec_info; ++ ucc_fast_private_t *uccf; ++ struct eth_device *dev; ++ uec_t *uec_regs; ++ /* enet init command parameter */ ++ uec_init_cmd_pram_t *p_init_enet_param; ++ u32 init_enet_param_offset; ++ /* Rx and Tx paramter */ ++ uec_rx_global_pram_t *p_rx_glbl_pram; ++ u32 rx_glbl_pram_offset; ++ uec_tx_global_pram_t *p_tx_glbl_pram; ++ u32 tx_glbl_pram_offset; ++ uec_send_queue_mem_region_t *p_send_q_mem_reg; ++ u32 send_q_mem_reg_offset; ++ uec_thread_data_tx_t *p_thread_data_tx; ++ u32 thread_dat_tx_offset; ++ uec_thread_data_rx_t *p_thread_data_rx; ++ u32 thread_dat_rx_offset; ++ uec_rx_bd_queues_entry_t *p_rx_bd_qs_tbl; ++ u32 rx_bd_qs_tbl_offset; ++ /* BDs specific */ ++ u8 *p_tx_bd_ring; ++ u32 tx_bd_ring_offset; ++ u8 *p_rx_bd_ring; ++ u32 rx_bd_ring_offset; ++ u8 *p_rx_buf; ++ u32 rx_buf_offset; ++ volatile qe_bd_t *txBd; ++ volatile qe_bd_t *rxBd; ++ /* Status */ ++ int mac_tx_enabled; ++ int mac_rx_enabled; ++ int grace_stopped_tx; ++ int grace_stopped_rx; ++ int the_first_run; ++ /* PHY specific */ ++ struct uec_mii_info *mii_info; ++ int oldspeed; ++ int oldduplex; ++ int oldlink; ++} uec_private_t; ++ ++#endif /* __UEC_H__ */ +diff -Naupr u-boot-1.1.6/drivers/qe/uec_phy.c u-boot-1.1.6-fsl-1/drivers/qe/uec_phy.c +--- u-boot-1.1.6/drivers/qe/uec_phy.c 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/drivers/qe/uec_phy.c 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,607 @@ ++/* ++ * Copyright (C) 2005 Freescale Semiconductor, Inc. ++ * ++ * Author: Shlomi Gridish ++ * ++ * Description: UCC GETH Driver -- PHY handling ++ * Driver for UEC on QE ++ * Based on 8260_io/fcc_enet.c ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#include "common.h" ++#include "net.h" ++#include "malloc.h" ++#include "asm/errno.h" ++#include "asm/immap_qe.h" ++#include "asm/io.h" ++#include "qe.h" ++#include "uccf.h" ++#include "uec.h" ++#include "uec_phy.h" ++#include "miiphy.h" ++ ++#if defined(CONFIG_QE) ++ ++#define UEC_VERBOSE_DEBUG ++#define ugphy_printk(format, arg...) \ ++ printf(format "\n", ## arg) ++ ++#define ugphy_dbg(format, arg...) \ ++ ugphy_printk(format , ## arg) ++#define ugphy_err(format, arg...) \ ++ ugphy_printk(format , ## arg) ++#define ugphy_info(format, arg...) \ ++ ugphy_printk(format , ## arg) ++#define ugphy_warn(format, arg...) \ ++ ugphy_printk(format , ## arg) ++ ++#ifdef UEC_VERBOSE_DEBUG ++#define ugphy_vdbg ugphy_dbg ++#else ++#define ugphy_vdbg(ugeth, fmt, args...) do { } while (0) ++#endif /* UEC_VERBOSE_DEBUG */ ++ ++static void config_genmii_advert (struct uec_mii_info *mii_info); ++static void genmii_setup_forced (struct uec_mii_info *mii_info); ++static void genmii_restart_aneg (struct uec_mii_info *mii_info); ++static int gbit_config_aneg (struct uec_mii_info *mii_info); ++static int genmii_config_aneg (struct uec_mii_info *mii_info); ++static int genmii_update_link (struct uec_mii_info *mii_info); ++static int genmii_read_status (struct uec_mii_info *mii_info); ++u16 phy_read (struct uec_mii_info *mii_info, u16 regnum); ++void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val); ++ ++/* Write value to the PHY for this device to the register at regnum, */ ++/* waiting until the write is done before it returns. All PHY */ ++/* configuration has to be done through the TSEC1 MIIM regs */ ++void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value) ++{ ++ uec_private_t *ugeth = (uec_private_t *) dev->priv; ++ uec_t *ug_regs; ++ enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum; ++ u32 tmp_reg; ++ ++ ug_regs = ugeth->uec_regs; ++ ++ /* Stop the MII management read cycle */ ++ out_be32 (&ug_regs->miimcom, 0); ++ /* Setting up the MII Mangement Address Register */ ++ tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg; ++ out_be32 (&ug_regs->miimadd, tmp_reg); ++ ++ /* Setting up the MII Mangement Control Register with the value */ ++ out_be32 (&ug_regs->miimcon, (u32) value); ++ ++ /* Wait till MII management write is complete */ ++ while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY); ++ ++ udelay (100000); ++} ++ ++/* Reads from register regnum in the PHY for device dev, */ ++/* returning the value. Clears miimcom first. All PHY */ ++/* configuration has to be done through the TSEC1 MIIM regs */ ++int read_phy_reg (struct eth_device *dev, int mii_id, int regnum) ++{ ++ uec_private_t *ugeth = (uec_private_t *) dev->priv; ++ uec_t *ug_regs; ++ enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum; ++ u32 tmp_reg; ++ u16 value; ++ ++ ug_regs = ugeth->uec_regs; ++ ++ /* Setting up the MII Mangement Address Register */ ++ tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg; ++ out_be32 (&ug_regs->miimadd, tmp_reg); ++ ++ /* Perform an MII management read cycle */ ++ out_be32 (&ug_regs->miimcom, 0); ++ out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE); ++ ++ /* Wait till MII management write is complete */ ++ while ((in_be32 (&ug_regs->miimind)) & ++ (MIIMIND_NOT_VALID | MIIMIND_BUSY)); ++ ++ udelay (100000); ++ ++ /* Read MII management status */ ++ value = (u16) in_be32 (&ug_regs->miimstat); ++ if (value == 0xffff) ++ ugphy_warn ++ ("read wrong value : mii_id %d,mii_reg %d, base %08x", ++ mii_id, mii_reg, (u32) & (ug_regs->miimcfg)); ++ ++ return (value); ++} ++ ++void mii_clear_phy_interrupt (struct uec_mii_info *mii_info) ++{ ++ if (mii_info->phyinfo->ack_interrupt) ++ mii_info->phyinfo->ack_interrupt (mii_info); ++} ++ ++void mii_configure_phy_interrupt (struct uec_mii_info *mii_info, ++ u32 interrupts) ++{ ++ mii_info->interrupts = interrupts; ++ if (mii_info->phyinfo->config_intr) ++ mii_info->phyinfo->config_intr (mii_info); ++} ++ ++/* Writes MII_ADVERTISE with the appropriate values, after ++ * sanitizing advertise to make sure only supported features ++ * are advertised ++ */ ++static void config_genmii_advert (struct uec_mii_info *mii_info) ++{ ++ u32 advertise; ++ u16 adv; ++ ++ /* Only allow advertising what this PHY supports */ ++ mii_info->advertising &= mii_info->phyinfo->features; ++ advertise = mii_info->advertising; ++ ++ /* Setup standard advertisement */ ++ adv = phy_read (mii_info, PHY_ANAR); ++ adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); ++ if (advertise & ADVERTISED_10baseT_Half) ++ adv |= ADVERTISE_10HALF; ++ if (advertise & ADVERTISED_10baseT_Full) ++ adv |= ADVERTISE_10FULL; ++ if (advertise & ADVERTISED_100baseT_Half) ++ adv |= ADVERTISE_100HALF; ++ if (advertise & ADVERTISED_100baseT_Full) ++ adv |= ADVERTISE_100FULL; ++ phy_write (mii_info, PHY_ANAR, adv); ++} ++ ++static void genmii_setup_forced (struct uec_mii_info *mii_info) ++{ ++ u16 ctrl; ++ u32 features = mii_info->phyinfo->features; ++ ++ ctrl = phy_read (mii_info, PHY_BMCR); ++ ++ ctrl &= ~(PHY_BMCR_DPLX | PHY_BMCR_100_MBPS | ++ PHY_BMCR_1000_MBPS | PHY_BMCR_AUTON); ++ ctrl |= PHY_BMCR_RESET; ++ ++ switch (mii_info->speed) { ++ case SPEED_1000: ++ if (features & (SUPPORTED_1000baseT_Half ++ | SUPPORTED_1000baseT_Full)) { ++ ctrl |= PHY_BMCR_1000_MBPS; ++ break; ++ } ++ mii_info->speed = SPEED_100; ++ case SPEED_100: ++ if (features & (SUPPORTED_100baseT_Half ++ | SUPPORTED_100baseT_Full)) { ++ ctrl |= PHY_BMCR_100_MBPS; ++ break; ++ } ++ mii_info->speed = SPEED_10; ++ case SPEED_10: ++ if (features & (SUPPORTED_10baseT_Half ++ | SUPPORTED_10baseT_Full)) ++ break; ++ default: /* Unsupported speed! */ ++ ugphy_err ("%s: Bad speed!", mii_info->dev->name); ++ break; ++ } ++ ++ phy_write (mii_info, PHY_BMCR, ctrl); ++} ++ ++/* Enable and Restart Autonegotiation */ ++static void genmii_restart_aneg (struct uec_mii_info *mii_info) ++{ ++ u16 ctl; ++ ++ ctl = phy_read (mii_info, PHY_BMCR); ++ ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); ++ phy_write (mii_info, PHY_BMCR, ctl); ++} ++ ++static int gbit_config_aneg (struct uec_mii_info *mii_info) ++{ ++ u16 adv; ++ u32 advertise; ++ ++ if (mii_info->autoneg) { ++ /* Configure the ADVERTISE register */ ++ config_genmii_advert (mii_info); ++ advertise = mii_info->advertising; ++ ++ adv = phy_read (mii_info, MII_1000BASETCONTROL); ++ adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP | ++ MII_1000BASETCONTROL_HALFDUPLEXCAP); ++ if (advertise & SUPPORTED_1000baseT_Half) ++ adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP; ++ if (advertise & SUPPORTED_1000baseT_Full) ++ adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP; ++ phy_write (mii_info, MII_1000BASETCONTROL, adv); ++ ++ /* Start/Restart aneg */ ++ genmii_restart_aneg (mii_info); ++ } else ++ genmii_setup_forced (mii_info); ++ ++ return 0; ++} ++ ++static int marvell_config_aneg (struct uec_mii_info *mii_info) ++{ ++ /* The Marvell PHY has an errata which requires ++ * that certain registers get written in order ++ * to restart autonegotiation */ ++ phy_write (mii_info, PHY_BMCR, PHY_BMCR_RESET); ++ ++ phy_write (mii_info, 0x1d, 0x1f); ++ phy_write (mii_info, 0x1e, 0x200c); ++ phy_write (mii_info, 0x1d, 0x5); ++ phy_write (mii_info, 0x1e, 0); ++ phy_write (mii_info, 0x1e, 0x100); ++ ++ gbit_config_aneg (mii_info); ++ ++ return 0; ++} ++ ++static int genmii_config_aneg (struct uec_mii_info *mii_info) ++{ ++ if (mii_info->autoneg) { ++ config_genmii_advert (mii_info); ++ genmii_restart_aneg (mii_info); ++ } else ++ genmii_setup_forced (mii_info); ++ ++ return 0; ++} ++ ++static int genmii_update_link (struct uec_mii_info *mii_info) ++{ ++ u16 status; ++ ++ /* Do a fake read */ ++ phy_read (mii_info, PHY_BMSR); ++ ++ /* Read link and autonegotiation status */ ++ status = phy_read (mii_info, PHY_BMSR); ++ if ((status & PHY_BMSR_LS) == 0) ++ mii_info->link = 0; ++ else ++ mii_info->link = 1; ++ ++ /* If we are autonegotiating, and not done, ++ * return an error */ ++ if (mii_info->autoneg && !(status & PHY_BMSR_AUTN_COMP)) ++ return -EAGAIN; ++ ++ return 0; ++} ++ ++static int genmii_read_status (struct uec_mii_info *mii_info) ++{ ++ u16 status; ++ int err; ++ ++ /* Update the link, but return if there ++ * was an error */ ++ err = genmii_update_link (mii_info); ++ if (err) ++ return err; ++ ++ if (mii_info->autoneg) { ++ status = phy_read (mii_info, PHY_ANLPAR); ++ ++ if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) ++ mii_info->duplex = DUPLEX_FULL; ++ else ++ mii_info->duplex = DUPLEX_HALF; ++ if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) ++ mii_info->speed = SPEED_100; ++ else ++ mii_info->speed = SPEED_10; ++ mii_info->pause = 0; ++ } ++ /* On non-aneg, we assume what we put in BMCR is the speed, ++ * though magic-aneg shouldn't prevent this case from occurring ++ */ ++ ++ return 0; ++} ++ ++static int marvell_read_status (struct uec_mii_info *mii_info) ++{ ++ u16 status; ++ int err; ++ ++ /* Update the link, but return if there ++ * was an error */ ++ err = genmii_update_link (mii_info); ++ if (err) ++ return err; ++ ++ /* If the link is up, read the speed and duplex */ ++ /* If we aren't autonegotiating, assume speeds ++ * are as set */ ++ if (mii_info->autoneg && mii_info->link) { ++ int speed; ++ ++ status = phy_read (mii_info, MII_M1011_PHY_SPEC_STATUS); ++ ++ /* Get the duplexity */ ++ if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX) ++ mii_info->duplex = DUPLEX_FULL; ++ else ++ mii_info->duplex = DUPLEX_HALF; ++ ++ /* Get the speed */ ++ speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK; ++ switch (speed) { ++ case MII_M1011_PHY_SPEC_STATUS_1000: ++ mii_info->speed = SPEED_1000; ++ break; ++ case MII_M1011_PHY_SPEC_STATUS_100: ++ mii_info->speed = SPEED_100; ++ break; ++ default: ++ mii_info->speed = SPEED_10; ++ break; ++ } ++ mii_info->pause = 0; ++ } ++ ++ return 0; ++} ++ ++static int marvell_ack_interrupt (struct uec_mii_info *mii_info) ++{ ++ /* Clear the interrupts by reading the reg */ ++ phy_read (mii_info, MII_M1011_IEVENT); ++ ++ return 0; ++} ++ ++static int marvell_config_intr (struct uec_mii_info *mii_info) ++{ ++ if (mii_info->interrupts == MII_INTERRUPT_ENABLED) ++ phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT); ++ else ++ phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR); ++ ++ return 0; ++} ++ ++static int dm9161_init (struct uec_mii_info *mii_info) ++{ ++ /* Reset the PHY */ ++ phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) | ++ PHY_BMCR_RESET); ++ /* PHY and MAC connect */ ++ phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) & ++ ~PHY_BMCR_ISO); ++#ifdef CONFIG_RMII_MODE ++ phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_RMII_INIT); ++#else ++ phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT); ++#endif ++ config_genmii_advert (mii_info); ++ /* Start/restart aneg */ ++ genmii_config_aneg (mii_info); ++ /* Delay to wait the aneg compeleted */ ++ udelay (3000000); ++ ++ return 0; ++} ++ ++static int dm9161_config_aneg (struct uec_mii_info *mii_info) ++{ ++ return 0; ++} ++ ++static int dm9161_read_status (struct uec_mii_info *mii_info) ++{ ++ u16 status; ++ int err; ++ ++ /* Update the link, but return if there was an error */ ++ err = genmii_update_link (mii_info); ++ if (err) ++ return err; ++ /* If the link is up, read the speed and duplex ++ If we aren't autonegotiating assume speeds are as set */ ++ if (mii_info->autoneg && mii_info->link) { ++ status = phy_read (mii_info, MII_DM9161_SCSR); ++ if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H)) ++ mii_info->speed = SPEED_100; ++ else ++ mii_info->speed = SPEED_10; ++ ++ if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F)) ++ mii_info->duplex = DUPLEX_FULL; ++ else ++ mii_info->duplex = DUPLEX_HALF; ++ } ++ ++ return 0; ++} ++ ++static int dm9161_ack_interrupt (struct uec_mii_info *mii_info) ++{ ++ /* Clear the interrupt by reading the reg */ ++ phy_read (mii_info, MII_DM9161_INTR); ++ ++ return 0; ++} ++ ++static int dm9161_config_intr (struct uec_mii_info *mii_info) ++{ ++ if (mii_info->interrupts == MII_INTERRUPT_ENABLED) ++ phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT); ++ else ++ phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP); ++ ++ return 0; ++} ++ ++static void dm9161_close (struct uec_mii_info *mii_info) ++{ ++} ++ ++static struct phy_info phy_info_dm9161 = { ++ .phy_id = 0x0181b880, ++ .phy_id_mask = 0x0ffffff0, ++ .name = "Davicom DM9161E", ++ .init = dm9161_init, ++ .config_aneg = dm9161_config_aneg, ++ .read_status = dm9161_read_status, ++ .close = dm9161_close, ++}; ++ ++static struct phy_info phy_info_dm9161a = { ++ .phy_id = 0x0181b8a0, ++ .phy_id_mask = 0x0ffffff0, ++ .name = "Davicom DM9161A", ++ .features = MII_BASIC_FEATURES, ++ .init = dm9161_init, ++ .config_aneg = dm9161_config_aneg, ++ .read_status = dm9161_read_status, ++ .ack_interrupt = dm9161_ack_interrupt, ++ .config_intr = dm9161_config_intr, ++ .close = dm9161_close, ++}; ++ ++static struct phy_info phy_info_marvell = { ++ .phy_id = 0x01410c00, ++ .phy_id_mask = 0xffffff00, ++ .name = "Marvell 88E11x1", ++ .features = MII_GBIT_FEATURES, ++ .config_aneg = &marvell_config_aneg, ++ .read_status = &marvell_read_status, ++ .ack_interrupt = &marvell_ack_interrupt, ++ .config_intr = &marvell_config_intr, ++}; ++ ++static struct phy_info phy_info_genmii = { ++ .phy_id = 0x00000000, ++ .phy_id_mask = 0x00000000, ++ .name = "Generic MII", ++ .features = MII_BASIC_FEATURES, ++ .config_aneg = genmii_config_aneg, ++ .read_status = genmii_read_status, ++}; ++ ++static struct phy_info *phy_info[] = { ++ &phy_info_dm9161, ++ &phy_info_dm9161a, ++ &phy_info_marvell, ++ &phy_info_genmii, ++ NULL ++}; ++ ++u16 phy_read (struct uec_mii_info *mii_info, u16 regnum) ++{ ++ return mii_info->mdio_read (mii_info->dev, mii_info->mii_id, regnum); ++} ++ ++void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val) ++{ ++ mii_info->mdio_write (mii_info->dev, mii_info->mii_id, regnum, val); ++} ++ ++/* Use the PHY ID registers to determine what type of PHY is attached ++ * to device dev. return a struct phy_info structure describing that PHY ++ */ ++struct phy_info *get_phy_info (struct uec_mii_info *mii_info) ++{ ++ u16 phy_reg; ++ u32 phy_ID; ++ int i; ++ struct phy_info *theInfo = NULL; ++ ++ /* Grab the bits from PHYIR1, and put them in the upper half */ ++ phy_reg = phy_read (mii_info, PHY_PHYIDR1); ++ phy_ID = (phy_reg & 0xffff) << 16; ++ ++ /* Grab the bits from PHYIR2, and put them in the lower half */ ++ phy_reg = phy_read (mii_info, PHY_PHYIDR2); ++ phy_ID |= (phy_reg & 0xffff); ++ ++ /* loop through all the known PHY types, and find one that */ ++ /* matches the ID we read from the PHY. */ ++ for (i = 0; phy_info[i]; i++) ++ if (phy_info[i]->phy_id == ++ (phy_ID & phy_info[i]->phy_id_mask)) { ++ theInfo = phy_info[i]; ++ break; ++ } ++ ++ /* This shouldn't happen, as we have generic PHY support */ ++ if (theInfo == NULL) { ++ ugphy_info ("UEC: PHY id %x is not supported!", phy_ID); ++ return NULL; ++ } else { ++ ugphy_info ("UEC: PHY is %s (%x)", theInfo->name, phy_ID); ++ } ++ ++ return theInfo; ++} ++ ++void marvell_phy_interface_mode (struct eth_device *dev, ++ enet_interface_e mode) ++{ ++ uec_private_t *uec = (uec_private_t *) dev->priv; ++ struct uec_mii_info *mii_info; ++ ++ if (!uec->mii_info) { ++ printf ("%s: the PHY not intialized\n", __FUNCTION__); ++ return; ++ } ++ mii_info = uec->mii_info; ++ ++ if (mode == ENET_100_RGMII) { ++ phy_write (mii_info, 0x00, 0x9140); ++ phy_write (mii_info, 0x1d, 0x001f); ++ phy_write (mii_info, 0x1e, 0x200c); ++ phy_write (mii_info, 0x1d, 0x0005); ++ phy_write (mii_info, 0x1e, 0x0000); ++ phy_write (mii_info, 0x1e, 0x0100); ++ phy_write (mii_info, 0x09, 0x0e00); ++ phy_write (mii_info, 0x04, 0x01e1); ++ phy_write (mii_info, 0x00, 0x9140); ++ phy_write (mii_info, 0x00, 0x1000); ++ udelay (100000); ++ phy_write (mii_info, 0x00, 0x2900); ++ phy_write (mii_info, 0x14, 0x0cd2); ++ phy_write (mii_info, 0x00, 0xa100); ++ phy_write (mii_info, 0x09, 0x0000); ++ phy_write (mii_info, 0x1b, 0x800b); ++ phy_write (mii_info, 0x04, 0x05e1); ++ phy_write (mii_info, 0x00, 0xa100); ++ phy_write (mii_info, 0x00, 0x2100); ++ udelay (1000000); ++ } else if (mode == ENET_10_RGMII) { ++ phy_write (mii_info, 0x14, 0x8e40); ++ phy_write (mii_info, 0x1b, 0x800b); ++ phy_write (mii_info, 0x14, 0x0c82); ++ phy_write (mii_info, 0x00, 0x8100); ++ udelay (1000000); ++ } ++} ++ ++void change_phy_interface_mode (struct eth_device *dev, enet_interface_e mode) ++{ ++#ifdef CONFIG_PHY_MODE_NEED_CHANGE ++ marvell_phy_interface_mode (dev, mode); ++#endif ++} ++#endif /* CONFIG_QE */ +diff -Naupr u-boot-1.1.6/drivers/qe/uec_phy.h u-boot-1.1.6-fsl-1/drivers/qe/uec_phy.h +--- u-boot-1.1.6/drivers/qe/uec_phy.h 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/drivers/qe/uec_phy.h 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,259 @@ ++/* ++ * Copyright (C) 2005 Freescale Semiconductor, Inc. ++ * ++ * Author: Shlomi Gridish ++ * ++ * Description: UCC ethernet driver -- PHY handling ++ * Driver for UEC on QE ++ * Based on 8260_io/fcc_enet.c ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++#ifndef __UEC_PHY_H__ ++#define __UEC_PHY_H__ ++ ++#define MII_end ((u32)-2) ++#define MII_read ((u32)-1) ++ ++#define MIIMIND_BUSY 0x00000001 ++#define MIIMIND_NOTVALID 0x00000004 ++ ++#define UGETH_AN_TIMEOUT 2000 ++ ++/* 1000BT control (Marvell & BCM54xx at least) */ ++#define MII_1000BASETCONTROL 0x09 ++#define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200 ++#define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100 ++ ++/* Cicada Extended Control Register 1 */ ++#define MII_CIS8201_EXT_CON1 0x17 ++#define MII_CIS8201_EXTCON1_INIT 0x0000 ++ ++/* Cicada Interrupt Mask Register */ ++#define MII_CIS8201_IMASK 0x19 ++#define MII_CIS8201_IMASK_IEN 0x8000 ++#define MII_CIS8201_IMASK_SPEED 0x4000 ++#define MII_CIS8201_IMASK_LINK 0x2000 ++#define MII_CIS8201_IMASK_DUPLEX 0x1000 ++#define MII_CIS8201_IMASK_MASK 0xf000 ++ ++/* Cicada Interrupt Status Register */ ++#define MII_CIS8201_ISTAT 0x1a ++#define MII_CIS8201_ISTAT_STATUS 0x8000 ++#define MII_CIS8201_ISTAT_SPEED 0x4000 ++#define MII_CIS8201_ISTAT_LINK 0x2000 ++#define MII_CIS8201_ISTAT_DUPLEX 0x1000 ++ ++/* Cicada Auxiliary Control/Status Register */ ++#define MII_CIS8201_AUX_CONSTAT 0x1c ++#define MII_CIS8201_AUXCONSTAT_INIT 0x0004 ++#define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020 ++#define MII_CIS8201_AUXCONSTAT_SPEED 0x0018 ++#define MII_CIS8201_AUXCONSTAT_GBIT 0x0010 ++#define MII_CIS8201_AUXCONSTAT_100 0x0008 ++ ++/* 88E1011 PHY Status Register */ ++#define MII_M1011_PHY_SPEC_STATUS 0x11 ++#define MII_M1011_PHY_SPEC_STATUS_1000 0x8000 ++#define MII_M1011_PHY_SPEC_STATUS_100 0x4000 ++#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000 ++#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000 ++#define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800 ++#define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400 ++ ++#define MII_M1011_IEVENT 0x13 ++#define MII_M1011_IEVENT_CLEAR 0x0000 ++ ++#define MII_M1011_IMASK 0x12 ++#define MII_M1011_IMASK_INIT 0x6400 ++#define MII_M1011_IMASK_CLEAR 0x0000 ++ ++#define MII_DM9161_SCR 0x10 ++#define MII_DM9161_SCR_INIT 0x0610 ++#define MII_DM9161_SCR_RMII_INIT 0x0710 ++ ++/* DM9161 Specified Configuration and Status Register */ ++#define MII_DM9161_SCSR 0x11 ++#define MII_DM9161_SCSR_100F 0x8000 ++#define MII_DM9161_SCSR_100H 0x4000 ++#define MII_DM9161_SCSR_10F 0x2000 ++#define MII_DM9161_SCSR_10H 0x1000 ++ ++/* DM9161 Interrupt Register */ ++#define MII_DM9161_INTR 0x15 ++#define MII_DM9161_INTR_PEND 0x8000 ++#define MII_DM9161_INTR_DPLX_MASK 0x0800 ++#define MII_DM9161_INTR_SPD_MASK 0x0400 ++#define MII_DM9161_INTR_LINK_MASK 0x0200 ++#define MII_DM9161_INTR_MASK 0x0100 ++#define MII_DM9161_INTR_DPLX_CHANGE 0x0010 ++#define MII_DM9161_INTR_SPD_CHANGE 0x0008 ++#define MII_DM9161_INTR_LINK_CHANGE 0x0004 ++#define MII_DM9161_INTR_INIT 0x0000 ++#define MII_DM9161_INTR_STOP \ ++(MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \ ++ | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK) ++ ++/* DM9161 10BT Configuration/Status */ ++#define MII_DM9161_10BTCSR 0x12 ++#define MII_DM9161_10BTCSR_INIT 0x7800 ++ ++#define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | \ ++ SUPPORTED_10baseT_Full | \ ++ SUPPORTED_100baseT_Half | \ ++ SUPPORTED_100baseT_Full | \ ++ SUPPORTED_Autoneg | \ ++ SUPPORTED_TP | \ ++ SUPPORTED_MII) ++ ++#define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \ ++ SUPPORTED_1000baseT_Half | \ ++ SUPPORTED_1000baseT_Full) ++ ++#define MII_READ_COMMAND 0x00000001 ++ ++#define MII_INTERRUPT_DISABLED 0x0 ++#define MII_INTERRUPT_ENABLED 0x1 ++ ++#define SPEED_10 10 ++#define SPEED_100 100 ++#define SPEED_1000 1000 ++ ++/* Duplex, half or full. */ ++#define DUPLEX_HALF 0x00 ++#define DUPLEX_FULL 0x01 ++ ++/* Indicates what features are supported by the interface. */ ++#define SUPPORTED_10baseT_Half (1 << 0) ++#define SUPPORTED_10baseT_Full (1 << 1) ++#define SUPPORTED_100baseT_Half (1 << 2) ++#define SUPPORTED_100baseT_Full (1 << 3) ++#define SUPPORTED_1000baseT_Half (1 << 4) ++#define SUPPORTED_1000baseT_Full (1 << 5) ++#define SUPPORTED_Autoneg (1 << 6) ++#define SUPPORTED_TP (1 << 7) ++#define SUPPORTED_AUI (1 << 8) ++#define SUPPORTED_MII (1 << 9) ++#define SUPPORTED_FIBRE (1 << 10) ++#define SUPPORTED_BNC (1 << 11) ++#define SUPPORTED_10000baseT_Full (1 << 12) ++ ++#define ADVERTISED_10baseT_Half (1 << 0) ++#define ADVERTISED_10baseT_Full (1 << 1) ++#define ADVERTISED_100baseT_Half (1 << 2) ++#define ADVERTISED_100baseT_Full (1 << 3) ++#define ADVERTISED_1000baseT_Half (1 << 4) ++#define ADVERTISED_1000baseT_Full (1 << 5) ++#define ADVERTISED_Autoneg (1 << 6) ++#define ADVERTISED_TP (1 << 7) ++#define ADVERTISED_AUI (1 << 8) ++#define ADVERTISED_MII (1 << 9) ++#define ADVERTISED_FIBRE (1 << 10) ++#define ADVERTISED_BNC (1 << 11) ++#define ADVERTISED_10000baseT_Full (1 << 12) ++ ++/* Advertisement control register. */ ++#define ADVERTISE_SLCT 0x001f /* Selector bits */ ++#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ ++#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ ++#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ ++#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ ++#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ ++#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ ++#define ADVERTISE_RESV 0x1c00 /* Unused... */ ++#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ ++#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ ++#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ ++ ++#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ ++ ADVERTISE_CSMA) ++#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ++ ADVERTISE_100HALF | ADVERTISE_100FULL) ++ ++/* Taken from mii_if_info and sungem_phy.h */ ++struct uec_mii_info { ++ /* Information about the PHY type */ ++ /* And management functions */ ++ struct phy_info *phyinfo; ++ ++ struct eth_device *dev; ++ ++ /* forced speed & duplex (no autoneg) ++ * partner speed & duplex & pause (autoneg) ++ */ ++ int speed; ++ int duplex; ++ int pause; ++ ++ /* The most recently read link state */ ++ int link; ++ ++ /* Enabled Interrupts */ ++ u32 interrupts; ++ ++ u32 advertising; ++ int autoneg; ++ int mii_id; ++ ++ /* private data pointer */ ++ /* For use by PHYs to maintain extra state */ ++ void *priv; ++ ++ /* Provided by ethernet driver */ ++ int (*mdio_read) (struct eth_device * dev, int mii_id, int reg); ++ void (*mdio_write) (struct eth_device * dev, int mii_id, int reg, ++ int val); ++}; ++ ++/* struct phy_info: a structure which defines attributes for a PHY ++ * ++ * id will contain a number which represents the PHY. During ++ * startup, the driver will poll the PHY to find out what its ++ * UID--as defined by registers 2 and 3--is. The 32-bit result ++ * gotten from the PHY will be ANDed with phy_id_mask to ++ * discard any bits which may change based on revision numbers ++ * unimportant to functionality ++ * ++ * There are 6 commands which take a ugeth_mii_info structure. ++ * Each PHY must declare config_aneg, and read_status. ++ */ ++struct phy_info { ++ u32 phy_id; ++ char *name; ++ unsigned int phy_id_mask; ++ u32 features; ++ ++ /* Called to initialize the PHY */ ++ int (*init) (struct uec_mii_info * mii_info); ++ ++ /* Called to suspend the PHY for power */ ++ int (*suspend) (struct uec_mii_info * mii_info); ++ ++ /* Reconfigures autonegotiation (or disables it) */ ++ int (*config_aneg) (struct uec_mii_info * mii_info); ++ ++ /* Determines the negotiated speed and duplex */ ++ int (*read_status) (struct uec_mii_info * mii_info); ++ ++ /* Clears any pending interrupts */ ++ int (*ack_interrupt) (struct uec_mii_info * mii_info); ++ ++ /* Enables or disables interrupts */ ++ int (*config_intr) (struct uec_mii_info * mii_info); ++ ++ /* Clears up any memory if needed */ ++ void (*close) (struct uec_mii_info * mii_info); ++}; ++ ++struct phy_info *get_phy_info (struct uec_mii_info *mii_info); ++void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, ++ int value); ++int read_phy_reg (struct eth_device *dev, int mii_id, int regnum); ++void mii_clear_phy_interrupt (struct uec_mii_info *mii_info); ++void mii_configure_phy_interrupt (struct uec_mii_info *mii_info, ++ u32 interrupts); ++#endif /* __UEC_PHY_H__ */ +diff -Naupr u-boot-1.1.6/drivers/tsec.c u-boot-1.1.6-fsl-1/drivers/tsec.c +--- u-boot-1.1.6/drivers/tsec.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/drivers/tsec.c 2006-11-10 11:24:29.000000000 -0600 +@@ -610,11 +610,10 @@ static void adjust_link(struct eth_devic + regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF)) + | MACCFG2_MII); + +- /* If We're in reduced mode, we need +- * to say whether we're 10 or 100 MB. ++ /* Set R100 bit in all modes although ++ * it is only used in RGMII mode + */ +- if ((priv->speed == 100) +- && (priv->flags & TSEC_REDUCED)) ++ if (priv->speed == 100) + regs->ecntrl |= ECNTRL_R100; + else + regs->ecntrl &= ~(ECNTRL_R100); +@@ -816,6 +815,7 @@ struct phy_info phy_info_M88E1111S = { + {0x1d, 0x5, NULL}, + {0x1e, 0x0, NULL}, + {0x1e, 0x100, NULL}, ++ {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */ + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, +@@ -1110,10 +1110,8 @@ struct phy_info phy_info_dp83865 = { + }; + + struct phy_info *phy_info[] = { +-#if 0 +- &phy_info_cis8201, +-#endif + &phy_info_cis8204, ++ &phy_info_cis8201, + &phy_info_M88E1011S, + &phy_info_M88E1111S, + &phy_info_M88E1145, +diff -Naupr u-boot-1.1.6/drivers/tsec.h u-boot-1.1.6-fsl-1/drivers/tsec.h +--- u-boot-1.1.6/drivers/tsec.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/drivers/tsec.h 2006-11-10 11:24:29.000000000 -0600 +@@ -30,7 +30,7 @@ + #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) + #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET) + #elif defined(CONFIG_MPC83XX) +- #define TSEC_BASE_ADDR (CFG_IMMRBAR + CFG_TSEC1_OFFSET) ++ #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET) + #endif + + +diff -Naupr u-boot-1.1.6/include/74xx_7xx.h u-boot-1.1.6-fsl-1/include/74xx_7xx.h +--- u-boot-1.1.6/include/74xx_7xx.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/74xx_7xx.h 2006-12-06 10:33:49.000000000 -0600 +@@ -111,6 +111,7 @@ typedef enum __cpu_t { + CPU_750CX, CPU_750FX, CPU_750GX, + CPU_7400, + CPU_7410, ++ CPU_7448, + CPU_7450, CPU_7455, CPU_7457, + CPU_UNKNOWN} cpu_t; + +diff -Naupr u-boot-1.1.6/include/ACEX1K.h u-boot-1.1.6-fsl-1/include/ACEX1K.h +--- u-boot-1.1.6/include/ACEX1K.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/ACEX1K.h 2006-11-30 12:34:13.000000000 -0600 +@@ -35,6 +35,11 @@ extern int ACEX1K_dump( Altera_desc *des + extern int ACEX1K_info( Altera_desc *desc ); + extern int ACEX1K_reloc( Altera_desc *desc, ulong reloc_off ); + ++extern int CYC2_load( Altera_desc *desc, void *image, size_t size ); ++extern int CYC2_dump( Altera_desc *desc, void *buf, size_t bsize ); ++extern int CYC2_info( Altera_desc *desc ); ++extern int CYC2_reloc( Altera_desc *desc, ulong reloc_off ); ++ + /* Slave Serial Implementation function table */ + typedef struct { + Altera_pre_fn pre; +@@ -48,6 +53,18 @@ typedef struct { + int relocated; + } Altera_ACEX1K_Passive_Serial_fns; + ++/* Slave Serial Implementation function table */ ++typedef struct { ++ Altera_pre_fn pre; ++ Altera_config_fn config; ++ Altera_status_fn status; ++ Altera_done_fn done; ++ Altera_write_fn write; ++ Altera_abort_fn abort; ++ Altera_post_fn post; ++ int relocated; ++} Altera_CYC2_Passive_Serial_fns; ++ + /* Device Image Sizes + *********************************************************************/ + /* ACEX1K */ +@@ -60,6 +77,8 @@ typedef struct { + #endif + #define Altera_EP1K100_SIZE (166965*8) + ++#define Altera_EP2C35_SIZE 883905 ++ + /* Descriptor Macros + *********************************************************************/ + /* ACEX1K devices */ +diff -Naupr u-boot-1.1.6/include/altera.h u-boot-1.1.6-fsl-1/include/altera.h +--- u-boot-1.1.6/include/altera.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/altera.h 2006-11-30 12:34:13.000000000 -0600 +@@ -34,8 +34,10 @@ + /* Altera Model definitions + *********************************************************************/ + #define CFG_ACEX1K CFG_FPGA_DEV( 0x1 ) ++#define CFG_CYCLON2 CFG_FPGA_DEV( 0x2 ) + + #define CFG_ALTERA_ACEX1K (CFG_FPGA_ALTERA | CFG_ACEX1K) ++#define CFG_ALTERA_CYCLON2 (CFG_FPGA_ALTERA | CFG_CYCLON2) + /* Add new models here */ + + /* Altera Interface definitions +@@ -56,6 +58,7 @@ typedef enum { /* typedef Altera_ifac + typedef enum { /* typedef Altera_Family */ + min_altera_type, /* insert all new types after this */ + Altera_ACEX1K, /* ACEX1K Family */ ++ Altera_CYC2, /* CYCLONII Family */ + /* Add new models here */ + max_altera_type /* insert all new types before this */ + } Altera_Family; /* end, typedef Altera_Family */ +@@ -84,6 +87,7 @@ typedef int (*Altera_status_fn)( int coo + typedef int (*Altera_done_fn)( int cookie ); + typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie ); + typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie ); ++typedef int (*Altera_write_fn)(void *buf, size_t len, int flush, int cookie); + typedef int (*Altera_abort_fn)( int cookie ); + typedef int (*Altera_post_fn)( int cookie ); + +diff -Naupr u-boot-1.1.6/include/asm-ppc/e300.h u-boot-1.1.6-fsl-1/include/asm-ppc/e300.h +--- u-boot-1.1.6/include/asm-ppc/e300.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/asm-ppc/e300.h 2006-11-10 11:24:29.000000000 -0600 +@@ -12,6 +12,8 @@ + #define PVR_83xx 0x80830000 + #define PVR_8349_REV10 (PVR_83xx | 0x0010) + #define PVR_8349_REV11 (PVR_83xx | 0x0011) ++#define PVR_8360_REV10 (PVR_83xx | 0x0020) ++#define PVR_8360_REV11 (PVR_83xx | 0x0020) + + /* + * Hardware Implementation-Dependent Register 0 (HID0) +diff -Naupr u-boot-1.1.6/include/asm-ppc/fsl_i2c.h u-boot-1.1.6-fsl-1/include/asm-ppc/fsl_i2c.h +--- u-boot-1.1.6/include/asm-ppc/fsl_i2c.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/asm-ppc/fsl_i2c.h 2006-11-30 12:34:13.000000000 -0600 +@@ -83,8 +83,4 @@ typedef struct fsl_i2c { + u8 res6[0xE8]; + } fsl_i2c_t; + +- +-#define I2C_READ 1 +-#define I2C_WRITE 0 +- + #endif /* _ASM_I2C_H_ */ +diff -Naupr u-boot-1.1.6/include/asm-ppc/global_data.h u-boot-1.1.6-fsl-1/include/asm-ppc/global_data.h +--- u-boot-1.1.6/include/asm-ppc/global_data.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/asm-ppc/global_data.h 2006-11-10 11:24:29.000000000 -0600 +@@ -52,17 +52,29 @@ typedef struct global_data { + #if defined(CONFIG_MPC83XX) + /* There are other clocks in the MPC83XX */ + u32 csb_clk; ++#if defined (CONFIG_MPC8349) + u32 tsec1_clk; + u32 tsec2_clk; +- u32 core_clk; + u32 usbmph_clk; + u32 usbdr_clk; +- u32 i2c_clk; ++#endif /* CONFIG_MPC8349 */ ++ u32 core_clk; ++ u32 i2c1_clk; ++ u32 i2c2_clk; + u32 enc_clk; + u32 lbiu_clk; + u32 lclk_clk; + u32 ddr_clk; + u32 pci_clk; ++#if defined(CONFIG_QE) ++ u32 qe_clk; ++ u32 brg_clk; ++ uint mp_alloc_base; ++ uint mp_alloc_top; ++#endif /* CONFIG_QE */ ++#if defined (CONFIG_MPC8360) ++ u32 ddr_sec_clk; ++#endif /* CONFIG_MPC8360 */ + #endif + #if defined(CONFIG_MPC5xxx) + unsigned long ipb_clk; +diff -Naupr u-boot-1.1.6/include/asm-ppc/i2c.h u-boot-1.1.6-fsl-1/include/asm-ppc/i2c.h +--- u-boot-1.1.6/include/asm-ppc/i2c.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/asm-ppc/i2c.h 1969-12-31 18:00:00.000000000 -0600 +@@ -1,103 +0,0 @@ +-/* +- * Freescale I2C Controller +- * +- * This software may be used and distributed according to the +- * terms of the GNU Public License, Version 2, incorporated +- * herein by reference. +- * +- * Copyright 2004 Freescale Semiconductor. +- * (C) Copyright 2003, Motorola, Inc. +- * author: Eran Liberty (liberty@freescale.com) +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, +- * MA 02111-1307 USA +- */ +- +-#ifndef _ASM_I2C_H_ +-#define _ASM_I2C_H_ +- +-#include +- +-typedef struct i2c +-{ +- u8 adr; /**< I2C slave address */ +-#define I2C_ADR 0xFE +-#define I2C_ADR_SHIFT 1 +-#define I2C_ADR_RES ~(I2C_ADR) +- u8 res0[3]; +- u8 fdr; /**< I2C frequency divider register */ +-#define IC2_FDR 0x3F +-#define IC2_FDR_SHIFT 0 +-#define IC2_FDR_RES ~(IC2_FDR) +- u8 res1[3]; +- u8 cr; /**< I2C control redister */ +-#define I2C_CR_MEN 0x80 +-#define I2C_CR_MIEN 0x40 +-#define I2C_CR_MSTA 0x20 +-#define I2C_CR_MTX 0x10 +-#define I2C_CR_TXAK 0x08 +-#define I2C_CR_RSTA 0x04 +-#define I2C_CR_BCST 0x01 +- u8 res2[3]; +- u8 sr; /**< I2C status register */ +-#define I2C_SR_MCF 0x80 +-#define I2C_SR_MAAS 0x40 +-#define I2C_SR_MBB 0x20 +-#define I2C_SR_MAL 0x10 +-#define I2C_SR_BCSTM 0x08 +-#define I2C_SR_SRW 0x04 +-#define I2C_SR_MIF 0x02 +-#define I2C_SR_RXAK 0x01 +- u8 res3[3]; +- u8 dr; /**< I2C data register */ +-#define I2C_DR 0xFF +-#define I2C_DR_SHIFT 0 +-#define I2C_DR_RES ~(I2C_DR) +- u8 res4[3]; +- u8 dfsrr; /**< I2C digital filter sampling rate register */ +-#define I2C_DFSRR 0x3F +-#define I2C_DFSRR_SHIFT 0 +-#define I2C_DFSRR_RES ~(I2C_DR) +- u8 res5[3]; +- u8 res6[0xE8]; +-} i2c_t; +- +-#ifndef CFG_HZ +-#error CFG_HZ is not defined in /include/configs/${BOARD}.h +-#endif +-#define I2C_TIMEOUT (CFG_HZ/4) +- +-#ifndef CFG_IMMRBAR +-#error CFG_IMMRBAR is not defined in /include/configs/${BOARD}.h +-#endif +- +-#ifndef CFG_I2C_OFFSET +-#error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h +-#endif +- +-#if defined(CONFIG_MPC8349EMDS) || defined(CONFIG_TQM834X) +-/* +- * MPC8349 have two i2c bus +- */ +-extern i2c_t * mpc8349_i2c; +-#define I2C mpc8349_i2c +-#else +-#define I2C ((i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET)) +-#endif +- +-#define I2C_READ 1 +-#define I2C_WRITE 0 +- +-#endif /* _ASM_I2C_H_ */ +diff -Naupr u-boot-1.1.6/include/asm-ppc/immap_83xx.h u-boot-1.1.6-fsl-1/include/asm-ppc/immap_83xx.h +--- u-boot-1.1.6/include/asm-ppc/immap_83xx.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/asm-ppc/immap_83xx.h 2006-12-06 10:33:49.000000000 -0600 +@@ -1,75 +1,116 @@ + /* +- * MPC8349 Internal Memory Map +- * Copyright (c) 2004 Freescale Semiconductor. +- * Eran Liberty (liberty@freescale.com) ++ * (C) Copyright 2004-2006 Freescale Semiconductor, Inc. ++ * ++ * MPC83xx Internal Memory Map ++ * ++ * History : ++ * 20060601: Daveliu (daveliu@freescale.com) ++ * TanyaJiang (tanya.jiang@freescale.com) ++ * Unified variable names for mpc83xx ++ * 2005 : Mandy Lavi (mandy.lavi@freescale.com) ++ * support for mpc8360e ++ * 2004 : Eran Liberty (liberty@freescale.com) ++ * Initialized for mpc8349 ++ * based on: ++ * MPC8260 Internal Memory Map ++ * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) ++ * MPC85xx Internal Memory Map ++ * Copyright(c) 2002,2003 Motorola Inc. ++ * Xianghua Xiao (x.xiao@motorola.com) ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA + * +- * based on: +- * - MPC8260 Internal Memory Map +- * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) +- * - MPC85xx Internal Memory Map +- * Copyright(c) 2002,2003 Motorola Inc. +- * Xianghua Xiao (x.xiao@motorola.com) + */ +-#ifndef __IMMAP_8349__ +-#define __IMMAP_8349__ ++#ifndef __IMMAP_83xx__ ++#define __IMMAP_83xx__ + ++#include + #include +-#include ++#include + + /* + * Local Access Window. + */ +-typedef struct law8349 { +- u32 bar; /* LBIU local access window base address register */ ++typedef struct law83xx { ++ u32 bar; /* LBIU local access window base address register */ + /* Identifies the 20 most-significant address bits of the base of local + * access window n. The specified base address should be aligned to the + * window size, as defined by LBLAWARn[SIZE]. + */ +-#define LAWBAR_BAR 0xFFFFF000 ++#define LAWBAR_BAR 0xFFFFF000 + #define LAWBAR_RES ~(LAWBAR_BAR) +- u32 ar; /* LBIU local access window attribute register */ +-} law8349_t; ++ u32 ar; /* LBIU local access window attribute register */ ++} law83xx_t; + + /* + * System configuration registers. + */ +-typedef struct sysconf8349 { +- u32 immrbar; /* Internal memory map base address register */ ++typedef struct sysconf83xx { ++ u32 immrbar; /* Internal memory map base address register */ + u8 res0[0x04]; +- u32 altcbar; /* Alternate configuration base address register */ ++ u32 altcbar; /* Alternate configuration base address register */ + /* Identifies the12 most significant address bits of an alternate base + * address used for boot sequencer configuration accesses. + */ + #define ALTCBAR_BASE_ADDR 0xFFF00000 +-#define ALTCBAR_RES ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */ ++#define ALTCBAR_RES ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */ + u8 res1[0x14]; +- law8349_t lblaw[4]; /* LBIU local access window */ ++ law83xx_t lblaw[4]; /* LBIU local access window */ + u8 res2[0x20]; +- law8349_t pcilaw[2]; /* PCI local access window */ ++ law83xx_t pcilaw[2]; /* PCI local access window */ + u8 res3[0x30]; +- law8349_t ddrlaw[2]; /* DDR local access window */ ++ law83xx_t ddrlaw[2]; /* DDR local access window */ + u8 res4[0x50]; +- u32 sgprl; /* System General Purpose Register Low */ +- u32 sgprh; /* System General Purpose Register High */ +- u32 spridr; /* System Part and Revision ID Register */ +-#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification. */ +-#define SPRIDR_REVID 0x0000FFFF /* Revision Identification. */ ++ u32 sgprl; /* System General Purpose Register Low */ ++ u32 sgprh; /* System General Purpose Register High */ ++ u32 spridr; /* System Part and Revision ID Register */ ++#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification. */ ++#define SPRIDR_REVID 0x0000FFFF /* Revision Identification. */ + u8 res5[0x04]; +- u32 spcr; /* System Priority Configuration Register */ +-#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable. */ +-#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority. */ +-#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable. */ +-#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority. */ +-#define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority. */ +-#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */ +-#define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority. */ +-#define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority. */ +-#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */ +-#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority. */ ++ u32 spcr; /* System Priority Configuration Register */ ++#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable. */ ++#define SPCR_PCIHPE_SHIFT (31-3) ++#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority. */ ++#define SPCR_PCIPR_SHIFT (31-7) ++#define SPCR_OPT 0x00800000 /* Optimize */ ++#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable. */ ++#define SPCR_TBEN_SHIFT (31-9) ++#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority. */ ++#define SPCR_COREPR_SHIFT (31-11) ++#if defined (CONFIG_MPC8349) ++#define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority. */ ++#define SPCR_TSEC1DP_SHIFT (31-19) ++#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */ ++#define SPCR_TSEC1BDP_SHIFT (31-21) ++#define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority. */ ++#define SPCR_TSEC1EP_SHIFT (31-23) ++#define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority. */ ++#define SPCR_TSEC2DP_SHIFT (31-27) ++#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */ ++#define SPCR_TSEC2BDP_SHIFT (31-29) ++#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority. */ ++#define SPCR_TSEC2EP_SHIFT (31-31) + #define SPCR_RES ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \ + | SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \ + | SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP) +- u32 sicrl; /* System General Purpose Register Low */ ++#elif defined (CONFIG_MPC8360) ++#define SPCR_RES ~(SPCR_PCIHPE|SPCR_PCIPR|SPCR_OPT|SPCR_TBEN|SPCR_COREPR) ++#endif ++ u32 sicrl; /* System General Purpose Register Low */ ++#if defined (CONFIG_MPC8349) + #define SICRL_LDP_A 0x80000000 + #define SICRL_USB1 0x40000000 + #define SICRL_USB0 0x20000000 +@@ -91,8 +132,18 @@ typedef struct sysconf8349 { + | SICRL_GPIO1_D | SICRL_GPIO1_E | SICRL_GPIO1_F \ + | SICRL_GPIO1_G | SICRL_GPIO1_H | SICRL_GPIO1_I \ + | SICRL_GPIO1_J | SICRL_GPIO1_K | SICRL_GPIO1_L ) +- u32 sicrh; /* System General Purpose Register High */ ++#elif defined (CONFIG_MPC8360) ++#define SICRL_LDP_A 0xC0000000 ++#define SICRL_LCLK_1 0x10000000 ++#define SICRL_LCLK_2 0x08000000 ++#define SICRL_SRCID_A 0x03000000 ++#define SICRL_IRQ_CKSTP_A 0x00C00000 ++#define SICRL_RES ~(SICRL_LDP_A | SICRL_LCLK_1 | SICRL_LCLK_2 | \ ++ SICRL_SRCID_A | SICRL_IRQ_CKSTP_A) ++#endif ++ u32 sicrh; /* System General Purpose Register High */ + #define SICRH_DDR 0x80000000 ++#if defined (CONFIG_MPC8349) + #define SICRH_TSEC1_A 0x10000000 + #define SICRH_TSEC1_B 0x08000000 + #define SICRH_TSEC1_C 0x04000000 +@@ -117,7 +168,7 @@ typedef struct sysconf8349 { + #define SICRH_GPIO2_H 0x00000060 + #define SICRH_TSOBI1 0x00000002 + #define SICRH_TSOBI2 0x00000001 +-#define SICRh_RES ~( SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \ ++#define SICRH_RES ~( SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \ + | SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \ + | SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \ + | SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \ +@@ -126,207 +177,256 @@ typedef struct sysconf8349 { + | SICRH_GPIO2_D | SICRH_GPIO2_E | SICRH_GPIO2_F \ + | SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \ + | SICRH_TSOBI2) ++#elif defined (CONFIG_MPC8360) ++#define SICRH_SECONDARY_DDR 0x40000000 ++#define SICRH_SDDROE 0x02000000 /* SDDRIOE bit from reset configuration word high. */ ++#define SICRH_UC1EOBI 0x00000004 /* UCC1 Ethernet Output Buffer Impedance. */ ++#define SICRH_UC2E1OBI 0x00000002 /* UCC2 Ethernet pin option 1 Output Buffer Impedance. */ ++#define SICRH_UC2E2OBI 0x00000001 /* UCC2 Ethernet pin option 2 Output Buffer Impedance. */ ++#define SICRH_RES ~(SICRH_DDR | SICRH_SECONDARY_DDR | SICRH_SDDROE | \ ++ SICRH_UC2E1OBI | SICRH_UC2E2OBI | SICRH_UC2E2OBI) ++#endif + u8 res6[0xE4]; +-} sysconf8349_t; ++} sysconf83xx_t; + + /* + * Watch Dog Timer (WDT) Registers + */ +-typedef struct wdt8349 { ++typedef struct wdt83xx { + u8 res0[4]; +- u32 swcrr; /* System watchdog control register */ +- u32 swcnr; /* System watchdog count register */ ++ u32 swcrr; /* System watchdog control register */ ++ u32 swcnr; /* System watchdog count register */ + #define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field. + #define SWCNR_RES ~(SWCNR_SWCN) + u8 res1[2]; +- u16 swsrr; /* System watchdog service register */ ++ u16 swsrr; /* System watchdog service register */ ++#define SWSRR_WS 0x0000FFFF /* Software Watchdog Service Field. */ + u8 res2[0xF0]; +-} wdt8349_t; ++} wdt83xx_t; + + /* + * RTC/PIT Module Registers + */ +-typedef struct rtclk8349 { +- u32 cnr; /* control register */ +-#define CNR_CLEN 0x00000080 /* Clock Enable Control Bit */ +-#define CNR_CLIN 0x00000040 /* Input Clock Control Bit */ +-#define CNR_AIM 0x00000002 /* Alarm Interrupt Mask Bit */ +-#define CNR_SIM 0x00000001 /* Second Interrupt Mask Bit */ +-#define CNR_RES ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM) +- u32 ldr; /* load register */ +- u32 psr; /* prescale register */ +- u32 ctr; /* register */ +- u32 evr; /* event register */ +-#define RTEVR_SIF 0x00000001 /* Second Interrupt Flag Bit */ +-#define RTEVR_AIF 0x00000002 /* Alarm Interrupt Flag Bit */ +-#define RTEVR_RES ~(EVR_SIF | EVR_AIF) +- u32 alr; /* alarm register */ ++typedef struct rtclk83xx { ++ u32 cnr; /* control register */ ++#define CNR_CLEN 0x00000080 /* Clock Enable Control Bit */ ++#define CNR_CLIN 0x00000040 /* Input Clock Control Bit */ ++#define CNR_AIM 0x00000002 /* Alarm Interrupt Mask Bit */ ++#define CNR_SIM 0x00000001 /* Second Interrupt Mask Bit */ ++#define CNR_RES ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM) ++ u32 ldr; /* load register */ ++#define LDR_CLDV 0xFFFFFFFF /* Contains the 32-bit value to be ++ * loaded in a 32-bit RTC counter.*/ ++ u32 psr; /* prescale register */ ++#define PSR_PRSC 0xFFFFFFFF /* RTC Prescaler bits. */ ++ u32 ctr; /* Counter value field register */ ++#define CRT_CNTV 0xFFFFFFFF /* RTC Counter value field. */ ++ u32 evr; /* event register */ ++#define RTEVR_SIF 0x00000001 /* Second Interrupt Flag Bit */ ++#define RTEVR_AIF 0x00000002 /* Alarm Interrupt Flag Bit */ ++#define RTEVR_RES ~(RTEVR_SIF | RTEVR_AIF) ++#define PTEVR_PIF 0x00000001 /* Periodic interrupt flag bit. */ ++#define PTEVR_RES ~(PTEVR_PIF) ++ u32 alr; /* alarm register */ + u8 res0[0xE8]; +-} rtclk8349_t; ++} rtclk83xx_t; + + /* + * Global timper module + */ + +-typedef struct gtm8349 { +- u8 cfr1; /* Timer1/2 Configuration */ +-#define CFR1_PCAS 0x80 /* Pair Cascade mode */ +-#define CFR1_BCM 0x40 /* Backward compatible mode */ +-#define CFR1_STP2 0x20 /* Stop timer */ +-#define CFR1_RST2 0x10 /* Reset timer */ +-#define CFR1_GM2 0x08 /* Gate mode for pin 2 */ +-#define CFR1_GM1 0x04 /* Gate mode for pin 1 */ +-#define CFR1_STP1 0x02 /* Stop timer */ +-#define CFR1_RST1 0x01 /* Reset timer */ +- u8 res0[3]; +- u8 cfr2; /* Timer3/4 Configuration */ +-#define CFR2_PCAS 0x80 /* Pair Cascade mode */ +-#define CFR2_SCAS 0x40 /* Super Cascade mode */ +-#define CFR2_STP4 0x20 /* Stop timer */ +-#define CFR2_RST4 0x10 /* Reset timer */ +-#define CFR2_GM4 0x08 /* Gate mode for pin 4 */ +-#define CFR2_GM3 0x04 /* Gate mode for pin 3 */ +-#define CFR2_STP3 0x02 /* Stop timer */ +-#define CFR2_RST3 0x01 /* Reset timer */ +- u8 res1[10]; +- u16 mdr1; /* Timer1 Mode Register */ +-#define MDR_SPS 0xff00 /* Secondary Prescaler value */ +-#define MDR_CE 0x00c0 /* Capture edge and enable interrupt */ +-#define MDR_OM 0x0020 /* Output mode */ +-#define MDR_ORI 0x0010 /* Output reference interrupt enable */ +-#define MDR_FRR 0x0008 /* Free run/restart */ +-#define MDR_ICLK 0x0006 /* Input clock source for the timer */ +-#define MDR_GE 0x0001 /* Gate enable */ +- u16 mdr2; /* Timer2 Mode Register */ +- u16 rfr1; /* Timer1 Reference Register */ +- u16 rfr2; /* Timer2 Reference Register */ +- u16 cpr1; /* Timer1 Capture Register */ +- u16 cpr2; /* Timer2 Capture Register */ +- u16 cnr1; /* Timer1 Counter Register */ +- u16 cnr2; /* Timer2 Counter Register */ +- u16 mdr3; /* Timer3 Mode Register */ +- u16 mdr4; /* Timer4 Mode Register */ +- u16 rfr3; /* Timer3 Reference Register */ +- u16 rfr4; /* Timer4 Reference Register */ +- u16 cpr3; /* Timer3 Capture Register */ +- u16 cpr4; /* Timer4 Capture Register */ +- u16 cnr3; /* Timer3 Counter Register */ +- u16 cnr4; /* Timer4 Counter Register */ +- u16 evr1; /* Timer1 Event Register */ +- u16 evr2; /* Timer2 Event Register */ +- u16 evr3; /* Timer3 Event Register */ +- u16 evr4; /* Timer4 Event Register */ +-#define GTEVR_REF 0x0002 /* Output reference event */ +-#define GTEVR_CAP 0x0001 /* Counter Capture event */ ++typedef struct gtm83xx { ++ u8 cfr1; /* Timer1/2 Configuration */ ++#define CFR1_PCAS 0x80 /* Pair Cascade mode */ ++#define CFR1_BCM 0x40 /* Backward compatible mode */ ++#define CFR1_STP2 0x20 /* Stop timer */ ++#define CFR1_RST2 0x10 /* Reset timer */ ++#define CFR1_GM2 0x08 /* Gate mode for pin 2 */ ++#define CFR1_GM1 0x04 /* Gate mode for pin 1 */ ++#define CFR1_STP1 0x02 /* Stop timer */ ++#define CFR1_RST1 0x01 /* Reset timer */ ++#define CFR1_RES ~(CFR1_PCAS | CFR1_STP2 | CFR1_RST2 | CFR1_GM2 |\ ++ CFR1_GM1 | CFR1_STP1 | CFR1_RST1) ++ u8 res0[3]; ++ u8 cfr2; /* Timer3/4 Configuration */ ++#define CFR2_PCAS 0x80 /* Pair Cascade mode */ ++#define CFR2_SCAS 0x40 /* Super Cascade mode */ ++#define CFR2_STP4 0x20 /* Stop timer */ ++#define CFR2_RST4 0x10 /* Reset timer */ ++#define CFR2_GM4 0x08 /* Gate mode for pin 4 */ ++#define CFR2_GM3 0x04 /* Gate mode for pin 3 */ ++#define CFR2_STP3 0x02 /* Stop timer */ ++#define CFR2_RST3 0x01 /* Reset timer */ ++ u8 res1[10]; ++ u16 mdr1; /* Timer1 Mode Register */ ++#define MDR_SPS 0xff00 /* Secondary Prescaler value */ ++#define MDR_CE 0x00c0 /* Capture edge and enable interrupt */ ++#define MDR_OM 0x0020 /* Output mode */ ++#define MDR_ORI 0x0010 /* Output reference interrupt enable */ ++#define MDR_FRR 0x0008 /* Free run/restart */ ++#define MDR_ICLK 0x0006 /* Input clock source for the timer */ ++#define MDR_GE 0x0001 /* Gate enable */ ++ u16 mdr2; /* Timer2 Mode Register */ ++ u16 rfr1; /* Timer1 Reference Register */ ++ u16 rfr2; /* Timer2 Reference Register */ ++ u16 cpr1; /* Timer1 Capture Register */ ++ u16 cpr2; /* Timer2 Capture Register */ ++ u16 cnr1; /* Timer1 Counter Register */ ++ u16 cnr2; /* Timer2 Counter Register */ ++ u16 mdr3; /* Timer3 Mode Register */ ++ u16 mdr4; /* Timer4 Mode Register */ ++ u16 rfr3; /* Timer3 Reference Register */ ++ u16 rfr4; /* Timer4 Reference Register */ ++ u16 cpr3; /* Timer3 Capture Register */ ++ u16 cpr4; /* Timer4 Capture Register */ ++ u16 cnr3; /* Timer3 Counter Register */ ++ u16 cnr4; /* Timer4 Counter Register */ ++ u16 evr1; /* Timer1 Event Register */ ++ u16 evr2; /* Timer2 Event Register */ ++ u16 evr3; /* Timer3 Event Register */ ++ u16 evr4; /* Timer4 Event Register */ ++#define GTEVR_REF 0x0002 /* Output reference event */ ++#define GTEVR_CAP 0x0001 /* Counter Capture event */ + #define GTEVR_RES ~(EVR_CAP|EVR_REF) +- u16 psr1; /* Timer1 Prescaler Register */ +- u16 psr2; /* Timer2 Prescaler Register */ +- u16 psr3; /* Timer3 Prescaler Register */ +- u16 psr4; /* Timer4 Prescaler Register */ +- u8 res[0xC0]; +-} gtm8349_t; ++ u16 psr1; /* Timer1 Prescaler Register */ ++ u16 psr2; /* Timer2 Prescaler Register */ ++ u16 psr3; /* Timer3 Prescaler Register */ ++ u16 psr4; /* Timer4 Prescaler Register */ ++#define GTPSR_PPS 0x00FF /* Primary Prescaler Bits. */ ++#define GTPSR_RES ~(GTPSR_PPS) ++ u8 res[0xC0]; ++} gtm83xx_t; + + /* + * Integrated Programmable Interrupt Controller + */ +-typedef struct ipic8349 { +- u32 sicfr; /* System Global Interrupt Configuration Register (SICFR) */ +-#define SICFR_HPI 0x7f000000 /* Highest Priority Interrupt */ +-#define SICFR_MPSB 0x00400000 /* Mixed interrupts Priority Scheme for group B */ +-#define SICFR_MPSA 0x00200000 /* Mixed interrupts Priority Scheme for group A */ +-#define SICFR_IPSD 0x00080000 /* Internal interrupts Priority Scheme for group D */ +-#define SICFR_IPSA 0x00010000 /* Internal interrupts Priority Scheme for group A */ +-#define SICFR_HPIT 0x00000300 /* HPI priority position IPIC output interrupt Type */ ++typedef struct ipic83xx { ++ u32 sicfr; /* System Global Interrupt Configuration Register (SICFR) */ ++#define SICFR_HPI 0x7f000000 /* Highest Priority Interrupt */ ++#define SICFR_MPSB 0x00400000 /* Mixed interrupts Priority Scheme for group B */ ++#define SICFR_MPSA 0x00200000 /* Mixed interrupts Priority Scheme for group A */ ++#define SICFR_IPSD 0x00080000 /* Internal interrupts Priority Scheme for group D */ ++#define SICFR_IPSA 0x00010000 /* Internal interrupts Priority Scheme for group A */ ++#define SICFR_HPIT 0x00000300 /* HPI priority position IPIC output interrupt Type */ + #define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT) +- u32 sivcr; /* System Global Interrupt Vector Register (SIVCR) */ +-#define SICVR_IVECX 0xfc000000 /* Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation) */ +-#define SICVR_IVEC 0x0000007f /* Interrupt vector */ ++ u32 sivcr; /* System Global Interrupt Vector Register (SIVCR) */ ++#define SICVR_IVECX 0xfc000000 /* Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation) */ ++#define SICVR_IVEC 0x0000007f /* Interrupt vector */ + #define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC) +- u32 sipnr_h; /* System Internal Interrupt Pending Register - High (SIPNR_H) */ +-#define SIIH_TSEC1TX 0x80000000 /* TSEC1 Tx interrupt */ +-#define SIIH_TSEC1RX 0x40000000 /* TSEC1 Rx interrupt */ ++ u32 sipnr_h; /* System Internal Interrupt Pending Register - High (SIPNR_H) */ ++#if defined (CONFIG_MPC8349) ++#define SIIH_TSEC1TX 0x80000000 /* TSEC1 Tx interrupt */ ++#define SIIH_TSEC1RX 0x40000000 /* TSEC1 Rx interrupt */ + #define SIIH_TSEC1ER 0x20000000 /* TSEC1 Eror interrupt */ +-#define SIIH_TSEC2TX 0x10000000 /* TSEC2 Tx interrupt */ +-#define SIIH_TSEC2RX 0x08000000 /* TSEC2 Rx interrupt */ ++#define SIIH_TSEC2TX 0x10000000 /* TSEC2 Tx interrupt */ ++#define SIIH_TSEC2RX 0x08000000 /* TSEC2 Rx interrupt */ + #define SIIH_TSEC2ER 0x04000000 /* TSEC2 Eror interrupt */ + #define SIIH_USB2DR 0x02000000 /* USB2 DR interrupt */ +-#define SIIH_USB2MPH 0x01000000 /* USB2 MPH interrupt */ ++#define SIIH_USB2MPH 0x01000000 /* USB2 MPH interrupt */ ++#endif ++#if defined (CONFIG_MPC8360) ++#define SIIH_H_QE_H 0x80000000 /* QE high interrupt */ ++#define SIIH_H_QE_L 0x40000000 /* QE low interrupt */ ++#endif + #define SIIH_UART1 0x00000080 /* UART1 interrupt */ + #define SIIH_UART2 0x00000040 /* UART2 interrupt */ + #define SIIH_SEC 0x00000020 /* SEC interrupt */ + #define SIIH_I2C1 0x00000004 /* I2C1 interrupt */ +-#define SIIH_I2C2 0x00000002 /* I2C1 interrupt */ ++#define SIIH_I2C2 0x00000002 /* I2C2 interrupt */ ++#if defined (CONFIG_MPC8349) + #define SIIH_SPI 0x00000001 /* SPI interrupt */ + #define SIIH_RES ~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \ + | SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \ + | SIIH_USB2DR | SIIH_USB2MPH | SIIH_UART1 \ + | SIIH_UART2 | SIIH_SEC | SIIH_I2C1 \ + | SIIH_I2C2 | SIIH_SPI) +- u32 sipnr_l; /* System Internal Interrupt Pending Register - Low (SIPNR_L) */ +-#define SIIL_RTCS 0x80000000 /* RTC SECOND interrupt */ +-#define SIIL_PIT 0x40000000 /* PIT interrupt */ +-#define SIIL_PCI1 0x20000000 /* PCI1 interrupt */ +-#define SIIL_PCI2 0x10000000 /* PCI2 interrupt */ +-#define SIIL_RTCA 0x08000000 /* RTC ALARM interrupt */ +-#define SIIL_MU 0x04000000 /* Message Unit interrupt */ +-#define SIIL_SBA 0x02000000 /* System Bus Arbiter interrupt */ +-#define SIIL_DMA 0x01000000 /* DMA interrupt */ +-#define SIIL_GTM4 0x00800000 /* GTM4 interrupt */ +-#define SIIL_GTM8 0x00400000 /* GTM8 interrupt */ +-#define SIIL_GPIO1 0x00200000 /* GPIO1 interrupt */ +-#define SIIL_GPIO2 0x00100000 /* GPIO2 interrupt */ +-#define SIIL_DDR 0x00080000 /* DDR interrupt */ +-#define SIIL_LBC 0x00040000 /* LBC interrupt */ +-#define SIIL_GTM2 0x00020000 /* GTM2 interrupt */ +-#define SIIL_GTM6 0x00010000 /* GTM6 interrupt */ +-#define SIIL_PMC 0x00008000 /* PMC interrupt */ +-#define SIIL_GTM3 0x00000800 /* GTM3 interrupt */ +-#define SIIL_GTM7 0x00000400 /* GTM7 interrupt */ +-#define SIIL_GTM1 0x00000020 /* GTM1 interrupt */ +-#define SIIL_GTM5 0x00000010 /* GTM5 interrupt */ +-#define SIIL_DPTC 0x00000001 /* DPTC interrupt (!!! Invisible for user !!!) */ ++#endif ++#if defined (CONFIG_MPC8360) ++#define SIIH_RES ~(SIIH_H_QE_H | SIIH_H_QE_L | SIIH_H_UART1 | \ ++ SIIH_H_UART2| SIIH_H_SEC | SIIH_H_I2C1 |SIIH_H_I2C2) ++#endif ++ u32 sipnr_l; /* System Internal Interrupt Pending Register - Low (SIPNR_L) */ ++#define SIIL_RTCS 0x80000000 /* RTC SECOND interrupt */ ++#define SIIL_PIT 0x40000000 /* PIT interrupt */ ++#define SIIL_PCI1 0x20000000 /* PCI1 interrupt */ ++#if defined (CONFIG_MPC8349) ++#define SIIL_PCI2 0x10000000 /* PCI2 interrupt */ ++#endif ++#define SIIL_RTCA 0x08000000 /* RTC ALARM interrupt */ ++#define SIIL_MU 0x04000000 /* Message Unit interrupt */ ++#define SIIL_SBA 0x02000000 /* System Bus Arbiter interrupt */ ++#define SIIL_DMA 0x01000000 /* DMA interrupt */ ++#define SIIL_GTM4 0x00800000 /* GTM4 interrupt */ ++#define SIIL_GTM8 0x00400000 /* GTM8 interrupt */ ++#if defined (CONFIG_MPC8349) ++#define SIIL_GPIO1 0x00200000 /* GPIO1 interrupt */ ++#define SIIL_GPIO2 0x00100000 /* GPIO2 interrupt */ ++#endif ++#if defined (CONFIG_MPC8360) ++#define SIIL_QEP 0x00200000 /* QE ports interrupt */ ++#define SIIL_SDDR 0x00100000 /* SDDR interrupt */ ++#endif ++#define SIIL_DDR 0x00080000 /* DDR interrupt */ ++#define SIIL_LBC 0x00040000 /* LBC interrupt */ ++#define SIIL_GTM2 0x00020000 /* GTM2 interrupt */ ++#define SIIL_GTM6 0x00010000 /* GTM6 interrupt */ ++#define SIIL_PMC 0x00008000 /* PMC interrupt */ ++#define SIIL_GTM3 0x00000800 /* GTM3 interrupt */ ++#define SIIL_GTM7 0x00000400 /* GTM7 interrupt */ ++#define SIIL_GTM1 0x00000020 /* GTM1 interrupt */ ++#define SIIL_GTM5 0x00000010 /* GTM5 interrupt */ ++#define SIIL_DPTC 0x00000001 /* DPTC interrupt (!!! Invisible for user !!!) */ ++#if defined (CONFIG_MPC8349) + #define SIIL_RES ~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \ + | SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \ + | SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \ + | SIIL_DDR | SIIL_LBC | SIIL_GTM2 | SIIL_GTM6 \ + | SIIL_PMC |SIIL_GTM3 | SIIL_GTM7 | SIIL_GTM1 \ + | SIIL_GTM5 |SIIL_DPTC ) +- u32 siprr_a; /* System Internal Interrupt Group A Priority Register (PRR) */ +- u8 res0[8]; +- u32 siprr_d; /* System Internal Interrupt Group D Priority Register (PRR) */ +- u32 simsr_h; /* System Internal Interrupt Mask Register - High (SIIH) */ +- u32 simsr_l; /* System Internal Interrupt Mask Register - Low (SIIL) */ +- u8 res1[4]; +- u32 sepnr; /* System External Interrupt Pending Register (SEI) */ +- u32 smprr_a; /* System Mixed Interrupt Group A Priority Register (PRR) */ +- u32 smprr_b; /* System Mixed Interrupt Group B Priority Register (PRR) */ +-#define PRR_0 0xe0000000 /* Priority Register, Position 0 programming */ +-#define PRR_1 0x1c000000 /* Priority Register, Position 1 programming */ +-#define PRR_2 0x03800000 /* Priority Register, Position 2 programming */ +-#define PRR_3 0x00700000 /* Priority Register, Position 3 programming */ +-#define PRR_4 0x0000e000 /* Priority Register, Position 4 programming */ +-#define PRR_5 0x00001c00 /* Priority Register, Position 5 programming */ +-#define PRR_6 0x00000380 /* Priority Register, Position 6 programming */ +-#define PRR_7 0x00000070 /* Priority Register, Position 7 programming */ ++#endif ++#if defined (CONFIG_MPC8360) ++#define SIIL_RES ~(SIIL_RTCS |SIIL_PIT |SIIL_PCI1 |SIIL_RTCALR \ ++ |SIIL_MU |SIIL_SBA |SIIL_DMA |SIIL_GTM4 |SIIL_GTM8 \ ++ |SIIL_QEP | SIIL_SDDR| SIIL_DDR |SIIL_LBC |SIIL_GTM2 \ ++ |SIIL_GTM6 |SIIL_PMC |SIIL_GTM3 |SIIL_GTM7 |SIIL_GTM1 \ ++ |SIIL_GTM5 ) ++#endif ++ u32 siprr_a; /* System Internal Interrupt Group A Priority Register (PRR) */ ++ u8 res0[8]; ++ u32 siprr_d; /* System Internal Interrupt Group D Priority Register (PRR) */ ++ u32 simsr_h; /* System Internal Interrupt Mask Register - High (SIIH) */ ++ u32 simsr_l; /* System Internal Interrupt Mask Register - Low (SIIL) */ ++ u8 res1[4]; ++ u32 sepnr; /* System External Interrupt Pending Register (SEI) */ ++ u32 smprr_a; /* System Mixed Interrupt Group A Priority Register (PRR) */ ++ u32 smprr_b; /* System Mixed Interrupt Group B Priority Register (PRR) */ ++#define PRR_0 0xe0000000 /* Priority Register, Position 0 programming */ ++#define PRR_1 0x1c000000 /* Priority Register, Position 1 programming */ ++#define PRR_2 0x03800000 /* Priority Register, Position 2 programming */ ++#define PRR_3 0x00700000 /* Priority Register, Position 3 programming */ ++#define PRR_4 0x0000e000 /* Priority Register, Position 4 programming */ ++#define PRR_5 0x00001c00 /* Priority Register, Position 5 programming */ ++#define PRR_6 0x00000380 /* Priority Register, Position 6 programming */ ++#define PRR_7 0x00000070 /* Priority Register, Position 7 programming */ + #define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7) +- u32 semsr; /* System External Interrupt Mask Register (SEI) */ +-#define SEI_IRQ0 0x80000000 /* IRQ0 external interrupt */ +-#define SEI_IRQ1 0x40000000 /* IRQ1 external interrupt */ +-#define SEI_IRQ2 0x20000000 /* IRQ2 external interrupt */ +-#define SEI_IRQ3 0x10000000 /* IRQ3 external interrupt */ +-#define SEI_IRQ4 0x08000000 /* IRQ4 external interrupt */ +-#define SEI_IRQ5 0x04000000 /* IRQ5 external interrupt */ +-#define SEI_IRQ6 0x02000000 /* IRQ6 external interrupt */ +-#define SEI_IRQ7 0x01000000 /* IRQ7 external interrupt */ +-#define SEI_SIRQ0 0x00008000 /* SIRQ0 external interrupt */ ++ u32 semsr; /* System External Interrupt Mask Register (SEI) */ ++#define SEI_IRQ0 0x80000000 /* IRQ0 external interrupt */ ++#define SEI_IRQ1 0x40000000 /* IRQ1 external interrupt */ ++#define SEI_IRQ2 0x20000000 /* IRQ2 external interrupt */ ++#define SEI_IRQ3 0x10000000 /* IRQ3 external interrupt */ ++#define SEI_IRQ4 0x08000000 /* IRQ4 external interrupt */ ++#define SEI_IRQ5 0x04000000 /* IRQ5 external interrupt */ ++#define SEI_IRQ6 0x02000000 /* IRQ6 external interrupt */ ++#define SEI_IRQ7 0x01000000 /* IRQ7 external interrupt */ ++#define SEI_SIRQ0 0x00008000 /* SIRQ0 external interrupt */ + #define SEI_RES ~( SEI_IRQ0 | SEI_IRQ1 | SEI_IRQ2 | SEI_IRQ3 \ + | SEI_IRQ4 | SEI_IRQ5 | SEI_IRQ6 | SEI_IRQ7 \ + | SEI_SIRQ0) +- u32 secnr; /* System External Interrupt Control Register (SECNR) */ +-#define SECNR_MIXB0T 0xc0000000 /* MIXB0 priority position IPIC output interrupt type */ +-#define SECNR_MIXB1T 0x30000000 /* MIXB1 priority position IPIC output interrupt type */ +-#define SECNR_MIXA0T 0x00c00000 /* MIXA0 priority position IPIC output interrupt type */ +-#define SECNR_SYSA1T 0x00300000 /* MIXA1 priority position IPIC output interrupt type */ ++ u32 secnr; /* System External Interrupt Control Register (SECNR) */ ++#define SECNR_MIXB0T 0xc0000000 /* MIXB0 priority position IPIC output interrupt type */ ++#define SECNR_MIXB1T 0x30000000 /* MIXB1 priority position IPIC output interrupt type */ ++#define SECNR_MIXA0T 0x00c00000 /* MIXA0 priority position IPIC output interrupt type */ ++#define SECNR_SYSA1T 0x00300000 /* MIXA1 priority position IPIC output interrupt type */ + #define SECNR_EDI0 0x00008000 /* IRQ0 external interrupt edge/level detect */ + #define SECNR_EDI1 0x00004000 /* IRQ1 external interrupt edge/level detect */ + #define SECNR_EDI2 0x00002000 /* IRQ2 external interrupt edge/level detect */ +@@ -339,176 +439,238 @@ typedef struct ipic8349 { + | SECNR_SYSA1T | SECNR_EDI0 | SECNR_EDI1 \ + | SECNR_EDI2 | SECNR_EDI3 | SECNR_EDI4 \ + | SECNR_EDI5 | SECNR_EDI6 | SECNR_EDI7) +- u32 sersr; /* System Error Status Register (SERR) */ +- u32 sermr; /* System Error Mask Register (SERR) */ +-#define SERR_IRQ0 0x80000000 /* IRQ0 MCP request */ +-#define SERR_WDT 0x40000000 /* WDT MCP request */ +-#define SERR_SBA 0x20000000 /* SBA MCP request */ +-#define SERR_DDR 0x10000000 /* DDR MCP request */ +-#define SERR_LBC 0x08000000 /* LBC MCP request */ +-#define SERR_PCI1 0x04000000 /* PCI1 MCP request */ +-#define SERR_PCI2 0x02000000 /* PCI2 MCP request */ +-#define SERR_MU 0x01000000 /* MU MCP request */ +-#define SERR_RNC 0x00010000 /* MU MCP request (!!! Non-visible for users !!!) */ ++ u32 sersr; /* System Error Status Register (SERR) */ ++ u32 sermr; /* System Error Mask Register (SERR) */ ++#define SERR_IRQ0 0x80000000 /* IRQ0 MCP request */ ++#define SERR_WDT 0x40000000 /* WDT MCP request */ ++#define SERR_SBA 0x20000000 /* SBA MCP request */ ++#if defined (CONFIG_MPC8349) ++#define SERR_DDR 0x10000000 /* DDR MCP request */ ++#define SERR_LBC 0x08000000 /* LBC MCP request */ ++#define SERR_PCI1 0x04000000 /* PCI1 MCP request */ ++#define SERR_PCI2 0x02000000 /* PCI2 MCP request */ ++#endif ++#if defined (CONFIG_MPC8360) ++#define SERR_CIEE 0x10000000 /* CIEE MCP request */ ++#define SERR_CMEE 0x08000000 /* CMEEMCP request */ ++#define SERR_PCI 0x04000000 /* PCI MCP request */ ++#endif ++#define SERR_MU 0x01000000 /* MU MCP request */ ++#define SERR_RNC 0x00010000 /* MU MCP request (!!! Non-visible for users !!!) */ ++#if defined (CONFIG_MPC8349) + #define SERR_RES ~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \ + |SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \ + |SERR_RNC ) +- u32 sercr; /* System Error Control Register (SERCR) */ +-#define SERCR_MCPR 0x00000001 /* MCP Route */ ++#elif defined (CONFIG_MPC8360) ++#define SERR_RES ~( SERR_IRQ0|SERR_WDT |SERR_SBA |SERR_CIEE\ ++ |SERR_CMEE|SERR_PCI|SERR_MU) ++#endif ++ u32 sercr; /* System Error Control Register (SERCR) */ ++#define SERCR_MCPR 0x00000001 /* MCP Route */ + #define SERCR_RES ~(SERCR_MCPR) +- u8 res2[4]; +- u32 sifcr_h; /* System Internal Interrupt Force Register - High (SIIH) */ +- u32 sifcr_l; /* System Internal Interrupt Force Register - Low (SIIL) */ +- u32 sefcr; /* System External Interrupt Force Register (SEI) */ +- u32 serfr; /* System Error Force Register (SERR) */ +- u8 res3[0xA0]; +-} ipic8349_t; ++ u8 res2[4]; ++ u32 sifcr_h; /* System Internal Interrupt Force Register - High (SIIH) */ ++ u32 sifcr_l; /* System Internal Interrupt Force Register - Low (SIIL) */ ++ u32 sefcr; /* System External Interrupt Force Register (SEI) */ ++ u32 serfr; /* System Error Force Register (SERR) */ ++ u32 scvcr; /* System Critical Interrupt Vector Register */ ++#define SCVCR_CVECX 0xFC000000 /* Backward (MPC8260) compatible ++ critical interrupt vector. */ ++#define SCVCR_CVEC 0x0000007F /* Critical interrupt vector */ ++#define SCVCR_RES ~(SCVCR_CVECX|SCVCR_CVEC) ++ u32 smvcr; /* System Management Interrupt Vector Register */ ++#define SMVCR_CVECX 0xFC000000 /* Backward (MPC8260) compatible ++ critical interrupt vector. */ ++#define SMVCR_CVEC 0x0000007F /* Critical interrupt vector */ ++#define SMVCR_RES ~(SMVCR_CVECX|SMVCR_CVEC) ++ u8 res3[0x98]; ++} ipic83xx_t; + + /* + * System Arbiter Registers + */ +-typedef struct arbiter8349 { +- u32 acr; /* Arbiter Configuration Register */ +-#define ACR_COREDIS 0x10000000 /* Core disable. */ +-#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth (number of outstanding transactions). */ +-#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */ +-#define ACR_RPTCNT 0x00000700 /* Repeat count. */ +-#define ACR_APARK 0x00000030 /* Address parking. */ +-#define ACR_PARKM 0x0000000F /* Parking master. */ ++typedef struct arbiter83xx { ++ u32 acr; /* Arbiter Configuration Register */ ++#define ACR_COREDIS 0x10000000 /* Core disable. */ ++#define ACR_COREDIS_SHIFT (31-7) ++#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth (number of outstanding transactions). */ ++#define ACR_PIPE_DEP_SHIFT (31-15) ++#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */ ++#define ACR_PCI_RPTCNT_SHIFT (31-19) ++#define ACR_RPTCNT 0x00000700 /* Repeat count. */ ++#define ACR_RPTCNT_SHIFT (31-23) ++#define ACR_APARK 0x00000030 /* Address parking. */ ++#define ACR_APARK_SHIFT (31-27) ++#define ACR_PARKM 0x0000000F /* Parking master. */ ++#define ACR_PARKM_SHIFT (31-31) + #define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM) +- u32 atr; /* Arbiter Timers Register */ +-#define ATR_DTO 0x00FF0000 /* Data time out. */ +-#define ATR_ATO 0x000000FF /* Address time out. */ ++ u32 atr; /* Arbiter Timers Register */ ++#define ATR_DTO 0x00FF0000 /* Data time out. */ ++#define ATR_ATO 0x000000FF /* Address time out. */ + #define ATR_RES ~(ATR_DTO|ATR_ATO) + u8 res[4]; +- u32 aer; /* Arbiter Event Register (AE)*/ +- u32 aidr; /* Arbiter Interrupt Definition Register (AE) */ +- u32 amr; /* Arbiter Mask Register (AE) */ +- u32 aeatr; /* Arbiter Event Attributes Register */ +-#define AEATR_EVENT 0x07000000 /* Event type. */ +-#define AEATR_MSTR_ID 0x001F0000 /* Master Id. */ +-#define AEATR_TBST 0x00000800 /* Transfer burst. */ +-#define AEATR_TSIZE 0x00000700 /* Transfer Size. */ +-#define AEATR_TTYPE 0x0000001F /* Transfer Type. */ ++ u32 aer; /* Arbiter Event Register (AE) */ ++ u32 aidr; /* Arbiter Interrupt Definition Register (AE) */ ++ u32 amr; /* Arbiter Mask Register (AE) */ ++ u32 aeatr; /* Arbiter Event Attributes Register */ ++#define AEATR_EVENT 0x07000000 /* Event type. */ ++#define AEATR_MSTR_ID 0x001F0000 /* Master Id. */ ++#define AEATR_TBST 0x00000800 /* Transfer burst. */ ++#define AEATR_TSIZE 0x00000700 /* Transfer Size. */ ++#define AEATR_TTYPE 0x0000001F /* Transfer Type. */ + #define AEATR_RES ~(AEATR_EVENT|AEATR_MSTR_ID|AEATR_TBST|AEATR_TSIZE|AEATR_TTYPE) +- u32 aeadr; /* Arbiter Event Address Register */ +- u32 aerr; /* Arbiter Event Response Register (AE)*/ +-#define AE_ETEA 0x00000020 /* Transfer error. */ +-#define AE_RES_ 0x00000010 /* Reserved transfer type. */ +-#define AE_ECW 0x00000008 /* External control word transfer type. */ +-#define AE_AO 0x00000004 /* Address Only transfer type. */ +-#define AE_DTO 0x00000002 /* Data time out. */ +-#define AE_ATO 0x00000001 /* Address time out. */ ++ u32 aeadr; /* Arbiter Event Address Register */ ++ u32 aerr; /* Arbiter Event Response Register (AE) */ ++#define AE_ETEA 0x00000020 /* Transfer error. */ ++#define AE_RES_ 0x00000010 /* Reserved transfer type. */ ++#define AE_ECW 0x00000008 /* External control word transfer type. */ ++#define AE_AO 0x00000004 /* Address Only transfer type. */ ++#define AE_DTO 0x00000002 /* Data time out. */ ++#define AE_ATO 0x00000001 /* Address time out. */ + #define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO) + u8 res1[0xDC]; +-} arbiter8349_t; ++} arbiter83xx_t; + + /* + * Reset Module + */ +-typedef struct reset8349 { +- u32 rcwl; /* RCWL Register */ ++typedef struct reset83xx { ++ u32 rcwl; /* RCWL Register */ + #define RCWL_LBIUCM 0x80000000 /* LBIUCM */ + #define RCWL_LBIUCM_SHIFT 31 + #define RCWL_DDRCM 0x40000000 /* DDRCM */ + #define RCWL_DDRCM_SHIFT 30 ++#if defined (CONFIG_MPC8349) + #define RCWL_SVCOD 0x30000000 /* SVCOD */ +-#define RCWL_SPMF 0x0f000000 /* SPMF */ +-#define RCWL_SPMF_SHIFT 24 ++#endif ++#define RCWL_SPMF 0x0f000000 /* SPMF */ ++#define RCWL_SPMF_SHIFT 24 + #define RCWL_COREPLL 0x007F0000 /* COREPLL */ + #define RCWL_COREPLL_SHIFT 16 + #define RCWL_CEVCOD 0x000000C0 /* CEVCOD */ + #define RCWL_CEPDF 0x00000020 /* CEPDF */ ++#define RCWL_CEPDF_SHIFT 5 + #define RCWL_CEPMF 0x0000001F /* CEPMF */ +-#define RCWL_RES ~(RCWL_BIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF) +- u32 rcwh; /* RCHL Register */ ++#define RCWL_CEPMF_SHIFT 0 ++#if defined (CONFIG_MPC8349) ++#define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF) ++#elif defined (CONFIG_MPC8360) ++#define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SPMF|RCWL_COREPLL|RCWL_CEPDF|RCWL_CEPMF) ++#endif ++ u32 rcwh; /* RCHL Register */ + #define RCWH_PCIHOST 0x80000000 /* PCIHOST */ + #define RCWH_PCIHOST_SHIFT 31 ++#if defined (CONFIG_MPC8349) + #define RCWH_PCI64 0x40000000 /* PCI64 */ + #define RCWH_PCI1ARB 0x20000000 /* PCI1ARB */ + #define RCWH_PCI2ARB 0x10000000 /* PCI2ARB */ ++#elif defined (CONFIG_MPC8360) ++#define RCWH_PCIARB 0x20000000 /* PCI internal arbiter mode. */ ++#define RCWH_PCICKDRV 0x10000000 /* PCI clock output drive. */ ++#endif + #define RCWH_COREDIS 0x08000000 /* COREDIS */ +-#define RCWH_BMS 0x04000000 /* BMS */ ++#define RCWH_BMS 0x04000000 /* BMS */ + #define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ */ +-#define RCWH_SWEN 0x00800000 /* SWEN */ ++#define RCWH_SWEN 0x00800000 /* SWEN */ + #define RCWH_ROMLOC 0x00700000 /* ROMLOC */ ++#if defined (CONFIG_MPC8349) + #define RCWH_TSEC1M 0x0000c000 /* TSEC1M */ + #define RCWH_TSEC2M 0x00003000 /* TSEC2M */ +-#define RCWH_TPR 0x00000100 /* TPR */ +-#define RCWH_TLE 0x00000008 /* TLE */ +-#define RCWH_LALE 0x00000004 /* LALE */ ++#define RCWH_TPR 0x00000100 /* TPR */ ++#elif defined (CONFIG_MPC8360) ++#define RCWH_SDDRIOE 0x00000010 /* Secondary DDR IO Enable. */ ++#endif ++#define RCWH_TLE 0x00000008 /* TLE */ ++#define RCWH_LALE 0x00000004 /* LALE */ ++#if defined (CONFIG_MPC8349) + #define RCWH_RES ~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \ + | RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \ + | RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \ + | RCWH_TSEC1M | RCWH_TSEC2M | RCWH_TPR \ + | RCWH_TLE | RCWH_LALE) +- u8 res0[8]; +- u32 rsr; /* Reset status Register */ +-#define RSR_RSTSRC 0xE0000000 /* Reset source */ ++#elif defined (CONFIG_MPC8360) ++#define RCWH_RES ~(RCWH_PCIHOST|RCWH_PCIARB|RCWH_PCICKDRV \ ++ |RCWH_COREDIS|RCWH_BMS|RCWH_BOOTSEQ|RCWH_SWEN \ ++ |RCWH_SDDRIOE |RCWH_TLE) ++#endif ++ u8 res0[8]; ++ u32 rsr; /* Reset status Register */ ++#define RSR_RSTSRC 0xE0000000 /* Reset source */ + #define RSR_RSTSRC_SHIFT 29 +-#define RSR_BSF 0x00010000 /* Boot seq. fail */ +-#define RSR_BSF_SHIFT 16 +-#define RSR_SWSR 0x00002000 /* software soft reset */ +-#define RSR_SWSR_SHIFT 13 +-#define RSR_SWHR 0x00001000 /* software hard reset */ +-#define RSR_SWHR_SHIFT 12 +-#define RSR_JHRS 0x00000200 /* jtag hreset */ +-#define RSR_JHRS_SHIFT 9 +-#define RSR_JSRS 0x00000100 /* jtag sreset status */ +-#define RSR_JSRS_SHIFT 8 +-#define RSR_CSHR 0x00000010 /* checkstop reset status */ +-#define RSR_CSHR_SHIFT 4 +-#define RSR_SWRS 0x00000008 /* software watchdog reset status */ +-#define RSR_SWRS_SHIFT 3 +-#define RSR_BMRS 0x00000004 /* bus monitop reset status */ +-#define RSR_BMRS_SHIFT 2 +-#define RSR_SRS 0x00000002 /* soft reset status */ +-#define RSR_SRS_SHIFT 1 +-#define RSR_HRS 0x00000001 /* hard reset status */ +-#define RSR_HRS_SHIFT 0 ++#define RSR_BSF 0x00010000 /* Boot seq. fail */ ++#define RSR_BSF_SHIFT 16 ++#define RSR_SWSR 0x00002000 /* software soft reset */ ++#define RSR_SWSR_SHIFT 13 ++#define RSR_SWHR 0x00001000 /* software hard reset */ ++#define RSR_SWHR_SHIFT 12 ++#define RSR_JHRS 0x00000200 /* jtag hreset */ ++#define RSR_JHRS_SHIFT 9 ++#define RSR_JSRS 0x00000100 /* jtag sreset status */ ++#define RSR_JSRS_SHIFT 8 ++#define RSR_CSHR 0x00000010 /* checkstop reset status */ ++#define RSR_CSHR_SHIFT 4 ++#define RSR_SWRS 0x00000008 /* software watchdog reset status */ ++#define RSR_SWRS_SHIFT 3 ++#define RSR_BMRS 0x00000004 /* bus monitop reset status */ ++#define RSR_BMRS_SHIFT 2 ++#define RSR_SRS 0x00000002 /* soft reset status */ ++#define RSR_SRS_SHIFT 1 ++#define RSR_HRS 0x00000001 /* hard reset status */ ++#define RSR_HRS_SHIFT 0 + #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS | RSR_BMRS | RSR_SRS | RSR_HRS) +- u32 rmr; /* Reset mode Register */ +-#define RMR_CSRE 0x00000001 /* checkstop reset enable */ +-#define RMR_CSRE_SHIFT 0 ++ u32 rmr; /* Reset mode Register */ ++#define RMR_CSRE 0x00000001 /* checkstop reset enable */ ++#define RMR_CSRE_SHIFT 0 + #define RMR_RES ~(RMR_CSRE) +- u32 rpr; /* Reset protection Register */ +- u32 rcr; /* Reset Control Register */ +-#define RCR_SWHR 0x00000002 /* software hard reset */ +-#define RCR_SWSR 0x00000001 /* software soft reset */ ++ u32 rpr; /* Reset protection Register */ ++ u32 rcr; /* Reset Control Register */ ++#define RCR_SWHR 0x00000002 /* software hard reset */ ++#define RCR_SWSR 0x00000001 /* software soft reset */ + #define RCR_RES ~(RCR_SWHR | RCR_SWSR) +- u32 rcer; /* Reset Control Enable Register */ +-#define RCER_CRE 0x00000001 /* software hard reset */ ++ u32 rcer; /* Reset Control Enable Register */ ++#define RCER_CRE 0x00000001 /* software hard reset */ + #define RCER_RES ~(RCER_CRE) +- u8 res1[0xDC]; +-} reset8349_t; ++ u8 res1[0xDC]; ++} reset83xx_t; + +-typedef struct clk8349 { +- u32 spmr; /* system PLL mode Register */ ++typedef struct clk83xx { ++ u32 spmr; /* system PLL mode Register */ + #define SPMR_LBIUCM 0x80000000 /* LBIUCM */ + #define SPMR_DDRCM 0x40000000 /* DDRCM */ ++#if defined (CONFIG_MPC8349) + #define SPMR_SVCOD 0x30000000 /* SVCOD */ +-#define SPMR_SPMF 0x0F000000 /* SPMF */ +-#define SPMR_CKID 0x00800000 /* CKID */ ++#endif ++#define SPMR_SPMF 0x0F000000 /* SPMF */ ++#define SPMR_CKID 0x00800000 /* CKID */ + #define SPMR_CKID_SHIFT 23 + #define SPMR_COREPLL 0x007F0000 /* COREPLL */ + #define SPMR_CEVCOD 0x000000C0 /* CEVCOD */ + #define SPMR_CEPDF 0x00000020 /* CEPDF */ + #define SPMR_CEPMF 0x0000001F /* CEPMF */ ++#if defined (CONFIG_MPC8349) + #define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \ + | SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \ + | SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF) +- u32 occr; /* output clock control Register */ ++#elif defined (CONFIG_MPC8360) ++#define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SPMF \ ++ | SPMR_CKID | SPMR_COREPLL | SPMR_CEVCOD \ ++ | SPMR_CEPDF | SPMR_CEPMF) ++#endif ++ u32 occr; /* output clock control Register */ + #define OCCR_PCICOE0 0x80000000 /* PCICOE0 */ + #define OCCR_PCICOE1 0x40000000 /* PCICOE1 */ + #define OCCR_PCICOE2 0x20000000 /* PCICOE2 */ ++#if defined (CONFIG_MPC8349) + #define OCCR_PCICOE3 0x10000000 /* PCICOE3 */ + #define OCCR_PCICOE4 0x08000000 /* PCICOE4 */ + #define OCCR_PCICOE5 0x04000000 /* PCICOE5 */ + #define OCCR_PCICOE6 0x02000000 /* PCICOE6 */ + #define OCCR_PCICOE7 0x01000000 /* PCICOE7 */ ++#endif + #define OCCR_PCICD0 0x00800000 /* PCICD0 */ + #define OCCR_PCICD1 0x00400000 /* PCICD1 */ + #define OCCR_PCICD2 0x00200000 /* PCICD2 */ ++#if defined (CONFIG_MPC8349) + #define OCCR_PCICD3 0x00100000 /* PCICD3 */ + #define OCCR_PCICD4 0x00080000 /* PCICD4 */ + #define OCCR_PCICD5 0x00040000 /* PCICD5 */ +@@ -522,72 +684,253 @@ typedef struct clk8349 { + | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICD3 \ + | OCCR_PCICD4 | OCCR_PCICD5 | OCCR_PCICD6 \ + | OCCR_PCICD7 | OCCR_PCI1CR | OCCR_PCI2CR ) +- u32 sccr; /* system clock control Register */ +-#define SCCR_TSEC1CM 0xc0000000 /* TSEC1CM */ ++#endif ++#if defined (CONFIG_MPC8360) ++#define OCCR_PCICR 0x00000002 /* PCI clock rate */ ++#define OCCR_RES ~(OCCR_PCICOE0|OCCR_PCICOE1|OCCR_PCICOE2 \ ++ |OCCR_PCICD0|OCCR_PCICD1|OCCR_PCICD2|OCCR_PCICR ) ++#endif ++ u32 sccr; /* system clock control Register */ ++#if defined (CONFIG_MPC8349) ++#define SCCR_TSEC1CM 0xc0000000 /* TSEC1CM */ + #define SCCR_TSEC1CM_SHIFT 30 +-#define SCCR_TSEC2CM 0x30000000 /* TSEC2CM */ ++#define SCCR_TSEC2CM 0x30000000 /* TSEC2CM */ + #define SCCR_TSEC2CM_SHIFT 28 +-#define SCCR_ENCCM 0x03000000 /* ENCCM */ ++#endif ++#define SCCR_ENCCM 0x03000000 /* ENCCM */ + #define SCCR_ENCCM_SHIFT 24 +-#define SCCR_USBMPHCM 0x00c00000 /* USBMPHCM */ ++#if defined (CONFIG_MPC8349) ++#define SCCR_USBMPHCM 0x00c00000 /* USBMPHCM */ + #define SCCR_USBMPHCM_SHIFT 22 +-#define SCCR_USBDRCM 0x00300000 /* USBDRCM */ ++#define SCCR_USBDRCM 0x00300000 /* USBDRCM */ + #define SCCR_USBDRCM_SHIFT 20 +-#define SCCR_PCICM 0x00010000 /* PCICM */ ++#endif ++#define SCCR_PCICM 0x00010000 /* PCICM */ ++#if defined (CONFIG_MPC8349) + #define SCCR_RES ~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \ + | SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM) +- u8 res0[0xF4]; +-} clk8349_t; ++#endif ++#if defined (CONFIG_MPC8360) ++#define SCCR_RES ~(SCCR_ENCCM | SCCR_PCICM) ++#endif ++ u8 res0[0xF4]; ++} clk83xx_t; + + /* + * Power Management Control Module + */ +-typedef struct pmc8349 { +- u32 pmccr; /* PMC Configuration Register */ +-#define PMCCR_SLPEN 0x00000001 /* System Low Power Enable */ +-#define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable */ +-#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN) +- u32 pmcer; /* PMC Event Register */ +-#define PMCER_PMCI 0x00000001 /* PMC Interrupt */ ++typedef struct pmc83xx { ++ u32 pmccr; /* PMC Configuration Register */ ++#define PMCCR_SLPEN 0x00000001 /* System Low Power Enable */ ++#define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable */ ++#if defined (CONFIG_MPC8360) ++#define PMCCR_SDLPEN 0x00000004 /* Secondary DDR SDRAM Low Power Enable */ ++#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN | PMCCR_SDLPEN) ++#elif defined (CONFIG_MPC8349) ++#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN) ++#endif ++ u32 pmcer; /* PMC Event Register */ ++#define PMCER_PMCI 0x00000001 /* PMC Interrupt */ + #define PMCER_RES ~(PMCER_PMCI) +- u32 pmcmr; /* PMC Mask Register */ +-#define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable */ ++ u32 pmcmr; /* PMC Mask Register */ ++#define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable */ + #define PMCMR_RES ~(PMCMR_PMCIE) + u8 res0[0xF4]; +-} pmc8349_t; +- ++} pmc83xx_t; + ++#if defined (CONFIG_MPC8349) + /* + * general purpose I/O module + */ +-typedef struct gpio8349 { +- u32 dir; /* direction register */ +- u32 odr; /* open drain register */ +- u32 dat; /* data register */ +- u32 ier; /* interrupt event register */ +- u32 imr; /* interrupt mask register */ +- u32 icr; /* external interrupt control register */ ++typedef struct gpio83xx { ++ u32 dir; /* direction register */ ++ u32 odr; /* open drain register */ ++ u32 dat; /* data register */ ++ u32 ier; /* interrupt event register */ ++ u32 imr; /* interrupt mask register */ ++ u32 icr; /* external interrupt control register */ + u8 res0[0xE8]; +-} gpio8349_t; ++} gpio83xx_t; ++#endif ++ ++#if defined (CONFIG_MPC8360) ++/* ++ * QE Ports Interrupts Registers ++ */ ++typedef struct qepi83xx { ++ u8 res0[0xC]; ++ u32 qepier; /* QE Ports Interrupt Event Register */ ++#define QEPIER_PA15 0x80000000 ++#define QEPIER_PA16 0x40000000 ++#define QEPIER_PA29 0x20000000 ++#define QEPIER_PA30 0x10000000 ++#define QEPIER_PB3 0x08000000 ++#define QEPIER_PB5 0x04000000 ++#define QEPIER_PB12 0x02000000 ++#define QEPIER_PB13 0x01000000 ++#define QEPIER_PB26 0x00800000 ++#define QEPIER_PB27 0x00400000 ++#define QEPIER_PC27 0x00200000 ++#define QEPIER_PC28 0x00100000 ++#define QEPIER_PC29 0x00080000 ++#define QEPIER_PD12 0x00040000 ++#define QEPIER_PD13 0x00020000 ++#define QEPIER_PD16 0x00010000 ++#define QEPIER_PD17 0x00008000 ++#define QEPIER_PD26 0x00004000 ++#define QEPIER_PD27 0x00002000 ++#define QEPIER_PE12 0x00001000 ++#define QEPIER_PE13 0x00000800 ++#define QEPIER_PE24 0x00000400 ++#define QEPIER_PE25 0x00000200 ++#define QEPIER_PE26 0x00000100 ++#define QEPIER_PE27 0x00000080 ++#define QEPIER_PE31 0x00000040 ++#define QEPIER_PF20 0x00000020 ++#define QEPIER_PG31 0x00000010 ++#define QEPIER_RES ~(QEPIER_PA15|QEPIER_PA16|QEPIER_PA29|QEPIER_PA30|QEPIER_PB3 \ ++ |QEPIER_PB5|QEPIER_PB12|QEPIER_PB13|QEPIER_PB26|QEPIER_PB27 \ ++ |QEPIER_PC27|QEPIER_PC28|QEPIER_PC29|QEPIER_PD12|QEPIER_PD13 \ ++ |QEPIER_PD16|QEPIER_PD17|QEPIER_PD26|QEPIER_PD27|QEPIER_PE12 \ ++ |QEPIER_PE13|QEPIER_PE24|QEPIER_PE25|QEPIER_PE26|QEPIER_PE27 \ ++ |QEPIER_PE31|QEPIER_PF20|QEPIER_PG31) ++ u32 qepimr; /* QE Ports Interrupt Mask Register */ ++#define QEPIMR_PA15 0x80000000 ++#define QEPIMR_PA16 0x40000000 ++#define QEPIMR_PA29 0x20000000 ++#define QEPIMR_PA30 0x10000000 ++#define QEPIMR_PB3 0x08000000 ++#define QEPIMR_PB5 0x04000000 ++#define QEPIMR_PB12 0x02000000 ++#define QEPIMR_PB13 0x01000000 ++#define QEPIMR_PB26 0x00800000 ++#define QEPIMR_PB27 0x00400000 ++#define QEPIMR_PC27 0x00200000 ++#define QEPIMR_PC28 0x00100000 ++#define QEPIMR_PC29 0x00080000 ++#define QEPIMR_PD12 0x00040000 ++#define QEPIMR_PD13 0x00020000 ++#define QEPIMR_PD16 0x00010000 ++#define QEPIMR_PD17 0x00008000 ++#define QEPIMR_PD26 0x00004000 ++#define QEPIMR_PD27 0x00002000 ++#define QEPIMR_PE12 0x00001000 ++#define QEPIMR_PE13 0x00000800 ++#define QEPIMR_PE24 0x00000400 ++#define QEPIMR_PE25 0x00000200 ++#define QEPIMR_PE26 0x00000100 ++#define QEPIMR_PE27 0x00000080 ++#define QEPIMR_PE31 0x00000040 ++#define QEPIMR_PF20 0x00000020 ++#define QEPIMR_PG31 0x00000010 ++#define QEPIMR_RES ~(QEPIMR_PA15|QEPIMR_PA16|QEPIMR_PA29|QEPIMR_PA30|QEPIMR_PB3 \ ++ |QEPIMR_PB5|QEPIMR_PB12|QEPIMR_PB13|QEPIMR_PB26|QEPIMR_PB27 \ ++ |QEPIMR_PC27|QEPIMR_PC28|QEPIMR_PC29|QEPIMR_PD12|QEPIMR_PD13 \ ++ |QEPIMR_PD16|QEPIMR_PD17|QEPIMR_PD26|QEPIMR_PD27|QEPIMR_PE12 \ ++ |QEPIMR_PE13|QEPIMR_PE24|QEPIMR_PE25|QEPIMR_PE26|QEPIMR_PE27 \ ++ |QEPIMR_PE31|QEPIMR_PF20|QEPIMR_PG31) ++ u32 qepicr; /* QE Ports Interrupt Control Register */ ++#define QEPICR_PA15 0x80000000 ++#define QEPICR_PA16 0x40000000 ++#define QEPICR_PA29 0x20000000 ++#define QEPICR_PA30 0x10000000 ++#define QEPICR_PB3 0x08000000 ++#define QEPICR_PB5 0x04000000 ++#define QEPICR_PB12 0x02000000 ++#define QEPICR_PB13 0x01000000 ++#define QEPICR_PB26 0x00800000 ++#define QEPICR_PB27 0x00400000 ++#define QEPICR_PC27 0x00200000 ++#define QEPICR_PC28 0x00100000 ++#define QEPICR_PC29 0x00080000 ++#define QEPICR_PD12 0x00040000 ++#define QEPICR_PD13 0x00020000 ++#define QEPICR_PD16 0x00010000 ++#define QEPICR_PD17 0x00008000 ++#define QEPICR_PD26 0x00004000 ++#define QEPICR_PD27 0x00002000 ++#define QEPICR_PE12 0x00001000 ++#define QEPICR_PE13 0x00000800 ++#define QEPICR_PE24 0x00000400 ++#define QEPICR_PE25 0x00000200 ++#define QEPICR_PE26 0x00000100 ++#define QEPICR_PE27 0x00000080 ++#define QEPICR_PE31 0x00000040 ++#define QEPICR_PF20 0x00000020 ++#define QEPICR_PG31 0x00000010 ++#define QEPICR_RES ~(QEPICR_PA15|QEPICR_PA16|QEPICR_PA29|QEPICR_PA30|QEPICR_PB3 \ ++ |QEPICR_PB5|QEPICR_PB12|QEPICR_PB13|QEPICR_PB26|QEPICR_PB27 \ ++ |QEPICR_PC27|QEPICR_PC28|QEPICR_PC29|QEPICR_PD12|QEPICR_PD13 \ ++ |QEPICR_PD16|QEPICR_PD17|QEPICR_PD26|QEPICR_PD27|QEPICR_PE12 \ ++ |QEPICR_PE13|QEPICR_PE24|QEPICR_PE25|QEPICR_PE26|QEPICR_PE27 \ ++ |QEPICR_PE31|QEPICR_PF20|QEPICR_PG31) ++ u8 res1[0xE8]; ++} qepi83xx_t; ++ ++/* ++ * general purpose I/O module ++ */ ++typedef struct gpio_n { ++ u32 podr; /* Open Drain Register */ ++ u32 pdat; /* Data Register */ ++ u32 dir1; /* direction register 1 */ ++ u32 dir2; /* direction register 2 */ ++ u32 ppar1; /* Pin Assignment Register 1 */ ++ u32 ppar2; /* Pin Assignment Register 2 */ ++} gpio_n_t; ++ ++typedef struct gpio83xx { ++ gpio_n_t ioport[0x7]; ++ u8 res0[0x358]; ++} gpio83xx_t; ++ ++/* ++ * QE Secondary Bus Access Windows ++ */ ++ ++typedef struct qesba83xx { ++ u32 lbmcsar; /* Local bus memory controller start address */ ++#define LBMCSAR_SA 0x000FFFFF /* 20 most-significant bits of the start address */ ++#define LBMCSAR_RES ~(LBMCSAR_SA) ++ u32 sdmcsar; /* Secondary DDR memory controller start address */ ++#define SDMCSAR_SA 0x000FFFFF /* 20 most-significant bits of the start address */ ++#define SDMCSAR_RES ~(SDMCSAR_SA) ++ u8 res0[0x38]; ++ u32 lbmcear; /* Local bus memory controller end address */ ++#define LBMCEAR_EA 0x000FFFFF /* 20 most-significant bits of the end address */ ++#define LBMCEAR_RES ~(LBMCEAR_EA) ++ u32 sdmcear; /* Secondary DDR memory controller end address */ ++#define SDMCEAR_EA 0x000FFFFF /* 20 most-significant bits of the end address */ ++#define SDMCEAR_RES ~(SDMCEAR_EA) ++ u8 res1[0x38]; ++ u32 lbmcar; /* Local bus memory controller attributes */ ++#define LBMCAR_WEN 0x00000001 /* Forward transactions to the QE local bus */ ++#define LBMCAR_RES ~(LBMCAR_WEN) ++ u32 sdmcar; /* Secondary DDR memory controller attributes */ ++#define SDMCAR_WEN 0x00000001 /* Forward transactions to the second DDR bus */ ++#define SDMCAR_RES ~(SDMCAR_WEN) ++ u8 res2[0x778]; ++} qesba83xx_t; ++#endif + + /* + * DDR Memory Controller Memory Map + */ +-typedef struct ddr_cs_bnds{ ++typedef struct ddr_cs_bnds { + u32 csbnds; + #define CSBNDS_SA 0x00FF0000 +-#define CSBNDS_SA_SHIFT 8 ++#define CSBNDS_SA_SHIFT 8 + #define CSBNDS_EA 0x000000FF +-#define CSBNDS_EA_SHIFT 24 +- u8 res0[4]; ++#define CSBNDS_EA_SHIFT 24 ++ u8 res0[4]; + } ddr_cs_bnds_t; + +-typedef struct ddr8349{ +- ddr_cs_bnds_t csbnds[4]; /**< Chip Select x Memory Bounds */ ++typedef struct ddr83xx { ++ ddr_cs_bnds_t csbnds[4]; /**< Chip Select x Memory Bounds */ + u8 res0[0x60]; +- u32 cs_config[4]; /**< Chip Select x Configuration */ +-#define CSCONFIG_EN 0x80000000 +-#define CSCONFIG_AP 0x00800000 ++ u32 cs_config[4]; /**< Chip Select x Configuration */ ++#define CSCONFIG_EN 0x80000000 ++#define CSCONFIG_AP 0x00800000 + #define CSCONFIG_ROW_BIT 0x00000700 + #define CSCONFIG_ROW_BIT_12 0x00000000 + #define CSCONFIG_ROW_BIT_13 0x00000100 +@@ -598,7 +941,7 @@ typedef struct ddr8349{ + #define CSCONFIG_COL_BIT_10 0x00000002 + #define CSCONFIG_COL_BIT_11 0x00000003 + u8 res1[0x78]; +- u32 timing_cfg_1; /**< SDRAM Timing Configuration 1 */ ++ u32 timing_cfg_1; /**< SDRAM Timing Configuration 1 */ + #define TIMING_CFG1_PRETOACT 0x70000000 + #define TIMING_CFG1_PRETOACT_SHIFT 28 + #define TIMING_CFG1_ACTTOPRE 0x0F000000 +@@ -610,70 +953,70 @@ typedef struct ddr8349{ + #define TIMING_CFG1_REFREC 0x0000F000 + #define TIMING_CFG1_REFREC_SHIFT 12 + #define TIMING_CFG1_WRREC 0x00000700 +-#define TIMING_CFG1_WRREC_SHIFT 8 ++#define TIMING_CFG1_WRREC_SHIFT 8 + #define TIMING_CFG1_ACTTOACT 0x00000070 + #define TIMING_CFG1_ACTTOACT_SHIFT 4 + #define TIMING_CFG1_WRTORD 0x00000007 + #define TIMING_CFG1_WRTORD_SHIFT 0 +-#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ +-#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ ++#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ ++#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ + +- u32 timing_cfg_2; /**< SDRAM Timing Configuration 2 */ +-#define TIMING_CFG2_CPO 0x0F000000 +-#define TIMING_CFG2_CPO_SHIFT 24 +-#define TIMING_CFG2_ACSM 0x00080000 ++ u32 timing_cfg_2; /**< SDRAM Timing Configuration 2 */ ++#define TIMING_CFG2_CPO 0x0F000000 ++#define TIMING_CFG2_CPO_SHIFT 24 ++#define TIMING_CFG2_ACSM 0x00080000 + #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 +-#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 +-#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ ++#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 ++#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ + +- u32 sdram_cfg; /**< SDRAM Control Configuration */ ++ u32 sdram_cfg; /**< SDRAM Control Configuration */ + #define SDRAM_CFG_MEM_EN 0x80000000 +-#define SDRAM_CFG_SREN 0x40000000 ++#define SDRAM_CFG_SREN 0x40000000 + #define SDRAM_CFG_ECC_EN 0x20000000 +-#define SDRAM_CFG_RD_EN 0x10000000 ++#define SDRAM_CFG_RD_EN 0x10000000 + #define SDRAM_CFG_SDRAM_TYPE 0x03000000 + #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 + #define SDRAM_CFG_DYN_PWR 0x00200000 +-#define SDRAM_CFG_32_BE 0x00080000 +-#define SDRAM_CFG_8_BE 0x00040000 +-#define SDRAM_CFG_NCAP 0x00020000 +-#define SDRAM_CFG_2T_EN 0x00008000 ++#define SDRAM_CFG_32_BE 0x00080000 ++#define SDRAM_CFG_8_BE 0x00040000 ++#define SDRAM_CFG_NCAP 0x00020000 ++#define SDRAM_CFG_2T_EN 0x00008000 + #define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000 + + u8 res2[4]; +- u32 sdram_mode; /**< SDRAM Mode Configuration */ ++ u32 sdram_mode; /**< SDRAM Mode Configuration */ + #define SDRAM_MODE_ESD 0xFFFF0000 + #define SDRAM_MODE_ESD_SHIFT 16 + #define SDRAM_MODE_SD 0x0000FFFF +-#define SDRAM_MODE_SD_SHIFT 0 +-#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ +-#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ +-#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ +-#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ +-#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ +-#define DDR_MODE_WEAK 0x0002 /* weak drivers */ +-#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ +-#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ +-#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ +-#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ +-#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ +-#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ +-#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ +-#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ +-#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ +-#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ +-#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125 µs */ +-#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ +-#define DDR_MODE_MODEREG 0x0000 /* select mode register */ ++#define SDRAM_MODE_SD_SHIFT 0 ++#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ ++#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ ++#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ ++#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ ++#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ ++#define DDR_MODE_WEAK 0x0002 /* weak drivers */ ++#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ ++#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ ++#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ ++#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ ++#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ ++#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ ++#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ ++#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ ++#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ ++#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ ++#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125 µs */ ++#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ ++#define DDR_MODE_MODEREG 0x0000 /* select mode register */ + + u8 res3[8]; +- u32 sdram_interval; /**< SDRAM Interval Configuration */ ++ u32 sdram_interval; /**< SDRAM Interval Configuration */ + #define SDRAM_INTERVAL_REFINT 0x3FFF0000 + #define SDRAM_INTERVAL_REFINT_SHIFT 16 + #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF +-#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 +- u8 res9[8]; +- u32 sdram_clk_cntl; ++#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 ++ u8 res9[8]; ++ u32 sdram_clk_cntl; + #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 + #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 + #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 +@@ -683,37 +1026,37 @@ typedef struct ddr8349{ + u8 res4[0xCCC]; + u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */ + u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */ +- u32 ecc_err_inject; /**< Memory Data Path Error Injection Mask ECC */ ++ u32 ecc_err_inject; /**< Memory Data Path Error Injection Mask ECC */ + #define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ + #define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ + #define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ + #define ECC_ERR_INJECT_EEIM_SHIFT 0 + u8 res5[0x14]; +- u32 capture_data_hi; /**< Memory Data Path Read Capture High */ +- u32 capture_data_lo; /**< Memory Data Path Read Capture Low */ +- u32 capture_ecc; /**< Memory Data Path Read Capture ECC */ ++ u32 capture_data_hi; /**< Memory Data Path Read Capture High */ ++ u32 capture_data_lo; /**< Memory Data Path Read Capture Low */ ++ u32 capture_ecc; /**< Memory Data Path Read Capture ECC */ + #define CAPTURE_ECC_ECE (0xff000000>>24) + #define CAPTURE_ECC_ECE_SHIFT 0 + u8 res6[0x14]; +- u32 err_detect; /**< Memory Error Detect */ +-#define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ ++ u32 err_detect; /**< Memory Error Detect */ ++#define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ + #define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ + #define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ + #define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ +- u32 err_disable; /**< Memory Error Disable */ ++ u32 err_disable; /**< Memory Error Disable */ + #define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ + #define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ + #define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ + #define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED|ECC_ERROR_DISABLE_SBED|ECC_ERROR_DISABLE_MBED) +- u32 err_int_en; /**< Memory Error Interrupt Enable */ ++ u32 err_int_en; /**< Memory Error Interrupt Enable */ + #define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ + #define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ + #define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ + #define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE|ECC_ERR_INT_EN_SBEE|ECC_ERR_INT_EN_MSEE) + u32 capture_attributes; /**< Memory Error Attributes Capture */ +-#define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ ++#define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ + #define ECC_CAPT_ATTR_BNUM_SHIFT 28 +-#define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ ++#define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ + #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 + #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 + #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 +@@ -738,209 +1081,207 @@ typedef struct ddr8349{ + #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 + #define ECC_CAPT_ATTR_TTYP_SHIFT 12 + #define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ +- u32 capture_address; /**< Memory Error Address Capture */ ++ u32 capture_address; /**< Memory Error Address Capture */ + u32 capture_ext_address;/**< Memory Error Extended Address Capture */ +- u32 err_sbe; /**< Memory Single-Bit ECC Error Management */ +-#define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255*/ ++ u32 err_sbe; /**< Memory Single-Bit ECC Error Management */ ++#define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ + #define ECC_ERROR_MAN_SBET_SHIFT 16 +-#define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255*/ ++#define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ + #define ECC_ERROR_MAN_SBEC_SHIFT 0 + u8 res7[0xA4]; + u32 debug_reg; + u8 res8[0xFC]; +-} ddr8349_t; ++} ddr83xx_t; + + /* + * I2C1 Controller + */ + +- + /* + * DUART + */ +-typedef struct duart8349{ ++typedef struct duart83xx { + u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */ +- u8 uier_udmb; /**< combined register for UIER and UDMB */ ++ u8 uier_udmb; /**< combined register for UIER and UDMB */ + u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */ +- u8 ulcr; /**< line control register */ +- u8 umcr; /**< MODEM control register */ +- u8 ulsr; /**< line status register */ +- u8 umsr; /**< MODEM status register */ +- u8 uscr; /**< scratch register */ ++ u8 ulcr; /**< line control register */ ++ u8 umcr; /**< MODEM control register */ ++ u8 ulsr; /**< line status register */ ++ u8 umsr; /**< MODEM status register */ ++ u8 uscr; /**< scratch register */ + u8 res0[8]; +- u8 udsr; /**< DMA status register */ ++ u8 udsr; /**< DMA status register */ + u8 res1[3]; + u8 res2[0xEC]; +-} duart8349_t; ++} duart83xx_t; + + /* + * Local Bus Controller Registers + */ +-typedef struct lbus_bank{ +- u32 br; /**< Base Register */ +- u32 or; /**< Base Register */ ++typedef struct lbus_bank { ++ u32 br; /**< Base Register */ ++ u32 or; /**< Base Register */ + } lbus_bank_t; + +-typedef struct lbus8349 { ++typedef struct lbus83xx { + lbus_bank_t bank[8]; + u8 res0[0x28]; +- u32 mar; /**< UPM Address Register */ ++ u32 mar; /**< UPM Address Register */ + u8 res1[0x4]; +- u32 mamr; /**< UPMA Mode Register */ +- u32 mbmr; /**< UPMB Mode Register */ +- u32 mcmr; /**< UPMC Mode Register */ ++ u32 mamr; /**< UPMA Mode Register */ ++ u32 mbmr; /**< UPMB Mode Register */ ++ u32 mcmr; /**< UPMC Mode Register */ + u8 res2[0x8]; +- u32 mrtpr; /**< Memory Refresh Timer Prescaler Register */ +- u32 mdr; /**< UPM Data Register */ ++ u32 mrtpr; /**< Memory Refresh Timer Prescaler Register */ ++ u32 mdr; /**< UPM Data Register */ + u8 res3[0x8]; +- u32 lsdmr; /**< SDRAM Mode Register */ ++ u32 lsdmr; /**< SDRAM Mode Register */ + u8 res4[0x8]; +- u32 lurt; /**< UPM Refresh Timer */ +- u32 lsrt; /**< SDRAM Refresh Timer */ ++ u32 lurt; /**< UPM Refresh Timer */ ++ u32 lsrt; /**< SDRAM Refresh Timer */ + u8 res5[0x8]; +- u32 ltesr; /**< Transfer Error Status Register */ +- u32 ltedr; /**< Transfer Error Disable Register */ +- u32 lteir; /**< Transfer Error Interrupt Register */ +- u32 lteatr; /**< Transfer Error Attributes Register */ +- u32 ltear; /**< Transfer Error Address Register */ ++ u32 ltesr; /**< Transfer Error Status Register */ ++ u32 ltedr; /**< Transfer Error Disable Register */ ++ u32 lteir; /**< Transfer Error Interrupt Register */ ++ u32 lteatr; /**< Transfer Error Attributes Register */ ++ u32 ltear; /**< Transfer Error Address Register */ + u8 res6[0xC]; +- u32 lbcr; /**< Configuration Register */ ++ u32 lbcr; /**< Configuration Register */ + #define LBCR_LDIS 0x80000000 +-#define LBCR_LDIS_SHIFT 31 ++#define LBCR_LDIS_SHIFT 31 + #define LBCR_BCTLC 0x00C00000 + #define LBCR_BCTLC_SHIFT 22 + #define LBCR_LPBSE 0x00020000 + #define LBCR_LPBSE_SHIFT 17 + #define LBCR_EPAR 0x00010000 +-#define LBCR_EPAR_SHIFT 16 ++#define LBCR_EPAR_SHIFT 16 + #define LBCR_BMT 0x0000FF00 +-#define LBCR_BMT_SHIFT 8 +- u32 lcrr; /**< Clock Ratio Register */ ++#define LBCR_BMT_SHIFT 8 ++ u32 lcrr; /**< Clock Ratio Register */ + #define LCRR_DBYP 0x80000000 +-#define LCRR_DBYP_SHIFT 31 ++#define LCRR_DBYP_SHIFT 31 + #define LCRR_BUFCMDC 0x30000000 + #define LCRR_BUFCMDC_SHIFT 28 + #define LCRR_ECL 0x03000000 +-#define LCRR_ECL_SHIFT 24 ++#define LCRR_ECL_SHIFT 24 + #define LCRR_EADC 0x00030000 +-#define LCRR_EADC_SHIFT 16 ++#define LCRR_EADC_SHIFT 16 + #define LCRR_CLKDIV 0x0000000F + #define LCRR_CLKDIV_SHIFT 0 + +- + u8 res7[0x28]; + u8 res8[0xF00]; +-} lbus8349_t; ++} lbus83xx_t; + ++#if defined (CONFIG_MPC8349) + /* + * Serial Peripheral Interface + */ +-typedef struct spi8349 +-{ ++typedef struct spi83xx { + u32 mode; /**< mode register */ + u32 event; /**< event register */ + u32 mask; /**< mask register */ + u32 com; /**< command register */ + u8 res0[0x10]; +- u32 tx; /**< transmit register */ +- u32 rx; /**< receive register */ ++ u32 tx; /**< transmit register */ ++ u32 rx; /**< receive register */ + u8 res1[0xD8]; +-} spi8349_t; +- ++} spi83xx_t; ++#endif + + /* + * DMA/Messaging Unit + */ +-typedef struct dma8349 { +- u32 res0[0xC]; /* 0x0-0x29 reseverd */ +- u32 omisr; /* 0x30 Outbound message interrupt status register */ +- u32 omimr; /* 0x34 Outbound message interrupt mask register */ +- u32 res1[0x6]; /* 0x38-0x49 reserved */ +- +- u32 imr0; /* 0x50 Inbound message register 0 */ +- u32 imr1; /* 0x54 Inbound message register 1 */ +- u32 omr0; /* 0x58 Outbound message register 0 */ +- u32 omr1; /* 0x5C Outbound message register 1 */ +- +- u32 odr; /* 0x60 Outbound doorbell register */ +- u32 res2; /* 0x64-0x67 reserved */ +- u32 idr; /* 0x68 Inbound doorbell register */ +- u32 res3[0x5]; /* 0x6C-0x79 reserved */ +- +- u32 imisr; /* 0x80 Inbound message interrupt status register */ +- u32 imimr; /* 0x84 Inbound message interrupt mask register */ +- u32 res4[0x1E]; /* 0x88-0x99 reserved */ +- +- u32 dmamr0; /* 0x100 DMA 0 mode register */ +- u32 dmasr0; /* 0x104 DMA 0 status register */ +- u32 dmacdar0; /* 0x108 DMA 0 current descriptor address register */ +- u32 res5; /* 0x10C reserved */ +- u32 dmasar0; /* 0x110 DMA 0 source address register */ +- u32 res6; /* 0x114 reserved */ +- u32 dmadar0; /* 0x118 DMA 0 destination address register */ +- u32 res7; /* 0x11C reserved */ +- u32 dmabcr0; /* 0x120 DMA 0 byte count register */ +- u32 dmandar0; /* 0x124 DMA 0 next descriptor address register */ +- u32 res8[0x16]; /* 0x128-0x179 reserved */ +- +- u32 dmamr1; /* 0x180 DMA 1 mode register */ +- u32 dmasr1; /* 0x184 DMA 1 status register */ +- u32 dmacdar1; /* 0x188 DMA 1 current descriptor address register */ +- u32 res9; /* 0x18C reserved */ +- u32 dmasar1; /* 0x190 DMA 1 source address register */ +- u32 res10; /* 0x194 reserved */ +- u32 dmadar1; /* 0x198 DMA 1 destination address register */ +- u32 res11; /* 0x19C reserved */ +- u32 dmabcr1; /* 0x1A0 DMA 1 byte count register */ +- u32 dmandar1; /* 0x1A4 DMA 1 next descriptor address register */ +- u32 res12[0x16];/* 0x1A8-0x199 reserved */ +- +- u32 dmamr2; /* 0x200 DMA 2 mode register */ +- u32 dmasr2; /* 0x204 DMA 2 status register */ +- u32 dmacdar2; /* 0x208 DMA 2 current descriptor address register */ +- u32 res13; /* 0x20C reserved */ +- u32 dmasar2; /* 0x210 DMA 2 source address register */ +- u32 res14; /* 0x214 reserved */ +- u32 dmadar2; /* 0x218 DMA 2 destination address register */ +- u32 res15; /* 0x21C reserved */ +- u32 dmabcr2; /* 0x220 DMA 2 byte count register */ +- u32 dmandar2; /* 0x224 DMA 2 next descriptor address register */ +- u32 res16[0x16];/* 0x228-0x279 reserved */ +- +- u32 dmamr3; /* 0x280 DMA 3 mode register */ +- u32 dmasr3; /* 0x284 DMA 3 status register */ +- u32 dmacdar3; /* 0x288 DMA 3 current descriptor address register */ +- u32 res17; /* 0x28C reserved */ +- u32 dmasar3; /* 0x290 DMA 3 source address register */ +- u32 res18; /* 0x294 reserved */ +- u32 dmadar3; /* 0x298 DMA 3 destination address register */ +- u32 res19; /* 0x29C reserved */ +- u32 dmabcr3; /* 0x2A0 DMA 3 byte count register */ +- u32 dmandar3; /* 0x2A4 DMA 3 next descriptor address register */ +- +- u32 dmagsr; /* 0x2A8 DMA general status register */ +- u32 res20[0x15];/* 0x2AC-0x2FF reserved */ +-} dma8349_t; ++typedef struct dma83xx { ++ u32 res0[0xC]; /* 0x0-0x29 reseverd */ ++ u32 omisr; /* 0x30 Outbound message interrupt status register */ ++ u32 omimr; /* 0x34 Outbound message interrupt mask register */ ++ u32 res1[0x6]; /* 0x38-0x49 reserved */ ++ ++ u32 imr0; /* 0x50 Inbound message register 0 */ ++ u32 imr1; /* 0x54 Inbound message register 1 */ ++ u32 omr0; /* 0x58 Outbound message register 0 */ ++ u32 omr1; /* 0x5C Outbound message register 1 */ ++ ++ u32 odr; /* 0x60 Outbound doorbell register */ ++ u32 res2; /* 0x64-0x67 reserved */ ++ u32 idr; /* 0x68 Inbound doorbell register */ ++ u32 res3[0x5]; /* 0x6C-0x79 reserved */ ++ ++ u32 imisr; /* 0x80 Inbound message interrupt status register */ ++ u32 imimr; /* 0x84 Inbound message interrupt mask register */ ++ u32 res4[0x1E]; /* 0x88-0x99 reserved */ ++ ++ u32 dmamr0; /* 0x100 DMA 0 mode register */ ++ u32 dmasr0; /* 0x104 DMA 0 status register */ ++ u32 dmacdar0; /* 0x108 DMA 0 current descriptor address register */ ++ u32 res5; /* 0x10C reserved */ ++ u32 dmasar0; /* 0x110 DMA 0 source address register */ ++ u32 res6; /* 0x114 reserved */ ++ u32 dmadar0; /* 0x118 DMA 0 destination address register */ ++ u32 res7; /* 0x11C reserved */ ++ u32 dmabcr0; /* 0x120 DMA 0 byte count register */ ++ u32 dmandar0; /* 0x124 DMA 0 next descriptor address register */ ++ u32 res8[0x16]; /* 0x128-0x179 reserved */ ++ ++ u32 dmamr1; /* 0x180 DMA 1 mode register */ ++ u32 dmasr1; /* 0x184 DMA 1 status register */ ++ u32 dmacdar1; /* 0x188 DMA 1 current descriptor address register */ ++ u32 res9; /* 0x18C reserved */ ++ u32 dmasar1; /* 0x190 DMA 1 source address register */ ++ u32 res10; /* 0x194 reserved */ ++ u32 dmadar1; /* 0x198 DMA 1 destination address register */ ++ u32 res11; /* 0x19C reserved */ ++ u32 dmabcr1; /* 0x1A0 DMA 1 byte count register */ ++ u32 dmandar1; /* 0x1A4 DMA 1 next descriptor address register */ ++ u32 res12[0x16]; /* 0x1A8-0x199 reserved */ ++ ++ u32 dmamr2; /* 0x200 DMA 2 mode register */ ++ u32 dmasr2; /* 0x204 DMA 2 status register */ ++ u32 dmacdar2; /* 0x208 DMA 2 current descriptor address register */ ++ u32 res13; /* 0x20C reserved */ ++ u32 dmasar2; /* 0x210 DMA 2 source address register */ ++ u32 res14; /* 0x214 reserved */ ++ u32 dmadar2; /* 0x218 DMA 2 destination address register */ ++ u32 res15; /* 0x21C reserved */ ++ u32 dmabcr2; /* 0x220 DMA 2 byte count register */ ++ u32 dmandar2; /* 0x224 DMA 2 next descriptor address register */ ++ u32 res16[0x16]; /* 0x228-0x279 reserved */ ++ ++ u32 dmamr3; /* 0x280 DMA 3 mode register */ ++ u32 dmasr3; /* 0x284 DMA 3 status register */ ++ u32 dmacdar3; /* 0x288 DMA 3 current descriptor address register */ ++ u32 res17; /* 0x28C reserved */ ++ u32 dmasar3; /* 0x290 DMA 3 source address register */ ++ u32 res18; /* 0x294 reserved */ ++ u32 dmadar3; /* 0x298 DMA 3 destination address register */ ++ u32 res19; /* 0x29C reserved */ ++ u32 dmabcr3; /* 0x2A0 DMA 3 byte count register */ ++ u32 dmandar3; /* 0x2A4 DMA 3 next descriptor address register */ ++ ++ u32 dmagsr; /* 0x2A8 DMA general status register */ ++ u32 res20[0x15]; /* 0x2AC-0x2FF reserved */ ++} dma83xx_t; + + /* DMAMRn bits */ +-#define DMA_CHANNEL_START (0x00000001) /* Bit - DMAMRn CS */ +-#define DMA_CHANNEL_TRANSFER_MODE_DIRECT (0x00000004) /* Bit - DMAMRn CTM */ +-#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN (0x00001000) /* Bit - DMAMRn SAHE */ +-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B (0x00000000) /* 2Bit- DMAMRn SAHTS 1byte */ +-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B (0x00004000) /* 2Bit- DMAMRn SAHTS 2bytes */ +-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B (0x00008000) /* 2Bit- DMAMRn SAHTS 4bytes */ +-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B (0x0000c000) /* 2Bit- DMAMRn SAHTS 8bytes */ +-#define DMA_CHANNEL_SNOOP (0x00010000) /* Bit - DMAMRn DMSEN */ ++#define DMA_CHANNEL_START (0x00000001) /* Bit - DMAMRn CS */ ++#define DMA_CHANNEL_TRANSFER_MODE_DIRECT (0x00000004) /* Bit - DMAMRn CTM */ ++#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN (0x00001000) /* Bit - DMAMRn SAHE */ ++#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B (0x00000000) /* 2Bit- DMAMRn SAHTS 1byte */ ++#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B (0x00004000) /* 2Bit- DMAMRn SAHTS 2bytes */ ++#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B (0x00008000) /* 2Bit- DMAMRn SAHTS 4bytes */ ++#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B (0x0000c000) /* 2Bit- DMAMRn SAHTS 8bytes */ ++#define DMA_CHANNEL_SNOOP (0x00010000) /* Bit - DMAMRn DMSEN */ + + /* DMASRn bits */ +-#define DMA_CHANNEL_BUSY (0x00000004) /* Bit - DMASRn CB */ +-#define DMA_CHANNEL_TRANSFER_ERROR (0x00000080) /* Bit - DMASRn TE */ ++#define DMA_CHANNEL_BUSY (0x00000004) /* Bit - DMASRn CB */ ++#define DMA_CHANNEL_TRANSFER_ERROR (0x00000080) /* Bit - DMASRn TE */ + + /* + * PCI Software Configuration Registers + */ +-typedef struct pciconf8349 { +- u32 config_address; ++typedef struct pciconf83xx { ++ u32 config_address; + #define PCI_CONFIG_ADDRESS_EN 0x80000000 + #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 + #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 +@@ -952,235 +1293,788 @@ typedef struct pciconf8349 { + #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc + u32 config_data; + u32 int_ack; +- u8 res[116]; +-} pciconf8349_t; ++ u8 res[116]; ++} pciconf83xx_t; + + /* + * PCI Outbound Translation Register + */ + typedef struct pci_outbound_window { +- u32 potar; +- u8 res0[4]; +- u32 pobar; +- u8 res1[4]; +- u32 pocmr; +- u8 res2[4]; +-} pot8349_t; ++ u32 potar; ++ u8 res0[4]; ++ u32 pobar; ++ u8 res1[4]; ++ u32 pocmr; ++ u8 res2[4]; ++} pot83xx_t; ++ + /* + * Sequencer + */ +-typedef struct ios8349 { +- pot8349_t pot[6]; ++typedef struct ios83xx { ++ pot83xx_t pot[6]; + #define POTAR_TA_MASK 0x000fffff +-#define POBAR_BA_MASK 0x000fffff +-#define POCMR_EN 0x80000000 +-#define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */ +-#define POCMR_SE 0x20000000 /* streaming enable */ +-#define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2*/ +-#define POCMR_CM_MASK 0x000fffff +-#define POCMR_CM_4G 0x00000000 +-#define POCMR_CM_2G 0x00080000 +-#define POCMR_CM_1G 0x000C0000 +-#define POCMR_CM_512M 0x000E0000 +-#define POCMR_CM_256M 0x000F0000 +-#define POCMR_CM_128M 0x000F8000 +-#define POCMR_CM_64M 0x000FC000 +-#define POCMR_CM_32M 0x000FE000 +-#define POCMR_CM_16M 0x000FF000 +-#define POCMR_CM_8M 0x000FF800 +-#define POCMR_CM_4M 0x000FFC00 +-#define POCMR_CM_2M 0x000FFE00 +-#define POCMR_CM_1M 0x000FFF00 +-#define POCMR_CM_512K 0x000FFF80 +-#define POCMR_CM_256K 0x000FFFC0 +-#define POCMR_CM_128K 0x000FFFE0 +-#define POCMR_CM_64K 0x000FFFF0 +-#define POCMR_CM_32K 0x000FFFF8 +-#define POCMR_CM_16K 0x000FFFFC +-#define POCMR_CM_8K 0x000FFFFE +-#define POCMR_CM_4K 0x000FFFFF +- u8 res0[0x60]; +- u32 pmcr; +- u8 res1[4]; +- u32 dtcr; +- u8 res2[4]; +-} ios8349_t; ++#define POBAR_BA_MASK 0x000fffff ++#define POCMR_EN 0x80000000 ++#define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */ ++#define POCMR_SE 0x20000000 /* streaming enable */ ++#define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2 */ ++#define POCMR_CM_MASK 0x000fffff ++#define POCMR_CM_4G 0x00000000 ++#define POCMR_CM_2G 0x00080000 ++#define POCMR_CM_1G 0x000C0000 ++#define POCMR_CM_512M 0x000E0000 ++#define POCMR_CM_256M 0x000F0000 ++#define POCMR_CM_128M 0x000F8000 ++#define POCMR_CM_64M 0x000FC000 ++#define POCMR_CM_32M 0x000FE000 ++#define POCMR_CM_16M 0x000FF000 ++#define POCMR_CM_8M 0x000FF800 ++#define POCMR_CM_4M 0x000FFC00 ++#define POCMR_CM_2M 0x000FFE00 ++#define POCMR_CM_1M 0x000FFF00 ++#define POCMR_CM_512K 0x000FFF80 ++#define POCMR_CM_256K 0x000FFFC0 ++#define POCMR_CM_128K 0x000FFFE0 ++#define POCMR_CM_64K 0x000FFFF0 ++#define POCMR_CM_32K 0x000FFFF8 ++#define POCMR_CM_16K 0x000FFFFC ++#define POCMR_CM_8K 0x000FFFFE ++#define POCMR_CM_4K 0x000FFFFF ++ u8 res0[0x60]; ++ u32 pmcr; ++ u8 res1[4]; ++ u32 dtcr; ++ u8 res2[4]; ++} ios83xx_t; + + /* + * PCI Controller Control and Status Registers + */ +-typedef struct pcictrl8349 { +- u32 esr; ++typedef struct pcictrl83xx { ++ u32 esr; + #define ESR_MERR 0x80000000 + #define ESR_APAR 0x00000400 +-#define ESR_PCISERR 0x00000200 +-#define ESR_MPERR 0x00000100 +-#define ESR_TPERR 0x00000080 +-#define ESR_NORSP 0x00000040 +-#define ESR_TABT 0x00000020 +- u32 ecdr; ++#define ESR_PCISERR 0x00000200 ++#define ESR_MPERR 0x00000100 ++#define ESR_TPERR 0x00000080 ++#define ESR_NORSP 0x00000040 ++#define ESR_TABT 0x00000020 ++ u32 ecdr; + #define ECDR_APAR 0x00000400 +-#define ECDR_PCISERR 0x00000200 +-#define ECDR_MPERR 0x00000100 +-#define ECDR_TPERR 0x00000080 +-#define ECDR_NORSP 0x00000040 +-#define ECDR_TABT 0x00000020 ++#define ECDR_PCISERR 0x00000200 ++#define ECDR_MPERR 0x00000100 ++#define ECDR_TPERR 0x00000080 ++#define ECDR_NORSP 0x00000040 ++#define ECDR_TABT 0x00000020 + u32 eer; + #define EER_APAR 0x00000400 +-#define EER_PCISERR 0x00000200 +-#define EER_MPERR 0x00000100 +-#define EER_TPERR 0x00000080 +-#define EER_NORSP 0x00000040 +-#define EER_TABT 0x00000020 +- u32 eatcr; +-#define EATCR_ERRTYPR_MASK 0x70000000 +-#define EATCR_ERRTYPR_APR 0x00000000 /* address parity error */ +-#define EATCR_ERRTYPR_WDPR 0x10000000 /* write data parity error */ +-#define EATCR_ERRTYPR_RDPR 0x20000000 /* read data parity error */ +-#define EATCR_ERRTYPR_MA 0x30000000 /* master abort */ +-#define EATCR_ERRTYPR_TA 0x40000000 /* target abort */ +-#define EATCR_ERRTYPR_SE 0x50000000 /* system error indication received */ +-#define EATCR_ERRTYPR_PEA 0x60000000 /* parity error indication received on a read */ +-#define EATCR_ERRTYPR_PEW 0x70000000 /* parity error indication received on a write */ ++#define EER_PCISERR 0x00000200 ++#define EER_MPERR 0x00000100 ++#define EER_TPERR 0x00000080 ++#define EER_NORSP 0x00000040 ++#define EER_TABT 0x00000020 ++ u32 eatcr; ++#define EATCR_ERRTYPR_MASK 0x70000000 ++#define EATCR_ERRTYPR_APR 0x00000000 /* address parity error */ ++#define EATCR_ERRTYPR_WDPR 0x10000000 /* write data parity error */ ++#define EATCR_ERRTYPR_RDPR 0x20000000 /* read data parity error */ ++#define EATCR_ERRTYPR_MA 0x30000000 /* master abort */ ++#define EATCR_ERRTYPR_TA 0x40000000 /* target abort */ ++#define EATCR_ERRTYPR_SE 0x50000000 /* system error indication received */ ++#define EATCR_ERRTYPR_PEA 0x60000000 /* parity error indication received on a read */ ++#define EATCR_ERRTYPR_PEW 0x70000000 /* parity error indication received on a write */ + #define EATCR_BN_MASK 0x0f000000 /* beat number */ +-#define EATCR_BN_1st 0x00000000 +-#define EATCR_BN_2ed 0x01000000 +-#define EATCR_BN_3rd 0x02000000 +-#define EATCR_BN_4th 0x03000000 +-#define EATCR_BN_5th 0x0400000 +-#define EATCR_BN_6th 0x05000000 +-#define EATCR_BN_7th 0x06000000 +-#define EATCR_BN_8th 0x07000000 +-#define EATCR_BN_9th 0x08000000 ++#define EATCR_BN_1st 0x00000000 ++#define EATCR_BN_2ed 0x01000000 ++#define EATCR_BN_3rd 0x02000000 ++#define EATCR_BN_4th 0x03000000 ++#define EATCR_BN_5th 0x0400000 ++#define EATCR_BN_6th 0x05000000 ++#define EATCR_BN_7th 0x06000000 ++#define EATCR_BN_8th 0x07000000 ++#define EATCR_BN_9th 0x08000000 + #define EATCR_TS_MASK 0x00300000 /* transaction size */ +-#define EATCR_TS_4 0x00000000 +-#define EATCR_TS_1 0x00100000 +-#define EATCR_TS_2 0x00200000 +-#define EATCR_TS_3 0x00300000 +-#define EATCR_ES_MASK 0x000f0000 /* error source */ +-#define EATCR_ES_EM 0x00000000 /* external master */ +-#define EATCR_ES_DMA 0x00050000 +-#define EATCR_CMD_MASK 0x0000f000 +-#define EATCR_HBE_MASK 0x00000f00 /* PCI high byte enable*/ +-#define EATCR_BE_MASK 0x000000f0 /* PCI byte enable */ +-#define EATCR_HPB 0x00000004 /* high parity bit */ +-#define EATCR_PB 0x00000002 /* parity bit*/ +-#define EATCR_VI 0x00000001 /* error information valid */ +- u32 eacr; +- u32 eeacr; +- u32 edlcr; +- u32 edhcr; +- u32 gcr; +- u32 ecr; +- u32 gsr; +- u8 res0[12]; +- u32 pitar2; +- u8 res1[4]; +- u32 pibar2; +- u32 piebar2; +- u32 piwar2; +- u8 res2[4]; +- u32 pitar1; +- u8 res3[4]; +- u32 pibar1; +- u32 piebar1; +- u32 piwar1; +- u8 res4[4]; +- u32 pitar0; +- u8 res5[4]; +- u32 pibar0; +- u8 res6[4]; +- u32 piwar0; +- u8 res7[132]; ++#define EATCR_TS_4 0x00000000 ++#define EATCR_TS_1 0x00100000 ++#define EATCR_TS_2 0x00200000 ++#define EATCR_TS_3 0x00300000 ++#define EATCR_ES_MASK 0x000f0000 /* error source */ ++#define EATCR_ES_EM 0x00000000 /* external master */ ++#define EATCR_ES_DMA 0x00050000 ++#define EATCR_CMD_MASK 0x0000f000 ++#if defined (CONFIG_MPC8349) ++#define EATCR_HBE_MASK 0x00000f00 /* PCI high byte enable */ ++#endif ++#define EATCR_BE_MASK 0x000000f0 /* PCI byte enable */ ++#if defined (CONFIG_MPC8349) ++#define EATCR_HPB 0x00000004 /* high parity bit */ ++#endif ++#define EATCR_PB 0x00000002 /* parity bit */ ++#define EATCR_VI 0x00000001 /* error information valid */ ++ u32 eacr; ++ u32 eeacr; ++#if defined (CONFIG_MPC8349) ++ u32 edlcr; ++ u32 edhcr; ++#elif defined (CONFIG_MPC8360) ++ u32 edcr; /* was edlcr */ ++ u8 res_edcr[0x4]; ++#endif ++ u32 gcr; ++ u32 ecr; ++ u32 gsr; ++ u8 res0[12]; ++ u32 pitar2; ++ u8 res1[4]; ++ u32 pibar2; ++ u32 piebar2; ++ u32 piwar2; ++ u8 res2[4]; ++ u32 pitar1; ++ u8 res3[4]; ++ u32 pibar1; ++ u32 piebar1; ++ u32 piwar1; ++ u8 res4[4]; ++ u32 pitar0; ++ u8 res5[4]; ++ u32 pibar0; ++ u8 res6[4]; ++ u32 piwar0; ++ u8 res7[132]; + #define PITAR_TA_MASK 0x000fffff + #define PIBAR_MASK 0xffffffff + #define PIEBAR_EBA_MASK 0x000fffff + #define PIWAR_EN 0x80000000 + #define PIWAR_PF 0x20000000 +-#define PIWAR_RTT_MASK 0x000f0000 +-#define PIWAR_RTT_NO_SNOOP 0x00040000 ++#define PIWAR_RTT_MASK 0x000f0000 ++#define PIWAR_RTT_NO_SNOOP 0x00040000 + #define PIWAR_RTT_SNOOP 0x00050000 +-#define PIWAR_WTT_MASK 0x0000f000 +-#define PIWAR_WTT_NO_SNOOP 0x00004000 ++#define PIWAR_WTT_MASK 0x0000f000 ++#define PIWAR_WTT_NO_SNOOP 0x00004000 + #define PIWAR_WTT_SNOOP 0x00005000 +-#define PIWAR_IWS_MASK 0x0000003F +-#define PIWAR_IWS_4K 0x0000000B +-#define PIWAR_IWS_8K 0x0000000C +-#define PIWAR_IWS_16K 0x0000000D +-#define PIWAR_IWS_32K 0x0000000E +-#define PIWAR_IWS_64K 0x0000000F +-#define PIWAR_IWS_128K 0x00000010 +-#define PIWAR_IWS_256K 0x00000011 +-#define PIWAR_IWS_512K 0x00000012 +-#define PIWAR_IWS_1M 0x00000013 +-#define PIWAR_IWS_2M 0x00000014 +-#define PIWAR_IWS_4M 0x00000015 +-#define PIWAR_IWS_8M 0x00000016 +-#define PIWAR_IWS_16M 0x00000017 +-#define PIWAR_IWS_32M 0x00000018 +-#define PIWAR_IWS_64M 0x00000019 +-#define PIWAR_IWS_128M 0x0000001A +-#define PIWAR_IWS_256M 0x0000001B +-#define PIWAR_IWS_512M 0x0000001C +-#define PIWAR_IWS_1G 0x0000001D +-#define PIWAR_IWS_2G 0x0000001E +-} pcictrl8349_t; ++#define PIWAR_IWS_MASK 0x0000003F ++#define PIWAR_IWS_4K 0x0000000B ++#define PIWAR_IWS_8K 0x0000000C ++#define PIWAR_IWS_16K 0x0000000D ++#define PIWAR_IWS_32K 0x0000000E ++#define PIWAR_IWS_64K 0x0000000F ++#define PIWAR_IWS_128K 0x00000010 ++#define PIWAR_IWS_256K 0x00000011 ++#define PIWAR_IWS_512K 0x00000012 ++#define PIWAR_IWS_1M 0x00000013 ++#define PIWAR_IWS_2M 0x00000014 ++#define PIWAR_IWS_4M 0x00000015 ++#define PIWAR_IWS_8M 0x00000016 ++#define PIWAR_IWS_16M 0x00000017 ++#define PIWAR_IWS_32M 0x00000018 ++#define PIWAR_IWS_64M 0x00000019 ++#define PIWAR_IWS_128M 0x0000001A ++#define PIWAR_IWS_256M 0x0000001B ++#define PIWAR_IWS_512M 0x0000001C ++#define PIWAR_IWS_1G 0x0000001D ++#define PIWAR_IWS_2G 0x0000001E ++} pcictrl83xx_t; + ++#if defined (CONFIG_MPC8349) + /* + * USB + */ +-typedef struct usb8349 { ++typedef struct usb83xx { + u8 fixme[0x2000]; +-} usb8349_t; ++} usb83xx_t; + + /* + * TSEC + */ +-typedef struct tsec8349 { ++typedef struct tsec83xx { + u8 fixme[0x1000]; +-} tsec8349_t; ++} tsec83xx_t; ++#endif + + /* + * Security + */ +-typedef struct security8349 { ++typedef struct security83xx { + u8 fixme[0x10000]; +-} security8349_t; ++} security83xx_t; ++ ++#if defined (CONFIG_MPC8360) ++/* ++ * iram ++ */ ++typedef struct iram83xx { ++ u32 iadd; /* I-RAM address register */ ++ u32 idata; /* I-RAM data register */ ++ u8 res0[0x78]; ++} iram83xx_t; ++ ++/* ++ * Interrupt Controller ++ */ ++typedef struct irq83xx { ++ u32 cicr; /* QE system interrupt configuration */ ++ u32 civec; /* QE system interrupt vector register */ ++ u32 cripnr; /* QE RISC interrupt pending register */ ++ u32 cipnr; /* QE system interrupt pending register */ ++ u32 cipxcc; /* QE interrupt priority register */ ++ u32 cipycc; /* QE interrupt priority register */ ++ u32 cipwcc; /* QE interrupt priority register */ ++ u32 cipzcc; /* QE interrupt priority register */ ++ u32 cimr; /* QE system interrupt mask register */ ++ u32 crimr; /* QE RISC interrupt mask register */ ++ u32 cicnr; /* QE system interrupt control register */ ++ u8 res0[0x4]; ++ u32 ciprta; /* QE system interrupt priority register for RISC tasks A */ ++ u32 ciprtb; /* QE system interrupt priority register for RISC tasks B */ ++ u8 res1[0x4]; ++ u32 cricr; /* QE system RISC interrupt control */ ++ u8 res2[0x20]; ++ u32 chivec; /* QE high system interrupt vector */ ++ u8 res3[0x1C]; ++} irq83xx_t; ++ ++/* ++ * Communications Processor ++ */ ++typedef struct cp83xx { ++ u32 cecr; /* QE command register */ ++ u32 ceccr; /* QE controller configuration register */ ++ u32 cecdr; /* QE command data register */ ++ u8 res0[0xA]; ++ u16 ceter; /* QE timer event register */ ++ u8 res1[0x2]; ++ u16 cetmr; /* QE timers mask register */ ++ u32 cetscr; /* QE time-stamp timer control register */ ++ u32 cetsr1; /* QE time-stamp register 1 */ ++ u32 cetsr2; /* QE time-stamp register 2 */ ++ u8 res2[0x8]; ++ u32 cevter; /* QE virtual tasks event register */ ++ u32 cevtmr; /* QE virtual tasks mask register */ ++ u16 cercr; /* QE RAM control register */ ++ u8 res3[0x2]; ++ u8 res4[0x24]; ++ u16 ceexe1; /* QE external request 1 event register */ ++ u8 res5[0x2]; ++ u16 ceexm1; /* QE external request 1 mask register */ ++ u8 res6[0x2]; ++ u16 ceexe2; /* QE external request 2 event register */ ++ u8 res7[0x2]; ++ u16 ceexm2; /* QE external request 2 mask register */ ++ u8 res8[0x2]; ++ u16 ceexe3; /* QE external request 3 event register */ ++ u8 res9[0x2]; ++ u16 ceexm3; /* QE external request 3 mask register */ ++ u8 res10[0x2]; ++ u16 ceexe4; /* QE external request 4 event register */ ++ u8 res11[0x2]; ++ u16 ceexm4; /* QE external request 4 mask register */ ++ u8 res12[0x2]; ++ u8 res13[0x280]; ++} cp83xx_t; ++ ++/* ++ * QE Multiplexer ++ */ ++ ++typedef struct qmx83xx { ++ u32 cmxgcr; /* CMX general clock route register */ ++ u32 cmxsi1cr_l; /* CMX SI1 clock route low register */ ++ u32 cmxsi1cr_h; /* CMX SI1 clock route high register */ ++ u32 cmxsi1syr; /* CMX SI1 SYNC route register */ ++ u32 cmxucr1; /* CMX UCC1, UCC3 clock route register */ ++ u32 cmxucr2; /* CMX UCC5, UCC7 clock route register */ ++ u32 cmxucr3; /* CMX UCC2, UCC4 clock route register */ ++ u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */ ++ u32 cmxupcr; /* CMX UPC clock route register */ ++ u8 res0[0x1C]; ++} qmx83xx_t; ++ ++/* ++* QE Timers ++*/ ++ ++typedef struct qet83xx { ++ u8 gtcfr1; /* Timer 1 and Timer 2 global configuration register */ ++ u8 res0[0x3]; ++ u8 gtcfr2; /* Timer 3 and timer 4 global configuration register */ ++ u8 res1[0xB]; ++ u16 gtmdr1; /* Timer 1 mode register */ ++ u16 gtmdr2; /* Timer 2 mode register */ ++ u16 gtrfr1; /* Timer 1 reference register */ ++ u16 gtrfr2; /* Timer 2 reference register */ ++ u16 gtcpr1; /* Timer 1 capture register */ ++ u16 gtcpr2; /* Timer 2 capture register */ ++ u16 gtcnr1; /* Timer 1 counter */ ++ u16 gtcnr2; /* Timer 2 counter */ ++ u16 gtmdr3; /* Timer 3 mode register */ ++ u16 gtmdr4; /* Timer 4 mode register */ ++ u16 gtrfr3; /* Timer 3 reference register */ ++ u16 gtrfr4; /* Timer 4 reference register */ ++ u16 gtcpr3; /* Timer 3 capture register */ ++ u16 gtcpr4; /* Timer 4 capture register */ ++ u16 gtcnr3; /* Timer 3 counter */ ++ u16 gtcnr4; /* Timer 4 counter */ ++ u16 gtevr1; /* Timer 1 event register */ ++ u16 gtevr2; /* Timer 2 event register */ ++ u16 gtevr3; /* Timer 3 event register */ ++ u16 gtevr4; /* Timer 4 event register */ ++ u16 gtps; /* Timer 1 prescale register */ ++ u8 res2[0x46]; ++} qet83xx_t; ++ ++/* ++* spi ++*/ ++ ++typedef struct spi83xx { ++ u8 res0[0x20]; ++ u32 spmode; /* SPI mode register */ ++ u8 res1[0x2]; ++ u8 spie; /* SPI event register */ ++ u8 res2[0x1]; ++ u8 res3[0x2]; ++ u8 spim; /* SPI mask register */ ++ u8 res4[0x1]; ++ u8 res5[0x1]; ++ u8 spcom; /* SPI command register */ ++ u8 res6[0x2]; ++ u32 spitd; /* SPI transmit data register (cpu mode) */ ++ u32 spird; /* SPI receive data register (cpu mode) */ ++ u8 res7[0x8]; ++} spi83xx_t; ++ ++/* ++* mcc ++*/ ++ ++typedef struct mcc83xx { ++ u32 mcce; /* MCC event register */ ++ u32 mccm; /* MCC mask register */ ++ u32 mccf; /* MCC configuration register */ ++ u32 merl; /* MCC emergency request level register */ ++ u8 res0[0xF0]; ++} mcc83xx_t; ++ ++/* ++* brg ++*/ ++ ++typedef struct brg83xx { ++ u32 brgc1; /* BRG1 configuration register */ ++ u32 brgc2; /* BRG2 configuration register */ ++ u32 brgc3; /* BRG3 configuration register */ ++ u32 brgc4; /* BRG4 configuration register */ ++ u32 brgc5; /* BRG5 configuration register */ ++ u32 brgc6; /* BRG6 configuration register */ ++ u32 brgc7; /* BRG7 configuration register */ ++ u32 brgc8; /* BRG8 configuration register */ ++ u32 brgc9; /* BRG9 configuration register */ ++ u32 brgc10; /* BRG10 configuration register */ ++ u32 brgc11; /* BRG11 configuration register */ ++ u32 brgc12; /* BRG12 configuration register */ ++ u32 brgc13; /* BRG13 configuration register */ ++ u32 brgc14; /* BRG14 configuration register */ ++ u32 brgc15; /* BRG15 configuration register */ ++ u32 brgc16; /* BRG16 configuration register */ ++ u8 res0[0x40]; ++} brg83xx_t; ++ ++/* ++* USB ++*/ ++ ++typedef struct usb83xx { ++ u8 usmod; /* USB mode register */ ++ u8 usadd; /* USB address register */ ++ u8 uscom; /* USB command register */ ++ u8 res0[0x1]; ++ u16 usep0; /* USB endpoint register 0 */ ++ u16 usep1; /* USB endpoint register 1 */ ++ u16 usep2; /* USB endpoint register 2 */ ++ u16 usep3; /* USB endpoint register 3 */ ++ u8 res1[0x4]; ++ u16 usber; /* USB event register */ ++ u8 res2[0x2]; ++ u16 usbmr; /* USB mask register */ ++ u8 res3[0x1]; ++ u8 usbs; /* USB status register */ ++ u32 ussft; /* USB start of frame timer */ ++ u8 res4[0x24]; ++} usb83xx_t; ++ ++/* ++* SI ++*/ ++ ++typedef struct si1_83xx { ++ u16 siamr1; /* SI1 TDMA mode register */ ++ u16 sibmr1; /* SI1 TDMB mode register */ ++ u16 sicmr1; /* SI1 TDMC mode register */ ++ u16 sidmr1; /* SI1 TDMD mode register */ ++ u8 siglmr1_h; /* SI1 global mode register high */ ++ u8 res0[0x1]; ++ u8 sicmdr1_h; /* SI1 command register high */ ++ u8 res2[0x1]; ++ u8 sistr1_h; /* SI1 status register high */ ++ u8 res3[0x1]; ++ u16 sirsr1_h; /* SI1 RAM shadow address register high */ ++ u8 sitarc1; /* SI1 RAM counter Tx TDMA */ ++ u8 sitbrc1; /* SI1 RAM counter Tx TDMB */ ++ u8 sitcrc1; /* SI1 RAM counter Tx TDMC */ ++ u8 sitdrc1; /* SI1 RAM counter Tx TDMD */ ++ u8 sirarc1; /* SI1 RAM counter Rx TDMA */ ++ u8 sirbrc1; /* SI1 RAM counter Rx TDMB */ ++ u8 sircrc1; /* SI1 RAM counter Rx TDMC */ ++ u8 sirdrc1; /* SI1 RAM counter Rx TDMD */ ++ u8 res4[0x8]; ++ u16 siemr1; /* SI1 TDME mode register 16 bits */ ++ u16 sifmr1; /* SI1 TDMF mode register 16 bits */ ++ u16 sigmr1; /* SI1 TDMG mode register 16 bits */ ++ u16 sihmr1; /* SI1 TDMH mode register 16 bits */ ++ u8 siglmg1_l; /* SI1 global mode register low 8 bits */ ++ u8 res5[0x1]; ++ u8 sicmdr1_l; /* SI1 command register low 8 bits */ ++ u8 res6[0x1]; ++ u8 sistr1_l; /* SI1 status register low 8 bits */ ++ u8 res7[0x1]; ++ u16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits */ ++ u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */ ++ u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */ ++ u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */ ++ u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */ ++ u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */ ++ u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */ ++ u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */ ++ u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */ ++ u8 res8[0x8]; ++ u32 siml1; /* SI1 multiframe limit register */ ++ u8 siedm1; /* SI1 extended diagnostic mode register */ ++ u8 res9[0xBB]; ++} si1_83xx_t; ++ ++/* ++* SI Routing Tables ++*/ ++ ++typedef struct sir83xx { ++ u8 tx[0x400]; ++ u8 rx[0x400]; ++ u8 res0[0x800]; ++} sir83xx_t; ++ ++/* ++* ucc ++*/ ++ ++typedef struct uslow { ++ u32 gumr_l; /* UCCx general mode register (low) */ ++ u32 gumr_h; /* UCCx general mode register (high) */ ++ u16 upsmr; /* UCCx protocol-specific mode register */ ++ u8 res0[0x2]; ++ u16 utodr; /* UCCx transmit on demand register */ ++ u16 udsr; /* UCCx data synchronization register */ ++ u16 ucce; /* UCCx event register */ ++ u8 res1[0x2]; ++ u16 uccm; /* UCCx mask register */ ++ u8 res2[0x1]; ++ u8 uccs; /* UCCx status register */ ++ u8 res3[0x1E8]; ++} uslow_t; ++ ++typedef struct ufast { ++ u32 gumr; /* UCCx general mode register */ ++ u32 upsmr; /* UCCx protocol-specific mode register */ ++ u16 utodr; /* UCCx transmit on demand register */ ++ u8 res0[0x2]; ++ u16 udsr; /* UCCx data synchronization register */ ++ u8 res1[0x2]; ++ u32 ucce; /* UCCx event register */ ++ u32 uccm; /* UCCx mask register. */ ++ u8 uccs; /* UCCx status register */ ++ u8 res2[0x7]; ++ u32 urfb; /* UCC receive FIFO base */ ++ u16 urfs; /* UCC receive FIFO size */ ++ u8 res3[0x2]; ++ u16 urfet; /* UCC receive FIFO emergency threshold */ ++ u16 urfset; /* UCC receive FIFO special emergency threshold */ ++ u32 utfb; /* UCC transmit FIFO base */ ++ u16 utfs; /* UCC transmit FIFO size */ ++ u8 res4[0x2]; ++ u16 utfet; /* UCC transmit FIFO emergency threshold */ ++ u8 res5[0x2]; ++ u16 utftt; /* UCC transmit FIFO transmit threshold */ ++ u8 res6[0x2]; ++ u16 utpt; /* UCC transmit polling timer */ ++ u32 urtry; /* UCC retry counter register */ ++ u8 res7[0x4C]; ++ u8 guemr; /* UCC general extended mode register */ ++ u8 res8[0x3]; ++ u8 res9[0x6C]; ++ u32 maccfg1; /* Mac configuration register #1 */ ++ u32 maccfg2; /* Mac configuration register #2 */ ++ u16 ipgifg; /* Interframe gap register */ ++ u8 res10[0x2]; ++ u32 hafdup; /* Half-duplex register */ ++ u8 res11[0xC]; ++ u32 emtr; /* Ethernet MAC test register */ ++ u32 miimcfg; /* MII mgmt configuration register */ ++ u32 miimcom; /* MII mgmt command register */ ++ u32 miimadd; /* MII mgmt address register */ ++ u32 miimcon; /* MII mgmt control register */ ++ u32 miistat; /* MII mgmt status register */ ++ u32 miimnd; /* MII mgmt indication register */ ++ u32 ifctl; /* Interface control register */ ++ u32 ifstat; /* Interface status register */ ++ u32 macstnaddr1; /* Station address part 1 register */ ++ u32 macstnaddr2; /* Station address part 2 register */ ++ u8 res12[0x8]; ++ u32 uempr; /* UCC Ethernet MAC parameter register */ ++ u32 utbipa; /* UCC TBI address */ ++ u16 uescr; /* UCC Ethernet statistics control register */ ++ u8 res13[0x26]; ++ u32 tx64; /* Transmit and receive 64-byte frame counter */ ++ u32 tx127; /* Transmit and receive 65- to 127-byte frame counter */ ++ u32 tx255; /* Transmit and receive 128- to 255-byte frame counter */ ++ u32 rx64; /* Receive and receive 64-byte frame counter */ ++ u32 rx127; /* Receive and receive 65- to 127-byte frame counter */ ++ u32 rx255; /* Receive and receive 128- to 255-byte frame counter */ ++ u32 txok; /* Transmit good bytes counter */ ++ u32 txcf; /* Transmit control frame counter */ ++ u32 tmca; /* Transmit multicast control frame counter */ ++ u32 tbca; /* Transmit broadcast packet counter */ ++ u32 rxfok; /* Receive frame OK counter */ ++ u32 rbyt; /* Receive good and bad bytes counter */ ++ u32 rxbok; /* Receive bytes OK counter */ ++ u32 rmca; /* Receive multicast packet counter */ ++ u32 rbca; /* Receive broadcast packet counter */ ++ u32 scar; /* Statistics carry register */ ++ u32 scam; /* Statistics carry mask register */ ++ u8 res14[0x3C]; ++} ufast_t; ++ ++typedef struct ucc83xx { ++ union { ++ uslow_t slow; ++ ufast_t fast; ++ }; ++} ucc83xx_t; ++ ++/* ++* MultiPHY UTOPIA POS Controllers ++*/ ++ ++typedef struct upc83xx { ++ u32 upgcr; /* UTOPIA/POS general configuration register */ ++#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */ ++#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */ ++#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */ ++#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing: */ ++#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */ ++ u32 uplpa; /* UTOPIA/POS last PHY address */ ++ u32 uphec; /* ATM HEC register */ ++ u32 upuc; /* UTOPIA/POS UCC configuration */ ++ u32 updc1; /* UTOPIA/POS device 1 configuration */ ++ u32 updc2; /* UTOPIA/POS device 2 configuration */ ++ u32 updc3; /* UTOPIA/POS device 3 configuration */ ++ u32 updc4; /* UTOPIA/POS device 4 configuration */ ++ u32 upstpa; /* UTOPIA/POS STPA threshold */ ++ u8 res0[0xC]; ++ u32 updrs1_h; /* UTOPIA/POS device 1 rate select */ ++ u32 updrs1_l; /* UTOPIA/POS device 1 rate select */ ++ u32 updrs2_h; /* UTOPIA/POS device 2 rate select */ ++ u32 updrs2_l; /* UTOPIA/POS device 2 rate select */ ++ u32 updrs3_h; /* UTOPIA/POS device 3 rate select */ ++ u32 updrs3_l; /* UTOPIA/POS device 3 rate select */ ++ u32 updrs4_h; /* UTOPIA/POS device 4 rate select */ ++ u32 updrs4_l; /* UTOPIA/POS device 4 rate select */ ++ u32 updrp1; /* UTOPIA/POS device 1 receive priority low */ ++ u32 updrp2; /* UTOPIA/POS device 2 receive priority low */ ++ u32 updrp3; /* UTOPIA/POS device 3 receive priority low */ ++ u32 updrp4; /* UTOPIA/POS device 4 receive priority low */ ++ u32 upde1; /* UTOPIA/POS device 1 event */ ++ u32 upde2; /* UTOPIA/POS device 2 event */ ++ u32 upde3; /* UTOPIA/POS device 3 event */ ++ u32 upde4; /* UTOPIA/POS device 4 event */ ++ u16 uprp1; ++ u16 uprp2; ++ u16 uprp3; ++ u16 uprp4; ++ u8 res1[0x8]; ++ u16 uptirr1_0; /* Device 1 transmit internal rate 0 */ ++ u16 uptirr1_1; /* Device 1 transmit internal rate 1 */ ++ u16 uptirr1_2; /* Device 1 transmit internal rate 2 */ ++ u16 uptirr1_3; /* Device 1 transmit internal rate 3 */ ++ u16 uptirr2_0; /* Device 2 transmit internal rate 0 */ ++ u16 uptirr2_1; /* Device 2 transmit internal rate 1 */ ++ u16 uptirr2_2; /* Device 2 transmit internal rate 2 */ ++ u16 uptirr2_3; /* Device 2 transmit internal rate 3 */ ++ u16 uptirr3_0; /* Device 3 transmit internal rate 0 */ ++ u16 uptirr3_1; /* Device 3 transmit internal rate 1 */ ++ u16 uptirr3_2; /* Device 3 transmit internal rate 2 */ ++ u16 uptirr3_3; /* Device 3 transmit internal rate 3 */ ++ u16 uptirr4_0; /* Device 4 transmit internal rate 0 */ ++ u16 uptirr4_1; /* Device 4 transmit internal rate 1 */ ++ u16 uptirr4_2; /* Device 4 transmit internal rate 2 */ ++ u16 uptirr4_3; /* Device 4 transmit internal rate 3 */ ++ u32 uper1; /* Device 1 port enable register */ ++ u32 uper2; /* Device 2 port enable register */ ++ u32 uper3; /* Device 3 port enable register */ ++ u32 uper4; /* Device 4 port enable register */ ++ u8 res2[0x150]; ++} upc83xx_t; ++ ++/* ++* SDMA ++*/ ++ ++typedef struct sdma83xx { ++ u32 sdsr; /* Serial DMA status register */ ++ u32 sdmr; /* Serial DMA mode register */ ++ u32 sdtr1; /* SDMA system bus threshold register */ ++ u32 sdtr2; /* SDMA secondary bus threshold register */ ++ u32 sdhy1; /* SDMA system bus hysteresis register */ ++ u32 sdhy2; /* SDMA secondary bus hysteresis register */ ++ u32 sdta1; /* SDMA system bus address register */ ++ u32 sdta2; /* SDMA secondary bus address register */ ++ u32 sdtm1; /* SDMA system bus MSNUM register */ ++ u32 sdtm2; /* SDMA secondary bus MSNUM register */ ++ u8 res0[0x10]; ++ u32 sdaqr; /* SDMA address bus qualify register */ ++ u32 sdaqmr; /* SDMA address bus qualify mask register */ ++ u8 res1[0x4]; ++ u32 sdwbcr; /* SDMA CAM entries base register */ ++ u8 res2[0x38]; ++} sdma83xx_t; ++ ++/* ++* Debug Space ++*/ ++ ++typedef struct dbg83xx { ++ u32 bpdcr; /* Breakpoint debug command register */ ++ u32 bpdsr; /* Breakpoint debug status register */ ++ u32 bpdmr; /* Breakpoint debug mask register */ ++ u32 bprmrr0; /* Breakpoint request mode risc register 0 */ ++ u32 bprmrr1; /* Breakpoint request mode risc register 1 */ ++ u8 res0[0x8]; ++ u32 bprmtr0; /* Breakpoint request mode trb register 0 */ ++ u32 bprmtr1; /* Breakpoint request mode trb register 1 */ ++ u8 res1[0x8]; ++ u32 bprmir; /* Breakpoint request mode immediate register */ ++ u32 bprmsr; /* Breakpoint request mode serial register */ ++ u32 bpemr; /* Breakpoint exit mode register */ ++ u8 res2[0x48]; ++} dbg83xx_t; ++ ++/* ++* RISC Special Registers (Trap and Breakpoint) ++*/ ++ ++typedef struct rsp83xx { ++ u8 fixme[0x100]; ++} rsp83xx_t; ++#endif + + typedef struct immap { +- sysconf8349_t sysconf; /* System configuration */ +- wdt8349_t wdt; /* Watch Dog Timer (WDT) Registers */ +- rtclk8349_t rtc; /* Real Time Clock Module Registers */ +- rtclk8349_t pit; /* Periodic Interval Timer */ +- gtm8349_t gtm[2]; /* Global Timers Module */ +- ipic8349_t ipic; /* Integrated Programmable Interrupt Controller */ +- arbiter8349_t arbiter; /* System Arbiter Registers */ +- reset8349_t reset; /* Reset Module */ +- clk8349_t clk; /* System Clock Module */ +- pmc8349_t pmc; /* Power Management Control Module */ +- gpio8349_t pgio[2]; /* general purpose I/O module */ ++ sysconf83xx_t sysconf; /* System configuration */ ++ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ ++ rtclk83xx_t rtc; /* Real Time Clock Module Registers */ ++ rtclk83xx_t pit; /* Periodic Interval Timer */ ++ gtm83xx_t gtm[2]; /* Global Timers Module */ ++ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ ++ arbiter83xx_t arbiter; /* System Arbiter Registers */ ++ reset83xx_t reset; /* Reset Module */ ++ clk83xx_t clk; /* System Clock Module */ ++ pmc83xx_t pmc; /* Power Management Control Module */ ++#if defined (CONFIG_MPC8349) ++ gpio83xx_t pgio[2]; /* general purpose I/O module */ ++#elif defined (CONFIG_MPC8360) ++ qepi83xx_t qepi; /* QE Ports Interrupts Registers */ ++#endif + u8 res0[0x200]; ++#if defined (CONFIG_MPC8360) ++ u8 DLL_LBDDR[0x100]; ++#endif + u8 DDL_DDR[0x100]; + u8 DDL_LBIU[0x100]; ++#if defined (CONFIG_MPC8349) + u8 res1[0xE00]; +- ddr8349_t ddr; /* DDR Memory Controller Memory */ +- i2c_t i2c[2]; /* I2C1 Controller */ ++#elif defined (CONFIG_MPC8360) ++ u8 res1[0x200]; ++ gpio83xx_t gpio; /* General purpose I/O module */ ++ qesba83xx_t qesba; /* QE Secondary Bus Access Windows */ ++#endif ++ ddr83xx_t ddr; /* DDR Memory Controller Memory */ ++ fsl_i2c_t i2c[2]; /* I2C Controllers */ + u8 res2[0x1300]; +- duart8349_t duart[2];/* DUART */ ++ duart83xx_t duart[2]; /* DUART */ ++#if defined (CONFIG_MPC8349) + u8 res3[0x900]; +- lbus8349_t lbus; /* Local Bus Controller Registers */ ++ lbus83xx_t lbus; /* Local Bus Controller Registers */ + u8 res4[0x1000]; +- spi8349_t spi; /* Serial Peripheral Interface */ ++ spi83xx_t spi; /* Serial Peripheral Interface */ + u8 res5[0xF00]; +- dma8349_t dma; /* DMA */ +- pciconf8349_t pci_conf[2]; /* PCI Software Configuration Registers */ +- ios8349_t ios; /* Sequencer */ +- pcictrl8349_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */ ++#elif defined (CONFIG_MPC8360) ++ u8 res3[0x900]; ++ lbus83xx_t lbus; /* Local Bus Controller */ ++ u8 res4[0x2000]; ++#endif ++ dma83xx_t dma; /* DMA */ ++#if defined (CONFIG_MPC8349) ++ pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */ ++ ios83xx_t ios; /* Sequencer */ ++ pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */ + u8 res6[0x19900]; +- usb8349_t usb; +- tsec8349_t tsec[2]; ++ usb83xx_t usb; ++ tsec83xx_t tsec[2]; + u8 res7[0xA000]; +- security8349_t security; ++ security83xx_t security; ++#elif defined (CONFIG_MPC8360) ++ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ ++ u8 res_5[128]; ++ ios83xx_t ios; /* Sequencer (IOS) */ ++ pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ ++ u8 res6[0x4A00]; ++ ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */ ++ u8 res7[0x22000]; ++ security83xx_t security; ++ u8 res8[0xC0000]; ++ iram83xx_t iram; /* IRAM */ ++ irq83xx_t irq; /* Interrupt Controller */ ++ cp83xx_t cp; /* Communications Processor */ ++ qmx83xx_t qmx; /* QE Multiplexer */ ++ qet83xx_t qet; /* QE Timers */ ++ spi83xx_t spi[0x2]; /* spi */ ++ mcc83xx_t mcc; /* mcc */ ++ brg83xx_t brg; /* brg */ ++ usb83xx_t usb; /* USB */ ++ si1_83xx_t si1; /* SI */ ++ u8 res9[0x800]; ++ sir83xx_t sir; /* SI Routing Tables */ ++ ucc83xx_t ucc1; /* ucc1 */ ++ ucc83xx_t ucc3; /* ucc3 */ ++ ucc83xx_t ucc5; /* ucc5 */ ++ ucc83xx_t ucc7; /* ucc7 */ ++ u8 res10[0x600]; ++ upc83xx_t upc1; /* MultiPHY UTOPIA POS Controller 1 */ ++ ucc83xx_t ucc2; /* ucc2 */ ++ ucc83xx_t ucc4; /* ucc4 */ ++ ucc83xx_t ucc6; /* ucc6 */ ++ ucc83xx_t ucc8; /* ucc8 */ ++ u8 res11[0x600]; ++ upc83xx_t upc2; /* MultiPHY UTOPIA POS Controller 2 */ ++ sdma83xx_t sdma; /* SDMA */ ++ dbg83xx_t dbg; /* Debug Space */ ++ rsp83xx_t rsp[0x2]; /* RISC Special Registers (Trap and Breakpoint) */ ++ u8 res12[0x300]; ++ u8 res13[0x3A00]; ++ u8 res14[0x8000]; /* 0x108000 - 0x110000 */ ++ u8 res15[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */ ++ u8 res16[0x24000]; /* 0x11C000 - 0x140000 */ ++ u8 res17[0xC0000]; /* 0x140000 - 0x200000 */ ++#endif + } immap_t; + +-#endif /* __IMMAP_8349__ */ ++#endif /* __IMMAP_83xx__ */ +diff -Naupr u-boot-1.1.6/include/asm-ppc/immap_qe.h u-boot-1.1.6-fsl-1/include/asm-ppc/immap_qe.h +--- u-boot-1.1.6/include/asm-ppc/immap_qe.h 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/asm-ppc/immap_qe.h 2006-11-10 11:24:29.000000000 -0600 +@@ -0,0 +1,550 @@ ++/* ++ * QUICC Engine (QE) Internal Memory Map. ++ * The Internal Memory Map for devices with QE on them. This ++ * is the superset of all QE devices (8360, etc.). ++ * ++ * Copyright (c) 2006 Freescale Semiconductor, Inc. ++ * Author: Shlomi Gridih ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#ifndef __IMMAP_QE_H__ ++#define __IMMAP_QE_H__ ++ ++/* QE I-RAM ++*/ ++typedef struct qe_iram { ++ u32 iadd; /* I-RAM Address Register */ ++ u32 idata; /* I-RAM Data Register */ ++ u8 res0[0x78]; ++} __attribute__ ((packed)) qe_iram_t; ++ ++/* QE Interrupt Controller ++*/ ++typedef struct qe_ic { ++ u32 qicr; ++ u32 qivec; ++ u32 qripnr; ++ u32 qipnr; ++ u32 qipxcc; ++ u32 qipycc; ++ u32 qipwcc; ++ u32 qipzcc; ++ u32 qimr; ++ u32 qrimr; ++ u32 qicnr; ++ u8 res0[0x4]; ++ u32 qiprta; ++ u32 qiprtb; ++ u8 res1[0x4]; ++ u32 qricr; ++ u8 res2[0x20]; ++ u32 qhivec; ++ u8 res3[0x1C]; ++} __attribute__ ((packed)) qe_ic_t; ++ ++/* Communications Processor ++*/ ++typedef struct cp_qe { ++ u32 cecr; /* QE command register */ ++ u32 ceccr; /* QE controller configuration register */ ++ u32 cecdr; /* QE command data register */ ++ u8 res0[0xA]; ++ u16 ceter; /* QE timer event register */ ++ u8 res1[0x2]; ++ u16 cetmr; /* QE timers mask register */ ++ u32 cetscr; /* QE time-stamp timer control register */ ++ u32 cetsr1; /* QE time-stamp register 1 */ ++ u32 cetsr2; /* QE time-stamp register 2 */ ++ u8 res2[0x8]; ++ u32 cevter; /* QE virtual tasks event register */ ++ u32 cevtmr; /* QE virtual tasks mask register */ ++ u16 cercr; /* QE RAM control register */ ++ u8 res3[0x2]; ++ u8 res4[0x24]; ++ u16 ceexe1; /* QE external request 1 event register */ ++ u8 res5[0x2]; ++ u16 ceexm1; /* QE external request 1 mask register */ ++ u8 res6[0x2]; ++ u16 ceexe2; /* QE external request 2 event register */ ++ u8 res7[0x2]; ++ u16 ceexm2; /* QE external request 2 mask register */ ++ u8 res8[0x2]; ++ u16 ceexe3; /* QE external request 3 event register */ ++ u8 res9[0x2]; ++ u16 ceexm3; /* QE external request 3 mask register */ ++ u8 res10[0x2]; ++ u16 ceexe4; /* QE external request 4 event register */ ++ u8 res11[0x2]; ++ u16 ceexm4; /* QE external request 4 mask register */ ++ u8 res12[0x2]; ++ u8 res13[0x280]; ++} __attribute__ ((packed)) cp_qe_t; ++ ++/* QE Multiplexer ++*/ ++typedef struct qe_mux { ++ u32 cmxgcr; /* CMX general clock route register */ ++ u32 cmxsi1cr_l; /* CMX SI1 clock route low register */ ++ u32 cmxsi1cr_h; /* CMX SI1 clock route high register */ ++ u32 cmxsi1syr; /* CMX SI1 SYNC route register */ ++ u32 cmxucr1; /* CMX UCC1, UCC3 clock route register */ ++ u32 cmxucr2; /* CMX UCC5, UCC7 clock route register */ ++ u32 cmxucr3; /* CMX UCC2, UCC4 clock route register */ ++ u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */ ++ u32 cmxupcr; /* CMX UPC clock route register */ ++ u8 res0[0x1C]; ++} __attribute__ ((packed)) qe_mux_t; ++ ++/* QE Timers ++*/ ++typedef struct qe_timers { ++ u8 gtcfr1; /* Timer 1 2 global configuration register */ ++ u8 res0[0x3]; ++ u8 gtcfr2; /* Timer 3 4 global configuration register */ ++ u8 res1[0xB]; ++ u16 gtmdr1; /* Timer 1 mode register */ ++ u16 gtmdr2; /* Timer 2 mode register */ ++ u16 gtrfr1; /* Timer 1 reference register */ ++ u16 gtrfr2; /* Timer 2 reference register */ ++ u16 gtcpr1; /* Timer 1 capture register */ ++ u16 gtcpr2; /* Timer 2 capture register */ ++ u16 gtcnr1; /* Timer 1 counter */ ++ u16 gtcnr2; /* Timer 2 counter */ ++ u16 gtmdr3; /* Timer 3 mode register */ ++ u16 gtmdr4; /* Timer 4 mode register */ ++ u16 gtrfr3; /* Timer 3 reference register */ ++ u16 gtrfr4; /* Timer 4 reference register */ ++ u16 gtcpr3; /* Timer 3 capture register */ ++ u16 gtcpr4; /* Timer 4 capture register */ ++ u16 gtcnr3; /* Timer 3 counter */ ++ u16 gtcnr4; /* Timer 4 counter */ ++ u16 gtevr1; /* Timer 1 event register */ ++ u16 gtevr2; /* Timer 2 event register */ ++ u16 gtevr3; /* Timer 3 event register */ ++ u16 gtevr4; /* Timer 4 event register */ ++ u16 gtps; /* Timer 1 prescale register */ ++ u8 res2[0x46]; ++} __attribute__ ((packed)) qe_timers_t; ++ ++/* BRG ++*/ ++typedef struct qe_brg { ++ u32 brgc1; /* BRG1 configuration register */ ++ u32 brgc2; /* BRG2 configuration register */ ++ u32 brgc3; /* BRG3 configuration register */ ++ u32 brgc4; /* BRG4 configuration register */ ++ u32 brgc5; /* BRG5 configuration register */ ++ u32 brgc6; /* BRG6 configuration register */ ++ u32 brgc7; /* BRG7 configuration register */ ++ u32 brgc8; /* BRG8 configuration register */ ++ u32 brgc9; /* BRG9 configuration register */ ++ u32 brgc10; /* BRG10 configuration register */ ++ u32 brgc11; /* BRG11 configuration register */ ++ u32 brgc12; /* BRG12 configuration register */ ++ u32 brgc13; /* BRG13 configuration register */ ++ u32 brgc14; /* BRG14 configuration register */ ++ u32 brgc15; /* BRG15 configuration register */ ++ u32 brgc16; /* BRG16 configuration register */ ++ u8 res0[0x40]; ++} __attribute__ ((packed)) qe_brg_t; ++ ++/* SPI ++*/ ++typedef struct spi { ++ u8 res0[0x20]; ++ u32 spmode; /* SPI mode register */ ++ u8 res1[0x2]; ++ u8 spie; /* SPI event register */ ++ u8 res2[0x1]; ++ u8 res3[0x2]; ++ u8 spim; /* SPI mask register */ ++ u8 res4[0x1]; ++ u8 res5[0x1]; ++ u8 spcom; /* SPI command register */ ++ u8 res6[0x2]; ++ u32 spitd; /* SPI transmit data register (cpu mode) */ ++ u32 spird; /* SPI receive data register (cpu mode) */ ++ u8 res7[0x8]; ++} __attribute__ ((packed)) spi_t; ++ ++/* SI ++*/ ++typedef struct si1 { ++ u16 siamr1; /* SI1 TDMA mode register */ ++ u16 sibmr1; /* SI1 TDMB mode register */ ++ u16 sicmr1; /* SI1 TDMC mode register */ ++ u16 sidmr1; /* SI1 TDMD mode register */ ++ u8 siglmr1_h; /* SI1 global mode register high */ ++ u8 res0[0x1]; ++ u8 sicmdr1_h; /* SI1 command register high */ ++ u8 res2[0x1]; ++ u8 sistr1_h; /* SI1 status register high */ ++ u8 res3[0x1]; ++ u16 sirsr1_h; /* SI1 RAM shadow address register high */ ++ u8 sitarc1; /* SI1 RAM counter Tx TDMA */ ++ u8 sitbrc1; /* SI1 RAM counter Tx TDMB */ ++ u8 sitcrc1; /* SI1 RAM counter Tx TDMC */ ++ u8 sitdrc1; /* SI1 RAM counter Tx TDMD */ ++ u8 sirarc1; /* SI1 RAM counter Rx TDMA */ ++ u8 sirbrc1; /* SI1 RAM counter Rx TDMB */ ++ u8 sircrc1; /* SI1 RAM counter Rx TDMC */ ++ u8 sirdrc1; /* SI1 RAM counter Rx TDMD */ ++ u8 res4[0x8]; ++ u16 siemr1; /* SI1 TDME mode register 16 bits */ ++ u16 sifmr1; /* SI1 TDMF mode register 16 bits */ ++ u16 sigmr1; /* SI1 TDMG mode register 16 bits */ ++ u16 sihmr1; /* SI1 TDMH mode register 16 bits */ ++ u8 siglmg1_l; /* SI1 global mode register low 8 bits */ ++ u8 res5[0x1]; ++ u8 sicmdr1_l; /* SI1 command register low 8 bits */ ++ u8 res6[0x1]; ++ u8 sistr1_l; /* SI1 status register low 8 bits */ ++ u8 res7[0x1]; ++ u16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits */ ++ u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */ ++ u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */ ++ u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */ ++ u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */ ++ u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */ ++ u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */ ++ u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */ ++ u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */ ++ u8 res8[0x8]; ++ u32 siml1; /* SI1 multiframe limit register */ ++ u8 siedm1; /* SI1 extended diagnostic mode register */ ++ u8 res9[0xBB]; ++} __attribute__ ((packed)) si1_t; ++ ++/* SI Routing Tables ++*/ ++typedef struct sir { ++ u8 tx[0x400]; ++ u8 rx[0x400]; ++ u8 res0[0x800]; ++} __attribute__ ((packed)) sir_t; ++ ++/* USB Controller. ++*/ ++typedef struct usb_ctlr { ++ u8 usb_usmod; ++ u8 usb_usadr; ++ u8 usb_uscom; ++ u8 res1[1]; ++ u16 usb_usep1; ++ u16 usb_usep2; ++ u16 usb_usep3; ++ u16 usb_usep4; ++ u8 res2[4]; ++ u16 usb_usber; ++ u8 res3[2]; ++ u16 usb_usbmr; ++ u8 res4[1]; ++ u8 usb_usbs; ++ u16 usb_ussft; ++ u8 res5[2]; ++ u16 usb_usfrn; ++ u8 res6[0x22]; ++} __attribute__ ((packed)) usb_t; ++ ++/* MCC ++*/ ++typedef struct mcc { ++ u32 mcce; /* MCC event register */ ++ u32 mccm; /* MCC mask register */ ++ u32 mccf; /* MCC configuration register */ ++ u32 merl; /* MCC emergency request level register */ ++ u8 res0[0xF0]; ++} __attribute__ ((packed)) mcc_t; ++ ++/* QE UCC Slow ++*/ ++typedef struct ucc_slow { ++ u32 gumr_l; /* UCCx general mode register (low) */ ++ u32 gumr_h; /* UCCx general mode register (high) */ ++ u16 upsmr; /* UCCx protocol-specific mode register */ ++ u8 res0[0x2]; ++ u16 utodr; /* UCCx transmit on demand register */ ++ u16 udsr; /* UCCx data synchronization register */ ++ u16 ucce; /* UCCx event register */ ++ u8 res1[0x2]; ++ u16 uccm; /* UCCx mask register */ ++ u8 res2[0x1]; ++ u8 uccs; /* UCCx status register */ ++ u8 res3[0x24]; ++ u16 utpt; ++ u8 guemr; /* UCC general extended mode register */ ++ u8 res4[0x200 - 0x091]; ++} __attribute__ ((packed)) ucc_slow_t; ++ ++typedef struct ucc_ethernet { ++ u32 maccfg1; /* mac configuration reg. 1 */ ++ u32 maccfg2; /* mac configuration reg. 2 */ ++ u32 ipgifg; /* interframe gap reg. */ ++ u32 hafdup; /* half-duplex reg. */ ++ u8 res1[0x10]; ++ u32 miimcfg; /* MII management configuration reg */ ++ u32 miimcom; /* MII management command reg */ ++ u32 miimadd; /* MII management address reg */ ++ u32 miimcon; /* MII management control reg */ ++ u32 miimstat; /* MII management status reg */ ++ u32 miimind; /* MII management indication reg */ ++ u32 ifctl; /* interface control reg */ ++ u32 ifstat; /* interface statux reg */ ++ u32 macstnaddr1; /* mac station address part 1 reg */ ++ u32 macstnaddr2; /* mac station address part 2 reg */ ++ u8 res2[0x8]; ++ u32 uempr; /* UCC Ethernet Mac parameter reg */ ++ u32 utbipar; /* UCC tbi address reg */ ++ u16 uescr; /* UCC Ethernet statistics control reg */ ++ u8 res3[0x180 - 0x15A]; ++ u32 tx64; /* Total number of frames (including bad ++ * frames) transmitted that were exactly ++ * of the minimal length (64 for un tagged, ++ * 68 for tagged, or with length exactly ++ * equal to the parameter MINLength */ ++ u32 tx127; /* Total number of frames (including bad ++ * frames) transmitted that were between ++ * MINLength (Including FCS length==4) ++ * and 127 octets */ ++ u32 tx255; /* Total number of frames (including bad ++ * frames) transmitted that were between ++ * 128 (Including FCS length==4) and 255 ++ * octets */ ++ u32 rx64; /* Total number of frames received including ++ * bad frames that were exactly of the ++ * mninimal length (64 bytes) */ ++ u32 rx127; /* Total number of frames (including bad ++ * frames) received that were between ++ * MINLength (Including FCS length==4) ++ * and 127 octets */ ++ u32 rx255; /* Total number of frames (including ++ * bad frames) received that were between ++ * 128 (Including FCS length==4) and 255 ++ * octets */ ++ u32 txok; /* Total number of octets residing in frames ++ * that where involved in succesfull ++ * transmission */ ++ u16 txcf; /* Total number of PAUSE control frames ++ * transmitted by this MAC */ ++ u8 res4[0x2]; ++ u32 tmca; /* Total number of frames that were transmitted ++ * succesfully with the group address bit set ++ * that are not broadcast frames */ ++ u32 tbca; /* Total number of frames transmitted ++ * succesfully that had destination address ++ * field equal to the broadcast address */ ++ u32 rxfok; /* Total number of frames received OK */ ++ u32 rxbok; /* Total number of octets received OK */ ++ u32 rbyt; /* Total number of octets received including ++ * octets in bad frames. Must be implemented ++ * in HW because it includes octets in frames ++ * that never even reach the UCC */ ++ u32 rmca; /* Total number of frames that were received ++ * succesfully with the group address bit set ++ * that are not broadcast frames */ ++ u32 rbca; /* Total number of frames received succesfully ++ * that had destination address equal to the ++ * broadcast address */ ++ u32 scar; /* Statistics carry register */ ++ u32 scam; /* Statistics caryy mask register */ ++ u8 res5[0x200 - 0x1c4]; ++} __attribute__ ((packed)) uec_t; ++ ++/* QE UCC Fast ++*/ ++typedef struct ucc_fast { ++ u32 gumr; /* UCCx general mode register */ ++ u32 upsmr; /* UCCx protocol-specific mode register */ ++ u16 utodr; /* UCCx transmit on demand register */ ++ u8 res0[0x2]; ++ u16 udsr; /* UCCx data synchronization register */ ++ u8 res1[0x2]; ++ u32 ucce; /* UCCx event register */ ++ u32 uccm; /* UCCx mask register. */ ++ u8 uccs; /* UCCx status register */ ++ u8 res2[0x7]; ++ u32 urfb; /* UCC receive FIFO base */ ++ u16 urfs; /* UCC receive FIFO size */ ++ u8 res3[0x2]; ++ u16 urfet; /* UCC receive FIFO emergency threshold */ ++ u16 urfset; /* UCC receive FIFO special emergency ++ * threshold */ ++ u32 utfb; /* UCC transmit FIFO base */ ++ u16 utfs; /* UCC transmit FIFO size */ ++ u8 res4[0x2]; ++ u16 utfet; /* UCC transmit FIFO emergency threshold */ ++ u8 res5[0x2]; ++ u16 utftt; /* UCC transmit FIFO transmit threshold */ ++ u8 res6[0x2]; ++ u16 utpt; /* UCC transmit polling timer */ ++ u8 res7[0x2]; ++ u32 urtry; /* UCC retry counter register */ ++ u8 res8[0x4C]; ++ u8 guemr; /* UCC general extended mode register */ ++ u8 res9[0x100 - 0x091]; ++ uec_t ucc_eth; ++} __attribute__ ((packed)) ucc_fast_t; ++ ++/* QE UCC ++*/ ++typedef struct ucc_common { ++ u8 res1[0x90]; ++ u8 guemr; ++ u8 res2[0x200 - 0x091]; ++} __attribute__ ((packed)) ucc_common_t; ++ ++typedef struct ucc { ++ union { ++ ucc_slow_t slow; ++ ucc_fast_t fast; ++ ucc_common_t common; ++ }; ++} __attribute__ ((packed)) ucc_t; ++ ++/* MultiPHY UTOPIA POS Controllers (UPC) ++*/ ++typedef struct upc { ++ u32 upgcr; /* UTOPIA/POS general configuration register */ ++ u32 uplpa; /* UTOPIA/POS last PHY address */ ++ u32 uphec; /* ATM HEC register */ ++ u32 upuc; /* UTOPIA/POS UCC configuration */ ++ u32 updc1; /* UTOPIA/POS device 1 configuration */ ++ u32 updc2; /* UTOPIA/POS device 2 configuration */ ++ u32 updc3; /* UTOPIA/POS device 3 configuration */ ++ u32 updc4; /* UTOPIA/POS device 4 configuration */ ++ u32 upstpa; /* UTOPIA/POS STPA threshold */ ++ u8 res0[0xC]; ++ u32 updrs1_h; /* UTOPIA/POS device 1 rate select */ ++ u32 updrs1_l; /* UTOPIA/POS device 1 rate select */ ++ u32 updrs2_h; /* UTOPIA/POS device 2 rate select */ ++ u32 updrs2_l; /* UTOPIA/POS device 2 rate select */ ++ u32 updrs3_h; /* UTOPIA/POS device 3 rate select */ ++ u32 updrs3_l; /* UTOPIA/POS device 3 rate select */ ++ u32 updrs4_h; /* UTOPIA/POS device 4 rate select */ ++ u32 updrs4_l; /* UTOPIA/POS device 4 rate select */ ++ u32 updrp1; /* UTOPIA/POS device 1 receive priority low */ ++ u32 updrp2; /* UTOPIA/POS device 2 receive priority low */ ++ u32 updrp3; /* UTOPIA/POS device 3 receive priority low */ ++ u32 updrp4; /* UTOPIA/POS device 4 receive priority low */ ++ u32 upde1; /* UTOPIA/POS device 1 event */ ++ u32 upde2; /* UTOPIA/POS device 2 event */ ++ u32 upde3; /* UTOPIA/POS device 3 event */ ++ u32 upde4; /* UTOPIA/POS device 4 event */ ++ u16 uprp1; ++ u16 uprp2; ++ u16 uprp3; ++ u16 uprp4; ++ u8 res1[0x8]; ++ u16 uptirr1_0; /* Device 1 transmit internal rate 0 */ ++ u16 uptirr1_1; /* Device 1 transmit internal rate 1 */ ++ u16 uptirr1_2; /* Device 1 transmit internal rate 2 */ ++ u16 uptirr1_3; /* Device 1 transmit internal rate 3 */ ++ u16 uptirr2_0; /* Device 2 transmit internal rate 0 */ ++ u16 uptirr2_1; /* Device 2 transmit internal rate 1 */ ++ u16 uptirr2_2; /* Device 2 transmit internal rate 2 */ ++ u16 uptirr2_3; /* Device 2 transmit internal rate 3 */ ++ u16 uptirr3_0; /* Device 3 transmit internal rate 0 */ ++ u16 uptirr3_1; /* Device 3 transmit internal rate 1 */ ++ u16 uptirr3_2; /* Device 3 transmit internal rate 2 */ ++ u16 uptirr3_3; /* Device 3 transmit internal rate 3 */ ++ u16 uptirr4_0; /* Device 4 transmit internal rate 0 */ ++ u16 uptirr4_1; /* Device 4 transmit internal rate 1 */ ++ u16 uptirr4_2; /* Device 4 transmit internal rate 2 */ ++ u16 uptirr4_3; /* Device 4 transmit internal rate 3 */ ++ u32 uper1; /* Device 1 port enable register */ ++ u32 uper2; /* Device 2 port enable register */ ++ u32 uper3; /* Device 3 port enable register */ ++ u32 uper4; /* Device 4 port enable register */ ++ u8 res2[0x150]; ++} __attribute__ ((packed)) upc_t; ++ ++/* SDMA ++*/ ++typedef struct sdma { ++ u32 sdsr; /* Serial DMA status register */ ++ u32 sdmr; /* Serial DMA mode register */ ++ u32 sdtr1; /* SDMA system bus threshold register */ ++ u32 sdtr2; /* SDMA secondary bus threshold register */ ++ u32 sdhy1; /* SDMA system bus hysteresis register */ ++ u32 sdhy2; /* SDMA secondary bus hysteresis register */ ++ u32 sdta1; /* SDMA system bus address register */ ++ u32 sdta2; /* SDMA secondary bus address register */ ++ u32 sdtm1; /* SDMA system bus MSNUM register */ ++ u32 sdtm2; /* SDMA secondary bus MSNUM register */ ++ u8 res0[0x10]; ++ u32 sdaqr; /* SDMA address bus qualify register */ ++ u32 sdaqmr; /* SDMA address bus qualify mask register */ ++ u8 res1[0x4]; ++ u32 sdwbcr; /* SDMA CAM entries base register */ ++ u8 res2[0x38]; ++} __attribute__ ((packed)) sdma_t; ++ ++/* Debug Space ++*/ ++typedef struct dbg { ++ u32 bpdcr; /* Breakpoint debug command register */ ++ u32 bpdsr; /* Breakpoint debug status register */ ++ u32 bpdmr; /* Breakpoint debug mask register */ ++ u32 bprmrr0; /* Breakpoint request mode risc register 0 */ ++ u32 bprmrr1; /* Breakpoint request mode risc register 1 */ ++ u8 res0[0x8]; ++ u32 bprmtr0; /* Breakpoint request mode trb register 0 */ ++ u32 bprmtr1; /* Breakpoint request mode trb register 1 */ ++ u8 res1[0x8]; ++ u32 bprmir; /* Breakpoint request mode immediate register */ ++ u32 bprmsr; /* Breakpoint request mode serial register */ ++ u32 bpemr; /* Breakpoint exit mode register */ ++ u8 res2[0x48]; ++} __attribute__ ((packed)) dbg_t; ++ ++/* RISC Special Registers (Trap and Breakpoint) ++*/ ++typedef struct rsp { ++ u8 fixme[0x100]; ++} __attribute__ ((packed)) rsp_t; ++ ++typedef struct qe_immap { ++ qe_iram_t iram; /* I-RAM */ ++ qe_ic_t ic; /* Interrupt Controller */ ++ cp_qe_t cp; /* Communications Processor */ ++ qe_mux_t qmx; /* QE Multiplexer */ ++ qe_timers_t qet; /* QE Timers */ ++ spi_t spi[0x2]; /* spi */ ++ mcc_t mcc; /* mcc */ ++ qe_brg_t brg; /* brg */ ++ usb_t usb; /* USB */ ++ si1_t si1; /* SI */ ++ u8 res11[0x800]; ++ sir_t sir; /* SI Routing Tables */ ++ ucc_t ucc1; /* ucc1 */ ++ ucc_t ucc3; /* ucc3 */ ++ ucc_t ucc5; /* ucc5 */ ++ ucc_t ucc7; /* ucc7 */ ++ u8 res12[0x600]; ++ upc_t upc1; /* MultiPHY UTOPIA POS Controller 1 */ ++ ucc_t ucc2; /* ucc2 */ ++ ucc_t ucc4; /* ucc4 */ ++ ucc_t ucc6; /* ucc6 */ ++ ucc_t ucc8; /* ucc8 */ ++ u8 res13[0x600]; ++ upc_t upc2; /* MultiPHY UTOPIA POS Controller 2 */ ++ sdma_t sdma; /* SDMA */ ++ dbg_t dbg; /* Debug Space */ ++ rsp_t rsp[0x2]; /* RISC Special Registers ++ * (Trap and Breakpoint) */ ++ u8 res14[0x300]; ++ u8 res15[0x3A00]; ++ u8 res16[0x8000]; /* 0x108000 - 0x110000 */ ++ u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */ ++ u8 res17[0x24000]; /* 0x11C000 - 0x140000 */ ++ u8 res18[0xC0000]; /* 0x140000 - 0x200000 */ ++} __attribute__ ((packed)) qe_map_t; ++ ++extern qe_map_t *qe_immr; ++ ++#endif /* __IMMAP_QE_H__ */ +diff -Naupr u-boot-1.1.6/include/asm-ppc/processor.h u-boot-1.1.6-fsl-1/include/asm-ppc/processor.h +--- u-boot-1.1.6/include/asm-ppc/processor.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/asm-ppc/processor.h 2006-12-06 10:33:49.000000000 -0600 +@@ -749,6 +749,7 @@ + #define PVR_405EP_RB 0x51210950 + #define PVR_440SP_RA 0x53221850 + #define PVR_440SP_RB 0x53221891 ++#define PVR_440SP_RC 0x53221892 + #define PVR_440SPe_RA 0x53421890 + #define PVR_440SPe_RB 0x53421891 + #define PVR_601 0x00010000 +diff -Naupr u-boot-1.1.6/include/common.h u-boot-1.1.6-fsl-1/include/common.h +--- u-boot-1.1.6/include/common.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/common.h 2006-11-30 12:34:13.000000000 -0600 +@@ -270,7 +270,7 @@ int misc_init_r (void); + void jumptable_init(void); + + /* common/memsize.c */ +-int get_ram_size (volatile long *, long); ++long get_ram_size (volatile long *, long); + + /* $(BOARD)/$(BOARD).c */ + void reset_phy (void); +@@ -402,6 +402,11 @@ void ppcSync(void); + void ppcDcbz(unsigned long value); + #endif + ++#if defined (CONFIG_MPC83XX) ++void ppcDWload(unsigned int *addr, unsigned int *ret); ++void ppcDWstore(unsigned int *addr, unsigned int *value); ++#endif ++ + /* $(CPU)/cpu.c */ + int checkcpu (void); + int checkicache (void); +diff -Naupr u-boot-1.1.6/include/configs/alpr.h u-boot-1.1.6-fsl-1/include/configs/alpr.h +--- u-boot-1.1.6/include/configs/alpr.h 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/configs/alpr.h 2006-11-30 12:34:13.000000000 -0600 +@@ -0,0 +1,346 @@ ++/* ++ * (C) Copyright 2006 ++ * Stefan Roese, DENX Software Engineering, sr@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++/*----------------------------------------------------------------------- ++ * High Level Configuration Options ++ *----------------------------------------------------------------------*/ ++#define CONFIG_ALPR 1 /* Board is ebony */ ++#define CONFIG_440GX 1 /* Specifc GX support */ ++#define CONFIG_4xx 1 /* ... PPC4xx family */ ++#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ ++#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */ ++#undef CFG_DRAM_TEST /* Disable-takes long time! */ ++#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ ++ ++/*----------------------------------------------------------------------- ++ * Base addresses -- Note these are effective addresses where the ++ * actual resources get mapped (not physical addresses) ++ *----------------------------------------------------------------------*/ ++#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ ++#define CFG_FLASH_BASE 0xffe00000 /* start of FLASH */ ++#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ ++#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ ++#define CFG_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */ ++#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ ++#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ ++#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ ++#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 ++#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 ++#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 ++ ++ ++#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) ++#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) ++ ++/*----------------------------------------------------------------------- ++ * Initial RAM & stack pointer (placed in internal SRAM) ++ *----------------------------------------------------------------------*/ ++#define CFG_TEMP_STACK_OCM 1 ++#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE ++#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ ++#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ ++#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ ++ ++#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) ++#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) ++#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR ++ ++#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ ++#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ ++ ++/*----------------------------------------------------------------------- ++ * Serial Port ++ *----------------------------------------------------------------------*/ ++#undef CFG_EXT_SERIAL_CLOCK ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ ++ ++#define CFG_BAUDRATE_TABLE \ ++ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} ++ ++/*----------------------------------------------------------------------- ++ * FLASH related ++ *----------------------------------------------------------------------*/ ++#define CFG_FLASH_CFI 1 /* The flash is CFI compatible */ ++#define CFG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */ ++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ ++#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ ++#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ ++#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ ++#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ ++ ++#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ ++ ++#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ ++#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) ++#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ ++ ++/* Address and size of Redundant Environment Sector */ ++#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) ++#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) ++ ++/*----------------------------------------------------------------------- ++ * DDR SDRAM ++ *----------------------------------------------------------------------*/ ++#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ ++#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */ ++#undef CONFIG_SDRAM_ECC /* enable ECC support */ ++#define CFG_SDRAM_TABLE { \ ++ {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \ ++ {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */ ++ ++/*----------------------------------------------------------------------- ++ * I2C ++ *----------------------------------------------------------------------*/ ++#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ ++#undef CONFIG_SOFT_I2C /* I2C bit-banged */ ++#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ ++#define CFG_I2C_SLAVE 0x7F ++#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ ++ ++/*----------------------------------------------------------------------- ++ * I2C EEPROM (PCF8594C) ++ *----------------------------------------------------------------------*/ ++#define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */ ++#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ ++/* mask of address bits that overflow into the "EEPROM chip address" */ ++#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 ++#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */ ++ /* 8 byte page write mode using */ ++ /* last 3 bits of the address */ ++#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */ ++#define CFG_EEPROM_PAGE_WRITE_ENABLE ++ ++#define CONFIG_PREBOOT "echo;" \ ++ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ ++ "echo" ++ ++#undef CONFIG_BOOTARGS ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "netdev=eth3\0" \ ++ "hostname=alpr\0" \ ++ "nfsargs=setenv bootargs root=/dev/nfs rw " \ ++ "nfsroot=${serverip}:${rootpath}\0" \ ++ "ramargs=setenv bootargs root=/dev/ram rw\0" \ ++ "addip=setenv bootargs ${bootargs} " \ ++ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ++ ":${hostname}:${netdev}:off panic=1\0" \ ++ "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \ ++ "mem=193M\0" \ ++ "flash_nfs=run nfsargs addip addtty;" \ ++ "bootm ${kernel_addr}\0" \ ++ "flash_self=run ramargs addip addtty;" \ ++ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ ++ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ ++ "bootm\0" \ ++ "rootpath=/opt/projects/alpr/nfs_root\0" \ ++ "bootfile=/alpr/uImage\0" \ ++ "kernel_addr=fff00000\0" \ ++ "ramdisk_addr=fff10000\0" \ ++ "load=tftp 100000 /alpr/u-boot/u-boot.bin\0" \ ++ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ ++ "cp.b 100000 fffc0000 40000;" \ ++ "setenv filesize;saveenv\0" \ ++ "upd=run load;run update\0" \ ++ "" ++#define CONFIG_BOOTCOMMAND "run flash_self" ++ ++#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ ++ ++#define CONFIG_BAUDRATE 115200 ++ ++#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ ++#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ ++ ++#define CONFIG_MII 1 /* MII PHY management */ ++#define CONFIG_NET_MULTI 1 ++#define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */ ++#define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */ ++#define CONFIG_PHY2_ADDR 0x01 /* PHY address for EMAC2 */ ++#define CONFIG_PHY3_ADDR 0x02 /* PHY address for EMAC3 */ ++#define CONFIG_HAS_ETH0 ++#define CONFIG_HAS_ETH1 ++#define CONFIG_HAS_ETH2 ++#define CONFIG_HAS_ETH3 ++#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ ++#define CONFIG_M88E1111_PHY 1 /* needed for PHY specific setup*/ ++#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ ++#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ ++ ++#define CONFIG_NETCONSOLE /* include NetConsole support */ ++ ++#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ ++ CFG_CMD_ASKENV | \ ++ CFG_CMD_DHCP | \ ++ CFG_CMD_DIAG | \ ++ CFG_CMD_EEPROM | \ ++ CFG_CMD_ELF | \ ++ CFG_CMD_I2C | \ ++ CFG_CMD_IRQ | \ ++ CFG_CMD_MII | \ ++ CFG_CMD_NET | \ ++ CFG_CMD_NFS | \ ++ CFG_CMD_PCI | \ ++ CFG_CMD_PING | \ ++ CFG_CMD_FPGA | \ ++ CFG_CMD_NAND | \ ++ CFG_CMD_REGINFO) ++ ++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ ++#include ++ ++#undef CONFIG_WATCHDOG /* watchdog disabled */ ++ ++/* ++ * Miscellaneous configurable options ++ */ ++#define CFG_LONGHELP /* undef to save memory */ ++#define CFG_PROMPT "=> " /* Monitor Command Prompt */ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ ++#else ++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ ++#endif ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ ++#define CFG_MAXARGS 16 /* max number of command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ ++ ++#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ ++#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ ++ ++#define CFG_LOAD_ADDR 0x100000 /* default load address */ ++#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ ++ ++#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ ++ ++#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ ++#define CONFIG_LOOPW 1 /* enable loopw command */ ++#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ ++#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ ++#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ ++ ++#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ ++ ++/*----------------------------------------------------------------------- ++ * PCI stuff ++ *----------------------------------------------------------------------- ++ */ ++/* General PCI */ ++#define CONFIG_PCI /* include pci support */ ++#define CONFIG_PCI_PNP /* do pci plug-and-play */ ++#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ ++#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ ++#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/ ++ ++/* Board-specific PCI */ ++#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ ++#define CFG_PCI_TARGET_INIT /* let board init pci target */ ++#define CFG_PCI_MASTER_INIT ++ ++#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ ++#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ ++ ++/*----------------------------------------------------------------------- ++ * FPGA stuff ++ *-----------------------------------------------------------------------*/ ++#define CONFIG_FPGA CFG_ALTERA_CYCLON2 ++#define CFG_FPGA_CHECK_CTRLC ++#define CFG_FPGA_PROG_FEEDBACK ++#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in ++ Reihe geschaltet -> sollte gehen, ++ aufpassen mit Datasize ist jetzt ++ halt doppelt so gross ... Seite 306 ++ ist das mit den multiple Device in PS ++ Mode erklaert ...*/ ++ ++/* FPGA program pin configuration */ ++#define CFG_GPIO_CLK 18 /* FPGA clk pin (cpu output) */ ++#define CFG_GPIO_DATA 19 /* FPGA data pin (cpu output) */ ++#define CFG_GPIO_STATUS 20 /* FPGA status pin (cpu input) */ ++#define CFG_GPIO_CONFIG 21 /* FPGA CONFIG pin (cpu output) */ ++#define CFG_GPIO_CON_DON 22 /* FPGA CONFIG_DONE pin (cpu input) */ ++ ++#define CFG_GPIO_SEL_DPR 14 /* cpu output */ ++#define CFG_GPIO_SEL_AVR 15 /* cpu output */ ++#define CFG_GPIO_PROG_EN 23 /* cpu output */ ++ ++/*----------------------------------------------------------------------- ++ * Definitions for GPIO setup ++ *-----------------------------------------------------------------------*/ ++#define CFG_GPIO_EREADY (0x80000000 >> 26) ++#define CFG_GPIO_REV0 (0x80000000 >> 14) ++#define CFG_GPIO_REV1 (0x80000000 >> 15) ++ ++/*----------------------------------------------------------------------- ++ * NAND-FLASH stuff ++ *-----------------------------------------------------------------------*/ ++#define CFG_MAX_NAND_DEVICE 4 ++#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE ++#define CFG_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */ ++#define CFG_NAND_BASE_LIST { CFG_NAND_BASE + 0, CFG_NAND_BASE + 2, \ ++ CFG_NAND_BASE + 4, CFG_NAND_BASE + 6 } ++#define CFG_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */ ++ ++/*----------------------------------------------------------------------- ++ * External Bus Controller (EBC) Setup ++ *----------------------------------------------------------------------*/ ++#define CFG_FLASH CFG_FLASH_BASE ++ ++/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ ++#define CFG_EBC_PB0AP 0x92015480 ++#define CFG_EBC_PB0CR (CFG_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */ ++ ++/* Memory Bank 1 (NAND-FLASH) initialization */ ++#define CFG_EBC_PB1AP 0x01840380 /* TWT=3 */ ++#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */ ++ ++/* ++ * For booting Linux, the board info and command line data ++ * have to be in the first 8 MB of memory, since this is ++ * the maximum mapped by the Linux kernel during initialization. ++ */ ++#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ ++/*----------------------------------------------------------------------- ++ * Cache Configuration ++ */ ++#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ ++#define CFG_CACHELINE_SIZE 32 /* ... */ ++#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ ++ ++/* ++ * Internal Definitions ++ * ++ * Boot Flags ++ */ ++#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ ++#define BOOTFLAG_WARM 0x02 /* Software reboot */ ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ ++#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ ++#endif ++#endif /* __CONFIG_H */ +diff -Naupr u-boot-1.1.6/include/configs/IceCube.h u-boot-1.1.6-fsl-1/include/configs/IceCube.h +--- u-boot-1.1.6/include/configs/IceCube.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/configs/IceCube.h 2006-12-06 10:33:49.000000000 -0600 +@@ -172,6 +172,19 @@ + #undef CFG_IPBSPEED_133 /* define for 133MHz speed */ + #endif + #endif /* CONFIG_MPC5200 */ ++ ++/* pass open firmware flat tree */ ++#define CONFIG_OF_FLAT_TREE 1 ++#define CONFIG_OF_BOARD_SETUP 1 ++ ++/* maximum size of the flat tree (8K) */ ++#define OF_FLAT_TREE_MAX_SIZE 8192 ++ ++#define OF_CPU "PowerPC,5200@0" ++#define OF_SOC "soc5200@f0000000" ++#define OF_TBCLK (bd->bi_busfreq / 8) ++#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" ++ + /* + * I2C configuration + */ +diff -Naupr u-boot-1.1.6/include/configs/MPC8349EMDS.h u-boot-1.1.6-fsl-1/include/configs/MPC8349EMDS.h +--- u-boot-1.1.6/include/configs/MPC8349EMDS.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/configs/MPC8349EMDS.h 2006-11-10 11:24:30.000000000 -0600 +@@ -36,6 +36,7 @@ + */ + #define CONFIG_E300 1 /* E300 Family */ + #define CONFIG_MPC83XX 1 /* MPC83XX family */ ++#define CONFIG_MPC834X 1 /* MPC834X family */ + #define CONFIG_MPC8349 1 /* MPC8349 specific */ + #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ + +@@ -59,9 +60,20 @@ + #endif + #endif + ++#define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK)) ++#define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */ ++#define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */ ++#define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */ ++#define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */ ++#define CFG_SCCR_VAL ( CFG_SCCR_INIT \ ++ | CFG_SCCR_TSEC1CM \ ++ | CFG_SCCR_TSEC2CM \ ++ | CFG_SCCR_ENCCM \ ++ | CFG_SCCR_USBCM ) ++ + #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ + +-#define CFG_IMMRBAR 0xE0000000 ++#define CFG_IMMR 0xE0000000 + + #undef CFG_DRAM_TEST /* memory test, takes time */ + #define CFG_MEMTEST_START 0x00000000 /* memtest region */ +@@ -299,8 +311,8 @@ + #define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +-#define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500) +-#define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600) ++#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) ++#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) + + /* Use the HUSH parser */ + #define CFG_HUSH_PARSER +@@ -308,20 +320,35 @@ + #define CFG_PROMPT_HUSH_PS2 "> " + #endif + ++/* pass open firmware flat tree */ ++#define CONFIG_OF_FLAT_TREE 1 ++#define CONFIG_OF_BOARD_SETUP 1 ++ ++/* maximum size of the flat tree (8K) */ ++#define OF_FLAT_TREE_MAX_SIZE 8192 ++ ++#define OF_CPU "PowerPC,8349@0" ++#define OF_SOC "soc8349@e0000000" ++#define OF_TBCLK (bd->bi_busfreq / 4) ++#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" ++ + /* I2C */ + #define CONFIG_HARD_I2C /* I2C with hardware support*/ + #undef CONFIG_SOFT_I2C /* I2C bit-banged */ ++#define CONFIG_FSL_I2C ++#define CONFIG_I2C_MULTI_BUS ++#define CONFIG_I2C_CMD_TREE + #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ + #define CFG_I2C_SLAVE 0x7F +-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ ++#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ + #define CFG_I2C_OFFSET 0x3000 + #define CFG_I2C2_OFFSET 0x3100 + + /* TSEC */ + #define CFG_TSEC1_OFFSET 0x24000 +-#define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET) ++#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) + #define CFG_TSEC2_OFFSET 0x25000 +-#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET) ++#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) + + /* USB */ + #define CFG_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ +@@ -615,8 +642,8 @@ + #endif + + /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ +-#define CFG_IBAT5L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +-#define CFG_IBAT5U (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP) ++#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) ++#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) + + /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ + #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +@@ -666,11 +693,11 @@ + #define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21 + #endif + +-#define CONFIG_IPADDR 192.168.205.5 ++#define CONFIG_IPADDR 192.168.1.253 + + #define CONFIG_HOSTNAME mpc8349emds +-#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx +-#define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage ++#define CONFIG_ROOTPATH /nfsroot/rootfs ++#define CONFIG_BOOTFILE uImage + + #define CONFIG_SERVERIP 192.168.1.1 + #define CONFIG_GATEWAYIP 192.168.1.1 +@@ -703,14 +730,31 @@ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ +- "rootpath=/opt/eldk/ppc_6xx\0" \ +- "bootfile=/tftpboot/mpc8349emds/uImage\0" \ + "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ + "update=protect off fe000000 fe03ffff; " \ + "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \ + "upd=run load;run update\0" \ ++ "fdtaddr=400000\0" \ ++ "fdtfile=mpc8349emds.dtb\0" \ + "" + ++#define CONFIG_NFSBOOTCOMMAND \ ++ "setenv bootargs root=/dev/nfs rw " \ ++ "nfsroot=$serverip:$rootpath " \ ++ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ ++ "console=$consoledev,$baudrate $othbootargs;" \ ++ "tftp $loadaddr $bootfile;" \ ++ "tftp $fdtaddr $fdtfile;" \ ++ "bootm $loadaddr - $fdtaddr" ++ ++#define CONFIG_RAMBOOTCOMMAND \ ++ "setenv bootargs root=/dev/ram rw " \ ++ "console=$consoledev,$baudrate $othbootargs;" \ ++ "tftp $ramdiskaddr $ramdiskfile;" \ ++ "tftp $loadaddr $bootfile;" \ ++ "tftp $fdtaddr $fdtfile;" \ ++ "bootm $loadaddr $ramdiskaddr $fdtaddr" ++ + #define CONFIG_BOOTCOMMAND "run flash_self" + + #endif /* __CONFIG_H */ +diff -Naupr u-boot-1.1.6/include/configs/MPC8349ITX.h u-boot-1.1.6-fsl-1/include/configs/MPC8349ITX.h +--- u-boot-1.1.6/include/configs/MPC8349ITX.h 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/configs/MPC8349ITX.h 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,804 @@ ++/* ++ * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* ++ MPC8349E-mITX board configuration file ++ ++ Memory map: ++ ++ 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) ++ 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) ++ 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) ++ 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) ++ 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) ++ 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) ++ 0xF000_0000-0xF000_FFFF Compact Flash ++ 0xF001_0000-0xF001_FFFF Local bus expansion slot ++ 0xF800_0000-0xF801_FFFF GBE L2 Switch VSC7385 ++ 0xFF00_0000-0xFF7F_FFFF Alternative bank of Flash memory (8MB) ++ 0xFF80_0000-0xFFFF_FFFF Boot Flash (8 MB) ++ ++ I2C address list: ++ Align. Board ++ Bus Addr Part No. Description Length Location ++ ---------------------------------------------------------------- ++ I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 ++ ++ I2C1 0x20 PCF8574 I2C Expander 0 U8 ++ I2C1 0x21 PCF8574 I2C Expander 0 U10 ++ I2C1 0x38 PCF8574A I2C Expander 0 U8 ++ I2C1 0x39 PCF8574A I2C Expander 0 U10 ++ I2C1 0x51 (DDR) DDR EEPROM 1 U1 ++ I2C1 0x68 DS1339 RTC 1 U68 ++ ++ Note that a given board has *either* a pair of 8574s or a pair of 8574As. ++*/ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#undef DEBUG ++ ++/* ++ * High Level Configuration Options ++ */ ++#define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ ++#define CONFIG_MPC8349 /* MPC8349 specific */ ++ ++#define CONFIG_PCI ++ ++#define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ ++#define CONFIG_RTC_DS1337 ++ ++/* I2C */ ++#define CONFIG_HARD_I2C ++ ++#ifdef CONFIG_HARD_I2C ++ ++#define CONFIG_MISC_INIT_F ++#define CONFIG_MISC_INIT_R ++ ++#define CONFIG_FSL_I2C ++#define CONFIG_I2C_MULTI_BUS ++#define CONFIG_I2C_CMD_TREE ++#define CFG_I2C_OFFSET 0x3000 ++#define CFG_I2C2_OFFSET 0x3100 ++#define CFG_SPD_BUS_NUM 1 /* The I2C bus for SPD */ ++ ++#define CFG_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ ++#define CFG_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ ++#define CFG_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ ++#define CFG_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ ++#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ ++#define CFG_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ ++#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ ++ ++#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ ++#define CFG_I2C_SLAVE 0x7F ++ ++/* Don't probe these addresses: */ ++#define CFG_I2C_NOPROBES {{1, CFG_I2C_8574_ADDR1}, \ ++ {1, CFG_I2C_8574_ADDR2}, \ ++ {1, CFG_I2C_8574A_ADDR1}, \ ++ {1, CFG_I2C_8574A_ADDR2}} ++/* Bit definitions for the 8574[A] I2C expander */ ++#define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ ++#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ ++#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ ++#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ ++#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ ++ ++#undef CONFIG_SOFT_I2C ++ ++#endif ++ ++#define CONFIG_TSEC_ENET /* tsec ethernet support */ ++#define CONFIG_ENV_OVERWRITE ++ ++#define PCI_66M ++#ifdef PCI_66M ++#define CONFIG_83XX_CLKIN 66666666 /* in Hz */ ++#else ++#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ ++#endif ++ ++#ifndef CONFIG_SYS_CLK_FREQ ++#ifdef PCI_66M ++#define CONFIG_SYS_CLK_FREQ 66666666 ++#else ++#define CONFIG_SYS_CLK_FREQ 33333333 ++#endif ++#endif ++ ++#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ ++ ++#undef CFG_DRAM_TEST /* memory test, takes time */ ++#define CFG_MEMTEST_START 0x00003000 /* memtest region */ ++#define CFG_MEMTEST_END 0x07100000 /* only has 128M */ ++ ++/* ++ * DDR Setup ++ */ ++#undef CONFIG_DDR_ECC /* only for ECC DDR module */ ++#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ ++#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ ++ ++/* ++ * 32-bit data path mode. ++ * ++ * Please note that using this mode for devices with the real density of 64-bit ++ * effectively reduces the amount of available memory due to the effect of ++ * wrapping around while translating address to row/columns, for example in the ++ * 256MB module the upper 128MB get aliased with contents of the lower ++ * 128MB); normally this define should be used for devices with real 32-bit ++ * data path. ++ */ ++#undef CONFIG_DDR_32BIT ++ ++#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ ++#define CFG_SDRAM_BASE CFG_DDR_BASE ++#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE ++#undef CONFIG_DDR_2T_TIMING ++#define CFG_83XX_DDR_USES_CS0 ++ ++#ifndef CONFIG_SPD_EEPROM ++/* ++ * Manually set up DDR parameters ++ */ ++ #define CFG_DDR_SIZE 256 /* Mb */ ++ #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) ++ ++ #define CFG_DDR_TIMING_1 0x26242321 ++ #define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ ++#endif ++ ++/* FLASH on the Local Bus */ ++#define CFG_FLASH_CFI /* use the Common Flash Interface */ ++#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ ++#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ ++#define CFG_FLASH_SIZE 16 /* FLASH size in MB */ ++#define CFG_FLASH_EMPTY_INFO ++ ++#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) ++#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ ++ OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ ++ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) ++#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ ++#define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16Mb window bytes */ ++ ++/* VSC7385 on the Local Bus */ ++#define CFG_VSC7385_BASE 0xF8000000 /* start of VSC7385 */ ++ ++#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) ++#define CFG_OR1_PRELIM (0xFFFE0000 /* 128KB */ | \ ++ OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ ++ OR_GPCM_SETA | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) ++ ++#define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE /* Access window base at VSC7385 base */ ++#define CFG_LBLAWAR1_PRELIM 0x80000010 /* Access window size 128K */ ++ ++#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ ++#define CFG_MAX_FLASH_SECT 135 /* sectors per device */ ++ ++#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} ++ ++#undef CFG_FLASH_CHECKSUM ++#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ ++#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ ++ ++#define CFG_LED_BASE 0xF9000000 /* start of LED and Board ID */ ++#define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) ++#define CFG_OR2_PRELIM (0xFFE00000 /* 2MB */ | \ ++ OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | \ ++ OR_GPCM_SCY_9 | \ ++ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) ++ ++#ifdef CONFIG_COMPACT_FLASH ++ ++#define CFG_CF_BASE 0xF0000000 ++ ++#define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) ++#define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) ++ ++#define CFG_LBLAWBAR2_PRELIM CFG_CF_BASE /* Window base at flash base + LED & Board ID */ ++#define CFG_LBLAWAR2_PRELIM 0x8000000F /* 64K bytes */ ++ ++#undef CONFIG_IDE_RESET ++#undef CONFIG_IDE_PREINIT ++ ++#define CFG_IDE_MAXBUS 1 ++#define CFG_IDE_MAXDEVICE 1 ++ ++#define CFG_ATA_IDE0_OFFSET 0x0000 ++#define CFG_ATA_BASE_ADDR CFG_CF_BASE ++#define CFG_ATA_DATA_OFFSET 0x0000 ++#define CFG_ATA_REG_OFFSET 0 ++#define CFG_ATA_ALT_OFFSET 0x0200 ++#define CFG_ATA_STRIDE 2 ++ ++#define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ ++ ++#endif ++ ++#define CONFIG_DOS_PARTITION ++ ++#define CFG_MID_FLASH_JUMP 0x7F000000 ++#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ ++ ++ ++#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) ++#define CFG_RAMBOOT ++#else ++#undef CFG_RAMBOOT ++#endif ++ ++#define CONFIG_L1_INIT_RAM ++#define CFG_INIT_RAM_LOCK ++#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ ++#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ ++ ++#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ ++#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) ++#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET ++ ++#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ ++#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ ++ ++/* ++ * Local Bus LCRR and LBCR regs ++ * LCRR: DLL bypass, Clock divider is 4 ++ * External Local Bus rate is ++ * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV ++ */ ++#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) ++#define CFG_LBC_LBCR 0x00000000 ++ ++#undef CFG_LB_SDRAM /* if board has SRDAM on local bus */ ++ ++#ifdef CFG_LB_SDRAM ++/*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/ ++/* ++ * Base Register 2 and Option Register 2 configure SDRAM. ++ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. ++ * ++ * For BR2, need: ++ * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 ++ * port-size = 32-bits = BR2[19:20] = 11 ++ * no parity checking = BR2[21:22] = 00 ++ * SDRAM for MSEL = BR2[24:26] = 011 ++ * Valid = BR[31] = 1 ++ * ++ * 0 4 8 12 16 20 24 28 ++ * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 ++ */ ++ ++#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ ++#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ ++ ++#define CFG_LBLAWBAR2_PRELIM 0xF0000000 ++#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ ++ ++#define CFG_BR2_PRELIM (CFG_LBC_SDRAM_BASE | BR_PS_32 | BR_MS_SDRAM | BR_V) ++#define CFG_OR2_PRELIM (0xFC000000 /* 64 MB */ | \ ++ OR_SDRAM_XAM | \ ++ ((9 - 7) << OR_SDRAM_COLS_SHIFT) | \ ++ ((13 - 9) << OR_SDRAM_ROWS_SHIFT) | \ ++ OR_SDRAM_EAD) ++ ++#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ ++#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ ++ ++/* ++ * LSDMR masks ++ */ ++#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) ++#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) ++#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) ++#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) ++#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) ++#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) ++#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) ++#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) ++#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) ++#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) ++#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) ++#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) ++#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) ++#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) ++#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) ++#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) ++#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) ++#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) ++ ++#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) ++ ++#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ ++ | CFG_LBC_LSDMR_BSMA1516 \ ++ | CFG_LBC_LSDMR_RFCR8 \ ++ | CFG_LBC_LSDMR_PRETOACT6 \ ++ | CFG_LBC_LSDMR_ACTTORW3 \ ++ | CFG_LBC_LSDMR_BL8 \ ++ | CFG_LBC_LSDMR_WRC3 \ ++ | CFG_LBC_LSDMR_CL3 \ ++ ) ++ ++/* ++ * SDRAM Controller configuration sequence. ++ */ ++#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ ++ | CFG_LBC_LSDMR_OP_PCHALL) ++#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ ++ | CFG_LBC_LSDMR_OP_ARFRSH) ++#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ ++ | CFG_LBC_LSDMR_OP_ARFRSH) ++#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ ++ | CFG_LBC_LSDMR_OP_MRW) ++#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ ++ | CFG_LBC_LSDMR_OP_NORMAL) ++#endif ++ ++/* ++ * Serial Port ++ */ ++#define CONFIG_CONS_INDEX 1 ++#undef CONFIG_SERIAL_SOFTWARE_FIFO ++#define CFG_NS16550 ++#define CFG_NS16550_SERIAL ++#define CFG_NS16550_REG_SIZE 1 ++#define CFG_NS16550_CLK get_bus_freq(0) ++ ++#define CFG_BAUDRATE_TABLE \ ++ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} ++ ++#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) ++#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) ++ ++/* Use the HUSH parser */ ++#define CFG_HUSH_PARSER ++#ifdef CFG_HUSH_PARSER ++#define CFG_PROMPT_HUSH_PS2 "> " ++#endif ++ ++/* pass open firmware flat tree */ ++#define CONFIG_OF_FLAT_TREE 1 ++#define CONFIG_OF_BOARD_SETUP 1 ++ ++/* maximum size of the flat tree (8K) */ ++#define OF_FLAT_TREE_MAX_SIZE 8192 ++ ++#define OF_CPU "PowerPC,8349@0" ++#define OF_SOC "soc8349@e0000000" ++#define OF_TBCLK (bd->bi_busfreq / 4) ++#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" ++ ++#ifdef CONFIG_PCI ++ ++#define CONFIG_MPC83XX_PCI2 ++ ++/* ++ * General PCI ++ * Addresses are mapped 1-1. ++ */ ++#define CFG_PCI1_MEM_BASE 0x80000000 ++#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE ++#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ ++#define CFG_PCI1_MMIO_BASE (CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE) ++#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE ++#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ ++#define CFG_PCI1_IO_BASE 0x00000000 ++#define CFG_PCI1_IO_PHYS 0xE2000000 ++#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ ++ ++#ifdef CONFIG_MPC83XX_PCI2 ++#define CFG_PCI2_MEM_BASE (CFG_PCI1_MMIO_BASE + CFG_PCI1_MMIO_SIZE) ++#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE ++#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ ++#define CFG_PCI2_MMIO_BASE (CFG_PCI2_MEM_BASE + CFG_PCI2_MEM_SIZE) ++#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE ++#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ ++#define CFG_PCI2_IO_BASE 0x00000000 ++#define CFG_PCI2_IO_PHYS (CFG_PCI1_IO_PHYS + CFG_PCI1_IO_SIZE) ++#define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */ ++#endif ++ ++#define _IO_BASE 0x00000000 /* points to PCI I/O space */ ++ ++#define CONFIG_NET_MULTI ++#define CONFIG_PCI_PNP /* do pci plug-and-play */ ++ ++#ifdef CONFIG_RTL8139 ++/* This macro is used by RTL8139 but not defined in PPC architecture */ ++#define KSEG1ADDR(x) (x) ++#endif ++ ++#ifndef CONFIG_PCI_PNP ++ #define PCI_ENET0_IOADDR 0x00000000 ++ #define PCI_ENET0_MEMADDR CFG_PCI2_MEM_BASE ++ #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ ++#endif ++ ++#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ ++ ++#endif ++ ++/* TSEC */ ++ ++#ifdef CONFIG_TSEC_ENET ++ ++#ifndef CONFIG_NET_MULTI ++#define CONFIG_NET_MULTI ++#endif ++ ++#define CONFIG_MII ++#define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */ ++ ++#define CONFIG_MPC83XX_TSEC1 ++ ++#ifdef CONFIG_MPC83XX_TSEC1 ++#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" ++#define CFG_TSEC1_OFFSET 0x24000 ++#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ ++#define TSEC1_PHYIDX 0 ++#endif ++ ++#ifdef CONFIG_MPC83XX_TSEC2 ++#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" ++#define CFG_TSEC2_OFFSET 0x25000 ++#define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ ++#define TSEC2_PHY_ADDR 4 ++#define TSEC2_PHYIDX 0 ++#endif ++ ++#define CONFIG_ETHPRIME "Freescale TSEC" ++ ++#endif ++ ++ ++/* ++ * Environment ++ */ ++#ifndef CFG_RAMBOOT ++ #define CFG_ENV_IS_IN_FLASH ++ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) ++ #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ ++ #define CFG_ENV_SIZE 0x2000 ++#else ++ #define CFG_NO_FLASH /* Flash is not usable now */ ++ #define CFG_ENV_IS_NOWHERE /* Store ENV in memory only */ ++ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) ++ #define CFG_ENV_SIZE 0x2000 ++#endif ++ ++#define CONFIG_LOADS_ECHO /* echo on for serial download */ ++#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ ++ ++/* CONFIG_COMMANDS */ ++ ++#ifdef CONFIG_COMPACT_FLASH ++#define CONFIG_COMMANDS_CF (CFG_CMD_IDE | CFG_CMD_FAT) ++#else ++#define CONFIG_COMMANDS_CF 0 ++#endif ++ ++#ifdef CONFIG_PCI ++#define CONFIG_COMMANDS_PCI CFG_CMD_PCI ++#else ++#define CONFIG_COMMANDS_PCI 0 ++#endif ++ ++#ifdef CONFIG_HARD_I2C ++#define CONFIG_COMMANDS_I2C CFG_CMD_I2C ++#else ++#define CONFIG_COMMANDS_I2C 0 ++#endif ++ ++#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ ++ CONFIG_COMMANDS_CF | \ ++ CFG_CMD_NET | \ ++ CFG_CMD_PING | \ ++ CONFIG_COMMANDS_I2C | \ ++ CONFIG_COMMANDS_PCI | \ ++ CFG_CMD_SDRAM | \ ++ CFG_CMD_DATE | \ ++ CFG_CMD_CACHE | \ ++ CFG_CMD_IRQ) ++#include ++ ++/* Watchdog */ ++ ++#undef CONFIG_WATCHDOG /* watchdog disabled */ ++#ifdef CONFIG_WATCHDOG ++#define CFG_WATCHDOG_VALUE 0xFFFFFFC3 ++#endif ++ ++/* ++ * Miscellaneous configurable options ++ */ ++#define CFG_LONGHELP /* undef to save memory */ ++#define CFG_LOAD_ADDR 0x2000000 /* default load address */ ++#define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ ++#else ++ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ ++#endif ++ ++#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ ++#define CFG_MAXARGS 16 /* max number of command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ ++#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ ++ ++/* ++ * For booting Linux, the board info and command line data ++ * have to be in the first 8 MB of memory, since this is ++ * the maximum mapped by the Linux kernel during initialization. ++ */ ++#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ ++ ++/* Cache Configuration */ ++#define CFG_DCACHE_SIZE 32768 ++#define CFG_CACHELINE_SIZE 32 ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */ ++#endif ++ ++#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ ++ ++#define CFG_HRCW_LOW (\ ++ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ ++ HRCWL_DDR_TO_SCB_CLK_1X1 |\ ++ HRCWL_CSB_TO_CLKIN_4X1 |\ ++ HRCWL_VCO_1X2 |\ ++ HRCWL_CORE_TO_CSB_2X1) ++ ++#ifdef PCI_64BIT ++#define CFG_HRCW_HIGH (\ ++ HRCWH_PCI_HOST |\ ++ HRCWH_64_BIT_PCI |\ ++ HRCWH_PCI1_ARBITER_ENABLE |\ ++ HRCWH_PCI2_ARBITER_DISABLE |\ ++ HRCWH_CORE_ENABLE |\ ++ HRCWH_FROM_0X00000100 |\ ++ HRCWH_BOOTSEQ_DISABLE |\ ++ HRCWH_SW_WATCHDOG_DISABLE |\ ++ HRCWH_ROM_LOC_LOCAL_16BIT |\ ++ HRCWH_TSEC1M_IN_GMII |\ ++ HRCWH_TSEC2M_IN_GMII ) ++#else ++#define CFG_HRCW_HIGH (\ ++ HRCWH_PCI_HOST |\ ++ HRCWH_32_BIT_PCI |\ ++ HRCWH_PCI1_ARBITER_ENABLE |\ ++ HRCWH_PCI2_ARBITER_DISABLE |\ ++ HRCWH_CORE_ENABLE |\ ++ HRCWH_FROM_0XFFF00100 |\ ++ HRCWH_BOOTSEQ_DISABLE |\ ++ HRCWH_SW_WATCHDOG_DISABLE |\ ++ HRCWH_ROM_LOC_LOCAL_16BIT |\ ++ HRCWH_TSEC1M_IN_GMII |\ ++ HRCWH_TSEC2M_IN_GMII ) ++#endif ++ ++/* System performance */ ++#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ ++#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ ++#define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ ++#define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ ++#define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ ++#define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ ++#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count */ ++ ++/* System IO Config */ ++#define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ ++#define CFG_SICRL (SICRL_LDP_A | SICRL_USB1) ++ ++#define CFG_HID0_INIT 0x000000000 ++ ++#define CFG_HID0_FINAL CFG_HID0_INIT ++ ++#define CFG_HID2 HID2_HBE ++ ++/* DDR @ 0x00000000 */ ++#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) ++#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) ++ ++/* PCI @ 0x80000000 */ ++#ifdef CONFIG_PCI ++#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) ++#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) ++#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) ++#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) ++#else ++#define CFG_IBAT1L 0 ++#define CFG_IBAT1U 0 ++#define CFG_IBAT2L 0 ++#define CFG_IBAT2U 0 ++#endif ++ ++#ifdef CONFIG_MPC83XX_PCI2 ++#define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) ++#define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) ++#define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) ++#define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) ++#else ++#define CFG_IBAT3L 0 ++#define CFG_IBAT3U 0 ++#define CFG_IBAT4L 0 ++#define CFG_IBAT4U 0 ++#endif ++ ++/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ ++#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) ++#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) ++ ++/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ ++#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) ++#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) ++ ++#define CFG_IBAT7L 0 ++#define CFG_IBAT7U 0 ++ ++#define CFG_DBAT0L CFG_IBAT0L ++#define CFG_DBAT0U CFG_IBAT0U ++#define CFG_DBAT1L CFG_IBAT1L ++#define CFG_DBAT1U CFG_IBAT1U ++#define CFG_DBAT2L CFG_IBAT2L ++#define CFG_DBAT2U CFG_IBAT2U ++#define CFG_DBAT3L CFG_IBAT3L ++#define CFG_DBAT3U CFG_IBAT3U ++#define CFG_DBAT4L CFG_IBAT4L ++#define CFG_DBAT4U CFG_IBAT4U ++#define CFG_DBAT5L CFG_IBAT5L ++#define CFG_DBAT5U CFG_IBAT5U ++#define CFG_DBAT6L CFG_IBAT6L ++#define CFG_DBAT6U CFG_IBAT6U ++#define CFG_DBAT7L CFG_IBAT7L ++#define CFG_DBAT7U CFG_IBAT7U ++ ++/* ++ * Internal Definitions ++ * ++ * Boot Flags ++ */ ++#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ ++#define BOOTFLAG_WARM 0x02 /* Software reboot */ ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ ++#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ ++#endif ++ ++ ++/* ++ * Environment Configuration ++ */ ++#define CONFIG_ENV_OVERWRITE ++ ++#ifdef CONFIG_MPC83XX_TSEC1 ++#define CONFIG_ETHADDR 00:E0:0C:00:8C:01 ++#endif ++ ++#ifdef CONFIG_MPC83XX_TSEC2 ++#define CONFIG_HAS_ETH1 ++#define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 ++#endif ++ ++#if 1 ++#define CONFIG_IPADDR 10.82.19.159 ++#define CONFIG_SERVERIP 10.82.48.106 ++#define CONFIG_GATEWAYIP 10.82.19.254 ++#define CONFIG_NETMASK 255.255.252.0 ++#define CONFIG_NETDEV eth0 ++ ++#define CONFIG_HOSTNAME mpc8349emitx ++#define CONFIG_ROOTPATH /nfsroot0/u/timur/itx-ltib/rootfs ++#define CONFIG_BOOTFILE timur/uImage ++ ++#define CONFIG_UBOOTPATH timur/u-boot.bin ++#else ++#define CONFIG_IPADDR 192.168.1.253 ++#define CONFIG_SERVERIP 192.168.1.1 ++#define CONFIG_GATEWAYIP 192.168.1.1 ++#define CONFIG_NETMASK 255.255.252.0 ++#define CONFIG_NETDEV eth0 ++ ++#define CONFIG_HOSTNAME mpc8349emitx ++#define CONFIG_ROOTPATH /nfsroot/rootfs ++#define CONFIG_BOOTFILE uImage ++ ++#define CONFIG_UBOOTPATH u-boot.bin ++#endif ++ ++#define CONFIG_UBOOTSTART fe700000 ++#define CONFIG_UBOOTEND fe77ffff ++ ++#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ ++ ++#define CONFIG_BAUDRATE 115200 ++ ++#undef CONFIG_BOOTCOMMAND ++#ifdef CONFIG_BOOTCOMMAND ++#define CONFIG_BOOTDELAY 6 ++#else ++#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ ++#endif ++ ++#define XMK_STR(x) #x ++#define MK_STR(x) XMK_STR(x) ++ ++#define CONFIG_BOOTARGS \ ++ "root=/dev/nfs rw" \ ++ " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ ++ " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ ++ MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ ++ MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ ++ " console=ttyS0," MK_STR(CONFIG_BAUDRATE) ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ ++ "tftpflash=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ ++ "erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ ++ "cp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize; " \ ++ "cmp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize\0" \ ++ "tftpupdate=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ ++ "protect off FEF00000 FEF7FFFF; " \ ++ "erase FEF00000 FEF7FFFF; " \ ++ "cp.b $loadaddr FEF00000 $filesize; " \ ++ "protect on FEF00000 FEF7FFFF; " \ ++ "cmp.b $loadaddr FEF00000 $filesize\0" \ ++ "tftplinux=tftpboot $loadaddr $bootfile; bootm\0" \ ++ "copyuboot=erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ ++ "cp.b fef00000 " MK_STR(CONFIG_UBOOTSTART) " 80000\0" \ ++ "fdtaddr=400000\0" \ ++ "fdtfile=mpc8349emitx.dtb\0" \ ++ "" ++ ++#define CONFIG_NFSBOOTCOMMAND \ ++ "setenv bootargs root=/dev/nfs rw " \ ++ "nfsroot=$serverip:$rootpath " \ ++ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ ++ "console=$consoledev,$baudrate $othbootargs;" \ ++ "tftp $loadaddr $bootfile;" \ ++ "tftp $fdtaddr $fdtfile;" \ ++ "bootm $loadaddr - $fdtaddr" ++ ++#define CONFIG_RAMBOOTCOMMAND \ ++ "setenv bootargs root=/dev/ram rw " \ ++ "console=$consoledev,$baudrate $othbootargs;" \ ++ "tftp $ramdiskaddr $ramdiskfile;" \ ++ "tftp $loadaddr $bootfile;" \ ++ "tftp $fdtaddr $fdtfile;" \ ++ "bootm $loadaddr $ramdiskaddr $fdtaddr" ++ ++ ++#undef MK_STR ++#undef XMK_STR ++ ++#endif +diff -Naupr u-boot-1.1.6/include/configs/MPC8360EMDS.h u-boot-1.1.6-fsl-1/include/configs/MPC8360EMDS.h +--- u-boot-1.1.6/include/configs/MPC8360EMDS.h 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/configs/MPC8360EMDS.h 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,635 @@ ++/* ++ * Copyright (C) 2006 Freescale Semiconductor, Inc. ++ * ++ * Dave Liu ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#undef DEBUG ++ ++/* ++ * High Level Configuration Options ++ */ ++#define CONFIG_E300 1 /* E300 family */ ++#define CONFIG_QE 1 /* Has QE */ ++#define CONFIG_MPC83XX 1 /* MPC83XX family */ ++#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ ++#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */ ++ ++/* ++ * System Clock Setup ++ */ ++#ifdef CONFIG_PCISLAVE ++#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ ++#else ++#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ ++#endif ++ ++#ifndef CONFIG_SYS_CLK_FREQ ++#define CONFIG_SYS_CLK_FREQ 66000000 ++#endif ++ ++/* ++ * Hardware Reset Configuration Word ++ */ ++#define CFG_HRCW_LOW (\ ++ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ ++ HRCWL_DDR_TO_SCB_CLK_1X1 |\ ++ HRCWL_CSB_TO_CLKIN_4X1 |\ ++ HRCWL_VCO_1X2 |\ ++ HRCWL_CE_PLL_VCO_DIV_4 |\ ++ HRCWL_CE_PLL_DIV_1X1 |\ ++ HRCWL_CE_TO_PLL_1X6 |\ ++ HRCWL_CORE_TO_CSB_2X1) ++ ++#ifdef CONFIG_PCISLAVE ++#define CFG_HRCW_HIGH (\ ++ HRCWH_PCI_AGENT |\ ++ HRCWH_PCI1_ARBITER_DISABLE |\ ++ HRCWH_PCICKDRV_DISABLE |\ ++ HRCWH_CORE_ENABLE |\ ++ HRCWH_FROM_0XFFF00100 |\ ++ HRCWH_BOOTSEQ_DISABLE |\ ++ HRCWH_SW_WATCHDOG_DISABLE |\ ++ HRCWH_ROM_LOC_LOCAL_16BIT) ++#else ++#define CFG_HRCW_HIGH (\ ++ HRCWH_PCI_HOST |\ ++ HRCWH_PCI1_ARBITER_ENABLE |\ ++ HRCWH_PCICKDRV_ENABLE |\ ++ HRCWH_CORE_ENABLE |\ ++ HRCWH_FROM_0X00000100 |\ ++ HRCWH_BOOTSEQ_DISABLE |\ ++ HRCWH_SW_WATCHDOG_DISABLE |\ ++ HRCWH_ROM_LOC_LOCAL_16BIT) ++#endif ++ ++/* ++ * System IO Config ++ */ ++#define CFG_SICRH 0x00000000 ++#define CFG_SICRL 0x40000000 ++ ++#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ ++ ++/* ++ * IMMR new address ++ */ ++#define CFG_IMMR 0xE0000000 ++ ++/* ++ * DDR Setup ++ */ ++#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ ++#define CFG_SDRAM_BASE CFG_DDR_BASE ++#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE ++ ++#define CFG_83XX_DDR_USES_CS0 ++ ++#undef CONFIG_DDR_ECC /* only for ECC DDR module */ ++#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ ++ ++#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ ++#if defined(CONFIG_SPD_EEPROM) ++/* ++ * Determine DDR configuration from I2C interface. ++ */ ++#define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */ ++#else ++/* ++ * Manually set up DDR parameters ++ */ ++#define CFG_DDR_SIZE 256 /* MB */ ++#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9) ++#define CFG_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */ ++#define CFG_DDR_TIMING_2 0x00000800 /* may need tuning */ ++#define CFG_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */ ++#define CFG_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */ ++#define CFG_DDR_INTERVAL 0x045b0100 /* page mode */ ++#endif ++ ++/* ++ * Memory test ++ */ ++#undef CFG_DRAM_TEST /* memory test, takes time */ ++#define CFG_MEMTEST_START 0x00000000 /* memtest region */ ++#define CFG_MEMTEST_END 0x00100000 ++ ++/* ++ * The reserved memory ++ */ ++ ++#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ ++ ++#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) ++#define CFG_RAMBOOT ++#else ++#undef CFG_RAMBOOT ++#endif ++ ++#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ ++#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ ++ ++/* ++ * Initial RAM Base Address Setup ++ */ ++#define CFG_INIT_RAM_LOCK 1 ++#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ ++#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ ++#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ ++#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) ++ ++/* ++ * Local Bus Configuration & Clock Setup ++ */ ++#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) ++#define CFG_LBC_LBCR 0x00000000 ++ ++/* ++ * FLASH on the Local Bus ++ */ ++#define CFG_FLASH_CFI /* use the Common Flash Interface */ ++#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ ++#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ ++#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */ ++ ++#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ ++#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ ++ ++#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ ++ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ ++ BR_V) /* valid */ ++#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ ++ ++#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ ++#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ ++ ++#undef CFG_FLASH_CHECKSUM ++ ++/* ++ * BCSR on the Local Bus ++ */ ++#define CFG_BCSR 0xF8000000 ++#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ ++#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ ++ ++#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */ ++#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ ++ ++/* ++ * SDRAM on the Local Bus ++ */ ++#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ ++#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ ++ ++#define CFG_LB_SDRAM /* if board has SRDAM on local bus */ ++ ++#ifdef CFG_LB_SDRAM ++#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE ++#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ ++ ++/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ ++/* ++ * Base Register 2 and Option Register 2 configure SDRAM. ++ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. ++ * ++ * For BR2, need: ++ * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 ++ * port size = 32-bits = BR2[19:20] = 11 ++ * no parity checking = BR2[21:22] = 00 ++ * SDRAM for MSEL = BR2[24:26] = 011 ++ * Valid = BR[31] = 1 ++ * ++ * 0 4 8 12 16 20 24 28 ++ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 ++ * ++ * CFG_LBC_SDRAM_BASE should be masked and OR'ed into ++ * the top 17 bits of BR2. ++ */ ++ ++#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ ++ ++/* ++ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. ++ * ++ * For OR2, need: ++ * 64MB mask for AM, OR2[0:7] = 1111 1100 ++ * XAM, OR2[17:18] = 11 ++ * 9 columns OR2[19-21] = 010 ++ * 13 rows OR2[23-25] = 100 ++ * EAD set for extra time OR[31] = 1 ++ * ++ * 0 4 8 12 16 20 24 28 ++ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 ++ */ ++ ++#define CFG_OR2_PRELIM 0xfc006901 ++ ++#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ ++#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ ++ ++/* ++ * LSDMR masks ++ */ ++#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) ++#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) ++ ++#define CFG_LBC_LSDMR_COMMON 0x0063b723 ++ ++/* ++ * SDRAM Controller configuration sequence. ++ */ ++#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ ++ | CFG_LBC_LSDMR_OP_PCHALL) ++#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ ++ | CFG_LBC_LSDMR_OP_ARFRSH) ++#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ ++ | CFG_LBC_LSDMR_OP_ARFRSH) ++#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ ++ | CFG_LBC_LSDMR_OP_MRW) ++#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ ++ | CFG_LBC_LSDMR_OP_NORMAL) ++ ++#endif ++ ++/* ++ * Windows to access PIB via local bus ++ */ ++#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ ++#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ ++ ++/* ++ * CS4 on Local Bus, to PIB ++ */ ++#define CFG_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */ ++#define CFG_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ ++ ++/* ++ * CS5 on Local Bus, to PIB ++ */ ++#define CFG_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */ ++#define CFG_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ ++ ++/* ++ * Serial Port ++ */ ++#define CONFIG_CONS_INDEX 1 ++#undef CONFIG_SERIAL_SOFTWARE_FIFO ++#define CFG_NS16550 ++#define CFG_NS16550_SERIAL ++#define CFG_NS16550_REG_SIZE 1 ++#define CFG_NS16550_CLK get_bus_freq(0) ++ ++#define CFG_BAUDRATE_TABLE \ ++ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} ++ ++#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) ++#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) ++ ++/* Use the HUSH parser */ ++#define CFG_HUSH_PARSER ++#ifdef CFG_HUSH_PARSER ++#define CFG_PROMPT_HUSH_PS2 "> " ++#endif ++ ++/* pass open firmware flat tree */ ++#define CONFIG_OF_FLAT_TREE 1 ++#define CONFIG_OF_BOARD_SETUP 1 ++ ++/* maximum size of the flat tree (8K) */ ++#define OF_FLAT_TREE_MAX_SIZE 8192 ++ ++#define OF_CPU "PowerPC,8360@0" ++#define OF_SOC "soc8360@e0000000" ++#define OF_TBCLK (bd->bi_busfreq / 4) ++#define OF_STDOUT_PATH "/soc8360@e0000000/serial@4500" ++ ++/* I2C */ ++#define CONFIG_HARD_I2C /* I2C with hardware support */ ++#undef CONFIG_SOFT_I2C /* I2C bit-banged */ ++#define CONFIG_FSL_I2C ++#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ ++#define CFG_I2C_SLAVE 0x7F ++#define CFG_I2C_NOPROBES {0x52} /* Don't probe these addrs */ ++#define CFG_I2C_OFFSET 0x3000 ++#define CFG_I2C2_OFFSET 0x3100 ++ ++/* ++ * Config on-board RTC ++ */ ++#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ ++#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ ++ ++/* ++ * General PCI ++ * Addresses are mapped 1-1. ++ */ ++#define CFG_PCI_MEM_BASE 0x80000000 ++#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE ++#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ ++#define CFG_PCI_MMIO_BASE 0x90000000 ++#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE ++#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ ++#define CFG_PCI_IO_BASE 0xE0300000 ++#define CFG_PCI_IO_PHYS 0xE0300000 ++#define CFG_PCI_IO_SIZE 0x100000 /* 1M */ ++ ++#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE ++#define CFG_PCI_SLV_MEM_BUS 0x00000000 ++#define CFG_PCI_SLV_MEM_SIZE 0x80000000 ++ ++ ++#ifdef CONFIG_PCI ++ ++#define CONFIG_NET_MULTI ++#define CONFIG_PCI_PNP /* do pci plug-and-play */ ++ ++#undef CONFIG_EEPRO100 ++#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ ++#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ ++ ++#endif /* CONFIG_PCI */ ++ ++ ++#ifndef CONFIG_NET_MULTI ++#define CONFIG_NET_MULTI 1 ++#endif ++ ++/* ++ * QE UEC ethernet configuration ++ */ ++#define CONFIG_UEC_ETH ++#define CONFIG_ETHPRIME "Freescale GETH" ++#define CONFIG_PHY_MODE_NEED_CHANGE ++ ++#define CONFIG_UEC_ETH1 /* GETH1 */ ++ ++#ifdef CONFIG_UEC_ETH1 ++#define CFG_UEC1_UCC_NUM 0 /* UCC1 */ ++#define CFG_UEC1_RX_CLK QE_CLK_NONE ++#define CFG_UEC1_TX_CLK QE_CLK9 ++#define CFG_UEC1_ETH_TYPE GIGA_ETH ++#define CFG_UEC1_PHY_ADDR 0 ++#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII ++#endif ++ ++#define CONFIG_UEC_ETH2 /* GETH2 */ ++ ++#ifdef CONFIG_UEC_ETH2 ++#define CFG_UEC2_UCC_NUM 1 /* UCC2 */ ++#define CFG_UEC2_RX_CLK QE_CLK_NONE ++#define CFG_UEC2_TX_CLK QE_CLK4 ++#define CFG_UEC2_ETH_TYPE GIGA_ETH ++#define CFG_UEC2_PHY_ADDR 1 ++#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII ++#endif ++ ++/* ++ * Environment ++ */ ++ ++#ifndef CFG_RAMBOOT ++ #define CFG_ENV_IS_IN_FLASH 1 ++ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) ++ #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ ++ #define CFG_ENV_SIZE 0x2000 ++#else ++ #define CFG_NO_FLASH 1 /* Flash is not usable now */ ++ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ ++ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) ++ #define CFG_ENV_SIZE 0x2000 ++#endif ++ ++#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ ++#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ ++ ++#if defined(CFG_RAMBOOT) ++#if defined(CONFIG_PCI) ++#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ ++ | CFG_CMD_PING \ ++ | CFG_CMD_ASKENV \ ++ | CFG_CMD_PCI \ ++ | CFG_CMD_I2C) \ ++ & \ ++ ~(CFG_CMD_ENV \ ++ | CFG_CMD_LOADS)) ++#else ++#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ ++ | CFG_CMD_PING \ ++ | CFG_CMD_ASKENV \ ++ | CFG_CMD_I2C) \ ++ & \ ++ ~(CFG_CMD_ENV \ ++ | CFG_CMD_LOADS)) ++#endif ++#else ++#if defined(CONFIG_PCI) ++#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ ++ | CFG_CMD_PCI \ ++ | CFG_CMD_PING \ ++ | CFG_CMD_ASKENV \ ++ | CFG_CMD_I2C) ++#else ++#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ ++ | CFG_CMD_PING \ ++ | CFG_CMD_ASKENV \ ++ | CFG_CMD_I2C ) ++#endif ++#endif ++ ++#include ++ ++#undef CONFIG_WATCHDOG /* watchdog disabled */ ++ ++/* ++ * Miscellaneous configurable options ++ */ ++#define CFG_LONGHELP /* undef to save memory */ ++#define CFG_LOAD_ADDR 0x2000000 /* default load address */ ++#define CFG_PROMPT "=> " /* Monitor Command Prompt */ ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ ++#else ++ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ ++#endif ++ ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ ++#define CFG_MAXARGS 16 /* max number of command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ ++#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ ++ ++/* ++ * For booting Linux, the board info and command line data ++ * have to be in the first 8 MB of memory, since this is ++ * the maximum mapped by the Linux kernel during initialization. ++ */ ++#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ ++ ++/* ++ * Core HID Setup ++ */ ++#define CFG_HID0_INIT 0x000000000 ++#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK ++#define CFG_HID2 HID2_HBE ++ ++/* ++ * Cache Config ++ */ ++#define CFG_DCACHE_SIZE 32768 ++#define CFG_CACHELINE_SIZE 32 ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ ++#endif ++ ++/* ++ * MMU Setup ++ */ ++ ++/* DDR: cache cacheable */ ++#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) ++#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) ++#define CFG_DBAT0L CFG_IBAT0L ++#define CFG_DBAT0U CFG_IBAT0U ++ ++/* IMMRBAR & PCI IO: cache-inhibit and guarded */ ++#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ ++ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) ++#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) ++#define CFG_DBAT1L CFG_IBAT1L ++#define CFG_DBAT1U CFG_IBAT1U ++ ++/* BCSR: cache-inhibit and guarded */ ++#define CFG_IBAT2L (CFG_BCSR | BATL_PP_10 | \ ++ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) ++#define CFG_IBAT2U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) ++#define CFG_DBAT2L CFG_IBAT2L ++#define CFG_DBAT2U CFG_IBAT2U ++ ++/* FLASH: icache cacheable, but dcache-inhibit and guarded */ ++#define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) ++#define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) ++#define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \ ++ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) ++#define CFG_DBAT3U CFG_IBAT3U ++ ++/* Local bus SDRAM: cacheable */ ++#define CFG_IBAT4L (CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) ++#define CFG_IBAT4U (CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) ++#define CFG_DBAT4L CFG_IBAT4L ++#define CFG_DBAT4U CFG_IBAT4U ++ ++/* Stack in dcache: cacheable, no memory coherence */ ++#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) ++#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) ++#define CFG_DBAT5L CFG_IBAT5L ++#define CFG_DBAT5U CFG_IBAT5U ++ ++#ifdef CONFIG_PCI ++/* PCI MEM space: cacheable */ ++#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) ++#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) ++#define CFG_DBAT6L CFG_IBAT6L ++#define CFG_DBAT6U CFG_IBAT6U ++/* PCI MMIO space: cache-inhibit and guarded */ ++#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ ++ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) ++#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) ++#define CFG_DBAT7L CFG_IBAT7L ++#define CFG_DBAT7U CFG_IBAT7U ++#else ++#define CFG_IBAT6L (0) ++#define CFG_IBAT6U (0) ++#define CFG_IBAT7L (0) ++#define CFG_IBAT7U (0) ++#define CFG_DBAT6L CFG_IBAT6L ++#define CFG_DBAT6U CFG_IBAT6U ++#define CFG_DBAT7L CFG_IBAT7L ++#define CFG_DBAT7U CFG_IBAT7U ++#endif ++ ++/* ++ * Internal Definitions ++ * ++ * Boot Flags ++ */ ++#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ ++#define BOOTFLAG_WARM 0x02 /* Software reboot */ ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ ++#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ ++#endif ++ ++/* ++ * Environment Configuration ++ */ ++ ++#define CONFIG_ENV_OVERWRITE ++ ++#if defined(CONFIG_UEC_ETH) ++#define CONFIG_ETHADDR 00:04:9f:ef:01:01 ++#define CONFIG_HAS_ETH1 ++#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02 ++#endif ++ ++#define CONFIG_BAUDRATE 115200 ++ ++#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ ++ ++#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ ++#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "netdev=eth0\0" \ ++ "consoledev=ttyS0\0" \ ++ "ramdiskaddr=1000000\0" \ ++ "ramdiskfile=ramfs.83xx\0" \ ++ "fdtaddr=400000\0" \ ++ "fdtfile=mpc8349emds.dtb\0" \ ++ "" ++ ++#define CONFIG_NFSBOOTCOMMAND \ ++ "setenv bootargs root=/dev/nfs rw " \ ++ "nfsroot=$serverip:$rootpath " \ ++ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ ++ "console=$consoledev,$baudrate $othbootargs;" \ ++ "tftp $loadaddr $bootfile;" \ ++ "tftp $fdtaddr $fdtfile;" \ ++ "bootm $loadaddr - $fdtaddr" ++ ++#define CONFIG_RAMBOOTCOMMAND \ ++ "setenv bootargs root=/dev/ram rw " \ ++ "console=$consoledev,$baudrate $othbootargs;" \ ++ "tftp $ramdiskaddr $ramdiskfile;" \ ++ "tftp $loadaddr $bootfile;" \ ++ "tftp $fdtaddr $fdtfile;" \ ++ "bootm $loadaddr $ramdiskaddr $fdtaddr" ++ ++ ++#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND ++ ++#endif /* __CONFIG_H */ +diff -Naupr u-boot-1.1.6/include/configs/p3mx.h u-boot-1.1.6-fsl-1/include/configs/p3mx.h +--- u-boot-1.1.6/include/configs/p3mx.h 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/configs/p3mx.h 2006-12-06 10:33:49.000000000 -0600 +@@ -0,0 +1,450 @@ ++/* ++ * (C) Copyright 2006 ++ * Stefan Roese, DENX Software Engineering, sr@denx.de. ++ * ++ * Based on original work by ++ * Roel Loeffen, (C) Copyright 2006 Prodrive B.V. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/************************************************************************ ++ * p3mx.h - configuration for Prodrive P3M750 & P3M7448 boards ++ * ++ * The defines: ++ * CONFIG_P3M750 or ++ * CONFIG_P3M7448 ++ * are written into include/config.h by the "make xxx_config" command ++ ***********************************************************************/ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++/*----------------------------------------------------------------------- ++ * High Level Configuration Options ++ *----------------------------------------------------------------------*/ ++#define CONFIG_P3Mx /* used for both board versions */ ++ ++#if defined (CONFIG_P3M750) ++#define CONFIG_750FX /* 750GL/GX/FX */ ++#define CFG_BOARD_NAME "P3M750" ++#define CFG_BUS_HZ 100000000 ++#define CFG_BUS_CLK CFG_BUS_HZ ++#define CFG_TCLK 100000000 ++#elif defined (CONFIG_P3M7448) ++#define CONFIG_74xx ++#define CFG_BOARD_NAME "P3M7448" ++#define CFG_BUS_HZ 133333333 ++#define CFG_BUS_CLK CFG_BUS_HZ ++#define CFG_TCLK 133333333 ++#endif ++#define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */ ++ ++/* which initialization functions to call for this board */ ++#define CFG_BOARD_ASM_INIT 1 ++#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ ++#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_f */ ++#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ ++#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ ++ ++/*----------------------------------------------------------------------- ++ * Base addresses -- Note these are effective addresses where the ++ * actual resources get mapped (not physical addresses) ++ *----------------------------------------------------------------------*/ ++#define CFG_SDRAM_BASE 0x00000000 ++#ifdef CONFIG_P3M750 ++#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */ ++#endif ++ ++#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ ++#if defined (CONFIG_P3M750) ++#define CFG_FLASH_BASE 0xff800000 /* start of flash banks */ ++#define CFG_BOOT_SIZE _8M /* boot flash */ ++#elif defined (CONFIG_P3M7448) ++#define CFG_FLASH_BASE 0xff000000 /* start of flash banks */ ++#define CFG_BOOT_SIZE _16M /* boot flash */ ++#endif ++#define CFG_BOOT_SPACE CFG_FLASH_BASE /* BOOT_CS0 flash 0 */ ++#define CFG_MONITOR_BASE 0xfff00000 ++#define CFG_RESET_ADDRESS 0xfff00100 ++#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ ++#define CFG_MISC_REGION_BASE 0xf0000000 ++ ++#define CFG_DFL_GT_REGS 0xf1000000 /* boot time GT_REGS */ ++#define CFG_GT_REGS 0xf1000000 /* GT Registers are mapped here */ ++#define CFG_INT_SRAM_BASE 0x42000000 /* GT offers 256k internal SRAM */ ++ ++/*----------------------------------------------------------------------- ++ * Initial RAM & stack pointer (placed in internal SRAM) ++ *----------------------------------------------------------------------*/ ++ /* ++ * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS ++ * To an unused memory region. The stack will remain in cache until RAM ++ * is initialized ++*/ ++#undef CFG_INIT_RAM_LOCK ++#define CFG_INIT_RAM_ADDR 0x42000000 ++#define CFG_INIT_RAM_END 0x1000 ++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ ++#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) ++ ++ ++/*----------------------------------------------------------------------- ++ * Serial Port ++ *----------------------------------------------------------------------*/ ++#define CONFIG_MPSC /* MV64460 Serial */ ++#define CONFIG_MPSC_PORT 0 ++#define CONFIG_BAUDRATE 115200 /* console baudrate */ ++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } ++#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ ++#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ ++ ++/*----------------------------------------------------------------------- ++ * Ethernet ++ *----------------------------------------------------------------------*/ ++/* Change the default ethernet port, use this define (options: 0, 1, 2) */ ++#define CFG_ETH_PORT ETH_0 ++#define CONFIG_NET_MULTI ++#define MV_ETH_DEVS 2 ++#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ ++#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ ++ ++/*----------------------------------------------------------------------- ++ * FLASH related ++ *----------------------------------------------------------------------*/ ++#define CFG_FLASH_CFI /* The flash is CFI compatible */ ++#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ ++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ ++#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ ++#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ ++#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ ++#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ ++#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ ++#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ ++ ++#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ ++#if defined (CONFIG_P3M750) ++#define CFG_ENV_SECT_SIZE 0x20000 /* one sector (1 device)*/ ++#elif defined (CONFIG_P3M7448) ++#define CFG_ENV_SECT_SIZE 0x40000 /* two sectors (2 devices parallel */ ++#endif ++#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ ++#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) ++ ++/*----------------------------------------------------------------------- ++ * DDR SDRAM ++ *----------------------------------------------------------------------*/ ++#define CONFIG_MV64460_ECC ++ ++/*----------------------------------------------------------------------- ++ * I2C ++ *----------------------------------------------------------------------*/ ++#define CFG_I2C_SPEED 100000 /* I2C speed default */ ++ ++/* I2C RTC */ ++#define CONFIG_RTC_M41T11 1 ++#define CFG_I2C_RTC_ADDR 0x68 ++#define CFG_M41T11_BASE_YEAR 1900 /* play along with linux */ ++ ++/*----------------------------------------------------------------------- ++ * PCI stuff ++ *----------------------------------------------------------------------*/ ++#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ ++#define PCI_HOST_FORCE 1 /* configure as pci host */ ++#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ ++ ++#define CONFIG_PCI /* include pci support */ ++#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ ++#define CONFIG_PCI_PNP /* do pci plug-and-play */ ++#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ ++ ++/* PCI MEMORY MAP section */ ++#define CFG_PCI0_MEM_BASE 0x80000000 ++#define CFG_PCI0_MEM_SIZE _128M ++#define CFG_PCI1_MEM_BASE 0x88000000 ++#define CFG_PCI1_MEM_SIZE _128M ++ ++#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) ++#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) ++ ++/* PCI I/O MAP section */ ++#define CFG_PCI0_IO_BASE 0xfa000000 ++#define CFG_PCI0_IO_SIZE _16M ++#define CFG_PCI1_IO_BASE 0xfb000000 ++#define CFG_PCI1_IO_SIZE _16M ++ ++#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) ++#define CFG_PCI0_IO_SPACE_PCI 0x00000000 ++#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) ++#define CFG_PCI1_IO_SPACE_PCI 0x00000000 ++ ++#define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE) ++ ++#define CFG_PCI_IDSEL 0x30 ++ ++#undef CONFIG_BOOTARGS ++#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ ++ "netdev=eth0\0" \ ++ "nfsargs=setenv bootargs root=/dev/nfs rw " \ ++ "nfsroot=${serverip}:${rootpath}\0" \ ++ "ramargs=setenv bootargs root=/dev/ram rw\0" \ ++ "addip=setenv bootargs ${bootargs} " \ ++ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ++ ":${hostname}:${netdev}:off panic=1\0" \ ++ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ ++ "flash_nfs=run nfsargs addip addtty;" \ ++ "bootm ${kernel_addr}\0" \ ++ "flash_self=run ramargs addip addtty;" \ ++ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ ++ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ ++ "bootm\0" \ ++ "rootpath=/opt/eldk/ppc_6xx\0" \ ++ "u-boot=p3mx/u-boot/u-boot.bin\0" \ ++ "load=tftp 100000 ${u-boot}\0" \ ++ "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \ ++ "cp.b 100000 fff00000 40000;" \ ++ "setenv filesize;saveenv\0" \ ++ "upd=run load;run update\0" \ ++ "serverip=11.0.0.152\0" ++ ++#if defined (CONFIG_P3M750) ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_EXTRA_ENV_SETTINGS_COMMON \ ++ "hostname=p3m750\0" \ ++ "bootfile=/tftpboot/p3mx/vxWorks.st\0" \ ++ "kernel_addr=fc000000\0" \ ++ "ramdisk_addr=fc180000\0" \ ++ "vxfile=p3m750/vxWorks\0" \ ++ "vxuser=ddg\0" \ ++ "vxpass=ddg\0" \ ++ "vxtarget=target\0" \ ++ "vxflags=0x8\0" \ ++ "vxargs=setenv bootargs mgi(0,0)host:${vxfile} h=${serverip} " \ ++ "e=${ipaddr} u=${vxuser} pw=${vxpass} tn=${vxtarget} " \ ++ "f=${vxflags}\0" ++#elif defined (CONFIG_P3M7448) ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_EXTRA_ENV_SETTINGS_COMMON \ ++ "hostname=p3m7448\0" ++#endif ++ ++#if defined (CONFIG_P3M750) ++#define CONFIG_BOOTCOMMAND "tftp;run vxargs;bootvx" ++#elif defined (CONFIG_P3M7448) ++#define CONFIG_BOOTCOMMAND " " ++#endif ++ ++#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ ++#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ ++ CONFIG_BOOTP_BOOTFILESIZE) ++#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ ++ CFG_CMD_ASKENV | \ ++ CFG_CMD_DATE | \ ++ CFG_CMD_DIAG | \ ++ CFG_CMD_ELF | \ ++ CFG_CMD_I2C | \ ++ CFG_CMD_IRQ | \ ++ CFG_CMD_MII | \ ++ CFG_CMD_NET | \ ++ CFG_CMD_NFS | \ ++ CFG_CMD_PING | \ ++ CFG_CMD_REGINFO | \ ++ CFG_CMD_PCI | \ ++ CFG_CMD_CACHE | \ ++ CFG_CMD_SDRAM) ++ ++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ ++#include ++ ++/*----------------------------------------------------------------------- ++ * Miscellaneous configurable options ++ *----------------------------------------------------------------------*/ ++#define CFG_HUSH_PARSER ++#define CFG_PROMPT_HUSH_PS2 "> " ++ ++#define CFG_LONGHELP /* undef to save memory */ ++#define CFG_PROMPT "=> " /* Monitor Command Prompt */ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ ++#else ++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ ++#endif ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ ++#define CFG_MAXARGS 16 /* max number of command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ ++ ++#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ ++#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ ++ ++#define CFG_LOAD_ADDR 0x08000000 /* default load address */ ++ ++#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ ++ ++#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ ++#define CONFIG_LOOPW 1 /* enable loopw command */ ++#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ ++#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ ++#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ ++ ++/*----------------------------------------------------------------------- ++ * Marvell MV64460 config settings ++ *----------------------------------------------------------------------*/ ++/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */ ++#if defined (CONFIG_P3M750) ++#define CFG_BOOT_PAR 0x8FDFF87F /* 16 bit flash, disable burst*/ ++#elif defined (CONFIG_P3M7448) ++#define CFG_BOOT_PAR 0x8FEFFFFF /* 32 bit flash, burst enabled */ ++#endif ++ ++/* ++ * MPP[0] Serial Port 0 TxD TxD OUT Connected to P14 (buffered) ++ * MPP[1] Serial Port 0 RxD RxD IN Connected to P14 (buffered) ++ * MPP[2] NC ++ * MPP[3] Serial Port 1 TxD TxD OUT Connected to P14 (buffered) ++ * MPP[4] PCI Monarch# GPIO IN Connected to P12 ++ * MPP[5] Serial Port 1 RxD RxD IN Connected to P14 (buffered) ++ * MPP[6] PMC Carrier Interrupt 0 Int IN Connected to P14 ++ * MPP[7] PMC Carrier Interrupt 1 Int IN Connected to P14 ++ * MPP[8] Reserved Do not use ++ * MPP[9] Reserved Do not use ++ * MPP[10] Reserved Do not use ++ * MPP[11] Reserved Do not use ++ * MPP[12] Phy 0 Interrupt Int IN ++ * MPP[13] Phy 1 Interrupt Int IN ++ * MPP[14] NC ++ * MPP[15] NC ++ * MPP[16] PCI Interrupt C Int IN Connected to P11 ++ * MPP[17] PCI Interrupt D Int IN Connected to P11 ++ * MPP[18] Watchdog NMI# GPIO IN Connected to MPP[24] ++ * MPP[19] Watchdog Expired# WDE OUT Connected to rst logic ++ * MPP[20] Watchdog Status WD_STS IN Read back of rst by watchdog ++ * MPP[21] NC ++ * MPP[22] GP LED Green GPIO OUT ++ * MPP[23] GP LED Red GPIO OUT ++ * MPP[24] Watchdog NMI# Int OUT ++ * MPP[25] NC ++ * MPP[26] NC ++ * MPP[27] PCI Interrupt A Int IN Connected to P11 ++ * MPP[28] NC ++ * MPP[29] PCI Interrupt B Int IN Connected to P11 ++ * MPP[30] Module reset GPIO OUT Board reset ++ * MPP[31] PCI EReady GPIO IN Connected to P12 ++ */ ++#define CFG_MPP_CONTROL_0 0x00303022 ++#define CFG_MPP_CONTROL_1 0x00000000 ++#define CFG_MPP_CONTROL_2 0x00004000 ++#define CFG_MPP_CONTROL_3 0x00000004 ++#define CFG_GPP_LEVEL_CONTROL 0x280730D0 ++ ++/*---------------------------------------------------------------------- ++ * Initial BAT mappings ++ */ ++ ++/* NOTES: ++ * 1) GUARDED and WRITE_THRU not allowed in IBATS ++ * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT ++ */ ++/* SDRAM */ ++#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) ++#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) ++#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT) ++#define CFG_DBAT0U CFG_IBAT0U ++ ++/* init ram */ ++#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) ++#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) ++#define CFG_DBAT1L CFG_IBAT1L ++#define CFG_DBAT1U CFG_IBAT1U ++ ++/* PCI0, PCI1 in one BAT */ ++#define CFG_IBAT2L BATL_NO_ACCESS ++#define CFG_IBAT2U CFG_DBAT2U ++#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) ++#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) ++ ++/* GT regs, bootrom, all the devices, PCI I/O */ ++#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) ++#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) ++#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) ++#define CFG_DBAT3U CFG_IBAT3U ++ ++#define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) ++#define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP) ++#define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) ++#define CFG_DBAT4U CFG_IBAT4U ++ ++/* set rest out of range for Linux !!!!!!!!!!! */ ++ ++/* IBAT5 and DBAT5 */ ++#define CFG_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) ++#define CFG_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) ++#define CFG_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) ++#define CFG_DBAT5U CFG_IBAT5U ++ ++/* IBAT6 and DBAT6 */ ++#define CFG_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) ++#define CFG_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) ++#define CFG_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) ++#define CFG_DBAT6U CFG_IBAT6U ++ ++/* IBAT7 and DBAT7 */ ++#define CFG_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) ++#define CFG_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) ++#define CFG_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) ++#define CFG_DBAT7U CFG_IBAT7U ++ ++/* ++ * For booting Linux, the board info and command line data ++ * have to be in the first 8 MB of memory, since this is ++ * the maximum mapped by the Linux kernel during initialization. ++ */ ++#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ ++#define CFG_VXWORKS_MAC_PTR 0x42010000 /* use some memory in SRAM that's not used!!! */ ++ ++/*----------------------------------------------------------------------- ++ * Cache Configuration ++ */ ++#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ ++#endif ++ ++/*----------------------------------------------------------------------- ++ * L2CR setup -- make sure this is right for your board! ++ * look in include/mpc74xx.h for the defines used here ++ */ ++#define CFG_L2 ++ ++#if defined (CONFIG_750CX) || defined (CONFIG_750FX) ++#define L2_INIT 0 ++#else ++#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ ++ L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) ++#endif ++ ++#define L2_ENABLE (L2_INIT | L2CR_L2E) ++ ++/* ++ * Internal Definitions ++ * ++ * Boot Flags ++ */ ++#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ ++#define BOOTFLAG_WARM 0x02 /* Software reboot */ ++ ++#endif /* __CONFIG_H */ +diff -Naupr u-boot-1.1.6/include/configs/sequoia.h u-boot-1.1.6-fsl-1/include/configs/sequoia.h +--- u-boot-1.1.6/include/configs/sequoia.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/configs/sequoia.h 2006-11-30 12:34:13.000000000 -0600 +@@ -53,7 +53,7 @@ + + #define CFG_BOOT_BASE_ADDR 0xf0000000 + #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +-#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */ ++#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ + #define CFG_MONITOR_BASE TEXT_BASE + #define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */ + #define CFG_OCM_BASE 0xe0010000 /* ocm */ +@@ -102,6 +102,7 @@ + #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + #else + #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ ++#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */ + #endif + + /*----------------------------------------------------------------------- +@@ -234,10 +235,10 @@ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ +- "rootpath=/opt/eldk/ppc_4xx\0" \ ++ "rootpath=/opt/eldk/ppc_4xxFP\0" \ + "bootfile=/tftpboot/sequoia/uImage\0" \ +- "kernel_addr=FE000000\0" \ +- "ramdisk_addr=FE180000\0" \ ++ "kernel_addr=FC000000\0" \ ++ "ramdisk_addr=FC180000\0" \ + "load=tftp 100000 /tftpboot/sequoia/u-boot.bin\0" \ + "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ + "cp.b 100000 FFFA0000 60000\0" \ +@@ -378,7 +379,7 @@ + #define CFG_NAND_CS 3 /* NAND chip connected to CSx */ + /* Memory Bank 0 (NOR-FLASH) initialization */ + #define CFG_EBC_PB0AP 0x03017300 +-#define CFG_EBC_PB0CR (CFG_FLASH | 0xba000) ++#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000) + + /* Memory Bank 3 (NAND-FLASH) initialization */ + #define CFG_EBC_PB3AP 0x018003c0 +@@ -387,7 +388,7 @@ + #define CFG_NAND_CS 0 /* NAND chip connected to CSx */ + /* Memory Bank 3 (NOR-FLASH) initialization */ + #define CFG_EBC_PB3AP 0x03017300 +-#define CFG_EBC_PB3CR (CFG_FLASH | 0xba000) ++#define CFG_EBC_PB3CR (CFG_FLASH | 0xda000) + + /* Memory Bank 0 (NAND-FLASH) initialization */ + #define CFG_EBC_PB0AP 0x018003c0 +diff -Naupr u-boot-1.1.6/include/configs/TQM5200.h u-boot-1.1.6-fsl-1/include/configs/TQM5200.h +--- u-boot-1.1.6/include/configs/TQM5200.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/configs/TQM5200.h 2006-11-30 12:34:13.000000000 -0600 +@@ -217,43 +217,19 @@ + + #undef CONFIG_BOOTARGS + +-#ifdef CONFIG_STK52XX +-# if defined(CONFIG_TQM5200_B) +-# if defined(CFG_LOWBOOT) +-# define ENV_UPDT \ +- "update=protect off FC000000 FC07FFFF;" \ +- "erase FC000000 FC07FFFF;" \ +- "cp.b 200000 FC000000 ${filesize};" \ +- "protect on FC000000 FC07FFFF\0" +-# else /* highboot */ +-# define ENV_UPDT \ +- "update=protect off FFF00000 FFF7FFFF;" \ +- "erase FFF00000 FFF7FFFF;" \ ++#if defined(CONFIG_TQM5200_B) && !defined(CFG_LOWBOOT) ++# define ENV_UPDT \ ++ "update=protect off FFF00000 +${filesize};" \ ++ "erase FFF00000 +${filesize};" \ + "cp.b 200000 FFF00000 ${filesize};" \ +- "protect on FFF00000 FFF7FFFF\0" +-# endif /* CFG_LOWBOOT */ +-# else /* !CONFIG_TQM5200_B */ +-# define ENV_UPDT \ +- "update=protect off FC000000 FC05FFFF;" \ +- "erase FC000000 FC05FFFF;" \ +- "cp.b 200000 FC000000 ${filesize};" \ +- "protect on FC000000 FC05FFFF\0" +-# endif /* CONFIG_TQM5200_B */ +-#elif defined (CONFIG_CAM5200) +-# define ENV_UPDT \ +- "update=protect off FC000000 FC03FFFF;" \ +- "erase FC000000 FC03FFFF;" \ +- "cp.b 200000 FC000000 ${filesize};" \ +- "protect on FC000000 FC03FFFF\0" +-#elif defined (CONFIG_FO300) ++ "protect on FFF00000 +${filesize}\0" ++#else /* default lowboot configuration */ + # define ENV_UPDT \ +- "update=protect off FC000000 FC05FFFF;" \ +- "erase FC000000 FC05FFFF;" \ ++ "update=protect off FC000000 +${filesize};" \ ++ "erase FC000000 +${filesize};" \ + "cp.b 200000 FC000000 ${filesize};" \ +- "protect on FC000000 FC05FFFF\0" +-#else +-# error "Unknown Carrier Board" +-#endif /* CONFIG_STK52XX */ ++ "protect on FC000000 +${filesize}\0" ++#endif + + #define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ +@@ -432,7 +408,7 @@ + */ + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */ +-#if defined(CONFIG_TQM5200_B) ++#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200) + #define CFG_ENV_SECT_SIZE 0x40000 + #else + #define CFG_ENV_SECT_SIZE 0x20000 +diff -Naupr u-boot-1.1.6/include/configs/TQM834x.h u-boot-1.1.6-fsl-1/include/configs/TQM834x.h +--- u-boot-1.1.6/include/configs/TQM834x.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/configs/TQM834x.h 2006-11-10 11:24:30.000000000 -0600 +@@ -37,10 +37,11 @@ + #define CONFIG_E300 1 /* E300 Family */ + #define CONFIG_MPC83XX 1 /* MPC83XX family */ + #define CONFIG_MPC834X 1 /* MPC834X specific */ ++#define CONFIG_MPC8349 1 /* MPC8349 specific */ + #define CONFIG_TQM834X 1 /* TQM834X board specific */ + + /* IMMR Base Addres Register, use Freescale default: 0xff400000 */ +-#define CFG_IMMRBAR 0xff400000 ++#define CFG_IMMR 0xff400000 + + /* System clock. Primary input clock when in PCI host mode */ + #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ +@@ -56,6 +57,17 @@ + */ + #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) + ++#define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK)) ++#define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */ ++#define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */ ++#define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */ ++#define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */ ++#define CFG_SCCR_VAL ( CFG_SCCR_INIT \ ++ | CFG_SCCR_TSEC1CM \ ++ | CFG_SCCR_TSEC2CM \ ++ | CFG_SCCR_ENCCM \ ++ | CFG_SCCR_USBCM ) ++ + /* board pre init: do not call, nothing to do */ + #undef CONFIG_BOARD_EARLY_INIT_F + +@@ -83,6 +95,7 @@ + #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ + #undef CFG_FLASH_CHECKSUM + #define CFG_FLASH_BASE 0x80000000 /* start of FLASH */ ++#define CFG_FLASH_SIZE 8 /* FLASH size in MB */ + + /* buffered writes in the AMD chip set is not supported yet */ + #undef CFG_FLASH_USE_BUFFER_WRITE +@@ -197,14 +210,15 @@ extern int tqm834x_num_flash_banks; + #define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +-#define CFG_NS16550_COM1 (CFG_IMMRBAR + 0x4500) +-#define CFG_NS16550_COM2 (CFG_IMMRBAR + 0x4600) ++#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) ++#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) + + /* + * I2C + */ + #define CONFIG_HARD_I2C /* I2C with hardware support */ + #undef CONFIG_SOFT_I2C /* I2C bit-banged */ ++#define CONFIG_FSL_I2C + #define CFG_I2C_SPEED 400000 /* I2C speed: 400KHz */ + #define CFG_I2C_SLAVE 0x7F /* slave address */ + #define CFG_I2C_OFFSET 0x3000 +@@ -235,9 +249,9 @@ extern int tqm834x_num_flash_banks; + #define CONFIG_MII + + #define CFG_TSEC1_OFFSET 0x24000 +-#define CFG_TSEC1 (CFG_IMMRBAR + CFG_TSEC1_OFFSET) ++#define CFG_TSEC1 (CFG_IMMR + CFG_TSEC1_OFFSET) + #define CFG_TSEC2_OFFSET 0x25000 +-#define CFG_TSEC2 (CFG_IMMRBAR + CFG_TSEC2_OFFSET) ++#define CFG_TSEC2 (CFG_IMMR + CFG_TSEC2_OFFSET) + + #if defined(CONFIG_TSEC_ENET) + +@@ -460,8 +474,8 @@ extern int tqm834x_num_flash_banks; + #endif + + /* IMMRBAR */ +-#define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +-#define CFG_IBAT6U (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP) ++#define CFG_IBAT6L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) ++#define CFG_IBAT6U (CFG_IMMR | BATU_BL_1M | BATU_VS | BATU_VP) + + /* FLASH */ + #define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +diff -Naupr u-boot-1.1.6/include/configs/v38b.h u-boot-1.1.6-fsl-1/include/configs/v38b.h +--- u-boot-1.1.6/include/configs/v38b.h 1969-12-31 18:00:00.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/configs/v38b.h 2006-11-30 12:34:13.000000000 -0600 +@@ -0,0 +1,343 @@ ++/* ++ * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering, ++ * wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this project. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the Free ++ * Software Foundation; either version 2 of the License, or (at your option) ++ * any later version. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., 59 ++ * Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++/* ++ * High Level Configuration Options ++ * (easy to change) ++ */ ++#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ ++#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ ++#define CONFIG_V38B 1 /* ...on V38B board */ ++#define CFG_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */ ++ ++#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ ++#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ ++ ++#undef CONFIG_HW_WATCHDOG /* don't use watchdog */ ++ ++#define CONFIG_NETCONSOLE 1 ++ ++#define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */ ++ ++#define CFG_XLB_PIPELINING 1 /* gives better performance */ ++ ++#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ ++#define BOOTFLAG_WARM 0x02 /* Software reboot */ ++ ++#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ ++#endif ++ ++/* ++ * Serial console configuration ++ */ ++#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ ++#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ ++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } ++ ++/* ++ * DDR ++ */ ++#define SDRAM_DDR 1 /* is DDR */ ++/* Settings for XLB = 132 MHz */ ++#define SDRAM_MODE 0x018D0000 ++#define SDRAM_EMODE 0x40090000 ++#define SDRAM_CONTROL 0x704f0f00 ++#define SDRAM_CONFIG1 0x73722930 ++#define SDRAM_CONFIG2 0x47770000 ++#define SDRAM_TAPDELAY 0x10000000 ++ ++/* ++ * PCI - no suport ++ */ ++#undef CONFIG_PCI ++ ++/* ++ * Partitions ++ */ ++#define CONFIG_MAC_PARTITION 1 ++#define CONFIG_DOS_PARTITION 1 ++ ++/* ++ * USB ++ */ ++#define CONFIG_USB_OHCI ++#define CONFIG_USB_STORAGE ++#define CONFIG_USB_CLOCK 0x0001BBBB ++#define CONFIG_USB_CONFIG 0x00001000 ++ ++/* ++ * Supported commands ++ */ ++#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ ++ CFG_CMD_FAT | \ ++ CFG_CMD_I2C | \ ++ CFG_CMD_IDE | \ ++ CFG_CMD_PING | \ ++ CFG_CMD_DHCP | \ ++ CFG_CMD_DIAG | \ ++ CFG_CMD_IRQ | \ ++ CFG_CMD_JFFS2 | \ ++ CFG_CMD_MII | \ ++ CFG_CMD_SDRAMi | \ ++ CFG_CMD_DATE | \ ++ CFG_CMD_USB | \ ++ CFG_CMD_FAT) ++ ++#define CONFIG_TIMESTAMP /* Print image info with timestamp */ ++ ++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ ++#include ++ ++/* ++ * Boot low with 16 MB Flash ++ */ ++#define CFG_LOWBOOT 1 ++#define CFG_LOWBOOT16 1 ++ ++/* ++ * Autobooting ++ */ ++#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ ++ ++#define CONFIG_PREBOOT "echo;" \ ++ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ ++ "echo" ++ ++#undef CONFIG_BOOTARGS ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "bootcmd=run net_nfs\0" \ ++ "bootdelay=3\0" \ ++ "baudrate=115200\0" \ ++ "preboot=echo;echo Type \"run flash_nfs\" to mount root " \ ++ "filesystem over NFS; echo\0" \ ++ "netdev=eth0\0" \ ++ "ramargs=setenv bootargs root=/dev/ram rw\0" \ ++ "addip=setenv bootargs $(bootargs) " \ ++ "ip=$(ipaddr):$(serverip):$(gatewayip):" \ ++ "$(netmask):$(hostname):$(netdev):off panic=1\0" \ ++ "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ ++ "flash_self=run ramargs addip;bootm $(kernel_addr) " \ ++ "$(ramdisk_addr)\0" \ ++ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ ++ "nfsargs=setenv bootargs root=/dev/nfs rw " \ ++ "nfsroot=$(serverip):$(rootpath)\0" \ ++ "hostname=v38b\0" \ ++ "ethact=FEC ETHERNET\0" \ ++ "rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \ ++ "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \ ++ "cp.b 200000 ff000000 $(filesize);" \ ++ "prot on ff000000 ff03ffff\0" \ ++ "load=tftp 200000 $(u-boot)\0" \ ++ "netmask=255.255.0.0\0" \ ++ "ipaddr=192.168.160.18\0" \ ++ "serverip=192.168.1.1\0" \ ++ "ethaddr=00:e0:ee:00:05:2e\0" \ ++ "bootfile=/tftpboot/v38b/uImage\0" \ ++ "u-boot=/tftpboot/v38b/u-boot.bin\0" \ ++ "" ++ ++#define CONFIG_BOOTCOMMAND "run net_nfs" ++ ++#if defined(CONFIG_MPC5200) ++/* ++ * IPB Bus clocking configuration. ++ */ ++#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ ++#endif ++ ++/* ++ * I2C configuration ++ */ ++#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ ++#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ ++#define CFG_I2C_SPEED 100000 /* 100 kHz */ ++#define CFG_I2C_SLAVE 0x7F ++ ++/* ++ * EEPROM configuration ++ */ ++#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ ++#define CFG_I2C_EEPROM_ADDR_LEN 1 ++#define CFG_EEPROM_PAGE_WRITE_BITS 3 ++#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 ++ ++/* ++ * RTC configuration ++ */ ++#define CFG_I2C_RTC_ADDR 0x51 ++ ++/* ++ * Flash configuration - use CFI driver ++ */ ++#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ ++#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ ++#define CFG_FLASH_CFI_AMD_RESET 1 ++#define CFG_FLASH_BASE 0xFF000000 ++#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ ++#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } ++#define CFG_FLASH_SIZE 0x01000000 /* 16 MiB */ ++#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ ++#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ ++ ++/* ++ * Environment settings ++ */ ++#define CFG_ENV_IS_IN_FLASH 1 ++#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000) ++#define CFG_ENV_SIZE 0x10000 ++#define CFG_ENV_SECT_SIZE 0x10000 ++#define CONFIG_ENV_OVERWRITE 1 ++ ++/* ++ * Memory map ++ */ ++#define CFG_MBAR 0xF0000000 ++#define CFG_SDRAM_BASE 0x00000000 ++#define CFG_DEFAULT_MBAR 0x80000000 ++ ++/* Use SRAM until RAM will be available */ ++#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM ++#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ ++ ++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ ++#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) ++#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET ++ ++#define CFG_MONITOR_BASE TEXT_BASE ++#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) ++# define CFG_RAMBOOT 1 ++#endif ++ ++#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */ ++#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */ ++#define CFG_BOOTMAPSZ (8 << 20) /* Linux initial memory map */ ++ ++/* ++ * Ethernet configuration ++ */ ++#define CONFIG_MPC5xxx_FEC 1 ++#define CONFIG_PHY_ADDR 0x00 ++#define CONFIG_MII 1 ++ ++/* ++ * GPIO configuration ++ */ ++#define CFG_GPS_PORT_CONFIG 0x90001404 ++ ++/* ++ * Miscellaneous configurable options ++ */ ++#define CFG_LONGHELP /* undef to save memory */ ++#define CFG_PROMPT "=> " /* Monitor Command Prompt */ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ ++#else ++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ ++#endif ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ ++#define CFG_MAXARGS 16 /* max number of command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ ++ ++#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ ++#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ ++ ++#define CFG_LOAD_ADDR 0x100000 /* default load address */ ++ ++#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ ++ ++/* ++ * Various low-level settings ++ */ ++#define CFG_HID0_INIT HID0_ICE | HID0_ICFI ++#define CFG_HID0_FINAL HID0_ICE ++ ++#define CFG_BOOTCS_START CFG_FLASH_BASE ++#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE ++#define CFG_BOOTCS_CFG 0x00047801 ++#define CFG_CS0_START CFG_FLASH_BASE ++#define CFG_CS0_SIZE CFG_FLASH_SIZE ++ ++#define CFG_CS_BURST 0x00000000 ++#define CFG_CS_DEADCYCLE 0x33333333 ++ ++#define CFG_RESET_ADDRESS 0xff000000 ++ ++/* ++ * IDE/ATA (supports IDE harddisk) ++ */ ++#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ ++#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ ++#undef CONFIG_IDE_LED /* LED for ide not supported */ ++ ++#define CONFIG_IDE_RESET /* reset for ide supported */ ++#define CONFIG_IDE_PREINIT ++ ++#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ ++#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ ++ ++#define CFG_ATA_IDE0_OFFSET 0x0000 ++ ++#define CFG_ATA_BASE_ADDR MPC5XXX_ATA ++ ++#define CFG_ATA_DATA_OFFSET (0x0060) /* data I/O offset */ ++ ++#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) /* normal register accesses offset */ ++ ++#define CFG_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */ ++ ++#define CFG_ATA_STRIDE 4 /* Interval between registers */ ++ ++/* ++ * Status LED ++ */ ++#define CONFIG_STATUS_LED /* Status LED enabled */ ++#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ ++ ++#define CFG_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */ ++#ifndef __ASSEMBLY__ ++typedef unsigned int led_id_t; ++ ++#define __led_toggle(_msk) \ ++ do { \ ++ *((volatile long *) (CFG_LED_BASE)) ^= (_msk); \ ++ } while(0) ++ ++#define __led_set(_msk, _st) \ ++ do { \ ++ if ((_st)) \ ++ *((volatile long *) (CFG_LED_BASE)) &= ~(_msk); \ ++ else \ ++ *((volatile long *) (CFG_LED_BASE)) |= (_msk); \ ++ } while(0) ++ ++#define __led_init(_msk, st) \ ++ do { \ ++ *((volatile long *) (CFG_LED_BASE)) |= 0x34; \ ++ } while(0) ++#endif /* __ASSEMBLY__ */ ++ ++#endif /* __CONFIG_H */ +diff -Naupr u-boot-1.1.6/include/configs/V38B.h u-boot-1.1.6-fsl-1/include/configs/V38B.h +--- u-boot-1.1.6/include/configs/V38B.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/configs/V38B.h 1969-12-31 18:00:00.000000000 -0600 +@@ -1,368 +0,0 @@ +-/* +- * (C) Copyright 2003-2004 Wolfgang Denk, DENX Software Engineering, +- * wd@denx.de. +- * +- * See file CREDITS for list of people who contributed to this project. +- * +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License as published by the Free +- * Software Foundation; either version 2 of the License, or (at your option) +- * any later version. +- * +- * This program is distributed in the hope that it will be useful, but WITHOUT +- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +- * for more details. +- * +- * You should have received a copy of the GNU General Public License along +- * with this program; if not, write to the Free Software Foundation, Inc., 59 +- * Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-#ifndef __CONFIG_H +-#define __CONFIG_H +- +-#if 0 +-#define DEBUG 0xFFF +-#endif +- +-#if 0 +-#define DEBUG 0x01 +-#endif +- +-/* +- * High Level Configuration Options +- * (easy to change) +-*/ +- +-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +-#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ +-#define CONFIG_V38B 1 /* ... on V38B board */ +-#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ +- +-#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ +-#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ +-#define CONFIG_HW_WATCHDOG 1 /* has watchdog */ +- +-#define CONFIG_NETCONSOLE 1 +- +-#define CONFIG_BOARD_EARLY_INIT_R 1 /* make flash read/write */ +- +-#define CFG_XLB_PIPELINING 1 /* gives better performance */ +- +- +-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +-#define BOOTFLAG_WARM 0x02 /* Software reboot */ +- +-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +-#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +-#endif +- +-/* +- * Serial console configuration +- */ +-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +-#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +- +- +-/* +- * DDR +- */ +-#define SDRAM_DDR 1 /* is DDR */ +-/* Settings for XLB = 132 MHz */ +-#define SDRAM_MODE 0x018D0000 +-#define SDRAM_EMODE 0x40090000 +-#define SDRAM_CONTROL 0x704f0f00 +-#define SDRAM_CONFIG1 0x73722930 +-#define SDRAM_CONFIG2 0x47770000 +-#define SDRAM_TAPDELAY 0x10000000 +- +- +-/* +- * PCI - no suport +- */ +-#undef CONFIG_PCI +- +-/* +- * Partitions +- */ +-#define CONFIG_MAC_PARTITION 1 +-#define CONFIG_DOS_PARTITION 1 +- +-/* +- * USB +- */ +-#define CONFIG_USB_OHCI +-#define CONFIG_USB_STORAGE +- +-#define CONFIG_TIMESTAMP /* Print image info with timestamp */ +- +-/* +- * Supported commands +- */ +-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ +- CFG_CMD_FAT | \ +- CFG_CMD_I2C | \ +- CFG_CMD_IDE | \ +- CFG_CMD_PING | \ +- CFG_CMD_DHCP | \ +- CFG_CMD_DIAG | \ +- CFG_CMD_IRQ | \ +- CFG_CMD_JFFS2 | \ +- CFG_CMD_MII | \ +- CFG_CMD_SDRAMi | \ +- CFG_CMD_DATE | \ +- CFG_CMD_USB | \ +- CFG_CMD_FAT) +- +-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +-#include +- +-/* +- * Boot low with 16 MB Flash +- */ +-# define CFG_LOWBOOT 1 +-# define CFG_LOWBOOT16 1 +- +-/* +- * Autobooting +- */ +-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +- +-#define CONFIG_PREBOOT "echo;" \ +- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ +- "echo" +- +-#undef CONFIG_BOOTARGS +- +-#define CONFIG_EXTRA_ENV_SETTINGS \ +- "netdev=eth0\0" \ +- "devno=5\0" \ +- "hostname=V38B_$(devno)\0" \ +- "ipaddr=10.100.99.$(devno)\0" \ +- "netmask=255.255.0.0\0" \ +- "serverip=10.100.10.90\0" \ +- "gatewayip=10.100.254.254\0" \ +- "ramargs=setenv bootargs root=/dev/ram rw\0" \ +- "rootpath=/opt/eldk/ppc_6xx\0" \ +- "bootfile=mpc5200/uImage\0" \ +- "bootcmd=run net_nfs\0" \ +- "addip=setenv bootargs $(bootargs) " \ +- "ip=$(ipaddr):$(serverip):$(gatewayip):" \ +- "$(netmask):$(hostname):$(netdev):off panic=1\0" \ +- "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ +- "flash_self=run ramargs addip;bootm $(kernel_addr) " \ +- "$(ramdisk_addr)\0" \ +- "net_nfs=tftp 200000 $(bootfile);run nfsargs " \ +- "addip;bootm\0" \ +- "nfsargs=setenv bootargs root=/dev/nfs rw " \ +- "nfsroot=$(serverip):$(rootpath)\0" \ +- "" +- +-#define CONFIG_BOOTCOMMAND "run net_nfs" +- +-#if defined(CONFIG_MPC5200) +-/* +- * IPB Bus clocking configuration. +- */ +-#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +-#endif +-/* +- * I2C configuration +- */ +-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +-#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ +- +-#define CFG_I2C_SPEED 100000 /* 100 kHz */ +-#define CFG_I2C_SLAVE 0x7F +- +-/* +- * EEPROM configuration +- */ +-#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +-#define CFG_I2C_EEPROM_ADDR_LEN 1 +-#define CFG_EEPROM_PAGE_WRITE_BITS 3 +-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 +- +-/* +- * RTC configuration +- */ +-#define CFG_I2C_RTC_ADDR 0x51 +- +-/* +- * Flash configuration - use CFI driver +- */ +-#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +-#define CFG_FLASH_CFI_AMD_RESET 1 +-#define CFG_FLASH_BASE 0xFF000000 +-#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ +-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +-#define CFG_FLASH_SIZE 0x01000000 /* 16 MiB */ +-#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ +-#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ +- +-/* +- * Environment settings +- */ +-#define CFG_ENV_IS_IN_FLASH 1 +-#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000) +-#define CFG_ENV_SIZE 0x10000 +-#define CFG_ENV_SECT_SIZE 0x10000 +-#define CONFIG_ENV_OVERWRITE 1 +- +-/* +- * Memory map +- */ +-#define CFG_MBAR 0xF0000000 +-#define CFG_SDRAM_BASE 0x00000000 +-#define CFG_DEFAULT_MBAR 0x80000000 +- +-/* Use SRAM until RAM will be available */ +-#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +-#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ +- +- +-#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +- +-#define CFG_MONITOR_BASE TEXT_BASE +-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +-# define CFG_RAMBOOT 1 +-#endif +- +-#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +- +-/* +- * Ethernet configuration +- */ +-#define CONFIG_MPC5xxx_FEC 1 +-#define CONFIG_PHY_ADDR 0x00 +-#define CONFIG_MII 1 +- +-/* +- * GPIO configuration +- */ +-#define CFG_GPS_PORT_CONFIG 0x90000404 +- +-/* +- * Miscellaneous configurable options +- */ +-#define CFG_LONGHELP /* undef to save memory */ +-#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +-#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +-#else +-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +-#endif +-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +-#define CFG_MAXARGS 16 /* max number of command args */ +-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +- +-#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +-#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ +- +-#define CFG_LOAD_ADDR 0x100000 /* default load address */ +- +-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +- +-/* +- * Various low-level settings +- */ +-#if defined(CONFIG_MPC5200) +-#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +-#define CFG_HID0_FINAL HID0_ICE +-#else +-#define CFG_HID0_INIT 0 +-#define CFG_HID0_FINAL 0 +-#endif +- +- +-#define CFG_BOOTCS_START CFG_FLASH_BASE +-#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +-#define CFG_BOOTCS_CFG 0x00047801 +-#define CFG_CS0_START CFG_FLASH_BASE +-#define CFG_CS0_SIZE CFG_FLASH_SIZE +- +-#define CFG_CS_BURST 0x00000000 +-#define CFG_CS_DEADCYCLE 0x33333333 +- +-#define CFG_RESET_ADDRESS 0xff000000 +- +-/*----------------------------------------------------------------------- +- * USB stuff +- *----------------------------------------------------------------------- +- */ +-#define CONFIG_USB_CLOCK 0x0001BBBB +-#define CONFIG_USB_CONFIG 0x00001000 +- +- +-/*----------------------------------------------------------------------- +- * IDE/ATA stuff Supports IDE harddisk +- *----------------------------------------------------------------------- +- */ +- +-#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ +- +-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +-#undef CONFIG_IDE_LED /* LED for ide not supported */ +- +-#define CONFIG_IDE_RESET /* reset for ide supported */ +-#define CONFIG_IDE_PREINIT +- +-#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +-#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ +- +-#define CFG_ATA_IDE0_OFFSET 0x0000 +- +-#define CFG_ATA_BASE_ADDR MPC5XXX_ATA +- +-/* Offset for data I/O */ +-#define CFG_ATA_DATA_OFFSET (0x0060) +- +-/* Offset for normal register accesses */ +-#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) +- +-/* Offset for alternate registers */ +-#define CFG_ATA_ALT_OFFSET (0x005C) +- +-/* Interval between registers */ +-#define CFG_ATA_STRIDE 4 +- +-/* Status LED */ +- +-#define CONFIG_STATUS_LED /* Status LED enabled */ +-#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ +- +-#define CFG_LED_BASE (0xf0000600 + 0x70) /* Timer 7 GPIO */ +- +-#ifndef __ASSEMBLY__ +-/* LEDs */ +-typedef unsigned int led_id_t; +- +-#define __led_toggle(_msk) \ +- do { \ +- *((volatile long *) (CFG_LED_BASE)) ^= (_msk); \ +- } while(0) +- +-#define __led_set(_msk, _st) \ +- do { \ +- if ((_st)) \ +- *((volatile long *) (CFG_LED_BASE)) &= ~(_msk); \ +- else \ +- *((volatile long *) (CFG_LED_BASE)) |= (_msk); \ +- } while(0) +- +-#define __led_init(_msk, st) \ +- { \ +- *((volatile long *) (CFG_LED_BASE)) |= 0x34; \ +- } +- +-#endif +- +-#endif /* __CONFIG_H */ +diff -Naupr u-boot-1.1.6/include/configs/yellowstone.h u-boot-1.1.6-fsl-1/include/configs/yellowstone.h +--- u-boot-1.1.6/include/configs/yellowstone.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/configs/yellowstone.h 2006-11-30 12:34:13.000000000 -0600 +@@ -37,6 +37,7 @@ + + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ ++#define CONFIG_BOARD_RESET 1 /* call board_reset() */ + + /*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the +diff -Naupr u-boot-1.1.6/include/configs/yosemite.h u-boot-1.1.6-fsl-1/include/configs/yosemite.h +--- u-boot-1.1.6/include/configs/yosemite.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/configs/yosemite.h 2006-11-30 12:34:13.000000000 -0600 +@@ -37,6 +37,7 @@ + + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ ++#define CONFIG_BOARD_RESET 1 /* call board_reset() */ + + /*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the +diff -Naupr u-boot-1.1.6/include/environment.h u-boot-1.1.6-fsl-1/include/environment.h +--- u-boot-1.1.6/include/environment.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/environment.h 2006-11-30 12:34:13.000000000 -0600 +@@ -79,8 +79,7 @@ + # ifdef CFG_ENV_OFFSET_REDUND + # define CFG_REDUNDAND_ENVIRONMENT + # endif +-# if defined(CONFIG_NAND_U_BOOT) +-/* Use embedded environment in NAND boot versions */ ++# ifdef CFG_ENV_IS_EMBEDDED + # define ENV_IS_EMBEDDED 1 + # endif + #endif /* CFG_ENV_IS_IN_NAND */ +diff -Naupr u-boot-1.1.6/include/flash.h u-boot-1.1.6-fsl-1/include/flash.h +--- u-boot-1.1.6/include/flash.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/flash.h 2006-11-30 12:34:13.000000000 -0600 +@@ -43,9 +43,14 @@ typedef struct { + ulong write_tout; /* maximum write timeout */ + ulong buffer_write_tout; /* maximum buffer write timeout */ + ushort vendor; /* the primary vendor id */ +- ushort cmd_reset; /* Vendor specific reset command */ ++ ushort cmd_reset; /* vendor specific reset command */ + ushort interface; /* used for x8/x16 adjustments */ + ushort legacy_unlock; /* support Intel legacy (un)locking */ ++ uchar manufacturer_id; /* manufacturer id */ ++ ushort device_id; /* device id */ ++ ushort device_id2; /* extended device id */ ++ ushort ext_addr; /* extended query table address */ ++ ushort cfi_version; /* cfi version */ + #endif + } flash_info_t; + +@@ -439,6 +444,7 @@ extern void flash_read_factory_serial(fl + #define FLASH_MAN_MT 0x00400000 + #define FLASH_MAN_SHARP 0x00500000 + #define FLASH_MAN_ATM 0x00600000 ++#define FLASH_MAN_CFI 0x01000000 + + + #define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */ +diff -Naupr u-boot-1.1.6/include/i2c.h u-boot-1.1.6-fsl-1/include/i2c.h +--- u-boot-1.1.6/include/i2c.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/i2c.h 2006-11-10 11:24:30.000000000 -0600 +@@ -82,4 +82,49 @@ int i2c_write(uchar chip, uint addr, int + uchar i2c_reg_read (uchar chip, uchar reg); + void i2c_reg_write(uchar chip, uchar reg, uchar val); + ++/* ++ * Functions for setting the current I2C bus and its speed ++ */ ++ ++/* ++ * i2c_set_bus_num: ++ * ++ * Change the active I2C bus. Subsequent read/write calls will ++ * go to this one. ++ * ++ * bus - bus index, zero based ++ * ++ * Returns: 0 on success, not 0 on failure ++ * ++ */ ++int i2c_set_bus_num(unsigned int bus); ++ ++/* ++ * i2c_get_bus_num: ++ * ++ * Returns index of currently active I2C bus. Zero-based. ++ */ ++ ++unsigned int i2c_get_bus_num(void); ++ ++/* ++ * i2c_set_bus_speed: ++ * ++ * Change the speed of the active I2C bus ++ * ++ * speed - bus speed in Hz ++ * ++ * Returns: 0 on success, not 0 on failure ++ * ++ */ ++int i2c_set_bus_speed(unsigned int); ++ ++/* ++ * i2c_get_bus_speed: ++ * ++ * Returns speed of currently active I2C bus in Hz ++ */ ++ ++unsigned int i2c_get_bus_speed(void); ++ + #endif /* _I2C_H_ */ +diff -Naupr u-boot-1.1.6/include/ioports.h u-boot-1.1.6-fsl-1/include/ioports.h +--- u-boot-1.1.6/include/ioports.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/ioports.h 2006-12-06 10:33:49.000000000 -0600 +@@ -53,3 +53,13 @@ typedef struct { + * like the table in the 8260UM (and in the hymod manuals). + */ + extern const iop_conf_t iop_conf_tab[4][32]; ++ ++typedef struct { ++ unsigned char port; ++ unsigned char pin; ++ int dir; ++ int open_drain; ++ int assign; ++} qe_iop_conf_t; ++ ++#define QE_IOP_TAB_END (-1) +diff -Naupr u-boot-1.1.6/include/mpc5xxx.h u-boot-1.1.6-fsl-1/include/mpc5xxx.h +--- u-boot-1.1.6/include/mpc5xxx.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/mpc5xxx.h 2006-11-10 11:24:30.000000000 -0600 +@@ -188,7 +188,14 @@ + #define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000) + #define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004) + #define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008) +-#define MPC5XXX_WU_GPIO_DATA (MPC5XXX_WU_GPIO + 0x000c) ++#define MPC5XXX_WU_GPIO_DATA_O (MPC5XXX_WU_GPIO + 0x000c) ++#define MPC5XXX_WU_GPIO_DATA_I (MPC5XXX_WU_GPIO + 0x0020) ++ ++/* GPIO pins */ ++#define GPIO_WKUP_7 0x80000000UL ++#define GPIO_PSC6_0 0x10000000UL ++#define GPIO_PSC3_9 0x04000000UL ++#define GPIO_PSC1_4 0x01000000UL + + /* PCI registers */ + #define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04) +diff -Naupr u-boot-1.1.6/include/mpc83xx.h u-boot-1.1.6-fsl-1/include/mpc83xx.h +--- u-boot-1.1.6/include/mpc83xx.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/mpc83xx.h 2006-11-10 11:24:30.000000000 -0600 +@@ -1,5 +1,5 @@ + /* +- * Copyright 2004 Freescale Semiconductor, Inc. ++ * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. +@@ -8,16 +8,6 @@ + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, +- * MA 02111-1307 USA + */ + + /* +@@ -29,6 +19,7 @@ + #ifndef __MPC83XX_H__ + #define __MPC83XX_H__ + ++#include + #if defined(CONFIG_E300) + #include + #endif +@@ -85,6 +76,33 @@ + #define LBLAWBAR3 0x0038 + #define LBLAWAR3 0x003C + ++/* ++ * The device ID and revision numbers ++ */ ++#define SPR_8349E_REV10 0x80300100 ++#define SPR_8349_REV10 0x80310100 ++#define SPR_8347E_REV10_TBGA 0x80320100 ++#define SPR_8347_REV10_TBGA 0x80330100 ++#define SPR_8347E_REV10_PBGA 0x80340100 ++#define SPR_8347_REV10_PBGA 0x80350100 ++#define SPR_8343E_REV10 0x80360100 ++#define SPR_8343_REV10 0x80370100 ++ ++#define SPR_8349E_REV11 0x80300101 ++#define SPR_8349_REV11 0x80310101 ++#define SPR_8347E_REV11_TBGA 0x80320101 ++#define SPR_8347_REV11_TBGA 0x80330101 ++#define SPR_8347E_REV11_PBGA 0x80340101 ++#define SPR_8347_REV11_PBGA 0x80350101 ++#define SPR_8343E_REV11 0x80360101 ++#define SPR_8343_REV11 0x80370101 ++ ++#define SPR_8360E_REV10 0x80480010 ++#define SPR_8360_REV10 0x80490010 ++#define SPR_8360E_REV11 0x80480011 ++#define SPR_8360_REV11 0x80490011 ++#define SPR_8360E_REV12 0x80480012 ++#define SPR_8360_REV12 0x80490012 + + /* + * Base Registers & Option Registers +@@ -116,9 +134,17 @@ + #define BR_MS_UPMA 0x00000080 /* UPMA */ + #define BR_MS_UPMB 0x000000A0 /* UPMB */ + #define BR_MS_UPMC 0x000000C0 /* UPMC */ ++#if defined (CONFIG_MPC8360) ++#define BR_ATOM 0x0000000C ++#define BR_ATOM_SHIFT 2 ++#endif + #define BR_V 0x00000001 + #define BR_V_SHIFT 0 ++#if defined (CONFIG_MPC8349) + #define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V) ++#elif defined (CONFIG_MPC8360) ++#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_ATOM|BR_V) ++#endif + + #define OR0 0x5004 + #define OR1 0x500C +@@ -201,14 +227,21 @@ + #define HRCWH_PCI_AGENT 0x00000000 + #define HRCWH_PCI_HOST 0x80000000 + ++#if defined (CONFIG_MPC8349) + #define HRCWH_32_BIT_PCI 0x00000000 + #define HRCWH_64_BIT_PCI 0x40000000 ++#endif + + #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 + #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 + ++#if defined (CONFIG_MPC8349) + #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 + #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 ++#elif defined (CONFIG_MPC8360) ++#define HRCWH_PCICKDRV_DISABLE 0x00000000 ++#define HRCWH_PCICKDRV_ENABLE 0x10000000 ++#endif + + #define HRCWH_CORE_DISABLE 0x08000000 + #define HRCWH_CORE_ENABLE 0x00000000 +@@ -225,11 +258,14 @@ + + #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 + #define HRCWH_ROM_LOC_PCI1 0x00100000 ++#if defined (CONFIG_MPC8349) + #define HRCWH_ROM_LOC_PCI2 0x00200000 ++#endif + #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 + #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 + #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 + ++#if defined (CONFIG_MPC8349) + #define HRCWH_TSEC1M_IN_RGMII 0x00000000 + #define HRCWH_TSEC1M_IN_RTBI 0x00004000 + #define HRCWH_TSEC1M_IN_GMII 0x00008000 +@@ -239,10 +275,22 @@ + #define HRCWH_TSEC2M_IN_RTBI 0x00001000 + #define HRCWH_TSEC2M_IN_GMII 0x00002000 + #define HRCWH_TSEC2M_IN_TBI 0x00003000 ++#endif ++ ++#if defined (CONFIG_MPC8360) ++#define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 ++#define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 ++#endif + + #define HRCWH_BIG_ENDIAN 0x00000000 + #define HRCWH_LITTLE_ENDIAN 0x00000008 + ++#define HRCWH_LALE_NORMAL 0x00000000 ++#define HRCWH_LALE_EARLY 0x00000004 ++ ++#define HRCWH_LDP_SET 0x00000000 ++#define HRCWH_LDP_CLEAR 0x00000002 ++ + /* + * Hard Reset Configration Word - Low + */ +@@ -281,6 +329,47 @@ + #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 + #define HRCWL_CORE_TO_CSB_3X1 0x00060000 + ++#if defined (CONFIG_MPC8360) ++#define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 ++#define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 ++#define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 ++ ++#define HRCWL_CE_PLL_DIV_1X1 0x00000000 ++#define HRCWL_CE_PLL_DIV_2X1 0x00000020 ++ ++#define HRCWL_CE_TO_PLL_1X16_ 0x00000000 ++#define HRCWL_CE_TO_PLL_1X2 0x00000002 ++#define HRCWL_CE_TO_PLL_1X3 0x00000003 ++#define HRCWL_CE_TO_PLL_1X4 0x00000004 ++#define HRCWL_CE_TO_PLL_1X5 0x00000005 ++#define HRCWL_CE_TO_PLL_1X6 0x00000006 ++#define HRCWL_CE_TO_PLL_1X7 0x00000007 ++#define HRCWL_CE_TO_PLL_1X8 0x00000008 ++#define HRCWL_CE_TO_PLL_1X9 0x00000009 ++#define HRCWL_CE_TO_PLL_1X10 0x0000000A ++#define HRCWL_CE_TO_PLL_1X11 0x0000000B ++#define HRCWL_CE_TO_PLL_1X12 0x0000000C ++#define HRCWL_CE_TO_PLL_1X13 0x0000000D ++#define HRCWL_CE_TO_PLL_1X14 0x0000000E ++#define HRCWL_CE_TO_PLL_1X15 0x0000000F ++#define HRCWL_CE_TO_PLL_1X16 0x00000010 ++#define HRCWL_CE_TO_PLL_1X17 0x00000011 ++#define HRCWL_CE_TO_PLL_1X18 0x00000012 ++#define HRCWL_CE_TO_PLL_1X19 0x00000013 ++#define HRCWL_CE_TO_PLL_1X20 0x00000014 ++#define HRCWL_CE_TO_PLL_1X21 0x00000015 ++#define HRCWL_CE_TO_PLL_1X22 0x00000016 ++#define HRCWL_CE_TO_PLL_1X23 0x00000017 ++#define HRCWL_CE_TO_PLL_1X24 0x00000018 ++#define HRCWL_CE_TO_PLL_1X25 0x00000019 ++#define HRCWL_CE_TO_PLL_1X26 0x0000001A ++#define HRCWL_CE_TO_PLL_1X27 0x0000001B ++#define HRCWL_CE_TO_PLL_1X28 0x0000001C ++#define HRCWL_CE_TO_PLL_1X29 0x0000001D ++#define HRCWL_CE_TO_PLL_1X30 0x0000001E ++#define HRCWL_CE_TO_PLL_1X31 0x0000001F ++#endif ++ + /* + * LCRR - Clock Ratio Register (10.3.1.16) + */ +@@ -310,4 +399,31 @@ + #define LCRR_CLKDIV_8 0x00000008 + #define LCRR_CLKDIV_SHIFT 0 + ++/* ++ * SCCR-System Clock Control Register ++ */ ++#define SCCR_TSEC1CM_0 0x00000000 ++#define SCCR_TSEC1CM_1 0x40000000 ++#define SCCR_TSEC1CM_2 0x80000000 ++#define SCCR_TSEC1CM_3 0xC0000000 ++#define SCCR_TSEC2CM_0 0x00000000 ++#define SCCR_TSEC2CM_1 0x10000000 ++#define SCCR_TSEC2CM_2 0x20000000 ++#define SCCR_TSEC2CM_3 0x30000000 ++#define SCCR_ENCCM_0 0x00000000 ++#define SCCR_ENCCM_1 0x01000000 ++#define SCCR_ENCCM_2 0x02000000 ++#define SCCR_ENCCM_3 0x03000000 ++#define SCCR_USBCM_0 0x00000000 ++#define SCCR_USBCM_1 0x00500000 ++#define SCCR_USBCM_2 0x00A00000 ++#define SCCR_USBCM_3 0x00F00000 ++ ++#define SCCR_CLK_MASK ( SCCR_TSEC1CM_3 \ ++ | SCCR_TSEC2CM_3 \ ++ | SCCR_ENCCM_3 \ ++ | SCCR_USBCM_3 ) ++ ++#define SCCR_DEFAULT 0xFFFFFFFF ++ + #endif /* __MPC83XX_H__ */ +diff -Naupr u-boot-1.1.6/include/ppc440.h u-boot-1.1.6-fsl-1/include/ppc440.h +--- u-boot-1.1.6/include/ppc440.h 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/include/ppc440.h 2006-12-06 10:33:49.000000000 -0600 +@@ -1350,26 +1350,26 @@ + + #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + #define UIC2_DCR_BASE 0xe0 +-#define uic2sr (UIC0_DCR_BASE+0x0) /* UIC2 status-Read Clear */ +-#define uic2srs (UIC0_DCR_BASE+0x1) /* UIC2 status-Read Set */ +-#define uic2er (UIC0_DCR_BASE+0x2) /* UIC2 enable */ +-#define uic2cr (UIC0_DCR_BASE+0x3) /* UIC2 critical */ +-#define uic2pr (UIC0_DCR_BASE+0x4) /* UIC2 polarity */ +-#define uic2tr (UIC0_DCR_BASE+0x5) /* UIC2 triggering */ +-#define uic2msr (UIC0_DCR_BASE+0x6) /* UIC2 masked status */ +-#define uic2vr (UIC0_DCR_BASE+0x7) /* UIC2 vector */ +-#define uic2vcr (UIC0_DCR_BASE+0x8) /* UIC2 vector configuration */ ++#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */ ++#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */ ++#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */ ++#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */ ++#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */ ++#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */ ++#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */ ++#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */ ++#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ + + #define UIC3_DCR_BASE 0xf0 +-#define uic3sr (UIC1_DCR_BASE+0x0) /* UIC3 status-Read Clear */ +-#define uic3srs (UIC0_DCR_BASE+0x1) /* UIC3 status-Read Set */ +-#define uic3er (UIC1_DCR_BASE+0x2) /* UIC3 enable */ +-#define uic3cr (UIC1_DCR_BASE+0x3) /* UIC3 critical */ +-#define uic3pr (UIC1_DCR_BASE+0x4) /* UIC3 polarity */ +-#define uic3tr (UIC1_DCR_BASE+0x5) /* UIC3 triggering */ +-#define uic3msr (UIC1_DCR_BASE+0x6) /* UIC3 masked status */ +-#define uic3vr (UIC1_DCR_BASE+0x7) /* UIC3 vector */ +-#define uic3vcr (UIC1_DCR_BASE+0x8) /* UIC3 vector configuration */ ++#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */ ++#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */ ++#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */ ++#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */ ++#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */ ++#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */ ++#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */ ++#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */ ++#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */ + #endif /* CONFIG_440SPE */ + + #if defined(CONFIG_440GX) +@@ -3183,7 +3183,7 @@ + #define GPIO0 0 + #define GPIO1 1 + +-#if defined(CONFIG_440GP) ++#if defined(CONFIG_440GP) || defined(CONFIG_440GX) + #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700) + + #define GPIO0_OR (GPIO0_BASE+0x0) +diff -Naupr u-boot-1.1.6/lib_ppc/board.c u-boot-1.1.6-fsl-1/lib_ppc/board.c +--- u-boot-1.1.6/lib_ppc/board.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/lib_ppc/board.c 2006-12-06 10:33:49.000000000 -0600 +@@ -511,7 +511,7 @@ void board_init_f (ulong bootflag) + bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */ + #endif + #if defined(CONFIG_MPC83XX) +- bd->bi_immrbar = CFG_IMMRBAR; ++ bd->bi_immrbar = CFG_IMMR; + #endif + #if defined(CONFIG_MPC8220) + bd->bi_mbar_base = CFG_MBAR; /* base of internal registers */ +@@ -521,17 +521,17 @@ void board_init_f (ulong bootflag) + bd->bi_pevfreq = gd->pev_clk; + bd->bi_flbfreq = gd->flb_clk; + +- /* store bootparam to sram (backward compatible), here? */ +- { +- u32 *sram = (u32 *)CFG_SRAM_BASE; +- *sram++ = gd->ram_size; +- *sram++ = gd->bus_clk; +- *sram++ = gd->inp_clk; +- *sram++ = gd->cpu_clk; +- *sram++ = gd->vco_clk; +- *sram++ = gd->flb_clk; +- *sram++ = 0xb8c3ba11; /* boot signature */ +- } ++ /* store bootparam to sram (backward compatible), here? */ ++ { ++ u32 *sram = (u32 *)CFG_SRAM_BASE; ++ *sram++ = gd->ram_size; ++ *sram++ = gd->bus_clk; ++ *sram++ = gd->inp_clk; ++ *sram++ = gd->cpu_clk; ++ *sram++ = gd->vco_clk; ++ *sram++ = gd->flb_clk; ++ *sram++ = 0xb8c3ba11; /* boot signature */ ++ } + #endif + + bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */ +diff -Naupr u-boot-1.1.6/MAINTAINERS u-boot-1.1.6-fsl-1/MAINTAINERS +--- u-boot-1.1.6/MAINTAINERS 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/MAINTAINERS 2006-12-06 10:33:48.000000000 -0600 +@@ -277,10 +277,13 @@ Daniel Poirot + + Stefan Roese + ++ P3M7448 MPC7448 ++ + uc100 MPC857 + + TQM85xx MPC8540/8541/8555/8560 + ++ alpr PPC440GX + bamboo PPC440EP + bunbinga PPC405EP + ebony PPC440GP +@@ -293,6 +296,8 @@ Stefan Roese + yellowstone PPC440GR + yosemite PPC440EP + ++ P3M750 PPC750FX/GX/GL ++ + Yusdi Santoso + + HIDDEN_DRAGON MPC8241/MPC8245 +@@ -339,6 +344,18 @@ John Zhan + + svm_sc8xx MPC8xx + ++Timur Tabi ++ ++ MPC8349E-mITX MPC8349 ++ ++Kim Phillips ++ ++ MPC8349EMDS MPC8349 ++ ++Dave Liu ++ ++ MPC8360EMDS MPC8360 ++ + ------------------------------------------------------------------------- + + Unknown / orphaned boards: +diff -Naupr u-boot-1.1.6/MAKEALL u-boot-1.1.6-fsl-1/MAKEALL +--- u-boot-1.1.6/MAKEALL 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/MAKEALL 2006-12-06 10:33:48.000000000 -0600 +@@ -74,21 +74,21 @@ LIST_8xx=" \ + ######################################################################### + + LIST_4xx=" \ +- ADCIOP AP1000 AR405 ASH405 \ +- bamboo bubinga CANBT CMS700 \ +- CPCI2DP CPCI405 CPCI4052 CPCI405AB \ +- CPCI405DT CPCI440 CPCIISER4 CRAYL1 \ +- csb272 csb472 DASA_SIM DP405 \ +- DU405 ebony ERIC EXBITGEN \ +- G2000 HH405 HUB405 JSE \ +- KAREF luan METROBOX MIP405 \ +- MIP405T ML2 ml300 ocotea \ +- OCRTC ORSG p3p440 PCI405 \ +- pcs440ep PIP405 PLU405 PMC405 \ +- PPChameleonEVB sbc405 sequoia sequoia_nand \ +- VOH405 VOM405 W7OLMC W7OLMG \ +- walnut WUH405 XPEDITE1K yellowstone \ +- yosemite yucca bamboo \ ++ ADCIOP alpr AP1000 AR405 \ ++ ASH405 bamboo bubinga CANBT \ ++ CMS700 CPCI2DP CPCI405 CPCI4052 \ ++ CPCI405AB CPCI405DT CPCI440 CPCIISER4 \ ++ CRAYL1 csb272 csb472 DASA_SIM \ ++ DP405 DU405 ebony ERIC \ ++ EXBITGEN G2000 HH405 HUB405 \ ++ JSE KAREF luan METROBOX \ ++ MIP405 MIP405T ML2 ml300 \ ++ ocotea OCRTC ORSG p3p440 \ ++ PCI405 pcs440ep PIP405 PLU405 \ ++ PMC405 PPChameleonEVB sbc405 sequoia \ ++ sequoia_nand VOH405 VOM405 W7OLMC \ ++ W7OLMG walnut WUH405 XPEDITE1K \ ++ yellowstone yosemite yucca \ + " + + ######################################################################### +@@ -130,7 +130,7 @@ LIST_8260=" \ + ######################################################################### + + LIST_83xx=" \ +- TQM834x MPC8349EMDS \ ++ TQM834x MPC8349EMDS MPC8349ITX MPC8360EMDS \ + " + + +@@ -151,11 +151,12 @@ LIST_85xx=" \ + + LIST_74xx=" \ + DB64360 DB64460 EVB64260 P3G4 \ +- PCIPPC2 PCIPPC6 ZUMA \ ++ p3m7448 PCIPPC2 PCIPPC6 ZUMA \ + " + + LIST_7xx=" \ +- BAB7xx CPCI750 ELPPC ppmc7xx \ ++ BAB7xx CPCI750 ELPPC p3m750 \ ++ ppmc7xx \ + " + + LIST_ppc="${LIST_5xx} ${LIST_5xxx} \ +diff -Naupr u-boot-1.1.6/Makefile u-boot-1.1.6-fsl-1/Makefile +--- u-boot-1.1.6/Makefile 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/Makefile 2006-12-06 10:33:48.000000000 -0600 +@@ -93,7 +93,7 @@ MKCONFIG := $(SRCTREE)/mkconfig + export MKCONFIG + + ifneq ($(OBJTREE),$(SRCTREE)) +-REMOTE_BUILD := 1 ++REMOTE_BUILD := 1 + export REMOTE_BUILD + endif + +@@ -174,9 +174,6 @@ endif + ifeq ($(CPU),ppc4xx) + OBJS += cpu/$(CPU)/resetvec.o + endif +-ifeq ($(CPU),mpc83xx) +-OBJS += cpu/$(CPU)/resetvec.o +-endif + ifeq ($(CPU),mpc85xx) + OBJS += cpu/$(CPU)/resetvec.o + endif +@@ -206,6 +203,9 @@ LIBS += dtt/libdtt.a + LIBS += drivers/libdrivers.a + LIBS += drivers/nand/libnand.a + LIBS += drivers/nand_legacy/libnand_legacy.a ++ifeq ($(CPU),mpc83xx) ++LIBS += drivers/qe/qe.a ++endif + LIBS += drivers/sk98lin/libsk98lin.a + LIBS += post/libpost.a post/cpu/libcpu.a + LIBS += common/libcommon.a +@@ -378,8 +378,8 @@ Lite5200_LOWBOOT08_config \ + icecube_5200_config \ + icecube_5200_LOWBOOT_config \ + icecube_5200_LOWBOOT08_config \ +-icecube_5200_DDR_config \ +-icecube_5200_DDR_LOWBOOT_config \ ++icecube_5200_DDR_config \ ++icecube_5200_DDR_LOWBOOT_config \ + icecube_5200_DDR_LOWBOOT08_config \ + icecube_5100_config: unconfig + @mkdir -p $(obj)include +@@ -412,7 +412,7 @@ icecube_5100_config: unconfig + @$(MKCONFIG) -a IceCube ppc mpc5xxx icecube + + v38b_config: unconfig +- @./mkconfig -a V38B ppc mpc5xxx v38b ++ @./mkconfig -a v38b ppc mpc5xxx v38b + + inka4x0_config: unconfig + @$(MKCONFIG) inka4x0 ppc mpc5xxx inka4x0 +@@ -458,7 +458,7 @@ prs200_highboot_DDR_config: unconfig + @[ -n "$(findstring _SDRAM,$@)" ] || \ + { if [ -n "$(findstring mcc200,$@)" ]; \ + then \ +- echo "... with DDR" ; \ ++ echo "... with DDR" ; \ + else \ + if [ -n "$(findstring _DDR,$@)" ];\ + then \ +@@ -865,9 +865,9 @@ RPXClassic_config: unconfig + RPXlite_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc8xx RPXlite + +-RPXlite_DW_64_config \ +-RPXlite_DW_LCD_config \ +-RPXlite_DW_64_LCD_config \ ++RPXlite_DW_64_config \ ++RPXlite_DW_LCD_config \ ++RPXlite_DW_64_LCD_config \ + RPXlite_DW_NVRAM_config \ + RPXlite_DW_NVRAM_64_config \ + RPXlite_DW_NVRAM_LCD_config \ +@@ -880,12 +880,12 @@ RPXlite_DW_config: unconfig + echo "... with 64MHz system clock ..."; \ + } + @[ -z "$(findstring _LCD,$@)" ] || \ +- { echo "#define CONFIG_LCD" >>$(obj)include/config.h ; \ ++ { echo "#define CONFIG_LCD" >>$(obj)include/config.h ; \ + echo "#define CONFIG_NEC_NL6448BC20" >>$(obj)include/config.h ; \ + echo "... with LCD display ..."; \ + } + @[ -z "$(findstring _NVRAM,$@)" ] || \ +- { echo "#define CFG_ENV_IS_IN_NVRAM" >>$(obj)include/config.h ; \ ++ { echo "#define CFG_ENV_IS_IN_NVRAM" >>$(obj)include/config.h ; \ + echo "... with ENV in NVRAM ..."; \ + } + @$(MKCONFIG) -a RPXlite_DW ppc mpc8xx RPXlite_dw +@@ -984,6 +984,9 @@ xtract_4xx = $(subst _25,,$(subst _33,,$ + ADCIOP_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx adciop esd + ++alpr_config: unconfig ++ @./mkconfig $(@:_config=) ppc ppc4xx alpr prodrive ++ + AP1000_config:unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx ap1000 amirix + +@@ -1585,15 +1588,39 @@ r5200_config : unconfig + ## MPC83xx Systems + ######################################################################### + +-MPC8349ADS_config: unconfig +- @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349ads +- + TQM834x_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x + + MPC8349EMDS_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds + ++MPC8360EMDS_config \ ++MPC8360EMDS_HOST_33_config \ ++MPC8360EMDS_HOST_66_config \ ++MPC8360EMDS_SLAVE_config: unconfig ++ @echo "" >include/config.h ; \ ++ if [ "$(findstring _HOST_,$@)" ] ; then \ ++ echo -n "... PCI HOST " ; \ ++ echo "#define CONFIG_PCI" >>include/config.h ; \ ++ fi ; \ ++ if [ "$(findstring _SLAVE_,$@)" ] ; then \ ++ echo "...PCI SLAVE 66M" ; \ ++ echo "#define CONFIG_PCI" >>include/config.h ; \ ++ echo "#define CONFIG_PCISLAVE" >>include/config.h ; \ ++ fi ; \ ++ if [ "$(findstring _33_,$@)" ] ; then \ ++ echo -n "...33M ..." ; \ ++ echo "#define PCI_33M" >>include/config.h ; \ ++ fi ; \ ++ if [ "$(findstring _66_,$@)" ] ; then \ ++ echo -n "...66M..." ; \ ++ echo "#define PCI_66M" >>include/config.h ; \ ++ fi ; ++ @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds ++ ++MPC8349ITX_config: unconfig ++ @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349itx ++ + ######################################################################### + ## MPC85xx Systems + ######################################################################### +@@ -1721,6 +1748,16 @@ EVB64260_750CX_config: unconfig + P3G4_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260 + ++p3m750_config \ ++p3m7448_config: unconfig ++ @mkdir -p $(obj)include ++ @if [ "$(findstring 750_,$@)" ] ; then \ ++ echo "#define CONFIG_P3M750" >>$(obj)include/config.h ; \ ++ else \ ++ echo "#define CONFIG_P3M7448" >>$(obj)include/config.h ; \ ++ fi ++ @$(MKCONFIG) -a p3mx ppc 74xx_7xx p3mx prodrive ++ + PCIPPC2_config \ + PCIPPC6_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx pcippc2 +@@ -1784,7 +1821,7 @@ ap966_config \ + ap922_config \ + ap922_XA10_config \ + ap7_config \ +-ap720t_config \ ++ap720t_config \ + ap920t_config \ + ap926ejs_config \ + ap946es_config: unconfig +@@ -1941,7 +1978,7 @@ cm4008_config : unconfig + cm41xx_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t cm41xx NULL ks8695 + +-gth2_config : unconfig ++gth2_config : unconfig + @mkdir -p $(obj)include + @ >$(obj)include/config.h + @echo "#define CONFIG_GTH2 1" >>$(obj)include/config.h +@@ -2087,19 +2124,19 @@ tb0229_config: unconfig + ######################################################################### + ## MIPS32 AU1X00 + ######################################################################### +-dbau1000_config : unconfig ++dbau1000_config : unconfig + @mkdir -p $(obj)include + @ >$(obj)include/config.h + @echo "#define CONFIG_DBAU1000 1" >>$(obj)include/config.h + @$(MKCONFIG) -a dbau1x00 mips mips dbau1x00 + +-dbau1100_config : unconfig ++dbau1100_config : unconfig + @mkdir -p $(obj)include + @ >$(obj)include/config.h + @echo "#define CONFIG_DBAU1100 1" >>$(obj)include/config.h + @$(MKCONFIG) -a dbau1x00 mips mips dbau1x00 + +-dbau1500_config : unconfig ++dbau1500_config : unconfig + @mkdir -p $(obj)include + @ >$(obj)include/config.h + @echo "#define CONFIG_DBAU1500 1" >>$(obj)include/config.h +@@ -2117,7 +2154,7 @@ dbau1550_el_config : unconfig + @echo "#define CONFIG_DBAU1550 1" >>$(obj)include/config.h + @$(MKCONFIG) -a dbau1x00 mips mips dbau1x00 + +-pb1000_config : unconfig ++pb1000_config : unconfig + @mkdir -p $(obj)include + @ >$(obj)include/config.h + @echo "#define CONFIG_PB1000 1" >>$(obj)include/config.h +diff -Naupr u-boot-1.1.6/net/eth.c u-boot-1.1.6-fsl-1/net/eth.c +--- u-boot-1.1.6/net/eth.c 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/net/eth.c 2006-12-06 10:33:49.000000000 -0600 +@@ -54,6 +54,7 @@ extern int scc_initialize(bd_t*); + extern int skge_initialize(bd_t*); + extern int tsec_initialize(bd_t*, int, char *); + extern int npe_initialize(bd_t *); ++extern int uec_initialize(int); + + static struct eth_device *eth_devices, *eth_current; + +@@ -142,13 +143,10 @@ int eth_initialize(bd_t *bis) + miiphy_init(); + #endif + +-#ifdef CONFIG_DB64360 ++#if defined(CONFIG_DB64360) || defined(CONFIG_CPCI750) + mv6436x_eth_initialize(bis); + #endif +-#ifdef CONFIG_CPCI750 +- mv6436x_eth_initialize(bis); +-#endif +-#ifdef CONFIG_DB64460 ++#if defined(CONFIG_DB64460) || defined(CONFIG_P3Mx) + mv6446x_eth_initialize(bis); + #endif + #if defined(CONFIG_4xx) && !defined(CONFIG_IOP480) && !defined(CONFIG_AP1000) +@@ -196,6 +194,12 @@ int eth_initialize(bd_t *bis) + tsec_initialize(bis, 3, CONFIG_MPC83XX_TSEC4_NAME); + # endif + #endif ++#if defined(CONFIG_UEC_ETH1) ++ uec_initialize(0); ++#endif ++#if defined(CONFIG_UEC_ETH2) ++ uec_initialize(1); ++#endif + #if defined(CONFIG_MPC86XX_TSEC1) + tsec_initialize(bis, 0, CONFIG_MPC86XX_TSEC1_NAME); + #endif +diff -Naupr u-boot-1.1.6/README u-boot-1.1.6-fsl-1/README +--- u-boot-1.1.6/README 2006-11-02 08:15:01.000000000 -0600 ++++ u-boot-1.1.6-fsl-1/README 2006-11-30 12:34:13.000000000 -0600 +@@ -1207,7 +1207,12 @@ The following options need to be configu + clock chips. See common/cmd_i2c.c for a description of the + command line interface. + +- CONFIG_HARD_I2C selects the CPM hardware driver for I2C. ++ CONFIG_I2C_CMD_TREE is a recommended option that places ++ all I2C commands under a single 'i2c' root command. The ++ older 'imm', 'imd', 'iprobe' etc. commands are considered ++ deprecated and may disappear in the future. ++ ++ CONFIG_HARD_I2C selects a hardware I2C controller. + + CONFIG_SOFT_I2C configures u-boot to use a software (aka + bit-banging) driver instead of CPM or similar hardware +@@ -1312,6 +1317,42 @@ The following options need to be configu + in u-boot bd_info structure based on u-boot environment + variable "i2cfast". (see also i2cfast) + ++ CONFIG_I2C_MULTI_BUS ++ ++ This option allows the use of multiple I2C buses, each of which ++ must have a controller. At any point in time, only one bus is ++ active. To switch to a different bus, use the 'i2c dev' command. ++ Note that bus numbering is zero-based. ++ ++ CFG_I2C_NOPROBES ++ ++ This option specifies a list of I2C devices that will be skipped ++ when the 'i2c probe' command is issued (or 'iprobe' using the legacy ++ command). If CONFIG_I2C_MULTI_BUS is set, specify a list of bus-device ++ pairs. Otherwise, specify a 1D array of device addresses ++ ++ e.g. ++ #undef CONFIG_I2C_MULTI_BUS ++ #define CFG_I2C_NOPROBES {0x50,0x68} ++ ++ will skip addresses 0x50 and 0x68 on a board with one I2C bus ++ ++ #define CONFIG_I2C_MULTI_BUS ++ #define CFG_I2C_MULTI_NOPROBES {{0,0x50},{0,0x68},{1,0x54}} ++ ++ will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1 ++ ++ CFG_SPD_BUS_NUM ++ ++ If defined, then this indicates the I2C bus number for DDR SPD. ++ If not defined, then U-Boot assumes that SPD is on I2C bus 0. ++ ++ CONFIG_FSL_I2C ++ ++ Define this option if you want to use Freescale's I2C driver in ++ drivers/fsl_i2c.c. ++ ++ + - SPI Support: CONFIG_SPI + + Enables SPI driver (so far only tested with +@@ -1470,8 +1511,8 @@ The following options need to be configu + + Enable auto completion of commands using TAB. + +- Note that this feature has NOT been implemented yet +- for the "hush" shell. ++ Note that this feature has NOT been implemented yet ++ for the "hush" shell. + + + CFG_HUSH_PARSER +@@ -2209,6 +2250,24 @@ Low Level (hardware related) configurati + CFG_POCMR2_MASK_ATTRIB: (MPC826x only) + Overrides the default PCI memory map in cpu/mpc8260/pci.c if set. + ++- CONFIG_SPD_EEPROM ++ Get DDR timing information from an I2C EEPROM. Common with pluggable ++ memory modules such as SODIMMs ++ SPD_EEPROM_ADDRESS ++ I2C address of the SPD EEPROM ++ ++- CFG_SPD_BUS_NUM ++ If SPD EEPROM is on an I2C bus other than the first one, specify here. ++ Note that the value must resolve to something your driver can deal with. ++ ++- CFG_83XX_DDR_USES_CS0 ++ Only for 83xx systems. If specified, then DDR should be configured ++ using CS0 and CS1 instead of CS2 and CS3. ++ ++- CFG_83XX_DDR_USES_CS0 ++ Only for 83xx systems. If specified, then DDR should be configured ++ using CS0 and CS1 instead of CS2 and CS3. ++ + - CONFIG_ETHER_ON_FEC[12] + Define to enable FEC[12] on a 8xx series processor. + +@@ -3114,11 +3173,11 @@ loadaddr=200000 + oftaddr=0x300000 + => bootm $loadaddr - $oftaddr + ## Booting image at 00200000 ... +- Image Name: Linux-2.6.17-dirty +- Image Type: PowerPC Linux Kernel Image (gzip compressed) +- Data Size: 1029343 Bytes = 1005.2 kB ++ Image Name: Linux-2.6.17-dirty ++ Image Type: PowerPC Linux Kernel Image (gzip compressed) ++ Data Size: 1029343 Bytes = 1005.2 kB + Load Address: 00000000 +- Entry Point: 00000000 ++ Entry Point: 00000000 + Verifying Checksum ... OK + Uncompressing Kernel Image ... OK + Booting using flat device tree at 0x300000 diff --git a/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-streamline-the-83xx-immr-head-file.patch b/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-streamline-the-83xx-immr-head-file.patch new file mode 100644 index 0000000000..30981dc43c --- /dev/null +++ b/packages/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-streamline-the-83xx-immr-head-file.patch @@ -0,0 +1,3640 @@ +ce4d6db21531bc35da7180436c6f49efac7c0461 +diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c +index 36d901f..9c35e22 100644 +--- a/board/tqm834x/tqm834x.c ++++ b/board/tqm834x/tqm834x.c +@@ -148,14 +148,14 @@ int checkboard (void) + u32 w, f; + + immr = (immap_t *)CFG_IMMR; +- if (!(immr->reset.rcwh & RCWH_PCIHOST)) { ++ if (!(immr->reset.rcwh & HRCWH_PCI_HOST)) { + printf("PCI: NOT in host mode..?!\n"); + return 0; + } + + /* get bus width */ + w = 32; +- if (immr->reset.rcwh & RCWH_PCI64) ++ if (immr->reset.rcwh & HRCWH_64_BIT_PCI) + w = 64; + + /* get clock */ +diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c +index e5725fb..7574fab 100644 +--- a/cpu/mpc83xx/cpu_init.c ++++ b/cpu/mpc83xx/cpu_init.c +@@ -202,12 +202,12 @@ void cpu_init_f (volatile immap_t * im) + im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM; + #endif + #ifdef CFG_GPIO1_PRELIM +- im->pgio[0].dir = CFG_GPIO1_DIR; +- im->pgio[0].dat = CFG_GPIO1_DAT; ++ im->gpio[0].dir = CFG_GPIO1_DIR; ++ im->gpio[0].dat = CFG_GPIO1_DAT; + #endif + #ifdef CFG_GPIO2_PRELIM +- im->pgio[1].dir = CFG_GPIO2_DIR; +- im->pgio[1].dat = CFG_GPIO2_DAT; ++ im->gpio[1].dir = CFG_GPIO2_DIR; ++ im->gpio[1].dat = CFG_GPIO2_DAT; + #endif + } + +diff --git a/cpu/mpc83xx/qe_io.c b/cpu/mpc83xx/qe_io.c +index ebe3487..8b3937a 100644 +--- a/cpu/mpc83xx/qe_io.c ++++ b/cpu/mpc83xx/qe_io.c +@@ -35,7 +35,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) + u32 pin_1bit_mask; + u32 tmp_val; + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; +- volatile gpio83xx_t *par_io =(volatile gpio83xx_t *)&im->gpio; ++ volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio; + + /* Caculate pin location and 2bit mask and dir */ + pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); +diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c +index 7e53b1e..40ba6b0 100644 +--- a/cpu/mpc83xx/speed.c ++++ b/cpu/mpc83xx/speed.c +@@ -139,7 +139,7 @@ int get_clocks(void) + #endif + } + +- spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT); ++ spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT); + csb_clk = pci_sync_in * (1 + clkin_div) * spmf; + + sccr = im->clk.sccr; +@@ -251,7 +251,7 @@ int get_clocks(void) + } + #if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360) + lbiu_clk = csb_clk * +- (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT)); ++ (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); + #else + #error Unknown MPC83xx chip + #endif +@@ -268,11 +268,11 @@ int get_clocks(void) + } + #if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360) + ddr_clk = csb_clk * +- (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT)); +- corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT; ++ (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT)); ++ corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT; + #if defined (CONFIG_MPC8360) + ddr_sec_clk = csb_clk * (1 + +- ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT)); ++ ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); + #endif + #else + #error Unknown MPC83xx chip +@@ -307,8 +307,8 @@ int get_clocks(void) + } + + #if defined (CONFIG_MPC8360) +- qepmf = (im->reset.rcwl & RCWL_CEPMF) >> RCWL_CEPMF_SHIFT; +- qepdf = (im->reset.rcwl & RCWL_CEPDF) >> RCWL_CEPDF_SHIFT; ++ qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT; ++ qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT; + qe_clk = (pci_sync_in * qepmf) / (1 + qepdf); + brg_clk = qe_clk / 2; + #endif +diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h +index 43cde5e..67b035c 100644 +--- a/include/asm-ppc/immap_83xx.h ++++ b/include/asm-ppc/immap_83xx.h +@@ -3,20 +3,11 @@ + * + * MPC83xx Internal Memory Map + * +- * History : +- * 20060601: Daveliu (daveliu@freescale.com) +- * TanyaJiang (tanya.jiang@freescale.com) +- * Unified variable names for mpc83xx +- * 2005 : Mandy Lavi (mandy.lavi@freescale.com) +- * support for mpc8360e +- * 2004 : Eran Liberty (liberty@freescale.com) +- * Initialized for mpc8349 +- * based on: +- * MPC8260 Internal Memory Map +- * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) +- * MPC85xx Internal Memory Map +- * Copyright(c) 2002,2003 Motorola Inc. +- * Xianghua Xiao (x.xiao@motorola.com) ++ * Contributors: ++ * Dave Liu ++ * Tanya Jiang ++ * Mandy Lavi ++ * Eran Liberty + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as +@@ -25,7 +16,7 @@ + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License +@@ -37,36 +28,24 @@ + #ifndef __IMMAP_83xx__ + #define __IMMAP_83xx__ + +-#include + #include + #include + + /* +- * Local Access Window. ++ * Local Access Window + */ + typedef struct law83xx { + u32 bar; /* LBIU local access window base address register */ +-/* Identifies the 20 most-significant address bits of the base of local +- * access window n. The specified base address should be aligned to the +- * window size, as defined by LBLAWARn[SIZE]. +- */ +-#define LAWBAR_BAR 0xFFFFF000 +-#define LAWBAR_RES ~(LAWBAR_BAR) + u32 ar; /* LBIU local access window attribute register */ + } law83xx_t; + + /* +- * System configuration registers. ++ * System configuration registers + */ + typedef struct sysconf83xx { + u32 immrbar; /* Internal memory map base address register */ + u8 res0[0x04]; + u32 altcbar; /* Alternate configuration base address register */ +-/* Identifies the12 most significant address bits of an alternate base +- * address used for boot sequencer configuration accesses. +- */ +-#define ALTCBAR_BASE_ADDR 0xFFF00000 +-#define ALTCBAR_RES ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */ + u8 res1[0x14]; + law83xx_t lblaw[4]; /* LBIU local access window */ + u8 res2[0x20]; +@@ -77,115 +56,10 @@ typedef struct sysconf83xx { + u32 sgprl; /* System General Purpose Register Low */ + u32 sgprh; /* System General Purpose Register High */ + u32 spridr; /* System Part and Revision ID Register */ +-#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification. */ +-#define SPRIDR_REVID 0x0000FFFF /* Revision Identification. */ + u8 res5[0x04]; + u32 spcr; /* System Priority Configuration Register */ +-#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable. */ +-#define SPCR_PCIHPE_SHIFT (31-3) +-#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority. */ +-#define SPCR_PCIPR_SHIFT (31-7) +-#define SPCR_OPT 0x00800000 /* Optimize */ +-#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable. */ +-#define SPCR_TBEN_SHIFT (31-9) +-#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority. */ +-#define SPCR_COREPR_SHIFT (31-11) +-#if defined (CONFIG_MPC8349) +-#define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority. */ +-#define SPCR_TSEC1DP_SHIFT (31-19) +-#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */ +-#define SPCR_TSEC1BDP_SHIFT (31-21) +-#define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority. */ +-#define SPCR_TSEC1EP_SHIFT (31-23) +-#define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority. */ +-#define SPCR_TSEC2DP_SHIFT (31-27) +-#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */ +-#define SPCR_TSEC2BDP_SHIFT (31-29) +-#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority. */ +-#define SPCR_TSEC2EP_SHIFT (31-31) +-#define SPCR_RES ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \ +- | SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \ +- | SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP) +-#elif defined (CONFIG_MPC8360) +-#define SPCR_RES ~(SPCR_PCIHPE|SPCR_PCIPR|SPCR_OPT|SPCR_TBEN|SPCR_COREPR) +-#endif +- u32 sicrl; /* System General Purpose Register Low */ +-#if defined (CONFIG_MPC8349) +-#define SICRL_LDP_A 0x80000000 +-#define SICRL_USB1 0x40000000 +-#define SICRL_USB0 0x20000000 +-#define SICRL_UART 0x0C000000 +-#define SICRL_GPIO1_A 0x02000000 +-#define SICRL_GPIO1_B 0x01000000 +-#define SICRL_GPIO1_C 0x00800000 +-#define SICRL_GPIO1_D 0x00400000 +-#define SICRL_GPIO1_E 0x00200000 +-#define SICRL_GPIO1_F 0x00180000 +-#define SICRL_GPIO1_G 0x00040000 +-#define SICRL_GPIO1_H 0x00020000 +-#define SICRL_GPIO1_I 0x00010000 +-#define SICRL_GPIO1_J 0x00008000 +-#define SICRL_GPIO1_K 0x00004000 +-#define SICRL_GPIO1_L 0x00003000 +-#define SICRL_RES ~(SICRL_LDP_A | SICRL_USB0 | SICRL_USB1 | SICRL_UART \ +- | SICRL_GPIO1_A | SICRL_GPIO1_B | SICRL_GPIO1_C \ +- | SICRL_GPIO1_D | SICRL_GPIO1_E | SICRL_GPIO1_F \ +- | SICRL_GPIO1_G | SICRL_GPIO1_H | SICRL_GPIO1_I \ +- | SICRL_GPIO1_J | SICRL_GPIO1_K | SICRL_GPIO1_L ) +-#elif defined (CONFIG_MPC8360) +-#define SICRL_LDP_A 0xC0000000 +-#define SICRL_LCLK_1 0x10000000 +-#define SICRL_LCLK_2 0x08000000 +-#define SICRL_SRCID_A 0x03000000 +-#define SICRL_IRQ_CKSTP_A 0x00C00000 +-#define SICRL_RES ~(SICRL_LDP_A | SICRL_LCLK_1 | SICRL_LCLK_2 | \ +- SICRL_SRCID_A | SICRL_IRQ_CKSTP_A) +-#endif +- u32 sicrh; /* System General Purpose Register High */ +-#define SICRH_DDR 0x80000000 +-#if defined (CONFIG_MPC8349) +-#define SICRH_TSEC1_A 0x10000000 +-#define SICRH_TSEC1_B 0x08000000 +-#define SICRH_TSEC1_C 0x04000000 +-#define SICRH_TSEC1_D 0x02000000 +-#define SICRH_TSEC1_E 0x01000000 +-#define SICRH_TSEC1_F 0x00800000 +-#define SICRH_TSEC2_A 0x00400000 +-#define SICRH_TSEC2_B 0x00200000 +-#define SICRH_TSEC2_C 0x00100000 +-#define SICRH_TSEC2_D 0x00080000 +-#define SICRH_TSEC2_E 0x00040000 +-#define SICRH_TSEC2_F 0x00020000 +-#define SICRH_TSEC2_G 0x00010000 +-#define SICRH_TSEC2_H 0x00008000 +-#define SICRH_GPIO2_A 0x00004000 +-#define SICRH_GPIO2_B 0x00002000 +-#define SICRH_GPIO2_C 0x00001000 +-#define SICRH_GPIO2_D 0x00000800 +-#define SICRH_GPIO2_E 0x00000400 +-#define SICRH_GPIO2_F 0x00000200 +-#define SICRH_GPIO2_G 0x00000180 +-#define SICRH_GPIO2_H 0x00000060 +-#define SICRH_TSOBI1 0x00000002 +-#define SICRH_TSOBI2 0x00000001 +-#define SICRH_RES ~( SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \ +- | SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \ +- | SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \ +- | SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \ +- | SICRH_TSEC2_F | SICRH_TSEC2_G | SICRH_TSEC2_H \ +- | SICRH_GPIO2_A | SICRH_GPIO2_B | SICRH_GPIO2_C \ +- | SICRH_GPIO2_D | SICRH_GPIO2_E | SICRH_GPIO2_F \ +- | SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \ +- | SICRH_TSOBI2) +-#elif defined (CONFIG_MPC8360) +-#define SICRH_SECONDARY_DDR 0x40000000 +-#define SICRH_SDDROE 0x02000000 /* SDDRIOE bit from reset configuration word high. */ +-#define SICRH_UC1EOBI 0x00000004 /* UCC1 Ethernet Output Buffer Impedance. */ +-#define SICRH_UC2E1OBI 0x00000002 /* UCC2 Ethernet pin option 1 Output Buffer Impedance. */ +-#define SICRH_UC2E2OBI 0x00000001 /* UCC2 Ethernet pin option 2 Output Buffer Impedance. */ +-#define SICRH_RES ~(SICRH_DDR | SICRH_SECONDARY_DDR | SICRH_SDDROE | \ +- SICRH_UC2E1OBI | SICRH_UC2E2OBI | SICRH_UC2E2OBI) +-#endif ++ u32 sicrl; /* System I/O Configuration Register Low */ ++ u32 sicrh; /* System I/O Configuration Register High */ + u8 res6[0xE4]; + } sysconf83xx_t; + +@@ -196,11 +70,8 @@ typedef struct wdt83xx { + u8 res0[4]; + u32 swcrr; /* System watchdog control register */ + u32 swcnr; /* System watchdog count register */ +-#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field. +-#define SWCNR_RES ~(SWCNR_SWCN) + u8 res1[2]; + u16 swsrr; /* System watchdog service register */ +-#define SWSRR_WS 0x0000FFFF /* Software Watchdog Service Field. */ + u8 res2[0xF0]; + } wdt83xx_t; + +@@ -209,91 +80,46 @@ typedef struct wdt83xx { + */ + typedef struct rtclk83xx { + u32 cnr; /* control register */ +-#define CNR_CLEN 0x00000080 /* Clock Enable Control Bit */ +-#define CNR_CLIN 0x00000040 /* Input Clock Control Bit */ +-#define CNR_AIM 0x00000002 /* Alarm Interrupt Mask Bit */ +-#define CNR_SIM 0x00000001 /* Second Interrupt Mask Bit */ +-#define CNR_RES ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM) + u32 ldr; /* load register */ +-#define LDR_CLDV 0xFFFFFFFF /* Contains the 32-bit value to be +- * loaded in a 32-bit RTC counter.*/ + u32 psr; /* prescale register */ +-#define PSR_PRSC 0xFFFFFFFF /* RTC Prescaler bits. */ +- u32 ctr; /* Counter value field register */ +-#define CRT_CNTV 0xFFFFFFFF /* RTC Counter value field. */ ++ u32 ctr; /* counter value field register */ + u32 evr; /* event register */ +-#define RTEVR_SIF 0x00000001 /* Second Interrupt Flag Bit */ +-#define RTEVR_AIF 0x00000002 /* Alarm Interrupt Flag Bit */ +-#define RTEVR_RES ~(RTEVR_SIF | RTEVR_AIF) +-#define PTEVR_PIF 0x00000001 /* Periodic interrupt flag bit. */ +-#define PTEVR_RES ~(PTEVR_PIF) + u32 alr; /* alarm register */ + u8 res0[0xE8]; + } rtclk83xx_t; + + /* +- * Global timper module ++ * Global timer module + */ +- + typedef struct gtm83xx { +- u8 cfr1; /* Timer1/2 Configuration */ +-#define CFR1_PCAS 0x80 /* Pair Cascade mode */ +-#define CFR1_BCM 0x40 /* Backward compatible mode */ +-#define CFR1_STP2 0x20 /* Stop timer */ +-#define CFR1_RST2 0x10 /* Reset timer */ +-#define CFR1_GM2 0x08 /* Gate mode for pin 2 */ +-#define CFR1_GM1 0x04 /* Gate mode for pin 1 */ +-#define CFR1_STP1 0x02 /* Stop timer */ +-#define CFR1_RST1 0x01 /* Reset timer */ +-#define CFR1_RES ~(CFR1_PCAS | CFR1_STP2 | CFR1_RST2 | CFR1_GM2 |\ +- CFR1_GM1 | CFR1_STP1 | CFR1_RST1) ++ u8 cfr1; /* Timer1/2 Configuration */ + u8 res0[3]; +- u8 cfr2; /* Timer3/4 Configuration */ +-#define CFR2_PCAS 0x80 /* Pair Cascade mode */ +-#define CFR2_SCAS 0x40 /* Super Cascade mode */ +-#define CFR2_STP4 0x20 /* Stop timer */ +-#define CFR2_RST4 0x10 /* Reset timer */ +-#define CFR2_GM4 0x08 /* Gate mode for pin 4 */ +-#define CFR2_GM3 0x04 /* Gate mode for pin 3 */ +-#define CFR2_STP3 0x02 /* Stop timer */ +-#define CFR2_RST3 0x01 /* Reset timer */ ++ u8 cfr2; /* Timer3/4 Configuration */ + u8 res1[10]; +- u16 mdr1; /* Timer1 Mode Register */ +-#define MDR_SPS 0xff00 /* Secondary Prescaler value */ +-#define MDR_CE 0x00c0 /* Capture edge and enable interrupt */ +-#define MDR_OM 0x0020 /* Output mode */ +-#define MDR_ORI 0x0010 /* Output reference interrupt enable */ +-#define MDR_FRR 0x0008 /* Free run/restart */ +-#define MDR_ICLK 0x0006 /* Input clock source for the timer */ +-#define MDR_GE 0x0001 /* Gate enable */ +- u16 mdr2; /* Timer2 Mode Register */ +- u16 rfr1; /* Timer1 Reference Register */ +- u16 rfr2; /* Timer2 Reference Register */ +- u16 cpr1; /* Timer1 Capture Register */ +- u16 cpr2; /* Timer2 Capture Register */ +- u16 cnr1; /* Timer1 Counter Register */ +- u16 cnr2; /* Timer2 Counter Register */ +- u16 mdr3; /* Timer3 Mode Register */ +- u16 mdr4; /* Timer4 Mode Register */ +- u16 rfr3; /* Timer3 Reference Register */ +- u16 rfr4; /* Timer4 Reference Register */ +- u16 cpr3; /* Timer3 Capture Register */ +- u16 cpr4; /* Timer4 Capture Register */ +- u16 cnr3; /* Timer3 Counter Register */ +- u16 cnr4; /* Timer4 Counter Register */ +- u16 evr1; /* Timer1 Event Register */ +- u16 evr2; /* Timer2 Event Register */ +- u16 evr3; /* Timer3 Event Register */ +- u16 evr4; /* Timer4 Event Register */ +-#define GTEVR_REF 0x0002 /* Output reference event */ +-#define GTEVR_CAP 0x0001 /* Counter Capture event */ +-#define GTEVR_RES ~(EVR_CAP|EVR_REF) +- u16 psr1; /* Timer1 Prescaler Register */ +- u16 psr2; /* Timer2 Prescaler Register */ +- u16 psr3; /* Timer3 Prescaler Register */ +- u16 psr4; /* Timer4 Prescaler Register */ +-#define GTPSR_PPS 0x00FF /* Primary Prescaler Bits. */ +-#define GTPSR_RES ~(GTPSR_PPS) ++ u16 mdr1; /* Timer1 Mode Register */ ++ u16 mdr2; /* Timer2 Mode Register */ ++ u16 rfr1; /* Timer1 Reference Register */ ++ u16 rfr2; /* Timer2 Reference Register */ ++ u16 cpr1; /* Timer1 Capture Register */ ++ u16 cpr2; /* Timer2 Capture Register */ ++ u16 cnr1; /* Timer1 Counter Register */ ++ u16 cnr2; /* Timer2 Counter Register */ ++ u16 mdr3; /* Timer3 Mode Register */ ++ u16 mdr4; /* Timer4 Mode Register */ ++ u16 rfr3; /* Timer3 Reference Register */ ++ u16 rfr4; /* Timer4 Reference Register */ ++ u16 cpr3; /* Timer3 Capture Register */ ++ u16 cpr4; /* Timer4 Capture Register */ ++ u16 cnr3; /* Timer3 Counter Register */ ++ u16 cnr4; /* Timer4 Counter Register */ ++ u16 evr1; /* Timer1 Event Register */ ++ u16 evr2; /* Timer2 Event Register */ ++ u16 evr3; /* Timer3 Event Register */ ++ u16 evr4; /* Timer4 Event Register */ ++ u16 psr1; /* Timer1 Prescaler Register */ ++ u16 psr2; /* Timer2 Prescaler Register */ ++ u16 psr3; /* Timer3 Prescaler Register */ ++ u16 psr4; /* Timer4 Prescaler Register */ + u8 res[0xC0]; + } gtm83xx_t; + +@@ -301,188 +127,31 @@ typedef struct gtm83xx { + * Integrated Programmable Interrupt Controller + */ + typedef struct ipic83xx { +- u32 sicfr; /* System Global Interrupt Configuration Register (SICFR) */ +-#define SICFR_HPI 0x7f000000 /* Highest Priority Interrupt */ +-#define SICFR_MPSB 0x00400000 /* Mixed interrupts Priority Scheme for group B */ +-#define SICFR_MPSA 0x00200000 /* Mixed interrupts Priority Scheme for group A */ +-#define SICFR_IPSD 0x00080000 /* Internal interrupts Priority Scheme for group D */ +-#define SICFR_IPSA 0x00010000 /* Internal interrupts Priority Scheme for group A */ +-#define SICFR_HPIT 0x00000300 /* HPI priority position IPIC output interrupt Type */ +-#define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT) +- u32 sivcr; /* System Global Interrupt Vector Register (SIVCR) */ +-#define SICVR_IVECX 0xfc000000 /* Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation) */ +-#define SICVR_IVEC 0x0000007f /* Interrupt vector */ +-#define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC) +- u32 sipnr_h; /* System Internal Interrupt Pending Register - High (SIPNR_H) */ +-#if defined (CONFIG_MPC8349) +-#define SIIH_TSEC1TX 0x80000000 /* TSEC1 Tx interrupt */ +-#define SIIH_TSEC1RX 0x40000000 /* TSEC1 Rx interrupt */ +-#define SIIH_TSEC1ER 0x20000000 /* TSEC1 Eror interrupt */ +-#define SIIH_TSEC2TX 0x10000000 /* TSEC2 Tx interrupt */ +-#define SIIH_TSEC2RX 0x08000000 /* TSEC2 Rx interrupt */ +-#define SIIH_TSEC2ER 0x04000000 /* TSEC2 Eror interrupt */ +-#define SIIH_USB2DR 0x02000000 /* USB2 DR interrupt */ +-#define SIIH_USB2MPH 0x01000000 /* USB2 MPH interrupt */ +-#endif +-#if defined (CONFIG_MPC8360) +-#define SIIH_H_QE_H 0x80000000 /* QE high interrupt */ +-#define SIIH_H_QE_L 0x40000000 /* QE low interrupt */ +-#endif +-#define SIIH_UART1 0x00000080 /* UART1 interrupt */ +-#define SIIH_UART2 0x00000040 /* UART2 interrupt */ +-#define SIIH_SEC 0x00000020 /* SEC interrupt */ +-#define SIIH_I2C1 0x00000004 /* I2C1 interrupt */ +-#define SIIH_I2C2 0x00000002 /* I2C2 interrupt */ +-#if defined (CONFIG_MPC8349) +-#define SIIH_SPI 0x00000001 /* SPI interrupt */ +-#define SIIH_RES ~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \ +- | SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \ +- | SIIH_USB2DR | SIIH_USB2MPH | SIIH_UART1 \ +- | SIIH_UART2 | SIIH_SEC | SIIH_I2C1 \ +- | SIIH_I2C2 | SIIH_SPI) +-#endif +-#if defined (CONFIG_MPC8360) +-#define SIIH_RES ~(SIIH_H_QE_H | SIIH_H_QE_L | SIIH_H_UART1 | \ +- SIIH_H_UART2| SIIH_H_SEC | SIIH_H_I2C1 |SIIH_H_I2C2) +-#endif +- u32 sipnr_l; /* System Internal Interrupt Pending Register - Low (SIPNR_L) */ +-#define SIIL_RTCS 0x80000000 /* RTC SECOND interrupt */ +-#define SIIL_PIT 0x40000000 /* PIT interrupt */ +-#define SIIL_PCI1 0x20000000 /* PCI1 interrupt */ +-#if defined (CONFIG_MPC8349) +-#define SIIL_PCI2 0x10000000 /* PCI2 interrupt */ +-#endif +-#define SIIL_RTCA 0x08000000 /* RTC ALARM interrupt */ +-#define SIIL_MU 0x04000000 /* Message Unit interrupt */ +-#define SIIL_SBA 0x02000000 /* System Bus Arbiter interrupt */ +-#define SIIL_DMA 0x01000000 /* DMA interrupt */ +-#define SIIL_GTM4 0x00800000 /* GTM4 interrupt */ +-#define SIIL_GTM8 0x00400000 /* GTM8 interrupt */ +-#if defined (CONFIG_MPC8349) +-#define SIIL_GPIO1 0x00200000 /* GPIO1 interrupt */ +-#define SIIL_GPIO2 0x00100000 /* GPIO2 interrupt */ +-#endif +-#if defined (CONFIG_MPC8360) +-#define SIIL_QEP 0x00200000 /* QE ports interrupt */ +-#define SIIL_SDDR 0x00100000 /* SDDR interrupt */ +-#endif +-#define SIIL_DDR 0x00080000 /* DDR interrupt */ +-#define SIIL_LBC 0x00040000 /* LBC interrupt */ +-#define SIIL_GTM2 0x00020000 /* GTM2 interrupt */ +-#define SIIL_GTM6 0x00010000 /* GTM6 interrupt */ +-#define SIIL_PMC 0x00008000 /* PMC interrupt */ +-#define SIIL_GTM3 0x00000800 /* GTM3 interrupt */ +-#define SIIL_GTM7 0x00000400 /* GTM7 interrupt */ +-#define SIIL_GTM1 0x00000020 /* GTM1 interrupt */ +-#define SIIL_GTM5 0x00000010 /* GTM5 interrupt */ +-#define SIIL_DPTC 0x00000001 /* DPTC interrupt (!!! Invisible for user !!!) */ +-#if defined (CONFIG_MPC8349) +-#define SIIL_RES ~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \ +- | SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \ +- | SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \ +- | SIIL_DDR | SIIL_LBC | SIIL_GTM2 | SIIL_GTM6 \ +- | SIIL_PMC |SIIL_GTM3 | SIIL_GTM7 | SIIL_GTM1 \ +- | SIIL_GTM5 |SIIL_DPTC ) +-#endif +-#if defined (CONFIG_MPC8360) +-#define SIIL_RES ~(SIIL_RTCS |SIIL_PIT |SIIL_PCI1 |SIIL_RTCALR \ +- |SIIL_MU |SIIL_SBA |SIIL_DMA |SIIL_GTM4 |SIIL_GTM8 \ +- |SIIL_QEP | SIIL_SDDR| SIIL_DDR |SIIL_LBC |SIIL_GTM2 \ +- |SIIL_GTM6 |SIIL_PMC |SIIL_GTM3 |SIIL_GTM7 |SIIL_GTM1 \ +- |SIIL_GTM5 ) +-#endif +- u32 siprr_a; /* System Internal Interrupt Group A Priority Register (PRR) */ ++ u32 sicfr; /* System Global Interrupt Configuration Register */ ++ u32 sivcr; /* System Global Interrupt Vector Register */ ++ u32 sipnr_h; /* System Internal Interrupt Pending Register - High */ ++ u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */ ++ u32 siprr_a; /* System Internal Interrupt Group A Priority Register */ + u8 res0[8]; +- u32 siprr_d; /* System Internal Interrupt Group D Priority Register (PRR) */ +- u32 simsr_h; /* System Internal Interrupt Mask Register - High (SIIH) */ +- u32 simsr_l; /* System Internal Interrupt Mask Register - Low (SIIL) */ ++ u32 siprr_d; /* System Internal Interrupt Group D Priority Register */ ++ u32 simsr_h; /* System Internal Interrupt Mask Register - High */ ++ u32 simsr_l; /* System Internal Interrupt Mask Register - Low */ + u8 res1[4]; +- u32 sepnr; /* System External Interrupt Pending Register (SEI) */ +- u32 smprr_a; /* System Mixed Interrupt Group A Priority Register (PRR) */ +- u32 smprr_b; /* System Mixed Interrupt Group B Priority Register (PRR) */ +-#define PRR_0 0xe0000000 /* Priority Register, Position 0 programming */ +-#define PRR_1 0x1c000000 /* Priority Register, Position 1 programming */ +-#define PRR_2 0x03800000 /* Priority Register, Position 2 programming */ +-#define PRR_3 0x00700000 /* Priority Register, Position 3 programming */ +-#define PRR_4 0x0000e000 /* Priority Register, Position 4 programming */ +-#define PRR_5 0x00001c00 /* Priority Register, Position 5 programming */ +-#define PRR_6 0x00000380 /* Priority Register, Position 6 programming */ +-#define PRR_7 0x00000070 /* Priority Register, Position 7 programming */ +-#define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7) +- u32 semsr; /* System External Interrupt Mask Register (SEI) */ +-#define SEI_IRQ0 0x80000000 /* IRQ0 external interrupt */ +-#define SEI_IRQ1 0x40000000 /* IRQ1 external interrupt */ +-#define SEI_IRQ2 0x20000000 /* IRQ2 external interrupt */ +-#define SEI_IRQ3 0x10000000 /* IRQ3 external interrupt */ +-#define SEI_IRQ4 0x08000000 /* IRQ4 external interrupt */ +-#define SEI_IRQ5 0x04000000 /* IRQ5 external interrupt */ +-#define SEI_IRQ6 0x02000000 /* IRQ6 external interrupt */ +-#define SEI_IRQ7 0x01000000 /* IRQ7 external interrupt */ +-#define SEI_SIRQ0 0x00008000 /* SIRQ0 external interrupt */ +-#define SEI_RES ~( SEI_IRQ0 | SEI_IRQ1 | SEI_IRQ2 | SEI_IRQ3 \ +- | SEI_IRQ4 | SEI_IRQ5 | SEI_IRQ6 | SEI_IRQ7 \ +- | SEI_SIRQ0) +- u32 secnr; /* System External Interrupt Control Register (SECNR) */ +-#define SECNR_MIXB0T 0xc0000000 /* MIXB0 priority position IPIC output interrupt type */ +-#define SECNR_MIXB1T 0x30000000 /* MIXB1 priority position IPIC output interrupt type */ +-#define SECNR_MIXA0T 0x00c00000 /* MIXA0 priority position IPIC output interrupt type */ +-#define SECNR_SYSA1T 0x00300000 /* MIXA1 priority position IPIC output interrupt type */ +-#define SECNR_EDI0 0x00008000 /* IRQ0 external interrupt edge/level detect */ +-#define SECNR_EDI1 0x00004000 /* IRQ1 external interrupt edge/level detect */ +-#define SECNR_EDI2 0x00002000 /* IRQ2 external interrupt edge/level detect */ +-#define SECNR_EDI3 0x00001000 /* IRQ3 external interrupt edge/level detect */ +-#define SECNR_EDI4 0x00000800 /* IRQ4 external interrupt edge/level detect */ +-#define SECNR_EDI5 0x00000400 /* IRQ5 external interrupt edge/level detect */ +-#define SECNR_EDI6 0x00000200 /* IRQ6 external interrupt edge/level detect */ +-#define SECNR_EDI7 0x00000100 /* IRQ7 external interrupt edge/level detect */ +-#define SECNR_RES ~( SECNR_MIXB0T | SECNR_MIXB1T | SECNR_MIXA0T \ +- | SECNR_SYSA1T | SECNR_EDI0 | SECNR_EDI1 \ +- | SECNR_EDI2 | SECNR_EDI3 | SECNR_EDI4 \ +- | SECNR_EDI5 | SECNR_EDI6 | SECNR_EDI7) +- u32 sersr; /* System Error Status Register (SERR) */ +- u32 sermr; /* System Error Mask Register (SERR) */ +-#define SERR_IRQ0 0x80000000 /* IRQ0 MCP request */ +-#define SERR_WDT 0x40000000 /* WDT MCP request */ +-#define SERR_SBA 0x20000000 /* SBA MCP request */ +-#if defined (CONFIG_MPC8349) +-#define SERR_DDR 0x10000000 /* DDR MCP request */ +-#define SERR_LBC 0x08000000 /* LBC MCP request */ +-#define SERR_PCI1 0x04000000 /* PCI1 MCP request */ +-#define SERR_PCI2 0x02000000 /* PCI2 MCP request */ +-#endif +-#if defined (CONFIG_MPC8360) +-#define SERR_CIEE 0x10000000 /* CIEE MCP request */ +-#define SERR_CMEE 0x08000000 /* CMEEMCP request */ +-#define SERR_PCI 0x04000000 /* PCI MCP request */ +-#endif +-#define SERR_MU 0x01000000 /* MU MCP request */ +-#define SERR_RNC 0x00010000 /* MU MCP request (!!! Non-visible for users !!!) */ +-#if defined (CONFIG_MPC8349) +-#define SERR_RES ~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \ +- |SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \ +- |SERR_RNC ) +-#elif defined (CONFIG_MPC8360) +-#define SERR_RES ~( SERR_IRQ0|SERR_WDT |SERR_SBA |SERR_CIEE\ +- |SERR_CMEE|SERR_PCI|SERR_MU) +-#endif +- u32 sercr; /* System Error Control Register (SERCR) */ +-#define SERCR_MCPR 0x00000001 /* MCP Route */ +-#define SERCR_RES ~(SERCR_MCPR) ++ u32 sepnr; /* System External Interrupt Pending Register */ ++ u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */ ++ u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */ ++ u32 semsr; /* System External Interrupt Mask Register */ ++ u32 secnr; /* System External Interrupt Control Register */ ++ u32 sersr; /* System Error Status Register */ ++ u32 sermr; /* System Error Mask Register */ ++ u32 sercr; /* System Error Control Register */ + u8 res2[4]; +- u32 sifcr_h; /* System Internal Interrupt Force Register - High (SIIH) */ +- u32 sifcr_l; /* System Internal Interrupt Force Register - Low (SIIL) */ +- u32 sefcr; /* System External Interrupt Force Register (SEI) */ +- u32 serfr; /* System Error Force Register (SERR) */ ++ u32 sifcr_h; /* System Internal Interrupt Force Register - High */ ++ u32 sifcr_l; /* System Internal Interrupt Force Register - Low */ ++ u32 sefcr; /* System External Interrupt Force Register */ ++ u32 serfr; /* System Error Force Register */ + u32 scvcr; /* System Critical Interrupt Vector Register */ +-#define SCVCR_CVECX 0xFC000000 /* Backward (MPC8260) compatible +- critical interrupt vector. */ +-#define SCVCR_CVEC 0x0000007F /* Critical interrupt vector */ +-#define SCVCR_RES ~(SCVCR_CVECX|SCVCR_CVEC) + u32 smvcr; /* System Management Interrupt Vector Register */ +-#define SMVCR_CVECX 0xFC000000 /* Backward (MPC8260) compatible +- critical interrupt vector. */ +-#define SMVCR_CVEC 0x0000007F /* Critical interrupt vector */ +-#define SMVCR_RES ~(SMVCR_CVECX|SMVCR_CVEC) + u8 res3[0x98]; + } ipic83xx_t; + +@@ -491,43 +160,14 @@ typedef struct ipic83xx { + */ + typedef struct arbiter83xx { + u32 acr; /* Arbiter Configuration Register */ +-#define ACR_COREDIS 0x10000000 /* Core disable. */ +-#define ACR_COREDIS_SHIFT (31-7) +-#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth (number of outstanding transactions). */ +-#define ACR_PIPE_DEP_SHIFT (31-15) +-#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */ +-#define ACR_PCI_RPTCNT_SHIFT (31-19) +-#define ACR_RPTCNT 0x00000700 /* Repeat count. */ +-#define ACR_RPTCNT_SHIFT (31-23) +-#define ACR_APARK 0x00000030 /* Address parking. */ +-#define ACR_APARK_SHIFT (31-27) +-#define ACR_PARKM 0x0000000F /* Parking master. */ +-#define ACR_PARKM_SHIFT (31-31) +-#define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM) + u32 atr; /* Arbiter Timers Register */ +-#define ATR_DTO 0x00FF0000 /* Data time out. */ +-#define ATR_ATO 0x000000FF /* Address time out. */ +-#define ATR_RES ~(ATR_DTO|ATR_ATO) + u8 res[4]; +- u32 aer; /* Arbiter Event Register (AE) */ +- u32 aidr; /* Arbiter Interrupt Definition Register (AE) */ +- u32 amr; /* Arbiter Mask Register (AE) */ ++ u32 aer; /* Arbiter Event Register */ ++ u32 aidr; /* Arbiter Interrupt Definition Register */ ++ u32 amr; /* Arbiter Mask Register */ + u32 aeatr; /* Arbiter Event Attributes Register */ +-#define AEATR_EVENT 0x07000000 /* Event type. */ +-#define AEATR_MSTR_ID 0x001F0000 /* Master Id. */ +-#define AEATR_TBST 0x00000800 /* Transfer burst. */ +-#define AEATR_TSIZE 0x00000700 /* Transfer Size. */ +-#define AEATR_TTYPE 0x0000001F /* Transfer Type. */ +-#define AEATR_RES ~(AEATR_EVENT|AEATR_MSTR_ID|AEATR_TBST|AEATR_TSIZE|AEATR_TTYPE) + u32 aeadr; /* Arbiter Event Address Register */ +- u32 aerr; /* Arbiter Event Response Register (AE) */ +-#define AE_ETEA 0x00000020 /* Transfer error. */ +-#define AE_RES_ 0x00000010 /* Reserved transfer type. */ +-#define AE_ECW 0x00000008 /* External control word transfer type. */ +-#define AE_AO 0x00000004 /* Address Only transfer type. */ +-#define AE_DTO 0x00000002 /* Data time out. */ +-#define AE_ATO 0x00000001 /* Address time out. */ +-#define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO) ++ u32 aerr; /* Arbiter Event Response Register */ + u8 res1[0xDC]; + } arbiter83xx_t; + +@@ -535,184 +175,24 @@ typedef struct arbiter83xx { + * Reset Module + */ + typedef struct reset83xx { +- u32 rcwl; /* RCWL Register */ +-#define RCWL_LBIUCM 0x80000000 /* LBIUCM */ +-#define RCWL_LBIUCM_SHIFT 31 +-#define RCWL_DDRCM 0x40000000 /* DDRCM */ +-#define RCWL_DDRCM_SHIFT 30 +-#if defined (CONFIG_MPC8349) +-#define RCWL_SVCOD 0x30000000 /* SVCOD */ +-#endif +-#define RCWL_SPMF 0x0f000000 /* SPMF */ +-#define RCWL_SPMF_SHIFT 24 +-#define RCWL_COREPLL 0x007F0000 /* COREPLL */ +-#define RCWL_COREPLL_SHIFT 16 +-#define RCWL_CEVCOD 0x000000C0 /* CEVCOD */ +-#define RCWL_CEPDF 0x00000020 /* CEPDF */ +-#define RCWL_CEPDF_SHIFT 5 +-#define RCWL_CEPMF 0x0000001F /* CEPMF */ +-#define RCWL_CEPMF_SHIFT 0 +-#if defined (CONFIG_MPC8349) +-#define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF) +-#elif defined (CONFIG_MPC8360) +-#define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SPMF|RCWL_COREPLL|RCWL_CEPDF|RCWL_CEPMF) +-#endif +- u32 rcwh; /* RCHL Register */ +-#define RCWH_PCIHOST 0x80000000 /* PCIHOST */ +-#define RCWH_PCIHOST_SHIFT 31 +-#if defined (CONFIG_MPC8349) +-#define RCWH_PCI64 0x40000000 /* PCI64 */ +-#define RCWH_PCI1ARB 0x20000000 /* PCI1ARB */ +-#define RCWH_PCI2ARB 0x10000000 /* PCI2ARB */ +-#elif defined (CONFIG_MPC8360) +-#define RCWH_PCIARB 0x20000000 /* PCI internal arbiter mode. */ +-#define RCWH_PCICKDRV 0x10000000 /* PCI clock output drive. */ +-#endif +-#define RCWH_COREDIS 0x08000000 /* COREDIS */ +-#define RCWH_BMS 0x04000000 /* BMS */ +-#define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ */ +-#define RCWH_SWEN 0x00800000 /* SWEN */ +-#define RCWH_ROMLOC 0x00700000 /* ROMLOC */ +-#if defined (CONFIG_MPC8349) +-#define RCWH_TSEC1M 0x0000c000 /* TSEC1M */ +-#define RCWH_TSEC2M 0x00003000 /* TSEC2M */ +-#define RCWH_TPR 0x00000100 /* TPR */ +-#elif defined (CONFIG_MPC8360) +-#define RCWH_SDDRIOE 0x00000010 /* Secondary DDR IO Enable. */ +-#endif +-#define RCWH_TLE 0x00000008 /* TLE */ +-#define RCWH_LALE 0x00000004 /* LALE */ +-#if defined (CONFIG_MPC8349) +-#define RCWH_RES ~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \ +- | RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \ +- | RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \ +- | RCWH_TSEC1M | RCWH_TSEC2M | RCWH_TPR \ +- | RCWH_TLE | RCWH_LALE) +-#elif defined (CONFIG_MPC8360) +-#define RCWH_RES ~(RCWH_PCIHOST|RCWH_PCIARB|RCWH_PCICKDRV \ +- |RCWH_COREDIS|RCWH_BMS|RCWH_BOOTSEQ|RCWH_SWEN \ +- |RCWH_SDDRIOE |RCWH_TLE) +-#endif ++ u32 rcwl; /* Reset Configuration Word Low Register */ ++ u32 rcwh; /* Reset Configuration Word High Register */ + u8 res0[8]; +- u32 rsr; /* Reset status Register */ +-#define RSR_RSTSRC 0xE0000000 /* Reset source */ +-#define RSR_RSTSRC_SHIFT 29 +-#define RSR_BSF 0x00010000 /* Boot seq. fail */ +-#define RSR_BSF_SHIFT 16 +-#define RSR_SWSR 0x00002000 /* software soft reset */ +-#define RSR_SWSR_SHIFT 13 +-#define RSR_SWHR 0x00001000 /* software hard reset */ +-#define RSR_SWHR_SHIFT 12 +-#define RSR_JHRS 0x00000200 /* jtag hreset */ +-#define RSR_JHRS_SHIFT 9 +-#define RSR_JSRS 0x00000100 /* jtag sreset status */ +-#define RSR_JSRS_SHIFT 8 +-#define RSR_CSHR 0x00000010 /* checkstop reset status */ +-#define RSR_CSHR_SHIFT 4 +-#define RSR_SWRS 0x00000008 /* software watchdog reset status */ +-#define RSR_SWRS_SHIFT 3 +-#define RSR_BMRS 0x00000004 /* bus monitop reset status */ +-#define RSR_BMRS_SHIFT 2 +-#define RSR_SRS 0x00000002 /* soft reset status */ +-#define RSR_SRS_SHIFT 1 +-#define RSR_HRS 0x00000001 /* hard reset status */ +-#define RSR_HRS_SHIFT 0 +-#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS | RSR_BMRS | RSR_SRS | RSR_HRS) +- u32 rmr; /* Reset mode Register */ +-#define RMR_CSRE 0x00000001 /* checkstop reset enable */ +-#define RMR_CSRE_SHIFT 0 +-#define RMR_RES ~(RMR_CSRE) +- u32 rpr; /* Reset protection Register */ +- u32 rcr; /* Reset Control Register */ +-#define RCR_SWHR 0x00000002 /* software hard reset */ +-#define RCR_SWSR 0x00000001 /* software soft reset */ +-#define RCR_RES ~(RCR_SWHR | RCR_SWSR) +- u32 rcer; /* Reset Control Enable Register */ +-#define RCER_CRE 0x00000001 /* software hard reset */ +-#define RCER_RES ~(RCER_CRE) ++ u32 rsr; /* Reset Status Register */ ++ u32 rmr; /* Reset Mode Register */ ++ u32 rpr; /* Reset protection Register */ ++ u32 rcr; /* Reset Control Register */ ++ u32 rcer; /* Reset Control Enable Register */ + u8 res1[0xDC]; + } reset83xx_t; + ++/* ++ * Clock Module ++ */ + typedef struct clk83xx { +- u32 spmr; /* system PLL mode Register */ +-#define SPMR_LBIUCM 0x80000000 /* LBIUCM */ +-#define SPMR_DDRCM 0x40000000 /* DDRCM */ +-#if defined (CONFIG_MPC8349) +-#define SPMR_SVCOD 0x30000000 /* SVCOD */ +-#endif +-#define SPMR_SPMF 0x0F000000 /* SPMF */ +-#define SPMR_CKID 0x00800000 /* CKID */ +-#define SPMR_CKID_SHIFT 23 +-#define SPMR_COREPLL 0x007F0000 /* COREPLL */ +-#define SPMR_CEVCOD 0x000000C0 /* CEVCOD */ +-#define SPMR_CEPDF 0x00000020 /* CEPDF */ +-#define SPMR_CEPMF 0x0000001F /* CEPMF */ +-#if defined (CONFIG_MPC8349) +-#define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \ +- | SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \ +- | SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF) +-#elif defined (CONFIG_MPC8360) +-#define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SPMF \ +- | SPMR_CKID | SPMR_COREPLL | SPMR_CEVCOD \ +- | SPMR_CEPDF | SPMR_CEPMF) +-#endif +- u32 occr; /* output clock control Register */ +-#define OCCR_PCICOE0 0x80000000 /* PCICOE0 */ +-#define OCCR_PCICOE1 0x40000000 /* PCICOE1 */ +-#define OCCR_PCICOE2 0x20000000 /* PCICOE2 */ +-#if defined (CONFIG_MPC8349) +-#define OCCR_PCICOE3 0x10000000 /* PCICOE3 */ +-#define OCCR_PCICOE4 0x08000000 /* PCICOE4 */ +-#define OCCR_PCICOE5 0x04000000 /* PCICOE5 */ +-#define OCCR_PCICOE6 0x02000000 /* PCICOE6 */ +-#define OCCR_PCICOE7 0x01000000 /* PCICOE7 */ +-#endif +-#define OCCR_PCICD0 0x00800000 /* PCICD0 */ +-#define OCCR_PCICD1 0x00400000 /* PCICD1 */ +-#define OCCR_PCICD2 0x00200000 /* PCICD2 */ +-#if defined (CONFIG_MPC8349) +-#define OCCR_PCICD3 0x00100000 /* PCICD3 */ +-#define OCCR_PCICD4 0x00080000 /* PCICD4 */ +-#define OCCR_PCICD5 0x00040000 /* PCICD5 */ +-#define OCCR_PCICD6 0x00020000 /* PCICD6 */ +-#define OCCR_PCICD7 0x00010000 /* PCICD7 */ +-#define OCCR_PCI1CR 0x00000002 /* PCI1CR */ +-#define OCCR_PCI2CR 0x00000001 /* PCI2CR */ +-#define OCCR_RES ~(OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 \ +- | OCCR_PCICOE3 | OCCR_PCICOE4 | OCCR_PCICOE5 \ +- | OCCR_PCICOE6 | OCCR_PCICOE7 | OCCR_PCICD0 \ +- | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICD3 \ +- | OCCR_PCICD4 | OCCR_PCICD5 | OCCR_PCICD6 \ +- | OCCR_PCICD7 | OCCR_PCI1CR | OCCR_PCI2CR ) +-#endif +-#if defined (CONFIG_MPC8360) +-#define OCCR_PCICR 0x00000002 /* PCI clock rate */ +-#define OCCR_RES ~(OCCR_PCICOE0|OCCR_PCICOE1|OCCR_PCICOE2 \ +- |OCCR_PCICD0|OCCR_PCICD1|OCCR_PCICD2|OCCR_PCICR ) +-#endif +- u32 sccr; /* system clock control Register */ +-#if defined (CONFIG_MPC8349) +-#define SCCR_TSEC1CM 0xc0000000 /* TSEC1CM */ +-#define SCCR_TSEC1CM_SHIFT 30 +-#define SCCR_TSEC2CM 0x30000000 /* TSEC2CM */ +-#define SCCR_TSEC2CM_SHIFT 28 +-#endif +-#define SCCR_ENCCM 0x03000000 /* ENCCM */ +-#define SCCR_ENCCM_SHIFT 24 +-#if defined (CONFIG_MPC8349) +-#define SCCR_USBMPHCM 0x00c00000 /* USBMPHCM */ +-#define SCCR_USBMPHCM_SHIFT 22 +-#define SCCR_USBDRCM 0x00300000 /* USBDRCM */ +-#define SCCR_USBDRCM_SHIFT 20 +-#endif +-#define SCCR_PCICM 0x00010000 /* PCICM */ +-#if defined (CONFIG_MPC8349) +-#define SCCR_RES ~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \ +- | SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM) +-#endif +-#if defined (CONFIG_MPC8360) +-#define SCCR_RES ~(SCCR_ENCCM | SCCR_PCICM) +-#endif ++ u32 spmr; /* system PLL mode Register */ ++ u32 occr; /* output clock control Register */ ++ u32 sccr; /* system clock control Register */ + u8 res0[0xF4]; + } clk83xx_t; + +@@ -720,27 +200,14 @@ typedef struct clk83xx { + * Power Management Control Module + */ + typedef struct pmc83xx { +- u32 pmccr; /* PMC Configuration Register */ +-#define PMCCR_SLPEN 0x00000001 /* System Low Power Enable */ +-#define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable */ +-#if defined (CONFIG_MPC8360) +-#define PMCCR_SDLPEN 0x00000004 /* Secondary DDR SDRAM Low Power Enable */ +-#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN | PMCCR_SDLPEN) +-#elif defined (CONFIG_MPC8349) +-#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN) +-#endif +- u32 pmcer; /* PMC Event Register */ +-#define PMCER_PMCI 0x00000001 /* PMC Interrupt */ +-#define PMCER_RES ~(PMCER_PMCI) +- u32 pmcmr; /* PMC Mask Register */ +-#define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable */ +-#define PMCMR_RES ~(PMCMR_PMCIE) ++ u32 pmccr; /* PMC Configuration Register */ ++ u32 pmcer; /* PMC Event Register */ ++ u32 pmcmr; /* PMC Mask Register */ + u8 res0[0xF4]; + } pmc83xx_t; + +-#if defined (CONFIG_MPC8349) + /* +- * general purpose I/O module ++ * General purpose I/O module + */ + typedef struct gpio83xx { + u32 dir; /* direction register */ +@@ -751,124 +218,20 @@ typedef struct gpio83xx { + u32 icr; /* external interrupt control register */ + u8 res0[0xE8]; + } gpio83xx_t; +-#endif + +-#if defined (CONFIG_MPC8360) + /* + * QE Ports Interrupts Registers + */ + typedef struct qepi83xx { + u8 res0[0xC]; + u32 qepier; /* QE Ports Interrupt Event Register */ +-#define QEPIER_PA15 0x80000000 +-#define QEPIER_PA16 0x40000000 +-#define QEPIER_PA29 0x20000000 +-#define QEPIER_PA30 0x10000000 +-#define QEPIER_PB3 0x08000000 +-#define QEPIER_PB5 0x04000000 +-#define QEPIER_PB12 0x02000000 +-#define QEPIER_PB13 0x01000000 +-#define QEPIER_PB26 0x00800000 +-#define QEPIER_PB27 0x00400000 +-#define QEPIER_PC27 0x00200000 +-#define QEPIER_PC28 0x00100000 +-#define QEPIER_PC29 0x00080000 +-#define QEPIER_PD12 0x00040000 +-#define QEPIER_PD13 0x00020000 +-#define QEPIER_PD16 0x00010000 +-#define QEPIER_PD17 0x00008000 +-#define QEPIER_PD26 0x00004000 +-#define QEPIER_PD27 0x00002000 +-#define QEPIER_PE12 0x00001000 +-#define QEPIER_PE13 0x00000800 +-#define QEPIER_PE24 0x00000400 +-#define QEPIER_PE25 0x00000200 +-#define QEPIER_PE26 0x00000100 +-#define QEPIER_PE27 0x00000080 +-#define QEPIER_PE31 0x00000040 +-#define QEPIER_PF20 0x00000020 +-#define QEPIER_PG31 0x00000010 +-#define QEPIER_RES ~(QEPIER_PA15|QEPIER_PA16|QEPIER_PA29|QEPIER_PA30|QEPIER_PB3 \ +- |QEPIER_PB5|QEPIER_PB12|QEPIER_PB13|QEPIER_PB26|QEPIER_PB27 \ +- |QEPIER_PC27|QEPIER_PC28|QEPIER_PC29|QEPIER_PD12|QEPIER_PD13 \ +- |QEPIER_PD16|QEPIER_PD17|QEPIER_PD26|QEPIER_PD27|QEPIER_PE12 \ +- |QEPIER_PE13|QEPIER_PE24|QEPIER_PE25|QEPIER_PE26|QEPIER_PE27 \ +- |QEPIER_PE31|QEPIER_PF20|QEPIER_PG31) + u32 qepimr; /* QE Ports Interrupt Mask Register */ +-#define QEPIMR_PA15 0x80000000 +-#define QEPIMR_PA16 0x40000000 +-#define QEPIMR_PA29 0x20000000 +-#define QEPIMR_PA30 0x10000000 +-#define QEPIMR_PB3 0x08000000 +-#define QEPIMR_PB5 0x04000000 +-#define QEPIMR_PB12 0x02000000 +-#define QEPIMR_PB13 0x01000000 +-#define QEPIMR_PB26 0x00800000 +-#define QEPIMR_PB27 0x00400000 +-#define QEPIMR_PC27 0x00200000 +-#define QEPIMR_PC28 0x00100000 +-#define QEPIMR_PC29 0x00080000 +-#define QEPIMR_PD12 0x00040000 +-#define QEPIMR_PD13 0x00020000 +-#define QEPIMR_PD16 0x00010000 +-#define QEPIMR_PD17 0x00008000 +-#define QEPIMR_PD26 0x00004000 +-#define QEPIMR_PD27 0x00002000 +-#define QEPIMR_PE12 0x00001000 +-#define QEPIMR_PE13 0x00000800 +-#define QEPIMR_PE24 0x00000400 +-#define QEPIMR_PE25 0x00000200 +-#define QEPIMR_PE26 0x00000100 +-#define QEPIMR_PE27 0x00000080 +-#define QEPIMR_PE31 0x00000040 +-#define QEPIMR_PF20 0x00000020 +-#define QEPIMR_PG31 0x00000010 +-#define QEPIMR_RES ~(QEPIMR_PA15|QEPIMR_PA16|QEPIMR_PA29|QEPIMR_PA30|QEPIMR_PB3 \ +- |QEPIMR_PB5|QEPIMR_PB12|QEPIMR_PB13|QEPIMR_PB26|QEPIMR_PB27 \ +- |QEPIMR_PC27|QEPIMR_PC28|QEPIMR_PC29|QEPIMR_PD12|QEPIMR_PD13 \ +- |QEPIMR_PD16|QEPIMR_PD17|QEPIMR_PD26|QEPIMR_PD27|QEPIMR_PE12 \ +- |QEPIMR_PE13|QEPIMR_PE24|QEPIMR_PE25|QEPIMR_PE26|QEPIMR_PE27 \ +- |QEPIMR_PE31|QEPIMR_PF20|QEPIMR_PG31) + u32 qepicr; /* QE Ports Interrupt Control Register */ +-#define QEPICR_PA15 0x80000000 +-#define QEPICR_PA16 0x40000000 +-#define QEPICR_PA29 0x20000000 +-#define QEPICR_PA30 0x10000000 +-#define QEPICR_PB3 0x08000000 +-#define QEPICR_PB5 0x04000000 +-#define QEPICR_PB12 0x02000000 +-#define QEPICR_PB13 0x01000000 +-#define QEPICR_PB26 0x00800000 +-#define QEPICR_PB27 0x00400000 +-#define QEPICR_PC27 0x00200000 +-#define QEPICR_PC28 0x00100000 +-#define QEPICR_PC29 0x00080000 +-#define QEPICR_PD12 0x00040000 +-#define QEPICR_PD13 0x00020000 +-#define QEPICR_PD16 0x00010000 +-#define QEPICR_PD17 0x00008000 +-#define QEPICR_PD26 0x00004000 +-#define QEPICR_PD27 0x00002000 +-#define QEPICR_PE12 0x00001000 +-#define QEPICR_PE13 0x00000800 +-#define QEPICR_PE24 0x00000400 +-#define QEPICR_PE25 0x00000200 +-#define QEPICR_PE26 0x00000100 +-#define QEPICR_PE27 0x00000080 +-#define QEPICR_PE31 0x00000040 +-#define QEPICR_PF20 0x00000020 +-#define QEPICR_PG31 0x00000010 +-#define QEPICR_RES ~(QEPICR_PA15|QEPICR_PA16|QEPICR_PA29|QEPICR_PA30|QEPICR_PB3 \ +- |QEPICR_PB5|QEPICR_PB12|QEPICR_PB13|QEPICR_PB26|QEPICR_PB27 \ +- |QEPICR_PC27|QEPICR_PC28|QEPICR_PC29|QEPICR_PD12|QEPICR_PD13 \ +- |QEPICR_PD16|QEPICR_PD17|QEPICR_PD26|QEPICR_PD27|QEPICR_PE12 \ +- |QEPICR_PE13|QEPICR_PE24|QEPICR_PE25|QEPICR_PE26|QEPICR_PE27 \ +- |QEPICR_PE31|QEPICR_PF20|QEPICR_PG31) + u8 res1[0xE8]; + } qepi83xx_t; + + /* +- * general purpose I/O module ++ * QE Parallel I/O Ports + */ + typedef struct gpio_n { + u32 podr; /* Open Drain Register */ +@@ -879,238 +242,83 @@ typedef struct gpio_n { + u32 ppar2; /* Pin Assignment Register 2 */ + } gpio_n_t; + +-typedef struct gpio83xx { ++typedef struct qegpio83xx { + gpio_n_t ioport[0x7]; + u8 res0[0x358]; +-} gpio83xx_t; ++} qepio83xx_t; + + /* + * QE Secondary Bus Access Windows + */ +- + typedef struct qesba83xx { + u32 lbmcsar; /* Local bus memory controller start address */ +-#define LBMCSAR_SA 0x000FFFFF /* 20 most-significant bits of the start address */ +-#define LBMCSAR_RES ~(LBMCSAR_SA) + u32 sdmcsar; /* Secondary DDR memory controller start address */ +-#define SDMCSAR_SA 0x000FFFFF /* 20 most-significant bits of the start address */ +-#define SDMCSAR_RES ~(SDMCSAR_SA) + u8 res0[0x38]; + u32 lbmcear; /* Local bus memory controller end address */ +-#define LBMCEAR_EA 0x000FFFFF /* 20 most-significant bits of the end address */ +-#define LBMCEAR_RES ~(LBMCEAR_EA) + u32 sdmcear; /* Secondary DDR memory controller end address */ +-#define SDMCEAR_EA 0x000FFFFF /* 20 most-significant bits of the end address */ +-#define SDMCEAR_RES ~(SDMCEAR_EA) + u8 res1[0x38]; +- u32 lbmcar; /* Local bus memory controller attributes */ +-#define LBMCAR_WEN 0x00000001 /* Forward transactions to the QE local bus */ +-#define LBMCAR_RES ~(LBMCAR_WEN) ++ u32 lbmcar; /* Local bus memory controller attributes */ + u32 sdmcar; /* Secondary DDR memory controller attributes */ +-#define SDMCAR_WEN 0x00000001 /* Forward transactions to the second DDR bus */ +-#define SDMCAR_RES ~(SDMCAR_WEN) +- u8 res2[0x778]; ++ u8 res2[0x378]; + } qesba83xx_t; +-#endif + + /* + * DDR Memory Controller Memory Map + */ + typedef struct ddr_cs_bnds { + u32 csbnds; +-#define CSBNDS_SA 0x00FF0000 +-#define CSBNDS_SA_SHIFT 8 +-#define CSBNDS_EA 0x000000FF +-#define CSBNDS_EA_SHIFT 24 + u8 res0[4]; + } ddr_cs_bnds_t; + + typedef struct ddr83xx { +- ddr_cs_bnds_t csbnds[4]; /**< Chip Select x Memory Bounds */ ++ ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */ + u8 res0[0x60]; +- u32 cs_config[4]; /**< Chip Select x Configuration */ +-#define CSCONFIG_EN 0x80000000 +-#define CSCONFIG_AP 0x00800000 +-#define CSCONFIG_ROW_BIT 0x00000700 +-#define CSCONFIG_ROW_BIT_12 0x00000000 +-#define CSCONFIG_ROW_BIT_13 0x00000100 +-#define CSCONFIG_ROW_BIT_14 0x00000200 +-#define CSCONFIG_COL_BIT 0x00000007 +-#define CSCONFIG_COL_BIT_8 0x00000000 +-#define CSCONFIG_COL_BIT_9 0x00000001 +-#define CSCONFIG_COL_BIT_10 0x00000002 +-#define CSCONFIG_COL_BIT_11 0x00000003 ++ u32 cs_config[4]; /* Chip Select x Configuration */ + u8 res1[0x78]; +- u32 timing_cfg_1; /**< SDRAM Timing Configuration 1 */ +-#define TIMING_CFG1_PRETOACT 0x70000000 +-#define TIMING_CFG1_PRETOACT_SHIFT 28 +-#define TIMING_CFG1_ACTTOPRE 0x0F000000 +-#define TIMING_CFG1_ACTTOPRE_SHIFT 24 +-#define TIMING_CFG1_ACTTORW 0x00700000 +-#define TIMING_CFG1_ACTTORW_SHIFT 20 +-#define TIMING_CFG1_CASLAT 0x00070000 +-#define TIMING_CFG1_CASLAT_SHIFT 16 +-#define TIMING_CFG1_REFREC 0x0000F000 +-#define TIMING_CFG1_REFREC_SHIFT 12 +-#define TIMING_CFG1_WRREC 0x00000700 +-#define TIMING_CFG1_WRREC_SHIFT 8 +-#define TIMING_CFG1_ACTTOACT 0x00000070 +-#define TIMING_CFG1_ACTTOACT_SHIFT 4 +-#define TIMING_CFG1_WRTORD 0x00000007 +-#define TIMING_CFG1_WRTORD_SHIFT 0 +-#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ +-#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ +- +- u32 timing_cfg_2; /**< SDRAM Timing Configuration 2 */ +-#define TIMING_CFG2_CPO 0x0F000000 +-#define TIMING_CFG2_CPO_SHIFT 24 +-#define TIMING_CFG2_ACSM 0x00080000 +-#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 +-#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 +-#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ +- +- u32 sdram_cfg; /**< SDRAM Control Configuration */ +-#define SDRAM_CFG_MEM_EN 0x80000000 +-#define SDRAM_CFG_SREN 0x40000000 +-#define SDRAM_CFG_ECC_EN 0x20000000 +-#define SDRAM_CFG_RD_EN 0x10000000 +-#define SDRAM_CFG_SDRAM_TYPE 0x03000000 +-#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 +-#define SDRAM_CFG_DYN_PWR 0x00200000 +-#define SDRAM_CFG_32_BE 0x00080000 +-#define SDRAM_CFG_8_BE 0x00040000 +-#define SDRAM_CFG_NCAP 0x00020000 +-#define SDRAM_CFG_2T_EN 0x00008000 +-#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000 +- ++ u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ ++ u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ ++ u32 sdram_cfg; /* SDRAM Control Configuration */ + u8 res2[4]; +- u32 sdram_mode; /**< SDRAM Mode Configuration */ +-#define SDRAM_MODE_ESD 0xFFFF0000 +-#define SDRAM_MODE_ESD_SHIFT 16 +-#define SDRAM_MODE_SD 0x0000FFFF +-#define SDRAM_MODE_SD_SHIFT 0 +-#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ +-#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ +-#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ +-#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ +-#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ +-#define DDR_MODE_WEAK 0x0002 /* weak drivers */ +-#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ +-#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ +-#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ +-#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ +-#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ +-#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ +-#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ +-#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ +-#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ +-#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ +-#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125 µs */ +-#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ +-#define DDR_MODE_MODEREG 0x0000 /* select mode register */ +- ++ u32 sdram_mode; /* SDRAM Mode Configuration */ + u8 res3[8]; +- u32 sdram_interval; /**< SDRAM Interval Configuration */ +-#define SDRAM_INTERVAL_REFINT 0x3FFF0000 +-#define SDRAM_INTERVAL_REFINT_SHIFT 16 +-#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF +-#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 ++ u32 sdram_interval; /* SDRAM Interval Configuration */ + u8 res9[8]; + u32 sdram_clk_cntl; +-#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 +-#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 +-#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 +-#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 +-#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 +- + u8 res4[0xCCC]; +- u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */ +- u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */ +- u32 ecc_err_inject; /**< Memory Data Path Error Injection Mask ECC */ +-#define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ +-#define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ +-#define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ +-#define ECC_ERR_INJECT_EEIM_SHIFT 0 ++ u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */ ++ u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */ ++ u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */ + u8 res5[0x14]; +- u32 capture_data_hi; /**< Memory Data Path Read Capture High */ +- u32 capture_data_lo; /**< Memory Data Path Read Capture Low */ +- u32 capture_ecc; /**< Memory Data Path Read Capture ECC */ +-#define CAPTURE_ECC_ECE (0xff000000>>24) +-#define CAPTURE_ECC_ECE_SHIFT 0 ++ u32 capture_data_hi; /* Memory Data Path Read Capture High */ ++ u32 capture_data_lo; /* Memory Data Path Read Capture Low */ ++ u32 capture_ecc; /* Memory Data Path Read Capture ECC */ + u8 res6[0x14]; +- u32 err_detect; /**< Memory Error Detect */ +-#define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ +-#define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ +-#define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ +-#define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ +- u32 err_disable; /**< Memory Error Disable */ +-#define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ +-#define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ +-#define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ +-#define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED|ECC_ERROR_DISABLE_SBED|ECC_ERROR_DISABLE_MBED) +- u32 err_int_en; /**< Memory Error Interrupt Enable */ +-#define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ +-#define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ +-#define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ +-#define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE|ECC_ERR_INT_EN_SBEE|ECC_ERR_INT_EN_MSEE) +- u32 capture_attributes; /**< Memory Error Attributes Capture */ +-#define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ +-#define ECC_CAPT_ATTR_BNUM_SHIFT 28 +-#define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ +-#define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 +-#define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 +-#define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 +-#define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 +-#define ECC_CAPT_ATTR_TSIZ_SHIFT 24 +-#define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ +-#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 +-#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 +-#define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 +-#define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 +-#define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) +-#define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 +-#define ECC_CAPT_ATTR_TSRC_I2C 0x9 +-#define ECC_CAPT_ATTR_TSRC_JTAG 0xA +-#define ECC_CAPT_ATTR_TSRC_PCI1 0xD +-#define ECC_CAPT_ATTR_TSRC_PCI2 0xE +-#define ECC_CAPT_ATTR_TSRC_DMA 0xF +-#define ECC_CAPT_ATTR_TSRC_SHIFT 16 +-#define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ +-#define ECC_CAPT_ATTR_TTYP_WRITE 0x1 +-#define ECC_CAPT_ATTR_TTYP_READ 0x2 +-#define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 +-#define ECC_CAPT_ATTR_TTYP_SHIFT 12 +-#define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ +- u32 capture_address; /**< Memory Error Address Capture */ +- u32 capture_ext_address;/**< Memory Error Extended Address Capture */ +- u32 err_sbe; /**< Memory Single-Bit ECC Error Management */ +-#define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ +-#define ECC_ERROR_MAN_SBET_SHIFT 16 +-#define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ +-#define ECC_ERROR_MAN_SBEC_SHIFT 0 ++ u32 err_detect; /* Memory Error Detect */ ++ u32 err_disable; /* Memory Error Disable */ ++ u32 err_int_en; /* Memory Error Interrupt Enable */ ++ u32 capture_attributes; /* Memory Error Attributes Capture */ ++ u32 capture_address; /* Memory Error Address Capture */ ++ u32 capture_ext_address;/* Memory Error Extended Address Capture */ ++ u32 err_sbe; /* Memory Single-Bit ECC Error Management */ + u8 res7[0xA4]; + u32 debug_reg; + u8 res8[0xFC]; + } ddr83xx_t; + + /* +- * I2C1 Controller +- */ +- +-/* + * DUART + */ + typedef struct duart83xx { +- u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */ +- u8 uier_udmb; /**< combined register for UIER and UDMB */ +- u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */ +- u8 ulcr; /**< line control register */ +- u8 umcr; /**< MODEM control register */ +- u8 ulsr; /**< line status register */ +- u8 umsr; /**< MODEM status register */ +- u8 uscr; /**< scratch register */ ++ u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */ ++ u8 uier_udmb; /* combined register for UIER and UDMB */ ++ u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */ ++ u8 ulcr; /* line control register */ ++ u8 umcr; /* MODEM control register */ ++ u8 ulsr; /* line status register */ ++ u8 umsr; /* MODEM status register */ ++ u8 uscr; /* scratch register */ + u8 res0[8]; +- u8 udsr; /**< DMA status register */ ++ u8 udsr; /* DMA status register */ + u8 res1[3]; + u8 res2[0xEC]; + } duart83xx_t; +@@ -1119,75 +327,52 @@ typedef struct duart83xx { + * Local Bus Controller Registers + */ + typedef struct lbus_bank { +- u32 br; /**< Base Register */ +- u32 or; /**< Base Register */ ++ u32 br; /* Base Register */ ++ u32 or; /* Option Register */ + } lbus_bank_t; + + typedef struct lbus83xx { + lbus_bank_t bank[8]; + u8 res0[0x28]; +- u32 mar; /**< UPM Address Register */ ++ u32 mar; /* UPM Address Register */ + u8 res1[0x4]; +- u32 mamr; /**< UPMA Mode Register */ +- u32 mbmr; /**< UPMB Mode Register */ +- u32 mcmr; /**< UPMC Mode Register */ ++ u32 mamr; /* UPMA Mode Register */ ++ u32 mbmr; /* UPMB Mode Register */ ++ u32 mcmr; /* UPMC Mode Register */ + u8 res2[0x8]; +- u32 mrtpr; /**< Memory Refresh Timer Prescaler Register */ +- u32 mdr; /**< UPM Data Register */ ++ u32 mrtpr; /* Memory Refresh Timer Prescaler Register */ ++ u32 mdr; /* UPM Data Register */ + u8 res3[0x8]; +- u32 lsdmr; /**< SDRAM Mode Register */ ++ u32 lsdmr; /* SDRAM Mode Register */ + u8 res4[0x8]; +- u32 lurt; /**< UPM Refresh Timer */ +- u32 lsrt; /**< SDRAM Refresh Timer */ ++ u32 lurt; /* UPM Refresh Timer */ ++ u32 lsrt; /* SDRAM Refresh Timer */ + u8 res5[0x8]; +- u32 ltesr; /**< Transfer Error Status Register */ +- u32 ltedr; /**< Transfer Error Disable Register */ +- u32 lteir; /**< Transfer Error Interrupt Register */ +- u32 lteatr; /**< Transfer Error Attributes Register */ +- u32 ltear; /**< Transfer Error Address Register */ ++ u32 ltesr; /* Transfer Error Status Register */ ++ u32 ltedr; /* Transfer Error Disable Register */ ++ u32 lteir; /* Transfer Error Interrupt Register */ ++ u32 lteatr; /* Transfer Error Attributes Register */ ++ u32 ltear; /* Transfer Error Address Register */ + u8 res6[0xC]; +- u32 lbcr; /**< Configuration Register */ +-#define LBCR_LDIS 0x80000000 +-#define LBCR_LDIS_SHIFT 31 +-#define LBCR_BCTLC 0x00C00000 +-#define LBCR_BCTLC_SHIFT 22 +-#define LBCR_LPBSE 0x00020000 +-#define LBCR_LPBSE_SHIFT 17 +-#define LBCR_EPAR 0x00010000 +-#define LBCR_EPAR_SHIFT 16 +-#define LBCR_BMT 0x0000FF00 +-#define LBCR_BMT_SHIFT 8 +- u32 lcrr; /**< Clock Ratio Register */ +-#define LCRR_DBYP 0x80000000 +-#define LCRR_DBYP_SHIFT 31 +-#define LCRR_BUFCMDC 0x30000000 +-#define LCRR_BUFCMDC_SHIFT 28 +-#define LCRR_ECL 0x03000000 +-#define LCRR_ECL_SHIFT 24 +-#define LCRR_EADC 0x00030000 +-#define LCRR_EADC_SHIFT 16 +-#define LCRR_CLKDIV 0x0000000F +-#define LCRR_CLKDIV_SHIFT 0 +- ++ u32 lbcr; /* Configuration Register */ ++ u32 lcrr; /* Clock Ratio Register */ + u8 res7[0x28]; + u8 res8[0xF00]; + } lbus83xx_t; + +-#if defined (CONFIG_MPC8349) + /* + * Serial Peripheral Interface + */ + typedef struct spi83xx { +- u32 mode; /**< mode register */ +- u32 event; /**< event register */ +- u32 mask; /**< mask register */ +- u32 com; /**< command register */ ++ u32 mode; /* mode register */ ++ u32 event; /* event register */ ++ u32 mask; /* mask register */ ++ u32 com; /* command register */ + u8 res0[0x10]; +- u32 tx; /**< transmit register */ +- u32 rx; /**< receive register */ +- u8 res1[0xD8]; ++ u32 tx; /* transmit register */ ++ u32 rx; /* receive register */ ++ u8 res1[0xFD8]; + } spi83xx_t; +-#endif + + /* + * DMA/Messaging Unit +@@ -1197,21 +382,17 @@ typedef struct dma83xx { + u32 omisr; /* 0x30 Outbound message interrupt status register */ + u32 omimr; /* 0x34 Outbound message interrupt mask register */ + u32 res1[0x6]; /* 0x38-0x49 reserved */ +- + u32 imr0; /* 0x50 Inbound message register 0 */ + u32 imr1; /* 0x54 Inbound message register 1 */ + u32 omr0; /* 0x58 Outbound message register 0 */ + u32 omr1; /* 0x5C Outbound message register 1 */ +- + u32 odr; /* 0x60 Outbound doorbell register */ + u32 res2; /* 0x64-0x67 reserved */ + u32 idr; /* 0x68 Inbound doorbell register */ + u32 res3[0x5]; /* 0x6C-0x79 reserved */ +- + u32 imisr; /* 0x80 Inbound message interrupt status register */ + u32 imimr; /* 0x84 Inbound message interrupt mask register */ + u32 res4[0x1E]; /* 0x88-0x99 reserved */ +- + u32 dmamr0; /* 0x100 DMA 0 mode register */ + u32 dmasr0; /* 0x104 DMA 0 status register */ + u32 dmacdar0; /* 0x108 DMA 0 current descriptor address register */ +@@ -1223,7 +404,6 @@ typedef struct dma83xx { + u32 dmabcr0; /* 0x120 DMA 0 byte count register */ + u32 dmandar0; /* 0x124 DMA 0 next descriptor address register */ + u32 res8[0x16]; /* 0x128-0x179 reserved */ +- + u32 dmamr1; /* 0x180 DMA 1 mode register */ + u32 dmasr1; /* 0x184 DMA 1 status register */ + u32 dmacdar1; /* 0x188 DMA 1 current descriptor address register */ +@@ -1235,7 +415,6 @@ typedef struct dma83xx { + u32 dmabcr1; /* 0x1A0 DMA 1 byte count register */ + u32 dmandar1; /* 0x1A4 DMA 1 next descriptor address register */ + u32 res12[0x16]; /* 0x1A8-0x199 reserved */ +- + u32 dmamr2; /* 0x200 DMA 2 mode register */ + u32 dmasr2; /* 0x204 DMA 2 status register */ + u32 dmacdar2; /* 0x208 DMA 2 current descriptor address register */ +@@ -1247,7 +426,6 @@ typedef struct dma83xx { + u32 dmabcr2; /* 0x220 DMA 2 byte count register */ + u32 dmandar2; /* 0x224 DMA 2 next descriptor address register */ + u32 res16[0x16]; /* 0x228-0x279 reserved */ +- + u32 dmamr3; /* 0x280 DMA 3 mode register */ + u32 dmasr3; /* 0x284 DMA 3 status register */ + u32 dmacdar3; /* 0x288 DMA 3 current descriptor address register */ +@@ -1258,39 +436,15 @@ typedef struct dma83xx { + u32 res19; /* 0x29C reserved */ + u32 dmabcr3; /* 0x2A0 DMA 3 byte count register */ + u32 dmandar3; /* 0x2A4 DMA 3 next descriptor address register */ +- + u32 dmagsr; /* 0x2A8 DMA general status register */ + u32 res20[0x15]; /* 0x2AC-0x2FF reserved */ + } dma83xx_t; + +-/* DMAMRn bits */ +-#define DMA_CHANNEL_START (0x00000001) /* Bit - DMAMRn CS */ +-#define DMA_CHANNEL_TRANSFER_MODE_DIRECT (0x00000004) /* Bit - DMAMRn CTM */ +-#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN (0x00001000) /* Bit - DMAMRn SAHE */ +-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B (0x00000000) /* 2Bit- DMAMRn SAHTS 1byte */ +-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B (0x00004000) /* 2Bit- DMAMRn SAHTS 2bytes */ +-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B (0x00008000) /* 2Bit- DMAMRn SAHTS 4bytes */ +-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B (0x0000c000) /* 2Bit- DMAMRn SAHTS 8bytes */ +-#define DMA_CHANNEL_SNOOP (0x00010000) /* Bit - DMAMRn DMSEN */ +- +-/* DMASRn bits */ +-#define DMA_CHANNEL_BUSY (0x00000004) /* Bit - DMASRn CB */ +-#define DMA_CHANNEL_TRANSFER_ERROR (0x00000080) /* Bit - DMASRn TE */ +- + /* + * PCI Software Configuration Registers + */ + typedef struct pciconf83xx { + u32 config_address; +-#define PCI_CONFIG_ADDRESS_EN 0x80000000 +-#define PCI_CONFIG_ADDRESS_BN_SHIFT 16 +-#define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 +-#define PCI_CONFIG_ADDRESS_DN_SHIFT 11 +-#define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 +-#define PCI_CONFIG_ADDRESS_FN_SHIFT 8 +-#define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 +-#define PCI_CONFIG_ADDRESS_RN_SHIFT 0 +-#define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc + u32 config_data; + u32 int_ack; + u8 res[116]; +@@ -1313,34 +467,6 @@ typedef struct pci_outbound_window { + */ + typedef struct ios83xx { + pot83xx_t pot[6]; +-#define POTAR_TA_MASK 0x000fffff +-#define POBAR_BA_MASK 0x000fffff +-#define POCMR_EN 0x80000000 +-#define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */ +-#define POCMR_SE 0x20000000 /* streaming enable */ +-#define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2 */ +-#define POCMR_CM_MASK 0x000fffff +-#define POCMR_CM_4G 0x00000000 +-#define POCMR_CM_2G 0x00080000 +-#define POCMR_CM_1G 0x000C0000 +-#define POCMR_CM_512M 0x000E0000 +-#define POCMR_CM_256M 0x000F0000 +-#define POCMR_CM_128M 0x000F8000 +-#define POCMR_CM_64M 0x000FC000 +-#define POCMR_CM_32M 0x000FE000 +-#define POCMR_CM_16M 0x000FF000 +-#define POCMR_CM_8M 0x000FF800 +-#define POCMR_CM_4M 0x000FFC00 +-#define POCMR_CM_2M 0x000FFE00 +-#define POCMR_CM_1M 0x000FFF00 +-#define POCMR_CM_512K 0x000FFF80 +-#define POCMR_CM_256K 0x000FFFC0 +-#define POCMR_CM_128K 0x000FFFE0 +-#define POCMR_CM_64K 0x000FFFF0 +-#define POCMR_CM_32K 0x000FFFF8 +-#define POCMR_CM_16K 0x000FFFFC +-#define POCMR_CM_8K 0x000FFFFE +-#define POCMR_CM_4K 0x000FFFFF + u8 res0[0x60]; + u32 pmcr; + u8 res1[4]; +@@ -1353,74 +479,13 @@ typedef struct ios83xx { + */ + typedef struct pcictrl83xx { + u32 esr; +-#define ESR_MERR 0x80000000 +-#define ESR_APAR 0x00000400 +-#define ESR_PCISERR 0x00000200 +-#define ESR_MPERR 0x00000100 +-#define ESR_TPERR 0x00000080 +-#define ESR_NORSP 0x00000040 +-#define ESR_TABT 0x00000020 + u32 ecdr; +-#define ECDR_APAR 0x00000400 +-#define ECDR_PCISERR 0x00000200 +-#define ECDR_MPERR 0x00000100 +-#define ECDR_TPERR 0x00000080 +-#define ECDR_NORSP 0x00000040 +-#define ECDR_TABT 0x00000020 + u32 eer; +-#define EER_APAR 0x00000400 +-#define EER_PCISERR 0x00000200 +-#define EER_MPERR 0x00000100 +-#define EER_TPERR 0x00000080 +-#define EER_NORSP 0x00000040 +-#define EER_TABT 0x00000020 + u32 eatcr; +-#define EATCR_ERRTYPR_MASK 0x70000000 +-#define EATCR_ERRTYPR_APR 0x00000000 /* address parity error */ +-#define EATCR_ERRTYPR_WDPR 0x10000000 /* write data parity error */ +-#define EATCR_ERRTYPR_RDPR 0x20000000 /* read data parity error */ +-#define EATCR_ERRTYPR_MA 0x30000000 /* master abort */ +-#define EATCR_ERRTYPR_TA 0x40000000 /* target abort */ +-#define EATCR_ERRTYPR_SE 0x50000000 /* system error indication received */ +-#define EATCR_ERRTYPR_PEA 0x60000000 /* parity error indication received on a read */ +-#define EATCR_ERRTYPR_PEW 0x70000000 /* parity error indication received on a write */ +-#define EATCR_BN_MASK 0x0f000000 /* beat number */ +-#define EATCR_BN_1st 0x00000000 +-#define EATCR_BN_2ed 0x01000000 +-#define EATCR_BN_3rd 0x02000000 +-#define EATCR_BN_4th 0x03000000 +-#define EATCR_BN_5th 0x0400000 +-#define EATCR_BN_6th 0x05000000 +-#define EATCR_BN_7th 0x06000000 +-#define EATCR_BN_8th 0x07000000 +-#define EATCR_BN_9th 0x08000000 +-#define EATCR_TS_MASK 0x00300000 /* transaction size */ +-#define EATCR_TS_4 0x00000000 +-#define EATCR_TS_1 0x00100000 +-#define EATCR_TS_2 0x00200000 +-#define EATCR_TS_3 0x00300000 +-#define EATCR_ES_MASK 0x000f0000 /* error source */ +-#define EATCR_ES_EM 0x00000000 /* external master */ +-#define EATCR_ES_DMA 0x00050000 +-#define EATCR_CMD_MASK 0x0000f000 +-#if defined (CONFIG_MPC8349) +-#define EATCR_HBE_MASK 0x00000f00 /* PCI high byte enable */ +-#endif +-#define EATCR_BE_MASK 0x000000f0 /* PCI byte enable */ +-#if defined (CONFIG_MPC8349) +-#define EATCR_HPB 0x00000004 /* high parity bit */ +-#endif +-#define EATCR_PB 0x00000002 /* parity bit */ +-#define EATCR_VI 0x00000001 /* error information valid */ + u32 eacr; + u32 eeacr; +-#if defined (CONFIG_MPC8349) + u32 edlcr; + u32 edhcr; +-#elif defined (CONFIG_MPC8360) +- u32 edcr; /* was edlcr */ +- u8 res_edcr[0x4]; +-#endif + u32 gcr; + u32 ecr; + u32 gsr; +@@ -1443,41 +508,8 @@ typedef struct pcictrl83xx { + u8 res6[4]; + u32 piwar0; + u8 res7[132]; +-#define PITAR_TA_MASK 0x000fffff +-#define PIBAR_MASK 0xffffffff +-#define PIEBAR_EBA_MASK 0x000fffff +-#define PIWAR_EN 0x80000000 +-#define PIWAR_PF 0x20000000 +-#define PIWAR_RTT_MASK 0x000f0000 +-#define PIWAR_RTT_NO_SNOOP 0x00040000 +-#define PIWAR_RTT_SNOOP 0x00050000 +-#define PIWAR_WTT_MASK 0x0000f000 +-#define PIWAR_WTT_NO_SNOOP 0x00004000 +-#define PIWAR_WTT_SNOOP 0x00005000 +-#define PIWAR_IWS_MASK 0x0000003F +-#define PIWAR_IWS_4K 0x0000000B +-#define PIWAR_IWS_8K 0x0000000C +-#define PIWAR_IWS_16K 0x0000000D +-#define PIWAR_IWS_32K 0x0000000E +-#define PIWAR_IWS_64K 0x0000000F +-#define PIWAR_IWS_128K 0x00000010 +-#define PIWAR_IWS_256K 0x00000011 +-#define PIWAR_IWS_512K 0x00000012 +-#define PIWAR_IWS_1M 0x00000013 +-#define PIWAR_IWS_2M 0x00000014 +-#define PIWAR_IWS_4M 0x00000015 +-#define PIWAR_IWS_8M 0x00000016 +-#define PIWAR_IWS_16M 0x00000017 +-#define PIWAR_IWS_32M 0x00000018 +-#define PIWAR_IWS_64M 0x00000019 +-#define PIWAR_IWS_128M 0x0000001A +-#define PIWAR_IWS_256M 0x0000001B +-#define PIWAR_IWS_512M 0x0000001C +-#define PIWAR_IWS_1G 0x0000001D +-#define PIWAR_IWS_2G 0x0000001E + } pcictrl83xx_t; + +-#if defined (CONFIG_MPC8349) + /* + * USB + */ +@@ -1491,7 +523,6 @@ typedef struct usb83xx { + typedef struct tsec83xx { + u8 fixme[0x1000]; + } tsec83xx_t; +-#endif + + /* + * Security +@@ -1500,581 +531,82 @@ typedef struct security83xx { + u8 fixme[0x10000]; + } security83xx_t; + +-#if defined (CONFIG_MPC8360) +-/* +- * iram +- */ +-typedef struct iram83xx { +- u32 iadd; /* I-RAM address register */ +- u32 idata; /* I-RAM data register */ +- u8 res0[0x78]; +-} iram83xx_t; +- +-/* +- * Interrupt Controller +- */ +-typedef struct irq83xx { +- u32 cicr; /* QE system interrupt configuration */ +- u32 civec; /* QE system interrupt vector register */ +- u32 cripnr; /* QE RISC interrupt pending register */ +- u32 cipnr; /* QE system interrupt pending register */ +- u32 cipxcc; /* QE interrupt priority register */ +- u32 cipycc; /* QE interrupt priority register */ +- u32 cipwcc; /* QE interrupt priority register */ +- u32 cipzcc; /* QE interrupt priority register */ +- u32 cimr; /* QE system interrupt mask register */ +- u32 crimr; /* QE RISC interrupt mask register */ +- u32 cicnr; /* QE system interrupt control register */ +- u8 res0[0x4]; +- u32 ciprta; /* QE system interrupt priority register for RISC tasks A */ +- u32 ciprtb; /* QE system interrupt priority register for RISC tasks B */ +- u8 res1[0x4]; +- u32 cricr; /* QE system RISC interrupt control */ +- u8 res2[0x20]; +- u32 chivec; /* QE high system interrupt vector */ +- u8 res3[0x1C]; +-} irq83xx_t; +- +-/* +- * Communications Processor +- */ +-typedef struct cp83xx { +- u32 cecr; /* QE command register */ +- u32 ceccr; /* QE controller configuration register */ +- u32 cecdr; /* QE command data register */ +- u8 res0[0xA]; +- u16 ceter; /* QE timer event register */ +- u8 res1[0x2]; +- u16 cetmr; /* QE timers mask register */ +- u32 cetscr; /* QE time-stamp timer control register */ +- u32 cetsr1; /* QE time-stamp register 1 */ +- u32 cetsr2; /* QE time-stamp register 2 */ +- u8 res2[0x8]; +- u32 cevter; /* QE virtual tasks event register */ +- u32 cevtmr; /* QE virtual tasks mask register */ +- u16 cercr; /* QE RAM control register */ +- u8 res3[0x2]; +- u8 res4[0x24]; +- u16 ceexe1; /* QE external request 1 event register */ +- u8 res5[0x2]; +- u16 ceexm1; /* QE external request 1 mask register */ +- u8 res6[0x2]; +- u16 ceexe2; /* QE external request 2 event register */ +- u8 res7[0x2]; +- u16 ceexm2; /* QE external request 2 mask register */ +- u8 res8[0x2]; +- u16 ceexe3; /* QE external request 3 event register */ +- u8 res9[0x2]; +- u16 ceexm3; /* QE external request 3 mask register */ +- u8 res10[0x2]; +- u16 ceexe4; /* QE external request 4 event register */ +- u8 res11[0x2]; +- u16 ceexm4; /* QE external request 4 mask register */ +- u8 res12[0x2]; +- u8 res13[0x280]; +-} cp83xx_t; +- +-/* +- * QE Multiplexer +- */ +- +-typedef struct qmx83xx { +- u32 cmxgcr; /* CMX general clock route register */ +- u32 cmxsi1cr_l; /* CMX SI1 clock route low register */ +- u32 cmxsi1cr_h; /* CMX SI1 clock route high register */ +- u32 cmxsi1syr; /* CMX SI1 SYNC route register */ +- u32 cmxucr1; /* CMX UCC1, UCC3 clock route register */ +- u32 cmxucr2; /* CMX UCC5, UCC7 clock route register */ +- u32 cmxucr3; /* CMX UCC2, UCC4 clock route register */ +- u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */ +- u32 cmxupcr; /* CMX UPC clock route register */ +- u8 res0[0x1C]; +-} qmx83xx_t; +- +-/* +-* QE Timers +-*/ +- +-typedef struct qet83xx { +- u8 gtcfr1; /* Timer 1 and Timer 2 global configuration register */ +- u8 res0[0x3]; +- u8 gtcfr2; /* Timer 3 and timer 4 global configuration register */ +- u8 res1[0xB]; +- u16 gtmdr1; /* Timer 1 mode register */ +- u16 gtmdr2; /* Timer 2 mode register */ +- u16 gtrfr1; /* Timer 1 reference register */ +- u16 gtrfr2; /* Timer 2 reference register */ +- u16 gtcpr1; /* Timer 1 capture register */ +- u16 gtcpr2; /* Timer 2 capture register */ +- u16 gtcnr1; /* Timer 1 counter */ +- u16 gtcnr2; /* Timer 2 counter */ +- u16 gtmdr3; /* Timer 3 mode register */ +- u16 gtmdr4; /* Timer 4 mode register */ +- u16 gtrfr3; /* Timer 3 reference register */ +- u16 gtrfr4; /* Timer 4 reference register */ +- u16 gtcpr3; /* Timer 3 capture register */ +- u16 gtcpr4; /* Timer 4 capture register */ +- u16 gtcnr3; /* Timer 3 counter */ +- u16 gtcnr4; /* Timer 4 counter */ +- u16 gtevr1; /* Timer 1 event register */ +- u16 gtevr2; /* Timer 2 event register */ +- u16 gtevr3; /* Timer 3 event register */ +- u16 gtevr4; /* Timer 4 event register */ +- u16 gtps; /* Timer 1 prescale register */ +- u8 res2[0x46]; +-} qet83xx_t; +- +-/* +-* spi +-*/ +- +-typedef struct spi83xx { +- u8 res0[0x20]; +- u32 spmode; /* SPI mode register */ +- u8 res1[0x2]; +- u8 spie; /* SPI event register */ +- u8 res2[0x1]; +- u8 res3[0x2]; +- u8 spim; /* SPI mask register */ +- u8 res4[0x1]; +- u8 res5[0x1]; +- u8 spcom; /* SPI command register */ +- u8 res6[0x2]; +- u32 spitd; /* SPI transmit data register (cpu mode) */ +- u32 spird; /* SPI receive data register (cpu mode) */ +- u8 res7[0x8]; +-} spi83xx_t; +- +-/* +-* mcc +-*/ +- +-typedef struct mcc83xx { +- u32 mcce; /* MCC event register */ +- u32 mccm; /* MCC mask register */ +- u32 mccf; /* MCC configuration register */ +- u32 merl; /* MCC emergency request level register */ +- u8 res0[0xF0]; +-} mcc83xx_t; +- +-/* +-* brg +-*/ +- +-typedef struct brg83xx { +- u32 brgc1; /* BRG1 configuration register */ +- u32 brgc2; /* BRG2 configuration register */ +- u32 brgc3; /* BRG3 configuration register */ +- u32 brgc4; /* BRG4 configuration register */ +- u32 brgc5; /* BRG5 configuration register */ +- u32 brgc6; /* BRG6 configuration register */ +- u32 brgc7; /* BRG7 configuration register */ +- u32 brgc8; /* BRG8 configuration register */ +- u32 brgc9; /* BRG9 configuration register */ +- u32 brgc10; /* BRG10 configuration register */ +- u32 brgc11; /* BRG11 configuration register */ +- u32 brgc12; /* BRG12 configuration register */ +- u32 brgc13; /* BRG13 configuration register */ +- u32 brgc14; /* BRG14 configuration register */ +- u32 brgc15; /* BRG15 configuration register */ +- u32 brgc16; /* BRG16 configuration register */ +- u8 res0[0x40]; +-} brg83xx_t; +- +-/* +-* USB +-*/ +- +-typedef struct usb83xx { +- u8 usmod; /* USB mode register */ +- u8 usadd; /* USB address register */ +- u8 uscom; /* USB command register */ +- u8 res0[0x1]; +- u16 usep0; /* USB endpoint register 0 */ +- u16 usep1; /* USB endpoint register 1 */ +- u16 usep2; /* USB endpoint register 2 */ +- u16 usep3; /* USB endpoint register 3 */ +- u8 res1[0x4]; +- u16 usber; /* USB event register */ +- u8 res2[0x2]; +- u16 usbmr; /* USB mask register */ +- u8 res3[0x1]; +- u8 usbs; /* USB status register */ +- u32 ussft; /* USB start of frame timer */ +- u8 res4[0x24]; +-} usb83xx_t; +- +-/* +-* SI +-*/ +- +-typedef struct si1_83xx { +- u16 siamr1; /* SI1 TDMA mode register */ +- u16 sibmr1; /* SI1 TDMB mode register */ +- u16 sicmr1; /* SI1 TDMC mode register */ +- u16 sidmr1; /* SI1 TDMD mode register */ +- u8 siglmr1_h; /* SI1 global mode register high */ +- u8 res0[0x1]; +- u8 sicmdr1_h; /* SI1 command register high */ +- u8 res2[0x1]; +- u8 sistr1_h; /* SI1 status register high */ +- u8 res3[0x1]; +- u16 sirsr1_h; /* SI1 RAM shadow address register high */ +- u8 sitarc1; /* SI1 RAM counter Tx TDMA */ +- u8 sitbrc1; /* SI1 RAM counter Tx TDMB */ +- u8 sitcrc1; /* SI1 RAM counter Tx TDMC */ +- u8 sitdrc1; /* SI1 RAM counter Tx TDMD */ +- u8 sirarc1; /* SI1 RAM counter Rx TDMA */ +- u8 sirbrc1; /* SI1 RAM counter Rx TDMB */ +- u8 sircrc1; /* SI1 RAM counter Rx TDMC */ +- u8 sirdrc1; /* SI1 RAM counter Rx TDMD */ +- u8 res4[0x8]; +- u16 siemr1; /* SI1 TDME mode register 16 bits */ +- u16 sifmr1; /* SI1 TDMF mode register 16 bits */ +- u16 sigmr1; /* SI1 TDMG mode register 16 bits */ +- u16 sihmr1; /* SI1 TDMH mode register 16 bits */ +- u8 siglmg1_l; /* SI1 global mode register low 8 bits */ +- u8 res5[0x1]; +- u8 sicmdr1_l; /* SI1 command register low 8 bits */ +- u8 res6[0x1]; +- u8 sistr1_l; /* SI1 status register low 8 bits */ +- u8 res7[0x1]; +- u16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits */ +- u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */ +- u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */ +- u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */ +- u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */ +- u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */ +- u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */ +- u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */ +- u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */ +- u8 res8[0x8]; +- u32 siml1; /* SI1 multiframe limit register */ +- u8 siedm1; /* SI1 extended diagnostic mode register */ +- u8 res9[0xBB]; +-} si1_83xx_t; +- +-/* +-* SI Routing Tables +-*/ +- +-typedef struct sir83xx { +- u8 tx[0x400]; +- u8 rx[0x400]; +- u8 res0[0x800]; +-} sir83xx_t; +- +-/* +-* ucc +-*/ +- +-typedef struct uslow { +- u32 gumr_l; /* UCCx general mode register (low) */ +- u32 gumr_h; /* UCCx general mode register (high) */ +- u16 upsmr; /* UCCx protocol-specific mode register */ +- u8 res0[0x2]; +- u16 utodr; /* UCCx transmit on demand register */ +- u16 udsr; /* UCCx data synchronization register */ +- u16 ucce; /* UCCx event register */ +- u8 res1[0x2]; +- u16 uccm; /* UCCx mask register */ +- u8 res2[0x1]; +- u8 uccs; /* UCCx status register */ +- u8 res3[0x1E8]; +-} uslow_t; +- +-typedef struct ufast { +- u32 gumr; /* UCCx general mode register */ +- u32 upsmr; /* UCCx protocol-specific mode register */ +- u16 utodr; /* UCCx transmit on demand register */ +- u8 res0[0x2]; +- u16 udsr; /* UCCx data synchronization register */ +- u8 res1[0x2]; +- u32 ucce; /* UCCx event register */ +- u32 uccm; /* UCCx mask register. */ +- u8 uccs; /* UCCx status register */ +- u8 res2[0x7]; +- u32 urfb; /* UCC receive FIFO base */ +- u16 urfs; /* UCC receive FIFO size */ +- u8 res3[0x2]; +- u16 urfet; /* UCC receive FIFO emergency threshold */ +- u16 urfset; /* UCC receive FIFO special emergency threshold */ +- u32 utfb; /* UCC transmit FIFO base */ +- u16 utfs; /* UCC transmit FIFO size */ +- u8 res4[0x2]; +- u16 utfet; /* UCC transmit FIFO emergency threshold */ +- u8 res5[0x2]; +- u16 utftt; /* UCC transmit FIFO transmit threshold */ +- u8 res6[0x2]; +- u16 utpt; /* UCC transmit polling timer */ +- u32 urtry; /* UCC retry counter register */ +- u8 res7[0x4C]; +- u8 guemr; /* UCC general extended mode register */ +- u8 res8[0x3]; +- u8 res9[0x6C]; +- u32 maccfg1; /* Mac configuration register #1 */ +- u32 maccfg2; /* Mac configuration register #2 */ +- u16 ipgifg; /* Interframe gap register */ +- u8 res10[0x2]; +- u32 hafdup; /* Half-duplex register */ +- u8 res11[0xC]; +- u32 emtr; /* Ethernet MAC test register */ +- u32 miimcfg; /* MII mgmt configuration register */ +- u32 miimcom; /* MII mgmt command register */ +- u32 miimadd; /* MII mgmt address register */ +- u32 miimcon; /* MII mgmt control register */ +- u32 miistat; /* MII mgmt status register */ +- u32 miimnd; /* MII mgmt indication register */ +- u32 ifctl; /* Interface control register */ +- u32 ifstat; /* Interface status register */ +- u32 macstnaddr1; /* Station address part 1 register */ +- u32 macstnaddr2; /* Station address part 2 register */ +- u8 res12[0x8]; +- u32 uempr; /* UCC Ethernet MAC parameter register */ +- u32 utbipa; /* UCC TBI address */ +- u16 uescr; /* UCC Ethernet statistics control register */ +- u8 res13[0x26]; +- u32 tx64; /* Transmit and receive 64-byte frame counter */ +- u32 tx127; /* Transmit and receive 65- to 127-byte frame counter */ +- u32 tx255; /* Transmit and receive 128- to 255-byte frame counter */ +- u32 rx64; /* Receive and receive 64-byte frame counter */ +- u32 rx127; /* Receive and receive 65- to 127-byte frame counter */ +- u32 rx255; /* Receive and receive 128- to 255-byte frame counter */ +- u32 txok; /* Transmit good bytes counter */ +- u32 txcf; /* Transmit control frame counter */ +- u32 tmca; /* Transmit multicast control frame counter */ +- u32 tbca; /* Transmit broadcast packet counter */ +- u32 rxfok; /* Receive frame OK counter */ +- u32 rbyt; /* Receive good and bad bytes counter */ +- u32 rxbok; /* Receive bytes OK counter */ +- u32 rmca; /* Receive multicast packet counter */ +- u32 rbca; /* Receive broadcast packet counter */ +- u32 scar; /* Statistics carry register */ +- u32 scam; /* Statistics carry mask register */ +- u8 res14[0x3C]; +-} ufast_t; +- +-typedef struct ucc83xx { +- union { +- uslow_t slow; +- ufast_t fast; +- }; +-} ucc83xx_t; +- +-/* +-* MultiPHY UTOPIA POS Controllers +-*/ +- +-typedef struct upc83xx { +- u32 upgcr; /* UTOPIA/POS general configuration register */ +-#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */ +-#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */ +-#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */ +-#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing: */ +-#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */ +- u32 uplpa; /* UTOPIA/POS last PHY address */ +- u32 uphec; /* ATM HEC register */ +- u32 upuc; /* UTOPIA/POS UCC configuration */ +- u32 updc1; /* UTOPIA/POS device 1 configuration */ +- u32 updc2; /* UTOPIA/POS device 2 configuration */ +- u32 updc3; /* UTOPIA/POS device 3 configuration */ +- u32 updc4; /* UTOPIA/POS device 4 configuration */ +- u32 upstpa; /* UTOPIA/POS STPA threshold */ +- u8 res0[0xC]; +- u32 updrs1_h; /* UTOPIA/POS device 1 rate select */ +- u32 updrs1_l; /* UTOPIA/POS device 1 rate select */ +- u32 updrs2_h; /* UTOPIA/POS device 2 rate select */ +- u32 updrs2_l; /* UTOPIA/POS device 2 rate select */ +- u32 updrs3_h; /* UTOPIA/POS device 3 rate select */ +- u32 updrs3_l; /* UTOPIA/POS device 3 rate select */ +- u32 updrs4_h; /* UTOPIA/POS device 4 rate select */ +- u32 updrs4_l; /* UTOPIA/POS device 4 rate select */ +- u32 updrp1; /* UTOPIA/POS device 1 receive priority low */ +- u32 updrp2; /* UTOPIA/POS device 2 receive priority low */ +- u32 updrp3; /* UTOPIA/POS device 3 receive priority low */ +- u32 updrp4; /* UTOPIA/POS device 4 receive priority low */ +- u32 upde1; /* UTOPIA/POS device 1 event */ +- u32 upde2; /* UTOPIA/POS device 2 event */ +- u32 upde3; /* UTOPIA/POS device 3 event */ +- u32 upde4; /* UTOPIA/POS device 4 event */ +- u16 uprp1; +- u16 uprp2; +- u16 uprp3; +- u16 uprp4; +- u8 res1[0x8]; +- u16 uptirr1_0; /* Device 1 transmit internal rate 0 */ +- u16 uptirr1_1; /* Device 1 transmit internal rate 1 */ +- u16 uptirr1_2; /* Device 1 transmit internal rate 2 */ +- u16 uptirr1_3; /* Device 1 transmit internal rate 3 */ +- u16 uptirr2_0; /* Device 2 transmit internal rate 0 */ +- u16 uptirr2_1; /* Device 2 transmit internal rate 1 */ +- u16 uptirr2_2; /* Device 2 transmit internal rate 2 */ +- u16 uptirr2_3; /* Device 2 transmit internal rate 3 */ +- u16 uptirr3_0; /* Device 3 transmit internal rate 0 */ +- u16 uptirr3_1; /* Device 3 transmit internal rate 1 */ +- u16 uptirr3_2; /* Device 3 transmit internal rate 2 */ +- u16 uptirr3_3; /* Device 3 transmit internal rate 3 */ +- u16 uptirr4_0; /* Device 4 transmit internal rate 0 */ +- u16 uptirr4_1; /* Device 4 transmit internal rate 1 */ +- u16 uptirr4_2; /* Device 4 transmit internal rate 2 */ +- u16 uptirr4_3; /* Device 4 transmit internal rate 3 */ +- u32 uper1; /* Device 1 port enable register */ +- u32 uper2; /* Device 2 port enable register */ +- u32 uper3; /* Device 3 port enable register */ +- u32 uper4; /* Device 4 port enable register */ +- u8 res2[0x150]; +-} upc83xx_t; +- +-/* +-* SDMA +-*/ +- +-typedef struct sdma83xx { +- u32 sdsr; /* Serial DMA status register */ +- u32 sdmr; /* Serial DMA mode register */ +- u32 sdtr1; /* SDMA system bus threshold register */ +- u32 sdtr2; /* SDMA secondary bus threshold register */ +- u32 sdhy1; /* SDMA system bus hysteresis register */ +- u32 sdhy2; /* SDMA secondary bus hysteresis register */ +- u32 sdta1; /* SDMA system bus address register */ +- u32 sdta2; /* SDMA secondary bus address register */ +- u32 sdtm1; /* SDMA system bus MSNUM register */ +- u32 sdtm2; /* SDMA secondary bus MSNUM register */ +- u8 res0[0x10]; +- u32 sdaqr; /* SDMA address bus qualify register */ +- u32 sdaqmr; /* SDMA address bus qualify mask register */ +- u8 res1[0x4]; +- u32 sdwbcr; /* SDMA CAM entries base register */ +- u8 res2[0x38]; +-} sdma83xx_t; +- +-/* +-* Debug Space +-*/ +- +-typedef struct dbg83xx { +- u32 bpdcr; /* Breakpoint debug command register */ +- u32 bpdsr; /* Breakpoint debug status register */ +- u32 bpdmr; /* Breakpoint debug mask register */ +- u32 bprmrr0; /* Breakpoint request mode risc register 0 */ +- u32 bprmrr1; /* Breakpoint request mode risc register 1 */ +- u8 res0[0x8]; +- u32 bprmtr0; /* Breakpoint request mode trb register 0 */ +- u32 bprmtr1; /* Breakpoint request mode trb register 1 */ +- u8 res1[0x8]; +- u32 bprmir; /* Breakpoint request mode immediate register */ +- u32 bprmsr; /* Breakpoint request mode serial register */ +- u32 bpemr; /* Breakpoint exit mode register */ +- u8 res2[0x48]; +-} dbg83xx_t; +- +-/* +-* RISC Special Registers (Trap and Breakpoint) +-*/ +- +-typedef struct rsp83xx { +- u8 fixme[0x100]; +-} rsp83xx_t; +-#endif ++#if defined(CONFIG_MPC8349) ++typedef struct immap { ++ sysconf83xx_t sysconf; /* System configuration */ ++ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ ++ rtclk83xx_t rtc; /* Real Time Clock Module Registers */ ++ rtclk83xx_t pit; /* Periodic Interval Timer */ ++ gtm83xx_t gtm[2]; /* Global Timers Module */ ++ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ ++ arbiter83xx_t arbiter; /* System Arbiter Registers */ ++ reset83xx_t reset; /* Reset Module */ ++ clk83xx_t clk; /* System Clock Module */ ++ pmc83xx_t pmc; /* Power Management Control Module */ ++ gpio83xx_t gpio[2]; /* General purpose I/O module */ ++ u8 res0[0x200]; ++ u8 dll_ddr[0x100]; ++ u8 dll_lbc[0x100]; ++ u8 res1[0xE00]; ++ ddr83xx_t ddr; /* DDR Memory Controller Memory */ ++ fsl_i2c_t i2c[2]; /* I2C Controllers */ ++ u8 res2[0x1300]; ++ duart83xx_t duart[2]; /* DUART */ ++ u8 res3[0x900]; ++ lbus83xx_t lbus; /* Local Bus Controller Registers */ ++ u8 res4[0x1000]; ++ spi83xx_t spi; /* Serial Peripheral Interface */ ++ dma83xx_t dma; /* DMA */ ++ pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */ ++ ios83xx_t ios; /* Sequencer */ ++ pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */ ++ u8 res5[0x19900]; ++ usb83xx_t usb; ++ tsec83xx_t tsec[2]; ++ u8 res6[0xA000]; ++ security83xx_t security; ++ u8 res7[0xC0000]; ++} immap_t; + ++#elif defined(CONFIG_MPC8360) + typedef struct immap { +- sysconf83xx_t sysconf; /* System configuration */ +- wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ +- rtclk83xx_t rtc; /* Real Time Clock Module Registers */ +- rtclk83xx_t pit; /* Periodic Interval Timer */ +- gtm83xx_t gtm[2]; /* Global Timers Module */ +- ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ +- arbiter83xx_t arbiter; /* System Arbiter Registers */ +- reset83xx_t reset; /* Reset Module */ +- clk83xx_t clk; /* System Clock Module */ +- pmc83xx_t pmc; /* Power Management Control Module */ +-#if defined (CONFIG_MPC8349) +- gpio83xx_t pgio[2]; /* general purpose I/O module */ +-#elif defined (CONFIG_MPC8360) +- qepi83xx_t qepi; /* QE Ports Interrupts Registers */ +-#endif +- u8 res0[0x200]; +-#if defined (CONFIG_MPC8360) +- u8 DLL_LBDDR[0x100]; +-#endif +- u8 DDL_DDR[0x100]; +- u8 DDL_LBIU[0x100]; +-#if defined (CONFIG_MPC8349) +- u8 res1[0xE00]; +-#elif defined (CONFIG_MPC8360) +- u8 res1[0x200]; +- gpio83xx_t gpio; /* General purpose I/O module */ +- qesba83xx_t qesba; /* QE Secondary Bus Access Windows */ +-#endif +- ddr83xx_t ddr; /* DDR Memory Controller Memory */ +- fsl_i2c_t i2c[2]; /* I2C Controllers */ +- u8 res2[0x1300]; +- duart83xx_t duart[2]; /* DUART */ +-#if defined (CONFIG_MPC8349) +- u8 res3[0x900]; +- lbus83xx_t lbus; /* Local Bus Controller Registers */ +- u8 res4[0x1000]; +- spi83xx_t spi; /* Serial Peripheral Interface */ +- u8 res5[0xF00]; +-#elif defined (CONFIG_MPC8360) +- u8 res3[0x900]; +- lbus83xx_t lbus; /* Local Bus Controller */ +- u8 res4[0x2000]; +-#endif +- dma83xx_t dma; /* DMA */ +-#if defined (CONFIG_MPC8349) +- pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */ +- ios83xx_t ios; /* Sequencer */ +- pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */ +- u8 res6[0x19900]; +- usb83xx_t usb; +- tsec83xx_t tsec[2]; +- u8 res7[0xA000]; +- security83xx_t security; +-#elif defined (CONFIG_MPC8360) +- pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ +- u8 res_5[128]; +- ios83xx_t ios; /* Sequencer (IOS) */ +- pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ +- u8 res6[0x4A00]; +- ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */ +- u8 res7[0x22000]; +- security83xx_t security; +- u8 res8[0xC0000]; +- iram83xx_t iram; /* IRAM */ +- irq83xx_t irq; /* Interrupt Controller */ +- cp83xx_t cp; /* Communications Processor */ +- qmx83xx_t qmx; /* QE Multiplexer */ +- qet83xx_t qet; /* QE Timers */ +- spi83xx_t spi[0x2]; /* spi */ +- mcc83xx_t mcc; /* mcc */ +- brg83xx_t brg; /* brg */ +- usb83xx_t usb; /* USB */ +- si1_83xx_t si1; /* SI */ +- u8 res9[0x800]; +- sir83xx_t sir; /* SI Routing Tables */ +- ucc83xx_t ucc1; /* ucc1 */ +- ucc83xx_t ucc3; /* ucc3 */ +- ucc83xx_t ucc5; /* ucc5 */ +- ucc83xx_t ucc7; /* ucc7 */ +- u8 res10[0x600]; +- upc83xx_t upc1; /* MultiPHY UTOPIA POS Controller 1 */ +- ucc83xx_t ucc2; /* ucc2 */ +- ucc83xx_t ucc4; /* ucc4 */ +- ucc83xx_t ucc6; /* ucc6 */ +- ucc83xx_t ucc8; /* ucc8 */ +- u8 res11[0x600]; +- upc83xx_t upc2; /* MultiPHY UTOPIA POS Controller 2 */ +- sdma83xx_t sdma; /* SDMA */ +- dbg83xx_t dbg; /* Debug Space */ +- rsp83xx_t rsp[0x2]; /* RISC Special Registers (Trap and Breakpoint) */ +- u8 res12[0x300]; +- u8 res13[0x3A00]; +- u8 res14[0x8000]; /* 0x108000 - 0x110000 */ +- u8 res15[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */ +- u8 res16[0x24000]; /* 0x11C000 - 0x140000 */ +- u8 res17[0xC0000]; /* 0x140000 - 0x200000 */ +-#endif ++ sysconf83xx_t sysconf; /* System configuration */ ++ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ ++ rtclk83xx_t rtc; /* Real Time Clock Module Registers */ ++ rtclk83xx_t pit; /* Periodic Interval Timer */ ++ u8 res0[0x200]; ++ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ ++ arbiter83xx_t arbiter; /* System Arbiter Registers */ ++ reset83xx_t reset; /* Reset Module */ ++ clk83xx_t clk; /* System Clock Module */ ++ pmc83xx_t pmc; /* Power Management Control Module */ ++ qepi83xx_t qepi; /* QE Ports Interrupts Registers */ ++ u8 res1[0x300]; ++ u8 dll_ddr[0x100]; ++ u8 dll_lbc[0x100]; ++ u8 res2[0x200]; ++ qepio83xx_t qepio; /* QE Parallel I/O ports */ ++ qesba83xx_t qesba; /* QE Secondary Bus Access Windows */ ++ u8 res3[0x400]; ++ ddr83xx_t ddr; /* DDR Memory Controller Memory */ ++ fsl_i2c_t i2c[2]; /* I2C Controllers */ ++ u8 res4[0x1300]; ++ duart83xx_t duart[2]; /* DUART */ ++ u8 res5[0x900]; ++ lbus83xx_t lbus; /* Local Bus Controller Registers */ ++ u8 res6[0x2000]; ++ dma83xx_t dma; /* DMA */ ++ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ ++ u8 res7[128]; ++ ios83xx_t ios; /* Sequencer (IOS) */ ++ pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ ++ u8 res8[0x4A00]; ++ ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */ ++ u8 res9[0x22000]; ++ security83xx_t security; ++ u8 res10[0xC0000]; ++ u8 qe[0x100000]; /* QE block */ + } immap_t; ++#endif + + #endif /* __IMMAP_83xx__ */ +diff --git a/include/mpc83xx.h b/include/mpc83xx.h +index 03dd0ca..504b6a9 100644 +--- a/include/mpc83xx.h ++++ b/include/mpc83xx.h +@@ -10,12 +10,6 @@ + * the License, or (at your option) any later version. + */ + +-/* +- * mpc83xx.h +- * +- * MPC83xx specific definitions +- */ +- + #ifndef __MPC83XX_H__ + #define __MPC83XX_H__ + +@@ -24,406 +18,941 @@ + #include + #endif + +-/* +- * MPC83xx cpu provide RCR register to do reset thing specially. easier +- * to implement ++/* MPC83xx cpu provide RCR register to do reset thing specially + */ +- + #define MPC83xx_RESET + +-/* +- * System reset offset (PowerPC standard) ++/* System reset offset (PowerPC standard) + */ +-#define EXC_OFF_SYS_RESET 0x0100 ++#define EXC_OFF_SYS_RESET 0x0100 + +-/* +- * Default Internal Memory Register Space (Freescale recomandation) ++/* IMMRBAR - Internal Memory Register Base Address + */ +-#define CONFIG_DEFAULT_IMMR 0xFF400000 ++#define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ ++#define IMMRBAR 0x0000 /* Register offset to immr */ ++#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ ++#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) + +-/* +- * Watchdog ++/* LAWBAR - Local Access Window Base Address Register + */ +-#define SWCRR 0x0204 +-#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */ +-#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */ +-#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit. */ +-#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */ +-#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) ++#define LBLAWBAR0 0x0020 /* Register offset to immr */ ++#define LBLAWAR0 0x0024 ++#define LBLAWBAR1 0x0028 ++#define LBLAWAR1 0x002C ++#define LBLAWBAR2 0x0030 ++#define LBLAWAR2 0x0034 ++#define LBLAWBAR3 0x0038 ++#define LBLAWAR3 0x003C ++#define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ ++ ++/* SPRIDR - System Part and Revision ID Register ++ */ ++#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */ ++#define SPRIDR_REVID 0x0000FFFF /* Revision Identification */ ++ ++#define SPR_8349E_REV10 0x80300100 ++#define SPR_8349_REV10 0x80310100 ++#define SPR_8347E_REV10_TBGA 0x80320100 ++#define SPR_8347_REV10_TBGA 0x80330100 ++#define SPR_8347E_REV10_PBGA 0x80340100 ++#define SPR_8347_REV10_PBGA 0x80350100 ++#define SPR_8343E_REV10 0x80360100 ++#define SPR_8343_REV10 0x80370100 ++ ++#define SPR_8349E_REV11 0x80300101 ++#define SPR_8349_REV11 0x80310101 ++#define SPR_8347E_REV11_TBGA 0x80320101 ++#define SPR_8347_REV11_TBGA 0x80330101 ++#define SPR_8347E_REV11_PBGA 0x80340101 ++#define SPR_8347_REV11_PBGA 0x80350101 ++#define SPR_8343E_REV11 0x80360101 ++#define SPR_8343_REV11 0x80370101 ++ ++#define SPR_8360E_REV10 0x80480010 ++#define SPR_8360_REV10 0x80490010 ++#define SPR_8360E_REV11 0x80480011 ++#define SPR_8360_REV11 0x80490011 ++#define SPR_8360E_REV12 0x80480012 ++#define SPR_8360_REV12 0x80490012 ++ ++/* SPCR - System Priority Configuration Register ++ */ ++#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ ++#define SPCR_PCIHPE_SHIFT (31-3) ++#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ ++#define SPCR_PCIPR_SHIFT (31-7) ++#define SPCR_OPT 0x00800000 /* Optimize */ ++#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ ++#define SPCR_TBEN_SHIFT (31-9) ++#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ ++#define SPCR_COREPR_SHIFT (31-11) ++ ++#if defined(CONFIG_MPC8349) ++/* SPCR bits - MPC8349 specific */ ++#define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */ ++#define SPCR_TSEC1DP_SHIFT (31-19) ++#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */ ++#define SPCR_TSEC1BDP_SHIFT (31-21) ++#define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */ ++#define SPCR_TSEC1EP_SHIFT (31-23) ++#define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */ ++#define SPCR_TSEC2DP_SHIFT (31-27) ++#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */ ++#define SPCR_TSEC2BDP_SHIFT (31-29) ++#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */ ++#define SPCR_TSEC2EP_SHIFT (31-31) ++#endif + +-#define SWCNR 0x0208 +-#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field. +-#define SWCNR_RES ~(SWCNR_SWCN) ++/* SICRL/H - System I/O Configuration Register Low/High ++ */ ++#if defined(CONFIG_MPC8349) ++/* SICRL bits - MPC8349 specific */ ++#define SICRL_LDP_A 0x80000000 ++#define SICRL_USB1 0x40000000 ++#define SICRL_USB0 0x20000000 ++#define SICRL_UART 0x0C000000 ++#define SICRL_GPIO1_A 0x02000000 ++#define SICRL_GPIO1_B 0x01000000 ++#define SICRL_GPIO1_C 0x00800000 ++#define SICRL_GPIO1_D 0x00400000 ++#define SICRL_GPIO1_E 0x00200000 ++#define SICRL_GPIO1_F 0x00180000 ++#define SICRL_GPIO1_G 0x00040000 ++#define SICRL_GPIO1_H 0x00020000 ++#define SICRL_GPIO1_I 0x00010000 ++#define SICRL_GPIO1_J 0x00008000 ++#define SICRL_GPIO1_K 0x00004000 ++#define SICRL_GPIO1_L 0x00003000 ++ ++/* SICRH bits - MPC8349 specific */ ++#define SICRH_DDR 0x80000000 ++#define SICRH_TSEC1_A 0x10000000 ++#define SICRH_TSEC1_B 0x08000000 ++#define SICRH_TSEC1_C 0x04000000 ++#define SICRH_TSEC1_D 0x02000000 ++#define SICRH_TSEC1_E 0x01000000 ++#define SICRH_TSEC1_F 0x00800000 ++#define SICRH_TSEC2_A 0x00400000 ++#define SICRH_TSEC2_B 0x00200000 ++#define SICRH_TSEC2_C 0x00100000 ++#define SICRH_TSEC2_D 0x00080000 ++#define SICRH_TSEC2_E 0x00040000 ++#define SICRH_TSEC2_F 0x00020000 ++#define SICRH_TSEC2_G 0x00010000 ++#define SICRH_TSEC2_H 0x00008000 ++#define SICRH_GPIO2_A 0x00004000 ++#define SICRH_GPIO2_B 0x00002000 ++#define SICRH_GPIO2_C 0x00001000 ++#define SICRH_GPIO2_D 0x00000800 ++#define SICRH_GPIO2_E 0x00000400 ++#define SICRH_GPIO2_F 0x00000200 ++#define SICRH_GPIO2_G 0x00000180 ++#define SICRH_GPIO2_H 0x00000060 ++#define SICRH_TSOBI1 0x00000002 ++#define SICRH_TSOBI2 0x00000001 ++ ++#elif defined(CONFIG_MPC8360) ++/* SICRL bits - MPC8360 specific */ ++#define SICRL_LDP_A 0xC0000000 ++#define SICRL_LCLK_1 0x10000000 ++#define SICRL_LCLK_2 0x08000000 ++#define SICRL_SRCID_A 0x03000000 ++#define SICRL_IRQ_CKSTP_A 0x00C00000 ++ ++/* SICRH bits - MPC8360 specific */ ++#define SICRH_DDR 0x80000000 ++#define SICRH_SECONDARY_DDR 0x40000000 ++#define SICRH_SDDROE 0x20000000 ++#define SICRH_IRQ3 0x10000000 ++#define SICRH_UC1EOBI 0x00000004 ++#define SICRH_UC2E1OBI 0x00000002 ++#define SICRH_UC2E2OBI 0x00000001 ++#endif + +-#define SWSRR 0x020E ++/* SWCRR - System Watchdog Control Register ++ */ ++#define SWCRR 0x0204 /* Register offset to immr */ ++#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */ ++#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */ ++#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */ ++#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */ ++#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) ++ ++/* SWCNR - System Watchdog Counter Register ++ */ ++#define SWCNR 0x0208 /* Register offset to immr */ ++#define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */ ++#define SWCNR_RES ~(SWCNR_SWCN) + +-/* +- * Default Internal Memory Register Space (Freescale recomandation) ++/* SWSRR - System Watchdog Service Register + */ +-#define IMMRBAR 0x0000 +-#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Identifies the 12 most-significant address bits of the base of the 1 MByte internal memory window. */ +-#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) ++#define SWSRR 0x020E /* Register offset to immr */ + +-/* +- * Default Internal Memory Register Space (Freescale recomandation) ++/* ACR - Arbiter Configuration Register + */ +-#define LBLAWBAR0 0x0020 +-#define LBLAWAR0 0x0024 +-#define LBLAWBAR1 0x0028 +-#define LBLAWAR1 0x002C +-#define LBLAWBAR2 0x0030 +-#define LBLAWAR2 0x0034 +-#define LBLAWBAR3 0x0038 +-#define LBLAWAR3 0x003C ++#define ACR_COREDIS 0x10000000 /* Core disable */ ++#define ACR_COREDIS_SHIFT (31-7) ++#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ ++#define ACR_PIPE_DEP_SHIFT (31-15) ++#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ ++#define ACR_PCI_RPTCNT_SHIFT (31-19) ++#define ACR_RPTCNT 0x00000700 /* Repeat count */ ++#define ACR_RPTCNT_SHIFT (31-23) ++#define ACR_APARK 0x00000030 /* Address parking */ ++#define ACR_APARK_SHIFT (31-27) ++#define ACR_PARKM 0x0000000F /* Parking master */ ++#define ACR_PARKM_SHIFT (31-31) ++ ++/* ATR - Arbiter Timers Register ++ */ ++#define ATR_DTO 0x00FF0000 /* Data time out */ ++#define ATR_ATO 0x000000FF /* Address time out */ + +-/* +- * The device ID and revision numbers +- */ +-#define SPR_8349E_REV10 0x80300100 +-#define SPR_8349_REV10 0x80310100 +-#define SPR_8347E_REV10_TBGA 0x80320100 +-#define SPR_8347_REV10_TBGA 0x80330100 +-#define SPR_8347E_REV10_PBGA 0x80340100 +-#define SPR_8347_REV10_PBGA 0x80350100 +-#define SPR_8343E_REV10 0x80360100 +-#define SPR_8343_REV10 0x80370100 +- +-#define SPR_8349E_REV11 0x80300101 +-#define SPR_8349_REV11 0x80310101 +-#define SPR_8347E_REV11_TBGA 0x80320101 +-#define SPR_8347_REV11_TBGA 0x80330101 +-#define SPR_8347E_REV11_PBGA 0x80340101 +-#define SPR_8347_REV11_PBGA 0x80350101 +-#define SPR_8343E_REV11 0x80360101 +-#define SPR_8343_REV11 0x80370101 +- +-#define SPR_8360E_REV10 0x80480010 +-#define SPR_8360_REV10 0x80490010 +-#define SPR_8360E_REV11 0x80480011 +-#define SPR_8360_REV11 0x80490011 +-#define SPR_8360E_REV12 0x80480012 +-#define SPR_8360_REV12 0x80490012 ++/* AER - Arbiter Event Register ++ */ ++#define AER_ETEA 0x00000020 /* Transfer error */ ++#define AER_RES 0x00000010 /* Reserved transfer type */ ++#define AER_ECW 0x00000008 /* External control word transfer type */ ++#define AER_AO 0x00000004 /* Address Only transfer type */ ++#define AER_DTO 0x00000002 /* Data time out */ ++#define AER_ATO 0x00000001 /* Address time out */ ++ ++/* AEATR - Arbiter Event Address Register ++ */ ++#define AEATR_EVENT 0x07000000 /* Event type */ ++#define AEATR_MSTR_ID 0x001F0000 /* Master Id */ ++#define AEATR_TBST 0x00000800 /* Transfer burst */ ++#define AEATR_TSIZE 0x00000700 /* Transfer Size */ ++#define AEATR_TTYPE 0x0000001F /* Transfer Type */ + +-/* +- * Base Registers & Option Registers +- */ +-#define BR0 0x5000 +-#define BR1 0x5008 +-#define BR2 0x5010 +-#define BR3 0x5018 +-#define BR4 0x5020 +-#define BR5 0x5028 +-#define BR6 0x5030 +-#define BR7 0x5038 +- +-#define BR_BA 0xFFFF8000 +-#define BR_BA_SHIFT 15 +-#define BR_PS 0x00001800 +-#define BR_PS_SHIFT 11 +-#define BR_PS_8 0x00000800 /* Port Size 8 bit */ +-#define BR_PS_16 0x00001000 /* Port Size 16 bit */ +-#define BR_PS_32 0x00001800 /* Port Size 32 bit */ +-#define BR_DECC 0x00000600 +-#define BR_DECC_SHIFT 9 +-#define BR_WP 0x00000100 +-#define BR_WP_SHIFT 8 +-#define BR_MSEL 0x000000E0 +-#define BR_MSEL_SHIFT 5 +-#define BR_MS_GPCM 0x00000000 /* GPCM */ +-#define BR_MS_SDRAM 0x00000060 /* SDRAM */ +-#define BR_MS_UPMA 0x00000080 /* UPMA */ +-#define BR_MS_UPMB 0x000000A0 /* UPMB */ +-#define BR_MS_UPMC 0x000000C0 /* UPMC */ +-#if defined (CONFIG_MPC8360) +-#define BR_ATOM 0x0000000C +-#define BR_ATOM_SHIFT 2 +-#endif +-#define BR_V 0x00000001 +-#define BR_V_SHIFT 0 +-#if defined (CONFIG_MPC8349) +-#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V) +-#elif defined (CONFIG_MPC8360) +-#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_ATOM|BR_V) ++/* HRCWL - Hard Reset Configuration Word Low ++ */ ++#define HRCWL_LBIUCM 0x80000000 ++#define HRCWL_LBIUCM_SHIFT 31 ++#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 ++#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 ++ ++#define HRCWL_DDRCM 0x40000000 ++#define HRCWL_DDRCM_SHIFT 30 ++#define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 ++#define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 ++ ++#define HRCWL_SPMF 0x0f000000 ++#define HRCWL_SPMF_SHIFT 24 ++#define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 ++#define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 ++#define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 ++#define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 ++#define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 ++#define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 ++#define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 ++#define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 ++#define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 ++#define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 ++#define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 ++#define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 ++#define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 ++#define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 ++#define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 ++#define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 ++ ++#define HRCWL_VCO_BYPASS 0x00000000 ++#define HRCWL_VCO_1X2 0x00000000 ++#define HRCWL_VCO_1X4 0x00200000 ++#define HRCWL_VCO_1X8 0x00400000 ++ ++#define HRCWL_COREPLL 0x007F0000 ++#define HRCWL_COREPLL_SHIFT 16 ++#define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 ++#define HRCWL_CORE_TO_CSB_1X1 0x00020000 ++#define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 ++#define HRCWL_CORE_TO_CSB_2X1 0x00040000 ++#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 ++#define HRCWL_CORE_TO_CSB_3X1 0x00060000 ++ ++#if defined(CONFIG_MPC8360) ++#define HRCWL_CEVCOD 0x000000C0 ++#define HRCWL_CEVCOD_SHIFT 6 ++#define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 ++#define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 ++#define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 ++ ++#define HRCWL_CEPDF 0x00000020 ++#define HRCWL_CEPDF_SHIFT 5 ++#define HRCWL_CE_PLL_DIV_1X1 0x00000000 ++#define HRCWL_CE_PLL_DIV_2X1 0x00000020 ++ ++#define HRCWL_CEPMF 0x0000001F ++#define HRCWL_CEPMF_SHIFT 0 ++#define HRCWL_CE_TO_PLL_1X16_ 0x00000000 ++#define HRCWL_CE_TO_PLL_1X2 0x00000002 ++#define HRCWL_CE_TO_PLL_1X3 0x00000003 ++#define HRCWL_CE_TO_PLL_1X4 0x00000004 ++#define HRCWL_CE_TO_PLL_1X5 0x00000005 ++#define HRCWL_CE_TO_PLL_1X6 0x00000006 ++#define HRCWL_CE_TO_PLL_1X7 0x00000007 ++#define HRCWL_CE_TO_PLL_1X8 0x00000008 ++#define HRCWL_CE_TO_PLL_1X9 0x00000009 ++#define HRCWL_CE_TO_PLL_1X10 0x0000000A ++#define HRCWL_CE_TO_PLL_1X11 0x0000000B ++#define HRCWL_CE_TO_PLL_1X12 0x0000000C ++#define HRCWL_CE_TO_PLL_1X13 0x0000000D ++#define HRCWL_CE_TO_PLL_1X14 0x0000000E ++#define HRCWL_CE_TO_PLL_1X15 0x0000000F ++#define HRCWL_CE_TO_PLL_1X16 0x00000010 ++#define HRCWL_CE_TO_PLL_1X17 0x00000011 ++#define HRCWL_CE_TO_PLL_1X18 0x00000012 ++#define HRCWL_CE_TO_PLL_1X19 0x00000013 ++#define HRCWL_CE_TO_PLL_1X20 0x00000014 ++#define HRCWL_CE_TO_PLL_1X21 0x00000015 ++#define HRCWL_CE_TO_PLL_1X22 0x00000016 ++#define HRCWL_CE_TO_PLL_1X23 0x00000017 ++#define HRCWL_CE_TO_PLL_1X24 0x00000018 ++#define HRCWL_CE_TO_PLL_1X25 0x00000019 ++#define HRCWL_CE_TO_PLL_1X26 0x0000001A ++#define HRCWL_CE_TO_PLL_1X27 0x0000001B ++#define HRCWL_CE_TO_PLL_1X28 0x0000001C ++#define HRCWL_CE_TO_PLL_1X29 0x0000001D ++#define HRCWL_CE_TO_PLL_1X30 0x0000001E ++#define HRCWL_CE_TO_PLL_1X31 0x0000001F + #endif + +-#define OR0 0x5004 +-#define OR1 0x500C +-#define OR2 0x5014 +-#define OR3 0x501C +-#define OR4 0x5024 +-#define OR5 0x502C +-#define OR6 0x5034 +-#define OR7 0x503C +- +-#define OR_GPCM_AM 0xFFFF8000 +-#define OR_GPCM_AM_SHIFT 15 +-#define OR_GPCM_BCTLD 0x00001000 +-#define OR_GPCM_BCTLD_SHIFT 12 +-#define OR_GPCM_CSNT 0x00000800 +-#define OR_GPCM_CSNT_SHIFT 11 +-#define OR_GPCM_ACS 0x00000600 +-#define OR_GPCM_ACS_SHIFT 9 +-#define OR_GPCM_ACS_0b10 0x00000400 +-#define OR_GPCM_ACS_0b11 0x00000600 +-#define OR_GPCM_XACS 0x00000100 +-#define OR_GPCM_XACS_SHIFT 8 +-#define OR_GPCM_SCY 0x000000F0 +-#define OR_GPCM_SCY_SHIFT 4 +-#define OR_GPCM_SCY_1 0x00000010 +-#define OR_GPCM_SCY_2 0x00000020 +-#define OR_GPCM_SCY_3 0x00000030 +-#define OR_GPCM_SCY_4 0x00000040 +-#define OR_GPCM_SCY_5 0x00000050 +-#define OR_GPCM_SCY_6 0x00000060 +-#define OR_GPCM_SCY_7 0x00000070 +-#define OR_GPCM_SCY_8 0x00000080 +-#define OR_GPCM_SCY_9 0x00000090 +-#define OR_GPCM_SCY_10 0x000000a0 +-#define OR_GPCM_SCY_11 0x000000b0 +-#define OR_GPCM_SCY_12 0x000000c0 +-#define OR_GPCM_SCY_13 0x000000d0 +-#define OR_GPCM_SCY_14 0x000000e0 +-#define OR_GPCM_SCY_15 0x000000f0 +-#define OR_GPCM_SETA 0x00000008 +-#define OR_GPCM_SETA_SHIFT 3 +-#define OR_GPCM_TRLX 0x00000004 +-#define OR_GPCM_TRLX_SHIFT 2 +-#define OR_GPCM_EHTR 0x00000002 +-#define OR_GPCM_EHTR_SHIFT 1 +-#define OR_GPCM_EAD 0x00000001 +-#define OR_GPCM_EAD_SHIFT 0 +- +-#define OR_UPM_AM 0xFFFF8000 +-#define OR_UPM_AM_SHIFT 15 +-#define OR_UPM_XAM 0x00006000 +-#define OR_UPM_XAM_SHIFT 13 +-#define OR_UPM_BCTLD 0x00001000 +-#define OR_UPM_BCTLD_SHIFT 12 +-#define OR_UPM_BI 0x00000100 +-#define OR_UPM_BI_SHIFT 8 +-#define OR_UPM_TRLX 0x00000004 +-#define OR_UPM_TRLX_SHIFT 2 +-#define OR_UPM_EHTR 0x00000002 +-#define OR_UPM_EHTR_SHIFT 1 +-#define OR_UPM_EAD 0x00000001 +-#define OR_UPM_EAD_SHIFT 0 +- +-#define OR_SDRAM_AM 0xFFFF8000 +-#define OR_SDRAM_AM_SHIFT 15 +-#define OR_SDRAM_XAM 0x00006000 +-#define OR_SDRAM_XAM_SHIFT 13 +-#define OR_SDRAM_COLS 0x00001C00 +-#define OR_SDRAM_COLS_SHIFT 10 +-#define OR_SDRAM_ROWS 0x000001C0 +-#define OR_SDRAM_ROWS_SHIFT 6 +-#define OR_SDRAM_PMSEL 0x00000020 +-#define OR_SDRAM_PMSEL_SHIFT 5 +-#define OR_SDRAM_EAD 0x00000001 +-#define OR_SDRAM_EAD_SHIFT 0 +- +-/* +- * Hard Reset Configration Word - High ++/* HRCWH - Hardware Reset Configuration Word High + */ +-#define HRCWH_PCI_AGENT 0x00000000 +-#define HRCWH_PCI_HOST 0x80000000 ++#define HRCWH_PCI_HOST 0x80000000 ++#define HRCWH_PCI_HOST_SHIFT 31 ++#define HRCWH_PCI_AGENT 0x00000000 + +-#if defined (CONFIG_MPC8349) +-#define HRCWH_32_BIT_PCI 0x00000000 +-#define HRCWH_64_BIT_PCI 0x40000000 ++#if defined(CONFIG_MPC8349) ++#define HRCWH_32_BIT_PCI 0x00000000 ++#define HRCWH_64_BIT_PCI 0x40000000 + #endif + +-#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 +-#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 ++#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 ++#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 ++ ++#define HRCWH_PCI_ARBITER_DISABLE 0x00000000 ++#define HRCWH_PCI_ARBITER_ENABLE 0x20000000 + +-#if defined (CONFIG_MPC8349) +-#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 +-#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 +-#elif defined (CONFIG_MPC8360) +-#define HRCWH_PCICKDRV_DISABLE 0x00000000 +-#define HRCWH_PCICKDRV_ENABLE 0x10000000 ++#if defined(CONFIG_MPC8349) ++#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 ++#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 ++ ++#elif defined(CONFIG_MPC8360) ++#define HRCWH_PCICKDRV_DISABLE 0x00000000 ++#define HRCWH_PCICKDRV_ENABLE 0x10000000 + #endif + +-#define HRCWH_CORE_DISABLE 0x08000000 +-#define HRCWH_CORE_ENABLE 0x00000000 ++#define HRCWH_CORE_DISABLE 0x08000000 ++#define HRCWH_CORE_ENABLE 0x00000000 + +-#define HRCWH_FROM_0X00000100 0x00000000 +-#define HRCWH_FROM_0XFFF00100 0x04000000 ++#define HRCWH_FROM_0X00000100 0x00000000 ++#define HRCWH_FROM_0XFFF00100 0x04000000 + +-#define HRCWH_BOOTSEQ_DISABLE 0x00000000 +-#define HRCWH_BOOTSEQ_NORMAL 0x01000000 +-#define HRCWH_BOOTSEQ_EXTENDED 0x02000000 ++#define HRCWH_BOOTSEQ_DISABLE 0x00000000 ++#define HRCWH_BOOTSEQ_NORMAL 0x01000000 ++#define HRCWH_BOOTSEQ_EXTENDED 0x02000000 + +-#define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 +-#define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 ++#define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 ++#define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 + +-#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 +-#define HRCWH_ROM_LOC_PCI1 0x00100000 +-#if defined (CONFIG_MPC8349) +-#define HRCWH_ROM_LOC_PCI2 0x00200000 ++#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 ++#define HRCWH_ROM_LOC_PCI1 0x00100000 ++#if defined(CONFIG_MPC8349) ++#define HRCWH_ROM_LOC_PCI2 0x00200000 + #endif +-#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 +-#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 +-#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 +- +-#if defined (CONFIG_MPC8349) +-#define HRCWH_TSEC1M_IN_RGMII 0x00000000 +-#define HRCWH_TSEC1M_IN_RTBI 0x00004000 +-#define HRCWH_TSEC1M_IN_GMII 0x00008000 +-#define HRCWH_TSEC1M_IN_TBI 0x0000C000 +- +-#define HRCWH_TSEC2M_IN_RGMII 0x00000000 +-#define HRCWH_TSEC2M_IN_RTBI 0x00001000 +-#define HRCWH_TSEC2M_IN_GMII 0x00002000 +-#define HRCWH_TSEC2M_IN_TBI 0x00003000 ++#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 ++#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 ++#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 ++ ++#if defined(CONFIG_MPC8349) ++#define HRCWH_TSEC1M_IN_RGMII 0x00000000 ++#define HRCWH_TSEC1M_IN_RTBI 0x00004000 ++#define HRCWH_TSEC1M_IN_GMII 0x00008000 ++#define HRCWH_TSEC1M_IN_TBI 0x0000C000 ++#define HRCWH_TSEC2M_IN_RGMII 0x00000000 ++#define HRCWH_TSEC2M_IN_RTBI 0x00001000 ++#define HRCWH_TSEC2M_IN_GMII 0x00002000 ++#define HRCWH_TSEC2M_IN_TBI 0x00003000 + #endif + +-#if defined (CONFIG_MPC8360) +-#define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 +-#define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 ++#if defined(CONFIG_MPC8360) ++#define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 ++#define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 + #endif + +-#define HRCWH_BIG_ENDIAN 0x00000000 +-#define HRCWH_LITTLE_ENDIAN 0x00000008 ++#define HRCWH_BIG_ENDIAN 0x00000000 ++#define HRCWH_LITTLE_ENDIAN 0x00000008 + +-#define HRCWH_LALE_NORMAL 0x00000000 +-#define HRCWH_LALE_EARLY 0x00000004 ++#define HRCWH_LALE_NORMAL 0x00000000 ++#define HRCWH_LALE_EARLY 0x00000004 + +-#define HRCWH_LDP_SET 0x00000000 +-#define HRCWH_LDP_CLEAR 0x00000002 ++#define HRCWH_LDP_SET 0x00000000 ++#define HRCWH_LDP_CLEAR 0x00000002 + +-/* +- * Hard Reset Configration Word - Low +- */ +-#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 +-#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 +- +-#define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 +-#define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 +- +-#define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 +-#define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 +-#define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 +-#define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 +-#define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 +-#define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 +-#define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 +-#define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 +-#define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 +-#define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 +-#define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 +-#define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 +-#define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 +-#define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 +-#define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 +-#define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 +- +-#define HRCWL_VCO_BYPASS 0x00000000 +-#define HRCWL_VCO_1X2 0x00000000 +-#define HRCWL_VCO_1X4 0x00200000 +-#define HRCWL_VCO_1X8 0x00400000 +- +-#define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 +-#define HRCWL_CORE_TO_CSB_1X1 0x00020000 +-#define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 +-#define HRCWL_CORE_TO_CSB_2X1 0x00040000 +-#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 +-#define HRCWL_CORE_TO_CSB_3X1 0x00060000 +- +-#if defined (CONFIG_MPC8360) +-#define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 +-#define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 +-#define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 +- +-#define HRCWL_CE_PLL_DIV_1X1 0x00000000 +-#define HRCWL_CE_PLL_DIV_2X1 0x00000020 +- +-#define HRCWL_CE_TO_PLL_1X16_ 0x00000000 +-#define HRCWL_CE_TO_PLL_1X2 0x00000002 +-#define HRCWL_CE_TO_PLL_1X3 0x00000003 +-#define HRCWL_CE_TO_PLL_1X4 0x00000004 +-#define HRCWL_CE_TO_PLL_1X5 0x00000005 +-#define HRCWL_CE_TO_PLL_1X6 0x00000006 +-#define HRCWL_CE_TO_PLL_1X7 0x00000007 +-#define HRCWL_CE_TO_PLL_1X8 0x00000008 +-#define HRCWL_CE_TO_PLL_1X9 0x00000009 +-#define HRCWL_CE_TO_PLL_1X10 0x0000000A +-#define HRCWL_CE_TO_PLL_1X11 0x0000000B +-#define HRCWL_CE_TO_PLL_1X12 0x0000000C +-#define HRCWL_CE_TO_PLL_1X13 0x0000000D +-#define HRCWL_CE_TO_PLL_1X14 0x0000000E +-#define HRCWL_CE_TO_PLL_1X15 0x0000000F +-#define HRCWL_CE_TO_PLL_1X16 0x00000010 +-#define HRCWL_CE_TO_PLL_1X17 0x00000011 +-#define HRCWL_CE_TO_PLL_1X18 0x00000012 +-#define HRCWL_CE_TO_PLL_1X19 0x00000013 +-#define HRCWL_CE_TO_PLL_1X20 0x00000014 +-#define HRCWL_CE_TO_PLL_1X21 0x00000015 +-#define HRCWL_CE_TO_PLL_1X22 0x00000016 +-#define HRCWL_CE_TO_PLL_1X23 0x00000017 +-#define HRCWL_CE_TO_PLL_1X24 0x00000018 +-#define HRCWL_CE_TO_PLL_1X25 0x00000019 +-#define HRCWL_CE_TO_PLL_1X26 0x0000001A +-#define HRCWL_CE_TO_PLL_1X27 0x0000001B +-#define HRCWL_CE_TO_PLL_1X28 0x0000001C +-#define HRCWL_CE_TO_PLL_1X29 0x0000001D +-#define HRCWL_CE_TO_PLL_1X30 0x0000001E +-#define HRCWL_CE_TO_PLL_1X31 0x0000001F ++/* RSR - Reset Status Register ++ */ ++#define RSR_RSTSRC 0xE0000000 /* Reset source */ ++#define RSR_RSTSRC_SHIFT 29 ++#define RSR_BSF 0x00010000 /* Boot seq. fail */ ++#define RSR_BSF_SHIFT 16 ++#define RSR_SWSR 0x00002000 /* software soft reset */ ++#define RSR_SWSR_SHIFT 13 ++#define RSR_SWHR 0x00001000 /* software hard reset */ ++#define RSR_SWHR_SHIFT 12 ++#define RSR_JHRS 0x00000200 /* jtag hreset */ ++#define RSR_JHRS_SHIFT 9 ++#define RSR_JSRS 0x00000100 /* jtag sreset status */ ++#define RSR_JSRS_SHIFT 8 ++#define RSR_CSHR 0x00000010 /* checkstop reset status */ ++#define RSR_CSHR_SHIFT 4 ++#define RSR_SWRS 0x00000008 /* software watchdog reset status */ ++#define RSR_SWRS_SHIFT 3 ++#define RSR_BMRS 0x00000004 /* bus monitop reset status */ ++#define RSR_BMRS_SHIFT 2 ++#define RSR_SRS 0x00000002 /* soft reset status */ ++#define RSR_SRS_SHIFT 1 ++#define RSR_HRS 0x00000001 /* hard reset status */ ++#define RSR_HRS_SHIFT 0 ++#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\ ++ RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ ++ RSR_BMRS | RSR_SRS | RSR_HRS) ++/* RMR - Reset Mode Register ++ */ ++#define RMR_CSRE 0x00000001 /* checkstop reset enable */ ++#define RMR_CSRE_SHIFT 0 ++#define RMR_RES ~(RMR_CSRE) ++ ++/* RCR - Reset Control Register ++ */ ++#define RCR_SWHR 0x00000002 /* software hard reset */ ++#define RCR_SWSR 0x00000001 /* software soft reset */ ++#define RCR_RES ~(RCR_SWHR | RCR_SWSR) ++ ++/* RCER - Reset Control Enable Register ++ */ ++#define RCER_CRE 0x00000001 /* software hard reset */ ++#define RCER_RES ~(RCER_CRE) ++ ++/* SPMR - System PLL Mode Register ++ */ ++#define SPMR_LBIUCM 0x80000000 ++#define SPMR_DDRCM 0x40000000 ++#define SPMR_SPMF 0x0F000000 ++#define SPMR_CKID 0x00800000 ++#define SPMR_CKID_SHIFT 23 ++#define SPMR_COREPLL 0x007F0000 ++#define SPMR_CEVCOD 0x000000C0 ++#define SPMR_CEPDF 0x00000020 ++#define SPMR_CEPMF 0x0000001F ++ ++/* OCCR - Output Clock Control Register ++ */ ++#define OCCR_PCICOE0 0x80000000 ++#define OCCR_PCICOE1 0x40000000 ++#define OCCR_PCICOE2 0x20000000 ++#define OCCR_PCICOE3 0x10000000 ++#define OCCR_PCICOE4 0x08000000 ++#define OCCR_PCICOE5 0x04000000 ++#define OCCR_PCICOE6 0x02000000 ++#define OCCR_PCICOE7 0x01000000 ++#define OCCR_PCICD0 0x00800000 ++#define OCCR_PCICD1 0x00400000 ++#define OCCR_PCICD2 0x00200000 ++#define OCCR_PCICD3 0x00100000 ++#define OCCR_PCICD4 0x00080000 ++#define OCCR_PCICD5 0x00040000 ++#define OCCR_PCICD6 0x00020000 ++#define OCCR_PCICD7 0x00010000 ++#define OCCR_PCI1CR 0x00000002 ++#define OCCR_PCI2CR 0x00000001 ++#define OCCR_PCICR OCCR_PCI1CR ++ ++/* SCCR - System Clock Control Register ++ */ ++#define SCCR_ENCCM 0x03000000 ++#define SCCR_ENCCM_SHIFT 24 ++#define SCCR_ENCCM_0 0x00000000 ++#define SCCR_ENCCM_1 0x01000000 ++#define SCCR_ENCCM_2 0x02000000 ++#define SCCR_ENCCM_3 0x03000000 ++ ++#define SCCR_PCICM 0x00010000 ++#define SCCR_PCICM_SHIFT 16 ++ ++/* SCCR bits - MPC8349 specific */ ++#define SCCR_TSEC1CM 0xc0000000 ++#define SCCR_TSEC1CM_SHIFT 30 ++#define SCCR_TSEC1CM_0 0x00000000 ++#define SCCR_TSEC1CM_1 0x40000000 ++#define SCCR_TSEC1CM_2 0x80000000 ++#define SCCR_TSEC1CM_3 0xC0000000 ++ ++#define SCCR_TSEC2CM 0x30000000 ++#define SCCR_TSEC2CM_SHIFT 28 ++#define SCCR_TSEC2CM_0 0x00000000 ++#define SCCR_TSEC2CM_1 0x10000000 ++#define SCCR_TSEC2CM_2 0x20000000 ++#define SCCR_TSEC2CM_3 0x30000000 ++ ++#define SCCR_USBMPHCM 0x00c00000 ++#define SCCR_USBMPHCM_SHIFT 22 ++#define SCCR_USBDRCM 0x00300000 ++#define SCCR_USBDRCM_SHIFT 20 ++ ++#define SCCR_USBCM_0 0x00000000 ++#define SCCR_USBCM_1 0x00500000 ++#define SCCR_USBCM_2 0x00A00000 ++#define SCCR_USBCM_3 0x00F00000 ++ ++#define SCCR_CLK_MASK ( SCCR_TSEC1CM_3 \ ++ | SCCR_TSEC2CM_3 \ ++ | SCCR_ENCCM_3 \ ++ | SCCR_USBCM_3 ) ++ ++#define SCCR_DEFAULT 0xFFFFFFFF ++ ++/* CSn_BDNS - Chip Select memory Bounds Register ++ */ ++#define CSBNDS_SA 0x00FF0000 ++#define CSBNDS_SA_SHIFT 8 ++#define CSBNDS_EA 0x000000FF ++#define CSBNDS_EA_SHIFT 24 ++ ++/* CSn_CONFIG - Chip Select Configuration Register ++ */ ++#define CSCONFIG_EN 0x80000000 ++#define CSCONFIG_AP 0x00800000 ++#define CSCONFIG_ROW_BIT 0x00000700 ++#define CSCONFIG_ROW_BIT_12 0x00000000 ++#define CSCONFIG_ROW_BIT_13 0x00000100 ++#define CSCONFIG_ROW_BIT_14 0x00000200 ++#define CSCONFIG_COL_BIT 0x00000007 ++#define CSCONFIG_COL_BIT_8 0x00000000 ++#define CSCONFIG_COL_BIT_9 0x00000001 ++#define CSCONFIG_COL_BIT_10 0x00000002 ++#define CSCONFIG_COL_BIT_11 0x00000003 ++ ++/* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 ++ */ ++#define TIMING_CFG1_PRETOACT 0x70000000 ++#define TIMING_CFG1_PRETOACT_SHIFT 28 ++#define TIMING_CFG1_ACTTOPRE 0x0F000000 ++#define TIMING_CFG1_ACTTOPRE_SHIFT 24 ++#define TIMING_CFG1_ACTTORW 0x00700000 ++#define TIMING_CFG1_ACTTORW_SHIFT 20 ++#define TIMING_CFG1_CASLAT 0x00070000 ++#define TIMING_CFG1_CASLAT_SHIFT 16 ++#define TIMING_CFG1_REFREC 0x0000F000 ++#define TIMING_CFG1_REFREC_SHIFT 12 ++#define TIMING_CFG1_WRREC 0x00000700 ++#define TIMING_CFG1_WRREC_SHIFT 8 ++#define TIMING_CFG1_ACTTOACT 0x00000070 ++#define TIMING_CFG1_ACTTOACT_SHIFT 4 ++#define TIMING_CFG1_WRTORD 0x00000007 ++#define TIMING_CFG1_WRTORD_SHIFT 0 ++#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ ++#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ ++ ++/* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 ++ */ ++#define TIMING_CFG2_CPO 0x0F000000 ++#define TIMING_CFG2_CPO_SHIFT 24 ++#define TIMING_CFG2_ACSM 0x00080000 ++#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 ++#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 ++#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ ++ ++/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration ++ */ ++#define SDRAM_CFG_MEM_EN 0x80000000 ++#define SDRAM_CFG_SREN 0x40000000 ++#define SDRAM_CFG_ECC_EN 0x20000000 ++#define SDRAM_CFG_RD_EN 0x10000000 ++#define SDRAM_CFG_SDRAM_TYPE 0x03000000 ++#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 ++#define SDRAM_CFG_DYN_PWR 0x00200000 ++#define SDRAM_CFG_32_BE 0x00080000 ++#define SDRAM_CFG_8_BE 0x00040000 ++#define SDRAM_CFG_NCAP 0x00020000 ++#define SDRAM_CFG_2T_EN 0x00008000 ++#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000 ++ ++/* DDR_SDRAM_MODE - DDR SDRAM Mode Register ++ */ ++#define SDRAM_MODE_ESD 0xFFFF0000 ++#define SDRAM_MODE_ESD_SHIFT 16 ++#define SDRAM_MODE_SD 0x0000FFFF ++#define SDRAM_MODE_SD_SHIFT 0 ++#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ ++#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ ++#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ ++#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ ++#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ ++#define DDR_MODE_WEAK 0x0002 /* weak drivers */ ++#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ ++#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ ++#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ ++#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ ++#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ ++#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ ++#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ ++#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ ++#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ ++#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ ++#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */ ++#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ ++#define DDR_MODE_MODEREG 0x0000 /* select mode register */ ++ ++/* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register ++ */ ++#define SDRAM_INTERVAL_REFINT 0x3FFF0000 ++#define SDRAM_INTERVAL_REFINT_SHIFT 16 ++#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF ++#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 ++ ++/* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register ++ */ ++#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 ++#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 ++#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 ++#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 ++#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 ++ ++/* ECC_ERR_INJECT - Memory data path error injection mask ECC ++ */ ++#define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ ++#define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ ++#define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ ++#define ECC_ERR_INJECT_EEIM_SHIFT 0 ++ ++/* CAPTURE_ECC - Memory data path read capture ECC ++ */ ++#define CAPTURE_ECC_ECE (0xff000000>>24) ++#define CAPTURE_ECC_ECE_SHIFT 0 ++ ++/* ERR_DETECT - Memory error detect ++ */ ++#define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ ++#define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ ++#define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ ++#define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ ++ ++/* ERR_DISABLE - Memory error disable ++ */ ++#define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ ++#define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ ++#define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ ++#define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\ ++ ECC_ERROR_DISABLE_MBED) ++/* ERR_INT_EN - Memory error interrupt enable ++ */ ++#define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ ++#define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ ++#define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ ++#define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\ ++ ECC_ERR_INT_EN_MSEE) ++/* CAPTURE_ATTRIBUTES - Memory error attributes capture ++ */ ++#define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ ++#define ECC_CAPT_ATTR_BNUM_SHIFT 28 ++#define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ ++#define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 ++#define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 ++#define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 ++#define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 ++#define ECC_CAPT_ATTR_TSIZ_SHIFT 24 ++#define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ ++#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 ++#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 ++#define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 ++#define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 ++#define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) ++#define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 ++#define ECC_CAPT_ATTR_TSRC_I2C 0x9 ++#define ECC_CAPT_ATTR_TSRC_JTAG 0xA ++#define ECC_CAPT_ATTR_TSRC_PCI1 0xD ++#define ECC_CAPT_ATTR_TSRC_PCI2 0xE ++#define ECC_CAPT_ATTR_TSRC_DMA 0xF ++#define ECC_CAPT_ATTR_TSRC_SHIFT 16 ++#define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ ++#define ECC_CAPT_ATTR_TTYP_WRITE 0x1 ++#define ECC_CAPT_ATTR_TTYP_READ 0x2 ++#define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 ++#define ECC_CAPT_ATTR_TTYP_SHIFT 12 ++#define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ ++ ++/* ERR_SBE - Single bit ECC memory error management ++ */ ++#define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ ++#define ECC_ERROR_MAN_SBET_SHIFT 16 ++#define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ ++#define ECC_ERROR_MAN_SBEC_SHIFT 0 ++ ++/* BR - Base Registers ++ */ ++#define BR0 0x5000 /* Register offset to immr */ ++#define BR1 0x5008 ++#define BR2 0x5010 ++#define BR3 0x5018 ++#define BR4 0x5020 ++#define BR5 0x5028 ++#define BR6 0x5030 ++#define BR7 0x5038 ++ ++#define BR_BA 0xFFFF8000 ++#define BR_BA_SHIFT 15 ++#define BR_PS 0x00001800 ++#define BR_PS_SHIFT 11 ++#define BR_PS_8 0x00000800 /* Port Size 8 bit */ ++#define BR_PS_16 0x00001000 /* Port Size 16 bit */ ++#define BR_PS_32 0x00001800 /* Port Size 32 bit */ ++#define BR_DECC 0x00000600 ++#define BR_DECC_SHIFT 9 ++#define BR_WP 0x00000100 ++#define BR_WP_SHIFT 8 ++#define BR_MSEL 0x000000E0 ++#define BR_MSEL_SHIFT 5 ++#define BR_MS_GPCM 0x00000000 /* GPCM */ ++#define BR_MS_SDRAM 0x00000060 /* SDRAM */ ++#define BR_MS_UPMA 0x00000080 /* UPMA */ ++#define BR_MS_UPMB 0x000000A0 /* UPMB */ ++#define BR_MS_UPMC 0x000000C0 /* UPMC */ ++#if defined(CONFIG_MPC8360) ++#define BR_ATOM 0x0000000C ++#define BR_ATOM_SHIFT 2 + #endif ++#define BR_V 0x00000001 ++#define BR_V_SHIFT 0 + +-/* +- * LCRR - Clock Ratio Register (10.3.1.16) +- */ +-#define LCRR_DBYP 0x80000000 +-#define LCRR_DBYP_SHIFT 31 +-#define LCRR_BUFCMDC 0x30000000 +-#define LCRR_BUFCMDC_1 0x10000000 +-#define LCRR_BUFCMDC_2 0x20000000 +-#define LCRR_BUFCMDC_3 0x30000000 +-#define LCRR_BUFCMDC_4 0x00000000 +-#define LCRR_BUFCMDC_SHIFT 28 +-#define LCRR_ECL 0x03000000 +-#define LCRR_ECL_4 0x00000000 +-#define LCRR_ECL_5 0x01000000 +-#define LCRR_ECL_6 0x02000000 +-#define LCRR_ECL_7 0x03000000 +-#define LCRR_ECL_SHIFT 24 +-#define LCRR_EADC 0x00030000 +-#define LCRR_EADC_1 0x00010000 +-#define LCRR_EADC_2 0x00020000 +-#define LCRR_EADC_3 0x00030000 +-#define LCRR_EADC_4 0x00000000 +-#define LCRR_EADC_SHIFT 16 +-#define LCRR_CLKDIV 0x0000000F +-#define LCRR_CLKDIV_2 0x00000002 +-#define LCRR_CLKDIV_4 0x00000004 +-#define LCRR_CLKDIV_8 0x00000008 +-#define LCRR_CLKDIV_SHIFT 0 ++#if defined(CONFIG_MPC8349) ++#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) ++#elif defined(CONFIG_MPC8360) ++#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) ++#endif + +-/* +- * SCCR-System Clock Control Register +- */ +-#define SCCR_TSEC1CM_0 0x00000000 +-#define SCCR_TSEC1CM_1 0x40000000 +-#define SCCR_TSEC1CM_2 0x80000000 +-#define SCCR_TSEC1CM_3 0xC0000000 +-#define SCCR_TSEC2CM_0 0x00000000 +-#define SCCR_TSEC2CM_1 0x10000000 +-#define SCCR_TSEC2CM_2 0x20000000 +-#define SCCR_TSEC2CM_3 0x30000000 +-#define SCCR_ENCCM_0 0x00000000 +-#define SCCR_ENCCM_1 0x01000000 +-#define SCCR_ENCCM_2 0x02000000 +-#define SCCR_ENCCM_3 0x03000000 +-#define SCCR_USBCM_0 0x00000000 +-#define SCCR_USBCM_1 0x00500000 +-#define SCCR_USBCM_2 0x00A00000 +-#define SCCR_USBCM_3 0x00F00000 +- +-#define SCCR_CLK_MASK ( SCCR_TSEC1CM_3 \ +- | SCCR_TSEC2CM_3 \ +- | SCCR_ENCCM_3 \ +- | SCCR_USBCM_3 ) +- +-#define SCCR_DEFAULT 0xFFFFFFFF ++/* OR - Option Registers ++ */ ++#define OR0 0x5004 /* Register offset to immr */ ++#define OR1 0x500C ++#define OR2 0x5014 ++#define OR3 0x501C ++#define OR4 0x5024 ++#define OR5 0x502C ++#define OR6 0x5034 ++#define OR7 0x503C ++ ++#define OR_GPCM_AM 0xFFFF8000 ++#define OR_GPCM_AM_SHIFT 15 ++#define OR_GPCM_BCTLD 0x00001000 ++#define OR_GPCM_BCTLD_SHIFT 12 ++#define OR_GPCM_CSNT 0x00000800 ++#define OR_GPCM_CSNT_SHIFT 11 ++#define OR_GPCM_ACS 0x00000600 ++#define OR_GPCM_ACS_SHIFT 9 ++#define OR_GPCM_ACS_0b10 0x00000400 ++#define OR_GPCM_ACS_0b11 0x00000600 ++#define OR_GPCM_XACS 0x00000100 ++#define OR_GPCM_XACS_SHIFT 8 ++#define OR_GPCM_SCY 0x000000F0 ++#define OR_GPCM_SCY_SHIFT 4 ++#define OR_GPCM_SCY_1 0x00000010 ++#define OR_GPCM_SCY_2 0x00000020 ++#define OR_GPCM_SCY_3 0x00000030 ++#define OR_GPCM_SCY_4 0x00000040 ++#define OR_GPCM_SCY_5 0x00000050 ++#define OR_GPCM_SCY_6 0x00000060 ++#define OR_GPCM_SCY_7 0x00000070 ++#define OR_GPCM_SCY_8 0x00000080 ++#define OR_GPCM_SCY_9 0x00000090 ++#define OR_GPCM_SCY_10 0x000000a0 ++#define OR_GPCM_SCY_11 0x000000b0 ++#define OR_GPCM_SCY_12 0x000000c0 ++#define OR_GPCM_SCY_13 0x000000d0 ++#define OR_GPCM_SCY_14 0x000000e0 ++#define OR_GPCM_SCY_15 0x000000f0 ++#define OR_GPCM_SETA 0x00000008 ++#define OR_GPCM_SETA_SHIFT 3 ++#define OR_GPCM_TRLX 0x00000004 ++#define OR_GPCM_TRLX_SHIFT 2 ++#define OR_GPCM_EHTR 0x00000002 ++#define OR_GPCM_EHTR_SHIFT 1 ++#define OR_GPCM_EAD 0x00000001 ++#define OR_GPCM_EAD_SHIFT 0 ++ ++#define OR_UPM_AM 0xFFFF8000 ++#define OR_UPM_AM_SHIFT 15 ++#define OR_UPM_XAM 0x00006000 ++#define OR_UPM_XAM_SHIFT 13 ++#define OR_UPM_BCTLD 0x00001000 ++#define OR_UPM_BCTLD_SHIFT 12 ++#define OR_UPM_BI 0x00000100 ++#define OR_UPM_BI_SHIFT 8 ++#define OR_UPM_TRLX 0x00000004 ++#define OR_UPM_TRLX_SHIFT 2 ++#define OR_UPM_EHTR 0x00000002 ++#define OR_UPM_EHTR_SHIFT 1 ++#define OR_UPM_EAD 0x00000001 ++#define OR_UPM_EAD_SHIFT 0 ++ ++#define OR_SDRAM_AM 0xFFFF8000 ++#define OR_SDRAM_AM_SHIFT 15 ++#define OR_SDRAM_XAM 0x00006000 ++#define OR_SDRAM_XAM_SHIFT 13 ++#define OR_SDRAM_COLS 0x00001C00 ++#define OR_SDRAM_COLS_SHIFT 10 ++#define OR_SDRAM_ROWS 0x000001C0 ++#define OR_SDRAM_ROWS_SHIFT 6 ++#define OR_SDRAM_PMSEL 0x00000020 ++#define OR_SDRAM_PMSEL_SHIFT 5 ++#define OR_SDRAM_EAD 0x00000001 ++#define OR_SDRAM_EAD_SHIFT 0 ++ ++/* LBCR - Local Bus Configuration Register ++ */ ++#define LBCR_LDIS 0x80000000 ++#define LBCR_LDIS_SHIFT 31 ++#define LBCR_BCTLC 0x00C00000 ++#define LBCR_BCTLC_SHIFT 22 ++#define LBCR_LPBSE 0x00020000 ++#define LBCR_LPBSE_SHIFT 17 ++#define LBCR_EPAR 0x00010000 ++#define LBCR_EPAR_SHIFT 16 ++#define LBCR_BMT 0x0000FF00 ++#define LBCR_BMT_SHIFT 8 ++ ++/* LCRR - Clock Ratio Register ++ */ ++#define LCRR_DBYP 0x80000000 ++#define LCRR_DBYP_SHIFT 31 ++#define LCRR_BUFCMDC 0x30000000 ++#define LCRR_BUFCMDC_SHIFT 28 ++#define LCRR_BUFCMDC_1 0x10000000 ++#define LCRR_BUFCMDC_2 0x20000000 ++#define LCRR_BUFCMDC_3 0x30000000 ++#define LCRR_BUFCMDC_4 0x00000000 ++#define LCRR_ECL 0x03000000 ++#define LCRR_ECL_SHIFT 24 ++#define LCRR_ECL_4 0x00000000 ++#define LCRR_ECL_5 0x01000000 ++#define LCRR_ECL_6 0x02000000 ++#define LCRR_ECL_7 0x03000000 ++#define LCRR_EADC 0x00030000 ++#define LCRR_EADC_SHIFT 16 ++#define LCRR_EADC_1 0x00010000 ++#define LCRR_EADC_2 0x00020000 ++#define LCRR_EADC_3 0x00030000 ++#define LCRR_EADC_4 0x00000000 ++#define LCRR_CLKDIV 0x0000000F ++#define LCRR_CLKDIV_SHIFT 0 ++#define LCRR_CLKDIV_2 0x00000002 ++#define LCRR_CLKDIV_4 0x00000004 ++#define LCRR_CLKDIV_8 0x00000008 ++ ++/* DMAMR - DMA Mode Register ++ */ ++#define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */ ++#define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */ ++#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */ ++#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */ ++#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */ ++#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */ ++#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */ ++#define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */ ++ ++/* DMASR - DMA Status Register ++ */ ++#define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */ ++#define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */ ++ ++/* CONFIG_ADDRESS - PCI Config Address Register ++ */ ++#define PCI_CONFIG_ADDRESS_EN 0x80000000 ++#define PCI_CONFIG_ADDRESS_BN_SHIFT 16 ++#define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 ++#define PCI_CONFIG_ADDRESS_DN_SHIFT 11 ++#define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 ++#define PCI_CONFIG_ADDRESS_FN_SHIFT 8 ++#define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 ++#define PCI_CONFIG_ADDRESS_RN_SHIFT 0 ++#define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc ++ ++/* POTAR - PCI Outbound Translation Address Register ++ */ ++#define POTAR_TA_MASK 0x000fffff ++ ++/* POBAR - PCI Outbound Base Address Register ++ */ ++#define POBAR_BA_MASK 0x000fffff ++ ++/* POCMR - PCI Outbound Comparision Mask Register ++ */ ++#define POCMR_EN 0x80000000 ++#define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ ++#define POCMR_SE 0x20000000 /* streaming enable */ ++#define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ ++#define POCMR_CM_MASK 0x000fffff ++#define POCMR_CM_4G 0x00000000 ++#define POCMR_CM_2G 0x00080000 ++#define POCMR_CM_1G 0x000C0000 ++#define POCMR_CM_512M 0x000E0000 ++#define POCMR_CM_256M 0x000F0000 ++#define POCMR_CM_128M 0x000F8000 ++#define POCMR_CM_64M 0x000FC000 ++#define POCMR_CM_32M 0x000FE000 ++#define POCMR_CM_16M 0x000FF000 ++#define POCMR_CM_8M 0x000FF800 ++#define POCMR_CM_4M 0x000FFC00 ++#define POCMR_CM_2M 0x000FFE00 ++#define POCMR_CM_1M 0x000FFF00 ++#define POCMR_CM_512K 0x000FFF80 ++#define POCMR_CM_256K 0x000FFFC0 ++#define POCMR_CM_128K 0x000FFFE0 ++#define POCMR_CM_64K 0x000FFFF0 ++#define POCMR_CM_32K 0x000FFFF8 ++#define POCMR_CM_16K 0x000FFFFC ++#define POCMR_CM_8K 0x000FFFFE ++#define POCMR_CM_4K 0x000FFFFF ++ ++/* PITAR - PCI Inbound Translation Address Register ++ */ ++#define PITAR_TA_MASK 0x000fffff ++ ++/* PIBAR - PCI Inbound Base/Extended Address Register ++ */ ++#define PIBAR_MASK 0xffffffff ++#define PIEBAR_EBA_MASK 0x000fffff ++ ++/* PIWAR - PCI Inbound Windows Attributes Register ++ */ ++#define PIWAR_EN 0x80000000 ++#define PIWAR_PF 0x20000000 ++#define PIWAR_RTT_MASK 0x000f0000 ++#define PIWAR_RTT_NO_SNOOP 0x00040000 ++#define PIWAR_RTT_SNOOP 0x00050000 ++#define PIWAR_WTT_MASK 0x0000f000 ++#define PIWAR_WTT_NO_SNOOP 0x00004000 ++#define PIWAR_WTT_SNOOP 0x00005000 ++#define PIWAR_IWS_MASK 0x0000003F ++#define PIWAR_IWS_4K 0x0000000B ++#define PIWAR_IWS_8K 0x0000000C ++#define PIWAR_IWS_16K 0x0000000D ++#define PIWAR_IWS_32K 0x0000000E ++#define PIWAR_IWS_64K 0x0000000F ++#define PIWAR_IWS_128K 0x00000010 ++#define PIWAR_IWS_256K 0x00000011 ++#define PIWAR_IWS_512K 0x00000012 ++#define PIWAR_IWS_1M 0x00000013 ++#define PIWAR_IWS_2M 0x00000014 ++#define PIWAR_IWS_4M 0x00000015 ++#define PIWAR_IWS_8M 0x00000016 ++#define PIWAR_IWS_16M 0x00000017 ++#define PIWAR_IWS_32M 0x00000018 ++#define PIWAR_IWS_64M 0x00000019 ++#define PIWAR_IWS_128M 0x0000001A ++#define PIWAR_IWS_256M 0x0000001B ++#define PIWAR_IWS_512M 0x0000001C ++#define PIWAR_IWS_1G 0x0000001D ++#define PIWAR_IWS_2G 0x0000001E + + #endif /* __MPC83XX_H__ */ diff --git a/packages/u-boot/u-boot-1.2.0/.mtn2git_empty b/packages/u-boot/u-boot-1.2.0/.mtn2git_empty new file mode 100644 index 0000000000..e69de29bb2 diff --git a/packages/u-boot/u-boot-1.2.0/defconfig_lsppchd b/packages/u-boot/u-boot-1.2.0/defconfig_lsppchd new file mode 100644 index 0000000000..5919f5eb2c --- /dev/null +++ b/packages/u-boot/u-boot-1.2.0/defconfig_lsppchd @@ -0,0 +1,500 @@ +/* + * Copyright (C) 2006 Mihai Georgian + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#if 0 +#define DEBUG +#endif + +/*----------------------------------------------------------------------- + * User configurable settings: + * Mandatory settings: + * CONFIG_IPADDR_LS - the IP address of the LinkStation + * CONFIG_SERVERIP_LS - the address of the server for NFS/TFTP/DHCP/BOOTP + * Optional settins: + * CONFIG_NCIP_LS - the adress of the computer running net console + * if not configured, it will be set to + * CONFIG_SERVERIP_LS + */ + +#define CONFIG_IPADDR_LS 192.168.11.150 +#define CONFIG_SERVERIP_LS 192.168.11.149 + +#if !defined(CONFIG_IPADDR_LS) || !defined(CONFIG_SERVERIP_LS) +#error Both CONFIG_IPADDR_LS and CONFIG_SERVERIP_LS must be defined +#endif + +#if !defined(CONFIG_NCIP_LS) +#define CONFIG_NCIP_LS CONFIG_SERVERIP_LS +#endif + +/*---------------------------------------------------------------------- + * DO NOT CHANGE ANYTHING BELOW, UNLESS YOU KNOW WHAT YOU ARE DOING + *---------------------------------------------------------------------*/ + +#define CONFIG_MPC8245 1 +#define CONFIG_LINKSTATION 1 + +/*--------------------------------------- + * Supported models + * + * LinkStation HDLAN /KuroBox Standard (CONFIG_HLAN) + * LinkStation old model (CONFIG_LAN) - totally untested + * LinkStation HGLAN / KuroBox HG (CONFIG_HGLAN) + * + * Models not supported yet + * TeraStatin (CONFIG_HTGL) + */ + +#if defined(CONFIG_HLAN) || defined(CONFIG_LAN) +#define CONFIG_IDENT_STRING " LinkStation / KuroBox" +#elif defined(CONFIG_HGLAN) +#define CONFIG_IDENT_STRING " LinkStation HG / KuroBox HG" +#elif defined(CONFIG_HTGL) +#define CONFIG_IDENT_STRING " TeraStation" +#else +#error No LinkStation model defined +#endif + +#define CONFIG_BOOTDELAY 10 +#define CONFIG_ZERO_BOOTDELAY_CHECK +#undef CONFIG_BOOT_RETRY_TIME + +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT "Boot in %02d seconds ('s' to stop)..." +#define CONFIG_AUTOBOOT_STOP_STR "s" + +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_LOADS | \ + CFG_CMD_LOADB | \ + CFG_CMD_FLASH | \ + CFG_CMD_MEMORY | \ + CFG_CMD_NET | \ + CFG_CMD_ENV | \ + CFG_CMD_IDE | \ + CFG_CMD_PCI | \ + CFG_CMD_BOOTD | \ + CFG_CMD_CONSOLE | \ + CFG_CMD_RUN | \ + CFG_CMD_ECHO | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING | \ + CFG_CMD_NFS | \ + CFG_CMD_EXT2 ) +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL + +#define CONFIG_OF_FLAT_TREE 1 + +#ifdef CONFIG_OF_FLAT_TREE +#define OF_CPU "PowerPC,603e" +#define OF_SOC "soc10x@80000000" +#define OF_STDOUT_PATH "/soc10x/serial@80004600" +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_MAXARGS 16 /* Max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00800000 /* Default load address: 8 MB */ + +//#define CONFIG_BOOTCOMMAND "run nfsboot" +#define CONFIG_BOOTCOMMAND "run bootcmd1" +#define CONFIG_BOOTARGS "root=/dev/sda1 netconsole=6666@192.168.11.150/,@192.168.11.149/ rtc-rs5c372.probe=0,0x32" +#define CONFIG_NFSBOOTCOMMAND "bootp;run nfsargs;bootm" + +#define CFG_CONSOLE_IS_IN_ENV + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +#if defined(CONFIG_HLAN) || defined(CONFIG_LAN) +#define UBFILE "share/u-boot/u-boot-hd.flash.bin" +#elif defined(CONFIG_HGLAN) +#define UBFILE "share/u-boot/u-boot-hg.flash.bin" +#elif defined(CONFIG_HTGL) +#define UBFILE "share/u-boot/u-boot-ht.flash.bin" +#else +#error No LinkStation model defined +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=no\0" \ + "stdin=nc\0" \ + "stdout=nc\0" \ + "stderr=nc\0" \ + "ipaddr="MK_STR(CONFIG_IPADDR_LS)"\0" \ + "netmask=255.255.255.0\0" \ + "serverip="MK_STR(CONFIG_SERVERIP_LS)"\0" \ + "ncip="MK_STR(CONFIG_NCIP_LS)"\0" \ + "netretry=no\0" \ + "nc=setenv stdin nc;setenv stdout nc;setenv stderr nc\0" \ + "ser=setenv stdin serial;setenv stdout serial;setenv stderr serial\0" \ + "ldaddr=800000\0" \ + "hdpart=0:1\0" \ + "hdfile=boot/uImage\0" \ + "hdload=echo Loading ${hdpart}:${hdfile};ext2load ide ${hdpart} ${ldaddr} ${hdfile};ext2load ide ${hdpart} 7f0000 boot/kuroboxHD.dtb\0" \ + "boothd=setenv bootargs " CONFIG_BOOTARGS ";bootm ${ldaddr} - 7f0000\0" \ + "hdboot=run hdload boothd\0" \ + "flboot=setenv bootargs root=/dev/hda1;bootm ffc00000\0" \ + "emboot=setenv bootargs root=/dev/ram0;bootm ffc00000\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \ + "bootretry=30\0" \ + "bootcmd1=run hdboot;run flboot\0" \ + "bootcmd2=run flboot\0" \ + "bootcmd3=run emboot\0" \ + "writeng=protect off fff70000 fff7ffff;era fff70000 fff7ffff;mw.l 800000 4e474e47 1;cp.b 800000 fff70000 4\0" \ + "writeok=protect off fff70000 fff7ffff;era fff70000 fff7ffff;mw.l 800000 4f4b4f4b 1;cp.b 800000 fff70000 4\0" \ + "ubpart=0:1\0" \ + "ubfile="UBFILE"\0" \ + "ubload=echo Loading ${ubpart}:${ubfile};ext2load ide ${ubpart} ${ldaddr} ${ubfile}\0" \ + "ubsaddr=fff00000\0" \ + "ubeaddr=fff2ffff\0" \ + "ubflash=protect off ${ubsaddr} ${ubeaddr};era ${ubsaddr} ${ubeaddr};cp.b ${ldaddr} ${ubsaddr} ${filesize};cmp.b ${ldaddr} ${ubsaddr} ${filesize}\0" \ + "upgrade=run ubload ubflash\0" + +/*----------------------------------------------------------------------- + * PCI stuff + */ +#define CONFIG_PCI +#undef CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW + +#ifndef CONFIG_PCI_PNP +/* Keep the following defines in sync with the BAT mappings */ + +#define PCI_ETH_IOADDR 0xbfff00 +#define PCI_ETH_MEMADDR 0xbffffc00 +#define PCI_IDE_IOADDR 0xbffed0 +#define PCI_IDE_MEMADDR 0xbffffb00 +#define PCI_USB0_IOADDR 0 +#define PCI_USB0_MEMADDR 0xbfffe000 +#define PCI_USB1_IOADDR 0 +#define PCI_USB1_MEMADDR 0xbfffd000 +#define PCI_USB2_IOADDR 0 +#define PCI_USB2_MEMADDR 0xbfffcf00 + +#endif + +/*----------------------------------------------------------------------- + * Ethernet stuff + */ +#define CONFIG_NET_MULTI + +#if defined(CONFIG_LAN) || defined(CONFIG_HLAN) +#define CONFIG_TULIP +#define CONFIG_TULIP_USE_IO +#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) +#define CONFIG_RTL8169 +#endif + +#define CONFIG_NET_RETRY_COUNT 5 + +#define CONFIG_NETCONSOLE + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 + +#define CFG_FLASH_BASE 0xFFC00000 +#define CFG_MONITOR_BASE TEXT_BASE + +#define CFG_RESET_ADDRESS 0xFFF00100 +#define CFG_EUMB_ADDR 0x80000000 +#define CFG_PCI_MEM_ADDR 0xB0000000 +#define CFG_MISC_REGION_ADDR 0xFE000000 + +#define CFG_MONITOR_LEN 0x00040000 /* 256 kB */ +#define CFG_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */ + +/* Maximum amount of RAM */ +#if defined(CONFIG_HLAN) || defined(CONFIG_LAN) +#define CFG_MAX_RAM_SIZE 0x04000000 /* 64MB of SDRAM */ +#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) +#define CFG_MAX_RAM_SIZE 0x08000000 /* 128MB of SDRAM */ +#else +#error Unknown LinkStation type +#endif + +/*----------------------------------------------------------------------- + * Change TEXT_BASE in bord/linkstation/config.mk to get a RAM build + * + * RAM based builds are for testing purposes. A Linux module, uloader.o, + * exists to load U-Boot and pass control to it + * + * Always do "make clean" after changing the build type + */ +#if CFG_MONITOR_BASE < CFG_FLASH_BASE +#define CFG_RAMBOOT +#endif + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ +#if 1 /* RAM is available when the first C function is called */ +#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE - 0x1000) +#else +#define CFG_INIT_RAM_ADDR 0x40000000 +#endif +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_SIZE 128 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/*---------------------------------------------------------------------- + * Serial configuration + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 57600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 + +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4600) /* Console port */ +#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4500) /* AVR port */ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + * For the detail description refer to the MPC8245 user's manual. + * + * Unless indicated otherwise, the values are + * taken from the orignal Linkstation boot code + * + * Most of the low level configuration setttings are normally used + * in cpu/mpc824x/cpu_init.c which is NOT used by this implementation. + * Low level initialisation is done in board/linkstation/early_init.S + * The values below are included for reference purpose only + */ + +/* FIXME: 32.768 MHz is the crystal frequency but */ +/* the real frequency is lower by about 0.75% */ +#define CONFIG_SYS_CLK_FREQ 32768000 +#define CFG_HZ 1000 + +/* Bit-field values for MCCR1. */ +#define CFG_ROMNAL 0 +#define CFG_ROMFAL 11 + +#define CFG_BANK0_ROW 2 /* Only bank 0 used: 13 x n x 4 */ +#define CFG_BANK1_ROW 0 +#define CFG_BANK2_ROW 0 +#define CFG_BANK3_ROW 0 +#define CFG_BANK4_ROW 0 +#define CFG_BANK5_ROW 0 +#define CFG_BANK6_ROW 0 +#define CFG_BANK7_ROW 0 + +/* Bit-field values for MCCR2. */ +#define CFG_TSWAIT 0 +#define CFG_REFINT 1400 + +/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ +#define CFG_BSTOPRE 121 + +/* Bit-field values for MCCR3. */ +#define CFG_REFREC 7 + +/* Bit-field values for MCCR4. */ +#define CFG_PRETOACT 2 +#define CFG_ACTTOPRE 5 /* Original value was 2 */ +#define CFG_ACTORW 2 +#define CFG_SDMODE_CAS_LAT 2 /* For 100MHz bus. Use 3 for 133MHz */ +#define CFG_REGISTERD_TYPE_BUFFER 1 +#define CFG_EXTROM 1 /* Original setting but there is no EXTROM */ +#define CFG_REGDIMM 0 +#define CFG_DBUS_SIZE2 1 +#define CFG_SDMODE_WRAP 0 + +#define CFG_PGMAX 0x32 /* All boards use this setting. Original 0x92 */ +#define CFG_SDRAM_DSCD 0x30 + +/* Memory bank settings. + * Only bits 20-29 are actually used from these vales to set the + * start/end addresses. The upper two bits will always be 0, and the lower + * 20 bits will be 0x00000 for a start address, or 0xfffff for an end + * address. Refer to the MPC8240 book. + */ + +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x3ff00000 +#define CFG_BANK1_END 0x3fffffff +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x3ff00000 +#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x3ff00000 +#define CFG_BANK4_END 0x3fffffff +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x3ff00000 +#define CFG_BANK5_END 0x3fffffff +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x3ff00000 +#define CFG_BANK6_END 0x3fffffff +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x3ff00000 +#define CFG_BANK7_END 0x3fffffff +#define CFG_BANK7_ENABLE 0 + +#define CFG_ODCR 0x95 /* 0x15 or 0x95 ? */ + +/*---------------------------------------------------------------------- + * Initial BAT mappings + */ + +/* NOTES: + * 1) GUARDED and WRITETHROUGH not allowed in IBATS + * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT + */ + +/* SDRAM */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U + +/* EUMB: 1MB of address space */ +#define CFG_IBAT1L (CFG_EUMB_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT1U (CFG_EUMB_ADDR | BATU_BL_1M | BATU_VS | BATU_VP) + +#define CFG_DBAT1L (CFG_IBAT1L | BATL_GUARDEDSTORAGE) +#define CFG_DBAT1U CFG_IBAT1U + +/* PCI Mem: 256MB of address space */ +#define CFG_IBAT2L (CFG_PCI_MEM_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (CFG_PCI_MEM_ADDR | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT2L (CFG_IBAT2L | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2U CFG_IBAT2U + +/* PCI and local ROM/Flash: last 32MB of address space */ +#define CFG_IBAT3L (CFG_MISC_REGION_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (CFG_MISC_REGION_ADDR | BATU_BL_32M | BATU_VS | BATU_VP) + +#define CFG_DBAT3L (CFG_IBAT3L | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + * + * FIXME: This doesn't appear to be true for the newer kernels + * which map more that 8 MB + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#undef CFG_FLASH_PROTECTION +#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 72 /* Max number of sectors per flash */ + +#define CFG_FLASH_ERASE_TOUT 12000 +#define CFG_FLASH_WRITE_TOUT 1000 + + +#define CFG_ENV_IS_IN_FLASH +/* + * The original LinkStation flash organisation uses + * 448 kB (0xFFF00000 - 0xFFF6FFFF) for the boot loader + * We use the last sector of this area to store the environment + * which leaves max. 384 kB for the U-Boot itself + */ +#define CFG_ENV_ADDR 0xFFF60000 +#define CFG_ENV_SIZE 0x00010000 +#define CFG_ENV_SECT_SIZE 0x00010000 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * IDE/ATA definitions + */ +#undef CONFIG_IDE_LED /* No IDE LED */ +#define CONFIG_IDE_RESET /* no reset for ide supported */ +#define CONFIG_IDE_PREINIT /* check for units */ +#define CONFIG_LBA48 /* 48 bit LBA supported */ + +#if defined(CONFIG_LAN) || defined(CONFIG_HLAN) || defined(CONFIG_HGLAN) +#define CFG_IDE_MAXBUS 1 /* Scan only 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* Only 1 drive per IDE bus */ +#elif defined(CONFIG_HGTL) +#define CFG_IDE_MAXBUS 2 /* Max. 2 IDE busses */ +#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ +#else +#error Config IDE: Unknown LinkStation type +#endif + +#define CFG_ATA_BASE_ADDR 0 + +#define CFG_ATA_DATA_OFFSET 0 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0 /* Offset for normal registers */ +#define CFG_ATA_ALT_OFFSET 0 /* Offset for alternate registers */ + +/*----------------------------------------------------------------------- + * Partitions and file system + */ +#define CONFIG_DOS_PARTITION + +/*----------------------------------------------------------------------- + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ + +/* vim: set ts=4: */ diff --git a/packages/u-boot/u-boot-1.2.0/defconfig_lsppchg b/packages/u-boot/u-boot-1.2.0/defconfig_lsppchg new file mode 100644 index 0000000000..b9943b4c76 --- /dev/null +++ b/packages/u-boot/u-boot-1.2.0/defconfig_lsppchg @@ -0,0 +1,500 @@ +/* + * Copyright (C) 2006 Mihai Georgian + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#if 0 +#define DEBUG +#endif + +/*----------------------------------------------------------------------- + * User configurable settings: + * Mandatory settings: + * CONFIG_IPADDR_LS - the IP address of the LinkStation + * CONFIG_SERVERIP_LS - the address of the server for NFS/TFTP/DHCP/BOOTP + * Optional settins: + * CONFIG_NCIP_LS - the adress of the computer running net console + * if not configured, it will be set to + * CONFIG_SERVERIP_LS + */ + +#define CONFIG_IPADDR_LS 192.168.11.150 +#define CONFIG_SERVERIP_LS 192.168.11.149 + +#if !defined(CONFIG_IPADDR_LS) || !defined(CONFIG_SERVERIP_LS) +#error Both CONFIG_IPADDR_LS and CONFIG_SERVERIP_LS must be defined +#endif + +#if !defined(CONFIG_NCIP_LS) +#define CONFIG_NCIP_LS CONFIG_SERVERIP_LS +#endif + +/*---------------------------------------------------------------------- + * DO NOT CHANGE ANYTHING BELOW, UNLESS YOU KNOW WHAT YOU ARE DOING + *---------------------------------------------------------------------*/ + +#define CONFIG_MPC8245 1 +#define CONFIG_LINKSTATION 1 + +/*--------------------------------------- + * Supported models + * + * LinkStation HDLAN /KuroBox Standard (CONFIG_HLAN) + * LinkStation old model (CONFIG_LAN) - totally untested + * LinkStation HGLAN / KuroBox HG (CONFIG_HGLAN) + * + * Models not supported yet + * TeraStatin (CONFIG_HTGL) + */ + +#if defined(CONFIG_HLAN) || defined(CONFIG_LAN) +#define CONFIG_IDENT_STRING " LinkStation / KuroBox" +#elif defined(CONFIG_HGLAN) +#define CONFIG_IDENT_STRING " LinkStation HG / KuroBox HG" +#elif defined(CONFIG_HTGL) +#define CONFIG_IDENT_STRING " TeraStation" +#else +#error No LinkStation model defined +#endif + +#define CONFIG_BOOTDELAY 10 +#define CONFIG_ZERO_BOOTDELAY_CHECK +#undef CONFIG_BOOT_RETRY_TIME + +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT "Boot in %02d seconds ('s' to stop)..." +#define CONFIG_AUTOBOOT_STOP_STR "s" + +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_LOADS | \ + CFG_CMD_LOADB | \ + CFG_CMD_FLASH | \ + CFG_CMD_MEMORY | \ + CFG_CMD_NET | \ + CFG_CMD_ENV | \ + CFG_CMD_IDE | \ + CFG_CMD_PCI | \ + CFG_CMD_BOOTD | \ + CFG_CMD_CONSOLE | \ + CFG_CMD_RUN | \ + CFG_CMD_ECHO | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING | \ + CFG_CMD_NFS | \ + CFG_CMD_EXT2 ) +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL + +#define CONFIG_OF_FLAT_TREE 1 + +#ifdef CONFIG_OF_FLAT_TREE +#define OF_CPU "PowerPC,603e" +#define OF_SOC "soc10x@80000000" +#define OF_STDOUT_PATH "/soc10x/serial@80004600" +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_MAXARGS 16 /* Max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00800000 /* Default load address: 8 MB */ + +//#define CONFIG_BOOTCOMMAND "run nfsboot" +#define CONFIG_BOOTCOMMAND "run bootcmd1" +#define CONFIG_BOOTARGS "root=/dev/sda1 netconsole=6666@192.168.11.150/,@192.168.11.149/ rtc-rs5c372.probe=0,0x32" +#define CONFIG_NFSBOOTCOMMAND "bootp;run nfsargs;bootm" + +#define CFG_CONSOLE_IS_IN_ENV + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +#if defined(CONFIG_HLAN) || defined(CONFIG_LAN) +#define UBFILE "share/u-boot/u-boot-hd.flash.bin" +#elif defined(CONFIG_HGLAN) +#define UBFILE "share/u-boot/u-boot-hg.flash.bin" +#elif defined(CONFIG_HTGL) +#define UBFILE "share/u-boot/u-boot-ht.flash.bin" +#else +#error No LinkStation model defined +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=no\0" \ + "stdin=nc\0" \ + "stdout=nc\0" \ + "stderr=nc\0" \ + "ipaddr="MK_STR(CONFIG_IPADDR_LS)"\0" \ + "netmask=255.255.255.0\0" \ + "serverip="MK_STR(CONFIG_SERVERIP_LS)"\0" \ + "ncip="MK_STR(CONFIG_NCIP_LS)"\0" \ + "netretry=no\0" \ + "nc=setenv stdin nc;setenv stdout nc;setenv stderr nc\0" \ + "ser=setenv stdin serial;setenv stdout serial;setenv stderr serial\0" \ + "ldaddr=800000\0" \ + "hdpart=0:1\0" \ + "hdfile=boot/uImage\0" \ + "hdload=echo Loading ${hdpart}:${hdfile};ext2load ide ${hdpart} ${ldaddr} ${hdfile};ext2load ide ${hdpart} 7f0000 boot/kuroboxHG.dtb\0" \ + "boothd=setenv bootargs " CONFIG_BOOTARGS ";bootm ${ldaddr} - 7f0000\0" \ + "hdboot=run hdload boothd\0" \ + "flboot=setenv bootargs root=/dev/hda1;bootm ffc00000\0" \ + "emboot=setenv bootargs root=/dev/ram0;bootm ffc00000\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \ + "bootretry=30\0" \ + "bootcmd1=run hdboot;run flboot\0" \ + "bootcmd2=run flboot\0" \ + "bootcmd3=run emboot\0" \ + "writeng=protect off fff70000 fff7ffff;era fff70000 fff7ffff;mw.l 800000 4e474e47 1;cp.b 800000 fff70000 4\0" \ + "writeok=protect off fff70000 fff7ffff;era fff70000 fff7ffff;mw.l 800000 4f4b4f4b 1;cp.b 800000 fff70000 4\0" \ + "ubpart=0:1\0" \ + "ubfile="UBFILE"\0" \ + "ubload=echo Loading ${ubpart}:${ubfile};ext2load ide ${ubpart} ${ldaddr} ${ubfile}\0" \ + "ubsaddr=fff00000\0" \ + "ubeaddr=fff2ffff\0" \ + "ubflash=protect off ${ubsaddr} ${ubeaddr};era ${ubsaddr} ${ubeaddr};cp.b ${ldaddr} ${ubsaddr} ${filesize};cmp.b ${ldaddr} ${ubsaddr} ${filesize}\0" \ + "upgrade=run ubload ubflash\0" + +/*----------------------------------------------------------------------- + * PCI stuff + */ +#define CONFIG_PCI +#undef CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW + +#ifndef CONFIG_PCI_PNP +/* Keep the following defines in sync with the BAT mappings */ + +#define PCI_ETH_IOADDR 0xbfff00 +#define PCI_ETH_MEMADDR 0xbffffc00 +#define PCI_IDE_IOADDR 0xbffed0 +#define PCI_IDE_MEMADDR 0xbffffb00 +#define PCI_USB0_IOADDR 0 +#define PCI_USB0_MEMADDR 0xbfffe000 +#define PCI_USB1_IOADDR 0 +#define PCI_USB1_MEMADDR 0xbfffd000 +#define PCI_USB2_IOADDR 0 +#define PCI_USB2_MEMADDR 0xbfffcf00 + +#endif + +/*----------------------------------------------------------------------- + * Ethernet stuff + */ +#define CONFIG_NET_MULTI + +#if defined(CONFIG_LAN) || defined(CONFIG_HLAN) +#define CONFIG_TULIP +#define CONFIG_TULIP_USE_IO +#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) +#define CONFIG_RTL8169 +#endif + +#define CONFIG_NET_RETRY_COUNT 5 + +#define CONFIG_NETCONSOLE + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 + +#define CFG_FLASH_BASE 0xFFC00000 +#define CFG_MONITOR_BASE TEXT_BASE + +#define CFG_RESET_ADDRESS 0xFFF00100 +#define CFG_EUMB_ADDR 0x80000000 +#define CFG_PCI_MEM_ADDR 0xB0000000 +#define CFG_MISC_REGION_ADDR 0xFE000000 + +#define CFG_MONITOR_LEN 0x00040000 /* 256 kB */ +#define CFG_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */ + +/* Maximum amount of RAM */ +#if defined(CONFIG_HLAN) || defined(CONFIG_LAN) +#define CFG_MAX_RAM_SIZE 0x04000000 /* 64MB of SDRAM */ +#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) +#define CFG_MAX_RAM_SIZE 0x08000000 /* 128MB of SDRAM */ +#else +#error Unknown LinkStation type +#endif + +/*----------------------------------------------------------------------- + * Change TEXT_BASE in bord/linkstation/config.mk to get a RAM build + * + * RAM based builds are for testing purposes. A Linux module, uloader.o, + * exists to load U-Boot and pass control to it + * + * Always do "make clean" after changing the build type + */ +#if CFG_MONITOR_BASE < CFG_FLASH_BASE +#define CFG_RAMBOOT +#endif + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ +#if 1 /* RAM is available when the first C function is called */ +#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE - 0x1000) +#else +#define CFG_INIT_RAM_ADDR 0x40000000 +#endif +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_SIZE 128 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/*---------------------------------------------------------------------- + * Serial configuration + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 57600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 + +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4600) /* Console port */ +#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4500) /* AVR port */ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + * For the detail description refer to the MPC8245 user's manual. + * + * Unless indicated otherwise, the values are + * taken from the orignal Linkstation boot code + * + * Most of the low level configuration setttings are normally used + * in cpu/mpc824x/cpu_init.c which is NOT used by this implementation. + * Low level initialisation is done in board/linkstation/early_init.S + * The values below are included for reference purpose only + */ + +/* FIXME: 32.768 MHz is the crystal frequency but */ +/* the real frequency is lower by about 0.75% */ +#define CONFIG_SYS_CLK_FREQ 32768000 +#define CFG_HZ 1000 + +/* Bit-field values for MCCR1. */ +#define CFG_ROMNAL 0 +#define CFG_ROMFAL 11 + +#define CFG_BANK0_ROW 2 /* Only bank 0 used: 13 x n x 4 */ +#define CFG_BANK1_ROW 0 +#define CFG_BANK2_ROW 0 +#define CFG_BANK3_ROW 0 +#define CFG_BANK4_ROW 0 +#define CFG_BANK5_ROW 0 +#define CFG_BANK6_ROW 0 +#define CFG_BANK7_ROW 0 + +/* Bit-field values for MCCR2. */ +#define CFG_TSWAIT 0 +#define CFG_REFINT 1400 + +/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ +#define CFG_BSTOPRE 121 + +/* Bit-field values for MCCR3. */ +#define CFG_REFREC 7 + +/* Bit-field values for MCCR4. */ +#define CFG_PRETOACT 2 +#define CFG_ACTTOPRE 5 /* Original value was 2 */ +#define CFG_ACTORW 2 +#define CFG_SDMODE_CAS_LAT 2 /* For 100MHz bus. Use 3 for 133MHz */ +#define CFG_REGISTERD_TYPE_BUFFER 1 +#define CFG_EXTROM 1 /* Original setting but there is no EXTROM */ +#define CFG_REGDIMM 0 +#define CFG_DBUS_SIZE2 1 +#define CFG_SDMODE_WRAP 0 + +#define CFG_PGMAX 0x32 /* All boards use this setting. Original 0x92 */ +#define CFG_SDRAM_DSCD 0x30 + +/* Memory bank settings. + * Only bits 20-29 are actually used from these vales to set the + * start/end addresses. The upper two bits will always be 0, and the lower + * 20 bits will be 0x00000 for a start address, or 0xfffff for an end + * address. Refer to the MPC8240 book. + */ + +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x3ff00000 +#define CFG_BANK1_END 0x3fffffff +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x3ff00000 +#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x3ff00000 +#define CFG_BANK4_END 0x3fffffff +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x3ff00000 +#define CFG_BANK5_END 0x3fffffff +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x3ff00000 +#define CFG_BANK6_END 0x3fffffff +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x3ff00000 +#define CFG_BANK7_END 0x3fffffff +#define CFG_BANK7_ENABLE 0 + +#define CFG_ODCR 0x95 /* 0x15 or 0x95 ? */ + +/*---------------------------------------------------------------------- + * Initial BAT mappings + */ + +/* NOTES: + * 1) GUARDED and WRITETHROUGH not allowed in IBATS + * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT + */ + +/* SDRAM */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U + +/* EUMB: 1MB of address space */ +#define CFG_IBAT1L (CFG_EUMB_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT1U (CFG_EUMB_ADDR | BATU_BL_1M | BATU_VS | BATU_VP) + +#define CFG_DBAT1L (CFG_IBAT1L | BATL_GUARDEDSTORAGE) +#define CFG_DBAT1U CFG_IBAT1U + +/* PCI Mem: 256MB of address space */ +#define CFG_IBAT2L (CFG_PCI_MEM_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (CFG_PCI_MEM_ADDR | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_DBAT2L (CFG_IBAT2L | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2U CFG_IBAT2U + +/* PCI and local ROM/Flash: last 32MB of address space */ +#define CFG_IBAT3L (CFG_MISC_REGION_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (CFG_MISC_REGION_ADDR | BATU_BL_32M | BATU_VS | BATU_VP) + +#define CFG_DBAT3L (CFG_IBAT3L | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + * + * FIXME: This doesn't appear to be true for the newer kernels + * which map more that 8 MB + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#undef CFG_FLASH_PROTECTION +#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 72 /* Max number of sectors per flash */ + +#define CFG_FLASH_ERASE_TOUT 12000 +#define CFG_FLASH_WRITE_TOUT 1000 + + +#define CFG_ENV_IS_IN_FLASH +/* + * The original LinkStation flash organisation uses + * 448 kB (0xFFF00000 - 0xFFF6FFFF) for the boot loader + * We use the last sector of this area to store the environment + * which leaves max. 384 kB for the U-Boot itself + */ +#define CFG_ENV_ADDR 0xFFF60000 +#define CFG_ENV_SIZE 0x00010000 +#define CFG_ENV_SECT_SIZE 0x00010000 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * IDE/ATA definitions + */ +#undef CONFIG_IDE_LED /* No IDE LED */ +#define CONFIG_IDE_RESET /* no reset for ide supported */ +#define CONFIG_IDE_PREINIT /* check for units */ +#define CONFIG_LBA48 /* 48 bit LBA supported */ + +#if defined(CONFIG_LAN) || defined(CONFIG_HLAN) || defined(CONFIG_HGLAN) +#define CFG_IDE_MAXBUS 1 /* Scan only 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* Only 1 drive per IDE bus */ +#elif defined(CONFIG_HGTL) +#define CFG_IDE_MAXBUS 2 /* Max. 2 IDE busses */ +#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ +#else +#error Config IDE: Unknown LinkStation type +#endif + +#define CFG_ATA_BASE_ADDR 0 + +#define CFG_ATA_DATA_OFFSET 0 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0 /* Offset for normal registers */ +#define CFG_ATA_ALT_OFFSET 0 /* Offset for alternate registers */ + +/*----------------------------------------------------------------------- + * Partitions and file system + */ +#define CONFIG_DOS_PARTITION + +/*----------------------------------------------------------------------- + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ + +/* vim: set ts=4: */ diff --git a/packages/u-boot/u-boot-1.2.0/env-Makefile.patch b/packages/u-boot/u-boot-1.2.0/env-Makefile.patch new file mode 100644 index 0000000000..f6e9cb39ae --- /dev/null +++ b/packages/u-boot/u-boot-1.2.0/env-Makefile.patch @@ -0,0 +1,19 @@ +--- u-boot-1.2.0/tools/env/Makefile.orig 2007-12-12 12:52:51.508745236 -0800 ++++ u-boot-1.2.0/tools/env/Makefile 2007-12-12 12:54:09.997218038 -0800 +@@ -31,7 +31,7 @@ + all: $(obj)fw_printenv + + $(obj)fw_printenv: $(SRCS) $(HEADERS) +- $(CROSS_COMPILE)gcc $(CPPFLAGS) $(SRCS) -o $(obj)fw_printenv ++ $(CROSS_COMPILE)gcc $(TARGET_CFLAGS) -idirafter ../../include -DUSE_HOSTCC $(SRCS) -o $(obj)fw_printenv + + clean: + rm -f $(obj)fw_printenv $(obj)crc32.c +@@ -43,6 +43,6 @@ + + include $(TOPDIR)/rules.mk + +-sinclude $(obj).depend ++#sinclude $(obj).depend + + ######################################################################### diff --git a/packages/u-boot/u-boot-1.2.0/fic-gta01/.mtn2git_empty b/packages/u-boot/u-boot-1.2.0/fic-gta01/.mtn2git_empty new file mode 100644 index 0000000000..e69de29bb2 diff --git a/packages/u-boot/u-boot-1.2.0/fic-gta01/fw_env.config b/packages/u-boot/u-boot-1.2.0/fic-gta01/fw_env.config new file mode 100644 index 0000000000..9fe07672c5 --- /dev/null +++ b/packages/u-boot/u-boot-1.2.0/fic-gta01/fw_env.config @@ -0,0 +1,6 @@ +# Configuration file for fw_(printenv/saveenv) utility. +# Up to two entries are valid, in this case the redundand +# environment sector is assumed present. + +# MTD device name Device offset Env. size Flash sector size +/dev/mtd1 0x0000 0x4000 0x4000 diff --git a/packages/u-boot/u-boot-1.2.0/fw_env.c.patch b/packages/u-boot/u-boot-1.2.0/fw_env.c.patch new file mode 100644 index 0000000000..62f364ad4a --- /dev/null +++ b/packages/u-boot/u-boot-1.2.0/fw_env.c.patch @@ -0,0 +1,13 @@ +--- u-boot-1.1.2.orig/tools/env/fw_env.c 2004-12-31 01:32:54.000000000 -0800 ++++ u-boot-1.1.2/tools/env/fw_env.c 2006-11-08 12:43:41.000000000 -0800 +@@ -31,7 +31,9 @@ + #include + #include + #include +-#include ++#include ++#include ++#include + #include "fw_env.h" + + typedef unsigned char uchar; diff --git a/packages/u-boot/u-boot-1.2.0/fw_env.config b/packages/u-boot/u-boot-1.2.0/fw_env.config new file mode 100644 index 0000000000..2432bd866c --- /dev/null +++ b/packages/u-boot/u-boot-1.2.0/fw_env.config @@ -0,0 +1,7 @@ +# Configuration file for fw_(printenv/saveenv) utility. +# Up to two entries are valid, in this case the redundand +# environment sector is assumed present. + +# MTD device name Device offset Env. size Flash sector size +/dev/mtd1 0x0000 0x4000 0x4000 +/dev/mtd2 0x0000 0x4000 0x4000 diff --git a/packages/u-boot/u-boot-1.2.0/kurobox_powerpc-20061105_target.gitdiff b/packages/u-boot/u-boot-1.2.0/kurobox_powerpc-20061105_target.gitdiff new file mode 100644 index 0000000000..02027b1062 --- /dev/null +++ b/packages/u-boot/u-boot-1.2.0/kurobox_powerpc-20061105_target.gitdiff @@ -0,0 +1,2286 @@ +diff --git a/arch/powerpc/boot/dts/kuroboxHG.dts b/arch/powerpc/boot/dts/kuroboxHG.dts +new file mode 100644 +index 0000000..6c76ef6 +--- /dev/null ++++ b/arch/powerpc/boot/dts/kuroboxHG.dts +@@ -0,0 +1,183 @@ ++/* ++ * Device Tree Souce for Buffalo KuroboxHG ++ * ++ * Based on sandpoint.dts ++ * ++ * 2006 (c) G. Liakhovetski ++ * ++ * This file is licensed under ++ * the terms of the GNU General Public License version 2. This program ++ * is licensed "as is" without any warranty of any kind, whether express ++ * or implied. ++ ++XXXX add flash parts, rtc, ?? ++ ++build with: "dtc -f -I dts -O dtb -o kuroboxHG.dtb -V 16 kuroboxHG.dts" ++ ++ ++ */ ++ ++/ { ++ linux,phandle = <1000>; ++ model = "KuroboxHG"; ++ compatible = "linkstation"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ cpus { ++ linux,phandle = <2000>; ++ #cpus = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ PowerPC,603e { /* Really 8241 */ ++ linux,phandle = <2100>; ++ linux,boot-cpu; ++ device_type = "cpu"; ++ reg = <0>; ++ clock-frequency = ; /* Fixed by bootwrapper */ ++ timebase-frequency = <1F04000>; /* Fixed by bootwrapper */ ++ bus-frequency = <0>; /* From bootloader */ ++ /* Following required by dtc but not used */ ++ i-cache-line-size = <0>; ++ d-cache-line-size = <0>; ++ i-cache-size = <4000>; ++ d-cache-size = <4000>; ++ }; ++ }; ++ ++ memory { ++ linux,phandle = <3000>; ++ device_type = "memory"; ++ reg = <00000000 08000000>; ++ }; ++ ++ soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */ ++ linux,phandle = <4000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ #interrupt-cells = <2>; ++ device_type = "soc"; ++ compatible = "mpc10x"; ++ store-gathering = <0>; /* 0 == off, !0 == on */ ++ reg = <80000000 00100000>; ++ ranges = <80000000 80000000 70000000 /* pci mem space */ ++ fc000000 fc000000 00100000 /* EUMB */ ++ fe000000 fe000000 00c00000 /* pci i/o space */ ++ fec00000 fec00000 00300000 /* pci cfg regs */ ++ fef00000 fef00000 00100000>; /* pci iack */ ++ ++ dma@80001100 { ++ linux,phandle = <4100>; ++ #interrupt-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ device_type = "dma"; ++ compatible = "fsl-dma"; ++ clock-frequency = <0>; ++ reg = <80001100 24>; ++ interrupts = <6 0>; ++ interrupt-parent = <4400>; ++ }; ++ ++ dma@80001200 { ++ linux,phandle = <4200>; ++ #interrupt-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ device_type = "dma"; ++ compatible = "fsl-dma"; ++ clock-frequency = <0>; ++ reg = <80001200 24>; ++ interrupts = <7 0>; ++ interrupt-parent = <4400>; ++ }; ++ ++ i2c@80003000 { ++ linux,phandle = <4300>; ++ device_type = "i2c"; ++ compatible = "fsl-i2c"; ++ clock-frequency = <0>; ++ reg = <80003000 1000>; ++ interrupts = <5 2>; ++ interrupt-parent = <4400>; ++ }; ++ ++ serial@80004500 { ++ linux,phandle = <4511>; ++ device_type = "serial"; ++ compatible = "ns16550"; ++ reg = <80004500 8>; ++ clock-frequency = <7c044a8>; ++ current-speed = <2580>; ++ interrupts = <9 2>; ++ interrupt-parent = <4400>; ++ }; ++ ++ serial@80004600 { ++ linux,phandle = <4512>; ++ device_type = "serial"; ++ compatible = "ns16550"; ++ reg = <80004600 8>; ++ clock-frequency = <7c044a8>; ++ current-speed = ; ++ interrupts = ; ++ interrupt-parent = <4400>; ++ }; ++ ++ pic@80040000 { ++ linux,phandle = <4400>; ++ #interrupt-cells = <2>; ++ #address-cells = <0>; ++ device_type = "open-pic"; ++ compatible = "chrp,open-pic"; ++ interrupt-controller; ++ reg = <80040000 40000>; ++ clock-frequency = <0>; /* ??? */ ++ built-in; ++ }; ++ ++ pci@fec00000 { ++ linux,phandle = <4500>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ device_type = "pci"; ++ compatible = "mpc10x-pci"; ++ reg = ; ++ ranges = <01000000 0 0 fe000000 0 00c00000 ++ 02000000 0 80000000 80000000 0 70000000>; ++ bus-range = <0 ff>; ++ clock-frequency = <7f28155>; ++ interrupt-parent = <4400>; ++ interrupt-map-mask = ; ++ interrupt-map = < ++ /* IDSEL 0x11 - IRQ0 ETH */ ++ 5800 0 0 1 4400 0 1 ++ 5800 0 0 2 4400 1 1 ++ 5800 0 0 3 4400 2 1 ++ 5800 0 0 4 4400 3 1 ++ /* IDSEL 0x12 - IRQ1 IDE0 */ ++ 6000 0 0 1 4400 1 1 ++ 6000 0 0 2 4400 2 1 ++ 6000 0 0 3 4400 3 1 ++ 6000 0 0 4 4400 0 1 ++ /* IDSEL 0x13 - IRQ4 IDE1 */ ++ 6800 0 0 1 4400 3 1 ++ 6800 0 0 2 4400 0 1 ++ 6800 0 0 3 4400 1 1 ++ 6800 0 0 4 4400 2 1 ++ /* IDSEL 0x14 - IRQ3 USB2.0 */ ++ 7000 0 0 1 4400 3 1 ++ 7000 0 0 2 4400 3 1 ++ 7000 0 0 3 4400 3 1 ++ 7000 0 0 4 4400 3 1 ++ /* IDSEL 0x15 - IRQ2 fan ctrl*/ ++ 7800 0 0 1 4400 2 1 ++ 7800 0 0 2 4400 3 1 ++ 7800 0 0 3 4400 0 1 ++ 7800 0 0 4 4400 1 1 ++ >; ++ }; ++ }; ++}; +diff --git a/arch/powerpc/configs/kuroboxhg_defconfig b/arch/powerpc/configs/kuroboxhg_defconfig +new file mode 100644 +index 0000000..136632f +--- /dev/null ++++ b/arch/powerpc/configs/kuroboxhg_defconfig +@@ -0,0 +1,1577 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.19-rc2 ++# Wed Nov 1 16:56:07 2006 ++# ++# CONFIG_PPC64 is not set ++CONFIG_PPC32=y ++CONFIG_PPC_MERGE=y ++CONFIG_MMU=y ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_IRQ_PER_CPU=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_GENERIC_FIND_NEXT_BIT=y ++CONFIG_PPC=y ++CONFIG_EARLY_PRINTK=y ++CONFIG_GENERIC_NVRAM=y ++CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y ++CONFIG_ARCH_MAY_HAVE_PC_FDC=y ++CONFIG_PPC_OF=y ++CONFIG_PPC_UDBG_16550=y ++# CONFIG_GENERIC_TBSYNC is not set ++CONFIG_AUDIT_ARCH=y ++# CONFIG_DEFAULT_UIMAGE is not set ++ ++# ++# Processor support ++# ++CONFIG_CLASSIC32=y ++# CONFIG_PPC_52xx is not set ++# CONFIG_PPC_82xx is not set ++# CONFIG_PPC_83xx is not set ++# CONFIG_PPC_85xx is not set ++# CONFIG_PPC_86xx is not set ++# CONFIG_40x is not set ++# CONFIG_44x is not set ++# CONFIG_8xx is not set ++# CONFIG_E200 is not set ++CONFIG_6xx=y ++CONFIG_PPC_FPU=y ++# CONFIG_ALTIVEC is not set ++CONFIG_PPC_STD_MMU=y ++CONFIG_PPC_STD_MMU_32=y ++# CONFIG_SMP is not set ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# Code maturity level options ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++ ++# ++# General setup ++# ++CONFIG_LOCALVERSION="-kuroboxHG" ++CONFIG_LOCALVERSION_AUTO=y ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++# CONFIG_IPC_NS is not set ++CONFIG_POSIX_MQUEUE=y ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_UTS_NS is not set ++# CONFIG_AUDIT is not set ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++# CONFIG_RELAY is not set ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++# CONFIG_KALLSYMS_ALL is not set ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SHMEM=y ++CONFIG_SLAB=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++# CONFIG_SLOB is not set ++ ++# ++# Loadable module support ++# ++CONFIG_MODULES=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++ ++# ++# Block layer ++# ++CONFIG_BLOCK=y ++# CONFIG_LBD is not set ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_LSF is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++CONFIG_DEFAULT_AS=y ++# CONFIG_DEFAULT_DEADLINE is not set ++# CONFIG_DEFAULT_CFQ is not set ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="anticipatory" ++ ++# ++# Platform support ++# ++# CONFIG_PPC_MULTIPLATFORM is not set ++CONFIG_EMBEDDED6xx=y ++# CONFIG_APUS is not set ++# CONFIG_PPC_CELL is not set ++# CONFIG_PPC_CELL_NATIVE is not set ++# CONFIG_PPC_RTAS is not set ++# CONFIG_MMIO_NVRAM is not set ++# CONFIG_PPC_MPC106 is not set ++# CONFIG_PPC_970_NAP is not set ++# CONFIG_CPU_FREQ is not set ++# CONFIG_TAU is not set ++# CONFIG_KATANA is not set ++# CONFIG_WILLOW is not set ++# CONFIG_CPCI690 is not set ++# CONFIG_POWERPMC250 is not set ++# CONFIG_CHESTNUT is not set ++# CONFIG_SPRUCE is not set ++# CONFIG_HDPU is not set ++# CONFIG_EV64260 is not set ++# CONFIG_LOPEC is not set ++# CONFIG_MVME5100 is not set ++# CONFIG_PPLUS is not set ++# CONFIG_PRPMC750 is not set ++# CONFIG_PRPMC800 is not set ++# CONFIG_SANDPOINT is not set ++CONFIG_LINKSTATION=y ++# CONFIG_MPC7448HPC2 is not set ++# CONFIG_RADSTONE_PPC7D is not set ++# CONFIG_PAL4 is not set ++# CONFIG_GEMINI is not set ++# CONFIG_EST8260 is not set ++# CONFIG_SBC82xx is not set ++# CONFIG_SBS8260 is not set ++# CONFIG_RPX8260 is not set ++# CONFIG_TQM8260 is not set ++# CONFIG_ADS8272 is not set ++# CONFIG_PQ2FADS is not set ++# CONFIG_LITE5200 is not set ++# CONFIG_EV64360 is not set ++CONFIG_PPC_GEN550=y ++CONFIG_MPC10X_BRIDGE=y ++CONFIG_MPC10X_OPENPIC=y ++# CONFIG_MPC10X_STORE_GATHERING is not set ++# CONFIG_WANT_EARLY_SERIAL is not set ++CONFIG_MPIC=y ++ ++# ++# Kernel options ++# ++# CONFIG_HIGHMEM is not set ++CONFIG_HZ_100=y ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_PREEMPT_NONE=y ++# CONFIG_PREEMPT_VOLUNTARY is not set ++# CONFIG_PREEMPT is not set ++CONFIG_BINFMT_ELF=y ++# CONFIG_BINFMT_MISC is not set ++CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y ++CONFIG_ARCH_FLATMEM_ENABLE=y ++CONFIG_ARCH_POPULATES_NODE_MAP=y ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++# CONFIG_SPARSEMEM_STATIC is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_RESOURCES_64BIT is not set ++CONFIG_PROC_DEVICETREE=y ++CONFIG_CMDLINE_BOOL=y ++CONFIG_CMDLINE="console=ttyS1,57600 root=/dev/sdd1 netconsole=@192.168.1.7/eth0,@192.168.1.1/00:50:BF:A4:59:71 rtc-rs5c372.probe=0,0x32" ++# CONFIG_PM is not set ++# CONFIG_SECCOMP is not set ++CONFIG_ISA_DMA_API=y ++ ++# ++# Bus options ++# ++CONFIG_GENERIC_ISA_DMA=y ++# CONFIG_MPIC_WEIRD is not set ++# CONFIG_PPC_I8259 is not set ++CONFIG_PPC_INDIRECT_PCI=y ++CONFIG_FSL_SOC=y ++CONFIG_PCI=y ++CONFIG_PCI_DOMAINS=y ++# CONFIG_PCIEPORTBUS is not set ++# CONFIG_PCI_MULTITHREAD_PROBE is not set ++# CONFIG_PCI_DEBUG is not set ++ ++# ++# PCCARD (PCMCIA/CardBus) support ++# ++# CONFIG_PCCARD is not set ++ ++# ++# PCI Hotplug Support ++# ++# CONFIG_HOTPLUG_PCI is not set ++ ++# ++# Advanced setup ++# ++# CONFIG_ADVANCED_OPTIONS is not set ++ ++# ++# Default settings for advanced configuration options are used ++# ++CONFIG_HIGHMEM_START=0xfe000000 ++CONFIG_LOWMEM_SIZE=0x30000000 ++CONFIG_KERNEL_START=0xc0000000 ++CONFIG_TASK_SIZE=0x80000000 ++CONFIG_BOOT_LOAD=0x00800000 ++ ++# ++# Networking ++# ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_NETDEBUG is not set ++CONFIG_PACKET=y ++CONFIG_PACKET_MMAP=y ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_BOOTP=y ++# CONFIG_IP_PNP_RARP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE is not set ++# CONFIG_IP_MROUTE is not set ++# CONFIG_ARPD is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++CONFIG_INET_XFRM_MODE_TRANSPORT=y ++CONFIG_INET_XFRM_MODE_TUNNEL=y ++CONFIG_INET_XFRM_MODE_BEET=y ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++ ++# ++# IP: Virtual Server Configuration ++# ++# CONFIG_IP_VS is not set ++# CONFIG_IPV6 is not set ++# CONFIG_INET6_XFRM_TUNNEL is not set ++# CONFIG_INET6_TUNNEL is not set ++# CONFIG_NETWORK_SECMARK is not set ++CONFIG_NETFILTER=y ++# CONFIG_NETFILTER_DEBUG is not set ++ ++# ++# Core Netfilter Configuration ++# ++# CONFIG_NETFILTER_NETLINK is not set ++CONFIG_NETFILTER_XTABLES=m ++CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m ++# CONFIG_NETFILTER_XT_TARGET_DSCP is not set ++CONFIG_NETFILTER_XT_TARGET_MARK=m ++# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set ++# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set ++# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set ++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m ++# CONFIG_NETFILTER_XT_MATCH_DCCP is not set ++# CONFIG_NETFILTER_XT_MATCH_DSCP is not set ++CONFIG_NETFILTER_XT_MATCH_ESP=m ++# CONFIG_NETFILTER_XT_MATCH_HELPER is not set ++CONFIG_NETFILTER_XT_MATCH_LENGTH=m ++CONFIG_NETFILTER_XT_MATCH_LIMIT=m ++CONFIG_NETFILTER_XT_MATCH_MAC=m ++CONFIG_NETFILTER_XT_MATCH_MARK=m ++# CONFIG_NETFILTER_XT_MATCH_POLICY is not set ++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m ++CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m ++# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set ++# CONFIG_NETFILTER_XT_MATCH_REALM is not set ++# CONFIG_NETFILTER_XT_MATCH_SCTP is not set ++CONFIG_NETFILTER_XT_MATCH_STATE=m ++# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set ++# CONFIG_NETFILTER_XT_MATCH_STRING is not set ++# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set ++ ++# ++# IP: Netfilter Configuration ++# ++CONFIG_IP_NF_CONNTRACK=m ++# CONFIG_IP_NF_CT_ACCT is not set ++# CONFIG_IP_NF_CONNTRACK_MARK is not set ++# CONFIG_IP_NF_CONNTRACK_EVENTS is not set ++# CONFIG_IP_NF_CT_PROTO_SCTP is not set ++CONFIG_IP_NF_FTP=m ++CONFIG_IP_NF_IRC=m ++# CONFIG_IP_NF_NETBIOS_NS is not set ++CONFIG_IP_NF_TFTP=m ++# CONFIG_IP_NF_AMANDA is not set ++# CONFIG_IP_NF_PPTP is not set ++# CONFIG_IP_NF_H323 is not set ++# CONFIG_IP_NF_SIP is not set ++# CONFIG_IP_NF_QUEUE is not set ++CONFIG_IP_NF_IPTABLES=m ++CONFIG_IP_NF_MATCH_IPRANGE=m ++# CONFIG_IP_NF_MATCH_TOS is not set ++# CONFIG_IP_NF_MATCH_RECENT is not set ++# CONFIG_IP_NF_MATCH_ECN is not set ++# CONFIG_IP_NF_MATCH_AH is not set ++# CONFIG_IP_NF_MATCH_TTL is not set ++# CONFIG_IP_NF_MATCH_OWNER is not set ++# CONFIG_IP_NF_MATCH_ADDRTYPE is not set ++# CONFIG_IP_NF_MATCH_HASHLIMIT is not set ++CONFIG_IP_NF_FILTER=m ++CONFIG_IP_NF_TARGET_REJECT=m ++# CONFIG_IP_NF_TARGET_LOG is not set ++# CONFIG_IP_NF_TARGET_ULOG is not set ++# CONFIG_IP_NF_TARGET_TCPMSS is not set ++CONFIG_IP_NF_NAT=m ++CONFIG_IP_NF_NAT_NEEDED=y ++CONFIG_IP_NF_TARGET_MASQUERADE=m ++CONFIG_IP_NF_TARGET_REDIRECT=m ++CONFIG_IP_NF_TARGET_NETMAP=m ++CONFIG_IP_NF_TARGET_SAME=m ++# CONFIG_IP_NF_NAT_SNMP_BASIC is not set ++CONFIG_IP_NF_NAT_IRC=m ++CONFIG_IP_NF_NAT_FTP=m ++CONFIG_IP_NF_NAT_TFTP=m ++CONFIG_IP_NF_MANGLE=m ++CONFIG_IP_NF_TARGET_TOS=m ++CONFIG_IP_NF_TARGET_ECN=m ++CONFIG_IP_NF_TARGET_TTL=m ++CONFIG_IP_NF_RAW=m ++CONFIG_IP_NF_ARPTABLES=m ++CONFIG_IP_NF_ARPFILTER=m ++CONFIG_IP_NF_ARP_MANGLE=m ++ ++# ++# DCCP Configuration (EXPERIMENTAL) ++# ++# CONFIG_IP_DCCP is not set ++ ++# ++# SCTP Configuration (EXPERIMENTAL) ++# ++# CONFIG_IP_SCTP is not set ++ ++# ++# TIPC Configuration (EXPERIMENTAL) ++# ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++ ++# ++# QoS and/or fair queueing ++# ++# CONFIG_NET_SCHED is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++CONFIG_IEEE80211=m ++CONFIG_IEEE80211_DEBUG=y ++CONFIG_IEEE80211_CRYPT_WEP=m ++CONFIG_IEEE80211_CRYPT_CCMP=m ++CONFIG_IEEE80211_CRYPT_TKIP=m ++CONFIG_IEEE80211_SOFTMAC=m ++CONFIG_IEEE80211_SOFTMAC_DEBUG=y ++CONFIG_WIRELESS_EXT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=m ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_SYS_HYPERVISOR is not set ++ ++# ++# Connector - unified userspace <-> kernelspace linker ++# ++# CONFIG_CONNECTOR is not set ++ ++# ++# Memory Technology Devices (MTD) ++# ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++CONFIG_MTD_CONCAT=y ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_REDBOOT_PARTS is not set ++# CONFIG_MTD_CMDLINE_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_CHAR=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++CONFIG_MTD_CFI=y ++CONFIG_MTD_JEDECPROBE=y ++CONFIG_MTD_GEN_PROBE=y ++CONFIG_MTD_CFI_ADV_OPTIONS=y ++CONFIG_MTD_CFI_NOSWAP=y ++# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set ++# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set ++CONFIG_MTD_CFI_GEOMETRY=y ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++# CONFIG_MTD_MAP_BANK_WIDTH_2 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++# CONFIG_MTD_CFI_I2 is not set ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_OTP is not set ++# CONFIG_MTD_CFI_INTELEXT is not set ++CONFIG_MTD_CFI_AMDSTD=y ++# CONFIG_MTD_CFI_STAA is not set ++CONFIG_MTD_CFI_UTIL=y ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++# CONFIG_MTD_OBSOLETE_CHIPS is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP=y ++CONFIG_MTD_PHYSMAP_START=0xffc00000 ++CONFIG_MTD_PHYSMAP_LEN=0x400000 ++CONFIG_MTD_PHYSMAP_BANKWIDTH=1 ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_PMC551 is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++ ++# ++# NAND Flash Device Drivers ++# ++# CONFIG_MTD_NAND is not set ++ ++# ++# OneNAND Flash Device Drivers ++# ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# Parallel port support ++# ++# CONFIG_PARPORT is not set ++ ++# ++# Plug and Play support ++# ++ ++# ++# Block devices ++# ++# CONFIG_BLK_DEV_FD is not set ++# CONFIG_BLK_CPQ_DA is not set ++# CONFIG_BLK_CPQ_CISS_DA is not set ++# CONFIG_BLK_DEV_DAC960 is not set ++# CONFIG_BLK_DEV_UMEM is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_SX8 is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=2 ++CONFIG_BLK_DEV_RAM_SIZE=8192 ++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 ++CONFIG_BLK_DEV_INITRD=y ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++ ++# ++# ATA/ATAPI/MFM/RLL support ++# ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++CONFIG_CHR_DEV_SG=y ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++CONFIG_SCSI_MULTI_LUN=y ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++ ++# ++# SCSI low-level drivers ++# ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_BLK_DEV_3W_XXXX_RAID is not set ++# CONFIG_SCSI_3W_9XXX is not set ++# CONFIG_SCSI_ACARD is not set ++# CONFIG_SCSI_AACRAID is not set ++# CONFIG_SCSI_AIC7XXX is not set ++# CONFIG_SCSI_AIC7XXX_OLD is not set ++# CONFIG_SCSI_AIC79XX is not set ++# CONFIG_SCSI_AIC94XX is not set ++# CONFIG_SCSI_DPT_I2O is not set ++# CONFIG_SCSI_ARCMSR is not set ++# CONFIG_MEGARAID_NEWGEN is not set ++# CONFIG_MEGARAID_LEGACY is not set ++# CONFIG_MEGARAID_SAS is not set ++# CONFIG_SCSI_HPTIOP is not set ++# CONFIG_SCSI_BUSLOGIC is not set ++# CONFIG_SCSI_DMX3191D is not set ++# CONFIG_SCSI_EATA is not set ++# CONFIG_SCSI_FUTURE_DOMAIN is not set ++# CONFIG_SCSI_GDTH is not set ++# CONFIG_SCSI_IPS is not set ++# CONFIG_SCSI_INITIO is not set ++# CONFIG_SCSI_INIA100 is not set ++# CONFIG_SCSI_STEX is not set ++# CONFIG_SCSI_SYM53C8XX_2 is not set ++# CONFIG_SCSI_IPR is not set ++# CONFIG_SCSI_QLOGIC_1280 is not set ++# CONFIG_SCSI_QLA_FC is not set ++# CONFIG_SCSI_QLA_ISCSI is not set ++# CONFIG_SCSI_LPFC is not set ++# CONFIG_SCSI_DC395x is not set ++# CONFIG_SCSI_DC390T is not set ++# CONFIG_SCSI_NSP32 is not set ++# CONFIG_SCSI_DEBUG is not set ++ ++# ++# Serial ATA (prod) and Parallel ATA (experimental) drivers ++# ++CONFIG_ATA=y ++# CONFIG_SATA_AHCI is not set ++# CONFIG_SATA_SVW is not set ++# CONFIG_ATA_PIIX is not set ++# CONFIG_SATA_MV is not set ++# CONFIG_SATA_NV is not set ++# CONFIG_PDC_ADMA is not set ++# CONFIG_SATA_QSTOR is not set ++# CONFIG_SATA_PROMISE is not set ++# CONFIG_SATA_SX4 is not set ++# CONFIG_SATA_SIL is not set ++# CONFIG_SATA_SIL24 is not set ++# CONFIG_SATA_SIS is not set ++# CONFIG_SATA_ULI is not set ++# CONFIG_SATA_VIA is not set ++# CONFIG_SATA_VITESSE is not set ++# CONFIG_PATA_ALI is not set ++# CONFIG_PATA_AMD is not set ++# CONFIG_PATA_ARTOP is not set ++# CONFIG_PATA_ATIIXP is not set ++# CONFIG_PATA_CMD64X is not set ++# CONFIG_PATA_CS5520 is not set ++# CONFIG_PATA_CS5530 is not set ++# CONFIG_PATA_CYPRESS is not set ++# CONFIG_PATA_EFAR is not set ++# CONFIG_ATA_GENERIC is not set ++# CONFIG_PATA_HPT366 is not set ++# CONFIG_PATA_HPT37X is not set ++# CONFIG_PATA_HPT3X2N is not set ++# CONFIG_PATA_HPT3X3 is not set ++# CONFIG_PATA_IT821X is not set ++# CONFIG_PATA_JMICRON is not set ++# CONFIG_PATA_TRIFLEX is not set ++# CONFIG_PATA_MPIIX is not set ++# CONFIG_PATA_OLDPIIX is not set ++# CONFIG_PATA_NETCELL is not set ++# CONFIG_PATA_NS87410 is not set ++# CONFIG_PATA_OPTI is not set ++# CONFIG_PATA_OPTIDMA is not set ++# CONFIG_PATA_PDC_OLD is not set ++# CONFIG_PATA_RADISYS is not set ++# CONFIG_PATA_RZ1000 is not set ++# CONFIG_PATA_SC1200 is not set ++# CONFIG_PATA_SERVERWORKS is not set ++# CONFIG_PATA_PDC2027X is not set ++CONFIG_PATA_SIL680=y ++# CONFIG_PATA_SIS is not set ++# CONFIG_PATA_VIA is not set ++# CONFIG_PATA_WINBOND is not set ++ ++# ++# Multi-device support (RAID and LVM) ++# ++# CONFIG_MD is not set ++ ++# ++# Fusion MPT device support ++# ++# CONFIG_FUSION is not set ++# CONFIG_FUSION_SPI is not set ++# CONFIG_FUSION_FC is not set ++# CONFIG_FUSION_SAS is not set ++ ++# ++# IEEE 1394 (FireWire) support ++# ++# CONFIG_IEEE1394 is not set ++ ++# ++# I2O device support ++# ++# CONFIG_I2O is not set ++ ++# ++# Macintosh device drivers ++# ++# CONFIG_WINDFARM is not set ++ ++# ++# Network device support ++# ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_EQUALIZER is not set ++CONFIG_TUN=m ++ ++# ++# ARCnet devices ++# ++# CONFIG_ARCNET is not set ++ ++# ++# PHY device support ++# ++ ++# ++# Ethernet (10 or 100Mbit) ++# ++# CONFIG_NET_ETHERNET is not set ++ ++# ++# Ethernet (1000 Mbit) ++# ++# CONFIG_ACENIC is not set ++# CONFIG_DL2K is not set ++# CONFIG_E1000 is not set ++# CONFIG_NS83820 is not set ++# CONFIG_HAMACHI is not set ++# CONFIG_YELLOWFIN is not set ++CONFIG_R8169=y ++# CONFIG_R8169_NAPI is not set ++# CONFIG_SIS190 is not set ++# CONFIG_SKGE is not set ++# CONFIG_SKY2 is not set ++# CONFIG_SK98LIN is not set ++# CONFIG_TIGON3 is not set ++# CONFIG_BNX2 is not set ++# CONFIG_QLA3XXX is not set ++ ++# ++# Ethernet (10000 Mbit) ++# ++# CONFIG_CHELSIO_T1 is not set ++# CONFIG_IXGB is not set ++# CONFIG_S2IO is not set ++# CONFIG_MYRI10GE is not set ++ ++# ++# Token Ring devices ++# ++# CONFIG_TR is not set ++ ++# ++# Wireless LAN (non-hamradio) ++# ++CONFIG_NET_RADIO=y ++# CONFIG_NET_WIRELESS_RTNETLINK is not set ++ ++# ++# Obsolete Wireless cards support (pre-802.11) ++# ++# CONFIG_STRIP is not set ++ ++# ++# Wireless 802.11b ISA/PCI cards support ++# ++# CONFIG_IPW2100 is not set ++# CONFIG_IPW2200 is not set ++# CONFIG_AIRO is not set ++# CONFIG_HERMES is not set ++# CONFIG_ATMEL is not set ++ ++# ++# Prism GT/Duette 802.11(a/b/g) PCI/Cardbus support ++# ++# CONFIG_PRISM54 is not set ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_HOSTAP is not set ++# CONFIG_BCM43XX is not set ++# CONFIG_ZD1211RW is not set ++CONFIG_NET_WIRELESS=y ++ ++# ++# Wan interfaces ++# ++# CONFIG_WAN is not set ++# CONFIG_FDDI is not set ++# CONFIG_HIPPI is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NET_FC is not set ++# CONFIG_SHAPER is not set ++CONFIG_NETCONSOLE=y ++CONFIG_NETPOLL=y ++# CONFIG_NETPOLL_RX is not set ++# CONFIG_NETPOLL_TRAP is not set ++CONFIG_NET_POLL_CONTROLLER=y ++ ++# ++# ISDN subsystem ++# ++# CONFIG_ISDN is not set ++ ++# ++# Telephony Support ++# ++# CONFIG_PHONE is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_TSDEV is not set ++CONFIG_INPUT_EVDEV=m ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++CONFIG_INPUT_MISC=y ++CONFIG_INPUT_UINPUT=m ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++# CONFIG_SERIO_I8042 is not set ++CONFIG_SERIO_SERPORT=y ++# CONFIG_SERIO_PCIPS2 is not set ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++ ++# ++# Serial drivers ++# ++CONFIG_SERIAL_8250=y ++CONFIG_SERIAL_8250_CONSOLE=y ++CONFIG_SERIAL_8250_PCI=y ++CONFIG_SERIAL_8250_NR_UARTS=4 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=4 ++# CONFIG_SERIAL_8250_EXTENDED is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_JSM is not set ++CONFIG_UNIX98_PTYS=y ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++ ++# ++# IPMI ++# ++# CONFIG_IPMI_HANDLER is not set ++ ++# ++# Watchdog Cards ++# ++# CONFIG_WATCHDOG is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_NVRAM is not set ++# CONFIG_GEN_RTC is not set ++# CONFIG_DTLK is not set ++# CONFIG_R3964 is not set ++# CONFIG_APPLICOM is not set ++ ++# ++# Ftape, the floppy tape device driver ++# ++# CONFIG_AGP is not set ++# CONFIG_DRM is not set ++# CONFIG_RAW_DRIVER is not set ++ ++# ++# TPM devices ++# ++# CONFIG_TCG_TPM is not set ++# CONFIG_TELCLOCK is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_CHARDEV=y ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++# CONFIG_I2C_ALI1535 is not set ++# CONFIG_I2C_ALI1563 is not set ++# CONFIG_I2C_ALI15X3 is not set ++# CONFIG_I2C_AMD756 is not set ++# CONFIG_I2C_AMD8111 is not set ++# CONFIG_I2C_I801 is not set ++# CONFIG_I2C_I810 is not set ++# CONFIG_I2C_PIIX4 is not set ++CONFIG_I2C_MPC=y ++# CONFIG_I2C_NFORCE2 is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_PROSAVAGE is not set ++# CONFIG_I2C_SAVAGE4 is not set ++# CONFIG_I2C_SIS5595 is not set ++# CONFIG_I2C_SIS630 is not set ++# CONFIG_I2C_SIS96X is not set ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_VIA is not set ++# CONFIG_I2C_VIAPRO is not set ++# CONFIG_I2C_VOODOO3 is not set ++# CONFIG_I2C_PCA_ISA is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++# CONFIG_SENSORS_DS1337 is not set ++# CONFIG_SENSORS_DS1374 is not set ++CONFIG_SENSORS_EEPROM=m ++# CONFIG_SENSORS_PCF8574 is not set ++# CONFIG_SENSORS_PCA9539 is not set ++# CONFIG_SENSORS_PCF8591 is not set ++# CONFIG_SENSORS_M41T00 is not set ++# CONFIG_SENSORS_MAX6875 is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_I2C_DEBUG_CHIP is not set ++ ++# ++# SPI support ++# ++# CONFIG_SPI is not set ++# CONFIG_SPI_MASTER is not set ++ ++# ++# Dallas's 1-wire bus ++# ++ ++# ++# Hardware Monitoring support ++# ++CONFIG_HWMON=y ++# CONFIG_HWMON_VID is not set ++# CONFIG_SENSORS_ABITUGURU is not set ++# CONFIG_SENSORS_ADM1021 is not set ++# CONFIG_SENSORS_ADM1025 is not set ++# CONFIG_SENSORS_ADM1026 is not set ++# CONFIG_SENSORS_ADM1031 is not set ++# CONFIG_SENSORS_ADM9240 is not set ++# CONFIG_SENSORS_ASB100 is not set ++# CONFIG_SENSORS_ATXP1 is not set ++# CONFIG_SENSORS_DS1621 is not set ++# CONFIG_SENSORS_F71805F is not set ++# CONFIG_SENSORS_FSCHER is not set ++# CONFIG_SENSORS_FSCPOS is not set ++# CONFIG_SENSORS_GL518SM is not set ++# CONFIG_SENSORS_GL520SM is not set ++# CONFIG_SENSORS_IT87 is not set ++# CONFIG_SENSORS_LM63 is not set ++# CONFIG_SENSORS_LM75 is not set ++# CONFIG_SENSORS_LM77 is not set ++# CONFIG_SENSORS_LM78 is not set ++# CONFIG_SENSORS_LM80 is not set ++# CONFIG_SENSORS_LM83 is not set ++# CONFIG_SENSORS_LM85 is not set ++# CONFIG_SENSORS_LM87 is not set ++# CONFIG_SENSORS_LM90 is not set ++# CONFIG_SENSORS_LM92 is not set ++# CONFIG_SENSORS_MAX1619 is not set ++# CONFIG_SENSORS_PC87360 is not set ++# CONFIG_SENSORS_SIS5595 is not set ++# CONFIG_SENSORS_SMSC47M1 is not set ++# CONFIG_SENSORS_SMSC47M192 is not set ++# CONFIG_SENSORS_SMSC47B397 is not set ++# CONFIG_SENSORS_VIA686A is not set ++# CONFIG_SENSORS_VT1211 is not set ++# CONFIG_SENSORS_VT8231 is not set ++# CONFIG_SENSORS_W83781D is not set ++# CONFIG_SENSORS_W83791D is not set ++# CONFIG_SENSORS_W83792D is not set ++# CONFIG_SENSORS_W83L785TS is not set ++# CONFIG_SENSORS_W83627HF is not set ++# CONFIG_SENSORS_W83627EHF is not set ++# CONFIG_HWMON_DEBUG_CHIP is not set ++ ++# ++# Misc devices ++# ++# CONFIG_TIFM_CORE is not set ++ ++# ++# Multimedia devices ++# ++# CONFIG_VIDEO_DEV is not set ++ ++# ++# Digital Video Broadcasting Devices ++# ++# CONFIG_DVB is not set ++# CONFIG_USB_DABUSB is not set ++ ++# ++# Graphics support ++# ++CONFIG_FIRMWARE_EDID=y ++# CONFIG_FB is not set ++ ++# ++# Console display driver support ++# ++# CONFIG_VGA_CONSOLE is not set ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Sound ++# ++# CONFIG_SOUND is not set ++ ++# ++# USB support ++# ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB_ARCH_HAS_OHCI=y ++CONFIG_USB_ARCH_HAS_EHCI=y ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEVICEFS=y ++# CONFIG_USB_BANDWIDTH is not set ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++ ++# ++# USB Host Controller Drivers ++# ++CONFIG_USB_EHCI_HCD=y ++# CONFIG_USB_EHCI_SPLIT_ISO is not set ++# CONFIG_USB_EHCI_ROOT_HUB_TT is not set ++# CONFIG_USB_EHCI_TT_NEWSCHED is not set ++# CONFIG_USB_ISP116X_HCD is not set ++CONFIG_USB_OHCI_HCD=y ++# CONFIG_USB_OHCI_BIG_ENDIAN is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_UHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++ ++# ++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' ++# ++ ++# ++# may also be needed; see USB_STORAGE Help for more information ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_DPCM is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_LIBUSUAL is not set ++ ++# ++# USB Input Devices ++# ++# CONFIG_USB_HID is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++# CONFIG_USB_AIPTEK is not set ++# CONFIG_USB_WACOM is not set ++# CONFIG_USB_ACECAD is not set ++# CONFIG_USB_KBTAB is not set ++# CONFIG_USB_POWERMATE is not set ++# CONFIG_USB_TOUCHSCREEN is not set ++# CONFIG_USB_YEALINK is not set ++# CONFIG_USB_XPAD is not set ++# CONFIG_USB_ATI_REMOTE is not set ++# CONFIG_USB_ATI_REMOTE2 is not set ++# CONFIG_USB_KEYSPAN_REMOTE is not set ++# CONFIG_USB_APPLETOUCH is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_USBNET is not set ++CONFIG_USB_MON=y ++ ++# ++# USB port drivers ++# ++ ++# ++# USB Serial Converter support ++# ++CONFIG_USB_SERIAL=y ++CONFIG_USB_SERIAL_CONSOLE=y ++# CONFIG_USB_SERIAL_GENERIC is not set ++# CONFIG_USB_SERIAL_AIRCABLE is not set ++# CONFIG_USB_SERIAL_AIRPRIME is not set ++# CONFIG_USB_SERIAL_ARK3116 is not set ++# CONFIG_USB_SERIAL_BELKIN is not set ++# CONFIG_USB_SERIAL_WHITEHEAT is not set ++# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set ++# CONFIG_USB_SERIAL_CP2101 is not set ++# CONFIG_USB_SERIAL_CYPRESS_M8 is not set ++# CONFIG_USB_SERIAL_EMPEG is not set ++CONFIG_USB_SERIAL_FTDI_SIO=y ++# CONFIG_USB_SERIAL_FUNSOFT is not set ++# CONFIG_USB_SERIAL_VISOR is not set ++# CONFIG_USB_SERIAL_IPAQ is not set ++# CONFIG_USB_SERIAL_IR is not set ++# CONFIG_USB_SERIAL_EDGEPORT is not set ++# CONFIG_USB_SERIAL_EDGEPORT_TI is not set ++# CONFIG_USB_SERIAL_GARMIN is not set ++# CONFIG_USB_SERIAL_IPW is not set ++# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set ++# CONFIG_USB_SERIAL_KEYSPAN is not set ++# CONFIG_USB_SERIAL_KLSI is not set ++# CONFIG_USB_SERIAL_KOBIL_SCT is not set ++# CONFIG_USB_SERIAL_MCT_U232 is not set ++# CONFIG_USB_SERIAL_MOS7840 is not set ++# CONFIG_USB_SERIAL_NAVMAN is not set ++# CONFIG_USB_SERIAL_PL2303 is not set ++# CONFIG_USB_SERIAL_HP4X is not set ++# CONFIG_USB_SERIAL_SAFE is not set ++# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set ++# CONFIG_USB_SERIAL_TI is not set ++# CONFIG_USB_SERIAL_CYBERJACK is not set ++# CONFIG_USB_SERIAL_XIRCOM is not set ++# CONFIG_USB_SERIAL_OPTION is not set ++# CONFIG_USB_SERIAL_OMNINET is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_AUERSWALD is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_PHIDGET is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TEST is not set ++ ++# ++# USB DSL modem support ++# ++ ++# ++# USB Gadget Support ++# ++# CONFIG_USB_GADGET is not set ++ ++# ++# MMC/SD Card support ++# ++# CONFIG_MMC is not set ++ ++# ++# LED devices ++# ++# CONFIG_NEW_LEDS is not set ++ ++# ++# LED drivers ++# ++ ++# ++# LED Triggers ++# ++ ++# ++# InfiniBand support ++# ++# CONFIG_INFINIBAND is not set ++ ++# ++# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) ++# ++ ++# ++# Real Time Clock ++# ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++ ++# ++# RTC drivers ++# ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++CONFIG_RTC_DRV_RS5C372=y ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_TEST is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# DMA Engine support ++# ++# CONFIG_DMA_ENGINE is not set ++ ++# ++# DMA Clients ++# ++ ++# ++# DMA Devices ++# ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=y ++# CONFIG_EXT2_FS_XATTR is not set ++# CONFIG_EXT2_FS_XIP is not set ++CONFIG_EXT3_FS=y ++CONFIG_EXT3_FS_XATTR=y ++# CONFIG_EXT3_FS_POSIX_ACL is not set ++# CONFIG_EXT3_FS_SECURITY is not set ++# CONFIG_EXT4DEV_FS is not set ++CONFIG_JBD=y ++# CONFIG_JBD_DEBUG is not set ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_FS_POSIX_ACL=y ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_ROMFS_FS is not set ++CONFIG_INOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_QUOTA is not set ++CONFIG_DNOTIFY=y ++# CONFIG_AUTOFS_FS is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++CONFIG_ISO9660_FS=m ++CONFIG_JOLIET=y ++CONFIG_ZISOFS=y ++CONFIG_ZISOFS_FS=m ++CONFIG_UDF_FS=m ++CONFIG_UDF_NLS=y ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_KCORE=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_RAMFS=y ++# CONFIG_CONFIGFS_FS is not set ++ ++# ++# Miscellaneous filesystems ++# ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_JFFS_FS is not set ++# CONFIG_JFFS2_FS is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_VXFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++ ++# ++# Network File Systems ++# ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++# CONFIG_NFS_DIRECTIO is not set ++CONFIG_NFSD=m ++CONFIG_NFSD_V3=y ++# CONFIG_NFSD_V3_ACL is not set ++# CONFIG_NFSD_V4 is not set ++CONFIG_NFSD_TCP=y ++CONFIG_ROOT_NFS=y ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_EXPORTFS=m ++CONFIG_NFS_ACL_SUPPORT=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++CONFIG_SUNRPC_GSS=y ++CONFIG_RPCSEC_GSS_KRB5=y ++# CONFIG_RPCSEC_GSS_SPKM3 is not set ++# CONFIG_SMB_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++# CONFIG_9P_FS is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++ ++# ++# Native Language Support ++# ++CONFIG_NLS=m ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=m ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=m ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++CONFIG_NLS_UTF8=m ++ ++# ++# Library routines ++# ++# CONFIG_CRC_CCITT is not set ++# CONFIG_CRC16 is not set ++CONFIG_CRC32=y ++CONFIG_LIBCRC32C=m ++CONFIG_ZLIB_INFLATE=m ++CONFIG_ZLIB_DEFLATE=m ++CONFIG_PLIST=y ++ ++# ++# Instrumentation Support ++# ++CONFIG_PROFILING=y ++CONFIG_OPROFILE=m ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_MAGIC_SYSRQ=y ++# CONFIG_UNUSED_SYMBOLS is not set ++CONFIG_DEBUG_KERNEL=y ++CONFIG_LOG_BUF_SHIFT=14 ++CONFIG_DETECT_SOFTLOCKUP=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_DEBUG_SLAB is not set ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_RT_MUTEX_TESTER is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++# CONFIG_DEBUG_MUTEXES is not set ++# CONFIG_DEBUG_RWSEMS is not set ++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_INFO is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_LIST is not set ++CONFIG_FORCED_INLINING=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_DEBUGGER is not set ++# CONFIG_BDI_SWITCH is not set ++# CONFIG_BOOTX_TEXT is not set ++# CONFIG_SERIAL_TEXT_DEBUG is not set ++# CONFIG_PPC_EARLY_DEBUG is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY is not set ++ ++# ++# Cryptographic options ++# ++CONFIG_CRYPTO=y ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_MANAGER=m ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_MD4=m ++CONFIG_CRYPTO_MD5=y ++CONFIG_CRYPTO_SHA1=m ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_WP512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_CBC is not set ++CONFIG_CRYPTO_DES=y ++CONFIG_CRYPTO_BLOWFISH=m ++CONFIG_CRYPTO_TWOFISH=m ++CONFIG_CRYPTO_TWOFISH_COMMON=m ++CONFIG_CRYPTO_SERPENT=m ++CONFIG_CRYPTO_AES=m ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_TEA is not set ++CONFIG_CRYPTO_ARC4=m ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_DEFLATE=m ++CONFIG_CRYPTO_MICHAEL_MIC=m ++CONFIG_CRYPTO_CRC32C=m ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Hardware crypto devices ++# +diff --git a/arch/powerpc/platforms/embedded6xx/Kconfig b/arch/powerpc/platforms/embedded6xx/Kconfig +index 234a861..c1c6748 100644 +--- a/arch/powerpc/platforms/embedded6xx/Kconfig ++++ b/arch/powerpc/platforms/embedded6xx/Kconfig +@@ -76,6 +76,15 @@ config PRPMC800 + Select SANDPOINT if configuring for a Motorola Sandpoint X3 + (any flavor). + ++config LINKSTATION ++ bool "Linkstation / Kurobox(HG) from Buffalo" ++ select MPIC ++ select FSL_SOC ++ select PPC_UDBG_16550 if SERIAL_8250 ++ help ++ Select LINKSTATION if configuring for a PPC-based Linkstation ++ (LS-1) or Kurobox(HG) from Buffalo Technologies. ++ + config MPC7448HPC2 + bool "Freescale MPC7448HPC2(Taiga)" + select TSI108_BRIDGE +@@ -210,7 +219,7 @@ config PPC_GEN550 + depends on SANDPOINT || SPRUCE || PPLUS || \ + PRPMC750 || PRPMC800 || LOPEC || \ + (EV64260 && !SERIAL_MPSC) || CHESTNUT || RADSTONE_PPC7D || \ +- 83xx ++ 83xx || LINKSTATION + default y + + config FORCE +@@ -284,13 +293,13 @@ config HARRIER + + config MPC10X_BRIDGE + bool +- depends on POWERPMC250 || LOPEC || SANDPOINT ++ depends on POWERPMC250 || LOPEC || SANDPOINT || LINKSTATION + select PPC_INDIRECT_PCI + default y + + config MPC10X_OPENPIC + bool +- depends on POWERPMC250 || LOPEC || SANDPOINT ++ depends on POWERPMC250 || LOPEC || SANDPOINT || LINKSTATION + default y + + config MPC10X_STORE_GATHERING +diff --git a/arch/powerpc/platforms/embedded6xx/Makefile b/arch/powerpc/platforms/embedded6xx/Makefile +index fa499fe..1f3edc7 100644 +--- a/arch/powerpc/platforms/embedded6xx/Makefile ++++ b/arch/powerpc/platforms/embedded6xx/Makefile +@@ -3,3 +3,4 @@ # + # + obj-$(CONFIG_MPC7448HPC2) += mpc7448_hpc2.o + obj-$(CONFIG_SANDPOINT) += sandpoint.o ++obj-$(CONFIG_LINKSTATION) += linkstation.o ls_uart.o +diff --git a/arch/powerpc/platforms/embedded6xx/linkstation.c b/arch/powerpc/platforms/embedded6xx/linkstation.c +new file mode 100644 +index 0000000..30bcb5b +--- /dev/null ++++ b/arch/powerpc/platforms/embedded6xx/linkstation.c +@@ -0,0 +1,254 @@ ++/* ++ * arch/powerpc/platforms/embedded6xx/linkstation.c ++ * ++ * Board setup routines for the Buffalo Linkstation / Kurobox Platform. ++ * ++ * Author: Mark A. Greer ++ * mgreer@mvista.com ++ * ++ * 2000-2003 (c) MontaVista Software, Inc. This file is licensed under ++ * the terms of the GNU General Public License version 2. This program ++ * is licensed "as is" without any warranty of any kind, whether express ++ * or implied. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* for linux/serial_core.h */ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct mtd_partition linkstation_physmap_partitions[] = { ++ { ++ .name = "mtd_firmimg", ++ .offset = 0x000000, ++ .size = 0x300000, ++ }, ++ { ++ .name = "mtd_bootcode", ++ .offset = 0x300000, ++ .size = 0x70000, ++ }, ++ { ++ .name = "mtd_status", ++ .offset = 0x370000, ++ .size = 0x10000, ++ }, ++ { ++ .name = "mtd_conf", ++ .offset = 0x380000, ++ .size = 0x80000, ++ }, ++ { ++ .name = "mtd_allflash", ++ .offset = 0x000000, ++ .size = 0x400000, ++ }, ++ { ++ .name = "mtd_data", ++ .offset = 0x310000, ++ .size = 0xf0000, ++ }, ++}; ++ ++/* ++ * Buffalo linkstation interrupt routing. ++ */ ++ ++void __init linkstation_pcibios_fixup(void) ++{ ++ struct pci_dev *dev = NULL; ++ ++ for_each_pci_dev(dev) ++ pci_read_irq_line(dev); ++} ++ ++static int __init add_bridge(struct device_node *dev) ++{ ++ int len; ++ struct pci_controller *hose; ++ int *bus_range; ++ ++ printk("Adding PCI host bridge %s\n", dev->full_name); ++ ++ bus_range = (int *) get_property(dev, "bus-range", &len); ++ if (bus_range == NULL || len < 2 * sizeof(int)) ++ printk(KERN_WARNING "Can't get bus-range for %s, assume" ++ " bus 0\n", dev->full_name); ++ ++ hose = pcibios_alloc_controller(); ++ if (hose == NULL) ++ return -ENOMEM; ++ hose->first_busno = bus_range ? bus_range[0] : 0; ++ hose->last_busno = bus_range ? bus_range[1] : 0xff; ++ hose->arch_data = dev; ++ setup_indirect_pci(hose, 0xfec00000, 0xfee00000); ++ ++ /* Interpret the "ranges" property */ ++ /* This also maps the I/O region and sets isa_io/mem_base */ ++ pci_process_bridge_OF_ranges(hose, dev, 1); ++ ++ return 0; ++} ++ ++static void __init linkstation_setup_arch(void) ++{ ++ struct device_node *np; ++#ifdef CONFIG_MTD_PHYSMAP ++ physmap_set_partitions(linkstation_physmap_partitions, ++ ARRAY_SIZE(linkstation_physmap_partitions)); ++#endif ++ ++#ifdef CONFIG_BLK_DEV_INITRD ++ if (initrd_start) ++ ROOT_DEV = Root_RAM0; ++ else ++#endif ++#ifdef CONFIG_ROOT_NFS ++ ROOT_DEV = Root_NFS; ++#else ++ ROOT_DEV = Root_HDA1; ++#endif ++ ++ /* Lookup PCI host bridges */ ++ for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) ++ add_bridge(np); ++ ++ ppc_md.pci_swizzle = common_swizzle; ++ ++ printk(KERN_INFO "BUFFALO Network Attached Storage Series\n"); ++ printk(KERN_INFO "(C) 2002-2005 BUFFALO INC.\n"); ++} ++ ++/* ++ * Interrupt setup and service. Interrrupts on the linkstation come ++ * from the four PCI slots plus onboard 8241 devices: I2C, DUART. ++ */ ++static void __init linkstation_init_IRQ(void) ++{ ++ struct mpic *mpic; ++ struct device_node *dnp; ++ void *prop; ++ int size; ++ phys_addr_t paddr; ++ ++ dnp = of_find_node_by_type(NULL, "open-pic"); ++ if (dnp == NULL) ++ return; ++ ++ prop = (struct device_node *)get_property(dnp, "reg", &size); ++ paddr = (phys_addr_t)of_translate_address(dnp, prop); ++ ++ mpic = mpic_alloc(dnp, paddr, MPIC_PRIMARY | MPIC_WANTS_RESET, 4, 32, " EPIC "); ++ BUG_ON(mpic == NULL); ++ ++ /* PCI IRQs */ ++ mpic_assign_isu(mpic, 0, paddr + 0x10200); ++ ++ /* I2C */ ++ mpic_assign_isu(mpic, 1, paddr + 0x11000); ++ ++ /* ttyS0, ttyS1 */ ++ mpic_assign_isu(mpic, 2, paddr + 0x11100); ++ ++ mpic_init(mpic); ++} ++ ++extern void avr_uart_configure(void); ++extern void avr_uart_send(const char); ++ ++static void linkstation_restart(char *cmd) ++{ ++ local_irq_disable(); ++ ++ /* Reset system via AVR */ ++ avr_uart_configure(); ++ /* Send reboot command */ ++ avr_uart_send('C'); ++ ++ for(;;) /* Spin until reset happens */ ++ avr_uart_send('G'); /* "kick" */ ++} ++ ++static void linkstation_power_off(void) ++{ ++ local_irq_disable(); ++ ++ avr_uart_configure(); ++ /* send shutdown command */ ++ avr_uart_send('E'); ++ ++ for(;;) /* Spin until power-off happens */ ++ avr_uart_send('G'); /* "kick" */ ++ /* NOTREACHED */ ++} ++ ++static void linkstation_halt(void) ++{ ++ linkstation_power_off(); ++ /* NOTREACHED */ ++} ++ ++static void linkstation_show_cpuinfo(struct seq_file *m) ++{ ++ seq_printf(m, "vendor\t\t: Buffalo Technology\n"); ++ seq_printf(m, "machine\t\t: Linkstation I/Kurobox(HG)\n"); ++} ++ ++static int __init linkstation_probe(void) ++{ ++ unsigned long root; ++ ++ root = of_get_flat_dt_root(); ++ ++ if (!of_flat_dt_is_compatible(root, "linkstation")) ++ return 0; ++ return 1; ++} ++ ++define_machine(linkstation){ ++ .name = "Buffalo Linkstation", ++ .probe = linkstation_probe, ++ .setup_arch = linkstation_setup_arch, ++ .init_IRQ = linkstation_init_IRQ, ++ .show_cpuinfo = linkstation_show_cpuinfo, ++ .pcibios_fixup = linkstation_pcibios_fixup, ++ .get_irq = mpic_get_irq, ++ .restart = linkstation_restart, ++ .power_off = linkstation_power_off, ++ .halt = linkstation_halt, ++ .calibrate_decr = generic_calibrate_decr, ++}; +diff --git a/arch/powerpc/platforms/embedded6xx/ls_uart.c b/arch/powerpc/platforms/embedded6xx/ls_uart.c +new file mode 100644 +index 0000000..b640115 +--- /dev/null ++++ b/arch/powerpc/platforms/embedded6xx/ls_uart.c +@@ -0,0 +1,131 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static void __iomem *avr_addr; ++static unsigned long avr_clock; ++ ++static struct work_struct wd_work; ++ ++static void wd_stop(void *unused) ++{ ++ const char string[] = "AAAAFFFFJJJJ>>>>VVVV>>>>ZZZZVVVVKKKK"; ++ int i = 0, rescue = 8; ++ int len = strlen(string); ++ ++ while (rescue--) { ++ int j; ++ char lsr = in_8(avr_addr + UART_LSR); ++ ++ if (lsr & (UART_LSR_THRE | UART_LSR_TEMT)) { ++ for (j = 0; j < 16 && i < len; j++, i++) ++ out_8(avr_addr + UART_TX, string[i]); ++ if (i == len) { ++ /* Read "OK" back: 4ms for the last "KKKK" ++ plus a couple bytes back */ ++ msleep(7); ++ printk("linkstation: disarming the AVR watchdog: "); ++ while (in_8(avr_addr + UART_LSR) & UART_LSR_DR) ++ printk("%c", in_8(avr_addr + UART_RX)); ++ break; ++ } ++ } ++ msleep(17); ++ } ++ printk("\n"); ++} ++ ++#define AVR_QUOT(clock) ((clock) + 8 * 9600) / (16 * 9600) ++ ++void avr_uart_configure(void) ++{ ++ unsigned char cval = UART_LCR_WLEN8; ++ unsigned int quot = AVR_QUOT(avr_clock); ++ ++ if (!avr_addr || !avr_clock) ++ return; ++ ++ out_8(avr_addr + UART_LCR, cval); /* initialise UART */ ++ out_8(avr_addr + UART_MCR, 0); ++ out_8(avr_addr + UART_IER, 0); ++ ++ cval |= UART_LCR_STOP | UART_LCR_PARITY | UART_LCR_EPAR; ++ ++ out_8(avr_addr + UART_LCR, cval); /* Set character format */ ++ ++ out_8(avr_addr + UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */ ++ out_8(avr_addr + UART_DLL, quot & 0xff); /* LS of divisor */ ++ out_8(avr_addr + UART_DLM, quot >> 8); /* MS of divisor */ ++ out_8(avr_addr + UART_LCR, cval); /* reset DLAB */ ++ out_8(avr_addr + UART_FCR, UART_FCR_ENABLE_FIFO); /* enable FIFO */ ++} ++ ++void avr_uart_send(const char c) ++{ ++ if (!avr_addr || !avr_clock) ++ return; ++ ++ out_8(avr_addr + UART_TX, c); ++ out_8(avr_addr + UART_TX, c); ++ out_8(avr_addr + UART_TX, c); ++ out_8(avr_addr + UART_TX, c); ++} ++ ++static void __init ls_uart_init(void) ++{ ++ local_irq_disable(); ++ ++#ifndef CONFIG_SERIAL_8250 ++ out_8(avr_addr + UART_FCR, UART_FCR_ENABLE_FIFO); /* enable FIFO */ ++ out_8(avr_addr + UART_FCR, UART_FCR_ENABLE_FIFO | ++ UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); /* clear FIFOs */ ++ out_8(avr_addr + UART_FCR, 0); ++ out_8(avr_addr + UART_IER, 0); ++ ++ /* Clear up interrupts */ ++ (void) in_8(avr_addr + UART_LSR); ++ (void) in_8(avr_addr + UART_RX); ++ (void) in_8(avr_addr + UART_IIR); ++ (void) in_8(avr_addr + UART_MSR); ++#endif ++ avr_uart_configure(); ++ ++ local_irq_enable(); ++} ++ ++static int __init ls_uarts_init(void) ++{ ++ struct device_node *avr; ++ phys_addr_t phys_addr; ++ int len; ++ ++ avr = of_find_node_by_path("/soc10x/serial@80004500"); ++ if (!avr) ++ return -EINVAL; ++ ++ avr_clock = *(u32*)get_property(avr, "clock-frequency", &len); ++ phys_addr = ((u32*)get_property(avr, "reg", &len))[0]; ++ ++ if (!avr_clock || !phys_addr) ++ return -EINVAL; ++ ++ avr_addr = ioremap(phys_addr, 32); ++ if (!avr_addr) ++ return -EFAULT; ++ ++ ls_uart_init(); ++ ++ INIT_WORK(&wd_work, wd_stop, NULL); ++ schedule_work(&wd_work); ++ ++ return 0; ++} ++ ++late_initcall(ls_uarts_init); +diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c +index f1c7575..25cd8de 100644 +--- a/drivers/net/r8169.c ++++ b/drivers/net/r8169.c +@@ -1396,41 +1396,6 @@ static void rtl8169_netpoll(struct net_d + } + #endif + +-static void __rtl8169_set_mac_addr(struct net_device *dev, void __iomem *ioaddr) +-{ +- unsigned int i, j; +- +- RTL_W8(Cfg9346, Cfg9346_Unlock); +- for (i = 0; i < 2; i++) { +- __le32 l = 0; +- +- for (j = 0; j < 4; j++) { +- l <<= 8; +- l |= dev->dev_addr[4*i + j]; +- } +- RTL_W32(MAC0 + 4*i, cpu_to_be32(l)); +- } +- RTL_W8(Cfg9346, Cfg9346_Lock); +-} +- +-static int rtl8169_set_mac_addr(struct net_device *dev, void *p) +-{ +- struct rtl8169_private *tp = netdev_priv(dev); +- struct sockaddr *addr = p; +- +- if (!is_valid_ether_addr(addr->sa_data)) +- return -EINVAL; +- +- memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); +- +- if (netif_running(dev)) { +- spin_lock_irq(&tp->lock); +- __rtl8169_set_mac_addr(dev, tp->mmio_addr); +- spin_unlock_irq(&tp->lock); +- } +- return 0; +-} +- + static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, + void __iomem *ioaddr) + { +@@ -1680,7 +1645,6 @@ rtl8169_init_one(struct pci_dev *pdev, c + dev->stop = rtl8169_close; + dev->tx_timeout = rtl8169_tx_timeout; + dev->set_multicast_list = rtl8169_set_rx_mode; +- dev->set_mac_address = rtl8169_set_mac_addr; + dev->watchdog_timeo = RTL8169_TX_TIMEOUT; + dev->irq = pdev->irq; + dev->base_addr = (unsigned long) ioaddr; +@@ -1928,8 +1892,6 @@ rtl8169_hw_start(struct net_device *dev) + /* Enable all known interrupts by setting the interrupt mask. */ + RTL_W16(IntrMask, rtl8169_intr_mask); + +- __rtl8169_set_mac_addr(dev, ioaddr); +- + netif_start_queue(dev); + } + diff --git a/packages/u-boot/u-boot-1.2.0/qnap.diff b/packages/u-boot/u-boot-1.2.0/qnap.diff new file mode 100644 index 0000000000..b9ac34e6a8 --- /dev/null +++ b/packages/u-boot/u-boot-1.2.0/qnap.diff @@ -0,0 +1,1089 @@ +--- u-boot-1.2.0.vanilla/board/qnap/config.mk 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.2.0/board/qnap/config.mk 2007-02-26 01:55:37.000000000 +0100 +@@ -0,0 +1,35 @@ ++# ++# (C) Copyright 2000, 2001 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++# Valid values for TEXT_BASE are: ++# ++# Standard configuration ++# 0xFFF00000 boot from flash ++# ++# Standard configuration ++# 0xFFF60000 chain boot from flash ++# ++ ++ ++TEXT_BASE = 0xFFF60000 ++ ++PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) +--- u-boot-1.2.0.vanilla/board/qnap/ide.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.2.0/board/qnap/ide.c 2007-02-26 01:55:37.000000000 +0100 +@@ -0,0 +1,67 @@ ++/* ++ * (C) Copyright 2000 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++ #include ++ ++#ifdef CFG_CMD_IDE ++#include ++#include ++#include ++ ++extern ulong ide_bus_offset[CFG_IDE_MAXBUS]; ++extern struct pci_controller hose; ++ ++int ide_preinit (void) ++{ ++ int status; ++ pci_dev_t devbusfn; ++ int l; ++ ++ status = 1; ++ for (l = 0; l < CFG_IDE_MAXBUS; l++) { ++ ide_bus_offset[l] = -ATA_STATUS; ++ } ++ devbusfn = pci_find_device (0x1095, 0x3512, 0); ++ ++ if (devbusfn != -1) { ++ ++ status = 0; ++ ++ pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, ++ (u32 *) &ide_bus_offset[0]); ++ ide_bus_offset[0] &= 0xfffffffe; ++ ide_bus_offset[0] = pci_hose_bus_to_phys(&hose, ++ ide_bus_offset[0] & 0xfffffffe, ++ PCI_REGION_IO); ++ ++ pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2, ++ (u32 *) &ide_bus_offset[1]); ++ ide_bus_offset[1] &= 0xfffffffe; ++ ide_bus_offset[1] = pci_hose_bus_to_phys(&hose, ++ ide_bus_offset[1] & 0xfffffffe, ++ PCI_REGION_IO); ++ } ++ return (status); ++} ++ ++#endif /* of CONFIG_CMDS_IDE */ +--- u-boot-1.2.0.vanilla/board/qnap/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.2.0/board/qnap/Makefile 2007-02-26 01:55:37.000000000 +0100 +@@ -0,0 +1,40 @@ ++# ++# (C) Copyright 2000 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = lib$(BOARD).a ++ ++OBJS = $(BOARD).o ide.o ++ ++$(LIB): .depend $(OBJS) ++ $(AR) crv $@ $(OBJS) ++ ++######################################################################### ++ ++.depend: Makefile $(OBJS:.o=.c) ++ $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ ++ ++sinclude .depend ++ ++######################################################################### +--- u-boot-1.2.0.vanilla/board/qnap/qnap.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.2.0/board/qnap/qnap.c 2007-02-26 01:55:37.000000000 +0100 +@@ -0,0 +1,126 @@ ++/* ++ * Copyright (C) 2006 Andrew Luyten ++ * ++ * Copyright (C) 2000 ++ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++ ++int checkboard (void) ++{ ++ ulong busfreq = get_bus_freq(0); ++ char buf[32]; ++ ++ printf("Board: QNAP TS-101/TS-201 local bus at %s MHz\n", strmhz(buf, busfreq)); ++ return 0; ++} ++ ++ ++long int initdram (int board_type) ++{ ++ long size; ++ long new_bank0_end; ++ long mear1; ++ long emear1; ++ ++ size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); ++ ++ new_bank0_end = size - 1; ++ mear1 = mpc824x_mpc107_getreg(MEAR1); ++ emear1 = mpc824x_mpc107_getreg(EMEAR1); ++ mear1 = (mear1 & 0xFFFFFF00) | ++ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); ++ emear1 = (emear1 & 0xFFFFFF00) | ++ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); ++ mpc824x_mpc107_setreg(MEAR1, mear1); ++ mpc824x_mpc107_setreg(EMEAR1, emear1); ++ ++ return (size); ++} ++ ++/* ++ * Initialize PCI Devices, report devices found. ++ */ ++#ifndef CONFIG_PCI_PNP ++ ++static struct pci_config_table pci_qnap_config_table[] = { ++ /* vendor, device, class */ ++ /* bus, dev, func */ ++ ++ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, ++ PCI_ANY_ID, 0x0f, 0, /* RTL8110SC or Intel 82540EM */ ++ /* Gigabit ethernet controller */ ++ pci_cfgfunc_config_device, { PCI_ETH_IOADDR, ++ PCI_ETH_MEMADDR, ++ PCI_COMMAND_IO | ++ PCI_COMMAND_MEMORY | ++ PCI_COMMAND_MASTER }}, ++ ++ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, ++ PCI_ANY_ID, 0x0d, 0, /* SII3512 */ ++ /* SATA controller */ ++ pci_cfgfunc_config_device, { PCI_IDE_IOADDR, ++ PCI_IDE_MEMADDR, ++ PCI_COMMAND_IO | ++ PCI_COMMAND_MEMORY | ++ PCI_COMMAND_MASTER }}, ++ ++ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, ++ PCI_ANY_ID, 0x0e, 0, /* D720101 USB controller, 1st USB 1.1 */ ++ pci_cfgfunc_config_device, { PCI_USB0_IOADDR, ++ PCI_USB0_MEMADDR, ++ PCI_COMMAND_MEMORY | ++ PCI_COMMAND_MASTER }}, ++ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, ++ PCI_ANY_ID, 0x0e, 1, /* D720101 USB controller, 2nd USB 1.1 */ ++ pci_cfgfunc_config_device, { PCI_USB1_IOADDR, ++ PCI_USB1_MEMADDR, ++ PCI_COMMAND_MEMORY | ++ PCI_COMMAND_MASTER }}, ++ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, ++ PCI_ANY_ID, 0x0e, 2, /* D720101 USB controller, USB 2.0 */ ++ pci_cfgfunc_config_device, { PCI_USB2_IOADDR, ++ PCI_USB2_MEMADDR, ++ PCI_COMMAND_MEMORY | ++ PCI_COMMAND_MASTER }}, ++ { } ++}; ++#endif ++ ++struct pci_controller hose = { ++#ifndef CONFIG_PCI_PNP ++ config_table: pci_qnap_config_table, ++#endif ++}; ++ ++void pci_init_board(void) ++{ ++ pci_mpc824x_init(&hose); ++ ++ /* Reset USB 1.1 !/ ++ out_le32(PCI_USB0_MEMADDR+8, 1); ++ out_le32(PCI_USB1_MEMADDR+8, 1); ++ */ ++} +--- u-boot-1.2.0.vanilla/board/qnap/README 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.2.0/board/qnap/README 2007-02-26 01:55:37.000000000 +0100 +@@ -0,0 +1,10 @@ ++*This port of U-Boot will run on a QNAP TS-101/TS-201 NAS* ++Andrew Luyten (u-boot@luyten.org.uk) ++ ++Adapted from a Linkstation port by Mihai Georgian ++http://http://www.linuxnotincluded.org.uk/ ++ ++Adapted from Motorola Sandpoint 3 development system equipped with ++a Unity X4 PPMC card (MPC8240 CPU) only. It is a snapshot of work ++in progress and far from being completed. ++Thomas Koeller +--- u-boot-1.2.0.vanilla/board/qnap/u-boot.lds 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.2.0/board/qnap/u-boot.lds 2007-02-26 01:55:37.000000000 +0100 +@@ -0,0 +1,136 @@ ++/* ++ * (C) Copyright 2001 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_ARCH(powerpc) ++SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); ++/* Do we need any of these for elf? ++ __DYNAMIC = 0; */ ++SECTIONS ++{ ++ /* Read-only sections, merged into text segment: */ ++ . = + SIZEOF_HEADERS; ++ .interp : { *(.interp) } ++ .hash : { *(.hash) } ++ .dynsym : { *(.dynsym) } ++ .dynstr : { *(.dynstr) } ++ .rel.text : { *(.rel.text) } ++ .rela.text : { *(.rela.text) } ++ .rel.data : { *(.rel.data) } ++ .rela.data : { *(.rela.data) } ++ .rel.rodata : { *(.rel.rodata) } ++ .rela.rodata : { *(.rela.rodata) } ++ .rel.got : { *(.rel.got) } ++ .rela.got : { *(.rela.got) } ++ .rel.ctors : { *(.rel.ctors) } ++ .rela.ctors : { *(.rela.ctors) } ++ .rel.dtors : { *(.rel.dtors) } ++ .rela.dtors : { *(.rela.dtors) } ++ .rel.bss : { *(.rel.bss) } ++ .rela.bss : { *(.rela.bss) } ++ .rel.plt : { *(.rel.plt) } ++ .rela.plt : { *(.rela.plt) } ++ .init : { *(.init) } ++ .plt : { *(.plt) } ++ .text : ++ { ++ cpu/mpc824x/start.o (.text) ++ lib_ppc/board.o (.text) ++ lib_ppc/ppcstring.o (.text) ++ lib_generic/vsprintf.o (.text) ++ lib_generic/crc32.o (.text) ++ lib_generic/zlib.o (.text) ++ ++ . = DEFINED(env_offset) ? env_offset : .; ++ common/environment.o (.text) ++ ++ *(.text) ++ ++ *(.fixup) ++ *(.got1) ++ . = ALIGN(16); ++ *(.rodata) ++ *(.rodata1) ++ *(.rodata.str1.4) ++ *(.eh_frame) ++ } ++ .fini : { *(.fini) } =0 ++ .ctors : { *(.ctors) } ++ .dtors : { *(.dtors) } ++ ++ /* Read-write section, merged into data segment: */ ++ . = (. + 0x0FFF) & 0xFFFFF000; ++ _erotext = .; ++ PROVIDE (erotext = .); ++ .reloc : ++ { ++ *(.got) ++ _GOT2_TABLE_ = .; ++ *(.got2) ++ _FIXUP_TABLE_ = .; ++ *(.fixup) ++ } ++ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; ++ __fixup_entries = (. - _FIXUP_TABLE_) >> 2; ++ ++ .data : ++ { ++ *(.data) ++ *(.data1) ++ *(.sdata) ++ *(.sdata2) ++ *(.dynamic) ++ CONSTRUCTORS ++ } ++ _edata = .; ++ PROVIDE (edata = .); ++ ++ . = .; ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ ++ . = .; ++ __start___ex_table = .; ++ __ex_table : { *(__ex_table) } ++ __stop___ex_table = .; ++ ++ . = ALIGN(4096); ++ __init_begin = .; ++ .text.init : { *(.text.init) } ++ .data.init : { *(.data.init) } ++ . = ALIGN(4096); ++ __init_end = .; ++ ++ __bss_start = .; ++ .bss : ++ { ++ *(.sbss) *(.scommon) ++ *(.dynbss) ++ *(.bss) ++ *(COMMON) ++ } ++ ++ _end = . ; ++ PROVIDE (end = .); ++} +--- u-boot-1.2.0.vanilla/cpu/mpc824x/cpu.c 2007-01-07 00:13:11.000000000 +0100 ++++ u-boot-1.2.0/cpu/mpc824x/cpu.c 2007-02-26 01:55:37.000000000 +0100 +@@ -44,7 +44,11 @@ + break; + + case CPU_TYPE_8245: ++#ifdef CONFIG_MPC8241 ++ puts ("MPC8241"); /* impossible to distinguish using chip registers */ ++#else + puts ("MPC8245"); ++#endif + break; + + default: +--- u-boot-1.2.0.vanilla/drivers/rtl8169.c 2007-01-07 00:13:11.000000000 +0100 ++++ u-boot-1.2.0/drivers/rtl8169.c 2007-02-26 01:55:37.000000000 +0100 +@@ -48,7 +48,10 @@ + * + * Indent Options: indent -kr -i8 + ***************************************************************************/ +- ++/* ++ * 26 August 2006 Mihai Georgian ++ * Modified to use le32_to_cpu and cpu_to_le32 properly ++ */ + #include + #include + #include +@@ -68,6 +71,7 @@ + static u32 ioaddr; + + /* Condensed operations for readability. */ ++#define virt_to_bus(addr) cpu_to_le32(addr) + #define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr)) + #define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr)) + +@@ -247,8 +251,15 @@ + u8 version; /* depend on RTL8169 docs */ + u32 RxConfigMask; /* should clear the bits supported by this chip */ + } rtl_chip_info[] = { +- {"RTL-8169", 0x00, 0xff7e1880,}, +- {"RTL-8169", 0x04, 0xff7e1880,}, ++ {"RTL8169", 0x00, 0xff7e1880,}, ++ {"RTL8169s/8110s", 0x02, 0xff7e1880,}, ++ {"RTL8169s/8110s", 0x04, 0xff7e1880,}, ++ {"RTL8169sb/8110sb", 0x10, 0xff7e1880,}, ++ {"RTL8169sc/8110sc", 0x18, 0xff7e1880,}, ++ {"RTL8168b/8111sb", 0x30, 0xff7e1880,}, ++ {"RTL8168b/8111sb", 0x38, 0xff7e1880,}, ++ {"RTL8101e", 0x34, 0xff7e1880,}, ++ {"RTL8100e", 0x32, 0xff7e1880,}, + }; + + enum _DescStatusBit { +@@ -315,6 +326,7 @@ + + static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_REALTEK, 0x8169}, ++ {PCI_VENDOR_ID_REALTEK, 0x8167}, + {} + }; + +@@ -383,13 +395,15 @@ + for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ + if (tmp == rtl_chip_info[i].version) { + tpc->chipset = i; ++ printf ("%s... ", rtl_chip_info[i].name); + goto match; + } + } + + /* if unknown chip, assume array element #0, original RTL-8169 in this case */ + printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name); +- printf("PCI device: TxConfig = 0x%hX\n", (unsigned long) RTL_R32(TxConfig)); ++ printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig)); ++ + tpc->chipset = 0; + + match: +@@ -413,23 +427,23 @@ + ioaddr = dev->iobase; + + cur_rx = tpc->cur_rx; +- if ((tpc->RxDescArray[cur_rx].status & OWNbit) == 0) { +- if (!(tpc->RxDescArray[cur_rx].status & RxRES)) { ++ if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { ++ if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { + unsigned char rxdata[RX_BUF_LEN]; +- length = (int) (tpc->RxDescArray[cur_rx]. +- status & 0x00001FFF) - 4; ++ length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. ++ status) & 0x00001FFF) - 4; + + memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); + NetReceive(rxdata, length); + + if (cur_rx == NUM_RX_DESC - 1) + tpc->RxDescArray[cur_rx].status = +- (OWNbit | EORbit) + RX_BUF_SIZE; ++ cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); + else + tpc->RxDescArray[cur_rx].status = +- OWNbit + RX_BUF_SIZE; ++ cpu_to_le32(OWNbit + RX_BUF_SIZE); + tpc->RxDescArray[cur_rx].buf_addr = +- virt_to_bus(tpc->RxBufferRing[cur_rx]); ++ cpu_to_le32((u32)tpc->RxBufferRing[cur_rx]); + } else { + puts("Error Rx"); + } +@@ -454,6 +468,7 @@ + u8 *ptxb; + int entry = tpc->cur_tx % NUM_TX_DESC; + u32 len = length; ++ int ret; + + #ifdef DEBUG_RTL8169_TX + int stime = currticks(); +@@ -465,39 +480,46 @@ + + /* point to the current txb incase multiple tx_rings are used */ + ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; ++#ifdef DEBUG_RTL8169_TX ++ printf("ptxb: %08X, length: %d\n", ptxb, (int)length); ++#endif + memcpy(ptxb, (char *)packet, (int)length); + + while (len < ETH_ZLEN) + ptxb[len++] = '\0'; + +- tpc->TxDescArray[entry].buf_addr = virt_to_bus(ptxb); ++ tpc->TxDescArray[entry].buf_addr = cpu_to_le32((u32)ptxb); + if (entry != (NUM_TX_DESC - 1)) { + tpc->TxDescArray[entry].status = +- (OWNbit | FSbit | LSbit) | ((len > ETH_ZLEN) ? +- len : ETH_ZLEN); ++ cpu_to_le32((OWNbit | FSbit | LSbit) | ++ ((len > ETH_ZLEN) ? len : ETH_ZLEN)); + } else { + tpc->TxDescArray[entry].status = +- (OWNbit | EORbit | FSbit | LSbit) | +- ((len > ETH_ZLEN) ? length : ETH_ZLEN); ++ cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | ++ ((len > ETH_ZLEN) ? len : ETH_ZLEN)); + } + RTL_W8(TxPoll, 0x40); /* set polling bit */ + + tpc->cur_tx++; + to = currticks() + TX_TIMEOUT; +- while ((tpc->TxDescArray[entry].status & OWNbit) && (currticks() < to)); /* wait */ ++ while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) ++ && (currticks() < to)); /* wait */ + + if (currticks() >= to) { + #ifdef DEBUG_RTL8169_TX + puts ("tx timeout/error\n"); + printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); + #endif +- return 0; ++ ret = 0; + } else { + #ifdef DEBUG_RTL8169_TX + puts("tx done\n"); + #endif +- return length; ++ ret = length; + } ++ /* Delay to make net console (nc) work properly */ ++ udelay(20); ++ return ret; + } + + static void rtl8169_set_rx_mode(struct eth_device *dev) +@@ -564,8 +586,8 @@ + + tpc->cur_rx = 0; + +- RTL_W32(TxDescStartAddr, virt_to_le32desc(tpc->TxDescArray)); +- RTL_W32(RxDescStartAddr, virt_to_le32desc(tpc->RxDescArray)); ++ RTL_W32(TxDescStartAddr, virt_to_le32desc((u32)tpc->TxDescArray)); ++ RTL_W32(RxDescStartAddr, virt_to_le32desc((u32)tpc->RxDescArray)); + RTL_W8(Cfg9346, Cfg9346_Lock); + udelay(10); + +@@ -603,13 +625,14 @@ + for (i = 0; i < NUM_RX_DESC; i++) { + if (i == (NUM_RX_DESC - 1)) + tpc->RxDescArray[i].status = +- (OWNbit | EORbit) + RX_BUF_SIZE; ++ cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); + else +- tpc->RxDescArray[i].status = OWNbit + RX_BUF_SIZE; ++ tpc->RxDescArray[i].status = ++ cpu_to_le32(OWNbit + RX_BUF_SIZE); + + tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; + tpc->RxDescArray[i].buf_addr = +- virt_to_bus(tpc->RxBufferRing[i]); ++ cpu_to_le32((u32)tpc->RxBufferRing[i]); + } + + #ifdef DEBUG_RTL8169 +@@ -620,7 +643,7 @@ + /************************************************************************** + RESET - Finish setting up the ethernet interface + ***************************************************************************/ +-static void rtl_reset(struct eth_device *dev, bd_t *bis) ++static int rtl_reset(struct eth_device *dev, bd_t *bis) + { + int i; + u8 diff; +@@ -635,21 +658,27 @@ + if (tpc->TxDescArrays == 0) + puts("Allot Error"); + /* Tx Desscriptor needs 256 bytes alignment; */ +- TxPhyAddr = virt_to_bus(tpc->TxDescArrays); ++ TxPhyAddr = (u32)tpc->TxDescArrays; + diff = 256 - (TxPhyAddr - ((TxPhyAddr >> 8) << 8)); + TxPhyAddr += diff; + tpc->TxDescArray = (struct TxDesc *) (tpc->TxDescArrays + diff); ++#ifdef DEBUG_RTL8169 ++ printf("tpc->TxDescArray: %08X\n", tpc->TxDescArray); ++#endif + + tpc->RxDescArrays = rx_ring; + /* Rx Desscriptor needs 256 bytes alignment; */ +- RxPhyAddr = virt_to_bus(tpc->RxDescArrays); ++ RxPhyAddr = (u32)tpc->RxDescArrays; + diff = 256 - (RxPhyAddr - ((RxPhyAddr >> 8) << 8)); + RxPhyAddr += diff; + tpc->RxDescArray = (struct RxDesc *) (tpc->RxDescArrays + diff); ++#ifdef DEBUG_RTL8169 ++ printf("tpc->RxDescArray: %08X\n", tpc->RxDescArray); ++#endif + + if (tpc->TxDescArrays == NULL || tpc->RxDescArrays == NULL) { + puts("Allocate RxDescArray or TxDescArray failed\n"); +- return; ++ return 0; + } + + rtl8169_init_ring(dev); +@@ -669,6 +698,7 @@ + #ifdef DEBUG_RTL8169 + printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); + #endif ++ return 1; + } + + /************************************************************************** +@@ -733,7 +763,7 @@ + + /* Get MAC address. FIXME: read EEPROM */ + for (i = 0; i < MAC_ADDR_LEN; i++) +- dev->enetaddr[i] = RTL_R8(MAC0 + i); ++ bis->bi_enetaddr[i] = dev->enetaddr[i] = RTL_R8(MAC0 + i); + + #ifdef DEBUG_RTL8169 + printf("MAC Address"); +@@ -814,17 +844,14 @@ + if (option & _1000bpsF) { + #ifdef DEBUG_RTL8169 + printf("%s: 1000Mbps Full-duplex operation.\n", +- dev->name); ++ dev->name); + #endif + } else { + #ifdef DEBUG_RTL8169 +- printf +- ("%s: %sMbps %s-duplex operation.\n", +- dev->name, +- (option & _100bps) ? "100" : +- "10", +- (option & FullDup) ? "Full" : +- "Half"); ++ printf("%s: %sMbps %s-duplex operation.\n", ++ dev->name, ++ (option & _100bps) ? "100" : "10", ++ (option & FullDup) ? "Full" : "Half"); + #endif + } + break; +@@ -886,3 +913,5 @@ + } + + #endif ++ ++/* vim: set ts=4: */ +--- u-boot-1.2.0.vanilla/include/configs/qnap.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.2.0/include/configs/qnap.h 2007-02-26 01:55:37.000000000 +0100 +@@ -0,0 +1,354 @@ ++/* ++ * Copyright (C) 2006 Andrew Luyten ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* ------------------------------------------------------------------------- */ ++ ++/* ++ * board/config.h - configuration options, board specific ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++/* ++ * High Level Configuration Options ++ * (easy to change) ++ */ ++ ++#define CONFIG_MPC824X 1 ++#define CONFIG_MPC8245 1 ++#define CONFIG_MPC8241 1 ++ ++#define CONFIG_IDENT_STRING " OpenTS(c)" ++#define CONFIG_TIMESTAMP ++#define CFG_HUSH_PARSER 1 ++#define CFG_PROMPT_HUSH_PS2 "turbostation> " ++#define CONFIG_BOOTDELAY 3 ++ ++ ++/*---------------------------------------------------------------------- ++ * Define supported commands ++ */ ++ ++#define CONFIG_COMMANDS ( \ ++ CONFIG_CMD_DFL | \ ++ CFG_CMD_ELF | \ ++ CFG_CMD_I2C | \ ++ CFG_CMD_PING | \ ++ CFG_CMD_DHCP | \ ++ CFG_CMD_IDE | \ ++ CFG_CMD_EXT2 | \ ++ CFG_CMD_DATE | \ ++ CFG_CMD_PCI ) ++ ++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ ++#include ++ ++ ++/*----------------------------------------------------------------------- ++ * Miscellaneous configurable options ++ */ ++ ++#define CFG_LONGHELP 1 /* undef to save memory */ ++#define CFG_PROMPT "=> " /* Monitor Command Prompt*/ ++#define CFG_CBSIZE 256 /* Console I/O Buffer Size*/ ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size*/ ++#define CFG_MAXARGS 16 /* max number of command args*/ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size*/ ++#define CFG_LOAD_ADDR 0x00100000 /* default load address */ ++#define CFG_HZ 1000 /* decrementer freq:1 ms ticks*/ ++ ++ ++/*----------------------------------------------------------------------- ++ * PCI ++ * ++ */ ++ ++#define CONFIG_PCI ++#undef CONFIG_PCI_PNP ++ ++#define PCI_ETH_IOADDR 0xbffe00 ++#define PCI_ETH_MEMADDR 0xbfffce00 ++ ++#define PCI_IDE_IOADDR 0xbfffd0 ++#define PCI_IDE_MEMADDR 0xbffffe00 ++ ++#define PCI_USB0_IOADDR 0 ++#define PCI_USB0_MEMADDR 0xbfffe000 ++#define PCI_USB1_IOADDR 0 ++#define PCI_USB1_MEMADDR 0xbfffd000 ++#define PCI_USB2_IOADDR 0 ++#define PCI_USB2_MEMADDR 0xbfffcf00 ++ ++ ++/*----------------------------------------------------------------------- ++ * Start addresses for the final memory configuration ++ * (Set up by the startup code) ++ */ ++ ++#define CFG_SDRAM_BASE 0x00000000 ++#define CFG_MONITOR_BASE TEXT_BASE ++#undef CFG_RAMBOOT ++ ++#define CFG_PCI_MEM_ADDR 0xB0000000 ++#define CFG_EUMB_ADDR 0xFC000000 ++#define CFG_FLASH_BASE 0xFF000000 ++ ++#define CFG_RESET_ADDRESS 0xFFF00100 ++ ++#define CFG_MONITOR_LEN (256 << 10) ++#define CFG_MALLOC_LEN (512 << 10) ++ ++#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ ++#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ ++#define CFG_MAX_RAM_SIZE 0x10000000 /* up to 256M of SDRAM */ ++ ++ ++/*----------------------------------------------------------------------- ++ * Definitions for initial stack pointer and data area ++ */ ++ ++#define CFG_INIT_RAM_ADDR 0x40000000 ++#define CFG_INIT_RAM_END 0x1000 ++#define CFG_GBL_DATA_SIZE 128 ++#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) ++ ++ ++/*----------------------------------------------------------------------- ++ * FLASH organization ++ */ ++ ++#define CFG_FLASH_CFI 1 ++#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ ++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ ++#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip*/ ++#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ ++#define CFG_FLASH_USE_BUFFER_WRITE /* faster writes */ ++ ++#define CFG_ENV_IS_IN_FLASH 1 ++#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00FA0000) ++#define CFG_ENV_SECT_SIZE 0x00020000 /* Total Size of Environment Sector*/ ++ ++ ++/*----------------------------------------------------------------------- ++ * Gigabit Ethernet ++ */ ++ ++#define CONFIG_NET_MULTI ++#define CONFIG_RTL8169 ++ ++ ++/*----------------------------------------------------------------------- ++ * Filesystems ++ */ ++ ++#define CONFIG_MAC_PARTITION ++#define CONFIG_DOS_PARTITION ++//#define CONFIG_ISO_PARTITION ++ ++ ++/*----------------------------------------------------------------------- ++ * IDE/ATA ++ */ ++ ++#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ ++#undef CONFIG_IDE_LED /* no led for ide supported */ ++#undef CONFIG_IDE_RESET /* no reset for ide supported */ ++#undef CONFIG_ATAPI /* no ATAPI support */ ++ ++#define CONFIG_IDE_PREINIT /* To set up MMIO adresses */ ++#define CONFIG_LBA48 /* Large disk support */ ++ ++#define CFG_IDE_MAXBUS 2 /* Two channels x 1 device each */ ++#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) ++ ++#define CFG_ATA_BASE_ADDR 0x0000 /* Set up in board specific code */ ++#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ ++#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ ++#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ ++ ++ ++/*---------------------------------------------------------------------- ++ * On Chip Serial configuration ++ */ ++ ++#define CONFIG_CONS_INDEX 1 ++#define CONFIG_BAUDRATE 115200 ++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } ++ ++#define CFG_NS16550 ++#define CFG_NS16550_SERIAL ++ ++#define CFG_NS16550_REG_SIZE 1 ++#define CFG_NS16550_CLK get_bus_freq(0) ++ ++#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) /* Console port */ ++#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) /* PIC ? */ ++ ++ ++/*---------------------------------------------------------------------- ++ * i2c support configuration ++ */ ++ ++#define CONFIG_HARD_I2C 1 /* To enable I2C support */ ++#undef CONFIG_SOFT_I2C /* I2C bit-banged */ ++#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ ++#define CFG_I2C_SLAVE 0x7F ++ ++#define CONFIG_RTC_RS5C372A /* Real-time clock chip */ ++ ++ ++/*---------------------------------------------------------------------- ++ * Low Level Configuration Settings ++ * (address mappings, register initial values, etc.) ++ * You should know what you are doing if you make changes here. ++ */ ++ ++#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ ++ ++#define CFG_ROMNAL 7 /*rom/flash next access time */ ++#define CFG_ROMFAL 11 /*rom/flash access time */ ++ ++#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */ ++ ++/* the following are for SDRAM only*/ ++#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ ++#define CFG_REFREC 8 /* Refresh to activate interval */ ++#define CFG_RDLAT 4 /* data latency from read command */ ++#define CFG_PRETOACT 3 /* Precharge to activate interval */ ++#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ ++#define CFG_ACTORW 3 /* Activate to R/W */ ++#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ ++#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ ++ ++#define CFG_REGISTERD_TYPE_BUFFER 1 ++#define CFG_EXTROM 1 ++#define CFG_REGDIMM 0 ++ ++ ++/*---------------------------------------------------------------------- ++ * memory bank settings ++ * ++ * only bits 20-29 are actually used from these vales to set the ++ * start/end address the upper two bits will be 0, and the lower 20 ++ * bits will be set to 0x00000 for a start address, or 0xfffff for an ++ * end address ++ */ ++ ++#define CFG_BANK0_START 0x00000000 ++#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) ++#define CFG_BANK0_ENABLE 1 ++#define CFG_BANK1_START 0x3ff00000 ++#define CFG_BANK1_END 0x3fffffff ++#define CFG_BANK1_ENABLE 0 ++#define CFG_BANK2_START 0x3ff00000 ++#define CFG_BANK2_END 0x3fffffff ++#define CFG_BANK2_ENABLE 0 ++#define CFG_BANK3_START 0x3ff00000 ++#define CFG_BANK3_END 0x3fffffff ++#define CFG_BANK3_ENABLE 0 ++#define CFG_BANK4_START 0x00000000 ++#define CFG_BANK4_END 0x00000000 ++#define CFG_BANK4_ENABLE 0 ++#define CFG_BANK5_START 0x00000000 ++#define CFG_BANK5_END 0x00000000 ++#define CFG_BANK5_ENABLE 0 ++#define CFG_BANK6_START 0x00000000 ++#define CFG_BANK6_END 0x00000000 ++#define CFG_BANK6_ENABLE 0 ++#define CFG_BANK7_START 0x00000000 ++#define CFG_BANK7_END 0x00000000 ++#define CFG_BANK7_ENABLE 0 ++ ++ ++/* ++ * Memory bank enable bitmask, specifying which of the banks defined above ++ are actually present. MSB is for bank #7, LSB is for bank #0. ++ */ ++#define CFG_BANK_ENABLE 0x01 ++ ++#define CFG_ODCR 0xff /* configures line driver impedances, */ ++ /* see 8240 book for bit definitions */ ++#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ ++ /* currently accessed page in memory */ ++ /* see 8240 book for details */ ++#define CFG_DBUS_SIZE2 1 ++#define CFG_BANK0_ROW 2 ++ ++ ++/*---------------------------------------------------------------------- ++ * Initial BAT mappings ++ */ ++ ++/* SDRAM 0 - 256MB */ ++#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) ++#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) ++ ++/* stack in DCACHE @ 1GB (no backing mem) */ ++#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) ++#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) ++ ++/* PCI memory */ ++#define CFG_IBAT2L (CFG_PCI_MEM_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT) ++#define CFG_IBAT2U (CFG_PCI_MEM_ADDR | BATU_BL_256M | BATU_VS | BATU_VP) ++ ++/* Flash, config addrs, etc */ ++#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) ++#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) ++ ++#define CFG_DBAT0L CFG_IBAT0L ++#define CFG_DBAT0U CFG_IBAT0U ++#define CFG_DBAT1L CFG_IBAT1L ++#define CFG_DBAT1U CFG_IBAT1U ++#define CFG_DBAT2L CFG_IBAT2L ++#define CFG_DBAT2U CFG_IBAT2U ++#define CFG_DBAT3L CFG_IBAT3L ++#define CFG_DBAT3U CFG_IBAT3U ++ ++/* ++ * For booting Linux, the board info and command line data ++ * have to be in the first 8 MB of memory, since this is ++ * the maximum mapped by the Linux kernel during initialization. ++ */ ++#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ ++ ++ ++/*----------------------------------------------------------------------- ++ * Cache Configuration ++ */ ++ ++#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ ++#endif ++ ++ ++/*----------------------------------------------------------------------- ++ * Internal Definitions ++ * ++ * Boot Flags ++ */ ++#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ ++#define BOOTFLAG_WARM 0x02 /* Software reboot */ ++ ++ ++#endif /* __CONFIG_H */ +--- u-boot-1.2.0.vanilla/Makefile 2007-01-07 00:13:11.000000000 +0100 ++++ u-boot-1.2.0/Makefile 2007-02-26 01:55:37.000000000 +0100 +@@ -1296,6 +1296,9 @@ + PN62_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc824x pn62 + ++qnap_config: unconfig ++ @$(MKCONFIG) $(@:_config=) ppc mpc824x qnap ++ + Sandpoint8240_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc824x sandpoint + diff --git a/packages/u-boot/u-boot-1.2.0/tools-Makefile.patch b/packages/u-boot/u-boot-1.2.0/tools-Makefile.patch new file mode 100644 index 0000000000..a44bc917d6 --- /dev/null +++ b/packages/u-boot/u-boot-1.2.0/tools-Makefile.patch @@ -0,0 +1,19 @@ +--- u-boot-1.1.2.orig/tools/Makefile 2004-09-28 14:39:46.000000000 -0700 ++++ u-boot-1.1.2/tools/Makefile 2006-11-08 11:07:18.000000000 -0800 +@@ -56,7 +56,7 @@ + HOSTOS := $(shell uname -s | tr A-Z a-z | \ + sed -e 's/\(cygwin\).*/cygwin/') + +-TOOLSUBDIRS = ++TOOLSUBDIRS = env + + # + # Mac OS X / Darwin's C preprocessor is Apple specific. It +@@ -176,6 +176,7 @@ + else + @for dir in $(TOOLSUBDIRS) ; do \ + $(MAKE) \ ++ CROSS_COMPILE=$(CROSS_COMPILE) \ + HOSTOS=$(HOSTOS) \ + HOSTARCH=$(HOSTARCH) \ + HOST_CFLAGS="$(HOST_CFLAGS)" \ diff --git a/packages/u-boot/u-boot-1.2.0/turbostation/.mtn2git_empty b/packages/u-boot/u-boot-1.2.0/turbostation/.mtn2git_empty new file mode 100644 index 0000000000..e69de29bb2 diff --git a/packages/u-boot/u-boot-1.2.0/turbostation/fw_env.config b/packages/u-boot/u-boot-1.2.0/turbostation/fw_env.config new file mode 100644 index 0000000000..2432bd866c --- /dev/null +++ b/packages/u-boot/u-boot-1.2.0/turbostation/fw_env.config @@ -0,0 +1,7 @@ +# Configuration file for fw_(printenv/saveenv) utility. +# Up to two entries are valid, in this case the redundand +# environment sector is assumed present. + +# MTD device name Device offset Env. size Flash sector size +/dev/mtd1 0x0000 0x4000 0x4000 +/dev/mtd2 0x0000 0x4000 0x4000 diff --git a/packages/u-boot/u-boot-1.2.0/u-boot-kurobox-fdt.patch b/packages/u-boot/u-boot-1.2.0/u-boot-kurobox-fdt.patch new file mode 100644 index 0000000000..182c3785c7 --- /dev/null +++ b/packages/u-boot/u-boot-1.2.0/u-boot-kurobox-fdt.patch @@ -0,0 +1,29 @@ +diff -ur u-boot-86xx-kuro_clean/include/configs/linkstation.h u-boot-86xx-kuro_flash/include/configs/linkstation.h +--- u-boot-86xx-kuro_clean/include/configs/linkstation.h 2006-11-06 22:05:38.000000000 +0100 ++++ u-boot-86xx-kuro_flash/include/configs/linkstation.h 2006-10-28 11:27:42.000000000 +0200 +@@ -101,6 +101,14 @@ + CFG_CMD_EXT2 ) + #define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL + ++#define CONFIG_OF_FLAT_TREE 1 ++ ++#ifdef CONFIG_OF_FLAT_TREE ++#define OF_CPU "PowerPC,603e" ++#define OF_SOC "soc10x@80000000" ++#define OF_STDOUT_PATH "/soc10x/serial@80004600" ++#endif ++ + /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ + #include + +@@ -151,8 +159,8 @@ + "ldaddr=800000\0" \ + "hdpart=0:1\0" \ + "hdfile=boot/vmlinux.UBoot\0" \ +- "hdload=echo Loading ${hdpart}:${hdfile};ext2load ide ${hdpart} ${ldaddr} ${hdfile}\0" \ +- "boothd=setenv bootargs root=/dev/hda1;bootm ${ldaddr}\0" \ ++ "hdload=echo Loading ${hdpart}:${hdfile};ext2load ide ${hdpart} ${ldaddr} ${hdfile};ext2load ide ${hdpart} 7f0000 boot/kuroboxHG.dtb\0" \ ++ "boothd=setenv bootargs " CONFIG_BOOTARGS ";bootm ${ldaddr} - 7f0000\0" \ + "hdboot=run hdload boothd\0" \ + "flboot=setenv bootargs root=/dev/hda1;bootm ffc00000\0" \ + "emboot=setenv bootargs root=/dev/ram0;bootm ffc00000\0" \ diff --git a/packages/u-boot/u-boot-1.2.0/u-boot-kurobox.patch b/packages/u-boot/u-boot-1.2.0/u-boot-kurobox.patch new file mode 100644 index 0000000000..79f7a8e48a --- /dev/null +++ b/packages/u-boot/u-boot-1.2.0/u-boot-kurobox.patch @@ -0,0 +1,5595 @@ +diff -urN u-boot-86xx/MAKEALL u-boot-86xx-kuro_clean/MAKEALL +--- u-boot-86xx/MAKEALL 2006-10-13 00:27:12.000000000 +0200 ++++ u-boot-86xx-kuro_clean/MAKEALL 2006-11-06 22:13:16.000000000 +0100 +@@ -106,9 +106,9 @@ + LIST_824x=" \ + A3000 barco BMW CPC45 \ + CU824 debris eXalion HIDDEN_DRAGON \ +- MOUSSE MUSENKI MVBLUE \ +- OXC PN62 Sandpoint8240 Sandpoint8245 \ +- sbc8240 SL8245 utx8245 \ ++ linkstation linkstationhg MOUSSE MUSENKI \ ++ MVBLUE OXC PN62 Sandpoint8240 \ ++ Sandpoint8245 sbc8240 SL8245 utx8245 \ + " + + ######################################################################### +diff -urN u-boot-86xx/Makefile u-boot-86xx-kuro_clean/Makefile +--- u-boot-86xx/Makefile 2006-10-13 00:27:12.000000000 +0200 ++++ u-boot-86xx-kuro_clean/Makefile 2006-11-06 22:15:20.000000000 +0100 +@@ -122,7 +122,7 @@ + CROSS_COMPILE = + else + ifeq ($(ARCH),ppc) +-CROSS_COMPILE = powerpc-linux- ++CROSS_COMPILE = ppc_6xx- + endif + ifeq ($(ARCH),arm) + CROSS_COMPILE = arm-linux- +@@ -237,6 +237,40 @@ + + all: $(ALL) + ++LSMODEL := $(shell head -n 1 include/config.h) ++ ++linkstation_HGLAN_RAM: include/config.h ++ @[ -n "$(findstring HGLAN_RAM, $(LSMODEL))" ] || \ ++ { echo "Bad configuration: $(LSMODEL)" ; \ ++ exit 1 ; \ ++ } ++ @make all ++ @mv u-boot.bin u-boot-hg.ram.bin ++ ++linkstation_HGLAN: include/config.h ++ @[ -n "$(findstring HGLAN_ROM, $(LSMODEL))" ] || \ ++ { echo "Bad configuration: $(LSMODEL)" ; \ ++ exit 1 ; \ ++ } ++ @make all ++ @mv u-boot.bin u-boot-hg.flash.bin ++ ++linkstation_HDLAN_RAM: include/config.h ++ @[ -n "$(findstring HDLAN_RAM, $(LSMODEL))" ] || \ ++ { echo "Bad configuration: $(LSMODEL)" ; \ ++ exit 1 ; \ ++ } ++ @make all ++ @mv u-boot.bin u-boot-hd.ram.bin ++ ++linkstation_HDLAN: include/config.h ++ @[ -n "$(findstring HDLAN_ROM, $(LSMODEL))" ] || \ ++ { echo "Bad configuration: $(LSMODEL)" ; \ ++ exit 1 ; \ ++ } ++ @make all ++ @mv u-boot.bin u-boot-hd.flash.bin ++ + $(obj)u-boot.hex: $(obj)u-boot + $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ + +@@ -317,6 +351,10 @@ + + ######################################################################### + else ++linkstation_HGLAN_RAM \ ++linkstation_HGLAN \ ++linkstation_HDLAN_RAM \ ++linkstation_HDLAN \ + all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \ + $(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \ + $(SUBDIRS) version gdbtools updater env depend \ +@@ -1262,6 +1300,38 @@ + kvme080_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc824x kvme080 etin + ++linkstation_HGLAN_RAM_config: mrproper ++ @>include/config.h ; \ ++ echo "/* HGLAN_RAM */" >>include/config.h ; \ ++ echo "#define CONFIG_HGLAN 1" >>include/config.h ; \ ++ echo "TEXT_BASE = 0x07F00000" >board/linkstation/config.tmp ; \ ++ ./mkconfig -a linkstation ppc mpc824x linkstation ; \ ++ echo "LinkStation HGLAN -- RAM BUILD ..." ++ ++linkstation_HGLAN_config: mrproper ++ @>include/config.h ; \ ++ echo "/* HGLAN_ROM */" >>include/config.h ; \ ++ echo "#define CONFIG_HGLAN 1" >>include/config.h ; \ ++ echo "TEXT_BASE = 0xFFF00000" >board/linkstation/config.tmp ; \ ++ ./mkconfig -a linkstation ppc mpc824x linkstation ; \ ++ echo "LinkStation HGLAN -- ROM BUILD ..." ++ ++linkstation_HDLAN_RAM_config: mrproper ++ @>include/config.h ; \ ++ echo "/* HDLAN_RAM */" >>include/config.h ; \ ++ echo "#define CONFIG_HLAN 1" >>include/config.h ; \ ++ echo "TEXT_BASE = 0x03F00000" >board/linkstation/config.tmp ; \ ++ ./mkconfig -a linkstation ppc mpc824x linkstation ; \ ++ echo "LinkStation HDLAN -- RAM BUILD ..." ++ ++linkstation_HDLAN_config: mrproper ++ @>include/config.h ; \ ++ echo "/* HDLAN_ROM */" >>include/config.h ; \ ++ echo "#define CONFIG_HLAN 1" >>include/config.h ; \ ++ echo "TEXT_BASE = 0xFFF00000" >board/linkstation/config.tmp ; \ ++ ./mkconfig -a linkstation ppc mpc824x linkstation ; \ ++ echo "LinkStation HDLAN -- ROM BUILD ..." ++ + MOUSSE_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc824x mousse + +diff -urN u-boot-86xx/board/linkstation/INSTALL u-boot-86xx-kuro_clean/board/linkstation/INSTALL +--- u-boot-86xx/board/linkstation/INSTALL 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-86xx-kuro_clean/board/linkstation/INSTALL 2006-11-06 22:05:38.000000000 +0100 +@@ -0,0 +1,631 @@ ++ ++ Installing U-Boot for LinkStation ++ ++ For U-Boot port version 2.1.0 ++ 16 September 2006 ++ ++ Copyright (c) 2006 Mihai Georgian ++ ++ Permission is granted to copy, distribute and/or modify this document under ++ the terms of the [1]GNU Free Documentation License, Version 1.2 or any later ++ version published by the Free Software Foundation; with no Invariant ++ Sections, no Front-Cover Texts, and no Back-Cover Texts. The full text of ++ the license can be obtained by clicking on the above link. ++ ++ No liability for the contents of this document can be accepted. The ++ information in this document is provided in good faith but no warranty can ++ be made for its accuracy and the author does not take any responsibility. ++ Use the concepts, examples and information at your own risk. There may be ++ errors and inaccuracies, that could be damaging to your system. ++ ++ Use of a term in this document should not be regarded as affecting the ++ validity of any trademark or service mark. Naming of particular products or ++ brands should not be seen as endorsements. ++ _________________________________________________________________ ++ ++ WARNING ++ ++ Flashing the LinkStation with unauthorised firmare voids your warranty. When ++ installing firmware on an embedded computer things can and, sometimes, do go ++ wrong. The power can go down in the middle of the flash operation or the ++ flash write can fail rendering your LinkStation unusable. Please read this ++ entire page carefully before attempting to install U-Boot. ++ ++ If you are not prepared to lose your LinkStation, do not attempt to install ++ U-Boot ++ ++ Introduction ++ ++ U-Boot for the LinkStation is distributed as a source patch against ++ u-boot-1.1.4. To compile it you will need either a cross toolchain installed ++ on your PC or native development tools installed on your LinkStation. These ++ instructions assume that you are running Linux on a X86 PC and that you are ++ using a cross toolchain. ++ ++ To allow testing of U-Boot on your LinkStation without burning it into ++ flash, a kernel module named uloader.o is provided. Uloader allows you to ++ use Linux to load a RAM build of U-Boot and start it. The RAM build of ++ U-Boot is very close to the ROM build. The only differences are the absence ++ of the basic initialisation code (which cannot run from RAM) and the link ++ address. It is strongly recommended that you test U-Boot on your LinkStation ++ using a RAM build before building the ROM version and attempting to burn it ++ into flash. Once you have the RAM build up and running you can use it to ++ install (burn) the ROM version. ++ ++ Supported Hardware ++ ++ The LinkStation port of U-Boot described in this document supports the ++ following PowerPC based models: ++ 1. LinkStation version 1 (model HD-HLAN-1) ++ 2. KuroBox standard ++ 3. LinkStation HG (model HD-HGLAN) ++ 4. KuroBox HG ++ ++ This version of U-Boot will certainly not work on the the LinkStation ++ version 2 (model HD-HLAN-2) as the LinkStation version 2 is based on a MIPS ++ processor. The MIPS processor is completely different from the PowerPC ++ processor and attempting to flash a LinkStation version 2 with PowerPC ++ firmware it is guaranteed to make it completely unusable. ++ ++ Get telnet Access ++ ++ Try to connect to your LinkStation using telnet. If you see the telnet ++ command prompt, read [2]CGI Exploit (PowerPC) original method of Hacking the ++ LinkStation about how to get telnet access. ++ ++ If the above method doesn't work for you, read [3]Turn your LinkStation into ++ a Kuro Box (PowerPC) for other methods to get telnet access. ++ ++ The above methods do not work for the LinkStation HG. For this model, the ++ only solution is to load a telnet-enabled version of the firmware. Read the ++ pages about [4]OpenLink and the [5]firmware flasher ++ ++ You can also try to flash [6]a modified version of the original firmware. ++ ++ Install the Serial Console ++ ++ Installing the serial console is not an absolute requirement and it will ++ void your warranty. U-Boot can be installed and controlled without it. ++ However, the serial console will give you the best control over both U-Boot ++ and Linux. ++ ++ Read [7]Add a Serial port to the PowerPC Linkstation to learn how to install ++ the serial console. ++ ++ Install netcat (nc) ++ ++ If you haven't installed the serial console you will need to install netcat ++ (nc). Netcat is a networking utility which reads and writes data across ++ network connections, using the TCP/IP protocol. It comes standard with most ++ Linux distributions. For more information, visit the netcat home page ++ [8]http://netcat.sourceforge.net or [9]http://www.vulnwatch.org/netcat for ++ the Windows version. ++ ++ Get the ELDK ++ ++ If you don't have a cross toolchain installed, download the DENX Embedded ++ Linux Development Kit (ELDK) from ++ [10]http://ftp.sunet.se/pub/Linux/distributions/eldk/3.1.1/ppc-linux-x86/iso ++ /ppc-2005-03-07.iso, install it and spend some time getting familiar with ++ it. ++ ++ Preparation ++ ++ Create the build directory and set the environment variable UBOOT_BUILD to ++ the path to it ++ # mkdir ++ # export UBOOT_BUILD= ++ # cd $UBOOT_BUILD ++ Download the tarball for u-boot-1.1.4 from ++ [11]ftp://ftp.denx.de/pub/u-boot/u-boot-1.1.4.tar.bz2 ++ Download the LinkStation patch, [12]u-boot-1.1.4-list-2.1.0.diff.gz ++ Download the uloader module for your LinkStation / KuroBox model. ++ * For the LinkStation 1 / KuroBox standard, download ++ [13]uloader-2.4.17.tar.gz ++ * For the LinkStation HG / KuroBox HG, download [14]uloader-2.4.20.tar.gz ++ ++ Untar u-boot-1.1.4 and apply the patch. ++ # tar xjf u-boot-1.1.4.tar.bz2 ++ # cd u-boot-1.1.4 ++ # gunzip ../u-boot-1.1.4-list-2.01.diff.gz | patch -p1 ++ ++ Untar the uloader archive for your LinkStation / KuroBox model. The archive ++ contains the source code, a binary module compiled for the original ++ LinkStation kernel and a simple bash script to load and start a RAM build of ++ U-Boot. ++ ++ The binary in uloader-2.4.17.tar.gz has been compiled against ++ 2.4.17_mvl21-sandpoint. Use only on the LinkStation 1 / KuroBox standard. ++ The binary in uloader-2.4.20.tar.gz has been compiled against ++ 2.4.20_mvl31-ppc_linkstation. Use only on the LinkStation HG / KuroBog HG. ++ If you have a different kernel version, you may need to recompile the module ++ for your kernel. Compiling the module requires a fully configured kernel ++ source tree. It is recommended to use the same gcc version as the one used ++ to compile the kernel. There is a small but important difference between the ++ two uloader source archives. The difference is the U-Boot load address. If ++ you compile uloader for the LinkStation 1 / KuroBox standard, use the ++ sources in uloader-2.4.17.tar.gz. If you compile for the LinkStation HG / ++ KuroBox HG, use the sources in uloader-2.4.20.tar.gz. In both cases you ++ need to modify the Makefile to match your development environment. ++ ++ LinkStation 1 / KuroBox standard ++ # cd .. ++ # tar xzf uloader-2.4.17.tar.gz ++ # cd u-boot-1.1.4 ++ ++ LinkStation HG / KuroBox HG ++ # cd .. ++ # tar xzf uloader-2.4.20.tar.gz ++ # cd u-boot-1.1.4 ++ ++ Source your ELDK environment ++ # . /config_6xx ++ ++ Configure ++ ++ Edit include/configs/linkstation.h and set the following variables for your ++ environment: ++ ++ CONFIG_IPADDR_LS - the IP address of your LinkStation while running ++ U-Boot (mandatory). The default address is ++ 192.168.11.150. ++ CONFIG_SERVERIP_LS - the IP address of the NFS/TFTP/DHCP/BOOTP server, ++ normally the address of your Linux PC (mandatory). ++ The default address is 192.168.11.149. ++ CONFIG_NCIP_LS - the address of the computer running netcat (nc), ++ normally the address of your Linux PC (optional). ++ If the define is missing, CONFIG_NCIP_LS will be ++ set to the same value as CONFIG_SERVERIP_LS ++ ++ RAM Build ++ ++ For LinkStation 1 / KuroBox standard run: ++ make linkstation_HDLAN_RAM_config ++ make linkstation_HDLAN_RAM ++ ++ The name of the resulting binary is u-boot-hd.ram.bin ++ ++ For LinkStation HG / KuroBox HG run: ++ make linkstation_HGLAN_RAM_config ++ make linkstation_HGLAN_RAM ++ ++ The name of the resulting binary is u-boot-hg.ram.bin ++ ++ Net Console ++ ++ The net console is the U-Boot driver which uses the UDP protocol with a ++ default port of 6666 to send the console output to and receive the console ++ input from a remote computer. You need to run netcat on the remote computer ++ to communicate with the U-Boot net console. The communication is ++ bidirectional. Netcat will display on your screen the console output ++ received from U-Boot and will send your keyboard input back to U-Boot. ++ ++ If U-Boot cannot contact the remote computer, it switches the console to the ++ serial port. To show that it changed the console, U-Boot makes the HDD LED ++ blink with the pattern corresponding to the serial console (see The Reset ++ Button below). The timeout period is 20 sec. ++ ++ Minimal Console ++ ++ U-Boot for the LinkStation is designed to allow some control over the boot ++ process even in the absence of a console. For this, it uses the power button ++ (the big button at the front) and the reset button (the small red button at ++ the back). ++ ++ Before installing U-Boot, when the LinkStation is switched on, the power LED ++ starts blinking, the original boot loader starts executing and, very ++ quickly, it starts booting the kernel from flash. If U-Boot is installed, ++ the power LED will change from blinking quickly to blinking very slowly. The ++ blink pattern is the same as the one used to indicate sleep mode in normal ++ operation. When the power LED starts blinking slowly at boot, U-Boot has ++ taken over and it is counting down the boot delay before booting the kernel. ++ The default boot delay is 10 sec. From the moment when the power LED starts ++ blinking slowly and for the duration of the boot delay, you can control the ++ boot process with the power and reset buttons. ++ ++ The Power Button ++ ++ If you push the power button and keep it pressed for more than 1 sec, the ++ boot process will stop and the LinkStation will wait for a command. A ++ stopped boot process is indicated by the power LED being lit solid. The ++ effect is the same a pressing 's' on the console. ++ ++ A long push of the power button acts as a toggle. If the boot delay count ++ down is in progress, a long push of the power button stops the boot process. ++ If the boot process is stopped (U-Boot is at the command prompt, even if you ++ can't see it), a long push of the power button restarts the boot process ++ resetting the boot delay to its original value. The restart of the boot ++ process is indicated by the power LED blinking slowly. ++ ++ By default U-Boot supports three pre-configured boot commands: ++ 1. The first boot command will attempt to load and boot a file named ++ boot/vmlinux.UBoot from the first hard disk partition, /dev/hda1. The ++ file can be in any of the U-Boot bootable formats but uImage is the ++ preferred format. If the file is missing or corrupted, U-Boot will fall ++ back to booting the original kernel from flash. ++ 2. The second boot command will boot the original kernel from flash. ++ Please note that the original kernel for the LinkStation 1 / KuroBox ++ standard has a bug in the function that calibrates the decrementer and ++ it will stop for up to 180 sec during boot. This bug is not an U-Boot ++ bug but a kernel bug which is uncovered by the fact that U-Boot ++ activates the decrementer where the original boot loader does not. ++ The original kernel for LinkStation HG / KuroBox HG does not suffer from ++ the above problem. ++ 3. The third boot command will attempt to boot in emergency mode (EM). It ++ does this by passing the argument root=/dev/ram0 to the kernel. ++ LinkStation / LinkStation HG owners should avoid booting in EM mode as ++ the root password for this mode on the LinkStation is unknown. ++ The original kernel for the LinkStation / KuroBox standard and for some ++ of the earlier LinkStation HG / KuroBox HG models ignores the root ++ argument. These models will boot normally from the on-board flash when ++ the EM boot command is used. Read the section on EM mode if your ++ LinkStation HG / KuroBox HG has a kernel that doesn't boot in EM mode ++ using this boot command. ++ ++ You can cycle through the boot commands with the power button. ++ ++ To see which of the three commands U-Boot is going to execute, press the ++ power button quickly. The HDD LED (the third from the top) will start ++ blinking. The number of times the LED blinks, shows the number of the active ++ boot command. For example, a pattern short on - short off - short on - long ++ off, means that the boot command number 2 is active. U-Boot will repeat the ++ blinking cycle for a total duration of about 5 sec counting from the moment ++ the power button is released. ++ ++ A short press of the power button while the HDD LED is blinking will advance ++ the boot command to the next one. ++ ++ Changing the boot command does not change the boot status. If the boot is ++ stopped, it will not be restarted. If the boot is in progress, it will not ++ be stopped but the boot delay will be reset to the original value. ++ ++ The Reset Button ++ ++ Two consoles are currently configured, the serial console and the net ++ console. The first console is the serial console and the second console is ++ the net console (nc). The net console is the default console. ++ ++ The reset button can be used, similarly to the power button, to switch ++ consoles. A press on the reset button (here, it doesn't matter how long you ++ keep the button pressed) displays the currently active console using the HDD ++ LED. Repeatedly pressing the reset button while the HDD LED is blinking will ++ toggle between the two consoles. The blinking pattern is different from the ++ one showing the boot command. The pattern which shows that the second (net) ++ console is active is short off - short on - short off - long on. U-Boot will ++ repeat the blinking cycle for a total duration of about 5 sec counting from ++ the moment the reset button is released. ++ ++ Load and Test ++ ++ Mount the LinkStation SMB public share and copy the following files to it: ++ ++ For LinkStation 1 / KuroBox standard ++ # mount -t smbfs -o password="" ///share/mnt ++ # cp u-boot-hd.ram.bin /mnt ++ # cp ../uloader-2.4.17/uloader.o /mnt ++ # cp ../uloader-2.4.17/u-boot-load-hd.sh /mnt ++ # umount /mmt ++ ++ For LinkStation HG / KuroBox HG ++ # mount -t smbfs -o password="" ///share/mnt ++ # cp u-boot-hg.ram.bin /mnt ++ # cp ../uloader-2.4.20/uloader.o /mnt ++ # cp ../uloader-2.4.20/u-boot-load-hg.sh /mnt ++ # umount /mmt ++ ++ If you installed the serial port, open another window and use minicom to ++ connect to your LinkStation serial console. The serial port settings are ++ 57600,N,8, the same as the settings used by the original Linux kernel. ++ ++ Start netcat to communicate with the U-Boot net console. Open another window ++ and run board/linkstation/nc.sh. Nc.sh is a simple script which invokes ++ netcat with the correct options. To quit nc, press ^T (control-T). ++ # cd $UBOOT_BUILD/u-boot-1.1.4 ++ # board/linkstation/nc.sh ++ ++ Where is CONFIG_IPADDR_LS (see Configure U-Boot ++ above). When you run nc.sh nothing will be written to the screen. This is ++ normal as Linux is not using the net console. ++ ++ From your original window, use telnet to connect to the LinkStation and ++ launch U-Boot. Replace lshg in the example below with the name / IP address ++ of your LinkStation. Replace myroot with the login you created when you ++ gained telnet access. For LinkStation 1 / KuroBox standard, use ++ u-boot-load-hd.sh instead of u-boot-load-hg.sh. Type the commands shown in ++ bold. ++ # telnet lshg ++ Trying 192.168.0.58... ++ Connected to lshg. ++ Escape character is '^]'. ++ BUFFALO INC. Link Station series HD-HGLAN (IEMITSU) ++ HD-HGLAN6C5 login: myroot ++ Linux (none) 2.4.20_mvl31-ppc_linkstation #3 Thu May 19 13:34:18 JST 2005 ++ ppc unknown ++ root@HD-HGLAN6C5:~# cd /mnt/share ++ root@HD-HGLAN6C5:/mnt/share# ./u-boot-load-hg.sh ++ root@HD-HGLAN6C5:/mnt/share# exit ++ Connection closed by foreign host. ++ # ++ ++ If you have a serial console you should see the initial U-Boot startup ++ messages. Even if the default console is the net console, U-Boot still sends ++ the console output to the serial port until it initialises the network ++ controller. ++ U-Boot 1.1.4 LiSt 2.1.0 (Sep 12 2006 - 23:09:44) LinkStation HG / KuroBox HG ++ CPU: MPC8245 Revision 1.4 at 262.144 MHz: 16 kB I-Cache 16 kB D-Cache ++ DRAM: 128 MB ++ FLASH: 4 MB ++ *** Warning - bad CRC, using default environment ++ 00 0b 10ec 8169 0200 ff ++ 00 0c 1283 8212 0180 ff ++ 00 0e 1033 0035 0c03 ff ++ 00 0e 1033 0035 0c03 ff ++ 00 0e 1033 00e0 0c03 ff ++ Net: RTL8169#0 ++ ++ Watch the net console window. After a few seconds, time needed by U-Boot to ++ initialise the network controller and the IDE controller you should see the ++ U-Boot messages. ++ U-Boot 1.1.4 LiSt 2.1.0 (Sep 12 2006 - 23:09:44) LinkStation HG / KuroBox HG ++ IDE: Bus 0: OK ++ Device 0: Model: Maxtor 7Y250P0 Firm: YAR41BW0 Ser#: Y62W8PDE ++ Type: Hard Disk ++ Supports 48-bit addressing ++ Capacity: 239372.4 MB = 233.7 GB (490234752 x 512) ++ Boot in 10 seconds ('s' to stop)... ++ ++ Press 's' on your keyboard to stop the boot process. ++ ++ If you want to use the serial console, watch the power LED of your ++ LinkStation. When it starts blinking very slowly, use the power button to ++ stop the boot process. Wait for the power LED to go dim and press and hold ++ the power button until the LED lights up brightly indicating that the boot ++ process has stopped. Now press the reset button twice and you should see the ++ U-Boot command prompt (=>) in your minicom window. You can now control ++ U-Boot from the minicom window. ++ ++ Using u-boot-load-hd.sh / u-boot-load-hg.sh leads to the above results on ++ devices with the original software. On some LinkStations with modified ++ software, reboot has been modified to send a reboot command to the AVR. ++ This is indicated by the fast blinking of the power LED immediately after ++ running u-boot-load-hd.sh / u-boot-load-hg.sh. Once the AVR receives a ++ reboot command, the reboot process cannot be stopped. The AVR will reboot ++ the LinkStation 5 min after receiving the reboot command. ++ If you find yourself in the above situation you can still test U-Boot by ++ booting your LinkStation with the AVR disabled. Press and hold the reset ++ button and then press the power button. All LEDs will start flashing but ++ your LinkStation will boot normally. Now you can use the procedure ++ described above with one caveat: the AVR being disabled, pressing the ++ buttons will have no effect so you will not be able to test the behaviour ++ of the minimal console. ++ ++ Once you get the U-Boot command prompt, start testing it. Read the ++ [15]U-Boot documentation and try each command you are interested in. ++ ++ Keep in mind that U-Boot interprets all input number as hex numbers. If, for ++ example, you type 256, U-Boot will interpret it as 598 decimal. ++ ++ When you are testing memory write commands, do not attempt to write to the ++ first MB of memory (0x00000000 to 0x00100000) as you will be overwriting the ++ exception vectors and U-Boot will crash. ++ ++ An important command is flinfo which displays information about the flash ++ chip. If the information displayed is correct for your flash, test the flash ++ erase and flash write commands. To do this, you will need to find an empty ++ sector, one for which each byte is 0xFF. Hint: check the last flash sector ++ first, chances are that it's empty. When you are testing commands that write ++ to the flash, always remember that you can write a single byte but you can ++ only erase whole sectors. ++ ++ Be very careful not to write to the flash memory range 0xFFC00000 to ++ 0xFFF7FFFF. This area contains the Linux kernel, the initial RAM disk used ++ for EM mode, the bootloader and the configuration sector (which holds the ++ "OKOK" or "NGNG" pattern). The range 0xFFF80000 to 0xFFFFFFFF is the user ++ area and, in most cases, is empty. Always check using the U-Boot command md ++ (memory display) if the flash area you intend to use is empty (all bytes are ++ 0xFF). For more information about the flash organisation, read ++ [16]PPCFlashROM for the LinkStation 1 / KuroBox standard or [17]HGFlashROM ++ for the LinkStation HG / KuroBox HG. ++ ++ ROM Build ++ ++ Once you are happy with the RAM build, you are ready for the ROM build. ++ ++ For LinkStation 1 / KuroBox standard run: ++ make linkstation_HDLAN_config ++ make linkstation_HDLAN ++ ++ The name of the resulting binary is u-boot-hd.flash.bin ++ ++ For LinkStation HG / KuroBox HG run: ++ make linkstation_HGLAN_config ++ make linkstation_HGLAN ++ ++ The name of the resulting binary is u-boot-hg.flash.bin ++ ++ Install ++ ++ Do not attempt to flash from U-Boot if the power LED is blinking. Your ++ LinkStation is likely to reboot and you will end up with a "brick" ++ Test the flash commands thoroughly before deciding to burn U-Boot into ++ flash. Write at least 128 kB to the flash to test potential timeout ++ problems ++ The flash routines in this version of U-Boot for the LinkStation should be ++ able to identify and handle any CFI flash which uses the AMD standard ++ command set. However, they were tested only on a LinkStation with a Fujitsu ++ MBM29PL32TM flash chip and on a LinkStation HG with a ST Micro M29DW324DB ++ flash chip. ++ Be very careful not to flash your hardware with the wrong U-Boot build. ++ Flashing any RAM build or flashing a ROM build for the LinkStation 1 / ++ KuroBox standard into the LinkStation HG / KuroBox HG or viceversa will ++ "brick" your device. This is especially true if you are flashing from Linux ++ as U-Boot has safety checks to avoid flashing the wrong build. ++ ++ Flashing U-Boot from U-Boot ++ ++ The RAM build of U-Boot can be used to load and flash the ROM build. This is ++ the preferred method. ++ ++ Boot your LinkStation normally. Open a telnet session and create a directory ++ to hold the U-Boot flash image. ++ root@linkstation:~# cd /mnt/share ++ root@linkstation:/mnt/share# mkdir u-boot ++ ++ Copy the U-Boot flash image to your LinkStation SMB share in the directory ++ u-boot. ++ ++ Load the RAM build of U-Boot and at the U-Boot command prompt type: ++ => run upgrade ++ ++ U-Boot will attempt to load the ROM build from the directory share/u-boot/ ++ on the third partition of the hard drive. If the load is successful, it will ++ do the following: ++ 1. unprotect the bootloader area; ++ 2. erase the bootloader area; ++ 3. copy the loaded file to the bootloader area; ++ 4. verify the copy; ++ ++ Here is the output of run upgrade ++ => run upgrade ++ Loading 0:3:share/u-boot/u-boot-hg.flash.bin ++ 174668 bytes read ++ Un-Protected 3 sectors ++ Flash erase: first = 55 @ 0xfff00000 ++ last = 57 @ 0xfff20000 ++ Flash erase: Done ++ Erased 3 sectors ++ Copy to Flash... done ++ Total of 174668 bytes were the same ++ => ++ ++ When the above sequence finishes, U-Boot returns to the command prompt (=>). ++ ++ Depending on your flash chip, the flash operation can take a long time. Wait ++ patiently and do not try to power down or otherwise interrupt the flash or ++ you will end up with a "brick". ++ ++ Reboot: ++ => reset ++ ++ The power LED should start blinking slowly and, if you have a serial ++ console, you should see the U-Boot startup messages. Your LinkStation is now ++ running U-Boot. ++ ++ Flashing U-Boot from Linux ++ ++ Connect to your LinkStation using either the serial port or telnet. ++ ++ For LinkStation 1 / KuroBox standard run: ++ # cd /mnt/share/u-boot ++ # dd if=u-boot-hd.flash.bin of=/dev/fl2 bs=1k ++ # cmp u-boot.bin /dev/fl2 ++ ++ For LinkStation HG / KuroBox HG run: ++ # cd /mnt/share/u-boot ++ # dd if=u-boot-hg.flash.bin of=/dev/mtd1 bs=1k ++ # cmp u-boot.bin /dev/mtd1 ++ ++ The above commands for LinkStation HG / KuroBox HG will work on devices with ++ the original kernel version 2.4.20 but might to work on earlier devices ++ using kernel version 2.4.17. Please check which device corresponds to the ++ bootloader partition on your hardware. ++ ++ If the Flash Fails ++ ++ If the flash was not written correctly but U-Boot returns at the command ++ prompt, try to re-run run upgrade. ++ ++ If the same happens when you attempt to install U-Boot from Linux, try to dd ++ again. ++ ++ If your flash fails completely, for example due to a power failure, all is ++ not completely lost. You can still use a JTAG cable to re-flash your ++ Linkstation. Unfortunately, this is a relatively complicated and expensive ++ solution as it involves acquiring or building the JTAG cable and soldering ++ the header for it on the LinkStation motherboard. For more information on ++ how to use a JTAG cable with the LinkStation you can visit ++ [18]www.linkstationwiki.net and [19]www.kurobox.com/mwiki. ++ ++ EM Mode ++ ++ Warning for the LinkStation / LinkStation HG users ++ ++ Do not attempt to boot into EM mode using the method described here. The ++ password for the EM mode is unknown for all LinkStation models. ++ ++ Once you have U-Boot installed in the on-board flash, you can boot in EM ++ mode even if the third boot command described above doesn't work. ++ ++ Stop the boot countdown by pressing 's' in your net console window and, at ++ the U-Boot command prompt, run: ++ => run writeng ++ => run flboot ++ ++ The above commands write "NGNG" to 0xFFF70000 and boot from the on-board ++ flash. To revert to normal boot by writing "OKOK" to 0xFFF70000, run: ++ => run writeok ++ => boot ++ ++ Advanced configuration ++ ++ The initial U-Boot configuration can be changed by editing the file ++ include/configs/linkstation.h. ++ ++ In all the examples below, please note the backslash-zero (\0) at the end of ++ the strings and the space-backslash ( \) at the end of each lines and do not ++ change them. ++ ++ Change the name of the default boot file ++ ++ Search for the lines containing: ++ "hdpart=0:1\0" \ ++ "hdfile=boot/vmlinux.UBoot\0" \ ++ ++ and change them to the values you want. Partition 0:1 means disk 0, ++ partition 1. Obviously, you can only change the partition number as there is ++ only one disk. The name of the file must be given relative to the root of ++ the partition. ++ ++ Change the default console to the serial console ++ ++ Search for the lines containing: ++ "stdin=nc\0" \ ++ "stdout=nc\0" \ ++ "stderr=nc\0" \ ++ ++ and change them to: ++ "stdin=serial\0" \ ++ "stdout=serial\0" \ ++ "stderr=serial\0" \ ++ ++ Change the default boot command to boot from flash ++ ++ Search for the lines containing: ++ "bootcmd1=run hdboot;run flboot\0" \ ++ "bootcmd2=run flboot\0" \ ++ ++ and change them to: ++ "bootcmd1=run flboot\0" \ ++ "bootcmd2=run hdboot;run flboot\0" \ ++ ++References ++ ++ 1. http://www.linuxnotincluded.org.uk/fdl.txt ++ 2. http://www.linkstationwiki.net/index.php?title=CGI_Exploit_%28PowerPC%29_original_method_of_Hacking_the_LinkStation ++ 3. http://www.linkstationwiki.net/index.php?title=Turn_your_LinkStation_into_a_Kuro_Box_%28PowerPC%29 ++ 4. http://linkstationwiki.net/index.php?title=OpenLink ++ 5. http://linkstationwiki.net/index.php?title=The_LinkStation_firmware_flasher ++ 6. http://downloads.linkstationwiki.net/snapshots/HD-HGLAN_149_100_telnet.zip ++ 7. http://www.linkstationwiki.net/index.php?title=Add_a_Serial_port_to_the_PowerPC_Linkstation ++ 8. http://netcat.sourceforge.net/ ++ 9. http://www.vulnwatch.org/netcat ++ 10. http://ftp.sunet.se/pub/Linux/distributions/eldk/3.1.1/ppc-linux-x86/iso/ppc-2005-03-07.iso ++ 11. ftp://ftp.denx.de/pub/u-boot/u-boot-1.1.4.tar.bz2 ++ 12. http://www.linuxnotincluded.org.uk/linkstation/downloads/u-boot-1.1.4-list-2.1.0.diff.gz ++ 13. http://www.linuxnotincluded.org.uk/linkstation/downloads/uloader-2.4.17.tar.gz ++ 14. http://www.linuxnotincluded.org.uk/linkstation/downloads/uloader-2.4.20.tar.gz ++ 15. http://www.denx.de/wiki/DULG/Manual ++ 16. http://linkstationwiki.net/index.php?title=Information/PPCFlashROM ++ 17. http://linkstationwiki.net/index.php?title=Information/HGFlashROM ++ 18. http://www.linkstationwiki.net/ ++ 19. http://www.kurobox.com/mwiki +diff -urN u-boot-86xx/board/linkstation/Makefile u-boot-86xx-kuro_clean/board/linkstation/Makefile +--- u-boot-86xx/board/linkstation/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-86xx-kuro_clean/board/linkstation/Makefile 2006-11-06 22:05:38.000000000 +0100 +@@ -0,0 +1,41 @@ ++# ++# (C) Copyright 2001 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = lib$(BOARD).a ++ ++OBJS = $(BOARD).o flash.o ide.o hwctl.o bootls.o avr.o ++SOBJS = early_init.o ++ ++$(LIB): .depend $(OBJS) $(SOBJS) ++ $(AR) crv $@ $(OBJS) $(SOBJS) ++ ++######################################################################### ++ ++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) ++ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ ++ ++sinclude .depend ++ ++######################################################################### +diff -urN u-boot-86xx/board/linkstation/avr.c u-boot-86xx-kuro_clean/board/linkstation/avr.c +--- u-boot-86xx/board/linkstation/avr.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-86xx-kuro_clean/board/linkstation/avr.c 2006-11-06 22:05:38.000000000 +0100 +@@ -0,0 +1,307 @@ ++/* ++ * avr.c ++ * ++ * AVR functions ++ * ++ * Copyright (C) 2006 Mihai Georgian ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++#include ++#include ++#include ++ ++/* Button codes from the AVR */ ++#define PWRR 0x20 /* Power button release */ ++#define PWRP 0x21 /* Power button push */ ++#define RESR 0x22 /* Reset button release */ ++#define RESP 0x23 /* Reset button push */ ++#define AVRINIT 0x33 /* Init complete */ ++#define AVRRESET 0x31 /* Reset request */ ++ ++/* LED commands */ ++#define PWRBLINKSTRT '[' /* Blink power LED */ ++#define PWRBLINKSTOP 'Z' /* Solid power LED */ ++#define HDDLEDON 'W' /* HDD LED on */ ++#define HDDLEDOFF 'V' /* HDD LED off */ ++#define HDDBLINKSTRT 'Y' /* HDD LED start blink */ ++#define HDDBLINKSTOP 'X' /* HDD LED stop blink */ ++ ++/* Timings for LEDs blinking to show choice */ ++#define PULSETIME 250 /* msecs */ ++#define LONGPAUSE (5 * PULSETIME) ++ ++/* Button press times */ ++#define PUSHHOLD 1000 /* msecs */ ++#define NOBUTTON (6 * (LONGPAUSE+PULSETIME)) ++ ++/* Boot and console choices */ ++#define MAX_BOOT_CHOICE 3 ++ ++static char *consoles[] = { ++ "serial", ++#if defined(CONFIG_NETCONSOLE) ++ "nc", ++#endif ++}; ++#define MAX_CONS_CHOICE (sizeof(consoles)/sizeof(char *)) ++ ++#if !defined(CONFIG_NETCONSOLE) ++#define DEF_CONS_CHOICE 0 ++#else ++#define DEF_CONS_CHOICE 1 ++#endif ++ ++#define perror(fmt,args...) printf("%s: ",__FUNCTION__);printf(fmt,##args) ++ ++extern void miconCntl_SendCmd(unsigned char dat); ++extern void miconCntl_DisWDT(void); ++ ++static int boot_stop; ++ ++static int boot_choice = 1; ++static int cons_choice = DEF_CONS_CHOICE; ++ ++static char envbuffer[16]; ++ ++void init_AVR_DUART (void) ++{ ++ NS16550_t AVR_port = (NS16550_t) CFG_NS16550_COM2; ++ int clock_divisor = CFG_NS16550_CLK / 16 / 9600; ++ ++ /* ++ * AVR port init sequence taken from ++ * the original Linkstation init code ++ * Normal U-Boot serial reinit doesn't ++ * work because the AVR uses even parity ++ */ ++ AVR_port->lcr = 0x00; ++ AVR_port->ier = 0x00; ++ AVR_port->lcr = LCR_BKSE; ++ AVR_port->dll = clock_divisor & 0xff; ++ AVR_port->dlm = (clock_divisor >> 8) & 0xff; ++ AVR_port->lcr = LCR_WLS_8 | LCR_PEN | LCR_EPS; ++ AVR_port->mcr = 0x00; ++ AVR_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; ++ ++ miconCntl_DisWDT(); ++ ++ boot_stop = 0; ++ miconCntl_SendCmd(PWRBLINKSTRT); ++} ++ ++void hw_watchdog_reset (void) ++{ ++} ++ ++static inline int avr_tstc(void) ++{ ++ return (NS16550_tstc((NS16550_t)CFG_NS16550_COM2)); ++} ++ ++static inline char avr_getc(void) ++{ ++ return (NS16550_getc((NS16550_t)CFG_NS16550_COM2)); ++} ++ ++static int push_timeout(char button_code) ++{ ++ ulong push_start = get_timer(0); ++ while (get_timer(push_start) <= PUSHHOLD) ++ if (avr_tstc() && avr_getc() == button_code) ++ return 0; ++ return 1; ++} ++ ++static void next_boot_choice(void) ++{ ++ ulong return_start; ++ ulong pulse_start; ++ int on_times; ++ int button_on; ++ int led_state; ++ char c; ++ ++ button_on = 0; ++ return_start = get_timer(0); ++ ++ on_times = boot_choice; ++ led_state = 0; ++ miconCntl_SendCmd(HDDLEDOFF); ++ pulse_start = get_timer(0); ++ ++ while (get_timer(return_start) <= NOBUTTON || button_on) ++ { ++ if (avr_tstc()) { ++ c = avr_getc(); ++ if (c == PWRP) ++ button_on = 1; ++ else if (c == PWRR) { ++ button_on = 0; ++ return_start = get_timer(0); ++ if (++boot_choice > MAX_BOOT_CHOICE) ++ boot_choice = 1; ++ sprintf(envbuffer, "bootcmd%d", boot_choice); ++ if (getenv(envbuffer)) { ++ sprintf(envbuffer, "run bootcmd%d", boot_choice); ++ setenv("bootcmd", envbuffer); ++ } ++ on_times = boot_choice; ++ led_state = 1; ++ miconCntl_SendCmd(HDDLEDON); ++ pulse_start = get_timer(0); ++ } else { ++ perror("Unexpected code: 0x%02X\n", c); ++ } ++ } ++ if (on_times && get_timer(pulse_start) > PULSETIME) { ++ if (led_state == 1) { ++ --on_times; ++ led_state = 0; ++ miconCntl_SendCmd(HDDLEDOFF); ++ } else { ++ led_state = 1; ++ miconCntl_SendCmd(HDDLEDON); ++ } ++ pulse_start = get_timer(0); ++ } ++ if (!on_times && get_timer(pulse_start) > LONGPAUSE) { ++ on_times = boot_choice; ++ led_state = 1; ++ miconCntl_SendCmd(HDDLEDON); ++ pulse_start = get_timer(0); ++ } ++ } ++ if (led_state) ++ miconCntl_SendCmd(HDDLEDOFF); ++} ++ ++void next_cons_choice(int console) ++{ ++ ulong return_start; ++ ulong pulse_start; ++ int on_times; ++ int button_on; ++ int led_state; ++ char c; ++ device_t *idev; ++ device_t *odev; ++ ++ button_on = 0; ++ cons_choice = console; ++ return_start = get_timer(0); ++ ++ on_times = cons_choice+1; ++ led_state = 1; ++ miconCntl_SendCmd(HDDLEDON); ++ pulse_start = get_timer(0); ++ ++ while (get_timer(return_start) <= NOBUTTON || button_on) ++ { ++ if (avr_tstc()) { ++ c = avr_getc(); ++ if (c == RESP) ++ button_on = 1; ++ else if (c == RESR) { ++ button_on = 0; ++ return_start = get_timer(0); ++ cons_choice = (cons_choice + 1) % MAX_CONS_CHOICE; ++ idev = search_device(DEV_FLAGS_INPUT, consoles[cons_choice]); ++ odev = search_device(DEV_FLAGS_OUTPUT, consoles[cons_choice]); ++ console_setfile (stdin, idev); ++ console_setfile (stdout, odev); ++ console_setfile (stderr, odev); ++ on_times = cons_choice+1; ++ led_state = 0; ++ miconCntl_SendCmd(HDDLEDOFF); ++ pulse_start = get_timer(0); ++ } else { ++ perror("Unexpected code: 0x%02X\n", c); ++ } ++ } ++ if (on_times && get_timer(pulse_start) > PULSETIME) { ++ if (led_state == 0) { ++ --on_times; ++ led_state = 1; ++ miconCntl_SendCmd(HDDLEDON); ++ } else { ++ led_state = 0; ++ miconCntl_SendCmd(HDDLEDOFF); ++ } ++ pulse_start = get_timer(0); ++ } ++ if (!on_times && get_timer(pulse_start) > LONGPAUSE) { ++ on_times = cons_choice+1; ++ led_state = 0; ++ miconCntl_SendCmd(HDDLEDOFF); ++ pulse_start = get_timer(0); ++ } ++ } ++ if (led_state); ++ miconCntl_SendCmd(HDDLEDOFF); ++} ++ ++int avr_input(void) ++{ ++ char avr_button; ++ int ret; ++ ++ if (!avr_tstc()) ++ return 0; ++ ++ avr_button = avr_getc(); ++ switch (avr_button) { ++ case PWRP: ++ if (push_timeout(PWRR)) { ++ /* Timeout before power button release */ ++ boot_stop = ~boot_stop; ++ if (boot_stop) ++ miconCntl_SendCmd(PWRBLINKSTOP); ++ else ++ miconCntl_SendCmd(PWRBLINKSTRT); ++ /* Wait for power button release */ ++ while (avr_getc() != PWRR) ++ ; ++ } ++ else ++ /* Power button released */ ++ next_boot_choice(); ++ break; ++ case RESP: ++ /* Wait for Reset button release */ ++ while (avr_getc() != RESR) ++ ; ++ next_cons_choice(cons_choice); ++ break; ++ case AVRINIT: ++ return 0; ++ default: ++ perror("Unexpected code: 0x%02X\n", avr_button); ++ return 0; ++ } ++ if (boot_stop) ++ return (-3); ++ else ++ return (-2); ++} ++ ++void avr_StopBoot(void) ++{ ++ boot_stop = ~0; ++ miconCntl_SendCmd(PWRBLINKSTOP); ++} ++ ++/* vim: set ts=4: */ +diff -urN u-boot-86xx/board/linkstation/bootls.c u-boot-86xx-kuro_clean/board/linkstation/bootls.c +--- u-boot-86xx/board/linkstation/bootls.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-86xx-kuro_clean/board/linkstation/bootls.c 2006-11-06 22:05:38.000000000 +0100 +@@ -0,0 +1,304 @@ ++/* ++ * bootls.c ++ * ++ * Boot a Linkstation kernel of type firmimg.bin ++ * ++ * U-Boot loader code for Linkstation kernel. A file of type firmimg.bin ++ * consists of a header, immediately followed by a compressed kernel image, ++ * followed by a compressed initrd image. ++ * ++ * Copyright (C) 2006 Mihai Georgian ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ * Derived from: ++ * ++ * arch/ppc/common/misc-simple.c (linux-2.4.17_mvl21-sandpoint) ++ * Author: Matt Porter ++ * Derived from arch/ppc/boot/prep/misc.c ++ * 2001 (c) MontaVista, Software, Inc. ++ * ++ * common/cmd_bootm.c (u-boot-1.1.4) ++ * (C) Copyright 2000-2002 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ */ ++ ++#include ++#include ++ ++#include "firminfo.h" ++ ++#define _ALIGN(addr,size) (((addr)+size-1)&(~(size-1))) ++ ++struct bi_record { ++ unsigned long tag; /* tag ID */ ++ unsigned long size; /* size of record (in bytes) */ ++ unsigned long data[0]; /* data */ ++}; ++ ++#define BI_FIRST 0x1010 /* first record - marker */ ++#define BI_LAST 0x1011 /* last record - marker */ ++ ++extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); ++extern int gunzip(void *, int, unsigned char *, int *); ++ ++/* ++ * output BYTE data ++ */ ++static inline void outb(volatile unsigned char *addr, int val) ++{ ++ asm volatile("eieio"); ++ asm volatile("stb%U0%X0 %1,%0; sync; isync" : "=m" (*addr) : "r" (val)); ++} ++ ++unsigned long checksum_check(unsigned char* addr, unsigned long size) ++{ ++ long *laddr = (long *)addr; ++ unsigned long sum = 0,remain = 0; ++ int i; ++ while(size>=4) { ++ sum += *laddr; ++ laddr++; ++ size -= 4; ++ } ++ addr = (unsigned char*)laddr; ++ for(i=0;i<4;++i) { ++ remain = remain << 8; ++ if(size>i) remain += *addr; ++ addr++; ++ } ++ sum += remain; ++ return sum; ++} ++ ++void do_boot_lskernel (cmd_tbl_t *cmdtp, ++ int flag, ++ int argc, ++ char *argv[], ++ unsigned long load_addr, ++ unsigned long *len_ptr, ++ int verify) ++{ ++ DECLARE_GLOBAL_DATA_PTR; ++ ++ char *zimage_start; ++ int zimage_size; ++ unsigned long initrd_start; ++ unsigned long initrd_end; ++ unsigned long sp; ++ unsigned long cmd_start; ++ unsigned long cmd_end; ++ char *cmdline; ++ char *s; ++ bd_t *kbd; ++ void (*kernel)(bd_t *, ulong, ulong, ulong, ulong); ++ unsigned long iflag; ++ struct firminfo *info = (struct firminfo *)load_addr; ++ struct bi_record *rec; ++ ++ int i; ++ char *flashstr="FLASH"; ++ ++ for (i=0; i <= 4; i++) ++ if (info->subver[i] != flashstr[i]) { ++ puts ("Not a Linkstation kernel\n"); ++ return; ++ } ++ ++ printf("\n******* Product Information *******\n"); ++ printf("----------------------------------\n"); ++ ++ printf("Product Name: %s\n", info->firmname); ++ printf(" VER: %d.%02d\n", info->ver_major, info->ver_minor); ++ printf(" Date: %d/%d/%d %d:%d:%d\n", ++ info->year+1900, info->mon, info->day, ++ info->hour,info->min,info->sec); ++ printf("----------------------------------\n"); ++ ++ if (verify) { ++ printf("Verifying checksum... "); ++ if (checksum_check((unsigned char*)info, info->size) != 0) { ++ printf("Failed!: checksum %08X, expecting 0\n", ++ checksum_check((unsigned char*)info, info->size)); ++ return; /* Returns on error */ ++ } else ++ printf("OK\n"); ++ } ++ ++ zimage_start = (char*)info + info->kernel_offset; ++ zimage_size = (int)info->kernel_size; ++ iflag = disable_interrupts(); ++ puts("Uncompressing kernel..."); ++ if (gunzip(0, 0x400000, zimage_start, &zimage_size) != 0) { ++ puts ("Failed! MUST reset board to recover\n"); ++ do_reset (cmdtp, flag, argc, argv); ++ } else ++ puts("done.\n"); ++ ++ /* ++ * Allocate space for command line and board info - the ++ * address should be as high as possible within the reach of ++ * the kernel (see CFG_BOOTMAPSZ settings), but in unused ++ * memory, which means far enough below the current stack ++ * pointer. ++ */ ++ ++ asm( "mr %0,1": "=r"(sp) : ); ++ debug ("## Current stack ends at 0x%08lX ", sp); ++ sp -= 2048; /* just to be sure */ ++ if (sp > CFG_BOOTMAPSZ) ++ sp = CFG_BOOTMAPSZ; ++ sp &= ~0xF; ++ debug ("=> set upper limit to 0x%08lX\n", sp); ++ ++ cmdline = (char *)((sp - CFG_BARGSIZE) & ~0xF); ++ if ((s = getenv("bootargs")) == NULL) ++ s = "root=/dev/hda1"; ++ strcpy (cmdline, s); ++ cmd_start = (ulong)&cmdline[0]; ++ cmd_end = cmd_start + strlen(cmdline); ++ debug ("## cmdline at 0x%08lX ... 0x%08lX\n", cmd_start, cmd_end); ++ ++ kbd = (bd_t *)(((ulong)cmdline - sizeof(bd_t)) & ~0xF); ++ *kbd = *(gd->bd); ++ if ((s = getenv ("clocks_in_mhz")) != NULL) { ++ /* convert all clock information to MHz */ ++ kbd->bi_intfreq /= 1000000L; ++ kbd->bi_busfreq /= 1000000L; ++ } ++ ++ kernel = (void (*)(bd_t *, ulong, ulong, ulong, ulong))0x4; ++ ++ if (info->initrd_size > 0) { ++ initrd_start = (unsigned long)((char*)info + info->initrd_offset); ++ initrd_end = initrd_start + info->initrd_size; ++ if(initrd_start > 0xffc00000 && initrd_end < 0xffefffff) { ++ unsigned long nsp; ++ unsigned long data; ++ ++ data = initrd_start; ++ /* ++ * the inital ramdisk does not need to be within ++ * CFG_BOOTMAPSZ as it is not accessed until after ++ * the mm system is initialised. ++ * ++ * do the stack bottom calculation again and see if ++ * the initrd will fit just below the monitor stack ++ * bottom without overwriting the area allocated ++ * above for command line args and board info. ++ */ ++ asm( "mr %0,1": "=r"(nsp) : ); ++ nsp -= 2048; /* just to be sure */ ++ nsp &= ~0xF; ++ nsp -= info->initrd_size; ++ nsp &= ~(4096 - 1); /* align on page */ ++ initrd_start = nsp; ++ initrd_end = initrd_start + info->initrd_size; ++ printf ("Loading Ramdisk at 0x%08lX, end 0x%08lX ... ", ++ initrd_start, initrd_end); ++ memmove ((void *)initrd_start, (void *)data, info->initrd_size); ++ puts ("OK\n"); ++ } ++ } else { ++ initrd_start = 0; ++ initrd_end = 0; ++ } ++ ++ /* ++ * The kernel looks for this structure even if ++ * the information in it is replaced by the ++ * Linkstation kernel ++ */ ++ rec = (struct bi_record *)_ALIGN((unsigned long)zimage_size + ++ (1 << 20) - 1,(1 << 20)); ++ rec->tag = BI_FIRST; ++ rec->size = sizeof(struct bi_record); ++ rec = (struct bi_record *)((unsigned long)rec + rec->size); ++ rec->tag = BI_LAST; ++ rec->size = sizeof(struct bi_record); ++ ++#if defined(CONFIG_HLAN) || defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) ++ // kernel load done. ++ outb(0x80004500, 0x49); // send signal ++ outb(0x80004500, 0x49); // send signal ++ outb(0x80004500, 0x49); // send signal ++ outb(0x80004500, 0x49); // send signal ++#endif ++#if defined(CONFIG_HGLAN) ++ // full speed ++ udelay(10000); /* 10 msec */ ++ outb(0x80004500, 0x5D); // send signal ++ outb(0x80004500, 0x5D); // send signal ++ outb(0x80004500, 0x5D); // send signal ++ outb(0x80004500, 0x5D); // send signal ++#endif ++#if defined(CONFIG_HTGL) ++ // LINK/ACT led controll ++ outb(0x80004500, 0x61); // a ++ outb(0x80004500, 0x61); // a ++ outb(0x80004500, 0x39); // 9 ++ outb(0x80004500, 0x31); // 1 ++ outb(0x80004500, 0x39); // 9 ++ outb(0x80004500, 0x30); // 0 ++ outb(0x80004500, 0x92); // 1000Mbps down ++ outb(0x80004500, 0x92); // 1000Mbps down ++ ++ udelay(10000); /* 10 msec */ ++ outb(0x80004500, 0x61); // a ++ outb(0x80004500, 0x61); // a ++ outb(0x80004500, 0x39); // 9 ++ outb(0x80004500, 0x30); // 0 ++ outb(0x80004500, 0x39); // 9 ++ outb(0x80004500, 0x30); // 0 ++ outb(0x80004500, 0x90); // 100Mbps down ++ outb(0x80004500, 0x90); // 100Mbps down ++ ++ udelay(10000); /* 10 msec */ ++ outb(0x80004500, 0x61); // a ++ outb(0x80004500, 0x61); // a ++ outb(0x80004500, 0x38); // 8 ++ outb(0x80004500, 0x46); // F ++ outb(0x80004500, 0x39); // 9 ++ outb(0x80004500, 0x30); // 0 ++ outb(0x80004500, 0x8E); // 10Mbps down ++ outb(0x80004500, 0x8E); // 10Mbps down ++ ++ udelay(10000); /* 10 msec */ ++ outb(0x80004500, 0x5F); // _ ++ outb(0x80004500, 0x5F); // _ ++#endif ++ ++/* ++ * This is what the original boot loader sends ++ * just before jumping to the kernel start ++ */ ++ outb(0xFF000001, 0xFF); ++ ++ puts("Booting the kernel\n"); ++ ++ /* ++ * Linux Kernel Parameters: ++ * r3: ptr to board info data ++ * r4: initrd_start or 0 if no initrd ++ * r5: initrd_end - unused if r4 is 0 ++ * r6: Start of command line string ++ * r7: End of command line string ++ */ ++ (*kernel)((bd_t *)0xFF000001, initrd_start, initrd_end, cmd_start, cmd_end); ++} ++ ++/* vim: set ts=4: */ +diff -urN u-boot-86xx/board/linkstation/config.mk u-boot-86xx-kuro_clean/board/linkstation/config.mk +--- u-boot-86xx/board/linkstation/config.mk 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-86xx-kuro_clean/board/linkstation/config.mk 2006-11-06 22:05:38.000000000 +0100 +@@ -0,0 +1,50 @@ ++# ++# (C) Copyright 2001-2003 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++# LinkStation/LinkStation-HG: ++# ++# Valid values for TEXT_BASE are: ++# ++# Standard configuration - all models ++# 0xFFF00000 boot from flash ++# ++# Test configuration (boot from RAM using uloader.o) ++# LinkStation HD-HLAN and KuroBox Standard ++# 0x03F00000 boot from RAM ++# LinkStation HD-HGLAN and KuroBox HG ++# 0x07F00000 boot from RAM ++# ++ ++sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp ++ ++ifndef TEXT_BASE ++# For flash image - all models ++TEXT_BASE = 0xFFF00000 ++# For RAM image ++# HLAN and LAN ++#TEXT_BASE = 0x03F00000 ++# HGLAN and HGTL ++#TEXT_BASE = 0x07F00000 ++endif ++ ++PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) +diff -urN u-boot-86xx/board/linkstation/early_init.S u-boot-86xx-kuro_clean/board/linkstation/early_init.S +--- u-boot-86xx/board/linkstation/early_init.S 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-86xx-kuro_clean/board/linkstation/early_init.S 2006-11-06 22:05:38.000000000 +0100 +@@ -0,0 +1,432 @@ ++/* ++ * board/linkstation/early_init.S ++ * ++ * Begin at some arbitrary location in RAM or Flash ++ * Initialize core registers ++ * Configure memory controller (Not executing from RAM) ++ * Initialize UARTs ++ * Simple RAM test (currently suspended) ++ * ++ * Copyright (C) 2006 Mihai Georgian ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ * Modified for U-Boot from arch/ppc/boot/linkstation/head.S from ++ * the GPL code for the Buffalo Terastation, derived in its turn from: ++ * ++ * arch/ppc/boot/sandpoint/head.S ++ * ++ * Initial board bringup code for Motorola SPS Sandpoint test platform ++ * ++ * Author: Mark A. Greer ++ * mgreer@mvista.com ++ * Derived from arch/ppc/boot/pcore/head.S (mporter@mvista.com) ++ * ++ * Copyright 2001 MontaVista Software Inc. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_LAN) || defined(CONFIG_HLAN) ++#define RAM_SIZE 0x04000000 ++#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) ++#define RAM_SIZE 0x08000000 ++#endif ++ ++#define UART1 0x80004500 ++#define UART1_IER 0x80004501 ++#define UART1_FCR 0x80004502 ++#define UART1_LCR 0x80004503 ++#define UART1_DCR 0x80004511 ++#define UART2 0x80004600 ++#define UART2_IER 0x80004601 ++#define UART2_FCR 0x80004602 ++#define UART2_LCR 0x80004603 ++#define UART2_DCR 0x80004611 ++ ++#define WM32(address,data) \ ++ lis r3, address@h; \ ++ ori r3, r3, address@l; \ ++ lis r4, data@h; \ ++ ori r4, r4, data@l; \ ++ stw r4, 0x0000(r3); \ ++ sync; \ ++ isync; ++ ++#define WM16(address,data) \ ++ lis r3, address@h; \ ++ ori r3, r3, address@l; \ ++ li r4, data; \ ++ sth r4, 0x0000(r3); \ ++ sync; \ ++ isync; ++ ++#define WM8(address,data) \ ++ lis r3, address@h; \ ++ ori r3, r3, address@l; \ ++ li r4, data; \ ++ stb r4, 0(r3); \ ++ sync; \ ++ isync; ++ ++ .text ++ ++ .globl early_init_f ++early_init_f: ++/* ++ * Configure core registers ++ */ ++ ++ /* Establish default MSR value, exception prefix 0xFFF */ ++ li r3,MSR_IP|MSR_FP ++ mtmsr r3 ++ ++ /* Clear BATS */ ++ li r8,0 ++ mtspr DBAT0U,r8 ++ mtspr DBAT0L,r8 ++ mtspr DBAT1U,r8 ++ mtspr DBAT1L,r8 ++ mtspr DBAT2U,r8 ++ mtspr DBAT2L,r8 ++ mtspr DBAT3U,r8 ++ mtspr DBAT3L,r8 ++ mtspr IBAT0U,r8 ++ mtspr IBAT0L,r8 ++ mtspr IBAT1U,r8 ++ mtspr IBAT1L,r8 ++ mtspr IBAT2U,r8 ++ mtspr IBAT2L,r8 ++ mtspr IBAT3U,r8 ++ mtspr IBAT3L,r8 ++ isync ++ sync ++ sync ++ ++ /* Set segment registers */ ++ lis r8, 0x0000 ++ isync ++ mtsr SR0,r8 ++ mtsr SR1,r8 ++ mtsr SR2,r8 ++ mtsr SR3,r8 ++ mtsr SR4,r8 ++ mtsr SR5,r8 ++ mtsr SR6,r8 ++ mtsr SR7,r8 ++ mtsr SR8,r8 ++ mtsr SR9,r8 ++ mtsr SR10,r8 ++ mtsr SR11,r8 ++ mtsr SR12,r8 ++ mtsr SR13,r8 ++ mtsr SR14,r8 ++ mtsr SR15,r8 ++ isync ++ sync ++ sync ++ ++ /* Disable L1 icache/dcache */ ++ li r4,0x0000 ++ isync ++ mtspr HID0,r4 ++ sync ++ isync ++ ++ /* Flash Invalidate L1 icache/dcache */ ++ ++ ori r4,r4,0x8000 ++ ori r8,r4,0x0800 ++ isync ++ mtspr HID0,r8 ++ sync ++ isync ++ ++ /* Older cores need to manually clear ICFI bit */ ++ ++ mtspr HID0,r4 ++ sync ++ isync ++ ++#if !defined(CFG_RAMBOOT) ++melco_config_start: ++ /* --- CPU Configration registor setting for LinkStation --- */ ++ WM32(0x80041020,0x000000a0) /* Reset EPIC */ ++ ++ /* errata for latency timer */ ++ WM32(0xFEC00000,0x0d000080) ++ WM8(0xFEE00001,0x20) ++ /* cash size */ ++ WM32(0xFEC00000,0x0c000080) ++ WM8(0xFEE00000,0x08) ++ /* PCI configuration command register */ ++ WM32(0xFEC00000,0x04000080) ++ WM16(0xFEE00000,0x0600) ++ /* Processor interface configuration register 1 */ ++ WM32(0xFEC00000,0xa8000080) ++ /* WM32(0xFEE00000,0xd8131400) */ ++ lis r3, 0xFEE00000@h ++ ori r3, r3, 0xFEE00000@l ++ ++ lwz r5, 0(r3) /* load PCIR1 Config */ ++ lis r4, 0x0 ++ ori r4, r4, 0x1000 ++ and r5, r4, r5 /* Get Bit20(RCS0) */ ++ ++ lis r4, 0xd8130400@h ++ ori r4, r4, 0xd8130400@l ++ or r4, r4, r5 /* Save (RCS0) */ ++ ++ stw r4, 0x0000(r3) ++ sync ++ isync ++ ++ /* Processor interface configuration register 2 */ ++ WM32(0xFEC00000,0xac000080) ++ WM32(0xFEE00000,0x00000004) ++ /* Embeded Utility Memory Block Base Address register */ ++ WM32(0xFEC00000,0x78000080) ++ WM32(0xFEE00000,0x00000080) ++ /* Address map B option register */ ++ WM32(0xFEC00000,0xe0000080) ++ WM8(0xFEE00000,0x20) /* DLL_RESET on */ ++ ++ /* Address map B option register */ ++ WM32(0xFEC00000,0xe0000080) ++ WM8(0xFEE00000,0xc0) ++ /* PCI arbiter control register */ ++ WM32(0xFEC00000,0x46000080) ++ WM16(0xFEE00002,0x00c0) ++ ++ /* Added to use the high drive strength for the memory selects & addressing */ ++ WM32(0xFEC00000,0x73000080) ++ /* WM8(0xFEE00003,0x15) */ /*0x17*/ ++ /* Motorola Errata refer to User's Manual Errata#19 */ ++ /* WM8(0xFEE00003,0xD5) */ ++ WM8(0xFEE00003,0x95) ++ ++ /* set miscellaneous I/O control register 1 */ ++ WM32(0xFEC00000,0x76000080) ++ WM8(0xFEE00002,0x00) /*0x02*/ ++ /* set miscellaneous I/O control register 2 */ ++ WM32(0xFEC00000,0x77000080) ++ WM8(0xFEE00003,0x30) /* 0x30 */ ++ ++ /* init memory controller */ ++ WM32(0xFEC00000,0x80000080) ++ WM32(0xFEE00000,0x00FFFFFF) ++ ++ WM32(0xFEC00000,0x84000080) ++ WM32(0xFEE00000,0xFFFFFFFF) ++ ++ WM32(0xFEC00000,0x90000080) ++#if defined(CONFIG_LAN) || defined(CONFIG_HLAN) ++ WM32(0xFEE00000,0x3FFFFFFF) /* 64MB */ ++#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) ++ WM32(0xFEE00000,0x7FFFFFFF) /* 128MB */ ++#endif ++ ++ WM32(0xFEC00000,0x94000080) ++ WM32(0xFEE00000,0xFFFFFFFF) ++ ++ WM32(0xFEC00000,0x88000080) ++ WM32(0xFEE00000,0x00030303) ++ /* EMSAR2 */ ++ WM32(0xFEC00000,0x8C000080) ++ WM32(0xFEE00000,0x03030303) ++ /* select EMSER1 */ ++ WM32(0xFEC00000,0x98000080) ++ WM32(0xFEE00000,0x00030303) ++ /* select EMSER2 */ ++ WM32(0xFEC00000,0x9C000080) ++ WM32(0xFEE00000,0x03030303) ++ ++ /* MMCR1 */ ++ WM32(0xFEC00000,0xf0000080) ++#if defined(CONFIG_LAN) || defined(CONFIG_HLAN) ++ WM32(0xFEE00000,0x0200E005) /* bank 0 13xnx4 */ ++#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) ++ WM32(0xFEE00000,0x0200E005) /* bank 0 13xnx4 */ ++#endif ++ /* MCCR2 */ ++ WM32(0xFEC00000,0xf4000080) ++#if defined(CONFIG_LAN) || defined(CONFIG_HLAN) ++ WM32(0xFEE00000,0xe0150000) /* 100MHz Memory bus */ ++#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) ++ WM32(0xFEE00000,0x80150000) /* 133MHz Memory bus */ ++#endif ++ /* MCCR3 */ ++ WM32(0xFEC00000,0xf8000080) ++ WM32(0xFEE00000,0x00000077) /* BSTOPRE_M =7 / REFREC=8 */ ++ ++ /* MCCR4 */ ++ WM32(0xFEC00000,0xfc000080) ++#if defined(CONFIG_LAN) || defined(CONFIG_HLAN) ++ WM32(0xFEE00000,0x29233222) /* CAS latency=2, burst length=8, Ext Rom=eable */ ++#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) ++ WM32(0xFEE00000,0x29323222) /* CAS latency=3, burst length=4, Ext Rom=eable */ ++#endif ++ ++ /* Output driver control register */ ++ WM32(0xFEC00000,0x73000080) ++ WM8(0xFEE00003,0x15) /* for all 40 ohm */ ++ /* CLK driver Control Register */ ++ WM32(0xFEC00000,0x74000080) ++ WM16(0xFEE00000,0x7078) ++ /* select MBEN */ ++ WM32(0xFEC00000,0xa0000080) ++ WM8(0xFEE00000, 0x01) ++ /* MPM */ ++ WM32(0xFEC00000,0xa3000080) ++#if defined(CONFIG_LAN) || defined(CONFIG_HLAN) ++ WM8(0xFEE00003,0xF2) /* PGMAX = 242 */ ++#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) ++ WM8(0xFEE00003,0xC9) /* PGMAX = 201 */ ++#endif ++ /* ERCR s */ ++ WM32(0xFEC00000,0xd0000080) /* ; select ERCR1 */ ++ WM32(0xFEE00000,0xffffff85) ++ WM32(0xFEC00000,0xd4000080) /* ; select ERCR2 */ ++ WM32(0xFEE00000,0xffffff05) ++ WM32(0xFEC00000,0xd8000080) /* ; select ERCR3 */ ++ WM32(0xFEE00000,0x0000f80f) ++ WM32(0xFEC00000,0xdc000080) /* ; select ERCR4 */ ++ WM32(0xFEE00000,0x0e000000) ++ ++ /* MCCR1 */ ++ WM32(0xFEC00000,0xf0000080) ++ WM32(0xFEE00000,0x0200E805) /* 11 + 3 clock wait MEMGO on */ ++ ++ /* Init UART for AVR */ ++ WM8(UART1_LCR,0x00) /* clear LCR */ ++ WM8(UART1_IER,0x00) /* disable interrupt */ ++ WM8(UART1_LCR,0x80) /* set LCR[DLAB] bit */ ++ WM8(UART1_DCR,0x01) /* set DUART mode */ ++#if defined(CONFIG_LAN) || defined(CONFIG_HLAN) ++ WM8(UART1, 0x8B) /* set DLL(baudrate 9600bps, 100MHz) */ ++ WM8(UART1_IER,0x02) /* set DLM(baudrate 9600bps, 100MHz) */ ++#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) ++ WM8(UART1, 0x61) /* set DLL(baudrate 9600bps, 133MHz) */ ++ WM8(UART1_IER,0x03) /* set DLM(baudrate 9600bps, 133MHz) */ ++#endif ++ WM8(UART1_LCR,0x1b) /* set 8data, 1stop, even parity */ ++ WM8(UART1, 0x00) /* clear MCR */ ++ WM8(UART1_FCR,0x07) /* clear & enable FIFO */ ++ ++ /* Init UART for CONSOLE */ ++ WM8(UART2_LCR,0x00) /* clear LCR */ ++ WM8(UART2_IER,0x00) /* disable interrupt */ ++ WM8(UART2_LCR,0x80) /* set LCR[DLAB] bit */ ++ WM8(UART1_DCR,0x01) /* set DUART mode */ ++#if defined(CONFIG_LAN) || defined(CONFIG_HLAN) ++ WM8(UART2, 0x6C) /* set DLL(baudrate 57600bps, 100MHz) */ ++ WM8(UART2_IER,0x00) /* set DLM(baudrate 57600bps, 100MHz) */ ++#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) ++ WM8(UART2, 0x90) /* set DLL(baudrate 57600bps, 133MHz) */ ++ WM8(UART2_IER,0x00) /* set DLM(baudrate 57600bps, 133MHz) */ ++#endif ++ WM8(UART2_LCR,0x03) /* set 8data, 1stop, non parity */ ++ WM8(UART2, 0x00) /* clear MCR */ ++ WM8(UART2_FCR,0x07) /* clear & enable FIFO */ ++#endif /* !defined (CFG_RAMBOOT) ++ ++ /* PCI Command Register initialize */ ++ lis r3, 0x8000 ++ ori r3, r3, 0x0004 ++ lis r4, 0xFEC0 ++ ori r4, r4, 0x0000 ++ stwbrx r4, 0, r3 ++ sync ++ isync ++ ++ li r6, 0x0006 ++ lis r5, 0xFEE0 ++ ori r5, r5, 0x0000 ++ sthbrx r5, 0, r6 ++ sync ++ isync ++ ++#if !defined(CFG_RAMBOOT) ++check_ram: ++ /* Wait 1 sec for AVR become enable */ ++ li r3,1000 ++ mulli r3,r3,1000 ++ mulli r4,r3,1000 /* nanoseconds */ ++ addi r4,r4,39 ++ li r5,40 /* 40ns if for 100 Mhz bus */ ++ divw r4,r4,r5 /* BUS ticks */ ++1: mftbu r5 ++ mftb r6 ++ mftbu r7 ++ cmp 0,r5,r7 ++ bne 1b /* Get [synced] base time */ ++ addc r9,r6,r4 /* Compute end time */ ++ addze r8,r5 ++2: mftbu r5 ++ cmp 0,r5,r8 ++ blt 2b ++ bgt 3f ++ mftb r6 ++ cmp 0,r6,r9 ++ blt 2b ++#if 1 ++3: ++#else ++ /* Check RAM */ ++ /* set start address(0x00000000) */ ++3: xor r4,r4,r4 ++ lis r5, RAM_SIZE@h ++ ori r5, r5, RAM_SIZE@l ++ lis r6, 0xaaaa /* mask pattern a */ ++ ori r6, r6, 0xaaaa ++ lis r7, 0x5555 /* mask pattern b */ ++ ori r7, r7, 0x5555 ++ lis r8, 0x0000 /* check step size */ ++ ori r8, r8, 0x0100 ++check_ram_loop: ++ cmp 0,r4,r5 ++ beq check_ram_end ++ stw r6,0(r4) ++ isync ++ lwz r3,0(r4) ++ isync ++ cmp 0,r3,r6 ++ bne ram_error ++ stw r7,0x00fc(r4) ++ isync ++ lwz r3,0x00fc(r4) ++ isync ++ cmp 0,r3,r7 ++ bne ram_error ++ add r4,r4,r8 ++ b check_ram_loop ++ram_error: ++#if defined(CONFIG_LAN) ++ WM8(UART1,0x39) /* ram error */ ++#elif defined(CONFIG_HGLAN) ||defined(CONFIG_HLAN) || defined(CONFIG_HTGL) ++ WM8(UART1,0x6F) /* ram error */ ++#endif ++ b ram_error ++check_ram_end: ++#endif /* #if 1 */ ++#endif /* !defined (CFG_RAMBOOT) */ ++ ++/* The instruction cache is enabled and the data cache is disabled */ ++ blr +diff -urN u-boot-86xx/board/linkstation/firminfo.h u-boot-86xx-kuro_clean/board/linkstation/firminfo.h +--- u-boot-86xx/board/linkstation/firminfo.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-86xx-kuro_clean/board/linkstation/firminfo.h 2006-11-06 22:05:38.000000000 +0100 +@@ -0,0 +1,27 @@ ++#define FIRMNAME_MAX 31 ++#define SUBVERSION_MAX 31 ++#define FIRMINFO_VER 1 ++ ++struct firminfo { ++ unsigned long info_ver; ++ unsigned long firmid; ++ char firmname[FIRMNAME_MAX+1]; ++ char subver[SUBVERSION_MAX+1]; ++ unsigned short ver_major; ++ unsigned short ver_minor; ++ unsigned short build; ++ char year; ++ char mon; ++ char day; ++ char hour; ++ char min; ++ char sec; ++ unsigned long size; ++ unsigned long chksum; ++ ++ unsigned long kernel_offset; ++ unsigned long kernel_size; ++ unsigned long initrd_offset; ++ unsigned long initrd_size; ++ } __attribute((aligned(4))); ++// ---------------------------------------------------- +diff -urN u-boot-86xx/board/linkstation/flash.c u-boot-86xx-kuro_clean/board/linkstation/flash.c +--- u-boot-86xx/board/linkstation/flash.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-86xx-kuro_clean/board/linkstation/flash.c 2006-11-06 22:05:38.000000000 +0100 +@@ -0,0 +1,893 @@ ++/* ++ * flash.c ++ * ++ * Flash device interface for LinkStation ++ * Supports CFI flash devices using the AMD standard command set ++ * ++ * Copyright (C) 2006 Mihai Georgin ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ * Based on the MTD code from the Linux kernel ++ * ++ * Based on include/melco/flashd.c (linux-2.4.17_mvl21-sandpoint) ++ * Copyright (C) 2001-2004 BUFFALO INC. ++ */ ++#include ++#include ++#include ++ ++#if 0 ++#define DEBUG_CFI ++#endif ++ ++#undef debug ++#ifdef DEBUG_CFI ++#define debug(fmt,args...) printf(fmt,##args) ++#else ++#define debug(fmt,args...) ++#endif /* DEBUG_CFI */ ++ ++#if CFG_MAX_FLASH_BANKS > 1 ++#error Only 1 flash bank supported ++#endif ++ ++#define perror(fmt,args...) printf("%s: ",__FUNCTION__);printf(fmt,##args) ++ ++#define MAX_ERASE_REGIONS 4 ++ ++#define P_ID_NONE 0 ++#define P_ID_INTEL_EXT 1 ++#define P_ID_AMD_STD 2 ++#define P_ID_INTEL_STD 3 ++#define P_ID_AMD_EXT 4 ++#define P_ID_MITSUBISHI_STD 256 ++#define P_ID_MITSUBISHI_EXT 257 ++#define P_ID_RESERVED 65535 ++ ++#define CFI_DEVICETYPE_X8 (8 / 8) ++#define CFI_DEVICETYPE_X16 (16 / 8) ++ ++#define FLASH_DATA_MASK 0xFF ++ ++#define FUJ_MANUFACT_LS (FUJ_MANUFACT & FLASH_DATA_MASK) ++#define STM_MANUFACT_LS (STM_MANUFACT & FLASH_DATA_MASK) ++#define MX_MANUFACT_LS (MX_MANUFACT & FLASH_DATA_MASK) ++ ++/* Unknown manufacturer */ ++#define FLASH_MAN_UNKNOWN 0xFFFF0000 ++ ++/* Fujitsu MBM29PL320MT which is using the same */ ++/* codes as the AMD Am29LV320MT "mirror" flash */ ++#define AMD_ID_MIRROR_LS (AMD_ID_MIRROR & FLASH_DATA_MASK) ++#define AMD_ID_LV320T_2_LS (AMD_ID_LV320T_2 & FLASH_DATA_MASK) ++#define AMD_ID_LV320T_3_LS (AMD_ID_LV320T_3 & FLASH_DATA_MASK) ++ ++/* ST Micro M29W320DT and M29W320DB */ ++#define STM_ID_29W320DT_LS (STM_ID_29W320DT & FLASH_DATA_MASK) ++#define STM_ID_29W320DB_LS (STM_ID_29W320DB & FLASH_DATA_MASK) ++ ++/* ST Micro M29DW324DT and M29DW324DB */ ++#define STM_ID_29W324DT_LS (STM_ID_29W324DT & FLASH_DATA_MASK) ++#define STM_ID_29W324DB_LS (STM_ID_29W324DB & FLASH_DATA_MASK) ++ ++/* Macronix MX29LV320T */ ++#define MX_ID_LV320T_LS (MX_ID_LV320T & FLASH_DATA_MASK) ++ ++/* Basic Query Structure */ ++struct cfi_ident { ++ __u8 qry[3]; ++ __u16 P_ID; ++ __u16 P_ADR; ++ __u16 A_ID; ++ __u16 A_ADR; ++ __u8 VccMin; ++ __u8 VccMax; ++ __u8 VppMin; ++ __u8 VppMax; ++ __u8 WordWriteTimeoutTyp; ++ __u8 BufWriteTimeoutTyp; ++ __u8 BlockEraseTimeoutTyp; ++ __u8 ChipEraseTimeoutTyp; ++ __u8 WordWriteTimeoutMax; ++ __u8 BufWriteTimeoutMax; ++ __u8 BlockEraseTimeoutMax; ++ __u8 ChipEraseTimeoutMax; ++ __u8 DevSize; ++ __u16 InterfaceDesc; ++ __u16 MaxBufWriteSize; ++ __u8 NumEraseRegions; ++ __u32 EraseRegionInfo[MAX_ERASE_REGIONS]; ++} __attribute__((packed)); ++ ++struct cfi_private { ++ __u32 base; ++ int device_type; ++ int addr_unlock1; ++ int addr_unlock2; ++ struct cfi_ident *cfiq; ++ int mfr; ++ int id[3]; /* Supports AMD MirrorBit flash */ ++ char *flash_name; ++ int wrd_wr_time; ++ int buf_wr_time; ++ int erase_time; ++ int (*blk_erase)(flash_info_t *info, int s_first, int s_last); ++ int (*blk_write)(flash_info_t *info, __u8 *buf, __u32 addr, int sz); ++}; ++ ++static inline __u8 cfi_read8(__u32 addr) ++{ ++ return (*(volatile __u8 *)(addr)); ++} ++ ++static inline void cfi_write8(__u8 val, __u32 addr) ++{ ++ *(volatile __u8 *)(addr) = val; ++ sync(); ++} ++ ++/* ++ * Sends a CFI command to a bank of flash for the given type. ++ * Returns the offset to the sent command ++ */ ++static inline __u32 cfi_cmd(__u8 cmd, __u32 cmd_addr, __u32 base, int type) ++{ ++ __u32 addr; ++ ++ addr = base + cmd_addr * type; ++ if (cmd_addr * type == 0x554) ++ ++addr; ++ ++ cfi_write8(cmd, addr); ++ ++ return addr - base; ++} ++ ++static inline __u8 cfi_read_query(__u32 addr) ++{ ++ return cfi_read8(addr); ++} ++ ++flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; ++static struct cfi_private cfis; ++static struct cfi_ident cfi_idents; ++static struct cfi_private *cfi; ++ ++static int cfi_probe_chip(struct cfi_private *cfi); ++static unsigned long cfi_amdstd_setup(struct cfi_private *cfi, int primary); ++static void print_cfi_ident(struct cfi_ident *); ++static int flash_amdstd_erase(flash_info_t *info, int s_first, int s_last); ++static int flash_amdstd_wbuff(flash_info_t *info, __u8 *buf, __u32 addr,int sz); ++static int flash_amdstd_wubyp(flash_info_t *info, __u8 *buf, __u32 addr,int sz); ++static int flash_amdstd_write(flash_info_t *info, __u8 *buf, __u32 addr,int sz); ++ ++ ++ ++unsigned long flash_init(void) ++{ ++ unsigned long flash_size; ++ __u16 type; ++ ++ debug("%s\n", __FUNCTION__); ++ ++ cfi = &cfis; ++ memset(cfi, 0, sizeof(struct cfi_private)); ++ ++ cfi->base = CFG_FLASH_BASE; ++ ++ /* Identify CFI chip */ ++ /* Probe for X8 device first */ ++ cfi->device_type = CFI_DEVICETYPE_X8; ++ if (cfi_probe_chip(cfi)) { ++ /* The probe didn't like it */ ++ /* so probe for X16/X8 device */ ++ cfi->device_type = CFI_DEVICETYPE_X16; ++ if (cfi_probe_chip(cfi)) { ++ /* The probe didn't like it */ ++ return 0UL; ++ } ++ } ++ ++ /* Check if it is AMD standard cmd set */ ++ type = cfi->cfiq->P_ID; ++ if (type == P_ID_AMD_STD) ++ flash_size = cfi_amdstd_setup(cfi, 1); ++ else { ++ perror("Primary cmd set is not AMD std. Trying alternate.\n"); ++ flash_size = 0; ++ } ++ if (!flash_size) { ++ type = cfi->cfiq->A_ID; ++ if (type == P_ID_AMD_STD) ++ flash_size = cfi_amdstd_setup(cfi, 0); ++ else { ++ perror("Alternate cmd set is not AMD std.\n"); ++ return 0UL; ++ } ++ } ++ ++ if (flash_size && flash_size == 4*1024*1024) { ++ /* Flash protection ON by default */ ++ flash_protect(FLAG_PROTECT_SET, cfi->base, cfi->base+flash_size-1, flash_info); ++ ++ return flash_size; ++ } ++ ++ if (flash_size) { ++ perror("Unsupported flash size: %d\n", flash_size); ++ } else { ++ perror("Vendor Command Set not supported\n"); ++ printf("Primary: 0x%04X, Alternate: 0x%04X\n", ++ cfi->cfiq->P_ID, cfi->cfiq->A_ID); ++ } ++ return 0UL; ++} ++ ++void flash_print_info(flash_info_t *info) ++{ ++ int i; ++ ++ debug("%s\n", __FUNCTION__); ++ ++ printf("Flash chip: %s\n\n", ++ cfi->flash_name?cfi->flash_name:"UNKNOWN"); ++ print_cfi_ident(cfi->cfiq); ++ printf("\nActual values used by U-Boot:\n"); ++ printf("Word write timeout: %6d ms\n", cfi->wrd_wr_time); ++ printf("Buffer write timeout: %6d ms\n", cfi->buf_wr_time); ++ printf("Sector erase timeout: %6d ms\n", cfi->erase_time); ++ printf("\nSize: %ld MiB in %d Sectors\n",info->size>>20,info->sector_count); ++ printf (" Sector Start Addresses:"); ++ for (i=0; isector_count; i++) { ++ if (!(i % 5)) ++ printf ("\n "); ++ printf (" %08lX%s", info->start[i], info->protect[i]?" (RO)" : " (RW)"); ++ } ++ printf ("\n"); ++} ++ ++int flash_erase(flash_info_t *info, int s_first, int s_last) ++{ ++ return (*(cfi->blk_erase))(info, s_first, s_last); ++} ++ ++int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) ++{ ++ return (*(cfi->blk_write))(info, src, addr, cnt); ++} ++ ++static int cfi_probe_chip(struct cfi_private *cfi) ++{ ++ int ofs_factor = cfi->device_type; ++ __u32 base = cfi->base; ++ int num_erase_regions, scount; ++ int i; ++ ++ debug("%s\n", __FUNCTION__); ++ ++ cfi_cmd(0xF0, 0x00, base, cfi->device_type); ++ cfi_cmd(0x98, 0x55, base, cfi->device_type); ++ ++ if (cfi_read8(base + ofs_factor * 0x10) != 'Q' || ++ cfi_read8(base + ofs_factor * 0x11) != 'R' || ++ cfi_read8(base + ofs_factor * 0x12) != 'Y') { ++ debug("Not a CFI flash\n"); ++ /* Put the chip back into read array mode */ ++ cfi_cmd(0xF0, 0x00, base, cfi->device_type); ++ return -1; ++ } ++ ++ num_erase_regions = cfi_read_query(base + 0x2C * ofs_factor); ++ if (!num_erase_regions) { ++ perror("No erase regions\n"); ++ /* Put the chip back into read read array mode */ ++ cfi_cmd(0xF0, 0x00, base, cfi->device_type); ++ return -1; ++ } ++ if (num_erase_regions > MAX_ERASE_REGIONS) { ++ perror("Number of erase regions (%d) > MAX_ERASE_REGIONS (%d)\n", ++ num_erase_regions, MAX_ERASE_REGIONS); ++ /* Put the chip back into read read array mode */ ++ cfi_cmd(0xF0, 0x00, base, cfi->device_type); ++ return -1; ++ } ++ ++ cfi->cfiq = &cfi_idents; ++ memset(cfi->cfiq, 0, sizeof(struct cfi_ident)); ++ debug("cfi->cfiq: 0x%08X\n", cfi->cfiq); ++ ++ /* Read the CFI info structure */ ++ for (i=0; i < sizeof(struct cfi_ident) + num_erase_regions * 4; i++) ++ ((__u8 *)cfi->cfiq)[i] = cfi_read_query(base + (0x10 + i) * ofs_factor); ++ ++ /* Do any necessary byteswapping */ ++ cfi->cfiq->P_ID = __le16_to_cpu(cfi->cfiq->P_ID); ++ cfi->cfiq->P_ADR = __le16_to_cpu(cfi->cfiq->P_ADR); ++ cfi->cfiq->A_ID = __le16_to_cpu(cfi->cfiq->A_ID); ++ cfi->cfiq->A_ADR = __le16_to_cpu(cfi->cfiq->A_ADR); ++ cfi->cfiq->InterfaceDesc = __le16_to_cpu(cfi->cfiq->InterfaceDesc); ++ cfi->cfiq->MaxBufWriteSize = __le16_to_cpu(cfi->cfiq->MaxBufWriteSize); ++ ++#if 0 ++ /* Dump the information therein */ ++ print_cfi_ident(cfi->cfiq); ++#endif ++ ++ scount = 0; ++ for (i=0; icfiq->NumEraseRegions; i++) { ++ cfi->cfiq->EraseRegionInfo[i] = __le32_to_cpu(cfi->cfiq->EraseRegionInfo[i]); ++ scount += (cfi->cfiq->EraseRegionInfo[i] & 0xFFFF) + 1; ++ debug(" Erase Region #%d: sector size 0x%4.4X bytes, %d sectors\n", ++ i, (cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xFF, ++ (cfi->cfiq->EraseRegionInfo[i] & 0xFFFF) + 1); ++ } ++ /* Put it back into Read Mode */ ++ cfi_cmd(0xF0, 0, base, cfi->device_type); ++ ++ if (scount > CFG_MAX_FLASH_SECT) { ++ perror("Number of sectors (%d) > CFG_MAX_FLASH_SECT (%d)\n", ++ scount, CFG_MAX_FLASH_SECT); ++ return -1; ++ } ++ ++ debug("Found x%d device in 8-bit mode\n", cfi->device_type*8); ++ ++ return 0; ++} ++ ++static char *vendorname(__u16 vendor) ++{ ++ switch (vendor) { ++ case P_ID_NONE: ++ return "None"; ++ case P_ID_INTEL_EXT: ++ return "Intel/Sharp Extended"; ++ case P_ID_AMD_STD: ++ return "AMD/Fujitsu Standard"; ++ case P_ID_INTEL_STD: ++ return "Intel/Sharp Standard"; ++ case P_ID_AMD_EXT: ++ return "AMD/Fujitsu Extended"; ++ case P_ID_MITSUBISHI_STD: ++ return "Mitsubishi Standard"; ++ case P_ID_MITSUBISHI_EXT: ++ return "Mitsubishi Extended"; ++ case P_ID_RESERVED: ++ return "Not Allowed / Reserved for Future Use"; ++ default: ++ return "Unknown"; ++ } ++} ++ ++static void print_cfi_ident(struct cfi_ident *cfip) ++{ ++ printf("CFI Query Results:\n"); ++ printf("Primary Vendor Command Set: 0x%4.4X (%s)\n", ++ cfip->P_ID, vendorname(cfip->P_ID)); ++ if (cfip->P_ADR) ++ printf("Primary Algorithm Table at 0x%4.4X\n", cfip->P_ADR); ++ else ++ printf("No Primary Algorithm Table\n"); ++ ++ printf("Alternate Vendor Command Set: 0x%4.4X (%s)\n", ++ cfip->A_ID, vendorname(cfip->A_ID)); ++ if (cfip->A_ADR) ++ printf("Alternate Algorithm Table at 0x%4.4X\n", cfip->A_ADR); ++ else ++ printf("No Alternate Algorithm Table\n"); ++ ++ printf("Vcc Min.: %d.%d V\n", cfip->VccMin >> 4, cfip->VccMin & 0xF); ++ printf("Vcc Max.: %d.%d V\n", cfip->VccMax >> 4, cfip->VccMax & 0xF); ++ if (cfip->VppMin) { ++ printf("Vpp Min.: %d.%d V\n", cfip->VppMin >> 4, cfip->VppMin & 0xF); ++ printf("Vpp Max.: %d.%d V\n", cfip->VppMax >> 4, cfip->VppMax & 0xF); ++ } ++ else ++ printf("No Vpp line\n"); ++ ++ printf("Typical byte/word write timeout: %d us\n", ++ 1<WordWriteTimeoutTyp); ++ printf("Maximum byte/word write timeout: %d us\n", ++ (1<WordWriteTimeoutMax) * (1<WordWriteTimeoutTyp)); ++ ++ if (cfip->BufWriteTimeoutTyp || cfip->BufWriteTimeoutMax) { ++ printf("Typical full buffer write timeout: %d us\n", ++ 1<BufWriteTimeoutTyp); ++ printf("Maximum full buffer write timeout: %d us\n", ++ (1<BufWriteTimeoutMax) * (1<BufWriteTimeoutTyp)); ++ } ++ else ++ printf("Full buffer write not supported\n"); ++ ++ printf("Typical block erase timeout: %d ms\n", ++ 1<BlockEraseTimeoutTyp); ++ printf("Maximum block erase timeout: %d ms\n", ++ (1<BlockEraseTimeoutMax) * (1<BlockEraseTimeoutTyp)); ++ if (cfip->ChipEraseTimeoutTyp || cfip->ChipEraseTimeoutMax) { ++ printf("Typical chip erase timeout: %d ms\n", ++ 1<ChipEraseTimeoutTyp); ++ printf("Maximum chip erase timeout: %d ms\n", ++ (1<ChipEraseTimeoutMax) * (1<ChipEraseTimeoutTyp)); ++ } ++ else ++ printf("Chip erase not supported\n"); ++ ++ printf("Device size: 0x%X bytes (%d MiB)\n", ++ 1 << cfip->DevSize, 1 << (cfip->DevSize - 20)); ++ printf("Flash Device Interface description: 0x%4.4X\n",cfip->InterfaceDesc); ++ switch(cfip->InterfaceDesc) { ++ case 0: ++ printf(" - x8-only asynchronous interface\n"); ++ break; ++ case 1: ++ printf(" - x16-only asynchronous interface\n"); ++ break; ++ case 2: ++ printf(" - x8 / x16 via BYTE# with asynchronous interface\n"); ++ break; ++ case 3: ++ printf(" - x32-only asynchronous interface\n"); ++ break; ++ case 65535: ++ printf(" - Not Allowed / Reserved\n"); ++ break; ++ default: ++ printf(" - Unknown\n"); ++ break; ++ } ++ printf("Max. bytes in buffer write: %d\n", 1 << cfip->MaxBufWriteSize); ++ printf("Number of Erase Block Regions: %d\n", cfip->NumEraseRegions); ++} ++ ++static unsigned long cfi_amdstd_setup(struct cfi_private *cfi, int primary) ++{ ++ flash_info_t *info = &flash_info[0]; ++ __u32 base = cfi->base; ++ int ofs_factor = cfi->device_type; ++ __u32 addr_et = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR; ++ __u8 major, minor, bootloc; ++ __u32 offset, ernum, ersize; ++ int i, j; ++ ++ /* Put the chip into read array mode */ ++ cfi_cmd(0xF0, 0x00, base, cfi->device_type); ++ /* Autoselect */ ++ cfi_cmd(0xAA, 0x555, base, cfi->device_type); ++ cfi_cmd(0x55, 0x2AA, base, cfi->device_type); ++ cfi_cmd(0x90, 0x555, base, cfi->device_type); ++ /* Read manufacturer and device id */ ++ cfi->mfr = cfi_read_query(base + 0x00 * ofs_factor); ++ if ((cfi->id[0] = cfi_read_query(base + 0x01 * ofs_factor)) == 0x7E) { ++ cfi->id[1] = cfi_read_query(base + 0x0E * ofs_factor); ++ cfi->id[2] = cfi_read_query(base + 0x0F * ofs_factor); ++ } ++ /* Put the chip into read array mode */ ++ cfi_cmd(0xF0, 0x00, base, cfi->device_type); ++ ++ /* Put the chip into read query mode */ ++ cfi_cmd(0x98, 0x55, base, cfi->device_type); ++ /* Find the boot block location and swap the erase regions as necessary */ ++ major = cfi_read_query(base + (addr_et + 3) * ofs_factor); ++ minor = cfi_read_query(base + (addr_et + 4) * ofs_factor); ++ debug(" Amd/Fujitsu Extended Query Table v%c.%c at 0x%4.4X\n", ++ major, minor, addr_et); ++ ++ if (((major << 8) | minor) < 0x3131) { ++ /* CFI version 1.0 => don't trust bootloc */ ++ if (cfi->id[0] & 0x80) { ++ printf("Device ID is 0x%02X. Assuming broken CFI table.\n", ++ cfi->id[0]); ++ bootloc = 3; /* top boot */ ++ } else ++ bootloc = 2; /* bottom boot */ ++ } else ++ bootloc = cfi_read_query(base + (addr_et + 0xF) * ofs_factor); ++ ++ if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) { ++ debug("Top boot block. Swapping erase regions.\n"); ++ for (i=0; icfiq->NumEraseRegions / 2; i++) { ++ int j = (cfi->cfiq->NumEraseRegions-1)-i; ++ __u32 swap; ++ ++ swap = cfi->cfiq->EraseRegionInfo[i]; ++ cfi->cfiq->EraseRegionInfo[i] = cfi->cfiq->EraseRegionInfo[j]; ++ cfi->cfiq->EraseRegionInfo[j] = swap; ++ } ++ } ++ ++ /* Put the chip into read array mode */ ++ cfi_cmd(0xF0, 0x00, base, cfi->device_type); ++ ++ switch (cfi->device_type) { ++ case CFI_DEVICETYPE_X8: ++ /* X8 chip */ ++ cfi->addr_unlock1 = 0x555; ++ cfi->addr_unlock2 = 0x2AA; ++ break; ++ case CFI_DEVICETYPE_X16: ++ /* X16 chip in X8 mode */ ++ cfi->addr_unlock1 = 0xAAA; ++ cfi->addr_unlock2 = 0x555; ++ break; ++ default: ++ perror("Unsupported device type %d\n", cfi->device_type); ++ return 0UL; ++ } ++ ++ cfi->wrd_wr_time = 1 << cfi->cfiq->WordWriteTimeoutTyp; ++ cfi->wrd_wr_time *= 1 << cfi->cfiq->WordWriteTimeoutMax; ++ /* Word write time is in us, convert to ms */ ++ cfi->wrd_wr_time = cfi->wrd_wr_time / 1000 + 1; ++ if (cfi->wrd_wr_time == 1) ++ /* Account for the timer resolution which is 1 ms */ ++ cfi->wrd_wr_time = 2; ++ cfi->buf_wr_time = 1 << cfi->cfiq->BufWriteTimeoutTyp; ++ cfi->buf_wr_time *= 1 << cfi->cfiq->BufWriteTimeoutMax; ++ /* Buffer write time is in us, convert to ms */ ++ cfi->buf_wr_time = cfi->buf_wr_time / 1000 + 1; ++ if (cfi->buf_wr_time == 1) ++ /* Account for the timer resolution which is 1 ms */ ++ cfi->buf_wr_time = 2; ++ cfi->erase_time = 1 << cfi->cfiq->BlockEraseTimeoutTyp; ++ cfi->erase_time *= 1 << cfi->cfiq->BlockEraseTimeoutMax; ++ ++ info->size = (1 << cfi->cfiq->DevSize); ++ ++ info->sector_count = 0; ++ offset = CFG_FLASH_BASE; ++ for (i=0; i < cfi->cfiq->NumEraseRegions; i++) { ++ ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xFF); ++ ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xFFFF) + 1; ++ ++ for (j=0; j < ernum; j++) { ++ info->start[info->sector_count + j] = offset; ++ offset += ersize; ++ } ++ ++ info->sector_count += ernum; ++ } ++ ++ switch (cfi->mfr) { ++ case FUJ_MANUFACT_LS: ++ info->flash_id = FLASH_MAN_FUJ; ++ switch (cfi->id[0]) { ++ case AMD_ID_MIRROR_LS: ++ if (cfi->id[1] == AMD_ID_LV320T_2_LS && ++ cfi->id[2] == AMD_ID_LV320T_3_LS) { ++ info->flash_id += FLASH_AMLV320T; ++ cfi->blk_write = flash_amdstd_wbuff; ++ cfi->flash_name = "FUJITSU MBM29PL32TM"; ++ } else ++ info->flash_id += FLASH_UNKNOWN; ++ break; ++ default: ++ info->flash_id += FLASH_UNKNOWN; ++ break; ++ } ++ break; ++ case STM_MANUFACT_LS: ++ info->flash_id = FLASH_MAN_STM; ++ switch (cfi->id[0]) { ++ case STM_ID_29W320DT_LS: ++ info->flash_id += FLASH_STMW320DT; ++ cfi->blk_write = flash_amdstd_wubyp; ++ cfi->flash_name = "STMICRO M29W320DT"; ++ break; ++ case STM_ID_29W320DB_LS: ++ info->flash_id += FLASH_STMW320DB; ++ cfi->blk_write = flash_amdstd_wubyp; ++ cfi->flash_name = "STMICRO M29W320DB"; ++ break; ++ case STM_ID_29W324DT_LS: ++ info->flash_id += FLASH_STMW324DT; ++ cfi->blk_write = flash_amdstd_wubyp; ++ cfi->flash_name = "STMICRO M29W324DT"; ++ break; ++ case STM_ID_29W324DB_LS: ++ info->flash_id += FLASH_STMW324DB; ++ cfi->blk_write = flash_amdstd_wubyp; ++ cfi->flash_name = "STMICRO M29W324DB"; ++ break; ++ default: ++ info->flash_id += FLASH_UNKNOWN; ++ break; ++ } ++ break; ++ case MX_MANUFACT_LS: ++ info->flash_id = FLASH_MAN_MX; ++ switch (cfi->id[0]) { ++ case MX_ID_LV320T_LS: ++ info->flash_id += FLASH_MXLV320T; ++ cfi->blk_write = flash_amdstd_write; ++ cfi->flash_name = "MXIC MX29LV320T"; ++ break; ++ default: ++ info->flash_id += FLASH_UNKNOWN; ++ break; ++ } ++ break; ++ default: ++ info->flash_id = FLASH_AMD_COMP; ++ break; ++ } ++ ++ if ((info->flash_id & FLASH_TYPEMASK) == FLASH_UNKNOWN) { ++ /* Unknown but supported CFI flash */ ++ cfi->flash_name = NULL; ++ if (cfi->cfiq->MaxBufWriteSize) ++ cfi->blk_write = flash_amdstd_wbuff; ++ else ++ cfi->blk_write = flash_amdstd_write; ++ } ++ ++ cfi->blk_erase = flash_amdstd_erase; ++ ++ return info->size; ++} ++ ++#define BIT(x) (1<base; ++ __u8 *faddr; ++ long i; ++ ++ debug("%s\n", __FUNCTION__); ++ ++ faddr = (__u8 *)addr; ++ for(i=0; i < sz; i++) { ++ if(faddr[i] != buf[i]) { ++ printf("Flash Write verify fail at %08x. ", &faddr[i]); ++ printf("Expecting: %02X, Actual: %02X\n", faddr[i], buf[i]); ++ printf("Retrying..."); ++ cfi_cmd(0xAA, cfi->addr_unlock1, base, CFI_DEVICETYPE_X8); ++ cfi_cmd(0x55, cfi->addr_unlock2, base, CFI_DEVICETYPE_X8); ++ cfi_cmd(0xA0, cfi->addr_unlock1, base, CFI_DEVICETYPE_X8); ++ cfi_write8(buf[i], (__u32)&faddr[i]); ++ if (flash_amdstd_state((__u32)&faddr[i], buf[i], cfi->wrd_wr_time)) { ++ printf("failed again\n"); ++ cfi_cmd(0xF0, 0, base, CFI_DEVICETYPE_X8); ++ return 1; ++ } else ++ printf("suceeded\n"); ++ } ++ } ++ return 0; ++} ++ ++/* ++ * Erase flash sectors ++ */ ++static int flash_amdstd_erase(flash_info_t *info, int s_first, int s_last) ++{ ++ int prot, sect, nsect, flag; ++ __u32 l_sect; ++ __u32 base = cfi->base; ++ ++ debug("%s\n", __FUNCTION__); ++ ++ if (!info->size) { ++ printf ("Flash erase: Can't erase unsupported flash\n"); ++ return 1; ++ } ++ ++ if (s_first < 0 || s_first > s_last || ++ s_first > (info->sector_count - 1) || ++ s_last > (info->sector_count - 1)) { ++ printf ("Flash erase: no sectors to erase\n"); ++ return 1; ++ } ++ ++ printf("\nFlash erase: first = %d @ 0x%08lx\n", ++ s_first, info->start[s_first]); ++ printf(" last = %d @ 0x%08lx\n", s_last, info->start[s_last]); ++ ++ nsect = s_last - s_first + 1; ++ for (prot = 0, sect=s_first; sect<=s_last; ++sect) ++ if (info->protect[sect]) ++ prot++; ++ if (prot) { ++ if (prot == nsect) { ++ printf("Warning: All requested sectors are protected!\n"); ++ printf(" No sectors to erase\n"); ++ return 1; ++ } ++ else ++ printf("Warning: %d protected sectors will not be erased!\n", prot); ++ } ++ cfi_cmd(0xF0, 0x00, base, CFI_DEVICETYPE_X8); ++ udelay(1000); ++ ++ /* Disable interrupts which might cause a timeout here */ ++ flag = disable_interrupts(); ++ ++ cfi_cmd(0xAA, cfi->addr_unlock1, base, CFI_DEVICETYPE_X8); ++ cfi_cmd(0x55, cfi->addr_unlock2, base, CFI_DEVICETYPE_X8); ++ cfi_cmd(0x80, cfi->addr_unlock1, base, CFI_DEVICETYPE_X8); ++ cfi_cmd(0xAA, cfi->addr_unlock1, base, CFI_DEVICETYPE_X8); ++ cfi_cmd(0x55, cfi->addr_unlock2, base, CFI_DEVICETYPE_X8); ++ for (sect = s_first; sect <= s_last; sect++) ++ if (!info->protect[sect]) { ++ l_sect = info->start[sect]; ++ cfi_write8(0x30, l_sect); ++ } ++ /* Erase begins 50us after the last sector address */ ++ udelay(50); ++ ++ /* All erase commands sent, enable interrupts */ ++ if (flag) ++ enable_interrupts(); ++ ++ if (flash_amdstd_state(l_sect, 0xff, cfi->erase_time * nsect)) { ++ printf("Flash erase: Timeout\n"); ++ cfi_cmd(0xF0, 0x00, base, CFI_DEVICETYPE_X8); ++ return 1; ++ } ++ printf("Flash erase: Done\n"); ++ return 0; ++} ++ ++/* ++ * Write to flash using Write Buffer programming ++ */ ++static int flash_amdstd_wbuff(flash_info_t *info, __u8 *buf, __u32 addr, int sz) ++{ ++ __u32 base = cfi->base; ++ __u32 wbufsz; ++ __u32 size, wsize, waddr, saddr; ++ __u8 *wbuf; ++ int i; ++ ++ debug("%s\n", __FUNCTION__); ++ ++ size = sz; ++ wbuf = buf; ++ wbufsz = 1 << cfi->cfiq->MaxBufWriteSize; ++ ++ waddr = (addr + wbufsz - 1) & ~(wbufsz - 1); ++ if (waddr > addr) ++ wsize = waddr-addr; ++ else ++ wsize = wbufsz; ++ if (wsize > size) ++ wsize = size; ++ waddr = addr; ++ ++ while (size > 0) { ++ for (i = 0; i < info->sector_count; i++) ++ if (waddr < info->start[i]) ++ break; ++ saddr = info->start[i-1]; ++ ++ cfi_cmd(0xAA, cfi->addr_unlock1, base, CFI_DEVICETYPE_X8); ++ cfi_cmd(0x55, cfi->addr_unlock2, base, CFI_DEVICETYPE_X8); ++ cfi_write8(0x25, saddr); ++ cfi_write8(wsize-1, saddr); ++ for (i = 0; i < wsize; i++) ++ cfi_write8(*wbuf++, waddr++); ++ cfi_write8(0x29, saddr); ++ ++ if (flash_amdstd_state(waddr-1, *(wbuf-1), cfi->buf_wr_time)) { ++ printf("Flash write buffer: Timeout\n"); ++ cfi_cmd(0xF0, 0x00, base, CFI_DEVICETYPE_X8); ++ return 1; ++ } ++ ++ size -= wsize; ++ if ((wsize = wbufsz) > size) ++ wsize = size; ++ } ++ ++ return flash_amdstd_vrfy(info, buf, addr, sz); ++} ++ ++/* ++ * Write to flash using Unlock Bypass command sequence ++ */ ++static int flash_amdstd_wubyp(flash_info_t *info, __u8 *buf, __u32 addr, int sz) ++{ ++ __u32 base = cfi->base; ++ __u32 waddr; ++ long i; ++ ++ debug("%s\n", __FUNCTION__); ++ ++ waddr = addr; ++ ++ cfi_cmd(0xAA, cfi->addr_unlock1, base, CFI_DEVICETYPE_X8); ++ cfi_cmd(0x55, cfi->addr_unlock2, base, CFI_DEVICETYPE_X8); ++ cfi_cmd(0x20, cfi->addr_unlock1, base, CFI_DEVICETYPE_X8); ++ ++ for(i=0; i < sz; i++) { ++ cfi_write8(0xA0, waddr); ++ cfi_write8(buf[i], waddr); ++ if (flash_amdstd_state(waddr, buf[i], cfi->wrd_wr_time)) { ++ printf("Flash unlock bypass write: Timeout\n"); ++ cfi_cmd(0x90, 0, base, CFI_DEVICETYPE_X8); ++ cfi_cmd(0x00, 0, base, CFI_DEVICETYPE_X8); ++ cfi_cmd(0xF0, 0, base, CFI_DEVICETYPE_X8); ++ return 1; ++ } ++ waddr++; ++ } ++ cfi_cmd(0x90, 0, base, CFI_DEVICETYPE_X8); ++ cfi_cmd(0x00, 0, base, CFI_DEVICETYPE_X8); ++ cfi_cmd(0xF0, 0, base, CFI_DEVICETYPE_X8); ++ ++ return flash_amdstd_vrfy(info, buf, addr, sz); ++} ++ ++/* ++ * Write to flash using Word/Byte Program command sequence ++ */ ++static int flash_amdstd_write(flash_info_t *info, __u8 *buf, __u32 addr, int sz) ++{ ++ __u32 base = cfi->base; ++ __u32 waddr; ++ long i; ++ ++ debug("%s\n", __FUNCTION__); ++ ++ waddr = addr; ++ ++ cfi_cmd(0xF0, 0, base, CFI_DEVICETYPE_X8); ++ for (i = 0; i < sz; i++) { ++ cfi_cmd(0xAA, cfi->addr_unlock1, base, CFI_DEVICETYPE_X8); ++ cfi_cmd(0x55, cfi->addr_unlock2, base, CFI_DEVICETYPE_X8); ++ cfi_cmd(0xA0, cfi->addr_unlock1, base, CFI_DEVICETYPE_X8); ++ cfi_write8(buf[i], waddr); ++ if (flash_amdstd_state(waddr, buf[i], cfi->wrd_wr_time)) { ++ printf("Flash write: Timeout\n"); ++ cfi_cmd(0xF0, 0, base, CFI_DEVICETYPE_X8); ++ return 1; ++ } ++ waddr++; ++ } ++ cfi_cmd(0xF0, 0, base, CFI_DEVICETYPE_X8); ++ ++ return flash_amdstd_vrfy(info, buf, addr, sz); ++} ++ ++/* vim: set ts=4: */ +diff -urN u-boot-86xx/board/linkstation/hwctl.c u-boot-86xx-kuro_clean/board/linkstation/hwctl.c +--- u-boot-86xx/board/linkstation/hwctl.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-86xx-kuro_clean/board/linkstation/hwctl.c 2006-11-06 22:05:38.000000000 +0100 +@@ -0,0 +1,258 @@ ++/* ++ * hwctl.c ++ * ++ * LinkStation HW Control Driver ++ * ++ * Copyright (C) 2001-2004 BUFFALO INC. ++ * ++ * This software may be used and distributed according to the terms of ++ * the GNU General Public License (GPL), incorporated herein by reference. ++ * Drivers based on or derived from this code fall under the GPL and must ++ * retain the authorship, copyright and license notice. This file is not ++ * a complete program and may only be used when the entire operating ++ * system is licensed under the GPL. ++ * ++ */ ++ ++#include ++#include ++#include ++ ++#define mdelay(n) udelay((n)*1000) ++ ++#define AVR_PORT CFG_NS16550_COM2 ++extern void udelay(unsigned long usec); ++ ++ ++// output BYTE data ++static inline void out_b(volatile unsigned char *addr, int val) ++{ ++ __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); ++} ++ ++#if 0 ++// PWR,DISK_FULL/STATUS,DIAG LED controll ++void blink_led(unsigned char state) ++{ ++#ifdef CONFIG_HTGL ++ switch (state) ++ { ++ case FLASH_CLEAR_START: ++ case FLASH_UPDATE_START: ++ out_b(AVR_PORT, 0x61); ++ out_b(AVR_PORT, 0x61); ++ out_b(AVR_PORT, 0x38); ++ out_b(AVR_PORT, 0x30); ++ out_b(AVR_PORT, 0x34); ++ out_b(AVR_PORT, 0x31); ++ mdelay(10); ++ out_b(AVR_PORT, 0x61); ++ out_b(AVR_PORT, 0x61); ++ out_b(AVR_PORT, 0x38); ++ out_b(AVR_PORT, 0x31); ++ out_b(AVR_PORT, 0x34); ++ out_b(AVR_PORT, 0x31); ++ mdelay(10); ++ out_b(AVR_PORT, 0x71); ++ out_b(AVR_PORT, 0x71); ++// out_b(AVR_PORT, 0x71); ++// out_b(AVR_PORT, 0x71); ++ mdelay(10); ++ out_b(AVR_PORT, 0x73); ++ out_b(AVR_PORT, 0x73); ++// out_b(AVR_PORT, 0x73); ++// out_b(AVR_PORT, 0x73); ++ mdelay(10); ++ break; ++ case FLASH_CLEAR_END: ++ case FLASH_UPDATE_END: ++ out_b(AVR_PORT, 0x70); ++ out_b(AVR_PORT, 0x70); ++// out_b(AVR_PORT, 0x70); ++// out_b(AVR_PORT, 0x70); ++ mdelay(10); ++ out_b(AVR_PORT, 0x72); ++ out_b(AVR_PORT, 0x72); ++// out_b(AVR_PORT, 0x72); ++// out_b(AVR_PORT, 0x72); ++ mdelay(10); ++ break; ++ case RAID_RESYNC_START: ++ break; ++ case RAID_RESYNC_END: ++ break; ++ default: ++ out_b(AVR_PORT, state); ++ out_b(AVR_PORT, state); ++ out_b(AVR_PORT, state); ++ out_b(AVR_PORT, state); ++ break; ++ } ++#else ++ out_b(AVR_PORT, state); ++ out_b(AVR_PORT, state); ++ out_b(AVR_PORT, state); ++ out_b(AVR_PORT, state); ++#endif ++ ++} ++#endif ++ ++// 2005.5.10 BUFFALO add ++//-------------------------------------------------------------- ++static inline void miconCntl_SendUart(unsigned char dat) ++{ ++ out_b((char *)AVR_PORT, dat); ++ udelay(1000); ++} ++ ++//-------------------------------------------------------------- ++void miconCntl_SendCmd(unsigned char dat) ++{ ++ int i; ++ ++ for (i=0; i<4; i++){ ++ miconCntl_SendUart(dat); ++ } ++} ++ ++//-------------------------------------------------------------- ++void miconCntl_FanLow(void) ++{ ++ debug("%s\n",__FUNCTION__); ++#ifdef CONFIG_HTGL ++ miconCntl_SendCmd(0x5C); ++#endif ++} ++//-------------------------------------------------------------- ++void miconCntl_FanHigh(void) ++{ ++ debug("%s\n",__FUNCTION__); ++#ifdef CONFIG_HTGL ++ miconCntl_SendCmd(0x5D); ++#endif ++} ++ ++//-------------------------------------------------------------- ++//1000Mbps ++void miconCntl_Eth1000M(int up) ++{ ++ debug("%s (%d)\n",__FUNCTION__,up); ++#ifdef CONFIG_HTGL ++ if (up){ ++ miconCntl_SendCmd(0x93); ++ }else{ ++ miconCntl_SendCmd(0x92); ++ } ++#else ++ if (up){ ++ miconCntl_SendCmd(0x5D); ++ }else{ ++ miconCntl_SendCmd(0x5C); ++ } ++#endif ++} ++//-------------------------------------------------------------- ++//100Mbps ++void miconCntl_Eth100M(int up) ++{ ++ debug("%s (%d)\n",__FUNCTION__,up); ++#ifdef CONFIG_HTGL ++ if (up){ ++ miconCntl_SendCmd(0x91); ++ }else{ ++ miconCntl_SendCmd(0x90); ++ } ++#else ++ if (up){ ++ miconCntl_SendCmd(0x5C); ++ } ++#endif ++} ++//-------------------------------------------------------------- ++//10Mbps ++void miconCntl_Eth10M(int up) ++{ ++ debug("%s (%d)\n",__FUNCTION__,up); ++#ifdef CONFIG_HTGL ++ if (up){ ++ miconCntl_SendCmd(0x8F); ++ }else{ ++ miconCntl_SendCmd(0x8E); ++ } ++#else ++ if (up){ ++ miconCntl_SendCmd(0x5C); ++ } ++#endif ++} ++//-------------------------------------------------------------- ++//�������� ++void miconCntl_5f(void) ++{ ++ debug("%s\n",__FUNCTION__); ++ miconCntl_SendCmd(0x5F); ++ mdelay(100); ++} ++ ++//-------------------------------------------------------------- ++// "reboot start" signal ++void miconCntl_Reboot(void) ++{ ++ debug("%s\n",__FUNCTION__); ++ miconCntl_SendCmd(0x43); ++} ++#if 0 ++//-------------------------------------------------------------- ++// Raid recovery start ++void miconCntl_RadiRecovery(void) ++{ ++ debug("%s\n",__FUNCTION__); ++#ifdef CONFIG_HTGL ++ miconCntl_SendUart(0x61); // a ++ miconCntl_SendUart(0x61); // a ++ miconCntl_SendUart(0x38); // 8 ++ miconCntl_SendUart(0x30); // 0 ++ miconCntl_SendUart(0x34); // 4 ++ miconCntl_SendUart(0x31); // 1 ++ miconCntl_SendCmd(0x71); // q ++#endif ++} ++//-------------------------------------------------------------- ++// Raid recovery finish ++void miconCntl_RadiRecoveryFin(void) ++{ ++ debug("%s\n",__FUNCTION__); ++#ifdef CONFIG_HTGL ++ miconCntl_SendCmd(0x70); ++#endif ++} ++#endif ++ ++// --------------------------------------------------------------- ++// Disable watchdog timer ++void miconCntl_DisWDT(void) ++{ ++ debug("%s\n",__FUNCTION__); ++ miconCntl_SendCmd(0x41); // A ++ miconCntl_SendCmd(0x46); // F ++ miconCntl_SendCmd(0x4A); // J ++ miconCntl_SendCmd(0x3E); // > ++ miconCntl_SendCmd(0x56); // V ++ miconCntl_SendCmd(0x3E); // > ++ miconCntl_SendCmd(0x5A); // Z ++ miconCntl_SendCmd(0x56); // V ++ miconCntl_SendCmd(0x4B); // K ++} ++// --------------------------------------------------------------- ++// U-Boot calls this function ++int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ++{ ++ disable_interrupts(); ++ miconCntl_Reboot(); ++ while (1) ++ miconCntl_SendUart(0x47); /* Wait for reboot */ ++ ++} ++ ++/* vim: set ts=4: */ +diff -urN u-boot-86xx/board/linkstation/ide.c u-boot-86xx-kuro_clean/board/linkstation/ide.c +--- u-boot-86xx/board/linkstation/ide.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-86xx-kuro_clean/board/linkstation/ide.c 2006-11-06 22:05:38.000000000 +0100 +@@ -0,0 +1,101 @@ ++/* ++ * (C) Copyright 2000 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++/* ide.c - ide support functions */ ++ ++ ++#include ++ ++#ifdef CFG_CMD_IDE ++#include ++#include ++#include ++ ++#define IT8212_PCI_CpuCONTROL 0x5e ++#define IT8212_PCI_PciModeCONTROL 0x50 ++#define IT8212_PCI_IdeIoCONFIG 0x40 ++#define IT8212_PCI_IdeBusSkewCONTROL 0x4c ++#define IT8212_PCI_IdeDrivingCURRENT 0x42 ++ ++extern ulong ide_bus_offset[CFG_IDE_MAXBUS]; ++extern struct pci_controller hose; ++ ++int ide_preinit (void) ++{ ++ int status; ++ pci_dev_t devbusfn; ++ int l; ++ ++ status = 1; ++ for (l = 0; l < CFG_IDE_MAXBUS; l++) { ++ ide_bus_offset[l] = -ATA_STATUS; ++ } ++ devbusfn = pci_find_device (PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, 0); ++ if (devbusfn == -1) ++ devbusfn = pci_find_device (PCI_VENDOR_ID_ITE,PCI_DEVICE_ID_ITE_8212,0); ++ if (devbusfn != -1) { ++ status = 0; ++ ++ pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, ++ (u32 *) &ide_bus_offset[0]); ++ ide_bus_offset[0] &= 0xfffffffe; ++ ide_bus_offset[0] = pci_hose_bus_to_phys(&hose, ++ ide_bus_offset[0] & 0xfffffffe, ++ PCI_REGION_IO); ++ pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2, ++ (u32 *) &ide_bus_offset[1]); ++ ide_bus_offset[1] &= 0xfffffffe; ++ ide_bus_offset[1] = pci_hose_bus_to_phys(&hose, ++ ide_bus_offset[1] & 0xfffffffe, ++ PCI_REGION_IO); ++ } ++ ++ if (pci_find_device (PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8212, 0) != -1) { ++ pci_write_config_byte(devbusfn, IT8212_PCI_CpuCONTROL, 0x01); ++ pci_write_config_byte(devbusfn, IT8212_PCI_PciModeCONTROL, 0x00); ++ pci_write_config_word(devbusfn, PCI_COMMAND, 0x0047); ++#ifdef CONFIG_IT8212_SECONDARY_ENABLE ++ pci_write_config_word(devbusfn, IT8212_PCI_IdeIoCONFIG, 0xA0F3); ++#else ++ pci_write_config_word(devbusfn, IT8212_PCI_IdeIoCONFIG, 0x8031); ++#endif ++ pci_write_config_dword(devbusfn, IT8212_PCI_IdeBusSkewCONTROL, 0x02040204); ++// __LS_COMMENT__ BUFFALO changed 2004.11.10 changed for EMI ++ pci_write_config_byte(devbusfn, IT8212_PCI_IdeDrivingCURRENT, 0x36); // 10mA ++// pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x09); // 4mA ++// pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x12); // 6mA ++// pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x24); // 6mA,2mA ++// pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x2D); // 8mA,4mA ++ pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x00); ++ } ++ ++ return (status); ++} ++ ++void ide_set_reset (int flag) { ++ return; ++} ++ ++#endif /* of CONFIG_CMDS_IDE */ ++ ++/* vim: set ts=4: */ +diff -urN u-boot-86xx/board/linkstation/linkstation.c u-boot-86xx-kuro_clean/board/linkstation/linkstation.c +--- u-boot-86xx/board/linkstation/linkstation.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-86xx-kuro_clean/board/linkstation/linkstation.c 2006-11-06 22:05:38.000000000 +0100 +@@ -0,0 +1,127 @@ ++/* ++ * linkstation.c ++ * ++ * Misc LinkStation specific functions ++ * ++ * Copyright (C) 2006 Mihai Georgin ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_PCI ++#include ++#endif ++ ++extern void init_AVR_DUART(void); ++extern void hw_watchdog_reset(void); ++ ++int checkboard (void) ++{ ++ DECLARE_GLOBAL_DATA_PTR; ++ ulong busfreq = get_bus_freq (0); ++ char buf[32]; ++ char *p; ++ bd_t *bd = gd->bd; ++ ++ init_AVR_DUART(); ++ hw_watchdog_reset(); ++ ++ if ((p = getenv ("console_nr")) != NULL) { ++ unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3; ++ ++ bd->bi_baudrate &= ~3; ++ bd->bi_baudrate |= con_nr & 3; ++ } ++ return 0; ++} ++ ++long int initdram (int board_type) ++{ ++ return (get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE)); ++} ++ ++/* ++ * Initialize PCI Devices ++ */ ++#ifdef CONFIG_PCI ++ ++#ifndef CONFIG_PCI_PNP ++ ++static struct pci_config_table pci_linkstation_config_table[] = { ++ /* vendor, device, class */ ++ /* bus, dev, func */ ++ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, ++ PCI_ANY_ID, 0x0b, 0, /* AN983B or RTL8110S */ ++ /* ethernet controller */ ++ pci_cfgfunc_config_device, { PCI_ETH_IOADDR, ++ PCI_ETH_MEMADDR, ++ PCI_COMMAND_IO | ++ PCI_COMMAND_MEMORY | ++ PCI_COMMAND_MASTER }}, ++ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, ++ PCI_ANY_ID, 0x0c, 0, /* SII680 or IT8211AF */ ++ /* ide controller */ ++ pci_cfgfunc_config_device, { PCI_IDE_IOADDR, ++ PCI_IDE_MEMADDR, ++ PCI_COMMAND_IO | ++ PCI_COMMAND_MEMORY | ++ PCI_COMMAND_MASTER }}, ++ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, ++ PCI_ANY_ID, 0x0e, 0, /* D720101 USB controller, 1st USB 1.1 */ ++ pci_cfgfunc_config_device, { PCI_USB0_IOADDR, ++ PCI_USB0_MEMADDR, ++ PCI_COMMAND_MEMORY | ++ PCI_COMMAND_MASTER }}, ++ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, ++ PCI_ANY_ID, 0x0e, 1, /* D720101 USB controller, 2nd USB 1.1 */ ++ pci_cfgfunc_config_device, { PCI_USB1_IOADDR, ++ PCI_USB1_MEMADDR, ++ PCI_COMMAND_MEMORY | ++ PCI_COMMAND_MASTER }}, ++ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, ++ PCI_ANY_ID, 0x0e, 2, /* D720101 USB controller, USB 2.0 */ ++ pci_cfgfunc_config_device, { PCI_USB2_IOADDR, ++ PCI_USB2_MEMADDR, ++ PCI_COMMAND_MEMORY | ++ PCI_COMMAND_MASTER }}, ++ { } ++}; ++#endif ++ ++struct pci_controller hose = { ++#ifndef CONFIG_PCI_PNP ++ config_table:pci_linkstation_config_table, ++#endif ++}; ++ ++void pci_init_board (void) ++{ ++ pci_mpc824x_init (&hose); ++ ++ /* Reset USB 1.1 */ ++ out_le32(PCI_USB0_MEMADDR+8, 1); ++ out_le32(PCI_USB1_MEMADDR+8, 1); ++ ++} ++#endif /* CONFIG_PCI */ ++ ++/* vim: set ts=4: */ +diff -urN u-boot-86xx/board/linkstation/nc.sh u-boot-86xx-kuro_clean/board/linkstation/nc.sh +--- u-boot-86xx/board/linkstation/nc.sh 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-86xx-kuro_clean/board/linkstation/nc.sh 2006-11-06 22:05:38.000000000 +0100 +@@ -0,0 +1,10 @@ ++#! /bin/bash ++ ++[ $# = 1 ] || { echo "Usage: $0 target_ip" >&2 ; exit 1 ; } ++TARGET_IP=$1 ++ ++stty -icanon -echo intr ^T ++#nc -u -l -p 6666 < /dev/null & ++nc -u -p 6666 -v -v ${TARGET_IP} 6666 ++stty icanon echo intr ^C ++ +diff -urN u-boot-86xx/board/linkstation/u-boot.lds u-boot-86xx-kuro_clean/board/linkstation/u-boot.lds +--- u-boot-86xx/board/linkstation/u-boot.lds 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-86xx-kuro_clean/board/linkstation/u-boot.lds 2006-11-06 22:05:38.000000000 +0100 +@@ -0,0 +1,138 @@ ++/* ++ * (C) Copyright 2001 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_ARCH(powerpc) ++/* ++SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); SEARCH_DIR(/usr/lib/gcc-lib/ppc-linux/3.3.3); ++*/ ++/* Do we need any of these for elf? ++ __DYNAMIC = 0; */ ++SECTIONS ++{ ++ /* Read-only sections, merged into text segment: */ ++ . = + SIZEOF_HEADERS; ++ .interp : { *(.interp) } ++ .hash : { *(.hash) } ++ .dynsym : { *(.dynsym) } ++ .dynstr : { *(.dynstr) } ++ .rel.text : { *(.rel.text) } ++ .rela.text : { *(.rela.text) } ++ .rel.data : { *(.rel.data) } ++ .rela.data : { *(.rela.data) } ++ .rel.rodata : { *(.rel.rodata) } ++ .rela.rodata : { *(.rela.rodata) } ++ .rel.got : { *(.rel.got) } ++ .rela.got : { *(.rela.got) } ++ .rel.ctors : { *(.rel.ctors) } ++ .rela.ctors : { *(.rela.ctors) } ++ .rel.dtors : { *(.rel.dtors) } ++ .rela.dtors : { *(.rela.dtors) } ++ .rel.bss : { *(.rel.bss) } ++ .rela.bss : { *(.rela.bss) } ++ .rel.plt : { *(.rel.plt) } ++ .rela.plt : { *(.rela.plt) } ++ .init : { *(.init) } ++ .plt : { *(.plt) } ++ .text : ++ { ++ cpu/mpc824x/start.o (.text) ++ lib_ppc/board.o (.text) ++ lib_ppc/ppcstring.o (.text) ++ lib_generic/vsprintf.o (.text) ++ lib_generic/crc32.o (.text) ++ lib_generic/zlib.o (.text) ++ ++ . = DEFINED(env_offset) ? env_offset : .; ++ common/environment.o (.text) ++ ++ *(.text) ++ ++ *(.fixup) ++ *(.got1) ++ . = ALIGN(16); ++ *(.rodata) ++ *(.rodata1) ++ *(.rodata.str1.4) ++ *(.eh_frame) ++ } ++ .fini : { *(.fini) } =0 ++ .ctors : { *(.ctors) } ++ .dtors : { *(.dtors) } ++ ++ /* Read-write section, merged into data segment: */ ++ . = (. + 0x0FFF) & 0xFFFFF000; ++ _erotext = .; ++ PROVIDE (erotext = .); ++ .reloc : ++ { ++ *(.got) ++ _GOT2_TABLE_ = .; ++ *(.got2) ++ _FIXUP_TABLE_ = .; ++ *(.fixup) ++ } ++ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; ++ __fixup_entries = (. - _FIXUP_TABLE_) >> 2; ++ ++ .data : ++ { ++ *(.data) ++ *(.data1) ++ *(.sdata) ++ *(.sdata2) ++ *(.dynamic) ++ CONSTRUCTORS ++ } ++ _edata = .; ++ PROVIDE (edata = .); ++ ++ . = .; ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ ++ . = .; ++ __start___ex_table = .; ++ __ex_table : { *(__ex_table) } ++ __stop___ex_table = .; ++ ++ . = ALIGN(4096); ++ __init_begin = .; ++ .text.init : { *(.text.init) } ++ .data.init : { *(.data.init) } ++ . = ALIGN(4096); ++ __init_end = .; ++ ++ __bss_start = .; ++ .bss : ++ { ++ *(.sbss) *(.scommon) ++ *(.dynbss) ++ *(.bss) ++ *(COMMON) ++ } ++ ++ _end = . ; ++ PROVIDE (end = .); ++} +diff -urN u-boot-86xx/common/cmd_bootm.c u-boot-86xx-kuro_clean/common/cmd_bootm.c +--- u-boot-86xx/common/cmd_bootm.c 2006-10-13 00:27:16.000000000 +0200 ++++ u-boot-86xx-kuro_clean/common/cmd_bootm.c 2006-11-06 22:05:38.000000000 +0100 +@@ -193,6 +193,12 @@ + verify = 0; + } else + #endif /* __I386__ */ ++#ifdef CONFIG_LINKSTATION ++ extern boot_os_Fcn do_boot_lskernel; ++ do_boot_lskernel(cmdtp, flag, argc, argv, ++ addr, NULL, verify); ++ return 1; /* Only returns on error */ ++#endif + { + puts ("Bad Magic Number\n"); + SHOW_BOOT_PROGRESS (-1); +diff -urN u-boot-86xx/common/cmd_ext2.c u-boot-86xx-kuro_clean/common/cmd_ext2.c +--- u-boot-86xx/common/cmd_ext2.c 2006-10-13 00:27:16.000000000 +0200 ++++ u-boot-86xx-kuro_clean/common/cmd_ext2.c 2006-11-06 22:05:38.000000000 +0100 +@@ -283,7 +283,8 @@ + sprintf(buf, "%lX", filelen); + setenv("filesize", buf); + +- return(filelen); ++// return(filelen); ++ return(0); + } + + U_BOOT_CMD( +diff -urN u-boot-86xx/common/console.c u-boot-86xx-kuro_clean/common/console.c +--- u-boot-86xx/common/console.c 2006-10-13 00:27:16.000000000 +0200 ++++ u-boot-86xx-kuro_clean/common/console.c 2006-11-06 22:05:38.000000000 +0100 +@@ -48,7 +48,7 @@ + + #endif /* CFG_CONSOLE_IS_IN_ENV */ + +-static int console_setfile (int file, device_t * dev) ++int console_setfile (int file, device_t * dev) + { + int error = 0; + +@@ -444,22 +444,27 @@ + gd->flags |= GD_FLG_DEVINIT; /* device initialization completed */ + + #ifndef CFG_CONSOLE_INFO_QUIET ++ if (strcmp(stdio_devices[stdout]->name, "serial")) { ++ extern char version_string[]; ++ printf ("\n%s\n", version_string); ++ } ++ + /* Print information */ +- puts ("In: "); ++ puts ("stdin : "); + if (stdio_devices[stdin] == NULL) { + puts ("No input devices available!\n"); + } else { + printf ("%s\n", stdio_devices[stdin]->name); + } + +- puts ("Out: "); ++ puts ("stdout: "); + if (stdio_devices[stdout] == NULL) { + puts ("No output devices available!\n"); + } else { + printf ("%s\n", stdio_devices[stdout]->name); + } + +- puts ("Err: "); ++ puts ("stderr: "); + if (stdio_devices[stderr] == NULL) { + puts ("No error devices available!\n"); + } else { +diff -urN u-boot-86xx/common/main.c u-boot-86xx-kuro_clean/common/main.c +--- u-boot-86xx/common/main.c 2006-10-13 00:27:16.000000000 +0200 ++++ u-boot-86xx-kuro_clean/common/main.c 2006-11-06 22:05:38.000000000 +0100 +@@ -84,6 +84,11 @@ + extern void mdm_init(void); /* defined in board.c */ + #endif + ++#ifdef CONFIG_LINKSTATION ++extern int avr_input(void); ++extern void avr_StopBoot(void); ++#endif ++ + /*************************************************************************** + * Watch for 'delay' seconds for autoboot stop or autoboot delay string. + * returns: 0 - no key string, allow autoboot +@@ -162,7 +167,14 @@ + /* In order to keep up with incoming data, check timeout only + * when catch up. + */ ++ uint64_t onesec = endtick(1); ++ int bootremain = bootdelay; + while (!abort && get_ticks() <= etime) { ++ if (get_ticks() >= onesec) { ++ onesec = endtick(1); ++ putc('\r'); ++ printf (CONFIG_AUTOBOOT_PROMPT, --bootremain); ++ } + for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i ++) { + if (delaykey[i].len > 0 && + presskey_len >= delaykey[i].len && +@@ -183,6 +195,20 @@ + } + } + ++#ifdef CONFIG_LINKSTATION ++ int avr_action = avr_input(); ++ if (avr_action == -3) ++ /* Abort boot */ ++ abort = 1; ++ else if (avr_action == -2) { ++ /* Restart boot */ ++ putc('\r'); ++ printf (CONFIG_AUTOBOOT_PROMPT, bootdelay); ++ etime = endtick(bootdelay); ++ onesec = endtick(1); ++ bootremain = bootdelay; ++ } ++#endif + if (tstc()) { + if (presskey_len < presskey_max) { + presskey [presskey_len ++] = getc(); +@@ -195,6 +221,7 @@ + } + } + } ++ putc('\n'); + # if DEBUG_BOOTKEYS + if (!abort) + puts ("key timeout\n"); +@@ -411,6 +438,10 @@ + int prev = disable_ctrlc(1); /* disable Control C checking */ + # endif + ++#ifdef CONFIG_LINKSTATION ++ s = getenv("bootcmd"); /* bootcmd can change (see avr.c) */ ++#endif ++ + # ifndef CFG_HUSH_PARSER + run_command (s, 0); + # else +@@ -445,6 +476,10 @@ + } + #endif + ++#ifdef CONFIG_LINKSTATION ++ avr_StopBoot(); ++#endif ++ + /* + * Main Loop for Monitor Command Processing + */ +@@ -469,6 +504,10 @@ + strcpy (lastcommand, console_buffer); + else if (len == 0) + flag |= CMD_FLAG_REPEAT; ++#ifdef CONFIG_LINKSTATION ++ else if (len == -2) ++ return; ++#endif + #ifdef CONFIG_BOOT_RETRY_TIME + else if (len == -2) { + /* -2 means timed out, retry autoboot +@@ -978,6 +1017,15 @@ + show_activity(0); + } + #endif ++#ifdef CONFIG_LINKSTATION ++ while (!tstc()) { ++ int avr_ret = avr_input(); ++ if (avr_ret == -2) ++ return (-2); ++ else if (avr_ret > 0) ++ return avr_ret; ++ } ++#endif + c = getc(); + + /* +diff -urN u-boot-86xx/cpu/mpc824x/cpu.c u-boot-86xx-kuro_clean/cpu/mpc824x/cpu.c +--- u-boot-86xx/cpu/mpc824x/cpu.c 2006-10-13 00:27:17.000000000 +0200 ++++ u-boot-86xx-kuro_clean/cpu/mpc824x/cpu.c 2006-11-06 22:05:38.000000000 +0100 +@@ -92,6 +92,7 @@ + + /*------------------------------------------------------------------- */ + ++#ifndef CONFIG_LINKSTATION + int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) + { + ulong msr, addr; +@@ -125,6 +126,7 @@ + return 1; + + } ++#endif + + /* ------------------------------------------------------------------------- */ + +diff -urN u-boot-86xx/cpu/mpc824x/start.S u-boot-86xx-kuro_clean/cpu/mpc824x/start.S +--- u-boot-86xx/cpu/mpc824x/start.S 2006-10-13 00:27:17.000000000 +0200 ++++ u-boot-86xx-kuro_clean/cpu/mpc824x/start.S 2006-11-06 22:05:38.000000000 +0100 +@@ -130,7 +130,7 @@ + + + in_flash: +-#if defined(CONFIG_BMW) ++#if defined(CONFIG_BMW) || defined(CONFIG_LINKSTATION) + bl early_init_f /* Must be ASM: no stack yet! */ + #endif + /* +@@ -155,6 +155,7 @@ + mtspr HID0, r2 + sync + ++#if !defined(CONFIG_LINKSTATION) + /* Allocate Initial RAM in data cache. + */ + lis r3, CFG_INIT_RAM_ADDR@h +@@ -175,6 +176,7 @@ + ori r3, r3, 0x0080 + sync + mtspr 1011, r3 ++#endif /* !CONFIG_LINKSTATION */ + #endif /* !CONFIG_BMW */ + /* + * Thisk the stack pointer *somewhere* sensible. Doesnt +@@ -195,7 +197,9 @@ + GET_GOT /* initialize GOT access */ + + /* r3: IMMR */ ++#if !defined(CONFIG_LINKSTATION) + bl cpu_init_f /* run low-level CPU init code (from Flash) */ ++#endif + + mr r3, r21 + /* r3: BOOTFLAG */ +@@ -475,7 +479,7 @@ + mr r10, r5 /* Save copy of Destination Address */ + + mr r3, r5 /* Destination Address */ +-#ifdef CFG_RAMBOOT ++#if defined(CFG_RAMBOOT) && !defined(CONFIG_LINKSTATION) + lis r4, CFG_SDRAM_BASE@h /* Source Address */ + ori r4, r4, CFG_SDRAM_BASE@l + #else +@@ -689,6 +693,14 @@ + cmplw 0, r7, r8 + blt 4b + ++ mfmsr r7 /* Exception prefix 0x000 */ ++ li r8,0 ++ ori r8,r8,MSR_IP ++ andc r7,r7,r8 ++ SYNC ++ mtmsr r7 ++ SYNC ++ + mtlr r4 /* restore link register */ + blr + +diff -urN u-boot-86xx/drivers/dc2114x.c u-boot-86xx-kuro_clean/drivers/dc2114x.c +--- u-boot-86xx/drivers/dc2114x.c 2006-10-13 00:27:17.000000000 +0200 ++++ u-boot-86xx-kuro_clean/drivers/dc2114x.c 2006-11-06 22:05:38.000000000 +0100 +@@ -27,14 +27,20 @@ + #include + #include + ++#if 0 ++#define DEBUG_TRACE ++#define DEBUG_TULIP ++#endif ++ + #undef DEBUG_SROM + #undef DEBUG_SROM2 + + #undef UPDATE_SROM + +-/* PCI Registers. ++/* ++ * PCI Registers. + */ +-#define PCI_CFDA_PSM 0x43 ++#define PCI_CFDA_PSM 0x43 + + #define CFRV_RN 0x000000f0 /* Revision Number */ + +@@ -43,10 +49,12 @@ + + #define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */ + +-/* Ethernet chip registers. ++/* ++ * Ethernet chip registers. + */ + #define DE4X5_BMR 0x000 /* Bus Mode Register */ + #define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */ ++#define DE4X5_RPD 0x010 /* Receive Poll Demand Reg */ + #define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */ + #define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */ + #define DE4X5_STS 0x028 /* Status Register */ +@@ -54,7 +62,8 @@ + #define DE4X5_SICR 0x068 /* SIA Connectivity Register */ + #define DE4X5_APROM 0x048 /* Ethernet Address PROM */ + +-/* Register bits. ++/* ++ * Register bits. + */ + #define BMR_SWR 0x00000001 /* Software Reset */ + #define STS_TS 0x00700000 /* Transmit Process State */ +@@ -64,8 +73,10 @@ + #define OMR_PS 0x00040000 /* Port Select */ + #define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */ + #define OMR_PM 0x00000080 /* Pass All Multicast */ ++#define OMR_PMS 0x00000040 /* Promiscuous */ + +-/* Descriptor bits. ++/* ++ * Descriptor bits. + */ + #define R_OWN 0x80000000 /* Own Bit */ + #define RD_RER 0x02000000 /* Receive End Of Ring */ +@@ -85,10 +96,10 @@ + + #define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */ + #define SROM_RD 0x00004000 /* Read from Boot ROM */ +-#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ ++#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ + #define EE_WRITE_0 0x4801 + #define EE_WRITE_1 0x4805 +-#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ ++#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ + #define SROM_SR 0x00000800 /* Select Serial ROM when set */ + + #define DT_IN 0x00000004 /* Serial Data In */ +@@ -97,6 +108,36 @@ + + #define POLL_DEMAND 1 + ++#ifndef PCI_VENDOR_ID_ADMTEK ++# define PCI_VENDOR_ID_ADMTEK 0x1317 ++#endif ++#ifndef PCI_DEVICE_ID_ADMTEK_AN983B ++# define PCI_DEVICE_ID_ADMTEK_AN983B 0x985 ++#endif ++ ++/* The chip types have been taken from linux-2.4.31 ++ * drivers/net/tulip/tulip.h ++ * Only COMET is used for now ++ */ ++enum chips { ++ DC21040 = 0, ++ DC21041 = 1, ++ DC21140 = 2, ++ DC21142 = 3, DC21143 = 3, ++ LC82C168, ++ MX98713, ++ MX98715, ++ MX98725, ++ AX88140, ++ PNIC2, ++ COMET, ++ COMPEX9881, ++ I21145, ++ DM910X, ++ CONEXANT, ++}; ++static int chip_idx = DC21143; ++ + #ifdef CONFIG_TULIP_FIX_DAVICOM + #define RESET_DM9102(dev) {\ + unsigned long i;\ +@@ -108,58 +149,63 @@ + #else + #define RESET_DE4X5(dev) {\ + int i;\ +- i=INL(dev, DE4X5_BMR);\ +- udelay(1000);\ ++ i=0x01A04000;\ + OUTL(dev, i | BMR_SWR, DE4X5_BMR);\ + udelay(1000);\ + OUTL(dev, i, DE4X5_BMR);\ + udelay(1000);\ +- for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\ +- udelay(1000);\ + } + #endif + + #define START_DE4X5(dev) {\ +- s32 omr; \ ++ u32 omr; \ + omr = INL(dev, DE4X5_OMR);\ + omr |= OMR_ST | OMR_SR;\ + OUTL(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */\ + } + + #define STOP_DE4X5(dev) {\ +- s32 omr; \ ++ u32 omr; \ + omr = INL(dev, DE4X5_OMR);\ + omr &= ~(OMR_ST|OMR_SR);\ + OUTL(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ \ + } + +-#define NUM_RX_DESC PKTBUFSRX ++#define NUM_RX_DESC 4 + #ifndef CONFIG_TULIP_FIX_DAVICOM +- #define NUM_TX_DESC 1 /* Number of TX descriptors */ ++ #define NUM_TX_DESC 2 /* Number of TX descriptors */ + #else + #define NUM_TX_DESC 4 + #endif +-#define RX_BUFF_SZ PKTSIZE_ALIGN ++#define BUFLEN 1536 + + #define TOUT_LOOP 1000000 + + #define SETUP_FRAME_LEN 192 + #define ETH_ALEN 6 ++#define ETH_ZLEN 60 + + struct de4x5_desc { +- volatile s32 status; ++ volatile u32 status; + u32 des1; + u32 buf; + u32 next; + }; + +-static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring */ +-static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring */ +-static int rx_new; /* RX descriptor ring pointer */ +-static int tx_new; /* TX descriptor ring pointer */ ++/* Note: transmit and receive buffers must be longword aligned and ++ longword divisable */ + +-static char rxRingSize; +-static char txRingSize; ++/* TX descriptor ring */ ++static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(4))); ++/* TX buffer */ ++static unsigned char txb[BUFLEN] __attribute__ ((aligned(32))); ++ ++/* RX descriptor ring */ ++static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(4))); ++/* RX buffers */ ++static unsigned char rxb[NUM_RX_DESC * BUFLEN] __attribute__ ((aligned(32))); ++ ++static int rx_new; /* RX descriptor ring pointer */ + + #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) + static void sendto_srom(struct eth_device* dev, u_int command, u_long addr); +@@ -204,6 +250,7 @@ + static struct pci_device_id supported[] = { + { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST }, + { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 }, ++ { PCI_VENDOR_ID_ADMTEK, PCI_DEVICE_ID_ADMTEK_AN983B }, + #ifdef CONFIG_TULIP_FIX_DAVICOM + { PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DAVICOM_DM9102A }, + #endif +@@ -214,29 +261,44 @@ + { + int idx=0; + int card_number = 0; +- unsigned int cfrv; ++ unsigned int cfrv; + unsigned char timer; +- pci_dev_t devbusfn; ++ pci_dev_t devbusfn; + unsigned int iobase; + unsigned short status; + struct eth_device* dev; ++ u16 vendor; ++ u16 device; + ++#ifdef DEBUG_TULIP ++ printf("%s\n", __FUNCTION__); ++#endif + while(1) { + devbusfn = pci_find_devices(supported, idx++); + if (devbusfn == -1) { + break; + } ++ pci_read_config_word(devbusfn, PCI_VENDOR_ID, &vendor); ++ pci_read_config_word(devbusfn, PCI_DEVICE_ID, &device); + +- /* Get the chip configuration revision register. */ +- pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv); ++ debug("dc21x4x: devbusfn: %08lX, VID: %08lX, DID: %08lX\n", ++ devbusfn, vendor, device); ++ ++ if (vendor == PCI_VENDOR_ID_ADMTEK && \ ++ device == PCI_DEVICE_ID_ADMTEK_AN983B) { ++ chip_idx = COMET; ++ } else { ++ /* Get the chip configuration revision register. */ ++ pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv); + + #ifndef CONFIG_TULIP_FIX_DAVICOM +- if ((cfrv & CFRV_RN) < DC2114x_BRK ) { +- printf("Error: The chip is not DC21143.\n"); +- continue; +- } ++ if ((cfrv & CFRV_RN) < DC2114x_BRK ) { ++ printf("Error: The chip is not DC21143.\n"); ++ idx++; ++ continue; ++ } + #endif +- ++ } + pci_read_config_word(devbusfn, PCI_COMMAND, &status); + status |= + #ifdef CONFIG_TULIP_USE_IO +@@ -286,7 +348,10 @@ + #ifdef CONFIG_TULIP_FIX_DAVICOM + sprintf(dev->name, "Davicom#%d", card_number); + #else +- sprintf(dev->name, "dc21x4x#%d", card_number); ++ if (chip_idx == COMET) ++ sprintf(dev->name, "COMET#%d", card_number); ++ else ++ sprintf(dev->name, "dc21x4x#%d", card_number); + #endif + + #ifdef CONFIG_TULIP_USE_IO +@@ -303,8 +368,6 @@ + /* Ensure we're not sleeping. */ + pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); + +- udelay(10 * 1000); +- + #ifndef CONFIG_TULIP_FIX_DAVICOM + read_hw_addr(dev, bis); + #endif +@@ -321,8 +384,9 @@ + int i; + int devbusfn = (int) dev->priv; + +- /* Ensure we're not sleeping. */ +- pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); ++#if defined(DEBUG_TULIP) || defined(DEBUG_TRACE) ++ serial_printf("%0lu %s\n", get_timer(0), __FUNCTION__); ++#endif + + #ifdef CONFIG_TULIP_FIX_DAVICOM + RESET_DM9102(dev); +@@ -330,57 +394,71 @@ + RESET_DE4X5(dev); + #endif + +- if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) { +- printf("Error: Cannot reset ethernet controller.\n"); +- return 0; +- } +- + #ifdef CONFIG_TULIP_SELECT_MEDIA + dc21x4x_select_media(dev); + #else +- OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); ++ if (chip_idx == COMET) { ++ /* No multicast */ ++ OUTL(dev, 0, 0xAC); ++ OUTL(dev, 0, 0xB0); ++ } else { ++ OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); ++ } + #endif + + for (i = 0; i < NUM_RX_DESC; i++) { + rx_ring[i].status = cpu_to_le32(R_OWN); +- rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); +- rx_ring[i].buf = cpu_to_le32(phys_to_bus((u32) NetRxPackets[i])); +-#ifdef CONFIG_TULIP_FIX_DAVICOM +- rx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &rx_ring[(i+1) % NUM_RX_DESC])); +-#else +- rx_ring[i].next = 0; +-#endif ++ rx_ring[i].des1 = cpu_to_le32(BUFLEN); ++ rx_ring[i].buf = cpu_to_le32(phys_to_bus((u32)&rxb[i * BUFLEN])); ++ rx_ring[i].next = cpu_to_le32(phys_to_bus((u32)&rx_ring[i+1])); + } ++ /* Write the end of list marker to the descriptor lists. */ ++ rx_ring[NUM_RX_DESC - 1].des1 |= cpu_to_le32(RD_RER); ++ rx_ring[NUM_RX_DESC - 1].next = cpu_to_le32(phys_to_bus((u32)&rx_ring[0])); + +- for (i=0; i < NUM_TX_DESC; i++) { +- tx_ring[i].status = 0; +- tx_ring[i].des1 = 0; +- tx_ring[i].buf = 0; ++ /* Point to the first descriptor */ ++ rx_new = 0; + +-#ifdef CONFIG_TULIP_FIX_DAVICOM +- tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC])); +-#else +- tx_ring[i].next = 0; +-#endif +- } ++ /* We only use 1 transmit buffer, but we use 2 descriptors so ++ transmit engines have somewhere to point to if they feel the need */ + +- rxRingSize = NUM_RX_DESC; +- txRingSize = NUM_TX_DESC; ++ tx_ring[0].status = 0; ++ tx_ring[0].des1 = 0; ++ tx_ring[0].buf = cpu_to_le32(phys_to_bus((u32)&txb[0])); ++ tx_ring[0].next = cpu_to_le32(phys_to_bus((u32)&tx_ring[1])); ++ ++ /* this descriptor should never get used, since it will never be owned ++ by the machine (status will always == 0) */ ++ ++ tx_ring[1].status = 0; ++ tx_ring[1].des1 = 0; ++ tx_ring[1].buf = cpu_to_le32(phys_to_bus((u32)&txb[0])); ++ tx_ring[1].next = cpu_to_le32(phys_to_bus((u32)&tx_ring[0])); + + /* Write the end of list marker to the descriptor lists. */ +- rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER); +- tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER); ++ tx_ring[1].des1 |= cpu_to_le32(TD_TER); + + /* Tell the adapter where the TX/RX rings are located. */ +- OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA); +- OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA); ++ OUTL(dev, phys_to_bus((u32) &rx_ring[0]), DE4X5_RRBA); ++ OUTL(dev, phys_to_bus((u32) &tx_ring[0]), DE4X5_TRBA); ++ ++ if (chip_idx == COMET) { ++ /* Bit 18 (0x00040000) is reserved in the AN983B */ ++ /* datasheet, but it is used by the tulip driver */ ++ OUTL(dev, (INL(dev, (DE4X5_OMR)) & ~(OMR_PMS | OMR_PM)) | OMR_PS, DE4X5_OMR); ++ /* Enable automatic Tx underrun recovery */ ++ OUTL(dev, INL(dev, 0x88) | 1, 0x88); ++// OUTL(dev, INL(dev, 0x88) | 0x19, 0x88); ++ } + + START_DE4X5(dev); + +- tx_new = 0; +- rx_new = 0; ++ /* Start receiving */ ++ OUTL(dev, POLL_DEMAND, DE4X5_RPD); + +- send_setup_frame(dev, bis); ++ if (chip_idx != COMET) { /* No setup frame needed by COMET */ ++ send_setup_frame(dev, bis); ++ } + + return 1; + } +@@ -389,90 +467,117 @@ + { + int status = -1; + int i; ++ u32 len = length; + + if (length <= 0) { + printf("%s: bad packet size: %d\n", dev->name, length); + goto Done; + } + +- for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { ++ for(i = 0; tx_ring[0].status & cpu_to_le32(T_OWN); i++) { + if (i >= TOUT_LOOP) { +- printf("%s: tx error buffer not ready\n", dev->name); ++ printf(".%s: Tx not ready\n", dev->name); + goto Done; + } + } + +- tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) packet)); +- tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length); +- tx_ring[tx_new].status = cpu_to_le32(T_OWN); ++ /* Disable the TX */ ++ OUTL(dev, INL(dev, DE4X5_OMR) & ~OMR_ST, DE4X5_OMR); ++ ++ memcpy(txb, (char*)packet, length); ++ ++ /* setup the transmit descriptor */ ++ tx_ring[0].des1 = cpu_to_le32(TD_LS | TD_FS | length); ++ tx_ring[0].status = cpu_to_le32(T_OWN); + ++ /* Point to transmit descriptor */ ++ OUTL(dev, phys_to_bus((u32) &tx_ring[0]), DE4X5_TRBA); ++ ++ /* Enable the TX */ ++ OUTL(dev, INL(dev, DE4X5_OMR) | OMR_ST, DE4X5_OMR); ++ ++ /* Immediate transmit demand */ + OUTL(dev, POLL_DEMAND, DE4X5_TPD); + +- for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { ++ for(i = 0; tx_ring[0].status & cpu_to_le32(T_OWN); i++) { + if (i >= TOUT_LOOP) { +- printf(".%s: tx buffer not ready\n", dev->name); ++ printf(".%s: Tx Timeout\n", dev->name); + goto Done; + } + } + +- if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) { +-#if 0 /* test-only */ ++#ifdef DEBUG_TRACE ++ serial_printf("%0lu Tx L2: %d P: %04X IP: %08X\n", ++ get_timer(0), i, *((u16 *)(packet+0xC)), ++ *((u32 *)(packet+0x1E))); ++#endif ++ ++ if (le32_to_cpu(tx_ring[0].status) & TD_ES) { ++#if 1 /* test-only */ + printf("TX error status = 0x%08X\n", +- le32_to_cpu(tx_ring[tx_new].status)); ++ le32_to_cpu(tx_ring[0].status)); + #endif +- tx_ring[tx_new].status = 0x0; ++ tx_ring[0].status = 0x0; + goto Done; + } + + status = length; + + Done: +- tx_new = (tx_new+1) % NUM_TX_DESC; + return status; + } + + static int dc21x4x_recv(struct eth_device* dev) + { +- s32 status; ++ u32 status; ++ int rx_prv; + int length = 0; + +- for ( ; ; ) { +- status = (s32)le32_to_cpu(rx_ring[rx_new].status); ++#ifdef DEBUG_TULIP ++ u32 csr5 = INL(dev, DE4X5_STS); ++ if ((csr5 & STS_RS) != 0x00060000) { ++ OUTL(dev, 0x0001ffff, DE4X5_STS); ++ printf("Receive status: 0x%08X\n", csr5); ++ } ++#endif + +- if (status & R_OWN) { +- break; +- } ++ status = (u32)le32_to_cpu(rx_ring[rx_new].status); ++ if (status & R_OWN) ++ return 0; + +- if (status & RD_LS) { +- /* Valid frame status. +- */ +- if (status & RD_ES) { +- +- /* There was an error. +- */ +- printf("RX error status = 0x%08X\n", status); +- } else { +- /* A valid frame received. +- */ +- length = (le32_to_cpu(rx_ring[rx_new].status) >> 16); +- +- /* Pass the packet up to the protocol +- * layers. +- */ +- NetReceive(NetRxPackets[rx_new], length - 4); +- } ++#ifdef DEBUG_TULIP ++ printf("recv status: 0x%08X\n", status); ++#endif + +- /* Change buffer ownership for this frame, back +- * to the adapter. +- */ ++ if (status & RD_LS) { ++#ifdef DEBUG_TRACE ++ serial_printf("rx: %d status: %08X\n", rx_new, status); ++#endif ++ /* Valid frame status */ ++ if (status & RD_ES) { ++ /* There was an error */ ++ printf("RX error status = 0x%08X\n", status); + rx_ring[rx_new].status = cpu_to_le32(R_OWN); +- } ++ } else { ++ /* Received valid frame */ ++ length = (int)(le32_to_cpu(rx_ring[rx_new].status) >> 16); ++ ++ /* Pass the packet up to the protocol layers. */ ++ unsigned char rxdata[BUFLEN]; ++ memcpy(rxdata, rxb + rx_new * BUFLEN, length - 4); + +- /* Update entry information. +- */ +- rx_new = (rx_new + 1) % rxRingSize; ++ /* Give buffer ownership for this ++ * frame back to the adapter */ ++ rx_ring[rx_new].status = cpu_to_le32(R_OWN); ++ ++ /* Pass the received packet to the upper layer */ ++ NetReceive(rxdata, length - 4); ++ } + } + ++ /* Update current descriptor index */ ++ rx_new = (rx_new + 1) % NUM_RX_DESC; ++ + return length; + } + +@@ -480,10 +585,12 @@ + { + int devbusfn = (int) dev->priv; + ++#ifdef DEBUG_TULIP ++ printf("%s\n", __FUNCTION__); ++#endif + STOP_DE4X5(dev); + OUTL(dev, 0, DE4X5_SICR); + +- pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP); + } + + static void send_setup_frame(struct eth_device* dev, bd_t *bis) +@@ -501,30 +608,29 @@ + } + } + +- for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { ++ for(i = 0; tx_ring[0].status & cpu_to_le32(T_OWN); i++) { + if (i >= TOUT_LOOP) { + printf("%s: tx error buffer not ready\n", dev->name); + goto Done; + } + } + +- tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0])); +- tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN); +- tx_ring[tx_new].status = cpu_to_le32(T_OWN); ++ tx_ring[0].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0])); ++ tx_ring[0].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN); ++ tx_ring[0].status = cpu_to_le32(T_OWN); + + OUTL(dev, POLL_DEMAND, DE4X5_TPD); + +- for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { ++ for(i = 0; tx_ring[0].status & cpu_to_le32(T_OWN); i++) { + if (i >= TOUT_LOOP) { + printf("%s: tx buffer not ready\n", dev->name); + goto Done; + } + } + +- if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) { +- printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status)); ++ if (le32_to_cpu(tx_ring[0].status) != 0x7FFFFFFF) { ++ printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[0].status)); + } +- tx_new = (tx_new+1) % NUM_TX_DESC; + + Done: + return; +@@ -543,7 +649,7 @@ + static int + getfrom_srom(struct eth_device* dev, u_long addr) + { +- s32 tmp; ++ u32 tmp; + + tmp = INL(dev, addr); + udelay(1); +@@ -708,19 +814,27 @@ + #ifndef CONFIG_TULIP_FIX_DAVICOM + static void read_hw_addr(struct eth_device *dev, bd_t *bis) + { +- u_short tmp, *p = (u_short *)(&dev->enetaddr[0]); +- int i, j = 0; +- +- for (i = 0; i < (ETH_ALEN >> 1); i++) { +- tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i)); +- *p = le16_to_cpu(tmp); +- j += *p++; +- } +- +- if ((j == 0) || (j == 0x2fffd)) { +- memset (dev->enetaddr, 0, ETH_ALEN); +- debug ("Warning: can't read HW address from SROM.\n"); +- goto Done; ++ if (chip_idx == COMET) { ++ /* COMET reads the ehernet address directly from the EEPROM */ ++ *(u32 *)dev->enetaddr = cpu_to_le32(INL(dev, 0xA4)); ++ *(u16 *)(dev->enetaddr+4) = cpu_to_le16(INL(dev, 0xA8)); ++ *(u32 *)bis->bi_enetaddr = *(u32 *)dev->enetaddr; ++ *(u16 *)(bis->bi_enetaddr+4) = *(u16 *)(dev->enetaddr+4); ++ } else { ++ u_short tmp, *p = (u_short *)(&dev->enetaddr[0]); ++ int i, j = 0; ++ ++ for (i = 0; i < (ETH_ALEN >> 1); i++) { ++ tmp=read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1)+i)); ++ *p = le16_to_cpu(tmp); ++ j += *p++; ++ } ++ ++ if ((j == 0) || (j == 0x2fffd)) { ++ memset (dev->enetaddr, 0, ETH_ALEN); ++ debug ("Warning: can't read HW address from SROM.\n"); ++ goto Done; ++ } + } + + return; +@@ -769,3 +883,5 @@ + #endif /* UPDATE_SROM */ + + #endif /* CFG_CMD_NET && CONFIG_NET_MULTI && CONFIG_TULIP */ ++ ++/* vim: set ts=4: */ +diff -urN u-boot-86xx/drivers/netconsole.c u-boot-86xx-kuro_clean/drivers/netconsole.c +--- u-boot-86xx/drivers/netconsole.c 2006-10-13 00:27:17.000000000 +0200 ++++ u-boot-86xx-kuro_clean/drivers/netconsole.c 2006-11-06 22:05:38.000000000 +0100 +@@ -27,6 +27,7 @@ + + #include + #include ++#include + #include + + DECLARE_GLOBAL_DATA_PTR; +@@ -124,6 +125,26 @@ + output_packet_len = len; + NetLoop (NETCONS); /* wait for arp reply and send packet */ + output_packet_len = 0; ++#if defined(CFG_CONSOLE_IS_IN_ENV) || defined(CONFIG_SILENT_CONSOLE) ++ if (NetState == NETLOOP_FAIL) { ++ /* ARP failed, fail back to serial console */ ++ device_t *idev; ++ device_t *odev; ++ ++ idev = search_device(DEV_FLAGS_INPUT, "serial"); ++ odev = search_device(DEV_FLAGS_OUTPUT, "serial"); ++ ++ console_setfile (stdin, idev); ++ console_setfile (stdout, odev); ++ console_setfile (stderr, odev); ++ ++#if defined(CONFIG_LINKSTATION) ++ void next_cons_choice(int console); ++ /* Console 0 is the serial console */ ++ next_cons_choice(0); ++#endif ++ } ++#endif + return; + } + +@@ -236,7 +257,8 @@ + + input_recursion = 1; + +- net_timeout = 1; ++// net_timeout = 1; ++ net_timeout = 50; + NetLoop (NETCONS); /* kind of poll */ + + input_recursion = 0; +diff -urN u-boot-86xx/drivers/rtl8169.c u-boot-86xx-kuro_clean/drivers/rtl8169.c +--- u-boot-86xx/drivers/rtl8169.c 2006-10-13 00:27:17.000000000 +0200 ++++ u-boot-86xx-kuro_clean/drivers/rtl8169.c 2006-11-06 22:05:38.000000000 +0100 +@@ -48,7 +48,10 @@ + * + * Indent Options: indent -kr -i8 + ***************************************************************************/ +- ++/* ++ * 26 August 2006 Mihai Georgian ++ * Modified to use le32_to_cpu and cpu_to_le32 properly ++ */ + #include + #include + #include +@@ -68,6 +71,7 @@ + static u32 ioaddr; + + /* Condensed operations for readability. */ ++#define virt_to_bus(addr) cpu_to_le32(addr) + #define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr)) + #define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr)) + +@@ -413,23 +417,23 @@ + ioaddr = dev->iobase; + + cur_rx = tpc->cur_rx; +- if ((tpc->RxDescArray[cur_rx].status & OWNbit) == 0) { +- if (!(tpc->RxDescArray[cur_rx].status & RxRES)) { ++ if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { ++ if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { + unsigned char rxdata[RX_BUF_LEN]; +- length = (int) (tpc->RxDescArray[cur_rx]. +- status & 0x00001FFF) - 4; ++ length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. ++ status) & 0x00001FFF) - 4; + + memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); + NetReceive(rxdata, length); + + if (cur_rx == NUM_RX_DESC - 1) + tpc->RxDescArray[cur_rx].status = +- (OWNbit | EORbit) + RX_BUF_SIZE; ++ cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); + else + tpc->RxDescArray[cur_rx].status = +- OWNbit + RX_BUF_SIZE; ++ cpu_to_le32(OWNbit + RX_BUF_SIZE); + tpc->RxDescArray[cur_rx].buf_addr = +- virt_to_bus(tpc->RxBufferRing[cur_rx]); ++ cpu_to_le32(tpc->RxBufferRing[cur_rx]); + } else { + puts("Error Rx"); + } +@@ -454,6 +458,7 @@ + u8 *ptxb; + int entry = tpc->cur_tx % NUM_TX_DESC; + u32 len = length; ++ int ret; + + #ifdef DEBUG_RTL8169_TX + int stime = currticks(); +@@ -465,39 +470,46 @@ + + /* point to the current txb incase multiple tx_rings are used */ + ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; ++#ifdef DEBUG_RTL8169_TX ++ printf("ptxb: %08X, length: %d\n", ptxb, (int)length); ++#endif + memcpy(ptxb, (char *)packet, (int)length); + + while (len < ETH_ZLEN) + ptxb[len++] = '\0'; + +- tpc->TxDescArray[entry].buf_addr = virt_to_bus(ptxb); ++ tpc->TxDescArray[entry].buf_addr = cpu_to_le32(ptxb); + if (entry != (NUM_TX_DESC - 1)) { + tpc->TxDescArray[entry].status = +- (OWNbit | FSbit | LSbit) | ((len > ETH_ZLEN) ? +- len : ETH_ZLEN); ++ cpu_to_le32((OWNbit | FSbit | LSbit) | ++ ((len > ETH_ZLEN) ? len : ETH_ZLEN)); + } else { + tpc->TxDescArray[entry].status = +- (OWNbit | EORbit | FSbit | LSbit) | +- ((len > ETH_ZLEN) ? length : ETH_ZLEN); ++ cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | ++ ((len > ETH_ZLEN) ? len : ETH_ZLEN)); + } + RTL_W8(TxPoll, 0x40); /* set polling bit */ + + tpc->cur_tx++; + to = currticks() + TX_TIMEOUT; +- while ((tpc->TxDescArray[entry].status & OWNbit) && (currticks() < to)); /* wait */ ++ while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) ++ && (currticks() < to)); /* wait */ + + if (currticks() >= to) { + #ifdef DEBUG_RTL8169_TX + puts ("tx timeout/error\n"); + printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); + #endif +- return 0; ++ ret = 0; + } else { + #ifdef DEBUG_RTL8169_TX + puts("tx done\n"); + #endif +- return length; ++ ret = length; + } ++ /* Delay to make net console (nc) work properly */ ++ udelay(20); ++ return ret; + } + + static void rtl8169_set_rx_mode(struct eth_device *dev) +@@ -603,13 +615,14 @@ + for (i = 0; i < NUM_RX_DESC; i++) { + if (i == (NUM_RX_DESC - 1)) + tpc->RxDescArray[i].status = +- (OWNbit | EORbit) + RX_BUF_SIZE; ++ cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); + else +- tpc->RxDescArray[i].status = OWNbit + RX_BUF_SIZE; ++ tpc->RxDescArray[i].status = ++ cpu_to_le32(OWNbit + RX_BUF_SIZE); + + tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; + tpc->RxDescArray[i].buf_addr = +- virt_to_bus(tpc->RxBufferRing[i]); ++ cpu_to_le32(tpc->RxBufferRing[i]); + } + + #ifdef DEBUG_RTL8169 +@@ -635,17 +648,23 @@ + if (tpc->TxDescArrays == 0) + puts("Allot Error"); + /* Tx Desscriptor needs 256 bytes alignment; */ +- TxPhyAddr = virt_to_bus(tpc->TxDescArrays); ++ TxPhyAddr = tpc->TxDescArrays; + diff = 256 - (TxPhyAddr - ((TxPhyAddr >> 8) << 8)); + TxPhyAddr += diff; + tpc->TxDescArray = (struct TxDesc *) (tpc->TxDescArrays + diff); ++#ifdef DEBUG_RTL8169 ++ printf("tpc->TxDescArray: %08X\n", tpc->TxDescArray); ++#endif + + tpc->RxDescArrays = rx_ring; + /* Rx Desscriptor needs 256 bytes alignment; */ +- RxPhyAddr = virt_to_bus(tpc->RxDescArrays); ++ RxPhyAddr = tpc->RxDescArrays; + diff = 256 - (RxPhyAddr - ((RxPhyAddr >> 8) << 8)); + RxPhyAddr += diff; + tpc->RxDescArray = (struct RxDesc *) (tpc->RxDescArrays + diff); ++#ifdef DEBUG_RTL8169 ++ printf("tpc->RxDescArray: %08X\n", tpc->RxDescArray); ++#endif + + if (tpc->TxDescArrays == NULL || tpc->RxDescArrays == NULL) { + puts("Allocate RxDescArray or TxDescArray failed\n"); +@@ -733,7 +752,7 @@ + + /* Get MAC address. FIXME: read EEPROM */ + for (i = 0; i < MAC_ADDR_LEN; i++) +- dev->enetaddr[i] = RTL_R8(MAC0 + i); ++ bis->bi_enetaddr[i] = dev->enetaddr[i] = RTL_R8(MAC0 + i); + + #ifdef DEBUG_RTL8169 + printf("MAC Address"); +@@ -805,33 +824,68 @@ + PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); + udelay(100); + ++#ifdef CONFIG_LINKSTATION ++void miconCntl_FanLow(void); ++void miconCntl_FanHigh(void); ++void miconCntl_Eth1000M(int up); ++void miconCntl_Eth100M(int up); ++void miconCntl_Eth10M(int up); ++void miconCntl_5f(void); ++ ++ miconCntl_FanLow(); ++#endif ++ + /* wait for auto-negotiation process */ + for (i = 10000; i > 0; i--) { + /* check if auto-negotiation complete */ + if (mdio_read(PHY_STAT_REG) & PHY_Auto_Neco_Comp) { + udelay(100); + option = RTL_R8(PHYstatus); ++#if defined(CONFIG_LINKSTATION) && defined(CONFIG_HTGL) + if (option & _1000bpsF) { + #ifdef DEBUG_RTL8169 + printf("%s: 1000Mbps Full-duplex operation.\n", + dev->name); + #endif +- } else { ++ miconCntl_Eth1000M(1); ++ } else if (option & _100bps) { ++#ifdef DEBUG_RTL8169 ++ printf("%s: 100Mbps %s-duplexoperation.\n", ++ dev->name, ++ (option & FullDup) ? "Full" : "Half"); ++#endif ++ miconCntl_Eth100M(1); ++ } else if (option & _10bps) { + #ifdef DEBUG_RTL8169 + printf +- ("%s: %sMbps %s-duplex operation.\n", ++ ("%s: 10Mbps %s-duplex operation.\n", + dev->name, +- (option & _100bps) ? "100" : +- "10", +- (option & FullDup) ? "Full" : +- "Half"); ++ (option & FullDup) ? "Full" : "Half"); ++#endif ++ miconCntl_Eth100M(1); ++ } ++ miconCntl_5f(); ++#else /* !defined(CONFIG_LINKSTATION) || !defined(CONFIG_HTGL) */ ++ if (option & _1000bpsF) { ++#ifdef DEBUG_RTL8169 ++ printf("%s: 1000Mbps Full-duplex operation.\n", ++ dev->name); ++#endif ++ miconCntl_FanHigh(); ++ } else { ++#ifdef DEBUG_RTL8169 ++ printk("%s: %sMbps %s-duplex operation.\n", ++ dev->name, ++ (option & _100bps) ? "100" : "10", ++ (option & FullDup) ? "Full" : "Half"); + #endif + } ++#endif + break; + } else { + udelay(100); + } +- } /* end for-loop to wait for auto-negotiation process */ ++ } /* end for-loop to wait for auto-negotiation process */ + + } else { + udelay(100); +@@ -886,3 +940,5 @@ + } + + #endif ++ ++/* vim: set ts=4: */ +diff -urN u-boot-86xx/fs/ext2/ext2fs.c u-boot-86xx-kuro_clean/fs/ext2/ext2fs.c +--- u-boot-86xx/fs/ext2/ext2fs.c 2006-10-13 00:27:17.000000000 +0200 ++++ u-boot-86xx-kuro_clean/fs/ext2/ext2fs.c 2006-11-06 22:05:38.000000000 +0100 +@@ -35,6 +35,8 @@ + + /* Magic value used to identify an ext2 filesystem. */ + #define EXT2_MAGIC 0xEF53 ++/* Magic value used to identify Buffalo's idea of ext2 */ ++#define LINKSTATION_MAGIC 0xEF54 + /* Amount of indirect blocks in an inode. */ + #define INDIRECT_BLOCKS 12 + /* Maximum lenght of a pathname. */ +@@ -851,7 +853,8 @@ + goto fail; + } + /* Make sure this is an ext2 filesystem. */ +- if (__le16_to_cpu (data->sblock.magic) != EXT2_MAGIC) { ++ if ((__le16_to_cpu (data->sblock.magic) != EXT2_MAGIC) && ++ (__le16_to_cpu (data->sblock.magic) != LINKSTATION_MAGIC)) { + goto fail; + } + data->diropen.data = data; +diff -urN u-boot-86xx/include/configs/linkstation.h u-boot-86xx-kuro_clean/include/configs/linkstation.h +--- u-boot-86xx/include/configs/linkstation.h 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-86xx-kuro_clean/include/configs/linkstation.h 2006-11-06 22:30:33.000000000 +0100 +@@ -0,0 +1,492 @@ ++/* ++ * Copyright (C) 2006 Mihai Georgian ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#if 0 ++#define DEBUG ++#endif ++ ++/*----------------------------------------------------------------------- ++ * User configurable settings: ++ * Mandatory settings: ++ * CONFIG_IPADDR_LS - the IP address of the LinkStation ++ * CONFIG_SERVERIP_LS - the address of the server for NFS/TFTP/DHCP/BOOTP ++ * Optional settins: ++ * CONFIG_NCIP_LS - the adress of the computer running net console ++ * if not configured, it will be set to ++ * CONFIG_SERVERIP_LS ++ */ ++ ++#define CONFIG_IPADDR_LS 192.168.11.150 ++#define CONFIG_SERVERIP_LS 192.168.11.149 ++ ++#if !defined(CONFIG_IPADDR_LS) || !defined(CONFIG_SERVERIP_LS) ++#error Both CONFIG_IPADDR_LS and CONFIG_SERVERIP_LS must be defined ++#endif ++ ++#if !defined(CONFIG_NCIP_LS) ++#define CONFIG_NCIP_LS CONFIG_SERVERIP_LS ++#endif ++ ++/*---------------------------------------------------------------------- ++ * DO NOT CHANGE ANYTHING BELOW, UNLESS YOU KNOW WHAT YOU ARE DOING ++ *---------------------------------------------------------------------*/ ++ ++#define CONFIG_MPC8245 1 ++#define CONFIG_LINKSTATION 1 ++ ++/*--------------------------------------- ++ * Supported models ++ * ++ * LinkStation HDLAN /KuroBox Standard (CONFIG_HLAN) ++ * LinkStation old model (CONFIG_LAN) - totally untested ++ * LinkStation HGLAN / KuroBox HG (CONFIG_HGLAN) ++ * ++ * Models not supported yet ++ * TeraStatin (CONFIG_HTGL) ++ */ ++ ++#if defined(CONFIG_HLAN) || defined(CONFIG_LAN) ++#define CONFIG_IDENT_STRING " LinkStation / KuroBox" ++#elif defined(CONFIG_HGLAN) ++#define CONFIG_IDENT_STRING " LinkStation HG / KuroBox HG" ++#elif defined(CONFIG_HTGL) ++#define CONFIG_IDENT_STRING " TeraStation" ++#else ++#error No LinkStation model defined ++#endif ++ ++#define CONFIG_BOOTDELAY 10 ++#define CONFIG_ZERO_BOOTDELAY_CHECK ++#undef CONFIG_BOOT_RETRY_TIME ++ ++#define CONFIG_AUTOBOOT_KEYED ++#define CONFIG_AUTOBOOT_PROMPT "Boot in %02d seconds ('s' to stop)..." ++#define CONFIG_AUTOBOOT_STOP_STR "s" ++ ++#define CONFIG_COMMANDS (CFG_CMD_BDI | \ ++ CFG_CMD_LOADS | \ ++ CFG_CMD_LOADB | \ ++ CFG_CMD_FLASH | \ ++ CFG_CMD_MEMORY | \ ++ CFG_CMD_NET | \ ++ CFG_CMD_ENV | \ ++ CFG_CMD_IDE | \ ++ CFG_CMD_PCI | \ ++ CFG_CMD_BOOTD | \ ++ CFG_CMD_CONSOLE | \ ++ CFG_CMD_RUN | \ ++ CFG_CMD_ECHO | \ ++ CFG_CMD_DHCP | \ ++ CFG_CMD_PING | \ ++ CFG_CMD_NFS | \ ++ CFG_CMD_EXT2 ) ++#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL ++ ++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ ++#include ++ ++/* ++ * Miscellaneous configurable options ++ */ ++#define CFG_LONGHELP /* undef to save memory */ ++#define CFG_PROMPT "=> " /* Monitor Command Prompt */ ++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ ++ ++#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) ++#define CFG_MAXARGS 16 /* Max number of command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ ++#define CFG_LOAD_ADDR 0x00800000 /* Default load address: 8 MB */ ++ ++//#define CONFIG_BOOTCOMMAND "run nfsboot" ++#define CONFIG_BOOTCOMMAND "run bootcmd1" ++#define CONFIG_BOOTARGS "root=/dev/hda1" ++#define CONFIG_NFSBOOTCOMMAND "bootp;run nfsargs;bootm" ++ ++#define CFG_CONSOLE_IS_IN_ENV ++ ++#define XMK_STR(x) #x ++#define MK_STR(x) XMK_STR(x) ++ ++#if defined(CONFIG_HLAN) || defined(CONFIG_LAN) ++#define UBFILE "share/u-boot/u-boot-hd.flash.bin" ++#elif defined(CONFIG_HGLAN) ++#define UBFILE "share/u-boot/u-boot-hg.flash.bin" ++#elif defined(CONFIG_HTGL) ++#define UBFILE "share/u-boot/u-boot-ht.flash.bin" ++#else ++#error No LinkStation model defined ++#endif ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "autoload=no\0" \ ++ "stdin=nc\0" \ ++ "stdout=nc\0" \ ++ "stderr=nc\0" \ ++ "ipaddr="MK_STR(CONFIG_IPADDR_LS)"\0" \ ++ "netmask=255.255.255.0\0" \ ++ "serverip="MK_STR(CONFIG_SERVERIP_LS)"\0" \ ++ "ncip="MK_STR(CONFIG_NCIP_LS)"\0" \ ++ "netretry=no\0" \ ++ "nc=setenv stdin nc;setenv stdout nc;setenv stderr nc\0" \ ++ "ser=setenv stdin serial;setenv stdout serial;setenv stderr serial\0" \ ++ "ldaddr=800000\0" \ ++ "hdpart=0:1\0" \ ++ "hdfile=boot/vmlinux.UBoot\0" \ ++ "hdload=echo Loading ${hdpart}:${hdfile};ext2load ide ${hdpart} ${ldaddr} ${hdfile}\0" \ ++ "boothd=setenv bootargs root=/dev/hda1;bootm ${ldaddr}\0" \ ++ "hdboot=run hdload boothd\0" \ ++ "flboot=setenv bootargs root=/dev/hda1;bootm ffc00000\0" \ ++ "emboot=setenv bootargs root=/dev/ram0;bootm ffc00000\0" \ ++ "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ ++ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \ ++ "bootretry=30\0" \ ++ "bootcmd1=run hdboot;run flboot\0" \ ++ "bootcmd2=run flboot\0" \ ++ "bootcmd3=run emboot\0" \ ++ "writeng=protect off fff70000 fff7ffff;era fff70000 fff7ffff;mw.l 800000 4e474e47 1;cp.b 800000 fff70000 4\0" \ ++ "writeok=protect off fff70000 fff7ffff;era fff70000 fff7ffff;mw.l 800000 4f4b4f4b 1;cp.b 800000 fff70000 4\0" \ ++ "ubpart=0:3\0" \ ++ "ubfile="UBFILE"\0" \ ++ "ubload=echo Loading ${ubpart}:${ubfile};ext2load ide ${ubpart} ${ldaddr} ${ubfile}\0" \ ++ "ubsaddr=fff00000\0" \ ++ "ubeaddr=fff2ffff\0" \ ++ "ubflash=protect off ${ubsaddr} ${ubeaddr};era ${ubsaddr} ${ubeaddr};cp.b ${ldaddr} ${ubsaddr} ${filesize};cmp.b ${ldaddr} ${ubsaddr} ${filesize}\0" \ ++ "upgrade=run ubload ubflash\0" ++ ++/*----------------------------------------------------------------------- ++ * PCI stuff ++ */ ++#define CONFIG_PCI ++#undef CONFIG_PCI_PNP ++#define CONFIG_PCI_SCAN_SHOW ++ ++#ifndef CONFIG_PCI_PNP ++/* Keep the following defines in sync with the BAT mappings */ ++ ++#define PCI_ETH_IOADDR 0xbfff00 ++#define PCI_ETH_MEMADDR 0xbffffc00 ++#define PCI_IDE_IOADDR 0xbffed0 ++#define PCI_IDE_MEMADDR 0xbffffb00 ++#define PCI_USB0_IOADDR 0 ++#define PCI_USB0_MEMADDR 0xbfffe000 ++#define PCI_USB1_IOADDR 0 ++#define PCI_USB1_MEMADDR 0xbfffd000 ++#define PCI_USB2_IOADDR 0 ++#define PCI_USB2_MEMADDR 0xbfffcf00 ++ ++#endif ++ ++/*----------------------------------------------------------------------- ++ * Ethernet stuff ++ */ ++#define CONFIG_NET_MULTI ++ ++#if defined(CONFIG_LAN) || defined(CONFIG_HLAN) ++#define CONFIG_TULIP ++#define CONFIG_TULIP_USE_IO ++#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) ++#define CONFIG_RTL8169 ++#endif ++ ++#define CONFIG_NET_RETRY_COUNT 5 ++ ++#define CONFIG_NETCONSOLE ++ ++/*----------------------------------------------------------------------- ++ * Start addresses for the final memory configuration ++ * (Set up by the startup code) ++ * Please note that CFG_SDRAM_BASE _must_ start at 0 ++ */ ++#define CFG_SDRAM_BASE 0x00000000 ++ ++#define CFG_FLASH_BASE 0xFFC00000 ++#define CFG_MONITOR_BASE TEXT_BASE ++ ++#define CFG_RESET_ADDRESS 0xFFF00100 ++#define CFG_EUMB_ADDR 0x80000000 ++#define CFG_PCI_MEM_ADDR 0xB0000000 ++#define CFG_MISC_REGION_ADDR 0xFE000000 ++ ++#define CFG_MONITOR_LEN 0x00040000 /* 256 kB */ ++#define CFG_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */ ++ ++#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ ++#define CFG_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */ ++ ++/* Maximum amount of RAM */ ++#if defined(CONFIG_HLAN) || defined(CONFIG_LAN) ++#define CFG_MAX_RAM_SIZE 0x04000000 /* 64MB of SDRAM */ ++#elif defined(CONFIG_HGLAN) || defined(CONFIG_HTGL) ++#define CFG_MAX_RAM_SIZE 0x08000000 /* 128MB of SDRAM */ ++#else ++#error Unknown LinkStation type ++#endif ++ ++/*----------------------------------------------------------------------- ++ * Change TEXT_BASE in bord/linkstation/config.mk to get a RAM build ++ * ++ * RAM based builds are for testing purposes. A Linux module, uloader.o, ++ * exists to load U-Boot and pass control to it ++ * ++ * Always do "make clean" after changing the build type ++ */ ++#if CFG_MONITOR_BASE < CFG_FLASH_BASE ++#define CFG_RAMBOOT ++#endif ++ ++/*----------------------------------------------------------------------- ++ * Definitions for initial stack pointer and data area ++ */ ++#if 1 /* RAM is available when the first C function is called */ ++#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE - 0x1000) ++#else ++#define CFG_INIT_RAM_ADDR 0x40000000 ++#endif ++#define CFG_INIT_RAM_END 0x1000 ++#define CFG_GBL_DATA_SIZE 128 ++#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) ++ ++/*---------------------------------------------------------------------- ++ * Serial configuration ++ */ ++#define CONFIG_CONS_INDEX 1 ++#define CONFIG_BAUDRATE 57600 ++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } ++ ++#define CFG_NS16550 ++#define CFG_NS16550_SERIAL ++ ++#define CFG_NS16550_REG_SIZE 1 ++ ++#define CFG_NS16550_CLK get_bus_freq(0) ++ ++#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4600) /* Console port */ ++#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4500) /* AVR port */ ++ ++/* ++ * Low Level Configuration Settings ++ * (address mappings, register initial values, etc.) ++ * You should know what you are doing if you make changes here. ++ * For the detail description refer to the MPC8245 user's manual. ++ * ++ * Unless indicated otherwise, the values are ++ * taken from the orignal Linkstation boot code ++ * ++ * Most of the low level configuration setttings are normally used ++ * in cpu/mpc824x/cpu_init.c which is NOT used by this implementation. ++ * Low level initialisation is done in board/linkstation/early_init.S ++ * The values below are included for reference purpose only ++ */ ++ ++/* FIXME: 32.768 MHz is the crystal frequency but */ ++/* the real frequency is lower by about 0.75% */ ++#define CONFIG_SYS_CLK_FREQ 32768000 ++#define CFG_HZ 1000 ++ ++/* Bit-field values for MCCR1. */ ++#define CFG_ROMNAL 0 ++#define CFG_ROMFAL 11 ++ ++#define CFG_BANK0_ROW 2 /* Only bank 0 used: 13 x n x 4 */ ++#define CFG_BANK1_ROW 0 ++#define CFG_BANK2_ROW 0 ++#define CFG_BANK3_ROW 0 ++#define CFG_BANK4_ROW 0 ++#define CFG_BANK5_ROW 0 ++#define CFG_BANK6_ROW 0 ++#define CFG_BANK7_ROW 0 ++ ++/* Bit-field values for MCCR2. */ ++#define CFG_TSWAIT 0 ++#define CFG_REFINT 1400 ++ ++/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */ ++#define CFG_BSTOPRE 121 ++ ++/* Bit-field values for MCCR3. */ ++#define CFG_REFREC 7 ++ ++/* Bit-field values for MCCR4. */ ++#define CFG_PRETOACT 2 ++#define CFG_ACTTOPRE 5 /* Original value was 2 */ ++#define CFG_ACTORW 2 ++#define CFG_SDMODE_CAS_LAT 2 /* For 100MHz bus. Use 3 for 133MHz */ ++#define CFG_REGISTERD_TYPE_BUFFER 1 ++#define CFG_EXTROM 1 /* Original setting but there is no EXTROM */ ++#define CFG_REGDIMM 0 ++#define CFG_DBUS_SIZE2 1 ++#define CFG_SDMODE_WRAP 0 ++ ++#define CFG_PGMAX 0x32 /* All boards use this setting. Original 0x92 */ ++#define CFG_SDRAM_DSCD 0x30 ++ ++/* Memory bank settings. ++ * Only bits 20-29 are actually used from these vales to set the ++ * start/end addresses. The upper two bits will always be 0, and the lower ++ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end ++ * address. Refer to the MPC8240 book. ++ */ ++ ++#define CFG_BANK0_START 0x00000000 ++#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) ++#define CFG_BANK0_ENABLE 1 ++#define CFG_BANK1_START 0x3ff00000 ++#define CFG_BANK1_END 0x3fffffff ++#define CFG_BANK1_ENABLE 0 ++#define CFG_BANK2_START 0x3ff00000 ++#define CFG_BANK2_END 0x3fffffff ++#define CFG_BANK2_ENABLE 0 ++#define CFG_BANK3_START 0x3ff00000 ++#define CFG_BANK3_END 0x3fffffff ++#define CFG_BANK3_ENABLE 0 ++#define CFG_BANK4_START 0x3ff00000 ++#define CFG_BANK4_END 0x3fffffff ++#define CFG_BANK4_ENABLE 0 ++#define CFG_BANK5_START 0x3ff00000 ++#define CFG_BANK5_END 0x3fffffff ++#define CFG_BANK5_ENABLE 0 ++#define CFG_BANK6_START 0x3ff00000 ++#define CFG_BANK6_END 0x3fffffff ++#define CFG_BANK6_ENABLE 0 ++#define CFG_BANK7_START 0x3ff00000 ++#define CFG_BANK7_END 0x3fffffff ++#define CFG_BANK7_ENABLE 0 ++ ++#define CFG_ODCR 0x95 /* 0x15 or 0x95 ? */ ++ ++/*---------------------------------------------------------------------- ++ * Initial BAT mappings ++ */ ++ ++/* NOTES: ++ * 1) GUARDED and WRITETHROUGH not allowed in IBATS ++ * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT ++ */ ++ ++/* SDRAM */ ++#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) ++#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP) ++ ++#define CFG_DBAT0L CFG_IBAT0L ++#define CFG_DBAT0U CFG_IBAT0U ++ ++/* EUMB: 1MB of address space */ ++#define CFG_IBAT1L (CFG_EUMB_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT) ++#define CFG_IBAT1U (CFG_EUMB_ADDR | BATU_BL_1M | BATU_VS | BATU_VP) ++ ++#define CFG_DBAT1L (CFG_IBAT1L | BATL_GUARDEDSTORAGE) ++#define CFG_DBAT1U CFG_IBAT1U ++ ++/* PCI Mem: 256MB of address space */ ++#define CFG_IBAT2L (CFG_PCI_MEM_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT) ++#define CFG_IBAT2U (CFG_PCI_MEM_ADDR | BATU_BL_256M | BATU_VS | BATU_VP) ++ ++#define CFG_DBAT2L (CFG_IBAT2L | BATL_GUARDEDSTORAGE) ++#define CFG_DBAT2U CFG_IBAT2U ++ ++/* PCI and local ROM/Flash: last 32MB of address space */ ++#define CFG_IBAT3L (CFG_MISC_REGION_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT) ++#define CFG_IBAT3U (CFG_MISC_REGION_ADDR | BATU_BL_32M | BATU_VS | BATU_VP) ++ ++#define CFG_DBAT3L (CFG_IBAT3L | BATL_GUARDEDSTORAGE) ++#define CFG_DBAT3U CFG_IBAT3U ++ ++/* ++ * For booting Linux, the board info and command line data ++ * have to be in the first 8 MB of memory, since this is ++ * the maximum mapped by the Linux kernel during initialization. ++ * ++ * FIXME: This doesn't appear to be true for the newer kernels ++ * which map more that 8 MB ++ */ ++#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ ++ ++/*----------------------------------------------------------------------- ++ * FLASH organization ++ */ ++#undef CFG_FLASH_PROTECTION ++#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ ++#define CFG_MAX_FLASH_SECT 72 /* Max number of sectors per flash */ ++ ++#define CFG_FLASH_ERASE_TOUT 12000 ++#define CFG_FLASH_WRITE_TOUT 1000 ++ ++ ++#define CFG_ENV_IS_IN_FLASH ++/* ++ * The original LinkStation flash organisation uses ++ * 448 kB (0xFFF00000 - 0xFFF6FFFF) for the boot loader ++ * We use the last sector of this area to store the environment ++ * which leaves max. 384 kB for the U-Boot itself ++ */ ++#define CFG_ENV_ADDR 0xFFF60000 ++#define CFG_ENV_SIZE 0x00010000 ++#define CFG_ENV_SECT_SIZE 0x00010000 ++ ++/*----------------------------------------------------------------------- ++ * Cache Configuration ++ */ ++#define CFG_CACHELINE_SIZE 32 ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ ++#endif ++ ++/*----------------------------------------------------------------------- ++ * IDE/ATA definitions ++ */ ++#undef CONFIG_IDE_LED /* No IDE LED */ ++#define CONFIG_IDE_RESET /* no reset for ide supported */ ++#define CONFIG_IDE_PREINIT /* check for units */ ++#define CONFIG_LBA48 /* 48 bit LBA supported */ ++ ++#if defined(CONFIG_LAN) || defined(CONFIG_HLAN) || defined(CONFIG_HGLAN) ++#define CFG_IDE_MAXBUS 1 /* Scan only 1 IDE bus */ ++#define CFG_IDE_MAXDEVICE 1 /* Only 1 drive per IDE bus */ ++#elif defined(CONFIG_HGTL) ++#define CFG_IDE_MAXBUS 2 /* Max. 2 IDE busses */ ++#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ ++#else ++#error Config IDE: Unknown LinkStation type ++#endif ++ ++#define CFG_ATA_BASE_ADDR 0 ++ ++#define CFG_ATA_DATA_OFFSET 0 /* Offset for data I/O */ ++#define CFG_ATA_REG_OFFSET 0 /* Offset for normal registers */ ++#define CFG_ATA_ALT_OFFSET 0 /* Offset for alternate registers */ ++ ++/*----------------------------------------------------------------------- ++ * Partitions and file system ++ */ ++#define CONFIG_DOS_PARTITION ++ ++/*----------------------------------------------------------------------- ++ * Internal Definitions ++ * ++ * Boot Flags ++ */ ++#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ ++#define BOOTFLAG_WARM 0x02 /* Software reboot */ ++ ++#endif /* __CONFIG_H */ ++ ++/* vim: set ts=4: */ +diff -urN u-boot-86xx/include/devices.h u-boot-86xx-kuro_clean/include/devices.h +--- u-boot-86xx/include/devices.h 2006-10-13 00:27:18.000000000 +0200 ++++ u-boot-86xx-kuro_clean/include/devices.h 2006-11-06 22:05:38.000000000 +0100 +@@ -93,6 +93,7 @@ + int devices_init (void); + int devices_done (void); + int device_deregister(char *devname); ++int console_setfile (int file, device_t * dev); + #ifdef CONFIG_LCD + int drv_lcd_init (void); + #endif +@@ -111,5 +112,8 @@ + #ifdef CONFIG_NETCONSOLE + int drv_nc_init (void); + #endif ++#if defined(CFG_CONSOLE_IS_IN_ENV) || defined(CONFIG_SPLASH_SCREEN) || defined(CONFIG_SILENT_CONSOLE) ++device_t *search_device (int flags, char *name); ++#endif + + #endif /* _DEVICES_H_ */ +diff -urN u-boot-86xx/include/flash.h u-boot-86xx-kuro_clean/include/flash.h +--- u-boot-86xx/include/flash.h 2006-10-13 00:27:18.000000000 +0200 ++++ u-boot-86xx-kuro_clean/include/flash.h 2006-11-06 22:05:38.000000000 +0100 +@@ -215,6 +215,8 @@ + + #define AMD_ID_LV320B_2 0x221A221A /* 2d ID word for AM29LV320MB at 0x38 */ + #define AMD_ID_LV320B_3 0x22002200 /* 3d ID word for AM29LV320MB at 0x3c */ ++#define AMD_ID_LV320T_2 0x221A221A /* 2d ID word for AM29LV320MT at 0x38 */ ++#define AMD_ID_LV320T_3 0x22012201 /* 3d ID word for AM29LV320MT at 0x3c */ + + #define AMD_ID_LV640U 0x22D722D7 /* 29LV640U ID (64 M, uniform sectors) */ + #define AMD_ID_LV650U 0x22D722D7 /* 29LV650U ID (64 M, uniform sectors) */ +@@ -246,6 +248,8 @@ + #define STM_ID_x800AB 0x005B005B /* M29W800AB ID (8M = 512K x 16 ) */ + #define STM_ID_29W320DT 0x22CA22CA /* M29W320DT ID (32 M, top boot sector) */ + #define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect) */ ++#define STM_ID_29W324DT 0x225C225C /* M29W324DT ID (32 M, top boot sector) */ ++#define STM_ID_29W324DB 0x225D225D /* M29W324DB ID (32 M, bottom boot sect) */ + #define STM_ID_29W040B 0x00E300E3 /* M29W040B ID (4M = 512K x 8) */ + #define FLASH_PSD4256GV 0x00E9 /* PSD4256 Flash and CPLD combination */ + +@@ -353,6 +357,8 @@ + #define FLASH_STM800AB 0x0051 /* STM M29WF800AB ( 8M = 512K x 16 ) */ + #define FLASH_STMW320DT 0x0052 /* STM M29W320DT (32 M, top boot sector) */ + #define FLASH_STMW320DB 0x0053 /* STM M29W320DB (32 M, bottom boot sect)*/ ++#define FLASH_STMW324DT 0x005C /* STM M29W320DT (32 M, top boot sector) */ ++#define FLASH_STMW324DB 0x005D /* STM M29W320DB (32 M, bottom boot sect)*/ + #define FLASH_STM320DB 0x00CB /* STM M29W320DB (4M = 64K x 64, bottom)*/ + #define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */ + #define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom)*/ +diff -urN u-boot-86xx/include/pci_ids.h u-boot-86xx-kuro_clean/include/pci_ids.h +--- u-boot-86xx/include/pci_ids.h 2006-10-13 00:27:18.000000000 +0200 ++++ u-boot-86xx-kuro_clean/include/pci_ids.h 2006-11-06 22:05:38.000000000 +0100 +@@ -1473,6 +1473,8 @@ + #define PCI_DEVICE_ID_ITE_IT8172G_AUDIO 0x0801 + #define PCI_DEVICE_ID_ITE_IT8181 0x8181 + #define PCI_DEVICE_ID_ITE_8872 0x8872 ++#define PCI_DEVICE_ID_ITE_8211 0x8211 ++#define PCI_DEVICE_ID_ITE_8212 0x8212 + + #define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886 + +diff -urN u-boot-86xx/lib_ppc/board.c u-boot-86xx-kuro_clean/lib_ppc/board.c +--- u-boot-86xx/lib_ppc/board.c 2006-10-13 00:27:19.000000000 +0200 ++++ u-boot-86xx-kuro_clean/lib_ppc/board.c 2006-11-06 22:05:38.000000000 +0100 +@@ -439,6 +439,10 @@ + */ + addr -= len; + addr &= ~(4096 - 1); ++#ifdef CONFIG_LINKSTATION ++ /* U-Boot code at 1 MB boundary to make it easier to debug */ ++ addr &= ~(1048576 - 1); ++#endif + #ifdef CONFIG_E500 + /* round down to next 64 kB limit so that IVPR stays aligned */ + addr &= ~(65536 - 1); +@@ -895,8 +899,10 @@ + /* Initialize the jump table for applications */ + jumptable_init (); + ++#if !defined(CONFIG_LINKSTATION) + /* Initialize the console (after the relocation and devices init) */ + console_init_r (); ++#endif + + #if defined(CONFIG_CCM) || \ + defined(CONFIG_COGENT) || \ +@@ -949,6 +955,7 @@ + if ((s = getenv ("loadaddr")) != NULL) { + load_addr = simple_strtoul (s, NULL, 16); + } ++ debug("load_addr: %08lx\n", load_addr); + #if (CONFIG_COMMANDS & CFG_CMD_NET) + if ((s = getenv ("bootfile")) != NULL) { + copy_filename (BootFile, s, sizeof (BootFile)); +@@ -998,6 +1005,11 @@ + reset_phy (); + #endif + ++#if defined(CONFIG_LINKSTATION) ++ /* The LinkStation uses the net console by default */ ++ console_init_r (); ++#endif ++ + #ifdef CONFIG_POST + post_run (NULL, POST_RAM | post_bootmode_get(0)); + #endif +diff -urN u-boot-86xx/lib_ppc/interrupts.c u-boot-86xx-kuro_clean/lib_ppc/interrupts.c +--- u-boot-86xx/lib_ppc/interrupts.c 2006-10-13 00:27:19.000000000 +0200 ++++ u-boot-86xx-kuro_clean/lib_ppc/interrupts.c 2006-11-06 22:05:38.000000000 +0100 +@@ -40,7 +40,7 @@ + #endif + + extern int interrupt_init_cpu (unsigned *); +-extern void timer_interrupt_cpu (struct pt_regs *); ++extern void timer_interrupt_cpu (struct pt_regs *, ulong timestamp); + + static unsigned decrementer_count; /* count value for 1e6/HZ microseconds */ + +@@ -111,7 +111,7 @@ + void timer_interrupt (struct pt_regs *regs) + { + /* call cpu specific function from $(CPU)/interrupts.c */ +- timer_interrupt_cpu (regs); ++ timer_interrupt_cpu (regs, timestamp); + + /* Restore Decrementer Count */ + set_dec (decrementer_count); +diff -urN u-boot-86xx/net/net.c u-boot-86xx-kuro_clean/net/net.c +--- u-boot-86xx/net/net.c 2006-10-13 00:27:19.000000000 +0200 ++++ u-boot-86xx-kuro_clean/net/net.c 2006-11-06 22:05:38.000000000 +0100 +@@ -641,6 +641,11 @@ + { + uchar *pkt; + ++#ifdef ET_DEBUG ++ printf("%s dest: %08lx, dport: %d, sport: %d, len: %d\n", ++ __FUNCTION__, dest, dport, sport, len); ++#endif ++ + /* convert to new style broadcast */ + if (dest == 0) + dest = 0xFFFFFFFF; +@@ -758,6 +763,8 @@ + IPaddr_t tmp; + volatile IP_t *ip = (volatile IP_t *)pkt; + ++ if (!pkt && !dest && !src && !len) /* ARP packet */ ++ return; + tmp = NetReadIP((void *)&ip->ip_src); + if (tmp != NetPingIP) + return; +@@ -1146,7 +1153,7 @@ + ushort cti = 0, vlanid = VLAN_NONE, myvlanid, mynvlanid; + + #ifdef ET_DEBUG +- printf("packet received\n"); ++ printf("%s: packet received\n", __FUNCTION__); + #endif + + NetRxPkt = inpkt; +@@ -1171,10 +1178,6 @@ + + x = ntohs(et->et_protlen); + +-#ifdef ET_DEBUG +- printf("packet received\n"); +-#endif +- + if (x < 1514) { + /* + * Got a 802 packet. Check the other protocol field. +@@ -1305,13 +1308,16 @@ + /* matched waiting packet's address */ + if (tmp == NetArpWaitReplyIP) { + #ifdef ET_DEBUG +- puts ("Got it\n"); ++ puts ("ARP reply IP matches original pkt IP\n"); + #endif + /* save address for later use */ + memcpy(NetArpWaitPacketMAC, &arp->ar_data[0], 6); + + #ifdef CONFIG_NETCONSOLE +- (*packetHandler)(0,0,0,0); ++ if (packetHandler) ++ (*packetHandler)(0,0,0,0); ++ else ++ printf("ARP: NULL packetHandler\n"); + #endif + /* modify header, and transmit it */ + memcpy(((Ethernet_t *)NetArpWaitTxPacket)->et_dest, NetArpWaitPacketMAC, 6); +@@ -1354,7 +1360,10 @@ + NetCopyIP(&NetServerIP, &arp->ar_data[ 6]); + memcpy (NetServerEther, &arp->ar_data[ 0], 6); + +- (*packetHandler)(0,0,0,0); ++ if (packetHandler) ++ (*packetHandler)(0,0,0,0); ++ else ++ printf("ARP: NULL packetHandler\n"); + } + break; + +diff -urN u-boot-86xx/net/nfs.c u-boot-86xx-kuro_clean/net/nfs.c +--- u-boot-86xx/net/nfs.c 2006-10-13 00:27:19.000000000 +0200 ++++ u-boot-86xx-kuro_clean/net/nfs.c 2006-11-06 22:05:38.000000000 +0100 +@@ -29,7 +29,7 @@ + #include "nfs.h" + #include "bootp.h" + +-/*#define NFS_DEBUG*/ ++#undef NFS_DEBUG + + #if ((CONFIG_COMMANDS & CFG_CMD_NET) && (CONFIG_COMMANDS & CFG_CMD_NFS)) + +@@ -180,6 +180,9 @@ + int sport; + + id = ++rpc_id; ++#ifdef NFS_DEBUG ++ printf ("%s xid: %d, rpc_id: %d\n", __FUNCTION__, id, rpc_id); ++#endif + pkt.u.call.id = htonl(id); + pkt.u.call.type = htonl(MSG_CALL); + pkt.u.call.rpcvers = htonl(2); /* use RPC version 2 */ +@@ -213,6 +216,10 @@ + { + uint32_t data[16]; + ++#ifdef NFS_DEBUG ++ printf ("%s\n", __FUNCTION__); ++#endif ++ + data[0] = 0; data[1] = 0; /* auth credential */ + data[2] = 0; data[3] = 0; /* auth verifier */ + data[4] = htonl(prog); +@@ -234,6 +241,10 @@ + int len; + int pathlen; + ++#ifdef NFS_DEBUG ++ printf ("%s\n", __FUNCTION__); ++#endif ++ + pathlen = strlen (path); + + p = &(data[0]); +@@ -259,6 +270,10 @@ + uint32_t *p; + int len; + ++#ifdef NFS_DEBUG ++ printf ("%s\n", __FUNCTION__); ++#endif ++ + if ((NfsSrvMountPort == -1) || (!fs_mounted)) { + /* Nothing mounted, nothing to umount */ + return; +@@ -286,6 +301,10 @@ + uint32_t *p; + int len; + ++#ifdef NFS_DEBUG ++ printf ("%s\n", __FUNCTION__); ++#endif ++ + p = &(data[0]); + p = (uint32_t *)rpc_add_credentials ((long *)p); + +@@ -308,6 +327,10 @@ + int len; + int fnamelen; + ++#ifdef NFS_DEBUG ++ printf ("%s\n", __FUNCTION__); ++#endif ++ + fnamelen = strlen (fname); + + p = &(data[0]); +@@ -335,6 +358,10 @@ + uint32_t *p; + int len; + ++#ifdef NFS_DEBUG ++ printf ("%s\n", __FUNCTION__); ++#endif ++ + p = &(data[0]); + p = (uint32_t *)rpc_add_credentials ((long *)p); + +@@ -405,8 +432,13 @@ + + if (rpc_pkt.u.reply.rstatus || + rpc_pkt.u.reply.verifier || +- rpc_pkt.u.reply.astatus || + rpc_pkt.u.reply.astatus) { ++#ifdef NFS_DEBUG ++ printf ("rstatus: %d\n", rpc_pkt.u.reply.rstatus); ++ printf ("verifier: %08lx\n", rpc_pkt.u.reply.verifier); ++ printf ("v2: %08lx\n", rpc_pkt.u.reply.v2); ++ printf ("astatus: %d\n", rpc_pkt.u.reply.astatus); ++#endif + return -1; + } + +@@ -433,13 +465,24 @@ + + memcpy ((unsigned char *)&rpc_pkt, pkt, len); + +- if (ntohl(rpc_pkt.u.reply.id) != rpc_id) ++ if (ntohl(rpc_pkt.u.reply.id) != rpc_id) { ++#ifdef NFS_DEBUG ++ printf ("rpc_id error. expected: %d, got: %d\n", \ ++ rpc_id, ntohl(rpc_pkt.u.reply.id)); ++#endif + return -1; ++ } + + if (rpc_pkt.u.reply.rstatus || + rpc_pkt.u.reply.verifier || + rpc_pkt.u.reply.astatus || + rpc_pkt.u.reply.data[0]) { ++#ifdef NFS_DEBUG ++ printf ("rstatus: %d\n", rpc_pkt.u.reply.rstatus); ++ printf ("verifier: %08lx\n", rpc_pkt.u.reply.verifier); ++ printf ("astatus: %d\n", rpc_pkt.u.reply.astatus); ++ printf ("data[0]: %08lx\n", rpc_pkt.u.reply.data[0]); ++#endif + return -1; + } + +@@ -544,7 +587,7 @@ + struct rpc_t rpc_pkt; + int rlen; + +-#ifdef NFS_DEBUG_nop ++#ifdef NFS_DEBUG + printf ("%s\n", __FUNCTION__); + #endif + +@@ -601,6 +644,8 @@ + printf ("%s\n", __FUNCTION__); + #endif + ++ if (!pkt && !dest && !src && !len) /* ARP packet */ ++ return; + if (dest != NfsOurPort) return; + + switch (NfsState) { +diff -urN u-boot-86xx/tools/Makefile u-boot-86xx-kuro_clean/tools/Makefile +--- u-boot-86xx/tools/Makefile 2006-10-13 00:27:19.000000000 +0200 ++++ u-boot-86xx-kuro_clean/tools/Makefile 2006-11-06 22:18:42.000000000 +0100 +@@ -21,10 +21,10 @@ + # MA 02111-1307 USA + # + +-BIN_FILES = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX) ++BIN_FILES = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX) ncb$(SFX) + + OBJ_LINKS = environment.o crc32.o +-OBJ_FILES = img2srec.o mkimage.o envcrc.o gen_eth_addr.o bmp_logo.o ++OBJ_FILES = img2srec.o mkimage.o envcrc.o gen_eth_addr.o bmp_logo.o ncb.o + + ifeq ($(ARCH),mips) + BIN_FILES += inca-swap-bytes$(SFX) diff --git a/packages/u-boot/u-boot-1.2.0/uboot-qnap.diff b/packages/u-boot/u-boot-1.2.0/uboot-qnap.diff new file mode 100644 index 0000000000..2b2a17da7f --- /dev/null +++ b/packages/u-boot/u-boot-1.2.0/uboot-qnap.diff @@ -0,0 +1,1100 @@ +--- u-boot-1.2.0.vanilla/board/qnap/config.mk 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.2.0/board/qnap/config.mk 2007-02-26 01:55:37.000000000 +0100 +@@ -0,0 +1,35 @@ ++# ++# (C) Copyright 2000, 2001 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++# Valid values for TEXT_BASE are: ++# ++# Standard configuration ++# 0xFFF00000 boot from flash ++# ++# Standard configuration ++# 0xFFE60000 chain boot from flash ++# ++ ++ ++TEXT_BASE = 0xFFE60000 ++ ++PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) +--- u-boot-1.2.0.vanilla/board/qnap/ide.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.2.0/board/qnap/ide.c 2007-02-26 01:55:37.000000000 +0100 +@@ -0,0 +1,67 @@ ++/* ++ * (C) Copyright 2000 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++ #include ++ ++#ifdef CFG_CMD_IDE ++#include ++#include ++#include ++ ++extern ulong ide_bus_offset[CFG_IDE_MAXBUS]; ++extern struct pci_controller hose; ++ ++int ide_preinit (void) ++{ ++ int status; ++ pci_dev_t devbusfn; ++ int l; ++ ++ status = 1; ++ for (l = 0; l < CFG_IDE_MAXBUS; l++) { ++ ide_bus_offset[l] = -ATA_STATUS; ++ } ++ devbusfn = pci_find_device (0x1095, 0x3512, 0); ++ ++ if (devbusfn != -1) { ++ ++ status = 0; ++ ++ pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, ++ (u32 *) &ide_bus_offset[0]); ++ ide_bus_offset[0] &= 0xfffffffe; ++ ide_bus_offset[0] = pci_hose_bus_to_phys(&hose, ++ ide_bus_offset[0] & 0xfffffffe, ++ PCI_REGION_IO); ++ ++ pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2, ++ (u32 *) &ide_bus_offset[1]); ++ ide_bus_offset[1] &= 0xfffffffe; ++ ide_bus_offset[1] = pci_hose_bus_to_phys(&hose, ++ ide_bus_offset[1] & 0xfffffffe, ++ PCI_REGION_IO); ++ } ++ return (status); ++} ++ ++#endif /* of CONFIG_CMDS_IDE */ +--- u-boot-1.2.0.vanilla/board/qnap/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.2.0/board/qnap/Makefile 2007-02-26 01:55:37.000000000 +0100 +@@ -0,0 +1,40 @@ ++# ++# (C) Copyright 2000 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = lib$(BOARD).a ++ ++OBJS = $(BOARD).o ide.o ++ ++$(LIB): .depend $(OBJS) ++ $(AR) crv $@ $(OBJS) ++ ++######################################################################### ++ ++.depend: Makefile $(OBJS:.o=.c) ++ $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ ++ ++sinclude .depend ++ ++######################################################################### +--- u-boot-1.2.0.vanilla/board/qnap/qnap.c 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.2.0/board/qnap/qnap.c 2007-02-26 01:55:37.000000000 +0100 +@@ -0,0 +1,126 @@ ++/* ++ * Copyright (C) 2006 Andrew Luyten ++ * ++ * Copyright (C) 2000 ++ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++ ++#include ++#include ++#include ++ ++int checkboard (void) ++{ ++ ulong busfreq = get_bus_freq(0); ++ char buf[32]; ++ ++ printf("Board: QNAP TS-101/TS-201 local bus at %s MHz\n", strmhz(buf, busfreq)); ++ return 0; ++} ++ ++ ++long int initdram (int board_type) ++{ ++ long size; ++ long new_bank0_end; ++ long mear1; ++ long emear1; ++ ++ size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); ++ ++ new_bank0_end = size - 1; ++ mear1 = mpc824x_mpc107_getreg(MEAR1); ++ emear1 = mpc824x_mpc107_getreg(EMEAR1); ++ mear1 = (mear1 & 0xFFFFFF00) | ++ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); ++ emear1 = (emear1 & 0xFFFFFF00) | ++ ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); ++ mpc824x_mpc107_setreg(MEAR1, mear1); ++ mpc824x_mpc107_setreg(EMEAR1, emear1); ++ ++ return (size); ++} ++ ++/* ++ * Initialize PCI Devices, report devices found. ++ */ ++#ifndef CONFIG_PCI_PNP ++ ++static struct pci_config_table pci_qnap_config_table[] = { ++ /* vendor, device, class */ ++ /* bus, dev, func */ ++ ++ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, ++ PCI_ANY_ID, 0x0f, 0, /* RTL8110SC or Intel 82540EM */ ++ /* Gigabit ethernet controller */ ++ pci_cfgfunc_config_device, { PCI_ETH_IOADDR, ++ PCI_ETH_MEMADDR, ++ PCI_COMMAND_IO | ++ PCI_COMMAND_MEMORY | ++ PCI_COMMAND_MASTER }}, ++ ++ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, ++ PCI_ANY_ID, 0x0d, 0, /* SII3512 */ ++ /* SATA controller */ ++ pci_cfgfunc_config_device, { PCI_IDE_IOADDR, ++ PCI_IDE_MEMADDR, ++ PCI_COMMAND_IO | ++ PCI_COMMAND_MEMORY | ++ PCI_COMMAND_MASTER }}, ++ ++ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, ++ PCI_ANY_ID, 0x0e, 0, /* D720101 USB controller, 1st USB 1.1 */ ++ pci_cfgfunc_config_device, { PCI_USB0_IOADDR, ++ PCI_USB0_MEMADDR, ++ PCI_COMMAND_MEMORY | ++ PCI_COMMAND_MASTER }}, ++ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, ++ PCI_ANY_ID, 0x0e, 1, /* D720101 USB controller, 2nd USB 1.1 */ ++ pci_cfgfunc_config_device, { PCI_USB1_IOADDR, ++ PCI_USB1_MEMADDR, ++ PCI_COMMAND_MEMORY | ++ PCI_COMMAND_MASTER }}, ++ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, ++ PCI_ANY_ID, 0x0e, 2, /* D720101 USB controller, USB 2.0 */ ++ pci_cfgfunc_config_device, { PCI_USB2_IOADDR, ++ PCI_USB2_MEMADDR, ++ PCI_COMMAND_MEMORY | ++ PCI_COMMAND_MASTER }}, ++ { } ++}; ++#endif ++ ++struct pci_controller hose = { ++#ifndef CONFIG_PCI_PNP ++ config_table: pci_qnap_config_table, ++#endif ++}; ++ ++void pci_init_board(void) ++{ ++ pci_mpc824x_init(&hose); ++ ++ /* Reset USB 1.1 !/ ++ out_le32(PCI_USB0_MEMADDR+8, 1); ++ out_le32(PCI_USB1_MEMADDR+8, 1); ++ */ ++} +--- u-boot-1.2.0.vanilla/board/qnap/README 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.2.0/board/qnap/README 2007-02-26 01:55:37.000000000 +0100 +@@ -0,0 +1,10 @@ ++*This port of U-Boot will run on a QNAP TS-101/TS-201 NAS* ++Andrew Luyten (u-boot@luyten.org.uk) ++ ++Adapted from a Linkstation port by Mihai Georgian ++http://http://www.linuxnotincluded.org.uk/ ++ ++Adapted from Motorola Sandpoint 3 development system equipped with ++a Unity X4 PPMC card (MPC8240 CPU) only. It is a snapshot of work ++in progress and far from being completed. ++Thomas Koeller +--- u-boot-1.2.0.vanilla/board/qnap/u-boot.lds 1970-01-01 01:00:00.000000000 +0100 ++++ u-boot-1.2.0/board/qnap/u-boot.lds 2007-02-26 01:55:37.000000000 +0100 +@@ -0,0 +1,136 @@ ++/* ++ * (C) Copyright 2001 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_ARCH(powerpc) ++SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); ++/* Do we need any of these for elf? ++ __DYNAMIC = 0; */ ++SECTIONS ++{ ++ /* Read-only sections, merged into text segment: */ ++ . = + SIZEOF_HEADERS; ++ .interp : { *(.interp) } ++ .hash : { *(.hash) } ++ .dynsym : { *(.dynsym) } ++ .dynstr : { *(.dynstr) } ++ .rel.text : { *(.rel.text) } ++ .rela.text : { *(.rela.text) } ++ .rel.data : { *(.rel.data) } ++ .rela.data : { *(.rela.data) } ++ .rel.rodata : { *(.rel.rodata) } ++ .rela.rodata : { *(.rela.rodata) } ++ .rel.got : { *(.rel.got) } ++ .rela.got : { *(.rela.got) } ++ .rel.ctors : { *(.rel.ctors) } ++ .rela.ctors : { *(.rela.ctors) } ++ .rel.dtors : { *(.rel.dtors) } ++ .rela.dtors : { *(.rela.dtors) } ++ .rel.bss : { *(.rel.bss) } ++ .rela.bss : { *(.rela.bss) } ++ .rel.plt : { *(.rel.plt) } ++ .rela.plt : { *(.rela.plt) } ++ .init : { *(.init) } ++ .plt : { *(.plt) } ++ .text : ++ { ++ cpu/mpc824x/start.o (.text) ++ lib_ppc/board.o (.text) ++ lib_ppc/ppcstring.o (.text) ++ lib_generic/vsprintf.o (.text) ++ lib_generic/crc32.o (.text) ++ lib_generic/zlib.o (.text) ++ ++ . = DEFINED(env_offset) ? env_offset : .; ++ common/environment.o (.text) ++ ++ *(.text) ++ ++ *(.fixup) ++ *(.got1) ++ . = ALIGN(16); ++ *(.rodata) ++ *(.rodata1) ++ *(.rodata.str1.4) ++ *(.eh_frame) ++ } ++ .fini : { *(.fini) } =0 ++ .ctors : { *(.ctors) } ++ .dtors : { *(.dtors) } ++ ++ /* Read-write section, merged into data segment: */ ++ . = (. + 0x0FFF) & 0xFFFFF000; ++ _erotext = .; ++ PROVIDE (erotext = .); ++ .reloc : ++ { ++ *(.got) ++ _GOT2_TABLE_ = .; ++ *(.got2) ++ _FIXUP_TABLE_ = .; ++ *(.fixup) ++ } ++ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; ++ __fixup_entries = (. - _FIXUP_TABLE_) >> 2; ++ ++ .data : ++ { ++ *(.data) ++ *(.data1) ++ *(.sdata) ++ *(.sdata2) ++ *(.dynamic) ++ CONSTRUCTORS ++ } ++ _edata = .; ++ PROVIDE (edata = .); ++ ++ . = .; ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ ++ . = .; ++ __start___ex_table = .; ++ __ex_table : { *(__ex_table) } ++ __stop___ex_table = .; ++ ++ . = ALIGN(4096); ++ __init_begin = .; ++ .text.init : { *(.text.init) } ++ .data.init : { *(.data.init) } ++ . = ALIGN(4096); ++ __init_end = .; ++ ++ __bss_start = .; ++ .bss : ++ { ++ *(.sbss) *(.scommon) ++ *(.dynbss) ++ *(.bss) ++ *(COMMON) ++ } ++ ++ _end = . ; ++ PROVIDE (end = .); ++} +--- u-boot-1.2.0.vanilla/cpu/mpc824x/cpu.c 2007-01-07 00:13:11.000000000 +0100 ++++ u-boot-1.2.0/cpu/mpc824x/cpu.c 2007-02-26 01:55:37.000000000 +0100 +@@ -44,7 +44,11 @@ + break; + + case CPU_TYPE_8245: ++#ifdef CONFIG_MPC8241 ++ puts ("MPC8241"); /* impossible to distinguish using chip registers */ ++#else + puts ("MPC8245"); ++#endif + break; + + default: +--- u-boot-1.2.0.vanilla/drivers/rtl8169.c 2007-01-07 00:13:11.000000000 +0100 ++++ u-boot-1.2.0/drivers/rtl8169.c 2007-02-26 01:55:37.000000000 +0100 +@@ -48,7 +48,10 @@ + * + * Indent Options: indent -kr -i8 + ***************************************************************************/ +- ++/* ++ * 26 August 2006 Mihai Georgian ++ * Modified to use le32_to_cpu and cpu_to_le32 properly ++ */ + #include + #include + #include +@@ -68,6 +71,7 @@ + static u32 ioaddr; + + /* Condensed operations for readability. */ ++#define virt_to_bus(addr) cpu_to_le32(addr) + #define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr)) + #define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr)) + +@@ -247,8 +251,15 @@ + u8 version; /* depend on RTL8169 docs */ + u32 RxConfigMask; /* should clear the bits supported by this chip */ + } rtl_chip_info[] = { +- {"RTL-8169", 0x00, 0xff7e1880,}, +- {"RTL-8169", 0x04, 0xff7e1880,}, ++ {"RTL8169", 0x00, 0xff7e1880,}, ++ {"RTL8169s/8110s", 0x02, 0xff7e1880,}, ++ {"RTL8169s/8110s", 0x04, 0xff7e1880,}, ++ {"RTL8169sb/8110sb", 0x10, 0xff7e1880,}, ++ {"RTL8169sc/8110sc", 0x18, 0xff7e1880,}, ++ {"RTL8168b/8111sb", 0x30, 0xff7e1880,}, ++ {"RTL8168b/8111sb", 0x38, 0xff7e1880,}, ++ {"RTL8101e", 0x34, 0xff7e1880,}, ++ {"RTL8100e", 0x32, 0xff7e1880,}, + }; + + enum _DescStatusBit { +@@ -315,6 +326,7 @@ + + static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_REALTEK, 0x8169}, ++ {PCI_VENDOR_ID_REALTEK, 0x8167}, + {} + }; + +@@ -383,13 +395,15 @@ + for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ + if (tmp == rtl_chip_info[i].version) { + tpc->chipset = i; ++ printf ("%s... ", rtl_chip_info[i].name); + goto match; + } + } + + /* if unknown chip, assume array element #0, original RTL-8169 in this case */ + printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name); +- printf("PCI device: TxConfig = 0x%hX\n", (unsigned long) RTL_R32(TxConfig)); ++ printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig)); ++ + tpc->chipset = 0; + + match: +@@ -413,23 +427,23 @@ + ioaddr = dev->iobase; + + cur_rx = tpc->cur_rx; +- if ((tpc->RxDescArray[cur_rx].status & OWNbit) == 0) { +- if (!(tpc->RxDescArray[cur_rx].status & RxRES)) { ++ if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { ++ if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { + unsigned char rxdata[RX_BUF_LEN]; +- length = (int) (tpc->RxDescArray[cur_rx]. +- status & 0x00001FFF) - 4; ++ length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. ++ status) & 0x00001FFF) - 4; + + memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); + NetReceive(rxdata, length); + + if (cur_rx == NUM_RX_DESC - 1) + tpc->RxDescArray[cur_rx].status = +- (OWNbit | EORbit) + RX_BUF_SIZE; ++ cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); + else + tpc->RxDescArray[cur_rx].status = +- OWNbit + RX_BUF_SIZE; ++ cpu_to_le32(OWNbit + RX_BUF_SIZE); + tpc->RxDescArray[cur_rx].buf_addr = +- virt_to_bus(tpc->RxBufferRing[cur_rx]); ++ cpu_to_le32((u32)tpc->RxBufferRing[cur_rx]); + } else { + puts("Error Rx"); + } +@@ -454,6 +468,7 @@ + u8 *ptxb; + int entry = tpc->cur_tx % NUM_TX_DESC; + u32 len = length; ++ int ret; + + #ifdef DEBUG_RTL8169_TX + int stime = currticks(); +@@ -465,39 +480,46 @@ + + /* point to the current txb incase multiple tx_rings are used */ + ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; ++#ifdef DEBUG_RTL8169_TX ++ printf("ptxb: %08X, length: %d\n", ptxb, (int)length); ++#endif + memcpy(ptxb, (char *)packet, (int)length); + + while (len < ETH_ZLEN) + ptxb[len++] = '\0'; + +- tpc->TxDescArray[entry].buf_addr = virt_to_bus(ptxb); ++ tpc->TxDescArray[entry].buf_addr = cpu_to_le32((u32)ptxb); + if (entry != (NUM_TX_DESC - 1)) { + tpc->TxDescArray[entry].status = +- (OWNbit | FSbit | LSbit) | ((len > ETH_ZLEN) ? +- len : ETH_ZLEN); ++ cpu_to_le32((OWNbit | FSbit | LSbit) | ++ ((len > ETH_ZLEN) ? len : ETH_ZLEN)); + } else { + tpc->TxDescArray[entry].status = +- (OWNbit | EORbit | FSbit | LSbit) | +- ((len > ETH_ZLEN) ? length : ETH_ZLEN); ++ cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | ++ ((len > ETH_ZLEN) ? len : ETH_ZLEN)); + } + RTL_W8(TxPoll, 0x40); /* set polling bit */ + + tpc->cur_tx++; + to = currticks() + TX_TIMEOUT; +- while ((tpc->TxDescArray[entry].status & OWNbit) && (currticks() < to)); /* wait */ ++ while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) ++ && (currticks() < to)); /* wait */ + + if (currticks() >= to) { + #ifdef DEBUG_RTL8169_TX + puts ("tx timeout/error\n"); + printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); + #endif +- return 0; ++ ret = 0; + } else { + #ifdef DEBUG_RTL8169_TX + puts("tx done\n"); + #endif +- return length; ++ ret = length; + } ++ /* Delay to make net console (nc) work properly */ ++ udelay(20); ++ return ret; + } + + static void rtl8169_set_rx_mode(struct eth_device *dev) +@@ -564,8 +586,8 @@ + + tpc->cur_rx = 0; + +- RTL_W32(TxDescStartAddr, virt_to_le32desc(tpc->TxDescArray)); +- RTL_W32(RxDescStartAddr, virt_to_le32desc(tpc->RxDescArray)); ++ RTL_W32(TxDescStartAddr, virt_to_le32desc((u32)tpc->TxDescArray)); ++ RTL_W32(RxDescStartAddr, virt_to_le32desc((u32)tpc->RxDescArray)); + RTL_W8(Cfg9346, Cfg9346_Lock); + udelay(10); + +@@ -603,13 +625,14 @@ + for (i = 0; i < NUM_RX_DESC; i++) { + if (i == (NUM_RX_DESC - 1)) + tpc->RxDescArray[i].status = +- (OWNbit | EORbit) + RX_BUF_SIZE; ++ cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); + else +- tpc->RxDescArray[i].status = OWNbit + RX_BUF_SIZE; ++ tpc->RxDescArray[i].status = ++ cpu_to_le32(OWNbit + RX_BUF_SIZE); + + tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; + tpc->RxDescArray[i].buf_addr = +- virt_to_bus(tpc->RxBufferRing[i]); ++ cpu_to_le32((u32)tpc->RxBufferRing[i]); + } + + #ifdef DEBUG_RTL8169 +@@ -620,7 +643,7 @@ + /************************************************************************** + RESET - Finish setting up the ethernet interface + ***************************************************************************/ +-static void rtl_reset(struct eth_device *dev, bd_t *bis) ++static int rtl_reset(struct eth_device *dev, bd_t *bis) + { + int i; + u8 diff; +@@ -635,21 +658,27 @@ + if (tpc->TxDescArrays == 0) + puts("Allot Error"); + /* Tx Desscriptor needs 256 bytes alignment; */ +- TxPhyAddr = virt_to_bus(tpc->TxDescArrays); ++ TxPhyAddr = (u32)tpc->TxDescArrays; + diff = 256 - (TxPhyAddr - ((TxPhyAddr >> 8) << 8)); + TxPhyAddr += diff; + tpc->TxDescArray = (struct TxDesc *) (tpc->TxDescArrays + diff); ++#ifdef DEBUG_RTL8169 ++ printf("tpc->TxDescArray: %08X\n", tpc->TxDescArray); ++#endif + + tpc->RxDescArrays = rx_ring; + /* Rx Desscriptor needs 256 bytes alignment; */ +- RxPhyAddr = virt_to_bus(tpc->RxDescArrays); ++ RxPhyAddr = (u32)tpc->RxDescArrays; + diff = 256 - (RxPhyAddr - ((RxPhyAddr >> 8) << 8)); + RxPhyAddr += diff; + tpc->RxDescArray = (struct RxDesc *) (tpc->RxDescArrays + diff); ++#ifdef DEBUG_RTL8169 ++ printf("tpc->RxDescArray: %08X\n", tpc->RxDescArray); ++#endif + + if (tpc->TxDescArrays == NULL || tpc->RxDescArrays == NULL) { + puts("Allocate RxDescArray or TxDescArray failed\n"); +- return; ++ return 0; + } + + rtl8169_init_ring(dev); +@@ -669,6 +698,7 @@ + #ifdef DEBUG_RTL8169 + printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); + #endif ++ return 1; + } + + /************************************************************************** +@@ -733,7 +763,7 @@ + + /* Get MAC address. FIXME: read EEPROM */ + for (i = 0; i < MAC_ADDR_LEN; i++) +- dev->enetaddr[i] = RTL_R8(MAC0 + i); ++ bis->bi_enetaddr[i] = dev->enetaddr[i] = RTL_R8(MAC0 + i); + + #ifdef DEBUG_RTL8169 + printf("MAC Address"); +@@ -814,17 +844,14 @@ + if (option & _1000bpsF) { + #ifdef DEBUG_RTL8169 + printf("%s: 1000Mbps Full-duplex operation.\n", +- dev->name); ++ dev->name); + #endif + } else { + #ifdef DEBUG_RTL8169 +- printf +- ("%s: %sMbps %s-duplex operation.\n", +- dev->name, +- (option & _100bps) ? "100" : +- "10", +- (option & FullDup) ? "Full" : +- "Half"); ++ printf("%s: %sMbps %s-duplex operation.\n", ++ dev->name, ++ (option & _100bps) ? "100" : "10", ++ (option & FullDup) ? "Full" : "Half"); + #endif + } + break; +@@ -886,3 +913,5 @@ + } + + #endif ++ ++/* vim: set ts=4: */ +Index: u-boot-1.2.0/include/configs/qnap.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ u-boot-1.2.0/include/configs/qnap.h 2007-04-07 21:56:55.376393000 +0200 +@@ -0,0 +1,363 @@ ++/* ++ * Copyright (C) 2006 Andrew Luyten ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* ------------------------------------------------------------------------- */ ++ ++/* ++ * board/config.h - configuration options, board specific ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++/* ++ * High Level Configuration Options ++ * (easy to change) ++ */ ++ ++#define CONFIG_MPC824X 1 ++#define CONFIG_MPC8245 1 ++#define CONFIG_MPC8241 1 ++ ++#define CONFIG_IDENT_STRING " OpenTS(c)" ++#define CONFIG_TIMESTAMP ++#define CFG_HUSH_PARSER 1 ++#define CFG_PROMPT_HUSH_PS2 "turbostation> " ++#define CONFIG_BOOTDELAY 3 ++ ++ ++/*---------------------------------------------------------------------- ++ * Define supported commands ++ */ ++ ++#define CONFIG_COMMANDS ( \ ++ CONFIG_CMD_DFL | \ ++ CFG_CMD_ELF | \ ++ CFG_CMD_I2C | \ ++ CFG_CMD_PING | \ ++ CFG_CMD_DHCP | \ ++ CFG_CMD_IDE | \ ++ CFG_CMD_EXT2 | \ ++ CFG_CMD_DATE | \ ++ CFG_CMD_PCI ) ++ ++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ ++#include ++ ++ ++/*----------------------------------------------------------------------- ++ * Miscellaneous configurable options ++ */ ++ ++#define CFG_LONGHELP 1 /* undef to save memory */ ++#define CFG_PROMPT "=> " /* Monitor Command Prompt*/ ++#define CFG_CBSIZE 256 /* Console I/O Buffer Size*/ ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size*/ ++#define CFG_MAXARGS 16 /* max number of command args*/ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size*/ ++#define CFG_LOAD_ADDR 0x00100000 /* default load address */ ++#define CFG_HZ 1000 /* decrementer freq:1 ms ticks*/ ++ ++ ++/*----------------------------------------------------------------------- ++ * PCI ++ * ++ */ ++ ++#define CONFIG_PCI ++#undef CONFIG_PCI_PNP ++ ++#define PCI_ETH_IOADDR 0xbffe00 ++#define PCI_ETH_MEMADDR 0xbfffce00 ++ ++#define PCI_IDE_IOADDR 0xbfffd0 ++#define PCI_IDE_MEMADDR 0xbffffe00 ++ ++#define PCI_USB0_IOADDR 0 ++#define PCI_USB0_MEMADDR 0xbfffe000 ++#define PCI_USB1_IOADDR 0 ++#define PCI_USB1_MEMADDR 0xbfffd000 ++#define PCI_USB2_IOADDR 0 ++#define PCI_USB2_MEMADDR 0xbfffcf00 ++ ++ ++/*----------------------------------------------------------------------- ++ * Start addresses for the final memory configuration ++ * (Set up by the startup code) ++ */ ++ ++#define CFG_SDRAM_BASE 0x00000000 ++#define CFG_MONITOR_BASE TEXT_BASE ++#undef CFG_RAMBOOT ++ ++#define CFG_PCI_MEM_ADDR 0xB0000000 ++#define CFG_EUMB_ADDR 0xFC000000 ++#define CFG_FLASH_BASE 0xFF000000 ++ ++#define CFG_RESET_ADDRESS 0xFFF00100 ++ ++#define CFG_MONITOR_LEN (256 << 10) ++#define CFG_MALLOC_LEN (512 << 10) ++ ++#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ ++#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ ++#define CFG_MAX_RAM_SIZE 0x10000000 /* up to 256M of SDRAM */ ++ ++ ++/*----------------------------------------------------------------------- ++ * Definitions for initial stack pointer and data area ++ */ ++ ++#define CFG_INIT_RAM_ADDR 0x40000000 ++#define CFG_INIT_RAM_END 0x1000 ++#define CFG_GBL_DATA_SIZE 128 ++#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) ++ ++ ++/*----------------------------------------------------------------------- ++ * FLASH organization ++ */ ++ ++#define CFG_FLASH_CFI 1 ++#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ ++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ ++#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip*/ ++#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ ++#define CFG_FLASH_USE_BUFFER_WRITE /* faster writes */ ++ ++#define CFG_ENV_IS_IN_FLASH 1 ++#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00EA0000) ++#define CFG_ENV_SECT_SIZE 0x00020000 /* Total Size of Environment Sector*/ ++ ++ ++/*----------------------------------------------------------------------- ++ * Gigabit Ethernet ++ */ ++ ++#define CONFIG_NET_MULTI ++#define CONFIG_RTL8169 ++ ++ ++/*----------------------------------------------------------------------- ++ * Filesystems ++ */ ++ ++#define CONFIG_MAC_PARTITION ++#define CONFIG_DOS_PARTITION ++//#define CONFIG_ISO_PARTITION ++ ++ ++/*----------------------------------------------------------------------- ++ * IDE/ATA ++ */ ++ ++#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ ++#undef CONFIG_IDE_LED /* no led for ide supported */ ++#undef CONFIG_IDE_RESET /* no reset for ide supported */ ++#undef CONFIG_ATAPI /* no ATAPI support */ ++ ++#define CONFIG_IDE_PREINIT /* To set up MMIO adresses */ ++#define CONFIG_LBA48 /* Large disk support */ ++ ++#define CFG_IDE_MAXBUS 2 /* Two channels x 1 device each */ ++#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) ++ ++#define CFG_ATA_BASE_ADDR 0x0000 /* Set up in board specific code */ ++#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ ++#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ ++#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ ++ ++ ++/*---------------------------------------------------------------------- ++ * On Chip Serial configuration ++ */ ++ ++#define CONFIG_CONS_INDEX 1 ++#define CONFIG_BAUDRATE 115200 ++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } ++ ++#define CFG_NS16550 ++#define CFG_NS16550_SERIAL ++ ++#define CFG_NS16550_REG_SIZE 1 ++#define CFG_NS16550_CLK get_bus_freq(0) ++ ++#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) /* Console port */ ++#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) /* PIC ? */ ++ ++ ++/*---------------------------------------------------------------------- ++ * i2c support configuration ++ */ ++ ++#define CONFIG_HARD_I2C 1 /* To enable I2C support */ ++#undef CONFIG_SOFT_I2C /* I2C bit-banged */ ++#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ ++#define CFG_I2C_SLAVE 0x7F ++ ++#define CONFIG_RTC_RS5C372A /* Real-time clock chip */ ++ ++ ++/*---------------------------------------------------------------------- ++ * Low Level Configuration Settings ++ * (address mappings, register initial values, etc.) ++ * You should know what you are doing if you make changes here. ++ */ ++ ++#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ ++ ++#define CFG_ROMNAL 7 /*rom/flash next access time */ ++#define CFG_ROMFAL 11 /*rom/flash access time */ ++ ++#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */ ++ ++/* the following are for SDRAM only*/ ++#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ ++#define CFG_REFREC 8 /* Refresh to activate interval */ ++#define CFG_RDLAT 4 /* data latency from read command */ ++#define CFG_PRETOACT 3 /* Precharge to activate interval */ ++#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ ++#define CFG_ACTORW 3 /* Activate to R/W */ ++#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ ++#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ ++ ++#define CFG_REGISTERD_TYPE_BUFFER 1 ++#define CFG_EXTROM 1 ++#define CFG_REGDIMM 0 ++ ++ ++/*---------------------------------------------------------------------- ++ * memory bank settings ++ * ++ * only bits 20-29 are actually used from these vales to set the ++ * start/end address the upper two bits will be 0, and the lower 20 ++ * bits will be set to 0x00000 for a start address, or 0xfffff for an ++ * end address ++ */ ++ ++#define CFG_BANK0_START 0x00000000 ++#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) ++#define CFG_BANK0_ENABLE 1 ++#define CFG_BANK1_START 0x3ff00000 ++#define CFG_BANK1_END 0x3fffffff ++#define CFG_BANK1_ENABLE 0 ++#define CFG_BANK2_START 0x3ff00000 ++#define CFG_BANK2_END 0x3fffffff ++#define CFG_BANK2_ENABLE 0 ++#define CFG_BANK3_START 0x3ff00000 ++#define CFG_BANK3_END 0x3fffffff ++#define CFG_BANK3_ENABLE 0 ++#define CFG_BANK4_START 0x00000000 ++#define CFG_BANK4_END 0x00000000 ++#define CFG_BANK4_ENABLE 0 ++#define CFG_BANK5_START 0x00000000 ++#define CFG_BANK5_END 0x00000000 ++#define CFG_BANK5_ENABLE 0 ++#define CFG_BANK6_START 0x00000000 ++#define CFG_BANK6_END 0x00000000 ++#define CFG_BANK6_ENABLE 0 ++#define CFG_BANK7_START 0x00000000 ++#define CFG_BANK7_END 0x00000000 ++#define CFG_BANK7_ENABLE 0 ++ ++ ++/* ++ * Memory bank enable bitmask, specifying which of the banks defined above ++ are actually present. MSB is for bank #7, LSB is for bank #0. ++ */ ++#define CFG_BANK_ENABLE 0x01 ++ ++#define CFG_ODCR 0xff /* configures line driver impedances, */ ++ /* see 8240 book for bit definitions */ ++#define CFG_PGMAX 0x32 /* how long the 8240 retains the */ ++ /* currently accessed page in memory */ ++ /* see 8240 book for details */ ++#define CFG_DBUS_SIZE2 1 ++#define CFG_BANK0_ROW 2 ++ ++ ++/*---------------------------------------------------------------------- ++ * Initial BAT mappings ++ */ ++ ++/* SDRAM 0 - 256MB */ ++#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) ++#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) ++ ++/* stack in DCACHE @ 1GB (no backing mem) */ ++#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) ++#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) ++ ++/* PCI memory */ ++#define CFG_IBAT2L (CFG_PCI_MEM_ADDR | BATL_PP_10 | BATL_CACHEINHIBIT) ++#define CFG_IBAT2U (CFG_PCI_MEM_ADDR | BATU_BL_256M | BATU_VS | BATU_VP) ++ ++/* Flash, config addrs, etc */ ++#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) ++#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) ++ ++#define CFG_DBAT0L CFG_IBAT0L ++#define CFG_DBAT0U CFG_IBAT0U ++#define CFG_DBAT1L CFG_IBAT1L ++#define CFG_DBAT1U CFG_IBAT1U ++#define CFG_DBAT2L CFG_IBAT2L ++#define CFG_DBAT2U CFG_IBAT2U ++#define CFG_DBAT3L CFG_IBAT3L ++#define CFG_DBAT3U CFG_IBAT3U ++ ++/* ++ * For booting Linux, the board info and command line data ++ * have to be in the first 8 MB of memory, since this is ++ * the maximum mapped by the Linux kernel during initialization. ++ */ ++#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ ++ ++ ++/*----------------------------------------------------------------------- ++ * Cache Configuration ++ */ ++ ++#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ ++#endif ++ ++ ++/*----------------------------------------------------------------------- ++ * Internal Definitions ++ * ++ * Boot Flags ++ */ ++#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ ++#define BOOTFLAG_WARM 0x02 /* Software reboot */ ++ ++/* pass open firmware flat tree */ ++#define CONFIG_OF_FLAT_TREE 1 ++ ++/* maximum size of the flat tree (8K) */ ++#define OF_FLAT_TREE_MAX_SIZE 8192 ++ ++#define OF_CPU "PowerPC,603e" ++#define OF_STDOUT_PATH "/soc10x/serial@fc004500" ++ ++#endif /* __CONFIG_H */ ++ +--- u-boot-1.2.0.vanilla/Makefile 2007-01-07 00:13:11.000000000 +0100 ++++ u-boot-1.2.0/Makefile 2007-02-26 01:55:37.000000000 +0100 +@@ -1296,6 +1296,9 @@ + PN62_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc824x pn62 + ++qnap_config: unconfig ++ @$(MKCONFIG) $(@:_config=) ppc mpc824x qnap ++ + Sandpoint8240_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc824x sandpoint + diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/.mtn2git_empty b/packages/u-boot/u-boot-mkimage-openmoko-native/.mtn2git_empty new file mode 100644 index 0000000000..e69de29bb2 diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/bbt-create-optional.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/bbt-create-optional.patch new file mode 100644 index 0000000000..d7a2a872e5 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/bbt-create-optional.patch @@ -0,0 +1,52 @@ +This patch makes creation of the BBT optional for the s3c24x0 platform. +It adds: + +- a new platform-independent NAND-wide flag NAND_DONT_CREATE_BBT +- one user of this flag, namely s3c24x0 + +Experimental. + +- Werner Almesberger + + +Index: u-boot/cpu/arm920t/s3c24x0/nand.c +=================================================================== +--- u-boot.orig/cpu/arm920t/s3c24x0/nand.c 2007-02-16 23:53:29.000000000 +0100 ++++ u-boot/cpu/arm920t/s3c24x0/nand.c 2007-02-16 23:53:54.000000000 +0100 +@@ -169,7 +169,7 @@ + + nand->eccmode = NAND_ECC_SOFT; + #ifdef CONFIG_S3C2410_NAND_BBT +- nand->options = NAND_USE_FLASH_BBT; ++ nand->options = NAND_USE_FLASH_BBT | NAND_DONT_CREATE_BBT; + #else + nand->options = 0; + #endif +Index: u-boot/drivers/nand/nand_bbt.c +=================================================================== +--- u-boot.orig/drivers/nand/nand_bbt.c 2007-02-16 23:53:36.000000000 +0100 ++++ u-boot/drivers/nand/nand_bbt.c 2007-02-16 23:53:54.000000000 +0100 +@@ -678,7 +678,8 @@ + } + create: + /* Create the bad block table by scanning the device ? */ +- if (!(td->options & NAND_BBT_CREATE)) ++ if (!(td->options & NAND_BBT_CREATE) || ++ (this->options & NAND_DONT_CREATE_BBT)) + continue; + + /* Create the table in memory by scanning the chip(s) */ +Index: u-boot/include/linux/mtd/nand.h +=================================================================== +--- u-boot.orig/include/linux/mtd/nand.h 2007-02-16 23:53:08.000000000 +0100 ++++ u-boot/include/linux/mtd/nand.h 2007-02-16 23:53:54.000000000 +0100 +@@ -187,7 +187,8 @@ + * This can only work if we have the ecc bytes directly behind the + * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */ + #define NAND_HWECC_SYNDROME 0x00020000 +- ++/* Do not create an BBT if none is found. Overrides NAND_BBT_CREATE. */ ++#define NAND_DONT_CREATE_BBT 0x00040000 + + /* Options set by nand scan */ + /* Nand scan has allocated oob_buf */ diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/bbt-scan-second.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/bbt-scan-second.patch new file mode 100644 index 0000000000..37b2807908 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/bbt-scan-second.patch @@ -0,0 +1,69 @@ +Scan also the second OOB page for bad block information. + +board/neo1973/gta01/nand.c (board_nand_init): added board-specific badblock + pattern which sets NAND_BBT_SCAN2NDPAGE +drivers/nand/nand_base.c (nand_block_bad): also consider the second page in a + block if NAND_BBT_SCAN2NDPAGE is set + +- Werner Almesberger + +Index: u-boot/board/neo1973/gta01/nand.c +=================================================================== +--- u-boot.orig/board/neo1973/gta01/nand.c ++++ u-boot/board/neo1973/gta01/nand.c +@@ -113,9 +113,23 @@ + } + + ++/* Derived from drivers/nand/nand_bbt.c:smallpage_flashbased */ ++ ++static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; ++ ++static struct nand_bbt_descr badblock_pattern = { ++ .options = ++ NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES | NAND_BBT_SCAN2NDPAGE, ++ .offs = 5, ++ .len = 1, ++ .pattern = scan_ff_pattern ++}; ++ ++ + int board_nand_init(struct nand_chip *nand) + { + nand->read_otp = samsung_nand_read_otp; + nand->write_otp = samsung_nand_write_otp; ++ nand->badblock_pattern = &badblock_pattern; + return s3c24x0_nand_init(nand); + } +Index: u-boot/drivers/nand/nand_base.c +=================================================================== +--- u-boot.orig/drivers/nand/nand_base.c ++++ u-boot/drivers/nand/nand_base.c +@@ -421,7 +421,7 @@ + * + * Check, if the block is bad. + */ +-static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) ++static int nand_block_bad_page(struct mtd_info *mtd, loff_t ofs, int getchip) + { + int page, chipnr, res = 0; + struct nand_chip *this = mtd->priv; +@@ -460,6 +460,18 @@ + return res; + } + ++static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) ++{ ++ struct nand_chip *this = mtd->priv; ++ ++ if (nand_block_bad_page(mtd, ofs, getchip)) ++ return 1; ++ if (this->badblock_pattern->options & NAND_BBT_SCAN2NDPAGE && ++ nand_block_bad_page(mtd, ofs+(1 << this->page_shift), getchip)) ++ return 1; ++ return 0; ++} ++ + /** + * nand_default_block_markbad - [DEFAULT] mark a block bad + * @mtd: MTD device structure diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/boot-from-ram-and-nand.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/boot-from-ram-and-nand.patch new file mode 100644 index 0000000000..fa0de39ab7 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/boot-from-ram-and-nand.patch @@ -0,0 +1,98 @@ +Auto-detect whether we're booting from RAM or NAND, and act accordingly. This +allows us to use the same u-boot binary for all boot modes. + +include/configs/neo1973.h: introduced new config option + CONFIG_LL_INIT_NAND_ONLY to perform low-level initialization only when + booting from NAND +include/configs/neo1973.h: got rid of BUILD_FOR_RAM +cpu/arm920t/start.S: detect if we need to boot from NAND at run time (i.e., if + we're running at address 0) + +- Werner Almesberger + +Index: u-boot/cpu/arm920t/start.S +=================================================================== +--- u-boot.orig/cpu/arm920t/start.S ++++ u-boot/cpu/arm920t/start.S +@@ -157,18 +157,26 @@ + str r1, [r0] + #endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */ + +- /* +- * we do sys-critical inits only at reboot, +- * not when booting from ram! +- */ + #ifndef CONFIG_SKIP_LOWLEVEL_INIT ++#ifndef CONFIG_LL_INIT_NAND_ONLY + bl cpu_init_crit + #endif ++#endif + + #ifndef CONFIG_SKIP_RELOCATE_UBOOT +-#ifndef CONFIG_S3C2410_NAND_BOOT +-relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ ++ ++#ifdef CONFIG_S3C2410_NAND_BOOT ++ /* are we running from NAND ? */ ++#define BWSCON 0x48000000 ++ ldr r1, =BWSCON /* Z = CPU booted from NAND */ ++ ldr r1, [r1] ++ tst r1, #6 /* BWSCON[2:1] = OM[1:0] */ ++ teqeq r0, #0 /* Z &= running at address 0 */ ++ beq nand_load ++#endif /* CONFIG_S3C2410_NAND_BOOT */ ++ ++relocate: /* relocate U-Boot to RAM */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* don't reloc during debug */ + beq done_relocate +@@ -188,10 +196,13 @@ + ldr pc, _done_relocate /* jump to relocated code */ + _done_relocate: + .word done_relocate +-done_relocate: +-#else /* NAND_BOOT */ +-relocate: +-copy_myself: ++ ++#ifdef CONFIG_S3C2410_NAND_BOOT ++nand_load: ++#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && defined(CONFIG_LL_INIT_NAND_ONLY) ++ bl cpu_init_crit ++#endif ++ + /* mov r10, lr */ + + @ reset NAND +@@ -275,7 +286,8 @@ + #endif + 1: b 1b + done_nand_read: +-#endif /* NAND_BOOT */ ++#endif /* CONFIG_S3C2410_NAND_BOOT */ ++done_relocate: + #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ + + /* Set up the stack */ +Index: u-boot/include/configs/neo1973_gta01.h +=================================================================== +--- u-boot.orig/include/configs/neo1973_gta01.h ++++ u-boot/include/configs/neo1973_gta01.h +@@ -26,14 +26,10 @@ + #ifndef __CONFIG_H + #define __CONFIG_H + +-#if defined(BUILD_FOR_RAM) +-/* If we want to start u-boot from inside RAM */ +-#define CONFIG_SKIP_LOWLEVEL_INIT 1 +-#else +-/* we want to start u-boot directly from within NAND flash */ ++/* we want to be able to start u-boot directly from within NAND flash */ ++#define CONFIG_LL_INIT_NAND_ONLY + #define CONFIG_S3C2410_NAND_BOOT 1 + #define CONFIG_S3C2410_NAND_SKIP_BAD 1 +-#endif + + #define CFG_UBOOT_SIZE 0x40000 /* size of u-boot, for NAND loading */ + diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/boot-from-ram-reloc.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/boot-from-ram-reloc.patch new file mode 100644 index 0000000000..53a3e05c67 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/boot-from-ram-reloc.patch @@ -0,0 +1,62 @@ +This patch allows us to boot from anywhere in RAM. It mainly sets the stage +for later patches. The only real changes here is the better handling of already +cached code (e.g., if we were started by a previous instance of u-boot), and +that we drop CONFIG_SKIP_RELOCATE_UBOOT from neo1973.h + +cpu/arm920t/start.S: if not relocating, instead of going straight to + stack_setup, jump to done_relocate, which may perform other setup tasks +cpu/arm920t/start.S: after relocating, flush the cache and jump to the new code +include/configs/neo1973.h: remove CONFIG_SKIP_RELOCATE_UBOOT + +- Werner Almesberger + +Index: u-boot/cpu/arm920t/start.S +=================================================================== +--- u-boot.orig/cpu/arm920t/start.S ++++ u-boot/cpu/arm920t/start.S +@@ -171,7 +171,7 @@ relocate: /* relocate U-Boot to RAM + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* don't reloc during debug */ +- beq stack_setup ++ beq done_relocate + + ldr r2, _armboot_start + ldr r3, _bss_start +@@ -181,8 +181,14 @@ relocate: /* relocate U-Boot to RAM + copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ +- cmp r0, r2 /* until source end addreee [r2] */ ++ cmp r0, r2 /* until source end address [r2] */ + ble copy_loop ++ mov r0, #0 /* flush v3/v4 cache */ ++ mcr p15, 0, r0, c7, c7, 0 ++ ldr pc, _done_relocate /* jump to relocated code */ ++_done_relocate: ++ .word done_relocate ++done_relocate: + #else /* NAND_BOOT */ + relocate: + copy_myself: +@@ -270,7 +276,7 @@ notmatch: + 1: b 1b + done_nand_read: + #endif /* NAND_BOOT */ +-#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ ++#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ + + /* Set up the stack */ + stack_setup: +Index: u-boot/include/configs/neo1973_gta01.h +=================================================================== +--- u-boot.orig/include/configs/neo1973_gta01.h ++++ u-boot/include/configs/neo1973_gta01.h +@@ -28,7 +28,6 @@ + + #if defined(BUILD_FOR_RAM) + /* If we want to start u-boot from inside RAM */ +-#define CONFIG_SKIP_RELOCATE_UBOOT 1 + #define CONFIG_SKIP_LOWLEVEL_INIT 1 + #else + /* we want to start u-boot directly from within NAND flash */ diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/boot-menu.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/boot-menu.patch new file mode 100644 index 0000000000..352967ae06 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/boot-menu.patch @@ -0,0 +1,769 @@ +board/neo1973/bootmenu.c: simple configurable boot menu +board/neo1973/neo1973.c (neo1973_new_second): return 1 if a new second has + started since the last call +board/neo1973/neo1973.c (neo1973_on_key_pressed): return 1 if the $POWER key is + pressed +board/neo1973/neo1973.c (board_late_init): make use of neo1973_new_second and + neo1973_on_key_pressed +board/neo1973/neo1973.h: added function prototypes +u-boot/board/neo1973/neo1973.c (board_late_init): enter the boot menu when + "AUX" was pressed at least half the time +u-boot/board/neo1973/neo1973.c (board_late_init): minor code cleanup +u-boot/common/console.c, include/console.h: added "console_poll_hook" to be + called when waiting for console in put in "getc" and "tstc" +board/neo1973/neo1973.c (board_late_init): poll for the boot menu also on RAM + boot, reset, or unknown cause +board/neo1973/neo1973.c (board_late_init): don't look for the power key if + woken up by the charger +board/neo1973/neo1973.h, board/neo1973/neo1973.c, board/neo1973/bootmenu.c: + renamed neo1973_911_key_pressed to neo1973_aux_key_pressed + +- Werner Almesberger + +Index: u-boot/board/neo1973/common/bootmenu.c +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/common/bootmenu.c +@@ -0,0 +1,120 @@ ++/* ++ * bootmenu.c - Boot menu ++ * ++ * Copyright (C) 2006-2007 by OpenMoko, Inc. ++ * Written by Werner Almesberger ++ * All Rights Reserved ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. ++ */ ++ ++ ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_USBD_DFU ++#include "usbdcore.h" ++#include "usb_dfu.h" ++#endif ++ ++#include "neo1973.h" ++ ++ ++#define DEBOUNCE_LOOPS 1000 /* wild guess */ ++ ++ ++static int debounce(int (*fn)(void), int *last) ++{ ++ int on, i; ++ ++again: ++ on = fn(); ++ if (on != *last) ++ for (i = DEBOUNCE_LOOPS; i; i--) ++ if (on != fn()) ++ goto again; ++ *last = on; ++ return on; ++} ++ ++ ++static int aux_key(void *user) ++{ ++ static int last_aux = -1; ++ ++ return debounce(neo1973_aux_key_pressed, &last_aux); ++} ++ ++ ++static int on_key(void *user) ++{ ++ static int last_on = -1; ++ ++ return debounce(neo1973_on_key_pressed, &last_on); ++} ++ ++ ++static void factory_reset(void *user) ++{ ++ default_env(); ++ run_command("dynpart", 0); ++ run_command("bootd", 0); ++} ++ ++ ++static int seconds(void *user) ++{ ++ return neo1973_new_second(); ++} ++ ++ ++static int system_idle(void) ++{ ++#ifdef CONFIG_USBD_DFU ++ if (system_dfu_state) ++ return *system_dfu_state == DFU_STATE_appIDLE; ++#endif ++ return 1; ++} ++ ++ ++static void poweroff_if_idle(void *user) ++{ ++ unsigned long flags; ++ ++ local_irq_save(flags); ++ if (system_idle()) ++ neo1973_poweroff(); ++ local_irq_restore(flags); ++} ++ ++ ++static struct bootmenu_setup bootmenu_setup = { ++ .next_key = aux_key, ++ .enter_key = on_key, ++ .seconds = seconds, ++ .idle_action = poweroff_if_idle, ++}; ++ ++ ++void neo1973_bootmenu(void) ++{ ++ bootmenu_add("Boot", NULL, "bootd"); ++ bootmenu_init(&bootmenu_setup); ++ bootmenu_add("Factory reset", factory_reset, NULL); ++ bootmenu(); ++} +Index: u-boot/board/neo1973/gta01/gta01.c +=================================================================== +--- u-boot.orig/board/neo1973/gta01/gta01.c ++++ u-boot/board/neo1973/gta01/gta01.c +@@ -229,10 +229,15 @@ int board_late_init(void) + extern unsigned char booted_from_nand; + unsigned char tmp; + char buf[32]; ++ int menu_vote = 0; /* <= 0: no, > 0: yes */ ++ int seconds = 0; + + /* Initialize the Power Management Unit with a safe register set */ + pcf50606_init(); + ++ /* if there's no other reason, must be regular reset */ ++ neo1973_wakeup_cause = NEO1973_WAKEUP_RESET; ++ + if (!booted_from_nand) + goto woken_by_reset; + +@@ -242,45 +247,41 @@ int board_late_init(void) + setenv("pcf50606_int1", buf); + + if (tmp & PCF50606_INT1_ALARM) { +- /* we've been woken up by RTC alarm or charger insert, boot */ ++ /* we've been woken up by RTC alarm, boot */ + neo1973_wakeup_cause = NEO1973_WAKEUP_ALARM; + goto continue_boot; + } + if (tmp & PCF50606_INT1_EXTONR) { ++ /* we've been woken up by charger insert */ + neo1973_wakeup_cause = NEO1973_WAKEUP_CHARGER; + } + + if (tmp & PCF50606_INT1_ONKEYF) { +- int seconds = 0; +- neo1973_wakeup_cause = NEO1973_WAKEUP_POWER_KEY; + /* we've been woken up by a falling edge of the onkey */ ++ neo1973_wakeup_cause = NEO1973_WAKEUP_POWER_KEY; ++ } + +- /* we can't just setenv(bootdelay,-1) because that would +- * accidentially become permanent if the user does saveenv */ +- if (neo1973_911_key_pressed()) +- nobootdelay = 1; +- +- while (1) { +- u_int8_t int1, oocs; +- +- oocs = pcf50606_reg_read(PCF50606_REG_OOCS); +- if (oocs & PFC50606_OOCS_ONKEY) +- break; +- +- int1 = pcf50606_reg_read(PCF50606_REG_INT1); +- if (int1 & PCF50606_INT1_SECOND) +- seconds++; +- +- if (seconds >= POWER_KEY_SECONDS) +- goto continue_boot; +- } +- /* Power off if minimum number of seconds not reached */ +- neo1973_poweroff(); ++ if (neo1973_wakeup_cause == NEO1973_WAKEUP_CHARGER) { ++ /* if we still think it was only a charger insert, boot */ ++ goto continue_boot; + } + + woken_by_reset: +- /* if there's no other reason, must be regular reset */ +- neo1973_wakeup_cause = NEO1973_WAKEUP_RESET; ++ ++ while (neo1973_wakeup_cause == NEO1973_WAKEUP_RESET || ++ neo1973_on_key_pressed()) { ++ if (neo1973_aux_key_pressed()) ++ menu_vote++; ++ else ++ menu_vote--; ++ ++ if (neo1973_new_second()) ++ seconds++; ++ if (seconds >= POWER_KEY_SECONDS) ++ goto continue_boot; ++ } ++ /* Power off if minimum number of seconds not reached */ ++ neo1973_poweroff(); + + continue_boot: + jbt6k74_init(); +@@ -304,6 +305,11 @@ continue_boot: + } + #endif + ++ if (menu_vote > 0) { ++ neo1973_bootmenu(); ++ nobootdelay = 1; ++ } ++ + return 0; + } + +@@ -369,7 +375,17 @@ void neo1973_vibrator(int on) + #endif + } + +-int neo1973_911_key_pressed(void) ++int neo1973_new_second(void) ++{ ++ return pcf50606_reg_read(PCF50606_REG_INT1) & PCF50606_INT1_SECOND; ++} ++ ++int neo1973_on_key_pressed(void) ++{ ++ return !(pcf50606_reg_read(PCF50606_REG_OOCS) & PFC50606_OOCS_ONKEY); ++} ++ ++int neo1973_aux_key_pressed(void) + { + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + if (gpio->GPFDAT & (1 << 6)) +Index: u-boot/board/neo1973/gta01/Makefile +=================================================================== +--- u-boot.orig/board/neo1973/gta01/Makefile ++++ u-boot/board/neo1973/gta01/Makefile +@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk + + LIB = lib$(BOARD).a + +-OBJS := gta01.o pcf50606.o ../common/cmd_neo1973.o ../common/jbt6k74.o ../common/udc.o ++OBJS := gta01.o pcf50606.o ../common/cmd_neo1973.o ../common/jbt6k74.o ../common/udc.o ../common/bootmenu.o + SOBJS := ../common/lowlevel_init.o + + .PHONY: all +Index: u-boot/board/neo1973/common/neo1973.h +=================================================================== +--- u-boot.orig/board/neo1973/common/neo1973.h ++++ u-boot/board/neo1973/common/neo1973.h +@@ -29,4 +29,10 @@ int neo1973_911_key_pressed(void); + const char *neo1973_get_charge_status(void); + int neo1973_set_charge_mode(enum neo1973_charger_cmd cmd); + ++int neo1973_new_second(void); ++int neo1973_on_key_pressed(void); ++int neo1973_aux_key_pressed(void); ++ ++void neo1973_bootmenu(void); ++ + #endif +Index: u-boot/common/console.c +=================================================================== +--- u-boot.orig/common/console.c ++++ u-boot/common/console.c +@@ -160,8 +160,12 @@ void fprintf (int file, const char *fmt, + + /** U-Boot INITIAL CONSOLE-COMPATIBLE FUNCTION *****************************/ + ++void (*console_poll_hook)(int activity); ++ + int getc (void) + { ++ while (console_poll_hook && !tstc()); ++ + if (gd->flags & GD_FLG_DEVINIT) { + /* Get from the standard input */ + return fgetc (stdin); +@@ -171,7 +175,7 @@ int getc (void) + return serial_getc (); + } + +-int tstc (void) ++static int do_tstc (void) + { + if (gd->flags & GD_FLG_DEVINIT) { + /* Test the standard input */ +@@ -182,6 +186,16 @@ int tstc (void) + return serial_tstc (); + } + ++int tstc (void) ++{ ++ int ret; ++ ++ ret = do_tstc(); ++ if (console_poll_hook) ++ console_poll_hook(ret); ++ return ret; ++} ++ + void putc (const char c) + { + #ifdef CONFIG_SILENT_CONSOLE +Index: u-boot/include/console.h +=================================================================== +--- u-boot.orig/include/console.h ++++ u-boot/include/console.h +@@ -33,6 +33,8 @@ + extern device_t *stdio_devices[] ; + extern char *stdio_names[MAX_FILES] ; + ++extern void (*console_poll_hook)(int activity); ++ + int console_realloc(int top); + + #endif +Index: u-boot/common/Makefile +=================================================================== +--- u-boot.orig/common/Makefile ++++ u-boot/common/Makefile +@@ -50,7 +50,8 @@ COBJS = main.o ACEX1K.o altera.o bedbug. + memsize.o miiphybb.o miiphyutil.o \ + s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \ + usb.o usb_kbd.o usb_storage.o \ +- virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o cmd_mfsl.o ++ virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o cmd_mfsl.o \ ++ bootmenu.o + + SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) + OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS)) +Index: u-boot/common/bootmenu.c +=================================================================== +--- /dev/null ++++ u-boot/common/bootmenu.c +@@ -0,0 +1,311 @@ ++/* ++ * bootmenu.c - Boot menu ++ * ++ * Copyright (C) 2006-2007 by OpenMoko, Inc. ++ * Written by Werner Almesberger ++ * All Rights Reserved ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. ++ */ ++ ++ ++#include ++ ++#ifdef CFG_BOOTMENU ++ ++#include ++#include ++#include ++#include ++ ++ ++extern const char version_string[]; ++ ++ ++#define ANSI_CLEAR "\e[2J" ++#define ANSI_REVERSE "\e[7m" ++#define ANSI_NORMAL "\e[m" ++#define ANSI_GOTOYX "\e[%d;%dH" ++ ++/* ++ * MIN_BOOT_MENU_TIMEOUT ensures that users can't by accident set the timeout ++ * unusably short. ++ */ ++#define MIN_BOOT_MENU_TIMEOUT 10 /* 10 seconds */ ++#define BOOT_MENU_TIMEOUT 60 /* 60 seconds */ ++#define AFTER_COMMAND_WAIT 3 /* wait (2,3] after running commands */ ++#define MAX_MENU_ITEMS 10 /* cut off after that many */ ++ ++#define TOP_ROW 2 ++#define MENU_0_ROW (TOP_ROW+5) ++ ++ ++struct option { ++ const char *label; ++ void (*fn)(void *user); /* run_command if NULL */ ++ void *user; ++}; ++ ++ ++static const struct bootmenu_setup *setup; ++static struct option options[MAX_MENU_ITEMS]; ++static int num_options = 0; ++static int max_width = 0; ++ ++static device_t *bm_con; ++ ++ ++static void bm_printf(const char *fmt, ...) ++{ ++ va_list args; ++ char printbuffer[CFG_PBSIZE]; ++ ++ va_start(args, fmt); ++ vsprintf(printbuffer, fmt, args); ++ va_end(args); ++ ++ bm_con->puts(printbuffer); ++} ++ ++ ++static char *get_option(int n) ++{ ++ char name[] = "menu_XX"; ++ ++ sprintf(name+5, "%d", n); ++ return getenv(name); ++} ++ ++ ++static void print_option(const struct option *option, int reverse) ++{ ++ int n = option-options; ++ ++ bm_printf(ANSI_GOTOYX, MENU_0_ROW+n, 1); ++ if (reverse) ++ bm_printf(ANSI_REVERSE); ++ bm_printf(" %-*s ", max_width, option->label); ++ if (reverse) ++ bm_printf(ANSI_NORMAL); ++} ++ ++ ++static int get_var_positive_int(char *var, int default_value) ++{ ++ const char *s; ++ char *end; ++ int n; ++ ++ s = getenv(var); ++ if (!s) ++ return default_value; ++ n = simple_strtoul(s, &end, 0); ++ if (!*s || *end || n < 1) ++ return default_value; ++ return n; ++} ++ ++ ++static void show_bootmenu(void) ++{ ++ const struct option *option; ++ ++ bm_printf(ANSI_CLEAR ANSI_GOTOYX "%s", TOP_ROW, 1, version_string); ++ bm_printf(ANSI_GOTOYX "*** BOOT MENU ***", TOP_ROW+3, 1); ++ bm_printf(ANSI_GOTOYX, MENU_0_ROW, 1); ++ ++ for (option = options; option != options+num_options; option++) ++ print_option(option, option == options); ++ ++ bm_printf("\n\nPress [AUX] to select, [POWER] to execute.\n"); ++} ++ ++ ++static void redirect_console(int grab) ++{ ++ static device_t *orig_stdout, *orig_stderr; ++ ++ if (grab) { ++ orig_stdout = stdio_devices[stdout]; ++ orig_stderr = stdio_devices[stderr]; ++ stdio_devices[stdout] = bm_con; ++ stdio_devices[stderr] = bm_con; ++ } ++ else { ++ /* ++ * Make this conditional, because the command may also change ++ * the console. ++ */ ++ if (stdio_devices[stdout] == bm_con) ++ stdio_devices[stdout] = orig_stdout; ++ if (stdio_devices[stderr] == bm_con) ++ stdio_devices[stderr] = orig_stderr; ++ } ++} ++ ++ ++static void do_option(const struct option *option) ++{ ++ int seconds, aux; ++ ++ bm_printf(ANSI_CLEAR ANSI_GOTOYX, 1, 1); ++ redirect_console(1); ++ ++ if (option->fn) ++ option->fn(option->user); ++ else ++ run_command(option->user, 0); ++ ++ redirect_console(0); ++ seconds = get_var_positive_int("after_command_wait", ++ AFTER_COMMAND_WAIT); ++ if (seconds) ++ bm_printf("\nPress [AUX] to %s.", ++ option ? "return to boot menu" : "power off"); ++ aux = 1; /* require up-down transition */ ++ while (seconds) { ++ int tmp; ++ ++ tmp = setup->next_key(setup->user); ++ if (tmp && !aux) ++ break; ++ aux = tmp; ++ if (setup->seconds(setup->user)) ++ seconds--; ++ } ++ if (!option) ++ setup->idle_action(setup->idle_action); ++ show_bootmenu(); ++} ++ ++ ++static void bootmenu_hook(int activity) ++{ ++ static int aux = 1, on = 1; ++ static const struct option *option = options; ++ static int seconds = 0; ++ int tmp; ++ ++ if (activity) ++ seconds = 0; ++ tmp = setup->next_key(setup->user); ++ if (tmp && !aux) { ++ print_option(option, 0); ++ option++; ++ if (option == options+num_options) ++ option = options; ++ print_option(option, 1); ++ seconds = 0; ++ } ++ aux = tmp; ++ tmp = setup->enter_key(setup->user); ++ if (tmp && !on) { ++ do_option(option); ++ option = options; ++ seconds = 0; ++ } ++ on = tmp; ++ if (setup->seconds(setup->user)) { ++ int timeout; ++ ++ timeout = get_var_positive_int("boot_menu_timeout", ++ BOOT_MENU_TIMEOUT); ++ if (timeout < MIN_BOOT_MENU_TIMEOUT) ++ timeout = MIN_BOOT_MENU_TIMEOUT; ++ if (++seconds > timeout) { ++ setup->idle_action(setup->idle_action); ++ seconds = 0; ++ } ++ } ++} ++ ++ ++static device_t *find_console(const char *name) ++{ ++ int i; ++ ++ for (i = 1; i != ListNumItems(devlist); i++) { ++ device_t *dev = ListGetPtrToItem(devlist, i); ++ ++ if (!strcmp(name, dev->name)) ++ if (dev->flags & DEV_FLAGS_OUTPUT) ++ return dev; ++ } ++ return NULL; ++} ++ ++ ++void bootmenu_add(const char *label, void (*fn)(void *user), void *user) ++{ ++ int len; ++ ++ options[num_options].label = label; ++ options[num_options].fn = fn; ++ options[num_options].user = user; ++ num_options++; ++ ++ len = strlen(label); ++ if (len > max_width) ++ max_width = len; ++} ++ ++ ++void bootmenu_init(struct bootmenu_setup *__setup) ++{ ++ int n; ++ ++ setup = __setup; ++ for (n = 1; n != MAX_MENU_ITEMS+1; n++) { ++ const char *spec, *colon; ++ ++ spec = get_option(n); ++ if (!spec) ++ continue; ++ colon = strchr(spec, ':'); ++ if (!colon) ++ bootmenu_add(spec, NULL, (char *) spec); ++ else { ++ char *label; ++ int len = colon-spec; ++ ++ label = malloc(len+1); ++ if (!label) ++ return; ++ memcpy(label, spec, len); ++ label[len] = 0; ++ bootmenu_add(label, NULL, (char *) colon+1); ++ } ++ } ++} ++ ++ ++void bootmenu(void) ++{ ++ bm_con = find_console("vga"); ++ if (bm_con && bm_con->start && bm_con->start() < 0) ++ bm_con = NULL; ++ if (!bm_con) ++ bm_con = stdio_devices[stdout]; ++ if (!bm_con) ++ return; ++#if 0 ++ console_assign(stdout, "vga"); ++ console_assign(stderr, "vga"); ++#endif ++ show_bootmenu(); ++ console_poll_hook = bootmenu_hook; ++} ++ ++#endif /* CFG_BOOTMENU */ +Index: u-boot/include/bootmenu.h +=================================================================== +--- /dev/null ++++ u-boot/include/bootmenu.h +@@ -0,0 +1,71 @@ ++/* ++ * bootmenu.h - Boot menu ++ * ++ * Copyright (C) 2006-2007 by OpenMoko, Inc. ++ * Written by Werner Almesberger ++ * All Rights Reserved ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. ++ */ ++ ++#ifndef BOOTMENU_H ++#define BOOTMENU_H ++ ++#define MIN_BOOT_MENU_TIMEOUT 10 /* 10 seconds */ ++#define BOOT_MENU_TIMEOUT 60 /* 60 seconds */ ++#define AFTER_COMMAND_WAIT 3 /* wait (2,3] after running commands */ ++#define MAX_MENU_ITEMS 10 /* cut off after that many */ ++ ++ ++struct bootmenu_setup { ++ /* non-zero while the "next" key is being pressed */ ++ int (*next_key)(void *user); ++ ++ /* non-zero while the "enter" key is being pressed */ ++ int (*enter_key)(void *user); ++ ++ /* return the number of seconds that have passed since the last call ++ to "seconds". It's okay to limit the range to [0, 1]. */ ++ int (*seconds)(void *user); ++ ++ /* action to take if the boot menu times out */ ++ void (*idle_action)(void *user); ++ ++ /* user-specific data, passes "as is" to the functions above */ ++ void *user; ++}; ++ ++ ++/* ++ * Initialize the menu from the environment. ++ */ ++ ++void bootmenu_init(struct bootmenu_setup *setup); ++ ++/* ++ * To add entries on top of the boot menu, call bootmenu_add before ++ * bootmenu_init. To add entries at the end, call it after bootmenu_init. ++ * If "fn" is NULL, the command specified in "user" is executed. ++ */ ++ ++void bootmenu_add(const char *label, void (*fn)(void *user), void *user); ++ ++/* ++ * Run the boot menu. ++ */ ++ ++void bootmenu(void); ++ ++#endif /* !BOOTMENU_H */ +Index: u-boot/include/configs/neo1973_gta01.h +=================================================================== +--- u-boot.orig/include/configs/neo1973_gta01.h ++++ u-boot/include/configs/neo1973_gta01.h +@@ -160,6 +160,8 @@ + /* valid baudrates */ + #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + ++#define CFG_BOOTMENU ++ + /*----------------------------------------------------------------------- + * Stack sizes + * diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/cmd-unzip.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/cmd-unzip.patch new file mode 100644 index 0000000000..ee4c1984fc --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/cmd-unzip.patch @@ -0,0 +1,58 @@ +common/cmd_mem.c: new command "unzip srcaddr dstaddr [dstsize]" to unzip from + memory to memory, and option CONFIG_UNZIP to enable it + +- Werner Almesberger + +Index: u-boot/common/cmd_mem.c +=================================================================== +--- u-boot.orig/common/cmd_mem.c ++++ u-boot/common/cmd_mem.c +@@ -1148,6 +1148,34 @@ int do_mem_crc (cmd_tbl_t *cmdtp, int fl + } + #endif /* CONFIG_CRC32_VERIFY */ + ++ ++#ifdef CONFIG_UNZIP ++int gunzip (void *, int, unsigned char *, unsigned long *); ++ ++int do_unzip ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ++{ ++ unsigned long src, dst; ++ unsigned long src_len = ~0UL, dst_len = ~0UL; ++ int err; ++ ++ switch (argc) { ++ case 4: ++ dst_len = simple_strtoul(argv[3], NULL, 16); ++ /* fall through */ ++ case 3: ++ src = simple_strtoul(argv[1], NULL, 16); ++ dst = simple_strtoul(argv[2], NULL, 16); ++ break; ++ default: ++ printf ("Usage:\n%s\n", cmdtp->usage); ++ return 1; ++ } ++ ++ return !!gunzip((void *) dst, dst_len, (void *) src, &src_len); ++} ++#endif /* CONFIG_UNZIP */ ++ ++ + /**************************************************/ + #if (CONFIG_COMMANDS & CFG_CMD_MEMORY) + U_BOOT_CMD( +@@ -1251,5 +1279,13 @@ U_BOOT_CMD( + ); + #endif /* CONFIG_MX_CYCLIC */ + ++#ifdef CONFIG_UNZIP ++U_BOOT_CMD( ++ unzip, 4, 1, do_unzip, ++ "unzip - unzip a memory region\n", ++ "srcaddr dstaddr [dstsize]\n" ++); ++#endif /* CONFIG_UNZIP */ ++ + #endif + #endif /* CFG_CMD_MEMORY */ diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/console-ansi.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/console-ansi.patch new file mode 100644 index 0000000000..2ac5b75dee --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/console-ansi.patch @@ -0,0 +1,127 @@ +drivers/cfb_console.c: added processing of ANSI escape sequences \e[2J, \e[m, + \e[7m, and \e[row;colH +drivers/cfb_console.c (video_putc): make \r return to the beginning of the line + +- Werner Almesberger + +Index: u-boot/drivers/cfb_console.c +=================================================================== +--- u-boot.orig/drivers/cfb_console.c ++++ u-boot/drivers/cfb_console.c +@@ -181,6 +181,7 @@ CONFIG_VIDEO_HW_CURSOR: - Uses the + + #include + #include ++#include + #include + #include + #ifdef CFG_CMD_DATE +@@ -676,10 +677,96 @@ static void console_newline (void) + + /*****************************************************************************/ + ++static enum { ++ CS_NORMAL = 0, ++ CS_ESC, ++ CS_NUM1, ++ CS_NUM2, ++} state = 0; ++ ++static int num1, num2; ++ ++ ++static void swap_drawing_colors(void) ++{ ++ eorx = fgx; ++ fgx = bgx; ++ bgx = eorx; ++ eorx = fgx ^ bgx; ++} ++ ++ ++static void process_sequence(char c) ++{ ++ static int inverted = 0; ++ int i, inv; ++ ++ switch (c) { ++ case 'J': ++ /* assume num1 == 2 */ ++ for (i = 0; i != CONSOLE_ROWS; i++) ++ console_scrollup(); ++ break; ++ case 'H': ++ if (num1 > CONSOLE_ROWS || num2 > CONSOLE_COLS) ++ break; ++ console_col = num2 ? num2-1 : 0; ++ console_row = num1 ? num1-1 : 0; ++ break; ++ case 'm': ++ inv = num1 == 7; ++ if (num1 && !inv) ++ break; ++ if (inverted != inv) ++ swap_drawing_colors(); ++ inverted = inv; ++ break; ++ } ++} ++ ++ ++static void escape_sequence(char c) ++{ ++ switch (state) { ++ case CS_ESC: ++ state = c == '[' ? CS_NUM1 : CS_NORMAL; ++ num1 = num2 = 0; ++ break; ++ case CS_NUM1: ++ if (isdigit(c)) ++ num1 = num1*10+c-'0'; ++ else if (c == ';') ++ state = CS_NUM2; ++ else { ++ process_sequence(c); ++ state = CS_NORMAL; ++ } ++ break; ++ case CS_NUM2: ++ if (isdigit(c)) ++ num2 = num2*10+c-'0'; ++ else { ++ process_sequence(c); ++ state = CS_NORMAL; ++ } ++ default: ++ /* can't happen */; ++ } ++} ++ ++ + void video_putc (const char c) + { ++ if (state) { ++ escape_sequence(c); ++ CURSOR_SET; ++ return; ++ } ++ + switch (c) { +- case 13: /* ignore */ ++ case 13: /* return to beginning of line */ ++ CURSOR_OFF; ++ console_col = 0; + break; + + case '\n': /* next line */ +@@ -698,6 +785,10 @@ void video_putc (const char c) + console_back (); + break; + ++ case '\e': ++ state = CS_ESC; ++ break; ++ + default: /* draw the char */ + video_putchar (console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT, diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/default-env.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/default-env.patch new file mode 100644 index 0000000000..b9ae4f29fe --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/default-env.patch @@ -0,0 +1,101 @@ +common/env_common.c (default_env): new function that resets the environment to + the default value +common/env_common.c (env_relocate): use default_env instead of own copy +common/env_nand.c (env_relocate_spec): use default_env instead of own copy +include/environment.h: added default_env prototype + +- Werner Almesberger + +Index: u-boot/common/env_common.c +=================================================================== +--- u-boot.orig/common/env_common.c ++++ u-boot/common/env_common.c +@@ -202,6 +202,25 @@ uchar *env_get_addr (int index) + } + } + ++void default_env(void) ++{ ++ if (sizeof(default_environment) > ENV_SIZE) ++ { ++ puts ("*** Error - default environment is too large\n\n"); ++ return; ++ } ++ ++ memset (env_ptr, 0, sizeof(env_t)); ++ memcpy (env_ptr->data, ++ default_environment, ++ sizeof(default_environment)); ++#ifdef CFG_REDUNDAND_ENVIRONMENT ++ env_ptr->flags = 0xFF; ++#endif ++ env_crc_update (); ++ gd->env_valid = 1; ++} ++ + void env_relocate (void) + { + DEBUGF ("%s[%d] offset = 0x%lx\n", __FUNCTION__,__LINE__, +@@ -245,23 +264,8 @@ void env_relocate (void) + gd->env_valid = 0; + #endif + +- if (gd->env_valid == 0) { +- if (sizeof(default_environment) > ENV_SIZE) +- { +- puts ("*** Error - default environment is too large\n\n"); +- return; +- } +- +- memset (env_ptr, 0, sizeof(env_t)); +- memcpy (env_ptr->data, +- default_environment, +- sizeof(default_environment)); +-#ifdef CFG_REDUNDAND_ENVIRONMENT +- env_ptr->flags = 0xFF; +-#endif +- env_crc_update (); +- gd->env_valid = 1; +- } ++ if (gd->env_valid == 0) ++ default_env(); + else { + env_relocate_spec (); + } +Index: u-boot/common/env_nand.c +=================================================================== +--- u-boot.orig/common/env_nand.c ++++ u-boot/common/env_nand.c +@@ -313,19 +313,7 @@ void env_relocate_spec (void) + static void use_default() + { + puts ("*** Warning - bad CRC or NAND, using default environment\n\n"); +- +- if (default_environment_size > CFG_ENV_SIZE){ +- puts ("*** Error - default environment is too large\n\n"); +- return; +- } +- +- memset (env_ptr, 0, sizeof(env_t)); +- memcpy (env_ptr->data, +- default_environment, +- default_environment_size); +- env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE); +- gd->env_valid = 1; +- ++ default_env(); + } + #endif + +Index: u-boot/include/environment.h +=================================================================== +--- u-boot.orig/include/environment.h ++++ u-boot/include/environment.h +@@ -107,4 +107,7 @@ typedef struct environment_s { + unsigned char data[ENV_SIZE]; /* Environment data */ + } env_t; + ++ ++void default_env(void); ++ + #endif /* _ENVIRONMENT_H_ */ diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/dontask.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/dontask.patch new file mode 100644 index 0000000000..23d4b13626 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/dontask.patch @@ -0,0 +1,22 @@ +common/cmd_nand.c (yes): if the environment variable "dontask" is set to "y" or + "Y", non-interactively assume the answer was "yes". In all other cases, ask. + +- Werner Almesberger + +Index: u-boot/common/cmd_nand.c +=================================================================== +--- u-boot.orig/common/cmd_nand.c ++++ u-boot/common/cmd_nand.c +@@ -165,8 +165,12 @@ out: + + static int yes(void) + { ++ char *s; + char c; + ++ s = getenv("dontask"); ++ if (s && (s[0] =='y' || s[0] == 'Y') && !s[1]) ++ return 1; + c = getc(); + if (c != 'y' && c != 'Y') + return 0; diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/dynenv-harden.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/dynenv-harden.patch new file mode 100644 index 0000000000..cf12352553 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/dynenv-harden.patch @@ -0,0 +1,139 @@ +common/cmd_nand.c: globalized arg_off_size +include/util.h: new header to convenience functions, such as arg_off_size +common/cmd_dynenv.c (do_dynenv): use arg_off_size to sanity-check offset and to + allow use of partition name +common/cmd_dynenv.c (do_dynenv): indicate in no uncertain terms when an update + would not work due to Flash bits already cleared +common/cmd_dynenv.c (do_dynenv): update CFG_ENV_OFFSET after successful "dynenv + set", so that we can write the new environment without having to reboot + +- Werner Almesberger + +Index: u-boot/common/cmd_nand.c +=================================================================== +--- u-boot.orig/common/cmd_nand.c ++++ u-boot/common/cmd_nand.c +@@ -100,7 +100,7 @@ static inline int str2long(char *p, ulon + return (*p != '\0' && *endptr == '\0') ? 1 : 0; + } + +-static int ++int + arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, ulong *size) + { + int idx = nand_curr_device; +Index: u-boot/include/util.h +=================================================================== +--- /dev/null ++++ u-boot/include/util.h +@@ -0,0 +1,33 @@ ++/* ++ * util.h - Convenience functions ++ * ++ * (C) Copyright 2006-2007 OpenMoko, Inc. ++ * Author: Werner Almesberger ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef UTIL_H ++#define UTIL_H ++ ++#include "nand.h" ++ ++ ++/* common/cmd_nand.c */ ++int arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, ++ ulong *size); ++ ++#endif /* UTIL_H */ +Index: u-boot/common/cmd_dynenv.c +=================================================================== +--- u-boot.orig/common/cmd_dynenv.c ++++ u-boot/common/cmd_dynenv.c +@@ -23,6 +23,7 @@ + #include + #include + #include ++#include + #include + + #if defined(CFG_ENV_OFFSET_OOB) +@@ -39,8 +40,8 @@ int do_dynenv(cmd_tbl_t *cmdtp, int flag + if (!buf) + return -ENOMEM; + ++ ret = mtd->read_oob(mtd, 8, size, (size_t *) &size, (u_char *) buf); + if (!strcmp(cmd, "get")) { +- ret = mtd->read_oob(mtd, 8, size, (size_t *) &size, (u_char *) buf); + + if (buf[0] == 'E' && buf[1] == 'N' && + buf[2] == 'V' && buf[3] == '0') +@@ -49,7 +50,8 @@ int do_dynenv(cmd_tbl_t *cmdtp, int flag + printf("No dynamic environment marker in OOB block 0\n"); + + } else if (!strcmp(cmd, "set")) { +- unsigned long addr; ++ unsigned long addr, dummy; ++ + if (argc < 3) + goto usage; + +@@ -57,7 +59,23 @@ int do_dynenv(cmd_tbl_t *cmdtp, int flag + buf[1] = 'N'; + buf[2] = 'V'; + buf[3] = '0'; +- addr = simple_strtoul(argv[2], NULL, 16); ++ ++ if (arg_off_size(argc-2, argv+2, mtd, &addr, &dummy) < 0) { ++ printf("Offset or partition name expected\n"); ++ goto fail; ++ } ++ if (!ret) { ++ uint8_t tmp[4]; ++ int i; ++ ++ memcpy(&tmp, &addr, 4); ++ for (i = 0; i != 4; i++) ++ if (tmp[i] & ~buf[i+4]) { ++ printf("ERROR: erase OOB block to " ++ "write this value\n"); ++ goto fail; ++ } ++ } + memcpy(buf+4, &addr, 4); + + printf("%02x %02x %02x %02x - %02x %02x %02x %02x\n", +@@ -65,6 +83,8 @@ int do_dynenv(cmd_tbl_t *cmdtp, int flag + buf[4], buf[5], buf[6], buf[7]); + + ret = mtd->write_oob(mtd, 8, size, (size_t *) &size, (u_char *) buf); ++ if (!ret) ++ CFG_ENV_OFFSET = addr; + } else + goto usage; + +@@ -72,8 +92,9 @@ int do_dynenv(cmd_tbl_t *cmdtp, int flag + return ret; + + usage: +- free(buf); + printf("Usage:\n%s\n", cmdtp->usage); ++fail: ++ free(buf); + return 1; + } + diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/early-powerdown.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/early-powerdown.patch new file mode 100644 index 0000000000..7326c2daa6 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/early-powerdown.patch @@ -0,0 +1,40 @@ +Index: u-boot/board/neo1973/neo1973.c +=================================================================== +--- u-boot.orig/board/neo1973/gta01/gta01.c ++++ u-boot/board/neo1973/gta01/gta01.c +@@ -68,8 +68,12 @@ DECLARE_GLOBAL_DATA_PTR; + #define U_M_PDIV 0x2 + #define U_M_SDIV 0x3 + ++#define VALID_WAKEUP_REASONS (PCF50606_INT1_ONKEYF | PCF50606_INT1_ALARM) ++ + unsigned int neo1973_wakeup_cause; + extern int nobootdelay; ++static unsigned char int1; ++ + + static inline void delay (unsigned long loops) + { +@@ -179,6 +183,13 @@ int board_init (void) + #error Please define GTA01 version + #endif + ++ i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); ++ int1 = pcf50606_reg_read(PCF50606_REG_INT1); ++ if (!(int1 & VALID_WAKEUP_REASONS) && !neo1973_aux_key_pressed()) { ++ pcf50606_reg_write(PCF50606_REG_OOCC1, PCF50606_OOCC1_GOSTDBY); ++ while (1); ++ } ++ + /* arch number of SMDK2410-Board */ + gd->bd->bi_arch_number = MACH_TYPE_NEO1973_GTA01; + +@@ -200,7 +211,7 @@ int board_late_init(void) + pcf50606_init(); + + /* obtain wake-up reason, save INT1 in environment */ +- tmp = pcf50606_reg_read(PCF50606_REG_INT1); ++ tmp = int1; //pcf50606_reg_read(PCF50606_REG_INT1); + sprintf(buf, "0x%02x", tmp); + setenv("pcf50606_int1", buf); + diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/enable-splash-bmp.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/enable-splash-bmp.patch new file mode 100644 index 0000000000..dcb721c8d3 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/enable-splash-bmp.patch @@ -0,0 +1,56 @@ +drivers/cfb_console.c: include asm/byteorder.h for le32_to_cpu and friends + [ shouldn't someone else have found this long ago ? ] +include/configs/neo1973.h (CONFIG_COMMANDS): add CFG_CMD_BMP +include/configs/neo1973.h: enable splash screen and BMP support +include/configs/neo1973.h: remove #if 1 ... #endif around video definitions + +- Werner Almesberger + +Index: u-boot/drivers/cfb_console.c +=================================================================== +--- u-boot.orig/drivers/cfb_console.c ++++ u-boot/drivers/cfb_console.c +@@ -191,6 +191,7 @@ CONFIG_VIDEO_HW_CURSOR: - Uses the + #if (CONFIG_COMMANDS & CFG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) + #include + #include ++#include + #endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) || CONFIG_SPLASH_SCREEN */ + + /*****************************************************************************/ +Index: u-boot/include/configs/neo1973_gta01.h +=================================================================== +--- u-boot.orig/include/configs/neo1973_gta01.h ++++ u-boot/include/configs/neo1973_gta01.h +@@ -86,6 +86,7 @@ + /* CFG_CMD_IRQ | */ \ + CFG_CMD_BOOTD | \ + CFG_CMD_CONSOLE | \ ++ CFG_CMD_BMP | \ + CFG_CMD_ASKENV | \ + CFG_CMD_RUN | \ + CFG_CMD_ECHO | \ +@@ -244,19 +245,21 @@ + /* we have a board_late_init() function */ + #define BOARD_LATE_INIT 1 + +-#if 1 + #define CONFIG_VIDEO + #define CONFIG_VIDEO_S3C2410 + #define CONFIG_CFB_CONSOLE + #define CONFIG_VIDEO_LOGO ++#define CONFIG_SPLASH_SCREEN ++#define CFG_VIDEO_LOGO_MAX_SIZE (640*480+1024+100) /* 100 = slack */ ++#define CONFIG_VIDEO_BMP_GZIP + #define CONFIG_VGA_AS_SINGLE_DEVICE ++#define CONFIG_UNZIP + + #define VIDEO_KBD_INIT_FCT 0 + #define VIDEO_TSTC_FCT serial_tstc + #define VIDEO_GETC_FCT serial_getc + + #define LCD_VIDEO_ADDR 0x33d00000 +-#endif + + #define CONFIG_S3C2410_NAND_BBT 1 + diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/env_nand_oob.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/env_nand_oob.patch new file mode 100644 index 0000000000..5a2dd61461 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/env_nand_oob.patch @@ -0,0 +1,198 @@ +This patch adds support for CFG_ENV_OFFSET_PATCHED and +CFG_ENV_OFFSET_OOB. + +Both try to solve the problem of fixing the environment location in NAND flash +at compile time, which doesn't work well if the NAND flash has a bad block at +exactly that location. + +CFG_ENV_OFFSET_PATCHED puts the environment in a global variable. You can then +use the linker script to put that variable to a fixed location in the u-boot +image. Then you can use bianry patching during the production flash process. + +The idea of CFG_ENV_OFFSET_OOB is to store the environment offset in the NAND +OOB data of block 0. We can do this in case the vendor makes a guarantee that +block 0 never is a factory-default bad block. + +Signed-off-by: Harald Welte + +Index: u-boot/common/env_nand.c +=================================================================== +--- u-boot.orig/common/env_nand.c ++++ u-boot/common/env_nand.c +@@ -271,6 +271,33 @@ + ulong total; + int ret; + ++#if defined(CFG_ENV_OFFSET_OOB) ++ struct mtd_info *mtd = &nand_info[0]; ++ struct nand_chip *this = mtd->priv; ++ int buf_len; ++ uint8_t *buf; ++ ++ buf_len = (1 << this->bbt_erase_shift); ++ buf_len += (buf_len >> this->page_shift) * mtd->oobsize; ++ buf = malloc(buf_len); ++ if (!buf) ++ return; ++ ++ nand_read_raw(mtd, buf, 0, mtd->oobblock, mtd->oobsize); ++ if (buf[mtd->oobblock + 8 + 0] == 'E' && ++ buf[mtd->oobblock + 8 + 1] == 'N' && ++ buf[mtd->oobblock + 8 + 2] == 'V' && ++ buf[mtd->oobblock + 8 + 3] == '0') { ++ CFG_ENV_OFFSET = *((unsigned long *) &buf[mtd->oobblock + 8 + 4]); ++ /* fall through to the normal environment reading code below */ ++ free(buf); ++ puts("Found Environment offset in OOB..\n"); ++ } else { ++ free(buf); ++ return use_default(); ++ } ++#endif ++ + total = CFG_ENV_SIZE; + ret = nand_read(&nand_info[0], CFG_ENV_OFFSET, &total, (u_char*)env_ptr); + if (ret || total != CFG_ENV_SIZE) +Index: u-boot/common/environment.c +=================================================================== +--- u-boot.orig/common/environment.c ++++ u-boot/common/environment.c +@@ -29,6 +29,12 @@ + #undef __ASSEMBLY__ + #include + ++#if defined(CFG_ENV_OFFSET_PATCHED) ++unsigned long env_offset = CFG_ENV_OFFSET_PATCHED; ++#elif defined(CFG_ENV_OFFSET_OOB) ++unsigned long env_offset = CFG_ENV_OFFSET_OOB; ++#endif ++ + /* + * Handle HOSTS that have prepended + * crap on symbol names, not TARGETS. +Index: u-boot/include/environment.h +=================================================================== +--- u-boot.orig/include/environment.h ++++ u-boot/include/environment.h +@@ -70,6 +70,10 @@ + #endif /* CFG_ENV_IS_IN_FLASH */ + + #if defined(CFG_ENV_IS_IN_NAND) ++#if defined(CFG_ENV_OFFSET_PATCHED) || defined(CFG_ENV_OFFSET_OOB) ++extern unsigned long env_offset; ++#define CFG_ENV_OFFSET env_offset ++#else + # ifndef CFG_ENV_OFFSET + # error "Need to define CFG_ENV_OFFSET when using CFG_ENV_IS_IN_NAND" + # endif +@@ -82,6 +86,7 @@ + # ifdef CFG_ENV_IS_EMBEDDED + # define ENV_IS_EMBEDDED 1 + # endif ++#endif /* CFG_ENV_NAND_PATCHED */ + #endif /* CFG_ENV_IS_IN_NAND */ + + +Index: u-boot/common/Makefile +=================================================================== +--- u-boot.orig/common/Makefile ++++ u-boot/common/Makefile +@@ -31,7 +31,7 @@ + cmd_bdinfo.o cmd_bedbug.o cmd_bmp.o cmd_boot.o cmd_bootm.o \ + cmd_cache.o cmd_console.o \ + cmd_date.o cmd_dcr.o cmd_diag.o cmd_display.o cmd_doc.o cmd_dtt.o \ +- cmd_eeprom.o cmd_elf.o cmd_ext2.o \ ++ cmd_dynenv.o cmd_eeprom.o cmd_elf.o cmd_ext2.o \ + cmd_fat.o cmd_fdc.o cmd_fdt.o cmd_fdos.o cmd_flash.o cmd_fpga.o \ + cmd_i2c.o cmd_ide.o cmd_immap.o cmd_itest.o cmd_jffs2.o \ + cmd_load.o cmd_log.o \ +Index: u-boot/common/cmd_dynenv.c +=================================================================== +--- /dev/null ++++ u-boot/common/cmd_dynenv.c +@@ -0,0 +1,85 @@ ++/* ++ * (C) Copyright 2006-2007 OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined(CFG_ENV_OFFSET_OOB) ++ ++int do_dynenv(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ++{ ++ struct mtd_info *mtd = &nand_info[0]; ++ int ret, size = 8; ++ uint8_t *buf; ++ ++ char *cmd = argv[1]; ++ ++ buf = malloc(mtd->oobsize); ++ if (!buf) ++ return -ENOMEM; ++ ++ if (!strcmp(cmd, "get")) { ++ ret = mtd->read_oob(mtd, 8, size, (size_t *) &size, (u_char *) buf); ++ ++ if (buf[0] == 'E' && buf[1] == 'N' && ++ buf[2] == 'V' && buf[3] == '0') ++ printf("0x%08x\n", *((u_int32_t *) &buf[4])); ++ else ++ printf("No dynamic environment marker in OOB block 0\n"); ++ ++ } else if (!strcmp(cmd, "set")) { ++ unsigned long addr; ++ if (argc < 3) ++ goto usage; ++ ++ buf[0] = 'E'; ++ buf[1] = 'N'; ++ buf[2] = 'V'; ++ buf[3] = '0'; ++ addr = simple_strtoul(argv[2], NULL, 16); ++ memcpy(buf+4, &addr, 4); ++ ++ printf("%02x %02x %02x %02x - %02x %02x %02x %02x\n", ++ buf[0], buf[1], buf[2], buf[3], ++ buf[4], buf[5], buf[6], buf[7]); ++ ++ ret = mtd->write_oob(mtd, 8, size, (size_t *) &size, (u_char *) buf); ++ } else ++ goto usage; ++ ++ free(buf); ++ return ret; ++ ++usage: ++ free(buf); ++ printf("Usage:\n%s\n", cmdtp->usage); ++ return 1; ++} ++ ++U_BOOT_CMD(dynenv, 3, 1, do_dynenv, ++ "dynenv - dynamically placed (NAND) environment\n", ++ "dynenv set off - set enviromnent offset\n" ++ "dynenv get - get environment offset\n"); ++ ++#endif /* CFG_ENV_OFFSET_OOB */ diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/ext2load_hex.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/ext2load_hex.patch new file mode 100644 index 0000000000..ff8e9cd6fc --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/ext2load_hex.patch @@ -0,0 +1,17 @@ +This patch adds the hex-printing of the file size read by 'ext2load' + +Signed-off-by: Harald Welte + +Index: u-boot.git/common/cmd_ext2.c +=================================================================== +--- u-boot.git.orig/common/cmd_ext2.c 2007-01-02 18:26:17.000000000 +0100 ++++ u-boot.git/common/cmd_ext2.c 2007-01-02 18:26:27.000000000 +0100 +@@ -279,7 +279,7 @@ + /* Loading ok, update default load address */ + load_addr = addr; + +- printf ("\n%ld bytes read\n", filelen); ++ printf ("\n%ld (0x%lx) bytes read\n", filelen, filelen); + sprintf(buf, "%lX", filelen); + setenv("filesize", buf); + diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/lowlevel_foo.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/lowlevel_foo.patch new file mode 100644 index 0000000000..715c46ed81 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/lowlevel_foo.patch @@ -0,0 +1,229 @@ +board/neo1973/lowlevel_foo.S: http://people.openmoko.org/laforge/tmp/bbt-20070206/lowlevel_foo.S +board/neo1973/lowlevel_foo.lds: http://people.openmoko.org/laforge/tmp/bbt-20070206/lowlevel_foo.lds +board/neo1973/Makefile: added building of lowlevel_foo.bin (based on + http://people.openmoko.org/laforge/tmp/bbt-20070206/lowlevel_foo.build.sh) + +Index: u-boot/board/neo1973/common/lowlevel_foo.S +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/common/lowlevel_foo.S +@@ -0,0 +1,82 @@ ++ ++_start: ++ b reset ++undefvec: ++ b undefvec ++swivec: ++ b swivec ++pabtvec: ++ b pabtvec ++dabtvec: ++ b dabtvec ++rsvdvec: ++ b rsvdvec ++irqvec: ++ b irqvec ++fiqvec: ++ b fiqvec ++ ++reset: ++ /* ++ * set the cpu to SVC32 mode ++ */ ++ mrs r0,cpsr ++ bic r0,r0,#0x1f ++ orr r0,r0,#0xd3 ++ msr cpsr,r0 ++ ++/* turn off the watchdog */ ++#define pWTCON 0x53000000 ++#define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ ++#define INTSUBMSK 0x4A00001C ++#define CLKDIVN 0x4C000014 /* clock divisor register */ ++ ++ ldr r0, =pWTCON ++ mov r1, #0x0 ++ str r1, [r0] ++ ++ mov r1, #0xffffffff ++ ldr r0, =INTMSK ++ str r1, [r0] ++ ldr r1, =0x3ff ++ ldr r0, =INTSUBMSK ++ str r1, [r0] ++ ++ /* FCLK:HCLK:PCLK = 1:2:4 */ ++ /* default FCLK is 120 MHz ! */ ++ ldr r0, =CLKDIVN ++ mov r1, #3 ++ str r1, [r0] ++ ++ bl cpu_init_crit ++ ldr r0,=TEXT_BASE ++ mov pc, r0 ++ ++cpu_init_crit: ++ /* ++ * flush v4 I/D caches ++ */ ++ mov r0, #0 ++ mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ ++ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ ++ ++ /* ++ * disable MMU stuff and caches ++ */ ++ mrc p15, 0, r0, c1, c0, 0 ++ bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) ++ bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) ++ orr r0, r0, #0x00000002 @ set bit 2 (A) Align ++ orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache ++ mcr p15, 0, r0, c1, c0, 0 ++ ++ /* ++ * before relocating, we have to setup RAM timing ++ * because memory timing is board-dependend, you will ++ * find a lowlevel_init.S in your board directory. ++ */ ++ mov ip, lr ++ bl lowlevel_init ++ mov lr, ip ++ mov pc, lr ++ +Index: u-boot/board/neo1973/common/lowlevel_foo.lds +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/common/lowlevel_foo.lds +@@ -0,0 +1,56 @@ ++/* ++ * (C) Copyright 2002 ++ * Gary Jennejohn, DENX Software Engineering, ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++OUTPUT_ARCH(arm) ++ENTRY(_start) ++SECTIONS ++{ ++ . = 0x00000000; ++ ++ . = ALIGN(4); ++ .text : ++ { ++ lowlevel_foo.o (.text) ++ *(.text) ++ } ++ ++ . = ALIGN(4); ++ .rodata : { *(.rodata) } ++ ++ . = ALIGN(4); ++ .data : { *(.data) } ++ ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ . = .; ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss : { *(.bss) } ++ _end = .; ++} +Index: u-boot/board/neo1973/gta01/Makefile +=================================================================== +--- u-boot.orig/board/neo1973/gta01/Makefile ++++ u-boot/board/neo1973/gta01/Makefile +@@ -28,14 +28,31 @@ + OBJS := gta01.o pcf50606.o ../common/cmd_neo1973.o ../common/jbt6k74.o ../common/udc.o + SOBJS := ../common/lowlevel_init.o + ++.PHONY: all ++ ++all: $(LIB) lowevel_foo.bin ++ + $(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + ++lowlevel_foo.o: ../common/lowlevel_foo.S ++ $(CC) -c -DTEXT_BASE=0x33F80000 -march=armv4 \ ++ -o lowlevel_foo.o ../common/lowlevel_foo.S ++ ++lowlevel_foo: lowlevel_foo.o ../common/lowlevel_init.o ../common/lowlevel_foo.lds ++ $(LD) -T ../common/lowlevel_foo.lds -Ttext 0x33f80000 -Bstatic \ ++ ../common/lowlevel_init.o lowlevel_foo.o -o lowlevel_foo ++ ++lowevel_foo.bin: lowlevel_foo ++ $(CROSS_COMPILE)objcopy --gap-fill=0xff -O binary \ ++ lowlevel_foo lowlevel_foo.bin ++ ++ + clean: +- rm -f $(SOBJS) $(OBJS) ++ rm -f $(SOBJS) $(OBJS) lowlevel_foo lowlevel_foo.o + + distclean: clean +- rm -f $(LIB) core *.bak .depend ++ rm -f $(LIB) core *.bak .depend lowlevel_foo.bin + + ######################################################################### + +Index: u-boot/board/qt2410/Makefile +=================================================================== +--- u-boot.orig/board/qt2410/Makefile ++++ u-boot/board/qt2410/Makefile +@@ -28,14 +28,31 @@ + OBJS := qt2410.o flash.o + SOBJS := lowlevel_init.o + ++.PHONY: all ++ ++all: $(LIB) lowevel_foo.bin ++ + $(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + ++lowlevel_foo.o: ../neo1973/common/lowlevel_foo.S ++ $(CC) -c -DTEXT_BASE=0x33F80000 -march=armv4 \ ++ -o lowlevel_foo.o ../neo1973/common/lowlevel_foo.S ++ ++lowlevel_foo: lowlevel_foo.o lowlevel_init.o \ ++ ../neo1973/common/lowlevel_foo.lds ++ $(LD) -T ../neo1973/common/lowlevel_foo.lds -Ttext 0x33f80000 -Bstatic \ ++ lowlevel_init.o lowlevel_foo.o -o lowlevel_foo ++ ++lowevel_foo.bin: lowlevel_foo ++ $(CROSS_COMPILE)objcopy --gap-fill=0xff -O binary \ ++ lowlevel_foo lowlevel_foo.bin ++ + clean: +- rm -f $(SOBJS) $(OBJS) ++ rm -f $(SOBJS) $(OBJS) lowlevel_foo lowlevel_foo.o + + distclean: clean +- rm -f $(LIB) core *.bak .depend ++ rm -f $(LIB) core *.bak .depend lowlevel_foo.bin + + ######################################################################### + diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/mmcinit-power-up.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/mmcinit-power-up.patch new file mode 100644 index 0000000000..fcf54b9fd1 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/mmcinit-power-up.patch @@ -0,0 +1,73 @@ +board/neo1973/neo1973.c (board_late_init): moved MMC power-up to separate + function +cpu/arm920t/s3c24x0/mmc.c (mmc_init): call mmc_power_up and return -ENODEV + immediately if there is no card + +- Werner Almesberger + +Index: u-boot/board/neo1973/neo1973.c +=================================================================== +--- u-boot.orig/board/neo1973/neo1973.c ++++ u-boot/board/neo1973/neo1973.c +@@ -223,6 +223,19 @@ int board_init (void) + return 0; + } + ++int mmc_power_up(void) ++{ ++#if defined(CONFIG_ARCH_GTA01B_v4) ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ ++ /* check if sd card is inserted, and power-up if it is */ ++ if (gpio->GPFDAT & (1 << 5)) ++ return 0; ++ gpio->GPBDAT &= ~(1 << 2); ++#endif /* !CONFIG_ARCH_GTA01B_v4 */ ++ return 1; ++} ++ + int board_late_init(void) + { + unsigned char tmp; +@@ -289,14 +302,8 @@ continue_boot: + /* switch on the backlight */ + neo1973_backlight(1); + +-#if defined(CONFIG_ARCH_GTA01B_v4) +- { +- /* check if sd card is inserted, and power-up if it is */ +- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); +- if (!(gpio->GPFDAT & (1 << 5))) +- gpio->GPBDAT &= ~(1 << 2); +- } +-#endif ++ /* check if sd card is inserted, and power-up if it is */ ++ mmc_power_up(); + + return 0; + } +Index: u-boot/cpu/arm920t/s3c24x0/mmc.c +=================================================================== +--- u-boot.orig/cpu/arm920t/s3c24x0/mmc.c ++++ u-boot/cpu/arm920t/s3c24x0/mmc.c +@@ -381,6 +381,11 @@ static void print_sd_cid(const struct sd + cid->crc >> 1, cid->crc & 1); + } + ++int __attribute__((weak)) mmc_power_up(void) ++{ ++ return 1; ++} ++ + int mmc_init(int verbose) + { + int retries, rc = -ENODEV; +@@ -393,6 +398,8 @@ int mmc_init(int verbose) + debug("mmc_init(PCLK=%u)\n", get_PCLK()); + + clk_power->CLKCON |= (1 << 9); ++ if (!mmc_power_up()) ++ return -ENODEV; + + /* S3C2410 has some bug that prevents reliable operation at higher speed */ + //sdi->SDIPRE = 0x3e; /* SDCLK = PCLK/2 / (SDIPRE+1) = 396kHz */ diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/nand-badisbad.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/nand-badisbad.patch new file mode 100644 index 0000000000..a5800e2499 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/nand-badisbad.patch @@ -0,0 +1,30 @@ +This patch makes nand_block_checkbad check both the BBT and the actual +OOB data. This avoids accidently passing blocks as good when BBT and +OOB markers are not synchronized, e.g., before "nand createbbt". + +Experimental. + +- Werner Almesberger + +Index: u-boot/drivers/nand/nand_base.c +=================================================================== +--- u-boot.orig/drivers/nand/nand_base.c ++++ u-boot/drivers/nand/nand_base.c +@@ -517,11 +517,14 @@ static int nand_block_checkbad (struct m + { + struct nand_chip *this = mtd->priv; + +- if (!this->bbt) +- return this->block_bad(mtd, ofs, getchip); ++ if (this->block_bad(mtd, ofs, getchip)) ++ return 1; + + /* Return info from the table */ +- return nand_isbad_bbt (mtd, ofs, allowbbt); ++ if (this->bbt && nand_isbad_bbt (mtd, ofs, allowbbt)) ++ return 1; ++ ++ return 0; + } + + /** diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/nand-createbbt.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/nand-createbbt.patch new file mode 100644 index 0000000000..74b79da0a9 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/nand-createbbt.patch @@ -0,0 +1,126 @@ +This patch adds user-requested BBT creation. It includes the following changes: + +- common/cmd_nand.c: move yes/no decision to separate function +- do_nand: ask for confirmation for "nand erase" +- do_nand: add command "nand createbbt" to erase NAND and create a new BBT + +Experimental. + +- Werner Almesberger + + +Index: u-boot/common/cmd_nand.c +=================================================================== +--- u-boot.orig/common/cmd_nand.c 2007-02-16 23:53:28.000000000 +0100 ++++ u-boot/common/cmd_nand.c 2007-02-16 23:53:57.000000000 +0100 +@@ -163,6 +163,17 @@ + return 0; + } + ++static int yes(void) ++{ ++ char c; ++ ++ c = getc(); ++ if (c != 'y' && c != 'Y') ++ return 0; ++ c = getc(); ++ return c == '\r' || c == '\n'; ++} ++ + int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) + { + int i, dev, ret; +@@ -228,7 +239,8 @@ + strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0 && + strcmp(cmd, "scrub") != 0 && strcmp(cmd, "markbad") != 0 && + strcmp(cmd, "biterr") != 0 && +- strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 ) ++ strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 && ++ strcmp(cmd, "createbbt") != 0 ) + goto usage; + + /* the following commands operate on the current device */ +@@ -283,13 +295,23 @@ + "are sure of what you are doing!\n" + "\nReally scrub this NAND flash? \n"); + +- if (getc() == 'y' && getc() == '\r') { ++ if (yes()) { + opts.scrub = 1; + } else { + puts("scrub aborted\n"); + return -1; + } + } ++ else { ++ if (opts.length == nand->size) { ++ puts("Really erase everything ? \n"); ++ if (!yes()) { ++ puts("erase aborted\n"); ++ return -1; ++ } ++ } ++ } ++ + ret = nand_erase_opts(nand, &opts); + printf("%s\n", ret ? "ERROR" : "OK"); + +@@ -458,6 +480,33 @@ + return 0; + } + ++ if (strcmp(cmd, "createbbt") == 0) { ++ struct nand_chip *nand_chip = nand->priv; ++ nand_erase_options_t opts; ++ ++ puts("Create BBT and erase everything ? \n"); ++ if (!yes()) { ++ puts("createbbt aborted\n"); ++ return -1; ++ } ++ memset(&opts, 0, sizeof(opts)); ++ opts.length = nand->size; ++ if (nand_erase_opts(nand, &opts)) { ++ puts("Erase failed\n"); ++ return 1; ++ } ++ nand_chip->options &= ~NAND_DONT_CREATE_BBT; ++ puts("Creating BBT. Please wait ..."); ++ if (nand_default_bbt(nand)) { ++ puts("\nFailed\n"); ++ return 1; ++ } ++ else { ++ puts("\n"); ++ return 0; ++ } ++ } ++ + usage: + printf("Usage:\n%s\n", cmdtp->usage); + return 1; +@@ -478,7 +527,8 @@ + "nand markbad off - mark bad block at offset (UNSAFE)\n" + "nand biterr off - make a bit error at offset (UNSAFE)\n" + "nand lock [tight] [status] - bring nand to lock state or display locked pages\n" +- "nand unlock [offset] [size] - unlock section\n"); ++ "nand unlock [offset] [size] - unlock section\n" ++ "nand createbbt - create bad block table\n"); + + static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, + ulong offset, ulong addr, char *cmd) +Index: u-boot/drivers/nand/nand_bbt.c +=================================================================== +--- u-boot.orig/drivers/nand/nand_bbt.c 2007-02-16 23:53:54.000000000 +0100 ++++ u-boot/drivers/nand/nand_bbt.c 2007-02-16 23:53:57.000000000 +0100 +@@ -795,7 +795,8 @@ + + len = mtd->size >> (this->bbt_erase_shift + 2); + /* Allocate memory (2bit per block) */ +- this->bbt = kmalloc (len, GFP_KERNEL); ++ if (!this->bbt) ++ this->bbt = kmalloc (len, GFP_KERNEL); + if (!this->bbt) { + printk (KERN_ERR "nand_scan_bbt: Out of memory\n"); + return -ENOMEM; diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/nand-dynamic_partitions.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/nand-dynamic_partitions.patch new file mode 100644 index 0000000000..ecce004ca6 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/nand-dynamic_partitions.patch @@ -0,0 +1,354 @@ +This patch adds support for 'dynamic partitions'. This basically +works as follows: +* The nand code generates a bad-block-table at the first scan of the chip +* The dynamic partition code calculates the raw partition sizes based on + the bad block table. E.g. if you have a partition of size 0x30000, and there are + two bad blocks (0x4000 each) in it, the raw size will increase to 0x38000, and the + following partitions get shifted towards the end of flash. + +Please note that currently the desired partition sizes are stored at compile-time +in an array in drivers/nand/nand_bbt.c, so this definitely needs to change before +submitting/merging upstream. + +In order to calculate the partiton map (and set mtdparts accordingly), you can use +the 'dynpart' command at the prompt. Use 'saveenv' to make the setting permanent. + +Signed-off-by: Harald Welte + +Index: u-boot/drivers/nand/nand_bbt.c +=================================================================== +--- u-boot.orig/drivers/nand/nand_bbt.c ++++ u-boot/drivers/nand/nand_bbt.c +@@ -1044,9 +1044,86 @@ + switch ((int)res) { + case 0x00: return 0; + case 0x01: return 1; ++ case 0x03: return 1; + case 0x02: return allowbbt ? 0 : 1; + } + return 1; + } + ++#if defined(CONFIG_NAND_DYNPART) ++ ++extern unsigned int dynpart_size[]; ++extern char *dynpart_names[]; ++ ++#define MTDPARTS_MAX_SIZE 512 ++ ++ ++static int skip_offs(const struct nand_chip *this, unsigned int offs) ++{ ++ int block = (int) (offs >> (this->bbt_erase_shift - 1)); ++ u_int8_t bbt = (this->bbt[block >> 3] >> (block & 0x06)) & 0x03; ++ ++ return bbt == 3; ++} ++ ++int nand_create_mtd_dynpart(struct mtd_info *mtd) ++{ ++ struct nand_chip *this = mtd->priv; ++ int part; ++ char *mtdparts; ++ unsigned int cur_offs = 0; ++ ++ mtdparts = malloc(MTDPARTS_MAX_SIZE); /* FIXME: bounds checking */ ++ if (!mtdparts) ++ return -ENOMEM; ++ ++ sprintf(mtdparts, "mtdparts=" CFG_NAND_DYNPART_MTD_KERNEL_NAME ":"); ++ ++ for (part = 0; dynpart_size[part] != 0; part++) { ++ unsigned int bb_delta = 0; ++ unsigned int offs = 0; ++ char mtdpart[32]; ++ ++ for (offs = cur_offs; ++ offs < cur_offs + dynpart_size[part] + bb_delta; ++ offs += mtd->erasesize) { ++ if (skip_offs(this, offs)) ++ bb_delta += mtd->erasesize; ++ } ++ ++ /* ++ * Absorb bad blocks immediately following this partition also ++ * into the partition, in order to make next partition start ++ * with a good block. This simplifies handling of the ++ * environment partition. ++ */ ++ while (offs < this->chipsize && skip_offs(this, offs)) { ++ bb_delta += mtd->erasesize; ++ offs += mtd->erasesize; ++ } ++ ++ if (cur_offs + dynpart_size[part] + bb_delta > this->chipsize) ++ dynpart_size[part] = this->chipsize - cur_offs - bb_delta; ++#if 0 ++ printf("partition %u: start = 0x%08x, end=%08x size=%08x, size_inc_bb=%08x\n", ++ part, cur_offs, cur_offs + dynpart_size[part] + bb_delta, ++ dynpart_size[part], dynpart_size[part] + bb_delta); ++#endif ++ cur_offs += dynpart_size[part] + bb_delta; ++ sprintf(mtdpart, "0x%.8x(%.16s),", dynpart_size[part] + bb_delta, ++ dynpart_names[part]); ++ mtdpart[sizeof(mtdpart)-1] = '\0'; ++ strncat(mtdparts, mtdpart, ++ MTDPARTS_MAX_SIZE-strlen(mtdparts)-1); ++ } ++ ++ mtdparts[strlen(mtdparts)-1] = '\0'; ++ printf("mtdparts %s\n", mtdparts); ++ setenv("mtdparts", mtdparts); ++ ++ free(mtdparts); ++ return 0; ++} ++#endif /* CONFIG_NAND_DYNPART */ ++ + #endif +Index: u-boot/include/configs/neo1973_gta01.h +=================================================================== +--- u-boot.orig/include/configs/neo1973_gta01.h ++++ u-boot/include/configs/neo1973_gta01.h +@@ -99,7 +99,7 @@ + CFG_CMD_ELF | \ + CFG_CMD_MISC | \ + /* CFG_CMD_USB | */ \ +- /* CFG_CMD_JFFS2 | */ \ ++ CFG_CMD_JFFS2 | \ + CFG_CMD_DIAG | \ + /* CFG_CMD_HWFLOW | */ \ + CFG_CMD_SAVES | \ +@@ -212,13 +212,13 @@ + #define CONFIG_FAT 1 + #define CONFIG_SUPPORT_VFAT + +-#if 0 ++#if 1 + /* JFFS2 driver */ + #define CONFIG_JFFS2_CMDLINE 1 + #define CONFIG_JFFS2_NAND 1 + #define CONFIG_JFFS2_NAND_DEV 0 +-#define CONFIG_JFFS2_NAND_OFF 0x634000 +-#define CONFIG_JFFS2_NAND_SIZE 0x39cc000 ++//#define CONFIG_JFFS2_NAND_OFF 0x634000 ++//#define CONFIG_JFFS2_NAND_SIZE 0x39cc000 + #endif + + /* ATAG configuration */ +@@ -257,4 +257,9 @@ + + #define CONFIG_DRIVER_PCF50606 1 + ++#define MTDIDS_DEFAULT "nand0=neo1973-nand" ++#define MTPARTS_DEFAULT "neo1973-nand:256k(u-boot),16k(u-boot_env),2M(kernel),640k(splash),-(jffs2)" ++#define CFG_NAND_DYNPART_MTD_KERNEL_NAME "neo1973-nand" ++#define CONFIG_NAND_DYNPART ++ + #endif /* __CONFIG_H */ +Index: u-boot/common/cmd_jffs2.c +=================================================================== +--- u-boot.orig/common/cmd_jffs2.c ++++ u-boot/common/cmd_jffs2.c +@@ -1841,6 +1841,29 @@ + return NULL; + } + ++/* Return the 'net size' of the partition (i.e. excluding any bad blocks) */ ++unsigned int nand_net_part_size(struct part_info *part) ++{ ++ struct mtd_info *mtd; ++ unsigned int offs; ++ unsigned int bb_delta = 0; ++ ++ if (!part || !part->dev || !part->dev->id || ++ part->dev->id->num >= CFG_MAX_NAND_DEVICE) ++ return 0; ++ ++ mtd = &nand_info[part->dev->id->num]; ++ ++ for (offs = part->offset; offs < part->offset + part->size; ++ offs += mtd->erasesize) { ++ if (nand_isbad_bbt(mtd, offs, 0)) ++ bb_delta += mtd->erasesize; ++ } ++ ++ return part->size - bb_delta; ++} ++ ++ + /***************************************************/ + /* U-boot commands */ + /***************************************************/ +@@ -2132,6 +2155,24 @@ + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } ++ ++#if defined(CONFIG_NAND_DYNPART) ++extern int nand_create_mtd_dynpart(struct mtd_info *mtd); ++ ++int do_dynpart(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ++{ ++#if 0 ++ int i = simple_strtoul(argv[1], NULL, 0); ++ if (i >= CFG_MAX_NAND_DEVICE) ++ return -EINVAL; ++#endif ++ nand_create_mtd_dynpart(&nand_info[0]); ++ ++ return 0; ++} ++#endif /* CONFIG_NAND_DYNPART */ ++ ++ + #endif /* #ifdef CONFIG_JFFS2_CMDLINE */ + + /***************************************************/ +@@ -2197,6 +2238,15 @@ + " := '(' NAME ')'\n" + " := when set to 'ro' makes partition read-only (not used, passed to kernel)\n" + ); ++ ++#if defined(CONFIG_NAND_DYNPART) ++U_BOOT_CMD( ++ dynpart, 1, 1, do_dynpart, ++ "dynpart\t- dynamically calculate partition table based on BBT\n", ++ "\n" ++ " - sets 'mtdparts' according to BBT\n"); ++#endif /* CONFIG_NAND_DYNPART */ ++ + #endif /* #ifdef CONFIG_JFFS2_CMDLINE */ + + /***************************************************/ +Index: u-boot/common/cmd_nand.c +=================================================================== +--- u-boot.orig/common/cmd_nand.c ++++ u-boot/common/cmd_nand.c +@@ -101,7 +101,7 @@ + } + + int +-arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, ulong *size) ++arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, ulong *size, int net) + { + int idx = nand_curr_device; + #if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) +@@ -122,10 +122,17 @@ + printf("'%s' is not a number\n", argv[1]); + return -1; + } +- if (*size > part->size) +- *size = part->size; ++ if (*size > part->size) { ++ if (net) ++ *size = nand_net_part_size(part); ++ else ++ *size = part->size; ++ } + } else { +- *size = part->size; ++ if (net) ++ *size = nand_net_part_size(part); ++ else ++ *size = part->size; + } + idx = dev->id->num; + *nand = nand_info[idx]; +@@ -261,7 +268,7 @@ + + printf("\nNAND %s: ", scrub ? "scrub" : "erase"); + /* skip first two or three arguments, look for offset and size */ +- if (arg_off_size(argc - o, argv + o, nand, &off, &size) != 0) ++ if (arg_off_size(argc - o, argv + o, nand, &off, &size, 0) != 0) + return 1; + + memset(&opts, 0, sizeof(opts)); +@@ -323,7 +330,7 @@ + + read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */ + printf("\nNAND %s: ", read ? "read" : "write"); +- if (arg_off_size(argc - 3, argv + 3, nand, &off, &size) != 0) ++ if (arg_off_size(argc - 3, argv + 3, nand, &off, &size, 1) != 0) + return 1; + + s = strchr(cmd, '.'); +@@ -445,7 +452,7 @@ + } + + if (strcmp(cmd, "unlock") == 0) { +- if (arg_off_size(argc - 2, argv + 2, nand, &off, &size) < 0) ++ if (arg_off_size(argc - 2, argv + 2, nand, &off, &size, 0) < 0) + return 1; + + if (!nand_unlock(nand, off, size)) { +Index: u-boot/common/cmd_dynenv.c +=================================================================== +--- u-boot.orig/common/cmd_dynenv.c ++++ u-boot/common/cmd_dynenv.c +@@ -60,7 +60,7 @@ + buf[2] = 'V'; + buf[3] = '0'; + +- if (arg_off_size(argc-2, argv+2, mtd, &addr, &dummy) < 0) { ++ if (arg_off_size(argc-2, argv+2, mtd, &addr, &dummy, 1) < 0) { + printf("Offset or partition name expected\n"); + goto fail; + } +Index: u-boot/include/util.h +=================================================================== +--- u-boot.orig/include/util.h ++++ u-boot/include/util.h +@@ -28,6 +28,6 @@ + + /* common/cmd_nand.c */ + int arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, +- ulong *size); ++ ulong *size, int net); + + #endif /* UTIL_H */ +Index: u-boot/board/qt2410/qt2410.c +=================================================================== +--- u-boot.orig/board/qt2410/qt2410.c ++++ u-boot/board/qt2410/qt2410.c +@@ -126,3 +126,9 @@ + + return 0; + } ++ ++unsigned int dynpart_size[] = { ++ CFG_UBOOT_SIZE, 0x4000, 0x200000, 0xa0000, 0x3d5c000-CFG_UBOOT_SIZE, 0 }; ++char *dynpart_names[] = { ++ "u-boot", "u-boot_env", "kernel", "splash", "rootfs", NULL }; ++ +Index: u-boot/board/neo1973/gta01/gta01.c +=================================================================== +--- u-boot.orig/board/neo1973/gta01/gta01.c ++++ u-boot/board/neo1973/gta01/gta01.c +@@ -429,3 +434,14 @@ + return 0; + } + ++ ++/* The sum of all part_size[]s must equal to the NAND size, i.e., 0x4000000. ++ "initrd" is sized such that it can hold two uncompressed 16 bit 640*480 ++ images: 640*480*2*2 = 1228800 < 1245184. */ ++ ++unsigned int dynpart_size[] = { ++ CFG_UBOOT_SIZE, 0x4000, 0x200000, 0xa0000, 0x3d5c000-CFG_UBOOT_SIZE, 0 }; ++char *dynpart_names[] = { ++ "u-boot", "u-boot_env", "kernel", "splash", "rootfs", NULL }; ++ ++ +Index: u-boot/include/configs/qt2410.h +=================================================================== +--- u-boot.orig/include/configs/qt2410.h ++++ u-boot/include/configs/qt2410.h +@@ -283,5 +283,7 @@ + + #define MTDIDS_DEFAULT "nand0=qt2410-nand" + #define MTPARTS_DEFAULT "qt2410-nand:192k(u-boot),8k(u-boot_env),2M(kernel),2M(splash),-(jffs2)" ++#define CFG_NAND_DYNPART_MTD_KERNEL_NAME "qt2410-nand" ++#define CONFIG_NAND_DYNPART + + #endif /* __CONFIG_H */ diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/nand-otp.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/nand-otp.patch new file mode 100644 index 0000000000..b0e9bf4c4b --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/nand-otp.patch @@ -0,0 +1,302 @@ +Index: u-boot/common/cmd_nand.c +=================================================================== +--- u-boot.orig/common/cmd_nand.c ++++ u-boot/common/cmd_nand.c +@@ -392,6 +392,14 @@ + else + ret = nand->write_oob(nand, off, size, &size, + (u_char *) addr); ++ } else if (s != NULL && !strcmp(s, ".otp")) { ++ /* read out-of-band data */ ++ if (read) ++ ret = nand->read_otp(nand, off, size, &size, ++ (u_char *) addr); ++ else ++ ret = nand->write_otp(nand, off, size, &size, ++ (u_char *) addr); + } else { + if (read) + ret = nand_read(nand, off, &size, (u_char *)addr); +@@ -527,8 +535,9 @@ + "nand - NAND sub-system\n", + "info - show available NAND devices\n" + "nand device [dev] - show or set current device\n" +- "nand read[.jffs2] - addr off|partition size\n" +- "nand write[.jffs2] - addr off|partiton size - read/write `size' bytes starting\n" ++ "nand read[.jffs2, .oob, .otp] addr off|partition size\n" ++ "nand write[.jffs2, .oob, .otp] addr off|partiton size\n" ++ " - read/write `size' bytes starting\n" + " at offset `off' to/from memory address `addr'\n" + "nand erase [clean] [off size] - erase `size' bytes from\n" + " offset `off' (entire device if not specified)\n" +Index: u-boot/cpu/arm920t/s3c24x0/nand.c +=================================================================== +--- u-boot.orig/cpu/arm920t/s3c24x0/nand.c ++++ u-boot/cpu/arm920t/s3c24x0/nand.c +@@ -205,7 +205,7 @@ + } + #endif + +-int board_nand_init(struct nand_chip *nand) ++int s3c24x0_nand_init(struct nand_chip *nand) + { + u_int32_t cfg; + u_int8_t tacls, twrph0, twrph1; +Index: u-boot/drivers/nand/nand_base.c +=================================================================== +--- u-boot.orig/drivers/nand/nand_base.c ++++ u-boot/drivers/nand/nand_base.c +@@ -2042,6 +2042,32 @@ + } + #endif + ++/* ++ * See nand_read_oob and nand_write_oob ++ */ ++ ++static int nand_read_otp(struct mtd_info *mtd, loff_t from, size_t len, ++ size_t *retlen, u_char *buf) ++{ ++ struct nand_chip *this = mtd->priv; ++ ++ if (!this->read_otp) ++ return -ENOSYS; ++ return this->read_otp(mtd, from, len, retlen, buf); ++ ++} ++ ++static int nand_write_otp(struct mtd_info *mtd, loff_t to, size_t len, ++ size_t *retlen, const u_char *buf) ++{ ++ struct nand_chip *this = mtd->priv; ++ ++ if (!this->write_otp) ++ return -ENOSYS; ++ return this->write_otp(mtd, to, len, retlen, buf); ++} ++ ++ + /** + * single_erease_cmd - [GENERIC] NAND standard block erase command function + * @mtd: MTD device structure +@@ -2613,6 +2639,8 @@ + mtd->write_ecc = nand_write_ecc; + mtd->read_oob = nand_read_oob; + mtd->write_oob = nand_write_oob; ++ mtd->read_otp = nand_read_otp; ++ mtd->write_otp = nand_write_otp; + /* XXX U-BOOT XXX */ + #if 0 + mtd->readv = NULL; +Index: u-boot/include/linux/mtd/mtd.h +=================================================================== +--- u-boot.orig/include/linux/mtd/mtd.h ++++ u-boot/include/linux/mtd/mtd.h +@@ -95,6 +95,9 @@ + int (*read_oob) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); + int (*write_oob) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf); + ++ int (*read_otp) (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf); ++ int (*write_otp) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf); ++ + /* + * Methods to access the protection register area, present in some + * flash devices. The user data is one time programmable but the +Index: u-boot/include/linux/mtd/nand.h +=================================================================== +--- u-boot.orig/include/linux/mtd/nand.h ++++ u-boot/include/linux/mtd/nand.h +@@ -307,6 +307,10 @@ + void (*enable_hwecc)(struct mtd_info *mtd, int mode); + void (*erase_cmd)(struct mtd_info *mtd, int page); + int (*scan_bbt)(struct mtd_info *mtd); ++ int (*read_otp)(struct mtd_info *mtd, loff_t from, ++ size_t len, size_t *retlen, u_char *buf); ++ int (*write_otp) (struct mtd_info *mtd, loff_t to, ++ size_t len, size_t *retlen, const u_char *buf); + int eccmode; + int eccsize; + int eccbytes; +Index: u-boot/board/neo1973/gta01/Makefile +=================================================================== +--- u-boot.orig/board/neo1973/gta01/Makefile ++++ u-boot/board/neo1973/gta01/Makefile +@@ -25,7 +25,7 @@ + + LIB = lib$(BOARD).a + +-OBJS := gta01.o pcf50606.o ../common/cmd_neo1973.o ../common/jbt6k74.o ../common/udc.o ../common/bootmenu.o ++OBJS := gta01.o pcf50606.o nand.o ../common/cmd_neo1973.o ../common/jbt6k74.o ../common/udc.o ../common/bootmenu.o + SOBJS := ../common/lowlevel_init.o + + .PHONY: all +Index: u-boot/board/neo1973/gta01/nand.c +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/gta01/nand.c +@@ -0,0 +1,121 @@ ++/* ++ * nand.c - Board-specific NAND setup ++ * ++ * Copyright (C) 2007 by OpenMoko, Inc. ++ * Written by Werner Almesberger ++ * All Rights Reserved ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++ ++#include "config.h" /* nand.h needs NAND_MAX_CHIPS */ ++#include "linux/mtd/mtd.h" ++#include "linux/mtd/nand.h" ++#include "asm/errno.h" ++ ++ ++int s3c24x0_nand_init(struct nand_chip *nand); ++ ++ ++static void samsung_nand_begin_otp(struct mtd_info *mtd) ++{ ++ struct nand_chip *this = mtd->priv; ++ ++ /* @@@FIXME: this is ugly - we select the NAND chip to send the ++ mode switch commands, knowing that it will be switched off later */ ++ this->select_chip(mtd, 0); ++ /* "magic" mode change */ ++ this->cmdfunc(mtd, 0x30, -1, -1); ++ this->cmdfunc(mtd, 0x65, -1, -1); ++} ++ ++ ++static void samsung_nand_end_otp(struct mtd_info *mtd) ++{ ++ struct nand_chip *this = mtd->priv; ++ ++ /* read/write deselected the chip so now we need to select again */ ++ this->select_chip(mtd, 0); ++ this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); ++ this->select_chip(mtd, -1); ++} ++ ++ ++static loff_t otp_page[] = { ++ 0x15, /* 00-XX-00-00, with XX = 15h-19h */ ++ 0x16, ++ 0x17, ++ 0x18, ++ 0x19, ++ 0x1b, /* 00-1B-00-00 */ ++}; ++ ++#define OTP_PAGES (sizeof(otp_page)/sizeof(*otp_page)) ++ ++ ++static int convert_otp_address(loff_t *addr, size_t *len) ++{ ++ int page; ++ ++ if (*len && *addr >> 9 != (*addr+*len-1) >> 9) ++ return -EINVAL; ++ if (*len > 512) ++ return -EINVAL; ++ page = *addr >> 9; ++ if (page >= OTP_PAGES) ++ return -EINVAL; ++ *addr = otp_page[page] << 9; ++ return 0; ++} ++ ++ ++static int samsung_nand_read_otp(struct mtd_info *mtd, loff_t from, ++ size_t len, size_t *retlen, u_char *buf) ++{ ++ int ret; ++ ++ ret = convert_otp_address(&from, &len); ++ if (ret) ++ return ret; ++ samsung_nand_begin_otp(mtd); ++ ret = mtd->read(mtd, from, len, retlen, buf); ++ samsung_nand_end_otp(mtd); ++ return ret; ++} ++ ++ ++static int samsung_nand_write_otp(struct mtd_info *mtd, loff_t to, ++ size_t len, size_t *retlen, const u_char *buf) ++{ ++ int ret; ++ ++ ret = convert_otp_address(&to, &len); ++ if (ret) ++ return ret; ++ samsung_nand_begin_otp(mtd); ++ ret = mtd->write(mtd, to, len, retlen, buf); ++ samsung_nand_end_otp(mtd); ++ return ret; ++} ++ ++ ++int board_nand_init(struct nand_chip *nand) ++{ ++ nand->read_otp = samsung_nand_read_otp; ++ nand->write_otp = samsung_nand_write_otp; ++ return s3c24x0_nand_init(nand); ++} +Index: u-boot/board/neo1973/gta02/nand.c +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/gta02/nand.c +@@ -0,0 +1,39 @@ ++/* ++ * nand.c - Board-specific NAND setup ++ * ++ * Copyright (C) 2007 by OpenMoko, Inc. ++ * Written by Werner Almesberger ++ * All Rights Reserved ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++ ++#include "config.h" /* nand.h needs NAND_MAX_CHIPS */ ++#include "linux/mtd/mtd.h" ++#include "linux/mtd/nand.h" ++ ++ ++int s3c24x0_nand_init(struct nand_chip *nand); ++ ++ ++/* Add OTP et al later */ ++ ++ ++int board_nand_init(struct nand_chip *nand) ++{ ++ return s3c24x0_nand_init(nand); ++} diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/nand-read_write_oob.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/nand-read_write_oob.patch new file mode 100644 index 0000000000..8360409e46 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/nand-read_write_oob.patch @@ -0,0 +1,23 @@ +Re-introduce the 'nand read.oob' and 'nand write.oob' commands +that used to exist with the legacy NAND code + +Signed-off-by: Harald Welte +Index: u-boot.git/common/cmd_nand.c +=================================================================== +--- u-boot.git.orig/common/cmd_nand.c 2007-01-26 15:41:13.000000000 +0100 ++++ u-boot.git/common/cmd_nand.c 2007-01-26 15:49:37.000000000 +0100 +@@ -351,6 +351,14 @@ + opts.quiet = quiet; + ret = nand_write_opts(nand, &opts); + } ++ } else if (s != NULL && !strcmp(s, ".oob")) { ++ /* read out-of-band data */ ++ if (read) ++ ret = nand->read_oob(nand, off, size, &size, ++ (u_char *) addr); ++ else ++ ret = nand->write_oob(nand, off, size, &size, ++ (u_char *) addr); + } else { + if (read) + ret = nand_read(nand, off, &size, (u_char *)addr); diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/neo1973-chargefast.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/neo1973-chargefast.patch new file mode 100644 index 0000000000..6f6af2c758 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/neo1973-chargefast.patch @@ -0,0 +1,316 @@ +Index: u-boot/drivers/usbtty.c +=================================================================== +--- u-boot.orig/drivers/usbtty.c ++++ u-boot/drivers/usbtty.c +@@ -66,7 +66,7 @@ + /* + * Defines + */ +-#define NUM_CONFIGS 1 ++#define NUM_CONFIGS 2 + #define MAX_INTERFACES 2 + #define NUM_ENDPOINTS 3 + #define ACM_TX_ENDPOINT 3 +@@ -192,8 +192,7 @@ + #endif + .bConfigurationValue = 1, + .iConfiguration = STR_CONFIG, +- .bmAttributes = +- BMATTRIBUTE_SELF_POWERED|BMATTRIBUTE_RESERVED, ++ .bmAttributes = BMATTRIBUTE_RESERVED, + .bMaxPower = USBTTY_MAXPOWER + }, + /* Interface 1 */ +@@ -294,6 +293,120 @@ + .func_dfu = DFU_FUNC_DESC, + #endif + }, ++ { ++ .configuration_desc ={ ++ .bLength = ++ sizeof(struct usb_configuration_descriptor), ++ .bDescriptorType = USB_DT_CONFIG, ++ .wTotalLength = ++ cpu_to_le16(sizeof(struct acm_config_desc) ++#ifdef CONFIG_USBD_DFU ++ - sizeof(struct usb_interface_descriptor) ++ - sizeof(struct usb_dfu_func_descriptor) ++#endif ++ ), ++ .bNumInterfaces = NUM_ACM_INTERFACES, ++ .bConfigurationValue = 2, ++ .iConfiguration = STR_CONFIG, ++ .bmAttributes = BMATTRIBUTE_RESERVED, ++ .bMaxPower = 50, /* 100mA */ ++ }, ++ /* Interface 1 */ ++ .interface_desc = { ++ .bLength = sizeof(struct usb_interface_descriptor), ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = 0, ++ .bAlternateSetting = 0, ++ .bNumEndpoints = 0x01, ++ .bInterfaceClass = ++ COMMUNICATIONS_INTERFACE_CLASS_CONTROL, ++ .bInterfaceSubClass = COMMUNICATIONS_ACM_SUBCLASS, ++ .bInterfaceProtocol = COMMUNICATIONS_V25TER_PROTOCOL, ++ .iInterface = STR_CTRL_INTERFACE, ++ }, ++ .usb_class_header = { ++ .bFunctionLength = ++ sizeof(struct usb_class_header_function_descriptor), ++ .bDescriptorType = CS_INTERFACE, ++ .bDescriptorSubtype = USB_ST_HEADER, ++ .bcdCDC = cpu_to_le16(110), ++ }, ++ .usb_class_call_mgt = { ++ .bFunctionLength = ++ sizeof(struct usb_class_call_management_descriptor), ++ .bDescriptorType = CS_INTERFACE, ++ .bDescriptorSubtype = USB_ST_CMF, ++ .bmCapabilities = 0x00, ++ .bDataInterface = 0x01, ++ }, ++ .usb_class_acm = { ++ .bFunctionLength = ++ sizeof(struct usb_class_abstract_control_descriptor), ++ .bDescriptorType = CS_INTERFACE, ++ .bDescriptorSubtype = USB_ST_ACMF, ++ .bmCapabilities = 0x00, ++ }, ++ .usb_class_union = { ++ .bFunctionLength = ++ sizeof(struct usb_class_union_function_descriptor), ++ .bDescriptorType = CS_INTERFACE, ++ .bDescriptorSubtype = USB_ST_UF, ++ .bMasterInterface = 0x00, ++ .bSlaveInterface0 = 0x01, ++ }, ++ .notification_endpoint = { ++ .bLength = ++ sizeof(struct usb_endpoint_descriptor), ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = 0x01 | USB_DIR_IN, ++ .bmAttributes = USB_ENDPOINT_XFER_INT, ++ .wMaxPacketSize ++ = cpu_to_le16(CONFIG_USBD_SERIAL_INT_PKTSIZE), ++ .bInterval = 0xFF, ++ }, ++ ++ /* Interface 2 */ ++ .data_class_interface = { ++ .bLength = ++ sizeof(struct usb_interface_descriptor), ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = 0x01, ++ .bAlternateSetting = 0x00, ++ .bNumEndpoints = 0x02, ++ .bInterfaceClass = ++ COMMUNICATIONS_INTERFACE_CLASS_DATA, ++ .bInterfaceSubClass = DATA_INTERFACE_SUBCLASS_NONE, ++ .bInterfaceProtocol = DATA_INTERFACE_PROTOCOL_NONE, ++ .iInterface = STR_DATA_INTERFACE, ++ }, ++ .data_endpoints = { ++ { ++ .bLength = ++ sizeof(struct usb_endpoint_descriptor), ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = 0x02 | USB_DIR_OUT, ++ .bmAttributes = ++ USB_ENDPOINT_XFER_BULK, ++ .wMaxPacketSize = ++ cpu_to_le16(CONFIG_USBD_SERIAL_BULK_PKTSIZE), ++ .bInterval = 0xFF, ++ }, ++ { ++ .bLength = ++ sizeof(struct usb_endpoint_descriptor), ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = 0x03 | USB_DIR_IN, ++ .bmAttributes = ++ USB_ENDPOINT_XFER_BULK, ++ .wMaxPacketSize = ++ cpu_to_le16(CONFIG_USBD_SERIAL_BULK_PKTSIZE), ++ .bInterval = 0xFF, ++ }, ++ }, ++ /* We don't add the DFU functional descriptor here since we only ++ * want to do DFU in the high-current charging mode for safety reasons */ ++ }, ++ + }; + + static struct rs232_emu rs232_desc={ +@@ -330,8 +443,7 @@ + .bNumInterfaces = NUM_GSERIAL_INTERFACES, + .bConfigurationValue = 1, + .iConfiguration = STR_CONFIG, +- .bmAttributes = +- BMATTRIBUTE_SELF_POWERED|BMATTRIBUTE_RESERVED, ++ .bmAttributes = BMATTRIBUTE_RESERVED, + .bMaxPower = USBTTY_MAXPOWER + }, + .interface_desc = { +@@ -384,6 +496,68 @@ + }, + }, + }, ++ { ++ .configuration_desc ={ ++ .bLength = sizeof(struct usb_configuration_descriptor), ++ .bDescriptorType = USB_DT_CONFIG, ++ .wTotalLength = ++ cpu_to_le16(sizeof(struct gserial_config_desc)), ++ .bNumInterfaces = NUM_GSERIAL_INTERFACES, ++ .bConfigurationValue = 1, ++ .iConfiguration = STR_CONFIG, ++ .bmAttributes = BMATTRIBUTE_RESERVED, ++ .bMaxPower = 50 ++ }, ++ .interface_desc = { ++ { ++ .bLength = ++ sizeof(struct usb_interface_descriptor), ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = 0, ++ .bAlternateSetting = 0, ++ .bNumEndpoints = NUM_ENDPOINTS, ++ .bInterfaceClass = ++ COMMUNICATIONS_INTERFACE_CLASS_VENDOR, ++ .bInterfaceSubClass = ++ COMMUNICATIONS_NO_SUBCLASS, ++ .bInterfaceProtocol = ++ COMMUNICATIONS_NO_PROTOCOL, ++ .iInterface = STR_DATA_INTERFACE ++ }, ++ }, ++ .data_endpoints = { ++ { ++ .bLength = ++ sizeof(struct usb_endpoint_descriptor), ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = 0x01 | USB_DIR_OUT, ++ .bmAttributes = USB_ENDPOINT_XFER_BULK, ++ .wMaxPacketSize = ++ cpu_to_le16(CONFIG_USBD_SERIAL_OUT_PKTSIZE), ++ .bInterval= 0xFF, ++ }, ++ { ++ .bLength = ++ sizeof(struct usb_endpoint_descriptor), ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = 0x02 | USB_DIR_IN, ++ .bmAttributes = USB_ENDPOINT_XFER_BULK, ++ .wMaxPacketSize = ++ cpu_to_le16(CONFIG_USBD_SERIAL_IN_PKTSIZE), ++ .bInterval = 0xFF, ++ }, ++ { ++ .bLength = ++ sizeof(struct usb_endpoint_descriptor), ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = 0x03 | USB_DIR_IN, ++ .bmAttributes = USB_ENDPOINT_XFER_INT, ++ .wMaxPacketSize = ++ cpu_to_le16(CONFIG_USBD_SERIAL_INT_PKTSIZE), ++ .bInterval = 0xFF, ++ }, ++ }, ++ }, + }; + + /* +@@ -679,12 +853,14 @@ + bus_instance->maxpacketsize = 64; + bus_instance->serial_number_str = serial_number; + +- /* configuration instance */ +- memset (config_instance, 0, +- sizeof (struct usb_configuration_instance)); +- config_instance->interfaces = interface_count; +- config_instance->configuration_descriptor = configuration_descriptor; +- config_instance->interface_instance_array = interface_instance; ++ /* configuration instances */ ++ for (i = 0; i < NUM_CONFIGS; i++) { ++ memset(&config_instance[i], 0, sizeof(config_instance)); ++ config_instance[i].interfaces = interface_count; ++ /* FIXME: this breaks for the non-ACM case */ ++ config_instance[i].configuration_descriptor = &acm_configuration_descriptors[i]; ++ config_instance[i].interface_instance_array = interface_instance; ++ } + + /* interface instance */ + memset (interface_instance, 0, +@@ -1043,9 +1219,17 @@ + usbtty_configured_flag = 0; + break; + case DEVICE_CONFIGURED: ++ printf("DEVICE_CONFIGURED: %u\n", device->configuration); ++ if (device->configuration == 1) ++ udc_ctrl(UDC_CTRL_500mA_ENABLE, 1); ++ else ++ udc_ctrl(UDC_CTRL_500mA_ENABLE, 0); + usbtty_configured_flag = 1; + break; +- ++ case DEVICE_DE_CONFIGURED: ++ printf("DEVICE_DE_CONFIGURED\n"); ++ udc_ctrl(UDC_CTRL_500mA_ENABLE, 0); ++ break; + case DEVICE_ADDRESS_ASSIGNED: + usbtty_init_endpoints (); + +Index: u-boot/drivers/usbtty.h +=================================================================== +--- u-boot.orig/drivers/usbtty.h ++++ u-boot/drivers/usbtty.h +@@ -60,7 +60,7 @@ + #define USBTTY_DEVICE_CLASS COMMUNICATIONS_DEVICE_CLASS + + #define USBTTY_BCD_DEVICE 0x00 +-#define USBTTY_MAXPOWER 0x00 ++#define USBTTY_MAXPOWER 250 /* 500mA */ + + #define STR_LANG 0x00 + #define STR_MANUFACTURER 0x01 +Index: u-boot/board/neo1973/common/udc.c +=================================================================== +--- u-boot.orig/board/neo1973/common/udc.c ++++ u-boot/board/neo1973/common/udc.c +@@ -2,6 +2,7 @@ + #include + #include + #include ++#include + + void udc_ctrl(enum usbd_event event, int param) + { +@@ -17,6 +18,13 @@ + gpio->GPBDAT &= ~(1 << 9); + #endif + break; ++ case UDC_CTRL_500mA_ENABLE: ++#if defined(CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4) || \ ++ defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3) || \ ++ defined(CONFIG_ARCH_GTA01B_v4) ++ pcf50606_charge_autofast(param); ++#endif ++ break; + default: + break; + } +Index: u-boot/include/usbdcore.h +=================================================================== +--- u-boot.orig/include/usbdcore.h ++++ u-boot/include/usbdcore.h +@@ -686,8 +686,8 @@ + + enum usbd_event { + UDC_CTRL_PULLUP_ENABLE, ++ UDC_CTRL_500mA_ENABLE, + }; + + void udc_ctrl(enum usbd_event event, int param); + #endif +-#endif diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/preboot-override.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/preboot-override.patch new file mode 100644 index 0000000000..f32cbde27b --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/preboot-override.patch @@ -0,0 +1,137 @@ +Provide a place where the loader can patch the binary, such that it executes a +command string from RAM. We use this for automated installs, where we can thus +use the same u-boot binary for all stages. + +include/configs/neo1973.h: new option CFG_PREBOOT_OVERRIDE to allow setting of + the preboot command in memory +cpu/arm920t/start.S: added variable "preboot_override" at known location + (_start+0x40) +common/main.c (main_loop): if preboot_override is set, execute the command + string found there +common/env_common.c (env_relocate): if preboot_override is set, always use the + default environment + +- Werner Almesberger + +Index: u-boot/cpu/arm920t/start.S +=================================================================== +--- u-boot.orig/cpu/arm920t/start.S ++++ u-boot/cpu/arm920t/start.S +@@ -77,6 +77,14 @@ _fiq: .word fiq + ************************************************************************* + */ + ++ ++/* Must follow the .balign above, so we get a well-known address ! */ ++#ifdef CFG_PREBOOT_OVERRIDE ++.globl preboot_override ++preboot_override: ++ .word 0 ++#endif ++ + #ifdef CONFIG_S3C2410_NAND_BOOT + .globl booted_from_nand + booted_from_nand: +Index: u-boot/include/configs/neo1973_gta01.h +=================================================================== +--- u-boot.orig/include/configs/neo1973_gta01.h ++++ u-boot/include/configs/neo1973_gta01.h +@@ -207,6 +207,7 @@ + #define CFG_ENV_IS_IN_NAND 1 + #define CFG_ENV_SIZE 0x4000 /* 16k Total Size of Environment Sector */ + #define CFG_ENV_OFFSET_OOB 1 /* Location of ENV stored in block 0 OOB */ ++#define CFG_PREBOOT_OVERRIDE 1 /* allow preboot from memory */ + + #define NAND_MAX_CHIPS 1 + #define CFG_NAND_BASE 0x4e000000 +Index: u-boot/common/main.c +=================================================================== +--- u-boot.orig/common/main.c ++++ u-boot/common/main.c +@@ -85,6 +85,11 @@ int do_mdm_init = 0; + extern void mdm_init(void); /* defined in board.c */ + #endif + ++#ifdef CFG_PREBOOT_OVERRIDE ++extern char *preboot_override; ++#endif ++ ++ + /*************************************************************************** + * Watch for 'delay' seconds for autoboot stop or autoboot delay string. + * returns: 0 - no key string, allow autoboot +@@ -306,8 +311,8 @@ void main_loop (void) + char *s; + int bootdelay; + #endif +-#ifdef CONFIG_PREBOOT +- char *p; ++#if defined(CONFIG_PREBOOT) || defined(CFG_PREBOOT_OVERRIDE) ++ char *p = NULL; + #endif + #ifdef CONFIG_BOOTCOUNT_LIMIT + unsigned long bootcount = 0; +@@ -364,8 +369,23 @@ void main_loop (void) + install_auto_complete(); + #endif + ++#if defined(CONFIG_PREBOOT) || defined(CFG_PREBOOT_OVERRIDE) + #ifdef CONFIG_PREBOOT +- if ((p = getenv ("preboot")) != NULL) { ++ p = getenv ("preboot"); ++#endif ++#ifdef CFG_PREBOOT_OVERRIDE ++ if (preboot_override) { ++ /* for convenience, preboot_override may end in \n, not \0 */ ++ p = strchr(preboot_override, '\n'); ++ if (p) ++ *p = 0; ++ /* make sure we can overwrite the load area if we want to */ ++ p = strdup(preboot_override); ++ /* clean the image in case we want to flash it */ ++ preboot_override = NULL; ++ } ++#endif /* CFG_PREBOOT_OVERRIDE */ ++ if (p) { + # ifdef CONFIG_AUTOBOOT_KEYED + int prev = disable_ctrlc(1); /* disable Control C checking */ + # endif +@@ -381,7 +401,7 @@ void main_loop (void) + disable_ctrlc(prev); /* restore Control C checking */ + # endif + } +-#endif /* CONFIG_PREBOOT */ ++#endif /* CONFIG_PREBOOT || CFG_PREBOOT_OVERRIDE */ + + #if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) + s = getenv ("bootdelay"); +Index: u-boot/common/env_common.c +=================================================================== +--- u-boot.orig/common/env_common.c ++++ u-boot/common/env_common.c +@@ -37,6 +37,10 @@ + # define SHOW_BOOT_PROGRESS(arg) + #endif + ++#ifdef CFG_PREBOOT_OVERRIDE ++extern char *preboot_override; ++#endif ++ + DECLARE_GLOBAL_DATA_PTR; + + #ifdef CONFIG_AMIGAONEG3SE +@@ -234,7 +238,14 @@ void env_relocate (void) + puts ("*** Warning - bad CRC, using default environment\n\n"); + SHOW_BOOT_PROGRESS (-1); + #endif ++ } ++ ++#ifdef CFG_PREBOOT_OVERRIDE ++ if (preboot_override) ++ gd->env_valid = 0; ++#endif + ++ if (gd->env_valid == 0) { + if (sizeof(default_environment) > ENV_SIZE) + { + puts ("*** Error - default environment is too large\n\n"); diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/raise-limits.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/raise-limits.patch new file mode 100644 index 0000000000..a1c381a2cf --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/raise-limits.patch @@ -0,0 +1,31 @@ +include/configs/neo1973.h: increase heap from 128 kB to 400 kB, for BMP image + decompression + [ note: increasing it to 512 kB trips over something. note sure what. + find out. ] +include/configs/neo1973.h: raise number of command line arguments from 16 to 64 + +- Werner Almesberger + +Index: u-boot/include/configs/neo1973_gta01.h +=================================================================== +--- u-boot.orig/include/configs/neo1973_gta01.h ++++ u-boot/include/configs/neo1973_gta01.h +@@ -54,7 +54,8 @@ + /* + * Size of malloc() pool + */ +-#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) ++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 400*1024) ++ /* >> CFG_VIDEO_LOGO_MAX_SIZE */ + #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + + /* +@@ -142,7 +143,7 @@ + #endif + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +-#define CFG_MAXARGS 16 /* max number of command args */ ++#define CFG_MAXARGS 64 /* max number of command args */ + #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + + #define CFG_MEMTEST_START 0x30000000 /* memtest works on */ diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/series b/packages/u-boot/u-boot-mkimage-openmoko-native/series new file mode 100644 index 0000000000..4fc7d1342f --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/series @@ -0,0 +1,76 @@ +# just some local hacks +uboot-machtypes.patch +ext2load_hex.patch +uboot-mokoversion.patch + +# those we want to get mainline +uboot-s3c2410-warnings-fix.patch +uboot-strtoul.patch +uboot-cramfs_but_no_jffs2.patch +nand-read_write_oob.patch +uboot-arm920t-gd_in_irq.patch +uboot-arm920_s3c2410_irq_demux.patch +uboot-s3c2410-nand.patch +uboot-cmd_s3c2410.patch +uboot-s3c2410-mmc.patch +env_nand_oob.patch +dynenv-harden.patch +uboot-s3c2410_fb.patch +uboot-20061030-qt2410.patch +uboot-20061030-neo1973.patch + +# under construction, but intended for mainline +uboot-s3c2410-misccr-definitions.patch + +boot-from-ram-reloc.patch +boot-from-ram-and-nand.patch +wakeup-reason-nand-only.patch +uboot-neo1973-resume.patch + +# this will be somewhat more difficult +nand-dynamic_partitions.patch +uboot-s3c2410-norelocate_irqvec_cpy.patch +uboot-usbtty-acm.patch +uboot-s3c2410_udc.patch + +# those need to be cleaned up +bbt-create-optional.patch +nand-createbbt.patch +dontask.patch +nand-badisbad.patch +uboot-bbt-quiet.patch + +# splash screen +raise-limits.patch +splashimage-command.patch +cmd-unzip.patch +enable-splash-bmp.patch + +# for automated installation +preboot-override.patch +lowlevel_foo.patch + +# move these later, once the dust has settled +default-env.patch +console-ansi.patch +boot-menu.patch + +# those have to be implemented fully +uboot-dfu.patch +uboot-neo1973-defaultenv.patch +uboot-nand-markbad-reallybad.patch +usbdcore-multiple_configs.patch +neo1973-chargefast.patch + +uboot-s3c2440.patch +uboot-smdk2440.patch +uboot-hxd8.patch + +uboot-license.patch + +uboot-gta02.patch +uboot-s3c2443.patch +uboot-smdk2443.patch + +# for review, merge soon +unbusy-i2c.patch diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/splashimage-command.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/splashimage-command.patch new file mode 100644 index 0000000000..8ea48cf484 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/splashimage-command.patch @@ -0,0 +1,24 @@ +drivers/cfb_console.c (video_logo): if "splashimage" doesn't contain an + address, use its content as a command + +- Werner Almesberger + +Index: u-boot/drivers/cfb_console.c +=================================================================== +--- u-boot.orig/drivers/cfb_console.c ++++ u-boot/drivers/cfb_console.c +@@ -1121,7 +1121,13 @@ static void *video_logo (void) + ulong addr; + + if ((s = getenv ("splashimage")) != NULL) { +- addr = simple_strtoul (s, NULL, 16); ++ char *end; ++ ++ addr = simple_strtoul (s, &end, 16); ++ if (*end) { ++ run_command(s, 0); ++ return video_fb_address; ++ } + + if (video_display_bitmap (addr, 0, 0) == 0) { + return ((void *) (video_fb_address)); diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-20061030-neo1973.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-20061030-neo1973.patch new file mode 100644 index 0000000000..7c70244b38 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-20061030-neo1973.patch @@ -0,0 +1,2248 @@ +This patch adds neo1973 'board' (FIC Neo1973 phone) support to u-boot. +Specifically, it adds support for the GTA01v3, GTA01v4, GTA01Bv2 and +GTA01Bv3 hardware revisions. + +Signed-off-by: Harald Welte + +Index: u-boot/Makefile +=================================================================== +--- u-boot.orig/Makefile ++++ u-boot/Makefile +@@ -2009,6 +2009,14 @@ + sbc2410x_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t sbc2410x NULL s3c24x0 + ++gta01_config \ ++gta01v3_config \ ++gta01bv2_config \ ++gta01bv3_config \ ++gta01bv4_config \ ++gta01v4_config : unconfig ++ @sh board/neo1973/gta01/split_by_variant.sh $@ ++ + qt2410_config : unconfig + @./mkconfig $(@:_config=) arm arm920t qt2410 NULL s3c24x0 + +Index: u-boot/common/main.c +=================================================================== +--- u-boot.orig/common/main.c ++++ u-boot/common/main.c +@@ -61,6 +61,7 @@ + #undef DEBUG_PARSER + + char console_buffer[CFG_CBSIZE]; /* console I/O buffer */ ++int nobootdelay; + + #ifndef CONFIG_CMDLINE_EDITING + static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen); +@@ -376,7 +377,7 @@ + + debug ("### main_loop: bootcmd=\"%s\"\n", s ? s : ""); + +- if (bootdelay >= 0 && s && !abortboot (bootdelay)) { ++ if (!nobootdelay && bootdelay >= 0 && s && !abortboot (bootdelay)) { + # ifdef CONFIG_AUTOBOOT_KEYED + int prev = disable_ctrlc(1); /* disable Control C checking */ + # endif +Index: u-boot/drivers/Makefile +=================================================================== +--- u-boot.orig/drivers/Makefile ++++ u-boot/drivers/Makefile +@@ -50,6 +50,7 @@ + usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \ + videomodes.o w83c553f.o \ + ks8695eth.o \ ++ pcf50606.o \ + pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \ + rpx_pcmcia.o \ + fsl_i2c.o s3c2410_fb.o +Index: u-boot/drivers/pcf50606.c +=================================================================== +--- /dev/null ++++ u-boot/drivers/pcf50606.c +@@ -0,0 +1,112 @@ ++ ++#include ++ ++#ifdef CONFIG_DRIVER_PCF50606 ++ ++#include ++#include ++#include ++#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) ++ ++#define PCF50606_I2C_ADDR 0x08 ++ ++void __pcf50606_reg_write(u_int8_t reg, u_int8_t val) ++{ ++ i2c_write(PCF50606_I2C_ADDR, reg, 1, &val, 1); ++} ++ ++u_int8_t __pcf50606_reg_read(u_int8_t reg) ++{ ++ u_int8_t tmp; ++ i2c_read(PCF50606_I2C_ADDR, reg, 1, &tmp, 1); ++ return tmp; ++} ++ ++void pcf50606_reg_write(u_int8_t reg, u_int8_t val) ++{ ++ unsigned long flags; ++ ++ local_irq_save(flags); ++ __pcf50606_reg_write(reg, val); ++ local_irq_restore(flags); ++} ++ ++u_int8_t pcf50606_reg_read(u_int8_t reg) ++{ ++ unsigned long flags; ++ u_int8_t tmp; ++ ++ local_irq_save(flags); ++ tmp = __pcf50606_reg_read(reg); ++ local_irq_restore(flags); ++ ++ return tmp; ++} ++ ++void pcf50606_reg_set_bit_mask(u_int8_t reg, u_int8_t mask, u_int8_t val) ++{ ++ unsigned long flags; ++ u_int8_t tmp; ++ ++ local_irq_save(flags); ++ tmp = __pcf50606_reg_read(reg); ++ __pcf50606_reg_write(reg, (val & mask) | (tmp & ~mask)); ++ local_irq_restore(flags); ++} ++ ++void pcf50606_reg_clear_bits(u_int8_t reg, u_int8_t bits) ++{ ++ unsigned long flags; ++ u_int8_t tmp; ++ ++ local_irq_save(flags); ++ tmp = pcf50606_reg_read(reg); ++ pcf50606_reg_write(reg, (tmp & ~bits)); ++ local_irq_restore(flags); ++} ++ ++static const u_int8_t regs_valid[] = { ++ PCF50606_REG_OOCS, PCF50606_REG_INT1M, PCF50606_REG_INT2M, ++ PCF50606_REG_INT3M, PCF50606_REG_OOCC1, PCF50606_REG_OOCC2, ++ PCF50606_REG_PSSC, PCF50606_REG_PWROKM, PCF50606_REG_DCDC1, ++ PCF50606_REG_DCDC2, PCF50606_REG_DCDC3, PCF50606_REG_DCDC4, ++ PCF50606_REG_DCDEC1, PCF50606_REG_DCDEC2, PCF50606_REG_DCUDC1, ++ PCF50606_REG_DCUDC2, PCF50606_REG_IOREGC, PCF50606_REG_D1REGC1, ++ PCF50606_REG_D2REGC1, PCF50606_REG_D3REGC1, PCF50606_REG_LPREGC1, ++ PCF50606_REG_LPREGC2, PCF50606_REG_MBCC1, PCF50606_REG_MBCC2, ++ PCF50606_REG_MBCC3, PCF50606_REG_BBCC, PCF50606_REG_ADCC1, ++ PCF50606_REG_ADCC2, PCF50606_REG_ACDC1, PCF50606_REG_BVMC, ++ PCF50606_REG_PWMC1, PCF50606_REG_LEDC1, PCF50606_REG_LEDC2, ++ PCF50606_REG_GPOC1, PCF50606_REG_GPOC2, PCF50606_REG_GPOC3, ++ PCF50606_REG_GPOC4, PCF50606_REG_GPOC5, ++}; ++ ++ ++/* initialize PCF50606 register set */ ++void pcf50606_init(void) ++{ ++ unsigned long flags; ++ int i; ++ ++ local_irq_save(flags); ++ for (i = 0; i < ARRAY_SIZE(regs_valid); i++) { ++ __pcf50606_reg_write(regs_valid[i], ++ pcf50606_initial_regs[regs_valid[i]]); ++ } ++ local_irq_restore(flags); ++} ++ ++void pcf50606_charge_autofast(int on) ++{ ++ if (on) { ++ printf("Enabling automatic fast charge\n"); ++ pcf50606_reg_set_bit_mask(PCF50606_REG_MBCC1, ++ PCF50606_MBCC1_AUTOFST, ++ PCF50606_MBCC1_AUTOFST); ++ } else { ++ printf("Disabling fast charge\n"); ++ pcf50606_reg_write(PCF50606_REG_MBCC1, 0x00); ++ } ++} ++ ++#endif /* CONFIG DRIVER_PCF50606 */ +Index: u-boot/include/pcf50606.h +=================================================================== +--- /dev/null ++++ u-boot/include/pcf50606.h +@@ -0,0 +1,273 @@ ++#ifndef _PCF50606_H ++#define _PCF50606_H ++ ++/* Philips PCF50606 Power Managemnt Unit (PMU) driver ++ * (C) 2006-2007 by OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ */ ++ ++enum pfc50606_regs { ++ PCF50606_REG_ID = 0x00, ++ PCF50606_REG_OOCS = 0x01, ++ PCF50606_REG_INT1 = 0x02, /* Interrupt Status */ ++ PCF50606_REG_INT2 = 0x03, /* Interrupt Status */ ++ PCF50606_REG_INT3 = 0x04, /* Interrupt Status */ ++ PCF50606_REG_INT1M = 0x05, /* Interrupt Mask */ ++ PCF50606_REG_INT2M = 0x06, /* Interrupt Mask */ ++ PCF50606_REG_INT3M = 0x07, /* Interrupt Mask */ ++ PCF50606_REG_OOCC1 = 0x08, ++ PCF50606_REG_OOCC2 = 0x09, ++ PCF50606_REG_RTCSC = 0x0a, /* Second */ ++ PCF50606_REG_RTCMN = 0x0b, /* Minute */ ++ PCF50606_REG_RTCHR = 0x0c, /* Hour */ ++ PCF50606_REG_RTCWD = 0x0d, /* Weekday */ ++ PCF50606_REG_RTCDT = 0x0e, /* Day */ ++ PCF50606_REG_RTCMT = 0x0f, /* Month */ ++ PCF50606_REG_RTCYR = 0x10, /* Year */ ++ PCF50606_REG_RTCSCA = 0x11, /* Alarm Second */ ++ PCF50606_REG_RTCMNA = 0x12, /* Alarm Minute */ ++ PCF50606_REG_RTCHRA = 0x13, /* Alarm Hour */ ++ PCF50606_REG_RTCWDA = 0x14, /* Alarm Weekday */ ++ PCF50606_REG_RTCDTA = 0x15, /* Alarm Day */ ++ PCF50606_REG_RTCMTA = 0x16, /* Alarm Month */ ++ PCF50606_REG_RTCYRA = 0x17, /* Alarm Year */ ++ PCF50606_REG_PSSC = 0x18, /* Power sequencing */ ++ PCF50606_REG_PWROKM = 0x19, /* PWROK mask */ ++ PCF50606_REG_PWROKS = 0x1a, /* PWROK status */ ++ PCF50606_REG_DCDC1 = 0x1b, ++ PCF50606_REG_DCDC2 = 0x1c, ++ PCF50606_REG_DCDC3 = 0x1d, ++ PCF50606_REG_DCDC4 = 0x1e, ++ PCF50606_REG_DCDEC1 = 0x1f, ++ PCF50606_REG_DCDEC2 = 0x20, ++ PCF50606_REG_DCUDC1 = 0x21, ++ PCF50606_REG_DCUDC2 = 0x22, ++ PCF50606_REG_IOREGC = 0x23, ++ PCF50606_REG_D1REGC1 = 0x24, ++ PCF50606_REG_D2REGC1 = 0x25, ++ PCF50606_REG_D3REGC1 = 0x26, ++ PCF50606_REG_LPREGC1 = 0x27, ++ PCF50606_REG_LPREGC2 = 0x28, ++ PCF50606_REG_MBCC1 = 0x29, ++ PCF50606_REG_MBCC2 = 0x2a, ++ PCF50606_REG_MBCC3 = 0x2b, ++ PCF50606_REG_MBCS1 = 0x2c, ++ PCF50606_REG_BBCC = 0x2d, ++ PCF50606_REG_ADCC1 = 0x2e, ++ PCF50606_REG_ADCC2 = 0x2f, ++ PCF50606_REG_ADCS1 = 0x30, ++ PCF50606_REG_ADCS2 = 0x31, ++ PCF50606_REG_ADCS3 = 0x32, ++ PCF50606_REG_ACDC1 = 0x33, ++ PCF50606_REG_BVMC = 0x34, ++ PCF50606_REG_PWMC1 = 0x35, ++ PCF50606_REG_LEDC1 = 0x36, ++ PCF50606_REG_LEDC2 = 0x37, ++ PCF50606_REG_GPOC1 = 0x38, ++ PCF50606_REG_GPOC2 = 0x39, ++ PCF50606_REG_GPOC3 = 0x3a, ++ PCF50606_REG_GPOC4 = 0x3b, ++ PCF50606_REG_GPOC5 = 0x3c, ++ __NUM_PCF50606_REGS ++}; ++ ++enum pcf50606_reg_oocs { ++ PFC50606_OOCS_ONKEY = 0x01, ++ PCF50606_OOCS_EXTON = 0x02, ++ PCF50606_OOCS_PWROKRST = 0x04, ++ PCF50606_OOCS_BATOK = 0x08, ++ PCF50606_OOCS_BACKOK = 0x10, ++ PCF50606_OOCS_CHGOK = 0x20, ++ PCF50606_OOCS_TEMPOK = 0x40, ++ PCF50606_OOCS_WDTEXP = 0x80, ++}; ++ ++enum pcf50606_reg_oocc1 { ++ PCF50606_OOCC1_GOSTDBY = 0x01, ++ PCF50606_OOCC1_TOTRST = 0x02, ++ PCF50606_OOCC1_CLK32ON = 0x04, ++ PCF50606_OOCC1_WDTRST = 0x08, ++ PCF50606_OOCC1_RTCWAK = 0x10, ++ PCF50606_OOCC1_CHGWAK = 0x20, ++ PCF50606_OOCC1_EXTONWAK_HIGH = 0x40, ++ PCF50606_OOCC1_EXTONWAK_LOW = 0x80, ++ PCF50606_OOCC1_EXTONWAK_NO_WAKEUP = 0x3f, ++}; ++ ++enum pcf50606_reg_oocc2 { ++ PCF50606_OOCC2_ONKEYDB_NONE = 0x00, ++ PCF50606_OOCC2_ONKEYDB_14ms = 0x01, ++ PCF50606_OOCC2_ONKEYDB_62ms = 0x02, ++ PCF50606_OOCC2_ONKEYDB_500ms = 0x03, ++ PCF50606_OOCC2_EXTONDB_NONE = 0x00, ++ PCF50606_OOCC2_EXTONDB_14ms = 0x04, ++ PCF50606_OOCC2_EXTONDB_62ms = 0x08, ++ PCF50606_OOCC2_EXTONDB_500ms = 0x0c, ++}; ++ ++enum pcf50606_reg_int1 { ++ PCF50606_INT1_ONKEYR = 0x01, /* ONKEY rising edge */ ++ PCF50606_INT1_ONKEYF = 0x02, /* ONKEY falling edge */ ++ PCF50606_INT1_ONKEY1S = 0x04, /* OMKEY at least 1sec low */ ++ PCF50606_INT1_EXTONR = 0x08, /* EXTON rising edge */ ++ PCF50606_INT1_EXTONF = 0x10, /* EXTON falling edge */ ++ PCF50606_INT1_SECOND = 0x40, /* RTC periodic second interrupt */ ++ PCF50606_INT1_ALARM = 0x80, /* RTC alarm time is reached */ ++}; ++ ++enum pcf50606_reg_int2 { ++ PCF50606_INT2_CHGINS = 0x01, /* Charger inserted */ ++ PCF50606_INT2_CHGRM = 0x02, /* Charger removed */ ++ PCF50606_INT2_CHGFOK = 0x04, /* Fast charging OK */ ++ PCF50606_INT2_CHGERR = 0x08, /* Error in charging mode */ ++ PCF50606_INT2_CHGFRDY = 0x10, /* Fast charge completed */ ++ PCF50606_INT2_CHGPROT = 0x20, /* Charging protection interrupt */ ++ PCF50606_INT2_CHGWD10S = 0x40, /* Charger watchdig expires in 10s */ ++ PCF50606_INT2_CHGWDEXP = 0x80, /* Charger watchdog expires */ ++}; ++ ++enum pcf50606_reg_int3 { ++ PCF50606_INT3_ADCRDY = 0x01, /* ADC conversion finished */ ++ PCF50606_INT3_ACDINS = 0x02, /* Accessory inserted */ ++ PCF50606_INT3_ACDREM = 0x04, /* Accessory removed */ ++ PCF50606_INT3_TSCPRES = 0x08, /* Touch screen pressed */ ++ PCF50606_INT3_LOWBAT = 0x40, /* Low battery voltage */ ++ PCF50606_INT3_HIGHTMP = 0x80, /* High temperature */ ++}; ++ ++/* used by PSSC, PWROKM, PWROKS, */ ++enum pcf50606_regu { ++ PCF50606_REGU_DCD = 0x01, /* DCD in phase 2 */ ++ PCF50606_REGU_DCDE = 0x02, /* DCDE in phase 2 */ ++ PCF50606_REGU_DCUD = 0x04, /* DCDU in phase 2 */ ++ PCF50606_REGU_IO = 0x08, /* IO in phase 2 */ ++ PCF50606_REGU_D1 = 0x10, /* D1 in phase 2 */ ++ PCF50606_REGU_D2 = 0x20, /* D2 in phase 2 */ ++ PCF50606_REGU_D3 = 0x40, /* D3 in phase 2 */ ++ PCF50606_REGU_LP = 0x80, /* LP in phase 2 */ ++}; ++ ++enum pcf50606_reg_dcdc4 { ++ PCF50606_DCDC4_MODE_AUTO = 0x00, ++ PCF50606_DCDC4_MODE_PWM = 0x01, ++ PCF50606_DCDC4_MODE_PCF = 0x02, ++ PCF50606_DCDC4_OFF_FLOAT = 0x00, ++ PCF50606_DCDC4_OFF_BYPASS = 0x04, ++ PCF50606_DCDC4_OFF_PULLDOWN = 0x08, ++ PCF50606_DCDC4_CURLIM_500mA = 0x00, ++ PCF50606_DCDC4_CURLIM_750mA = 0x10, ++ PCF50606_DCDC4_CURLIM_1000mA = 0x20, ++ PCF50606_DCDC4_CURLIM_1250mA = 0x30, ++ PCF50606_DCDC4_TOGGLE = 0x40, ++ PCF50606_DCDC4_REGSEL_DCDC2 = 0x80, ++}; ++ ++enum pcf50606_reg_dcdec2 { ++ PCF50606_DCDEC2_MODE_AUTO = 0x00, ++ PCF50606_DCDEC2_MODE_PWM = 0x01, ++ PCF50606_DCDEC2_MODE_PCF = 0x02, ++ PCF50606_DCDEC2_OFF_FLOAT = 0x00, ++ PCF50606_DCDEC2_OFF_BYPASS = 0x04, ++}; ++ ++enum pcf50606_reg_dcudc2 { ++ PCF50606_DCUDC2_MODE_AUTO = 0x00, ++ PCF50606_DCUDC2_MODE_PWM = 0x01, ++ PCF50606_DCUDC2_MODE_PCF = 0x02, ++ PCF50606_DCUDC2_OFF_FLOAT = 0x00, ++ PCF50606_DCUDC2_OFF_BYPASS = 0x04, ++}; ++ ++enum pcf50606_reg_adcc1 { ++ PCF50606_ADCC1_TSCMODACT = 0x01, ++ PCF50606_ADCC1_TSCMODSTB = 0x02, ++ PCF50606_ADCC1_TRATSET = 0x04, ++ PCF50606_ADCC1_NTCSWAPE = 0x08, ++ PCF50606_ADCC1_NTCSWAOFF = 0x10, ++ PCF50606_ADCC1_EXTSYNCBREAK = 0x20, ++ /* reserved */ ++ PCF50606_ADCC1_TSCINT = 0x80, ++}; ++ ++enum pcf50606_reg_adcc2 { ++ PCF50606_ADCC2_ADCSTART = 0x01, ++ /* see enum pcf50606_adcc2_adcmux */ ++ PCF50606_ADCC2_SYNC_NONE = 0x00, ++ PCF50606_ADCC2_SYNC_TXON = 0x20, ++ PCF50606_ADCC2_SYNC_PWREN1 = 0x40, ++ PCF50606_ADCC2_SYNC_PWREN2 = 0x60, ++ PCF50606_ADCC2_RES_10BIT = 0x00, ++ PCF50606_ADCC2_RES_8BIT = 0x80, ++}; ++ ++#define PCF50606_ADCC2_ADCMUX_MASK (0xf << 1) ++ ++#define ADCMUX_SHIFT 1 ++enum pcf50606_adcc2_adcmux { ++ PCF50606_ADCMUX_BATVOLT_RES = 0x0 << ADCMUX_SHIFT, ++ PCF50606_ADCMUX_BATVOLT_SUBTR = 0x1 << ADCMUX_SHIFT, ++ PCF50606_ADCMUX_ADCIN1_RES = 0x2 << ADCMUX_SHIFT, ++ PCF50606_ADCMUX_ADCIN1_SUBTR = 0x3 << ADCMUX_SHIFT, ++ PCF50606_ADCMUX_BATTEMP = 0x4 << ADCMUX_SHIFT, ++ PCF50606_ADCMUX_ADCIN2 = 0x5 << ADCMUX_SHIFT, ++ PCF50606_ADCMUX_ADCIN3 = 0x6 << ADCMUX_SHIFT, ++ PCF50606_ADCMUX_ADCIN3_RATIO = 0x7 << ADCMUX_SHIFT, ++ PCF50606_ADCMUX_XPOS = 0x8 << ADCMUX_SHIFT, ++ PCF50606_ADCMUX_YPOS = 0x9 << ADCMUX_SHIFT, ++ PCF50606_ADCMUX_P1 = 0xa << ADCMUX_SHIFT, ++ PCF50606_ADCMUX_P2 = 0xb << ADCMUX_SHIFT, ++ PCF50606_ADCMUX_BATVOLT_ADCIN1 = 0xc << ADCMUX_SHIFT, ++ PCF50606_ADCMUX_XY_SEQUENCE = 0xe << ADCMUX_SHIFT, ++ PCF50606_P1_P2_RESISTANCE = 0xf << ADCMUX_SHIFT, ++}; ++ ++enum pcf50606_adcs2 { ++ PCF50606_ADCS2_ADCRDY = 0x80, ++}; ++ ++enum pcf50606_reg_mbcc1 { ++ PCF50606_MBCC1_CHGAPE = 0x01, ++ PCF50606_MBCC1_AUTOFST = 0x02, ++#define PCF50606_MBCC1_CHGMOD_MASK 0x1c ++#define PCF50606_MBCC1_CHGMOD_SHIFT 2 ++ PCF50606_MBCC1_CHGMOD_QUAL = 0x00, ++ PCF50606_MBCC1_CHGMOD_PRE = 0x04, ++ PCF50606_MBCC1_CHGMOD_TRICKLE = 0x08, ++ PCF50606_MBCC1_CHGMOD_FAST_CCCV = 0x0c, ++ PCF50606_MBCC1_CHGMOD_FAST_NOCC = 0x10, ++ PCF50606_MBCC1_CHGMOD_FAST_NOCV = 0x14, ++ PCF50606_MBCC1_CHGMOD_FAST_SW = 0x18, ++ PCF50606_MBCC1_CHGMOD_IDLE = 0x1c, ++ PCF50606_MBCC1_DETMOD_LOWCHG = 0x20, ++ PCF50606_MBCC1_DETMOD_WDRST = 0x40, ++}; ++ ++enum pcf50606_reg_bvmc { ++ PCF50606_BVMC_LOWBAT = 0x01, ++ PCF50606_BVMC_THRSHLD_NULL = 0x00, ++ PCF50606_BVMC_THRSHLD_2V8 = 0x02, ++ PCF50606_BVMC_THRSHLD_2V9 = 0x04, ++ PCF50606_BVMC_THRSHLD_3V = 0x08, ++ PCF50606_BVMC_THRSHLD_3V1 = 0x08, ++ PCF50606_BVMC_THRSHLD_3V2 = 0x0a, ++ PCF50606_BVMC_THRSHLD_3V3 = 0x0c, ++ PCF50606_BVMC_THRSHLD_3V4 = 0x0e, ++ PCF50606_BVMC_DISDB = 0x10, ++}; ++ ++/* this is to be provided by the board implementation */ ++extern const u_int8_t pcf50606_initial_regs[__NUM_PCF50606_REGS]; ++ ++void pcf50606_reg_write(u_int8_t reg, u_int8_t val); ++ ++u_int8_t pcf50606_reg_read(u_int8_t reg); ++ ++void pcf50606_reg_set_bit_mask(u_int8_t reg, u_int8_t mask, u_int8_t val); ++void pcf50606_reg_clear_bits(u_int8_t reg, u_int8_t bits); ++ ++void pcf50606_init(void); ++void pcf50606_charge_autofast(int on); ++ ++#endif /* _PCF50606_H */ ++ +Index: u-boot/board/neo1973/common/cmd_neo1973.c +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/common/cmd_neo1973.c +@@ -0,0 +1,99 @@ ++/* ++ * (C) Copyright 2006 by OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* ++ * Boot support ++ */ ++#include ++#include ++#include /* for print_IPaddr */ ++#include ++ ++#include "neo1973.h" ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#if (CONFIG_COMMANDS & CFG_CMD_BDI) ++ ++int do_neo1973 ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ++{ ++ int i; ++ ++ if (!strcmp(argv[1], "info")) { ++ printf("FIC Neo1973 Hardware Revision 0x%04x\n", get_board_rev()); ++ } else if (!strcmp(argv[1], "power-off")) { ++ neo1973_poweroff(); ++ } else if (!strcmp(argv[1], "charger") || !strcmp(argv[1], "charge")) { ++ if (argc < 3) ++ goto out_help; ++ if (!strcmp(argv[2], "status") || !strcmp(argv[2], "state")) { ++ printf("%s\n", neo1973_get_charge_status()); ++ } else if (!strcmp(argv[2], "autofast")) { ++ neo1973_set_charge_mode(NEO1973_CHGCMD_AUTOFAST); ++ } else if (!strcmp(argv[2], "!autofast")) { ++ neo1973_set_charge_mode(NEO1973_CHGCMD_NO_AUTOFAST); ++ } else if (!strcmp(argv[2], "off")) { ++ neo1973_set_charge_mode(NEO1973_CHGCMD_OFF); ++ } else if (!strcmp(argv[2], "fast")) { ++ neo1973_set_charge_mode(NEO1973_CHGCMD_FAST); ++ } else ++ goto out_help; ++ } else if (!strcmp(argv[1], "backlight")) { ++ if (argc < 3) ++ goto out_help; ++ if (!strcmp(argv[2], "on")) ++ neo1973_backlight(1); ++ else ++ neo1973_backlight(0); ++ } else if (!strcmp(argv[1], "vibrator")) { ++ if (argc < 3) ++ goto out_help; ++ if (!strcmp(argv[2], "on")) ++ neo1973_vibrator(1); ++ else ++ neo1973_vibrator(0); ++ } else { ++out_help: ++ printf("Usage:\n%s\n", cmdtp->usage); ++ return 1; ++ } ++ ++ return 0; ++} ++ ++/* -------------------------------------------------------------------- */ ++ ++U_BOOT_CMD( ++ neo1973, 4, 1, do_neo1973, ++ "neo1973 - phone specific commands\n", ++ "neo1973 info - display phone informantion\n" ++ "neo1973 power-off - switch off the phone\n" ++ "neo1973 charger status - display charger status\n" ++ "neo1973 charger autofast - enable automatic fast (500mA) charging\n" ++ "neo1973 charger !autofast - disable automatic fast (500mA) charging\n" ++ "neo1973 charger fast - enable fast (500mA) charging\n" ++ "neo1973 charger off - disable charging\n" ++ "neo1973 backlight (on|off) - switch backlight on or off\n" ++ "neo1973 vibrator (on|off) - switch vibrator on or off\n" ++); ++#endif /* CFG_CMD_BDI */ +Index: u-boot/board/neo1973/common/jbt6k74.c +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/common/jbt6k74.c +@@ -0,0 +1,420 @@ ++/* u-boot driver for the tpo JBT6K74-AS LCM ASIC ++ * ++ * Copyright (C) 2006-2007 by OpenMoko, Inc. ++ * Author: Harald Welte ++ * All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include "jbt6k74.h" ++ ++#if 0 ++#define DEBUGP(x, args...) printf("%s: " x, __FUNCTION__, ## args); ++#define DEBUGPC(x, args...) printf(x, ## args); ++#else ++#define DEBUGP(x, args...) do { } while (0) ++#define DEBUGPC(x, args...) do { } while (0) ++#endif ++ ++ ++enum jbt_register { ++ JBT_REG_SLEEP_IN = 0x10, ++ JBT_REG_SLEEP_OUT = 0x11, ++ ++ JBT_REG_DISPLAY_OFF = 0x28, ++ JBT_REG_DISPLAY_ON = 0x29, ++ ++ JBT_REG_RGB_FORMAT = 0x3a, ++ JBT_REG_QUAD_RATE = 0x3b, ++ ++ JBT_REG_POWER_ON_OFF = 0xb0, ++ JBT_REG_BOOSTER_OP = 0xb1, ++ JBT_REG_BOOSTER_MODE = 0xb2, ++ JBT_REG_BOOSTER_FREQ = 0xb3, ++ JBT_REG_OPAMP_SYSCLK = 0xb4, ++ JBT_REG_VSC_VOLTAGE = 0xb5, ++ JBT_REG_VCOM_VOLTAGE = 0xb6, ++ JBT_REG_EXT_DISPL = 0xb7, ++ JBT_REG_OUTPUT_CONTROL = 0xb8, ++ JBT_REG_DCCLK_DCEV = 0xb9, ++ JBT_REG_DISPLAY_MODE1 = 0xba, ++ JBT_REG_DISPLAY_MODE2 = 0xbb, ++ JBT_REG_DISPLAY_MODE = 0xbc, ++ JBT_REG_ASW_SLEW = 0xbd, ++ JBT_REG_DUMMY_DISPLAY = 0xbe, ++ JBT_REG_DRIVE_SYSTEM = 0xbf, ++ ++ JBT_REG_SLEEP_OUT_FR_A = 0xc0, ++ JBT_REG_SLEEP_OUT_FR_B = 0xc1, ++ JBT_REG_SLEEP_OUT_FR_C = 0xc2, ++ JBT_REG_SLEEP_IN_LCCNT_D = 0xc3, ++ JBT_REG_SLEEP_IN_LCCNT_E = 0xc4, ++ JBT_REG_SLEEP_IN_LCCNT_F = 0xc5, ++ JBT_REG_SLEEP_IN_LCCNT_G = 0xc6, ++ ++ JBT_REG_GAMMA1_FINE_1 = 0xc7, ++ JBT_REG_GAMMA1_FINE_2 = 0xc8, ++ JBT_REG_GAMMA1_INCLINATION = 0xc9, ++ JBT_REG_GAMMA1_BLUE_OFFSET = 0xca, ++ ++ JBT_REG_BLANK_CONTROL = 0xcf, ++ JBT_REG_BLANK_TH_TV = 0xd0, ++ JBT_REG_CKV_ON_OFF = 0xd1, ++ JBT_REG_CKV_1_2 = 0xd2, ++ JBT_REG_OEV_TIMING = 0xd3, ++ JBT_REG_ASW_TIMING_1 = 0xd4, ++ JBT_REG_ASW_TIMING_2 = 0xd5, ++ ++ JBT_REG_HCLOCK_VGA = 0xec, ++ JBT_REG_HCLOCK_QVGA = 0xed, ++ ++}; ++ ++static const char *jbt_state_names[] = { ++ [JBT_STATE_DEEP_STANDBY] = "deep-standby", ++ [JBT_STATE_SLEEP] = "sleep", ++ [JBT_STATE_NORMAL] = "normal", ++}; ++ ++#define GTA01_SCLK (1 << 7) /* GPG7 */ ++#define GTA01_MOSI (1 << 6) /* GPG6 */ ++#define GTA01_MISO (1 << 5) /* GPG5 */ ++#define GTA01_CS (1 << 3) /* GPG3 */ ++ ++#define SPI_READ ((immr->GPGDAT & GTA01_MISO) != 0) ++ ++#define SPI_CS(bit) if (bit) gpio->GPGDAT |= GTA01_CS; \ ++ else gpio->GPGDAT &= ~GTA01_CS ++ ++#define SPI_SDA(bit) if (bit) gpio->GPGDAT |= GTA01_MOSI; \ ++ else gpio->GPGDAT &= ~GTA01_MOSI ++ ++#define SPI_SCL(bit) if (bit) gpio->GPGDAT |= GTA01_SCLK; \ ++ else gpio->GPGDAT &= ~GTA01_SCLK ++ ++/* 150uS minimum clock cycle, we have two of this plus our other ++ * instructions */ ++#define SPI_DELAY udelay(100) /* 200uS */ ++ ++ ++#define JBT_TX_BUF_SIZE ++struct jbt_info { ++ enum jbt_state state; ++ u_int16_t tx_buf[4]; ++ struct spi_device *spi_dev; ++}; ++ ++static struct jbt_info _jbt, *jbt = &_jbt; ++ ++static int jbt_spi_xfer(int wordnum, int bitlen, u_int16_t *dout) ++{ ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ u_int16_t tmpdout = 0; ++ int i, j; ++ ++ DEBUGP("spi_xfer: dout %08X wordnum %u bitlen %d\n", ++ *(uint *)dout, wordnum, bitlen); ++ ++ SPI_CS(0); ++ ++ for (i = 0; i < wordnum; i ++) { ++ tmpdout = dout[i]; ++ ++ for (j = 0; j < bitlen; j++) { ++ SPI_SCL(0); ++ if (tmpdout & (1 << bitlen-1)) { ++ SPI_SDA(1); ++ DEBUGPC("1"); ++ } else { ++ SPI_SDA(0); ++ DEBUGPC("0"); ++ } ++ SPI_DELAY; ++ SPI_SCL(1); ++ SPI_DELAY; ++ tmpdout <<= 1; ++ } ++ DEBUGPC(" "); ++ } ++ DEBUGPC("\n"); ++ ++ SPI_CS(1); ++ ++ return 0; ++} ++ ++#define JBT_COMMAND 0x000 ++#define JBT_DATA 0x100 ++ ++static int jbt_reg_write_nodata(struct jbt_info *jbt, u_int8_t reg) ++{ ++ int rc; ++ ++ jbt->tx_buf[0] = JBT_COMMAND | reg; ++ ++ rc = jbt_spi_xfer(1, 9, jbt->tx_buf); ++ ++ return rc; ++} ++ ++ ++static int jbt_reg_write(struct jbt_info *jbt, u_int8_t reg, u_int8_t data) ++{ ++ int rc; ++ ++ jbt->tx_buf[0] = JBT_COMMAND | reg; ++ jbt->tx_buf[1] = JBT_DATA | data; ++ ++ rc = jbt_spi_xfer(2, 9, jbt->tx_buf); ++ ++ return rc; ++} ++ ++static int jbt_reg_write16(struct jbt_info *jbt, u_int8_t reg, u_int16_t data) ++{ ++ int rc; ++ ++ jbt->tx_buf[0] = JBT_COMMAND | reg; ++ jbt->tx_buf[1] = JBT_DATA | (data >> 8); ++ jbt->tx_buf[2] = JBT_DATA | (data & 0xff); ++ ++ rc = jbt_spi_xfer(3, 9, jbt->tx_buf); ++ ++ return rc; ++} ++ ++static int jbt_init_regs(struct jbt_info *jbt) ++{ ++ int rc; ++ ++ DEBUGP("entering\n"); ++ ++ rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE1, 0x01); ++ rc |= jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE2, 0x00); ++ rc |= jbt_reg_write(jbt, JBT_REG_RGB_FORMAT, 0x60); ++ rc |= jbt_reg_write(jbt, JBT_REG_DRIVE_SYSTEM, 0x10); ++ rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_OP, 0x56); ++ rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_MODE, 0x33); ++ rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_FREQ, 0x11); ++ rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_FREQ, 0x11); ++ rc |= jbt_reg_write(jbt, JBT_REG_OPAMP_SYSCLK, 0x02); ++ rc |= jbt_reg_write(jbt, JBT_REG_VSC_VOLTAGE, 0x2b); ++ rc |= jbt_reg_write(jbt, JBT_REG_VCOM_VOLTAGE, 0x40); ++ rc |= jbt_reg_write(jbt, JBT_REG_EXT_DISPL, 0x03); ++ rc |= jbt_reg_write(jbt, JBT_REG_DCCLK_DCEV, 0x04); ++ rc |= jbt_reg_write(jbt, JBT_REG_ASW_SLEW, 0x02); ++ rc |= jbt_reg_write(jbt, JBT_REG_DUMMY_DISPLAY, 0x00); ++ ++ rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_A, 0x11); ++ rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_B, 0x11); ++ rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_C, 0x11); ++ rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040); ++ rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0); ++ rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020); ++ rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0); ++ ++ rc |= jbt_reg_write16(jbt, JBT_REG_GAMMA1_FINE_1, 0x5533); ++ rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_FINE_2, 0x00); ++ rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_INCLINATION, 0x00); ++ rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00); ++ rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00); ++ ++ rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_VGA, 0x1f0); ++ rc |= jbt_reg_write(jbt, JBT_REG_BLANK_CONTROL, 0x02); ++ rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV, 0x0804); ++ rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV, 0x0804); ++ ++ rc |= jbt_reg_write(jbt, JBT_REG_CKV_ON_OFF, 0x01); ++ rc |= jbt_reg_write16(jbt, JBT_REG_CKV_1_2, 0x0000); ++ ++ rc |= jbt_reg_write16(jbt, JBT_REG_OEV_TIMING, 0x0d0e); ++ rc |= jbt_reg_write16(jbt, JBT_REG_ASW_TIMING_1, 0x11a4); ++ rc |= jbt_reg_write(jbt, JBT_REG_ASW_TIMING_2, 0x0e); ++ ++#if 0 ++ rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_QVGA, 0x00ff); ++ rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_QVGA, 0x00ff); ++#endif ++ ++ return rc; ++} ++ ++static int standby_to_sleep(struct jbt_info *jbt) ++{ ++ int rc; ++ ++ DEBUGP("entering\n"); ++ ++ /* three times command zero */ ++ rc = jbt_reg_write_nodata(jbt, 0x00); ++ udelay(1000); ++ rc = jbt_reg_write_nodata(jbt, 0x00); ++ udelay(1000); ++ rc = jbt_reg_write_nodata(jbt, 0x00); ++ udelay(1000); ++ ++ /* deep standby out */ ++ rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x17); ++ ++ return rc; ++} ++ ++static int sleep_to_normal(struct jbt_info *jbt) ++{ ++ int rc; ++ DEBUGP("entering\n"); ++ ++ /* RGB I/F on, RAM wirte off, QVGA through, SIGCON enable */ ++ rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE, 0x80); ++ ++ /* Quad mode off */ ++ rc |= jbt_reg_write(jbt, JBT_REG_QUAD_RATE, 0x00); ++ ++ /* AVDD on, XVDD on */ ++ rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x16); ++ ++ /* Output control */ ++ rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0xfff9); ++ ++ /* Sleep mode off */ ++ rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_OUT); ++ ++ /* initialize register set */ ++ rc |= jbt_init_regs(jbt); ++ return rc; ++} ++ ++static int normal_to_sleep(struct jbt_info *jbt) ++{ ++ int rc; ++ DEBUGP("entering\n"); ++ ++ rc = jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_OFF); ++ rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0x8002); ++ rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_IN); ++ ++ return rc; ++} ++ ++static int sleep_to_standby(struct jbt_info *jbt) ++{ ++ DEBUGP("entering\n"); ++ return jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x00); ++} ++ ++/* frontend function */ ++int jbt6k74_enter_state(enum jbt_state new_state) ++{ ++ int rc = -EINVAL; ++ ++ DEBUGP("entering(old_state=%u, new_state=%u)\n", jbt->state, new_state); ++ ++ switch (jbt->state) { ++ case JBT_STATE_DEEP_STANDBY: ++ switch (new_state) { ++ case JBT_STATE_DEEP_STANDBY: ++ rc = 0; ++ break; ++ case JBT_STATE_SLEEP: ++ rc = standby_to_sleep(jbt); ++ break; ++ case JBT_STATE_NORMAL: ++ /* first transition into sleep */ ++ rc = standby_to_sleep(jbt); ++ /* then transition into normal */ ++ rc |= sleep_to_normal(jbt); ++ break; ++ } ++ break; ++ case JBT_STATE_SLEEP: ++ switch (new_state) { ++ case JBT_STATE_SLEEP: ++ rc = 0; ++ break; ++ case JBT_STATE_DEEP_STANDBY: ++ rc = sleep_to_standby(jbt); ++ break; ++ case JBT_STATE_NORMAL: ++ rc = sleep_to_normal(jbt); ++ break; ++ } ++ break; ++ case JBT_STATE_NORMAL: ++ switch (new_state) { ++ case JBT_STATE_NORMAL: ++ rc = 0; ++ break; ++ case JBT_STATE_DEEP_STANDBY: ++ /* first transition into sleep */ ++ rc = normal_to_sleep(jbt); ++ /* then transition into deep standby */ ++ rc |= sleep_to_standby(jbt); ++ break; ++ case JBT_STATE_SLEEP: ++ rc = normal_to_sleep(jbt); ++ break; ++ } ++ break; ++ } ++ ++ return rc; ++} ++ ++int jbt6k74_display_onoff(int on) ++{ ++ DEBUGP("entering\n"); ++ if (on) ++ return jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_ON); ++ else ++ return jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_OFF); ++} ++ ++int jbt6k74_init(void) ++{ ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ ++ /* initialize SPI for GPIO bitbang */ ++ gpio->GPGCON &= 0xffff033f; ++ gpio->GPGCON |= 0x00005440; ++ ++ /* get LCM out of reset */ ++ gpio->GPCDAT |= (1 << 6); ++ ++ /* according to data sheet: wait 50ms (Tpos of LCM). However, 50ms ++ * seems unreliable with later LCM batches, increasing to 90ms */ ++ udelay(90000); ++ ++ return 0; ++} ++ ++void board_video_init(GraphicDevice *pGD) ++{ ++ S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD(); ++ ++ lcd->LCDCON1 = 0x00000178; /* CLKVAL=1, BPPMODE=16bpp, TFT, ENVID=0 */ ++ ++ lcd->LCDCON2 = 0x019fc3c1; ++ lcd->LCDCON3 = 0x0039df67; ++ lcd->LCDCON4 = 0x00000007; ++ lcd->LCDCON5 = 0x0001cf09; ++ lcd->LPCSEL = 0x00000000; ++} +Index: u-boot/board/neo1973/common/jbt6k74.h +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/common/jbt6k74.h +@@ -0,0 +1,14 @@ ++#ifndef _JBT6K74_H ++#define _JBT6K74_H ++ ++enum jbt_state { ++ JBT_STATE_DEEP_STANDBY, ++ JBT_STATE_SLEEP, ++ JBT_STATE_NORMAL, ++}; ++ ++int jbt6k74_init(void); ++int jbt6k74_display_onoff(int on); ++int jbt6k74_enter_state(enum jbt_state new_state); ++ ++#endif +Index: u-boot/board/neo1973/common/lowlevel_init.S +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/common/lowlevel_init.S +@@ -0,0 +1,187 @@ ++/* ++ * Memory Setup stuff - taken from blob memsetup.S ++ * ++ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and ++ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) ++ * ++ * Modified for the FIC Neo1973 GTA01 by Harald Welte ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++ ++#include ++#include ++ ++ ++/* some parameters for the board */ ++ ++/* ++ * ++ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S ++ * ++ * Copyright (C) 2002 Samsung Electronics SW.LEE ++ * ++ */ ++ ++#define BWSCON 0x48000000 ++ ++/* BWSCON */ ++#define DW8 (0x0) ++#define DW16 (0x1) ++#define DW32 (0x2) ++#define WAIT (0x1<<2) ++#define UBLB (0x1<<3) ++ ++#define B1_BWSCON (DW32) ++#define B2_BWSCON (DW16) ++#define B3_BWSCON (DW16 + WAIT + UBLB) ++#define B4_BWSCON (DW16) ++#define B5_BWSCON (DW16) ++#define B6_BWSCON (DW32) ++#define B7_BWSCON (DW32) ++ ++/* BANK0CON */ ++#define B0_Tacs 0x0 /* 0clk */ ++#define B0_Tcos 0x0 /* 0clk */ ++#define B0_Tacc 0x7 /* 14clk */ ++#define B0_Tcoh 0x0 /* 0clk */ ++#define B0_Tah 0x0 /* 0clk */ ++#define B0_Tacp 0x0 ++#define B0_PMC 0x0 /* normal */ ++ ++/* BANK1CON */ ++#define B1_Tacs 0x0 /* 0clk */ ++#define B1_Tcos 0x0 /* 0clk */ ++#define B1_Tacc 0x7 /* 14clk */ ++#define B1_Tcoh 0x0 /* 0clk */ ++#define B1_Tah 0x0 /* 0clk */ ++#define B1_Tacp 0x0 ++#define B1_PMC 0x0 ++ ++#define B2_Tacs 0x0 ++#define B2_Tcos 0x0 ++#define B2_Tacc 0x7 ++#define B2_Tcoh 0x0 ++#define B2_Tah 0x0 ++#define B2_Tacp 0x0 ++#define B2_PMC 0x0 ++ ++#define B3_Tacs 0x0 /* 0clk */ ++#define B3_Tcos 0x3 /* 4clk */ ++#define B3_Tacc 0x7 /* 14clk */ ++#define B3_Tcoh 0x1 /* 1clk */ ++#define B3_Tah 0x0 /* 0clk */ ++#define B3_Tacp 0x3 /* 6clk */ ++#define B3_PMC 0x0 /* normal */ ++ ++#define B4_Tacs 0x0 /* 0clk */ ++#define B4_Tcos 0x0 /* 0clk */ ++#define B4_Tacc 0x7 /* 14clk */ ++#define B4_Tcoh 0x0 /* 0clk */ ++#define B4_Tah 0x0 /* 0clk */ ++#define B4_Tacp 0x0 ++#define B4_PMC 0x0 /* normal */ ++ ++#define B5_Tacs 0x0 /* 0clk */ ++#define B5_Tcos 0x0 /* 0clk */ ++#define B5_Tacc 0x7 /* 14clk */ ++#define B5_Tcoh 0x0 /* 0clk */ ++#define B5_Tah 0x0 /* 0clk */ ++#define B5_Tacp 0x0 ++#define B5_PMC 0x0 /* normal */ ++ ++#define B6_MT 0x3 /* SDRAM */ ++#define B6_Trcd 0x1 /* 3clk */ ++#if defined (CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4) ++#define B6_SCAN 0x1 /* 9bit */ ++#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3) || \ ++ defined(CONFIG_ARCH_GTA01B_v4) ++#define B6_SCAN 0x2 /* 10bit */ ++#endif ++ ++#define B7_MT 0x3 /* SDRAM */ ++#define B7_Trcd 0x1 /* 3clk */ ++#define B7_SCAN 0x2 /* 10bit */ ++ ++/* REFRESH parameter */ ++#define REFEN 0x1 /* Refresh enable */ ++#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ ++#define Trp 0x1 /* 3clk */ ++#define Trc 0x3 /* 7clk */ ++#define Tchr 0x2 /* 3clk */ ++//#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ ++#define REFCNT 997 /* period=17.5us, HCLK=60Mhz, (2048+1-15.6*60) */ ++/**************************************/ ++ ++_TEXT_BASE: ++ .word TEXT_BASE ++ ++.globl lowlevel_init ++lowlevel_init: ++ /* memory control configuration */ ++ /* make r0 relative the current location so that it */ ++ /* reads SMRDATA out of FLASH rather than memory ! */ ++ adr r0, SMRDATA ++ ldr r1, =BWSCON /* Bus Width Status Controller */ ++ add r2, r0, #13*4 ++0: ++ ldr r3, [r0], #4 ++ str r3, [r1], #4 ++ cmp r2, r0 ++ bne 0b ++ ++ /* setup asynchronous bus mode */ ++ mrc p15, 0, r1 ,c1 ,c0, 0 ++ orr r1, r1, #0xc0000000 ++ mcr p15, 0, r1, c1, c0, 0 ++ ++#if defined(CONFIG_ARCH_GTA01_v4) || defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3) ++ /* switch on power for NAND */ ++ ldr r0, =0x56000010 /* GPBCON */ ++ ldr r1, [r0] ++ orr r1, r1, #0x10 ++ str r1, [r0] ++ ++ ldr r0, =0x56000014 /* GPBDAT */ ++ ldr r1, [r0] ++ orr r1, r1, #(1 <<2) ++ str r1, [r0] ++#endif ++ ++ /* everything is fine now */ ++ mov pc, lr ++ ++ .ltorg ++/* the literal pools origin */ ++ ++SMRDATA: ++ .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) ++ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ++ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ++ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ++ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ++ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ++ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ++ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ++ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ++ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) ++ .word 0xb2 ++ .word 0x30 ++ .word 0x30 +Index: u-boot/board/neo1973/gta01/Makefile +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/gta01/Makefile +@@ -0,0 +1,47 @@ ++# ++# (C) Copyright 2000, 2001, 2002 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = lib$(BOARD).a ++ ++OBJS := gta01.o pcf50606.o ../common/cmd_neo1973.o ../common/jbt6k74.o ++SOBJS := ../common/lowlevel_init.o ++ ++$(LIB): $(OBJS) $(SOBJS) ++ $(AR) crv $@ $(OBJS) $(SOBJS) ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak .depend ++ ++######################################################################### ++ ++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) ++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ ++ ++-include .depend ++ ++######################################################################### +Index: u-boot/board/neo1973/gta01/config.mk +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/gta01/config.mk +@@ -0,0 +1,34 @@ ++# ++# (C) Copyright 2002 ++# Gary Jennejohn, DENX Software Engineering, ++# David Mueller, ELSOFT AG, ++# ++# FIC Neo1973 GTA01 board with S3C2410X (ARM920T) cpu ++# ++# see http://www.samsung.com/ for more information on SAMSUNG ++# ++ ++# GTA01v3 has 1 bank of 64 MB SDRAM ++# GTA01v4 has 1 bank of 64 MB SDRAM ++# ++# 3000'0000 to 3400'0000 ++# we load ourself to 33F8'0000 ++# ++# GTA01Bv2 or later has 1 bank of 128 MB SDRAM ++# ++# 3000'0000 to 3800'0000 ++# we load ourself to 37F8'0000 ++# ++# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 ++# optionally with a ramdisk at 3080'0000 ++# ++# download area is 3200'0000 or 3300'0000 ++ ++sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp ++ ++ifeq ($(GTA01_BIG_RAM),y) ++# FIXME: TEXT_BASE = 0x37F80000 ++TEXT_BASE = 0x33F80000 ++else ++TEXT_BASE = 0x33F80000 ++endif +Index: u-boot/board/neo1973/gta01/gta01.c +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/gta01/gta01.c +@@ -0,0 +1,422 @@ ++/* ++ * (C) 2006 by OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * based on existing S3C2410 startup code in u-boot: ++ * ++ * (C) Copyright 2002 ++ * Sysgo Real-Time Solutions, GmbH ++ * Marius Groeger ++ * ++ * (C) Copyright 2002 ++ * David Mueller, ELSOFT AG, ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++ ++#include "pcf50606.h" ++ ++#include "../common/neo1973.h" ++#include "../common/jbt6k74.h" ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++/* That many seconds the power key needs to be pressed to power up */ ++#define POWER_KEY_SECONDS 2 ++ ++#if defined(CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4) ++//#define M_MDIV 0xA1 /* Fout = 202.8MHz */ ++//#define M_PDIV 0x3 ++//#define M_SDIV 0x1 ++#define M_MDIV 0x90 /* Fout = 202.8MHz */ ++#define M_PDIV 0x7 ++#define M_SDIV 0x0 ++#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3) ++/* In case the debug board is attached, we cannot go beyond 200 MHz */ ++#if 0 ++#define M_MDIV 0x7d /* Fout = 266MHz */ ++#define M_PDIV 0x1 ++#define M_SDIV 0x1 ++#else ++#define M_MDIV 0x90 /* Fout = 202.8MHz */ ++#define M_PDIV 0x7 ++#define M_SDIV 0x0 ++#endif ++#elif defined(CONFIG_ARCH_GTA01B_v4) ++/* This board doesn't have bus lines at teh debug port, and we can go to 266 */ ++#define M_MDIV 0x7d /* Fout = 266MHz */ ++#define M_PDIV 0x1 ++#define M_SDIV 0x1 ++#else ++#error Please define GTA01 revision ++#endif ++ ++#define U_M_MDIV 0x78 ++#define U_M_PDIV 0x2 ++#define U_M_SDIV 0x3 ++ ++unsigned int neo1973_wakeup_cause; ++extern int nobootdelay; ++ ++static inline void delay (unsigned long loops) ++{ ++ __asm__ volatile ("1:\n" ++ "subs %0, %1, #1\n" ++ "bne 1b":"=r" (loops):"0" (loops)); ++} ++ ++/* ++ * Miscellaneous platform dependent initialisations ++ */ ++ ++int board_init (void) ++{ ++ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ ++ /* to reduce PLL lock time, adjust the LOCKTIME register */ ++ clk_power->LOCKTIME = 0xFFFFFF; ++ ++ /* configure MPLL */ ++ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); ++ ++ /* some delay between MPLL and UPLL */ ++ delay (4000); ++ ++ /* configure UPLL */ ++ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); ++ ++ /* some delay between MPLL and UPLL */ ++ delay (8000); ++ ++ /* set up the I/O ports */ ++#if defined(CONFIG_ARCH_GTA01_v3) ++ gpio->GPACON = 0x007FFFFF; ++ ++ gpio->GPBCON = 0x00005055; ++ gpio->GPBUP = 0x000007FF; ++ ++ gpio->GPCCON = 0xAAAA12A8; ++ gpio->GPCUP = 0x0000FFFF; ++ ++ gpio->GPDCON = 0xAAAAAAAA; ++ gpio->GPDUP = 0x0000FFFF; ++ ++ gpio->GPECON = 0xAAAAAAAA; ++ gpio->GPEUP = 0x0000FFFF; ++ ++ gpio->GPFCON = 0x00002AA9; ++ gpio->GPFUP = 0x000000FF; ++ ++ gpio->GPGCON = 0xA846F0C0; ++ gpio->GPGUP = 0x0000AFEF; ++ ++ gpio->GPHCON = 0x0008FAAA; ++ gpio->GPHUP = 0x000007FF; ++#elif defined(CONFIG_ARCH_GTA01_v4) ++ gpio->GPACON = 0x005E47FF; ++ ++ gpio->GPBCON = 0x00045015; ++ gpio->GPBUP = 0x000007FF; ++ gpio->GPBDAT |= 0x4; /* Set GPB2 to high (Flash power-up) */ ++ ++ gpio->GPCCON = 0xAAAA12A9; ++ gpio->GPCUP = 0x0000FFFF; ++ ++ gpio->GPDCON = 0xAAAAAAAA; ++ gpio->GPDUP = 0x0000FFFF; ++ ++ gpio->GPECON = 0xA02AAAAA; ++ gpio->GPEUP = 0x0000FFFF; ++ ++ gpio->GPFCON = 0x0000aa09; ++ gpio->GPFUP = 0x000000FF; ++ ++ gpio->GPGCON = 0xFF40F0C1; ++ gpio->GPGUP = 0x0000AFEF; ++ ++ gpio->GPHCON = 0x0000FAAA; ++ gpio->GPHUP = 0x000007FF; ++#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3) ++ gpio->GPACON = 0x005E4FFF; ++ ++ gpio->GPBCON = 0x00145415; ++ gpio->GPBUP = 0x000007FF; ++ gpio->GPBDAT |= 0x4; /* Set GPB2 to high (Flash power-up) */ ++ ++ gpio->GPCCON = 0xAAAA12A9; ++ gpio->GPCUP = 0x0000FFFF; ++ ++ gpio->GPDCON = 0xAAAAAAAA; ++ gpio->GPDUP = 0x0000FFFF; ++ ++ gpio->GPECON = 0xA02AAAAA; ++ gpio->GPEUP = 0x0000FFFF; ++ ++ gpio->GPFCON = 0x0000aa19; ++ gpio->GPFUP = 0x000000FF; ++ gpio->GPFDAT |= 0x4; /* Set GBF2 to high (nGSM_EN) */ ++ ++ gpio->GPGCON = 0xFF40F0C1; ++ gpio->GPGUP = 0x0000AFEF; ++ ++ gpio->GPHCON = 0x0000FAAA; ++ gpio->GPHUP = 0x000007FF; ++#elif defined(CONFIG_ARCH_GTA01B_v4) ++ gpio->GPACON = 0x0005E0FFF; ++ gpio->GPADAT |= (1 << 16); /* Set GPA16 to high (nNAND_WP) */ ++ ++ gpio->GPBCON = 0x00045455; ++ gpio->GPBUP = 0x000007FF; ++ gpio->GPBDAT |= 0x4; /* Set GPB2 to high (SD power down) */ ++ ++ gpio->GPCCON = 0xAAAA12A9; ++ gpio->GPCUP = 0x0000FFFF; ++ ++ gpio->GPDCON = 0xAAAAAAAA; ++ gpio->GPDUP = 0x0000FFFF; ++ ++ gpio->GPECON = 0xAAAAAAAA; ++ gpio->GPEUP = 0x0000FFFF; ++ ++ gpio->GPFCON = 0x0000aa99; ++ gpio->GPFUP = 0x000000FF; ++ gpio->GPFDAT |= 0x4; /* Set GBF2 to high (nGSM_EN) */ ++ ++ gpio->GPGCON = 0xFF14F0F8; ++ gpio->GPGUP = 0x0000AFEF; ++ ++ gpio->GPHCON = 0x0000FAAA; ++ gpio->GPHUP = 0x000007FF; ++#else ++#error Please define GTA01 version ++#endif ++ ++ /* arch number of SMDK2410-Board */ ++ gd->bd->bi_arch_number = MACH_TYPE_NEO1973_GTA01; ++ ++ /* adress of boot parameters */ ++ gd->bd->bi_boot_params = 0x30000100; ++ ++ icache_enable(); ++ dcache_enable(); ++ ++ return 0; ++} ++ ++int board_late_init(void) ++{ ++ unsigned char tmp; ++ char buf[32]; ++ ++ /* Initialize the Power Management Unit with a safe register set */ ++ pcf50606_init(); ++ ++ /* obtain wake-up reason, save INT1 in environment */ ++ tmp = pcf50606_reg_read(PCF50606_REG_INT1); ++ sprintf(buf, "0x%02x", tmp); ++ setenv("pcf50606_int1", buf); ++ ++ if (tmp & PCF50606_INT1_ALARM) { ++ /* we've been woken up by RTC alarm or charger insert, boot */ ++ neo1973_wakeup_cause = NEO1973_WAKEUP_ALARM; ++ goto continue_boot; ++ } ++ if (tmp & PCF50606_INT1_EXTONR) { ++ neo1973_wakeup_cause = NEO1973_WAKEUP_CHARGER; ++ } ++ ++ if (tmp & PCF50606_INT1_ONKEYF) { ++ int seconds = 0; ++ neo1973_wakeup_cause = NEO1973_WAKEUP_POWER_KEY; ++ /* we've been woken up by a falling edge of the onkey */ ++ ++ /* we can't just setenv(bootdelay,-1) because that would ++ * accidentially become permanent if the user does saveenv */ ++ if (neo1973_911_key_pressed()) ++ nobootdelay = 1; ++ ++ while (1) { ++ u_int8_t int1, oocs; ++ ++ oocs = pcf50606_reg_read(PCF50606_REG_OOCS); ++ if (oocs & PFC50606_OOCS_ONKEY) ++ break; ++ ++ int1 = pcf50606_reg_read(PCF50606_REG_INT1); ++ if (int1 & PCF50606_INT1_SECOND) ++ seconds++; ++ ++ if (seconds >= POWER_KEY_SECONDS) ++ goto continue_boot; ++ } ++ /* Power off if minimum number of seconds not reached */ ++ neo1973_poweroff(); ++ } ++ ++ /* if there's no other reason, must be regular reset */ ++ neo1973_wakeup_cause = NEO1973_WAKEUP_RESET; ++ ++continue_boot: ++ jbt6k74_init(); ++ jbt6k74_enter_state(JBT_STATE_NORMAL); ++ jbt6k74_display_onoff(1); ++ ++ /* issue a short pulse with the vibrator */ ++ neo1973_vibrator(1); ++ udelay(50000); ++ neo1973_vibrator(0); ++ ++ /* switch on the backlight */ ++ neo1973_backlight(1); ++ ++#if defined(CONFIG_ARCH_GTA01B_v4) ++ { ++ /* check if sd card is inserted, and power-up if it is */ ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ if (!(gpio->GPFDAT & (1 << 5))) ++ gpio->GPBDAT &= ~(1 << 2); ++ } ++#endif ++ ++ return 0; ++} ++ ++int dram_init (void) ++{ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; ++ ++ return 0; ++} ++ ++u_int32_t get_board_rev(void) ++{ ++#if defined(CONFIG_ARCH_GTA01_v3) ++ return 0x00000130; ++#elif defined(CONFIG_ARCH_GTA01_v4) ++ return 0x00000140; ++#elif defined(CONFIG_ARCH_GTA01B_v2) ++ return 0x00000220; ++#elif defined(CONFIG_ARCH_GTA01B_v3) ++ return 0x00000230; ++#elif defined(CONFIG_ARCH_GTA01B_v4) ++ return 0x00000240; ++#endif ++} ++ ++void neo1973_poweroff(void) ++{ ++ serial_printf("poweroff\n"); ++ udc_disconnect(); ++ pcf50606_reg_write(PCF50606_REG_OOCC1, PCF50606_OOCC1_GOSTDBY); ++ /* don't return to caller */ ++ while (1) ; ++} ++ ++void neo1973_backlight(int on) ++{ ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ if (on) ++ gpio->GPBDAT |= 0x01; ++ else ++ gpio->GPBDAT &= ~0x01; ++} ++ ++void neo1973_vibrator(int on) ++{ ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ if (on) ++#if defined(CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4) ++ gpio->GPGDAT |= (1 << 11); /* GPG11 */ ++#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3) ++ gpio->GPBDAT |= (1 << 10); /* GPB10 */ ++#elif defined(CONFIG_ARCH_GTA01B_v4) ++ gpio->GPBDAT |= (1 << 3); /* GPB3 */ ++#endif ++ else ++#if defined(CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4) ++ gpio->GPGDAT &= ~(1 << 11); /* GPG11 */ ++#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3) ++ gpio->GPBDAT &= ~(1 << 10); /* GPB10 */ ++#elif defined(CONFIG_ARCH_GTA01B_v4) ++ gpio->GPBDAT &= ~(1 << 3); /* GPB3 */ ++#endif ++} ++ ++int neo1973_911_key_pressed(void) ++{ ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ if (gpio->GPFDAT & (1 << 6)) ++ return 0; ++ return 1; ++} ++ ++static const char *chgstate_names[] = { ++ [PCF50606_MBCC1_CHGMOD_QUAL] = "qualification", ++ [PCF50606_MBCC1_CHGMOD_PRE] = "pre", ++ [PCF50606_MBCC1_CHGMOD_TRICKLE] = "trickle", ++ [PCF50606_MBCC1_CHGMOD_FAST_CCCV] = "fast_cccv", ++ [PCF50606_MBCC1_CHGMOD_FAST_NOCC] = "fast_nocc", ++ [PCF50606_MBCC1_CHGMOD_FAST_NOCV] = "fast_nocv", ++ [PCF50606_MBCC1_CHGMOD_FAST_SW] = "fast_switch", ++ [PCF50606_MBCC1_CHGMOD_IDLE] = "idle", ++}; ++ ++const char *neo1973_get_charge_status(void) ++{ ++ u_int8_t mbcc1 = pcf50606_reg_read(PCF50606_REG_MBCC1); ++ u_int8_t chgmod = (mbcc1 & PCF50606_MBCC1_CHGMOD_MASK); ++ return chgstate_names[chgmod]; ++} ++ ++int neo1973_set_charge_mode(enum neo1973_charger_cmd cmd) ++{ ++ switch (cmd) { ++ case NEO1973_CHGCMD_NONE: ++ break; ++ case NEO1973_CHGCMD_AUTOFAST: ++ pcf50606_reg_set_bit_mask(PCF50606_REG_MBCC1, ++ PCF50606_MBCC1_AUTOFST, ++ PCF50606_MBCC1_AUTOFST); ++ break; ++ case NEO1973_CHGCMD_NO_AUTOFAST: ++ pcf50606_reg_set_bit_mask(PCF50606_REG_MBCC1, ++ PCF50606_MBCC1_AUTOFST, 0); ++ break; ++ case NEO1973_CHGCMD_OFF: ++ pcf50606_reg_set_bit_mask(PCF50606_REG_MBCC1, ++ PCF50606_MBCC1_CHGMOD_MASK, ++ PCF50606_MBCC1_CHGMOD_IDLE); ++ break; ++ ++ case NEO1973_CHGCMD_FAST: ++ case NEO1973_CHGCMD_FASTER: ++ pcf50606_reg_set_bit_mask(PCF50606_REG_MBCC1, ++ PCF50606_MBCC1_CHGMOD_MASK, ++ PCF50606_MBCC1_CHGMOD_FAST_CCCV); ++ break; ++ } ++ return 0; ++} ++ +Index: u-boot/board/neo1973/gta01/pcf50606.c +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/gta01/pcf50606.c +@@ -0,0 +1,100 @@ ++ ++#include ++#include ++ ++/* initial register set for PCF50606 in Neo1973 devices */ ++const u_int8_t pcf50606_initial_regs[__NUM_PCF50606_REGS] = { ++ [PCF50606_REG_OOCS] = 0x00, ++ /* gap */ ++ [PCF50606_REG_INT1M] = PCF50606_INT1_SECOND, ++ [PCF50606_REG_INT2M] = 0x00, ++ [PCF50606_REG_INT3M] = PCF50606_INT3_TSCPRES, ++ [PCF50606_REG_OOCC1] = PCF50606_OOCC1_RTCWAK | ++ PCF50606_OOCC1_CHGWAK | ++ PCF50606_OOCC1_EXTONWAK_HIGH, ++ [PCF50606_REG_OOCC2] = PCF50606_OOCC2_ONKEYDB_14ms | ++ PCF50606_OOCC2_EXTONDB_14ms, ++ /* gap */ ++ [PCF50606_REG_PSSC] = 0x00, ++ [PCF50606_REG_PWROKM] = 0x00, ++ /* gap */ ++#if defined(CONFIG_ARCH_GTA01B_v2) ++ [PCF50606_REG_DCDC1] = 0x1e, /* GL_3V3: off */ ++#elif defined(CONFIG_ARCH_GTA01B_v3) || defined(CONFIG_ARCH_GTA01B_v4) ++ [PCF50606_REG_DCDC1] = 0x18, /* GL_1V5: off */ ++#endif ++ [PCF50606_REG_DCDC2] = 0x00, ++ [PCF50606_REG_DCDC3] = 0x00, ++ [PCF50606_REG_DCDC4] = 0x30, /* 1.25A */ ++ ++ [PCF50606_REG_DCDEC1] = 0xe8, /* IO_3V3: on */ ++ [PCF50606_REG_DCDEC2] = 0x00, ++ ++#if defined(CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4) ++ [PCF50606_REG_DCUDC1] = 0xe3, /* CORE_1V8: 1.8V */ ++#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3) ++ [PCF50606_REG_DCUDC1] = 0xe4, /* CORE_1V8: 2.1V */ ++#elif defined(CONFIG_ARCH_GTA01B_v4) ++ [PCF50606_REG_DCUDC1] = 0xc4, /* CORE_1V8: 2.1V if PWREN2 = HIGH */ ++#endif ++ [PCF50606_REG_DCUDC2] = 0x30, /* 1.25A current limit */ ++ ++#if defined(CONFIG_ARCH_GTA01_v3) ++ [PCF50606_REG_IOREGC] = 0x13, /* VTCXO_2V8: off */ ++#elif defined(CONFIG_ARCH_GTA01_v4) || defined(CONFIG_ARCH_GTA01B_v2) || \ ++ defined(CONFIG_ARCH_GTA01B_v3) || defined(CONFIG_ARCH_GTA01B_v4) ++ //see internal bug 94 [PCF50606_REG_IOREGC] = 0x18, /* CODEC_3V3: off */ ++ [PCF50606_REG_IOREGC] = 0xf8, /* CODEC_3V3: on */ ++#endif ++ ++#if defined(CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4) ++ [PCF50606_REG_D1REGC1] = 0x15, /* VRF_3V: off */ ++#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3) || \ ++ defined(CONFIG_ARCH_GTA01B_v4) ++ [PCF50606_REG_D1REGC1] = 0x16, /* BT_3V15: off */ ++#endif ++ ++#if defined(CONFIG_ARCH_GTA01_v3) ++ [PCF50606_REG_D2REGC1] = 0xf8, /* SD_3V3: on */ ++#elif defined(CONFIG_ARCH_GTA01_v4) || defined(CONFIG_ARCH_GTA01B_v2) || \ ++ defined(CONFIG_ARCH_GTA01B_v3) || defined(CONFIG_ARCH_GTA01B_v4) ++ [PCF50606_REG_D2REGC1] = 0x10, /* GL_2V5: off */ ++#endif ++ ++#if defined(CONFIG_ARCH_GTA01_v3) ++ [PCF50606_REG_D3REGC1] = 0x18, /* CODEC_3V3: off */ ++#elif defined(CONFIG_ARCH_GTA01_v4) ++ [PCF50606_REG_D3REGC1] = 0x13, /* VTXCO_2V8: off */ ++#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3) ++ [PCF50606_REG_D3REGC1] = 0x00, /* USER1: off */ ++#elif defined(CONFIG_ARCH_GTA01B_v4) ++ [PCF50606_REG_D3REGC1] = 0xec, /* STBY_1V8: 2.1V */ ++#endif ++ ++ [PCF50606_REG_LPREGC1] = 0xf8, /* LCM_3V3: on */ ++ [PCF50606_REG_LPREGC2] = 0x00, ++ ++ [PCF50606_REG_MBCC1] = 0x01, /* CHGAPE */ ++ [PCF50606_REG_MBCC2] = 0x00, /* unlimited charging */ ++ [PCF50606_REG_MBCC3] = 0x1a, /* 0.2*Ifast, 4.20V */ ++ [PCF50606_REG_BBCC] = 0x1f, /* 400uA */ ++ [PCF50606_REG_ADCC1] = 0x00, ++ [PCF50606_REG_ADCC2] = 0x00, ++ /* gap */ ++#if defined(CONFIG_ARCH_GTA01B_v4) ++ [PCF50606_REG_ACDC1] = 0x86, /* ACD thresh 1.6V, enabled */ ++#else ++ [PCF50606_REG_ACDC1] = 0x00, ++#endif ++ [PCF50606_REG_BVMC] = PCF50606_BVMC_THRSHLD_3V3, ++ [PCF50606_REG_PWMC1] = 0x00, ++ [PCF50606_REG_LEDC1] = 0x00, ++ [PCF50606_REG_LEDC2] = 0x00, ++ [PCF50606_REG_GPOC1] = 0x00, ++ [PCF50606_REG_GPOC2] = 0x00, ++ [PCF50606_REG_GPOC3] = 0x00, ++ [PCF50606_REG_GPOC4] = 0x00, ++ [PCF50606_REG_GPOC5] = 0x00, ++}; ++ ++ +Index: u-boot/board/neo1973/gta01/split_by_variant.sh +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/gta01/split_by_variant.sh +@@ -0,0 +1,57 @@ ++#!/bin/sh ++# --------------------------------------------------------- ++# Set the core module defines according to Core Module ++# --------------------------------------------------------- ++# --------------------------------------------------------- ++# Set up the GTA01 type define ++# --------------------------------------------------------- ++ ++CFGINC=${obj}include/config.h ++CFGTMP=${obj}board/neo1973/gta01/config.tmp ++ ++mkdir -p ${obj}include ++if [ "$1" == "" ] ++then ++ echo "$0:: No parameters - using GTA01Bv3 config" ++ echo "#define CONFIG_ARCH_GTA01B_v3" > $CFGINC ++ echo "GTA01_BIG_RAM=y" > $CFGTMP ++else ++ case "$1" in ++ gta01v4_config) ++ echo "#define CONFIG_ARCH_GTA01_v4" > $CFGINC ++ echo "GTA01_BIG_RAM=n" > $CFGTMP ++ ;; ++ ++ gta01v3_config) ++ echo "#define CONFIG_ARCH_GTA01_v3" > $CFGINC ++ echo "GTA01_BIG_RAM=n" > $CFGTMP ++ ;; ++ ++ gta01bv2_config) ++ echo "#define CONFIG_ARCH_GTA01B_v2" > $CFGINC ++ echo "GTA01_BIG_RAM=y" > $CFGTMP ++ ;; ++ ++ gta01bv3_config) ++ echo "#define CONFIG_ARCH_GTA01B_v3" > $CFGINC ++ echo "GTA01_BIG_RAM=y" > $CFGTMP ++ ;; ++ ++ gta01bv4_config) ++ echo "#define CONFIG_ARCH_GTA01B_v4" > $CFGINC ++ echo "GTA01_BIG_RAM=y" > $CFGTMP ++ ;; ++ ++ *) ++ echo "$0:: Unrecognised config - using GTA01Bv4 config" ++ echo "#define CONFIG_ARCH_GTA01B_v4" > $CFGINC ++ echo "GTA01_BIG_RAM=y" > $CFGTMP ++ ;; ++ ++ esac ++ ++fi ++# --------------------------------------------------------- ++# Complete the configuration ++# --------------------------------------------------------- ++$MKCONFIG -a neo1973_gta01 arm arm920t gta01 neo1973 s3c24x0 +Index: u-boot/board/neo1973/gta01/u-boot.lds +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/gta01/u-boot.lds +@@ -0,0 +1,58 @@ ++/* ++ * (C) Copyright 2002 ++ * Gary Jennejohn, DENX Software Engineering, ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ ++OUTPUT_ARCH(arm) ++ENTRY(_start) ++SECTIONS ++{ ++ . = 0x00000000; ++ ++ . = ALIGN(4); ++ .text : ++ { ++ cpu/arm920t/start.o (.text) ++ cpu/arm920t/s3c24x0/nand_read.o (.text) ++ *(.text) ++ } ++ ++ . = ALIGN(4); ++ .rodata : { *(.rodata) } ++ ++ . = ALIGN(4); ++ .data : { *(.data) } ++ ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ . = .; ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss : { *(.bss) } ++ _end = .; ++} +Index: u-boot/include/configs/neo1973_gta01.h +=================================================================== +--- /dev/null ++++ u-boot/include/configs/neo1973_gta01.h +@@ -0,0 +1,265 @@ ++/* ++ * (C) Copyright 2006 OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * Configuation settings for the FIC Neo1973 GTA01 Linux GSM phone ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#if defined(BUILD_FOR_RAM) ++/* If we want to start u-boot from inside RAM */ ++#define CONFIG_SKIP_RELOCATE_UBOOT 1 ++#define CONFIG_SKIP_LOWLEVEL_INIT 1 ++#else ++/* we want to start u-boot directly from within NAND flash */ ++#define CONFIG_S3C2410_NAND_BOOT 1 ++#define CONFIG_S3C2410_NAND_SKIP_BAD 1 ++#endif ++ ++#define CFG_UBOOT_SIZE 0x40000 /* size of u-boot, for NAND loading */ ++ ++/* ++ * High Level Configuration Options ++ * (easy to change) ++ */ ++#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ ++#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ ++#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */ ++ ++/* input clock of PLL */ ++#define CONFIG_SYS_CLK_FREQ 12000000/* the GTA01 has 12MHz input clock */ ++ ++ ++#define USE_920T_MMU 1 ++#define CONFIG_USE_IRQ 1 ++ ++/* ++ * Size of malloc() pool ++ */ ++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) ++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ ++ ++/* ++ * Hardware drivers ++ */ ++ ++/* ++ * select serial console configuration ++ */ ++#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on GTA01 */ ++ ++/************************************************************ ++ * RTC ++ ************************************************************/ ++#define CONFIG_RTC_S3C24X0 1 ++ ++/* allow to overwrite serial and ethaddr */ ++#define CONFIG_ENV_OVERWRITE ++ ++#define CONFIG_BAUDRATE 115200 ++ ++/*********************************************************** ++ * Command definition ++ ***********************************************************/ ++#define CONFIG_COMMANDS (\ ++ CFG_CMD_BDI | \ ++ CFG_CMD_LOADS | \ ++ CFG_CMD_LAODB | \ ++ CFG_CMD_IMI | \ ++ CFG_CMD_CACHE | \ ++ CFG_CMD_MEMORY | \ ++ CFG_CMD_ENV | \ ++ /* CFG_CMD_IRQ | */ \ ++ CFG_CMD_BOOTD | \ ++ CFG_CMD_CONSOLE | \ ++ CFG_CMD_ASKENV | \ ++ CFG_CMD_RUN | \ ++ CFG_CMD_ECHO | \ ++ CFG_CMD_I2C | \ ++ CFG_CMD_REGINFO | \ ++ CFG_CMD_IMMAP | \ ++ CFG_CMD_DATE | \ ++ CFG_CMD_AUTOSCRIPT | \ ++ CFG_CMD_BSP | \ ++ CFG_CMD_ELF | \ ++ CFG_CMD_MISC | \ ++ /* CFG_CMD_USB | */ \ ++ /* CFG_CMD_JFFS2 | */ \ ++ CFG_CMD_DIAG | \ ++ /* CFG_CMD_HWFLOW | */ \ ++ CFG_CMD_SAVES | \ ++ CFG_CMD_NAND | \ ++ CFG_CMD_PORTIO | \ ++ CFG_CMD_MMC | \ ++ CFG_CMD_FAT | \ ++ CFG_CMD_EXT2 | \ ++ 0) ++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ ++#include ++ ++#define CONFIG_BOOTDELAY 3 ++#define CONFIG_BOOTARGS "rootfstype=jffs2 root=/dev/mtdblock4 console=ttySAC0,115200 console=tty0 loglevel=8" ++#define CONFIG_BOOTCOMMAND "nand read.e 0x32000000 0x34000 0x200000; bootm 0x32000000" ++ ++#define CONFIG_DOS_PARTITION 1 ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ ++/* what's this ? it's not used anywhere */ ++#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ ++#endif ++ ++/* ++ * Miscellaneous configurable options ++ */ ++#define CFG_LONGHELP /* undef to save memory */ ++#if defined(CONFIG_ARCH_GTA01_v3) ++#define CFG_PROMPT "GTA01v3 # " /* Monitor Command Prompt */ ++#elif defined(CONFIG_ARCH_GTA01_v4) ++#define CFG_PROMPT "GTA01v4 # " /* Monitor Command Prompt */ ++#elif defined(CONFIG_ARCH_GTA01B_v2) ++#define CFG_PROMPT "GTA01Bv2 # " /* Monitor Command Prompt */ ++#elif defined(CONFIG_ARCH_GTA01B_v3) ++#define CFG_PROMPT "GTA01Bv3 # " /* Monitor Command Prompt */ ++#elif defined(CONFIG_ARCH_GTA01B_v4) ++#define CFG_PROMPT "GTA01Bv4 # " /* Monitor Command Prompt */ ++#endif ++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ ++#define CFG_MAXARGS 16 /* max number of command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ ++ ++#define CFG_MEMTEST_START 0x30000000 /* memtest works on */ ++#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ ++ ++#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ ++ ++#define CFG_LOAD_ADDR 0x33000000 /* default load address */ ++ ++/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ ++/* it to wrap 100 times (total 1562500) to get 1 sec. */ ++#define CFG_HZ 1562500 ++ ++/* valid baudrates */ ++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } ++ ++/*----------------------------------------------------------------------- ++ * Stack sizes ++ * ++ * The stack sizes are set up in start.S using the settings below ++ */ ++#define CONFIG_STACKSIZE (128*1024) /* regular stack */ ++#ifdef CONFIG_USE_IRQ ++#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ ++#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ ++#endif ++ ++#if 0 ++#define CONFIG_USB_OHCI 1 ++#endif ++ ++/*----------------------------------------------------------------------- ++ * Physical Memory Map ++ */ ++#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ ++#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ ++#if defined(CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4) ++#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ ++#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3) || \ ++ defined(CONFIG_ARCH_GTA01B_v4) ++#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ ++#else ++#error Please define GTA01 variant ++#endif ++#define PHYS_SDRAM_RES_SIZE 0x00200000 /* 2 MB for frame buffer */ ++ ++/*----------------------------------------------------------------------- ++ * FLASH and environment organization ++ */ ++ ++/* No NOR flash in this device */ ++#define CFG_NO_FLASH 1 ++ ++#define CFG_ENV_IS_IN_NAND 1 ++#define CFG_ENV_SIZE 0x4000 /* 16k Total Size of Environment Sector */ ++#define CFG_ENV_OFFSET_OOB 1 /* Location of ENV stored in block 0 OOB */ ++ ++#define NAND_MAX_CHIPS 1 ++#define CFG_NAND_BASE 0x4e000000 ++#define CFG_MAX_NAND_DEVICE 1 ++ ++#define CONFIG_MMC 1 ++#define CFG_MMC_BASE 0xff000000 ++ ++/* EXT2 driver */ ++#define CONFIG_EXT2 1 ++ ++#define CONFIG_FAT 1 ++#define CONFIG_SUPPORT_VFAT ++ ++#if 0 ++/* JFFS2 driver */ ++#define CONFIG_JFFS2_CMDLINE 1 ++#define CONFIG_JFFS2_NAND 1 ++#define CONFIG_JFFS2_NAND_DEV 0 ++#define CONFIG_JFFS2_NAND_OFF 0x634000 ++#define CONFIG_JFFS2_NAND_SIZE 0x39cc000 ++#endif ++ ++/* ATAG configuration */ ++#define CONFIG_INITRD_TAG 1 ++#define CONFIG_SETUP_MEMORY_TAGS 1 ++#define CONFIG_CMDLINE_TAG 1 ++#define CONFIG_REVISION_TAG 1 ++#if 0 ++#define CONFIG_SERIAL_TAG 1 ++#endif ++ ++#define CONFIG_DRIVER_S3C24X0_I2C 1 ++#define CONFIG_HARD_I2C 1 ++#define CFG_I2C_SPEED 400000 /* 400kHz according to PCF50606 data sheet */ ++#define CFG_I2C_SLAVE 0x7f ++ ++/* we have a board_late_init() function */ ++#define BOARD_LATE_INIT 1 ++ ++#if 1 ++#define CONFIG_VIDEO ++#define CONFIG_VIDEO_S3C2410 ++#define CONFIG_CFB_CONSOLE ++#define CONFIG_VIDEO_LOGO ++#define CONFIG_VGA_AS_SINGLE_DEVICE ++ ++#define VIDEO_KBD_INIT_FCT 0 ++#define VIDEO_TSTC_FCT serial_tstc ++#define VIDEO_GETC_FCT serial_getc ++ ++#define LCD_VIDEO_ADDR 0x33d00000 ++#endif ++ ++#define CONFIG_S3C2410_NAND_BBT 1 ++#define CONFIG_S3C2410_NAND_HWECC 1 ++ ++#define CONFIG_DRIVER_PCF50606 1 ++ ++#endif /* __CONFIG_H */ +Index: u-boot/board/neo1973/common/neo1973.h +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/common/neo1973.h +@@ -0,0 +1,32 @@ ++#ifndef _NEO1973_H ++#define _NEO1973_H ++ ++enum wakeup_reason { ++ NEO1973_WAKEUP_NONE, ++ NEO1973_WAKEUP_RESET, ++ NEO1973_WAKEUP_POWER_KEY, ++ NEO1973_WAKEUP_CHARGER, ++ NEO1973_WAKEUP_ALARM, ++}; ++ ++enum neo1973_charger_cmd { ++ NEO1973_CHGCMD_NONE, ++ NEO1973_CHGCMD_AUTOFAST, ++ NEO1973_CHGCMD_NO_AUTOFAST, ++ NEO1973_CHGCMD_OFF, ++ NEO1973_CHGCMD_FAST, ++ NEO1973_CHGCMD_FASTER, ++}; ++ ++extern unsigned int neo1973_wakeup_cause; ++ ++void neo1973_poweroff(void); ++void neo1973_backlight(int on); ++void neo1973_vibrator(int on); ++ ++int neo1973_911_key_pressed(void); ++ ++const char *neo1973_get_charge_status(void); ++int neo1973_set_charge_mode(enum neo1973_charger_cmd cmd); ++ ++#endif diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-20061030-qt2410.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-20061030-qt2410.patch new file mode 100644 index 0000000000..343598902f --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-20061030-qt2410.patch @@ -0,0 +1,1233 @@ +This patch adds 'board' support for the Armzone QT2410 +development board to u-boot. + +Signed-off-by: Harald Welte + +Index: u-boot/Makefile +=================================================================== +--- u-boot.orig/Makefile ++++ u-boot/Makefile +@@ -2009,6 +2009,9 @@ + sbc2410x_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t sbc2410x NULL s3c24x0 + ++qt2410_config : unconfig ++ @./mkconfig $(@:_config=) arm arm920t qt2410 NULL s3c24x0 ++ + scb9328_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t scb9328 NULL imx + +Index: u-boot/board/qt2410/Makefile +=================================================================== +--- /dev/null ++++ u-boot/board/qt2410/Makefile +@@ -0,0 +1,47 @@ ++# ++# (C) Copyright 2000, 2001, 2002 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = lib$(BOARD).a ++ ++OBJS := qt2410.o flash.o ++SOBJS := lowlevel_init.o ++ ++$(LIB): $(OBJS) $(SOBJS) ++ $(AR) crv $@ $(OBJS) $(SOBJS) ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak .depend ++ ++######################################################################### ++ ++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) ++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ ++ ++-include .depend ++ ++######################################################################### +Index: u-boot/board/qt2410/config.mk +=================================================================== +--- /dev/null ++++ u-boot/board/qt2410/config.mk +@@ -0,0 +1,29 @@ ++# ++# (C) Copyright 2002 ++# Gary Jennejohn, DENX Software Engineering, ++# David Mueller, ELSOFT AG, ++# ++# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu ++# ++# see http://www.samsung.com/ for more information on SAMSUNG ++# ++ ++CONFIG_USB_DFU_VENDOR=0x1457 ++CONFIG_USB_DFU_PRODUCT=0x511d ++CONFIG_USB_DFU_REVISION=0x0100 ++ ++# ++# SMDK2410 has 1 bank of 64 MB DRAM ++# ++# 3000'0000 to 3400'0000 ++# ++# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 ++# optionally with a ramdisk at 3080'0000 ++# ++# we load ourself to 33F8'0000 ++# ++# download area is 3300'0000 ++# ++ ++ ++TEXT_BASE = 0x33F80000 +Index: u-boot/board/qt2410/flash.c +=================================================================== +--- /dev/null ++++ u-boot/board/qt2410/flash.c +@@ -0,0 +1,435 @@ ++/* ++ * (C) Copyright 2002 ++ * Sysgo Real-Time Solutions, GmbH ++ * Alex Zuepke ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++ ++ulong myflush (void); ++ ++ ++#define FLASH_BANK_SIZE PHYS_FLASH_SIZE ++#define MAIN_SECT_SIZE 0x10000 /* 64 KB */ ++ ++flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; ++ ++ ++#define CMD_READ_ARRAY 0x000000F0 ++#define CMD_UNLOCK1 0x000000AA ++#define CMD_UNLOCK2 0x00000055 ++#define CMD_ERASE_SETUP 0x00000080 ++#define CMD_ERASE_CONFIRM 0x00000030 ++#define CMD_PROGRAM 0x000000A0 ++#define CMD_UNLOCK_BYPASS 0x00000020 ++ ++#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1))) ++#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1))) ++ ++#define BIT_ERASE_DONE 0x00000080 ++#define BIT_RDY_MASK 0x00000080 ++#define BIT_PROGRAM_ERROR 0x00000020 ++#define BIT_TIMEOUT 0x80000000 /* our flag */ ++ ++#define READY 1 ++#define ERR 2 ++#define TMO 4 ++ ++/*----------------------------------------------------------------------- ++ */ ++ ++ulong flash_init (void) ++{ ++ int i, j; ++ ulong size = 0; ++ ++ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { ++ ulong flashbase = 0; ++ ++ flash_info[i].flash_id = ++#if defined(CONFIG_AMD_LV400) ++ (AMD_MANUFACT & FLASH_VENDMASK) | ++ (AMD_ID_LV400B & FLASH_TYPEMASK); ++#elif defined(CONFIG_AMD_LV800) ++ (AMD_MANUFACT & FLASH_VENDMASK) | ++ (AMD_ID_LV800B & FLASH_TYPEMASK); ++#else ++#error "Unknown flash configured" ++#endif ++ flash_info[i].size = FLASH_BANK_SIZE; ++ flash_info[i].sector_count = CFG_MAX_FLASH_SECT; ++ memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); ++ if (i == 0) ++ flashbase = PHYS_FLASH_1; ++ else ++ panic ("configured too many flash banks!\n"); ++ for (j = 0; j < flash_info[i].sector_count; j++) { ++ if (j <= 3) { ++ /* 1st one is 16 KB */ ++ if (j == 0) { ++ flash_info[i].start[j] = ++ flashbase + 0; ++ } ++ ++ /* 2nd and 3rd are both 8 KB */ ++ if ((j == 1) || (j == 2)) { ++ flash_info[i].start[j] = ++ flashbase + 0x4000 + (j - ++ 1) * ++ 0x2000; ++ } ++ ++ /* 4th 32 KB */ ++ if (j == 3) { ++ flash_info[i].start[j] = ++ flashbase + 0x8000; ++ } ++ } else { ++ flash_info[i].start[j] = ++ flashbase + (j - 3) * MAIN_SECT_SIZE; ++ } ++ } ++ size += flash_info[i].size; ++ } ++ ++ flash_protect (FLAG_PROTECT_SET, ++ CFG_FLASH_BASE, ++ CFG_FLASH_BASE + monitor_flash_len - 1, ++ &flash_info[0]); ++ ++#if 0 ++ flash_protect (FLAG_PROTECT_SET, ++ CFG_ENV_ADDR, ++ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); ++#endif ++ ++ return size; ++} ++ ++/*----------------------------------------------------------------------- ++ */ ++void flash_print_info (flash_info_t * info) ++{ ++ int i; ++ ++ switch (info->flash_id & FLASH_VENDMASK) { ++ case (AMD_MANUFACT & FLASH_VENDMASK): ++ printf ("AMD: "); ++ break; ++ default: ++ printf ("Unknown Vendor "); ++ break; ++ } ++ ++ switch (info->flash_id & FLASH_TYPEMASK) { ++ case (AMD_ID_LV400B & FLASH_TYPEMASK): ++ printf ("1x Amd29LV400BB (4Mbit)\n"); ++ break; ++ case (AMD_ID_LV800B & FLASH_TYPEMASK): ++ printf ("1x Amd29LV800BB (8Mbit)\n"); ++ break; ++ default: ++ printf ("Unknown Chip Type\n"); ++ goto Done; ++ break; ++ } ++ ++ printf (" Size: %ld MB in %d Sectors\n", ++ info->size >> 20, info->sector_count); ++ ++ printf (" Sector Start Addresses:"); ++ for (i = 0; i < info->sector_count; i++) { ++ if ((i % 5) == 0) { ++ printf ("\n "); ++ } ++ printf (" %08lX%s", info->start[i], ++ info->protect[i] ? " (RO)" : " "); ++ } ++ printf ("\n"); ++ ++ Done:; ++} ++ ++/*----------------------------------------------------------------------- ++ */ ++ ++int flash_erase (flash_info_t * info, int s_first, int s_last) ++{ ++ ushort result; ++ int iflag, cflag, prot, sect; ++ int rc = ERR_OK; ++ int chip; ++ ++ /* first look for protection bits */ ++ ++ if (info->flash_id == FLASH_UNKNOWN) ++ return ERR_UNKNOWN_FLASH_TYPE; ++ ++ if ((s_first < 0) || (s_first > s_last)) { ++ return ERR_INVAL; ++ } ++ ++ if ((info->flash_id & FLASH_VENDMASK) != ++ (AMD_MANUFACT & FLASH_VENDMASK)) { ++ return ERR_UNKNOWN_FLASH_VENDOR; ++ } ++ ++ prot = 0; ++ for (sect = s_first; sect <= s_last; ++sect) { ++ if (info->protect[sect]) { ++ prot++; ++ } ++ } ++ if (prot) ++ return ERR_PROTECTED; ++ ++ /* ++ * Disable interrupts which might cause a timeout ++ * here. Remember that our exception vectors are ++ * at address 0 in the flash, and we don't want a ++ * (ticker) exception to happen while the flash ++ * chip is in programming mode. ++ */ ++ cflag = icache_status (); ++ icache_disable (); ++ iflag = disable_interrupts (); ++ ++ /* Start erase on unprotected sectors */ ++ for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { ++ printf ("Erasing sector %2d ... ", sect); ++ ++ /* arm simple, non interrupt dependent timer */ ++ reset_timer_masked (); ++ ++ if (info->protect[sect] == 0) { /* not protected */ ++ vu_short *addr = (vu_short *) (info->start[sect]); ++ ++ MEM_FLASH_ADDR1 = CMD_UNLOCK1; ++ MEM_FLASH_ADDR2 = CMD_UNLOCK2; ++ MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; ++ ++ MEM_FLASH_ADDR1 = CMD_UNLOCK1; ++ MEM_FLASH_ADDR2 = CMD_UNLOCK2; ++ *addr = CMD_ERASE_CONFIRM; ++ ++ /* wait until flash is ready */ ++ chip = 0; ++ ++ do { ++ result = *addr; ++ ++ /* check timeout */ ++ if (get_timer_masked () > ++ CFG_FLASH_ERASE_TOUT) { ++ MEM_FLASH_ADDR1 = CMD_READ_ARRAY; ++ chip = TMO; ++ break; ++ } ++ ++ if (!chip ++ && (result & 0xFFFF) & BIT_ERASE_DONE) ++ chip = READY; ++ ++ if (!chip ++ && (result & 0xFFFF) & BIT_PROGRAM_ERROR) ++ chip = ERR; ++ ++ } while (!chip); ++ ++ MEM_FLASH_ADDR1 = CMD_READ_ARRAY; ++ ++ if (chip == ERR) { ++ rc = ERR_PROG_ERROR; ++ goto outahere; ++ } ++ if (chip == TMO) { ++ rc = ERR_TIMOUT; ++ goto outahere; ++ } ++ ++ printf ("ok.\n"); ++ } else { /* it was protected */ ++ ++ printf ("protected!\n"); ++ } ++ } ++ ++ if (ctrlc ()) ++ printf ("User Interrupt!\n"); ++ ++ outahere: ++ /* allow flash to settle - wait 10 ms */ ++ udelay_masked (10000); ++ ++ if (iflag) ++ enable_interrupts (); ++ ++ if (cflag) ++ icache_enable (); ++ ++ return rc; ++} ++ ++/*----------------------------------------------------------------------- ++ * Copy memory to flash ++ */ ++ ++volatile static int write_hword (flash_info_t * info, ulong dest, ushort data) ++{ ++ vu_short *addr = (vu_short *) dest; ++ ushort result; ++ int rc = ERR_OK; ++ int cflag, iflag; ++ int chip; ++ ++ /* ++ * Check if Flash is (sufficiently) erased ++ */ ++ result = *addr; ++ if ((result & data) != data) ++ return ERR_NOT_ERASED; ++ ++ ++ /* ++ * Disable interrupts which might cause a timeout ++ * here. Remember that our exception vectors are ++ * at address 0 in the flash, and we don't want a ++ * (ticker) exception to happen while the flash ++ * chip is in programming mode. ++ */ ++ cflag = icache_status (); ++ icache_disable (); ++ iflag = disable_interrupts (); ++ ++ MEM_FLASH_ADDR1 = CMD_UNLOCK1; ++ MEM_FLASH_ADDR2 = CMD_UNLOCK2; ++ MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS; ++ *addr = CMD_PROGRAM; ++ *addr = data; ++ ++ /* arm simple, non interrupt dependent timer */ ++ reset_timer_masked (); ++ ++ /* wait until flash is ready */ ++ chip = 0; ++ do { ++ result = *addr; ++ ++ /* check timeout */ ++ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { ++ chip = ERR | TMO; ++ break; ++ } ++ if (!chip && ((result & 0x80) == (data & 0x80))) ++ chip = READY; ++ ++ if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { ++ result = *addr; ++ ++ if ((result & 0x80) == (data & 0x80)) ++ chip = READY; ++ else ++ chip = ERR; ++ } ++ ++ } while (!chip); ++ ++ *addr = CMD_READ_ARRAY; ++ ++ if (chip == ERR || *addr != data) ++ rc = ERR_PROG_ERROR; ++ ++ if (iflag) ++ enable_interrupts (); ++ ++ if (cflag) ++ icache_enable (); ++ ++ return rc; ++} ++ ++/*----------------------------------------------------------------------- ++ * Copy memory to flash. ++ */ ++ ++int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) ++{ ++ ulong cp, wp; ++ int l; ++ int i, rc; ++ ushort data; ++ ++ wp = (addr & ~1); /* get lower word aligned address */ ++ ++ /* ++ * handle unaligned start bytes ++ */ ++ if ((l = addr - wp) != 0) { ++ data = 0; ++ for (i = 0, cp = wp; i < l; ++i, ++cp) { ++ data = (data >> 8) | (*(uchar *) cp << 8); ++ } ++ for (; i < 2 && cnt > 0; ++i) { ++ data = (data >> 8) | (*src++ << 8); ++ --cnt; ++ ++cp; ++ } ++ for (; cnt == 0 && i < 2; ++i, ++cp) { ++ data = (data >> 8) | (*(uchar *) cp << 8); ++ } ++ ++ if ((rc = write_hword (info, wp, data)) != 0) { ++ return (rc); ++ } ++ wp += 2; ++ } ++ ++ /* ++ * handle word aligned part ++ */ ++ while (cnt >= 2) { ++ data = *((vu_short *) src); ++ if ((rc = write_hword (info, wp, data)) != 0) { ++ return (rc); ++ } ++ src += 2; ++ wp += 2; ++ cnt -= 2; ++ } ++ ++ if (cnt == 0) { ++ return ERR_OK; ++ } ++ ++ /* ++ * handle unaligned tail bytes ++ */ ++ data = 0; ++ for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { ++ data = (data >> 8) | (*src++ << 8); ++ --cnt; ++ } ++ for (; i < 2; ++i, ++cp) { ++ data = (data >> 8) | (*(uchar *) cp << 8); ++ } ++ ++ return write_hword (info, wp, data); ++} +Index: u-boot/board/qt2410/lowlevel_init.S +=================================================================== +--- /dev/null ++++ u-boot/board/qt2410/lowlevel_init.S +@@ -0,0 +1,171 @@ ++/* ++ * Memory Setup stuff - taken from blob memsetup.S ++ * ++ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and ++ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) ++ * ++ * Modified for the Samsung SMDK2410 by ++ * (C) Copyright 2002 ++ * David Mueller, ELSOFT AG, ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++ ++#include ++#include ++ ++ ++/* some parameters for the board */ ++ ++/* ++ * ++ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S ++ * ++ * Copyright (C) 2002 Samsung Electronics SW.LEE ++ * ++ */ ++ ++#define BWSCON 0x48000000 ++ ++/* BWSCON */ ++#define DW8 (0x0) ++#define DW16 (0x1) ++#define DW32 (0x2) ++#define WAIT (0x1<<2) ++#define UBLB (0x1<<3) ++ ++#define B1_BWSCON (DW32) ++#define B2_BWSCON (DW16) ++#define B3_BWSCON (DW16 + WAIT + UBLB) ++#define B4_BWSCON (DW16) ++#define B5_BWSCON (DW16) ++#define B6_BWSCON (DW32) ++#define B7_BWSCON (DW32) ++ ++/* BANK0CON */ ++#define B0_Tacs 0x0 /* 0clk */ ++#define B0_Tcos 0x0 /* 0clk */ ++#define B0_Tacc 0x7 /* 14clk */ ++#define B0_Tcoh 0x0 /* 0clk */ ++#define B0_Tah 0x0 /* 0clk */ ++#define B0_Tacp 0x0 ++#define B0_PMC 0x0 /* normal */ ++ ++/* BANK1CON */ ++#define B1_Tacs 0x0 /* 0clk */ ++#define B1_Tcos 0x0 /* 0clk */ ++#define B1_Tacc 0x7 /* 14clk */ ++#define B1_Tcoh 0x0 /* 0clk */ ++#define B1_Tah 0x0 /* 0clk */ ++#define B1_Tacp 0x0 ++#define B1_PMC 0x0 ++ ++#define B2_Tacs 0x0 ++#define B2_Tcos 0x0 ++#define B2_Tacc 0x7 ++#define B2_Tcoh 0x0 ++#define B2_Tah 0x0 ++#define B2_Tacp 0x0 ++#define B2_PMC 0x0 ++ ++#define B3_Tacs 0x0 /* 0clk */ ++#define B3_Tcos 0x3 /* 4clk */ ++#define B3_Tacc 0x7 /* 14clk */ ++#define B3_Tcoh 0x1 /* 1clk */ ++#define B3_Tah 0x0 /* 0clk */ ++#define B3_Tacp 0x3 /* 6clk */ ++#define B3_PMC 0x0 /* normal */ ++ ++#define B4_Tacs 0x0 /* 0clk */ ++#define B4_Tcos 0x0 /* 0clk */ ++#define B4_Tacc 0x7 /* 14clk */ ++#define B4_Tcoh 0x0 /* 0clk */ ++#define B4_Tah 0x0 /* 0clk */ ++#define B4_Tacp 0x0 ++#define B4_PMC 0x0 /* normal */ ++ ++#define B5_Tacs 0x0 /* 0clk */ ++#define B5_Tcos 0x0 /* 0clk */ ++#define B5_Tacc 0x7 /* 14clk */ ++#define B5_Tcoh 0x0 /* 0clk */ ++#define B5_Tah 0x0 /* 0clk */ ++#define B5_Tacp 0x0 ++#define B5_PMC 0x0 /* normal */ ++ ++#define B6_MT 0x3 /* SDRAM */ ++#define B6_Trcd 0x1 ++#define B6_SCAN 0x1 /* 9bit */ ++ ++#define B7_MT 0x3 /* SDRAM */ ++#define B7_Trcd 0x1 /* 3clk */ ++#define B7_SCAN 0x1 /* 9bit */ ++ ++/* REFRESH parameter */ ++#define REFEN 0x1 /* Refresh enable */ ++#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ ++#define Trp 0x1 /* 3clk */ ++#define Trc 0x3 /* 7clk */ ++#define Tchr 0x2 /* 3clk */ ++//#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ ++#define REFCNT 997 /* period=17.5us, HCLK=60Mhz, (2048+1-15.6*60) */ ++/**************************************/ ++ ++_TEXT_BASE: ++ .word TEXT_BASE ++ ++.globl lowlevel_init ++lowlevel_init: ++ /* memory control configuration */ ++ /* make r0 relative the current location so that it */ ++ /* reads SMRDATA out of FLASH rather than memory ! */ ++ adr r0, SMRDATA ++ ldr r1, =BWSCON /* Bus Width Status Controller */ ++ add r2, r0, #13*4 ++0: ++ ldr r3, [r0], #4 ++ str r3, [r1], #4 ++ cmp r2, r0 ++ bne 0b ++ ++ /* setup asynchronous bus mode */ ++ mrc p15, 0, r1 ,c1 ,c0, 0 ++ orr r1, r1, #0xc0000000 ++ mcr p15, 0, r1, c1, c0, 0 ++ ++ /* everything is fine now */ ++ mov pc, lr ++ ++ .ltorg ++/* the literal pools origin */ ++ ++SMRDATA: ++ .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) ++ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ++ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ++ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ++ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ++ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ++ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ++ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ++ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ++ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) ++ .word 0xb2 ++ .word 0x30 ++ .word 0x30 +Index: u-boot/board/qt2410/qt2410.c +=================================================================== +--- /dev/null ++++ u-boot/board/qt2410/qt2410.c +@@ -0,0 +1,152 @@ ++/* ++ * (C) 2006 by OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * based on existing S3C2410 startup code in u-boot: ++ * ++ * (C) Copyright 2002 ++ * Sysgo Real-Time Solutions, GmbH ++ * Marius Groeger ++ * ++ * (C) Copyright 2002 ++ * David Mueller, ELSOFT AG, ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#if 1 ++//#define M_MDIV 0xA1 /* Fout = 202.8MHz */ ++//#define M_PDIV 0x3 ++//#define M_SDIV 0x1 ++#define M_MDIV 0x90 /* Fout = 202.8MHz */ ++#define M_PDIV 0x7 ++#define M_SDIV 0x0 ++#else ++#define M_MDIV 0x5c /* Fout = 150.0MHz */ ++#define M_PDIV 0x4 ++#define M_SDIV 0x0 ++#endif ++ ++#if 1 ++#define U_M_MDIV 0x78 ++#define U_M_PDIV 0x2 ++#define U_M_SDIV 0x3 ++#else ++#define U_M_MDIV 0x48 ++#define U_M_PDIV 0x3 ++#define U_M_SDIV 0x2 ++#endif ++ ++static inline void delay (unsigned long loops) ++{ ++ __asm__ volatile ("1:\n" ++ "subs %0, %1, #1\n" ++ "bne 1b":"=r" (loops):"0" (loops)); ++} ++ ++/* ++ * Miscellaneous platform dependent initialisations ++ */ ++ ++int board_init (void) ++{ ++ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ ++ /* to reduce PLL lock time, adjust the LOCKTIME register */ ++ clk_power->LOCKTIME = 0xFFFFFF; ++ ++ /* configure MPLL */ ++ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); ++ ++ /* some delay between MPLL and UPLL */ ++ delay (4000); ++ ++ /* configure UPLL */ ++ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); ++ ++ /* some delay between MPLL and UPLL */ ++ delay (8000); ++ ++ /* set up the I/O ports */ ++ gpio->GPACON = 0x007FFFFF; ++ gpio->GPBCON = 0x00044555; ++ gpio->GPBUP = 0x000007FF; ++ gpio->GPCCON = 0xAAAAAAAA; ++ gpio->GPCUP = 0x0000FFFF; ++ gpio->GPDCON = 0xAAAAAAAA; ++ gpio->GPDUP = 0x0000FFFF; ++ gpio->GPECON = 0xAAAAAAAA; ++ gpio->GPEUP = 0x0000FFFF; ++ gpio->GPFCON = 0x000055AA; ++ gpio->GPFUP = 0x000000FF; ++ gpio->GPGCON = 0xFF95FFBA; ++ //gpio->GPGUP = 0x0000FFFF; ++ gpio->GPGUP = 0x0000AFEF; ++ gpio->GPHCON = 0x0028FAAA; ++ gpio->GPHUP = 0x000007FF; ++ ++ /* arch number of SMDK2410-Board */ ++ gd->bd->bi_arch_number = MACH_TYPE_QT2410; ++ ++ /* adress of boot parameters */ ++ gd->bd->bi_boot_params = 0x30000100; ++ ++ icache_enable(); ++ dcache_enable(); ++ ++ return 0; ++} ++ ++#if defined(CONFIG_USB_DEVICE) ++void udc_ctrl(enum usbd_event event, int param) ++{ ++} ++#endif ++ ++void board_video_init(GraphicDevice *pGD) ++{ ++ S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD(); ++ ++ /* FIXME: select LCM type by env variable */ ++ ++ /* Configuration for GTA01 LCM on QT2410 */ ++ lcd->LCDCON1 = 0x00000178; /* CLKVAL=1, BPPMODE=16bpp, TFT, ENVID=0 */ ++ ++ lcd->LCDCON2 = 0x019fc3c1; ++ lcd->LCDCON3 = 0x0039df67; ++ lcd->LCDCON4 = 0x00000007; ++ lcd->LCDCON5 = 0x0001cf09; ++ lcd->LPCSEL = 0x00000000; ++} ++ ++int dram_init (void) ++{ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; ++ ++ return 0; ++} +Index: u-boot/board/qt2410/u-boot.lds +=================================================================== +--- /dev/null ++++ u-boot/board/qt2410/u-boot.lds +@@ -0,0 +1,58 @@ ++/* ++ * (C) Copyright 2002 ++ * Gary Jennejohn, DENX Software Engineering, ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ ++OUTPUT_ARCH(arm) ++ENTRY(_start) ++SECTIONS ++{ ++ . = 0x00000000; ++ ++ . = ALIGN(4); ++ .text : ++ { ++ cpu/arm920t/start.o (.text) ++ cpu/arm920t/s3c24x0/nand_read.o (.text) ++ *(.text) ++ } ++ ++ . = ALIGN(4); ++ .rodata : { *(.rodata) } ++ ++ . = ALIGN(4); ++ .data : { *(.data) } ++ ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ . = .; ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss : { *(.bss) } ++ _end = .; ++} +Index: u-boot/include/configs/qt2410.h +=================================================================== +--- /dev/null ++++ u-boot/include/configs/qt2410.h +@@ -0,0 +1,287 @@ ++/* ++ * (C) Copyright 2002 ++ * Sysgo Real-Time Solutions, GmbH ++ * Marius Groeger ++ * Gary Jennejohn ++ * David Mueller ++ * ++ * Configuation settings for the Armzone QT2410 board. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#if 0 ++/* If we want to start u-boot from usb bootloader in NOR flash */ ++#define CONFIG_SKIP_RELOCATE_UBOOT 1 ++#define CONFIG_SKIP_LOWLEVEL_INIT 1 ++#else ++/* If we want to start u-boot directly from within NAND flash */ ++#define CONFIG_S3C2410_NAND_BOOT 1 ++#define CONFIG_S3C2410_NAND_SKIP_BAD 1 ++#endif ++ ++#define CFG_UBOOT_SIZE 0x40000 ++ ++/* ++ * High Level Configuration Options ++ * (easy to change) ++ */ ++#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ ++#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ ++#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */ ++ ++/* input clock of PLL */ ++#define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */ ++ ++ ++#define USE_920T_MMU 1 ++#define CONFIG_USE_IRQ 1 ++ ++/* ++ * Size of malloc() pool ++ */ ++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 400*1024) ++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ ++ ++/* ++ * Hardware drivers ++ */ ++#if 0 ++#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ ++#define CS8900_BASE 0x19000300 ++#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ ++#endif ++ ++/* ++ * select serial console configuration ++ */ ++#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */ ++#define CONFIG_HWFLOW 1 ++ ++/************************************************************ ++ * RTC ++ ************************************************************/ ++#define CONFIG_RTC_S3C24X0 1 ++ ++/* allow to overwrite serial and ethaddr */ ++#define CONFIG_ENV_OVERWRITE ++ ++#define CONFIG_BAUDRATE 115200 ++ ++/*********************************************************** ++ * Command definition ++ ***********************************************************/ ++#define CONFIG_COMMANDS (\ ++ CFG_CMD_BDI | \ ++ CFG_CMD_LOADS | \ ++ CFG_CMD_LOADB | \ ++ CFG_CMD_IMI | \ ++ CFG_CMD_CACHE | \ ++ CFG_CMD_MEMORY | \ ++ CFG_CMD_ENV | \ ++ /* CFG_CMD_IRQ | */ \ ++ CFG_CMD_BOOTD | \ ++ CFG_CMD_CONSOLE | \ ++ CFG_CMD_BMP | \ ++ CFG_CMD_ASKENV | \ ++ CFG_CMD_RUN | \ ++ CFG_CMD_ECHO | \ ++ CFG_CMD_I2C | \ ++ CFG_CMD_REGINFO | \ ++ CFG_CMD_IMMAP | \ ++ CFG_CMD_DATE | \ ++ CFG_CMD_AUTOSCRIPT | \ ++ CFG_CMD_BSP | \ ++ CFG_CMD_ELF | \ ++ CFG_CMD_MISC | \ ++ /* CFG_CMD_USB | */ \ ++ CFG_CMD_JFFS2 | \ ++ CFG_CMD_DIAG | \ ++ CFG_CMD_HWFLOW | \ ++ CFG_CMD_SAVES | \ ++ CFG_CMD_NAND | \ ++ CFG_CMD_PORTIO | \ ++ CFG_CMD_MMC | \ ++ CFG_CMD_FAT | \ ++ CFG_CMD_EXT2 | \ ++ 0) ++ ++#if 0 ++ CFG_CMD_DHCP | \ ++ CFG_CMD_PING | \ ++ CFG_CMD_NET | \ ++ ++#endif ++ ++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ ++#include ++ ++#define CONFIG_BOOTDELAY 3 ++#define CONFIG_BOOTARGS "rootfstype=jffs2 root=/dev/mtdblock4 console=ttySAC0,115200 console=tty0 loglevel=8" ++#define CONFIG_ETHADDR 01:ab:cd:ef:fe:dc ++#define CONFIG_NETMASK 255.255.255.0 ++#define CONFIG_IPADDR 10.0.0.110 ++#define CONFIG_SERVERIP 10.0.0.1 ++/*#define CONFIG_BOOTFILE "elinos-lart" */ ++#define CONFIG_BOOTCOMMAND "nand load 0x32000000 0x34000 0x200000; bootm 0x32000000" ++ ++#define CONFIG_DOS_PARTITION 1 ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ ++/* what's this ? it's not used anywhere */ ++#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ ++#endif ++ ++/* ++ * Miscellaneous configurable options ++ */ ++#define CFG_LONGHELP /* undef to save memory */ ++#define CFG_PROMPT "QT2410 # " /* Monitor Command Prompt */ ++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ ++#define CFG_MAXARGS 64 /* max number of command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ ++ ++#define CFG_MEMTEST_START 0x30000000 /* memtest works on */ ++#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ ++ ++#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ ++ ++#define CFG_LOAD_ADDR 0x33000000 /* default load address */ ++ ++/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ ++/* it to wrap 100 times (total 1562500) to get 1 sec. */ ++#define CFG_HZ 1562500 ++ ++/* valid baudrates */ ++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } ++ ++/*----------------------------------------------------------------------- ++ * Stack sizes ++ * ++ * The stack sizes are set up in start.S using the settings below ++ */ ++#define CONFIG_STACKSIZE (128*1024) /* regular stack */ ++#ifdef CONFIG_USE_IRQ ++#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ ++#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ ++#endif ++ ++#define CONFIG_USB_OHCI 1 ++ ++#define CONFIG_USB_DEVICE 1 ++#define CONFIG_USB_TTY 1 ++#define CFG_CONSOLE_IS_IN_ENV 1 ++#define CONFIG_USBD_VENDORID 0x1457 /* Linux/NetChip */ ++#define CONFIG_USBD_PRODUCTID_GSERIAL 0x5120 /* gserial */ ++#define CONFIG_USBD_PRODUCTID_CDCACM 0x511d /* CDC ACM */ ++#define CONFIG_USBD_MANUFACTURER "Armzone" ++#define CONFIG_USBD_PRODUCT_NAME "QT2410 Bootloader " U_BOOT_VERSION ++#define CONFIG_EXTRA_ENV_SETTINGS "usbtty=cdc_acm\0" ++#define CONFIG_USBD_DFU 1 ++#define CONFIG_USBD_DFU_XFER_SIZE 0x4000 ++ ++/*----------------------------------------------------------------------- ++ * Physical Memory Map ++ */ ++#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ ++#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ ++#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ ++#define PHYS_SDRAM_RES_SIZE 0x00200000 /* 2 MB for frame buffer */ ++ ++#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ ++ ++#define CFG_FLASH_BASE PHYS_FLASH_1 ++ ++/*----------------------------------------------------------------------- ++ * FLASH and environment organization ++ */ ++ ++#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ ++ ++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ ++#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ ++#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ ++ ++/* timeout values are in ticks */ ++#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ ++#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ ++ ++#define CFG_ENV_IS_IN_NAND 1 ++#define CFG_ENV_SIZE 0x4000 /* 16k Total Size of Environment Sector */ ++#define CFG_ENV_OFFSET_OOB 1 /* Location of ENV stored in block 0 OOB */ ++ ++#define NAND_MAX_CHIPS 1 ++#define CFG_NAND_BASE 0x4e000000 ++#define CFG_MAX_NAND_DEVICE 1 ++ ++#define CONFIG_MMC 1 ++#define CFG_MMC_BASE 0xff000000 ++ ++#define CONFIG_EXT2 1 ++ ++/* FAT driver in u-boot is broken currently */ ++#define CONFIG_FAT 1 ++#define CONFIG_SUPPORT_VFAT ++ ++#if 1 ++/* JFFS2 driver */ ++#define CONFIG_JFFS2_CMDLINE 1 ++#define CONFIG_JFFS2_NAND 1 ++#define CONFIG_JFFS2_NAND_DEV 0 ++//#define CONFIG_JFFS2_NAND_OFF 0x634000 ++//#define CONFIG_JFFS2_NAND_SIZE 0x39cc000 ++#endif ++ ++/* ATAG configuration */ ++#define CONFIG_INITRD_TAG 1 ++#define CONFIG_SETUP_MEMORY_TAGS 1 ++#define CONFIG_CMDLINE_TAG 1 ++ ++#define CONFIG_DRIVER_S3C24X0_I2C 1 ++#define CONFIG_HARD_I2C 1 ++#define CFG_I2C_SPEED 400000 /* 400kHz according to PCF50606 data sheet */ ++#define CFG_I2C_SLAVE 0x7f ++ ++#define CONFIG_VIDEO ++#define CONFIG_VIDEO_S3C2410 ++#define CONFIG_CFB_CONSOLE ++#define CONFIG_VIDEO_LOGO ++#define CONFIG_SPLASH_SCREEN ++#define CFG_VIDEO_LOGO_MAX_SIZE (640*480+1024+100) /* 100 = slack */ ++#define CONFIG_VIDEO_BMP_GZIP ++#define CONFIG_VGA_AS_SINGLE_DEVICE ++#define CONFIG_UNZIP ++ ++#define VIDEO_KBD_INIT_FCT 0 ++#define VIDEO_TSTC_FCT serial_tstc ++#define VIDEO_GETC_FCT serial_getc ++ ++#define LCD_VIDEO_ADDR 0x33d00000 ++ ++#define CONFIG_S3C2410_NAND_BBT 1 ++ ++#define MTDIDS_DEFAULT "nand0=qt2410-nand" ++#define MTPARTS_DEFAULT "qt2410-nand:192k(u-boot),8k(u-boot_env),2M(kernel),2M(splash),-(jffs2)" ++ ++#endif /* __CONFIG_H */ diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-arm920_s3c2410_irq_demux.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-arm920_s3c2410_irq_demux.patch new file mode 100644 index 0000000000..b39a268c84 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-arm920_s3c2410_irq_demux.patch @@ -0,0 +1,56 @@ +This patch adds a IRQ demultiplexer callback to the arm920 cpu core code, +plus a stub implementation of it for the S3C2410. + +Index: u-boot.git/cpu/arm920t/interrupts.c +=================================================================== +--- u-boot.git.orig/cpu/arm920t/interrupts.c 2007-02-05 22:49:11.000000000 +0100 ++++ u-boot.git/cpu/arm920t/interrupts.c 2007-02-05 23:19:01.000000000 +0100 +@@ -161,11 +161,16 @@ + + void do_irq (struct pt_regs *pt_regs) + { +-#if defined (CONFIG_USE_IRQ) && defined (CONFIG_ARCH_INTEGRATOR) ++#if defined (CONFIG_USE_IRQ) ++#if defined (ARM920_IRQ_CALLBACK) ++ ARM920_IRQ_CALLBACK(); ++ return; ++#elif defined (CONFIG_ARCH_INTEGRATOR) + /* ASSUMED to be a timer interrupt */ + /* Just clear it - count handled in */ + /* integratorap.c */ + *(volatile ulong *)(CFG_TIMERBASE + 0x0C) = 0; ++#endif /* ARCH_INTEGRATOR */ + #else + printf ("interrupt request\n"); + show_regs (pt_regs); +Index: u-boot.git/cpu/arm920t/s3c24x0/interrupts.c +=================================================================== +--- u-boot.git.orig/cpu/arm920t/s3c24x0/interrupts.c 2007-02-05 22:49:11.000000000 +0100 ++++ u-boot.git/cpu/arm920t/s3c24x0/interrupts.c 2007-02-05 23:21:35.000000000 +0100 +@@ -216,4 +216,13 @@ + /*NOTREACHED*/ + } + ++#ifdef CONFIG_USE_IRQ ++void s3c2410_irq(void) ++{ ++ S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT(); ++ u_int32_t intpnd = irq->INTPND; ++ ++} ++#endif /* USE_IRQ */ ++ + #endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ +Index: u-boot.git/include/common.h +=================================================================== +--- u-boot.git.orig/include/common.h 2007-02-05 22:49:11.000000000 +0100 ++++ u-boot.git/include/common.h 2007-02-05 23:19:01.000000000 +0100 +@@ -452,6 +452,8 @@ + ulong get_PCI_freq (void); + #endif + #if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_LH7A40X) ++void s3c2410_irq(void); ++#define ARM920_IRQ_CALLBACK s3c2410_irq + ulong get_FCLK (void); + ulong get_HCLK (void); + ulong get_PCLK (void); diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-arm920t-gd_in_irq.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-arm920t-gd_in_irq.patch new file mode 100644 index 0000000000..b3d7bc1166 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-arm920t-gd_in_irq.patch @@ -0,0 +1,28 @@ +This patch allows us to use the 'gd' pointer (and thus environment +and everything else associated with it) from interrupt context on +arm920t. + +Signed-off-by: Harald Welte + +Index: u-boot/cpu/arm920t/start.S +=================================================================== +--- u-boot.orig/cpu/arm920t/start.S 2007-02-24 02:35:38.000000000 +0100 ++++ u-boot/cpu/arm920t/start.S 2007-02-24 02:36:01.000000000 +0100 +@@ -474,12 +474,12 @@ + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 +- add r8, sp, #S_PC +- stmdb r8, {sp, lr}^ @ Calling SP, LR +- str lr, [r8, #0] @ Save calling PC ++ add r7, sp, #S_PC ++ stmdb r7, {sp, lr}^ @ Calling SP, LR ++ str lr, [r7, #0] @ Save calling PC + mrs r6, spsr +- str r6, [r8, #4] @ Save CPSR +- str r0, [r8, #8] @ Save OLD_R0 ++ str r6, [r7, #4] @ Save CPSR ++ str r0, [r7, #8] @ Save OLD_R0 + mov r0, sp + .endm + diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-bbt-quiet.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-bbt-quiet.patch new file mode 100644 index 0000000000..9b1febe956 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-bbt-quiet.patch @@ -0,0 +1,43 @@ +This patch makes the u-boot NAND BBT code a bit more quiet + +Signed-off-by: Harald Welte + +Index: u-boot/drivers/nand/nand_bbt.c +=================================================================== +--- u-boot.orig/drivers/nand/nand_bbt.c 2007-02-16 23:54:02.000000000 +0100 ++++ u-boot/drivers/nand/nand_bbt.c 2007-02-16 23:54:05.000000000 +0100 +@@ -157,10 +157,6 @@ + this->bbt[offs + (act >> 3)] |= 0x2 << (act & 0x06); + continue; + } +- /* Leave it for now, if its matured we can move this +- * message to MTD_DEBUG_LEVEL0 */ +- printk (KERN_DEBUG "nand_read_bbt: Bad block at 0x%08x\n", +- ((offs << 2) + (act >> 1)) << this->bbt_erase_shift); + /* Factory marked bad or worn out ? */ + if (tmp == 0) + this->bbt[offs + (act >> 3)] |= 0x3 << (act & 0x06); +@@ -229,14 +225,12 @@ + if (td->options & NAND_BBT_VERSION) { + nand_read_raw (mtd, buf, td->pages[0] << this->page_shift, mtd->oobblock, mtd->oobsize); + td->version[0] = buf[mtd->oobblock + td->veroffs]; +- printk (KERN_DEBUG "Bad block table at page %d, version 0x%02X\n", td->pages[0], td->version[0]); + } + + /* Read the mirror version, if available */ + if (md && (md->options & NAND_BBT_VERSION)) { + nand_read_raw (mtd, buf, md->pages[0] << this->page_shift, mtd->oobblock, mtd->oobsize); + md->version[0] = buf[mtd->oobblock + md->veroffs]; +- printk (KERN_DEBUG "Bad block table at page %d, version 0x%02X\n", md->pages[0], md->version[0]); + } + + return 1; +@@ -374,8 +368,6 @@ + for (i = 0; i < chips; i++) { + if (td->pages[i] == -1) + printk (KERN_WARNING "Bad block table not found for chip %d\n", i); +- else +- printk (KERN_DEBUG "Bad block table found at page %d, version 0x%02X\n", td->pages[i], td->version[i]); + } + return 0; + } diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-cmd_s3c2410.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-cmd_s3c2410.patch new file mode 100644 index 0000000000..993ef4f6f2 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-cmd_s3c2410.patch @@ -0,0 +1,175 @@ +This patch adds a new 's3c2410' command which currently supports 's3c2410 speed +{set,get,list} and thus allows dynamic change of the CPU clock. + +Signed-off-by: Harald Welte + +Index: u-boot/cpu/arm920t/s3c24x0/Makefile +=================================================================== +--- u-boot.orig/cpu/arm920t/s3c24x0/Makefile 2007-02-24 15:14:00.000000000 +0100 ++++ u-boot/cpu/arm920t/s3c24x0/Makefile 2007-02-24 15:21:02.000000000 +0100 +@@ -26,7 +26,7 @@ + LIB = $(obj)lib$(SOC).a + + COBJS = i2c.o interrupts.o serial.o speed.o \ +- usb_ohci.o nand_read.o nand.o ++ usb_ohci.o nand_read.o nand.o cmd_s3c2410.o + + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) + OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +Index: u-boot/cpu/arm920t/s3c24x0/cmd_s3c2410.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ u-boot/cpu/arm920t/s3c24x0/cmd_s3c2410.c 2007-02-24 15:22:17.000000000 +0100 +@@ -0,0 +1,152 @@ ++/* ++ * (C) Copyright 2006 by OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* ++ * Boot support ++ */ ++#include ++#include ++#include /* for print_IPaddr */ ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#if (CONFIG_COMMANDS & CFG_CMD_BDI) ++ ++#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) ++#define MHZ 1000000 ++ ++static void print_cpu_speed(void) ++{ ++ printf("FCLK = %u MHz, HCLK = %u MHz, PCLK = %u MHz\n", ++ get_FCLK()/MHZ, get_HCLK()/MHZ, get_PCLK()/MHZ); ++} ++ ++struct s3c2410_pll_speed { ++ u_int16_t mhz; ++ u_int32_t mpllcon; ++ u_int32_t clkdivn; ++}; ++ ++#define CLKDIVN_1_1_1 0x00 ++#define CLKDIVN_1_2_2 0x02 ++#define CLKDIVN_1_2_4 0x03 ++#define CLKDIVN_1_4_4 0x04 ++ ++static const struct s3c2410_pll_speed pll_configs[] = { ++ { ++ .mhz = 50, ++ .mpllcon = ((0x5c << 12) + (0x4 << 4) + 0x2), ++ .clkdivn = CLKDIVN_1_1_1, ++ }, ++ { ++ .mhz = 101, ++ .mpllcon = ((0x7f << 12) + (0x2 << 4) + 0x2), ++ .clkdivn = CLKDIVN_1_2_2, ++ }, ++ { ++ .mhz = 202, ++ .mpllcon = ((0x90 << 12) + (0x7 << 4) + 0x0), ++ .clkdivn = CLKDIVN_1_2_4, ++ }, ++ { ++ .mhz = 266, ++ .mpllcon = ((0x7d << 12) + (0x1 << 4) + 0x1), ++ .clkdivn = CLKDIVN_1_2_4, ++ }, ++}; ++ ++static void list_cpu_speeds(void) ++{ ++ int i; ++ for (i = 0; i < ARRAY_SIZE(pll_configs); i++) ++ printf("%u MHz\n", pll_configs[i].mhz); ++} ++ ++static int reconfig_mpll(u_int16_t mhz) ++{ ++ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(pll_configs); i++) { ++ if (pll_configs[i].mhz == mhz) { ++ /* to reduce PLL lock time, adjust the LOCKTIME register */ ++ clk_power->LOCKTIME = 0xFFFFFF; ++ ++ /* configure MPLL */ ++ clk_power->MPLLCON = pll_configs[i].mpllcon; ++ clk_power->UPLLCON = ((0x78 << 12) + (0x2 << 4) + 0x3), ++ clk_power->CLKDIVN = pll_configs[i].clkdivn; ++ ++ /* If we changed the speed, we need to re-configure ++ * the serial baud rate generator */ ++ serial_setbrg(); ++ return 0; ++ } ++ } ++ return -1; ++} ++ ++int do_s3c2410 ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ++{ ++ if (!strcmp(argv[1], "speed")) { ++ if (argc < 2) ++ goto out_help; ++ if (!strcmp(argv[2], "get")) ++ print_cpu_speed(); ++ else if (!strcmp(argv[2], "list")) ++ list_cpu_speeds(); ++ else if (!strcmp(argv[2], "set")) { ++ unsigned long mhz; ++ if (argc < 3) ++ goto out_help; ++ ++ mhz = simple_strtoul(argv[3], NULL, 10); ++ ++ if (reconfig_mpll(mhz) < 0) ++ printf("error, speed %uMHz unknown\n", mhz); ++ else ++ print_cpu_speed(); ++ } else ++ goto out_help; ++ } else { ++out_help: ++ printf("Usage:\n%s\n", cmdtp->usage); ++ return 1; ++ } ++ ++ return 0; ++} ++ ++/* -------------------------------------------------------------------- */ ++ ++ ++U_BOOT_CMD( ++ s3c2410, 4, 1, do_s3c2410, ++ "s3c2410 - SoC specific commands\n", ++ "speed get - display current PLL speed config\n" ++ "s3c2410 speed list - display supporte PLL speed configs\n" ++ "s3c2410 speed set - set PLL speed\n" ++); ++ ++#endif diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-cramfs_but_no_jffs2.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-cramfs_but_no_jffs2.patch new file mode 100644 index 0000000000..349b83697e --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-cramfs_but_no_jffs2.patch @@ -0,0 +1,41 @@ +Fix building with CRAMFS but not JFFS2 support + +Signed-off-by: Harald Welte + +Index: u-boot/fs/cramfs/cramfs.c +=================================================================== +--- u-boot.orig/fs/cramfs/cramfs.c 2007-02-17 11:46:26.000000000 +0100 ++++ u-boot/fs/cramfs/cramfs.c 2007-02-17 11:54:36.000000000 +0100 +@@ -27,7 +27,7 @@ + #include + #include + +-#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) ++#if (CONFIG_COMMANDS & CFG_CMD_CRAMFS) + + #include + #include +Index: u-boot/common/cmd_jffs2.c +=================================================================== +--- u-boot.orig/common/cmd_jffs2.c 2007-02-17 11:47:51.000000000 +0100 ++++ u-boot/common/cmd_jffs2.c 2007-02-17 14:08:25.000000000 +0100 +@@ -170,10 +170,19 @@ + static struct mtd_device *current_dev = NULL; + static u8 current_partnum = 0; + ++#ifdef CFG_CMD_CRAMFS + extern int cramfs_check (struct part_info *info); + extern int cramfs_load (char *loadoffset, struct part_info *info, char *filename); + extern int cramfs_ls (struct part_info *info, char *filename); + extern int cramfs_info (struct part_info *info); ++#else ++/* defining empty macros for function names is ugly but avoids ifdef clutter ++ * all over the code */ ++#define cramfs_check(x) (0) ++#define cramfs_load(x,y,z) (-1) ++#define cramfs_ls(x,y) (0) ++#define cramfs_info(x) (0) ++#endif + + static struct part_info* jffs2_part_info(struct mtd_device *dev, unsigned int part_num); + diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-dfu.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-dfu.patch new file mode 100644 index 0000000000..1122f4894f --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-dfu.patch @@ -0,0 +1,2081 @@ +Index: u-boot/drivers/usbdcore_ep0.c +=================================================================== +--- u-boot.orig/drivers/usbdcore_ep0.c ++++ u-boot/drivers/usbdcore_ep0.c +@@ -42,10 +42,15 @@ + */ + + #include ++DECLARE_GLOBAL_DATA_PTR; + + #if defined(CONFIG_USB_DEVICE) + #include "usbdcore.h" + ++#ifdef CONFIG_USBD_DFU ++#include ++#endif ++ + #if 0 + #define dbg_ep0(lvl,fmt,args...) serial_printf("[%s] %s:%d: "fmt"\n",__FILE__,__FUNCTION__,__LINE__,##args) + #else +@@ -213,7 +218,7 @@ + urb->buffer = device_descriptor; + urb->actual_length = MIN(sizeof(*device_descriptor), max); + } +- /*dbg_ep0(3, "copied device configuration, actual_length: %x", urb->actual_length); */ ++ dbg_ep0(3, "using device configuration, actual_length: %x", urb->actual_length); + break; + + case USB_DESCRIPTOR_TYPE_CONFIGURATION: +@@ -267,7 +272,24 @@ + return -1; + case USB_DESCRIPTOR_TYPE_ENDPOINT: + return -1; ++ /* This really means "Class Specific Descriptor #1 == USB_DT_DFU */ + case USB_DESCRIPTOR_TYPE_HID: ++#ifdef CONFIG_USBD_DFU ++ { ++ int bNumInterface = ++ le16_to_cpu(urb->device_request.wIndex); ++ ++ /* In runtime mode, we only respond to the DFU INTERFACE, ++ * whereas in DFU mode, we respond for all intrfaces */ ++ if (device->dfu_state != DFU_STATE_appIDLE && ++ device->dfu_state != DFU_STATE_appDETACH || ++ bNumInterface == CONFIG_USBD_DFU_INTERFACE) { ++ urb->buffer = &device->dfu_cfg_desc->func_dfu; ++ urb->actual_length = sizeof(struct usb_dfu_func_descriptor); ++ } else ++ return -1; ++ } ++#else /* CONFIG_USBD_DFU */ + { + return -1; /* unsupported at this time */ + #if 0 +@@ -294,6 +316,7 @@ + max); + #endif + } ++#endif /* CONFIG_USBD_DFU */ + break; + case USB_DESCRIPTOR_TYPE_REPORT: + { +@@ -388,6 +411,24 @@ + le16_to_cpu (request->wLength), + USBD_DEVICE_REQUESTS (request->bRequest)); + ++#ifdef CONFIG_USBD_DFU ++ if ((request->bmRequestType & 0x3f) == USB_TYPE_DFU && ++ (device->dfu_state != DFU_STATE_appIDLE || ++ le16_to_cpu(request->wIndex) == CONFIG_USBD_DFU_INTERFACE)) { ++ int rc = dfu_ep0_handler(urb); ++ switch (rc) { ++ case DFU_EP0_NONE: ++ case DFU_EP0_UNHANDLED: ++ break; ++ case DFU_EP0_ZLP: ++ case DFU_EP0_DATA: ++ return 0; ++ case DFU_EP0_STALL: ++ return -1; ++ } ++ } ++#endif /* CONFIG_USB_DFU */ ++ + /* handle USB Standard Request (c.f. USB Spec table 9-2) */ + if ((request->bmRequestType & USB_REQ_TYPE_MASK) != 0) { + if (device->device_state <= STATE_CONFIGURED) +@@ -570,7 +611,8 @@ + device->interface = le16_to_cpu (request->wIndex); + device->alternate = le16_to_cpu (request->wValue); + /*dbg_ep0(2, "set interface: %d alternate: %d", device->interface, device->alternate); */ +- serial_printf ("DEVICE_SET_INTERFACE.. event?\n"); ++ usbd_device_event_irq(device, DEVICE_SET_INTERFACE, ++ (request->wIndex << 16 | request->wValue)); + return 0; + + case USB_REQ_GET_STATUS: +Index: u-boot/drivers/usbdfu.c +=================================================================== +--- /dev/null ++++ u-boot/drivers/usbdfu.c +@@ -0,0 +1,1069 @@ ++/* ++ * (C) 2007 by OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * based on existing SAM7DFU code from OpenPCD: ++ * (C) Copyright 2006 by Harald Welte ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ * TODO: ++ * - make NAND support reasonably self-contained and put in apropriate ++ * ifdefs ++ * - add some means of synchronization, i.e. block commandline access ++ * while DFU transfer is in progress, and return to commandline once ++ * we're finished ++ * - add VERIFY support after writing to flash ++ * - sanely free() resources allocated during first uppload/download ++ * request when aborting ++ * - sanely free resources when another alternate interface is selected ++ * ++ * Maybe: ++ * - add something like uImage or some other header that provides CRC ++ * checking? ++ * - make 'dnstate' attached to 'struct usb_device_instance' ++ */ ++ ++#include ++#if defined(CONFIG_USBD_DFU) ++ ++#include ++DECLARE_GLOBAL_DATA_PTR; ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++int mtdparts_init(void); ++extern struct list_head devices; ++ ++#include "usbdcore_s3c2410.h" ++#include "usbtty.h" /* for STR_* defs */ ++ ++#define RET_NOTHING 0 ++#define RET_ZLP 1 ++#define RET_STALL 2 ++ ++volatile enum dfu_state *system_dfu_state; /* for 3rd parties */ ++ ++ ++struct dnload_state { ++ nand_info_t *nand; ++ struct part_info *part; ++ unsigned int part_net_size; /* net sizee (excl. bad blocks) of part */ ++ ++ nand_erase_options_t erase_opts; ++ nand_write_options_t write_opts; ++ nand_read_options_t read_opts; ++ ++ unsigned char *ptr; /* pointer to next empty byte in buffer */ ++ unsigned int off; /* offset of current erase page in flash chip */ ++ unsigned char *buf; /* pointer to allocated erase page buffer */ ++ ++ /* unless doing an atomic transfer, we use the static buffer below. ++ * This saves us from having to clean up dynamic allications in the ++ * various error paths of the code. Also, it will always work, no ++ * matter what the memory situation is. */ ++ unsigned char _buf[0x20000]; /* FIXME: depends flash page size */ ++}; ++ ++static struct dnload_state _dnstate; ++ ++static int dfu_trailer_matching(const struct uboot_dfu_trailer *trailer) ++{ ++ if (trailer->magic != UBOOT_DFU_TRAILER_MAGIC || ++ trailer->version != UBOOT_DFU_TRAILER_V1 || ++ trailer->vendor != CONFIG_USBD_VENDORID || ++ (trailer->product != CONFIG_USBD_PRODUCTID_CDCACM && ++ trailer->product != CONFIG_USBD_PRODUCTID_GSERIAL)) ++ return 0; ++#ifdef CONFIG_REVISION_TAG ++ if (trailer->revision != get_board_rev()) ++ return 0; ++#endif ++ ++ return 1; ++} ++ ++static struct part_info *get_partition_nand(int idx) ++{ ++ struct mtd_device *dev; ++ struct part_info *part; ++ struct list_head *pentry; ++ int i; ++ ++ if (mtdparts_init()) ++ return NULL; ++ if (list_empty(&devices)) ++ return NULL; ++ ++ dev = list_entry(devices.next, struct mtd_device, link); ++ i = 0; ++ list_for_each(pentry, &dev->parts) { ++ if (i == idx) { ++ part = list_entry(pentry, struct part_info, link); ++ return part; ++ } ++ i++; ++ } ++ ++ return NULL; ++} ++ ++#define LOAD_ADDR ((unsigned char *)0x32000000) ++ ++static int initialize_ds_nand(struct usb_device_instance *dev, struct dnload_state *ds) ++{ ++ ds->part = get_partition_nand(dev->alternate - 1); ++ if (!ds->part) { ++ printf("DFU: unable to find partition %u\b", dev->alternate-1); ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ dev->dfu_status = DFU_STATUS_errADDRESS; ++ return RET_STALL; ++ } ++ ds->nand = &nand_info[ds->part->dev->id->num]; ++ ds->off = ds->part->offset; ++ ds->part_net_size = nand_net_part_size(ds->part); ++ ++ if (ds->nand->erasesize > sizeof(ds->_buf)) { ++ printf("*** Warning - NAND ERASESIZE bigger than static buffer\n"); ++ ds->buf = malloc(ds->nand->erasesize); ++ if (!ds->buf) { ++ printf("DFU: can't allocate %u bytes\n", ds->nand->erasesize); ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ dev->dfu_status = DFU_STATUS_errADDRESS; ++ return RET_STALL; ++ } ++ } else ++ ds->buf = ds->_buf; ++ ++ ds->ptr = ds->buf; ++ ++ memset(&ds->read_opts, 0, sizeof(ds->read_opts)); ++ ++ memset(&ds->erase_opts, 0, sizeof(ds->erase_opts)); ++ ds->erase_opts.quiet = 1; ++ /* FIXME: do this more dynamic */ ++ if (!strcmp(ds->part->name, "rootfs")) ++ ds->erase_opts.jffs2 = 1; ++ ++ memset(&ds->write_opts, 0, sizeof(ds->write_opts)); ++ ds->write_opts.pad = 1; ++ ds->write_opts.blockalign = 1; ++ ds->write_opts.quiet = 1; ++ ++ debug("initialize_ds_nand(dev=%p, ds=%p): ", dev, ds); ++ debug("nand=%p, ptr=%p, buf=%p, off=0x%x\n", ds->nand, ds->ptr, ds->buf, ds->off); ++ ++ return RET_NOTHING; ++} ++ ++static int erase_flash_verify_nand(struct urb *urb, struct dnload_state *ds, ++ unsigned long erasesize, unsigned long size) ++{ ++ struct usb_device_instance *dev = urb->device; ++ int rc; ++ ++ debug("erase_flash_verify_nand(urb=%p, ds=%p, erase=0x%x size=0x%x)\n", ++ urb, ds, erasesize, size); ++ ++ if (erasesize == ds->nand->erasesize) { ++ /* we're only writing a single block and need to ++ * do bad block skipping / offset adjustments our own */ ++ while (ds->nand->block_isbad(ds->nand, ds->off)) { ++ debug("SKIP_ONE_BLOCK(0x%08x)!!\n", ds->off); ++ ds->off += ds->nand->erasesize; ++ } ++ } ++ ++ /* we have finished one eraseblock, flash it */ ++ ds->erase_opts.offset = ds->off; ++ ds->erase_opts.length = erasesize; ++ debug("Erasing 0x%x bytes @ offset 0x%x (jffs=%u)\n", ++ ds->erase_opts.length, ds->erase_opts.offset, ++ ds->erase_opts.jffs2); ++ rc = nand_erase_opts(ds->nand, &ds->erase_opts); ++ if (rc) { ++ debug("Error erasing\n"); ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ dev->dfu_status = DFU_STATUS_errERASE; ++ return RET_STALL; ++ } ++ ++ ds->write_opts.buffer = ds->buf; ++ ds->write_opts.length = size; ++ ds->write_opts.offset = ds->off; ++ debug("Writing 0x%x bytes @ offset 0x%x\n", size, ds->off); ++ rc = nand_write_opts(ds->nand, &ds->write_opts); ++ if (rc) { ++ debug("Error writing\n"); ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ dev->dfu_status = DFU_STATUS_errWRITE; ++ return RET_STALL; ++ } ++ ++ ds->off += size; ++ ds->ptr = ds->buf; ++ ++ /* FIXME: implement verify! */ ++ return RET_NOTHING; ++} ++ ++static int erase_tail_clean_nand(struct urb *urb, struct dnload_state *ds) ++{ ++ struct usb_device_instance *dev = urb->device; ++ int rc; ++ ++ ds->erase_opts.offset = ds->off; ++ ds->erase_opts.length = ds->part->size-ds->off; ++ debug("Erasing 0x%x bytes @ offset 0x%x (jffs=%u)\n", ++ ds->erase_opts.length, ds->erase_opts.offset, ++ ds->erase_opts.jffs2); ++ rc = nand_erase_opts(ds->nand, &ds->erase_opts); ++ if (rc) { ++ debug("Error erasing\n"); ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ dev->dfu_status = DFU_STATUS_errERASE; ++ return RET_STALL; ++ } ++ ++ ds->off += ds->part->size; /* for consistency */ ++ ++ return RET_NOTHING; ++} ++ ++/* Read the next erase blcok from NAND into buffer */ ++static int read_next_nand(struct urb *urb, struct dnload_state *ds) ++{ ++ struct usb_device_instance *dev = urb->device; ++ int rc; ++ ++ ds->read_opts.buffer = ds->buf; ++ ds->read_opts.length = ds->nand->erasesize; ++ ds->read_opts.offset = ds->off; ++ ds->read_opts.quiet = 1; ++ ++ debug("Reading 0x%x@0x%x to 0x%08p\n", ds->nand->erasesize, ++ ds->off, ds->buf); ++ rc = nand_read_opts(ds->nand, &ds->read_opts); ++ if (rc) { ++ debug("Error reading\n"); ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ dev->dfu_status = DFU_STATUS_errWRITE; ++ return RET_STALL; ++ } ++ ds->off += ds->nand->erasesize; ++ ds->ptr = ds->buf; ++ ++ return RET_NOTHING; ++} ++ ++ ++static int handle_dnload(struct urb *urb, u_int16_t val, u_int16_t len, int first) ++{ ++ struct usb_device_instance *dev = urb->device; ++ struct dnload_state *ds = &_dnstate; ++ unsigned int actual_len = len; ++ unsigned int remain_len; ++ unsigned long size; ++ int rc; ++ ++ debug("download(len=%u, first=%u) ", len, first); ++ ++ if (len > CONFIG_USBD_DFU_XFER_SIZE) { ++ /* Too big. Not that we'd really care, but it's a ++ * DFU protocol violation */ ++ debug("length exceeds flash page size "); ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ dev->dfu_status = DFU_STATUS_errADDRESS; ++ return RET_STALL; ++ } ++ ++ if (first) { ++ /* Make sure that we have a valid mtd partition table */ ++ char *mtdp = getenv("mtdparts"); ++ if (!mtdp) ++ run_command("dynpart", 0); ++ } ++ ++ if (len == 0) { ++ debug("zero-size write -> MANIFEST_SYNC "); ++ dev->dfu_state = DFU_STATE_dfuMANIFEST_SYNC; ++ ++ /* cleanup */ ++ switch (dev->alternate) { ++ char buf[12]; ++ case 0: ++ sprintf(buf, "%lx", ds->ptr - ds->buf); ++ setenv("filesize", buf); ++ ds->ptr = ds->buf; ++ break; ++ case 1: ++ if (ds->ptr > ++ ds->buf + sizeof(struct uboot_dfu_trailer)) { ++ struct uboot_dfu_trailer trailer; ++ dfu_trailer_mirror(&trailer, ds->ptr); ++ if (!dfu_trailer_matching(&trailer)) { ++ printf("DFU TRAILER NOT OK\n"); ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ dev->dfu_status = DFU_STATUS_errTARGET; ++ return RET_STALL; ++ } ++ ++ rc = erase_flash_verify_nand(urb, ds, ++ ds->part->size, ++ ds->part_net_size); ++ /* re-write dynenv marker in OOB */ ++ run_command("dynenv set u-boot_env", 0); ++ } ++ ds->nand = NULL; ++ free(ds->buf); ++ ds->ptr = ds->buf = ds->_buf; ++ break; ++ default: ++ rc = 0; ++ if (ds->ptr > ds->buf) ++ rc = erase_flash_verify_nand(urb, ds, ++ ds->nand->erasesize, ++ ds->nand->erasesize); ++ /* rootfs partition */ ++ if (!rc && dev->alternate == 5) ++ rc = erase_tail_clean_nand(urb, ds); ++ ++ ds->nand = NULL; ++ break; ++ } ++ ++ return RET_ZLP; ++ } ++ ++ if (urb->actual_length != len) { ++ debug("urb->actual_length(%u) != len(%u) ?!? ", ++ urb->actual_length, len); ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ dev->dfu_status = DFU_STATUS_errADDRESS; ++ return RET_STALL; ++ } ++ ++ if (first && ds->buf && ds->buf != ds->_buf && ds->buf != LOAD_ADDR) { ++ free(ds->buf); ++ ds->buf = ds->_buf; ++ } ++ ++ switch (dev->alternate) { ++ case 0: ++ if (first) { ++ printf("Starting DFU DOWNLOAD to RAM (0x%08p)\n", ++ LOAD_ADDR); ++ ds->buf = LOAD_ADDR; ++ ds->ptr = ds->buf; ++ } ++ ++ memcpy(ds->ptr, urb->buffer, len); ++ ds->ptr += len; ++ break; ++ case 1: ++ if (first) { ++ rc = initialize_ds_nand(dev, ds); ++ if (rc) ++ return rc; ++ ds->buf = malloc(ds->part_net_size); ++ if (!ds->buf) { ++ printf("No memory for atomic buffer!!\n"); ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ dev->dfu_status = DFU_STATUS_errUNKNOWN; ++ return RET_STALL; ++ } ++ ds->ptr = ds->buf; ++ printf("Starting Atomic DFU DOWNLOAD to partition '%s'\n", ++ ds->part->name); ++ } ++ ++ remain_len = (ds->buf + ds->part_net_size) - ds->ptr; ++ if (remain_len < len) { ++ len = remain_len; ++ printf("End of write exceeds partition end\n"); ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ dev->dfu_status = DFU_STATUS_errADDRESS; ++ return RET_STALL; ++ } ++ memcpy(ds->ptr, urb->buffer, len); ++ ds->ptr += len; ++ break; ++ default: ++ if (first) { ++ rc = initialize_ds_nand(dev, ds); ++ if (rc) ++ return rc; ++ printf("Starting DFU DOWNLOAD to partition '%s'\n", ++ ds->part->name); ++ } ++ ++ size = ds->nand->erasesize; ++ remain_len = ds->buf + size - ds->ptr; ++ if (remain_len < len) ++ actual_len = remain_len; ++ ++ memcpy(ds->ptr, urb->buffer, actual_len); ++ ds->ptr += actual_len; ++ ++ /* check partition end */ ++ if (ds->off + (ds->ptr - ds->buf) > ds->part->offset + ds->part->size) { ++ printf("End of write exceeds partition end\n"); ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ dev->dfu_status = DFU_STATUS_errADDRESS; ++ return RET_STALL; ++ } ++ ++ if (ds->ptr >= ds->buf + size) { ++ rc = erase_flash_verify_nand(urb, ds, ++ ds->nand->erasesize, ++ ds->nand->erasesize); ++ if (rc) ++ return rc; ++ /* copy remainder of data into buffer */ ++ memcpy(ds->ptr, urb->buffer + actual_len, len - actual_len); ++ ds->ptr += (len - actual_len); ++ } ++ break; ++ } ++ ++ return RET_ZLP; ++} ++ ++static int handle_upload(struct urb *urb, u_int16_t val, u_int16_t len, int first) ++{ ++ struct usb_device_instance *dev = urb->device; ++ struct dnload_state *ds = &_dnstate; ++ unsigned int remain; ++ int rc; ++ ++ debug("upload(val=0x%02x, len=%u, first=%u) ", val, len, first); ++ ++ if (len > CONFIG_USBD_DFU_XFER_SIZE) { ++ /* Too big */ ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ dev->dfu_status = DFU_STATUS_errADDRESS; ++ //udc_ep0_send_stall(); ++ debug("Error: Transfer size > CONFIG_USBD_DFU_XFER_SIZE "); ++ return -EINVAL; ++ } ++ ++ switch (dev->alternate) { ++ case 0: ++ if (first) { ++ printf("Starting DFU Upload of RAM (0x%08p)\n", ++ LOAD_ADDR); ++ ds->ptr = ds->buf; ++ } ++ ++ /* FIXME: end at some more dynamic point */ ++ if (ds->ptr + len > LOAD_ADDR + 0x200000) ++ len = (LOAD_ADDR + 0x200000) - ds->ptr; ++ ++ urb->buffer = ds->ptr; ++ urb->actual_length = len; ++ ds->ptr += len; ++ break; ++ default: ++ if (first) { ++ rc = initialize_ds_nand(dev, ds); ++ if (rc) ++ return -EINVAL; ++ printf("Starting DFU Upload of partition '%s'\n", ++ ds->part->name); ++ rc = read_next_nand(urb, ds); ++ if (rc) ++ return -EINVAL; ++ } ++ ++ if (len > ds->nand->erasesize) { ++ printf("We don't support transfers bigger than %u\n", ++ ds->nand->erasesize); ++ len = ds->nand->erasesize; ++ } ++ ++ remain = ds->nand->erasesize - (ds->ptr - ds->buf); ++ if (len < remain) ++ remain = len; ++ ++ debug("copying %u bytes ", remain); ++ urb->buffer = ds->ptr; ++ ds->ptr += remain; ++ urb->actual_length = remain; ++ ++ if (ds->ptr >= ds->buf + ds->nand->erasesize && ++ ds->off < ds->part->offset + ds->part->size) { ++ rc = read_next_nand(urb, ds); ++ if (rc) ++ return -EINVAL; ++ if (len > remain) { ++ debug("copying another %u bytes ", len - remain); ++ memcpy(urb->buffer + remain, ds->ptr, len - remain); ++ ds->ptr += (len - remain); ++ urb->actual_length += (len - remain); ++ } ++ } ++ break; ++ } ++ ++ debug("returning len=%u\n", len); ++ return len; ++} ++ ++static void handle_getstatus(struct urb *urb, int max) ++{ ++ struct usb_device_instance *dev = urb->device; ++ struct dfu_status *dstat = (struct dfu_status *) urb->buffer; ++ ++ debug("getstatus "); ++ ++ if (!urb->buffer || urb->buffer_length < sizeof(*dstat)) { ++ debug("invalid urb! "); ++ return; ++ } ++ ++ switch (dev->dfu_state) { ++ case DFU_STATE_dfuDNLOAD_SYNC: ++ case DFU_STATE_dfuDNBUSY: ++#if 0 ++ if (fsr & AT91C_MC_PROGE) { ++ debug("errPROG "); ++ dev->dfu_status = DFU_STATUS_errPROG; ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ } else if (fsr & AT91C_MC_LOCKE) { ++ debug("errWRITE "); ++ dev->dfu_status = DFU_STATUS_errWRITE; ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ } else if (fsr & AT91C_MC_FRDY) { ++#endif ++ debug("DNLOAD_IDLE "); ++ dev->dfu_state = DFU_STATE_dfuDNLOAD_IDLE; ++#if 0 ++ } else { ++ debug("DNBUSY "); ++ dev->dfu_state = DFU_STATE_dfuDNBUSY; ++ } ++#endif ++ break; ++ case DFU_STATE_dfuMANIFEST_SYNC: ++ break; ++ default: ++ //return; ++ break; ++ } ++ ++ /* send status response */ ++ dstat->bStatus = dev->dfu_status; ++ dstat->bState = dev->dfu_state; ++ dstat->iString = 0; ++ /* FIXME: set dstat->bwPollTimeout */ ++ urb->actual_length = MIN(sizeof(*dstat), max); ++ ++ /* we don't need to explicitly send data here, will ++ * be done by the original caller! */ ++} ++ ++static void handle_getstate(struct urb *urb, int max) ++{ ++ debug("getstate "); ++ ++ if (!urb->buffer || urb->buffer_length < sizeof(u_int8_t)) { ++ debug("invalid urb! "); ++ return; ++ } ++ ++ urb->buffer[0] = urb->device->dfu_state & 0xff; ++ urb->actual_length = sizeof(u_int8_t); ++} ++ ++#ifndef CONFIG_USBD_PRODUCTID_DFU ++#define CONFIG_USBD_PRODUCTID_DFU CONFIG_USBD_PRODUCTID_CDCACM ++#endif ++ ++static const struct usb_device_descriptor dfu_dev_descriptor = { ++ .bLength = USB_DT_DEVICE_SIZE, ++ .bDescriptorType = USB_DT_DEVICE, ++ .bcdUSB = 0x0100, ++ .bDeviceClass = 0x00, ++ .bDeviceSubClass = 0x00, ++ .bDeviceProtocol = 0x00, ++ .bMaxPacketSize0 = EP0_MAX_PACKET_SIZE, ++ .idVendor = CONFIG_USBD_VENDORID, ++ .idProduct = CONFIG_USBD_PRODUCTID_DFU, ++ .bcdDevice = 0x0000, ++ .iManufacturer = DFU_STR_MANUFACTURER, ++ .iProduct = DFU_STR_PRODUCT, ++ .iSerialNumber = DFU_STR_SERIAL, ++ .bNumConfigurations = 0x01, ++}; ++ ++static const struct _dfu_desc dfu_cfg_descriptor = { ++ .ucfg = { ++ .bLength = USB_DT_CONFIG_SIZE, ++ .bDescriptorType = USB_DT_CONFIG, ++ .wTotalLength = USB_DT_CONFIG_SIZE + ++ DFU_NUM_ALTERNATES * USB_DT_INTERFACE_SIZE + ++ USB_DT_DFU_SIZE, ++ .bNumInterfaces = 5, ++ .bConfigurationValue = 1, ++ .iConfiguration = DFU_STR_CONFIG, ++ .bmAttributes = BMATTRIBUTE_RESERVED, ++ .bMaxPower = 50, ++ }, ++ .uif[0] = { ++ .bLength = USB_DT_INTERFACE_SIZE, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = 0x00, ++ .bAlternateSetting = 0x00, ++ .bNumEndpoints = 0x00, ++ .bInterfaceClass = 0xfe, ++ .bInterfaceSubClass = 0x01, ++ .bInterfaceProtocol = 0x02, ++ .iInterface = DFU_STR_ALT0, ++ }, ++ .uif[1] = { ++ .bLength = USB_DT_INTERFACE_SIZE, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = 0x00, ++ .bAlternateSetting = 0x01, ++ .bNumEndpoints = 0x00, ++ .bInterfaceClass = 0xfe, ++ .bInterfaceSubClass = 0x01, ++ .bInterfaceProtocol = 0x02, ++ .iInterface = DFU_STR_ALT1, ++ }, ++ .uif[2] = { ++ .bLength = USB_DT_INTERFACE_SIZE, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = 0x00, ++ .bAlternateSetting = 0x02, ++ .bNumEndpoints = 0x00, ++ .bInterfaceClass = 0xfe, ++ .bInterfaceSubClass = 0x01, ++ .bInterfaceProtocol = 0x02, ++ .iInterface = DFU_STR_ALT2, ++ }, ++ .uif[3] = { ++ .bLength = USB_DT_INTERFACE_SIZE, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = 0x00, ++ .bAlternateSetting = 0x03, ++ .bNumEndpoints = 0x00, ++ .bInterfaceClass = 0xfe, ++ .bInterfaceSubClass = 0x01, ++ .bInterfaceProtocol = 0x02, ++ .iInterface = DFU_STR_ALT3, ++ }, ++ .uif[4] = { ++ .bLength = USB_DT_INTERFACE_SIZE, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = 0x00, ++ .bAlternateSetting = 0x04, ++ .bNumEndpoints = 0x00, ++ .bInterfaceClass = 0xfe, ++ .bInterfaceSubClass = 0x01, ++ .bInterfaceProtocol = 0x02, ++ .iInterface = DFU_STR_ALT4, ++ }, ++ .uif[5] = { ++ .bLength = USB_DT_INTERFACE_SIZE, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = 0x00, ++ .bAlternateSetting = 0x05, ++ .bNumEndpoints = 0x00, ++ .bInterfaceClass = 0xfe, ++ .bInterfaceSubClass = 0x01, ++ .bInterfaceProtocol = 0x02, ++ .iInterface = DFU_STR_ALT5, ++ }, ++ .func_dfu = DFU_FUNC_DESC, ++}; ++ ++int dfu_ep0_handler(struct urb *urb) ++{ ++ int rc, ret = RET_NOTHING; ++ u_int8_t req = urb->device_request.bRequest; ++ u_int16_t val = urb->device_request.wValue; ++ u_int16_t len = urb->device_request.wLength; ++ struct usb_device_instance *dev = urb->device; ++ ++ debug("dfu_ep0(req=0x%x, val=0x%x, len=%u) old_state = %u ", ++ req, val, len, dev->dfu_state); ++ ++ switch (dev->dfu_state) { ++ case DFU_STATE_appIDLE: ++ switch (req) { ++ case USB_REQ_DFU_GETSTATUS: ++ handle_getstatus(urb, len); ++ break; ++ case USB_REQ_DFU_GETSTATE: ++ handle_getstate(urb, len); ++ break; ++ case USB_REQ_DFU_DETACH: ++ dev->dfu_state = DFU_STATE_appDETACH; ++ ret = RET_ZLP; ++ goto out; ++ break; ++ default: ++ ret = RET_STALL; ++ } ++ break; ++ case DFU_STATE_appDETACH: ++ switch (req) { ++ case USB_REQ_DFU_GETSTATUS: ++ handle_getstatus(urb, len); ++ break; ++ case USB_REQ_DFU_GETSTATE: ++ handle_getstate(urb, len); ++ break; ++ default: ++ dev->dfu_state = DFU_STATE_appIDLE; ++ ret = RET_STALL; ++ goto out; ++ break; ++ } ++ /* FIXME: implement timer to return to appIDLE */ ++ break; ++ case DFU_STATE_dfuIDLE: ++ switch (req) { ++ case USB_REQ_DFU_DNLOAD: ++ if (len == 0) { ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ ret = RET_STALL; ++ goto out; ++ } ++ dev->dfu_state = DFU_STATE_dfuDNLOAD_SYNC; ++ ret = handle_dnload(urb, val, len, 1); ++ break; ++ case USB_REQ_DFU_UPLOAD: ++ dev->dfu_state = DFU_STATE_dfuUPLOAD_IDLE; ++ handle_upload(urb, val, len, 1); ++ break; ++ case USB_REQ_DFU_ABORT: ++ /* no zlp? */ ++ ret = RET_ZLP; ++ break; ++ case USB_REQ_DFU_GETSTATUS: ++ handle_getstatus(urb, len); ++ break; ++ case USB_REQ_DFU_GETSTATE: ++ handle_getstate(urb, len); ++ break; ++ case USB_REQ_DFU_DETACH: ++ /* Proprietary extension: 'detach' from idle mode and ++ * get back to runtime mode in case of USB Reset. As ++ * much as I dislike this, we just can't use every USB ++ * bus reset to switch back to runtime mode, since at ++ * least the Linux USB stack likes to send a number of resets ++ * in a row :( */ ++ dev->dfu_state = DFU_STATE_dfuMANIFEST_WAIT_RST; ++ break; ++ default: ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ ret = RET_STALL; ++ goto out; ++ break; ++ } ++ break; ++ case DFU_STATE_dfuDNLOAD_SYNC: ++ switch (req) { ++ case USB_REQ_DFU_GETSTATUS: ++ handle_getstatus(urb, len); ++ /* FIXME: state transition depending on block completeness */ ++ break; ++ case USB_REQ_DFU_GETSTATE: ++ handle_getstate(urb, len); ++ break; ++ default: ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ ret = RET_STALL; ++ goto out; ++ } ++ break; ++ case DFU_STATE_dfuDNBUSY: ++ switch (req) { ++ case USB_REQ_DFU_GETSTATUS: ++ /* FIXME: only accept getstatus if bwPollTimeout ++ * has elapsed */ ++ handle_getstatus(urb, len); ++ break; ++ default: ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ ret = RET_STALL; ++ goto out; ++ } ++ break; ++ case DFU_STATE_dfuDNLOAD_IDLE: ++ switch (req) { ++ case USB_REQ_DFU_DNLOAD: ++ dev->dfu_state = DFU_STATE_dfuDNLOAD_SYNC; ++ ret = handle_dnload(urb, val, len, 0); ++ break; ++ case USB_REQ_DFU_ABORT: ++ dev->dfu_state = DFU_STATE_dfuIDLE; ++ ret = RET_ZLP; ++ break; ++ case USB_REQ_DFU_GETSTATUS: ++ handle_getstatus(urb, len); ++ break; ++ case USB_REQ_DFU_GETSTATE: ++ handle_getstate(urb, len); ++ break; ++ default: ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ ret = RET_STALL; ++ break; ++ } ++ break; ++ case DFU_STATE_dfuMANIFEST_SYNC: ++ switch (req) { ++ case USB_REQ_DFU_GETSTATUS: ++ /* We're MainfestationTolerant */ ++ dev->dfu_state = DFU_STATE_dfuIDLE; ++ handle_getstatus(urb, len); ++ break; ++ case USB_REQ_DFU_GETSTATE: ++ handle_getstate(urb, len); ++ break; ++ default: ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ ret = RET_STALL; ++ break; ++ } ++ break; ++ case DFU_STATE_dfuMANIFEST: ++ /* we should never go here */ ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ ret = RET_STALL; ++ break; ++ case DFU_STATE_dfuMANIFEST_WAIT_RST: ++ /* we should never go here */ ++ break; ++ case DFU_STATE_dfuUPLOAD_IDLE: ++ switch (req) { ++ case USB_REQ_DFU_UPLOAD: ++ /* state transition if less data then requested */ ++ rc = handle_upload(urb, val, len, 0); ++ if (rc >= 0 && rc < len) ++ dev->dfu_state = DFU_STATE_dfuIDLE; ++ break; ++ case USB_REQ_DFU_ABORT: ++ dev->dfu_state = DFU_STATE_dfuIDLE; ++ /* no zlp? */ ++ ret = RET_ZLP; ++ break; ++ case USB_REQ_DFU_GETSTATUS: ++ handle_getstatus(urb, len); ++ break; ++ case USB_REQ_DFU_GETSTATE: ++ handle_getstate(urb, len); ++ break; ++ default: ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ ret = RET_STALL; ++ break; ++ } ++ break; ++ case DFU_STATE_dfuERROR: ++ switch (req) { ++ case USB_REQ_DFU_GETSTATUS: ++ handle_getstatus(urb, len); ++ break; ++ case USB_REQ_DFU_GETSTATE: ++ handle_getstate(urb, len); ++ break; ++ case USB_REQ_DFU_CLRSTATUS: ++ dev->dfu_state = DFU_STATE_dfuIDLE; ++ dev->dfu_status = DFU_STATUS_OK; ++ /* no zlp? */ ++ ret = RET_ZLP; ++ break; ++ default: ++ dev->dfu_state = DFU_STATE_dfuERROR; ++ ret = RET_STALL; ++ break; ++ } ++ break; ++ default: ++ return DFU_EP0_UNHANDLED; ++ break; ++ } ++ ++out: ++ debug("new_state = %u, ret = %u\n", dev->dfu_state, ret); ++ ++ switch (ret) { ++ case RET_ZLP: ++ //udc_ep0_send_zlp(); ++ urb->actual_length = 0; ++ return DFU_EP0_ZLP; ++ break; ++ case RET_STALL: ++ //udc_ep0_send_stall(); ++ return DFU_EP0_STALL; ++ break; ++ case RET_NOTHING: ++ break; ++ } ++ ++ return DFU_EP0_DATA; ++} ++ ++void str2wide (char *str, u16 * wide); ++static struct usb_string_descriptor *create_usbstring(char *string) ++{ ++ struct usb_string_descriptor *strdesc; ++ int size = sizeof(*strdesc) + strlen(string)*2; ++ ++ if (size > 255) ++ return NULL; ++ ++ strdesc = malloc(size); ++ if (!strdesc) ++ return NULL; ++ ++ strdesc->bLength = size; ++ strdesc->bDescriptorType = USB_DT_STRING; ++ str2wide(string, strdesc->wData); ++ ++ return strdesc; ++} ++ ++ ++static void dfu_init_strings(struct usb_device_instance *dev) ++{ ++ int i; ++ struct usb_string_descriptor *strdesc; ++ ++ strdesc = create_usbstring(CONFIG_DFU_CFG_STR); ++ usb_strings[DFU_STR_CONFIG] = strdesc; ++ ++ for (i = 0; i < DFU_NUM_ALTERNATES; i++) { ++ if (i == 0) { ++ strdesc = create_usbstring(CONFIG_DFU_ALT0_STR); ++ } else { ++ struct part_info *part = get_partition_nand(i-1); ++ ++ if (part) ++ strdesc = create_usbstring(part->name); ++ else ++ strdesc = ++ create_usbstring("undefined partition"); ++ } ++ if (!strdesc) ++ continue; ++ usb_strings[STR_COUNT+i+1] = strdesc; ++ } ++} ++ ++int dfu_init_instance(struct usb_device_instance *dev) ++{ ++ dev->dfu_dev_desc = &dfu_dev_descriptor; ++ dev->dfu_cfg_desc = &dfu_cfg_descriptor; ++ dev->dfu_state = DFU_STATE_appIDLE; ++ dev->dfu_status = DFU_STATUS_OK; ++ ++ if (system_dfu_state) ++ printf("SURPRISE: system_dfu_state is already set\n"); ++ system_dfu_state = &dev->dfu_state; ++ ++ dfu_init_strings(dev); ++ ++ return 0; ++} ++ ++static int stdout_switched; ++ ++/* event handler for usb device state events */ ++void dfu_event(struct usb_device_instance *device, ++ usb_device_event_t event, int data) ++{ ++ char *out; ++ ++ switch (event) { ++ case DEVICE_RESET: ++ switch (device->dfu_state) { ++ case DFU_STATE_appDETACH: ++ device->dfu_state = DFU_STATE_dfuIDLE; ++ out = getenv("stdout"); ++ if (out && !strcmp(out, "usbtty")) { ++ setenv("stdout", "vga"); ++ setenv("stderr", "vga"); ++ stdout_switched = 1; ++ } ++ printf("DFU: Switching to DFU Mode\n"); ++ break; ++ case DFU_STATE_dfuMANIFEST_WAIT_RST: ++ device->dfu_state = DFU_STATE_appIDLE; ++ printf("DFU: Switching back to Runtime mode\n"); ++ if (stdout_switched) { ++ setenv("stdout", "usbtty"); ++ setenv("stderr", "usbtty"); ++ stdout_switched = 0; ++ } ++ break; ++ default: ++ break; ++ } ++ break; ++ case DEVICE_CONFIGURED: ++ case DEVICE_DE_CONFIGURED: ++ debug("SET_CONFIGURATION(%u) ", device->configuration); ++ /* fallthrough */ ++ case DEVICE_SET_INTERFACE: ++ debug("SET_INTERFACE(%u,%u) old_state = %u ", ++ device->interface, device->alternate, ++ device->dfu_state); ++ switch (device->dfu_state) { ++ case DFU_STATE_appIDLE: ++ case DFU_STATE_appDETACH: ++ case DFU_STATE_dfuIDLE: ++ case DFU_STATE_dfuMANIFEST_WAIT_RST: ++ /* do nothing, we're fine */ ++ break; ++ case DFU_STATE_dfuDNLOAD_SYNC: ++ case DFU_STATE_dfuDNBUSY: ++ case DFU_STATE_dfuDNLOAD_IDLE: ++ case DFU_STATE_dfuMANIFEST: ++ device->dfu_state = DFU_STATE_dfuERROR; ++ device->dfu_status = DFU_STATUS_errNOTDONE; ++ /* FIXME: free malloc()ed buffer! */ ++ break; ++ case DFU_STATE_dfuMANIFEST_SYNC: ++ case DFU_STATE_dfuUPLOAD_IDLE: ++ case DFU_STATE_dfuERROR: ++ device->dfu_state = DFU_STATE_dfuERROR; ++ device->dfu_status = DFU_STATUS_errUNKNOWN; ++ break; ++ } ++ debug("new_state = %u\n", device->dfu_state); ++ break; ++ default: ++ break; ++ } ++} ++#endif /* CONFIG_USBD_DFU */ +Index: u-boot/drivers/Makefile +=================================================================== +--- u-boot.orig/drivers/Makefile ++++ u-boot/drivers/Makefile +@@ -47,7 +47,7 @@ + status_led.o sym53c8xx.o systemace.o ahci.o \ + ti_pci1410a.o tigon3.o tsec.o \ + tsi108_eth.o tsi108_i2c.o tsi108_pci.o \ +- usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbdcore_s3c2410.o usbtty.o \ ++ usbdcore.o usbdfu.o usbdcore_ep0.o usbdcore_omap1510.o usbdcore_s3c2410.o usbtty.o \ + videomodes.o w83c553f.o \ + ks8695eth.o \ + pcf50606.o \ +Index: u-boot/drivers/usbdcore.c +=================================================================== +--- u-boot.orig/drivers/usbdcore.c ++++ u-boot/drivers/usbdcore.c +@@ -31,6 +31,7 @@ + + #include + #include "usbdcore.h" ++#include + + #define MAX_INTERFACES 2 + +@@ -212,6 +213,10 @@ + */ + struct usb_device_descriptor *usbd_device_device_descriptor (struct usb_device_instance *device, int port) + { ++#ifdef CONFIG_USBD_DFU ++ if (device->dfu_state != DFU_STATE_appIDLE) ++ return device->dfu_dev_desc; ++#endif + return (device->device_descriptor); + } + +@@ -232,6 +237,10 @@ + if (!(configuration_instance = usbd_device_configuration_instance (device, port, configuration))) { + return NULL; + } ++#ifdef CONFIG_USBD_DFU ++ if (device->dfu_state != DFU_STATE_appIDLE) ++ return (&device->dfu_cfg_desc->ucfg); ++#endif + return (configuration_instance->configuration_descriptor); + } + +@@ -253,6 +262,13 @@ + if (!(interface_instance = usbd_device_interface_instance (device, port, configuration, interface))) { + return NULL; + } ++#ifdef CONFIG_USBD_DFU ++ if (device->dfu_state != DFU_STATE_appIDLE) { ++ if (alternate < 0 || alternate >= DFU_NUM_ALTERNATES) ++ return NULL; ++ return &device->dfu_cfg_desc->uif[alternate]; ++ } ++#endif + if ((alternate < 0) || (alternate >= interface_instance->alternates)) { + return NULL; + } +@@ -681,4 +697,7 @@ + /* usbdbg("calling device->event"); */ + device->event(device, event, data); + } ++#ifdef CONFIG_USBD_DFU ++ dfu_event(device, event, data); ++#endif + } +Index: u-boot/drivers/usbtty.c +=================================================================== +--- u-boot.orig/drivers/usbtty.c ++++ u-boot/drivers/usbtty.c +@@ -31,6 +31,8 @@ + #include "usbtty.h" + #include "usb_cdc_acm.h" + #include "usbdescriptors.h" ++#include ++#include + #include /* If defined, override Linux identifiers with + * vendor specific ones */ + +@@ -118,7 +120,7 @@ + static unsigned short rx_endpoint = 0; + static unsigned short tx_endpoint = 0; + static unsigned short interface_count = 0; +-static struct usb_string_descriptor *usbtty_string_table[STR_COUNT]; ++static struct usb_string_descriptor *usbtty_string_table[NUM_STRINGS]; + + /* USB Descriptor Strings */ + static u8 wstrLang[4] = {4,USB_DT_STRING,0x9,0x4}; +@@ -169,6 +171,10 @@ + struct usb_interface_descriptor data_class_interface; + struct usb_endpoint_descriptor + data_endpoints[NUM_ENDPOINTS-1] __attribute__((packed)); ++#ifdef CONFIG_USBD_DFU ++ struct usb_interface_descriptor uif_dfu; ++ struct usb_dfu_func_descriptor func_dfu; ++#endif + } __attribute__((packed)); + + static struct acm_config_desc acm_configuration_descriptors[NUM_CONFIGS] = { +@@ -179,7 +185,11 @@ + .bDescriptorType = USB_DT_CONFIG, + .wTotalLength = + cpu_to_le16(sizeof(struct acm_config_desc)), ++#ifdef CONFIG_USBD_DFU ++ .bNumInterfaces = NUM_ACM_INTERFACES +1, ++#else + .bNumInterfaces = NUM_ACM_INTERFACES, ++#endif + .bConfigurationValue = 1, + .iConfiguration = STR_CONFIG, + .bmAttributes = +@@ -278,6 +288,11 @@ + .bInterval = 0xFF, + }, + }, ++#ifdef CONFIG_USBD_DFU ++ /* Interface 3 */ ++ .uif_dfu = DFU_RT_IF_DESC, ++ .func_dfu = DFU_FUNC_DESC, ++#endif + }, + }; + +@@ -390,7 +405,7 @@ + void usbtty_poll (void); + + /* utility function for converting char* to wide string used by USB */ +-static void str2wide (char *str, u16 * wide) ++void str2wide (char *str, u16 * wide) + { + int i; + for (i = 0; i < strlen (str) && str[i]; i++){ +@@ -652,6 +667,9 @@ + device_instance->bus = bus_instance; + device_instance->configurations = NUM_CONFIGS; + device_instance->configuration_instance_array = config_instance; ++#ifdef CONFIG_USBD_DFU ++ dfu_init_instance(device_instance); ++#endif + + /* initialize bus instance */ + memset (bus_instance, 0, sizeof (struct usb_bus_instance)); +Index: u-boot/include/configs/neo1973_gta01.h +=================================================================== +--- u-boot.orig/include/configs/neo1973_gta01.h ++++ u-boot/include/configs/neo1973_gta01.h +@@ -167,7 +167,7 @@ + */ + #define CONFIG_STACKSIZE (128*1024) /* regular stack */ + #ifdef CONFIG_USE_IRQ +-#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ ++#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */ + #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ + #endif + +@@ -184,6 +184,10 @@ + #define CONFIG_USBD_MANUFACTURER "OpenMoko, Inc" + #define CONFIG_USBD_PRODUCT_NAME "Neo1973 Bootloader " U_BOOT_VERSION + #define CONFIG_EXTRA_ENV_SETTINGS "usbtty=cdc_acm\0" ++#define CONFIG_USBD_DFU 1 ++#define CONFIG_USBD_DFU_XFER_SIZE 4096 /* 0x4000 */ ++#define CONFIG_USBD_DFU_INTERFACE 2 ++ + + /*----------------------------------------------------------------------- + * Physical Memory Map +Index: u-boot/include/usb_dfu.h +=================================================================== +--- /dev/null ++++ u-boot/include/usb_dfu.h +@@ -0,0 +1,99 @@ ++#ifndef _DFU_H ++#define _DFU_H ++ ++/* USB Device Firmware Update Implementation for u-boot ++ * (C) 2007 by OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * based on: USB Device Firmware Update Implementation for OpenPCD ++ * (C) 2006 by Harald Welte ++ * ++ * This ought to be compliant to the USB DFU Spec 1.0 as available from ++ * http://www.usb.org/developers/devclass_docs/usbdfu10.pdf ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++ ++/* USB DFU functional descriptor */ ++#define DFU_FUNC_DESC { \ ++ .bLength = USB_DT_DFU_SIZE, \ ++ .bDescriptorType = USB_DT_DFU, \ ++ .bmAttributes = USB_DFU_CAN_UPLOAD | USB_DFU_CAN_DOWNLOAD | USB_DFU_MANIFEST_TOL, \ ++ .wDetachTimeOut = 0xff00, \ ++ .wTransferSize = CONFIG_USBD_DFU_XFER_SIZE, \ ++ .bcdDFUVersion = 0x0100, \ ++} ++ ++/* USB Interface descriptor in Runtime mode */ ++#define DFU_RT_IF_DESC { \ ++ .bLength = USB_DT_INTERFACE_SIZE, \ ++ .bDescriptorType = USB_DT_INTERFACE, \ ++ .bInterfaceNumber = CONFIG_USBD_DFU_INTERFACE, \ ++ .bAlternateSetting = 0x00, \ ++ .bNumEndpoints = 0x00, \ ++ .bInterfaceClass = 0xfe, \ ++ .bInterfaceSubClass = 0x01, \ ++ .bInterfaceProtocol = 0x01, \ ++ .iInterface = DFU_STR_CONFIG, \ ++} ++ ++#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) ++ ++#define DFU_NUM_ALTERNATES 6 ++ ++#define DFU_STR_MANUFACTURER STR_MANUFACTURER ++#define DFU_STR_PRODUCT STR_PRODUCT ++#define DFU_STR_SERIAL STR_SERIAL ++#define DFU_STR_CONFIG (STR_COUNT) ++#define DFU_STR_ALT0 (STR_COUNT+1) ++#define DFU_STR_ALT1 (STR_COUNT+2) ++#define DFU_STR_ALT2 (STR_COUNT+3) ++#define DFU_STR_ALT3 (STR_COUNT+4) ++#define DFU_STR_ALT4 (STR_COUNT+5) ++#define DFU_STR_ALT5 (STR_COUNT+6) ++#define DFU_STR_COUNT (STR_COUNT+7) ++ ++#define DFU_NUM_STRINGS (STR_COUNT+8) ++ ++#define CONFIG_DFU_CFG_STR "USB Device Firmware Upgrade" ++#define CONFIG_DFU_ALT0_STR "RAM 0x32000000" ++ ++struct _dfu_desc { ++ struct usb_configuration_descriptor ucfg; ++ struct usb_interface_descriptor uif[DFU_NUM_ALTERNATES]; ++ struct usb_dfu_func_descriptor func_dfu; ++}; ++ ++int dfu_init_instance(struct usb_device_instance *dev); ++ ++#define DFU_EP0_NONE 0 ++#define DFU_EP0_UNHANDLED 1 ++#define DFU_EP0_STALL 2 ++#define DFU_EP0_ZLP 3 ++#define DFU_EP0_DATA 4 ++ ++extern volatile enum dfu_state *system_dfu_state; /* for 3rd parties */ ++ ++int dfu_ep0_handler(struct urb *urb); ++ ++void dfu_event(struct usb_device_instance *device, ++ usb_device_event_t event, int data); ++ ++#endif /* _DFU_H */ +Index: u-boot/include/usb_dfu_descriptors.h +=================================================================== +--- /dev/null ++++ u-boot/include/usb_dfu_descriptors.h +@@ -0,0 +1,94 @@ ++#ifndef _USB_DFU_H ++#define _USB_DFU_H ++/* USB Device Firmware Update Implementation for OpenPCD ++ * (C) 2006 by Harald Welte ++ * ++ * Protocol definitions for USB DFU ++ * ++ * This ought to be compliant to the USB DFU Spec 1.0 as available from ++ * http://www.usb.org/developers/devclass_docs/usbdfu10.pdf ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++ ++#define USB_DT_DFU 0x21 ++ ++struct usb_dfu_func_descriptor { ++ u_int8_t bLength; ++ u_int8_t bDescriptorType; ++ u_int8_t bmAttributes; ++#define USB_DFU_CAN_DOWNLOAD (1 << 0) ++#define USB_DFU_CAN_UPLOAD (1 << 1) ++#define USB_DFU_MANIFEST_TOL (1 << 2) ++#define USB_DFU_WILL_DETACH (1 << 3) ++ u_int16_t wDetachTimeOut; ++ u_int16_t wTransferSize; ++ u_int16_t bcdDFUVersion; ++} __attribute__ ((packed)); ++ ++#define USB_DT_DFU_SIZE 9 ++ ++#define USB_TYPE_DFU (USB_TYPE_CLASS|USB_RECIP_INTERFACE) ++ ++/* DFU class-specific requests (Section 3, DFU Rev 1.1) */ ++#define USB_REQ_DFU_DETACH 0x00 ++#define USB_REQ_DFU_DNLOAD 0x01 ++#define USB_REQ_DFU_UPLOAD 0x02 ++#define USB_REQ_DFU_GETSTATUS 0x03 ++#define USB_REQ_DFU_CLRSTATUS 0x04 ++#define USB_REQ_DFU_GETSTATE 0x05 ++#define USB_REQ_DFU_ABORT 0x06 ++ ++struct dfu_status { ++ u_int8_t bStatus; ++ u_int8_t bwPollTimeout[3]; ++ u_int8_t bState; ++ u_int8_t iString; ++} __attribute__((packed)); ++ ++#define DFU_STATUS_OK 0x00 ++#define DFU_STATUS_errTARGET 0x01 ++#define DFU_STATUS_errFILE 0x02 ++#define DFU_STATUS_errWRITE 0x03 ++#define DFU_STATUS_errERASE 0x04 ++#define DFU_STATUS_errCHECK_ERASED 0x05 ++#define DFU_STATUS_errPROG 0x06 ++#define DFU_STATUS_errVERIFY 0x07 ++#define DFU_STATUS_errADDRESS 0x08 ++#define DFU_STATUS_errNOTDONE 0x09 ++#define DFU_STATUS_errFIRMWARE 0x0a ++#define DFU_STATUS_errVENDOR 0x0b ++#define DFU_STATUS_errUSBR 0x0c ++#define DFU_STATUS_errPOR 0x0d ++#define DFU_STATUS_errUNKNOWN 0x0e ++#define DFU_STATUS_errSTALLEDPKT 0x0f ++ ++enum dfu_state { ++ DFU_STATE_appIDLE = 0, ++ DFU_STATE_appDETACH = 1, ++ DFU_STATE_dfuIDLE = 2, ++ DFU_STATE_dfuDNLOAD_SYNC = 3, ++ DFU_STATE_dfuDNBUSY = 4, ++ DFU_STATE_dfuDNLOAD_IDLE = 5, ++ DFU_STATE_dfuMANIFEST_SYNC = 6, ++ DFU_STATE_dfuMANIFEST = 7, ++ DFU_STATE_dfuMANIFEST_WAIT_RST = 8, ++ DFU_STATE_dfuUPLOAD_IDLE = 9, ++ DFU_STATE_dfuERROR = 10, ++}; ++ ++#endif /* _USB_DFU_H */ +Index: u-boot/include/usbdcore.h +=================================================================== +--- u-boot.orig/include/usbdcore.h ++++ u-boot/include/usbdcore.h +@@ -33,6 +33,7 @@ + + #include + #include "usbdescriptors.h" ++#include + + + #define MAX_URBS_QUEUED 5 +@@ -475,7 +476,11 @@ + * function driver to inform it that data has arrived. + */ + ++#ifdef CONFIG_USBD_DFU ++#define URB_BUF_SIZE (128+CONFIG_USBD_DFU_XFER_SIZE) ++#else + #define URB_BUF_SIZE 128 /* in linux we'd malloc this, but in u-boot we prefer static data */ ++#endif + struct urb { + + struct usb_endpoint_instance *endpoint; +@@ -603,6 +608,12 @@ + unsigned long usbd_rxtx_timestamp; + unsigned long usbd_last_rxtx_timestamp; + ++#ifdef CONFIG_USBD_DFU ++ const struct usb_device_descriptor *dfu_dev_desc; ++ const struct _dfu_desc *dfu_cfg_desc; ++ enum dfu_state dfu_state; ++ u_int8_t dfu_status; ++#endif + }; + + /* Bus Interface configuration structure +@@ -632,6 +643,8 @@ + extern char *usbd_device_requests[]; + extern char *usbd_device_descriptors[]; + ++extern struct usb_string_descriptor **usb_strings; ++ + void urb_link_init (urb_link * ul); + void urb_detach (struct urb *urb); + urb_link *first_urb_link (urb_link * hd); +Index: u-boot/drivers/usbtty.h +=================================================================== +--- u-boot.orig/drivers/usbtty.h ++++ u-boot/drivers/usbtty.h +@@ -71,4 +71,10 @@ + #define STR_CTRL_INTERFACE 0x06 + #define STR_COUNT 0x07 + ++#ifdef CONFIG_USBD_DFU ++#define NUM_STRINGS DFU_STR_COUNT ++#else ++#define NUM_STRINGS STR_COUNT ++#endif ++ + #endif +Index: u-boot/include/configs/qt2410.h +=================================================================== +--- u-boot.orig/include/configs/qt2410.h ++++ u-boot/include/configs/qt2410.h +@@ -199,7 +199,8 @@ + #define CONFIG_USBD_PRODUCT_NAME "QT2410 Bootloader " U_BOOT_VERSION + #define CONFIG_EXTRA_ENV_SETTINGS "usbtty=cdc_acm\0" + #define CONFIG_USBD_DFU 1 +-#define CONFIG_USBD_DFU_XFER_SIZE 0x4000 ++#define CONFIG_USBD_DFU_XFER_SIZE 4096 ++#define CONFIG_USBD_DFU_INTERFACE 2 + + /*----------------------------------------------------------------------- + * Physical Memory Map +Index: u-boot/tools/Makefile +=================================================================== +--- u-boot.orig/tools/Makefile ++++ u-boot/tools/Makefile +@@ -21,10 +21,10 @@ + # MA 02111-1307 USA + # + +-BIN_FILES = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX) ++BIN_FILES = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX) mkudfu$(SFX) + + OBJ_LINKS = environment.o crc32.o +-OBJ_FILES = img2srec.o mkimage.o envcrc.o gen_eth_addr.o bmp_logo.o ++OBJ_FILES = img2srec.o mkimage.o envcrc.o gen_eth_addr.o bmp_logo.o mkudfu.o + + ifeq ($(ARCH),mips) + BIN_FILES += inca-swap-bytes$(SFX) +@@ -137,6 +137,10 @@ + $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ + $(STRIP) $@ + ++$(obj)mkudfu$(SFX): $(obj)mkudfu.o ++ $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ ++ $(STRIP) $@ ++ + $(obj)ncb$(SFX): $(obj)ncb.o + $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ + $(STRIP) $@ +Index: u-boot/tools/mkudfu.c +=================================================================== +--- /dev/null ++++ u-boot/tools/mkudfu.c +@@ -0,0 +1,314 @@ ++/* ++ * USB DFU file trailer tool ++ * (C) Copyright by OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * based on mkimage.c, copyright information as follows: ++ * ++ * (C) Copyright 2000-2004 ++ * DENX Software Engineering ++ * Wolfgang Denk, wd@denx.de ++ * All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#ifndef __WIN32__ ++#include /* for host / network byte order conversions */ ++#endif ++#include ++#include ++#include ++#include ++ ++#if defined(__BEOS__) || defined(__NetBSD__) || defined(__APPLE__) ++#include ++#endif ++ ++#ifdef __WIN32__ ++typedef unsigned int __u32; ++ ++#define SWAP_LONG(x) \ ++ ((__u32)( \ ++ (((__u32)(x) & (__u32)0x000000ffUL) << 24) | \ ++ (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ ++ (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ ++ (((__u32)(x) & (__u32)0xff000000UL) >> 24) )) ++typedef unsigned char uint8_t; ++typedef unsigned short uint16_t; ++typedef unsigned int uint32_t; ++ ++#define ntohl(a) SWAP_LONG(a) ++#define htonl(a) SWAP_LONG(a) ++#endif /* __WIN32__ */ ++ ++#ifndef O_BINARY /* should be define'd on __WIN32__ */ ++#define O_BINARY 0 ++#endif ++ ++#include ++ ++extern int errno; ++ ++#ifndef MAP_FAILED ++#define MAP_FAILED (-1) ++#endif ++ ++static char *cmdname; ++ ++static char *datafile; ++static char *imagefile; ++ ++ ++static void usage() ++{ ++ fprintf (stderr, "%s - create / display u-boot DFU trailer\n", cmdname); ++ fprintf (stderr, "Usage: %s -l image\n" ++ " -l ==> list image header information\n" ++ " %s -v VID -p PID -r REV -d data_file image\n", ++ cmdname, cmdname); ++ fprintf (stderr, " -v ==> set vendor ID to 'VID'\n" ++ " -p ==> set product ID system to 'PID'\n" ++ " -r ==> set hardware revision to 'REV'\n" ++ " -d ==> use 'data_file' as input file\n" ++ ); ++ exit (EXIT_FAILURE); ++} ++ ++static void print_trailer(struct uboot_dfu_trailer *trailer) ++{ ++ printf("===> DFU Trailer information:\n"); ++ printf("Trailer Vers.: %d\n", trailer->version); ++ printf("Trailer Length: %d\n", trailer->length); ++ printf("VendorID: 0x%04x\n", trailer->vendor); ++ printf("ProductID: 0x%04x\n", trailer->product); ++ printf("HW Revision: 0x%04x\n", trailer->revision); ++} ++ ++static void copy_file (int ifd, const char *datafile, int pad) ++{ ++ int dfd; ++ struct stat sbuf; ++ unsigned char *ptr; ++ int tail; ++ int zero = 0; ++ int offset = 0; ++ int size; ++ ++ if ((dfd = open(datafile, O_RDONLY|O_BINARY)) < 0) { ++ fprintf (stderr, "%s: Can't open %s: %s\n", ++ cmdname, datafile, strerror(errno)); ++ exit (EXIT_FAILURE); ++ } ++ ++ if (fstat(dfd, &sbuf) < 0) { ++ fprintf (stderr, "%s: Can't stat %s: %s\n", ++ cmdname, datafile, strerror(errno)); ++ exit (EXIT_FAILURE); ++ } ++ ++ ptr = (unsigned char *)mmap(0, sbuf.st_size, ++ PROT_READ, MAP_SHARED, dfd, 0); ++ if (ptr == (unsigned char *)MAP_FAILED) { ++ fprintf (stderr, "%s: Can't read %s: %s\n", ++ cmdname, datafile, strerror(errno)); ++ exit (EXIT_FAILURE); ++ } ++ ++ size = sbuf.st_size - offset; ++ if (write(ifd, ptr + offset, size) != size) { ++ fprintf (stderr, "%s: Write error on %s: %s\n", ++ cmdname, imagefile, strerror(errno)); ++ exit (EXIT_FAILURE); ++ } ++ ++ if (pad && ((tail = size % 4) != 0)) { ++ ++ if (write(ifd, (char *)&zero, 4-tail) != 4-tail) { ++ fprintf (stderr, "%s: Write error on %s: %s\n", ++ cmdname, imagefile, strerror(errno)); ++ exit (EXIT_FAILURE); ++ } ++ } ++ ++ (void) munmap((void *)ptr, sbuf.st_size); ++ (void) close (dfd); ++} ++ ++ ++int main(int argc, char **argv) ++{ ++ int ifd; ++ int lflag = 0; ++ struct stat sbuf; ++ u_int16_t opt_vendor, opt_product, opt_revision; ++ struct uboot_dfu_trailer _hdr, _mirror, *hdr = &_hdr; ++ ++ opt_vendor = opt_product = opt_revision = 0; ++ ++ cmdname = *argv; ++ ++ while (--argc > 0 && **++argv == '-') { ++ while (*++*argv) { ++ switch (**argv) { ++ case 'l': ++ lflag = 1; ++ break; ++ case 'v': ++ if (--argc <= 0) ++ usage (); ++ opt_vendor = strtoul(*++argv, NULL, 16); ++ goto NXTARG; ++ case 'p': ++ if (--argc <= 0) ++ usage (); ++ opt_product = strtoul(*++argv, NULL, 16); ++ goto NXTARG; ++ case 'r': ++ if (--argc <= 0) ++ usage (); ++ opt_revision = strtoul(*++argv, NULL, 16); ++ goto NXTARG; ++ case 'd': ++ if (--argc <= 0) ++ usage (); ++ datafile = *++argv; ++ goto NXTARG; ++ case 'h': ++ usage(); ++ break; ++ default: ++ usage(); ++ } ++ } ++NXTARG: ; ++ } ++ ++ if (argc != 1) ++ usage(); ++ ++ imagefile = *argv; ++ ++ if (lflag) ++ ifd = open(imagefile, O_RDONLY|O_BINARY); ++ else ++ ifd = open(imagefile, O_RDWR|O_CREAT|O_TRUNC|O_BINARY, 0666); ++ ++ if (ifd < 0) { ++ fprintf (stderr, "%s: Can't open %s: %s\n", ++ cmdname, imagefile, strerror(errno)); ++ exit (EXIT_FAILURE); ++ } ++ ++ if (lflag) { ++ unsigned char *ptr; ++ /* list header information of existing image */ ++ if (fstat(ifd, &sbuf) < 0) { ++ fprintf (stderr, "%s: Can't stat %s: %s\n", ++ cmdname, imagefile, strerror(errno)); ++ exit (EXIT_FAILURE); ++ } ++ ++ if ((unsigned)sbuf.st_size < sizeof(struct uboot_dfu_trailer)) { ++ fprintf (stderr, ++ "%s: Bad size: \"%s\" is no valid image\n", ++ cmdname, imagefile); ++ exit (EXIT_FAILURE); ++ } ++ ++ ptr = (unsigned char *)mmap(0, sbuf.st_size, ++ PROT_READ, MAP_SHARED, ifd, 0); ++ if ((caddr_t)ptr == (caddr_t)-1) { ++ fprintf (stderr, "%s: Can't read %s: %s\n", ++ cmdname, imagefile, strerror(errno)); ++ exit (EXIT_FAILURE); ++ } ++ ++ dfu_trailer_mirror(hdr, ptr+sbuf.st_size); ++ ++ if (hdr->magic != UBOOT_DFU_TRAILER_MAGIC) { ++ fprintf (stderr, ++ "%s: Bad Magic Number: \"%s\" is no valid image\n", ++ cmdname, imagefile); ++ exit (EXIT_FAILURE); ++ } ++ ++ /* for multi-file images we need the data part, too */ ++ print_trailer(hdr); ++ ++ (void) munmap((void *)ptr, sbuf.st_size); ++ (void) close (ifd); ++ ++ exit (EXIT_SUCCESS); ++ } ++ ++ /* if we're not listing: */ ++ ++ copy_file (ifd, datafile, 0); ++ ++ memset (hdr, 0, sizeof(struct uboot_dfu_trailer)); ++ ++ /* Build new header */ ++ hdr->version = UBOOT_DFU_TRAILER_V1; ++ hdr->magic = UBOOT_DFU_TRAILER_MAGIC; ++ hdr->length = sizeof(struct uboot_dfu_trailer); ++ hdr->vendor = opt_vendor; ++ hdr->product = opt_product; ++ hdr->revision = opt_revision; ++ ++ print_trailer(hdr); ++ dfu_trailer_mirror(&_mirror, (unsigned char *)hdr+sizeof(*hdr)); ++ ++ if (write(ifd, &_mirror, sizeof(struct uboot_dfu_trailer)) ++ != sizeof(struct uboot_dfu_trailer)) { ++ fprintf (stderr, "%s: Write error on %s: %s\n", ++ cmdname, imagefile, strerror(errno)); ++ exit (EXIT_FAILURE); ++ } ++ ++ /* We're a bit of paranoid */ ++#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) ++ (void) fdatasync (ifd); ++#else ++ (void) fsync (ifd); ++#endif ++ ++ if (fstat(ifd, &sbuf) < 0) { ++ fprintf (stderr, "%s: Can't stat %s: %s\n", ++ cmdname, imagefile, strerror(errno)); ++ exit (EXIT_FAILURE); ++ } ++ ++ /* We're a bit of paranoid */ ++#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) ++ (void) fdatasync (ifd); ++#else ++ (void) fsync (ifd); ++#endif ++ ++ if (close(ifd)) { ++ fprintf (stderr, "%s: Write error on %s: %s\n", ++ cmdname, imagefile, strerror(errno)); ++ exit (EXIT_FAILURE); ++ } ++ ++ exit (EXIT_SUCCESS); ++} +Index: u-boot/include/usb_dfu_trailer.h +=================================================================== +--- /dev/null ++++ u-boot/include/usb_dfu_trailer.h +@@ -0,0 +1,31 @@ ++#ifndef _USB_DFU_TRAILER_H ++#define _USB_DFU_TRAILER_H ++ ++/* trailer handling for DFU files */ ++ ++#define UBOOT_DFU_TRAILER_V1 1 ++#define UBOOT_DFU_TRAILER_MAGIC 0x19731978 ++struct uboot_dfu_trailer { ++ u_int32_t magic; ++ u_int16_t version; ++ u_int16_t length; ++ u_int16_t vendor; ++ u_int16_t product; ++ u_int32_t revision; ++} __attribute__((packed)); ++ ++/* we mirror the trailer because we want it to be longer in later versions ++ * while keeping backwards compatibility */ ++static inline void dfu_trailer_mirror(struct uboot_dfu_trailer *trailer, ++ unsigned char *eof) ++{ ++ int i; ++ int len = sizeof(struct uboot_dfu_trailer); ++ unsigned char *src = eof - len; ++ unsigned char *dst = (unsigned char *) trailer; ++ ++ for (i = 0; i < len; i++) ++ dst[len-1-i] = src[i]; ++} ++ ++#endif /* _USB_DFU_TRAILER_H */ +Index: u-boot/Makefile +=================================================================== +--- u-boot.orig/Makefile ++++ u-boot/Makefile +@@ -261,6 +261,12 @@ + $(obj)u-boot.bin: $(obj)u-boot + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + ++$(obj)u-boot.udfu: $(obj)u-boot.bin ++ ./tools/mkudfu -v $(CONFIG_USB_DFU_VENDOR) \ ++ -p $(CONFIG_USB_DFU_PRODUCT) \ ++ -r $(CONFIG_USB_DFU_REVISION) \ ++ -d $< $@ ++ + $(obj)u-boot.img: $(obj)u-boot.bin + ./tools/mkimage -A $(ARCH) -T firmware -C none \ + -a $(TEXT_BASE) -e 0 \ +Index: u-boot/board/neo1973/gta01/split_by_variant.sh +=================================================================== +--- u-boot.orig/board/neo1973/gta01/split_by_variant.sh ++++ u-boot/board/neo1973/gta01/split_by_variant.sh +@@ -15,37 +15,44 @@ + echo "$0:: No parameters - using GTA01Bv3 config" + echo "#define CONFIG_ARCH_GTA01B_v3" > $CFGINC + echo "GTA01_BIG_RAM=y" > $CFGTMP ++ echo "CONFIG_USB_DFU_REVISION=0x0230" > $CFGTMP + else + case "$1" in + gta01v4_config) + echo "#define CONFIG_ARCH_GTA01_v4" > $CFGINC + echo "GTA01_BIG_RAM=n" > $CFGTMP ++ echo "CONFIG_USB_DFU_REVISION=0x0140" > $CFGTMP + ;; + + gta01v3_config) + echo "#define CONFIG_ARCH_GTA01_v3" > $CFGINC + echo "GTA01_BIG_RAM=n" > $CFGTMP ++ echo "CONFIG_USB_DFU_REVISION=0x0130" > $CFGTMP + ;; + + gta01bv2_config) + echo "#define CONFIG_ARCH_GTA01B_v2" > $CFGINC + echo "GTA01_BIG_RAM=y" > $CFGTMP ++ echo "CONFIG_USB_DFU_REVISION=0x0220" > $CFGTMP + ;; + + gta01bv3_config) + echo "#define CONFIG_ARCH_GTA01B_v3" > $CFGINC + echo "GTA01_BIG_RAM=y" > $CFGTMP ++ echo "CONFIG_USB_DFU_REVISION=0x0230" > $CFGTMP + ;; + + gta01bv4_config) + echo "#define CONFIG_ARCH_GTA01B_v4" > $CFGINC + echo "GTA01_BIG_RAM=y" > $CFGTMP ++ echo "CONFIG_USB_DFU_REVISION=0x0240" > $CFGTMP + ;; + + *) + echo "$0:: Unrecognised config - using GTA01Bv4 config" + echo "#define CONFIG_ARCH_GTA01B_v4" > $CFGINC + echo "GTA01_BIG_RAM=y" > $CFGTMP ++ echo "CONFIG_USB_DFU_REVISION=0x0240" > $CFGTMP + ;; + + esac +Index: u-boot/board/neo1973/gta01/config.mk +=================================================================== +--- u-boot.orig/board/neo1973/gta01/config.mk ++++ u-boot/board/neo1973/gta01/config.mk +@@ -24,6 +24,9 @@ + # + # download area is 3200'0000 or 3300'0000 + ++CONFIG_USB_DFU_VENDOR=0x1457 ++CONFIG_USB_DFU_PRODUCT=0x5119 ++ + sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + + ifeq ($(GTA01_BIG_RAM),y) diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-gta02.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-gta02.patch new file mode 100644 index 0000000000..ca54ebeff7 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-gta02.patch @@ -0,0 +1,1560 @@ +Add support for new GTA02 version of Neo1973 + +Index: u-boot/Makefile +=================================================================== +--- u-boot.orig/Makefile ++++ u-boot/Makefile +@@ -2038,6 +2038,10 @@ + sbc2410x_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t sbc2410x NULL s3c24x0 + ++gta02_config \ ++gta02v1_config : unconfig ++ @sh board/neo1973/gta02/split_by_variant.sh $@ ++ + gta01_config \ + gta01v3_config \ + gta01bv2_config \ +Index: u-boot/board/neo1973/gta02/Makefile +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/gta02/Makefile +@@ -0,0 +1,64 @@ ++# ++# (C) Copyright 2000, 2001, 2002 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = lib$(BOARD).a ++ ++OBJS := gta02.o pcf50633.o ../common/cmd_neo1973.o ../common/jbt6k74.o ../common/udc.o ../common/bootmenu.o ++SOBJS := ../common/lowlevel_init.o ++ ++.PHONY: all ++ ++all: $(LIB) lowevel_foo.bin ++ ++$(LIB): $(OBJS) $(SOBJS) ++ $(AR) crv $@ $(OBJS) $(SOBJS) ++ ++lowlevel_foo.o: ../common/lowlevel_foo.S ++ $(CC) -c -DTEXT_BASE=0x33F80000 -march=armv4 \ ++ -o lowlevel_foo.o ../common/lowlevel_foo.S ++ ++lowlevel_foo: lowlevel_foo.o ../common/lowlevel_init.o ../common/lowlevel_foo.lds ++ $(LD) -T ../common/lowlevel_foo.lds -Ttext 0x33f80000 -Bstatic \ ++ ../common/lowlevel_init.o lowlevel_foo.o -o lowlevel_foo ++ ++lowevel_foo.bin: lowlevel_foo ++ $(CROSS_COMPILE)objcopy --gap-fill=0xff -O binary \ ++ lowlevel_foo lowlevel_foo.bin ++ ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) lowlevel_foo lowlevel_foo.o ++ ++distclean: clean ++ rm -f $(LIB) core *.bak .depend lowlevel_foo.bin ++ ++######################################################################### ++ ++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) ++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ ++ ++-include .depend ++ ++######################################################################### +Index: u-boot/board/neo1973/gta02/gta02.c +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/gta02/gta02.c +@@ -0,0 +1,313 @@ ++/* ++ * (C) 2006-2007 by OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * based on existing S3C2410 startup code in u-boot: ++ * ++ * (C) Copyright 2002 ++ * Sysgo Real-Time Solutions, GmbH ++ * Marius Groeger ++ * ++ * (C) Copyright 2002 ++ * David Mueller, ELSOFT AG, ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++ ++#include "../common/neo1973.h" ++#include "../common/jbt6k74.h" ++ ++#include "pcf50633.h" ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++/* That many seconds the power key needs to be pressed to power up */ ++#define POWER_KEY_SECONDS 2 ++ ++#define M_MDIV 0x7f /* Fout = 405.00MHz */ ++#define M_PDIV 0x2 ++#define M_SDIV 0x1 ++ ++#define U_M_MDIV 0x38 ++#define U_M_PDIV 0x2 ++#define U_M_SDIV 0x2 ++ ++unsigned int neo1973_wakeup_cause; ++extern int nobootdelay; ++ ++static inline void delay (unsigned long loops) ++{ ++ __asm__ volatile ("1:\n" ++ "subs %0, %1, #1\n" ++ "bne 1b":"=r" (loops):"0" (loops)); ++} ++ ++/* ++ * Miscellaneous platform dependent initialisations ++ */ ++ ++int board_init (void) ++{ ++ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ ++ /* to reduce PLL lock time, adjust the LOCKTIME register */ ++ clk_power->LOCKTIME = 0xFFFFFF; ++ ++ /* configure MPLL */ ++ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); ++ ++ /* some delay between MPLL and UPLL */ ++ delay (4000); ++ ++ /* configure UPLL */ ++ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); ++ ++ /* some delay between MPLL and UPLL */ ++ delay (8000); ++ ++ /* set up the I/O ports */ ++#if defined(CONFIG_ARCH_GTA02_v1) ++ gpio->GPACON = 0x007E1FFF; ++ gpio->GPADAT |= (1 << 16); /* Set GPA16 to high (nNAND_WP) */ ++ ++ gpio->GPBCON = 0x00155555; ++ gpio->GPBUP = 0x000007FF; ++ ++ gpio->GPCCON = 0x55551155; ++ gpio->GPCUP = 0x0000FFFF; ++ ++ gpio->GPDCON = 0x55555555; ++ gpio->GPDUP = 0x0000FFFF; ++ ++ gpio->GPECON = 0xAAAAAAAA; ++ gpio->GPEUP = 0x0000FFFF; ++ ++ gpio->GPFCON = 0x0000AAAA; ++ gpio->GPFUP = 0x000000FF; ++ ++ gpio->GPGCON = 0x013DFDFA; ++ gpio->GPGUP = 0x0000FFFF; ++ ++ gpio->GPHCON = 0x0028AAAA; ++ gpio->GPHUP = 0x000007FF; ++ ++ gpio->GPJCON = 0x1545541; ++#else ++#error Please define GTA02 version ++#endif ++ ++ /* arch number of SMDK2410-Board */ ++ gd->bd->bi_arch_number = MACH_TYPE_NEO1973_GTA02; ++ ++ /* adress of boot parameters */ ++ gd->bd->bi_boot_params = 0x30000100; ++ ++ icache_enable(); ++ dcache_enable(); ++ ++ return 0; ++} ++ ++int board_late_init(void) ++{ ++ extern unsigned char booted_from_nand; ++ unsigned char tmp; ++ char buf[32]; ++ int menu_vote = 0; /* <= 0: no, > 0: yes */ ++ int seconds = 0; ++ ++ /* Initialize the Power Management Unit with a safe register set */ ++ pcf50633_init(); ++#if 0 ++ /* if there's no other reason, must be regular reset */ ++ neo1973_wakeup_cause = NEO1973_WAKEUP_RESET; ++ ++ if (!booted_from_nand) ++ goto woken_by_reset; ++ ++ /* obtain wake-up reason, save INT1 in environment */ ++ tmp = pcf50606_reg_read(PCF50606_REG_INT1); ++ sprintf(buf, "0x%02x", tmp); ++ setenv("pcf50606_int1", buf); ++ ++ if (tmp & PCF50606_INT1_ALARM) { ++ /* we've been woken up by RTC alarm, boot */ ++ neo1973_wakeup_cause = NEO1973_WAKEUP_ALARM; ++ goto continue_boot; ++ } ++ if (tmp & PCF50606_INT1_EXTONR) { ++ /* we've been woken up by charger insert */ ++ neo1973_wakeup_cause = NEO1973_WAKEUP_CHARGER; ++ } ++ ++ if (tmp & PCF50606_INT1_ONKEYF) { ++ /* we've been woken up by a falling edge of the onkey */ ++ neo1973_wakeup_cause = NEO1973_WAKEUP_POWER_KEY; ++ } ++ ++ if (neo1973_wakeup_cause == NEO1973_WAKEUP_CHARGER) { ++ /* if we still think it was only a charger insert, boot */ ++ goto continue_boot; ++ } ++ ++woken_by_reset: ++ ++ while (neo1973_wakeup_cause == NEO1973_WAKEUP_RESET || ++ neo1973_on_key_pressed()) { ++ if (neo1973_aux_key_pressed()) ++ menu_vote++; ++ else ++ menu_vote--; ++ ++ if (neo1973_new_second()) ++ seconds++; ++ if (seconds >= POWER_KEY_SECONDS) ++ goto continue_boot; ++ } ++ /* Power off if minimum number of seconds not reached */ ++ neo1973_poweroff(); ++ ++continue_boot: ++ jbt6k74_init(); ++ jbt6k74_enter_state(JBT_STATE_NORMAL); ++ jbt6k74_display_onoff(1); ++#endif ++ ++ /* issue a short pulse with the vibrator */ ++ neo1973_vibrator(1); ++ udelay(50000); ++ neo1973_vibrator(0); ++ ++ /* switch on the backlight */ ++ neo1973_backlight(1); ++ ++#if 0 ++ { ++ /* check if sd card is inserted, and power-up if it is */ ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ if (!(gpio->GPFDAT & (1 << 5))) ++ gpio->GPBDAT &= ~(1 << 2); ++ } ++ ++ if (menu_vote > 0) { ++ bootmenu(); ++ nobootdelay = 1; ++ } ++#endif ++ ++ return 0; ++} ++ ++int dram_init (void) ++{ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; ++ ++ return 0; ++} ++ ++u_int32_t get_board_rev(void) ++{ ++#if defined(CONFIG_ARCH_GTA02_v1) ++ return 0x00000310; ++#endif ++} ++ ++void neo1973_poweroff(void) ++{ ++ printf("poweroff\n"); ++ udc_disconnect(); ++ pcf50633_reg_write(PCF50633_REG_OOCSHDWN, 0x01); ++ /* don't return to caller */ ++ while (1) ; ++} ++ ++void neo1973_backlight(int on) ++{ ++ /* FIXME: PMU based implementation */ ++} ++ ++/* FIXME: shared */ ++void neo1973_vibrator(int on) ++{ ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ if (on) ++#if defined(CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4) ++ gpio->GPGDAT |= (1 << 11); /* GPG11 */ ++#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3) ++ gpio->GPBDAT |= (1 << 10); /* GPB10 */ ++#elif defined(CONFIG_ARCH_GTA01B_v4) || defined(CONFIG_ARCH_GTA02_v1) ++ gpio->GPBDAT |= (1 << 3); /* GPB3 */ ++#endif ++ else ++#if defined(CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4) ++ gpio->GPGDAT &= ~(1 << 11); /* GPG11 */ ++#elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3) ++ gpio->GPBDAT &= ~(1 << 10); /* GPB10 */ ++#elif defined(CONFIG_ARCH_GTA01B_v4) || defined(CONFIG_ARCH_GTA02_v1) ++ gpio->GPBDAT &= ~(1 << 3); /* GPB3 */ ++#endif ++} ++ ++int neo1973_new_second(void) ++{ ++ return pcf50633_reg_read(PCF50633_REG_INT1) & PCF50633_INT1_SECOND; ++} ++ ++int neo1973_on_key_pressed(void) ++{ ++ return !(pcf50633_reg_read(PCF50633_REG_OOCSTAT) ++ & PCF50633_OOCSTAT_ONKEY); ++} ++ ++/* FIXME: shared */ ++int neo1973_aux_key_pressed(void) ++{ ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ if (gpio->GPFDAT & (1 << 6)) ++ return 0; ++ return 1; ++} ++ ++/* The sum of all part_size[]s must equal to the NAND size, i.e., 0x4000000. ++ "initrd" is sized such that it can hold two uncompressed 16 bit 640*480 ++ images: 640*480*2*2 = 1228800 < 1245184. */ ++ ++unsigned int dynpart_size[] = { ++ CFG_UBOOT_SIZE, CFG_ENV_SIZE, 0x200000, 0xa0000, 0x1fce0000, 0 }; ++char *dynpart_names[] = { ++ "u-boot", "u-boot_env", "kernel", "splash", "rootfs", NULL }; ++ ++ ++const char *neo1973_get_charge_status(void) ++{ ++ /* FIXME */ ++ return "unknown"; ++} ++ ++int neo1973_set_charge_mode(enum neo1973_charger_cmd cmd) ++{ ++ /* FIXME */ ++ return 0; ++} +Index: u-boot/board/neo1973/gta02/u-boot.lds +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/gta02/u-boot.lds +@@ -0,0 +1,58 @@ ++/* ++ * (C) Copyright 2002 ++ * Gary Jennejohn, DENX Software Engineering, ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ ++OUTPUT_ARCH(arm) ++ENTRY(_start) ++SECTIONS ++{ ++ . = 0x00000000; ++ ++ . = ALIGN(4); ++ .text : ++ { ++ cpu/arm920t/start.o (.text) ++ cpu/arm920t/s3c24x0/nand_read.o (.text) ++ *(.text) ++ } ++ ++ . = ALIGN(4); ++ .rodata : { *(.rodata) } ++ ++ . = ALIGN(4); ++ .data : { *(.data) } ++ ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ . = .; ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss : { *(.bss) } ++ _end = .; ++} +Index: u-boot/include/configs/neo1973_gta02.h +=================================================================== +--- /dev/null ++++ u-boot/include/configs/neo1973_gta02.h +@@ -0,0 +1,276 @@ ++/* ++ * (C) Copyright 2007 OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * Configuation settings for the FIC Neo1973 GTA02 Linux GSM phone ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++/* we want to be able to start u-boot directly from within NAND flash */ ++#define CONFIG_LL_INIT_NAND_ONLY ++#define CONFIG_S3C2410_NAND_BOOT 1 ++#define CONFIG_S3C2410_NAND_SKIP_BAD 1 ++ ++#define CFG_UBOOT_SIZE 0x40000 /* size of u-boot, for NAND loading */ ++ ++/* ++ * High Level Configuration Options ++ * (easy to change) ++ */ ++#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ ++#define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2410 SoC */ ++#define CONFIG_SMDK2440 1 /* on a SAMSUNG SMDK2410 Board */ ++ ++/* input clock of PLL */ ++#define CONFIG_SYS_CLK_FREQ 12000000/* the GTA02 has this input clock */ ++ ++ ++#define USE_920T_MMU 1 ++#define CONFIG_USE_IRQ 1 ++ ++/* ++ * Size of malloc() pool ++ */ ++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 400*1024) ++ /* >> CFG_VIDEO_LOGO_MAX_SIZE */ ++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ ++ ++/* ++ * Hardware drivers ++ */ ++ ++/* ++ * select serial console configuration ++ */ ++#define CONFIG_SERIAL3 1 /* we use SERIAL 1 on GTA01 */ ++ ++/************************************************************ ++ * RTC ++ ************************************************************/ ++#define CONFIG_RTC_S3C24X0 1 ++ ++/* allow to overwrite serial and ethaddr */ ++#define CONFIG_ENV_OVERWRITE ++ ++#define CONFIG_BAUDRATE 115200 ++ ++/*********************************************************** ++ * Command definition ++ ***********************************************************/ ++#define CONFIG_COMMANDS (\ ++ CFG_CMD_BDI | \ ++ CFG_CMD_LOADS | \ ++ CFG_CMD_LAODB | \ ++ CFG_CMD_IMI | \ ++ CFG_CMD_CACHE | \ ++ CFG_CMD_MEMORY | \ ++ CFG_CMD_ENV | \ ++ /* CFG_CMD_IRQ | */ \ ++ CFG_CMD_BOOTD | \ ++ CFG_CMD_CONSOLE | \ ++ /* CFG_CMD_BMP | */ \ ++ CFG_CMD_ASKENV | \ ++ CFG_CMD_RUN | \ ++ CFG_CMD_ECHO | \ ++ CFG_CMD_I2C | \ ++ CFG_CMD_REGINFO | \ ++ CFG_CMD_IMMAP | \ ++ CFG_CMD_DATE | \ ++ CFG_CMD_AUTOSCRIPT | \ ++ CFG_CMD_BSP | \ ++ CFG_CMD_ELF | \ ++ CFG_CMD_MISC | \ ++ /* CFG_CMD_USB | */ \ ++ CFG_CMD_JFFS2 | \ ++ CFG_CMD_DIAG | \ ++ /* CFG_CMD_HWFLOW | */ \ ++ CFG_CMD_SAVES | \ ++ CFG_CMD_NAND | \ ++ CFG_CMD_PORTIO | \ ++ CFG_CMD_MMC | \ ++ CFG_CMD_FAT | \ ++ CFG_CMD_EXT2 | \ ++ 0) ++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ ++#include ++ ++#define CONFIG_BOOTDELAY 3 ++#define CONFIG_BOOTARGS "" ++#define CONFIG_BOOTCOMMAND "setenv bootargs ${bootargs_base} ${mtdparts}; nand read.e 0x32000000 kernel; bootm 0x32000000" ++ ++#define CONFIG_DOS_PARTITION 1 ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ ++/* what's this ? it's not used anywhere */ ++#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ ++#endif ++ ++/* ++ * Miscellaneous configurable options ++ */ ++#define CFG_LONGHELP /* undef to save memory */ ++#if defined(CONFIG_ARCH_GTA02_v1) ++#define CFG_PROMPT "GTA02v1 # " /* Monitor Command Prompt */ ++#endif ++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ ++#define CFG_MAXARGS 64 /* max number of command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ ++ ++#define CFG_MEMTEST_START 0x30000000 /* memtest works on */ ++#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ ++ ++#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ ++ ++#define CFG_LOAD_ADDR 0x33000000 /* default load address */ ++ ++/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ ++/* it to wrap 100 times (total 1562500) to get 1 sec. */ ++#define CFG_HZ 1562500 ++ ++/* valid baudrates */ ++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } ++ ++#define CFG_BOOTMENU ++ ++/*----------------------------------------------------------------------- ++ * Stack sizes ++ * ++ * The stack sizes are set up in start.S using the settings below ++ */ ++#define CONFIG_STACKSIZE (128*1024) /* regular stack */ ++#ifdef CONFIG_USE_IRQ ++#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */ ++#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ ++#endif ++ ++#if 0 ++#define CONFIG_USB_OHCI 1 ++#endif ++ ++#define CONFIG_USB_DEVICE 1 ++#define CONFIG_USB_TTY 1 ++#define CFG_CONSOLE_IS_IN_ENV 1 ++#define CONFIG_USBD_VENDORID 0x1457 /* Linux/NetChip */ ++#define CONFIG_USBD_PRODUCTID_GSERIAL 0x5120 /* gserial */ ++#define CONFIG_USBD_PRODUCTID_CDCACM 0x5119 /* CDC ACM */ ++#define CONFIG_USBD_MANUFACTURER "OpenMoko, Inc" ++#define CONFIG_USBD_PRODUCT_NAME "Neo1973 Bootloader " U_BOOT_VERSION ++#define CONFIG_USBD_DFU 1 ++#define CONFIG_USBD_DFU_XFER_SIZE 4096 /* 0x4000 */ ++#define CONFIG_USBD_DFU_INTERFACE 2 ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "usbtty=cdc_acm\0" \ ++ "bootargs_base=rootfstype=jffs2 root=/dev/mtdblock4 console=ttySAC0,115200 console=tty0 loglevel=8\0" \ ++ "" ++ ++/*----------------------------------------------------------------------- ++ * Physical Memory Map ++ */ ++#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ ++#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ ++#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ ++#define PHYS_SDRAM_RES_SIZE 0x00200000 /* 2 MB for frame buffer */ ++ ++/*----------------------------------------------------------------------- ++ * FLASH and environment organization ++ */ ++ ++/* No NOR flash in this device */ ++#define CFG_NO_FLASH 1 ++ ++#define CFG_ENV_IS_IN_NAND 1 ++#define CFG_ENV_SIZE 0x40000 /* 128k Total Size of Environment Sector */ ++#define CFG_ENV_OFFSET_OOB 1 /* Location of ENV stored in block 0 OOB */ ++#define CFG_PREBOOT_OVERRIDE 1 /* allow preboot from memory */ ++ ++#define NAND_MAX_CHIPS 1 ++#define CFG_NAND_BASE 0x4e000000 ++#define CFG_MAX_NAND_DEVICE 1 ++ ++#define CONFIG_MMC 1 ++#define CFG_MMC_BASE 0xff000000 ++ ++/* EXT2 driver */ ++#define CONFIG_EXT2 1 ++ ++#define CONFIG_FAT 1 ++#define CONFIG_SUPPORT_VFAT ++ ++#if 1 ++/* JFFS2 driver */ ++#define CONFIG_JFFS2_CMDLINE 1 ++#define CONFIG_JFFS2_NAND 1 ++#define CONFIG_JFFS2_NAND_DEV 0 ++//#define CONFIG_JFFS2_NAND_OFF 0x634000 ++//#define CONFIG_JFFS2_NAND_SIZE 0x39cc000 ++#endif ++ ++/* ATAG configuration */ ++#define CONFIG_INITRD_TAG 1 ++#define CONFIG_SETUP_MEMORY_TAGS 1 ++#define CONFIG_CMDLINE_TAG 1 ++#define CONFIG_REVISION_TAG 1 ++#if 0 ++#define CONFIG_SERIAL_TAG 1 ++#endif ++ ++#define CONFIG_DRIVER_S3C24X0_I2C 1 ++#define CONFIG_HARD_I2C 1 ++#define CFG_I2C_SPEED 400000 /* 400kHz according to PCF50633 data sheet */ ++#define CFG_I2C_SLAVE 0x7f ++ ++/* we have a board_late_init() function */ ++#define BOARD_LATE_INIT 1 ++ ++#if 0 ++#define CONFIG_VIDEO ++#define CONFIG_VIDEO_S3C2410 ++#define CONFIG_CFB_CONSOLE ++#define CONFIG_VIDEO_LOGO ++#define CONFIG_SPLASH_SCREEN ++#define CFG_VIDEO_LOGO_MAX_SIZE (640*480+1024+100) /* 100 = slack */ ++#define CONFIG_VIDEO_BMP_GZIP ++#define CONFIG_VGA_AS_SINGLE_DEVICE ++#define CONFIG_UNZIP ++ ++#define VIDEO_KBD_INIT_FCT 0 ++#define VIDEO_TSTC_FCT serial_tstc ++#define VIDEO_GETC_FCT serial_getc ++ ++#define LCD_VIDEO_ADDR 0x33d00000 ++#endif ++ ++#define CONFIG_S3C2410_NAND_BBT 1 ++//#define CONFIG_S3C2410_NAND_HWECC 1 ++ ++#define CONFIG_DRIVER_PCF50633 1 ++ ++#define MTDIDS_DEFAULT "nand0=neo1973-nand" ++#define MTPARTS_DEFAULT "neo1973-nand:256k(u-boot),128k(u-boot_env),2M(kernel),640k(splash),-(jffs2)" ++#define CFG_NAND_DYNPART_MTD_KERNEL_NAME "neo1973-nand" ++#define CONFIG_NAND_DYNPART ++ ++#endif /* __CONFIG_H */ +Index: u-boot/board/neo1973/gta02/split_by_variant.sh +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/gta02/split_by_variant.sh +@@ -0,0 +1,37 @@ ++#!/bin/sh ++# --------------------------------------------------------- ++# Set the core module defines according to Core Module ++# --------------------------------------------------------- ++# --------------------------------------------------------- ++# Set up the GTA01 type define ++# --------------------------------------------------------- ++ ++CFGINC=${obj}include/config.h ++CFGTMP=${obj}board/neo1973/gta02/config.tmp ++ ++mkdir -p ${obj}include ++if [ "$1" == "" ] ++then ++ echo "$0:: No parameters - using GTA02Bv1 config" ++ echo "#define CONFIG_ARCH_GTA02_v1" > $CFGINC ++ echo "CONFIG_USB_DFU_REVISION=0x0310" > $CFGTMP ++else ++ case "$1" in ++ gta02v1_config) ++ echo "#define CONFIG_ARCH_GTA02_v1" > $CFGINC ++ echo "CONFIG_USB_DFU_REVISION=0x0310" > $CFGTMP ++ ;; ++ ++ *) ++ echo "$0:: Unrecognised config - using GTA02v1 config" ++ echo "#define CONFIG_ARCH_GTA02_v1" > $CFGINC ++ echo "CONFIG_USB_DFU_REVISION=0x0310" > $CFGTMP ++ ;; ++ ++ esac ++ ++fi ++# --------------------------------------------------------- ++# Complete the configuration ++# --------------------------------------------------------- ++$MKCONFIG -a neo1973_gta02 arm arm920t gta02 neo1973 s3c24x0 +Index: u-boot/include/pcf50633.h +=================================================================== +--- /dev/null ++++ u-boot/include/pcf50633.h +@@ -0,0 +1,235 @@ ++#ifndef _PCF50633_H ++#define _PCF50633_H ++ ++/* Philips PCF50633 Power Managemnt Unit (PMU) driver ++ * (C) 2006-2007 by OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ */ ++ ++enum pfc50633_regs { ++ PCF50633_REG_VERSION = 0x00, ++ PCF50633_REG_VARIANT = 0x01, ++ PCF50633_REG_INT1 = 0x02, /* Interrupt Status */ ++ PCF50633_REG_INT2 = 0x03, /* Interrupt Status */ ++ PCF50633_REG_INT3 = 0x04, /* Interrupt Status */ ++ PCF50633_REG_INT4 = 0x05, /* Interrupt Status */ ++ PCF50633_REG_INT5 = 0x06, /* Interrupt Status */ ++ PCF50633_REG_INT1M = 0x07, /* Interrupt Mask */ ++ PCF50633_REG_INT2M = 0x08, /* Interrupt Mask */ ++ PCF50633_REG_INT3M = 0x09, /* Interrupt Mask */ ++ PCF50633_REG_INT4M = 0x0a, /* Interrupt Mask */ ++ PCF50633_REG_INT5M = 0x0b, /* Interrupt Mask */ ++ PCF50633_REG_OOCSHDWN = 0x0c, ++ PCF50633_REG_OOCWAKE = 0x0d, ++ PCF50633_REG_OOCTIM1 = 0x0e, ++ PCF50633_REG_OOCTIM2 = 0x0f, ++ PCF50633_REG_OOCMODE = 0x10, ++ PCF50633_REG_OOCCTL = 0x11, ++ PCF50633_REG_OOCSTAT = 0x12, ++ PCF50633_REG_GPIOCTL = 0x13, ++ PCF50633_REG_GPIO1CFG = 0x14, ++ PCF50633_REG_GPIO2CFG = 0x15, ++ PCF50633_REG_GPIO3CFG = 0x16, ++ PCF50633_REG_GPOCFG = 0x17, ++ PCF50633_REG_BVMCTL = 0x18, ++ PCF50633_REG_SVMCTL = 0x19, ++ PCF50633_REG_AUTOOUT = 0x1a, ++ PCF50633_REG_AUTOENA = 0x1b, ++ PCF50633_REG_AUTOCTL = 0x1c, ++ PCF50633_REG_AUTOMXC = 0x1d, ++ PCF50633_REG_DOWN1OUT = 0x1e, ++ PCF50633_REG_DOWN1ENA = 0x1f, ++ PCF50633_REG_DOWN1CTL = 0x20, ++ PCF50633_REG_DOWN1MXC = 0x21, ++ PCF50633_REG_DOWN2OUT = 0x22, ++ PCF50633_REG_DOWN2ENA = 0x23, ++ PCF50633_REG_DOWN2CTL = 0x24, ++ PCF50633_REG_DOWN2MXC = 0x25, ++ PCF50633_REG_MEMLDOOUT = 0x26, ++ PCF50633_REG_MEMLDOENA = 0x27, ++ PCF50633_REG_LEDOUT = 0x28, ++ PCF50633_REG_LEDENA = 0x29, ++ PCF50633_REG_LEDCTL = 0x2a, ++ PCF50633_REG_LEDDIM = 0x2b, ++ /* reserved */ ++ PCF50633_REG_LDO1OUT = 0x2d, ++ PCF50633_REG_LDO1ENA = 0x2e, ++ PCF50633_REG_LDO2OUT = 0x2f, ++ PCF50633_REG_LDO2ENA = 0x30, ++ PCF50633_REG_LDO3OUT = 0x31, ++ PCF50633_REG_LDO3ENA = 0x32, ++ PCF50633_REG_LDO4OUT = 0x33, ++ PCF50633_REG_LDO4ENA = 0x34, ++ PCF50633_REG_LDO5OUT = 0x35, ++ PCF50633_REG_LDO5ENA = 0x36, ++ PCF50633_REG_LDO6OUT = 0x37, ++ PCF50633_REG_LDO6ENA = 0x38, ++ PCF50633_REG_HCLDOOUT = 0x39, ++ PCF50633_REG_HCLDOENA = 0x3a, ++ PCF50633_REG_STBYCTL1 = 0x3b, ++ PCF50633_REG_STBYCTL2 = 0x3c, ++ PCF50633_REG_DEBPF1 = 0x3d, ++ PCF50633_REG_DEBPF2 = 0x3e, ++ PCF50633_REG_DEBPF3 = 0x3f, ++ PCF50633_REG_HCLDOOVL = 0x40, ++ PCF50633_REG_DCDCSTAT = 0x41, ++ PCF50633_REG_LDOSTAT = 0x42, ++ PCF50633_REG_MBCC1 = 0x43, ++ PCF50633_REG_MBCC2 = 0x44, ++ PCF50633_REG_MBCC3 = 0x45, ++ PCF50633_REG_MBCC4 = 0x46, ++ PCF50633_REG_MBCC5 = 0x47, ++ PCF50633_REG_MBCC6 = 0x48, ++ PCF50633_REG_MBCC7 = 0x49, ++ PCF50633_REG_MBCC8 = 0x4a, ++ PCF50633_REG_MBCS1 = 0x4b, ++ PCF50633_REG_MBCS2 = 0x4c, ++ PCF50633_REG_MBCS3 = 0x4d, ++ PCF50633_REG_BBCCTL = 0x4e, ++ PCF50633_REG_ALMGAIN = 0x4f, ++ PCF50633_REG_ALMDATA = 0x50, ++ /* reserved */ ++ PCF50633_REG_ADCC3 = 0x52, ++ PCF50633_REG_ADCC2 = 0x53, ++ PCF50633_REG_ADCC1 = 0x54, ++ PCF50633_REG_ADCS1 = 0x55, ++ PCF50633_REG_ADCS2 = 0x56, ++ PCF50633_REG_ADCS3 = 0x57, ++ /* reserved */ ++ PCF50633_REG_RTCSC = 0x59, /* Second */ ++ PCF50633_REG_RTCMN = 0x5a, /* Minute */ ++ PCF50633_REG_RTCHR = 0x5b, /* Hour */ ++ PCF50633_REG_RTCWD = 0x5c, /* Weekday */ ++ PCF50633_REG_RTCDT = 0x5d, /* Day */ ++ PCF50633_REG_RTCMT = 0x5e, /* Month */ ++ PCF50633_REG_RTCYR = 0x5f, /* Year */ ++ PCF50633_REG_RTCSCA = 0x60, /* Alarm Second */ ++ PCF50633_REG_RTCMNA = 0x61, /* Alarm Minute */ ++ PCF50633_REG_RTCHRA = 0x62, /* Alarm Hour */ ++ PCF50633_REG_RTCWDA = 0x63, /* Alarm Weekday */ ++ PCF50633_REG_RTCDTA = 0x64, /* Alarm Day */ ++ PCF50633_REG_RTCMTA = 0x65, /* Alarm Month */ ++ PCF50633_REG_RTCYRA = 0x66, /* Alarm Year */ ++ ++ PCF50633_REG_MEMBYTE0 = 0x67, ++ PCF50633_REG_MEMBYTE1 = 0x68, ++ PCF50633_REG_MEMBYTE2 = 0x69, ++ PCF50633_REG_MEMBYTE3 = 0x6a, ++ PCF50633_REG_MEMBYTE4 = 0x6b, ++ PCF50633_REG_MEMBYTE5 = 0x6c, ++ PCF50633_REG_MEMBYTE6 = 0x6d, ++ PCF50633_REG_MEMBYTE7 = 0x6e, ++ /* reserved */ ++ PCF50633_REG_DCDCPFM = 0x84, ++ __NUM_PCF50633_REGS ++}; ++ ++enum pcf50633_reg_int1 { ++ PCF50633_INT1_ADPINS = 0x01, /* Adapter inserted */ ++ PCF50633_INT1_ADPREM = 0x02, /* Adapter removed */ ++ PCF50633_INT1_USBINS = 0x04, /* USB inserted */ ++ PCF50633_INT1_USBREM = 0x08, /* USB removed */ ++ /* reserved */ ++ PCF50633_INT1_ALARM = 0x40, /* RTC alarm time is reached */ ++ PCF50633_INT1_SECOND = 0x80, /* RTC periodic second interrupt */ ++}; ++ ++enum pcf50633_reg_int2 { ++ PCF50633_INT2_ONKEYR = 0x01, /* ONKEY rising edge */ ++ PCF50633_INT2_ONKEYF = 0x02, /* ONKEY falling edge */ ++ PCF50633_INT2_EXTON1R = 0x04, /* EXTON1 rising edge */ ++ PCF50633_INT2_EXTON1F = 0x08, /* EXTON1 falling edge */ ++ PCF50633_INT2_EXTON2R = 0x10, /* EXTON2 rising edge */ ++ PCF50633_INT2_EXTON2F = 0x20, /* EXTON2 falling edge */ ++ PCF50633_INT2_EXTON3R = 0x40, /* EXTON3 rising edge */ ++ PCF50633_INT2_EXTON3F = 0x80, /* EXTON3 falling edge */ ++}; ++ ++enum pcf50633_reg_int3 { ++ PCF50633_INT3_BATFULL = 0x01, /* Battery full */ ++ PCF50633_INT3_CHGHALT = 0x02, /* Charger halt */ ++ PCF50633_INT3_THLIMON = 0x04, ++ PCF50633_INT3_THLIMOFF = 0x08, ++ PCF50633_INT3_USBLIMON = 0x10, ++ PCF50633_INT3_USBLIMOFF = 0x20, ++ PCF50633_INT3_ADCRDY = 0x40, /* ADC conversion finished */ ++ PCF50633_INT3_ONKEY1S = 0x80, /* ONKEY pressed 1 second */ ++}; ++ ++enum pcf50633_reg_int4 { ++ PCF50633_INT4_LOWSYS = 0x01, ++ PCF50633_INT4_LOWBAT = 0x02, ++ PCF50633_INT4_HIGHTMP = 0x04, ++ PCF50633_INT4_AUTOPWRFAIL = 0x08, ++ PCF50633_INT4_DWN1PWRFAIL = 0x10, ++ PCF50633_INT4_DWN2PWRFAIL = 0x20, ++ PCF50633_INT4_LEDPWRFAIL = 0x40, ++ PCF50633_INT4_LEDOVP = 0x80, ++}; ++ ++enum pcf50633_reg_int5 { ++ PCF50633_INT4_LDO1PWRFAIL = 0x01, ++ PCF50633_INT4_LDO2PWRFAIL = 0x02, ++ PCF50633_INT4_LDO3PWRFAIL = 0x04, ++ PCF50633_INT4_LDO4PWRFAIL = 0x08, ++ PCF50633_INT4_LDO5PWRFAIL = 0x10, ++ PCF50633_INT4_LDO6PWRFAIL = 0x20, ++ PCF50633_INT4_HCLDOPWRFAIL = 0x40, ++ PCF50633_INT4_HCLDOOVL = 0x80, ++}; ++ ++enum pcf50633_reg_oocwake { ++ PCF50633_OOCWAKE_ONKEY = 0x01, ++ PCF50633_OOCWAKE_EXTON1 = 0x02, ++ PCF50633_OOCWAKE_EXTON2 = 0x04, ++ PCF50633_OOCWAKE_EXTON3 = 0x08, ++ PCF50633_OOCWAKE_RTC = 0x10, ++ /* reserved */ ++ PCF50633_OOCWAKE_USB = 0x40, ++ PCF50633_OOCWAKE_ADP = 0x80, ++}; ++ ++enum pcf50633_reg_mbcc1 { ++ PCF50633_MBCC1_CHGENA = 0x01, /* Charger enable */ ++ PCF50633_MBCC1_AUTOSTOP = 0x02, ++ PCF50633_MBCC1_AUTORES = 0x04, /* automatic resume */ ++ PCF50633_MBCC1_RESUME = 0x08, /* explicit resume cmd */ ++ PCF50633_MBCC1_RESTART = 0x10, /* restart charging */ ++ PCF50633_MBCC1_PREWDTIME_60M = 0x20, /* max. precharging time */ ++ PCF50633_MBCC1_WDTIME_1H = 0x00, ++ PCF50633_MBCC1_WDTIME_2H = 0x40, ++ PCF50633_MBCC1_WDTIME_4H = 0x80, ++ PCF50633_MBCC1_WDTIME_6H = 0xc0, ++}; ++#define PCF50633_MBCC1_WDTIME_MASK 0xc0 ++ ++enum pcf50633_reg_mbcc2 { ++ PCF50633_MBCC2_VBATCOND_2V7 = 0x00, ++ PCF50633_MBCC2_VBATCOND_2V85 = 0x01, ++ PCF50633_MBCC2_VBATCOND_3V = 0x02, ++ PCF50633_MBCC2_VBATCOND_3V15 = 0x03, ++ PCF50633_MBCC2_VMAX_4V = 0x00, ++ PCF50633_MBCC2_VMAX_4V20 = 0x28, ++ PCF50633_MBCC2_VRESDEBTIME_64S = 0x80, /* debounce time (32/64sec) */ ++}; ++#define PCF50633_MBCC2_VBATCOND_MASK 0x03 ++#define PCF50633_MBCC2_VMAX_MASK 0x3c ++ ++#define PCF50633_OOCSTAT_ONKEY 0x01 ++ ++/* this is to be provided by the board implementation */ ++extern const u_int8_t pcf50633_initial_regs[__NUM_PCF50633_REGS]; ++ ++void pcf50633_reg_write(u_int8_t reg, u_int8_t val); ++ ++u_int8_t pcf50633_reg_read(u_int8_t reg); ++ ++void pcf50633_reg_set_bit_mask(u_int8_t reg, u_int8_t mask, u_int8_t val); ++void pcf50633_reg_clear_bits(u_int8_t reg, u_int8_t bits); ++ ++void pcf50633_init(void); ++void pcf50633_usb_maxcurrent(unsigned int ma); ++ ++#endif /* _PCF50633_H */ ++ +Index: u-boot/drivers/pcf50633.c +=================================================================== +--- /dev/null ++++ u-boot/drivers/pcf50633.c +@@ -0,0 +1,142 @@ ++#include ++ ++#ifdef CONFIG_DRIVER_PCF50633 ++ ++#include ++#include ++#include ++#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) ++ ++#define PCF50633_I2C_ADDR 0x73 ++ ++void __pcf50633_reg_write(u_int8_t reg, u_int8_t val) ++{ ++ i2c_write(PCF50633_I2C_ADDR, reg, 1, &val, 1); ++} ++ ++u_int8_t __pcf50633_reg_read(u_int8_t reg) ++{ ++ u_int8_t tmp; ++ i2c_read(PCF50633_I2C_ADDR, reg, 1, &tmp, 1); ++ return tmp; ++} ++ ++void pcf50633_reg_write(u_int8_t reg, u_int8_t val) ++{ ++ unsigned long flags; ++ ++ local_irq_save(flags); ++ __pcf50633_reg_write(reg, val); ++ local_irq_restore(flags); ++} ++ ++u_int8_t pcf50633_reg_read(u_int8_t reg) ++{ ++ unsigned long flags; ++ u_int8_t tmp; ++ ++ local_irq_save(flags); ++ tmp = __pcf50633_reg_read(reg); ++ local_irq_restore(flags); ++ ++ return tmp; ++} ++ ++void pcf50633_reg_set_bit_mask(u_int8_t reg, u_int8_t mask, u_int8_t val) ++{ ++ unsigned long flags; ++ u_int8_t tmp; ++ ++ local_irq_save(flags); ++ tmp = __pcf50633_reg_read(reg); ++ __pcf50633_reg_write(reg, (val & mask) | (tmp & ~mask)); ++ local_irq_restore(flags); ++} ++ ++void pcf50633_reg_clear_bits(u_int8_t reg, u_int8_t bits) ++{ ++ unsigned long flags; ++ u_int8_t tmp; ++ ++ local_irq_save(flags); ++ tmp = pcf50633_reg_read(reg); ++ pcf50633_reg_write(reg, (tmp & ~bits)); ++ local_irq_restore(flags); ++} ++ ++static const u_int8_t regs_invalid[] = { ++ PCF50633_REG_VERSION, ++ PCF50633_REG_VARIANT, ++ PCF50633_REG_OOCSHDWN, ++ PCF50633_REG_INT1, ++ PCF50633_REG_INT2, ++ PCF50633_REG_INT3, ++ PCF50633_REG_INT4, ++ PCF50633_REG_INT5, ++ PCF50633_REG_OOCSTAT, ++ 0x2c, ++ PCF50633_REG_DCDCSTAT, ++ PCF50633_REG_LDOSTAT, ++ PCF50633_REG_MBCS1, ++ PCF50633_REG_MBCS2, ++ PCF50633_REG_MBCS3, ++ PCF50633_REG_ALMDATA, ++ 0x51, ++ /* 0x55 ... 0x6e: don't write */ ++ /* 0x6f ... 0x83: reserved */ ++}; ++#define PCF50633_LAST_REG 0x55 ++ ++static int reg_is_invalid(u_int8_t reg) ++{ ++ int i; ++ ++ /* all registers above 0x55 (ADCS1) except 0x84 */ ++ if (reg == PCF50633_REG_DCDCPFM) ++ return 0; ++ if (reg >= 0x55) ++ return 1; ++ ++ for (i = 0; i < ARRAY_SIZE(regs_invalid); i++) { ++ if (regs_invalid[i] > reg) ++ return 0; ++ if (regs_invalid[i] == reg) ++ return 1; ++ } ++ ++ return 0; ++} ++ ++ ++/* initialize PCF50633 register set */ ++void pcf50633_init(void) ++{ ++ unsigned long flags; ++ u_int8_t i; ++ ++ local_irq_save(flags); ++ for (i = 0; i < PCF50633_LAST_REG; i++) { ++ if (reg_is_invalid(i)) ++ continue; ++ __pcf50633_reg_write(i, pcf50633_initial_regs[i]); ++ } ++ local_irq_restore(flags); ++} ++ ++void pcf50633_usb_maxcurrent(unsigned int ma) ++{ ++ u_int8_t val; ++ ++ if (ma < 100) ++ val = 0x03; ++ else if (ma < 500) ++ val = 0x00; ++ else if (ma < 1000) ++ val = 0x01; ++ else ++ val = 0x02; ++ ++ return pcf50633_reg_set_bit_mask(PCF50633_REG_MBCC7, 0x03, val); ++} ++ ++#endif /* CONFIG DRIVER_PCF50633 */ +Index: u-boot/board/neo1973/common/lowlevel_init.S +=================================================================== +--- u-boot.orig/board/neo1973/common/lowlevel_init.S ++++ u-boot/board/neo1973/common/lowlevel_init.S +@@ -49,7 +49,7 @@ + #define WAIT (0x1<<2) + #define UBLB (0x1<<3) + +-#define B1_BWSCON (DW32) ++#define B1_BWSCON (DW16 + WAIT + UBLB) + #define B2_BWSCON (DW16) + #define B3_BWSCON (DW16 + WAIT + UBLB) + #define B4_BWSCON (DW16) +@@ -68,9 +68,9 @@ + + /* BANK1CON */ + #define B1_Tacs 0x0 /* 0clk */ +-#define B1_Tcos 0x0 /* 0clk */ +-#define B1_Tacc 0x7 /* 14clk */ +-#define B1_Tcoh 0x0 /* 0clk */ ++#define B1_Tcos 0x1 /* 1clk */ ++#define B1_Tacc 0x4 /* 4clk */ ++#define B1_Tcoh 0x1 /* 1clk */ + #define B1_Tah 0x0 /* 0clk */ + #define B1_Tacp 0x0 + #define B1_PMC 0x0 +@@ -112,7 +112,7 @@ + #if defined (CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4) + #define B6_SCAN 0x1 /* 9bit */ + #elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3) || \ +- defined(CONFIG_ARCH_GTA01B_v4) ++ defined(CONFIG_ARCH_GTA01B_v4) || defined(CONFIG_ARCH_GTA02_v1) + #define B6_SCAN 0x2 /* 10bit */ + #endif + +@@ -165,6 +165,18 @@ + str r1, [r0] + #endif + ++#if defined(CONFIG_ARCH_GTA02_v1) ++ /* enable KEEPACT to make sure PMU keeps us alive */ ++ ldr r0, =0x56000000 /* GPJ base */ ++ ldr r1, [r0, #0xd0] /* GPJCON */ ++ orr r1, r1, #(1 << 6) ++ str r1, [r0, #0xd0] ++ ++ ldr r1, [r0, #0xd4] /* GPJDAT */ ++ orr r1, r1, #(1 << 3) ++ str r1, [r0, #0xd4] ++#endif ++ + /* everything is fine now */ + mov pc, lr + +Index: u-boot/board/neo1973/gta02/pcf50633.c +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/gta02/pcf50633.c +@@ -0,0 +1,91 @@ ++ ++#include ++#include ++ ++/* initial register set for PCF50633 in Neo1973 GTA02 devices */ ++const u_int8_t pcf50633_initial_regs[__NUM_PCF50633_REGS] = { ++ /* gap */ ++ [PCF50633_REG_INT1M] = PCF50633_INT1_SECOND, ++ [PCF50633_REG_INT2M] = PCF50633_INT2_EXTON3F | ++ PCF50633_INT2_EXTON3R | ++ PCF50633_INT2_EXTON2F | ++ PCF50633_INT2_EXTON2R | ++ PCF50633_INT2_EXTON1R | ++ PCF50633_INT2_EXTON1F, ++ [PCF50633_REG_INT3M] = PCF50633_INT3_ADCRDY, ++ [PCF50633_REG_INT4M] = 0x00, ++ [PCF50633_REG_INT5M] = 0x00, ++ ++ [PCF50633_REG_OOCWAKE] = 0xd3, /* wake from ONKEY,EXTON!,RTC,USB,ADP */ ++ [PCF50633_REG_OOCTIM1] = 0xaa, /* debounce 14ms everything */ ++ [PCF50633_REG_OOCTIM2] = 0x4a, ++ [PCF50633_REG_OOCMODE] = 0x55, ++ [PCF50633_REG_OOCCTL] = 0x44, ++ ++ [PCF50633_REG_GPIOCTL] = 0x01, /* only GPIO1 is input */ ++ [PCF50633_REG_GPIO2CFG] = 0x00, ++ [PCF50633_REG_GPIO3CFG] = 0x00, ++ [PCF50633_REG_GPOCFG] = 0x00, ++ ++ [PCF50633_REG_SVMCTL] = 0x08, /* 3.10V SYS voltage thresh. */ ++ [PCF50633_REG_BVMCTL] = 0x02, /* 2.80V BAT voltage thresh. */ ++ ++ [PCF50633_REG_STBYCTL1] = 0x00, ++ [PCF50633_REG_STBYCTL2] = 0x00, ++ ++ [PCF50633_REG_DEBPF1] = 0xff, ++ [PCF50633_REG_DEBPF2] = 0xff, ++ [PCF50633_REG_DEBPF2] = 0x3f, ++ ++ [PCF50633_REG_AUTOOUT] = 0x6b, /* 3.300V */ ++ [PCF50633_REG_AUTOENA] = 0x01, /* always on */ ++ [PCF50633_REG_AUTOCTL] = 0x00, /* automatic up/down operation */ ++ [PCF50633_REG_AUTOMXC] = 0x0a, /* 400mA at startup FIXME */ ++ ++ [PCF50633_REG_DOWN1OUT] = 0x1b, /* 1.3V (0x1b * .025V + 0.625V) */ ++ [PCF50633_REG_DOWN1ENA] = 0x02, /* enabled if GPIO1 = HIGH */ ++ [PCF50633_REG_DOWN1CTL] = 0x00, /* no DVM */ ++ [PCF50633_REG_DOWN1MXC] = 0x22, /* limit to 510mA at startup */ ++ ++ [PCF50633_REG_DOWN2OUT] = 0x2f, /* 1.8V (0x2f * .025V + 0.625V) */ ++ [PCF50633_REG_DOWN2ENA] = 0x02, /* enabled if GPIO1 = HIGH */ ++ [PCF50633_REG_DOWN2CTL] = 0x00, /* no DVM */ ++ [PCF50633_REG_DOWN2MXC] = 0x22, /* limit to 510mA at startup */ ++ ++ [PCF50633_REG_MEMLDOOUT] = 0x00, ++ [PCF50633_REG_MEMLDOENA] = 0x00, ++ ++ [PCF50633_REG_LEDOUT] = 0x2f, /* full backlight power */ ++ [PCF50633_REG_LEDENA] = 0x02, /* enabled if GPIO1 = HIGH */ ++ [PCF50633_REG_LEDCTL] = 0x05, /* ovp enabled, ocp 500mA */ ++ [PCF50633_REG_LEDDIM] = 0x20, /* dimming curve */ ++ ++ [PCF50633_REG_LDO1OUT] = 0x04, /* 1.3V (4 * 0.1V + 0.9V) */ ++ [PCF50633_REG_LDO1ENA] = 0x01, /* always on */ ++ ++ [PCF50633_REG_LDO2OUT] = 0x18, /* 3.3V (24 * 0.1V + 0.9V) */ ++ [PCF50633_REG_LDO2ENA] = 0x02, /* enabled if GPIO1 = HIGH */ ++ ++ [PCF50633_REG_LDO3OUT] = 0x15, /* 3.0V (21 * 0.1V + 0.9V) */ ++ [PCF50633_REG_LDO3ENA] = 0x02, /* enabled if GPIO1 = HIGH */ ++ ++ [PCF50633_REG_LDO4ENA] = 0x00, ++ [PCF50633_REG_LDO5ENA] = 0x00, ++ [PCF50633_REG_LDO6ENA] = 0x00, ++ ++ [PCF50633_REG_HCLDOOUT] = 0x18, /* 3.3V (24 * 0.1V + 0.9V) */ ++ [PCF50633_REG_HCLDOENA] = 0x00, /* off by default*/ ++ ++ [PCF50633_REG_DCDCPFM] = 0x00, /* off by default*/ ++ ++ [PCF50633_REG_MBCC1] = 0xe6, ++ [PCF50633_REG_MBCC2] = 0x28, /* Vbatconid=2.7V, Vmax=4.20V */ ++ [PCF50633_REG_MBCC3] = 0x19, /* 25/255 == 98mA pre-charge */ ++ [PCF50633_REG_MBCC4] = 0xff, /* 255/255 == 1A adapter fast */ ++ [PCF50633_REG_MBCC5] = 0x7f, /* 127/255 == 500mA usb fast */ ++ [PCF50633_REG_MBCC6] = 0x00, /* cutoff current 1/32 * Ichg */ ++ [PCF50633_REG_MBCC7] = 0x00, /* 1.6A max bat curr, USB 100mA */ ++ [PCF50633_REG_MBCC8] = 0x00, ++ ++ [PCF50633_REG_BBCCTL] = 0x19, /* 3V, 200uA, on */ ++}; +Index: u-boot/board/neo1973/gta02/config.mk +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/gta02/config.mk +@@ -0,0 +1,32 @@ ++# ++# (C) Copyright 2002 ++# Gary Jennejohn, DENX Software Engineering, ++# David Mueller, ELSOFT AG, ++# ++# FIC Neo1973 GTA01 board with S3C2410X (ARM920T) cpu ++# ++# see http://www.samsung.com/ for more information on SAMSUNG ++# ++ ++# GTA01v3 has 1 bank of 64 MB SDRAM ++# GTA01v4 has 1 bank of 64 MB SDRAM ++# ++# 3000'0000 to 3400'0000 ++# we load ourself to 33F8'0000 ++# ++# GTA01Bv2 or later has 1 bank of 128 MB SDRAM ++# ++# 3000'0000 to 3800'0000 ++# we load ourself to 37F8'0000 ++# ++# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 ++# optionally with a ramdisk at 3080'0000 ++# ++# download area is 3200'0000 or 3300'0000 ++ ++CONFIG_USB_DFU_VENDOR=0x1457 ++CONFIG_USB_DFU_PRODUCT=0x5119 ++ ++sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp ++ ++TEXT_BASE = 0x33F80000 +Index: u-boot/drivers/smedia3362.c +=================================================================== +--- /dev/null ++++ u-boot/drivers/smedia3362.c +@@ -0,0 +1,125 @@ ++/* ++ * (C) Copyright 2007 by OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++ ++#if defined(CONFIG_VIDEO_GLAMO3362) ++ ++#include ++#include "videomodes.h" ++#include ++#include "smedia3362.h" ++ ++/* ++ * Export Graphic Device ++ */ ++GraphicDevice smi; ++ ++ ++struct glamo_script { ++ u_int16_t reg; ++ u_int16_t val; ++} __attribute__((packed)); ++ ++/* from 'initial glamo 3365 script' */ ++static struct glamo_script gl3362_init_script[] = { ++ /* clock */ ++ { GLAMO_REG_CLOCK_MEMORY, 0x300a }, ++ { GLAMO_REG_CLOCK_LCD, 0x10aa }, ++ { GLAMO_REG_CLOCK_MMC, 0x100a }, ++ { GLAMO_REG_CLOCK_ISP, 0x32aa }, ++ { GLAMO_REG_CLOCK_JPEG, 0x100a }, ++ { GLAMO_REG_CLOCK_3D, 0x302a }, ++ { GLAMO_REG_CLOCK_2D, 0x302a }, ++ //{ GLAMO_REG_CLOCK_RISC1, 0x1aaa }, ++ //{ GLAMO_REG_CLOCK_RISC2, 0x002a }, ++ { GLAMO_REG_CLOCK_MPEG, 0x3aaa }, ++ { GLAMO_REG_CLOCK_MPROC, 0x12aa }, ++ { 0xfffe, 5 }, ++ { GLAMO_REG_CLOCK_HOST, 0x000d }, ++ { GLAMO_REG_CLOCK_MEMORY, 0x000a }I, ++ { GLAMO_REG_CLOCK_LCD, 0x00ee }, ++ { GLAMO_REG_CLOCK_MMC, 0x000a }, ++ { GLAMO_REG_CLOCK_ISP, 0x02aa }, ++ { GLAMO_REG_CLOCK_JPEG, 0x000a }, ++ { GLAMO_REG_CLOCK_3D, 0x002a }, ++ { GLAMO_REG_CLOCK_2D, 0x002a }, ++ //{ GLAMO_REG_CLOCK_RISC1, 0x0aaa }, ++ //{ GLAMO_REG_CLOCK_RISC2, 0x002a }, ++ { GLAMO_REG_CLOCK_MPEG, 0x0aaa }, ++ { GLAMO_REG_CLOCK_MPROC, 0x02aa }, ++ { 0xfffe, 5 }, ++ { GLAMO_REG_PLL_GEN1, 0x061a }, /* PLL1=50MHz, OSCI=32kHz */ ++ { GLAMO_REG_PLL_GEN3, 0x09c3 }, /* PLL2=80MHz, OSCI=32kHz */ ++ { 0xfffe, 5 }, ++ { GLAMO_REG_CLOCK_GEN5_1, 0x18ff }, ++ { GLAMO_REG_CLOCK_GEN5_2, 0x051f }, ++ { GLAMO_REG_CLOCK_GEN6, 0x2000 }, ++ { GLAMO_REG_CLOCK_GEN7, 0x0105 }, ++ { GLAMO_REG_CLOCK_GEN8, 0x0100 }, ++ { GLAMO_REG_CLOCK_GEN10, 0x0017 }, ++ { GLAMO_REG_CLOCK_GEN11, 0x0017 }, ++ ++ /* hostbus interface */ ++ { GLAMO_REG_HOSTBUS(1), 0x0e00 }, ++ { GLAMO_REG_HOSTBUS(2), 0x07ff }, ++ { GLAMO_REG_HOSTBUS(4), 0x0080 }, ++ { GLAMO_REG_HOSTBUS(5), 0x0244 }, ++ { GLAMO_REG_HOSTBUS(6), 0x0600 }, ++ { GLAMO_REG_HOSTBUS(12), 0xf00e }, ++ ++ /* memory */ ++ { GLAMO_REG_MEM_TYPE, 0x0874 }, /* VRAM 8Mbyte */ ++ { GLAMO_REG_MEM_GEN, 0xafaf }, ++ { GLAMO_REG_MEM_TIMING(1), 0x0108 }, ++ { GLAMO_REG_MEM_TIMING(2), 0x0010 }, ++ { GLAMO_REG_MEM_TIMING(3), 0x0000 }, ++ { GLAMO_REG_MEM_TIMING(4), 0x0000 }, ++ { GLAMO_REG_MEM_TIMING(5), 0x0000 }, ++ { GLAMO_REG_MEM_TIMING(6), 0x0000 }, ++ { GLAMO_REG_MEM_TIMING(7), 0x0000 }, ++ { GLAMO_REG_MEM_TIMING(8), 0x1002 }, ++ { GLAMO_REG_MEM_TIMING(9), 0x6006 }, ++ { GLAMO_REG_MEM_TIMING(10), 0x00ff }, ++ { GLAMO_REG_MEM_TIMING(11), 0x0001 }, ++ { GLAMO_REG_MEM_POWER1, 0x0020 }, ++ { GLAMO_REG_MEM_POWRE2, 0x0000 }, ++ { GLAMO_REG_MEM_DRAM1, 0x0000 }, ++ { 0xfffe, 1 }, ++ { GLAMO_REG_MEM_DRAM1, 0xc100 }, ++ { GLAMO_REG_MEM_DRAM2, 0x01d6 }, ++}; ++ ++static int glamo3362_init(void) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(gl3362_init_script); i++) { ++ struct glamo_reg *reg = gl3362_init_script[i]; ++ ++ if (reg->reg == 0xfffe) ++ delay(reg->val); ++ else ++ gl3362_reg_write(reg->reg, reg->val); ++ } ++ /* FIXME */ ++} ++ ++#endif /* CONFIG_VIDEO_GLAMO3362 */ +Index: u-boot/drivers/Makefile +=================================================================== +--- u-boot.orig/drivers/Makefile ++++ u-boot/drivers/Makefile +@@ -50,7 +50,7 @@ + usbdcore.o usbdfu.o usbdcore_ep0.o usbdcore_omap1510.o usbdcore_s3c2410.o usbtty.o \ + videomodes.o w83c553f.o \ + ks8695eth.o \ +- pcf50606.o \ ++ pcf50606.o pcf50633.o \ + pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \ + rpx_pcmcia.o \ + fsl_i2c.o s3c2410_fb.o +Index: u-boot/common/cmd_nand.c +=================================================================== +--- u-boot.orig/common/cmd_nand.c ++++ u-boot/common/cmd_nand.c +@@ -208,8 +208,10 @@ + putc('\n'); + for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) { + if (nand_info[i].name) +- printf("Device %d: %s, sector size %lu KiB\n", ++ printf("Device %d: %s, page size %lu, " ++ "sector size %lu KiB\n", + i, nand_info[i].name, ++ nand_info[i].oobblock, + nand_info[i].erasesize >> 10); + } + return 0; +Index: u-boot/drivers/nand/nand_ids.c +=================================================================== +--- u-boot.orig/drivers/nand/nand_ids.c ++++ u-boot/drivers/nand/nand_ids.c +@@ -67,7 +67,7 @@ + + {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0}, + +- {"NAND 512MiB 3,3V 8-bit", 0xDC, 512, 512, 0x4000, 0}, ++ //{"NAND 512MiB 3,3V 8-bit", 0xDC, 512, 512, 0x4000, 0}, + + /* These are the new chips with large page size. The pagesize + * and the erasesize is determined from the extended id bytes +Index: u-boot/board/neo1973/common/udc.c +=================================================================== +--- u-boot.orig/board/neo1973/common/udc.c ++++ u-boot/board/neo1973/common/udc.c +@@ -3,6 +3,7 @@ + #include + #include + #include ++#include + + void udc_ctrl(enum usbd_event event, int param) + { +@@ -23,6 +24,11 @@ + defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3) || \ + defined(CONFIG_ARCH_GTA01B_v4) + pcf50606_charge_autofast(param); ++#elif defined(CONFIG_ARCH_GTA02_v1) ++ if (param) ++ pcf50633_usb_maxcurrent(500); ++ else ++ pcf50633_usb_maxcurrent(0); + #endif + break; + default: diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-hxd8.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-hxd8.patch new file mode 100644 index 0000000000..f85fdea836 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-hxd8.patch @@ -0,0 +1,1169 @@ +Patch to add HXD8 support + +Index: u-boot/Makefile +=================================================================== +--- u-boot.orig/Makefile ++++ u-boot/Makefile +@@ -2026,6 +2026,9 @@ + qt2410_config : unconfig + @./mkconfig $(@:_config=) arm arm920t qt2410 NULL s3c24x0 + ++hxd8_config : unconfig ++ @$(MKCONFIG) $(@:_config=) arm arm920t hxd8 NULL s3c24x0 ++ + scb9328_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t scb9328 NULL imx + +Index: u-boot/board/hxd8/Makefile +=================================================================== +--- /dev/null ++++ u-boot/board/hxd8/Makefile +@@ -0,0 +1,65 @@ ++# ++# (C) Copyright 2000-2006 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).a ++ ++COBJS := hxd8.o udc.o pcf50606.o ++SOBJS := lowlevel_init.o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++all: $(LIB) lowevel_foo.bin ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) ++ ++lowlevel_foo.o: lowlevel_foo.S ++ $(CC) -c -DTEXT_BASE=0x33F80000 -march=armv4 \ ++ -o lowlevel_foo.o lowlevel_foo.S ++ ++lowlevel_foo: lowlevel_foo.o lowlevel_init.o lowlevel_foo.lds ++ $(LD) -T ./lowlevel_foo.lds -Ttext 0x33f80000 -Bstatic \ ++ lowlevel_init.o lowlevel_foo.o -o lowlevel_foo ++ ++lowevel_foo.bin: lowlevel_foo ++ $(CROSS_COMPILE)objcopy --gap-fill=0xff -O binary \ ++ lowlevel_foo lowlevel_foo.bin ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak .depend ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +Index: u-boot/board/hxd8/hxd8.c +=================================================================== +--- /dev/null ++++ u-boot/board/hxd8/hxd8.c +@@ -0,0 +1,189 @@ ++/* ++ * (C) Copyright 2007 by OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * (C) Copyright 2002 ++ * Sysgo Real-Time Solutions, GmbH ++ * Marius Groeger ++ * ++ * (C) Copyright 2002 ++ * David Mueller, ELSOFT AG, ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#define FCLK_SPEED 1 ++ ++#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ ++#define M_MDIV 0xC3 ++#define M_PDIV 0x4 ++#define M_SDIV 0x1 ++#elif FCLK_SPEED==1 ++#if 0 ++#define M_MDIV 0x6e /* Fout = 399.65MHz */ ++#define M_PDIV 0x3 ++#define M_SDIV 0x1 ++#else ++#define M_MDIV 0x61 /* Fout = 296.35MHz due to wrong PLL capacitors */ ++#define M_PDIV 0x1 ++#define M_SDIV 0x2 ++#endif ++#endif ++ ++#define USB_CLOCK 1 ++ ++#if USB_CLOCK==0 ++#define U_M_MDIV 0xA1 ++#define U_M_PDIV 0x3 ++#define U_M_SDIV 0x1 ++#elif USB_CLOCK==1 ++#define U_M_MDIV 0x3c ++#define U_M_PDIV 0x4 ++#define U_M_SDIV 0x2 ++#endif ++ ++static inline void delay (unsigned long loops) ++{ ++ __asm__ volatile ("1:\n" ++ "subs %0, %1, #1\n" ++ "bne 1b":"=r" (loops):"0" (loops)); ++} ++ ++/* ++ * Miscellaneous platform dependent initialisations ++ */ ++ ++int board_init (void) ++{ ++ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ ++ /* to reduce PLL lock time, adjust the LOCKTIME register */ ++ clk_power->LOCKTIME = 0xFFFFFF; ++ ++ /* configure MPLL */ ++ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); ++ ++ /* some delay between MPLL and UPLL */ ++ delay (4000); ++ ++ /* configure UPLL */ ++ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); ++ ++ /* some delay between MPLL and UPLL */ ++ delay (8000); ++ ++ /* set up the I/O ports */ ++ gpio->GPACON = 0x005E0FFE; ++ gpio->GPADAT = 0x0001C000; ++ gpio->GPBCON = 0x00045542; ++ gpio->GPBUP = 0x000007FF; ++ gpio->GPCCON = 0xAAAA02A9; ++ gpio->GPCUP = 0x0000FFFF; ++ gpio->GPDCON = 0xAAAAAAAA; ++ gpio->GPDUP = 0x0000FFFF; ++ gpio->GPECON = 0xAAAAAAAA; ++ gpio->GPEUP = 0x0000FFFF; ++ gpio->GPFCON = 0x0000AAA9; ++ gpio->GPFUP = 0x000000FF; ++ gpio->GPGCON = 0x027D0316; ++ gpio->GPGUP = 0x0000FFFF; ++ gpio->GPHCON = 0x0014AAAA; ++ gpio->GPHUP = 0x000007FF; ++ gpio->GPJCON = 0x00000000; ++ ++ /* USB CHG enable */ ++ gpio->GPGDAT |= ( 1 << 11); ++#if 0 ++ /* USB Device Part */ ++ /*GPGCON is reset for USB Device */ ++ gpio->GPGCON = (gpio->GPGCON & ~(3 << 24)) | (1 << 24); /* Output Mode */ ++ gpio->GPGUP = gpio->GPGUP | ( 1 << 12); /* Pull up disable */ ++ ++ gpio->GPGDAT |= ( 1 << 12); ++ gpio->GPGDAT &= ~( 1 << 12); ++ udelay(20000); ++ gpio->GPGDAT |= ( 1 << 12); ++#endif ++ ++ /* arch number of SMDK2440-Board */ ++ gd->bd->bi_arch_number = MACH_TYPE_HXD8; ++ ++ /* adress of boot parameters */ ++ gd->bd->bi_boot_params = 0x30000100; ++ ++ icache_enable(); ++ dcache_enable(); ++ ++ return 0; ++} ++ ++void board_video_init(GraphicDevice *pGD) ++{ ++ S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD(); ++ ++ lcd->LCDCON1 = 0x0000057b; ++ lcd->LCDCON2 = 0x0143c049; ++ lcd->LCDCON3 = 0x0009df01; ++ lcd->LCDCON4 = 0x00000028; ++ lcd->LCDCON5 = 0x00000b08; ++ ++ lcd->TPAL = 0x01202020; ++ ++ //lcd->LCDCON5 |= (0x01 << 3); ++} ++ ++int board_late_init(void) ++{ ++ /* Initialize the Power Management Unit with a safe register set */ ++ pcf50606_init(); ++ ++ return 0; ++} ++ ++int dram_init(void) ++{ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; ++ ++ return 0; ++} ++ ++u_int32_t get_board_rev(void) ++{ ++ return 0x00000110; ++} ++ ++/* The sum of all part_size[]s must equal to the NAND size, i.e., 0x4000000. ++ "initrd" is sized such that it can hold two uncompressed 16 bit 640*480 ++ images: 640*480*2*2 = 1228800 < 1245184. */ ++ ++unsigned int dynpart_size[] = { ++ CFG_UBOOT_SIZE, 0x20000, 0x200000, 0xa0000, 0x3fd00000, 0 }; ++char *dynpart_names[] = { ++ "u-boot", "u-boot_env", "kernel", "splash", "rootfs", NULL }; ++ +Index: u-boot/board/hxd8/lowlevel_init.S +=================================================================== +--- /dev/null ++++ u-boot/board/hxd8/lowlevel_init.S +@@ -0,0 +1,171 @@ ++/* ++ * Memory Setup stuff - taken from blob memsetup.S ++ * ++ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and ++ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) ++ * ++ * Modified for the FIC HXD8 by Harald Welte ++ * (C) Copyright 2007 by OpenMoko, Inc. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++ ++#include ++#include ++ ++ ++/* some parameters for the board */ ++ ++/* ++ * ++ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S ++ * ++ * Copyright (C) 2002 Samsung Electronics SW.LEE ++ * ++ */ ++ ++#define BWSCON 0x48000000 ++ ++/* BWSCON */ ++#define DW8 (0x0) ++#define DW16 (0x1) ++#define DW32 (0x2) ++#define WAIT (0x1<<2) ++#define UBLB (0x1<<3) ++ ++#define B1_BWSCON (DW32) ++#define B2_BWSCON (DW16) ++#define B3_BWSCON (DW16 + WAIT + UBLB) ++#define B4_BWSCON (DW16) ++#define B5_BWSCON (DW16) ++#define B6_BWSCON (DW32) ++#define B7_BWSCON (DW32) ++ ++/* BANK0CON */ ++#define B0_Tacs 0x0 /* 0clk */ ++#define B0_Tcos 0x0 /* 0clk */ ++#define B0_Tacc 0x7 /* 14clk */ ++#define B0_Tcoh 0x0 /* 0clk */ ++#define B0_Tah 0x0 /* 0clk */ ++#define B0_Tacp 0x0 ++#define B0_PMC 0x0 /* normal */ ++ ++/* BANK1CON */ ++#define B1_Tacs 0x0 /* 0clk */ ++#define B1_Tcos 0x0 /* 0clk */ ++#define B1_Tacc 0x7 /* 14clk */ ++#define B1_Tcoh 0x0 /* 0clk */ ++#define B1_Tah 0x0 /* 0clk */ ++#define B1_Tacp 0x0 ++#define B1_PMC 0x0 ++ ++#define B2_Tacs 0x0 ++#define B2_Tcos 0x0 ++#define B2_Tacc 0x7 ++#define B2_Tcoh 0x0 ++#define B2_Tah 0x0 ++#define B2_Tacp 0x0 ++#define B2_PMC 0x0 ++ ++#define B3_Tacs 0x0 /* 0clk */ ++#define B3_Tcos 0x3 /* 4clk */ ++#define B3_Tacc 0x7 /* 14clk */ ++#define B3_Tcoh 0x1 /* 1clk */ ++#define B3_Tah 0x0 /* 0clk */ ++#define B3_Tacp 0x3 /* 6clk */ ++#define B3_PMC 0x0 /* normal */ ++ ++#define B4_Tacs 0x0 /* 0clk */ ++#define B4_Tcos 0x0 /* 0clk */ ++#define B4_Tacc 0x7 /* 14clk */ ++#define B4_Tcoh 0x0 /* 0clk */ ++#define B4_Tah 0x0 /* 0clk */ ++#define B4_Tacp 0x0 ++#define B4_PMC 0x0 /* normal */ ++ ++#define B5_Tacs 0x0 /* 0clk */ ++#define B5_Tcos 0x0 /* 0clk */ ++#define B5_Tacc 0x7 /* 14clk */ ++#define B5_Tcoh 0x0 /* 0clk */ ++#define B5_Tah 0x0 /* 0clk */ ++#define B5_Tacp 0x0 ++#define B5_PMC 0x0 /* normal */ ++ ++#define B6_MT 0x3 /* SDRAM */ ++#define B6_Trcd 0x1 /* 3clk */ ++#define B6_SCAN 0x2 /* 10bit */ ++ ++#define B7_MT 0x3 /* SDRAM */ ++#define B7_Trcd 0x1 /* 3clk */ ++#define B7_SCAN 0x1 /* 9bit */ ++ ++/* REFRESH parameter */ ++#define REFEN 0x1 /* Refresh enable */ ++#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ ++#define Trp 0x1 /* 3clk */ ++#define Trc 0x3 /* 7clk */ ++#define Tchr 0x2 /* 3clk */ ++#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ ++/**************************************/ ++ ++_TEXT_BASE: ++ .word TEXT_BASE ++ ++.globl lowlevel_init ++lowlevel_init: ++ /* memory control configuration */ ++ /* make r0 relative the current location so that it */ ++ /* reads SMRDATA out of FLASH rather than memory ! */ ++ ldr r0, =SMRDATA ++ ldr r1, _TEXT_BASE ++ sub r0, r0, r1 ++ ldr r1, =BWSCON /* Bus Width Status Controller */ ++ add r2, r0, #13*4 ++0: ++ ldr r3, [r0], #4 ++ str r3, [r1], #4 ++ cmp r2, r0 ++ bne 0b ++ ++ /* setup asynchronous bus mode */ ++ mrc p15, 0, r1 ,c1 ,c0, 0 ++ orr r1, r1, #0xc0000000 ++ mcr p15, 0, r1, c1, c0, 0 ++ ++ /* everything is fine now */ ++ mov pc, lr ++ ++ .ltorg ++/* the literal pools origin */ ++ ++SMRDATA: ++ .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) ++ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ++ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ++ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ++ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ++ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ++ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ++ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ++ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ++ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) ++ .word 0x32 ++ .word 0x30 ++ .word 0x30 +Index: u-boot/include/configs/hxd8.h +=================================================================== +--- /dev/null ++++ u-boot/include/configs/hxd8.h +@@ -0,0 +1,277 @@ ++/* ++ * (C) Copyright 2007 OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * Configuation settings for the FIC HXD8 ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++/* we want to be able to start u-boot directly from within NAND flash */ ++#define CONFIG_LL_INIT_NAND_ONLY ++#define CONFIG_S3C2410_NAND_BOOT 1 ++#define CONFIG_S3C2410_NAND_SKIP_BAD 1 ++ ++#define CFG_UBOOT_SIZE 0x40000 /* size of u-boot, for NAND loading */ ++ ++/* ++ * High Level Configuration Options ++ * (easy to change) ++ */ ++#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ ++#define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2440 SoC */ ++#define CONFIG_SMDK2440 1 /* on a SAMSUNG SMDK2440 Board */ ++#define CONFIG_HXD8 1 /* on a FIC HXD8 Board */ ++ ++/* input clock of PLL */ ++#define CONFIG_SYS_CLK_FREQ 16934400/* the HXD8 has this input clock */ ++ ++ ++#define USE_920T_MMU 1 ++#define CONFIG_USE_IRQ 1 ++ ++/* ++ * Size of malloc() pool ++ */ ++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 2048*1024) ++ /* >> CFG_VIDEO_LOGO_MAX_SIZE */ ++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ ++ ++/* ++ * Hardware drivers ++ */ ++ ++/* ++ * select serial console configuration ++ */ ++#define CONFIG_SERIAL3 1 /* we use SERIAL 3 on HXD8 */ ++ ++/************************************************************ ++ * RTC ++ ************************************************************/ ++#define CONFIG_RTC_S3C24X0 1 ++ ++/* allow to overwrite serial and ethaddr */ ++#define CONFIG_ENV_OVERWRITE ++ ++#define CONFIG_BAUDRATE 115200 ++ ++/*********************************************************** ++ * Command definition ++ ***********************************************************/ ++#define CONFIG_COMMANDS (\ ++ CFG_CMD_BDI | \ ++ CFG_CMD_LOADS | \ ++ CFG_CMD_LAODB | \ ++ CFG_CMD_IMI | \ ++ CFG_CMD_CACHE | \ ++ CFG_CMD_MEMORY | \ ++ CFG_CMD_ENV | \ ++ /* CFG_CMD_IRQ | */ \ ++ CFG_CMD_BOOTD | \ ++ CFG_CMD_CONSOLE | \ ++ /* CFG_CMD_BMP | */ \ ++ CFG_CMD_ASKENV | \ ++ CFG_CMD_RUN | \ ++ CFG_CMD_ECHO | \ ++ CFG_CMD_I2C | \ ++ CFG_CMD_REGINFO | \ ++ CFG_CMD_IMMAP | \ ++ CFG_CMD_DATE | \ ++ CFG_CMD_AUTOSCRIPT | \ ++ CFG_CMD_BSP | \ ++ CFG_CMD_ELF | \ ++ CFG_CMD_MISC | \ ++ /* CFG_CMD_USB | */ \ ++ CFG_CMD_JFFS2 | \ ++ CFG_CMD_DIAG | \ ++ /* CFG_CMD_HWFLOW | */ \ ++ CFG_CMD_SAVES | \ ++ CFG_CMD_NAND | \ ++ CFG_CMD_PORTIO | \ ++ CFG_CMD_MMC | \ ++ CFG_CMD_FAT | \ ++ CFG_CMD_EXT2 | \ ++ 0) ++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ ++#include ++ ++#define CONFIG_BOOTDELAY 3 ++#define CONFIG_BOOTARGS "" ++#define CONFIG_BOOTCOMMAND "setenv bootargs ${bootargs_base} ${mtdparts}; nand read.e 0x32000000 kernel; bootm 0x32000000" ++ ++#define CONFIG_DOS_PARTITION 1 ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ ++/* what's this ? it's not used anywhere */ ++#define CONFIG_KGDB_SER_INDEX 3 /* which serial port to use */ ++#endif ++ ++/* ++ * Miscellaneous configurable options ++ */ ++#define CFG_LONGHELP /* undef to save memory */ ++#define CFG_PROMPT "HXD8 # " /* Monitor Command Prompt */ ++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ ++#define CFG_MAXARGS 64 /* max number of command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ ++ ++#define CFG_MEMTEST_START 0x30000000 /* memtest works on */ ++#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ ++ ++#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ ++ ++#define CFG_LOAD_ADDR 0x33000000 /* default load address */ ++ ++/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ ++/* it to wrap 100 times (total 1562500) to get 1 sec. */ ++#define CFG_HZ 1562500 ++ ++/* valid baudrates */ ++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } ++ ++/*----------------------------------------------------------------------- ++ * Stack sizes ++ * ++ * The stack sizes are set up in start.S using the settings below ++ */ ++#define CONFIG_STACKSIZE (512*1024) /* regular stack */ ++#ifdef CONFIG_USE_IRQ ++#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */ ++#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ ++#endif ++ ++#if 0 ++#define CONFIG_USB_OHCI 1 ++#endif ++ ++#if 1 ++#define CONFIG_USB_DEVICE 1 ++#define CONFIG_USB_TTY 1 ++#define CFG_CONSOLE_IS_IN_ENV 1 ++#define CONFIG_USBD_VENDORID 0x1457 /* Linux/NetChip */ ++#define CONFIG_USBD_PRODUCTID_GSERIAL 0x5120 /* gserial */ ++#define CONFIG_USBD_PRODUCTID_CDCACM 0x511a /* CDC ACM */ ++#define CONFIG_USBD_MANUFACTURER "OpenMoko, Inc" ++#define CONFIG_USBD_PRODUCT_NAME "HXD8 Bootloader " U_BOOT_VERSION ++#define CONFIG_USBD_DFU 1 ++#define CONFIG_USBD_DFU_XFER_SIZE 4096 /* 0x4000 */ ++#define CONFIG_USBD_DFU_INTERFACE 2 ++#endif ++#define CFG_CONSOLE_IS_IN_ENV 1 ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "usbtty=cdc_acm\0" \ ++ "bootargs_base=rootfstype=jffs2 root=/dev/mtdblock4 console=ttySAC2,115200 console=tty0 loglevel=8\0" \ ++ "" ++ ++/*----------------------------------------------------------------------- ++ * Physical Memory Map ++ */ ++#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ ++#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ ++#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ ++#define PHYS_SDRAM_RES_SIZE 0x00200000 /* 2 MB for frame buffer */ ++ ++/*----------------------------------------------------------------------- ++ * FLASH and environment organization ++ */ ++ ++/* No NOR flash in this device */ ++#define CFG_NO_FLASH 1 ++ ++#define CFG_ENV_SIZE 0x20000 /* 128k Total Size of Environment Sector */ ++#define CFG_ENV_IS_IN_NAND 1 ++#define CFG_ENV_OFFSET_OOB 1 /* Location of ENV stored in block 0 OOB */ ++#define CFG_PREBOOT_OVERRIDE 1 /* allow preboot from memory */ ++ ++#define NAND_MAX_CHIPS 3 ++#define CFG_NAND_BASE 0x4e000000 ++#define CFG_MAX_NAND_DEVICE NAND_MAX_CHIPS ++#define CFG_NAND_BASE_LIST { CFG_NAND_BASE, CFG_NAND_BASE, CFG_NAND_BASE } ++ ++#define CONFIG_MMC 1 ++#define CFG_MMC_BASE 0xff000000 ++ ++/* EXT2 driver */ ++#define CONFIG_EXT2 1 ++ ++#define CONFIG_FAT 1 ++#define CONFIG_SUPPORT_VFAT ++ ++#if 1 ++/* JFFS2 driver */ ++#define CONFIG_JFFS2_CMDLINE 1 ++#define CONFIG_JFFS2_NAND 1 ++#define CONFIG_JFFS2_NAND_DEV 0 ++//#define CONFIG_JFFS2_NAND_OFF 0x634000 ++//#define CONFIG_JFFS2_NAND_SIZE 0x39cc000 ++#endif ++ ++/* ATAG configuration */ ++#define CONFIG_INITRD_TAG 1 ++#define CONFIG_SETUP_MEMORY_TAGS 1 ++#define CONFIG_CMDLINE_TAG 1 ++#define CONFIG_REVISION_TAG 1 ++#if 0 ++#define CONFIG_SERIAL_TAG 1 ++#endif ++ ++#define CONFIG_DRIVER_S3C24X0_I2C 1 ++#define CONFIG_HARD_I2C 1 ++#define CFG_I2C_SPEED 400000 /* 400kHz according to PCF50606 data sheet */ ++#define CFG_I2C_SLAVE 0x7f ++ ++/* we have a board_late_init() function */ ++#define BOARD_LATE_INIT 1 ++ ++#if 1 ++#define CONFIG_VIDEO ++#define CONFIG_VIDEO_S3C2410 ++#define CONFIG_CFB_CONSOLE ++#define CONFIG_VIDEO_LOGO ++#define CONFIG_SPLASH_SCREEN ++#define CFG_VIDEO_LOGO_MAX_SIZE (640*480+1024+100) /* 100 = slack */ ++#define CONFIG_VIDEO_BMP_GZIP ++#define CONFIG_VGA_AS_SINGLE_DEVICE ++#define CONFIG_UNZIP ++ ++#define VIDEO_KBD_INIT_FCT 0 ++#define VIDEO_TSTC_FCT serial_tstc ++#define VIDEO_GETC_FCT serial_getc ++ ++#define LCD_VIDEO_ADDR 0x33d00000 ++#endif ++ ++#define CONFIG_S3C2410_NAND_BBT 1 ++//#define CONFIG_S3C2410_NAND_HWECC 1 ++ ++#define CONFIG_DRIVER_PCF50606 1 ++ ++#define MTDIDS_DEFAULT "nand0=hxd8-nand" ++#define MTPARTS_DEFAULT "hxd8-nand:256k(u-boot),128k(u-boot_env),2M(kernel),640k(splash),0x3fd00000(jffs2)" ++#define CFG_NAND_DYNPART_MTD_KERNEL_NAME "hxd8-nand" ++#define CONFIG_NAND_DYNPART ++ ++#endif /* __CONFIG_H */ +Index: u-boot/board/hxd8/udc.c +=================================================================== +--- /dev/null ++++ u-boot/board/hxd8/udc.c +@@ -0,0 +1,30 @@ ++ ++#include ++#include ++#include ++ ++#if defined(CONFIG_USB_DEVICE) ++ ++void udc_ctrl(enum usbd_event event, int param) ++{ ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ ++ switch (event) { ++ case UDC_CTRL_PULLUP_ENABLE: ++ if (param) ++ gpio->GPBDAT |= (1 << 9); /* GPB9 */ ++ else ++ gpio->GPBDAT &= ~(1 << 9); /* GPB9 */ ++ break; ++ case UDC_CTRL_500mA_ENABLE: ++ if (param) ++ gpio->GPADAT |= (1 << 0); /* GPA0 */ ++ else ++ gpio->GPADAT &= ~(1 << 0); /* GPA0 */ ++ break; ++ default: ++ break; ++ } ++} ++ ++#endif /* CONFIG_USB_DEVICE */ +Index: u-boot/board/hxd8/pcf50606.c +=================================================================== +--- /dev/null ++++ u-boot/board/hxd8/pcf50606.c +@@ -0,0 +1,67 @@ ++ ++#include ++#include ++ ++/* initial register set for PCF50606 in HXD8 devices */ ++const u_int8_t pcf50606_initial_regs[__NUM_PCF50606_REGS] = { ++ [PCF50606_REG_OOCS] = 0x00, ++ /* gap */ ++ [PCF50606_REG_INT1M] = PCF50606_INT1_SECOND, ++ [PCF50606_REG_INT2M] = PCF50606_INT2_CHGFOK | ++ PCF50606_INT2_CHGERR | ++ PCF50606_INT2_CHGFRDY | ++ PCF50606_INT2_CHGPROT | ++ PCF50606_INT2_CHGWD10S | ++ PCF50606_INT2_CHGWDEXP, ++ [PCF50606_REG_INT3M] = PCF50606_INT3_TSCPRES, ++ [PCF50606_REG_OOCC1] = PCF50606_OOCC1_RTCWAK | ++ PCF50606_OOCC1_CHGWAK & ++ PCF50606_OOCC1_EXTONWAK_NO_WAKEUP, ++ [PCF50606_REG_OOCC2] = PCF50606_OOCC2_ONKEYDB_14ms | ++ PCF50606_OOCC2_EXTONDB_14ms, ++ /* gap */ ++ [PCF50606_REG_PSSC] = 0x00, ++ [PCF50606_REG_PWROKM] = 0x00, ++ /* gap */ ++ [PCF50606_REG_DCDC1] = 0xf0, /* CORE_1V3: on */ ++ [PCF50606_REG_DCDC2] = 0x00, ++ [PCF50606_REG_DCDC3] = 0x00, ++ [PCF50606_REG_DCDC4] = 0x30, /* 1.25A */ ++ ++ [PCF50606_REG_DCDEC1] = 0xe8, /* IO1_3V3: off */ ++ [PCF50606_REG_DCDEC2] = 0x00, ++ ++ [PCF50606_REG_DCUDC1] = 0x08, /* RF_3V3: off */ ++ [PCF50606_REG_DCUDC2] = 0x30, /* 1.25A current limit */ ++ ++ [PCF50606_REG_IOREGC] = 0xf8, /* AUDIO_3V3: on */ ++ ++ [PCF50606_REG_D1REGC1] = 0xf8, /* RC_3V3: on */ ++ ++ [PCF50606_REG_D2REGC1] = 0x18, /* GPS_3V3: off */ ++ ++ [PCF50606_REG_D3REGC1] = 0xf8, /* IO2_3V3: off */ ++ ++ [PCF50606_REG_LPREGC1] = 0xf8, /* LCM_3V3: on */ ++ [PCF50606_REG_LPREGC2] = 0x00, ++ ++ [PCF50606_REG_MBCC1] = 0x00, /* charger unused */ ++ [PCF50606_REG_MBCC2] = 0x00, /* unlimited charging */ ++ [PCF50606_REG_MBCC3] = 0x1a, /* 0.2*Ifast, 4.20V */ ++ [PCF50606_REG_BBCC] = 0x1f, /* 400uA */ ++ [PCF50606_REG_ADCC1] = 0x00, ++ [PCF50606_REG_ADCC2] = 0x00, ++ /* gap */ ++ [PCF50606_REG_ACDC1] = 0x00, ++ [PCF50606_REG_BVMC] = PCF50606_BVMC_THRSHLD_3V3, ++ [PCF50606_REG_PWMC1] = 0x1f, /* clock: 512 DC: 15/16*/ ++ [PCF50606_REG_LEDC1] = 0x00, ++ [PCF50606_REG_LEDC2] = 0x00, ++ [PCF50606_REG_GPOC1] = 0x03, /* PWM ACTIVE */ ++ [PCF50606_REG_GPOC2] = 0x07, /* back light pull low */ ++ [PCF50606_REG_GPOC3] = 0x00, ++ [PCF50606_REG_GPOC4] = 0x00, ++ [PCF50606_REG_GPOC5] = 0x00, ++}; ++ ++ +Index: u-boot/board/hxd8/config.mk +=================================================================== +--- /dev/null ++++ u-boot/board/hxd8/config.mk +@@ -0,0 +1,27 @@ ++# ++# (C) Copyright 2002 ++# Gary Jennejohn, DENX Software Engineering, ++# David Mueller, ELSOFT AG, ++# ++# FIC HXD8 board with S3C2440X (ARM920T) cpu ++# ++# see http://www.samsung.com/ for more information on SAMSUNG ++# ++ ++CONFIG_USB_DFU_VENDOR=0x1457 ++CONFIG_USB_DFU_PRODUCT=0x511a ++CONFIG_USB_DFU_REVISION=0x0100 ++ ++# ++# HXD81v011 or later has 1 bank of 128 MB SDRAM ++# ++# 3000'0000 to 3800'0000 ++# we load ourself to 37F8'0000 ++# ++# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 ++# optionally with a ramdisk at 3080'0000 ++# ++# download area is 3200'0000 or 3300'0000 ++ ++# FIXME: TEXT_BASE = 0x37F80000 ++TEXT_BASE = 0x33F80000 +Index: u-boot/board/hxd8/u-boot.lds +=================================================================== +--- /dev/null ++++ u-boot/board/hxd8/u-boot.lds +@@ -0,0 +1,58 @@ ++/* ++ * (C) Copyright 2002 ++ * Gary Jennejohn, DENX Software Engineering, ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ ++OUTPUT_ARCH(arm) ++ENTRY(_start) ++SECTIONS ++{ ++ . = 0x00000000; ++ ++ . = ALIGN(4); ++ .text : ++ { ++ cpu/arm920t/start.o (.text) ++ cpu/arm920t/s3c24x0/nand_read.o (.text) ++ *(.text) ++ } ++ ++ . = ALIGN(4); ++ .rodata : { *(.rodata) } ++ ++ . = ALIGN(4); ++ .data : { *(.data) } ++ ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ . = .; ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss : { *(.bss) } ++ _end = .; ++} +Index: u-boot/board/hxd8/lowlevel_foo.S +=================================================================== +--- /dev/null ++++ u-boot/board/hxd8/lowlevel_foo.S +@@ -0,0 +1,87 @@ ++ ++_start: ++ b reset ++undefvec: ++ b undefvec ++swivec: ++ b swivec ++pabtvec: ++ b pabtvec ++dabtvec: ++ b dabtvec ++rsvdvec: ++ b rsvdvec ++irqvec: ++ b irqvec ++fiqvec: ++ b fiqvec ++ ++reset: ++ /* ++ * set the cpu to SVC32 mode ++ */ ++ mrs r0,cpsr ++ bic r0,r0,#0x1f ++ orr r0,r0,#0xd3 ++ msr cpsr,r0 ++ ++/* turn off the watchdog */ ++#define pWTCON 0x53000000 ++#define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ ++#define INTSUBMSK 0x4A00001C ++#define CLKDIVN 0x4C000014 /* clock divisor register */ ++#define CAMDIVN 0x4C000018 ++ ++ ldr r0, =pWTCON ++ mov r1, #0x0 ++ str r1, [r0] ++ ++ mov r1, #0xffffffff ++ ldr r0, =INTMSK ++ str r1, [r0] ++ ldr r1, =0x7ff ++ ldr r0, =INTSUBMSK ++ str r1, [r0] ++ ++ /* FCLK:HCLK:PCLK = 1:3:6 */ ++ ldr r0, =CAMDIVN ++ mov r1, #0 ++ str r1, [r0] ++ ++ /* FCLK:HCLK:PCLK = 1:3:6 */ ++ ldr r0, =CLKDIVN ++ mov r1, #7 ++ str r1, [r0] ++ ++ bl cpu_init_crit ++ ldr r0,=TEXT_BASE ++ mov pc, r0 ++ ++cpu_init_crit: ++ /* ++ * flush v4 I/D caches ++ */ ++ mov r0, #0 ++ mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ ++ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ ++ ++ /* ++ * disable MMU stuff and caches ++ */ ++ mrc p15, 0, r0, c1, c0, 0 ++ bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) ++ bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) ++ orr r0, r0, #0x00000002 @ set bit 2 (A) Align ++ orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache ++ mcr p15, 0, r0, c1, c0, 0 ++ ++ /* ++ * before relocating, we have to setup RAM timing ++ * because memory timing is board-dependend, you will ++ * find a lowlevel_init.S in your board directory. ++ */ ++ mov ip, lr ++ bl lowlevel_init ++ mov lr, ip ++ mov pc, lr ++ +Index: u-boot/board/hxd8/lowlevel_foo.lds +=================================================================== +--- /dev/null ++++ u-boot/board/hxd8/lowlevel_foo.lds +@@ -0,0 +1,56 @@ ++/* ++ * (C) Copyright 2002 ++ * Gary Jennejohn, DENX Software Engineering, ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++OUTPUT_ARCH(arm) ++ENTRY(_start) ++SECTIONS ++{ ++ . = 0x00000000; ++ ++ . = ALIGN(4); ++ .text : ++ { ++ lowlevel_foo.o (.text) ++ *(.text) ++ } ++ ++ . = ALIGN(4); ++ .rodata : { *(.rodata) } ++ ++ . = ALIGN(4); ++ .data : { *(.data) } ++ ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ . = .; ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss : { *(.bss) } ++ _end = .; ++} +Index: u-boot/cpu/arm920t/s3c24x0/nand.c +=================================================================== +--- u-boot.orig/cpu/arm920t/s3c24x0/nand.c ++++ u-boot/cpu/arm920t/s3c24x0/nand.c +@@ -83,6 +83,59 @@ + #define NFDATA __REGb(NF_BASE + oNFDATA) + #define NFSTAT __REGb(NF_BASE + oNFSTAT) + ++#if defined(CONFIG_HXD8) ++static int hxd8_nand_dev_ready(struct mtd_info *mtd) ++{ ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ u_int32_t val = gpio->GPCDAT; ++ ++ switch (nand_curr_device) { ++ case 0: ++ return (NFSTAT & 0x01); ++ case 1: /* RnB 3 */ ++ return ((val>>6) & 0x01); ++ case 2: /* RnB 4 */ ++ return ((val>>7) & 0x01); ++ case 3: /* RnB 2 */ ++ return ((val>>5) & 0x01); ++ default: ++ return 0; ++ } ++} ++ ++/* 4G Nand flash chip select function */ ++static void hxd8_nand_select_chip(struct nand_chip *this, int chip) ++{ ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ ++ if (chip == 0) ++ gpio->GPGDAT &= ~(1 << 1); ++ else ++ gpio->GPGDAT |= (1 << 1); ++ ++ if (chip == 1) ++ gpio->GPADAT &= ~(1 << 15); ++ else ++ gpio->GPADAT |= (1 << 15); ++ ++ if (chip == 2) ++ gpio->GPADAT &= ~(1 << 16); ++ else ++ gpio->GPADAT |= (1 << 16); ++ ++ if (chip == 3) ++ gpio->GPADAT &= ~(1 << 14); ++ else ++ gpio->GPADAT |= (1 << 14); ++ ++ /* UGLY: ew don't have mtd_info pointer, but know that ++ * s3c24xx hwcontrol function does not use it for CLRNCE */ ++ if (chip == -1) ++ this->hwcontrol(NULL, NAND_CTL_CLRNCE); ++ else ++ this->hwcontrol(NULL, NAND_CTL_SETNCE); ++} ++#endif + + static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd) + { +@@ -251,6 +304,11 @@ + nand->eccmode = NAND_ECC_SOFT; + #endif + ++#if defined(CONFIG_HXD8) ++ nand->dev_ready = hxd8_nand_dev_ready; ++ nand->select_chip = hxd8_nand_select_chip; ++#endif ++ + #ifdef CONFIG_S3C2410_NAND_BBT + nand->options = NAND_USE_FLASH_BBT | NAND_DONT_CREATE_BBT; + #else diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-license.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-license.patch new file mode 100644 index 0000000000..227a97e71a --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-license.patch @@ -0,0 +1,712 @@ +Index: u-boot/common/Makefile +=================================================================== +--- u-boot.orig/common/Makefile ++++ u-boot/common/Makefile +@@ -34,7 +34,7 @@ + cmd_dynenv.o cmd_eeprom.o cmd_elf.o cmd_ext2.o \ + cmd_fat.o cmd_fdc.o cmd_fdt.o cmd_fdos.o cmd_flash.o cmd_fpga.o \ + cmd_i2c.o cmd_ide.o cmd_immap.o cmd_itest.o cmd_jffs2.o \ +- cmd_load.o cmd_log.o \ ++ cmd_license.o cmd_load.o cmd_log.o \ + cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \ + cmd_nand.o cmd_net.o cmd_nvedit.o \ + cmd_pci.o cmd_pcmcia.o cmd_portio.o \ +Index: u-boot/common/cmd_license.c +=================================================================== +--- /dev/null ++++ u-boot/common/cmd_license.c +@@ -0,0 +1,57 @@ ++/* ++ * (C) Copyright 2007 by OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++ ++#if (CONFIG_COMMANDS & CFG_CMD_LICENSE) ++ ++#define LICENSE_MAX 20480 ++#include ++#include ++#include ++int gunzip(void *, int, unsigned char *, unsigned long *); ++ ++int do_license(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ++{ ++ char *tok, *dst = malloc(LICENSE_MAX); ++ unsigned long len = LICENSE_MAX; ++ ++ if (!dst) ++ return -1; ++ ++ if (gunzip(dst, LICENSE_MAX, gpl_gz, &len) != 0) { ++ printf("Error uncompressing license text\n"); ++ free(dst); ++ return -1; ++ } ++ puts(dst); ++ free(dst); ++ ++ return 0; ++} ++ ++U_BOOT_CMD(license, 1, 1, do_license, ++ "license - print GPL license text\n", ++ NULL); ++ ++#endif /* CFG_CMD_LICENSE */ +Index: u-boot/include/cmd_confdefs.h +=================================================================== +--- u-boot.orig/include/cmd_confdefs.h ++++ u-boot/include/cmd_confdefs.h +@@ -75,6 +75,7 @@ + #define CFG_CMD_FPGA 0x0000010000000000ULL /* FPGA configuration Support */ + #define CFG_CMD_HWFLOW 0x0000020000000000ULL /* RTS/CTS hw flow control */ + #define CFG_CMD_SAVES 0x0000040000000000ULL /* save S record dump */ ++#define CFG_CMD_LICENSE 0x0000080000000000ULL /* Display GPL License */ + #define CFG_CMD_SPI 0x0000100000000000ULL /* SPI utility */ + #define CFG_CMD_FDOS 0x0000200000000000ULL /* Floppy DOS support */ + #define CFG_CMD_VFD 0x0000400000000000ULL /* VFD support (TRAB) */ +Index: u-boot/include/license.h +=================================================================== +--- /dev/null ++++ u-boot/include/license.h +@@ -0,0 +1,584 @@ ++/* bin2header converting 'gpl.gz' */ ++unsigned char gpl_gz[] = { ++ 0x1f, 0x8b, 0x08, 0x08, 0xb2, 0x10, 0x0d, 0x46, 0x00, 0x03, ++ 0x67, 0x70, 0x6c, 0x00, 0x9d, 0x5b, 0x5d, 0x77, 0xdb, 0x46, ++ 0x92, 0x7d, 0x4e, 0xff, 0x8a, 0x3e, 0x7e, 0x89, 0x74, 0x0e, ++ 0xc3, 0xc4, 0x9e, 0x9d, 0xdd, 0x49, 0xfc, 0x44, 0x49, 0x94, ++ 0xcd, 0x1d, 0x99, 0x52, 0x48, 0xca, 0x8e, 0x1f, 0x41, 0xb2, ++ 0x29, 0x62, 0x0c, 0x02, 0x5c, 0x7c, 0x48, 0xe6, 0xbf, 0xdf, ++ 0x7b, 0xab, 0xba, 0x81, 0x06, 0x49, 0x25, 0xb3, 0x9b, 0x93, ++ 0xc4, 0x16, 0x09, 0x54, 0xd7, 0x77, 0xdd, 0xaa, 0x2e, 0xfd, ++ 0xf0, 0x83, 0xc5, 0x3f, 0x1f, 0xa6, 0x8f, 0xf6, 0xc3, 0x78, ++ 0x3a, 0x9e, 0x8d, 0xee, 0xec, 0xc3, 0xe3, 0xd5, 0xdd, 0xe4, ++ 0xda, 0xe2, 0xbf, 0xf1, 0x74, 0x3e, 0x36, 0x3f, 0xc8, 0x03, ++ 0xf8, 0xe7, 0xb3, 0x2b, 0xab, 0xb4, 0xc8, 0xed, 0xbb, 0x81, ++ 0xfd, 0xef, 0x26, 0x77, 0xf6, 0xed, 0xaf, 0xbf, 0xbe, 0x35, ++ 0xc6, 0x5e, 0x17, 0xfb, 0x43, 0x99, 0x3e, 0x6d, 0x6b, 0x7b, ++ 0x71, 0x7d, 0x89, 0x0f, 0xff, 0xf1, 0xeb, 0x40, 0xbe, 0xb2, ++ 0xb7, 0xa5, 0x73, 0x76, 0x5e, 0x6c, 0xea, 0x97, 0xa4, 0x74, ++ 0xf6, 0xb6, 0x68, 0xf2, 0x75, 0x52, 0x83, 0xc0, 0xc0, 0x4e, ++ 0xf2, 0xd5, 0x70, 0x60, 0xec, 0xdf, 0xf9, 0x4c, 0x92, 0x7f, ++ 0xcb, 0xd2, 0xdc, 0xce, 0x6b, 0x3c, 0x5d, 0x0f, 0xec, 0x6d, ++ 0xba, 0xa9, 0xb7, 0xf6, 0x36, 0x2b, 0x8a, 0x72, 0x60, 0xaf, ++ 0x8a, 0xaa, 0xe6, 0xf3, 0x9f, 0x46, 0xf6, 0x97, 0x77, 0x6f, ++ 0xdf, 0xfe, 0xf2, 0xd3, 0xdb, 0xbf, 0xfd, 0xf2, 0xd6, 0x3e, ++ 0xce, 0x47, 0xc6, 0x8e, 0x9f, 0x5d, 0x79, 0x28, 0xc0, 0x45, ++ 0x5a, 0xd9, 0xbd, 0x2b, 0x77, 0x69, 0x5d, 0xbb, 0xb5, 0xad, ++ 0x0b, 0xbb, 0x02, 0x3b, 0x36, 0xc9, 0xd7, 0x76, 0x9d, 0x56, ++ 0x75, 0x99, 0x2e, 0x9b, 0xda, 0x59, 0x3c, 0xbb, 0xc4, 0xd1, ++ 0x3b, 0x7e, 0x99, 0xba, 0xca, 0xd8, 0x62, 0x63, 0xeb, 0x2d, ++ 0xde, 0xcc, 0xd2, 0x95, 0xcb, 0x2b, 0x67, 0xd7, 0xc5, 0xaa, ++ 0xd9, 0xb9, 0x1c, 0xe7, 0xe3, 0x79, 0xbb, 0xda, 0x26, 0xf9, ++ 0x53, 0x9a, 0x3f, 0xd9, 0xb4, 0x26, 0xf9, 0xbc, 0xa8, 0x6d, ++ 0x92, 0x65, 0xc5, 0x8b, 0x5b, 0x0f, 0x0d, 0xd4, 0x21, 0xfa, ++ 0x78, 0x28, 0x5d, 0xb2, 0x5b, 0x66, 0x0e, 0x0a, 0xb0, 0x8b, ++ 0xad, 0x0b, 0x94, 0x2a, 0xbb, 0x29, 0x4a, 0xbb, 0x03, 0xdf, ++ 0xb6, 0x0a, 0x92, 0xf3, 0xbf, 0xb5, 0xab, 0xd2, 0xa7, 0x5c, ++ 0x39, 0xac, 0x93, 0x6f, 0xf8, 0xf0, 0x25, 0x39, 0xd8, 0x43, ++ 0xd1, 0x94, 0x66, 0x03, 0xc1, 0xd7, 0xc5, 0x8e, 0xdf, 0x54, ++ 0x5b, 0x79, 0x1e, 0xcc, 0x0b, 0x0b, 0x10, 0xae, 0x1e, 0x5a, ++ 0x7b, 0x75, 0x00, 0xdf, 0x79, 0x5d, 0x26, 0x15, 0xf8, 0xab, ++ 0x71, 0x96, 0x18, 0xcb, 0xe5, 0xae, 0x4c, 0x32, 0xfb, 0xd0, ++ 0x2c, 0x71, 0xb4, 0xb9, 0xf3, 0x82, 0x80, 0xdd, 0x34, 0xaf, ++ 0x5d, 0xbe, 0xd6, 0xa3, 0x9e, 0x9a, 0x04, 0x0a, 0xae, 0x61, ++ 0x07, 0x1e, 0x65, 0xff, 0xec, 0x28, 0x7e, 0x67, 0x02, 0xcf, ++ 0x3f, 0xfd, 0x84, 0x47, 0x76, 0xe4, 0xb3, 0x6a, 0xf0, 0x18, ++ 0x0f, 0x6d, 0xc5, 0xc1, 0x11, 0x7c, 0x56, 0x04, 0x85, 0x5a, ++ 0xc0, 0x63, 0x65, 0x9b, 0x0a, 0xbe, 0x31, 0xa4, 0x26, 0xd2, ++ 0xca, 0xf4, 0x59, 0xb3, 0x81, 0xb5, 0x64, 0xbf, 0xcf, 0xa0, ++ 0x7c, 0x1e, 0x2e, 0xfa, 0x11, 0x1b, 0xb8, 0xbe, 0x97, 0x98, ++ 0xce, 0x4b, 0x7e, 0xac, 0x22, 0x0d, 0xe6, 0x22, 0x4d, 0x92, ++ 0x1f, 0x6c, 0x81, 0x77, 0x4a, 0xbb, 0x2f, 0x8b, 0xa7, 0x32, ++ 0xd9, 0xd9, 0x97, 0x6d, 0x41, 0xca, 0x4d, 0xbd, 0x2d, 0xca, ++ 0x0a, 0x5a, 0xda, 0xc1, 0x0f, 0xf0, 0xa4, 0x69, 0x2a, 0x35, ++ 0x1f, 0x58, 0xba, 0x98, 0x17, 0x3b, 0xe7, 0x5f, 0x7b, 0xcd, ++ 0x23, 0x7b, 0xc2, 0xad, 0x0a, 0xb8, 0x0b, 0xd4, 0xb7, 0x3c, ++ 0x98, 0xa0, 0xec, 0x3b, 0x57, 0x41, 0x40, 0xfb, 0x8a, 0x60, ++ 0x69, 0x5e, 0xd5, 0x2e, 0x59, 0x0f, 0x2f, 0xad, 0xfd, 0x5a, ++ 0x34, 0x76, 0x95, 0xe4, 0x22, 0xeb, 0xc1, 0x2a, 0x2f, 0xa2, ++ 0x79, 0xcf, 0x70, 0x05, 0x03, 0x16, 0xc5, 0x90, 0x4e, 0xf3, ++ 0x65, 0xeb, 0x72, 0xfb, 0x02, 0xbd, 0xee, 0x5d, 0xf2, 0x8d, ++ 0xca, 0x10, 0xa5, 0x06, 0x46, 0x06, 0xfc, 0x8a, 0x0c, 0x95, ++ 0x6e, 0xe3, 0xca, 0x92, 0xd2, 0x40, 0x01, 0xde, 0x7e, 0x03, ++ 0xba, 0xa4, 0xd9, 0x97, 0x38, 0x1f, 0x02, 0xde, 0x37, 0xaf, ++ 0x71, 0x56, 0x9d, 0xb8, 0x5e, 0x6c, 0xd2, 0xa4, 0xa6, 0x53, ++ 0x98, 0x6d, 0xf2, 0xac, 0x06, 0x8e, 0x9c, 0x23, 0x0a, 0x1d, ++ 0x8d, 0x98, 0x13, 0xfe, 0xec, 0x85, 0x77, 0x9d, 0xf2, 0x49, ++ 0x3c, 0xc1, 0x48, 0x38, 0x41, 0x49, 0xcf, 0x38, 0xda, 0xa6, ++ 0x1b, 0x92, 0xb6, 0x2f, 0x69, 0xb5, 0xbd, 0x1c, 0xb4, 0x47, ++ 0x41, 0x96, 0x95, 0x4b, 0x9f, 0x49, 0xa4, 0x29, 0x57, 0x24, ++ 0xbd, 0x86, 0x61, 0x4a, 0x51, 0xd8, 0x93, 0x43, 0xa8, 0xd5, ++ 0x26, 0xbc, 0x08, 0x9f, 0xc5, 0x8f, 0xd1, 0xab, 0x7c, 0xc6, ++ 0x3b, 0x6a, 0xcf, 0x19, 0xf1, 0x3a, 0x7c, 0xcf, 0x82, 0xc7, ++ 0x95, 0x72, 0x49, 0x22, 0xb9, 0xcd, 0xdd, 0x8b, 0xf2, 0x1b, ++ 0xf4, 0xfe, 0x5e, 0x7d, 0x28, 0x90, 0xfb, 0x96, 0x17, 0x2f, ++ 0x2d, 0xdd, 0x75, 0x41, 0x9a, 0x15, 0x29, 0x43, 0xcf, 0x95, ++ 0x58, 0x67, 0x51, 0xf0, 0xd5, 0xda, 0xad, 0x6a, 0x8d, 0x1c, ++ 0x49, 0x70, 0x95, 0x58, 0x25, 0x77, 0x91, 0x2e, 0x4b, 0x47, ++ 0x4d, 0xad, 0xe8, 0x44, 0x95, 0x92, 0x87, 0x32, 0x96, 0xe9, ++ 0xda, 0xc0, 0x57, 0x99, 0x9d, 0xa8, 0x4c, 0x97, 0x4b, 0xa4, ++ 0xfb, 0x43, 0x94, 0x12, 0x19, 0xa7, 0x47, 0x57, 0xdf, 0xf4, ++ 0xab, 0x82, 0x56, 0x29, 0x19, 0xb7, 0xa5, 0x08, 0xa8, 0x4f, ++ 0x0d, 0xcd, 0x42, 0xdf, 0xe9, 0x9d, 0x82, 0x88, 0xae, 0xb2, ++ 0xa4, 0x16, 0xe2, 0x2b, 0x57, 0xd6, 0x09, 0x04, 0xc6, 0x13, ++ 0x7b, 0x7c, 0x99, 0x2e, 0xd3, 0x2c, 0xad, 0x53, 0x9f, 0x86, ++ 0x48, 0x59, 0x35, 0x6a, 0xce, 0x5a, 0x34, 0xd6, 0xe4, 0x80, ++ 0x1c, 0x79, 0xf5, 0xef, 0x8a, 0x75, 0xba, 0xa1, 0xfb, 0x8a, ++ 0x2a, 0x6e, 0xf1, 0x85, 0xfb, 0x9e, 0xec, 0xf6, 0x19, 0x1e, ++ 0xf2, 0x4f, 0x9c, 0x25, 0x57, 0x35, 0xab, 0xad, 0x4d, 0x82, ++ 0xca, 0xa1, 0xab, 0xad, 0x63, 0xd4, 0x19, 0xfc, 0x54, 0xa7, ++ 0x22, 0xb1, 0xa4, 0x0c, 0xbb, 0x71, 0x20, 0x24, 0xe7, 0x34, ++ 0x48, 0x03, 0x4f, 0xa9, 0xf7, 0x3f, 0x78, 0x47, 0x0a, 0x52, ++ 0x39, 0x94, 0xc3, 0xb4, 0xd2, 0x69, 0x41, 0xf4, 0xca, 0x30, ++ 0xb2, 0xf4, 0xd5, 0xa1, 0x46, 0x99, 0xbc, 0x7b, 0xe4, 0xce, ++ 0x78, 0xe5, 0x20, 0x01, 0x36, 0x68, 0x5d, 0x2d, 0x72, 0x2f, ++ 0x7c, 0x6b, 0x22, 0xcf, 0x03, 0x9d, 0x11, 0x5c, 0xa2, 0xe5, ++ 0xa3, 0xda, 0xc2, 0x25, 0xf0, 0xcc, 0x2e, 0x38, 0x03, 0x8a, ++ 0x0a, 0x53, 0x90, 0x50, 0x55, 0x87, 0xc1, 0xdf, 0xd2, 0xd2, ++ 0x04, 0xd3, 0x30, 0x86, 0xdd, 0x39, 0x2f, 0x81, 0xdf, 0xa3, ++ 0x84, 0xd5, 0x2f, 0xb0, 0x69, 0xed, 0xf6, 0xd5, 0x6f, 0xf6, ++ 0xe2, 0xed, 0xa5, 0x94, 0x25, 0xad, 0x92, 0x7d, 0xad, 0xc3, ++ 0x2d, 0xcd, 0xc5, 0xbb, 0x4b, 0xe8, 0x0f, 0x71, 0xee, 0xdd, ++ 0x24, 0x2a, 0x4c, 0x2f, 0xdb, 0x14, 0x4a, 0xa5, 0x8e, 0x2a, ++ 0xf9, 0x32, 0x73, 0x4f, 0x08, 0x73, 0x29, 0x78, 0x95, 0x14, ++ 0x63, 0x5f, 0xf1, 0x06, 0xb1, 0x85, 0x41, 0xf3, 0x67, 0xa9, ++ 0x42, 0x62, 0xc6, 0xf8, 0x3c, 0xe1, 0x7a, 0x94, 0x55, 0xd0, ++ 0x10, 0x6d, 0xe1, 0x12, 0x5a, 0x4c, 0xb2, 0x27, 0xd2, 0xad, ++ 0x17, 0x85, 0x54, 0x19, 0x2c, 0x10, 0x48, 0x1d, 0x5e, 0xa2, ++ 0x31, 0x38, 0xbc, 0x77, 0x38, 0x23, 0x0a, 0x77, 0xa1, 0x08, ++ 0x37, 0x74, 0xdc, 0xaa, 0xc6, 0x6b, 0x55, 0x6b, 0x0a, 0xcd, ++ 0xa6, 0x79, 0x81, 0xf7, 0x4b, 0x16, 0xa1, 0x83, 0x1c, 0x29, ++ 0xd2, 0xf5, 0x6a, 0x0d, 0x0c, 0x31, 0xd9, 0x9c, 0x94, 0x18, ++ 0x61, 0x3e, 0x95, 0x34, 0x8c, 0xcf, 0x77, 0x8e, 0xa7, 0xb8, ++ 0xac, 0xd2, 0x5a, 0xb0, 0x4f, 0x90, 0x8f, 0xc1, 0x61, 0x4e, ++ 0xfe, 0x8c, 0xcf, 0x16, 0x55, 0xec, 0x41, 0x60, 0xd7, 0x9b, ++ 0x0c, 0xcc, 0xbc, 0x04, 0xe7, 0x10, 0x07, 0x0a, 0x25, 0x9d, ++ 0x27, 0x16, 0x30, 0x49, 0x9a, 0x27, 0xd9, 0x00, 0x67, 0xa8, ++ 0x48, 0xac, 0x31, 0x50, 0x04, 0x2a, 0xfb, 0x4e, 0x4a, 0x69, ++ 0x59, 0xac, 0x9b, 0x95, 0xb2, 0x21, 0x35, 0x84, 0xd6, 0x85, ++ 0x77, 0x92, 0x00, 0x52, 0x73, 0x46, 0xd3, 0xd3, 0x0a, 0x11, ++ 0x2d, 0xe3, 0xcb, 0xd1, 0x8f, 0x78, 0x60, 0xdf, 0xd4, 0x52, ++ 0x60, 0xd4, 0x5d, 0x6e, 0xf9, 0x75, 0x76, 0x18, 0xc8, 0x21, ++ 0x71, 0x7a, 0x22, 0x4b, 0xf5, 0x16, 0x88, 0x02, 0x95, 0x1b, ++ 0x67, 0xa1, 0xda, 0x53, 0x97, 0x35, 0x4a, 0x88, 0x48, 0xef, ++ 0x6b, 0xe3, 0x9e, 0x5f, 0xd7, 0x2c, 0xb3, 0xf0, 0x3b, 0xe6, ++ 0x56, 0xc9, 0x20, 0xcf, 0x45, 0xba, 0x96, 0xf3, 0xd7, 0xcc, ++ 0x8e, 0xa5, 0x4a, 0x8c, 0xfa, 0x15, 0xdc, 0x81, 0x85, 0x11, ++ 0xc1, 0x99, 0xa8, 0xd2, 0xdb, 0xc2, 0x49, 0x21, 0xd2, 0x7c, ++ 0x9d, 0x3e, 0xa7, 0xeb, 0x86, 0x4c, 0xd9, 0x62, 0x29, 0x89, ++ 0x44, 0x0f, 0x69, 0xe1, 0x0c, 0x22, 0x3e, 0xb7, 0x0e, 0xbe, ++ 0xb9, 0x92, 0x68, 0x93, 0x3a, 0xb4, 0xed, 0xc8, 0xe0, 0x4f, ++ 0x94, 0x21, 0x57, 0x27, 0xe5, 0x61, 0xe8, 0x93, 0x26, 0x7c, ++ 0x82, 0xee, 0x02, 0x33, 0x8b, 0xf3, 0x88, 0xc6, 0x77, 0xc9, ++ 0x9a, 0x58, 0xc6, 0xae, 0x32, 0x97, 0x78, 0x0e, 0xa1, 0x02, ++ 0x2f, 0x90, 0x86, 0xdf, 0xb2, 0x85, 0x50, 0x6b, 0x75, 0x4d, ++ 0xef, 0x5a, 0x3f, 0x7a, 0xb4, 0xc1, 0x2c, 0x8f, 0x8f, 0xa9, ++ 0xf7, 0xf6, 0xb9, 0x44, 0x70, 0xd9, 0x30, 0x40, 0xb0, 0x3d, ++ 0xed, 0xdf, 0x46, 0xae, 0xd4, 0xa7, 0x02, 0x12, 0x6a, 0xd6, ++ 0x24, 0x4d, 0x06, 0x0a, 0x24, 0x18, 0x74, 0xe9, 0xcb, 0xfb, ++ 0xba, 0x51, 0x6f, 0x5b, 0x29, 0x18, 0xd8, 0x14, 0x04, 0x7b, ++ 0x02, 0xf5, 0xfe, 0x02, 0x1a, 0xe3, 0xdb, 0xc5, 0x78, 0xf6, ++ 0x69, 0x6e, 0x47, 0xd3, 0x1b, 0x7b, 0x7d, 0x3f, 0xbd, 0x99, ++ 0x2c, 0x26, 0xf7, 0xd3, 0xb9, 0xbd, 0xbd, 0x9f, 0xe1, 0xc7, ++ 0x87, 0xaf, 0x93, 0xe9, 0x87, 0x81, 0xbd, 0x99, 0xcc, 0x17, ++ 0xb3, 0xc9, 0xd5, 0x23, 0xbf, 0x92, 0x07, 0x3f, 0xdd, 0xdf, ++ 0x4c, 0x6e, 0x27, 0xd7, 0x23, 0x7e, 0x40, 0xde, 0x7f, 0x19, ++ 0x0a, 0x6e, 0x3a, 0x07, 0x94, 0xbc, 0x37, 0x8a, 0xae, 0x21, ++ 0x80, 0xa2, 0x98, 0x97, 0xa2, 0xfc, 0xe6, 0x13, 0x03, 0x71, ++ 0x21, 0xac, 0x56, 0x99, 0x84, 0x9a, 0x61, 0xe9, 0xdd, 0x67, ++ 0x89, 0x77, 0x57, 0xfa, 0x44, 0x97, 0x75, 0xb6, 0x45, 0xc6, ++ 0xda, 0x52, 0x25, 0x07, 0x0f, 0x6c, 0x77, 0xc0, 0x9f, 0x50, ++ 0x7a, 0x97, 0x36, 0xd6, 0xa6, 0x69, 0xcb, 0x8f, 0xaa, 0x30, ++ 0xa0, 0xe4, 0xf3, 0xe8, 0x62, 0xa8, 0x5a, 0x7f, 0xf3, 0xa0, ++ 0xfc, 0xbd, 0x01, 0x76, 0x76, 0xd0, 0xdb, 0xc0, 0x08, 0x64, ++ 0x69, 0xd9, 0x97, 0xaa, 0x10, 0xc9, 0x40, 0xee, 0x25, 0xed, ++ 0xc1, 0x25, 0xdf, 0x88, 0x28, 0xcb, 0x44, 0x83, 0x59, 0x4e, ++ 0x0e, 0xd4, 0xcc, 0xce, 0xa1, 0xcc, 0x59, 0x97, 0x8a, 0xc8, ++ 0xd1, 0x37, 0xa4, 0x41, 0xba, 0x60, 0x35, 0x7d, 0x86, 0xc1, ++ 0xe0, 0x5e, 0x42, 0x45, 0x99, 0xef, 0x04, 0xce, 0x92, 0x97, ++ 0xdf, 0x34, 0xa4, 0x53, 0xe1, 0x05, 0x92, 0xe3, 0x58, 0x7d, ++ 0xd6, 0xab, 0xcd, 0x7b, 0x73, 0x8f, 0xb2, 0xdd, 0x17, 0xa5, ++ 0x78, 0x81, 0x60, 0x89, 0x81, 0xf1, 0x0c, 0xb4, 0x1d, 0x04, ++ 0x25, 0x60, 0x7a, 0x8f, 0x3d, 0xa6, 0x0a, 0x19, 0xb7, 0x2d, ++ 0xcd, 0x6b, 0xa6, 0x0e, 0xca, 0x2f, 0x16, 0x33, 0x19, 0x42, ++ 0xb3, 0x49, 0x9e, 0xa8, 0xb2, 0x8b, 0x8f, 0x48, 0x8c, 0xc8, ++ 0x03, 0x1b, 0xa8, 0x78, 0xd0, 0xbe, 0xc0, 0x03, 0x05, 0xba, ++ 0xaf, 0xb2, 0x86, 0xd0, 0x9d, 0x47, 0x14, 0x0d, 0x5d, 0x1d, ++ 0x80, 0xd6, 0x7f, 0x9d, 0x9b, 0x60, 0x19, 0xfb, 0x26, 0x3e, ++ 0xfd, 0x0d, 0x81, 0xe7, 0x98, 0x99, 0xdc, 0x07, 0x86, 0x64, ++ 0xb8, 0x64, 0xbd, 0x2e, 0x9d, 0x64, 0xc9, 0xa4, 0xb2, 0x6f, ++ 0x50, 0x3a, 0xde, 0xc0, 0xa1, 0x47, 0xc8, 0xee, 0xcf, 0x8a, ++ 0x0f, 0x0a, 0xaf, 0x57, 0xe2, 0xaa, 0xd7, 0xc2, 0xa2, 0x27, ++ 0xa4, 0x60, 0x49, 0xe2, 0xce, 0x0e, 0x1f, 0xab, 0x77, 0x78, ++ 0x77, 0x78, 0xaf, 0x19, 0x56, 0x40, 0x59, 0x53, 0x57, 0xa9, ++ 0x44, 0x3c, 0x0a, 0x28, 0xa8, 0x07, 0x57, 0x49, 0x98, 0x2c, ++ 0x37, 0xa6, 0x6c, 0xf2, 0x13, 0xd5, 0xfb, 0x9c, 0x1c, 0x80, ++ 0x8e, 0x5b, 0x0f, 0x3c, 0x60, 0x13, 0x6a, 0x48, 0xa3, 0xc8, ++ 0x02, 0xc5, 0x2e, 0x7e, 0xc5, 0x44, 0x50, 0xbd, 0xc8, 0x89, ++ 0xb6, 0x37, 0x72, 0x20, 0x6d, 0x2b, 0x25, 0x40, 0xb2, 0x68, ++ 0x5a, 0x4b, 0x41, 0xb4, 0x27, 0x8e, 0x66, 0xc2, 0xc9, 0x17, ++ 0xc8, 0x82, 0x6e, 0x4f, 0xe4, 0x95, 0x4b, 0x4f, 0x82, 0x84, ++ 0x45, 0xe6, 0x96, 0x0e, 0xf0, 0x5c, 0xf2, 0x16, 0xe4, 0x3c, ++ 0xc3, 0xf1, 0xe5, 0xd0, 0x7c, 0x51, 0x7c, 0x63, 0x5b, 0x27, ++ 0x2b, 0x1b, 0xa2, 0x6d, 0xd2, 0xaa, 0x78, 0x4a, 0x28, 0x3b, ++ 0xad, 0x90, 0xeb, 0xc2, 0x69, 0x21, 0x78, 0x3b, 0x54, 0x0c, ++ 0x93, 0x1c, 0xfe, 0x9d, 0x76, 0x35, 0x40, 0x35, 0x4f, 0xe6, ++ 0xc7, 0x2a, 0x86, 0x31, 0x34, 0x6f, 0x8c, 0xad, 0x89, 0x9a, ++ 0xd3, 0x5c, 0x22, 0x64, 0x87, 0x22, 0xd0, 0x00, 0x87, 0x21, ++ 0xf8, 0x90, 0xe5, 0x5d, 0x07, 0x7f, 0x0d, 0x55, 0xb3, 0x4f, ++ 0x57, 0x4d, 0xd1, 0x54, 0x99, 0x9e, 0x8e, 0x9c, 0x23, 0xa9, ++ 0x1c, 0xbe, 0x8b, 0x4f, 0xf6, 0x0c, 0x74, 0xd4, 0x17, 0x08, ++ 0x21, 0x10, 0xc1, 0x33, 0x19, 0x3f, 0x65, 0xba, 0x48, 0xf3, ++ 0x99, 0xc7, 0x0b, 0xb1, 0xca, 0x92, 0x74, 0x07, 0xad, 0x80, ++ 0xe9, 0x50, 0xf8, 0xdf, 0xdb, 0x6f, 0xce, 0xed, 0x19, 0x12, ++ 0xf4, 0x00, 0x0f, 0xee, 0x8c, 0xbe, 0x56, 0x85, 0x82, 0x45, ++ 0xf8, 0xc3, 0xe6, 0xb8, 0x97, 0x09, 0xb5, 0xef, 0xa3, 0xf0, ++ 0xc9, 0xb2, 0x72, 0x39, 0x4e, 0x61, 0x29, 0x83, 0x6c, 0x2d, ++ 0x69, 0xc3, 0x67, 0x04, 0x43, 0x76, 0xdd, 0x61, 0x84, 0x03, ++ 0xfa, 0xaa, 0x83, 0x23, 0x88, 0x28, 0x21, 0xb1, 0xf9, 0x73, ++ 0x4c, 0x92, 0x15, 0xb0, 0xae, 0xc2, 0xb6, 0xee, 0x69, 0x98, ++ 0xaa, 0xb5, 0x92, 0x36, 0x3a, 0x82, 0x5d, 0x3d, 0x8c, 0x41, ++ 0xaa, 0xdd, 0x1e, 0x2a, 0x04, 0x47, 0xe6, 0xfd, 0x5a, 0x83, ++ 0x39, 0x74, 0x6b, 0x7a, 0x92, 0xe2, 0xbb, 0x83, 0xa7, 0x92, ++ 0x78, 0x98, 0x58, 0xec, 0x7d, 0x86, 0xa1, 0xcc, 0x2d, 0x3a, ++ 0x8a, 0xe0, 0x17, 0x6b, 0xee, 0xf7, 0xd0, 0x97, 0x07, 0xcc, ++ 0x2c, 0x9e, 0xf3, 0xae, 0xf3, 0x1c, 0x0f, 0xef, 0x84, 0xa2, ++ 0x4a, 0x55, 0x9e, 0x77, 0x98, 0x90, 0x31, 0x7d, 0x66, 0x33, ++ 0x9a, 0xd9, 0xf0, 0x44, 0x23, 0x65, 0x71, 0xa7, 0xec, 0xbe, ++ 0x9a, 0x8a, 0x07, 0xbe, 0x94, 0xaa, 0x9f, 0xc6, 0x38, 0x53, ++ 0x52, 0x7b, 0x3f, 0x11, 0xfa, 0x04, 0x6f, 0xcf, 0x94, 0x92, ++ 0xb9, 0x17, 0xee, 0xad, 0x49, 0x96, 0x88, 0xdb, 0x33, 0x7e, ++ 0x09, 0xd7, 0x00, 0xde, 0xde, 0x39, 0xa7, 0x4e, 0xa2, 0x52, ++ 0x54, 0x2e, 0x2a, 0xe3, 0xbf, 0x51, 0x07, 0xd6, 0x26, 0x97, ++ 0x5d, 0x0f, 0xb0, 0x4a, 0x9a, 0x4a, 0x1b, 0x88, 0x16, 0x32, ++ 0x6e, 0xd2, 0x4c, 0xcb, 0xe7, 0x0a, 0xba, 0x15, 0xc5, 0x42, ++ 0x46, 0x86, 0xb7, 0x77, 0x39, 0xa1, 0x51, 0x31, 0xaf, 0x4a, ++ 0x4c, 0x87, 0x16, 0x53, 0xf4, 0xad, 0x39, 0x47, 0x29, 0x84, ++ 0x0c, 0xb4, 0x66, 0xb3, 0xe5, 0x1d, 0x4f, 0x9f, 0x1a, 0x2a, ++ 0x1f, 0xcb, 0x13, 0x3e, 0xc4, 0x37, 0xa9, 0x80, 0x96, 0x6c, ++ 0xa4, 0x2f, 0x28, 0xc7, 0x47, 0x96, 0xef, 0x6c, 0x91, 0xd3, ++ 0x49, 0xe6, 0x05, 0xc5, 0x59, 0xbe, 0x15, 0xfc, 0x55, 0xd6, ++ 0x6d, 0x59, 0x97, 0xcf, 0x2a, 0x2d, 0x75, 0x94, 0xeb, 0x28, ++ 0x05, 0x7a, 0xc3, 0x0a, 0x0d, 0x79, 0x4f, 0x50, 0x77, 0xb1, ++ 0x61, 0x0f, 0xd4, 0x03, 0x54, 0xc8, 0x11, 0x89, 0x3f, 0x25, ++ 0xa1, 0x16, 0x82, 0x3f, 0xb3, 0x44, 0x49, 0x34, 0xa6, 0xe5, ++ 0xba, 0xa5, 0x42, 0x07, 0x7a, 0x0d, 0x09, 0x84, 0xd2, 0xaf, ++ 0xe2, 0xaf, 0x2e, 0x03, 0x72, 0x6f, 0x55, 0x1f, 0x0a, 0x7d, ++ 0x0e, 0xbf, 0x12, 0x58, 0x09, 0x50, 0xbb, 0xd6, 0xc9, 0x8c, ++ 0x34, 0x07, 0x1c, 0x4e, 0x95, 0x09, 0xcb, 0x10, 0xf2, 0x8c, ++ 0x17, 0x1e, 0x89, 0x16, 0x09, 0x36, 0x6a, 0x09, 0x55, 0x95, ++ 0xf4, 0x51, 0xf9, 0x12, 0x96, 0x2a, 0x59, 0x52, 0x43, 0x16, ++ 0x66, 0x44, 0xd0, 0xf5, 0xe4, 0xf5, 0x88, 0xa0, 0x60, 0xc4, ++ 0x34, 0xf7, 0x0c, 0x71, 0xc2, 0x54, 0xae, 0x51, 0x69, 0x4b, ++ 0x66, 0x0b, 0xe9, 0x0b, 0xc1, 0x5d, 0xca, 0x24, 0x5f, 0xd2, ++ 0x28, 0x00, 0x4a, 0x74, 0x68, 0xf5, 0xa7, 0x3c, 0x2f, 0x1a, ++ 0x64, 0x17, 0x8e, 0x00, 0x7d, 0x11, 0x96, 0xa0, 0xe8, 0x65, ++ 0x3c, 0x7b, 0x36, 0xe3, 0x25, 0x42, 0xc0, 0x7f, 0xf0, 0x7a, ++ 0xeb, 0x73, 0x41, 0x48, 0x8b, 0xf6, 0x65, 0x10, 0x10, 0x58, ++ 0xeb, 0x1f, 0x3e, 0x0a, 0x94, 0x8f, 0xf6, 0x85, 0xcb, 0x6e, ++ 0x5e, 0x21, 0xb3, 0x35, 0x89, 0xf8, 0x08, 0xd5, 0xab, 0xc7, ++ 0x07, 0x6d, 0x8b, 0xb9, 0x84, 0xc2, 0x71, 0xc0, 0xf8, 0x32, ++ 0xea, 0xb2, 0x2c, 0xd4, 0x2f, 0x92, 0xb3, 0xd2, 0xeb, 0x16, ++ 0xf6, 0x39, 0x75, 0x2f, 0x47, 0x39, 0x51, 0xa8, 0x74, 0x08, ++ 0xef, 0x62, 0xfc, 0x7d, 0xe5, 0x24, 0x5d, 0xfd, 0xc6, 0x02, ++ 0xdb, 0x2b, 0xd9, 0x75, 0xe5, 0xb2, 0x4d, 0x98, 0x38, 0x06, ++ 0x1b, 0x80, 0x37, 0x21, 0xc1, 0x5a, 0x27, 0x25, 0xbd, 0xf5, ++ 0x04, 0x55, 0xbe, 0x0e, 0x09, 0xf2, 0x9e, 0xca, 0x07, 0x9a, ++ 0xc4, 0x7a, 0x19, 0x28, 0x48, 0x73, 0x8a, 0x10, 0xfe, 0xa7, ++ 0x49, 0x4b, 0x9d, 0xc0, 0x28, 0xc5, 0x23, 0x62, 0xc3, 0x4b, ++ 0xd3, 0x4e, 0x4d, 0xe4, 0xd1, 0x9d, 0x8e, 0x14, 0x64, 0x22, ++ 0xe7, 0x8b, 0x49, 0xeb, 0xae, 0x72, 0x64, 0x17, 0x1d, 0xd2, ++ 0x8a, 0x9a, 0x94, 0x50, 0x00, 0xdf, 0x27, 0x68, 0x02, 0x6d, ++ 0xe5, 0xfc, 0xd8, 0x45, 0xf4, 0xc3, 0x66, 0x52, 0x5e, 0x51, ++ 0x2c, 0xf4, 0x6a, 0x64, 0x0e, 0xa4, 0x2c, 0x71, 0xf2, 0xb0, ++ 0x24, 0x1f, 0x49, 0x55, 0xe4, 0xa0, 0x26, 0x73, 0x5c, 0x22, ++ 0xa3, 0x52, 0x00, 0x62, 0x07, 0x3b, 0xf8, 0x70, 0xe5, 0x10, ++ 0x7c, 0x74, 0x33, 0x1e, 0x50, 0x79, 0xb8, 0xb7, 0x83, 0x8a, ++ 0x9f, 0xd9, 0x85, 0xd5, 0x0c, 0x84, 0x38, 0x04, 0xd5, 0xb0, ++ 0x04, 0x3c, 0x12, 0xa1, 0x03, 0x4e, 0xb1, 0x64, 0x50, 0xdd, ++ 0xc9, 0x59, 0xa0, 0xb2, 0xb5, 0xec, 0x4b, 0x24, 0x1d, 0xe5, ++ 0x23, 0x99, 0x76, 0x24, 0xd5, 0xd1, 0xd1, 0x9c, 0x38, 0x37, ++ 0x75, 0xfb, 0x82, 0x39, 0xf2, 0xb9, 0x2a, 0xd9, 0x45, 0x5a, ++ 0xc1, 0xdb, 0x92, 0x79, 0xa4, 0xc3, 0xd4, 0x0c, 0xa3, 0x9d, ++ 0x49, 0x5a, 0xf5, 0x6a, 0x8a, 0x39, 0xae, 0x29, 0x92, 0x57, ++ 0x63, 0xbc, 0xe9, 0x6b, 0x96, 0xd2, 0x08, 0x2d, 0xa1, 0x7f, ++ 0x2b, 0x24, 0x21, 0xd3, 0xd7, 0x80, 0x4e, 0x7f, 0xbb, 0x61, ++ 0x88, 0x76, 0x79, 0x8a, 0x01, 0x02, 0x16, 0x46, 0x0b, 0xf1, ++ 0x9d, 0xf3, 0x70, 0x6f, 0x7a, 0x43, 0xd3, 0x96, 0xfe, 0x98, ++ 0x80, 0x31, 0x1b, 0x29, 0x16, 0x3a, 0x0c, 0xc1, 0x07, 0xd2, ++ 0x7a, 0xaa, 0x58, 0xa5, 0x7b, 0x4a, 0xca, 0x35, 0x6a, 0x81, ++ 0xd8, 0x1f, 0x2f, 0xd9, 0x17, 0x56, 0x69, 0x1d, 0x8d, 0x2d, ++ 0xf0, 0xe2, 0x20, 0xba, 0x23, 0x20, 0xa7, 0x32, 0x7c, 0xaf, ++ 0xdb, 0x7c, 0xe9, 0xf5, 0x24, 0xb5, 0x88, 0xb8, 0x28, 0x9a, ++ 0xfe, 0x09, 0x4e, 0xad, 0x6a, 0x13, 0x0f, 0x8e, 0xf0, 0x98, ++ 0x36, 0x77, 0x25, 0xaf, 0x33, 0x00, 0x02, 0x84, 0x59, 0x1d, ++ 0x03, 0xe0, 0xb9, 0xf7, 0x16, 0x56, 0xda, 0x4a, 0xdf, 0xd0, ++ 0x1d, 0x25, 0xdd, 0x8d, 0x71, 0xdf, 0x5d, 0xa9, 0xcd, 0x6f, ++ 0x18, 0x9b, 0xe9, 0x64, 0x88, 0x03, 0x8c, 0xec, 0xac, 0xb2, ++ 0xa3, 0xfe, 0xa9, 0x28, 0x81, 0xe6, 0x32, 0xce, 0x32, 0x42, ++ 0x37, 0x55, 0x9d, 0x45, 0x02, 0x90, 0x79, 0x92, 0xb3, 0xb3, ++ 0x48, 0xf5, 0x1a, 0x67, 0xc7, 0x44, 0x97, 0x3c, 0x3d, 0x51, ++ 0x4b, 0x81, 0xac, 0x6f, 0x79, 0x54, 0x0e, 0x6a, 0xe5, 0x1c, ++ 0x21, 0x73, 0x0c, 0xb5, 0x24, 0x3f, 0xca, 0x87, 0x7f, 0x02, ++ 0x44, 0x2e, 0xf9, 0x73, 0x62, 0x9f, 0x8b, 0xac, 0xe1, 0x44, ++ 0x7f, 0x83, 0xa6, 0xb7, 0xaa, 0x8b, 0x12, 0x7d, 0x95, 0x4f, ++ 0xe9, 0x9d, 0x7c, 0x0a, 0x7d, 0xbb, 0x24, 0xb4, 0x2c, 0x43, ++ 0xfa, 0x8b, 0xb8, 0xd3, 0xac, 0x29, 0x3e, 0xcd, 0x26, 0xe5, ++ 0x6c, 0x91, 0xfb, 0xdb, 0x9f, 0x23, 0xf5, 0x63, 0x11, 0x8e, ++ 0xb9, 0x67, 0x07, 0xa9, 0xb5, 0x34, 0xa0, 0x9f, 0x77, 0x97, ++ 0x2c, 0x51, 0xc5, 0xf2, 0x5f, 0x9c, 0xa8, 0x84, 0x09, 0x38, ++ 0xac, 0xb7, 0x6a, 0x6a, 0xc9, 0x37, 0x04, 0x64, 0x67, 0xca, ++ 0xaf, 0x99, 0x87, 0x88, 0x7b, 0x2b, 0x3c, 0xbc, 0xb3, 0x02, ++ 0xa2, 0x5e, 0xc3, 0x50, 0x48, 0x06, 0x1c, 0x98, 0xf9, 0x98, ++ 0xd2, 0x81, 0x06, 0x34, 0xd0, 0xc1, 0xa7, 0xd1, 0x0a, 0x25, ++ 0x79, 0x4f, 0xb4, 0x02, 0xff, 0x6d, 0xad, 0xc1, 0xcf, 0x32, ++ 0x27, 0xa5, 0xae, 0xd4, 0x89, 0xb2, 0xd4, 0xc1, 0x1d, 0x22, ++ 0x03, 0x00, 0xea, 0x27, 0xd6, 0x72, 0x32, 0xa9, 0xf8, 0xa9, ++ 0xeb, 0x41, 0x06, 0x3e, 0xe6, 0x43, 0xd4, 0x46, 0x33, 0x85, ++ 0x3f, 0x01, 0x82, 0x5a, 0x6a, 0xfa, 0xe2, 0x88, 0x81, 0xbd, ++ 0xf1, 0x56, 0xa0, 0x56, 0xec, 0x92, 0x32, 0x85, 0xff, 0x37, ++ 0x61, 0x2c, 0xd4, 0x8d, 0x08, 0x59, 0x73, 0x14, 0x8c, 0xbd, ++ 0x87, 0x0a, 0x07, 0x2d, 0x20, 0x3b, 0x95, 0x2c, 0x69, 0xe3, ++ 0x49, 0x10, 0xf7, 0xc0, 0x3e, 0x27, 0x59, 0xaa, 0xe4, 0xa0, ++ 0xb3, 0x0c, 0xd9, 0xb9, 0x96, 0xe9, 0x9b, 0xca, 0x75, 0x70, ++ 0x49, 0x29, 0xd7, 0x34, 0x5d, 0x57, 0x21, 0xf8, 0x48, 0x12, ++ 0xc2, 0x61, 0xe0, 0xf1, 0xb8, 0x07, 0x50, 0x39, 0xef, 0xb2, ++ 0x74, 0xfc, 0x9c, 0xeb, 0x6d, 0x9e, 0xe0, 0x22, 0x7f, 0xbd, ++ 0x15, 0x1a, 0x04, 0x16, 0x3f, 0x57, 0x06, 0xa8, 0xed, 0x15, ++ 0x17, 0xfb, 0xeb, 0x40, 0x8a, 0xb0, 0xea, 0x5e, 0x28, 0x1c, ++ 0x6b, 0x3c, 0x2a, 0xd1, 0xc7, 0xc6, 0xe9, 0xd9, 0x41, 0x70, ++ 0x9f, 0xd6, 0xdf, 0x7f, 0xcf, 0x06, 0xaf, 0xeb, 0x5f, 0x25, ++ 0xf9, 0x7f, 0xd8, 0x60, 0xf5, 0x9a, 0x77, 0xa5, 0x39, 0x55, ++ 0xa0, 0x99, 0x22, 0x6a, 0x59, 0x05, 0x9e, 0xfa, 0xc2, 0x2c, ++ 0x06, 0xd2, 0xd2, 0x7f, 0x74, 0x0b, 0xf5, 0x8a, 0xc8, 0x84, ++ 0x28, 0x32, 0x3c, 0x4b, 0x32, 0xf0, 0x92, 0x6b, 0x3e, 0xf3, ++ 0x28, 0xc6, 0xdf, 0xd9, 0xea, 0x74, 0x60, 0x23, 0xc3, 0xc3, ++ 0x9c, 0x40, 0x94, 0x99, 0x12, 0x5d, 0xdb, 0xc9, 0xb4, 0x23, ++ 0x4c, 0x11, 0x58, 0xf4, 0xf8, 0x7e, 0xcb, 0x5f, 0x0c, 0xb5, ++ 0xfe, 0x3a, 0x78, 0x45, 0xde, 0x16, 0x9f, 0x26, 0xad, 0xd7, ++ 0xb1, 0x2b, 0x87, 0x5e, 0x4a, 0x9d, 0xee, 0xd8, 0x79, 0xb3, ++ 0x0c, 0xd5, 0x61, 0xa9, 0xda, 0xf7, 0xc8, 0xa5, 0x77, 0x3d, ++ 0xb6, 0xe9, 0x92, 0x8a, 0x0e, 0xc4, 0x94, 0x17, 0xb9, 0x14, ++ 0x54, 0x73, 0xec, 0xda, 0xca, 0xc9, 0x87, 0x78, 0x15, 0xe7, ++ 0xe7, 0xb4, 0xfd, 0xc6, 0x0c, 0xfa, 0x94, 0xeb, 0xd0, 0x5b, ++ 0xe9, 0x19, 0x62, 0xa6, 0x75, 0x20, 0xd7, 0x86, 0xbe, 0x9e, ++ 0x6e, 0xe4, 0x74, 0x3d, 0x32, 0xdc, 0xc6, 0x9c, 0xf0, 0x85, ++ 0xcf, 0x71, 0x48, 0xc3, 0x56, 0x29, 0xed, 0x9a, 0x16, 0x34, ++ 0x76, 0x59, 0x53, 0x49, 0x63, 0x92, 0x54, 0x55, 0xb1, 0x4a, ++ 0xc3, 0x3c, 0x0c, 0x21, 0x90, 0xd0, 0xf1, 0xdd, 0x26, 0xcd, ++ 0x53, 0x9d, 0xb4, 0xb2, 0xcd, 0xf2, 0xcf, 0x6b, 0x1e, 0x2e, ++ 0xd3, 0xbd, 0x5e, 0x27, 0xb3, 0x60, 0x9b, 0x50, 0xbf, 0xc8, ++ 0x5c, 0xea, 0xc7, 0x64, 0x02, 0x7b, 0x38, 0x1f, 0xcf, 0xb2, ++ 0x24, 0x06, 0x0e, 0x9d, 0x44, 0x90, 0xf2, 0x23, 0x0c, 0xff, ++ 0x4c, 0xa5, 0x13, 0xdb, 0x99, 0x6a, 0xef, 0xc4, 0xe2, 0x2e, ++ 0x60, 0xd9, 0xc1, 0x89, 0x3c, 0x71, 0xb8, 0xc8, 0x05, 0x1f, ++ 0xab, 0x86, 0x1f, 0xc7, 0xf1, 0x2e, 0x4f, 0xae, 0x06, 0xdb, ++ 0x49, 0x4f, 0x8b, 0x69, 0xe3, 0xd7, 0x2e, 0xd8, 0xb5, 0xeb, ++ 0xb4, 0xd0, 0x53, 0x86, 0x8e, 0x96, 0xd2, 0x80, 0x18, 0xda, ++ 0xe9, 0xb2, 0x8b, 0x84, 0x5d, 0xf2, 0x2f, 0x41, 0x00, 0x3b, ++ 0x78, 0xb4, 0xa0, 0xd3, 0x0b, 0x95, 0x90, 0x1c, 0x7f, 0x83, ++ 0x1b, 0xbb, 0x4c, 0xa1, 0x49, 0xc5, 0x34, 0x7e, 0xe9, 0x25, ++ 0x34, 0xa8, 0x51, 0xa5, 0xf6, 0xac, 0xd5, 0xa1, 0xaa, 0x01, ++ 0xdd, 0x64, 0xc6, 0xc4, 0xc4, 0xdb, 0x97, 0x9f, 0x8d, 0x12, ++ 0xb4, 0xda, 0xe4, 0x82, 0x5b, 0x84, 0xe7, 0xf6, 0x28, 0xe3, ++ 0x51, 0x7b, 0xe2, 0x23, 0x54, 0xe6, 0xcc, 0x7d, 0xed, 0xa1, ++ 0xc8, 0x6f, 0x4e, 0xd0, 0x42, 0x44, 0x9d, 0x10, 0x2b, 0x8a, ++ 0x00, 0xde, 0xd5, 0xf8, 0x31, 0x99, 0x38, 0x3a, 0xf8, 0x33, ++ 0xa0, 0x2e, 0x47, 0xfb, 0x6d, 0x0c, 0x41, 0xc7, 0x89, 0xbf, ++ 0x88, 0x16, 0x6f, 0x90, 0x29, 0xb5, 0x47, 0xb5, 0xe1, 0x2d, ++ 0x4b, 0xb8, 0x8e, 0xd4, 0x4c, 0x2e, 0x8f, 0x08, 0x9c, 0x78, ++ 0x5f, 0x80, 0xdb, 0x02, 0x46, 0x85, 0x18, 0xbe, 0x68, 0x04, ++ 0xe7, 0x57, 0xe6, 0x1c, 0xac, 0xec, 0x65, 0x49, 0x5e, 0x51, ++ 0x10, 0x1f, 0x37, 0x4f, 0xdb, 0x28, 0xb7, 0xa7, 0xfe, 0xbe, ++ 0x5c, 0x67, 0x9c, 0xbb, 0x3d, 0x7a, 0xa6, 0x68, 0xa3, 0x24, ++ 0x22, 0x72, 0x34, 0x2d, 0x8a, 0x94, 0x21, 0x90, 0xe1, 0x3f, ++ 0x3a, 0xc8, 0x40, 0x27, 0xd2, 0x31, 0x90, 0x0e, 0x6b, 0xd0, ++ 0xfd, 0xc9, 0x08, 0x5d, 0xe1, 0x6b, 0x0c, 0x5a, 0x7a, 0x50, ++ 0xc2, 0xa8, 0xa3, 0xd2, 0x79, 0xdd, 0xf7, 0x3d, 0xc7, 0xb8, ++ 0xd2, 0x3e, 0xf9, 0x4a, 0x1f, 0xb2, 0x79, 0x84, 0x54, 0x78, ++ 0x95, 0xc9, 0xf1, 0x12, 0x9c, 0x62, 0x5f, 0x1b, 0x81, 0x38, ++ 0x2f, 0x02, 0x06, 0x8b, 0x57, 0x8f, 0x7f, 0xfd, 0x74, 0xa6, ++ 0x4f, 0x5e, 0x2a, 0xa9, 0x0b, 0xca, 0x45, 0x51, 0xd2, 0xb0, ++ 0x0a, 0xd4, 0xbe, 0x96, 0xb1, 0x88, 0xa4, 0xb4, 0x63, 0xef, ++ 0xd2, 0xf3, 0x0c, 0x5b, 0xa6, 0x0d, 0xc3, 0xa0, 0x5f, 0x22, ++ 0x68, 0xb9, 0x11, 0x6a, 0x73, 0xab, 0x4e, 0xac, 0x44, 0x19, ++ 0xe1, 0x8e, 0x5d, 0xac, 0xcb, 0x02, 0x11, 0x00, 0x5a, 0x34, ++ 0x11, 0x6c, 0x2f, 0xdf, 0xc2, 0xda, 0x42, 0x5a, 0x76, 0xab, ++ 0x37, 0x2d, 0x63, 0x12, 0x39, 0x62, 0x25, 0x76, 0x37, 0x4c, ++ 0xc5, 0x81, 0x01, 0xb4, 0x83, 0xbc, 0xe5, 0xc2, 0xbf, 0x9b, ++ 0x26, 0xd3, 0xc4, 0x92, 0xa5, 0x09, 0x5a, 0x47, 0x31, 0xdd, ++ 0xdf, 0xd5, 0x74, 0xa1, 0xbb, 0x8b, 0x7b, 0x4d, 0x7a, 0xe4, ++ 0xbe, 0x3e, 0x6a, 0xc1, 0xaa, 0x94, 0x23, 0xc9, 0x70, 0x33, ++ 0x2d, 0x9e, 0xe3, 0x77, 0x2d, 0x24, 0xd7, 0xb6, 0xe2, 0x13, ++ 0x13, 0x8b, 0x87, 0xf3, 0x02, 0xf3, 0x89, 0x0d, 0xbe, 0x0e, ++ 0x6d, 0xfb, 0xf7, 0xb8, 0x7e, 0xa0, 0x87, 0x0c, 0xfe, 0x8a, ++ 0x61, 0x38, 0x0d, 0xaa, 0xab, 0xe3, 0x9b, 0x0f, 0xdd, 0xbb, ++ 0x61, 0xc3, 0x9b, 0x84, 0xa6, 0xac, 0x94, 0x1b, 0xba, 0x6d, ++ 0xba, 0x4c, 0x6b, 0x1d, 0xd4, 0x67, 0xc9, 0x4b, 0x7b, 0x75, ++ 0xef, 0xfb, 0xc4, 0x53, 0x79, 0x94, 0x0e, 0x6a, 0x4b, 0xc1, ++ 0x8b, 0xe9, 0xe5, 0x41, 0x6f, 0xc5, 0x64, 0x5a, 0xd1, 0xc3, ++ 0xd7, 0x47, 0xa3, 0xfb, 0x0b, 0x3f, 0x5e, 0x7c, 0x75, 0xc4, ++ 0x7e, 0xa9, 0xa3, 0x1d, 0xde, 0x36, 0xae, 0x5a, 0xaf, 0xd1, ++ 0xf3, 0x13, 0x3f, 0xd2, 0xed, 0xd9, 0xb8, 0x16, 0xfc, 0xca, ++ 0x3b, 0x6a, 0xce, 0x1b, 0xc3, 0x8a, 0xd1, 0xff, 0xe5, 0x56, ++ 0x4f, 0x39, 0x6e, 0xd9, 0x37, 0x47, 0x4a, 0x3c, 0xea, 0x70, ++ 0xfc, 0x9e, 0xc3, 0x7f, 0x0e, 0xf5, 0x16, 0xa5, 0x4e, 0x77, ++ 0xce, 0xe3, 0x93, 0x3f, 0x43, 0xfa, 0x7f, 0x21, 0x71, 0x1d, ++ 0x6f, 0x34, 0x1c, 0x05, 0x90, 0x77, 0x7e, 0x76, 0xc8, 0x21, ++ 0x1a, 0x43, 0x46, 0x33, 0xe1, 0x16, 0xd9, 0x7f, 0xa3, 0x6b, ++ 0x22, 0x1a, 0xc4, 0xfd, 0x49, 0x62, 0x74, 0xbb, 0x1f, 0xf8, ++ 0x42, 0x74, 0x4b, 0x2a, 0xaa, 0x79, 0x97, 0xed, 0x5e, 0xb9, ++ 0x09, 0x0d, 0xfb, 0x13, 0x3e, 0x3d, 0xa5, 0x28, 0x0c, 0x7e, ++ 0x6e, 0xb9, 0x69, 0x4a, 0xb9, 0xad, 0xea, 0x6d, 0x9b, 0xf8, ++ 0x16, 0xac, 0x1b, 0xa9, 0xff, 0x68, 0xdb, 0x5e, 0xd3, 0xe7, ++ 0x56, 0x9f, 0x00, 0xc4, 0xaf, 0xa1, 0x8a, 0xad, 0x5c, 0x70, ++ 0x0d, 0x4d, 0x3f, 0x92, 0xfc, 0x7a, 0x8a, 0x82, 0x24, 0x34, ++ 0xb6, 0xf8, 0xff, 0x8a, 0x76, 0xea, 0x22, 0xd0, 0x5f, 0x28, ++ 0x45, 0xd9, 0x58, 0xe4, 0x38, 0x6a, 0xc8, 0xfe, 0x6b, 0x68, ++ 0x27, 0x1b, 0xad, 0xeb, 0x32, 0x4d, 0x41, 0x88, 0xb6, 0xf7, ++ 0x02, 0xac, 0x01, 0x68, 0xda, 0xff, 0xd5, 0xac, 0x9f, 0x64, ++ 0x92, 0xa7, 0x18, 0x25, 0x6a, 0x4e, 0xf5, 0xc2, 0xd9, 0x00, ++ 0x88, 0xb2, 0xe0, 0xb8, 0xf0, 0xd0, 0xc6, 0xdb, 0x33, 0xdc, ++ 0x1e, 0x70, 0x5c, 0x63, 0x2f, 0xf4, 0xaa, 0x79, 0x97, 0xfa, ++ 0xbd, 0x42, 0x7f, 0x59, 0x8d, 0x70, 0x6d, 0x5c, 0x75, 0x39, ++ 0x30, 0x91, 0x17, 0x0a, 0x16, 0x16, 0x3d, 0x8a, 0x23, 0xd0, ++ 0x77, 0x2e, 0xfc, 0xf2, 0x0b, 0x85, 0x52, 0xae, 0x00, 0xfc, ++ 0x04, 0x90, 0xa0, 0x5b, 0x0e, 0x07, 0x77, 0x99, 0xfa, 0x32, ++ 0x94, 0x69, 0xae, 0xf9, 0x21, 0x4c, 0x6a, 0x0f, 0xf4, 0xdb, ++ 0x23, 0x8e, 0x62, 0x64, 0xa0, 0x97, 0x6d, 0x1a, 0xcb, 0x2c, ++ 0x17, 0x1c, 0x7d, 0xf2, 0xdc, 0xb6, 0x32, 0xbe, 0xfe, 0xae, ++ 0xee, 0x5b, 0xf8, 0xe5, 0x27, 0xbe, 0x1e, 0x4f, 0xf4, 0x0b, ++ 0x0f, 0xc6, 0x2b, 0xae, 0xec, 0xc0, 0xbd, 0xaa, 0x74, 0xd7, ++ 0x64, 0x08, 0x53, 0xa7, 0x57, 0x45, 0x7a, 0x7d, 0x81, 0x1a, ++ 0xf2, 0xe4, 0x61, 0x65, 0x97, 0xf5, 0x4d, 0x7c, 0x69, 0x13, ++ 0x6d, 0xea, 0x39, 0xd8, 0x52, 0x86, 0xef, 0xd1, 0x6b, 0xbe, ++ 0xf2, 0x9f, 0x18, 0x91, 0xc8, 0x3b, 0x38, 0xe6, 0x2b, 0xb1, ++ 0xe7, 0xef, 0xfc, 0x4f, 0xd7, 0x92, 0x92, 0x60, 0xdd, 0x76, ++ 0x75, 0xa6, 0x68, 0x32, 0xc5, 0x71, 0xba, 0x1f, 0x6a, 0xcb, ++ 0xe2, 0x80, 0x2e, 0xe1, 0xf0, 0x93, 0xec, 0x13, 0x44, 0xc1, ++ 0x1d, 0xc1, 0x84, 0x70, 0x0a, 0x92, 0x9f, 0xa2, 0xde, 0x42, ++ 0x76, 0x70, 0x8a, 0xf6, 0x7a, 0xcd, 0x5f, 0xb0, 0xac, 0x51, ++ 0x16, 0x56, 0xdc, 0xcf, 0x90, 0xa1, 0x7d, 0xfb, 0x13, 0xba, ++ 0x48, 0x01, 0x15, 0x90, 0x43, 0x45, 0x94, 0xcc, 0x23, 0x7d, ++ 0x85, 0x5f, 0xf7, 0xa4, 0x33, 0x80, 0xab, 0xa0, 0xde, 0x25, ++ 0x94, 0x44, 0xec, 0xac, 0x73, 0xa8, 0xb8, 0xce, 0xc9, 0x63, ++ 0x4b, 0x26, 0x43, 0xde, 0xa7, 0x97, 0x2c, 0x5a, 0xed, 0x34, ++ 0x48, 0x8c, 0xfc, 0x27, 0xec, 0x2b, 0x84, 0x8b, 0xae, 0x7c, ++ 0x4e, 0xe6, 0x51, 0xf8, 0xeb, 0xd6, 0x65, 0x04, 0xd2, 0xda, ++ 0x0b, 0x73, 0x8d, 0x2e, 0xd7, 0xa0, 0x74, 0x02, 0xf2, 0xb4, ++ 0xf4, 0x0a, 0x09, 0x06, 0xe3, 0xaa, 0xc9, 0x12, 0x64, 0xda, ++ 0xb4, 0x5c, 0x35, 0xbb, 0x4a, 0xb2, 0xb6, 0x66, 0xb8, 0x65, ++ 0x92, 0x75, 0x29, 0xdc, 0xc5, 0xe4, 0xa3, 0x2d, 0x54, 0xa3, ++ 0x33, 0xc9, 0x70, 0x9b, 0x12, 0x1e, 0x8a, 0x2e, 0x25, 0x8e, ++ 0xb6, 0x56, 0xfd, 0xf6, 0x64, 0xae, 0x2e, 0x64, 0xe2, 0x63, ++ 0x79, 0x7f, 0x3a, 0xe9, 0x4d, 0xdc, 0xf6, 0x4d, 0x29, 0x19, ++ 0xec, 0xcc, 0xc8, 0x0d, 0x96, 0x69, 0x7c, 0x7d, 0x96, 0x9f, ++ 0x34, 0xea, 0xa3, 0xd5, 0x93, 0xaa, 0x5b, 0xaa, 0xe0, 0x98, ++ 0x1f, 0xae, 0x7a, 0xf0, 0xc3, 0x33, 0x99, 0xd6, 0x85, 0x2d, ++ 0x3d, 0x3f, 0xaa, 0xd3, 0xb9, 0x41, 0x5a, 0x1f, 0xfc, 0x5d, ++ 0x90, 0x91, 0x59, 0xb6, 0x3e, 0xf9, 0xbe, 0x7f, 0xf8, 0x36, ++ 0xf1, 0x0d, 0x0d, 0xa5, 0x8b, 0x38, 0x0c, 0x77, 0x7c, 0x7e, ++ 0x8d, 0x86, 0x42, 0x3f, 0x95, 0x9e, 0x62, 0xed, 0x77, 0x30, ++ 0xbb, 0xfe, 0xba, 0x67, 0x62, 0xc5, 0xfc, 0x83, 0x76, 0xbc, ++ 0x6a, 0x52, 0xba, 0x3e, 0x33, 0x89, 0x96, 0xf8, 0xbd, 0x2e, ++ 0x67, 0x04, 0xef, 0xdf, 0xcb, 0x40, 0x9e, 0x0a, 0xb3, 0xf6, ++ 0x93, 0xd8, 0xd1, 0x15, 0x78, 0xbe, 0xdb, 0xc7, 0x31, 0x4f, ++ 0xdc, 0xea, 0x40, 0x58, 0x6b, 0xd6, 0xf1, 0xc7, 0xb4, 0x9d, ++ 0xf8, 0x0b, 0x2f, 0xf0, 0x4b, 0xb9, 0x81, 0xe4, 0x6a, 0xdf, ++ 0x09, 0x4b, 0x6e, 0x6d, 0x82, 0xb7, 0x4b, 0xea, 0xf2, 0x2d, ++ 0x89, 0xac, 0x22, 0xfa, 0x7c, 0x5e, 0xe4, 0x3a, 0xef, 0xae, ++ 0x24, 0x71, 0xca, 0x56, 0xcb, 0x2a, 0x6a, 0xd9, 0x12, 0x80, ++ 0x25, 0x79, 0xe9, 0xbd, 0x9f, 0xa1, 0x36, 0xfb, 0xf6, 0xb2, ++ 0x57, 0x36, 0xa8, 0x7e, 0x5e, 0x17, 0xb9, 0x1a, 0x60, 0x8d, ++ 0xea, 0xb3, 0x96, 0xb5, 0x52, 0xd9, 0xb3, 0xb2, 0xd5, 0x56, ++ 0x7c, 0x86, 0x60, 0x50, 0xca, 0x7b, 0x6f, 0x56, 0xd0, 0xf2, ++ 0x1a, 0xf8, 0xeb, 0x92, 0x91, 0x67, 0x52, 0x97, 0x4f, 0xda, ++ 0x6d, 0x09, 0x9f, 0x06, 0x7d, 0x25, 0xd4, 0x44, 0xbc, 0x2d, ++ 0x52, 0xc1, 0x84, 0x8b, 0xa3, 0xa8, 0x89, 0xdd, 0x54, 0xf6, ++ 0xe1, 0xc8, 0x28, 0x4f, 0xe1, 0x70, 0x5f, 0xb6, 0x9b, 0x5e, ++ 0x7c, 0x8f, 0xb8, 0x84, 0x1a, 0xdc, 0xb3, 0x06, 0xc0, 0xd2, ++ 0x9d, 0x56, 0x2b, 0xad, 0xaa, 0x55, 0x7d, 0x92, 0x9e, 0x59, ++ 0xe5, 0xfe, 0x31, 0x0c, 0x37, 0x6b, 0xc7, 0x53, 0x8a, 0x9f, ++ 0xfd, 0xc6, 0xeb, 0x51, 0xc2, 0x4a, 0xab, 0x68, 0x77, 0x82, ++ 0x97, 0x07, 0x61, 0x31, 0x54, 0xda, 0xa2, 0x92, 0x39, 0xcb, ++ 0xf7, 0xa6, 0x74, 0x95, 0xce, 0xf9, 0x97, 0x87, 0xee, 0x5a, ++ 0x2b, 0xee, 0xd2, 0x35, 0x45, 0x77, 0x68, 0xe4, 0x64, 0x91, ++ 0x88, 0x49, 0x51, 0x1a, 0xaf, 0xaa, 0xc7, 0xc7, 0x69, 0x17, ++ 0x20, 0x09, 0x3d, 0x59, 0xaf, 0x75, 0xea, 0x40, 0x1f, 0x80, ++ 0xb5, 0x9f, 0x1c, 0x1f, 0xdf, 0x6f, 0xe5, 0xfa, 0xbc, 0x27, ++ 0x62, 0xb4, 0xf1, 0x82, 0xb2, 0xa6, 0x17, 0x71, 0x46, 0xf3, ++ 0x70, 0x2b, 0xca, 0x40, 0xd7, 0x32, 0x93, 0xba, 0xff, 0x6a, ++ 0xef, 0x37, 0x01, 0x74, 0x98, 0x93, 0x0b, 0x06, 0xd8, 0xa1, ++ 0x13, 0x30, 0x9d, 0x22, 0x34, 0x73, 0x34, 0x95, 0x3f, 0xc0, ++ 0xad, 0x59, 0x11, 0x73, 0xbd, 0x99, 0x5a, 0x25, 0x5a, 0x5c, ++ 0xa3, 0x54, 0x0c, 0x8c, 0x5f, 0x20, 0x80, 0x79, 0x41, 0x52, ++ 0x49, 0x3e, 0x8f, 0x58, 0x44, 0x98, 0xc3, 0x29, 0xc3, 0x78, ++ 0xd1, 0xdf, 0x3d, 0x2e, 0x8b, 0xf5, 0xc9, 0x8a, 0x81, 0x58, ++ 0xf5, 0xd7, 0xa1, 0xac, 0xc1, 0xbc, 0xba, 0x85, 0x4e, 0x4d, ++ 0x85, 0xd5, 0x8b, 0xd2, 0x3d, 0xa7, 0x72, 0x75, 0xab, 0x26, ++ 0xe7, 0x42, 0xf3, 0xb3, 0xfe, 0xfe, 0x45, 0x65, 0xbc, 0xed, ++ 0x5f, 0x59, 0x47, 0x57, 0x08, 0x40, 0x10, 0xcb, 0x68, 0xc2, ++ 0x9f, 0x10, 0x6f, 0x4e, 0xd9, 0x62, 0x1a, 0x12, 0x3b, 0xf4, ++ 0x4b, 0x14, 0xf8, 0x94, 0xb9, 0x1d, 0xbc, 0x57, 0xfb, 0xb4, ++ 0x94, 0x95, 0xf5, 0x30, 0x64, 0xaa, 0x18, 0xb7, 0xfe, 0x0d, ++ 0xfd, 0xcd, 0x08, 0x72, 0x08, 0xd8, 0xc9, 0xbd, 0x05, 0xbc, ++ 0xb0, 0x76, 0x70, 0xb1, 0x4c, 0x32, 0xbc, 0x6e, 0x1b, 0xc9, ++ 0x11, 0xed, 0xf6, 0xa4, 0x5e, 0x72, 0xc0, 0x11, 0x65, 0xfd, ++ 0x51, 0xb0, 0xb5, 0x27, 0x46, 0x53, 0x71, 0xba, 0xca, 0x69, ++ 0x23, 0x4d, 0x08, 0x1b, 0x37, 0x10, 0x9a, 0x69, 0x31, 0x3c, ++ 0x91, 0x37, 0xbb, 0xa5, 0x2b, 0xbb, 0xdd, 0xd0, 0xd0, 0x1a, ++ 0xcb, 0x2c, 0x67, 0x23, 0xbd, 0xfa, 0xd1, 0xb3, 0x27, 0x7d, ++ 0x84, 0x66, 0xca, 0x68, 0x9b, 0xce, 0x17, 0xda, 0x37, 0xcc, ++ 0xdd, 0xdc, 0xd2, 0x2a, 0x03, 0x85, 0x37, 0x83, 0xae, 0x89, ++ 0x93, 0x8a, 0x1d, 0x16, 0x34, 0xba, 0xd1, 0x79, 0x34, 0x3e, ++ 0xed, 0xe3, 0xe9, 0xb0, 0x21, 0x16, 0xee, 0x07, 0x03, 0x53, ++ 0x45, 0x19, 0x56, 0x06, 0x7a, 0x47, 0x05, 0x03, 0x77, 0x3b, ++ 0x7a, 0x74, 0x07, 0x73, 0xc6, 0x1d, 0x4e, 0x64, 0xef, 0xae, ++ 0x33, 0x54, 0x09, 0x87, 0x73, 0x2a, 0x38, 0xba, 0x22, 0x3b, ++ 0xb4, 0x0b, 0x2c, 0x45, 0x80, 0xf9, 0xe1, 0x15, 0xb6, 0xa6, ++ 0xe7, 0xb9, 0x39, 0xf7, 0xeb, 0x18, 0xba, 0xb7, 0xf4, 0xcb, ++ 0x30, 0x60, 0xc7, 0xb0, 0x7f, 0x1a, 0x45, 0x87, 0x40, 0x85, ++ 0x93, 0xe5, 0x13, 0x59, 0x84, 0xd3, 0xf4, 0x1b, 0x6f, 0xa0, ++ 0x56, 0xfe, 0xf6, 0xae, 0x17, 0xc1, 0x47, 0x98, 0x5a, 0x3d, ++ 0x4d, 0x2e, 0x88, 0x19, 0x62, 0xae, 0x5f, 0x1e, 0x8c, 0xdf, ++ 0x9f, 0x27, 0x7a, 0xef, 0x1a, 0x69, 0x8f, 0x0c, 0xdb, 0x22, ++ 0xd0, 0xde, 0x46, 0xc6, 0x69, 0xee, 0x2f, 0x34, 0x7f, 0x74, ++ 0xdc, 0x6b, 0xf1, 0xfa, 0x5e, 0x7e, 0x7d, 0xa3, 0xd8, 0x39, ++ 0x06, 0x59, 0x65, 0xa4, 0x1c, 0xb4, 0x23, 0xc6, 0xaa, 0xdd, ++ 0x76, 0xf6, 0xbf, 0xa2, 0xc1, 0x1a, 0x26, 0x7a, 0x97, 0x11, ++ 0x06, 0x22, 0x0f, 0x2e, 0xbf, 0xee, 0x78, 0xe1, 0xba, 0xf8, ++ 0x53, 0x91, 0x64, 0x12, 0xdd, 0x12, 0x7b, 0xe5, 0x73, 0x70, ++ 0x3b, 0x45, 0x05, 0x48, 0x39, 0x8d, 0xae, 0xf2, 0xe2, 0xfd, ++ 0x6e, 0x06, 0x20, 0x1f, 0x85, 0x5f, 0xee, 0xe9, 0xfd, 0xca, ++ 0x8c, 0x52, 0x2a, 0x76, 0x45, 0xdb, 0xb2, 0xf3, 0x97, 0x7e, ++ 0x74, 0xb1, 0x61, 0x8d, 0x04, 0xe3, 0xcb, 0x48, 0xfb, 0xca, ++ 0x93, 0xe6, 0x93, 0xec, 0xd0, 0xfd, 0x96, 0xd3, 0xf4, 0xde, ++ 0x7e, 0x19, 0xcd, 0x66, 0xa3, 0xe9, 0xe2, 0xab, 0xd8, 0xff, ++ 0xed, 0xd0, 0x5e, 0x8d, 0xaf, 0x47, 0x8f, 0xf3, 0xb1, 0x5d, ++ 0x7c, 0x1c, 0xdb, 0x87, 0xd9, 0xfd, 0x87, 0xd9, 0xe8, 0x93, ++ 0x9d, 0xcc, 0xc3, 0x4a, 0xec, 0x8d, 0xbd, 0x9d, 0x8d, 0xc7, ++ 0xf6, 0xfe, 0xd6, 0x5e, 0x7f, 0x1c, 0xcd, 0x3e, 0x8c, 0x07, ++ 0x7c, 0x6e, 0x36, 0xe6, 0x13, 0x31, 0x2d, 0x2e, 0xc8, 0x46, ++ 0x04, 0xf0, 0xd4, 0xbd, 0xfc, 0x3c, 0xfe, 0x63, 0x31, 0x9e, ++ 0x2e, 0xec, 0xc3, 0x78, 0xf6, 0x69, 0xb2, 0x58, 0x80, 0xda, ++ 0xd5, 0x57, 0x3b, 0x7a, 0x78, 0x00, 0xf1, 0xd1, 0xd5, 0xdd, ++ 0xd8, 0xde, 0x8d, 0xbe, 0x40, 0x9b, 0xe3, 0x3f, 0xae, 0xc7, ++ 0x0f, 0x0b, 0xfb, 0xe5, 0xe3, 0x78, 0x6a, 0xee, 0x49, 0xfe, ++ 0xcb, 0x04, 0xfc, 0xcc, 0x17, 0x23, 0xbe, 0x30, 0x99, 0xda, ++ 0x2f, 0xb3, 0xc9, 0x62, 0x32, 0xfd, 0x20, 0x04, 0xb9, 0x85, ++ 0x3b, 0x9b, 0x7c, 0xf8, 0xb8, 0xb0, 0x1f, 0xef, 0xef, 0x6e, ++ 0xc6, 0x33, 0x59, 0xd5, 0xfd, 0x19, 0xa7, 0xcb, 0x8b, 0xf6, ++ 0x61, 0x34, 0x5b, 0x4c, 0xc6, 0x73, 0x03, 0x3e, 0x3e, 0x4f, ++ 0x6e, 0xfa, 0x42, 0xbd, 0x19, 0xcd, 0xc1, 0xf6, 0x1b, 0xfb, ++ 0x65, 0xb2, 0xf8, 0x78, 0xff, 0xb8, 0x68, 0x99, 0xa7, 0x70, ++ 0xa3, 0xe9, 0x57, 0xfb, 0xcf, 0xc9, 0xf4, 0x66, 0x60, 0xc7, ++ 0x13, 0x21, 0x34, 0xfe, 0xe3, 0x61, 0x36, 0x9e, 0x43, 0x7e, ++ 0x03, 0xda, 0x93, 0x4f, 0xe0, 0x78, 0x8c, 0x2f, 0x27, 0xd3, ++ 0xeb, 0xbb, 0xc7, 0x1b, 0xd9, 0x02, 0xbe, 0x02, 0x85, 0xe9, ++ 0xfd, 0x02, 0x7a, 0x82, 0x64, 0xe0, 0x73, 0x71, 0x2f, 0xaa, ++ 0x09, 0xcf, 0x06, 0xea, 0x60, 0x06, 0xf4, 0xcd, 0xa7, 0xf1, ++ 0x0c, 0xfa, 0x9b, 0x2e, 0x46, 0x57, 0x93, 0xbb, 0x09, 0x8e, ++ 0xe4, 0xda, 0xf0, 0xed, 0x64, 0x31, 0xc5, 0x11, 0xb2, 0x5c, ++ 0x3c, 0x52, 0xce, 0xaf, 0x1f, 0xef, 0x46, 0x10, 0xe2, 0x71, ++ 0xf6, 0x70, 0x3f, 0x1f, 0x73, 0x7c, 0x43, 0x15, 0x82, 0x08, ++ 0x14, 0x3e, 0x9b, 0xcc, 0xff, 0x69, 0x47, 0x73, 0xe3, 0x15, ++ 0xfb, 0xfb, 0xe3, 0xa8, 0x25, 0x04, 0xed, 0x82, 0xc6, 0xa7, ++ 0xd1, 0xf4, 0x5a, 0x0c, 0x75, 0x64, 0x48, 0x8a, 0x6b, 0xbf, ++ 0xde, 0x3f, 0xb2, 0x6a, 0x40, 0xee, 0xbb, 0x1b, 0x3e, 0x60, ++ 0xc2, 0x03, 0x54, 0xd4, 0xd8, 0xde, 0x8c, 0x6f, 0xc7, 0xd7, ++ 0x8b, 0xc9, 0x67, 0x98, 0x17, 0x4f, 0xe2, 0x98, 0xf9, 0xe3, ++ 0xa7, 0xb1, 0xd7, 0xf7, 0x7c, 0x21, 0x0a, 0xba, 0xbb, 0xb3, ++ 0xd3, 0xf1, 0x35, 0xf8, 0x1d, 0xcd, 0xbe, 0xda, 0xf9, 0x78, ++ 0xf6, 0x79, 0x72, 0x4d, 0x3d, 0x98, 0xd9, 0xf8, 0x61, 0x34, ++ 0x81, 0xfa, 0xb9, 0x20, 0x3d, 0x9b, 0x91, 0xca, 0xfd, 0x54, ++ 0x73, 0xcb, 0xbb, 0x21, 0x8d, 0x07, 0x2f, 0x19, 0x7f, 0xa6, ++ 0x0f, 0x3c, 0x4e, 0xef, 0x28, 0xed, 0x6c, 0xfc, 0xfb, 0x23, ++ 0xe4, 0x39, 0xe3, 0x09, 0xa4, 0x31, 0xfa, 0x00, 0x6f, 0xa3, ++ 0x32, 0x23, 0xbb, 0x9b, 0x2f, 0x13, 0x1c, 0x4e, 0x0b, 0x1d, ++ 0x1b, 0x7f, 0x20, 0xaf, 0xe0, 0x8b, 0xce, 0xf8, 0x5f, 0xe1, ++ 0x46, 0xf7, 0xf6, 0xd3, 0xe8, 0xab, 0x6e, 0x65, 0x7f, 0xf5, ++ 0xee, 0x01, 0x36, 0xdb, 0xb5, 0xed, 0xbe, 0x57, 0xc0, 0x29, ++ 0x3a, 0xef, 0x1c, 0x5d, 0xdd, 0x53, 0x07, 0x57, 0xe0, 0x67, ++ 0x22, 0x6c, 0x81, 0x11, 0x2a, 0x84, 0x26, 0xba, 0x19, 0x7d, ++ 0x1a, 0x7d, 0x18, 0xcf, 0x07, 0xa6, 0x75, 0x02, 0x39, 0xda, ++ 0x6f, 0x92, 0x0f, 0xec, 0xfc, 0x61, 0x7c, 0x3d, 0xe1, 0x5f, ++ 0xf0, 0x3d, 0x5c, 0x0f, 0xb6, 0xbe, 0x53, 0xad, 0x20, 0x8a, ++ 0x7e, 0x7f, 0xa4, 0x15, 0xf1, 0x81, 0x27, 0x62, 0x47, 0x30, ++ 0x27, 0x45, 0xa3, 0x1f, 0x7a, 0x93, 0x31, 0x06, 0xe9, 0x6b, ++ 0xd3, 0xe0, 0x23, 0x38, 0xfb, 0x38, 0x2e, 0x2f, 0xba, 0xb3, ++ 0x8f, 0xfc, 0x8f, 0x7e, 0x71, 0x77, 0x3f, 0xa7, 0xb3, 0xe1, ++ 0x90, 0xc5, 0xc8, 0x0a, 0xc7, 0xf8, 0xf3, 0x6a, 0xcc, 0xa7, ++ 0x67, 0xe3, 0x29, 0xf4, 0x25, 0xe1, 0x34, 0xba, 0xbe, 0x7e, ++ 0x9c, 0x21, 0xb4, 0xf8, 0x04, 0xdf, 0x00, 0x37, 0xf3, 0x47, ++ 0x04, 0xdb, 0x64, 0x2a, 0x46, 0x31, 0x94, 0x57, 0xa2, 0x79, ++ 0x32, 0xbb, 0x09, 0xf1, 0x24, 0x7a, 0xb6, 0xb7, 0xa3, 0xc9, ++ 0xdd, 0xe3, 0xec, 0xc4, 0xc7, 0x70, 0xf2, 0x3d, 0x54, 0x48, ++ 0x92, 0xe2, 0x6b, 0xad, 0x41, 0x82, 0x93, 0xcd, 0x2f, 0x07, ++ 0xe2, 0x03, 0x76, 0x72, 0x8b, 0xa3, 0xae, 0x3f, 0x7a, 0xeb, ++ 0xd9, 0x5e, 0xd4, 0x7e, 0xb5, 0x1f, 0x61, 0x8a, 0xab, 0x31, ++ 0x1e, 0x1b, 0xdd, 0x7c, 0x9e, 0x30, 0xf3, 0xe8, 0x39, 0x06, ++ 0xb1, 0x30, 0x9f, 0x78, 0x9d, 0xdc, 0x7b, 0x0a, 0x5e, 0x8f, ++ 0xed, 0x4e, 0x3f, 0xa2, 0x44, 0x9f, 0x3f, 0xb3, 0xbd, 0x6f, ++ 0xfe, 0x17, 0x84, 0xf3, 0x1b, 0xef, 0x12, 0x3b, 0x00, 0x00, ++ ++}; +Index: u-boot/include/configs/neo1973_gta01.h +=================================================================== +--- u-boot.orig/include/configs/neo1973_gta01.h ++++ u-boot/include/configs/neo1973_gta01.h +@@ -110,6 +110,7 @@ + CFG_CMD_MMC | \ + CFG_CMD_FAT | \ + CFG_CMD_EXT2 | \ ++ CFG_CMD_LICENSE | \ + 0) + /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ + #include +Index: u-boot/include/configs/hxd8.h +=================================================================== +--- u-boot.orig/include/configs/hxd8.h ++++ u-boot/include/configs/hxd8.h +@@ -110,6 +110,7 @@ + CFG_CMD_MMC | \ + CFG_CMD_FAT | \ + CFG_CMD_EXT2 | \ ++ CFG_CMD_LICENSE | \ + 0) + /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ + #include +Index: u-boot/include/configs/smdk2440.h +=================================================================== +--- u-boot.orig/include/configs/smdk2440.h ++++ u-boot/include/configs/smdk2440.h +@@ -110,6 +110,7 @@ + CFG_CMD_PORTIO | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SAVES | \ ++ CFG_CMD_LICENSE | \ + CFG_CMD_USB) + + /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-machtypes.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-machtypes.patch new file mode 100644 index 0000000000..db3cee6e99 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-machtypes.patch @@ -0,0 +1,4121 @@ +This adds a more recent version of mach-types.h to u-boot + +Signed-off-by: Harald Welte + +Index: u-boot/include/asm-arm/mach-types.h +=================================================================== +--- u-boot.orig/include/asm-arm/mach-types.h ++++ u-boot/include/asm-arm/mach-types.h +@@ -424,7 +424,7 @@ + #define MACH_TYPE_MPORT3S 411 + #define MACH_TYPE_RA_ALPHA 412 + #define MACH_TYPE_XCEP 413 +-#define MACH_TYPE_ARCOM_MERCURY 414 ++#define MACH_TYPE_ARCOM_VULCAN 414 + #define MACH_TYPE_STARGATE 415 + #define MACH_TYPE_ARMADILLOJ 416 + #define MACH_TYPE_ELROY_JACK 417 +@@ -457,7 +457,7 @@ + #define MACH_TYPE_XM250 444 + #define MACH_TYPE_T6TC1XB 445 + #define MACH_TYPE_ESS710 446 +-#define MACH_TYPE_MX3ADS 447 ++#define MACH_TYPE_MX31ADS 447 + #define MACH_TYPE_HIMALAYA 448 + #define MACH_TYPE_BOLFENK 449 + #define MACH_TYPE_AT91RM9200KR 450 +@@ -736,7 +736,311 @@ + #define MACH_TYPE_LN2410SBC 725 + #define MACH_TYPE_CB3RUFC 726 + #define MACH_TYPE_MP2USB 727 +-#define MACH_TYPE_PDNB3 1002 ++#define MACH_TYPE_NTNP425C 728 ++#define MACH_TYPE_COLIBRI 729 ++#define MACH_TYPE_PCM7220 730 ++#define MACH_TYPE_GATEWAY7001 731 ++#define MACH_TYPE_PCM027 732 ++#define MACH_TYPE_CMPXA 733 ++#define MACH_TYPE_ANUBIS 734 ++#define MACH_TYPE_ITE8152 735 ++#define MACH_TYPE_LPC3XXX 736 ++#define MACH_TYPE_PUPPETEER 737 ++#define MACH_TYPE_MACH_VADATECH 738 ++#define MACH_TYPE_E570 739 ++#define MACH_TYPE_X50 740 ++#define MACH_TYPE_RECON 741 ++#define MACH_TYPE_XBOARDGP8 742 ++#define MACH_TYPE_FPIC2 743 ++#define MACH_TYPE_AKITA 744 ++#define MACH_TYPE_A81 745 ++#define MACH_TYPE_SVM_SC25X 746 ++#define MACH_TYPE_VADATECH020 747 ++#define MACH_TYPE_TLI 748 ++#define MACH_TYPE_EDB9315LC 749 ++#define MACH_TYPE_PASSEC 750 ++#define MACH_TYPE_DS_TIGER 751 ++#define MACH_TYPE_E310 752 ++#define MACH_TYPE_E330 753 ++#define MACH_TYPE_RT3000 754 ++#define MACH_TYPE_NOKIA770 755 ++#define MACH_TYPE_PNX0106 756 ++#define MACH_TYPE_HX21XX 757 ++#define MACH_TYPE_FARADAY 758 ++#define MACH_TYPE_SBC9312 759 ++#define MACH_TYPE_BATMAN 760 ++#define MACH_TYPE_JPD201 761 ++#define MACH_TYPE_MIPSA 762 ++#define MACH_TYPE_KACOM 763 ++#define MACH_TYPE_SWARCOCPU 764 ++#define MACH_TYPE_SWARCODSL 765 ++#define MACH_TYPE_BLUEANGEL 766 ++#define MACH_TYPE_HAIRYGRAMA 767 ++#define MACH_TYPE_BANFF 768 ++#define MACH_TYPE_CARMEVA 769 ++#define MACH_TYPE_SAM255 770 ++#define MACH_TYPE_PPM10 771 ++#define MACH_TYPE_EDB9315A 772 ++#define MACH_TYPE_SUNSET 773 ++#define MACH_TYPE_STARGATE2 774 ++#define MACH_TYPE_INTELMOTE2 775 ++#define MACH_TYPE_TRIZEPS4 776 ++#define MACH_TYPE_MAINSTONE2 777 ++#define MACH_TYPE_EZ_IXP42X 778 ++#define MACH_TYPE_TAPWAVE_ZODIAC 779 ++#define MACH_TYPE_UNIVERSALMETER 780 ++#define MACH_TYPE_HICOARM9 781 ++#define MACH_TYPE_PNX4008 782 ++#define MACH_TYPE_KWS6000 783 ++#define MACH_TYPE_PORTUX920T 784 ++#define MACH_TYPE_EZ_X5 785 ++#define MACH_TYPE_OMAP_RUDOLPH 786 ++#define MACH_TYPE_CPUAT91 787 ++#define MACH_TYPE_REA9200 788 ++#define MACH_TYPE_ACTS_PUNE_SA1110 789 ++#define MACH_TYPE_IXP425 790 ++#define MACH_TYPE_ARGONPLUSODYSSEY 791 ++#define MACH_TYPE_PERCH 792 ++#define MACH_TYPE_EIS05R1 793 ++#define MACH_TYPE_PEPPERPAD 794 ++#define MACH_TYPE_SB3010 795 ++#define MACH_TYPE_RM9200 796 ++#define MACH_TYPE_DMA03 797 ++#define MACH_TYPE_ROAD_S101 798 ++#define MACH_TYPE_IQ_NEXTGEN_A 799 ++#define MACH_TYPE_IQ_NEXTGEN_B 800 ++#define MACH_TYPE_IQ_NEXTGEN_C 801 ++#define MACH_TYPE_IQ_NEXTGEN_D 802 ++#define MACH_TYPE_IQ_NEXTGEN_E 803 ++#define MACH_TYPE_MALLOW_AT91 804 ++#define MACH_TYPE_CYBERTRACKER_I 805 ++#define MACH_TYPE_GESBC931X 806 ++#define MACH_TYPE_CENTIPAD 807 ++#define MACH_TYPE_ARMSOC 808 ++#define MACH_TYPE_SE4200 809 ++#define MACH_TYPE_EMS197A 810 ++#define MACH_TYPE_MICRO9 811 ++#define MACH_TYPE_MICRO9L 812 ++#define MACH_TYPE_UC5471DSP 813 ++#define MACH_TYPE_SJ5471ENG 814 ++#define MACH_TYPE_CMPXA26X 815 ++#define MACH_TYPE_NC 816 ++#define MACH_TYPE_OMAP_PALMTE 817 ++#define MACH_TYPE_AJAX52X 818 ++#define MACH_TYPE_SIRIUSTAR 819 ++#define MACH_TYPE_IODATA_HDLG 820 ++#define MACH_TYPE_AT91RM9200UTL 821 ++#define MACH_TYPE_BIOSAFE 822 ++#define MACH_TYPE_MP1000 823 ++#define MACH_TYPE_PARSY 824 ++#define MACH_TYPE_CCXP 825 ++#define MACH_TYPE_OMAP_GSAMPLE 826 ++#define MACH_TYPE_REALVIEW_EB 827 ++#define MACH_TYPE_SAMOA 828 ++#define MACH_TYPE_T3XSCALE 829 ++#define MACH_TYPE_I878 830 ++#define MACH_TYPE_BORZOI 831 ++#define MACH_TYPE_GECKO 832 ++#define MACH_TYPE_DS101 833 ++#define MACH_TYPE_OMAP_PALMTT2 834 ++#define MACH_TYPE_XSCALE_PALMLD 835 ++#define MACH_TYPE_CC9C 836 ++#define MACH_TYPE_SBC1670 837 ++#define MACH_TYPE_IXDP28X5 838 ++#define MACH_TYPE_OMAP_PALMTT 839 ++#define MACH_TYPE_ML696K 840 ++#define MACH_TYPE_ARCOM_ZEUS 841 ++#define MACH_TYPE_OSIRIS 842 ++#define MACH_TYPE_MAESTRO 843 ++#define MACH_TYPE_TUNGE2 844 ++#define MACH_TYPE_IXBBM 845 ++#define MACH_TYPE_MX27 846 ++#define MACH_TYPE_AX8004 847 ++#define MACH_TYPE_AT91SAM9261EK 848 ++#define MACH_TYPE_LOFT 849 ++#define MACH_TYPE_MAGPIE 850 ++#define MACH_TYPE_MX21 851 ++#define MACH_TYPE_MB87M3400 852 ++#define MACH_TYPE_MGUARD_DELTA 853 ++#define MACH_TYPE_DAVINCI_DVDP 854 ++#define MACH_TYPE_HTCUNIVERSAL 855 ++#define MACH_TYPE_TPAD 856 ++#define MACH_TYPE_ROVERP3 857 ++#define MACH_TYPE_JORNADA928 858 ++#define MACH_TYPE_MV88FXX81 859 ++#define MACH_TYPE_STMP36XX 860 ++#define MACH_TYPE_SXNI79524 861 ++#define MACH_TYPE_AMS_DELTA 862 ++#define MACH_TYPE_URANIUM 863 ++#define MACH_TYPE_UCON 864 ++#define MACH_TYPE_NAS100D 865 ++#define MACH_TYPE_L083_1000 866 ++#define MACH_TYPE_EZX 867 ++#define MACH_TYPE_PNX5220 868 ++#define MACH_TYPE_BUTTE 869 ++#define MACH_TYPE_SRM2 870 ++#define MACH_TYPE_DSBR 871 ++#define MACH_TYPE_CRYSTALBALL 872 ++#define MACH_TYPE_TINYPXA27X 873 ++#define MACH_TYPE_HERBIE 874 ++#define MACH_TYPE_MAGICIAN 875 ++#define MACH_TYPE_CM4002 876 ++#define MACH_TYPE_B4 877 ++#define MACH_TYPE_MAUI 878 ++#define MACH_TYPE_CYBERTRACKER_G 879 ++#define MACH_TYPE_NXDKN 880 ++#define MACH_TYPE_MIO8390 881 ++#define MACH_TYPE_OMI_BOARD 882 ++#define MACH_TYPE_MX21CIV 883 ++#define MACH_TYPE_MAHI_CDAC 884 ++#define MACH_TYPE_XSCALE_PALMTX 885 ++#define MACH_TYPE_S3C2413 887 ++#define MACH_TYPE_SAMSYS_EP0 888 ++#define MACH_TYPE_WG302V1 889 ++#define MACH_TYPE_WG302V2 890 ++#define MACH_TYPE_EB42X 891 ++#define MACH_TYPE_IQ331ES 892 ++#define MACH_TYPE_COSYDSP 893 ++#define MACH_TYPE_UPLAT7D 894 ++#define MACH_TYPE_PTDAVINCI 895 ++#define MACH_TYPE_MBUS 896 ++#define MACH_TYPE_NADIA2VB 897 ++#define MACH_TYPE_R1000 898 ++#define MACH_TYPE_HW90250 899 ++#define MACH_TYPE_OMAP_2430SDP 900 ++#define MACH_TYPE_DAVINCI_EVM 901 ++#define MACH_TYPE_OMAP_TORNADO 902 ++#define MACH_TYPE_OLOCREEK 903 ++#define MACH_TYPE_PALMZ72 904 ++#define MACH_TYPE_NXDB500 905 ++#define MACH_TYPE_APF9328 906 ++#define MACH_TYPE_OMAP_WIPOQ 907 ++#define MACH_TYPE_OMAP_TWIP 908 ++#define MACH_TYPE_XSCALE_PALMTREO650 909 ++#define MACH_TYPE_ACUMEN 910 ++#define MACH_TYPE_XP100 911 ++#define MACH_TYPE_FS2410 912 ++#define MACH_TYPE_PXA270_CERF 913 ++#define MACH_TYPE_SQ2FTLPALM 914 ++#define MACH_TYPE_BSEMSERVER 915 ++#define MACH_TYPE_NETCLIENT 916 ++#define MACH_TYPE_XSCALE_PALMTT5 917 ++#define MACH_TYPE_OMAP_PALMTC 918 ++#define MACH_TYPE_OMAP_APOLLON 919 ++#define MACH_TYPE_ARGONLVEVB 920 ++#define MACH_TYPE_REA_2D 921 ++#define MACH_TYPE_TI3E524 922 ++#define MACH_TYPE_ATEB9200 923 ++#define MACH_TYPE_AUCKLAND 924 ++#define MACH_TYPE_AK3320M 925 ++#define MACH_TYPE_DURAMAX 926 ++#define MACH_TYPE_N35 927 ++#define MACH_TYPE_PRONGHORN 928 ++#define MACH_TYPE_FUNDY 929 ++#define MACH_TYPE_LOGICPD_PXA270 930 ++#define MACH_TYPE_CPU777 931 ++#define MACH_TYPE_SIMICON9201 932 ++#define MACH_TYPE_LEAP2_HPM 933 ++#define MACH_TYPE_CM922TXA10 934 ++#define MACH_TYPE_PXA 935 ++#define MACH_TYPE_SANDGATE2 936 ++#define MACH_TYPE_SANDGATE2G 937 ++#define MACH_TYPE_SANDGATE2P 938 ++#define MACH_TYPE_FRED_JACK 939 ++#define MACH_TYPE_TTG_COLOR1 940 ++#define MACH_TYPE_NXEB500HMI 941 ++#define MACH_TYPE_NETDCU8 942 ++#define MACH_TYPE_ML675050_CPU_BOA 943 ++#define MACH_TYPE_NG_FVX538 944 ++#define MACH_TYPE_NG_FVS338 945 ++#define MACH_TYPE_PNX4103 946 ++#define MACH_TYPE_HESDB 947 ++#define MACH_TYPE_XSILO 948 ++#define MACH_TYPE_ESPRESSO 949 ++#define MACH_TYPE_EMLC 950 ++#define MACH_TYPE_SISTERON 951 ++#define MACH_TYPE_RX1950 952 ++#define MACH_TYPE_TSC_VENUS 953 ++#define MACH_TYPE_DS101J 954 ++#define MACH_TYPE_MXC30030ADS 955 ++#define MACH_TYPE_FUJITSU_WIMAXSOC 956 ++#define MACH_TYPE_DUALPCMODEM 957 ++#define MACH_TYPE_GESBC9312 958 ++#define MACH_TYPE_HTCAPACHE 959 ++#define MACH_TYPE_IXDP435 960 ++#define MACH_TYPE_CATPROVT100 961 ++#define MACH_TYPE_PICOTUX1XX 962 ++#define MACH_TYPE_PICOTUX2XX 963 ++#define MACH_TYPE_DSMG600 964 ++#define MACH_TYPE_EMPC2 965 ++#define MACH_TYPE_VENTURA 966 ++#define MACH_TYPE_PHIDGET_SBC 967 ++#define MACH_TYPE_IJ3K 968 ++#define MACH_TYPE_PISGAH 969 ++#define MACH_TYPE_OMAP_FSAMPLE 970 ++#define MACH_TYPE_SG720 971 ++#define MACH_TYPE_REDFOX 972 ++#define MACH_TYPE_MYSH_EP9315_1 973 ++#define MACH_TYPE_TPF106 974 ++#define MACH_TYPE_AT91RM9200KG 975 ++#define MACH_TYPE_SLEDB 976 ++#define MACH_TYPE_ONTRACK 977 ++#define MACH_TYPE_PM1200 978 ++#define MACH_TYPE_ESS24XXX 979 ++#define MACH_TYPE_COREMP7 980 ++#define MACH_TYPE_NEXCODER_6446 981 ++#define MACH_TYPE_STVC8380 982 ++#define MACH_TYPE_TEKLYNX 983 ++#define MACH_TYPE_CARBONADO 984 ++#define MACH_TYPE_SYSMOS_MP730 985 ++#define MACH_TYPE_SNAPPER_CL15 986 ++#define MACH_TYPE_PGIGIM 987 ++#define MACH_TYPE_PTX9160P2 988 ++#define MACH_TYPE_DCORE1 989 ++#define MACH_TYPE_VICTORPXA 990 ++#define MACH_TYPE_MX2DTB 991 ++#define MACH_TYPE_PXA_IREX_ER0100 992 ++#define MACH_TYPE_OMAP_PALMZ71 993 ++#define MACH_TYPE_BARTEC_DEG 994 ++#define MACH_TYPE_HW50251 995 ++#define MACH_TYPE_IBOX 996 ++#define MACH_TYPE_ATLASLH7A404 997 ++#define MACH_TYPE_PT2026 998 ++#define MACH_TYPE_HTCALPINE 999 ++#define MACH_TYPE_BARTEC_VTU 1000 ++#define MACH_TYPE_VCOREII 1001 ++#define MACH_TYPE_PDNB3 1002 ++#define MACH_TYPE_HTCBEETLES 1003 ++#define MACH_TYPE_S3C6400 1004 ++#define MACH_TYPE_S3C2443 1005 ++#define MACH_TYPE_OMAP_LDK 1006 ++#define MACH_TYPE_SMDK2460 1007 ++#define MACH_TYPE_SMDK2440 1008 ++#define MACH_TYPE_SMDK2412 1009 ++#define MACH_TYPE_WEBBOX 1010 ++#define MACH_TYPE_CWWNDP 1011 ++#define MACH_TYPE_DRAGON 1012 ++#define MACH_TYPE_OPENDO_CPU_BOARD 1013 ++#define MACH_TYPE_CCM2200 1014 ++#define MACH_TYPE_ETWARM 1015 ++#define MACH_TYPE_M93030 1016 ++#define MACH_TYPE_CC7U 1017 ++#define MACH_TYPE_MTT_RANGER 1018 ++#define MACH_TYPE_NEXUS 1019 ++#define MACH_TYPE_DESMAN 1020 ++#define MACH_TYPE_BKDE303 1021 ++#define MACH_TYPE_SMDK2413 1022 ++#define MACH_TYPE_AML_M7200 1023 ++#define MACH_TYPE_AML_M5900 1024 ++#define MACH_TYPE_SG640 1025 ++#define MACH_TYPE_EDG79524 1026 ++#define MACH_TYPE_AI2410 1027 ++#define MACH_TYPE_IXP465 1028 ++#define MACH_TYPE_BALLOON3 1029 ++#define MACH_TYPE_QT2410 1108 ++#define MACH_TYPE_NEO1973_GTA01 1182 ++#define MACH_TYPE_HXD8 1303 ++#define MACH_TYPE_NEO1973_GTA02 1304 + + #ifdef CONFIG_ARCH_EBSA110 + # ifdef machine_arch_type +@@ -3541,9 +3845,9 @@ + # else + # define machine_arch_type MACH_TYPE_RAMSES + # endif +-# define machine_is_ramses() (machine_arch_type == MACH_TYPE_RAMSES) ++# define machine_is_mnci() (machine_arch_type == MACH_TYPE_RAMSES) + #else +-# define machine_is_ramses() (0) ++# define machine_is_mnci() (0) + #endif + + #ifdef CONFIG_ARCH_S28X +@@ -4501,9 +4805,9 @@ + # else + # define machine_arch_type MACH_TYPE_M825XX + # endif +-# define machine_is_m825xx() (machine_arch_type == MACH_TYPE_M825XX) ++# define machine_is_comcerto() (machine_arch_type == MACH_TYPE_M825XX) + #else +-# define machine_is_m825xx() (0) ++# define machine_is_comcerto() (0) + #endif + + #ifdef CONFIG_SA1100_M7100 +@@ -5658,16 +5962,16 @@ + # define machine_is_xcep() (0) + #endif + +-#ifdef CONFIG_MACH_ARCOM_MERCURY ++#ifdef CONFIG_MACH_ARCOM_VULCAN + # ifdef machine_arch_type + # undef machine_arch_type + # define machine_arch_type __machine_arch_type + # else +-# define machine_arch_type MACH_TYPE_ARCOM_MERCURY ++# define machine_arch_type MACH_TYPE_ARCOM_VULCAN + # endif +-# define machine_is_arcom_mercury() (machine_arch_type == MACH_TYPE_ARCOM_MERCURY) ++# define machine_is_arcom_vulcan() (machine_arch_type == MACH_TYPE_ARCOM_VULCAN) + #else +-# define machine_is_arcom_mercury() (0) ++# define machine_is_arcom_vulcan() (0) + #endif + + #ifdef CONFIG_MACH_STARGATE +@@ -6054,16 +6358,16 @@ + # define machine_is_ess710() (0) + #endif + +-#ifdef CONFIG_MACH_MX3ADS ++#ifdef CONFIG_MACH_MX31ADS + # ifdef machine_arch_type + # undef machine_arch_type + # define machine_arch_type __machine_arch_type + # else +-# define machine_arch_type MACH_TYPE_MX3ADS ++# define machine_arch_type MACH_TYPE_MX31ADS + # endif +-# define machine_is_mx3ads() (machine_arch_type == MACH_TYPE_MX3ADS) ++# define machine_is_mx31ads() (machine_arch_type == MACH_TYPE_MX31ADS) + #else +-# define machine_is_mx3ads() (0) ++# define machine_is_mx31ads() (0) + #endif + + #ifdef CONFIG_MACH_HIMALAYA +@@ -7333,9 +7637,9 @@ + # else + # define machine_arch_type MACH_TYPE_ARGONPLUSEVB + # endif +-# define machine_is_argonplusevb() (machine_arch_type == MACH_TYPE_ARGONPLUSEVB) ++# define machine_is_i30030evb() (machine_arch_type == MACH_TYPE_ARGONPLUSEVB) + #else +-# define machine_is_argonplusevb() (0) ++# define machine_is_i30030evb() (0) + #endif + + #ifdef CONFIG_MACH_SCMA11EVB +@@ -7345,9 +7649,9 @@ + # else + # define machine_arch_type MACH_TYPE_SCMA11EVB + # endif +-# define machine_is_scma11evb() (machine_arch_type == MACH_TYPE_SCMA11EVB) ++# define machine_is_mxc27530evb() (machine_arch_type == MACH_TYPE_SCMA11EVB) + #else +-# define machine_is_scma11evb() (0) ++# define machine_is_mxc27530evb() (0) + #endif + + #ifdef CONFIG_MACH_SMDK2800 +@@ -8305,9 +8609,9 @@ + # else + # define machine_arch_type MACH_TYPE_SCMA11BB + # endif +-# define machine_is_scma11bb() (machine_arch_type == MACH_TYPE_SCMA11BB) ++# define machine_is_mxc27530ads() (machine_arch_type == MACH_TYPE_SCMA11BB) + #else +-# define machine_is_scma11bb() (0) ++# define machine_is_mxc27530ads() (0) + #endif + + #ifdef CONFIG_MACH_TRIZEPS3 +@@ -9193,9 +9497,9 @@ + # else + # define machine_arch_type MACH_TYPE_ZEUSEVB + # endif +-# define machine_is_zeusevb() (machine_arch_type == MACH_TYPE_ZEUSEVB) ++# define machine_is_mxc91131evb() (machine_arch_type == MACH_TYPE_ZEUSEVB) + #else +-# define machine_is_zeusevb() (0) ++# define machine_is_mxc91131evb() (0) + #endif + + #ifdef CONFIG_MACH_P700 +@@ -9402,6 +9706,3667 @@ + # define machine_is_mp2usb() (0) + #endif + ++#ifdef CONFIG_MACH_NTNP425C ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_NTNP425C ++# endif ++# define machine_is_ntnp425c() (machine_arch_type == MACH_TYPE_NTNP425C) ++#else ++# define machine_is_ntnp425c() (0) ++#endif ++ ++#ifdef CONFIG_MACH_COLIBRI ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_COLIBRI ++# endif ++# define machine_is_colibri() (machine_arch_type == MACH_TYPE_COLIBRI) ++#else ++# define machine_is_colibri() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PCM7220 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PCM7220 ++# endif ++# define machine_is_pcm7220() (machine_arch_type == MACH_TYPE_PCM7220) ++#else ++# define machine_is_pcm7220() (0) ++#endif ++ ++#ifdef CONFIG_MACH_GATEWAY7001 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_GATEWAY7001 ++# endif ++# define machine_is_gateway7001() (machine_arch_type == MACH_TYPE_GATEWAY7001) ++#else ++# define machine_is_gateway7001() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PCM027 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PCM027 ++# endif ++# define machine_is_pcm027() (machine_arch_type == MACH_TYPE_PCM027) ++#else ++# define machine_is_pcm027() (0) ++#endif ++ ++#ifdef CONFIG_MACH_CMPXA ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_CMPXA ++# endif ++# define machine_is_cmpxa() (machine_arch_type == MACH_TYPE_CMPXA) ++#else ++# define machine_is_cmpxa() (0) ++#endif ++ ++#ifdef CONFIG_MACH_ANUBIS ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_ANUBIS ++# endif ++# define machine_is_anubis() (machine_arch_type == MACH_TYPE_ANUBIS) ++#else ++# define machine_is_anubis() (0) ++#endif ++ ++#ifdef CONFIG_MACH_ITE8152 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_ITE8152 ++# endif ++# define machine_is_ite8152() (machine_arch_type == MACH_TYPE_ITE8152) ++#else ++# define machine_is_ite8152() (0) ++#endif ++ ++#ifdef CONFIG_MACH_LPC3XXX ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_LPC3XXX ++# endif ++# define machine_is_lpc3xxx() (machine_arch_type == MACH_TYPE_LPC3XXX) ++#else ++# define machine_is_lpc3xxx() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PUPPETEER ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PUPPETEER ++# endif ++# define machine_is_puppeteer() (machine_arch_type == MACH_TYPE_PUPPETEER) ++#else ++# define machine_is_puppeteer() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MACH_VADATECH ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MACH_VADATECH ++# endif ++# define machine_is_vt001() (machine_arch_type == MACH_TYPE_MACH_VADATECH) ++#else ++# define machine_is_vt001() (0) ++#endif ++ ++#ifdef CONFIG_MACH_E570 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_E570 ++# endif ++# define machine_is_e570() (machine_arch_type == MACH_TYPE_E570) ++#else ++# define machine_is_e570() (0) ++#endif ++ ++#ifdef CONFIG_MACH_X50 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_X50 ++# endif ++# define machine_is_x50() (machine_arch_type == MACH_TYPE_X50) ++#else ++# define machine_is_x50() (0) ++#endif ++ ++#ifdef CONFIG_MACH_RECON ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_RECON ++# endif ++# define machine_is_recon() (machine_arch_type == MACH_TYPE_RECON) ++#else ++# define machine_is_recon() (0) ++#endif ++ ++#ifdef CONFIG_MACH_XBOARDGP8 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_XBOARDGP8 ++# endif ++# define machine_is_xboardgp8() (machine_arch_type == MACH_TYPE_XBOARDGP8) ++#else ++# define machine_is_xboardgp8() (0) ++#endif ++ ++#ifdef CONFIG_MACH_FPIC2 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_FPIC2 ++# endif ++# define machine_is_fpic2() (machine_arch_type == MACH_TYPE_FPIC2) ++#else ++# define machine_is_fpic2() (0) ++#endif ++ ++#ifdef CONFIG_MACH_AKITA ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_AKITA ++# endif ++# define machine_is_akita() (machine_arch_type == MACH_TYPE_AKITA) ++#else ++# define machine_is_akita() (0) ++#endif ++ ++#ifdef CONFIG_MACH_A81 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_A81 ++# endif ++# define machine_is_a81() (machine_arch_type == MACH_TYPE_A81) ++#else ++# define machine_is_a81() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SVM_SC25X ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SVM_SC25X ++# endif ++# define machine_is_svm_sc25x() (machine_arch_type == MACH_TYPE_SVM_SC25X) ++#else ++# define machine_is_svm_sc25x() (0) ++#endif ++ ++#ifdef CONFIG_MACH_VADATECH020 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_VADATECH020 ++# endif ++# define machine_is_vt020() (machine_arch_type == MACH_TYPE_VADATECH020) ++#else ++# define machine_is_vt020() (0) ++#endif ++ ++#ifdef CONFIG_MACH_TLI ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_TLI ++# endif ++# define machine_is_tli() (machine_arch_type == MACH_TYPE_TLI) ++#else ++# define machine_is_tli() (0) ++#endif ++ ++#ifdef CONFIG_MACH_EDB9315LC ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_EDB9315LC ++# endif ++# define machine_is_edb9315lc() (machine_arch_type == MACH_TYPE_EDB9315LC) ++#else ++# define machine_is_edb9315lc() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PASSEC ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PASSEC ++# endif ++# define machine_is_passec() (machine_arch_type == MACH_TYPE_PASSEC) ++#else ++# define machine_is_passec() (0) ++#endif ++ ++#ifdef CONFIG_MACH_DS_TIGER ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_DS_TIGER ++# endif ++# define machine_is_ds_tiger() (machine_arch_type == MACH_TYPE_DS_TIGER) ++#else ++# define machine_is_ds_tiger() (0) ++#endif ++ ++#ifdef CONFIG_MACH_E310 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_E310 ++# endif ++# define machine_is_e310() (machine_arch_type == MACH_TYPE_E310) ++#else ++# define machine_is_e310() (0) ++#endif ++ ++#ifdef CONFIG_MACH_E330 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_E330 ++# endif ++# define machine_is_e330() (machine_arch_type == MACH_TYPE_E330) ++#else ++# define machine_is_e330() (0) ++#endif ++ ++#ifdef CONFIG_MACH_RT3000 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_RT3000 ++# endif ++# define machine_is_rt3000() (machine_arch_type == MACH_TYPE_RT3000) ++#else ++# define machine_is_rt3000() (0) ++#endif ++ ++#ifdef CONFIG_MACH_NOKIA770 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_NOKIA770 ++# endif ++# define machine_is_nokia770() (machine_arch_type == MACH_TYPE_NOKIA770) ++#else ++# define machine_is_nokia770() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PNX0106 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PNX0106 ++# endif ++# define machine_is_pnx0106() (machine_arch_type == MACH_TYPE_PNX0106) ++#else ++# define machine_is_pnx0106() (0) ++#endif ++ ++#ifdef CONFIG_MACH_HX21XX ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_HX21XX ++# endif ++# define machine_is_hx21xx() (machine_arch_type == MACH_TYPE_HX21XX) ++#else ++# define machine_is_hx21xx() (0) ++#endif ++ ++#ifdef CONFIG_MACH_FARADAY ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_FARADAY ++# endif ++# define machine_is_faraday() (machine_arch_type == MACH_TYPE_FARADAY) ++#else ++# define machine_is_faraday() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SBC9312 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SBC9312 ++# endif ++# define machine_is_sbc9312() (machine_arch_type == MACH_TYPE_SBC9312) ++#else ++# define machine_is_sbc9312() (0) ++#endif ++ ++#ifdef CONFIG_MACH_BATMAN ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_BATMAN ++# endif ++# define machine_is_batman() (machine_arch_type == MACH_TYPE_BATMAN) ++#else ++# define machine_is_batman() (0) ++#endif ++ ++#ifdef CONFIG_MACH_JPD201 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_JPD201 ++# endif ++# define machine_is_jpd201() (machine_arch_type == MACH_TYPE_JPD201) ++#else ++# define machine_is_jpd201() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MIPSA ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MIPSA ++# endif ++# define machine_is_mipsa() (machine_arch_type == MACH_TYPE_MIPSA) ++#else ++# define machine_is_mipsa() (0) ++#endif ++ ++#ifdef CONFIG_MACH_KACOM ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_KACOM ++# endif ++# define machine_is_kacom() (machine_arch_type == MACH_TYPE_KACOM) ++#else ++# define machine_is_kacom() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SWARCOCPU ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SWARCOCPU ++# endif ++# define machine_is_swarcocpu() (machine_arch_type == MACH_TYPE_SWARCOCPU) ++#else ++# define machine_is_swarcocpu() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SWARCODSL ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SWARCODSL ++# endif ++# define machine_is_swarcodsl() (machine_arch_type == MACH_TYPE_SWARCODSL) ++#else ++# define machine_is_swarcodsl() (0) ++#endif ++ ++#ifdef CONFIG_MACH_BLUEANGEL ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_BLUEANGEL ++# endif ++# define machine_is_blueangel() (machine_arch_type == MACH_TYPE_BLUEANGEL) ++#else ++# define machine_is_blueangel() (0) ++#endif ++ ++#ifdef CONFIG_MACH_HAIRYGRAMA ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_HAIRYGRAMA ++# endif ++# define machine_is_hairygrama() (machine_arch_type == MACH_TYPE_HAIRYGRAMA) ++#else ++# define machine_is_hairygrama() (0) ++#endif ++ ++#ifdef CONFIG_MACH_BANFF ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_BANFF ++# endif ++# define machine_is_banff() (machine_arch_type == MACH_TYPE_BANFF) ++#else ++# define machine_is_banff() (0) ++#endif ++ ++#ifdef CONFIG_MACH_CARMEVA ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_CARMEVA ++# endif ++# define machine_is_carmeva() (machine_arch_type == MACH_TYPE_CARMEVA) ++#else ++# define machine_is_carmeva() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SAM255 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SAM255 ++# endif ++# define machine_is_sam255() (machine_arch_type == MACH_TYPE_SAM255) ++#else ++# define machine_is_sam255() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PPM10 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PPM10 ++# endif ++# define machine_is_ppm10() (machine_arch_type == MACH_TYPE_PPM10) ++#else ++# define machine_is_ppm10() (0) ++#endif ++ ++#ifdef CONFIG_MACH_EDB9315A ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_EDB9315A ++# endif ++# define machine_is_edb9315a() (machine_arch_type == MACH_TYPE_EDB9315A) ++#else ++# define machine_is_edb9315a() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SUNSET ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SUNSET ++# endif ++# define machine_is_sunset() (machine_arch_type == MACH_TYPE_SUNSET) ++#else ++# define machine_is_sunset() (0) ++#endif ++ ++#ifdef CONFIG_MACH_STARGATE2 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_STARGATE2 ++# endif ++# define machine_is_stargate2() (machine_arch_type == MACH_TYPE_STARGATE2) ++#else ++# define machine_is_stargate2() (0) ++#endif ++ ++#ifdef CONFIG_MACH_INTELMOTE2 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_INTELMOTE2 ++# endif ++# define machine_is_intelmote2() (machine_arch_type == MACH_TYPE_INTELMOTE2) ++#else ++# define machine_is_intelmote2() (0) ++#endif ++ ++#ifdef CONFIG_MACH_TRIZEPS4 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_TRIZEPS4 ++# endif ++# define machine_is_trizeps4() (machine_arch_type == MACH_TYPE_TRIZEPS4) ++#else ++# define machine_is_trizeps4() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MAINSTONE2 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MAINSTONE2 ++# endif ++# define machine_is_mainstone2() (machine_arch_type == MACH_TYPE_MAINSTONE2) ++#else ++# define machine_is_mainstone2() (0) ++#endif ++ ++#ifdef CONFIG_MACH_EZ_IXP42X ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_EZ_IXP42X ++# endif ++# define machine_is_ez_ixp42x() (machine_arch_type == MACH_TYPE_EZ_IXP42X) ++#else ++# define machine_is_ez_ixp42x() (0) ++#endif ++ ++#ifdef CONFIG_MACH_TAPWAVE_ZODIAC ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_TAPWAVE_ZODIAC ++# endif ++# define machine_is_tapwave_zodiac() (machine_arch_type == MACH_TYPE_TAPWAVE_ZODIAC) ++#else ++# define machine_is_tapwave_zodiac() (0) ++#endif ++ ++#ifdef CONFIG_MACH_UNIVERSALMETER ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_UNIVERSALMETER ++# endif ++# define machine_is_universalmeter() (machine_arch_type == MACH_TYPE_UNIVERSALMETER) ++#else ++# define machine_is_universalmeter() (0) ++#endif ++ ++#ifdef CONFIG_MACH_HICOARM9 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_HICOARM9 ++# endif ++# define machine_is_hicoarm9() (machine_arch_type == MACH_TYPE_HICOARM9) ++#else ++# define machine_is_hicoarm9() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PNX4008 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PNX4008 ++# endif ++# define machine_is_pnx4008() (machine_arch_type == MACH_TYPE_PNX4008) ++#else ++# define machine_is_pnx4008() (0) ++#endif ++ ++#ifdef CONFIG_MACH_KWS6000 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_KWS6000 ++# endif ++# define machine_is_kws6000() (machine_arch_type == MACH_TYPE_KWS6000) ++#else ++# define machine_is_kws6000() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PORTUX920T ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PORTUX920T ++# endif ++# define machine_is_portux920t() (machine_arch_type == MACH_TYPE_PORTUX920T) ++#else ++# define machine_is_portux920t() (0) ++#endif ++ ++#ifdef CONFIG_MACH_EZ_X5 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_EZ_X5 ++# endif ++# define machine_is_ez_x5() (machine_arch_type == MACH_TYPE_EZ_X5) ++#else ++# define machine_is_ez_x5() (0) ++#endif ++ ++#ifdef CONFIG_MACH_OMAP_RUDOLPH ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_OMAP_RUDOLPH ++# endif ++# define machine_is_omap_rudolph() (machine_arch_type == MACH_TYPE_OMAP_RUDOLPH) ++#else ++# define machine_is_omap_rudolph() (0) ++#endif ++ ++#ifdef CONFIG_MACH_CPUAT91 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_CPUAT91 ++# endif ++# define machine_is_cpuat91() (machine_arch_type == MACH_TYPE_CPUAT91) ++#else ++# define machine_is_cpuat91() (0) ++#endif ++ ++#ifdef CONFIG_MACH_REA9200 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_REA9200 ++# endif ++# define machine_is_rea9200() (machine_arch_type == MACH_TYPE_REA9200) ++#else ++# define machine_is_rea9200() (0) ++#endif ++ ++#ifdef CONFIG_MACH_ACTS_PUNE_SA1110 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_ACTS_PUNE_SA1110 ++# endif ++# define machine_is_acts_pune_sa1110() (machine_arch_type == MACH_TYPE_ACTS_PUNE_SA1110) ++#else ++# define machine_is_acts_pune_sa1110() (0) ++#endif ++ ++#ifdef CONFIG_MACH_IXP425 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_IXP425 ++# endif ++# define machine_is_ixp425() (machine_arch_type == MACH_TYPE_IXP425) ++#else ++# define machine_is_ixp425() (0) ++#endif ++ ++#ifdef CONFIG_MACH_ARGONPLUSODYSSEY ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_ARGONPLUSODYSSEY ++# endif ++# define machine_is_i30030ads() (machine_arch_type == MACH_TYPE_ARGONPLUSODYSSEY) ++#else ++# define machine_is_i30030ads() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PERCH ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PERCH ++# endif ++# define machine_is_perch() (machine_arch_type == MACH_TYPE_PERCH) ++#else ++# define machine_is_perch() (0) ++#endif ++ ++#ifdef CONFIG_MACH_EIS05R1 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_EIS05R1 ++# endif ++# define machine_is_eis05r1() (machine_arch_type == MACH_TYPE_EIS05R1) ++#else ++# define machine_is_eis05r1() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PEPPERPAD ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PEPPERPAD ++# endif ++# define machine_is_pepperpad() (machine_arch_type == MACH_TYPE_PEPPERPAD) ++#else ++# define machine_is_pepperpad() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SB3010 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SB3010 ++# endif ++# define machine_is_sb3010() (machine_arch_type == MACH_TYPE_SB3010) ++#else ++# define machine_is_sb3010() (0) ++#endif ++ ++#ifdef CONFIG_MACH_RM9200 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_RM9200 ++# endif ++# define machine_is_rm9200() (machine_arch_type == MACH_TYPE_RM9200) ++#else ++# define machine_is_rm9200() (0) ++#endif ++ ++#ifdef CONFIG_MACH_DMA03 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_DMA03 ++# endif ++# define machine_is_dma03() (machine_arch_type == MACH_TYPE_DMA03) ++#else ++# define machine_is_dma03() (0) ++#endif ++ ++#ifdef CONFIG_MACH_ROAD_S101 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_ROAD_S101 ++# endif ++# define machine_is_road_s101() (machine_arch_type == MACH_TYPE_ROAD_S101) ++#else ++# define machine_is_road_s101() (0) ++#endif ++ ++#ifdef CONFIG_MACH_IQ_NEXTGEN_A ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_A ++# endif ++# define machine_is_iq_nextgen_a() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_A) ++#else ++# define machine_is_iq_nextgen_a() (0) ++#endif ++ ++#ifdef CONFIG_MACH_IQ_NEXTGEN_B ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_B ++# endif ++# define machine_is_iq_nextgen_b() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_B) ++#else ++# define machine_is_iq_nextgen_b() (0) ++#endif ++ ++#ifdef CONFIG_MACH_IQ_NEXTGEN_C ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_C ++# endif ++# define machine_is_iq_nextgen_c() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_C) ++#else ++# define machine_is_iq_nextgen_c() (0) ++#endif ++ ++#ifdef CONFIG_MACH_IQ_NEXTGEN_D ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_D ++# endif ++# define machine_is_iq_nextgen_d() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_D) ++#else ++# define machine_is_iq_nextgen_d() (0) ++#endif ++ ++#ifdef CONFIG_MACH_IQ_NEXTGEN_E ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_E ++# endif ++# define machine_is_iq_nextgen_e() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_E) ++#else ++# define machine_is_iq_nextgen_e() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MALLOW_AT91 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MALLOW_AT91 ++# endif ++# define machine_is_mallow_at91() (machine_arch_type == MACH_TYPE_MALLOW_AT91) ++#else ++# define machine_is_mallow_at91() (0) ++#endif ++ ++#ifdef CONFIG_MACH_CYBERTRACKER_I ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_CYBERTRACKER_I ++# endif ++# define machine_is_cybertracker_i() (machine_arch_type == MACH_TYPE_CYBERTRACKER_I) ++#else ++# define machine_is_cybertracker_i() (0) ++#endif ++ ++#ifdef CONFIG_MACH_GESBC931X ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_GESBC931X ++# endif ++# define machine_is_gesbc931x() (machine_arch_type == MACH_TYPE_GESBC931X) ++#else ++# define machine_is_gesbc931x() (0) ++#endif ++ ++#ifdef CONFIG_MACH_CENTIPAD ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_CENTIPAD ++# endif ++# define machine_is_centipad() (machine_arch_type == MACH_TYPE_CENTIPAD) ++#else ++# define machine_is_centipad() (0) ++#endif ++ ++#ifdef CONFIG_MACH_ARMSOC ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_ARMSOC ++# endif ++# define machine_is_armsoc() (machine_arch_type == MACH_TYPE_ARMSOC) ++#else ++# define machine_is_armsoc() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SE4200 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SE4200 ++# endif ++# define machine_is_se4200() (machine_arch_type == MACH_TYPE_SE4200) ++#else ++# define machine_is_se4200() (0) ++#endif ++ ++#ifdef CONFIG_MACH_EMS197A ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_EMS197A ++# endif ++# define machine_is_ems197a() (machine_arch_type == MACH_TYPE_EMS197A) ++#else ++# define machine_is_ems197a() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MICRO9 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MICRO9 ++# endif ++# define machine_is_micro9() (machine_arch_type == MACH_TYPE_MICRO9) ++#else ++# define machine_is_micro9() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MICRO9L ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MICRO9L ++# endif ++# define machine_is_micro9l() (machine_arch_type == MACH_TYPE_MICRO9L) ++#else ++# define machine_is_micro9l() (0) ++#endif ++ ++#ifdef CONFIG_MACH_UC5471DSP ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_UC5471DSP ++# endif ++# define machine_is_uc5471dsp() (machine_arch_type == MACH_TYPE_UC5471DSP) ++#else ++# define machine_is_uc5471dsp() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SJ5471ENG ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SJ5471ENG ++# endif ++# define machine_is_sj5471eng() (machine_arch_type == MACH_TYPE_SJ5471ENG) ++#else ++# define machine_is_sj5471eng() (0) ++#endif ++ ++#ifdef CONFIG_MACH_CMPXA26X ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_CMPXA26X ++# endif ++# define machine_is_none() (machine_arch_type == MACH_TYPE_CMPXA26X) ++#else ++# define machine_is_none() (0) ++#endif ++ ++#ifdef CONFIG_MACH_NC ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_NC ++# endif ++# define machine_is_nc1() (machine_arch_type == MACH_TYPE_NC) ++#else ++# define machine_is_nc1() (0) ++#endif ++ ++#ifdef CONFIG_MACH_OMAP_PALMTE ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_OMAP_PALMTE ++# endif ++# define machine_is_omap_palmte() (machine_arch_type == MACH_TYPE_OMAP_PALMTE) ++#else ++# define machine_is_omap_palmte() (0) ++#endif ++ ++#ifdef CONFIG_MACH_AJAX52X ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_AJAX52X ++# endif ++# define machine_is_ajax52x() (machine_arch_type == MACH_TYPE_AJAX52X) ++#else ++# define machine_is_ajax52x() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SIRIUSTAR ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SIRIUSTAR ++# endif ++# define machine_is_siriustar() (machine_arch_type == MACH_TYPE_SIRIUSTAR) ++#else ++# define machine_is_siriustar() (0) ++#endif ++ ++#ifdef CONFIG_MACH_IODATA_HDLG ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_IODATA_HDLG ++# endif ++# define machine_is_iodata_hdlg() (machine_arch_type == MACH_TYPE_IODATA_HDLG) ++#else ++# define machine_is_iodata_hdlg() (0) ++#endif ++ ++#ifdef CONFIG_MACH_AT91RM9200UTL ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_AT91RM9200UTL ++# endif ++# define machine_is_at91rm9200utl() (machine_arch_type == MACH_TYPE_AT91RM9200UTL) ++#else ++# define machine_is_at91rm9200utl() (0) ++#endif ++ ++#ifdef CONFIG_MACH_BIOSAFE ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_BIOSAFE ++# endif ++# define machine_is_biosafe() (machine_arch_type == MACH_TYPE_BIOSAFE) ++#else ++# define machine_is_biosafe() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MP1000 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MP1000 ++# endif ++# define machine_is_mp1000() (machine_arch_type == MACH_TYPE_MP1000) ++#else ++# define machine_is_mp1000() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PARSY ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PARSY ++# endif ++# define machine_is_parsy() (machine_arch_type == MACH_TYPE_PARSY) ++#else ++# define machine_is_parsy() (0) ++#endif ++ ++#ifdef CONFIG_MACH_CCXP ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_CCXP ++# endif ++# define machine_is_ccxp270() (machine_arch_type == MACH_TYPE_CCXP) ++#else ++# define machine_is_ccxp270() (0) ++#endif ++ ++#ifdef CONFIG_MACH_OMAP_GSAMPLE ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_OMAP_GSAMPLE ++# endif ++# define machine_is_omap_gsample() (machine_arch_type == MACH_TYPE_OMAP_GSAMPLE) ++#else ++# define machine_is_omap_gsample() (0) ++#endif ++ ++#ifdef CONFIG_MACH_REALVIEW_EB ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_REALVIEW_EB ++# endif ++# define machine_is_realview_eb() (machine_arch_type == MACH_TYPE_REALVIEW_EB) ++#else ++# define machine_is_realview_eb() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SAMOA ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SAMOA ++# endif ++# define machine_is_samoa() (machine_arch_type == MACH_TYPE_SAMOA) ++#else ++# define machine_is_samoa() (0) ++#endif ++ ++#ifdef CONFIG_MACH_T3XSCALE ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_T3XSCALE ++# endif ++# define machine_is_t3xscale() (machine_arch_type == MACH_TYPE_T3XSCALE) ++#else ++# define machine_is_t3xscale() (0) ++#endif ++ ++#ifdef CONFIG_MACH_I878 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_I878 ++# endif ++# define machine_is_i878() (machine_arch_type == MACH_TYPE_I878) ++#else ++# define machine_is_i878() (0) ++#endif ++ ++#ifdef CONFIG_MACH_BORZOI ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_BORZOI ++# endif ++# define machine_is_borzoi() (machine_arch_type == MACH_TYPE_BORZOI) ++#else ++# define machine_is_borzoi() (0) ++#endif ++ ++#ifdef CONFIG_MACH_GECKO ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_GECKO ++# endif ++# define machine_is_gecko() (machine_arch_type == MACH_TYPE_GECKO) ++#else ++# define machine_is_gecko() (0) ++#endif ++ ++#ifdef CONFIG_MACH_DS101 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_DS101 ++# endif ++# define machine_is_ds101() (machine_arch_type == MACH_TYPE_DS101) ++#else ++# define machine_is_ds101() (0) ++#endif ++ ++#ifdef CONFIG_MACH_OMAP_PALMTT2 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_OMAP_PALMTT2 ++# endif ++# define machine_is_omap_palmtt2() (machine_arch_type == MACH_TYPE_OMAP_PALMTT2) ++#else ++# define machine_is_omap_palmtt2() (0) ++#endif ++ ++#ifdef CONFIG_MACH_XSCALE_PALMLD ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_XSCALE_PALMLD ++# endif ++# define machine_is_xscale_palmld() (machine_arch_type == MACH_TYPE_XSCALE_PALMLD) ++#else ++# define machine_is_xscale_palmld() (0) ++#endif ++ ++#ifdef CONFIG_MACH_CC9C ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_CC9C ++# endif ++# define machine_is_cc9c() (machine_arch_type == MACH_TYPE_CC9C) ++#else ++# define machine_is_cc9c() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SBC1670 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SBC1670 ++# endif ++# define machine_is_sbc1670() (machine_arch_type == MACH_TYPE_SBC1670) ++#else ++# define machine_is_sbc1670() (0) ++#endif ++ ++#ifdef CONFIG_MACH_IXDP28X5 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_IXDP28X5 ++# endif ++# define machine_is_ixdp28x5() (machine_arch_type == MACH_TYPE_IXDP28X5) ++#else ++# define machine_is_ixdp28x5() (0) ++#endif ++ ++#ifdef CONFIG_MACH_OMAP_PALMTT ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_OMAP_PALMTT ++# endif ++# define machine_is_omap_palmtt() (machine_arch_type == MACH_TYPE_OMAP_PALMTT) ++#else ++# define machine_is_omap_palmtt() (0) ++#endif ++ ++#ifdef CONFIG_MACH_ML696K ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_ML696K ++# endif ++# define machine_is_ml696k() (machine_arch_type == MACH_TYPE_ML696K) ++#else ++# define machine_is_ml696k() (0) ++#endif ++ ++#ifdef CONFIG_MACH_ARCOM_ZEUS ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_ARCOM_ZEUS ++# endif ++# define machine_is_arcom_zeus() (machine_arch_type == MACH_TYPE_ARCOM_ZEUS) ++#else ++# define machine_is_arcom_zeus() (0) ++#endif ++ ++#ifdef CONFIG_MACH_OSIRIS ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_OSIRIS ++# endif ++# define machine_is_osiris() (machine_arch_type == MACH_TYPE_OSIRIS) ++#else ++# define machine_is_osiris() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MAESTRO ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MAESTRO ++# endif ++# define machine_is_maestro() (machine_arch_type == MACH_TYPE_MAESTRO) ++#else ++# define machine_is_maestro() (0) ++#endif ++ ++#ifdef CONFIG_MACH_TUNGE2 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_TUNGE2 ++# endif ++# define machine_is_tunge2() (machine_arch_type == MACH_TYPE_TUNGE2) ++#else ++# define machine_is_tunge2() (0) ++#endif ++ ++#ifdef CONFIG_MACH_IXBBM ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_IXBBM ++# endif ++# define machine_is_ixbbm() (machine_arch_type == MACH_TYPE_IXBBM) ++#else ++# define machine_is_ixbbm() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MX27 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MX27 ++# endif ++# define machine_is_mx27ads() (machine_arch_type == MACH_TYPE_MX27) ++#else ++# define machine_is_mx27ads() (0) ++#endif ++ ++#ifdef CONFIG_MACH_AX8004 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_AX8004 ++# endif ++# define machine_is_ax8004() (machine_arch_type == MACH_TYPE_AX8004) ++#else ++# define machine_is_ax8004() (0) ++#endif ++ ++#ifdef CONFIG_MACH_AT91SAM9261EK ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_AT91SAM9261EK ++# endif ++# define machine_is_at91sam9261ek() (machine_arch_type == MACH_TYPE_AT91SAM9261EK) ++#else ++# define machine_is_at91sam9261ek() (0) ++#endif ++ ++#ifdef CONFIG_MACH_LOFT ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_LOFT ++# endif ++# define machine_is_loft() (machine_arch_type == MACH_TYPE_LOFT) ++#else ++# define machine_is_loft() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MAGPIE ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MAGPIE ++# endif ++# define machine_is_magpie() (machine_arch_type == MACH_TYPE_MAGPIE) ++#else ++# define machine_is_magpie() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MX21 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MX21 ++# endif ++# define machine_is_mx21ads() (machine_arch_type == MACH_TYPE_MX21) ++#else ++# define machine_is_mx21ads() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MB87M3400 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MB87M3400 ++# endif ++# define machine_is_mb87m3400() (machine_arch_type == MACH_TYPE_MB87M3400) ++#else ++# define machine_is_mb87m3400() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MGUARD_DELTA ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MGUARD_DELTA ++# endif ++# define machine_is_mguard_delta() (machine_arch_type == MACH_TYPE_MGUARD_DELTA) ++#else ++# define machine_is_mguard_delta() (0) ++#endif ++ ++#ifdef CONFIG_MACH_DAVINCI_DVDP ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_DAVINCI_DVDP ++# endif ++# define machine_is_davinci_dvdp() (machine_arch_type == MACH_TYPE_DAVINCI_DVDP) ++#else ++# define machine_is_davinci_dvdp() (0) ++#endif ++ ++#ifdef CONFIG_MACH_HTCUNIVERSAL ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_HTCUNIVERSAL ++# endif ++# define machine_is_htcuniversal() (machine_arch_type == MACH_TYPE_HTCUNIVERSAL) ++#else ++# define machine_is_htcuniversal() (0) ++#endif ++ ++#ifdef CONFIG_MACH_TPAD ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_TPAD ++# endif ++# define machine_is_tpad() (machine_arch_type == MACH_TYPE_TPAD) ++#else ++# define machine_is_tpad() (0) ++#endif ++ ++#ifdef CONFIG_MACH_ROVERP3 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_ROVERP3 ++# endif ++# define machine_is_roverp3() (machine_arch_type == MACH_TYPE_ROVERP3) ++#else ++# define machine_is_roverp3() (0) ++#endif ++ ++#ifdef CONFIG_MACH_JORNADA928 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_JORNADA928 ++# endif ++# define machine_is_jornada928() (machine_arch_type == MACH_TYPE_JORNADA928) ++#else ++# define machine_is_jornada928() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MV88FXX81 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MV88FXX81 ++# endif ++# define machine_is_mv88fxx81() (machine_arch_type == MACH_TYPE_MV88FXX81) ++#else ++# define machine_is_mv88fxx81() (0) ++#endif ++ ++#ifdef CONFIG_MACH_STMP36XX ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_STMP36XX ++# endif ++# define machine_is_stmp36xx() (machine_arch_type == MACH_TYPE_STMP36XX) ++#else ++# define machine_is_stmp36xx() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SXNI79524 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SXNI79524 ++# endif ++# define machine_is_sxni79524() (machine_arch_type == MACH_TYPE_SXNI79524) ++#else ++# define machine_is_sxni79524() (0) ++#endif ++ ++#ifdef CONFIG_MACH_AMS_DELTA ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_AMS_DELTA ++# endif ++# define machine_is_ams_delta() (machine_arch_type == MACH_TYPE_AMS_DELTA) ++#else ++# define machine_is_ams_delta() (0) ++#endif ++ ++#ifdef CONFIG_MACH_URANIUM ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_URANIUM ++# endif ++# define machine_is_uranium() (machine_arch_type == MACH_TYPE_URANIUM) ++#else ++# define machine_is_uranium() (0) ++#endif ++ ++#ifdef CONFIG_MACH_UCON ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_UCON ++# endif ++# define machine_is_ucon() (machine_arch_type == MACH_TYPE_UCON) ++#else ++# define machine_is_ucon() (0) ++#endif ++ ++#ifdef CONFIG_MACH_NAS100D ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_NAS100D ++# endif ++# define machine_is_nas100d() (machine_arch_type == MACH_TYPE_NAS100D) ++#else ++# define machine_is_nas100d() (0) ++#endif ++ ++#ifdef CONFIG_MACH_L083_1000 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_L083_1000 ++# endif ++# define machine_is_l083() (machine_arch_type == MACH_TYPE_L083_1000) ++#else ++# define machine_is_l083() (0) ++#endif ++ ++#ifdef CONFIG_MACH_EZX ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_EZX ++# endif ++# define machine_is_ezx() (machine_arch_type == MACH_TYPE_EZX) ++#else ++# define machine_is_ezx() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PNX5220 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PNX5220 ++# endif ++# define machine_is_pnx5220() (machine_arch_type == MACH_TYPE_PNX5220) ++#else ++# define machine_is_pnx5220() (0) ++#endif ++ ++#ifdef CONFIG_MACH_BUTTE ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_BUTTE ++# endif ++# define machine_is_butte() (machine_arch_type == MACH_TYPE_BUTTE) ++#else ++# define machine_is_butte() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SRM2 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SRM2 ++# endif ++# define machine_is_srm2() (machine_arch_type == MACH_TYPE_SRM2) ++#else ++# define machine_is_srm2() (0) ++#endif ++ ++#ifdef CONFIG_MACH_DSBR ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_DSBR ++# endif ++# define machine_is_dsbr() (machine_arch_type == MACH_TYPE_DSBR) ++#else ++# define machine_is_dsbr() (0) ++#endif ++ ++#ifdef CONFIG_MACH_CRYSTALBALL ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_CRYSTALBALL ++# endif ++# define machine_is_crystalball() (machine_arch_type == MACH_TYPE_CRYSTALBALL) ++#else ++# define machine_is_crystalball() (0) ++#endif ++ ++#ifdef CONFIG_MACH_TINYPXA27X ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_TINYPXA27X ++# endif ++# define machine_is_tinypxa27x() (machine_arch_type == MACH_TYPE_TINYPXA27X) ++#else ++# define machine_is_tinypxa27x() (0) ++#endif ++ ++#ifdef CONFIG_MACH_HERBIE ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_HERBIE ++# endif ++# define machine_is_herbie() (machine_arch_type == MACH_TYPE_HERBIE) ++#else ++# define machine_is_herbie() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MAGICIAN ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MAGICIAN ++# endif ++# define machine_is_magician() (machine_arch_type == MACH_TYPE_MAGICIAN) ++#else ++# define machine_is_magician() (0) ++#endif ++ ++#ifdef CONFIG_MACH_CM4002 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_CM4002 ++# endif ++# define machine_is_cm4002() (machine_arch_type == MACH_TYPE_CM4002) ++#else ++# define machine_is_cm4002() (0) ++#endif ++ ++#ifdef CONFIG_MACH_B4 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_B4 ++# endif ++# define machine_is_b4() (machine_arch_type == MACH_TYPE_B4) ++#else ++# define machine_is_b4() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MAUI ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MAUI ++# endif ++# define machine_is_maui() (machine_arch_type == MACH_TYPE_MAUI) ++#else ++# define machine_is_maui() (0) ++#endif ++ ++#ifdef CONFIG_MACH_CYBERTRACKER_G ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_CYBERTRACKER_G ++# endif ++# define machine_is_cybertracker_g() (machine_arch_type == MACH_TYPE_CYBERTRACKER_G) ++#else ++# define machine_is_cybertracker_g() (0) ++#endif ++ ++#ifdef CONFIG_MACH_NXDKN ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_NXDKN ++# endif ++# define machine_is_nxdkn() (machine_arch_type == MACH_TYPE_NXDKN) ++#else ++# define machine_is_nxdkn() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MIO8390 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MIO8390 ++# endif ++# define machine_is_mio8390() (machine_arch_type == MACH_TYPE_MIO8390) ++#else ++# define machine_is_mio8390() (0) ++#endif ++ ++#ifdef CONFIG_MACH_OMI_BOARD ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_OMI_BOARD ++# endif ++# define machine_is_omi_board() (machine_arch_type == MACH_TYPE_OMI_BOARD) ++#else ++# define machine_is_omi_board() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MX21CIV ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MX21CIV ++# endif ++# define machine_is_mx21civ() (machine_arch_type == MACH_TYPE_MX21CIV) ++#else ++# define machine_is_mx21civ() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MAHI_CDAC ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MAHI_CDAC ++# endif ++# define machine_is_mahi_cdac() (machine_arch_type == MACH_TYPE_MAHI_CDAC) ++#else ++# define machine_is_mahi_cdac() (0) ++#endif ++ ++#ifdef CONFIG_MACH_XSCALE_PALMTX ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_XSCALE_PALMTX ++# endif ++# define machine_is_xscale_palmtx() (machine_arch_type == MACH_TYPE_XSCALE_PALMTX) ++#else ++# define machine_is_xscale_palmtx() (0) ++#endif ++ ++#ifdef CONFIG_MACH_S3C2413 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_S3C2413 ++# endif ++# define machine_is_s3c2413() (machine_arch_type == MACH_TYPE_S3C2413) ++#else ++# define machine_is_s3c2413() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SAMSYS_EP0 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SAMSYS_EP0 ++# endif ++# define machine_is_samsys_ep0() (machine_arch_type == MACH_TYPE_SAMSYS_EP0) ++#else ++# define machine_is_samsys_ep0() (0) ++#endif ++ ++#ifdef CONFIG_MACH_WG302V1 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_WG302V1 ++# endif ++# define machine_is_wg302v1() (machine_arch_type == MACH_TYPE_WG302V1) ++#else ++# define machine_is_wg302v1() (0) ++#endif ++ ++#ifdef CONFIG_MACH_WG302V2 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_WG302V2 ++# endif ++# define machine_is_wg302v2() (machine_arch_type == MACH_TYPE_WG302V2) ++#else ++# define machine_is_wg302v2() (0) ++#endif ++ ++#ifdef CONFIG_MACH_EB42X ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_EB42X ++# endif ++# define machine_is_eb42x() (machine_arch_type == MACH_TYPE_EB42X) ++#else ++# define machine_is_eb42x() (0) ++#endif ++ ++#ifdef CONFIG_MACH_IQ331ES ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_IQ331ES ++# endif ++# define machine_is_iq331es() (machine_arch_type == MACH_TYPE_IQ331ES) ++#else ++# define machine_is_iq331es() (0) ++#endif ++ ++#ifdef CONFIG_MACH_COSYDSP ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_COSYDSP ++# endif ++# define machine_is_cosydsp() (machine_arch_type == MACH_TYPE_COSYDSP) ++#else ++# define machine_is_cosydsp() (0) ++#endif ++ ++#ifdef CONFIG_MACH_UPLAT7D ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_UPLAT7D ++# endif ++# define machine_is_uplat7d_proto() (machine_arch_type == MACH_TYPE_UPLAT7D) ++#else ++# define machine_is_uplat7d_proto() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PTDAVINCI ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PTDAVINCI ++# endif ++# define machine_is_ptdavinci() (machine_arch_type == MACH_TYPE_PTDAVINCI) ++#else ++# define machine_is_ptdavinci() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MBUS ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MBUS ++# endif ++# define machine_is_mbus() (machine_arch_type == MACH_TYPE_MBUS) ++#else ++# define machine_is_mbus() (0) ++#endif ++ ++#ifdef CONFIG_MACH_NADIA2VB ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_NADIA2VB ++# endif ++# define machine_is_nadia2vb() (machine_arch_type == MACH_TYPE_NADIA2VB) ++#else ++# define machine_is_nadia2vb() (0) ++#endif ++ ++#ifdef CONFIG_MACH_R1000 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_R1000 ++# endif ++# define machine_is_r1000() (machine_arch_type == MACH_TYPE_R1000) ++#else ++# define machine_is_r1000() (0) ++#endif ++ ++#ifdef CONFIG_MACH_HW90250 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_HW90250 ++# endif ++# define machine_is_hw90250() (machine_arch_type == MACH_TYPE_HW90250) ++#else ++# define machine_is_hw90250() (0) ++#endif ++ ++#ifdef CONFIG_MACH_OMAP_2430SDP ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_OMAP_2430SDP ++# endif ++# define machine_is_omap_2430sdp() (machine_arch_type == MACH_TYPE_OMAP_2430SDP) ++#else ++# define machine_is_omap_2430sdp() (0) ++#endif ++ ++#ifdef CONFIG_MACH_DAVINCI_EVM ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_DAVINCI_EVM ++# endif ++# define machine_is_davinci_evm() (machine_arch_type == MACH_TYPE_DAVINCI_EVM) ++#else ++# define machine_is_davinci_evm() (0) ++#endif ++ ++#ifdef CONFIG_MACH_OMAP_TORNADO ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_OMAP_TORNADO ++# endif ++# define machine_is_omap_tornado() (machine_arch_type == MACH_TYPE_OMAP_TORNADO) ++#else ++# define machine_is_omap_tornado() (0) ++#endif ++ ++#ifdef CONFIG_MACH_OLOCREEK ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_OLOCREEK ++# endif ++# define machine_is_olocreek() (machine_arch_type == MACH_TYPE_OLOCREEK) ++#else ++# define machine_is_olocreek() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PALMZ72 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PALMZ72 ++# endif ++# define machine_is_palmz72() (machine_arch_type == MACH_TYPE_PALMZ72) ++#else ++# define machine_is_palmz72() (0) ++#endif ++ ++#ifdef CONFIG_MACH_NXDB500 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_NXDB500 ++# endif ++# define machine_is_nxdb500() (machine_arch_type == MACH_TYPE_NXDB500) ++#else ++# define machine_is_nxdb500() (0) ++#endif ++ ++#ifdef CONFIG_MACH_APF9328 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_APF9328 ++# endif ++# define machine_is_apf9328() (machine_arch_type == MACH_TYPE_APF9328) ++#else ++# define machine_is_apf9328() (0) ++#endif ++ ++#ifdef CONFIG_MACH_OMAP_WIPOQ ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_OMAP_WIPOQ ++# endif ++# define machine_is_omap_wipoq() (machine_arch_type == MACH_TYPE_OMAP_WIPOQ) ++#else ++# define machine_is_omap_wipoq() (0) ++#endif ++ ++#ifdef CONFIG_MACH_OMAP_TWIP ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_OMAP_TWIP ++# endif ++# define machine_is_omap_twip() (machine_arch_type == MACH_TYPE_OMAP_TWIP) ++#else ++# define machine_is_omap_twip() (0) ++#endif ++ ++#ifdef CONFIG_MACH_XSCALE_PALMTREO650 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_XSCALE_PALMTREO650 ++# endif ++# define machine_is_xscale_treo650() (machine_arch_type == MACH_TYPE_XSCALE_PALMTREO650) ++#else ++# define machine_is_xscale_treo650() (0) ++#endif ++ ++#ifdef CONFIG_MACH_ACUMEN ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_ACUMEN ++# endif ++# define machine_is_acumen() (machine_arch_type == MACH_TYPE_ACUMEN) ++#else ++# define machine_is_acumen() (0) ++#endif ++ ++#ifdef CONFIG_MACH_XP100 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_XP100 ++# endif ++# define machine_is_xp100() (machine_arch_type == MACH_TYPE_XP100) ++#else ++# define machine_is_xp100() (0) ++#endif ++ ++#ifdef CONFIG_MACH_FS2410 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_FS2410 ++# endif ++# define machine_is_fs2410() (machine_arch_type == MACH_TYPE_FS2410) ++#else ++# define machine_is_fs2410() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PXA270_CERF ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PXA270_CERF ++# endif ++# define machine_is_pxa270_cerf() (machine_arch_type == MACH_TYPE_PXA270_CERF) ++#else ++# define machine_is_pxa270_cerf() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SQ2FTLPALM ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SQ2FTLPALM ++# endif ++# define machine_is_sq2ftlpalm() (machine_arch_type == MACH_TYPE_SQ2FTLPALM) ++#else ++# define machine_is_sq2ftlpalm() (0) ++#endif ++ ++#ifdef CONFIG_MACH_BSEMSERVER ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_BSEMSERVER ++# endif ++# define machine_is_bsemserver() (machine_arch_type == MACH_TYPE_BSEMSERVER) ++#else ++# define machine_is_bsemserver() (0) ++#endif ++ ++#ifdef CONFIG_MACH_NETCLIENT ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_NETCLIENT ++# endif ++# define machine_is_netclient() (machine_arch_type == MACH_TYPE_NETCLIENT) ++#else ++# define machine_is_netclient() (0) ++#endif ++ ++#ifdef CONFIG_MACH_XSCALE_PALMTT5 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_XSCALE_PALMTT5 ++# endif ++# define machine_is_xscale_palmtt5() (machine_arch_type == MACH_TYPE_XSCALE_PALMTT5) ++#else ++# define machine_is_xscale_palmtt5() (0) ++#endif ++ ++#ifdef CONFIG_MACH_OMAP_PALMTC ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_OMAP_PALMTC ++# endif ++# define machine_is_xscale_palmtc() (machine_arch_type == MACH_TYPE_OMAP_PALMTC) ++#else ++# define machine_is_xscale_palmtc() (0) ++#endif ++ ++#ifdef CONFIG_MACH_OMAP_APOLLON ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_OMAP_APOLLON ++# endif ++# define machine_is_omap_apollon() (machine_arch_type == MACH_TYPE_OMAP_APOLLON) ++#else ++# define machine_is_omap_apollon() (0) ++#endif ++ ++#ifdef CONFIG_MACH_ARGONLVEVB ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_ARGONLVEVB ++# endif ++# define machine_is_mxc30030evb() (machine_arch_type == MACH_TYPE_ARGONLVEVB) ++#else ++# define machine_is_mxc30030evb() (0) ++#endif ++ ++#ifdef CONFIG_MACH_REA_2D ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_REA_2D ++# endif ++# define machine_is_rea_2d() (machine_arch_type == MACH_TYPE_REA_2D) ++#else ++# define machine_is_rea_2d() (0) ++#endif ++ ++#ifdef CONFIG_MACH_TI3E524 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_TI3E524 ++# endif ++# define machine_is_eti3e524() (machine_arch_type == MACH_TYPE_TI3E524) ++#else ++# define machine_is_eti3e524() (0) ++#endif ++ ++#ifdef CONFIG_MACH_ATEB9200 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_ATEB9200 ++# endif ++# define machine_is_ateb9200() (machine_arch_type == MACH_TYPE_ATEB9200) ++#else ++# define machine_is_ateb9200() (0) ++#endif ++ ++#ifdef CONFIG_MACH_AUCKLAND ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_AUCKLAND ++# endif ++# define machine_is_auckland() (machine_arch_type == MACH_TYPE_AUCKLAND) ++#else ++# define machine_is_auckland() (0) ++#endif ++ ++#ifdef CONFIG_MACH_AK3320M ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_AK3320M ++# endif ++# define machine_is_ak3220m() (machine_arch_type == MACH_TYPE_AK3320M) ++#else ++# define machine_is_ak3220m() (0) ++#endif ++ ++#ifdef CONFIG_MACH_DURAMAX ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_DURAMAX ++# endif ++# define machine_is_duramax() (machine_arch_type == MACH_TYPE_DURAMAX) ++#else ++# define machine_is_duramax() (0) ++#endif ++ ++#ifdef CONFIG_MACH_N35 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_N35 ++# endif ++# define machine_is_n35() (machine_arch_type == MACH_TYPE_N35) ++#else ++# define machine_is_n35() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PRONGHORN ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PRONGHORN ++# endif ++# define machine_is_pronghorn() (machine_arch_type == MACH_TYPE_PRONGHORN) ++#else ++# define machine_is_pronghorn() (0) ++#endif ++ ++#ifdef CONFIG_MACH_FUNDY ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_FUNDY ++# endif ++# define machine_is_fundy() (machine_arch_type == MACH_TYPE_FUNDY) ++#else ++# define machine_is_fundy() (0) ++#endif ++ ++#ifdef CONFIG_MACH_LOGICPD_PXA270 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_LOGICPD_PXA270 ++# endif ++# define machine_is_logicpd_pxa270() (machine_arch_type == MACH_TYPE_LOGICPD_PXA270) ++#else ++# define machine_is_logicpd_pxa270() (0) ++#endif ++ ++#ifdef CONFIG_MACH_CPU777 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_CPU777 ++# endif ++# define machine_is_cpu777() (machine_arch_type == MACH_TYPE_CPU777) ++#else ++# define machine_is_cpu777() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SIMICON9201 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SIMICON9201 ++# endif ++# define machine_is_simicon9201() (machine_arch_type == MACH_TYPE_SIMICON9201) ++#else ++# define machine_is_simicon9201() (0) ++#endif ++ ++#ifdef CONFIG_MACH_LEAP2_HPM ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_LEAP2_HPM ++# endif ++# define machine_is_leap2_hpm() (machine_arch_type == MACH_TYPE_LEAP2_HPM) ++#else ++# define machine_is_leap2_hpm() (0) ++#endif ++ ++#ifdef CONFIG_MACH_CM922TXA10 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_CM922TXA10 ++# endif ++# define machine_is_cm922txa10() (machine_arch_type == MACH_TYPE_CM922TXA10) ++#else ++# define machine_is_cm922txa10() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PXA ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PXA ++# endif ++# define machine_is_sandgate() (machine_arch_type == MACH_TYPE_PXA) ++#else ++# define machine_is_sandgate() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SANDGATE2 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SANDGATE2 ++# endif ++# define machine_is_sandgate2() (machine_arch_type == MACH_TYPE_SANDGATE2) ++#else ++# define machine_is_sandgate2() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SANDGATE2G ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SANDGATE2G ++# endif ++# define machine_is_sandgate2g() (machine_arch_type == MACH_TYPE_SANDGATE2G) ++#else ++# define machine_is_sandgate2g() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SANDGATE2P ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SANDGATE2P ++# endif ++# define machine_is_sandgate2p() (machine_arch_type == MACH_TYPE_SANDGATE2P) ++#else ++# define machine_is_sandgate2p() (0) ++#endif ++ ++#ifdef CONFIG_MACH_FRED_JACK ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_FRED_JACK ++# endif ++# define machine_is_fred_jack() (machine_arch_type == MACH_TYPE_FRED_JACK) ++#else ++# define machine_is_fred_jack() (0) ++#endif ++ ++#ifdef CONFIG_MACH_TTG_COLOR1 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_TTG_COLOR1 ++# endif ++# define machine_is_ttg_color1() (machine_arch_type == MACH_TYPE_TTG_COLOR1) ++#else ++# define machine_is_ttg_color1() (0) ++#endif ++ ++#ifdef CONFIG_MACH_NXEB500HMI ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_NXEB500HMI ++# endif ++# define machine_is_nxeb500hmi() (machine_arch_type == MACH_TYPE_NXEB500HMI) ++#else ++# define machine_is_nxeb500hmi() (0) ++#endif ++ ++#ifdef CONFIG_MACH_NETDCU8 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_NETDCU8 ++# endif ++# define machine_is_netdcu8() (machine_arch_type == MACH_TYPE_NETDCU8) ++#else ++# define machine_is_netdcu8() (0) ++#endif ++ ++#ifdef CONFIG_MACH_ML675050_CPU_BOA ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_ML675050_CPU_BOA ++# endif ++# define machine_is_ml675050_cpu_boa() (machine_arch_type == MACH_TYPE_ML675050_CPU_BOA) ++#else ++# define machine_is_ml675050_cpu_boa() (0) ++#endif ++ ++#ifdef CONFIG_MACH_NG_FVX538 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_NG_FVX538 ++# endif ++# define machine_is_ng_fvx538() (machine_arch_type == MACH_TYPE_NG_FVX538) ++#else ++# define machine_is_ng_fvx538() (0) ++#endif ++ ++#ifdef CONFIG_MACH_NG_FVS338 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_NG_FVS338 ++# endif ++# define machine_is_ng_fvs338() (machine_arch_type == MACH_TYPE_NG_FVS338) ++#else ++# define machine_is_ng_fvs338() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PNX4103 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PNX4103 ++# endif ++# define machine_is_pnx4103() (machine_arch_type == MACH_TYPE_PNX4103) ++#else ++# define machine_is_pnx4103() (0) ++#endif ++ ++#ifdef CONFIG_MACH_HESDB ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_HESDB ++# endif ++# define machine_is_hesdb() (machine_arch_type == MACH_TYPE_HESDB) ++#else ++# define machine_is_hesdb() (0) ++#endif ++ ++#ifdef CONFIG_MACH_XSILO ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_XSILO ++# endif ++# define machine_is_xsilo() (machine_arch_type == MACH_TYPE_XSILO) ++#else ++# define machine_is_xsilo() (0) ++#endif ++ ++#ifdef CONFIG_MACH_ESPRESSO ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_ESPRESSO ++# endif ++# define machine_is_espresso() (machine_arch_type == MACH_TYPE_ESPRESSO) ++#else ++# define machine_is_espresso() (0) ++#endif ++ ++#ifdef CONFIG_MACH_EMLC ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_EMLC ++# endif ++# define machine_is_emlc() (machine_arch_type == MACH_TYPE_EMLC) ++#else ++# define machine_is_emlc() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SISTERON ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SISTERON ++# endif ++# define machine_is_sisteron() (machine_arch_type == MACH_TYPE_SISTERON) ++#else ++# define machine_is_sisteron() (0) ++#endif ++ ++#ifdef CONFIG_MACH_RX1950 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_RX1950 ++# endif ++# define machine_is_rx1950() (machine_arch_type == MACH_TYPE_RX1950) ++#else ++# define machine_is_rx1950() (0) ++#endif ++ ++#ifdef CONFIG_MACH_TSC_VENUS ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_TSC_VENUS ++# endif ++# define machine_is_tsc_venus() (machine_arch_type == MACH_TYPE_TSC_VENUS) ++#else ++# define machine_is_tsc_venus() (0) ++#endif ++ ++#ifdef CONFIG_MACH_DS101J ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_DS101J ++# endif ++# define machine_is_ds101j() (machine_arch_type == MACH_TYPE_DS101J) ++#else ++# define machine_is_ds101j() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MXC30030ADS ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MXC30030ADS ++# endif ++# define machine_is_mxc30030ads() (machine_arch_type == MACH_TYPE_MXC30030ADS) ++#else ++# define machine_is_mxc30030ads() (0) ++#endif ++ ++#ifdef CONFIG_MACH_FUJITSU_WIMAXSOC ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_FUJITSU_WIMAXSOC ++# endif ++# define machine_is_fujitsu_wimaxsoc() (machine_arch_type == MACH_TYPE_FUJITSU_WIMAXSOC) ++#else ++# define machine_is_fujitsu_wimaxsoc() (0) ++#endif ++ ++#ifdef CONFIG_MACH_DUALPCMODEM ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_DUALPCMODEM ++# endif ++# define machine_is_dualpcmodem() (machine_arch_type == MACH_TYPE_DUALPCMODEM) ++#else ++# define machine_is_dualpcmodem() (0) ++#endif ++ ++#ifdef CONFIG_MACH_GESBC9312 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_GESBC9312 ++# endif ++# define machine_is_gesbc9312() (machine_arch_type == MACH_TYPE_GESBC9312) ++#else ++# define machine_is_gesbc9312() (0) ++#endif ++ ++#ifdef CONFIG_MACH_HTCAPACHE ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_HTCAPACHE ++# endif ++# define machine_is_htcapache() (machine_arch_type == MACH_TYPE_HTCAPACHE) ++#else ++# define machine_is_htcapache() (0) ++#endif ++ ++#ifdef CONFIG_MACH_IXDP435 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_IXDP435 ++# endif ++# define machine_is_ixdp435() (machine_arch_type == MACH_TYPE_IXDP435) ++#else ++# define machine_is_ixdp435() (0) ++#endif ++ ++#ifdef CONFIG_MACH_CATPROVT100 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_CATPROVT100 ++# endif ++# define machine_is_catprovt100() (machine_arch_type == MACH_TYPE_CATPROVT100) ++#else ++# define machine_is_catprovt100() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PICOTUX1XX ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PICOTUX1XX ++# endif ++# define machine_is_picotux1xx() (machine_arch_type == MACH_TYPE_PICOTUX1XX) ++#else ++# define machine_is_picotux1xx() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PICOTUX2XX ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PICOTUX2XX ++# endif ++# define machine_is_picotux2xx() (machine_arch_type == MACH_TYPE_PICOTUX2XX) ++#else ++# define machine_is_picotux2xx() (0) ++#endif ++ ++#ifdef CONFIG_MACH_DSMG600 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_DSMG600 ++# endif ++# define machine_is_dsmg600() (machine_arch_type == MACH_TYPE_DSMG600) ++#else ++# define machine_is_dsmg600() (0) ++#endif ++ ++#ifdef CONFIG_MACH_EMPC2 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_EMPC2 ++# endif ++# define machine_is_empc2() (machine_arch_type == MACH_TYPE_EMPC2) ++#else ++# define machine_is_empc2() (0) ++#endif ++ ++#ifdef CONFIG_MACH_VENTURA ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_VENTURA ++# endif ++# define machine_is_ventura() (machine_arch_type == MACH_TYPE_VENTURA) ++#else ++# define machine_is_ventura() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PHIDGET_SBC ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PHIDGET_SBC ++# endif ++# define machine_is_phidget_sbc() (machine_arch_type == MACH_TYPE_PHIDGET_SBC) ++#else ++# define machine_is_phidget_sbc() (0) ++#endif ++ ++#ifdef CONFIG_MACH_IJ3K ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_IJ3K ++# endif ++# define machine_is_ij3k() (machine_arch_type == MACH_TYPE_IJ3K) ++#else ++# define machine_is_ij3k() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PISGAH ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PISGAH ++# endif ++# define machine_is_pisgah() (machine_arch_type == MACH_TYPE_PISGAH) ++#else ++# define machine_is_pisgah() (0) ++#endif ++ ++#ifdef CONFIG_MACH_OMAP_FSAMPLE ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_OMAP_FSAMPLE ++# endif ++# define machine_is_omap_fsample() (machine_arch_type == MACH_TYPE_OMAP_FSAMPLE) ++#else ++# define machine_is_omap_fsample() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SG720 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SG720 ++# endif ++# define machine_is_sg720() (machine_arch_type == MACH_TYPE_SG720) ++#else ++# define machine_is_sg720() (0) ++#endif ++ ++#ifdef CONFIG_MACH_REDFOX ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_REDFOX ++# endif ++# define machine_is_redfox() (machine_arch_type == MACH_TYPE_REDFOX) ++#else ++# define machine_is_redfox() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MYSH_EP9315_1 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MYSH_EP9315_1 ++# endif ++# define machine_is_mysh_ep9315_1() (machine_arch_type == MACH_TYPE_MYSH_EP9315_1) ++#else ++# define machine_is_mysh_ep9315_1() (0) ++#endif ++ ++#ifdef CONFIG_MACH_TPF106 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_TPF106 ++# endif ++# define machine_is_tpf106() (machine_arch_type == MACH_TYPE_TPF106) ++#else ++# define machine_is_tpf106() (0) ++#endif ++ ++#ifdef CONFIG_MACH_AT91RM9200KG ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_AT91RM9200KG ++# endif ++# define machine_is_at91rm9200kg() (machine_arch_type == MACH_TYPE_AT91RM9200KG) ++#else ++# define machine_is_at91rm9200kg() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SLEDB ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SLEDB ++# endif ++# define machine_is_racemt2() (machine_arch_type == MACH_TYPE_SLEDB) ++#else ++# define machine_is_racemt2() (0) ++#endif ++ ++#ifdef CONFIG_MACH_ONTRACK ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_ONTRACK ++# endif ++# define machine_is_ontrack() (machine_arch_type == MACH_TYPE_ONTRACK) ++#else ++# define machine_is_ontrack() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PM1200 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PM1200 ++# endif ++# define machine_is_pm1200() (machine_arch_type == MACH_TYPE_PM1200) ++#else ++# define machine_is_pm1200() (0) ++#endif ++ ++#ifdef CONFIG_MACH_ESS24XXX ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_ESS24XXX ++# endif ++# define machine_is_ess24562() (machine_arch_type == MACH_TYPE_ESS24XXX) ++#else ++# define machine_is_ess24562() (0) ++#endif ++ ++#ifdef CONFIG_MACH_COREMP7 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_COREMP7 ++# endif ++# define machine_is_coremp7() (machine_arch_type == MACH_TYPE_COREMP7) ++#else ++# define machine_is_coremp7() (0) ++#endif ++ ++#ifdef CONFIG_MACH_NEXCODER_6446 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_NEXCODER_6446 ++# endif ++# define machine_is_nexcoder_6446() (machine_arch_type == MACH_TYPE_NEXCODER_6446) ++#else ++# define machine_is_nexcoder_6446() (0) ++#endif ++ ++#ifdef CONFIG_MACH_STVC8380 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_STVC8380 ++# endif ++# define machine_is_stvc8380() (machine_arch_type == MACH_TYPE_STVC8380) ++#else ++# define machine_is_stvc8380() (0) ++#endif ++ ++#ifdef CONFIG_MACH_TEKLYNX ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_TEKLYNX ++# endif ++# define machine_is_teklynx() (machine_arch_type == MACH_TYPE_TEKLYNX) ++#else ++# define machine_is_teklynx() (0) ++#endif ++ ++#ifdef CONFIG_MACH_CARBONADO ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_CARBONADO ++# endif ++# define machine_is_carbonado() (machine_arch_type == MACH_TYPE_CARBONADO) ++#else ++# define machine_is_carbonado() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SYSMOS_MP730 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SYSMOS_MP730 ++# endif ++# define machine_is_sysmos_mp730() (machine_arch_type == MACH_TYPE_SYSMOS_MP730) ++#else ++# define machine_is_sysmos_mp730() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SNAPPER_CL15 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SNAPPER_CL15 ++# endif ++# define machine_is_snapper_cl15() (machine_arch_type == MACH_TYPE_SNAPPER_CL15) ++#else ++# define machine_is_snapper_cl15() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PGIGIM ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PGIGIM ++# endif ++# define machine_is_pgigim() (machine_arch_type == MACH_TYPE_PGIGIM) ++#else ++# define machine_is_pgigim() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PTX9160P2 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PTX9160P2 ++# endif ++# define machine_is_ptx9160p2() (machine_arch_type == MACH_TYPE_PTX9160P2) ++#else ++# define machine_is_ptx9160p2() (0) ++#endif ++ ++#ifdef CONFIG_MACH_DCORE1 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_DCORE1 ++# endif ++# define machine_is_dcore1() (machine_arch_type == MACH_TYPE_DCORE1) ++#else ++# define machine_is_dcore1() (0) ++#endif ++ ++#ifdef CONFIG_MACH_VICTORPXA ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_VICTORPXA ++# endif ++# define machine_is_victorpxa() (machine_arch_type == MACH_TYPE_VICTORPXA) ++#else ++# define machine_is_victorpxa() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MX2DTB ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MX2DTB ++# endif ++# define machine_is_mx2dtb() (machine_arch_type == MACH_TYPE_MX2DTB) ++#else ++# define machine_is_mx2dtb() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PXA_IREX_ER0100 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PXA_IREX_ER0100 ++# endif ++# define machine_is_pxa_irex_er0100() (machine_arch_type == MACH_TYPE_PXA_IREX_ER0100) ++#else ++# define machine_is_pxa_irex_er0100() (0) ++#endif ++ ++#ifdef CONFIG_MACH_OMAP_PALMZ71 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_OMAP_PALMZ71 ++# endif ++# define machine_is_omap_palmz71() (machine_arch_type == MACH_TYPE_OMAP_PALMZ71) ++#else ++# define machine_is_omap_palmz71() (0) ++#endif ++ ++#ifdef CONFIG_MACH_BARTEC_DEG ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_BARTEC_DEG ++# endif ++# define machine_is_bartec_deg() (machine_arch_type == MACH_TYPE_BARTEC_DEG) ++#else ++# define machine_is_bartec_deg() (0) ++#endif ++ ++#ifdef CONFIG_MACH_HW50251 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_HW50251 ++# endif ++# define machine_is_hw50251() (machine_arch_type == MACH_TYPE_HW50251) ++#else ++# define machine_is_hw50251() (0) ++#endif ++ ++#ifdef CONFIG_MACH_IBOX ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_IBOX ++# endif ++# define machine_is_ibox() (machine_arch_type == MACH_TYPE_IBOX) ++#else ++# define machine_is_ibox() (0) ++#endif ++ ++#ifdef CONFIG_MACH_ATLASLH7A404 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_ATLASLH7A404 ++# endif ++# define machine_is_atlaslh7a404() (machine_arch_type == MACH_TYPE_ATLASLH7A404) ++#else ++# define machine_is_atlaslh7a404() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PT2026 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PT2026 ++# endif ++# define machine_is_pt2026() (machine_arch_type == MACH_TYPE_PT2026) ++#else ++# define machine_is_pt2026() (0) ++#endif ++ ++#ifdef CONFIG_MACH_HTCALPINE ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_HTCALPINE ++# endif ++# define machine_is_htcalpine() (machine_arch_type == MACH_TYPE_HTCALPINE) ++#else ++# define machine_is_htcalpine() (0) ++#endif ++ ++#ifdef CONFIG_MACH_BARTEC_VTU ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_BARTEC_VTU ++# endif ++# define machine_is_bartec_vtu() (machine_arch_type == MACH_TYPE_BARTEC_VTU) ++#else ++# define machine_is_bartec_vtu() (0) ++#endif ++ ++#ifdef CONFIG_MACH_VCOREII ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_VCOREII ++# endif ++# define machine_is_vcoreii() (machine_arch_type == MACH_TYPE_VCOREII) ++#else ++# define machine_is_vcoreii() (0) ++#endif ++ ++#ifdef CONFIG_MACH_PDNB3 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_PDNB3 ++# endif ++# define machine_is_pdnb3() (machine_arch_type == MACH_TYPE_PDNB3) ++#else ++# define machine_is_pdnb3() (0) ++#endif ++ ++#ifdef CONFIG_MACH_HTCBEETLES ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_HTCBEETLES ++# endif ++# define machine_is_htcbeetles() (machine_arch_type == MACH_TYPE_HTCBEETLES) ++#else ++# define machine_is_htcbeetles() (0) ++#endif ++ ++#ifdef CONFIG_MACH_S3C6400 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_S3C6400 ++# endif ++# define machine_is_s3c6400() (machine_arch_type == MACH_TYPE_S3C6400) ++#else ++# define machine_is_s3c6400() (0) ++#endif ++ ++#ifdef CONFIG_MACH_S3C2443 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_S3C2443 ++# endif ++# define machine_is_s3c2443() (machine_arch_type == MACH_TYPE_S3C2443) ++#else ++# define machine_is_s3c2443() (0) ++#endif ++ ++#ifdef CONFIG_MACH_OMAP_LDK ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_OMAP_LDK ++# endif ++# define machine_is_omap_ldk() (machine_arch_type == MACH_TYPE_OMAP_LDK) ++#else ++# define machine_is_omap_ldk() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SMDK2460 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SMDK2460 ++# endif ++# define machine_is_smdk2460() (machine_arch_type == MACH_TYPE_SMDK2460) ++#else ++# define machine_is_smdk2460() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SMDK2440 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SMDK2440 ++# endif ++# define machine_is_smdk2440() (machine_arch_type == MACH_TYPE_SMDK2440) ++#else ++# define machine_is_smdk2440() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SMDK2412 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SMDK2412 ++# endif ++# define machine_is_smdk2412() (machine_arch_type == MACH_TYPE_SMDK2412) ++#else ++# define machine_is_smdk2412() (0) ++#endif ++ ++#ifdef CONFIG_MACH_WEBBOX ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_WEBBOX ++# endif ++# define machine_is_webbox() (machine_arch_type == MACH_TYPE_WEBBOX) ++#else ++# define machine_is_webbox() (0) ++#endif ++ ++#ifdef CONFIG_MACH_CWWNDP ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_CWWNDP ++# endif ++# define machine_is_cwwndp() (machine_arch_type == MACH_TYPE_CWWNDP) ++#else ++# define machine_is_cwwndp() (0) ++#endif ++ ++#ifdef CONFIG_MACH_DRAGON ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_DRAGON ++# endif ++# define machine_is_dragon() (machine_arch_type == MACH_TYPE_DRAGON) ++#else ++# define machine_is_dragon() (0) ++#endif ++ ++#ifdef CONFIG_MACH_OPENDO_CPU_BOARD ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_OPENDO_CPU_BOARD ++# endif ++# define machine_is_opendo_cpu_board() (machine_arch_type == MACH_TYPE_OPENDO_CPU_BOARD) ++#else ++# define machine_is_opendo_cpu_board() (0) ++#endif ++ ++#ifdef CONFIG_MACH_CCM2200 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_CCM2200 ++# endif ++# define machine_is_ccm2200() (machine_arch_type == MACH_TYPE_CCM2200) ++#else ++# define machine_is_ccm2200() (0) ++#endif ++ ++#ifdef CONFIG_MACH_ETWARM ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_ETWARM ++# endif ++# define machine_is_etwarm() (machine_arch_type == MACH_TYPE_ETWARM) ++#else ++# define machine_is_etwarm() (0) ++#endif ++ ++#ifdef CONFIG_MACH_M93030 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_M93030 ++# endif ++# define machine_is_m93030() (machine_arch_type == MACH_TYPE_M93030) ++#else ++# define machine_is_m93030() (0) ++#endif ++ ++#ifdef CONFIG_MACH_CC7U ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_CC7U ++# endif ++# define machine_is_cc7u() (machine_arch_type == MACH_TYPE_CC7U) ++#else ++# define machine_is_cc7u() (0) ++#endif ++ ++#ifdef CONFIG_MACH_MTT_RANGER ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_MTT_RANGER ++# endif ++# define machine_is_mtt_ranger() (machine_arch_type == MACH_TYPE_MTT_RANGER) ++#else ++# define machine_is_mtt_ranger() (0) ++#endif ++ ++#ifdef CONFIG_MACH_NEXUS ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_NEXUS ++# endif ++# define machine_is_nexus() (machine_arch_type == MACH_TYPE_NEXUS) ++#else ++# define machine_is_nexus() (0) ++#endif ++ ++#ifdef CONFIG_MACH_DESMAN ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_DESMAN ++# endif ++# define machine_is_desman() (machine_arch_type == MACH_TYPE_DESMAN) ++#else ++# define machine_is_desman() (0) ++#endif ++ ++#ifdef CONFIG_MACH_BKDE303 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_BKDE303 ++# endif ++# define machine_is_bkde303() (machine_arch_type == MACH_TYPE_BKDE303) ++#else ++# define machine_is_bkde303() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SMDK2413 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SMDK2413 ++# endif ++# define machine_is_smdk2413() (machine_arch_type == MACH_TYPE_SMDK2413) ++#else ++# define machine_is_smdk2413() (0) ++#endif ++ ++#ifdef CONFIG_MACH_AML_M7200 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_AML_M7200 ++# endif ++# define machine_is_aml_m7200() (machine_arch_type == MACH_TYPE_AML_M7200) ++#else ++# define machine_is_aml_m7200() (0) ++#endif ++ ++#ifdef CONFIG_MACH_AML_M5900 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_AML_M5900 ++# endif ++# define machine_is_aml_m5900() (machine_arch_type == MACH_TYPE_AML_M5900) ++#else ++# define machine_is_aml_m5900() (0) ++#endif ++ ++#ifdef CONFIG_MACH_SG640 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SG640 ++# endif ++# define machine_is_sg640() (machine_arch_type == MACH_TYPE_SG640) ++#else ++# define machine_is_sg640() (0) ++#endif ++ ++#ifdef CONFIG_MACH_EDG79524 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_EDG79524 ++# endif ++# define machine_is_edg79524() (machine_arch_type == MACH_TYPE_EDG79524) ++#else ++# define machine_is_edg79524() (0) ++#endif ++ ++#ifdef CONFIG_MACH_AI2410 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_AI2410 ++# endif ++# define machine_is_ai2410() (machine_arch_type == MACH_TYPE_AI2410) ++#else ++# define machine_is_ai2410() (0) ++#endif ++ ++#ifdef CONFIG_MACH_IXP465 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_IXP465 ++# endif ++# define machine_is_ixp465() (machine_arch_type == MACH_TYPE_IXP465) ++#else ++# define machine_is_ixp465() (0) ++#endif ++ ++#ifdef CONFIG_MACH_BALLOON3 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_BALLOON3 ++# endif ++# define machine_is_balloon3() (machine_arch_type == MACH_TYPE_BALLOON3) ++#else ++# define machine_is_balloon3() (0) ++#endif ++ ++#ifdef CONFIG_MACH_QT2410 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_QT2410 ++# endif ++# define machine_is_qt2410() (machine_arch_type == MACH_TYPE_QT2410) ++#else ++# define machine_is_qt2410() (0) ++#endif ++ ++#ifdef CONFIG_MACH_NEO1973_GTA01 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_NEO1973_GTA01 ++# endif ++# define machine_is_neo1973_gta01() (machine_arch_type == MACH_TYPE_NEO1973_GTA01) ++#else ++# define machine_is_neo1973_gta01() (0) ++#endif ++ ++#ifdef CONFIG_MACH_HXD8 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_HXD8 ++# endif ++# define machine_is_hxd8() (machine_arch_type == MACH_TYPE_HXD8) ++#else ++# define machine_is_neo8() (0) ++#endif ++ ++#ifdef CONFIG_MACH_NEO1973_GTA02 ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_NEO1973_GTA02 ++# endif ++# define machine_is_neo1973_gta02() (machine_arch_type == MACH_TYPE_NEO1973_GTA02) ++#else ++# define machine_is_neo1973_gta02() (0) ++#endif ++ ++ + /* + * These have not yet been registered + */ diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-mokoversion.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-mokoversion.patch new file mode 100644 index 0000000000..a44434155e --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-mokoversion.patch @@ -0,0 +1,10 @@ +Index: u-boot/tools/setlocalversion +=================================================================== +--- u-boot.orig/tools/setlocalversion 2007-03-26 14:42:58.000000000 +0200 ++++ u-boot/tools/setlocalversion 2007-03-26 14:46:47.000000000 +0200 +@@ -20,3 +20,5 @@ + printf '%s' -dirty + fi + fi ++ ++printf '%s' -moko9 diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-nand-markbad-reallybad.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-nand-markbad-reallybad.patch new file mode 100644 index 0000000000..d630889e3c --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-nand-markbad-reallybad.patch @@ -0,0 +1,20 @@ +This patch makes sure that the 'nand markbad' command does not only mark a block +'bad' in the bad-block table, but _also_ marks it bad in the OOB area. + +we need this to preserve the bad block status when re-creating the bad block table +at some later point. + +Signed-off-by: Harald Welte +Index: u-boot/drivers/nand/nand_base.c +=================================================================== +--- u-boot.orig/drivers/nand/nand_base.c 2007-03-01 12:47:31.000000000 +0100 ++++ u-boot/drivers/nand/nand_base.c 2007-03-01 12:48:08.000000000 +0100 +@@ -481,7 +481,7 @@ + + /* Do we have a flash based bad block table ? */ + if (this->options & NAND_USE_FLASH_BBT) +- return nand_update_bbt (mtd, ofs); ++ nand_update_bbt (mtd, ofs); + + /* We write two bytes, so we dont have to mess with 16 bit access */ + ofs += mtd->oobsize + (this->badblockpos & ~0x01); diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-neo1973-defaultenv.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-neo1973-defaultenv.patch new file mode 100644 index 0000000000..7e3aa4f480 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-neo1973-defaultenv.patch @@ -0,0 +1,31 @@ +Index: u-boot/include/configs/neo1973_gta01.h +=================================================================== +--- u-boot.orig/include/configs/neo1973_gta01.h 2007-02-27 00:43:16.000000000 +0100 ++++ u-boot/include/configs/neo1973_gta01.h 2007-02-27 00:47:49.000000000 +0100 +@@ -115,8 +115,8 @@ + #include + + #define CONFIG_BOOTDELAY 3 +-#define CONFIG_BOOTARGS "rootfstype=jffs2 root=/dev/mtdblock4 console=ttySAC0,115200 console=tty0 loglevel=8" +-#define CONFIG_BOOTCOMMAND "nand read.e 0x32000000 0x34000 0x200000; bootm 0x32000000" ++#define CONFIG_BOOTARGS "" ++#define CONFIG_BOOTCOMMAND "setenv bootargs ${bootargs_base} ${mtdparts}; nand read.e 0x32000000 kernel; bootm 0x32000000" + + #define CONFIG_DOS_PARTITION 1 + +@@ -181,11 +181,14 @@ + #define CONFIG_USBD_PRODUCTID_CDCACM 0x5119 /* CDC ACM */ + #define CONFIG_USBD_MANUFACTURER "OpenMoko, Inc" + #define CONFIG_USBD_PRODUCT_NAME "Neo1973 Bootloader " U_BOOT_VERSION +-#define CONFIG_EXTRA_ENV_SETTINGS "usbtty=cdc_acm\0" + #define CONFIG_USBD_DFU 1 + #define CONFIG_USBD_DFU_XFER_SIZE 4096 /* 0x4000 */ + #define CONFIG_USBD_DFU_INTERFACE 2 + ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "usbtty=cdc_acm\0" \ ++ "bootargs_base=rootfstype=jffs2 root=/dev/mtdblock4 console=ttySAC0,115200 console=tty0 loglevel=8\0" \ ++ "" + + /*----------------------------------------------------------------------- + * Physical Memory Map diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-neo1973-resume.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-neo1973-resume.patch new file mode 100644 index 0000000000..19d912620d --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-neo1973-resume.patch @@ -0,0 +1,113 @@ +Resume support for low-level uboot code, Version 5 + +Signed-off-by: Ben Dooks + +Index: u-boot/cpu/arm920t/start.S +=================================================================== +--- u-boot.orig/cpu/arm920t/start.S 2007-02-28 03:51:24.000000000 +0100 ++++ u-boot/cpu/arm920t/start.S 2007-03-01 02:43:47.000000000 +0100 +@@ -158,18 +158,68 @@ + str r1, [r0] + # endif + ++ /* default FCLK is 202 MHz ! */ ++#define LOCKTIME 0x4c000000 ++#define UPLLCON 0x4c000008 ++//#define MPLLCFG ((0x90 << 12) + (0x2 << 4) + 0x2) ++#define MPLLCFG ((0x90 << 12) + (0x7 << 4) + 0x0) ++#define UPLLCFG ((0x78 << 12) + (0x2 << 4) + 0x3) ++ ldr r0, =LOCKTIME ++ mov r1, #0xffffff ++ str r1, [r0] ++ ++ ldr r0, =UPLLCON ++ ldr r1, =UPLLCFG ++ str r1, [r0] ++ ++ /* Page 7-19, seven nops between UPLL and MPLL */ ++ nop ++ nop ++ nop ++ nop ++ nop ++ nop ++ nop ++ ++ ldr r1, =MPLLCFG ++ str r1, [r0, #-4] /* MPLLCON */ ++ + /* FCLK:HCLK:PCLK = 1:2:4 */ +- /* default FCLK is 120 MHz ! */ + ldr r0, =CLKDIVN + mov r1, #3 + str r1, [r0] ++ ++#if 1 ++ /* enable uart */ ++ ldr r0, =0x4c00000c /* clkcon */ ++ ldr r1, =0x7fff0 /* all clocks on */ ++ str r1, [r0] ++ ++ /* gpio UART0 init */ ++ ldr r0, =0x56000070 ++ mov r1, #0xaa ++ str r1, [r0] ++ ++ /* init uart */ ++ ldr r0, =0x50000000 ++ mov r1, #0x03 ++ str r1, [r0] ++ ldr r1, =0x245 ++ str r1, [r0, #0x04] ++ mov r1, #0x01 ++ str r1, [r0, #0x08] ++ mov r1, #0x00 ++ str r1, [r0, #0x0c] ++ mov r1, #0x1a ++ str r1, [r0, #0x28] ++#endif ++ + #endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */ + + #ifndef CONFIG_SKIP_LOWLEVEL_INIT + #ifndef CONFIG_LL_INIT_NAND_ONLY + bl cpu_init_crit + #endif +-#endif + + #ifndef CONFIG_SKIP_RELOCATE_UBOOT + adr r0, _start /* r0 <- current position of code */ +@@ -202,9 +252,33 @@ + + #ifdef CONFIG_S3C2410_NAND_BOOT + nand_load: ++ /* take sdram out of power down */ ++ ldr r0, =0x56000080 /* misccr */ ++ ldr r1, [ r0 ] ++ bic r1, r1, #(S3C2410_MISCCR_nEN_SCLK0 | S3C2410_MISCCR_nEN_SCLK1 | S3C2410_MISCCR_nEN_SCLKE) ++ str r1, [ r0 ] ++ ++ /* ensure signals stabalise */ ++ mov r1, #128 ++1: subs r1, r1, #1 ++ bpl 1b ++ + #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && defined(CONFIG_LL_INIT_NAND_ONLY) + bl cpu_init_crit + #endif ++#if defined(CONFIG_S3C2410) ++ /* ensure some refresh has happened */ ++ ldr r1, =0xfffff ++1: subs r1, r1, #1 ++ bpl 1b ++ ++ /* test for resume */ ++ ldr r1, =0x560000B4 /* gstatus2 */ ++ ldr r0, [ r1 ] ++ tst r0, #0x02 /* is this resume from power down */ ++ ldrne pc, [r1, #4] /* gstatus3 */ ++#endif /* CONFIG_S3C2410 */ ++#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + + /* mov r10, lr */ + diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2410-misccr-definitions.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2410-misccr-definitions.patch new file mode 100644 index 0000000000..6efe24651a --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2410-misccr-definitions.patch @@ -0,0 +1,45 @@ +Index: u-boot/include/s3c2410.h +=================================================================== +--- u-boot.orig/include/s3c2410.h ++++ u-boot/include/s3c2410.h +@@ -233,4 +233,40 @@ static inline S3C2410_SDI * S3C2410_GetB + rINTPND;\ + } + /* Wait until rINTPND is changed for the case that the ISR is very short. */ ++ ++#define S3C2410_MISCCR_USBDEV (0<<3) ++#define S3C2410_MISCCR_USBHOST (1<<3) ++ ++#define S3C2410_MISCCR_CLK0_MPLL (0<<4) ++#define S3C2410_MISCCR_CLK0_UPLL (1<<4) ++#define S3C2410_MISCCR_CLK0_FCLK (2<<4) ++#define S3C2410_MISCCR_CLK0_HCLK (3<<4) ++#define S3C2410_MISCCR_CLK0_PCLK (4<<4) ++#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4) ++#define S3C2410_MISCCR_CLK0_MASK (7<<4) ++ ++#define S3C2410_MISCCR_CLK1_MPLL (0<<8) ++#define S3C2410_MISCCR_CLK1_UPLL (1<<8) ++#define S3C2410_MISCCR_CLK1_FCLK (2<<8) ++#define S3C2410_MISCCR_CLK1_HCLK (3<<8) ++#define S3C2410_MISCCR_CLK1_PCLK (4<<8) ++#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8) ++#define S3C2410_MISCCR_CLK1_MASK (7<<8) ++ ++#define S3C2410_MISCCR_USBSUSPND0 (1<<12) ++#define S3C2410_MISCCR_USBSUSPND1 (1<<13) ++ ++#define S3C2410_MISCCR_nRSTCON (1<<16) ++ ++#define S3C2410_MISCCR_nEN_SCLK0 (1<<17) ++#define S3C2410_MISCCR_nEN_SCLK1 (1<<18) ++#define S3C2410_MISCCR_nEN_SCLKE (1<<19) ++#define S3C2410_MISCCR_SDSLEEP (7<<17) ++ ++#define S3C2410_CLKSLOW_UCLK_OFF (1<<7) ++#define S3C2410_CLKSLOW_MPLL_OFF (1<<5) ++#define S3C2410_CLKSLOW_SLOW (1<<4) ++#define S3C2410_CLKSLOW_SLOWVAL(x) (x) ++#define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7) ++ + #endif /*__S3C2410_H__*/ diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2410-mmc.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2410-mmc.patch new file mode 100644 index 0000000000..b775beaa07 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2410-mmc.patch @@ -0,0 +1,818 @@ +This patch adds MMC/SD support to the S3C2410 SoC code in +u-boot + +Signed-off-by: Harald Welte + +Index: u-boot/cpu/arm920t/s3c24x0/Makefile +=================================================================== +--- u-boot.orig/cpu/arm920t/s3c24x0/Makefile ++++ u-boot/cpu/arm920t/s3c24x0/Makefile +@@ -26,7 +26,7 @@ + LIB = $(obj)lib$(SOC).a + + COBJS = i2c.o interrupts.o serial.o speed.o \ +- usb_ohci.o nand_read.o nand.o cmd_s3c2410.o ++ usb_ohci.o nand_read.o nand.o mmc.o cmd_s3c2410.o + + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) + OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +Index: u-boot/cpu/arm920t/s3c24x0/mmc.c +=================================================================== +--- /dev/null ++++ u-boot/cpu/arm920t/s3c24x0/mmc.c +@@ -0,0 +1,531 @@ ++/* ++ * u-boot S3C2410 MMC/SD card driver ++ * (C) Copyright 2006 by OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * based on u-boot pxa MMC driver and linux/drivers/mmc/s3c2410mci.c ++ * (C) 2005-2005 Thomas Kleffel ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_MMC ++ ++#define CONFIG_MMC_WIDE ++ ++static S3C2410_SDI *sdi; ++ ++static block_dev_desc_t mmc_dev; ++ ++block_dev_desc_t * mmc_get_dev(int dev) ++{ ++ return ((block_dev_desc_t *)&mmc_dev); ++} ++ ++/* ++ * FIXME needs to read cid and csd info to determine block size ++ * and other parameters ++ */ ++static uchar mmc_buf[MMC_BLOCK_SIZE]; ++static mmc_csd_t mmc_csd; ++static int mmc_ready = 0; ++static int wide = 0; ++ ++ ++#define CMD_F_RESP 0x01 ++#define CMD_F_RESP_LONG 0x02 ++ ++static u_int32_t *mmc_cmd(ushort cmd, ulong arg, ushort flags) ++{ ++ static u_int32_t resp[5]; ++ ++ u_int32_t ccon, csta; ++ u_int32_t csta_rdy_bit = S3C2410_SDICMDSTAT_CMDSENT; ++ ++ memset(resp, 0, sizeof(resp)); ++ ++ debug("mmc_cmd CMD%d arg=0x%08x flags=%x\n", cmd, arg, flags); ++ ++ sdi->SDICSTA = 0xffffffff; ++ sdi->SDIDSTA = 0xffffffff; ++ sdi->SDIFSTA = 0xffffffff; ++ ++ sdi->SDICARG = arg; ++ ++ ccon = cmd & S3C2410_SDICMDCON_INDEX; ++ ccon |= S3C2410_SDICMDCON_SENDERHOST|S3C2410_SDICMDCON_CMDSTART; ++ ++ if (flags & CMD_F_RESP) { ++ ccon |= S3C2410_SDICMDCON_WAITRSP; ++ csta_rdy_bit = S3C2410_SDICMDSTAT_RSPFIN; /* 1 << 9 */ ++ } ++ ++ if (flags & CMD_F_RESP_LONG) ++ ccon |= S3C2410_SDICMDCON_LONGRSP; ++ ++ sdi->SDICCON = ccon; ++ ++ while (1) { ++ csta = sdi->SDICSTA; ++ if (csta & csta_rdy_bit) ++ break; ++ if (csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) { ++ printf("===============> MMC CMD Timeout\n"); ++ sdi->SDICSTA |= S3C2410_SDICMDSTAT_CMDTIMEOUT; ++ break; ++ } ++ } ++ ++ debug("final MMC CMD status 0x%x\n", csta); ++ ++ sdi->SDICSTA |= csta_rdy_bit; ++ ++ if (flags & CMD_F_RESP) { ++ resp[0] = sdi->SDIRSP0; ++ resp[1] = sdi->SDIRSP1; ++ resp[2] = sdi->SDIRSP2; ++ resp[3] = sdi->SDIRSP3; ++ } ++ ++ return resp; ++} ++ ++#define FIFO_FILL(host) ((host->SDIFSTA & S3C2410_SDIFSTA_COUNTMASK) >> 2) ++ ++static int mmc_block_read(uchar *dst, ulong src, ulong len) ++{ ++ u_int32_t dcon, fifo; ++ u_int32_t *dst_u32 = (u_int32_t *)dst; ++ u_int32_t *resp; ++ ++ if (len == 0) ++ return 0; ++ ++ debug("mmc_block_rd dst %lx src %lx len %d\n", (ulong)dst, src, len); ++ ++ /* set block len */ ++ resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, len, CMD_F_RESP); ++ sdi->SDIBSIZE = len; ++ ++ //sdi->SDIPRE = 0xff; ++ ++ /* setup data */ ++ dcon = (len >> 9) & S3C2410_SDIDCON_BLKNUM; ++ dcon |= S3C2410_SDIDCON_BLOCKMODE; ++ dcon |= S3C2410_SDIDCON_RXAFTERCMD|S3C2410_SDIDCON_XFER_RXSTART; ++ if (wide) ++ dcon |= S3C2410_SDIDCON_WIDEBUS; ++ sdi->SDIDCON = dcon; ++ ++ /* send read command */ ++ resp = mmc_cmd(MMC_CMD_READ_BLOCK, src, CMD_F_RESP); ++ ++ while (len > 0) { ++ u_int32_t sdidsta = sdi->SDIDSTA; ++ fifo = FIFO_FILL(sdi); ++ if (sdidsta & (S3C2410_SDIDSTA_FIFOFAIL| ++ S3C2410_SDIDSTA_CRCFAIL| ++ S3C2410_SDIDSTA_RXCRCFAIL| ++ S3C2410_SDIDSTA_DATATIMEOUT)) { ++ printf("mmc_block_read: err SDIDSTA=0x%08x\n", sdidsta); ++ return -EIO; ++ } ++ ++ while (fifo--) { ++ //debug("dst_u32 = 0x%08x\n", dst_u32); ++ *(dst_u32++) = sdi->SDIDAT; ++ if (len >= 4) ++ len -= 4; ++ else { ++ len = 0; ++ break; ++ } ++ } ++ } ++ ++ debug("waiting for SDIDSTA (currently 0x%08x\n", sdi->SDIDSTA); ++ while (!(sdi->SDIDSTA & (1 << 4))) {} ++ debug("done waiting for SDIDSTA (currently 0x%08x\n", sdi->SDIDSTA); ++ ++ sdi->SDIDCON = 0; ++ ++ if (!(sdi->SDIDSTA & S3C2410_SDIDSTA_XFERFINISH)) ++ debug("mmc_block_read; transfer not finished!\n"); ++ ++ return 0; ++} ++ ++static int mmc_block_write(ulong dst, uchar *src, int len) ++{ ++ printf("MMC block write not yet supported on S3C2410!\n"); ++ return -1; ++} ++ ++ ++int mmc_read(ulong src, uchar *dst, int size) ++{ ++ ulong end, part_start, part_end, part_len, aligned_start, aligned_end; ++ ulong mmc_block_size, mmc_block_address; ++ ++ if (size == 0) ++ return 0; ++ ++ if (!mmc_ready) { ++ printf("Please initialize the MMC first\n"); ++ return -1; ++ } ++ ++ mmc_block_size = MMC_BLOCK_SIZE; ++ mmc_block_address = ~(mmc_block_size - 1); ++ ++ src -= CFG_MMC_BASE; ++ end = src + size; ++ part_start = ~mmc_block_address & src; ++ part_end = ~mmc_block_address & end; ++ aligned_start = mmc_block_address & src; ++ aligned_end = mmc_block_address & end; ++ ++ /* all block aligned accesses */ ++ debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", ++ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); ++ if (part_start) { ++ part_len = mmc_block_size - part_start; ++ debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", ++ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); ++ if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) ++ return -1; ++ ++ memcpy(dst, mmc_buf+part_start, part_len); ++ dst += part_len; ++ src += part_len; ++ } ++ debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", ++ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); ++ for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size) { ++ debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", ++ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); ++ if ((mmc_block_read((uchar *)(dst), src, mmc_block_size)) < 0) ++ return -1; ++ } ++ debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", ++ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); ++ if (part_end && src < end) { ++ debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", ++ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); ++ if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) ++ return -1; ++ ++ memcpy(dst, mmc_buf, part_end); ++ } ++ return 0; ++} ++ ++int mmc_write(uchar *src, ulong dst, int size) ++{ ++ ulong end, part_start, part_end, part_len, aligned_start, aligned_end; ++ ulong mmc_block_size, mmc_block_address; ++ ++ if (size == 0) ++ return 0; ++ ++ if (!mmc_ready) { ++ printf("Please initialize the MMC first\n"); ++ return -1; ++ } ++ ++ mmc_block_size = MMC_BLOCK_SIZE; ++ mmc_block_address = ~(mmc_block_size - 1); ++ ++ dst -= CFG_MMC_BASE; ++ end = dst + size; ++ part_start = ~mmc_block_address & dst; ++ part_end = ~mmc_block_address & end; ++ aligned_start = mmc_block_address & dst; ++ aligned_end = mmc_block_address & end; ++ ++ /* all block aligned accesses */ ++ debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", ++ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); ++ if (part_start) { ++ part_len = mmc_block_size - part_start; ++ debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", ++ (ulong)src, dst, end, part_start, part_end, aligned_start, aligned_end); ++ if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) ++ return -1; ++ ++ memcpy(mmc_buf+part_start, src, part_len); ++ if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) < 0) ++ return -1; ++ ++ dst += part_len; ++ src += part_len; ++ } ++ debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", ++ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); ++ for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) { ++ debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", ++ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); ++ if ((mmc_block_write(dst, (uchar *)src, mmc_block_size)) < 0) ++ return -1; ++ ++ } ++ debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", ++ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); ++ if (part_end && dst < end) { ++ debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n", ++ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end); ++ if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) ++ return -1; ++ ++ memcpy(mmc_buf, src, part_end); ++ if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0) ++ return -1; ++ ++ } ++ return 0; ++} ++ ++ulong mmc_bread(int dev_num, ulong blknr, ulong blkcnt, void *dst) ++{ ++ int mmc_block_size = MMC_BLOCK_SIZE; ++ ulong src = blknr * mmc_block_size + CFG_MMC_BASE; ++ ++ mmc_read(src, dst, blkcnt*mmc_block_size); ++ return blkcnt; ++} ++ ++/* MMC_DEFAULT_RCA should probably be just 1, but this may break other code ++ that expects it to be shifted. */ ++static u_int16_t rca = MMC_DEFAULT_RCA >> 16; ++ ++static u_int32_t mmc_size(const struct mmc_csd *csd) ++{ ++ u_int32_t block_len, mult, blocknr; ++ ++ block_len = csd->read_bl_len << 12; ++ mult = csd->c_size_mult1 << 8; ++ blocknr = (csd->c_size+1) * mult; ++ ++ return blocknr * block_len; ++} ++ ++struct sd_cid { ++ char pnm_0; /* product name */ ++ char oid_1; /* OEM/application ID */ ++ char oid_0; ++ uint8_t mid; /* manufacturer ID */ ++ char pnm_4; ++ char pnm_3; ++ char pnm_2; ++ char pnm_1; ++ uint8_t psn_2; /* product serial number */ ++ uint8_t psn_1; ++ uint8_t psn_0; /* MSB */ ++ uint8_t prv; /* product revision */ ++ uint8_t crc; /* CRC7 checksum, b0 is unused and set to 1 */ ++ uint8_t mdt_1; /* manufacturing date, LSB, RRRRyyyy yyyymmmm */ ++ uint8_t mdt_0; /* MSB */ ++ uint8_t psn_3; /* LSB */ ++}; ++ ++static void print_mmc_cid(mmc_cid_t *cid) ++{ ++ printf("MMC found. Card desciption is:\n"); ++ printf("Manufacturer ID = %02x%02x%02x\n", ++ cid->id[0], cid->id[1], cid->id[2]); ++ printf("HW/FW Revision = %x %x\n",cid->hwrev, cid->fwrev); ++ cid->hwrev = cid->fwrev = 0; /* null terminate string */ ++ printf("Product Name = %s\n",cid->name); ++ printf("Serial Number = %02x%02x%02x\n", ++ cid->sn[0], cid->sn[1], cid->sn[2]); ++ printf("Month = %d\n",cid->month); ++ printf("Year = %d\n",1997 + cid->year); ++} ++ ++static void print_sd_cid(const struct sd_cid *cid) ++{ ++ printf("Manufacturer: 0x%02x, OEM \"%c%c\"\n", ++ cid->mid, cid->oid_0, cid->oid_1); ++ printf("Product name: \"%c%c%c%c%c\", revision %d.%d\n", ++ cid->pnm_0, cid->pnm_1, cid->pnm_2, cid->pnm_3, cid->pnm_4, ++ cid->prv >> 4, cid->prv & 15); ++ printf("Serial number: %u\n", ++ cid->psn_0 << 24 | cid->psn_1 << 16 | cid->psn_2 << 8 | ++ cid->psn_3); ++ printf("Manufacturing date: %d/%d\n", ++ cid->mdt_1 & 15, ++ 2000+((cid->mdt_0 & 15) << 4)+((cid->mdt_1 & 0xf0) >> 4)); ++ printf("CRC: 0x%02x, b0 = %d\n", ++ cid->crc >> 1, cid->crc & 1); ++} ++ ++int mmc_init(int verbose) ++{ ++ int retries, rc = -ENODEV; ++ int is_sd = 0; ++ u_int32_t *resp; ++ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); ++ ++ sdi = S3C2410_GetBase_SDI(); ++ ++ debug("mmc_init(PCLK=%u)\n", get_PCLK()); ++ ++ clk_power->CLKCON |= (1 << 9); ++ ++ /* S3C2410 has some bug that prevents reliable operation at higher speed */ ++ //sdi->SDIPRE = 0x3e; /* SDCLK = PCLK/2 / (SDIPRE+1) = 396kHz */ ++ sdi->SDIPRE = 0x02; /* SDCLK = PCLK/2 / (SDIPRE+1) = 396kHz */ ++ sdi->SDIBSIZE = 512; ++ sdi->SDIDTIMER = 0xffff; ++ sdi->SDIIMSK = 0x0; ++ sdi->SDICON = S3C2410_SDICON_FIFORESET|S3C2440_SDICON_MMCCLOCK; ++ udelay(125000); /* FIXME: 74 SDCLK cycles */ ++ ++ mmc_csd.c_size = 0; ++ ++ /* reset */ ++ retries = 10; ++ resp = mmc_cmd(MMC_CMD_RESET, 0, 0); ++ ++ printf("trying to detect SD Card...\n"); ++ while (retries--) { ++ udelay(100000); ++ resp = mmc_cmd(55, 0x00000000, CMD_F_RESP); ++ resp = mmc_cmd(41, 0x00300000, CMD_F_RESP); ++ ++ if (resp[0] & (1 << 31)) { ++ is_sd = 1; ++ break; ++ } ++ } ++ ++ if (retries == 0 && !is_sd) { ++ retries = 10; ++ printf("failed to detect SD Card, trying MMC\n"); ++ resp = mmc_cmd(MMC_CMD_SEND_OP_COND, 0x00ffc000, CMD_F_RESP); ++ while (retries-- && resp && !(resp[4] & 0x80)) { ++ debug("resp %x %x\n", resp[0], resp[1]); ++ udelay(50); ++ resp = mmc_cmd(1, 0x00ffff00, CMD_F_RESP); ++ } ++ } ++ ++ /* try to get card id */ ++ resp = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, CMD_F_RESP|CMD_F_RESP_LONG); ++ if (resp) { ++ if (!is_sd) { ++ /* TODO configure mmc driver depending on card ++ attributes */ ++ mmc_cid_t *cid = (mmc_cid_t *)resp; ++ ++ if (verbose) ++ print_mmc_cid(cid); ++ sprintf((char *) mmc_dev.vendor, ++ "Man %02x%02x%02x Snr %02x%02x%02x", ++ cid->id[0], cid->id[1], cid->id[2], ++ cid->sn[0], cid->sn[1], cid->sn[2]); ++ sprintf((char *) mmc_dev.product,"%s",cid->name); ++ sprintf((char *) mmc_dev.revision,"%x %x", ++ cid->hwrev, cid->fwrev); ++ } ++ else { ++ struct sd_cid *cid = (struct sd_cid *) resp; ++ ++ if (verbose) ++ print_sd_cid(cid); ++ sprintf((char *) mmc_dev.vendor, ++ "Man %02 OEM %c%c \"%c%c%c%c%c\"", ++ cid->mid, cid->oid_0, cid->oid_1, ++ cid->pnm_0, cid->pnm_1, cid->pnm_2, cid->pnm_3, ++ cid->pnm_4); ++ sprintf((char *) mmc_dev.product, "%d", ++ cid->psn_0 << 24 | cid->psn_1 << 16 | ++ cid->psn_2 << 8 | cid->psn_3); ++ sprintf((char *) mmc_dev.revision, "%d.%d", ++ cid->prv >> 4, cid->prv & 15); ++ } ++ ++ /* fill in device description */ ++ mmc_dev.if_type = IF_TYPE_MMC; ++ mmc_dev.part_type = PART_TYPE_DOS; ++ mmc_dev.dev = 0; ++ mmc_dev.lun = 0; ++ mmc_dev.type = 0; ++ /* FIXME fill in the correct size (is set to 32MByte) */ ++ mmc_dev.blksz = 512; ++ mmc_dev.lba = 0x10000; ++ mmc_dev.removable = 0; ++ mmc_dev.block_read = mmc_bread; ++ ++ /* MMC exists, get CSD too */ ++ resp = mmc_cmd(MMC_CMD_SET_RCA, MMC_DEFAULT_RCA, CMD_F_RESP); ++ if (is_sd) ++ rca = resp[0] >> 16; ++ ++ resp = mmc_cmd(MMC_CMD_SEND_CSD, rca<<16, CMD_F_RESP|CMD_F_RESP_LONG); ++ if (resp) { ++ mmc_csd_t *csd = (mmc_csd_t *)resp; ++ memcpy(&mmc_csd, csd, sizeof(csd)); ++ rc = 0; ++ mmc_ready = 1; ++ /* FIXME add verbose printout for csd */ ++ printf("READ_BL_LEN=%u, C_SIZE_MULT=%u, C_SIZE=%u\n", ++ csd->read_bl_len, csd->c_size_mult1, csd->c_size); ++ printf("size = %u\n", mmc_size(csd)); ++ } ++ } ++ ++ resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca<<16, CMD_F_RESP); ++ ++#ifdef CONFIG_MMC_WIDE ++ if (is_sd) { ++ resp = mmc_cmd(55, rca<<16, CMD_F_RESP); ++ resp = mmc_cmd(6, 0x02, CMD_F_RESP); ++ wide = 1; ++ } ++#endif ++ ++ fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */ ++ ++ return rc; ++} ++ ++int ++mmc_ident(block_dev_desc_t *dev) ++{ ++ return 0; ++} ++ ++int ++mmc2info(ulong addr) ++{ ++ /* FIXME hard codes to 32 MB device */ ++ if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000) ++ return 1; ++ ++ return 0; ++} ++ ++#endif /* CONFIG_MMC */ +Index: u-boot/include/asm-arm/arch-s3c24x0/mmc.h +=================================================================== +--- /dev/null ++++ u-boot/include/asm-arm/arch-s3c24x0/mmc.h +@@ -0,0 +1,112 @@ ++/* ++ * linux/drivers/mmc/mmc_pxa.h ++ * ++ * Author: Vladimir Shebordaev, Igor Oblakov ++ * Copyright: MontaVista Software Inc. ++ * ++ * $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#ifndef __MMC_PXA_P_H__ ++#define __MMC_PXA_P_H__ ++ ++#include ++ ++#define MMC_DEFAULT_RCA (1<<16) ++ ++#define MMC_BLOCK_SIZE 512 ++#define MMC_CMD_RESET 0 ++#define MMC_CMD_SEND_OP_COND 1 ++#define MMC_CMD_ALL_SEND_CID 2 ++#define MMC_CMD_SET_RCA 3 ++#define MMC_CMD_SELECT_CARD 7 ++#define MMC_CMD_SEND_CSD 9 ++#define MMC_CMD_SEND_CID 10 ++#define MMC_CMD_SEND_STATUS 13 ++#define MMC_CMD_SET_BLOCKLEN 16 ++#define MMC_CMD_READ_BLOCK 17 ++#define MMC_CMD_RD_BLK_MULTI 18 ++#define MMC_CMD_WRITE_BLOCK 24 ++ ++#define MMC_MAX_BLOCK_SIZE 512 ++ ++#define MMC_R1_IDLE_STATE 0x01 ++#define MMC_R1_ERASE_STATE 0x02 ++#define MMC_R1_ILLEGAL_CMD 0x04 ++#define MMC_R1_COM_CRC_ERR 0x08 ++#define MMC_R1_ERASE_SEQ_ERR 0x01 ++#define MMC_R1_ADDR_ERR 0x02 ++#define MMC_R1_PARAM_ERR 0x04 ++ ++#define MMC_R1B_WP_ERASE_SKIP 0x0002 ++#define MMC_R1B_ERR 0x0004 ++#define MMC_R1B_CC_ERR 0x0008 ++#define MMC_R1B_CARD_ECC_ERR 0x0010 ++#define MMC_R1B_WP_VIOLATION 0x0020 ++#define MMC_R1B_ERASE_PARAM 0x0040 ++#define MMC_R1B_OOR 0x0080 ++#define MMC_R1B_IDLE_STATE 0x0100 ++#define MMC_R1B_ERASE_RESET 0x0200 ++#define MMC_R1B_ILLEGAL_CMD 0x0400 ++#define MMC_R1B_COM_CRC_ERR 0x0800 ++#define MMC_R1B_ERASE_SEQ_ERR 0x1000 ++#define MMC_R1B_ADDR_ERR 0x2000 ++#define MMC_R1B_PARAM_ERR 0x4000 ++ ++typedef struct mmc_cid ++{ ++ /* FIXME: BYTE_ORDER */ ++ uchar year:4, ++ month:4; ++ uchar sn[3]; ++ uchar fwrev:4, ++ hwrev:4; ++ uchar name[6]; ++ uchar id[3]; ++} mmc_cid_t; ++ ++typedef struct mmc_csd ++{ ++ uchar ecc:2, ++ file_format:2, ++ tmp_write_protect:1, ++ perm_write_protect:1, ++ copy:1, ++ file_format_grp:1; ++ uint64_t content_prot_app:1, ++ rsvd3:4, ++ write_bl_partial:1, ++ write_bl_len:4, ++ r2w_factor:3, ++ default_ecc:2, ++ wp_grp_enable:1, ++ wp_grp_size:5, ++ erase_grp_mult:5, ++ erase_grp_size:5, ++ c_size_mult1:3, ++ vdd_w_curr_max:3, ++ vdd_w_curr_min:3, ++ vdd_r_curr_max:3, ++ vdd_r_curr_min:3, ++ c_size:12, ++ rsvd2:2, ++ dsr_imp:1, ++ read_blk_misalign:1, ++ write_blk_misalign:1, ++ read_bl_partial:1; ++ ++ ushort read_bl_len:4, ++ ccc:12; ++ uchar tran_speed; ++ uchar nsac; ++ uchar taac; ++ uchar rsvd1:2, ++ spec_vers:4, ++ csd_structure:2; ++} mmc_csd_t; ++ ++ ++#endif /* __MMC_PXA_P_H__ */ +Index: u-boot/include/asm-arm/arch-s3c24x0/regs-sdi.h +=================================================================== +--- /dev/null ++++ u-boot/include/asm-arm/arch-s3c24x0/regs-sdi.h +@@ -0,0 +1,110 @@ ++/* linux/include/asm/arch-s3c2410/regs-sdi.h ++ * ++ * Copyright (c) 2004 Simtec Electronics ++ * http://www.simtec.co.uk/products/SWLINUX/ ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * S3C2410 MMC/SDIO register definitions ++ * ++ * Changelog: ++ * 18-Aug-2004 Ben Dooks Created initial file ++ * 29-Nov-2004 Koen Martens Added some missing defines, fixed duplicates ++ * 29-Nov-2004 Ben Dooks Updated Koen's patch ++*/ ++ ++#ifndef __ASM_ARM_REGS_SDI ++#define __ASM_ARM_REGS_SDI "regs-sdi.h" ++ ++#define S3C2440_SDICON_SDRESET (1<<8) ++#define S3C2440_SDICON_MMCCLOCK (1<<5) ++#define S3C2410_SDICON_BYTEORDER (1<<4) ++#define S3C2410_SDICON_SDIOIRQ (1<<3) ++#define S3C2410_SDICON_RWAITEN (1<<2) ++#define S3C2410_SDICON_FIFORESET (1<<1) ++#define S3C2410_SDICON_CLOCKTYPE (1<<0) ++ ++#define S3C2410_SDICMDCON_ABORT (1<<12) ++#define S3C2410_SDICMDCON_WITHDATA (1<<11) ++#define S3C2410_SDICMDCON_LONGRSP (1<<10) ++#define S3C2410_SDICMDCON_WAITRSP (1<<9) ++#define S3C2410_SDICMDCON_CMDSTART (1<<8) ++#define S3C2410_SDICMDCON_SENDERHOST (1<<6) ++#define S3C2410_SDICMDCON_INDEX (0x3f) ++ ++#define S3C2410_SDICMDSTAT_CRCFAIL (1<<12) ++#define S3C2410_SDICMDSTAT_CMDSENT (1<<11) ++#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10) ++#define S3C2410_SDICMDSTAT_RSPFIN (1<<9) ++#define S3C2410_SDICMDSTAT_XFERING (1<<8) ++#define S3C2410_SDICMDSTAT_INDEX (0xff) ++ ++#define S3C2440_SDIDCON_DS_BYTE (0<<22) ++#define S3C2440_SDIDCON_DS_HALFWORD (1<<22) ++#define S3C2440_SDIDCON_DS_WORD (2<<22) ++#define S3C2410_SDIDCON_IRQPERIOD (1<<21) ++#define S3C2410_SDIDCON_TXAFTERRESP (1<<20) ++#define S3C2410_SDIDCON_RXAFTERCMD (1<<19) ++#define S3C2410_SDIDCON_BUSYAFTERCMD (1<<18) ++#define S3C2410_SDIDCON_BLOCKMODE (1<<17) ++#define S3C2410_SDIDCON_WIDEBUS (1<<16) ++#define S3C2410_SDIDCON_DMAEN (1<<15) ++#define S3C2410_SDIDCON_STOP (1<<14) ++#define S3C2440_SDIDCON_DATSTART (1<<14) ++#define S3C2410_SDIDCON_DATMODE (3<<12) ++#define S3C2410_SDIDCON_BLKNUM (0x7ff) ++ ++/* constants for S3C2410_SDIDCON_DATMODE */ ++#define S3C2410_SDIDCON_XFER_READY (0<<12) ++#define S3C2410_SDIDCON_XFER_CHKSTART (1<<12) ++#define S3C2410_SDIDCON_XFER_RXSTART (2<<12) ++#define S3C2410_SDIDCON_XFER_TXSTART (3<<12) ++ ++#define S3C2410_SDIDCNT_BLKNUM_MASK (0xFFF) ++#define S3C2410_SDIDCNT_BLKNUM_SHIFT (12) ++ ++#define S3C2410_SDIDSTA_RDYWAITREQ (1<<10) ++#define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9) ++#define S3C2410_SDIDSTA_FIFOFAIL (1<<8) /* reserved on 2440 */ ++#define S3C2410_SDIDSTA_CRCFAIL (1<<7) ++#define S3C2410_SDIDSTA_RXCRCFAIL (1<<6) ++#define S3C2410_SDIDSTA_DATATIMEOUT (1<<5) ++#define S3C2410_SDIDSTA_XFERFINISH (1<<4) ++#define S3C2410_SDIDSTA_BUSYFINISH (1<<3) ++#define S3C2410_SDIDSTA_SBITERR (1<<2) /* reserved on 2410a/2440 */ ++#define S3C2410_SDIDSTA_TXDATAON (1<<1) ++#define S3C2410_SDIDSTA_RXDATAON (1<<0) ++ ++#define S3C2440_SDIFSTA_FIFORESET (1<<16) ++#define S3C2440_SDIFSTA_FIFOFAIL (3<<14) /* 3 is correct (2 bits) */ ++#define S3C2410_SDIFSTA_TFDET (1<<13) ++#define S3C2410_SDIFSTA_RFDET (1<<12) ++#define S3C2410_SDIFSTA_TFHALF (1<<11) ++#define S3C2410_SDIFSTA_TFEMPTY (1<<10) ++#define S3C2410_SDIFSTA_RFLAST (1<<9) ++#define S3C2410_SDIFSTA_RFFULL (1<<8) ++#define S3C2410_SDIFSTA_RFHALF (1<<7) ++#define S3C2410_SDIFSTA_COUNTMASK (0x7f) ++ ++#define S3C2410_SDIIMSK_RESPONSECRC (1<<17) ++#define S3C2410_SDIIMSK_CMDSENT (1<<16) ++#define S3C2410_SDIIMSK_CMDTIMEOUT (1<<15) ++#define S3C2410_SDIIMSK_RESPONSEND (1<<14) ++#define S3C2410_SDIIMSK_READWAIT (1<<13) ++#define S3C2410_SDIIMSK_SDIOIRQ (1<<12) ++#define S3C2410_SDIIMSK_FIFOFAIL (1<<11) ++#define S3C2410_SDIIMSK_CRCSTATUS (1<<10) ++#define S3C2410_SDIIMSK_DATACRC (1<<9) ++#define S3C2410_SDIIMSK_DATATIMEOUT (1<<8) ++#define S3C2410_SDIIMSK_DATAFINISH (1<<7) ++#define S3C2410_SDIIMSK_BUSYFINISH (1<<6) ++#define S3C2410_SDIIMSK_SBITERR (1<<5) /* reserved 2440/2410a */ ++#define S3C2410_SDIIMSK_TXFIFOHALF (1<<4) ++#define S3C2410_SDIIMSK_TXFIFOEMPTY (1<<3) ++#define S3C2410_SDIIMSK_RXFIFOLAST (1<<2) ++#define S3C2410_SDIIMSK_RXFIFOFULL (1<<1) ++#define S3C2410_SDIIMSK_RXFIFOHALF (1<<0) ++ ++#endif /* __ASM_ARM_REGS_SDI */ +Index: u-boot/include/s3c24x0.h +=================================================================== +--- u-boot.orig/include/s3c24x0.h ++++ u-boot/include/s3c24x0.h +@@ -637,13 +637,7 @@ + S3C24X0_REG32 SDIDCNT; + S3C24X0_REG32 SDIDSTA; + S3C24X0_REG32 SDIFSTA; +-#ifdef __BIG_ENDIAN +- S3C24X0_REG8 res[3]; +- S3C24X0_REG8 SDIDAT; +-#else +- S3C24X0_REG8 SDIDAT; +- S3C24X0_REG8 res[3]; +-#endif ++ S3C24X0_REG32 SDIDAT; + S3C24X0_REG32 SDIIMSK; + } /*__attribute__((__packed__))*/ S3C2410_SDI; + +@@ -1123,11 +1117,7 @@ + #define rSDIDatCnt (*(volatile unsigned *)0x5A000030) + #define rSDIDatSta (*(volatile unsigned *)0x5A000034) + #define rSDIFSTA (*(volatile unsigned *)0x5A000038) +-#ifdef __BIG_ENDIAN +-#define rSDIDAT (*(volatile unsigned char *)0x5A00003F) +-#else +-#define rSDIDAT (*(volatile unsigned char *)0x5A00003C) +-#endif ++#define rSDIDAT (*(volatile unsigned *)0x5A00003C) + #define rSDIIntMsk (*(volatile unsigned *)0x5A000040) + + #endif diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2410-nand.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2410-nand.patch new file mode 100644 index 0000000000..dc363bbbab --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2410-nand.patch @@ -0,0 +1,525 @@ +This patch adds NAND (including boot-from-NAND via steppingstone) support to +the S3C2410 SoC code in u-boot + +Signed-off-by: Harald Welte + +Index: u-boot/cpu/arm920t/s3c24x0/Makefile +=================================================================== +--- u-boot.orig/cpu/arm920t/s3c24x0/Makefile 2007-02-28 03:47:44.000000000 +0100 ++++ u-boot/cpu/arm920t/s3c24x0/Makefile 2007-03-01 14:29:32.000000000 +0100 +@@ -26,7 +26,7 @@ + LIB = $(obj)lib$(SOC).a + + COBJS = i2c.o interrupts.o serial.o speed.o \ +- usb_ohci.o ++ usb_ohci.o nand_read.o nand.o + + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) + OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +Index: u-boot/cpu/arm920t/s3c24x0/nand.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ u-boot/cpu/arm920t/s3c24x0/nand.c 2007-03-01 14:30:27.000000000 +0100 +@@ -0,0 +1,225 @@ ++/* ++ * (C) Copyright 2006 OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++ ++#if 0 ++#define DEBUGN printf ++#else ++#define DEBUGN(x, args ...) {} ++#endif ++ ++#if (CONFIG_COMMANDS & CFG_CMD_NAND) ++#if !defined(CFG_NAND_LEGACY) ++ ++#include ++#include ++ ++#define __REGb(x) (*(volatile unsigned char *)(x)) ++#define __REGi(x) (*(volatile unsigned int *)(x)) ++ ++#define NF_BASE 0x4e000000 ++#define NFCONF __REGi(NF_BASE + 0x0) ++#define NFCMD __REGb(NF_BASE + 0x4) ++#define NFADDR __REGb(NF_BASE + 0x8) ++#define NFDATA __REGb(NF_BASE + 0xc) ++#define NFSTAT __REGb(NF_BASE + 0x10) ++#define NFECC0 __REGb(NF_BASE + 0x14) ++#define NFECC1 __REGb(NF_BASE + 0x15) ++#define NFECC2 __REGb(NF_BASE + 0x16) ++ ++#define S3C2410_NFCONF_EN (1<<15) ++#define S3C2410_NFCONF_512BYTE (1<<14) ++#define S3C2410_NFCONF_4STEP (1<<13) ++#define S3C2410_NFCONF_INITECC (1<<12) ++#define S3C2410_NFCONF_nFCE (1<<11) ++#define S3C2410_NFCONF_TACLS(x) ((x)<<8) ++#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) ++#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0) ++ ++static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd) ++{ ++ struct nand_chip *chip = mtd->priv; ++ ++ DEBUGN("hwcontrol(): 0x%02x: ", cmd); ++ ++ switch (cmd) { ++ case NAND_CTL_SETNCE: ++ NFCONF &= ~S3C2410_NFCONF_nFCE; ++ DEBUGN("NFCONF=0x%08x\n", NFCONF); ++ break; ++ case NAND_CTL_CLRNCE: ++ NFCONF |= S3C2410_NFCONF_nFCE; ++ DEBUGN("NFCONF=0x%08x\n", NFCONF); ++ break; ++ case NAND_CTL_SETALE: ++ chip->IO_ADDR_W = NF_BASE + 0x8; ++ DEBUGN("SETALE\n"); ++ break; ++ case NAND_CTL_SETCLE: ++ chip->IO_ADDR_W = NF_BASE + 0x4; ++ DEBUGN("SETCLE\n"); ++ break; ++ default: ++ chip->IO_ADDR_W = NF_BASE + 0xc; ++ break; ++ } ++ return; ++} ++ ++static int s3c2410_dev_ready(struct mtd_info *mtd) ++{ ++ DEBUGN("dev_ready\n"); ++ return (NFSTAT & 0x01); ++} ++ ++static void s3c2410_cmdfunc(struct mtd_info *mtd, unsigned cmd, ++ int column, int page_addr) ++{ ++ DEBUGN("cmdfunc(): 0x%02x, col=%d, page=%d\n", cmd, column, page_addr); ++ ++ switch (cmd) { ++ case NAND_CMD_READ0: ++ case NAND_CMD_READ1: ++ case NAND_CMD_READOOB: ++ NFCMD = cmd; ++ NFADDR = column & 0xff; ++ NFADDR = page_addr & 0xff; ++ NFADDR = (page_addr >> 8) & 0xff; ++ NFADDR = (page_addr >> 16) & 0xff; ++ break; ++ case NAND_CMD_READID: ++ NFCMD = cmd; ++ NFADDR = 0; ++ break; ++ case NAND_CMD_PAGEPROG: ++ NFCMD = cmd; ++ printf("PAGEPROG not implemented\n"); ++ break; ++ case NAND_CMD_ERASE1: ++ NFCMD = cmd; ++ NFADDR = page_addr & 0xff; ++ NFADDR = (page_addr >> 8) & 0xff; ++ NFADDR = (page_addr >> 16) & 0xff; ++ break; ++ case NAND_CMD_ERASE2: ++ NFCMD = cmd; ++ break; ++ case NAND_CMD_SEQIN: ++ printf("SEQIN not implemented\n"); ++ break; ++ case NAND_CMD_STATUS: ++ NFCMD = cmd; ++ break; ++ case NAND_CMD_RESET: ++ NFCMD = cmd; ++ break; ++ default: ++ break; ++ } ++ ++ while (!s3c2410_dev_ready(mtd)); ++} ++ ++#ifdef CONFIG_S3C2410_NAND_HWECC ++void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) ++{ ++ DEBUGN("s3c2410_nand_enable_hwecc(%p, %d)\n", mtd ,mode); ++ NFCONF |= S3C2410_NFCONF_INITECC; ++} ++ ++static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) ++{ ++ ecc_code[0] = NFECC0; ++ ecc_code[1] = NFECC1; ++ ecc_code[2] = NFECC2; ++ DEBUGN("s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", mtd , ecc_code[0], ecc_code[1], ecc_code[2]); ++ ++ return 0; ++} ++ ++int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) ++{ ++ if (read_ecc[0] == calc_ecc[0] && ++ read_ecc[1] == calc_ecc[1] && ++ read_ecc[2] == calc_ecc[2]) ++ return 0; ++ ++ printf("s3c2410_nand_correct_data: not implemented\n"); ++ return -1; ++} ++#endif ++ ++int board_nand_init(struct nand_chip *nand) ++{ ++ u_int32_t cfg; ++ u_int8_t tacls, twrph0, twrph1; ++ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); ++ ++ DEBUGN("board_nand_init()\n"); ++ ++ clk_power->CLKCON |= (1 << 4); ++ ++ /* initialize hardware */ ++ twrph0 = 3; twrph1 = 0; tacls = 0; ++ ++ cfg = S3C2410_NFCONF_EN; ++ cfg |= S3C2410_NFCONF_TACLS(tacls - 1); ++ cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); ++ cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); ++ ++ NFCONF = cfg; ++ //NFCONF = 0xf842; ++ ++ /* initialize nand_chip data structure */ ++ nand->IO_ADDR_R = nand->IO_ADDR_W = 0x4e00000c; ++ ++ /* read_buf and write_buf are default */ ++ /* read_byte and write_byte are default */ ++ ++ /* hwcontrol always must be implemented */ ++ nand->hwcontrol = s3c2410_hwcontrol; ++ ++ nand->dev_ready = s3c2410_dev_ready; ++ ++#ifdef CONFIG_S3C2410_NAND_HWECC ++ nand->enable_hwecc = s3c2410_nand_enable_hwecc; ++ nand->calculate_ecc = s3c2410_nand_calculate_ecc; ++ nand->correct_data = s3c2410_nand_correct_data; ++ nand->eccmode = NAND_ECC_HW3_512; ++#else ++ nand->eccmode = NAND_ECC_SOFT; ++#endif ++ ++#ifdef CONFIG_S3C2410_NAND_BBT ++ nand->options = NAND_USE_FLASH_BBT; ++#else ++ nand->options = 0; ++#endif ++ ++ DEBUGN("end of nand_init\n"); ++ ++ return 0; ++} ++ ++#else ++ #error "U-Boot legacy NAND support not available for S3C2410" ++#endif ++#endif +Index: u-boot/cpu/arm920t/s3c24x0/nand_read.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ u-boot/cpu/arm920t/s3c24x0/nand_read.c 2007-02-28 03:51:24.000000000 +0100 +@@ -0,0 +1,98 @@ ++/* ++ * nand_read.c: Simple NAND read functions for booting from NAND ++ * ++ * This is used by cpu/arm920/start.S assembler code, ++ * and the board-specific linker script must make sure this ++ * file is linked within the first 4kB of NAND flash. ++ * ++ * Taken from GPLv2 licensed vivi bootloader, ++ * Copyright (C) 2002 MIZI Research, Inc. ++ * ++ * Author: Hwang, Chideok ++ * Date : $Date: 2004/02/04 10:37:37 $ ++ * ++ * u-boot integration and bad-block skipping (C) 2006 by OpenMoko, Inc. ++ * Author: Harald Welte ++ */ ++ ++#include ++ ++#ifdef CONFIG_S3C2410_NAND_BOOT ++ ++#define __REGb(x) (*(volatile unsigned char *)(x)) ++#define __REGi(x) (*(volatile unsigned int *)(x)) ++#define NF_BASE 0x4e000000 ++#define NFCONF __REGi(NF_BASE + 0x0) ++#define NFCMD __REGb(NF_BASE + 0x4) ++#define NFADDR __REGb(NF_BASE + 0x8) ++#define NFDATA __REGb(NF_BASE + 0xc) ++#define NFSTAT __REGb(NF_BASE + 0x10) ++ ++#define BUSY 1 ++inline void wait_idle(void) ++{ ++ int i; ++ ++ while (!(NFSTAT & BUSY)) ++ for (i=0; i<10; i++); ++} ++ ++#define NAND_SECTOR_SIZE 512 ++#define NAND_BLOCK_MASK (NAND_SECTOR_SIZE - 1) ++#define NAND_PAGE_SIZE 0x4000 ++ ++/* low level nand read function */ ++int nand_read_ll(unsigned char *buf, unsigned long start_addr, int size) ++{ ++ int i, j; ++ ++ if ((start_addr & NAND_BLOCK_MASK) || (size & NAND_BLOCK_MASK)) ++ return -1; /* invalid alignment */ ++ ++ /* chip Enable */ ++ NFCONF &= ~0x800; ++ for (i=0; i<10; i++); ++ ++ for (i=start_addr; i < (start_addr + size);) { ++#ifdef CONFIG_S3C2410_NAND_SKIP_BAD ++ if (start_addr % NAND_PAGE_SIZE == 0) { ++ unsigned char data; ++ NFCMD = 0x50; ++ NFADDR = 517&0xf; ++ NFADDR = (i >> 9) & 0xff; ++ NFADDR = (i >> 17) & 0xff; ++ NFADDR = (i >> 25) & 0xff; ++ wait_idle(); ++ data = (NFDATA & 0xff); ++ if (data != 0xff) { ++ /* Bad block */ ++ i += NAND_PAGE_SIZE; ++ size += NAND_PAGE_SIZE; ++ continue; ++ } ++ } ++#endif ++ /* READ0 */ ++ NFCMD = 0; ++ ++ /* Write Address */ ++ NFADDR = i & 0xff; ++ NFADDR = (i >> 9) & 0xff; ++ NFADDR = (i >> 17) & 0xff; ++ NFADDR = (i >> 25) & 0xff; ++ ++ wait_idle(); ++ ++ for (j=0; j < NAND_SECTOR_SIZE; j++, i++) { ++ *buf = (NFDATA & 0xff); ++ buf++; ++ } ++ } ++ ++ /* chip Disable */ ++ NFCONF |= 0x800; /* chip disable */ ++ ++ return 0; ++} ++ ++#endif /* CONFIG_S3C2410_NAND_BOOT */ +Index: u-boot/cpu/arm920t/start.S +=================================================================== +--- u-boot.orig/cpu/arm920t/start.S 2007-02-28 03:47:44.000000000 +0100 ++++ u-boot/cpu/arm920t/start.S 2007-03-01 14:29:22.000000000 +0100 +@@ -5,6 +5,10 @@ + * Copyright (c) 2002 Alex Züpke + * Copyright (c) 2002 Gary Jennejohn + * ++ * S3C2410 NAND portions ++ * Copyright (c) 2001 MIZI Research, Inc. ++ * Copyright (c) 2006 OpenMoko, Inc. (Harald Welte ++ * + * See file CREDITS for list of people who contributed to this + * project. + * +@@ -27,6 +31,7 @@ + + #include + #include ++#include + + + /* +@@ -161,6 +166,7 @@ + #endif + + #ifndef CONFIG_SKIP_RELOCATE_UBOOT ++#ifndef CONFIG_S3C2410_NAND_BOOT + relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ +@@ -177,6 +183,93 @@ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop ++#else /* NAND_BOOT */ ++relocate: ++copy_myself: ++ /* mov r10, lr */ ++ ++ @ reset NAND ++ mov r1, #S3C2410_NAND_BASE ++ ldr r2, =0xf842 @ initial value enable tacls=3,rph0=6,rph1=0 ++ str r2, [r1, #oNFCONF] ++ ldr r2, [r1, #oNFCONF] ++ bic r2, r2, #0x800 @ enable chip ++ str r2, [r1, #oNFCONF] ++ mov r2, #0xff @ RESET command ++ strb r2, [r1, #oNFCMD] ++ mov r3, #0 @ wait ++1: add r3, r3, #0x1 ++ cmp r3, #0xa ++ blt 1b ++2: ldr r2, [r1, #oNFSTAT] @ wait ready ++ tst r2, #0x1 ++ beq 2b ++ ldr r2, [r1, #oNFCONF] ++ orr r2, r2, #0x800 @ disable chip ++ str r2, [r1, #oNFCONF] ++ ++#if 0 ++ @ get ready to call C functions (for nand_read()) ++ ldr sp, DW_STACK_START @ setup stack pointer ++ mov fp, #0 @ no previous frame, so fp=0 ++#else ++ ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ ++ sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ ++ sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ ++#ifdef CONFIG_USE_IRQ ++ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) ++#endif ++ sub sp, r0, #12 /* leave 3 words for abort-stack */ ++#endif ++ ++ @ copy u-boot to RAM ++ ldr r0, _TEXT_BASE ++ mov r1, #0x0 ++ mov r2, #CFG_UBOOT_SIZE ++ bl nand_read_ll ++ ++ tst r0, #0x0 ++ beq ok_nand_read ++#ifdef CONFIG_DEBUG_LL ++bad_nand_read: ++ ldr r0, STR_FAIL ++ ldr r1, SerBase ++ bl PrintWord ++1: b 1b @ infinite loop ++#endif ++ ++ok_nand_read: ++#ifdef CONFIG_DEBUG_LL ++ ldr r0, STR_OK ++ ldr r1, SerBase ++ bl PrintWord ++#endif ++ ++ @ verify ++ mov r0, #0 ++ @ldr r1, =0x33f00000 ++ ldr r1, _TEXT_BASE ++ mov r2, #0x400 @ 4 bytes * 1024 = 4K-bytes ++go_next: ++ ldr r3, [r0], #4 ++ ldr r4, [r1], #4 ++ teq r3, r4 ++ bne notmatch ++ subs r2, r2, #4 ++ beq done_nand_read ++ bne go_next ++notmatch: ++#ifdef CONFIG_DEBUG_LL ++ sub r0, r0, #4 ++ ldr r1, SerBase ++ bl PrintHexWord ++ ldr r0, STR_FAIL ++ ldr r1, SerBase ++ bl PrintWord ++#endif ++1: b 1b ++done_nand_read: ++#endif /* NAND_BOOT */ + #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ + + /* Set up the stack */ +Index: u-boot/include/s3c2410.h +=================================================================== +--- u-boot.orig/include/s3c2410.h 2007-02-28 03:51:24.000000000 +0100 ++++ u-boot/include/s3c2410.h 2007-03-01 14:29:22.000000000 +0100 +@@ -38,12 +38,6 @@ + #define S3C2410_ECCSIZE 512 + #define S3C2410_ECCBYTES 3 + +-typedef enum { +- S3C24X0_UART0, +- S3C24X0_UART1, +- S3C24X0_UART2 +-} S3C24X0_UARTS_NR; +- + /* S3C2410 device base addresses */ + #define S3C24X0_MEMCTL_BASE 0x48000000 + #define S3C24X0_USB_HOST_BASE 0x49000000 +@@ -65,9 +59,23 @@ + #define S3C2410_SDI_BASE 0x5A000000 + + ++#define oNFCONF 0x00 ++#define oNFCMD 0x04 ++#define oNFADDR 0x08 ++#define oNFDATA 0x0C ++#define oNFSTAT 0x10 ++#define oNFECC 0x14 ++ ++#ifndef __ASSEMBLER__ ++ + /* include common stuff */ + #include + ++typedef enum { ++ S3C24X0_UART0, ++ S3C24X0_UART1, ++ S3C24X0_UART2 ++} S3C24X0_UARTS_NR; + + static inline S3C24X0_MEMCTL * S3C24X0_GetBase_MEMCTL(void) + { +@@ -142,6 +150,7 @@ + return (S3C2410_SDI * const)S3C2410_SDI_BASE; + } + ++#endif + + /* ISR */ + #define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0)) diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2410-norelocate_irqvec_cpy.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2410-norelocate_irqvec_cpy.patch new file mode 100644 index 0000000000..0d5a49771d --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2410-norelocate_irqvec_cpy.patch @@ -0,0 +1,32 @@ +If we've somehow magically make u-boot end up in RAM (JTAG, ...), then that RAM +is mapped to 0x30000000 and not 0, so we need to copy the interrupt vectors, etc. + +Index: u-boot/cpu/arm920t/start.S +=================================================================== +--- u-boot.orig/cpu/arm920t/start.S ++++ u-boot/cpu/arm920t/start.S +@@ -332,7 +332,23 @@ done_nand_read: + strb r1, [r0] + #endif /* CONFIG_S3C2410_NAND_BOOT */ + done_relocate: +-#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ ++ ++#if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C2410) ++ /* In the case of the S3C2410, if we've somehow magically (JTAG, ...) ++ ended up in RAM, then that ram is mapped to 0x30000000 and not 0. ++ So we need to copy the interrupt vectors, etc. */ ++ ++ mov r0, #0 ++ ldr r1, _TEXT_BASE ++ mov r2, #0x40 ++irqvec_cpy_next: ++ ldr r3, [r1], #4 ++ str r3, [r0], #4 ++ subs r2, r2, #4 ++ bne irqvec_cpy_next ++#endif /* CONFIG_USE_IRQ */ ++ ++#endif /* !CONFIG_SKIP_RELOCATE_UBOOT */ + + /* Set up the stack */ + stack_setup: diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2410-warnings-fix.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2410-warnings-fix.patch new file mode 100644 index 0000000000..8cc442a865 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2410-warnings-fix.patch @@ -0,0 +1,98 @@ +Index: u-boot/include/s3c2410.h +=================================================================== +--- u-boot.orig/include/s3c2410.h 2007-02-16 23:53:20.000000000 +0100 ++++ u-boot/include/s3c2410.h 2007-02-16 23:53:21.000000000 +0100 +@@ -69,75 +69,75 @@ + #include + + +-static inline S3C24X0_MEMCTL * const S3C24X0_GetBase_MEMCTL(void) ++static inline S3C24X0_MEMCTL * S3C24X0_GetBase_MEMCTL(void) + { + return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE; + } +-static inline S3C24X0_USB_HOST * const S3C24X0_GetBase_USB_HOST(void) ++static inline S3C24X0_USB_HOST * S3C24X0_GetBase_USB_HOST(void) + { + return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE; + } +-static inline S3C24X0_INTERRUPT * const S3C24X0_GetBase_INTERRUPT(void) ++static inline S3C24X0_INTERRUPT * S3C24X0_GetBase_INTERRUPT(void) + { + return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE; + } +-static inline S3C24X0_DMAS * const S3C24X0_GetBase_DMAS(void) ++static inline S3C24X0_DMAS * S3C24X0_GetBase_DMAS(void) + { + return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE; + } +-static inline S3C24X0_CLOCK_POWER * const S3C24X0_GetBase_CLOCK_POWER(void) ++static inline S3C24X0_CLOCK_POWER * S3C24X0_GetBase_CLOCK_POWER(void) + { + return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE; + } +-static inline S3C24X0_LCD * const S3C24X0_GetBase_LCD(void) ++static inline S3C24X0_LCD * S3C24X0_GetBase_LCD(void) + { + return (S3C24X0_LCD * const)S3C24X0_LCD_BASE; + } +-static inline S3C2410_NAND * const S3C2410_GetBase_NAND(void) ++static inline S3C2410_NAND * S3C2410_GetBase_NAND(void) + { + return (S3C2410_NAND * const)S3C2410_NAND_BASE; + } +-static inline S3C24X0_UART * const S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr) ++static inline S3C24X0_UART * S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr) + { + return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000)); + } +-static inline S3C24X0_TIMERS * const S3C24X0_GetBase_TIMERS(void) ++static inline S3C24X0_TIMERS * S3C24X0_GetBase_TIMERS(void) + { + return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE; + } +-static inline S3C24X0_USB_DEVICE * const S3C24X0_GetBase_USB_DEVICE(void) ++static inline S3C24X0_USB_DEVICE * S3C24X0_GetBase_USB_DEVICE(void) + { + return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE; + } +-static inline S3C24X0_WATCHDOG * const S3C24X0_GetBase_WATCHDOG(void) ++static inline S3C24X0_WATCHDOG * S3C24X0_GetBase_WATCHDOG(void) + { + return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE; + } +-static inline S3C24X0_I2C * const S3C24X0_GetBase_I2C(void) ++static inline S3C24X0_I2C * S3C24X0_GetBase_I2C(void) + { + return (S3C24X0_I2C * const)S3C24X0_I2C_BASE; + } +-static inline S3C24X0_I2S * const S3C24X0_GetBase_I2S(void) ++static inline S3C24X0_I2S * S3C24X0_GetBase_I2S(void) + { + return (S3C24X0_I2S * const)S3C24X0_I2S_BASE; + } +-static inline S3C24X0_GPIO * const S3C24X0_GetBase_GPIO(void) ++static inline S3C24X0_GPIO * S3C24X0_GetBase_GPIO(void) + { + return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE; + } +-static inline S3C24X0_RTC * const S3C24X0_GetBase_RTC(void) ++static inline S3C24X0_RTC * S3C24X0_GetBase_RTC(void) + { + return (S3C24X0_RTC * const)S3C24X0_RTC_BASE; + } +-static inline S3C2410_ADC * const S3C2410_GetBase_ADC(void) ++static inline S3C2410_ADC * S3C2410_GetBase_ADC(void) + { + return (S3C2410_ADC * const)S3C2410_ADC_BASE; + } +-static inline S3C24X0_SPI * const S3C24X0_GetBase_SPI(void) ++static inline S3C24X0_SPI * S3C24X0_GetBase_SPI(void) + { + return (S3C24X0_SPI * const)S3C24X0_SPI_BASE; + } +-static inline S3C2410_SDI * const S3C2410_GetBase_SDI(void) ++static inline S3C2410_SDI * S3C2410_GetBase_SDI(void) + { + return (S3C2410_SDI * const)S3C2410_SDI_BASE; + } diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2410_fb.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2410_fb.patch new file mode 100644 index 0000000000..b50853554b --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2410_fb.patch @@ -0,0 +1,215 @@ +Index: u-boot/drivers/Makefile +=================================================================== +--- u-boot.orig/drivers/Makefile ++++ u-boot/drivers/Makefile +@@ -52,7 +52,7 @@ + ks8695eth.o \ + pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \ + rpx_pcmcia.o \ +- fsl_i2c.o ++ fsl_i2c.o s3c2410_fb.o + + SRCS := $(COBJS:.o=.c) + OBJS := $(addprefix $(obj),$(COBJS)) +Index: u-boot/drivers/s3c2410_fb.c +=================================================================== +--- /dev/null ++++ u-boot/drivers/s3c2410_fb.c +@@ -0,0 +1,166 @@ ++/* ++ * (C) Copyright 2006 by OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++ ++#if defined(CONFIG_VIDEO_S3C2410) ++ ++#include ++#include "videomodes.h" ++#include ++/* ++ * Export Graphic Device ++ */ ++GraphicDevice smi; ++ ++#define VIDEO_MEM_SIZE 0x200000 /* 480x640x16bit = 614400 bytes */ ++ ++extern void board_video_init(GraphicDevice *pGD); ++ ++/******************************************************************************* ++ * ++ * Init video chip with common Linux graphic modes (lilo) ++ */ ++void *video_hw_init (void) ++{ ++ S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD(); ++ GraphicDevice *pGD = (GraphicDevice *)&smi; ++ int videomode; ++ unsigned long t1, hsynch, vsynch; ++ char *penv; ++ int tmp, i, bits_per_pixel; ++ struct ctfb_res_modes *res_mode; ++ struct ctfb_res_modes var_mode; ++ unsigned char videoout; ++ ++ /* Search for video chip */ ++ printf("Video: "); ++ ++ tmp = 0; ++ ++ videomode = CFG_DEFAULT_VIDEO_MODE; ++ /* get video mode via environment */ ++ if ((penv = getenv ("videomode")) != NULL) { ++ /* deceide if it is a string */ ++ if (penv[0] <= '9') { ++ videomode = (int) simple_strtoul (penv, NULL, 16); ++ tmp = 1; ++ } ++ } else { ++ tmp = 1; ++ } ++ if (tmp) { ++ /* parameter are vesa modes */ ++ /* search params */ ++ for (i = 0; i < VESA_MODES_COUNT; i++) { ++ if (vesa_modes[i].vesanr == videomode) ++ break; ++ } ++ if (i == VESA_MODES_COUNT) { ++ printf ("no VESA Mode found, switching to mode 0x%x ", CFG_DEFAULT_VIDEO_MODE); ++ i = 0; ++ } ++ res_mode = ++ (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i]. ++ resindex]; ++ bits_per_pixel = vesa_modes[i].bits_per_pixel; ++ } else { ++ ++ res_mode = (struct ctfb_res_modes *) &var_mode; ++ bits_per_pixel = video_get_params (res_mode, penv); ++ } ++ ++ /* calculate hsynch and vsynch freq (info only) */ ++ t1 = (res_mode->left_margin + res_mode->xres + ++ res_mode->right_margin + res_mode->hsync_len) / 8; ++ t1 *= 8; ++ t1 *= res_mode->pixclock; ++ t1 /= 1000; ++ hsynch = 1000000000L / t1; ++ t1 *= ++ (res_mode->upper_margin + res_mode->yres + ++ res_mode->lower_margin + res_mode->vsync_len); ++ t1 /= 1000; ++ vsynch = 1000000000L / t1; ++ ++ /* fill in Graphic device struct */ ++ sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, ++ res_mode->yres, bits_per_pixel, (hsynch / 1000), ++ (vsynch / 1000)); ++ printf ("%s\n", pGD->modeIdent); ++ pGD->winSizeX = res_mode->xres; ++ pGD->winSizeY = res_mode->yres; ++ pGD->plnSizeX = res_mode->xres; ++ pGD->plnSizeY = res_mode->yres; ++ switch (bits_per_pixel) { ++ case 8: ++ pGD->gdfBytesPP = 1; ++ pGD->gdfIndex = GDF__8BIT_INDEX; ++ break; ++ case 15: ++ pGD->gdfBytesPP = 2; ++ pGD->gdfIndex = GDF_15BIT_555RGB; ++ break; ++ case 16: ++ pGD->gdfBytesPP = 2; ++ pGD->gdfIndex = GDF_16BIT_565RGB; ++ break; ++ case 24: ++ pGD->gdfBytesPP = 3; ++ pGD->gdfIndex = GDF_24BIT_888RGB; ++ break; ++ } ++ ++ /* statically configure settings */ ++ pGD->winSizeX = pGD->plnSizeX = 480; ++ pGD->winSizeY = pGD->plnSizeY = 640; ++ pGD->gdfBytesPP = 2; ++ pGD->gdfIndex = GDF_16BIT_565RGB; ++ ++ pGD->frameAdrs = LCD_VIDEO_ADDR; ++ pGD->memSize = VIDEO_MEM_SIZE; ++ ++ board_video_init(pGD); ++ ++ lcd->LCDSADDR1 = pGD->frameAdrs >> 1; ++ ++ /* This marks the end of the frame buffer. */ ++ lcd->LCDSADDR2 = (lcd->LCDSADDR1&0x1fffff) + (pGD->winSizeX+0) * pGD->winSizeY; ++ lcd->LCDSADDR3 = pGD->winSizeX; ++ ++ /* Clear video memory */ ++ memset(pGD->frameAdrs, 0, pGD->memSize); ++ ++ /* Enable Display */ ++ lcd->LCDCON1 |= 0x01; /* ENVID = 1 */ ++ ++ return ((void*)&smi); ++} ++ ++void ++video_set_lut (unsigned int index, /* color number */ ++ unsigned char r, /* red */ ++ unsigned char g, /* green */ ++ unsigned char b /* blue */ ++ ) ++{ ++} ++ ++#endif /* CONFIG_VIDEO_S3C2410 */ +Index: u-boot/drivers/cfb_console.c +=================================================================== +--- u-boot.orig/drivers/cfb_console.c ++++ u-boot/drivers/cfb_console.c +@@ -141,6 +141,14 @@ + #endif + + /*****************************************************************************/ ++/* Defines for the S3C2410 driver */ ++/*****************************************************************************/ ++#ifdef CONFIG_VIDEO_S3C2410 ++/* it actually is little-endian, but the host CPU, too ! */ ++//#define VIDEO_FB_LITTLE_ENDIAN ++#endif ++ ++/*****************************************************************************/ + /* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc */ + /*****************************************************************************/ + #include +@@ -307,6 +315,11 @@ + #define SHORTSWAP32(x) (x) + #endif + ++#ifdef CONFIG_VIDEO_S3C2410 ++#undef SHORTSWAP32 ++#define SHORTSWAP32(x) ((((x) & 0xffff) << 16) | (((x) >> 16) & 0xffff)) ++#endif ++ + #if defined(DEBUG) || defined(DEBUG_CFB_CONSOLE) + #define PRINTD(x) printf(x) + #else diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2410_udc.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2410_udc.patch new file mode 100644 index 0000000000..16bee3e26a --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2410_udc.patch @@ -0,0 +1,1263 @@ +USB Device Controller Driver for Samsung S3C2410 SoC + +Index: u-boot/drivers/Makefile +=================================================================== +--- u-boot.orig/drivers/Makefile ++++ u-boot/drivers/Makefile +@@ -47,7 +47,7 @@ + status_led.o sym53c8xx.o systemace.o ahci.o \ + ti_pci1410a.o tigon3.o tsec.o \ + tsi108_eth.o tsi108_i2c.o tsi108_pci.o \ +- usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \ ++ usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbdcore_s3c2410.o usbtty.o \ + videomodes.o w83c553f.o \ + ks8695eth.o \ + pcf50606.o \ +Index: u-boot/drivers/usbdcore_s3c2410.c +=================================================================== +--- /dev/null ++++ u-boot/drivers/usbdcore_s3c2410.c +@@ -0,0 +1,730 @@ ++/* S3C2410 USB Device Controller Driver for u-boot ++ * ++ * (C) Copyright 2007 by OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * based on Linux' s3c2410_udc.c, which is ++ * Copyright (C) 2004-2006 Herbert Pötzl - Arnaud Patard ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#include ++ ++#if defined(CONFIG_S3C2410) && defined(CONFIG_USB_DEVICE) ++ ++#include ++ ++/* we can't use the regular debug macros since the console might be ++ * set to usbtty, which would cause deadlocks! */ ++#ifdef DEBUG ++#undef debug ++#undef debugX ++#define debug(fmt,args...) serial_printf (fmt ,##args) ++#define debugX(level,fmt,args...) if (DEBUG>=level) serial_printf(fmt,##args) ++#endif ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#include ++#include ++ ++#include "usbdcore.h" ++#include "usbdcore_s3c2410.h" ++#include "usbdcore_ep0.h" ++#include ++ ++enum ep0_state { ++ EP0_IDLE, ++ EP0_IN_DATA_PHASE, ++ EP0_OUT_DATA_PHASE, ++ EP0_END_XFER, ++ EP0_STALL, ++}; ++ ++static struct urb *ep0_urb = NULL; ++ ++static struct usb_device_instance *udc_device; /* Used in interrupt handler */ ++ ++static inline int fifo_count_out(void) ++{ ++ int tmp; ++ ++ tmp = inl(S3C2410_UDC_OUT_FIFO_CNT2_REG) << 8; ++ tmp |= inl(S3C2410_UDC_OUT_FIFO_CNT1_REG); ++ ++ return tmp & 0xffff; ++} ++ ++static const unsigned long ep_fifo_reg[S3C2410_UDC_NUM_ENDPOINTS] = { ++ S3C2410_UDC_EP0_FIFO_REG, ++ S3C2410_UDC_EP1_FIFO_REG, ++ S3C2410_UDC_EP2_FIFO_REG, ++ S3C2410_UDC_EP3_FIFO_REG, ++ S3C2410_UDC_EP4_FIFO_REG, ++}; ++ ++static int s3c2410_write_noniso_tx_fifo(struct usb_endpoint_instance *endpoint) ++{ ++ struct urb *urb = endpoint->tx_urb; ++ unsigned int last, i; ++ unsigned int ep = endpoint->endpoint_address & 0x7f; ++ unsigned long fifo_reg = ep_fifo_reg[ep]; ++ ++ /* WARNING: don't ever put serial debug printf's in non-error codepaths ++ * here, it is called from the time critical EP0 codepath ! */ ++ ++ if (!urb || ep >= S3C2410_UDC_NUM_ENDPOINTS) { ++ serial_printf("no urb or wrong endpoint\n"); ++ return -1; ++ } ++ ++ S3C2410_UDC_SETIX(ep); ++ if ((last = MIN(urb->actual_length - endpoint->sent, ++ endpoint->tx_packetSize))) { ++ u8 *cp = urb->buffer + endpoint->sent; ++ ++ for (i = 0; i < last; i++) ++ outb(*(cp+i), fifo_reg); ++ } ++ endpoint->last = last; ++ ++ if (endpoint->sent + last < urb->actual_length) { ++ /* not all data has been transmitted so far */ ++ return 0; ++ } ++ ++ if (last == endpoint->tx_packetSize) { ++ /* we need to send one more packet (ZLP) */ ++ return 0; ++ } ++ ++ return 1; ++} ++ ++ ++static void s3c2410_deconfigure_device (void) ++{ ++ /* FIXME: Implement this */ ++} ++ ++static void s3c2410_configure_device (struct usb_device_instance *device) ++{ ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ S3C24X0_CLOCK_POWER * const cpower = S3C24X0_GetBase_CLOCK_POWER(); ++ ++ /* disable EP0-4 SUBD interrupts ? */ ++ outl(0x00, S3C2410_UDC_USB_INT_EN_REG); ++ ++ /* UPLL already configured by board-level init code */ ++ ++ /* configure USB pads to device mode */ ++ gpio->MISCCR &= ~(S3C2410_MISCCR_USBHOST|S3C2410_MISCCR_USBSUSPND1); ++ ++ /* don't disable USB clock */ ++ cpower->CLKSLOW &= ~S3C2410_CLKSLOW_UCLK_OFF; ++ ++ /* clear interrupt registers */ ++ inl(S3C2410_UDC_EP_INT_REG); ++ inl(S3C2410_UDC_USB_INT_REG); ++ outl(0xff, S3C2410_UDC_EP_INT_REG); ++ outl(0xff, S3C2410_UDC_USB_INT_REG); ++ ++ /* enable USB interrupts for RESET and SUSPEND/RESUME */ ++ outl(S3C2410_UDC_USBINT_RESET|S3C2410_UDC_USBINT_SUSPEND, ++ S3C2410_UDC_USB_INT_EN_REG); ++} ++ ++static void udc_set_address(unsigned char address) ++{ ++ address |= 0x80; /* ADDR_UPDATE bit */ ++ outl(address, S3C2410_UDC_FUNC_ADDR_REG); ++} ++ ++extern struct usb_device_descriptor device_descriptor; ++ ++static void s3c2410_udc_ep0(void) ++{ ++ u_int8_t ep0csr; ++ struct usb_endpoint_instance *ep0 = udc_device->bus->endpoint_array; ++ ++ S3C2410_UDC_SETIX(0); ++ ep0csr = inl(S3C2410_UDC_IN_CSR1_REG); ++ ++ /* clear stall status */ ++ if (ep0csr & S3C2410_UDC_EP0_CSR_SENTSTL) { ++ serial_printf("Clearing SENT_STALL\n"); ++ clear_ep0_sst(); ++ if (ep0csr & S3C2410_UDC_EP0_CSR_SOPKTRDY) ++ clear_ep0_opr(); ++ ep0->state = EP0_IDLE; ++ return; ++ } ++ ++ /* clear setup end */ ++ if (ep0csr & S3C2410_UDC_EP0_CSR_SE ++ /* && ep0->state != EP0_IDLE */) { ++ serial_printf("Clearing SETUP_END\n"); ++ clear_ep0_se(); ++#if 1 ++ if (ep0csr & S3C2410_UDC_EP0_CSR_SOPKTRDY) { ++ /* Flush FIFO */ ++ while (inl(S3C2410_UDC_OUT_FIFO_CNT1_REG)) ++ inl(S3C2410_UDC_EP0_FIFO_REG); ++ clear_ep0_opr(); ++ } ++#endif ++ ep0->state = EP0_IDLE; ++ return; ++ } ++ ++ /* Don't ever put [serial] debugging in non-error codepaths here, it ++ * will violate the tight timing constraints of this USB Device ++ * controller (and lead to bus enumeration failures) */ ++ ++ switch (ep0->state) { ++ int i, fifo_count; ++ unsigned char *datap; ++ case EP0_IDLE: ++ if (!(ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY)) ++ break; ++ ++ datap = (unsigned char *) &ep0_urb->device_request; ++ /* host->device packet has been received */ ++ ++ /* pull it out of the fifo */ ++ fifo_count = fifo_count_out(); ++ for (i = 0; i < fifo_count; i++) { ++ *datap = (unsigned char)inl(S3C2410_UDC_EP0_FIFO_REG); ++ datap++; ++ } ++ if (fifo_count != 8) { ++ debug("STRANGE FIFO COUNT: %u bytes\n", fifo_count); ++ set_ep0_ss(); ++ return; ++ } ++ ++ if (ep0_urb->device_request.wLength == 0) { ++ if (ep0_recv_setup(ep0_urb)) { ++ /* Not a setup packet, stall next EP0 transaction */ ++ debug("can't parse setup packet1\n"); ++ set_ep0_ss(); ++ set_ep0_de_out(); ++ ep0->state = EP0_IDLE; ++ return; ++ } ++ /* There are some requests with which we need to deal ++ * manually here */ ++ switch (ep0_urb->device_request.bRequest) { ++ case USB_REQ_SET_CONFIGURATION: ++ if (!ep0_urb->device_request.wValue) ++ usbd_device_event_irq(udc_device, ++ DEVICE_DE_CONFIGURED, 0); ++ else ++ usbd_device_event_irq(udc_device, ++ DEVICE_CONFIGURED, 0); ++ break; ++ case USB_REQ_SET_ADDRESS: ++ udc_set_address(udc_device->address); ++ usbd_device_event_irq(udc_device, ++ DEVICE_ADDRESS_ASSIGNED, 0); ++ break; ++ default: ++ break; ++ } ++ set_ep0_de_out(); ++ ep0->state = EP0_IDLE; ++ } else { ++ if ((ep0_urb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK) ++ == USB_REQ_HOST2DEVICE) { ++ clear_ep0_opr(); ++ ep0->state = EP0_OUT_DATA_PHASE; ++ ep0_urb->buffer = ep0_urb->buffer_data; ++ ep0_urb->buffer_length = sizeof(ep0_urb->buffer_data); ++ ep0_urb->actual_length = 0; ++ } else { ++ ep0->state = EP0_IN_DATA_PHASE; ++ ++ if (ep0_recv_setup(ep0_urb)) { ++ /* Not a setup packet, stall next EP0 transaction */ ++ debug("can't parse setup packet2\n"); ++ set_ep0_ss(); ++ //set_ep0_de_out(); ++ ep0->state = EP0_IDLE; ++ return; ++ } ++ clear_ep0_opr(); ++ ep0->tx_urb = ep0_urb; ++ ep0->sent = ep0->last = 0; ++ ++ if (s3c2410_write_noniso_tx_fifo(ep0)) { ++ ep0->state = EP0_IDLE; ++ set_ep0_de_in(); ++ } else ++ set_ep0_ipr(); ++ } ++ } ++ break; ++ case EP0_IN_DATA_PHASE: ++ if (!(ep0csr & S3C2410_UDC_EP0_CSR_IPKRDY)) { ++ ep0->sent += ep0->last; ++ ++ if (s3c2410_write_noniso_tx_fifo(ep0)) { ++ ep0->state = EP0_IDLE; ++ set_ep0_de_in(); ++ } else ++ set_ep0_ipr(); ++ } ++ break; ++ case EP0_OUT_DATA_PHASE: ++ if (ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY) { ++ u32 urb_avail = ep0_urb->buffer_length - ep0_urb->actual_length; ++ u_int8_t *cp = ep0_urb->buffer + ep0_urb->actual_length; ++ int i, fifo_count; ++ ++ fifo_count = fifo_count_out(); ++ if (fifo_count < urb_avail) ++ urb_avail = fifo_count; ++ ++ for (i = 0; i < urb_avail; i++) ++ *cp++ = inl(S3C2410_UDC_EP0_FIFO_REG); ++ ++ ep0_urb->actual_length += urb_avail; ++ ++ if (fifo_count < ep0->rcv_packetSize || ++ ep0_urb->actual_length >= ep0_urb->device_request.wLength) { ++ ep0->state = EP0_IDLE; ++ if (ep0_recv_setup(ep0_urb)) { ++ /* Not a setup packet, stall next EP0 transaction */ ++ debug("can't parse setup packet3\n"); ++ set_ep0_ss(); ++ //set_ep0_de_out(); ++ return; ++ } ++ set_ep0_de_out(); ++ } else ++ clear_ep0_opr(); ++ } ++ break; ++ case EP0_END_XFER: ++ ep0->state = EP0_IDLE; ++ break; ++ case EP0_STALL: ++ //set_ep0_ss; ++ ep0->state = EP0_IDLE; ++ break; ++ } ++} ++ ++ ++static void s3c2410_udc_epn(int ep) ++{ ++ struct usb_endpoint_instance *endpoint; ++ struct urb *urb; ++ u32 ep_csr1; ++ ++ if (ep >= S3C2410_UDC_NUM_ENDPOINTS) ++ return; ++ ++ endpoint = &udc_device->bus->endpoint_array[ep]; ++ ++ S3C2410_UDC_SETIX(ep); ++ ++ if (endpoint->endpoint_address & USB_DIR_IN) { ++ /* IN transfer (device to host) */ ++ ep_csr1 = inl(S3C2410_UDC_IN_CSR1_REG); ++ debug("for ep=%u, CSR1=0x%x ", ep, ep_csr1); ++ ++ urb = endpoint->tx_urb; ++ if (ep_csr1 & S3C2410_UDC_ICSR1_SENTSTL) { ++ /* Stall handshake */ ++ debug("stall\n"); ++ outl(0x00, S3C2410_UDC_IN_CSR1_REG); ++ return; ++ } ++ if (!(ep_csr1 & S3C2410_UDC_ICSR1_PKTRDY) && urb && ++ urb->actual_length) { ++ ++ debug("completing previously send data "); ++ usbd_tx_complete(endpoint); ++ ++ /* push pending data into FIFO */ ++ if ((endpoint->last == endpoint->tx_packetSize) && ++ (urb->actual_length - endpoint->sent - endpoint->last == 0)) { ++ endpoint->sent += endpoint->last; ++ /* Write 0 bytes of data (ZLP) */ ++ debug("ZLP "); ++ outl(ep_csr1|S3C2410_UDC_ICSR1_PKTRDY, S3C2410_UDC_IN_CSR1_REG); ++ } else { ++ /* write actual data to fifo */ ++ debug("TX_DATA "); ++ s3c2410_write_noniso_tx_fifo(endpoint); ++ outl(ep_csr1|S3C2410_UDC_ICSR1_PKTRDY, S3C2410_UDC_IN_CSR1_REG); ++ } ++ } ++ debug("\n"); ++ } else { ++ /* OUT transfer (host to device) */ ++ ep_csr1 = inl(S3C2410_UDC_OUT_CSR1_REG); ++ debug("for ep=%u, CSR1=0x%x ", ep, ep_csr1); ++ ++ urb = endpoint->rcv_urb; ++ if (ep_csr1 & S3C2410_UDC_OCSR1_SENTSTL) { ++ /* Stall handshake */ ++ outl(0x00, S3C2410_UDC_IN_CSR1_REG); ++ return; ++ } ++ if ((ep_csr1 & S3C2410_UDC_OCSR1_PKTRDY) && urb) { ++ /* Read pending data from fifo */ ++ u32 fifo_count = fifo_count_out(); ++ int is_last = 0; ++ u32 i, urb_avail = urb->buffer_length - urb->actual_length; ++ u8 *cp = urb->buffer + urb->actual_length; ++ ++ if (fifo_count < endpoint->rcv_packetSize) ++ is_last = 1; ++ ++ debug("fifo_count=%u is_last=%, urb_avail=%u)\n", ++ fifo_count, is_last, urb_avail); ++ ++ if (fifo_count < urb_avail) ++ urb_avail = fifo_count; ++ ++ for (i = 0; i < urb_avail; i++) ++ *cp++ = inb(ep_fifo_reg[ep]); ++ ++ if (is_last) ++ outl(ep_csr1 & ~S3C2410_UDC_OCSR1_PKTRDY, ++ S3C2410_UDC_OUT_CSR1_REG); ++ ++ usbd_rcv_complete(endpoint, urb_avail, 0); ++ } ++ } ++ ++ urb = endpoint->rcv_urb; ++} ++ ++/* ++------------------------------------------------------------------------------- ++*/ ++ ++/* this is just an empty wrapper for usbtty who assumes polling operation */ ++void udc_irq(void) ++{ ++} ++ ++/* Handle general USB interrupts and dispatch according to type. ++ * This function implements TRM Figure 14-13. ++ */ ++void s3c2410_udc_irq(void) ++{ ++ struct usb_endpoint_instance *ep0 = udc_device->bus->endpoint_array; ++ u_int32_t save_idx = inl(S3C2410_UDC_INDEX_REG); ++ ++ /* read interrupt sources */ ++ u_int32_t usb_status = inl(S3C2410_UDC_USB_INT_REG); ++ u_int32_t usbd_status = inl(S3C2410_UDC_EP_INT_REG); ++ ++ //debug("< IRQ usbs=0x%02x, usbds=0x%02x start >", usb_status, usbd_status); ++ ++ /* clear interrupts */ ++ outl(usb_status, S3C2410_UDC_USB_INT_REG); ++ ++ if (usb_status & S3C2410_UDC_USBINT_RESET) { ++ //serial_putc('R'); ++ debug("RESET pwr=0x%x\n", inl(S3C2410_UDC_PWR_REG)); ++ udc_setup_ep(udc_device, 0, ep0); ++ outl(S3C2410_UDC_EP0_CSR_SSE|S3C2410_UDC_EP0_CSR_SOPKTRDY, S3C2410_UDC_EP0_CSR_REG); ++ ep0->state = EP0_IDLE; ++ usbd_device_event_irq (udc_device, DEVICE_RESET, 0); ++ } ++ ++ if (usb_status & S3C2410_UDC_USBINT_RESUME) { ++ debug("RESUME\n"); ++ usbd_device_event_irq(udc_device, DEVICE_BUS_ACTIVITY, 0); ++ } ++ ++ if (usb_status & S3C2410_UDC_USBINT_SUSPEND) { ++ debug("SUSPEND\n"); ++ usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0); ++ } ++ ++ /* Endpoint Interrupts */ ++ if (usbd_status) { ++ int i; ++ ++ if (usbd_status & S3C2410_UDC_INT_EP0) { ++ outl(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_REG); ++ s3c2410_udc_ep0(); ++ } ++ ++ for (i = 1; i < 5; i++) { ++ u_int32_t tmp = 1 << i; ++ ++ if (usbd_status & tmp) { ++ /* FIXME: Handle EP X */ ++ outl(tmp, S3C2410_UDC_EP_INT_REG); ++ s3c2410_udc_epn(i); ++ } ++ } ++ } ++ S3C2410_UDC_SETIX(save_idx); ++} ++ ++/* ++------------------------------------------------------------------------------- ++*/ ++ ++ ++/* ++ * Start of public functions. ++ */ ++ ++/* Called to start packet transmission. */ ++void udc_endpoint_write (struct usb_endpoint_instance *endpoint) ++{ ++ unsigned short epnum = ++ endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK; ++ ++ debug("Entering for ep %x ", epnum); ++ ++ if (endpoint->tx_urb) { ++ u32 ep_csr1; ++ debug("We have an URB, transmitting\n"); ++ ++ s3c2410_write_noniso_tx_fifo(endpoint); ++ ++ S3C2410_UDC_SETIX(epnum); ++ ++ ep_csr1 = inl(S3C2410_UDC_IN_CSR1_REG); ++ outl(ep_csr1|S3C2410_UDC_ICSR1_PKTRDY, S3C2410_UDC_IN_CSR1_REG); ++ } else ++ debug("\n"); ++} ++ ++/* Start to initialize h/w stuff */ ++int udc_init (void) ++{ ++ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); ++ S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT(); ++ ++ udc_device = NULL; ++ ++ /* Set and check clock control. ++ * We might ought to be using the clock control API to do ++ * this instead of fiddling with the clock registers directly ++ * here. ++ */ ++ clk_power->CLKCON |= (1 << 7); ++ ++ /* Print banner with device revision */ ++ printf("USB: S3C2410 USB Deviced\n"); ++ ++ /* ++ * At this point, device is ready for configuration... ++ */ ++ outl(0x00, S3C2410_UDC_EP_INT_EN_REG); ++ outl(0x00, S3C2410_UDC_USB_INT_EN_REG); ++ ++ irq->INTMSK &= ~BIT_USBD; ++ ++ return 0; ++} ++ ++/* ++ * udc_setup_ep - setup endpoint ++ * ++ * Associate a physical endpoint with endpoint_instance ++ */ ++int udc_setup_ep (struct usb_device_instance *device, ++ unsigned int ep, struct usb_endpoint_instance *endpoint) ++{ ++ int ep_addr = endpoint->endpoint_address; ++ int packet_size; ++ int attributes; ++ u_int32_t maxp; ++ ++ S3C2410_UDC_SETIX(ep); ++ ++ if (ep) { ++ if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { ++ /* IN endpoint */ ++ outl(S3C2410_UDC_ICSR1_FFLUSH|S3C2410_UDC_ICSR1_CLRDT, ++ S3C2410_UDC_IN_CSR1_REG); ++ outl(S3C2410_UDC_ICSR2_MODEIN, S3C2410_UDC_IN_CSR2_REG); ++ packet_size = endpoint->tx_packetSize; ++ attributes = endpoint->tx_attributes; ++ } else { ++ /* OUT endpoint */ ++ outl(S3C2410_UDC_ICSR1_CLRDT, S3C2410_UDC_IN_CSR1_REG); ++ outl(0, S3C2410_UDC_IN_CSR2_REG); ++ outl(S3C2410_UDC_OCSR1_FFLUSH|S3C2410_UDC_OCSR1_CLRDT, ++ S3C2410_UDC_OUT_CSR1_REG); ++ outl(0, S3C2410_UDC_OUT_CSR2_REG); ++ packet_size = endpoint->rcv_packetSize; ++ attributes = endpoint->rcv_attributes; ++ } ++ } else ++ packet_size = endpoint->tx_packetSize; ++ ++ switch (packet_size) { ++ case 8: ++ maxp = S3C2410_UDC_MAXP_8; ++ break; ++ case 16: ++ maxp = S3C2410_UDC_MAXP_16; ++ break; ++ case 32: ++ maxp = S3C2410_UDC_MAXP_32; ++ break; ++ case 64: ++ maxp = S3C2410_UDC_MAXP_64; ++ break; ++ default: ++ debug("invalid packet size %u\n", packet_size); ++ return -1; ++ } ++ ++ debug("setting up endpoint %u addr %x packet_size %u maxp %u\n", ep, ++ endpoint->endpoint_address, packet_size, maxp); ++ ++ /* Set maximum packet size */ ++ writel(maxp, S3C2410_UDC_MAXP_REG); ++ ++ return 0; ++} ++ ++/* ************************************************************************** */ ++ ++/** ++ * udc_connected - is the USB cable connected ++ * ++ * Return non-zero if cable is connected. ++ */ ++#if 0 ++int udc_connected (void) ++{ ++ return ((inw (UDC_DEVSTAT) & UDC_ATT) == UDC_ATT); ++} ++#endif ++ ++/* Turn on the USB connection by enabling the pullup resistor */ ++void udc_connect (void) ++{ ++ debug("connect, enable Pullup\n"); ++ S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT(); ++ ++ udc_ctrl(UDC_CTRL_PULLUP_ENABLE, 0); ++ udelay(10000); ++ udc_ctrl(UDC_CTRL_PULLUP_ENABLE, 1); ++ ++ irq->INTMSK &= ~BIT_USBD; ++} ++ ++/* Turn off the USB connection by disabling the pullup resistor */ ++void udc_disconnect (void) ++{ ++ debug("disconnect, disable Pullup\n"); ++ S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT(); ++ ++ udc_ctrl(UDC_CTRL_PULLUP_ENABLE, 0); ++ ++ /* Disable interrupt (we don't want to get interrupts while the kernel ++ * is relocating itself */ ++ irq->INTMSK |= BIT_USBD; ++} ++ ++/* Switch on the UDC */ ++void udc_enable (struct usb_device_instance *device) ++{ ++ debug("enable device %p, status %d\n", device, device->status); ++ ++ /* Save the device structure pointer */ ++ udc_device = device; ++ ++ /* Setup ep0 urb */ ++ if (!ep0_urb) ++ ep0_urb = usbd_alloc_urb(udc_device, ++ udc_device->bus->endpoint_array); ++ else ++ serial_printf("udc_enable: ep0_urb already allocated %p\n", ++ ep0_urb); ++ ++ s3c2410_configure_device(device); ++} ++ ++/* Switch off the UDC */ ++void udc_disable (void) ++{ ++ debug("disable UDC\n"); ++ ++ s3c2410_deconfigure_device(); ++ ++ /* Free ep0 URB */ ++ if (ep0_urb) { ++ /*usbd_dealloc_urb(ep0_urb); */ ++ ep0_urb = NULL; ++ } ++ ++ /* Reset device pointer. ++ * We ought to do this here to balance the initialization of udc_device ++ * in udc_enable, but some of our other exported functions get called ++ * by the bus interface driver after udc_disable, so we have to hang on ++ * to the device pointer to avoid a null pointer dereference. */ ++ /* udc_device = NULL; */ ++} ++ ++/** ++ * udc_startup - allow udc code to do any additional startup ++ */ ++void udc_startup_events (struct usb_device_instance *device) ++{ ++ /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */ ++ usbd_device_event_irq (device, DEVICE_INIT, 0); ++ ++ /* The DEVICE_CREATE event puts the USB device in the state ++ * STATE_ATTACHED. ++ */ ++ usbd_device_event_irq (device, DEVICE_CREATE, 0); ++ ++ /* Some USB controller driver implementations signal ++ * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here. ++ * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED, ++ * and DEVICE_RESET causes a transition to the state STATE_DEFAULT. ++ * The OMAP USB client controller has the capability to detect when the ++ * USB cable is connected to a powered USB bus via the ATT bit in the ++ * DEVSTAT register, so we will defer the DEVICE_HUB_CONFIGURED and ++ * DEVICE_RESET events until later. ++ */ ++ ++ /* The GTA01 can detect usb device attachment, but we just assume being ++ * attached for now (go to STATE_POWERED) */ ++ usbd_device_event_irq (device, DEVICE_HUB_CONFIGURED, 0); ++ ++ udc_enable (device); ++} ++ ++void udc_set_nak(int epid) ++{ ++ /* FIXME: implement this */ ++} ++ ++void udc_unset_nak(int epid) ++{ ++ /* FIXME: implement this */ ++} ++ ++#endif /* CONFIG_S3C2410 && CONFIG_USB_DEVICE */ +Index: u-boot/drivers/usbdcore_s3c2410.h +=================================================================== +--- /dev/null ++++ u-boot/drivers/usbdcore_s3c2410.h +@@ -0,0 +1,273 @@ ++/* linux/include/asm/arch-s3c2410/regs-udc.h ++ * ++ * Copyright (C) 2004 Herbert Poetzl ++ * ++ * This include file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * Changelog: ++ * 01-08-2004 Initial creation ++ * 12-09-2004 Cleanup for submission ++ * 24-10-2004 Fixed S3C2410_UDC_MAXP_REG definition ++ * 10-03-2005 Changed S3C2410_VA to S3C24XX_VA ++ * 10-01-2007 Modify for u-boot ++ */ ++ ++#ifndef __ASM_ARCH_REGS_UDC_H ++#define __ASM_ARCH_REGS_UDC_H ++ ++#define S3C2410_UDC_REG_BASE_PHYS 0x52000000 ++#define S3C2410_UDC_NUM_ENDPOINTS 5 ++ ++#define S3C2410_USBDREG(x) (x + S3C2410_UDC_REG_BASE_PHYS) ++ ++#define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140) ++#define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144) ++#define S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148) ++ ++#define S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158) ++#define S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c) ++ ++#define S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c) ++ ++#define S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170) ++#define S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174) ++ ++#define S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0) ++#define S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4) ++#define S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8) ++#define S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc) ++#define S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0) ++ ++#define S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200) ++#define S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204) ++#define S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208) ++#define S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c) ++#define S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210) ++#define S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214) ++ ++#define S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218) ++#define S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c) ++#define S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220) ++#define S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224) ++#define S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228) ++#define S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c) ++ ++#define S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240) ++#define S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244) ++#define S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248) ++#define S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c) ++#define S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250) ++#define S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254) ++ ++#define S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258) ++#define S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c) ++#define S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260) ++#define S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264) ++#define S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268) ++#define S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c) ++ ++#define S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178) ++ ++/* indexed registers */ ++ ++#define S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x0180) ++ ++#define S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184) ++ ++#define S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184) ++#define S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188) ++ ++#define S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190) ++#define S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194) ++#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198) ++#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c) ++ ++ ++ ++#define S3C2410_UDC_PWR_ISOUP (1<<7) // R/W ++#define S3C2410_UDC_PWR_RESET (1<<3) // R ++#define S3C2410_UDC_PWR_RESUME (1<<2) // R/W ++#define S3C2410_UDC_PWR_SUSPEND (1<<1) // R ++#define S3C2410_UDC_PWR_ENSUSPEND (1<<0) // R/W ++ ++#define S3C2410_UDC_PWR_DEFAULT 0x00 ++ ++#define S3C2410_UDC_INT_EP4 (1<<4) // R/W (clear only) ++#define S3C2410_UDC_INT_EP3 (1<<3) // R/W (clear only) ++#define S3C2410_UDC_INT_EP2 (1<<2) // R/W (clear only) ++#define S3C2410_UDC_INT_EP1 (1<<1) // R/W (clear only) ++#define S3C2410_UDC_INT_EP0 (1<<0) // R/W (clear only) ++ ++#define S3C2410_UDC_USBINT_RESET (1<<2) // R/W (clear only) ++#define S3C2410_UDC_USBINT_RESUME (1<<1) // R/W (clear only) ++#define S3C2410_UDC_USBINT_SUSPEND (1<<0) // R/W (clear only) ++ ++#define S3C2410_UDC_INTE_EP4 (1<<4) // R/W ++#define S3C2410_UDC_INTE_EP3 (1<<3) // R/W ++#define S3C2410_UDC_INTE_EP2 (1<<2) // R/W ++#define S3C2410_UDC_INTE_EP1 (1<<1) // R/W ++#define S3C2410_UDC_INTE_EP0 (1<<0) // R/W ++ ++#define S3C2410_UDC_USBINTE_RESET (1<<2) // R/W ++#define S3C2410_UDC_USBINTE_SUSPEND (1<<0) // R/W ++ ++ ++#define S3C2410_UDC_INDEX_EP0 (0x00) ++#define S3C2410_UDC_INDEX_EP1 (0x01) // ?? ++#define S3C2410_UDC_INDEX_EP2 (0x02) // ?? ++#define S3C2410_UDC_INDEX_EP3 (0x03) // ?? ++#define S3C2410_UDC_INDEX_EP4 (0x04) // ?? ++ ++#define S3C2410_UDC_ICSR1_CLRDT (1<<6) // R/W ++#define S3C2410_UDC_ICSR1_SENTSTL (1<<5) // R/W (clear only) ++#define S3C2410_UDC_ICSR1_SENDSTL (1<<4) // R/W ++#define S3C2410_UDC_ICSR1_FFLUSH (1<<3) // W (set only) ++#define S3C2410_UDC_ICSR1_UNDRUN (1<<2) // R/W (clear only) ++#define S3C2410_UDC_ICSR1_PKTRDY (1<<0) // R/W (set only) ++ ++#define S3C2410_UDC_ICSR2_AUTOSET (1<<7) // R/W ++#define S3C2410_UDC_ICSR2_ISO (1<<6) // R/W ++#define S3C2410_UDC_ICSR2_MODEIN (1<<5) // R/W ++#define S3C2410_UDC_ICSR2_DMAIEN (1<<4) // R/W ++ ++#define S3C2410_UDC_OCSR1_CLRDT (1<<7) // R/W ++#define S3C2410_UDC_OCSR1_SENTSTL (1<<6) // R/W (clear only) ++#define S3C2410_UDC_OCSR1_SENDSTL (1<<5) // R/W ++#define S3C2410_UDC_OCSR1_FFLUSH (1<<4) // R/W ++#define S3C2410_UDC_OCSR1_DERROR (1<<3) // R ++#define S3C2410_UDC_OCSR1_OVRRUN (1<<2) // R/W (clear only) ++#define S3C2410_UDC_OCSR1_PKTRDY (1<<0) // R/W (clear only) ++ ++#define S3C2410_UDC_OCSR2_AUTOCLR (1<<7) // R/W ++#define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W ++#define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W ++ ++#define S3C2410_UDC_SETIX(X) writel(X, S3C2410_UDC_INDEX_REG) ++ ++#define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0) ++#define S3C2410_UDC_EP0_CSR_IPKRDY (1<<1) ++#define S3C2410_UDC_EP0_CSR_SENTSTL (1<<2) ++#define S3C2410_UDC_EP0_CSR_DE (1<<3) ++#define S3C2410_UDC_EP0_CSR_SE (1<<4) ++#define S3C2410_UDC_EP0_CSR_SENDSTL (1<<5) ++#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1<<6) ++#define S3C2410_UDC_EP0_CSR_SSE (1<<7) ++ ++#define S3C2410_UDC_MAXP_8 (1<<0) ++#define S3C2410_UDC_MAXP_16 (1<<1) ++#define S3C2410_UDC_MAXP_32 (1<<2) ++#define S3C2410_UDC_MAXP_64 (1<<3) ++ ++/****************** MACROS ******************/ ++#define BIT_MASK 0xFF ++ ++#if 1 ++#define maskl(v,m,a) \ ++ writel((readl(a) & ~(m))|((v)&(m)), (a)) ++#else ++#define maskl(v,m,a) do { \ ++ unsigned long foo = readl(a); \ ++ unsigned long bar = (foo & ~(m)) | ((v)&(m)); \ ++ serial_printf("0x%08x:0x%x->0x%x\n", (a), foo, bar); \ ++ writel(bar, (a)); \ ++} while(0) ++#endif ++ ++#define clear_ep0_sst() do { \ ++ S3C2410_UDC_SETIX(0); \ ++ writel(0x00, S3C2410_UDC_EP0_CSR_REG); \ ++} while(0) ++ ++#define clear_ep0_se() do { \ ++ S3C2410_UDC_SETIX(0); \ ++ maskl(S3C2410_UDC_EP0_CSR_SSE, \ ++ BIT_MASK, S3C2410_UDC_EP0_CSR_REG); \ ++} while(0) ++ ++#define clear_ep0_opr() do { \ ++ S3C2410_UDC_SETIX(0); \ ++ maskl(S3C2410_UDC_EP0_CSR_SOPKTRDY, \ ++ BIT_MASK, S3C2410_UDC_EP0_CSR_REG); \ ++} while(0) ++ ++#define set_ep0_ipr() do { \ ++ S3C2410_UDC_SETIX(0); \ ++ maskl(S3C2410_UDC_EP0_CSR_IPKRDY, \ ++ BIT_MASK, S3C2410_UDC_EP0_CSR_REG); \ ++} while(0) ++ ++#define set_ep0_de() do { \ ++ S3C2410_UDC_SETIX(0); \ ++ maskl(S3C2410_UDC_EP0_CSR_DE, \ ++ BIT_MASK, S3C2410_UDC_EP0_CSR_REG); \ ++} while(0) ++ ++#define set_ep0_ss() do { \ ++ S3C2410_UDC_SETIX(0); \ ++ maskl(S3C2410_UDC_EP0_CSR_SENDSTL, \ ++ BIT_MASK, S3C2410_UDC_EP0_CSR_REG); \ ++} while(0) ++ ++#define set_ep0_de_out() do { \ ++ S3C2410_UDC_SETIX(0); \ ++ maskl((S3C2410_UDC_EP0_CSR_SOPKTRDY \ ++ | S3C2410_UDC_EP0_CSR_DE), \ ++ BIT_MASK, S3C2410_UDC_EP0_CSR_REG); \ ++} while(0) ++ ++#define set_ep0_sse_out() do { \ ++ S3C2410_UDC_SETIX(0); \ ++ maskl((S3C2410_UDC_EP0_CSR_SOPKTRDY \ ++ | S3C2410_UDC_EP0_CSR_SSE), \ ++ BIT_MASK, S3C2410_UDC_EP0_CSR_REG); \ ++} while(0) ++ ++#define set_ep0_de_in() do { \ ++ S3C2410_UDC_SETIX(0); \ ++ maskl((S3C2410_UDC_EP0_CSR_IPKRDY \ ++ | S3C2410_UDC_EP0_CSR_DE), \ ++ BIT_MASK, S3C2410_UDC_EP0_CSR_REG); \ ++} while(0) ++ ++ ++#if 0 ++ ++#define clear_stall_ep1_out(base) do { \ ++ S3C2410_UDC_SETIX(base,EP1); \ ++ orl(0,base+S3C2410_UDC_OUT_CSR1_REG); \ ++} while(0) ++ ++ ++#define clear_stall_ep2_out(base) do { \ ++ S3C2410_UDC_SETIX(base,EP2); \ ++ orl(0, base+S3C2410_UDC_OUT_CSR1_REG); \ ++} while(0) ++ ++ ++#define clear_stall_ep3_out(base) do { \ ++ S3C2410_UDC_SETIX(base,EP3); \ ++ orl(0,base+S3C2410_UDC_OUT_CSR1_REG); \ ++} while(0) ++ ++ ++#define clear_stall_ep4_out(base) do { \ ++ S3C2410_UDC_SETIX(base,EP4); \ ++ orl(0, base+S3C2410_UDC_OUT_CSR1_REG); \ ++} while(0) ++ ++#endif ++ ++/* S3C2410 Endpoint parameters */ ++#define EP0_MAX_PACKET_SIZE 16 ++#define UDC_OUT_ENDPOINT 2 ++#define UDC_OUT_PACKET_SIZE 64 ++#define UDC_IN_ENDPOINT 1 ++#define UDC_IN_PACKET_SIZE 64 ++#define UDC_INT_ENDPOINT 5 ++#define UDC_INT_PACKET_SIZE 16 ++#define UDC_BULK_PACKET_SIZE 16 ++ ++#endif +Index: u-boot/drivers/usbdcore_ep0.c +=================================================================== +--- u-boot.orig/drivers/usbdcore_ep0.c ++++ u-boot/drivers/usbdcore_ep0.c +@@ -43,7 +43,7 @@ + + #include + +-#if defined(CONFIG_OMAP1510) && defined(CONFIG_USB_DEVICE) ++#if defined(CONFIG_USB_DEVICE) + #include "usbdcore.h" + + #if 0 +@@ -187,9 +187,13 @@ + if (!urb || !urb->buffer || !urb->buffer_length + || (urb->buffer_length < 255)) { + dbg_ep0 (2, "invalid urb %p", urb); ++ serial_printf("invalid urb %p", urb); + return -1L; + } + ++ /* re-initialize the ep0 buffer pointer */ ++ urb->buffer = (u8 *) urb->buffer_data; ++ + /* setup tx urb */ + urb->actual_length = 0; + cp = urb->buffer; +@@ -206,17 +210,8 @@ + usbd_device_device_descriptor (device, port))) { + return -1; + } +- /* copy descriptor for this device */ +- copy_config (urb, device_descriptor, +- sizeof (struct usb_device_descriptor), +- max); +- +- /* correct the correct control endpoint 0 max packet size into the descriptor */ +- device_descriptor = +- (struct usb_device_descriptor *) urb->buffer; +- device_descriptor->bMaxPacketSize0 = +- urb->device->bus->maxpacketsize; +- ++ urb->buffer = device_descriptor; ++ urb->actual_length = MIN(sizeof(*device_descriptor), max); + } + /*dbg_ep0(3, "copied device configuration, actual_length: %x", urb->actual_length); */ + break; +@@ -250,11 +245,9 @@ + index); + return -1; + } +- copy_config (urb, configuration_descriptor, +- sizeof (struct +- usb_configuration_descriptor), +- max); +- ++ urb->buffer = configuration_descriptor; ++ urb->actual_length = ++ MIN(le16_to_cpu(configuration_descriptor->wTotalLength), max); + } + break; + +@@ -376,6 +369,7 @@ + dbg_ep0 (0, "entering ep0_recv_setup()"); + if (!urb || !urb->device) { + dbg_ep0 (3, "invalid URB %p", urb); ++ serial_printf("invalid URB %p", urb); + return -1; + } + +@@ -400,6 +394,7 @@ + return device->cdc_recv_setup(request, urb); + dbg_ep0 (1, "non standard request: %x", + request->bmRequestType & USB_REQ_TYPE_MASK); ++ serial_printf("non standard request: %x", request->bmRequestType & USB_REQ_TYPE_MASK); + return -1; /* Stall here */ + } + +@@ -448,6 +443,8 @@ + dbg_ep0 (1, "request %s not allowed in UNKNOWN state: %s", + USBD_DEVICE_REQUESTS (request->bRequest), + usbd_device_states[device->device_state]); ++ serial_printf("request %s not allowed in UNKNOWN state: %s", USBD_DEVICE_REQUESTS (request->bRequest), usbd_device_states[device->device_state]); ++ break; + return -1; + } + +@@ -545,7 +542,8 @@ + /*dbg_ep0(2, "address: %d %d %d", */ + /* request->wValue, le16_to_cpu(request->wValue), device->address); */ + +- serial_printf ("DEVICE_ADDRESS_ASSIGNED.. event?\n"); ++ //serial_printf ("DEVICE_ADDRESS_ASSIGNED.. event?\n"); ++ //udc_set_address(device->address); + return 0; + + case USB_REQ_SET_DESCRIPTOR: /* XXX should we support this? */ +Index: u-boot/include/configs/neo1973_gta01.h +=================================================================== +--- u-boot.orig/include/configs/neo1973_gta01.h ++++ u-boot/include/configs/neo1973_gta01.h +@@ -173,6 +173,16 @@ + #define CONFIG_USB_OHCI 1 + #endif + ++#define CONFIG_USB_DEVICE 1 ++#define CONFIG_USB_TTY 1 ++#define CFG_CONSOLE_IS_IN_ENV 1 ++#define CONFIG_USBD_VENDORID 0x1457 /* Linux/NetChip */ ++#define CONFIG_USBD_PRODUCTID_GSERIAL 0x5120 /* gserial */ ++#define CONFIG_USBD_PRODUCTID_CDCACM 0x5119 /* CDC ACM */ ++#define CONFIG_USBD_MANUFACTURER "OpenMoko, Inc" ++#define CONFIG_USBD_PRODUCT_NAME "Neo1973 Bootloader " U_BOOT_VERSION ++#define CONFIG_EXTRA_ENV_SETTINGS "usbtty=cdc_acm\0" ++ + /*----------------------------------------------------------------------- + * Physical Memory Map + */ +Index: u-boot/cpu/arm920t/s3c24x0/interrupts.c +=================================================================== +--- u-boot.orig/cpu/arm920t/s3c24x0/interrupts.c ++++ u-boot/cpu/arm920t/s3c24x0/interrupts.c +@@ -222,6 +222,13 @@ + S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT(); + u_int32_t intpnd = irq->INTPND; + ++#ifdef CONFIG_USB_DEVICE ++ if (intpnd & BIT_USBD) { ++ s3c2410_udc_irq(); ++ irq->SRCPND = BIT_USBD; ++ irq->INTPND = BIT_USBD; ++ } ++#endif /* USB_DEVICE */ + } + #endif /* USE_IRQ */ + +Index: u-boot/drivers/usbtty.h +=================================================================== +--- u-boot.orig/drivers/usbtty.h ++++ u-boot/drivers/usbtty.h +@@ -29,6 +29,8 @@ + #include "usbdcore_mpc8xx.h" + #elif defined(CONFIG_OMAP1510) + #include "usbdcore_omap1510.h" ++#elif defined(CONFIG_S3C2410) ++#include "usbdcore_s3c2410.h" + #endif + + #include +Index: u-boot/board/neo1973/common/cmd_neo1973.c +=================================================================== +--- u-boot.orig/board/neo1973/common/cmd_neo1973.c ++++ u-boot/board/neo1973/common/cmd_neo1973.c +@@ -72,6 +72,18 @@ + neo1973_vibrator(1); + else + neo1973_vibrator(0); ++ } else if (!strcmp(argv[1], "udc")) { ++ if (argc < 3) ++ goto out_help; ++ if (!strcmp(argv[2], "udc")) { ++ if (argc < 4) ++ goto out_help; ++ if (!strcmp(argv[3], "on")) ++ udc_connect(); ++ else ++ udc_disconnect(); ++ } else ++ goto out_help; + } else { + out_help: + printf("Usage:\n%s\n", cmdtp->usage); +@@ -95,5 +107,6 @@ + "neo1973 charger off - disable charging\n" + "neo1973 backlight (on|off) - switch backlight on or off\n" + "neo1973 vibrator (on|off) - switch vibrator on or off\n" ++ "neo1973 udc pullup (on|off) - switch pull-up on or off\n" + ); + #endif /* CFG_CMD_BDI */ +Index: u-boot/board/neo1973/gta01/Makefile +=================================================================== +--- u-boot.orig/board/neo1973/gta01/Makefile ++++ u-boot/board/neo1973/gta01/Makefile +@@ -25,7 +25,7 @@ + + LIB = lib$(BOARD).a + +-OBJS := gta01.o pcf50606.o ../common/cmd_neo1973.o ../common/jbt6k74.o ++OBJS := gta01.o pcf50606.o ../common/cmd_neo1973.o ../common/jbt6k74.o ../common/udc.o + SOBJS := ../common/lowlevel_init.o + + $(LIB): $(OBJS) $(SOBJS) +Index: u-boot/board/neo1973/common/udc.c +=================================================================== +--- /dev/null ++++ u-boot/board/neo1973/common/udc.c +@@ -0,0 +1,23 @@ ++ ++#include ++#include ++#include ++ ++void udc_ctrl(enum usbd_event event, int param) ++{ ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ ++ switch (event) { ++ case UDC_CTRL_PULLUP_ENABLE: ++#if defined(CONFIG_ARCH_GTA01_v4) || defined(CONFIG_ARCH_GTA01B_v2) || \ ++ defined(CONFIG_ARCH_GTA01B_v3) || defined(CONFIG_ARCH_GTA01B_v4) ++ if (param) ++ gpio->GPBDAT |= (1 << 9); ++ else ++ gpio->GPBDAT &= ~(1 << 9); ++#endif ++ break; ++ default: ++ break; ++ } ++} +Index: u-boot/include/usbdcore.h +=================================================================== +--- u-boot.orig/include/usbdcore.h ++++ u-boot/include/usbdcore.h +@@ -671,4 +671,10 @@ + void usbd_rcv_complete(struct usb_endpoint_instance *endpoint, int len, int urb_bad); + void usbd_tx_complete (struct usb_endpoint_instance *endpoint); + ++enum usbd_event { ++ UDC_CTRL_PULLUP_ENABLE, ++}; ++ ++void udc_ctrl(enum usbd_event event, int param); ++#endif + #endif diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2440.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2440.patch new file mode 100644 index 0000000000..da0fb8cf2d --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2440.patch @@ -0,0 +1,1301 @@ +Add proper support for S3C2440 CPU's + +Index: u-boot/include/s3c24x0.h +=================================================================== +--- u-boot.orig/include/s3c24x0.h ++++ u-boot/include/s3c24x0.h +@@ -82,7 +82,7 @@ + S3C24X0_REG32 PRIORITY; + S3C24X0_REG32 INTPND; + S3C24X0_REG32 INTOFFSET; +-#ifdef CONFIG_S3C2410 ++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) + S3C24X0_REG32 SUBSRCPND; + S3C24X0_REG32 INTSUBMSK; + #endif +@@ -92,11 +92,11 @@ + /* DMAS (see manual chapter 8) */ + typedef struct { + S3C24X0_REG32 DISRC; +-#ifdef CONFIG_S3C2410 ++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) + S3C24X0_REG32 DISRCC; + #endif + S3C24X0_REG32 DIDST; +-#ifdef CONFIG_S3C2410 ++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) + S3C24X0_REG32 DIDSTC; + #endif + S3C24X0_REG32 DCON; +@@ -107,7 +107,7 @@ + #ifdef CONFIG_S3C2400 + S3C24X0_REG32 res[1]; + #endif +-#ifdef CONFIG_S3C2410 ++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) + S3C24X0_REG32 res[7]; + #endif + } /*__attribute__((__packed__))*/ S3C24X0_DMA; +@@ -126,6 +126,9 @@ + S3C24X0_REG32 CLKCON; + S3C24X0_REG32 CLKSLOW; + S3C24X0_REG32 CLKDIVN; ++#ifdef CONFIG_S3C2440 ++ S3C24X0_REG32 CAMDIVN; ++#endif + } /*__attribute__((__packed__))*/ S3C24X0_CLOCK_POWER; + + +@@ -145,7 +148,7 @@ + S3C24X0_REG32 res[8]; + S3C24X0_REG32 DITHMODE; + S3C24X0_REG32 TPAL; +-#ifdef CONFIG_S3C2410 ++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) + S3C24X0_REG32 LCDINTPND; + S3C24X0_REG32 LCDSRCPND; + S3C24X0_REG32 LCDINTMSK; +@@ -157,6 +160,9 @@ + /* NAND FLASH (see S3C2410 manual chapter 6) */ + typedef struct { + S3C24X0_REG32 NFCONF; ++#ifdef CONFIG_S3C2440 ++ S3C24X0_REG32 NFCONT; ++#endif + S3C24X0_REG32 NFCMD; + S3C24X0_REG32 NFADDR; + S3C24X0_REG32 NFDATA; +@@ -164,6 +170,15 @@ + S3C24X0_REG32 NFECC; + } /*__attribute__((__packed__))*/ S3C2410_NAND; + ++/* NAND FLASH (see S3C2440 manual chapter 6) */ ++typedef struct { ++ S3C24X0_REG32 NFCONF; ++ S3C24X0_REG32 NFCMD; ++ S3C24X0_REG32 NFADDR; ++ S3C24X0_REG32 NFDATA; ++ S3C24X0_REG32 NFSTAT; ++ S3C24X0_REG32 NFECC; ++} /*__attribute__((__packed__))*/ S3C2440_NAND; + + /* UART (see manual chapter 11) */ + typedef struct { +@@ -451,6 +466,65 @@ + S3C24X0_REG32 GSTATUS3; + S3C24X0_REG32 GSTATUS4; + #endif ++#ifdef CONFIG_S3C2440 ++ S3C24X0_REG32 GPACON; ++ S3C24X0_REG32 GPADAT; ++ S3C24X0_REG32 res1[2]; ++ S3C24X0_REG32 GPBCON; ++ S3C24X0_REG32 GPBDAT; ++ S3C24X0_REG32 GPBUP; ++ S3C24X0_REG32 res2; ++ S3C24X0_REG32 GPCCON; ++ S3C24X0_REG32 GPCDAT; ++ S3C24X0_REG32 GPCUP; ++ S3C24X0_REG32 res3; ++ S3C24X0_REG32 GPDCON; ++ S3C24X0_REG32 GPDDAT; ++ S3C24X0_REG32 GPDUP; ++ S3C24X0_REG32 res4; ++ S3C24X0_REG32 GPECON; ++ S3C24X0_REG32 GPEDAT; ++ S3C24X0_REG32 GPEUP; ++ S3C24X0_REG32 res5; ++ S3C24X0_REG32 GPFCON; ++ S3C24X0_REG32 GPFDAT; ++ S3C24X0_REG32 GPFUP; ++ S3C24X0_REG32 res6; ++ S3C24X0_REG32 GPGCON; ++ S3C24X0_REG32 GPGDAT; ++ S3C24X0_REG32 GPGUP; ++ S3C24X0_REG32 res7; ++ S3C24X0_REG32 GPHCON; ++ S3C24X0_REG32 GPHDAT; ++ S3C24X0_REG32 GPHUP; ++ S3C24X0_REG32 res8; ++ ++ S3C24X0_REG32 MISCCR; ++ S3C24X0_REG32 DCLKCON; ++ S3C24X0_REG32 EXTINT0; ++ S3C24X0_REG32 EXTINT1; ++ S3C24X0_REG32 EXTINT2; ++ S3C24X0_REG32 EINTFLT0; ++ S3C24X0_REG32 EINTFLT1; ++ S3C24X0_REG32 EINTFLT2; ++ S3C24X0_REG32 EINTFLT3; ++ S3C24X0_REG32 EINTMASK; ++ S3C24X0_REG32 EINTPEND; ++ S3C24X0_REG32 GSTATUS0; ++ S3C24X0_REG32 GSTATUS1; ++ S3C24X0_REG32 GSTATUS2; ++ S3C24X0_REG32 GSTATUS3; ++ S3C24X0_REG32 GSTATUS4; ++ ++ S3C24X0_REG32 res9; ++ S3C24X0_REG32 DSC0; ++ S3C24X0_REG32 DSC1; ++ S3C24X0_REG32 MSLCON; ++ S3C24X0_REG32 GPJCON; ++ S3C24X0_REG32 GPJDAT; ++ S3C24X0_REG32 GPJUP; ++ S3C24X0_REG32 res10; ++#endif + } /*__attribute__((__packed__))*/ S3C24X0_GPIO; + + +@@ -637,8 +711,13 @@ + S3C24X0_REG32 SDIDCNT; + S3C24X0_REG32 SDIDSTA; + S3C24X0_REG32 SDIFSTA; ++#if defined(CONFIG_S3C2410) + S3C24X0_REG32 SDIDAT; + S3C24X0_REG32 SDIIMSK; ++#elif defined(CONFIG_S3C2440) ++ S3C24X0_REG32 SDIIMSK; ++ S3C24X0_REG32 SDIDAT; ++#endif + } /*__attribute__((__packed__))*/ S3C2410_SDI; + + +Index: u-boot/rtc/s3c24x0_rtc.c +=================================================================== +--- u-boot.orig/rtc/s3c24x0_rtc.c ++++ u-boot/rtc/s3c24x0_rtc.c +@@ -34,6 +34,8 @@ + #include + #elif defined(CONFIG_S3C2410) + #include ++#elif defined(CONFIG_S3C2440) ++#include + #endif + + #include +Index: u-boot/include/s3c2440.h +=================================================================== +--- /dev/null ++++ u-boot/include/s3c2440.h +@@ -0,0 +1,300 @@ ++/* ++ * (C) Copyright 2003 ++ * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/************************************************ ++ * NAME : s3c2440.h ++ * Version : 2007. ++ * ++ * Based on S3C2410X User's manual Rev 1.1 ++ ************************************************/ ++ ++#ifndef __S3C2440_H__ ++#define __S3C2440_H__ ++ ++#define S3C24X0_UART_CHANNELS 3 ++#define S3C24X0_SPI_CHANNELS 2 ++ ++/* S3C2440 only supports 512 Byte HW ECC */ ++#define S3C2440_ECCSIZE 512 ++#define S3C2440_ECCBYTES 3 ++ ++/* S3C2440 device base addresses */ ++#define S3C24X0_MEMCTL_BASE 0x48000000 ++#define S3C24X0_USB_HOST_BASE 0x49000000 ++#define S3C24X0_INTERRUPT_BASE 0x4A000000 ++#define S3C24X0_DMA_BASE 0x4B000000 ++#define S3C24X0_CLOCK_POWER_BASE 0x4C000000 ++#define S3C24X0_LCD_BASE 0x4D000000 ++#define S3C2440_NAND_BASE 0x4E000000 ++#define S3C24X0_UART_BASE 0x50000000 ++#define S3C24X0_TIMER_BASE 0x51000000 ++#define S3C24X0_USB_DEVICE_BASE 0x52000140 ++#define USB_DEVICE_PHYS_ADR 0x52000000 ++#define S3C24X0_WATCHDOG_BASE 0x53000000 ++#define S3C24X0_I2C_BASE 0x54000000 ++#define S3C24X0_I2S_BASE 0x55000000 ++#define S3C24X0_GPIO_BASE 0x56000000 ++#define S3C24X0_RTC_BASE 0x57000000 ++#define S3C2440_ADC_BASE 0x58000000 ++#define S3C24X0_SPI_BASE 0x59000000 ++#define S3C2440_SDI_BASE 0x5A000000 ++ ++#define oNFCONF 0x00 ++#define oNFCONT 0x04 ++ ++#ifndef __ASSEMBLER__ ++ ++/* include common stuff */ ++#include ++ ++typedef enum { ++ S3C24X0_UART0, ++ S3C24X0_UART1, ++ S3C24X0_UART2 ++} S3C24X0_UARTS_NR; ++ ++static inline S3C24X0_MEMCTL * S3C24X0_GetBase_MEMCTL(void) ++{ ++ return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE; ++} ++static inline S3C24X0_USB_HOST * S3C24X0_GetBase_USB_HOST(void) ++{ ++ return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE; ++} ++static inline S3C24X0_INTERRUPT * S3C24X0_GetBase_INTERRUPT(void) ++{ ++ return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE; ++} ++static inline S3C24X0_DMAS * S3C24X0_GetBase_DMAS(void) ++{ ++ return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE; ++} ++static inline S3C24X0_CLOCK_POWER * S3C24X0_GetBase_CLOCK_POWER(void) ++{ ++ return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE; ++} ++static inline S3C24X0_LCD * S3C24X0_GetBase_LCD(void) ++{ ++ return (S3C24X0_LCD * const)S3C24X0_LCD_BASE; ++} ++static inline S3C2440_NAND * S3C2440_GetBase_NAND(void) ++{ ++ return (S3C2440_NAND * const)S3C2440_NAND_BASE; ++} ++static inline S3C24X0_UART * S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr) ++{ ++ return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000)); ++} ++static inline S3C24X0_TIMERS * S3C24X0_GetBase_TIMERS(void) ++{ ++ return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE; ++} ++static inline S3C24X0_USB_DEVICE * S3C24X0_GetBase_USB_DEVICE(void) ++{ ++ return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE; ++} ++static inline S3C24X0_WATCHDOG * S3C24X0_GetBase_WATCHDOG(void) ++{ ++ return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE; ++} ++static inline S3C24X0_I2C * S3C24X0_GetBase_I2C(void) ++{ ++ return (S3C24X0_I2C * const)S3C24X0_I2C_BASE; ++} ++static inline S3C24X0_I2S * S3C24X0_GetBase_I2S(void) ++{ ++ return (S3C24X0_I2S * const)S3C24X0_I2S_BASE; ++} ++static inline S3C24X0_GPIO * S3C24X0_GetBase_GPIO(void) ++{ ++ return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE; ++} ++static inline S3C24X0_RTC * S3C24X0_GetBase_RTC(void) ++{ ++ return (S3C24X0_RTC * const)S3C24X0_RTC_BASE; ++} ++/* ++static inline S3C2440_ADC * S3C2440_GetBase_ADC(void) ++{ ++ return (S3C2440_ADC * const)S3C2440_ADC_BASE; ++} ++static inline S3C24X0_SPI * S3C24X0_GetBase_SPI(void) ++{ ++ return (S3C24X0_SPI * const)S3C24X0_SPI_BASE; ++} ++*/ ++static inline S3C2410_SDI * S3C2410_GetBase_SDI(void) ++{ ++ return (S3C2410_SDI * const)S3C2440_SDI_BASE; ++} ++ ++#endif /* __ASSEMBLER__ */ ++ ++/* ISR */ ++#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0)) ++#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4)) ++#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8)) ++#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xC)) ++#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10)) ++#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14)) ++#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18)) ++#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1C)) ++ ++#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20)) ++#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24)) ++#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28)) ++#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2C)) ++#define pISR_EINT4_7 (*(unsigned *)(_ISR_STARTADDRESS+0x30)) ++#define pISR_EINT8_23 (*(unsigned *)(_ISR_STARTADDRESS+0x34)) ++#define pISR_BAT_FLT (*(unsigned *)(_ISR_STARTADDRESS+0x3C)) ++#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40)) ++#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44)) ++#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48)) ++#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4C)) ++#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50)) ++#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54)) ++#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58)) ++#define pISR_UART2 (*(unsigned *)(_ISR_STARTADDRESS+0x5C)) ++#define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60)) ++#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64)) ++#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68)) ++#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6C)) ++#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70)) ++#define pISR_SDI (*(unsigned *)(_ISR_STARTADDRESS+0x74)) ++#define pISR_SPI0 (*(unsigned *)(_ISR_STARTADDRESS+0x78)) ++#define pISR_UART1 (*(unsigned *)(_ISR_STARTADDRESS+0x7C)) ++#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84)) ++#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88)) ++#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8C)) ++#define pISR_UART0 (*(unsigned *)(_ISR_STARTADDRESS+0x90)) ++#define pISR_SPI1 (*(unsigned *)(_ISR_STARTADDRESS+0x94)) ++#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98)) ++#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xA0)) ++ ++ ++/* PENDING BIT */ ++#define BIT_EINT0 (0x1) ++#define BIT_EINT1 (0x1<<1) ++#define BIT_EINT2 (0x1<<2) ++#define BIT_EINT3 (0x1<<3) ++#define BIT_EINT4_7 (0x1<<4) ++#define BIT_EINT8_23 (0x1<<5) ++#define BIT_BAT_FLT (0x1<<7) ++#define BIT_TICK (0x1<<8) ++#define BIT_WDT (0x1<<9) ++#define BIT_TIMER0 (0x1<<10) ++#define BIT_TIMER1 (0x1<<11) ++#define BIT_TIMER2 (0x1<<12) ++#define BIT_TIMER3 (0x1<<13) ++#define BIT_TIMER4 (0x1<<14) ++#define BIT_UART2 (0x1<<15) ++#define BIT_LCD (0x1<<16) ++#define BIT_DMA0 (0x1<<17) ++#define BIT_DMA1 (0x1<<18) ++#define BIT_DMA2 (0x1<<19) ++#define BIT_DMA3 (0x1<<20) ++#define BIT_SDI (0x1<<21) ++#define BIT_SPI0 (0x1<<22) ++#define BIT_UART1 (0x1<<23) ++#define BIT_USBD (0x1<<25) ++#define BIT_USBH (0x1<<26) ++#define BIT_IIC (0x1<<27) ++#define BIT_UART0 (0x1<<28) ++#define BIT_SPI1 (0x1<<29) ++#define BIT_RTC (0x1<<30) ++#define BIT_ADC (0x1<<31) ++#define BIT_ALLMSK (0xFFFFFFFF) ++ ++#define ClearPending(bit) {\ ++ rSRCPND = bit;\ ++ rINTPND = bit;\ ++ rINTPND;\ ++ } ++/* Wait until rINTPND is changed for the case that the ISR is very short. */ ++ ++#define __REG(x) (*(volatile unsigned long *)(x)) ++#define __REGl(x) (*(volatile unsigned long *)(x)) ++#define __REGw(x) (*(volatile unsigned short *)(x)) ++#define __REGb(x) (*(volatile unsigned char *)(x)) ++#define __REG2(x,y) (*(volatile unsigned long *)((x) + (y))) ++ ++/* ++ * * Nand flash controller ++ * */ ++ ++#define NFDATA8 (*(volatile unsigned char *)0x4E000010) ++#define NFDATA16 (*(volatile unsigned short *)0x4E000010) ++#define NFDATA32 (*(volatile unsigned *)0x4E000010) ++ ++#define NFCONF __REG(0x4E000000) ++#define NFCONT __REG(0x4E000004) ++#define NFCMD __REG(0x4E000008) ++#define NFADDR __REGb(0x4E00000C) ++#define NFMECCD0 __REG(0x4E000014) ++#define NFMECCD1 __REG(0x4E000018) ++#define NFSECCD __REG(0x4E00001C) ++#define NFSTAT __REG(0x4E000020) ++#define NFESTAT0 __REG(0x4E000024) ++#define NFESTAT1 __REG(0x4E000028) ++#define NFMECC0 __REG(0x4E00002C) ++#define NFMECC1 __REG(0x4E000030) ++#define NFSECC __REG(0x4E000034) ++#define NFSBLK __REG(0x4E000038) ++ ++ ++#define S3C2410_MISCCR_USBDEV (0<<3) ++#define S3C2410_MISCCR_USBHOST (1<<3) ++ ++#define S3C2410_MISCCR_CLK0_MPLL (0<<4) ++#define S3C2410_MISCCR_CLK0_UPLL (1<<4) ++#define S3C2410_MISCCR_CLK0_FCLK (2<<4) ++#define S3C2410_MISCCR_CLK0_HCLK (3<<4) ++#define S3C2410_MISCCR_CLK0_PCLK (4<<4) ++#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4) ++#define S3C2410_MISCCR_CLK0_MASK (7<<4) ++ ++#define S3C2410_MISCCR_CLK1_MPLL (0<<8) ++#define S3C2410_MISCCR_CLK1_UPLL (1<<8) ++#define S3C2410_MISCCR_CLK1_FCLK (2<<8) ++#define S3C2410_MISCCR_CLK1_HCLK (3<<8) ++#define S3C2410_MISCCR_CLK1_PCLK (4<<8) ++#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8) ++#define S3C2410_MISCCR_CLK1_MASK (7<<8) ++ ++#define S3C2410_MISCCR_USBSUSPND0 (1<<12) ++#define S3C2410_MISCCR_USBSUSPND1 (1<<13) ++ ++#define S3C2410_MISCCR_nRSTCON (1<<16) ++ ++#define S3C2410_MISCCR_nEN_SCLK0 (1<<17) ++#define S3C2410_MISCCR_nEN_SCLK1 (1<<18) ++#define S3C2410_MISCCR_nEN_SCLKE (1<<19) ++#define S3C2410_MISCCR_SDSLEEP (7<<17) ++ ++#define S3C2410_CLKSLOW_UCLK_OFF (1<<7) ++#define S3C2410_CLKSLOW_MPLL_OFF (1<<5) ++#define S3C2410_CLKSLOW_SLOW (1<<4) ++#define S3C2410_CLKSLOW_SLOWVAL(x) (x) ++#define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7) ++ ++#endif /*__S3C2440_H__*/ +Index: u-boot/include/common.h +=================================================================== +--- u-boot.orig/include/common.h ++++ u-boot/include/common.h +@@ -454,7 +454,7 @@ + ulong get_OPB_freq (void); + ulong get_PCI_freq (void); + #endif +-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_LH7A40X) ++#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || defined(CONFIG_LH7A40X) + void s3c2410_irq(void); + #define ARM920_IRQ_CALLBACK s3c2410_irq + ulong get_FCLK (void); +Index: u-boot/cpu/arm920t/s3c24x0/usb_ohci.c +=================================================================== +--- u-boot.orig/cpu/arm920t/s3c24x0/usb_ohci.c ++++ u-boot/cpu/arm920t/s3c24x0/usb_ohci.c +@@ -44,6 +44,8 @@ + #include + #elif defined(CONFIG_S3C2410) + #include ++#elif defined(CONFIG_S3C2440) ++#include + #endif + + #include +Index: u-boot/cpu/arm920t/s3c24x0/speed.c +=================================================================== +--- u-boot.orig/cpu/arm920t/s3c24x0/speed.c ++++ u-boot/cpu/arm920t/s3c24x0/speed.c +@@ -30,12 +30,15 @@ + */ + + #include +-#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) ++#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \ ++ defined (CONFIG_S3C2440) || defined (CONFIG_TRAB) + + #if defined(CONFIG_S3C2400) + #include + #elif defined(CONFIG_S3C2410) + #include ++#elif defined(CONFIG_S3C2440) ++#include + #endif + + #define MPLL 0 +@@ -66,8 +69,12 @@ + m = ((r & 0xFF000) >> 12) + 8; + p = ((r & 0x003F0) >> 4) + 2; + s = r & 0x3; +- ++#ifndef CONFIG_S3C2440 + return((CONFIG_SYS_CLK_FREQ * m) / (p << s)); ++#else ++ /* To avoid integer overflow, changed the calc order */ ++ return( 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s )) ); ++#endif + } + + /* return FCLK frequency */ +@@ -81,7 +88,21 @@ + { + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + ++#ifndef CONFIG_S3C2440 + return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK()); ++#else ++ switch (clk_power->CLKDIVN & 0x6) { ++ case 0x0: ++ return get_FCLK(); ++ case 0x2: ++ return get_FCLK()/2; ++ case 0x4: ++ return (clk_power->CAMDIVN & 0x200) ? get_FCLK()/8 : get_FCLK()/4; ++ case 0x6: ++ return (clk_power->CAMDIVN & 0x100) ? get_FCLK()/6 : get_FCLK()/3; ++ } ++ return 0; ++#endif + } + + /* return PCLK frequency */ +@@ -98,4 +119,5 @@ + return(get_PLLCLK(UPLL)); + } + +-#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ ++#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || ++ defined(CONFIG_S3C2440) || defined (CONFIG_TRAB) */ +Index: u-boot/cpu/arm920t/s3c24x0/interrupts.c +=================================================================== +--- u-boot.orig/cpu/arm920t/s3c24x0/interrupts.c ++++ u-boot/cpu/arm920t/s3c24x0/interrupts.c +@@ -30,13 +30,16 @@ + */ + + #include +-#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) ++#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \ ++ defined(CONFIG_S3C2440) || defined (CONFIG_TRAB) + + #include + #if defined(CONFIG_S3C2400) + #include + #elif defined(CONFIG_S3C2410) + #include ++#elif defined(CONFIG_S3C2440) ++#include + #endif + + int timer_load_val = 0; +@@ -59,6 +62,7 @@ + /* use PWM Timer 4 because it has no output */ + /* prescaler for Timer 4 is 16 */ + timers->TCFG0 = 0x0f00; ++#ifndef CONFIG_S3C2440 + if (timer_load_val == 0) + { + /* +@@ -68,6 +72,9 @@ + */ + timer_load_val = get_PCLK()/(2 * 16 * 100); + } ++#else ++ timer_load_val = get_PCLK()/(2 * 16 * 100); ++#endif + /* load value for 10 ms timeout */ + lastdec = timers->TCNTB4 = timer_load_val; + /* auto load, manual update of Timer 4 */ +@@ -178,6 +185,7 @@ + tbclk = timer_load_val * 100; + #elif defined(CONFIG_SBC2410X) || \ + defined(CONFIG_SMDK2410) || \ ++ defined(CONFIG_SMDK2440) || \ + defined(CONFIG_VCMA9) + tbclk = CFG_HZ; + #else +@@ -232,4 +240,5 @@ + } + #endif /* USE_IRQ */ + +-#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ ++#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || ++ defined(CONFIG_S3C2440) || defined (CONFIG_TRAB) */ +Index: u-boot/cpu/arm920t/s3c24x0/serial.c +=================================================================== +--- u-boot.orig/cpu/arm920t/s3c24x0/serial.c ++++ u-boot/cpu/arm920t/s3c24x0/serial.c +@@ -19,12 +19,15 @@ + */ + + #include +-#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) ++#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \ ++ defined(CONFIG_S3C2440) || defined (CONFIG_TRAB) + + #if defined(CONFIG_S3C2400) || defined(CONFIG_TRAB) + #include + #elif defined(CONFIG_S3C2410) + #include ++#elif defined(CONFIG_S3C2440) ++#include + #endif + + DECLARE_GLOBAL_DATA_PTR; +@@ -180,4 +183,5 @@ + } + } + +-#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ ++#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || ++ defined(CONFIG_S3C2440) || defined (CONFIG_TRAB) */ +Index: u-boot/cpu/arm920t/s3c24x0/i2c.c +=================================================================== +--- u-boot.orig/cpu/arm920t/s3c24x0/i2c.c ++++ u-boot/cpu/arm920t/s3c24x0/i2c.c +@@ -34,6 +34,8 @@ + #include + #elif defined(CONFIG_S3C2410) + #include ++#elif defined(CONFIG_S3C2440) ++#include + #endif + #include + +@@ -63,7 +65,7 @@ + { + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + +-#ifdef CONFIG_S3C2410 ++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) + return (gpio->GPEDAT & 0x8000) >> 15; + #endif + #ifdef CONFIG_S3C2400 +@@ -82,7 +84,7 @@ + { + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); + +-#ifdef CONFIG_S3C2410 ++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) + gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14; + #endif + #ifdef CONFIG_S3C2400 +@@ -139,7 +141,7 @@ + } + + if ((status & I2CSTAT_BSY) || GetI2CSDA () == 0) { +-#ifdef CONFIG_S3C2410 ++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) + ulong old_gpecon = gpio->GPECON; + #endif + #ifdef CONFIG_S3C2400 +@@ -147,7 +149,7 @@ + #endif + /* bus still busy probably by (most) previously interrupted transfer */ + +-#ifdef CONFIG_S3C2410 ++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) + /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */ + gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000; + #endif +@@ -171,7 +173,7 @@ + udelay (1000); + + /* restore pin functions */ +-#ifdef CONFIG_S3C2410 ++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) + gpio->GPECON = old_gpecon; + #endif + #ifdef CONFIG_S3C2400 +Index: u-boot/drivers/usbdcore_s3c2410.c +=================================================================== +--- u-boot.orig/drivers/usbdcore_s3c2410.c ++++ u-boot/drivers/usbdcore_s3c2410.c +@@ -24,7 +24,7 @@ + + #include + +-#if defined(CONFIG_S3C2410) && defined(CONFIG_USB_DEVICE) ++#if (defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)) && defined(CONFIG_USB_DEVICE) + + #include + +Index: u-boot/drivers/usbtty.h +=================================================================== +--- u-boot.orig/drivers/usbtty.h ++++ u-boot/drivers/usbtty.h +@@ -29,7 +29,7 @@ + #include "usbdcore_mpc8xx.h" + #elif defined(CONFIG_OMAP1510) + #include "usbdcore_omap1510.h" +-#elif defined(CONFIG_S3C2410) ++#elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) + #include "usbdcore_s3c2410.h" + #endif + +Index: u-boot/cpu/arm920t/start.S +=================================================================== +--- u-boot.orig/cpu/arm920t/start.S ++++ u-boot/cpu/arm920t/start.S +@@ -31,7 +31,11 @@ + + #include + #include ++#if defined(CONFIG_S3C2410) + #include ++#elif defined(CONFIG_S3C2440) ++#include ++#endif + + + /* +@@ -142,14 +146,32 @@ + # define pWTCON 0x15300000 + # define INTMSK 0x14400008 /* Interupt-Controller base addresses */ + # define CLKDIVN 0x14800014 /* clock divisor register */ +-#elif defined(CONFIG_S3C2410) ++#elif defined(CONFIG_S3C2410) || defined (CONFIG_S3C2440) + # define pWTCON 0x53000000 + # define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ + # define INTSUBMSK 0x4A00001C + # define CLKDIVN 0x4C000014 /* clock divisor register */ + #endif + +-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) ++#if defined(CONFIG_S3C2410) ++# define INTSUBMSK_val 0x7ff ++# define MPLLCON_val ((0x90 << 12) + (0x7 << 4) + 0x0) /* 202 MHz */ ++# define UPLLCON_val ((0x78 << 12) + (0x2 << 4) + 0x3) ++# define CLKDIVN_val 3 /* FCLK:HCLK:PCLK = 1:2:4 */ ++#elif defined(CONFIG_S3C2440) ++# define INTSUBMSK_val 0xffff ++#if (CONFIG_SYS_CLK_FREQ == 16934400) ++# define MPLLCON_val ((0x61 << 12) + (0x1 << 4) + 0x2) /* 296.35 MHz */ ++# define UPLLCON_val ((0x3c << 12) + (0x4 << 4) + 0x2) /* 47.98 MHz */ ++#else if (CONFIG_SYS_CLK_FREQ == 12000000) ++# define MPLLCON_val ((0x44 << 12) + (0x1 << 4) + 0x1) /* 304.00 MHz */ ++# define UPLLCON_val ((0x38 << 12) + (0x2 << 4) + 0x2) /* 48.00 MHz */ ++#endif ++# define CLKDIVN_val 7 /* FCLK:HCLK:PCLK = 1:3:6 */ ++# define CAMDIVN 0x4C000018 ++#endif ++ ++#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) + ldr r0, =pWTCON + mov r1, #0x0 + str r1, [r0] +@@ -160,24 +182,34 @@ + mov r1, #0xffffffff + ldr r0, =INTMSK + str r1, [r0] +-# if defined(CONFIG_S3C2410) +- ldr r1, =0x3ff ++# if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) ++ ldr r1, =INTSUBMSK_val + ldr r0, =INTSUBMSK + str r1, [r0] + # endif + +- /* default FCLK is 202 MHz ! */ ++#if defined(CONFIG_S3C2440) ++ /* Make sure we get FCLK:HCLK:PCLK = 1:3:6 */ ++ ldr r0, =CAMDIVN ++ mov r1, #0 ++ str r1, [r0] ++#endif ++ ++ /* Clock asynchronous mode */ ++ mrc p15, 0, r1, c1, c0, 0 ++ orr r1, r1, #0xc0000000 ++ mcr p15, 0, r1, c1, c0, 0 ++ ++ + #define LOCKTIME 0x4c000000 + #define UPLLCON 0x4c000008 +-//#define MPLLCFG ((0x90 << 12) + (0x2 << 4) + 0x2) +-#define MPLLCFG ((0x90 << 12) + (0x7 << 4) + 0x0) +-#define UPLLCFG ((0x78 << 12) + (0x2 << 4) + 0x3) ++ + ldr r0, =LOCKTIME + mov r1, #0xffffff + str r1, [r0] + + ldr r0, =UPLLCON +- ldr r1, =UPLLCFG ++ ldr r1, =UPLLCON_val + str r1, [r0] + + /* Page 7-19, seven nops between UPLL and MPLL */ +@@ -189,12 +221,12 @@ + nop + nop + +- ldr r1, =MPLLCFG ++ ldr r1, =MPLLCON_val + str r1, [r0, #-4] /* MPLLCON */ + + /* FCLK:HCLK:PCLK = 1:2:4 */ + ldr r0, =CLKDIVN +- mov r1, #3 ++ mov r1, #CLKDIVN_val + str r1, [r0] + + #if 1 +@@ -222,7 +254,7 @@ + str r1, [r0, #0x28] + #endif + +-#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */ ++#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 || CONFIG_S3C2440 */ + + #ifndef CONFIG_SKIP_LOWLEVEL_INIT + #ifndef CONFIG_LL_INIT_NAND_ONLY +@@ -279,7 +311,7 @@ + #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && defined(CONFIG_LL_INIT_NAND_ONLY) + bl cpu_init_crit + #endif +-#if defined(CONFIG_S3C2410) ++#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) + /* ensure some refresh has happened */ + ldr r1, =0xfffff + 1: subs r1, r1, #1 +@@ -290,11 +322,12 @@ + ldr r0, [ r1 ] + tst r0, #0x02 /* is this resume from power down */ + ldrne pc, [r1, #4] /* gstatus3 */ +-#endif /* CONFIG_S3C2410 */ ++#endif /* CONFIG_S3C2410 || CONFIG_S3C2440 */ + #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + + /* mov r10, lr */ + ++#if defined(CONFIG_S3C2410) + @ reset NAND + mov r1, #S3C2410_NAND_BASE + ldr r2, =0xf842 @ initial value enable tacls=3,rph0=6,rph1=0 +@@ -314,6 +347,17 @@ + ldr r2, [r1, #oNFCONF] + orr r2, r2, #0x800 @ disable chip + str r2, [r1, #oNFCONF] ++#elif defined(CONFIG_S3C2440) ++ mov r1, #S3C2440_NAND_BASE ++ ldr r2, =0xfff0 @ initial value tacls=3,rph0=7,rph1=7 ++ ldr r3, [r1, #oNFCONF] ++ orr r3, r3, r2 ++ str r3, [r1, #oNFCONF] ++ ++ ldr r3, [r1, #oNFCONT] ++ orr r3, r3, #1 @ enable nand controller ++ str r3, [r1, #oNFCONT] ++#endif + + #if 0 + @ get ready to call C functions (for nand_read()) +@@ -382,7 +426,7 @@ + #endif /* CONFIG_S3C2410_NAND_BOOT */ + done_relocate: + +-#if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C2410) ++#if defined(CONFIG_USE_IRQ) && (defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)) + /* In the case of the S3C2410, if we've somehow magically (JTAG, ...) + ended up in RAM, then that ram is mapped to 0x30000000 and not 0. + So we need to copy the interrupt vectors, etc. */ +Index: u-boot/cpu/arm920t/s3c24x0/nand_read.c +=================================================================== +--- u-boot.orig/cpu/arm920t/s3c24x0/nand_read.c ++++ u-boot/cpu/arm920t/s3c24x0/nand_read.c +@@ -16,30 +16,141 @@ + */ + + #include ++#include + + #ifdef CONFIG_S3C2410_NAND_BOOT + + #define __REGb(x) (*(volatile unsigned char *)(x)) ++#define __REGw(x) (*(volatile unsigned short *)(x)) + #define __REGi(x) (*(volatile unsigned int *)(x)) + #define NF_BASE 0x4e000000 ++#if defined(CONFIG_S3C2410) + #define NFCONF __REGi(NF_BASE + 0x0) + #define NFCMD __REGb(NF_BASE + 0x4) + #define NFADDR __REGb(NF_BASE + 0x8) + #define NFDATA __REGb(NF_BASE + 0xc) + #define NFSTAT __REGb(NF_BASE + 0x10) ++#define NFSTAT_BUSY 1 ++#define nand_select() (NFCONF &= ~0x800) ++#define nand_deselect() (NFCONF |= 0x800) ++#define nand_clear_RnB() do {} while (0) ++#elif defined(CONFIG_S3C2440) ++#define NFCONF __REGi(NF_BASE + 0x0) ++#define NFCONT __REGi(NF_BASE + 0x4) ++#define NFCMD __REGb(NF_BASE + 0x8) ++#define NFADDR __REGb(NF_BASE + 0xc) ++#define NFDATA __REGb(NF_BASE + 0x10) ++#define NFDATA16 __REGw(NF_BASE + 0x10) ++#define NFSTAT __REGb(NF_BASE + 0x20) ++#define NFSTAT_BUSY 1 ++#define nand_select() (NFCONT &= ~(1 << 1)) ++#define nand_deselect() (NFCONT |= (1 << 1)) ++#define nand_clear_RnB() (NFSTAT |= (1 << 2)) ++#endif + +-#define BUSY 1 +-inline void wait_idle(void) ++static inline void nand_wait(void) + { + int i; + +- while (!(NFSTAT & BUSY)) ++ while (!(NFSTAT & NFSTAT_BUSY)) + for (i=0; i<10; i++); + } + +-#define NAND_SECTOR_SIZE 512 +-#define NAND_BLOCK_MASK (NAND_SECTOR_SIZE - 1) +-#define NAND_PAGE_SIZE 0x4000 ++#if defined(CONFIG_S3C2410) ++/* configuration for 2410 with 512byte sized flash */ ++#define NAND_PAGE_SIZE 512 ++#define BAD_BLOCK_OFFSET 517 ++#define NAND_BLOCK_MASK (NAND_PAGE_SIZE - 1) ++#define NAND_BLOCK_SIZE 0x4000 ++#else ++/* configuration for 2440 with 2048byte sized flash */ ++#define NAND_5_ADDR_CYCLE ++#define NAND_PAGE_SIZE 2048 ++#define BAD_BLOCK_OFFSET NAND_PAGE_SIZE ++#define NAND_BLOCK_MASK (NAND_PAGE_SIZE - 1) ++#define NAND_BLOCK_SIZE (NAND_PAGE_SIZE * 64) ++#endif ++ ++/* compile time failure in case of an invalid configuration */ ++#if defined(CONFIG_S3C2410) && (NAND_PAGE_SIZE != 512) ++#error "S3C2410 does not support nand page size != 512" ++#endif ++ ++static int is_bad_block(unsigned long i) ++{ ++ unsigned char data; ++ unsigned long page_num; ++ ++ /* FIXME: do this twice, for first and second page in block */ ++ ++ nand_clear_RnB(); ++#if (NAND_PAGE_SIZE == 512) ++ NFCMD = NAND_CMD_READOOB; /* 0x50 */ ++ NFADDR = BAD_BLOCK_OFFSET & 0xf; ++ NFADDR = (i >> 9) & 0xff; ++ NFADDR = (i >> 17) & 0xff; ++ NFADDR = (i >> 25) & 0xff; ++#elif (NAND_PAGE_SIZE == 2048) ++ page_num = i >> 11; /* addr / 2048 */ ++ NFCMD = NAND_CMD_READ0; ++ NFADDR = BAD_BLOCK_OFFSET & 0xff; ++ NFADDR = (BAD_BLOCK_OFFSET >> 8) & 0xff; ++ NFADDR = page_num & 0xff; ++ NFADDR = (page_num >> 8) & 0xff; ++ NFADDR = (page_num >> 16) & 0xff; ++ NFCMD = NAND_CMD_READSTART; ++#endif ++ nand_wait(); ++ data = (NFDATA & 0xff); ++ if (data != 0xff) ++ return 1; ++ ++ return 0; ++} ++ ++static int nand_read_page_ll(unsigned char *buf, unsigned long addr) ++{ ++ unsigned short *ptr16 = (unsigned short *)buf; ++ unsigned int i, page_num; ++ ++ nand_clear_RnB(); ++ ++ NFCMD = NAND_CMD_READ0; ++ ++#if (NAND_PAGE_SIZE == 512) ++ /* Write Address */ ++ NFADDR = addr & 0xff; ++ NFADDR = (addr >> 9) & 0xff; ++ NFADDR = (addr >> 17) & 0xff; ++ NFADDR = (addr >> 25) & 0xff; ++#elif (NAND_PAGE_SIZE == 2048) ++ page_num = addr >> 11; /* addr / 2048 */ ++ /* Write Address */ ++ NFADDR = 0; ++ NFADDR = 0; ++ NFADDR = page_num & 0xff; ++ NFADDR = (page_num >> 8) & 0xff; ++ NFADDR = (page_num >> 16) & 0xff; ++ NFCMD = NAND_CMD_READSTART; ++#else ++#error "unsupported nand page size" ++#endif ++ nand_wait(); ++ ++#if defined(CONFIG_S3C2410) ++ for (i = 0; i < NAND_PAGE_SIZE; i++) { ++ *buf = (NFDATA & 0xff); ++ buf++; ++ } ++#elif defined(CONFIG_S3C2440) ++ for (i = 0; i < NAND_PAGE_SIZE/2; i++) { ++ *ptr16 = NFDATA16; ++ ptr16++; ++ } ++#endif ++ ++ return NAND_PAGE_SIZE; ++} + + /* low level nand read function */ + int nand_read_ll(unsigned char *buf, unsigned long start_addr, int size) +@@ -50,47 +161,28 @@ + return -1; /* invalid alignment */ + + /* chip Enable */ +- NFCONF &= ~0x800; ++ nand_select(); ++ nand_clear_RnB(); + for (i=0; i<10; i++); + + for (i=start_addr; i < (start_addr + size);) { + #ifdef CONFIG_S3C2410_NAND_SKIP_BAD +- if (start_addr % NAND_PAGE_SIZE == 0) { +- unsigned char data; +- NFCMD = 0x50; +- NFADDR = 517&0xf; +- NFADDR = (i >> 9) & 0xff; +- NFADDR = (i >> 17) & 0xff; +- NFADDR = (i >> 25) & 0xff; +- wait_idle(); +- data = (NFDATA & 0xff); +- if (data != 0xff) { ++ if (start_addr % NAND_BLOCK_SIZE == 0) { ++ if (is_bad_block(i)) { + /* Bad block */ +- i += NAND_PAGE_SIZE; +- size += NAND_PAGE_SIZE; ++ i += NAND_BLOCK_SIZE; ++ size += NAND_BLOCK_SIZE; + continue; + } + } + #endif +- /* READ0 */ +- NFCMD = 0; +- +- /* Write Address */ +- NFADDR = i & 0xff; +- NFADDR = (i >> 9) & 0xff; +- NFADDR = (i >> 17) & 0xff; +- NFADDR = (i >> 25) & 0xff; +- +- wait_idle(); +- +- for (j=0; j < NAND_SECTOR_SIZE; j++, i++) { +- *buf = (NFDATA & 0xff); +- buf++; +- } ++ j = nand_read_page_ll(buf, i); ++ i += j; ++ buf += j; + } + + /* chip Disable */ +- NFCONF |= 0x800; /* chip disable */ ++ nand_deselect(); + + return 0; + } +Index: u-boot/cpu/arm920t/s3c24x0/nand.c +=================================================================== +--- u-boot.orig/cpu/arm920t/s3c24x0/nand.c ++++ u-boot/cpu/arm920t/s3c24x0/nand.c +@@ -36,24 +36,54 @@ + #define __REGi(x) (*(volatile unsigned int *)(x)) + + #define NF_BASE 0x4e000000 ++ + #define NFCONF __REGi(NF_BASE + 0x0) +-#define NFCMD __REGb(NF_BASE + 0x4) +-#define NFADDR __REGb(NF_BASE + 0x8) +-#define NFDATA __REGb(NF_BASE + 0xc) +-#define NFSTAT __REGb(NF_BASE + 0x10) ++ ++#if defined(CONFIG_S3C2410) ++ ++#define oNFCMD 0x4 ++#define oNFADDR 0x8 ++#define oNFDATA 0xc ++#define oNFSTAT 0x10 + #define NFECC0 __REGb(NF_BASE + 0x14) + #define NFECC1 __REGb(NF_BASE + 0x15) + #define NFECC2 __REGb(NF_BASE + 0x16) ++#define NFCONF_nFCE (1<<11) + + #define S3C2410_NFCONF_EN (1<<15) + #define S3C2410_NFCONF_512BYTE (1<<14) + #define S3C2410_NFCONF_4STEP (1<<13) + #define S3C2410_NFCONF_INITECC (1<<12) +-#define S3C2410_NFCONF_nFCE (1<<11) + #define S3C2410_NFCONF_TACLS(x) ((x)<<8) + #define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) + #define S3C2410_NFCONF_TWRPH1(x) ((x)<<0) + ++#elif defined(CONFIG_S3C2440) ++ ++#define oNFCMD 0x8 ++#define oNFADDR 0xc ++#define oNFDATA 0x10 ++#define oNFSTAT 0x20 ++ ++#define NFCONT __REGi(NF_BASE + 0x04) ++#define NFMECC0 __REGi(NF_BASE + 0x2C) ++#define NFCONF_nFCE (1<<1) ++#define S3C2440_NFCONF_INITECC (1<<4) ++#define S3C2440_NFCONF_MAINECCLOCK (1<<5) ++#define nand_select() (NFCONT &= ~(1 << 1)) ++#define nand_deselect() (NFCONT |= (1 << 1)) ++#define nand_clear_RnB() (NFSTAT |= (1 << 2)) ++#define nand_detect_RB() { while(!(NFSTAT&(1<<2))); } ++#define nand_wait() { while(!(NFSTAT & 0x4)); } /* RnB_TransDectect */ ++ ++#endif ++ ++#define NFCMD __REGb(NF_BASE + oNFCMD) ++#define NFADDR __REGb(NF_BASE + oNFADDR) ++#define NFDATA __REGb(NF_BASE + oNFDATA) ++#define NFSTAT __REGb(NF_BASE + oNFSTAT) ++ ++ + static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd) + { + struct nand_chip *chip = mtd->priv; +@@ -62,23 +92,31 @@ + + switch (cmd) { + case NAND_CTL_SETNCE: +- NFCONF &= ~S3C2410_NFCONF_nFCE; ++#if defined(CONFIG_S3C2410) ++ NFCONF &= ~NFCONF_nFCE; ++#elif defined(CONFIG_S3C2440) ++ NFCONT &= ~NFCONF_nFCE; ++#endif + DEBUGN("NFCONF=0x%08x\n", NFCONF); + break; + case NAND_CTL_CLRNCE: +- NFCONF |= S3C2410_NFCONF_nFCE; ++#if defined(CONFIG_S3C2410) ++ NFCONF |= NFCONF_nFCE; ++#elif defined(CONFIG_S3C2440) ++ NFCONT &= ~NFCONF_nFCE; ++#endif + DEBUGN("NFCONF=0x%08x\n", NFCONF); + break; + case NAND_CTL_SETALE: +- chip->IO_ADDR_W = NF_BASE + 0x8; ++ chip->IO_ADDR_W = NF_BASE + oNFADDR; + DEBUGN("SETALE\n"); + break; + case NAND_CTL_SETCLE: +- chip->IO_ADDR_W = NF_BASE + 0x4; ++ chip->IO_ADDR_W = NF_BASE + oNFCMD; + DEBUGN("SETCLE\n"); + break; + default: +- chip->IO_ADDR_W = NF_BASE + 0xc; ++ chip->IO_ADDR_W = NF_BASE + oNFDATA; + break; + } + return; +@@ -180,16 +218,21 @@ + /* initialize hardware */ + twrph0 = 3; twrph1 = 0; tacls = 0; + ++#if defined(CONFIG_S3C2410) + cfg = S3C2410_NFCONF_EN; + cfg |= S3C2410_NFCONF_TACLS(tacls - 1); + cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); + cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); + + NFCONF = cfg; +- //NFCONF = 0xf842; ++#elif defined(CONFIG_S3C2440) ++ twrph0 = 7; twrph1 = 7; tacls = 7; ++ NFCONF = (tacls<<12)|(twrph0<<8)|(twrph1<<4)|(0<<0); ++ NFCONT = (0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0); ++#endif + + /* initialize nand_chip data structure */ +- nand->IO_ADDR_R = nand->IO_ADDR_W = 0x4e00000c; ++ nand->IO_ADDR_R = nand->IO_ADDR_W = NF_BASE + oNFDATA; + + /* read_buf and write_buf are default */ + /* read_byte and write_byte are default */ +@@ -214,12 +257,23 @@ + nand->options = 0; + #endif + ++#if defined(CONFIG_S3C2440) ++/* ++ nand_select(); ++ nand_clear_RnB(); ++ NFCMD = NAND_CMD_RESET; ++ { volatile int i; for (i = 0; i < 10; i ++); } ++ nand_detect_RB(); ++ nand_deselect(); ++*/ ++#endif ++ + DEBUGN("end of nand_init\n"); + + return 0; + } + + #else +- #error "U-Boot legacy NAND support not available for S3C2410" ++ #error "U-Boot legacy NAND support not available for S3C24xx" + #endif + #endif +Index: u-boot/cpu/arm920t/s3c24x0/mmc.c +=================================================================== +--- u-boot.orig/cpu/arm920t/s3c24x0/mmc.c ++++ u-boot/cpu/arm920t/s3c24x0/mmc.c +@@ -137,6 +137,9 @@ + dcon |= S3C2410_SDIDCON_RXAFTERCMD|S3C2410_SDIDCON_XFER_RXSTART; + if (wide) + dcon |= S3C2410_SDIDCON_WIDEBUS; ++#if defined(CONFIG_S3C2440) ++ dcon |= S3C2440_SDIDCON_DS_WORD | S3C2440_SDIDCON_DATSTART; ++#endif + sdi->SDIDCON = dcon; + + /* send read command */ +@@ -394,13 +397,18 @@ + + clk_power->CLKCON |= (1 << 9); + ++ sdi->SDIBSIZE = 512; ++#if defined(CONFIG_S3C2410) + /* S3C2410 has some bug that prevents reliable operation at higher speed */ + //sdi->SDIPRE = 0x3e; /* SDCLK = PCLK/2 / (SDIPRE+1) = 396kHz */ +- sdi->SDIPRE = 0x02; /* SDCLK = PCLK/2 / (SDIPRE+1) = 396kHz */ +- sdi->SDIBSIZE = 512; ++ sdi->SDIPRE = 0x02; /* 2410: SDCLK = PCLK/2 / (SDIPRE+1) = 11MHz */ + sdi->SDIDTIMER = 0xffff; ++#elif defined(CONFIG_S3C2440) ++ sdi->SDIPRE = 0x05; /* 2410: SDCLK = PCLK / (SDIPRE+1) = 11MHz */ ++ sdi->SDIDTIMER = 0x7fffff; ++#endif + sdi->SDIIMSK = 0x0; +- sdi->SDICON = S3C2410_SDICON_FIFORESET|S3C2440_SDICON_MMCCLOCK; ++ sdi->SDICON = S3C2410_SDICON_FIFORESET|S3C2410_SDICON_CLOCKTYPE; + udelay(125000); /* FIXME: 74 SDCLK cycles */ + + mmc_csd.c_size = 0; diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2443.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2443.patch new file mode 100644 index 0000000000..62ae5592ab --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-s3c2443.patch @@ -0,0 +1,256 @@ +Index: u-boot/cpu/arm920t/start.S +=================================================================== +--- u-boot.orig/cpu/arm920t/start.S ++++ u-boot/cpu/arm920t/start.S +@@ -35,6 +35,8 @@ + #include + #elif defined(CONFIG_S3C2440) + #include ++#elif defined(CONFIG_S3C2443) ++#include + #endif + + +@@ -164,9 +166,15 @@ + # define UPLLCON_val ((0x3c << 12) + (0x4 << 4) + 0x2) + # define CLKDIVN_val 7 /* FCLK:HCLK:PCLK = 1:3:6 */ + # define CAMDIVN 0x4C000018 ++#elif defined(CONFIG_S3C2443) ++# define INTSUBMSK_val 0x1fffffff ++# define EPLLCON_val ((40 << 16) | (1 << 8) | (1)) /* 96 MHz */ ++# define MPLLCON_val ((81 << 16) | (2 << 8) | (0)) /* 1068 MHz */ ++# define CLKDIV0_val ((8 << 9) | (1 << 4) | (1 << 3) | (1 << 2) + #endif + +-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) ++#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || \ ++ defined(CONFIG_S3C2440) || defined(CONFIG_S3C2443) + ldr r0, =pWTCON + mov r1, #0x0 + str r1, [r0] +@@ -177,7 +185,7 @@ + mov r1, #0xffffffff + ldr r0, =INTMSK + str r1, [r0] +-# if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) ++# if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || defined(CONFIG_S3C2443) + ldr r1, =INTSUBMSK_val + ldr r0, =INTSUBMSK + str r1, [r0] +@@ -196,6 +204,43 @@ + mcr p15, 0, r1, c1, c0, 0 + + ++#if defined(CONFIG_S3C2443) ++#define LOCKCON0 0x4c000000 ++#define LOCKCON1 0x4c000004 ++#define MPLLCON 0x4c000010 ++#define EPLLCON 0x4c000018 ++ ++ ldr r0, =CLKDIV0 ++ ldr r1, =CLKDIV0_val ++ str r1, [r0] ++ ++ /* set safe (way too long) locktime for both PLLs */ ++ ldr r0, =LOCKCON0 ++ mov r1, #0xffffff ++ str r1, [r0] ++ ldr r0, =LOCKCON1 ++ str r1, [r0] ++ ++ /* configure MPLL */ ++ ldr r0, =MPLLCON ++ ldr r1, =MPLLCON_val ++ str r1, [r0] ++ ++ /* select MPLL clock out for SYSCLK */ ++ ldr r0, =CLKSRC ++ ldr r1, [r0] ++ orr r1, r1, #0x10 ++ str r1, [r0] ++ ++#if 0 ++ /* configure EPLL */ ++ ldr r0, =EPLLCON ++ ldr r1, =EPLLCON_val ++ str r1, [r0] ++#endif ++ ++ ++#else /* i.e. 2440, 2410 and 2440 */ + #define LOCKTIME 0x4c000000 + #define UPLLCON 0x4c000008 + +@@ -223,6 +268,7 @@ + ldr r0, =CLKDIVN + mov r1, #CLKDIVN_val + str r1, [r0] ++#endif + + #if 1 + /* enable uart */ +@@ -249,7 +295,7 @@ + str r1, [r0, #0x28] + #endif + +-#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 || CONFIG_S3C2440 */ ++#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 || CONFIG_S3C2440 || CONFIG_S3C2443 */ + + #ifndef CONFIG_SKIP_LOWLEVEL_INIT + #ifndef CONFIG_LL_INIT_NAND_ONLY +Index: u-boot/cpu/arm920t/s3c24x0/interrupts.c +=================================================================== +--- u-boot.orig/cpu/arm920t/s3c24x0/interrupts.c ++++ u-boot/cpu/arm920t/s3c24x0/interrupts.c +@@ -31,7 +31,8 @@ + + #include + #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \ +- defined(CONFIG_S3C2440) || defined (CONFIG_TRAB) ++ defined(CONFIG_S3C2440) || defined(CONFIG_S3C2443) || \ ++ defined (CONFIG_TRAB) + + #include + #if defined(CONFIG_S3C2400) +@@ -40,6 +41,8 @@ + #include + #elif defined(CONFIG_S3C2440) + #include ++#elif defined(CONFIG_S3C2443) ++#include + #endif + + int timer_load_val = 0; +@@ -186,6 +189,7 @@ + #elif defined(CONFIG_SBC2410X) || \ + defined(CONFIG_SMDK2410) || \ + defined(CONFIG_SMDK2440) || \ ++ defined(CONFIG_SMDK2443) || \ + defined(CONFIG_VCMA9) + tbclk = CFG_HZ; + #else +Index: u-boot/drivers/usbdcore_s3c2410.c +=================================================================== +--- u-boot.orig/drivers/usbdcore_s3c2410.c ++++ u-boot/drivers/usbdcore_s3c2410.c +@@ -24,7 +24,8 @@ + + #include + +-#if (defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)) && defined(CONFIG_USB_DEVICE) ++#if (defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \ ++ defined(CONFIG_S3C2443)) && defined(CONFIG_USB_DEVICE) + + #include + +Index: u-boot/include/s3c2443.h +=================================================================== +--- /dev/null ++++ u-boot/include/s3c2443.h +@@ -0,0 +1,106 @@ ++/* ++ * (C) Copyright 2007 OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __S3C2443_H ++#define __S3C2443_H ++ ++#include ++ ++/* CLOCK & POWER MANAGEMENT (see S3C2443 manual chapter 2) */ ++typedef struct { ++ S3C24X0_REG32 LOCKCON0; ++ S3C24X0_REG32 LOCKCON1; ++ S3C24X0_REG32 OSCSET; ++ S3C24X0_REG32 res1; ++ S3C24X0_REG32 MPLLCON; ++ S3C24X0_REG32 res2; ++ S3C24X0_REG32 EPLLCON; ++ S3C24X0_REG32 res3; ++ S3C24X0_REG32 CLKSRC; ++ S3C24X0_REG32 CLKDIV0; ++ S3C24X0_REG32 CLKDIV1; ++ S3C24X0_REG32 res4; ++ S3C24X0_REG32 HCLKCON; ++ S3C24X0_REG32 PCLKCON; ++ S3C24X0_REG32 SCLKCON; ++ S3C24X0_REG32 res5; ++ S3C24X0_REG32 PWRMODE; ++ S3C24X0_REG32 SWRST; ++ S3C24X0_REG32 res6[2]; ++ S3C24X0_REG32 BUSPRI0; ++ S3C24X0_REG32 res7[3]; ++} /*__attribute__((__packed__))*/ S3C2443_CLOCK_POWER; ++ ++/* NAND FLASH (see S3C2443 manual chapter 7) */ ++typedef struct { ++ S3C24X0_REG32 NFCONF; ++ S3C24X0_REG32 NFCONT; ++ S3C24X0_REG32 NFCMD; ++ S3C24X0_REG32 NFADDR; ++ S3C24X0_REG32 NFDATA; ++ S3C24X0_REG32 NFMECCD0; ++ S3C24X0_REG32 NFMECCD1; ++ S3C24X0_REG32 NFSECCD; ++ S3C24X0_REG32 NFSBLK; ++ S3C24X0_REG32 NFEBLK; ++ S3C24X0_REG32 NFSTAT; ++ S3C24X0_REG32 NFECCERR0; ++ S3C24X0_REG32 NFECCERR1; ++ S3C24X0_REG32 NFMECC0; ++ S3C24X0_REG32 NFMECC1; ++ S3C24X0_REG32 NFSECC; ++ S3C24X0_REG32 NFMLCBITPT; ++} /*__attribute__((__packed__))*/ S3C2443_NAND; ++ ++/* STATIC MEMORY (see S3C2443 manual chapter 5) */ ++struct s3c2443_sm_bank { ++ S3C24X0_REG32 SMBIDCYR; ++ S3C24X0_REG32 SMBWSTRDR; ++ S3C24X0_REG32 SMBWSTWRR; ++ S3C24X0_REG32 SMBWSTOENR; ++ S3C24X0_REG32 SMBWSTWENR; ++ S3C24X0_REG32 SMBCR; ++ S3C24X0_REG32 SMBSR; ++ S3C24X0_REG32 SMBWSTBRDR; ++}; ++ ++typedef struct { ++ struct s3c2443_sm_bank bank[5]; /* 0x4f000000..0x4f0000bf */ ++ S3C24X0_REG32 res[0x40]; /* 0x4f0000c0..0x4f0000ff */ ++ S3C24X0_REG32 SMBONETYPER; ++ S3C24X0_REG32 SMCSR; ++ S3C24X0_REG32 SMCCR; ++} /*__attribute__((__packed__))*/ S3C2443_SMEM; ++ ++ ++/* MOBILE DRAM (see S3C2443 manual chapter 6) */ ++typedef struct { ++ S3C24X0_REG32 BANKCFG; ++ S3C24X0_REG32 BANKCON1; ++ S3C24X0_REG32 BANKCON2; ++ S3C24X0_REG32 BANKCON3; ++ S3C24X0_REG32 REFRESH; ++ S3C24X0_REG32 TIMEOUT; ++} /*__attribute__((__packed__))*/ S3C2443_MDRAM ++ ++#endif /* __S3C2443_H */ diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-smdk2440.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-smdk2440.patch new file mode 100644 index 0000000000..09392ad2cf --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-smdk2440.patch @@ -0,0 +1,1481 @@ +Add support for the Samsung SMDK2440 development board + +Index: u-boot/Makefile +=================================================================== +--- u-boot.orig/Makefile ++++ u-boot/Makefile +@@ -2035,6 +2035,9 @@ + smdk2410_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 NULL s3c24x0 + ++smdk2440_config : unconfig ++ @$(MKCONFIG) $(@:_config=) arm arm920t smdk2440 NULL s3c24x0 ++ + SX1_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm925t sx1 + +Index: u-boot/include/configs/smdk2440.h +=================================================================== +--- /dev/null ++++ u-boot/include/configs/smdk2440.h +@@ -0,0 +1,296 @@ ++/* ++ * (C) Copyright 2002 ++ * Sysgo Real-Time Solutions, GmbH ++ * Marius Groeger ++ * Gary Jennejohn ++ * David Mueller ++ * ++ * Configuation settings for the SAMSUNG SMDK2440 board. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#if 0 ++/* If we want to start u-boot from usb bootloader in NOR flash */ ++#define CONFIG_SKIP_RELOCATE_UBOOT 1 ++#define CONFIG_SKIP_LOWLEVEL_INIT 1 ++#else ++/* If we want to start u-boot directly from within NAND flash */ ++#define CONFIG_LL_INIT_NAND_ONLY ++#define CONFIG_S3C2410_NAND_BOOT 1 ++#define CONFIG_S3C2410_NAND_SKIP_BAD 1 ++#endif ++ ++#define CFG_UBOOT_SIZE 0x40000 /* size of u-boot, for NAND loading */ ++ ++/* ++ * High Level Configuration Options ++ * (easy to change) ++ */ ++#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ ++#define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2440 SoC */ ++#define CONFIG_SMDK2440 1 /* on a SAMSUNG SMDK2440 Board */ ++ ++/* input clock of PLL */ ++#define CONFIG_SYS_CLK_FREQ 16934400/* SMDK2440 has 16.9344MHz input clock */ ++ ++ ++#define USE_920T_MMU 1 ++#define CONFIG_USE_IRQ 1 ++//#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ ++ ++/* ++ * Size of malloc() pool ++ */ ++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 2048*1024) ++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ ++ ++/* ++ * Hardware drivers ++ */ ++#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ ++#define CS8900_BASE 0x19000300 ++#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ ++ ++/* ++ * select serial console configuration ++ */ ++#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2440 */ ++#define CONFIG_HWFLOW 1 ++ ++/************************************************************ ++ * RTC ++ ************************************************************/ ++#define CONFIG_RTC_S3C24X0 1 ++ ++/* allow to overwrite serial and ethaddr */ ++#define CONFIG_ENV_OVERWRITE ++ ++#define CONFIG_BAUDRATE 115200 ++ ++/*********************************************************** ++ * Command definition ++ ***********************************************************/ ++#define CONFIG_COMMANDS \ ++ (CONFIG_CMD_DFL | \ ++ /*CFG_CMD_BSP | */ \ ++ CFG_CMD_CACHE | \ ++ CFG_CMD_DATE | \ ++ /*CFG_CMD_DHCP | */ \ ++ CFG_CMD_DIAG | \ ++ CFG_CMD_ELF | \ ++ CFG_CMD_EXT2 | \ ++ CFG_CMD_FAT | \ ++ /*CFG_CMD_HWFLOW | */ \ ++ /* CFG_CMD_IDE | */ \ ++ /* CFG_CMD_IRQ | */ \ ++ CFG_CMD_JFFS2 | \ ++ CFG_CMD_MMC | \ ++ CFG_CMD_NAND | \ ++ CFG_CMD_PING | \ ++ CFG_CMD_PORTIO | \ ++ CFG_CMD_REGINFO | \ ++ CFG_CMD_SAVES | \ ++ CFG_CMD_USB) ++ ++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ ++#include ++ ++#define CONFIG_BOOTDELAY 3 ++#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 console=ttySAC2,115200 loglevel=8" ++#define CONFIG_ETHADDR 00:0c:20:02:0a:5b ++#define CONFIG_NETMASK 255.255.255.0 ++#define CONFIG_IPADDR 192.168.1.100 ++#define CONFIG_SERVERIP 192.168.1.21 ++/*#define CONFIG_BOOTFILE "elinos-lart" */ ++//#define CONFIG_BOOTCOMMAND "nand read 0x32000000 0x34000 0x200000; bootm" ++#define CONFIG_BOOTCOMMAND "nand read.e 0x32000000 0x100000 0x200000; bootm" ++ ++#define CONFIG_DOS_PARTITION 1 ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ ++/* what's this ? it's not used anywhere */ ++#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ ++#endif ++ ++/* ++ * Miscellaneous configurable options ++ */ ++#define CFG_LONGHELP /* undef to save memory */ ++#define CFG_PROMPT "SMDK2440 # " /* Monitor Command Prompt */ ++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ ++#define CFG_MAXARGS 32 /* max number of command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ ++ ++#define CFG_MEMTEST_START 0x30000000 /* memtest works on */ ++#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ ++ ++#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ ++ ++#define CFG_LOAD_ADDR 0x32000000 /* default load address */ ++ ++/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ ++/* it to wrap 100 times (total 1562500) to get 1 sec. */ ++#define CFG_HZ 1562500 ++ ++/* valid baudrates */ ++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } ++ ++/*----------------------------------------------------------------------- ++ * Stack sizes ++ * ++ * The stack sizes are set up in start.S using the settings below ++ */ ++#define CONFIG_STACKSIZE (512*1024) /* regular stack */ ++#ifdef CONFIG_USE_IRQ ++#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */ ++#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ ++#endif ++ ++/* IDE/ATA config */ ++ ++#if 0 ++#define CFG_IDE_MAXBUS 1 ++#define CFG_IDE_MAXDEVICE 2 ++#define CFG_IDE_PREINIT 0 ++ ++#define CFG_ATA_BASE_ADDR ++#endif ++ ++#define CONFIG_USB_OHCI 1 ++ ++#define CONFIG_USB_DEVICE 1 ++#define CONFIG_USB_TTY 1 ++#define CFG_CONSOLE_IS_IN_ENV 1 ++#define CONFIG_USBD_VENDORID 0x1457 /* FIC */ ++#define CONFIG_USBD_PRODUCTID_GSERIAL 0x5120 /* gserial */ ++#define CONFIG_USBD_PRODUCTID_CDCACM 0x511b /* SMDK2440 CDC ACM */ ++#define CONFIG_USBD_MANUFACTURER "OpenMoko, Inc." ++#define CONFIG_USBD_PRODUCT_NAME "S3C2440 Bootloader " U_BOOT_VERSION ++#define CONFIG_EXTRA_ENV_SETTINGS "usbtty=cdc_acm\0" ++#define CONFIG_USBD_DFU 1 ++#define CONFIG_USBD_DFU_XFER_SIZE 4096 ++#define CONFIG_USBD_DFU_INTERFACE 2 ++ ++/*----------------------------------------------------------------------- ++ * Physical Memory Map ++ */ ++#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ ++#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ ++#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ ++ ++#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ ++ ++#define CFG_FLASH_BASE PHYS_FLASH_1 ++ ++/*----------------------------------------------------------------------- ++ * FLASH and environment organization ++ */ ++ ++#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ ++#if 0 ++#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ ++#endif ++ ++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ ++#ifdef CONFIG_AMD_LV800 ++#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ ++#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ ++#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */ ++#endif ++#ifdef CONFIG_AMD_LV400 ++#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ ++#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ ++#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */ ++#endif ++ ++/* timeout values are in ticks */ ++#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ ++#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ ++ ++#define CFG_ENV_IS_IN_NAND 1 ++#define CFG_ENV_SIZE 0x20000 /* 128k Total Size of Environment Sector */ ++#define CFG_ENV_OFFSET_OOB 1 ++#define CFG_PREBOOT_OVERRIDE 1 ++ ++#define NAND_MAX_CHIPS 1 ++#define CFG_NAND_BASE 0x4e000000 ++#define CFG_MAX_NAND_DEVICE 1 ++ ++#define CONFIG_MMC 1 ++#define CFG_MMC_BASE 0xff000000 ++ ++#define CONFIG_EXT2 1 ++ ++#define CONFIG_NEW_QT2440 0 ++ ++/* FAT driver in u-boot is broken currently */ ++#define CONFIG_FAT 1 ++#define CONFIG_SUPPORT_VFAT ++ ++#if 1 ++/* JFFS2 driver */ ++#define CONFIG_JFFS2_CMDLINE 1 ++#define CONFIG_JFFS2_NAND 1 ++#define CONFIG_JFFS2_NAND_DEV 0 ++//#define CONFIG_JFFS2_NAND_OFF 0x634000 ++//#define CONFIG_JFFS2_NAND_SIZE 0x39cc000 ++#endif ++ ++/* ATAG configuration */ ++#define CONFIG_INITRD_TAG 1 ++#define CONFIG_SETUP_MEMORY_TAGS 1 ++#define CONFIG_CMDLINE_TAG 1 ++#if 0 ++#define CONFIG_SERIAL_TAG 1 ++#define CONFIG_REVISION_TAG 1 ++#endif ++ ++ ++#if 0 ++#define CONFIG_VIDEO ++#define CONFIG_VIDEO_S3C2410 ++#define CONFIG_CFB_CONSOLE ++#define CONFIG_VIDEO_LOGO ++#define CONFIG_VGA_AS_SINGLE_DEVICE ++ ++#define VIDEO_KBD_INIT_FCT 0 ++#define VIDEO_TSTC_FCT serial_tstc ++#define VIDEO_GETC_FCT serial_getc ++ ++#define LCD_VIDEO_ADDR 0x33d00000 ++#endif ++ ++#define CONFIG_S3C2410_NAND_BBT 1 ++//#define CONFIG_S3C2410_NAND_HWECC 1 ++ ++#define CFG_NAND_YAFFS_WRITE ++#define CFG_NAND_YAFFS1_NEW_OOB_LAYOUT ++ ++#define MTDIDS_DEFAULT "nand0=smdk2440-nand" ++#define MTPARTS_DEFAULT "smdk2440-nand:0x00100000(u-boot),0x00200000(kernel),0x00200000(update),0x00100000(splash),0x01400000(jffs2),-(temp)" ++#define CFG_NAND_DYNPART_MTD_KERNEL_NAME "smdk2440-nand" ++#define CONFIG_NAND_DYNPART ++ ++#endif /* __CONFIG_H */ +Index: u-boot/include/configs/smdk2440nand.h +=================================================================== +--- /dev/null ++++ u-boot/include/configs/smdk2440nand.h +@@ -0,0 +1,47 @@ ++/* ++ * (C) Copyright 2004 ++ * Samsung Electronics : SW.LEE ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ */ ++ ++#ifndef __SMDK2440_NAND_H ++#define __SMDK2440_NAND_H ++ ++#define CFG_ENV_NAND_BLOCK 8 ++ ++#if 0 //old flash ++#define NAND_OOB_SIZE (16) ++#define NAND_PAGES_IN_BLOCK (32) ++#define NAND_PAGE_SIZE (512) ++ ++#define NAND_BLOCK_SIZE (NAND_PAGE_SIZE*NAND_PAGES_IN_BLOCK) ++#define NAND_BLOCK_MASK (NAND_BLOCK_SIZE - 1) ++#define NAND_PAGE_MASK (NAND_PAGE_SIZE - 1) ++#else //new flash ++#define NAND_OOB_SIZE (64) ++#define NAND_PAGES_IN_BLOCK (64) ++#define NAND_PAGE_SIZE (2048) ++ ++#define NAND_BLOCK_SIZE (NAND_PAGE_SIZE*NAND_PAGES_IN_BLOCK) ++#define NAND_BLOCK_MASK (NAND_BLOCK_SIZE - 1) ++#define NAND_PAGE_MASK (NAND_PAGE_SIZE - 1) ++ ++#endif ++ ++ ++ ++//#define NAND_3_ADDR_CYCLE 1 ++//#define S3C24X0_16BIT_NAND 1 ++ ++#ifdef KINGFISH ++#undef S3C24X0_16BIT_NAND ++#define S3C24X0_16BIT_NAND 1 ++#endif ++ ++#endif ++ +Index: u-boot/board/smdk2440/Makefile +=================================================================== +--- /dev/null ++++ u-boot/board/smdk2440/Makefile +@@ -0,0 +1,67 @@ ++# ++# (C) Copyright 2000-2006 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).a ++ ++COBJS := smdk2440.o flash.o udc.o ++SOBJS := lowlevel_init.o ++ ++.PHONY: all ++ ++all: $(LIB) lowlevel_foo.bin ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) ++ ++lowlevel_foo.o: lowlevel_foo.S ++ $(CC) -c -DTEXT_BASE=0x33F80000 -march=armv4 \ ++ -o lowlevel_foo.o lowlevel_foo.S ++ ++lowlevel_foo: lowlevel_foo.o lowlevel_init.o lowlevel_foo.lds ++ $(LD) -T ./lowlevel_foo.lds -Ttext 0x33f80000 -Bstatic \ ++ lowlevel_init.o lowlevel_foo.o -o lowlevel_foo ++ ++lowlevel_foo.bin: lowlevel_foo ++ $(CROSS_COMPILE)objcopy --gap-fill=0xff -O binary \ ++ lowlevel_foo lowlevel_foo.bin ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak .depend ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +Index: u-boot/board/smdk2440/config.mk +=================================================================== +--- /dev/null ++++ u-boot/board/smdk2440/config.mk +@@ -0,0 +1,29 @@ ++# ++# (C) Copyright 2002 ++# Gary Jennejohn, DENX Software Engineering, ++# David Mueller, ELSOFT AG, ++# ++# SAMSUNG SMDK2440 board with S3C2440 (ARM920T) cpu ++# ++# see http://www.samsung.com/ for more information on SAMSUNG ++# ++ ++CONFIG_USB_DFU_VENDOR=0x1457 ++CONFIG_USB_DFU_PRODUCT=0x511b ++CONFIG_USB_DFU_REVISION=0x0100 ++ ++# ++# SMDK2440 has 1 bank of 64 MB DRAM ++# ++# 3000'0000 to 3400'0000 ++# ++# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 ++# optionally with a ramdisk at 3080'0000 ++# ++# we load ourself to 33F8'0000 ++# ++# download area is 3300'0000 ++# ++ ++ ++TEXT_BASE = 0x33F80000 +Index: u-boot/board/smdk2440/flash.c +=================================================================== +--- /dev/null ++++ u-boot/board/smdk2440/flash.c +@@ -0,0 +1,433 @@ ++/* ++ * (C) Copyright 2002 ++ * Sysgo Real-Time Solutions, GmbH ++ * Alex Zuepke ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++ ++ulong myflush (void); ++ ++ ++#define FLASH_BANK_SIZE PHYS_FLASH_SIZE ++#define MAIN_SECT_SIZE 0x10000 /* 64 KB */ ++ ++flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; ++ ++ ++#define CMD_READ_ARRAY 0x000000F0 ++#define CMD_UNLOCK1 0x000000AA ++#define CMD_UNLOCK2 0x00000055 ++#define CMD_ERASE_SETUP 0x00000080 ++#define CMD_ERASE_CONFIRM 0x00000030 ++#define CMD_PROGRAM 0x000000A0 ++#define CMD_UNLOCK_BYPASS 0x00000020 ++ ++#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1))) ++#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1))) ++ ++#define BIT_ERASE_DONE 0x00000080 ++#define BIT_RDY_MASK 0x00000080 ++#define BIT_PROGRAM_ERROR 0x00000020 ++#define BIT_TIMEOUT 0x80000000 /* our flag */ ++ ++#define READY 1 ++#define ERR 2 ++#define TMO 4 ++ ++/*----------------------------------------------------------------------- ++ */ ++ ++ulong flash_init (void) ++{ ++ int i, j; ++ ulong size = 0; ++ ++ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { ++ ulong flashbase = 0; ++ ++ flash_info[i].flash_id = ++#if defined(CONFIG_AMD_LV400) ++ (AMD_MANUFACT & FLASH_VENDMASK) | ++ (AMD_ID_LV400B & FLASH_TYPEMASK); ++#elif defined(CONFIG_AMD_LV800) ++ (AMD_MANUFACT & FLASH_VENDMASK) | ++ (AMD_ID_LV800B & FLASH_TYPEMASK); ++#else ++#error "Unknown flash configured" ++#endif ++ flash_info[i].size = FLASH_BANK_SIZE; ++ flash_info[i].sector_count = CFG_MAX_FLASH_SECT; ++ memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); ++ if (i == 0) ++ flashbase = PHYS_FLASH_1; ++ else ++ panic ("configured too many flash banks!\n"); ++ for (j = 0; j < flash_info[i].sector_count; j++) { ++ if (j <= 3) { ++ /* 1st one is 16 KB */ ++ if (j == 0) { ++ flash_info[i].start[j] = ++ flashbase + 0; ++ } ++ ++ /* 2nd and 3rd are both 8 KB */ ++ if ((j == 1) || (j == 2)) { ++ flash_info[i].start[j] = ++ flashbase + 0x4000 + (j - ++ 1) * ++ 0x2000; ++ } ++ ++ /* 4th 32 KB */ ++ if (j == 3) { ++ flash_info[i].start[j] = ++ flashbase + 0x8000; ++ } ++ } else { ++ flash_info[i].start[j] = ++ flashbase + (j - 3) * MAIN_SECT_SIZE; ++ } ++ } ++ size += flash_info[i].size; ++ } ++ ++ flash_protect (FLAG_PROTECT_SET, ++ CFG_FLASH_BASE, ++ CFG_FLASH_BASE + monitor_flash_len - 1, ++ &flash_info[0]); ++ ++ flash_protect (FLAG_PROTECT_SET, ++ CFG_ENV_ADDR, ++ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); ++ ++ return size; ++} ++ ++/*----------------------------------------------------------------------- ++ */ ++void flash_print_info (flash_info_t * info) ++{ ++ int i; ++ ++ switch (info->flash_id & FLASH_VENDMASK) { ++ case (AMD_MANUFACT & FLASH_VENDMASK): ++ printf ("AMD: "); ++ break; ++ default: ++ printf ("Unknown Vendor "); ++ break; ++ } ++ ++ switch (info->flash_id & FLASH_TYPEMASK) { ++ case (AMD_ID_LV400B & FLASH_TYPEMASK): ++ printf ("1x Amd29LV400BB (4Mbit)\n"); ++ break; ++ case (AMD_ID_LV800B & FLASH_TYPEMASK): ++ printf ("1x Amd29LV800BB (8Mbit)\n"); ++ break; ++ default: ++ printf ("Unknown Chip Type\n"); ++ goto Done; ++ break; ++ } ++ ++ printf (" Size: %ld MB in %d Sectors\n", ++ info->size >> 20, info->sector_count); ++ ++ printf (" Sector Start Addresses:"); ++ for (i = 0; i < info->sector_count; i++) { ++ if ((i % 5) == 0) { ++ printf ("\n "); ++ } ++ printf (" %08lX%s", info->start[i], ++ info->protect[i] ? " (RO)" : " "); ++ } ++ printf ("\n"); ++ ++ Done:; ++} ++ ++/*----------------------------------------------------------------------- ++ */ ++ ++int flash_erase (flash_info_t * info, int s_first, int s_last) ++{ ++ ushort result; ++ int iflag, cflag, prot, sect; ++ int rc = ERR_OK; ++ int chip; ++ ++ /* first look for protection bits */ ++ ++ if (info->flash_id == FLASH_UNKNOWN) ++ return ERR_UNKNOWN_FLASH_TYPE; ++ ++ if ((s_first < 0) || (s_first > s_last)) { ++ return ERR_INVAL; ++ } ++ ++ if ((info->flash_id & FLASH_VENDMASK) != ++ (AMD_MANUFACT & FLASH_VENDMASK)) { ++ return ERR_UNKNOWN_FLASH_VENDOR; ++ } ++ ++ prot = 0; ++ for (sect = s_first; sect <= s_last; ++sect) { ++ if (info->protect[sect]) { ++ prot++; ++ } ++ } ++ if (prot) ++ return ERR_PROTECTED; ++ ++ /* ++ * Disable interrupts which might cause a timeout ++ * here. Remember that our exception vectors are ++ * at address 0 in the flash, and we don't want a ++ * (ticker) exception to happen while the flash ++ * chip is in programming mode. ++ */ ++ cflag = icache_status (); ++ icache_disable (); ++ iflag = disable_interrupts (); ++ ++ /* Start erase on unprotected sectors */ ++ for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { ++ printf ("Erasing sector %2d ... ", sect); ++ ++ /* arm simple, non interrupt dependent timer */ ++ reset_timer_masked (); ++ ++ if (info->protect[sect] == 0) { /* not protected */ ++ vu_short *addr = (vu_short *) (info->start[sect]); ++ ++ MEM_FLASH_ADDR1 = CMD_UNLOCK1; ++ MEM_FLASH_ADDR2 = CMD_UNLOCK2; ++ MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; ++ ++ MEM_FLASH_ADDR1 = CMD_UNLOCK1; ++ MEM_FLASH_ADDR2 = CMD_UNLOCK2; ++ *addr = CMD_ERASE_CONFIRM; ++ ++ /* wait until flash is ready */ ++ chip = 0; ++ ++ do { ++ result = *addr; ++ ++ /* check timeout */ ++ if (get_timer_masked () > ++ CFG_FLASH_ERASE_TOUT) { ++ MEM_FLASH_ADDR1 = CMD_READ_ARRAY; ++ chip = TMO; ++ break; ++ } ++ ++ if (!chip ++ && (result & 0xFFFF) & BIT_ERASE_DONE) ++ chip = READY; ++ ++ if (!chip ++ && (result & 0xFFFF) & BIT_PROGRAM_ERROR) ++ chip = ERR; ++ ++ } while (!chip); ++ ++ MEM_FLASH_ADDR1 = CMD_READ_ARRAY; ++ ++ if (chip == ERR) { ++ rc = ERR_PROG_ERROR; ++ goto outahere; ++ } ++ if (chip == TMO) { ++ rc = ERR_TIMOUT; ++ goto outahere; ++ } ++ ++ printf ("ok.\n"); ++ } else { /* it was protected */ ++ ++ printf ("protected!\n"); ++ } ++ } ++ ++ if (ctrlc ()) ++ printf ("User Interrupt!\n"); ++ ++ outahere: ++ /* allow flash to settle - wait 10 ms */ ++ udelay_masked (10000); ++ ++ if (iflag) ++ enable_interrupts (); ++ ++ if (cflag) ++ icache_enable (); ++ ++ return rc; ++} ++ ++/*----------------------------------------------------------------------- ++ * Copy memory to flash ++ */ ++ ++volatile static int write_hword (flash_info_t * info, ulong dest, ushort data) ++{ ++ vu_short *addr = (vu_short *) dest; ++ ushort result; ++ int rc = ERR_OK; ++ int cflag, iflag; ++ int chip; ++ ++ /* ++ * Check if Flash is (sufficiently) erased ++ */ ++ result = *addr; ++ if ((result & data) != data) ++ return ERR_NOT_ERASED; ++ ++ ++ /* ++ * Disable interrupts which might cause a timeout ++ * here. Remember that our exception vectors are ++ * at address 0 in the flash, and we don't want a ++ * (ticker) exception to happen while the flash ++ * chip is in programming mode. ++ */ ++ cflag = icache_status (); ++ icache_disable (); ++ iflag = disable_interrupts (); ++ ++ MEM_FLASH_ADDR1 = CMD_UNLOCK1; ++ MEM_FLASH_ADDR2 = CMD_UNLOCK2; ++ MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS; ++ *addr = CMD_PROGRAM; ++ *addr = data; ++ ++ /* arm simple, non interrupt dependent timer */ ++ reset_timer_masked (); ++ ++ /* wait until flash is ready */ ++ chip = 0; ++ do { ++ result = *addr; ++ ++ /* check timeout */ ++ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { ++ chip = ERR | TMO; ++ break; ++ } ++ if (!chip && ((result & 0x80) == (data & 0x80))) ++ chip = READY; ++ ++ if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { ++ result = *addr; ++ ++ if ((result & 0x80) == (data & 0x80)) ++ chip = READY; ++ else ++ chip = ERR; ++ } ++ ++ } while (!chip); ++ ++ *addr = CMD_READ_ARRAY; ++ ++ if (chip == ERR || *addr != data) ++ rc = ERR_PROG_ERROR; ++ ++ if (iflag) ++ enable_interrupts (); ++ ++ if (cflag) ++ icache_enable (); ++ ++ return rc; ++} ++ ++/*----------------------------------------------------------------------- ++ * Copy memory to flash. ++ */ ++ ++int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) ++{ ++ ulong cp, wp; ++ int l; ++ int i, rc; ++ ushort data; ++ ++ wp = (addr & ~1); /* get lower word aligned address */ ++ ++ /* ++ * handle unaligned start bytes ++ */ ++ if ((l = addr - wp) != 0) { ++ data = 0; ++ for (i = 0, cp = wp; i < l; ++i, ++cp) { ++ data = (data >> 8) | (*(uchar *) cp << 8); ++ } ++ for (; i < 2 && cnt > 0; ++i) { ++ data = (data >> 8) | (*src++ << 8); ++ --cnt; ++ ++cp; ++ } ++ for (; cnt == 0 && i < 2; ++i, ++cp) { ++ data = (data >> 8) | (*(uchar *) cp << 8); ++ } ++ ++ if ((rc = write_hword (info, wp, data)) != 0) { ++ return (rc); ++ } ++ wp += 2; ++ } ++ ++ /* ++ * handle word aligned part ++ */ ++ while (cnt >= 2) { ++ data = *((vu_short *) src); ++ if ((rc = write_hword (info, wp, data)) != 0) { ++ return (rc); ++ } ++ src += 2; ++ wp += 2; ++ cnt -= 2; ++ } ++ ++ if (cnt == 0) { ++ return ERR_OK; ++ } ++ ++ /* ++ * handle unaligned tail bytes ++ */ ++ data = 0; ++ for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { ++ data = (data >> 8) | (*src++ << 8); ++ --cnt; ++ } ++ for (; i < 2; ++i, ++cp) { ++ data = (data >> 8) | (*(uchar *) cp << 8); ++ } ++ ++ return write_hword (info, wp, data); ++} +Index: u-boot/board/smdk2440/lowlevel_init.S +=================================================================== +--- /dev/null ++++ u-boot/board/smdk2440/lowlevel_init.S +@@ -0,0 +1,167 @@ ++/* ++ * Memory Setup stuff - taken from blob memsetup.S ++ * ++ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and ++ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) ++ * ++ * Modified for the Samsung SMDK2410 by ++ * (C) Copyright 2002 ++ * David Mueller, ELSOFT AG, ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++ ++#include ++#include ++ ++ ++/* some parameters for the board */ ++ ++/* ++ * ++ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S ++ * ++ * Copyright (C) 2002 Samsung Electronics SW.LEE ++ * ++ */ ++ ++#define BWSCON 0x48000000 ++ ++/* BWSCON */ ++#define DW8 (0x0) ++#define DW16 (0x1) ++#define DW32 (0x2) ++#define WAIT (0x1<<2) ++#define UBLB (0x1<<3) ++ ++#define B1_BWSCON (DW32) ++#define B2_BWSCON (DW16) ++#define B3_BWSCON (DW16 + WAIT + UBLB) ++#define B4_BWSCON (DW16) ++#define B5_BWSCON (DW16) ++#define B6_BWSCON (DW32) ++#define B7_BWSCON (DW32) ++ ++/* BANK0CON */ ++#define B0_Tacs 0x0 /* 0clk */ ++#define B0_Tcos 0x0 /* 0clk */ ++#define B0_Tacc 0x7 /* 14clk */ ++#define B0_Tcoh 0x0 /* 0clk */ ++#define B0_Tah 0x0 /* 0clk */ ++#define B0_Tacp 0x0 ++#define B0_PMC 0x0 /* normal */ ++ ++/* BANK1CON */ ++#define B1_Tacs 0x0 /* 0clk */ ++#define B1_Tcos 0x0 /* 0clk */ ++#define B1_Tacc 0x7 /* 14clk */ ++#define B1_Tcoh 0x0 /* 0clk */ ++#define B1_Tah 0x0 /* 0clk */ ++#define B1_Tacp 0x0 ++#define B1_PMC 0x0 ++ ++#define B2_Tacs 0x0 ++#define B2_Tcos 0x0 ++#define B2_Tacc 0x7 ++#define B2_Tcoh 0x0 ++#define B2_Tah 0x0 ++#define B2_Tacp 0x0 ++#define B2_PMC 0x0 ++ ++#define B3_Tacs 0x0 /* 0clk */ ++#define B3_Tcos 0x3 /* 4clk */ ++#define B3_Tacc 0x7 /* 14clk */ ++#define B3_Tcoh 0x1 /* 1clk */ ++#define B3_Tah 0x0 /* 0clk */ ++#define B3_Tacp 0x3 /* 6clk */ ++#define B3_PMC 0x0 /* normal */ ++ ++#define B4_Tacs 0x0 /* 0clk */ ++#define B4_Tcos 0x0 /* 0clk */ ++#define B4_Tacc 0x7 /* 14clk */ ++#define B4_Tcoh 0x0 /* 0clk */ ++#define B4_Tah 0x0 /* 0clk */ ++#define B4_Tacp 0x0 ++#define B4_PMC 0x0 /* normal */ ++ ++#define B5_Tacs 0x0 /* 0clk */ ++#define B5_Tcos 0x0 /* 0clk */ ++#define B5_Tacc 0x7 /* 14clk */ ++#define B5_Tcoh 0x0 /* 0clk */ ++#define B5_Tah 0x0 /* 0clk */ ++#define B5_Tacp 0x0 ++#define B5_PMC 0x0 /* normal */ ++ ++#define B6_MT 0x3 /* SDRAM */ ++#define B6_Trcd 0x1 ++#define B6_SCAN 0x1 /* 9bit */ ++ ++#define B7_MT 0x3 /* SDRAM */ ++#define B7_Trcd 0x1 /* 3clk */ ++#define B7_SCAN 0x1 /* 9bit */ ++ ++/* REFRESH parameter */ ++#define REFEN 0x1 /* Refresh enable */ ++#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ ++#define Trp 0x0 /* 2clk */ ++#define Trc 0x3 /* 7clk */ ++#define Tchr 0x2 /* 3clk */ ++#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ ++/**************************************/ ++ ++_TEXT_BASE: ++ .word TEXT_BASE ++ ++.globl lowlevel_init ++lowlevel_init: ++ /* memory control configuration */ ++ /* make r0 relative the current location so that it */ ++ /* reads SMRDATA out of FLASH rather than memory ! */ ++ ldr r0, =SMRDATA ++ ldr r1, _TEXT_BASE ++ sub r0, r0, r1 ++ ldr r1, =BWSCON /* Bus Width Status Controller */ ++ add r2, r0, #13*4 ++0: ++ ldr r3, [r0], #4 ++ str r3, [r1], #4 ++ cmp r2, r0 ++ bne 0b ++ ++ /* everything is fine now */ ++ mov pc, lr ++ ++ .ltorg ++/* the literal pools origin */ ++ ++SMRDATA: ++ .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) ++ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ++ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ++ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ++ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ++ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ++ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ++ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ++ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ++ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) ++ .word 0x32 ++ .word 0x30 ++ .word 0x30 +Index: u-boot/board/smdk2440/smdk2440.c +=================================================================== +--- /dev/null ++++ u-boot/board/smdk2440/smdk2440.c +@@ -0,0 +1,152 @@ ++/* ++ * (C) Copyright 2002 ++ * Sysgo Real-Time Solutions, GmbH ++ * Marius Groeger ++ * ++ * (C) Copyright 2002 ++ * David Mueller, ELSOFT AG, ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#define FCLK_SPEED 1 ++ ++#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ ++#define M_MDIV 0xC3 ++#define M_PDIV 0x4 ++#define M_SDIV 0x1 ++#elif FCLK_SPEED==1 /* Fout = 399.65MHz */ ++#define M_MDIV 0x6e ++#define M_PDIV 0x3 ++#define M_SDIV 0x1 ++#endif ++ ++#define USB_CLOCK 1 ++ ++#if USB_CLOCK==0 ++#define U_M_MDIV 0xA1 ++#define U_M_PDIV 0x3 ++#define U_M_SDIV 0x1 ++#elif USB_CLOCK==1 ++#define U_M_MDIV 0x3c ++#define U_M_PDIV 0x4 ++#define U_M_SDIV 0x2 ++#endif ++ ++static inline void delay (unsigned long loops) ++{ ++ __asm__ volatile ("1:\n" ++ "subs %0, %1, #1\n" ++ "bne 1b":"=r" (loops):"0" (loops)); ++} ++ ++/* ++ * Miscellaneous platform dependent initialisations ++ */ ++ ++int board_init (void) ++{ ++ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ ++ /* to reduce PLL lock time, adjust the LOCKTIME register */ ++ clk_power->LOCKTIME = 0xFFFFFF; ++ ++ /* configure MPLL */ ++ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); ++ ++ /* some delay between MPLL and UPLL */ ++ delay (4000); ++ ++ /* configure UPLL */ ++ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); ++ ++ /* some delay between MPLL and UPLL */ ++ delay (8000); ++ ++ /* set up the I/O ports */ ++ gpio->GPACON = 0x007FFFFF; ++ gpio->GPBCON = 0x002a9655; ++ gpio->GPBUP = 0x000007FF; ++ gpio->GPCCON = 0xAAAAAAAA; ++ gpio->GPCUP = 0x0000FFFF; ++ gpio->GPDCON = 0xAAAAAAAA; ++ gpio->GPDUP = 0x0000FFFF; ++ gpio->GPECON = 0xAAAAAAAA; ++ gpio->GPEUP = 0x0000FFFF; ++ gpio->GPFCON = 0x000055AA; ++ gpio->GPFUP = 0x000000FF; ++ gpio->GPGCON = 0xFD95FFBA; ++ gpio->GPGUP = 0x0000FFFF; ++#ifdef CONFIG_SERIAL3 ++ gpio->GPHCON = 0x002AAAAA; ++#else ++ gpio->GPHCON = 0x002AFAAA; ++#endif ++ gpio->GPHUP = 0x000007FF; ++ ++ gpio->GPJCON = 0x2AAAAAA; ++ ++#if 0 ++ /* USB Device Part */ ++ /*GPGCON is reset for USB Device */ ++ gpio->GPGCON = (gpio->GPGCON & ~(3 << 24)) | (1 << 24); /* Output Mode */ ++ gpio->GPGUP = gpio->GPGUP | ( 1 << 12); /* Pull up disable */ ++ ++ gpio->GPGDAT |= ( 1 << 12) ; ++ gpio->GPGDAT &= ~( 1 << 12) ; ++ udelay(20000); ++ gpio->GPGDAT |= ( 1 << 12) ; ++#endif ++ ++ /* arch number of SMDK2440-Board */ ++ gd->bd->bi_arch_number = MACH_TYPE_S3C2440; ++ ++ /* adress of boot parameters */ ++ gd->bd->bi_boot_params = 0x30000100; ++ ++ icache_enable(); ++ dcache_enable(); ++ ++ return 0; ++} ++ ++int dram_init (void) ++{ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; ++ ++ return 0; ++} ++ ++/* The sum of all part_size[]s must equal to the NAND size, i.e., 0x4000000. ++ "initrd" is sized such that it can hold two uncompressed 16 bit 640*480 ++ images: 640*480*2*2 = 1228800 < 1245184. */ ++ ++unsigned int dynpart_size[] = { ++ CFG_UBOOT_SIZE, 0x20000, 0x200000, 0xa0000, 0x3d5c000-CFG_UBOOT_SIZE, 0 }; ++char *dynpart_names[] = { ++ "u-boot", "u-boot_env", "kernel", "splash", "rootfs", NULL }; ++ ++ +Index: u-boot/board/smdk2440/u-boot.lds +=================================================================== +--- /dev/null ++++ u-boot/board/smdk2440/u-boot.lds +@@ -0,0 +1,58 @@ ++/* ++ * (C) Copyright 2002 ++ * Gary Jennejohn, DENX Software Engineering, ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ ++OUTPUT_ARCH(arm) ++ENTRY(_start) ++SECTIONS ++{ ++ . = 0x00000000; ++ ++ . = ALIGN(4); ++ .text : ++ { ++ cpu/arm920t/start.o (.text) ++ cpu/arm920t/s3c24x0/nand_read.o (.text) ++ *(.text) ++ } ++ ++ . = ALIGN(4); ++ .rodata : { *(.rodata) } ++ ++ . = ALIGN(4); ++ .data : { *(.data) } ++ ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ . = .; ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss : { *(.bss) } ++ _end = .; ++} +Index: u-boot/board/smdk2440/udc.c +=================================================================== +--- /dev/null ++++ u-boot/board/smdk2440/udc.c +@@ -0,0 +1,23 @@ ++ ++#include ++#include ++#include ++ ++void udc_ctrl(enum usbd_event event, int param) ++{ ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ ++ switch (event) { ++ case UDC_CTRL_PULLUP_ENABLE: ++ if (param) ++ gpio->GPGDAT |= (1 << 12); ++ else ++ gpio->GPGDAT &= ~(1 << 12); ++ break; ++ case UDC_CTRL_500mA_ENABLE: ++ /* IGNORE */ ++ break; ++ default: ++ break; ++ } ++} +Index: u-boot/board/smdk2440/lowlevel_foo.S +=================================================================== +--- /dev/null ++++ u-boot/board/smdk2440/lowlevel_foo.S +@@ -0,0 +1,82 @@ ++ ++_start: ++ b reset ++undefvec: ++ b undefvec ++swivec: ++ b swivec ++pabtvec: ++ b pabtvec ++dabtvec: ++ b dabtvec ++rsvdvec: ++ b rsvdvec ++irqvec: ++ b irqvec ++fiqvec: ++ b fiqvec ++ ++reset: ++ /* ++ * set the cpu to SVC32 mode ++ */ ++ mrs r0,cpsr ++ bic r0,r0,#0x1f ++ orr r0,r0,#0xd3 ++ msr cpsr,r0 ++ ++/* turn off the watchdog */ ++#define pWTCON 0x53000000 ++#define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ ++#define INTSUBMSK 0x4A00001C ++#define CLKDIVN 0x4C000014 /* clock divisor register */ ++ ++ ldr r0, =pWTCON ++ mov r1, #0x0 ++ str r1, [r0] ++ ++ mov r1, #0xffffffff ++ ldr r0, =INTMSK ++ str r1, [r0] ++ ldr r1, =0x3ff ++ ldr r0, =INTSUBMSK ++ str r1, [r0] ++ ++ /* FCLK:HCLK:PCLK = 1:2:4 */ ++ /* default FCLK is 120 MHz ! */ ++ ldr r0, =CLKDIVN ++ mov r1, #3 ++ str r1, [r0] ++ ++ bl cpu_init_crit ++ ldr r0,=TEXT_BASE ++ mov pc, r0 ++ ++cpu_init_crit: ++ /* ++ * flush v4 I/D caches ++ */ ++ mov r0, #0 ++ mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ ++ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ ++ ++ /* ++ * disable MMU stuff and caches ++ */ ++ mrc p15, 0, r0, c1, c0, 0 ++ bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) ++ bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) ++ orr r0, r0, #0x00000002 @ set bit 2 (A) Align ++ orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache ++ mcr p15, 0, r0, c1, c0, 0 ++ ++ /* ++ * before relocating, we have to setup RAM timing ++ * because memory timing is board-dependend, you will ++ * find a lowlevel_init.S in your board directory. ++ */ ++ mov ip, lr ++ bl lowlevel_init ++ mov lr, ip ++ mov pc, lr ++ +Index: u-boot/board/smdk2440/lowlevel_foo.lds +=================================================================== +--- /dev/null ++++ u-boot/board/smdk2440/lowlevel_foo.lds +@@ -0,0 +1,56 @@ ++/* ++ * (C) Copyright 2002 ++ * Gary Jennejohn, DENX Software Engineering, ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++OUTPUT_ARCH(arm) ++ENTRY(_start) ++SECTIONS ++{ ++ . = 0x00000000; ++ ++ . = ALIGN(4); ++ .text : ++ { ++ lowlevel_foo.o (.text) ++ *(.text) ++ } ++ ++ . = ALIGN(4); ++ .rodata : { *(.rodata) } ++ ++ . = ALIGN(4); ++ .data : { *(.data) } ++ ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ . = .; ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss : { *(.bss) } ++ _end = .; ++} diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-smdk2443.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-smdk2443.patch new file mode 100644 index 0000000000..5757cc078b --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-smdk2443.patch @@ -0,0 +1,1411 @@ +Index: u-boot/Makefile +=================================================================== +--- u-boot.orig/Makefile ++++ u-boot/Makefile +@@ -2045,6 +2045,9 @@ + smdk2440_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t smdk2440 NULL s3c24x0 + ++smdk2443_config : unconfig ++ @$(MKCONFIG) $(@:_config=) arm arm920t smdk2443 NULL s3c24x0 ++ + SX1_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm925t sx1 + +Index: u-boot/board/smdk2443/Makefile +=================================================================== +--- /dev/null ++++ u-boot/board/smdk2443/Makefile +@@ -0,0 +1,67 @@ ++# ++# (C) Copyright 2000-2006 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).a ++ ++COBJS := smdk2443.o flash.o udc.o ++SOBJS := lowlevel_init.o ++ ++.PHONY: all ++ ++all: $(LIB) lowlevel_foo.bin ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) ++ ++lowlevel_foo.o: lowlevel_foo.S ++ $(CC) -c -DTEXT_BASE=0x33F80000 -march=armv4 \ ++ -o lowlevel_foo.o lowlevel_foo.S ++ ++lowlevel_foo: lowlevel_foo.o lowlevel_init.o lowlevel_foo.lds ++ $(LD) -T ./lowlevel_foo.lds -Ttext 0x33f80000 -Bstatic \ ++ lowlevel_init.o lowlevel_foo.o -o lowlevel_foo ++ ++lowlevel_foo.bin: lowlevel_foo ++ $(CROSS_COMPILE)objcopy --gap-fill=0xff -O binary \ ++ lowlevel_foo lowlevel_foo.bin ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak .depend ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +Index: u-boot/board/smdk2443/smdk2443.c +=================================================================== +--- /dev/null ++++ u-boot/board/smdk2443/smdk2443.c +@@ -0,0 +1,147 @@ ++/* ++ * (C) Copyright 2006 OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#define FCLK_SPEED 1 ++ ++#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ ++#define M_MDIV 0xC3 ++#define M_PDIV 0x4 ++#define M_SDIV 0x1 ++#elif FCLK_SPEED==1 /* Fout = 399.65MHz */ ++#define M_MDIV 0x6e ++#define M_PDIV 0x3 ++#define M_SDIV 0x1 ++#endif ++ ++#define USB_CLOCK 1 ++ ++#if USB_CLOCK==0 ++#define U_M_MDIV 0xA1 ++#define U_M_PDIV 0x3 ++#define U_M_SDIV 0x1 ++#elif USB_CLOCK==1 ++#define U_M_MDIV 0x3c ++#define U_M_PDIV 0x4 ++#define U_M_SDIV 0x2 ++#endif ++ ++static inline void delay (unsigned long loops) ++{ ++ __asm__ volatile ("1:\n" ++ "subs %0, %1, #1\n" ++ "bne 1b":"=r" (loops):"0" (loops)); ++} ++ ++/* ++ * Miscellaneous platform dependent initialisations ++ */ ++ ++int board_init (void) ++{ ++ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ ++ /* to reduce PLL lock time, adjust the LOCKTIME register */ ++ clk_power->LOCKTIME = 0xFFFFFF; ++ ++ /* configure MPLL */ ++ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); ++ ++ /* some delay between MPLL and UPLL */ ++ delay (4000); ++ ++ /* configure UPLL */ ++ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); ++ ++ /* some delay between MPLL and UPLL */ ++ delay (8000); ++ ++ /* set up the I/O ports */ ++ gpio->GPACON = 0x007FFFFF; ++ gpio->GPBCON = 0x00044555; ++ gpio->GPBUP = 0x000007FF; ++ gpio->GPCCON = 0xAAAAAAAA; ++ gpio->GPCUP = 0x0000FFFF; ++ gpio->GPDCON = 0xAAAAAAAA; ++ gpio->GPDUP = 0x0000FFFF; ++ gpio->GPECON = 0xAAAAAAAA; ++ gpio->GPEUP = 0x0000FFFF; ++ gpio->GPFCON = 0x000055AA; ++ gpio->GPFUP = 0x000000FF; ++ gpio->GPGCON = 0xFD95FFBA; ++ gpio->GPGUP = 0x0000FFFF; ++#ifdef CONFIG_SERIAL3 ++ gpio->GPHCON = 0x002AAAAA; ++#else ++ gpio->GPHCON = 0x002AFAAA; ++#endif ++ gpio->GPHUP = 0x000007FF; ++ ++#if 0 ++ /* USB Device Part */ ++ /*GPGCON is reset for USB Device */ ++ gpio->GPGCON = (gpio->GPGCON & ~(3 << 24)) | (1 << 24); /* Output Mode */ ++ gpio->GPGUP = gpio->GPGUP | ( 1 << 12); /* Pull up disable */ ++ ++ gpio->GPGDAT |= ( 1 << 12) ; ++ gpio->GPGDAT &= ~( 1 << 12) ; ++ udelay(20000); ++ gpio->GPGDAT |= ( 1 << 12) ; ++#endif ++ ++ /* arch number of SMDK2440-Board */ ++ gd->bd->bi_arch_number = MACH_TYPE_S3C2440; ++ ++ /* adress of boot parameters */ ++ gd->bd->bi_boot_params = 0x30000100; ++ ++ icache_enable(); ++ dcache_enable(); ++ ++ return 0; ++} ++ ++int dram_init (void) ++{ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; ++ ++ return 0; ++} ++ ++/* The sum of all part_size[]s must equal to the NAND size, i.e., 0x4000000. ++ "initrd" is sized such that it can hold two uncompressed 16 bit 640*480 ++ images: 640*480*2*2 = 1228800 < 1245184. */ ++ ++unsigned int dynpart_size[] = { ++ CFG_UBOOT_SIZE, 0x20000, 0x200000, 0xa0000, 0x3d5c000-CFG_UBOOT_SIZE, 0 }; ++ ++char *dynpart_names[] = { ++ "u-boot", "u-boot_env", "kernel", "splash", "rootfs", NULL }; ++ ++ +Index: u-boot/board/smdk2443/u-boot.lds +=================================================================== +--- /dev/null ++++ u-boot/board/smdk2443/u-boot.lds +@@ -0,0 +1,58 @@ ++/* ++ * (C) Copyright 2002 ++ * Gary Jennejohn, DENX Software Engineering, ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ ++OUTPUT_ARCH(arm) ++ENTRY(_start) ++SECTIONS ++{ ++ . = 0x00000000; ++ ++ . = ALIGN(4); ++ .text : ++ { ++ cpu/arm920t/start.o (.text) ++ cpu/arm920t/s3c24x0/nand_read.o (.text) ++ *(.text) ++ } ++ ++ . = ALIGN(4); ++ .rodata : { *(.rodata) } ++ ++ . = ALIGN(4); ++ .data : { *(.data) } ++ ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ . = .; ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss : { *(.bss) } ++ _end = .; ++} +Index: u-boot/include/configs/smdk2443.h +=================================================================== +--- /dev/null ++++ u-boot/include/configs/smdk2443.h +@@ -0,0 +1,289 @@ ++/* ++ * (C) Copyright 2007 OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * Configuation settings for the SAMSUNG SMDK2443 board. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#if 0 ++/* If we want to start u-boot from usb bootloader in NOR flash */ ++#define CONFIG_SKIP_RELOCATE_UBOOT 1 ++#define CONFIG_SKIP_LOWLEVEL_INIT 1 ++#else ++/* If we want to start u-boot directly from within NAND flash */ ++#define CONFIG_LL_INIT_NAND_ONLY ++#define CONFIG_S3C2410_NAND_BOOT 1 ++#define CONFIG_S3C2410_NAND_SKIP_BAD 1 ++#endif ++ ++#define CFG_UBOOT_SIZE 0x40000 /* size of u-boot, for NAND loading */ ++ ++/* ++ * High Level Configuration Options ++ * (easy to change) ++ */ ++#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ ++#define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2440 SoC */ ++#define CONFIG_SMDK2443 1 /* on a SAMSUNG SMDK2440 Board */ ++ ++/* input clock of PLL */ ++#define CONFIG_SYS_CLK_FREQ 16934400/* SMDK2440 has 16.9344MHz input clock */ ++ ++ ++#define USE_920T_MMU 1 ++#define CONFIG_USE_IRQ 1 ++ ++/* ++ * Size of malloc() pool ++ */ ++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 2048*1024) ++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ ++ ++/* ++ * Hardware drivers ++ */ ++#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ ++#define CS8900_BASE 0x19000300 ++#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ ++ ++/* ++ * select serial console configuration ++ */ ++#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2440 */ ++#define CONFIG_HWFLOW 1 ++ ++/************************************************************ ++ * RTC ++ ************************************************************/ ++#define CONFIG_RTC_S3C24X0 1 ++ ++/* allow to overwrite serial and ethaddr */ ++#define CONFIG_ENV_OVERWRITE ++ ++#define CONFIG_BAUDRATE 115200 ++ ++/*********************************************************** ++ * Command definition ++ ***********************************************************/ ++#define CONFIG_COMMANDS \ ++ (CONFIG_CMD_DFL | \ ++ /*CFG_CMD_BSP | */ \ ++ CFG_CMD_CACHE | \ ++ CFG_CMD_DATE | \ ++ /*CFG_CMD_DHCP | */ \ ++ CFG_CMD_DIAG | \ ++ CFG_CMD_ELF | \ ++ CFG_CMD_EXT2 | \ ++ CFG_CMD_FAT | \ ++ /*CFG_CMD_HWFLOW | */ \ ++ /* CFG_CMD_IDE | */ \ ++ /* CFG_CMD_IRQ | */ \ ++ CFG_CMD_JFFS2 | \ ++ CFG_CMD_MMC | \ ++ CFG_CMD_NAND | \ ++ CFG_CMD_PING | \ ++ CFG_CMD_PORTIO | \ ++ CFG_CMD_REGINFO | \ ++ CFG_CMD_SAVES | \ ++ CFG_CMD_LICENSE | \ ++ CFG_CMD_USB) ++ ++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ ++#include ++ ++#define CONFIG_BOOTDELAY 3 ++#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 console=ttySAC2,115200 loglevel=8" ++#define CONFIG_ETHADDR 00:0c:20:02:0a:5b ++#define CONFIG_NETMASK 255.255.255.0 ++#define CONFIG_IPADDR 192.168.1.100 ++#define CONFIG_SERVERIP 192.168.1.21 ++#define CONFIG_BOOTCOMMAND "nand read.e 0x32000000 0x100000 0x200000; bootm" ++ ++#define CONFIG_DOS_PARTITION 1 ++ ++#if (CONFIG_COMMANDS & CFG_CMD_KGDB) ++#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ ++/* what's this ? it's not used anywhere */ ++#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ ++#endif ++ ++/* ++ * Miscellaneous configurable options ++ */ ++#define CFG_LONGHELP /* undef to save memory */ ++#define CFG_PROMPT "SMDK2443 # " /* Monitor Command Prompt */ ++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ ++#define CFG_MAXARGS 32 /* max number of command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ ++ ++#define CFG_MEMTEST_START 0x30000000 /* memtest works on */ ++#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ ++ ++#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ ++ ++#define CFG_LOAD_ADDR 0x32000000 /* default load address */ ++ ++/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ ++/* it to wrap 100 times (total 1562500) to get 1 sec. */ ++#define CFG_HZ 1562500 ++ ++/* valid baudrates */ ++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } ++ ++/*----------------------------------------------------------------------- ++ * Stack sizes ++ * ++ * The stack sizes are set up in start.S using the settings below ++ */ ++#define CONFIG_STACKSIZE (512*1024) /* regular stack */ ++#ifdef CONFIG_USE_IRQ ++#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */ ++#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ ++#endif ++ ++/* IDE/ATA config */ ++ ++#if 0 ++#define CFG_IDE_MAXBUS 1 ++#define CFG_IDE_MAXDEVICE 2 ++#define CFG_IDE_PREINIT 0 ++ ++#define CFG_ATA_BASE_ADDR ++#endif ++ ++#define CONFIG_USB_OHCI 1 ++ ++#define CONFIG_USB_DEVICE 1 ++#define CONFIG_USB_TTY 1 ++#define CFG_CONSOLE_IS_IN_ENV 1 ++#define CONFIG_USBD_VENDORID 0x1457 /* Linux/NetChip */ ++#define CONFIG_USBD_PRODUCTID_GSERIAL 0x5120 /* gserial */ ++#define CONFIG_USBD_PRODUCTID_CDCACM 0x5119 /* CDC ACM */ ++#define CONFIG_USBD_MANUFACTURER "FiWin" ++#define CONFIG_USBD_PRODUCT_NAME "S3C2443 Bootloader " U_BOOT_VERSION ++#define CONFIG_EXTRA_ENV_SETTINGS "usbtty=cdc_acm\0" ++#define CONFIG_USBD_DFU 1 ++#define CONFIG_USBD_DFU_XFER_SIZE 4096 ++#define CONFIG_USBD_DFU_INTERFACE 2 ++ ++/*----------------------------------------------------------------------- ++ * Physical Memory Map ++ */ ++#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ ++#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ ++#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ ++ ++#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ ++ ++#define CFG_FLASH_BASE PHYS_FLASH_1 ++ ++/*----------------------------------------------------------------------- ++ * FLASH and environment organization ++ */ ++ ++#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ ++#if 0 ++#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ ++#endif ++ ++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ ++#ifdef CONFIG_AMD_LV800 ++#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ ++#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ ++#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */ ++#endif ++#ifdef CONFIG_AMD_LV400 ++#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ ++#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ ++#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */ ++#endif ++ ++/* timeout values are in ticks */ ++#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ ++#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ ++ ++#define CFG_ENV_IS_IN_NAND 1 ++#define CFG_ENV_SIZE 0x20000 /* 128k Total Size of Environment Sector */ ++#define CFG_ENV_OFFSET_OOB 1 ++#define CFG_PREBOOT_OVERRIDE 1 ++ ++#define NAND_MAX_CHIPS 1 ++#define CFG_NAND_BASE 0x4e000000 ++#define CFG_MAX_NAND_DEVICE 1 ++ ++#define CONFIG_MMC 1 ++#define CFG_MMC_BASE 0xff000000 ++ ++#define CONFIG_EXT2 1 ++ ++/* FAT driver in u-boot is broken currently */ ++#define CONFIG_FAT 1 ++#define CONFIG_SUPPORT_VFAT ++ ++#if 1 ++/* JFFS2 driver */ ++#define CONFIG_JFFS2_CMDLINE 1 ++#define CONFIG_JFFS2_NAND 1 ++#define CONFIG_JFFS2_NAND_DEV 0 ++//#define CONFIG_JFFS2_NAND_OFF 0x634000 ++//#define CONFIG_JFFS2_NAND_SIZE 0x39cc000 ++#endif ++ ++/* ATAG configuration */ ++#define CONFIG_INITRD_TAG 1 ++#define CONFIG_SETUP_MEMORY_TAGS 1 ++#define CONFIG_CMDLINE_TAG 1 ++#if 0 ++#define CONFIG_SERIAL_TAG 1 ++#define CONFIG_REVISION_TAG 1 ++#endif ++ ++ ++#if 0 ++#define CONFIG_VIDEO ++#define CONFIG_VIDEO_S3C2410 ++#define CONFIG_CFB_CONSOLE ++#define CONFIG_VIDEO_LOGO ++#define CONFIG_VGA_AS_SINGLE_DEVICE ++ ++#define VIDEO_KBD_INIT_FCT 0 ++#define VIDEO_TSTC_FCT serial_tstc ++#define VIDEO_GETC_FCT serial_getc ++ ++#define LCD_VIDEO_ADDR 0x33d00000 ++#endif ++ ++#define CONFIG_S3C2410_NAND_BBT 1 ++//#define CONFIG_S3C2410_NAND_HWECC 1 ++ ++#define CFG_NAND_YAFFS_WRITE ++#define CFG_NAND_YAFFS1_NEW_OOB_LAYOUT ++ ++#define MTDIDS_DEFAULT "nand0=smdk2443-nand" ++#define MTPARTS_DEFAULT "smdk2443-nand:0x00100000(u-boot),0x00200000(kernel),0x00200000(update),0x00100000(splash),0x01400000(jffs2),-(temp)" ++#define CFG_NAND_DYNPART_MTD_KERNEL_NAME "smdk2443-nand" ++#define CONFIG_NAND_DYNPART ++ ++#endif /* __CONFIG_H */ +Index: u-boot/board/smdk2443/lowlevel_foo.S +=================================================================== +--- /dev/null ++++ u-boot/board/smdk2443/lowlevel_foo.S +@@ -0,0 +1,82 @@ ++ ++_start: ++ b reset ++undefvec: ++ b undefvec ++swivec: ++ b swivec ++pabtvec: ++ b pabtvec ++dabtvec: ++ b dabtvec ++rsvdvec: ++ b rsvdvec ++irqvec: ++ b irqvec ++fiqvec: ++ b fiqvec ++ ++reset: ++ /* ++ * set the cpu to SVC32 mode ++ */ ++ mrs r0,cpsr ++ bic r0,r0,#0x1f ++ orr r0,r0,#0xd3 ++ msr cpsr,r0 ++ ++/* turn off the watchdog */ ++#define pWTCON 0x53000000 ++#define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ ++#define INTSUBMSK 0x4A00001C ++#define CLKDIVN 0x4C000014 /* clock divisor register */ ++ ++ ldr r0, =pWTCON ++ mov r1, #0x0 ++ str r1, [r0] ++ ++ mov r1, #0xffffffff ++ ldr r0, =INTMSK ++ str r1, [r0] ++ ldr r1, =0x3ff ++ ldr r0, =INTSUBMSK ++ str r1, [r0] ++ ++ /* FCLK:HCLK:PCLK = 1:2:4 */ ++ /* default FCLK is 120 MHz ! */ ++ ldr r0, =CLKDIVN ++ mov r1, #3 ++ str r1, [r0] ++ ++ bl cpu_init_crit ++ ldr r0,=TEXT_BASE ++ mov pc, r0 ++ ++cpu_init_crit: ++ /* ++ * flush v4 I/D caches ++ */ ++ mov r0, #0 ++ mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ ++ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ ++ ++ /* ++ * disable MMU stuff and caches ++ */ ++ mrc p15, 0, r0, c1, c0, 0 ++ bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) ++ bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) ++ orr r0, r0, #0x00000002 @ set bit 2 (A) Align ++ orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache ++ mcr p15, 0, r0, c1, c0, 0 ++ ++ /* ++ * before relocating, we have to setup RAM timing ++ * because memory timing is board-dependend, you will ++ * find a lowlevel_init.S in your board directory. ++ */ ++ mov ip, lr ++ bl lowlevel_init ++ mov lr, ip ++ mov pc, lr ++ +Index: u-boot/board/smdk2443/lowlevel_init.S +=================================================================== +--- /dev/null ++++ u-boot/board/smdk2443/lowlevel_init.S +@@ -0,0 +1,163 @@ ++/* ++ * SMDK2443 Memory Setup ++ * ++ * Copyright (C) 2007 by OpenMoko, Inc. ++ * Author: Harald Welte ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++ ++#include ++#include ++ ++ ++/* some parameters for the board */ ++ ++/* ++ * ++ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S ++ * ++ * Copyright (C) 2002 Samsung Electronics SW.LEE ++ * ++ */ ++ ++#define BWSCON 0x48000000 ++ ++/* BWSCON */ ++#define DW8 (0x0) ++#define DW16 (0x1) ++#define DW32 (0x2) ++#define WAIT (0x1<<2) ++#define UBLB (0x1<<3) ++ ++#define B1_BWSCON (DW32) ++#define B2_BWSCON (DW16) ++#define B3_BWSCON (DW16 + WAIT + UBLB) ++#define B4_BWSCON (DW16) ++#define B5_BWSCON (DW16) ++#define B6_BWSCON (DW32) ++#define B7_BWSCON (DW32) ++ ++/* BANK0CON */ ++#define B0_Tacs 0x0 /* 0clk */ ++#define B0_Tcos 0x0 /* 0clk */ ++#define B0_Tacc 0x7 /* 14clk */ ++#define B0_Tcoh 0x0 /* 0clk */ ++#define B0_Tah 0x0 /* 0clk */ ++#define B0_Tacp 0x0 ++#define B0_PMC 0x0 /* normal */ ++ ++/* BANK1CON */ ++#define B1_Tacs 0x0 /* 0clk */ ++#define B1_Tcos 0x0 /* 0clk */ ++#define B1_Tacc 0x7 /* 14clk */ ++#define B1_Tcoh 0x0 /* 0clk */ ++#define B1_Tah 0x0 /* 0clk */ ++#define B1_Tacp 0x0 ++#define B1_PMC 0x0 ++ ++#define B2_Tacs 0x0 ++#define B2_Tcos 0x0 ++#define B2_Tacc 0x7 ++#define B2_Tcoh 0x0 ++#define B2_Tah 0x0 ++#define B2_Tacp 0x0 ++#define B2_PMC 0x0 ++ ++#define B3_Tacs 0x0 /* 0clk */ ++#define B3_Tcos 0x3 /* 4clk */ ++#define B3_Tacc 0x7 /* 14clk */ ++#define B3_Tcoh 0x1 /* 1clk */ ++#define B3_Tah 0x0 /* 0clk */ ++#define B3_Tacp 0x3 /* 6clk */ ++#define B3_PMC 0x0 /* normal */ ++ ++#define B4_Tacs 0x0 /* 0clk */ ++#define B4_Tcos 0x0 /* 0clk */ ++#define B4_Tacc 0x7 /* 14clk */ ++#define B4_Tcoh 0x0 /* 0clk */ ++#define B4_Tah 0x0 /* 0clk */ ++#define B4_Tacp 0x0 ++#define B4_PMC 0x0 /* normal */ ++ ++#define B5_Tacs 0x0 /* 0clk */ ++#define B5_Tcos 0x0 /* 0clk */ ++#define B5_Tacc 0x7 /* 14clk */ ++#define B5_Tcoh 0x0 /* 0clk */ ++#define B5_Tah 0x0 /* 0clk */ ++#define B5_Tacp 0x0 ++#define B5_PMC 0x0 /* normal */ ++ ++#define B6_MT 0x3 /* SDRAM */ ++#define B6_Trcd 0x1 ++#define B6_SCAN 0x1 /* 9bit */ ++ ++#define B7_MT 0x3 /* SDRAM */ ++#define B7_Trcd 0x1 /* 3clk */ ++#define B7_SCAN 0x1 /* 9bit */ ++ ++/* REFRESH parameter */ ++#define REFEN 0x1 /* Refresh enable */ ++#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ ++#define Trp 0x0 /* 2clk */ ++#define Trc 0x3 /* 7clk */ ++#define Tchr 0x2 /* 3clk */ ++#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ ++/**************************************/ ++ ++_TEXT_BASE: ++ .word TEXT_BASE ++ ++.globl lowlevel_init ++lowlevel_init: ++ /* memory control configuration */ ++ /* make r0 relative the current location so that it */ ++ /* reads SMRDATA out of FLASH rather than memory ! */ ++ ldr r0, =SMRDATA ++ ldr r1, _TEXT_BASE ++ sub r0, r0, r1 ++ ldr r1, =BWSCON /* Bus Width Status Controller */ ++ add r2, r0, #13*4 ++0: ++ ldr r3, [r0], #4 ++ str r3, [r1], #4 ++ cmp r2, r0 ++ bne 0b ++ ++ /* everything is fine now */ ++ mov pc, lr ++ ++ .ltorg ++/* the literal pools origin */ ++ ++SMRDATA: ++ .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) ++ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ++ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ++ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ++ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ++ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ++ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ++ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ++ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ++ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) ++ .word 0x32 ++ .word 0x30 ++ .word 0x30 +Index: u-boot/board/smdk2443/config.mk +=================================================================== +--- /dev/null ++++ u-boot/board/smdk2443/config.mk +@@ -0,0 +1,29 @@ ++# ++# (C) Copyright 2002 ++# Gary Jennejohn, DENX Software Engineering, ++# David Mueller, ELSOFT AG, ++# ++# SAMSUNG SMDK2443 board with S3C2443 (ARM920T) cpu ++# ++# see http://www.samsung.com/ for more information on SAMSUNG ++# ++ ++CONFIG_USB_DFU_VENDOR=0x1457 ++CONFIG_USB_DFU_PRODUCT=0x511c ++CONFIG_USB_DFU_REVISION=0x0100 ++ ++# ++# SMDK2443 has 1 bank of 64 MB DRAM ++# ++# 3000'0000 to 3400'0000 ++# ++# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 ++# optionally with a ramdisk at 3080'0000 ++# ++# we load ourself to 33F8'0000 ++# ++# download area is 3300'0000 ++# ++ ++ ++TEXT_BASE = 0x33F80000 +Index: u-boot/board/smdk2443/lowlevel_foo.lds +=================================================================== +--- /dev/null ++++ u-boot/board/smdk2443/lowlevel_foo.lds +@@ -0,0 +1,56 @@ ++/* ++ * (C) Copyright 2002 ++ * Gary Jennejohn, DENX Software Engineering, ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++OUTPUT_ARCH(arm) ++ENTRY(_start) ++SECTIONS ++{ ++ . = 0x00000000; ++ ++ . = ALIGN(4); ++ .text : ++ { ++ lowlevel_foo.o (.text) ++ *(.text) ++ } ++ ++ . = ALIGN(4); ++ .rodata : { *(.rodata) } ++ ++ . = ALIGN(4); ++ .data : { *(.data) } ++ ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ . = .; ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss : { *(.bss) } ++ _end = .; ++} +Index: u-boot/board/smdk2443/flash.c +=================================================================== +--- /dev/null ++++ u-boot/board/smdk2443/flash.c +@@ -0,0 +1,433 @@ ++/* ++ * (C) Copyright 2002 ++ * Sysgo Real-Time Solutions, GmbH ++ * Alex Zuepke ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++ ++ulong myflush (void); ++ ++ ++#define FLASH_BANK_SIZE PHYS_FLASH_SIZE ++#define MAIN_SECT_SIZE 0x10000 /* 64 KB */ ++ ++flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; ++ ++ ++#define CMD_READ_ARRAY 0x000000F0 ++#define CMD_UNLOCK1 0x000000AA ++#define CMD_UNLOCK2 0x00000055 ++#define CMD_ERASE_SETUP 0x00000080 ++#define CMD_ERASE_CONFIRM 0x00000030 ++#define CMD_PROGRAM 0x000000A0 ++#define CMD_UNLOCK_BYPASS 0x00000020 ++ ++#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1))) ++#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1))) ++ ++#define BIT_ERASE_DONE 0x00000080 ++#define BIT_RDY_MASK 0x00000080 ++#define BIT_PROGRAM_ERROR 0x00000020 ++#define BIT_TIMEOUT 0x80000000 /* our flag */ ++ ++#define READY 1 ++#define ERR 2 ++#define TMO 4 ++ ++/*----------------------------------------------------------------------- ++ */ ++ ++ulong flash_init (void) ++{ ++ int i, j; ++ ulong size = 0; ++ ++ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { ++ ulong flashbase = 0; ++ ++ flash_info[i].flash_id = ++#if defined(CONFIG_AMD_LV400) ++ (AMD_MANUFACT & FLASH_VENDMASK) | ++ (AMD_ID_LV400B & FLASH_TYPEMASK); ++#elif defined(CONFIG_AMD_LV800) ++ (AMD_MANUFACT & FLASH_VENDMASK) | ++ (AMD_ID_LV800B & FLASH_TYPEMASK); ++#else ++#error "Unknown flash configured" ++#endif ++ flash_info[i].size = FLASH_BANK_SIZE; ++ flash_info[i].sector_count = CFG_MAX_FLASH_SECT; ++ memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); ++ if (i == 0) ++ flashbase = PHYS_FLASH_1; ++ else ++ panic ("configured too many flash banks!\n"); ++ for (j = 0; j < flash_info[i].sector_count; j++) { ++ if (j <= 3) { ++ /* 1st one is 16 KB */ ++ if (j == 0) { ++ flash_info[i].start[j] = ++ flashbase + 0; ++ } ++ ++ /* 2nd and 3rd are both 8 KB */ ++ if ((j == 1) || (j == 2)) { ++ flash_info[i].start[j] = ++ flashbase + 0x4000 + (j - ++ 1) * ++ 0x2000; ++ } ++ ++ /* 4th 32 KB */ ++ if (j == 3) { ++ flash_info[i].start[j] = ++ flashbase + 0x8000; ++ } ++ } else { ++ flash_info[i].start[j] = ++ flashbase + (j - 3) * MAIN_SECT_SIZE; ++ } ++ } ++ size += flash_info[i].size; ++ } ++ ++ flash_protect (FLAG_PROTECT_SET, ++ CFG_FLASH_BASE, ++ CFG_FLASH_BASE + monitor_flash_len - 1, ++ &flash_info[0]); ++ ++ flash_protect (FLAG_PROTECT_SET, ++ CFG_ENV_ADDR, ++ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); ++ ++ return size; ++} ++ ++/*----------------------------------------------------------------------- ++ */ ++void flash_print_info (flash_info_t * info) ++{ ++ int i; ++ ++ switch (info->flash_id & FLASH_VENDMASK) { ++ case (AMD_MANUFACT & FLASH_VENDMASK): ++ printf ("AMD: "); ++ break; ++ default: ++ printf ("Unknown Vendor "); ++ break; ++ } ++ ++ switch (info->flash_id & FLASH_TYPEMASK) { ++ case (AMD_ID_LV400B & FLASH_TYPEMASK): ++ printf ("1x Amd29LV400BB (4Mbit)\n"); ++ break; ++ case (AMD_ID_LV800B & FLASH_TYPEMASK): ++ printf ("1x Amd29LV800BB (8Mbit)\n"); ++ break; ++ default: ++ printf ("Unknown Chip Type\n"); ++ goto Done; ++ break; ++ } ++ ++ printf (" Size: %ld MB in %d Sectors\n", ++ info->size >> 20, info->sector_count); ++ ++ printf (" Sector Start Addresses:"); ++ for (i = 0; i < info->sector_count; i++) { ++ if ((i % 5) == 0) { ++ printf ("\n "); ++ } ++ printf (" %08lX%s", info->start[i], ++ info->protect[i] ? " (RO)" : " "); ++ } ++ printf ("\n"); ++ ++ Done:; ++} ++ ++/*----------------------------------------------------------------------- ++ */ ++ ++int flash_erase (flash_info_t * info, int s_first, int s_last) ++{ ++ ushort result; ++ int iflag, cflag, prot, sect; ++ int rc = ERR_OK; ++ int chip; ++ ++ /* first look for protection bits */ ++ ++ if (info->flash_id == FLASH_UNKNOWN) ++ return ERR_UNKNOWN_FLASH_TYPE; ++ ++ if ((s_first < 0) || (s_first > s_last)) { ++ return ERR_INVAL; ++ } ++ ++ if ((info->flash_id & FLASH_VENDMASK) != ++ (AMD_MANUFACT & FLASH_VENDMASK)) { ++ return ERR_UNKNOWN_FLASH_VENDOR; ++ } ++ ++ prot = 0; ++ for (sect = s_first; sect <= s_last; ++sect) { ++ if (info->protect[sect]) { ++ prot++; ++ } ++ } ++ if (prot) ++ return ERR_PROTECTED; ++ ++ /* ++ * Disable interrupts which might cause a timeout ++ * here. Remember that our exception vectors are ++ * at address 0 in the flash, and we don't want a ++ * (ticker) exception to happen while the flash ++ * chip is in programming mode. ++ */ ++ cflag = icache_status (); ++ icache_disable (); ++ iflag = disable_interrupts (); ++ ++ /* Start erase on unprotected sectors */ ++ for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { ++ printf ("Erasing sector %2d ... ", sect); ++ ++ /* arm simple, non interrupt dependent timer */ ++ reset_timer_masked (); ++ ++ if (info->protect[sect] == 0) { /* not protected */ ++ vu_short *addr = (vu_short *) (info->start[sect]); ++ ++ MEM_FLASH_ADDR1 = CMD_UNLOCK1; ++ MEM_FLASH_ADDR2 = CMD_UNLOCK2; ++ MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; ++ ++ MEM_FLASH_ADDR1 = CMD_UNLOCK1; ++ MEM_FLASH_ADDR2 = CMD_UNLOCK2; ++ *addr = CMD_ERASE_CONFIRM; ++ ++ /* wait until flash is ready */ ++ chip = 0; ++ ++ do { ++ result = *addr; ++ ++ /* check timeout */ ++ if (get_timer_masked () > ++ CFG_FLASH_ERASE_TOUT) { ++ MEM_FLASH_ADDR1 = CMD_READ_ARRAY; ++ chip = TMO; ++ break; ++ } ++ ++ if (!chip ++ && (result & 0xFFFF) & BIT_ERASE_DONE) ++ chip = READY; ++ ++ if (!chip ++ && (result & 0xFFFF) & BIT_PROGRAM_ERROR) ++ chip = ERR; ++ ++ } while (!chip); ++ ++ MEM_FLASH_ADDR1 = CMD_READ_ARRAY; ++ ++ if (chip == ERR) { ++ rc = ERR_PROG_ERROR; ++ goto outahere; ++ } ++ if (chip == TMO) { ++ rc = ERR_TIMOUT; ++ goto outahere; ++ } ++ ++ printf ("ok.\n"); ++ } else { /* it was protected */ ++ ++ printf ("protected!\n"); ++ } ++ } ++ ++ if (ctrlc ()) ++ printf ("User Interrupt!\n"); ++ ++ outahere: ++ /* allow flash to settle - wait 10 ms */ ++ udelay_masked (10000); ++ ++ if (iflag) ++ enable_interrupts (); ++ ++ if (cflag) ++ icache_enable (); ++ ++ return rc; ++} ++ ++/*----------------------------------------------------------------------- ++ * Copy memory to flash ++ */ ++ ++volatile static int write_hword (flash_info_t * info, ulong dest, ushort data) ++{ ++ vu_short *addr = (vu_short *) dest; ++ ushort result; ++ int rc = ERR_OK; ++ int cflag, iflag; ++ int chip; ++ ++ /* ++ * Check if Flash is (sufficiently) erased ++ */ ++ result = *addr; ++ if ((result & data) != data) ++ return ERR_NOT_ERASED; ++ ++ ++ /* ++ * Disable interrupts which might cause a timeout ++ * here. Remember that our exception vectors are ++ * at address 0 in the flash, and we don't want a ++ * (ticker) exception to happen while the flash ++ * chip is in programming mode. ++ */ ++ cflag = icache_status (); ++ icache_disable (); ++ iflag = disable_interrupts (); ++ ++ MEM_FLASH_ADDR1 = CMD_UNLOCK1; ++ MEM_FLASH_ADDR2 = CMD_UNLOCK2; ++ MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS; ++ *addr = CMD_PROGRAM; ++ *addr = data; ++ ++ /* arm simple, non interrupt dependent timer */ ++ reset_timer_masked (); ++ ++ /* wait until flash is ready */ ++ chip = 0; ++ do { ++ result = *addr; ++ ++ /* check timeout */ ++ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { ++ chip = ERR | TMO; ++ break; ++ } ++ if (!chip && ((result & 0x80) == (data & 0x80))) ++ chip = READY; ++ ++ if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { ++ result = *addr; ++ ++ if ((result & 0x80) == (data & 0x80)) ++ chip = READY; ++ else ++ chip = ERR; ++ } ++ ++ } while (!chip); ++ ++ *addr = CMD_READ_ARRAY; ++ ++ if (chip == ERR || *addr != data) ++ rc = ERR_PROG_ERROR; ++ ++ if (iflag) ++ enable_interrupts (); ++ ++ if (cflag) ++ icache_enable (); ++ ++ return rc; ++} ++ ++/*----------------------------------------------------------------------- ++ * Copy memory to flash. ++ */ ++ ++int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) ++{ ++ ulong cp, wp; ++ int l; ++ int i, rc; ++ ushort data; ++ ++ wp = (addr & ~1); /* get lower word aligned address */ ++ ++ /* ++ * handle unaligned start bytes ++ */ ++ if ((l = addr - wp) != 0) { ++ data = 0; ++ for (i = 0, cp = wp; i < l; ++i, ++cp) { ++ data = (data >> 8) | (*(uchar *) cp << 8); ++ } ++ for (; i < 2 && cnt > 0; ++i) { ++ data = (data >> 8) | (*src++ << 8); ++ --cnt; ++ ++cp; ++ } ++ for (; cnt == 0 && i < 2; ++i, ++cp) { ++ data = (data >> 8) | (*(uchar *) cp << 8); ++ } ++ ++ if ((rc = write_hword (info, wp, data)) != 0) { ++ return (rc); ++ } ++ wp += 2; ++ } ++ ++ /* ++ * handle word aligned part ++ */ ++ while (cnt >= 2) { ++ data = *((vu_short *) src); ++ if ((rc = write_hword (info, wp, data)) != 0) { ++ return (rc); ++ } ++ src += 2; ++ wp += 2; ++ cnt -= 2; ++ } ++ ++ if (cnt == 0) { ++ return ERR_OK; ++ } ++ ++ /* ++ * handle unaligned tail bytes ++ */ ++ data = 0; ++ for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { ++ data = (data >> 8) | (*src++ << 8); ++ --cnt; ++ } ++ for (; i < 2; ++i, ++cp) { ++ data = (data >> 8) | (*(uchar *) cp << 8); ++ } ++ ++ return write_hword (info, wp, data); ++} +Index: u-boot/board/smdk2443/udc.c +=================================================================== +--- /dev/null ++++ u-boot/board/smdk2443/udc.c +@@ -0,0 +1,23 @@ ++ ++#include ++#include ++#include ++ ++void udc_ctrl(enum usbd_event event, int param) ++{ ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ ++ switch (event) { ++ case UDC_CTRL_PULLUP_ENABLE: ++ if (param) ++ gpio->GPGDAT |= (1 << 12); ++ else ++ gpio->GPGDAT &= ~(1 << 12); ++ break; ++ case UDC_CTRL_500mA_ENABLE: ++ /* IGNORE */ ++ break; ++ default: ++ break; ++ } ++} diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-strtoul.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-strtoul.patch new file mode 100644 index 0000000000..a88e94b006 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-strtoul.patch @@ -0,0 +1,43 @@ +Make simple_strtoul work with upper-case hex numbers. + +Signed-off-by: Harald Welte + +Index: u-boot/lib_generic/vsprintf.c +=================================================================== +--- u-boot.orig/lib_generic/vsprintf.c ++++ u-boot/lib_generic/vsprintf.c +@@ -25,21 +25,22 @@ unsigned long simple_strtoul(const char + { + unsigned long result = 0,value; + +- if (*cp == '0') { +- cp++; +- if ((*cp == 'x') && isxdigit(cp[1])) { +- base = 16; +- cp++; +- } +- if (!base) { +- base = 8; +- } +- } + if (!base) { + base = 10; ++ if (*cp == '0') { ++ base = 8; ++ cp++; ++ if ((toupper(*cp) == 'X') && isxdigit(cp[1])) { ++ cp++; ++ base = 16; ++ } ++ } ++ } else if (base == 16) { ++ if (cp[0] == '0' && toupper(cp[1]) == 'X') ++ cp += 2; + } +- while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp) +- ? toupper(*cp) : *cp)-'A'+10) < base) { ++ while (isxdigit(*cp) && ++ (value = isdigit(*cp) ? *cp-'0' : toupper(*cp)-'A'+10) < base) { + result = result*base + value; + cp++; + } diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-usbtty-acm.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-usbtty-acm.patch new file mode 100644 index 0000000000..722a227aa6 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/uboot-usbtty-acm.patch @@ -0,0 +1,1607 @@ +This patch adds cdc_acm interoperability to u-boot usbtty. + +It was taken (almost blindly) from the Linux for Siemens SX1 project on +handhelds.org. Please don't complain to me about coding style issues +or whitespace changes in this one - HW. + +Index: u-boot/drivers/usbtty.c +=================================================================== +--- u-boot.orig/drivers/usbtty.c 2007-02-08 21:11:27.000000000 +0100 ++++ u-boot/drivers/usbtty.c 2007-02-08 21:11:55.000000000 +0100 +@@ -1,6 +1,9 @@ + /* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments ++ * ++ * (C) Copyright 2006 ++ * Bryan O'Donoghue, bodonoghue codehermit.ie + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -22,26 +25,61 @@ + + #ifdef CONFIG_USB_TTY + ++#include + #include + #include + #include "usbtty.h" ++#include "usb_cdc_acm.h" ++#include "usbdescriptors.h" ++#include /* If defined, override Linux identifiers with ++ * vendor specific ones */ + + #if 0 +-#define TTYDBG(fmt,args...) serial_printf("[%s] %s %d: "fmt, __FILE__,__FUNCTION__,__LINE__,##args) ++//+++ debug print into memory buffer,like kernel log ++static char* log_buf = 0x10e00000; // somewhere in RAM ++static char log_str[512]; ++#define TTYDBG(fmt,args...)\ ++ sprintf(log_str,"\n[%s] %s %d: "fmt, __FILE__,__FUNCTION__,__LINE__,##args);\ ++ memcpy(log_buf, log_str, strlen(log_str));\ ++ log_buf+=strlen(log_str);\ ++ strcpy(log_buf,"\n---------------------------------------------------")\ ++//--- + #else + #define TTYDBG(fmt,args...) do{}while(0) + #endif + + #if 0 +-#define TTYERR(fmt,args...) serial_printf("ERROR![%s] %s %d: "fmt, __FILE__,__FUNCTION__,__LINE__,##args) ++#define TTYDBG(fmt,args...)\ ++ serial_printf("[%s] %s %d: "fmt"\n", __FILE__,__FUNCTION__,__LINE__,##args) ++#endif ++ ++#if 0 ++#define TTYERR(fmt,args...)\ ++ serial_printf("ERROR![%s] %s %d: "fmt"\n", __FILE__,__FUNCTION__,\ ++ __LINE__,##args) + #else + #define TTYERR(fmt,args...) do{}while(0) + #endif + + /* ++ * Defines ++ */ ++#define NUM_CONFIGS 1 ++#define MAX_INTERFACES 2 ++#define NUM_ENDPOINTS 3 ++#define ACM_TX_ENDPOINT 3 ++#define ACM_RX_ENDPOINT 2 ++#define GSERIAL_TX_ENDPOINT 2 ++#define GSERIAL_RX_ENDPOINT 1 ++#define NUM_ACM_INTERFACES 2 ++#define NUM_GSERIAL_INTERFACES 1 ++#define CONFIG_USBD_DATA_INTERFACE_STR "Bulk Data Interface" ++#define CONFIG_USBD_CTRL_INTERFACE_STR "Control Interface" ++ ++/* + * Buffers to hold input and output data + */ +-#define USBTTY_BUFFER_SIZE 256 ++#define USBTTY_BUFFER_SIZE 2048 + static circbuf_t usbtty_input; + static circbuf_t usbtty_output; + +@@ -50,157 +88,336 @@ + * Instance variables + */ + static device_t usbttydev; +-static struct usb_device_instance device_instance[1]; +-static struct usb_bus_instance bus_instance[1]; ++static struct usb_device_instance device_instance[1]; ++static struct usb_bus_instance bus_instance[1]; + static struct usb_configuration_instance config_instance[NUM_CONFIGS]; +-static struct usb_interface_instance interface_instance[NUM_INTERFACES]; +-static struct usb_alternate_instance alternate_instance[NUM_INTERFACES]; +-static struct usb_endpoint_instance endpoint_instance[NUM_ENDPOINTS+1]; /* one extra for control endpoint */ +- +-/* +- * Static allocation of urbs +- */ +-#define RECV_ENDPOINT 1 +-#define TX_ENDPOINT 2 ++static struct usb_interface_instance interface_instance[MAX_INTERFACES]; ++static struct usb_alternate_instance alternate_instance[MAX_INTERFACES]; ++/* one extra for control endpoint */ ++static struct usb_endpoint_instance endpoint_instance[NUM_ENDPOINTS+1]; + + /* + * Global flag + */ + int usbtty_configured_flag = 0; + +- + /* + * Serial number + */ + static char serial_number[16]; + ++ + /* +- * Descriptors ++ * Descriptors, Strings, Local variables. + */ ++ ++/* defined and used by usbdcore_ep0.c */ ++extern struct usb_string_descriptor **usb_strings; ++ ++/* Indicies, References */ ++static unsigned short rx_endpoint = 0; ++static unsigned short tx_endpoint = 0; ++static unsigned short interface_count = 0; ++static struct usb_string_descriptor *usbtty_string_table[STR_COUNT]; ++ ++/* USB Descriptor Strings */ + static u8 wstrLang[4] = {4,USB_DT_STRING,0x9,0x4}; + static u8 wstrManufacturer[2 + 2*(sizeof(CONFIG_USBD_MANUFACTURER)-1)]; + static u8 wstrProduct[2 + 2*(sizeof(CONFIG_USBD_PRODUCT_NAME)-1)]; + static u8 wstrSerial[2 + 2*(sizeof(serial_number) - 1)]; + static u8 wstrConfiguration[2 + 2*(sizeof(CONFIG_USBD_CONFIGURATION_STR)-1)]; +-static u8 wstrInterface[2 + 2*(sizeof(CONFIG_USBD_INTERFACE_STR)-1)]; +- +-static struct usb_string_descriptor *usbtty_string_table[] = { +- (struct usb_string_descriptor*)wstrLang, +- (struct usb_string_descriptor*)wstrManufacturer, +- (struct usb_string_descriptor*)wstrProduct, +- (struct usb_string_descriptor*)wstrSerial, +- (struct usb_string_descriptor*)wstrConfiguration, +- (struct usb_string_descriptor*)wstrInterface +-}; +-extern struct usb_string_descriptor **usb_strings; /* defined and used by omap1510_ep0.c */ ++static u8 wstrDataInterface[2 + 2*(sizeof(CONFIG_USBD_DATA_INTERFACE_STR)-1)]; ++static u8 wstrCtrlInterface[2 + 2*(sizeof(CONFIG_USBD_DATA_INTERFACE_STR)-1)]; + ++/* Standard USB Data Structures */ ++static struct usb_interface_descriptor interface_descriptors[MAX_INTERFACES]; ++static struct usb_endpoint_descriptor *ep_descriptor_ptrs[NUM_ENDPOINTS]; ++static struct usb_configuration_descriptor *configuration_descriptor = 0; + static struct usb_device_descriptor device_descriptor = { +- bLength: sizeof(struct usb_device_descriptor), +- bDescriptorType: USB_DT_DEVICE, +- bcdUSB: USB_BCD_VERSION, +- bDeviceClass: USBTTY_DEVICE_CLASS, +- bDeviceSubClass: USBTTY_DEVICE_SUBCLASS, +- bDeviceProtocol: USBTTY_DEVICE_PROTOCOL, +- bMaxPacketSize0: EP0_MAX_PACKET_SIZE, +- idVendor: CONFIG_USBD_VENDORID, +- idProduct: CONFIG_USBD_PRODUCTID, +- bcdDevice: USBTTY_BCD_DEVICE, +- iManufacturer: STR_MANUFACTURER, +- iProduct: STR_PRODUCT, +- iSerialNumber: STR_SERIAL, +- bNumConfigurations: NUM_CONFIGS +- }; +-static struct usb_configuration_descriptor config_descriptors[NUM_CONFIGS] = { +- { +- bLength: sizeof(struct usb_configuration_descriptor), +- bDescriptorType: USB_DT_CONFIG, +- wTotalLength: (sizeof(struct usb_configuration_descriptor)*NUM_CONFIGS) + +- (sizeof(struct usb_interface_descriptor)*NUM_INTERFACES) + +- (sizeof(struct usb_endpoint_descriptor)*NUM_ENDPOINTS), +- bNumInterfaces: NUM_INTERFACES, +- bConfigurationValue: 1, +- iConfiguration: STR_CONFIG, +- bmAttributes: BMATTRIBUTE_SELF_POWERED | BMATTRIBUTE_RESERVED, +- bMaxPower: USBTTY_MAXPOWER +- }, +-}; +-static struct usb_interface_descriptor interface_descriptors[NUM_INTERFACES] = { +- { +- bLength: sizeof(struct usb_interface_descriptor), +- bDescriptorType: USB_DT_INTERFACE, +- bInterfaceNumber: 0, +- bAlternateSetting: 0, +- bNumEndpoints: NUM_ENDPOINTS, +- bInterfaceClass: USBTTY_INTERFACE_CLASS, +- bInterfaceSubClass: USBTTY_INTERFACE_SUBCLASS, +- bInterfaceProtocol: USBTTY_INTERFACE_PROTOCOL, +- iInterface: STR_INTERFACE +- }, ++ .bLength = sizeof(struct usb_device_descriptor), ++ .bDescriptorType = USB_DT_DEVICE, ++ .bcdUSB = cpu_to_le16(USB_BCD_VERSION), ++ .bDeviceSubClass = 0x00, ++ .bDeviceProtocol = 0x00, ++ .bMaxPacketSize0 = EP0_MAX_PACKET_SIZE, ++ .idVendor = cpu_to_le16(CONFIG_USBD_VENDORID), ++ .bcdDevice = cpu_to_le16(USBTTY_BCD_DEVICE), ++ .iManufacturer = STR_MANUFACTURER, ++ .iProduct = STR_PRODUCT, ++ .iSerialNumber = STR_SERIAL, ++ .bNumConfigurations = NUM_CONFIGS + }; +-static struct usb_endpoint_descriptor ep_descriptors[NUM_ENDPOINTS] = { +- { +- bLength: sizeof(struct usb_endpoint_descriptor), +- bDescriptorType: USB_DT_ENDPOINT, +- bEndpointAddress: CONFIG_USBD_SERIAL_OUT_ENDPOINT | USB_DIR_OUT, +- bmAttributes: USB_ENDPOINT_XFER_BULK, +- wMaxPacketSize: CONFIG_USBD_SERIAL_OUT_PKTSIZE, +- bInterval: 0 +- }, +- { +- bLength: sizeof(struct usb_endpoint_descriptor), +- bDescriptorType: USB_DT_ENDPOINT, +- bEndpointAddress: CONFIG_USBD_SERIAL_IN_ENDPOINT | USB_DIR_IN, +- bmAttributes: USB_ENDPOINT_XFER_BULK, +- wMaxPacketSize: CONFIG_USBD_SERIAL_IN_PKTSIZE, +- bInterval: 0 +- }, +- { +- bLength: sizeof(struct usb_endpoint_descriptor), +- bDescriptorType: USB_DT_ENDPOINT, +- bEndpointAddress: CONFIG_USBD_SERIAL_INT_ENDPOINT | USB_DIR_IN, +- bmAttributes: USB_ENDPOINT_XFER_INT, +- wMaxPacketSize: CONFIG_USBD_SERIAL_INT_PKTSIZE, +- bInterval: 0 +- }, +-}; +-static struct usb_endpoint_descriptor *ep_descriptor_ptrs[NUM_ENDPOINTS] = { +- &(ep_descriptors[0]), +- &(ep_descriptors[1]), +- &(ep_descriptors[2]), ++ ++ ++/* ++ * Static CDC ACM specific descriptors ++ */ ++ ++struct acm_config_desc { ++ struct usb_configuration_descriptor configuration_desc; ++ ++ /* Master Interface */ ++ struct usb_interface_descriptor interface_desc; ++ ++ struct usb_class_header_function_descriptor usb_class_header; ++ struct usb_class_call_management_descriptor usb_class_call_mgt; ++ struct usb_class_abstract_control_descriptor usb_class_acm; ++ struct usb_class_union_function_descriptor usb_class_union; ++ struct usb_endpoint_descriptor notification_endpoint; ++ ++ /* Slave Interface */ ++ struct usb_interface_descriptor data_class_interface; ++ struct usb_endpoint_descriptor ++ data_endpoints[NUM_ENDPOINTS-1] __attribute__((packed)); ++} __attribute__((packed)); ++ ++static struct acm_config_desc acm_configuration_descriptors[NUM_CONFIGS] = { ++ { ++ .configuration_desc ={ ++ .bLength = ++ sizeof(struct usb_configuration_descriptor), ++ .bDescriptorType = USB_DT_CONFIG, ++ .wTotalLength = ++ cpu_to_le16(sizeof(struct acm_config_desc)), ++ .bNumInterfaces = NUM_ACM_INTERFACES, ++ .bConfigurationValue = 1, ++ .iConfiguration = STR_CONFIG, ++ .bmAttributes = ++ BMATTRIBUTE_SELF_POWERED|BMATTRIBUTE_RESERVED, ++ .bMaxPower = USBTTY_MAXPOWER ++ }, ++ /* Interface 1 */ ++ .interface_desc = { ++ .bLength = sizeof(struct usb_interface_descriptor), ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = 0, ++ .bAlternateSetting = 0, ++ .bNumEndpoints = 0x01, ++ .bInterfaceClass = ++ COMMUNICATIONS_INTERFACE_CLASS_CONTROL, ++ .bInterfaceSubClass = COMMUNICATIONS_ACM_SUBCLASS, ++ .bInterfaceProtocol = COMMUNICATIONS_V25TER_PROTOCOL, ++ .iInterface = STR_CTRL_INTERFACE, ++ }, ++ .usb_class_header = { ++ .bFunctionLength = ++ sizeof(struct usb_class_header_function_descriptor), ++ .bDescriptorType = CS_INTERFACE, ++ .bDescriptorSubtype = USB_ST_HEADER, ++ .bcdCDC = cpu_to_le16(110), ++ }, ++ .usb_class_call_mgt = { ++ .bFunctionLength = ++ sizeof(struct usb_class_call_management_descriptor), ++ .bDescriptorType = CS_INTERFACE, ++ .bDescriptorSubtype = USB_ST_CMF, ++ .bmCapabilities = 0x00, ++ .bDataInterface = 0x01, ++ }, ++ .usb_class_acm = { ++ .bFunctionLength = ++ sizeof(struct usb_class_abstract_control_descriptor), ++ .bDescriptorType = CS_INTERFACE, ++ .bDescriptorSubtype = USB_ST_ACMF, ++ .bmCapabilities = 0x00, ++ }, ++ .usb_class_union = { ++ .bFunctionLength = ++ sizeof(struct usb_class_union_function_descriptor), ++ .bDescriptorType = CS_INTERFACE, ++ .bDescriptorSubtype = USB_ST_UF, ++ .bMasterInterface = 0x00, ++ .bSlaveInterface0 = 0x01, ++ }, ++ .notification_endpoint = { ++ .bLength = ++ sizeof(struct usb_endpoint_descriptor), ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = 0x01 | USB_DIR_IN, ++ .bmAttributes = USB_ENDPOINT_XFER_INT, ++ .wMaxPacketSize ++ = cpu_to_le16(CONFIG_USBD_SERIAL_INT_PKTSIZE), ++ .bInterval = 0xFF, ++ }, ++ ++ /* Interface 2 */ ++ .data_class_interface = { ++ .bLength = ++ sizeof(struct usb_interface_descriptor), ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = 0x01, ++ .bAlternateSetting = 0x00, ++ .bNumEndpoints = 0x02, ++ .bInterfaceClass = ++ COMMUNICATIONS_INTERFACE_CLASS_DATA, ++ .bInterfaceSubClass = DATA_INTERFACE_SUBCLASS_NONE, ++ .bInterfaceProtocol = DATA_INTERFACE_PROTOCOL_NONE, ++ .iInterface = STR_DATA_INTERFACE, ++ }, ++ .data_endpoints = { ++ { ++ .bLength = ++ sizeof(struct usb_endpoint_descriptor), ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = 0x02 | USB_DIR_OUT, ++ .bmAttributes = ++ USB_ENDPOINT_XFER_BULK, ++ .wMaxPacketSize = ++ cpu_to_le16(CONFIG_USBD_SERIAL_BULK_PKTSIZE), ++ .bInterval = 0xFF, ++ }, ++ { ++ .bLength = ++ sizeof(struct usb_endpoint_descriptor), ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = 0x03 | USB_DIR_IN, ++ .bmAttributes = ++ USB_ENDPOINT_XFER_BULK, ++ .wMaxPacketSize = ++ cpu_to_le16(CONFIG_USBD_SERIAL_BULK_PKTSIZE), ++ .bInterval = 0xFF, ++ }, ++ }, ++ }, ++}; ++ ++static struct rs232_emu rs232_desc={ ++ .dter = 115200, ++ .stop_bits = 0x00, ++ .parity = 0x00, ++ .data_bits = 0x08 + }; + +-/* utility function for converting char* to wide string used by USB */ +-static void str2wide (char *str, u16 * wide) +-{ +- int i; + +- for (i = 0; i < strlen (str) && str[i]; i++) +- wide[i] = (u16) str[i]; +-} ++/* ++ * Static Generic Serial specific data ++ */ ++ ++ ++struct gserial_config_desc { ++ ++ struct usb_configuration_descriptor configuration_desc; ++ struct usb_interface_descriptor ++ interface_desc[NUM_GSERIAL_INTERFACES] __attribute__((packed)); ++ struct usb_endpoint_descriptor ++ data_endpoints[NUM_ENDPOINTS] __attribute__((packed)); ++ ++} __attribute__((packed)); ++ ++static struct gserial_config_desc ++gserial_configuration_descriptors[NUM_CONFIGS] ={ ++ { ++ .configuration_desc ={ ++ .bLength = sizeof(struct usb_configuration_descriptor), ++ .bDescriptorType = USB_DT_CONFIG, ++ .wTotalLength = ++ cpu_to_le16(sizeof(struct gserial_config_desc)), ++ .bNumInterfaces = NUM_GSERIAL_INTERFACES, ++ .bConfigurationValue = 1, ++ .iConfiguration = STR_CONFIG, ++ .bmAttributes = ++ BMATTRIBUTE_SELF_POWERED|BMATTRIBUTE_RESERVED, ++ .bMaxPower = USBTTY_MAXPOWER ++ }, ++ .interface_desc = { ++ { ++ .bLength = ++ sizeof(struct usb_interface_descriptor), ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = 0, ++ .bAlternateSetting = 0, ++ .bNumEndpoints = NUM_ENDPOINTS, ++ .bInterfaceClass = ++ COMMUNICATIONS_INTERFACE_CLASS_VENDOR, ++ .bInterfaceSubClass = ++ COMMUNICATIONS_NO_SUBCLASS, ++ .bInterfaceProtocol = ++ COMMUNICATIONS_NO_PROTOCOL, ++ .iInterface = STR_DATA_INTERFACE ++ }, ++ }, ++ .data_endpoints = { ++ { ++ .bLength = ++ sizeof(struct usb_endpoint_descriptor), ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = 0x01 | USB_DIR_OUT, ++ .bmAttributes = USB_ENDPOINT_XFER_BULK, ++ .wMaxPacketSize = ++ cpu_to_le16(CONFIG_USBD_SERIAL_OUT_PKTSIZE), ++ .bInterval= 0xFF, ++ }, ++ { ++ .bLength = ++ sizeof(struct usb_endpoint_descriptor), ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = 0x02 | USB_DIR_IN, ++ .bmAttributes = USB_ENDPOINT_XFER_BULK, ++ .wMaxPacketSize = ++ cpu_to_le16(CONFIG_USBD_SERIAL_IN_PKTSIZE), ++ .bInterval = 0xFF, ++ }, ++ { ++ .bLength = ++ sizeof(struct usb_endpoint_descriptor), ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = 0x03 | USB_DIR_IN, ++ .bmAttributes = USB_ENDPOINT_XFER_INT, ++ .wMaxPacketSize = ++ cpu_to_le16(CONFIG_USBD_SERIAL_INT_PKTSIZE), ++ .bInterval = 0xFF, ++ }, ++ }, ++ }, ++}; + + /* +- * Prototypes ++ * Static Function Prototypes + */ ++ + static void usbtty_init_strings (void); + static void usbtty_init_instances (void); + static void usbtty_init_endpoints (void); +- ++static void usbtty_init_terminal_type(short type); + static void usbtty_event_handler (struct usb_device_instance *device, +- usb_device_event_t event, int data); ++ usb_device_event_t event, int data); ++static int usbtty_cdc_setup(struct usb_device_request *request, ++ struct urb *urb); + static int usbtty_configured (void); +- + static int write_buffer (circbuf_t * buf); + static int fill_buffer (circbuf_t * buf); + + void usbtty_poll (void); +-static void pretend_interrupts (void); + ++/* utility function for converting char* to wide string used by USB */ ++static void str2wide (char *str, u16 * wide) ++{ ++ int i; ++ for (i = 0; i < strlen (str) && str[i]; i++){ ++ #if defined(__LITTLE_ENDIAN) ++ wide[i] = (u16) str[i]; ++ #elif defined(__BIG_ENDIAN) ++ wide[i] = ((u16)(str[i])<<8); ++ #else ++ #error "__LITTLE_ENDIAN or __BIG_ENDIAN undefined" ++ #endif ++ } ++} + + /* + * Test whether a character is in the RX buffer + */ ++ + int usbtty_tstc (void) + { ++ struct usb_endpoint_instance *endpoint = ++ &endpoint_instance[rx_endpoint]; ++ ++ /* If no input data exists, allow more RX to be accepted */ ++ if(usbtty_input.size <= 0){ ++ udc_unset_nak(endpoint->endpoint_address&0x03); ++ } ++ + usbtty_poll (); + return (usbtty_input.size > 0); + } +@@ -210,15 +427,21 @@ + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ ++ + int usbtty_getc (void) + { + char c; ++ struct usb_endpoint_instance *endpoint = ++ &endpoint_instance[rx_endpoint]; + + while (usbtty_input.size <= 0) { ++ udc_unset_nak(endpoint->endpoint_address&0x03); + usbtty_poll (); + } + + buf_pop (&usbtty_input, &c, 1); ++ udc_set_nak(endpoint->endpoint_address&0x03); ++ + return c; + } + +@@ -238,7 +461,6 @@ + } + } + +- + /* usbtty_puts() helper function for finding the next '\n' in a string */ + static int next_nl_pos (const char *s) + { +@@ -252,8 +474,9 @@ + } + + /* +- * Output a string to the usb client port. ++ * Output a string to the usb client port - implementing flow control + */ ++ + static void __usbtty_puts (const char *str, int len) + { + int maxlen = usbtty_output.totalsize; +@@ -261,22 +484,19 @@ + + /* break str into chunks < buffer size, if needed */ + while (len > 0) { +- space = maxlen - usbtty_output.size; ++ usbtty_poll (); + ++ space = maxlen - usbtty_output.size; + /* Empty buffer here, if needed, to ensure space... */ +- if (space <= 0) { ++ if (space) { + write_buffer (&usbtty_output); +- space = maxlen - usbtty_output.size; +- if (space <= 0) { +- space = len; /* allow old data to be overwritten. */ +- } +- } +- +- n = MIN (space, MIN (len, maxlen)); +- buf_push (&usbtty_output, str, n); ++ ++ n = MIN (space, MIN (len, maxlen)); ++ buf_push (&usbtty_output, str, n); + +- str += n; +- len -= n; ++ str += n; ++ len -= n; ++ } + } + } + +@@ -313,8 +533,10 @@ + { + int rc; + char * sn; ++ char * tt; + int snlen; + ++ /* Get serial number */ + if (!(sn = getenv("serial#"))) { + sn = "000000000000"; + } +@@ -327,6 +549,14 @@ + memcpy (serial_number, sn, snlen); + serial_number[snlen] = '\0'; + ++ /* Decide on which type of UDC device to be. ++ */ ++ ++ if(!(tt = getenv("usbtty"))) { ++ tt = "generic"; ++ } ++ usbtty_init_terminal_type(strcmp(tt,"cdc_acm")); ++ + /* prepare buffers... */ + buf_init (&usbtty_input, USBTTY_BUFFER_SIZE); + buf_init (&usbtty_output, USBTTY_BUFFER_SIZE); +@@ -337,7 +567,7 @@ + usbtty_init_strings (); + usbtty_init_instances (); + +- udc_startup_events (device_instance); /* Enable our device, initialize udc pointers */ ++ udc_startup_events (device_instance);/* Enable dev, init udc pointers */ + udc_connect (); /* Enable pullup for host detection */ + + usbtty_init_endpoints (); +@@ -362,34 +592,52 @@ + { + struct usb_string_descriptor *string; + ++ usbtty_string_table[STR_LANG] = ++ (struct usb_string_descriptor*)wstrLang; ++ + string = (struct usb_string_descriptor *) wstrManufacturer; +- string->bLength = sizeof (wstrManufacturer); ++ string->bLength = sizeof(wstrManufacturer); + string->bDescriptorType = USB_DT_STRING; + str2wide (CONFIG_USBD_MANUFACTURER, string->wData); ++ usbtty_string_table[STR_MANUFACTURER]=string; ++ + + string = (struct usb_string_descriptor *) wstrProduct; +- string->bLength = sizeof (wstrProduct); ++ string->bLength = sizeof(wstrProduct); + string->bDescriptorType = USB_DT_STRING; + str2wide (CONFIG_USBD_PRODUCT_NAME, string->wData); ++ usbtty_string_table[STR_PRODUCT]=string; ++ + + string = (struct usb_string_descriptor *) wstrSerial; +- string->bLength = 2 + 2*strlen(serial_number); ++ string->bLength = sizeof(serial_number); + string->bDescriptorType = USB_DT_STRING; + str2wide (serial_number, string->wData); ++ usbtty_string_table[STR_SERIAL]=string; ++ + + string = (struct usb_string_descriptor *) wstrConfiguration; +- string->bLength = sizeof (wstrConfiguration); ++ string->bLength = sizeof(wstrConfiguration); + string->bDescriptorType = USB_DT_STRING; + str2wide (CONFIG_USBD_CONFIGURATION_STR, string->wData); ++ usbtty_string_table[STR_CONFIG]=string; ++ ++ ++ string = (struct usb_string_descriptor *) wstrDataInterface; ++ string->bLength = sizeof(wstrDataInterface); ++ string->bDescriptorType = USB_DT_STRING; ++ str2wide (CONFIG_USBD_DATA_INTERFACE_STR, string->wData); ++ usbtty_string_table[STR_DATA_INTERFACE]=string; + +- string = (struct usb_string_descriptor *) wstrInterface; +- string->bLength = sizeof (wstrInterface); ++ string = (struct usb_string_descriptor *) wstrCtrlInterface; ++ string->bLength = sizeof(wstrCtrlInterface); + string->bDescriptorType = USB_DT_STRING; +- str2wide (CONFIG_USBD_INTERFACE_STR, string->wData); ++ str2wide (CONFIG_USBD_CTRL_INTERFACE_STR, string->wData); ++ usbtty_string_table[STR_CTRL_INTERFACE]=string; + + /* Now, initialize the string table for ep0 handling */ + usb_strings = usbtty_string_table; +-} ++} + + static void usbtty_init_instances (void) + { +@@ -400,6 +648,7 @@ + device_instance->device_state = STATE_INIT; + device_instance->device_descriptor = &device_descriptor; + device_instance->event = usbtty_event_handler; ++ device_instance->cdc_recv_setup = usbtty_cdc_setup; + device_instance->bus = bus_instance; + device_instance->configurations = NUM_CONFIGS; + device_instance->configuration_instance_array = config_instance; +@@ -415,8 +664,8 @@ + /* configuration instance */ + memset (config_instance, 0, + sizeof (struct usb_configuration_instance)); +- config_instance->interfaces = NUM_INTERFACES; +- config_instance->configuration_descriptor = config_descriptors; ++ config_instance->interfaces = interface_count; ++ config_instance->configuration_descriptor = configuration_descriptor; + config_instance->interface_instance_array = interface_instance; + + /* interface instance */ +@@ -447,17 +696,22 @@ + sizeof (struct usb_endpoint_instance)); + + endpoint_instance[i].endpoint_address = +- ep_descriptors[i - 1].bEndpointAddress; ++ ep_descriptor_ptrs[i - 1]->bEndpointAddress; + +- endpoint_instance[i].rcv_packetSize = +- ep_descriptors[i - 1].wMaxPacketSize; + endpoint_instance[i].rcv_attributes = +- ep_descriptors[i - 1].bmAttributes; ++ ep_descriptor_ptrs[i - 1]->bmAttributes; ++ ++ endpoint_instance[i].rcv_packetSize = ++ le16_to_cpu(ep_descriptor_ptrs[i - 1]->wMaxPacketSize); ++ ++ endpoint_instance[i].tx_attributes = ++ ep_descriptor_ptrs[i - 1]->bmAttributes; + + endpoint_instance[i].tx_packetSize = +- ep_descriptors[i - 1].wMaxPacketSize; ++ le16_to_cpu(ep_descriptor_ptrs[i - 1]->wMaxPacketSize); ++ + endpoint_instance[i].tx_attributes = +- ep_descriptors[i - 1].bmAttributes; ++ ep_descriptor_ptrs[i - 1]->bmAttributes; + + urb_link_init (&endpoint_instance[i].rcv); + urb_link_init (&endpoint_instance[i].rdy); +@@ -480,13 +734,79 @@ + int i; + + bus_instance->max_endpoints = NUM_ENDPOINTS + 1; +- for (i = 0; i <= NUM_ENDPOINTS; i++) { ++ for (i = 1; i <= NUM_ENDPOINTS; i++) { + udc_setup_ep (device_instance, i, &endpoint_instance[i]); + } + } + ++/* usbtty_init_terminal_type ++ * ++ * Do some late binding for our device type. ++ */ ++static void usbtty_init_terminal_type(short type) ++{ ++ switch(type){ ++ /* CDC ACM */ ++ case 0: ++ /* Assign endpoint descriptors */ ++ ep_descriptor_ptrs[0] = ++ &acm_configuration_descriptors[0].notification_endpoint; ++ ep_descriptor_ptrs[1] = ++ &acm_configuration_descriptors[0].data_endpoints[0]; ++ ep_descriptor_ptrs[2] = ++ &acm_configuration_descriptors[0].data_endpoints[1]; ++ ++ /* Enumerate Device Descriptor */ ++ device_descriptor.bDeviceClass = ++ COMMUNICATIONS_DEVICE_CLASS; ++ device_descriptor.idProduct = ++ cpu_to_le16(CONFIG_USBD_PRODUCTID_CDCACM); ++ ++ /* Assign endpoint indices */ ++ tx_endpoint = ACM_TX_ENDPOINT; ++ rx_endpoint = ACM_RX_ENDPOINT; ++ ++ /* Configuration Descriptor */ ++ configuration_descriptor = ++ (struct usb_configuration_descriptor*) ++ &acm_configuration_descriptors; ++ ++ /* Interface count */ ++ interface_count = NUM_ACM_INTERFACES; ++ break; ++ ++ /* BULK IN/OUT & Default */ ++ case 1: ++ default: ++ /* Assign endpoint descriptors */ ++ ep_descriptor_ptrs[0] = ++ &gserial_configuration_descriptors[0].data_endpoints[0]; ++ ep_descriptor_ptrs[1] = ++ &gserial_configuration_descriptors[0].data_endpoints[1]; ++ ep_descriptor_ptrs[2] = ++ &gserial_configuration_descriptors[0].data_endpoints[2]; ++ ++ /* Enumerate Device Descriptor */ ++ device_descriptor.bDeviceClass = 0xFF; ++ device_descriptor.idProduct = ++ cpu_to_le16(CONFIG_USBD_PRODUCTID_GSERIAL); ++ ++ /* Assign endpoint indices */ ++ tx_endpoint = GSERIAL_TX_ENDPOINT; ++ rx_endpoint = GSERIAL_RX_ENDPOINT; ++ ++ /* Configuration Descriptor */ ++ configuration_descriptor = ++ (struct usb_configuration_descriptor*) ++ &gserial_configuration_descriptors; ++ ++ /* Interface count */ ++ interface_count = NUM_GSERIAL_INTERFACES; ++ break; ++ } ++} + +-/*********************************************************************************/ ++/******************************************************************************/ + + static struct urb *next_urb (struct usb_device_instance *device, + struct usb_endpoint_instance *endpoint) +@@ -522,82 +842,179 @@ + + static int write_buffer (circbuf_t * buf) + { +- if (!usbtty_configured ()) { +- return 0; +- } ++ if (!usbtty_configured ()) { ++ return 0; ++ } ++ ++ if (buf->size) { ++ ++ struct usb_endpoint_instance *endpoint = ++ &endpoint_instance[tx_endpoint]; ++ struct urb *current_urb = NULL; ++ char *dest; ++ ++ int space_avail; ++ int popnum, popped; ++ int total = 0; ++ ++ /* Break buffer into urb sized pieces, and link each to the endpoint */ ++ while (buf->size > 0) { ++ TTYDBG ("buf->size= %d",buf->size); ++ current_urb = next_urb (device_instance, endpoint); ++ if (!current_urb) { ++ TTYDBG ("current_urb is NULL, buf->size %d\n", ++ buf->size); ++ return total; ++ } ++ ++ dest = current_urb->buffer + ++ current_urb->actual_length; ++ ++ space_avail = ++ current_urb->buffer_length - ++ current_urb->actual_length; ++ TTYDBG ("space_avail= %d",space_avail); ++ popnum = MIN (space_avail, buf->size); ++ if (popnum == 0) ++ break; ++ ++ popped = buf_pop (buf, dest, popnum); ++ TTYDBG ("popped= %d, %s",popped, dest); ++ if (popped == 0) ++ break; ++ current_urb->actual_length += popped; ++ total += popped; ++ ++ /* If endpoint->last == 0, then transfers have not started on this endpoint */ ++ if (endpoint->last == 0) { ++ udc_endpoint_write (endpoint); ++ } ++ ++ } /* end while */ ++ TTYDBG (" total= %d",total); ++ return total; ++ } /* end if tx_urb */ + +- if (buf->size) { ++ return 0; ++} ++// static int write_buffer (circbuf_t * buf) ++// { ++// if (!usbtty_configured ()) { ++// return 0; ++// } ++// ++// struct usb_endpoint_instance *endpoint = ++// &endpoint_instance[tx_endpoint]; ++// struct urb *current_urb = NULL; ++// ++// current_urb = next_urb (device_instance, endpoint); ++// /* TX data still exists - send it now ++// */ ++// if(endpoint->sent < current_urb->actual_length){ ++// if(udc_endpoint_write (endpoint)){ ++// /* Write pre-empted by RX */ ++// return -1; ++// } ++// } ++// ++// if (buf->size) { ++// char *dest; ++// ++// int space_avail; ++// int popnum, popped; ++// int total = 0; ++// ++// /* Break buffer into urb sized pieces, ++// * and link each to the endpoint ++// */ ++// while (buf->size > 0) { ++// ++// if (!current_urb) { ++// TTYERR ("current_urb is NULL, buf->size %d\n", ++// buf->size); ++// return total; ++// } ++// ++// dest = (char*)current_urb->buffer + ++// current_urb->actual_length; ++// ++// space_avail = ++// current_urb->buffer_length - ++// current_urb->actual_length; ++// popnum = MIN (space_avail, buf->size); ++// if (popnum == 0) ++// break; ++// ++// popped = buf_pop (buf, dest, popnum); ++// if (popped == 0) ++// break; ++// current_urb->actual_length += popped; ++// total += popped; ++// ++// /* If endpoint->last == 0, then transfers have ++// * not started on this endpoint ++// */ ++// if (endpoint->last == 0) { ++// if(udc_endpoint_write (endpoint)){ ++// /* Write pre-empted by RX */ ++// return -1; ++// } ++// } ++// ++// }/* end while */ ++// return total; ++// } ++// ++// return 0; ++// } + +- struct usb_endpoint_instance *endpoint = +- &endpoint_instance[TX_ENDPOINT]; +- struct urb *current_urb = NULL; +- char *dest; +- +- int space_avail; +- int popnum, popped; +- int total = 0; +- +- /* Break buffer into urb sized pieces, and link each to the endpoint */ +- while (buf->size > 0) { +- current_urb = next_urb (device_instance, endpoint); +- if (!current_urb) { +- TTYERR ("current_urb is NULL, buf->size %d\n", +- buf->size); +- return total; +- } +- +- dest = current_urb->buffer + +- current_urb->actual_length; +- +- space_avail = +- current_urb->buffer_length - +- current_urb->actual_length; +- popnum = MIN (space_avail, buf->size); +- if (popnum == 0) +- break; +- +- popped = buf_pop (buf, dest, popnum); +- if (popped == 0) +- break; +- current_urb->actual_length += popped; +- total += popped; +- +- /* If endpoint->last == 0, then transfers have not started on this endpoint */ +- if (endpoint->last == 0) { +- udc_endpoint_write (endpoint); +- } +- +- } /* end while */ +- return total; +- } /* end if tx_urb */ ++static int fill_buffer (circbuf_t * buf) ++{ ++ struct usb_endpoint_instance *endpoint = ++ &endpoint_instance[rx_endpoint]; + +- return 0; +-} ++ if (endpoint->rcv_urb && endpoint->rcv_urb->actual_length) { ++ unsigned int nb = endpoint->rcv_urb->actual_length; ++ char *src = (char *) endpoint->rcv_urb->buffer; + ++ buf_push (buf, src, nb); ++ endpoint->rcv_urb->actual_length = 0; ++ ++ TTYDBG ("nb= %d",nb); ++ return nb; ++ } ++ ++ return 0; ++} ++/* + static int fill_buffer (circbuf_t * buf) + { + struct usb_endpoint_instance *endpoint = +- &endpoint_instance[RECV_ENDPOINT]; ++ &endpoint_instance[rx_endpoint]; + + if (endpoint->rcv_urb && endpoint->rcv_urb->actual_length) { +- unsigned int nb = endpoint->rcv_urb->actual_length; ++ unsigned int nb = 0; + char *src = (char *) endpoint->rcv_urb->buffer; ++ unsigned int rx_avail = buf->totalsize - buf->size; + +- buf_push (buf, src, nb); +- endpoint->rcv_urb->actual_length = 0; ++ if(rx_avail >= endpoint->rcv_urb->actual_length){ + ++ nb = endpoint->rcv_urb->actual_length; ++ buf_push (buf, src, nb); ++ endpoint->rcv_urb->actual_length = 0; ++ ++ } + return nb; + } +- + return 0; + } +- ++*/ + static int usbtty_configured (void) + { + return usbtty_configured_flag; + } + +-/*********************************************************************************/ ++/******************************************************************************/ + + static void usbtty_event_handler (struct usb_device_instance *device, + usb_device_event_t event, int data) +@@ -619,8 +1036,34 @@ + } + } + +-/*********************************************************************************/ ++/******************************************************************************/ + ++int usbtty_cdc_setup(struct usb_device_request *request, struct urb *urb) ++{ ++ switch (request->bRequest){ ++ ++ case ACM_SET_CONTROL_LINE_STATE: /* Implies DTE ready */ ++ break; ++ case ACM_SEND_ENCAPSULATED_COMMAND : /* Required */ ++ break; ++ case ACM_SET_LINE_ENCODING : /* DTE stop/parity bits ++ * per character */ ++ break; ++ case ACM_GET_ENCAPSULATED_RESPONSE : /* request response */ ++ break; ++ case ACM_GET_LINE_ENCODING : /* request DTE rate, ++ * stop/parity bits */ ++ memcpy (urb->buffer , &rs232_desc, sizeof(rs232_desc)); ++ urb->actual_length = sizeof(rs232_desc); ++ ++ break; ++ default: ++ return 1; ++ } ++ return 0; ++} ++ ++/******************************************************************************/ + + /* + * Since interrupt handling has not yet been implemented, we use this function +@@ -630,36 +1073,29 @@ + void usbtty_poll (void) + { + /* New interrupts? */ +- pretend_interrupts (); ++ udc_irq(); + +- /* Write any output data to host buffer (do this before checking interrupts to avoid missing one) */ ++ /* Write any output data to host buffer ++ * (do this before checking interrupts to avoid missing one) ++ */ + if (usbtty_configured ()) { + write_buffer (&usbtty_output); + } + + /* New interrupts? */ +- pretend_interrupts (); +- +- /* Check for new data from host.. (do this after checking interrupts to get latest data) */ ++ udc_irq(); ++ ++ /* Check for new data from host.. ++ * (do this after checking interrupts to get latest data) ++ */ + if (usbtty_configured ()) { + fill_buffer (&usbtty_input); + } + + /* New interrupts? */ +- pretend_interrupts (); +-} ++ udc_irq(); + +-static void pretend_interrupts (void) +-{ +- /* Loop while we have interrupts. +- * If we don't do this, the input chain +- * polling delay is likely to miss +- * host requests. +- */ +- while (inw (UDC_IRQ_SRC) & ~UDC_SOF_Flg) { +- /* Handle any new IRQs */ +- omap1510_udc_irq (); +- omap1510_udc_noniso_irq (); +- } + } ++ ++ + #endif +Index: u-boot/drivers/usbtty.h +=================================================================== +--- u-boot.orig/drivers/usbtty.h 2007-02-08 21:11:27.000000000 +0100 ++++ u-boot/drivers/usbtty.h 2007-02-08 21:11:55.000000000 +0100 +@@ -2,6 +2,9 @@ + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + * ++ * (C) Copyright 2006 ++ * Bryan O'Donoghue, bodonoghue codehermit.ie, CodeHermit ++ * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or +@@ -21,44 +24,49 @@ + #ifndef __USB_TTY_H__ + #define __USB_TTY_H__ + +- + #include "usbdcore.h" ++#if defined(CONFIG_PPC) ++#include "usbdcore_mpc8xx.h" ++#elif defined(CONFIG_OMAP1510) + #include "usbdcore_omap1510.h" ++#endif + ++#include ++#include + +-#define NUM_CONFIGS 1 +-#define NUM_INTERFACES 1 +-#define NUM_ENDPOINTS 3 ++/* If no VendorID/ProductID is defined in config.h, pretend to be Linux ++ * DO NOT Reuse this Vendor/Product setup with protocol incompatible devices */ + +-#define EP0_MAX_PACKET_SIZE 64 ++#ifndef CONFIG_USBD_VENDORID ++#define CONFIG_USBD_VENDORID 0x0525 /* Linux/NetChip */ ++#define CONFIG_USBD_PRODUCTID_GSERIAL 0xa4a6 /* gserial */ ++#define CONFIG_USBD_PRODUCTID_CDCACM 0xa4a7 /* CDC ACM */ ++#define CONFIG_USBD_MANUFACTURER "Das U-Boot" ++#define CONFIG_USBD_PRODUCT_NAME U_BOOT_VERSION ++#endif /* CONFIG_USBD_VENDORID */ + + #define CONFIG_USBD_CONFIGURATION_STR "TTY via USB" +-#define CONFIG_USBD_INTERFACE_STR "Simple Serial Data Interface - Bulk Mode" +- +- +-#define CONFIG_USBD_SERIAL_OUT_ENDPOINT 2 +-#define CONFIG_USBD_SERIAL_OUT_PKTSIZE 64 +-#define CONFIG_USBD_SERIAL_IN_ENDPOINT 1 +-#define CONFIG_USBD_SERIAL_IN_PKTSIZE 64 +-#define CONFIG_USBD_SERIAL_INT_ENDPOINT 5 +-#define CONFIG_USBD_SERIAL_INT_PKTSIZE 16 + ++#define CONFIG_USBD_SERIAL_OUT_ENDPOINT UDC_OUT_ENDPOINT ++#define CONFIG_USBD_SERIAL_OUT_PKTSIZE UDC_OUT_PACKET_SIZE ++#define CONFIG_USBD_SERIAL_IN_ENDPOINT UDC_IN_ENDPOINT ++#define CONFIG_USBD_SERIAL_IN_PKTSIZE UDC_IN_PACKET_SIZE ++#define CONFIG_USBD_SERIAL_INT_ENDPOINT UDC_INT_ENDPOINT ++#define CONFIG_USBD_SERIAL_INT_PKTSIZE UDC_INT_PACKET_SIZE ++#define CONFIG_USBD_SERIAL_BULK_PKTSIZE UDC_BULK_PACKET_SIZE + + #define USBTTY_DEVICE_CLASS COMMUNICATIONS_DEVICE_CLASS +-#define USBTTY_DEVICE_SUBCLASS COMMUNICATIONS_NO_SUBCLASS +-#define USBTTY_DEVICE_PROTOCOL COMMUNICATIONS_NO_PROTOCOL + +-#define USBTTY_INTERFACE_CLASS 0xFF /* Vendor Specific */ +-#define USBTTY_INTERFACE_SUBCLASS 0x02 +-#define USBTTY_INTERFACE_PROTOCOL 0x01 +- +-#define USBTTY_BCD_DEVICE 0x0 +-#define USBTTY_MAXPOWER 0x0 +- +-#define STR_MANUFACTURER 1 +-#define STR_PRODUCT 2 +-#define STR_SERIAL 3 +-#define STR_CONFIG 4 +-#define STR_INTERFACE 5 ++#define USBTTY_BCD_DEVICE 0x00 ++#define USBTTY_MAXPOWER 0x00 ++ ++#define STR_LANG 0x00 ++#define STR_MANUFACTURER 0x01 ++#define STR_PRODUCT 0x02 ++#define STR_SERIAL 0x03 ++#define STR_CONFIG 0x04 ++#define STR_DATA_INTERFACE 0x05 ++#define STR_CTRL_INTERFACE 0x06 ++#define STR_COUNT 0x07 + + #endif +Index: u-boot/drivers/usbdcore_omap1510.c +=================================================================== +--- u-boot.orig/drivers/usbdcore_omap1510.c 2007-02-08 21:11:27.000000000 +0100 ++++ u-boot/drivers/usbdcore_omap1510.c 2007-02-08 21:11:55.000000000 +0100 +@@ -960,7 +960,7 @@ + /* Handle general USB interrupts and dispatch according to type. + * This function implements TRM Figure 14-13. + */ +-void omap1510_udc_irq (void) ++static void omap1510_udc_irq (void) + { + u16 irq_src = inw (UDC_IRQ_SRC); + int valid_irq = 0; +@@ -1000,7 +1000,7 @@ + } + + /* This function implements TRM Figure 14-26. */ +-void omap1510_udc_noniso_irq (void) ++static void omap1510_udc_noniso_irq (void) + { + unsigned short epnum; + unsigned short irq_src = inw (UDC_IRQ_SRC); +@@ -1054,6 +1054,20 @@ + irq_src); + } + ++void udc_irq(void) ++{ ++ /* Loop while we have interrupts. ++ * If we don't do this, the input chain ++ * polling delay is likely to miss ++ * host requests. ++ */ ++ while (inw (UDC_IRQ_SRC) & ~UDC_SOF_Flg) { ++ /* Handle any new IRQs */ ++ omap1510_udc_irq (); ++ omap1510_udc_noniso_irq (); ++ } ++} ++ + /* + ------------------------------------------------------------------------------- + */ +Index: u-boot/include/usb_cdc_acm.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ u-boot/include/usb_cdc_acm.h 2007-02-08 21:11:55.000000000 +0100 +@@ -0,0 +1,43 @@ ++/* ++ * (C) Copyright 2006 ++ * Bryan O'Donoghue, deckard codehermit.ie, CodeHermit ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ */ ++ ++/* ACM Control Requests */ ++#define ACM_SEND_ENCAPSULATED_COMMAND 0x00 ++#define ACM_GET_ENCAPSULATED_RESPONSE 0x01 ++#define ACM_SET_COMM_FEATURE 0x02 ++#define ACM_GET_COMM_FEATRUE 0x03 ++#define ACM_CLEAR_COMM_FEATURE 0x04 ++#define ACM_SET_LINE_ENCODING 0x20 ++#define ACM_GET_LINE_ENCODING 0x21 ++#define ACM_SET_CONTROL_LINE_STATE 0x22 ++#define ACM_SEND_BREAK 0x23 ++ ++/* ACM Notification Codes */ ++#define ACM_NETWORK_CONNECTION 0x00 ++#define ACM_RESPONSE_AVAILABLE 0x01 ++#define ACM_SERIAL_STATE 0x20 ++ ++/* Format of response expected by a ACM_GET_LINE_ENCODING request */ ++struct rs232_emu{ ++ unsigned long dter; ++ unsigned char stop_bits; ++ unsigned char parity; ++ unsigned char data_bits; ++}__attribute__((packed)); +Index: u-boot/include/usbdcore_omap1510.h +=================================================================== +--- u-boot.orig/include/usbdcore_omap1510.h 2007-02-08 21:11:27.000000000 +0100 ++++ u-boot/include/usbdcore_omap1510.h 2007-02-08 21:11:55.000000000 +0100 +@@ -161,13 +161,23 @@ + #define UDC_VBUS_CTRL (1 << 19) + #define UDC_VBUS_MODE (1 << 18) + +- +-void omap1510_udc_irq(void); +-void omap1510_udc_noniso_irq(void); +- ++/* OMAP Endpoint parameters */ ++#define EP0_MAX_PACKET_SIZE 64 ++#define UDC_OUT_ENDPOINT 2 ++#define UDC_OUT_PACKET_SIZE 64 ++#define UDC_IN_ENDPOINT 1 ++#define UDC_IN_PACKET_SIZE 64 ++#define UDC_INT_ENDPOINT 5 ++#define UDC_INT_PACKET_SIZE 16 ++#define UDC_BULK_PACKET_SIZE 16 ++ ++void udc_irq (void); ++/* Flow control */ ++void udc_set_nak(int epid); ++void udc_unset_nak (int epid); + + /* Higher level functions for abstracting away from specific device */ +-void udc_endpoint_write(struct usb_endpoint_instance *endpoint); ++int udc_endpoint_write(struct usb_endpoint_instance *endpoint); + + int udc_init (void); + +Index: u-boot/include/usbdescriptors.h +=================================================================== +--- u-boot.orig/include/usbdescriptors.h 2007-02-08 21:11:27.000000000 +0100 ++++ u-boot/include/usbdescriptors.h 2007-02-08 21:11:55.000000000 +0100 +@@ -92,15 +92,17 @@ + #define COMMUNICATIONS_DEVICE_CLASS 0x02 + + /* c.f. CDC 4.2 Table 15 */ +-#define COMMUNICATIONS_INTERFACE_CLASS 0x02 ++#define COMMUNICATIONS_INTERFACE_CLASS_CONTROL 0x02 ++#define COMMUNICATIONS_INTERFACE_CLASS_DATA 0x0A ++#define COMMUNICATIONS_INTERFACE_CLASS_VENDOR 0x0FF + + /* c.f. CDC 4.3 Table 16 */ +-#define COMMUNICATIONS_NO_SUBCLASS 0x00 ++#define COMMUNICATIONS_NO_SUBCLASS 0x00 + #define COMMUNICATIONS_DLCM_SUBCLASS 0x01 +-#define COMMUNICATIONS_ACM_SUBCLASS 0x02 +-#define COMMUNICATIONS_TCM_SUBCLASS 0x03 ++#define COMMUNICATIONS_ACM_SUBCLASS 0x02 ++#define COMMUNICATIONS_TCM_SUBCLASS 0x03 + #define COMMUNICATIONS_MCCM_SUBCLASS 0x04 +-#define COMMUNICATIONS_CCM_SUBCLASS 0x05 ++#define COMMUNICATIONS_CCM_SUBCLASS 0x05 + #define COMMUNICATIONS_ENCM_SUBCLASS 0x06 + #define COMMUNICATIONS_ANCM_SUBCLASS 0x07 + +@@ -110,15 +112,22 @@ + #define COMMUNICATIONS_MDLM_SUBCLASS 0x0a + #define COMMUNICATIONS_OBEX_SUBCLASS 0x0b + +-/* c.f. CDC 4.6 Table 18 */ ++/* c.f. CDC 4.4 Table 17 */ ++#define COMMUNICATIONS_NO_PROTOCOL 0x00 ++#define COMMUNICATIONS_V25TER_PROTOCOL 0x01 /*Common AT Hayes compatible*/ ++ ++/* c.f. CDC 4.5 Table 18 */ + #define DATA_INTERFACE_CLASS 0x0a + ++/* c.f. CDC 4.6 No Table */ ++#define DATA_INTERFACE_SUBCLASS_NONE 0x00 /* No subclass pertinent */ ++ + /* c.f. CDC 4.7 Table 19 */ +-#define COMMUNICATIONS_NO_PROTOCOL 0x00 ++#define DATA_INTERFACE_PROTOCOL_NONE 0x00 /* No class protcol required */ + + + /* c.f. CDC 5.2.3 Table 24 */ +-#define CS_INTERFACE 0x24 ++#define CS_INTERFACE 0x24 + #define CS_ENDPOINT 0x25 + + /* +@@ -128,7 +137,7 @@ + * c.f. WMCD 5.3 Table 5.3 + */ + +-#define USB_ST_HEADER 0x00 ++#define USB_ST_HEADER 0x00 + #define USB_ST_CMF 0x01 + #define USB_ST_ACMF 0x02 + #define USB_ST_DLMF 0x03 +@@ -137,18 +146,18 @@ + #define USB_ST_UF 0x06 + #define USB_ST_CSF 0x07 + #define USB_ST_TOMF 0x08 +-#define USB_ST_USBTF 0x09 ++#define USB_ST_USBTF 0x09 + #define USB_ST_NCT 0x0a + #define USB_ST_PUF 0x0b + #define USB_ST_EUF 0x0c + #define USB_ST_MCMF 0x0d + #define USB_ST_CCMF 0x0e + #define USB_ST_ENF 0x0f +-#define USB_ST_ATMNF 0x10 ++#define USB_ST_ATMNF 0x10 + + #define USB_ST_WHCM 0x11 + #define USB_ST_MDLM 0x12 +-#define USB_ST_MDLMD 0x13 ++#define USB_ST_MDLMD 0x13 + #define USB_ST_DMM 0x14 + #define USB_ST_OBEX 0x15 + #define USB_ST_CS 0x16 +@@ -312,7 +321,8 @@ + u8 bDescriptorType; + u8 bDescriptorSubtype; /* 0x06 */ + u8 bMasterInterface; +- u8 bSlaveInterface0[0]; ++ //u8 bSlaveInterface0[0]; ++ u8 bSlaveInterface0; + } __attribute__ ((packed)); + + struct usb_class_country_selection_descriptor { +Index: u-boot/include/usbdcore.h +=================================================================== +--- u-boot.orig/include/usbdcore.h 2007-02-08 21:11:27.000000000 +0100 ++++ u-boot/include/usbdcore.h 2007-02-08 21:11:55.000000000 +0100 +@@ -576,6 +576,9 @@ + + void (*event) (struct usb_device_instance *device, usb_device_event_t event, int data); + ++ /* Do cdc device specific control requests */ ++ int (*cdc_recv_setup)(struct usb_device_request *request, struct urb *urb); ++ + /* bus interface */ + struct usb_bus_instance *bus; /* which bus interface driver */ + +Index: u-boot/drivers/usbdcore_ep0.c +=================================================================== +--- u-boot.orig/drivers/usbdcore_ep0.c 2007-02-08 21:12:05.000000000 +0100 ++++ u-boot/drivers/usbdcore_ep0.c 2007-02-08 21:12:08.000000000 +0100 +@@ -223,7 +223,6 @@ + + case USB_DESCRIPTOR_TYPE_CONFIGURATION: + { +- int bNumInterface; + struct usb_configuration_descriptor + *configuration_descriptor; + struct usb_device_descriptor *device_descriptor; +@@ -256,105 +255,6 @@ + usb_configuration_descriptor), + max); + +- +- /* iterate across interfaces for specified configuration */ +- dbg_ep0 (0, "bNumInterfaces: %d", +- configuration_descriptor->bNumInterfaces); +- for (bNumInterface = 0; +- bNumInterface < +- configuration_descriptor->bNumInterfaces; +- bNumInterface++) { +- +- int bAlternateSetting; +- struct usb_interface_instance +- *interface_instance; +- +- dbg_ep0 (3, "[%d] bNumInterfaces: %d", +- bNumInterface, +- configuration_descriptor->bNumInterfaces); +- +- if (! (interface_instance = usbd_device_interface_instance (device, +- port, index, bNumInterface))) +- { +- dbg_ep0 (3, "[%d] interface_instance NULL", +- bNumInterface); +- return -1; +- } +- /* iterate across interface alternates */ +- for (bAlternateSetting = 0; +- bAlternateSetting < interface_instance->alternates; +- bAlternateSetting++) { +- /*int class; */ +- int bNumEndpoint; +- struct usb_interface_descriptor *interface_descriptor; +- +- struct usb_alternate_instance *alternate_instance; +- +- dbg_ep0 (3, "[%d:%d] alternates: %d", +- bNumInterface, +- bAlternateSetting, +- interface_instance->alternates); +- +- if (! (alternate_instance = usbd_device_alternate_instance (device, port, index, bNumInterface, bAlternateSetting))) { +- dbg_ep0 (3, "[%d] alternate_instance NULL", +- bNumInterface); +- return -1; +- } +- /* copy descriptor for this interface */ +- copy_config (urb, alternate_instance->interface_descriptor, +- sizeof (struct usb_interface_descriptor), +- max); +- +- /*dbg_ep0(3, "[%d:%d] classes: %d endpoints: %d", bNumInterface, bAlternateSetting, */ +- /* alternate_instance->classes, alternate_instance->endpoints); */ +- +- /* iterate across classes for this alternate interface */ +-#if 0 +- for (class = 0; +- class < alternate_instance->classes; +- class++) { +- struct usb_class_descriptor *class_descriptor; +- /*dbg_ep0(3, "[%d:%d:%d] classes: %d", bNumInterface, bAlternateSetting, */ +- /* class, alternate_instance->classes); */ +- if (!(class_descriptor = usbd_device_class_descriptor_index (device, port, index, bNumInterface, bAlternateSetting, class))) { +- dbg_ep0 (3, "[%d] class NULL", +- class); +- return -1; +- } +- /* copy descriptor for this class */ +- copy_config (urb, class_descriptor, +- sizeof (struct usb_class_descriptor), +- max); +- } +-#endif +- +- /* iterate across endpoints for this alternate interface */ +- interface_descriptor = alternate_instance->interface_descriptor; +- for (bNumEndpoint = 0; +- bNumEndpoint < alternate_instance->endpoints; +- bNumEndpoint++) { +- struct usb_endpoint_descriptor *endpoint_descriptor; +- dbg_ep0 (3, "[%d:%d:%d] endpoint: %d", +- bNumInterface, +- bAlternateSetting, +- bNumEndpoint, +- interface_descriptor-> +- bNumEndpoints); +- if (!(endpoint_descriptor = usbd_device_endpoint_descriptor_index (device, port, index, bNumInterface, bAlternateSetting, bNumEndpoint))) { +- dbg_ep0 (3, "[%d] endpoint NULL", +- bNumEndpoint); +- return -1; +- } +- /* copy descriptor for this endpoint */ +- copy_config (urb, endpoint_descriptor, +- sizeof (struct usb_endpoint_descriptor), +- max); +- } +- } +- } +- dbg_ep0 (3, "lengths: %d %d", +- le16_to_cpu (configuration_descriptor->wTotalLength), +- urb->actual_length); + } + break; + +@@ -363,6 +263,7 @@ + struct usb_string_descriptor *string_descriptor; + + if (!(string_descriptor = usbd_get_string (index))) { ++ dbg_ep0(0, "Invalid string index %u\n", index); + return -1; + } + /*dbg_ep0(3, "string_descriptor: %p", string_descriptor); */ +@@ -495,6 +396,8 @@ + + /* handle USB Standard Request (c.f. USB Spec table 9-2) */ + if ((request->bmRequestType & USB_REQ_TYPE_MASK) != 0) { ++ if (device->device_state <= STATE_CONFIGURED) ++ return device->cdc_recv_setup(request, urb); + dbg_ep0 (1, "non standard request: %x", + request->bmRequestType & USB_REQ_TYPE_MASK); + return -1; /* Stall here */ diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/unbusy-i2c.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/unbusy-i2c.patch new file mode 100644 index 0000000000..680b301620 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/unbusy-i2c.patch @@ -0,0 +1,88 @@ +board/neo1973/gta01/gta01.c: added logic to detect pending PMU interrupts +board/neo1973/gta01/gta01.c (neo1973_new_second, neo1973_on_key_pressed): only + poll PMU if there is a pending interrupt +board/neo1973/gta01/pcf50606.c (pcf50606_initial_regs): cleared (unmasked) + SECONDM in INT1M + +- Werner Almesberger + +Index: u-boot/board/neo1973/gta01/gta01.c +=================================================================== +--- u-boot.orig/board/neo1973/gta01/gta01.c ++++ u-boot/board/neo1973/gta01/gta01.c +@@ -375,19 +375,60 @@ + #endif + } + ++static int pwr_int_pending(void) ++{ ++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ ++#if defined(CONFIG_ARCH_GTA01B_v4) ++ return !(gpio->GPGDAT & (1 << 1)); /* EINT9/GPG1 */ ++#else ++ return !(gpio->GPGDAT & (1 << 8)); /* EINT16/GPG8 */ ++#endif /* !CONFIG_ARCH_GTA01B_v4 */ ++} ++ ++static int have_int1(uint8_t mask) ++{ ++ static uint8_t pending = 0; ++ ++ if (pwr_int_pending()) { ++ /* ++ * We retrieve all interupts, so that we clear any stray ones ++ * in INT2 and INT3. ++ */ ++ uint8_t int1,int2,int3; ++ ++ int1 = pcf50606_reg_read(PCF50606_REG_INT1); ++ int2 = pcf50606_reg_read(PCF50606_REG_INT2); ++ int3 = pcf50606_reg_read(PCF50606_REG_INT3); ++ pending |= int1; ++ } ++ if (!(pending & mask)) ++ return 0; ++ pending &= ~mask; ++ return 1; ++} ++ + int neo1973_new_second(void) + { +- return pcf50606_reg_read(PCF50606_REG_INT1) & PCF50606_INT1_SECOND; ++ return have_int1(PCF50606_INT1_SECOND); + } + + int neo1973_on_key_pressed(void) + { +- return !(pcf50606_reg_read(PCF50606_REG_OOCS) & PFC50606_OOCS_ONKEY); ++ static int pressed = -1; ++ ++ if (pressed == -1 || ++ have_int1(PCF50606_INT1_ONKEYF | PCF50606_INT1_ONKEYR)) { ++ pressed = !(pcf50606_reg_read(PCF50606_REG_OOCS) & ++ PFC50606_OOCS_ONKEY); ++} ++ return pressed; + } + + int neo1973_aux_key_pressed(void) + { + S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); ++ + if (gpio->GPFDAT & (1 << 6)) + return 0; + return 1; +Index: u-boot/board/neo1973/gta01/pcf50606.c +=================================================================== +--- u-boot.orig/board/neo1973/gta01/pcf50606.c ++++ u-boot/board/neo1973/gta01/pcf50606.c +@@ -6,7 +6,7 @@ + const u_int8_t pcf50606_initial_regs[__NUM_PCF50606_REGS] = { + [PCF50606_REG_OOCS] = 0x00, + /* gap */ +- [PCF50606_REG_INT1M] = PCF50606_INT1_SECOND, ++ [PCF50606_REG_INT1M] = 0x00, + [PCF50606_REG_INT2M] = 0x00, + [PCF50606_REG_INT3M] = PCF50606_INT3_TSCPRES, + [PCF50606_REG_OOCC1] = PCF50606_OOCC1_RTCWAK | diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/usbdcore-multiple_configs.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/usbdcore-multiple_configs.patch new file mode 100644 index 0000000000..339289699a --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/usbdcore-multiple_configs.patch @@ -0,0 +1,63 @@ +This patch fixes bugs in usbdcore*.c related to the use of devices +with multiple configurations. + +The original code made mistakes about the meaning of configuration value and +configuration index, and the resulting off-by-one errors resulted in: + +* SET_CONFIGURATION always selected the first configuration, no matter what + wValue is being passed. +* GET_DESCRIPTOR/CONFIGURATION always returned the descriptor for the first + configuration (index 0). + +Signed-off-by: Harald Welte + +Index: u-boot/drivers/usbdcore_ep0.c +=================================================================== +--- u-boot.orig/drivers/usbdcore_ep0.c 2007-03-14 20:29:05.000000000 +0100 ++++ u-boot/drivers/usbdcore_ep0.c 2007-03-14 20:29:06.000000000 +0100 +@@ -233,8 +233,8 @@ + return -1; + } + /*dbg_ep0(2, "%d %d", index, device_descriptor->bNumConfigurations); */ +- if (index > device_descriptor->bNumConfigurations) { +- dbg_ep0 (0, "index too large: %d > %d", index, ++ if (index >= device_descriptor->bNumConfigurations) { ++ dbg_ep0 (0, "index too large: %d >= %d", index, + device_descriptor-> + bNumConfigurations); + return -1; +@@ -593,13 +593,8 @@ + + case USB_REQ_SET_CONFIGURATION: + /* c.f. 9.4.7 - the top half of wValue is reserved */ +- /* */ +- if ((device->configuration = +- le16_to_cpu (request->wValue) & 0x7f) != 0) { +- /* c.f. 9.4.7 - zero is the default or addressed state, in our case this */ +- /* is the same is configuration zero */ +- device->configuration = 0; /* TBR - ?????? */ +- } ++ device->configuration = le16_to_cpu(request->wValue) & 0xff; ++ + /* reset interface and alternate settings */ + device->interface = device->alternate = 0; + +Index: u-boot/drivers/usbdcore.c +=================================================================== +--- u-boot.orig/drivers/usbdcore.c 2007-03-14 20:29:05.000000000 +0100 ++++ u-boot/drivers/usbdcore.c 2007-03-14 20:37:37.000000000 +0100 +@@ -147,12 +147,9 @@ + static struct usb_configuration_instance *usbd_device_configuration_instance (struct usb_device_instance *device, + unsigned int port, unsigned int configuration) + { +- /* XXX */ +- configuration = configuration ? configuration - 1 : 0; +- +- if (configuration >= device->configurations) { ++ if (configuration >= device->configurations) + return NULL; +- } ++ + return device->configuration_instance_array + configuration; + } + diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native/wakeup-reason-nand-only.patch b/packages/u-boot/u-boot-mkimage-openmoko-native/wakeup-reason-nand-only.patch new file mode 100644 index 0000000000..132a9f8da5 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native/wakeup-reason-nand-only.patch @@ -0,0 +1,68 @@ +This patch should get rid of spurious poweroff after booting from RAM. +Experimental. + +cpu/arm920t/start.S: record in global variable "booted_from_nand" whether we + booted from NAND or not +board/neo1973/neo1973.c (board_late_init): if booted from RAM, assume that + wakeup cause was "reset", and skip poweroff check + +- Werner Almesberger + +Index: u-boot/board/neo1973/gta01/gta01.c +=================================================================== +--- u-boot.orig/board/neo1973/gta01/gta01.c ++++ u-boot/board/neo1973/gta01/gta01.c +@@ -226,12 +226,16 @@ + + int board_late_init(void) + { ++ extern unsigned char booted_from_nand; + unsigned char tmp; + char buf[32]; + + /* Initialize the Power Management Unit with a safe register set */ + pcf50606_init(); + ++ if (!booted_from_nand) ++ goto woken_by_reset; ++ + /* obtain wake-up reason, save INT1 in environment */ + tmp = pcf50606_reg_read(PCF50606_REG_INT1); + sprintf(buf, "0x%02x", tmp); +@@ -274,6 +278,7 @@ + neo1973_poweroff(); + } + ++woken_by_reset: + /* if there's no other reason, must be regular reset */ + neo1973_wakeup_cause = NEO1973_WAKEUP_RESET; + +Index: u-boot/cpu/arm920t/start.S +=================================================================== +--- u-boot.orig/cpu/arm920t/start.S ++++ u-boot/cpu/arm920t/start.S +@@ -77,6 +77,14 @@ + ************************************************************************* + */ + ++#ifdef CONFIG_S3C2410_NAND_BOOT ++.globl booted_from_nand ++booted_from_nand: ++ .word 0 ++_booted_from_nand: ++ .word booted_from_nand ++#endif /* CONFIG_S3C2410_NAND_BOOT */ ++ + _TEXT_BASE: + .word TEXT_BASE + +@@ -281,6 +289,9 @@ + #endif + 1: b 1b + done_nand_read: ++ ldr r0, _booted_from_nand ++ mov r1, #1 ++ strb r1, [r0] + #endif /* CONFIG_S3C2410_NAND_BOOT */ + done_relocate: + #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ diff --git a/packages/u-boot/u-boot-mkimage-openmoko-native_oe.bb b/packages/u-boot/u-boot-mkimage-openmoko-native_oe.bb new file mode 100644 index 0000000000..e7812a5ed0 --- /dev/null +++ b/packages/u-boot/u-boot-mkimage-openmoko-native_oe.bb @@ -0,0 +1,86 @@ +require uboot-openmoko_svn.bb + +inherit native + +PV = "1.2.0+git9912121f7ed804ea58fd62f3f230b5dcfc357d88svn2238" +PR = "r1" + +SRC_URI = "git://www.denx.de/git/u-boot.git/;protocol=git;tag=9912121f7ed804ea58fd62f3f230b5dcfc357d88 \ +file://uboot-machtypes.patch;patch=1 \ +file://ext2load_hex.patch;patch=1 \ +file://uboot-s3c2410-warnings-fix.patch;patch=1 \ +file://uboot-strtoul.patch;patch=1 \ +file://uboot-cramfs_but_no_jffs2.patch;patch=1 \ +file://nand-read_write_oob.patch;patch=1 \ +file://uboot-arm920t-gd_in_irq.patch;patch=1 \ +file://uboot-arm920_s3c2410_irq_demux.patch;patch=1 \ +file://uboot-s3c2410-nand.patch;patch=1 \ +file://uboot-cmd_s3c2410.patch;patch=1 \ +file://uboot-s3c2410-mmc.patch;patch=1 \ +file://env_nand_oob.patch;patch=1 \ +file://dynenv-harden.patch;patch=1 \ +file://uboot-s3c2410_fb.patch;patch=1 \ +file://uboot-20061030-qt2410.patch;patch=1 \ +file://uboot-20061030-neo1973.patch;patch=1 \ +file://uboot-s3c2410-misccr-definitions.patch;patch=1 \ +file://boot-from-ram-reloc.patch;patch=1 \ +file://boot-from-ram-and-nand.patch;patch=1 \ +file://wakeup-reason-nand-only.patch;patch=1 \ +file://uboot-neo1973-resume.patch;patch=1 \ +file://nand-dynamic_partitions.patch;patch=1 \ +file://uboot-s3c2410-norelocate_irqvec_cpy.patch;patch=1 \ +file://uboot-usbtty-acm.patch;patch=1 \ +file://uboot-s3c2410_udc.patch;patch=1 \ +file://bbt-create-optional.patch;patch=1 \ +file://nand-createbbt.patch;patch=1 \ +file://dontask.patch;patch=1 \ +file://nand-badisbad.patch;patch=1 \ +file://uboot-bbt-quiet.patch;patch=1 \ +file://raise-limits.patch;patch=1 \ +file://splashimage-command.patch;patch=1 \ +file://cmd-unzip.patch;patch=1 \ +file://enable-splash-bmp.patch;patch=1 \ +file://preboot-override.patch;patch=1 \ +file://lowlevel_foo.patch;patch=1 \ +file://default-env.patch;patch=1 \ +file://console-ansi.patch;patch=1 \ +file://boot-menu.patch;patch=1 \ +file://uboot-dfu.patch;patch=1 \ +file://uboot-neo1973-defaultenv.patch;patch=1 \ +file://uboot-nand-markbad-reallybad.patch;patch=1 \ +file://usbdcore-multiple_configs.patch;patch=1 \ +file://neo1973-chargefast.patch;patch=1 \ +file://uboot-s3c2440.patch;patch=1 \ +file://uboot-smdk2440.patch;patch=1 \ +file://uboot-hxd8.patch;patch=1 \ +file://uboot-license.patch;patch=1 \ +file://uboot-gta02.patch;patch=1 \ +file://uboot-s3c2443.patch;patch=1 \ +file://uboot-smdk2443.patch;patch=1 \ +file://unbusy-i2c.patch;patch=1 \ +file://makefile-no-dirafter.patch;patch=1 \ +" + +PROVIDES = "" +TARGET_LDFLAGS = "" + +do_quilt() { +: +} + +do_compile () { + chmod +x board/neo1973/gta01/split_by_variant.sh + oe_runmake gta01bv3_config + oe_runmake clean + oe_runmake tools +} + +do_stage () { + install -m 0755 tools/mkimage ${STAGING_BINDIR}/uboot-mkimage + ln -sf ${STAGING_BINDIR}/uboot-mkimage ${STAGING_BINDIR}/mkimage +} + +do_deploy () { +: +} + diff --git a/packages/u-boot/u-boot-omap2430sdp-1.1.4/.mtn2git_empty b/packages/u-boot/u-boot-omap2430sdp-1.1.4/.mtn2git_empty new file mode 100644 index 0000000000..e69de29bb2 diff --git a/packages/u-boot/u-boot-omap2430sdp-1.1.4/u-boot-makefile-3.81.patch b/packages/u-boot/u-boot-omap2430sdp-1.1.4/u-boot-makefile-3.81.patch new file mode 100644 index 0000000000..f45a1d3aa3 --- /dev/null +++ b/packages/u-boot/u-boot-omap2430sdp-1.1.4/u-boot-makefile-3.81.patch @@ -0,0 +1,11 @@ +--- u-boot/examples/Makefile.orig 2007-08-13 13:09:59.000000000 -0700 ++++ u-boot/examples/Makefile 2007-08-13 13:11:34.000000000 -0700 +@@ -128,6 +128,8 @@ all: .depend $(OBJS) $(LIB) $(SREC) $(BI + $(LIB): .depend $(LIBOBJS) + $(AR) crv $@ $(LIBOBJS) + ++hello_world.srec: hello_world ++ + %: %.o $(LIB) + $(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \ + -o $@ -e $(<:.o=) $< $(LIB) \ diff --git a/packages/u-boot/u-boot-omap2430sdp_1.1.4.bb b/packages/u-boot/u-boot-omap2430sdp_1.1.4.bb new file mode 100644 index 0000000000..4dcc989107 --- /dev/null +++ b/packages/u-boot/u-boot-omap2430sdp_1.1.4.bb @@ -0,0 +1,13 @@ +require u-boot.inc +PR="r1" +DEFAULT_PREFERENCE = "-1" + +SRC_URI = "http://linux.omap.com/pub/bootloader/2430sdp/source/u-boot-SEP1106.tar.gz \ + file://u-boot-makefile-3.81.patch;patch=1 \ + " + +S = "${WORKDIR}/u-boot" + +PACKAGE_ARCH = "${MACHINE_ARCH}" + +#inherit base diff --git a/packages/u-boot/u-boot-openmoko_1.2.0+gitf34024d4a328e6edd906456da98d2c537155c4f7+svn2943.bb b/packages/u-boot/u-boot-openmoko_1.2.0+gitf34024d4a328e6edd906456da98d2c537155c4f7+svn2943.bb new file mode 100644 index 0000000000..1cee1edf37 --- /dev/null +++ b/packages/u-boot/u-boot-openmoko_1.2.0+gitf34024d4a328e6edd906456da98d2c537155c4f7+svn2943.bb @@ -0,0 +1,86 @@ +DESCRIPTION = "U-boot bootloader w/ Neo1973 (GTA01) support" +AUTHOR = "Harald Welte " +LICENSE = "GPL" +SECTION = "bootloader" +PRIORITY = "optional" + +UBOOT_UPSTREAM_REV = "f34024d4a328e6edd906456da98d2c537155c4f7" +UBOOT_OPENMOKO_REV = "2943" +UBOOT_MACHINES = "gta01bv2 gta01bv3 gta01bv4" + +PV = "1.2.0+git${UBOOT_UPSTREAM_REV}+svn${UBOOT_OPENMOKO_REV}" +PR = "r1" + +PROVIDES = "virtual/bootloader" +S = "${WORKDIR}/git" + +SRC_URI = "\ + git://www.denx.de/git/u-boot.git;protocol=git;tag=${UBOOT_UPSTREAM_REV} \ + svn://svn.openmoko.org/trunk/src/target/u-boot;module=patches;rev=${UBOOT_OPENMOKO_REV};proto=http \ + file://uboot-eabi-fix-HACK.patch \ + file://uboot-20070311-tools_makefile_ln_sf.patch;patch=1 \ + file://makefile-no-dirafter.patch;patch=1 \ +" + +EXTRA_OEMAKE = "CROSS_COMPILE=${TARGET_PREFIX}" +TARGET_LDFLAGS = "" + +do_quilt() { + mv ${WORKDIR}/patches ${S}/patches && cd ${S} && quilt push -av + rm -Rf patches .pc +} + +do_svnrev() { + mv -f tools/setlocalversion tools/setlocalversion.old + echo -n "echo " >>tools/setlocalversion + echo ${PV} >>tools/setlocalversion +} + +do_configure_prepend() { + find . -name "*.mk" -exec sed -i 's,-mabi=apcs-gnu,,' {} \; + find . -name "Makefile" -exec sed -i 's,-mabi=apcs-gnu,,' {} \; + cat ${WORKDIR}/uboot-eabi-fix-HACK.patch |patch -p1 +} + +do_compile () { + chmod +x board/neo1973/gta*/split_by_variant.sh + for mach in ${UBOOT_MACHINES} + do + oe_runmake ${mach}_config + oe_runmake clean + find board -name lowlevel_foo.bin -exec rm '{}' \; + oe_runmake all + oe_runmake u-boot.udfu + if [ -f u-boot.udfu ]; then + mv u-boot.udfu u-boot_${mach}.bin + else + mv u-boot.bin u-boot_${mach}.bin + fi + if [ -f board/${mach}/lowlevel_foo.bin ]; then + mv board/${mach}/lowlevel_foo.bin \ + lowlevel_foo_${mach}.bin + else + find board -name lowlevel_foo.bin \ + -exec mv '{}' lowlevel_foo_${mach}.bin \; + fi + done +} + +do_deploy () { + install -d ${DEPLOY_DIR_IMAGE} + for mach in ${UBOOT_MACHINES} + do + install -m 0644 ${S}/u-boot_${mach}.bin ${DEPLOY_DIR_IMAGE}/u-boot-${mach}-${PV}-${PR}.bin + ln -sf ${DEPLOY_DIR_IMAGE}/u-boot-${mach}-${PV}-${PR}.bin ${DEPLOY_DIR_IMAGE}/uboot-${mach}-latest.bin + if [ -f ${S}/lowlevel_foo_${mach}.bin ]; then + install -m 0644 ${S}/lowlevel_foo_${mach}.bin ${DEPLOY_DIR_IMAGE}/lowlevel_foo-${mach}-${PV}-${PR}.bin + ln -sf ${DEPLOY_DIR_IMAGE}/lowlevel_foo-${mach}-${PV}-${PR}.bin ${DEPLOY_DIR_IMAGE}/lowlevel-foo-${mach}-latest.bin + fi + done + install -m 0755 tools/mkimage ${STAGING_BINDIR_NATIVE}/uboot-mkimage +} + +do_deploy[dirs] = "${S}" +addtask deploy before do_package after do_install +addtask quilt before do_patch after do_unpack +addtask svnrev before do_patch after do_quilt diff --git a/packages/u-boot/u-boot-openmoko_svn.bb b/packages/u-boot/u-boot-openmoko_svn.bb new file mode 100644 index 0000000000..550ff5d499 --- /dev/null +++ b/packages/u-boot/u-boot-openmoko_svn.bb @@ -0,0 +1,85 @@ +DESCRIPTION = "U-boot bootloader w/ Neo1973 (GTA01) support" +AUTHOR = "Harald Welte " +LICENSE = "GPL" +SECTION = "bootloader" +PRIORITY = "optional" +PROVIDES = "virtual/bootloader" +LOCALVERSION = "+git${SRCDATE}+svnr${SRCREV}" +PV = "1.3.1${LOCALVERSION}" +PR = "r2" + +SRCREV_FORMAT = "patches" + +UBOOT_MACHINES = "gta01bv2 gta01bv3 gta01bv4 smdk2440 hxd8 qt2410 gta02v1 gta02v2 gta02v3 gta02v4" + +DEFAULT_PREFERENCE = "-1" + +SRC_URI = "\ + git://www.denx.de/git/u-boot.git/;protocol=git;name=upstream \ + svn://svn.openmoko.org/trunk/src/target/u-boot;module=patches;proto=http;name=patches \ + file://uboot-eabi-fix-HACK.patch \ + file://uboot-20070311-tools_makefile_ln_sf.patch;patch=1 \ + file://makefile-no-dirafter.patch;patch=1 \ + file://boot-menu-gfx-fix-openmoko-bug-1140.patch;patch=1 \ +" +S = "${WORKDIR}/git" + +EXTRA_OEMAKE = "CROSS_COMPILE=${TARGET_PREFIX}" +TARGET_LDFLAGS = "" + +do_quilt() { + mv ${WORKDIR}/patches ${S}/patches && cd ${S} && quilt push -av + rm -Rf patches .pc +} + +do_svnrev() { + mv -f tools/setlocalversion tools/setlocalversion.old + echo "echo ${LOCALVERSION}" >>tools/setlocalversion +} + +do_configure_prepend() { + find . -name "*.mk" -exec sed -i 's,-mabi=apcs-gnu,,' {} \; + find . -name "Makefile" -exec sed -i 's,-mabi=apcs-gnu,,' {} \; + cat ${WORKDIR}/uboot-eabi-fix-HACK.patch |patch -p1 +} + +do_compile () { + chmod +x board/neo1973/gta*/split_by_variant.sh + for mach in ${UBOOT_MACHINES} + do + oe_runmake ${mach}_config + oe_runmake clean + find board -name lowlevel_foo.bin -exec rm '{}' \; + oe_runmake all + oe_runmake u-boot.udfu + if [ -f u-boot.udfu ]; then + mv u-boot.udfu u-boot_${mach}.bin + else + mv u-boot.bin u-boot_${mach}.bin + fi + if [ -f board/${mach}/lowlevel_foo.bin ]; then + mv board/${mach}/lowlevel_foo.bin lowlevel_foo_${mach}.bin + else + find board -name lowlevel_foo.bin -exec mv '{}' lowlevel_foo_${mach}.bin \; + fi + done +} + +do_deploy () { + install -d ${DEPLOY_DIR_IMAGE} + for mach in ${UBOOT_MACHINES} + do + install -m 0644 ${S}/u-boot_${mach}.bin ${DEPLOY_DIR_IMAGE}/u-boot-${mach}-${PV}-${PR}.bin + ln -sf ${DEPLOY_DIR_IMAGE}/u-boot-${mach}-${PV}-${PR}.bin ${DEPLOY_DIR_IMAGE}/uboot-${mach}-latest.bin + if [ -f ${S}/lowlevel_foo_${mach}.bin ]; then + install -m 0644 ${S}/lowlevel_foo_${mach}.bin ${DEPLOY_DIR_IMAGE}/lowlevel_foo-${mach}-${PV}-${PR}.bin + ln -sf ${DEPLOY_DIR_IMAGE}/lowlevel_foo-${mach}-${PV}-${PR}.bin ${DEPLOY_DIR_IMAGE}/lowlevel-foo-${mach}-latest.bin + fi + done + install -m 0755 tools/mkimage ${STAGING_BINDIR_NATIVE}/uboot-mkimage +} + +do_deploy[dirs] = "${S}" +addtask deploy before do_package after do_install +addtask quilt before do_patch after do_unpack +addtask svnrev before do_patch after do_quilt diff --git a/packages/u-boot/u-boot-utils-native_1.2.0.bb b/packages/u-boot/u-boot-utils-native_1.2.0.bb new file mode 100644 index 0000000000..b04b366ffe --- /dev/null +++ b/packages/u-boot/u-boot-utils-native_1.2.0.bb @@ -0,0 +1,27 @@ +DESCRIPTION = "U-boot bootloader mkimage utility" +SECTION = "bootloaders" +PRIORITY = "optional" +LICENSE = "GPL" +ALLOW_EMPTY = "1" +PR = "r1" + +SRC_URI = "ftp://ftp.denx.de/pub/u-boot/u-boot-${PV}.tar.bz2" + +S = "${WORKDIR}/u-boot-${PV}" + +inherit native + +do_configure() { + : +} + +do_compile () { + oe_runmake Sandpoint8240_config + oe_runmake tools +} + +# install mkimage for the kernel makefile +do_stage() { + install -m 0755 tools/mkimage ${STAGING_BINDIR_NATIVE}/ +} + diff --git a/packages/u-boot/u-boot-utils_1.2.0.bb b/packages/u-boot/u-boot-utils_1.2.0.bb new file mode 100644 index 0000000000..1734b41a0e --- /dev/null +++ b/packages/u-boot/u-boot-utils_1.2.0.bb @@ -0,0 +1,38 @@ +DESCRIPTION = "U-boot bootloader OS env. access tools" +SECTION = "bootloaders" +PRIORITY = "optional" +LICENSE = "GPL" +DEPENDS = "mtd-utils" +PR = "r7" + +SRC_URI = "ftp://ftp.denx.de/pub/u-boot/u-boot-${PV}.tar.bz2 \ + file://fw_env.c.patch;patch=1 \ + file://tools-Makefile.patch;patch=1 \ + file://env-Makefile.patch;patch=1 \ + file://fw_env.config" + +S = "${WORKDIR}/u-boot-${PV}" + +FILESDIR = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/u-boot-${PV}" + +do_configure() { + : +} + +do_compile () { + oe_runmake Sandpoint8240_config + oe_runmake tools +} + +do_install () { + : +} + +do_install_openprotium () { + install -d ${D}/sbin + install -d ${D}${sysconfdir} + install -m 644 ${WORKDIR}/fw_env.config ${D}${sysconfdir}/fw_env.config + install -m 755 ${S}/tools/env/fw_printenv ${D}/sbin/fw_printenv + install -m 755 ${S}/tools/env/fw_printenv ${D}/sbin/fw_setenv +} + diff --git a/packages/u-boot/u-boot.inc b/packages/u-boot/u-boot.inc new file mode 100644 index 0000000000..9f7356d5d7 --- /dev/null +++ b/packages/u-boot/u-boot.inc @@ -0,0 +1,33 @@ +DESCRIPTION = "U-boot bootloader" +HOMEPAGE = "http://u-boot.sf.net" +SECTION = "bootloaders" +PRIORITY = "optional" +LICENSE = "GPL" +PROVIDES = "virtual/bootloader" + +PARALLEL_MAKE="" + +EXTRA_OEMAKE = "CROSS_COMPILE=${TARGET_PREFIX}" + +UBOOT_MACHINE ?= "${MACHINE}_config" +UBOOT_IMAGE = "u-boot-${MACHINE}-${PV}-${PR}.bin" + +do_compile () { + unset LDFLAGS + unset CFLAGS + unset CPPFLAGS + oe_runmake ${UBOOT_MACHINE} + oe_runmake all +} + +do_deploy () { + install -d ${DEPLOY_DIR_IMAGE} + install ${S}/u-boot.bin ${DEPLOY_DIR_IMAGE}/${UBOOT_IMAGE} +} +do_deploy[dirs] = "${S}" +addtask deploy before do_build after do_compile + +do_stage() { + install -d ${STAGING_BINDIR_NATIVE} + install -m 755 tools/mkimage ${STAGING_BINDIR_NATIVE}/ +} diff --git a/packages/u-boot/u-boot_1.1.2.bb b/packages/u-boot/u-boot_1.1.2.bb new file mode 100644 index 0000000000..82b169ccc4 --- /dev/null +++ b/packages/u-boot/u-boot_1.1.2.bb @@ -0,0 +1,49 @@ +PR = "r2" +require u-boot.inc + +SRC_URI = "ftp://ftp.denx.de/pub/u-boot/u-boot-${PV}.tar.bz2 \ + file://arm_flags.patch;patch=1 " +SRC_URI_append_vibren = "ftp://bec-systems.com/pub/pxa255_idp/u-boot/uboot_pxa255-idp_2005-03-23.patch;patch=1" +SRC_URI_append_mnci = "file://mnci.patch;patch=1 \ + file://mnci-jffs2.patch;patch=1 \ + file://cmd-arm-linux.patch;patch=1 \ + file://command-names.patch;patch=1" + +SRC_URI_append_magicbox = "file://u-boot-emetec.patch;patch=1 " +SRC_URI_append_bd-neon = "file://u-boot-1.1.2-neon.patch;patch=1" + +# TODO: SRC_URI_append_rt3000 + +TARGET_LDFLAGS = "" + +UBOOT_MACHINE_mnci = "mnci_config" +UBOOT_MACHINE_vibren = "pxa255_idp_config" +UBOOT_MACHINE_magicbox = "EMETEC405_config" + +inherit base + +do_compile () { + oe_runmake ${UBOOT_MACHINE} + oe_runmake all +} + +######################################################### + +RDEPENDS_append_mnci = " hwctrl" + +FILES_${PN}_mnci = "/tmp/${UBOOT_IMAGE}" +do_install_openmn() { + install -d ${D}/tmp + install ${S}/u-boot.bin ${D}/tmp/${UBOOT_IMAGE} +} + +pkg_postinst_mnci() { +ldconfig +A=/tmp/bootargs +hwctrl kernel_conf_get bootargs >$A +cp /tmp/${UBOOT_IMAGE} /dev/mtdblock/0 +rm /tmp/${UBOOT_IMAGE} +hwctrl kernel_conf_set bootargs "`cat $A`" +cat /dev/mtdblock/0 >/dev/null +exit 0 +} diff --git a/packages/u-boot/u-boot_1.1.4.bb b/packages/u-boot/u-boot_1.1.4.bb new file mode 100644 index 0000000000..7a92b57c34 --- /dev/null +++ b/packages/u-boot/u-boot_1.1.4.bb @@ -0,0 +1,53 @@ +require u-boot.inc + +DEFAULT_PREFERENCE = "-1" + +SRC_URI = "ftp://ftp.denx.de/pub/u-boot/u-boot-${PV}.tar.bz2 \ + file://u-boot-make381-fix.patch;patch=1" + +SRC_URI_append_gumstix = "\ + file://u-boot-autoscript.patch;patch=1 \ + file://u-boot-base.patch;patch=1 \ + file://u-boot-crc-warning-not-so-scary.patch;patch=1 \ + file://u-boot-flash-protect-fixup.patch;patch=1 \ + file://u-boot-fw_printenv.patch;patch=1 \ + file://u-boot-install.patch;patch=1 \ + file://u-boot-jerase-cmd.patch;patch=1 \ + file://u-boot-jffs2-new-nodetypes.patch;patch=1 \ + file://u-boot-loadb-safe.patch;patch=1 \ + file://u-boot-mmc-init.patch;patch=1 \ + file://u-boot-mmcclk-alternate.patch;patch=1 \ + file://u-boot-smc91x-multi.patch;patch=1 \ + file://u-boot-zzz-osx.patch;patch=1" +SRC_URI_append_amsdelta = "\ + http://the.earth.li/pub/e3/u-boot-amsdelta-20060519.diff;patch=1" + +SRC_URI_append_dht-walnut= "\ + file://u-boot-dht-walnut-df2.patch;patch=1" + +SRC_URI_append_avr32= "\ + http://avr32linux.org/twiki/pub/Main/UbootPatches/u-boot-1.1.4-avr1.patch.bz2;patch=1" + + +EXTRA_OEMAKE_gumstix = "CROSS_COMPILE=${TARGET_PREFIX} GUMSTIX_400MHZ=${GUMSTIX_400MHZ}" +TARGET_LDFLAGS = "" + +UBOOT_MACHINE_dht-walnut = "walnut_config" +UBOOT_MACHINE_atngw100 = "atngw_config" + +def gumstix_mhz(d): + import bb + m = bb.data.getVar('GUMSTIX_400MHZ', d, 1) + if 'y' == m: + return '400' + else: + return '200' + +UBOOT_IMAGE_gumstix = "u-boot-${MACHINE}-${@gumstix_mhz(d)}Mhz-${PV}-${PR}.bin" + +inherit base + +do_compile () { + oe_runmake ${UBOOT_MACHINE} + oe_runmake all +} diff --git a/packages/u-boot/u-boot_1.1.6.bb b/packages/u-boot/u-boot_1.1.6.bb new file mode 100644 index 0000000000..e003c69d7b --- /dev/null +++ b/packages/u-boot/u-boot_1.1.6.bb @@ -0,0 +1,25 @@ +require u-boot.inc + +PR = "r3" + +SRC_URI = "ftp://ftp.denx.de/pub/u-boot/u-boot-1.1.6.tar.bz2 \ + file://devkit-idp.patch;patch=1 \ +" + +SRC_URI_append_sarge-at91 = " file://sarge-uboot.patch;patch=1" + +SRC_URI_append_mpc8323e-rdb = " file://u-boot-1.1.6-fsl-1-mpc83xx-20061206.patch;patch=1 \ + file://u-boot-1.1.6-fsl-1-Fix-the-UEC-driver-bug-of-QE.patch;patch=1 \ + file://u-boot-1.1.6-fsl-1-streamline-the-83xx-immr-head-file.patch;patch=1 \ + file://u-boot-1.1.6-fsl-1-Add-support-for-the-MPC832XEMDS-board.patch;patch=1 \ + file://u-boot-1.1.6-fsl-1-Add-the-MPC832XEMDS-board-readme.patch;patch=1 \ + file://u-boot-1.1.6-fsl-1-Added-MPC8323E-RDB-board-support-2.patch;patch=1 \ + file://u-boot-1.1.6-fsl-1-UEC-remove-udelay.patch;patch=1 \ + file://u-boot-1.1.6-83xx-optimizations.patch;patch=1 \ +" + + + +PACKAGE_ARCH = "${MACHINE_ARCH}" + +UBOOT_MACHINE_sarge-at91 = "sarge_config" diff --git a/packages/u-boot/u-boot_1.2.0.bb b/packages/u-boot/u-boot_1.2.0.bb new file mode 100644 index 0000000000..f1075bb00b --- /dev/null +++ b/packages/u-boot/u-boot_1.2.0.bb @@ -0,0 +1,25 @@ +require u-boot.inc + +PR = "r2" + +SRC_URI = "ftp://ftp.denx.de/pub/u-boot/u-boot-1.2.0.tar.bz2 \ + " +SRC_URI_append_turbostation = "file://qnap.diff;patch=1" + +SRC_URI_append_lsppchg = "file://u-boot-kurobox.patch;patch=1 \ + file://u-boot-kurobox-fdt.patch;patch=1 \ + file://defconfig_lsppchg" + +SRC_URI_append_lsppchd = "file://u-boot-kurobox.patch;patch=1 \ + file://u-boot-kurobox-fdt.patch;patch=1 \ + file://defconfig_lsppchg" + +do_compile_prepend_lsppchg () { + cp ${WORKDIR}/defconfig_lsppchg ${S}/include/configs/linkstation.h +} + +do_compile_prepend_lsppchd () { + cp ${WORKDIR}/defconfig_lsppchd ${S}/include/configs/linkstation.h +} + +PACKAGE_ARCH = "${MACHINE_ARCH}" diff --git a/packages/u-boot/u-boot_1.3.0.bb b/packages/u-boot/u-boot_1.3.0.bb new file mode 100644 index 0000000000..2886ddecc8 --- /dev/null +++ b/packages/u-boot/u-boot_1.3.0.bb @@ -0,0 +1,7 @@ +require u-boot.inc + +DEFAULT_PREFERENCE = "-1" + +SRC_URI = "ftp://ftp.denx.de/pub/u-boot/u-boot-${PV}.tar.bz2" + +PACKAGE_ARCH = "${MACHINE_ARCH}" diff --git a/packages/u-boot/u-boot_git.bb b/packages/u-boot/u-boot_git.bb new file mode 100644 index 0000000000..60ab0ab3f6 --- /dev/null +++ b/packages/u-boot/u-boot_git.bb @@ -0,0 +1,10 @@ +require u-boot.inc +PR="r1" +DEFAULT_PREFERENCE = "-1" + +SRC_URI = "git://www.denx.de/git/u-boot.git;protocol=git " +SRC_URI_sequoia = "git://www.denx.de/git/u-boot.git;protocol=git;tag=cf3b41e0c1111dbb865b6e34e9f3c3d3145a6093 " + +S = "${WORKDIR}/git" + +PACKAGE_ARCH = "${MACHINE_ARCH}" -- cgit v1.2.3