From 7eb65ad93b115bfb02048479c46c1cc10cb7f5e3 Mon Sep 17 00:00:00 2001 From: John Bowler Date: Sat, 29 Oct 2005 01:28:23 +0000 Subject: nslu2-kernel: comment update, no change to 2.6.14 --- packages/linux/nslu2-kernel/2.6.14/10-ixp4xx-copy-from.patch | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'packages/linux') diff --git a/packages/linux/nslu2-kernel/2.6.14/10-ixp4xx-copy-from.patch b/packages/linux/nslu2-kernel/2.6.14/10-ixp4xx-copy-from.patch index db71342ab0..f2e65ecd8f 100644 --- a/packages/linux/nslu2-kernel/2.6.14/10-ixp4xx-copy-from.patch +++ b/packages/linux/nslu2-kernel/2.6.14/10-ixp4xx-copy-from.patch @@ -12,12 +12,12 @@ #include -+/* On a little-endian IXP4XX system (tested on NSLU2) contrary to the -+ * Intel documentation LDRH/STRH appears to XOR the address with 10b. ++/* On a little-endian IXP4XX system (tested on NSLU2) an LDRH or STRH ++ * will flip the second address bit - i.e. XOR the address with 10b. + * This causes the cfi commands (sent to the command address, 0xAA for + * 16 bit flash) to fail. This is fixed here by XOR'ing the address + * before use with 10b. The cost of this is that the flash layout ends -+ * up with pdp-endiannes (on an LE syste), however this is not a problem ++ * up with pdp-endiannes (on an LE system), however this is not a problem + * as the access code consistently only accesses half words - so the + * endianness is not determinable on stuff which is written and read + * consistently in the little endian world. -- cgit v1.2.3