From 0b07e526611dc0e1867caa3eb6e4372855488026 Mon Sep 17 00:00:00 2001 From: Holger Freyther Date: Tue, 15 Jan 2008 22:58:54 +0000 Subject: packages/gcc/gcc-cross_4.2.2: Attempt to fix the fortran issue f951 was not executable because libmpfr and libgmp which were build by OpenEmbedded were not found. They resist in the staging lib directory and we do not have the LD_LIBRARY_PATH set. --enable-rpath for gcc was not an option, as we would have difficulties to say which path would be checked (we install to cross and not staging). Attempt to set an rpath when linking to mpfr/gmp. We pass --with-mpfr to the gcc-cross, patch the configure to add an -Wl,-rpath, to gmplibs, this gets set to GMPLIBS, which gets replaced to HOST_GMPLIBS in the Makefile inside the builddir, which will be used when linking the f951 utility. --- .../fortran-libs-rpath-to-staging-hack.patch | 48 ++++++++++++++++++++++ packages/gcc/gcc-cross_4.2.2.bb | 1 + 2 files changed, 49 insertions(+) create mode 100644 packages/gcc/gcc-4.2.2/fortran-libs-rpath-to-staging-hack.patch (limited to 'packages/gcc') diff --git a/packages/gcc/gcc-4.2.2/fortran-libs-rpath-to-staging-hack.patch b/packages/gcc/gcc-4.2.2/fortran-libs-rpath-to-staging-hack.patch new file mode 100644 index 0000000000..bf319f8b0a --- /dev/null +++ b/packages/gcc/gcc-4.2.2/fortran-libs-rpath-to-staging-hack.patch @@ -0,0 +1,48 @@ +f951 (fortran) links to MPFR and GMP of our staging area but when executing +the command the libs can not be found. Use rpath like all the other apps in +our staging bin/ directory. + +Patch the configure to avoid the regeneration... + +Index: gcc-4.2.2/configure +=================================================================== +--- gcc-4.2.2.orig/configure 2008-01-15 23:23:41.000000000 +0100 ++++ gcc-4.2.2/configure 2008-01-15 23:25:20.000000000 +0100 +@@ -2278,14 +2278,14 @@ + + + if test "x$with_mpfr" != x; then +- gmplibs="-L$with_mpfr/lib $gmplibs" ++ gmplibs="-Wl,-rpath,$with_mpfr/lib -L$with_mpfr/lib $gmplibs" + gmpinc="-I$with_mpfr/include" + fi + if test "x$with_mpfr_include" != x; then + gmpinc="-I$with_mpfr_include" + fi + if test "x$with_mpfr_lib" != x; then +- gmplibs="-L$with_mpfr_lib $gmplibs" ++ gmplibs="-Wl,-rpath,$with_mpfr_lib -L$with_mpfr_lib $gmplibs" + fi + + # Specify a location for gmp +Index: gcc-4.2.2/configure.in +=================================================================== +--- gcc-4.2.2.orig/configure.in 2008-01-15 23:23:41.000000000 +0100 ++++ gcc-4.2.2/configure.in 2008-01-15 23:24:36.000000000 +0100 +@@ -1066,14 +1066,14 @@ + AC_ARG_WITH(mpfr_lib, [ --with-mpfr-lib=PATH Specify the directory for the installed MPFR library]) + + if test "x$with_mpfr" != x; then +- gmplibs="-L$with_mpfr/lib $gmplibs" ++ gmplibs="-Wl,-rpath,$with_mpfr/lib -L$with_mpfr/lib $gmplibs" + gmpinc="-I$with_mpfr/include" + fi + if test "x$with_mpfr_include" != x; then + gmpinc="-I$with_mpfr_include" + fi + if test "x$with_mpfr_lib" != x; then +- gmplibs="-L$with_mpfr_lib $gmplibs" ++ gmplibs="-Wl,-rpath,$with_mpfr_lib -L$with_mpfr_lib $gmplibs" + fi + + # Specify a location for gmp diff --git a/packages/gcc/gcc-cross_4.2.2.bb b/packages/gcc/gcc-cross_4.2.2.bb index ec169072af..3984147eae 100644 --- a/packages/gcc/gcc-cross_4.2.2.bb +++ b/packages/gcc/gcc-cross_4.2.2.bb @@ -15,6 +15,7 @@ require gcc3-build-cross.inc # cross packaging require gcc-package-cross.inc SRC_URI_append_fail-fast = " file://zecke-no-host-includes.patch;patch=1 " +SRC_URI_append = " file://fortran-libs-rpath-to-staging-hack.patch;patch=1 " # Do not build libssp libmudflap and libgomp # We might need them for some beefy targets EXTRA_OECONF += "--disable-libunwind-exceptions --disable-libssp \ -- cgit v1.2.3 From 100dd10ab554d037081f5649c3bfa8e4d6c70c74 Mon Sep 17 00:00:00 2001 From: Jeremy Laine Date: Wed, 16 Jan 2008 12:00:05 +0000 Subject: gcc_4.2.2.bb: add patch for powerpc e300c2 and e300c3 cores --- packages/gcc/gcc-4.2.2/gcc-4.0.2-e300c2c3.patch | 311 ++++++++++++++++++++++++ packages/gcc/gcc-cross_4.2.2.bb | 2 +- packages/gcc/gcc_4.2.2.bb | 3 +- 3 files changed, 314 insertions(+), 2 deletions(-) create mode 100644 packages/gcc/gcc-4.2.2/gcc-4.0.2-e300c2c3.patch (limited to 'packages/gcc') diff --git a/packages/gcc/gcc-4.2.2/gcc-4.0.2-e300c2c3.patch b/packages/gcc/gcc-4.2.2/gcc-4.0.2-e300c2c3.patch new file mode 100644 index 0000000000..736ac4b6b6 --- /dev/null +++ b/packages/gcc/gcc-4.2.2/gcc-4.0.2-e300c2c3.patch @@ -0,0 +1,311 @@ +Adds support for Freescale Power architecture e300c2 and e300c3 cores. +http://www.bitshrine.org/gpp/tc-fsl-x86lnx-e300c3-nptl-4.0.2-2.src.rpm + +Leon Woestenberg + +Index: gcc-4.1.2/gcc/config/rs6000/e300c2c3.md +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ gcc-4.1.2/gcc/config/rs6000/e300c2c3.md 2007-10-18 15:32:51.000000000 +0200 +@@ -0,0 +1,189 @@ ++;; Pipeline description for Motorola PowerPC e300c3 core. ++;; Copyright (C) 2003 Free Software Foundation, Inc. ++;; ++;; This file is part of GCC. ++ ++;; GCC is free software; you can redistribute it and/or modify it ++;; under the terms of the GNU General Public License as published ++;; by the Free Software Foundation; either version 2, or (at your ++;; option) any later version. ++ ++;; GCC is distributed in the hope that it will be useful, but WITHOUT ++;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++;; License for more details. ++ ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING. If not, write to the ++;; Free Software Foundation, 59 Temple Place - Suite 330, Boston, ++;; MA 02111-1307, USA. ++ ++(define_automaton "ppce300c3_most,ppce300c3_long,ppce300c3_retire") ++(define_cpu_unit "ppce300c3_decode_0,ppce300c3_decode_1" "ppce300c3_most") ++ ++;; We don't simulate general issue queue (GIC). If we have SU insn ++;; and then SU1 insn, they can not be issued on the same cycle ++;; (although SU1 insn and then SU insn can be issued) because the SU ++;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle ++;; multipass insn scheduling will find the situation and issue the SU1 ++;; insn and then the SU insn. ++(define_cpu_unit "ppce300c3_issue_0,ppce300c3_issue_1" "ppce300c3_most") ++ ++;; We could describe completion buffers slots in combination with the ++;; retirement units and the order of completion but the result ++;; automaton would behave in the same way because we can not describe ++;; real latency time with taking in order completion into account. ++;; Actually we could define the real latency time by querying reserved ++;; automaton units but the current scheduler uses latency time before ++;; issuing insns and making any reservations. ++;; ++;; So our description is aimed to achieve a insn schedule in which the ++;; insns would not wait in the completion buffer. ++(define_cpu_unit "ppce300c3_retire_0,ppce300c3_retire_1" "ppce300c3_retire") ++ ++;; Branch unit: ++(define_cpu_unit "ppce300c3_bu" "ppce300c3_most") ++ ++;; IU: ++(define_cpu_unit "ppce300c3_iu0_stage0,ppce300c3_iu1_stage0" "ppce300c3_most") ++ ++;; IU: This used to describe non-pipelined division. ++(define_cpu_unit "ppce300c3_mu_div" "ppce300c3_long") ++ ++;; SRU: ++(define_cpu_unit "ppce300c3_sru_stage0" "ppce300c3_most") ++ ++;; Here we simplified LSU unit description not describing the stages. ++(define_cpu_unit "ppce300c3_lsu" "ppce300c3_most") ++ ++;; FPU: ++(define_cpu_unit "ppce300c3_fpu" "ppce300c3_most") ++ ++;; The following units are used to make automata deterministic ++(define_cpu_unit "present_ppce300c3_decode_0" "ppce300c3_most") ++(define_cpu_unit "present_ppce300c3_issue_0" "ppce300c3_most") ++(define_cpu_unit "present_ppce300c3_retire_0" "ppce300c3_retire") ++(define_cpu_unit "present_ppce300c3_iu0_stage0" "ppce300c3_most") ++ ++;; The following sets to make automata deterministic when option ndfa is used. ++(presence_set "present_ppce300c3_decode_0" "ppce300c3_decode_0") ++(presence_set "present_ppce300c3_issue_0" "ppce300c3_issue_0") ++(presence_set "present_ppce300c3_retire_0" "ppce300c3_retire_0") ++(presence_set "present_ppce300c3_iu0_stage0" "ppce300c3_iu0_stage0") ++ ++;; Some useful abbreviations. ++(define_reservation "ppce300c3_decode" ++ "ppce300c3_decode_0|ppce300c3_decode_1+present_ppce300c3_decode_0") ++(define_reservation "ppce300c3_issue" ++ "ppce300c3_issue_0|ppce300c3_issue_1+present_ppce300c3_issue_0") ++(define_reservation "ppce300c3_retire" ++ "ppce300c3_retire_0|ppce300c3_retire_1+present_ppce300c3_retire_0") ++(define_reservation "ppce300c3_iu_stage0" ++ "ppce300c3_iu0_stage0|ppce300c3_iu1_stage0+present_ppce300c3_iu0_stage0") ++ ++;; Compares can be executed either one of the IU or SRU ++(define_insn_reservation "ppce300c3_cmp" 1 ++ (and (eq_attr "type" "cmp,compare,delayed_compare,fast_compare") ++ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) ++ "ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \ ++ +ppce300c3_retire") ++ ++;; Other one cycle IU insns ++(define_insn_reservation "ppce300c3_iu" 1 ++ (and (eq_attr "type" "integer,insert_word") ++ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire") ++ ++;; Branch. Actually this latency time is not used by the scheduler. ++(define_insn_reservation "ppce300c3_branch" 1 ++ (and (eq_attr "type" "jmpreg,branch") ++ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) ++ "ppce300c3_decode,ppce300c3_bu,ppce300c3_retire") ++ ++;; Multiply is non-pipelined but can be executed in any IU ++(define_insn_reservation "ppce300c3_multiply" 2 ++ (and (eq_attr "type" "imul,imul2,imul3,imul_compare") ++ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0, \ ++ ppce300c3_iu_stage0+ppce300c3_retire") ++ ++;; Divide. We use the average latency time here. We omit reserving a ++;; retire unit because of the result automata will be huge. ++(define_insn_reservation "ppce300c3_divide" 20 ++ (and (eq_attr "type" "idiv") ++ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_mu_div,\ ++ ppce300c3_mu_div*19") ++ ++;; CR logical ++(define_insn_reservation "ppce300c3_cr_logical" 1 ++ (and (eq_attr "type" "cr_logical,delayed_cr") ++ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire") ++ ++;; Mfcr ++(define_insn_reservation "ppce300c3_mfcr" 1 ++ (and (eq_attr "type" "mfcr") ++ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire") ++ ++;; Mtcrf ++(define_insn_reservation "ppce300c3_mtcrf" 1 ++ (and (eq_attr "type" "mtcr") ++ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire") ++ ++;; Mtjmpr ++(define_insn_reservation "ppce300c3_mtjmpr" 1 ++ (and (eq_attr "type" "mtjmpr,mfjmpr") ++ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire") ++ ++;; Float point instructions ++(define_insn_reservation "ppce300c3_fpcompare" 3 ++ (and (eq_attr "type" "fpcompare") ++ (eq_attr "cpu" "ppce300c3")) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire") ++ ++(define_insn_reservation "ppce300c3_fp" 3 ++ (and (eq_attr "type" "fp") ++ (eq_attr "cpu" "ppce300c3")) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire") ++ ++(define_insn_reservation "ppce300c3_dmul" 4 ++ (and (eq_attr "type" "dmul") ++ (eq_attr "cpu" "ppce300c3")) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu,nothing,ppce300c3_retire") ++ ++; Divides are not pipelined ++(define_insn_reservation "ppce300c3_sdiv" 18 ++ (and (eq_attr "type" "sdiv") ++ (eq_attr "cpu" "ppce300c3")) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*17") ++ ++(define_insn_reservation "ppce300c3_ddiv" 33 ++ (and (eq_attr "type" "ddiv") ++ (eq_attr "cpu" "ppce300c3")) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*32") ++ ++;; Loads ++(define_insn_reservation "ppce300c3_load" 2 ++ (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u") ++ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") ++ ++(define_insn_reservation "ppce300c3_fpload" 2 ++ (and (eq_attr "type" "fpload,fpload_ux,fpload_u") ++ (eq_attr "cpu" "ppce300c3")) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") ++ ++;; Stores. ++(define_insn_reservation "ppce300c3_store" 2 ++ (and (eq_attr "type" "store,store_ux,store_u") ++ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") ++ ++(define_insn_reservation "ppce300c3_fpstore" 2 ++ (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") ++ (eq_attr "cpu" "ppce300c3")) ++ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") +Index: gcc-4.1.2/gcc/config/rs6000/rs6000.c +=================================================================== +--- gcc-4.1.2.orig/gcc/config/rs6000/rs6000.c 2006-12-16 20:24:56.000000000 +0100 ++++ gcc-4.1.2/gcc/config/rs6000/rs6000.c 2007-10-18 15:34:26.000000000 +0200 +@@ -557,6 +557,21 @@ + COSTS_N_INSNS (29), /* ddiv */ + }; + ++/* Instruction costs on E300C2 and E300C3 cores. */ ++static const ++struct processor_costs ppce300c2c3_cost = { ++ COSTS_N_INSNS (4), /* mulsi */ ++ COSTS_N_INSNS (4), /* mulsi_const */ ++ COSTS_N_INSNS (4), /* mulsi_const9 */ ++ COSTS_N_INSNS (4), /* muldi */ ++ COSTS_N_INSNS (19), /* divsi */ ++ COSTS_N_INSNS (19), /* divdi */ ++ COSTS_N_INSNS (3), /* fp */ ++ COSTS_N_INSNS (4), /* dmul */ ++ COSTS_N_INSNS (18), /* sdiv */ ++ COSTS_N_INSNS (33), /* ddiv */ ++}; ++ + /* Instruction costs on POWER4 and POWER5 processors. */ + static const + struct processor_costs power4_cost = { +@@ -1140,6 +1155,8 @@ + /* 8548 has a dummy entry for now. */ + {"8548", PROCESSOR_PPC8540, + POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_STRICT_ALIGN}, ++ {"e300c2", PROCESSOR_PPCE300C2, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, ++ {"e300c3", PROCESSOR_PPCE300C3, POWERPC_BASE_MASK}, + {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT}, + {"970", PROCESSOR_POWER4, + POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64}, +@@ -1529,6 +1546,11 @@ + rs6000_cost = &ppc8540_cost; + break; + ++ case PROCESSOR_PPCE300C2: ++ case PROCESSOR_PPCE300C3: ++ rs6000_cost = &ppce300c2c3_cost; ++ break; ++ + case PROCESSOR_POWER4: + case PROCESSOR_POWER5: + rs6000_cost = &power4_cost; +@@ -16647,6 +16669,8 @@ + case CPU_PPC750: + case CPU_PPC7400: + case CPU_PPC8540: ++ case CPU_PPCE300C2: ++ case CPU_PPCE300C3: + return 2; + case CPU_RIOS2: + case CPU_PPC604: +Index: gcc-4.1.2/gcc/config/rs6000/rs6000.h +=================================================================== +--- gcc-4.1.2.orig/gcc/config/rs6000/rs6000.h 2006-11-18 01:25:49.000000000 +0100 ++++ gcc-4.1.2/gcc/config/rs6000/rs6000.h 2007-10-18 15:32:51.000000000 +0200 +@@ -111,6 +111,8 @@ + %{mcpu=970: -mpower4 -maltivec} \ + %{mcpu=G5: -mpower4 -maltivec} \ + %{mcpu=8540: -me500} \ ++%{mcpu=e300c2: -mppc} \ ++%{mcpu=e300c3: -mppc -mpmr} \ + %{maltivec: -maltivec} \ + -many" + +@@ -211,6 +213,8 @@ + PROCESSOR_PPC7400, + PROCESSOR_PPC7450, + PROCESSOR_PPC8540, ++ PROCESSOR_PPCE300C2, ++ PROCESSOR_PPCE300C3, + PROCESSOR_POWER4, + PROCESSOR_POWER5 + }; +Index: gcc-4.1.2/gcc/config/rs6000/rs6000.md +=================================================================== +--- gcc-4.1.2.orig/gcc/config/rs6000/rs6000.md 2006-12-16 20:24:56.000000000 +0100 ++++ gcc-4.1.2/gcc/config/rs6000/rs6000.md 2007-10-18 15:32:51.000000000 +0200 +@@ -103,7 +103,7 @@ + ;; Processor type -- this attribute must exactly match the processor_type + ;; enumeration in rs6000.h. + +-(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5" ++(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,power4,power5" + (const (symbol_ref "rs6000_cpu_attr"))) + + (automata_option "ndfa") +@@ -119,6 +119,7 @@ + (include "7xx.md") + (include "7450.md") + (include "8540.md") ++(include "e300c2c3.md") + (include "power4.md") + (include "power5.md") + +Index: gcc-4.1.2/gcc/config.gcc +=================================================================== +--- gcc-4.1.2.orig/gcc/config.gcc 2007-10-18 15:26:23.000000000 +0200 ++++ gcc-4.1.2/gcc/config.gcc 2007-10-18 15:32:51.000000000 +0200 +@@ -2710,7 +2710,7 @@ + | rios | rios1 | rios2 | rsc | rsc1 | rs64a \ + | 401 | 403 | 405 | 405fp | 440 | 440fp | 505 \ + | 601 | 602 | 603 | 603e | ec603e | 604 \ +- | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \ ++ | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 | e300c[23] \ + | 854[08] | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5) + # OK + ;; diff --git a/packages/gcc/gcc-cross_4.2.2.bb b/packages/gcc/gcc-cross_4.2.2.bb index 3984147eae..fdb6d0e30d 100644 --- a/packages/gcc/gcc-cross_4.2.2.bb +++ b/packages/gcc/gcc-cross_4.2.2.bb @@ -5,7 +5,7 @@ inherit cross FILESDIR = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/gcc-${PV}" # NOTE: split PR. If the main .oe changes something that affects its *build* # remember to increment this one too. -PR = "r2" +PR = "r3" DEPENDS = "virtual/${TARGET_PREFIX}binutils virtual/${TARGET_PREFIX}libc-for-gcc gmp-native mpfr-native" PROVIDES = "virtual/${TARGET_PREFIX}gcc virtual/${TARGET_PREFIX}g++" diff --git a/packages/gcc/gcc_4.2.2.bb b/packages/gcc/gcc_4.2.2.bb index de3b65ce7f..91f4691208 100644 --- a/packages/gcc/gcc_4.2.2.bb +++ b/packages/gcc/gcc_4.2.2.bb @@ -1,4 +1,4 @@ -PR = "r2" +PR = "r3" DESCRIPTION = "The GNU cc and gcc C compilers." HOMEPAGE = "http://www.gnu.org/software/gcc/" SECTION = "devel" @@ -39,6 +39,7 @@ SRC_URI = "ftp://ftp.gnu.org/pub/gnu/gcc/gcc-${PV}/gcc-${PV}.tar.bz2 \ file://fix-ICE-in-arm_unwind_emit_set.diff;patch=1 \ file://cache-amnesia.patch;patch=1 \ file://gfortran.patch;patch=1 \ + file://gcc-4.0.2-e300c2c3.patch;patch=1 \ file://pr34130.patch;patch=1 \ " -- cgit v1.2.3