From ca12f35c0611eab719c9e4cee282eccd928d5963 Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Thu, 12 Mar 2009 11:13:10 -0300 Subject: u-boot 1.2.0: add support for dm355-leopard --- packages/u-boot/u-boot-1.2.0/dm355-leopard.diff | 48455 ++++++++++++++++++++++ packages/u-boot/u-boot_1.2.0.bb | 2 + 2 files changed, 48457 insertions(+) create mode 100644 packages/u-boot/u-boot-1.2.0/dm355-leopard.diff diff --git a/packages/u-boot/u-boot-1.2.0/dm355-leopard.diff b/packages/u-boot/u-boot-1.2.0/dm355-leopard.diff new file mode 100644 index 0000000000..b614522f42 --- /dev/null +++ b/packages/u-boot/u-boot-1.2.0/dm355-leopard.diff @@ -0,0 +1,48455 @@ + Makefile | 36 + board/davinci/Makefile | 47 + board/davinci/config.mk | 27 + board/davinci/davinci.c | 417 + + board/davinci/dm644x_emac.c | 491 + + board/davinci/dm644x_emac.h | 290 + board/davinci/flash.c | 686 + + board/davinci/flash_params.h | 319 + board/davinci/lowlevel_init.S | 764 ++ + board/davinci/nand.c | 111 + board/davinci/soc.h | 339 + board/davinci/timer.c | 73 + board/davinci/timer.h | 51 + board/davinci/types.h | 46 + board/davinci/u-boot.lds | 52 + board/dm355_evm/Makefile | 47 + board/dm355_evm/config.mk | 25 + board/dm355_evm/dm355_evm.c | 598 + + board/dm355_evm/flash.c | 758 ++ + board/dm355_evm/flash_params.h | 319 + board/dm355_evm/lowlevel_init.S | 766 ++ + board/dm355_evm/nand.c | 805 ++ + board/dm355_evm/timer.c | 72 + board/dm355_evm/timer.h | 51 + board/dm355_evm/types.h | 46 + board/dm355_evm/u-boot.lds | 52 + board/dm355_ipnc/Makefile | 47 + board/dm355_ipnc/config.mk | 25 + board/dm355_ipnc/dm355_ipnc.c | 671 + + board/dm355_ipnc/flash.c | 758 ++ + board/dm355_ipnc/flash_params.h | 319 + board/dm355_ipnc/lowlevel_init.S | 766 ++ + board/dm355_ipnc/nand.c | 830 ++ + board/dm355_ipnc/timer.c | 72 + board/dm355_ipnc/timer.h | 51 + board/dm355_ipnc/types.h | 46 + board/dm355_ipnc/u-boot.lds | 52 + board/dm355_leopard/Makefile | 47 + board/dm355_leopard/config.mk | 25 + board/dm355_leopard/dm355_leopard.c | 671 + + board/dm355_leopard/flash.c | 758 ++ + board/dm355_leopard/flash_params.h | 319 + board/dm355_leopard/lowlevel_init.S | 766 ++ + board/dm355_leopard/nand.c | 830 ++ + board/dm355_leopard/timer.c | 72 + board/dm355_leopard/timer.h | 51 + board/dm355_leopard/types.h | 46 + board/dm355_leopard/u-boot.lds | 52 + board/dm700/Makefile | 47 + board/dm700/config.mk | 26 + board/dm700/davinci_hd.c | 203 + board/dm700/dm646x_emac.c | 506 + + board/dm700/dm646x_emac.h | 321 + board/dm700/flash.c | 686 + + board/dm700/flash_params.h | 319 + board/dm700/lowlevel_init.S | 725 ++ + board/dm700/nand.c | 111 + board/dm700/soc.h | 349 + + board/dm700/timer.c | 73 + board/dm700/timer.h | 51 + board/dm700/types.h | 46 + board/dm700/u-boot.lds | 52 + common/cmd_nand.c | 11 + common/env_nand.c | 14 + cpu/arm926ejs/config.mk | 4 + cpu/arm926ejs/interrupts.c | 148 + cpu/arm926ejs/interrupts.c.orig | 191 + doc/README.SBC8560 | 57 + doc/README.sbc8560 | 53 + drivers/Makefile | 4 + drivers/davinci_i2c.c | 296 + drivers/davinci_i2c.h | 87 + drivers/dm9000.c | 370 + + drivers/dm9000.h | 181 + drivers/dm9000x.c | 124 + drivers/nand/nand_base.c | 1404 ++-- + drivers/nand/nand_bbt.c | 17 + drivers/nand/nand_ids.c | 44 + drivers/nand/nand_util.c | 3 + examples/hello_world.bin |binary + examples/hello_world.srec | 36 + include/asm-arm/arch-arm926ejs/emif_defs.h | 59 + include/asm-arm/arch-arm926ejs/nand_defs.h | 92 + include/asm-arm/arch-arm926ejs/types.h | 31 + include/asm-arm/arch/emif_defs.h | 59 + include/asm-arm/arch/nand_defs.h | 92 + include/asm-arm/arch/sizes.h | 51 + include/asm-arm/arch/types.h | 31 + include/asm-arm/proc/domain.h | 50 + include/asm-arm/proc/processor.h | 74 + include/asm-arm/proc/ptrace.h | 109 + include/asm-arm/proc/system.h | 199 + include/asm/arch-arm1136/bits.h | 48 + include/asm/arch-arm1136/clocks.h | 112 + include/asm/arch-arm1136/i2c.h | 107 + include/asm/arch-arm1136/mem.h | 156 + include/asm/arch-arm1136/mux.h | 158 + include/asm/arch-arm1136/omap2420.h | 221 + include/asm/arch-arm1136/sizes.h | 49 + include/asm/arch-arm1136/sys_info.h | 82 + include/asm/arch-arm1136/sys_proto.h | 54 + include/asm/arch-arm720t/hardware.h | 43 + include/asm/arch-arm720t/netarm_dma_module.h | 182 + include/asm/arch-arm720t/netarm_eni_module.h | 121 + include/asm/arch-arm720t/netarm_eth_module.h | 160 + include/asm/arch-arm720t/netarm_gen_module.h | 186 + include/asm/arch-arm720t/netarm_mem_module.h | 184 + include/asm/arch-arm720t/netarm_registers.h | 96 + include/asm/arch-arm720t/netarm_ser_module.h | 347 + include/asm/arch-arm720t/s3c4510b.h | 272 + include/asm/arch-arm925t/sizes.h | 50 + include/asm/arch-arm926ejs/emif_defs.h | 59 + include/asm/arch-arm926ejs/nand_defs.h | 92 + include/asm/arch-arm926ejs/sizes.h | 51 + include/asm/arch-arm926ejs/types.h | 31 + include/asm/arch-at91rm9200/AT91RM9200.h | 762 ++ + include/asm/arch-at91rm9200/hardware.h | 77 + include/asm/arch-imx/imx-regs.h | 577 + + include/asm/arch-ixp/ixp425.h | 543 + + include/asm/arch-ixp/ixp425pci.h | 312 + include/asm/arch-ks8695/platform.h | 306 + include/asm/arch-omap/sizes.h | 52 + include/asm/arch-pxa/bitfield.h | 112 + include/asm/arch-pxa/hardware.h | 158 + include/asm/arch-pxa/mmc.h | 200 + include/asm/arch-pxa/pxa-regs.h | 2399 ++++++ + include/asm/arch-s3c24x0/memory.h | 162 + include/asm/arch-s3c44b0/hardware.h | 281 + include/asm/arch-sa1100/bitfield.h | 112 + include/asm/arch/emif_defs.h | 59 + include/asm/arch/nand_defs.h | 92 + include/asm/arch/sizes.h | 51 + include/asm/arch/types.h | 31 + include/asm/atomic.h | 113 + include/asm/bitops.h | 144 + include/asm/byteorder.h | 32 + include/asm/errno.h | 138 + include/asm/global_data.h | 66 + include/asm/hardware.h | 18 + include/asm/io.h | 307 + include/asm/mach-types.h | 9415 +++++++++++++++++++++++++++ + include/asm/memory.h | 137 + include/asm/posix_types.h | 79 + include/asm/proc-armv/domain.h | 50 + include/asm/proc-armv/processor.h | 74 + include/asm/proc-armv/ptrace.h | 109 + include/asm/proc-armv/system.h | 199 + include/asm/proc/domain.h | 50 + include/asm/proc/processor.h | 74 + include/asm/proc/ptrace.h | 109 + include/asm/proc/system.h | 199 + include/asm/processor.h | 134 + include/asm/ptrace.h | 33 + include/asm/setup.h | 269 + include/asm/sizes.h | 52 + include/asm/string.h | 47 + include/asm/types.h | 50 + include/asm/u-boot-arm.h | 62 + include/asm/u-boot.h | 60 + include/config.h | 2 + include/config.mk | 3 + include/configs/SBC8560.h | 410 - + include/configs/davinci.h | 222 + include/configs/dm355_evm.h | 227 + include/configs/dm355_ipnc.h | 234 + include/configs/dm355_leopard.h | 234 + include/configs/dm700.h | 204 + include/configs/omap2420h4.h | 2 + include/configs/sbc8560.h | 408 + + include/flash.h | 2 + include/linux/mtd/nand.h | 190 + include/linux/mtd/nand_ids.h | 1 + include/version_autogenerated.h | 1 + lib_arm/board.c | 8 + tools/crc32.c | 198 + tools/environment.c | 214 + 176 files changed, 44713 insertions(+), 982 deletions(-) +diff -Nurd u-boot-1.2.0/Makefile u-boot-1.2.0-leopard/Makefile +--- u-boot-1.2.0/Makefile 2007-01-06 20:13:11.000000000 -0300 ++++ u-boot-1.2.0-leopard/Makefile 2009-03-10 02:16:35.000000000 -0300 +@@ -125,7 +125,7 @@ + CROSS_COMPILE = powerpc-linux- + endif + ifeq ($(ARCH),arm) +-CROSS_COMPILE = arm-linux- ++CROSS_COMPILE = arm_v5t_le- + endif + ifeq ($(ARCH),i386) + ifeq ($(HOSTARCH),i386) +@@ -233,10 +233,12 @@ + __OBJS := $(subst $(obj),,$(OBJS)) + __LIBS := $(subst $(obj),,$(LIBS)) + ++U-BOOT = u-boot-1.2.0-$(BOARD).bin ++ + ######################################################################### + ######################################################################### + +-ALL = $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) ++ALL = $(obj)u-boot.srec $(obj)$(U-BOOT) $(obj)System.map $(U_BOOT_NAND) + + all: $(ALL) + +@@ -249,7 +251,10 @@ + $(obj)u-boot.bin: $(obj)u-boot + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +-$(obj)u-boot.img: $(obj)u-boot.bin ++$(obj)$(U-BOOT): $(obj)u-boot ++ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ ++ ++$(obj)u-boot.img: $(obj)$(U-BOOT) + ./tools/mkimage -A $(ARCH) -T firmware -C none \ + -a $(TEXT_BASE) -e 0 \ + -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \ +@@ -277,8 +282,8 @@ + $(NAND_SPL): version + $(MAKE) -C nand_spl/board/$(BOARDDIR) all + +-$(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin +- cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin ++$(U_BOOT_NAND): $(NAND_SPL) $(obj)$(U-BOOT) ++ cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)$(U-BOOT) > $(obj)u-boot-nand.bin + + version: + @echo -n "#define U_BOOT_VERSION \"U-Boot " > $(VERSION_FILE); \ +@@ -320,7 +325,7 @@ + + ######################################################################### + else +-all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \ ++all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)$(U-BOOT) \ + $(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \ + $(SUBDIRS) version gdbtools updater env depend \ + dep tags ctags etags $(obj)System.map: +@@ -336,7 +341,7 @@ + ######################################################################### + + unconfig: +- @rm -f $(obj)include/config.h $(obj)include/config.mk \ ++ @rm -rf $(obj)include/config.h $(obj)include/config.mk \ + $(obj)board/*/config.tmp $(obj)board/*/*/config.tmp + + #======================================================================== +@@ -1858,6 +1863,21 @@ + mx1fs2_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t mx1fs2 NULL imx + ++davinci_config : unconfig ++ @$(MKCONFIG) $(@:_config=) arm arm926ejs davinci ++ ++dm700_config : unconfig ++ @$(MKCONFIG) $(@:_config=) arm arm926ejs dm700 ++ ++dm355_evm_config : unconfig ++ @$(MKCONFIG) $(@:_config=) arm arm926ejs dm355_evm ++ ++dm355_ipnc_config : unconfig ++ @$(MKCONFIG) $(@:_config=) arm arm926ejs dm355_ipnc ++ ++dm355_leopard_config: unconfig ++ @$(MKCONFIG) $(@:_config=) arm arm926ejs dm355_leopard ++ + netstar_32_config \ + netstar_config: unconfig + @mkdir -p $(obj)include +@@ -2333,7 +2353,7 @@ + rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL) + rm -f $(obj)tools/crc32.c $(obj)tools/environment.c $(obj)tools/env/crc32.c + rm -f $(obj)tools/inca-swap-bytes $(obj)cpu/mpc824x/bedbug_603e.c +- rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm ++ rm -rf $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm + [ ! -d $(OBJTREE)/nand_spl ] || find $(obj)nand_spl -lname "*" -print | xargs rm -f + + ifeq ($(OBJTREE),$(SRCTREE)) +diff -Nurd u-boot-1.2.0/board/davinci/Makefile u-boot-1.2.0-leopard/board/davinci/Makefile +--- u-boot-1.2.0/board/davinci/Makefile 1969-12-31 21:00:00.000000000 -0300 ++++ u-boot-1.2.0-leopard/board/davinci/Makefile 2007-12-04 07:50:28.000000000 -0300 +@@ -0,0 +1,47 @@ ++# ++# (C) Copyright 2000, 2001, 2002 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = lib$(BOARD).a ++ ++OBJS := davinci.o flash.o timer.o dm644x_emac.o nand.o ++SOBJS := lowlevel_init.o ++ ++$(LIB): $(OBJS) $(SOBJS) ++ $(AR) crv $@ $^ ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak .depend ++ ++######################################################################### ++ ++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) ++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ ++ ++-include .depend ++ ++######################################################################### +diff -Nurd u-boot-1.2.0/board/davinci/config.mk u-boot-1.2.0-leopard/board/davinci/config.mk +--- u-boot-1.2.0/board/davinci/config.mk 1969-12-31 21:00:00.000000000 -0300 ++++ u-boot-1.2.0-leopard/board/davinci/config.mk 2007-12-04 07:50:28.000000000 -0300 +@@ -0,0 +1,27 @@ ++# ++# (C) Copyright 2002 ++# Gary Jennejohn, DENX Software Engineering, ++# David Mueller, ELSOFT AG, ++# ++# (C) Copyright 2003 ++# Texas Instruments, ++# Swaminathan ++# ++# Davinci EVM board (ARM925EJS) cpu ++# see http://www.ti.com/ for more information on Texas Instruments ++# ++# Davinci EVM has 1 bank of 256 MB DDR RAM ++# Physical Address: ++# 8000'0000 to 9000'0000 ++# ++# ++# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 ++# (mem base + reserved) ++# ++# we load ourself to 8100 '0000 ++# ++# ++ ++#Provide a atleast 16MB spacing between us and the Linux Kernel image ++TEXT_BASE = 0x81080000 ++BOARDLIBS = drivers/nand/libnand.a +diff -Nurd u-boot-1.2.0/board/davinci/davinci.c u-boot-1.2.0-leopard/board/davinci/davinci.c +--- u-boot-1.2.0/board/davinci/davinci.c 1969-12-31 21:00:00.000000000 -0300 ++++ u-boot-1.2.0-leopard/board/davinci/davinci.c 2007-12-04 07:50:28.000000000 -0300 +@@ -0,0 +1,417 @@ ++/* ++ * ++ * Copyright (C) 2004 Texas Instruments. ++ * ++ * ---------------------------------------------------------------------------- ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ---------------------------------------------------------------------------- ++ Modifications: ++ ver. 1.0: Oct 2005, Swaminathan S ++ * ++ */ ++ ++#include ++#include ++ ++#if 0 ++void flash__init (void); ++void ether__init (void); ++#endif ++#define PLL1_PLLM *(volatile unsigned int *)0x01c40910 ++#define PLL2_PLLM *(volatile unsigned int *)0x01c40D10 ++#define PLL2_DIV2 *(volatile unsigned char *)0x01c40D1C ++ ++void davinci_psc_all_enable(void); ++ ++/******************************************* ++ Routine: delay ++ Description: Delay function ++*******************************************/ ++static inline void delay (unsigned long loops) ++{ ++ __asm__ volatile ("1:\n" ++ "subs %0, %1, #1\n" ++ "bne 1b":"=r" (loops):"0" (loops)); ++} ++ ++/******************************************* ++ Routine: board_init ++ Description: Board Initialization routine ++*******************************************/ ++int board_init (void) ++{ ++ DECLARE_GLOBAL_DATA_PTR; ++ ++ /* arch number of DaVinci DVDP-Board */ ++ gd->bd->bi_arch_number = 901; ++ ++ /* adress of boot parameters */ ++ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; ++ /* Configure MUX settings */ ++ ++ /* Power on required peripherals */ ++ davinci_psc_all_enable(); ++#if 0 ++ /* this speeds up your boot a quite a bit. However to make it ++ * work, you need make sure your kernel startup flush bug is fixed. ++ * ... rkw ... ++ */ ++ icache_enable (); ++#endif ++ inittimer (); ++ ++ return 0; ++} ++ ++/* PSC Domains */ ++#define LPSC_VPSSMSTR 0 // VPSS Master LPSC ++#define LPSC_VPSSSLV 1 // VPSS Slave LPSC ++#define LPSC_TPCC 2 // TPCC LPSC ++#define LPSC_TPTC0 3 // TPTC0 LPSC ++#define LPSC_TPTC1 4 // TPTC1 LPSC ++#define LPSC_EMAC 5 // EMAC LPSC ++#define LPSC_EMAC_WRAPPER 6 // EMAC WRAPPER LPSC ++#define LPSC_MDIO 7 // MDIO LPSC ++#define LPSC_IEEE1394 8 // IEEE1394 LPSC ++#define LPSC_USB 9 // USB LPSC ++#define LPSC_ATA 10 // ATA LPSC ++#define LPSC_VLYNQ 11 // VLYNQ LPSC ++#define LPSC_UHPI 12 // UHPI LPSC ++#define LPSC_DDR_EMIF 13 // DDR_EMIF LPSC ++#define LPSC_AEMIF 14 // AEMIF LPSC ++#define LPSC_MMC_SD 15 // MMC_SD LPSC ++#define LPSC_MEMSTICK 16 // MEMSTICK LPSC ++#define LPSC_McBSP 17 // McBSP LPSC ++#define LPSC_I2C 18 // I2C LPSC ++#define LPSC_UART0 19 // UART0 LPSC ++#define LPSC_UART1 20 // UART1 LPSC ++#define LPSC_UART2 21 // UART2 LPSC ++#define LPSC_SPI 22 // SPI LPSC ++#define LPSC_PWM0 23 // PWM0 LPSC ++#define LPSC_PWM1 24 // PWM1 LPSC ++#define LPSC_PWM2 25 // PWM2 LPSC ++#define LPSC_GPIO 26 // GPIO LPSC ++#define LPSC_TIMER0 27 // TIMER0 LPSC ++#define LPSC_TIMER1 28 // TIMER1 LPSC ++#define LPSC_TIMER2 29 // TIMER2 LPSC ++#define LPSC_SYSTEM_SUBSYS 30 // SYSTEM SUBSYSTEM LPSC ++#define LPSC_ARM 31 // ARM LPSC ++#define LPSC_SCR2 32 // SCR2 LPSC ++#define LPSC_SCR3 33 // SCR3 LPSC ++#define LPSC_SCR4 34 // SCR4 LPSC ++#define LPSC_CROSSBAR 35 // CROSSBAR LPSC ++#define LPSC_CFG27 36 // CFG27 LPSC ++#define LPSC_CFG3 37 // CFG3 LPSC ++#define LPSC_CFG5 38 // CFG5 LPSC ++#define LPSC_GEM 39 // GEM LPSC ++#define LPSC_IMCOP 40 // IMCOP LPSC ++ ++#define CHP_SHRTSW *( volatile unsigned int* )( 0x01C40038 ) ++#define GBLCTL *( volatile unsigned int* )( 0x01C41010 ) ++#define EPCPR *( volatile unsigned int* )( 0x01C41070 ) ++#define EPCCR *( volatile unsigned int* )( 0x01C41078 ) ++#define PTCMD *( volatile unsigned int* )( 0x01C41120 ) ++#define PTSTAT *( volatile unsigned int* )( 0x01C41128 ) ++#define PDSTAT *( volatile unsigned int* )( 0x01C41200 ) ++#define PDSTAT1 *( volatile unsigned int* )( 0x01C41204 ) ++#define PDCTL *( volatile unsigned int* )( 0x01C41300 ) ++#define PDCTL1 *( volatile unsigned int* )( 0x01C41304 ) ++#define VBPR *( volatile unsigned int* )( 0x20000020 ) ++ ++/************************************** ++ Routine: board_setup_psc_on ++ Description: Enable a PSC domain ++**************************************/ ++void board_setup_psc_on( unsigned int domain, unsigned int id ) ++{ ++ volatile unsigned int* mdstat = ( unsigned int* )( 0x01C41800 + 4 * id ); ++ volatile unsigned int* mdctl = ( unsigned int* )( 0x01C41A00 + 4 * id ); ++ ++ *mdctl |= 0x00000003; // Set PowerDomain to turn on ++ ++ if ( ( PDSTAT & 0x00000001 ) == 0 ) ++ { ++ PDCTL1 |= 0x1; ++ PTCMD = ( 1 << domain ); ++ while ( ( ( ( EPCPR >> domain ) & 1 ) == 0 ) ); ++ ++ PDCTL1 |= 0x100 ; ++ while( ! ( ( ( PTSTAT >> domain ) & 1 ) == 0 ) ); ++ } ++ else ++ { ++ PTCMD = ( 1<> domain ) & 1 ) == 0 ) ); ++ } ++ ++ while( ! ( ( *mdstat & 0x0000001F ) == 0x3 ) ); ++} ++ ++/************************************** ++ Routine: davinci_psc_all_enable ++ Description: Enable all PSC domains ++**************************************/ ++void davinci_psc_all_enable(void) ++{ ++#define PSC_ADDR 0x01C41000 ++#define PTCMD (PSC_ADDR+0x120) ++#define PTSTAT (PSC_ADDR+0x128) ++ ++ unsigned int alwaysOnPdNum = 0, dspPdNum = 1, i; ++ int waiting; ++ unsigned int state; ++ ++ /* This function turns on all clocks in the ALWAYSON and DSP Power ++ * Domains. Note this function assumes that the Power Domains are ++ * already on. ++ */ ++#if 0 ++ /* Write ENABLE (0x3) to all 41 MDCTL[i].NEXT bit fields. */ ++ for( i = 0; i < 41; i++){ ++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*i) = ++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*i) | 0x3; ++ } ++ ++ /* For special workaround: Set MDCTL[i].EMURSTIE to 0x1 for all of the ++ * following Modules. VPSSSLV, EMAC, EMACCTRL, MDIO, USB, ATA, VLYNQ, ++ * HPI, DDREMIF, AEMIF, MMCSD, MEMSTICK, ASP, GPIO, IMCOP. ++ */ ++ /**(unsigned int*) (PSC_ADDR+0xA00+4*1) = *(unsigned int*) (PSC_ADDR+0xA00+4*1) | 0x203;*/ ++ *(unsigned int*) (PSC_ADDR+0xA00+4*5) = *(unsigned int*) (PSC_ADDR+0xA00+4*5) | 0x203; ++ *(unsigned int*) (PSC_ADDR+0xA00+4*6) = *(unsigned int*) (PSC_ADDR+0xA00+4*6) | 0x203; ++ *(unsigned int*) (PSC_ADDR+0xA00+4*7) = *(unsigned int*) (PSC_ADDR+0xA00+4*7) | 0x203; ++ /**(unsigned int*) (PSC_ADDR+0xA00+4*9) = *(unsigned int*) (PSC_ADDR+0xA00+4*9) | 0x203; ++ *(unsigned int*) (PSC_ADDR+0xA00+4*10) = *(unsigned int*) (PSC_ADDR+0xA00+4*10) | 0x203; ++ *(unsigned int*) (PSC_ADDR+0xA00+4*11) = *(unsigned int*) (PSC_ADDR+0xA00+4*11) | 0x203; ++ *(unsigned int*) (PSC_ADDR+0xA00+4*12) = *(unsigned int*) (PSC_ADDR+0xA00+4*12) | 0x203;*/ ++ *(unsigned int*) (PSC_ADDR+0xA00+4*13) = *(unsigned int*) (PSC_ADDR+0xA00+4*13) | 0x203; ++ *(unsigned int*) (PSC_ADDR+0xA00+4*14) = *(unsigned int*) (PSC_ADDR+0xA00+4*14) | 0x203; ++ /**(unsigned int*) (PSC_ADDR+0xA00+4*15) = *(unsigned int*) (PSC_ADDR+0xA00+4*15) | 0x203; ++ *(unsigned int*) (PSC_ADDR+0xA00+4*16) = *(unsigned int*) (PSC_ADDR+0xA00+4*16) | 0x203; ++ *(unsigned int*) (PSC_ADDR+0xA00+4*17) = *(unsigned int*) (PSC_ADDR+0xA00+4*17) | 0x203;*/ ++ *(unsigned int*) (PSC_ADDR+0xA00+4*19) = *(unsigned int*) (PSC_ADDR+0xA00+4*19) | 0x203; ++ /**(unsigned int*) (PSC_ADDR+0xA00+4*26) = *(unsigned int*) (PSC_ADDR+0xA00+4*26) | 0x203; ++ *(unsigned int*) (PSC_ADDR+0xA00+4*40) = *(unsigned int*) (PSC_ADDR+0xA00+4*40) | 0x203;*/ ++#endif ++ ++ /* For special workaround: Clear MDCTL[i].EMURSTIE to 0x0 for all of the following Modules. ++ * VPSSSLV, EMAC, EMACCTRL, MDIO, USB, ATA, VLYNQ, ++ * HPI, DDREMIF, AEMIF, MMCSD, MEMSTICK, ASP, GPIO, IMCOP. ++ */ ++ /**(unsigned int*) (PSC_ADDR+0xA00+4*1) = *(unsigned int*) (PSC_ADDR+0xA00+4*1) & 0x003;*/ ++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*5) = *(unsigned int*) (PSC_ADDR+0xA00+4*5) | 0x003; ++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*6) = *(unsigned int*) (PSC_ADDR+0xA00+4*6) | 0x003; ++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*7) = *(unsigned int*) (PSC_ADDR+0xA00+4*7) | 0x003; ++ /**(unsigned int*) (PSC_ADDR+0xA00+4*9) = *(unsigned int*) (PSC_ADDR+0xA00+4*9) & 0x003; ++ *(unsigned int*) (PSC_ADDR+0xA00+4*10) = *(unsigned int*) (PSC_ADDR+0xA00+4*10) & 0x003; ++ *(unsigned int*) (PSC_ADDR+0xA00+4*11) = *(unsigned int*) (PSC_ADDR+0xA00+4*11) & 0x003; ++ *(unsigned int*) (PSC_ADDR+0xA00+4*12) = *(unsigned int*) (PSC_ADDR+0xA00+4*12) & 0x003;*/ ++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*13) = *(unsigned int*) (PSC_ADDR+0xA00+4*13) | 0x003; ++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*14) = *(unsigned int*) (PSC_ADDR+0xA00+4*14) | 0x003; ++ /**(unsigned int*) (PSC_ADDR+0xA00+4*15) = *(unsigned int*) (PSC_ADDR+0xA00+4*15) & 0x003; ++ *(unsigned int*) (PSC_ADDR+0xA00+4*16) = *(unsigned int*) (PSC_ADDR+0xA00+4*16) & 0x003; ++ *(unsigned int*) (PSC_ADDR+0xA00+4*17) = *(unsigned int*) (PSC_ADDR+0xA00+4*17) & 0x003;*/ ++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*19) = *(unsigned int*) (PSC_ADDR+0xA00+4*19) | 0x003; ++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*18) = *(unsigned int*) (PSC_ADDR+0xA00+4*18) | 0x003; ++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*28) = *(unsigned int*) (PSC_ADDR+0xA00+4*28) | 0x003; ++ /**(unsigned int*) (PSC_ADDR+0xA00+4*26) = *(unsigned int*) (PSC_ADDR+0xA00+4*26) & 0x003; ++ *(unsigned int*) (PSC_ADDR+0xA00+4*40) = *(unsigned int*) (PSC_ADDR+0xA00+4*40) & 0x003;*/ ++ ++ /* Set PTCMD.GO0 to 0x1 to initiate the state transtion for Modules in ++ * the ALWAYSON Power Domain ++ */ ++ *(volatile unsigned int*) PTCMD = (1<> alwaysOnPdNum) & 0x00000001) == 0)); ++ ++ /* DO GEM AND IMCOP INITIALIZATION, ONLY IF DSP POWER DOMAIN IS OFF... */ ++ /* NOTE: this is a precise and refined sequence - use extreme care if modifying! */ ++ if ((PDSTAT1 & 0x1F) == 0) { ++ ++ /* set PSC FORCE mode; may not be necessary, added per reference code */ ++ GBLCTL = GBLCTL | 0x01; ++ ++ /* set DSP power domain next state to ON */ ++ PDCTL1 = PDCTL1 | 0x01; ++ ++ /* ensure external power indicator is cleared */ ++ PDCTL1 = PDCTL1 & 0xFFFFFEFF; ++ ++ /* enable DSP module */ ++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*LPSC_GEM) = ++ (*(volatile unsigned int*) (PSC_ADDR+0xA00+4*LPSC_GEM) & 0xFFFFFFE0) | 0x3; ++ ++ /* hold DSP in reset on next power ON */ ++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*LPSC_GEM) = ++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*LPSC_GEM) & 0xFFFFFEFF; ++ ++ /* set IMCOP to enable state */ ++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*LPSC_IMCOP) = ++ (*(volatile unsigned int*) (PSC_ADDR+0xA00+4*LPSC_IMCOP) & 0xFFFFFFE0) | 0x3; ++ ++ /* hold IMCOP in reset on next power ON */ ++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*LPSC_IMCOP) = ++ *(volatile unsigned int*) (PSC_ADDR+0xA00+4*LPSC_IMCOP) & 0xFFFFFEFF; ++ ++ /* start power state transitions for DSP power domain */ ++ *(volatile unsigned int*) PTCMD = (1<> dspPdNum) & 0x00000001) == 1) { ++ waiting = 0; ++ } ++ } ++ ++ /* close rail shorting switch */ ++ CHP_SHRTSW = 0x1; ++ ++ /* set external power good indicator */ ++ PDCTL1 = PDCTL1 | 0x0100; ++ ++ /* clear external power control pending register bit */ ++ EPCCR = (1 << dspPdNum); ++ ++ /* wait for DSP domain transitions to complete */ ++ for (i = 0, waiting = 1; (i < 100) && waiting; i++) { ++ state = *(volatile unsigned int*) PTSTAT; ++ if (((state >> dspPdNum) & 0x00000001) == 0) { ++ waiting = 0; ++ } ++ } ++ ++ /* turn off PSC FORCE mode */ ++ GBLCTL = GBLCTL & 0xFFFFFFFE; ++ ++ } /* END GEM AND IMCOP INITIALIZATION */ ++ ++ /* Bringup UART out of reset here since NS16650 code that we are using from uBoot ++ * will not do it ++ */ ++#define UARTPWREMU_MGMT 0x01c20030 ++ *(volatile unsigned int*) UARTPWREMU_MGMT = 0x0000E003; ++ ++ /* Enable GIO3.3V cells used for EMAC */ ++#define VDD3P3V_PWDN 0x01c40048 ++ *(volatile unsigned int*) VDD3P3V_PWDN = 0; ++ ++#define PINMUX0 0x01C40000 ++#define PINMUX4 0x01C40004 ++ ++ /* Enable UART0 MUX lines */ ++ *(volatile unsigned int *)PINMUX4 |= 1; ++ /* Enable EMAC and AEMIF pins */ ++#if (CONFIG_COMMANDS & CFG_CMD_NAND) ++ *(volatile unsigned int*) PINMUX0 = 0x80000000; ++#else ++ *(volatile unsigned int*) PINMUX0 = 0x80000C1F; ++#endif ++ ++ /* Enable I2C pin Mux */ ++ *(volatile unsigned int *)PINMUX4 |= (1 << 7); ++ ++ /* Set the Bus Priority Register to appropriate value */ ++ VBPR = 0x20; ++} ++ ++/****************************** ++ Routine: misc_init_r ++ Description: Misc. init ++******************************/ ++int misc_init_r (void) ++{ ++ char temp[20]; ++ char rtcdata[10] = { 2, 1, 0, 0, 0, 0, 0, 0, 0, 0}; ++ char emac_read_addr [10] = { 0x7f, 0 }, i= 0; ++ int clk = 0; ++ ++ clk = ((PLL2_PLLM + 1) * 27) / (PLL2_DIV2 + 1); ++ ++ printf ("ARM Clock :- %dMHz\n", ((((PLL1_PLLM + 1) * 27 ) / 2)) ); ++ printf ("DDR Clock :- %dMHz\n", (clk/2)); ++ ++ i2c_write (0x50, 0x00, 1, emac_read_addr, 2); ++ i2c_read (0x50, 0x00, 1, emac_read_addr, 6); ++ temp[0] = (emac_read_addr[0] & 0xF0) >> 4; ++ temp[1] = (emac_read_addr[0] & 0x0F); ++ temp[2] = ':'; ++ temp[3] = (emac_read_addr[1] & 0xF0) >> 4; ++ temp[4] = (emac_read_addr[1] & 0x0F); ++ temp[5] = ':'; ++ temp[6] = (emac_read_addr[2] & 0xF0) >> 4; ++ temp[7] = (emac_read_addr[2] & 0x0F); ++ temp[8] = ':'; ++ temp[9] = (emac_read_addr[3] & 0xF0) >> 4; ++ temp[10]= (emac_read_addr[3] & 0x0F); ++ temp[11]= ':'; ++ temp[12]= (emac_read_addr[4] & 0xF0) >> 4; ++ temp[13]= (emac_read_addr[4] & 0x0F); ++ temp[14]= ':'; ++ temp[15]= (emac_read_addr[5] & 0xF0) >> 4; ++ temp[16]= (emac_read_addr[5] & 0x0F); ++ ++ for (i = 0; i < 17; i++) ++ { ++ if (temp[i] == ':') ++ continue; ++ else if (temp[i] >= 0 && temp[i] <= 9) ++ temp[i] = temp[i] + 48; ++ else ++ temp[i] = temp[i] + 87; ++ } ++ ++ temp [17] = 0; ++ if ((emac_read_addr [0] != 0xFF) || ++ (emac_read_addr [1] != 0xFF) || ++ (emac_read_addr [2] != 0xFF) || ++ (emac_read_addr [3] != 0xFF) || ++ (emac_read_addr [4] != 0xFF) || ++ (emac_read_addr [5] != 0xFF)) ++ { ++ setenv ("ethaddr", temp); ++ } ++ ++ i2c_read (0x39, 0x00, 1, &i, 1); ++ ++ if ( !getenv("videostd") ) ++ setenv ("videostd", ((i & 0x80)?"pal":"ntsc")); ++ ++ i2c_write (0x23, 0x00, 1, rtcdata, 2); ++ i2c_read (0x23, 0x00, 1, rtcdata, 1); ++ ++ if (rtcdata[0] == 10) ++ printf ("MSP430 Firmware supports AM/PM Feature\n"); ++ else ++ printf ("MSP430 Firmware does not support AM/PM Feature\n"); ++ ++ return (0); ++} ++ ++/****************************** ++ Routine: dram_init ++ Description: Memory Info ++******************************/ ++int dram_init (void) ++{ ++ DECLARE_GLOBAL_DATA_PTR; ++ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; ++ ++ return 0; ++} ++ +diff -Nurd u-boot-1.2.0/board/davinci/dm644x_emac.c u-boot-1.2.0-leopard/board/davinci/dm644x_emac.c +--- u-boot-1.2.0/board/davinci/dm644x_emac.c 1969-12-31 21:00:00.000000000 -0300 ++++ u-boot-1.2.0-leopard/board/davinci/dm644x_emac.c 2007-12-04 07:50:28.000000000 -0300 +@@ -0,0 +1,491 @@ ++/* ++ * dm644x_emac.c ++ * ++ * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM ++ * ++ * Copyright (C) 2005 Texas Instruments. ++ * ++ * ---------------------------------------------------------------------------- ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ---------------------------------------------------------------------------- ++ ++ * Modifications: ++ * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot. ++ * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors ++ * ++ */ ++ ++#include ++#include ++#include ++#include "dm644x_emac.h" ++ ++#ifdef CONFIG_DRIVER_TI_EMAC ++ ++#if (CONFIG_COMMANDS & CFG_CMD_NET) ++ ++unsigned int emac_dbg = 0; ++#define debug_emac(fmt,args...) if (emac_dbg) printf (fmt ,##args) ++ ++/* EMAC internal functions - called when eth_xxx functions are invoked by the kernel */ ++static int emac_hw_init (void); ++static int emac_open (void); ++static int emac_close (void); ++static int emac_send_packet (volatile void *packet, int length); ++static int emac_rcv_packet (void); ++ ++/* The driver can be entered at any of the following entry points */ ++extern int eth_init (bd_t * bd); ++extern void eth_halt (void); ++extern int eth_rx (void); ++extern int eth_send (volatile void *packet, int length); ++ ++int eth_hw_init (void) ++{ ++ return emac_hw_init(); ++} ++ ++int eth_init (bd_t * bd) ++{ ++ return emac_open (); ++} ++ ++void eth_halt () ++{ ++ emac_close (); ++} ++ ++int eth_send (volatile void *packet, int length) ++{ ++ return emac_send_packet (packet, length); ++} ++ ++int eth_rx () ++{ ++ return emac_rcv_packet (); ++} ++ ++ ++static char emac_mac_addr[] = { 0x00, 0x00, 0x5b, 0xee, 0xde, 0xad }; ++ ++/* ++ * This function must be called before emac_open() if you want to override ++ * the default mac address. ++ */ ++ ++void emac_set_mac_addr (const char *addr) ++{ ++ int i; ++ ++ for (i = 0; i < sizeof (emac_mac_addr); i++) { ++ emac_mac_addr[i] = addr[i]; ++ } ++} ++ ++/*************************** ++ * EMAC Global variables ++ ***************************/ ++ ++/* EMAC Addresses */ ++static volatile emac_regs* adap_emac = (emac_regs *) EMAC_BASE_ADDR; ++static volatile ewrap_regs* adap_ewrap = (ewrap_regs *) EMAC_WRAPPER_BASE_ADDR; ++static volatile mdio_regs* adap_mdio = (mdio_regs *) EMAC_MDIO_BASE_ADDR; ++ ++/* EMAC descriptors */ ++static volatile emac_desc *emac_rx_desc = (emac_desc *) (EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE); ++static volatile emac_desc *emac_tx_desc = (emac_desc *) (EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); ++static volatile emac_desc *emac_rx_active_head = 0; ++static volatile emac_desc *emac_rx_active_tail = 0; ++static int emac_rx_queue_active = 0; ++ ++/* EMAC link status */ ++static int emac_link_status = 0; /* 0 = link down, 1 = link up */ ++ ++/* Receive packet buffers */ ++static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; ++ ++/* This function initializes the emac hardware */ ++static int emac_hw_init (void) ++{ ++ /* Enabling power and reset from outside the module is required */ ++ return (0); ++} ++ ++/* Read a PHY register via MDIO inteface */ ++static int mdio_read(int phy_addr, int reg_num) ++{ ++ adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ | ++ ((reg_num & 0x1F) << 21) | ++ ((phy_addr & 0x1F) << 16); ++ ++ /* Wait for command to complete */ ++ while ((adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) != 0); ++ ++ return (adap_mdio->USERACCESS0 & 0xFFFF); ++} ++ ++/* Write to a PHY register via MDIO inteface */ ++void mdio_write(int phy_addr, int reg_num, unsigned int data) ++{ ++ /* Wait for User access register to be ready */ ++ while ((adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) != 0); ++ ++ adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE | ++ ((reg_num & 0x1F) << 21) | ++ ((phy_addr & 0x1F) << 16) | ++ (data & 0xFFFF); ++} ++ ++ ++/* Get PHY link state - this function accepts a PHY mask for the caller to ++ * find out if any of the passed PHY addresses is connected ++ */ ++int mdio_get_link_state(unsigned int phy_mask) ++{ ++ unsigned int act_phy, phy_addr = 0, link_state = 0; ++ unsigned int config; ++ ++ act_phy = (adap_mdio->ALIVE & phy_mask); ++ ++ if (act_phy) ++ { ++ /* find the phy number */ ++ while(act_phy) ++ { ++ while(!(act_phy & 0x1)) ++ { ++ phy_addr++; ++ act_phy >>= 1; ++ } ++ /* Read the status register from PHY */ ++ link_state = ((mdio_read(phy_addr, MII_STATUS_REG) & 0x4) >> 2); ++ if(link_state == 1) ++ { ++ /* The link can break off anytime, hence adding the fix for boosting the PHY signal ++ * strength here so that everytime the link is found, this can be done and ensured ++ * that we dont miss it ++ */ ++ config = mdio_read(phy_addr, MII_DIGITAL_CONFIG_REG); ++ config |= 0x800; ++ mdio_write(phy_addr, MII_DIGITAL_CONFIG_REG, config); ++ /* Read back to verify */ ++ config = mdio_read(phy_addr, MII_DIGITAL_CONFIG_REG); ++ ++ break; ++ } ++ else ++ { ++ /* If no link, go to next phy. */ ++ act_phy >>= 1; ++ phy_addr++; ++ } ++ } ++ } ++ return link_state; ++} ++ ++/* ++ * The kernel calls this function when someone wants to use the device, ++ * typically 'ifconfig ethX up'. ++ */ ++static int emac_open (void) ++{ ++ volatile unsigned int *addr; ++ unsigned int clkdiv, cnt; ++ volatile emac_desc *rx_desc; ++ ++ debug_emac("+ emac_open\n"); ++ ++ /* Reset EMAC module and disable interrupts in wrapper */ ++ adap_emac->SOFTRESET = 1; ++ while (adap_emac->SOFTRESET != 0); ++ adap_ewrap->EWCTL = 0; ++ for (cnt=0; cnt < 5; cnt++) { ++ clkdiv = adap_ewrap->EWCTL; ++ } ++ ++ rx_desc = emac_rx_desc; ++ ++ adap_emac->TXCONTROL = 0x1; ++ adap_emac->RXCONTROL = 0x1; ++ ++ /* Set MAC Addresses & Init multicast Hash to 0 (disable any multicast receive) */ ++ /* Using channel 0 only - other channels are disabled */ ++ adap_emac->MACINDEX = 0; ++ adap_emac->MACADDRHI = (emac_mac_addr[3] << 24) | (emac_mac_addr[2] << 16) | ++ (emac_mac_addr[1] << 8) | (emac_mac_addr[0]); ++ adap_emac->MACADDRLO = ((emac_mac_addr[5] << 8) | emac_mac_addr[4]); ++ ++ adap_emac->MACHASH1 = 0; ++ adap_emac->MACHASH2 = 0; ++ ++ /* Set source MAC address - REQUIRED */ ++ adap_emac->MACSRCADDRHI = (emac_mac_addr[3] << 24) | (emac_mac_addr[2] << 16) | ++ (emac_mac_addr[1] << 8) | (emac_mac_addr[0]); ++ adap_emac->MACSRCADDRLO = ((emac_mac_addr[4] << 8) | emac_mac_addr[5]); ++ ++ /* Set DMA 8 TX / 8 RX Head pointers to 0 */ ++ addr = &adap_emac->TX0HDP; ++ for( cnt=0; cnt<16; cnt++ ) ++ *addr++ = 0; ++ addr = &adap_emac->RX0HDP; ++ for( cnt=0; cnt<16; cnt++ ) ++ *addr++ = 0; ++ ++ /* Clear Statistics (do this before setting MacControl register) */ ++ addr = &adap_emac->RXGOODFRAMES; ++ for( cnt=0; cnt < EMAC_NUM_STATS; cnt++ ) ++ *addr++ = 0; ++ ++ /* No multicast addressing */ ++ adap_emac->MACHASH1 = 0 ; ++ adap_emac->MACHASH2 = 0 ; ++ ++ /* Create RX queue and set receive process in place */ ++ emac_rx_active_head = emac_rx_desc; ++ for (cnt=0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) ++ { ++ rx_desc->next = (unsigned int) (rx_desc + 1); ++ rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)]; ++ rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; ++ rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; ++ ++rx_desc; ++ } ++ ++ /* Set the last descriptor's "next" parameter to 0 to end the RX desc list */ ++ --rx_desc; ++ rx_desc->next = 0; ++ emac_rx_active_tail = rx_desc; ++ emac_rx_queue_active = 1; ++ ++ /* Enable TX/RX */ ++ adap_emac->RXMAXLEN = EMAC_MAX_ETHERNET_PKT_SIZE; ++ adap_emac->RXBUFFEROFFSET = 0; ++ ++ /* No fancy configs - Use this for promiscous for debug - EMAC_RXMBPENABLE_RXCAFEN_ENABLE */ ++ adap_emac->RXMBPENABLE = EMAC_RXMBPENABLE_RXBROADEN ; ++ ++ /* Enable ch 0 only */ ++ adap_emac->RXUNICASTSET = 0x1; ++ ++ /* Enable MII interface and Full duplex mode */ ++ adap_emac->MACCONTROL = (EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE); ++ ++ /* Init MDIO & get link state */ ++ clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; ++ adap_mdio->CONTROL = ((clkdiv & 0xFF) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT); ++ emac_link_status = mdio_get_link_state(EMAC_MDIO_PHY_MASK); ++ ++ /* Start receive process */ ++ adap_emac->RX0HDP = (unsigned int) emac_rx_desc; ++ ++ debug_emac("- emac_open\n"); ++ ++ return (1); ++} ++ ++/* EMAC Channel Teardown */ ++void emac_ch_teardown(int ch) ++{ ++ volatile unsigned int dly = 0xFF; ++ volatile unsigned int cnt; ++ ++ debug_emac("+ emac_ch_teardown\n"); ++ ++ if (ch == EMAC_CH_TX) ++ { ++ /* Init TX channel teardown */ ++ adap_emac->TXTEARDOWN = 1; ++ for( cnt = 0; cnt != 0xFFFFFFFC; cnt = adap_emac->TX0CP){ ++ /* Wait here for Tx teardown completion interrupt to occur ++ * Note: A task delay can be called here to pend rather than ++ * occupying CPU cycles - anyway it has been found that teardown ++ * takes very few cpu cycles and does not affect functionality */ ++ --dly; ++ udelay(1); ++ if (dly == 0) break; ++ } ++ adap_emac->TX0CP = cnt; ++ adap_emac->TX0HDP = 0; ++ } ++ else ++ { ++ /* Init RX channel teardown */ ++ adap_emac->RXTEARDOWN = 1; ++ for( cnt = 0; cnt != 0xFFFFFFFC; cnt = adap_emac->RX0CP){ ++ /* Wait here for Tx teardown completion interrupt to occur ++ * Note: A task delay can be called here to pend rather than ++ * occupying CPU cycles - anyway it has been found that teardown ++ * takes very few cpu cycles and does not affect functionality */ ++ --dly; ++ udelay(1); ++ if (dly == 0) break; ++ } ++ adap_emac->RX0CP = cnt; ++ adap_emac->RX0HDP = 0; ++ } ++ ++ debug_emac("- emac_ch_teardown\n"); ++} ++ ++/* ++ * This is called by the kernel in response to 'ifconfig ethX down'. It ++ * is responsible for cleaning up everything that the open routine ++ * does, and maybe putting the card into a powerdown state. ++ */ ++static int emac_close (void) ++{ ++ debug_emac("+ emac_close\n"); ++ ++ emac_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */ ++ emac_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */ ++ ++ /* Reset EMAC module and disable interrupts in wrapper */ ++ adap_emac->SOFTRESET = 1; ++ adap_ewrap->EWCTL = 0; ++ ++ debug_emac("- emac_close\n"); ++ return (1); ++} ++ ++static int tx_send_loop = 0; ++ ++/* ++ * This function sends a single packet on the network and returns ++ * positive number (number of bytes transmitted) or negative for error ++ */ ++static int emac_send_packet (volatile void *packet, int length) ++{ ++ int ret_status = -1; ++ tx_send_loop = 0; ++ ++ /* Return error if no link */ ++ emac_link_status = mdio_get_link_state(EMAC_MDIO_PHY_MASK); ++ if (emac_link_status == 0) ++ { ++ printf("WARN: emac_send_packet: No link\n"); ++ return (ret_status); ++ } ++ ++ /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ ++ if (length < EMAC_MIN_ETHERNET_PKT_SIZE) ++ { ++ length = EMAC_MIN_ETHERNET_PKT_SIZE; ++ } ++ ++ /* Populate the TX descriptor */ ++ emac_tx_desc->next = 0; ++ emac_tx_desc->buffer = (unsigned char *)packet; ++ emac_tx_desc->buff_off_len = (length & 0xFFFF); ++ emac_tx_desc->pkt_flag_len = ((length & 0xFFFF) | ++ EMAC_CPPI_SOP_BIT | ++ EMAC_CPPI_OWNERSHIP_BIT | ++ EMAC_CPPI_EOP_BIT); ++ /* Send the packet */ ++ adap_emac->TX0HDP = (unsigned int) emac_tx_desc; ++ ++ /* Wait for packet to complete or link down */ ++ while (1) ++ { ++ emac_link_status = mdio_get_link_state(EMAC_MDIO_PHY_MASK); ++ if (emac_link_status == 0) ++ { ++ emac_ch_teardown(EMAC_CH_TX); ++ return (ret_status); ++ } ++ if (adap_emac->TXINTSTATRAW & 0x1) ++ { ++ ret_status = length; ++ break; ++ } ++ ++tx_send_loop; ++ } ++ ++ return (ret_status); ++ ++} ++ ++/* ++ * This function handles receipt of a packet from the network ++ */ ++static int emac_rcv_packet (void) ++{ ++ volatile emac_desc *rx_curr_desc; ++ volatile emac_desc *curr_desc; ++ volatile emac_desc *tail_desc; ++ unsigned int status, ret= -1; ++ ++ rx_curr_desc = emac_rx_active_head; ++ status = rx_curr_desc->pkt_flag_len; ++ if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) ++ { ++ if (status & EMAC_CPPI_RX_ERROR_FRAME) { ++ /* Error in packet - discard it and requeue desc */ ++ printf("WARN: emac_rcv_pkt: Error in packet\n"); ++ } ++ else { ++ NetReceive(rx_curr_desc->buffer, (rx_curr_desc->buff_off_len & 0xFFFF)); ++ ret = rx_curr_desc->buff_off_len & 0xFFFF; ++ } ++ ++ /* Ack received packet descriptor */ ++ adap_emac->RX0CP = (unsigned int) rx_curr_desc; ++ curr_desc = rx_curr_desc; ++ emac_rx_active_head = rx_curr_desc->next; ++ ++ if (status & EMAC_CPPI_EOQ_BIT) { ++ if (emac_rx_active_head) { ++ adap_emac->RX0HDP = (unsigned int) emac_rx_active_head; ++ } else { ++ emac_rx_queue_active = 0; ++ printf("INFO:emac_rcv_packet: RX Queue not active\n"); ++ } ++ } ++ ++ /* Recycle RX descriptor */ ++ rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; ++ rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; ++ rx_curr_desc->next = 0; ++ ++ if (emac_rx_active_head == 0) { ++ printf("INFO: emac_rcv_pkt: active queue head = 0\n"); ++ emac_rx_active_head = curr_desc; ++ emac_rx_active_tail = curr_desc; ++ if (emac_rx_queue_active != 0) { ++ adap_emac->RX0HDP = (unsigned int) emac_rx_active_head; ++ printf("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); ++ emac_rx_queue_active = 1; ++ } ++ } else { ++ ++ tail_desc = emac_rx_active_tail; ++ emac_rx_active_tail = curr_desc; ++ tail_desc->next = curr_desc; ++ status = tail_desc->pkt_flag_len; ++ if (status & EMAC_CPPI_EOQ_BIT) { ++ adap_emac->RX0HDP = (unsigned int) curr_desc; ++ status &= ~EMAC_CPPI_EOQ_BIT; ++ tail_desc->pkt_flag_len = status; ++ } ++ } ++ return ret; ++ } ++ return (0); ++} ++ ++#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ ++ ++#endif /* CONFIG_DRIVER_TI_EMAC */ +diff -Nurd u-boot-1.2.0/board/davinci/dm644x_emac.h u-boot-1.2.0-leopard/board/davinci/dm644x_emac.h +--- u-boot-1.2.0/board/davinci/dm644x_emac.h 1969-12-31 21:00:00.000000000 -0300 ++++ u-boot-1.2.0-leopard/board/davinci/dm644x_emac.h 2007-12-04 07:50:28.000000000 -0300 +@@ -0,0 +1,290 @@ ++/* ++ * dm644x_emac.h ++ * ++ * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM ++ * ++ * Copyright (C) 2005 Texas Instruments. ++ * ++ * ---------------------------------------------------------------------------- ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ---------------------------------------------------------------------------- ++ ++ * Modifications: ++ * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot. ++ * ++ */ ++ ++#ifndef _DM644X_EMAC_H_ ++#define _DM644X_EMAC_H_ ++ ++/*********************************************** ++ ********** Configurable items ***************** ++ ***********************************************/ ++ ++/* Addresses of EMAC module in DaVinci */ ++#define EMAC_BASE_ADDR (0x01C80000) ++#define EMAC_WRAPPER_BASE_ADDR (0x01C81000) ++#define EMAC_WRAPPER_RAM_ADDR (0x01C82000) ++#define EMAC_MDIO_BASE_ADDR (0x01C84000) ++ ++/* MDIO module input frequency */ ++#define EMAC_MDIO_BUS_FREQ 76500000 /* PLL/6 - 76.5 MHz */ ++/* MDIO clock output frequency */ ++#define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */ ++ ++/* PHY mask - set only those phy number bits where phy is/can be connected */ ++#define EMAC_MDIO_PHY_MASK 0xFFFFFFFF ++ ++/* Ethernet Min/Max packet size */ ++#define EMAC_MIN_ETHERNET_PKT_SIZE 60 ++#define EMAC_MAX_ETHERNET_PKT_SIZE 1518 ++#define EMAC_PKT_ALIGN 18 /* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */ ++ ++/* Number of RX packet buffers ++ * NOTE: Only 1 buffer supported as of now ++ */ ++#define EMAC_MAX_RX_BUFFERS 10 ++ ++/*********************************************** ++ ******** Internally used macros *************** ++ ***********************************************/ ++ ++#define EMAC_CH_TX 1 ++#define EMAC_CH_RX 0 ++ ++/* Each descriptor occupies 4, lets start RX desc's at 0 and ++ * reserve space for 64 descriptors max ++ */ ++#define EMAC_RX_DESC_BASE 0x0 ++#define EMAC_TX_DESC_BASE 0x1000 ++ ++/* EMAC Teardown value */ ++#define EMAC_TEARDOWN_VALUE 0xFFFFFFFC ++ ++/* MII Status Register */ ++#define MII_STATUS_REG 1 ++ ++/* Intel LXT971 Digtal Config Register */ ++#define MII_DIGITAL_CONFIG_REG 26 ++ ++/* Number of statistics registers */ ++#define EMAC_NUM_STATS 36 ++ ++/* EMAC Descriptor */ ++typedef volatile struct _emac_desc ++{ ++ unsigned int next; /* Pointer to next descriptor in chain */ ++ unsigned char *buffer; /* Pointer to data buffer */ ++ unsigned int buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */ ++ unsigned int pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */ ++} emac_desc; ++ ++/* CPPI bit positions */ ++#define EMAC_CPPI_SOP_BIT (0x80000000) /*(1 << 31)*/ ++#define EMAC_CPPI_EOP_BIT (0x40000000) /*(1 << 30*/ ++#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000) /*(1 << 29)*/ ++#define EMAC_CPPI_EOQ_BIT (0x10000000) /*(1 << 28)*/ ++#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000) /*(1 << 27)*/ ++#define EMAC_CPPI_PASS_CRC_BIT (0x04000000) /*(1 << 26)*/ ++ ++#define EMAC_CPPI_RX_ERROR_FRAME (0x03FC0000) ++ ++#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) ++#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) ++ ++#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) ++#define EMAC_RXMBPENABLE_RXBROADEN (0x2000) ++ ++ ++#define MDIO_CONTROL_ENABLE (0x40000000) ++#define MDIO_CONTROL_FAULT (0x80000) ++#define MDIO_USERACCESS0_GO (0x80000000) ++#define MDIO_USERACCESS0_WRITE_READ (0x0) ++#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000) ++ ++ ++ ++/* EMAC Register overlay */ ++ ++/* Ethernet MAC Register Overlay Structure */ ++typedef volatile struct { ++ unsigned int TXIDVER; ++ unsigned int TXCONTROL; ++ unsigned int TXTEARDOWN; ++ unsigned char RSVD0[4]; ++ unsigned int RXIDVER; ++ unsigned int RXCONTROL; ++ unsigned int RXTEARDOWN; ++ unsigned char RSVD1[100]; ++ unsigned int TXINTSTATRAW; ++ unsigned int TXINTSTATMASKED; ++ unsigned int TXINTMASKSET; ++ unsigned int TXINTMASKCLEAR; ++ unsigned int MACINVECTOR; ++ unsigned char RSVD2[12]; ++ unsigned int RXINTSTATRAW; ++ unsigned int RXINTSTATMASKED; ++ unsigned int RXINTMASKSET; ++ unsigned int RXINTMASKCLEAR; ++ unsigned int MACINTSTATRAW; ++ unsigned int MACINTSTATMASKED; ++ unsigned int MACINTMASKSET; ++ unsigned int MACINTMASKCLEAR; ++ unsigned char RSVD3[64]; ++ unsigned int RXMBPENABLE; ++ unsigned int RXUNICASTSET; ++ unsigned int RXUNICASTCLEAR; ++ unsigned int RXMAXLEN; ++ unsigned int RXBUFFEROFFSET; ++ unsigned int RXFILTERLOWTHRESH; ++ unsigned char RSVD4[8]; ++ unsigned int RX0FLOWTHRESH; ++ unsigned int RX1FLOWTHRESH; ++ unsigned int RX2FLOWTHRESH; ++ unsigned int RX3FLOWTHRESH; ++ unsigned int RX4FLOWTHRESH; ++ unsigned int RX5FLOWTHRESH; ++ unsigned int RX6FLOWTHRESH; ++ unsigned int RX7FLOWTHRESH; ++ unsigned int RX0FREEBUFFER; ++ unsigned int RX1FREEBUFFER; ++ unsigned int RX2FREEBUFFER; ++ unsigned int RX3FREEBUFFER; ++ unsigned int RX4FREEBUFFER; ++ unsigned int RX5FREEBUFFER; ++ unsigned int RX6FREEBUFFER; ++ unsigned int RX7FREEBUFFER; ++ unsigned int MACCONTROL; ++ unsigned int MACSTATUS; ++ unsigned int EMCONTROL; ++ unsigned int FIFOCONTROL; ++ unsigned int MACCONFIG; ++ unsigned int SOFTRESET; ++ unsigned char RSVD5[88]; ++ unsigned int MACSRCADDRLO; ++ unsigned int MACSRCADDRHI; ++ unsigned int MACHASH1; ++ unsigned int MACHASH2; ++ unsigned int BOFFTEST; ++ unsigned int TPACETEST; ++ unsigned int RXPAUSE; ++ unsigned int TXPAUSE; ++ unsigned char RSVD6[16]; ++ unsigned int RXGOODFRAMES; ++ unsigned int RXBCASTFRAMES; ++ unsigned int RXMCASTFRAMES; ++ unsigned int RXPAUSEFRAMES; ++ unsigned int RXCRCERRORS; ++ unsigned int RXALIGNCODEERRORS; ++ unsigned int RXOVERSIZED; ++ unsigned int RXJABBER; ++ unsigned int RXUNDERSIZED; ++ unsigned int RXFRAGMENTS; ++ unsigned int RXFILTERED; ++ unsigned int RXQOSFILTERED; ++ unsigned int RXOCTETS; ++ unsigned int TXGOODFRAMES; ++ unsigned int TXBCASTFRAMES; ++ unsigned int TXMCASTFRAMES; ++ unsigned int TXPAUSEFRAMES; ++ unsigned int TXDEFERRED; ++ unsigned int TXCOLLISION; ++ unsigned int TXSINGLECOLL; ++ unsigned int TXMULTICOLL; ++ unsigned int TXEXCESSIVECOLL; ++ unsigned int TXLATECOLL; ++ unsigned int TXUNDERRUN; ++ unsigned int TXCARRIERSENSE; ++ unsigned int TXOCTETS; ++ unsigned int FRAME64; ++ unsigned int FRAME65T127; ++ unsigned int FRAME128T255; ++ unsigned int FRAME256T511; ++ unsigned int FRAME512T1023; ++ unsigned int FRAME1024TUP; ++ unsigned int NETOCTETS; ++ unsigned int RXSOFOVERRUNS; ++ unsigned int RXMOFOVERRUNS; ++ unsigned int RXDMAOVERRUNS; ++ unsigned char RSVD7[624]; ++ unsigned int MACADDRLO; ++ unsigned int MACADDRHI; ++ unsigned int MACINDEX; ++ unsigned char RSVD8[244]; ++ unsigned int TX0HDP; ++ unsigned int TX1HDP; ++ unsigned int TX2HDP; ++ unsigned int TX3HDP; ++ unsigned int TX4HDP; ++ unsigned int TX5HDP; ++ unsigned int TX6HDP; ++ unsigned int TX7HDP; ++ unsigned int RX0HDP; ++ unsigned int RX1HDP; ++ unsigned int RX2HDP; ++ unsigned int RX3HDP; ++ unsigned int RX4HDP; ++ unsigned int RX5HDP; ++ unsigned int RX6HDP; ++ unsigned int RX7HDP; ++ unsigned int TX0CP; ++ unsigned int TX1CP; ++ unsigned int TX2CP; ++ unsigned int TX3CP; ++ unsigned int TX4CP; ++ unsigned int TX5CP; ++ unsigned int TX6CP; ++ unsigned int TX7CP; ++ unsigned int RX0CP; ++ unsigned int RX1CP; ++ unsigned int RX2CP; ++ unsigned int RX3CP; ++ unsigned int RX4CP; ++ unsigned int RX5CP; ++ unsigned int RX6CP; ++ unsigned int RX7CP; ++} emac_regs; ++ ++/* EMAC Wrapper Register Overlay */ ++typedef volatile struct { ++ volatile unsigned char RSVD0[4100]; ++ volatile unsigned int EWCTL; ++ volatile unsigned int EWINTTCNT; ++} ewrap_regs; ++ ++ ++/* EMAC MDIO Register Overlay */ ++typedef volatile struct { ++ volatile unsigned int VERSION; ++ volatile unsigned int CONTROL; ++ volatile unsigned int ALIVE; ++ volatile unsigned int LINK; ++ volatile unsigned int LINKINTRAW; ++ volatile unsigned int LINKINTMASKED; ++ volatile unsigned char RSVD0[8]; ++ volatile unsigned int USERINTRAW; ++ volatile unsigned int USERINTMASKED; ++ volatile unsigned int USERINTMASKSET; ++ volatile unsigned int USERINTMASKCLEAR; ++ volatile unsigned char RSVD1[80]; ++ volatile unsigned int USERACCESS0; ++ volatile unsigned int USERPHYSEL0; ++ volatile unsigned int USERACCESS1; ++ volatile unsigned int USERPHYSEL1; ++} mdio_regs; ++ ++ ++#endif /* _DM644X_EMAC_H_ */ +diff -Nurd u-boot-1.2.0/board/davinci/flash.c u-boot-1.2.0-leopard/board/davinci/flash.c +--- u-boot-1.2.0/board/davinci/flash.c 1969-12-31 21:00:00.000000000 -0300 ++++ u-boot-1.2.0-leopard/board/davinci/flash.c 2007-12-04 07:50:28.000000000 -0300 +@@ -0,0 +1,686 @@ ++/* ++ * (C) Copyright 2003 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * (C) Copyright 2003 ++ * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include "types.h" ++ ++flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ ++ ++#if defined (CFG_DAVINCI) ++ typedef unsigned short FLASH_PORT_WIDTH; ++ typedef volatile unsigned short FLASH_PORT_WIDTHV; ++ #define FLASH_ID_MASK 0xFF ++ ++ #define FPW FLASH_PORT_WIDTH ++ #define FPWV FLASH_PORT_WIDTHV ++ ++ #define FLASH_CYCLE1 0x0555 ++ #define FLASH_CYCLE2 0x02aa ++ #define FLASH_ID1 0 ++ #define FLASH_ID2 1 ++ #define FLASH_ID3 0x0e ++ #define FLASH_ID4 0x0F ++ #define SWAP(x) __swab16(x) ++#endif ++ ++#if defined (CONFIG_TOP860) ++ typedef unsigned short FLASH_PORT_WIDTH; ++ typedef volatile unsigned short FLASH_PORT_WIDTHV; ++ #define FLASH_ID_MASK 0xFF ++ ++ #define FPW FLASH_PORT_WIDTH ++ #define FPWV FLASH_PORT_WIDTHV ++ ++ #define FLASH_CYCLE1 0x0555 ++ #define FLASH_CYCLE2 0x02aa ++ #define FLASH_ID1 0 ++ #define FLASH_ID2 1 ++ #define FLASH_ID3 0x0e ++ #define FLASH_ID4 0x0F ++#endif ++ ++#if defined (CONFIG_TOP5200) && !defined (CONFIG_LITE5200) ++ typedef unsigned char FLASH_PORT_WIDTH; ++ typedef volatile unsigned char FLASH_PORT_WIDTHV; ++ #define FLASH_ID_MASK 0xFF ++ ++ #define FPW FLASH_PORT_WIDTH ++ #define FPWV FLASH_PORT_WIDTHV ++ ++ #define FLASH_CYCLE1 0x0aaa ++ #define FLASH_CYCLE2 0x0555 ++ #define FLASH_ID1 0 ++ #define FLASH_ID2 2 ++ #define FLASH_ID3 0x1c ++ #define FLASH_ID4 0x1E ++#endif ++ ++#if defined (CONFIG_TOP5200) && defined (