From 7cc9f9690818e8ad8eb8ebe847d431bb94c00640 Mon Sep 17 00:00:00 2001 From: Marcin Juszkiewicz Date: Sat, 16 May 2009 09:40:26 +0200 Subject: gcc 4.3.3: add ep93xx patches from Martin W. Guy Patchset taken from http://martinwguy.co.uk/martin/crunch/ Text from page: On 10 March there were no known bugs in this stuff (again). On 19 March libvorbisenc managed to find a bug in GCC whereby it incorrectly optimizes certain code sequences that use single-precision floats. The Maverick code generator exhibits similar symptoms for the same code, but only at optimization levels -O2 and above, so the fastest reliable optimization options for Maverick at present are -O -ffast-math. I've been working on GCC-4.3.3 to make it generate working code for the Cirrus Logic MaverickCrunch FPU, as found in their ARM-based EP9302, EP9307, EP9312 and EP9315 chips, making floating point-intensive code about 2.5 times faster. This follows on from Hasjim Williams' earlier work with gcc-4.1.2 and 4.2.0, a bundle of his more recent ideas and more hacks from me. If you want to understand the patches themselves, there is an article about the MaverickCrunch FPU and GCC's problems with it on the Debian wiki [1] and I have added commentary at the top of the individual patch files. 1. http://wiki.debian.org/ArmEabiMaverickCrunch Signed-off-by: Marcin Juszkiewicz Acked-by: Koen Kooi Acked-by: Tom Rini --- recipes/gcc/gcc-4.3.3.inc | 27 + recipes/gcc/gcc-4.3.3/ep93xx/README | 11 + recipes/gcc/gcc-4.3.3/ep93xx/URL | 1 + .../gcc/gcc-4.3.3/ep93xx/arm-crunch-20000320.patch | 13 + .../arm-crunch-arm_dbx_register_number.patch | 15 + .../gcc-4.3.3/ep93xx/arm-crunch-ccmav-mode.patch | 734 +++++++++++++++++++++ .../ep93xx/arm-crunch-cfcpy-with-cfsh64.patch | 27 + .../ep93xx/arm-crunch-cftruncd32-attr.patch | 12 + .../ep93xx/arm-crunch-cirrus-di-flag.patch | 248 +++++++ .../ep93xx/arm-crunch-disable-cmpdi.patch | 29 + .../gcc-4.3.3/ep93xx/arm-crunch-drop-thumb2.patch | 98 +++ ...eabi-ieee754-endian-littleword-littlebyte.patch | 15 + .../arm-crunch-eabi-mvf0-scratch-ieee754.patch | 89 +++ .../arm-crunch-fix-64bit-const-offsets.patch | 25 + .../ep93xx/arm-crunch-fix-cirrus-reorg5.patch | 313 +++++++++ .../ep93xx/arm-crunch-floatsi-no-scratch.patch | 35 + .../gcc-4.3.3/ep93xx/arm-crunch-fp_consts.patch | 15 + .../gcc/gcc-4.3.3/ep93xx/arm-crunch-mieee.patch | 267 ++++++++ .../ep93xx/arm-crunch-movsf-movdf-Uy.patch | 65 ++ .../gcc-4.3.3/ep93xx/arm-crunch-neg-enable.patch | 31 + .../gcc-4.3.3/ep93xx/arm-crunch-neg-protect.patch | 33 + .../gcc/gcc-4.3.3/ep93xx/arm-crunch-pipeline.patch | 461 +++++++++++++ .../gcc/gcc-4.3.3/ep93xx/arm-crunch-readme.patch | 107 +++ .../ep93xx/arm-crunch-repair-truncxfsi.patch | 29 + .../gcc/gcc-4.3.3/ep93xx/arm-crunch-saveregs.patch | 88 +++ .../gcc/gcc-4.3.3/ep93xx/arm-crunch-scratch.patch | 27 + .../gcc-4.3.3/ep93xx/arm-prologue_use-length.patch | 10 + recipes/gcc/gcc-4.3.3/ep93xx/arm-size-bugfix.patch | 33 + recipes/gcc/gcc-4.3.3/ep93xx/series | 25 + 29 files changed, 2883 insertions(+) create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/README create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/URL create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-20000320.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-arm_dbx_register_number.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-ccmav-mode.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-cfcpy-with-cfsh64.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-cftruncd32-attr.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-cirrus-di-flag.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-disable-cmpdi.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-drop-thumb2.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-eabi-ieee754-endian-littleword-littlebyte.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-eabi-mvf0-scratch-ieee754.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-fix-64bit-const-offsets.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-fix-cirrus-reorg5.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-floatsi-no-scratch.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-fp_consts.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-mieee.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-movsf-movdf-Uy.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-neg-enable.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-neg-protect.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-pipeline.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-readme.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-repair-truncxfsi.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-saveregs.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-scratch.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-prologue_use-length.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/arm-size-bugfix.patch create mode 100644 recipes/gcc/gcc-4.3.3/ep93xx/series diff --git a/recipes/gcc/gcc-4.3.3.inc b/recipes/gcc/gcc-4.3.3.inc index 2947b185b9..6ccb0f1895 100644 --- a/recipes/gcc/gcc-4.3.3.inc +++ b/recipes/gcc/gcc-4.3.3.inc @@ -65,6 +65,33 @@ SRC_URI_append_sh3 = " file://sh3-installfix-fixheaders.patch;patch=1 " SRC_URI_append_sh4 = " file://sh_unwind.patch;patch=1 \ file://gcc-4.2.3-linux-multilib-fix.patch;patch=1 \ " +SRC_URI_append_ep93xx = " \ + file://ep93xx/arm-crunch-readme.patch;patch=1 \ + file://ep93xx/arm-crunch-saveregs.patch;patch=1 \ + file://ep93xx/arm-crunch-scratch.patch;patch=1 \ + file://ep93xx/arm-crunch-eabi-ieee754-endian-littleword-littlebyte.patch;patch=1 \ + file://ep93xx/arm-crunch-eabi-mvf0-scratch-ieee754.patch;patch=1 \ + file://ep93xx/arm-crunch-20000320.patch;patch=1 \ + file://ep93xx/arm-crunch-disable-cmpdi.patch;patch=1 \ + file://ep93xx/arm-crunch-fix-64bit-const-offsets.patch;patch=1 \ + file://ep93xx/arm-crunch-fp_consts.patch;patch=1 \ + file://ep93xx/arm-crunch-neg-enable.patch;patch=1 \ + file://ep93xx/arm-crunch-neg-protect.patch;patch=1 \ + file://ep93xx/arm-crunch-repair-truncxfsi.patch;patch=1 \ + file://ep93xx/arm-crunch-floatsi-no-scratch.patch;patch=1 \ + file://ep93xx/arm-crunch-movsf-movdf-Uy.patch;patch=1 \ + file://ep93xx/arm-crunch-drop-thumb2.patch;patch=1 \ + file://ep93xx/arm-crunch-arm_dbx_register_number.patch;patch=1 \ + file://ep93xx/arm-crunch-pipeline.patch;patch=1 \ + file://ep93xx/arm-crunch-ccmav-mode.patch;patch=1 \ + file://ep93xx/arm-crunch-cfcpy-with-cfsh64.patch;patch=1 \ + file://ep93xx/arm-crunch-mieee.patch;patch=1 \ + file://ep93xx/arm-size-bugfix.patch;patch=1 \ + file://ep93xx/arm-prologue_use-length.patch;patch=1 \ + file://ep93xx/arm-crunch-cftruncd32-attr.patch;patch=1 \ + file://ep93xx/arm-crunch-fix-cirrus-reorg5.patch;patch=1 \ + file://ep93xx/arm-crunch-cirrus-di-flag.patch;patch=1 \ +" # Language Overrides FORTRAN = "" FORTRAN_linux-gnueabi = ",fortran" diff --git a/recipes/gcc/gcc-4.3.3/ep93xx/README b/recipes/gcc/gcc-4.3.3/ep93xx/README new file mode 100644 index 0000000000..a656a850cb --- /dev/null +++ b/recipes/gcc/gcc-4.3.3/ep93xx/README @@ -0,0 +1,11 @@ +This is a set of patches for gcc-4.3 that fix code generation for the +Maverick Crunch FPU present in Cirrus Logic EP93xx devices. + +They are based on the patch ideas for OpenEmbedded that Hasjim Williams sent me +privately in April 2008, with my own reimplementation of the CCMAV mode and the +addition of a -mieee switch to fully respect denormalized values (with a 50% +speed penalty). + +See the comments at the top of each patch file for further details. + + Martin Guy , 21 November 2008 - 12 March 2009 diff --git a/recipes/gcc/gcc-4.3.3/ep93xx/URL b/recipes/gcc/gcc-4.3.3/ep93xx/URL new file mode 100644 index 0000000000..7761ed8cee --- /dev/null +++ b/recipes/gcc/gcc-4.3.3/ep93xx/URL @@ -0,0 +1 @@ +http://martinwguy.co.uk/martin/crunch/gcc-4.3.3-patches/ diff --git a/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-20000320.patch b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-20000320.patch new file mode 100644 index 0000000000..8a9836bb2e --- /dev/null +++ b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-20000320.patch @@ -0,0 +1,13 @@ +Fix one test in the testsuite to know about Maverick crunch word order + +--- gcc-4.3.2/gcc/testsuite/gcc.c-torture/execute/ieee/20000320-1.c.original 2007-06-07 16:33:44.000000000 +1000 ++++ gcc-4.3.2/gcc/testsuite/gcc.c-torture/execute/ieee/20000320-1.c 2007-06-07 16:34:05.000000000 +1000 +@@ -48,7 +48,7 @@ + exit (0); + + c(0x3690000000000000ULL, 0x00000000U); +-#if (defined __arm__ || defined __thumb__) && ! (defined __ARMEB__ || defined __VFP_FP__) ++#if (defined __arm__ || defined __thumb__) && ! (defined __ARMEB__ || defined __VFP_FP__) && ! (defined __MAVERICK__) + /* The ARM always stores FP numbers in big-wordian format, + even when running in little-byteian mode. */ + c(0x0000000136900000ULL, 0x00000001U); diff --git a/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-arm_dbx_register_number.patch b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-arm_dbx_register_number.patch new file mode 100644 index 0000000000..4d4b9da298 --- /dev/null +++ b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-arm_dbx_register_number.patch @@ -0,0 +1,15 @@ +Include the Maverick Crunch registers in the GCC->DWARF2 register number +mapping. Without this, cc -g with maverick hardfloat fails. + +--- gcc-4.3.2/gcc/config/arm/arm.c-original 2008-04-11 16:16:25.000000000 +1000 ++++ gcc-4.3.2/gcc/config/arm/arm.c 2008-04-11 16:19:15.000000000 +1000 +@@ -18298,6 +18298,9 @@ + if (IS_FPA_REGNUM (regno)) + return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM; + ++ if (IS_CIRRUS_REGNUM (regno)) ++ return 28 + regno - FIRST_CIRRUS_FP_REGNUM; ++ + /* FIXME: VFPv3 register numbering. */ + if (IS_VFP_REGNUM (regno)) + return 64 + regno - FIRST_VFP_REGNUM; diff --git a/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-ccmav-mode.patch b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-ccmav-mode.patch new file mode 100644 index 0000000000..0edb1c0334 --- /dev/null +++ b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-ccmav-mode.patch @@ -0,0 +1,734 @@ +These modifications implement a new condition code mode CCMAV which is used +on floating point comparisons that were performed in the Maverick Crunch FPU. + +This is necessary because the Maverick sets the conditions codes differently +from the ARM/FPA/VFP. Since we do not use the Maverick's 32-bit int modes nor +its 64-bit comparison, these different conditions pertain to all floating point +comparisons when compiling for Maverick hardfloat. + + ARM/FPA/VFP - (cmp*): MaverickCrunch - (cfcmp*): + N Z C V N Z C V + A == B 0 1 1 0 A == B 0 1 0 0 + A < B 1 0 0 0 A < B 1 0 0 0 + A > B 0 0 1 0 A > B 1 0 0 1 + unord 0 0 1 1 unord 0 0 0 0 + +The new mode is set on floating point comparisons instead of the usual +CCFP and CCFPE, then acted upon when the conditional instruction flags +are output. + +Furthermore, the list of conditions that cannot be tested with a single +conditional test is different. On ARM/FPA/VFP it is UNEQ and LTGT while +on Maverick it is GE UNLT ORDERED and UNORDERED. +We handle this with a new predicate "maverick_comparison_operator" that omits +the comparisons that cannot be represented and we split the cond_exec pattern +into for CCMAV mode plus a separate rule for every non-Maverick CC mode. +This prevents generation of conditional instructions that cannot be represented. + +Although Maverick can also represent LTGT and UNEQ with a single test, we do not +include these since it would mean splitting every other rule that uses +"arm_comparison_operator" in a similar way for very little gain. + +A few other tests are added to prevent optimisations that would +generate these unrepresentable conditions. + +None of these changes affect code generation for ARM or for other FPUs. + +One missed optimisation: movsfcc and movdfcc have been +disabled for Maverick because we don't use the Maverick's instructions +conditionally to avoid hardware bugs. But a limited movsfcc and movdfcc +could be included when Maverick, that applies to all modes where the things +to be moved do not involve the Maverick registers, if such a thing is feasible +without the optimizer moving things into registers between the expand and the +instruction generation. + + Martin Guy , November 2008 + +--- gcc-4.3.2/gcc/config/arm/arm-modes.def.old 2007-08-02 11:49:31.000000000 +0100 ++++ gcc-4.3.2/gcc/config/arm/arm-modes.def 2008-11-18 14:39:39.000000000 +0000 +@@ -27,6 +27,7 @@ + + /* CCFPEmode should be used with floating inequalities, + CCFPmode should be used with floating equalities. ++ CCMAVmode should be used with comparisons performed in the Maverick FPU + CC_NOOVmode should be used with SImode integer equalities. + CC_Zmode should be used if only the Z flag is set correctly + CC_Nmode should be used if only the N (sign) flag is set correctly +@@ -37,6 +38,7 @@ + CC_MODE (CC_SWP); + CC_MODE (CCFP); + CC_MODE (CCFPE); ++CC_MODE (CCMAV); + CC_MODE (CC_DNE); + CC_MODE (CC_DEQ); + CC_MODE (CC_DLE); +--- gcc-4.3.2/gcc/config/arm/arm.h 2008-11-18 15:32:10.000000000 +0000 ++++ cluster/gcc-4.3.2/gcc/config/arm/arm.h 2008-11-21 19:24:10.000000000 +0000 +@@ -2306,7 +2306,7 @@ + #define REVERSIBLE_CC_MODE(MODE) 1 + + #define REVERSE_CONDITION(CODE,MODE) \ +- (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ ++ (((MODE) == CCFPmode || (MODE) == CCFPEmode || (MODE) == CCMAVmode) \ + ? reverse_condition_maybe_unordered (code) \ + : reverse_condition (code)) + +--- gcc-4.3.2/gcc/config/arm/predicates.md.old 2007-08-02 11:49:31.000000000 +0100 ++++ gcc-4.3.2/gcc/config/arm/predicates.md 2008-11-20 15:05:50.000000000 +0000 +@@ -195,6 +195,16 @@ + (define_special_predicate "arm_comparison_operator" + (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt")) + ++;; Comparisons that can be predicated after a Maverick FP comparison, true for ++;; floating point comparisons other than GE, UNLT, UNORDERED or ORDERED ++;; ++;; Maverick can also match LTGT and UNEQ with a single condition ++;; but including these means duplicating every rule containing ++;; arm_comparison_operator including cond_branch and all the *cc rules. ++;; Extra speed when predicating ltgt and uneq is rare enough not to be worth it. ++(define_special_predicate "maverick_comparison_operator" ++(match_code "eq,ne,le,lt,gt,unle,unge,ungt")) ++ + (define_special_predicate "minmax_operator" + (and (match_code "smin,smax,umin,umax") + (match_test "mode == GET_MODE (op)"))) +--- gcc-4.3.2/gcc/config/arm/arm.c.old 2008-11-19 10:01:53.000000000 +0000 ++++ gcc-4.3.2/gcc/config/arm/arm.c 2008-11-21 12:49:48.000000000 +0000 +@@ -1720,6 +1720,14 @@ + return 0; + } + ++ /* Optimisation of __builtin_inunordered at the end of a ++ * function would generate conditional return on (UN)ORDERED, which cannot ++ * be represented by a single condition code test on Maverick. ++ * Since we do not have access to the specific condition used, ++ * we just disable all conditional returns on Maverick. */ ++ if (iscond && TARGET_MAVERICK && TARGET_HARD_FLOAT) ++ return 0; ++ + /* If there are saved registers but the LR isn't saved, then we need + two instructions for the return. */ + if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM))) +@@ -7733,6 +7741,10 @@ + comparison, and CCFPE otherwise. */ + if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) + { ++ /* Comparisons performed in the Maverick FPU set the CCs their own way. */ ++ if (TARGET_HARD_FLOAT && TARGET_MAVERICK) ++ return CCMAVmode; ++ + switch (op) + { + case EQ: +@@ -7751,8 +7763,6 @@ + case LE: + case GT: + case GE: +- if (TARGET_HARD_FLOAT && TARGET_MAVERICK) +- return CCFPmode; + return CCFPEmode; + + default: +@@ -13367,6 +13377,29 @@ + default: gcc_unreachable (); + } + ++ case CCMAVmode: ++ /* Maverick cmp sets the condition codes differently from ARM/FPA/VFP */ ++ switch (comp_code) ++ { ++ case GT: return ARM_VS; ++ case LE: return ARM_LE; ++ case LT: return ARM_LT; ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case UNLE: return ARM_VC; ++ case UNGT: return ARM_GT; ++ case UNGE: return ARM_GE; ++ case UNEQ: return ARM_PL; ++ case LTGT: return ARM_MI; ++ /* These cannot be represented by a single condition code. */ ++ case GE: /* Fall through */ ++ case UNLT:/* Fall through */ ++ case ORDERED:/* Fall through */ ++ case UNORDERED:/* Fall through */ ++ default: ++ gcc_unreachable (); ++ } ++ + case CC_SWPmode: + switch (comp_code) + { +--- gcc-4.3.2/gcc/config/arm/arm.md.old 2008-11-21 19:08:44.000000000 +0000 ++++ gcc-4.3.2/gcc/config/arm/arm.md 2008-11-21 19:09:18.000000000 +0000 +@@ -258,7 +258,9 @@ + ; they are altered at all + ; + ; JUMP_CLOB is used when the condition cannot be represented by a single +-; instruction (UNEQ and LTGT). These cannot be predicated. ++; instruction. This applies to UNEQ and LTGT for ARM/FPA/VFP comparisons, ++; GE UNLT ORDERED and UNORDERED for Maverick comparisons. ++; These cannot be predicated. + ; + ; NOCOND means that the condition codes are neither altered nor affect the + ; output of this insn +@@ -7332,9 +7334,9 @@ + + ;; Cirrus SF compare instruction + (define_insn "*cirrus_cmpsf" +- [(set (reg:CCFP CC_REGNUM) +- (compare:CCFP (match_operand:SF 0 "cirrus_fp_register" "v") +- (match_operand:SF 1 "cirrus_fp_register" "v")))] ++ [(set (reg:CCMAV CC_REGNUM) ++ (compare:CCMAV (match_operand:SF 0 "cirrus_fp_register" "v") ++ (match_operand:SF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfcmps%?\\tr15, %V0, %V1" + [(set_attr "type" "farith") +@@ -7343,9 +7347,9 @@ + + ;; Cirrus DF compare instruction + (define_insn "*cirrus_cmpdf" +- [(set (reg:CCFP CC_REGNUM) +- (compare:CCFP (match_operand:DF 0 "cirrus_fp_register" "v") +- (match_operand:DF 1 "cirrus_fp_register" "v")))] ++ [(set (reg:CCMAV CC_REGNUM) ++ (compare:CCMAV (match_operand:DF 0 "cirrus_fp_register" "v") ++ (match_operand:DF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfcmpd%?\\tr15, %V0, %V1" + [(set_attr "type" "farith") +@@ -7482,12 +7484,18 @@ + "operands[1] = arm_gen_compare_reg (LTU, arm_compare_op0, arm_compare_op1);" + ) + ++;; Some of the following patterns may need two branch instructions, since ++;; there is no single instruction that will handle all cases. Specifically: ++;; ARM/FPA/VFP cannot test UNEQ and LTGT ++;; Maverick cannot test GE on floating point values, UNLT, ORDERED or UNORDERED. ++ + (define_expand "bunordered" + [(set (pc) + (if_then_else (unordered (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_32BIT && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7497,7 +7505,8 @@ + (if_then_else (ordered (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_32BIT && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7507,7 +7516,8 @@ + (if_then_else (ungt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_32BIT && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7516,7 +7526,8 @@ + (if_then_else (unlt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_32BIT && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7525,7 +7536,8 @@ + (if_then_else (unge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_32BIT && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7534,18 +7546,18 @@ + (if_then_else (unle (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_32BIT && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);" + ) + +-;; The following two patterns need two branch instructions, since there is +-;; no single instruction that will handle all cases. + (define_expand "buneq" + [(set (pc) + (if_then_else (uneq (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_32BIT && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7554,7 +7566,8 @@ + (if_then_else (ltgt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_32BIT && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7562,7 +7575,7 @@ + ;; Patterns to match conditional branch insns. + ;; + +-; Special pattern to match UNEQ. ++; Special pattern to match UNEQ for FPA and VFP. + (define_insn "*arm_buneq" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7578,7 +7591,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match LTGT. ++; Special pattern to match LTGT for FPA and VFP. + (define_insn "*arm_bltgt" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7594,6 +7607,101 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match floating point GE for Maverick. ++(define_insn "*cirrus_bge" ++ [(set (pc) ++ (if_then_else (ge (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++; Special pattern to match UNORDERED for Maverick. ++(define_insn "*cirrus_bunordered" ++ [(set (pc) ++ (if_then_else (unordered (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bmi\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ ++; Special pattern to match ORDERED for Maverick. ++(define_insn "*cirrus_bordered" ++ [(set (pc) ++ (if_then_else (ordered (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bmi\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++; Special pattern to match UNLT for Maverick. ++(define_insn "*cirrus_bunlt" ++ [(set (pc) ++ (if_then_else (unlt (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ ++; Special atterns to match UNEQ and LTGT for Maverick, to handle ++; the two cases not covered by generic *arm_cond_branch ++ ++(define_insn "*cirrus_buneq" ++ [(set (pc) ++ (if_then_else (uneq (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"bpl\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob")] ++) ++ ++(define_insn "*cirrus_bltgt" ++ [(set (pc) ++ (if_then_else (ltgt (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"bmi\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob")] ++) ++ + (define_insn "*arm_cond_branch" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7613,7 +7721,7 @@ + (set_attr "type" "branch")] + ) + +-; Special pattern to match reversed UNEQ. ++; Special pattern to match reversed UNEQ for FPA and VFP. + (define_insn "*arm_buneq_reversed" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7629,7 +7737,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match reversed LTGT. ++; Special pattern to match reversed LTGT for FPA and VFP. + (define_insn "*arm_bltgt_reversed" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7645,6 +7753,101 @@ + (set_attr "length" "8")] + ) + ++; Patterns to match reversed UNEQ and LTGT for Maverick, the two cases ++; not covered by generic "*arm_cond_branch_reversed" ++ ++(define_insn "*cirrus_buneq_reversed" ++ [(set (pc) ++ (if_then_else (uneq (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"bmi\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob")] ++) ++ ++(define_insn "*cirrus_bltgt_reversed" ++ [(set (pc) ++ (if_then_else (ltgt (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"bpl\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob")] ++) ++ ++; Special pattern to match reversed floating point GE for Maverick. ++(define_insn "*cirrus_bge_reversed" ++ [(set (pc) ++ (if_then_else (ge (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ ++; Special pattern to match reversed UNORDERED for Maverick. ++(define_insn "*cirrus_bunordered_reversed" ++ [(set (pc) ++ (if_then_else (unordered (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bmi\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++; Special pattern to match reversed ORDERED for Maverick. ++(define_insn "*cirrus_bordered_reversed" ++ [(set (pc) ++ (if_then_else (ordered (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bmi\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ ++; Special pattern to match reversed UNLT for Maverick. ++(define_insn "*cirrus_bunlt_reversed" ++ [(set (pc) ++ (if_then_else (unlt (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ + (define_insn "*arm_cond_branch_reversed" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7696,11 +7899,16 @@ + "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" + ) + ++; SGE can only be represented as a single condition code on ARM/VFP/FPA, ++; not with Maverick when the operands are floating point. + (define_expand "sge" + [(set (match_operand:SI 0 "s_register_operand" "") + (ge:SI (match_dup 1) (const_int 0)))] + "TARGET_32BIT" +- "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" ++ "if (TARGET_HARD_FLOAT && TARGET_MAVERICK ++ && GET_MODE_CLASS (GET_MODE (arm_compare_op0)) == MODE_FLOAT) ++ FAIL; ++ operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" + ) + + (define_expand "slt" +@@ -7738,6 +7946,7 @@ + "operands[1] = arm_gen_compare_reg (LTU, arm_compare_op0, arm_compare_op1);" + ) + ++; SORDERED and SUNORDERED cannot be represented on Maverick + (define_expand "sunordered" + [(set (match_operand:SI 0 "s_register_operand" "") + (unordered:SI (match_dup 1) (const_int 0)))] +@@ -7757,7 +7966,8 @@ + (define_expand "sungt" + [(set (match_operand:SI 0 "s_register_operand" "") + (ungt:SI (match_dup 1) (const_int 0)))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_32BIT && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7765,11 +7975,13 @@ + (define_expand "sunge" + [(set (match_operand:SI 0 "s_register_operand" "") + (unge:SI (match_dup 1) (const_int 0)))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_32BIT && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, + arm_compare_op1);" + ) + ++; SUNLT cannot be represented on Maverick + (define_expand "sunlt" + [(set (match_operand:SI 0 "s_register_operand" "") + (unlt:SI (match_dup 1) (const_int 0)))] +@@ -7781,7 +7993,8 @@ + (define_expand "sunle" + [(set (match_operand:SI 0 "s_register_operand" "") + (unle:SI (match_dup 1) (const_int 0)))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_32BIT && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, + arm_compare_op1);" + ) +@@ -8039,20 +8252,32 @@ + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) +- FAIL; ++ /* Reject comparisons not representable by a single condition code */ ++ if (TARGET_HARD_FLOAT && TARGET_MAVERICK ++ && GET_MODE_CLASS (GET_MODE (arm_compare_op0)) == MODE_FLOAT) ++ { ++ if (code == GE || code == UNLT || code == ORDERED || code == UNORDERED) ++ FAIL; ++ } ++ else ++ { ++ if (code == UNEQ || code == LTGT) ++ FAIL; ++ } + + ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); + operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); + }" + ) + ++; We do not use Maverick conditional FP instructions to avoid hardware bugs ++ + (define_expand "movsfcc" + [(set (match_operand:SF 0 "s_register_operand" "") + (if_then_else:SF (match_operand 1 "arm_comparison_operator" "") + (match_operand:SF 2 "s_register_operand" "") + (match_operand:SF 3 "nonmemory_operand" "")))] +- "TARGET_32BIT" ++ "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" + " + { + enum rtx_code code = GET_CODE (operands[1]); +@@ -10419,7 +10644,7 @@ + + operands[5] = gen_rtx_REG (mode, CC_REGNUM); + operands[6] = gen_rtx_COMPARE (mode, operands[2], operands[3]); +- if (mode == CCFPmode || mode == CCFPEmode) ++ if (mode == CCFPmode || mode == CCFPEmode || mode == CCMAVmode) + rc = reverse_condition_maybe_unordered (rc); + else + rc = reverse_condition (rc); +@@ -10470,7 +10695,7 @@ + + operands[6] = gen_rtx_REG (mode, CC_REGNUM); + operands[7] = gen_rtx_COMPARE (mode, operands[2], operands[3]); +- if (mode == CCFPmode || mode == CCFPEmode) ++ if (mode == CCFPmode || mode == CCFPEmode || mode == CCMAVmode) + rc = reverse_condition_maybe_unordered (rc); + else + rc = reverse_condition (rc); +@@ -10502,7 +10727,7 @@ + + operands[6] = gen_rtx_REG (mode, CC_REGNUM); + operands[7] = gen_rtx_COMPARE (mode, operands[2], operands[3]); +- if (mode == CCFPmode || mode == CCFPEmode) ++ if (mode == CCFPmode || mode == CCFPEmode || mode == CCMAVmode) + rc = reverse_condition_maybe_unordered (rc); + else + rc = reverse_condition (rc); +@@ -10809,13 +11034,75 @@ + "TARGET_32BIT && arm_arch5e" + "pld\\t%a0") + ++;; Special predication patterns for Maverick Crunch floating-point ++;; which has a different set of predicable conditions after a floating ++;; point comparison. ++ ++(define_cond_exec ++ [(match_operator 0 "maverick_comparison_operator" ++ [(match_operand:CCMAV 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++;; Every else is the same as the general ARM pattern. ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_NOOV 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_Z 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_SWP 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_C 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_N 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ + ;; General predication pattern + + (define_cond_exec + [(match_operator 0 "arm_comparison_operator" + [(match_operand 1 "cc_register" "") + (const_int 0)])] +- "TARGET_32BIT" ++ "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" + "" + ) + diff --git a/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-cfcpy-with-cfsh64.patch b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-cfcpy-with-cfsh64.patch new file mode 100644 index 0000000000..6260699167 --- /dev/null +++ b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-cfcpy-with-cfsh64.patch @@ -0,0 +1,27 @@ +cfcpys and cfcpyd have hardware bugs which mean they truncate denormalized +values to zero and convert minus zero to plus zero. + +A 64-bit shift with a shift count of 0 copies them bitwise. + + Martin Guy , December 2008 + +--- gcc-4.3.2/gcc/config/arm/cirrus.md.old 2008-11-21 19:06:37.000000000 +0000 ++++ gcc-4.3.2/gcc/config/arm/cirrus.md 2008-12-03 12:13:08.000000000 +0000 +@@ -485,7 +485,7 @@ + && (GET_CODE (operands[0]) != MEM + || register_operand (operands[1], SFmode))" + "@ +- cfcpys%?\\t%V0, %V1 ++ cfsh64%?\\t%Z0, %Z1, #0\\t%@ float + cfldrs%?\\t%V0, %1 + cfmvsr%?\\t%V0, %1 + cfmvrs%?\\t%0, %V1 +@@ -514,7 +514,7 @@ + case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\"; + case 2: return \"#\"; + case 3: case 4: return output_move_double (operands); +- case 5: return \"cfcpyd%?\\t%V0, %V1\"; ++ case 5: return \"cfsh64%?\\t%Z0, %Z1, #0\\t%@ double\"; + case 6: return \"cfldrd%?\\t%V0, %1\"; + case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\"; + case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\"; diff --git a/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-cftruncd32-attr.patch b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-cftruncd32-attr.patch new file mode 100644 index 0000000000..bdc603ac91 --- /dev/null +++ b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-cftruncd32-attr.patch @@ -0,0 +1,12 @@ +--- gcc-4.3.2/gcc/config/arm/cirrus.md.old 2009-02-16 16:19:19.000000000 +0000 ++++ gcc-4.3.2/gcc/config/arm/cirrus.md 2009-03-10 12:13:10.000000000 +0000 +@@ -425,7 +425,8 @@ + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" + [(set_attr "type" "f_cvt") +- (set_attr "length" "8")] ++ (set_attr "length" "8") ++ (set_attr "cirrus" "normal")] + ) + + ; Cirrus hardware bugs: denormalized values on input are truncated to zero diff --git a/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-cirrus-di-flag.patch b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-cirrus-di-flag.patch new file mode 100644 index 0000000000..c25c108eaa --- /dev/null +++ b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-cirrus-di-flag.patch @@ -0,0 +1,248 @@ +This patch disables all 64-bit integer operations of the MaverickCrunch unit +unless the new flag -mcirrus-di is supplied (as well as -mcpu-ep9312 +-mfpu=maverick -mfloat-abi=softfp). + +The 64-bit instructions (or their GCC support) are known to be buggy, as shown +for example by openssl-0.9.8g's testsuite: +In the unpacked openssl source directory: + $ ./config + $ vi Makefile + > /^CC= /s/$/-4.3-crunch/ + > /^CFLAG= /s/$/ -mcpu=ep9312 -mfpu=maverick -mfloat-abi=softfp -mcirrus-di/ + > :wq + $ make + $ make test +fails if either of the two files: */sha/sha512.c and */bn/bn_asm.c are compiled +with cirrus 64-bit support enabled. If you disable cfmul64, sha512.c works ok, +but I've disabled everything down to cfadd64, cfsub64 and 64-bit load and store +and bn_asm still fails, which suggests another hardware timing bug. + +--- gcc-4.3.2/gcc/config/arm/arm.opt.old 2009-03-10 22:08:13.000000000 +0000 ++++ gcc-4.3.2/gcc/config/arm/arm.opt 2009-03-10 12:47:31.000000000 +0000 +@@ -63,6 +63,10 @@ + Target Report Mask(CALLER_INTERWORKING) + Thumb: Assume function pointers may go to non-Thumb aware code + ++mcirrus-di ++Target Report Mask(CIRRUS_DI) ++Cirrus: Enable processing of 64-bit integers in the MaverickCrunch unit (buggy) ++ + mcpu= + Target RejectNegative Joined + Specify the name of the target CPU +--- gcc-4.3.2/gcc/config/arm/arm.c.old 2009-03-10 09:32:31.000000000 +0000 ++++ gcc-4.3.2/gcc/config/arm/arm.c 2009-03-10 12:44:48.000000000 +0000 +@@ -13917,7 +13917,8 @@ + upper 32 bits. This causes gcc all sorts of grief. We can't + even split the registers into pairs because Cirrus SI values + get sign extended to 64bits-- aldyh. */ +- return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode); ++ return (GET_MODE_CLASS (mode) == MODE_FLOAT) ++ || (mode == DImode && TARGET_CIRRUS_DI); + + if (TARGET_HARD_FLOAT && TARGET_VFP + && IS_VFP_REGNUM (regno)) +--- gcc-4.3.2/gcc/config/arm/arm.md.old 2009-03-10 12:14:01.000000000 +0000 ++++ gcc-4.3.2/gcc/config/arm/arm.md 2009-03-10 12:42:55.000000000 +0000 +@@ -369,7 +369,7 @@ + (clobber (reg:CC CC_REGNUM))])] + "TARGET_EITHER" + " +- if (TARGET_HARD_FLOAT && TARGET_MAVERICK) ++ if (TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI) + { + if (!cirrus_fp_register (operands[0], DImode)) + operands[0] = force_reg (DImode, operands[0]); +@@ -405,7 +405,7 @@ + (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0") + (match_operand:DI 2 "s_register_operand" "r, 0"))) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" ++ "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI)" + "#" + "TARGET_32BIT && reload_completed" + [(parallel [(set (reg:CC_C CC_REGNUM) +@@ -433,7 +433,7 @@ + (match_operand:SI 2 "s_register_operand" "r,r")) + (match_operand:DI 1 "s_register_operand" "r,0"))) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" ++ "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI)" + "#" + "TARGET_32BIT && reload_completed" + [(parallel [(set (reg:CC_C CC_REGNUM) +@@ -462,7 +462,7 @@ + (match_operand:SI 2 "s_register_operand" "r,r")) + (match_operand:DI 1 "s_register_operand" "r,0"))) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" ++ "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI)" + "#" + "TARGET_32BIT && reload_completed" + [(parallel [(set (reg:CC_C CC_REGNUM) +@@ -857,7 +857,7 @@ + (clobber (reg:CC CC_REGNUM))])] + "TARGET_EITHER" + " +- if (TARGET_HARD_FLOAT && TARGET_MAVERICK ++ if (TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI + && TARGET_32BIT + && cirrus_fp_register (operands[0], DImode) + && cirrus_fp_register (operands[1], DImode)) +@@ -2979,7 +2979,8 @@ + values to iwmmxt regs and back. */ + FAIL; + } +- else if (!TARGET_REALLY_IWMMXT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)) ++ else if (!TARGET_REALLY_IWMMXT ++ && !(TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI)) + FAIL; + " + ) +@@ -4544,7 +4545,8 @@ + [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m") + (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r"))] + "TARGET_ARM +- && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP)) ++ && !(TARGET_HARD_FLOAT ++ && ((TARGET_MAVERICK && TARGET_CIRRUS_DI) || TARGET_VFP)) + && !TARGET_IWMMXT + && ( register_operand (operands[0], DImode) + || register_operand (operands[1], DImode))" +@@ -4664,7 +4666,7 @@ + [(set (match_operand:DI 0 "nonimmediate_operand" "=l,l,l,l,>,l, m,*r") + (match_operand:DI 1 "general_operand" "l, I,J,>,l,mi,l,*r"))] + "TARGET_THUMB1 +- && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) ++ && !(TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI) + && ( register_operand (operands[0], DImode) + || register_operand (operands[1], DImode))" + "* +--- gcc-4.3.2/gcc/config/arm/cirrus.md.old 2009-03-10 12:13:10.000000000 +0000 ++++ gcc-4.3.2/gcc/config/arm/cirrus.md 2009-03-10 12:32:00.000000000 +0000 +@@ -85,7 +85,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (plus:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:DI 2 "cirrus_fp_register" "v")))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI" + "cfadd64%?\\t%V0, %V1, %V2" + [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] +@@ -126,7 +126,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (minus:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:DI 2 "cirrus_fp_register" "v")))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI" + "cfsub64%?\\t%V0, %V1, %V2" + [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] +@@ -176,7 +176,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (mult:DI (match_operand:DI 2 "cirrus_fp_register" "v") + (match_operand:DI 1 "cirrus_fp_register" "v")))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI" + "cfmul64%?\\t%V0, %V1, %V2" + [(set_attr "type" "fmul") + (set_attr "cirrus" "normal")] +@@ -261,7 +261,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "register_operand" "r")))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI" + "cfrshl64%?\\t%V1, %V0, %s2" + [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] +@@ -271,7 +271,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "cirrus_shift_const" "")))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI" + "cfsh64%?\\t%V0, %V1, #%s2" + [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] +@@ -281,7 +281,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (ashiftrt:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "cirrus_shift_const" "")))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI" + "cfsh64%?\\t%V0, %V1, #-%s2" + [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] +@@ -290,7 +290,7 @@ + (define_insn "*cirrus_absdi2" + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (abs:DI (match_operand:DI 1 "cirrus_fp_register" "v")))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI" + "cfabs64%?\\t%V0, %V1" + [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] +@@ -301,7 +301,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (neg:DI (match_operand:DI 1 "cirrus_fp_register" "v"))) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI" + "cfneg64%?\\t%V0, %V1" + [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] +@@ -392,7 +392,7 @@ + (define_insn "floatdisf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI" + "cfcvt64s%?\\t%V0, %V1" + [(set_attr "type" "f_cvt") + (set_attr "cirrus" "normal")] +@@ -401,7 +401,7 @@ + (define_insn "floatdidf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI" + "cfcvt64d%?\\t%V0, %V1" + [(set_attr "type" "f_cvt") + (set_attr "cirrus" "normal")] +@@ -454,7 +454,7 @@ + (define_insn "*cirrus_arm_movdi" + [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v") + (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,mi,v,v"))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI" + "* + { + switch (which_alternative) +--- gcc-4.3.2/gcc/doc/invoke.texi.old 2009-03-10 17:17:19.000000000 +0000 ++++ gcc-4.3.2/gcc/doc/invoke.texi 2009-03-10 17:24:19.000000000 +0000 +@@ -429,6 +429,7 @@ + -msingle-pic-base -mno-single-pic-base @gol + -mpic-register=@var{reg} @gol + -mnop-fun-dllimport @gol ++-mirrus-di @gol + -mieee @gol + -mpoke-function-name @gol + -mthumb -marm @gol +@@ -8670,6 +8671,16 @@ + Specify the register to be used for PIC addressing. The default is R10 + unless stack-checking is enabled, when R9 is used. + ++@item -mcirrus-di ++When compiling for the Maverick FPU, enable handling of 64-bit integers ++in the FPU (add, subtract, multiply, arithmetic shifts and conversions). ++Normally they are disabled because some instruction sequences can give ++erroneous results. ++This option only has any effect if the ++@option{-mcpu=ep9312} @option{-mfpu=maverick} options have been used and is ++disabled by default. ++The default can be re-enabled by use of the @option{-mno-cirrus-di} switch. ++ + @item -mieee + When compiling for the Maverick FPU, disable the instructions that fail + to honor denormalized values. As these include floating point add, sub, diff --git a/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-disable-cmpdi.patch b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-disable-cmpdi.patch new file mode 100644 index 0000000000..7db1274ef9 --- /dev/null +++ b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-disable-cmpdi.patch @@ -0,0 +1,29 @@ +Disable the Maverick's cmpdi instruction which cannot perform the simultaneous +signed/unsigned comparison expected by GCC. + +diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.md gcc-4.1.2/gcc/config/arm/arm.md +--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.md 2006-09-28 03:10:22.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-15 09:53:21.000000000 +1000 +@@ -7354,10 +7366,12 @@ + ) + + ;; Cirrus DI compare instruction ++;; This is disabled and left go through ARM core registers, because currently ++;; Crunch coprocessor does only signed comparison. + (define_expand "cmpdi" + [(match_operand:DI 0 "cirrus_fp_register" "") + (match_operand:DI 1 "cirrus_fp_register" "")] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK & 0" + "{ + arm_compare_op0 = operands[0]; + arm_compare_op1 = operands[1]; +@@ -7368,7 +7382,7 @@ + [(set (reg:CC CC_REGNUM) + (compare:CC (match_operand:DI 0 "cirrus_fp_register" "v") + (match_operand:DI 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK & 0" + "cfcmp64%?\\tr15, %V0, %V1" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "compare")] diff --git a/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-drop-thumb2.patch b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-drop-thumb2.patch new file mode 100644 index 0000000000..2722e2d0d1 --- /dev/null +++ b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-drop-thumb2.patch @@ -0,0 +1,98 @@ +MaverickCrunch FPUs only exist in silicon with an arm920t core and Cirrus have +stopped development of their ARM processors (1 April 2008, no joke!) + +This means Maverick-Thumb2 combinations will never exist in hardware, +so remove all existing Maverick+Thumb2 descriptions. + + Martin Guy November 2008 + +--- gcc-4.3.2/gcc/config/arm/cirrus.md.old 2008-11-18 12:09:40.000000000 +0000 ++++ gcc-4.3.2/gcc/config/arm/cirrus.md 2008-11-18 12:12:38.000000000 +0000 +@@ -452,87 +452,3 @@ + (set_attr "neg_pool_range" " *, *, *, *, 1008, *, 1008, *, *, *") + (set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")] + ) +- +-(define_insn "*cirrus_thumb2_movdi" +- [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v") +- (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,mi,v,v"))] +- "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_MAVERICK" +- "* +- { +- switch (which_alternative) +- { +- case 0: +- case 1: +- case 2: +- return (output_move_double (operands)); +- +- case 3: return \"cfmv64lr%?\\t%V0, %Q1\;cfmv64hr%?\\t%V0, %R1\"; +- case 4: return \"cfmvr64l%?\\t%Q0, %V1\;cfmvr64h%?\\t%R0, %V1\"; +- +- case 5: return \"cfldr64%?\\t%V0, %1\"; +- case 6: return \"cfstr64%?\\t%V1, %0\"; +- +- /* Shifting by 0 will just copy %1 into %0. */ +- case 7: return \"cfsh64%?\\t%V0, %V1, #0\"; +- +- default: abort (); +- } +- }" +- [(set_attr "length" " 8, 8, 8, 8, 8, 4, 4, 4") +- (set_attr "type" " *,load2,store2, *, *, load2,store2, *") +- (set_attr "pool_range" " *,4096, *, *, *, 1020, *, *") +- (set_attr "neg_pool_range" " *, 0, *, *, *, 1008, *, *") +- (set_attr "cirrus" "not, not, not,move,normal,double,double,normal")] +-) +- +-(define_insn "*thumb2_cirrus_movsf_hard_insn" +- [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m") +- (match_operand:SF 1 "general_operand" "v,mE,r,v,v,r,mE,r"))] +- "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_MAVERICK +- && (GET_CODE (operands[0]) != MEM +- || register_operand (operands[1], SFmode))" +- "@ +- cfcpys%?\\t%V0, %V1 +- cfldrs%?\\t%V0, %1 +- cfmvsr%?\\t%V0, %1 +- cfmvrs%?\\t%0, %V1 +- cfstrs%?\\t%V1, %0 +- mov%?\\t%0, %1 +- ldr%?\\t%0, %1\\t%@ float +- str%?\\t%1, %0\\t%@ float" +- [(set_attr "length" " *, *, *, *, *, 4, 4, 4") +- (set_attr "type" " *, load1, *, *,store1, *,load1,store1") +- (set_attr "pool_range" " *, 1020, *, *, *, *,4096, *") +- (set_attr "neg_pool_range" " *, 1008, *, *, *, *, 0, *") +- (set_attr "cirrus" "normal,normal,move,normal,normal,not, not, not")] +-) +- +-(define_insn "*thumb2_cirrus_movdf_hard_insn" +- [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m") +- (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,mF,r,v,v"))] +- "TARGET_THUMB2 +- && TARGET_HARD_FLOAT && TARGET_MAVERICK +- && (GET_CODE (operands[0]) != MEM +- || register_operand (operands[1], DFmode))" +- "* +- { +- switch (which_alternative) +- { +- case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\"; +- case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\"; +- case 2: case 3: case 4: return output_move_double (operands); +- case 5: return \"cfcpyd%?\\t%V0, %V1\"; +- case 6: return \"cfldrd%?\\t%V0, %1\"; +- case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\"; +- case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\"; +- case 9: return \"cfstrd%?\\t%V1, %0\"; +- default: abort (); +- } +- }" +- [(set_attr "type" "load1,store2, *,store2,load1, *, load1, *, *,store2") +- (set_attr "length" " 4, 4, 8, 8, 8, 4, 4, 8, 8, 4") +- (set_attr "pool_range" " *, *, *, *,4092, *, 1020, *, *, *") +- (set_attr "neg_pool_range" " *, *, *, *, 0, *, 1008, *, *, *") +- (set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")] +-) +- diff --git a/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-eabi-ieee754-endian-littleword-littlebyte.patch b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-eabi-ieee754-endian-littleword-littlebyte.patch new file mode 100644 index 0000000000..f16336d05d --- /dev/null +++ b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-eabi-ieee754-endian-littleword-littlebyte.patch @@ -0,0 +1,15 @@ +Define Maverick floating point word order in libgcc's assemble support routines + +--- ../gcc-cross-4.1.2-r4-unpatched/gcc-4.1.2/gcc/config/arm/ieee754-df.S 2007-06-07 13:06:52.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/ieee754-df.S 2008-04-07 13:15:49.000000000 +1000 +@@ -42,8 +42,9 @@ + + + @ For FPA, float words are always big-endian. ++@ For MAVERICK, float words are always little-endian. + @ For VFP, floats words follow the memory system mode. +-#if defined(__VFP_FP__) && !defined(__ARMEB__) ++#if ((defined(__VFP_FP__) && !defined(__ARMEB__)) || defined(__MAVERICK__)) + #define xl r0 + #define xh r1 + #define yl r2 diff --git a/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-eabi-mvf0-scratch-ieee754.patch b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-eabi-mvf0-scratch-ieee754.patch new file mode 100644 index 0000000000..72283f5381 --- /dev/null +++ b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-eabi-mvf0-scratch-ieee754.patch @@ -0,0 +1,89 @@ +Don't try to copy results into an FPA register when compiling for Maverick + +diff -urN gcc-4.3.0/gcc/config/arm-original/arm/ieee754-df.S gcc-4.3.0/gcc/config/arm/ieee754-df.S +--- gcc-4.3.0/gcc/config/arm-original/arm/ieee754-df.S 2008-02-19 14:32:15.000000000 +1000 ++++ gcc-4.3.0/gcc/config/arm/ieee754-df.S 2008-04-10 16:38:45.000000000 +1000 +@@ -500,7 +500,7 @@ + ARM_FUNC_ALIAS aeabi_ul2d floatundidf + + orrs r2, r0, r1 +-#if !defined (__VFP_FP__) && !defined(__SOFTFP__) ++#if !defined (__VFP_FP__) && !defined (__MAVERICK__) && !defined(__SOFTFP__) + do_it eq, t + mvfeqd f0, #0.0 + #else +@@ -508,7 +508,7 @@ + #endif + RETc(eq) + +-#if !defined (__VFP_FP__) && !defined(__SOFTFP__) ++#if !defined (__VFP_FP__) && !defined (__MAVERICK__) && !defined(__SOFTFP__) + @ For hard FPA code we want to return via the tail below so that + @ we can return the result in f0 as well as in r0/r1 for backwards + @ compatibility. +@@ -526,7 +526,7 @@ + ARM_FUNC_ALIAS aeabi_l2d floatdidf + + orrs r2, r0, r1 +-#if !defined (__VFP_FP__) && !defined(__SOFTFP__) ++#if !defined (__VFP_FP__) && !defined (__MAVERICK__) && !defined(__SOFTFP__) + do_it eq, t + mvfeqd f0, #0.0 + #else +@@ -534,7 +534,7 @@ + #endif + RETc(eq) + +-#if !defined (__VFP_FP__) && !defined(__SOFTFP__) ++#if !defined (__VFP_FP__) && !defined (__MAVERICK__) && !defined(__SOFTFP__) + @ For hard FPA code we want to return via the tail below so that + @ we can return the result in f0 as well as in r0/r1 for backwards + @ compatibility. +@@ -586,7 +586,7 @@ + add r4, r4, r2 + b LSYM(Lad_p) + +-#if !defined (__VFP_FP__) && !defined(__SOFTFP__) ++#if !defined (__VFP_FP__) && !defined (__MAVERICK__) && !defined(__SOFTFP__) + + @ Legacy code expects the result to be returned in f0. Copy it + @ there as well. +diff -urN gcc-4.3.0/gcc/config/arm-original/arm/ieee754-sf.S gcc-4.3.0/gcc/config/arm/ieee754-sf.S +--- gcc-4.3.0/gcc/config/arm-original/arm/ieee754-sf.S 2008-02-19 14:32:15.000000000 +1000 ++++ gcc-4.3.0/gcc/config/arm/ieee754-sf.S 2008-04-10 16:39:15.000000000 +1000 +@@ -330,7 +330,7 @@ + ARM_FUNC_ALIAS aeabi_ul2f floatundisf + + orrs r2, r0, r1 +-#if !defined (__VFP_FP__) && !defined(__SOFTFP__) ++#if !defined (__VFP_FP__) && !defined (__MAVERICK__) && !defined(__SOFTFP__) + do_it eq, t + mvfeqs f0, #0.0 + #else +@@ -345,7 +345,7 @@ + ARM_FUNC_ALIAS aeabi_l2f floatdisf + + orrs r2, r0, r1 +-#if !defined (__VFP_FP__) && !defined(__SOFTFP__) ++#if !defined (__VFP_FP__) && !defined (__MAVERICK__) && !defined(__SOFTFP__) + do_it eq, t + mvfeqs f0, #0.0 + #else +@@ -363,7 +363,7 @@ + rsc ah, ah, #0 + #endif + 1: +-#if !defined (__VFP_FP__) && !defined(__SOFTFP__) ++#if !defined (__VFP_FP__) && !defined (__MAVERICK__) && !defined(__SOFTFP__) + @ For hard FPA code we want to return via the tail below so that + @ we can return the result in f0 as well as in r0 for backwards + @ compatibility. +@@ -432,7 +432,7 @@ + biceq r0, r0, ip, lsr #31 + RET + +-#if !defined (__VFP_FP__) && !defined(__SOFTFP__) ++#if !defined (__VFP_FP__) && !defined (__MAVERICK__) && !defined(__SOFTFP__) + + LSYM(f0_ret): + str r0, [sp, #-4]! diff --git a/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-fix-64bit-const-offsets.patch b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-fix-64bit-const-offsets.patch new file mode 100644 index 0000000000..e3d67013d4 --- /dev/null +++ b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-fix-64bit-const-offsets.patch @@ -0,0 +1,25 @@ +Fixup possible address offsets for constant double integers +also when using Maverick to handle 64-bit integers. + +--- gcc-4.3.2/gcc/config/arm/arm.c-original 2007-06-12 14:46:20.000000000 +1000 ++++ gcc-4.3.2/gcc/config/arm/arm.c 2007-06-12 14:48:06.000000000 +1000 +@@ -3815,7 +3815,8 @@ + + use_ldrd = (TARGET_LDRD + && (mode == DImode +- || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP)))); ++ || (mode == DFmode ++ && (TARGET_SOFT_FLOAT || TARGET_VFP || TARGET_MAVERICK)))); + + if (code == POST_INC || code == PRE_DEC + || ((code == PRE_INC || code == POST_DEC) +@@ -4424,7 +4424,8 @@ + /* VFP addressing modes actually allow greater offsets, but for + now we just stick with the lowest common denominator. */ + if (mode == DImode +- || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode)) ++ || (mode == DFmode ++ && (TARGET_SOFT_FLOAT || TARGET_VFP || TARGET_MAVERICK))) + { + low_n = n & 0x0f; + n &= ~0x0f; diff --git a/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-fix-cirrus-reorg5.patch b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-fix-cirrus-reorg5.patch new file mode 100644 index 0000000000..313b7001bd --- /dev/null +++ b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-fix-cirrus-reorg5.patch @@ -0,0 +1,313 @@ +This patch: +- maps branch-cirrus_insn to branch-nop-nop-cirrus_insn +- maps branch-noncirrus-cirrus to branch-noncirrus-nop-cirrus +- inserts a nop in load rN - load/store64 mvX,[rN] sequences to avoid an + undocumented hardware bug. +- always fixes up invalid code sequences when compiling hard Maverick insns + and removes the -mcirrus-fix-invalid-insns flag because chip development + has stopped and all existing silicon has these bugs, while the extra code + that claimed to do other things for the extra bugs in the old revision D0 + silicon was complete junk. +- Takes the cirrus checking out of the main arm_reorg loop, to remove the + speed penalty it caused when not compiling for Maverick. + + Martin Guy 3 March 2009 + +--- gcc-4.3.2/gcc/config/arm/arm.c.orig 2009-02-18 14:59:22.000000000 +0000 ++++ gcc-4.3.2/gcc/config/arm/arm.c 2009-03-10 09:32:31.000000000 +0000 +@@ -134,7 +134,7 @@ + static int arm_address_cost (rtx); + static bool arm_memory_load_p (rtx); + static bool arm_cirrus_insn_p (rtx); +-static void cirrus_reorg (rtx); ++static void cirrus_reorg (void); + static void arm_init_builtins (void); + static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); + static void arm_init_iwmmxt_builtins (void); +@@ -6580,122 +6580,122 @@ + + /* Cirrus reorg for invalid instruction combinations. */ + static void +-cirrus_reorg (rtx first) ++cirrus_reorg (void) + { +- enum attr_cirrus attr; +- rtx body = PATTERN (first); +- rtx t; +- int nops; +- +- /* Any branch must be followed by 2 non Cirrus instructions. */ +- if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN) +- { +- nops = 0; +- t = next_nonnote_insn (first); +- +- if (arm_cirrus_insn_p (t)) +- ++ nops; +- +- if (arm_cirrus_insn_p (next_nonnote_insn (t))) +- ++ nops; +- +- while (nops --) +- emit_insn_after (gen_nop (), first); +- +- return; +- } +- +- /* (float (blah)) is in parallel with a clobber. */ +- if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) +- body = XVECEXP (body, 0, 0); +- +- if (GET_CODE (body) == SET) +- { +- rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1); +- +- /* cfldrd, cfldr64, cfstrd, cfstr64 must +- be followed by a non Cirrus insn. */ +- if (get_attr_cirrus (first) == CIRRUS_DOUBLE) +- { +- if (arm_cirrus_insn_p (next_nonnote_insn (first))) +- emit_insn_after (gen_nop (), first); ++ rtx insn, body; + +- return; +- } +- else if (arm_memory_load_p (first)) +- { +- unsigned int arm_regno; ++ /* Examine every instruc