From 7286737587f0097d033db3d91ba0e4570ea17b0b Mon Sep 17 00:00:00 2001 From: Koen Kooi Date: Tue, 8 Sep 2009 12:10:01 +0200 Subject: u-boot git: add support for omap3517-evm --- conf/machine/omap3517-evm.conf | 2 +- .../0001-Changes-for-making-a-NAND-build.patch | 50 + .../0002-Fix-for-NFS-boot-for-OMAP3-EVM.patch | 55 + ...-handling-to-1ms-tick-and-CONFIG_SYS_HZ-t.patch | 277 +++ ...tch-for-NFS-boot-to-fix-comments-provided.patch | 53 + .../0005-SMC911x-driver-fixed-for-NFS-boot.patch | 61 + .../0006-Added-OMAP3517-3505-support.patch | 2501 ++++++++++++++++++++ ...MAP3517TEB-validated-on-OMAP3517TEB-board.patch | 403 ++++ ...E-ALPHA-validated-on-OMAP3517PRE_ALPHA-bo.patch | 126 + ...09-OMAP3517PRE-ALPHA-DDR-size-issue-fixed.patch | 125 + ...RE-ALPHA-Mux-configuration-for-MMC-CD-and.patch | 34 + ...-driver-functional-no-need-for-time-delay.patch | 488 ++++ ...AC-driver-Implement-GPIO-driven-PHY-reset.patch | 319 +++ .../0013-Cleaned-up-during-EVM-hang-issue.patch | 45 + ...-EMAC-driver-cleanup-removed-debug-prints.patch | 419 ++++ ...r-Check-for-link-status-in-packet-send-lo.patch | 42 + ...g-option-and-name-changed-to-omap3517_evm.patch | 750 ++++++ recipes/u-boot/u-boot_git.bb | 22 + 18 files changed, 5771 insertions(+), 1 deletion(-) create mode 100644 recipes/u-boot/u-boot-git/omap3evm/0001-Changes-for-making-a-NAND-build.patch create mode 100644 recipes/u-boot/u-boot-git/omap3evm/0002-Fix-for-NFS-boot-for-OMAP3-EVM.patch create mode 100644 recipes/u-boot/u-boot-git/omap3evm/0003-OMAP3-timer-handling-to-1ms-tick-and-CONFIG_SYS_HZ-t.patch create mode 100644 recipes/u-boot/u-boot-git/omap3evm/0004-Reverse-patch-for-NFS-boot-to-fix-comments-provided.patch create mode 100644 recipes/u-boot/u-boot-git/omap3evm/0005-SMC911x-driver-fixed-for-NFS-boot.patch create mode 100644 recipes/u-boot/u-boot-git/omap3evm/0006-Added-OMAP3517-3505-support.patch create mode 100644 recipes/u-boot/u-boot-git/omap3evm/0007-OMAP3517TEB-validated-on-OMAP3517TEB-board.patch create mode 100644 recipes/u-boot/u-boot-git/omap3evm/0008-OMAP3517PRE-ALPHA-validated-on-OMAP3517PRE_ALPHA-bo.patch create mode 100644 recipes/u-boot/u-boot-git/omap3evm/0009-OMAP3517PRE-ALPHA-DDR-size-issue-fixed.patch create mode 100644 recipes/u-boot/u-boot-git/omap3evm/0010-OMAP3517PRE-ALPHA-Mux-configuration-for-MMC-CD-and.patch create mode 100644 recipes/u-boot/u-boot-git/omap3evm/0011-Ethernet-driver-functional-no-need-for-time-delay.patch create mode 100644 recipes/u-boot/u-boot-git/omap3evm/0012-EMAC-driver-Implement-GPIO-driven-PHY-reset.patch create mode 100644 recipes/u-boot/u-boot-git/omap3evm/0013-Cleaned-up-during-EVM-hang-issue.patch create mode 100644 recipes/u-boot/u-boot-git/omap3evm/0014-EMAC-driver-cleanup-removed-debug-prints.patch create mode 100644 recipes/u-boot/u-boot-git/omap3evm/0015-EMAC-driver-Check-for-link-status-in-packet-send-lo.patch create mode 100644 recipes/u-boot/u-boot-git/omap3evm/0016-Config-option-and-name-changed-to-omap3517_evm.patch diff --git a/conf/machine/omap3517-evm.conf b/conf/machine/omap3517-evm.conf index 5552681d12..a7ef4be0fd 100644 --- a/conf/machine/omap3517-evm.conf +++ b/conf/machine/omap3517-evm.conf @@ -26,7 +26,7 @@ SERIAL_CONSOLE = "115200 ttyS0" PREFERRED_PROVIDER_virtual/kernel = "linux-omap-psp" UBOOT_ARCH = "arm" -UBOOT_MACHINE = "omap3_evm_config" +UBOOT_MACHINE = "omap3517_evm_config" MACHINE_FEATURES = "kernel26 apm usbgadget usbhost vfat ext2 screen touchscreen ethernet" diff --git a/recipes/u-boot/u-boot-git/omap3evm/0001-Changes-for-making-a-NAND-build.patch b/recipes/u-boot/u-boot-git/omap3evm/0001-Changes-for-making-a-NAND-build.patch new file mode 100644 index 0000000000..b762ac0f1e --- /dev/null +++ b/recipes/u-boot/u-boot-git/omap3evm/0001-Changes-for-making-a-NAND-build.patch @@ -0,0 +1,50 @@ +From d58014b0e26652eac04f9799e14640854f7885a8 Mon Sep 17 00:00:00 2001 +From: Manikandan Pillai +Date: Tue, 7 Apr 2009 14:26:41 +0530 +Subject: [PATCH 01/16] Changes for making a NAND build. + +--- + include/configs/omap3_evm.h | 7 +++++-- + 1 files changed, 5 insertions(+), 2 deletions(-) + +diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h +index f4498a9..6283d59 100644 +--- a/include/configs/omap3_evm.h ++++ b/include/configs/omap3_evm.h +@@ -106,7 +106,7 @@ + + #define CONFIG_CMD_I2C /* I2C serial bus support */ + #define CONFIG_CMD_MMC /* MMC support */ +-#define CONFIG_CMD_ONENAND /* ONENAND support */ ++#define CONFIG_CMD_NAND /* NAND support */ + #define CONFIG_CMD_DHCP + #define CONFIG_CMD_PING + +@@ -125,12 +125,15 @@ + /* + * Board NAND Info. + */ ++#define CONFIG_NAND_OMAP_GPMC + #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ + #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access */ + /* nand at CS0 */ + ++#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 ++ + #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ + /* NAND devices */ + #define SECTORSIZE 512 +@@ -271,7 +274,7 @@ + #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP + +-#define CONFIG_ENV_IS_IN_ONENAND 1 ++#define CONFIG_ENV_IS_IN_NAND 1 + #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ + #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +-- +1.6.2.4 + diff --git a/recipes/u-boot/u-boot-git/omap3evm/0002-Fix-for-NFS-boot-for-OMAP3-EVM.patch b/recipes/u-boot/u-boot-git/omap3evm/0002-Fix-for-NFS-boot-for-OMAP3-EVM.patch new file mode 100644 index 0000000000..243f175728 --- /dev/null +++ b/recipes/u-boot/u-boot-git/omap3evm/0002-Fix-for-NFS-boot-for-OMAP3-EVM.patch @@ -0,0 +1,55 @@ +From 57a0438b9f70bb3e98a20773134b17ef33e266b9 Mon Sep 17 00:00:00 2001 +From: Manikandan Pillai +Date: Tue, 7 Apr 2009 14:27:31 +0530 +Subject: [PATCH 02/16] Fix for NFS boot for OMAP3 EVM + +The eth_halt() function has been modified to remove the +chip reset and instead stop the transmit/receive from the device. +--- + drivers/net/smc911x.c | 23 ++++++++++++++++++++++- + 1 files changed, 22 insertions(+), 1 deletions(-) + +diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c +index 1ded8f0..2f0852e 100644 +--- a/drivers/net/smc911x.c ++++ b/drivers/net/smc911x.c +@@ -116,6 +116,27 @@ static int smc911x_phy_reset(void) + return 0; + } + ++static void smc911x_shutdown(void) ++{ ++ unsigned cr; ++ ++ /* Turn of Rx and TX */ ++ cr = smc911x_get_mac_csr(MAC_CR); ++ cr &= ~(MAC_CR_TXEN | MAC_CR_RXEN | MAC_CR_HBDIS); ++ smc911x_set_mac_csr(MAC_CR, cr); ++ ++ /* Stop Transmission */ ++ cr = smc911x_get_mac_csr(TX_CFG); ++ cr &= ~(TX_CFG_STOP_TX); ++ smc911x_set_mac_csr(TX_CFG, cr); ++ /* Stop receiving packets */ ++ cr = smc911x_get_mac_csr(RX_CFG); ++ cr &= ~(RX_CFG_RXDOFF); ++ smc911x_set_mac_csr(RX_CFG, cr); ++ ++} ++ ++ + static void smc911x_phy_configure(void) + { + int timeout; +@@ -224,7 +245,7 @@ int eth_send(volatile void *packet, int length) + + void eth_halt(void) + { +- smc911x_reset(); ++ smc911x_shutdown(); + } + + int eth_rx(void) +-- +1.6.2.4 + diff --git a/recipes/u-boot/u-boot-git/omap3evm/0003-OMAP3-timer-handling-to-1ms-tick-and-CONFIG_SYS_HZ-t.patch b/recipes/u-boot/u-boot-git/omap3evm/0003-OMAP3-timer-handling-to-1ms-tick-and-CONFIG_SYS_HZ-t.patch new file mode 100644 index 0000000000..75f7ef230a --- /dev/null +++ b/recipes/u-boot/u-boot-git/omap3evm/0003-OMAP3-timer-handling-to-1ms-tick-and-CONFIG_SYS_HZ-t.patch @@ -0,0 +1,277 @@ +From 13fc02c66aa4cc1c5653a4987fdddce63810a7e9 Mon Sep 17 00:00:00 2001 +From: Manikandan Pillai +Date: Tue, 7 Apr 2009 14:28:05 +0530 +Subject: [PATCH 03/16] OMAP3 timer handling to 1ms tick and CONFIG_SYS_HZ to 1000. + +Clean up macros and comments. +--- + cpu/arm_cortexa8/omap3/interrupts.c | 81 ++++++++++------------------------ + examples/Makefile | 2 +- + include/configs/omap3_beagle.h | 11 +++-- + include/configs/omap3_evm.h | 13 +++--- + include/configs/omap3_overo.h | 10 ++-- + include/configs/omap3_pandora.h | 11 ++--- + include/configs/omap3_zoom1.h | 11 ++--- + 7 files changed, 52 insertions(+), 87 deletions(-) + +diff --git a/cpu/arm_cortexa8/omap3/interrupts.c b/cpu/arm_cortexa8/omap3/interrupts.c +index 9e9817d..b99e284 100644 +--- a/cpu/arm_cortexa8/omap3/interrupts.c ++++ b/cpu/arm_cortexa8/omap3/interrupts.c +@@ -169,7 +169,16 @@ static ulong timestamp; + static ulong lastinc; + static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE; + +-/* nothing really to do with interrupts, just starts up a counter. */ ++/* ++ * Nothing really to do with interrupts, just starts up a counter. ++ * We run the counter with 13MHz, divided by 8, resulting in timer ++ * frequency of 1.625MHz. With 32bit counter register, counter ++ * overflows in ~44min ++ */ ++ ++/* 13MHz / 8 = 1.625MHz */ ++#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PVT)) ++ + int interrupt_init(void) + { + /* start the counter ticking up, reload value on overflow */ +@@ -204,78 +213,38 @@ void set_timer(ulong t) + /* delay x useconds AND perserve advance timstamp value */ + void udelay(unsigned long usec) + { +- ulong tmo, tmp; +- +- /* if "big" number, spread normalization to seconds */ +- if (usec >= 1000) { +- /* if "big" number, spread normalization to seconds */ +- tmo = usec / 1000; +- /* find number of "ticks" to wait to achieve target */ +- tmo *= CONFIG_SYS_HZ; +- tmo /= 1000; /* finish normalize. */ +- } else {/* else small number, don't kill it prior to HZ multiply */ +- tmo = usec * CONFIG_SYS_HZ; +- tmo /= (1000 * 1000); +- } +- +- tmp = get_timer(0); /* get current timestamp */ +- /* if setting this forward will roll time stamp */ +- if ((tmo + tmp + 1) < tmp) +- /* reset "advancing" timestamp to 0, set lastinc value */ +- reset_timer_masked(); +- else +- tmo += tmp; /* else, set advancing stamp wake up time */ +- while (get_timer_masked() < tmo) /* loop till event */ +- /*NOP*/; ++ ulong tmo, endtime; ++ ++ tmo = usec * (TIMER_CLOCK / CONFIG_SYS_HZ); ++ tmo /= 1000; ++ ++ endtime = readl(&timer_base->tcrr) + tmo; ++ ++ while (readl(&timer_base->tcrr) < endtime); + } + + void reset_timer_masked(void) + { + /* reset time, capture current incrementer value time */ +- lastinc = readl(&timer_base->tcrr); ++ lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); + timestamp = 0; /* start "advancing" time stamp from 0 */ + } + + ulong get_timer_masked(void) + { +- ulong now = readl(&timer_base->tcrr); /* current tick value */ ++ /* current tick value */ ++ ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); + + if (now >= lastinc) /* normal mode (non roll) */ + /* move stamp fordward with absoulte diff ticks */ + timestamp += (now - lastinc); + else /* we have rollover of incrementer */ +- timestamp += (0xFFFFFFFF - lastinc) + now; ++ timestamp += ((0xFFFFFFFF / (TIMER_CLOCK / CONFIG_SYS_HZ)) ++ - lastinc) + now; + lastinc = now; + return timestamp; + } + +-/* waits specified delay value and resets timestamp */ +-void udelay_masked(unsigned long usec) +-{ +- ulong tmo; +- ulong endtime; +- signed long diff; +- +- /* if "big" number, spread normalization to seconds */ +- if (usec >= 1000) { +- /* start to normalize for usec to ticks per sec */ +- tmo = usec / 1000; +- /* find number of "ticks" to wait to achieve target */ +- tmo *= CONFIG_SYS_HZ; +- tmo /= 1000; /* finish normalize. */ +- } else { /* else small number, */ +- /* don't kill it prior to HZ multiply */ +- tmo = usec * CONFIG_SYS_HZ; +- tmo /= (1000 * 1000); +- } +- endtime = get_timer_masked() + tmo; +- +- do { +- ulong now = get_timer_masked(); +- diff = endtime - now; +- } while (diff >= 0); +-} +- + /* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. +@@ -291,7 +260,5 @@ unsigned long long get_ticks(void) + */ + ulong get_tbclk(void) + { +- ulong tbclk; +- tbclk = CONFIG_SYS_HZ; +- return tbclk; ++ return CONFIG_SYS_HZ; + } +diff --git a/examples/Makefile b/examples/Makefile +index dbcfa92..d2e811a 100644 +--- a/examples/Makefile ++++ b/examples/Makefile +@@ -33,7 +33,7 @@ ifeq ($(ARCH),arm) + ifeq ($(BOARD),omap2420h4) + LOAD_ADDR = 0x80300000 + else +-ifeq ($(CPU),omap3) ++ifeq ($(SOC),omap3) + LOAD_ADDR = 0x80300000 + else + LOAD_ADDR = 0xc100000 +diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h +index 9057606..2f30783 100644 +--- a/include/configs/omap3_beagle.h ++++ b/include/configs/omap3_beagle.h +@@ -220,14 +220,15 @@ + /* load address */ + + /* +- * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by +- * 32KHz clk, or from external sig. This rate is divided by a local divisor. ++ * OMAP3 has 12 GP timers, they can be driven by the system clock ++ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). ++ * This rate is divided by a local divisor. + */ +-#define V_PVT 7 + + #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +-#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ +-#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) ++#define CONFIG_SYS_PVT 2 /* Divisor: 2^(PVT+1) => 8 */ ++#define CONFIG_SYS_HZ 1000 ++ + + /*----------------------------------------------------------------------- + * Stack sizes +diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h +index 6283d59..fb8a424 100644 +--- a/include/configs/omap3_evm.h ++++ b/include/configs/omap3_evm.h +@@ -222,14 +222,13 @@ + /* address */ + + /* +- * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by +- * 32KHz clk, or from external sig. This rate is divided by a local divisor. ++ * OMAP3 has 12 GP timers, they can be driven by the system clock ++ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). ++ * This rate is divided by a local divisor. + */ +-#define V_PVT 7 +- +-#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +-#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ +-#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) ++#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) ++#define CONFIG_SYS_PVT 2 /* Divisor: 2^(PVT+1) => 8 */ ++#define CONFIG_SYS_HZ 1000 + + /*----------------------------------------------------------------------- + * Stack sizes +diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h +index dee0417..45e5478 100644 +--- a/include/configs/omap3_overo.h ++++ b/include/configs/omap3_overo.h +@@ -213,14 +213,14 @@ + /* address */ + + /* +- * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by +- * 32KHz clk, or from external sig. This rate is divided by a local divisor. ++ * OMAP3 has 12 GP timers, they can be driven by the system clock ++ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). ++ * This rate is divided by a local divisor. + */ +-#define V_PVT 7 + + #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +-#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ +-#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) ++#define CONFIG_SYS_PVT 2 /* Divisor: 2^(PVT+1) => 8 */ ++#define CONFIG_SYS_HZ 1000 + + /*----------------------------------------------------------------------- + * Stack sizes +diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h +index 00c0374..4ed8373 100644 +--- a/include/configs/omap3_pandora.h ++++ b/include/configs/omap3_pandora.h +@@ -215,14 +215,13 @@ + /* address */ + + /* +- * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by +- * 32KHz clk, or from external sig. This rate is divided by a local divisor. ++ * OMAP3 has 12 GP timers, they can be driven by the system clock ++ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). ++ * This rate is divided by a local divisor. + */ +-#define V_PVT 7 +- + #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +-#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ +-#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) ++#define CONFIG_SYS_PVT 2 /* Divisor: 2^(PVT+1) => 8 */ ++#define CONFIG_SYS_HZ 1000 + + /*----------------------------------------------------------------------- + * Stack sizes +diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h +index f8ae163..0185fa6 100644 +--- a/include/configs/omap3_zoom1.h ++++ b/include/configs/omap3_zoom1.h +@@ -222,14 +222,13 @@ + /* load address */ + + /* +- * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by +- * 32KHz clk, or from external sig. This rate is divided by a local divisor. ++ * OMAP3 has 12 GP timers, they can be driven by the system clock ++ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). ++ * This rate is divided by a local divisor. + */ +-#define V_PVT 7 +- + #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +-#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ +-#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) ++#define CONFIG_SYS_PVT 2 /* Divisor: 2^(PVT+1) => 8 */ ++#define CONFIG_SYS_HZ 1000 + + /*----------------------------------------------------------------------- + * Stack sizes +-- +1.6.2.4 + diff --git a/recipes/u-boot/u-boot-git/omap3evm/0004-Reverse-patch-for-NFS-boot-to-fix-comments-provided.patch b/recipes/u-boot/u-boot-git/omap3evm/0004-Reverse-patch-for-NFS-boot-to-fix-comments-provided.patch new file mode 100644 index 0000000000..8ce6ac9602 --- /dev/null +++ b/recipes/u-boot/u-boot-git/omap3evm/0004-Reverse-patch-for-NFS-boot-to-fix-comments-provided.patch @@ -0,0 +1,53 @@ +From 515c1e71f21e6666d8f8da7a539d6edd122a0fc3 Mon Sep 17 00:00:00 2001 +From: Manikandan Pillai +Date: Wed, 8 Apr 2009 09:03:10 +0530 +Subject: [PATCH 04/16] Reverse patch for NFS boot to fix comments provided by community + +--- + drivers/net/smc911x.c | 23 +---------------------- + 1 files changed, 1 insertions(+), 22 deletions(-) + +diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c +index 2f0852e..1ded8f0 100644 +--- a/drivers/net/smc911x.c ++++ b/drivers/net/smc911x.c +@@ -116,27 +116,6 @@ static int smc911x_phy_reset(void) + return 0; + } + +-static void smc911x_shutdown(void) +-{ +- unsigned cr; +- +- /* Turn of Rx and TX */ +- cr = smc911x_get_mac_csr(MAC_CR); +- cr &= ~(MAC_CR_TXEN | MAC_CR_RXEN | MAC_CR_HBDIS); +- smc911x_set_mac_csr(MAC_CR, cr); +- +- /* Stop Transmission */ +- cr = smc911x_get_mac_csr(TX_CFG); +- cr &= ~(TX_CFG_STOP_TX); +- smc911x_set_mac_csr(TX_CFG, cr); +- /* Stop receiving packets */ +- cr = smc911x_get_mac_csr(RX_CFG); +- cr &= ~(RX_CFG_RXDOFF); +- smc911x_set_mac_csr(RX_CFG, cr); +- +-} +- +- + static void smc911x_phy_configure(void) + { + int timeout; +@@ -245,7 +224,7 @@ int eth_send(volatile void *packet, int length) + + void eth_halt(void) + { +- smc911x_shutdown(); ++ smc911x_reset(); + } + + int eth_rx(void) +-- +1.6.2.4 + diff --git a/recipes/u-boot/u-boot-git/omap3evm/0005-SMC911x-driver-fixed-for-NFS-boot.patch b/recipes/u-boot/u-boot-git/omap3evm/0005-SMC911x-driver-fixed-for-NFS-boot.patch new file mode 100644 index 0000000000..8b3894bc3f --- /dev/null +++ b/recipes/u-boot/u-boot-git/omap3evm/0005-SMC911x-driver-fixed-for-NFS-boot.patch @@ -0,0 +1,61 @@ +From 3ffa2549a4f61053f78c00b8716cda392cf97b93 Mon Sep 17 00:00:00 2001 +From: Manikandan Pillai +Date: Wed, 8 Apr 2009 09:08:00 +0530 +Subject: [PATCH 05/16] SMC911x driver fixed for NFS boot + +eth_halt() function in the smc911x drivers used to call the +smc911x_reset() function. eth_halt() used to be called after +tftp transfers. This used to put the ethernet chip in reset +while the linux boots up resulting in the ethernet driver +not coming up. NFS boot used to fail as a result. + +This patch calls smc911x_shutdown() instead of smc911x_reset(). +Some comments received has also been fixed. +--- + drivers/net/smc911x.c | 23 ++++++++++++++++++++++- + 1 files changed, 22 insertions(+), 1 deletions(-) + +diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c +index 1ded8f0..5bc3914 100644 +--- a/drivers/net/smc911x.c ++++ b/drivers/net/smc911x.c +@@ -116,6 +116,27 @@ static int smc911x_phy_reset(void) + return 0; + } + ++static void smc911x_shutdown(void) ++{ ++ unsigned int cr; ++ ++ /* Turn of Rx and TX */ ++ cr = smc911x_get_mac_csr(MAC_CR); ++ cr &= ~(MAC_CR_TXEN | MAC_CR_RXEN | MAC_CR_HBDIS); ++ smc911x_set_mac_csr(MAC_CR, cr); ++ ++ /* Stop Transmission */ ++ cr = smc911x_get_mac_csr(TX_CFG); ++ cr &= ~(TX_CFG_STOP_TX); ++ smc911x_set_mac_csr(TX_CFG, cr); ++ /* Stop receiving packets */ ++ cr = smc911x_get_mac_csr(RX_CFG); ++ cr &= ~(RX_CFG_RXDOFF); ++ smc911x_set_mac_csr(RX_CFG, cr); ++ ++} ++ ++ + static void smc911x_phy_configure(void) + { + int timeout; +@@ -224,7 +245,7 @@ int eth_send(volatile void *packet, int length) + + void eth_halt(void) + { +- smc911x_reset(); ++ smc911x_shutdown(); + } + + int eth_rx(void) +-- +1.6.2.4 + diff --git a/recipes/u-boot/u-boot-git/omap3evm/0006-Added-OMAP3517-3505-support.patch b/recipes/u-boot/u-boot-git/omap3evm/0006-Added-OMAP3517-3505-support.patch new file mode 100644 index 0000000000..326679af78 --- /dev/null +++ b/recipes/u-boot/u-boot-git/omap3evm/0006-Added-OMAP3517-3505-support.patch @@ -0,0 +1,2501 @@ +From 4144e9f85d1b0e48732c80b05bc380ae6d2af6d8 Mon Sep 17 00:00:00 2001 +From: Vaibhav Hiremath +Date: Sat, 13 Jun 2009 00:47:34 +0530 +Subject: [PATCH 06/16] Added OMAP3517/3505 support + +Added support for OMAP3517/3505 SoC, it includes all the changes +from Mani's commit for OMAP3517 and review comments fix. + +Major features/changes - + - New config file + - New board files + - New ethernet driver + +Major Review comments - + - Added macine ID for OMAP3517 + - Naming conventions used. +--- + Makefile | 3 + + board/omap3/omap3517evm/Makefile | 47 +++ + board/omap3/omap3517evm/config.mk | 33 ++ + board/omap3/omap3517evm/omap3517evm.c | 124 ++++++ + board/omap3/omap3517evm/omap3517evm.h | 392 ++++++++++++++++++ + board/omap3/omap3517evm/u-boot.lds | 63 +++ + cpu/arm_cortexa8/omap3/board.c | 8 + + cpu/arm_cortexa8/omap3/clock.c | 4 + + cpu/arm_cortexa8/omap3/mem.c | 110 +++++ + drivers/net/Makefile | 1 + + drivers/net/ticpgmac.c | 693 ++++++++++++++++++++++++++++++++ + include/asm-arm/arch-omap3/cpu.h | 26 ++ + include/asm-arm/arch-omap3/mux.h | 41 ++ + include/asm-arm/arch-omap3/sys_proto.h | 1 + + include/asm-arm/arch-omap3/ticpgmac.h | 340 ++++++++++++++++ + include/asm-arm/mach-types.h | 1 + + include/configs/omap3517evm.h | 349 ++++++++++++++++ + lib_arm/board.c | 4 +- + net/eth.c | 4 +- + 19 files changed, 2240 insertions(+), 4 deletions(-) + create mode 100644 board/omap3/omap3517evm/Makefile + create mode 100644 board/omap3/omap3517evm/config.mk + create mode 100644 board/omap3/omap3517evm/omap3517evm.c + create mode 100644 board/omap3/omap3517evm/omap3517evm.h + create mode 100644 board/omap3/omap3517evm/u-boot.lds + create mode 100644 drivers/net/ticpgmac.c + create mode 100644 include/asm-arm/arch-omap3/ticpgmac.h + create mode 100644 include/configs/omap3517evm.h + +diff --git a/Makefile b/Makefile +index 61bae6d..df25fb3 100644 +--- a/Makefile ++++ b/Makefile +@@ -2942,6 +2942,9 @@ omap3_pandora_config : unconfig + omap3_zoom1_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom1 omap3 omap3 + ++omap3517evm_config : unconfig ++ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 omap3517evm omap3 omap3 ++ + ######################################################################### + ## XScale Systems + ######################################################################### +diff --git a/board/omap3/omap3517evm/Makefile b/board/omap3/omap3517evm/Makefile +new file mode 100644 +index 0000000..8f6d10e +--- /dev/null ++++ b/board/omap3/omap3517evm/Makefile +@@ -0,0 +1,47 @@ ++# ++# (C) Copyright 2000, 2001, 2002 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).a ++ ++COBJS := omap3517evm.o ++ ++SRCS := $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) ++ $(AR) $(ARFLAGS) $@ $(OBJS) ++ ++clean: ++ rm -f $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak $(obj).depend ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend +diff --git a/board/omap3/omap3517evm/config.mk b/board/omap3/omap3517evm/config.mk +new file mode 100644 +index 0000000..4d873eb +--- /dev/null ++++ b/board/omap3/omap3517evm/config.mk +@@ -0,0 +1,33 @@ ++# ++# (C) Copyright 2006 - 2008 ++# Texas Instruments, ++# ++# EVM uses OMAP3 (ARM-CortexA8) cpu ++# see http://www.ti.com/ for more information on Texas Instruments ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++# Physical Address: ++# 8000'0000 (bank0) ++# A000/0000 (bank1) ++# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 ++# (mem base + reserved) ++ ++# For use with external or internal boots. ++TEXT_BASE = 0x80e80000 +diff --git a/board/omap3/omap3517evm/omap3517evm.c b/board/omap3/omap3517evm/omap3517evm.c +new file mode 100644 +index 0000000..2330776 +--- /dev/null ++++ b/board/omap3/omap3517evm/omap3517evm.c +@@ -0,0 +1,124 @@ ++/* ++ * (C) Copyright 2004-2008 ++ * Texas Instruments, ++ * ++ * Author : ++ * Manikandan Pillai ++ * ++ * Derived from Beagle Board and 3430 SDP code by ++ * Richard Woodruff ++ * Syed Mohammed Khasim ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "omap3517evm.h" ++ ++/****************************************************************************** ++ * Routine: board_init ++ * Description: Early hardware init. ++ *****************************************************************************/ ++int board_init(void) ++{ ++ DECLARE_GLOBAL_DATA_PTR; ++ ++ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ ++ /* board id for Linux */ ++ gd->bd->bi_arch_number = MACH_TYPE_OMAP3517EVM; ++ /* boot param addr */ ++ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); ++ ++ return 0; ++} ++ ++/****************************************************************************** ++ * Routine: misc_init_r ++ * Description: Init ethernet (done here so udelay works) ++ *****************************************************************************/ ++int misc_init_r(void) ++{ ++ ++#ifdef CONFIG_DRIVER_OMAP34XX_I2C ++ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); ++#endif ++ ++#if defined(CONFIG_CMD_NET) ++ setup_net_chip(); ++#endif ++ ++ dieid_num_r(); ++ ++ return 0; ++} ++ ++/****************************************************************************** ++ * Routine: set_muxconf_regs ++ * Description: Setting up the configuration Mux registers specific to the ++ * hardware. Many pins need to be moved from protect to primary ++ * mode. ++ *****************************************************************************/ ++void set_muxconf_regs(void) ++{ ++ MUX_OMAP3517EVM(); ++} ++ ++/****************************************************************************** ++ * Routine: setup_net_chip ++ * Description: Setting up the configuration GPMC registers specific to the ++ * Ethernet hardware. ++ *****************************************************************************/ ++static void setup_net_chip(void) ++{ ++ gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE; ++ gpmc_csx_t *gpmc_cs6_base = (gpmc_csx_t *)GPMC_CONFIG_CS6_BASE; ++ ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE; ++ ++ /* Configure GPMC registers */ ++ writel(NET_GPMC_CONFIG1, &gpmc_cs6_base->config1); ++ writel(NET_GPMC_CONFIG2, &gpmc_cs6_base->config2); ++ writel(NET_GPMC_CONFIG3, &gpmc_cs6_base->config3); ++ writel(NET_GPMC_CONFIG4, &gpmc_cs6_base->config4); ++ writel(NET_GPMC_CONFIG5, &gpmc_cs6_base->config5); ++ writel(NET_GPMC_CONFIG6, &gpmc_cs6_base->config6); ++ writel(NET_GPMC_CONFIG7, &gpmc_cs6_base->config7); ++ ++ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ ++ writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); ++ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ ++ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); ++ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ ++ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, ++ &ctrl_base->gpmc_nadv_ale); ++ ++ /* Make GPIO 64 as output pin */ ++ writel(readl(&gpio3_base->oe) & ~(GPIO0), &gpio3_base->oe); ++ ++ /* Now send a pulse on the GPIO pin */ ++ writel(GPIO0, &gpio3_base->setdataout); ++ udelay(1); ++ writel(GPIO0, &gpio3_base->cleardataout); ++ udelay(1); ++ writel(GPIO0, &gpio3_base->setdataout); ++} +diff --git a/board/omap3/omap3517evm/omap3517evm.h b/board/omap3/omap3517evm/omap3517evm.h +new file mode 100644 +index 0000000..aba53bf +--- /dev/null ++++ b/board/omap3/omap3517evm/omap3517evm.h +@@ -0,0 +1,392 @@ ++/* ++ * (C) Copyright 2008 ++ * Nishanth Menon ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++#ifndef _OMAP3517EVM_H_ ++#define _OMAP3517EVM_H_ ++ ++const omap3_sysinfo sysinfo = { ++ OMAP3EVM_V1, ++ OMAP3EVM_V2, ++ DDR_DISCRETE, ++ "OMAP3 omap3517evm board", ++ "NAND", ++}; ++ ++static void setup_net_chip(void); ++ ++/* ++ * IEN - Input Enable ++ * IDIS - Input Disable ++ * PTD - Pull type Down ++ * PTU - Pull type Up ++ * DIS - Pull type selection is inactive ++ * EN - Pull type selection is active ++ * M0 - Mode 0 ++ * The commented string gives the final mux configuration for that pin ++ */ ++#define MUX_OMAP3517EVM() \ ++ /*SDRC*/\ ++ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ ++ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ ++ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ ++ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ ++ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ ++ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ ++ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ ++ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ ++ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ ++ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ ++ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ ++ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ ++ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ ++ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ ++ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ ++ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ ++ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ ++ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ ++ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ ++ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ ++ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ ++ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ ++ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ ++ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ ++ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ ++ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ ++ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ ++ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ ++ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ ++ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ ++ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ ++ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ ++ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ ++ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ ++ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ ++ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ ++ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ ++ /*GPMC*/\ ++ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\ ++ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\ ++ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\ ++ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\ ++ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\ ++ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\ ++ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\ ++ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\ ++ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\ ++ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\ ++ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\ ++ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\ ++ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\ ++ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\ ++ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\ ++ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\ ++ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\ ++ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\ ++ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\ ++ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\ ++ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\ ++ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\ ++ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\ ++ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\ ++ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\ ++ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\ ++ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ ++ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ ++ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ ++ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ ++ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) /*GPMC_nCS4*/\ ++ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ ++ MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\ ++ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\ ++ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\ ++ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ ++ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ ++ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ ++ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) /*GPMC_nBE0_CLE*/\ ++ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) /*GPMC_nBE1*/\ ++ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ ++ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ ++ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ ++ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ ++ /* - ETH_nRESET*/\ ++ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\ ++ /*DSS*/\ ++ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ ++ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ ++ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ ++ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ ++ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ ++ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ ++ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ ++ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ ++ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ ++ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ ++ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ ++ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ ++ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ ++ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ ++ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ ++ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ ++ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ ++ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ ++ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ ++ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ ++ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ ++ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ ++ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ ++ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ ++ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ ++ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ ++ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ ++ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ ++ /*CAMERA*/\ ++ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\ ++ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\ ++ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ ++ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\ ++ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ ++ /* - CAM_RESET*/\ ++ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\ ++ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\ ++ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\ ++ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\ ++ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\ ++ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\ ++ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\ ++ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\ ++ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\ ++ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\ ++ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\ ++ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\ ++ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ ++ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ ++ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ ++ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ ++ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ ++ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ ++ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ ++ /*Audio Interface */\ ++ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ ++ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ ++ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ ++ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ ++ /*Expansion card */\ ++ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ ++ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ ++ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ ++ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ ++ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ ++ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ ++ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ ++ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ ++ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ ++ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ ++ /*Wireless LAN */\ ++ MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) /*MMC2_CLK*/\ ++ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ ++ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ ++ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ ++ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\ ++ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\ ++ MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M0)) /*MMC2_DAT4*/\ ++ MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M0)) /*MMC2_DAT5*/\ ++ MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M0)) /*MMC2_DAT6 */\ ++ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)) /*MMC2_DAT7*/\ ++ /*Bluetooth*/\ ++ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\ ++ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) /*McBSP3_DR*/\ ++ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /*McBSP3_CLKX */\ ++ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /*McBSP3_FSX*/\ ++ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\ ++ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ ++ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\ ++ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /*UART2_RX*/\ ++ /*Modem Interface */\ ++ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ ++ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ ++ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\ ++ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ ++ MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\ ++ /* - LCD_INI*/\ ++ MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\ ++ /* - LCD_ENVDD */\ ++ MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\ ++ /* - LCD_QVGA/nVGA */\ ++ MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\ ++ /* - LCD_RESB */\ ++ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /*MCBSP1_CLKR */\ ++ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) /*MCBSP1_FSR*/\ ++ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) /*MCBSP1_DX*/\ ++ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /*MCBSP1_DR*/\ ++ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*MCBSP_CLKS */\ ++ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) /*MCBSP1_FSX*/\ ++ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) /*MCBSP1_CLKX */\ ++ /*Serial Interface*/\ ++ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_*/\ ++ /* RCTX*/\ ++ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ ++ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ ++ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ ++ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ ++ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ ++ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ ++ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ ++ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\ ++ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\ ++ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\ ++ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\ ++ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\ ++ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\ ++ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\ ++ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\ ++ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ ++ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ ++ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ ++ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ ++ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ ++ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ ++ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ ++ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ ++ MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) /*HDQ_SIO*/\ ++ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\ ++ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\ ++ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\ ++ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ ++ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\ ++ /* TS_PEN_IRQ */\ ++ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\ ++ /* - LAN_INTR*/\ ++ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) /*McSPI1_CS3*/\ ++ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\ ++ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\ ++ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\ ++ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\ ++ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\ ++ /*Control and debug */\ ++ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ ++ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ ++ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ ++ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ ++ /* - PEN_IRQ */\ ++ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ ++ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\ ++ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ ++ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ ++ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ ++ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\ ++ /* - VIO_1V8*/\ ++ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ ++ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\ ++ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) /*SYS_CLKOUT2*/\ ++ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ ++ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ ++ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ ++ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ ++ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ ++ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ ++ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) /*ETK_CLK*/\ ++ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) /*ETK_CTL*/\ ++ MUX_VAL(CP(ETK_D0_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D0*/\ ++ MUX_VAL(CP(ETK_D1_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D1*/\ ++ MUX_VAL(CP(ETK_D2_ES2 ), (IEN | PTD | EN | M0)) /*ETK_D2*/\ ++ MUX_VAL(CP(ETK_D3_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D3*/\ ++ MUX_VAL(CP(ETK_D4_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D4*/\ ++ MUX_VAL(CP(ETK_D5_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D5*/\ ++ MUX_VAL(CP(ETK_D6_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D6*/\ ++ MUX_VAL(CP(ETK_D7_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D7*/\ ++ MUX_VAL(CP(ETK_D8_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D8*/\ ++ MUX_VAL(CP(ETK_D9_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D9*/\ ++ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) /*ETK_D10*/\ ++ MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) /*ETK_D11*/\ ++ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) /*ETK_D12*/\ ++ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) /*ETK_D13*/\ ++ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) /*ETK_D14*/\ ++ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) /*ETK_D15*/\ ++ /*Die to Die */\ ++ MUX_VAL(CP(CCDC_PCLK), (IEN | PTD | EN | M0)) /*ccdc_pclk*/\ ++ MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | EN | M0)) /*ccdc_field*/\ ++ MUX_VAL(CP(CCDC_HD), (IEN | PTD | EN | M0)) /*ccdc_hd*/\ ++ MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M0)) /*ccdc_vd*/\ ++ MUX_VAL(CP(CCDC_WEN), (IEN | PTD | EN | M0)) /*ccdc_wen*/\ ++ MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | EN | M0)) /*ccdc_data0*/\ ++ MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | EN | M0)) /*ccdc_data1*/\ ++ MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | EN | M0)) /*ccdc_data2*/\ ++ MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | EN | M0)) /*ccdc_data3*/\ ++ MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | EN | M0)) /*ccdc_data4*/\ ++ MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | EN | M0)) /*ccdc_data5*/\ ++ MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | EN | M0)) /*ccdc_data6*/\ ++ MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | EN | M0)) /*ccdc_data7*/\ ++ MUX_VAL(CP(RMII_MDIO_DATA), (IEN | PTD | EN | M0)) /*rmii_mdio_data*/\ ++ MUX_VAL(CP(RMII_MDIO_CLK), (IEN | PTD | EN | M0)) /*rmii_mdio_clk*/\ ++ MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | EN | M0)) /*rmii_rxd0*/\ ++ MUX_VAL(CP(RMII_RXD1), (IEN | PTD | EN | M0)) /*rmii_rxd1*/\ ++ MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | EN | M0)) /*rmii_crs_dv*/\ ++ MUX_VAL(CP(RMII_RXER), (IEN | PTD | EN | M0)) /*rmii_rxer*/\ ++ MUX_VAL(CP(RMII_TXD0), (IEN | PTD | EN | M0)) /*rmii_txd0*/\ ++ MUX_VAL(CP(RMII_TXD1), (IEN | PTD | EN | M0)) /*rmii_txd1*/\ ++ MUX_VAL(CP(RMII_TXEN), (IEN | PTD | EN | M0)) /*rmii_txen*/\ ++ MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) /*rmii_50mhz_clk*/\ ++ MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) /*usb0_drvbus*/\ ++ MUX_VAL(CP(HECCL_TXD), (IEN | PTD | EN | M0)) /*heccl_txd*/\ ++ MUX_VAL(CP(HECCL_RXD), (IEN | PTD | EN | M0)) /*heccl_rxd*/\ ++ MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) /*sys_boot7*/\ ++ MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) /*sdrc_dqs0n*/\ ++ MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) /*sdrc_dqs1n*/\ ++ MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) /*sdrc_dqs2n*/\ ++ MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) /*sdrc_dqs3n*/\ ++ MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) /*sdrc_strben_dly0*/\ ++ MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) /*sdrc_strben_dly1*/\ ++ MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) /*sys_boot8*/\ ++ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ ++ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ ++ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ ++ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\ ++ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ ++ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ ++ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ ++ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ ++ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\ ++ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\ ++ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\ ++ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\ ++ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\ ++ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\ ++ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\ ++ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ ++ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ ++ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ ++ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ ++ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\ ++ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ ++ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\ ++ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\ ++ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\ ++ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ ++ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ ++ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ ++ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ ++ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\ ++ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\ ++ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ ++ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/\ ++ ++#endif +diff --git a/board/omap3/omap3517evm/u-boot.lds b/board/omap3/omap3517evm/u-boot.lds +new file mode 100644 +index 0000000..69d8ac9 +--- /dev/null ++++ b/board/omap3/omap3517evm/u-boot.lds +@@ -0,0 +1,63 @@ ++/* ++ * January 2004 - Changed to support H4 device ++ * Copyright (c) 2004 Texas Instruments ++ * ++ * (C) Copyright 2002 ++ * Gary Jennejohn, DENX Software Engineering, ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++OUTPUT_ARCH(arm) ++ENTRY(_start) ++SECTIONS ++{ ++ . = 0x00000000; ++ ++ . = ALIGN(4); ++ .text : ++ { ++ cpu/arm_cortexa8/start.o (.text) ++ *(.text) ++ } ++ ++ . = ALIGN(4); ++ .rodata : { *(.rodata) } ++ ++ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } ++ __exidx_start = .; ++ .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } ++ __exidx_end = .; ++ ++ . = ALIGN(4); ++ .data : { *(.data) } ++ ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss : { *(.bss) } ++ _end = .; ++} +diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c +index 7bb3e28..a0c2d05 100644 +--- a/cpu/arm_cortexa8/omap3/board.c ++++ b/cpu/arm_cortexa8/omap3/board.c +@@ -224,7 +224,11 @@ void s_init(void) + per_clocks_enable(); + + if (!in_sdram) ++#ifdef CONFIG_OMAP3_OMAP3517EVM ++ emif4_init(); ++#else + sdrc_init(); ++#endif + } + + /****************************************************************************** +@@ -284,8 +288,12 @@ int dram_init(void) + * memory on CS0. + */ + if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) { ++#ifdef CONFIG_OMAP3_OMAP3517EVM ++ emif4_init(); ++#else + do_sdrc_init(CS1, NOT_EARLY); + make_cs1_contiguous(); ++#endif + } + + size0 = get_sdr_cs_size(CS0); +diff --git a/cpu/arm_cortexa8/omap3/clock.c b/cpu/arm_cortexa8/omap3/clock.c +index 8ac31be..a706cd4 100644 +--- a/cpu/arm_cortexa8/omap3/clock.c ++++ b/cpu/arm_cortexa8/omap3/clock.c +@@ -352,6 +352,10 @@ void per_clocks_enable(void) + sr32(&prcm_base->fclken1_core, 13, 1, 0x1); + sr32(&prcm_base->iclken1_core, 13, 1, 0x1); + ++ /* Enable UART2 clocks */ ++ sr32(&prcm_base->fclken1_core, 14, 1, 0x1); ++ sr32(&prcm_base->iclken1_core, 14, 1, 0x1); ++ + /* UART 3 Clocks */ + sr32(&prcm_base->fclken_per, 11, 1, 0x1); + sr32(&prcm_base->iclken_per, 11, 1, 0x1); +diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c +index 3cc22c4..1badb34 100644 +--- a/cpu/arm_cortexa8/omap3/mem.c ++++ b/cpu/arm_cortexa8/omap3/mem.c +@@ -31,6 +31,53 @@ + #include + #include + ++/* Definitions for EMIF4 configuration values */ ++#define EMIF4_TIM1_T_RP 0x4 ++#define EMIF4_TIM1_T_RCD 0x4 ++#define EMIF4_TIM1_T_WR 0x2 ++#define EMIF4_TIM1_T_RAS 0x8 ++#define EMIF4_TIM1_T_RC 13 ++#define EMIF4_TIM1_T_RRD 0x2 ++#define EMIF4_TIM1_T_WTR 0x2 ++ ++#define EMIF4_TIM2_T_XP 0x2 ++#define EMIF4_TIM2_T_ODT 0x0 ++#define EMIF4_TIM2_T_XSNR 28 ++#define EMIF4_TIM2_T_XSRD 200 ++#define EMIF4_TIM2_T_RTP 0x2 ++#define EMIF4_TIM2_T_CKE 0x3 ++ ++#define EMIF4_TIM3_T_TDQSCKMAX 0x0 ++#define EMIF4_TIM3_T_RFC 33 ++#define EMIF4_TIM3_T_RAS_MAX 0x7 ++ ++#define EMIF4_PWR_IDLE 0x2 ++#define EMIF4_PWR_DPD_EN 0x0 ++#define EMIF4_PWR_PM_EN 0x0 ++#define EMIF4_PWR_PM_TIM 0x0 ++ ++#define EMIF4_INITREF_DIS 0x0 ++#define EMIF4_PASR 0x0 ++#define EMIF4_REFRESH_RATE 1295 ++ ++#define EMIF4_CFG_SDRAM_TYP 0x2 ++#define EMIF4_CFG_IBANK_POS 0x0 ++#define EMIF4_CFG_DDR_TERM 0x0 ++#define EMIF4_CFG_DDR2_DDQS 0x1 ++#define EMIF4_CFG_DYN_ODT 0x0 ++#define EMIF4_CFG_DDR_DIS_DLL 0x0 ++#define EMIF4_CFG_SDR_DRV 0x0 ++#define EMIF4_CFG_CWL 0x0 ++#define EMIF4_CFG_NARROW_MD 0x0 ++#define EMIF4_CFG_CL 0x3 ++#define EMIF4_CFG_ROWSIZE 0x3 ++#define EMIF4_CFG_IBANK 0x3 ++#define EMIF4_CFG_EBANK 0x0 ++#define EMIF4_CFG_PGSIZE 0x2 ++ ++#define EMIF4_DDR1_READ_LAT 0x3 ++#define EMIF4_DDR1_VTP_DYN 0x1 ++ + /* + * Only One NAND allowed on board at a time. + * The GPMC CS Base for the same +@@ -83,6 +130,7 @@ gpmc_csx_t *onenand_cs_base; + #endif + + static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE; ++static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE; + + /************************************************************************** + * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow +@@ -195,6 +243,68 @@ void do_sdrc_init(u32 cs, u32 early) + writel(0, &sdrc_base->cs[cs].mcfg); + } + ++/******************************************************** ++ * emif4 _init() - init the emif4 module for DDR access ++ * - early init routines, called from flash or ++ * SRAM. ++ *******************************************************/ ++void emif4_init(void) ++{ ++ unsigned int regval; ++ /* Set the DDR PHY parameters in PHY ctrl registers */ ++ regval = (EMIF4_DDR1_READ_LAT | (EMIF4_DDR1_VTP_DYN << 15)); ++ writel(regval, &emif4_base->ddr_phyctrl1); ++ writel(regval, &emif4_base->ddr_phyctrl1_shdw); ++ writel(0, &emif4_base->ddr_phyctrl2); ++ ++ /* Reset the DDR PHY and wait till completed */ ++ regval = readl(&emif4_base->sdram_iodft_tlgc); ++ regval |= (1<<10); ++ writel(regval, &emif4_base->sdram_iodft_tlgc); ++ while ((readl(&emif4_base->sdram_sts) & (1<<10)) == 0x0); ++ ++ /* Set SDR timing registers */ ++ regval = (EMIF4_TIM1_T_WTR | (EMIF4_TIM1_T_RRD << 3) | ++ (EMIF4_TIM1_T_RC << 6) | (EMIF4_TIM1_T_RAS << 12) | ++ (EMIF4_TIM1_T_WR << 17) | (EMIF4_TIM1_T_RCD << 21) | ++ (EMIF4_TIM1_T_RP << 25)); ++ writel(regval, &emif4_base->sdram_time1); ++ writel(regval, &emif4_base->sdram_time1_shdw); ++ ++ regval = (EMIF4_TIM2_T_CKE | (EMIF4_TIM2_T_RTP << 3) | ++ (EMIF4_TIM2_T_XSRD << 6) | (EMIF4_TIM2_T_XSNR << 16) | ++ (EMIF4_TIM2_T_ODT << 25) | (EMIF4_TIM2_T_XP << 28)); ++ writel(regval, &emif4_base->sdram_time2); ++ writel(regval, &emif4_base->sdram_time2_shdw); ++ ++ regval = (EMIF4_TIM3_T_RAS_MAX | (EMIF4_TIM3_T_RFC << 4) | ++ (EMIF4_TIM3_T_TDQSCKMAX << 13)); ++ writel(regval, &emif4_base->sdram_time3); ++ writel(regval, &emif4_base->sdram_time3_shdw); ++ ++ /* Set the PWR control register */ ++ regval = (EMIF4_PWR_PM_TIM | (EMIF4_PWR_PM_EN << 8) | ++ (EMIF4_PWR_DPD_EN << 10) | (EMIF4_PWR_IDLE << 30)); ++ writel(regval, &emif4_base->sdram_pwr_mgmt); ++ writel(regval, &emif4_base->sdram_pwr_mgmt_shdw); ++ ++ /* Set the DDR refresh rate control register */ ++ regval = (EMIF4_REFRESH_RATE | (EMIF4_PASR << 24) | ++ (EMIF4_INITREF_DIS << 31)); ++ writel(regval, &emif4_base->sdram_refresh_ctrl); ++ writel(regval, &emif4_base->sdram_refresh_ctrl_shdw); ++ ++ /* set the SDRAM configuration register */ ++ regval = (EMIF4_CFG_PGSIZE | (EMIF4_CFG_EBANK << 3) | ++ (EMIF4_CFG_IBANK << 4) | (EMIF4_CFG_ROWSIZE << 7) | ++ (EMIF4_CFG_CL << 10) | (EMIF4_CFG_NARROW_MD << 14) | ++ (EMIF4_CFG_CWL << 16) | (EMIF4_CFG_SDR_DRV << 18) | ++ (EMIF4_CFG_DDR_DIS_DLL << 20) | (EMIF4_CFG_DYN_ODT << 21) | ++ (EMIF4_CFG_DDR2_DDQS << 23) | (EMIF4_CFG_DDR_TERM << 24) | ++ (EMIF4_CFG_IBANK_POS << 27) | (EMIF4_CFG_SDRAM_TYP << 29)); ++ writel(regval, &emif4_base->sdram_config); ++} ++ + void enable_gpmc_config(u32 *gpmc_config, gpmc_csx_t *gpmc_cs_base, u32 base, + u32 size) + { +diff --git a/drivers/net/Makefile b/drivers/net/Makefile +index a360a50..3d803f4 100644 +--- a/drivers/net/Makefile ++++ b/drivers/net/Makefile +@@ -70,6 +70,7 @@ COBJS-$(CONFIG_ULI526X) += uli526x.o + COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o + COBJS-$(CONFIG_XILINX_EMAC) += xilinx_emac.o + COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o ++COBJS-$(CONFIG_TICPGMAC) += ticpgmac.o + + COBJS := $(COBJS-y) + SRCS := $(COBJS:.o=.c) +diff --git a/drivers/net/ticpgmac.c b/drivers/net/ticpgmac.c +new file mode 100644 +index 0000000..e83b951 +--- /dev/null ++++ b/drivers/net/ticpgmac.c +@@ -0,0 +1,693 @@ ++/* ++ * Ethernet driver for OMAP3 OMAP3517EVM chip. ++ * ++ * Copyright (C) 2007 Sergey Kubushyn ++ * ++ * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright ++ * follows: ++ * ++ * ---------------------------------------------------------------------------- ++ * Derived from - ++ * dm644x_emac.c ++ * ++ * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM ++ * ++ * Copyright (C) 2005 Texas Instruments. ++ * ++ * ---------------------------------------------------------------------------- ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This prog